From 097aac9f47c7c2021bc28489f24de509d1d80f33 Mon Sep 17 00:00:00 2001
From: sjthales <sebastien.jacq@thalesgroup.com>
Date: Tue, 13 Oct 2020 09:48:22 +0200
Subject: [PATCH] updating readme

---
 README.md | 17 +++++++++++++++--
 1 file changed, 15 insertions(+), 2 deletions(-)

diff --git a/README.md b/README.md
index 02fb8534..16b68141 100644
--- a/README.md
+++ b/README.md
@@ -9,7 +9,7 @@ Checkout the repository and initialize all submodules:
 $ git --recursive clone https://github.com/ThalesGroup/cva6-softcore-contest.git
 ```
 
-> As of Nov. 12<sup>th</sup>, 2020, we are working hard to solve an alleged performance regression of CVA6 vs. an older versions. You'll be updated when it's solved.
+> As of October 12th, 2020, we are working hard to solve an alleged performance regression of CVA6 vs. an older versions. You'll be updated when it's solved.
 
  CoreMark application has been customized for the contest, for using CoreMark application, run:
 
@@ -41,7 +41,7 @@ When the installation is achieved, do not forget to add $RISCV/bin to your PATH.
 
 ## Questa tool
 Questa Prime **version 10.7** has been used for simulations.
-Other simuluation tools and versions can be used but will receive no support from the organization team.
+Other simulation tools and versions can be used but will receive no support from the organization team.
 
 ## Vitis/Vivado setting up
 This section will be completed in a next release (planned early December 2020).
@@ -55,6 +55,8 @@ This files ease the creation of new projects with automated configuration of sev
 All guidelines to install **vitis 2020.1** and **Zybo Z7-20** board files are explained to the following link:
 https://reference.digilentinc.com/reference/programmable-logic/guides/installation
 
+**be careful about your linux distribution and the supported version of Vitis 2020.1 environment**
+
 If you have not yet done so, start provisioning the following:
 
 | Reference	                 | URL                                                                             |	List price |	Remark                            |
@@ -93,6 +95,17 @@ Moreover, all `printf` used in software application will be displayed into the *
 
 > Simulation may take lot of time, so you need to be patient to have results.
 
+Simulation is programmed to run 10000000 cycles but the result is displayed before the end of simulation.
+
+For Dhrystone application, at the end of the simulation, Dhrystone result is diplayed as following:
+```
+Dhrystones per Second: 
+```
+and for coremark application, result at the end of simulation is displayed as following:
+```
+
+```
+
 CVA6 software environment is detailed into `sw/app` directory.
 
 # Synthesis and place and route get started
-- 
GitLab