diff --git a/.gitignore b/.gitignore index b79d207fa2cfbbe3859862d467e8f68e5afce692..421d7473e2f0dbc8a2e7e5b15155ae6eaeb0c73f 100644 --- a/.gitignore +++ b/.gitignore @@ -1,2 +1,3 @@ bench/build/ +bench/sic.patch diff --git a/bench/Makefile b/bench/Makefile index 102e60960efa6845ac3ad495b791532ee4b87241..50cdb7d58a49b54aa912272e93cb3d3a202fb601 100755 --- a/bench/Makefile +++ b/bench/Makefile @@ -57,29 +57,41 @@ kernels = \ isqrt \ jfdctint \ lms \ + ludcmp \ matrix1 \ md5 \ minver \ + pm \ prime \ + quicksort \ rad2deg \ recursion \ + sha \ st sequentials = \ adpcm_dec \ - adpcm_enc \ - cjpeg_transupp \ - cjpeg_wrbmp \ - dijkstra \ - fmref \ - g723_enc \ - gsm_dec \ - h264_dec \ - huff_dec \ - huff_enc \ - ndes \ - petrinet \ - statemate + adpcm_enc \ + ammunition \ + anagram \ + audiobeam \ + cjpeg_transupp \ + cjpeg_wrbmp \ + dijkstra \ + epic \ + fmref \ + g723_enc \ + gsm_dec \ + gsm_enc \ + h264_dec \ + huff_dec \ + huff_enc \ + ndes \ + petrinet \ + rijndael_dec \ + rijndael_enc \ + statemate \ + susan bmarks = $(addprefix kernel/,$(kernels)) $(addprefix sequential/,$(sequentials)) @@ -96,22 +108,24 @@ RISCV_OBJDUMP ?= $(RISCV_PREFIX)objdump SRC_BSP_C = $(wildcard $(bsp_dir)/hal/*.c) $(wildcard $(bsp_dir)/drivers/uart/*.c) SRC_BSP_S = $(wildcard $(bsp_dir)/hal/*.S) +COCCI_SRC_FILES = $(shell find kernel/ sequential/ -type f -name "*.c") + OBJ_BSP_C = $(addprefix build/,$(SRC_BSP_C:.c=.o)) OBJ_BSP_S = $(addprefix build/,$(SRC_BSP_S:.S=.o)) OBJ_BSP = $(OBJ_BSP_S) $(OBJ_BSP_C) BSP_INCS = -Ibsp/config -Ibsp/drivers/uart -Ibsp/hal -INCS = $(BSP_INCS) +INCS = $(BSP_INCS) -Isic FLAGS_STR := "$(RISCV_CFLAGS) $(RISCV_LDFLAGS) " -CFLAGS ?= -DPREALLOCATE=1 -fvisibility=hidden -DSTDIO_THRU_UART -O3 -mcmodel=medany -static -Wall -pedantic +CFLAGS ?= -DPREALLOCATE=1 -fvisibility=hidden -DSTDIO_THRU_UART -Os -mcmodel=medany -static -Wall -pedantic RISCV_CFLAGS := -DPERFORMANCE_RUN=1 \ -DITERATIONS=3 \ -DFLAGS_STR=\"$(FLAGS_STR)\" \ -Wno-unknown-pragmas \ - -DPREALLOCATE=1 -fvisibility=hidden -DSTDIO_THRU_UART -O3 -mcmodel=medany -static -Wall -pedantic + -DPREALLOCATE=1 -fvisibility=hidden -DSTDIO_THRU_UART -Os -mcmodel=medany -static -Wall -pedantic RISCV_LDFLAGS = -Lbuild/ -lcva6 -static -nostartfiles -T bsp/config/link.ld @@ -130,7 +144,7 @@ $(1): build/artifacts/$(1).D $(1): build/artifacts/$(1).hex $(1): build/artifacts/$(1).bin $(1): build/mem/$(1).mem -build/artifacts/$(1).riscv: build/libcva6.a build/dtor.o $$($(1)_OBJ_FILES) +build/artifacts/$(1).riscv: build/libcva6.a $$($(1)_OBJ_FILES) $$(DIR_GUARD) @echo " LD $$@" @$$(RISCV_GCC) $$(RISCV_CFLAGS) -o $$@ $$^ $$(RISCV_LDFLAGS) @@ -153,10 +167,10 @@ build/artifacts/%.bin: build/artifacts/%.riscv @echo " OBJCOPY $< -> $@" @$(RISCV_OBJCOPY) -O binary $< $@ -build/libcva6.a: $(OBJ_BSP) +build/libcva6.a: $(OBJ_BSP) build/sic/siccsrs.o $(DIR_GUARD) @echo " AR $< -> $@" - @$(RISCV_AR) rcs build/libcva6.a $(OBJ_BSP) + @$(RISCV_AR) rcs build/libcva6.a $^ build/%.o: %.c $(DIR_GUARD) @@ -173,8 +187,12 @@ build/mem/%.mem: build/artifacts/%.bin @echo " BIN2MEM $< -> $@" @$(utils_dir)/bin2mem.py $< $@ +sic.patch: sic.cocci + @echo " SPATCH $<" + @spatch --sp-file $< $(COCCI_SRC_FILES) --patch . >$@ + clean: @echo " RM build/" - @rm -rf build/ + @rm -rf build/ sic.patch .PHONY: all clean diff --git a/bench/dtor.c b/bench/dtor.c deleted file mode 100644 index b5c74168cd7a07a3c7d1154c59683bdcaec2cd48..0000000000000000000000000000000000000000 --- a/bench/dtor.c +++ /dev/null @@ -1,20 +0,0 @@ -#include <stdint.h> -#include <stdio.h> -#include <stdlib.h> - -#define READCSR(_t, counter) \ - asm volatile("csrr %0, " # counter : "=r" (_t)) - -static void __attribute__((destructor)) dtor(void) { - uint32_t brpending, mempending, lsu, imiss; - - READCSR(brpending, 0xB11); - READCSR(mempending, 0xB12); - READCSR(lsu, 0xB13); - READCSR(imiss, 0xB14); - - printf("==== dtor ====\n" - "brpending: %ld; mempending: %ld; lsu: %ld; imiss: %ld\n" - "==== end of dtor ====\n", - brpending, mempending, lsu, imiss); -} diff --git a/bench/sic.cocci b/bench/sic.cocci new file mode 100644 index 0000000000000000000000000000000000000000..3991c3daa1fa9524f9726be080ade633725ad6bc --- /dev/null +++ b/bench/sic.cocci @@ -0,0 +1,13 @@ +@@ +@@ + ++ #include <siccsrs.h> + +int main(void) +{ +... + ++ siccsrs(); + + return ...; +} diff --git a/bench/sic/siccsrs.c b/bench/sic/siccsrs.c new file mode 100644 index 0000000000000000000000000000000000000000..c19b131a54a127c20b3ba0696059813e91bc7f95 --- /dev/null +++ b/bench/sic/siccsrs.c @@ -0,0 +1,31 @@ +#include <stdint.h> +#include <stdio.h> +#include <stdlib.h> + +#include "siccsrs.h" + +#define READCSR(_t, counter) \ + asm volatile ("csrr %0, " # counter : "=r" (_t)) + +static inline void print_uint(const char *msg, uint32_t val) { + char buffer[sizeof(uint32_t) * 8 + 1] = {0}; + + utoa(val, buffer, 10); + fputs(msg, stdout); + fputs(buffer, stdout); +} + +void siccsrs(void) { + uint32_t brpending, mempending, lsu, imiss; + + READCSR(brpending, 0xB11); + READCSR(mempending, 0xB12); + READCSR(lsu, 0xB13); + READCSR(imiss, 0xB14); + + print_uint("brpending: ", brpending); + print_uint("; mempending: ", mempending); + print_uint("; lsu: ", lsu); + print_uint("; imiss: ", imiss); + puts(""); +} diff --git a/bench/sic/siccsrs.h b/bench/sic/siccsrs.h new file mode 100644 index 0000000000000000000000000000000000000000..8a704b78d7b3ec9646d05ef1d8975bc64e7a9584 --- /dev/null +++ b/bench/sic/siccsrs.h @@ -0,0 +1,6 @@ +#ifndef __SICCSRS_H_ +#define __SICCSRS_H_ + +void siccsrs(void); + +#endif /* __SICCSRS_H_ */