diff --git a/fpga/openocd_digilent_hs2.cfg b/fpga/openocd_digilent_hs2.cfg index 7387551c2c489dbbd8fad755bcfb1345a6f6c0aa..d5effd32843fe0b0e38378a696fac973c509a8b8 100644 --- a/fpga/openocd_digilent_hs2.cfg +++ b/fpga/openocd_digilent_hs2.cfg @@ -1,28 +1,33 @@ +# SPDX-License-Identifier: GPL-2.0-or-later +# this supports JTAG-HS2 (and apparently Nexys4 as well) -# Digilent JTAG-HS2 +# ADBUS5 controls TMS tri-state buffer enable +# ACBUS6=SEL_TMS controls mux to TMS output buffer: 0=TMS 1=TDI +# ACBUS5=SEL_TDO controls mux to TDO input: 0=TDO 1=TMS +adapter driver ftdi +# ftdi device_desc "Digilent USB Device" +ftdi vid_pid 0x0403 0x6014 -interface ftdi -ftdi_device_desc "Digilent USB Device" -ftdi_vid_pid 0x0403 0x6014 -##ftdi_serial 210249A85F9B -ftdi_channel 0 -ftdi_layout_init 0x00e8 0x60eb +ftdi channel 0 +ftdi layout_init 0x00e8 0x60eb +ftdi layout_signal SWD_EN -data 0x6000 +ftdi layout_signal SWDIO_OE -data 0x20 reset_config none - adapter_khz 1000 - -# TAP declaration -set _CHIPNAME riscv + transport select jtag + + set _CHIPNAME riscv jtag newtap $_CHIPNAME cpu -irlen 5 -expected-id 0x249511C3 set _TARGETNAME $_CHIPNAME.cpu target create $_TARGETNAME riscv -chain-position $_TARGETNAME -coreid 0 +# jtag newtap auto0 tap -irlen 5 -expected-id 0x249511c3 gdb_report_data_abort enable gdb_report_register_access_error enable @@ -30,7 +35,7 @@ riscv set_reset_timeout_sec 120 riscv set_command_timeout_sec 120 # prefer to use sba for system bus access -riscv set_prefer_sba on +# riscv set_prefer_sba on # dump jtag chain scan_chain diff --git a/fpga/scripts/run_cva6_fpga.tcl b/fpga/scripts/run_cva6_fpga.tcl index 9a52a7e25b7d620822e64142cfc1677fdc4fa1c1..e7983dc7f98a3bc96876879bbd8b5ecfbf3a6eb0 100644 --- a/fpga/scripts/run_cva6_fpga.tcl +++ b/fpga/scripts/run_cva6_fpga.tcl @@ -29,6 +29,8 @@ # =========================================================================== # set project cva6_fpga +set_param board.repoPaths [list $env(HOME)/.Xilinx/Vivado/2024.1/xhub/board_store/xilinx_board_store $env(PATH_VIVADO)/Vivado/2024.1/data/xhub/boards] + create_project $project . -force -part $::env(XILINX_PART) set_property board_part $::env(XILINX_BOARD) [current_project] @@ -43,13 +45,13 @@ set_msg_config -id {[Synth 8-4480]} -limit 1000 add_files -fileset constrs_1 -norecurse constraints/zybo_z7_20.xdc -read_ip xilinx/xlnx_processing_system7/ip/xlnx_processing_system7.xci -read_ip xilinx/xlnx_blk_mem_gen/ip/xlnx_blk_mem_gen.xci -read_ip xilinx/xlnx_axi_clock_converter/ip/xlnx_axi_clock_converter.xci -read_ip xilinx/xlnx_axi_dwidth_converter_dm_slave/ip/xlnx_axi_dwidth_converter_dm_slave.xci -read_ip xilinx/xlnx_axi_dwidth_converter_dm_master/ip/xlnx_axi_dwidth_converter_dm_master.xci +read_ip xilinx/xlnx_processing_system7/xlnx_processing_system7.srcs/sources_1/ip/xlnx_processing_system7/xlnx_processing_system7.xci +read_ip xilinx/xlnx_blk_mem_gen/xlnx_blk_mem_gen.srcs/sources_1/ip/xlnx_blk_mem_gen/xlnx_blk_mem_gen.xci +read_ip xilinx/xlnx_axi_clock_converter/xlnx_axi_clock_converter.srcs/sources_1/ip/xlnx_axi_clock_converter/xlnx_axi_clock_converter.xci +read_ip xilinx/xlnx_axi_dwidth_converter_dm_slave/xlnx_axi_dwidth_converter_dm_slave.srcs/sources_1/ip/xlnx_axi_dwidth_converter_dm_slave/xlnx_axi_dwidth_converter_dm_slave.xci +read_ip xilinx/xlnx_axi_dwidth_converter_dm_master/xlnx_axi_dwidth_converter_dm_master.srcs/sources_1/ip/xlnx_axi_dwidth_converter_dm_master/xlnx_axi_dwidth_converter_dm_master.xci -read_ip xilinx/xlnx_clk_gen/ip/xlnx_clk_gen.xci +read_ip xilinx/xlnx_clk_gen/xlnx_clk_gen.srcs/sources_1/ip/xlnx_clk_gen/xlnx_clk_gen.xci set_property include_dirs { "src/axi_sd_bridge/include" "../src/common_cells/include" } [current_fileset] diff --git a/fpga/scripts/run_cva6_ooc.tcl b/fpga/scripts/run_cva6_ooc.tcl index 3cc83757461a129d92050c936419d0569511220e..6c4d79bef16b6379b13c463735a012167730af9f 100644 --- a/fpga/scripts/run_cva6_ooc.tcl +++ b/fpga/scripts/run_cva6_ooc.tcl @@ -29,6 +29,8 @@ # =========================================================================== # set project cva6_ooc +set_param board.repoPaths [list $env(HOME)/.Xilinx/Vivado/2024.1/xhub/board_store/xilinx_board_store $env(PATH_VIVADO)/Vivado/2024.1/data/xhub/boards] + create_project $project . -force -part $::env(XILINX_PART) set_property board_part $::env(XILINX_BOARD) [current_project] diff --git a/fpga/xilinx/xlnx_axi_clock_converter/tcl/run.tcl b/fpga/xilinx/xlnx_axi_clock_converter/tcl/run.tcl index ba0551e7f361e1005d2588464133b688a27b7c7f..e539cf41ddcb983b085245738a11e73388e62535 100644 --- a/fpga/xilinx/xlnx_axi_clock_converter/tcl/run.tcl +++ b/fpga/xilinx/xlnx_axi_clock_converter/tcl/run.tcl @@ -3,6 +3,8 @@ set boardName $::env(XILINX_BOARD) set ipName xlnx_axi_clock_converter +set_param board.repoPaths [list $env(HOME)/.Xilinx/Vivado/2024.1/xhub/board_store/xilinx_board_store $env(PATH_VIVADO)/Vivado/2024.1/data/xhub/boards] + create_project $ipName . -force -part $partNumber set_property board_part $boardName [current_project] @@ -14,4 +16,4 @@ generate_target {instantiation_template} [get_files ./$ipName.srcs/sources_1/ip/ generate_target all [get_files ./$ipName.srcs/sources_1/ip/$ipName/$ipName.xci] create_ip_run [get_files -of_objects [get_fileset sources_1] ./$ipName.srcs/sources_1/ip/$ipName/$ipName.xci] launch_run -jobs 8 ${ipName}_synth_1 -wait_on_run ${ipName}_synth_1 \ No newline at end of file +wait_on_run ${ipName}_synth_1 diff --git a/fpga/xilinx/xlnx_axi_dwidth_converter_dm_master/tcl/run.tcl b/fpga/xilinx/xlnx_axi_dwidth_converter_dm_master/tcl/run.tcl index ae2095f04a0a2f173028f056954e2d30c3363fac..a6ef71286c6744a9db0e6cebabf8fc4131c328b6 100644 --- a/fpga/xilinx/xlnx_axi_dwidth_converter_dm_master/tcl/run.tcl +++ b/fpga/xilinx/xlnx_axi_dwidth_converter_dm_master/tcl/run.tcl @@ -3,6 +3,8 @@ set boardName $::env(XILINX_BOARD) set ipName xlnx_axi_dwidth_converter_dm_master +set_param board.repoPaths [list $env(HOME)/.Xilinx/Vivado/2024.1/xhub/board_store/xilinx_board_store $env(PATH_VIVADO)/Vivado/2024.1/data/xhub/boards] + create_project $ipName . -force -part $partNumber set_property board_part $boardName [current_project] diff --git a/fpga/xilinx/xlnx_axi_dwidth_converter_dm_slave/tcl/run.tcl b/fpga/xilinx/xlnx_axi_dwidth_converter_dm_slave/tcl/run.tcl index e6dab6376672a87ef93fe95391d88bb4d2e7926e..e80d8e7f4e2adf83c522b2d654e7e3b4124297bd 100644 --- a/fpga/xilinx/xlnx_axi_dwidth_converter_dm_slave/tcl/run.tcl +++ b/fpga/xilinx/xlnx_axi_dwidth_converter_dm_slave/tcl/run.tcl @@ -3,6 +3,8 @@ set boardName $::env(XILINX_BOARD) set ipName xlnx_axi_dwidth_converter_dm_slave +set_param board.repoPaths [list $env(HOME)/.Xilinx/Vivado/2024.1/xhub/board_store/xilinx_board_store $env(PATH_VIVADO)/Vivado/2024.1/data/xhub/boards] + create_project $ipName . -force -part $partNumber set_property board_part $boardName [current_project] diff --git a/fpga/xilinx/xlnx_blk_mem_gen/tcl/run.tcl b/fpga/xilinx/xlnx_blk_mem_gen/tcl/run.tcl index 6324a5063dd2da019821b1be15ea30c8a249ae64..5cd3a26385ed25e430a8ff37c330f846894a0766 100644 --- a/fpga/xilinx/xlnx_blk_mem_gen/tcl/run.tcl +++ b/fpga/xilinx/xlnx_blk_mem_gen/tcl/run.tcl @@ -3,6 +3,8 @@ set boardName $::env(XILINX_BOARD) set ipName xlnx_blk_mem_gen +set_param board.repoPaths [list $env(HOME)/.Xilinx/Vivado/2024.1/xhub/board_store/xilinx_board_store $env(PATH_VIVADO)/Vivado/2024.1/data/xhub/boards] + create_project $ipName . -force -part $partNumber set_property board_part $boardName [current_project] diff --git a/fpga/xilinx/xlnx_clk_gen/tcl/run.tcl b/fpga/xilinx/xlnx_clk_gen/tcl/run.tcl index 26a329e61a19afe56ff651e9783fe2a07c4a48fc..6bfc065e01489a28db5a40444c2918041ed5ac7a 100644 --- a/fpga/xilinx/xlnx_clk_gen/tcl/run.tcl +++ b/fpga/xilinx/xlnx_clk_gen/tcl/run.tcl @@ -3,6 +3,8 @@ set boardName $::env(XILINX_BOARD) set ipName xlnx_clk_gen +set_param board.repoPaths [list $env(HOME)/.Xilinx/Vivado/2024.1/xhub/board_store/xilinx_board_store $env(PATH_VIVADO)/Vivado/2024.1/data/xhub/boards] + create_project $ipName . -force -part $partNumber set_property board_part $boardName [current_project] diff --git a/fpga/xilinx/xlnx_processing_system7/tcl/run.tcl b/fpga/xilinx/xlnx_processing_system7/tcl/run.tcl index c58edef06908d61ba91986e7a6633ce60f7dc7c9..24ac2d9c40b38706c48a956d24b79f46a21694c6 100644 --- a/fpga/xilinx/xlnx_processing_system7/tcl/run.tcl +++ b/fpga/xilinx/xlnx_processing_system7/tcl/run.tcl @@ -3,6 +3,8 @@ set boardName $::env(XILINX_BOARD) set ipName xlnx_processing_system7 +set_param board.repoPaths [list $env(HOME)/.Xilinx/Vivado/2024.1/xhub/board_store/xilinx_board_store $env(PATH_VIVADO)/Vivado/2024.1/data/xhub/boards] + create_project $ipName . -force -part $partNumber set_property board_part $boardName [current_project]