From 19a17b524c8170793262681f6af68f13b118d8c1 Mon Sep 17 00:00:00 2001
From: Thomas Carle <tcarle@xptraces.irit.fr>
Date: Mon, 14 Oct 2024 14:07:55 +0200
Subject: [PATCH] First commit for Printemps
---
fpga/openocd_digilent_hs2.cfg | 29 +++++++++++--------
fpga/scripts/run_cva6_fpga.tcl | 14 +++++----
fpga/scripts/run_cva6_ooc.tcl | 2 ++
.../xlnx_axi_clock_converter/tcl/run.tcl | 4 ++-
.../tcl/run.tcl | 2 ++
.../tcl/run.tcl | 2 ++
fpga/xilinx/xlnx_blk_mem_gen/tcl/run.tcl | 2 ++
fpga/xilinx/xlnx_clk_gen/tcl/run.tcl | 2 ++
.../xlnx_processing_system7/tcl/run.tcl | 2 ++
9 files changed, 40 insertions(+), 19 deletions(-)
diff --git a/fpga/openocd_digilent_hs2.cfg b/fpga/openocd_digilent_hs2.cfg
index 7387551c..d5effd32 100644
--- a/fpga/openocd_digilent_hs2.cfg
+++ b/fpga/openocd_digilent_hs2.cfg
@@ -1,28 +1,33 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+# this supports JTAG-HS2 (and apparently Nexys4 as well)
-# Digilent JTAG-HS2
+# ADBUS5 controls TMS tri-state buffer enable
+# ACBUS6=SEL_TMS controls mux to TMS output buffer: 0=TMS 1=TDI
+# ACBUS5=SEL_TDO controls mux to TDO input: 0=TDO 1=TMS
+adapter driver ftdi
+# ftdi device_desc "Digilent USB Device"
+ftdi vid_pid 0x0403 0x6014
-interface ftdi
-ftdi_device_desc "Digilent USB Device"
-ftdi_vid_pid 0x0403 0x6014
-##ftdi_serial 210249A85F9B
-ftdi_channel 0
-ftdi_layout_init 0x00e8 0x60eb
+ftdi channel 0
+ftdi layout_init 0x00e8 0x60eb
+ftdi layout_signal SWD_EN -data 0x6000
+ftdi layout_signal SWDIO_OE -data 0x20
reset_config none
-
adapter_khz 1000
-
-# TAP declaration
-set _CHIPNAME riscv
+ transport select jtag
+
+ set _CHIPNAME riscv
jtag newtap $_CHIPNAME cpu -irlen 5 -expected-id 0x249511C3
set _TARGETNAME $_CHIPNAME.cpu
target create $_TARGETNAME riscv -chain-position $_TARGETNAME -coreid 0
+# jtag newtap auto0 tap -irlen 5 -expected-id 0x249511c3
gdb_report_data_abort enable
gdb_report_register_access_error enable
@@ -30,7 +35,7 @@ riscv set_reset_timeout_sec 120
riscv set_command_timeout_sec 120
# prefer to use sba for system bus access
-riscv set_prefer_sba on
+# riscv set_prefer_sba on
# dump jtag chain
scan_chain
diff --git a/fpga/scripts/run_cva6_fpga.tcl b/fpga/scripts/run_cva6_fpga.tcl
index 9a52a7e2..e7983dc7 100644
--- a/fpga/scripts/run_cva6_fpga.tcl
+++ b/fpga/scripts/run_cva6_fpga.tcl
@@ -29,6 +29,8 @@
# =========================================================================== #
set project cva6_fpga
+set_param board.repoPaths [list $env(HOME)/.Xilinx/Vivado/2024.1/xhub/board_store/xilinx_board_store $env(PATH_VIVADO)/Vivado/2024.1/data/xhub/boards]
+
create_project $project . -force -part $::env(XILINX_PART)
set_property board_part $::env(XILINX_BOARD) [current_project]
@@ -43,13 +45,13 @@ set_msg_config -id {[Synth 8-4480]} -limit 1000
add_files -fileset constrs_1 -norecurse constraints/zybo_z7_20.xdc
-read_ip xilinx/xlnx_processing_system7/ip/xlnx_processing_system7.xci
-read_ip xilinx/xlnx_blk_mem_gen/ip/xlnx_blk_mem_gen.xci
-read_ip xilinx/xlnx_axi_clock_converter/ip/xlnx_axi_clock_converter.xci
-read_ip xilinx/xlnx_axi_dwidth_converter_dm_slave/ip/xlnx_axi_dwidth_converter_dm_slave.xci
-read_ip xilinx/xlnx_axi_dwidth_converter_dm_master/ip/xlnx_axi_dwidth_converter_dm_master.xci
+read_ip xilinx/xlnx_processing_system7/xlnx_processing_system7.srcs/sources_1/ip/xlnx_processing_system7/xlnx_processing_system7.xci
+read_ip xilinx/xlnx_blk_mem_gen/xlnx_blk_mem_gen.srcs/sources_1/ip/xlnx_blk_mem_gen/xlnx_blk_mem_gen.xci
+read_ip xilinx/xlnx_axi_clock_converter/xlnx_axi_clock_converter.srcs/sources_1/ip/xlnx_axi_clock_converter/xlnx_axi_clock_converter.xci
+read_ip xilinx/xlnx_axi_dwidth_converter_dm_slave/xlnx_axi_dwidth_converter_dm_slave.srcs/sources_1/ip/xlnx_axi_dwidth_converter_dm_slave/xlnx_axi_dwidth_converter_dm_slave.xci
+read_ip xilinx/xlnx_axi_dwidth_converter_dm_master/xlnx_axi_dwidth_converter_dm_master.srcs/sources_1/ip/xlnx_axi_dwidth_converter_dm_master/xlnx_axi_dwidth_converter_dm_master.xci
-read_ip xilinx/xlnx_clk_gen/ip/xlnx_clk_gen.xci
+read_ip xilinx/xlnx_clk_gen/xlnx_clk_gen.srcs/sources_1/ip/xlnx_clk_gen/xlnx_clk_gen.xci
set_property include_dirs { "src/axi_sd_bridge/include" "../src/common_cells/include" } [current_fileset]
diff --git a/fpga/scripts/run_cva6_ooc.tcl b/fpga/scripts/run_cva6_ooc.tcl
index 3cc83757..6c4d79be 100644
--- a/fpga/scripts/run_cva6_ooc.tcl
+++ b/fpga/scripts/run_cva6_ooc.tcl
@@ -29,6 +29,8 @@
# =========================================================================== #
set project cva6_ooc
+set_param board.repoPaths [list $env(HOME)/.Xilinx/Vivado/2024.1/xhub/board_store/xilinx_board_store $env(PATH_VIVADO)/Vivado/2024.1/data/xhub/boards]
+
create_project $project . -force -part $::env(XILINX_PART)
set_property board_part $::env(XILINX_BOARD) [current_project]
diff --git a/fpga/xilinx/xlnx_axi_clock_converter/tcl/run.tcl b/fpga/xilinx/xlnx_axi_clock_converter/tcl/run.tcl
index ba0551e7..e539cf41 100644
--- a/fpga/xilinx/xlnx_axi_clock_converter/tcl/run.tcl
+++ b/fpga/xilinx/xlnx_axi_clock_converter/tcl/run.tcl
@@ -3,6 +3,8 @@ set boardName $::env(XILINX_BOARD)
set ipName xlnx_axi_clock_converter
+set_param board.repoPaths [list $env(HOME)/.Xilinx/Vivado/2024.1/xhub/board_store/xilinx_board_store $env(PATH_VIVADO)/Vivado/2024.1/data/xhub/boards]
+
create_project $ipName . -force -part $partNumber
set_property board_part $boardName [current_project]
@@ -14,4 +16,4 @@ generate_target {instantiation_template} [get_files ./$ipName.srcs/sources_1/ip/
generate_target all [get_files ./$ipName.srcs/sources_1/ip/$ipName/$ipName.xci]
create_ip_run [get_files -of_objects [get_fileset sources_1] ./$ipName.srcs/sources_1/ip/$ipName/$ipName.xci]
launch_run -jobs 8 ${ipName}_synth_1
-wait_on_run ${ipName}_synth_1
\ No newline at end of file
+wait_on_run ${ipName}_synth_1
diff --git a/fpga/xilinx/xlnx_axi_dwidth_converter_dm_master/tcl/run.tcl b/fpga/xilinx/xlnx_axi_dwidth_converter_dm_master/tcl/run.tcl
index ae2095f0..a6ef7128 100644
--- a/fpga/xilinx/xlnx_axi_dwidth_converter_dm_master/tcl/run.tcl
+++ b/fpga/xilinx/xlnx_axi_dwidth_converter_dm_master/tcl/run.tcl
@@ -3,6 +3,8 @@ set boardName $::env(XILINX_BOARD)
set ipName xlnx_axi_dwidth_converter_dm_master
+set_param board.repoPaths [list $env(HOME)/.Xilinx/Vivado/2024.1/xhub/board_store/xilinx_board_store $env(PATH_VIVADO)/Vivado/2024.1/data/xhub/boards]
+
create_project $ipName . -force -part $partNumber
set_property board_part $boardName [current_project]
diff --git a/fpga/xilinx/xlnx_axi_dwidth_converter_dm_slave/tcl/run.tcl b/fpga/xilinx/xlnx_axi_dwidth_converter_dm_slave/tcl/run.tcl
index e6dab637..e80d8e7f 100644
--- a/fpga/xilinx/xlnx_axi_dwidth_converter_dm_slave/tcl/run.tcl
+++ b/fpga/xilinx/xlnx_axi_dwidth_converter_dm_slave/tcl/run.tcl
@@ -3,6 +3,8 @@ set boardName $::env(XILINX_BOARD)
set ipName xlnx_axi_dwidth_converter_dm_slave
+set_param board.repoPaths [list $env(HOME)/.Xilinx/Vivado/2024.1/xhub/board_store/xilinx_board_store $env(PATH_VIVADO)/Vivado/2024.1/data/xhub/boards]
+
create_project $ipName . -force -part $partNumber
set_property board_part $boardName [current_project]
diff --git a/fpga/xilinx/xlnx_blk_mem_gen/tcl/run.tcl b/fpga/xilinx/xlnx_blk_mem_gen/tcl/run.tcl
index 6324a506..5cd3a263 100644
--- a/fpga/xilinx/xlnx_blk_mem_gen/tcl/run.tcl
+++ b/fpga/xilinx/xlnx_blk_mem_gen/tcl/run.tcl
@@ -3,6 +3,8 @@ set boardName $::env(XILINX_BOARD)
set ipName xlnx_blk_mem_gen
+set_param board.repoPaths [list $env(HOME)/.Xilinx/Vivado/2024.1/xhub/board_store/xilinx_board_store $env(PATH_VIVADO)/Vivado/2024.1/data/xhub/boards]
+
create_project $ipName . -force -part $partNumber
set_property board_part $boardName [current_project]
diff --git a/fpga/xilinx/xlnx_clk_gen/tcl/run.tcl b/fpga/xilinx/xlnx_clk_gen/tcl/run.tcl
index 26a329e6..6bfc065e 100644
--- a/fpga/xilinx/xlnx_clk_gen/tcl/run.tcl
+++ b/fpga/xilinx/xlnx_clk_gen/tcl/run.tcl
@@ -3,6 +3,8 @@ set boardName $::env(XILINX_BOARD)
set ipName xlnx_clk_gen
+set_param board.repoPaths [list $env(HOME)/.Xilinx/Vivado/2024.1/xhub/board_store/xilinx_board_store $env(PATH_VIVADO)/Vivado/2024.1/data/xhub/boards]
+
create_project $ipName . -force -part $partNumber
set_property board_part $boardName [current_project]
diff --git a/fpga/xilinx/xlnx_processing_system7/tcl/run.tcl b/fpga/xilinx/xlnx_processing_system7/tcl/run.tcl
index c58edef0..24ac2d9c 100644
--- a/fpga/xilinx/xlnx_processing_system7/tcl/run.tcl
+++ b/fpga/xilinx/xlnx_processing_system7/tcl/run.tcl
@@ -3,6 +3,8 @@ set boardName $::env(XILINX_BOARD)
set ipName xlnx_processing_system7
+set_param board.repoPaths [list $env(HOME)/.Xilinx/Vivado/2024.1/xhub/board_store/xilinx_board_store $env(PATH_VIVADO)/Vivado/2024.1/data/xhub/boards]
+
create_project $ipName . -force -part $partNumber
set_property board_part $boardName [current_project]
--
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