From 2247eb0c18bd13c4eca99e049280ad2750d5601b Mon Sep 17 00:00:00 2001
From: Alban Gruin <alban.gruin@irit.fr>
Date: Sun, 8 May 2022 16:17:46 +0200
Subject: [PATCH] Revert "verifier: lock I$ on D$ writes"
This reverts commit 38d335fcd7688bcedb8d86a171352c5bcfd5d2dc.
---
src/ariane.sv | 8 +-------
src/ex_stage.sv | 2 --
src/load_store_unit.sv | 5 ++---
src/verifier.sv | 5 +----
4 files changed, 4 insertions(+), 16 deletions(-)
diff --git a/src/ariane.sv b/src/ariane.sv
index 01bc663a..69c045bc 100644
--- a/src/ariane.sv
+++ b/src/ariane.sv
@@ -103,8 +103,6 @@ module ariane import ariane_pkg::*; #(
logic has_mem_access_is_verif;
logic has_ctrl_flow_is_icache;
- logic store_buffer_empty_verif;
-
// --------------
// ISSUE <-> EX
// --------------
@@ -447,7 +445,6 @@ module ariane import ariane_pkg::*; #(
.lsu_commit_ready_o ( lsu_commit_ready_ex_commit ), // to commit
.commit_tran_id_i ( lsu_commit_trans_id ), // from commit
.no_st_pending_o ( no_st_pending_ex ),
- .store_buffer_empty_o ( store_buffer_empty_verif ),
// FPU
.fpu_ready_o ( fpu_ready_ex_id ),
.fpu_valid_i ( fpu_valid_id_ex ),
@@ -667,9 +664,6 @@ module ariane import ariane_pkg::*; #(
// I$
.icache_miss_i (icache_miss_cache_perf),
- // D$
- .dcache_wbuffer_empty_i (dcache_commit_wbuffer_empty),
-
// IF
.if_has_mem_access_i (has_mem_access_if_verif),
.if_has_cf_i (has_ctrl_flow_if_icache),
@@ -683,7 +677,7 @@ module ariane import ariane_pkg::*; #(
.is_has_cf_i (has_ctrl_flow_is_icache),
// LSU
- .no_st_pending_commit_i (store_buffer_empty_verif),
+ .no_st_pending_commit_i (no_st_pending_ex),
// CO
.commit_instr_i (commit_instr_id_commit),
diff --git a/src/ex_stage.sv b/src/ex_stage.sv
index c035ad8d..402bbb33 100644
--- a/src/ex_stage.sv
+++ b/src/ex_stage.sv
@@ -71,7 +71,6 @@ module ex_stage import ariane_pkg::*; #(
output logic lsu_commit_ready_o, // commit queue is ready to accept another commit request
input logic [TRANS_ID_BITS-1:0] commit_tran_id_i,
output logic no_st_pending_o,
- output logic store_buffer_empty_o,
input logic amo_valid_commit_i,
// FPU
output logic fpu_ready_o, // FU is ready
@@ -278,7 +277,6 @@ module ex_stage import ariane_pkg::*; #(
.rst_ni,
.flush_i,
.no_st_pending_o,
- .store_buffer_empty_o,
.fu_data_i ( lsu_data ),
.lsu_ready_o,
.lsu_valid_i,
diff --git a/src/load_store_unit.sv b/src/load_store_unit.sv
index 18791202..fe2a6859 100644
--- a/src/load_store_unit.sv
+++ b/src/load_store_unit.sv
@@ -21,7 +21,6 @@ module load_store_unit import ariane_pkg::*; #(
input logic rst_ni,
input logic flush_i,
output logic no_st_pending_o,
- output logic store_buffer_empty_o,
input logic amo_valid_commit_i,
input fu_data_t fu_data_i,
@@ -197,9 +196,9 @@ module load_store_unit import ariane_pkg::*; #(
end
endgenerate
- logic store_buffer_empty;
- assign store_buffer_empty_o = store_buffer_empty;
+
+ logic store_buffer_empty;
// ------------------
// Store Unit
// ------------------
diff --git a/src/verifier.sv b/src/verifier.sv
index 8618d1ff..ebe7f803 100644
--- a/src/verifier.sv
+++ b/src/verifier.sv
@@ -9,9 +9,6 @@ module verifier #(
// I$
input logic icache_miss_i,
- // D$
- input logic dcache_wbuffer_empty_i,
-
// Frontend
input logic if_has_mem_access_i,
input logic if_has_cf_i,
@@ -38,7 +35,7 @@ module verifier #(
// Bus accesses (I$ misses and memory instructions in the pipeline)
logic has_mem_access;
- assign has_mem_access = if_has_mem_access_i | id_has_mem_access_i | is_has_mem_access_i | ~no_st_pending_commit_i | ~dcache_wbuffer_empty_i;
+ assign has_mem_access = if_has_mem_access_i | id_has_mem_access_i | is_has_mem_access_i | (~no_st_pending_commit_i);
// assign should_lock_icache_o = has_mem_access & icache_miss_i;
assign should_lock_icache_o = has_mem_access | if_has_cf_i | id_has_cf_i | is_has_cf_i;
--
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