From 3368298049098c9950fad22285d7b5f560e363c7 Mon Sep 17 00:00:00 2001
From: Alban Gruin <alban.gruin@irit.fr>
Date: Tue, 6 Apr 2021 23:37:28 +0200
Subject: [PATCH] wt_icache: lock requests
Signed-off-by: Alban Gruin <alban.gruin@irit.fr>
---
src/cache_subsystem/wt_icache.sv | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/src/cache_subsystem/wt_icache.sv b/src/cache_subsystem/wt_icache.sv
index 0b3cd9db..60b4afc9 100644
--- a/src/cache_subsystem/wt_icache.sv
+++ b/src/cache_subsystem/wt_icache.sv
@@ -197,7 +197,7 @@ end else begin : gen_piton_offset
// wait for incoming requests
end else begin
// mem requests are for sure invals here
- if (!mem_rtrn_vld_i) begin
+ if (!mem_rtrn_vld_i && !stall_req_i) begin
dreq_o.ready = 1'b1;
// we have a new request
if (dreq_i.req) begin
@@ -250,7 +250,7 @@ end else begin : gen_piton_offset
// we have a miss / NC transaction
end else if (dreq_i.kill_s2) begin
state_d = IDLE;
- end else begin
+ end else if (!stall_req_i) begin
cmp_en_d = 1'b0;
// only count this as a miss if the cache is enabled, and
// the address is cacheable
--
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