From 398de2ea32ea2a71e8b92292db6a83c13ec2ce60 Mon Sep 17 00:00:00 2001
From: Florian Zaruba <zarubaf@iis.ee.ethz.ch>
Date: Mon, 5 Nov 2018 01:34:18 +0100
Subject: [PATCH] Small SoC modifications
---
.editorconfig | 4 ++--
fpga/src/ariane_peripherals.sv | 6 +++---
fpga/src/bootrom/ariane.dts | 6 +++---
src/decoder.sv | 2 +-
src/mmu.sv | 19 +++++++++++++++++++
5 files changed, 28 insertions(+), 9 deletions(-)
diff --git a/.editorconfig b/.editorconfig
index 25d42946..f36e411b 100644
--- a/.editorconfig
+++ b/.editorconfig
@@ -6,8 +6,8 @@ root = true
end_of_line = lf
insert_final_newline = true
trim_trailing_whitespace = true
-max_line_length = off
+max_line_length = 100
# 4 space indentation
[*.{sv, svh, v, vhd}]
indent_style = space
-indent_size = 4
+indent_size = 2
diff --git a/fpga/src/ariane_peripherals.sv b/fpga/src/ariane_peripherals.sv
index 68d87def..f36a9508 100644
--- a/fpga/src/ariane_peripherals.sv
+++ b/fpga/src/ariane_peripherals.sv
@@ -74,10 +74,10 @@ module ariane_peripherals #(
.clk_i ( clk_i ),
.rst_ni ( rst_ni ),
.irq_sources_i ( irq_sources ),
- .eip_targets_o ( irq_o ),
+ .eip_targets_o ( ),
.external_bus_io ( reg_bus )
);
-
+ assign irq_o = '0;
// ---------------
// UART
// ---------------
@@ -432,4 +432,4 @@ module ariane_peripherals #(
assign s_axi_spi_rlast = 1'b1;
assign s_axi_spi_rvalid = 1'b1;
end
-endmodule
\ No newline at end of file
+endmodule
diff --git a/fpga/src/bootrom/ariane.dts b/fpga/src/bootrom/ariane.dts
index 606c9a84..e64aa79c 100644
--- a/fpga/src/bootrom/ariane.dts
+++ b/fpga/src/bootrom/ariane.dts
@@ -5,9 +5,9 @@
#size-cells = <2>;
compatible = "eth,ariane-bare-dev";
model = "eth,ariane-bare";
- chosen {
- stdout-path = "/soc/uart@10000000:115200";
- };
+ // chosen {
+ // stdout-path = "/soc/uart@10000000:115200";
+ // };
cpus {
#address-cells = <1>;
#size-cells = <0>;
diff --git a/src/decoder.sv b/src/decoder.sv
index efb31c5a..f02fe9c2 100644
--- a/src/decoder.sv
+++ b/src/decoder.sv
@@ -108,7 +108,7 @@ module decoder (
if (priv_lvl_i == riscv::PRIV_LVL_S && tsr_i) begin
illegal_instr = 1'b1;
// do not change privilege level if this is an illegal instruction
- instruction_o.op = ADD;
+ instruction_o.op = ADD;
end
end
// MRET
diff --git a/src/mmu.sv b/src/mmu.sv
index ada0e861..8a982cc0 100644
--- a/src/mmu.sv
+++ b/src/mmu.sv
@@ -156,6 +156,25 @@ module mmu #(
.*
);
+ ila_1 i_ila_1 (
+ .clk(clk_i), // input wire clk
+ .probe0({req_port_o.address_tag, req_port_o.address_index}),
+ .probe1(req_port_o.data_req), // input wire [63:0] probe1
+ .probe2(req_port_i.data_gnt), // input wire [0:0] probe2
+ .probe3(req_port_i.data_rdata), // input wire [0:0] probe3
+ .probe4(req_port_i.data_rvalid), // input wire [0:0] probe4
+ .probe5(ptw_error), // input wire [1:0] probe5
+ .probe6(update_vaddr), // input wire [0:0] probe6
+ .probe7(update_ptw_itlb.valid), // input wire [0:0] probe7
+ .probe8(update_ptw_dtlb.valid), // input wire [0:0] probe8
+ .probe9(dtlb_lu_access), // input wire [0:0] probe9
+ .probe10(lsu_vaddr_i), // input wire [0:0] probe10
+ .probe11(dtlb_lu_hit), // input wire [0:0] probe11
+ .probe12(itlb_lu_access), // input wire [0:0] probe12
+ .probe13(icache_areq_i.fetch_vaddr), // input wire [0:0] probe13
+ .probe14(itlb_lu_hit) // input wire [0:0] probe13
+ );
+
//-----------------------
// Instruction Interface
//-----------------------
--
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