From 4a62b8c2baa39af041b2fcd74e22f0c9808f1bf8 Mon Sep 17 00:00:00 2001
From: Jonathan Richard Robert Kimmitt <jrrk2@cl.cam.ac.uk>
Date: Tue, 29 Jan 2019 08:51:23 +0000
Subject: [PATCH] Update Makefile with path to ethernet submodule Verilog files

---
 Makefile                 | 2 +-
 fpga/src/ariane-ethernet | 2 +-
 2 files changed, 2 insertions(+), 2 deletions(-)

diff --git a/Makefile b/Makefile
index 157ed542..cf1afed1 100644
--- a/Makefile
+++ b/Makefile
@@ -142,7 +142,7 @@ src := $(addprefix $(root-dir), $(src))
 uart_src := $(wildcard fpga/src/apb_uart/src/*.vhd)
 uart_src := $(addprefix $(root-dir), $(uart_src))
 
-fpga_src :=  $(wildcard fpga/src/*.sv) $(wildcard fpga/src/bootrom/*.sv)
+fpga_src :=  $(wildcard fpga/src/*.sv) $(wildcard fpga/src/bootrom/*.sv) $(wildcard fpga/src/ariane-ethernet/*.sv)
 fpga_src := $(addprefix $(root-dir), $(fpga_src))
 
 # look for testbenches
diff --git a/fpga/src/ariane-ethernet b/fpga/src/ariane-ethernet
index c8fd8943..4ea1127e 160000
--- a/fpga/src/ariane-ethernet
+++ b/fpga/src/ariane-ethernet
@@ -1 +1 @@
-Subproject commit c8fd89437d250b59ead30c233cf2a279be1c48c7
+Subproject commit 4ea1127e5d2d0b5d3bd281542066b4a4e4d2fe50
-- 
GitLab