diff --git a/Makefile b/Makefile index bf3e6a62c7a556817788542f6881d2f6b40fe9d0..da25bebc610bb11394aac3111a7297ea34bc3fc9 100644 --- a/Makefile +++ b/Makefile @@ -288,7 +288,7 @@ cva6_ooc: $(ariane_pkg) $(util) $(src) $(fpga_src) @echo read_verilog -sv {$(fpga_src)} >> fpga/scripts/add_sources.tcl cd fpga && make cva6_ooc BOARD=$(BOARD) XILINX_PART=$(XILINX_PART) XILINX_BOARD=$(XILINX_BOARD) CLK_PERIOD_NS=$(CLK_PERIOD_NS) BATCH_MODE=$(BATCH_MODE) -.PHONY: cva6_ooc cva6_fpga program_cva6_fpga get_hs2_id +.PHONY: cva6_ooc cva6_fpga program_cva6_fpga get_hs2_sn cva6_fpga: $(ariane_pkg) $(util) $(src) $(fpga_src) $(uart_src) @echo "[FPGA] Generate sources"