From 4b0b5c0822fa57de96639965cd73b9d6f8422507 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?s=C3=A9bastien=20jacq?=
<57099003+sjthales@users.noreply.github.com>
Date: Tue, 8 Dec 2020 14:08:11 +0100
Subject: [PATCH] Update Makefile
---
Makefile | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/Makefile b/Makefile
index bf3e6a62..da25bebc 100644
--- a/Makefile
+++ b/Makefile
@@ -288,7 +288,7 @@ cva6_ooc: $(ariane_pkg) $(util) $(src) $(fpga_src)
@echo read_verilog -sv {$(fpga_src)} >> fpga/scripts/add_sources.tcl
cd fpga && make cva6_ooc BOARD=$(BOARD) XILINX_PART=$(XILINX_PART) XILINX_BOARD=$(XILINX_BOARD) CLK_PERIOD_NS=$(CLK_PERIOD_NS) BATCH_MODE=$(BATCH_MODE)
-.PHONY: cva6_ooc cva6_fpga program_cva6_fpga get_hs2_id
+.PHONY: cva6_ooc cva6_fpga program_cva6_fpga get_hs2_sn
cva6_fpga: $(ariane_pkg) $(util) $(src) $(fpga_src) $(uart_src)
@echo "[FPGA] Generate sources"
--
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