diff --git a/src/ariane.sv b/src/ariane.sv
index 5ea04ec5f7d4bdb3ad3e4c35e48f4409a47a78f5..cfd985050ed06ac63603e2a6167e5155b1e0cb15 100644
--- a/src/ariane.sv
+++ b/src/ariane.sv
@@ -655,12 +655,15 @@ module ariane import ariane_pkg::*; #(
 
     // IF
     .if_has_mem_access_i (has_mem_access_if_verif),
+    .if_has_cf_i         (has_ctrl_flow_if_icache),
 
     // ID
     .id_has_mem_access_i (has_mem_access_id_verif),
+    .id_has_cf_i         (has_ctrl_flow_id_icache),
 
     // IS
     .is_has_mem_access_i (has_mem_access_is_verif),
+    .is_has_cf_i         (has_ctrl_flow_is_icache),
 
     // LSU
     .no_st_pending_commit_i (no_st_pending_ex),
diff --git a/src/verifier.sv b/src/verifier.sv
index 3d5346bb22a3d23d981b0f2006d1f4312c33ed88..4c2485548af4b00452c75afc371e0400e3331471 100644
--- a/src/verifier.sv
+++ b/src/verifier.sv
@@ -11,12 +11,15 @@ module verifier #(
 
   // Frontend
   input logic                       if_has_mem_access_i,
+  input logic                       if_has_cf_i,
 
   // ID
   input logic                       id_has_mem_access_i,
+  input logic                       id_has_cf_i,
 
   // IS
   input logic                       is_has_mem_access_i,
+  input logic                       is_has_cf_i,
 
   // LSU
   input logic                       no_st_pending_commit_i,
@@ -33,8 +36,9 @@ module verifier #(
   // Bus accesses (I$ misses and memory instructions in the pipeline)
   logic                             has_mem_access;
   assign has_mem_access = if_has_mem_access_i | id_has_mem_access_i | is_has_mem_access_i | (~no_st_pending_commit_i);
+
   // assign should_lock_icache_o = has_mem_access & icache_miss_i;
-  assign should_lock_icache_o = has_mem_access;
+  assign should_lock_icache_o = has_mem_access | if_has_cf_i | id_has_cf_i | is_has_cf_i;
 
   // CO
   logic [NR_COMMIT_PORTS-1:0][BITS_ENTRIES-1:0]          commit_id_n, commit_id_q;