From 60d42274cc6f336894f8cc79f53eb5b65bada001 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?s=C3=A9bastien=20jacq?= <57099003+sjthales@users.noreply.github.com> Date: Mon, 7 Dec 2020 13:35:24 +0100 Subject: [PATCH] Update README.md --- README.md | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/README.md b/README.md index 832b1e96..6b2bf998 100644 --- a/README.md +++ b/README.md @@ -234,7 +234,7 @@ Below is described steps to run Coremark application on CV32A6 FPGA platform, st 1. First, make sure the digilent **JTAG-HS2 debug adapter** is properly connected to the **PMOD JE** connector and that the USBUART adapter is properly connected to the **PMOD JB** connector of the Zybo Z7-20 board.  -2. Compile coremark application in `sw/app` +2. Compile Coremark application in `sw/app`. Commands to compile Coremark application are described in `sw/app` directory. 3. Generate the bitstream of the FPGA platform: ``` $ make cva6_fpga -- GitLab