From 65c783086948e3d19d9418ed90af8813745a7be2 Mon Sep 17 00:00:00 2001 From: Alban Gruin <alban.gruin@univ-tlse3.fr> Date: Wed, 31 Mar 2021 15:54:13 +0200 Subject: [PATCH] Add a destructor to dump some CSRs at the end of a bench Signed-off-by: Alban Gruin <alban.gruin@univ-tlse3.fr> --- bench/Makefile | 2 +- bench/dtor.c | 20 ++++++++++++++++++++ 2 files changed, 21 insertions(+), 1 deletion(-) create mode 100644 bench/dtor.c diff --git a/bench/Makefile b/bench/Makefile index e4087895..102e6096 100755 --- a/bench/Makefile +++ b/bench/Makefile @@ -130,7 +130,7 @@ $(1): build/artifacts/$(1).D $(1): build/artifacts/$(1).hex $(1): build/artifacts/$(1).bin $(1): build/mem/$(1).mem -build/artifacts/$(1).riscv: build/libcva6.a $$($(1)_OBJ_FILES) +build/artifacts/$(1).riscv: build/libcva6.a build/dtor.o $$($(1)_OBJ_FILES) $$(DIR_GUARD) @echo " LD $$@" @$$(RISCV_GCC) $$(RISCV_CFLAGS) -o $$@ $$^ $$(RISCV_LDFLAGS) diff --git a/bench/dtor.c b/bench/dtor.c new file mode 100644 index 00000000..b5c74168 --- /dev/null +++ b/bench/dtor.c @@ -0,0 +1,20 @@ +#include <stdint.h> +#include <stdio.h> +#include <stdlib.h> + +#define READCSR(_t, counter) \ + asm volatile("csrr %0, " # counter : "=r" (_t)) + +static void __attribute__((destructor)) dtor(void) { + uint32_t brpending, mempending, lsu, imiss; + + READCSR(brpending, 0xB11); + READCSR(mempending, 0xB12); + READCSR(lsu, 0xB13); + READCSR(imiss, 0xB14); + + printf("==== dtor ====\n" + "brpending: %ld; mempending: %ld; lsu: %ld; imiss: %ld\n" + "==== end of dtor ====\n", + brpending, mempending, lsu, imiss); +} -- GitLab