diff --git a/Makefile b/Makefile
index dc105cc1717f9fbfab739f7077aa0d172fd05a35..9693a5fc6a61d81a8221e51056ee4065054bdf11 100644
--- a/Makefile
+++ b/Makefile
@@ -52,6 +52,10 @@ else ifeq ($(BOARD), kc705)
XILINX_PART := xc7k325tffg900-2
XILINX_BOARD := xilinx.com:kc705:part0:1.5
CLK_PERIOD_NS := 20
+else ifeq ($(BOARD), vc707)
+ XILINX_PART := xc7vx485tffg1761-2
+ XILINX_BOARD := xilinx.com:vc707:part0:1.3
+ CLK_PERIOD_NS := 20
else
$(error Unknown board - please specify a supported FPGA board)
endif
diff --git a/fpga/constraints/vc707.xdc b/fpga/constraints/vc707.xdc
new file mode 100644
index 0000000000000000000000000000000000000000..959a6819c6ed35ba8725a8a295be38f9d1f2380c
--- /dev/null
+++ b/fpga/constraints/vc707.xdc
@@ -0,0 +1,127 @@
+## Buttons
+set_property -dict {PACKAGE_PIN AV40 IOSTANDARD LVCMOS18} [get_ports cpu_reset]
+
+## To use FTDI FT2232 JTAG
+set_property -dict { PACKAGE_PIN AV39 IOSTANDARD LVCMOS18 } [get_ports trst];
+set_property -dict { PACKAGE_PIN M32 IOSTANDARD LVCMOS18 } [get_ports tck ];
+set_property -dict { PACKAGE_PIN V29 IOSTANDARD LVCMOS18 } [get_ports tdi ];
+set_property -dict { PACKAGE_PIN M28 IOSTANDARD LVCMOS18 } [get_ports tdo ];
+set_property -dict { PACKAGE_PIN U31 IOSTANDARD LVCMOS18 } [get_ports tms ];
+
+## UART
+set_property -dict {PACKAGE_PIN AU36 IOSTANDARD LVCMOS18} [get_ports tx]
+set_property -dict {PACKAGE_PIN AU33 IOSTANDARD LVCMOS18} [get_ports rx]
+
+
+## LEDs
+set_property -dict {PACKAGE_PIN AM39 IOSTANDARD LVCMOS18} [get_ports {led[0]}]
+set_property -dict {PACKAGE_PIN AN39 IOSTANDARD LVCMOS18} [get_ports {led[1]}]
+set_property -dict {PACKAGE_PIN AR37 IOSTANDARD LVCMOS18} [get_ports {led[2]}]
+set_property -dict {PACKAGE_PIN AT37 IOSTANDARD LVCMOS18} [get_ports {led[3]}]
+set_property -dict {PACKAGE_PIN AR35 IOSTANDARD LVCMOS18} [get_ports {led[4]}]
+set_property -dict {PACKAGE_PIN AP41 IOSTANDARD LVCMOS18} [get_ports {led[5]}]
+set_property -dict {PACKAGE_PIN AP42 IOSTANDARD LVCMOS18} [get_ports {led[6]}]
+set_property -dict {PACKAGE_PIN AU39 IOSTANDARD LVCMOS18} [get_ports {led[7]}]
+
+## Switches
+set_property -dict {PACKAGE_PIN AV30 IOSTANDARD LVCMOS18} [get_ports {sw[0]}]
+set_property -dict {PACKAGE_PIN AY33 IOSTANDARD LVCMOS18} [get_ports {sw[1]}]
+set_property -dict {PACKAGE_PIN BA31 IOSTANDARD LVCMOS18} [get_ports {sw[2]}]
+set_property -dict {PACKAGE_PIN BA32 IOSTANDARD LVCMOS18} [get_ports {sw[3]}]
+set_property -dict {PACKAGE_PIN AW30 IOSTANDARD LVCMOS18} [get_ports {sw[4]}]
+set_property -dict {PACKAGE_PIN AY30 IOSTANDARD LVCMOS18} [get_ports {sw[5]}]
+set_property -dict {PACKAGE_PIN BA30 IOSTANDARD LVCMOS18} [get_ports {sw[6]}]
+set_property -dict {PACKAGE_PIN BB31 IOSTANDARD LVCMOS18} [get_ports {sw[7]}]
+
+## Fan Control
+set_property -dict {PACKAGE_PIN BA37 IOSTANDARD LVCMOS18} [get_ports fan_pwm]
+#set_property -dict { PACKAGE_PIN V21 IOSTANDARD LVCMOS18 } [get_ports { FAN_TACH }]; #IO_L22P_T3_A05_D21_14 Sch=fan_tac
+
+## Ethernet
+set_property -dict {PACKAGE_PIN N26 IOSTANDARD LVCMOS18} [get_ports eth_rst_n]; #IO_L14N_T2_SRCC_12 Sch=eth_phyrst_n
+set_property -dict {PACKAGE_PIN N25 IOSTANDARD LVCMOS18} [get_ports eth_txck]; #IO_L14P_T2_SRCC_33 Sch=eth_tx_clk
+set_property -dict {PACKAGE_PIN P23 IOSTANDARD LVCMOS18} [get_ports eth_txctl]; #IO_L20P_T3_33 Sch=eth_tx_en
+set_property -dict {PACKAGE_PIN M26 IOSTANDARD LVCMOS18} [get_ports { eth_txd[0] }]; #IO_L22N_T3_33 Sch=eth_tx_d[0]
+set_property -dict {PACKAGE_PIN L27 IOSTANDARD LVCMOS18} [get_ports { eth_txd[1] }]; #IO_L17P_T2_33 Sch=eth_tx_d[1]
+set_property -dict {PACKAGE_PIN M27 IOSTANDARD LVCMOS18} [get_ports { eth_txd[2] }]; #IO_L18N_T2_33 Sch=eth_tx_d[2]
+set_property -dict {PACKAGE_PIN N24 IOSTANDARD LVCMOS18} [get_ports { eth_txd[3] }]; #IO_L17N_T2_33 Sch=eth_tx_d[3]
+set_property -dict {PACKAGE_PIN M21 IOSTANDARD LVCMOS18} [get_ports { eth_rxd[0] }]; #IO_L21N_T3_DQS_33 Sch=eth_rx_d[0]
+set_property -dict {PACKAGE_PIN M24 IOSTANDARD LVCMOS18} [get_ports eth_rxck]; #IO_L13P_T2_MRCC_33 Sch=eth_rx_clk
+set_property -dict {PACKAGE_PIN L25 IOSTANDARD LVCMOS18} [get_ports eth_rxctl]; #IO_L18P_T2_33 Sch=eth_rx_ctl
+set_property -dict {PACKAGE_PIN J22 IOSTANDARD LVCMOS18} [get_ports { eth_rxd[1] }]; #IO_L21P_T3_DQS_33 Sch=eth_rx_d[1]
+set_property -dict {PACKAGE_PIN K22 IOSTANDARD LVCMOS18} [get_ports { eth_rxd[2] }]; #IO_L20N_T3_33 Sch=eth_rx_d[2]
+set_property -dict {PACKAGE_PIN L26 IOSTANDARD LVCMOS18} [get_ports { eth_rxd[3] }]; #IO_L22P_T3_33 Sch=eth_rx_d[3]
+set_property -dict {PACKAGE_PIN N23 IOSTANDARD LVCMOS18} [get_ports eth_mdc ]; #IO_L23P_T3_33 Sch=eth_mdc
+set_property -dict {PACKAGE_PIN L21 IOSTANDARD LVCMOS18} [get_ports eth_mdio]; #IO_L23N_T3_33 Sch=eth_mdio
+
+# set_property -dict {PACKAGE_PIN AK15 IOSTANDARD LVCMOS18} [get_ports { eth_pme_b }]; #IO_L1N_T0_32 Sch=eth_pmeb
+# set_property -dict {PACKAGE_PIN AK16 IOSTANDARD LVCMOS18} [get_ports { eth_int_b }]; #IO_L1P_T0_32 Sch=eth_intb
+
+#############################################
+# Ethernet Constraints for 1Gb/s
+#############################################
+# Modified for 125MHz receive clock
+create_clock -period 8.000 -name eth_rxck [get_ports eth_rxck]
+
+set_clock_groups -asynchronous -group [get_clocks eth_rxck -include_generated_clocks]
+set_clock_groups -asynchronous -group [get_clocks clk_out2_xlnx_clk_gen]
+
+#############################################
+## SD Card
+#############################################
+set_property -dict {PACKAGE_PIN AN30 IOSTANDARD LVCMOS18} [get_ports spi_clk_o]
+set_property -dict {PACKAGE_PIN AT30 IOSTANDARD LVCMOS18} [get_ports spi_ss]
+set_property -dict {PACKAGE_PIN AR30 IOSTANDARD LVCMOS18} [get_ports spi_miso]
+set_property -dict {PACKAGE_PIN AP30 IOSTANDARD LVCMOS18} [get_ports spi_mosi]
+# set_property -dict { PACKAGE_PIN P28 IOSTANDARD LVCMOS18 } [get_ports { sd_cd }]; #IO_L8N_T1_D12_14 Sch=sd_cd
+# set_property -dict { PACKAGE_PIN R29 IOSTANDARD LVCMOS18 } [get_ports { sd_cmd }]; #IO_L7N_T1_D10_14 Sch=sd_cmd
+# set_property -dict { PACKAGE_PIN R26 IOSTANDARD LVCMOS18 } [get_ports { sd_dat[0] }]; #IO_L10N_T1_D15_14 Sch=sd_dat[0]
+# set_property -dict { PACKAGE_PIN R30 IOSTANDARD LVCMOS18 } [get_ports { sd_dat[1] }]; #IO_L9P_T1_DQS_14 Sch=sd_dat[1]
+# set_property -dict { PACKAGE_PIN P29 IOSTANDARD LVCMOS18 } [get_ports { sd_dat[2] }]; #IO_L7P_T1_D09_14 Sch=sd_dat[2]
+# set_property -dict { PACKAGE_PIN T30 IOSTANDARD LVCMOS18 } [get_ports { sd_dat[3] }]; #IO_L9N_T1_DQS_D13_14 Sch=sd_dat[3]
+# set_property -dict { PACKAGE_PIN AE24 IOSTANDARD LVCMOS18 } [get_ports { sd_reset }]; #IO_L12N_T1_MRCC_12 Sch=sd_reset
+# set_property -dict { PACKAGE_PIN R28 IOSTANDARD LVCMOS18 } [get_ports { sd_clk }]; #IO_L11P_T1_SRCC_14 Sch=sd_sclk
+
+# create_generated_clock -name sd_fast_clk -source [get_pins clk_mmcm/sd_sys_clk] -divide_by 2 [get_pins chipset_impl/piton_sd_top/sdc_controller/clock_divider0/fast_clk_reg/Q]
+# create_generated_clock -name sd_slow_clk -source [get_pins clk_mmcm/sd_sys_clk] -divide_by 200 [get_pins chipset_impl/piton_sd_top/sdc_controller/clock_divider0/slow_clk_reg/Q]
+# create_generated_clock -name sd_clk_out -source [get_pins sd_clk_oddr/C] -divide_by 1 -add -master_clock sd_fast_clk [get_ports sd_clk_out]
+# create_generated_clock -name sd_clk_out_1 -source [get_pins sd_clk_oddr/C] -divide_by 1 -add -master_clock sd_slow_clk [get_ports sd_clk_out]
+
+# create_clock -period 40.000 -name VIRTUAL_sd_fast_clk -waveform {0.000 20.000}
+# create_clock -period 4000.000 -name VIRTUAL_sd_slow_clk -waveform {0.000 2000.000}
+
+# set_output_delay -clock [get_clocks sd_clk_out] -min -add_delay 5.000 [get_ports {sd_dat[*]}]
+# set_output_delay -clock [get_clocks sd_clk_out] -max -add_delay 15.000 [get_ports {sd_dat[*]}]
+# set_output_delay -clock [get_clocks sd_clk_out_1] -min -add_delay 5.000 [get_ports {sd_dat[*]}]
+# set_output_delay -clock [get_clocks sd_clk_out_1] -max -add_delay 1500.000 [get_ports {sd_dat[*]}]
+# set_output_delay -clock [get_clocks sd_clk_out] -min -add_delay 5.000 [get_ports sd_cmd]
+# set_output_delay -clock [get_clocks sd_clk_out] -max -add_delay 15.000 [get_ports sd_cmd]
+# set_output_delay -clock [get_clocks sd_clk_out_1] -min -add_delay 5.000 [get_ports sd_cmd]
+# set_output_delay -clock [get_clocks sd_clk_out_1] -max -add_delay 1500.000 [get_ports sd_cmd]
+# set_input_delay -clock [get_clocks VIRTUAL_sd_fast_clk] -min -add_delay 20.000 [get_ports {sd_dat[*]}]
+# set_input_delay -clock [get_clocks VIRTUAL_sd_fast_clk] -max -add_delay 35.000 [get_ports {sd_dat[*]}]
+# set_input_delay -clock [get_clocks VIRTUAL_sd_slow_clk] -min -add_delay 2000.000 [get_ports {sd_dat[*]}]
+# set_input_delay -clock [get_clocks VIRTUAL_sd_slow_clk] -max -add_delay 3500.000 [get_ports {sd_dat[*]}]
+# set_input_delay -clock [get_clocks VIRTUAL_sd_fast_clk] -min -add_delay 20.000 [get_ports sd_cmd]
+# set_input_delay -clock [get_clocks VIRTUAL_sd_fast_clk] -max -add_delay 35.000 [get_ports sd_cmd]
+# set_input_delay -clock [get_clocks VIRTUAL_sd_slow_clk] -min -add_delay 2000.000 [get_ports sd_cmd]
+# set_input_delay -clock [get_clocks VIRTUAL_sd_slow_clk] -max -add_delay 3500.000 [get_ports sd_cmd]
+# set_clock_groups -physically_exclusive -group [get_clocks -include_generated_clocks sd_clk_out] -group [get_clocks -include_generated_clocks sd_clk_out_1]
+# set_clock_groups -logically_exclusive -group [get_clocks -include_generated_clocks {VIRTUAL_sd_fast_clk sd_fast_clk}] -group [get_clocks -include_generated_clocks {sd_slow_clk VIRTUAL_sd_slow_clk}]
+# set_clock_groups -asynchronous -group [get_clocks [list [get_clocks -of_objects [get_pins clk_mmcm/chipset_clk]]]] -group [get_clocks -filter { NAME =~ "*sd*" }]
+
+
+# Genesys 2 has a quad SPI flash
+# set_property BITSTREAM.CONFIG.SPI_BUSWIDTH 4 [current_design]
+
+## JTAG
+# minimize routing delay
+
+set_max_delay -to [get_ports tdo ] 20
+set_max_delay -from [get_ports tms ] 20
+set_max_delay -from [get_ports tdi ] 20
+set_max_delay -from [get_ports trst ] 20
+
+# reset signal
+# set_false_path -from [get_ports { trst } ]
+# set_false_path -from [get_pins i_ddr/u_xlnx_mig_7_ddr3_mig/u_ddr3_infrastructure/rstdiv0_sync_r1_reg_rep/C]
diff --git a/fpga/scripts/program.tcl b/fpga/scripts/program.tcl
index 40321272f2fbcd93477246b2fa51d26b84bacce3..0dbb1b67ce6f35d5319e3620243604631a8c9bf7 100644
--- a/fpga/scripts/program.tcl
+++ b/fpga/scripts/program.tcl
@@ -18,9 +18,21 @@
open_hw
connect_hw_server -url localhost:3121
-open_hw_target {localhost:3121/xilinx_tcf/Digilent/200300A8CD43B}
-current_hw_device [get_hw_devices xc7k325t_0]
-set_property PROGRAM.FILE {work-fpga/ariane_xilinx.bit} [get_hw_devices xc7k325t_0]
-program_hw_devices [get_hw_devices xc7k325t_0]
-refresh_hw_device [lindex [get_hw_devices xc7k325t_0] 0]
+if {$::env(BOARD) eq "genesys2"} {
+ open_hw_target {localhost:3121/xilinx_tcf/Digilent/200300A8CD43B}
+
+ current_hw_device [get_hw_devices xc7k325t_0]
+ set_property PROGRAM.FILE {work-fpga/ariane_xilinx.bit} [get_hw_devices xc7k325t_0]
+ program_hw_devices [get_hw_devices xc7k325t_0]
+ refresh_hw_device [lindex [get_hw_devices xc7k325t_0] 0]
+} elseif {$::env(BOARD) eq "vc707"} {
+ open_hw_target {localhost:3121/xilinx_tcf/Digilent/210203A5FC70A}
+
+ current_hw_device [get_hw_devices xc7vx485t_0]
+ set_property PROGRAM.FILE {work-fpga/ariane_xilinx.bit} [get_hw_devices xc7vx485t_0]
+ program_hw_devices [get_hw_devices xc7vx485t_0]
+ refresh_hw_device [lindex [get_hw_devices xc7vx485t_0] 0]
+} else {
+ exit 1
+}
diff --git a/fpga/scripts/run.tcl b/fpga/scripts/run.tcl
index a3bb14c147337f8ca678c2b383617b226a322d65..7804fb3fe8a6bf2090ac1ca8560842d46943b901 100644
--- a/fpga/scripts/run.tcl
+++ b/fpga/scripts/run.tcl
@@ -20,6 +20,8 @@ if {$::env(BOARD) eq "genesys2"} {
add_files -fileset constrs_1 -norecurse constraints/genesys-2.xdc
} elseif {$::env(BOARD) eq "kc705"} {
add_files -fileset constrs_1 -norecurse constraints/kc705.xdc
+} elseif {$::env(BOARD) eq "vc707"} {
+ add_files -fileset constrs_1 -norecurse constraints/vc707.xdc
} else {
exit 1
}
@@ -46,6 +48,10 @@ if {$::env(BOARD) eq "genesys2"} {
read_verilog -sv {src/kc705.svh ../src/common_cells/include/common_cells/registers.svh}
set file "src/kc705.svh"
set registers "../src/common_cells/include/common_cells/registers.svh"
+} elseif {$::env(BOARD) eq "vc707"} {
+ read_verilog -sv {src/vc707.svh ../src/common_cells/include/common_cells/registers.svh}
+ set file "src/vc707.svh"
+ set registers "../src/common_cells/include/common_cells/registers.svh"
} else {
exit 1
}
diff --git a/fpga/scripts/write_cfgmem.tcl b/fpga/scripts/write_cfgmem.tcl
index c940e278e645fb24f4eb2e2005a9f527fd415aaf..30f3e96288049138bd6d1d4211aabeb953628067 100644
--- a/fpga/scripts/write_cfgmem.tcl
+++ b/fpga/scripts/write_cfgmem.tcl
@@ -25,4 +25,11 @@ if {$argc < 2 || $argc > 4} {
lassign $argv mcsfile bitfile
# https://scholar.princeton.edu/jbalkind/blog/programming-genesys-2-qspi-spi-x4-flash
-write_cfgmem -format mcs -interface SPIx4 -size 256 -loadbit "up 0x0 $bitfile" -file $mcsfile -force
+# https://scholar.princeton.edu/jbalkind/blog/programming-vc707-virtex-7-bpi-flash
+if {$::env(BOARD) eq "genesys2"} {
+ write_cfgmem -format mcs -interface SPIx4 -size 256 -loadbit "up 0x0 $bitfile" -file $mcsfile -force
+} elseif {$::env(BOARD) eq "vc707"} {
+ write_cfgmem -format mcs -interface bpix16 -size 128 -loadbit "up 0x0 $bitfile" -file $mcsfile -force
+} else {
+ exit 1
+}
diff --git a/fpga/sourceme.sh b/fpga/sourceme.sh
index b35e22e1958c02543dd54ca0b45e5d186313418e..f3267beb038998aa129aa81f674e88ff4085c2d8 100644
--- a/fpga/sourceme.sh
+++ b/fpga/sourceme.sh
@@ -20,3 +20,11 @@ if [ "$BOARD" = "kc705" ]; then
export XILINX_BOARD="xilinx.com:kc705:part0:1.5"
export CLK_PERIOD_NS="20"
fi
+
+if [ "$BOARD" = "vc707" ]; then
+ echo -n "Configuring for "
+ echo "Virtex vc707"
+ export XILINX_PART="xc7vx485tffg1761-2"
+ export XILINX_BOARD="xilinx.com:vc707:part0:1.3"
+ export CLK_PERIOD_NS="20"
+fi
diff --git a/fpga/src/ariane_xilinx.sv b/fpga/src/ariane_xilinx.sv
index 8931146a8d049aac1108706b1a41685751cbc3bf..331c3b01c5d5ebc195140713986b998c45e1aff0 100644
--- a/fpga/src/ariane_xilinx.sv
+++ b/fpga/src/ariane_xilinx.sv
@@ -77,6 +77,37 @@ module ariane_xilinx (
output logic [ 3:0] led ,
input logic [ 3:0] sw ,
output logic fan_pwm ,
+`elsif VC707
+ input logic sys_clk_p ,
+ input logic sys_clk_n ,
+ input logic cpu_reset ,
+ inout wire [63:0] ddr3_dq ,
+ inout wire [ 7:0] ddr3_dqs_n ,
+ inout wire [ 7:0] ddr3_dqs_p ,
+ output logic [13:0] ddr3_addr ,
+ output logic [ 2:0] ddr3_ba ,
+ output logic ddr3_ras_n ,
+ output logic ddr3_cas_n ,
+ output logic ddr3_we_n ,
+ output logic ddr3_reset_n,
+ output logic [ 0:0] ddr3_ck_p ,
+ output logic [ 0:0] ddr3_ck_n ,
+ output logic [ 0:0] ddr3_cke ,
+ output logic [ 0:0] ddr3_cs_n ,
+ output logic [ 7:0] ddr3_dm ,
+ output logic [ 0:0] ddr3_odt ,
+ output wire eth_rst_n ,
+ input wire eth_rxck ,
+ input wire eth_rxctl ,
+ input wire [3:0] eth_rxd ,
+ output wire eth_txck ,
+ output wire eth_txctl ,
+ output wire [3:0] eth_txd ,
+ inout wire eth_mdio ,
+ output logic eth_mdc ,
+ output logic [ 7:0] led ,
+ input logic [ 7:0] sw ,
+ output logic fan_pwm ,
`elsif VCU118
input wire c0_sys_clk_p , // 250 MHz Clock for DDR
input wire c0_sys_clk_n , // 250 MHz Clock for DDR
@@ -169,6 +200,8 @@ logic cpu_reset;
assign cpu_reset = ~cpu_resetn;
`elsif KC705
assign cpu_resetn = ~cpu_reset;
+`elsif VC707
+assign cpu_resetn = ~cpu_reset;
`endif
logic pll_locked;
@@ -479,6 +512,9 @@ ariane_peripherals #(
`elsif KC705
.InclSPI ( 1'b1 ),
.InclEthernet ( 1'b0 ) // Ethernet requires RAMB16 fpga/src/ariane-ethernet/dualmem_widen8.sv to be defined
+ `elsif VC707
+ .InclSPI ( 1'b1 ),
+ .InclEthernet ( 1'b0 )
`elsif VCU118
.InclSPI ( 1'b0 ),
.InclEthernet ( 1'b0 )
@@ -750,6 +786,83 @@ fan_ctrl i_fan_ctrl (
.fan_pwm_o ( fan_pwm )
);
+xlnx_mig_7_ddr3 i_ddr (
+ .sys_clk_p,
+ .sys_clk_n,
+ .ddr3_dq,
+ .ddr3_dqs_n,
+ .ddr3_dqs_p,
+ .ddr3_addr,
+ .ddr3_ba,
+ .ddr3_ras_n,
+ .ddr3_cas_n,
+ .ddr3_we_n,
+ .ddr3_reset_n,
+ .ddr3_ck_p,
+ .ddr3_ck_n,
+ .ddr3_cke,
+ .ddr3_cs_n,
+ .ddr3_dm,
+ .ddr3_odt,
+ .mmcm_locked ( ), // keep open
+ .app_sr_req ( '0 ),
+ .app_ref_req ( '0 ),
+ .app_zq_req ( '0 ),
+ .app_sr_active ( ), // keep open
+ .app_ref_ack ( ), // keep open
+ .app_zq_ack ( ), // keep open
+ .ui_clk ( ddr_clock_out ),
+ .ui_clk_sync_rst ( ddr_sync_reset ),
+ .aresetn ( ndmreset_n ),
+ .s_axi_awid,
+ .s_axi_awaddr ( s_axi_awaddr[29:0] ),
+ .s_axi_awlen,
+ .s_axi_awsize,
+ .s_axi_awburst,
+ .s_axi_awlock,
+ .s_axi_awcache,
+ .s_axi_awprot,
+ .s_axi_awqos,
+ .s_axi_awvalid,
+ .s_axi_awready,
+ .s_axi_wdata,
+ .s_axi_wstrb,
+ .s_axi_wlast,
+ .s_axi_wvalid,
+ .s_axi_wready,
+ .s_axi_bready,
+ .s_axi_bid,
+ .s_axi_bresp,
+ .s_axi_bvalid,
+ .s_axi_arid,
+ .s_axi_araddr ( s_axi_araddr[29:0] ),
+ .s_axi_arlen,
+ .s_axi_arsize,
+ .s_axi_arburst,
+ .s_axi_arlock,
+ .s_axi_arcache,
+ .s_axi_arprot,
+ .s_axi_arqos,
+ .s_axi_arvalid,
+ .s_axi_arready,
+ .s_axi_rready,
+ .s_axi_rid,
+ .s_axi_rdata,
+ .s_axi_rresp,
+ .s_axi_rlast,
+ .s_axi_rvalid,
+ .init_calib_complete ( ), // keep open
+ .device_temp ( ), // keep open
+ .sys_rst ( cpu_resetn )
+);
+`elsif VC707
+fan_ctrl i_fan_ctrl (
+ .clk_i ( clk ),
+ .rst_ni ( ndmreset_n ),
+ .pwm_setting_i ( '1 ),
+ .fan_pwm_o ( fan_pwm )
+);
+
xlnx_mig_7_ddr3 i_ddr (
.sys_clk_p,
.sys_clk_n,
diff --git a/fpga/src/vc707.svh b/fpga/src/vc707.svh
new file mode 100644
index 0000000000000000000000000000000000000000..3886cae984a46903305159d7e182fb220edae747
--- /dev/null
+++ b/fpga/src/vc707.svh
@@ -0,0 +1,25 @@
+// Copyright 2018 ETH Zurich and University of Bologna.
+// Copyright and related rights are licensed under the Solderpad Hardware
+// License, Version 0.51 (the "License"); you may not use this file except in
+// compliance with the License. You may obtain a copy of the License at
+// http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law
+// or agreed to in writing, software, hardware and materials distributed under
+// this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR
+// CONDITIONS OF ANY KIND, either express or implied. See the License for the
+// specific language governing permissions and limitations under the License.
+
+// Description: Set global FPGA degines
+// Author: Florian Zaruba <zarubaf@iis.ee.ethz.ch>
+
+`define VC707
+
+`define ARIANE_DATA_WIDTH 64
+
+// Instantiate protocl checker
+// `define PROTOCOL_CHECKER
+
+// write-back cache
+// `define WB_DCACHE
+
+// write-through cache
+`define WT_DCACHE
diff --git a/fpga/xilinx/xlnx_mig_7_ddr3/mig_vc707.prj b/fpga/xilinx/xlnx_mig_7_ddr3/mig_vc707.prj
new file mode 100644
index 0000000000000000000000000000000000000000..fcf0bbe954a5b503c065b79c52e780359a31a777
--- /dev/null
+++ b/fpga/xilinx/xlnx_mig_7_ddr3/mig_vc707.prj
@@ -0,0 +1,203 @@
+<?xml version='1.0' encoding='UTF-8'?>
+<!-- IMPORTANT: This is an internal file that has been generated by the MIG software. Any direct editing or changes made to this file may result in unpredictable behavior or data corruption. It is strongly advised that users do not edit the contents of this file. Re-run the MIG GUI with the required settings if any of the options provided below need to be altered. -->
+<Project NoOfControllers="1" >
+ <ModuleName>xlnx_mig_7_ddr3</ModuleName>
+ <dci_inouts_inputs>1</dci_inouts_inputs>
+ <dci_inputs>1</dci_inputs>
+ <Debug_En>OFF</Debug_En>
+ <DataDepth_En>1024</DataDepth_En>
+ <LowPower_En>ON</LowPower_En>
+ <XADC_En>Enabled</XADC_En>
+ <TargetFPGA>xc7vx485t-ffg1761/-2</TargetFPGA>
+ <Version>4.1</Version>
+ <SystemClock>Differential</SystemClock>
+ <ReferenceClock>Use System Clock</ReferenceClock>
+ <SysResetPolarity>ACTIVE LOW</SysResetPolarity>
+ <BankSelectionFlag>FALSE</BankSelectionFlag>
+ <InternalVref>0</InternalVref>
+ <dci_hr_inouts_inputs>50 Ohms</dci_hr_inouts_inputs>
+ <dci_cascade>0</dci_cascade>
+ <Controller number="0" >
+ <MemoryDevice>DDR3_SDRAM/SODIMMs/MT8JTF12864HZ-1G6</MemoryDevice>
+ <TimePeriod>1250</TimePeriod>
+ <VccAuxIO>2.0V</VccAuxIO>
+ <PHYRatio>4:1</PHYRatio>
+ <InputClkFreq>200</InputClkFreq>
+ <UIExtraClocks>0</UIExtraClocks>
+ <MMCM_VCO>800</MMCM_VCO>
+ <MMCMClkOut0> 1.000</MMCMClkOut0>
+ <MMCMClkOut1>1</MMCMClkOut1>
+ <MMCMClkOut2>1</MMCMClkOut2>
+ <MMCMClkOut3>1</MMCMClkOut3>
+ <MMCMClkOut4>1</MMCMClkOut4>
+ <DataWidth>64</DataWidth>
+ <DeepMemory>1</DeepMemory>
+ <DataMask>1</DataMask>
+ <ECC>Disabled</ECC>
+ <Ordering>Normal</Ordering>
+ <BankMachineCnt>4</BankMachineCnt>
+ <CustomPart>FALSE</CustomPart>
+ <NewPartName></NewPartName>
+ <RowAddress>14</RowAddress>
+ <ColAddress>10</ColAddress>
+ <BankAddress>3</BankAddress>
+ <MemoryVoltage>1.5V</MemoryVoltage>
+ <UserMemoryAddressMap>BANK_ROW_COLUMN</UserMemoryAddressMap>
+ <PinSelection>
+ <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15" PADName="A20" SLEW="" name="ddr3_addr[0]" IN_TERM="" />
+ <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15" PADName="B21" SLEW="" name="ddr3_addr[10]" IN_TERM="" />
+ <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15" PADName="B17" SLEW="" name="ddr3_addr[11]" IN_TERM="" />
+ <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15" PADName="A15" SLEW="" name="ddr3_addr[12]" IN_TERM="" />
+ <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15" PADName="A21" SLEW="" name="ddr3_addr[13]" IN_TERM="" />
+ <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15" PADName="B19" SLEW="" name="ddr3_addr[1]" IN_TERM="" />
+ <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15" PADName="C20" SLEW="" name="ddr3_addr[2]" IN_TERM="" />
+ <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15" PADName="A19" SLEW="" name="ddr3_addr[3]" IN_TERM="" />
+ <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15" PADName="A17" SLEW="" name="ddr3_addr[4]" IN_TERM="" />
+ <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15" PADName="A16" SLEW="" name="ddr3_addr[5]" IN_TERM="" />
+ <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15" PADName="D20" SLEW="" name="ddr3_addr[6]" IN_TERM="" />
+ <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15" PADName="C18" SLEW="" name="ddr3_addr[7]" IN_TERM="" />
+ <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15" PADName="D17" SLEW="" name="ddr3_addr[8]" IN_TERM="" />
+ <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15" PADName="C19" SLEW="" name="ddr3_addr[9]" IN_TERM="" />
+ <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15" PADName="D21" SLEW="" name="ddr3_ba[0]" IN_TERM="" />
+ <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15" PADName="C21" SLEW="" name="ddr3_ba[1]" IN_TERM="" />
+ <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15" PADName="D18" SLEW="" name="ddr3_ba[2]" IN_TERM="" />
+ <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15" PADName="K17" SLEW="" name="ddr3_cas_n" IN_TERM="" />
+ <Pin VCCAUX_IO="HIGH" IOSTANDARD="DIFF_SSTL15" PADName="G18" SLEW="" name="ddr3_ck_n[0]" IN_TERM="" />
+ <Pin VCCAUX_IO="HIGH" IOSTANDARD="DIFF_SSTL15" PADName="H19" SLEW="" name="ddr3_ck_p[0]" IN_TERM="" />
+ <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15" PADName="K19" SLEW="" name="ddr3_cke[0]" IN_TERM="" />
+ <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15" PADName="J17" SLEW="" name="ddr3_cs_n[0]" IN_TERM="" />
+ <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15" PADName="M13" SLEW="" name="ddr3_dm[0]" IN_TERM="" />
+ <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15" PADName="K15" SLEW="" name="ddr3_dm[1]" IN_TERM="" />
+ <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15" PADName="F12" SLEW="" name="ddr3_dm[2]" IN_TERM="" />
+ <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15" PADName="A14" SLEW="" name="ddr3_dm[3]" IN_TERM="" />
+ <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15" PADName="C23" SLEW="" name="ddr3_dm[4]" IN_TERM="" />
+ <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15" PADName="D25" SLEW="" name="ddr3_dm[5]" IN_TERM="" />
+ <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15" PADName="C31" SLEW="" name="ddr3_dm[6]" IN_TERM="" />
+ <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15" PADName="F31" SLEW="" name="ddr3_dm[7]" IN_TERM="" />
+ <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="N14" SLEW="" name="ddr3_dq[0]" IN_TERM="" />
+ <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="H13" SLEW="" name="ddr3_dq[10]" IN_TERM="" />
+ <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="J13" SLEW="" name="ddr3_dq[11]" IN_TERM="" />
+ <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="L16" SLEW="" name="ddr3_dq[12]" IN_TERM="" />
+ <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="L15" SLEW="" name="ddr3_dq[13]" IN_TERM="" />
+ <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="H14" SLEW="" name="ddr3_dq[14]" IN_TERM="" />
+ <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="J15" SLEW="" name="ddr3_dq[15]" IN_TERM="" />
+ <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="E15" SLEW="" name="ddr3_dq[16]" IN_TERM="" />
+ <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="E13" SLEW="" name="ddr3_dq[17]" IN_TERM="" />
+ <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="F15" SLEW="" name="ddr3_dq[18]" IN_TERM="" />
+ <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="E14" SLEW="" name="ddr3_dq[19]" IN_TERM="" />
+ <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="N13" SLEW="" name="ddr3_dq[1]" IN_TERM="" />
+ <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="G13" SLEW="" name="ddr3_dq[20]" IN_TERM="" />
+ <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="G12" SLEW="" name="ddr3_dq[21]" IN_TERM="" />
+ <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="F14" SLEW="" name="ddr3_dq[22]" IN_TERM="" />
+ <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="G14" SLEW="" name="ddr3_dq[23]" IN_TERM="" />
+ <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="B14" SLEW="" name="ddr3_dq[24]" IN_TERM="" />
+ <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="C13" SLEW="" name="ddr3_dq[25]" IN_TERM="" />
+ <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="B16" SLEW="" name="ddr3_dq[26]" IN_TERM="" />
+ <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="D15" SLEW="" name="ddr3_dq[27]" IN_TERM="" />
+ <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="D13" SLEW="" name="ddr3_dq[28]" IN_TERM="" />
+ <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="E12" SLEW="" name="ddr3_dq[29]" IN_TERM="" />
+ <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="L14" SLEW="" name="ddr3_dq[2]" IN_TERM="" />
+ <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="C16" SLEW="" name="ddr3_dq[30]" IN_TERM="" />
+ <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="D16" SLEW="" name="ddr3_dq[31]" IN_TERM="" />
+ <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="A24" SLEW="" name="ddr3_dq[32]" IN_TERM="" />
+ <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="B23" SLEW="" name="ddr3_dq[33]" IN_TERM="" />
+ <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="B27" SLEW="" name="ddr3_dq[34]" IN_TERM="" />
+ <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="B26" SLEW="" name="ddr3_dq[35]" IN_TERM="" />
+ <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="A22" SLEW="" name="ddr3_dq[36]" IN_TERM="" />
+ <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="B22" SLEW="" name="ddr3_dq[37]" IN_TERM="" />
+ <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="A25" SLEW="" name="ddr3_dq[38]" IN_TERM="" />
+ <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="C24" SLEW="" name="ddr3_dq[39]" IN_TERM="" />
+ <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="M14" SLEW="" name="ddr3_dq[3]" IN_TERM="" />
+ <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="E24" SLEW="" name="ddr3_dq[40]" IN_TERM="" />
+ <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="D23" SLEW="" name="ddr3_dq[41]" IN_TERM="" />
+ <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="D26" SLEW="" name="ddr3_dq[42]" IN_TERM="" />
+ <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="C25" SLEW="" name="ddr3_dq[43]" IN_TERM="" />
+ <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="E23" SLEW="" name="ddr3_dq[44]" IN_TERM="" />
+ <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="D22" SLEW="" name="ddr3_dq[45]" IN_TERM="" />
+ <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="F22" SLEW="" name="ddr3_dq[46]" IN_TERM="" />
+ <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="E22" SLEW="" name="ddr3_dq[47]" IN_TERM="" />
+ <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="A30" SLEW="" name="ddr3_dq[48]" IN_TERM="" />
+ <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="D27" SLEW="" name="ddr3_dq[49]" IN_TERM="" />
+ <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="M12" SLEW="" name="ddr3_dq[4]" IN_TERM="" />
+ <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="A29" SLEW="" name="ddr3_dq[50]" IN_TERM="" />
+ <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="C28" SLEW="" name="ddr3_dq[51]" IN_TERM="" />
+ <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="D28" SLEW="" name="ddr3_dq[52]" IN_TERM="" />
+ <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="B31" SLEW="" name="ddr3_dq[53]" IN_TERM="" />
+ <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="A31" SLEW="" name="ddr3_dq[54]" IN_TERM="" />
+ <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="A32" SLEW="" name="ddr3_dq[55]" IN_TERM="" />
+ <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="E30" SLEW="" name="ddr3_dq[56]" IN_TERM="" />
+ <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="F29" SLEW="" name="ddr3_dq[57]" IN_TERM="" />
+ <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="F30" SLEW="" name="ddr3_dq[58]" IN_TERM="" />
+ <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="F27" SLEW="" name="ddr3_dq[59]" IN_TERM="" />
+ <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="N15" SLEW="" name="ddr3_dq[5]" IN_TERM="" />
+ <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="C30" SLEW="" name="ddr3_dq[60]" IN_TERM="" />
+ <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="E29" SLEW="" name="ddr3_dq[61]" IN_TERM="" />
+ <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="F26" SLEW="" name="ddr3_dq[62]" IN_TERM="" />
+ <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="D30" SLEW="" name="ddr3_dq[63]" IN_TERM="" />
+ <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="M11" SLEW="" name="ddr3_dq[6]" IN_TERM="" />
+ <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="L12" SLEW="" name="ddr3_dq[7]" IN_TERM="" />
+ <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="K14" SLEW="" name="ddr3_dq[8]" IN_TERM="" />
+ <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="K13" SLEW="" name="ddr3_dq[9]" IN_TERM="" />
+ <Pin VCCAUX_IO="HIGH" IOSTANDARD="DIFF_SSTL15_T_DCI" PADName="M16" SLEW="" name="ddr3_dqs_n[0]" IN_TERM="" />
+ <Pin VCCAUX_IO="HIGH" IOSTANDARD="DIFF_SSTL15_T_DCI" PADName="J12" SLEW="" name="ddr3_dqs_n[1]" IN_TERM="" />
+ <Pin VCCAUX_IO="HIGH" IOSTANDARD="DIFF_SSTL15_T_DCI" PADName="G16" SLEW="" name="ddr3_dqs_n[2]" IN_TERM="" />
+ <Pin VCCAUX_IO="HIGH" IOSTANDARD="DIFF_SSTL15_T_DCI" PADName="C14" SLEW="" name="ddr3_dqs_n[3]" IN_TERM="" />
+ <Pin VCCAUX_IO="HIGH" IOSTANDARD="DIFF_SSTL15_T_DCI" PADName="A27" SLEW="" name="ddr3_dqs_n[4]" IN_TERM="" />
+ <Pin VCCAUX_IO="HIGH" IOSTANDARD="DIFF_SSTL15_T_DCI" PADName="E25" SLEW="" name="ddr3_dqs_n[5]" IN_TERM="" />
+ <Pin VCCAUX_IO="HIGH" IOSTANDARD="DIFF_SSTL15_T_DCI" PADName="B29" SLEW="" name="ddr3_dqs_n[6]" IN_TERM="" />
+ <Pin VCCAUX_IO="HIGH" IOSTANDARD="DIFF_SSTL15_T_DCI" PADName="E28" SLEW="" name="ddr3_dqs_n[7]" IN_TERM="" />
+ <Pin VCCAUX_IO="HIGH" IOSTANDARD="DIFF_SSTL15_T_DCI" PADName="N16" SLEW="" name="ddr3_dqs_p[0]" IN_TERM="" />
+ <Pin VCCAUX_IO="HIGH" IOSTANDARD="DIFF_SSTL15_T_DCI" PADName="K12" SLEW="" name="ddr3_dqs_p[1]" IN_TERM="" />
+ <Pin VCCAUX_IO="HIGH" IOSTANDARD="DIFF_SSTL15_T_DCI" PADName="H16" SLEW="" name="ddr3_dqs_p[2]" IN_TERM="" />
+ <Pin VCCAUX_IO="HIGH" IOSTANDARD="DIFF_SSTL15_T_DCI" PADName="C15" SLEW="" name="ddr3_dqs_p[3]" IN_TERM="" />
+ <Pin VCCAUX_IO="HIGH" IOSTANDARD="DIFF_SSTL15_T_DCI" PADName="A26" SLEW="" name="ddr3_dqs_p[4]" IN_TERM="" />
+ <Pin VCCAUX_IO="HIGH" IOSTANDARD="DIFF_SSTL15_T_DCI" PADName="F25" SLEW="" name="ddr3_dqs_p[5]" IN_TERM="" />
+ <Pin VCCAUX_IO="HIGH" IOSTANDARD="DIFF_SSTL15_T_DCI" PADName="B28" SLEW="" name="ddr3_dqs_p[6]" IN_TERM="" />
+ <Pin VCCAUX_IO="HIGH" IOSTANDARD="DIFF_SSTL15_T_DCI" PADName="E27" SLEW="" name="ddr3_dqs_p[7]" IN_TERM="" />
+ <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15" PADName="H20" SLEW="" name="ddr3_odt[0]" IN_TERM="" />
+ <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15" PADName="E20" SLEW="" name="ddr3_ras_n" IN_TERM="" />
+ <Pin VCCAUX_IO="HIGH" IOSTANDARD="LVCMOS15" PADName="C29" SLEW="" name="ddr3_reset_n" IN_TERM="" />
+ <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15" PADName="F20" SLEW="" name="ddr3_we_n" IN_TERM="" />
+ </PinSelection>
+ <System_Clock>
+ <Pin PADName="E19/E18(CC_P/N)" Bank="38" name="sys_clk_p/n" />
+ </System_Clock>
+ <System_Control>
+ <Pin PADName="AV40(MRCC_P)" Bank="15" name="sys_rst" />
+ <Pin PADName="No connect" Bank="Select Bank" name="init_calib_complete" />
+ <Pin PADName="No connect" Bank="Select Bank" name="tg_compare_error" />
+ </System_Control>
+ <TimingParameters>
+ <Parameters twtr="7.5" trrd="6" trefi="7.8" tfaw="30" trtp="7.5" tcke="5" trfc="110" trp="13.75" tras="35" trcd="13.75" />
+ </TimingParameters>
+ <mrBurstLength name="Burst Length" >8 - Fixed</mrBurstLength>
+ <mrBurstType name="Read Burst Type and Length" >Sequential</mrBurstType>
+ <mrCasLatency name="CAS Latency" >11</mrCasLatency>
+ <mrMode name="Mode" >Normal</mrMode>
+ <mrDllReset name="DLL Reset" >No</mrDllReset>
+ <mrPdMode name="DLL control for precharge PD" >Slow Exit</mrPdMode>
+ <emrDllEnable name="DLL Enable" >Enable</emrDllEnable>
+ <emrOutputDriveStrength name="Output Driver Impedance Control" >RZQ/7</emrOutputDriveStrength>
+ <emrMirrorSelection name="Address Mirroring" >Disable</emrMirrorSelection>
+ <emrCSSelection name="Controller Chip Select Pin" >Enable</emrCSSelection>
+ <emrRTT name="RTT (nominal) - On Die Termination (ODT)" >RZQ/6</emrRTT>
+ <emrPosted name="Additive Latency (AL)" >0</emrPosted>
+ <emrOCD name="Write Leveling Enable" >Disabled</emrOCD>
+ <emrDQS name="TDQS enable" >Enabled</emrDQS>
+ <emrRDQS name="Qoff" >Output Buffer Enabled</emrRDQS>
+ <mr2PartialArraySelfRefresh name="Partial-Array Self Refresh" >Full Array</mr2PartialArraySelfRefresh>
+ <mr2CasWriteLatency name="CAS write latency" >8</mr2CasWriteLatency>
+ <mr2AutoSelfRefresh name="Auto Self Refresh" >Enabled</mr2AutoSelfRefresh>
+ <mr2SelfRefreshTempRange name="High Temparature Self Refresh Rate" >Normal</mr2SelfRefreshTempRange>
+ <mr2RTTWR name="RTT_WR - Dynamic On Die Termination (ODT)" >Dynamic ODT off</mr2RTTWR>
+ <PortInterface>AXI</PortInterface>
+ <AXIParameters>
+ <C0_C_RD_WR_ARB_ALGORITHM>RD_PRI_REG</C0_C_RD_WR_ARB_ALGORITHM>
+ <C0_S_AXI_ADDR_WIDTH>30</C0_S_AXI_ADDR_WIDTH>
+ <C0_S_AXI_DATA_WIDTH>64</C0_S_AXI_DATA_WIDTH>
+ <C0_S_AXI_ID_WIDTH>5</C0_S_AXI_ID_WIDTH>
+ <C0_S_AXI_SUPPORTS_NARROW_BURST>0</C0_S_AXI_SUPPORTS_NARROW_BURST>
+ </AXIParameters>
+ </Controller>
+
+</Project>