diff --git a/Flist.ariane b/Flist.ariane
index 60492174e034cf95edc15119e9e0f1ae36de7682..45e1d49b3902e208ac5b51c82bab5b82c5786b76 100644
--- a/Flist.ariane
+++ b/Flist.ariane
@@ -17,19 +17,14 @@
 // Description: File list for OpenPiton flow
 +incdir+src/common_cells/include/common_cells/
 +incdir+src/util/
-src/common_cells/src/deprecated/fifo_v1.sv
-src/common_cells/src/deprecated/fifo_v2.sv
 src/common_cells/src/fifo_v3.sv
 src/common_cells/src/lfsr_8bit.sv
 src/common_cells/src/lzc.sv
 src/common_cells/src/rr_arb_tree.sv
-src/common_cells/src/deprecated/rrarbiter.sv
 src/common_cells/src/rstgen_bypass.sv
 src/common_cells/src/sync.sv
 src/common_cells/src/sync_wedge.sv
 src/common_cells/src/cdc_2phase.sv
-src/common_cells/src/deprecated/stream_arbiter.sv
-src/common_cells/src/deprecated/stream_arbiter_flushable.sv
 src/common_cells/src/shift_reg.sv
 src/register_interface/src/apb_to_reg.sv
 src/register_interface/src/reg_intf_pkg.sv
diff --git a/Makefile b/Makefile
index 7d2ccec16d38b7322bf92e65bfe125e05b6eba1f..4dc8febf43fccc84570a25e6665de0919da26bf5 100644
--- a/Makefile
+++ b/Makefile
@@ -137,8 +137,6 @@ src :=  $(filter-out src/ariane_regfile.sv, $(wildcard src/*.sv))              \
         src/common_cells/src/rstgen.sv                                         \
         src/common_cells/src/stream_mux.sv                                     \
         src/common_cells/src/stream_demux.sv                                   \
-        src/common_cells/src/deprecated/stream_arbiter.sv                      \
-        src/common_cells/src/deprecated/stream_arbiter_flushable.sv            \
         src/util/axi_master_connect.sv                                         \
         src/util/axi_slave_connect.sv                                          \
         src/util/axi_master_connect_rev.sv                                     \
@@ -153,9 +151,11 @@ src :=  $(filter-out src/ariane_regfile.sv, $(wildcard src/*.sv))              \
         src/common_cells/src/spill_register.sv                                 \
         src/common_cells/src/sync_wedge.sv                                     \
         src/common_cells/src/edge_detect.sv                                    \
-        src/common_cells/src/fifo_v3.sv                                        \
-        src/common_cells/src/deprecated/fifo_v2.sv                             \
+        src/common_cells/src/deprecated/stream_arbiter.sv                      \
+        src/common_cells/src/deprecated/stream_arbiter_flushable.sv            \
         src/common_cells/src/deprecated/fifo_v1.sv                             \
+        src/common_cells/src/deprecated/fifo_v2.sv                             \
+        src/common_cells/src/fifo_v3.sv                                        \
         src/common_cells/src/lzc.sv                                            \
         src/common_cells/src/rr_arb_tree.sv                                    \
         src/common_cells/src/deprecated/rrarbiter.sv                           \
diff --git a/src/amo_buffer.sv b/src/amo_buffer.sv
index 89ed8484ac418277d1edd91f9bb6469e64aa838c..288aed269d526e49a6f59ee4d9b41ded473635de 100644
--- a/src/amo_buffer.sv
+++ b/src/amo_buffer.sv
@@ -60,10 +60,8 @@ module amo_buffer (
     // e.g.: it is not speculative anymore
     assign flush_amo_buffer = flush_i & !amo_valid_commit_i;
 
-    fifo_v2 #(
+    fifo_v3 #(
         .DEPTH        ( 1                ),
-        .ALM_EMPTY_TH ( 0                ),
-        .ALM_FULL_TH  ( 0                ),
         .dtype        ( amo_op_t         )
     ) i_amo_fifo (
         .clk_i        ( clk_i            ),
@@ -72,8 +70,7 @@ module amo_buffer (
         .testmode_i   ( 1'b0             ),
         .full_o       ( amo_valid        ),
         .empty_o      ( ready_o          ),
-        .alm_full_o   (  ), // left open
-        .alm_empty_o  (  ), // left open
+        .usage_o      (  ), // left open
         .data_i       ( amo_data_in      ),
         .push_i       ( valid_i          ),
         .data_o       ( amo_data_out     ),
diff --git a/src/cache_subsystem/wt_axi_adapter.sv b/src/cache_subsystem/wt_axi_adapter.sv
index 824651eecb46e4f0fca695052e20d6cf0ff4f9c8..090f6e7e49ae9b3187cb3331fb0d845da4ebd50b 100644
--- a/src/cache_subsystem/wt_axi_adapter.sv
+++ b/src/cache_subsystem/wt_axi_adapter.sv
@@ -98,18 +98,23 @@ module wt_axi_adapter #(
 
   assign arb_gnt           = axi_rd_gnt | axi_wr_gnt;
 
-  rrarbiter #(
-    .NUM_REQ(2),
-    .LOCK_IN(1)
-  ) i_rrarbiter (
-    .clk_i  ( clk_i   ),
-    .rst_ni ( rst_ni  ),
-    .flush_i( '0      ),
-    .en_i   ( arb_gnt ),
-    .req_i  ( arb_req ),
-    .ack_o  ( arb_ack ),
-    .vld_o  (         ),
-    .idx_o  ( arb_idx )
+  rr_arb_tree #(
+    .NumIn     (2),
+    .DataWidth (1),
+    .AxiVldRdy (1'b1),
+    .LockIn    (1'b1)
+  ) i_rr_arb_tree (
+    .clk_i  (clk_i   ),
+    .rst_ni (rst_ni  ),
+    .flush_i('0      ),
+    .rr_i   ('0      ),
+    .req_i  (arb_req ),
+    .gnt_o  (arb_ack ),
+    .data_i ('0      ),
+    .gnt_i  (arb_gnt ),
+    .req_o  (        ),
+    .data_o (        ),
+    .idx_o  (arb_idx )
   );
 
   // request side
@@ -226,7 +231,7 @@ module wt_axi_adapter #(
     end
   end
 
-  fifo_v2 #(
+  fifo_v3 #(
     .dtype       (  icache_req_t            ),
     .DEPTH       (  ReqFifoDepth            )
   ) i_icache_data_fifo (
@@ -236,15 +241,14 @@ module wt_axi_adapter #(
     .testmode_i  (  1'b0                    ),
     .full_o      (  icache_data_full        ),
     .empty_o     (  icache_data_empty       ),
-    .alm_full_o  (                          ),
-    .alm_empty_o (                          ),
+    .usage_o     (                          ),
     .data_i      (  icache_data_i           ),
     .push_i      (  icache_data_ack_o       ),
     .data_o      (  icache_data             ),
     .pop_i       (  arb_ack[0]              )
   );
 
-  fifo_v2 #(
+  fifo_v3 #(
     .dtype       (  dcache_req_t            ),
     .DEPTH       (  ReqFifoDepth            )
   ) i_dcache_data_fifo (
@@ -254,8 +258,7 @@ module wt_axi_adapter #(
     .testmode_i  (  1'b0                    ),
     .full_o      (  dcache_data_full        ),
     .empty_o     (  dcache_data_empty       ),
-    .alm_full_o  (                          ),
-    .alm_empty_o (                          ),
+    .usage_o     (                          ),
     .data_i      (  dcache_data_i           ),
     .push_i      (  dcache_data_ack_o       ),
     .data_o      (  dcache_data             ),
@@ -271,7 +274,7 @@ module wt_axi_adapter #(
 
   fifo_v3 #(
     .DATA_WIDTH ( wt_cache_pkg::CACHE_ID_WIDTH ),
-    .DEPTH      ( MetaFifoDepth                     )
+    .DEPTH      ( MetaFifoDepth                )
   ) i_rd_icache_id (
     .clk_i      ( clk_i                   ),
     .rst_ni     ( rst_ni                  ),
@@ -288,7 +291,7 @@ module wt_axi_adapter #(
 
   fifo_v3 #(
     .DATA_WIDTH ( wt_cache_pkg::CACHE_ID_WIDTH ),
-    .DEPTH      ( MetaFifoDepth                     )
+    .DEPTH      ( MetaFifoDepth                )
   ) i_rd_dcache_id (
     .clk_i      ( clk_i                   ),
     .rst_ni     ( rst_ni                  ),
@@ -305,7 +308,7 @@ module wt_axi_adapter #(
 
   fifo_v3 #(
     .DATA_WIDTH ( wt_cache_pkg::CACHE_ID_WIDTH ),
-    .DEPTH      ( MetaFifoDepth                     )
+    .DEPTH      ( MetaFifoDepth                 )
   ) i_wr_dcache_id (
     .clk_i      ( clk_i                   ),
     .rst_ni     ( rst_ni                  ),
diff --git a/src/cache_subsystem/wt_dcache_mem.sv b/src/cache_subsystem/wt_dcache_mem.sv
index e1c2910505fa94110b162f6605a992d3208d3af1..398ebdec6745b50776c1f947d6758bd5a058de82 100644
--- a/src/cache_subsystem/wt_dcache_mem.sv
+++ b/src/cache_subsystem/wt_dcache_mem.sv
@@ -135,20 +135,26 @@ module wt_dcache_mem #(
   assign rd_req_prio   = rd_req_i & rd_prio_i;
   assign rd_req_masked = (|rd_req_prio) ? rd_req_prio : rd_req_i;
 
-  // read port arbiter
-  rrarbiter #(
-    .NUM_REQ(NumPorts)
-  ) i_rrarbiter (
-    .clk_i  ( clk_i         ),
-    .rst_ni ( rst_ni        ),
-    .flush_i( 1'b0          ),
-    .en_i   ( ~wr_cl_vld_i  ),
-    .req_i  ( rd_req_masked ),
-    .ack_o  ( rd_ack_o      ),
-    .vld_o  ( rd_acked      ),
-    .idx_o  ( vld_sel_d     )
+  logic rd_req;
+  rr_arb_tree #(
+    .NumIn     (NumPorts),
+    .DataWidth (1)
+  ) i_rr_arb_tree (
+    .clk_i  (clk_i   ),
+    .rst_ni (rst_ni  ),
+    .flush_i('0      ),
+    .rr_i   ('0      ),
+    .req_i  (rd_req_masked ),
+    .gnt_o  (rd_ack_o      ),
+    .data_i ('0            ),
+    .gnt_i  (~wr_cl_vld_i  ),
+    .req_o  (rd_req        ),
+    .data_o (              ),
+    .idx_o  (vld_sel_d     )
   );
 
+  assign rd_acked = rd_req & ~wr_cl_vld_i;
+
   always_comb begin : p_bank_req
     vld_we   = wr_cl_vld_i;
     bank_req = '0;
diff --git a/src/cache_subsystem/wt_dcache_wbuffer.sv b/src/cache_subsystem/wt_dcache_wbuffer.sv
index 865411bf46b92c1a02af5b8ba99595a311bb4df2..4bde85323b0577edcd1d6e2a48ba6972fdc799df 100644
--- a/src/cache_subsystem/wt_dcache_wbuffer.sv
+++ b/src/cache_subsystem/wt_dcache_wbuffer.sv
@@ -129,6 +129,8 @@ module wt_dcache_wbuffer #(
 
   logic [63:0] debug_paddr [DCACHE_WBUF_DEPTH-1:0];
 
+  wbuffer_t wbuffer_check_mux, wbuffer_dirty_mux;
+
 ///////////////////////////////////////////////////////
 // misc
 ///////////////////////////////////////////////////////
@@ -168,7 +170,7 @@ module wt_dcache_wbuffer #(
   );
 
   // add the offset to the physical base address of this buffer entry
-  assign miss_paddr_o = {wbuffer_q[dirty_ptr].wtag, bdirty_off};
+  assign miss_paddr_o = {wbuffer_dirty_mux.wtag, bdirty_off};
   assign miss_id_o    = tx_id;
 
   // is there any dirty word to be transmitted, and is there a free TX slot?
@@ -181,7 +183,7 @@ module wt_dcache_wbuffer #(
   assign miss_size_o  = toSize64(bdirty[dirty_ptr]);
 
   // replicate transfers shorter than a dword
-  assign miss_wdata_o = repData64(wbuffer_q[dirty_ptr].data,
+  assign miss_wdata_o = repData64(wbuffer_dirty_mux.data,
                                   bdirty_off,
                                   miss_size_o[1:0]);
 
@@ -193,7 +195,7 @@ module wt_dcache_wbuffer #(
 ///////////////////////////////////////////////////////
 
   // TODO: todo: make this fall through if timing permits it
-  fifo_v2 #(
+  fifo_v3 #(
     .FALL_THROUGH ( 1'b0                  ),
     .DATA_WIDTH   ( $clog2(DCACHE_MAX_TX) ),
     .DEPTH        ( DCACHE_MAX_TX         )
@@ -204,8 +206,7 @@ module wt_dcache_wbuffer #(
     .testmode_i ( 1'b0             ),
     .full_o     (                  ),
     .empty_o    ( rtrn_empty       ),
-    .alm_full_o (                  ),
-    .alm_empty_o(                  ),
+    .usage_o    (                  ),
     .data_i     ( miss_rtrn_id_i   ),
     .push_i     ( miss_rtrn_vld_i  ),
     .data_o     ( rtrn_id          ),
@@ -243,19 +244,23 @@ module wt_dcache_wbuffer #(
 
   assign free_tx_slots = |(~tx_vld_o);
 
-  // get free TX slot
-  rrarbiter #(
-    .NUM_REQ ( DCACHE_MAX_TX ),
-    .LOCK_IN ( 1             )// lock the decision, once request is asserted
+  // next word to lookup in the cache
+  rr_arb_tree #(
+    .NumIn     (DCACHE_MAX_TX),
+    .LockIn    (1'b1),
+    .DataWidth (1)
   ) i_tx_id_rr (
-    .clk_i   ( clk_i         ),
-    .rst_ni  ( rst_ni        ),
-    .flush_i ( 1'b0          ),
-    .en_i    ( dirty_rd_en   ),
-    .req_i   ( ~tx_vld_o     ),
-    .ack_o   (               ),
-    .vld_o   (               ),
-    .idx_o   ( tx_id         )
+    .clk_i  (clk_i       ),
+    .rst_ni (rst_ni      ),
+    .flush_i('0          ),
+    .rr_i   ('0          ),
+    .req_i  (~tx_vld_o   ),
+    .gnt_o  (            ),
+    .data_i ('0          ),
+    .gnt_i  (dirty_rd_en ),
+    .req_o  (            ),
+    .data_o (            ),
+    .idx_o  (tx_id       )
   );
 
 ///////////////////////////////////////////////////////
@@ -266,7 +271,7 @@ module wt_dcache_wbuffer #(
 
   // trigger TAG readout in cache
   assign rd_tag_only_o = 1'b1;
-  assign rd_paddr   = wbuffer_q[check_ptr_d].wtag<<3;
+  assign rd_paddr   = wbuffer_check_mux.wtag<<3;
   assign rd_req_o   = |tocheck;
   assign rd_tag_o   = rd_tag_q;//delay by one cycle
   assign rd_idx_o   = rd_paddr[DCACHE_INDEX_WIDTH-1:DCACHE_OFFSET_WIDTH];
@@ -341,32 +346,40 @@ module wt_dcache_wbuffer #(
   );
 
   // next dirty word to serve
-  rrarbiter #(
-    .NUM_REQ ( DCACHE_WBUF_DEPTH ),
-    .LOCK_IN ( 1                 )// lock the decision, once request is asserted
+  rr_arb_tree #(
+    .NumIn     ( DCACHE_WBUF_DEPTH ),
+    .LockIn    ( 1'b1              ),
+    .DataType  ( wbuffer_t         )
   ) i_dirty_rr (
-    .clk_i   ( clk_i         ),
-    .rst_ni  ( rst_ni        ),
-    .flush_i ( 1'b0          ),
-    .en_i    ( dirty_rd_en   ),
-    .req_i   ( dirty         ),
-    .ack_o   (               ),
-    .vld_o   (               ),
-    .idx_o   ( dirty_ptr     )
+    .clk_i  ( clk_i             ),
+    .rst_ni ( rst_ni            ),
+    .flush_i( '0                ),
+    .rr_i   ( '0                ),
+    .req_i  ( dirty             ),
+    .gnt_o  (                   ),
+    .data_i ( wbuffer_q         ),
+    .gnt_i  ( dirty_rd_en       ),
+    .req_o  (                   ),
+    .data_o ( wbuffer_dirty_mux ),
+    .idx_o  ( dirty_ptr         )
   );
 
   // next word to lookup in the cache
-  rrarbiter #(
-    .NUM_REQ ( DCACHE_WBUF_DEPTH )
+  rr_arb_tree #(
+    .NumIn     ( DCACHE_WBUF_DEPTH ),
+    .DataType  ( wbuffer_t         )
   ) i_clean_rr (
-    .clk_i   ( clk_i         ),
-    .rst_ni  ( rst_ni        ),
-    .flush_i ( 1'b0          ),
-    .en_i    ( check_en_d    ),
-    .req_i   ( tocheck       ),
-    .ack_o   (               ),
-    .vld_o   (               ),
-    .idx_o   ( check_ptr_d   )
+    .clk_i  ( clk_i             ),
+    .rst_ni ( rst_ni            ),
+    .flush_i( '0                ),
+    .rr_i   ( '0                ),
+    .req_i  ( tocheck           ),
+    .gnt_o  (                   ),
+    .data_i ( wbuffer_q         ),
+    .gnt_i  ( check_en_d        ),
+    .req_o  (                   ),
+    .data_o ( wbuffer_check_mux ),
+    .idx_o  ( check_ptr_d       )
   );
 
 ///////////////////////////////////////////////////////
diff --git a/src/common_cells b/src/common_cells
index 34d8ed90e03209501fa64da5cb30068846caaeca..32dd115abf114e03a9dda0c5963452c8ec82ed04 160000
--- a/src/common_cells
+++ b/src/common_cells
@@ -1 +1 @@
-Subproject commit 34d8ed90e03209501fa64da5cb30068846caaeca
+Subproject commit 32dd115abf114e03a9dda0c5963452c8ec82ed04
diff --git a/src/frontend/frontend.sv b/src/frontend/frontend.sv
index 8d661cd20b8c16946a51a18419bfbb9e63953b70..3195d0d60c64fc226d6152ee02b0a59ddc133990 100644
--- a/src/frontend/frontend.sv
+++ b/src/frontend/frontend.sv
@@ -484,8 +484,7 @@ module frontend #(
         );
     end
 
-
-    fifo_v2 #(
+    fifo_v3 #(
         .DEPTH        (  8                   ),
         .dtype        ( frontend_fetch_t     )
     ) i_fetch_fifo (
@@ -495,8 +494,7 @@ module frontend #(
         .testmode_i  ( 1'b0                  ),
         .full_o      (                       ),
         .empty_o     ( fifo_empty            ),
-        .alm_full_o  (                       ),
-        .alm_empty_o (                       ),
+        .usage_o     (                       ),
         .data_i      ( {icache_vaddr_q, icache_data_q, bp_sbe, taken[INSTR_PER_FETCH:1], icache_ex_valid_q} ),
         .push_i      ( fifo_valid            ),
         .data_o      ( fetch_entry_o         ),
diff --git a/tb/tb_wt_dcache/hdl/tb.sv b/tb/tb_wt_dcache/hdl/tb.sv
index 3b817bf9976f40d5a2afe9cdb888a108224784cd..0ff0892585de7f96660e48f46cd5f08fea5ff8d9 100644
--- a/tb/tb_wt_dcache/hdl/tb.sv
+++ b/tb/tb_wt_dcache/hdl/tb.sv
@@ -267,7 +267,7 @@ module tb;
       assign fifo_flush[k] = req_ports_i[k].kill_req;
       assign fifo_pop[k]   = req_ports_o[k].data_rvalid;
 
-      fifo_v2 #(
+      fifo_v3 #(
         .dtype(resp_fifo_t)
       ) i_resp_fifo (
         .clk_i       ( clk_i            ),
@@ -276,8 +276,7 @@ module tb;
         .testmode_i  ( '0               ),
         .full_o      (                  ),
         .empty_o     (                  ),
-        .alm_full_o  (                  ),
-        .alm_empty_o (                  ),
+        .usage_o     (                  ),
         .data_i      ( fifo_data_in[k]  ),
         .push_i      ( fifo_push[k]     ),
         .data_o      ( fifo_data[k]     ),
diff --git a/tb/tb_wt_dcache/hdl/tb_mem.sv b/tb/tb_wt_dcache/hdl/tb_mem.sv
index 3f1ba0b4d53511a66b74cf1aa15fa70a7c1e6c56..4dd3ace66ca18439b0d1a94f2a8b6795986e1886 100644
--- a/tb/tb_wt_dcache/hdl/tb_mem.sv
+++ b/tb/tb_wt_dcache/hdl/tb_mem.sv
@@ -244,7 +244,7 @@ module tb_mem #(
         end
     end
 
-  fifo_v2 #(
+  fifo_v3 #(
     .dtype(dcache_req_t),
     .DEPTH(2)
   ) i_outfifo (
@@ -254,8 +254,7 @@ module tb_mem #(
     .testmode_i  ( 1'b0          ),
     .full_o      ( outfifo_full  ),
     .empty_o     ( outfifo_empty ),
-    .alm_full_o  (               ),
-    .alm_empty_o (               ),
+    .usage_o     (               ),
     .data_i      ( mem_data_i    ),
     .push_i      ( outfifo_push  ),
     .data_o      ( outfifo_data  ),
@@ -265,7 +264,7 @@ module tb_mem #(
   assign outfifo_push   = mem_data_req_i & (~outfifo_full);
   assign mem_data_ack_o = outfifo_push;
 
-  fifo_v2 #(
+  fifo_v3 #(
     .dtype(dcache_rtrn_t),
     .DEPTH(2)
   ) i_infifo (
@@ -275,8 +274,7 @@ module tb_mem #(
     .testmode_i  ( 1'b0          ),
     .full_o      ( infifo_full   ),
     .empty_o     ( infifo_empty  ),
-    .alm_full_o  (               ),
-    .alm_empty_o (               ),
+    .usage_o     (               ),
     .data_i      ( infifo_data   ),
     .push_i      ( infifo_push   ),
     .data_o      ( mem_rtrn_o    ),
diff --git a/tb/tb_wt_dcache/tb.list b/tb/tb_wt_dcache/tb.list
index b9d19488c930a5622c7d35b4e32f281f65774b8b..2f75f9cefddf6fe5fed140e146b9a89705350f47 100644
--- a/tb/tb_wt_dcache/tb.list
+++ b/tb/tb_wt_dcache/tb.list
@@ -9,11 +9,9 @@
 ../../src/cache_subsystem/wt_dcache_wbuffer.sv
 ../../src/cache_subsystem/wt_dcache.sv
 ../../src/common_cells/src/lfsr_8bit.sv
-../../src/common_cells/src/fifo_v2.sv
 ../../src/common_cells/src/fifo_v3.sv
 ../../src/common_cells/src/lzc.sv
 ../../src/common_cells/src/rr_arb_tree.sv
-../../src/common_cells/src/rrarbiter.sv
 ../../src/util/sram.sv
 hdl/tb_pkg.sv
 hdl/tb_mem.sv
diff --git a/tb/tb_wt_icache/hdl/mem_emul.sv b/tb/tb_wt_icache/hdl/mem_emul.sv
index 23051a4a891c67252af2cdeb2d7397bfa2225256..88d327ba0ea7c51c286db0d58e71bdcecaddb2fc 100644
--- a/tb/tb_wt_icache/hdl/mem_emul.sv
+++ b/tb/tb_wt_icache/hdl/mem_emul.sv
@@ -181,7 +181,7 @@ module mem_emul #(
     end
   end
 
-  fifo_v2 #(
+  fifo_v3 #(
     .dtype(icache_req_t),
     .DEPTH(2)
   ) i_outfifo (
@@ -191,8 +191,7 @@ module mem_emul #(
     .testmode_i  ( 1'b0          ),
     .full_o      ( outfifo_full  ),
     .empty_o     ( outfifo_empty ),
-    .alm_full_o  (               ),
-    .alm_empty_o (               ),
+    .usage_o     (               ),
     .data_i      ( mem_data_i    ),
     .push_i      ( outfifo_push  ),
     .data_o      ( outfifo_data  ),
@@ -202,7 +201,7 @@ module mem_emul #(
   assign outfifo_push   = mem_data_req_i & (~outfifo_full);
   assign mem_data_ack_o = outfifo_push;
 
-  fifo_v2 #(
+  fifo_v3 #(
     .dtype(icache_rtrn_t),
     .DEPTH(2)
   ) i_infifo (
@@ -212,8 +211,7 @@ module mem_emul #(
     .testmode_i  ( 1'b0          ),
     .full_o      ( infifo_full   ),
     .empty_o     ( infifo_empty  ),
-    .alm_full_o  (               ),
-    .alm_empty_o (               ),
+    .usage_o     (               ),
     .data_i      ( infifo_data   ),
     .push_i      ( infifo_push   ),
     .data_o      ( mem_rtrn_o    ),
@@ -224,7 +222,7 @@ module mem_emul #(
   assign mem_rtrn_vld_o = infifo_pop;
 
   // this is to readout the expected responses
-  fifo_v2 #(
+  fifo_v3 #(
     .DATA_WIDTH(64),
     .DEPTH(3)
   ) i_stimuli_fifo (
@@ -234,8 +232,7 @@ module mem_emul #(
     .testmode_i  ( 1'b0          ),
     .full_o      ( stim_full_o   ),
     .empty_o     ( exp_empty     ),
-    .alm_full_o  (               ),
-    .alm_empty_o (               ),
+    .usage_o     (               ),
     .data_i      ( stim_vaddr_i  ),
     .push_i      ( stim_push_i   ),
     .data_o      ( stim_addr     ),
diff --git a/tb/tb_wt_icache/tb.list b/tb/tb_wt_icache/tb.list
index 7b1327f65b7778299a137b84c6ef07667f5bf7ac..3415a645453880627283972a1c82016f6af300c6 100644
--- a/tb/tb_wt_icache/tb.list
+++ b/tb/tb_wt_icache/tb.list
@@ -5,7 +5,6 @@
 ../../src/fpga-support/rtl/SyncSpRamBeNx64.sv
 ../../src/cache_subsystem/wt_icache.sv
 ../../src/common_cells/src/lfsr_8bit.sv
-../../src/common_cells/src/fifo_v2.sv
 ../../src/common_cells/src/fifo_v3.sv
 ../../src/common_cells/src/lzc.sv
 ../../src/util/sram.sv