From 98a16adfbe6b82d2c61b4a8a238fd0baaff3fb2a Mon Sep 17 00:00:00 2001
From: Alban Gruin <alban.gruin@irit.fr>
Date: Mon, 28 Feb 2022 22:50:09 +0100
Subject: [PATCH] controller: force D$ and BP flush on fence.i instructions
Signed-off-by: Alban Gruin <alban.gruin@irit.fr>
---
src/controller.sv | 12 ++++--------
1 file changed, 4 insertions(+), 8 deletions(-)
diff --git a/src/controller.sv b/src/controller.sv
index 6e8a1dc2..ef40190d 100644
--- a/src/controller.sv
+++ b/src/controller.sv
@@ -97,17 +97,13 @@ module controller import ariane_pkg::*; (
flush_id_o = 1'b1;
flush_ex_o = 1'b1;
flush_icache_o = 1'b1;
-// this is not needed in the case since we
-// have a write-through cache in this case
-`ifndef WT_DCACHE
+ // Force D$ flushing to avoid issues on the FPGA.
flush_dcache = 1'b1;
fence_active_d = 1'b1;
-`endif
+
+ flush_bp_o = 1'b1;
end
-// this is not needed in the case since we
-// have a write-through cache in this case
-`ifndef WT_DCACHE
// wait for the acknowledge here
if (flush_dcache_ack_i && fence_active_q) begin
fence_active_d = 1'b0;
@@ -115,7 +111,7 @@ module controller import ariane_pkg::*; (
end else if (fence_active_q) begin
flush_dcache = 1'b1;
end
-`endif
+
// ---------------------------------
// SFENCE.VMA
// ---------------------------------
--
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