From 9c5b7c939843b73fc294489f95d6c218c67fa0f6 Mon Sep 17 00:00:00 2001
From: sjthales <sebastien.jacq@thalesgroup.com>
Date: Fri, 4 Dec 2020 11:46:48 +0100
Subject: [PATCH] update to implement cv32a6 on zybo z7-20 board

---
 bench/bsp/config/fpga_platform_config.h | 2 +-
 bench/bsp/config/link.ld                | 2 +-
 2 files changed, 2 insertions(+), 2 deletions(-)

diff --git a/bench/bsp/config/fpga_platform_config.h b/bench/bsp/config/fpga_platform_config.h
index 6c11bb82..e0bd0d49 100644
--- a/bench/bsp/config/fpga_platform_config.h
+++ b/bench/bsp/config/fpga_platform_config.h
@@ -35,7 +35,7 @@
  * Platform frequency
  */
 
-#define FPGA_UART_0_FREQUENCY 50000000
+#define FPGA_UART_0_FREQUENCY 25000000
 
 
 /***************************************************************************//**
diff --git a/bench/bsp/config/link.ld b/bench/bsp/config/link.ld
index fa397107..5856d17a 100644
--- a/bench/bsp/config/link.ld
+++ b/bench/bsp/config/link.ld
@@ -32,7 +32,7 @@ MEMORY
 	   allowing initialized sections to be placed there). Infact we dump all
 	   sections to ram. */
 
-	ram (rwxai) : ORIGIN = 0x80000000, LENGTH = 0x40000
+	ram (rwxai) : ORIGIN = 0x80000000, LENGTH = 0x20000
 	dbg (rwxai) : ORIGIN = 0x1A110800, LENGTH = 0x1000
 }
 
-- 
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