diff --git a/Makefile b/Makefile
index f83eaffdf4dbe67d3f3cb2747a569ddb63b809dc..dc105cc1717f9fbfab739f7077aa0d172fd05a35 100644
--- a/Makefile
+++ b/Makefile
@@ -28,6 +28,8 @@ test-location ?= output/test
torture-logs :=
# custom elf bin to run with sim or sim-verilator
elf-bin ?= tmp/riscv-tests/build/benchmarks/dhrystone.riscv
+# board name for bitstream generation. Currently supported: kc705, genesys2
+BOARD ?= genesys2
# root path
mkfile_path := $(abspath $(lastword $(MAKEFILE_LIST)))
root-dir := $(dir $(mkfile_path))
@@ -41,6 +43,19 @@ ifndef RISCV
$(error RISCV not set - please point your RISCV variable to your RISCV installation)
endif
+# setting additional xilinx board parameters for the selected board
+ifeq ($(BOARD), genesys2)
+ XILINX_PART := xc7k325tffg900-2
+ XILINX_BOARD := digilentinc.com:genesys2:part0:1.1
+ CLK_PERIOD_NS := 20
+else ifeq ($(BOARD), kc705)
+ XILINX_PART := xc7k325tffg900-2
+ XILINX_BOARD := xilinx.com:kc705:part0:1.5
+ CLK_PERIOD_NS := 20
+else
+$(error Unknown board - please specify a supported FPGA board)
+endif
+
# spike tandem verification
ifdef spike-tandem
compile_flag += -define SPIKE_TANDEM
@@ -503,7 +518,7 @@ fpga: $(ariane_pkg) $(util) $(src) $(fpga_src) $(uart_src)
@echo read_verilog -sv {$(filter-out $(fpga_filter), $(src))} >> fpga/scripts/add_sources.tcl
@echo read_verilog -sv {$(fpga_src)} >> fpga/scripts/add_sources.tcl
@echo "[FPGA] Generate Bitstream"
- cd fpga && make BOARD="genesys2" XILINX_PART="xc7k325tffg900-2" XILINX_BOARD="digilentinc.com:genesys2:part0:1.1" CLK_PERIOD_NS="20"
+ cd fpga && make BOARD=$(BOARD) XILINX_PART=$(XILINX_PART) XILINX_BOARD=$(XILINX_BOARD) CLK_PERIOD_NS=$(CLK_PERIOD_NS)
.PHONY: fpga
@@ -522,4 +537,3 @@ clean:
check-benchmarks check-asm-tests \
torture-gen torture-itest torture-rtest \
run-torture run-torture-verilator check-torture check-torture-verilator
-
diff --git a/fpga/constraints/kc705.xdc b/fpga/constraints/kc705.xdc
new file mode 100644
index 0000000000000000000000000000000000000000..833a1b6a5013d4d9217d71bb36bc1f0e06dd08ab
--- /dev/null
+++ b/fpga/constraints/kc705.xdc
@@ -0,0 +1,203 @@
+## Buttons
+set_property -dict {PACKAGE_PIN AB7 IOSTANDARD LVCMOS15} [get_ports cpu_reset]
+set_property slave_banks {32 34} [get_iobanks 33]
+
+# on board differential clock, 200MHz
+set_property PACKAGE_PIN AD12 [get_ports sys_clk_p]
+set_property PACKAGE_PIN AD11 [get_ports sys_clk_n]
+set_property IOSTANDARD DIFF_SSTL15 [get_ports sys_clk_n]
+
+
+## To use FTDI FT2232 JTAG
+# Reset Not connected because optional?
+set_property -dict { PACKAGE_PIN D29 IOSTANDARD LVCMOS33 } [get_ports { tck }];
+set_property -dict { PACKAGE_PIN G27 IOSTANDARD LVCMOS33 } [get_ports { trst_n }];
+set_property -dict { PACKAGE_PIN C29 IOSTANDARD LVCMOS33 } [get_ports { tdo }];
+set_property -dict { PACKAGE_PIN A25 IOSTANDARD LVCMOS33 } [get_ports { tdi }];
+set_property -dict { PACKAGE_PIN B28 IOSTANDARD LVCMOS33 } [get_ports { tms }];
+set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets tck_IBUF]
+
+## UART
+set_property -dict {PACKAGE_PIN K24 IOSTANDARD LVCMOS25} [get_ports tx]
+set_property -dict {PACKAGE_PIN M19 IOSTANDARD LVCMOS25} [get_ports rx]
+
+
+## LEDs
+# set_property -dict {PACKAGE_PIN DS4 IOSTANDARD LVCMOS25} [get_ports {led[0]}]
+# set_property -dict {PACKAGE_PIN DS1 IOSTANDARD LVCMOS25} [get_ports {led[1]}]
+# set_property -dict {PACKAGE_PIN DS10 IOSTANDARD LVCMOS25} [get_ports {led[2]}]
+# set_property -dict {PACKAGE_PIN DS2 IOSTANDARD LVCMOS25} [get_ports {led[3]}]
+# set_property -dict {PACKAGE_PIN DS3 IOSTANDARD LVCMOS25} [get_ports {led[4]}]
+# set_property -dict {PACKAGE_PIN DS25 IOSTANDARD LVCMOS25} [get_ports {led[5]}]
+# set_property -dict {PACKAGE_PIN DS26 IOSTANDARD LVCMOS25} [get_ports {led[6]}]
+# set_property -dict {PACKAGE_PIN DS27 IOSTANDARD LVCMOS25} [get_ports {led[7]}]
+
+#set_property IOSTANDARD LVCMOS15 [get_ports {led[0]}]
+#set_property SLEW SLOW [get_ports {led[0]}]
+#set_property DRIVE 4 [get_ports {led[0]}]
+#set_property LOC AB8 [get_ports {led[0]}]
+#set_property IOSTANDARD LVCMOS15 [get_ports {led[1]}]
+#set_property SLEW SLOW [get_ports {led[1]}]
+#set_property DRIVE 4 [get_ports {led[1]}]
+#set_property LOC AA8 [get_ports {led[1]}]
+#set_property IOSTANDARD LVCMOS15 [get_ports {led[2]}]
+#set_property SLEW SLOW [get_ports {led[2]}]
+#set_property DRIVE 4 [get_ports {led[2]}]
+#set_property LOC AC9 [get_ports {led[2]}]
+#set_property IOSTANDARD LVCMOS15 [get_ports {led[3]}]
+#set_property SLEW SLOW [get_ports {led[3]}]
+#set_property DRIVE 4 [get_ports {led[3]}]
+#set_property LOC AB9 [get_ports {led[3]}]
+#set_property IOSTANDARD LVCMOS25 [get_ports {led[4]}]
+#set_property SLEW SLOW [get_ports {led[4]}]
+#set_property DRIVE 4 [get_ports {led[4]}]
+#set_property LOC AE26 [get_ports {led[4]}]
+#set_property IOSTANDARD LVCMOS25 [get_ports {led[5]}]
+#set_property SLEW SLOW [get_ports {led[5]}]
+#set_property DRIVE 4 [get_ports {led[5]}]
+#set_property LOC G19 [get_ports {led[5]}]
+#set_property IOSTANDARD LVCMOS25 [get_ports {led[6]}]
+#set_property SLEW SLOW [get_ports {led[6]}]
+#set_property DRIVE 4 [get_ports {led[6]}]
+#set_property LOC E18 [get_ports {led[6]}]
+#set_property IOSTANDARD LVCMOS25 [get_ports {led[7]}]
+#set_property SLEW SLOW [get_ports {led[7]}]
+#set_property DRIVE 4 [get_ports {led[7]}]
+#set_property LOC F16 [get_ports {led[7]}]
+
+set_property IOSTANDARD LVCMOS25 [get_ports {led[0]}]
+set_property SLEW SLOW [get_ports {led[0]}]
+set_property DRIVE 4 [get_ports {led[0]}]
+set_property LOC AE26 [get_ports {led[0]}]
+set_property IOSTANDARD LVCMOS25 [get_ports {led[1]}]
+set_property SLEW SLOW [get_ports {led[1]}]
+set_property DRIVE 4 [get_ports {led[1]}]
+set_property LOC G19 [get_ports {led[1]}]
+set_property IOSTANDARD LVCMOS25 [get_ports {led[2]}]
+set_property SLEW SLOW [get_ports {led[2]}]
+set_property DRIVE 4 [get_ports {led[2]}]
+set_property LOC E18 [get_ports {led[2]}]
+set_property IOSTANDARD LVCMOS25 [get_ports {led[3]}]
+set_property SLEW SLOW [get_ports {led[3]}]
+set_property DRIVE 4 [get_ports {led[3]}]
+set_property LOC F16 [get_ports {led[3]}]
+#set_property IOSTANDARD LVCMOS15 [get_ports {led[4]}]
+#set_property SLEW SLOW [get_ports {led[4]}]
+#set_property DRIVE 4 [get_ports {led[4]}]
+#set_property LOC AB8 [get_ports {led[4]}]
+#set_property IOSTANDARD LVCMOS15 [get_ports {led[5]}]
+#set_property SLEW SLOW [get_ports {led[5]}]
+#set_property DRIVE 4 [get_ports {led[5]}]
+#set_property LOC AA8 [get_ports {led[5]}]
+#set_property IOSTANDARD LVCMOS15 [get_ports {led[6]}]
+#set_property SLEW SLOW [get_ports {led[6]}]
+#set_property DRIVE 4 [get_ports {led[6]}]
+#set_property LOC AC9 [get_ports {led[6]}]
+#set_property IOSTANDARD LVCMOS15 [get_ports {led[7]}]
+#set_property SLEW SLOW [get_ports {led[7]}]
+#set_property DRIVE 4 [get_ports {led[7]}]
+#set_property LOC AB9 [get_ports {led[7]}]
+
+
+## Switches
+set_property -dict {PACKAGE_PIN Y29 IOSTANDARD LVCMOS25} [get_ports {sw[0]}]
+set_property -dict {PACKAGE_PIN W29 IOSTANDARD LVCMOS25} [get_ports {sw[1]}]
+set_property -dict {PACKAGE_PIN AA28 IOSTANDARD LVCMOS25} [get_ports {sw[2]}]
+set_property -dict {PACKAGE_PIN Y28 IOSTANDARD LVCMOS25} [get_ports {sw[3]}]
+#set_property -dict {PACKAGE_PIN N19 IOSTANDARD LVCMOS12} [get_ports {sw[4]}]
+#set_property -dict {PACKAGE_PIN P19 IOSTANDARD LVCMOS12} [get_ports {sw[5]}]
+#set_property -dict {PACKAGE_PIN P26 IOSTANDARD LVCMOS33} [get_ports {sw[6]}]
+#set_property -dict {PACKAGE_PIN P27 IOSTANDARD LVCMOS33} [get_ports {sw[7]}]
+
+## Fan Control
+set_property -dict {PACKAGE_PIN L26 IOSTANDARD LVCMOS25} [get_ports fan_pwm]
+#set_property -dict { PACKAGE_PIN U22 IOSTANDARD LVCMOS33 } [get_ports { FAN_TACH }]; #IO_L22P_T3_A05_D21_14 Sch=fan_tac
+
+## Ethernet
+set_property -dict {PACKAGE_PIN L20 IOSTANDARD LVCMOS25} [get_ports { eth_rst_n }]; #IO_L14N_T2_SRCC_12 Sch=eth_phyrst_n
+set_property -dict {PACKAGE_PIN M28 IOSTANDARD LVCMOS25} [get_ports { eth_txck }]; #IO_L14P_T2_SRCC_33 Sch=eth_tx_clk
+set_property -dict {PACKAGE_PIN M27 IOSTANDARD LVCMOS25} [get_ports { eth_txctl }]; #IO_L20P_T3_33 Sch=eth_tx_en
+set_property -dict {PACKAGE_PIN N27 IOSTANDARD LVCMOS25} [get_ports { eth_txd[0] }]; #IO_L22N_T3_33 Sch=eth_tx_d[0]
+set_property -dict {PACKAGE_PIN N25 IOSTANDARD LVCMOS25} [get_ports { eth_txd[1] }]; #IO_L17P_T2_33 Sch=eth_tx_d[1]
+set_property -dict {PACKAGE_PIN M29 IOSTANDARD LVCMOS25} [get_ports { eth_txd[2] }]; #IO_L18N_T2_33 Sch=eth_tx_d[2]
+set_property -dict {PACKAGE_PIN L28 IOSTANDARD LVCMOS25} [get_ports { eth_txd[3] }]; #IO_L17N_T2_33 Sch=eth_tx_d[3]
+set_property -dict {PACKAGE_PIN U30 IOSTANDARD LVCMOS25} [get_ports { eth_rxd[0] }]; #IO_L21N_T3_DQS_33 Sch=eth_rx_d[0]
+set_property -dict {PACKAGE_PIN U27 IOSTANDARD LVCMOS25} [get_ports { eth_rxck }]; #IO_L13P_T2_MRCC_33 Sch=eth_rx_clk
+set_property -dict {PACKAGE_PIN V26 IOSTANDARD LVCMOS25} [get_ports { eth_rxctl }]; #IO_L18P_T2_33 Sch=eth_rx_ctl
+set_property -dict {PACKAGE_PIN U25 IOSTANDARD LVCMOS25} [get_ports { eth_rxd[1] }]; #IO_L21P_T3_DQS_33 Sch=eth_rx_d[1]
+set_property -dict {PACKAGE_PIN T25 IOSTANDARD LVCMOS25} [get_ports { eth_rxd[2] }]; #IO_L20N_T3_33 Sch=eth_rx_d[2]
+set_property -dict {PACKAGE_PIN U28 IOSTANDARD LVCMOS25} [get_ports { eth_rxd[3] }]; #IO_L22P_T3_33 Sch=eth_rx_d[3]
+set_property -dict {PACKAGE_PIN R23 IOSTANDARD LVCMOS25} [get_ports { eth_mdc }]; #IO_L23P_T3_33 Sch=eth_mdc
+set_property -dict {PACKAGE_PIN J21 IOSTANDARD LVCMOS25} [get_ports { eth_mdio }]; #IO_L23N_T3_33 Sch=eth_mdio
+
+# set_property -dict {PACKAGE_PIN AK15 IOSTANDARD LVCMOS18} [get_ports { eth_pme_b }]; #IO_L1N_T0_32 Sch=eth_pmeb
+# set_property -dict {PACKAGE_PIN AK16 IOSTANDARD LVCMOS18} [get_ports { eth_int_b }]; #IO_L1P_T0_32 Sch=eth_intb
+
+#############################################
+# Ethernet Constraints for 1Gb/s
+#############################################
+# Modified for 125MHz receive clock
+create_clock -period 8.000 -name eth_rxck [get_ports eth_rxck]
+
+set_clock_groups -asynchronous -group [get_clocks eth_rxck -include_generated_clocks]
+set_clock_groups -asynchronous -group [get_clocks clk_out2_xlnx_clk_gen]
+
+#############################################
+## SD Card
+#############################################
+set_property -dict {PACKAGE_PIN AB23 IOSTANDARD LVCMOS25} [get_ports spi_clk_o]
+set_property -dict {PACKAGE_PIN AC21 IOSTANDARD LVCMOS25} [get_ports spi_ss]
+set_property -dict {PACKAGE_PIN AC20 IOSTANDARD LVCMOS25} [get_ports spi_miso]
+set_property -dict {PACKAGE_PIN AB22 IOSTANDARD LVCMOS25} [get_ports spi_mosi]
+# set_property -dict { PACKAGE_PIN P28 IOSTANDARD LVCMOS33 } [get_ports { sd_cd }]; #IO_L8N_T1_D12_14 Sch=sd_cd
+# set_property -dict { PACKAGE_PIN R29 IOSTANDARD LVCMOS33 } [get_ports { sd_cmd }]; #IO_L7N_T1_D10_14 Sch=sd_cmd
+# set_property -dict { PACKAGE_PIN R26 IOSTANDARD LVCMOS33 } [get_ports { sd_dat[0] }]; #IO_L10N_T1_D15_14 Sch=sd_dat[0]
+# set_property -dict { PACKAGE_PIN R30 IOSTANDARD LVCMOS33 } [get_ports { sd_dat[1] }]; #IO_L9P_T1_DQS_14 Sch=sd_dat[1]
+# set_property -dict { PACKAGE_PIN P29 IOSTANDARD LVCMOS33 } [get_ports { sd_dat[2] }]; #IO_L7P_T1_D09_14 Sch=sd_dat[2]
+# set_property -dict { PACKAGE_PIN T30 IOSTANDARD LVCMOS33 } [get_ports { sd_dat[3] }]; #IO_L9N_T1_DQS_D13_14 Sch=sd_dat[3]
+# set_property -dict { PACKAGE_PIN AE24 IOSTANDARD LVCMOS33 } [get_ports { sd_reset }]; #IO_L12N_T1_MRCC_12 Sch=sd_reset
+# set_property -dict { PACKAGE_PIN R28 IOSTANDARD LVCMOS33 } [get_ports { sd_clk }]; #IO_L11P_T1_SRCC_14 Sch=sd_sclk
+
+# create_generated_clock -name sd_fast_clk -source [get_pins clk_mmcm/sd_sys_clk] -divide_by 2 [get_pins chipset_impl/piton_sd_top/sdc_controller/clock_divider0/fast_clk_reg/Q]
+# create_generated_clock -name sd_slow_clk -source [get_pins clk_mmcm/sd_sys_clk] -divide_by 200 [get_pins chipset_impl/piton_sd_top/sdc_controller/clock_divider0/slow_clk_reg/Q]
+# create_generated_clock -name sd_clk_out -source [get_pins sd_clk_oddr/C] -divide_by 1 -add -master_clock sd_fast_clk [get_ports sd_clk_out]
+# create_generated_clock -name sd_clk_out_1 -source [get_pins sd_clk_oddr/C] -divide_by 1 -add -master_clock sd_slow_clk [get_ports sd_clk_out]
+
+# create_clock -period 40.000 -name VIRTUAL_sd_fast_clk -waveform {0.000 20.000}
+# create_clock -period 4000.000 -name VIRTUAL_sd_slow_clk -waveform {0.000 2000.000}
+
+# set_output_delay -clock [get_clocks sd_clk_out] -min -add_delay 5.000 [get_ports {sd_dat[*]}]
+# set_output_delay -clock [get_clocks sd_clk_out] -max -add_delay 15.000 [get_ports {sd_dat[*]}]
+# set_output_delay -clock [get_clocks sd_clk_out_1] -min -add_delay 5.000 [get_ports {sd_dat[*]}]
+# set_output_delay -clock [get_clocks sd_clk_out_1] -max -add_delay 1500.000 [get_ports {sd_dat[*]}]
+# set_output_delay -clock [get_clocks sd_clk_out] -min -add_delay 5.000 [get_ports sd_cmd]
+# set_output_delay -clock [get_clocks sd_clk_out] -max -add_delay 15.000 [get_ports sd_cmd]
+# set_output_delay -clock [get_clocks sd_clk_out_1] -min -add_delay 5.000 [get_ports sd_cmd]
+# set_output_delay -clock [get_clocks sd_clk_out_1] -max -add_delay 1500.000 [get_ports sd_cmd]
+# set_input_delay -clock [get_clocks VIRTUAL_sd_fast_clk] -min -add_delay 20.000 [get_ports {sd_dat[*]}]
+# set_input_delay -clock [get_clocks VIRTUAL_sd_fast_clk] -max -add_delay 35.000 [get_ports {sd_dat[*]}]
+# set_input_delay -clock [get_clocks VIRTUAL_sd_slow_clk] -min -add_delay 2000.000 [get_ports {sd_dat[*]}]
+# set_input_delay -clock [get_clocks VIRTUAL_sd_slow_clk] -max -add_delay 3500.000 [get_ports {sd_dat[*]}]
+# set_input_delay -clock [get_clocks VIRTUAL_sd_fast_clk] -min -add_delay 20.000 [get_ports sd_cmd]
+# set_input_delay -clock [get_clocks VIRTUAL_sd_fast_clk] -max -add_delay 35.000 [get_ports sd_cmd]
+# set_input_delay -clock [get_clocks VIRTUAL_sd_slow_clk] -min -add_delay 2000.000 [get_ports sd_cmd]
+# set_input_delay -clock [get_clocks VIRTUAL_sd_slow_clk] -max -add_delay 3500.000 [get_ports sd_cmd]
+# set_clock_groups -physically_exclusive -group [get_clocks -include_generated_clocks sd_clk_out] -group [get_clocks -include_generated_clocks sd_clk_out_1]
+# set_clock_groups -logically_exclusive -group [get_clocks -include_generated_clocks {VIRTUAL_sd_fast_clk sd_fast_clk}] -group [get_clocks -include_generated_clocks {sd_slow_clk VIRTUAL_sd_slow_clk}]
+# set_clock_groups -asynchronous -group [get_clocks [list [get_clocks -of_objects [get_pins clk_mmcm/chipset_clk]]]] -group [get_clocks -filter { NAME =~ "*sd*" }]
+
+
+# Genesys 2 has a quad SPI flash
+set_property BITSTREAM.CONFIG.SPI_BUSWIDTH 4 [current_design]
+
+## JTAG
+# minimize routing delay
+
+set_max_delay -to [get_ports { tdo } ] 20
+set_max_delay -from [get_ports { tms } ] 20
+set_max_delay -from [get_ports { tdi } ] 20
+set_max_delay -from [get_ports { trst_n } ] 20
+
+# reset signal
+set_false_path -from [get_ports { trst_n } ]
+set_false_path -from [get_pins i_ddr/u_xlnx_mig_7_ddr3_mig/u_ddr3_infrastructure/rstdiv0_sync_r1_reg_rep/C]
diff --git a/fpga/scripts/run.tcl b/fpga/scripts/run.tcl
index d85cc23e6f2976dcb9a97a2f8acf1eb6438e1f92..a3bb14c147337f8ca678c2b383617b226a322d65 100644
--- a/fpga/scripts/run.tcl
+++ b/fpga/scripts/run.tcl
@@ -15,7 +15,14 @@
# Author: Florian Zaruba <zarubaf@iis.ee.ethz.ch>
# hard-coded to Genesys 2 for the moment
-add_files -fileset constrs_1 -norecurse constraints/genesys-2.xdc
+
+if {$::env(BOARD) eq "genesys2"} {
+ add_files -fileset constrs_1 -norecurse constraints/genesys-2.xdc
+} elseif {$::env(BOARD) eq "kc705"} {
+ add_files -fileset constrs_1 -norecurse constraints/kc705.xdc
+} else {
+ exit 1
+}
read_ip xilinx/xlnx_mig_7_ddr3/ip/xlnx_mig_7_ddr3.xci
read_ip xilinx/xlnx_axi_clock_converter/ip/xlnx_axi_clock_converter.xci
@@ -35,6 +42,10 @@ if {$::env(BOARD) eq "genesys2"} {
read_verilog -sv {src/genesysii.svh ../src/common_cells/include/common_cells/registers.svh}
set file "src/genesysii.svh"
set registers "../src/common_cells/include/common_cells/registers.svh"
+} elseif {$::env(BOARD) eq "kc705"} {
+ read_verilog -sv {src/kc705.svh ../src/common_cells/include/common_cells/registers.svh}
+ set file "src/kc705.svh"
+ set registers "../src/common_cells/include/common_cells/registers.svh"
} else {
exit 1
}
diff --git a/fpga/sourceme.sh b/fpga/sourceme.sh
index 5a6d15683a2ee53288ab5673956a8ecc7649d636..b35e22e1958c02543dd54ca0b45e5d186313418e 100644
--- a/fpga/sourceme.sh
+++ b/fpga/sourceme.sh
@@ -12,3 +12,11 @@ if [ "$BOARD" = "genesys2" ]; then
export XILINX_BOARD="digilentinc.com:genesys2:part0:1.1"
export CLK_PERIOD_NS="20"
fi
+
+if [ "$BOARD" = "kc705" ]; then
+ echo -n "Configuring for "
+ echo "Kintex kc705"
+ export XILINX_PART="xc7k325tffg900-2"
+ export XILINX_BOARD="xilinx.com:kc705:part0:1.5"
+ export CLK_PERIOD_NS="20"
+fi
diff --git a/fpga/src/ariane-ethernet b/fpga/src/ariane-ethernet
index 63e7644a1c498c89de603663d0d045992f539119..6a5436bf110f83ebb13119dbd82650ccd8f947c9 160000
--- a/fpga/src/ariane-ethernet
+++ b/fpga/src/ariane-ethernet
@@ -1 +1 @@
-Subproject commit 63e7644a1c498c89de603663d0d045992f539119
+Subproject commit 6a5436bf110f83ebb13119dbd82650ccd8f947c9
diff --git a/fpga/src/ariane_xilinx.sv b/fpga/src/ariane_xilinx.sv
index 8e41dd733aaa69987f79016808183dbbe8138440..8931146a8d049aac1108706b1a41685751cbc3bf 100644
--- a/fpga/src/ariane_xilinx.sv
+++ b/fpga/src/ariane_xilinx.sv
@@ -31,6 +31,7 @@ module ariane_xilinx (
output logic [ 0:0] ddr3_cs_n ,
output logic [ 3:0] ddr3_dm ,
output logic [ 0:0] ddr3_odt ,
+
output wire eth_rst_n ,
input wire eth_rxck ,
input wire eth_rxctl ,
@@ -43,6 +44,39 @@ module ariane_xilinx (
output logic [ 7:0] led ,
input logic [ 7:0] sw ,
output logic fan_pwm ,
+`elsif KC705
+ input logic sys_clk_p ,
+ input logic sys_clk_n ,
+
+ input logic cpu_reset ,
+ inout logic [63:0] ddr3_dq ,
+ inout logic [ 7:0] ddr3_dqs_n ,
+ inout logic [ 7:0] ddr3_dqs_p ,
+ output logic [13:0] ddr3_addr ,
+ output logic [ 2:0] ddr3_ba ,
+ output logic ddr3_ras_n ,
+ output logic ddr3_cas_n ,
+ output logic ddr3_we_n ,
+ output logic ddr3_reset_n,
+ output logic [ 0:0] ddr3_ck_p ,
+ output logic [ 0:0] ddr3_ck_n ,
+ output logic [ 0:0] ddr3_cke ,
+ output logic [ 0:0] ddr3_cs_n ,
+ output logic [ 7:0] ddr3_dm ,
+ output logic [ 0:0] ddr3_odt ,
+
+ output wire eth_rst_n ,
+ input wire eth_rxck ,
+ input wire eth_rxctl ,
+ input wire [3:0] eth_rxd ,
+ output wire eth_txck ,
+ output wire eth_txctl ,
+ output wire [3:0] eth_txd ,
+ inout wire eth_mdio ,
+ output logic eth_mdc ,
+ output logic [ 3:0] led ,
+ input logic [ 3:0] sw ,
+ output logic fan_pwm ,
`elsif VCU118
input wire c0_sys_clk_p , // 250 MHz Clock for DDR
input wire c0_sys_clk_n , // 250 MHz Clock for DDR
@@ -133,6 +167,8 @@ assign cpu_resetn = ~cpu_reset;
`elsif GENESYSII
logic cpu_reset;
assign cpu_reset = ~cpu_resetn;
+`elsif KC705
+assign cpu_resetn = ~cpu_reset;
`endif
logic pll_locked;
@@ -425,6 +461,11 @@ bootrom i_bootrom (
// ---------------
// Peripherals
// ---------------
+`ifdef KC705
+ logic [7:0] unused_led;
+ logic [3:0] unused_switches = 4'b0000;
+`endif
+
ariane_peripherals #(
.AxiAddrWidth ( AxiAddrWidth ),
.AxiDataWidth ( AxiDataWidth ),
@@ -432,9 +473,12 @@ ariane_peripherals #(
.AxiUserWidth ( AxiUserWidth ),
.InclUART ( 1'b1 ),
.InclGPIO ( 1'b1 ),
- `ifdef GENESYSII
+ `ifdef KINTEX7
.InclSPI ( 1'b1 ),
.InclEthernet ( 1'b1 )
+ `elsif KC705
+ .InclSPI ( 1'b1 ),
+ .InclEthernet ( 1'b0 ) // Ethernet requires RAMB16 fpga/src/ariane-ethernet/dualmem_widen8.sv to be defined
`elsif VCU118
.InclSPI ( 1'b0 ),
.InclEthernet ( 1'b0 )
@@ -467,8 +511,13 @@ ariane_peripherals #(
.spi_mosi ( spi_mosi ),
.spi_miso ( spi_miso ),
.spi_ss ( spi_ss ),
- .leds_o ( led ),
- .dip_switches_i ( sw )
+ `ifdef KC705
+ .leds_o ( {led[3:0], unused_led[7:4]}),
+ .dip_switches_i ( {sw, unused_switches} )
+ `else
+ .leds_o ( led ),
+ .dip_switches_i ( sw )
+ `endif
);
@@ -541,8 +590,6 @@ axi_riscv_atomics_wrap #(
`ifdef PROTOCOL_CHECKER
logic pc_status;
-// assign led[0] = pc_status;
-// assign led[7:1] = '0;
xlnx_protocol_checker i_xlnx_protocol_checker (
.pc_status(),
@@ -695,7 +742,7 @@ xlnx_clk_gen i_xlnx_clk_gen (
.clk_in1 ( ddr_clock_out )
);
-`ifdef GENESYSII
+`ifdef KINTEX7
fan_ctrl i_fan_ctrl (
.clk_i ( clk ),
.rst_ni ( ndmreset_n ),
diff --git a/fpga/src/genesysii.svh b/fpga/src/genesysii.svh
index abf5beeba22139244e211a21bc220e0b2f0cbb2e..cd350a9355380ea6869c5ef8fad0bdde95d48dc4 100644
--- a/fpga/src/genesysii.svh
+++ b/fpga/src/genesysii.svh
@@ -12,6 +12,8 @@
// Author: Florian Zaruba <zarubaf@iis.ee.ethz.ch>
`define GENESYSII
+// include KINTEX7 specific code (relevant for KC705, GENESYSII,...)
+`define KINTEX7
`define ARIANE_DATA_WIDTH 64
diff --git a/fpga/src/kc705.svh b/fpga/src/kc705.svh
new file mode 100644
index 0000000000000000000000000000000000000000..a66e76383d85d5640aa912b9149b926eb49474e6
--- /dev/null
+++ b/fpga/src/kc705.svh
@@ -0,0 +1,27 @@
+// Copyright 2018 ETH Zurich and University of Bologna.
+// Copyright and related rights are licensed under the Solderpad Hardware
+// License, Version 0.51 (the "License"); you may not use this file except in
+// compliance with the License. You may obtain a copy of the License at
+// http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law
+// or agreed to in writing, software, hardware and materials distributed under
+// this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR
+// CONDITIONS OF ANY KIND, either express or implied. See the License for the
+// specific language governing permissions and limitations under the License.
+
+// Description: Set global FPGA degines
+// Author: Florian Zaruba <zarubaf@iis.ee.ethz.ch>
+
+`define KC705
+// include KINTEX7 specific code (relevant for KC705, GENESYSII,...)
+`define KINTEX7
+
+`define ARIANE_DATA_WIDTH 64
+
+// Instantiate protocl checker
+// `define PROTOCOL_CHECKER
+
+// write-back cache
+// `define WB_DCACHE
+
+// write-through cache
+`define WT_DCACHE
diff --git a/fpga/xilinx/xlnx_mig_7_ddr3/mig_kc705.prj b/fpga/xilinx/xlnx_mig_7_ddr3/mig_kc705.prj
new file mode 100644
index 0000000000000000000000000000000000000000..a523f97304f94dc6aa84222fd92d318d3a77a696
--- /dev/null
+++ b/fpga/xilinx/xlnx_mig_7_ddr3/mig_kc705.prj
@@ -0,0 +1,200 @@
+<?xml version='1.0' encoding='UTF-8'?>
+<!-- IMPORTANT: This is an internal file that has been generated by the MIG software. Any direct editing or changes made to this file may result in unpredictable behavior or data corruption. It is strongly advised that users do not edit the contents of this file. Re-run the MIG GUI with the required settings if any of the options provided below need to be altered. -->
+<Project NoOfControllers="1" >
+ <ModuleName>xlnx_mig_7_ddr3</ModuleName>
+ <dci_inouts_inputs>1</dci_inouts_inputs>
+ <dci_inputs>1</dci_inputs>
+ <Debug_En>OFF</Debug_En>
+ <DataDepth_En>1024</DataDepth_En>
+ <LowPower_En>ON</LowPower_En>
+ <XADC_En>Enabled</XADC_En>
+ <TargetFPGA>xc7k325t-ffg900/-2</TargetFPGA>
+ <Version>4.1</Version>
+ <SystemClock>Differential</SystemClock>
+ <ReferenceClock>Use System Clock</ReferenceClock>
+ <SysResetPolarity>ACTIVE LOW</SysResetPolarity>
+ <BankSelectionFlag>FALSE</BankSelectionFlag>
+ <InternalVref>0</InternalVref>
+ <dci_hr_inouts_inputs>50 Ohms</dci_hr_inouts_inputs>
+ <dci_cascade>1</dci_cascade>
+ <Controller number="0" >
+ <MemoryDevice>DDR3_SDRAM/SODIMMs/MT8JTF12864HZ-1G6</MemoryDevice>
+ <TimePeriod>1250</TimePeriod>
+ <VccAuxIO>2.0V</VccAuxIO>
+ <PHYRatio>4:1</PHYRatio>
+ <InputClkFreq>200</InputClkFreq>
+ <UIExtraClocks>0</UIExtraClocks>
+ <MMCM_VCO>800</MMCM_VCO>
+ <MMCMClkOut0>16</MMCMClkOut0>
+ <MMCMClkOut1>1</MMCMClkOut1>
+ <MMCMClkOut2>1</MMCMClkOut2>
+ <MMCMClkOut3>1</MMCMClkOut3>
+ <MMCMClkOut4>1</MMCMClkOut4>
+ <DataWidth>64</DataWidth>
+ <DeepMemory>1</DeepMemory>
+ <DataMask>1</DataMask>
+ <ECC>Disabled</ECC>
+ <Ordering>Normal</Ordering>
+ <BankMachineCnt>4</BankMachineCnt>
+ <CustomPart>FALSE</CustomPart>
+ <NewPartName></NewPartName>
+ <RowAddress>14</RowAddress>
+ <ColAddress>10</ColAddress>
+ <BankAddress>3</BankAddress>
+ <MemoryVoltage>1.5V</MemoryVoltage>
+ <UserMemoryAddressMap>BANK_ROW_COLUMN</UserMemoryAddressMap>
+ <PinSelection>
+ <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15" PADName="AH12" SLEW="" name="ddr3_addr[0]" IN_TERM="" />
+ <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15" PADName="AF13" SLEW="" name="ddr3_addr[10]" IN_TERM="" />
+ <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15" PADName="AE13" SLEW="" name="ddr3_addr[11]" IN_TERM="" />
+ <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15" PADName="AJ11" SLEW="" name="ddr3_addr[12]" IN_TERM="" />
+ <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15" PADName="AH11" SLEW="" name="ddr3_addr[13]" IN_TERM="" />
+ <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15" PADName="AG13" SLEW="" name="ddr3_addr[1]" IN_TERM="" />
+ <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15" PADName="AG12" SLEW="" name="ddr3_addr[2]" IN_TERM="" />
+ <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15" PADName="AF12" SLEW="" name="ddr3_addr[3]" IN_TERM="" />
+ <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15" PADName="AJ12" SLEW="" name="ddr3_addr[4]" IN_TERM="" />
+ <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15" PADName="AJ13" SLEW="" name="ddr3_addr[5]" IN_TERM="" />
+ <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15" PADName="AJ14" SLEW="" name="ddr3_addr[6]" IN_TERM="" />
+ <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15" PADName="AH14" SLEW="" name="ddr3_addr[7]" IN_TERM="" />
+ <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15" PADName="AK13" SLEW="" name="ddr3_addr[8]" IN_TERM="" />
+ <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15" PADName="AK14" SLEW="" name="ddr3_addr[9]" IN_TERM="" />
+ <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15" PADName="AH9" SLEW="" name="ddr3_ba[0]" IN_TERM="" />
+ <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15" PADName="AG9" SLEW="" name="ddr3_ba[1]" IN_TERM="" />
+ <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15" PADName="AK9" SLEW="" name="ddr3_ba[2]" IN_TERM="" />
+ <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15" PADName="AC11" SLEW="" name="ddr3_cas_n" IN_TERM="" />
+ <Pin VCCAUX_IO="HIGH" IOSTANDARD="DIFF_SSTL15" PADName="AH10" SLEW="" name="ddr3_ck_n[0]" IN_TERM="" />
+ <Pin VCCAUX_IO="HIGH" IOSTANDARD="DIFF_SSTL15" PADName="AG10" SLEW="" name="ddr3_ck_p[0]" IN_TERM="" />
+ <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15" PADName="AF10" SLEW="" name="ddr3_cke[0]" IN_TERM="" />
+ <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15" PADName="AC12" SLEW="" name="ddr3_cs_n[0]" IN_TERM="" />
+ <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15" PADName="Y16" SLEW="" name="ddr3_dm[0]" IN_TERM="" />
+ <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15" PADName="AB17" SLEW="" name="ddr3_dm[1]" IN_TERM="" />
+ <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15" PADName="AF17" SLEW="" name="ddr3_dm[2]" IN_TERM="" />
+ <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15" PADName="AE16" SLEW="" name="ddr3_dm[3]" IN_TERM="" />
+ <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15" PADName="AK5" SLEW="" name="ddr3_dm[4]" IN_TERM="" />
+ <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15" PADName="AJ3" SLEW="" name="ddr3_dm[5]" IN_TERM="" />
+ <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15" PADName="AF6" SLEW="" name="ddr3_dm[6]" IN_TERM="" />
+ <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15" PADName="AC7" SLEW="" name="ddr3_dm[7]" IN_TERM="" />
+ <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="AA15" SLEW="" name="ddr3_dq[0]" IN_TERM="" />
+ <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="AC19" SLEW="" name="ddr3_dq[10]" IN_TERM="" />
+ <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="AD17" SLEW="" name="ddr3_dq[11]" IN_TERM="" />
+ <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="AA18" SLEW="" name="ddr3_dq[12]" IN_TERM="" />
+ <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="AB18" SLEW="" name="ddr3_dq[13]" IN_TERM="" />
+ <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="AE18" SLEW="" name="ddr3_dq[14]" IN_TERM="" />
+ <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="AD18" SLEW="" name="ddr3_dq[15]" IN_TERM="" />
+ <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="AG19" SLEW="" name="ddr3_dq[16]" IN_TERM="" />
+ <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="AK19" SLEW="" name="ddr3_dq[17]" IN_TERM="" />
+ <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="AG18" SLEW="" name="ddr3_dq[18]" IN_TERM="" />
+ <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="AF18" SLEW="" name="ddr3_dq[19]" IN_TERM="" />
+ <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="AA16" SLEW="" name="ddr3_dq[1]" IN_TERM="" />
+ <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="AH19" SLEW="" name="ddr3_dq[20]" IN_TERM="" />
+ <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="AJ19" SLEW="" name="ddr3_dq[21]" IN_TERM="" />
+ <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="AE19" SLEW="" name="ddr3_dq[22]" IN_TERM="" />
+ <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="AD19" SLEW="" name="ddr3_dq[23]" IN_TERM="" />
+ <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="AK16" SLEW="" name="ddr3_dq[24]" IN_TERM="" />
+ <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="AJ17" SLEW="" name="ddr3_dq[25]" IN_TERM="" />
+ <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="AG15" SLEW="" name="ddr3_dq[26]" IN_TERM="" />
+ <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="AF15" SLEW="" name="ddr3_dq[27]" IN_TERM="" />
+ <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="AH17" SLEW="" name="ddr3_dq[28]" IN_TERM="" />
+ <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="AG14" SLEW="" name="ddr3_dq[29]" IN_TERM="" />
+ <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="AC14" SLEW="" name="ddr3_dq[2]" IN_TERM="" />
+ <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="AH15" SLEW="" name="ddr3_dq[30]" IN_TERM="" />
+ <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="AK15" SLEW="" name="ddr3_dq[31]" IN_TERM="" />
+ <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="AK8" SLEW="" name="ddr3_dq[32]" IN_TERM="" />
+ <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="AK6" SLEW="" name="ddr3_dq[33]" IN_TERM="" />
+ <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="AG7" SLEW="" name="ddr3_dq[34]" IN_TERM="" />
+ <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="AF7" SLEW="" name="ddr3_dq[35]" IN_TERM="" />
+ <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="AF8" SLEW="" name="ddr3_dq[36]" IN_TERM="" />
+ <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="AK4" SLEW="" name="ddr3_dq[37]" IN_TERM="" />
+ <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="AJ8" SLEW="" name="ddr3_dq[38]" IN_TERM="" />
+ <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="AJ6" SLEW="" name="ddr3_dq[39]" IN_TERM="" />
+ <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="AD14" SLEW="" name="ddr3_dq[3]" IN_TERM="" />
+ <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="AH5" SLEW="" name="ddr3_dq[40]" IN_TERM="" />
+ <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="AH6" SLEW="" name="ddr3_dq[41]" IN_TERM="" />
+ <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="AJ2" SLEW="" name="ddr3_dq[42]" IN_TERM="" />
+ <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="AH2" SLEW="" name="ddr3_dq[43]" IN_TERM="" />
+ <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="AH4" SLEW="" name="ddr3_dq[44]" IN_TERM="" />
+ <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="AJ4" SLEW="" name="ddr3_dq[45]" IN_TERM="" />
+ <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="AK1" SLEW="" name="ddr3_dq[46]" IN_TERM="" />
+ <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="AJ1" SLEW="" name="ddr3_dq[47]" IN_TERM="" />
+ <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="AF1" SLEW="" name="ddr3_dq[48]" IN_TERM="" />
+ <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="AF2" SLEW="" name="ddr3_dq[49]" IN_TERM="" />
+ <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="AA17" SLEW="" name="ddr3_dq[4]" IN_TERM="" />
+ <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="AE4" SLEW="" name="ddr3_dq[50]" IN_TERM="" />
+ <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="AE3" SLEW="" name="ddr3_dq[51]" IN_TERM="" />
+ <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="AF3" SLEW="" name="ddr3_dq[52]" IN_TERM="" />
+ <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="AF5" SLEW="" name="ddr3_dq[53]" IN_TERM="" />
+ <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="AE1" SLEW="" name="ddr3_dq[54]" IN_TERM="" />
+ <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="AE5" SLEW="" name="ddr3_dq[55]" IN_TERM="" />
+ <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="AC1" SLEW="" name="ddr3_dq[56]" IN_TERM="" />
+ <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="AD3" SLEW="" name="ddr3_dq[57]" IN_TERM="" />
+ <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="AC4" SLEW="" name="ddr3_dq[58]" IN_TERM="" />
+ <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="AC5" SLEW="" name="ddr3_dq[59]" IN_TERM="" />
+ <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="AB15" SLEW="" name="ddr3_dq[5]" IN_TERM="" />
+ <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="AE6" SLEW="" name="ddr3_dq[60]" IN_TERM="" />
+ <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="AD6" SLEW="" name="ddr3_dq[61]" IN_TERM="" />
+ <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="AC2" SLEW="" name="ddr3_dq[62]" IN_TERM="" />
+ <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="AD4" SLEW="" name="ddr3_dq[63]" IN_TERM="" />
+ <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="AE15" SLEW="" name="ddr3_dq[6]" IN_TERM="" />
+ <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="Y15" SLEW="" name="ddr3_dq[7]" IN_TERM="" />
+ <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="AB19" SLEW="" name="ddr3_dq[8]" IN_TERM="" />
+ <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="AD16" SLEW="" name="ddr3_dq[9]" IN_TERM="" />
+ <Pin VCCAUX_IO="HIGH" IOSTANDARD="DIFF_SSTL15_T_DCI" PADName="AC15" SLEW="" name="ddr3_dqs_n[0]" IN_TERM="" />
+ <Pin VCCAUX_IO="HIGH" IOSTANDARD="DIFF_SSTL15_T_DCI" PADName="Y18" SLEW="" name="ddr3_dqs_n[1]" IN_TERM="" />
+ <Pin VCCAUX_IO="HIGH" IOSTANDARD="DIFF_SSTL15_T_DCI" PADName="AK18" SLEW="" name="ddr3_dqs_n[2]" IN_TERM="" />
+ <Pin VCCAUX_IO="HIGH" IOSTANDARD="DIFF_SSTL15_T_DCI" PADName="AJ16" SLEW="" name="ddr3_dqs_n[3]" IN_TERM="" />
+ <Pin VCCAUX_IO="HIGH" IOSTANDARD="DIFF_SSTL15_T_DCI" PADName="AJ7" SLEW="" name="ddr3_dqs_n[4]" IN_TERM="" />
+ <Pin VCCAUX_IO="HIGH" IOSTANDARD="DIFF_SSTL15_T_DCI" PADName="AH1" SLEW="" name="ddr3_dqs_n[5]" IN_TERM="" />
+ <Pin VCCAUX_IO="HIGH" IOSTANDARD="DIFF_SSTL15_T_DCI" PADName="AG3" SLEW="" name="ddr3_dqs_n[6]" IN_TERM="" />
+ <Pin VCCAUX_IO="HIGH" IOSTANDARD="DIFF_SSTL15_T_DCI" PADName="AD1" SLEW="" name="ddr3_dqs_n[7]" IN_TERM="" />
+ <Pin VCCAUX_IO="HIGH" IOSTANDARD="DIFF_SSTL15_T_DCI" PADName="AC16" SLEW="" name="ddr3_dqs_p[0]" IN_TERM="" />
+ <Pin VCCAUX_IO="HIGH" IOSTANDARD="DIFF_SSTL15_T_DCI" PADName="Y19" SLEW="" name="ddr3_dqs_p[1]" IN_TERM="" />
+ <Pin VCCAUX_IO="HIGH" IOSTANDARD="DIFF_SSTL15_T_DCI" PADName="AJ18" SLEW="" name="ddr3_dqs_p[2]" IN_TERM="" />
+ <Pin VCCAUX_IO="HIGH" IOSTANDARD="DIFF_SSTL15_T_DCI" PADName="AH16" SLEW="" name="ddr3_dqs_p[3]" IN_TERM="" />
+ <Pin VCCAUX_IO="HIGH" IOSTANDARD="DIFF_SSTL15_T_DCI" PADName="AH7" SLEW="" name="ddr3_dqs_p[4]" IN_TERM="" />
+ <Pin VCCAUX_IO="HIGH" IOSTANDARD="DIFF_SSTL15_T_DCI" PADName="AG2" SLEW="" name="ddr3_dqs_p[5]" IN_TERM="" />
+ <Pin VCCAUX_IO="HIGH" IOSTANDARD="DIFF_SSTL15_T_DCI" PADName="AG4" SLEW="" name="ddr3_dqs_p[6]" IN_TERM="" />
+ <Pin VCCAUX_IO="HIGH" IOSTANDARD="DIFF_SSTL15_T_DCI" PADName="AD2" SLEW="" name="ddr3_dqs_p[7]" IN_TERM="" />
+ <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15" PADName="AD8" SLEW="" name="ddr3_odt[0]" IN_TERM="" />
+ <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15" PADName="AD9" SLEW="" name="ddr3_ras_n" IN_TERM="" />
+ <Pin VCCAUX_IO="HIGH" IOSTANDARD="LVCMOS15" PADName="AK3" SLEW="" name="ddr3_reset_n" IN_TERM="" />
+ <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15" PADName="AE9" SLEW="" name="ddr3_we_n" IN_TERM="" />
+ </PinSelection>
+ <System_Control>
+ <Pin PADName="No connect" Bank="Select Bank" name="sys_rst" />
+ <Pin PADName="No connect" Bank="Select Bank" name="init_calib_complete" />
+ <Pin PADName="No connect" Bank="Select Bank" name="tg_compare_error" />
+ </System_Control>
+ <TimingParameters>
+ <Parameters twtr="7.5" trrd="6" trefi="7.8" tfaw="30" trtp="7.5" tcke="5" trfc="110" trp="13.75" tras="35" trcd="13.75" />
+ </TimingParameters>
+ <mrBurstLength name="Burst Length" >8 - Fixed</mrBurstLength>
+ <mrBurstType name="Read Burst Type and Length" >Sequential</mrBurstType>
+ <mrCasLatency name="CAS Latency" >11</mrCasLatency>
+ <mrMode name="Mode" >Normal</mrMode>
+ <mrDllReset name="DLL Reset" >No</mrDllReset>
+ <mrPdMode name="DLL control for precharge PD" >Slow Exit</mrPdMode>
+ <emrDllEnable name="DLL Enable" >Enable</emrDllEnable>
+ <emrOutputDriveStrength name="Output Driver Impedance Control" >RZQ/7</emrOutputDriveStrength>
+ <emrMirrorSelection name="Address Mirroring" >Disable</emrMirrorSelection>
+ <emrCSSelection name="Controller Chip Select Pin" >Enable</emrCSSelection>
+ <emrRTT name="RTT (nominal) - On Die Termination (ODT)" >RZQ/6</emrRTT>
+ <emrPosted name="Additive Latency (AL)" >0</emrPosted>
+ <emrOCD name="Write Leveling Enable" >Disabled</emrOCD>
+ <emrDQS name="TDQS enable" >Enabled</emrDQS>
+ <emrRDQS name="Qoff" >Output Buffer Enabled</emrRDQS>
+ <mr2PartialArraySelfRefresh name="Partial-Array Self Refresh" >Full Array</mr2PartialArraySelfRefresh>
+ <mr2CasWriteLatency name="CAS write latency" >8</mr2CasWriteLatency>
+ <mr2AutoSelfRefresh name="Auto Self Refresh" >Enabled</mr2AutoSelfRefresh>
+ <mr2SelfRefreshTempRange name="High Temparature Self Refresh Rate" >Normal</mr2SelfRefreshTempRange>
+ <mr2RTTWR name="RTT_WR - Dynamic On Die Termination (ODT)" >Dynamic ODT off</mr2RTTWR>
+ <PortInterface>AXI</PortInterface>
+ <AXIParameters>
+ <C0_C_RD_WR_ARB_ALGORITHM>RD_PRI_REG</C0_C_RD_WR_ARB_ALGORITHM>
+ <C0_S_AXI_ADDR_WIDTH>30</C0_S_AXI_ADDR_WIDTH>
+ <C0_S_AXI_DATA_WIDTH>64</C0_S_AXI_DATA_WIDTH>
+ <C0_S_AXI_ID_WIDTH>4</C0_S_AXI_ID_WIDTH>
+ <C0_S_AXI_SUPPORTS_NARROW_BURST>0</C0_S_AXI_SUPPORTS_NARROW_BURST>
+ </AXIParameters>
+ </Controller>
+
+</Project>
diff --git a/fpga/xilinx/xlnx_mig_7_ddr3/tcl/run.tcl b/fpga/xilinx/xlnx_mig_7_ddr3/tcl/run.tcl
index 324be30155755ee8916ada70fe19e65150d3d41c..bb2576009390c971052e4f6bae1e4df866d3e742 100644
--- a/fpga/xilinx/xlnx_mig_7_ddr3/tcl/run.tcl
+++ b/fpga/xilinx/xlnx_mig_7_ddr3/tcl/run.tcl
@@ -1,5 +1,6 @@
set partNumber $::env(XILINX_PART)
set boardName $::env(XILINX_BOARD)
+set boardNameShort $::env(BOARD)
set ipName xlnx_mig_7_ddr3
@@ -8,7 +9,7 @@ set_property board_part $boardName [current_project]
create_ip -name mig_7series -vendor xilinx.com -library ip -module_name $ipName
-exec cp mig_genesys2.prj ./$ipName.srcs/sources_1/ip/$ipName/mig_a.prj
+exec cp mig_$boardNameShort.prj ./$ipName.srcs/sources_1/ip/$ipName/mig_a.prj
set_property -dict [list CONFIG.XML_INPUT_FILE {mig_a.prj} CONFIG.RESET_BOARD_INTERFACE {Custom} CONFIG.MIG_DONT_TOUCH_PARAM {Custom} CONFIG.BOARD_MIG_PARAM {Custom}] [get_ips $ipName]
@@ -16,4 +17,4 @@ generate_target {instantiation_template} [get_files ./$ipName.srcs/sources_1/ip/
generate_target all [get_files ./$ipName.srcs/sources_1/ip/$ipName/$ipName.xci]
create_ip_run [get_files -of_objects [get_fileset sources_1] ./$ipName.srcs/sources_1/ip/$ipName/$ipName.xci]
launch_run -jobs 8 ${ipName}_synth_1
-wait_on_run ${ipName}_synth_1
\ No newline at end of file
+wait_on_run ${ipName}_synth_1