From acf7dc6a635b69a3d4103cc4ed080bcf55b4f77c Mon Sep 17 00:00:00 2001
From: sjthales <sebastien.jacq@thalesgroup.com>
Date: Fri, 9 Oct 2020 10:07:43 +0200
Subject: [PATCH] modification student contest
---
Makefile | 402 +-
README.md | 373 +-
fpga/Makefile | 86 +-
fpga/ariane-multi-hart.cfg | 40 -
fpga/ariane.cfg | 44 -
fpga/ariane_pmod.cfg | 30 -
fpga/ariane_pmod_tiny.cfg | 30 -
fpga/constraints/ariane.xdc | 19 -
fpga/constraints/genesys-2.xdc | 127 -
fpga/constraints/kc705.xdc | 203 -
fpga/constraints/vc707.xdc | 127 -
fpga/constraints/vcu118.xdc | 1990 ------
fpga/scripts/program.tcl | 38 -
fpga/scripts/prologue.tcl | 27 -
fpga/scripts/run.tcl | 105 -
fpga/scripts/run_cva6_ooc.tcl | 96 +
fpga/scripts/write_cfgmem.tcl | 35 -
fpga/sourceme.sh | 30 -
fpga/src/zybo-z7-20.svh | 11 +
fpga/xilinx/.gitignore | 5 -
fpga/xilinx/ariane_xlnx_ip.yml | 92 -
fpga/xilinx/common.mk | 19 -
fpga/xilinx/xlnx_axi_clock_converter/Makefile | 2 -
.../xlnx_axi_clock_converter/tcl/run.tcl | 17 -
.../xilinx/xlnx_axi_dwidth_converter/Makefile | 2 -
.../xlnx_axi_dwidth_converter/tcl/run.tcl | 17 -
fpga/xilinx/xlnx_axi_gpio/Makefile | 2 -
fpga/xilinx/xlnx_axi_gpio/tcl/run.tcl | 16 -
fpga/xilinx/xlnx_axi_quad_spi/Makefile | 2 -
fpga/xilinx/xlnx_axi_quad_spi/tcl/run.tcl | 16 -
fpga/xilinx/xlnx_clk_gen/Makefile | 2 -
fpga/xilinx/xlnx_clk_gen/tcl/run.tcl | 28 -
fpga/xilinx/xlnx_ila/Makefile | 2 -
fpga/xilinx/xlnx_ila/tcl/run.tcl | 22 -
fpga/xilinx/xlnx_mig_7_ddr3/Makefile | 2 -
fpga/xilinx/xlnx_mig_7_ddr3/mig_genesys2.prj | 160 -
fpga/xilinx/xlnx_mig_7_ddr3/mig_kc705.prj | 200 -
fpga/xilinx/xlnx_mig_7_ddr3/mig_vc707.prj | 203 -
fpga/xilinx/xlnx_mig_7_ddr3/tcl/run.tcl | 20 -
fpga/xilinx/xlnx_protocol_checker/Makefile | 2 -
fpga/xilinx/xlnx_protocol_checker/tcl/run.tcl | 35 -
include/ariane_axi_pkg.sv | 18 +-
include/ariane_pkg.sv | 5 +
include/riscv_pkg.sv | 11 +-
src/axi_adapter.sv | 6 +-
src/csr_regfile.sv | 67 +-
src/frontend/frontend.sv | 2 +-
src/issue_stage.sv | 4 +-
src/load_store_unit.sv | 100 +-
src/load_unit.sv | 2 +-
src/mmu.sv | 2 +-
src/tlb.sv | 2 +-
sw/README.md | 44 +
sw/app/Makefile | 148 +
sw/app/common/util.h | 90 +
sw/app/dhrystone/dhrystone.c | 186 +
sw/app/dhrystone/dhrystone.h | 477 ++
sw/app/dhrystone/dhrystone_main.c | 353 +
sw/app/helloworld/helloworld.c | 16 +
sw/app/helloworld_printf/helloworld_printf.c | 17 +
sw/app/median/dataset1.h | 53 +
sw/app/median/median.c | 42 +
sw/app/median/median.h | 11 +
sw/app/median/median_gendata.pl | 140 +
sw/app/median/median_main.c | 65 +
sw/app/mm/common.h | 36 +
sw/app/mm/gen.scala | 81 +
sw/app/mm/mm.c | 152 +
sw/app/mm/mm_main.c | 72 +
sw/app/mm/rb.h | 210 +
sw/app/mt-matmul/dataset.h | 63 +
sw/app/mt-matmul/matmul.c | 23 +
sw/app/mt-matmul/matmul_gendata.pl | 205 +
sw/app/mt-matmul/mt-matmul.c | 57 +
sw/app/mt-vvadd/dataset.h | 173 +
sw/app/mt-vvadd/mt-vvadd.c | 78 +
sw/app/mt-vvadd/vvadd.c | 18 +
sw/app/mt-vvadd/vvadd_gendata.pl | 139 +
sw/app/multiply/dataset1.h | 32 +
sw/app/multiply/multiply.c | 24 +
sw/app/multiply/multiply.h | 11 +
sw/app/multiply/multiply_gendata.pl | 142 +
sw/app/multiply/multiply_main.c | 66 +
sw/app/pmp/pmp.c | 198 +
sw/app/qsort/dataset1.h | 219 +
sw/app/qsort/qsort_gendata.pl | 132 +
sw/app/qsort/qsort_main.c | 175 +
sw/app/rsort/dataset1.h | 219 +
sw/app/rsort/rsort.c | 145 +
sw/app/spmv/dataset1.h | 6312 +++++++++++++++++
sw/app/spmv/spmv_gendata.scala | 48 +
sw/app/spmv/spmv_main.c | 73 +
sw/app/towers/towers_main.c | 256 +
sw/app/vvadd/dataset1-large.h | 167 +
sw/app/vvadd/dataset1.h | 62 +
sw/app/vvadd/vvadd_gendata.pl | 139 +
sw/app/vvadd/vvadd_main.c | 70 +
sw/bsp/config/fpga_platform_config.h | 48 +
sw/bsp/config/link.ld | 320 +
sw/bsp/hal/crt0.S | 75 +
sw/bsp/hal/encoding.h | 251 +
sw/bsp/hal/hal_assert.h | 19 +
sw/bsp/hal/handlers.S | 130 +
sw/bsp/hal/plic.h | 365 +
sw/bsp/hal/riscv_hal_stubs.c | 197 +
sw/bsp/hal/syscalls.c | 438 ++
sw/bsp/hal/vectors.S | 64 +
sw/utils/bin2mem.py | 60 +
tb/ariane_tb.sv | 173 +-
tb/ariane_testharness.sv | 222 +-
tb/jtag_pkg.sv | 2908 ++++++++
111 files changed, 16842 insertions(+), 4765 deletions(-)
delete mode 100644 fpga/ariane-multi-hart.cfg
delete mode 100644 fpga/ariane.cfg
delete mode 100644 fpga/ariane_pmod.cfg
delete mode 100644 fpga/ariane_pmod_tiny.cfg
delete mode 100644 fpga/constraints/ariane.xdc
delete mode 100644 fpga/constraints/genesys-2.xdc
delete mode 100644 fpga/constraints/kc705.xdc
delete mode 100644 fpga/constraints/vc707.xdc
delete mode 100644 fpga/constraints/vcu118.xdc
delete mode 100644 fpga/scripts/program.tcl
delete mode 100644 fpga/scripts/prologue.tcl
delete mode 100644 fpga/scripts/run.tcl
create mode 100644 fpga/scripts/run_cva6_ooc.tcl
delete mode 100644 fpga/scripts/write_cfgmem.tcl
delete mode 100644 fpga/sourceme.sh
create mode 100644 fpga/src/zybo-z7-20.svh
delete mode 100644 fpga/xilinx/.gitignore
delete mode 100644 fpga/xilinx/ariane_xlnx_ip.yml
delete mode 100644 fpga/xilinx/common.mk
delete mode 100644 fpga/xilinx/xlnx_axi_clock_converter/Makefile
delete mode 100644 fpga/xilinx/xlnx_axi_clock_converter/tcl/run.tcl
delete mode 100644 fpga/xilinx/xlnx_axi_dwidth_converter/Makefile
delete mode 100644 fpga/xilinx/xlnx_axi_dwidth_converter/tcl/run.tcl
delete mode 100644 fpga/xilinx/xlnx_axi_gpio/Makefile
delete mode 100644 fpga/xilinx/xlnx_axi_gpio/tcl/run.tcl
delete mode 100644 fpga/xilinx/xlnx_axi_quad_spi/Makefile
delete mode 100644 fpga/xilinx/xlnx_axi_quad_spi/tcl/run.tcl
delete mode 100644 fpga/xilinx/xlnx_clk_gen/Makefile
delete mode 100644 fpga/xilinx/xlnx_clk_gen/tcl/run.tcl
delete mode 100644 fpga/xilinx/xlnx_ila/Makefile
delete mode 100644 fpga/xilinx/xlnx_ila/tcl/run.tcl
delete mode 100644 fpga/xilinx/xlnx_mig_7_ddr3/Makefile
delete mode 100755 fpga/xilinx/xlnx_mig_7_ddr3/mig_genesys2.prj
delete mode 100644 fpga/xilinx/xlnx_mig_7_ddr3/mig_kc705.prj
delete mode 100644 fpga/xilinx/xlnx_mig_7_ddr3/mig_vc707.prj
delete mode 100644 fpga/xilinx/xlnx_mig_7_ddr3/tcl/run.tcl
delete mode 100644 fpga/xilinx/xlnx_protocol_checker/Makefile
delete mode 100644 fpga/xilinx/xlnx_protocol_checker/tcl/run.tcl
create mode 100644 sw/README.md
create mode 100755 sw/app/Makefile
create mode 100644 sw/app/common/util.h
create mode 100644 sw/app/dhrystone/dhrystone.c
create mode 100644 sw/app/dhrystone/dhrystone.h
create mode 100644 sw/app/dhrystone/dhrystone_main.c
create mode 100644 sw/app/helloworld/helloworld.c
create mode 100644 sw/app/helloworld_printf/helloworld_printf.c
create mode 100644 sw/app/median/dataset1.h
create mode 100644 sw/app/median/median.c
create mode 100644 sw/app/median/median.h
create mode 100755 sw/app/median/median_gendata.pl
create mode 100644 sw/app/median/median_main.c
create mode 100644 sw/app/mm/common.h
create mode 100644 sw/app/mm/gen.scala
create mode 100644 sw/app/mm/mm.c
create mode 100644 sw/app/mm/mm_main.c
create mode 100644 sw/app/mm/rb.h
create mode 100644 sw/app/mt-matmul/dataset.h
create mode 100644 sw/app/mt-matmul/matmul.c
create mode 100755 sw/app/mt-matmul/matmul_gendata.pl
create mode 100644 sw/app/mt-matmul/mt-matmul.c
create mode 100644 sw/app/mt-vvadd/dataset.h
create mode 100644 sw/app/mt-vvadd/mt-vvadd.c
create mode 100644 sw/app/mt-vvadd/vvadd.c
create mode 100755 sw/app/mt-vvadd/vvadd_gendata.pl
create mode 100644 sw/app/multiply/dataset1.h
create mode 100644 sw/app/multiply/multiply.c
create mode 100644 sw/app/multiply/multiply.h
create mode 100755 sw/app/multiply/multiply_gendata.pl
create mode 100644 sw/app/multiply/multiply_main.c
create mode 100644 sw/app/pmp/pmp.c
create mode 100644 sw/app/qsort/dataset1.h
create mode 100755 sw/app/qsort/qsort_gendata.pl
create mode 100644 sw/app/qsort/qsort_main.c
create mode 100644 sw/app/rsort/dataset1.h
create mode 100644 sw/app/rsort/rsort.c
create mode 100644 sw/app/spmv/dataset1.h
create mode 100644 sw/app/spmv/spmv_gendata.scala
create mode 100644 sw/app/spmv/spmv_main.c
create mode 100644 sw/app/towers/towers_main.c
create mode 100644 sw/app/vvadd/dataset1-large.h
create mode 100644 sw/app/vvadd/dataset1.h
create mode 100755 sw/app/vvadd/vvadd_gendata.pl
create mode 100644 sw/app/vvadd/vvadd_main.c
create mode 100644 sw/bsp/config/fpga_platform_config.h
create mode 100644 sw/bsp/config/link.ld
create mode 100644 sw/bsp/hal/crt0.S
create mode 100644 sw/bsp/hal/encoding.h
create mode 100644 sw/bsp/hal/hal_assert.h
create mode 100644 sw/bsp/hal/handlers.S
create mode 100644 sw/bsp/hal/plic.h
create mode 100755 sw/bsp/hal/riscv_hal_stubs.c
create mode 100644 sw/bsp/hal/syscalls.c
create mode 100644 sw/bsp/hal/vectors.S
create mode 100755 sw/utils/bin2mem.py
create mode 100644 tb/jtag_pkg.sv
diff --git a/Makefile b/Makefile
index 29d45792..2b08ebea 100644
--- a/Makefile
+++ b/Makefile
@@ -1,6 +1,27 @@
+# Copyright (c) 2020 Thales.
+#
+# Copyright and related rights are licensed under the Apache
+# License, Version 2.0 (the "License"); you may not use this file except in
+# compliance with the License. You may obtain a copy of the License at
+# https://www.apache.org/licenses/LICENSE-2.0. Unless required by applicable law
+# or agreed to in writing, software, hardware and materials distributed under
+# this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR
+# CONDITIONS OF ANY KIND, either express or implied. See the License for the
+# specific language governing permissions and limitations under the License.
+#
# Author: Florian Zaruba, ETH Zurich
# Date: 03/19/2017
+#
+# Additional contributions by:
+# Sebastien Jacq - sjthales on github.com
+#
# Description: Makefile for linting and testing Ariane.
+#
+# =========================================================================== #
+# Revisions :
+# Date Version Author Description
+# 2020-10-06 0.1 S.Jacq modification for CVA6 softcore
+# =========================================================================== #
# questa library
library ?= work
@@ -11,13 +32,13 @@ dpi-library ?= work-dpi
# Top level module to compile
top_level ?= ariane_tb
# Maximum amount of cycles for a successful simulation run
-max_cycles ?= 10000000
+max_cycles ?= 1000000000
# Test case to run
test_case ?= core_test
# QuestaSim Version
questa_version ?= ${QUESTASIM_VERSION}
# verilator version
-verilator ?= verilator
+#verilator ?= verilator
# traget option
target-options ?=
# additional definess
@@ -27,46 +48,25 @@ test-location ?= output/test
# set to either nothing or -log
torture-logs :=
# custom elf bin to run with sim or sim-verilator
-elf-bin ?= tmp/riscv-tests/build/benchmarks/dhrystone.riscv
-# board name for bitstream generation. Currently supported: kc705, genesys2
-BOARD ?= genesys2
+elf-bin ?= sw/app/benchmarks/coremark.riscv
+
+# Application to simulate
+APP ?= coremark
+
# root path
mkfile_path := $(abspath $(lastword $(MAKEFILE_LIST)))
root-dir := $(dir $(mkfile_path))
-support_verilator_4 := $(shell ($(verilator) --version | grep '4\.') &> /dev/null; echo $$?)
-ifeq ($(support_verilator_4), 0)
- verilator_threads := 2
-endif
+# software application path
+app_path := $(root-dir)/sw/app
-ifndef RISCV
-$(error RISCV not set - please point your RISCV variable to your RISCV installation)
-endif
-# setting additional xilinx board parameters for the selected board
-ifeq ($(BOARD), genesys2)
- XILINX_PART := xc7k325tffg900-2
- XILINX_BOARD := digilentinc.com:genesys2:part0:1.1
- CLK_PERIOD_NS := 20
-else ifeq ($(BOARD), kc705)
- XILINX_PART := xc7k325tffg900-2
- XILINX_BOARD := xilinx.com:kc705:part0:1.5
- CLK_PERIOD_NS := 20
-else ifeq ($(BOARD), vc707)
- XILINX_PART := xc7vx485tffg1761-2
- XILINX_BOARD := xilinx.com:vc707:part0:1.3
- CLK_PERIOD_NS := 20
-else
-$(error Unknown board - please specify a supported FPGA board)
-endif
-
-# spike tandem verification
-ifdef spike-tandem
- compile_flag += -define SPIKE_TANDEM
- ifndef preload
- $(error Tandem verification requires preloading)
- endif
-endif
+# board name for bitstream generation.
+BOARD := zybo-z7-20
+XILINX_PART := xc7z020clg400-1
+XILINX_BOARD := digilentinc.com:zybo-z7-20:part0:1.0
+CLK_PERIOD_NS := 25
+BATCH_MODE ?= 1
# Sources
# Package files -> compile first
@@ -93,9 +93,6 @@ util := include/instr_tracer_pkg.sv \
tb/common/mock_uart.sv \
src/util/sram.sv
-ifdef spike-tandem
- util += tb/common/spike.sv
-endif
util := $(addprefix $(root-dir), $(util))
# Test packages
@@ -105,28 +102,13 @@ test_pkg := $(wildcard tb/test/*/*sequence_pkg.sv*) \
# DPI
dpi := $(patsubst tb/dpi/%.cc, ${dpi-library}/%.o, $(wildcard tb/dpi/*.cc))
-# filter spike stuff if tandem is not activated
-ifndef spike-tandem
- dpi := $(filter-out ${dpi-library}/spike.o ${dpi-library}/sim_spike.o, $(dpi))
-endif
-
-# filter dromajo stuff if dromajo is not activated
-ifndef DROMAJO
- dpi := $(filter-out ${dpi-library}/dromajo_cosim_dpi.o, $(dpi))
-endif
dpi_hdr := $(wildcard tb/dpi/*.h)
dpi_hdr := $(addprefix $(root-dir), $(dpi_hdr))
CFLAGS := -I$(QUESTASIM_HOME)/include \
-I$(RISCV)/include \
- $(if $(DROMAJO), -I../tb/dromajo/src,) \
-std=c++11 -I../tb/dpi
-
-ifdef spike-tandem
- CFLAGS += -Itb/riscv-isa-sim/install/include/spike
-endif
-
# this list contains the standalone components
src := $(filter-out src/ariane_regfile.sv, $(wildcard src/*.sv)) \
$(filter-out src/fpu/src/fpnew_pkg.sv, $(wildcard src/fpu/src/*.sv)) \
@@ -214,20 +196,12 @@ fpga_src := $(wildcard fpga/src/*.sv) $(wildcard fpga/src/bootrom/*.sv) $(wildc
fpga_src := $(addprefix $(root-dir), $(fpga_src))
# look for testbenches
-tbs := tb/ariane_tb.sv tb/ariane_testharness.sv
+tbs := tb/jtag_pkg.sv tb/ariane_tb.sv tb/ariane_testharness.sv
# RISCV asm tests and benchmark setup (used for CI)
# there is a definesd test-list with selected CI tests
riscv-test-dir := tmp/riscv-tests/build/isa/
riscv-benchmarks-dir := tmp/riscv-tests/build/benchmarks/
-riscv-asm-tests-list := ci/riscv-asm-tests.list
-riscv-amo-tests-list := ci/riscv-amo-tests.list
-riscv-mul-tests-list := ci/riscv-mul-tests.list
-riscv-fp-tests-list := ci/riscv-fp-tests.list
riscv-benchmarks-list := ci/riscv-benchmarks.list
-riscv-asm-tests := $(shell xargs printf '\n%s' < $(riscv-asm-tests-list) | cut -b 1-)
-riscv-amo-tests := $(shell xargs printf '\n%s' < $(riscv-amo-tests-list) | cut -b 1-)
-riscv-mul-tests := $(shell xargs printf '\n%s' < $(riscv-mul-tests-list) | cut -b 1-)
-riscv-fp-tests := $(shell xargs printf '\n%s' < $(riscv-fp-tests-list) | cut -b 1-)
riscv-benchmarks := $(shell xargs printf '\n%s' < $(riscv-benchmarks-list) | cut -b 1-)
# Search here for include files (e.g.: non-standalone components)
@@ -242,39 +216,19 @@ compile_flag_vhd += -64 -nologo -quiet -2008
# +incdir+ works for Verilator and QuestaSim
list_incdir := $(foreach dir, ${incdir}, +incdir+$(dir))
-# RISCV torture setup
-riscv-torture-dir := tmp/riscv-torture
-# old java flags -Xmx1G -Xss8M -XX:MaxPermSize=128M
-# -XshowSettings -Xdiag
-riscv-torture-bin := java -jar sbt-launch.jar
# if defined, calls the questa targets in batch mode
ifdef batch-mode
questa-flags += -c
questa-cmd := -do "coverage save -onexit tmp/$@.ucdb; run -a; quit -code [coverage attribute -name TESTSTATUS -concise]"
- questa-cmd += -do " log -r /*; run -all;"
+ questa-cmd += -do " run -all;"
else
- questa-cmd := -do " log -r /*; run -all;"
-endif
-# we want to preload the memories
-ifdef preload
- questa-cmd += +PRELOAD=$(preload)
- elf-bin = none
-endif
-
-ifdef spike-tandem
- questa-cmd += -gblso tb/riscv-isa-sim/install/lib/libriscv.so
+ questa-cmd := -do " run -all;"
endif
-# remote bitbang is enabled
-ifdef rbb
- questa-cmd += +jtag_rbb_enable=1
-else
- questa-cmd += +jtag_rbb_enable=0
-endif
# Build the TB and module using QuestaSim
-build: $(library) $(library)/.build-srcs $(library)/.build-tb $(dpi-library)/ariane_dpi.so
+build: $(library) $(library)/.build-srcs $(library)/.build-tb
# Optimize top level
vopt$(questa_version) $(compile_flag) -work $(library) $(top_level) -o $(top_level)_optimized +acc -check_synthesis
@@ -290,7 +244,7 @@ $(library)/.build-srcs: $(util) $(library)
touch $(library)/.build-srcs
# build TBs
-$(library)/.build-tb: $(dpi)
+$(library)/.build-tb:
# Compile top level
vlog$(questa_version) $(compile_flag) -sv $(tbs) -work $(library)
touch $(library)/.build-tb
@@ -298,257 +252,24 @@ $(library)/.build-tb: $(dpi)
$(library):
vlib${questa_version} $(library)
-# compile DPIs
-$(dpi-library)/%.o: tb/dpi/%.cc $(dpi_hdr)
- mkdir -p $(dpi-library)
- $(CXX) -shared -fPIC -std=c++0x -Bsymbolic $(CFLAGS) -c $< -o $@
-
-$(dpi-library)/ariane_dpi.so: $(dpi)
- mkdir -p $(dpi-library)
- # Compile C-code and generate .so file
- $(CXX) -shared -m64 -o $(dpi-library)/ariane_dpi.so $? -L$(RISCV)/lib -Wl,-rpath,$(RISCV)/lib -lfesvr
-# single test runs on Questa can be started by calling make <testname>, e.g. make towers.riscv
-# the test names are defined in ci/riscv-asm-tests.list, and in ci/riscv-benchmarks.list
+# target used to run simulation, make sim APP=<software application to run on CVA6>
# if you want to run in batch mode, use make <testname> batch-mode=1
-# alternatively you can call make sim elf-bin=<path/to/elf-bin> in order to load an arbitrary binary
-sim: build
+sim: build benchmark
+ echo $(riscv-benchmarks)
vsim${questa_version} +permissive $(questa-flags) $(questa-cmd) -lib $(library) +MAX_CYCLES=$(max_cycles) +UVM_TESTNAME=$(test_case) \
- +BASEDIR=$(riscv-test-dir) $(uvm-flags) $(QUESTASIM_FLAGS) -gblso $(RISCV)/lib/libfesvr.so -sv_lib $(dpi-library)/ariane_dpi \
- ${top_level}_optimized +permissive-off ++$(elf-bin) ++$(target-options) | tee sim.log
-
-$(riscv-asm-tests): build
- vsim${questa_version} +permissive $(questa-flags) $(questa-cmd) -lib $(library) +max-cycles=$(max_cycles) +UVM_TESTNAME=$(test_case) \
- +BASEDIR=$(riscv-test-dir) $(uvm-flags) +jtag_rbb_enable=0 -gblso $(RISCV)/lib/libfesvr.so -sv_lib $(dpi-library)/ariane_dpi \
- ${top_level}_optimized $(QUESTASIM_FLAGS) +permissive-off ++$(riscv-test-dir)/$@ ++$(target-options) | tee tmp/riscv-asm-tests-$@.log
-
-$(riscv-amo-tests): build
- vsim${questa_version} +permissive $(questa-flags) $(questa-cmd) -lib $(library) +max-cycles=$(max_cycles) +UVM_TESTNAME=$(test_case) \
- +BASEDIR=$(riscv-test-dir) $(uvm-flags) +jtag_rbb_enable=0 -gblso $(RISCV)/lib/libfesvr.so -sv_lib $(dpi-library)/ariane_dpi \
- ${top_level}_optimized $(QUESTASIM_FLAGS) +permissive-off ++$(riscv-test-dir)/$@ ++$(target-options) | tee tmp/riscv-amo-tests-$@.log
-
-$(riscv-mul-tests): build
- vsim${questa_version} +permissive $(questa-flags) $(questa-cmd) -lib $(library) +max-cycles=$(max_cycles) +UVM_TESTNAME=$(test_case) \
- +BASEDIR=$(riscv-test-dir) $(uvm-flags) +jtag_rbb_enable=0 -gblso $(RISCV)/lib/libfesvr.so -sv_lib $(dpi-library)/ariane_dpi \
- ${top_level}_optimized $(QUESTASIM_FLAGS) +permissive-off ++$(riscv-test-dir)/$@ ++$(target-options) | tee tmp/riscv-mul-tests-$@.log
-
-$(riscv-fp-tests): build
- vsim${questa_version} +permissive $(questa-flags) $(questa-cmd) -lib $(library) +max-cycles=$(max_cycles) +UVM_TESTNAME=$(test_case) \
- +BASEDIR=$(riscv-test-dir) $(uvm-flags) +jtag_rbb_enable=0 -gblso $(RISCV)/lib/libfesvr.so -sv_lib $(dpi-library)/ariane_dpi \
- ${top_level}_optimized $(QUESTASIM_FLAGS) +permissive-off ++$(riscv-test-dir)/$@ ++$(target-options) | tee tmp/riscv-fp-tests-$@.log
-
-$(riscv-benchmarks): build
- vsim${questa_version} +permissive $(questa-flags) $(questa-cmd) -lib $(library) +max-cycles=$(max_cycles) +UVM_TESTNAME=$(test_case) \
- +BASEDIR=$(riscv-benchmarks-dir) $(uvm-flags) +jtag_rbb_enable=0 -gblso $(RISCV)/lib/libfesvr.so -sv_lib $(dpi-library)/ariane_dpi \
- ${top_level}_optimized $(QUESTASIM_FLAGS) +permissive-off ++$(riscv-benchmarks-dir)/$@ ++$(target-options) | tee tmp/riscv-benchmarks-$@.log
-
-# can use -jX to run ci tests in parallel using X processes
-run-asm-tests: $(riscv-asm-tests)
- $(MAKE) check-asm-tests
+ $(uvm-flags) $(QUESTASIM_FLAGS) \
+ ${top_level}_optimized +permissive-off +binary_mem=$(app_path)/$(APP).mem | tee sim.log
-run-amo-tests: $(riscv-amo-tests)
- $(MAKE) check-amo-tests
-run-mul-tests: $(riscv-mul-tests)
- $(MAKE) check-mul-tests
-
-run-fp-tests: $(riscv-fp-tests)
- $(MAKE) check-fp-tests
-
-check-asm-tests:
- ci/check-tests.sh tmp/riscv-asm-tests- $(shell wc -l $(riscv-asm-tests-list) | awk -F " " '{ print $1 }')
-
-check-amo-tests:
- ci/check-tests.sh tmp/riscv-amo-tests- $(shell wc -l $(riscv-amo-tests-list) | awk -F " " '{ print $1 }')
-
-check-mul-tests:
- ci/check-tests.sh tmp/riscv-mul-tests- $(shell wc -l $(riscv-mul-tests-list) | awk -F " " '{ print $1 }')
-
-check-fp-tests:
- ci/check-tests.sh tmp/riscv-fp-tests- $(shell wc -l $(riscv-fp-tests-list) | awk -F " " '{ print $1 }')
-
-# can use -jX to run ci tests in parallel using X processes
run-benchmarks: $(riscv-benchmarks)
$(MAKE) check-benchmarks
check-benchmarks:
ci/check-tests.sh tmp/riscv-benchmarks- $(shell wc -l $(riscv-benchmarks-list) | awk -F " " '{ print $1 }')
-# verilator-specific
-verilate_command := $(verilator) \
- $(filter-out %.vhd, $(ariane_pkg)) \
- $(filter-out src/fpu_wrap.sv, $(filter-out %.vhd, $(src))) \
- +define+$(defines) \
- src/util/sram.sv \
- tb/common/mock_uart.sv \
- +incdir+src/axi_node \
- $(if $(verilator_threads), --threads $(verilator_threads)) \
- --unroll-count 256 \
- -Werror-PINMISSING \
- -Werror-IMPLICIT \
- -Wno-fatal \
- -Wno-PINCONNECTEMPTY \
- -Wno-ASSIGNDLY \
- -Wno-DECLFILENAME \
- -Wno-UNUSED \
- -Wno-UNOPTFLAT \
- -Wno-BLKANDNBLK \
- -Wno-style \
- $(if $(DROMAJO), -DDROMAJO=1,) \
- $(if $(PROFILE),--stats --stats-vars --profile-cfuncs,) \
- $(if $(DEBUG),--trace --trace-structs,) \
- -LDFLAGS "-L$(RISCV)/lib -Wl,-rpath,$(RISCV)/lib -lfesvr$(if $(PROFILE), -g -pg,) $(if $(DROMAJO), -L../tb/dromajo/src -ldromajo_cosim,) -lpthread" \
- -CFLAGS "$(CFLAGS)$(if $(PROFILE), -g -pg,) $(if $(DROMAJO), -DDROMAJO=1,)" -Wall --cc --vpi \
- $(list_incdir) --top-module ariane_testharness \
- --Mdir $(ver-library) -O3 \
- --exe tb/ariane_tb.cpp tb/dpi/SimDTM.cc tb/dpi/SimJTAG.cc \
- tb/dpi/remote_bitbang.cc tb/dpi/msim_helper.cc $(if $(DROMAJO), tb/dpi/dromajo_cosim_dpi.cc,)
-
-dromajo:
- cd ./tb/dromajo/src && make
-
-run-dromajo-verilator:
- $(if $(BIN), $(MAKE) checkpoint_dromajo, $(error "Please provide absolute path to the binary. Usage: make run_dromajo BIN=/absolute/path/to/binary"))
-
-checkpoint_dromajo:
- cd ./tb/dromajo/run/checkpoints/ && \
- rm -rf $(notdir $(BIN)) && mkdir $(notdir $(BIN)) && cd $(notdir $(BIN)) && \
- cp $(BIN) . && \
- echo -e "\
- {\n\
- \"version\":1,\n\
- \"machine\":\"riscv64\",\n\
- \"memory_size\":256,\n\
- \"bios\":\"$(shell pwd)/tb/dromajo/run/checkpoints/$(notdir $(BIN))/$(notdir $(BIN))\",\n\
- \"memory_base_addr\":0x80000000,\n\
- \"missing_csrs\": [0x323, 0x324, 0x325, 0x326, //mhpmevent csrs\n\
- 0x327, 0x328, 0x329, 0x32a,\n\
- 0x32b, 0x32c, 0x32d, 0x32e,\n\
- 0x32f, 0x330, 0x331, 0x332,\n\
- 0x333, 0x334, 0x335, 0x336,\n\
- 0x337, 0x338, 0x339, 0x33a,\n\
- 0x33b, 0x33c, 0x33d, 0x33e,\n\
- 0x33f,\n\
- 0x3a0, 0x3a1, 0x3a2, 0x3a3, //pmp csrs\n\
- 0x3b0, 0x3b1, 0x3b2, 0x3b3,\n\
- 0x3b4, 0x3b5, 0x3b6, 0x3b7,\n\
- 0x3b8, 0x3b9, 0x3ba, 0x3bb,\n\
- 0x3bc, 0x3bd, 0x3be, 0x3bf,\n\
- 0x320], //mcountinhibit\n\
- \"maxinsns\": 100,\n\
- \"clint_base_addr\": 0x02000000,\n\
- \"clint_size\": 0xC0000,\n\
- \"plic_base_addr\": 0x0C000000,\n\
- \"plic_size\": 0x3FFFFFF,\n\
- \"uart_base_addr\": 0x10000000,\n\
- \"uart_size\": 0x1000\n\
- }" > "$(notdir $(BIN))_boot.cfg" && \
- echo -e "\
- {\n\
- \"version\":1,\n\
- \"machine\":\"riscv64\",\n\
- \"memory_size\":256,\n\
- \"bios\":\"$(shell pwd)/tb/dromajo/run/checkpoints/$(notdir $(BIN))/$(notdir $(BIN))\",\n\
- \"load\":\"$(shell pwd)/tb/dromajo/run/checkpoints/$(notdir $(BIN))/$(notdir $(BIN))\",\n\
- \"skip_commit\": [0x73, 0x9002, 0x100073],\n\
- \"memory_base_addr\":0x80000000,\n\
- \"clint_base_addr\": 0x02000000,\n\
- \"clint_size\": 0xC0000,\n\
- \"plic_base_addr\": 0x0C000000,\n\
- \"plic_size\": 0x3FFFFFF,\n\
- \"uart_base_addr\": 0x10000000,\n\
- \"uart_size\": 0x1000\n\
- }" > "$(notdir $(BIN)).cfg" && \
- ../../../src/dromajo --save=$(notdir $(BIN)) --save_format=1 ./$(notdir $(BIN))_boot.cfg && \
- cd ../../../../../ && \
- ./work-ver/Variane_testharness +checkpoint=$(shell pwd)/tb/dromajo/run/checkpoints/$(notdir $(BIN))/$(notdir $(BIN))
-
-
-# User Verilator, at some point in the future this will be auto-generated
-verilate: $(if $(DROMAJO), dromajo,)
- @echo "[Verilator] Building Model$(if $(PROFILE), for Profiling,)"
- $(verilate_command)
- cd $(ver-library) && $(MAKE) -j${NUM_JOBS} -f Variane_testharness.mk
-
-sim-verilator: verilate
- $(ver-library)/Variane_testharness $(elf-bin)
-
-$(addsuffix -verilator,$(riscv-asm-tests)): verilate
- $(ver-library)/Variane_testharness $(riscv-test-dir)/$(subst -verilator,,$@)
-
-$(addsuffix -verilator,$(riscv-amo-tests)): verilate
- $(ver-library)/Variane_testharness $(riscv-test-dir)/$(subst -verilator,,$@)
-
-$(addsuffix -verilator,$(riscv-mul-tests)): verilate
- $(ver-library)/Variane_testharness $(riscv-test-dir)/$(subst -verilator,,$@)
-
-$(addsuffix -verilator,$(riscv-fp-tests)): verilate
- $(ver-library)/Variane_testharness $(riscv-test-dir)/$(subst -verilator,,$@)
-
-$(addsuffix -verilator,$(riscv-benchmarks)): verilate
- $(ver-library)/Variane_testharness $(riscv-benchmarks-dir)/$(subst -verilator,,$@)
-
-run-all-tests-verilator: $(addsuffix -verilator, $(riscv-asm-tests)) $(addsuffix -verilator, $(riscv-amo-tests)) $(addsuffix -verilator, $(run-mul-verilator)) $(addsuffix -verilator, $(riscv-fp-tests))
-
-run-asm-tests-verilator: $(addsuffix -verilator, $(riscv-asm-tests))
-
-run-amo-verilator: $(addsuffix -verilator, $(riscv-amo-tests))
-
-run-mul-verilator: $(addsuffix -verilator, $(riscv-mul-tests))
-
-run-fp-verilator: $(addsuffix -verilator, $(riscv-fp-tests))
-
-run-fp-d-verilator: $(addsuffix -verilator, $(filter rv64ud%, $(riscv-fp-tests)))
-
-run-fp-f-verilator: $(addsuffix -verilator, $(filter rv64uf%, $(riscv-fp-tests)))
-
-run-benchmarks-verilator: $(addsuffix -verilator,$(riscv-benchmarks))
-
-# torture-specific
-torture-gen:
- cd $(riscv-torture-dir) && $(riscv-torture-bin) 'generator/run'
-
-torture-itest:
- cd $(riscv-torture-dir) && $(riscv-torture-bin) 'testrun/run -a output/test.S'
-
-torture-rtest: build
- cd $(riscv-torture-dir) && printf "#!/bin/sh\ncd $(root-dir) && $(MAKE) run-torture$(torture-logs) batch-mode=1 defines=$(defines) test-location=$(test-location)" > call.sh && chmod +x call.sh
- cd $(riscv-torture-dir) && $(riscv-torture-bin) 'testrun/run -r ./call.sh -a $(test-location).S' | tee $(test-location).log
- make check-torture test-location=$(test-location)
-
-torture-dummy: build
- cd $(riscv-torture-dir) && printf "#!/bin/sh\ncd $(root-dir) && $(MAKE) run-torture batch-mode=1 defines=$(defines) test-location=\$${@: -1}" > call.sh
-
-torture-rnight: build
- cd $(riscv-torture-dir) && printf "#!/bin/sh\ncd $(root-dir) && $(MAKE) run-torture$(torture-logs) batch-mode=1 defines=$(defines) test-location=\$${@: -1}" > call.sh && chmod +x call.sh
- cd $(riscv-torture-dir) && $(riscv-torture-bin) 'overnight/run -r ./call.sh -g none' | tee output/overnight.log
- $(MAKE) check-torture
-
-torture-rtest-verilator: verilate
- cd $(riscv-torture-dir) && printf "#!/bin/sh\ncd $(root-dir) && $(MAKE) run-torture-verilator batch-mode=1 defines=$(defines)" > call.sh && chmod +x call.sh
- cd $(riscv-torture-dir) && $(riscv-torture-bin) 'testrun/run -r ./call.sh -a output/test.S' | tee output/test.log
- $(MAKE) check-torture
-
-run-torture: build
- vsim${questa_version} +permissive $(questa-flags) $(questa-cmd) -lib $(library) +max-cycles=$(max_cycles)+UVM_TESTNAME=$(test_case) \
- +BASEDIR=$(riscv-torture-dir) $(uvm-flags) +jtag_rbb_enable=0 -gblso $(RISCV)/lib/libfesvr.so -sv_lib $(dpi-library)/ariane_dpi \
- ${top_level}_optimized +permissive-off +signature=$(riscv-torture-dir)/$(test-location).rtlsim.sig ++$(riscv-torture-dir)/$(test-location) ++$(target-options)
-
-run-torture-log: build
- vsim${questa_version} +permissive $(questa-flags) $(questa-cmd) -lib $(library) +max-cycles=$(max_cycles)+UVM_TESTNAME=$(test_case) \
- +BASEDIR=$(riscv-torture-dir) $(uvm-flags) +jtag_rbb_enable=0 -gblso $(RISCV)/lib/libfesvr.so -sv_lib $(dpi-library)/ariane_dpi \
- ${top_level}_optimized +permissive-off +signature=$(riscv-torture-dir)/$(test-location).rtlsim.sig ++$(riscv-torture-dir)/$(test-location) ++$(target-options)
- cp vsim.wlf $(riscv-torture-dir)/$(test-location).wlf
- cp trace_hart_0000.log $(riscv-torture-dir)/$(test-location).trace
- cp trace_hart_0000_commit.log $(riscv-torture-dir)/$(test-location).commit
- cp transcript $(riscv-torture-dir)/$(test-location).transcript
-
-run-torture-verilator: verilate
- $(ver-library)/Variane_testharness +max-cycles=$(max_cycles) +signature=$(riscv-torture-dir)/output/test.rtlsim.sig $(riscv-torture-dir)/output/test
-
-check-torture:
- grep 'All signatures match for $(test-location)' $(riscv-torture-dir)/$(test-location).log
- diff -s $(riscv-torture-dir)/$(test-location).spike.sig $(riscv-torture-dir)/$(test-location).rtlsim.sig
+benchmark:
+ cd sw/app && make $(APP).mem
fpga_filter := $(addprefix $(root-dir), bootrom/bootrom.sv)
fpga_filter += $(addprefix $(root-dir), include/instr_tracer_pkg.sv)
@@ -557,30 +278,27 @@ fpga_filter += $(addprefix $(root-dir), src/util/instr_trace_item.sv)
fpga_filter += $(addprefix $(root-dir), src/util/instr_tracer_if.sv)
fpga_filter += $(addprefix $(root-dir), src/util/instr_tracer.sv)
-fpga: $(ariane_pkg) $(util) $(src) $(fpga_src) $(uart_src)
- @echo "[FPGA] Generate sources"
- @echo read_vhdl {$(uart_src)} > fpga/scripts/add_sources.tcl
+# target rused to run synthesis and place and route in out of context mode
+# make cva6_ooc CLK_PERIOD_NS=<period of the CVA6 architecture>
+cva6_ooc: $(ariane_pkg) $(util) $(src) $(fpga_src)
+ @echo "Generate sources for synthesis"
@echo read_verilog -sv {$(ariane_pkg)} >> fpga/scripts/add_sources.tcl
@echo read_verilog -sv {$(filter-out $(fpga_filter), $(util))} >> fpga/scripts/add_sources.tcl
@echo read_verilog -sv {$(filter-out $(fpga_filter), $(src))} >> fpga/scripts/add_sources.tcl
@echo read_verilog -sv {$(fpga_src)} >> fpga/scripts/add_sources.tcl
- @echo "[FPGA] Generate Bitstream"
- cd fpga && make BOARD=$(BOARD) XILINX_PART=$(XILINX_PART) XILINX_BOARD=$(XILINX_BOARD) CLK_PERIOD_NS=$(CLK_PERIOD_NS)
-
-.PHONY: fpga
+ cd fpga && make cva6_ooc BOARD=$(BOARD) XILINX_PART=$(XILINX_PART) XILINX_BOARD=$(XILINX_BOARD) CLK_PERIOD_NS=$(CLK_PERIOD_NS) BATCH_MODE=$(BATCH_MODE)
-build-spike:
- cd tb/riscv-isa-sim && mkdir -p build && cd build && ../configure --prefix=`pwd`/../install --with-fesvr=$(RISCV) --enable-commitlog && make -j8 install
+.PHONY: cva6_ooc
clean:
rm -rf $(riscv-torture-dir)/output/test*
rm -rf $(library)/ $(dpi-library)/ $(ver-library)/
rm -f tmp/*.ucdb tmp/*.log *.wlf *vstf wlft* *.ucdb
+ cd sw/app && make clean
+ cd fpga && make clean
.PHONY:
- build sim sim-verilate clean \
- $(riscv-asm-tests) $(addsuffix _verilator,$(riscv-asm-tests)) \
- $(riscv-benchmarks) $(addsuffix _verilator,$(riscv-benchmarks)) \
- check-benchmarks check-asm-tests \
- torture-gen torture-itest torture-rtest \
- run-torture run-torture-verilator check-torture check-torture-verilator
+ build sim benchmark clean \
+ $(riscv-benchmarks) \
+ check-benchmarks
+
diff --git a/README.md b/README.md
index eee63bb1..7d57292d 100644
--- a/README.md
+++ b/README.md
@@ -1,363 +1,96 @@
-[](https://travis-ci.org/openhwgroup/cva6)
+# Getting started
-# CVA6 RISC-V CPU
+To get more familiar with CVA6 architecture, documentation is available to this link:
-CVA6 is a 6-stage, single issue, in-order CPU which implements the 64-bit RISC-V instruction set. It fully implements I, M, A and C extensions as specified in Volume I: User-Level ISA V 2.3 as well as the draft privilege extension 1.10. It implements three privilege levels M, S, U to fully support a Unix-like operating system. Furthermore it is compliant to the draft external debug spec 0.13.
-
-It has configurable size, separate TLBs, a hardware PTW and branch-prediction (branch target buffer and branch history table). The primary design goal was on reducing critical path length.
-
-
-
-## Publication
-
-If you use CVA6 in your academic work you can cite us:
-
-```
-@article{8777130,
- author={F. {Zaruba} and L. {Benini}},
- journal={IEEE Transactions on Very Large Scale Integration (VLSI) Systems},
- title={The Cost of Application-Class Processing: Energy and Performance Analysis of a Linux-Ready 1.7-GHz 64-Bit RISC-V Core in 22-nm FDSOI Technology},
- year={2019},
- volume={27},
- number={11},
- pages={2629-2640},
- doi={10.1109/TVLSI.2019.2926114},
- ISSN={1557-9999},
- month={Nov},
-}
-```
-
-Table of Contents
-=================
-
- * [CVA6 RISC-V CPU](#cva6-risc-v-cpu)
- * [Table of Contents](#table-of-contents)
- * [Getting Started](#getting-started)
- * [Running User-Space Applications](#running-user-space-applications)
- * [FPGA Emulation](#fpga-emulation)
- * [Programming the Memory Configuration File](#programming-the-memory-configuration-file)
- * [Preparing the SD Card](#preparing-the-sd-card)
- * [Generating a Bitstream](#generating-a-bitstream)
- * [Debugging](#debugging)
- * [Preliminary Support for OpenPiton Cache System](#preliminary-support-for-openpiton-cache-system)
- * [Planned Improvements](#planned-improvements)
- * [Going Beyond](#going-beyond)
- * [CI Testsuites and Randomized Constrained Testing with Torture](#ci-testsuites-and-randomized-constrained-testing-with-torture)
- * [Re-generating the Bootcode (ZSBL)](#re-generating-the-bootcode-zsbl)
- * [Co-simulation with Dromajo](#co-simulation-with-dromajo)
- * [Contributing](#contributing)
- * [Acknowledgements](#acknowledgements)
-
-Created by [gh-md-toc](https://github.com/ekalinin/github-markdown-toc)
-
-## Getting Started
-
-Go and get the [RISC-V tools](https://github.com/riscv/riscv-tools). Make sure that your `RISCV` environment variable points to your RISC-V installation (see the RISC-V tools and related projects for further information).
+https://cva6.readthedocs.io/en/latest/
Checkout the repository and initialize all submodules
```
-$ git clone https://github.com/openhwgroup/cva6.git
-$ git submodule update --init --recursive
-```
-
-Build the Verilator model of CVA6 by using the Makefile:
-```
-$ make verilate
-```
-
-To build the verilator model with support for vcd files run
-```
-$ make verilate DEBUG=1
-```
-
-This will create a C++ model of the core including a SystemVerilog wrapper and link it against a C++ testbench (in the `tb` subfolder). The binary can be found in the `work-ver` and accepts a RISC-V ELF binary as an argument, e.g.:
-
-```
-$ work-ver/Variane_testharness rv64um-v-divuw
-```
-
-The Verilator testbench makes use of the `riscv-fesvr`. This means that you can use the `riscv-tests` repository as well as `riscv-pk` out-of-the-box. As a general rule of thumb the Verilator model will behave like Spike (exception for being orders of magnitudes slower).
-
-Both, the Verilator model as well as the Questa simulation will produce trace logs. The Verilator trace is more basic but you can feed the log to `spike-dasm` to resolve instructions to mnemonics. Unfortunately value inspection is currently not possible for the Verilator trace file.
-
+$ git --recursive clone https://github.com/ThalesGroup/cva6-softcore-contest.git
```
-$ spike-dasm < trace_hart_00.dasm > logfile.txt
-```
-
-### Running User-Space Applications
-
-It is possible to run user-space binaries on CVA6 with `riscv-pk` ([link](https://github.com/riscv/riscv-pk)).
-
-```
-$ mkdir build
-$ cd build
-$ ../configure --prefix=$RISCV --host=riscv64-unknown-elf
-$ make
-$ make install
-```
-
-Then to run a RISC-V ELF using the Verilator model do:
-
-```
-$ echo '
-#include <stdio.h>
-
-int main(int argc, char const *argv[]) {
- printf("Hello CVA6!\\n");
- return 0;
-}' > hello.c
-$ riscv64-unknown-elf-gcc hello.c -o hello.elf
-```
-
-```
-$ make verilate
-$ work-ver/Variane_testharness $RISCV/riscv64-unknown-elf/bin/pk hello.elf
-```
-
-If you want to use QuestaSim to run it you can use the following command:
-```
-$ make sim elf-bin=$RISCV/riscv64-unknown-elf/bin/pk target-options=hello.elf batch-mode=1
-```
-
-> Be patient! RTL simulation is way slower than Spike. If you think that you ran into problems you can inspect the trace files.
-
-## FPGA Emulation
-
-We currently only provide support for the [Genesys 2 board](https://reference.digilentinc.com/reference/programmable-logic/genesys-2/reference-manual). We provide pre-build bitstream and memory configuration files for the Genesys 2 [here](https://github.com/openhwgroup/cva6/releases).
-
-Tested on Vivado 2018.2. The FPGA SoC currently contains the following peripherals:
-
-- DDR3 memory controller
-- SPI controller to conncet to an SDCard
-- Ethernet controller
-- JTAG port (see debugging section below)
-- Bootrom containing zero stage bootloader and device tree.
-
-
-
-> The ethernet controller and the corresponding network connection is still work in progress and not functional at the moment. Expect some updates soon-ish.
-
-### Programming the Memory Configuration File
+# Prerequisites
-- Open Vivado
-- Open the hardware manager and open the target board (Genesys II - `xc7k325t`)
-- Tools - Add Configuration Memory Device
-- Select the following Spansion SPI flash `s25fl256xxxxxx0`
-- Add `ariane_xilinx.mcs`
-- Press Ok. Flashing will take a couple of minutes.
-- Right click on the FPGA device - Boot from Configuration Memory Device (or press the program button on the FPGA)
-### Preparing the SD Card
-
-The first stage bootloader will boot from SD Card by default. Get yourself a suitable SD Card (we use [this](https://www.amazon.com/Kingston-Digital-Mobility-MBLY10G2-32GB/dp/B00519BEQO) one). Either grab a pre-built Linux image from [here](https://github.com/pulp-platform/ariane-sdk/releases) or generate the Linux image yourself following the README in the [ariane-sdk repository](https://github.com/pulp-platform/ariane-sdk). Prepare the SD Card by following the "Booting from SD card" section in the ariane-sdk repository.
-
-Connect a terminal to the USB serial device opened by the FTDI chip e.g.:
+## RISCV tool chain setting up
+The tool chain is available to this link: https://github.com/riscv/riscv-gnu-toolchain
+At first, you have to get the sources of the RISCV gnu toolchain:
```
-$ screen /dev/ttyUSB0 115200
+$ git clone --recursive https://github.com/riscv/riscv-gnu-toolchain
```
-
-Default baudrate set by the bootlaoder and Linux is `115200`.
-
-After you've inserted the SD Card and programmed the FPGA you can connect to the serial port of the FPGA and should see the bootloader and afterwards Linux booting. Default username is `root`, no password required.
-
-### Generating a Bitstream
-
-To generate the FPGA bitstream (and memory configuration) yourself for the Genesys II board run:
-
+Next, you have to install all standard packages needed to build the toolchain depending on your linux distribution.
+Before installing the tool chain, it is important to define the environment variable RISCV=”path where the tool chain will be installed”.
+Then, you have to set up the compiler by running the following command:
```
-$ make fpga
+$ ./configure --prefix=$RISCV --disable-linux --with-cmodel=medany --with-arch=rv32ima
+$ make newlib
```
+When the installation is achieved, do not forget to add $RISCV/bin to your PATH.
-This will produce a bitstream file and memory configuration file (in `fpga/work-fpga`) which you can permanently flash by running the above commands.
+## Questa tool
+Questa sim **version 10.7** has been used for simulations.
-### Debugging
+## Vitis/Vivado setting up
+For the contest, CVA6 processor will be implemented on Zybo 7-20 board from Digilent. This board consists of Zynq 7 FPGA from Xilinx.
+To do so, **Vitis 2020.1** environment from Xilinx need to be installed.
-You can debug (and program) the FPGA using [OpenOCD](http://openocd.org/doc/html/Architecture-and-Core-Commands.html). We provide two example scripts for OpenOCD below.
+Furthermore, Digilent provides board files for each development board.
-To get started, connect the micro USB port that is labeled with JTAG to your machine. This port is attached to the FTDI 2232 USB-to-serial chip on the Genesys 2 board, and is usually used to access the native JTAG interface of the Kintex-7 FPGA (e.g. to program the device using Vivado). However, the FTDI chip also exposes a second serial link that is routed to GPIO pins on the FPGA, and we leverage this to wire up the JTAG from the RISC-V debug module.
+This files ease the creating of new projects with automated configuration of several complicated components such as Zynq Processing System and memory interfaces.
->If you are on an Ubuntu based system you need to add the following udev rule to `/etc/udev/rules.d/99-ftdi.rules`
->```
-> SUBSYSTEM=="usb", ACTION=="add", ATTRS{idProduct}=="6010", ATTRS{idVendor}=="0403", MODE="664", GROUP="plugdev"
->```
+All guidelines to install **vitis 2020.1** and **Zybo 7-20** board files are explained to the following link:
+https://reference.digilentinc.com/reference/programmable-logic/guides/installation
-Once attached to your system, the FTDI chip should be listed when you type `lsusb`:
+## Simulation get started
+When the development environment is set up, it is now possible to run a simulation.
+Some software applications are available into the sw/app directory. Especially, there are benchmark applications such as Dhrystone and Coremark and other test applications.
+To simulate a software application on CVA6 processor, run the following command:
```
-Bus 005 Device 019: ID 0403:6010 Future Technology Devices International, Ltd FT2232C/D/H Dual UART/FIFO IC
+$ make sim APP=’application to run’
```
-
-If this is the case, you can go on and start openocd with the `fpga/ariane.cfg` configuration file:
-
-```
-$ openocd -f fpga/ariane.cfg
-Open On-Chip Debugger 0.10.0+dev-00195-g933cb87 (2018-09-14-19:32)
-Licensed under GNU GPL v2
-For bug reports, read
- http://openocd.org/doc/doxygen/bugs.html
-adapter speed: 1000 kHz
-Info : auto-selecting first available session transport "jtag". To override use 'transport select <transport>'.
-Info : clock speed 1000 kHz
-Info : TAP riscv.cpu does not have IDCODE
-Info : datacount=2 progbufsize=8
-Info : Examined RISC-V core; found 1 harts
-Info : hart 0: XLEN=64, misa=0x8000000000141105
-Info : Listening on port 3333 for gdb connections
-Ready for Remote Connections
-Info : Listening on port 6666 for tcl connections
-Info : Listening on port 4444 for telnet connections
-Info : accepting 'gdb' connection on tcp/3333
+For instance, if you want to run Coremark application, you will have to run :
```
-
-Then you will be able to either connect through `telnet` or with `gdb`:
-
+$ make sim APP=coremark
```
-$ riscv64-unknown-elf-gdb /path/to/elf
-(gdb) target remote localhost:3333
-(gdb) load
-Loading section .text, size 0x6508 lma 0x80000000
-Loading section .rodata, size 0x900 lma 0x80006508
-(gdb) b putchar
-(gdb) c
-Continuing.
-
-Program received signal SIGTRAP, Trace/breakpoint trap.
-0x0000000080009126 in putchar (s=72) at lib/qprintf.c:69
-69 uart_sendchar(s);
-(gdb) si
-0x000000008000912a 69 uart_sendchar(s);
-(gdb) p/x $mepc
-$1 = 0xfffffffffffdb5ee
+For instance, if you want to run Dhrystone application, you will have to run :
```
+$ make sim APP=dhrystone
-You can read or write device memory by using:
```
-(gdb) x/i 0x1000
- 0x1000: lui t0,0x4
-(gdb) set {int} 0x1000 = 22
-(gdb) set $pc = 0x1000
-```
-
-### Preliminary Support for OpenPiton Cache System
+**This command:**
+- Compile CVA6 architecture and testbench with Questa Sim tool.
+- Compile the software application to be run on CVA6 with RISCV tool chain.
+- Run the simulation.
-CVA6 has preliminary support for the OpenPiton distributed cache system from Princeton University. To this end, a different L1 cache subsystem (`src/cache_subsystem/wt_cache_subsystem.sv`) has been developed that follows a write-through protocol and that has support for cache invalidations and atomics.
+Questa tool will open with wave window. Some signals will be displayed; you are free to add as much as signals you for the contest.
-The corresponding integration patches will be released on [OpenPiton GitHub repository](https://github.com/PrincetonUniversity/openpiton). Check the `README` in that repository to see how to use CVA6 in the OpenPiton setting.
+Moreover, all `printf` used into software application will be displayed into the **transcript** window of Questa Sim and save into **uart** file to the root directory.
-To activate the different cache system, compile your code with the macro `WT_DCACHE` (set by default).
+> Simulation may take lot of time, so you need to be patient to have results.
-## Planned Improvements
+CVA6 software environment is detailed into `sw/app` directory.
-Check-out the issue tab which also loosely tracks planned improvements.
+# Synthesis and place and route get started
+You can perform synthesis and place and route of the CVA6 architecture.
+In the first time, synthesis and place and route are carried in out of context mode, that means that the CVA6 architecture is synthetized in the FPGA fabric without consideration of the IOs constraints.
-## Going Beyond
+That allows to have an estimation of the logical resources used by the CVA6 in the FPGA fabric as well as the maximal frequency of CVA6 architecture.
-The core has been developed with a full licensed version of QuestaSim. If you happen to have this simulator available yourself here is how you could run the core with it.
+These both metrics are majors for a computation architecture.
-To specify the test to run use (e.g.: you want to run `rv64ui-p-sraw` inside the `tmp/risc-tests/build/isa` folder:
+Command to run for synthesis and place and route in out of context mode:
```
-$ make sim elf-bin=path/to/rv64ui-p-sraw
+$ make cva6_ooc CLK_PERIOD_NS=<period of the architecture in ns>
```
-
-If you call `sim` with `batch-mode=1` it will run without the GUI. QuestaSim uses `riscv-fesvr` for communication as well.
-
-### CI Testsuites and Randomized Constrained Testing with Torture
-
-We provide two CI configuration files for Travis CI and GitLab CI that run the RISCV assembly tests, the RISCV benchmarks and a randomized RISCV Torture test. The difference between the two is that Travis CI runs these tests only on Verilator, whereas GitLab CI runs the same tests on QuestaSim and Verilator.
-
-If you would like to run the CI test suites locally on your machine, follow any of the two scripts `ci/travis-ci-emul.sh` and `ci/travis-ci-emul.sh` (depending on whether you have QuestaSim or not). In particular, you have to get the required packages for your system, the paths in `ci/path-setup.sh` to match your setup, and run the installation and build scripts prior to running any of the tests suites.
-
-Once everything is set up and installed, you can run the tests suites as follows (using Verilator):
-
-```
-$ make verilate
-$ make run-asm-tests-verilator
-$ make run-benchmarks-verilator
+For example, if you want to clock the architecture to 50MHz, you have to run:
```
-
-In order to run randomized Torture tests, you first have to generate the randomized program prior to running the simulation:
-
+$ make cva6_ooc CLK_PERIOD_NS=20
```
-$ ./ci/get-torture.sh
-$ make torture-gen
-$ make torture-rtest-verilator
+By default, synthesis is performed in batch mode, however that is possible to run this command using the GUI of Vivado:
```
-This runs the randomized program on Spike and on the RTL target, and checks whether the two signatures match. The random instruction mix can be configured in the `./tmp/riscv-torture/config/default.config` file.
-
-CVA6 can dump a trace-log in Questa which can be easily diffed against Spike with commit log enabled. In `include/ariane_pkg.sv` set:
-
-```verilog
-localparam bit ENABLE_SPIKE_COMMIT_LOG = 1'b1;
+$ make cva6_ooc CLK_PERIOD_NS=20 BATCH_MODE=0
```
-This runs the randomized program on Spike and on the RTL target, and checks whether the two signatures match. The random instruction mix can be configured in the `./tmp/riscv-torture/config/default.config` file.
-This will dump a file called `trace_hart_*_*_commit.log`.
-
-This can be helpful for debugging long traces (e.g.: torture traces). To compile Spike with the commit log feature do:
-
-```
-$ apt-get install device-tree-compiler
-$ mkdir build
-$ cd build
-$ ../configure --prefix=$RISCV --with-fesvr=$RISCV --enable-commitlog
-$ make
-$ [sudo] make install
-```
-
-### Memory Preloading
-
-In standard configuration the debug module will take care of loading the memory content. It will also handle communication with `riscv-fesvr`.
-Depending on the scenario this might not be diserable (e.g.: preloading of a large elf or linux boot in simulation). You can use the preload elf flag to specify the path
-to a binary which will be preloaded.
-
-> You will loose all `riscv-fesvr` communcation like sytemcalls and eoc capabilities.
-
-```
-$ make sim preload=elf
-```
-
-<!-- ### Tandem Verification with Spike
-
-```
-$ make sim preload=/home/zarubaf/Downloads/riscv-tests/build/benchmarks/dhrystone.riscv tandem=1
-```
-There are a couple of caveats:
-
-- Memories should be initialized to zero. Random or `x` are not supported.
-- UART needs to be replaced by a mock UART which exhibits always ready behavior.
-- There is no end of test signaling at the moment. You are supposed to kill the simulation when sufficiently long run.
-- You need to use the modified Spike version in the `tb` subdirectory.
-- The RTC clock needs to be sufficiently slow (e.g.: 32 kHz seems to work). This is needed as otherwise there will be a difference when reading the `mtime` register as the RTL simulation takes more time to propagate the information through the system.
-- All traps except memory traps need to zero the `tval` register. There is a switch you can set in `ariane_pkg`.
-- `mcycle` needs to be incremented with `instret` to be similar to the performance counters found in Spike (IPC = 1)
- -->
-
-### Re-generating the Bootcode (ZSBL)
-
-The zero stage bootloader (ZSBL) for RTL simulation lives in `bootrom/` while the bootcode for the FPGA is in `fpga/src/bootrom`. The RTL bootcode simply jumps to the base of the DRAM where the FSBL takes over. For the FPGA the ZSBL performs additional housekeeping. Both bootloader pass the hartid as well as address to the device tree in argumen register `a0` and `a1` respectively.
-
-To re-generate the bootcode you can use the existing makefile within those directories. To generate the SystemVerilog files you will need the `bitstring` python package installed on your system.
-
-### Co-simulation with Dromajo
-CVA6 can be co-simulated with [Dromajo](https://github.com/chipsalliance/dromajo) (currently in the verilator model).
-
-```
-make verilate DROMAJO=1
-make run-dromajo-verilator BIN=/path/to/elf
-```
-
-The co-simulation flow is depicted in the figure below.
-
-1. Load the binary of interest into Dromajo.
-2. Run Dromajo stand alone and let a couple of instructions to complete.
-3. Dump the checkpoint. This is the whole architectural state of the reference model. Dromajo dumps the main and boot memories. In addition, it generates a boot code. If you were to run that code it will restore the whole architectural state. This means that you can bring any two or more cores into complete synced architectural state by running this piece of code.
-4. Load the checkpoint into the RTL memory and the instance of Dromajo in RTL. Dromajo gets linked to a simulator as a shared library. RTL communicates to Dromajo through set of DPI calls.
-5. Run the RTL simulation and perform co-simulation.
-
-# Contributing
-
-Check out the [contribution guide](CONTRIBUTING.md)
+This command generates synthesis and place and route reports in **fpga/reports_cva6_ooc_synth** and **fpga/reports_cva6_ooc_impl**.
-# Acknowledgements
-Thanks to Gian Marti, Thomas Kramer and Thomas E. Benz for implementing the PLIC.
diff --git a/fpga/Makefile b/fpga/Makefile
index d322545f..13dbd64d 100644
--- a/fpga/Makefile
+++ b/fpga/Makefile
@@ -1,44 +1,60 @@
-VIVADO ?= vivado
-VIVADOFLAGS ?= -nojournal -mode batch -source scripts/prologue.tcl
-
-work-dir := work-fpga
-bit := $(work-dir)/ariane_xilinx.bit
-mcs := $(work-dir)/ariane_xilinx.mcs
-ip-dir := xilinx
-ips := xlnx_axi_clock_converter.xci \
- xlnx_axi_dwidth_converter.xci \
- xlnx_axi_quad_spi.xci \
- xlnx_axi_gpio.xci \
- xlnx_clk_gen.xci \
- xlnx_mig_7_ddr3.xci
-
-ips := $(addprefix $(work-dir)/, $(ips))
-ips-target := $(join $(addsuffix /ip/, $(addprefix $(ip-dir)/, $(basename $(ips)))), $(ips))
-
-all: $(mcs)
+# Copyright (c) 2020 Thales.
+#
+# Copyright and related rights are licensed under the Solderpad
+# License, Version 2.0 (the "License"); you may not use this file except in
+# compliance with the License. You may obtain a copy of the License at
+# http://solderpad.org/licenses/SHL-2.0/ Unless required by applicable law
+# or agreed to in writing, software, hardware and materials distributed under
+# this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR
+# CONDITIONS OF ANY KIND, either express or implied. See the License for the
+# specific language governing permissions and limitations under the License.
+#
+# Author: Sebastien Jacq - sjthales on github.com
+
+#
+# Additional contributions by:
+#
+#
+# script Name: Hardware architecture Makefile
+# Project Name: CVA6 softcore
+# Language: Makefile
+#
+# Description: Makefile to synthesize/place and route CVA6 architecture
+#
+# =========================================================================== #
+# Revisions :
+# Date Version Author Description
+# 2020-10-06 0.1 S.Jacq Created
+# =========================================================================== #
-# Generate mcs from bitstream
-$(mcs): $(bit)
- $(VIVADO) $(VIVADOFLAGS) -source scripts/write_cfgmem.tcl -tclargs $@ $^
-
-$(bit): $(ips)
- mkdir -p $(work-dir)
- $(VIVADO) $(VIVADOFLAGS) -source scripts/run.tcl
- cp ariane.runs/impl_1/ariane_xilinx* ./$(work-dir)
+VIVADO ?= vivado
-$(ips): %.xci :
- mkdir -p $(work-dir)
- @echo Generating $(@F)
- @cd $(ip-dir)/$(basename $(@F)) && make clean && make
- @cp $(ip-dir)/$(basename $(@F))/ip/$(@F) $@
+all: $(cva6_ooc)
-mcs: $(mcs)
+cva6_ooc:
+ifeq ($(BATCH_MODE), 1)
+ $(VIVADO) -mode batch -source scripts/run_cva6_ooc.tcl
+else
+ $(VIVADO) -source scripts/run_cva6_ooc.tcl
+endif
-program:
- $(VIVADO) $(VIVADOFLAGS) -source scripts/program.tcl
clean:
- rm -rf *.log *.jou *.str *.mif *.xpr $(work-dir) ariane.cache ariane.hw ariane.ip_user_files
+ rm -rf *.log \
+ *.jou \
+ *.str \
+ *.mif \
+ *.xpr \
+ cva6_ooc.cache \
+ cva6_ooc.hw \
+ cva6_ooc.ip_user_files \
+ cva6_ooc.sim \
+ cva6_ooc.runs \
+ cva6_ooc.hbs \
+ .Xil \
+ reports_cva6_ooc_synth \
+ reports_cva6_ooc_impl
+
.PHONY:
clean
diff --git a/fpga/ariane-multi-hart.cfg b/fpga/ariane-multi-hart.cfg
deleted file mode 100644
index 3f21b864..00000000
--- a/fpga/ariane-multi-hart.cfg
+++ /dev/null
@@ -1,40 +0,0 @@
-adapter_khz 1000
-
-interface ftdi
-ftdi_vid_pid 0x0403 0x6010
-
-# Channel 1 is taken by Xilinx JTAG
-ftdi_channel 0
-
-# links:
-# http://openocd.org/doc-release/html/Debug-Adapter-Configuration.html
-#
-# Bit MPSSE FT2232 JTAG Type Description
-# Bit0 TCK ADBUS0 TCK Out Clock Signal Output
-# Bit1 TDI ADBUS1 TDI Out Serial Data Out
-# Bit2 TDO ADBUS2 TDO In Serial Data In
-# Bit3 TMS ADBUS3 TMS Out Select Signal Out
-# Bit4 GPIOL0 ADBUS4 nTRST In/Out General Purpose I/O
-# this corresponds to the following in/out layout, with TMS initially set to 1
-ftdi_layout_init 0x0018 0x001b
-# we only have to specify nTRST, the others are assigned correctly by default
-ftdi_layout_signal nTRST -ndata 0x0010
-
-set _CHIPNAME riscv
-jtag newtap $_CHIPNAME cpu -irlen 5
-
-set _TARGETNAME $_CHIPNAME.cpu
-target create $_TARGETNAME riscv -chain-position $_TARGETNAME -rtos riscv
-
-gdb_report_data_abort enable
-gdb_report_register_access_error enable
-
-riscv set_reset_timeout_sec 120
-riscv set_command_timeout_sec 120
-
-# prefer to use sba for system bus access
-riscv set_prefer_sba off
-
-init
-halt
-echo "Ready for Remote Connections"
diff --git a/fpga/ariane.cfg b/fpga/ariane.cfg
deleted file mode 100644
index 82d3f5ab..00000000
--- a/fpga/ariane.cfg
+++ /dev/null
@@ -1,44 +0,0 @@
-adapter_khz 1000
-
-interface ftdi
-ftdi_vid_pid 0x0403 0x6010
-
-# Channel 1 is taken by Xilinx JTAG
-ftdi_channel 0
-
-# links:
-# http://openocd.org/doc-release/html/Debug-Adapter-Configuration.html
-#
-# Bit MPSSE FT2232 JTAG Type Description
-# Bit0 TCK ADBUS0 TCK Out Clock Signal Output
-# Bit1 TDI ADBUS1 TDI Out Serial Data Out
-# Bit2 TDO ADBUS2 TDO In Serial Data In
-# Bit3 TMS ADBUS3 TMS Out Select Signal Out
-# Bit4 GPIOL0 ADBUS4 nTRST In/Out General Purpose I/O
-# this corresponds to the following in/out layout, with TMS initially set to 1
-ftdi_layout_init 0x0018 0x001b
-# we only have to specify nTRST, the others are assigned correctly by default
-ftdi_layout_signal nTRST -ndata 0x0010
-
-set _CHIPNAME riscv
-jtag newtap $_CHIPNAME cpu -irlen 5
-
-set _TARGETNAME $_CHIPNAME.cpu
-target create $_TARGETNAME riscv -chain-position $_TARGETNAME -coreid 0
-
-gdb_report_data_abort enable
-gdb_report_register_access_error enable
-
-riscv set_reset_timeout_sec 120
-riscv set_command_timeout_sec 120
-
-# prefer to use sba for system bus access
-riscv set_prefer_sba off
-
-# Try enabling address translation (only works for newer versions)
-if { [catch {riscv set_enable_virtual on} ] } {
- echo "Warning: This version of OpenOCD does not support address translation. To debug on virtual addresses, please update to the latest version." }
-
-init
-halt
-echo "Ready for Remote Connections"
diff --git a/fpga/ariane_pmod.cfg b/fpga/ariane_pmod.cfg
deleted file mode 100644
index 21da8599..00000000
--- a/fpga/ariane_pmod.cfg
+++ /dev/null
@@ -1,30 +0,0 @@
-adapter_khz 1000
-
-interface ftdi
-# ftdi_device_desc "Olimex Ltd. ARM-USB-OCD-H JTAG+RS232"
-ftdi_vid_pid 0x15ba 0x002b
-
-ftdi_layout_init 0x0808 0x0a1b
-ftdi_layout_signal nSRST -oe 0x0200
-ftdi_layout_signal nTRST -data 0x0100 -oe 0x0100
-ftdi_layout_signal LED -data 0x0800
-
-set _CHIPNAME riscv
-jtag newtap $_CHIPNAME cpu -irlen 5
-
-set _TARGETNAME $_CHIPNAME.cpu
-# select the HART to debug with the coreid switch
-target create $_TARGETNAME riscv -chain-position $_TARGETNAME -coreid 0
-
-gdb_report_data_abort enable
-gdb_report_register_access_error enable
-
-riscv set_reset_timeout_sec 120
-riscv set_command_timeout_sec 120
-
-# prefer to use sba for system bus access
-riscv set_prefer_sba off
-
-init
-halt
-echo "Ready for Remote Connections"
diff --git a/fpga/ariane_pmod_tiny.cfg b/fpga/ariane_pmod_tiny.cfg
deleted file mode 100644
index bc8a500c..00000000
--- a/fpga/ariane_pmod_tiny.cfg
+++ /dev/null
@@ -1,30 +0,0 @@
-adapter_khz 1000
-
-interface ftdi
-ftdi_device_desc "Olimex OpenOCD JTAG ARM-USB-TINY-H"
-ftdi_vid_pid 0x15ba 0x002a
-
-ftdi_layout_init 0x0808 0x0a1b
-ftdi_layout_signal nSRST -oe 0x0200
-ftdi_layout_signal nTRST -data 0x0100 -oe 0x0100
-ftdi_layout_signal LED -data 0x0800
-
-set _CHIPNAME riscv
-jtag newtap $_CHIPNAME cpu -irlen 5
-
-set _TARGETNAME $_CHIPNAME.cpu
-# select the HART to debug with the coreid switch
-target create $_TARGETNAME riscv -chain-position $_TARGETNAME -coreid 0
-
-gdb_report_data_abort enable
-gdb_report_register_access_error enable
-
-riscv set_reset_timeout_sec 120
-riscv set_command_timeout_sec 120
-
-# prefer to use sba for system bus access
-riscv set_prefer_sba off
-
-init
-halt
-echo "Ready for Remote Connections"
diff --git a/fpga/constraints/ariane.xdc b/fpga/constraints/ariane.xdc
deleted file mode 100644
index 714bc451..00000000
--- a/fpga/constraints/ariane.xdc
+++ /dev/null
@@ -1,19 +0,0 @@
-## Common Ariane XDCs
-
-create_clock -period 100.000 -name tck -waveform {0.000 50.000} [get_ports tck]
-set_input_jitter tck 1.000
-
-# minimize routing delay
-set_input_delay -clock tck -clock_fall 5 [get_ports tdi ]
-set_input_delay -clock tck -clock_fall 5 [get_ports tms ]
-set_output_delay -clock tck 5 [get_ports tdo ]
-set_false_path -from [get_ports trst_n ]
-
-
-set_max_delay -datapath_only -from [get_pins i_dmi_jtag/i_dmi_cdc/i_cdc_resp/i_src/data_src_q_reg*/C] -to [get_pins i_dmi_jtag/i_dmi_cdc/i_cdc_resp/i_dst/data_dst_q_reg*/D] 20.000
-set_max_delay -datapath_only -from [get_pins i_dmi_jtag/i_dmi_cdc/i_cdc_resp/i_src/req_src_q_reg/C] -to [get_pins i_dmi_jtag/i_dmi_cdc/i_cdc_resp/i_dst/req_dst_q_reg/D] 20.000
-set_max_delay -datapath_only -from [get_pins i_dmi_jtag/i_dmi_cdc/i_cdc_req/i_dst/ack_dst_q_reg/C] -to [get_pins i_dmi_jtag/i_dmi_cdc/i_cdc_req/i_src/ack_src_q_reg/D] 20.000
-
-# set multicycle path on reset, on the FPGA we do not care about the reset anyway
-set_multicycle_path -from [get_pins i_rstgen_main/i_rstgen_bypass/synch_regs_q_reg[3]/C] 4
-set_multicycle_path -from [get_pins i_rstgen_main/i_rstgen_bypass/synch_regs_q_reg[3]/C] 3 -hold
diff --git a/fpga/constraints/genesys-2.xdc b/fpga/constraints/genesys-2.xdc
deleted file mode 100644
index 52fd7144..00000000
--- a/fpga/constraints/genesys-2.xdc
+++ /dev/null
@@ -1,127 +0,0 @@
-## Buttons
-set_property -dict {PACKAGE_PIN R19 IOSTANDARD LVCMOS33} [get_ports cpu_resetn]
-
-## To use FTDI FT2232 JTAG
-set_property -dict { PACKAGE_PIN Y29 IOSTANDARD LVCMOS33 } [get_ports { trst_n }];
-set_property -dict { PACKAGE_PIN AD27 IOSTANDARD LVCMOS33 } [get_ports { tck }];
-set_property -dict { PACKAGE_PIN W27 IOSTANDARD LVCMOS33 } [get_ports { tdi }];
-set_property -dict { PACKAGE_PIN W28 IOSTANDARD LVCMOS33 } [get_ports { tdo }];
-set_property -dict { PACKAGE_PIN W29 IOSTANDARD LVCMOS33 } [get_ports { tms }];
-
-## UART
-set_property -dict {PACKAGE_PIN Y23 IOSTANDARD LVCMOS33} [get_ports tx]
-set_property -dict {PACKAGE_PIN Y20 IOSTANDARD LVCMOS33} [get_ports rx]
-
-
-## LEDs
-set_property -dict {PACKAGE_PIN T28 IOSTANDARD LVCMOS33} [get_ports {led[0]}]
-set_property -dict {PACKAGE_PIN V19 IOSTANDARD LVCMOS33} [get_ports {led[1]}]
-set_property -dict {PACKAGE_PIN U30 IOSTANDARD LVCMOS33} [get_ports {led[2]}]
-set_property -dict {PACKAGE_PIN U29 IOSTANDARD LVCMOS33} [get_ports {led[3]}]
-set_property -dict {PACKAGE_PIN V20 IOSTANDARD LVCMOS33} [get_ports {led[4]}]
-set_property -dict {PACKAGE_PIN V26 IOSTANDARD LVCMOS33} [get_ports {led[5]}]
-set_property -dict {PACKAGE_PIN W24 IOSTANDARD LVCMOS33} [get_ports {led[6]}]
-set_property -dict {PACKAGE_PIN W23 IOSTANDARD LVCMOS33} [get_ports {led[7]}]
-
-## Switches
-set_property -dict {PACKAGE_PIN G19 IOSTANDARD LVCMOS12} [get_ports {sw[0]}]
-set_property -dict {PACKAGE_PIN G25 IOSTANDARD LVCMOS12} [get_ports {sw[1]}]
-set_property -dict {PACKAGE_PIN H24 IOSTANDARD LVCMOS12} [get_ports {sw[2]}]
-set_property -dict {PACKAGE_PIN K19 IOSTANDARD LVCMOS12} [get_ports {sw[3]}]
-set_property -dict {PACKAGE_PIN N19 IOSTANDARD LVCMOS12} [get_ports {sw[4]}]
-set_property -dict {PACKAGE_PIN P19 IOSTANDARD LVCMOS12} [get_ports {sw[5]}]
-set_property -dict {PACKAGE_PIN P26 IOSTANDARD LVCMOS33} [get_ports {sw[6]}]
-set_property -dict {PACKAGE_PIN P27 IOSTANDARD LVCMOS33} [get_ports {sw[7]}]
-
-## Fan Control
-set_property -dict {PACKAGE_PIN W19 IOSTANDARD LVCMOS33} [get_ports fan_pwm]
-#set_property -dict { PACKAGE_PIN V21 IOSTANDARD LVCMOS33 } [get_ports { FAN_TACH }]; #IO_L22P_T3_A05_D21_14 Sch=fan_tac
-
-## Ethernet
-set_property -dict {PACKAGE_PIN AH24 IOSTANDARD LVCMOS33} [get_ports { eth_rst_n }]; #IO_L14N_T2_SRCC_12 Sch=eth_phyrst_n
-set_property -dict {PACKAGE_PIN AE10 IOSTANDARD LVCMOS15} [get_ports { eth_txck }]; #IO_L14P_T2_SRCC_33 Sch=eth_tx_clk
-set_property -dict {PACKAGE_PIN AK14 IOSTANDARD LVCMOS15} [get_ports { eth_txctl }]; #IO_L20P_T3_33 Sch=eth_tx_en
-set_property -dict {PACKAGE_PIN AJ12 IOSTANDARD LVCMOS15} [get_ports { eth_txd[0] }]; #IO_L22N_T3_33 Sch=eth_tx_d[0]
-set_property -dict {PACKAGE_PIN AK11 IOSTANDARD LVCMOS15} [get_ports { eth_txd[1] }]; #IO_L17P_T2_33 Sch=eth_tx_d[1]
-set_property -dict {PACKAGE_PIN AJ11 IOSTANDARD LVCMOS15} [get_ports { eth_txd[2] }]; #IO_L18N_T2_33 Sch=eth_tx_d[2]
-set_property -dict {PACKAGE_PIN AK10 IOSTANDARD LVCMOS15} [get_ports { eth_txd[3] }]; #IO_L17N_T2_33 Sch=eth_tx_d[3]
-set_property -dict {PACKAGE_PIN AJ14 IOSTANDARD LVCMOS15} [get_ports { eth_rxd[0] }]; #IO_L21N_T3_DQS_33 Sch=eth_rx_d[0]
-set_property -dict {PACKAGE_PIN AG10 IOSTANDARD LVCMOS15} [get_ports { eth_rxck }]; #IO_L13P_T2_MRCC_33 Sch=eth_rx_clk
-set_property -dict {PACKAGE_PIN AH11 IOSTANDARD LVCMOS15} [get_ports { eth_rxctl }]; #IO_L18P_T2_33 Sch=eth_rx_ctl
-set_property -dict {PACKAGE_PIN AH14 IOSTANDARD LVCMOS15} [get_ports { eth_rxd[1] }]; #IO_L21P_T3_DQS_33 Sch=eth_rx_d[1]
-set_property -dict {PACKAGE_PIN AK13 IOSTANDARD LVCMOS15} [get_ports { eth_rxd[2] }]; #IO_L20N_T3_33 Sch=eth_rx_d[2]
-set_property -dict {PACKAGE_PIN AJ13 IOSTANDARD LVCMOS15} [get_ports { eth_rxd[3] }]; #IO_L22P_T3_33 Sch=eth_rx_d[3]
-set_property -dict {PACKAGE_PIN AF12 IOSTANDARD LVCMOS15} [get_ports { eth_mdc }]; #IO_L23P_T3_33 Sch=eth_mdc
-set_property -dict {PACKAGE_PIN AG12 IOSTANDARD LVCMOS15} [get_ports { eth_mdio }]; #IO_L23N_T3_33 Sch=eth_mdio
-
-# set_property -dict {PACKAGE_PIN AK15 IOSTANDARD LVCMOS18} [get_ports { eth_pme_b }]; #IO_L1N_T0_32 Sch=eth_pmeb
-# set_property -dict {PACKAGE_PIN AK16 IOSTANDARD LVCMOS18} [get_ports { eth_int_b }]; #IO_L1P_T0_32 Sch=eth_intb
-
-#############################################
-# Ethernet Constraints for 1Gb/s
-#############################################
-# Modified for 125MHz receive clock
-create_clock -period 8.000 -name eth_rxck [get_ports eth_rxck]
-
-set_clock_groups -asynchronous -group [get_clocks eth_rxck -include_generated_clocks]
-set_clock_groups -asynchronous -group [get_clocks clk_out2_xlnx_clk_gen]
-
-#############################################
-## SD Card
-#############################################
-set_property -dict {PACKAGE_PIN R28 IOSTANDARD LVCMOS33} [get_ports spi_clk_o]
-set_property -dict {PACKAGE_PIN T30 IOSTANDARD LVCMOS33} [get_ports spi_ss]
-set_property -dict {PACKAGE_PIN R26 IOSTANDARD LVCMOS33} [get_ports spi_miso]
-set_property -dict {PACKAGE_PIN R29 IOSTANDARD LVCMOS33} [get_ports spi_mosi]
-# set_property -dict { PACKAGE_PIN P28 IOSTANDARD LVCMOS33 } [get_ports { sd_cd }]; #IO_L8N_T1_D12_14 Sch=sd_cd
-# set_property -dict { PACKAGE_PIN R29 IOSTANDARD LVCMOS33 } [get_ports { sd_cmd }]; #IO_L7N_T1_D10_14 Sch=sd_cmd
-# set_property -dict { PACKAGE_PIN R26 IOSTANDARD LVCMOS33 } [get_ports { sd_dat[0] }]; #IO_L10N_T1_D15_14 Sch=sd_dat[0]
-# set_property -dict { PACKAGE_PIN R30 IOSTANDARD LVCMOS33 } [get_ports { sd_dat[1] }]; #IO_L9P_T1_DQS_14 Sch=sd_dat[1]
-# set_property -dict { PACKAGE_PIN P29 IOSTANDARD LVCMOS33 } [get_ports { sd_dat[2] }]; #IO_L7P_T1_D09_14 Sch=sd_dat[2]
-# set_property -dict { PACKAGE_PIN T30 IOSTANDARD LVCMOS33 } [get_ports { sd_dat[3] }]; #IO_L9N_T1_DQS_D13_14 Sch=sd_dat[3]
-# set_property -dict { PACKAGE_PIN AE24 IOSTANDARD LVCMOS33 } [get_ports { sd_reset }]; #IO_L12N_T1_MRCC_12 Sch=sd_reset
-# set_property -dict { PACKAGE_PIN R28 IOSTANDARD LVCMOS33 } [get_ports { sd_clk }]; #IO_L11P_T1_SRCC_14 Sch=sd_sclk
-
-# create_generated_clock -name sd_fast_clk -source [get_pins clk_mmcm/sd_sys_clk] -divide_by 2 [get_pins chipset_impl/piton_sd_top/sdc_controller/clock_divider0/fast_clk_reg/Q]
-# create_generated_clock -name sd_slow_clk -source [get_pins clk_mmcm/sd_sys_clk] -divide_by 200 [get_pins chipset_impl/piton_sd_top/sdc_controller/clock_divider0/slow_clk_reg/Q]
-# create_generated_clock -name sd_clk_out -source [get_pins sd_clk_oddr/C] -divide_by 1 -add -master_clock sd_fast_clk [get_ports sd_clk_out]
-# create_generated_clock -name sd_clk_out_1 -source [get_pins sd_clk_oddr/C] -divide_by 1 -add -master_clock sd_slow_clk [get_ports sd_clk_out]
-
-# create_clock -period 40.000 -name VIRTUAL_sd_fast_clk -waveform {0.000 20.000}
-# create_clock -period 4000.000 -name VIRTUAL_sd_slow_clk -waveform {0.000 2000.000}
-
-# set_output_delay -clock [get_clocks sd_clk_out] -min -add_delay 5.000 [get_ports {sd_dat[*]}]
-# set_output_delay -clock [get_clocks sd_clk_out] -max -add_delay 15.000 [get_ports {sd_dat[*]}]
-# set_output_delay -clock [get_clocks sd_clk_out_1] -min -add_delay 5.000 [get_ports {sd_dat[*]}]
-# set_output_delay -clock [get_clocks sd_clk_out_1] -max -add_delay 1500.000 [get_ports {sd_dat[*]}]
-# set_output_delay -clock [get_clocks sd_clk_out] -min -add_delay 5.000 [get_ports sd_cmd]
-# set_output_delay -clock [get_clocks sd_clk_out] -max -add_delay 15.000 [get_ports sd_cmd]
-# set_output_delay -clock [get_clocks sd_clk_out_1] -min -add_delay 5.000 [get_ports sd_cmd]
-# set_output_delay -clock [get_clocks sd_clk_out_1] -max -add_delay 1500.000 [get_ports sd_cmd]
-# set_input_delay -clock [get_clocks VIRTUAL_sd_fast_clk] -min -add_delay 20.000 [get_ports {sd_dat[*]}]
-# set_input_delay -clock [get_clocks VIRTUAL_sd_fast_clk] -max -add_delay 35.000 [get_ports {sd_dat[*]}]
-# set_input_delay -clock [get_clocks VIRTUAL_sd_slow_clk] -min -add_delay 2000.000 [get_ports {sd_dat[*]}]
-# set_input_delay -clock [get_clocks VIRTUAL_sd_slow_clk] -max -add_delay 3500.000 [get_ports {sd_dat[*]}]
-# set_input_delay -clock [get_clocks VIRTUAL_sd_fast_clk] -min -add_delay 20.000 [get_ports sd_cmd]
-# set_input_delay -clock [get_clocks VIRTUAL_sd_fast_clk] -max -add_delay 35.000 [get_ports sd_cmd]
-# set_input_delay -clock [get_clocks VIRTUAL_sd_slow_clk] -min -add_delay 2000.000 [get_ports sd_cmd]
-# set_input_delay -clock [get_clocks VIRTUAL_sd_slow_clk] -max -add_delay 3500.000 [get_ports sd_cmd]
-# set_clock_groups -physically_exclusive -group [get_clocks -include_generated_clocks sd_clk_out] -group [get_clocks -include_generated_clocks sd_clk_out_1]
-# set_clock_groups -logically_exclusive -group [get_clocks -include_generated_clocks {VIRTUAL_sd_fast_clk sd_fast_clk}] -group [get_clocks -include_generated_clocks {sd_slow_clk VIRTUAL_sd_slow_clk}]
-# set_clock_groups -asynchronous -group [get_clocks [list [get_clocks -of_objects [get_pins clk_mmcm/chipset_clk]]]] -group [get_clocks -filter { NAME =~ "*sd*" }]
-
-
-# Genesys 2 has a quad SPI flash
-set_property BITSTREAM.CONFIG.SPI_BUSWIDTH 4 [current_design]
-
-## JTAG
-# minimize routing delay
-
-set_max_delay -to [get_ports { tdo } ] 20
-set_max_delay -from [get_ports { tms } ] 20
-set_max_delay -from [get_ports { tdi } ] 20
-set_max_delay -from [get_ports { trst_n } ] 20
-
-# reset signal
-set_false_path -from [get_ports { trst_n } ]
-set_false_path -from [get_pins i_ddr/u_xlnx_mig_7_ddr3_mig/u_ddr3_infrastructure/rstdiv0_sync_r1_reg_rep/C]
diff --git a/fpga/constraints/kc705.xdc b/fpga/constraints/kc705.xdc
deleted file mode 100644
index 833a1b6a..00000000
--- a/fpga/constraints/kc705.xdc
+++ /dev/null
@@ -1,203 +0,0 @@
-## Buttons
-set_property -dict {PACKAGE_PIN AB7 IOSTANDARD LVCMOS15} [get_ports cpu_reset]
-set_property slave_banks {32 34} [get_iobanks 33]
-
-# on board differential clock, 200MHz
-set_property PACKAGE_PIN AD12 [get_ports sys_clk_p]
-set_property PACKAGE_PIN AD11 [get_ports sys_clk_n]
-set_property IOSTANDARD DIFF_SSTL15 [get_ports sys_clk_n]
-
-
-## To use FTDI FT2232 JTAG
-# Reset Not connected because optional?
-set_property -dict { PACKAGE_PIN D29 IOSTANDARD LVCMOS33 } [get_ports { tck }];
-set_property -dict { PACKAGE_PIN G27 IOSTANDARD LVCMOS33 } [get_ports { trst_n }];
-set_property -dict { PACKAGE_PIN C29 IOSTANDARD LVCMOS33 } [get_ports { tdo }];
-set_property -dict { PACKAGE_PIN A25 IOSTANDARD LVCMOS33 } [get_ports { tdi }];
-set_property -dict { PACKAGE_PIN B28 IOSTANDARD LVCMOS33 } [get_ports { tms }];
-set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets tck_IBUF]
-
-## UART
-set_property -dict {PACKAGE_PIN K24 IOSTANDARD LVCMOS25} [get_ports tx]
-set_property -dict {PACKAGE_PIN M19 IOSTANDARD LVCMOS25} [get_ports rx]
-
-
-## LEDs
-# set_property -dict {PACKAGE_PIN DS4 IOSTANDARD LVCMOS25} [get_ports {led[0]}]
-# set_property -dict {PACKAGE_PIN DS1 IOSTANDARD LVCMOS25} [get_ports {led[1]}]
-# set_property -dict {PACKAGE_PIN DS10 IOSTANDARD LVCMOS25} [get_ports {led[2]}]
-# set_property -dict {PACKAGE_PIN DS2 IOSTANDARD LVCMOS25} [get_ports {led[3]}]
-# set_property -dict {PACKAGE_PIN DS3 IOSTANDARD LVCMOS25} [get_ports {led[4]}]
-# set_property -dict {PACKAGE_PIN DS25 IOSTANDARD LVCMOS25} [get_ports {led[5]}]
-# set_property -dict {PACKAGE_PIN DS26 IOSTANDARD LVCMOS25} [get_ports {led[6]}]
-# set_property -dict {PACKAGE_PIN DS27 IOSTANDARD LVCMOS25} [get_ports {led[7]}]
-
-#set_property IOSTANDARD LVCMOS15 [get_ports {led[0]}]
-#set_property SLEW SLOW [get_ports {led[0]}]
-#set_property DRIVE 4 [get_ports {led[0]}]
-#set_property LOC AB8 [get_ports {led[0]}]
-#set_property IOSTANDARD LVCMOS15 [get_ports {led[1]}]
-#set_property SLEW SLOW [get_ports {led[1]}]
-#set_property DRIVE 4 [get_ports {led[1]}]
-#set_property LOC AA8 [get_ports {led[1]}]
-#set_property IOSTANDARD LVCMOS15 [get_ports {led[2]}]
-#set_property SLEW SLOW [get_ports {led[2]}]
-#set_property DRIVE 4 [get_ports {led[2]}]
-#set_property LOC AC9 [get_ports {led[2]}]
-#set_property IOSTANDARD LVCMOS15 [get_ports {led[3]}]
-#set_property SLEW SLOW [get_ports {led[3]}]
-#set_property DRIVE 4 [get_ports {led[3]}]
-#set_property LOC AB9 [get_ports {led[3]}]
-#set_property IOSTANDARD LVCMOS25 [get_ports {led[4]}]
-#set_property SLEW SLOW [get_ports {led[4]}]
-#set_property DRIVE 4 [get_ports {led[4]}]
-#set_property LOC AE26 [get_ports {led[4]}]
-#set_property IOSTANDARD LVCMOS25 [get_ports {led[5]}]
-#set_property SLEW SLOW [get_ports {led[5]}]
-#set_property DRIVE 4 [get_ports {led[5]}]
-#set_property LOC G19 [get_ports {led[5]}]
-#set_property IOSTANDARD LVCMOS25 [get_ports {led[6]}]
-#set_property SLEW SLOW [get_ports {led[6]}]
-#set_property DRIVE 4 [get_ports {led[6]}]
-#set_property LOC E18 [get_ports {led[6]}]
-#set_property IOSTANDARD LVCMOS25 [get_ports {led[7]}]
-#set_property SLEW SLOW [get_ports {led[7]}]
-#set_property DRIVE 4 [get_ports {led[7]}]
-#set_property LOC F16 [get_ports {led[7]}]
-
-set_property IOSTANDARD LVCMOS25 [get_ports {led[0]}]
-set_property SLEW SLOW [get_ports {led[0]}]
-set_property DRIVE 4 [get_ports {led[0]}]
-set_property LOC AE26 [get_ports {led[0]}]
-set_property IOSTANDARD LVCMOS25 [get_ports {led[1]}]
-set_property SLEW SLOW [get_ports {led[1]}]
-set_property DRIVE 4 [get_ports {led[1]}]
-set_property LOC G19 [get_ports {led[1]}]
-set_property IOSTANDARD LVCMOS25 [get_ports {led[2]}]
-set_property SLEW SLOW [get_ports {led[2]}]
-set_property DRIVE 4 [get_ports {led[2]}]
-set_property LOC E18 [get_ports {led[2]}]
-set_property IOSTANDARD LVCMOS25 [get_ports {led[3]}]
-set_property SLEW SLOW [get_ports {led[3]}]
-set_property DRIVE 4 [get_ports {led[3]}]
-set_property LOC F16 [get_ports {led[3]}]
-#set_property IOSTANDARD LVCMOS15 [get_ports {led[4]}]
-#set_property SLEW SLOW [get_ports {led[4]}]
-#set_property DRIVE 4 [get_ports {led[4]}]
-#set_property LOC AB8 [get_ports {led[4]}]
-#set_property IOSTANDARD LVCMOS15 [get_ports {led[5]}]
-#set_property SLEW SLOW [get_ports {led[5]}]
-#set_property DRIVE 4 [get_ports {led[5]}]
-#set_property LOC AA8 [get_ports {led[5]}]
-#set_property IOSTANDARD LVCMOS15 [get_ports {led[6]}]
-#set_property SLEW SLOW [get_ports {led[6]}]
-#set_property DRIVE 4 [get_ports {led[6]}]
-#set_property LOC AC9 [get_ports {led[6]}]
-#set_property IOSTANDARD LVCMOS15 [get_ports {led[7]}]
-#set_property SLEW SLOW [get_ports {led[7]}]
-#set_property DRIVE 4 [get_ports {led[7]}]
-#set_property LOC AB9 [get_ports {led[7]}]
-
-
-## Switches
-set_property -dict {PACKAGE_PIN Y29 IOSTANDARD LVCMOS25} [get_ports {sw[0]}]
-set_property -dict {PACKAGE_PIN W29 IOSTANDARD LVCMOS25} [get_ports {sw[1]}]
-set_property -dict {PACKAGE_PIN AA28 IOSTANDARD LVCMOS25} [get_ports {sw[2]}]
-set_property -dict {PACKAGE_PIN Y28 IOSTANDARD LVCMOS25} [get_ports {sw[3]}]
-#set_property -dict {PACKAGE_PIN N19 IOSTANDARD LVCMOS12} [get_ports {sw[4]}]
-#set_property -dict {PACKAGE_PIN P19 IOSTANDARD LVCMOS12} [get_ports {sw[5]}]
-#set_property -dict {PACKAGE_PIN P26 IOSTANDARD LVCMOS33} [get_ports {sw[6]}]
-#set_property -dict {PACKAGE_PIN P27 IOSTANDARD LVCMOS33} [get_ports {sw[7]}]
-
-## Fan Control
-set_property -dict {PACKAGE_PIN L26 IOSTANDARD LVCMOS25} [get_ports fan_pwm]
-#set_property -dict { PACKAGE_PIN U22 IOSTANDARD LVCMOS33 } [get_ports { FAN_TACH }]; #IO_L22P_T3_A05_D21_14 Sch=fan_tac
-
-## Ethernet
-set_property -dict {PACKAGE_PIN L20 IOSTANDARD LVCMOS25} [get_ports { eth_rst_n }]; #IO_L14N_T2_SRCC_12 Sch=eth_phyrst_n
-set_property -dict {PACKAGE_PIN M28 IOSTANDARD LVCMOS25} [get_ports { eth_txck }]; #IO_L14P_T2_SRCC_33 Sch=eth_tx_clk
-set_property -dict {PACKAGE_PIN M27 IOSTANDARD LVCMOS25} [get_ports { eth_txctl }]; #IO_L20P_T3_33 Sch=eth_tx_en
-set_property -dict {PACKAGE_PIN N27 IOSTANDARD LVCMOS25} [get_ports { eth_txd[0] }]; #IO_L22N_T3_33 Sch=eth_tx_d[0]
-set_property -dict {PACKAGE_PIN N25 IOSTANDARD LVCMOS25} [get_ports { eth_txd[1] }]; #IO_L17P_T2_33 Sch=eth_tx_d[1]
-set_property -dict {PACKAGE_PIN M29 IOSTANDARD LVCMOS25} [get_ports { eth_txd[2] }]; #IO_L18N_T2_33 Sch=eth_tx_d[2]
-set_property -dict {PACKAGE_PIN L28 IOSTANDARD LVCMOS25} [get_ports { eth_txd[3] }]; #IO_L17N_T2_33 Sch=eth_tx_d[3]
-set_property -dict {PACKAGE_PIN U30 IOSTANDARD LVCMOS25} [get_ports { eth_rxd[0] }]; #IO_L21N_T3_DQS_33 Sch=eth_rx_d[0]
-set_property -dict {PACKAGE_PIN U27 IOSTANDARD LVCMOS25} [get_ports { eth_rxck }]; #IO_L13P_T2_MRCC_33 Sch=eth_rx_clk
-set_property -dict {PACKAGE_PIN V26 IOSTANDARD LVCMOS25} [get_ports { eth_rxctl }]; #IO_L18P_T2_33 Sch=eth_rx_ctl
-set_property -dict {PACKAGE_PIN U25 IOSTANDARD LVCMOS25} [get_ports { eth_rxd[1] }]; #IO_L21P_T3_DQS_33 Sch=eth_rx_d[1]
-set_property -dict {PACKAGE_PIN T25 IOSTANDARD LVCMOS25} [get_ports { eth_rxd[2] }]; #IO_L20N_T3_33 Sch=eth_rx_d[2]
-set_property -dict {PACKAGE_PIN U28 IOSTANDARD LVCMOS25} [get_ports { eth_rxd[3] }]; #IO_L22P_T3_33 Sch=eth_rx_d[3]
-set_property -dict {PACKAGE_PIN R23 IOSTANDARD LVCMOS25} [get_ports { eth_mdc }]; #IO_L23P_T3_33 Sch=eth_mdc
-set_property -dict {PACKAGE_PIN J21 IOSTANDARD LVCMOS25} [get_ports { eth_mdio }]; #IO_L23N_T3_33 Sch=eth_mdio
-
-# set_property -dict {PACKAGE_PIN AK15 IOSTANDARD LVCMOS18} [get_ports { eth_pme_b }]; #IO_L1N_T0_32 Sch=eth_pmeb
-# set_property -dict {PACKAGE_PIN AK16 IOSTANDARD LVCMOS18} [get_ports { eth_int_b }]; #IO_L1P_T0_32 Sch=eth_intb
-
-#############################################
-# Ethernet Constraints for 1Gb/s
-#############################################
-# Modified for 125MHz receive clock
-create_clock -period 8.000 -name eth_rxck [get_ports eth_rxck]
-
-set_clock_groups -asynchronous -group [get_clocks eth_rxck -include_generated_clocks]
-set_clock_groups -asynchronous -group [get_clocks clk_out2_xlnx_clk_gen]
-
-#############################################
-## SD Card
-#############################################
-set_property -dict {PACKAGE_PIN AB23 IOSTANDARD LVCMOS25} [get_ports spi_clk_o]
-set_property -dict {PACKAGE_PIN AC21 IOSTANDARD LVCMOS25} [get_ports spi_ss]
-set_property -dict {PACKAGE_PIN AC20 IOSTANDARD LVCMOS25} [get_ports spi_miso]
-set_property -dict {PACKAGE_PIN AB22 IOSTANDARD LVCMOS25} [get_ports spi_mosi]
-# set_property -dict { PACKAGE_PIN P28 IOSTANDARD LVCMOS33 } [get_ports { sd_cd }]; #IO_L8N_T1_D12_14 Sch=sd_cd
-# set_property -dict { PACKAGE_PIN R29 IOSTANDARD LVCMOS33 } [get_ports { sd_cmd }]; #IO_L7N_T1_D10_14 Sch=sd_cmd
-# set_property -dict { PACKAGE_PIN R26 IOSTANDARD LVCMOS33 } [get_ports { sd_dat[0] }]; #IO_L10N_T1_D15_14 Sch=sd_dat[0]
-# set_property -dict { PACKAGE_PIN R30 IOSTANDARD LVCMOS33 } [get_ports { sd_dat[1] }]; #IO_L9P_T1_DQS_14 Sch=sd_dat[1]
-# set_property -dict { PACKAGE_PIN P29 IOSTANDARD LVCMOS33 } [get_ports { sd_dat[2] }]; #IO_L7P_T1_D09_14 Sch=sd_dat[2]
-# set_property -dict { PACKAGE_PIN T30 IOSTANDARD LVCMOS33 } [get_ports { sd_dat[3] }]; #IO_L9N_T1_DQS_D13_14 Sch=sd_dat[3]
-# set_property -dict { PACKAGE_PIN AE24 IOSTANDARD LVCMOS33 } [get_ports { sd_reset }]; #IO_L12N_T1_MRCC_12 Sch=sd_reset
-# set_property -dict { PACKAGE_PIN R28 IOSTANDARD LVCMOS33 } [get_ports { sd_clk }]; #IO_L11P_T1_SRCC_14 Sch=sd_sclk
-
-# create_generated_clock -name sd_fast_clk -source [get_pins clk_mmcm/sd_sys_clk] -divide_by 2 [get_pins chipset_impl/piton_sd_top/sdc_controller/clock_divider0/fast_clk_reg/Q]
-# create_generated_clock -name sd_slow_clk -source [get_pins clk_mmcm/sd_sys_clk] -divide_by 200 [get_pins chipset_impl/piton_sd_top/sdc_controller/clock_divider0/slow_clk_reg/Q]
-# create_generated_clock -name sd_clk_out -source [get_pins sd_clk_oddr/C] -divide_by 1 -add -master_clock sd_fast_clk [get_ports sd_clk_out]
-# create_generated_clock -name sd_clk_out_1 -source [get_pins sd_clk_oddr/C] -divide_by 1 -add -master_clock sd_slow_clk [get_ports sd_clk_out]
-
-# create_clock -period 40.000 -name VIRTUAL_sd_fast_clk -waveform {0.000 20.000}
-# create_clock -period 4000.000 -name VIRTUAL_sd_slow_clk -waveform {0.000 2000.000}
-
-# set_output_delay -clock [get_clocks sd_clk_out] -min -add_delay 5.000 [get_ports {sd_dat[*]}]
-# set_output_delay -clock [get_clocks sd_clk_out] -max -add_delay 15.000 [get_ports {sd_dat[*]}]
-# set_output_delay -clock [get_clocks sd_clk_out_1] -min -add_delay 5.000 [get_ports {sd_dat[*]}]
-# set_output_delay -clock [get_clocks sd_clk_out_1] -max -add_delay 1500.000 [get_ports {sd_dat[*]}]
-# set_output_delay -clock [get_clocks sd_clk_out] -min -add_delay 5.000 [get_ports sd_cmd]
-# set_output_delay -clock [get_clocks sd_clk_out] -max -add_delay 15.000 [get_ports sd_cmd]
-# set_output_delay -clock [get_clocks sd_clk_out_1] -min -add_delay 5.000 [get_ports sd_cmd]
-# set_output_delay -clock [get_clocks sd_clk_out_1] -max -add_delay 1500.000 [get_ports sd_cmd]
-# set_input_delay -clock [get_clocks VIRTUAL_sd_fast_clk] -min -add_delay 20.000 [get_ports {sd_dat[*]}]
-# set_input_delay -clock [get_clocks VIRTUAL_sd_fast_clk] -max -add_delay 35.000 [get_ports {sd_dat[*]}]
-# set_input_delay -clock [get_clocks VIRTUAL_sd_slow_clk] -min -add_delay 2000.000 [get_ports {sd_dat[*]}]
-# set_input_delay -clock [get_clocks VIRTUAL_sd_slow_clk] -max -add_delay 3500.000 [get_ports {sd_dat[*]}]
-# set_input_delay -clock [get_clocks VIRTUAL_sd_fast_clk] -min -add_delay 20.000 [get_ports sd_cmd]
-# set_input_delay -clock [get_clocks VIRTUAL_sd_fast_clk] -max -add_delay 35.000 [get_ports sd_cmd]
-# set_input_delay -clock [get_clocks VIRTUAL_sd_slow_clk] -min -add_delay 2000.000 [get_ports sd_cmd]
-# set_input_delay -clock [get_clocks VIRTUAL_sd_slow_clk] -max -add_delay 3500.000 [get_ports sd_cmd]
-# set_clock_groups -physically_exclusive -group [get_clocks -include_generated_clocks sd_clk_out] -group [get_clocks -include_generated_clocks sd_clk_out_1]
-# set_clock_groups -logically_exclusive -group [get_clocks -include_generated_clocks {VIRTUAL_sd_fast_clk sd_fast_clk}] -group [get_clocks -include_generated_clocks {sd_slow_clk VIRTUAL_sd_slow_clk}]
-# set_clock_groups -asynchronous -group [get_clocks [list [get_clocks -of_objects [get_pins clk_mmcm/chipset_clk]]]] -group [get_clocks -filter { NAME =~ "*sd*" }]
-
-
-# Genesys 2 has a quad SPI flash
-set_property BITSTREAM.CONFIG.SPI_BUSWIDTH 4 [current_design]
-
-## JTAG
-# minimize routing delay
-
-set_max_delay -to [get_ports { tdo } ] 20
-set_max_delay -from [get_ports { tms } ] 20
-set_max_delay -from [get_ports { tdi } ] 20
-set_max_delay -from [get_ports { trst_n } ] 20
-
-# reset signal
-set_false_path -from [get_ports { trst_n } ]
-set_false_path -from [get_pins i_ddr/u_xlnx_mig_7_ddr3_mig/u_ddr3_infrastructure/rstdiv0_sync_r1_reg_rep/C]
diff --git a/fpga/constraints/vc707.xdc b/fpga/constraints/vc707.xdc
deleted file mode 100644
index 959a6819..00000000
--- a/fpga/constraints/vc707.xdc
+++ /dev/null
@@ -1,127 +0,0 @@
-## Buttons
-set_property -dict {PACKAGE_PIN AV40 IOSTANDARD LVCMOS18} [get_ports cpu_reset]
-
-## To use FTDI FT2232 JTAG
-set_property -dict { PACKAGE_PIN AV39 IOSTANDARD LVCMOS18 } [get_ports trst];
-set_property -dict { PACKAGE_PIN M32 IOSTANDARD LVCMOS18 } [get_ports tck ];
-set_property -dict { PACKAGE_PIN V29 IOSTANDARD LVCMOS18 } [get_ports tdi ];
-set_property -dict { PACKAGE_PIN M28 IOSTANDARD LVCMOS18 } [get_ports tdo ];
-set_property -dict { PACKAGE_PIN U31 IOSTANDARD LVCMOS18 } [get_ports tms ];
-
-## UART
-set_property -dict {PACKAGE_PIN AU36 IOSTANDARD LVCMOS18} [get_ports tx]
-set_property -dict {PACKAGE_PIN AU33 IOSTANDARD LVCMOS18} [get_ports rx]
-
-
-## LEDs
-set_property -dict {PACKAGE_PIN AM39 IOSTANDARD LVCMOS18} [get_ports {led[0]}]
-set_property -dict {PACKAGE_PIN AN39 IOSTANDARD LVCMOS18} [get_ports {led[1]}]
-set_property -dict {PACKAGE_PIN AR37 IOSTANDARD LVCMOS18} [get_ports {led[2]}]
-set_property -dict {PACKAGE_PIN AT37 IOSTANDARD LVCMOS18} [get_ports {led[3]}]
-set_property -dict {PACKAGE_PIN AR35 IOSTANDARD LVCMOS18} [get_ports {led[4]}]
-set_property -dict {PACKAGE_PIN AP41 IOSTANDARD LVCMOS18} [get_ports {led[5]}]
-set_property -dict {PACKAGE_PIN AP42 IOSTANDARD LVCMOS18} [get_ports {led[6]}]
-set_property -dict {PACKAGE_PIN AU39 IOSTANDARD LVCMOS18} [get_ports {led[7]}]
-
-## Switches
-set_property -dict {PACKAGE_PIN AV30 IOSTANDARD LVCMOS18} [get_ports {sw[0]}]
-set_property -dict {PACKAGE_PIN AY33 IOSTANDARD LVCMOS18} [get_ports {sw[1]}]
-set_property -dict {PACKAGE_PIN BA31 IOSTANDARD LVCMOS18} [get_ports {sw[2]}]
-set_property -dict {PACKAGE_PIN BA32 IOSTANDARD LVCMOS18} [get_ports {sw[3]}]
-set_property -dict {PACKAGE_PIN AW30 IOSTANDARD LVCMOS18} [get_ports {sw[4]}]
-set_property -dict {PACKAGE_PIN AY30 IOSTANDARD LVCMOS18} [get_ports {sw[5]}]
-set_property -dict {PACKAGE_PIN BA30 IOSTANDARD LVCMOS18} [get_ports {sw[6]}]
-set_property -dict {PACKAGE_PIN BB31 IOSTANDARD LVCMOS18} [get_ports {sw[7]}]
-
-## Fan Control
-set_property -dict {PACKAGE_PIN BA37 IOSTANDARD LVCMOS18} [get_ports fan_pwm]
-#set_property -dict { PACKAGE_PIN V21 IOSTANDARD LVCMOS18 } [get_ports { FAN_TACH }]; #IO_L22P_T3_A05_D21_14 Sch=fan_tac
-
-## Ethernet
-set_property -dict {PACKAGE_PIN N26 IOSTANDARD LVCMOS18} [get_ports eth_rst_n]; #IO_L14N_T2_SRCC_12 Sch=eth_phyrst_n
-set_property -dict {PACKAGE_PIN N25 IOSTANDARD LVCMOS18} [get_ports eth_txck]; #IO_L14P_T2_SRCC_33 Sch=eth_tx_clk
-set_property -dict {PACKAGE_PIN P23 IOSTANDARD LVCMOS18} [get_ports eth_txctl]; #IO_L20P_T3_33 Sch=eth_tx_en
-set_property -dict {PACKAGE_PIN M26 IOSTANDARD LVCMOS18} [get_ports { eth_txd[0] }]; #IO_L22N_T3_33 Sch=eth_tx_d[0]
-set_property -dict {PACKAGE_PIN L27 IOSTANDARD LVCMOS18} [get_ports { eth_txd[1] }]; #IO_L17P_T2_33 Sch=eth_tx_d[1]
-set_property -dict {PACKAGE_PIN M27 IOSTANDARD LVCMOS18} [get_ports { eth_txd[2] }]; #IO_L18N_T2_33 Sch=eth_tx_d[2]
-set_property -dict {PACKAGE_PIN N24 IOSTANDARD LVCMOS18} [get_ports { eth_txd[3] }]; #IO_L17N_T2_33 Sch=eth_tx_d[3]
-set_property -dict {PACKAGE_PIN M21 IOSTANDARD LVCMOS18} [get_ports { eth_rxd[0] }]; #IO_L21N_T3_DQS_33 Sch=eth_rx_d[0]
-set_property -dict {PACKAGE_PIN M24 IOSTANDARD LVCMOS18} [get_ports eth_rxck]; #IO_L13P_T2_MRCC_33 Sch=eth_rx_clk
-set_property -dict {PACKAGE_PIN L25 IOSTANDARD LVCMOS18} [get_ports eth_rxctl]; #IO_L18P_T2_33 Sch=eth_rx_ctl
-set_property -dict {PACKAGE_PIN J22 IOSTANDARD LVCMOS18} [get_ports { eth_rxd[1] }]; #IO_L21P_T3_DQS_33 Sch=eth_rx_d[1]
-set_property -dict {PACKAGE_PIN K22 IOSTANDARD LVCMOS18} [get_ports { eth_rxd[2] }]; #IO_L20N_T3_33 Sch=eth_rx_d[2]
-set_property -dict {PACKAGE_PIN L26 IOSTANDARD LVCMOS18} [get_ports { eth_rxd[3] }]; #IO_L22P_T3_33 Sch=eth_rx_d[3]
-set_property -dict {PACKAGE_PIN N23 IOSTANDARD LVCMOS18} [get_ports eth_mdc ]; #IO_L23P_T3_33 Sch=eth_mdc
-set_property -dict {PACKAGE_PIN L21 IOSTANDARD LVCMOS18} [get_ports eth_mdio]; #IO_L23N_T3_33 Sch=eth_mdio
-
-# set_property -dict {PACKAGE_PIN AK15 IOSTANDARD LVCMOS18} [get_ports { eth_pme_b }]; #IO_L1N_T0_32 Sch=eth_pmeb
-# set_property -dict {PACKAGE_PIN AK16 IOSTANDARD LVCMOS18} [get_ports { eth_int_b }]; #IO_L1P_T0_32 Sch=eth_intb
-
-#############################################
-# Ethernet Constraints for 1Gb/s
-#############################################
-# Modified for 125MHz receive clock
-create_clock -period 8.000 -name eth_rxck [get_ports eth_rxck]
-
-set_clock_groups -asynchronous -group [get_clocks eth_rxck -include_generated_clocks]
-set_clock_groups -asynchronous -group [get_clocks clk_out2_xlnx_clk_gen]
-
-#############################################
-## SD Card
-#############################################
-set_property -dict {PACKAGE_PIN AN30 IOSTANDARD LVCMOS18} [get_ports spi_clk_o]
-set_property -dict {PACKAGE_PIN AT30 IOSTANDARD LVCMOS18} [get_ports spi_ss]
-set_property -dict {PACKAGE_PIN AR30 IOSTANDARD LVCMOS18} [get_ports spi_miso]
-set_property -dict {PACKAGE_PIN AP30 IOSTANDARD LVCMOS18} [get_ports spi_mosi]
-# set_property -dict { PACKAGE_PIN P28 IOSTANDARD LVCMOS18 } [get_ports { sd_cd }]; #IO_L8N_T1_D12_14 Sch=sd_cd
-# set_property -dict { PACKAGE_PIN R29 IOSTANDARD LVCMOS18 } [get_ports { sd_cmd }]; #IO_L7N_T1_D10_14 Sch=sd_cmd
-# set_property -dict { PACKAGE_PIN R26 IOSTANDARD LVCMOS18 } [get_ports { sd_dat[0] }]; #IO_L10N_T1_D15_14 Sch=sd_dat[0]
-# set_property -dict { PACKAGE_PIN R30 IOSTANDARD LVCMOS18 } [get_ports { sd_dat[1] }]; #IO_L9P_T1_DQS_14 Sch=sd_dat[1]
-# set_property -dict { PACKAGE_PIN P29 IOSTANDARD LVCMOS18 } [get_ports { sd_dat[2] }]; #IO_L7P_T1_D09_14 Sch=sd_dat[2]
-# set_property -dict { PACKAGE_PIN T30 IOSTANDARD LVCMOS18 } [get_ports { sd_dat[3] }]; #IO_L9N_T1_DQS_D13_14 Sch=sd_dat[3]
-# set_property -dict { PACKAGE_PIN AE24 IOSTANDARD LVCMOS18 } [get_ports { sd_reset }]; #IO_L12N_T1_MRCC_12 Sch=sd_reset
-# set_property -dict { PACKAGE_PIN R28 IOSTANDARD LVCMOS18 } [get_ports { sd_clk }]; #IO_L11P_T1_SRCC_14 Sch=sd_sclk
-
-# create_generated_clock -name sd_fast_clk -source [get_pins clk_mmcm/sd_sys_clk] -divide_by 2 [get_pins chipset_impl/piton_sd_top/sdc_controller/clock_divider0/fast_clk_reg/Q]
-# create_generated_clock -name sd_slow_clk -source [get_pins clk_mmcm/sd_sys_clk] -divide_by 200 [get_pins chipset_impl/piton_sd_top/sdc_controller/clock_divider0/slow_clk_reg/Q]
-# create_generated_clock -name sd_clk_out -source [get_pins sd_clk_oddr/C] -divide_by 1 -add -master_clock sd_fast_clk [get_ports sd_clk_out]
-# create_generated_clock -name sd_clk_out_1 -source [get_pins sd_clk_oddr/C] -divide_by 1 -add -master_clock sd_slow_clk [get_ports sd_clk_out]
-
-# create_clock -period 40.000 -name VIRTUAL_sd_fast_clk -waveform {0.000 20.000}
-# create_clock -period 4000.000 -name VIRTUAL_sd_slow_clk -waveform {0.000 2000.000}
-
-# set_output_delay -clock [get_clocks sd_clk_out] -min -add_delay 5.000 [get_ports {sd_dat[*]}]
-# set_output_delay -clock [get_clocks sd_clk_out] -max -add_delay 15.000 [get_ports {sd_dat[*]}]
-# set_output_delay -clock [get_clocks sd_clk_out_1] -min -add_delay 5.000 [get_ports {sd_dat[*]}]
-# set_output_delay -clock [get_clocks sd_clk_out_1] -max -add_delay 1500.000 [get_ports {sd_dat[*]}]
-# set_output_delay -clock [get_clocks sd_clk_out] -min -add_delay 5.000 [get_ports sd_cmd]
-# set_output_delay -clock [get_clocks sd_clk_out] -max -add_delay 15.000 [get_ports sd_cmd]
-# set_output_delay -clock [get_clocks sd_clk_out_1] -min -add_delay 5.000 [get_ports sd_cmd]
-# set_output_delay -clock [get_clocks sd_clk_out_1] -max -add_delay 1500.000 [get_ports sd_cmd]
-# set_input_delay -clock [get_clocks VIRTUAL_sd_fast_clk] -min -add_delay 20.000 [get_ports {sd_dat[*]}]
-# set_input_delay -clock [get_clocks VIRTUAL_sd_fast_clk] -max -add_delay 35.000 [get_ports {sd_dat[*]}]
-# set_input_delay -clock [get_clocks VIRTUAL_sd_slow_clk] -min -add_delay 2000.000 [get_ports {sd_dat[*]}]
-# set_input_delay -clock [get_clocks VIRTUAL_sd_slow_clk] -max -add_delay 3500.000 [get_ports {sd_dat[*]}]
-# set_input_delay -clock [get_clocks VIRTUAL_sd_fast_clk] -min -add_delay 20.000 [get_ports sd_cmd]
-# set_input_delay -clock [get_clocks VIRTUAL_sd_fast_clk] -max -add_delay 35.000 [get_ports sd_cmd]
-# set_input_delay -clock [get_clocks VIRTUAL_sd_slow_clk] -min -add_delay 2000.000 [get_ports sd_cmd]
-# set_input_delay -clock [get_clocks VIRTUAL_sd_slow_clk] -max -add_delay 3500.000 [get_ports sd_cmd]
-# set_clock_groups -physically_exclusive -group [get_clocks -include_generated_clocks sd_clk_out] -group [get_clocks -include_generated_clocks sd_clk_out_1]
-# set_clock_groups -logically_exclusive -group [get_clocks -include_generated_clocks {VIRTUAL_sd_fast_clk sd_fast_clk}] -group [get_clocks -include_generated_clocks {sd_slow_clk VIRTUAL_sd_slow_clk}]
-# set_clock_groups -asynchronous -group [get_clocks [list [get_clocks -of_objects [get_pins clk_mmcm/chipset_clk]]]] -group [get_clocks -filter { NAME =~ "*sd*" }]
-
-
-# Genesys 2 has a quad SPI flash
-# set_property BITSTREAM.CONFIG.SPI_BUSWIDTH 4 [current_design]
-
-## JTAG
-# minimize routing delay
-
-set_max_delay -to [get_ports tdo ] 20
-set_max_delay -from [get_ports tms ] 20
-set_max_delay -from [get_ports tdi ] 20
-set_max_delay -from [get_ports trst ] 20
-
-# reset signal
-# set_false_path -from [get_ports { trst } ]
-# set_false_path -from [get_pins i_ddr/u_xlnx_mig_7_ddr3_mig/u_ddr3_infrastructure/rstdiv0_sync_r1_reg_rep/C]
diff --git a/fpga/constraints/vcu118.xdc b/fpga/constraints/vcu118.xdc
deleted file mode 100644
index ea71aa8d..00000000
--- a/fpga/constraints/vcu118.xdc
+++ /dev/null
@@ -1,1990 +0,0 @@
-############################################################################
-### VCU118 Rev2.0 XDC 12/08/2017
-############################################################################
-# Buttons
-set_property -dict {PACKAGE_PIN L19 IOSTANDARD LVCMOS12} [get_ports cpu_reset] ;# Bank 73 VCCO - VCC1V2_FPGA - IO_T1U_N12_73
-set_property PULLDOWN true [get_ports cpu_reset]
-# PCIe
-set_false_path -from [get_ports sys_rst_n]
-set_property PULLUP true [get_ports sys_rst_n]
-set_property IOSTANDARD LVCMOS18 [get_ports sys_rst_n]
-set_property PACKAGE_PIN AM17 [get_ports sys_rst_n]
-create_clock -name sys_clk -period 10 [get_ports sys_clk_p]
-
-set_property -dict {PACKAGE_PIN AC9} [get_ports sys_clk_p]
-set_property -dict {PACKAGE_PIN AC8} [get_ports sys_clk_n]
-
-# JTAG
-set_property -dict {PACKAGE_PIN N28 IOSTANDARD LVCMOS12} [get_ports tck] ; # PMOD1_0
-set_property -dict {PACKAGE_PIN M30 IOSTANDARD LVCMOS12} [get_ports tdi] ; # PMOD1_1
-set_property -dict {PACKAGE_PIN N30 IOSTANDARD LVCMOS12} [get_ports tdo] ; # PMOD1_2
-set_property -dict {PACKAGE_PIN P30 IOSTANDARD LVCMOS12} [get_ports tms] ; # PMOD1_3
-set_property -dict {PACKAGE_PIN P29 IOSTANDARD LVCMOS12} [get_ports trst_n] ;# PMOD1_4
-# accept sub-optimal placement
-set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets tck_IBUF_inst/O]
-
-set_property -dict {PACKAGE_PIN AW25 IOSTANDARD LVCMOS18} [get_ports tx] ;# Bank 64 VCCO - VCC1V8_FPGA - IO_L9P_T1L_N4_AD12P_64
-set_property -dict {PACKAGE_PIN BB21 IOSTANDARD LVCMOS18} [get_ports rx] ;# Bank 64 VCCO - VCC1V8_FPGA - IO_L8N_T1L_N3_AD5N_64
-
-## SD Card **TODO(zarubaf)*** This is wrong for the VCU118
-set_property -dict {PACKAGE_PIN AY14 IOSTANDARD LVCMOS18} [get_ports spi_clk_o] ;# Bank 47 VCCO - VCC1V2_FPGA - IO_L13N_T2L_N1_GC_QBC_47
-set_property -dict {PACKAGE_PIN AY15 IOSTANDARD LVCMOS18} [get_ports spi_clk_o_2] ;# Bank 47 VCCO - VCC1V2_FPGA - IO_L13P_T2L_N0_GC_QBC_47
-
-set_property -dict {PACKAGE_PIN BF16 IOSTANDARD LVCMOS18} [get_ports spi_ss] ;# Bank 65 VCCO - VCC1V8_FPGA - IO_L2N_T0L_N3_FWE_FCS2_B_65
-set_property -dict {PACKAGE_PIN BF20 IOSTANDARD LVCMOS18} [get_ports spi_ss_2] ;# Bank 65 VCCO - VCC1V8_FPGA - IO_L1N_T0L_N1_DBC_RS1_65
-
-set_property -dict {PACKAGE_PIN AM18 IOSTANDARD LVCMOS18} [get_ports spi_miso] ;# Bank 65 VCCO - VCC1V8_FPGA - IO_L22N_T3U_N7_DBC_AD0N_D05_65
-set_property -dict {PACKAGE_PIN AM19 IOSTANDARD LVCMOS18} [get_ports spi_mosi] ;# Bank 65 VCCO - VCC1V8_FPGA - IO_L22P_T3U_N6_DBC_AD0P_D04_65
-set_property -dict {PACKAGE_PIN AP20 IOSTANDARD LVCMOS18} [get_ports spi_miso_2] ;# Bank 65 VCCO - VCC1V8_FPGA - IO_L21N_T3L_N5_AD8N_D07_65
-set_property -dict {PACKAGE_PIN AN20 IOSTANDARD LVCMOS18} [get_ports spi_mosi_2] ;# Bank 65 VCCO - VCC1V8_FPGA - IO_L21P_T3L_N4_AD8P_D06_65
-
-# #Other net PACKAGE_PIN AE17 - DXN Bank 0 - DXN
-# #Other net PACKAGE_PIN AE18 - DXP Bank 0 - DXP
-# #Other net PACKAGE_PIN AD18 - GND Bank 0 - VREFP
-# #Other net PACKAGE_PIN AC17 - GND Bank 0 - VREFN
-# #Other net PACKAGE_PIN AC18 - SYSMON_VP Bank 0 - VP
-# #Other net PACKAGE_PIN AD17 - SYSMON_VN Bank 0 - VN
-# #Other net PACKAGE_PIN U10 - FPGA_M0 Bank 0 - M0_0
-# #Other net PACKAGE_PIN Y11 - FPGA_M1 Bank 0 - M1_0
-# #Other net PACKAGE_PIN AC12 - FPGA_INIT_B Bank 0 - INIT_B_0
-# #Other net PACKAGE_PIN W11 - FPGA_M2 Bank 0 - M2_0
-# #Other net PACKAGE_PIN AB11 - GND Bank 0 - RSVDGND
-# #Other net PACKAGE_PIN AD12 - PUDC_B_PIN Bank 0 - PUDC_B_0
-# #Other net PACKAGE_PIN AG12 - POR_OVERRIDE_PIN Bank 0 - POR_OVERRIDE
-# #Other net PACKAGE_PIN AE12 - FPGA_DONE Bank 0 - DONE_0
-# #Other net PACKAGE_PIN AH11 - FPGA_PROG_B Bank 0 - PROGRAM_B_0
-# #Other net PACKAGE_PIN AD13 - FPGA_TDO_FMC_TDI Bank 0 - TDO_0
-# #Other net PACKAGE_PIN AD15 - JTAG_TDI Bank 0 - TDI_0
-# #Other net PACKAGE_PIN AJ11 - QSPI0_CS_B Bank 0 - RDWR_FCS_B_0
-# #Other net PACKAGE_PIN AM11 - QSPI0_DQ2 Bank 0 - D02_0
-# #Other net PACKAGE_PIN AP11 - QSPI0_DQ0 Bank 0 - D00_MOSI_0
-# #Other net PACKAGE_PIN AL11 - QSPI0_DQ3 Bank 0 - D03_0
-# #Other net PACKAGE_PIN AN11 - QSPI0_DQ1 Bank 0 - D01_DIN_0
-# #Other net PACKAGE_PIN AF15 - JTAG_TMS Bank 0 - TMS_0
-# #Other net PACKAGE_PIN AF13 - QSPI_CCLK Bank 0 - CCLK_0
-# #Other net PACKAGE_PIN AE13 - JTAG_TCK Bank 0 - TCK_0
-# #Other net PACKAGE_PIN AT11 - FPGA_VBATT Bank 0 - VBATT
-# set_property PACKAGE_PIN B25 [get_ports "RLD3_C3_72B_DM3"] ;# Bank 48 VCCO - VCC1V2_FPGA - IO_L24N_T3U_N11_48
-# set_property IOSTANDARD SSTL12 [get_ports "RLD3_C3_72B_DM3"] ;# Bank 48 VCCO - VCC1V2_FPGA - IO_L24N_T3U_N11_48
-# set_property PACKAGE_PIN C25 [get_ports "RLD3_C3_72B_DQ71"] ;# Bank 48 VCCO - VCC1V2_FPGA - IO_L24P_T3U_N10_48
-# set_property IOSTANDARD SSTL12 [get_ports "RLD3_C3_72B_DQ71"] ;# Bank 48 VCCO - VCC1V2_FPGA - IO_L24P_T3U_N10_48
-# set_property PACKAGE_PIN D26 [get_ports "RLD3_C3_72B_DQ70"] ;# Bank 48 VCCO - VCC1V2_FPGA - IO_L23N_T3U_N9_48
-# set_property IOSTANDARD SSTL12 [get_ports "RLD3_C3_72B_DQ70"] ;# Bank 48 VCCO - VCC1V2_FPGA - IO_L23N_T3U_N9_48
-# set_property PACKAGE_PIN D25 [get_ports "RLD3_C3_72B_DQ69"] ;# Bank 48 VCCO - VCC1V2_FPGA - IO_L23P_T3U_N8_48
-# set_property IOSTANDARD SSTL12 [get_ports "RLD3_C3_72B_DQ69"] ;# Bank 48 VCCO - VCC1V2_FPGA - IO_L23P_T3U_N8_48
-# set_property PACKAGE_PIN A26 [get_ports "RLD3_C3_72B_DQ68"] ;# Bank 48 VCCO - VCC1V2_FPGA - IO_L22N_T3U_N7_DBC_AD0N_48
-# set_property IOSTANDARD SSTL12 [get_ports "RLD3_C3_72B_DQ68"] ;# Bank 48 VCCO - VCC1V2_FPGA - IO_L22N_T3U_N7_DBC_AD0N_48
-# set_property PACKAGE_PIN B26 [get_ports "RLD3_C3_72B_DQ67"] ;# Bank 48 VCCO - VCC1V2_FPGA - IO_L22P_T3U_N6_DBC_AD0P_48
-# set_property IOSTANDARD SSTL12 [get_ports "RLD3_C3_72B_DQ67"] ;# Bank 48 VCCO - VCC1V2_FPGA - IO_L22P_T3U_N6_DBC_AD0P_48
-# set_property PACKAGE_PIN B27 [get_ports "RLD3_C3_72B_DQ66"] ;# Bank 48 VCCO - VCC1V2_FPGA - IO_L21N_T3L_N5_AD8N_48
-# set_property IOSTANDARD SSTL12 [get_ports "RLD3_C3_72B_DQ66"] ;# Bank 48 VCCO - VCC1V2_FPGA - IO_L21N_T3L_N5_AD8N_48
-# set_property PACKAGE_PIN C27 [get_ports "RLD3_C3_72B_DQ65"] ;# Bank 48 VCCO - VCC1V2_FPGA - IO_L21P_T3L_N4_AD8P_48
-# set_property IOSTANDARD SSTL12 [get_ports "RLD3_C3_72B_DQ65"] ;# Bank 48 VCCO - VCC1V2_FPGA - IO_L21P_T3L_N4_AD8P_48
-# set_property PACKAGE_PIN A28 [get_ports "RLD3_C3_72B_DQ64"] ;# Bank 48 VCCO - VCC1V2_FPGA - IO_L20N_T3L_N3_AD1N_48
-# set_property IOSTANDARD SSTL12 [get_ports "RLD3_C3_72B_DQ64"] ;# Bank 48 VCCO - VCC1V2_FPGA - IO_L20N_T3L_N3_AD1N_48
-# set_property PACKAGE_PIN B28 [get_ports "RLD3_C3_72B_DQ63"] ;# Bank 48 VCCO - VCC1V2_FPGA - IO_L20P_T3L_N2_AD1P_48
-# set_property IOSTANDARD SSTL12 [get_ports "RLD3_C3_72B_DQ63"] ;# Bank 48 VCCO - VCC1V2_FPGA - IO_L20P_T3L_N2_AD1P_48
-# set_property PACKAGE_PIN C28 [get_ports "RLD3_C3_72B_QK7_N"] ;# Bank 48 VCCO - VCC1V2_FPGA - IO_L19N_T3L_N1_DBC_AD9N_48
-# set_property IOSTANDARD DIFF_SSTL12 [get_ports "RLD3_C3_72B_QK7_N"] ;# Bank 48 VCCO - VCC1V2_FPGA - IO_L19N_T3L_N1_DBC_AD9N_48
-# set_property PACKAGE_PIN D27 [get_ports "RLD3_C3_72B_QK7_P"] ;# Bank 48 VCCO - VCC1V2_FPGA - IO_L19P_T3L_N0_DBC_AD9P_48
-# set_property IOSTANDARD DIFF_SSTL12 [get_ports "RLD3_C3_72B_QK7_P"] ;# Bank 48 VCCO - VCC1V2_FPGA - IO_L19P_T3L_N0_DBC_AD9P_48
-# #set_property PACKAGE_PIN A25 [get_ports ""] ;# Bank 48 VCCO - VCC1V2_FPGA - IO_T3U_N12_48
-# #set_property IOSTANDARD LVCMOSxx [get_ports ""] ;# Bank 48 VCCO - VCC1V2_FPGA - IO_T3U_N12_48
-# #set_property PACKAGE_PIN H25 [get_ports ""] ;# Bank 48 VCCO - VCC1V2_FPGA - IO_T2U_N12_48
-# #set_property IOSTANDARD LVCMOSxx [get_ports ""] ;# Bank 48 VCCO - VCC1V2_FPGA - IO_T2U_N12_48
-# set_property PACKAGE_PIN F25 [get_ports "RLD3_C3_72B_QVLD3"] ;# Bank 48 VCCO - VCC1V2_FPGA - IO_L18N_T2U_N11_AD2N_48
-# set_property IOSTANDARD SSTL12 [get_ports "RLD3_C3_72B_QVLD3"] ;# Bank 48 VCCO - VCC1V2_FPGA - IO_L18N_T2U_N11_AD2N_48
-# set_property PACKAGE_PIN G25 [get_ports "RLD3_C3_72B_DQ62"] ;# Bank 48 VCCO - VCC1V2_FPGA - IO_L18P_T2U_N10_AD2P_48
-# set_property IOSTANDARD SSTL12 [get_ports "RLD3_C3_72B_DQ62"] ;# Bank 48 VCCO - VCC1V2_FPGA - IO_L18P_T2U_N10_AD2P_48
-# set_property PACKAGE_PIN E27 [get_ports "RLD3_C3_72B_DQ61"] ;# Bank 48 VCCO - VCC1V2_FPGA - IO_L17N_T2U_N9_AD10N_48
-# set_property IOSTANDARD SSTL12 [get_ports "RLD3_C3_72B_DQ61"] ;# Bank 48 VCCO - VCC1V2_FPGA - IO_L17N_T2U_N9_AD10N_48
-# set_property PACKAGE_PIN E26 [get_ports "RLD3_C3_72B_DQ60"] ;# Bank 48 VCCO - VCC1V2_FPGA - IO_L17P_T2U_N8_AD10P_48
-# set_property IOSTANDARD SSTL12 [get_ports "RLD3_C3_72B_DQ60"] ;# Bank 48 VCCO - VCC1V2_FPGA - IO_L17P_T2U_N8_AD10P_48
-# set_property PACKAGE_PIN G28 [get_ports "RLD3_C3_72B_DQ59"] ;# Bank 48 VCCO - VCC1V2_FPGA - IO_L16N_T2U_N7_QBC_AD3N_48
-# set_property IOSTANDARD SSTL12 [get_ports "RLD3_C3_72B_DQ59"] ;# Bank 48 VCCO - VCC1V2_FPGA - IO_L16N_T2U_N7_QBC_AD3N_48
-# set_property PACKAGE_PIN H28 [get_ports "RLD3_C3_72B_DQ58"] ;# Bank 48 VCCO - VCC1V2_FPGA - IO_L16P_T2U_N6_QBC_AD3P_48
-# set_property IOSTANDARD SSTL12 [get_ports "RLD3_C3_72B_DQ58"] ;# Bank 48 VCCO - VCC1V2_FPGA - IO_L16P_T2U_N6_QBC_AD3P_48
-# set_property PACKAGE_PIN E28 [get_ports "RLD3_C3_72B_DQ57"] ;# Bank 48 VCCO - VCC1V2_FPGA - IO_L15N_T2L_N5_AD11N_48
-# set_property IOSTANDARD SSTL12 [get_ports "RLD3_C3_72B_DQ57"] ;# Bank 48 VCCO - VCC1V2_FPGA - IO_L15N_T2L_N5_AD11N_48
-# set_property PACKAGE_PIN F28 [get_ports "RLD3_C3_72B_DQ56"] ;# Bank 48 VCCO - VCC1V2_FPGA - IO_L15P_T2L_N4_AD11P_48
-# set_property IOSTANDARD SSTL12 [get_ports "RLD3_C3_72B_DQ56"] ;# Bank 48 VCCO - VCC1V2_FPGA - IO_L15P_T2L_N4_AD11P_48
-# set_property PACKAGE_PIN G27 [get_ports "RLD3_C3_72B_DQ55"] ;# Bank 48 VCCO - VCC1V2_FPGA - IO_L14N_T2L_N3_GC_48
-# set_property IOSTANDARD SSTL12 [get_ports "RLD3_C3_72B_DQ55"] ;# Bank 48 VCCO - VCC1V2_FPGA - IO_L14N_T2L_N3_GC_48
-# set_property PACKAGE_PIN H27 [get_ports "RLD3_C3_72B_DQ54"] ;# Bank 48 VCCO - VCC1V2_FPGA - IO_L14P_T2L_N2_GC_48
-# set_property IOSTANDARD SSTL12 [get_ports "RLD3_C3_72B_DQ54"] ;# Bank 48 VCCO - VCC1V2_FPGA - IO_L14P_T2L_N2_GC_48
-# set_property PACKAGE_PIN F26 [get_ports "RLD3_C3_72B_QK6_N"] ;# Bank 48 VCCO - VCC1V2_FPGA - IO_L13N_T2L_N1_GC_QBC_48
-# set_property IOSTANDARD DIFF_SSTL12 [get_ports "RLD3_C3_72B_QK6_N"] ;# Bank 48 VCCO - VCC1V2_FPGA - IO_L13N_T2L_N1_GC_QBC_48
-# set_property PACKAGE_PIN G26 [get_ports "RLD3_C3_72B_QK6_P"] ;# Bank 48 VCCO - VCC1V2_FPGA - IO_L13P_T2L_N0_GC_QBC_48
-# set_property IOSTANDARD DIFF_SSTL12 [get_ports "RLD3_C3_72B_QK6_P"] ;# Bank 48 VCCO - VCC1V2_FPGA - IO_L13P_T2L_N0_GC_QBC_48
-# set_property PACKAGE_PIN J27 [get_ports "RLD3_C3_72B_QVLD2"] ;# Bank 48 VCCO - VCC1V2_FPGA - IO_L12N_T1U_N11_GC_48
-# set_property IOSTANDARD SSTL12 [get_ports "RLD3_C3_72B_QVLD2"] ;# Bank 48 VCCO - VCC1V2_FPGA - IO_L12N_T1U_N11_GC_48
-# set_property PACKAGE_PIN K27 [get_ports "RLD3_C3_72B_DQ53"] ;# Bank 48 VCCO - VCC1V2_FPGA - IO_L12P_T1U_N10_GC_48
-# set_property IOSTANDARD SSTL12 [get_ports "RLD3_C3_72B_DQ53"] ;# Bank 48 VCCO - VCC1V2_FPGA - IO_L12P_T1U_N10_GC_48
-# set_property PACKAGE_PIN J26 [get_ports "RLD3_C3_72B_DQ52"] ;# Bank 48 VCCO - VCC1V2_FPGA - IO_L11N_T1U_N9_GC_48
-# set_property IOSTANDARD SSTL12 [get_ports "RLD3_C3_72B_DQ52"] ;# Bank 48 VCCO - VCC1V2_FPGA - IO_L11N_T1U_N9_GC_48
-# set_property PACKAGE_PIN K26 [get_ports "RLD3_C3_72B_DQ51"] ;# Bank 48 VCCO - VCC1V2_FPGA - IO_L11P_T1U_N8_GC_48
-# set_property IOSTANDARD SSTL12 [get_ports "RLD3_C3_72B_DQ51"] ;# Bank 48 VCCO - VCC1V2_FPGA - IO_L11P_T1U_N8_GC_48
-# set_property PACKAGE_PIN L25 [get_ports "RLD3_C3_72B_DQ50"] ;# Bank 48 VCCO - VCC1V2_FPGA - IO_L10N_T1U_N7_QBC_AD4N_48
-# set_property IOSTANDARD SSTL12 [get_ports "RLD3_C3_72B_DQ50"] ;# Bank 48 VCCO - VCC1V2_FPGA - IO_L10N_T1U_N7_QBC_AD4N_48
-# set_property PACKAGE_PIN L24 [get_ports "RLD3_C3_72B_DQ49"] ;# Bank 48 VCCO - VCC1V2_FPGA - IO_L10P_T1U_N6_QBC_AD4P_48
-# set_property IOSTANDARD SSTL12 [get_ports "RLD3_C3_72B_DQ49"] ;# Bank 48 VCCO - VCC1V2_FPGA - IO_L10P_T1U_N6_QBC_AD4P_48
-# set_property PACKAGE_PIN K28 [get_ports "RLD3_C3_72B_DQ48"] ;# Bank 48 VCCO - VCC1V2_FPGA - IO_L9N_T1L_N5_AD12N_48
-# set_property IOSTANDARD SSTL12 [get_ports "RLD3_C3_72B_DQ48"] ;# Bank 48 VCCO - VCC1V2_FPGA - IO_L9N_T1L_N5_AD12N_48
-# set_property PACKAGE_PIN L28 [get_ports "RLD3_C3_72B_DQ47"] ;# Bank 48 VCCO - VCC1V2_FPGA - IO_L9P_T1L_N4_AD12P_48
-# set_property IOSTANDARD SSTL12 [get_ports "RLD3_C3_72B_DQ47"] ;# Bank 48 VCCO - VCC1V2_FPGA - IO_L9P_T1L_N4_AD12P_48
-# set_property PACKAGE_PIN L26 [get_ports "RLD3_C3_72B_DQ46"] ;# Bank 48 VCCO - VCC1V2_FPGA - IO_L8N_T1L_N3_AD5N_48
-# set_property IOSTANDARD SSTL12 [get_ports "RLD3_C3_72B_DQ46"] ;# Bank 48 VCCO - VCC1V2_FPGA - IO_L8N_T1L_N3_AD5N_48
-# set_property PACKAGE_PIN M25 [get_ports "RLD3_C3_72B_DQ45"] ;# Bank 48 VCCO - VCC1V2_FPGA - IO_L8P_T1L_N2_AD5P_48
-# set_property IOSTANDARD SSTL12 [get_ports "RLD3_C3_72B_DQ45"] ;# Bank 48 VCCO - VCC1V2_FPGA - IO_L8P_T1L_N2_AD5P_48
-# set_property PACKAGE_PIN M28 [get_ports "RLD3_C3_72B_QK5_N"] ;# Bank 48 VCCO - VCC1V2_FPGA - IO_L7N_T1L_N1_QBC_AD13N_48
-# set_property IOSTANDARD DIFF_SSTL12 [get_ports "RLD3_C3_72B_QK5_N"] ;# Bank 48 VCCO - VCC1V2_FPGA - IO_L7N_T1L_N1_QBC_AD13N_48
-# set_property PACKAGE_PIN M27 [get_ports "RLD3_C3_72B_QK5_P"] ;# Bank 48 VCCO - VCC1V2_FPGA - IO_L7P_T1L_N0_QBC_AD13P_48
-# set_property IOSTANDARD DIFF_SSTL12 [get_ports "RLD3_C3_72B_QK5_P"] ;# Bank 48 VCCO - VCC1V2_FPGA - IO_L7P_T1L_N0_QBC_AD13P_48
-# #set_property PACKAGE_PIN J25 [get_ports ""] ;# Bank 48 VCCO - VCC1V2_FPGA - IO_T1U_N12_48
-# #set_property IOSTANDARD LVCMOSxx [get_ports ""] ;# Bank 48 VCCO - VCC1V2_FPGA - IO_T1U_N12_48
-# #set_property PACKAGE_PIN M26 [get_ports "VRP_48"] ;# Bank 48 VCCO - VCC1V2_FPGA - IO_T0U_N12_VRP_48
-# #set_property IOSTANDARD LVCMOSxx [get_ports "VRP_48"] ;# Bank 48 VCCO - VCC1V2_FPGA - IO_T0U_N12_VRP_48
-# set_property PACKAGE_PIN N24 [get_ports "RLD3_C3_72B_DM2"] ;# Bank 48 VCCO - VCC1V2_FPGA - IO_L6N_T0U_N11_AD6N_48
-# set_property IOSTANDARD SSTL12 [get_ports "RLD3_C3_72B_DM2"] ;# Bank 48 VCCO - VCC1V2_FPGA - IO_L6N_T0U_N11_AD6N_48
-# set_property PACKAGE_PIN P24 [get_ports "RLD3_C3_72B_DQ44"] ;# Bank 48 VCCO - VCC1V2_FPGA - IO_L6P_T0U_N10_AD6P_48
-# set_property IOSTANDARD SSTL12 [get_ports "RLD3_C3_72B_DQ44"] ;# Bank 48 VCCO - VCC1V2_FPGA - IO_L6P_T0U_N10_AD6P_48
-# set_property PACKAGE_PIN N27 [get_ports "RLD3_C3_72B_DQ43"] ;# Bank 48 VCCO - VCC1V2_FPGA - IO_L5N_T0U_N9_AD14N_48
-# set_property IOSTANDARD SSTL12 [get_ports "RLD3_C3_72B_DQ43"] ;# Bank 48 VCCO - VCC1V2_FPGA - IO_L5N_T0U_N9_AD14N_48
-# set_property PACKAGE_PIN P26 [get_ports "RLD3_C3_72B_DQ42"] ;# Bank 48 VCCO - VCC1V2_FPGA - IO_L5P_T0U_N8_AD14P_48
-# set_property IOSTANDARD SSTL12 [get_ports "RLD3_C3_72B_DQ42"] ;# Bank 48 VCCO - VCC1V2_FPGA - IO_L5P_T0U_N8_AD14P_48
-# set_property PACKAGE_PIN N25 [get_ports "RLD3_C3_72B_DQ41"] ;# Bank 48 VCCO - VCC1V2_FPGA - IO_L4N_T0U_N7_DBC_AD7N_48
-# set_property IOSTANDARD SSTL12 [get_ports "RLD3_C3_72B_DQ41"] ;# Bank 48 VCCO - VCC1V2_FPGA - IO_L4N_T0U_N7_DBC_AD7N_48
-# set_property PACKAGE_PIN P25 [get_ports "RLD3_C3_72B_DQ40"] ;# Bank 48 VCCO - VCC1V2_FPGA - IO_L4P_T0U_N6_DBC_AD7P_48
-# set_property IOSTANDARD SSTL12 [get_ports "RLD3_C3_72B_DQ40"] ;# Bank 48 VCCO - VCC1V2_FPGA - IO_L4P_T0U_N6_DBC_AD7P_48
-# set_property PACKAGE_PIN P27 [get_ports "RLD3_C3_72B_DQ39"] ;# Bank 48 VCCO - VCC1V2_FPGA - IO_L3N_T0L_N5_AD15N_48
-# set_property IOSTANDARD SSTL12 [get_ports "RLD3_C3_72B_DQ39"] ;# Bank 48 VCCO - VCC1V2_FPGA - IO_L3N_T0L_N5_AD15N_48
-# set_property PACKAGE_PIN R27 [get_ports "RLD3_C3_72B_DQ38"] ;# Bank 48 VCCO - VCC1V2_FPGA - IO_L3P_T0L_N4_AD15P_48
-# set_property IOSTANDARD SSTL12 [get_ports "RLD3_C3_72B_DQ38"] ;# Bank 48 VCCO - VCC1V2_FPGA - IO_L3P_T0L_N4_AD15P_48
-# set_property PACKAGE_PIN R24 [get_ports "RLD3_C3_72B_DQ37"] ;# Bank 48 VCCO - VCC1V2_FPGA - IO_L2N_T0L_N3_48
-# set_property IOSTANDARD SSTL12 [get_ports "RLD3_C3_72B_DQ37"] ;# Bank 48 VCCO - VCC1V2_FPGA - IO_L2N_T0L_N3_48
-# set_property PACKAGE_PIN T24 [get_ports "RLD3_C3_72B_DQ36"] ;# Bank 48 VCCO - VCC1V2_FPGA - IO_L2P_T0L_N2_48
-# set_property IOSTANDARD SSTL12 [get_ports "RLD3_C3_72B_DQ36"] ;# Bank 48 VCCO - VCC1V2_FPGA - IO_L2P_T0L_N2_48
-# set_property PACKAGE_PIN R26 [get_ports "RLD3_C3_72B_QK4_N"] ;# Bank 48 VCCO - VCC1V2_FPGA - IO_L1N_T0L_N1_DBC_48
-# set_property IOSTANDARD DIFF_SSTL12 [get_ports "RLD3_C3_72B_QK4_N"] ;# Bank 48 VCCO - VCC1V2_FPGA - IO_L1N_T0L_N1_DBC_48
-# set_property PACKAGE_PIN T26 [get_ports "RLD3_C3_72B_QK4_P"] ;# Bank 48 VCCO - VCC1V2_FPGA - IO_L1P_T0L_N0_DBC_48
-# set_property IOSTANDARD DIFF_SSTL12 [get_ports "RLD3_C3_72B_QK4_P"] ;# Bank 48 VCCO - VCC1V2_FPGA - IO_L1P_T0L_N0_DBC_48
-# #Other net PACKAGE_PIN T25 - Bank 48 - VREF_48
-# set_property PACKAGE_PIN C29 [get_ports "RLD3_C3_72B_A1"] ;# Bank 47 VCCO - VCC1V2_FPGA - IO_L24N_T3U_N11_47
-# set_property IOSTANDARD SSTL12 [get_ports "RLD3_C3_72B_A1"] ;# Bank 47 VCCO - VCC1V2_FPGA - IO_L24N_T3U_N11_47
-# set_property PACKAGE_PIN D29 [get_ports "RLD3_C3_72B_A2"] ;# Bank 47 VCCO - VCC1V2_FPGA - IO_L24P_T3U_N10_47
-# set_property IOSTANDARD SSTL12 [get_ports "RLD3_C3_72B_A2"] ;# Bank 47 VCCO - VCC1V2_FPGA - IO_L24P_T3U_N10_47
-# set_property PACKAGE_PIN B30 [get_ports "RLD3_C3_72B_A3"] ;# Bank 47 VCCO - VCC1V2_FPGA - IO_L23N_T3U_N9_47
-# set_property IOSTANDARD SSTL12 [get_ports "RLD3_C3_72B_A3"] ;# Bank 47 VCCO - VCC1V2_FPGA - IO_L23N_T3U_N9_47
-# set_property PACKAGE_PIN C30 [get_ports "RLD3_C3_72B_A4"] ;# Bank 47 VCCO - VCC1V2_FPGA - IO_L23P_T3U_N8_47
-# set_property IOSTANDARD SSTL12 [get_ports "RLD3_C3_72B_A4"] ;# Bank 47 VCCO - VCC1V2_FPGA - IO_L23P_T3U_N8_47
-# set_property PACKAGE_PIN A31 [get_ports "RLD3_C3_72B_A5"] ;# Bank 47 VCCO - VCC1V2_FPGA - IO_L22N_T3U_N7_DBC_AD0N_47
-# set_property IOSTANDARD SSTL12 [get_ports "RLD3_C3_72B_A5"] ;# Bank 47 VCCO - VCC1V2_FPGA - IO_L22N_T3U_N7_DBC_AD0N_47
-# set_property PACKAGE_PIN A30 [get_ports "RLD3_C3_72B_A6"] ;# Bank 47 VCCO - VCC1V2_FPGA - IO_L22P_T3U_N6_DBC_AD0P_47
-# set_property IOSTANDARD SSTL12 [get_ports "RLD3_C3_72B_A6"] ;# Bank 47 VCCO - VCC1V2_FPGA - IO_L22P_T3U_N6_DBC_AD0P_47
-# set_property PACKAGE_PIN A33 [get_ports "RLD3_C3_72B_A7"] ;# Bank 47 VCCO - VCC1V2_FPGA - IO_L21N_T3L_N5_AD8N_47
-# set_property IOSTANDARD SSTL12 [get_ports "RLD3_C3_72B_A7"] ;# Bank 47 VCCO - VCC1V2_FPGA - IO_L21N_T3L_N5_AD8N_47
-# set_property PACKAGE_PIN B33 [get_ports "RLD3_C3_72B_A8"] ;# Bank 47 VCCO - VCC1V2_FPGA - IO_L21P_T3L_N4_AD8P_47
-# set_property IOSTANDARD SSTL12 [get_ports "RLD3_C3_72B_A8"] ;# Bank 47 VCCO - VCC1V2_FPGA - IO_L21P_T3L_N4_AD8P_47
-# set_property PACKAGE_PIN B32 [get_ports "RLD3_C3_72B_A9"] ;# Bank 47 VCCO - VCC1V2_FPGA - IO_L20N_T3L_N3_AD1N_47
-# set_property IOSTANDARD SSTL12 [get_ports "RLD3_C3_72B_A9"] ;# Bank 47 VCCO - VCC1V2_FPGA - IO_L20N_T3L_N3_AD1N_47
-# set_property PACKAGE_PIN B31 [get_ports "RLD3_C3_72B_A10"] ;# Bank 47 VCCO - VCC1V2_FPGA - IO_L20P_T3L_N2_AD1P_47
-# set_property IOSTANDARD SSTL12 [get_ports "RLD3_C3_72B_A10"] ;# Bank 47 VCCO - VCC1V2_FPGA - IO_L20P_T3L_N2_AD1P_47
-# set_property PACKAGE_PIN C33 [get_ports "RLD3_C3_72B_A11"] ;# Bank 47 VCCO - VCC1V2_FPGA - IO_L19N_T3L_N1_DBC_AD9N_47
-# set_property IOSTANDARD SSTL12 [get_ports "RLD3_C3_72B_A11"] ;# Bank 47 VCCO - VCC1V2_FPGA - IO_L19N_T3L_N1_DBC_AD9N_47
-# set_property PACKAGE_PIN C32 [get_ports "RLD3_C3_72B_A12"] ;# Bank 47 VCCO - VCC1V2_FPGA - IO_L19P_T3L_N0_DBC_AD9P_47
-# set_property IOSTANDARD SSTL12 [get_ports "RLD3_C3_72B_A12"] ;# Bank 47 VCCO - VCC1V2_FPGA - IO_L19P_T3L_N0_DBC_AD9P_47
-# set_property PACKAGE_PIN A29 [get_ports "RLD3_C3_72B_A0"] ;# Bank 47 VCCO - VCC1V2_FPGA - IO_T3U_N12_47
-# set_property IOSTANDARD SSTL12 [get_ports "RLD3_C3_72B_A0"] ;# Bank 47 VCCO - VCC1V2_FPGA - IO_T3U_N12_47
-# set_property PACKAGE_PIN D30 [get_ports "RLD3_C3_72B_A13"] ;# Bank 47 VCCO - VCC1V2_FPGA - IO_T2U_N12_47
-# set_property IOSTANDARD SSTL12 [get_ports "RLD3_C3_72B_A13"] ;# Bank 47 VCCO - VCC1V2_FPGA - IO_T2U_N12_47
-# set_property PACKAGE_PIN E29 [get_ports "RLD3_C3_72B_A14"] ;# Bank 47 VCCO - VCC1V2_FPGA - IO_L18N_T2U_N11_AD2N_47
-# set_property IOSTANDARD SSTL12 [get_ports "RLD3_C3_72B_A14"] ;# Bank 47 VCCO - VCC1V2_FPGA - IO_L18N_T2U_N11_AD2N_47
-# set_property PACKAGE_PIN F29 [get_ports "RLD3_C3_72B_A15"] ;# Bank 47 VCCO - VCC1V2_FPGA - IO_L18P_T2U_N10_AD2P_47
-# set_property IOSTANDARD SSTL12 [get_ports "RLD3_C3_72B_A15"] ;# Bank 47 VCCO - VCC1V2_FPGA - IO_L18P_T2U_N10_AD2P_47
-# set_property PACKAGE_PIN D32 [get_ports "RLD3_C3_72B_A16"] ;# Bank 47 VCCO - VCC1V2_FPGA - IO_L17N_T2U_N9_AD10N_47
-# set_property IOSTANDARD SSTL12 [get_ports "RLD3_C3_72B_A16"] ;# Bank 47 VCCO - VCC1V2_FPGA - IO_L17N_T2U_N9_AD10N_47
-# set_property PACKAGE_PIN E32 [get_ports "RLD3_C3_72B_A17"] ;# Bank 47 VCCO - VCC1V2_FPGA - IO_L17P_T2U_N8_AD10P_47
-# set_property IOSTANDARD SSTL12 [get_ports "RLD3_C3_72B_A17"] ;# Bank 47 VCCO - VCC1V2_FPGA - IO_L17P_T2U_N8_AD10P_47
-# set_property PACKAGE_PIN D31 [get_ports "RLD3_C3_72B_A18"] ;# Bank 47 VCCO - VCC1V2_FPGA - IO_L16N_T2U_N7_QBC_AD3N_47
-# set_property IOSTANDARD SSTL12 [get_ports "RLD3_C3_72B_A18"] ;# Bank 47 VCCO - VCC1V2_FPGA - IO_L16N_T2U_N7_QBC_AD3N_47
-# set_property PACKAGE_PIN E31 [get_ports "RLD3_C3_72B_A19"] ;# Bank 47 VCCO - VCC1V2_FPGA - IO_L16P_T2U_N6_QBC_AD3P_47
-# set_property IOSTANDARD SSTL12 [get_ports "RLD3_C3_72B_A19"] ;# Bank 47 VCCO - VCC1V2_FPGA - IO_L16P_T2U_N6_QBC_AD3P_47
-# set_property PACKAGE_PIN E33 [get_ports "RLD3_C3_72B_BA0"] ;# Bank 47 VCCO - VCC1V2_FPGA - IO_L15N_T2L_N5_AD11N_47
-# set_property IOSTANDARD SSTL12 [get_ports "RLD3_C3_72B_BA0"] ;# Bank 47 VCCO - VCC1V2_FPGA - IO_L15N_T2L_N5_AD11N_47
-# set_property PACKAGE_PIN F33 [get_ports "RLD3_C3_72B_BA1"] ;# Bank 47 VCCO - VCC1V2_FPGA - IO_L15P_T2L_N4_AD11P_47
-# set_property IOSTANDARD SSTL12 [get_ports "RLD3_C3_72B_BA1"] ;# Bank 47 VCCO - VCC1V2_FPGA - IO_L15P_T2L_N4_AD11P_47
-# set_property PACKAGE_PIN F30 [get_ports "RLD3_C3_72B_BA2"] ;# Bank 47 VCCO - VCC1V2_FPGA - IO_L14N_T2L_N3_GC_47
-# set_property IOSTANDARD SSTL12 [get_ports "RLD3_C3_72B_BA2"] ;# Bank 47 VCCO - VCC1V2_FPGA - IO_L14N_T2L_N3_GC_47
-# set_property PACKAGE_PIN G30 [get_ports "RLD3_C3_72B_BA3"] ;# Bank 47 VCCO - VCC1V2_FPGA - IO_L14P_T2L_N2_GC_47
-# set_property IOSTANDARD SSTL12 [get_ports "RLD3_C3_72B_BA3"] ;# Bank 47 VCCO - VCC1V2_FPGA - IO_L14P_T2L_N2_GC_47
-# set_property PACKAGE_PIN F31 [get_ports "SYSCLK1_300_N"] ;# Bank 47 VCCO - VCC1V2_FPGA - IO_L13N_T2L_N1_GC_QBC_47
-# set_property IOSTANDARD DIFF_SSTL12 [get_ports "SYSCLK1_300_N"] ;# Bank 47 VCCO - VCC1V2_FPGA - IO_L13N_T2L_N1_GC_QBC_47
-# set_property PACKAGE_PIN G31 [get_ports "SYSCLK1_300_P"] ;# Bank 47 VCCO - VCC1V2_FPGA - IO_L13P_T2L_N0_GC_QBC_47
-# set_property IOSTANDARD DIFF_SSTL12 [get_ports "SYSCLK1_300_P"] ;# Bank 47 VCCO - VCC1V2_FPGA - IO_L13P_T2L_N0_GC_QBC_47
-# set_property PACKAGE_PIN G32 [get_ports "USER_SI570_CLOCK_N"] ;# Bank 47 VCCO - VCC1V2_FPGA - IO_L12N_T1U_N11_GC_47
-# set_property IOSTANDARD DIFF_SSTL12 [get_ports "USER_SI570_CLOCK_N"] ;# Bank 47 VCCO - VCC1V2_FPGA - IO_L12N_T1U_N11_GC_47
-# set_property PACKAGE_PIN H32 [get_ports "USER_SI570_CLOCK_P"] ;# Bank 47 VCCO - VCC1V2_FPGA - IO_L12P_T1U_N10_GC_47
-# set_property IOSTANDARD DIFF_SSTL12 [get_ports "USER_SI570_CLOCK_P"] ;# Bank 47 VCCO - VCC1V2_FPGA - IO_L12P_T1U_N10_GC_47
-# set_property PACKAGE_PIN H30 [get_ports "RLD3_C3_72B_CK_N"] ;# Bank 47 VCCO - VCC1V2_FPGA - IO_L11N_T1U_N9_GC_47
-# set_property IOSTANDARD DIFF_SSTL12 [get_ports "RLD3_C3_72B_CK_N"] ;# Bank 47 VCCO - VCC1V2_FPGA - IO_L11N_T1U_N9_GC_47
-# set_property PACKAGE_PIN H29 [get_ports "RLD3_C3_72B_CK_P"] ;# Bank 47 VCCO - VCC1V2_FPGA - IO_L11P_T1U_N8_GC_47
-# set_property IOSTANDARD DIFF_SSTL12 [get_ports "RLD3_C3_72B_CK_P"] ;# Bank 47 VCCO - VCC1V2_FPGA - IO_L11P_T1U_N8_GC_47
-# set_property PACKAGE_PIN G33 [get_ports "RLD3_C3_72B_DK3_N"] ;# Bank 47 VCCO - VCC1V2_FPGA - IO_L10N_T1U_N7_QBC_AD4N_47
-# set_property IOSTANDARD DIFF_SSTL12 [get_ports "RLD3_C3_72B_DK3_N"] ;# Bank 47 VCCO - VCC1V2_FPGA - IO_L10N_T1U_N7_QBC_AD4N_47
-# set_property PACKAGE_PIN H33 [get_ports "RLD3_C3_72B_DK3_P"] ;# Bank 47 VCCO - VCC1V2_FPGA - IO_L10P_T1U_N6_QBC_AD4P_47
-# set_property IOSTANDARD DIFF_SSTL12 [get_ports "RLD3_C3_72B_DK3_P"] ;# Bank 47 VCCO - VCC1V2_FPGA - IO_L10P_T1U_N6_QBC_AD4P_47
-# set_property PACKAGE_PIN J30 [get_ports "RLD3_C3_72B_DK2_N"] ;# Bank 47 VCCO - VCC1V2_FPGA - IO_L9N_T1L_N5_AD12N_47
-# set_property IOSTANDARD DIFF_SSTL12 [get_ports "RLD3_C3_72B_DK2_N"] ;# Bank 47 VCCO - VCC1V2_FPGA - IO_L9N_T1L_N5_AD12N_47
-# set_property PACKAGE_PIN J29 [get_ports "RLD3_C3_72B_DK2_P"] ;# Bank 47 VCCO - VCC1V2_FPGA - IO_L9P_T1L_N4_AD12P_47
-# set_property IOSTANDARD DIFF_SSTL12 [get_ports "RLD3_C3_72B_DK2_P"] ;# Bank 47 VCCO - VCC1V2_FPGA - IO_L9P_T1L_N4_AD12P_47
-# set_property PACKAGE_PIN J32 [get_ports "RLD3_C3_72B_DK1_N"] ;# Bank 47 VCCO - VCC1V2_FPGA - IO_L8N_T1L_N3_AD5N_47
-# set_property IOSTANDARD DIFF_SSTL12 [get_ports "RLD3_C3_72B_DK1_N"] ;# Bank 47 VCCO - VCC1V2_FPGA - IO_L8N_T1L_N3_AD5N_47
-# set_property PACKAGE_PIN K32 [get_ports "RLD3_C3_72B_DK1_P"] ;# Bank 47 VCCO - VCC1V2_FPGA - IO_L8P_T1L_N2_AD5P_47
-# set_property IOSTANDARD DIFF_SSTL12 [get_ports "RLD3_C3_72B_DK1_P"] ;# Bank 47 VCCO - VCC1V2_FPGA - IO_L8P_T1L_N2_AD5P_47
-# set_property PACKAGE_PIN J31 [get_ports "RLD3_C3_72B_DK0_N"] ;# Bank 47 VCCO - VCC1V2_FPGA - IO_L7N_T1L_N1_QBC_AD13N_47
-# set_property IOSTANDARD DIFF_SSTL12 [get_ports "RLD3_C3_72B_DK0_N"] ;# Bank 47 VCCO - VCC1V2_FPGA - IO_L7N_T1L_N1_QBC_AD13N_47
-# set_property PACKAGE_PIN K31 [get_ports "RLD3_C3_72B_DK0_P"] ;# Bank 47 VCCO - VCC1V2_FPGA - IO_L7P_T1L_N0_QBC_AD13P_47
-# set_property IOSTANDARD DIFF_SSTL12 [get_ports "RLD3_C3_72B_DK0_P"] ;# Bank 47 VCCO - VCC1V2_FPGA - IO_L7P_T1L_N0_QBC_AD13P_47
-# set_property PACKAGE_PIN K29 [get_ports "RLD3_C3_72B_WE_B"] ;# Bank 47 VCCO - VCC1V2_FPGA - IO_T1U_N12_47
-# set_property IOSTANDARD SSTL12 [get_ports "RLD3_C3_72B_WE_B"] ;# Bank 47 VCCO - VCC1V2_FPGA - IO_T1U_N12_47
-# #set_property PACKAGE_PIN T29 [get_ports "VRP_47"] ;# Bank 47 VCCO - VCC1V2_FPGA - IO_T0U_N12_VRP_47
-# #set_property IOSTANDARD LVCMOSxx [get_ports "VRP_47"] ;# Bank 47 VCCO - VCC1V2_FPGA - IO_T0U_N12_VRP_47
-# set_property PACKAGE_PIN L30 [get_ports "RLD3_C3_72B_REF_B"] ;# Bank 47 VCCO - VCC1V2_FPGA - IO_L6N_T0U_N11_AD6N_47
-# set_property IOSTANDARD SSTL12 [get_ports "RLD3_C3_72B_REF_B"] ;# Bank 47 VCCO - VCC1V2_FPGA - IO_L6N_T0U_N11_AD6N_47
-# set_property PACKAGE_PIN L29 [get_ports "RLD3_C3_72B_RESET_B"] ;# Bank 47 VCCO - VCC1V2_FPGA - IO_L6P_T0U_N10_AD6P_47
-# set_property IOSTANDARD LVCMOS12 [get_ports "RLD3_C3_72B_RESET_B"] ;# Bank 47 VCCO - VCC1V2_FPGA - IO_L6P_T0U_N10_AD6P_47
-# set_property PACKAGE_PIN N29 [get_ports "RLD3_C3_72B_CS_B"] ;# Bank 47 VCCO - VCC1V2_FPGA - IO_L5N_T0U_N9_AD14N_47
-# set_property IOSTANDARD SSTL12 [get_ports "RLD3_C3_72B_CS_B"] ;# Bank 47 VCCO - VCC1V2_FPGA - IO_L5N_T0U_N9_AD14N_47
-
-# set_property PACKAGE_PIN R28 [get_ports "RLD3_C3_72B_A20"] ;# Bank 47 VCCO - VCC1V2_FPGA - IO_L1P_T0L_N0_DBC_47
-# set_property IOSTANDARD SSTL12 [get_ports "RLD3_C3_72B_A20"] ;# Bank 47 VCCO - VCC1V2_FPGA - IO_L1P_T0L_N0_DBC_47
-# #Other net PACKAGE_PIN T28 - 43N2999 Bank 47 - VREF_47
-# set_property PACKAGE_PIN A35 [get_ports "RLD3_C3_72B_DM1"] ;# Bank 46 VCCO - VCC1V2_FPGA - IO_L24N_T3U_N11_46
-# set_property IOSTANDARD SSTL12 [get_ports "RLD3_C3_72B_DM1"] ;# Bank 46 VCCO - VCC1V2_FPGA - IO_L24N_T3U_N11_46
-# set_property PACKAGE_PIN A34 [get_ports "RLD3_C3_72B_DQ35"] ;# Bank 46 VCCO - VCC1V2_FPGA - IO_L24P_T3U_N10_46
-# set_property IOSTANDARD SSTL12 [get_ports "RLD3_C3_72B_DQ35"] ;# Bank 46 VCCO - VCC1V2_FPGA - IO_L24P_T3U_N10_46
-# set_property PACKAGE_PIN A36 [get_ports "RLD3_C3_72B_DQ34"] ;# Bank 46 VCCO - VCC1V2_FPGA - IO_L23N_T3U_N9_46
-# set_property IOSTANDARD SSTL12 [get_ports "RLD3_C3_72B_DQ34"] ;# Bank 46 VCCO - VCC1V2_FPGA - IO_L23N_T3U_N9_46
-# set_property PACKAGE_PIN B35 [get_ports "RLD3_C3_72B_DQ33"] ;# Bank 46 VCCO - VCC1V2_FPGA - IO_L23P_T3U_N8_46
-# set_property IOSTANDARD SSTL12 [get_ports "RLD3_C3_72B_DQ33"] ;# Bank 46 VCCO - VCC1V2_FPGA - IO_L23P_T3U_N8_46
-# set_property PACKAGE_PIN B37 [get_ports "RLD3_C3_72B_DQ32"] ;# Bank 46 VCCO - VCC1V2_FPGA - IO_L22N_T3U_N7_DBC_AD0N_46
-# set_property IOSTANDARD SSTL12 [get_ports "RLD3_C3_72B_DQ32"] ;# Bank 46 VCCO - VCC1V2_FPGA - IO_L22N_T3U_N7_DBC_AD0N_46
-# set_property PACKAGE_PIN B36 [get_ports "RLD3_C3_72B_DQ31"] ;# Bank 46 VCCO - VCC1V2_FPGA - IO_L22P_T3U_N6_DBC_AD0P_46
-# set_property IOSTANDARD SSTL12 [get_ports "RLD3_C3_72B_DQ31"] ;# Bank 46 VCCO - VCC1V2_FPGA - IO_L22P_T3U_N6_DBC_AD0P_46
-# set_property PACKAGE_PIN C34 [get_ports "RLD3_C3_72B_DQ30"] ;# Bank 46 VCCO - VCC1V2_FPGA - IO_L21N_T3L_N5_AD8N_46
-# set_property IOSTANDARD SSTL12 [get_ports "RLD3_C3_72B_DQ30"] ;# Bank 46 VCCO - VCC1V2_FPGA - IO_L21N_T3L_N5_AD8N_46
-# set_property PACKAGE_PIN D34 [get_ports "RLD3_C3_72B_DQ29"] ;# Bank 46 VCCO - VCC1V2_FPGA - IO_L21P_T3L_N4_AD8P_46
-# set_property IOSTANDARD SSTL12 [get_ports "RLD3_C3_72B_DQ29"] ;# Bank 46 VCCO - VCC1V2_FPGA - IO_L21P_T3L_N4_AD8P_46
-# set_property PACKAGE_PIN C35 [get_ports "RLD3_C3_72B_DQ28"] ;# Bank 46 VCCO - VCC1V2_FPGA - IO_L20N_T3L_N3_AD1N_46
-# set_property IOSTANDARD SSTL12 [get_ports "RLD3_C3_72B_DQ28"] ;# Bank 46 VCCO - VCC1V2_FPGA - IO_L20N_T3L_N3_AD1N_46
-# set_property PACKAGE_PIN D35 [get_ports "RLD3_C3_72B_DQ27"] ;# Bank 46 VCCO - VCC1V2_FPGA - IO_L20P_T3L_N2_AD1P_46
-# set_property IOSTANDARD SSTL12 [get_ports "RLD3_C3_72B_DQ27"] ;# Bank 46 VCCO - VCC1V2_FPGA - IO_L20P_T3L_N2_AD1P_46
-# set_property PACKAGE_PIN C37 [get_ports "RLD3_C3_72B_QK3_N"] ;# Bank 46 VCCO - VCC1V2_FPGA - IO_L19N_T3L_N1_DBC_AD9N_46
-# set_property IOSTANDARD DIFF_SSTL12 [get_ports "RLD3_C3_72B_QK3_N"] ;# Bank 46 VCCO - VCC1V2_FPGA - IO_L19N_T3L_N1_DBC_AD9N_46
-# set_property PACKAGE_PIN D37 [get_ports "RLD3_C3_72B_QK3_P"] ;# Bank 46 VCCO - VCC1V2_FPGA - IO_L19P_T3L_N0_DBC_AD9P_46
-# set_property IOSTANDARD DIFF_SSTL12 [get_ports "RLD3_C3_72B_QK3_P"] ;# Bank 46 VCCO - VCC1V2_FPGA - IO_L19P_T3L_N0_DBC_AD9P_46
-# #set_property PACKAGE_PIN D36 [get_ports ""] ;# Bank 46 VCCO - VCC1V2_FPGA - IO_T3U_N12_46
-# #set_property IOSTANDARD LVCMOSxx [get_ports ""] ;# Bank 46 VCCO - VCC1V2_FPGA - IO_T3U_N12_46
-# #set_property PACKAGE_PIN C38 [get_ports ""] ;# Bank 46 VCCO - VCC1V2_FPGA - IO_T2U_N12_46
-# #set_property IOSTANDARD LVCMOSxx [get_ports ""] ;# Bank 46 VCCO - VCC1V2_FPGA - IO_T2U_N12_46
-# set_property PACKAGE_PIN A38 [get_ports "RLD3_C3_72B_QVLD1"] ;# Bank 46 VCCO - VCC1V2_FPGA - IO_L18N_T2U_N11_AD2N_46
-# set_property IOSTANDARD SSTL12 [get_ports "RLD3_C3_72B_QVLD1"] ;# Bank 46 VCCO - VCC1V2_FPGA - IO_L18N_T2U_N11_AD2N_46
-# set_property PACKAGE_PIN B38 [get_ports "RLD3_C3_72B_DQ26"] ;# Bank 46 VCCO - VCC1V2_FPGA - IO_L18P_T2U_N10_AD2P_46
-# set_property IOSTANDARD SSTL12 [get_ports "RLD3_C3_72B_DQ26"] ;# Bank 46 VCCO - VCC1V2_FPGA - IO_L18P_T2U_N10_AD2P_46
-# set_property PACKAGE_PIN C40 [get_ports "RLD3_C3_72B_DQ25"] ;# Bank 46 VCCO - VCC1V2_FPGA - IO_L17N_T2U_N9_AD10N_46
-# set_property IOSTANDARD SSTL12 [get_ports "RLD3_C3_72B_DQ25"] ;# Bank 46 VCCO - VCC1V2_FPGA - IO_L17N_T2U_N9_AD10N_46
-# set_property PACKAGE_PIN D40 [get_ports "RLD3_C3_72B_DQ24"] ;# Bank 46 VCCO - VCC1V2_FPGA - IO_L17P_T2U_N8_AD10P_46
-# set_property IOSTANDARD SSTL12 [get_ports "RLD3_C3_72B_DQ24"] ;# Bank 46 VCCO - VCC1V2_FPGA - IO_L17P_T2U_N8_AD10P_46
-# set_property PACKAGE_PIN A40 [get_ports "RLD3_C3_72B_DQ23"] ;# Bank 46 VCCO - VCC1V2_FPGA - IO_L16N_T2U_N7_QBC_AD3N_46
-# set_property IOSTANDARD SSTL12 [get_ports "RLD3_C3_72B_DQ23"] ;# Bank 46 VCCO - VCC1V2_FPGA - IO_L16N_T2U_N7_QBC_AD3N_46
-# set_property PACKAGE_PIN A39 [get_ports "RLD3_C3_72B_DQ22"] ;# Bank 46 VCCO - VCC1V2_FPGA - IO_L16P_T2U_N6_QBC_AD3P_46
-# set_property IOSTANDARD SSTL12 [get_ports "RLD3_C3_72B_DQ22"] ;# Bank 46 VCCO - VCC1V2_FPGA - IO_L16P_T2U_N6_QBC_AD3P_46
-# set_property PACKAGE_PIN B40 [get_ports "RLD3_C3_72B_DQ21"] ;# Bank 46 VCCO - VCC1V2_FPGA - IO_L15N_T2L_N5_AD11N_46
-# set_property IOSTANDARD SSTL12 [get_ports "RLD3_C3_72B_DQ21"] ;# Bank 46 VCCO - VCC1V2_FPGA - IO_L15N_T2L_N5_AD11N_46
-# set_property PACKAGE_PIN C39 [get_ports "RLD3_C3_72B_DQ20"] ;# Bank 46 VCCO - VCC1V2_FPGA - IO_L15P_T2L_N4_AD11P_46
-# set_property IOSTANDARD SSTL12 [get_ports "RLD3_C3_72B_DQ20"] ;# Bank 46 VCCO - VCC1V2_FPGA - IO_L15P_T2L_N4_AD11P_46
-# set_property PACKAGE_PIN E38 [get_ports "RLD3_C3_72B_DQ19"] ;# Bank 46 VCCO - VCC1V2_FPGA - IO_L14N_T2L_N3_GC_46
-# set_property IOSTANDARD SSTL12 [get_ports "RLD3_C3_72B_DQ19"] ;# Bank 46 VCCO - VCC1V2_FPGA - IO_L14N_T2L_N3_GC_46
-# set_property PACKAGE_PIN E37 [get_ports "RLD3_C3_72B_DQ18"] ;# Bank 46 VCCO - VCC1V2_FPGA - IO_L14P_T2L_N2_GC_46
-# set_property IOSTANDARD SSTL12 [get_ports "RLD3_C3_72B_DQ18"] ;# Bank 46 VCCO - VCC1V2_FPGA - IO_L14P_T2L_N2_GC_46
-# set_property PACKAGE_PIN D39 [get_ports "RLD3_C3_72B_QK2_N"] ;# Bank 46 VCCO - VCC1V2_FPGA - IO_L13N_T2L_N1_GC_QBC_46
-# set_property IOSTANDARD DIFF_SSTL12 [get_ports "RLD3_C3_72B_QK2_N"] ;# Bank 46 VCCO - VCC1V2_FPGA - IO_L13N_T2L_N1_GC_QBC_46
-# set_property PACKAGE_PIN E39 [get_ports "RLD3_C3_72B_QK2_P"] ;# Bank 46 VCCO - VCC1V2_FPGA - IO_L13P_T2L_N0_GC_QBC_46
-# set_property IOSTANDARD DIFF_SSTL12 [get_ports "RLD3_C3_72B_QK2_P"] ;# Bank 46 VCCO - VCC1V2_FPGA - IO_L13P_T2L_N0_GC_QBC_46
-# set_property PACKAGE_PIN G37 [get_ports "RLD3_C3_72B_QVLD0"] ;# Bank 46 VCCO - VCC1V2_FPGA - IO_L12N_T1U_N11_GC_46
-# set_property IOSTANDARD SSTL12 [get_ports "RLD3_C3_72B_QVLD0"] ;# Bank 46 VCCO - VCC1V2_FPGA - IO_L12N_T1U_N11_GC_46
-# set_property PACKAGE_PIN G36 [get_ports "RLD3_C3_72B_DQ17"] ;# Bank 46 VCCO - VCC1V2_FPGA - IO_L12P_T1U_N10_GC_46
-# set_property IOSTANDARD SSTL12 [get_ports "RLD3_C3_72B_DQ17"] ;# Bank 46 VCCO - VCC1V2_FPGA - IO_L12P_T1U_N10_GC_46
-# set_property PACKAGE_PIN F36 [get_ports "RLD3_C3_72B_DQ16"] ;# Bank 46 VCCO - VCC1V2_FPGA - IO_L11N_T1U_N9_GC_46
-# set_property IOSTANDARD SSTL12 [get_ports "RLD3_C3_72B_DQ16"] ;# Bank 46 VCCO - VCC1V2_FPGA - IO_L11N_T1U_N9_GC_46
-# set_property PACKAGE_PIN F35 [get_ports "RLD3_C3_72B_DQ15"] ;# Bank 46 VCCO - VCC1V2_FPGA - IO_L11P_T1U_N8_GC_46
-# set_property IOSTANDARD SSTL12 [get_ports "RLD3_C3_72B_DQ15"] ;# Bank 46 VCCO - VCC1V2_FPGA - IO_L11P_T1U_N8_GC_46
-# set_property PACKAGE_PIN G35 [get_ports "RLD3_C3_72B_DQ14"] ;# Bank 46 VCCO - VCC1V2_FPGA - IO_L10N_T1U_N7_QBC_AD4N_46
-# set_property IOSTANDARD SSTL12 [get_ports "RLD3_C3_72B_DQ14"] ;# Bank 46 VCCO - VCC1V2_FPGA - IO_L10N_T1U_N7_QBC_AD4N_46
-# set_property PACKAGE_PIN H34 [get_ports "RLD3_C3_72B_DQ13"] ;# Bank 46 VCCO - VCC1V2_FPGA - IO_L10P_T1U_N6_QBC_AD4P_46
-# set_property IOSTANDARD SSTL12 [get_ports "RLD3_C3_72B_DQ13"] ;# Bank 46 VCCO - VCC1V2_FPGA - IO_L10P_T1U_N6_QBC_AD4P_46
-# set_property PACKAGE_PIN H37 [get_ports "RLD3_C3_72B_DQ12"] ;# Bank 46 VCCO - VCC1V2_FPGA - IO_L9N_T1L_N5_AD12N_46
-# set_property IOSTANDARD SSTL12 [get_ports "RLD3_C3_72B_DQ12"] ;# Bank 46 VCCO - VCC1V2_FPGA - IO_L9N_T1L_N5_AD12N_46
-# set_property PACKAGE_PIN J36 [get_ports "RLD3_C3_72B_DQ11"] ;# Bank 46 VCCO - VCC1V2_FPGA - IO_L9P_T1L_N4_AD12P_46
-# set_property IOSTANDARD SSTL12 [get_ports "RLD3_C3_72B_DQ11"] ;# Bank 46 VCCO - VCC1V2_FPGA - IO_L9P_T1L_N4_AD12P_46
-# set_property PACKAGE_PIN H35 [get_ports "RLD3_C3_72B_DQ10"] ;# Bank 46 VCCO - VCC1V2_FPGA - IO_L8N_T1L_N3_AD5N_46
-# set_property IOSTANDARD SSTL12 [get_ports "RLD3_C3_72B_DQ10"] ;# Bank 46 VCCO - VCC1V2_FPGA - IO_L8N_T1L_N3_AD5N_46
-# set_property PACKAGE_PIN J35 [get_ports "RLD3_C3_72B_DQ9"] ;# Bank 46 VCCO - VCC1V2_FPGA - IO_L8P_T1L_N2_AD5P_46
-# set_property IOSTANDARD SSTL12 [get_ports "RLD3_C3_72B_DQ9"] ;# Bank 46 VCCO - VCC1V2_FPGA - IO_L8P_T1L_N2_AD5P_46
-# set_property PACKAGE_PIN E34 [get_ports "RLD3_C3_72B_QK1_N"] ;# Bank 46 VCCO - VCC1V2_FPGA - IO_L7N_T1L_N1_QBC_AD13N_46
-# set_property IOSTANDARD DIFF_SSTL12 [get_ports "RLD3_C3_72B_QK1_N"] ;# Bank 46 VCCO - VCC1V2_FPGA - IO_L7N_T1L_N1_QBC_AD13N_46
-# set_property PACKAGE_PIN F34 [get_ports "RLD3_C3_72B_QK1_P"] ;# Bank 46 VCCO - VCC1V2_FPGA - IO_L7P_T1L_N0_QBC_AD13P_46
-# set_property IOSTANDARD DIFF_SSTL12 [get_ports "RLD3_C3_72B_QK1_P"] ;# Bank 46 VCCO - VCC1V2_FPGA - IO_L7P_T1L_N0_QBC_AD13P_46
-# #set_property PACKAGE_PIN E36 [get_ports ""] ;# Bank 46 VCCO - VCC1V2_FPGA - IO_T1U_N12_46
-# #set_property IOSTANDARD LVCMOSxx [get_ports ""] ;# Bank 46 VCCO - VCC1V2_FPGA - IO_T1U_N12_46
-# #set_property PACKAGE_PIN K38 [get_ports "VRP_46"] ;# Bank 46 VCCO - VCC1V2_FPGA - IO_T0U_N12_VRP_46
-# #set_property IOSTANDARD LVCMOSxx [get_ports "VRP_46"] ;# Bank 46 VCCO - VCC1V2_FPGA - IO_T0U_N12_VRP_46
-# set_property PACKAGE_PIN F39 [get_ports "RLD3_C3_72B_DM0"] ;# Bank 46 VCCO - VCC1V2_FPGA - IO_L6N_T0U_N11_AD6N_46
-# set_property IOSTANDARD SSTL12 [get_ports "RLD3_C3_72B_DM0"] ;# Bank 46 VCCO - VCC1V2_FPGA - IO_L6N_T0U_N11_AD6N_46
-# set_property PACKAGE_PIN F38 [get_ports "RLD3_C3_72B_DQ8"] ;# Bank 46 VCCO - VCC1V2_FPGA - IO_L6P_T0U_N10_AD6P_46
-# set_property IOSTANDARD SSTL12 [get_ports "RLD3_C3_72B_DQ8"] ;# Bank 46 VCCO - VCC1V2_FPGA - IO_L6P_T0U_N10_AD6P_46
-# set_property PACKAGE_PIN J37 [get_ports "RLD3_C3_72B_DQ7"] ;# Bank 46 VCCO - VCC1V2_FPGA - IO_L5N_T0U_N9_AD14N_46
-# set_property IOSTANDARD SSTL12 [get_ports "RLD3_C3_72B_DQ7"] ;# Bank 46 VCCO - VCC1V2_FPGA - IO_L5N_T0U_N9_AD14N_46
-# set_property PACKAGE_PIN K37 [get_ports "RLD3_C3_72B_DQ6"] ;# Bank 46 VCCO - VCC1V2_FPGA - IO_L5P_T0U_N8_AD14P_46
-# set_property IOSTANDARD SSTL12 [get_ports "RLD3_C3_72B_DQ6"] ;# Bank 46 VCCO - VCC1V2_FPGA - IO_L5P_T0U_N8_AD14P_46
-# set_property PACKAGE_PIN G38 [get_ports "RLD3_C3_72B_DQ5"] ;# Bank 46 VCCO - VCC1V2_FPGA - IO_L4N_T0U_N7_DBC_AD7N_46
-# set_property IOSTANDARD SSTL12 [get_ports "RLD3_C3_72B_DQ5"] ;# Bank 46 VCCO - VCC1V2_FPGA - IO_L4N_T0U_N7_DBC_AD7N_46
-# set_property PACKAGE_PIN H38 [get_ports "RLD3_C3_72B_DQ4"] ;# Bank 46 VCCO - VCC1V2_FPGA - IO_L4P_T0U_N6_DBC_AD7P_46
-# set_property IOSTANDARD SSTL12 [get_ports "RLD3_C3_72B_DQ4"] ;# Bank 46 VCCO - VCC1V2_FPGA - IO_L4P_T0U_N6_DBC_AD7P_46
-# set_property PACKAGE_PIN F40 [get_ports "RLD3_C3_72B_DQ3"] ;# Bank 46 VCCO - VCC1V2_FPGA - IO_L3N_T0L_N5_AD15N_46
-# set_property IOSTANDARD SSTL12 [get_ports "RLD3_C3_72B_DQ3"] ;# Bank 46 VCCO - VCC1V2_FPGA - IO_L3N_T0L_N5_AD15N_46
-# set_property PACKAGE_PIN G40 [get_ports "RLD3_C3_72B_DQ2"] ;# Bank 46 VCCO - VCC1V2_FPGA - IO_L3P_T0L_N4_AD15P_46
-# set_property IOSTANDARD SSTL12 [get_ports "RLD3_C3_72B_DQ2"] ;# Bank 46 VCCO - VCC1V2_FPGA - IO_L3P_T0L_N4_AD15P_46
-# set_property PACKAGE_PIN H40 [get_ports "RLD3_C3_72B_DQ1"] ;# Bank 46 VCCO - VCC1V2_FPGA - IO_L2N_T0L_N3_46
-# set_property IOSTANDARD SSTL12 [get_ports "RLD3_C3_72B_DQ1"] ;# Bank 46 VCCO - VCC1V2_FPGA - IO_L2N_T0L_N3_46
-# set_property PACKAGE_PIN H39 [get_ports "RLD3_C3_72B_DQ0"] ;# Bank 46 VCCO - VCC1V2_FPGA - IO_L2P_T0L_N2_46
-# set_property IOSTANDARD SSTL12 [get_ports "RLD3_C3_72B_DQ0"] ;# Bank 46 VCCO - VCC1V2_FPGA - IO_L2P_T0L_N2_46
-# set_property PACKAGE_PIN J40 [get_ports "RLD3_C3_72B_QK0_N"] ;# Bank 46 VCCO - VCC1V2_FPGA - IO_L1N_T0L_N1_DBC_46
-# set_property IOSTANDARD DIFF_SSTL12 [get_ports "RLD3_C3_72B_QK0_N"] ;# Bank 46 VCCO - VCC1V2_FPGA - IO_L1N_T0L_N1_DBC_46
-# set_property PACKAGE_PIN J39 [get_ports "RLD3_C3_72B_QK0_P"] ;# Bank 46 VCCO - VCC1V2_FPGA - IO_L1P_T0L_N0_DBC_46
-# set_property IOSTANDARD DIFF_SSTL12 [get_ports "RLD3_C3_72B_QK0_P"] ;# Bank 46 VCCO - VCC1V2_FPGA - IO_L1P_T0L_N0_DBC_46
-# #Other net PACKAGE_PIN J34 - Bank 46 - VREF_46
-# set_property PACKAGE_PIN L35 [get_ports "FMCP_HSPC_LA21_N"] ;# Bank 45 VCCO - VADJ_1V8_FPGA - IO_L24N_T3U_N11_45
-# set_property IOSTANDARD LVDS [get_ports "FMCP_HSPC_LA21_N"] ;# Bank 45 VCCO - VADJ_1V8_FPGA - IO_L24N_T3U_N11_45
-# set_property PACKAGE_PIN M35 [get_ports "FMCP_HSPC_LA21_P"] ;# Bank 45 VCCO - VADJ_1V8_FPGA - IO_L24P_T3U_N10_45
-# set_property IOSTANDARD LVDS [get_ports "FMCP_HSPC_LA21_P"] ;# Bank 45 VCCO - VADJ_1V8_FPGA - IO_L24P_T3U_N10_45
-# set_property PACKAGE_PIN M32 [get_ports "FMCP_HSPC_LA20_N"] ;# Bank 45 VCCO - VADJ_1V8_FPGA - IO_L23N_T3U_N9_45
-# set_property IOSTANDARD LVDS [get_ports "FMCP_HSPC_LA20_N"] ;# Bank 45 VCCO - VADJ_1V8_FPGA - IO_L23N_T3U_N9_45
-# set_property PACKAGE_PIN N32 [get_ports "FMCP_HSPC_LA20_P"] ;# Bank 45 VCCO - VADJ_1V8_FPGA - IO_L23P_T3U_N8_45
-# set_property IOSTANDARD LVDS [get_ports "FMCP_HSPC_LA20_P"] ;# Bank 45 VCCO - VADJ_1V8_FPGA - IO_L23P_T3U_N8_45
-# set_property PACKAGE_PIN M33 [get_ports "FMCP_HSPC_LA19_N"] ;# Bank 45 VCCO - VADJ_1V8_FPGA - IO_L22N_T3U_N7_DBC_AD0N_45
-# set_property IOSTANDARD LVDS [get_ports "FMCP_HSPC_LA19_N"] ;# Bank 45 VCCO - VADJ_1V8_FPGA - IO_L22N_T3U_N7_DBC_AD0N_45
-# set_property PACKAGE_PIN N33 [get_ports "FMCP_HSPC_LA19_P"] ;# Bank 45 VCCO - VADJ_1V8_FPGA - IO_L22P_T3U_N6_DBC_AD0P_45
-# set_property IOSTANDARD LVDS [get_ports "FMCP_HSPC_LA19_P"] ;# Bank 45 VCCO - VADJ_1V8_FPGA - IO_L22P_T3U_N6_DBC_AD0P_45
-# set_property PACKAGE_PIN K33 [get_ports "FMCP_HSPC_LA32_N"] ;# Bank 45 VCCO - VADJ_1V8_FPGA - IO_L21N_T3L_N5_AD8N_45
-# set_property IOSTANDARD LVDS [get_ports "FMCP_HSPC_LA32_N"] ;# Bank 45 VCCO - VADJ_1V8_FPGA - IO_L21N_T3L_N5_AD8N_45
-# set_property PACKAGE_PIN L33 [get_ports "FMCP_HSPC_LA32_P"] ;# Bank 45 VCCO - VADJ_1V8_FPGA - IO_L21P_T3L_N4_AD8P_45
-# set_property IOSTANDARD LVDS [get_ports "FMCP_HSPC_LA32_P"] ;# Bank 45 VCCO - VADJ_1V8_FPGA - IO_L21P_T3L_N4_AD8P_45
-# set_property PACKAGE_PIN N35 [get_ports "FMCP_HSPC_LA22_N"] ;# Bank 45 VCCO - VADJ_1V8_FPGA - IO_L20N_T3L_N3_AD1N_45
-# set_property IOSTANDARD LVDS [get_ports "FMCP_HSPC_LA22_N"] ;# Bank 45 VCCO - VADJ_1V8_FPGA - IO_L20N_T3L_N3_AD1N_45
-# set_property PACKAGE_PIN N34 [get_ports "FMCP_HSPC_LA22_P"] ;# Bank 45 VCCO - VADJ_1V8_FPGA - IO_L20P_T3L_N2_AD1P_45
-# set_property IOSTANDARD LVDS [get_ports "FMCP_HSPC_LA22_P"] ;# Bank 45 VCCO - VADJ_1V8_FPGA - IO_L20P_T3L_N2_AD1P_45
-# set_property PACKAGE_PIN K34 [get_ports "FMCP_HSPC_LA33_N"] ;# Bank 45 VCCO - VADJ_1V8_FPGA - IO_L19N_T3L_N1_DBC_AD9N_45
-# set_property IOSTANDARD LVDS [get_ports "FMCP_HSPC_LA33_N"] ;# Bank 45 VCCO - VADJ_1V8_FPGA - IO_L19N_T3L_N1_DBC_AD9N_45
-# set_property PACKAGE_PIN L34 [get_ports "FMCP_HSPC_LA33_P"] ;# Bank 45 VCCO - VADJ_1V8_FPGA - IO_L19P_T3L_N0_DBC_AD9P_45
-# set_property IOSTANDARD LVDS [get_ports "FMCP_HSPC_LA33_P"] ;# Bank 45 VCCO - VADJ_1V8_FPGA - IO_L19P_T3L_N0_DBC_AD9P_45
-# #set_property PACKAGE_PIN K36 [get_ports ""] ;# Bank 45 VCCO - VADJ_1V8_FPGA - IO_T3U_N12_45
-# #set_property IOSTANDARD LVCMOSxx [get_ports ""] ;# Bank 45 VCCO - VADJ_1V8_FPGA - IO_T3U_N12_45
-# #set_property PACKAGE_PIN R36 [get_ports ""] ;# Bank 45 VCCO - VADJ_1V8_FPGA - IO_T2U_N12_45
-# #set_property IOSTANDARD LVCMOSxx [get_ports ""] ;# Bank 45 VCCO - VADJ_1V8_FPGA - IO_T2U_N12_45
-# set_property PACKAGE_PIN M38 [get_ports "FMCP_HSPC_LA30_N"] ;# Bank 45 VCCO - VADJ_1V8_FPGA - IO_L18N_T2U_N11_AD2N_45
-# set_property IOSTANDARD LVDS [get_ports "FMCP_HSPC_LA30_N"] ;# Bank 45 VCCO - VADJ_1V8_FPGA - IO_L18N_T2U_N11_AD2N_45
-# set_property PACKAGE_PIN N38 [get_ports "FMCP_HSPC_LA30_P"] ;# Bank 45 VCCO - VADJ_1V8_FPGA - IO_L18P_T2U_N10_AD2P_45
-# set_property IOSTANDARD LVDS [get_ports "FMCP_HSPC_LA30_P"] ;# Bank 45 VCCO - VADJ_1V8_FPGA - IO_L18P_T2U_N10_AD2P_45
-# set_property PACKAGE_PIN L36 [get_ports "FMCP_HSPC_LA28_N"] ;# Bank 45 VCCO - VADJ_1V8_FPGA - IO_L17N_T2U_N9_AD10N_45
-# set_property IOSTANDARD LVDS [get_ports "FMCP_HSPC_LA28_N"] ;# Bank 45 VCCO - VADJ_1V8_FPGA - IO_L17N_T2U_N9_AD10N_45
-# set_property PACKAGE_PIN M36 [get_ports "FMCP_HSPC_LA28_P"] ;# Bank 45 VCCO - VADJ_1V8_FPGA - IO_L17P_T2U_N8_AD10P_45
-# set_property IOSTANDARD LVDS [get_ports "FMCP_HSPC_LA28_P"] ;# Bank 45 VCCO - VADJ_1V8_FPGA - IO_L17P_T2U_N8_AD10P_45
-# set_property PACKAGE_PIN N37 [get_ports "FMCP_HSPC_LA31_N"] ;# Bank 45 VCCO - VADJ_1V8_FPGA - IO_L16N_T2U_N7_QBC_AD3N_45
-# set_property IOSTANDARD LVDS [get_ports "FMCP_HSPC_LA31_N"] ;# Bank 45 VCCO - VADJ_1V8_FPGA - IO_L16N_T2U_N7_QBC_AD3N_45
-# set_property PACKAGE_PIN P37 [get_ports "FMCP_HSPC_LA31_P"] ;# Bank 45 VCCO - VADJ_1V8_FPGA - IO_L16P_T2U_N6_QBC_AD3P_45
-# set_property IOSTANDARD LVDS [get_ports "FMCP_HSPC_LA31_P"] ;# Bank 45 VCCO - VADJ_1V8_FPGA - IO_L16P_T2U_N6_QBC_AD3P_45
-# #set_property PACKAGE_PIN L38 [get_ports ""] ;# Bank 45 VCCO - VADJ_1V8_FPGA - IO_L15N_T2L_N5_AD11N_45
-# #set_property IOSTANDARD LVCMOSxx [get_ports ""] ;# Bank 45 VCCO - VADJ_1V8_FPGA - IO_L15N_T2L_N5_AD11N_45
-# #set_property PACKAGE_PIN M37 [get_ports ""] ;# Bank 45 VCCO - VADJ_1V8_FPGA - IO_L15P_T2L_N4_AD11P_45
-# #set_property IOSTANDARD LVCMOSxx [get_ports ""] ;# Bank 45 VCCO - VADJ_1V8_FPGA - IO_L15P_T2L_N4_AD11P_45
-# set_property PACKAGE_PIN P36 [get_ports "FMCP_HSPC_CLK1_M2C_N"] ;# Bank 45 VCCO - VADJ_1V8_FPGA - IO_L14N_T2L_N3_GC_45
-# set_property IOSTANDARD LVDS [get_ports "FMCP_HSPC_CLK1_M2C_N"] ;# Bank 45 VCCO - VADJ_1V8_FPGA - IO_L14N_T2L_N3_GC_45
-# set_property PACKAGE_PIN P35 [get_ports "FMCP_HSPC_CLK1_M2C_P"] ;# Bank 45 VCCO - VADJ_1V8_FPGA - IO_L14P_T2L_N2_GC_45
-# set_property IOSTANDARD LVDS [get_ports "FMCP_HSPC_CLK1_M2C_P"] ;# Bank 45 VCCO - VADJ_1V8_FPGA - IO_L14P_T2L_N2_GC_45
-# set_property PACKAGE_PIN P34 [get_ports "FMCP_HSPC_LA17_CC_N"] ;# Bank 45 VCCO - VADJ_1V8_FPGA - IO_L13N_T2L_N1_GC_QBC_45
-# set_property IOSTANDARD LVDS [get_ports "FMCP_HSPC_LA17_CC_N"] ;# Bank 45 VCCO - VADJ_1V8_FPGA - IO_L13N_T2L_N1_GC_QBC_45
-# set_property PACKAGE_PIN R34 [get_ports "FMCP_HSPC_LA17_CC_P"] ;# Bank 45 VCCO - VADJ_1V8_FPGA - IO_L13P_T2L_N0_GC_QBC_45
-# set_property IOSTANDARD LVDS [get_ports "FMCP_HSPC_LA17_CC_P"] ;# Bank 45 VCCO - VADJ_1V8_FPGA - IO_L13P_T2L_N0_GC_QBC_45
-# #set_property PACKAGE_PIN R33 [get_ports ""] ;# Bank 45 VCCO - VADJ_1V8_FPGA - IO_L12N_T1U_N11_GC_45
-# #set_property IOSTANDARD LVCMOSxx [get_ports ""] ;# Bank 45 VCCO - VADJ_1V8_FPGA - IO_L12N_T1U_N11_GC_45
-# #set_property PACKAGE_PIN T33 [get_ports ""] ;# Bank 45 VCCO - VADJ_1V8_FPGA - IO_L12P_T1U_N10_GC_45
-# #set_property IOSTANDARD LVCMOSxx [get_ports ""] ;# Bank 45 VCCO - VADJ_1V8_FPGA - IO_L12P_T1U_N10_GC_45
-# set_property PACKAGE_PIN P32 [get_ports "USER_SMA_CLOCK_N"] ;# Bank 45 VCCO - VADJ_1V8_FPGA - IO_L11N_T1U_N9_GC_45
-# set_property IOSTANDARD LVDS [get_ports "USER_SMA_CLOCK_N"] ;# Bank 45 VCCO - VADJ_1V8_FPGA - IO_L11N_T1U_N9_GC_45
-# set_property PACKAGE_PIN R32 [get_ports "USER_SMA_CLOCK_P"] ;# Bank 45 VCCO - VADJ_1V8_FPGA - IO_L11P_T1U_N8_GC_45
-# set_property IOSTANDARD LVDS [get_ports "USER_SMA_CLOCK_P"] ;# Bank 45 VCCO - VADJ_1V8_FPGA - IO_L11P_T1U_N8_GC_45
-# set_property PACKAGE_PIN P31 [get_ports "FMCP_HSPC_LA18_CC_N"] ;# Bank 45 VCCO - VADJ_1V8_FPGA - IO_L10N_T1U_N7_QBC_AD4N_45
-# set_property IOSTANDARD LVDS [get_ports "FMCP_HSPC_LA18_CC_N"] ;# Bank 45 VCCO - VADJ_1V8_FPGA - IO_L10N_T1U_N7_QBC_AD4N_45
-# set_property PACKAGE_PIN R31 [get_ports "FMCP_HSPC_LA18_CC_P"] ;# Bank 45 VCCO - VADJ_1V8_FPGA - IO_L10P_T1U_N6_QBC_AD4P_45
-# set_property IOSTANDARD LVDS [get_ports "FMCP_HSPC_LA18_CC_P"] ;# Bank 45 VCCO - VADJ_1V8_FPGA - IO_L10P_T1U_N6_QBC_AD4P_45
-# #set_property PACKAGE_PIN W31 [get_ports ""] ;# Bank 45 VCCO - VADJ_1V8_FPGA - IO_L9N_T1L_N5_AD12N_45
-# #set_property IOSTANDARD LVCMOSxx [get_ports ""] ;# Bank 45 VCCO - VADJ_1V8_FPGA - IO_L9N_T1L_N5_AD12N_45
-# #set_property PACKAGE_PIN Y31 [get_ports ""] ;# Bank 45 VCCO - VADJ_1V8_FPGA - IO_L9P_T1L_N4_AD12P_45
-# #set_property IOSTANDARD LVCMOSxx [get_ports ""] ;# Bank 45 VCCO - VADJ_1V8_FPGA - IO_L9P_T1L_N4_AD12P_45
-# #set_property PACKAGE_PIN U32 [get_ports ""] ;# Bank 45 VCCO - VADJ_1V8_FPGA - IO_L8N_T1L_N3_AD5N_45
-# #set_property IOSTANDARD LVCMOSxx [get_ports ""] ;# Bank 45 VCCO - VADJ_1V8_FPGA - IO_L8N_T1L_N3_AD5N_45
-# #set_property PACKAGE_PIN U31 [get_ports ""] ;# Bank 45 VCCO - VADJ_1V8_FPGA - IO_L8P_T1L_N2_AD5P_45
-# #set_property IOSTANDARD LVCMOSxx [get_ports ""] ;# Bank 45 VCCO - VADJ_1V8_FPGA - IO_L8P_T1L_N2_AD5P_45
-# #set_property PACKAGE_PIN T31 [get_ports ""] ;# Bank 45 VCCO - VADJ_1V8_FPGA - IO_L7N_T1L_N1_QBC_AD13N_45
-# #set_property IOSTANDARD LVCMOSxx [get_ports ""] ;# Bank 45 VCCO - VADJ_1V8_FPGA - IO_L7N_T1L_N1_QBC_AD13N_45
-# #set_property PACKAGE_PIN T30 [get_ports ""] ;# Bank 45 VCCO - VADJ_1V8_FPGA - IO_L7P_T1L_N0_QBC_AD13P_45
-# #set_property IOSTANDARD LVCMOSxx [get_ports ""] ;# Bank 45 VCCO - VADJ_1V8_FPGA - IO_L7P_T1L_N0_QBC_AD13P_45
-# #set_property PACKAGE_PIN V30 [get_ports ""] ;# Bank 45 VCCO - VADJ_1V8_FPGA - IO_T1U_N12_45
-# #set_property IOSTANDARD LVCMOSxx [get_ports ""] ;# Bank 45 VCCO - VADJ_1V8_FPGA - IO_T1U_N12_45
-# #set_property PACKAGE_PIN Y33 [get_ports "VRP_45"] ;# Bank 45 VCCO - VADJ_1V8_FPGA - IO_T0U_N12_VRP_45
-# #set_property IOSTANDARD LVCMOSxx [get_ports "VRP_45"] ;# Bank 45 VCCO - VADJ_1V8_FPGA - IO_T0U_N12_VRP_45
-# set_property PACKAGE_PIN T35 [get_ports "FMCP_HSPC_LA24_N"] ;# Bank 45 VCCO - VADJ_1V8_FPGA - IO_L6N_T0U_N11_AD6N_45
-# set_property IOSTANDARD LVDS [get_ports "FMCP_HSPC_LA24_N"] ;# Bank 45 VCCO - VADJ_1V8_FPGA - IO_L6N_T0U_N11_AD6N_45
-# set_property PACKAGE_PIN T34 [get_ports "FMCP_HSPC_LA24_P"] ;# Bank 45 VCCO - VADJ_1V8_FPGA - IO_L6P_T0U_N10_AD6P_45
-# set_property IOSTANDARD LVDS [get_ports "FMCP_HSPC_LA24_P"] ;# Bank 45 VCCO - VADJ_1V8_FPGA - IO_L6P_T0U_N10_AD6P_45
-# set_property PACKAGE_PIN V34 [get_ports "FMCP_HSPC_LA27_N"] ;# Bank 45 VCCO - VADJ_1V8_FPGA - IO_L5N_T0U_N9_AD14N_45
-# set_property IOSTANDARD LVDS [get_ports "FMCP_HSPC_LA27_N"] ;# Bank 45 VCCO - VADJ_1V8_FPGA - IO_L5N_T0U_N9_AD14N_45
-# set_property PACKAGE_PIN V33 [get_ports "FMCP_HSPC_LA27_P"] ;# Bank 45 VCCO - VADJ_1V8_FPGA - IO_L5P_T0U_N8_AD14P_45
-# set_property IOSTANDARD LVDS [get_ports "FMCP_HSPC_LA27_P"] ;# Bank 45 VCCO - VADJ_1V8_FPGA - IO_L5P_T0U_N8_AD14P_45
-# set_property PACKAGE_PIN T36 [get_ports "FMCP_HSPC_LA29_N"] ;# Bank 45 VCCO - VADJ_1V8_FPGA - IO_L4N_T0U_N7_DBC_AD7N_45
-# set_property IOSTANDARD LVDS [get_ports "FMCP_HSPC_LA29_N"] ;# Bank 45 VCCO - VADJ_1V8_FPGA - IO_L4N_T0U_N7_DBC_AD7N_45
-# set_property PACKAGE_PIN U35 [get_ports "FMCP_HSPC_LA29_P"] ;# Bank 45 VCCO - VADJ_1V8_FPGA - IO_L4P_T0U_N6_DBC_AD7P_45
-# set_property IOSTANDARD LVDS [get_ports "FMCP_HSPC_LA29_P"] ;# Bank 45 VCCO - VADJ_1V8_FPGA - IO_L4P_T0U_N6_DBC_AD7P_45
-# set_property PACKAGE_PIN W34 [get_ports "FMCP_HSPC_LA25_N"] ;# Bank 45 VCCO - VADJ_1V8_FPGA - IO_L3N_T0L_N5_AD15N_45
-# set_property IOSTANDARD LVDS [get_ports "FMCP_HSPC_LA25_N"] ;# Bank 45 VCCO - VADJ_1V8_FPGA - IO_L3N_T0L_N5_AD15N_45
-# set_property PACKAGE_PIN Y34 [get_ports "FMCP_HSPC_LA25_P"] ;# Bank 45 VCCO - VADJ_1V8_FPGA - IO_L3P_T0L_N4_AD15P_45
-# set_property IOSTANDARD LVDS [get_ports "FMCP_HSPC_LA25_P"] ;# Bank 45 VCCO - VADJ_1V8_FPGA - IO_L3P_T0L_N4_AD15P_45
-# set_property PACKAGE_PIN U33 [get_ports "FMCP_HSPC_LA26_N"] ;# Bank 45 VCCO - VADJ_1V8_FPGA - IO_L2N_T0L_N3_45
-# set_property IOSTANDARD LVDS [get_ports "FMCP_HSPC_LA26_N"] ;# Bank 45 VCCO - VADJ_1V8_FPGA - IO_L2N_T0L_N3_45
-# set_property PACKAGE_PIN V32 [get_ports "FMCP_HSPC_LA26_P"] ;# Bank 45 VCCO - VADJ_1V8_FPGA - IO_L2P_T0L_N2_45
-# set_property IOSTANDARD LVDS [get_ports "FMCP_HSPC_LA26_P"] ;# Bank 45 VCCO - VADJ_1V8_FPGA - IO_L2P_T0L_N2_45
-# set_property PACKAGE_PIN W32 [get_ports "FMCP_HSPC_LA23_N"] ;# Bank 45 VCCO - VADJ_1V8_FPGA - IO_L1N_T0L_N1_DBC_45
-# set_property IOSTANDARD LVDS [get_ports "FMCP_HSPC_LA23_N"] ;# Bank 45 VCCO - VADJ_1V8_FPGA - IO_L1N_T0L_N1_DBC_45
-# set_property PACKAGE_PIN Y32 [get_ports "FMCP_HSPC_LA23_P"] ;# Bank 45 VCCO - VADJ_1V8_FPGA - IO_L1P_T0L_N0_DBC_45
-# set_property IOSTANDARD LVDS [get_ports "FMCP_HSPC_LA23_P"] ;# Bank 45 VCCO - VADJ_1V8_FPGA - IO_L1P_T0L_N0_DBC_45
-# #Other net PACKAGE_PIN U30 - VREF_45 Bank 45 - VREF_45
-# set_property PACKAGE_PIN AK13 [get_ports "FMC_HPC1_LA33_N"] ;# Bank 67 VCCO - VADJ_1V8_FPGA - IO_L24N_T3U_N11_67
-# set_property IOSTANDARD LVDS [get_ports "FMC_HPC1_LA33_N"] ;# Bank 67 VCCO - VADJ_1V8_FPGA - IO_L24N_T3U_N11_67
-# set_property PACKAGE_PIN AK14 [get_ports "FMC_HPC1_LA33_P"] ;# Bank 67 VCCO - VADJ_1V8_FPGA - IO_L24P_T3U_N10_67
-# set_property IOSTANDARD LVDS [get_ports "FMC_HPC1_LA33_P"] ;# Bank 67 VCCO - VADJ_1V8_FPGA - IO_L24P_T3U_N10_67
-# set_property PACKAGE_PIN AM12 [get_ports "FMC_HPC1_LA31_N"] ;# Bank 67 VCCO - VADJ_1V8_FPGA - IO_L23N_T3U_N9_67
-# set_property IOSTANDARD LVDS [get_ports "FMC_HPC1_LA31_N"] ;# Bank 67 VCCO - VADJ_1V8_FPGA - IO_L23N_T3U_N9_67
-# set_property PACKAGE_PIN AM13 [get_ports "FMC_HPC1_LA31_P"] ;# Bank 67 VCCO - VADJ_1V8_FPGA - IO_L23P_T3U_N8_67
-# set_property IOSTANDARD LVDS [get_ports "FMC_HPC1_LA31_P"] ;# Bank 67 VCCO - VADJ_1V8_FPGA - IO_L23P_T3U_N8_67
-# set_property PACKAGE_PIN AJ12 [get_ports "FMC_HPC1_LA32_N"] ;# Bank 67 VCCO - VADJ_1V8_FPGA - IO_L22N_T3U_N7_DBC_AD0N_67
-# set_property IOSTANDARD LVDS [get_ports "FMC_HPC1_LA32_N"] ;# Bank 67 VCCO - VADJ_1V8_FPGA - IO_L22N_T3U_N7_DBC_AD0N_67
-# set_property PACKAGE_PIN AJ13 [get_ports "FMC_HPC1_LA32_P"] ;# Bank 67 VCCO - VADJ_1V8_FPGA - IO_L22P_T3U_N6_DBC_AD0P_67
-# set_property IOSTANDARD LVDS [get_ports "FMC_HPC1_LA32_P"] ;# Bank 67 VCCO - VADJ_1V8_FPGA - IO_L22P_T3U_N6_DBC_AD0P_67
-# set_property PACKAGE_PIN AL12 [get_ports "FMC_HPC1_LA30_N"] ;# Bank 67 VCCO - VADJ_1V8_FPGA - IO_L21N_T3L_N5_AD8N_67
-# set_property IOSTANDARD LVDS [get_ports "FMC_HPC1_LA30_N"] ;# Bank 67 VCCO - VADJ_1V8_FPGA - IO_L21N_T3L_N5_AD8N_67
-# set_property PACKAGE_PIN AK12 [get_ports "FMC_HPC1_LA30_P"] ;# Bank 67 VCCO - VADJ_1V8_FPGA - IO_L21P_T3L_N4_AD8P_67
-# set_property IOSTANDARD LVDS [get_ports "FMC_HPC1_LA30_P"] ;# Bank 67 VCCO - VADJ_1V8_FPGA - IO_L21P_T3L_N4_AD8P_67
-# set_property PACKAGE_PIN AL15 [get_ports "FMC_HPC1_LA26_N"] ;# Bank 67 VCCO - VADJ_1V8_FPGA - IO_L20N_T3L_N3_AD1N_67
-# set_property IOSTANDARD LVDS [get_ports "FMC_HPC1_LA26_N"] ;# Bank 67 VCCO - VADJ_1V8_FPGA - IO_L20N_T3L_N3_AD1N_67
-# set_property PACKAGE_PIN AK15 [get_ports "FMC_HPC1_LA26_P"] ;# Bank 67 VCCO - VADJ_1V8_FPGA - IO_L20P_T3L_N2_AD1P_67
-# set_property IOSTANDARD LVDS [get_ports "FMC_HPC1_LA26_P"] ;# Bank 67 VCCO - VADJ_1V8_FPGA - IO_L20P_T3L_N2_AD1P_67
-# set_property PACKAGE_PIN AM14 [get_ports "FMC_HPC1_LA27_N"] ;# Bank 67 VCCO - VADJ_1V8_FPGA - IO_L19N_T3L_N1_DBC_AD9N_67
-# set_property IOSTANDARD LVDS [get_ports "FMC_HPC1_LA27_N"] ;# Bank 67 VCCO - VADJ_1V8_FPGA - IO_L19N_T3L_N1_DBC_AD9N_67
-# set_property PACKAGE_PIN AL14 [get_ports "FMC_HPC1_LA27_P"] ;# Bank 67 VCCO - VADJ_1V8_FPGA - IO_L19P_T3L_N0_DBC_AD9P_67
-# set_property IOSTANDARD LVDS [get_ports "FMC_HPC1_LA27_P"] ;# Bank 67 VCCO - VADJ_1V8_FPGA - IO_L19P_T3L_N0_DBC_AD9P_67
-# #set_property PACKAGE_PIN AM16 [get_ports ""] ;# Bank 67 VCCO - VADJ_1V8_FPGA - IO_T3U_N12_67
-# #set_property IOSTANDARD LVCMOSxx [get_ports ""] ;# Bank 67 VCCO - VADJ_1V8_FPGA - IO_T3U_N12_67
-# #set_property PACKAGE_PIN AR15 [get_ports ""] ;# Bank 67 VCCO - VADJ_1V8_FPGA - IO_T2U_N12_67
-# #set_property IOSTANDARD LVCMOSxx [get_ports ""] ;# Bank 67 VCCO - VADJ_1V8_FPGA - IO_T2U_N12_67
-# set_property PACKAGE_PIN AP15 [get_ports "FMC_HPC1_LA29_N"] ;# Bank 67 VCCO - VADJ_1V8_FPGA - IO_L18N_T2U_N11_AD2N_67
-# set_property IOSTANDARD LVDS [get_ports "FMC_HPC1_LA29_N"] ;# Bank 67 VCCO - VADJ_1V8_FPGA - IO_L18N_T2U_N11_AD2N_67
-# set_property PACKAGE_PIN AN15 [get_ports "FMC_HPC1_LA29_P"] ;# Bank 67 VCCO - VADJ_1V8_FPGA - IO_L18P_T2U_N10_AD2P_67
-# set_property IOSTANDARD LVDS [get_ports "FMC_HPC1_LA29_P"] ;# Bank 67 VCCO - VADJ_1V8_FPGA - IO_L18P_T2U_N10_AD2P_67
-# set_property PACKAGE_PIN AP16 [get_ports "FMC_HPC1_LA23_N"] ;# Bank 67 VCCO - VADJ_1V8_FPGA - IO_L17N_T2U_N9_AD10N_67
-# set_property IOSTANDARD LVDS [get_ports "FMC_HPC1_LA23_N"] ;# Bank 67 VCCO - VADJ_1V8_FPGA - IO_L17N_T2U_N9_AD10N_67
-# set_property PACKAGE_PIN AN16 [get_ports "FMC_HPC1_LA23_P"] ;# Bank 67 VCCO - VADJ_1V8_FPGA - IO_L17P_T2U_N8_AD10P_67
-# set_property IOSTANDARD LVDS [get_ports "FMC_HPC1_LA23_P"] ;# Bank 67 VCCO - VADJ_1V8_FPGA - IO_L17P_T2U_N8_AD10P_67
-# set_property PACKAGE_PIN AR12 [get_ports "FMC_HPC1_LA18_CC_N"] ;# Bank 67 VCCO - VADJ_1V8_FPGA - IO_L16N_T2U_N7_QBC_AD3N_67
-# set_property IOSTANDARD LVDS [get_ports "FMC_HPC1_LA18_CC_N"] ;# Bank 67 VCCO - VADJ_1V8_FPGA - IO_L16N_T2U_N7_QBC_AD3N_67
-# set_property PACKAGE_PIN AP12 [get_ports "FMC_HPC1_LA18_CC_P"] ;# Bank 67 VCCO - VADJ_1V8_FPGA - IO_L16P_T2U_N6_QBC_AD3P_67
-# set_property IOSTANDARD LVDS [get_ports "FMC_HPC1_LA18_CC_P"] ;# Bank 67 VCCO - VADJ_1V8_FPGA - IO_L16P_T2U_N6_QBC_AD3P_67
-# #set_property PACKAGE_PIN AN13 [get_ports ""] ;# Bank 67 VCCO - VADJ_1V8_FPGA - IO_L15N_T2L_N5_AD11N_67
-# #set_property IOSTANDARD LVCMOSxx [get_ports ""] ;# Bank 67 VCCO - VADJ_1V8_FPGA - IO_L15N_T2L_N5_AD11N_67
-# #set_property PACKAGE_PIN AN14 [get_ports ""] ;# Bank 67 VCCO - VADJ_1V8_FPGA - IO_L15P_T2L_N4_AD11P_67
-# #set_property IOSTANDARD LVCMOSxx [get_ports ""] ;# Bank 67 VCCO - VADJ_1V8_FPGA - IO_L15P_T2L_N4_AD11P_67
-# set_property PACKAGE_PIN AR13 [get_ports "FMC_HPC1_LA24_N"] ;# Bank 67 VCCO - VADJ_1V8_FPGA - IO_L14N_T2L_N3_GC_67
-# set_property IOSTANDARD LVDS [get_ports "FMC_HPC1_LA24_N"] ;# Bank 67 VCCO - VADJ_1V8_FPGA - IO_L14N_T2L_N3_GC_67
-# set_property PACKAGE_PIN AP13 [get_ports "FMC_HPC1_LA24_P"] ;# Bank 67 VCCO - VADJ_1V8_FPGA - IO_L14P_T2L_N2_GC_67
-# set_property IOSTANDARD LVDS [get_ports "FMC_HPC1_LA24_P"] ;# Bank 67 VCCO - VADJ_1V8_FPGA - IO_L14P_T2L_N2_GC_67
-# set_property PACKAGE_PIN AT14 [get_ports "FMC_HPC1_LA17_CC_N"] ;# Bank 67 VCCO - VADJ_1V8_FPGA - IO_L13N_T2L_N1_GC_QBC_67
-# set_property IOSTANDARD LVDS [get_ports "FMC_HPC1_LA17_CC_N"] ;# Bank 67 VCCO - VADJ_1V8_FPGA - IO_L13N_T2L_N1_GC_QBC_67
-# set_property PACKAGE_PIN AR14 [get_ports "FMC_HPC1_LA17_CC_P"] ;# Bank 67 VCCO - VADJ_1V8_FPGA - IO_L13P_T2L_N0_GC_QBC_67
-# set_property IOSTANDARD LVDS [get_ports "FMC_HPC1_LA17_CC_P"] ;# Bank 67 VCCO - VADJ_1V8_FPGA - IO_L13P_T2L_N0_GC_QBC_67
-# set_property PACKAGE_PIN AV13 [get_ports "FMC_HPC1_CLK1_M2C_N"] ;# Bank 67 VCCO - VADJ_1V8_FPGA - IO_L12N_T1U_N11_GC_67
-# set_property IOSTANDARD LVDS [get_ports "FMC_HPC1_CLK1_M2C_N"] ;# Bank 67 VCCO - VADJ_1V8_FPGA - IO_L12N_T1U_N11_GC_67
-# set_property PACKAGE_PIN AV14 [get_ports "FMC_HPC1_CLK1_M2C_P"] ;# Bank 67 VCCO - VADJ_1V8_FPGA - IO_L12P_T1U_N10_GC_67
-# set_property IOSTANDARD LVDS [get_ports "FMC_HPC1_CLK1_M2C_P"] ;# Bank 67 VCCO - VADJ_1V8_FPGA - IO_L12P_T1U_N10_GC_67
-# #set_property PACKAGE_PIN AU13 [get_ports ""] ;# Bank 67 VCCO - VADJ_1V8_FPGA - IO_L11N_T1U_N9_GC_67
-# #set_property IOSTANDARD LVCMOSxx [get_ports ""] ;# Bank 67 VCCO - VADJ_1V8_FPGA - IO_L11N_T1U_N9_GC_67
-# #set_property PACKAGE_PIN AU14 [get_ports ""] ;# Bank 67 VCCO - VADJ_1V8_FPGA - IO_L11P_T1U_N8_GC_67
-# #set_property IOSTANDARD LVCMOSxx [get_ports ""] ;# Bank 67 VCCO - VADJ_1V8_FPGA - IO_L11P_T1U_N8_GC_67
-# set_property PACKAGE_PIN AY14 [get_ports "PMOD0_0_LS"] ;# Bank 67 VCCO - VADJ_1V8_FPGA - IO_L10N_T1U_N7_QBC_AD4N_67
-# set_property IOSTANDARD LVCMOS18 [get_ports "PMOD0_0_LS"] ;# Bank 67 VCCO - VADJ_1V8_FPGA - IO_L10N_T1U_N7_QBC_AD4N_67
-# set_property PACKAGE_PIN AY15 [get_ports "PMOD0_1_LS"] ;# Bank 67 VCCO - VADJ_1V8_FPGA - IO_L10P_T1U_N6_QBC_AD4P_67
-# set_property IOSTANDARD LVCMOS18 [get_ports "PMOD0_1_LS"] ;# Bank 67 VCCO - VADJ_1V8_FPGA - IO_L10P_T1U_N6_QBC_AD4P_67
-# set_property PACKAGE_PIN AW15 [get_ports "PMOD0_2_LS"] ;# Bank 67 VCCO - VADJ_1V8_FPGA - IO_L9N_T1L_N5_AD12N_67
-# set_property IOSTANDARD LVCMOS18 [get_ports "PMOD0_2_LS"] ;# Bank 67 VCCO - VADJ_1V8_FPGA - IO_L9N_T1L_N5_AD12N_67
-# set_property PACKAGE_PIN AV15 [get_ports "PMOD0_3_LS"] ;# Bank 67 VCCO - VADJ_1V8_FPGA - IO_L9P_T1L_N4_AD12P_67
-# set_property IOSTANDARD LVCMOS18 [get_ports "PMOD0_3_LS"] ;# Bank 67 VCCO - VADJ_1V8_FPGA - IO_L9P_T1L_N4_AD12P_67
-# set_property PACKAGE_PIN AV16 [get_ports "PMOD0_4_LS"] ;# Bank 67 VCCO - VADJ_1V8_FPGA - IO_L8N_T1L_N3_AD5N_67
-# set_property IOSTANDARD LVCMOS18 [get_ports "PMOD0_4_LS"] ;# Bank 67 VCCO - VADJ_1V8_FPGA - IO_L8N_T1L_N3_AD5N_67
-# set_property PACKAGE_PIN AU16 [get_ports "PMOD0_5_LS"] ;# Bank 67 VCCO - VADJ_1V8_FPGA - IO_L8P_T1L_N2_AD5P_67
-# set_property IOSTANDARD LVCMOS18 [get_ports "PMOD0_5_LS"] ;# Bank 67 VCCO - VADJ_1V8_FPGA - IO_L8P_T1L_N2_AD5P_67
-# set_property PACKAGE_PIN AT15 [get_ports "PMOD0_6_LS"] ;# Bank 67 VCCO - VADJ_1V8_FPGA - IO_L7N_T1L_N1_QBC_AD13N_67
-# set_property IOSTANDARD LVCMOS18 [get_ports "PMOD0_6_LS"] ;# Bank 67 VCCO - VADJ_1V8_FPGA - IO_L7N_T1L_N1_QBC_AD13N_67
-# set_property PACKAGE_PIN AT16 [get_ports "PMOD0_7_LS"] ;# Bank 67 VCCO - VADJ_1V8_FPGA - IO_L7P_T1L_N0_QBC_AD13P_67
-# set_property IOSTANDARD LVCMOS18 [get_ports "PMOD0_7_LS"] ;# Bank 67 VCCO - VADJ_1V8_FPGA - IO_L7P_T1L_N0_QBC_AD13P_67
-# set_property PACKAGE_PIN AW16 [get_ports "10N8842"] ;# Bank 67 VCCO - VADJ_1V8_FPGA - IO_T1U_N12_67
-# set_property IOSTANDARD LVCMOSxx [get_ports "10N8842"] ;# Bank 67 VCCO - VADJ_1V8_FPGA - IO_T1U_N12_67
-# #set_property PACKAGE_PIN BA12 [get_ports "VRP_67"] ;# Bank 67 VCCO - VADJ_1V8_FPGA - IO_T0U_N12_VRP_67
-# #set_property IOSTANDARD LVCMOSxx [get_ports "VRP_67"] ;# Bank 67 VCCO - VADJ_1V8_FPGA - IO_T0U_N12_VRP_67
-# set_property PACKAGE_PIN AV11 [get_ports "FMC_HPC1_LA21_N"] ;# Bank 67 VCCO - VADJ_1V8_FPGA - IO_L6N_T0U_N11_AD6N_67
-# set_property IOSTANDARD LVDS [get_ports "FMC_HPC1_LA21_N"] ;# Bank 67 VCCO - VADJ_1V8_FPGA - IO_L6N_T0U_N11_AD6N_67
-# set_property PACKAGE_PIN AU11 [get_ports "FMC_HPC1_LA21_P"] ;# Bank 67 VCCO - VADJ_1V8_FPGA - IO_L6P_T0U_N10_AD6P_67
-# set_property IOSTANDARD LVDS [get_ports "FMC_HPC1_LA21_P"] ;# Bank 67 VCCO - VADJ_1V8_FPGA - IO_L6P_T0U_N10_AD6P_67
-# set_property PACKAGE_PIN AY13 [get_ports "FMC_HPC1_LA22_N"] ;# Bank 67 VCCO - VADJ_1V8_FPGA - IO_L5N_T0U_N9_AD14N_67
-# set_property IOSTANDARD LVDS [get_ports "FMC_HPC1_LA22_N"] ;# Bank 67 VCCO - VADJ_1V8_FPGA - IO_L5N_T0U_N9_AD14N_67
-# set_property PACKAGE_PIN AW13 [get_ports "FMC_HPC1_LA22_P"] ;# Bank 67 VCCO - VADJ_1V8_FPGA - IO_L5P_T0U_N8_AD14P_67
-# set_property IOSTANDARD LVDS [get_ports "FMC_HPC1_LA22_P"] ;# Bank 67 VCCO - VADJ_1V8_FPGA - IO_L5P_T0U_N8_AD14P_67
-# set_property PACKAGE_PIN AW10 [get_ports "FMC_HPC1_LA28_N"] ;# Bank 67 VCCO - VADJ_1V8_FPGA - IO_L4N_T0U_N7_DBC_AD7N_67
-# set_property IOSTANDARD LVDS [get_ports "FMC_HPC1_LA28_N"] ;# Bank 67 VCCO - VADJ_1V8_FPGA - IO_L4N_T0U_N7_DBC_AD7N_67
-# set_property PACKAGE_PIN AV10 [get_ports "FMC_HPC1_LA28_P"] ;# Bank 67 VCCO - VADJ_1V8_FPGA - IO_L4P_T0U_N6_DBC_AD7P_67
-# set_property IOSTANDARD LVDS [get_ports "FMC_HPC1_LA28_P"] ;# Bank 67 VCCO - VADJ_1V8_FPGA - IO_L4P_T0U_N6_DBC_AD7P_67
-# set_property PACKAGE_PIN AY10 [get_ports "FMC_HPC1_LA20_N"] ;# Bank 67 VCCO - VADJ_1V8_FPGA - IO_L3N_T0L_N5_AD15N_67
-# set_property IOSTANDARD LVDS [get_ports "FMC_HPC1_LA20_N"] ;# Bank 67 VCCO - VADJ_1V8_FPGA - IO_L3N_T0L_N5_AD15N_67
-# set_property PACKAGE_PIN AW11 [get_ports "FMC_HPC1_LA20_P"] ;# Bank 67 VCCO - VADJ_1V8_FPGA - IO_L3P_T0L_N4_AD15P_67
-# set_property IOSTANDARD LVDS [get_ports "FMC_HPC1_LA20_P"] ;# Bank 67 VCCO - VADJ_1V8_FPGA - IO_L3P_T0L_N4_AD15P_67
-# set_property PACKAGE_PIN AY12 [get_ports "FMC_HPC1_LA19_N"] ;# Bank 67 VCCO - VADJ_1V8_FPGA - IO_L2N_T0L_N3_67
-# set_property IOSTANDARD LVDS [get_ports "FMC_HPC1_LA19_N"] ;# Bank 67 VCCO - VADJ_1V8_FPGA - IO_L2N_T0L_N3_67
-# set_property PACKAGE_PIN AW12 [get_ports "FMC_HPC1_LA19_P"] ;# Bank 67 VCCO - VADJ_1V8_FPGA - IO_L2P_T0L_N2_67
-# set_property IOSTANDARD LVDS [get_ports "FMC_HPC1_LA19_P"] ;# Bank 67 VCCO - VADJ_1V8_FPGA - IO_L2P_T0L_N2_67
-# set_property PACKAGE_PIN AU12 [get_ports "FMC_HPC1_LA25_N"] ;# Bank 67 VCCO - VADJ_1V8_FPGA - IO_L1N_T0L_N1_DBC_67
-# set_property IOSTANDARD LVDS [get_ports "FMC_HPC1_LA25_N"] ;# Bank 67 VCCO - VADJ_1V8_FPGA - IO_L1N_T0L_N1_DBC_67
-# set_property PACKAGE_PIN AT12 [get_ports "FMC_HPC1_LA25_P"] ;# Bank 67 VCCO - VADJ_1V8_FPGA - IO_L1P_T0L_N0_DBC_67
-# set_property IOSTANDARD LVDS [get_ports "FMC_HPC1_LA25_P"] ;# Bank 67 VCCO - VADJ_1V8_FPGA - IO_L1P_T0L_N0_DBC_67
-# #Other net PACKAGE_PIN AL16 - VREF_67 Bank 67 - VREF_67
-# set_property PACKAGE_PIN BB12 [get_ports "FMC_HPC1_LA10_N"] ;# Bank 66 VCCO - VADJ_1V8_FPGA - IO_L24N_T3U_N11_66
-# set_property IOSTANDARD LVDS [get_ports "FMC_HPC1_LA10_N"] ;# Bank 66 VCCO - VADJ_1V8_FPGA - IO_L24N_T3U_N11_66
-# set_property PACKAGE_PIN BB13 [get_ports "FMC_HPC1_LA10_P"] ;# Bank 66 VCCO - VADJ_1V8_FPGA - IO_L24P_T3U_N10_66
-# set_property IOSTANDARD LVDS [get_ports "FMC_HPC1_LA10_P"] ;# Bank 66 VCCO - VADJ_1V8_FPGA - IO_L24P_T3U_N10_66
-# set_property PACKAGE_PIN BB14 [get_ports "FMC_HPC1_LA09_N"] ;# Bank 66 VCCO - VADJ_1V8_FPGA - IO_L23N_T3U_N9_66
-# set_property IOSTANDARD LVDS [get_ports "FMC_HPC1_LA09_N"] ;# Bank 66 VCCO - VADJ_1V8_FPGA - IO_L23N_T3U_N9_66
-# set_property PACKAGE_PIN BA14 [get_ports "FMC_HPC1_LA09_P"] ;# Bank 66 VCCO - VADJ_1V8_FPGA - IO_L23P_T3U_N8_66
-# set_property IOSTANDARD LVDS [get_ports "FMC_HPC1_LA09_P"] ;# Bank 66 VCCO - VADJ_1V8_FPGA - IO_L23P_T3U_N8_66
-# set_property PACKAGE_PIN BA15 [get_ports "FMC_HPC1_LA11_N"] ;# Bank 66 VCCO - VADJ_1V8_FPGA - IO_L22N_T3U_N7_DBC_AD0N_66
-# set_property IOSTANDARD LVDS [get_ports "FMC_HPC1_LA11_N"] ;# Bank 66 VCCO - VADJ_1V8_FPGA - IO_L22N_T3U_N7_DBC_AD0N_66
-# set_property PACKAGE_PIN BA16 [get_ports "FMC_HPC1_LA11_P"] ;# Bank 66 VCCO - VADJ_1V8_FPGA - IO_L22P_T3U_N6_DBC_AD0P_66
-# set_property IOSTANDARD LVDS [get_ports "FMC_HPC1_LA11_P"] ;# Bank 66 VCCO - VADJ_1V8_FPGA - IO_L22P_T3U_N6_DBC_AD0P_66
-# set_property PACKAGE_PIN BD15 [get_ports "FMC_HPC1_LA07_N"] ;# Bank 66 VCCO - VADJ_1V8_FPGA - IO_L21N_T3L_N5_AD8N_66
-# set_property IOSTANDARD LVDS [get_ports "FMC_HPC1_LA07_N"] ;# Bank 66 VCCO - VADJ_1V8_FPGA - IO_L21N_T3L_N5_AD8N_66
-# set_property PACKAGE_PIN BC15 [get_ports "FMC_HPC1_LA07_P"] ;# Bank 66 VCCO - VADJ_1V8_FPGA - IO_L21P_T3L_N4_AD8P_66
-# set_property IOSTANDARD LVDS [get_ports "FMC_HPC1_LA07_P"] ;# Bank 66 VCCO - VADJ_1V8_FPGA - IO_L21P_T3L_N4_AD8P_66
-# set_property PACKAGE_PIN BC16 [get_ports "FMC_HPC1_LA15_N"] ;# Bank 66 VCCO - VADJ_1V8_FPGA - IO_L20N_T3L_N3_AD1N_66
-# set_property IOSTANDARD LVDS [get_ports "FMC_HPC1_LA15_N"] ;# Bank 66 VCCO - VADJ_1V8_FPGA - IO_L20N_T3L_N3_AD1N_66
-# set_property PACKAGE_PIN BB16 [get_ports "FMC_HPC1_LA15_P"] ;# Bank 66 VCCO - VADJ_1V8_FPGA - IO_L20P_T3L_N2_AD1P_66
-# set_property IOSTANDARD LVDS [get_ports "FMC_HPC1_LA15_P"] ;# Bank 66 VCCO - VADJ_1V8_FPGA - IO_L20P_T3L_N2_AD1P_66
-# set_property PACKAGE_PIN BC13 [get_ports "FMC_HPC1_LA12_N"] ;# Bank 66 VCCO - VADJ_1V8_FPGA - IO_L19N_T3L_N1_DBC_AD9N_66
-# set_property IOSTANDARD LVDS [get_ports "FMC_HPC1_LA12_N"] ;# Bank 66 VCCO - VADJ_1V8_FPGA - IO_L19N_T3L_N1_DBC_AD9N_66
-# set_property PACKAGE_PIN BC14 [get_ports "FMC_HPC1_LA12_P"] ;# Bank 66 VCCO - VADJ_1V8_FPGA - IO_L19P_T3L_N0_DBC_AD9P_66
-# set_property IOSTANDARD LVDS [get_ports "FMC_HPC1_LA12_P"] ;# Bank 66 VCCO - VADJ_1V8_FPGA - IO_L19P_T3L_N0_DBC_AD9P_66
-# set_property PACKAGE_PIN BB11 [get_ports "10N8224"] ;# Bank 66 VCCO - VADJ_1V8_FPGA - IO_T3U_N12_66
-# set_property IOSTANDARD LVCMOSxx [get_ports "10N8224"] ;# Bank 66 VCCO - VADJ_1V8_FPGA - IO_T3U_N12_66
-# set_property PACKAGE_PIN BA10 [get_ports "10N9644"] ;# Bank 66 VCCO - VADJ_1V8_FPGA - IO_T2U_N12_66
-# set_property IOSTANDARD LVCMOSxx [get_ports "10N9644"] ;# Bank 66 VCCO - VADJ_1V8_FPGA - IO_T2U_N12_66
-# set_property PACKAGE_PIN AW7 [get_ports "FMC_HPC1_LA14_N"] ;# Bank 66 VCCO - VADJ_1V8_FPGA - IO_L18N_T2U_N11_AD2N_66
-# set_property IOSTANDARD LVDS [get_ports "FMC_HPC1_LA14_N"] ;# Bank 66 VCCO - VADJ_1V8_FPGA - IO_L18N_T2U_N11_AD2N_66
-# set_property PACKAGE_PIN AW8 [get_ports "FMC_HPC1_LA14_P"] ;# Bank 66 VCCO - VADJ_1V8_FPGA - IO_L18P_T2U_N10_AD2P_66
-# set_property IOSTANDARD LVDS [get_ports "FMC_HPC1_LA14_P"] ;# Bank 66 VCCO - VADJ_1V8_FPGA - IO_L18P_T2U_N10_AD2P_66
-# set_property PACKAGE_PIN AY7 [get_ports "FMC_HPC1_LA13_N"] ;# Bank 66 VCCO - VADJ_1V8_FPGA - IO_L17N_T2U_N9_AD10N_66
-# set_property IOSTANDARD LVDS [get_ports "FMC_HPC1_LA13_N"] ;# Bank 66 VCCO - VADJ_1V8_FPGA - IO_L17N_T2U_N9_AD10N_66
-# set_property PACKAGE_PIN AY8 [get_ports "FMC_HPC1_LA13_P"] ;# Bank 66 VCCO - VADJ_1V8_FPGA - IO_L17P_T2U_N8_AD10P_66
-# set_property IOSTANDARD LVDS [get_ports "FMC_HPC1_LA13_P"] ;# Bank 66 VCCO - VADJ_1V8_FPGA - IO_L17P_T2U_N8_AD10P_66
-# set_property PACKAGE_PIN AV8 [get_ports "FMC_HPC1_LA16_N"] ;# Bank 66 VCCO - VADJ_1V8_FPGA - IO_L16N_T2U_N7_QBC_AD3N_66
-# set_property IOSTANDARD LVDS [get_ports "FMC_HPC1_LA16_N"] ;# Bank 66 VCCO - VADJ_1V8_FPGA - IO_L16N_T2U_N7_QBC_AD3N_66
-# set_property PACKAGE_PIN AV9 [get_ports "FMC_HPC1_LA16_P"] ;# Bank 66 VCCO - VADJ_1V8_FPGA - IO_L16P_T2U_N6_QBC_AD3P_66
-# set_property IOSTANDARD LVDS [get_ports "FMC_HPC1_LA16_P"] ;# Bank 66 VCCO - VADJ_1V8_FPGA - IO_L16P_T2U_N6_QBC_AD3P_66
-# set_property PACKAGE_PIN BB7 [get_ports "FMC_HPC1_PRSNT_M2C_B_LS"] ;# Bank 66 VCCO - VADJ_1V8_FPGA - IO_L15N_T2L_N5_AD11N_66
-# set_property IOSTANDARD LVCMOS18 [get_ports "FMC_HPC1_PRSNT_M2C_B_LS"] ;# Bank 66 VCCO - VADJ_1V8_FPGA - IO_L15N_T2L_N5_AD11N_66
-# set_property PACKAGE_PIN BA7 [get_ports "FMC_HPC1_PG_M2C_LS"] ;# Bank 66 VCCO - VADJ_1V8_FPGA - IO_L15P_T2L_N4_AD11P_66
-# set_property IOSTANDARD LVCMOS18 [get_ports "FMC_HPC1_PG_M2C_LS"] ;# Bank 66 VCCO - VADJ_1V8_FPGA - IO_L15P_T2L_N4_AD11P_66
-# #set_property PACKAGE_PIN BB8 [get_ports ""] ;# Bank 66 VCCO - VADJ_1V8_FPGA - IO_L14N_T2L_N3_GC_66
-# #set_property IOSTANDARD LVCMOSxx [get_ports ""] ;# Bank 66 VCCO - VADJ_1V8_FPGA - IO_L14N_T2L_N3_GC_66
-# #set_property PACKAGE_PIN BB9 [get_ports ""] ;# Bank 66 VCCO - VADJ_1V8_FPGA - IO_L14P_T2L_N2_GC_66
-# #set_property IOSTANDARD LVCMOSxx [get_ports ""] ;# Bank 66 VCCO - VADJ_1V8_FPGA - IO_L14P_T2L_N2_GC_66
-# set_property PACKAGE_PIN BA9 [get_ports "FMC_HPC1_LA00_CC_N"] ;# Bank 66 VCCO - VADJ_1V8_FPGA - IO_L13N_T2L_N1_GC_QBC_66
-# set_property IOSTANDARD LVDS [get_ports "FMC_HPC1_LA00_CC_N"] ;# Bank 66 VCCO - VADJ_1V8_FPGA - IO_L13N_T2L_N1_GC_QBC_66
-# set_property PACKAGE_PIN AY9 [get_ports "FMC_HPC1_LA00_CC_P"] ;# Bank 66 VCCO - VADJ_1V8_FPGA - IO_L13P_T2L_N0_GC_QBC_66
-# set_property IOSTANDARD LVDS [get_ports "FMC_HPC1_LA00_CC_P"] ;# Bank 66 VCCO - VADJ_1V8_FPGA - IO_L13P_T2L_N0_GC_QBC_66
-# set_property PACKAGE_PIN BC8 [get_ports "FMC_HPC1_CLK0_M2C_N"] ;# Bank 66 VCCO - VADJ_1V8_FPGA - IO_L12N_T1U_N11_GC_66
-# set_property IOSTANDARD LVDS [get_ports "FMC_HPC1_CLK0_M2C_N"] ;# Bank 66 VCCO - VADJ_1V8_FPGA - IO_L12N_T1U_N11_GC_66
-# set_property PACKAGE_PIN BC9 [get_ports "FMC_HPC1_CLK0_M2C_P"] ;# Bank 66 VCCO - VADJ_1V8_FPGA - IO_L12P_T1U_N10_GC_66
-# set_property IOSTANDARD LVDS [get_ports "FMC_HPC1_CLK0_M2C_P"] ;# Bank 66 VCCO - VADJ_1V8_FPGA - IO_L12P_T1U_N10_GC_66
-# #set_property PACKAGE_PIN BD10 [get_ports ""] ;# Bank 66 VCCO - VADJ_1V8_FPGA - IO_L11N_T1U_N9_GC_66
-# #set_property IOSTANDARD LVCMOSxx [get_ports ""] ;# Bank 66 VCCO - VADJ_1V8_FPGA - IO_L11N_T1U_N9_GC_66
-# #set_property PACKAGE_PIN BC10 [get_ports ""] ;# Bank 66 VCCO - VADJ_1V8_FPGA - IO_L11P_T1U_N8_GC_66
-# #set_property IOSTANDARD LVCMOSxx [get_ports ""] ;# Bank 66 VCCO - VADJ_1V8_FPGA - IO_L11P_T1U_N8_GC_66
-# set_property PACKAGE_PIN BF9 [get_ports "FMC_HPC1_LA01_CC_N"] ;# Bank 66 VCCO - VADJ_1V8_FPGA - IO_L10N_T1U_N7_QBC_AD4N_66
-# set_property IOSTANDARD LVDS [get_ports "FMC_HPC1_LA01_CC_N"] ;# Bank 66 VCCO - VADJ_1V8_FPGA - IO_L10N_T1U_N7_QBC_AD4N_66
-# set_property PACKAGE_PIN BF10 [get_ports "FMC_HPC1_LA01_CC_P"] ;# Bank 66 VCCO - VADJ_1V8_FPGA - IO_L10P_T1U_N6_QBC_AD4P_66
-# set_property IOSTANDARD LVDS [get_ports "FMC_HPC1_LA01_CC_P"] ;# Bank 66 VCCO - VADJ_1V8_FPGA - IO_L10P_T1U_N6_QBC_AD4P_66
-# #set_property PACKAGE_PIN BE9 [get_ports ""] ;# Bank 66 VCCO - VADJ_1V8_FPGA - IO_L9N_T1L_N5_AD12N_66
-# #set_property IOSTANDARD LVCMOSxx [get_ports ""] ;# Bank 66 VCCO - VADJ_1V8_FPGA - IO_L9N_T1L_N5_AD12N_66
-# #set_property PACKAGE_PIN BE10 [get_ports ""] ;# Bank 66 VCCO - VADJ_1V8_FPGA - IO_L9P_T1L_N4_AD12P_66
-# #set_property IOSTANDARD LVCMOSxx [get_ports ""] ;# Bank 66 VCCO - VADJ_1V8_FPGA - IO_L9P_T1L_N4_AD12P_66
-# #set_property PACKAGE_PIN BE7 [get_ports ""] ;# Bank 66 VCCO - VADJ_1V8_FPGA - IO_L8N_T1L_N3_AD5N_66
-# #set_property IOSTANDARD LVCMOSxx [get_ports ""] ;# Bank 66 VCCO - VADJ_1V8_FPGA - IO_L8N_T1L_N3_AD5N_66
-# #set_property PACKAGE_PIN BE8 [get_ports ""] ;# Bank 66 VCCO - VADJ_1V8_FPGA - IO_L8P_T1L_N2_AD5P_66
-# #set_property IOSTANDARD LVCMOSxx [get_ports ""] ;# Bank 66 VCCO - VADJ_1V8_FPGA - IO_L8P_T1L_N2_AD5P_66
-# #set_property PACKAGE_PIN BD7 [get_ports ""] ;# Bank 66 VCCO - VADJ_1V8_FPGA - IO_L7N_T1L_N1_QBC_AD13N_66
-# #set_property IOSTANDARD LVCMOSxx [get_ports ""] ;# Bank 66 VCCO - VADJ_1V8_FPGA - IO_L7N_T1L_N1_QBC_AD13N_66
-# #set_property PACKAGE_PIN BD8 [get_ports ""] ;# Bank 66 VCCO - VADJ_1V8_FPGA - IO_L7P_T1L_N0_QBC_AD13P_66
-# #set_property IOSTANDARD LVCMOSxx [get_ports ""] ;# Bank 66 VCCO - VADJ_1V8_FPGA - IO_L7P_T1L_N0_QBC_AD13P_66
-# #set_property PACKAGE_PIN BF7 [get_ports ""] ;# Bank 66 VCCO - VADJ_1V8_FPGA - IO_T1U_N12_66
-# #set_property IOSTANDARD LVCMOSxx [get_ports ""] ;# Bank 66 VCCO - VADJ_1V8_FPGA - IO_T1U_N12_66
-# #set_property PACKAGE_PIN BD16 [get_ports "VRP_66"] ;# Bank 66 VCCO - VADJ_1V8_FPGA - IO_T0U_N12_VRP_66
-# #set_property IOSTANDARD LVCMOSxx [get_ports "VRP_66"] ;# Bank 66 VCCO - VADJ_1V8_FPGA - IO_T0U_N12_VRP_66
-# set_property PACKAGE_PIN BF15 [get_ports "FMC_HPC1_LA08_N"] ;# Bank 66 VCCO - VADJ_1V8_FPGA - IO_L6N_T0U_N11_AD6N_66
-# set_property IOSTANDARD LVDS [get_ports "FMC_HPC1_LA08_N"] ;# Bank 66 VCCO - VADJ_1V8_FPGA - IO_L6N_T0U_N11_AD6N_66
-# set_property PACKAGE_PIN BE15 [get_ports "FMC_HPC1_LA08_P"] ;# Bank 66 VCCO - VADJ_1V8_FPGA - IO_L6P_T0U_N10_AD6P_66
-# set_property IOSTANDARD LVDS [get_ports "FMC_HPC1_LA08_P"] ;# Bank 66 VCCO - VADJ_1V8_FPGA - IO_L6P_T0U_N10_AD6P_66
-# set_property PACKAGE_PIN BF14 [get_ports "FMC_HPC1_LA05_N"] ;# Bank 66 VCCO - VADJ_1V8_FPGA - IO_L5N_T0U_N9_AD14N_66
-# set_property IOSTANDARD LVDS [get_ports "FMC_HPC1_LA05_N"] ;# Bank 66 VCCO - VADJ_1V8_FPGA - IO_L5N_T0U_N9_AD14N_66
-# set_property PACKAGE_PIN BE14 [get_ports "FMC_HPC1_LA05_P"] ;# Bank 66 VCCO - VADJ_1V8_FPGA - IO_L5P_T0U_N8_AD14P_66
-# set_property IOSTANDARD LVDS [get_ports "FMC_HPC1_LA05_P"] ;# Bank 66 VCCO - VADJ_1V8_FPGA - IO_L5P_T0U_N8_AD14P_66
-# set_property PACKAGE_PIN BE13 [get_ports "FMC_HPC1_LA06_N"] ;# Bank 66 VCCO - VADJ_1V8_FPGA - IO_L4N_T0U_N7_DBC_AD7N_66
-# set_property IOSTANDARD LVDS [get_ports "FMC_HPC1_LA06_N"] ;# Bank 66 VCCO - VADJ_1V8_FPGA - IO_L4N_T0U_N7_DBC_AD7N_66
-# set_property PACKAGE_PIN BD13 [get_ports "FMC_HPC1_LA06_P"] ;# Bank 66 VCCO - VADJ_1V8_FPGA - IO_L4P_T0U_N6_DBC_AD7P_66
-# set_property IOSTANDARD LVDS [get_ports "FMC_HPC1_LA06_P"] ;# Bank 66 VCCO - VADJ_1V8_FPGA - IO_L4P_T0U_N6_DBC_AD7P_66
-# set_property PACKAGE_PIN BD11 [get_ports "FMC_HPC1_LA02_N"] ;# Bank 66 VCCO - VADJ_1V8_FPGA - IO_L3N_T0L_N5_AD15N_66
-# set_property IOSTANDARD LVDS [get_ports "FMC_HPC1_LA02_N"] ;# Bank 66 VCCO - VADJ_1V8_FPGA - IO_L3N_T0L_N5_AD15N_66
-# set_property PACKAGE_PIN BC11 [get_ports "FMC_HPC1_LA02_P"] ;# Bank 66 VCCO - VADJ_1V8_FPGA - IO_L3P_T0L_N4_AD15P_66
-# set_property IOSTANDARD LVDS [get_ports "FMC_HPC1_LA02_P"] ;# Bank 66 VCCO - VADJ_1V8_FPGA - IO_L3P_T0L_N4_AD15P_66
-# set_property PACKAGE_PIN BF11 [get_ports "FMC_HPC1_LA04_N"] ;# Bank 66 VCCO - VADJ_1V8_FPGA - IO_L2N_T0L_N3_66
-# set_property IOSTANDARD LVDS [get_ports "FMC_HPC1_LA04_N"] ;# Bank 66 VCCO - VADJ_1V8_FPGA - IO_L2N_T0L_N3_66
-# set_property PACKAGE_PIN BF12 [get_ports "FMC_HPC1_LA04_P"] ;# Bank 66 VCCO - VADJ_1V8_FPGA - IO_L2P_T0L_N2_66
-# set_property IOSTANDARD LVDS [get_ports "FMC_HPC1_LA04_P"] ;# Bank 66 VCCO - VADJ_1V8_FPGA - IO_L2P_T0L_N2_66
-# set_property PACKAGE_PIN BE12 [get_ports "FMC_HPC1_LA03_N"] ;# Bank 66 VCCO - VADJ_1V8_FPGA - IO_L1N_T0L_N1_DBC_66
-# set_property IOSTANDARD LVDS [get_ports "FMC_HPC1_LA03_N"] ;# Bank 66 VCCO - VADJ_1V8_FPGA - IO_L1N_T0L_N1_DBC_66
-# set_property PACKAGE_PIN BD12 [get_ports "FMC_HPC1_LA03_P"] ;# Bank 66 VCCO - VADJ_1V8_FPGA - IO_L1P_T0L_N0_DBC_66
-# set_property IOSTANDARD LVDS [get_ports "FMC_HPC1_LA03_P"] ;# Bank 66 VCCO - VADJ_1V8_FPGA - IO_L1P_T0L_N0_DBC_66
-# #Other net PACKAGE_PIN BA11 - VREF_66 Bank 66 - VREF_66
-# #set_property PACKAGE_PIN AL19 [get_ports ""] ;# Bank 65 VCCO - VCC1V8_FPGA - IO_L24N_T3U_N11_DOUT_CSO_B_65
-# #set_property IOSTANDARD LVCMOSxx [get_ports ""] ;# Bank 65 VCCO - VCC1V8_FPGA - IO_L24N_T3U_N11_DOUT_CSO_B_65
-# set_property PACKAGE_PIN AL20 [get_ports "FPGA_EMCCLK"] ;# Bank 65 VCCO - VCC1V8_FPGA - IO_L24P_T3U_N10_EMCCLK_65
-# set_property IOSTANDARD LVCMOS18 [get_ports "FPGA_EMCCLK"] ;# Bank 65 VCCO - VCC1V8_FPGA - IO_L24P_T3U_N10_EMCCLK_65
-# set_property PACKAGE_PIN AP17 [get_ports "SYSMON_SDA"] ;# Bank 65 VCCO - VCC1V8_FPGA - IO_L23N_T3U_N9_PERSTN1_I2C_SDA_65
-# set_property IOSTANDARD LVCMOS18 [get_ports "SYSMON_SDA"] ;# Bank 65 VCCO - VCC1V8_FPGA - IO_L23N_T3U_N9_PERSTN1_I2C_SDA_65
-# set_property PACKAGE_PIN AP18 [get_ports "SYSMON_SCL"] ;# Bank 65 VCCO - VCC1V8_FPGA - IO_L23P_T3U_N8_I2C_SCLK_65
-# set_property IOSTANDARD LVCMOS18 [get_ports "SYSMON_SCL"] ;# Bank 65 VCCO - VCC1V8_FPGA - IO_L23P_T3U_N8_I2C_SCLK_65
-# set_property PACKAGE_PIN AM18 [get_ports "QSPI1_DQ1"] ;# Bank 65 VCCO - VCC1V8_FPGA - IO_L22N_T3U_N7_DBC_AD0N_D05_65
-# set_property IOSTANDARD LVCMOS18 [get_ports "QSPI1_DQ1"] ;# Bank 65 VCCO - VCC1V8_FPGA - IO_L22N_T3U_N7_DBC_AD0N_D05_65
-# set_property PACKAGE_PIN AM19 [get_ports "QSPI1_DQ0"] ;# Bank 65 VCCO - VCC1V8_FPGA - IO_L22P_T3U_N6_DBC_AD0P_D04_65
-# set_property IOSTANDARD LVCMOS18 [get_ports "QSPI1_DQ0"] ;# Bank 65 VCCO - VCC1V8_FPGA - IO_L22P_T3U_N6_DBC_AD0P_D04_65
-# set_property PACKAGE_PIN AP20 [get_ports "QSPI1_DQ3"] ;# Bank 65 VCCO - VCC1V8_FPGA - IO_L21N_T3L_N5_AD8N_D07_65
-# set_property IOSTANDARD LVCMOS18 [get_ports "QSPI1_DQ3"] ;# Bank 65 VCCO - VCC1V8_FPGA - IO_L21N_T3L_N5_AD8N_D07_65
-# set_property PACKAGE_PIN AN20 [get_ports "QSPI1_DQ2"] ;# Bank 65 VCCO - VCC1V8_FPGA - IO_L21P_T3L_N4_AD8P_D06_65
-# set_property IOSTANDARD LVCMOS18 [get_ports "QSPI1_DQ2"] ;# Bank 65 VCCO - VCC1V8_FPGA - IO_L21P_T3L_N4_AD8P_D06_65
-# #set_property PACKAGE_PIN AN18 [get_ports ""] ;# Bank 65 VCCO - VCC1V8_FPGA - IO_L20N_T3L_N3_AD1N_D09_65
-# #set_property IOSTANDARD LVCMOSxx [get_ports ""] ;# Bank 65 VCCO - VCC1V8_FPGA - IO_L20N_T3L_N3_AD1N_D09_65
-# #set_property PACKAGE_PIN AN19 [get_ports ""] ;# Bank 65 VCCO - VCC1V8_FPGA - IO_L20P_T3L_N2_AD1P_D08_65
-# #set_property IOSTANDARD LVCMOSxx [get_ports ""] ;# Bank 65 VCCO - VCC1V8_FPGA - IO_L20P_T3L_N2_AD1P_D08_65
-# #set_property PACKAGE_PIN AR17 [get_ports ""] ;# Bank 65 VCCO - VCC1V8_FPGA - IO_L19N_T3L_N1_DBC_AD9N_D11_65
-# #set_property IOSTANDARD LVCMOSxx [get_ports ""] ;# Bank 65 VCCO - VCC1V8_FPGA - IO_L19N_T3L_N1_DBC_AD9N_D11_65
-# #set_property PACKAGE_PIN AR18 [get_ports ""] ;# Bank 65 VCCO - VCC1V8_FPGA - IO_L19P_T3L_N0_DBC_AD9P_D10_65
-# #set_property IOSTANDARD LVCMOSxx [get_ports ""] ;# Bank 65 VCCO - VCC1V8_FPGA - IO_L19P_T3L_N0_DBC_AD9P_D10_65
-# set_property PACKAGE_PIN AM17 [get_ports "PCIE_PERST_LS"] ;# Bank 65 VCCO - VCC1V8_FPGA - IO_T3U_N12_PERSTN0_65
-# set_property IOSTANDARD LVCMOS18 [get_ports "PCIE_PERST_LS"] ;# Bank 65 VCCO - VCC1V8_FPGA - IO_T3U_N12_PERSTN0_65
-# #set_property PACKAGE_PIN AW17 [get_ports ""] ;# Bank 65 VCCO - VCC1V8_FPGA - IO_T2U_N12_CSI_ADV_B_65
-# #set_property IOSTANDARD LVCMOSxx [get_ports ""] ;# Bank 65 VCCO - VCC1V8_FPGA - IO_T2U_N12_CSI_ADV_B_65
-# #set_property PACKAGE_PIN AT19 [get_ports ""] ;# Bank 65 VCCO - VCC1V8_FPGA - IO_L18N_T2U_N11_AD2N_D13_65
-# #set_property IOSTANDARD LVCMOSxx [get_ports ""] ;# Bank 65 VCCO - VCC1V8_FPGA - IO_L18N_T2U_N11_AD2N_D13_65
-# #set_property PACKAGE_PIN AT20 [get_ports ""] ;# Bank 65 VCCO - VCC1V8_FPGA - IO_L18P_T2U_N10_AD2P_D12_65
-# #set_property IOSTANDARD LVCMOSxx [get_ports ""] ;# Bank 65 VCCO - VCC1V8_FPGA - IO_L18P_T2U_N10_AD2P_D12_65
-# #set_property PACKAGE_PIN AU17 [get_ports ""] ;# Bank 65 VCCO - VCC1V8_FPGA - IO_L17N_T2U_N9_AD10N_D15_65
-# #set_property IOSTANDARD LVCMOSxx [get_ports ""] ;# Bank 65 VCCO - VCC1V8_FPGA - IO_L17N_T2U_N9_AD10N_D15_65
-# #set_property PACKAGE_PIN AT17 [get_ports ""] ;# Bank 65 VCCO - VCC1V8_FPGA - IO_L17P_T2U_N8_AD10P_D14_65
-# #set_property IOSTANDARD LVCMOSxx [get_ports ""] ;# Bank 65 VCCO - VCC1V8_FPGA - IO_L17P_T2U_N8_AD10P_D14_65
-# #set_property PACKAGE_PIN AR19 [get_ports ""] ;# Bank 65 VCCO - VCC1V8_FPGA - IO_L16N_T2U_N7_QBC_AD3N_A01_D17_65
-# #set_property IOSTANDARD LVCMOSxx [get_ports ""] ;# Bank 65 VCCO - VCC1V8_FPGA - IO_L16N_T2U_N7_QBC_AD3N_A01_D17_65
-# #set_property PACKAGE_PIN AR20 [get_ports ""] ;# Bank 65 VCCO - VCC1V8_FPGA - IO_L16P_T2U_N6_QBC_AD3P_A00_D16_65
-# #set_property IOSTANDARD LVCMOSxx [get_ports ""] ;# Bank 65 VCCO - VCC1V8_FPGA - IO_L16P_T2U_N6_QBC_AD3P_A00_D16_65
-# #set_property PACKAGE_PIN AW20 [get_ports ""] ;# Bank 65 VCCO - VCC1V8_FPGA - IO_L15N_T2L_N5_AD11N_A03_D19_65
-# #set_property IOSTANDARD LVCMOSxx [get_ports ""] ;# Bank 65 VCCO - VCC1V8_FPGA - IO_L15N_T2L_N5_AD11N_A03_D19_65
-# #set_property PACKAGE_PIN AV20 [get_ports ""] ;# Bank 65 VCCO - VCC1V8_FPGA - IO_L15P_T2L_N4_AD11P_A02_D18_65
-# #set_property IOSTANDARD LVCMOSxx [get_ports ""] ;# Bank 65 VCCO - VCC1V8_FPGA - IO_L15P_T2L_N4_AD11P_A02_D18_65
-# #set_property PACKAGE_PIN AU18 [get_ports ""] ;# Bank 65 VCCO - VCC1V8_FPGA - IO_L14N_T2L_N3_GC_A05_D21_65
-# #set_property IOSTANDARD LVCMOSxx [get_ports ""] ;# Bank 65 VCCO - VCC1V8_FPGA - IO_L14N_T2L_N3_GC_A05_D21_65
-# #set_property PACKAGE_PIN AU19 [get_ports ""] ;# Bank 65 VCCO - VCC1V8_FPGA - IO_L14P_T2L_N2_GC_A04_D20_65
-# #set_property IOSTANDARD LVCMOSxx [get_ports ""] ;# Bank 65 VCCO - VCC1V8_FPGA - IO_L14P_T2L_N2_GC_A04_D20_65
-# #set_property PACKAGE_PIN AV18 [get_ports ""] ;# Bank 65 VCCO - VCC1V8_FPGA - IO_L13N_T2L_N1_GC_QBC_A07_D23_65
-# #set_property IOSTANDARD LVCMOSxx [get_ports ""] ;# Bank 65 VCCO - VCC1V8_FPGA - IO_L13N_T2L_N1_GC_QBC_A07_D23_65
-# #set_property PACKAGE_PIN AV19 [get_ports ""] ;# Bank 65 VCCO - VCC1V8_FPGA - IO_L13P_T2L_N0_GC_QBC_A06_D22_65
-# #set_property IOSTANDARD LVCMOSxx [get_ports ""] ;# Bank 65 VCCO - VCC1V8_FPGA - IO_L13P_T2L_N0_GC_QBC_A06_D22_65
-# #set_property PACKAGE_PIN AY18 [get_ports ""] ;# Bank 65 VCCO - VCC1V8_FPGA - IO_L12N_T1U_N11_GC_A09_D25_65
-# #set_property IOSTANDARD LVCMOSxx [get_ports ""] ;# Bank 65 VCCO - VCC1V8_FPGA - IO_L12N_T1U_N11_GC_A09_D25_65
-# #set_property PACKAGE_PIN AW18 [get_ports ""] ;# Bank 65 VCCO - VCC1V8_FPGA - IO_L12P_T1U_N10_GC_A08_D24_65
-# #set_property IOSTANDARD LVCMOSxx [get_ports ""] ;# Bank 65 VCCO - VCC1V8_FPGA - IO_L12P_T1U_N10_GC_A08_D24_65
-# #set_property PACKAGE_PIN BA19 [get_ports ""] ;# Bank 65 VCCO - VCC1V8_FPGA - IO_L11N_T1U_N9_GC_A11_D27_65
-# #set_property IOSTANDARD LVCMOSxx [get_ports ""] ;# Bank 65 VCCO - VCC1V8_FPGA - IO_L11N_T1U_N9_GC_A11_D27_65
-# #set_property PACKAGE_PIN AY19 [get_ports ""] ;# Bank 65 VCCO - VCC1V8_FPGA - IO_L11P_T1U_N8_GC_A10_D26_65
-# #set_property IOSTANDARD LVCMOSxx [get_ports ""] ;# Bank 65 VCCO - VCC1V8_FPGA - IO_L11P_T1U_N8_GC_A10_D26_65
-# #set_property PACKAGE_PIN BB17 [get_ports ""] ;# Bank 65 VCCO - VCC1V8_FPGA - IO_L10N_T1U_N7_QBC_AD4N_A13_D29_65
-# #set_property IOSTANDARD LVCMOSxx [get_ports ""] ;# Bank 65 VCCO - VCC1V8_FPGA - IO_L10N_T1U_N7_QBC_AD4N_A13_D29_65
-# #set_property PACKAGE_PIN BA17 [get_ports ""] ;# Bank 65 VCCO - VCC1V8_FPGA - IO_L10P_T1U_N6_QBC_AD4P_A12_D28_65
-# #set_property IOSTANDARD LVCMOSxx [get_ports ""] ;# Bank 65 VCCO - VCC1V8_FPGA - IO_L10P_T1U_N6_QBC_AD4P_A12_D28_65
-# #set_property PACKAGE_PIN BC19 [get_ports ""] ;# Bank 65 VCCO - VCC1V8_FPGA - IO_L9N_T1L_N5_AD12N_A15_D31_65
-# #set_property IOSTANDARD LVCMOSxx [get_ports ""] ;# Bank 65 VCCO - VCC1V8_FPGA - IO_L9N_T1L_N5_AD12N_A15_D31_65
-# #set_property PACKAGE_PIN BB19 [get_ports ""] ;# Bank 65 VCCO - VCC1V8_FPGA - IO_L9P_T1L_N4_AD12P_A14_D30_65
-# #set_property IOSTANDARD LVCMOSxx [get_ports ""] ;# Bank 65 VCCO - VCC1V8_FPGA - IO_L9P_T1L_N4_AD12P_A14_D30_65
-# #set_property PACKAGE_PIN BC18 [get_ports ""] ;# Bank 65 VCCO - VCC1V8_FPGA - IO_L8N_T1L_N3_AD5N_A17_65
-# #set_property IOSTANDARD LVCMOSxx [get_ports ""] ;# Bank 65 VCCO - VCC1V8_FPGA - IO_L8N_T1L_N3_AD5N_A17_65
-# #set_property PACKAGE_PIN BB18 [get_ports ""] ;# Bank 65 VCCO - VCC1V8_FPGA - IO_L8P_T1L_N2_AD5P_A16_65
-# #set_property IOSTANDARD LVCMOSxx [get_ports ""] ;# Bank 65 VCCO - VCC1V8_FPGA - IO_L8P_T1L_N2_AD5P_A16_65
-# #set_property PACKAGE_PIN BA20 [get_ports ""] ;# Bank 65 VCCO - VCC1V8_FPGA - IO_L7N_T1L_N1_QBC_AD13N_A19_65
-# #set_property IOSTANDARD LVCMOSxx [get_ports ""] ;# Bank 65 VCCO - VCC1V8_FPGA - IO_L7N_T1L_N1_QBC_AD13N_A19_65
-# #set_property PACKAGE_PIN AY20 [get_ports ""] ;# Bank 65 VCCO - VCC1V8_FPGA - IO_L7P_T1L_N0_QBC_AD13P_A18_65
-# #set_property IOSTANDARD LVCMOSxx [get_ports ""] ;# Bank 65 VCCO - VCC1V8_FPGA - IO_L7P_T1L_N0_QBC_AD13P_A18_65
-# #set_property PACKAGE_PIN AY17 [get_ports ""] ;# Bank 65 VCCO - VCC1V8_FPGA - IO_T1U_N12_SMBALERT_65
-# #set_property IOSTANDARD LVCMOSxx [get_ports ""] ;# Bank 65 VCCO - VCC1V8_FPGA - IO_T1U_N12_SMBALERT_65
-# #set_property PACKAGE_PIN BF21 [get_ports "VRP_65"] ;# Bank 65 VCCO - VCC1V8_FPGA - IO_T0U_N12_VRP_A28_65
-# #set_property IOSTANDARD LVCMOSxx [get_ports "VRP_65"] ;# Bank 65 VCCO - VCC1V8_FPGA - IO_T0U_N12_VRP_A28_65
-# #set_property PACKAGE_PIN BD17 [get_ports ""] ;# Bank 65 VCCO - VCC1V8_FPGA - IO_L6N_T0U_N11_AD6N_A21_65
-# #set_property IOSTANDARD LVCMOSxx [get_ports ""] ;# Bank 65 VCCO - VCC1V8_FPGA - IO_L6N_T0U_N11_AD6N_A21_65
-# #set_property PACKAGE_PIN BD18 [get_ports ""] ;# Bank 65 VCCO - VCC1V8_FPGA - IO_L6P_T0U_N10_AD6P_A20_65
-# #set_property IOSTANDARD LVCMOSxx [get_ports ""] ;# Bank 65 VCCO - VCC1V8_FPGA - IO_L6P_T0U_N10_AD6P_A20_65
-# #set_property PACKAGE_PIN BD20 [get_ports ""] ;# Bank 65 VCCO - VCC1V8_FPGA - IO_L5N_T0U_N9_AD14N_A23_65
-# #set_property IOSTANDARD LVCMOSxx [get_ports ""] ;# Bank 65 VCCO - VCC1V8_FPGA - IO_L5N_T0U_N9_AD14N_A23_65
-# #set_property PACKAGE_PIN BC20 [get_ports ""] ;# Bank 65 VCCO - VCC1V8_FPGA - IO_L5P_T0U_N8_AD14P_A22_65
-# #set_property IOSTANDARD LVCMOSxx [get_ports ""] ;# Bank 65 VCCO - VCC1V8_FPGA - IO_L5P_T0U_N8_AD14P_A22_65
-# #set_property PACKAGE_PIN BE17 [get_ports ""] ;# Bank 65 VCCO - VCC1V8_FPGA - IO_L4N_T0U_N7_DBC_AD7N_A25_65
-# #set_property IOSTANDARD LVCMOSxx [get_ports ""] ;# Bank 65 VCCO - VCC1V8_FPGA - IO_L4N_T0U_N7_DBC_AD7N_A25_65
-# #set_property PACKAGE_PIN BE18 [get_ports ""] ;# Bank 65 VCCO - VCC1V8_FPGA - IO_L4P_T0U_N6_DBC_AD7P_A24_65
-# #set_property IOSTANDARD LVCMOSxx [get_ports ""] ;# Bank 65 VCCO - VCC1V8_FPGA - IO_L4P_T0U_N6_DBC_AD7P_A24_65
-# #set_property PACKAGE_PIN BF19 [get_ports ""] ;# Bank 65 VCCO - VCC1V8_FPGA - IO_L3N_T0L_N5_AD15N_A27_65
-# #set_property IOSTANDARD LVCMOSxx [get_ports ""] ;# Bank 65 VCCO - VCC1V8_FPGA - IO_L3N_T0L_N5_AD15N_A27_65
-# #set_property PACKAGE_PIN BE19 [get_ports ""] ;# Bank 65 VCCO - VCC1V8_FPGA - IO_L3P_T0L_N4_AD15P_A26_65
-# #set_property IOSTANDARD LVCMOSxx [get_ports ""] ;# Bank 65 VCCO - VCC1V8_FPGA - IO_L3P_T0L_N4_AD15P_A26_65
-# set_property PACKAGE_PIN BF16 [get_ports "QSPI1_CS_B"] ;# Bank 65 VCCO - VCC1V8_FPGA - IO_L2N_T0L_N3_FWE_FCS2_B_65
-# set_property IOSTANDARD LVCMOS18 [get_ports "QSPI1_CS_B"] ;# Bank 65 VCCO - VCC1V8_FPGA - IO_L2N_T0L_N3_FWE_FCS2_B_65
-# set_property PACKAGE_PIN BF17 [get_ports "BPI_FLASH_OE_B"] ;# Bank 65 VCCO - VCC1V8_FPGA - IO_L2P_T0L_N2_FOE_B_65
-# set_property IOSTANDARD LVCMOS18 [get_ports "BPI_FLASH_OE_B"] ;# Bank 65 VCCO - VCC1V8_FPGA - IO_L2P_T0L_N2_FOE_B_65
-# #set_property PACKAGE_PIN BF20 [get_ports ""] ;# Bank 65 VCCO - VCC1V8_FPGA - IO_L1N_T0L_N1_DBC_RS1_65
-# #set_property IOSTANDARD LVCMOSxx [get_ports ""] ;# Bank 65 VCCO - VCC1V8_FPGA - IO_L1N_T0L_N1_DBC_RS1_65
-# #set_property PACKAGE_PIN BE20 [get_ports ""] ;# Bank 65 VCCO - VCC1V8_FPGA - IO_L1P_T0L_N0_DBC_RS0_65
-# #set_property IOSTANDARD LVCMOSxx [get_ports ""] ;# Bank 65 VCCO - VCC1V8_FPGA - IO_L1P_T0L_N0_DBC_RS0_65
-# #Other net PACKAGE_PIN AL17 - 8N8196 Bank 65 - VREF_65
-# set_property PACKAGE_PIN AM24 [get_ports "IIC_MAIN_SCL"] ;# Bank 64 VCCO - VCC1V8_FPGA - IO_L24N_T3U_N11_64
-# set_property IOSTANDARD LVCMOS18 [get_ports "IIC_MAIN_SCL"] ;# Bank 64 VCCO - VCC1V8_FPGA - IO_L24N_T3U_N11_64
-# set_property PACKAGE_PIN AL24 [get_ports "IIC_MAIN_SDA"] ;# Bank 64 VCCO - VCC1V8_FPGA - IO_L24P_T3U_N10_64
-# set_property IOSTANDARD LVCMOS18 [get_ports "IIC_MAIN_SDA"] ;# Bank 64 VCCO - VCC1V8_FPGA - IO_L24P_T3U_N10_64
-# set_property PACKAGE_PIN AM21 [get_ports "QSFP1_MODSELL_LS"] ;# Bank 64 VCCO - VCC1V8_FPGA - IO_L23N_T3U_N9_64
-# set_property IOSTANDARD LVCMOS18 [get_ports "QSFP1_MODSELL_LS"] ;# Bank 64 VCCO - VCC1V8_FPGA - IO_L23N_T3U_N9_64
-# set_property PACKAGE_PIN AL21 [get_ports "QSFP1_MODPRSL_LS"] ;# Bank 64 VCCO - VCC1V8_FPGA - IO_L23P_T3U_N8_64
-# set_property IOSTANDARD LVCMOS18 [get_ports "QSFP1_MODPRSL_LS"] ;# Bank 64 VCCO - VCC1V8_FPGA - IO_L23P_T3U_N8_64
-# set_property PACKAGE_PIN AM22 [get_ports "QSFP1_RECCLK_N"] ;# Bank 64 VCCO - VCC1V8_FPGA - IO_L22N_T3U_N7_DBC_AD0N_64
-# set_property IOSTANDARD LVDS [get_ports "QSFP1_RECCLK_N"] ;# Bank 64 VCCO - VCC1V8_FPGA - IO_L22N_T3U_N7_DBC_AD0N_64
-# set_property PACKAGE_PIN AM23 [get_ports "QSFP1_RECCLK_P"] ;# Bank 64 VCCO - VCC1V8_FPGA - IO_L22P_T3U_N6_DBC_AD0P_64
-# set_property IOSTANDARD LVDS [get_ports "QSFP1_RECCLK_P"] ;# Bank 64 VCCO - VCC1V8_FPGA - IO_L22P_T3U_N6_DBC_AD0P_64
-# set_property PACKAGE_PIN AP21 [get_ports "QSFP1_INTL_LS"] ;# Bank 64 VCCO - VCC1V8_FPGA - IO_L21N_T3L_N5_AD8N_64
-# set_property IOSTANDARD LVCMOS18 [get_ports "QSFP1_INTL_LS"] ;# Bank 64 VCCO - VCC1V8_FPGA - IO_L21N_T3L_N5_AD8N_64
-# set_property PACKAGE_PIN AN21 [get_ports "QSFP1_LPMODE_LS"] ;# Bank 64 VCCO - VCC1V8_FPGA - IO_L21P_T3L_N4_AD8P_64
-# set_property IOSTANDARD LVCMOS18 [get_ports "QSFP1_LPMODE_LS"] ;# Bank 64 VCCO - VCC1V8_FPGA - IO_L21P_T3L_N4_AD8P_64
-# set_property PACKAGE_PIN AN23 [get_ports "QSFP2_MODSELL_LS"] ;# Bank 64 VCCO - VCC1V8_FPGA - IO_L20N_T3L_N3_AD1N_64
-# set_property IOSTANDARD LVCMOS18 [get_ports "QSFP2_MODSELL_LS"] ;# Bank 64 VCCO - VCC1V8_FPGA - IO_L20N_T3L_N3_AD1N_64
-# set_property PACKAGE_PIN AN24 [get_ports "QSFP2_MODPRSL_LS"] ;# Bank 64 VCCO - VCC1V8_FPGA - IO_L20P_T3L_N2_AD1P_64
-# set_property IOSTANDARD LVCMOS18 [get_ports "QSFP2_MODPRSL_LS"] ;# Bank 64 VCCO - VCC1V8_FPGA - IO_L20P_T3L_N2_AD1P_64
-# set_property PACKAGE_PIN AP22 [get_ports "QSFP2_RECCLK_N"] ;# Bank 64 VCCO - VCC1V8_FPGA - IO_L19N_T3L_N1_DBC_AD9N_64
-# set_property IOSTANDARD LVDS [get_ports "QSFP2_RECCLK_N"] ;# Bank 64 VCCO - VCC1V8_FPGA - IO_L19N_T3L_N1_DBC_AD9N_64
-# set_property PACKAGE_PIN AP23 [get_ports "QSFP2_RECCLK_P"] ;# Bank 64 VCCO - VCC1V8_FPGA - IO_L19P_T3L_N0_DBC_AD9P_64
-# set_property IOSTANDARD LVDS [get_ports "QSFP2_RECCLK_P"] ;# Bank 64 VCCO - VCC1V8_FPGA - IO_L19P_T3L_N0_DBC_AD9P_64
-# set_property PACKAGE_PIN AL25 [get_ports "IIC_MUX_RESET_B"] ;# Bank 64 VCCO - VCC1V8_FPGA - IO_T3U_N12_64
-# set_property IOSTANDARD LVCMOS18 [get_ports "IIC_MUX_RESET_B"] ;# Bank 64 VCCO - VCC1V8_FPGA - IO_T3U_N12_64
-# set_property PACKAGE_PIN AT21 [get_ports "QSFP2_INTL_LS"] ;# Bank 64 VCCO - VCC1V8_FPGA - IO_T2U_N12_64
-# set_property IOSTANDARD LVCMOS18 [get_ports "QSFP2_INTL_LS"] ;# Bank 64 VCCO - VCC1V8_FPGA - IO_T2U_N12_64
-# set_property PACKAGE_PIN AT24 [get_ports "QSFP2_LPMODE_LS"] ;# Bank 64 VCCO - VCC1V8_FPGA - IO_L18N_T2U_N11_AD2N_64
-# set_property IOSTANDARD LVCMOS18 [get_ports "QSFP2_LPMODE_LS"] ;# Bank 64 VCCO - VCC1V8_FPGA - IO_L18N_T2U_N11_AD2N_64
-# set_property PACKAGE_PIN AR24 [get_ports "PHY1_PDWN_B_I_INT_B_O"] ;# Bank 64 VCCO - VCC1V8_FPGA - IO_L18P_T2U_N10_AD2P_64
-# set_property IOSTANDARD LVCMOS18 [get_ports "PHY1_PDWN_B_I_INT_B_O"] ;# Bank 64 VCCO - VCC1V8_FPGA - IO_L18P_T2U_N10_AD2P_64
-# set_property PACKAGE_PIN AR22 [get_ports "PHY1_GPIO_0"] ;# Bank 64 VCCO - VCC1V8_FPGA - IO_L17N_T2U_N9_AD10N_64
-# set_property IOSTANDARD LVCMOS18 [get_ports "PHY1_GPIO_0"] ;# Bank 64 VCCO - VCC1V8_FPGA - IO_L17N_T2U_N9_AD10N_64
-# set_property PACKAGE_PIN AR23 [get_ports "PHY1_MDIO"] ;# Bank 64 VCCO - VCC1V8_FPGA - IO_L17P_T2U_N8_AD10P_64
-# set_property IOSTANDARD LVCMOS18 [get_ports "PHY1_MDIO"] ;# Bank 64 VCCO - VCC1V8_FPGA - IO_L17P_T2U_N8_AD10P_64
-# set_property PACKAGE_PIN AV24 [get_ports "PHY1_SGMII_OUT_N"] ;# Bank 64 VCCO - VCC1V8_FPGA - IO_L16N_T2U_N7_QBC_AD3N_64
-# set_property IOSTANDARD LVDS [get_ports "PHY1_SGMII_OUT_N"] ;# Bank 64 VCCO - VCC1V8_FPGA - IO_L16N_T2U_N7_QBC_AD3N_64
-# set_property PACKAGE_PIN AU24 [get_ports "PHY1_SGMII_OUT_P"] ;# Bank 64 VCCO - VCC1V8_FPGA - IO_L16P_T2U_N6_QBC_AD3P_64
-# set_property IOSTANDARD LVDS [get_ports "PHY1_SGMII_OUT_P"] ;# Bank 64 VCCO - VCC1V8_FPGA - IO_L16P_T2U_N6_QBC_AD3P_64
-# set_property PACKAGE_PIN AV21 [get_ports "PHY1_SGMII_IN_N"] ;# Bank 64 VCCO - VCC1V8_FPGA - IO_L15N_T2L_N5_AD11N_64
-# set_property IOSTANDARD LVDS [get_ports "PHY1_SGMII_IN_N"] ;# Bank 64 VCCO - VCC1V8_FPGA - IO_L15N_T2L_N5_AD11N_64
-# set_property PACKAGE_PIN AU21 [get_ports "PHY1_SGMII_IN_P"] ;# Bank 64 VCCO - VCC1V8_FPGA - IO_L15P_T2L_N4_AD11P_64
-# set_property IOSTANDARD LVDS [get_ports "PHY1_SGMII_IN_P"] ;# Bank 64 VCCO - VCC1V8_FPGA - IO_L15P_T2L_N4_AD11P_64
-# set_property PACKAGE_PIN AV23 [get_ports "PHY1_MDC"] ;# Bank 64 VCCO - VCC1V8_FPGA - IO_L14N_T2L_N3_GC_64
-# set_property IOSTANDARD LVCMOS18 [get_ports "PHY1_MDC"] ;# Bank 64 VCCO - VCC1V8_FPGA - IO_L14N_T2L_N3_GC_64
-# set_property PACKAGE_PIN AU23 [get_ports "PHY1_CLKOUT"] ;# Bank 64 VCCO - VCC1V8_FPGA - IO_L14P_T2L_N2_GC_64
-# set_property IOSTANDARD LVCMOS18 [get_ports "PHY1_CLKOUT"] ;# Bank 64 VCCO - VCC1V8_FPGA - IO_L14P_T2L_N2_GC_64
-# set_property PACKAGE_PIN AU22 [get_ports "PHY1_SGMII_CLK_N"] ;# Bank 64 VCCO - VCC1V8_FPGA - IO_L13N_T2L_N1_GC_QBC_64
-# set_property IOSTANDARD LVDS [get_ports "PHY1_SGMII_CLK_N"] ;# Bank 64 VCCO - VCC1V8_FPGA - IO_L13N_T2L_N1_GC_QBC_64
-# set_property PACKAGE_PIN AT22 [get_ports "PHY1_SGMII_CLK_P"] ;# Bank 64 VCCO - VCC1V8_FPGA - IO_L13P_T2L_N0_GC_QBC_64
-# set_property IOSTANDARD LVDS [get_ports "PHY1_SGMII_CLK_P"] ;# Bank 64 VCCO - VCC1V8_FPGA - IO_L13P_T2L_N0_GC_QBC_64
-# set_property PACKAGE_PIN AW22 [get_ports "USER_SI570_CLOCK1_N"] ;# Bank 64 VCCO - VCC1V8_FPGA - IO_L12N_T1U_N11_GC_64
-# set_property IOSTANDARD LVDS [get_ports "USER_SI570_CLOCK1_N"] ;# Bank 64 VCCO - VCC1V8_FPGA - IO_L12N_T1U_N11_GC_64
-# set_property PACKAGE_PIN AW23 [get_ports "USER_SI570_CLOCK1_P"] ;# Bank 64 VCCO - VCC1V8_FPGA - IO_L12P_T1U_N10_GC_64
-# set_property IOSTANDARD LVDS [get_ports "USER_SI570_CLOCK1_P"] ;# Bank 64 VCCO - VCC1V8_FPGA - IO_L12P_T1U_N10_GC_64
-# set_property PACKAGE_PIN BA22 [get_ports "QSFP1_RESETL_LS"] ;# Bank 64 VCCO - VCC1V8_FPGA - IO_L10N_T1U_N7_QBC_AD4N_64
-# set_property IOSTANDARD LVCMOS18 [get_ports "QSFP1_RESETL_LS"] ;# Bank 64 VCCO - VCC1V8_FPGA - IO_L10N_T1U_N7_QBC_AD4N_64
-# set_property PACKAGE_PIN AY22 [get_ports "QSFP2_RESETL_LS"] ;# Bank 64 VCCO - VCC1V8_FPGA - IO_L10P_T1U_N6_QBC_AD4P_64
-# set_property IOSTANDARD LVCMOS18 [get_ports "QSFP2_RESETL_LS"] ;# Bank 64 VCCO - VCC1V8_FPGA - IO_L10P_T1U_N6_QBC_AD4P_64
-# set_property PACKAGE_PIN AY25 [get_ports "USB_UART_RTS"] ;# Bank 64 VCCO - VCC1V8_FPGA - IO_L9N_T1L_N5_AD12N_64
-# set_property IOSTANDARD LVCMOS18 [get_ports "USB_UART_RTS"] ;# Bank 64 VCCO - VCC1V8_FPGA - IO_L9N_T1L_N5_AD12N_64
-
-# set_property PACKAGE_PIN BB22 [get_ports "USB_UART_CTS"] ;# Bank 64 VCCO - VCC1V8_FPGA - IO_L8P_T1L_N2_AD5P_64
-# set_property IOSTANDARD LVCMOS18 [get_ports "USB_UART_CTS"] ;# Bank 64 VCCO - VCC1V8_FPGA - IO_L8P_T1L_N2_AD5P_64
-# set_property PACKAGE_PIN BA24 [get_ports "SYSCTLR_GPIO_7"] ;# Bank 64 VCCO - VCC1V8_FPGA - IO_L7N_T1L_N1_QBC_AD13N_64
-# set_property IOSTANDARD LVCMOS18 [get_ports "SYSCTLR_GPIO_7"] ;# Bank 64 VCCO - VCC1V8_FPGA - IO_L7N_T1L_N1_QBC_AD13N_64
-# set_property PACKAGE_PIN BA25 [get_ports "SYSCTLR_GPIO_6"] ;# Bank 64 VCCO - VCC1V8_FPGA - IO_L7P_T1L_N0_QBC_AD13P_64
-# set_property IOSTANDARD LVCMOS18 [get_ports "SYSCTLR_GPIO_6"] ;# Bank 64 VCCO - VCC1V8_FPGA - IO_L7P_T1L_N0_QBC_AD13P_64
-# set_property PACKAGE_PIN BA21 [get_ports "PHY1_RESET_B"] ;# Bank 64 VCCO - VCC1V8_FPGA - IO_T1U_N12_64
-# set_property IOSTANDARD LVCMOS18 [get_ports "PHY1_RESET_B"] ;# Bank 64 VCCO - VCC1V8_FPGA - IO_T1U_N12_64
-# #set_property PACKAGE_PIN BC24 [get_ports "PCIE_WAKE_B_LS"] ;# Bank 64 VCCO - VCC1V8_FPGA - IO_T0U_N12_VRP_64
-# #set_property IOSTANDARD LVCMOS18 [get_ports "PCIE_WAKE_B_LS"] ;# Bank 64 VCCO - VCC1V8_FPGA - IO_T0U_N12_VRP_64
-# set_property PACKAGE_PIN BD21 [get_ports "SYSCTLR_GPIO_5"] ;# Bank 64 VCCO - VCC1V8_FPGA - IO_L6N_T0U_N11_AD6N_64
-# set_property IOSTANDARD LVCMOS18 [get_ports "SYSCTLR_GPIO_5"] ;# Bank 64 VCCO - VCC1V8_FPGA - IO_L6N_T0U_N11_AD6N_64
-# set_property PACKAGE_PIN BC21 [get_ports "SI5328_RST_LS_B"] ;# Bank 64 VCCO - VCC1V8_FPGA - IO_L6P_T0U_N10_AD6P_64
-# set_property IOSTANDARD LVCMOS18 [get_ports "SI5328_RST_LS_B"] ;# Bank 64 VCCO - VCC1V8_FPGA - IO_L6P_T0U_N10_AD6P_64
-# set_property PACKAGE_PIN BB23 [get_ports "PMBUS_ALERT_FPGA"] ;# Bank 64 VCCO - VCC1V8_FPGA - IO_L5N_T0U_N9_AD14N_64
-# set_property IOSTANDARD LVCMOS18 [get_ports "PMBUS_ALERT_FPGA"] ;# Bank 64 VCCO - VCC1V8_FPGA - IO_L5N_T0U_N9_AD14N_64
-# set_property PACKAGE_PIN BB24 [get_ports "GPIO_SW_N"] ;# Bank 64 VCCO - VCC1V8_FPGA - IO_L5P_T0U_N8_AD14P_64
-# set_property IOSTANDARD LVCMOS18 [get_ports "GPIO_SW_N"] ;# Bank 64 VCCO - VCC1V8_FPGA - IO_L5P_T0U_N8_AD14P_64
-# set_property PACKAGE_PIN BF22 [get_ports "GPIO_SW_W"] ;# Bank 64 VCCO - VCC1V8_FPGA - IO_L4N_T0U_N7_DBC_AD7N_64
-# set_property IOSTANDARD LVCMOS18 [get_ports "GPIO_SW_W"] ;# Bank 64 VCCO - VCC1V8_FPGA - IO_L4N_T0U_N7_DBC_AD7N_64
-# set_property PACKAGE_PIN BE22 [get_ports "GPIO_SW_S"] ;# Bank 64 VCCO - VCC1V8_FPGA - IO_L4P_T0U_N6_DBC_AD7P_64
-# set_property IOSTANDARD LVCMOS18 [get_ports "GPIO_SW_S"] ;# Bank 64 VCCO - VCC1V8_FPGA - IO_L4P_T0U_N6_DBC_AD7P_64
-# set_property PACKAGE_PIN BE23 [get_ports "GPIO_SW_E"] ;# Bank 64 VCCO - VCC1V8_FPGA - IO_L3N_T0L_N5_AD15N_64
-# set_property IOSTANDARD LVCMOS18 [get_ports "GPIO_SW_E"] ;# Bank 64 VCCO - VCC1V8_FPGA - IO_L3N_T0L_N5_AD15N_64
-# set_property PACKAGE_PIN BD23 [get_ports "GPIO_SW_C"] ;# Bank 64 VCCO - VCC1V8_FPGA - IO_L3P_T0L_N4_AD15P_64
-# set_property IOSTANDARD LVCMOS18 [get_ports "GPIO_SW_C"] ;# Bank 64 VCCO - VCC1V8_FPGA - IO_L3P_T0L_N4_AD15P_64
-# set_property PACKAGE_PIN BD22 [get_ports "FIREFLY_MODPRS_LS_B"] ;# Bank 64 VCCO - VCC1V8_FPGA - IO_L2N_T0L_N3_64
-# set_property IOSTANDARD LVCMOS18 [get_ports "FIREFLY_MODPRS_LS_B"] ;# Bank 64 VCCO - VCC1V8_FPGA - IO_L2N_T0L_N3_64
-# set_property PACKAGE_PIN BC23 [get_ports "FIREFLY_MODSEL_LS_B"] ;# Bank 64 VCCO - VCC1V8_FPGA - IO_L2P_T0L_N2_64
-# set_property IOSTANDARD LVCMOS18 [get_ports "FIREFLY_MODSEL_LS_B"] ;# Bank 64 VCCO - VCC1V8_FPGA - IO_L2P_T0L_N2_64
-# set_property PACKAGE_PIN BF24 [get_ports "FIREFLY_INT_LS_B"] ;# Bank 64 VCCO - VCC1V8_FPGA - IO_L1N_T0L_N1_DBC_64
-# set_property IOSTANDARD LVCMOS18 [get_ports "FIREFLY_INT_LS_B"] ;# Bank 64 VCCO - VCC1V8_FPGA - IO_L1N_T0L_N1_DBC_64
-# set_property PACKAGE_PIN BE24 [get_ports "FIREFLY_RESET_LS_B"] ;# Bank 64 VCCO - VCC1V8_FPGA - IO_L1P_T0L_N0_DBC_64
-# set_property IOSTANDARD LVCMOS18 [get_ports "FIREFLY_RESET_LS_B"] ;# Bank 64 VCCO - VCC1V8_FPGA - IO_L1P_T0L_N0_DBC_64
-# #Other net PACKAGE_PIN AL22 - 30N4994 Bank 64 - VREF_64
-# set_property PACKAGE_PIN AG33 [get_ports "FMCP_HSPC_LA15_N"] ;# Bank 43 VCCO - VADJ_1V8_FPGA - IO_L24N_T3U_N11_43
-# set_property IOSTANDARD LVDS [get_ports "FMCP_HSPC_LA15_N"] ;# Bank 43 VCCO - VADJ_1V8_FPGA - IO_L24N_T3U_N11_43
-# set_property PACKAGE_PIN AG32 [get_ports "FMCP_HSPC_LA15_P"] ;# Bank 43 VCCO - VADJ_1V8_FPGA - IO_L24P_T3U_N10_43
-# set_property IOSTANDARD LVDS [get_ports "FMCP_HSPC_LA15_P"] ;# Bank 43 VCCO - VADJ_1V8_FPGA - IO_L24P_T3U_N10_43
-# set_property PACKAGE_PIN AH31 [get_ports "FMCP_HSPC_LA14_N"] ;# Bank 43 VCCO - VADJ_1V8_FPGA - IO_L23N_T3U_N9_43
-# set_property IOSTANDARD LVDS [get_ports "FMCP_HSPC_LA14_N"] ;# Bank 43 VCCO - VADJ_1V8_FPGA - IO_L23N_T3U_N9_43
-# set_property PACKAGE_PIN AG31 [get_ports "FMCP_HSPC_LA14_P"] ;# Bank 43 VCCO - VADJ_1V8_FPGA - IO_L23P_T3U_N8_43
-# set_property IOSTANDARD LVDS [get_ports "FMCP_HSPC_LA14_P"] ;# Bank 43 VCCO - VADJ_1V8_FPGA - IO_L23P_T3U_N8_43
-# set_property PACKAGE_PIN AH35 [get_ports "FMCP_HSPC_LA16_N"] ;# Bank 43 VCCO - VADJ_1V8_FPGA - IO_L22N_T3U_N7_DBC_AD0N_43
-# set_property IOSTANDARD LVDS [get_ports "FMCP_HSPC_LA16_N"] ;# Bank 43 VCCO - VADJ_1V8_FPGA - IO_L22N_T3U_N7_DBC_AD0N_43
-# set_property PACKAGE_PIN AG34 [get_ports "FMCP_HSPC_LA16_P"] ;# Bank 43 VCCO - VADJ_1V8_FPGA - IO_L22P_T3U_N6_DBC_AD0P_43
-# set_property IOSTANDARD LVDS [get_ports "FMCP_HSPC_LA16_P"] ;# Bank 43 VCCO - VADJ_1V8_FPGA - IO_L22P_T3U_N6_DBC_AD0P_43
-# set_property PACKAGE_PIN AH34 [get_ports "FMCP_HSPC_LA12_N"] ;# Bank 43 VCCO - VADJ_1V8_FPGA - IO_L21N_T3L_N5_AD8N_43
-# set_property IOSTANDARD LVDS [get_ports "FMCP_HSPC_LA12_N"] ;# Bank 43 VCCO - VADJ_1V8_FPGA - IO_L21N_T3L_N5_AD8N_43
-# set_property PACKAGE_PIN AH33 [get_ports "FMCP_HSPC_LA12_P"] ;# Bank 43 VCCO - VADJ_1V8_FPGA - IO_L21P_T3L_N4_AD8P_43
-# set_property IOSTANDARD LVDS [get_ports "FMCP_HSPC_LA12_P"] ;# Bank 43 VCCO - VADJ_1V8_FPGA - IO_L21P_T3L_N4_AD8P_43
-# set_property PACKAGE_PIN AJ36 [get_ports "FMCP_HSPC_LA13_N"] ;# Bank 43 VCCO - VADJ_1V8_FPGA - IO_L20N_T3L_N3_AD1N_43
-# set_property IOSTANDARD LVDS [get_ports "FMCP_HSPC_LA13_N"] ;# Bank 43 VCCO - VADJ_1V8_FPGA - IO_L20N_T3L_N3_AD1N_43
-# set_property PACKAGE_PIN AJ35 [get_ports "FMCP_HSPC_LA13_P"] ;# Bank 43 VCCO - VADJ_1V8_FPGA - IO_L20P_T3L_N2_AD1P_43
-# set_property IOSTANDARD LVDS [get_ports "FMCP_HSPC_LA13_P"] ;# Bank 43 VCCO - VADJ_1V8_FPGA - IO_L20P_T3L_N2_AD1P_43
-# set_property PACKAGE_PIN AK33 [get_ports "FMCP_HSPC_LA09_N"] ;# Bank 43 VCCO - VADJ_1V8_FPGA - IO_L19N_T3L_N1_DBC_AD9N_43
-# set_property IOSTANDARD LVDS [get_ports "FMCP_HSPC_LA09_N"] ;# Bank 43 VCCO - VADJ_1V8_FPGA - IO_L19N_T3L_N1_DBC_AD9N_43
-# set_property PACKAGE_PIN AJ33 [get_ports "FMCP_HSPC_LA09_P"] ;# Bank 43 VCCO - VADJ_1V8_FPGA - IO_L19P_T3L_N0_DBC_AD9P_43
-# set_property IOSTANDARD LVDS [get_ports "FMCP_HSPC_LA09_P"] ;# Bank 43 VCCO - VADJ_1V8_FPGA - IO_L19P_T3L_N0_DBC_AD9P_43
-# set_property PACKAGE_PIN AH30 [get_ports "9N9738"] ;# Bank 43 VCCO - VADJ_1V8_FPGA - IO_T3U_N12_43
-# set_property IOSTANDARD LVCMOSxx [get_ports "9N9738"] ;# Bank 43 VCCO - VADJ_1V8_FPGA - IO_T3U_N12_43
-# set_property PACKAGE_PIN AM31 [get_ports "9N9739"] ;# Bank 43 VCCO - VADJ_1V8_FPGA - IO_T2U_N12_43
-# set_property IOSTANDARD LVCMOSxx [get_ports "9N9739"] ;# Bank 43 VCCO - VADJ_1V8_FPGA - IO_T2U_N12_43
-# set_property PACKAGE_PIN AK30 [get_ports "FMCP_HSPC_LA08_N"] ;# Bank 43 VCCO - VADJ_1V8_FPGA - IO_L18N_T2U_N11_AD2N_43
-# set_property IOSTANDARD LVDS [get_ports "FMCP_HSPC_LA08_N"] ;# Bank 43 VCCO - VADJ_1V8_FPGA - IO_L18N_T2U_N11_AD2N_43
-# set_property PACKAGE_PIN AK29 [get_ports "FMCP_HSPC_LA08_P"] ;# Bank 43 VCCO - VADJ_1V8_FPGA - IO_L18P_T2U_N10_AD2P_43
-# set_property IOSTANDARD LVDS [get_ports "FMCP_HSPC_LA08_P"] ;# Bank 43 VCCO - VADJ_1V8_FPGA - IO_L18P_T2U_N10_AD2P_43
-# set_property PACKAGE_PIN AJ31 [get_ports "FMCP_HSPC_LA11_N"] ;# Bank 43 VCCO - VADJ_1V8_FPGA - IO_L17N_T2U_N9_AD10N_43
-# set_property IOSTANDARD LVDS [get_ports "FMCP_HSPC_LA11_N"] ;# Bank 43 VCCO - VADJ_1V8_FPGA - IO_L17N_T2U_N9_AD10N_43
-# set_property PACKAGE_PIN AJ30 [get_ports "FMCP_HSPC_LA11_P"] ;# Bank 43 VCCO - VADJ_1V8_FPGA - IO_L17P_T2U_N8_AD10P_43
-# set_property IOSTANDARD LVDS [get_ports "FMCP_HSPC_LA11_P"] ;# Bank 43 VCCO - VADJ_1V8_FPGA - IO_L17P_T2U_N8_AD10P_43
-# set_property PACKAGE_PIN AL31 [get_ports "FMCP_HSPC_LA01_CC_N"] ;# Bank 43 VCCO - VADJ_1V8_FPGA - IO_L16N_T2U_N7_QBC_AD3N_43
-# set_property IOSTANDARD LVDS [get_ports "FMCP_HSPC_LA01_CC_N"] ;# Bank 43 VCCO - VADJ_1V8_FPGA - IO_L16N_T2U_N7_QBC_AD3N_43
-# set_property PACKAGE_PIN AL30 [get_ports "FMCP_HSPC_LA01_CC_P"] ;# Bank 43 VCCO - VADJ_1V8_FPGA - IO_L16P_T2U_N6_QBC_AD3P_43
-# set_property IOSTANDARD LVDS [get_ports "FMCP_HSPC_LA01_CC_P"] ;# Bank 43 VCCO - VADJ_1V8_FPGA - IO_L16P_T2U_N6_QBC_AD3P_43
-# set_property PACKAGE_PIN AM29 [get_ports "FMCP_HSPC_Z_PRSNT_M2C_B_LS"] ;# Bank 43 VCCO - VADJ_1V8_FPGA - IO_L15N_T2L_N5_AD11N_43
-# set_property IOSTANDARD LVCMOS18 [get_ports "FMCP_HSPC_Z_PRSNT_M2C_B_LS"] ;# Bank 43 VCCO - VADJ_1V8_FPGA - IO_L15N_T2L_N5_AD11N_43
-# set_property PACKAGE_PIN AL29 [get_ports "FMC_VADJ_ON_LS"] ;# Bank 43 VCCO - VADJ_1V8_FPGA - IO_L15P_T2L_N4_AD11P_43
-# set_property IOSTANDARD LVCMOS18 [get_ports "FMC_VADJ_ON_LS"] ;# Bank 43 VCCO - VADJ_1V8_FPGA - IO_L15P_T2L_N4_AD11P_43
-# set_property PACKAGE_PIN AK32 [get_ports "FMCP_HSPC_LA02_N"] ;# Bank 43 VCCO - VADJ_1V8_FPGA - IO_L14N_T2L_N3_GC_43
-# set_property IOSTANDARD LVDS [get_ports "FMCP_HSPC_LA02_N"] ;# Bank 43 VCCO - VADJ_1V8_FPGA - IO_L14N_T2L_N3_GC_43
-# set_property PACKAGE_PIN AJ32 [get_ports "FMCP_HSPC_LA02_P"] ;# Bank 43 VCCO - VADJ_1V8_FPGA - IO_L14P_T2L_N2_GC_43
-# set_property IOSTANDARD LVDS [get_ports "FMCP_HSPC_LA02_P"] ;# Bank 43 VCCO - VADJ_1V8_FPGA - IO_L14P_T2L_N2_GC_43
-# set_property PACKAGE_PIN AM32 [get_ports "FMCP_HSPC_CLK0_M2C_N"] ;# Bank 43 VCCO - VADJ_1V8_FPGA - IO_L13N_T2L_N1_GC_QBC_43
-# set_property IOSTANDARD LVDS [get_ports "FMCP_HSPC_CLK0_M2C_N"] ;# Bank 43 VCCO - VADJ_1V8_FPGA - IO_L13N_T2L_N1_GC_QBC_43
-# set_property PACKAGE_PIN AL32 [get_ports "FMCP_HSPC_CLK0_M2C_P"] ;# Bank 43 VCCO - VADJ_1V8_FPGA - IO_L13P_T2L_N0_GC_QBC_43
-# set_property IOSTANDARD LVDS [get_ports "FMCP_HSPC_CLK0_M2C_P"] ;# Bank 43 VCCO - VADJ_1V8_FPGA - IO_L13P_T2L_N0_GC_QBC_43
-# set_property PACKAGE_PIN AM34 [get_ports "FMCP_HSPC_PG_M2C_LS"] ;# Bank 43 VCCO - VADJ_1V8_FPGA - IO_L12N_T1U_N11_GC_43
-# set_property IOSTANDARD LVDS [get_ports "FMCP_HSPC_PG_M2C_LS"] ;# Bank 43 VCCO - VADJ_1V8_FPGA - IO_L12N_T1U_N11_GC_43
-# set_property PACKAGE_PIN AM33 [get_ports "FMCP_HSPC_H_PRSNT_M2C_B_LS"] ;# Bank 43 VCCO - VADJ_1V8_FPGA - IO_L12P_T1U_N10_GC_43
-# set_property IOSTANDARD LVCMOS18 [get_ports "FMCP_HSPC_H_PRSNT_M2C_B_LS"] ;# Bank 43 VCCO - VADJ_1V8_FPGA - IO_L12P_T1U_N10_GC_43
-# set_property PACKAGE_PIN AL34 [get_ports "FMCP_HSPC_REFCLK_M2C_N"] ;# Bank 43 VCCO - VADJ_1V8_FPGA - IO_L11N_T1U_N9_GC_43
-# set_property IOSTANDARD LVDS [get_ports "FMCP_HSPC_REFCLK_M2C_N"] ;# Bank 43 VCCO - VADJ_1V8_FPGA - IO_L11N_T1U_N9_GC_43
-# set_property PACKAGE_PIN AK34 [get_ports "FMCP_HSPC_REFCLK_M2C_P"] ;# Bank 43 VCCO - VADJ_1V8_FPGA - IO_L11P_T1U_N8_GC_43
-# set_property IOSTANDARD LVDS [get_ports "FMCP_HSPC_REFCLK_M2C_P"] ;# Bank 43 VCCO - VADJ_1V8_FPGA - IO_L11P_T1U_N8_GC_43
-# set_property PACKAGE_PIN AP33 [get_ports "FMCP_HSPC_REFCLK_C2M_N"] ;# Bank 43 VCCO - VADJ_1V8_FPGA - IO_L10N_T1U_N7_QBC_AD4N_43
-# set_property IOSTANDARD LVDS [get_ports "FMCP_HSPC_REFCLK_C2M_N"] ;# Bank 43 VCCO - VADJ_1V8_FPGA - IO_L10N_T1U_N7_QBC_AD4N_43
-# set_property PACKAGE_PIN AN33 [get_ports "FMCP_HSPC_REFCLK_C2M_P"] ;# Bank 43 VCCO - VADJ_1V8_FPGA - IO_L10P_T1U_N6_QBC_AD4P_43
-# set_property IOSTANDARD LVDS [get_ports "FMCP_HSPC_REFCLK_C2M_P"] ;# Bank 43 VCCO - VADJ_1V8_FPGA - IO_L10P_T1U_N6_QBC_AD4P_43
-# set_property PACKAGE_PIN AN36 [get_ports "FMCP_HSPC_SYNC_M2C_N"] ;# Bank 43 VCCO - VADJ_1V8_FPGA - IO_L9N_T1L_N5_AD12N_43
-# set_property IOSTANDARD LVDS [get_ports "FMCP_HSPC_SYNC_M2C_N"] ;# Bank 43 VCCO - VADJ_1V8_FPGA - IO_L9N_T1L_N5_AD12N_43
-# set_property PACKAGE_PIN AM36 [get_ports "FMCP_HSPC_SYNC_M2C_P"] ;# Bank 43 VCCO - VADJ_1V8_FPGA - IO_L9P_T1L_N4_AD12P_43
-# set_property IOSTANDARD LVDS [get_ports "FMCP_HSPC_SYNC_M2C_P"] ;# Bank 43 VCCO - VADJ_1V8_FPGA - IO_L9P_T1L_N4_AD12P_43
-# set_property PACKAGE_PIN AN35 [get_ports "FMCP_HSPC_SYNC_C2M_N"] ;# Bank 43 VCCO - VADJ_1V8_FPGA - IO_L8N_T1L_N3_AD5N_43
-# set_property IOSTANDARD LVDS [get_ports "FMCP_HSPC_SYNC_C2M_N"] ;# Bank 43 VCCO - VADJ_1V8_FPGA - IO_L8N_T1L_N3_AD5N_43
-# set_property PACKAGE_PIN AN34 [get_ports "FMCP_HSPC_SYNC_C2M_P"] ;# Bank 43 VCCO - VADJ_1V8_FPGA - IO_L8P_T1L_N2_AD5P_43
-# set_property IOSTANDARD LVDS [get_ports "FMCP_HSPC_SYNC_C2M_P"] ;# Bank 43 VCCO - VADJ_1V8_FPGA - IO_L8P_T1L_N2_AD5P_43
-# set_property PACKAGE_PIN AL36 [get_ports "FMCP_HSPC_LA00_CC_N"] ;# Bank 43 VCCO - VADJ_1V8_FPGA - IO_L7N_T1L_N1_QBC_AD13N_43
-# set_property IOSTANDARD LVDS [get_ports "FMCP_HSPC_LA00_CC_N"] ;# Bank 43 VCCO - VADJ_1V8_FPGA - IO_L7N_T1L_N1_QBC_AD13N_43
-# set_property PACKAGE_PIN AL35 [get_ports "FMCP_HSPC_LA00_CC_P"] ;# Bank 43 VCCO - VADJ_1V8_FPGA - IO_L7P_T1L_N0_QBC_AD13P_43
-# set_property IOSTANDARD LVDS [get_ports "FMCP_HSPC_LA00_CC_P"] ;# Bank 43 VCCO - VADJ_1V8_FPGA - IO_L7P_T1L_N0_QBC_AD13P_43
-# set_property PACKAGE_PIN AK35 [get_ports "VADJ_1V8_PGOOD_LS"] ;# Bank 43 VCCO - VADJ_1V8_FPGA - IO_T1U_N12_43
-# set_property IOSTANDARD LVCMOS18 [get_ports "VADJ_1V8_PGOOD_LS"] ;# Bank 43 VCCO - VADJ_1V8_FPGA - IO_T1U_N12_43
-# #set_property PACKAGE_PIN AR34 [get_ports "VRP_43"] ;# Bank 43 VCCO - VADJ_1V8_FPGA - IO_T0U_N12_VRP_43
-# #set_property IOSTANDARD LVCMOSxx [get_ports "VRP_43"] ;# Bank 43 VCCO - VADJ_1V8_FPGA - IO_T0U_N12_VRP_43
-# set_property PACKAGE_PIN AT37 [get_ports "FMCP_HSPC_LA04_N"] ;# Bank 43 VCCO - VADJ_1V8_FPGA - IO_L6N_T0U_N11_AD6N_43
-# set_property IOSTANDARD LVDS [get_ports "FMCP_HSPC_LA04_N"] ;# Bank 43 VCCO - VADJ_1V8_FPGA - IO_L6N_T0U_N11_AD6N_43
-# set_property PACKAGE_PIN AR37 [get_ports "FMCP_HSPC_LA04_P"] ;# Bank 43 VCCO - VADJ_1V8_FPGA - IO_L6P_T0U_N10_AD6P_43
-# set_property IOSTANDARD LVDS [get_ports "FMCP_HSPC_LA04_P"] ;# Bank 43 VCCO - VADJ_1V8_FPGA - IO_L6P_T0U_N10_AD6P_43
-# set_property PACKAGE_PIN AP37 [get_ports "FMCP_HSPC_LA07_N"] ;# Bank 43 VCCO - VADJ_1V8_FPGA - IO_L5N_T0U_N9_AD14N_43
-# set_property IOSTANDARD LVDS [get_ports "FMCP_HSPC_LA07_N"] ;# Bank 43 VCCO - VADJ_1V8_FPGA - IO_L5N_T0U_N9_AD14N_43
-# set_property PACKAGE_PIN AP36 [get_ports "FMCP_HSPC_LA07_P"] ;# Bank 43 VCCO - VADJ_1V8_FPGA - IO_L5P_T0U_N8_AD14P_43
-# set_property IOSTANDARD LVDS [get_ports "FMCP_HSPC_LA07_P"] ;# Bank 43 VCCO - VADJ_1V8_FPGA - IO_L5P_T0U_N8_AD14P_43
-# set_property PACKAGE_PIN AT40 [get_ports "FMCP_HSPC_LA03_N"] ;# Bank 43 VCCO - VADJ_1V8_FPGA - IO_L4N_T0U_N7_DBC_AD7N_43
-# set_property IOSTANDARD LVDS [get_ports "FMCP_HSPC_LA03_N"] ;# Bank 43 VCCO - VADJ_1V8_FPGA - IO_L4N_T0U_N7_DBC_AD7N_43
-# set_property PACKAGE_PIN AT39 [get_ports "FMCP_HSPC_LA03_P"] ;# Bank 43 VCCO - VADJ_1V8_FPGA - IO_L4P_T0U_N6_DBC_AD7P_43
-# set_property IOSTANDARD LVDS [get_ports "FMCP_HSPC_LA03_P"] ;# Bank 43 VCCO - VADJ_1V8_FPGA - IO_L4P_T0U_N6_DBC_AD7P_43
-# set_property PACKAGE_PIN AR35 [get_ports "FMCP_HSPC_LA10_N"] ;# Bank 43 VCCO - VADJ_1V8_FPGA - IO_L3N_T0L_N5_AD15N_43
-# set_property IOSTANDARD LVDS [get_ports "FMCP_HSPC_LA10_N"] ;# Bank 43 VCCO - VADJ_1V8_FPGA - IO_L3N_T0L_N5_AD15N_43
-# set_property PACKAGE_PIN AP35 [get_ports "FMCP_HSPC_LA10_P"] ;# Bank 43 VCCO - VADJ_1V8_FPGA - IO_L3P_T0L_N4_AD15P_43
-# set_property IOSTANDARD LVDS [get_ports "FMCP_HSPC_LA10_P"] ;# Bank 43 VCCO - VADJ_1V8_FPGA - IO_L3P_T0L_N4_AD15P_43
-# set_property PACKAGE_PIN AT36 [get_ports "FMCP_HSPC_LA06_N"] ;# Bank 43 VCCO - VADJ_1V8_FPGA - IO_L2N_T0L_N3_43
-# set_property IOSTANDARD LVDS [get_ports "FMCP_HSPC_LA06_N"] ;# Bank 43 VCCO - VADJ_1V8_FPGA - IO_L2N_T0L_N3_43
-# set_property PACKAGE_PIN AT35 [get_ports "FMCP_HSPC_LA06_P"] ;# Bank 43 VCCO - VADJ_1V8_FPGA - IO_L2P_T0L_N2_43
-# set_property IOSTANDARD LVDS [get_ports "FMCP_HSPC_LA06_P"] ;# Bank 43 VCCO - VADJ_1V8_FPGA - IO_L2P_T0L_N2_43
-# set_property PACKAGE_PIN AR38 [get_ports "FMCP_HSPC_LA05_N"] ;# Bank 43 VCCO - VADJ_1V8_FPGA - IO_L1N_T0L_N1_DBC_43
-# set_property IOSTANDARD LVDS [get_ports "FMCP_HSPC_LA05_N"] ;# Bank 43 VCCO - VADJ_1V8_FPGA - IO_L1N_T0L_N1_DBC_43
-# set_property PACKAGE_PIN AP38 [get_ports "FMCP_HSPC_LA05_P"] ;# Bank 43 VCCO - VADJ_1V8_FPGA - IO_L1P_T0L_N0_DBC_43
-# set_property IOSTANDARD LVDS [get_ports "FMCP_HSPC_LA05_P"] ;# Bank 43 VCCO - VADJ_1V8_FPGA - IO_L1P_T0L_N0_DBC_43
-# #Other net PACKAGE_PIN AJ29 - VREF_43 Bank 43 - VREF_43
-# set_property PACKAGE_PIN AV39 [get_ports "DDR4_C2_DQ63"] ;# Bank 42 VCCO - VCC1V2_FPGA - IO_L24N_T3U_N11_42
-# set_property IOSTANDARD POD12 [get_ports "DDR4_C2_DQ63"] ;# Bank 42 VCCO - VCC1V2_FPGA - IO_L24N_T3U_N11_42
-# set_property PACKAGE_PIN AV38 [get_ports "DDR4_C2_DQ62"] ;# Bank 42 VCCO - VCC1V2_FPGA - IO_L24P_T3U_N10_42
-# set_property IOSTANDARD POD12 [get_ports "DDR4_C2_DQ62"] ;# Bank 42 VCCO - VCC1V2_FPGA - IO_L24P_T3U_N10_42
-# set_property PACKAGE_PIN AU39 [get_ports "DDR4_C2_DQ61"] ;# Bank 42 VCCO - VCC1V2_FPGA - IO_L23N_T3U_N9_42
-# set_property IOSTANDARD POD12 [get_ports "DDR4_C2_DQ61"] ;# Bank 42 VCCO - VCC1V2_FPGA - IO_L23N_T3U_N9_42
-# set_property PACKAGE_PIN AU38 [get_ports "DDR4_C2_DQ60"] ;# Bank 42 VCCO - VCC1V2_FPGA - IO_L23P_T3U_N8_42
-# set_property IOSTANDARD POD12 [get_ports "DDR4_C2_DQ60"] ;# Bank 42 VCCO - VCC1V2_FPGA - IO_L23P_T3U_N8_42
-# set_property PACKAGE_PIN AW38 [get_ports "DDR4_C2_DQS7_C"] ;# Bank 42 VCCO - VCC1V2_FPGA - IO_L22N_T3U_N7_DBC_AD0N_42
-# set_property IOSTANDARD DIFF_POD12 [get_ports "DDR4_C2_DQS7_C"] ;# Bank 42 VCCO - VCC1V2_FPGA - IO_L22N_T3U_N7_DBC_AD0N_42
-# set_property PACKAGE_PIN AW37 [get_ports "DDR4_C2_DQS7_T"] ;# Bank 42 VCCO - VCC1V2_FPGA - IO_L22P_T3U_N6_DBC_AD0P_42
-# set_property IOSTANDARD DIFF_POD12 [get_ports "DDR4_C2_DQS7_T"] ;# Bank 42 VCCO - VCC1V2_FPGA - IO_L22P_T3U_N6_DBC_AD0P_42
-# set_property PACKAGE_PIN AV40 [get_ports "DDR4_C2_DQ59"] ;# Bank 42 VCCO - VCC1V2_FPGA - IO_L21N_T3L_N5_AD8N_42
-# set_property IOSTANDARD POD12 [get_ports "DDR4_C2_DQ59"] ;# Bank 42 VCCO - VCC1V2_FPGA - IO_L21N_T3L_N5_AD8N_42
-# set_property PACKAGE_PIN AU40 [get_ports "DDR4_C2_DQ58"] ;# Bank 42 VCCO - VCC1V2_FPGA - IO_L21P_T3L_N4_AD8P_42
-# set_property IOSTANDARD POD12 [get_ports "DDR4_C2_DQ58"] ;# Bank 42 VCCO - VCC1V2_FPGA - IO_L21P_T3L_N4_AD8P_42
-# set_property PACKAGE_PIN AW36 [get_ports "DDR4_C2_DQ57"] ;# Bank 42 VCCO - VCC1V2_FPGA - IO_L20N_T3L_N3_AD1N_42
-# set_property IOSTANDARD POD12 [get_ports "DDR4_C2_DQ57"] ;# Bank 42 VCCO - VCC1V2_FPGA - IO_L20N_T3L_N3_AD1N_42
-# set_property PACKAGE_PIN AW35 [get_ports "DDR4_C2_DQ56"] ;# Bank 42 VCCO - VCC1V2_FPGA - IO_L20P_T3L_N2_AD1P_42
-# set_property IOSTANDARD POD12 [get_ports "DDR4_C2_DQ56"] ;# Bank 42 VCCO - VCC1V2_FPGA - IO_L20P_T3L_N2_AD1P_42
-# set_property PACKAGE_PIN AV36 [get_ports "GPIO_LED6"] ;# Bank 42 VCCO - VCC1V2_FPGA - IO_L19N_T3L_N1_DBC_AD9N_42
-# set_property IOSTANDARD LVCMOS12 [get_ports "GPIO_LED6"] ;# Bank 42 VCCO - VCC1V2_FPGA - IO_L19N_T3L_N1_DBC_AD9N_42
-# set_property PACKAGE_PIN AV35 [get_ports "DDR4_C2_DM7"] ;# Bank 42 VCCO - VCC1V2_FPGA - IO_L19P_T3L_N0_DBC_AD9P_42
-# set_property IOSTANDARD POD12 [get_ports "DDR4_C2_DM7"] ;# Bank 42 VCCO - VCC1V2_FPGA - IO_L19P_T3L_N0_DBC_AD9P_42
-# set_property PACKAGE_PIN AU37 [get_ports "GPIO_LED5"] ;# Bank 42 VCCO - VCC1V2_FPGA - IO_T3U_N12_42
-# set_property IOSTANDARD LVCMOS12 [get_ports "GPIO_LED5"] ;# Bank 42 VCCO - VCC1V2_FPGA - IO_T3U_N12_42
-# set_property PACKAGE_PIN AY35 [get_ports "DDR4_C2_TEN"] ;# Bank 42 VCCO - VCC1V2_FPGA - IO_T2U_N12_42
-# set_property IOSTANDARD POD12 [get_ports "DDR4_C2_TEN"] ;# Bank 42 VCCO - VCC1V2_FPGA - IO_T2U_N12_42
-# set_property PACKAGE_PIN AY39 [get_ports "DDR4_C2_DQ55"] ;# Bank 42 VCCO - VCC1V2_FPGA - IO_L18N_T2U_N11_AD2N_42
-# set_property IOSTANDARD POD12 [get_ports "DDR4_C2_DQ55"] ;# Bank 42 VCCO - VCC1V2_FPGA - IO_L18N_T2U_N11_AD2N_42
-# set_property PACKAGE_PIN AY38 [get_ports "DDR4_C2_DQ54"] ;# Bank 42 VCCO - VCC1V2_FPGA - IO_L18P_T2U_N10_AD2P_42
-# set_property IOSTANDARD POD12 [get_ports "DDR4_C2_DQ54"] ;# Bank 42 VCCO - VCC1V2_FPGA - IO_L18P_T2U_N10_AD2P_42
-# set_property PACKAGE_PIN AY40 [get_ports "DDR4_C2_DQ53"] ;# Bank 42 VCCO - VCC1V2_FPGA - IO_L17N_T2U_N9_AD10N_42
-# set_property IOSTANDARD POD12 [get_ports "DDR4_C2_DQ53"] ;# Bank 42 VCCO - VCC1V2_FPGA - IO_L17N_T2U_N9_AD10N_42
-# set_property PACKAGE_PIN AW40 [get_ports "DDR4_C2_DQ52"] ;# Bank 42 VCCO - VCC1V2_FPGA - IO_L17P_T2U_N8_AD10P_42
-# set_property IOSTANDARD POD12 [get_ports "DDR4_C2_DQ52"] ;# Bank 42 VCCO - VCC1V2_FPGA - IO_L17P_T2U_N8_AD10P_42
-# set_property PACKAGE_PIN BA36 [get_ports "DDR4_C2_DQS6_C"] ;# Bank 42 VCCO - VCC1V2_FPGA - IO_L16N_T2U_N7_QBC_AD3N_42
-# set_property IOSTANDARD DIFF_POD12 [get_ports "DDR4_C2_DQS6_C"] ;# Bank 42 VCCO - VCC1V2_FPGA - IO_L16N_T2U_N7_QBC_AD3N_42
-# set_property PACKAGE_PIN BA35 [get_ports "DDR4_C2_DQS6_T"] ;# Bank 42 VCCO - VCC1V2_FPGA - IO_L16P_T2U_N6_QBC_AD3P_42
-# set_property IOSTANDARD DIFF_POD12 [get_ports "DDR4_C2_DQS6_T"] ;# Bank 42 VCCO - VCC1V2_FPGA - IO_L16P_T2U_N6_QBC_AD3P_42
-# set_property PACKAGE_PIN BA40 [get_ports "DDR4_C2_DQ51"] ;# Bank 42 VCCO - VCC1V2_FPGA - IO_L15N_T2L_N5_AD11N_42
-# set_property IOSTANDARD POD12 [get_ports "DDR4_C2_DQ51"] ;# Bank 42 VCCO - VCC1V2_FPGA - IO_L15N_T2L_N5_AD11N_42
-# set_property PACKAGE_PIN BA39 [get_ports "DDR4_C2_DQ50"] ;# Bank 42 VCCO - VCC1V2_FPGA - IO_L15P_T2L_N4_AD11P_42
-# set_property IOSTANDARD POD12 [get_ports "DDR4_C2_DQ50"] ;# Bank 42 VCCO - VCC1V2_FPGA - IO_L15P_T2L_N4_AD11P_42
-# set_property PACKAGE_PIN BB37 [get_ports "DDR4_C2_DQ49"] ;# Bank 42 VCCO - VCC1V2_FPGA - IO_L14N_T2L_N3_GC_42
-# set_property IOSTANDARD POD12 [get_ports "DDR4_C2_DQ49"] ;# Bank 42 VCCO - VCC1V2_FPGA - IO_L14N_T2L_N3_GC_42
-# set_property PACKAGE_PIN BB36 [get_ports "DDR4_C2_DQ48"] ;# Bank 42 VCCO - VCC1V2_FPGA - IO_L14P_T2L_N2_GC_42
-# set_property IOSTANDARD POD12 [get_ports "DDR4_C2_DQ48"] ;# Bank 42 VCCO - VCC1V2_FPGA - IO_L14P_T2L_N2_GC_42
-# set_property PACKAGE_PIN BA37 [get_ports "GPIO_LED7"] ;# Bank 42 VCCO - VCC1V2_FPGA - IO_L13N_T2L_N1_GC_QBC_42
-# set_property IOSTANDARD LVCMOS12 [get_ports "GPIO_LED7"] ;# Bank 42 VCCO - VCC1V2_FPGA - IO_L13N_T2L_N1_GC_QBC_42
-# set_property PACKAGE_PIN AY37 [get_ports "DDR4_C2_DM6"] ;# Bank 42 VCCO - VCC1V2_FPGA - IO_L13P_T2L_N0_GC_QBC_42
-# set_property IOSTANDARD POD12 [get_ports "DDR4_C2_DM6"] ;# Bank 42 VCCO - VCC1V2_FPGA - IO_L13P_T2L_N0_GC_QBC_42
-# set_property PACKAGE_PIN BD38 [get_ports "DDR4_C2_DQ47"] ;# Bank 42 VCCO - VCC1V2_FPGA - IO_L12N_T1U_N11_GC_42
-# set_property IOSTANDARD POD12 [get_ports "DDR4_C2_DQ47"] ;# Bank 42 VCCO - VCC1V2_FPGA - IO_L12N_T1U_N11_GC_42
-# set_property PACKAGE_PIN BC38 [get_ports "DDR4_C2_DQ46"] ;# Bank 42 VCCO - VCC1V2_FPGA - IO_L12P_T1U_N10_GC_42
-# set_property IOSTANDARD POD12 [get_ports "DDR4_C2_DQ46"] ;# Bank 42 VCCO - VCC1V2_FPGA - IO_L12P_T1U_N10_GC_42
-# set_property PACKAGE_PIN BB39 [get_ports "DDR4_C2_DQ45"] ;# Bank 42 VCCO - VCC1V2_FPGA - IO_L11N_T1U_N9_GC_42
-# set_property IOSTANDARD POD12 [get_ports "DDR4_C2_DQ45"] ;# Bank 42 VCCO - VCC1V2_FPGA - IO_L11N_T1U_N9_GC_42
-# set_property PACKAGE_PIN BB38 [get_ports "DDR4_C2_DQ44"] ;# Bank 42 VCCO - VCC1V2_FPGA - IO_L11P_T1U_N8_GC_42
-# set_property IOSTANDARD POD12 [get_ports "DDR4_C2_DQ44"] ;# Bank 42 VCCO - VCC1V2_FPGA - IO_L11P_T1U_N8_GC_42
-# set_property PACKAGE_PIN BF39 [get_ports "DDR4_C2_DQS5_C"] ;# Bank 42 VCCO - VCC1V2_FPGA - IO_L10N_T1U_N7_QBC_AD4N_42
-# set_property IOSTANDARD DIFF_POD12 [get_ports "DDR4_C2_DQS5_C"] ;# Bank 42 VCCO - VCC1V2_FPGA - IO_L10N_T1U_N7_QBC_AD4N_42
-# set_property PACKAGE_PIN BE39 [get_ports "DDR4_C2_DQS5_T"] ;# Bank 42 VCCO - VCC1V2_FPGA - IO_L10P_T1U_N6_QBC_AD4P_42
-# set_property IOSTANDARD DIFF_POD12 [get_ports "DDR4_C2_DQS5_T"] ;# Bank 42 VCCO - VCC1V2_FPGA - IO_L10P_T1U_N6_QBC_AD4P_42
-# set_property PACKAGE_PIN BD40 [get_ports "DDR4_C2_DQ43"] ;# Bank 42 VCCO - VCC1V2_FPGA - IO_L9N_T1L_N5_AD12N_42
-# set_property IOSTANDARD POD12 [get_ports "DDR4_C2_DQ43"] ;# Bank 42 VCCO - VCC1V2_FPGA - IO_L9N_T1L_N5_AD12N_42
-# set_property PACKAGE_PIN BC39 [get_ports "DDR4_C2_DQ42"] ;# Bank 42 VCCO - VCC1V2_FPGA - IO_L9P_T1L_N4_AD12P_42
-# set_property IOSTANDARD POD12 [get_ports "DDR4_C2_DQ42"] ;# Bank 42 VCCO - VCC1V2_FPGA - IO_L9P_T1L_N4_AD12P_42
-# set_property PACKAGE_PIN BE38 [get_ports "DDR4_C2_DQ41"] ;# Bank 42 VCCO - VCC1V2_FPGA - IO_L8N_T1L_N3_AD5N_42
-# set_property IOSTANDARD POD12 [get_ports "DDR4_C2_DQ41"] ;# Bank 42 VCCO - VCC1V2_FPGA - IO_L8N_T1L_N3_AD5N_42
-# set_property PACKAGE_PIN BD37 [get_ports "DDR4_C2_DQ40"] ;# Bank 42 VCCO - VCC1V2_FPGA - IO_L8P_T1L_N2_AD5P_42
-# set_property IOSTANDARD POD12 [get_ports "DDR4_C2_DQ40"] ;# Bank 42 VCCO - VCC1V2_FPGA - IO_L8P_T1L_N2_AD5P_42
-# set_property PACKAGE_PIN BF40 [get_ports "MAXIM_CABLE_LS_B"] ;# Bank 42 VCCO - VCC1V2_FPGA - IO_L7N_T1L_N1_QBC_AD13N_42
-# set_property IOSTANDARD LVCMOS12 [get_ports "MAXIM_CABLE_LS_B"] ;# Bank 42 VCCO - VCC1V2_FPGA - IO_L7N_T1L_N1_QBC_AD13N_42
-# set_property PACKAGE_PIN BE40 [get_ports "DDR4_C2_DM5"] ;# Bank 42 VCCO - VCC1V2_FPGA - IO_L7P_T1L_N0_QBC_AD13P_42
-# set_property IOSTANDARD POD12 [get_ports "DDR4_C2_DM5"] ;# Bank 42 VCCO - VCC1V2_FPGA - IO_L7P_T1L_N0_QBC_AD13P_42
-# set_property PACKAGE_PIN BC40 [get_ports "FAN_OT_LS_B"] ;# Bank 42 VCCO - VCC1V2_FPGA - IO_T1U_N12_42
-# set_property IOSTANDARD LVCMOS12 [get_ports "FAN_OT_LS_B"] ;# Bank 42 VCCO - VCC1V2_FPGA - IO_T1U_N12_42
-# #set_property PACKAGE_PIN BB34 [get_ports "VRP_42"] ;# Bank 42 VCCO - VCC1V2_FPGA - IO_T0U_N12_VRP_42
-# #set_property IOSTANDARD LVCMOSxx [get_ports "VRP_42"] ;# Bank 42 VCCO - VCC1V2_FPGA - IO_T0U_N12_VRP_42
-# set_property PACKAGE_PIN BF37 [get_ports "DDR4_C2_DQ39"] ;# Bank 42 VCCO - VCC1V2_FPGA - IO_L6N_T0U_N11_AD6N_42
-# set_property IOSTANDARD POD12 [get_ports "DDR4_C2_DQ39"] ;# Bank 42 VCCO - VCC1V2_FPGA - IO_L6N_T0U_N11_AD6N_42
-# set_property PACKAGE_PIN BF36 [get_ports "DDR4_C2_DQ38"] ;# Bank 42 VCCO - VCC1V2_FPGA - IO_L6P_T0U_N10_AD6P_42
-# set_property IOSTANDARD POD12 [get_ports "DDR4_C2_DQ38"] ;# Bank 42 VCCO - VCC1V2_FPGA - IO_L6P_T0U_N10_AD6P_42
-# set_property PACKAGE_PIN BE37 [get_ports "DDR4_C2_DQ37"] ;# Bank 42 VCCO - VCC1V2_FPGA - IO_L5N_T0U_N9_AD14N_42
-# set_property IOSTANDARD POD12 [get_ports "DDR4_C2_DQ37"] ;# Bank 42 VCCO - VCC1V2_FPGA - IO_L5N_T0U_N9_AD14N_42
-# set_property PACKAGE_PIN BD36 [get_ports "DDR4_C2_DQ36"] ;# Bank 42 VCCO - VCC1V2_FPGA - IO_L5P_T0U_N8_AD14P_42
-# set_property IOSTANDARD POD12 [get_ports "DDR4_C2_DQ36"] ;# Bank 42 VCCO - VCC1V2_FPGA - IO_L5P_T0U_N8_AD14P_42
-# set_property PACKAGE_PIN BF35 [get_ports "DDR4_C2_DQS4_C"] ;# Bank 42 VCCO - VCC1V2_FPGA - IO_L4N_T0U_N7_DBC_AD7N_42
-# set_property IOSTANDARD DIFF_POD12 [get_ports "DDR4_C2_DQS4_C"] ;# Bank 42 VCCO - VCC1V2_FPGA - IO_L4N_T0U_N7_DBC_AD7N_42
-# set_property PACKAGE_PIN BE35 [get_ports "DDR4_C2_DQS4_T"] ;# Bank 42 VCCO - VCC1V2_FPGA - IO_L4P_T0U_N6_DBC_AD7P_42
-# set_property IOSTANDARD DIFF_POD12 [get_ports "DDR4_C2_DQS4_T"] ;# Bank 42 VCCO - VCC1V2_FPGA - IO_L4P_T0U_N6_DBC_AD7P_42
-# set_property PACKAGE_PIN BC36 [get_ports "DDR4_C2_DQ35"] ;# Bank 42 VCCO - VCC1V2_FPGA - IO_L3N_T0L_N5_AD15N_42
-# set_property IOSTANDARD POD12 [get_ports "DDR4_C2_DQ35"] ;# Bank 42 VCCO - VCC1V2_FPGA - IO_L3N_T0L_N5_AD15N_42
-# set_property PACKAGE_PIN BC35 [get_ports "DDR4_C2_DQ34"] ;# Bank 42 VCCO - VCC1V2_FPGA - IO_L3P_T0L_N4_AD15P_42
-# set_property IOSTANDARD POD12 [get_ports "DDR4_C2_DQ34"] ;# Bank 42 VCCO - VCC1V2_FPGA - IO_L3P_T0L_N4_AD15P_42
-# set_property PACKAGE_PIN BF34 [get_ports "DDR4_C2_DQ33"] ;# Bank 42 VCCO - VCC1V2_FPGA - IO_L2N_T0L_N3_42
-# set_property IOSTANDARD POD12 [get_ports "DDR4_C2_DQ33"] ;# Bank 42 VCCO - VCC1V2_FPGA - IO_L2N_T0L_N3_42
-# set_property PACKAGE_PIN BE34 [get_ports "DDR4_C2_DQ32"] ;# Bank 42 VCCO - VCC1V2_FPGA - IO_L2P_T0L_N2_42
-# set_property IOSTANDARD POD12 [get_ports "DDR4_C2_DQ32"] ;# Bank 42 VCCO - VCC1V2_FPGA - IO_L2P_T0L_N2_42
-# set_property PACKAGE_PIN BD35 [get_ports "DDR4_C2_RESET_B"] ;# Bank 42 VCCO - VCC1V2_FPGA - IO_L1N_T0L_N1_DBC_42
-# set_property IOSTANDARD LVCMOS12 [get_ports "DDR4_C2_RESET_B"] ;# Bank 42 VCCO - VCC1V2_FPGA - IO_L1N_T0L_N1_DBC_42
-# set_property PACKAGE_PIN BC34 [get_ports "DDR4_C2_DM4"] ;# Bank 42 VCCO - VCC1V2_FPGA - IO_L1P_T0L_N0_DBC_42
-# set_property IOSTANDARD POD12 [get_ports "DDR4_C2_DM4"] ;# Bank 42 VCCO - VCC1V2_FPGA - IO_L1P_T0L_N0_DBC_42
-# #Other net PACKAGE_PIN AU36 - 5N11683 Bank 42 - VREF_42
-# set_property PACKAGE_PIN AM27 [get_ports "DDR4_C2_A0"] ;# Bank 41 VCCO - VCC1V2_FPGA - IO_L24N_T3U_N11_41
-# set_property IOSTANDARD SSTL12 [get_ports "DDR4_C2_A0"] ;# Bank 41 VCCO - VCC1V2_FPGA - IO_L24N_T3U_N11_41
-# set_property PACKAGE_PIN AL27 [get_ports "DDR4_C2_A1"] ;# Bank 41 VCCO - VCC1V2_FPGA - IO_L24P_T3U_N10_41
-# set_property IOSTANDARD SSTL12 [get_ports "DDR4_C2_A1"] ;# Bank 41 VCCO - VCC1V2_FPGA - IO_L24P_T3U_N10_41
-# set_property PACKAGE_PIN AP26 [get_ports "DDR4_C2_A2"] ;# Bank 41 VCCO - VCC1V2_FPGA - IO_L23N_T3U_N9_41
-# set_property IOSTANDARD SSTL12 [get_ports "DDR4_C2_A2"] ;# Bank 41 VCCO - VCC1V2_FPGA - IO_L23N_T3U_N9_41
-# set_property PACKAGE_PIN AP25 [get_ports "DDR4_C2_A3"] ;# Bank 41 VCCO - VCC1V2_FPGA - IO_L23P_T3U_N8_41
-# set_property IOSTANDARD SSTL12 [get_ports "DDR4_C2_A3"] ;# Bank 41 VCCO - VCC1V2_FPGA - IO_L23P_T3U_N8_41
-# set_property PACKAGE_PIN AN28 [get_ports "DDR4_C2_A4"] ;# Bank 41 VCCO - VCC1V2_FPGA - IO_L22N_T3U_N7_DBC_AD0N_41
-# set_property IOSTANDARD SSTL12 [get_ports "DDR4_C2_A4"] ;# Bank 41 VCCO - VCC1V2_FPGA - IO_L22N_T3U_N7_DBC_AD0N_41
-# set_property PACKAGE_PIN AM28 [get_ports "DDR4_C2_A5"] ;# Bank 41 VCCO - VCC1V2_FPGA - IO_L22P_T3U_N6_DBC_AD0P_41
-# set_property IOSTANDARD SSTL12 [get_ports "DDR4_C2_A5"] ;# Bank 41 VCCO - VCC1V2_FPGA - IO_L22P_T3U_N6_DBC_AD0P_41
-# set_property PACKAGE_PIN AP28 [get_ports "DDR4_C2_A6"] ;# Bank 41 VCCO - VCC1V2_FPGA - IO_L21N_T3L_N5_AD8N_41
-# set_property IOSTANDARD SSTL12 [get_ports "DDR4_C2_A6"] ;# Bank 41 VCCO - VCC1V2_FPGA - IO_L21N_T3L_N5_AD8N_41
-# set_property PACKAGE_PIN AP27 [get_ports "DDR4_C2_A7"] ;# Bank 41 VCCO - VCC1V2_FPGA - IO_L21P_T3L_N4_AD8P_41
-# set_property IOSTANDARD SSTL12 [get_ports "DDR4_C2_A7"] ;# Bank 41 VCCO - VCC1V2_FPGA - IO_L21P_T3L_N4_AD8P_41
-# set_property PACKAGE_PIN AN26 [get_ports "DDR4_C2_A8"] ;# Bank 41 VCCO - VCC1V2_FPGA - IO_L20N_T3L_N3_AD1N_41
-# set_property IOSTANDARD SSTL12 [get_ports "DDR4_C2_A8"] ;# Bank 41 VCCO - VCC1V2_FPGA - IO_L20N_T3L_N3_AD1N_41
-# set_property PACKAGE_PIN AM26 [get_ports "DDR4_C2_A9"] ;# Bank 41 VCCO - VCC1V2_FPGA - IO_L20P_T3L_N2_AD1P_41
-# set_property IOSTANDARD SSTL12 [get_ports "DDR4_C2_A9"] ;# Bank 41 VCCO - VCC1V2_FPGA - IO_L20P_T3L_N2_AD1P_41
-# set_property PACKAGE_PIN AR28 [get_ports "DDR4_C2_A10"] ;# Bank 41 VCCO - VCC1V2_FPGA - IO_L19N_T3L_N1_DBC_AD9N_41
-# set_property IOSTANDARD SSTL12 [get_ports "DDR4_C2_A10"] ;# Bank 41 VCCO - VCC1V2_FPGA - IO_L19N_T3L_N1_DBC_AD9N_41
-# set_property PACKAGE_PIN AR27 [get_ports "DDR4_C2_A11"] ;# Bank 41 VCCO - VCC1V2_FPGA - IO_L19P_T3L_N0_DBC_AD9P_41
-# set_property IOSTANDARD SSTL12 [get_ports "DDR4_C2_A11"] ;# Bank 41 VCCO - VCC1V2_FPGA - IO_L19P_T3L_N0_DBC_AD9P_41
-# set_property PACKAGE_PIN AN25 [get_ports "DDR4_C2_ACT_B"] ;# Bank 41 VCCO - VCC1V2_FPGA - IO_T3U_N12_41
-# set_property IOSTANDARD SSTL12 [get_ports "DDR4_C2_ACT_B"] ;# Bank 41 VCCO - VCC1V2_FPGA - IO_T3U_N12_41
-# set_property PACKAGE_PIN AV25 [get_ports "DDR4_C2_A12"] ;# Bank 41 VCCO - VCC1V2_FPGA - IO_T2U_N12_41
-# set_property IOSTANDARD SSTL12 [get_ports "DDR4_C2_A12"] ;# Bank 41 VCCO - VCC1V2_FPGA - IO_T2U_N12_41
-# set_property PACKAGE_PIN AT25 [get_ports "DDR4_C2_A13"] ;# Bank 41 VCCO - VCC1V2_FPGA - IO_L18N_T2U_N11_AD2N_41
-# set_property IOSTANDARD SSTL12 [get_ports "DDR4_C2_A13"] ;# Bank 41 VCCO - VCC1V2_FPGA - IO_L18N_T2U_N11_AD2N_41
-# set_property PACKAGE_PIN AR25 [get_ports "DDR4_C2_BA0"] ;# Bank 41 VCCO - VCC1V2_FPGA - IO_L18P_T2U_N10_AD2P_41
-# set_property IOSTANDARD SSTL12 [get_ports "DDR4_C2_BA0"] ;# Bank 41 VCCO - VCC1V2_FPGA - IO_L18P_T2U_N10_AD2P_41
-# set_property PACKAGE_PIN AU28 [get_ports "DDR4_C2_BA1"] ;# Bank 41 VCCO - VCC1V2_FPGA - IO_L17N_T2U_N9_AD10N_41
-# set_property IOSTANDARD SSTL12 [get_ports "DDR4_C2_BA1"] ;# Bank 41 VCCO - VCC1V2_FPGA - IO_L17N_T2U_N9_AD10N_41
-# set_property PACKAGE_PIN AU27 [get_ports "DDR4_C2_BG0"] ;# Bank 41 VCCO - VCC1V2_FPGA - IO_L17P_T2U_N8_AD10P_41
-# set_property IOSTANDARD SSTL12 [get_ports "DDR4_C2_BG0"] ;# Bank 41 VCCO - VCC1V2_FPGA - IO_L17P_T2U_N8_AD10P_41
-# set_property PACKAGE_PIN AT27 [get_ports "DDR4_C2_CK_C"] ;# Bank 41 VCCO - VCC1V2_FPGA - IO_L16N_T2U_N7_QBC_AD3N_41
-# set_property IOSTANDARD DIFF_POD12 [get_ports "DDR4_C2_CK_C"] ;# Bank 41 VCCO - VCC1V2_FPGA - IO_L16N_T2U_N7_QBC_AD3N_41
-# set_property PACKAGE_PIN AT26 [get_ports "DDR4_C2_CK_T"] ;# Bank 41 VCCO - VCC1V2_FPGA - IO_L16P_T2U_N6_QBC_AD3P_41
-# set_property IOSTANDARD DIFF_POD12 [get_ports "DDR4_C2_CK_T"] ;# Bank 41 VCCO - VCC1V2_FPGA - IO_L16P_T2U_N6_QBC_AD3P_41
-# set_property PACKAGE_PIN AW28 [get_ports "DDR4_C2_CKE"] ;# Bank 41 VCCO - VCC1V2_FPGA - IO_L15N_T2L_N5_AD11N_41
-# set_property IOSTANDARD SSTL12 [get_ports "DDR4_C2_CKE"] ;# Bank 41 VCCO - VCC1V2_FPGA - IO_L15N_T2L_N5_AD11N_41
-# set_property PACKAGE_PIN AV28 [get_ports "DDR4_C2_A14_WE_B"] ;# Bank 41 VCCO - VCC1V2_FPGA - IO_L15P_T2L_N4_AD11P_41
-# set_property IOSTANDARD SSTL12 [get_ports "DDR4_C2_A14_WE_B"] ;# Bank 41 VCCO - VCC1V2_FPGA - IO_L15P_T2L_N4_AD11P_41
-# set_property PACKAGE_PIN AV26 [get_ports "DDR4_C2_A16_RAS_B"] ;# Bank 41 VCCO - VCC1V2_FPGA - IO_L14N_T2L_N3_GC_41
-# set_property IOSTANDARD SSTL12 [get_ports "DDR4_C2_A16_RAS_B"] ;# Bank 41 VCCO - VCC1V2_FPGA - IO_L14N_T2L_N3_GC_41
-# set_property PACKAGE_PIN AU26 [get_ports "DDR4_C2_A15_CAS_B"] ;# Bank 41 VCCO - VCC1V2_FPGA - IO_L14P_T2L_N2_GC_41
-# set_property IOSTANDARD SSTL12 [get_ports "DDR4_C2_A15_CAS_B"] ;# Bank 41 VCCO - VCC1V2_FPGA - IO_L14P_T2L_N2_GC_41
-# set_property PACKAGE_PIN AW27 [get_ports "250MHZ_CLK2_N"] ;# Bank 41 VCCO - VCC1V2_FPGA - IO_L13N_T2L_N1_GC_QBC_41
-# set_property IOSTANDARD DIFF_SSTL12 [get_ports "250MHZ_CLK2_N"] ;# Bank 41 VCCO - VCC1V2_FPGA - IO_L13N_T2L_N1_GC_QBC_41
-# set_property PACKAGE_PIN AW26 [get_ports "250MHZ_CLK2_P"] ;# Bank 41 VCCO - VCC1V2_FPGA - IO_L13P_T2L_N0_GC_QBC_41
-# set_property IOSTANDARD DIFF_SSTL12 [get_ports "250MHZ_CLK2_P"] ;# Bank 41 VCCO - VCC1V2_FPGA - IO_L13P_T2L_N0_GC_QBC_41
-# set_property PACKAGE_PIN BB27 [get_ports "DDR4_C2_DQ79"] ;# Bank 41 VCCO - VCC1V2_FPGA - IO_L12N_T1U_N11_GC_41
-# set_property IOSTANDARD POD12 [get_ports "DDR4_C2_DQ79"] ;# Bank 41 VCCO - VCC1V2_FPGA - IO_L12N_T1U_N11_GC_41
-# set_property PACKAGE_PIN BA27 [get_ports "DDR4_C2_DQ78"] ;# Bank 41 VCCO - VCC1V2_FPGA - IO_L12P_T1U_N10_GC_41
-# set_property IOSTANDARD POD12 [get_ports "DDR4_C2_DQ78"] ;# Bank 41 VCCO - VCC1V2_FPGA - IO_L12P_T1U_N10_GC_41
-# set_property PACKAGE_PIN AY28 [get_ports "DDR4_C2_DQ77"] ;# Bank 41 VCCO - VCC1V2_FPGA - IO_L11N_T1U_N9_GC_41
-# set_property IOSTANDARD POD12 [get_ports "DDR4_C2_DQ77"] ;# Bank 41 VCCO - VCC1V2_FPGA - IO_L11N_T1U_N9_GC_41
-# set_property PACKAGE_PIN AY27 [get_ports "DDR4_C2_DQ76"] ;# Bank 41 VCCO - VCC1V2_FPGA - IO_L11P_T1U_N8_GC_41
-# set_property IOSTANDARD POD12 [get_ports "DDR4_C2_DQ76"] ;# Bank 41 VCCO - VCC1V2_FPGA - IO_L11P_T1U_N8_GC_41
-# set_property PACKAGE_PIN BB26 [get_ports "DDR4_C2_DQS9_C"] ;# Bank 41 VCCO - VCC1V2_FPGA - IO_L10N_T1U_N7_QBC_AD4N_41
-# set_property IOSTANDARD DIFF_POD12 [get_ports "DDR4_C2_DQS9_C"] ;# Bank 41 VCCO - VCC1V2_FPGA - IO_L10N_T1U_N7_QBC_AD4N_41
-# set_property PACKAGE_PIN BA26 [get_ports "DDR4_C2_DQS9_T"] ;# Bank 41 VCCO - VCC1V2_FPGA - IO_L10P_T1U_N6_QBC_AD4P_41
-# set_property IOSTANDARD DIFF_POD12 [get_ports "DDR4_C2_DQS9_T"] ;# Bank 41 VCCO - VCC1V2_FPGA - IO_L10P_T1U_N6_QBC_AD4P_41
-# set_property PACKAGE_PIN BC28 [get_ports "DDR4_C2_DQ75"] ;# Bank 41 VCCO - VCC1V2_FPGA - IO_L9N_T1L_N5_AD12N_41
-# set_property IOSTANDARD POD12 [get_ports "DDR4_C2_DQ75"] ;# Bank 41 VCCO - VCC1V2_FPGA - IO_L9N_T1L_N5_AD12N_41
-# set_property PACKAGE_PIN BB28 [get_ports "DDR4_C2_DQ74"] ;# Bank 41 VCCO - VCC1V2_FPGA - IO_L9P_T1L_N4_AD12P_41
-# set_property IOSTANDARD POD12 [get_ports "DDR4_C2_DQ74"] ;# Bank 41 VCCO - VCC1V2_FPGA - IO_L9P_T1L_N4_AD12P_41
-# set_property PACKAGE_PIN BC26 [get_ports "DDR4_C2_DQ73"] ;# Bank 41 VCCO - VCC1V2_FPGA - IO_L8N_T1L_N3_AD5N_41
-# set_property IOSTANDARD POD12 [get_ports "DDR4_C2_DQ73"] ;# Bank 41 VCCO - VCC1V2_FPGA - IO_L8N_T1L_N3_AD5N_41
-# set_property PACKAGE_PIN BC25 [get_ports "DDR4_C2_DQ72"] ;# Bank 41 VCCO - VCC1V2_FPGA - IO_L8P_T1L_N2_AD5P_41
-# set_property IOSTANDARD POD12 [get_ports "DDR4_C2_DQ72"] ;# Bank 41 VCCO - VCC1V2_FPGA - IO_L8P_T1L_N2_AD5P_41
-# set_property PACKAGE_PIN BB29 [get_ports "DDR4_C2_ODT"] ;# Bank 41 VCCO - VCC1V2_FPGA - IO_L7N_T1L_N1_QBC_AD13N_41
-# set_property IOSTANDARD SSTL12 [get_ports "DDR4_C2_ODT"] ;# Bank 41 VCCO - VCC1V2_FPGA - IO_L7N_T1L_N1_QBC_AD13N_41
-# set_property PACKAGE_PIN BA29 [get_ports "DDR4_C2_DM9"] ;# Bank 41 VCCO - VCC1V2_FPGA - IO_L7P_T1L_N0_QBC_AD13P_41
-# set_property IOSTANDARD SSTL12 [get_ports "DDR4_C2_DM9"] ;# Bank 41 VCCO - VCC1V2_FPGA - IO_L7P_T1L_N0_QBC_AD13P_41
-# set_property PACKAGE_PIN AY29 [get_ports "DDR4_C2_CS_B"] ;# Bank 41 VCCO - VCC1V2_FPGA - IO_T1U_N12_41
-# set_property IOSTANDARD SSTL12 [get_ports "DDR4_C2_CS_B"] ;# Bank 41 VCCO - VCC1V2_FPGA - IO_T1U_N12_41
-# #set_property PACKAGE_PIN BC29 [get_ports "VRP_41"] ;# Bank 41 VCCO - VCC1V2_FPGA - IO_T0U_N12_VRP_41
-# #set_property IOSTANDARD LVCMOSxx [get_ports "VRP_41"] ;# Bank 41 VCCO - VCC1V2_FPGA - IO_T0U_N12_VRP_41
-# set_property PACKAGE_PIN BD26 [get_ports "DDR4_C2_DQ71"] ;# Bank 41 VCCO - VCC1V2_FPGA - IO_L6N_T0U_N11_AD6N_41
-# set_property IOSTANDARD POD12 [get_ports "DDR4_C2_DQ71"] ;# Bank 41 VCCO - VCC1V2_FPGA - IO_L6N_T0U_N11_AD6N_41
-# set_property PACKAGE_PIN BD25 [get_ports "DDR4_C2_DQ70"] ;# Bank 41 VCCO - VCC1V2_FPGA - IO_L6P_T0U_N10_AD6P_41
-# set_property IOSTANDARD POD12 [get_ports "DDR4_C2_DQ70"] ;# Bank 41 VCCO - VCC1V2_FPGA - IO_L6P_T0U_N10_AD6P_41
-# set_property PACKAGE_PIN BE27 [get_ports "DDR4_C2_DQ69"] ;# Bank 41 VCCO - VCC1V2_FPGA - IO_L5N_T0U_N9_AD14N_41
-# set_property IOSTANDARD POD12 [get_ports "DDR4_C2_DQ69"] ;# Bank 41 VCCO - VCC1V2_FPGA - IO_L5N_T0U_N9_AD14N_41
-# set_property PACKAGE_PIN BD27 [get_ports "DDR4_C2_DQ68"] ;# Bank 41 VCCO - VCC1V2_FPGA - IO_L5P_T0U_N8_AD14P_41
-# set_property IOSTANDARD POD12 [get_ports "DDR4_C2_DQ68"] ;# Bank 41 VCCO - VCC1V2_FPGA - IO_L5P_T0U_N8_AD14P_41
-# set_property PACKAGE_PIN BF25 [get_ports "DDR4_C2_DQS8_C"] ;# Bank 41 VCCO - VCC1V2_FPGA - IO_L4N_T0U_N7_DBC_AD7N_41
-# set_property IOSTANDARD DIFF_POD12 [get_ports "DDR4_C2_DQS8_C"] ;# Bank 41 VCCO - VCC1V2_FPGA - IO_L4N_T0U_N7_DBC_AD7N_41
-# set_property PACKAGE_PIN BE25 [get_ports "DDR4_C2_DQS8_T"] ;# Bank 41 VCCO - VCC1V2_FPGA - IO_L4P_T0U_N6_DBC_AD7P_41
-# set_property IOSTANDARD DIFF_POD12 [get_ports "DDR4_C2_DQS8_T"] ;# Bank 41 VCCO - VCC1V2_FPGA - IO_L4P_T0U_N6_DBC_AD7P_41
-# set_property PACKAGE_PIN BE28 [get_ports "DDR4_C2_DQ67"] ;# Bank 41 VCCO - VCC1V2_FPGA - IO_L3N_T0L_N5_AD15N_41
-# set_property IOSTANDARD POD12 [get_ports "DDR4_C2_DQ67"] ;# Bank 41 VCCO - VCC1V2_FPGA - IO_L3N_T0L_N5_AD15N_41
-# set_property PACKAGE_PIN BD28 [get_ports "DDR4_C2_DQ66"] ;# Bank 41 VCCO - VCC1V2_FPGA - IO_L3P_T0L_N4_AD15P_41
-# set_property IOSTANDARD POD12 [get_ports "DDR4_C2_DQ66"] ;# Bank 41 VCCO - VCC1V2_FPGA - IO_L3P_T0L_N4_AD15P_41
-# set_property PACKAGE_PIN BF27 [get_ports "DDR4_C2_DQ65"] ;# Bank 41 VCCO - VCC1V2_FPGA - IO_L2N_T0L_N3_41
-# set_property IOSTANDARD POD12 [get_ports "DDR4_C2_DQ65"] ;# Bank 41 VCCO - VCC1V2_FPGA - IO_L2N_T0L_N3_41
-# set_property PACKAGE_PIN BF26 [get_ports "DDR4_C2_DQ64"] ;# Bank 41 VCCO - VCC1V2_FPGA - IO_L2P_T0L_N2_41
-# set_property IOSTANDARD POD12 [get_ports "DDR4_C2_DQ64"] ;# Bank 41 VCCO - VCC1V2_FPGA - IO_L2P_T0L_N2_41
-# set_property PACKAGE_PIN BF29 [get_ports "DDR4_C2_PAR"] ;# Bank 41 VCCO - VCC1V2_FPGA - IO_L1N_T0L_N1_DBC_41
-# set_property IOSTANDARD POD12 [get_ports "DDR4_C2_PAR"] ;# Bank 41 VCCO - VCC1V2_FPGA - IO_L1N_T0L_N1_DBC_41
-# set_property PACKAGE_PIN BE29 [get_ports "DDR4_C2_DM8"] ;# Bank 41 VCCO - VCC1V2_FPGA - IO_L1P_T0L_N0_DBC_41
-# set_property IOSTANDARD POD12 [get_ports "DDR4_C2_DM8"] ;# Bank 41 VCCO - VCC1V2_FPGA - IO_L1P_T0L_N0_DBC_41
-# #Other net PACKAGE_PIN AL26 - 6N5608 Bank 41 - VREF_41
-# set_property PACKAGE_PIN AN31 [get_ports "DDR4_C2_DQ31"] ;# Bank 40 VCCO - VCC1V2_FPGA - IO_L24N_T3U_N11_40
-# set_property IOSTANDARD POD12 [get_ports "DDR4_C2_DQ31"] ;# Bank 40 VCCO - VCC1V2_FPGA - IO_L24N_T3U_N11_40
-# set_property PACKAGE_PIN AN30 [get_ports "DDR4_C2_DQ30"] ;# Bank 40 VCCO - VCC1V2_FPGA - IO_L24P_T3U_N10_40
-# set_property IOSTANDARD POD12 [get_ports "DDR4_C2_DQ30"] ;# Bank 40 VCCO - VCC1V2_FPGA - IO_L24P_T3U_N10_40
-# set_property PACKAGE_PIN AR30 [get_ports "DDR4_C2_DQ29"] ;# Bank 40 VCCO - VCC1V2_FPGA - IO_L23N_T3U_N9_40
-# set_property IOSTANDARD POD12 [get_ports "DDR4_C2_DQ29"] ;# Bank 40 VCCO - VCC1V2_FPGA - IO_L23N_T3U_N9_40
-# set_property PACKAGE_PIN AP30 [get_ports "DDR4_C2_DQ28"] ;# Bank 40 VCCO - VCC1V2_FPGA - IO_L23P_T3U_N8_40
-# set_property IOSTANDARD POD12 [get_ports "DDR4_C2_DQ28"] ;# Bank 40 VCCO - VCC1V2_FPGA - IO_L23P_T3U_N8_40
-# set_property PACKAGE_PIN AP32 [get_ports "DDR4_C2_DQS3_C"] ;# Bank 40 VCCO - VCC1V2_FPGA - IO_L22N_T3U_N7_DBC_AD0N_40
-# set_property IOSTANDARD DIFF_POD12 [get_ports "DDR4_C2_DQS3_C"] ;# Bank 40 VCCO - VCC1V2_FPGA - IO_L22N_T3U_N7_DBC_AD0N_40
-# set_property PACKAGE_PIN AP31 [get_ports "DDR4_C2_DQS3_T"] ;# Bank 40 VCCO - VCC1V2_FPGA - IO_L22P_T3U_N6_DBC_AD0P_40
-# set_property IOSTANDARD DIFF_POD12 [get_ports "DDR4_C2_DQS3_T"] ;# Bank 40 VCCO - VCC1V2_FPGA - IO_L22P_T3U_N6_DBC_AD0P_40
-# set_property PACKAGE_PIN AT30 [get_ports "DDR4_C2_DQ27"] ;# Bank 40 VCCO - VCC1V2_FPGA - IO_L21N_T3L_N5_AD8N_40
-# set_property IOSTANDARD POD12 [get_ports "DDR4_C2_DQ27"] ;# Bank 40 VCCO - VCC1V2_FPGA - IO_L21N_T3L_N5_AD8N_40
-# set_property PACKAGE_PIN AT29 [get_ports "DDR4_C2_DQ26"] ;# Bank 40 VCCO - VCC1V2_FPGA - IO_L21P_T3L_N4_AD8P_40
-# set_property IOSTANDARD POD12 [get_ports "DDR4_C2_DQ26"] ;# Bank 40 VCCO - VCC1V2_FPGA - IO_L21P_T3L_N4_AD8P_40
-# set_property PACKAGE_PIN AT34 [get_ports "DDR4_C2_DQ25"] ;# Bank 40 VCCO - VCC1V2_FPGA - IO_L20N_T3L_N3_AD1N_40
-# set_property IOSTANDARD POD12 [get_ports "DDR4_C2_DQ25"] ;# Bank 40 VCCO - VCC1V2_FPGA - IO_L20N_T3L_N3_AD1N_40
-# set_property PACKAGE_PIN AR33 [get_ports "DDR4_C2_DQ24"] ;# Bank 40 VCCO - VCC1V2_FPGA - IO_L20P_T3L_N2_AD1P_40
-# set_property IOSTANDARD POD12 [get_ports "DDR4_C2_DQ24"] ;# Bank 40 VCCO - VCC1V2_FPGA - IO_L20P_T3L_N2_AD1P_40
-# set_property PACKAGE_PIN AT32 [get_ports "GPIO_LED0"] ;# Bank 40 VCCO - VCC1V2_FPGA - IO_L19N_T3L_N1_DBC_AD9N_40
-# set_property IOSTANDARD LVCMOS12 [get_ports "GPIO_LED0"] ;# Bank 40 VCCO - VCC1V2_FPGA - IO_L19N_T3L_N1_DBC_AD9N_40
-# set_property PACKAGE_PIN AR32 [get_ports "DDR4_C2_DM3"] ;# Bank 40 VCCO - VCC1V2_FPGA - IO_L19P_T3L_N0_DBC_AD9P_40
-# set_property IOSTANDARD POD12 [get_ports "DDR4_C2_DM3"] ;# Bank 40 VCCO - VCC1V2_FPGA - IO_L19P_T3L_N0_DBC_AD9P_40
-# set_property PACKAGE_PIN AR29 [get_ports "DDR4_C2_ALERT_B"] ;# Bank 40 VCCO - VCC1V2_FPGA - IO_T3U_N12_40
-# set_property IOSTANDARD SSTL12 [get_ports "DDR4_C2_ALERT_B"] ;# Bank 40 VCCO - VCC1V2_FPGA - IO_T3U_N12_40
-# set_property PACKAGE_PIN AV34 [get_ports "GPIO_LED1"] ;# Bank 40 VCCO - VCC1V2_FPGA - IO_T2U_N12_40
-# set_property IOSTANDARD LVCMOS12 [get_ports "GPIO_LED1"] ;# Bank 40 VCCO - VCC1V2_FPGA - IO_T2U_N12_40
-# set_property PACKAGE_PIN AV31 [get_ports "DDR4_C2_DQ23"] ;# Bank 40 VCCO - VCC1V2_FPGA - IO_L18N_T2U_N11_AD2N_40
-# set_property IOSTANDARD POD12 [get_ports "DDR4_C2_DQ23"] ;# Bank 40 VCCO - VCC1V2_FPGA - IO_L18N_T2U_N11_AD2N_40
-# set_property PACKAGE_PIN AU31 [get_ports "DDR4_C2_DQ22"] ;# Bank 40 VCCO - VCC1V2_FPGA - IO_L18P_T2U_N10_AD2P_40
-# set_property IOSTANDARD POD12 [get_ports "DDR4_C2_DQ22"] ;# Bank 40 VCCO - VCC1V2_FPGA - IO_L18P_T2U_N10_AD2P_40
-# set_property PACKAGE_PIN AU32 [get_ports "DDR4_C2_DQ21"] ;# Bank 40 VCCO - VCC1V2_FPGA - IO_L17N_T2U_N9_AD10N_40
-# set_property IOSTANDARD POD12 [get_ports "DDR4_C2_DQ21"] ;# Bank 40 VCCO - VCC1V2_FPGA - IO_L17N_T2U_N9_AD10N_40
-# set_property PACKAGE_PIN AT31 [get_ports "DDR4_C2_DQ20"] ;# Bank 40 VCCO - VCC1V2_FPGA - IO_L17P_T2U_N8_AD10P_40
-# set_property IOSTANDARD POD12 [get_ports "DDR4_C2_DQ20"] ;# Bank 40 VCCO - VCC1V2_FPGA - IO_L17P_T2U_N8_AD10P_40
-# set_property PACKAGE_PIN AV29 [get_ports "DDR4_C2_DQS2_C"] ;# Bank 40 VCCO - VCC1V2_FPGA - IO_L16N_T2U_N7_QBC_AD3N_40
-# set_property IOSTANDARD DIFF_POD12 [get_ports "DDR4_C2_DQS2_C"] ;# Bank 40 VCCO - VCC1V2_FPGA - IO_L16N_T2U_N7_QBC_AD3N_40
-# set_property PACKAGE_PIN AU29 [get_ports "DDR4_C2_DQS2_T"] ;# Bank 40 VCCO - VCC1V2_FPGA - IO_L16P_T2U_N6_QBC_AD3P_40
-# set_property IOSTANDARD DIFF_POD12 [get_ports "DDR4_C2_DQS2_T"] ;# Bank 40 VCCO - VCC1V2_FPGA - IO_L16P_T2U_N6_QBC_AD3P_40
-# set_property PACKAGE_PIN AU34 [get_ports "DDR4_C2_DQ19"] ;# Bank 40 VCCO - VCC1V2_FPGA - IO_L15N_T2L_N5_AD11N_40
-# set_property IOSTANDARD POD12 [get_ports "DDR4_C2_DQ19"] ;# Bank 40 VCCO - VCC1V2_FPGA - IO_L15N_T2L_N5_AD11N_40
-# set_property PACKAGE_PIN AU33 [get_ports "DDR4_C2_DQ18"] ;# Bank 40 VCCO - VCC1V2_FPGA - IO_L15P_T2L_N4_AD11P_40
-# set_property IOSTANDARD POD12 [get_ports "DDR4_C2_DQ18"] ;# Bank 40 VCCO - VCC1V2_FPGA - IO_L15P_T2L_N4_AD11P_40
-# set_property PACKAGE_PIN AW30 [get_ports "DDR4_C2_DQ17"] ;# Bank 40 VCCO - VCC1V2_FPGA - IO_L14N_T2L_N3_GC_40
-# set_property IOSTANDARD POD12 [get_ports "DDR4_C2_DQ17"] ;# Bank 40 VCCO - VCC1V2_FPGA - IO_L14N_T2L_N3_GC_40
-# set_property PACKAGE_PIN AV30 [get_ports "DDR4_C2_DQ16"] ;# Bank 40 VCCO - VCC1V2_FPGA - IO_L14P_T2L_N2_GC_40
-# set_property IOSTANDARD POD12 [get_ports "DDR4_C2_DQ16"] ;# Bank 40 VCCO - VCC1V2_FPGA - IO_L14P_T2L_N2_GC_40
-# set_property PACKAGE_PIN AW33 [get_ports "FAN_FAIL_LS_B"] ;# Bank 40 VCCO - VCC1V2_FPGA - IO_L13N_T2L_N1_GC_QBC_40
-# set_property IOSTANDARD LVCMOS12 [get_ports "FAN_FAIL_LS_B"] ;# Bank 40 VCCO - VCC1V2_FPGA - IO_L13N_T2L_N1_GC_QBC_40
-# set_property PACKAGE_PIN AV33 [get_ports "DDR4_C2_DM2"] ;# Bank 40 VCCO - VCC1V2_FPGA - IO_L13P_T2L_N0_GC_QBC_40
-# set_property IOSTANDARD POD12 [get_ports "DDR4_C2_DM2"] ;# Bank 40 VCCO - VCC1V2_FPGA - IO_L13P_T2L_N0_GC_QBC_40
-# set_property PACKAGE_PIN AY33 [get_ports "DDR4_C2_DQ15"] ;# Bank 40 VCCO - VCC1V2_FPGA - IO_L12N_T1U_N11_GC_40
-# set_property IOSTANDARD POD12 [get_ports "DDR4_C2_DQ15"] ;# Bank 40 VCCO - VCC1V2_FPGA - IO_L12N_T1U_N11_GC_40
-# set_property PACKAGE_PIN AY32 [get_ports "DDR4_C2_DQ14"] ;# Bank 40 VCCO - VCC1V2_FPGA - IO_L12P_T1U_N10_GC_40
-# set_property IOSTANDARD POD12 [get_ports "DDR4_C2_DQ14"] ;# Bank 40 VCCO - VCC1V2_FPGA - IO_L12P_T1U_N10_GC_40
-# set_property PACKAGE_PIN AW32 [get_ports "DDR4_C2_DQ13"] ;# Bank 40 VCCO - VCC1V2_FPGA - IO_L11N_T1U_N9_GC_40
-# set_property IOSTANDARD POD12 [get_ports "DDR4_C2_DQ13"] ;# Bank 40 VCCO - VCC1V2_FPGA - IO_L11N_T1U_N9_GC_40
-# set_property PACKAGE_PIN AW31 [get_ports "DDR4_C2_DQ12"] ;# Bank 40 VCCO - VCC1V2_FPGA - IO_L11P_T1U_N8_GC_40
-# set_property IOSTANDARD POD12 [get_ports "DDR4_C2_DQ12"] ;# Bank 40 VCCO - VCC1V2_FPGA - IO_L11P_T1U_N8_GC_40
-# set_property PACKAGE_PIN BA34 [get_ports "DDR4_C2_DQS1_C"] ;# Bank 40 VCCO - VCC1V2_FPGA - IO_L10N_T1U_N7_QBC_AD4N_40
-# set_property IOSTANDARD POD12 [get_ports "DDR4_C2_DQS1_C"] ;# Bank 40 VCCO - VCC1V2_FPGA - IO_L10N_T1U_N7_QBC_AD4N_40
-# set_property PACKAGE_PIN AY34 [get_ports "DDR4_C2_DQS1_T"] ;# Bank 40 VCCO - VCC1V2_FPGA - IO_L10P_T1U_N6_QBC_AD4P_40
-# set_property IOSTANDARD POD12 [get_ports "DDR4_C2_DQS1_T"] ;# Bank 40 VCCO - VCC1V2_FPGA - IO_L10P_T1U_N6_QBC_AD4P_40
-# set_property PACKAGE_PIN BA31 [get_ports "DDR4_C2_DQ11"] ;# Bank 40 VCCO - VCC1V2_FPGA - IO_L9N_T1L_N5_AD12N_40
-# set_property IOSTANDARD POD12 [get_ports "DDR4_C2_DQ11"] ;# Bank 40 VCCO - VCC1V2_FPGA - IO_L9N_T1L_N5_AD12N_40
-# set_property PACKAGE_PIN BA30 [get_ports "DDR4_C2_DQ10"] ;# Bank 40 VCCO - VCC1V2_FPGA - IO_L9P_T1L_N4_AD12P_40
-# set_property IOSTANDARD POD12 [get_ports "DDR4_C2_DQ10"] ;# Bank 40 VCCO - VCC1V2_FPGA - IO_L9P_T1L_N4_AD12P_40
-# set_property PACKAGE_PIN BB33 [get_ports "DDR4_C2_DQ9"] ;# Bank 40 VCCO - VCC1V2_FPGA - IO_L8N_T1L_N3_AD5N_40
-# set_property IOSTANDARD POD12 [get_ports "DDR4_C2_DQ9"] ;# Bank 40 VCCO - VCC1V2_FPGA - IO_L8N_T1L_N3_AD5N_40
-# set_property PACKAGE_PIN BA32 [get_ports "DDR4_C2_DQ8"] ;# Bank 40 VCCO - VCC1V2_FPGA - IO_L8P_T1L_N2_AD5P_40
-# set_property IOSTANDARD POD12 [get_ports "DDR4_C2_DQ8"] ;# Bank 40 VCCO - VCC1V2_FPGA - IO_L8P_T1L_N2_AD5P_40
-# set_property PACKAGE_PIN BB32 [get_ports "GPIO_LED3"] ;# Bank 40 VCCO - VCC1V2_FPGA - IO_L7N_T1L_N1_QBC_AD13N_40
-# set_property IOSTANDARD LVCMOS12 [get_ports "GPIO_LED3"] ;# Bank 40 VCCO - VCC1V2_FPGA - IO_L7N_T1L_N1_QBC_AD13N_40
-# set_property PACKAGE_PIN BB31 [get_ports "DDR4_C2_DM1"] ;# Bank 40 VCCO - VCC1V2_FPGA - IO_L7P_T1L_N0_QBC_AD13P_40
-# set_property IOSTANDARD POD12 [get_ports "DDR4_C2_DM1"] ;# Bank 40 VCCO - VCC1V2_FPGA - IO_L7P_T1L_N0_QBC_AD13P_40
-# set_property PACKAGE_PIN AY30 [get_ports "GPIO_LED2"] ;# Bank 40 VCCO - VCC1V2_FPGA - IO_T1U_N12_40
-# set_property IOSTANDARD LVCMOS12 [get_ports "GPIO_LED2"] ;# Bank 40 VCCO - VCC1V2_FPGA - IO_T1U_N12_40
-# #set_property PACKAGE_PIN BC30 [get_ports "VRP_40"] ;# Bank 40 VCCO - VCC1V2_FPGA - IO_T0U_N12_VRP_40
-# #set_property IOSTANDARD LVCMOSxx [get_ports "VRP_40"] ;# Bank 40 VCCO - VCC1V2_FPGA - IO_T0U_N12_VRP_40
-# set_property PACKAGE_PIN BD31 [get_ports "DDR4_C2_DQ7"] ;# Bank 40 VCCO - VCC1V2_FPGA - IO_L6N_T0U_N11_AD6N_40
-# set_property IOSTANDARD POD12 [get_ports "DDR4_C2_DQ7"] ;# Bank 40 VCCO - VCC1V2_FPGA - IO_L6N_T0U_N11_AD6N_40
-# set_property PACKAGE_PIN BC31 [get_ports "DDR4_C2_DQ6"] ;# Bank 40 VCCO - VCC1V2_FPGA - IO_L6P_T0U_N10_AD6P_40
-# set_property IOSTANDARD POD12 [get_ports "DDR4_C2_DQ6"] ;# Bank 40 VCCO - VCC1V2_FPGA - IO_L6P_T0U_N10_AD6P_40
-# set_property PACKAGE_PIN BD33 [get_ports "DDR4_C2_DQ5"] ;# Bank 40 VCCO - VCC1V2_FPGA - IO_L5N_T0U_N9_AD14N_40
-# set_property IOSTANDARD POD12 [get_ports "DDR4_C2_DQ5"] ;# Bank 40 VCCO - VCC1V2_FPGA - IO_L5N_T0U_N9_AD14N_40
-# set_property PACKAGE_PIN BC33 [get_ports "DDR4_C2_DQ4"] ;# Bank 40 VCCO - VCC1V2_FPGA - IO_L5P_T0U_N8_AD14P_40
-# set_property IOSTANDARD POD12 [get_ports "DDR4_C2_DQ4"] ;# Bank 40 VCCO - VCC1V2_FPGA - IO_L5P_T0U_N8_AD14P_40
-# set_property PACKAGE_PIN BF31 [get_ports "DDR4_C2_DQS0_C"] ;# Bank 40 VCCO - VCC1V2_FPGA - IO_L4N_T0U_N7_DBC_AD7N_40
-# set_property IOSTANDARD DIFF_POD12 [get_ports "DDR4_C2_DQS0_C"] ;# Bank 40 VCCO - VCC1V2_FPGA - IO_L4N_T0U_N7_DBC_AD7N_40
-# set_property PACKAGE_PIN BF30 [get_ports "DDR4_C2_DQS0_T"] ;# Bank 40 VCCO - VCC1V2_FPGA - IO_L4P_T0U_N6_DBC_AD7P_40
-# set_property IOSTANDARD DIFF_POD12 [get_ports "DDR4_C2_DQS0_T"] ;# Bank 40 VCCO - VCC1V2_FPGA - IO_L4P_T0U_N6_DBC_AD7P_40
-# set_property PACKAGE_PIN BE33 [get_ports "DDR4_C2_DQ3"] ;# Bank 40 VCCO - VCC1V2_FPGA - IO_L3N_T0L_N5_AD15N_40
-# set_property IOSTANDARD POD12 [get_ports "DDR4_C2_DQ3"] ;# Bank 40 VCCO - VCC1V2_FPGA - IO_L3N_T0L_N5_AD15N_40
-# set_property PACKAGE_PIN BD32 [get_ports "DDR4_C2_DQ2"] ;# Bank 40 VCCO - VCC1V2_FPGA - IO_L3P_T0L_N4_AD15P_40
-# set_property IOSTANDARD POD12 [get_ports "DDR4_C2_DQ2"] ;# Bank 40 VCCO - VCC1V2_FPGA - IO_L3P_T0L_N4_AD15P_40
-# set_property PACKAGE_PIN BE30 [get_ports "DDR4_C2_DQ1"] ;# Bank 40 VCCO - VCC1V2_FPGA - IO_L2N_T0L_N3_40
-# set_property IOSTANDARD POD12 [get_ports "DDR4_C2_DQ1"] ;# Bank 40 VCCO - VCC1V2_FPGA - IO_L2N_T0L_N3_40
-# set_property PACKAGE_PIN BD30 [get_ports "DDR4_C2_DQ0"] ;# Bank 40 VCCO - VCC1V2_FPGA - IO_L2P_T0L_N2_40
-# set_property IOSTANDARD POD12 [get_ports "DDR4_C2_DQ0"] ;# Bank 40 VCCO - VCC1V2_FPGA - IO_L2P_T0L_N2_40
-# set_property PACKAGE_PIN BF32 [get_ports "GPIO_LED4"] ;# Bank 40 VCCO - VCC1V2_FPGA - IO_L1N_T0L_N1_DBC_40
-# set_property IOSTANDARD LVCMOS12 [get_ports "GPIO_LED4"] ;# Bank 40 VCCO - VCC1V2_FPGA - IO_L1N_T0L_N1_DBC_40
-# set_property PACKAGE_PIN BE32 [get_ports "DDR4_C2_DM0"] ;# Bank 40 VCCO - VCC1V2_FPGA - IO_L1P_T0L_N0_DBC_40
-# set_property IOSTANDARD POD12 [get_ports "DDR4_C2_DM0"] ;# Bank 40 VCCO - VCC1V2_FPGA - IO_L1P_T0L_N0_DBC_40
-# #Other net PACKAGE_PIN AN29 - 5N11680 Bank 40 - VREF_40
-# set_property PACKAGE_PIN B20 [get_ports "DDR4_C1_DQ39"] ;# Bank 73 VCCO - VCC1V2_FPGA - IO_L24N_T3U_N11_73
-# set_property IOSTANDARD POD12 [get_ports "DDR4_C1_DQ39"] ;# Bank 73 VCCO - VCC1V2_FPGA - IO_L24N_T3U_N11_73
-# set_property PACKAGE_PIN C20 [get_ports "DDR4_C1_DQ38"] ;# Bank 73 VCCO - VCC1V2_FPGA - IO_L24P_T3U_N10_73
-# set_property IOSTANDARD POD12 [get_ports "DDR4_C1_DQ38"] ;# Bank 73 VCCO - VCC1V2_FPGA - IO_L24P_T3U_N10_73
-# set_property PACKAGE_PIN D19 [get_ports "DDR4_C1_DQ37"] ;# Bank 73 VCCO - VCC1V2_FPGA - IO_L23N_T3U_N9_73
-# set_property IOSTANDARD POD12 [get_ports "DDR4_C1_DQ37"] ;# Bank 73 VCCO - VCC1V2_FPGA - IO_L23N_T3U_N9_73
-# set_property PACKAGE_PIN D20 [get_ports "DDR4_C1_DQ36"] ;# Bank 73 VCCO - VCC1V2_FPGA - IO_L23P_T3U_N8_73
-# set_property IOSTANDARD POD12 [get_ports "DDR4_C1_DQ36"] ;# Bank 73 VCCO - VCC1V2_FPGA - IO_L23P_T3U_N8_73
-# set_property PACKAGE_PIN A18 [get_ports "DDR4_C1_DQS4_C"] ;# Bank 73 VCCO - VCC1V2_FPGA - IO_L22N_T3U_N7_DBC_AD0N_73
-# set_property IOSTANDARD DIFF_POD12 [get_ports "DDR4_C1_DQS4_C"] ;# Bank 73 VCCO - VCC1V2_FPGA - IO_L22N_T3U_N7_DBC_AD0N_73
-# set_property PACKAGE_PIN A19 [get_ports "DDR4_C1_DQS4_T"] ;# Bank 73 VCCO - VCC1V2_FPGA - IO_L22P_T3U_N6_DBC_AD0P_73
-# set_property IOSTANDARD DIFF_POD12 [get_ports "DDR4_C1_DQS4_T"] ;# Bank 73 VCCO - VCC1V2_FPGA - IO_L22P_T3U_N6_DBC_AD0P_73
-# set_property PACKAGE_PIN C18 [get_ports "DDR4_C1_DQ35"] ;# Bank 73 VCCO - VCC1V2_FPGA - IO_L21N_T3L_N5_AD8N_73
-# set_property IOSTANDARD POD12 [get_ports "DDR4_C1_DQ35"] ;# Bank 73 VCCO - VCC1V2_FPGA - IO_L21N_T3L_N5_AD8N_73
-# set_property PACKAGE_PIN C19 [get_ports "DDR4_C1_DQ34"] ;# Bank 73 VCCO - VCC1V2_FPGA - IO_L21P_T3L_N4_AD8P_73
-# set_property IOSTANDARD POD12 [get_ports "DDR4_C1_DQ34"] ;# Bank 73 VCCO - VCC1V2_FPGA - IO_L21P_T3L_N4_AD8P_73
-# set_property PACKAGE_PIN C17 [get_ports "DDR4_C1_DQ33"] ;# Bank 73 VCCO - VCC1V2_FPGA - IO_L20N_T3L_N3_AD1N_73
-# set_property IOSTANDARD POD12 [get_ports "DDR4_C1_DQ33"] ;# Bank 73 VCCO - VCC1V2_FPGA - IO_L20N_T3L_N3_AD1N_73
-# set_property PACKAGE_PIN D17 [get_ports "DDR4_C1_DQ32"] ;# Bank 73 VCCO - VCC1V2_FPGA - IO_L20P_T3L_N2_AD1P_73
-# set_property IOSTANDARD POD12 [get_ports "DDR4_C1_DQ32"] ;# Bank 73 VCCO - VCC1V2_FPGA - IO_L20P_T3L_N2_AD1P_73
-# set_property PACKAGE_PIN B17 [get_ports "GPIO_DIP_SW1"] ;# Bank 73 VCCO - VCC1V2_FPGA - IO_L19N_T3L_N1_DBC_AD9N_73
-# set_property IOSTANDARD LVCMOS12 [get_ports "GPIO_DIP_SW1"] ;# Bank 73 VCCO - VCC1V2_FPGA - IO_L19N_T3L_N1_DBC_AD9N_73
-# set_property PACKAGE_PIN B18 [get_ports "DDR4_C1_DM4"] ;# Bank 73 VCCO - VCC1V2_FPGA - IO_L19P_T3L_N0_DBC_AD9P_73
-# set_property IOSTANDARD POD12 [get_ports "DDR4_C1_DM4"] ;# Bank 73 VCCO - VCC1V2_FPGA - IO_L19P_T3L_N0_DBC_AD9P_73
-# set_property PACKAGE_PIN A20 [get_ports "DDR4_C1_TEN"] ;# Bank 73 VCCO - VCC1V2_FPGA - IO_T3U_N12_73
-# set_property IOSTANDARD POD12 [get_ports "DDR4_C1_TEN"] ;# Bank 73 VCCO - VCC1V2_FPGA - IO_T3U_N12_73
-# set_property PACKAGE_PIN G16 [get_ports "GPIO_DIP_SW2"] ;# Bank 73 VCCO - VCC1V2_FPGA - IO_T2U_N12_73
-# set_property IOSTANDARD LVCMOS12 [get_ports "GPIO_DIP_SW2"] ;# Bank 73 VCCO - VCC1V2_FPGA - IO_T2U_N12_73
-# set_property PACKAGE_PIN D16 [get_ports "DDR4_C1_DQ31"] ;# Bank 73 VCCO - VCC1V2_FPGA - IO_L18N_T2U_N11_AD2N_73
-# set_property IOSTANDARD POD12 [get_ports "DDR4_C1_DQ31"] ;# Bank 73 VCCO - VCC1V2_FPGA - IO_L18N_T2U_N11_AD2N_73
-# set_property PACKAGE_PIN E17 [get_ports "DDR4_C1_DQ30"] ;# Bank 73 VCCO - VCC1V2_FPGA - IO_L18P_T2U_N10_AD2P_73
-# set_property IOSTANDARD POD12 [get_ports "DDR4_C1_DQ30"] ;# Bank 73 VCCO - VCC1V2_FPGA - IO_L18P_T2U_N10_AD2P_73
-# set_property PACKAGE_PIN F20 [get_ports "DDR4_C1_DQ29"] ;# Bank 73 VCCO - VCC1V2_FPGA - IO_L17N_T2U_N9_AD10N_73
-# set_property IOSTANDARD POD12 [get_ports "DDR4_C1_DQ29"] ;# Bank 73 VCCO - VCC1V2_FPGA - IO_L17N_T2U_N9_AD10N_73
-# set_property PACKAGE_PIN G20 [get_ports "DDR4_C1_DQ28"] ;# Bank 73 VCCO - VCC1V2_FPGA - IO_L17P_T2U_N8_AD10P_73
-# set_property IOSTANDARD POD12 [get_ports "DDR4_C1_DQ28"] ;# Bank 73 VCCO - VCC1V2_FPGA - IO_L17P_T2U_N8_AD10P_73
-# set_property PACKAGE_PIN E16 [get_ports "DDR4_C1_DQS3_C"] ;# Bank 73 VCCO - VCC1V2_FPGA - IO_L16N_T2U_N7_QBC_AD3N_73
-# set_property IOSTANDARD DIFF_POD12 [get_ports "DDR4_C1_DQS3_C"] ;# Bank 73 VCCO - VCC1V2_FPGA - IO_L16N_T2U_N7_QBC_AD3N_73
-# set_property PACKAGE_PIN F16 [get_ports "DDR4_C1_DQS3_T"] ;# Bank 73 VCCO - VCC1V2_FPGA - IO_L16P_T2U_N6_QBC_AD3P_73
-# set_property IOSTANDARD DIFF_POD12 [get_ports "DDR4_C1_DQS3_T"] ;# Bank 73 VCCO - VCC1V2_FPGA - IO_L16P_T2U_N6_QBC_AD3P_73
-# set_property PACKAGE_PIN E18 [get_ports "DDR4_C1_DQ27"] ;# Bank 73 VCCO - VCC1V2_FPGA - IO_L15N_T2L_N5_AD11N_73
-# set_property IOSTANDARD POD12 [get_ports "DDR4_C1_DQ27"] ;# Bank 73 VCCO - VCC1V2_FPGA - IO_L15N_T2L_N5_AD11N_73
-# set_property PACKAGE_PIN E19 [get_ports "DDR4_C1_DQ26"] ;# Bank 73 VCCO - VCC1V2_FPGA - IO_L15P_T2L_N4_AD11P_73
-# set_property IOSTANDARD POD12 [get_ports "DDR4_C1_DQ26"] ;# Bank 73 VCCO - VCC1V2_FPGA - IO_L15P_T2L_N4_AD11P_73
-# set_property PACKAGE_PIN F18 [get_ports "DDR4_C1_DQ25"] ;# Bank 73 VCCO - VCC1V2_FPGA - IO_L14N_T2L_N3_GC_73
-# set_property IOSTANDARD POD12 [get_ports "DDR4_C1_DQ25"] ;# Bank 73 VCCO - VCC1V2_FPGA - IO_L14N_T2L_N3_GC_73
-# set_property PACKAGE_PIN F19 [get_ports "DDR4_C1_DQ24"] ;# Bank 73 VCCO - VCC1V2_FPGA - IO_L14P_T2L_N2_GC_73
-# set_property IOSTANDARD POD12 [get_ports "DDR4_C1_DQ24"] ;# Bank 73 VCCO - VCC1V2_FPGA - IO_L14P_T2L_N2_GC_73
-# set_property PACKAGE_PIN G17 [get_ports "5329N4285"] ;# Bank 73 VCCO - VCC1V2_FPGA - IO_L13N_T2L_N1_GC_QBC_73
-# set_property IOSTANDARD LVCMOSxx [get_ports "5329N4285"] ;# Bank 73 VCCO - VCC1V2_FPGA - IO_L13N_T2L_N1_GC_QBC_73
-# set_property PACKAGE_PIN G18 [get_ports "DDR4_C1_DM3"] ;# Bank 73 VCCO - VCC1V2_FPGA - IO_L13P_T2L_N0_GC_QBC_73
-# set_property IOSTANDARD POD12 [get_ports "DDR4_C1_DM3"] ;# Bank 73 VCCO - VCC1V2_FPGA - IO_L13P_T2L_N0_GC_QBC_73
-# set_property PACKAGE_PIN H18 [get_ports "DDR4_C1_DQ23"] ;# Bank 73 VCCO - VCC1V2_FPGA - IO_L12N_T1U_N11_GC_73
-# set_property IOSTANDARD POD12 [get_ports "DDR4_C1_DQ23"] ;# Bank 73 VCCO - VCC1V2_FPGA - IO_L12N_T1U_N11_GC_73
-# set_property PACKAGE_PIN H19 [get_ports "DDR4_C1_DQ22"] ;# Bank 73 VCCO - VCC1V2_FPGA - IO_L12P_T1U_N10_GC_73
-# set_property IOSTANDARD POD12 [get_ports "DDR4_C1_DQ22"] ;# Bank 73 VCCO - VCC1V2_FPGA - IO_L12P_T1U_N10_GC_73
-# set_property PACKAGE_PIN H17 [get_ports "DDR4_C1_DQ21"] ;# Bank 73 VCCO - VCC1V2_FPGA - IO_L11N_T1U_N9_GC_73
-# set_property IOSTANDARD POD12 [get_ports "DDR4_C1_DQ21"] ;# Bank 73 VCCO - VCC1V2_FPGA - IO_L11N_T1U_N9_GC_73
-# set_property PACKAGE_PIN J17 [get_ports "DDR4_C1_DQ20"] ;# Bank 73 VCCO - VCC1V2_FPGA - IO_L11P_T1U_N8_GC_73
-# set_property IOSTANDARD POD12 [get_ports "DDR4_C1_DQ20"] ;# Bank 73 VCCO - VCC1V2_FPGA - IO_L11P_T1U_N8_GC_73
-# set_property PACKAGE_PIN J19 [get_ports "DDR4_C1_DQS2_C"] ;# Bank 73 VCCO - VCC1V2_FPGA - IO_L10N_T1U_N7_QBC_AD4N_73
-# set_property IOSTANDARD DIFF_POD12 [get_ports "DDR4_C1_DQS2_C"] ;# Bank 73 VCCO - VCC1V2_FPGA - IO_L10N_T1U_N7_QBC_AD4N_73
-# set_property PACKAGE_PIN K19 [get_ports "DDR4_C1_DQS2_T"] ;# Bank 73 VCCO - VCC1V2_FPGA - IO_L10P_T1U_N6_QBC_AD4P_73
-# set_property IOSTANDARD DIFF_POD12 [get_ports "DDR4_C1_DQS2_T"] ;# Bank 73 VCCO - VCC1V2_FPGA - IO_L10P_T1U_N6_QBC_AD4P_73
-# set_property PACKAGE_PIN K18 [get_ports "DDR4_C1_DQ19"] ;# Bank 73 VCCO - VCC1V2_FPGA - IO_L9N_T1L_N5_AD12N_73
-# set_property IOSTANDARD POD12 [get_ports "DDR4_C1_DQ19"] ;# Bank 73 VCCO - VCC1V2_FPGA - IO_L9N_T1L_N5_AD12N_73
-# set_property PACKAGE_PIN L18 [get_ports "DDR4_C1_DQ18"] ;# Bank 73 VCCO - VCC1V2_FPGA - IO_L9P_T1L_N4_AD12P_73
-# set_property IOSTANDARD POD12 [get_ports "DDR4_C1_DQ18"] ;# Bank 73 VCCO - VCC1V2_FPGA - IO_L9P_T1L_N4_AD12P_73
-# set_property PACKAGE_PIN K16 [get_ports "DDR4_C1_DQ17"] ;# Bank 73 VCCO - VCC1V2_FPGA - IO_L8N_T1L_N3_AD5N_73
-# set_property IOSTANDARD POD12 [get_ports "DDR4_C1_DQ17"] ;# Bank 73 VCCO - VCC1V2_FPGA - IO_L8N_T1L_N3_AD5N_73
-# set_property PACKAGE_PIN L16 [get_ports "DDR4_C1_DQ16"] ;# Bank 73 VCCO - VCC1V2_FPGA - IO_L8P_T1L_N2_AD5P_73
-# set_property IOSTANDARD POD12 [get_ports "DDR4_C1_DQ16"] ;# Bank 73 VCCO - VCC1V2_FPGA - IO_L8P_T1L_N2_AD5P_73
-# set_property PACKAGE_PIN J16 [get_ports "GPIO_DIP_SW3"] ;# Bank 73 VCCO - VCC1V2_FPGA - IO_L7N_T1L_N1_QBC_AD13N_73
-# set_property IOSTANDARD LVCMOS12 [get_ports "GPIO_DIP_SW3"] ;# Bank 73 VCCO - VCC1V2_FPGA - IO_L7N_T1L_N1_QBC_AD13N_73
-# set_property PACKAGE_PIN K17 [get_ports "DDR4_C1_DM2"] ;# Bank 73 VCCO - VCC1V2_FPGA - IO_L7P_T1L_N0_QBC_AD13P_73
-# set_property IOSTANDARD POD12 [get_ports "DDR4_C1_DM2"] ;# Bank 73 VCCO - VCC1V2_FPGA - IO_L7P_T1L_N0_QBC_AD13P_73
-# #set_property PACKAGE_PIN T18 [get_ports "VRP_73"] ;# Bank 73 VCCO - VCC1V2_FPGA - IO_T0U_N12_VRP_73
-# #set_property IOSTANDARD LVCMOSxx [get_ports "VRP_73"] ;# Bank 73 VCCO - VCC1V2_FPGA - IO_T0U_N12_VRP_73
-# set_property PACKAGE_PIN M16 [get_ports "DDR4_C1_DQ15"] ;# Bank 73 VCCO - VCC1V2_FPGA - IO_L6N_T0U_N11_AD6N_73
-# set_property IOSTANDARD POD12 [get_ports "DDR4_C1_DQ15"] ;# Bank 73 VCCO - VCC1V2_FPGA - IO_L6N_T0U_N11_AD6N_73
-# set_property PACKAGE_PIN N17 [get_ports "DDR4_C1_DQ14"] ;# Bank 73 VCCO - VCC1V2_FPGA - IO_L6P_T0U_N10_AD6P_73
-# set_property IOSTANDARD POD12 [get_ports "DDR4_C1_DQ14"] ;# Bank 73 VCCO - VCC1V2_FPGA - IO_L6P_T0U_N10_AD6P_73
-# set_property PACKAGE_PIN N18 [get_ports "DDR4_C1_DQ13"] ;# Bank 73 VCCO - VCC1V2_FPGA - IO_L5N_T0U_N9_AD14N_73
-# set_property IOSTANDARD POD12 [get_ports "DDR4_C1_DQ13"] ;# Bank 73 VCCO - VCC1V2_FPGA - IO_L5N_T0U_N9_AD14N_73
-# set_property PACKAGE_PIN N19 [get_ports "DDR4_C1_DQ12"] ;# Bank 73 VCCO - VCC1V2_FPGA - IO_L5P_T0U_N8_AD14P_73
-# set_property IOSTANDARD POD12 [get_ports "DDR4_C1_DQ12"] ;# Bank 73 VCCO - VCC1V2_FPGA - IO_L5P_T0U_N8_AD14P_73
-# set_property PACKAGE_PIN P16 [get_ports "DDR4_C1_DQS1_C"] ;# Bank 73 VCCO - VCC1V2_FPGA - IO_L4N_T0U_N7_DBC_AD7N_73
-# set_property IOSTANDARD DIFF_POD12 [get_ports "DDR4_C1_DQS1_C"] ;# Bank 73 VCCO - VCC1V2_FPGA - IO_L4N_T0U_N7_DBC_AD7N_73
-# set_property PACKAGE_PIN P17 [get_ports "DDR4_C1_DQS1_T"] ;# Bank 73 VCCO - VCC1V2_FPGA - IO_L4P_T0U_N6_DBC_AD7P_73
-# set_property IOSTANDARD DIFF_POD12 [get_ports "DDR4_C1_DQS1_T"] ;# Bank 73 VCCO - VCC1V2_FPGA - IO_L4P_T0U_N6_DBC_AD7P_73
-# set_property PACKAGE_PIN M17 [get_ports "DDR4_C1_DQ11"] ;# Bank 73 VCCO - VCC1V2_FPGA - IO_L3N_T0L_N5_AD15N_73
-# set_property IOSTANDARD POD12 [get_ports "DDR4_C1_DQ11"] ;# Bank 73 VCCO - VCC1V2_FPGA - IO_L3N_T0L_N5_AD15N_73
-# set_property PACKAGE_PIN M18 [get_ports "DDR4_C1_DQ10"] ;# Bank 73 VCCO - VCC1V2_FPGA - IO_L3P_T0L_N4_AD15P_73
-# set_property IOSTANDARD POD12 [get_ports "DDR4_C1_DQ10"] ;# Bank 73 VCCO - VCC1V2_FPGA - IO_L3P_T0L_N4_AD15P_73
-# set_property PACKAGE_PIN P19 [get_ports "DDR4_C1_DQ9"] ;# Bank 73 VCCO - VCC1V2_FPGA - IO_L2N_T0L_N3_73
-# set_property IOSTANDARD POD12 [get_ports "DDR4_C1_DQ9"] ;# Bank 73 VCCO - VCC1V2_FPGA - IO_L2N_T0L_N3_73
-# set_property PACKAGE_PIN R19 [get_ports "DDR4_C1_DQ8"] ;# Bank 73 VCCO - VCC1V2_FPGA - IO_L2P_T0L_N2_73
-# set_property IOSTANDARD POD12 [get_ports "DDR4_C1_DQ8"] ;# Bank 73 VCCO - VCC1V2_FPGA - IO_L2P_T0L_N2_73
-# set_property PACKAGE_PIN R17 [get_ports "DDR4_C1_ALERT_B"] ;# Bank 73 VCCO - VCC1V2_FPGA - IO_L1N_T0L_N1_DBC_73
-# set_property IOSTANDARD POD12 [get_ports "DDR4_C1_ALERT_B"] ;# Bank 73 VCCO - VCC1V2_FPGA - IO_L1N_T0L_N1_DBC_73
-# set_property PACKAGE_PIN R18 [get_ports "DDR4_C1_DM1"] ;# Bank 73 VCCO - VCC1V2_FPGA - IO_L1P_T0L_N0_DBC_73
-# set_property IOSTANDARD POD12 [get_ports "DDR4_C1_DM1"] ;# Bank 73 VCCO - VCC1V2_FPGA - IO_L1P_T0L_N0_DBC_73
-# #Other net PACKAGE_PIN T19 - 5329N4282 Bank 73 - VREF_73
-# set_property PACKAGE_PIN A21 [get_ports "DDR4_C1_DQ71"] ;# Bank 72 VCCO - VCC1V2_FPGA - IO_L24N_T3U_N11_72
-# set_property IOSTANDARD POD12 [get_ports "DDR4_C1_DQ71"] ;# Bank 72 VCCO - VCC1V2_FPGA - IO_L24N_T3U_N11_72
-# set_property PACKAGE_PIN B21 [get_ports "DDR4_C1_DQ70"] ;# Bank 72 VCCO - VCC1V2_FPGA - IO_L24P_T3U_N10_72
-# set_property IOSTANDARD POD12 [get_ports "DDR4_C1_DQ70"] ;# Bank 72 VCCO - VCC1V2_FPGA - IO_L24P_T3U_N10_72
-# set_property PACKAGE_PIN B22 [get_ports "DDR4_C1_DQ69"] ;# Bank 72 VCCO - VCC1V2_FPGA - IO_L23N_T3U_N9_72
-# set_property IOSTANDARD POD12 [get_ports "DDR4_C1_DQ69"] ;# Bank 72 VCCO - VCC1V2_FPGA - IO_L23N_T3U_N9_72
-# set_property PACKAGE_PIN B23 [get_ports "DDR4_C1_DQ68"] ;# Bank 72 VCCO - VCC1V2_FPGA - IO_L23P_T3U_N8_72
-# set_property IOSTANDARD POD12 [get_ports "DDR4_C1_DQ68"] ;# Bank 72 VCCO - VCC1V2_FPGA - IO_L23P_T3U_N8_72
-# set_property PACKAGE_PIN C22 [get_ports "DDR4_C1_DQS8_C"] ;# Bank 72 VCCO - VCC1V2_FPGA - IO_L22N_T3U_N7_DBC_AD0N_72
-# set_property IOSTANDARD DIFF_POD12 [get_ports "DDR4_C1_DQS8_C"] ;# Bank 72 VCCO - VCC1V2_FPGA - IO_L22N_T3U_N7_DBC_AD0N_72
-# set_property PACKAGE_PIN D22 [get_ports "DDR4_C1_DQS8_T"] ;# Bank 72 VCCO - VCC1V2_FPGA - IO_L22P_T3U_N6_DBC_AD0P_72
-# set_property IOSTANDARD DIFF_POD12 [get_ports "DDR4_C1_DQS8_T"] ;# Bank 72 VCCO - VCC1V2_FPGA - IO_L22P_T3U_N6_DBC_AD0P_72
-# set_property PACKAGE_PIN C23 [get_ports "DDR4_C1_DQ67"] ;# Bank 72 VCCO - VCC1V2_FPGA - IO_L21N_T3L_N5_AD8N_72
-# set_property IOSTANDARD POD12 [get_ports "DDR4_C1_DQ67"] ;# Bank 72 VCCO - VCC1V2_FPGA - IO_L21N_T3L_N5_AD8N_72
-# set_property PACKAGE_PIN C24 [get_ports "DDR4_C1_DQ66"] ;# Bank 72 VCCO - VCC1V2_FPGA - IO_L21P_T3L_N4_AD8P_72
-# set_property IOSTANDARD POD12 [get_ports "DDR4_C1_DQ66"] ;# Bank 72 VCCO - VCC1V2_FPGA - IO_L21P_T3L_N4_AD8P_72
-# set_property PACKAGE_PIN A23 [get_ports "DDR4_C1_DQ65"] ;# Bank 72 VCCO - VCC1V2_FPGA - IO_L20N_T3L_N3_AD1N_72
-# set_property IOSTANDARD POD12 [get_ports "DDR4_C1_DQ65"] ;# Bank 72 VCCO - VCC1V2_FPGA - IO_L20N_T3L_N3_AD1N_72
-# set_property PACKAGE_PIN A24 [get_ports "DDR4_C1_DQ64"] ;# Bank 72 VCCO - VCC1V2_FPGA - IO_L20P_T3L_N2_AD1P_72
-# set_property IOSTANDARD POD12 [get_ports "DDR4_C1_DQ64"] ;# Bank 72 VCCO - VCC1V2_FPGA - IO_L20P_T3L_N2_AD1P_72
-# set_property PACKAGE_PIN D24 [get_ports "5329N4244"] ;# Bank 72 VCCO - VCC1V2_FPGA - IO_L19N_T3L_N1_DBC_AD9N_72
-# set_property IOSTANDARD LVCMOSxx [get_ports "5329N4244"] ;# Bank 72 VCCO - VCC1V2_FPGA - IO_L19N_T3L_N1_DBC_AD9N_72
-# set_property PACKAGE_PIN E24 [get_ports "DDR4_C1_DM8"] ;# Bank 72 VCCO - VCC1V2_FPGA - IO_L19P_T3L_N0_DBC_AD9P_72
-# set_property IOSTANDARD POD12 [get_ports "DDR4_C1_DM8"] ;# Bank 72 VCCO - VCC1V2_FPGA - IO_L19P_T3L_N0_DBC_AD9P_72
-# set_property PACKAGE_PIN D21 [get_ports "GPIO_DIP_SW4"] ;# Bank 72 VCCO - VCC1V2_FPGA - IO_T3U_N12_72
-# set_property IOSTANDARD LVCMOS12 [get_ports "GPIO_DIP_SW4"] ;# Bank 72 VCCO - VCC1V2_FPGA - IO_T3U_N12_72
-# set_property PACKAGE_PIN H20 [get_ports "SI5328_INT_ALM_LS"] ;# Bank 72 VCCO - VCC1V2_FPGA - IO_T2U_N12_72
-# set_property IOSTANDARD LVCMOS12 [get_ports "SI5328_INT_ALM_LS"] ;# Bank 72 VCCO - VCC1V2_FPGA - IO_T2U_N12_72
-# set_property PACKAGE_PIN F23 [get_ports "DDR4_C1_DQ63"] ;# Bank 72 VCCO - VCC1V2_FPGA - IO_L18N_T2U_N11_AD2N_72
-# set_property IOSTANDARD POD12 [get_ports "DDR4_C1_DQ63"] ;# Bank 72 VCCO - VCC1V2_FPGA - IO_L18N_T2U_N11_AD2N_72
-# set_property PACKAGE_PIN F24 [get_ports "DDR4_C1_DQ62"] ;# Bank 72 VCCO - VCC1V2_FPGA - IO_L18P_T2U_N10_AD2P_72
-# set_property IOSTANDARD POD12 [get_ports "DDR4_C1_DQ62"] ;# Bank 72 VCCO - VCC1V2_FPGA - IO_L18P_T2U_N10_AD2P_72
-# set_property PACKAGE_PIN E21 [get_ports "DDR4_C1_DQ61"] ;# Bank 72 VCCO - VCC1V2_FPGA - IO_L17N_T2U_N9_AD10N_72
-# set_property IOSTANDARD POD12 [get_ports "DDR4_C1_DQ61"] ;# Bank 72 VCCO - VCC1V2_FPGA - IO_L17N_T2U_N9_AD10N_72
-# set_property PACKAGE_PIN F21 [get_ports "DDR4_C1_DQ60"] ;# Bank 72 VCCO - VCC1V2_FPGA - IO_L17P_T2U_N8_AD10P_72
-# set_property IOSTANDARD POD12 [get_ports "DDR4_C1_DQ60"] ;# Bank 72 VCCO - VCC1V2_FPGA - IO_L17P_T2U_N8_AD10P_72
-# set_property PACKAGE_PIN G23 [get_ports "DDR4_C1_DQS7_C"] ;# Bank 72 VCCO - VCC1V2_FPGA - IO_L16N_T2U_N7_QBC_AD3N_72
-# set_property IOSTANDARD DIFF_POD12 [get_ports "DDR4_C1_DQS7_C"] ;# Bank 72 VCCO - VCC1V2_FPGA - IO_L16N_T2U_N7_QBC_AD3N_72
-# set_property PACKAGE_PIN H24 [get_ports "DDR4_C1_DQS7_T"] ;# Bank 72 VCCO - VCC1V2_FPGA - IO_L16P_T2U_N6_QBC_AD3P_72
-# set_property IOSTANDARD DIFF_POD12 [get_ports "DDR4_C1_DQS7_T"] ;# Bank 72 VCCO - VCC1V2_FPGA - IO_L16P_T2U_N6_QBC_AD3P_72
-# set_property PACKAGE_PIN E22 [get_ports "DDR4_C1_DQ59"] ;# Bank 72 VCCO - VCC1V2_FPGA - IO_L15N_T2L_N5_AD11N_72
-# set_property IOSTANDARD POD12 [get_ports "DDR4_C1_DQ59"] ;# Bank 72 VCCO - VCC1V2_FPGA - IO_L15N_T2L_N5_AD11N_72
-# set_property PACKAGE_PIN E23 [get_ports "DDR4_C1_DQ58"] ;# Bank 72 VCCO - VCC1V2_FPGA - IO_L15P_T2L_N4_AD11P_72
-# set_property IOSTANDARD POD12 [get_ports "DDR4_C1_DQ58"] ;# Bank 72 VCCO - VCC1V2_FPGA - IO_L15P_T2L_N4_AD11P_72
-# set_property PACKAGE_PIN H22 [get_ports "DDR4_C1_DQ57"] ;# Bank 72 VCCO - VCC1V2_FPGA - IO_L14N_T2L_N3_GC_72
-# set_property IOSTANDARD POD12 [get_ports "DDR4_C1_DQ57"] ;# Bank 72 VCCO - VCC1V2_FPGA - IO_L14N_T2L_N3_GC_72
-# set_property PACKAGE_PIN H23 [get_ports "DDR4_C1_DQ56"] ;# Bank 72 VCCO - VCC1V2_FPGA - IO_L14P_T2L_N2_GC_72
-# set_property IOSTANDARD POD12 [get_ports "DDR4_C1_DQ56"] ;# Bank 72 VCCO - VCC1V2_FPGA - IO_L14P_T2L_N2_GC_72
-# set_property PACKAGE_PIN G21 [get_ports "5329N4246"] ;# Bank 72 VCCO - VCC1V2_FPGA - IO_L13N_T2L_N1_GC_QBC_72
-# set_property IOSTANDARD LVCMOSxx [get_ports "5329N4246"] ;# Bank 72 VCCO - VCC1V2_FPGA - IO_L13N_T2L_N1_GC_QBC_72
-# set_property PACKAGE_PIN G22 [get_ports "DDR4_C1_DM7"] ;# Bank 72 VCCO - VCC1V2_FPGA - IO_L13P_T2L_N0_GC_QBC_72
-# set_property IOSTANDARD POD12 [get_ports "DDR4_C1_DM7"] ;# Bank 72 VCCO - VCC1V2_FPGA - IO_L13P_T2L_N0_GC_QBC_72
-# set_property PACKAGE_PIN J22 [get_ports "DDR4_C1_DQ55"] ;# Bank 72 VCCO - VCC1V2_FPGA - IO_L12N_T1U_N11_GC_72
-# set_property IOSTANDARD POD12 [get_ports "DDR4_C1_DQ55"] ;# Bank 72 VCCO - VCC1V2_FPGA - IO_L12N_T1U_N11_GC_72
-# set_property PACKAGE_PIN K22 [get_ports "DDR4_C1_DQ54"] ;# Bank 72 VCCO - VCC1V2_FPGA - IO_L12P_T1U_N10_GC_72
-# set_property IOSTANDARD POD12 [get_ports "DDR4_C1_DQ54"] ;# Bank 72 VCCO - VCC1V2_FPGA - IO_L12P_T1U_N10_GC_72
-# set_property PACKAGE_PIN J21 [get_ports "DDR4_C1_DQ53"] ;# Bank 72 VCCO - VCC1V2_FPGA - IO_L11N_T1U_N9_GC_72
-# set_property IOSTANDARD POD12 [get_ports "DDR4_C1_DQ53"] ;# Bank 72 VCCO - VCC1V2_FPGA - IO_L11N_T1U_N9_GC_72
-# set_property PACKAGE_PIN K21 [get_ports "DDR4_C1_DQ52"] ;# Bank 72 VCCO - VCC1V2_FPGA - IO_L11P_T1U_N8_GC_72
-# set_property IOSTANDARD POD12 [get_ports "DDR4_C1_DQ52"] ;# Bank 72 VCCO - VCC1V2_FPGA - IO_L11P_T1U_N8_GC_72
-# set_property PACKAGE_PIN L20 [get_ports "DDR4_C1_DQS6_C"] ;# Bank 72 VCCO - VCC1V2_FPGA - IO_L10N_T1U_N7_QBC_AD4N_72
-# set_property IOSTANDARD DIFF_POD12 [get_ports "DDR4_C1_DQS6_C"] ;# Bank 72 VCCO - VCC1V2_FPGA - IO_L10N_T1U_N7_QBC_AD4N_72
-# set_property PACKAGE_PIN M20 [get_ports "DDR4_C1_DQS6_T"] ;# Bank 72 VCCO - VCC1V2_FPGA - IO_L10P_T1U_N6_QBC_AD4P_72
-# set_property IOSTANDARD DIFF_POD12 [get_ports "DDR4_C1_DQS6_T"] ;# Bank 72 VCCO - VCC1V2_FPGA - IO_L10P_T1U_N6_QBC_AD4P_72
-# set_property PACKAGE_PIN L21 [get_ports "DDR4_C1_DQ51"] ;# Bank 72 VCCO - VCC1V2_FPGA - IO_L9N_T1L_N5_AD12N_72
-# set_property IOSTANDARD POD12 [get_ports "DDR4_C1_DQ51"] ;# Bank 72 VCCO - VCC1V2_FPGA - IO_L9N_T1L_N5_AD12N_72
-# set_property PACKAGE_PIN M21 [get_ports "DDR4_C1_DQ50"] ;# Bank 72 VCCO - VCC1V2_FPGA - IO_L9P_T1L_N4_AD12P_72
-# set_property IOSTANDARD POD12 [get_ports "DDR4_C1_DQ50"] ;# Bank 72 VCCO - VCC1V2_FPGA - IO_L9P_T1L_N4_AD12P_72
-# set_property PACKAGE_PIN J24 [get_ports "DDR4_C1_DQ49"] ;# Bank 72 VCCO - VCC1V2_FPGA - IO_L8N_T1L_N3_AD5N_72
-# set_property IOSTANDARD POD12 [get_ports "DDR4_C1_DQ49"] ;# Bank 72 VCCO - VCC1V2_FPGA - IO_L8N_T1L_N3_AD5N_72
-# set_property PACKAGE_PIN K24 [get_ports "DDR4_C1_DQ48"] ;# Bank 72 VCCO - VCC1V2_FPGA - IO_L8P_T1L_N2_AD5P_72
-# set_property IOSTANDARD POD12 [get_ports "DDR4_C1_DQ48"] ;# Bank 72 VCCO - VCC1V2_FPGA - IO_L8P_T1L_N2_AD5P_72
-# set_property PACKAGE_PIN K23 [get_ports "5329N4248"] ;# Bank 72 VCCO - VCC1V2_FPGA - IO_L7N_T1L_N1_QBC_AD13N_72
-# set_property IOSTANDARD LVCMOSxx [get_ports "5329N4248"] ;# Bank 72 VCCO - VCC1V2_FPGA - IO_L7N_T1L_N1_QBC_AD13N_72
-# set_property PACKAGE_PIN L23 [get_ports "DDR4_C1_DM6"] ;# Bank 72 VCCO - VCC1V2_FPGA - IO_L7P_T1L_N0_QBC_AD13P_72
-# set_property IOSTANDARD POD12 [get_ports "DDR4_C1_DM6"] ;# Bank 72 VCCO - VCC1V2_FPGA - IO_L7P_T1L_N0_QBC_AD13P_72
-# set_property PACKAGE_PIN J20 [get_ports "5329N4257"] ;# Bank 72 VCCO - VCC1V2_FPGA - IO_T1U_N12_72
-# set_property IOSTANDARD LVCMOSxx [get_ports "5329N4257"] ;# Bank 72 VCCO - VCC1V2_FPGA - IO_T1U_N12_72
-# #set_property PACKAGE_PIN T21 [get_ports "VRP_72"] ;# Bank 72 VCCO - VCC1V2_FPGA - IO_T0U_N12_VRP_72
-# #set_property IOSTANDARD LVCMOSxx [get_ports "VRP_72"] ;# Bank 72 VCCO - VCC1V2_FPGA - IO_T0U_N12_VRP_72
-# set_property PACKAGE_PIN R23 [get_ports "DDR4_C1_DQ47"] ;# Bank 72 VCCO - VCC1V2_FPGA - IO_L6N_T0U_N11_AD6N_72
-# set_property IOSTANDARD POD12 [get_ports "DDR4_C1_DQ47"] ;# Bank 72 VCCO - VCC1V2_FPGA - IO_L6N_T0U_N11_AD6N_72
-# set_property PACKAGE_PIN T23 [get_ports "DDR4_C1_DQ46"] ;# Bank 72 VCCO - VCC1V2_FPGA - IO_L6P_T0U_N10_AD6P_72
-# set_property IOSTANDARD POD12 [get_ports "DDR4_C1_DQ46"] ;# Bank 72 VCCO - VCC1V2_FPGA - IO_L6P_T0U_N10_AD6P_72
-# set_property PACKAGE_PIN P22 [get_ports "DDR4_C1_DQ45"] ;# Bank 72 VCCO - VCC1V2_FPGA - IO_L5N_T0U_N9_AD14N_72
-# set_property IOSTANDARD POD12 [get_ports "DDR4_C1_DQ45"] ;# Bank 72 VCCO - VCC1V2_FPGA - IO_L5N_T0U_N9_AD14N_72
-# set_property PACKAGE_PIN R22 [get_ports "DDR4_C1_DQ44"] ;# Bank 72 VCCO - VCC1V2_FPGA - IO_L5P_T0U_N8_AD14P_72
-# set_property IOSTANDARD POD12 [get_ports "DDR4_C1_DQ44"] ;# Bank 72 VCCO - VCC1V2_FPGA - IO_L5P_T0U_N8_AD14P_72
-# set_property PACKAGE_PIN M22 [get_ports "DDR4_C1_DQS5_C"] ;# Bank 72 VCCO - VCC1V2_FPGA - IO_L4N_T0U_N7_DBC_AD7N_72
-# set_property IOSTANDARD DIFF_POD12 [get_ports "DDR4_C1_DQS5_C"] ;# Bank 72 VCCO - VCC1V2_FPGA - IO_L4N_T0U_N7_DBC_AD7N_72
-# set_property PACKAGE_PIN N22 [get_ports "DDR4_C1_DQS5_T"] ;# Bank 72 VCCO - VCC1V2_FPGA - IO_L4P_T0U_N6_DBC_AD7P_72
-# set_property IOSTANDARD DIFF_POD12 [get_ports "DDR4_C1_DQS5_T"] ;# Bank 72 VCCO - VCC1V2_FPGA - IO_L4P_T0U_N6_DBC_AD7P_72
-# set_property PACKAGE_PIN P21 [get_ports "DDR4_C1_DQ43"] ;# Bank 72 VCCO - VCC1V2_FPGA - IO_L3N_T0L_N5_AD15N_72
-# set_property IOSTANDARD POD12 [get_ports "DDR4_C1_DQ43"] ;# Bank 72 VCCO - VCC1V2_FPGA - IO_L3N_T0L_N5_AD15N_72
-# set_property PACKAGE_PIN R21 [get_ports "DDR4_C1_DQ42"] ;# Bank 72 VCCO - VCC1V2_FPGA - IO_L3P_T0L_N4_AD15P_72
-# set_property IOSTANDARD POD12 [get_ports "DDR4_C1_DQ42"] ;# Bank 72 VCCO - VCC1V2_FPGA - IO_L3P_T0L_N4_AD15P_72
-# set_property PACKAGE_PIN M23 [get_ports "DDR4_C1_DQ41"] ;# Bank 72 VCCO - VCC1V2_FPGA - IO_L2N_T0L_N3_72
-# set_property IOSTANDARD POD12 [get_ports "DDR4_C1_DQ41"] ;# Bank 72 VCCO - VCC1V2_FPGA - IO_L2N_T0L_N3_72
-# set_property PACKAGE_PIN N23 [get_ports "DDR4_C1_DQ40"] ;# Bank 72 VCCO - VCC1V2_FPGA - IO_L2P_T0L_N2_72
-# set_property IOSTANDARD POD12 [get_ports "DDR4_C1_DQ40"] ;# Bank 72 VCCO - VCC1V2_FPGA - IO_L2P_T0L_N2_72
-# set_property PACKAGE_PIN N20 [get_ports "DDR4_C1_RESET_B"] ;# Bank 72 VCCO - VCC1V2_FPGA - IO_L1N_T0L_N1_DBC_72
-# set_property IOSTANDARD LVCMOS12 [get_ports "DDR4_C1_RESET_B"] ;# Bank 72 VCCO - VCC1V2_FPGA - IO_L1N_T0L_N1_DBC_72
-# set_property PACKAGE_PIN P20 [get_ports "DDR4_C1_DM5"] ;# Bank 72 VCCO - VCC1V2_FPGA - IO_L1P_T0L_N0_DBC_72
-# set_property IOSTANDARD POD12 [get_ports "DDR4_C1_DM5"] ;# Bank 72 VCCO - VCC1V2_FPGA - IO_L1P_T0L_N0_DBC_72
-# #Other net PACKAGE_PIN T20 - 5329N4288 Bank 72 - VREF_72
-# set_property PACKAGE_PIN B15 [get_ports "DDR4_C1_A1"] ;# Bank 71 VCCO - VCC1V2_FPGA - IO_L24N_T3U_N11_71
-# set_property IOSTANDARD SSTL12 [get_ports "DDR4_C1_A1"] ;# Bank 71 VCCO - VCC1V2_FPGA - IO_L24N_T3U_N11_71
-# set_property PACKAGE_PIN B16 [get_ports "DDR4_C1_A2"] ;# Bank 71 VCCO - VCC1V2_FPGA - IO_L24P_T3U_N10_71
-# set_property IOSTANDARD SSTL12 [get_ports "DDR4_C1_A2"] ;# Bank 71 VCCO - VCC1V2_FPGA - IO_L24P_T3U_N10_71
-# set_property PACKAGE_PIN C14 [get_ports "DDR4_C1_A3"] ;# Bank 71 VCCO - VCC1V2_FPGA - IO_L23N_T3U_N9_71
-# set_property IOSTANDARD SSTL12 [get_ports "DDR4_C1_A3"] ;# Bank 71 VCCO - VCC1V2_FPGA - IO_L23N_T3U_N9_71
-# set_property PACKAGE_PIN C15 [get_ports "DDR4_C1_A4"] ;# Bank 71 VCCO - VCC1V2_FPGA - IO_L23P_T3U_N8_71
-# set_property IOSTANDARD SSTL12 [get_ports "DDR4_C1_A4"] ;# Bank 71 VCCO - VCC1V2_FPGA - IO_L23P_T3U_N8_71
-# set_property PACKAGE_PIN A13 [get_ports "DDR4_C1_A5"] ;# Bank 71 VCCO - VCC1V2_FPGA - IO_L22N_T3U_N7_DBC_AD0N_71
-# set_property IOSTANDARD SSTL12 [get_ports "DDR4_C1_A5"] ;# Bank 71 VCCO - VCC1V2_FPGA - IO_L22N_T3U_N7_DBC_AD0N_71
-# set_property PACKAGE_PIN A14 [get_ports "DDR4_C1_A6"] ;# Bank 71 VCCO - VCC1V2_FPGA - IO_L22P_T3U_N6_DBC_AD0P_71
-# set_property IOSTANDARD SSTL12 [get_ports "DDR4_C1_A6"] ;# Bank 71 VCCO - VCC1V2_FPGA - IO_L22P_T3U_N6_DBC_AD0P_71
-# set_property PACKAGE_PIN A15 [get_ports "DDR4_C1_A7"] ;# Bank 71 VCCO - VCC1V2_FPGA - IO_L21N_T3L_N5_AD8N_71
-# set_property IOSTANDARD SSTL12 [get_ports "DDR4_C1_A7"] ;# Bank 71 VCCO - VCC1V2_FPGA - IO_L21N_T3L_N5_AD8N_71
-# set_property PACKAGE_PIN A16 [get_ports "DDR4_C1_A8"] ;# Bank 71 VCCO - VCC1V2_FPGA - IO_L21P_T3L_N4_AD8P_71
-# set_property IOSTANDARD SSTL12 [get_ports "DDR4_C1_A8"] ;# Bank 71 VCCO - VCC1V2_FPGA - IO_L21P_T3L_N4_AD8P_71
-# set_property PACKAGE_PIN B12 [get_ports "DDR4_C1_A9"] ;# Bank 71 VCCO - VCC1V2_FPGA - IO_L20N_T3L_N3_AD1N_71
-# set_property IOSTANDARD SSTL12 [get_ports "DDR4_C1_A9"] ;# Bank 71 VCCO - VCC1V2_FPGA - IO_L20N_T3L_N3_AD1N_71
-# set_property PACKAGE_PIN C12 [get_ports "DDR4_C1_A10"] ;# Bank 71 VCCO - VCC1V2_FPGA - IO_L20P_T3L_N2_AD1P_71
-# set_property IOSTANDARD SSTL12 [get_ports "DDR4_C1_A10"] ;# Bank 71 VCCO - VCC1V2_FPGA - IO_L20P_T3L_N2_AD1P_71
-# set_property PACKAGE_PIN B13 [get_ports "DDR4_C1_A11"] ;# Bank 71 VCCO - VCC1V2_FPGA - IO_L19N_T3L_N1_DBC_AD9N_71
-# set_property IOSTANDARD SSTL12 [get_ports "DDR4_C1_A11"] ;# Bank 71 VCCO - VCC1V2_FPGA - IO_L19N_T3L_N1_DBC_AD9N_71
-# set_property PACKAGE_PIN C13 [get_ports "DDR4_C1_A12"] ;# Bank 71 VCCO - VCC1V2_FPGA - IO_L19P_T3L_N0_DBC_AD9P_71
-# set_property IOSTANDARD SSTL12 [get_ports "DDR4_C1_A12"] ;# Bank 71 VCCO - VCC1V2_FPGA - IO_L19P_T3L_N0_DBC_AD9P_71
-# set_property PACKAGE_PIN D14 [get_ports "DDR4_C1_A0"] ;# Bank 71 VCCO - VCC1V2_FPGA - IO_T3U_N12_71
-# set_property IOSTANDARD SSTL12 [get_ports "DDR4_C1_A0"] ;# Bank 71 VCCO - VCC1V2_FPGA - IO_T3U_N12_71
-# set_property PACKAGE_PIN D15 [get_ports "DDR4_C1_A13"] ;# Bank 71 VCCO - VCC1V2_FPGA - IO_T2U_N12_71
-# set_property IOSTANDARD SSTL12 [get_ports "DDR4_C1_A13"] ;# Bank 71 VCCO - VCC1V2_FPGA - IO_T2U_N12_71
-# set_property PACKAGE_PIN H14 [get_ports "DDR4_C1_A14_WE_B"] ;# Bank 71 VCCO - VCC1V2_FPGA - IO_L18N_T2U_N11_AD2N_71
-# set_property IOSTANDARD SSTL12 [get_ports "DDR4_C1_A14_WE_B"] ;# Bank 71 VCCO - VCC1V2_FPGA - IO_L18N_T2U_N11_AD2N_71
-# set_property PACKAGE_PIN H15 [get_ports "DDR4_C1_A15_CAS_B"] ;# Bank 71 VCCO - VCC1V2_FPGA - IO_L18P_T2U_N10_AD2P_71
-# set_property IOSTANDARD SSTL12 [get_ports "DDR4_C1_A15_CAS_B"] ;# Bank 71 VCCO - VCC1V2_FPGA - IO_L18P_T2U_N10_AD2P_71
-# set_property PACKAGE_PIN F15 [get_ports "DDR4_C1_A16_RAS_B"] ;# Bank 71 VCCO - VCC1V2_FPGA - IO_L17N_T2U_N9_AD10N_71
-# set_property IOSTANDARD SSTL12 [get_ports "DDR4_C1_A16_RAS_B"] ;# Bank 71 VCCO - VCC1V2_FPGA - IO_L17N_T2U_N9_AD10N_71
-# set_property PACKAGE_PIN G15 [get_ports "DDR4_C1_BA0"] ;# Bank 71 VCCO - VCC1V2_FPGA - IO_L17P_T2U_N8_AD10P_71
-# set_property IOSTANDARD SSTL12 [get_ports "DDR4_C1_BA0"] ;# Bank 71 VCCO - VCC1V2_FPGA - IO_L17P_T2U_N8_AD10P_71
-# set_property PACKAGE_PIN E14 [get_ports "DDR4_C1_CK_C"] ;# Bank 71 VCCO - VCC1V2_FPGA - IO_L16N_T2U_N7_QBC_AD3N_71
-# set_property IOSTANDARD POD12 [get_ports "DDR4_C1_CK_C"] ;# Bank 71 VCCO - VCC1V2_FPGA - IO_L16N_T2U_N7_QBC_AD3N_71
-# set_property PACKAGE_PIN F14 [get_ports "DDR4_C1_CK_T"] ;# Bank 71 VCCO - VCC1V2_FPGA - IO_L16P_T2U_N6_QBC_AD3P_71
-# set_property IOSTANDARD POD12 [get_ports "DDR4_C1_CK_T"] ;# Bank 71 VCCO - VCC1V2_FPGA - IO_L16P_T2U_N6_QBC_AD3P_71
-# set_property PACKAGE_PIN G13 [get_ports "DDR4_C1_BA1"] ;# Bank 71 VCCO - VCC1V2_FPGA - IO_L15N_T2L_N5_AD11N_71
-# set_property IOSTANDARD SSTL12 [get_ports "DDR4_C1_BA1"] ;# Bank 71 VCCO - VCC1V2_FPGA - IO_L15N_T2L_N5_AD11N_71
-# set_property PACKAGE_PIN H13 [get_ports "DDR4_C1_BG0"] ;# Bank 71 VCCO - VCC1V2_FPGA - IO_L15P_T2L_N4_AD11P_71
-# set_property IOSTANDARD SSTL12 [get_ports "DDR4_C1_BG0"] ;# Bank 71 VCCO - VCC1V2_FPGA - IO_L15P_T2L_N4_AD11P_71
-# set_property PACKAGE_PIN E13 [get_ports "DDR4_C1_ACT_B"] ;# Bank 71 VCCO - VCC1V2_FPGA - IO_L14N_T2L_N3_GC_71
-# set_property IOSTANDARD SSTL12 [get_ports "DDR4_C1_ACT_B"] ;# Bank 71 VCCO - VCC1V2_FPGA - IO_L14N_T2L_N3_GC_71
-# set_property PACKAGE_PIN F13 [get_ports "DDR4_C1_CS_B"] ;# Bank 71 VCCO - VCC1V2_FPGA - IO_L14P_T2L_N2_GC_71
-# set_property IOSTANDARD SSTL12 [get_ports "DDR4_C1_CS_B"] ;# Bank 71 VCCO - VCC1V2_FPGA - IO_L14P_T2L_N2_GC_71
-# set_property PACKAGE_PIN D12 [get_ports "250MHZ_CLK1_N"] ;# Bank 71 VCCO - VCC1V2_FPGA - IO_L13N_T2L_N1_GC_QBC_71
-# set_property IOSTANDARD DIFF_SSTL12 [get_ports "250MHZ_CLK1_N"] ;# Bank 71 VCCO - VCC1V2_FPGA - IO_L13N_T2L_N1_GC_QBC_71
-# set_property PACKAGE_PIN E12 [get_ports "250MHZ_CLK1_P"] ;# Bank 71 VCCO - VCC1V2_FPGA - IO_L13P_T2L_N0_GC_QBC_71
-# set_property IOSTANDARD DIFF_SSTL12 [get_ports "250MHZ_CLK1_P"] ;# Bank 71 VCCO - VCC1V2_FPGA - IO_L13P_T2L_N0_GC_QBC_71
-# set_property PACKAGE_PIN A11 [get_ports "DDR4_C1_DQ79"] ;# Bank 71 VCCO - VCC1V2_FPGA - IO_L12N_T1U_N11_GC_71
-# set_property IOSTANDARD POD12 [get_ports "DDR4_C1_DQ79"] ;# Bank 71 VCCO - VCC1V2_FPGA - IO_L12N_T1U_N11_GC_71
-# set_property PACKAGE_PIN B11 [get_ports "DDR4_C1_DQ78"] ;# Bank 71 VCCO - VCC1V2_FPGA - IO_L12P_T1U_N10_GC_71
-# set_property IOSTANDARD POD12 [get_ports "DDR4_C1_DQ78"] ;# Bank 71 VCCO - VCC1V2_FPGA - IO_L12P_T1U_N10_GC_71
-# set_property PACKAGE_PIN B10 [get_ports "DDR4_C1_DQ77"] ;# Bank 71 VCCO - VCC1V2_FPGA - IO_L11N_T1U_N9_GC_71
-# set_property IOSTANDARD POD12 [get_ports "DDR4_C1_DQ77"] ;# Bank 71 VCCO - VCC1V2_FPGA - IO_L11N_T1U_N9_GC_71
-# set_property PACKAGE_PIN C10 [get_ports "DDR4_C1_DQ76"] ;# Bank 71 VCCO - VCC1V2_FPGA - IO_L11P_T1U_N8_GC_71
-# set_property IOSTANDARD POD12 [get_ports "DDR4_C1_DQ76"] ;# Bank 71 VCCO - VCC1V2_FPGA - IO_L11P_T1U_N8_GC_71
-# set_property PACKAGE_PIN A8 [get_ports "DDR4_C1_DQS9_C"] ;# Bank 71 VCCO - VCC1V2_FPGA - IO_L10N_T1U_N7_QBC_AD4N_71
-# set_property IOSTANDARD DIFF_POD12 [get_ports "DDR4_C1_DQS9_C"] ;# Bank 71 VCCO - VCC1V2_FPGA - IO_L10N_T1U_N7_QBC_AD4N_71
-# set_property PACKAGE_PIN A9 [get_ports "DDR4_C1_DQS9_T"] ;# Bank 71 VCCO - VCC1V2_FPGA - IO_L10P_T1U_N6_QBC_AD4P_71
-# set_property IOSTANDARD DIFF_POD12 [get_ports "DDR4_C1_DQS9_T"] ;# Bank 71 VCCO - VCC1V2_FPGA - IO_L10P_T1U_N6_QBC_AD4P_71
-# set_property PACKAGE_PIN B7 [get_ports "DDR4_C1_DQ75"] ;# Bank 71 VCCO - VCC1V2_FPGA - IO_L9N_T1L_N5_AD12N_71
-# set_property IOSTANDARD POD12 [get_ports "DDR4_C1_DQ75"] ;# Bank 71 VCCO - VCC1V2_FPGA - IO_L9N_T1L_N5_AD12N_71
-# set_property PACKAGE_PIN B8 [get_ports "DDR4_C1_DQ74"] ;# Bank 71 VCCO - VCC1V2_FPGA - IO_L9P_T1L_N4_AD12P_71
-# set_property IOSTANDARD POD12 [get_ports "DDR4_C1_DQ74"] ;# Bank 71 VCCO - VCC1V2_FPGA - IO_L9P_T1L_N4_AD12P_71
-# set_property PACKAGE_PIN C7 [get_ports "DDR4_C1_DQ73"] ;# Bank 71 VCCO - VCC1V2_FPGA - IO_L8N_T1L_N3_AD5N_71
-# set_property IOSTANDARD POD12 [get_ports "DDR4_C1_DQ73"] ;# Bank 71 VCCO - VCC1V2_FPGA - IO_L8N_T1L_N3_AD5N_71
-# set_property PACKAGE_PIN D7 [get_ports "DDR4_C1_DQ72"] ;# Bank 71 VCCO - VCC1V2_FPGA - IO_L8P_T1L_N2_AD5P_71
-# set_property IOSTANDARD POD12 [get_ports "DDR4_C1_DQ72"] ;# Bank 71 VCCO - VCC1V2_FPGA - IO_L8P_T1L_N2_AD5P_71
-# set_property PACKAGE_PIN C8 [get_ports "DDR4_C1_ODT"] ;# Bank 71 VCCO - VCC1V2_FPGA - IO_L7N_T1L_N1_QBC_AD13N_71
-# set_property IOSTANDARD SSTL12 [get_ports "DDR4_C1_ODT"] ;# Bank 71 VCCO - VCC1V2_FPGA - IO_L7N_T1L_N1_QBC_AD13N_71
-# set_property PACKAGE_PIN C9 [get_ports "DDR4_C1_DM9"] ;# Bank 71 VCCO - VCC1V2_FPGA - IO_L7P_T1L_N0_QBC_AD13P_71
-# set_property IOSTANDARD POD12 [get_ports "DDR4_C1_DM9"] ;# Bank 71 VCCO - VCC1V2_FPGA - IO_L7P_T1L_N0_QBC_AD13P_71
-# set_property PACKAGE_PIN A10 [get_ports "DDR4_C1_CKE"] ;# Bank 71 VCCO - VCC1V2_FPGA - IO_T1U_N12_71
-# set_property IOSTANDARD SSTL12 [get_ports "DDR4_C1_CKE"] ;# Bank 71 VCCO - VCC1V2_FPGA - IO_T1U_N12_71
-# #set_property PACKAGE_PIN D8 [get_ports "VRP_71"] ;# Bank 71 VCCO - VCC1V2_FPGA - IO_T0U_N12_VRP_71
-# #set_property IOSTANDARD LVCMOSxx [get_ports "VRP_71"] ;# Bank 71 VCCO - VCC1V2_FPGA - IO_T0U_N12_VRP_71
-# set_property PACKAGE_PIN D9 [get_ports "DDR4_C1_DQ7"] ;# Bank 71 VCCO - VCC1V2_FPGA - IO_L6N_T0U_N11_AD6N_71
-# set_property IOSTANDARD POD12 [get_ports "DDR4_C1_DQ7"] ;# Bank 71 VCCO - VCC1V2_FPGA - IO_L6N_T0U_N11_AD6N_71
-# set_property PACKAGE_PIN E9 [get_ports "DDR4_C1_DQ6"] ;# Bank 71 VCCO - VCC1V2_FPGA - IO_L6P_T0U_N10_AD6P_71
-# set_property IOSTANDARD POD12 [get_ports "DDR4_C1_DQ6"] ;# Bank 71 VCCO - VCC1V2_FPGA - IO_L6P_T0U_N10_AD6P_71
-# set_property PACKAGE_PIN G12 [get_ports "DDR4_C1_DQ5"] ;# Bank 71 VCCO - VCC1V2_FPGA - IO_L5N_T0U_N9_AD14N_71
-# set_property IOSTANDARD POD12 [get_ports "DDR4_C1_DQ5"] ;# Bank 71 VCCO - VCC1V2_FPGA - IO_L5N_T0U_N9_AD14N_71
-# set_property PACKAGE_PIN H12 [get_ports "DDR4_C1_DQ4"] ;# Bank 71 VCCO - VCC1V2_FPGA - IO_L5P_T0U_N8_AD14P_71
-# set_property IOSTANDARD POD12 [get_ports "DDR4_C1_DQ4"] ;# Bank 71 VCCO - VCC1V2_FPGA - IO_L5P_T0U_N8_AD14P_71
-# set_property PACKAGE_PIN D10 [get_ports "DDR4_C1_DQS0_C"] ;# Bank 71 VCCO - VCC1V2_FPGA - IO_L4N_T0U_N7_DBC_AD7N_71
-# set_property IOSTANDARD DIFF_POD12 [get_ports "DDR4_C1_DQS0_C"] ;# Bank 71 VCCO - VCC1V2_FPGA - IO_L4N_T0U_N7_DBC_AD7N_71
-# set_property PACKAGE_PIN D11 [get_ports "DDR4_C1_DQS0_T"] ;# Bank 71 VCCO - VCC1V2_FPGA - IO_L4P_T0U_N6_DBC_AD7P_71
-# set_property IOSTANDARD DIFF_POD12 [get_ports "DDR4_C1_DQS0_T"] ;# Bank 71 VCCO - VCC1V2_FPGA - IO_L4P_T0U_N6_DBC_AD7P_71
-# set_property PACKAGE_PIN F9 [get_ports "DDR4_C1_DQ3"] ;# Bank 71 VCCO - VCC1V2_FPGA - IO_L3N_T0L_N5_AD15N_71
-# set_property IOSTANDARD POD12 [get_ports "DDR4_C1_DQ3"] ;# Bank 71 VCCO - VCC1V2_FPGA - IO_L3N_T0L_N5_AD15N_71
-# set_property PACKAGE_PIN F10 [get_ports "DDR4_C1_DQ2"] ;# Bank 71 VCCO - VCC1V2_FPGA - IO_L3P_T0L_N4_AD15P_71
-# set_property IOSTANDARD POD12 [get_ports "DDR4_C1_DQ2"] ;# Bank 71 VCCO - VCC1V2_FPGA - IO_L3P_T0L_N4_AD15P_71
-# set_property PACKAGE_PIN E11 [get_ports "DDR4_C1_DQ1"] ;# Bank 71 VCCO - VCC1V2_FPGA - IO_L2N_T0L_N3_71
-# set_property IOSTANDARD POD12 [get_ports "DDR4_C1_DQ1"] ;# Bank 71 VCCO - VCC1V2_FPGA - IO_L2N_T0L_N3_71
-# set_property PACKAGE_PIN F11 [get_ports "DDR4_C1_DQ0"] ;# Bank 71 VCCO - VCC1V2_FPGA - IO_L2P_T0L_N2_71
-# set_property IOSTANDARD POD12 [get_ports "DDR4_C1_DQ0"] ;# Bank 71 VCCO - VCC1V2_FPGA - IO_L2P_T0L_N2_71
-# set_property PACKAGE_PIN G10 [get_ports "DDR4_C1_PAR"] ;# Bank 71 VCCO - VCC1V2_FPGA - IO_L1N_T0L_N1_DBC_71
-# set_property IOSTANDARD POD12 [get_ports "DDR4_C1_PAR"] ;# Bank 71 VCCO - VCC1V2_FPGA - IO_L1N_T0L_N1_DBC_71
-# set_property PACKAGE_PIN G11 [get_ports "DDR4_C1_DM0"] ;# Bank 71 VCCO - VCC1V2_FPGA - IO_L1P_T0L_N0_DBC_71
-# set_property IOSTANDARD POD12 [get_ports "DDR4_C1_DM0"] ;# Bank 71 VCCO - VCC1V2_FPGA - IO_L1P_T0L_N0_DBC_71
-# #Other net PACKAGE_PIN J15 - 7N8237 Bank 71 - VREF_71
-# set_property PACKAGE_PIN J12 [get_ports "FMCP_HSPC_HA22_N"] ;# Bank 70 VCCO - VADJ_1V8_FPGA - IO_L24N_T3U_N11_70
-# set_property IOSTANDARD LVDS [get_ports "FMCP_HSPC_HA22_N"] ;# Bank 70 VCCO - VADJ_1V8_FPGA - IO_L24N_T3U_N11_70
-# set_property PACKAGE_PIN K12 [get_ports "FMCP_HSPC_HA22_P"] ;# Bank 70 VCCO - VADJ_1V8_FPGA - IO_L24P_T3U_N10_70
-# set_property IOSTANDARD LVDS [get_ports "FMCP_HSPC_HA22_P"] ;# Bank 70 VCCO - VADJ_1V8_FPGA - IO_L24P_T3U_N10_70
-# set_property PACKAGE_PIN K13 [get_ports "FMCP_HSPC_HA21_N"] ;# Bank 70 VCCO - VADJ_1V8_FPGA - IO_L23N_T3U_N9_70
-# set_property IOSTANDARD LVDS [get_ports "FMCP_HSPC_HA21_N"] ;# Bank 70 VCCO - VADJ_1V8_FPGA - IO_L23N_T3U_N9_70
-# set_property PACKAGE_PIN K14 [get_ports "FMCP_HSPC_HA21_P"] ;# Bank 70 VCCO - VADJ_1V8_FPGA - IO_L23P_T3U_N8_70
-# set_property IOSTANDARD LVDS [get_ports "FMCP_HSPC_HA21_P"] ;# Bank 70 VCCO - VADJ_1V8_FPGA - IO_L23P_T3U_N8_70
-# set_property PACKAGE_PIN L11 [get_ports "FMCP_HSPC_HA14_N"] ;# Bank 70 VCCO - VADJ_1V8_FPGA - IO_L22N_T3U_N7_DBC_AD0N_70
-# set_property IOSTANDARD LVDS [get_ports "FMCP_HSPC_HA14_N"] ;# Bank 70 VCCO - VADJ_1V8_FPGA - IO_L22N_T3U_N7_DBC_AD0N_70
-# set_property PACKAGE_PIN M11 [get_ports "FMCP_HSPC_HA14_P"] ;# Bank 70 VCCO - VADJ_1V8_FPGA - IO_L22P_T3U_N6_DBC_AD0P_70
-# set_property IOSTANDARD LVDS [get_ports "FMCP_HSPC_HA14_P"] ;# Bank 70 VCCO - VADJ_1V8_FPGA - IO_L22P_T3U_N6_DBC_AD0P_70
-# set_property PACKAGE_PIN J11 [get_ports "FMCP_HSPC_HA23_N"] ;# Bank 70 VCCO - VADJ_1V8_FPGA - IO_L21N_T3L_N5_AD8N_70
-# set_property IOSTANDARD LVDS [get_ports "FMCP_HSPC_HA23_N"] ;# Bank 70 VCCO - VADJ_1V8_FPGA - IO_L21N_T3L_N5_AD8N_70
-# set_property PACKAGE_PIN K11 [get_ports "FMCP_HSPC_HA23_P"] ;# Bank 70 VCCO - VADJ_1V8_FPGA - IO_L21P_T3L_N4_AD8P_70
-# set_property IOSTANDARD LVDS [get_ports "FMCP_HSPC_HA23_P"] ;# Bank 70 VCCO - VADJ_1V8_FPGA - IO_L21P_T3L_N4_AD8P_70
-# set_property PACKAGE_PIN L13 [get_ports "FMCP_HSPC_HA19_N"] ;# Bank 70 VCCO - VADJ_1V8_FPGA - IO_L20N_T3L_N3_AD1N_70
-# set_property IOSTANDARD LVDS [get_ports "FMCP_HSPC_HA19_N"] ;# Bank 70 VCCO - VADJ_1V8_FPGA - IO_L20N_T3L_N3_AD1N_70
-# set_property PACKAGE_PIN L14 [get_ports "FMCP_HSPC_HA19_P"] ;# Bank 70 VCCO - VADJ_1V8_FPGA - IO_L20P_T3L_N2_AD1P_70
-# set_property IOSTANDARD LVDS [get_ports "FMCP_HSPC_HA19_P"] ;# Bank 70 VCCO - VADJ_1V8_FPGA - IO_L20P_T3L_N2_AD1P_70
-# set_property PACKAGE_PIN M12 [get_ports "FMCP_HSPC_HA15_N"] ;# Bank 70 VCCO - VADJ_1V8_FPGA - IO_L19N_T3L_N1_DBC_AD9N_70
-# set_property IOSTANDARD LVDS [get_ports "FMCP_HSPC_HA15_N"] ;# Bank 70 VCCO - VADJ_1V8_FPGA - IO_L19N_T3L_N1_DBC_AD9N_70
-# set_property PACKAGE_PIN M13 [get_ports "FMCP_HSPC_HA15_P"] ;# Bank 70 VCCO - VADJ_1V8_FPGA - IO_L19P_T3L_N0_DBC_AD9P_70
-# set_property IOSTANDARD LVDS [get_ports "FMCP_HSPC_HA15_P"] ;# Bank 70 VCCO - VADJ_1V8_FPGA - IO_L19P_T3L_N0_DBC_AD9P_70
-# set_property PACKAGE_PIN J14 [get_ports "30N3618"] ;# Bank 70 VCCO - VADJ_1V8_FPGA - IO_T3U_N12_70
-# set_property IOSTANDARD LVCMOSxx [get_ports "30N3618"] ;# Bank 70 VCCO - VADJ_1V8_FPGA - IO_T3U_N12_70
-# set_property PACKAGE_PIN N12 [get_ports "30N3617"] ;# Bank 70 VCCO - VADJ_1V8_FPGA - IO_T2U_N12_70
-# set_property IOSTANDARD LVCMOSxx [get_ports "30N3617"] ;# Bank 70 VCCO - VADJ_1V8_FPGA - IO_T2U_N12_70
-# set_property PACKAGE_PIN P12 [get_ports "FMCP_HSPC_HA11_N"] ;# Bank 70 VCCO - VADJ_1V8_FPGA - IO_L18N_T2U_N11_AD2N_70
-# set_property IOSTANDARD LVDS [get_ports "FMCP_HSPC_HA11_N"] ;# Bank 70 VCCO - VADJ_1V8_FPGA - IO_L18N_T2U_N11_AD2N_70
-# set_property PACKAGE_PIN R12 [get_ports "FMCP_HSPC_HA11_P"] ;# Bank 70 VCCO - VADJ_1V8_FPGA - IO_L18P_T2U_N10_AD2P_70
-# set_property IOSTANDARD LVDS [get_ports "FMCP_HSPC_HA11_P"] ;# Bank 70 VCCO - VADJ_1V8_FPGA - IO_L18P_T2U_N10_AD2P_70
-# set_property PACKAGE_PIN L15 [get_ports "FMCP_HSPC_HA20_N"] ;# Bank 70 VCCO - VADJ_1V8_FPGA - IO_L17N_T2U_N9_AD10N_70
-# set_property IOSTANDARD LVDS [get_ports "FMCP_HSPC_HA20_N"] ;# Bank 70 VCCO - VADJ_1V8_FPGA - IO_L17N_T2U_N9_AD10N_70
-# set_property PACKAGE_PIN M15 [get_ports "FMCP_HSPC_HA20_P"] ;# Bank 70 VCCO - VADJ_1V8_FPGA - IO_L17P_T2U_N8_AD10P_70
-# set_property IOSTANDARD LVDS [get_ports "FMCP_HSPC_HA20_P"] ;# Bank 70 VCCO - VADJ_1V8_FPGA - IO_L17P_T2U_N8_AD10P_70
-# set_property PACKAGE_PIN P11 [get_ports "FMCP_HSPC_HA17_CC_N"] ;# Bank 70 VCCO - VADJ_1V8_FPGA - IO_L16N_T2U_N7_QBC_AD3N_70
-# set_property IOSTANDARD LVDS [get_ports "FMCP_HSPC_HA17_CC_N"] ;# Bank 70 VCCO - VADJ_1V8_FPGA - IO_L16N_T2U_N7_QBC_AD3N_70
-# set_property PACKAGE_PIN R11 [get_ports "FMCP_HSPC_HA17_CC_P"] ;# Bank 70 VCCO - VADJ_1V8_FPGA - IO_L16P_T2U_N6_QBC_AD3P_70
-# set_property IOSTANDARD LVDS [get_ports "FMCP_HSPC_HA17_CC_P"] ;# Bank 70 VCCO - VADJ_1V8_FPGA - IO_L16P_T2U_N6_QBC_AD3P_70
-# set_property PACKAGE_PIN N15 [get_ports "FMCP_HSPC_HA18_N"] ;# Bank 70 VCCO - VADJ_1V8_FPGA - IO_L15N_T2L_N5_AD11N_70
-# set_property IOSTANDARD LVDS [get_ports "FMCP_HSPC_HA18_N"] ;# Bank 70 VCCO - VADJ_1V8_FPGA - IO_L15N_T2L_N5_AD11N_70
-# set_property PACKAGE_PIN P15 [get_ports "FMCP_HSPC_HA18_P"] ;# Bank 70 VCCO - VADJ_1V8_FPGA - IO_L15P_T2L_N4_AD11P_70
-# set_property IOSTANDARD LVDS [get_ports "FMCP_HSPC_HA18_P"] ;# Bank 70 VCCO - VADJ_1V8_FPGA - IO_L15P_T2L_N4_AD11P_70
-# set_property PACKAGE_PIN P14 [get_ports "FMCP_HSPC_HA05_N"] ;# Bank 70 VCCO - VADJ_1V8_FPGA - IO_L14N_T2L_N3_GC_70
-# set_property IOSTANDARD LVDS [get_ports "FMCP_HSPC_HA05_N"] ;# Bank 70 VCCO - VADJ_1V8_FPGA - IO_L14N_T2L_N3_GC_70
-# set_property PACKAGE_PIN R14 [get_ports "FMCP_HSPC_HA05_P"] ;# Bank 70 VCCO - VADJ_1V8_FPGA - IO_L14P_T2L_N2_GC_70
-# set_property IOSTANDARD LVDS [get_ports "FMCP_HSPC_HA05_P"] ;# Bank 70 VCCO - VADJ_1V8_FPGA - IO_L14P_T2L_N2_GC_70
-# set_property PACKAGE_PIN N13 [get_ports "FMCP_HSPC_HA00_CC_N"] ;# Bank 70 VCCO - VADJ_1V8_FPGA - IO_L13N_T2L_N1_GC_QBC_70
-# set_property IOSTANDARD LVDS [get_ports "FMCP_HSPC_HA00_CC_N"] ;# Bank 70 VCCO - VADJ_1V8_FPGA - IO_L13N_T2L_N1_GC_QBC_70
-# set_property PACKAGE_PIN N14 [get_ports "FMCP_HSPC_HA00_CC_P"] ;# Bank 70 VCCO - VADJ_1V8_FPGA - IO_L13P_T2L_N0_GC_QBC_70
-# set_property IOSTANDARD LVDS [get_ports "FMCP_HSPC_HA00_CC_P"] ;# Bank 70 VCCO - VADJ_1V8_FPGA - IO_L13P_T2L_N0_GC_QBC_70
-# set_property PACKAGE_PIN T13 [get_ports "FMCP_HSPC_HA06_N"] ;# Bank 70 VCCO - VADJ_1V8_FPGA - IO_L12N_T1U_N11_GC_70
-# set_property IOSTANDARD LVDS [get_ports "FMCP_HSPC_HA06_N"] ;# Bank 70 VCCO - VADJ_1V8_FPGA - IO_L12N_T1U_N11_GC_70
-# set_property PACKAGE_PIN U13 [get_ports "FMCP_HSPC_HA06_P"] ;# Bank 70 VCCO - VADJ_1V8_FPGA - IO_L12P_T1U_N10_GC_70
-# set_property IOSTANDARD LVDS [get_ports "FMCP_HSPC_HA06_P"] ;# Bank 70 VCCO - VADJ_1V8_FPGA - IO_L12P_T1U_N10_GC_70
-# set_property PACKAGE_PIN R13 [get_ports "FMCP_HSPC_HA16_N"] ;# Bank 70 VCCO - VADJ_1V8_FPGA - IO_L11N_T1U_N9_GC_70
-# set_property IOSTANDARD LVDS [get_ports "FMCP_HSPC_HA16_N"] ;# Bank 70 VCCO - VADJ_1V8_FPGA - IO_L11N_T1U_N9_GC_70
-# set_property PACKAGE_PIN T14 [get_ports "FMCP_HSPC_HA16_P"] ;# Bank 70 VCCO - VADJ_1V8_FPGA - IO_L11P_T1U_N8_GC_70
-# set_property IOSTANDARD LVDS [get_ports "FMCP_HSPC_HA16_P"] ;# Bank 70 VCCO - VADJ_1V8_FPGA - IO_L11P_T1U_N8_GC_70
-# set_property PACKAGE_PIN T11 [get_ports "FMCP_HSPC_HA08_N"] ;# Bank 70 VCCO - VADJ_1V8_FPGA - IO_L10N_T1U_N7_QBC_AD4N_70
-# set_property IOSTANDARD LVDS [get_ports "FMCP_HSPC_HA08_N"] ;# Bank 70 VCCO - VADJ_1V8_FPGA - IO_L10N_T1U_N7_QBC_AD4N_70
-# set_property PACKAGE_PIN U11 [get_ports "FMCP_HSPC_HA08_P"] ;# Bank 70 VCCO - VADJ_1V8_FPGA - IO_L10P_T1U_N6_QBC_AD4P_70
-# set_property IOSTANDARD LVDS [get_ports "FMCP_HSPC_HA08_P"] ;# Bank 70 VCCO - VADJ_1V8_FPGA - IO_L10P_T1U_N6_QBC_AD4P_70
-# set_property PACKAGE_PIN T15 [get_ports "FMCP_HSPC_HA12_N"] ;# Bank 70 VCCO - VADJ_1V8_FPGA - IO_L9N_T1L_N5_AD12N_70
-# set_property IOSTANDARD LVDS [get_ports "FMCP_HSPC_HA12_N"] ;# Bank 70 VCCO - VADJ_1V8_FPGA - IO_L9N_T1L_N5_AD12N_70
-# set_property PACKAGE_PIN T16 [get_ports "FMCP_HSPC_HA12_P"] ;# Bank 70 VCCO - VADJ_1V8_FPGA - IO_L9P_T1L_N4_AD12P_70
-# set_property IOSTANDARD LVDS [get_ports "FMCP_HSPC_HA12_P"] ;# Bank 70 VCCO - VADJ_1V8_FPGA - IO_L9P_T1L_N4_AD12P_70
-# set_property PACKAGE_PIN U16 [get_ports "FMCP_HSPC_HA10_N"] ;# Bank 70 VCCO - VADJ_1V8_FPGA - IO_L8N_T1L_N3_AD5N_70
-# set_property IOSTANDARD LVDS [get_ports "FMCP_HSPC_HA10_N"] ;# Bank 70 VCCO - VADJ_1V8_FPGA - IO_L8N_T1L_N3_AD5N_70
-# set_property PACKAGE_PIN V16 [get_ports "FMCP_HSPC_HA10_P"] ;# Bank 70 VCCO - VADJ_1V8_FPGA - IO_L8P_T1L_N2_AD5P_70
-# set_property IOSTANDARD LVDS [get_ports "FMCP_HSPC_HA10_P"] ;# Bank 70 VCCO - VADJ_1V8_FPGA - IO_L8P_T1L_N2_AD5P_70
-# set_property PACKAGE_PIN U15 [get_ports "FMCP_HSPC_HA01_CC_N"] ;# Bank 70 VCCO - VADJ_1V8_FPGA - IO_L7N_T1L_N1_QBC_AD13N_70
-# set_property IOSTANDARD LVDS [get_ports "FMCP_HSPC_HA01_CC_N"] ;# Bank 70 VCCO - VADJ_1V8_FPGA - IO_L7N_T1L_N1_QBC_AD13N_70
-# set_property PACKAGE_PIN V15 [get_ports "FMCP_HSPC_HA01_CC_P"] ;# Bank 70 VCCO - VADJ_1V8_FPGA - IO_L7P_T1L_N0_QBC_AD13P_70
-# set_property IOSTANDARD LVDS [get_ports "FMCP_HSPC_HA01_CC_P"] ;# Bank 70 VCCO - VADJ_1V8_FPGA - IO_L7P_T1L_N0_QBC_AD13P_70
-# set_property PACKAGE_PIN R16 [get_ports "30N3619"] ;# Bank 70 VCCO - VADJ_1V8_FPGA - IO_T1U_N12_70
-# set_property IOSTANDARD LVCMOSxx [get_ports "30N3619"] ;# Bank 70 VCCO - VADJ_1V8_FPGA - IO_T1U_N12_70
-# #set_property PACKAGE_PIN W15 [get_ports "VRP_70"] ;# Bank 70 VCCO - VADJ_1V8_FPGA - IO_T0U_N12_VRP_70
-# #set_property IOSTANDARD LVCMOSxx [get_ports "VRP_70"] ;# Bank 70 VCCO - VADJ_1V8_FPGA - IO_T0U_N12_VRP_70
-# set_property PACKAGE_PIN V14 [get_ports "FMCP_HSPC_HA09_N"] ;# Bank 70 VCCO - VADJ_1V8_FPGA - IO_L6N_T0U_N11_AD6N_70
-# set_property IOSTANDARD LVDS [get_ports "FMCP_HSPC_HA09_N"] ;# Bank 70 VCCO - VADJ_1V8_FPGA - IO_L6N_T0U_N11_AD6N_70
-# set_property PACKAGE_PIN W14 [get_ports "FMCP_HSPC_HA09_P"] ;# Bank 70 VCCO - VADJ_1V8_FPGA - IO_L6P_T0U_N10_AD6P_70
-# set_property IOSTANDARD LVDS [get_ports "FMCP_HSPC_HA09_P"] ;# Bank 70 VCCO - VADJ_1V8_FPGA - IO_L6P_T0U_N10_AD6P_70
-# set_property PACKAGE_PIN Y12 [get_ports "FMCP_HSPC_HA02_N"] ;# Bank 70 VCCO - VADJ_1V8_FPGA - IO_L5N_T0U_N9_AD14N_70
-# set_property IOSTANDARD LVDS [get_ports "FMCP_HSPC_HA02_N"] ;# Bank 70 VCCO - VADJ_1V8_FPGA - IO_L5N_T0U_N9_AD14N_70
-# set_property PACKAGE_PIN AA12 [get_ports "FMCP_HSPC_HA02_P"] ;# Bank 70 VCCO - VADJ_1V8_FPGA - IO_L5P_T0U_N8_AD14P_70
-# set_property IOSTANDARD LVDS [get_ports "FMCP_HSPC_HA02_P"] ;# Bank 70 VCCO - VADJ_1V8_FPGA - IO_L5P_T0U_N8_AD14P_70
-# set_property PACKAGE_PIN U12 [get_ports "FMCP_HSPC_HA13_N"] ;# Bank 70 VCCO - VADJ_1V8_FPGA - IO_L4N_T0U_N7_DBC_AD7N_70
-# set_property IOSTANDARD LVDS [get_ports "FMCP_HSPC_HA13_N"] ;# Bank 70 VCCO - VADJ_1V8_FPGA - IO_L4N_T0U_N7_DBC_AD7N_70
-# set_property PACKAGE_PIN V13 [get_ports "FMCP_HSPC_HA13_P"] ;# Bank 70 VCCO - VADJ_1V8_FPGA - IO_L4P_T0U_N6_DBC_AD7P_70
-# set_property IOSTANDARD LVDS [get_ports "FMCP_HSPC_HA13_P"] ;# Bank 70 VCCO - VADJ_1V8_FPGA - IO_L4P_T0U_N6_DBC_AD7P_70
-# set_property PACKAGE_PIN V12 [get_ports "FMCP_HSPC_HA03_N"] ;# Bank 70 VCCO - VADJ_1V8_FPGA - IO_L3N_T0L_N5_AD15N_70
-# set_property IOSTANDARD LVDS [get_ports "FMCP_HSPC_HA03_N"] ;# Bank 70 VCCO - VADJ_1V8_FPGA - IO_L3N_T0L_N5_AD15N_70
-# set_property PACKAGE_PIN W12 [get_ports "FMCP_HSPC_HA03_P"] ;# Bank 70 VCCO - VADJ_1V8_FPGA - IO_L3P_T0L_N4_AD15P_70
-# set_property IOSTANDARD LVDS [get_ports "FMCP_HSPC_HA03_P"] ;# Bank 70 VCCO - VADJ_1V8_FPGA - IO_L3P_T0L_N4_AD15P_70
-# set_property PACKAGE_PIN Y14 [get_ports "FMCP_HSPC_HA07_N"] ;# Bank 70 VCCO - VADJ_1V8_FPGA - IO_L2N_T0L_N3_70
-# set_property IOSTANDARD LVDS [get_ports "FMCP_HSPC_HA07_N"] ;# Bank 70 VCCO - VADJ_1V8_FPGA - IO_L2N_T0L_N3_70
-# set_property PACKAGE_PIN AA14 [get_ports "FMCP_HSPC_HA07_P"] ;# Bank 70 VCCO - VADJ_1V8_FPGA - IO_L2P_T0L_N2_70
-# set_property IOSTANDARD LVDS [get_ports "FMCP_HSPC_HA07_P"] ;# Bank 70 VCCO - VADJ_1V8_FPGA - IO_L2P_T0L_N2_70
-# set_property PACKAGE_PIN Y13 [get_ports "FMCP_HSPC_HA04_N"] ;# Bank 70 VCCO - VADJ_1V8_FPGA - IO_L1N_T0L_N1_DBC_70
-# set_property IOSTANDARD LVDS [get_ports "FMCP_HSPC_HA04_N"] ;# Bank 70 VCCO - VADJ_1V8_FPGA - IO_L1N_T0L_N1_DBC_70
-# set_property PACKAGE_PIN AA13 [get_ports "FMCP_HSPC_HA04_P"] ;# Bank 70 VCCO - VADJ_1V8_FPGA - IO_L1P_T0L_N0_DBC_70
-# set_property IOSTANDARD LVDS [get_ports "FMCP_HSPC_HA04_P"] ;# Bank 70 VCCO - VADJ_1V8_FPGA - IO_L1P_T0L_N0_DBC_70
-# #Other net PACKAGE_PIN AB13 - VREF_70 Bank 70 - VREF_70
-# set_property PACKAGE_PIN AV43 [get_ports "FMCP_HSPC_DP23_C2M_N"] ;# Bank 120 - MGTYTXN3_120
-# set_property PACKAGE_PIN AV42 [get_ports "FMCP_HSPC_DP23_C2M_P"] ;# Bank 120 - MGTYTXP3_120
-# set_property PACKAGE_PIN AU45 [get_ports "FMCP_HSPC_DP23_M2C_P"] ;# Bank 120 - MGTYRXP3_120
-# set_property PACKAGE_PIN AU46 [get_ports "FMCP_HSPC_DP23_M2C_N"] ;# Bank 120 - MGTYRXN3_120
-# set_property PACKAGE_PIN AM39 [get_ports "FMCP_HSPC_GBT1_5_N"] ;# Bank 120 - MGTREFCLK1N_120
-# set_property PACKAGE_PIN AM38 [get_ports "FMCP_HSPC_GBT1_5_P"] ;# Bank 120 - MGTREFCLK1P_120
-# set_property PACKAGE_PIN AY43 [get_ports "FMCP_HSPC_DP22_C2M_N"] ;# Bank 120 - MGTYTXN2_120
-# set_property PACKAGE_PIN AY42 [get_ports "FMCP_HSPC_DP22_C2M_P"] ;# Bank 120 - MGTYTXP2_120
-# set_property PACKAGE_PIN AW45 [get_ports "FMCP_HSPC_DP22_M2C_P"] ;# Bank 120 - MGTYRXP2_120
-# set_property PACKAGE_PIN AW46 [get_ports "FMCP_HSPC_DP22_M2C_N"] ;# Bank 120 - MGTYRXN2_120
-# set_property PACKAGE_PIN BB43 [get_ports "FMCP_HSPC_DP21_C2M_N"] ;# Bank 120 - MGTYTXN1_120
-# set_property PACKAGE_PIN BB42 [get_ports "FMCP_HSPC_DP21_C2M_P"] ;# Bank 120 - MGTYTXP1_120
-# set_property PACKAGE_PIN BA45 [get_ports "FMCP_HSPC_DP21_M2C_P"] ;# Bank 120 - MGTYRXP1_120
-# set_property PACKAGE_PIN BA46 [get_ports "FMCP_HSPC_DP21_M2C_N"] ;# Bank 120 - MGTYRXN1_120
-# set_property PACKAGE_PIN AN41 [get_ports "FMCP_HSPC_GBTCLK5_M2C_C_N"] ;# Bank 120 - MGTREFCLK0N_120
-# set_property PACKAGE_PIN AN40 [get_ports "FMCP_HSPC_GBTCLK5_M2C_C_P"] ;# Bank 120 - MGTREFCLK0P_120
-# set_property PACKAGE_PIN BD43 [get_ports "FMCP_HSPC_DP20_C2M_N"] ;# Bank 120 - MGTYTXN0_120
-# set_property PACKAGE_PIN BD42 [get_ports "FMCP_HSPC_DP20_C2M_P"] ;# Bank 120 - MGTYTXP0_120
-# set_property PACKAGE_PIN BC45 [get_ports "FMCP_HSPC_DP20_M2C_P"] ;# Bank 120 - MGTYRXP0_120
-# set_property PACKAGE_PIN BC46 [get_ports "FMCP_HSPC_DP20_M2C_N"] ;# Bank 120 - MGTYRXN0_120
-# set_property PACKAGE_PIN AL41 [get_ports "FMCP_HSPC_DP3_C2M_N"] ;# Bank 121 - MGTYTXN3_121
-# set_property PACKAGE_PIN AL40 [get_ports "FMCP_HSPC_DP3_C2M_P"] ;# Bank 121 - MGTYTXP3_121
-# set_property PACKAGE_PIN AJ45 [get_ports "FMCP_HSPC_DP3_M2C_P"] ;# Bank 121 - MGTYRXP3_121
-# set_property PACKAGE_PIN AJ46 [get_ports "FMCP_HSPC_DP3_M2C_N"] ;# Bank 121 - MGTYRXN3_121
-# set_property PACKAGE_PIN AH39 [get_ports "FMCP_HSPC_GBT1_0_N"] ;# Bank 121 - MGTREFCLK1N_121
-# set_property PACKAGE_PIN AH38 [get_ports "FMCP_HSPC_GBT1_0_P"] ;# Bank 121 - MGTREFCLK1P_121
-# set_property PACKAGE_PIN AM43 [get_ports "FMCP_HSPC_DP2_C2M_N"] ;# Bank 121 - MGTYTXN2_121
-# set_property PACKAGE_PIN AM42 [get_ports "FMCP_HSPC_DP2_C2M_P"] ;# Bank 121 - MGTYTXP2_121
-# set_property PACKAGE_PIN AL45 [get_ports "FMCP_HSPC_DP2_M2C_P"] ;# Bank 121 - MGTYRXP2_121
-# set_property PACKAGE_PIN AL46 [get_ports "FMCP_HSPC_DP2_M2C_N"] ;# Bank 121 - MGTYRXN2_121
-# #Other net PACKAGE_PIN BF42 - MGTAVTT_FPGA Bank 121 - MGTAVTTRCAL_LS
-# set_property PACKAGE_PIN BF43 [get_ports "MGTRREF_121"] ;# Bank 121 - MGTRREF_LS
-# set_property PACKAGE_PIN AP43 [get_ports "FMCP_HSPC_DP1_C2M_N"] ;# Bank 121 - MGTYTXN1_121
-# set_property PACKAGE_PIN AP42 [get_ports "FMCP_HSPC_DP1_C2M_P"] ;# Bank 121 - MGTYTXP1_121
-# set_property PACKAGE_PIN AN45 [get_ports "FMCP_HSPC_DP1_M2C_P"] ;# Bank 121 - MGTYRXP1_121
-# set_property PACKAGE_PIN AN46 [get_ports "FMCP_HSPC_DP1_M2C_N"] ;# Bank 121 - MGTYRXN1_121
-# set_property PACKAGE_PIN AK39 [get_ports "FMCP_HSPC_GBT0_0_N"] ;# Bank 121 - MGTREFCLK0N_121
-# set_property PACKAGE_PIN AK38 [get_ports "FMCP_HSPC_GBT0_0_P"] ;# Bank 121 - MGTREFCLK0P_121
-# set_property PACKAGE_PIN AT43 [get_ports "FMCP_HSPC_DP0_C2M_N"] ;# Bank 121 - MGTYTXN0_121
-# set_property PACKAGE_PIN AT42 [get_ports "FMCP_HSPC_DP0_C2M_P"] ;# Bank 121 - MGTYTXP0_121
-# set_property PACKAGE_PIN AR45 [get_ports "FMCP_HSPC_DP0_M2C_P"] ;# Bank 121 - MGTYRXP0_121
-# set_property PACKAGE_PIN AR46 [get_ports "FMCP_HSPC_DP0_M2C_N"] ;# Bank 121 - MGTYRXN0_121
-# set_property PACKAGE_PIN AE41 [get_ports "FMCP_HSPC_DP11_C2M_N"] ;# Bank 122 - MGTYTXN3_122
-# set_property PACKAGE_PIN AE40 [get_ports "FMCP_HSPC_DP11_C2M_P"] ;# Bank 122 - MGTYTXP3_122
-# set_property PACKAGE_PIN AD43 [get_ports "FMCP_HSPC_DP11_M2C_P"] ;# Bank 122 - MGTYRXP3_122
-# set_property PACKAGE_PIN AD44 [get_ports "FMCP_HSPC_DP11_M2C_N"] ;# Bank 122 - MGTYRXN3_122
-# set_property PACKAGE_PIN AD39 [get_ports "FMCP_HSPC_GBT1_2_N"] ;# Bank 122 - MGTREFCLK1N_122
-# set_property PACKAGE_PIN AD38 [get_ports "FMCP_HSPC_GBT1_2_P"] ;# Bank 122 - MGTREFCLK1P_122
-# set_property PACKAGE_PIN AG41 [get_ports "FMCP_HSPC_DP10_C2M_N"] ;# Bank 122 - MGTYTXN2_122
-# set_property PACKAGE_PIN AG40 [get_ports "FMCP_HSPC_DP10_C2M_P"] ;# Bank 122 - MGTYTXP2_122
-# set_property PACKAGE_PIN AE45 [get_ports "FMCP_HSPC_DP10_M2C_P"] ;# Bank 122 - MGTYRXP2_122
-# set_property PACKAGE_PIN AE46 [get_ports "FMCP_HSPC_DP10_M2C_N"] ;# Bank 122 - MGTYRXN2_122
-# set_property PACKAGE_PIN AJ41 [get_ports "FMCP_HSPC_DP9_C2M_N"] ;# Bank 122 - MGTYTXN1_122
-# set_property PACKAGE_PIN AJ40 [get_ports "FMCP_HSPC_DP9_C2M_P"] ;# Bank 122 - MGTYTXP1_122
-# set_property PACKAGE_PIN AF43 [get_ports "FMCP_HSPC_DP9_M2C_P"] ;# Bank 122 - MGTYRXP1_122
-# set_property PACKAGE_PIN AF44 [get_ports "FMCP_HSPC_DP9_M2C_N"] ;# Bank 122 - MGTYRXN1_122
-# set_property PACKAGE_PIN AF39 [get_ports "FMCP_HSPC_GBTCLK2_M2C_C_N"] ;# Bank 122 - MGTREFCLK0N_122
-# set_property PACKAGE_PIN AF38 [get_ports "FMCP_HSPC_GBTCLK2_M2C_C_P"] ;# Bank 122 - MGTREFCLK0P_122
-# set_property PACKAGE_PIN AK43 [get_ports "FMCP_HSPC_DP8_C2M_N"] ;# Bank 122 - MGTYTXN0_122
-# set_property PACKAGE_PIN AK42 [get_ports "FMCP_HSPC_DP8_C2M_P"] ;# Bank 122 - MGTYTXP0_122
-# set_property PACKAGE_PIN AG45 [get_ports "FMCP_HSPC_DP8_M2C_P"] ;# Bank 122 - MGTYRXP0_122
-# set_property PACKAGE_PIN AG46 [get_ports "FMCP_HSPC_DP8_M2C_N"] ;# Bank 122 - MGTYRXN0_122
-# set_property PACKAGE_PIN U41 [get_ports "FMCP_HSPC_DP15_C2M_N"] ;# Bank 125 - MGTYTXN3_125
-# set_property PACKAGE_PIN U40 [get_ports "FMCP_HSPC_DP15_C2M_P"] ;# Bank 125 - MGTYTXP3_125
-# set_property PACKAGE_PIN Y43 [get_ports "FMCP_HSPC_DP15_M2C_P"] ;# Bank 125 - MGTYRXP3_125
-# set_property PACKAGE_PIN Y44 [get_ports "FMCP_HSPC_DP15_M2C_N"] ;# Bank 125 - MGTYRXN3_125
-# set_property PACKAGE_PIN Y39 [get_ports "FMCP_HSPC_GBT1_3_N"] ;# Bank 125 - MGTREFCLK1N_125
-# set_property PACKAGE_PIN Y38 [get_ports "FMCP_HSPC_GBT1_3_P"] ;# Bank 125 - MGTREFCLK1P_125
-# set_property PACKAGE_PIN W41 [get_ports "FMCP_HSPC_DP14_C2M_N"] ;# Bank 125 - MGTYTXN2_125
-# set_property PACKAGE_PIN W40 [get_ports "FMCP_HSPC_DP14_C2M_P"] ;# Bank 125 - MGTYTXP2_125
-# set_property PACKAGE_PIN AA45 [get_ports "FMCP_HSPC_DP14_M2C_P"] ;# Bank 125 - MGTYRXP2_125
-# set_property PACKAGE_PIN AA46 [get_ports "FMCP_HSPC_DP14_M2C_N"] ;# Bank 125 - MGTYRXN2_125
-# set_property PACKAGE_PIN AA41 [get_ports "FMCP_HSPC_DP13_C2M_N"] ;# Bank 125 - MGTYTXN1_125
-# set_property PACKAGE_PIN AA40 [get_ports "FMCP_HSPC_DP13_C2M_P"] ;# Bank 125 - MGTYTXP1_125
-# set_property PACKAGE_PIN AB43 [get_ports "FMCP_HSPC_DP13_M2C_P"] ;# Bank 125 - MGTYRXP1_125
-# set_property PACKAGE_PIN AB44 [get_ports "FMCP_HSPC_DP13_M2C_N"] ;# Bank 125 - MGTYRXN1_125
-# set_property PACKAGE_PIN AB39 [get_ports "FMCP_HSPC_GBTCLK3_M2C_C_N"] ;# Bank 125 - MGTREFCLK0N_125
-# set_property PACKAGE_PIN AB38 [get_ports "FMCP_HSPC_GBTCLK3_M2C_C_P"] ;# Bank 125 - MGTREFCLK0P_125
-# set_property PACKAGE_PIN AC41 [get_ports "FMCP_HSPC_DP12_C2M_N"] ;# Bank 125 - MGTYTXN0_125
-# set_property PACKAGE_PIN AC40 [get_ports "FMCP_HSPC_DP12_C2M_P"] ;# Bank 125 - MGTYTXP0_125
-# set_property PACKAGE_PIN AC45 [get_ports "FMCP_HSPC_DP12_M2C_P"] ;# Bank 125 - MGTYRXP0_125
-# set_property PACKAGE_PIN AC46 [get_ports "FMCP_HSPC_DP12_M2C_N"] ;# Bank 125 - MGTYRXN0_125
-# set_property PACKAGE_PIN K43 [get_ports "FMCP_HSPC_DP7_C2M_N"] ;# Bank 126 - MGTYTXN3_126
-# set_property PACKAGE_PIN K42 [get_ports "FMCP_HSPC_DP7_C2M_P"] ;# Bank 126 - MGTYTXP3_126
-# set_property PACKAGE_PIN N45 [get_ports "FMCP_HSPC_DP7_M2C_P"] ;# Bank 126 - MGTYRXP3_126
-# set_property PACKAGE_PIN N46 [get_ports "FMCP_HSPC_DP7_M2C_N"] ;# Bank 126 - MGTYRXN3_126
-# set_property PACKAGE_PIN T39 [get_ports "FMCP_HSPC_GBT1_1_N"] ;# Bank 126 - MGTREFCLK1N_126
-# set_property PACKAGE_PIN T38 [get_ports "FMCP_HSPC_GBT1_1_P"] ;# Bank 126 - MGTREFCLK1P_126
-# set_property PACKAGE_PIN M43 [get_ports "FMCP_HSPC_DP6_C2M_N"] ;# Bank 126 - MGTYTXN2_126
-# set_property PACKAGE_PIN M42 [get_ports "FMCP_HSPC_DP6_C2M_P"] ;# Bank 126 - MGTYTXP2_126
-# set_property PACKAGE_PIN R45 [get_ports "FMCP_HSPC_DP6_M2C_P"] ;# Bank 126 - MGTYRXP2_126
-# set_property PACKAGE_PIN R46 [get_ports "FMCP_HSPC_DP6_M2C_N"] ;# Bank 126 - MGTYRXN2_126
-# #Other net PACKAGE_PIN L40 - MGTAVTT_FPGA Bank 126 - MGTAVTTRCAL_LN
-# set_property PACKAGE_PIN L41 [get_ports "MGTRREF_126"] ;# Bank 126 - MGTRREF_LN
-# set_property PACKAGE_PIN P43 [get_ports "FMCP_HSPC_DP5_C2M_N"] ;# Bank 126 - MGTYTXN1_126
-# set_property PACKAGE_PIN P42 [get_ports "FMCP_HSPC_DP5_C2M_P"] ;# Bank 126 - MGTYTXP1_126
-# set_property PACKAGE_PIN U45 [get_ports "FMCP_HSPC_DP5_M2C_P"] ;# Bank 126 - MGTYRXP1_126
-# set_property PACKAGE_PIN U46 [get_ports "FMCP_HSPC_DP5_M2C_N"] ;# Bank 126 - MGTYRXN1_126
-# set_property PACKAGE_PIN V39 [get_ports "FMCP_HSPC_GBT0_1_N"] ;# Bank 126 - MGTREFCLK0N_126
-# set_property PACKAGE_PIN V38 [get_ports "FMCP_HSPC_GBT0_1_P"] ;# Bank 126 - MGTREFCLK0P_126
-# set_property PACKAGE_PIN T43 [get_ports "FMCP_HSPC_DP4_C2M_N"] ;# Bank 126 - MGTYTXN0_126
-# set_property PACKAGE_PIN T42 [get_ports "FMCP_HSPC_DP4_C2M_P"] ;# Bank 126 - MGTYTXP0_126
-# set_property PACKAGE_PIN W45 [get_ports "FMCP_HSPC_DP4_M2C_P"] ;# Bank 126 - MGTYRXP0_126
-# set_property PACKAGE_PIN W46 [get_ports "FMCP_HSPC_DP4_M2C_N"] ;# Bank 126 - MGTYRXN0_126
-# set_property PACKAGE_PIN B43 [get_ports "FMCP_HSPC_DP19_C2M_N"] ;# Bank 127 - MGTYTXN3_127
-# set_property PACKAGE_PIN B42 [get_ports "FMCP_HSPC_DP19_C2M_P"] ;# Bank 127 - MGTYTXP3_127
-# set_property PACKAGE_PIN E45 [get_ports "FMCP_HSPC_DP19_M2C_P"] ;# Bank 127 - MGTYRXP3_127
-# set_property PACKAGE_PIN E46 [get_ports "FMCP_HSPC_DP19_M2C_N"] ;# Bank 127 - MGTYRXN3_127
-# set_property PACKAGE_PIN N41 [get_ports "FMCP_HSPC_GBT1_4_N"] ;# Bank 127 - MGTREFCLK1N_127
-# set_property PACKAGE_PIN N40 [get_ports "FMCP_HSPC_GBT1_4_P"] ;# Bank 127 - MGTREFCLK1P_127
-# set_property PACKAGE_PIN D43 [get_ports "FMCP_HSPC_DP18_C2M_N"] ;# Bank 127 - MGTYTXN2_127
-# set_property PACKAGE_PIN D42 [get_ports "FMCP_HSPC_DP18_C2M_P"] ;# Bank 127 - MGTYTXP2_127
-# set_property PACKAGE_PIN G45 [get_ports "FMCP_HSPC_DP18_M2C_P"] ;# Bank 127 - MGTYRXP2_127
-# set_property PACKAGE_PIN G46 [get_ports "FMCP_HSPC_DP18_M2C_N"] ;# Bank 127 - MGTYRXN2_127
-# set_property PACKAGE_PIN F43 [get_ports "FMCP_HSPC_DP17_C2M_N"] ;# Bank 127 - MGTYTXN1_127
-# set_property PACKAGE_PIN F42 [get_ports "FMCP_HSPC_DP17_C2M_P"] ;# Bank 127 - MGTYTXP1_127
-# set_property PACKAGE_PIN J45 [get_ports "FMCP_HSPC_DP17_M2C_P"] ;# Bank 127 - MGTYRXP1_127
-# set_property PACKAGE_PIN J46 [get_ports "FMCP_HSPC_DP17_M2C_N"] ;# Bank 127 - MGTYRXN1_127
-# set_property PACKAGE_PIN R41 [get_ports "FMCP_HSPC_GBTCLK4_M2C_C_N"] ;# Bank 127 - MGTREFCLK0N_127
-# set_property PACKAGE_PIN R40 [get_ports "FMCP_HSPC_GBTCLK4_M2C_C_P"] ;# Bank 127 - MGTREFCLK0P_127
-# set_property PACKAGE_PIN H43 [get_ports "FMCP_HSPC_DP16_C2M_N"] ;# Bank 127 - MGTYTXN0_127
-# set_property PACKAGE_PIN H42 [get_ports "FMCP_HSPC_DP16_C2M_P"] ;# Bank 127 - MGTYTXP0_127
-# set_property PACKAGE_PIN L45 [get_ports "FMCP_HSPC_DP16_M2C_P"] ;# Bank 127 - MGTYRXP0_127
-# set_property PACKAGE_PIN L46 [get_ports "FMCP_HSPC_DP16_M2C_N"] ;# Bank 127 - MGTYRXN0_127
-# set_property PACKAGE_PIN AW5 [get_ports "PCIE_TX12_P"] ;# Bank 224 - MGTYTXP3_224
-# set_property PACKAGE_PIN AT2 [get_ports "PCIE_RX12_P"] ;# Bank 224 - MGTYRXP3_224
-# set_property PACKAGE_PIN AT1 [get_ports "PCIE_RX12_N"] ;# Bank 224 - MGTYRXN3_224
-# set_property PACKAGE_PIN AW4 [get_ports "PCIE_TX12_N"] ;# Bank 224 - MGTYTXN3_224
-# set_property PACKAGE_PIN AN9 [get_ports "11N8666"] ;# Bank 224 - MGTREFCLK1P_224
-# set_property PACKAGE_PIN AN8 [get_ports "11N8667"] ;# Bank 224 - MGTREFCLK1N_224
-# set_property PACKAGE_PIN BA5 [get_ports "PCIE_TX13_P"] ;# Bank 224 - MGTYTXP2_224
-# set_property PACKAGE_PIN AV2 [get_ports "PCIE_RX13_P"] ;# Bank 224 - MGTYRXP2_224
-# set_property PACKAGE_PIN AV1 [get_ports "PCIE_RX13_N"] ;# Bank 224 - MGTYRXN2_224
-# set_property PACKAGE_PIN BA4 [get_ports "PCIE_TX13_N"] ;# Bank 224 - MGTYTXN2_224
-# set_property PACKAGE_PIN BC5 [get_ports "PCIE_TX14_P"] ;# Bank 224 - MGTYTXP1_224
-# set_property PACKAGE_PIN AY2 [get_ports "PCIE_RX14_P"] ;# Bank 224 - MGTYRXP1_224
-# set_property PACKAGE_PIN AY1 [get_ports "PCIE_RX14_N"] ;# Bank 224 - MGTYRXN1_224
-# set_property PACKAGE_PIN BC4 [get_ports "PCIE_TX14_N"] ;# Bank 224 - MGTYTXN1_224
-# set_property PACKAGE_PIN AR9 [get_ports "11N9044"] ;# Bank 224 - MGTREFCLK0P_224
-# set_property PACKAGE_PIN AR8 [get_ports "11N9045"] ;# Bank 224 - MGTREFCLK0N_224
-# set_property PACKAGE_PIN BE5 [get_ports "PCIE_TX15_P"] ;# Bank 224 - MGTYTXP0_224
-# set_property PACKAGE_PIN BB2 [get_ports "PCIE_RX15_P"] ;# Bank 224 - MGTYRXP0_224
-# set_property PACKAGE_PIN BB1 [get_ports "PCIE_RX15_N"] ;# Bank 224 - MGTYRXN0_224
-# set_property PACKAGE_PIN BE4 [get_ports "PCIE_TX15_N"] ;# Bank 224 - MGTYTXN0_224
-# set_property PACKAGE_PIN AP7 [get_ports "PCIE_TX8_P"] ;# Bank 225 - MGTYTXP3_225
-# set_property PACKAGE_PIN AJ4 [get_ports "PCIE_RX8_P"] ;# Bank 225 - MGTYRXP3_225
-# set_property PACKAGE_PIN AJ3 [get_ports "PCIE_RX8_N"] ;# Bank 225 - MGTYRXN3_225
-# set_property PACKAGE_PIN AP6 [get_ports "PCIE_TX8_N"] ;# Bank 225 - MGTYTXN3_225
-# set_property PACKAGE_PIN AJ9 [get_ports "MGT_SI570_CLOCK1_C_P"] ;# Bank 225 - MGTREFCLK1P_225
-# set_property PACKAGE_PIN AJ8 [get_ports "MGT_SI570_CLOCK1_C_N"] ;# Bank 225 - MGTREFCLK1N_225
-# set_property PACKAGE_PIN AR5 [get_ports "PCIE_TX9_P"] ;# Bank 225 - MGTYTXP2_225
-# set_property PACKAGE_PIN AK2 [get_ports "PCIE_RX9_P"] ;# Bank 225 - MGTYRXP2_225
-# set_property PACKAGE_PIN AK1 [get_ports "PCIE_RX9_N"] ;# Bank 225 - MGTYRXN2_225
-# set_property PACKAGE_PIN AR4 [get_ports "PCIE_TX9_N"] ;# Bank 225 - MGTYTXN2_225
-# set_property PACKAGE_PIN AT7 [get_ports "PCIE_TX10_P"] ;# Bank 225 - MGTYTXP1_225
-# set_property PACKAGE_PIN AM2 [get_ports "PCIE_RX10_P"] ;# Bank 225 - MGTYRXP1_225
-# set_property PACKAGE_PIN AM1 [get_ports "PCIE_RX10_N"] ;# Bank 225 - MGTYRXN1_225
-# set_property PACKAGE_PIN AT6 [get_ports "PCIE_TX10_N"] ;# Bank 225 - MGTYTXN1_225
-# set_property PACKAGE_PIN AL9 [get_ports "PCIE_CLK1_P"] ;# Bank 225 - MGTREFCLK0P_225
-# set_property PACKAGE_PIN AL8 [get_ports "PCIE_CLK1_N"] ;# Bank 225 - MGTREFCLK0N_225
-# set_property PACKAGE_PIN AU5 [get_ports "PCIE_TX11_P"] ;# Bank 225 - MGTYTXP0_225
-# set_property PACKAGE_PIN AP2 [get_ports "PCIE_RX11_P"] ;# Bank 225 - MGTYRXP0_225
-# set_property PACKAGE_PIN AP1 [get_ports "PCIE_RX11_N"] ;# Bank 225 - MGTYRXN0_225
-# set_property PACKAGE_PIN AU4 [get_ports "PCIE_TX11_N"] ;# Bank 225 - MGTYTXN0_225
-# set_property PACKAGE_PIN AH7 [get_ports "PCIE_TX4_P"] ;# Bank 226 - MGTYTXP3_226
-# set_property PACKAGE_PIN AE4 [get_ports "PCIE_RX4_P"] ;# Bank 226 - MGTYRXP3_226
-# set_property PACKAGE_PIN AE3 [get_ports "PCIE_RX4_N"] ;# Bank 226 - MGTYRXN3_226
-# set_property PACKAGE_PIN AH6 [get_ports "PCIE_TX4_N"] ;# Bank 226 - MGTYTXN3_226
-# set_property PACKAGE_PIN AE9 [get_ports "11N5839"] ;# Bank 226 - MGTREFCLK1P_226
-# set_property PACKAGE_PIN AE8 [get_ports "11N5838"] ;# Bank 226 - MGTREFCLK1N_226
-# set_property PACKAGE_PIN AK7 [get_ports "PCIE_TX5_P"] ;# Bank 226 - MGTYTXP2_226
-# set_property PACKAGE_PIN AF2 [get_ports "PCIE_RX5_P"] ;# Bank 226 - MGTYRXP2_226
-# set_property PACKAGE_PIN AF1 [get_ports "PCIE_RX5_N"] ;# Bank 226 - MGTYRXN2_226
-# set_property PACKAGE_PIN AK6 [get_ports "PCIE_TX5_N"] ;# Bank 226 - MGTYTXN2_226
-# set_property PACKAGE_PIN BD2 [get_ports "MGTRREF_226"] ;# Bank 226 - MGTRREF_RS
-# #Other net PACKAGE_PIN BD3 - MGTAVTT_FPGA Bank 226 - MGTAVTTRCAL_RS
-# set_property PACKAGE_PIN AM7 [get_ports "PCIE_TX6_P"] ;# Bank 226 - MGTYTXP1_226
-# set_property PACKAGE_PIN AG4 [get_ports "PCIE_RX6_P"] ;# Bank 226 - MGTYRXP1_226
-# set_property PACKAGE_PIN AG3 [get_ports "PCIE_RX6_N"] ;# Bank 226 - MGTYRXN1_226
-# set_property PACKAGE_PIN AM6 [get_ports "PCIE_TX6_N"] ;# Bank 226 - MGTYTXN1_226
-# set_property PACKAGE_PIN AG9 [get_ports "MGT226_CLK0_P"] ;# Bank 226 - MGTREFCLK0P_226
-# set_property PACKAGE_PIN AG8 [get_ports "MGT226_CLK0_N"] ;# Bank 226 - MGTREFCLK0N_226
-# set_property PACKAGE_PIN AN5 [get_ports "PCIE_TX7_P"] ;# Bank 226 - MGTYTXP0_226
-# set_property PACKAGE_PIN AH2 [get_ports "PCIE_RX7_P"] ;# Bank 226 - MGTYRXP0_226
-# set_property PACKAGE_PIN AH1 [get_ports "PCIE_RX7_N"] ;# Bank 226 - MGTYRXN0_226
-# set_property PACKAGE_PIN AN4 [get_ports "PCIE_TX7_N"] ;# Bank 226 - MGTYTXN0_226
-# set_property PACKAGE_PIN Y7 [get_ports "PCIE_TX0_P"] ;# Bank 227 - MGTYTXP3_227
-# set_property PACKAGE_PIN AA4 [get_ports "PCIE_RX0_P"] ;# Bank 227 - MGTYRXP3_227
-# set_property PACKAGE_PIN AA3 [get_ports "PCIE_RX0_N"] ;# Bank 227 - MGTYRXN3_227
-# set_property PACKAGE_PIN Y6 [get_ports "PCIE_TX0_N"] ;# Bank 227 - MGTYTXN3_227
-# set_property PACKAGE_PIN AA9 [get_ports "11N8774"] ;# Bank 227 - MGTREFCLK1P_227
-# set_property PACKAGE_PIN AA8 [get_ports "11N8775"] ;# Bank 227 - MGTREFCLK1N_227
-# set_property PACKAGE_PIN AB7 [get_ports "PCIE_TX1_P"] ;# Bank 227 - MGTYTXP2_227
-# set_property PACKAGE_PIN AB2 [get_ports "PCIE_RX1_P"] ;# Bank 227 - MGTYRXP2_227
-# set_property PACKAGE_PIN AB1 [get_ports "PCIE_RX1_N"] ;# Bank 227 - MGTYRXN2_227
-# set_property PACKAGE_PIN AB6 [get_ports "PCIE_TX1_N"] ;# Bank 227 - MGTYTXN2_227
-# set_property PACKAGE_PIN AD7 [get_ports "PCIE_TX2_P"] ;# Bank 227 - MGTYTXP1_227
-# set_property PACKAGE_PIN AC4 [get_ports "PCIE_RX2_P"] ;# Bank 227 - MGTYRXP1_227
-# set_property PACKAGE_PIN AC3 [get_ports "PCIE_RX2_N"] ;# Bank 227 - MGTYRXN1_227
-# set_property PACKAGE_PIN AD6 [get_ports "PCIE_TX2_N"] ;# Bank 227 - MGTYTXN1_227
-# set_property PACKAGE_PIN AC9 [get_ports "PCIE_CLK2_P"] ;# Bank 227 - MGTREFCLK0P_227
-# set_property PACKAGE_PIN AC8 [get_ports "PCIE_CLK2_N"] ;# Bank 227 - MGTREFCLK0N_227
-# set_property PACKAGE_PIN AF7 [get_ports "PCIE_TX3_P"] ;# Bank 227 - MGTYTXP0_227
-# set_property PACKAGE_PIN AD2 [get_ports "PCIE_RX3_P"] ;# Bank 227 - MGTYRXP0_227
-# set_property PACKAGE_PIN AD1 [get_ports "PCIE_RX3_N"] ;# Bank 227 - MGTYRXN0_227
-# set_property PACKAGE_PIN AF6 [get_ports "PCIE_TX3_N"] ;# Bank 227 - MGTYTXN0_227
-# set_property PACKAGE_PIN M7 [get_ports "QSFP1_TX4_P"] ;# Bank 231 - MGTYTXP3_231
-# set_property PACKAGE_PIN U4 [get_ports "QSFP1_RX4_P"] ;# Bank 231 - MGTYRXP3_231
-# set_property PACKAGE_PIN U3 [get_ports "QSFP1_RX4_N"] ;# Bank 231 - MGTYRXN3_231
-# set_property PACKAGE_PIN M6 [get_ports "QSFP1_TX4_N"] ;# Bank 231 - MGTYTXN3_231
-# set_property PACKAGE_PIN U9 [get_ports "SI5328_CLOCK1_C_P"] ;# Bank 231 - MGTREFCLK1P_231
-# set_property PACKAGE_PIN U8 [get_ports "SI5328_CLOCK1_C_N"] ;# Bank 231 - MGTREFCLK1N_231
-# set_property PACKAGE_PIN P7 [get_ports "QSFP1_TX3_P"] ;# Bank 231 - MGTYTXP2_231
-# set_property PACKAGE_PIN V2 [get_ports "QSFP1_RX3_P"] ;# Bank 231 - MGTYRXP2_231
-# set_property PACKAGE_PIN V1 [get_ports "QSFP1_RX3_N"] ;# Bank 231 - MGTYRXN2_231
-# set_property PACKAGE_PIN P6 [get_ports "QSFP1_TX3_N"] ;# Bank 231 - MGTYTXN2_231
-# set_property PACKAGE_PIN A4 [get_ports "MGTRREF_231"] ;# Bank 231 - MGTRREF_RN
-# #Other net PACKAGE_PIN A5 - MGTAVTT_FPGA Bank 231 - MGTAVTTRCAL_RN
-# set_property PACKAGE_PIN T7 [get_ports "QSFP1_TX2_P"] ;# Bank 231 - MGTYTXP1_231
-# set_property PACKAGE_PIN W4 [get_ports "QSFP1_RX2_P"] ;# Bank 231 - MGTYRXP1_231
-# set_property PACKAGE_PIN W3 [get_ports "QSFP1_RX2_N"] ;# Bank 231 - MGTYRXN1_231
-# set_property PACKAGE_PIN T6 [get_ports "QSFP1_TX2_N"] ;# Bank 231 - MGTYTXN1_231
-# set_property PACKAGE_PIN W9 [get_ports "QSFP_SI570_CLOCK_C_P"] ;# Bank 231 - MGTREFCLK0P_231
-# set_property PACKAGE_PIN W8 [get_ports "QSFP_SI570_CLOCK_C_N"] ;# Bank 231 - MGTREFCLK0N_231
-# set_property PACKAGE_PIN V7 [get_ports "QSFP1_TX1_P"] ;# Bank 231 - MGTYTXP0_231
-# set_property PACKAGE_PIN Y2 [get_ports "QSFP1_RX1_P"] ;# Bank 231 - MGTYRXP0_231
-# set_property PACKAGE_PIN Y1 [get_ports "QSFP1_RX1_N"] ;# Bank 231 - MGTYRXN0_231
-# set_property PACKAGE_PIN V6 [get_ports "QSFP1_TX1_N"] ;# Bank 231 - MGTYTXN0_231
-# set_property PACKAGE_PIN H7 [get_ports "QSFP2_TX4_P"] ;# Bank 232 - MGTYTXP3_232
-# set_property PACKAGE_PIN M2 [get_ports "QSFP2_RX4_P"] ;# Bank 232 - MGTYRXP3_232
-# set_property PACKAGE_PIN M1 [get_ports "QSFP2_RX4_N"] ;# Bank 232 - MGTYRXN3_232
-# set_property PACKAGE_PIN H6 [get_ports "QSFP2_TX4_N"] ;# Bank 232 - MGTYTXN3_232
-# set_property PACKAGE_PIN N9 [get_ports "SI5328_CLOCK2_C_P"] ;# Bank 232 - MGTREFCLK1P_232
-# set_property PACKAGE_PIN N8 [get_ports "SI5328_CLOCK2_C_N"] ;# Bank 232 - MGTREFCLK1N_232
-# set_property PACKAGE_PIN J5 [get_ports "QSFP2_TX3_P"] ;# Bank 232 - MGTYTXP2_232
-# set_property PACKAGE_PIN P2 [get_ports "QSFP2_RX3_P"] ;# Bank 232 - MGTYRXP2_232
-# set_property PACKAGE_PIN P1 [get_ports "QSFP2_RX3_N"] ;# Bank 232 - MGTYRXN2_232
-# set_property PACKAGE_PIN J4 [get_ports "QSFP2_TX3_N"] ;# Bank 232 - MGTYTXN2_232
-# set_property PACKAGE_PIN K7 [get_ports "QSFP2_TX2_P"] ;# Bank 232 - MGTYTXP1_232
-# set_property PACKAGE_PIN R4 [get_ports "QSFP2_RX2_P"] ;# Bank 232 - MGTYRXP1_232
-# set_property PACKAGE_PIN R3 [get_ports "QSFP2_RX2_N"] ;# Bank 232 - MGTYRXN1_232
-# set_property PACKAGE_PIN K6 [get_ports "QSFP2_TX2_N"] ;# Bank 232 - MGTYTXN1_232
-# set_property PACKAGE_PIN R9 [get_ports "MGT_SI570_CLOCK2_C_P"] ;# Bank 232 - MGTREFCLK0P_232
-# set_property PACKAGE_PIN R8 [get_ports "MGT_SI570_CLOCK2_C_N"] ;# Bank 232 - MGTREFCLK0N_232
-# set_property PACKAGE_PIN L5 [get_ports "QSFP2_TX1_P"] ;# Bank 232 - MGTYTXP0_232
-# set_property PACKAGE_PIN T2 [get_ports "QSFP2_RX1_P"] ;# Bank 232 - MGTYRXP0_232
-# set_property PACKAGE_PIN T1 [get_ports "QSFP2_RX1_N"] ;# Bank 232 - MGTYRXN0_232
-# set_property PACKAGE_PIN L4 [get_ports "QSFP2_TX1_N"] ;# Bank 232 - MGTYTXN0_232
-# set_property PACKAGE_PIN C5 [get_ports "FIREFLY_TX4_P"] ;# Bank 233 - MGTYTXP3_233
-# set_property PACKAGE_PIN D2 [get_ports "FIREFLY_RX4_P"] ;# Bank 233 - MGTYRXP3_233
-# set_property PACKAGE_PIN D1 [get_ports "FIREFLY_RX4_N"] ;# Bank 233 - MGTYRXN3_233
-# set_property PACKAGE_PIN C4 [get_ports "FIREFLY_TX4_N"] ;# Bank 233 - MGTYTXN3_233
-# set_property PACKAGE_PIN J9 [get_ports "MGT233_CLK1_P"] ;# Bank 233 - MGTREFCLK1P_233
-# set_property PACKAGE_PIN J8 [get_ports "MGT233_CLK1_N"] ;# Bank 233 - MGTREFCLK1N_233
-# set_property PACKAGE_PIN E5 [get_ports "FIREFLY_TX3_P"] ;# Bank 233 - MGTYTXP2_233
-# set_property PACKAGE_PIN F2 [get_ports "FIREFLY_RX3_P"] ;# Bank 233 - MGTYRXP2_233
-# set_property PACKAGE_PIN F1 [get_ports "FIREFLY_RX3_N"] ;# Bank 233 - MGTYRXN2_233
-# set_property PACKAGE_PIN E4 [get_ports "FIREFLY_TX3_N"] ;# Bank 233 - MGTYTXN2_233
-# set_property PACKAGE_PIN F7 [get_ports "FIREFLY_TX2_P"] ;# Bank 233 - MGTYTXP1_233
-# set_property PACKAGE_PIN H2 [get_ports "FIREFLY_RX2_P"] ;# Bank 233 - MGTYRXP1_233
-# set_property PACKAGE_PIN H1 [get_ports "FIREFLY_RX2_N"] ;# Bank 233 - MGTYRXN1_233
-# set_property PACKAGE_PIN F6 [get_ports "FIREFLY_TX2_N"] ;# Bank 233 - MGTYTXN1_233
-# set_property PACKAGE_PIN L9 [get_ports "MGT_SI570_CLOCK3_C_P"] ;# Bank 233 - MGTREFCLK0P_233
-# set_property PACKAGE_PIN L8 [get_ports "MGT_SI570_CLOCK3_C_N"] ;# Bank 233 - MGTREFCLK0N_233
-# set_property PACKAGE_PIN G5 [get_ports "FIREFLY_TX1_P"] ;# Bank 233 - MGTYTXP0_233
-# set_property PACKAGE_PIN K2 [get_ports "FIREFLY_RX1_P"] ;# Bank 233 - MGTYRXP0_233
-# set_property PACKAGE_PIN K1 [get_ports "FIREFLY_RX1_N"] ;# Bank 233 - MGTYRXN0_233
-# set_property PACKAGE_PIN G4 [get_ports "FIREFLY_TX1_N"] ;# Bank 233 - MGTYTXN0_233
diff --git a/fpga/scripts/program.tcl b/fpga/scripts/program.tcl
deleted file mode 100644
index 0dbb1b67..00000000
--- a/fpga/scripts/program.tcl
+++ /dev/null
@@ -1,38 +0,0 @@
-# Copyright 2018 ETH Zurich and University of Bologna.
-#
-# Licensed under the Apache License, Version 2.0 (the "License");
-# you may not use this file except in compliance with the License.
-# You may obtain a copy of the License at
-#
-# http://www.apache.org/licenses/LICENSE-2.0
-#
-# Unless required by applicable law or agreed to in writing, software
-# distributed under the License is distributed on an "AS IS" BASIS,
-# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-# See the License for the specific language governing permissions and
-# limitations under the License.
-
-# Author: Florian Zaruba <zarubaf@iis.ee.ethz.ch>
-# Description: Program Genesys II
-
-open_hw
-
-connect_hw_server -url localhost:3121
-
-if {$::env(BOARD) eq "genesys2"} {
- open_hw_target {localhost:3121/xilinx_tcf/Digilent/200300A8CD43B}
-
- current_hw_device [get_hw_devices xc7k325t_0]
- set_property PROGRAM.FILE {work-fpga/ariane_xilinx.bit} [get_hw_devices xc7k325t_0]
- program_hw_devices [get_hw_devices xc7k325t_0]
- refresh_hw_device [lindex [get_hw_devices xc7k325t_0] 0]
-} elseif {$::env(BOARD) eq "vc707"} {
- open_hw_target {localhost:3121/xilinx_tcf/Digilent/210203A5FC70A}
-
- current_hw_device [get_hw_devices xc7vx485t_0]
- set_property PROGRAM.FILE {work-fpga/ariane_xilinx.bit} [get_hw_devices xc7vx485t_0]
- program_hw_devices [get_hw_devices xc7vx485t_0]
- refresh_hw_device [lindex [get_hw_devices xc7vx485t_0] 0]
-} else {
- exit 1
-}
diff --git a/fpga/scripts/prologue.tcl b/fpga/scripts/prologue.tcl
deleted file mode 100644
index a78e2ec9..00000000
--- a/fpga/scripts/prologue.tcl
+++ /dev/null
@@ -1,27 +0,0 @@
-# Copyright 2018 ETH Zurich and University of Bologna.
-#
-# Licensed under the Apache License, Version 2.0 (the "License");
-# you may not use this file except in compliance with the License.
-# You may obtain a copy of the License at
-#
-# http://www.apache.org/licenses/LICENSE-2.0
-#
-# Unless required by applicable law or agreed to in writing, software
-# distributed under the License is distributed on an "AS IS" BASIS,
-# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-# See the License for the specific language governing permissions and
-# limitations under the License.
-
-# Author: Florian Zaruba <zarubaf@iis.ee.ethz.ch>
-
-set project ariane
-
-create_project $project . -force -part $::env(XILINX_PART)
-set_property board_part $::env(XILINX_BOARD) [current_project]
-
-# set number of threads to 8 (maximum, unfortunately)
-set_param general.maxThreads 8
-
-set_msg_config -id {[Synth 8-5858]} -new_severity "info"
-
-set_msg_config -id {[Synth 8-4480]} -limit 1000
\ No newline at end of file
diff --git a/fpga/scripts/run.tcl b/fpga/scripts/run.tcl
deleted file mode 100644
index de25c7a1..00000000
--- a/fpga/scripts/run.tcl
+++ /dev/null
@@ -1,105 +0,0 @@
-# Copyright 2018 ETH Zurich and University of Bologna.
-#
-# Licensed under the Apache License, Version 2.0 (the "License");
-# you may not use this file except in compliance with the License.
-# You may obtain a copy of the License at
-#
-# http://www.apache.org/licenses/LICENSE-2.0
-#
-# Unless required by applicable law or agreed to in writing, software
-# distributed under the License is distributed on an "AS IS" BASIS,
-# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-# See the License for the specific language governing permissions and
-# limitations under the License.
-
-# Author: Florian Zaruba <zarubaf@iis.ee.ethz.ch>
-
-# hard-coded to Genesys 2 for the moment
-
-if {$::env(BOARD) eq "genesys2"} {
- add_files -fileset constrs_1 -norecurse constraints/genesys-2.xdc
-} elseif {$::env(BOARD) eq "kc705"} {
- add_files -fileset constrs_1 -norecurse constraints/kc705.xdc
-} elseif {$::env(BOARD) eq "vc707"} {
- add_files -fileset constrs_1 -norecurse constraints/vc707.xdc
-} else {
- exit 1
-}
-
-read_ip xilinx/xlnx_mig_7_ddr3/ip/xlnx_mig_7_ddr3.xci
-read_ip xilinx/xlnx_axi_clock_converter/ip/xlnx_axi_clock_converter.xci
-read_ip xilinx/xlnx_axi_dwidth_converter/ip/xlnx_axi_dwidth_converter.xci
-read_ip xilinx/xlnx_axi_gpio/ip/xlnx_axi_gpio.xci
-read_ip xilinx/xlnx_axi_quad_spi/ip/xlnx_axi_quad_spi.xci
-read_ip xilinx/xlnx_clk_gen/ip/xlnx_clk_gen.xci
-# read_ip xilinx/xlnx_protocol_checker/ip/xlnx_protocol_checker.xci
-
-set_property include_dirs { "src/axi_sd_bridge/include" "../src/common_cells/include" } [current_fileset]
-
-source scripts/add_sources.tcl
-
-set_property top ${project}_xilinx [current_fileset]
-
-if {$::env(BOARD) eq "genesys2"} {
- read_verilog -sv {src/genesysii.svh ../src/common_cells/include/common_cells/registers.svh}
- set file "src/genesysii.svh"
- set registers "../src/common_cells/include/common_cells/registers.svh"
-} elseif {$::env(BOARD) eq "kc705"} {
- read_verilog -sv {src/kc705.svh ../src/common_cells/include/common_cells/registers.svh}
- set file "src/kc705.svh"
- set registers "../src/common_cells/include/common_cells/registers.svh"
-} elseif {$::env(BOARD) eq "vc707"} {
- read_verilog -sv {src/vc707.svh ../src/common_cells/include/common_cells/registers.svh}
- set file "src/vc707.svh"
- set registers "../src/common_cells/include/common_cells/registers.svh"
-} else {
- exit 1
-}
-
-set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file" "$registers"]]
-set_property -dict { file_type {Verilog Header} is_global_include 1} -objects $file_obj
-
-update_compile_order -fileset sources_1
-
-add_files -fileset constrs_1 -norecurse constraints/$project.xdc
-
-synth_design -rtl -name rtl_1
-
-set_property STEPS.SYNTH_DESIGN.ARGS.RETIMING true [get_runs synth_1]
-
-launch_runs synth_1
-wait_on_run synth_1
-open_run synth_1
-
-exec mkdir -p reports/
-exec rm -rf reports/*
-
-check_timing -verbose -file reports/$project.check_timing.rpt
-report_timing -max_paths 100 -nworst 100 -delay_type max -sort_by slack -file reports/$project.timing_WORST_100.rpt
-report_timing -nworst 1 -delay_type max -sort_by group -file reports/$project.timing.rpt
-report_utilization -hierarchical -file reports/$project.utilization.rpt
-report_cdc -file reports/$project.cdc.rpt
-report_clock_interaction -file reports/$project.clock_interaction.rpt
-
-# set for RuntimeOptimized implementation
-set_property "steps.place_design.args.directive" "RuntimeOptimized" [get_runs impl_1]
-set_property "steps.route_design.args.directive" "RuntimeOptimized" [get_runs impl_1]
-
-launch_runs impl_1
-wait_on_run impl_1
-launch_runs impl_1 -to_step write_bitstream
-wait_on_run impl_1
-open_run impl_1
-
-# output Verilog netlist + SDC for timing simulation
-write_verilog -force -mode funcsim work-fpga/${project}_funcsim.v
-write_verilog -force -mode timesim work-fpga/${project}_timesim.v
-write_sdf -force work-fpga/${project}_timesim.sdf
-
-# reports
-exec mkdir -p reports/
-exec rm -rf reports/*
-check_timing -file reports/${project}.check_timing.rpt
-report_timing -max_paths 100 -nworst 100 -delay_type max -sort_by slack -file reports/${project}.timing_WORST_100.rpt
-report_timing -nworst 1 -delay_type max -sort_by group -file reports/${project}.timing.rpt
-report_utilization -hierarchical -file reports/${project}.utilization.rpt
diff --git a/fpga/scripts/run_cva6_ooc.tcl b/fpga/scripts/run_cva6_ooc.tcl
new file mode 100644
index 00000000..3cc83757
--- /dev/null
+++ b/fpga/scripts/run_cva6_ooc.tcl
@@ -0,0 +1,96 @@
+# Copyright (c) 2020 Thales.
+#
+# Copyright and related rights are licensed under the Solderpad
+# License, Version 2.0 (the "License"); you may not use this file except in
+# compliance with the License. You may obtain a copy of the License at
+# http://solderpad.org/licenses/SHL-2.0/ Unless required by applicable law
+# or agreed to in writing, software, hardware and materials distributed under
+# this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR
+# CONDITIONS OF ANY KIND, either express or implied. See the License for the
+# specific language governing permissions and limitations under the License.
+#
+# Author: Sebastien Jacq - sjthales on github.com
+
+#
+# Additional contributions by:
+#
+#
+# script Name: run_cva6_ooc
+# Project Name: CVA6 softcore
+# Language: tcl
+#
+# Description: Script to synthesize/place and route CVA6 architecture
+# in out of context mode
+#
+# =========================================================================== #
+# Revisions :
+# Date Version Author Description
+# 2020-10-06 0.1 S.Jacq Created
+# =========================================================================== #
+set project cva6_ooc
+
+create_project $project . -force -part $::env(XILINX_PART)
+set_property board_part $::env(XILINX_BOARD) [current_project]
+
+
+
+# set number of threads to 8 (maximum, unfortunately)
+set_param general.maxThreads 8
+
+set_msg_config -id {[Synth 8-5858]} -new_severity "info"
+
+set_msg_config -id {[Synth 8-4480]} -limit 1000
+
+set_property include_dirs { "src/axi_sd_bridge/include" "../src/common_cells/include" } [current_fileset]
+
+source scripts/add_sources.tcl
+
+set_property top ariane [current_fileset]
+
+read_verilog -sv {src/zybo-z7-20.svh ../src/common_cells/include/common_cells/registers.svh}
+set file "src/zybo-z7-20.svh"
+set registers "../src/common_cells/include/common_cells/registers.svh"
+
+set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file" "$registers"]]
+set_property -dict { file_type {Verilog Header} is_global_include 1} -objects $file_obj
+
+update_compile_order -fileset sources_1
+
+
+set_property -name {STEPS.SYNTH_DESIGN.ARGS.MORE OPTIONS} -value {-mode out_of_context} -objects [get_runs synth_1]
+set_property STEPS.SYNTH_DESIGN.ARGS.RETIMING true [get_runs synth_1]
+
+launch_runs synth_1
+wait_on_run synth_1
+open_run synth_1
+
+exec mkdir -p reports_cva6_ooc_synth/
+exec rm -rf reports_cva6_ooc_synth/*
+
+
+check_timing -verbose -file reports_cva6_ooc_synth/$project.check_timing.rpt
+report_timing -max_paths 100 -nworst 100 -delay_type max -sort_by slack -file reports_cva6_ooc_synth/$project.timing_WORST_100.rpt
+report_timing -nworst 1 -delay_type max -sort_by group -file reports_cva6_ooc_synth/$project.timing.rpt
+report_utilization -hierarchical -file reports_cva6_ooc_synth/$project.utilization.rpt
+report_cdc -file reports_cva6_ooc_synth/$project.cdc.rpt
+report_clock_interaction -file reports_cva6_ooc_synth/$project.clock_interaction.rpt
+
+# set for RuntimeOptimized implementation
+set_property "steps.place_design.args.directive" "RuntimeOptimized" [get_runs impl_1]
+set_property "steps.route_design.args.directive" "RuntimeOptimized" [get_runs impl_1]
+
+create_clock -period $::env(CLK_PERIOD_NS) -name clk_i [get_ports clk_i]
+
+#set_property HD.CLK_SRC BUFGCTRL_X1Y2 [get_ports clk_i]
+
+
+launch_runs impl_1
+wait_on_run impl_1
+
+# reports
+exec mkdir -p reports_cva6_ooc_impl/
+exec rm -rf reports_cva6_ooc_impl/*
+check_timing -file reports_cva6_ooc_impl/${project}.check_timing.rpt
+report_timing -max_paths 100 -nworst 100 -delay_type max -sort_by slack -file reports_cva6_ooc_impl/${project}.timing_WORST_100.rpt
+report_timing -nworst 1 -delay_type max -sort_by group -file reports_cva6_ooc_impl/${project}.timing.rpt
+report_utilization -hierarchical -file reports_cva6_ooc_impl/${project}.utilization.rpt
diff --git a/fpga/scripts/write_cfgmem.tcl b/fpga/scripts/write_cfgmem.tcl
deleted file mode 100644
index 30f3e962..00000000
--- a/fpga/scripts/write_cfgmem.tcl
+++ /dev/null
@@ -1,35 +0,0 @@
-# Copyright 2018 ETH Zurich and University of Bologna.
-#
-# Licensed under the Apache License, Version 2.0 (the "License");
-# you may not use this file except in compliance with the License.
-# You may obtain a copy of the License at
-#
-# http://www.apache.org/licenses/LICENSE-2.0
-#
-# Unless required by applicable law or agreed to in writing, software
-# distributed under the License is distributed on an "AS IS" BASIS,
-# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-# See the License for the specific language governing permissions and
-# limitations under the License.
-
-# Author: Florian Zaruba <zarubaf@iis.ee.ethz.ch>
-# Description: Generate a memory configuration file from a bitstream (Genesys II only right now)
-
-if {$argc < 2 || $argc > 4} {
- puts $argc
- puts {Error: Invalid number of arguments}
- puts {Usage: write_cfgmem.tcl mcsfile bitfile [datafile]}
- exit 1
-}
-
-lassign $argv mcsfile bitfile
-
-# https://scholar.princeton.edu/jbalkind/blog/programming-genesys-2-qspi-spi-x4-flash
-# https://scholar.princeton.edu/jbalkind/blog/programming-vc707-virtex-7-bpi-flash
-if {$::env(BOARD) eq "genesys2"} {
- write_cfgmem -format mcs -interface SPIx4 -size 256 -loadbit "up 0x0 $bitfile" -file $mcsfile -force
-} elseif {$::env(BOARD) eq "vc707"} {
- write_cfgmem -format mcs -interface bpix16 -size 128 -loadbit "up 0x0 $bitfile" -file $mcsfile -force
-} else {
- exit 1
-}
diff --git a/fpga/sourceme.sh b/fpga/sourceme.sh
deleted file mode 100644
index f3267beb..00000000
--- a/fpga/sourceme.sh
+++ /dev/null
@@ -1,30 +0,0 @@
-#!/bin/bash
-
-# genesys2
-if [ -z "${BOARD}" ]; then
- export BOARD="genesys2"
-fi
-
-if [ "$BOARD" = "genesys2" ]; then
- echo -n "Configuring for "
- echo "Genesys II"
- export XILINX_PART="xc7k325tffg900-2"
- export XILINX_BOARD="digilentinc.com:genesys2:part0:1.1"
- export CLK_PERIOD_NS="20"
-fi
-
-if [ "$BOARD" = "kc705" ]; then
- echo -n "Configuring for "
- echo "Kintex kc705"
- export XILINX_PART="xc7k325tffg900-2"
- export XILINX_BOARD="xilinx.com:kc705:part0:1.5"
- export CLK_PERIOD_NS="20"
-fi
-
-if [ "$BOARD" = "vc707" ]; then
- echo -n "Configuring for "
- echo "Virtex vc707"
- export XILINX_PART="xc7vx485tffg1761-2"
- export XILINX_BOARD="xilinx.com:vc707:part0:1.3"
- export CLK_PERIOD_NS="20"
-fi
diff --git a/fpga/src/zybo-z7-20.svh b/fpga/src/zybo-z7-20.svh
new file mode 100644
index 00000000..ab300420
--- /dev/null
+++ b/fpga/src/zybo-z7-20.svh
@@ -0,0 +1,11 @@
+
+`define ARIANE_DATA_WIDTH 64
+
+// Instantiate protocl checker
+// `define PROTOCOL_CHECKER
+
+// write-back cache
+// `define WB_DCACHE
+
+// write-through cache
+`define WT_DCACHE
diff --git a/fpga/xilinx/.gitignore b/fpga/xilinx/.gitignore
deleted file mode 100644
index 12ef7f9f..00000000
--- a/fpga/xilinx/.gitignore
+++ /dev/null
@@ -1,5 +0,0 @@
-xlnx*/*
-!xlnx*/tcl
-!Makefile
-!common.mk
-!*.prj
\ No newline at end of file
diff --git a/fpga/xilinx/ariane_xlnx_ip.yml b/fpga/xilinx/ariane_xlnx_ip.yml
deleted file mode 100644
index 2b3c0c1e..00000000
--- a/fpga/xilinx/ariane_xlnx_ip.yml
+++ /dev/null
@@ -1,92 +0,0 @@
-xlnx_axi_dwidth_converter:
- ip: axi_dwidth_converter
- vendor: xilinx.com
- config:
- si_data_width: 64
- si_id_width: 5
- mi_data_width: 32
-
-xlnx_axi_clock_converter:
- ip: axi_clock_converter
- vendor: xilinx.com
- config:
- width: 64
- data_width: 64
- id_width: 5
-
-xlnx_axi_gpio:
- ip: axi_gpio
- vendor: xilinx.com
- config:
- c_gpio_width: 8
- c_gpio2_width: 8
- c_is_dual: 1
- c_all_inputs_2: 1
- c_interrupt_present: 0
-
-xlnx_axi_quad_spi:
- ip: axi_quad_spi
- vendor: xilinx.com
- config:
- c_use_startup: 0
- c_sck_ratio: 4
- c_fifo_depth: 256
- c_type_of_axi4_interface: 1
- c_s_axi4_id_width: 0
-
-xlnx_clk_gen:
- ip: clk_wiz
- vendor: xilinx.com
- config:
- prim_in_freq: 200
- num_out_clks: 4
- clkout2_used: true
- clkout3_used: true
- clkout4_used: true
- clkout1_requested_out_freq: 50
- clkout2_requested_out_freq: 125
- clkout3_requested_out_freq: 125
- clkout3_requested_phase: 90
- clkout4_requested_out_freq: 50
- clkin1_jitter_ps: 50
-
-xlnx_ila:
- ip: ila
- vendor: xilinx.com
- config:
- c_num_of_probes: 8
- c_probe3_width: 4
- c_probe6_width: 4
- c_data_depth: 16384
- c_input_pipe_stages: 1
-
-xlnx_mig_7_ddr3:
- ip: mig_7series
- vendor: xilinx.com
- config:
- xml_input_file: mig_a.prj
- reset_board_interface: Custom
- mig_dont_touch_param: Custom
- board_mig_param: Custom
-
-xlnx_ila:
- ip: xlnx_ila
- vendor: xilinx.com
- config:
- addr_width: 64
- data_width: 64
- id_width: 5
- awuser_width: 1
- aruser_width: 1
- ruser_width: 1
- wuser_width: 1
- buser_width: 1
- max_aw_waits: 1024
- max_ar_waits: 1024
- max_w_waits: 1024
- max_r_waits: 1024
- max_b_waits: 1024
- max_continuous_wtransfers_waits: 1024
- max_wlast_to_awvalid_waits: 1024
- max_write_to_bvalid_waits: 1024
- max_continuous_rtransfers_waits: 1024
\ No newline at end of file
diff --git a/fpga/xilinx/common.mk b/fpga/xilinx/common.mk
deleted file mode 100644
index 60c91008..00000000
--- a/fpga/xilinx/common.mk
+++ /dev/null
@@ -1,19 +0,0 @@
-all:
- vivado -mode batch -source tcl/run.tcl
- mkdir -p ip
- cp -r ${PROJECT}.srcs/sources_1/ip/${PROJECT}/* ip/.
- cp ${PROJECT}.runs/${PROJECT}_synth_1/${PROJECT}.dcp ip/.
-
-gui:
- vivado -mode gui -source tcl/run.tcl &
-
-clean:
- rm -rf ip/*
- mkdir -p ip
- rm -rf ${PROJECT}.*
- rm -rf component.xml
- rm -rf vivado*.jou
- rm -rf vivado*.log
- rm -rf vivado*.str
- rm -rf xgui
- rm -rf .Xil
\ No newline at end of file
diff --git a/fpga/xilinx/xlnx_axi_clock_converter/Makefile b/fpga/xilinx/xlnx_axi_clock_converter/Makefile
deleted file mode 100644
index 426a7d73..00000000
--- a/fpga/xilinx/xlnx_axi_clock_converter/Makefile
+++ /dev/null
@@ -1,2 +0,0 @@
-PROJECT:=xlnx_axi_clock_converter
-include ../common.mk
\ No newline at end of file
diff --git a/fpga/xilinx/xlnx_axi_clock_converter/tcl/run.tcl b/fpga/xilinx/xlnx_axi_clock_converter/tcl/run.tcl
deleted file mode 100644
index ba0551e7..00000000
--- a/fpga/xilinx/xlnx_axi_clock_converter/tcl/run.tcl
+++ /dev/null
@@ -1,17 +0,0 @@
-set partNumber $::env(XILINX_PART)
-set boardName $::env(XILINX_BOARD)
-
-set ipName xlnx_axi_clock_converter
-
-create_project $ipName . -force -part $partNumber
-set_property board_part $boardName [current_project]
-
-create_ip -name axi_clock_converter -vendor xilinx.com -library ip -module_name $ipName
-
-set_property -dict [list CONFIG.ADDR_WIDTH {64} CONFIG.DATA_WIDTH {64} CONFIG.ID_WIDTH {5}] [get_ips $ipName]
-
-generate_target {instantiation_template} [get_files ./$ipName.srcs/sources_1/ip/$ipName/$ipName.xci]
-generate_target all [get_files ./$ipName.srcs/sources_1/ip/$ipName/$ipName.xci]
-create_ip_run [get_files -of_objects [get_fileset sources_1] ./$ipName.srcs/sources_1/ip/$ipName/$ipName.xci]
-launch_run -jobs 8 ${ipName}_synth_1
-wait_on_run ${ipName}_synth_1
\ No newline at end of file
diff --git a/fpga/xilinx/xlnx_axi_dwidth_converter/Makefile b/fpga/xilinx/xlnx_axi_dwidth_converter/Makefile
deleted file mode 100644
index d109f974..00000000
--- a/fpga/xilinx/xlnx_axi_dwidth_converter/Makefile
+++ /dev/null
@@ -1,2 +0,0 @@
-PROJECT:=xlnx_axi_dwidth_converter
-include ../common.mk
\ No newline at end of file
diff --git a/fpga/xilinx/xlnx_axi_dwidth_converter/tcl/run.tcl b/fpga/xilinx/xlnx_axi_dwidth_converter/tcl/run.tcl
deleted file mode 100644
index dab9f462..00000000
--- a/fpga/xilinx/xlnx_axi_dwidth_converter/tcl/run.tcl
+++ /dev/null
@@ -1,17 +0,0 @@
-set partNumber $::env(XILINX_PART)
-set boardName $::env(XILINX_BOARD)
-
-set ipName xlnx_axi_dwidth_converter
-
-create_project $ipName . -force -part $partNumber
-set_property board_part $boardName [current_project]
-
-create_ip -name axi_dwidth_converter -vendor xilinx.com -library ip -module_name $ipName
-
-set_property -dict [list CONFIG.SI_DATA_WIDTH {64} CONFIG.SI_ID_WIDTH {5} CONFIG.MI_DATA_WIDTH {32}] [get_ips $ipName]
-
-generate_target {instantiation_template} [get_files ./$ipName.srcs/sources_1/ip/$ipName/$ipName.xci]
-generate_target all [get_files ./$ipName.srcs/sources_1/ip/$ipName/$ipName.xci]
-create_ip_run [get_files -of_objects [get_fileset sources_1] ./$ipName.srcs/sources_1/ip/$ipName/$ipName.xci]
-launch_run -jobs 8 ${ipName}_synth_1
-wait_on_run ${ipName}_synth_1
\ No newline at end of file
diff --git a/fpga/xilinx/xlnx_axi_gpio/Makefile b/fpga/xilinx/xlnx_axi_gpio/Makefile
deleted file mode 100644
index 46dd3417..00000000
--- a/fpga/xilinx/xlnx_axi_gpio/Makefile
+++ /dev/null
@@ -1,2 +0,0 @@
-PROJECT:=xlnx_axi_gpio
-include ../common.mk
\ No newline at end of file
diff --git a/fpga/xilinx/xlnx_axi_gpio/tcl/run.tcl b/fpga/xilinx/xlnx_axi_gpio/tcl/run.tcl
deleted file mode 100644
index 6f8bad9f..00000000
--- a/fpga/xilinx/xlnx_axi_gpio/tcl/run.tcl
+++ /dev/null
@@ -1,16 +0,0 @@
-set partNumber $::env(XILINX_PART)
-set boardName $::env(XILINX_BOARD)
-
-set ipName xlnx_axi_gpio
-
-create_project $ipName . -force -part $partNumber
-set_property board_part $boardName [current_project]
-
-create_ip -name axi_gpio -vendor xilinx.com -library ip -module_name $ipName
-set_property -dict [list CONFIG.C_GPIO_WIDTH {8} CONFIG.C_GPIO2_WIDTH {8} CONFIG.C_IS_DUAL {1} CONFIG.C_ALL_INPUTS_2 {1} CONFIG.C_INTERRUPT_PRESENT {0}] [get_ips $ipName]
-
-generate_target {instantiation_template} [get_files ./$ipName.srcs/sources_1/ip/$ipName/$ipName.xci]
-generate_target all [get_files ./$ipName.srcs/sources_1/ip/$ipName/$ipName.xci]
-create_ip_run [get_files -of_objects [get_fileset sources_1] ./$ipName.srcs/sources_1/ip/$ipName/$ipName.xci]
-launch_run -jobs 8 ${ipName}_synth_1
-wait_on_run ${ipName}_synth_1
\ No newline at end of file
diff --git a/fpga/xilinx/xlnx_axi_quad_spi/Makefile b/fpga/xilinx/xlnx_axi_quad_spi/Makefile
deleted file mode 100644
index d61633d1..00000000
--- a/fpga/xilinx/xlnx_axi_quad_spi/Makefile
+++ /dev/null
@@ -1,2 +0,0 @@
-PROJECT:=xlnx_axi_quad_spi
-include ../common.mk
\ No newline at end of file
diff --git a/fpga/xilinx/xlnx_axi_quad_spi/tcl/run.tcl b/fpga/xilinx/xlnx_axi_quad_spi/tcl/run.tcl
deleted file mode 100644
index df8e09ad..00000000
--- a/fpga/xilinx/xlnx_axi_quad_spi/tcl/run.tcl
+++ /dev/null
@@ -1,16 +0,0 @@
-set partNumber $::env(XILINX_PART)
-set boardName $::env(XILINX_BOARD)
-
-set ipName xlnx_axi_quad_spi
-
-create_project $ipName . -part $partNumber
-set_property board_part $boardName [current_project]
-
-create_ip -name axi_quad_spi -vendor xilinx.com -library ip -module_name $ipName
-set_property -dict [list CONFIG.C_USE_STARTUP {0} CONFIG.C_SCK_RATIO {4} CONFIG.C_FIFO_DEPTH {256} CONFIG.C_TYPE_OF_AXI4_INTERFACE {1} CONFIG.C_S_AXI4_ID_WIDTH {0}] [get_ips $ipName]
-
-generate_target {instantiation_template} [get_files ./$ipName.srcs/sources_1/ip/$ipName/$ipName.xci]
-generate_target all [get_files ./$ipName.srcs/sources_1/ip/$ipName/$ipName.xci]
-create_ip_run [get_files -of_objects [get_fileset sources_1] ./$ipName.srcs/sources_1/ip/$ipName/$ipName.xci]
-launch_run -jobs 8 ${ipName}_synth_1
-wait_on_run ${ipName}_synth_1
\ No newline at end of file
diff --git a/fpga/xilinx/xlnx_clk_gen/Makefile b/fpga/xilinx/xlnx_clk_gen/Makefile
deleted file mode 100644
index 8ce5e6e6..00000000
--- a/fpga/xilinx/xlnx_clk_gen/Makefile
+++ /dev/null
@@ -1,2 +0,0 @@
-PROJECT:=xlnx_clk_gen
-include ../common.mk
\ No newline at end of file
diff --git a/fpga/xilinx/xlnx_clk_gen/tcl/run.tcl b/fpga/xilinx/xlnx_clk_gen/tcl/run.tcl
deleted file mode 100644
index e1fba9da..00000000
--- a/fpga/xilinx/xlnx_clk_gen/tcl/run.tcl
+++ /dev/null
@@ -1,28 +0,0 @@
-set partNumber $::env(XILINX_PART)
-set boardName $::env(XILINX_BOARD)
-
-set ipName xlnx_clk_gen
-
-create_project $ipName . -force -part $partNumber
-set_property board_part $boardName [current_project]
-
-create_ip -name clk_wiz -vendor xilinx.com -library ip -module_name $ipName
-
-set_property -dict [list CONFIG.PRIM_IN_FREQ {200.000} \
- CONFIG.NUM_OUT_CLKS {4} \
- CONFIG.CLKOUT2_USED {true} \
- CONFIG.CLKOUT3_USED {true} \
- CONFIG.CLKOUT4_USED {true} \
- CONFIG.CLKOUT1_REQUESTED_OUT_FREQ {50} \
- CONFIG.CLKOUT2_REQUESTED_OUT_FREQ {125} \
- CONFIG.CLKOUT3_REQUESTED_OUT_FREQ {125} \
- CONFIG.CLKOUT3_REQUESTED_PHASE {90.000} \
- CONFIG.CLKOUT4_REQUESTED_OUT_FREQ {50} \
- CONFIG.CLKIN1_JITTER_PS {50.0} \
- ] [get_ips $ipName]
-
-generate_target {instantiation_template} [get_files ./$ipName.srcs/sources_1/ip/$ipName/$ipName.xci]
-generate_target all [get_files ./$ipName.srcs/sources_1/ip/$ipName/$ipName.xci]
-create_ip_run [get_files -of_objects [get_fileset sources_1] ./$ipName.srcs/sources_1/ip/$ipName/$ipName.xci]
-launch_run -jobs 8 ${ipName}_synth_1
-wait_on_run ${ipName}_synth_1
diff --git a/fpga/xilinx/xlnx_ila/Makefile b/fpga/xilinx/xlnx_ila/Makefile
deleted file mode 100644
index 299a7133..00000000
--- a/fpga/xilinx/xlnx_ila/Makefile
+++ /dev/null
@@ -1,2 +0,0 @@
-PROJECT:=xlnx_ila
-include ../common.mk
\ No newline at end of file
diff --git a/fpga/xilinx/xlnx_ila/tcl/run.tcl b/fpga/xilinx/xlnx_ila/tcl/run.tcl
deleted file mode 100644
index 9aff7b11..00000000
--- a/fpga/xilinx/xlnx_ila/tcl/run.tcl
+++ /dev/null
@@ -1,22 +0,0 @@
-set partNumber $::env(XILINX_PART)
-set boardName $::env(XILINX_BOARD)
-
-set ipName xlnx_ila
-
-create_project $ipName . -force -part $partNumber
-set_property board_part $boardName [current_project]
-
-create_ip -name ila -vendor xilinx.com -library ip -module_name $ipName
-set_property -dict [list CONFIG.C_NUM_OF_PROBES {8} \
- CONFIG.C_PROBE3_WIDTH {4} \
- CONFIG.C_PROBE6_WIDTH {4} \
- CONFIG.C_DATA_DEPTH {16384} \
- CONFIG.C_INPUT_PIPE_STAGES {1} \
- ] [get_ips $ipName]
-
-
-generate_target {instantiation_template} [get_files ./$ipName.srcs/sources_1/ip/$ipName/$ipName.xci]
-generate_target all [get_files ./$ipName.srcs/sources_1/ip/$ipName/$ipName.xci]
-create_ip_run [get_files -of_objects [get_fileset sources_1] ./$ipName.srcs/sources_1/ip/$ipName/$ipName.xci]
-launch_run -jobs 8 ${ipName}_synth_1
-wait_on_run ${ipName}_synth_1
\ No newline at end of file
diff --git a/fpga/xilinx/xlnx_mig_7_ddr3/Makefile b/fpga/xilinx/xlnx_mig_7_ddr3/Makefile
deleted file mode 100644
index dd00c21c..00000000
--- a/fpga/xilinx/xlnx_mig_7_ddr3/Makefile
+++ /dev/null
@@ -1,2 +0,0 @@
-PROJECT:=xlnx_mig_7_ddr3
-include ../common.mk
\ No newline at end of file
diff --git a/fpga/xilinx/xlnx_mig_7_ddr3/mig_genesys2.prj b/fpga/xilinx/xlnx_mig_7_ddr3/mig_genesys2.prj
deleted file mode 100755
index cdc818e9..00000000
--- a/fpga/xilinx/xlnx_mig_7_ddr3/mig_genesys2.prj
+++ /dev/null
@@ -1,160 +0,0 @@
-<?xml version='1.0' encoding='UTF-8'?>
-<!-- IMPORTANT: This is an internal file that has been generated by the MIG software. Any direct editing or changes made to this file may result in unpredictable behavior or data corruption. It is strongly advised that users do not edit the contents of this file. Re-run the MIG GUI with the required settings if any of the options provided below need to be altered. -->
-<Project NoOfControllers="1" >
- <ModuleName>xlnx_mig_7_ddr3</ModuleName>
- <dci_inouts_inputs>1</dci_inouts_inputs>
- <dci_inputs>1</dci_inputs>
- <Debug_En>OFF</Debug_En>
- <DataDepth_En>1024</DataDepth_En>
- <LowPower_En>ON</LowPower_En>
- <XADC_En>Enabled</XADC_En>
- <TargetFPGA>xc7k325t-ffg900/-2</TargetFPGA>
- <Version>4.1</Version>
- <SystemClock>Differential</SystemClock>
- <ReferenceClock>Use System Clock</ReferenceClock>
- <SysResetPolarity>ACTIVE LOW</SysResetPolarity>
- <BankSelectionFlag>FALSE</BankSelectionFlag>
- <InternalVref>0</InternalVref>
- <dci_hr_inouts_inputs>50 Ohms</dci_hr_inouts_inputs>
- <dci_cascade>0</dci_cascade>
- <Controller number="0" >
- <MemoryDevice>DDR3_SDRAM/Components/MT41J256m16XX-107</MemoryDevice>
- <TimePeriod>1250</TimePeriod>
- <VccAuxIO>2.0V</VccAuxIO>
- <PHYRatio>4:1</PHYRatio>
- <InputClkFreq>200</InputClkFreq>
- <UIExtraClocks>0</UIExtraClocks>
- <MMCM_VCO>800</MMCM_VCO>
- <MMCMClkOut0> 1.000</MMCMClkOut0>
- <MMCMClkOut1>1</MMCMClkOut1>
- <MMCMClkOut2>1</MMCMClkOut2>
- <MMCMClkOut3>1</MMCMClkOut3>
- <MMCMClkOut4>1</MMCMClkOut4>
- <DataWidth>32</DataWidth>
- <DeepMemory>1</DeepMemory>
- <DataMask>1</DataMask>
- <ECC>Disabled</ECC>
- <Ordering>Normal</Ordering>
- <BankMachineCnt>4</BankMachineCnt>
- <CustomPart>FALSE</CustomPart>
- <NewPartName></NewPartName>
- <RowAddress>15</RowAddress>
- <ColAddress>10</ColAddress>
- <BankAddress>3</BankAddress>
- <MemoryVoltage>1.5V</MemoryVoltage>
- <UserMemoryAddressMap>BANK_ROW_COLUMN</UserMemoryAddressMap>
- <PinSelection>
- <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15" PADName="AC12" SLEW="" name="ddr3_addr[0]" IN_TERM="" />
- <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15" PADName="AB8" SLEW="" name="ddr3_addr[10]" IN_TERM="" />
- <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15" PADName="AA8" SLEW="" name="ddr3_addr[11]" IN_TERM="" />
- <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15" PADName="AB12" SLEW="" name="ddr3_addr[12]" IN_TERM="" />
- <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15" PADName="AA12" SLEW="" name="ddr3_addr[13]" IN_TERM="" />
- <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15" PADName="AH9" SLEW="" name="ddr3_addr[14]" IN_TERM="" />
- <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15" PADName="AE8" SLEW="" name="ddr3_addr[1]" IN_TERM="" />
- <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15" PADName="AD8" SLEW="" name="ddr3_addr[2]" IN_TERM="" />
- <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15" PADName="AC10" SLEW="" name="ddr3_addr[3]" IN_TERM="" />
- <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15" PADName="AD9" SLEW="" name="ddr3_addr[4]" IN_TERM="" />
- <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15" PADName="AA13" SLEW="" name="ddr3_addr[5]" IN_TERM="" />
- <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15" PADName="AA10" SLEW="" name="ddr3_addr[6]" IN_TERM="" />
- <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15" PADName="AA11" SLEW="" name="ddr3_addr[7]" IN_TERM="" />
- <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15" PADName="Y10" SLEW="" name="ddr3_addr[8]" IN_TERM="" />
- <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15" PADName="Y11" SLEW="" name="ddr3_addr[9]" IN_TERM="" />
- <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15" PADName="AE9" SLEW="" name="ddr3_ba[0]" IN_TERM="" />
- <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15" PADName="AB10" SLEW="" name="ddr3_ba[1]" IN_TERM="" />
- <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15" PADName="AC11" SLEW="" name="ddr3_ba[2]" IN_TERM="" />
- <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15" PADName="AF11" SLEW="" name="ddr3_cas_n" IN_TERM="" />
- <Pin VCCAUX_IO="HIGH" IOSTANDARD="DIFF_SSTL15" PADName="AC9" SLEW="" name="ddr3_ck_n[0]" IN_TERM="" />
- <Pin VCCAUX_IO="HIGH" IOSTANDARD="DIFF_SSTL15" PADName="AB9" SLEW="" name="ddr3_ck_p[0]" IN_TERM="" />
- <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15" PADName="AJ9" SLEW="" name="ddr3_cke[0]" IN_TERM="" />
- <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15" PADName="AH12" SLEW="" name="ddr3_cs_n[0]" IN_TERM="" />
- <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15" PADName="AD4" SLEW="" name="ddr3_dm[0]" IN_TERM="" />
- <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15" PADName="AF3" SLEW="" name="ddr3_dm[1]" IN_TERM="" />
- <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15" PADName="AH4" SLEW="" name="ddr3_dm[2]" IN_TERM="" />
- <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15" PADName="AF8" SLEW="" name="ddr3_dm[3]" IN_TERM="" />
- <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="AD3" SLEW="" name="ddr3_dq[0]" IN_TERM="" />
- <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="AF1" SLEW="" name="ddr3_dq[10]" IN_TERM="" />
- <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="AE4" SLEW="" name="ddr3_dq[11]" IN_TERM="" />
- <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="AE3" SLEW="" name="ddr3_dq[12]" IN_TERM="" />
- <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="AE5" SLEW="" name="ddr3_dq[13]" IN_TERM="" />
- <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="AF5" SLEW="" name="ddr3_dq[14]" IN_TERM="" />
- <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="AF6" SLEW="" name="ddr3_dq[15]" IN_TERM="" />
- <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="AJ4" SLEW="" name="ddr3_dq[16]" IN_TERM="" />
- <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="AH6" SLEW="" name="ddr3_dq[17]" IN_TERM="" />
- <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="AH5" SLEW="" name="ddr3_dq[18]" IN_TERM="" />
- <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="AH2" SLEW="" name="ddr3_dq[19]" IN_TERM="" />
- <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="AC2" SLEW="" name="ddr3_dq[1]" IN_TERM="" />
- <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="AJ2" SLEW="" name="ddr3_dq[20]" IN_TERM="" />
- <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="AJ1" SLEW="" name="ddr3_dq[21]" IN_TERM="" />
- <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="AK1" SLEW="" name="ddr3_dq[22]" IN_TERM="" />
- <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="AJ3" SLEW="" name="ddr3_dq[23]" IN_TERM="" />
- <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="AF7" SLEW="" name="ddr3_dq[24]" IN_TERM="" />
- <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="AG7" SLEW="" name="ddr3_dq[25]" IN_TERM="" />
- <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="AJ6" SLEW="" name="ddr3_dq[26]" IN_TERM="" />
- <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="AK6" SLEW="" name="ddr3_dq[27]" IN_TERM="" />
- <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="AJ8" SLEW="" name="ddr3_dq[28]" IN_TERM="" />
- <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="AK8" SLEW="" name="ddr3_dq[29]" IN_TERM="" />
- <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="AC1" SLEW="" name="ddr3_dq[2]" IN_TERM="" />
- <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="AK5" SLEW="" name="ddr3_dq[30]" IN_TERM="" />
- <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="AK4" SLEW="" name="ddr3_dq[31]" IN_TERM="" />
- <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="AC5" SLEW="" name="ddr3_dq[3]" IN_TERM="" />
- <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="AC4" SLEW="" name="ddr3_dq[4]" IN_TERM="" />
- <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="AD6" SLEW="" name="ddr3_dq[5]" IN_TERM="" />
- <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="AE6" SLEW="" name="ddr3_dq[6]" IN_TERM="" />
- <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="AC7" SLEW="" name="ddr3_dq[7]" IN_TERM="" />
- <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="AF2" SLEW="" name="ddr3_dq[8]" IN_TERM="" />
- <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="AE1" SLEW="" name="ddr3_dq[9]" IN_TERM="" />
- <Pin VCCAUX_IO="HIGH" IOSTANDARD="DIFF_SSTL15_T_DCI" PADName="AD1" SLEW="" name="ddr3_dqs_n[0]" IN_TERM="" />
- <Pin VCCAUX_IO="HIGH" IOSTANDARD="DIFF_SSTL15_T_DCI" PADName="AG3" SLEW="" name="ddr3_dqs_n[1]" IN_TERM="" />
- <Pin VCCAUX_IO="HIGH" IOSTANDARD="DIFF_SSTL15_T_DCI" PADName="AH1" SLEW="" name="ddr3_dqs_n[2]" IN_TERM="" />
- <Pin VCCAUX_IO="HIGH" IOSTANDARD="DIFF_SSTL15_T_DCI" PADName="AJ7" SLEW="" name="ddr3_dqs_n[3]" IN_TERM="" />
- <Pin VCCAUX_IO="HIGH" IOSTANDARD="DIFF_SSTL15_T_DCI" PADName="AD2" SLEW="" name="ddr3_dqs_p[0]" IN_TERM="" />
- <Pin VCCAUX_IO="HIGH" IOSTANDARD="DIFF_SSTL15_T_DCI" PADName="AG4" SLEW="" name="ddr3_dqs_p[1]" IN_TERM="" />
- <Pin VCCAUX_IO="HIGH" IOSTANDARD="DIFF_SSTL15_T_DCI" PADName="AG2" SLEW="" name="ddr3_dqs_p[2]" IN_TERM="" />
- <Pin VCCAUX_IO="HIGH" IOSTANDARD="DIFF_SSTL15_T_DCI" PADName="AH7" SLEW="" name="ddr3_dqs_p[3]" IN_TERM="" />
- <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15" PADName="AK9" SLEW="" name="ddr3_odt[0]" IN_TERM="" />
- <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15" PADName="AE11" SLEW="" name="ddr3_ras_n" IN_TERM="" />
- <Pin VCCAUX_IO="HIGH" IOSTANDARD="LVCMOS15" PADName="AG5" SLEW="" name="ddr3_reset_n" IN_TERM="" />
- <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15" PADName="AG13" SLEW="" name="ddr3_we_n" IN_TERM="" />
- </PinSelection>
- <System_Clock>
- <Pin PADName="AD12/AD11(CC_P/N)" Bank="33" name="sys_clk_p/n" />
- </System_Clock>
- <System_Control>
- <Pin PADName="No connect" Bank="Select Bank" name="sys_rst" />
- <Pin PADName="No connect" Bank="Select Bank" name="init_calib_complete" />
- <Pin PADName="No connect" Bank="Select Bank" name="tg_compare_error" />
- </System_Control>
- <TimingParameters>
- <Parameters twtr="7.5" trrd="6" trefi="7.8" tfaw="35" trtp="7.5" tcke="5" trfc="260" trp="13.91" tras="34" trcd="13.91" />
- </TimingParameters>
- <mrBurstLength name="Burst Length" >8 - Fixed</mrBurstLength>
- <mrBurstType name="Read Burst Type and Length" >Sequential</mrBurstType>
- <mrCasLatency name="CAS Latency" >11</mrCasLatency>
- <mrMode name="Mode" >Normal</mrMode>
- <mrDllReset name="DLL Reset" >No</mrDllReset>
- <mrPdMode name="DLL control for precharge PD" >Slow Exit</mrPdMode>
- <emrDllEnable name="DLL Enable" >Enable</emrDllEnable>
- <emrOutputDriveStrength name="Output Driver Impedance Control" >RZQ/7</emrOutputDriveStrength>
- <emrMirrorSelection name="Address Mirroring" >Disable</emrMirrorSelection>
- <emrCSSelection name="Controller Chip Select Pin" >Enable</emrCSSelection>
- <emrRTT name="RTT (nominal) - On Die Termination (ODT)" >RZQ/6</emrRTT>
- <emrPosted name="Additive Latency (AL)" >0</emrPosted>
- <emrOCD name="Write Leveling Enable" >Disabled</emrOCD>
- <emrDQS name="TDQS enable" >Enabled</emrDQS>
- <emrRDQS name="Qoff" >Output Buffer Enabled</emrRDQS>
- <mr2PartialArraySelfRefresh name="Partial-Array Self Refresh" >Full Array</mr2PartialArraySelfRefresh>
- <mr2CasWriteLatency name="CAS write latency" >8</mr2CasWriteLatency>
- <mr2AutoSelfRefresh name="Auto Self Refresh" >Enabled</mr2AutoSelfRefresh>
- <mr2SelfRefreshTempRange name="High Temparature Self Refresh Rate" >Normal</mr2SelfRefreshTempRange>
- <mr2RTTWR name="RTT_WR - Dynamic On Die Termination (ODT)" >Dynamic ODT off</mr2RTTWR>
- <PortInterface>AXI</PortInterface>
- <AXIParameters>
- <C0_C_RD_WR_ARB_ALGORITHM>RD_PRI_REG</C0_C_RD_WR_ARB_ALGORITHM>
- <C0_S_AXI_ADDR_WIDTH>30</C0_S_AXI_ADDR_WIDTH>
- <C0_S_AXI_DATA_WIDTH>64</C0_S_AXI_DATA_WIDTH>
- <C0_S_AXI_ID_WIDTH>5</C0_S_AXI_ID_WIDTH>
- <C0_S_AXI_SUPPORTS_NARROW_BURST>0</C0_S_AXI_SUPPORTS_NARROW_BURST>
- </AXIParameters>
- </Controller>
-
-</Project>
\ No newline at end of file
diff --git a/fpga/xilinx/xlnx_mig_7_ddr3/mig_kc705.prj b/fpga/xilinx/xlnx_mig_7_ddr3/mig_kc705.prj
deleted file mode 100644
index a523f973..00000000
--- a/fpga/xilinx/xlnx_mig_7_ddr3/mig_kc705.prj
+++ /dev/null
@@ -1,200 +0,0 @@
-<?xml version='1.0' encoding='UTF-8'?>
-<!-- IMPORTANT: This is an internal file that has been generated by the MIG software. Any direct editing or changes made to this file may result in unpredictable behavior or data corruption. It is strongly advised that users do not edit the contents of this file. Re-run the MIG GUI with the required settings if any of the options provided below need to be altered. -->
-<Project NoOfControllers="1" >
- <ModuleName>xlnx_mig_7_ddr3</ModuleName>
- <dci_inouts_inputs>1</dci_inouts_inputs>
- <dci_inputs>1</dci_inputs>
- <Debug_En>OFF</Debug_En>
- <DataDepth_En>1024</DataDepth_En>
- <LowPower_En>ON</LowPower_En>
- <XADC_En>Enabled</XADC_En>
- <TargetFPGA>xc7k325t-ffg900/-2</TargetFPGA>
- <Version>4.1</Version>
- <SystemClock>Differential</SystemClock>
- <ReferenceClock>Use System Clock</ReferenceClock>
- <SysResetPolarity>ACTIVE LOW</SysResetPolarity>
- <BankSelectionFlag>FALSE</BankSelectionFlag>
- <InternalVref>0</InternalVref>
- <dci_hr_inouts_inputs>50 Ohms</dci_hr_inouts_inputs>
- <dci_cascade>1</dci_cascade>
- <Controller number="0" >
- <MemoryDevice>DDR3_SDRAM/SODIMMs/MT8JTF12864HZ-1G6</MemoryDevice>
- <TimePeriod>1250</TimePeriod>
- <VccAuxIO>2.0V</VccAuxIO>
- <PHYRatio>4:1</PHYRatio>
- <InputClkFreq>200</InputClkFreq>
- <UIExtraClocks>0</UIExtraClocks>
- <MMCM_VCO>800</MMCM_VCO>
- <MMCMClkOut0>16</MMCMClkOut0>
- <MMCMClkOut1>1</MMCMClkOut1>
- <MMCMClkOut2>1</MMCMClkOut2>
- <MMCMClkOut3>1</MMCMClkOut3>
- <MMCMClkOut4>1</MMCMClkOut4>
- <DataWidth>64</DataWidth>
- <DeepMemory>1</DeepMemory>
- <DataMask>1</DataMask>
- <ECC>Disabled</ECC>
- <Ordering>Normal</Ordering>
- <BankMachineCnt>4</BankMachineCnt>
- <CustomPart>FALSE</CustomPart>
- <NewPartName></NewPartName>
- <RowAddress>14</RowAddress>
- <ColAddress>10</ColAddress>
- <BankAddress>3</BankAddress>
- <MemoryVoltage>1.5V</MemoryVoltage>
- <UserMemoryAddressMap>BANK_ROW_COLUMN</UserMemoryAddressMap>
- <PinSelection>
- <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15" PADName="AH12" SLEW="" name="ddr3_addr[0]" IN_TERM="" />
- <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15" PADName="AF13" SLEW="" name="ddr3_addr[10]" IN_TERM="" />
- <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15" PADName="AE13" SLEW="" name="ddr3_addr[11]" IN_TERM="" />
- <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15" PADName="AJ11" SLEW="" name="ddr3_addr[12]" IN_TERM="" />
- <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15" PADName="AH11" SLEW="" name="ddr3_addr[13]" IN_TERM="" />
- <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15" PADName="AG13" SLEW="" name="ddr3_addr[1]" IN_TERM="" />
- <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15" PADName="AG12" SLEW="" name="ddr3_addr[2]" IN_TERM="" />
- <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15" PADName="AF12" SLEW="" name="ddr3_addr[3]" IN_TERM="" />
- <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15" PADName="AJ12" SLEW="" name="ddr3_addr[4]" IN_TERM="" />
- <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15" PADName="AJ13" SLEW="" name="ddr3_addr[5]" IN_TERM="" />
- <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15" PADName="AJ14" SLEW="" name="ddr3_addr[6]" IN_TERM="" />
- <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15" PADName="AH14" SLEW="" name="ddr3_addr[7]" IN_TERM="" />
- <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15" PADName="AK13" SLEW="" name="ddr3_addr[8]" IN_TERM="" />
- <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15" PADName="AK14" SLEW="" name="ddr3_addr[9]" IN_TERM="" />
- <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15" PADName="AH9" SLEW="" name="ddr3_ba[0]" IN_TERM="" />
- <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15" PADName="AG9" SLEW="" name="ddr3_ba[1]" IN_TERM="" />
- <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15" PADName="AK9" SLEW="" name="ddr3_ba[2]" IN_TERM="" />
- <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15" PADName="AC11" SLEW="" name="ddr3_cas_n" IN_TERM="" />
- <Pin VCCAUX_IO="HIGH" IOSTANDARD="DIFF_SSTL15" PADName="AH10" SLEW="" name="ddr3_ck_n[0]" IN_TERM="" />
- <Pin VCCAUX_IO="HIGH" IOSTANDARD="DIFF_SSTL15" PADName="AG10" SLEW="" name="ddr3_ck_p[0]" IN_TERM="" />
- <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15" PADName="AF10" SLEW="" name="ddr3_cke[0]" IN_TERM="" />
- <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15" PADName="AC12" SLEW="" name="ddr3_cs_n[0]" IN_TERM="" />
- <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15" PADName="Y16" SLEW="" name="ddr3_dm[0]" IN_TERM="" />
- <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15" PADName="AB17" SLEW="" name="ddr3_dm[1]" IN_TERM="" />
- <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15" PADName="AF17" SLEW="" name="ddr3_dm[2]" IN_TERM="" />
- <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15" PADName="AE16" SLEW="" name="ddr3_dm[3]" IN_TERM="" />
- <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15" PADName="AK5" SLEW="" name="ddr3_dm[4]" IN_TERM="" />
- <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15" PADName="AJ3" SLEW="" name="ddr3_dm[5]" IN_TERM="" />
- <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15" PADName="AF6" SLEW="" name="ddr3_dm[6]" IN_TERM="" />
- <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15" PADName="AC7" SLEW="" name="ddr3_dm[7]" IN_TERM="" />
- <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="AA15" SLEW="" name="ddr3_dq[0]" IN_TERM="" />
- <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="AC19" SLEW="" name="ddr3_dq[10]" IN_TERM="" />
- <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="AD17" SLEW="" name="ddr3_dq[11]" IN_TERM="" />
- <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="AA18" SLEW="" name="ddr3_dq[12]" IN_TERM="" />
- <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="AB18" SLEW="" name="ddr3_dq[13]" IN_TERM="" />
- <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="AE18" SLEW="" name="ddr3_dq[14]" IN_TERM="" />
- <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="AD18" SLEW="" name="ddr3_dq[15]" IN_TERM="" />
- <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="AG19" SLEW="" name="ddr3_dq[16]" IN_TERM="" />
- <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="AK19" SLEW="" name="ddr3_dq[17]" IN_TERM="" />
- <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="AG18" SLEW="" name="ddr3_dq[18]" IN_TERM="" />
- <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="AF18" SLEW="" name="ddr3_dq[19]" IN_TERM="" />
- <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="AA16" SLEW="" name="ddr3_dq[1]" IN_TERM="" />
- <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="AH19" SLEW="" name="ddr3_dq[20]" IN_TERM="" />
- <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="AJ19" SLEW="" name="ddr3_dq[21]" IN_TERM="" />
- <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="AE19" SLEW="" name="ddr3_dq[22]" IN_TERM="" />
- <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="AD19" SLEW="" name="ddr3_dq[23]" IN_TERM="" />
- <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="AK16" SLEW="" name="ddr3_dq[24]" IN_TERM="" />
- <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="AJ17" SLEW="" name="ddr3_dq[25]" IN_TERM="" />
- <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="AG15" SLEW="" name="ddr3_dq[26]" IN_TERM="" />
- <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="AF15" SLEW="" name="ddr3_dq[27]" IN_TERM="" />
- <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="AH17" SLEW="" name="ddr3_dq[28]" IN_TERM="" />
- <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="AG14" SLEW="" name="ddr3_dq[29]" IN_TERM="" />
- <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="AC14" SLEW="" name="ddr3_dq[2]" IN_TERM="" />
- <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="AH15" SLEW="" name="ddr3_dq[30]" IN_TERM="" />
- <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="AK15" SLEW="" name="ddr3_dq[31]" IN_TERM="" />
- <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="AK8" SLEW="" name="ddr3_dq[32]" IN_TERM="" />
- <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="AK6" SLEW="" name="ddr3_dq[33]" IN_TERM="" />
- <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="AG7" SLEW="" name="ddr3_dq[34]" IN_TERM="" />
- <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="AF7" SLEW="" name="ddr3_dq[35]" IN_TERM="" />
- <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="AF8" SLEW="" name="ddr3_dq[36]" IN_TERM="" />
- <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="AK4" SLEW="" name="ddr3_dq[37]" IN_TERM="" />
- <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="AJ8" SLEW="" name="ddr3_dq[38]" IN_TERM="" />
- <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="AJ6" SLEW="" name="ddr3_dq[39]" IN_TERM="" />
- <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="AD14" SLEW="" name="ddr3_dq[3]" IN_TERM="" />
- <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="AH5" SLEW="" name="ddr3_dq[40]" IN_TERM="" />
- <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="AH6" SLEW="" name="ddr3_dq[41]" IN_TERM="" />
- <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="AJ2" SLEW="" name="ddr3_dq[42]" IN_TERM="" />
- <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="AH2" SLEW="" name="ddr3_dq[43]" IN_TERM="" />
- <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="AH4" SLEW="" name="ddr3_dq[44]" IN_TERM="" />
- <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="AJ4" SLEW="" name="ddr3_dq[45]" IN_TERM="" />
- <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="AK1" SLEW="" name="ddr3_dq[46]" IN_TERM="" />
- <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="AJ1" SLEW="" name="ddr3_dq[47]" IN_TERM="" />
- <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="AF1" SLEW="" name="ddr3_dq[48]" IN_TERM="" />
- <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="AF2" SLEW="" name="ddr3_dq[49]" IN_TERM="" />
- <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="AA17" SLEW="" name="ddr3_dq[4]" IN_TERM="" />
- <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="AE4" SLEW="" name="ddr3_dq[50]" IN_TERM="" />
- <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="AE3" SLEW="" name="ddr3_dq[51]" IN_TERM="" />
- <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="AF3" SLEW="" name="ddr3_dq[52]" IN_TERM="" />
- <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="AF5" SLEW="" name="ddr3_dq[53]" IN_TERM="" />
- <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="AE1" SLEW="" name="ddr3_dq[54]" IN_TERM="" />
- <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="AE5" SLEW="" name="ddr3_dq[55]" IN_TERM="" />
- <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="AC1" SLEW="" name="ddr3_dq[56]" IN_TERM="" />
- <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="AD3" SLEW="" name="ddr3_dq[57]" IN_TERM="" />
- <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="AC4" SLEW="" name="ddr3_dq[58]" IN_TERM="" />
- <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="AC5" SLEW="" name="ddr3_dq[59]" IN_TERM="" />
- <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="AB15" SLEW="" name="ddr3_dq[5]" IN_TERM="" />
- <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="AE6" SLEW="" name="ddr3_dq[60]" IN_TERM="" />
- <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="AD6" SLEW="" name="ddr3_dq[61]" IN_TERM="" />
- <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="AC2" SLEW="" name="ddr3_dq[62]" IN_TERM="" />
- <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="AD4" SLEW="" name="ddr3_dq[63]" IN_TERM="" />
- <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="AE15" SLEW="" name="ddr3_dq[6]" IN_TERM="" />
- <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="Y15" SLEW="" name="ddr3_dq[7]" IN_TERM="" />
- <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="AB19" SLEW="" name="ddr3_dq[8]" IN_TERM="" />
- <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="AD16" SLEW="" name="ddr3_dq[9]" IN_TERM="" />
- <Pin VCCAUX_IO="HIGH" IOSTANDARD="DIFF_SSTL15_T_DCI" PADName="AC15" SLEW="" name="ddr3_dqs_n[0]" IN_TERM="" />
- <Pin VCCAUX_IO="HIGH" IOSTANDARD="DIFF_SSTL15_T_DCI" PADName="Y18" SLEW="" name="ddr3_dqs_n[1]" IN_TERM="" />
- <Pin VCCAUX_IO="HIGH" IOSTANDARD="DIFF_SSTL15_T_DCI" PADName="AK18" SLEW="" name="ddr3_dqs_n[2]" IN_TERM="" />
- <Pin VCCAUX_IO="HIGH" IOSTANDARD="DIFF_SSTL15_T_DCI" PADName="AJ16" SLEW="" name="ddr3_dqs_n[3]" IN_TERM="" />
- <Pin VCCAUX_IO="HIGH" IOSTANDARD="DIFF_SSTL15_T_DCI" PADName="AJ7" SLEW="" name="ddr3_dqs_n[4]" IN_TERM="" />
- <Pin VCCAUX_IO="HIGH" IOSTANDARD="DIFF_SSTL15_T_DCI" PADName="AH1" SLEW="" name="ddr3_dqs_n[5]" IN_TERM="" />
- <Pin VCCAUX_IO="HIGH" IOSTANDARD="DIFF_SSTL15_T_DCI" PADName="AG3" SLEW="" name="ddr3_dqs_n[6]" IN_TERM="" />
- <Pin VCCAUX_IO="HIGH" IOSTANDARD="DIFF_SSTL15_T_DCI" PADName="AD1" SLEW="" name="ddr3_dqs_n[7]" IN_TERM="" />
- <Pin VCCAUX_IO="HIGH" IOSTANDARD="DIFF_SSTL15_T_DCI" PADName="AC16" SLEW="" name="ddr3_dqs_p[0]" IN_TERM="" />
- <Pin VCCAUX_IO="HIGH" IOSTANDARD="DIFF_SSTL15_T_DCI" PADName="Y19" SLEW="" name="ddr3_dqs_p[1]" IN_TERM="" />
- <Pin VCCAUX_IO="HIGH" IOSTANDARD="DIFF_SSTL15_T_DCI" PADName="AJ18" SLEW="" name="ddr3_dqs_p[2]" IN_TERM="" />
- <Pin VCCAUX_IO="HIGH" IOSTANDARD="DIFF_SSTL15_T_DCI" PADName="AH16" SLEW="" name="ddr3_dqs_p[3]" IN_TERM="" />
- <Pin VCCAUX_IO="HIGH" IOSTANDARD="DIFF_SSTL15_T_DCI" PADName="AH7" SLEW="" name="ddr3_dqs_p[4]" IN_TERM="" />
- <Pin VCCAUX_IO="HIGH" IOSTANDARD="DIFF_SSTL15_T_DCI" PADName="AG2" SLEW="" name="ddr3_dqs_p[5]" IN_TERM="" />
- <Pin VCCAUX_IO="HIGH" IOSTANDARD="DIFF_SSTL15_T_DCI" PADName="AG4" SLEW="" name="ddr3_dqs_p[6]" IN_TERM="" />
- <Pin VCCAUX_IO="HIGH" IOSTANDARD="DIFF_SSTL15_T_DCI" PADName="AD2" SLEW="" name="ddr3_dqs_p[7]" IN_TERM="" />
- <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15" PADName="AD8" SLEW="" name="ddr3_odt[0]" IN_TERM="" />
- <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15" PADName="AD9" SLEW="" name="ddr3_ras_n" IN_TERM="" />
- <Pin VCCAUX_IO="HIGH" IOSTANDARD="LVCMOS15" PADName="AK3" SLEW="" name="ddr3_reset_n" IN_TERM="" />
- <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15" PADName="AE9" SLEW="" name="ddr3_we_n" IN_TERM="" />
- </PinSelection>
- <System_Control>
- <Pin PADName="No connect" Bank="Select Bank" name="sys_rst" />
- <Pin PADName="No connect" Bank="Select Bank" name="init_calib_complete" />
- <Pin PADName="No connect" Bank="Select Bank" name="tg_compare_error" />
- </System_Control>
- <TimingParameters>
- <Parameters twtr="7.5" trrd="6" trefi="7.8" tfaw="30" trtp="7.5" tcke="5" trfc="110" trp="13.75" tras="35" trcd="13.75" />
- </TimingParameters>
- <mrBurstLength name="Burst Length" >8 - Fixed</mrBurstLength>
- <mrBurstType name="Read Burst Type and Length" >Sequential</mrBurstType>
- <mrCasLatency name="CAS Latency" >11</mrCasLatency>
- <mrMode name="Mode" >Normal</mrMode>
- <mrDllReset name="DLL Reset" >No</mrDllReset>
- <mrPdMode name="DLL control for precharge PD" >Slow Exit</mrPdMode>
- <emrDllEnable name="DLL Enable" >Enable</emrDllEnable>
- <emrOutputDriveStrength name="Output Driver Impedance Control" >RZQ/7</emrOutputDriveStrength>
- <emrMirrorSelection name="Address Mirroring" >Disable</emrMirrorSelection>
- <emrCSSelection name="Controller Chip Select Pin" >Enable</emrCSSelection>
- <emrRTT name="RTT (nominal) - On Die Termination (ODT)" >RZQ/6</emrRTT>
- <emrPosted name="Additive Latency (AL)" >0</emrPosted>
- <emrOCD name="Write Leveling Enable" >Disabled</emrOCD>
- <emrDQS name="TDQS enable" >Enabled</emrDQS>
- <emrRDQS name="Qoff" >Output Buffer Enabled</emrRDQS>
- <mr2PartialArraySelfRefresh name="Partial-Array Self Refresh" >Full Array</mr2PartialArraySelfRefresh>
- <mr2CasWriteLatency name="CAS write latency" >8</mr2CasWriteLatency>
- <mr2AutoSelfRefresh name="Auto Self Refresh" >Enabled</mr2AutoSelfRefresh>
- <mr2SelfRefreshTempRange name="High Temparature Self Refresh Rate" >Normal</mr2SelfRefreshTempRange>
- <mr2RTTWR name="RTT_WR - Dynamic On Die Termination (ODT)" >Dynamic ODT off</mr2RTTWR>
- <PortInterface>AXI</PortInterface>
- <AXIParameters>
- <C0_C_RD_WR_ARB_ALGORITHM>RD_PRI_REG</C0_C_RD_WR_ARB_ALGORITHM>
- <C0_S_AXI_ADDR_WIDTH>30</C0_S_AXI_ADDR_WIDTH>
- <C0_S_AXI_DATA_WIDTH>64</C0_S_AXI_DATA_WIDTH>
- <C0_S_AXI_ID_WIDTH>4</C0_S_AXI_ID_WIDTH>
- <C0_S_AXI_SUPPORTS_NARROW_BURST>0</C0_S_AXI_SUPPORTS_NARROW_BURST>
- </AXIParameters>
- </Controller>
-
-</Project>
diff --git a/fpga/xilinx/xlnx_mig_7_ddr3/mig_vc707.prj b/fpga/xilinx/xlnx_mig_7_ddr3/mig_vc707.prj
deleted file mode 100644
index fcf0bbe9..00000000
--- a/fpga/xilinx/xlnx_mig_7_ddr3/mig_vc707.prj
+++ /dev/null
@@ -1,203 +0,0 @@
-<?xml version='1.0' encoding='UTF-8'?>
-<!-- IMPORTANT: This is an internal file that has been generated by the MIG software. Any direct editing or changes made to this file may result in unpredictable behavior or data corruption. It is strongly advised that users do not edit the contents of this file. Re-run the MIG GUI with the required settings if any of the options provided below need to be altered. -->
-<Project NoOfControllers="1" >
- <ModuleName>xlnx_mig_7_ddr3</ModuleName>
- <dci_inouts_inputs>1</dci_inouts_inputs>
- <dci_inputs>1</dci_inputs>
- <Debug_En>OFF</Debug_En>
- <DataDepth_En>1024</DataDepth_En>
- <LowPower_En>ON</LowPower_En>
- <XADC_En>Enabled</XADC_En>
- <TargetFPGA>xc7vx485t-ffg1761/-2</TargetFPGA>
- <Version>4.1</Version>
- <SystemClock>Differential</SystemClock>
- <ReferenceClock>Use System Clock</ReferenceClock>
- <SysResetPolarity>ACTIVE LOW</SysResetPolarity>
- <BankSelectionFlag>FALSE</BankSelectionFlag>
- <InternalVref>0</InternalVref>
- <dci_hr_inouts_inputs>50 Ohms</dci_hr_inouts_inputs>
- <dci_cascade>0</dci_cascade>
- <Controller number="0" >
- <MemoryDevice>DDR3_SDRAM/SODIMMs/MT8JTF12864HZ-1G6</MemoryDevice>
- <TimePeriod>1250</TimePeriod>
- <VccAuxIO>2.0V</VccAuxIO>
- <PHYRatio>4:1</PHYRatio>
- <InputClkFreq>200</InputClkFreq>
- <UIExtraClocks>0</UIExtraClocks>
- <MMCM_VCO>800</MMCM_VCO>
- <MMCMClkOut0> 1.000</MMCMClkOut0>
- <MMCMClkOut1>1</MMCMClkOut1>
- <MMCMClkOut2>1</MMCMClkOut2>
- <MMCMClkOut3>1</MMCMClkOut3>
- <MMCMClkOut4>1</MMCMClkOut4>
- <DataWidth>64</DataWidth>
- <DeepMemory>1</DeepMemory>
- <DataMask>1</DataMask>
- <ECC>Disabled</ECC>
- <Ordering>Normal</Ordering>
- <BankMachineCnt>4</BankMachineCnt>
- <CustomPart>FALSE</CustomPart>
- <NewPartName></NewPartName>
- <RowAddress>14</RowAddress>
- <ColAddress>10</ColAddress>
- <BankAddress>3</BankAddress>
- <MemoryVoltage>1.5V</MemoryVoltage>
- <UserMemoryAddressMap>BANK_ROW_COLUMN</UserMemoryAddressMap>
- <PinSelection>
- <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15" PADName="A20" SLEW="" name="ddr3_addr[0]" IN_TERM="" />
- <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15" PADName="B21" SLEW="" name="ddr3_addr[10]" IN_TERM="" />
- <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15" PADName="B17" SLEW="" name="ddr3_addr[11]" IN_TERM="" />
- <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15" PADName="A15" SLEW="" name="ddr3_addr[12]" IN_TERM="" />
- <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15" PADName="A21" SLEW="" name="ddr3_addr[13]" IN_TERM="" />
- <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15" PADName="B19" SLEW="" name="ddr3_addr[1]" IN_TERM="" />
- <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15" PADName="C20" SLEW="" name="ddr3_addr[2]" IN_TERM="" />
- <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15" PADName="A19" SLEW="" name="ddr3_addr[3]" IN_TERM="" />
- <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15" PADName="A17" SLEW="" name="ddr3_addr[4]" IN_TERM="" />
- <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15" PADName="A16" SLEW="" name="ddr3_addr[5]" IN_TERM="" />
- <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15" PADName="D20" SLEW="" name="ddr3_addr[6]" IN_TERM="" />
- <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15" PADName="C18" SLEW="" name="ddr3_addr[7]" IN_TERM="" />
- <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15" PADName="D17" SLEW="" name="ddr3_addr[8]" IN_TERM="" />
- <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15" PADName="C19" SLEW="" name="ddr3_addr[9]" IN_TERM="" />
- <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15" PADName="D21" SLEW="" name="ddr3_ba[0]" IN_TERM="" />
- <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15" PADName="C21" SLEW="" name="ddr3_ba[1]" IN_TERM="" />
- <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15" PADName="D18" SLEW="" name="ddr3_ba[2]" IN_TERM="" />
- <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15" PADName="K17" SLEW="" name="ddr3_cas_n" IN_TERM="" />
- <Pin VCCAUX_IO="HIGH" IOSTANDARD="DIFF_SSTL15" PADName="G18" SLEW="" name="ddr3_ck_n[0]" IN_TERM="" />
- <Pin VCCAUX_IO="HIGH" IOSTANDARD="DIFF_SSTL15" PADName="H19" SLEW="" name="ddr3_ck_p[0]" IN_TERM="" />
- <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15" PADName="K19" SLEW="" name="ddr3_cke[0]" IN_TERM="" />
- <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15" PADName="J17" SLEW="" name="ddr3_cs_n[0]" IN_TERM="" />
- <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15" PADName="M13" SLEW="" name="ddr3_dm[0]" IN_TERM="" />
- <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15" PADName="K15" SLEW="" name="ddr3_dm[1]" IN_TERM="" />
- <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15" PADName="F12" SLEW="" name="ddr3_dm[2]" IN_TERM="" />
- <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15" PADName="A14" SLEW="" name="ddr3_dm[3]" IN_TERM="" />
- <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15" PADName="C23" SLEW="" name="ddr3_dm[4]" IN_TERM="" />
- <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15" PADName="D25" SLEW="" name="ddr3_dm[5]" IN_TERM="" />
- <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15" PADName="C31" SLEW="" name="ddr3_dm[6]" IN_TERM="" />
- <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15" PADName="F31" SLEW="" name="ddr3_dm[7]" IN_TERM="" />
- <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="N14" SLEW="" name="ddr3_dq[0]" IN_TERM="" />
- <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="H13" SLEW="" name="ddr3_dq[10]" IN_TERM="" />
- <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="J13" SLEW="" name="ddr3_dq[11]" IN_TERM="" />
- <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="L16" SLEW="" name="ddr3_dq[12]" IN_TERM="" />
- <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="L15" SLEW="" name="ddr3_dq[13]" IN_TERM="" />
- <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="H14" SLEW="" name="ddr3_dq[14]" IN_TERM="" />
- <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="J15" SLEW="" name="ddr3_dq[15]" IN_TERM="" />
- <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="E15" SLEW="" name="ddr3_dq[16]" IN_TERM="" />
- <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="E13" SLEW="" name="ddr3_dq[17]" IN_TERM="" />
- <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="F15" SLEW="" name="ddr3_dq[18]" IN_TERM="" />
- <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="E14" SLEW="" name="ddr3_dq[19]" IN_TERM="" />
- <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="N13" SLEW="" name="ddr3_dq[1]" IN_TERM="" />
- <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="G13" SLEW="" name="ddr3_dq[20]" IN_TERM="" />
- <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="G12" SLEW="" name="ddr3_dq[21]" IN_TERM="" />
- <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="F14" SLEW="" name="ddr3_dq[22]" IN_TERM="" />
- <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="G14" SLEW="" name="ddr3_dq[23]" IN_TERM="" />
- <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="B14" SLEW="" name="ddr3_dq[24]" IN_TERM="" />
- <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="C13" SLEW="" name="ddr3_dq[25]" IN_TERM="" />
- <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="B16" SLEW="" name="ddr3_dq[26]" IN_TERM="" />
- <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="D15" SLEW="" name="ddr3_dq[27]" IN_TERM="" />
- <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="D13" SLEW="" name="ddr3_dq[28]" IN_TERM="" />
- <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="E12" SLEW="" name="ddr3_dq[29]" IN_TERM="" />
- <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="L14" SLEW="" name="ddr3_dq[2]" IN_TERM="" />
- <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="C16" SLEW="" name="ddr3_dq[30]" IN_TERM="" />
- <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="D16" SLEW="" name="ddr3_dq[31]" IN_TERM="" />
- <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="A24" SLEW="" name="ddr3_dq[32]" IN_TERM="" />
- <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="B23" SLEW="" name="ddr3_dq[33]" IN_TERM="" />
- <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="B27" SLEW="" name="ddr3_dq[34]" IN_TERM="" />
- <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="B26" SLEW="" name="ddr3_dq[35]" IN_TERM="" />
- <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="A22" SLEW="" name="ddr3_dq[36]" IN_TERM="" />
- <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="B22" SLEW="" name="ddr3_dq[37]" IN_TERM="" />
- <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="A25" SLEW="" name="ddr3_dq[38]" IN_TERM="" />
- <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="C24" SLEW="" name="ddr3_dq[39]" IN_TERM="" />
- <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="M14" SLEW="" name="ddr3_dq[3]" IN_TERM="" />
- <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="E24" SLEW="" name="ddr3_dq[40]" IN_TERM="" />
- <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="D23" SLEW="" name="ddr3_dq[41]" IN_TERM="" />
- <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="D26" SLEW="" name="ddr3_dq[42]" IN_TERM="" />
- <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="C25" SLEW="" name="ddr3_dq[43]" IN_TERM="" />
- <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="E23" SLEW="" name="ddr3_dq[44]" IN_TERM="" />
- <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="D22" SLEW="" name="ddr3_dq[45]" IN_TERM="" />
- <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="F22" SLEW="" name="ddr3_dq[46]" IN_TERM="" />
- <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="E22" SLEW="" name="ddr3_dq[47]" IN_TERM="" />
- <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="A30" SLEW="" name="ddr3_dq[48]" IN_TERM="" />
- <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="D27" SLEW="" name="ddr3_dq[49]" IN_TERM="" />
- <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="M12" SLEW="" name="ddr3_dq[4]" IN_TERM="" />
- <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="A29" SLEW="" name="ddr3_dq[50]" IN_TERM="" />
- <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="C28" SLEW="" name="ddr3_dq[51]" IN_TERM="" />
- <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="D28" SLEW="" name="ddr3_dq[52]" IN_TERM="" />
- <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="B31" SLEW="" name="ddr3_dq[53]" IN_TERM="" />
- <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="A31" SLEW="" name="ddr3_dq[54]" IN_TERM="" />
- <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="A32" SLEW="" name="ddr3_dq[55]" IN_TERM="" />
- <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="E30" SLEW="" name="ddr3_dq[56]" IN_TERM="" />
- <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="F29" SLEW="" name="ddr3_dq[57]" IN_TERM="" />
- <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="F30" SLEW="" name="ddr3_dq[58]" IN_TERM="" />
- <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="F27" SLEW="" name="ddr3_dq[59]" IN_TERM="" />
- <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="N15" SLEW="" name="ddr3_dq[5]" IN_TERM="" />
- <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="C30" SLEW="" name="ddr3_dq[60]" IN_TERM="" />
- <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="E29" SLEW="" name="ddr3_dq[61]" IN_TERM="" />
- <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="F26" SLEW="" name="ddr3_dq[62]" IN_TERM="" />
- <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="D30" SLEW="" name="ddr3_dq[63]" IN_TERM="" />
- <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="M11" SLEW="" name="ddr3_dq[6]" IN_TERM="" />
- <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="L12" SLEW="" name="ddr3_dq[7]" IN_TERM="" />
- <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="K14" SLEW="" name="ddr3_dq[8]" IN_TERM="" />
- <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="K13" SLEW="" name="ddr3_dq[9]" IN_TERM="" />
- <Pin VCCAUX_IO="HIGH" IOSTANDARD="DIFF_SSTL15_T_DCI" PADName="M16" SLEW="" name="ddr3_dqs_n[0]" IN_TERM="" />
- <Pin VCCAUX_IO="HIGH" IOSTANDARD="DIFF_SSTL15_T_DCI" PADName="J12" SLEW="" name="ddr3_dqs_n[1]" IN_TERM="" />
- <Pin VCCAUX_IO="HIGH" IOSTANDARD="DIFF_SSTL15_T_DCI" PADName="G16" SLEW="" name="ddr3_dqs_n[2]" IN_TERM="" />
- <Pin VCCAUX_IO="HIGH" IOSTANDARD="DIFF_SSTL15_T_DCI" PADName="C14" SLEW="" name="ddr3_dqs_n[3]" IN_TERM="" />
- <Pin VCCAUX_IO="HIGH" IOSTANDARD="DIFF_SSTL15_T_DCI" PADName="A27" SLEW="" name="ddr3_dqs_n[4]" IN_TERM="" />
- <Pin VCCAUX_IO="HIGH" IOSTANDARD="DIFF_SSTL15_T_DCI" PADName="E25" SLEW="" name="ddr3_dqs_n[5]" IN_TERM="" />
- <Pin VCCAUX_IO="HIGH" IOSTANDARD="DIFF_SSTL15_T_DCI" PADName="B29" SLEW="" name="ddr3_dqs_n[6]" IN_TERM="" />
- <Pin VCCAUX_IO="HIGH" IOSTANDARD="DIFF_SSTL15_T_DCI" PADName="E28" SLEW="" name="ddr3_dqs_n[7]" IN_TERM="" />
- <Pin VCCAUX_IO="HIGH" IOSTANDARD="DIFF_SSTL15_T_DCI" PADName="N16" SLEW="" name="ddr3_dqs_p[0]" IN_TERM="" />
- <Pin VCCAUX_IO="HIGH" IOSTANDARD="DIFF_SSTL15_T_DCI" PADName="K12" SLEW="" name="ddr3_dqs_p[1]" IN_TERM="" />
- <Pin VCCAUX_IO="HIGH" IOSTANDARD="DIFF_SSTL15_T_DCI" PADName="H16" SLEW="" name="ddr3_dqs_p[2]" IN_TERM="" />
- <Pin VCCAUX_IO="HIGH" IOSTANDARD="DIFF_SSTL15_T_DCI" PADName="C15" SLEW="" name="ddr3_dqs_p[3]" IN_TERM="" />
- <Pin VCCAUX_IO="HIGH" IOSTANDARD="DIFF_SSTL15_T_DCI" PADName="A26" SLEW="" name="ddr3_dqs_p[4]" IN_TERM="" />
- <Pin VCCAUX_IO="HIGH" IOSTANDARD="DIFF_SSTL15_T_DCI" PADName="F25" SLEW="" name="ddr3_dqs_p[5]" IN_TERM="" />
- <Pin VCCAUX_IO="HIGH" IOSTANDARD="DIFF_SSTL15_T_DCI" PADName="B28" SLEW="" name="ddr3_dqs_p[6]" IN_TERM="" />
- <Pin VCCAUX_IO="HIGH" IOSTANDARD="DIFF_SSTL15_T_DCI" PADName="E27" SLEW="" name="ddr3_dqs_p[7]" IN_TERM="" />
- <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15" PADName="H20" SLEW="" name="ddr3_odt[0]" IN_TERM="" />
- <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15" PADName="E20" SLEW="" name="ddr3_ras_n" IN_TERM="" />
- <Pin VCCAUX_IO="HIGH" IOSTANDARD="LVCMOS15" PADName="C29" SLEW="" name="ddr3_reset_n" IN_TERM="" />
- <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15" PADName="F20" SLEW="" name="ddr3_we_n" IN_TERM="" />
- </PinSelection>
- <System_Clock>
- <Pin PADName="E19/E18(CC_P/N)" Bank="38" name="sys_clk_p/n" />
- </System_Clock>
- <System_Control>
- <Pin PADName="AV40(MRCC_P)" Bank="15" name="sys_rst" />
- <Pin PADName="No connect" Bank="Select Bank" name="init_calib_complete" />
- <Pin PADName="No connect" Bank="Select Bank" name="tg_compare_error" />
- </System_Control>
- <TimingParameters>
- <Parameters twtr="7.5" trrd="6" trefi="7.8" tfaw="30" trtp="7.5" tcke="5" trfc="110" trp="13.75" tras="35" trcd="13.75" />
- </TimingParameters>
- <mrBurstLength name="Burst Length" >8 - Fixed</mrBurstLength>
- <mrBurstType name="Read Burst Type and Length" >Sequential</mrBurstType>
- <mrCasLatency name="CAS Latency" >11</mrCasLatency>
- <mrMode name="Mode" >Normal</mrMode>
- <mrDllReset name="DLL Reset" >No</mrDllReset>
- <mrPdMode name="DLL control for precharge PD" >Slow Exit</mrPdMode>
- <emrDllEnable name="DLL Enable" >Enable</emrDllEnable>
- <emrOutputDriveStrength name="Output Driver Impedance Control" >RZQ/7</emrOutputDriveStrength>
- <emrMirrorSelection name="Address Mirroring" >Disable</emrMirrorSelection>
- <emrCSSelection name="Controller Chip Select Pin" >Enable</emrCSSelection>
- <emrRTT name="RTT (nominal) - On Die Termination (ODT)" >RZQ/6</emrRTT>
- <emrPosted name="Additive Latency (AL)" >0</emrPosted>
- <emrOCD name="Write Leveling Enable" >Disabled</emrOCD>
- <emrDQS name="TDQS enable" >Enabled</emrDQS>
- <emrRDQS name="Qoff" >Output Buffer Enabled</emrRDQS>
- <mr2PartialArraySelfRefresh name="Partial-Array Self Refresh" >Full Array</mr2PartialArraySelfRefresh>
- <mr2CasWriteLatency name="CAS write latency" >8</mr2CasWriteLatency>
- <mr2AutoSelfRefresh name="Auto Self Refresh" >Enabled</mr2AutoSelfRefresh>
- <mr2SelfRefreshTempRange name="High Temparature Self Refresh Rate" >Normal</mr2SelfRefreshTempRange>
- <mr2RTTWR name="RTT_WR - Dynamic On Die Termination (ODT)" >Dynamic ODT off</mr2RTTWR>
- <PortInterface>AXI</PortInterface>
- <AXIParameters>
- <C0_C_RD_WR_ARB_ALGORITHM>RD_PRI_REG</C0_C_RD_WR_ARB_ALGORITHM>
- <C0_S_AXI_ADDR_WIDTH>30</C0_S_AXI_ADDR_WIDTH>
- <C0_S_AXI_DATA_WIDTH>64</C0_S_AXI_DATA_WIDTH>
- <C0_S_AXI_ID_WIDTH>5</C0_S_AXI_ID_WIDTH>
- <C0_S_AXI_SUPPORTS_NARROW_BURST>0</C0_S_AXI_SUPPORTS_NARROW_BURST>
- </AXIParameters>
- </Controller>
-
-</Project>
diff --git a/fpga/xilinx/xlnx_mig_7_ddr3/tcl/run.tcl b/fpga/xilinx/xlnx_mig_7_ddr3/tcl/run.tcl
deleted file mode 100644
index bb257600..00000000
--- a/fpga/xilinx/xlnx_mig_7_ddr3/tcl/run.tcl
+++ /dev/null
@@ -1,20 +0,0 @@
-set partNumber $::env(XILINX_PART)
-set boardName $::env(XILINX_BOARD)
-set boardNameShort $::env(BOARD)
-
-set ipName xlnx_mig_7_ddr3
-
-create_project $ipName . -force -part $partNumber
-set_property board_part $boardName [current_project]
-
-create_ip -name mig_7series -vendor xilinx.com -library ip -module_name $ipName
-
-exec cp mig_$boardNameShort.prj ./$ipName.srcs/sources_1/ip/$ipName/mig_a.prj
-
-set_property -dict [list CONFIG.XML_INPUT_FILE {mig_a.prj} CONFIG.RESET_BOARD_INTERFACE {Custom} CONFIG.MIG_DONT_TOUCH_PARAM {Custom} CONFIG.BOARD_MIG_PARAM {Custom}] [get_ips $ipName]
-
-generate_target {instantiation_template} [get_files ./$ipName.srcs/sources_1/ip/$ipName/$ipName.xci]
-generate_target all [get_files ./$ipName.srcs/sources_1/ip/$ipName/$ipName.xci]
-create_ip_run [get_files -of_objects [get_fileset sources_1] ./$ipName.srcs/sources_1/ip/$ipName/$ipName.xci]
-launch_run -jobs 8 ${ipName}_synth_1
-wait_on_run ${ipName}_synth_1
diff --git a/fpga/xilinx/xlnx_protocol_checker/Makefile b/fpga/xilinx/xlnx_protocol_checker/Makefile
deleted file mode 100644
index 409144b2..00000000
--- a/fpga/xilinx/xlnx_protocol_checker/Makefile
+++ /dev/null
@@ -1,2 +0,0 @@
-PROJECT:=xlnx_protocol_checker
-include ../common.mk
\ No newline at end of file
diff --git a/fpga/xilinx/xlnx_protocol_checker/tcl/run.tcl b/fpga/xilinx/xlnx_protocol_checker/tcl/run.tcl
deleted file mode 100644
index 143d9fdb..00000000
--- a/fpga/xilinx/xlnx_protocol_checker/tcl/run.tcl
+++ /dev/null
@@ -1,35 +0,0 @@
-set partNumber $::env(XILINX_PART)
-set boardName $::env(XILINX_BOARD)
-
-set ipName xlnx_protocol_checker
-
-create_project $ipName . -force -part $partNumber
-set_property board_part $boardName [current_project]
-
-create_ip -name axi_protocol_checker -vendor xilinx.com -library ip -version 2.0 -module_name $ipName
-
-set_property -dict [list CONFIG.ADDR_WIDTH {64} \
- CONFIG.DATA_WIDTH {64} \
- CONFIG.ID_WIDTH {5} \
- CONFIG.AWUSER_WIDTH {1} \
- CONFIG.ARUSER_WIDTH {1} \
- CONFIG.RUSER_WIDTH {1} \
- CONFIG.WUSER_WIDTH {1} \
- CONFIG.BUSER_WIDTH {1} \
- CONFIG.MAX_AW_WAITS {1024} \
- CONFIG.MAX_AR_WAITS {1024} \
- CONFIG.MAX_W_WAITS {1024} \
- CONFIG.MAX_R_WAITS {1024} \
- CONFIG.MAX_B_WAITS {1024} \
- CONFIG.MAX_CONTINUOUS_WTRANSFERS_WAITS {1024} \
- CONFIG.MAX_WLAST_TO_AWVALID_WAITS {1024} \
- CONFIG.MAX_WRITE_TO_BVALID_WAITS {1024} \
- CONFIG.MAX_CONTINUOUS_RTRANSFERS_WAITS {1024} \
- ] [get_ips $ipName]
-
-
-generate_target {instantiation_template} [get_files ./$ipName.srcs/sources_1/ip/$ipName/$ipName.xci]
-generate_target all [get_files ./$ipName.srcs/sources_1/ip/$ipName/$ipName.xci]
-create_ip_run [get_files -of_objects [get_fileset sources_1] ./$ipName.srcs/sources_1/ip/$ipName/$ipName.xci]
-launch_run -jobs 8 ${ipName}_synth_1
-wait_on_run ${ipName}_synth_1
\ No newline at end of file
diff --git a/include/ariane_axi_pkg.sv b/include/ariane_axi_pkg.sv
index 45583e3e..66837518 100644
--- a/include/ariane_axi_pkg.sv
+++ b/include/ariane_axi_pkg.sv
@@ -45,7 +45,7 @@ package ariane_axi;
axi_pkg::qos_t qos;
axi_pkg::region_t region;
axi_pkg::atop_t atop;
- user_t user;
+ // user_t user;
} aw_chan_t;
// AW Channel - Slave
@@ -61,7 +61,7 @@ package ariane_axi;
axi_pkg::qos_t qos;
axi_pkg::region_t region;
axi_pkg::atop_t atop;
- user_t user;
+ //user_t user;
} aw_chan_slv_t;
// W Channel - AXI4 doesn't define a wid
@@ -69,21 +69,21 @@ package ariane_axi;
data_t data;
strb_t strb;
logic last;
- user_t user;
+ //user_t user;
} w_chan_t;
// B Channel
typedef struct packed {
id_t id;
axi_pkg::resp_t resp;
- user_t user;
+ //user_t user;
} b_chan_t;
// B Channel - Slave
typedef struct packed {
id_slv_t id;
axi_pkg::resp_t resp;
- user_t user;
+ //user_t user;
} b_chan_slv_t;
// AR Channel
@@ -98,7 +98,7 @@ package ariane_axi;
axi_pkg::prot_t prot;
axi_pkg::qos_t qos;
axi_pkg::region_t region;
- user_t user;
+ //user_t user;
} ar_chan_t;
// AR Channel - Slave
@@ -113,7 +113,7 @@ package ariane_axi;
axi_pkg::prot_t prot;
axi_pkg::qos_t qos;
axi_pkg::region_t region;
- user_t user;
+ //user_t user;
} ar_chan_slv_t;
// R Channel
@@ -122,7 +122,7 @@ package ariane_axi;
data_t data;
axi_pkg::resp_t resp;
logic last;
- user_t user;
+ //user_t user;
} r_chan_t;
// R Channel - Slave
@@ -131,7 +131,7 @@ package ariane_axi;
data_t data;
axi_pkg::resp_t resp;
logic last;
- user_t user;
+ //user_t user;
} r_chan_slv_t;
// Request/Response structs
diff --git a/include/ariane_pkg.sv b/include/ariane_pkg.sv
index 70c0af88..0b9447fc 100644
--- a/include/ariane_pkg.sv
+++ b/include/ariane_pkg.sv
@@ -610,6 +610,11 @@ package ariane_pkg;
// we want jump accordingly e.g.: +4, +2
} scoreboard_entry_t;
+ // ---------------
+ // MMU instanciation
+ // ---------------
+ localparam bit MMU_PRESENT = 1'b0; // MMU is present
+
// --------------------
// Atomics
// --------------------
diff --git a/include/riscv_pkg.sv b/include/riscv_pkg.sv
index 238663b0..45809efb 100644
--- a/include/riscv_pkg.sv
+++ b/include/riscv_pkg.sv
@@ -28,7 +28,7 @@ package riscv;
ModeSv64 = 11
} vm_mode_t;
- localparam XLEN = 64;
+ localparam XLEN = 32;
// Warning: When using STD_CACHE, configuration must be PLEN=56 and VLEN=64
// Warning: VLEN must be superior or equal to PLEN
@@ -633,10 +633,19 @@ package riscv;
return {csr, 5'h0, 3'h2, dest, 7'h73};
endfunction
+ function automatic logic [31:0] branch(logic [4:0] src2, logic [4:0] src1, logic [2:0] funct3, logic [11:0] offset);
+ // OpCode Branch
+ return {offset[11], offset[9:4], src2, src1, funct3, offset[3:0], offset[10], 7'b11_000_11};
+ endfunction
+
function automatic logic [31:0] ebreak ();
return 32'h00100073;
endfunction
+ function automatic logic [31:0] wfi ();
+ return 32'h10500073;
+ endfunction
+
function automatic logic [31:0] nop ();
return 32'h00000013;
endfunction
diff --git a/src/axi_adapter.sv b/src/axi_adapter.sv
index e9c2b208..a73f5dab 100644
--- a/src/axi_adapter.sv
+++ b/src/axi_adapter.sv
@@ -76,7 +76,7 @@ module axi_adapter #(
axi_req_o.aw.qos = 4'b0;
axi_req_o.aw.id = id_i;
axi_req_o.aw.atop = '0; // currently not used
- axi_req_o.aw.user = '0;
+ //axi_req_o.aw.user = '0;
axi_req_o.ar_valid = 1'b0;
// in case of a single request or wrapping transfer we can simply begin at the address, if we want to request a cache-line
@@ -91,13 +91,13 @@ module axi_adapter #(
axi_req_o.ar.cache = 4'b0;
axi_req_o.ar.qos = 4'b0;
axi_req_o.ar.id = id_i;
- axi_req_o.ar.user = '0;
+ // axi_req_o.ar.user = '0;
axi_req_o.w_valid = 1'b0;
axi_req_o.w.data = wdata_i[0];
axi_req_o.w.strb = be_i[0];
axi_req_o.w.last = 1'b0;
- axi_req_o.w.user = '0;
+ //axi_req_o.w.user = '0;
axi_req_o.b_ready = 1'b0;
axi_req_o.r_ready = 1'b0;
diff --git a/src/csr_regfile.sv b/src/csr_regfile.sv
index 2c65d0e1..46587622 100644
--- a/src/csr_regfile.sv
+++ b/src/csr_regfile.sv
@@ -140,7 +140,7 @@ module csr_regfile import ariane_pkg::*; #(
riscv::xlen_t instret_q, instret_d;
riscv::pmpcfg_t [15:0] pmpcfg_q, pmpcfg_d;
- logic [15:0][riscv::VLEN-3:0] pmpaddr_q, pmpaddr_d;
+ logic [15:0][riscv::PLEN-3:0] pmpaddr_q, pmpaddr_d;
assign pmpcfg_o = pmpcfg_q[15:0];
@@ -287,22 +287,22 @@ module csr_regfile import ariane_pkg::*; #(
// -> last bit of pmpaddr must be set 0/1 based on the mode:
// NA4, NAPOT: 1
// TOR, OFF: 0
- riscv::CSR_PMPADDR0: csr_rdata = {10'b0, pmpaddr_q[0][riscv::VLEN-3:1], (pmpcfg_q[0].addr_mode[1] == 1'b1 ? 1'b1 : 1'b0)};
- riscv::CSR_PMPADDR1: csr_rdata = {10'b0, pmpaddr_q[1][riscv::VLEN-3:1], (pmpcfg_q[1].addr_mode[1] == 1'b1 ? 1'b1 : 1'b0)};
- riscv::CSR_PMPADDR2: csr_rdata = {10'b0, pmpaddr_q[2][riscv::VLEN-3:1], (pmpcfg_q[2].addr_mode[1] == 1'b1 ? 1'b1 : 1'b0)};
- riscv::CSR_PMPADDR3: csr_rdata = {10'b0, pmpaddr_q[3][riscv::VLEN-3:1], (pmpcfg_q[3].addr_mode[1] == 1'b1 ? 1'b1 : 1'b0)};
- riscv::CSR_PMPADDR4: csr_rdata = {10'b0, pmpaddr_q[4][riscv::VLEN-3:1], (pmpcfg_q[4].addr_mode[1] == 1'b1 ? 1'b1 : 1'b0)};
- riscv::CSR_PMPADDR5: csr_rdata = {10'b0, pmpaddr_q[5][riscv::VLEN-3:1], (pmpcfg_q[5].addr_mode[1] == 1'b1 ? 1'b1 : 1'b0)};
- riscv::CSR_PMPADDR6: csr_rdata = {10'b0, pmpaddr_q[6][riscv::VLEN-3:1], (pmpcfg_q[6].addr_mode[1] == 1'b1 ? 1'b1 : 1'b0)};
- riscv::CSR_PMPADDR7: csr_rdata = {10'b0, pmpaddr_q[7][riscv::VLEN-3:1], (pmpcfg_q[7].addr_mode[1] == 1'b1 ? 1'b1 : 1'b0)};
- riscv::CSR_PMPADDR8: csr_rdata = {10'b0, pmpaddr_q[8][riscv::VLEN-3:1], (pmpcfg_q[8].addr_mode[1] == 1'b1 ? 1'b1 : 1'b0)};
- riscv::CSR_PMPADDR9: csr_rdata = {10'b0, pmpaddr_q[9][riscv::VLEN-3:1], (pmpcfg_q[9].addr_mode[1] == 1'b1 ? 1'b1 : 1'b0)};
- riscv::CSR_PMPADDR10: csr_rdata = {10'b0, pmpaddr_q[10][riscv::VLEN-3:1], (pmpcfg_q[10].addr_mode[1] == 1'b1 ? 1'b1 : 1'b0)};
- riscv::CSR_PMPADDR11: csr_rdata = {10'b0, pmpaddr_q[11][riscv::VLEN-3:1], (pmpcfg_q[11].addr_mode[1] == 1'b1 ? 1'b1 : 1'b0)};
- riscv::CSR_PMPADDR12: csr_rdata = {10'b0, pmpaddr_q[12][riscv::VLEN-3:1], (pmpcfg_q[12].addr_mode[1] == 1'b1 ? 1'b1 : 1'b0)};
- riscv::CSR_PMPADDR13: csr_rdata = {10'b0, pmpaddr_q[13][riscv::VLEN-3:1], (pmpcfg_q[13].addr_mode[1] == 1'b1 ? 1'b1 : 1'b0)};
- riscv::CSR_PMPADDR14: csr_rdata = {10'b0, pmpaddr_q[14][riscv::VLEN-3:1], (pmpcfg_q[14].addr_mode[1] == 1'b1 ? 1'b1 : 1'b0)};
- riscv::CSR_PMPADDR15: csr_rdata = {10'b0, pmpaddr_q[15][riscv::VLEN-3:1], (pmpcfg_q[15].addr_mode[1] == 1'b1 ? 1'b1 : 1'b0)};
+ riscv::CSR_PMPADDR0: csr_rdata = {10'b0, pmpaddr_q[0][riscv::PLEN-3:1], (pmpcfg_q[0].addr_mode[1] == 1'b1 ? 1'b1 : 1'b0)};
+ riscv::CSR_PMPADDR1: csr_rdata = {10'b0, pmpaddr_q[1][riscv::PLEN-3:1], (pmpcfg_q[1].addr_mode[1] == 1'b1 ? 1'b1 : 1'b0)};
+ riscv::CSR_PMPADDR2: csr_rdata = {10'b0, pmpaddr_q[2][riscv::PLEN-3:1], (pmpcfg_q[2].addr_mode[1] == 1'b1 ? 1'b1 : 1'b0)};
+ riscv::CSR_PMPADDR3: csr_rdata = {10'b0, pmpaddr_q[3][riscv::PLEN-3:1], (pmpcfg_q[3].addr_mode[1] == 1'b1 ? 1'b1 : 1'b0)};
+ riscv::CSR_PMPADDR4: csr_rdata = {10'b0, pmpaddr_q[4][riscv::PLEN-3:1], (pmpcfg_q[4].addr_mode[1] == 1'b1 ? 1'b1 : 1'b0)};
+ riscv::CSR_PMPADDR5: csr_rdata = {10'b0, pmpaddr_q[5][riscv::PLEN-3:1], (pmpcfg_q[5].addr_mode[1] == 1'b1 ? 1'b1 : 1'b0)};
+ riscv::CSR_PMPADDR6: csr_rdata = {10'b0, pmpaddr_q[6][riscv::PLEN-3:1], (pmpcfg_q[6].addr_mode[1] == 1'b1 ? 1'b1 : 1'b0)};
+ riscv::CSR_PMPADDR7: csr_rdata = {10'b0, pmpaddr_q[7][riscv::PLEN-3:1], (pmpcfg_q[7].addr_mode[1] == 1'b1 ? 1'b1 : 1'b0)};
+ riscv::CSR_PMPADDR8: csr_rdata = {10'b0, pmpaddr_q[8][riscv::PLEN-3:1], (pmpcfg_q[8].addr_mode[1] == 1'b1 ? 1'b1 : 1'b0)};
+ riscv::CSR_PMPADDR9: csr_rdata = {10'b0, pmpaddr_q[9][riscv::PLEN-3:1], (pmpcfg_q[9].addr_mode[1] == 1'b1 ? 1'b1 : 1'b0)};
+ riscv::CSR_PMPADDR10: csr_rdata = {10'b0, pmpaddr_q[10][riscv::PLEN-3:1], (pmpcfg_q[10].addr_mode[1] == 1'b1 ? 1'b1 : 1'b0)};
+ riscv::CSR_PMPADDR11: csr_rdata = {10'b0, pmpaddr_q[11][riscv::PLEN-3:1], (pmpcfg_q[11].addr_mode[1] == 1'b1 ? 1'b1 : 1'b0)};
+ riscv::CSR_PMPADDR12: csr_rdata = {10'b0, pmpaddr_q[12][riscv::PLEN-3:1], (pmpcfg_q[12].addr_mode[1] == 1'b1 ? 1'b1 : 1'b0)};
+ riscv::CSR_PMPADDR13: csr_rdata = {10'b0, pmpaddr_q[13][riscv::PLEN-3:1], (pmpcfg_q[13].addr_mode[1] == 1'b1 ? 1'b1 : 1'b0)};
+ riscv::CSR_PMPADDR14: csr_rdata = {10'b0, pmpaddr_q[14][riscv::PLEN-3:1], (pmpcfg_q[14].addr_mode[1] == 1'b1 ? 1'b1 : 1'b0)};
+ riscv::CSR_PMPADDR15: csr_rdata = {10'b0, pmpaddr_q[15][riscv::PLEN-3:1], (pmpcfg_q[15].addr_mode[1] == 1'b1 ? 1'b1 : 1'b0)};
default: read_access_exception = 1'b1;
endcase
end
@@ -595,7 +595,7 @@ module csr_regfile import ariane_pkg::*; #(
// 1. refuse to update any locked entry
// 2. also refuse to update the entry below a locked TOR entry
// Note that writes to pmpcfg below a locked TOR entry are valid
- riscv::CSR_PMPCFG0: for (int i = 0; i < 8; i++) if (!pmpcfg_q[i].locked) pmpcfg_d[i] = csr_wdata[i*8+:8];
+ /*riscv::CSR_PMPCFG0: for (int i = 0; i < 8; i++) if (!pmpcfg_q[i].locked) pmpcfg_d[i] = csr_wdata[i*8+:8];
riscv::CSR_PMPCFG2: for (int i = 0; i < 8; i++) if (!pmpcfg_q[i+8].locked) pmpcfg_d[i+8] = csr_wdata[i*8+:8];
riscv::CSR_PMPADDR0: if (!pmpcfg_q[ 0].locked && !(pmpcfg_q[ 1].locked && pmpcfg_q[ 1].addr_mode == riscv::TOR)) pmpaddr_d[0] = csr_wdata[riscv::VLEN-3:0];
riscv::CSR_PMPADDR1: if (!pmpcfg_q[ 1].locked && !(pmpcfg_q[ 2].locked && pmpcfg_q[ 2].addr_mode == riscv::TOR)) pmpaddr_d[1] = csr_wdata[riscv::VLEN-3:0];
@@ -612,7 +612,36 @@ module csr_regfile import ariane_pkg::*; #(
riscv::CSR_PMPADDR12: if (!pmpcfg_q[12].locked && !(pmpcfg_q[13].locked && pmpcfg_q[13].addr_mode == riscv::TOR)) pmpaddr_d[12] = csr_wdata[riscv::VLEN-3:0];
riscv::CSR_PMPADDR13: if (!pmpcfg_q[13].locked && !(pmpcfg_q[14].locked && pmpcfg_q[14].addr_mode == riscv::TOR)) pmpaddr_d[13] = csr_wdata[riscv::VLEN-3:0];
riscv::CSR_PMPADDR14: if (!pmpcfg_q[14].locked && !(pmpcfg_q[15].locked && pmpcfg_q[15].addr_mode == riscv::TOR)) pmpaddr_d[14] = csr_wdata[riscv::VLEN-3:0];
- riscv::CSR_PMPADDR15: if (!pmpcfg_q[15].locked) pmpaddr_d[15] = csr_wdata[riscv::VLEN-3:0];
+ riscv::CSR_PMPADDR15: if (!pmpcfg_q[15].locked) pmpaddr_d[15] = csr_wdata[riscv::VLEN-3:0];*/
+ riscv::CSR_PMPCFG0: for (int i = 0; i < (riscv::XLEN/8); i++) if (!pmpcfg_q[i].locked) pmpcfg_d[i] = csr_wdata[i*8+:8];
+ riscv::CSR_PMPCFG1: begin
+ if (riscv::XLEN == 32) begin
+ for (int i = 0; i < 4; i++) if (!pmpcfg_q[i+4].locked) pmpcfg_d[i+4] = csr_wdata[i*8+:8];
+ end
+ end
+ riscv::CSR_PMPCFG2: for (int i = 0; i < (riscv::XLEN/8); i++) if (!pmpcfg_q[i+8].locked) pmpcfg_d[i+8] = csr_wdata[i*8+:8];
+ riscv::CSR_PMPCFG3: begin
+ if (riscv::XLEN == 32) begin
+ for (int i = 0; i < 4; i++) if (!pmpcfg_q[i+12].locked) pmpcfg_d[i+12] = csr_wdata[i*8+:8];
+ end
+ end
+ riscv::CSR_PMPADDR0: if (!pmpcfg_q[ 0].locked && !(pmpcfg_q[ 1].locked && pmpcfg_q[ 1].addr_mode == riscv::TOR)) pmpaddr_d[0] = csr_wdata[riscv::PLEN-3:0];
+ riscv::CSR_PMPADDR1: if (!pmpcfg_q[ 1].locked && !(pmpcfg_q[ 2].locked && pmpcfg_q[ 2].addr_mode == riscv::TOR)) pmpaddr_d[1] = csr_wdata[riscv::PLEN-3:0];
+ riscv::CSR_PMPADDR2: if (!pmpcfg_q[ 2].locked && !(pmpcfg_q[ 3].locked && pmpcfg_q[ 3].addr_mode == riscv::TOR)) pmpaddr_d[2] = csr_wdata[riscv::PLEN-3:0];
+ riscv::CSR_PMPADDR3: if (!pmpcfg_q[ 3].locked && !(pmpcfg_q[ 4].locked && pmpcfg_q[ 4].addr_mode == riscv::TOR)) pmpaddr_d[3] = csr_wdata[riscv::PLEN-3:0];
+ riscv::CSR_PMPADDR4: if (!pmpcfg_q[ 4].locked && !(pmpcfg_q[ 5].locked && pmpcfg_q[ 5].addr_mode == riscv::TOR)) pmpaddr_d[4] = csr_wdata[riscv::PLEN-3:0];
+ riscv::CSR_PMPADDR5: if (!pmpcfg_q[ 5].locked && !(pmpcfg_q[ 6].locked && pmpcfg_q[ 6].addr_mode == riscv::TOR)) pmpaddr_d[5] = csr_wdata[riscv::PLEN-3:0];
+ riscv::CSR_PMPADDR6: if (!pmpcfg_q[ 6].locked && !(pmpcfg_q[ 7].locked && pmpcfg_q[ 7].addr_mode == riscv::TOR)) pmpaddr_d[6] = csr_wdata[riscv::PLEN-3:0];
+ riscv::CSR_PMPADDR7: if (!pmpcfg_q[ 7].locked && !(pmpcfg_q[ 8].locked && pmpcfg_q[ 8].addr_mode == riscv::TOR)) pmpaddr_d[7] = csr_wdata[riscv::PLEN-3:0];
+ riscv::CSR_PMPADDR8: if (!pmpcfg_q[ 8].locked && !(pmpcfg_q[ 9].locked && pmpcfg_q[ 9].addr_mode == riscv::TOR)) pmpaddr_d[8] = csr_wdata[riscv::PLEN-3:0];
+ riscv::CSR_PMPADDR9: if (!pmpcfg_q[ 9].locked && !(pmpcfg_q[10].locked && pmpcfg_q[10].addr_mode == riscv::TOR)) pmpaddr_d[9] = csr_wdata[riscv::PLEN-3:0];
+ riscv::CSR_PMPADDR10: if (!pmpcfg_q[10].locked && !(pmpcfg_q[11].locked && pmpcfg_q[11].addr_mode == riscv::TOR)) pmpaddr_d[10] = csr_wdata[riscv::PLEN-3:0];
+ riscv::CSR_PMPADDR11: if (!pmpcfg_q[11].locked && !(pmpcfg_q[12].locked && pmpcfg_q[12].addr_mode == riscv::TOR)) pmpaddr_d[11] = csr_wdata[riscv::PLEN-3:0];
+ riscv::CSR_PMPADDR12: if (!pmpcfg_q[12].locked && !(pmpcfg_q[13].locked && pmpcfg_q[13].addr_mode == riscv::TOR)) pmpaddr_d[12] = csr_wdata[riscv::PLEN-3:0];
+ riscv::CSR_PMPADDR13: if (!pmpcfg_q[13].locked && !(pmpcfg_q[14].locked && pmpcfg_q[14].addr_mode == riscv::TOR)) pmpaddr_d[13] = csr_wdata[riscv::PLEN-3:0];
+ riscv::CSR_PMPADDR14: if (!pmpcfg_q[14].locked && !(pmpcfg_q[15].locked && pmpcfg_q[15].addr_mode == riscv::TOR)) pmpaddr_d[14] = csr_wdata[riscv::PLEN-3:0];
+ riscv::CSR_PMPADDR15: if (!pmpcfg_q[15].locked) pmpaddr_d[15] = csr_wdata[riscv::PLEN-3:0];
+
default: update_access_exception = 1'b1;
endcase
end
diff --git a/src/frontend/frontend.sv b/src/frontend/frontend.sv
index 2713d85e..5bcf0e45 100644
--- a/src/frontend/frontend.sv
+++ b/src/frontend/frontend.sv
@@ -49,7 +49,7 @@ module frontend import ariane_pkg::*; #(
logic [FETCH_WIDTH-1:0] icache_data_q;
logic icache_valid_q;
ariane_pkg::frontend_exception_t icache_ex_valid_q;
- logic [63:0] icache_vaddr_q;
+ logic [riscv::VLEN-1:0] icache_vaddr_q;
logic instr_queue_ready;
logic [ariane_pkg::INSTR_PER_FETCH-1:0] instr_queue_consumed;
// upper-most branch-prediction from last cycle
diff --git a/src/issue_stage.sv b/src/issue_stage.sv
index b13c0d27..2258eb69 100644
--- a/src/issue_stage.sv
+++ b/src/issue_stage.sv
@@ -31,8 +31,8 @@ module issue_stage import ariane_pkg::*; #(
input logic is_ctrl_flow_i,
output logic decoded_instr_ack_o,
// to EX
- output [63:0] rs1_forwarding_o, // unregistered version of fu_data_o.operanda
- output [63:0] rs2_forwarding_o, // unregistered version of fu_data_o.operandb
+ output [riscv::VLEN-1:0] rs1_forwarding_o, // unregistered version of fu_data_o.operanda
+ output [riscv::VLEN-1:0] rs2_forwarding_o, // unregistered version of fu_data_o.operandb
output fu_data_t fu_data_o,
output logic [riscv::VLEN-1:0] pc_o,
output logic is_compressed_instr_o,
diff --git a/src/load_store_unit.sv b/src/load_store_unit.sv
index c4a24a7a..fe2a6859 100644
--- a/src/load_store_unit.sv
+++ b/src/load_store_unit.sv
@@ -55,7 +55,7 @@ module load_store_unit import ariane_pkg::*; #(
input logic [riscv::PPNW-1:0] satp_ppn_i, // From CSR register file
input logic [ASID_WIDTH-1:0] asid_i, // From CSR register file
input logic [ASID_WIDTH-1:0] asid_to_be_flushed_i,
- input logic [63:0] vaddr_to_be_flushed_i,
+ input logic [riscv::VLEN-1:0] vaddr_to_be_flushed_i,
input logic flush_tlb_i,
// Performance counters
output logic itlb_miss_o,
@@ -111,7 +111,7 @@ module load_store_unit import ariane_pkg::*; #(
logic [riscv::PLEN-1:0] mmu_paddr;
exception_t mmu_exception;
logic dtlb_hit;
- logic [riscv::PLEN-13:0] dtlb_ppn;
+ logic [riscv::PPNW-1:0] dtlb_ppn;
logic ld_valid;
logic [TRANS_ID_BITS-1:0] ld_trans_id;
@@ -127,37 +127,77 @@ module load_store_unit import ariane_pkg::*; #(
exception_t ld_ex;
exception_t st_ex;
+
// -------------------
// MMU e.g.: TLBs/PTW
// -------------------
- mmu #(
- .INSTR_TLB_ENTRIES ( 16 ),
- .DATA_TLB_ENTRIES ( 16 ),
- .ASID_WIDTH ( ASID_WIDTH ),
- .ArianeCfg ( ArianeCfg )
- ) i_mmu (
- // misaligned bypass
- .misaligned_ex_i ( misaligned_exception ),
- .lsu_is_store_i ( st_translation_req ),
- .lsu_req_i ( translation_req ),
- .lsu_vaddr_i ( mmu_vaddr ),
- .lsu_valid_o ( translation_valid ),
- .lsu_paddr_o ( mmu_paddr ),
- .lsu_exception_o ( mmu_exception ),
- .lsu_dtlb_hit_o ( dtlb_hit ), // send in the same cycle as the request
- .lsu_dtlb_ppn_o ( dtlb_ppn ), // send in the same cycle as the request
- // connecting PTW to D$ IF
- .req_port_i ( dcache_req_ports_i [0] ),
- .req_port_o ( dcache_req_ports_o [0] ),
- // icache address translation requests
- .icache_areq_i ( icache_areq_i ),
- .asid_to_be_flushed_i,
- .vaddr_to_be_flushed_i,
- .icache_areq_o ( icache_areq_o ),
- .pmpcfg_i,
- .pmpaddr_i,
- .*
- );
+ generate
+ if (MMU_PRESENT) begin : mmu_gen
+ mmu #(
+ .INSTR_TLB_ENTRIES ( 16 ),
+ .DATA_TLB_ENTRIES ( 16 ),
+ .ASID_WIDTH ( ASID_WIDTH ),
+ .ArianeCfg ( ArianeCfg )
+ ) i_mmu (
+ // misaligned bypass
+ .misaligned_ex_i ( misaligned_exception ),
+ .lsu_is_store_i ( st_translation_req ),
+ .lsu_req_i ( translation_req ),
+ .lsu_vaddr_i ( mmu_vaddr ),
+ .lsu_valid_o ( translation_valid ),
+ .lsu_paddr_o ( mmu_paddr ),
+ .lsu_exception_o ( mmu_exception ),
+ .lsu_dtlb_hit_o ( dtlb_hit ), // send in the same cycle as the request
+ .lsu_dtlb_ppn_o ( dtlb_ppn ), // send in the same cycle as the request
+ // connecting PTW to D$ IF
+ .req_port_i ( dcache_req_ports_i [0] ),
+ .req_port_o ( dcache_req_ports_o [0] ),
+ // icache address translation requests
+ .icache_areq_i ( icache_areq_i ),
+ .asid_to_be_flushed_i,
+ .vaddr_to_be_flushed_i,
+ .icache_areq_o ( icache_areq_o ),
+ .pmpcfg_i,
+ .pmpaddr_i,
+ .*
+ );
+ end else begin : no_mmu_gen
+ assign icache_areq_o.fetch_valid = icache_areq_i.fetch_req;
+ assign icache_areq_o.fetch_paddr = icache_areq_i.fetch_vaddr[riscv::PLEN-1:0];
+ assign icache_areq_o.fetch_exception = '0;
+
+ assign dcache_req_ports_o[0].address_index = '0;
+ assign dcache_req_ports_o[0].address_tag = '0;
+ assign dcache_req_ports_o[0].data_wdata = 64'b0;
+ assign dcache_req_ports_o[0].data_req = 1'b0;
+ assign dcache_req_ports_o[0].data_be = 8'hFF;
+ assign dcache_req_ports_o[0].data_size = 2'b11;
+ assign dcache_req_ports_o[0].data_we = 1'b0;
+ assign dcache_req_ports_o[0].kill_req = '0;
+ assign dcache_req_ports_o[0].tag_valid = 1'b0;
+
+ assign itlb_miss_o = 1'b0;
+ assign dtlb_miss_o = 1'b0;
+
+ assign dtlb_ppn = mmu_vaddr[riscv::PLEN-1:12];
+ assign dtlb_hit = 1'b1;
+
+ assign mmu_exception = '0;
+
+ always_ff @(posedge clk_i or negedge rst_ni) begin
+ if (~rst_ni) begin
+ mmu_paddr <= '0;
+ translation_valid <= '0;
+ end else begin
+ mmu_paddr <= mmu_vaddr[riscv::PLEN-1:0];
+ translation_valid <= translation_req;
+ end
+ end
+ end
+ endgenerate
+
+
+
logic store_buffer_empty;
// ------------------
// Store Unit
diff --git a/src/load_unit.sv b/src/load_unit.sv
index a572a0b9..c8a02869 100644
--- a/src/load_unit.sv
+++ b/src/load_unit.sv
@@ -34,7 +34,7 @@ module load_unit import ariane_pkg::*; #(
input logic [riscv::PLEN-1:0] paddr_i, // physical address in
input exception_t ex_i, // exception which may has happened earlier. for example: mis-aligned exception
input logic dtlb_hit_i, // hit on the dtlb, send in the same cycle as the request
- input logic [riscv::PLEN-13:0] dtlb_ppn_i, // ppn on the dtlb, send in the same cycle as the request
+ input logic [riscv::PPNW-1:0] dtlb_ppn_i, // ppn on the dtlb, send in the same cycle as the request
// address checker
output logic [11:0] page_offset_o,
input logic page_offset_matches_i,
diff --git a/src/mmu.sv b/src/mmu.sv
index 7f0af22e..b96cbc08 100644
--- a/src/mmu.sv
+++ b/src/mmu.sv
@@ -39,7 +39,7 @@ module mmu import ariane_pkg::*; #(
// if we need to walk the page table we can't grant in the same cycle
// Cycle 0
output logic lsu_dtlb_hit_o, // sent in the same cycle as the request if translation hits in the DTLB
- output logic [riscv::PLEN-13:0] lsu_dtlb_ppn_o, // ppn (send same cycle as hit)
+ output logic [riscv::PPNW-1:0] lsu_dtlb_ppn_o, // ppn (send same cycle as hit)
// Cycle 1
output logic lsu_valid_o, // translation is valid
output logic [riscv::PLEN-1:0] lsu_paddr_o, // translated address
diff --git a/src/tlb.sv b/src/tlb.sv
index df4331bc..5a0aeac5 100644
--- a/src/tlb.sv
+++ b/src/tlb.sv
@@ -114,7 +114,7 @@ module tlb import ariane_pkg::*; #(
vaddr_vpn0_match[i] = (vaddr_to_be_flushed_i[20:12] == tags_q[i].vpn0);
vaddr_vpn1_match[i] = (vaddr_to_be_flushed_i[29:21] == tags_q[i].vpn1);
- vaddr_vpn2_match[i] = (vaddr_to_be_flushed_i[38:30] == tags_q[i].vpn2);
+ vaddr_vpn2_match[i] = (vaddr_to_be_flushed_i[30+riscv::VPN2:30] == tags_q[i].vpn2);
if (flush_i) begin
// invalidate logic
diff --git a/sw/README.md b/sw/README.md
new file mode 100644
index 00000000..9771495d
--- /dev/null
+++ b/sw/README.md
@@ -0,0 +1,44 @@
+# Software stack
+A set of software applications is available in `app` directory.
+
+## Applications
+These applications are used to give an estimation of the computation performance of the CVA6 architecture.
+
+These software applications are compiled in baremetal using the **BSP (Board Support Package)** in the bsp directory.
+
+- **Coremark** : Complete benchmark for testing the computing power of a processor. It generates a score called Coremark.
+- **Dhrystone**: Benchmark for testing the computing power of a processor. That generates a score in DMIPS VAX.
+- **Spmv**: Double-precision sparse matrix-vector multiplication benchmark.
+- **Median**: Benchmark that performs a 1D three elements median filter.
+- **Qsort**: This benchmark uses quicksort to sort an array of integers.
+- **Rsort**: This benchmark uses quicksort to sort an array of integers.
+- **Tower**: Towers of Hanoi benchmark.
+- **Vvadd**: Vector-Vector add benchmark. This benchmark uses adds to vectors and writes the results to a third vector.
+- **Multiply**: Multiply filter benchmark. This tests the software multiply implementation.
+- **Pmp**: test of the PMP in CVA6.
+
+The Makefile in app directory allows the compilation of these applications. It consists of several targets .
+If you want to compile an application and generate an executable file, you need to go into app directory and run:
+```
+$ make ‘application’.riscv
+```
+That generates the `application.riscv` executable link file which can be run on CVA6.
+For instance with Coremark application:
+```
+$ make coremark.riscv
+```
+Another target may be useful to debug software applications on CVA6, it allows disassembling of the executable file, and it generates all the assembly code of the application. To do so, you have to run:
+```
+$ make ‘application’.D
+```
+For Coremark application:
+```
+$ make coremark.D
+```
+
+## BSP (Board Support Package)
+The **BSP** is a low-level software package that supports the hardware platform. The **BSP** is located into bsp directory and it consists of three directories:
+- **Config**: It contains the linker script and fpga_platform_config.h file which defines some constant relating to the FPGA platform.
+- **Drivers**: it contains all peripheral driver. For now, there is only the UART driver.
+- **Hal**: Hardware Abstract Layer contains the runtime system interrupt vectors, system calls.
+
diff --git a/sw/app/Makefile b/sw/app/Makefile
new file mode 100755
index 00000000..783482ba
--- /dev/null
+++ b/sw/app/Makefile
@@ -0,0 +1,148 @@
+# Copyright (c) 2020 Thales.
+#
+# Copyright and related rights are licensed under the Apache
+# License, Version 2.0 (the "License"); you may not use this file except in
+# compliance with the License. You may obtain a copy of the License at
+# https://www.apache.org/licenses/LICENSE-2.0. Unless required by applicable law
+# or agreed to in writing, software, hardware and materials distributed under
+# this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR
+# CONDITIONS OF ANY KIND, either express or implied. See the License for the
+# specific language governing permissions and limitations under the License.
+#
+# Author: Sebastien Jacq - sjthales on github.com
+# Kevin Eyssartier - EyssartK on github.com
+#
+# Additional contributions by:
+#
+#
+# script Name: Software application makefile
+# Project Name: CVA6 softcore
+# Language: Makefile
+#
+# Description: Makefile to compile software application for CVA6 platform
+#
+# =========================================================================== #
+# Revisions :
+# Date Version Author Description
+# 2020-10-06 0.1 S.Jacq Created
+# 2020-10-06 0.1 k.Eyssartier Created
+# =========================================================================== #
+
+XLEN ?= 32
+
+default: all
+
+utils_dir= ../utils
+src_dir = $(abspath .)
+bsp_dir = ../bsp
+
+
+#--------------------------------------------------------------------
+# Sources
+#--------------------------------------------------------------------
+
+bmarks = \
+ coremark \
+ helloworld \
+ helloworld_printf \
+ median \
+ qsort \
+ rsort \
+ towers \
+ vvadd \
+ multiply \
+ dhrystone \
+ spmv \
+ pmp
+
+#--------------------------------------------------------------------
+# Build rules
+#--------------------------------------------------------------------
+
+RISCV_PREFIX ?= riscv$(XLEN)-unknown-elf-
+RISCV_GCC ?= $(RISCV_PREFIX)gcc
+RISCV_OBJCOPY ?= $(RISCV_PREFIX)objcopy
+RISCV_AR ?= $(RISCV_PREFIX)ar
+RISCV_OBJDUMP ?= $(RISCV_PREFIX)objdump
+
+
+SRC_BSP_C=$(wildcard $(bsp_dir)/hal/*.c) $(wildcard $(bsp_dir)/drivers/uart/*.c)
+SRC_BSP_S=$(wildcard $(bsp_dir)/hal/*.S)
+
+
+OBJ_BSP_C=$(SRC_BSP_C:.c=.o)
+OBJ_BSP_S=$(SRC_BSP_S:.S=.o)
+OBJ_BSP= $(OBJ_BSP_S) $(OBJ_BSP_C)
+
+
+OBJ_APP=$(wildcard $(src_dir)/*.o)
+
+INCS += -I$(src_dir)/../bsp/config \
+ -I$(src_dir)/../bsp/drivers/uart \
+ -I$(src_dir)/../bsp/hal \
+ -I$(src_dir)/coremark/simple \
+ -I$(src_dir)/common \
+ $(addprefix -I$(src_dir)/, $(bmarks))
+
+FLAGS_STR:="$(RISCV_CFLAGS) $(RISCV_LDFLAGS) "
+
+CFLAGS ?=-DPREALLOCATE=1 -fvisibility=hidden -DSTDIO_THRU_UART -O3 -mcmodel=medany -static -Wall -pedantic
+
+RISCV_CFLAGS :=-DPERFORMANCE_RUN=1 \
+ -DITERATIONS=3 \
+ -DFLAGS_STR=\"$(FLAGS_STR)\" \
+ -DPREALLOCATE=1 -fvisibility=hidden -DSTDIO_THRU_UART -O3 -mcmodel=medany -static -Wall -pedantic
+
+RISCV_LDFLAGS=-L./ -lcva6 -static -nostartfiles -T $(src_dir)/../bsp/config/link.ld
+
+
+
+incs += -I$(src_dir)/../env -I$(src_dir)/common $(addprefix -I$(src_dir)/, $(bmarks))
+objs :=
+
+
+define generate_rules =
+$(1)_SRC_DIR = ./$(1)/
+$(1)_SRC_FILES = $$(shell find $$($(1)_SRC_DIR) -name "*.c")
+$(1)_OBJ_FILES = $$($(1)_SRC_FILES:.c=.o)
+ALL_OBJ += $$($(1)_OBJ_FILES)
+$(1): $(1).D $(1).riscv
+$(1): $(1).hex $(1).riscv
+$(1): $(1).bin $(1).riscv
+$(1): $(1).mem $(1).bin
+$(1).riscv: libcva6.a $$($(1)_OBJ_FILES)
+ # LINKING
+ $$(RISCV_GCC) $$(RISCV_CFLAGS) -o $$@ $$^ $$(RISCV_LDFLAGS)
+endef
+
+$(foreach bmark,$(bmarks),$(eval $(call generate_rules,$(bmark))))
+
+%.D: %.riscv
+ $(RISCV_OBJDUMP) -D $< > $@
+
+%.hex: %.riscv
+ $(RISCV_OBJCOPY) -O ihex $< $@
+
+%.bin: %.riscv
+ $(RISCV_OBJCOPY) -O binary $< $@
+
+libcva6.a: $(OBJ_BSP)
+ $(RISCV_AR) rcs libcva6.a $(OBJ_BSP)
+
+%.o: %.c
+ $(RISCV_GCC) $(INCS) -o $@ -c $< $(RISCV_CFLAGS)
+
+%.o: %.S
+ $(RISCV_GCC) -o $@ -c $< $(CFLAGS)
+
+%.mem: %.bin
+ $(utils_dir)/bin2mem.py $(src_dir)/$<
+
+
+all: $(bmarks)
+
+
+clean:
+ rm -rf $(OBJ_BSP) $(ALL_OBJ) libcva6.a *.riscv *.o *.D *.mem *.bin
+
+
diff --git a/sw/app/common/util.h b/sw/app/common/util.h
new file mode 100644
index 00000000..081cfd63
--- /dev/null
+++ b/sw/app/common/util.h
@@ -0,0 +1,90 @@
+// See LICENSE for license details.
+
+#ifndef __UTIL_H
+#define __UTIL_H
+
+extern void setStats(int enable);
+
+#include <stdint.h>
+
+#define static_assert(cond) switch(0) { case 0: case !!(long)(cond): ; }
+
+static int verify(int n, const volatile int* test, const int* verify)
+{
+ int i;
+ // Unrolled for faster verification
+ for (i = 0; i < n/2*2; i+=2)
+ {
+ int t0 = test[i], t1 = test[i+1];
+ int v0 = verify[i], v1 = verify[i+1];
+ if (t0 != v0) return i+1;
+ if (t1 != v1) return i+2;
+ }
+ if (n % 2 != 0 && test[n-1] != verify[n-1])
+ return n;
+ return 0;
+}
+
+static int verifyDouble(int n, const volatile double* test, const double* verify)
+{
+ int i;
+ // Unrolled for faster verification
+ for (i = 0; i < n/2*2; i+=2)
+ {
+ double t0 = test[i], t1 = test[i+1];
+ double v0 = verify[i], v1 = verify[i+1];
+ int eq1 = t0 == v0, eq2 = t1 == v1;
+ if (!(eq1 & eq2)) return i+1+eq1;
+ }
+ if (n % 2 != 0 && test[n-1] != verify[n-1])
+ return n;
+ return 0;
+}
+
+static void __attribute__((noinline)) barrier(int ncores)
+{
+ static volatile int sense;
+ static volatile int count;
+ static __thread int threadsense;
+
+ __sync_synchronize();
+
+ threadsense = !threadsense;
+ if (__sync_fetch_and_add(&count, 1) == ncores-1)
+ {
+ count = 0;
+ sense = threadsense;
+ }
+ else while(sense != threadsense)
+ ;
+
+ __sync_synchronize();
+}
+
+static uint64_t lfsr(uint64_t x)
+{
+ uint64_t bit = (x ^ (x >> 1)) & 1;
+ return (x >> 1) | (bit << 62);
+}
+
+static uintptr_t insn_len(uintptr_t pc)
+{
+ return (*(unsigned short*)pc & 3) ? 4 : 2;
+}
+
+#ifdef __riscv
+#include "encoding.h"
+#endif
+
+#define stringify_1(s) #s
+#define stringify(s) stringify_1(s)
+#define stats(code, iter) do { \
+ unsigned long _c = -read_csr(mcycle), _i = -read_csr(minstret); \
+ code; \
+ _c += read_csr(mcycle), _i += read_csr(minstret); \
+ if (cid == 0) \
+ printf("\n%s: %ld cycles, %ld.%ld cycles/iter, %ld.%ld CPI\n", \
+ stringify(code), _c, _c/iter, 10*_c/iter%10, _c/_i, 10*_c/_i%10); \
+ } while(0)
+
+#endif //__UTIL_H
diff --git a/sw/app/dhrystone/dhrystone.c b/sw/app/dhrystone/dhrystone.c
new file mode 100644
index 00000000..9528ef93
--- /dev/null
+++ b/sw/app/dhrystone/dhrystone.c
@@ -0,0 +1,186 @@
+// See LICENSE for license details.
+
+#pragma GCC optimize ("no-inline")
+
+#include "dhrystone.h"
+
+#ifndef REG
+#define REG
+ /* REG becomes defined as empty */
+ /* i.e. no register variables */
+#else
+#undef REG
+#define REG register
+#endif
+
+extern int Int_Glob;
+extern char Ch_1_Glob;
+
+
+Proc_6 (Enum_Val_Par, Enum_Ref_Par)
+/*********************************/
+ /* executed once */
+ /* Enum_Val_Par == Ident_3, Enum_Ref_Par becomes Ident_2 */
+
+Enumeration Enum_Val_Par;
+Enumeration *Enum_Ref_Par;
+{
+ *Enum_Ref_Par = Enum_Val_Par;
+ if (! Func_3 (Enum_Val_Par))
+ /* then, not executed */
+ *Enum_Ref_Par = Ident_4;
+ switch (Enum_Val_Par)
+ {
+ case Ident_1:
+ *Enum_Ref_Par = Ident_1;
+ break;
+ case Ident_2:
+ if (Int_Glob > 100)
+ /* then */
+ *Enum_Ref_Par = Ident_1;
+ else *Enum_Ref_Par = Ident_4;
+ break;
+ case Ident_3: /* executed */
+ *Enum_Ref_Par = Ident_2;
+ break;
+ case Ident_4: break;
+ case Ident_5:
+ *Enum_Ref_Par = Ident_3;
+ break;
+ } /* switch */
+} /* Proc_6 */
+
+
+Proc_7 (Int_1_Par_Val, Int_2_Par_Val, Int_Par_Ref)
+/**********************************************/
+ /* executed three times */
+ /* first call: Int_1_Par_Val == 2, Int_2_Par_Val == 3, */
+ /* Int_Par_Ref becomes 7 */
+ /* second call: Int_1_Par_Val == 10, Int_2_Par_Val == 5, */
+ /* Int_Par_Ref becomes 17 */
+ /* third call: Int_1_Par_Val == 6, Int_2_Par_Val == 10, */
+ /* Int_Par_Ref becomes 18 */
+One_Fifty Int_1_Par_Val;
+One_Fifty Int_2_Par_Val;
+One_Fifty *Int_Par_Ref;
+{
+ One_Fifty Int_Loc;
+
+ Int_Loc = Int_1_Par_Val + 2;
+ *Int_Par_Ref = Int_2_Par_Val + Int_Loc;
+} /* Proc_7 */
+
+
+Proc_8 (Arr_1_Par_Ref, Arr_2_Par_Ref, Int_1_Par_Val, Int_2_Par_Val)
+/*********************************************************************/
+ /* executed once */
+ /* Int_Par_Val_1 == 3 */
+ /* Int_Par_Val_2 == 7 */
+Arr_1_Dim Arr_1_Par_Ref;
+Arr_2_Dim Arr_2_Par_Ref;
+int Int_1_Par_Val;
+int Int_2_Par_Val;
+{
+ REG One_Fifty Int_Index;
+ REG One_Fifty Int_Loc;
+
+ Int_Loc = Int_1_Par_Val + 5;
+ Arr_1_Par_Ref [Int_Loc] = Int_2_Par_Val;
+ Arr_1_Par_Ref [Int_Loc+1] = Arr_1_Par_Ref [Int_Loc];
+ Arr_1_Par_Ref [Int_Loc+30] = Int_Loc;
+ for (Int_Index = Int_Loc; Int_Index <= Int_Loc+1; ++Int_Index)
+ Arr_2_Par_Ref [Int_Loc] [Int_Index] = Int_Loc;
+ Arr_2_Par_Ref [Int_Loc] [Int_Loc-1] += 1;
+ Arr_2_Par_Ref [Int_Loc+20] [Int_Loc] = Arr_1_Par_Ref [Int_Loc];
+ Int_Glob = 5;
+} /* Proc_8 */
+
+
+Enumeration Func_1 (Ch_1_Par_Val, Ch_2_Par_Val)
+/*************************************************/
+ /* executed three times */
+ /* first call: Ch_1_Par_Val == 'H', Ch_2_Par_Val == 'R' */
+ /* second call: Ch_1_Par_Val == 'A', Ch_2_Par_Val == 'C' */
+ /* third call: Ch_1_Par_Val == 'B', Ch_2_Par_Val == 'C' */
+
+Capital_Letter Ch_1_Par_Val;
+Capital_Letter Ch_2_Par_Val;
+{
+ Capital_Letter Ch_1_Loc;
+ Capital_Letter Ch_2_Loc;
+
+ Ch_1_Loc = Ch_1_Par_Val;
+ Ch_2_Loc = Ch_1_Loc;
+ if (Ch_2_Loc != Ch_2_Par_Val)
+ /* then, executed */
+ return (Ident_1);
+ else /* not executed */
+ {
+ Ch_1_Glob = Ch_1_Loc;
+ return (Ident_2);
+ }
+} /* Func_1 */
+
+
+Boolean Func_2 (Str_1_Par_Ref, Str_2_Par_Ref)
+/*************************************************/
+ /* executed once */
+ /* Str_1_Par_Ref == "DHRYSTONE PROGRAM, 1'ST STRING" */
+ /* Str_2_Par_Ref == "DHRYSTONE PROGRAM, 2'ND STRING" */
+
+Str_30 Str_1_Par_Ref;
+Str_30 Str_2_Par_Ref;
+{
+ REG One_Thirty Int_Loc;
+ Capital_Letter Ch_Loc;
+
+ Int_Loc = 2;
+ while (Int_Loc <= 2) /* loop body executed once */
+ if (Func_1 (Str_1_Par_Ref[Int_Loc],
+ Str_2_Par_Ref[Int_Loc+1]) == Ident_1)
+ /* then, executed */
+ {
+ Ch_Loc = 'A';
+ Int_Loc += 1;
+ } /* if, while */
+ if (Ch_Loc >= 'W' && Ch_Loc < 'Z')
+ /* then, not executed */
+ Int_Loc = 7;
+ if (Ch_Loc == 'R')
+ /* then, not executed */
+ return (true);
+ else /* executed */
+ {
+ if (strcmp (Str_1_Par_Ref, Str_2_Par_Ref) > 0)
+ /* then, not executed */
+ {
+ Int_Loc += 7;
+ Int_Glob = Int_Loc;
+ return (true);
+ }
+ else /* executed */
+ return (false);
+ } /* if Ch_Loc */
+} /* Func_2 */
+
+
+Boolean Func_3 (Enum_Par_Val)
+/***************************/
+ /* executed once */
+ /* Enum_Par_Val == Ident_3 */
+Enumeration Enum_Par_Val;
+{
+ Enumeration Enum_Loc;
+
+ Enum_Loc = Enum_Par_Val;
+ if (Enum_Loc == Ident_3)
+ /* then, executed */
+ return (true);
+ else /* not executed */
+ return (false);
+} /* Func_3 */
+
+void debug_printf(const char* str, ...)
+{
+ //printf(str);
+}
diff --git a/sw/app/dhrystone/dhrystone.h b/sw/app/dhrystone/dhrystone.h
new file mode 100644
index 00000000..e350c177
--- /dev/null
+++ b/sw/app/dhrystone/dhrystone.h
@@ -0,0 +1,477 @@
+// See LICENSE for license details.
+
+#ifndef _DHRYSTONE_H
+#define _DHRYSTONE_H
+
+/****************** "DHRYSTONE" Benchmark Program ***************************/
+#define Version "C, Version 2.2"
+/* File: dhry_1.c (part 2 of 3)
+ * Author: Reinhold P. Weicker
+ * Siemens Nixdorf, Paderborn/Germany
+ * weicker@specbench.org
+ * Date: May 25, 1988
+ * Modified: Steven Pemberton, CWI, Amsterdam; Steven.Pemberton@cwi.nl
+ * Date: October, 1993; March 1995
+ * Included both files into one source, that gets compiled
+ * in two passes. Made program auto-compiling, and auto-running,
+ * and generally made it much easier to use.
+ *
+ * Original Version (in Ada) published in
+ * "Communications of the ACM" vol. 27., no. 10 (Oct. 1984),
+ * pp. 1013 - 1030, together with the statistics
+ * on which the distribution of statements etc. is based.
+ *
+ * In this C version, the following C library functions are used:
+ * - strcpy, strcmp (inside the measurement loop)
+ * - printf, scanf (outside the measurement loop)
+ * In addition, Berkeley UNIX system calls "times ()" or "time ()"
+ * are used for execution time measurement. For measurements
+ * on other systems, these calls have to be changed.
+ *
+ * Collection of Results:
+ * Reinhold Weicker (address see above) and
+ *
+ * Rick Richardson
+ * PC Research. Inc.
+ * 94 Apple Orchard Drive
+ * Tinton Falls, NJ 07724
+ * Phone: (201) 389-8963 (9-17 EST)
+ * Usenet: ...!uunet!pcrat!rick
+ *
+ * Please send results to Rick Richardson and/or Reinhold Weicker.
+ * Complete information should be given on hardware and software used.
+ * Hardware information includes: Machine type, CPU, type and size
+ * of caches; for microprocessors: clock frequency, memory speed
+ * (number of wait states).
+ * Software information includes: Compiler (and runtime library)
+ * manufacturer and version, compilation switches, OS version.
+ * The Operating System version may give an indication about the compiler;
+ * Dhrystone itself performs no OS calls in the measurement loop.
+ *
+ * The complete output generated by the program should be mailed
+ * such that at least some checks for correctness can be made.
+ *
+ ***************************************************************************
+ *
+ * Defines: The following "Defines" are possible:
+ * -DREG (default: Not defined)
+ * As an approximation to what an average C programmer
+ * might do, causes the "register" storage class to be applied
+ * - for local variables, if they are used (dynamically)
+ * five or more times
+ * - for parameters if they are used (dynamically)
+ * six or more times
+ * Note that an optimal "register" strategy is
+ * compiler-dependent, and that "register" declarations
+ * do not necessarily lead to faster execution.
+ * -DNOSTRUCTASSIGN (default: Not defined)
+ * Define if the C compiler does not support
+ * assignment of structures.
+ * -DNOENUMS (default: Not defined)
+ * Define if the C compiler does not support
+ * enumeration types.
+ * -DTIMES (default)
+ * -DTIME
+ * The "times" function of UNIX (returning process times)
+ * or the "time" function (returning wallclock time)
+ * is used for measurement.
+ * For single user machines, "time ()" is adequate. For
+ * multi-user machines where you cannot get single-user
+ * access, use the "times ()" function. If you have
+ * neither, use a stopwatch in the dead of night.
+ * "printf"s are provided marking the points "Start Timer"
+ * and "Stop Timer". DO NOT use the UNIX "time(1)"
+ * command, as this will measure the total time to
+ * run this program, which will (erroneously) include
+ * the time to allocate storage (malloc) and to perform
+ * the initialization.
+ * -DHZ=nnn
+ * In Berkeley UNIX, the function "times" returns process
+ * time in 1/HZ seconds, with HZ = 60 for most systems.
+ * CHECK YOUR SYSTEM DESCRIPTION BEFORE YOU JUST APPLY
+ * A VALUE.
+ *
+ ***************************************************************************
+ *
+ * History: Version C/2.1 was made for two reasons:
+ *
+ * 1) There was an obvious need for a common C version of
+ * Dhrystone, since C is at present the most popular system
+ * programming language for the class of processors
+ * (microcomputers, minicomputers) where Dhrystone is used most.
+ * There should be, as far as possible, only one C version of
+ * Dhrystone such that results can be compared without
+ * restrictions. In the past, the C versions distributed
+ * by Rick Richardson (Version 1.1) and by Reinhold Weicker
+ * had small (though not significant) differences.
+ *
+ * 2) As far as it is possible without changes to the Dhrystone
+ * statistics, optimizing compilers should be prevented from
+ * removing significant statements.
+ *
+ * This C version has been developed in cooperation with
+ * Rick Richardson (Tinton Falls, NJ), it incorporates many
+ * ideas from the "Version 1.1" distributed previously by
+ * him over the UNIX network Usenet.
+ * I also thank Chaim Benedelac (National Semiconductor),
+ * David Ditzel (SUN), Earl Killian and John Mashey (MIPS),
+ * Alan Smith and Rafael Saavedra-Barrera (UC at Berkeley)
+ * for their help with comments on earlier versions of the
+ * benchmark.
+ *
+ * Changes: In the initialization part, this version follows mostly
+ * Rick Richardson's version distributed via Usenet, not the
+ * version distributed earlier via floppy disk by Reinhold Weicker.
+ * As a concession to older compilers, names have been made
+ * unique within the first 8 characters.
+ * Inside the measurement loop, this version follows the
+ * version previously distributed by Reinhold Weicker.
+ *
+ * At several places in the benchmark, code has been added,
+ * but within the measurement loop only in branches that
+ * are not executed. The intention is that optimizing compilers
+ * should be prevented from moving code out of the measurement
+ * loop, or from removing code altogether. Since the statements
+ * that are executed within the measurement loop have NOT been
+ * changed, the numbers defining the "Dhrystone distribution"
+ * (distribution of statements, operand types and locality)
+ * still hold. Except for sophisticated optimizing compilers,
+ * execution times for this version should be the same as
+ * for previous versions.
+ *
+ * Since it has proven difficult to subtract the time for the
+ * measurement loop overhead in a correct way, the loop check
+ * has been made a part of the benchmark. This does have
+ * an impact - though a very minor one - on the distribution
+ * statistics which have been updated for this version.
+ *
+ * All changes within the measurement loop are described
+ * and discussed in the companion paper "Rationale for
+ * Dhrystone version 2".
+ *
+ * Because of the self-imposed limitation that the order and
+ * distribution of the executed statements should not be
+ * changed, there are still cases where optimizing compilers
+ * may not generate code for some statements. To a certain
+ * degree, this is unavoidable for small synthetic benchmarks.
+ * Users of the benchmark are advised to check code listings
+ * whether code is generated for all statements of Dhrystone.
+ *
+ * Version 2.1 is identical to version 2.0 distributed via
+ * the UNIX network Usenet in March 1988 except that it corrects
+ * some minor deficiencies that were found by users of version 2.0.
+ * The only change within the measurement loop is that a
+ * non-executed "else" part was added to the "if" statement in
+ * Func_3, and a non-executed "else" part removed from Proc_3.
+ *
+ * Version C/2.2, Steven Pemberton, October 1993
+ * Functionally, identical to version 2.2; the changes are in
+ * how you compile and use it:
+ * - Everything is in one file now, but compiled in 2 passes
+ * - Compile (and run) by running the file through the shell: 'sh dhry.c"
+ * - Uses the system definition of HZ if one can be found
+ * - HZ must be defined, otherwise it won't compile (no defaults here)
+ * - The (uninteresting) output is printed to stderr (dhry2 > /dev/null)
+ * - The number of loops is passed as a parameter, rather than read
+ * (dhry2 500000)
+ * - If the number of loops is insufficient to get a good result,
+ * it repeats it with loops*10 until it is enough (rather than just
+ * stopping)
+ * - Output says which sort of clock it is using, and the HZ value
+ * - You can use -DREG instead of the -DREG=register of previous versions
+ * - Some stylistic cleanups.
+ *
+ ***************************************************************************
+ *
+ * Compilation model and measurement (IMPORTANT):
+ *
+ * The following "ground rules" apply for measurements:
+ * - Separate compilation
+ * - No procedure merging
+ * - Otherwise, compiler optimizations are allowed but should be indicated
+ * - Default results are those without register declarations
+ * See the companion paper "Rationale for Dhrystone Version 2" for a more
+ * detailed discussion of these ground rules.
+ *
+ * For 16-Bit processors (e.g. 80186, 80286), times for all compilation
+ * models ("small", "medium", "large" etc.) should be given if possible,
+ * together with a definition of these models for the compiler system used.
+ *
+ **************************************************************************
+ *
+ * Dhrystone (C version) statistics:
+ *
+ * [Comment from the first distribution, updated for version 2.
+ * Note that because of language differences, the numbers are slightly
+ * different from the Ada version.]
+ *
+ * The following program contains statements of a high level programming
+ * language (here: C) in a distribution considered representative:
+ *
+ * assignments 52 (51.0 %)
+ * control statements 33 (32.4 %)
+ * procedure, function calls 17 (16.7 %)
+ *
+ * 103 statements are dynamically executed. The program is balanced with
+ * respect to the three aspects:
+ *
+ * - statement type
+ * - operand type
+ * - operand locality
+ * operand global, local, parameter, or constant.
+ *
+ * The combination of these three aspects is balanced only approximately.
+ *
+ * 1. Statement Type:
+ * ----------------- number
+ *
+ * V1 = V2 9
+ * (incl. V1 = F(..)
+ * V = Constant 12
+ * Assignment, 7
+ * with array element
+ * Assignment, 6
+ * with record component
+ * --
+ * 34 34
+ *
+ * X = Y +|-|"&&"|"|" Z 5
+ * X = Y +|-|"==" Constant 6
+ * X = X +|- 1 3
+ * X = Y *|/ Z 2
+ * X = Expression, 1
+ * two operators
+ * X = Expression, 1
+ * three operators
+ * --
+ * 18 18
+ *
+ * if .... 14
+ * with "else" 7
+ * without "else" 7
+ * executed 3
+ * not executed 4
+ * for ... 7 | counted every time
+ * while ... 4 | the loop condition
+ * do ... while 1 | is evaluated
+ * switch ... 1
+ * break 1
+ * declaration with 1
+ * initialization
+ * --
+ * 34 34
+ *
+ * P (...) procedure call 11
+ * user procedure 10
+ * library procedure 1
+ * X = F (...)
+ * function call 6
+ * user function 5
+ * library function 1
+ * --
+ * 17 17
+ * ---
+ * 103
+ *
+ * The average number of parameters in procedure or function calls
+ * is 1.82 (not counting the function values aX *
+ *
+ * 2. Operators
+ * ------------
+ * number approximate
+ * percentage
+ *
+ * Arithmetic 32 50.8
+ *
+ * + 21 33.3
+ * - 7 11.1
+ * * 3 4.8
+ * / (int div) 1 1.6
+ *
+ * Comparison 27 42.8
+ *
+ * == 9 14.3
+ * /= 4 6.3
+ * > 1 1.6
+ * < 3 4.8
+ * >= 1 1.6
+ * <= 9 14.3
+ *
+ * Logic 4 6.3
+ *
+ * && (AND-THEN) 1 1.6
+ * | (OR) 1 1.6
+ * ! (NOT) 2 3.2
+ *
+ * -- -----
+ * 63 100.1
+ *
+ *
+ * 3. Operand Type (counted once per operand reference):
+ * ---------------
+ * number approximate
+ * percentage
+ *
+ * Integer 175 72.3 %
+ * Character 45 18.6 %
+ * Pointer 12 5.0 %
+ * String30 6 2.5 %
+ * Array 2 0.8 %
+ * Record 2 0.8 %
+ * --- -------
+ * 242 100.0 %
+ *
+ * When there is an access path leading to the final operand (e.g. a record
+ * component), only the final data type on the access path is counted.
+ *
+ *
+ * 4. Operand Locality:
+ * -------------------
+ * number approximate
+ * percentage
+ *
+ * local variable 114 47.1 %
+ * global variable 22 9.1 %
+ * parameter 45 18.6 %
+ * value 23 9.5 %
+ * reference 22 9.1 %
+ * function result 6 2.5 %
+ * constant 55 22.7 %
+ * --- -------
+ * 242 100.0 %
+ *
+ * The program does not compute anything meaningful, but it is syntactically
+ * and semantically correct. All variables have a value assigned to them
+ * before they are used as a source operand.
+ *
+ * There has been no explicit effort to account for the effects of a
+ * cache, or to balance the use of long or short displacements for code or
+ * data.
+ *
+ ***************************************************************************
+ */
+
+/* Compiler and system dependent definitions: */
+
+/* variables for time measurement: */
+
+#ifdef TIME
+
+#define CLOCK_TYPE "time()"
+#undef HZ
+#define HZ (1) /* time() returns time in seconds */
+extern long time(); /* see library function "time" */
+#define Too_Small_Time 2 /* Measurements should last at least 2 seconds */
+#define Start_Timer() Begin_Time = time ( (long *) 0)
+#define Stop_Timer() End_Time = time ( (long *) 0)
+
+#else
+
+#ifdef MSC_CLOCK /* Use Microsoft C hi-res clock */
+
+#undef HZ
+#undef TIMES
+#include <time.h>
+#define HZ CLK_TCK
+#define CLOCK_TYPE "MSC clock()"
+extern clock_t clock();
+#define Too_Small_Time (2*HZ)
+#define Start_Timer() Begin_Time = clock()
+#define Stop_Timer() End_Time = clock()
+
+#elif defined(__riscv)
+
+#define HZ 1000000
+#define Too_Small_Time 1
+#define CLOCK_TYPE "rdcycle()"
+#define Start_Timer() Begin_Time = read_csr(mcycle)
+#define Stop_Timer() End_Time = read_csr(mcycle)
+
+#else
+ /* Use times(2) time function unless */
+ /* explicitly defined otherwise */
+#define CLOCK_TYPE "times()"
+#include <sys/types.h>
+#include <sys/times.h>
+#ifndef HZ /* Added by SP 900619 */
+#include <sys/param.h> /* If your system doesn't have this, use -DHZ=xxx */
+#else
+ *** You must define HZ!!! ***
+#endif /* HZ */
+#ifndef PASS2
+struct tms time_info;
+#endif
+/*extern int times ();*/
+ /* see library function "times" */
+#define Too_Small_Time (2*HZ)
+ /* Measurements should last at least about 2 seconds */
+#define Start_Timer() times(&time_info); Begin_Time=(long)time_info.tms_utime
+#define Stop_Timer() times(&time_info); End_Time = (long)time_info.tms_utime
+
+#endif /* MSC_CLOCK */
+#endif /* TIME */
+
+
+#define Mic_secs_Per_Second 1000000
+#define NUMBER_OF_RUNS 500 /* Default number of runs */
+
+#ifdef NOSTRUCTASSIGN
+#define structassign(d, s) memcpy(&(d), &(s), sizeof(d))
+#else
+#define structassign(d, s) d = s
+#endif
+
+#ifdef NOENUM
+#define Ident_1 0
+#define Ident_2 1
+#define Ident_3 2
+#define Ident_4 3
+#define Ident_5 4
+ typedef int Enumeration;
+#else
+ typedef enum {Ident_1, Ident_2, Ident_3, Ident_4, Ident_5}
+ Enumeration;
+#endif
+ /* for boolean and enumeration types in Ada, Pascal */
+
+/* General definitions: */
+
+#include <stdio.h>
+#include <string.h>
+ /* for strcpy, strcmp */
+
+#define Null 0
+ /* Value of a Null pointer */
+#define true 1
+#define false 0
+
+typedef int One_Thirty;
+typedef int One_Fifty;
+typedef char Capital_Letter;
+typedef int Boolean;
+typedef char Str_30 [31];
+typedef int Arr_1_Dim [50];
+typedef int Arr_2_Dim [50] [50];
+
+typedef struct record
+ {
+ struct record *Ptr_Comp;
+ Enumeration Discr;
+ union {
+ struct {
+ Enumeration Enum_Comp;
+ int Int_Comp;
+ char Str_Comp [31];
+ } var_1;
+ struct {
+ Enumeration E_Comp_2;
+ char Str_2_Comp [31];
+ } var_2;
+ struct {
+ char Ch_1_Comp;
+ char Ch_2_Comp;
+ } var_3;
+ } variant;
+ } Rec_Type, *Rec_Pointer;
+
+#endif
diff --git a/sw/app/dhrystone/dhrystone_main.c b/sw/app/dhrystone/dhrystone_main.c
new file mode 100644
index 00000000..cad9a794
--- /dev/null
+++ b/sw/app/dhrystone/dhrystone_main.c
@@ -0,0 +1,353 @@
+// See LICENSE for license details.
+
+//**************************************************************************
+// Dhrystone bencmark
+//--------------------------------------------------------------------------
+//
+// This is the classic Dhrystone synthetic integer benchmark.
+//
+
+#pragma GCC optimize ("no-inline")
+
+#include "dhrystone.h"
+
+void debug_printf(const char* str, ...);
+
+#include "util.h"
+
+#include <alloca.h>
+
+#define NUM_COUNTERS 2
+static uintptr_t counters[NUM_COUNTERS];
+static char* counter_names[NUM_COUNTERS];
+
+
+void setStats(int enable)
+{
+ int i = 0;
+#define READ_CTR(name) do { \
+ while (i >= NUM_COUNTERS) ; \
+ uintptr_t csr = read_csr(name); \
+ if (!enable) { csr -= counters[i]; counter_names[i] = #name; } \
+ counters[i++] = csr; \
+ } while (0)
+
+ READ_CTR(mcycle);
+ READ_CTR(minstret);
+
+#undef READ_CTR
+}
+
+/* Global Variables: */
+
+Rec_Pointer Ptr_Glob,
+ Next_Ptr_Glob;
+int Int_Glob;
+Boolean Bool_Glob;
+char Ch_1_Glob,
+ Ch_2_Glob;
+int Arr_1_Glob [50];
+int Arr_2_Glob [50] [50];
+
+Enumeration Func_1 ();
+ /* forward declaration necessary since Enumeration may not simply be int */
+
+#ifndef REG
+ Boolean Reg = false;
+#define REG
+ /* REG becomes defined as empty */
+ /* i.e. no register variables */
+#else
+ Boolean Reg = true;
+#undef REG
+#define REG register
+#endif
+
+Boolean Done;
+
+long Begin_Time,
+ End_Time,
+ User_Time;
+long Microseconds,
+ Dhrystones_Per_Second;
+
+/* end of variables for time measurement */
+
+
+int main (int argc, char** argv)
+/*****/
+ /* main program, corresponds to procedures */
+ /* Main and Proc_0 in the Ada version */
+{
+ One_Fifty Int_1_Loc;
+ REG One_Fifty Int_2_Loc;
+ One_Fifty Int_3_Loc;
+ REG char Ch_Index;
+ Enumeration Enum_Loc;
+ Str_30 Str_1_Loc;
+ Str_30 Str_2_Loc;
+ REG int Run_Index;
+ REG int Number_Of_Runs;
+
+ /* Arguments */
+ Number_Of_Runs = NUMBER_OF_RUNS;
+
+ /* Initializations */
+
+ Next_Ptr_Glob = (Rec_Pointer) alloca (sizeof (Rec_Type));
+ Ptr_Glob = (Rec_Pointer) alloca (sizeof (Rec_Type));
+
+ Ptr_Glob->Ptr_Comp = Next_Ptr_Glob;
+ Ptr_Glob->Discr = Ident_1;
+ Ptr_Glob->variant.var_1.Enum_Comp = Ident_3;
+ Ptr_Glob->variant.var_1.Int_Comp = 40;
+ strcpy (Ptr_Glob->variant.var_1.Str_Comp,
+ "DHRYSTONE PROGRAM, SOME STRING");
+ strcpy (Str_1_Loc, "DHRYSTONE PROGRAM, 1'ST STRING");
+
+ Arr_2_Glob [8][7] = 10;
+ /* Was missing in published program. Without this statement, */
+ /* Arr_2_Glob [8][7] would have an undefined value. */
+ /* Warning: With 16-Bit processors and Number_Of_Runs > 32000, */
+ /* overflow may occur for this array element. */
+
+ debug_printf("\n");
+ debug_printf("Dhrystone Benchmark, Version %s\n", Version);
+ if (Reg)
+ {
+ debug_printf("Program compiled with 'register' attribute\n");
+ }
+ else
+ {
+ debug_printf("Program compiled without 'register' attribute\n");
+ }
+ debug_printf("Using %s, HZ=%d\n", CLOCK_TYPE, HZ);
+ debug_printf("\n");
+
+ Done = false;
+ while (!Done) {
+ debug_printf("Trying %d runs through Dhrystone:\n", Number_Of_Runs);
+
+ /***************/
+ /* Start timer */
+ /***************/
+
+ setStats(1);
+ Start_Timer();
+
+ for (Run_Index = 1; Run_Index <= Number_Of_Runs; ++Run_Index)
+ {
+
+ Proc_5();
+ Proc_4();
+ /* Ch_1_Glob == 'A', Ch_2_Glob == 'B', Bool_Glob == true */
+ Int_1_Loc = 2;
+ Int_2_Loc = 3;
+ strcpy (Str_2_Loc, "DHRYSTONE PROGRAM, 2'ND STRING");
+ Enum_Loc = Ident_2;
+ Bool_Glob = ! Func_2 (Str_1_Loc, Str_2_Loc);
+ /* Bool_Glob == 1 */
+ while (Int_1_Loc < Int_2_Loc) /* loop body executed once */
+ {
+ Int_3_Loc = 5 * Int_1_Loc - Int_2_Loc;
+ /* Int_3_Loc == 7 */
+ Proc_7 (Int_1_Loc, Int_2_Loc, &Int_3_Loc);
+ /* Int_3_Loc == 7 */
+ Int_1_Loc += 1;
+ } /* while */
+ /* Int_1_Loc == 3, Int_2_Loc == 3, Int_3_Loc == 7 */
+ Proc_8 (Arr_1_Glob, Arr_2_Glob, Int_1_Loc, Int_3_Loc);
+ /* Int_Glob == 5 */
+ Proc_1 (Ptr_Glob);
+ for (Ch_Index = 'A'; Ch_Index <= Ch_2_Glob; ++Ch_Index)
+ /* loop body executed twice */
+ {
+ if (Enum_Loc == Func_1 (Ch_Index, 'C'))
+ /* then, not executed */
+ {
+ Proc_6 (Ident_1, &Enum_Loc);
+ strcpy (Str_2_Loc, "DHRYSTONE PROGRAM, 3'RD STRING");
+ Int_2_Loc = Run_Index;
+ Int_Glob = Run_Index;
+ }
+ }
+ /* Int_1_Loc == 3, Int_2_Loc == 3, Int_3_Loc == 7 */
+ Int_2_Loc = Int_2_Loc * Int_1_Loc;
+ Int_1_Loc = Int_2_Loc / Int_3_Loc;
+ Int_2_Loc = 7 * (Int_2_Loc - Int_3_Loc) - Int_1_Loc;
+ /* Int_1_Loc == 1, Int_2_Loc == 13, Int_3_Loc == 7 */
+ Proc_2 (&Int_1_Loc);
+ /* Int_1_Loc == 5 */
+
+ } /* loop "for Run_Index" */
+
+ /**************/
+ /* Stop timer */
+ /**************/
+
+ Stop_Timer();
+ setStats(0);
+
+ User_Time = End_Time - Begin_Time;
+
+ if (User_Time < Too_Small_Time)
+ {
+ printf("Measured time too small to obtain meaningful results\n");
+ Number_Of_Runs = Number_Of_Runs * 10;
+ printf("\n");
+ } else Done = true;
+ }
+
+ debug_printf("Final values of the variables used in the benchmark:\n");
+ debug_printf("\n");
+ debug_printf("Int_Glob: %d\n", Int_Glob);
+ debug_printf(" should be: %d\n", 5);
+ debug_printf("Bool_Glob: %d\n", Bool_Glob);
+ debug_printf(" should be: %d\n", 1);
+ debug_printf("Ch_1_Glob: %c\n", Ch_1_Glob);
+ debug_printf(" should be: %c\n", 'A');
+ debug_printf("Ch_2_Glob: %c\n", Ch_2_Glob);
+ debug_printf(" should be: %c\n", 'B');
+ debug_printf("Arr_1_Glob[8]: %d\n", Arr_1_Glob[8]);
+ debug_printf(" should be: %d\n", 7);
+ debug_printf("Arr_2_Glob[8][7]: %d\n", Arr_2_Glob[8][7]);
+ debug_printf(" should be: Number_Of_Runs + 10\n");
+ debug_printf("Ptr_Glob->\n");
+ debug_printf(" Ptr_Comp: %d\n", (long) Ptr_Glob->Ptr_Comp);
+ debug_printf(" should be: (implementation-dependent)\n");
+ debug_printf(" Discr: %d\n", Ptr_Glob->Discr);
+ debug_printf(" should be: %d\n", 0);
+ debug_printf(" Enum_Comp: %d\n", Ptr_Glob->variant.var_1.Enum_Comp);
+ debug_printf(" should be: %d\n", 2);
+ debug_printf(" Int_Comp: %d\n", Ptr_Glob->variant.var_1.Int_Comp);
+ debug_printf(" should be: %d\n", 17);
+ debug_printf(" Str_Comp: %s\n", Ptr_Glob->variant.var_1.Str_Comp);
+ debug_printf(" should be: DHRYSTONE PROGRAM, SOME STRING\n");
+ debug_printf("Next_Ptr_Glob->\n");
+ debug_printf(" Ptr_Comp: %d\n", (long) Next_Ptr_Glob->Ptr_Comp);
+ debug_printf(" should be: (implementation-dependent), same as above\n");
+ debug_printf(" Discr: %d\n", Next_Ptr_Glob->Discr);
+ debug_printf(" should be: %d\n", 0);
+ debug_printf(" Enum_Comp: %d\n", Next_Ptr_Glob->variant.var_1.Enum_Comp);
+ debug_printf(" should be: %d\n", 1);
+ debug_printf(" Int_Comp: %d\n", Next_Ptr_Glob->variant.var_1.Int_Comp);
+ debug_printf(" should be: %d\n", 18);
+ debug_printf(" Str_Comp: %s\n",
+ Next_Ptr_Glob->variant.var_1.Str_Comp);
+ debug_printf(" should be: DHRYSTONE PROGRAM, SOME STRING\n");
+ debug_printf("Int_1_Loc: %d\n", Int_1_Loc);
+ debug_printf(" should be: %d\n", 5);
+ debug_printf("Int_2_Loc: %d\n", Int_2_Loc);
+ debug_printf(" should be: %d\n", 13);
+ debug_printf("Int_3_Loc: %d\n", Int_3_Loc);
+ debug_printf(" should be: %d\n", 7);
+ debug_printf("Enum_Loc: %d\n", Enum_Loc);
+ debug_printf(" should be: %d\n", 1);
+ debug_printf("Str_1_Loc: %s\n", Str_1_Loc);
+ debug_printf(" should be: DHRYSTONE PROGRAM, 1'ST STRING\n");
+ debug_printf("Str_2_Loc: %s\n", Str_2_Loc);
+ debug_printf(" should be: DHRYSTONE PROGRAM, 2'ND STRING\n");
+ debug_printf("\n");
+
+
+ Microseconds = ((User_Time / Number_Of_Runs) * Mic_secs_Per_Second) / HZ;
+ Dhrystones_Per_Second = (HZ * Number_Of_Runs) / User_Time;
+
+ printf("Microseconds for one run through Dhrystone: %ld\n", Microseconds);
+ printf("Dhrystones per Second: %ld\n", Dhrystones_Per_Second);
+
+ return 0;
+}
+
+
+Proc_1 (Ptr_Val_Par)
+/******************/
+
+REG Rec_Pointer Ptr_Val_Par;
+ /* executed once */
+{
+ REG Rec_Pointer Next_Record = Ptr_Val_Par->Ptr_Comp;
+ /* == Ptr_Glob_Next */
+ /* Local variable, initialized with Ptr_Val_Par->Ptr_Comp, */
+ /* corresponds to "rename" in Ada, "with" in Pascal */
+
+ structassign (*Ptr_Val_Par->Ptr_Comp, *Ptr_Glob);
+ Ptr_Val_Par->variant.var_1.Int_Comp = 5;
+ Next_Record->variant.var_1.Int_Comp
+ = Ptr_Val_Par->variant.var_1.Int_Comp;
+ Next_Record->Ptr_Comp = Ptr_Val_Par->Ptr_Comp;
+ Proc_3 (&Next_Record->Ptr_Comp);
+ /* Ptr_Val_Par->Ptr_Comp->Ptr_Comp
+ == Ptr_Glob->Ptr_Comp */
+ if (Next_Record->Discr == Ident_1)
+ /* then, executed */
+ {
+ Next_Record->variant.var_1.Int_Comp = 6;
+ Proc_6 (Ptr_Val_Par->variant.var_1.Enum_Comp,
+ &Next_Record->variant.var_1.Enum_Comp);
+ Next_Record->Ptr_Comp = Ptr_Glob->Ptr_Comp;
+ Proc_7 (Next_Record->variant.var_1.Int_Comp, 10,
+ &Next_Record->variant.var_1.Int_Comp);
+ }
+ else /* not executed */
+ structassign (*Ptr_Val_Par, *Ptr_Val_Par->Ptr_Comp);
+} /* Proc_1 */
+
+
+Proc_2 (Int_Par_Ref)
+/******************/
+ /* executed once */
+ /* *Int_Par_Ref == 1, becomes 4 */
+
+One_Fifty *Int_Par_Ref;
+{
+ One_Fifty Int_Loc;
+ Enumeration Enum_Loc;
+
+ Int_Loc = *Int_Par_Ref + 10;
+ do /* executed once */
+ if (Ch_1_Glob == 'A')
+ /* then, executed */
+ {
+ Int_Loc -= 1;
+ *Int_Par_Ref = Int_Loc - Int_Glob;
+ Enum_Loc = Ident_1;
+ } /* if */
+ while (Enum_Loc != Ident_1); /* true */
+} /* Proc_2 */
+
+
+Proc_3 (Ptr_Ref_Par)
+/******************/
+ /* executed once */
+ /* Ptr_Ref_Par becomes Ptr_Glob */
+
+Rec_Pointer *Ptr_Ref_Par;
+
+{
+ if (Ptr_Glob != Null)
+ /* then, executed */
+ *Ptr_Ref_Par = Ptr_Glob->Ptr_Comp;
+ Proc_7 (10, Int_Glob, &Ptr_Glob->variant.var_1.Int_Comp);
+} /* Proc_3 */
+
+
+Proc_4 () /* without parameters */
+/*******/
+ /* executed once */
+{
+ Boolean Bool_Loc;
+
+ Bool_Loc = Ch_1_Glob == 'A';
+ Bool_Glob = Bool_Loc | Bool_Glob;
+ Ch_2_Glob = 'B';
+} /* Proc_4 */
+
+
+Proc_5 () /* without parameters */
+/*******/
+ /* executed once */
+{
+ Ch_1_Glob = 'A';
+ Bool_Glob = false;
+} /* Proc_5 */
diff --git a/sw/app/helloworld/helloworld.c b/sw/app/helloworld/helloworld.c
new file mode 100644
index 00000000..10c68618
--- /dev/null
+++ b/sw/app/helloworld/helloworld.c
@@ -0,0 +1,16 @@
+#include <stdint.h>
+#include "uart.h"
+
+int main(void)
+ {
+ uint8_t message[12] = "Hello World";
+ UART_init(&g_uart_0,
+ UART_115200_BAUD,
+ UART_DATA_8_BITS | UART_NO_PARITY | UART_ONE_STOP_BIT);
+
+ UART_polled_tx_string(&g_uart_0, message);
+
+ while(UART_tx_complete(&g_uart_0)==0);
+
+ return(0);
+ }
diff --git a/sw/app/helloworld_printf/helloworld_printf.c b/sw/app/helloworld_printf/helloworld_printf.c
new file mode 100644
index 00000000..ea16af45
--- /dev/null
+++ b/sw/app/helloworld_printf/helloworld_printf.c
@@ -0,0 +1,17 @@
+#include <stdio.h>
+#include <stdlib.h>
+
+int main(void)
+{
+
+ printf("hello World!\n");
+
+ //wait end of uart frame
+ volatile int c, d;
+ for (c = 1; c <= 32767; c++)
+ for (d = 1; d <= 32767; d++)
+ {}
+
+ return(0);
+}
+
diff --git a/sw/app/median/dataset1.h b/sw/app/median/dataset1.h
new file mode 100644
index 00000000..b1e14912
--- /dev/null
+++ b/sw/app/median/dataset1.h
@@ -0,0 +1,53 @@
+// See LICENSE for license details.
+
+
+#define DATA_SIZE 400
+
+int input_data[DATA_SIZE] =
+{
+ 41, 454, 833, 335, 564, 1, 187, 989, 749, 365, 350, 572, 132, 64, 949, 153, 584, 216, 805, 140,
+ 621, 210, 6, 572, 931, 339, 890, 593, 392, 898, 694, 228, 961, 12, 110, 883, 116, 750, 296, 646,
+ 426, 500, 314, 436, 659, 701, 774, 812, 319, 981, 678, 150, 875, 696, 376, 564, 474, 272, 938, 258,
+ 539, 647, 569, 509, 203, 88, 280, 703, 759, 669, 606, 375, 511, 551, 657, 936, 195, 592, 81, 569,
+ 267, 952, 229, 800, 337, 584, 944, 643, 902, 368, 241, 489, 913, 328, 826, 313, 933, 592, 985, 388,
+ 195, 543, 960, 649, 566, 979, 350, 997, 649, 814, 657, 79, 181, 208, 111, 998, 859, 629, 65, 847,
+ 288, 704, 349, 997, 141, 253, 905, 715, 886, 430, 264, 415, 576, 538, 979, 700, 761, 4, 241, 494,
+ 478, 100, 499, 864, 403, 693, 222, 416, 444, 296, 721, 285, 676, 620, 317, 78, 224, 351, 937, 540,
+ 288, 646, 119, 169, 615, 527, 606, 289, 389, 796, 351, 801, 455, 720, 278, 758, 367, 745, 358, 92,
+ 584, 989, 62, 271, 985, 853, 403, 788, 346, 531, 517, 222, 559, 461, 908, 241, 775, 358, 255, 332,
+ 778, 684, 598, 740, 143, 446, 33, 311, 125, 743, 941, 557, 933, 479, 799, 557, 553, 925, 431, 796,
+ 648, 357, 952, 891, 287, 666, 19, 514, 49, 557, 86, 870, 95, 853, 441, 440, 587, 61, 614, 678,
+ 382, 396, 280, 9, 808, 17, 971, 170, 819, 291, 344, 380, 450, 536, 512, 185, 965, 917, 347, 539,
+ 808, 983, 882, 887, 537, 54, 946, 612, 701, 951, 356, 479, 567, 151, 891, 7, 22, 641, 568, 335,
+ 665, 730, 423, 95, 434, 728, 158, 280, 2, 395, 84, 688, 247, 911, 49, 476, 435, 815, 792, 729,
+ 869, 265, 486, 127, 414, 236, 369, 214, 548, 180, 518, 6, 888, 503, 682, 596, 284, 173, 264, 643,
+ 499, 346, 290, 599, 897, 68, 215, 849, 731, 658, 688, 619, 251, 121, 786, 131, 555, 828, 302, 667,
+ 528, 433, 544, 487, 322, 753, 947, 125, 287, 626, 824, 14, 304, 10, 788, 403, 733, 106, 959, 703,
+ 366, 818, 722, 964, 294, 406, 975, 874, 653, 856, 748, 86, 91, 60, 378, 660, 105, 667, 102, 153,
+ 381, 121, 651, 98, 825, 412, 840, 236, 356, 12, 148, 423, 54, 965, 140, 216, 955, 621, 343, 361
+};
+
+int verify_data[DATA_SIZE] =
+{
+ 0, 454, 454, 564, 335, 187, 187, 749, 749, 365, 365, 350, 132, 132, 153, 584, 216, 584, 216, 621,
+ 210, 210, 210, 572, 572, 890, 593, 593, 593, 694, 694, 694, 228, 110, 110, 116, 750, 296, 646, 426,
+ 500, 426, 436, 436, 659, 701, 774, 774, 812, 678, 678, 678, 696, 696, 564, 474, 474, 474, 272, 539,
+ 539, 569, 569, 509, 203, 203, 280, 703, 703, 669, 606, 511, 511, 551, 657, 657, 592, 195, 569, 267,
+ 569, 267, 800, 337, 584, 584, 643, 902, 643, 368, 368, 489, 489, 826, 328, 826, 592, 933, 592, 388,
+ 388, 543, 649, 649, 649, 566, 979, 649, 814, 657, 657, 181, 181, 181, 208, 859, 859, 629, 629, 288,
+ 704, 349, 704, 349, 253, 253, 715, 886, 715, 430, 415, 415, 538, 576, 700, 761, 700, 241, 241, 478,
+ 478, 478, 499, 499, 693, 403, 416, 416, 416, 444, 296, 676, 620, 620, 317, 224, 224, 351, 540, 540,
+ 540, 288, 169, 169, 527, 606, 527, 389, 389, 389, 796, 455, 720, 455, 720, 367, 745, 367, 358, 358,
+ 584, 584, 271, 271, 853, 853, 788, 403, 531, 517, 517, 517, 461, 559, 461, 775, 358, 358, 332, 332,
+ 684, 684, 684, 598, 446, 143, 311, 125, 311, 743, 743, 933, 557, 799, 557, 557, 557, 553, 796, 648,
+ 648, 648, 891, 891, 666, 287, 514, 49, 514, 86, 557, 95, 853, 441, 441, 441, 440, 587, 614, 614,
+ 396, 382, 280, 280, 17, 808, 170, 819, 291, 344, 344, 380, 450, 512, 512, 512, 917, 917, 539, 539,
+ 808, 882, 887, 882, 537, 537, 612, 701, 701, 701, 479, 479, 479, 567, 151, 22, 22, 568, 568, 568,
+ 665, 665, 423, 423, 434, 434, 280, 158, 280, 84, 395, 247, 688, 247, 476, 435, 476, 792, 792, 792,
+ 729, 486, 265, 414, 236, 369, 236, 369, 214, 518, 180, 518, 503, 682, 596, 596, 284, 264, 264, 499,
+ 499, 346, 346, 599, 599, 215, 215, 731, 731, 688, 658, 619, 251, 251, 131, 555, 555, 555, 667, 528,
+ 528, 528, 487, 487, 487, 753, 753, 287, 287, 626, 626, 304, 14, 304, 403, 733, 403, 733, 703, 703,
+ 703, 722, 818, 722, 406, 406, 874, 874, 856, 748, 748, 91, 86, 91, 378, 378, 660, 105, 153, 153,
+ 153, 381, 121, 651, 412, 825, 412, 356, 236, 148, 148, 148, 423, 140, 216, 216, 621, 621, 361, 0
+};
+
diff --git a/sw/app/median/median.c b/sw/app/median/median.c
new file mode 100644
index 00000000..1999185c
--- /dev/null
+++ b/sw/app/median/median.c
@@ -0,0 +1,42 @@
+// See LICENSE for license details.
+
+//**************************************************************************
+// Median filter (c version)
+//--------------------------------------------------------------------------
+
+void median( int n, int input[], int results[] )
+{
+ int A, B, C, i;
+
+ // Zero the ends
+ results[0] = 0;
+ results[n-1] = 0;
+
+ // Do the filter
+ for ( i = 1; i < (n-1); i++ ) {
+
+ A = input[i-1];
+ B = input[i];
+ C = input[i+1];
+
+ if ( A < B ) {
+ if ( B < C )
+ results[i] = B;
+ else if ( C < A )
+ results[i] = A;
+ else
+ results[i] = C;
+ }
+
+ else {
+ if ( A < C )
+ results[i] = A;
+ else if ( C < B )
+ results[i] = B;
+ else
+ results[i] = C;
+ }
+
+ }
+
+}
diff --git a/sw/app/median/median.h b/sw/app/median/median.h
new file mode 100644
index 00000000..7f9791cc
--- /dev/null
+++ b/sw/app/median/median.h
@@ -0,0 +1,11 @@
+// See LICENSE for license details.
+
+//**************************************************************************
+// Median filters
+//--------------------------------------------------------------------------
+
+// Simple C version
+void median( int n, int input[], int results[] );
+
+// Simple assembly version
+void median_asm( int n, int input[], int results[] );
diff --git a/sw/app/median/median_gendata.pl b/sw/app/median/median_gendata.pl
new file mode 100755
index 00000000..373904e9
--- /dev/null
+++ b/sw/app/median/median_gendata.pl
@@ -0,0 +1,140 @@
+#!/usr/bin/perl -w
+#==========================================================================
+# median_gendata.pl
+#
+# Author : Christopher Batten (cbatten@mit.edu)
+# Date : May 9, 2005
+#
+(our $usageMsg = <<'ENDMSG') =~ s/^\#//gm;
+#
+# Simple script which creates an input data set and the reference data
+# for the median benchmark.
+#
+ENDMSG
+
+use strict "vars";
+use warnings;
+no warnings("once");
+use Getopt::Long;
+
+#--------------------------------------------------------------------------
+# Command line processing
+#--------------------------------------------------------------------------
+
+our %opts;
+
+sub usage()
+{
+
+ print "\n";
+ print " Usage: median_gendata.pl [options] \n";
+ print "\n";
+ print " Options:\n";
+ print " --help print this message\n";
+ print " --size size of input data [750]\n";
+ print " --seed random seed [1]\n";
+ print "$usageMsg";
+
+ exit();
+}
+
+sub processCommandLine()
+{
+
+ $opts{"help"} = 0;
+ $opts{"size"} = 750;
+ $opts{"seed"} = 1;
+ Getopt::Long::GetOptions( \%opts, 'help|?', 'size:i', 'seed:i' ) or usage();
+ $opts{"help"} and usage();
+
+}
+
+#--------------------------------------------------------------------------
+# Helper Functions
+#--------------------------------------------------------------------------
+
+sub printArray
+{
+ my $arrayName = $_[0];
+ my $arrayRef = $_[1];
+
+ my $numCols = 20;
+ my $arrayLen = scalar(@{$arrayRef});
+
+ print "int ".$arrayName."[DATA_SIZE] = \n";
+ print "{\n";
+
+ if ( $arrayLen <= $numCols ) {
+ print " ";
+ for ( my $i = 0; $i < $arrayLen; $i++ ) {
+ print sprintf("%3d",$arrayRef->[$i]);
+ if ( $i != $arrayLen-1 ) {
+ print ", ";
+ }
+ }
+ print "\n";
+ }
+
+ else {
+ my $numRows = int($arrayLen/$numCols);
+ for ( my $j = 0; $j < $numRows; $j++ ) {
+ print " ";
+ for ( my $i = 0; $i < $numCols; $i++ ) {
+ my $index = $j*$numCols + $i;
+ print sprintf("%3d",$arrayRef->[$index]);
+ if ( $index != $arrayLen-1 ) {
+ print ", ";
+ }
+ }
+ print "\n";
+ }
+
+ if ( $arrayLen > ($numRows*$numCols) ) {
+ print " ";
+ for ( my $i = 0; $i < ($arrayLen-($numRows*$numCols)); $i++ ) {
+ my $index = $numCols*$numRows + $i;
+ print sprintf("%3d",$arrayRef->[$index]);
+ if ( $index != $arrayLen-1 ) {
+ print ", ";
+ }
+ }
+ print "\n";
+ }
+
+ }
+
+ print "};\n\n";
+}
+
+#--------------------------------------------------------------------------
+# Main
+#--------------------------------------------------------------------------
+
+sub main()
+{
+
+ processCommandLine();
+ srand($opts{"seed"});
+
+ my @values;
+ for ( my $i = 0; $i < $opts{"size"}; $i++ ) {
+ push( @values, int(rand(999)) );
+ }
+
+ my @median;
+ $median[0] = 0;
+ $median[$opts{"size"}-1] = 0;
+ for ( my $i = 1; $i < $opts{"size"}-1; $i++ ) {
+ my @tempList = ( $values[$i-1], $values[$i], $values[$i+1] );
+ my @sorted = sort { $a <=> $b } @tempList;
+ $median[$i] = $sorted[1];
+ }
+
+ print "\n\#define DATA_SIZE ".$opts{"size"}." \n\n";
+ printArray( "input_data", \@values );
+ printArray( "verify_data", \@median );
+
+}
+
+main();
+
diff --git a/sw/app/median/median_main.c b/sw/app/median/median_main.c
new file mode 100644
index 00000000..86da62a7
--- /dev/null
+++ b/sw/app/median/median_main.c
@@ -0,0 +1,65 @@
+// See LICENSE for license details.
+
+//**************************************************************************
+// Median filter bencmark
+//--------------------------------------------------------------------------
+//
+// This benchmark performs a 1D three element median filter. The
+// input data (and reference data) should be generated using the
+// median_gendata.pl perl script and dumped to a file named
+// dataset1.h.
+
+#include "util.h"
+
+#include "median.h"
+
+
+#define NUM_COUNTERS 2
+static uintptr_t counters[NUM_COUNTERS];
+static char* counter_names[NUM_COUNTERS];
+
+
+void setStats(int enable)
+{
+ int i = 0;
+#define READ_CTR(name) do { \
+ while (i >= NUM_COUNTERS) ; \
+ uintptr_t csr = read_csr(name); \
+ if (!enable) { csr -= counters[i]; counter_names[i] = #name; } \
+ counters[i++] = csr; \
+ } while (0)
+
+ READ_CTR(mcycle);
+ READ_CTR(minstret);
+
+#undef READ_CTR
+}
+
+
+//--------------------------------------------------------------------------
+// Input/Reference Data
+
+#include "dataset1.h"
+
+//--------------------------------------------------------------------------
+// Main
+
+
+
+int main( int argc, char* argv[] )
+{
+ int results_data[DATA_SIZE];
+
+#if PREALLOCATE
+ // If needed we preallocate everything in the caches
+ median( DATA_SIZE, input_data, results_data );
+#endif
+
+ // Do the filter
+ setStats(1);
+ median( DATA_SIZE, input_data, results_data );
+ setStats(0);
+
+ // Check the results
+ return verify( DATA_SIZE, results_data, verify_data );
+}
diff --git a/sw/app/mm/common.h b/sw/app/mm/common.h
new file mode 100644
index 00000000..01b9f3fe
--- /dev/null
+++ b/sw/app/mm/common.h
@@ -0,0 +1,36 @@
+// See LICENSE for license details.
+
+#ifndef _MM_H
+#define _MM_H
+
+#include <string.h>
+#include <stdint.h>
+#include <math.h>
+
+#ifdef SP
+typedef float t;
+#define fma fmaf
+#else
+typedef double t;
+#endif
+
+#define inline inline __attribute__((always_inline))
+
+#define alloca_aligned(s, a) ((void*)(((uintptr_t)alloca((s)+(a)-1)+(a)-1)&~((a)-1)))
+
+#include "rb.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+void mm(size_t m, size_t n, size_t p,
+ t* a, size_t lda, t* b, size_t ldb, t* c, size_t ldc);
+
+#ifdef __cplusplus
+}
+#endif
+
+//void rb(t* a, t* b, t* c, size_t lda, size_t ldb, size_t ldc);
+
+#endif
diff --git a/sw/app/mm/gen.scala b/sw/app/mm/gen.scala
new file mode 100644
index 00000000..982daa86
--- /dev/null
+++ b/sw/app/mm/gen.scala
@@ -0,0 +1,81 @@
+import scala.sys.process._
+object MMGen {
+ implicit def i2s(i: Int) = i.toString
+ def writeFile(name: String, contents: String) = {
+ val f = new java.io.FileWriter(name)
+ f.write(contents)
+ f.close
+ }
+
+ var indent = 0
+ def spacing = " " * indent
+ def assign(lhs: String, rhs: String) =
+ spacing + lhs + " = " + rhs + ";\n"
+ def init(t: String, n: String, v: String) =
+ assign(t+" "+n, v)
+ def open_block(s: String = "") = {
+ val result = (if (s != "") spacing + s else "") + spacing + "{\n"
+ indent = indent + 1
+ result
+ }
+ def close_block = {
+ indent = indent - 1
+ spacing + "}\n"
+ }
+
+ def ar(m: String, i: String) = m+"["+i+"]"
+ def r(a: String, b: String*) = (a :: b.toList).reduceLeft(_+"_"+_)
+
+ def rb(m: Int, n: Int, p: Int) = {
+ var s = open_block("static inline void kloop(size_t p, t* a0, size_t lda, t* b0, size_t ldb, t* c, size_t ldc)\n")
+
+ for (i <- 0 until m)
+ s += init("t*", r("c", i), "&"+ar("c", "ldc*"+i))
+ for (i <- 0 until m; j <- 0 until n)
+ s += init("t", r("c", i, j), ar(r("c", i), j))
+
+ def doit(m: Int, n: Int, p: Int) = {
+ for (i <- 0 until m)
+ s += init("t*", r("a", i), "&"+ar("a", "lda*"+i))
+ for (k <- 0 until p)
+ s += init("t*", r("b", k), "&"+ar("b", "ldb*"+k))
+ for (k <- 0 until p; i <- 0 until m; j <- 0 until n)
+ s += assign(r("c", i, j), "fma(" + ar(r("a", i), k) + ", " + ar(r("b", k), j) + ", " + r("c", i, j) + ")")
+ }
+
+ s += open_block("for (t *a = a0, *b = b0; a < a0 + p/RBK*RBK; a += RBK, b += RBK*ldb)\n")
+ doit(m, n, p)
+ s += close_block
+
+ s += open_block("for (t *a = a0 + p/RBK*RBK, *b = b0 + p/RBK*RBK*ldb; a < a0 + p; a++, b += ldb)\n")
+ doit(m, n, 1)
+ s += close_block
+
+ for (i <- 0 until m; j <- 0 until n)
+ s += assign(ar(r("c", i), j), r("c", i, j))
+ s += close_block
+
+ s
+ }
+ def gcd(a: Int, b: Int): Int = if (b == 0) a else gcd(b, a%b)
+ def lcm(a: Int, b: Int): Int = a*b/gcd(a, b)
+ def lcm(a: Seq[Int]): Int = {
+ if (a.tail.isEmpty) a.head
+ else lcm(a.head, lcm(a.tail))
+ }
+ def test1(m: Int, n: Int, p: Int, m1: Int, n1: Int, p1: Int) = {
+ val decl = "static const int RBM = "+m+", RBN = "+n+", RBK = "+p+";\n" +
+ "static const int CBM = "+m1+", CBN = "+n1+", CBK = "+p1+";\n"
+ writeFile("rb.h", decl + rb(m, n, p))
+ //"make"!!
+
+ "make run"!
+
+ ("cp a.out " + Seq("b", m, n, p, m1, n1, p1, "run").reduce(_+"."+_))!
+ }
+ def main(args: Array[String]): Unit = {
+ test1(4, 5, 6, 24, 25, 24)
+ //for (i <- 4 to 6; j <- 4 to 6; k <- 4 to 6)
+ // test1(i, j, k, if (i == 5) 35 else 36, if (j == 5) 35 else 36, if (k == 5) 35 else 36)
+ }
+}
diff --git a/sw/app/mm/mm.c b/sw/app/mm/mm.c
new file mode 100644
index 00000000..e5edd8af
--- /dev/null
+++ b/sw/app/mm/mm.c
@@ -0,0 +1,152 @@
+// See LICENSE for license details.
+
+#include "common.h"
+#include <assert.h>
+#include <math.h>
+#include <stdint.h>
+#include <alloca.h>
+
+#define MIN(a, b) ((a) < (b) ? (a) : (b))
+
+static void mm_naive(size_t m, size_t n, size_t p,
+ t* a, size_t lda, t* b, size_t ldb, t* c, size_t ldc)
+{
+ for (size_t i = 0; i < m; i++)
+ {
+ for (size_t j = 0; j < n; j++)
+ {
+ t s0 = c[i*ldc+j], s1 = 0, s2 = 0, s3 = 0;
+ for (size_t k = 0; k < p/4*4; k+=4)
+ {
+ s0 = fma(a[i*lda+k+0], b[(k+0)*ldb+j], s0);
+ s1 = fma(a[i*lda+k+1], b[(k+1)*ldb+j], s1);
+ s2 = fma(a[i*lda+k+2], b[(k+2)*ldb+j], s2);
+ s3 = fma(a[i*lda+k+3], b[(k+3)*ldb+j], s3);
+ }
+ for (size_t k = p/4*4; k < p; k++)
+ s0 = fma(a[i*lda+k], b[k*ldb+j], s0);
+ c[i*ldc+j] = (s0 + s1) + (s2 + s3);
+ }
+ }
+}
+
+static inline void mm_rb(size_t m, size_t n, size_t p,
+ t* a, size_t lda, t* b, size_t ldb, t* c, size_t ldc)
+{
+ size_t mb = m/RBM*RBM, nb = n/RBN*RBN;
+ for (size_t i = 0; i < mb; i += RBM)
+ {
+ for (size_t j = 0; j < nb; j += RBN)
+ kloop(p, a+i*lda, lda, b+j, ldb, c+i*ldc+j, ldc);
+ mm_naive(RBM, n - nb, p, a+i*lda, lda, b+nb, ldb, c+i*ldc+nb, ldc);
+ }
+ mm_naive(m - mb, n, p, a+mb*lda, lda, b, ldb, c+mb*ldc, ldc);
+}
+
+static inline void repack(t* a, size_t lda, const t* a0, size_t lda0, size_t m, size_t p)
+{
+ for (size_t i = 0; i < m; i++)
+ {
+ for (size_t j = 0; j < p/8*8; j+=8)
+ {
+ t t0 = a0[i*lda0+j+0];
+ t t1 = a0[i*lda0+j+1];
+ t t2 = a0[i*lda0+j+2];
+ t t3 = a0[i*lda0+j+3];
+ t t4 = a0[i*lda0+j+4];
+ t t5 = a0[i*lda0+j+5];
+ t t6 = a0[i*lda0+j+6];
+ t t7 = a0[i*lda0+j+7];
+ a[i*lda+j+0] = t0;
+ a[i*lda+j+1] = t1;
+ a[i*lda+j+2] = t2;
+ a[i*lda+j+3] = t3;
+ a[i*lda+j+4] = t4;
+ a[i*lda+j+5] = t5;
+ a[i*lda+j+6] = t6;
+ a[i*lda+j+7] = t7;
+ }
+ for (size_t j = p/8*8; j < p; j++)
+ a[i*lda+j] = a0[i*lda0+j];
+ }
+}
+
+static void mm_cb(size_t m, size_t n, size_t p,
+ t* a, size_t lda, t* b, size_t ldb, t* c, size_t ldc)
+{
+ size_t nmb = m/CBM, nnb = n/CBN, npb = p/CBK;
+ size_t mb = nmb*CBM, nb = nnb*CBN, pb = npb*CBK;
+ //t a1[mb*pb], b1[pb*nb], c1[mb*nb];
+ t* a1 = (t*)alloca_aligned(sizeof(t)*mb*pb, 8192);
+ t* b1 = (t*)alloca_aligned(sizeof(t)*pb*nb, 8192);
+ t* c1 = (t*)alloca_aligned(sizeof(t)*mb*nb, 8192);
+
+ for (size_t i = 0; i < mb; i += CBM)
+ for (size_t j = 0; j < pb; j += CBK)
+ repack(a1 + (npb*(i/CBM) + j/CBK)*(CBM*CBK), CBK, a + i*lda + j, lda, CBM, CBK);
+
+ for (size_t i = 0; i < pb; i += CBK)
+ for (size_t j = 0; j < nb; j += CBN)
+ repack(b1 + (nnb*(i/CBK) + j/CBN)*(CBK*CBN), CBN, b + i*ldb + j, ldb, CBK, CBN);
+
+ for (size_t i = 0; i < mb; i += CBM)
+ for (size_t j = 0; j < nb; j += CBN)
+ repack(c1 + (nnb*(i/CBM) + j/CBN)*(CBM*CBN), CBN, c + i*ldc + j, ldc, CBM, CBN);
+
+ for (size_t i = 0; i < mb; i += CBM)
+ {
+ for (size_t j = 0; j < nb; j += CBN)
+ {
+ for (size_t k = 0; k < pb; k += CBK)
+ {
+ mm_rb(CBM, CBN, CBK,
+ a1 + (npb*(i/CBM) + k/CBK)*(CBM*CBK), CBK,
+ b1 + (nnb*(k/CBK) + j/CBN)*(CBK*CBN), CBN,
+ c1 + (nnb*(i/CBM) + j/CBN)*(CBM*CBN), CBN);
+ }
+ if (pb < p)
+ {
+ mm_rb(CBM, CBN, p - pb,
+ a + i*lda + pb, lda,
+ b + pb*ldb + j, ldb,
+ c1 + (nnb*(i/CBM) + j/CBN)*(CBM*CBN), CBN);
+ }
+ }
+ if (nb < n)
+ {
+ for (size_t k = 0; k < p; k += CBK)
+ {
+ mm_rb(CBM, n - nb, MIN(p - k, CBK),
+ a + i*lda + k, lda,
+ b + k*ldb + nb, ldb,
+ c + i*ldc + nb, ldc);
+ }
+ }
+ }
+ if (mb < m)
+ {
+ for (size_t j = 0; j < n; j += CBN)
+ {
+ for (size_t k = 0; k < p; k += CBK)
+ {
+ mm_rb(m - mb, MIN(n - j, CBN), MIN(p - k, CBK),
+ a + mb*lda + k, lda,
+ b + k*ldb + j, ldb,
+ c + mb*ldc + j, ldc);
+ }
+ }
+ }
+
+ for (size_t i = 0; i < mb; i += CBM)
+ for (size_t j = 0; j < nb; j += CBN)
+ repack(c + i*ldc + j, ldc, c1 + (nnb*(i/CBM) + j/CBN)*(CBM*CBN), CBN, CBM, CBN);
+}
+
+void mm(size_t m, size_t n, size_t p,
+ t* a, size_t lda, t* b, size_t ldb, t* c, size_t ldc)
+{
+ if (__builtin_expect(m <= 2*CBM && n <= 2*CBN && p <= 2*CBK, 1))
+ mm_rb(m, n, p, a, lda, b, ldb, c, ldc);
+ else
+ mm_cb(m, n, p, a, lda, b, ldb, c, ldc);
+}
diff --git a/sw/app/mm/mm_main.c b/sw/app/mm/mm_main.c
new file mode 100644
index 00000000..133b5a2d
--- /dev/null
+++ b/sw/app/mm/mm_main.c
@@ -0,0 +1,72 @@
+// See LICENSE for license details.
+
+#include "common.h"
+#include <assert.h>
+#include <stdlib.h>
+#include <stdio.h>
+#include "util.h"
+
+#pragma GCC optimize ("unroll-loops")
+
+void thread_entry(int cid, int nc)
+{
+ const int R = 8;
+ int m, n, p;
+ uint64_t s = 0xdeadbeefU;
+
+ m = CBM;
+ n = CBN;
+ p = CBK;
+
+ t a[m*p];
+ t b[p*n];
+ t c[m*n];
+
+ for (size_t i = 0; i < m; i++)
+ for (size_t j = 0; j < p; j++)
+ a[i*p+j] = (t)(s = lfsr(s));
+ for (size_t i = 0; i < p; i++)
+ for (size_t j = 0; j < n; j++)
+ b[i*n+j] = (t)(s = lfsr(s));
+ memset(c, 0, m*n*sizeof(c[0]));
+
+ size_t instret, cycles;
+ for (int i = 0; i < R; i++)
+ {
+ instret = -read_csr(minstret);
+ cycles = -read_csr(mcycle);
+ mm(m, n, p, a, p, b, n, c, n);
+ instret += read_csr(minstret);
+ cycles += read_csr(mcycle);
+ }
+
+ asm volatile("fence");
+
+ printf("C%d: reg block %dx%dx%d, cache block %dx%dx%d\n",
+ cid, RBM, RBN, RBK, CBM, CBN, CBK);
+ printf("C%d: %d instructions\n", cid, (int)(instret));
+ printf("C%d: %d cycles\n", cid, (int)(cycles));
+ printf("C%d: %d flops\n", cid, 2*m*n*p);
+ printf("C%d: %d Mflops @ 1 GHz\n", cid, 2000*m*n*p/(cycles));
+
+#if 1
+ for (size_t i = 0; i < m; i++)
+ {
+ for (size_t j = 0; j < n; j++)
+ {
+ t s = 0;
+ for (size_t k = 0; k < p; k++)
+ s += a[i*p+k] * b[k*n+j];
+ s *= R;
+ if (fabs(c[i*n+j]-s) > fabs(1e-6*s))
+ {
+ printf("C%d: c[%lu][%lu] %f != %f\n", cid, i, j, c[i*n+j], s);
+ exit(1);
+ }
+ }
+ }
+#endif
+
+ barrier(nc);
+ exit(0);
+}
diff --git a/sw/app/mm/rb.h b/sw/app/mm/rb.h
new file mode 100644
index 00000000..421c9648
--- /dev/null
+++ b/sw/app/mm/rb.h
@@ -0,0 +1,210 @@
+static const int RBM = 4, RBN = 5, RBK = 6;
+static const int CBM = 24, CBN = 25, CBK = 24;
+static inline void kloop(size_t p, t* a0, size_t lda, t* b0, size_t ldb, t* c, size_t ldc)
+{
+ t* c_0 = &c[ldc*0];
+ t* c_1 = &c[ldc*1];
+ t* c_2 = &c[ldc*2];
+ t* c_3 = &c[ldc*3];
+ t c_0_0 = c_0[0];
+ t c_0_1 = c_0[1];
+ t c_0_2 = c_0[2];
+ t c_0_3 = c_0[3];
+ t c_0_4 = c_0[4];
+ t c_1_0 = c_1[0];
+ t c_1_1 = c_1[1];
+ t c_1_2 = c_1[2];
+ t c_1_3 = c_1[3];
+ t c_1_4 = c_1[4];
+ t c_2_0 = c_2[0];
+ t c_2_1 = c_2[1];
+ t c_2_2 = c_2[2];
+ t c_2_3 = c_2[3];
+ t c_2_4 = c_2[4];
+ t c_3_0 = c_3[0];
+ t c_3_1 = c_3[1];
+ t c_3_2 = c_3[2];
+ t c_3_3 = c_3[3];
+ t c_3_4 = c_3[4];
+ for (t *a = a0, *b = b0; a < a0 + p/RBK*RBK; a += RBK, b += RBK*ldb)
+ {
+ t* a_0 = &a[lda*0];
+ t* a_1 = &a[lda*1];
+ t* a_2 = &a[lda*2];
+ t* a_3 = &a[lda*3];
+ t* b_0 = &b[ldb*0];
+ t* b_1 = &b[ldb*1];
+ t* b_2 = &b[ldb*2];
+ t* b_3 = &b[ldb*3];
+ t* b_4 = &b[ldb*4];
+ t* b_5 = &b[ldb*5];
+ c_0_0 = fma(a_0[0], b_0[0], c_0_0);
+ c_0_1 = fma(a_0[0], b_0[1], c_0_1);
+ c_0_2 = fma(a_0[0], b_0[2], c_0_2);
+ c_0_3 = fma(a_0[0], b_0[3], c_0_3);
+ c_0_4 = fma(a_0[0], b_0[4], c_0_4);
+ c_1_0 = fma(a_1[0], b_0[0], c_1_0);
+ c_1_1 = fma(a_1[0], b_0[1], c_1_1);
+ c_1_2 = fma(a_1[0], b_0[2], c_1_2);
+ c_1_3 = fma(a_1[0], b_0[3], c_1_3);
+ c_1_4 = fma(a_1[0], b_0[4], c_1_4);
+ c_2_0 = fma(a_2[0], b_0[0], c_2_0);
+ c_2_1 = fma(a_2[0], b_0[1], c_2_1);
+ c_2_2 = fma(a_2[0], b_0[2], c_2_2);
+ c_2_3 = fma(a_2[0], b_0[3], c_2_3);
+ c_2_4 = fma(a_2[0], b_0[4], c_2_4);
+ c_3_0 = fma(a_3[0], b_0[0], c_3_0);
+ c_3_1 = fma(a_3[0], b_0[1], c_3_1);
+ c_3_2 = fma(a_3[0], b_0[2], c_3_2);
+ c_3_3 = fma(a_3[0], b_0[3], c_3_3);
+ c_3_4 = fma(a_3[0], b_0[4], c_3_4);
+ c_0_0 = fma(a_0[1], b_1[0], c_0_0);
+ c_0_1 = fma(a_0[1], b_1[1], c_0_1);
+ c_0_2 = fma(a_0[1], b_1[2], c_0_2);
+ c_0_3 = fma(a_0[1], b_1[3], c_0_3);
+ c_0_4 = fma(a_0[1], b_1[4], c_0_4);
+ c_1_0 = fma(a_1[1], b_1[0], c_1_0);
+ c_1_1 = fma(a_1[1], b_1[1], c_1_1);
+ c_1_2 = fma(a_1[1], b_1[2], c_1_2);
+ c_1_3 = fma(a_1[1], b_1[3], c_1_3);
+ c_1_4 = fma(a_1[1], b_1[4], c_1_4);
+ c_2_0 = fma(a_2[1], b_1[0], c_2_0);
+ c_2_1 = fma(a_2[1], b_1[1], c_2_1);
+ c_2_2 = fma(a_2[1], b_1[2], c_2_2);
+ c_2_3 = fma(a_2[1], b_1[3], c_2_3);
+ c_2_4 = fma(a_2[1], b_1[4], c_2_4);
+ c_3_0 = fma(a_3[1], b_1[0], c_3_0);
+ c_3_1 = fma(a_3[1], b_1[1], c_3_1);
+ c_3_2 = fma(a_3[1], b_1[2], c_3_2);
+ c_3_3 = fma(a_3[1], b_1[3], c_3_3);
+ c_3_4 = fma(a_3[1], b_1[4], c_3_4);
+ c_0_0 = fma(a_0[2], b_2[0], c_0_0);
+ c_0_1 = fma(a_0[2], b_2[1], c_0_1);
+ c_0_2 = fma(a_0[2], b_2[2], c_0_2);
+ c_0_3 = fma(a_0[2], b_2[3], c_0_3);
+ c_0_4 = fma(a_0[2], b_2[4], c_0_4);
+ c_1_0 = fma(a_1[2], b_2[0], c_1_0);
+ c_1_1 = fma(a_1[2], b_2[1], c_1_1);
+ c_1_2 = fma(a_1[2], b_2[2], c_1_2);
+ c_1_3 = fma(a_1[2], b_2[3], c_1_3);
+ c_1_4 = fma(a_1[2], b_2[4], c_1_4);
+ c_2_0 = fma(a_2[2], b_2[0], c_2_0);
+ c_2_1 = fma(a_2[2], b_2[1], c_2_1);
+ c_2_2 = fma(a_2[2], b_2[2], c_2_2);
+ c_2_3 = fma(a_2[2], b_2[3], c_2_3);
+ c_2_4 = fma(a_2[2], b_2[4], c_2_4);
+ c_3_0 = fma(a_3[2], b_2[0], c_3_0);
+ c_3_1 = fma(a_3[2], b_2[1], c_3_1);
+ c_3_2 = fma(a_3[2], b_2[2], c_3_2);
+ c_3_3 = fma(a_3[2], b_2[3], c_3_3);
+ c_3_4 = fma(a_3[2], b_2[4], c_3_4);
+ c_0_0 = fma(a_0[3], b_3[0], c_0_0);
+ c_0_1 = fma(a_0[3], b_3[1], c_0_1);
+ c_0_2 = fma(a_0[3], b_3[2], c_0_2);
+ c_0_3 = fma(a_0[3], b_3[3], c_0_3);
+ c_0_4 = fma(a_0[3], b_3[4], c_0_4);
+ c_1_0 = fma(a_1[3], b_3[0], c_1_0);
+ c_1_1 = fma(a_1[3], b_3[1], c_1_1);
+ c_1_2 = fma(a_1[3], b_3[2], c_1_2);
+ c_1_3 = fma(a_1[3], b_3[3], c_1_3);
+ c_1_4 = fma(a_1[3], b_3[4], c_1_4);
+ c_2_0 = fma(a_2[3], b_3[0], c_2_0);
+ c_2_1 = fma(a_2[3], b_3[1], c_2_1);
+ c_2_2 = fma(a_2[3], b_3[2], c_2_2);
+ c_2_3 = fma(a_2[3], b_3[3], c_2_3);
+ c_2_4 = fma(a_2[3], b_3[4], c_2_4);
+ c_3_0 = fma(a_3[3], b_3[0], c_3_0);
+ c_3_1 = fma(a_3[3], b_3[1], c_3_1);
+ c_3_2 = fma(a_3[3], b_3[2], c_3_2);
+ c_3_3 = fma(a_3[3], b_3[3], c_3_3);
+ c_3_4 = fma(a_3[3], b_3[4], c_3_4);
+ c_0_0 = fma(a_0[4], b_4[0], c_0_0);
+ c_0_1 = fma(a_0[4], b_4[1], c_0_1);
+ c_0_2 = fma(a_0[4], b_4[2], c_0_2);
+ c_0_3 = fma(a_0[4], b_4[3], c_0_3);
+ c_0_4 = fma(a_0[4], b_4[4], c_0_4);
+ c_1_0 = fma(a_1[4], b_4[0], c_1_0);
+ c_1_1 = fma(a_1[4], b_4[1], c_1_1);
+ c_1_2 = fma(a_1[4], b_4[2], c_1_2);
+ c_1_3 = fma(a_1[4], b_4[3], c_1_3);
+ c_1_4 = fma(a_1[4], b_4[4], c_1_4);
+ c_2_0 = fma(a_2[4], b_4[0], c_2_0);
+ c_2_1 = fma(a_2[4], b_4[1], c_2_1);
+ c_2_2 = fma(a_2[4], b_4[2], c_2_2);
+ c_2_3 = fma(a_2[4], b_4[3], c_2_3);
+ c_2_4 = fma(a_2[4], b_4[4], c_2_4);
+ c_3_0 = fma(a_3[4], b_4[0], c_3_0);
+ c_3_1 = fma(a_3[4], b_4[1], c_3_1);
+ c_3_2 = fma(a_3[4], b_4[2], c_3_2);
+ c_3_3 = fma(a_3[4], b_4[3], c_3_3);
+ c_3_4 = fma(a_3[4], b_4[4], c_3_4);
+ c_0_0 = fma(a_0[5], b_5[0], c_0_0);
+ c_0_1 = fma(a_0[5], b_5[1], c_0_1);
+ c_0_2 = fma(a_0[5], b_5[2], c_0_2);
+ c_0_3 = fma(a_0[5], b_5[3], c_0_3);
+ c_0_4 = fma(a_0[5], b_5[4], c_0_4);
+ c_1_0 = fma(a_1[5], b_5[0], c_1_0);
+ c_1_1 = fma(a_1[5], b_5[1], c_1_1);
+ c_1_2 = fma(a_1[5], b_5[2], c_1_2);
+ c_1_3 = fma(a_1[5], b_5[3], c_1_3);
+ c_1_4 = fma(a_1[5], b_5[4], c_1_4);
+ c_2_0 = fma(a_2[5], b_5[0], c_2_0);
+ c_2_1 = fma(a_2[5], b_5[1], c_2_1);
+ c_2_2 = fma(a_2[5], b_5[2], c_2_2);
+ c_2_3 = fma(a_2[5], b_5[3], c_2_3);
+ c_2_4 = fma(a_2[5], b_5[4], c_2_4);
+ c_3_0 = fma(a_3[5], b_5[0], c_3_0);
+ c_3_1 = fma(a_3[5], b_5[1], c_3_1);
+ c_3_2 = fma(a_3[5], b_5[2], c_3_2);
+ c_3_3 = fma(a_3[5], b_5[3], c_3_3);
+ c_3_4 = fma(a_3[5], b_5[4], c_3_4);
+ }
+ for (t *a = a0 + p/RBK*RBK, *b = b0 + p/RBK*RBK*ldb; a < a0 + p; a++, b += ldb)
+ {
+ t* a_0 = &a[lda*0];
+ t* a_1 = &a[lda*1];
+ t* a_2 = &a[lda*2];
+ t* a_3 = &a[lda*3];
+ t* b_0 = &b[ldb*0];
+ c_0_0 = fma(a_0[0], b_0[0], c_0_0);
+ c_0_1 = fma(a_0[0], b_0[1], c_0_1);
+ c_0_2 = fma(a_0[0], b_0[2], c_0_2);
+ c_0_3 = fma(a_0[0], b_0[3], c_0_3);
+ c_0_4 = fma(a_0[0], b_0[4], c_0_4);
+ c_1_0 = fma(a_1[0], b_0[0], c_1_0);
+ c_1_1 = fma(a_1[0], b_0[1], c_1_1);
+ c_1_2 = fma(a_1[0], b_0[2], c_1_2);
+ c_1_3 = fma(a_1[0], b_0[3], c_1_3);
+ c_1_4 = fma(a_1[0], b_0[4], c_1_4);
+ c_2_0 = fma(a_2[0], b_0[0], c_2_0);
+ c_2_1 = fma(a_2[0], b_0[1], c_2_1);
+ c_2_2 = fma(a_2[0], b_0[2], c_2_2);
+ c_2_3 = fma(a_2[0], b_0[3], c_2_3);
+ c_2_4 = fma(a_2[0], b_0[4], c_2_4);
+ c_3_0 = fma(a_3[0], b_0[0], c_3_0);
+ c_3_1 = fma(a_3[0], b_0[1], c_3_1);
+ c_3_2 = fma(a_3[0], b_0[2], c_3_2);
+ c_3_3 = fma(a_3[0], b_0[3], c_3_3);
+ c_3_4 = fma(a_3[0], b_0[4], c_3_4);
+ }
+ c_0[0] = c_0_0;
+ c_0[1] = c_0_1;
+ c_0[2] = c_0_2;
+ c_0[3] = c_0_3;
+ c_0[4] = c_0_4;
+ c_1[0] = c_1_0;
+ c_1[1] = c_1_1;
+ c_1[2] = c_1_2;
+ c_1[3] = c_1_3;
+ c_1[4] = c_1_4;
+ c_2[0] = c_2_0;
+ c_2[1] = c_2_1;
+ c_2[2] = c_2_2;
+ c_2[3] = c_2_3;
+ c_2[4] = c_2_4;
+ c_3[0] = c_3_0;
+ c_3[1] = c_3_1;
+ c_3[2] = c_3_2;
+ c_3[3] = c_3_3;
+ c_3[4] = c_3_4;
+}
diff --git a/sw/app/mt-matmul/dataset.h b/sw/app/mt-matmul/dataset.h
new file mode 100644
index 00000000..72fbc28b
--- /dev/null
+++ b/sw/app/mt-matmul/dataset.h
@@ -0,0 +1,63 @@
+// See LICENSE for license details.
+
+#ifndef __DATASET_H
+#define __DATASET_H
+#define ARRAY_SIZE 256
+
+
+#define DIM_SIZE 16
+
+
+typedef int data_t;static data_t input1_data[ARRAY_SIZE] =
+{
+ 0, 3, 2, 0, 3, 1, 0, 3, 2, 3, 2, 0, 3, 3, 1, 2, 3, 0, 0, 1,
+ 1, 1, 2, 3, 1, 2, 3, 1, 1, 3, 2, 2, 0, 1, 3, 2, 2, 2, 0, 0,
+ 1, 0, 1, 3, 3, 0, 3, 3, 3, 3, 0, 3, 2, 1, 2, 2, 0, 0, 3, 0,
+ 1, 1, 0, 3, 3, 1, 2, 3, 3, 0, 1, 2, 1, 0, 1, 2, 2, 1, 0, 3,
+ 1, 0, 2, 2, 1, 1, 1, 1, 1, 1, 2, 0, 3, 1, 1, 2, 2, 3, 3, 1,
+ 3, 2, 0, 0, 0, 3, 3, 3, 2, 1, 2, 3, 1, 0, 0, 0, 0, 1, 2, 2,
+ 1, 1, 3, 3, 3, 1, 1, 2, 3, 1, 3, 3, 2, 3, 2, 1, 2, 3, 0, 2,
+ 2, 1, 1, 0, 0, 0, 0, 0, 1, 3, 3, 1, 1, 1, 2, 2, 3, 2, 1, 1,
+ 1, 1, 3, 0, 2, 2, 1, 3, 2, 1, 2, 2, 1, 3, 1, 3, 1, 3, 2, 3,
+ 1, 2, 1, 3, 2, 2, 0, 1, 0, 0, 1, 2, 3, 3, 1, 0, 0, 0, 3, 1,
+ 2, 3, 2, 3, 2, 0, 0, 0, 0, 0, 3, 1, 3, 0, 0, 0, 3, 1, 1, 1,
+ 1, 2, 1, 2, 3, 2, 0, 0, 2, 2, 3, 0, 3, 0, 0, 3, 0, 3, 1, 3,
+ 3, 1, 1, 1, 2, 2, 1, 3, 0, 3, 3, 1, 0, 0, 3, 2
+};
+
+static data_t input2_data[ARRAY_SIZE] =
+{
+ 1, 1, 0, 3, 1, 2, 0, 0, 0, 0, 0, 2, 1, 2, 3, 0, 0, 3, 3, 2,
+ 2, 1, 2, 3, 3, 0, 2, 2, 1, 1, 2, 2, 0, 2, 2, 1, 2, 3, 2, 2,
+ 3, 3, 2, 2, 1, 1, 1, 1, 2, 1, 2, 2, 3, 3, 3, 0, 0, 3, 2, 3,
+ 2, 3, 1, 2, 1, 1, 2, 2, 0, 1, 0, 3, 2, 1, 1, 1, 2, 0, 1, 2,
+ 2, 0, 2, 1, 3, 3, 2, 3, 2, 0, 3, 1, 3, 3, 2, 0, 1, 0, 1, 1,
+ 2, 2, 1, 1, 2, 2, 1, 2, 3, 3, 1, 3, 2, 2, 2, 3, 3, 1, 0, 2,
+ 1, 0, 0, 0, 1, 1, 2, 0, 3, 2, 3, 3, 0, 2, 3, 1, 0, 0, 2, 1,
+ 2, 0, 2, 1, 1, 2, 3, 1, 3, 2, 1, 0, 0, 0, 0, 0, 2, 2, 0, 2,
+ 1, 2, 0, 3, 2, 2, 0, 0, 3, 2, 1, 1, 3, 0, 2, 0, 0, 1, 0, 2,
+ 3, 3, 1, 3, 3, 0, 0, 2, 2, 0, 0, 0, 1, 0, 0, 1, 3, 0, 2, 1,
+ 3, 2, 2, 1, 3, 2, 0, 1, 2, 2, 3, 2, 1, 1, 1, 1, 3, 0, 1, 3,
+ 2, 2, 3, 1, 1, 2, 0, 2, 1, 1, 2, 3, 1, 0, 1, 0, 1, 1, 0, 0,
+ 2, 0, 3, 0, 3, 0, 3, 2, 2, 3, 3, 2, 1, 0, 2, 2
+};
+
+static data_t verify_data[ARRAY_SIZE] =
+{
+ 36, 44, 57, 50, 54, 36, 38, 46, 55, 25, 38, 34, 51, 30, 40, 32, 37, 34, 38, 52,
+ 51, 40, 28, 32, 41, 22, 26, 35, 49, 35, 42, 23, 26, 26, 33, 36, 52, 40, 45, 49,
+ 50, 34, 41, 35, 44, 25, 23, 23, 31, 29, 39, 46, 50, 36, 31, 32, 42, 32, 34, 41,
+ 44, 33, 43, 30, 31, 28, 39, 46, 50, 40, 35, 37, 43, 35, 33, 43, 43, 29, 37, 29,
+ 27, 22, 30, 33, 43, 31, 32, 25, 36, 31, 31, 29, 40, 28, 26, 22, 29, 42, 48, 51,
+ 65, 52, 43, 54, 63, 34, 42, 44, 56, 33, 38, 32, 26, 22, 23, 38, 49, 32, 26, 30,
+ 43, 22, 24, 27, 45, 24, 26, 17, 35, 35, 47, 51, 59, 59, 43, 42, 43, 28, 37, 43,
+ 56, 48, 36, 32, 28, 19, 28, 34, 46, 34, 28, 34, 45, 20, 29, 28, 50, 32, 26, 21,
+ 37, 38, 51, 50, 55, 45, 38, 49, 56, 28, 38, 40, 50, 29, 44, 26, 32, 35, 50, 43,
+ 53, 44, 41, 41, 34, 24, 35, 34, 39, 33, 34, 29, 21, 33, 31, 45, 48, 42, 27, 29,
+ 40, 17, 21, 32, 45, 30, 29, 26, 26, 27, 38, 33, 29, 31, 32, 31, 35, 25, 29, 29,
+ 34, 15, 25, 23, 34, 28, 44, 45, 41, 41, 37, 45, 45, 17, 34, 44, 46, 30, 43, 29,
+ 31, 36, 37, 50, 54, 44, 28, 40, 38, 22, 27, 28, 45, 32, 36, 22
+};
+
+
+#endif //__DATASET_H
\ No newline at end of file
diff --git a/sw/app/mt-matmul/matmul.c b/sw/app/mt-matmul/matmul.c
new file mode 100644
index 00000000..6d7b9786
--- /dev/null
+++ b/sw/app/mt-matmul/matmul.c
@@ -0,0 +1,23 @@
+// See LICENSE for license details.
+
+#include "dataset.h"
+#include "util.h"
+#include <stddef.h>
+
+#pragma GCC optimize ("unroll-loops")
+
+void matmul(const size_t coreid, const size_t ncores, const size_t lda, const data_t A[], const data_t B[], data_t C[])
+{
+ size_t i, j, k;
+ size_t block = lda / ncores;
+ size_t start = block * coreid;
+
+ for (i = 0; i < lda; i++) {
+ for (j = start; j < (start+block); j++) {
+ data_t sum = 0;
+ for (k = 0; k < lda; k++)
+ sum += A[j*lda + k] * B[k*lda + i];
+ C[i + j*lda] = sum;
+ }
+ }
+}
diff --git a/sw/app/mt-matmul/matmul_gendata.pl b/sw/app/mt-matmul/matmul_gendata.pl
new file mode 100755
index 00000000..798d992e
--- /dev/null
+++ b/sw/app/mt-matmul/matmul_gendata.pl
@@ -0,0 +1,205 @@
+#!/usr/bin/perl -w
+#==========================================================================
+# matmul_gendata.pl
+#
+# Author : Christopher Batten (cbatten@mit.edu)
+# Date : April 29, 2005
+#
+(our $usageMsg = <<'ENDMSG') =~ s/^\#//gm;
+#
+# Simple script which creates an input data set and the reference data
+# for the matmul benchmark.
+#
+ENDMSG
+
+use strict "vars";
+use warnings;
+no warnings("once");
+use Getopt::Long;
+
+#--------------------------------------------------------------------------
+# Command line processing
+#--------------------------------------------------------------------------
+
+our %opts;
+
+sub usage()
+{
+
+ print "\n";
+ print " Usage: matmul_gendata.pl [options] \n";
+ print "\n";
+ print " Options:\n";
+ print " --help print this message\n";
+ print " --size size of input data [1000]\n";
+ print " --seed random seed [1]\n";
+ print "$usageMsg";
+
+ exit();
+}
+
+sub processCommandLine()
+{
+
+ $opts{"help"} = 0;
+ $opts{"size"} = 1000;
+ $opts{"seed"} = 1;
+ Getopt::Long::GetOptions( \%opts, 'help|?', 'size:i', 'seed:i' ) or usage();
+ $opts{"help"} and usage();
+
+}
+
+#--------------------------------------------------------------------------
+# Helper Functions
+#--------------------------------------------------------------------------
+
+sub printArray
+{
+ my $arrayName = $_[0];
+ my $arrayRef = $_[1];
+
+ my $numCols = 20;
+ my $arrayLen = scalar(@{$arrayRef});
+
+ print "static data_t ".$arrayName."[ARRAY_SIZE] = \n";
+ print "{\n";
+
+ if ( $arrayLen <= $numCols ) {
+ print " ";
+ for ( my $i = 0; $i < $arrayLen; $i++ ) {
+ print sprintf("%3d",$arrayRef->[$i]);
+ if ( $i != $arrayLen-1 ) {
+ print ", ";
+ }
+ }
+ print "\n";
+ }
+
+ else {
+ my $numRows = int($arrayLen/$numCols);
+ for ( my $j = 0; $j < $numRows; $j++ ) {
+ print " ";
+ for ( my $i = 0; $i < $numCols; $i++ ) {
+ my $index = $j*$numCols + $i;
+ print sprintf("%3d",$arrayRef->[$index]);
+ if ( $index != $arrayLen-1 ) {
+ print ", ";
+ }
+ }
+ print "\n";
+ }
+
+ if ( $arrayLen > ($numRows*$numCols) ) {
+ print " ";
+ for ( my $i = 0; $i < ($arrayLen-($numRows*$numCols)); $i++ ) {
+ my $index = $numCols*$numRows + $i;
+ print sprintf("%3d",$arrayRef->[$index]);
+ if ( $index != $arrayLen-1 ) {
+ print ", ";
+ }
+ }
+ print "\n";
+ }
+
+ }
+
+ print "};\n\n";
+}
+
+
+
+#--------------------------------------------------------------------------
+# Matmul
+#--------------------------------------------------------------------------
+
+# http://answers.oreilly.com/topic/418-how-to-multiply-matrices-in-perl/
+
+sub mmult {
+ my ($m1,$m2) = @_;
+ my ($m1rows,$m1cols) = matdim($m1);
+ my ($m2rows,$m2cols) = matdim($m2);
+
+ my $result = [ ];
+ my ($i, $j, $k);
+
+ for $i (range($m1rows)) {
+ for $j (range($m2cols)) {
+ for $k (range($m1cols)) {
+ $result->[$i][$j] += $m1->[$i][$k] * $m2->[$k][$j];
+ }
+ }
+ }
+ return $result;
+}
+
+sub range { 0 .. ($_[0] - 1) }
+
+
+sub veclen {
+ my $ary_ref = $_[0];
+ my $type = ref $ary_ref;
+ if ($type ne "ARRAY") { die "$type is bad array ref for $ary_ref" }
+ return scalar(@$ary_ref);
+}
+
+sub matdim {
+ my $matrix = $_[0];
+ my $rows = veclen($matrix);
+ my $cols = veclen($matrix->[0]);
+ return ($rows, $cols);
+}
+
+#--------------------------------------------------------------------------
+# Main
+#--------------------------------------------------------------------------
+
+sub main()
+{
+
+ processCommandLine();
+ srand($opts{"seed"});
+
+ # create random input arrays
+ my $mat_values1;
+ my $mat_values2;
+ for ( my $i = 0; $i < $opts{"size"}; $i++ ) {
+ for ( my $j = 0; $j < $opts{"size"}; $j++ ) {
+ $mat_values1->[$i][$j] = int(rand(4));
+ $mat_values2->[$i][$j] = int(rand(4));
+ }
+ }
+
+ # perform matmul
+ my $mat_results = mmult( $mat_values1, $mat_values2 );
+
+ # translate 2d arrays to 1d-somethings (I don't know how to code in perl - Chris)
+ my @values1;
+ my @values2;
+ my @results;
+ for ( my $i = 0; $i < $opts{"size"}; $i++ ) {
+ for ( my $j = 0; $j < $opts{"size"}; $j++ ) {
+ my $value1 = $mat_values1->[$i][$j];
+ my $value2 = $mat_values2->[$i][$j];
+ my $result = $mat_results->[$i][$j];
+ push( @values1, $value1 );
+ push( @values2, $value2 );
+ push( @results, $result );
+ }
+ }
+
+ print "\n#ifndef __DATASET_H";
+ print "\n#define __DATASET_H";
+ print "\n\#define ARRAY_SIZE ".($opts{"size"}*$opts{"size"})." \n\n";
+ print "\n\#define DIM_SIZE ".$opts{"size"}." \n\n";
+ print "\ntypedef int data_t;";
+
+ printArray( "input1_data", \@values1 );
+ printArray( "input2_data", \@values2 );
+ printArray( "verify_data", \@results);
+
+ print "\n#endif //__DATASET_H";
+
+}
+
+main();
+
diff --git a/sw/app/mt-matmul/mt-matmul.c b/sw/app/mt-matmul/mt-matmul.c
new file mode 100644
index 00000000..dbb75623
--- /dev/null
+++ b/sw/app/mt-matmul/mt-matmul.c
@@ -0,0 +1,57 @@
+// See LICENSE for license details.
+
+//**************************************************************************
+// Multi-threaded Matrix Multiply benchmark
+//--------------------------------------------------------------------------
+// TA : Christopher Celio
+// Student:
+//
+//
+// This benchmark multiplies two 2-D arrays together and writes the results to
+// a third vector. The input data (and reference data) should be generated
+// using the matmul_gendata.pl perl script and dumped to a file named
+// dataset.h.
+
+//--------------------------------------------------------------------------
+// Includes
+
+#include <string.h>
+#include <stdlib.h>
+#include <stdio.h>
+#include <stddef.h>
+
+
+//--------------------------------------------------------------------------
+// Input/Reference Data
+
+#include "dataset.h"
+
+
+//--------------------------------------------------------------------------
+// Basic Utilities and Multi-thread Support
+
+#include "util.h"
+
+
+//--------------------------------------------------------------------------
+// matmul function
+
+extern void matmul(const size_t coreid, const size_t ncores, const size_t lda, const data_t A[], const data_t B[], data_t C[] );
+
+
+//--------------------------------------------------------------------------
+// Main
+//
+// all threads start executing thread_entry(). Use their "coreid" to
+// differentiate between threads (each thread is running on a separate core).
+
+void thread_entry(int cid, int nc)
+{
+ static data_t results_data[ARRAY_SIZE];
+
+ stats(matmul(cid, nc, DIM_SIZE, input1_data, input2_data, results_data); barrier(nc), DIM_SIZE/DIM_SIZE/DIM_SIZE);
+
+ int res = verify(ARRAY_SIZE, results_data, verify_data);
+
+ exit(res);
+}
diff --git a/sw/app/mt-vvadd/dataset.h b/sw/app/mt-vvadd/dataset.h
new file mode 100644
index 00000000..a421b7b2
--- /dev/null
+++ b/sw/app/mt-vvadd/dataset.h
@@ -0,0 +1,173 @@
+// See LICENSE for license details.
+
+#ifndef __DATASET_H
+#define __DATASET_H
+
+#define DATA_SIZE 1000
+
+typedef double data_t;
+
+static data_t input1_data[DATA_SIZE] =
+{
+ 0.00, 15.00, 10.00, 3.00, 14.00, 6.00, 2.00, 18.00, 11.00, 15.00, 11.00, 0.00, 17.00, 16.00, 7.00, 13.00, 18.00, 2.00, 2.00, 5.00,
+ 8.00, 5.00, 12.00, 14.00, 6.00, 12.00, 16.00, 7.00, 9.00, 17.00, 10.00, 10.00, 3.00, 5.00, 14.00, 11.00, 9.00, 12.00, 3.00, 1.00,
+ 5.00, 4.00, 6.00, 17.00, 17.00, 4.00, 17.00, 15.00, 17.00, 18.00, 3.00, 18.00, 10.00, 6.00, 12.00, 12.00, 3.00, 2.00, 16.00, 1.00,
+ 5.00, 6.00, 2.00, 17.00, 16.00, 5.00, 10.00, 18.00, 14.00, 4.00, 9.00, 9.00, 7.00, 4.00, 8.00, 13.00, 12.00, 6.00, 4.00, 17.00,
+ 5.00, 2.00, 11.00, 11.00, 7.00, 6.00, 8.00, 5.00, 6.00, 6.00, 11.00, 1.00, 18.00, 7.00, 6.00, 9.00, 10.00, 17.00, 14.00, 4.00,
+ 14.00, 11.00, 2.00, 0.00, 2.00, 17.00, 17.00, 15.00, 10.00, 8.00, 12.00, 18.00, 5.00, 0.00, 0.00, 1.00, 1.00, 8.00, 11.00, 11.00,
+ 7.00, 5.00, 15.00, 18.00, 15.00, 6.00, 8.00, 9.00, 18.00, 6.00, 15.00, 16.00, 10.00, 18.00, 13.00, 6.00, 10.00, 16.00, 0.00, 10.00,
+ 12.00, 8.00, 8.00, 3.00, 0.00, 1.00, 4.00, 0.00, 8.00, 15.00, 16.00, 9.00, 7.00, 7.00, 10.00, 9.00, 16.00, 12.00, 5.00, 5.00,
+ 9.00, 5.00, 17.00, 4.00, 13.00, 13.00, 4.00, 14.00, 10.00, 5.00, 10.00, 10.00, 6.00, 18.00, 5.00, 15.00, 5.00, 15.00, 13.00, 18.00,
+ 6.00, 13.00, 5.00, 18.00, 12.00, 14.00, 1.00, 7.00, 2.00, 1.00, 7.00, 12.00, 15.00, 15.00, 6.00, 2.00, 1.00, 2.00, 18.00, 6.00,
+ 10.00, 14.00, 9.00, 15.00, 11.00, 0.00, 3.00, 1.00, 2.00, 2.00, 14.00, 7.00, 18.00, 0.00, 2.00, 2.00, 16.00, 8.00, 4.00, 5.00,
+ 7.00, 11.00, 7.00, 10.00, 14.00, 10.00, 3.00, 0.00, 13.00, 9.00, 14.00, 0.00, 14.00, 1.00, 3.00, 16.00, 2.00, 14.00, 6.00, 17.00,
+ 17.00, 6.00, 9.00, 8.00, 9.00, 12.00, 5.00, 14.00, 2.00, 16.00, 17.00, 5.00, 4.00, 0.00, 14.00, 10.00, 6.00, 15.00, 15.00, 14.00,
+ 5.00, 1.00, 8.00, 8.00, 13.00, 8.00, 0.00, 4.00, 7.00, 9.00, 13.00, 16.00, 9.00, 14.00, 9.00, 13.00, 0.00, 7.00, 16.00, 17.00,
+ 18.00, 10.00, 13.00, 8.00, 4.00, 9.00, 13.00, 0.00, 6.00, 4.00, 6.00, 4.00, 10.00, 14.00, 14.00, 9.00, 15.00, 15.00, 3.00, 3.00,
+ 12.00, 0.00, 3.00, 2.00, 16.00, 1.00, 7.00, 2.00, 16.00, 2.00, 2.00, 0.00, 14.00, 3.00, 3.00, 10.00, 4.00, 10.00, 3.00, 4.00,
+ 13.00, 14.00, 13.00, 0.00, 1.00, 15.00, 16.00, 9.00, 7.00, 9.00, 0.00, 11.00, 1.00, 1.00, 15.00, 17.00, 12.00, 16.00, 15.00, 4.00,
+ 8.00, 2.00, 10.00, 10.00, 0.00, 18.00, 17.00, 7.00, 7.00, 2.00, 10.00, 17.00, 9.00, 7.00, 5.00, 3.00, 8.00, 11.00, 6.00, 9.00,
+ 13.00, 0.00, 3.00, 5.00, 2.00, 5.00, 7.00, 4.00, 9.00, 2.00, 13.00, 17.00, 14.00, 12.00, 1.00, 3.00, 7.00, 17.00, 0.00, 14.00,
+ 16.00, 2.00, 2.00, 1.00, 2.00, 15.00, 16.00, 8.00, 2.00, 4.00, 15.00, 15.00, 10.00, 6.00, 11.00, 9.00, 15.00, 17.00, 3.00, 8.00,
+ 15.00, 3.00, 10.00, 15.00, 8.00, 14.00, 16.00, 15.00, 15.00, 14.00, 1.00, 7.00, 4.00, 18.00, 2.00, 13.00, 11.00, 15.00, 7.00, 10.00,
+ 13.00, 10.00, 7.00, 14.00, 18.00, 4.00, 18.00, 4.00, 3.00, 9.00, 1.00, 13.00, 15.00, 2.00, 5.00, 15.00, 12.00, 10.00, 2.00, 0.00,
+ 10.00, 15.00, 0.00, 11.00, 14.00, 11.00, 14.00, 9.00, 1.00, 18.00, 14.00, 18.00, 15.00, 5.00, 1.00, 15.00, 18.00, 14.00, 3.00, 15.00,
+ 11.00, 2.00, 15.00, 0.00, 13.00, 1.00, 4.00, 14.00, 14.00, 5.00, 2.00, 13.00, 17.00, 8.00, 7.00, 6.00, 5.00, 10.00, 14.00, 14.00,
+ 17.00, 0.00, 0.00, 17.00, 18.00, 15.00, 10.00, 16.00, 18.00, 5.00, 9.00, 10.00, 18.00, 7.00, 11.00, 5.00, 4.00, 16.00, 2.00, 8.00,
+ 13.00, 1.00, 12.00, 3.00, 4.00, 6.00, 15.00, 12.00, 0.00, 6.00, 18.00, 12.00, 14.00, 18.00, 3.00, 2.00, 3.00, 5.00, 3.00, 14.00,
+ 18.00, 12.00, 10.00, 11.00, 8.00, 4.00, 10.00, 10.00, 9.00, 18.00, 14.00, 3.00, 7.00, 17.00, 12.00, 0.00, 10.00, 9.00, 17.00, 3.00,
+ 0.00, 4.00, 6.00, 16.00, 14.00, 12.00, 13.00, 13.00, 18.00, 7.00, 0.00, 1.00, 9.00, 7.00, 12.00, 6.00, 18.00, 8.00, 9.00, 13.00,
+ 13.00, 17.00, 10.00, 16.00, 1.00, 10.00, 17.00, 16.00, 2.00, 18.00, 4.00, 2.00, 6.00, 1.00, 1.00, 1.00, 8.00, 14.00, 6.00, 6.00,
+ 13.00, 14.00, 13.00, 6.00, 5.00, 10.00, 11.00, 11.00, 16.00, 1.00, 5.00, 9.00, 13.00, 8.00, 10.00, 2.00, 12.00, 15.00, 5.00, 14.00,
+ 3.00, 7.00, 9.00, 18.00, 2.00, 11.00, 16.00, 4.00, 5.00, 10.00, 17.00, 10.00, 3.00, 4.00, 14.00, 18.00, 13.00, 6.00, 8.00, 11.00,
+ 14.00, 3.00, 5.00, 6.00, 6.00, 5.00, 13.00, 0.00, 9.00, 9.00, 1.00, 7.00, 5.00, 5.00, 1.00, 6.00, 18.00, 11.00, 17.00, 7.00,
+ 1.00, 10.00, 5.00, 12.00, 6.00, 16.00, 16.00, 5.00, 1.00, 10.00, 10.00, 15.00, 7.00, 18.00, 8.00, 17.00, 3.00, 5.00, 3.00, 14.00,
+ 0.00, 16.00, 12.00, 0.00, 14.00, 17.00, 16.00, 2.00, 18.00, 13.00, 10.00, 13.00, 4.00, 14.00, 2.00, 3.00, 4.00, 8.00, 17.00, 0.00,
+ 6.00, 11.00, 5.00, 3.00, 3.00, 2.00, 15.00, 13.00, 10.00, 4.00, 1.00, 11.00, 6.00, 17.00, 1.00, 0.00, 18.00, 3.00, 3.00, 11.00,
+ 7.00, 7.00, 11.00, 14.00, 7.00, 16.00, 11.00, 10.00, 8.00, 6.00, 11.00, 5.00, 17.00, 10.00, 7.00, 8.00, 14.00, 2.00, 9.00, 17.00,
+ 15.00, 13.00, 10.00, 6.00, 0.00, 15.00, 11.00, 10.00, 11.00, 18.00, 2.00, 5.00, 17.00, 18.00, 11.00, 15.00, 3.00, 17.00, 9.00, 17.00,
+ 8.00, 6.00, 2.00, 4.00, 2.00, 11.00, 15.00, 2.00, 18.00, 3.00, 9.00, 7.00, 15.00, 9.00, 14.00, 10.00, 9.00, 6.00, 13.00, 8.00,
+ 15.00, 14.00, 0.00, 11.00, 5.00, 2.00, 12.00, 14.00, 10.00, 16.00, 9.00, 7.00, 9.00, 17.00, 4.00, 4.00, 7.00, 8.00, 4.00, 4.00,
+ 9.00, 7.00, 3.00, 5.00, 11.00, 11.00, 10.00, 13.00, 3.00, 14.00, 15.00, 8.00, 1.00, 1.00, 3.00, 0.00, 16.00, 9.00, 6.00, 1.00,
+ 0.00, 2.00, 0.00, 6.00, 13.00, 12.00, 5.00, 18.00, 1.00, 11.00, 17.00, 11.00, 16.00, 14.00, 14.00, 9.00, 11.00, 9.00, 17.00, 15.00,
+ 5.00, 18.00, 2.00, 11.00, 10.00, 16.00, 18.00, 5.00, 11.00, 12.00, 11.00, 18.00, 7.00, 6.00, 8.00, 3.00, 4.00, 3.00, 16.00, 4.00,
+ 6.00, 2.00, 15.00, 6.00, 7.00, 16.00, 0.00, 7.00, 11.00, 10.00, 3.00, 0.00, 14.00, 16.00, 15.00, 15.00, 12.00, 7.00, 1.00, 4.00,
+ 8.00, 4.00, 12.00, 0.00, 7.00, 8.00, 1.00, 1.00, 14.00, 15.00, 9.00, 8.00, 6.00, 6.00, 4.00, 7.00, 8.00, 13.00, 10.00, 5.00,
+ 8.00, 11.00, 2.00, 16.00, 7.00, 17.00, 5.00, 2.00, 17.00, 0.00, 18.00, 6.00, 7.00, 4.00, 4.00, 12.00, 0.00, 18.00, 8.00, 4.00,
+ 7.00, 0.00, 11.00, 1.00, 11.00, 17.00, 18.00, 15.00, 8.00, 11.00, 15.00, 9.00, 12.00, 1.00, 5.00, 6.00, 1.00, 18.00, 14.00, 7.00,
+ 16.00, 16.00, 10.00, 3.00, 13.00, 0.00, 12.00, 9.00, 18.00, 14.00, 15.00, 4.00, 11.00, 15.00, 15.00, 8.00, 16.00, 11.00, 13.00, 12.00,
+ 1.00, 13.00, 14.00, 2.00, 11.00, 0.00, 17.00, 11.00, 12.00, 6.00, 4.00, 4.00, 11.00, 13.00, 10.00, 2.00, 10.00, 14.00, 0.00, 6.00,
+ 18.00, 10.00, 7.00, 14.00, 12.00, 9.00, 4.00, 16.00, 17.00, 8.00, 14.00, 9.00, 0.00, 4.00, 15.00, 13.00, 8.00, 13.00, 13.00, 8.00,
+ 15.00, 6.00, 11.00, 4.00, 2.00, 6.00, 5.00, 14.00, 5.00, 17.00, 12.00, 11.00, 17.00, 4.00, 13.00, 7.00, 16.00, 12.00, 7.00, 18.00
+};
+
+static data_t input2_data[DATA_SIZE] =
+{
+ 8.00, 6.00, 0.00, 18.00, 6.00, 10.00, 1.00, 2.00, 4.00, 2.00, 4.00, 10.00, 6.00, 11.00, 17.00, 4.00, 0.00, 16.00, 14.00, 12.00,
+ 9.00, 8.00, 13.00, 15.00, 18.00, 2.00, 13.00, 10.00, 5.00, 4.00, 12.00, 9.00, 1.00, 13.00, 12.00, 7.00, 10.00, 17.00, 11.00, 10.00,
+ 18.00, 15.00, 11.00, 12.00, 7.00, 9.00, 6.00, 5.00, 11.00, 7.00, 10.00, 12.00, 18.00, 18.00, 15.00, 1.00, 3.00, 18.00, 11.00, 16.00,
+ 13.00, 18.00, 4.00, 13.00, 8.00, 7.00, 10.00, 13.00, 0.00, 9.00, 1.00, 16.00, 13.00, 7.00, 5.00, 5.00, 11.00, 1.00, 6.00, 10.00,
+ 12.00, 3.00, 10.00, 5.00, 15.00, 15.00, 13.00, 14.00, 14.00, 1.00, 18.00, 5.00, 16.00, 14.00, 10.00, 4.00, 8.00, 4.00, 6.00, 6.00,
+ 13.00, 14.00, 8.00, 5.00, 14.00, 10.00, 9.00, 10.00, 17.00, 15.00, 6.00, 16.00, 12.00, 9.00, 10.00, 16.00, 16.00, 8.00, 1.00, 12.00,
+ 7.00, 0.00, 0.00, 3.00, 5.00, 7.00, 10.00, 3.00, 17.00, 10.00, 18.00, 16.00, 1.00, 11.00, 18.00, 9.00, 2.00, 0.00, 12.00, 6.00,
+ 13.00, 1.00, 13.00, 5.00, 7.00, 13.00, 17.00, 9.00, 15.00, 13.00, 5.00, 2.00, 4.00, 4.00, 3.00, 0.00, 9.00, 11.00, 3.00, 12.00,
+ 6.00, 11.00, 1.00, 16.00, 12.00, 11.00, 2.00, 2.00, 15.00, 12.00, 8.00, 9.00, 14.00, 2.00, 11.00, 0.00, 0.00, 7.00, 2.00, 13.00,
+ 15.00, 18.00, 7.00, 16.00, 16.00, 1.00, 1.00, 12.00, 12.00, 2.00, 2.00, 1.00, 7.00, 4.00, 0.00, 8.00, 18.00, 4.00, 11.00, 6.00,
+ 17.00, 13.00, 12.00, 5.00, 16.00, 12.00, 0.00, 9.00, 10.00, 10.00, 18.00, 12.00, 8.00, 7.00, 5.00, 8.00, 16.00, 3.00, 9.00, 18.00,
+ 12.00, 13.00, 18.00, 6.00, 8.00, 12.00, 2.00, 12.00, 8.00, 8.00, 9.00, 18.00, 8.00, 0.00, 9.00, 2.00, 6.00, 7.00, 0.00, 3.00,
+ 11.00, 2.00, 18.00, 2.00, 16.00, 1.00, 16.00, 11.00, 11.00, 16.00, 16.00, 11.00, 7.00, 4.00, 14.00, 10.00, 5.00, 8.00, 4.00, 14.00,
+ 17.00, 13.00, 13.00, 3.00, 1.00, 14.00, 1.00, 7.00, 0.00, 2.00, 7.00, 14.00, 4.00, 9.00, 14.00, 3.00, 9.00, 13.00, 13.00, 3.00,
+ 3.00, 17.00, 0.00, 18.00, 4.00, 8.00, 6.00, 9.00, 4.00, 2.00, 0.00, 14.00, 3.00, 3.00, 14.00, 8.00, 6.00, 7.00, 2.00, 12.00,
+ 5.00, 14.00, 6.00, 12.00, 2.00, 16.00, 1.00, 15.00, 7.00, 18.00, 0.00, 0.00, 13.00, 13.00, 12.00, 11.00, 16.00, 15.00, 14.00, 8.00,
+ 9.00, 10.00, 8.00, 8.00, 13.00, 13.00, 13.00, 10.00, 1.00, 15.00, 4.00, 0.00, 12.00, 1.00, 8.00, 12.00, 1.00, 18.00, 12.00, 18.00,
+ 9.00, 1.00, 11.00, 5.00, 13.00, 7.00, 1.00, 13.00, 5.00, 8.00, 17.00, 11.00, 13.00, 15.00, 9.00, 3.00, 17.00, 18.00, 9.00, 3.00,
+ 15.00, 11.00, 12.00, 0.00, 2.00, 15.00, 3.00, 0.00, 13.00, 1.00, 14.00, 14.00, 15.00, 8.00, 6.00, 0.00, 0.00, 11.00, 17.00, 0.00,
+ 1.00, 8.00, 6.00, 6.00, 10.00, 6.00, 18.00, 12.00, 7.00, 18.00, 4.00, 6.00, 15.00, 18.00, 7.00, 5.00, 8.00, 6.00, 6.00, 7.00,
+ 4.00, 4.00, 10.00, 17.00, 12.00, 13.00, 11.00, 15.00, 12.00, 18.00, 7.00, 12.00, 17.00, 10.00, 14.00, 12.00, 2.00, 7.00, 17.00, 3.00,
+ 8.00, 6.00, 3.00, 9.00, 3.00, 7.00, 7.00, 15.00, 18.00, 5.00, 13.00, 13.00, 15.00, 10.00, 0.00, 11.00, 10.00, 1.00, 5.00, 16.00,
+ 2.00, 7.00, 14.00, 12.00, 7.00, 17.00, 17.00, 11.00, 0.00, 5.00, 16.00, 14.00, 1.00, 9.00, 8.00, 8.00, 3.00, 17.00, 0.00, 8.00,
+ 6.00, 5.00, 7.00, 6.00, 17.00, 3.00, 3.00, 8.00, 3.00, 12.00, 17.00, 5.00, 14.00, 3.00, 11.00, 5.00, 17.00, 2.00, 15.00, 1.00,
+ 18.00, 11.00, 12.00, 0.00, 0.00, 14.00, 7.00, 17.00, 15.00, 10.00, 18.00, 10.00, 11.00, 7.00, 12.00, 10.00, 17.00, 2.00, 18.00, 9.00,
+ 11.00, 4.00, 17.00, 10.00, 15.00, 12.00, 4.00, 1.00, 5.00, 10.00, 4.00, 2.00, 11.00, 3.00, 4.00, 15.00, 16.00, 10.00, 2.00, 2.00,
+ 15.00, 16.00, 0.00, 13.00, 16.00, 9.00, 1.00, 7.00, 3.00, 10.00, 7.00, 2.00, 12.00, 8.00, 1.00, 5.00, 0.00, 16.00, 4.00, 14.00,
+ 13.00, 16.00, 3.00, 0.00, 10.00, 6.00, 3.00, 9.00, 1.00, 3.00, 0.00, 13.00, 12.00, 17.00, 11.00, 4.00, 15.00, 15.00, 12.00, 4.00,
+ 4.00, 2.00, 16.00, 6.00, 11.00, 17.00, 14.00, 7.00, 4.00, 14.00, 8.00, 8.00, 3.00, 18.00, 17.00, 17.00, 12.00, 10.00, 11.00, 1.00,
+ 8.00, 13.00, 1.00, 14.00, 0.00, 9.00, 0.00, 7.00, 9.00, 0.00, 7.00, 12.00, 0.00, 18.00, 10.00, 1.00, 5.00, 13.00, 13.00, 2.00,
+ 10.00, 4.00, 2.00, 6.00, 0.00, 16.00, 2.00, 15.00, 13.00, 6.00, 8.00, 5.00, 6.00, 15.00, 12.00, 6.00, 6.00, 7.00, 8.00, 1.00,
+ 11.00, 9.00, 7.00, 18.00, 14.00, 4.00, 9.00, 6.00, 4.00, 2.00, 10.00, 13.00, 6.00, 17.00, 2.00, 11.00, 7.00, 3.00, 8.00, 9.00,
+ 2.00, 6.00, 18.00, 12.00, 18.00, 13.00, 8.00, 1.00, 11.00, 4.00, 13.00, 14.00, 16.00, 8.00, 6.00, 18.00, 14.00, 15.00, 9.00, 11.00,
+ 2.00, 13.00, 4.00, 3.00, 3.00, 15.00, 14.00, 3.00, 13.00, 12.00, 14.00, 16.00, 18.00, 12.00, 5.00, 11.00, 2.00, 3.00, 15.00, 1.00,
+ 12.00, 1.00, 15.00, 13.00, 12.00, 18.00, 4.00, 17.00, 13.00, 7.00, 11.00, 13.00, 7.00, 10.00, 1.00, 3.00, 18.00, 6.00, 10.00, 3.00,
+ 9.00, 16.00, 12.00, 10.00, 6.00, 6.00, 7.00, 16.00, 16.00, 16.00, 17.00, 18.00, 8.00, 18.00, 0.00, 6.00, 17.00, 13.00, 14.00, 8.00,
+ 0.00, 7.00, 5.00, 13.00, 8.00, 12.00, 14.00, 9.00, 10.00, 10.00, 9.00, 9.00, 8.00, 6.00, 0.00, 14.00, 16.00, 8.00, 7.00, 16.00,
+ 10.00, 3.00, 1.00, 9.00, 11.00, 2.00, 6.00, 18.00, 5.00, 4.00, 2.00, 11.00, 10.00, 17.00, 16.00, 2.00, 12.00, 15.00, 14.00, 6.00,
+ 6.00, 17.00, 3.00, 10.00, 9.00, 18.00, 18.00, 6.00, 11.00, 16.00, 18.00, 17.00, 7.00, 14.00, 1.00, 16.00, 7.00, 9.00, 11.00, 12.00,
+ 10.00, 6.00, 1.00, 16.00, 9.00, 18.00, 0.00, 9.00, 16.00, 10.00, 14.00, 6.00, 9.00, 14.00, 15.00, 7.00, 12.00, 8.00, 1.00, 1.00,
+ 1.00, 17.00, 17.00, 17.00, 18.00, 1.00, 15.00, 18.00, 16.00, 16.00, 11.00, 7.00, 4.00, 15.00, 3.00, 14.00, 13.00, 14.00, 9.00, 2.00,
+ 4.00, 8.00, 14.00, 7.00, 0.00, 12.00, 14.00, 15.00, 8.00, 2.00, 11.00, 5.00, 6.00, 16.00, 6.00, 4.00, 16.00, 7.00, 9.00, 5.00,
+ 1.00, 0.00, 16.00, 10.00, 9.00, 6.00, 5.00, 8.00, 15.00, 13.00, 7.00, 18.00, 18.00, 8.00, 0.00, 15.00, 4.00, 6.00, 14.00, 3.00,
+ 3.00, 2.00, 9.00, 14.00, 18.00, 13.00, 10.00, 15.00, 0.00, 11.00, 16.00, 7.00, 16.00, 18.00, 0.00, 12.00, 6.00, 13.00, 12.00, 12.00,
+ 5.00, 3.00, 5.00, 16.00, 13.00, 16.00, 8.00, 5.00, 12.00, 8.00, 8.00, 0.00, 2.00, 9.00, 18.00, 11.00, 8.00, 4.00, 14.00, 6.00,
+ 17.00, 2.00, 6.00, 8.00, 11.00, 13.00, 6.00, 18.00, 17.00, 6.00, 8.00, 0.00, 1.00, 14.00, 18.00, 4.00, 0.00, 4.00, 3.00, 3.00,
+ 16.00, 8.00, 16.00, 1.00, 2.00, 0.00, 15.00, 14.00, 10.00, 9.00, 15.00, 3.00, 5.00, 18.00, 5.00, 6.00, 7.00, 3.00, 7.00, 2.00,
+ 6.00, 12.00, 10.00, 10.00, 18.00, 16.00, 0.00, 9.00, 17.00, 10.00, 9.00, 14.00, 15.00, 5.00, 8.00, 15.00, 3.00, 15.00, 14.00, 11.00,
+ 6.00, 6.00, 14.00, 0.00, 14.00, 0.00, 7.00, 12.00, 8.00, 7.00, 1.00, 3.00, 6.00, 10.00, 12.00, 1.00, 16.00, 5.00, 5.00, 6.00,
+ 17.00, 15.00, 15.00, 9.00, 4.00, 18.00, 17.00, 13.00, 12.00, 9.00, 7.00, 10.00, 2.00, 5.00, 8.00, 18.00, 1.00, 15.00, 8.00, 0.00
+};
+
+static data_t verify_data[DATA_SIZE] =
+{
+ 8.00, 21.00, 10.00, 21.00, 20.00, 16.00, 3.00, 20.00, 15.00, 17.00, 15.00, 10.00, 23.00, 27.00, 24.00, 17.00, 18.00, 18.00, 16.00, 17.00,
+ 17.00, 13.00, 25.00, 29.00, 24.00, 14.00, 29.00, 17.00, 14.00, 21.00, 22.00, 19.00, 4.00, 18.00, 26.00, 18.00, 19.00, 29.00, 14.00, 11.00,
+ 23.00, 19.00, 17.00, 29.00, 24.00, 13.00, 23.00, 20.00, 28.00, 25.00, 13.00, 30.00, 28.00, 24.00, 27.00, 13.00, 6.00, 20.00, 27.00, 17.00,
+ 18.00, 24.00, 6.00, 30.00, 24.00, 12.00, 20.00, 31.00, 14.00, 13.00, 10.00, 25.00, 20.00, 11.00, 13.00, 18.00, 23.00, 7.00, 10.00, 27.00,
+ 17.00, 5.00, 21.00, 16.00, 22.00, 21.00, 21.00, 19.00, 20.00, 7.00, 29.00, 6.00, 34.00, 21.00, 16.00, 13.00, 18.00, 21.00, 20.00, 10.00,
+ 27.00, 25.00, 10.00, 5.00, 16.00, 27.00, 26.00, 25.00, 27.00, 23.00, 18.00, 34.00, 17.00, 9.00, 10.00, 17.00, 17.00, 16.00, 12.00, 23.00,
+ 14.00, 5.00, 15.00, 21.00, 20.00, 13.00, 18.00, 12.00, 35.00, 16.00, 33.00, 32.00, 11.00, 29.00, 31.00, 15.00, 12.00, 16.00, 12.00, 16.00,
+ 25.00, 9.00, 21.00, 8.00, 7.00, 14.00, 21.00, 9.00, 23.00, 28.00, 21.00, 11.00, 11.00, 11.00, 13.00, 9.00, 25.00, 23.00, 8.00, 17.00,
+ 15.00, 16.00, 18.00, 20.00, 25.00, 24.00, 6.00, 16.00, 25.00, 17.00, 18.00, 19.00, 20.00, 20.00, 16.00, 15.00, 5.00, 22.00, 15.00, 31.00,
+ 21.00, 31.00, 12.00, 34.00, 28.00, 15.00, 2.00, 19.00, 14.00, 3.00, 9.00, 13.00, 22.00, 19.00, 6.00, 10.00, 19.00, 6.00, 29.00, 12.00,
+ 27.00, 27.00, 21.00, 20.00, 27.00, 12.00, 3.00, 10.00, 12.00, 12.00, 32.00, 19.00, 26.00, 7.00, 7.00, 10.00, 32.00, 11.00, 13.00, 23.00,
+ 19.00, 24.00, 25.00, 16.00, 22.00, 22.00, 5.00, 12.00, 21.00, 17.00, 23.00, 18.00, 22.00, 1.00, 12.00, 18.00, 8.00, 21.00, 6.00, 20.00,
+ 28.00, 8.00, 27.00, 10.00, 25.00, 13.00, 21.00, 25.00, 13.00, 32.00, 33.00, 16.00, 11.00, 4.00, 28.00, 20.00, 11.00, 23.00, 19.00, 28.00,
+ 22.00, 14.00, 21.00, 11.00, 14.00, 22.00, 1.00, 11.00, 7.00, 11.00, 20.00, 30.00, 13.00, 23.00, 23.00, 16.00, 9.00, 20.00, 29.00, 20.00,
+ 21.00, 27.00, 13.00, 26.00, 8.00, 17.00, 19.00, 9.00, 10.00, 6.00, 6.00, 18.00, 13.00, 17.00, 28.00, 17.00, 21.00, 22.00, 5.00, 15.00,
+ 17.00, 14.00, 9.00, 14.00, 18.00, 17.00, 8.00, 17.00, 23.00, 20.00, 2.00, 0.00, 27.00, 16.00, 15.00, 21.00, 20.00, 25.00, 17.00, 12.00,
+ 22.00, 24.00, 21.00, 8.00, 14.00, 28.00, 29.00, 19.00, 8.00, 24.00, 4.00, 11.00, 13.00, 2.00, 23.00, 29.00, 13.00, 34.00, 27.00, 22.00,
+ 17.00, 3.00, 21.00, 15.00, 13.00, 25.00, 18.00, 20.00, 12.00, 10.00, 27.00, 28.00, 22.00, 22.00, 14.00, 6.00, 25.00, 29.00, 15.00, 12.00,
+ 28.00, 11.00, 15.00, 5.00, 4.00, 20.00, 10.00, 4.00, 22.00, 3.00, 27.00, 31.00, 29.00, 20.00, 7.00, 3.00, 7.00, 28.00, 17.00, 14.00,
+ 17.00, 10.00, 8.00, 7.00, 12.00, 21.00, 34.00, 20.00, 9.00, 22.00, 19.00, 21.00, 25.00, 24.00, 18.00, 14.00, 23.00, 23.00, 9.00, 15.00,
+ 19.00, 7.00, 20.00, 32.00, 20.00, 27.00, 27.00, 30.00, 27.00, 32.00, 8.00, 19.00, 21.00, 28.00, 16.00, 25.00, 13.00, 22.00, 24.00, 13.00,
+ 21.00, 16.00, 10.00, 23.00, 21.00, 11.00, 25.00, 19.00, 21.00, 14.00, 14.00, 26.00, 30.00, 12.00, 5.00, 26.00, 22.00, 11.00, 7.00, 16.00,
+ 12.00, 22.00, 14.00, 23.00, 21.00, 28.00, 31.00, 20.00, 1.00, 23.00, 30.00, 32.00, 16.00, 14.00, 9.00, 23.00, 21.00, 31.00, 3.00, 23.00,
+ 17.00, 7.00, 22.00, 6.00, 30.00, 4.00, 7.00, 22.00, 17.00, 17.00, 19.00, 18.00, 31.00, 11.00, 18.00, 11.00, 22.00, 12.00, 29.00, 15.00,
+ 35.00, 11.00, 12.00, 17.00, 18.00, 29.00, 17.00, 33.00, 33.00, 15.00, 27.00, 20.00, 29.00, 14.00, 23.00, 15.00, 21.00, 18.00, 20.00, 17.00,
+ 24.00, 5.00, 29.00, 13.00, 19.00, 18.00, 19.00, 13.00, 5.00, 16.00, 22.00, 14.00, 25.00, 21.00, 7.00, 17.00, 19.00, 15.00, 5.00, 16.00,
+ 33.00, 28.00, 10.00, 24.00, 24.00, 13.00, 11.00, 17.00, 12.00, 28.00, 21.00, 5.00, 19.00, 25.00, 13.00, 5.00, 10.00, 25.00, 21.00, 17.00,
+ 13.00, 20.00, 9.00, 16.00, 24.00, 18.00, 16.00, 22.00, 19.00, 10.00, 0.00, 14.00, 21.00, 24.00, 23.00, 10.00, 33.00, 23.00, 21.00, 17.00,
+ 17.00, 19.00, 26.00, 22.00, 12.00, 27.00, 31.00, 23.00, 6.00, 32.00, 12.00, 10.00, 9.00, 19.00, 18.00, 18.00, 20.00, 24.00, 17.00, 7.00,
+ 21.00, 27.00, 14.00, 20.00, 5.00, 19.00, 11.00, 18.00, 25.00, 1.00, 12.00, 21.00, 13.00, 26.00, 20.00, 3.00, 17.00, 28.00, 18.00, 16.00,
+ 13.00, 11.00, 11.00, 24.00, 2.00, 27.00, 18.00, 19.00, 18.00, 16.00, 25.00, 15.00, 9.00, 19.00, 26.00, 24.00, 19.00, 13.00, 16.00, 12.00,
+ 25.00, 12.00, 12.00, 24.00, 20.00, 9.00, 22.00, 6.00, 13.00, 11.00, 11.00, 20.00, 11.00, 22.00, 3.00, 17.00, 25.00, 14.00, 25.00, 16.00,
+ 3.00, 16.00, 23.00, 24.00, 24.00, 29.00, 24.00, 6.00, 12.00, 14.00, 23.00, 29.00, 23.00, 26.00, 14.00, 35.00, 17.00, 20.00, 12.00, 25.00,
+ 2.00, 29.00, 16.00, 3.00, 17.00, 32.00, 30.00, 5.00, 31.00, 25.00, 24.00, 29.00, 22.00, 26.00, 7.00, 14.00, 6.00, 11.00, 32.00, 1.00,
+ 18.00, 12.00, 20.00, 16.00, 15.00, 20.00, 19.00, 30.00, 23.00, 11.00, 12.00, 24.00, 13.00, 27.00, 2.00, 3.00, 36.00, 9.00, 13.00, 14.00,
+ 16.00, 23.00, 23.00, 24.00, 13.00, 22.00, 18.00, 26.00, 24.00, 22.00, 28.00, 23.00, 25.00, 28.00, 7.00, 14.00, 31.00, 15.00, 23.00, 25.00,
+ 15.00, 20.00, 15.00, 19.00, 8.00, 27.00, 25.00, 19.00, 21.00, 28.00, 11.00, 14.00, 25.00, 24.00, 11.00, 29.00, 19.00, 25.00, 16.00, 33.00,
+ 18.00, 9.00, 3.00, 13.00, 13.00, 13.00, 21.00, 20.00, 23.00, 7.00, 11.00, 18.00, 25.00, 26.00, 30.00, 12.00, 21.00, 21.00, 27.00, 14.00,
+ 21.00, 31.00, 3.00, 21.00, 14.00, 20.00, 30.00, 20.00, 21.00, 32.00, 27.00, 24.00, 16.00, 31.00, 5.00, 20.00, 14.00, 17.00, 15.00, 16.00,
+ 19.00, 13.00, 4.00, 21.00, 20.00, 29.00, 10.00, 22.00, 19.00, 24.00, 29.00, 14.00, 10.00, 15.00, 18.00, 7.00, 28.00, 17.00, 7.00, 2.00,
+ 1.00, 19.00, 17.00, 23.00, 31.00, 13.00, 20.00, 36.00, 17.00, 27.00, 28.00, 18.00, 20.00, 29.00, 17.00, 23.00, 24.00, 23.00, 26.00, 17.00,
+ 9.00, 26.00, 16.00, 18.00, 10.00, 28.00, 32.00, 20.00, 19.00, 14.00, 22.00, 23.00, 13.00, 22.00, 14.00, 7.00, 20.00, 10.00, 25.00, 9.00,
+ 7.00, 2.00, 31.00, 16.00, 16.00, 22.00, 5.00, 15.00, 26.00, 23.00, 10.00, 18.00, 32.00, 24.00, 15.00, 30.00, 16.00, 13.00, 15.00, 7.00,
+ 11.00, 6.00, 21.00, 14.00, 25.00, 21.00, 11.00, 16.00, 14.00, 26.00, 25.00, 15.00, 22.00, 24.00, 4.00, 19.00, 14.00, 26.00, 22.00, 17.00,
+ 13.00, 14.00, 7.00, 32.00, 20.00, 33.00, 13.00, 7.00, 29.00, 8.00, 26.00, 6.00, 9.00, 13.00, 22.00, 23.00, 8.00, 22.00, 22.00, 10.00,
+ 24.00, 2.00, 17.00, 9.00, 22.00, 30.00, 24.00, 33.00, 25.00, 17.00, 23.00, 9.00, 13.00, 15.00, 23.00, 10.00, 1.00, 22.00, 17.00, 10.00,
+ 32.00, 24.00, 26.00, 4.00, 15.00, 0.00, 27.00, 23.00, 28.00, 23.00, 30.00, 7.00, 16.00, 33.00, 20.00, 14.00, 23.00, 14.00, 20.00, 14.00,
+ 7.00, 25.00, 24.00, 12.00, 29.00, 16.00, 17.00, 20.00, 29.00, 16.00, 13.00, 18.00, 26.00, 18.00, 18.00, 17.00, 13.00, 29.00, 14.00, 17.00,
+ 24.00, 16.00, 21.00, 14.00, 26.00, 9.00, 11.00, 28.00, 25.00, 15.00, 15.00, 12.00, 6.00, 14.00, 27.00, 14.00, 24.00, 18.00, 18.00, 14.00,
+ 32.00, 21.00, 26.00, 13.00, 6.00, 24.00, 22.00, 27.00, 17.00, 26.00, 19.00, 21.00, 19.00, 9.00, 21.00, 25.00, 17.00, 27.00, 15.00, 18.00
+};
+
+
+#endif //__DATASET_H
diff --git a/sw/app/mt-vvadd/mt-vvadd.c b/sw/app/mt-vvadd/mt-vvadd.c
new file mode 100644
index 00000000..54c96023
--- /dev/null
+++ b/sw/app/mt-vvadd/mt-vvadd.c
@@ -0,0 +1,78 @@
+// See LICENSE for license details.
+
+//**************************************************************************
+// Vector-vector add benchmark
+//--------------------------------------------------------------------------
+// Author : Andrew Waterman
+// TA : Christopher Celio
+// Student :
+//
+// This benchmark adds two vectors and writes the results to a
+// third vector. The input data (and reference data) should be
+// generated using the vvadd_gendata.pl perl script and dumped
+// to a file named dataset.h
+
+//--------------------------------------------------------------------------
+// Includes
+
+#include <string.h>
+#include <stdlib.h>
+#include <stdio.h>
+
+
+//--------------------------------------------------------------------------
+// Input/Reference Data
+
+#include "dataset.h"
+
+
+//--------------------------------------------------------------------------
+// Basic Utilities and Multi-thread Support
+
+#include "util.h"
+
+
+//--------------------------------------------------------------------------
+// vvadd function
+
+extern void __attribute__((noinline)) vvadd(int coreid, int ncores, size_t n, const data_t* x, const data_t* y, data_t* z);
+
+
+//--------------------------------------------------------------------------
+// Main
+//
+// all threads start executing thread_entry(). Use their "coreid" to
+// differentiate between threads (each thread is running on a separate core).
+
+void thread_entry(int cid, int nc)
+{
+ // static allocates data in the binary, which is visible to both threads
+ static data_t results_data[DATA_SIZE];
+
+ // First do out-of-place vvadd
+ barrier(nc);
+ stats(vvadd(cid, nc, DATA_SIZE, input1_data, input2_data, results_data); barrier(nc), DATA_SIZE);
+
+ if(cid == 0) {
+ int res = verifyDouble(DATA_SIZE, results_data, verify_data);
+ if(res) exit(res);
+ }
+
+ // Second do in-place vvadd
+ // Copying input
+ size_t i;
+ if(cid == 0) {
+ for (i = 0; i < DATA_SIZE; i++)
+ results_data[i] = input1_data[i];
+ }
+ barrier(nc);
+ stats(vvadd(cid, nc, DATA_SIZE, results_data, input2_data, results_data); barrier(nc), DATA_SIZE);
+
+ if(cid == 0) {
+ int res = verifyDouble(DATA_SIZE, results_data, verify_data);
+ if(res) exit(res);
+ }
+
+ barrier(nc);
+ exit(0);
+}
diff --git a/sw/app/mt-vvadd/vvadd.c b/sw/app/mt-vvadd/vvadd.c
new file mode 100644
index 00000000..5b74dd0f
--- /dev/null
+++ b/sw/app/mt-vvadd/vvadd.c
@@ -0,0 +1,18 @@
+// See LICENSE for license details.
+
+#include "stdlib.h"
+#include "dataset.h"
+
+//--------------------------------------------------------------------------
+// vvadd function
+
+void __attribute__((noinline)) vvadd(int coreid, int ncores, size_t n, const data_t* x, const data_t* y, data_t* z)
+{
+ size_t i;
+
+ // interleave accesses
+ for (i = coreid; i < n; i+=ncores)
+ {
+ z[i] = x[i] + y[i];
+ }
+}
diff --git a/sw/app/mt-vvadd/vvadd_gendata.pl b/sw/app/mt-vvadd/vvadd_gendata.pl
new file mode 100755
index 00000000..a9fceac6
--- /dev/null
+++ b/sw/app/mt-vvadd/vvadd_gendata.pl
@@ -0,0 +1,139 @@
+#!/usr/bin/perl -w
+#==========================================================================
+# vvadd_gendata.pl
+#
+# Author : Christopher Batten (cbatten@mit.edu)
+# Date : April 29, 2005
+#
+(our $usageMsg = <<'ENDMSG') =~ s/^\#//gm;
+#
+# Simple script which creates an input data set and the reference data
+# for the vvadd benchmark.
+#
+ENDMSG
+
+use strict "vars";
+use warnings;
+no warnings("once");
+use Getopt::Long;
+
+#--------------------------------------------------------------------------
+# Command line processing
+#--------------------------------------------------------------------------
+
+our %opts;
+
+sub usage()
+{
+
+ print "\n";
+ print " Usage: vvadd_gendata.pl [options] \n";
+ print "\n";
+ print " Options:\n";
+ print " --help print this message\n";
+ print " --size size of input data [1000]\n";
+ print " --seed random seed [1]\n";
+ print "$usageMsg";
+
+ exit();
+}
+
+sub processCommandLine()
+{
+
+ $opts{"help"} = 0;
+ $opts{"size"} = 1000;
+ $opts{"seed"} = 1;
+ Getopt::Long::GetOptions( \%opts, 'help|?', 'size:i', 'seed:i' ) or usage();
+ $opts{"help"} and usage();
+
+}
+
+#--------------------------------------------------------------------------
+# Helper Functions
+#--------------------------------------------------------------------------
+
+sub printArray
+{
+ my $arrayName = $_[0];
+ my $arrayRef = $_[1];
+
+ my $numCols = 20;
+ my $arrayLen = scalar(@{$arrayRef});
+
+ print "static data_t ".$arrayName."[DATA_SIZE] = \n";
+ print "{\n";
+
+ if ( $arrayLen <= $numCols ) {
+ print " ";
+ for ( my $i = 0; $i < $arrayLen; $i++ ) {
+ print sprintf("%3.2f",$arrayRef->[$i]);
+ if ( $i != $arrayLen-1 ) {
+ print ", ";
+ }
+ }
+ print "\n";
+ }
+
+ else {
+ my $numRows = int($arrayLen/$numCols);
+ for ( my $j = 0; $j < $numRows; $j++ ) {
+ print " ";
+ for ( my $i = 0; $i < $numCols; $i++ ) {
+ my $index = $j*$numCols + $i;
+ print sprintf("%3.2f",$arrayRef->[$index]);
+ if ( $index != $arrayLen-1 ) {
+ print ", ";
+ }
+ }
+ print "\n";
+ }
+
+ if ( $arrayLen > ($numRows*$numCols) ) {
+ print " ";
+ for ( my $i = 0; $i < ($arrayLen-($numRows*$numCols)); $i++ ) {
+ my $index = $numCols*$numRows + $i;
+ print sprintf("%3.2f",$arrayRef->[$index]);
+ if ( $index != $arrayLen-1 ) {
+ print ", ";
+ }
+ }
+ print "\n";
+ }
+
+ }
+
+ print "};\n\n";
+}
+
+#--------------------------------------------------------------------------
+# Main
+#--------------------------------------------------------------------------
+
+sub main()
+{
+
+ processCommandLine();
+ srand($opts{"seed"});
+
+ my @values1;
+ my @values2;
+ my @sum;
+ for ( my $i = 0; $i < $opts{"size"}; $i++ ) {
+ my $value1 = int(rand(19));
+ my $value2 = int(rand(19));
+ push( @values1, $value1 );
+ push( @values2, $value2 );
+ push( @sum, $value1 + $value2 );
+ }
+
+
+ print "\n\#define DATA_SIZE ".$opts{"size"}." \n\n";
+ printArray( "input1_data", \@values1 );
+ printArray( "input2_data", \@values2 );
+ printArray( "verify_data", \@sum );
+
+}
+
+main();
+
diff --git a/sw/app/multiply/dataset1.h b/sw/app/multiply/dataset1.h
new file mode 100644
index 00000000..2b0850e0
--- /dev/null
+++ b/sw/app/multiply/dataset1.h
@@ -0,0 +1,32 @@
+// See LICENSE for license details.
+
+
+#define DATA_SIZE 100
+
+int input_data1[DATA_SIZE] =
+{
+ 41, 454, 833, 335, 564, 1, 187, 989, 749, 365, 350, 572, 132, 64, 949, 153, 584, 216, 805, 140,
+ 621, 210, 6, 572, 931, 339, 890, 593, 392, 898, 694, 228, 961, 12, 110, 883, 116, 750, 296, 646,
+ 426, 500, 314, 436, 659, 701, 774, 812, 319, 981, 678, 150, 875, 696, 376, 564, 474, 272, 938, 258,
+ 539, 647, 569, 509, 203, 88, 280, 703, 759, 669, 606, 375, 511, 551, 657, 936, 195, 592, 81, 569,
+ 267, 952, 229, 800, 337, 584, 944, 643, 902, 368, 241, 489, 913, 328, 826, 313, 933, 592, 985, 388
+};
+
+int input_data2[DATA_SIZE] =
+{
+ 195, 543, 960, 649, 566, 979, 350, 997, 649, 814, 657, 79, 181, 208, 111, 998, 859, 629, 65, 847,
+ 288, 704, 349, 997, 141, 253, 905, 715, 886, 430, 264, 415, 576, 538, 979, 700, 761, 4, 241, 494,
+ 478, 100, 499, 864, 403, 693, 222, 416, 444, 296, 721, 285, 676, 620, 317, 78, 224, 351, 937, 540,
+ 288, 646, 119, 169, 615, 527, 606, 289, 389, 796, 351, 801, 455, 720, 278, 758, 367, 745, 358, 92,
+ 584, 989, 62, 271, 985, 853, 403, 788, 346, 531, 517, 222, 559, 461, 908, 241, 775, 358, 255, 332
+};
+
+int verify_data[DATA_SIZE] =
+{
+ 7995, 246522, 799680, 217415, 319224, 979, 65450, 986033, 486101, 297110, 229950, 45188, 23892, 13312, 105339, 152694, 501656, 135864, 52325, 118580,
+ 178848, 147840, 2094, 570284, 131271, 85767, 805450, 423995, 347312, 386140, 183216, 94620, 553536, 6456, 107690, 618100, 88276, 3000, 71336, 319124,
+ 203628, 50000, 156686, 376704, 265577, 485793, 171828, 337792, 141636, 290376, 488838, 42750, 591500, 431520, 119192, 43992, 106176, 95472, 878906, 139320,
+ 155232, 417962, 67711, 86021, 124845, 46376, 169680, 203167, 295251, 532524, 212706, 300375, 232505, 396720, 182646, 709488, 71565, 441040, 28998, 52348,
+ 155928, 941528, 14198, 216800, 331945, 498152, 380432, 506684, 312092, 195408, 124597, 108558, 510367, 151208, 750008, 75433, 723075, 211936, 251175, 128816
+};
+
diff --git a/sw/app/multiply/multiply.c b/sw/app/multiply/multiply.c
new file mode 100644
index 00000000..3a0b9036
--- /dev/null
+++ b/sw/app/multiply/multiply.c
@@ -0,0 +1,24 @@
+// See LICENSE for license details.
+
+// *************************************************************************
+// multiply function (c version)
+// -------------------------------------------------------------------------
+
+int multiply( int x, int y )
+{
+
+ int i;
+ int result = 0;
+
+ for (i = 0; i < 32; i++) {
+ if ((x & 0x1) == 1)
+ result = result + y;
+
+ x = x >> 1;
+ y = y << 1;
+ }
+
+ return result;
+
+}
+
diff --git a/sw/app/multiply/multiply.h b/sw/app/multiply/multiply.h
new file mode 100644
index 00000000..b2b1cf7a
--- /dev/null
+++ b/sw/app/multiply/multiply.h
@@ -0,0 +1,11 @@
+// See LICENSE for license details.
+
+//**************************************************************************
+// Software multiply function
+//--------------------------------------------------------------------------
+
+// Simple C version
+int multiply(int x, int y);
+
+// Simple assembly version
+int multiply_asm(int x, int y);
diff --git a/sw/app/multiply/multiply_gendata.pl b/sw/app/multiply/multiply_gendata.pl
new file mode 100755
index 00000000..b8d8ed5b
--- /dev/null
+++ b/sw/app/multiply/multiply_gendata.pl
@@ -0,0 +1,142 @@
+#!/usr/bin/perl -w
+#==========================================================================
+# multiply_gendata.pl
+#
+# Author : Christopher Batten (cbatten@mit.edu)
+# Date : May 9, 2005
+#
+(our $usageMsg = <<'ENDMSG') =~ s/^\#//gm;
+#
+# Simple script which creates an input data set and the reference data
+# for the multiply benchmark.
+#
+ENDMSG
+
+use strict "vars";
+use warnings;
+no warnings("once");
+use Getopt::Long;
+
+#--------------------------------------------------------------------------
+# Command line processing
+#--------------------------------------------------------------------------
+
+our %opts;
+
+sub usage()
+{
+
+ print "\n";
+ print " Usage: multiply_gendata.pl [options] \n";
+ print "\n";
+ print " Options:\n";
+ print " --help print this message\n";
+ print " --size size of input data [750]\n";
+ print " --seed random seed [1]\n";
+ print "$usageMsg";
+
+ exit();
+}
+
+sub processCommandLine()
+{
+
+ $opts{"help"} = 0;
+ $opts{"size"} = 750;
+ $opts{"seed"} = 1;
+ Getopt::Long::GetOptions( \%opts, 'help|?', 'size:i', 'seed:i' ) or usage();
+ $opts{"help"} and usage();
+
+}
+
+#--------------------------------------------------------------------------
+# Helper Functions
+#--------------------------------------------------------------------------
+
+sub printArray
+{
+ my $arrayName = $_[0];
+ my $arrayRef = $_[1];
+
+ my $numCols = 20;
+ my $arrayLen = scalar(@{$arrayRef});
+
+ print "int ".$arrayName."[DATA_SIZE] = \n";
+ print "{\n";
+
+ if ( $arrayLen <= $numCols ) {
+ print " ";
+ for ( my $i = 0; $i < $arrayLen; $i++ ) {
+ print sprintf("%3d",$arrayRef->[$i]);
+ if ( $i != $arrayLen-1 ) {
+ print ", ";
+ }
+ }
+ print "\n";
+ }
+
+ else {
+ my $numRows = int($arrayLen/$numCols);
+ for ( my $j = 0; $j < $numRows; $j++ ) {
+ print " ";
+ for ( my $i = 0; $i < $numCols; $i++ ) {
+ my $index = $j*$numCols + $i;
+ print sprintf("%3d",$arrayRef->[$index]);
+ if ( $index != $arrayLen-1 ) {
+ print ", ";
+ }
+ }
+ print "\n";
+ }
+
+ if ( $arrayLen > ($numRows*$numCols) ) {
+ print " ";
+ for ( my $i = 0; $i < ($arrayLen-($numRows*$numCols)); $i++ ) {
+ my $index = $numCols*$numRows + $i;
+ print sprintf("%3d",$arrayRef->[$index]);
+ if ( $index != $arrayLen-1 ) {
+ print ", ";
+ }
+ }
+ print "\n";
+ }
+
+ }
+
+ print "};\n\n";
+}
+
+#--------------------------------------------------------------------------
+# Main
+#--------------------------------------------------------------------------
+
+sub main()
+{
+
+ processCommandLine();
+ srand($opts{"seed"});
+
+ my @values1;
+ for ( my $i = 0; $i < $opts{"size"}; $i++ ) {
+ push( @values1, int(rand(999)) );
+ }
+
+ my @values2;
+ for ( my $i = 0; $i < $opts{"size"}; $i++ ) {
+ push( @values2, int(rand(999)) );
+ }
+
+ my @multiply;
+ for ( my $i = 0; $i < $opts{"size"}; $i++ ) {
+ $multiply[$i] = $values1[$i] * $values2[$i];
+ }
+
+ print "\n\#define DATA_SIZE ".$opts{"size"}." \n\n";
+ printArray( "input_data1", \@values1 );
+ printArray( "input_data2", \@values2 );
+ printArray( "verify_data", \@multiply );
+
+}
+
+main();
+
diff --git a/sw/app/multiply/multiply_main.c b/sw/app/multiply/multiply_main.c
new file mode 100644
index 00000000..299291ab
--- /dev/null
+++ b/sw/app/multiply/multiply_main.c
@@ -0,0 +1,66 @@
+// See LICENSE for license details.
+
+// *************************************************************************
+// multiply filter bencmark
+// -------------------------------------------------------------------------
+//
+// This benchmark tests the software multiply implemenation. The
+// input data (and reference data) should be generated using the
+// multiply_gendata.pl perl script and dumped to a file named
+// dataset1.h
+
+#include "util.h"
+
+#include "multiply.h"
+
+#define NUM_COUNTERS 2
+static uintptr_t counters[NUM_COUNTERS];
+static char* counter_names[NUM_COUNTERS];
+
+
+void setStats(int enable)
+{
+ int i = 0;
+#define READ_CTR(name) do { \
+ while (i >= NUM_COUNTERS) ; \
+ uintptr_t csr = read_csr(name); \
+ if (!enable) { csr -= counters[i]; counter_names[i] = #name; } \
+ counters[i++] = csr; \
+ } while (0)
+
+ READ_CTR(mcycle);
+ READ_CTR(minstret);
+
+#undef READ_CTR
+}
+
+//--------------------------------------------------------------------------
+// Input/Reference Data
+
+#include "dataset1.h"
+
+//--------------------------------------------------------------------------
+// Main
+
+int main( int argc, char* argv[] )
+{
+ int i;
+ int results_data[DATA_SIZE];
+
+#if PREALLOCATE
+ for (i = 0; i < DATA_SIZE; i++)
+ {
+ results_data[i] = multiply( input_data1[i], input_data2[i] );
+ }
+#endif
+
+ setStats(1);
+ for (i = 0; i < DATA_SIZE; i++)
+ {
+ results_data[i] = multiply( input_data1[i], input_data2[i] );
+ }
+ setStats(0);
+
+ // Check the results
+ return verify( DATA_SIZE, results_data, verify_data );
+}
diff --git a/sw/app/pmp/pmp.c b/sw/app/pmp/pmp.c
new file mode 100644
index 00000000..195a5757
--- /dev/null
+++ b/sw/app/pmp/pmp.c
@@ -0,0 +1,198 @@
+// See LICENSE for license details.
+
+// Test of PMP functionality.
+
+#include <stdint.h>
+#include <stdlib.h>
+#include <stdio.h>
+#include "util.h"
+
+volatile int trap_expected;
+
+#define INLINE inline __attribute__((always_inline))
+
+uintptr_t handle_trap(uintptr_t cause, uintptr_t epc, uintptr_t regs[32])
+{
+ if (cause == CAUSE_ILLEGAL_INSTRUCTION)
+ exit(0); // no PMP support
+
+ if (!trap_expected || cause != CAUSE_LOAD_ACCESS)
+ exit(1);
+ trap_expected = 0;
+ return epc + insn_len(epc);
+}
+
+#define SCRATCH RISCV_PGSIZE
+uintptr_t scratch[RISCV_PGSIZE / sizeof(uintptr_t)] __attribute__((aligned(RISCV_PGSIZE)));
+uintptr_t l1pt[RISCV_PGSIZE / sizeof(uintptr_t)] __attribute__((aligned(RISCV_PGSIZE)));
+uintptr_t l2pt[RISCV_PGSIZE / sizeof(uintptr_t)] __attribute__((aligned(RISCV_PGSIZE)));
+#if __riscv_xlen == 64
+uintptr_t l3pt[RISCV_PGSIZE / sizeof(uintptr_t)] __attribute__((aligned(RISCV_PGSIZE)));
+#else
+#define l3pt l2pt
+#endif
+
+static void init_pt()
+{
+ l1pt[0] = ((uintptr_t)l2pt >> RISCV_PGSHIFT << PTE_PPN_SHIFT) | PTE_V;
+ l3pt[SCRATCH / RISCV_PGSIZE] = ((uintptr_t)scratch >> RISCV_PGSHIFT << PTE_PPN_SHIFT) | PTE_A | PTE_D | PTE_V | PTE_R | PTE_W;
+#if __riscv_xlen == 64
+ l2pt[0] = ((uintptr_t)l3pt >> RISCV_PGSHIFT << PTE_PPN_SHIFT) | PTE_V;
+ uintptr_t vm_choice = SATP_MODE_SV39;
+#else
+ uintptr_t vm_choice = SATP_MODE_SV32;
+#endif
+ write_csr(sptbr, ((uintptr_t)l1pt >> RISCV_PGSHIFT) |
+ (vm_choice * (SATP_MODE & ~(SATP_MODE<<1))));
+ write_csr(pmpcfg0, (PMP_NAPOT | PMP_R) << 16);
+ write_csr(pmpaddr2, -1);
+}
+
+INLINE uintptr_t va2pa(uintptr_t va)
+{
+ if (va < SCRATCH || va >= SCRATCH + RISCV_PGSIZE)
+ exit(3);
+ return va - SCRATCH + (uintptr_t)scratch;
+}
+
+#define GRANULE (1UL << PMP_SHIFT)
+
+typedef struct {
+ uintptr_t cfg;
+ uintptr_t a0;
+ uintptr_t a1;
+} pmpcfg_t;
+
+INLINE int pmp_ok(pmpcfg_t p, uintptr_t addr, uintptr_t size)
+{
+ if ((p.cfg & PMP_A) == 0)
+ return 1;
+
+ if ((p.cfg & PMP_A) != PMP_TOR) {
+ uintptr_t range = 1;
+
+ if ((p.cfg & PMP_A) == PMP_NAPOT) {
+ range <<= 1;
+ for (uintptr_t i = 1; i; i <<= 1) {
+ if ((p.a1 & i) == 0)
+ break;
+ p.a1 &= ~i;
+ range <<= 1;
+ }
+ }
+
+ p.a0 = p.a1;
+ p.a1 = p.a0 + range;
+ }
+
+ p.a0 *= GRANULE;
+ p.a1 *= GRANULE;
+ addr = va2pa(addr);
+
+ uintptr_t hits = 0;
+ for (uintptr_t i = 0; i < size; i += GRANULE) {
+ if (p.a0 <= addr + i && addr + i < p.a1)
+ hits += GRANULE;
+ }
+
+ return hits == 0 || hits >= size;
+}
+
+INLINE void test_one(uintptr_t addr, uintptr_t size)
+{
+ uintptr_t new_mstatus = (read_csr(mstatus) & ~MSTATUS_MPP) | (MSTATUS_MPP & (MSTATUS_MPP >> 1)) | MSTATUS_MPRV;
+ switch (size) {
+ case 1: asm volatile ("csrrw %0, mstatus, %0; lb x0, (%1); csrw mstatus, %0" : "+&r" (new_mstatus) : "r" (addr)); break;
+ case 2: asm volatile ("csrrw %0, mstatus, %0; lh x0, (%1); csrw mstatus, %0" : "+&r" (new_mstatus) : "r" (addr)); break;
+ case 4: asm volatile ("csrrw %0, mstatus, %0; lw x0, (%1); csrw mstatus, %0" : "+&r" (new_mstatus) : "r" (addr)); break;
+#if __riscv_xlen >= 64
+ case 8: asm volatile ("csrrw %0, mstatus, %0; ld x0, (%1); csrw mstatus, %0" : "+&r" (new_mstatus) : "r" (addr)); break;
+#endif
+ default: __builtin_unreachable();
+ }
+}
+
+INLINE void test_all_sizes(pmpcfg_t p, uintptr_t addr)
+{
+ for (size_t size = 1; size <= sizeof(uintptr_t); size *= 2) {
+ if (addr & (size - 1))
+ continue;
+ trap_expected = !pmp_ok(p, addr, size);
+ test_one(addr, size);
+ if (trap_expected)
+ exit(2);
+ }
+}
+
+INLINE void test_range_once(pmpcfg_t p, uintptr_t base, uintptr_t range)
+{
+ for (uintptr_t addr = base; addr < base + range; addr += GRANULE)
+ test_all_sizes(p, addr);
+}
+
+INLINE pmpcfg_t set_pmp(pmpcfg_t p)
+{
+ uintptr_t cfg0 = read_csr(pmpcfg0);
+ write_csr(pmpcfg0, cfg0 & ~0xff00);
+ write_csr(pmpaddr0, p.a0);
+ write_csr(pmpaddr1, p.a1);
+ write_csr(pmpcfg0, ((p.cfg << 8) & 0xff00) | (cfg0 & ~0xff00));
+ asm volatile ("sfence.vma" ::: "memory");
+ return p;
+}
+
+INLINE pmpcfg_t set_pmp_range(uintptr_t base, uintptr_t range)
+{
+ pmpcfg_t p;
+ p.cfg = PMP_TOR | PMP_R;
+ p.a0 = base >> PMP_SHIFT;
+ p.a1 = (base + range) >> PMP_SHIFT;
+ return set_pmp(p);
+}
+
+INLINE pmpcfg_t set_pmp_napot(uintptr_t base, uintptr_t range)
+{
+ pmpcfg_t p;
+ p.cfg = PMP_R | (range > GRANULE ? PMP_NAPOT : PMP_NA4);
+ p.a0 = 0;
+ p.a1 = (base + (range/2 - 1)) >> PMP_SHIFT;
+ return set_pmp(p);
+}
+
+static void test_range(uintptr_t addr, uintptr_t range)
+{
+ pmpcfg_t p = set_pmp_range(va2pa(addr), range);
+ test_range_once(p, addr, range);
+
+ if ((range & (range - 1)) == 0 && (addr & (range - 1)) == 0) {
+ p = set_pmp_napot(va2pa(addr), range);
+ test_range_once(p, addr, range);
+ }
+}
+
+static void test_ranges(uintptr_t addr, uintptr_t size)
+{
+ for (uintptr_t range = GRANULE; range <= size; range += GRANULE)
+ test_range(addr, range);
+}
+
+static void exhaustive_test(uintptr_t addr, uintptr_t size)
+{
+ for (uintptr_t base = addr; base < addr + size; base += GRANULE)
+ test_ranges(base, size - (base - addr));
+}
+
+int main()
+{
+ init_pt();
+
+ const int max_exhaustive = 32;
+ exhaustive_test(SCRATCH, max_exhaustive);
+ exhaustive_test(SCRATCH + RISCV_PGSIZE - max_exhaustive, max_exhaustive);
+
+ test_range(SCRATCH, RISCV_PGSIZE);
+ test_range(SCRATCH, RISCV_PGSIZE / 2);
+ test_range(SCRATCH + RISCV_PGSIZE / 2, RISCV_PGSIZE / 2);
+
+ return 0;
+}
diff --git a/sw/app/qsort/dataset1.h b/sw/app/qsort/dataset1.h
new file mode 100644
index 00000000..dd1c6340
--- /dev/null
+++ b/sw/app/qsort/dataset1.h
@@ -0,0 +1,219 @@
+// See LICENSE for license details.
+
+
+#define DATA_SIZE 2048
+
+type input_data[DATA_SIZE] =
+{
+ 89400484, 976015092, 1792756324, 721524505, 1214379246, 3794415, 402845420, 2126940990, 1611680320, 786566648, 754215794, 1231249235, 284658041, 137796456, 2041942843, 329767814, 1255524953, 465119445, 1731949250, 301663421,
+ 1335861008, 452888789, 14125900, 1231149357, 2002881120, 730845665, 1913581092, 1275331596, 843738737, 1931282005, 1492488573, 490920543, 2066865713, 25885333, 238278880, 1898582764, 250731366, 1612593993, 637659983, 1388759892,
+ 916073297, 1075762632, 675549432, 937987129, 1417415680, 1508705426, 1663890071, 1746476698, 686797873, 2109530615, 1459500136, 324215873, 1881253854, 1496277718, 810387144, 1212974417, 1020037994, 585169793, 2017191527, 556328195,
+ 1160036198, 1391095995, 1223583276, 1094283114, 436580096, 190215907, 603159718, 1513255537, 1631935240, 1440145706, 1303736105, 806638567, 1100041120, 1185825535, 1414141069, 2014090929, 419476096, 1273955724, 175753599, 1223475486,
+ 574236644, 2046759770, 492507266, 1721767511, 726141970, 1256152080, 2029909894, 1382429941, 1939683211, 791188057, 519699747, 1051184301, 1962689485, 706913763, 1776471922, 672906535, 2005817027, 1274190723, 2119425672, 835063788,
+ 421198539, 1169327477, 2064145552, 1396662140, 1218522465, 2105638337, 754247044, 2143968639, 1395289708, 1750443194, 1412540552, 170281493, 389233190, 448284065, 240618723, 2145930822, 1846605728, 1353999206, 140536987, 1821559709,
+ 619972089, 1514278798, 750919339, 2143343312, 304427548, 545066288, 1946004194, 1538069400, 1904770864, 924541465, 567779677, 893302687, 1239665569, 1157666831, 2105814934, 1505475223, 1636203720, 9736243, 518073650, 1063743848,
+ 1029176122, 215018112, 1073871430, 1858933377, 866478506, 1491477359, 477407584, 895562064, 954441852, 638167485, 1550159640, 614612685, 1453397990, 1334857284, 683536723, 168771888, 481561285, 755798022, 2016161810, 1162679490,
+ 619428858, 1390306889, 256860662, 365275089, 1322281086, 1134185180, 1302724177, 621921213, 837554186, 1711761015, 754896618, 1723143470, 978247260, 1548804416, 598016845, 1631405417, 790929190, 1602517354, 770957259, 198186681,
+ 1256015513, 2126029304, 135012885, 583112200, 2118203528, 1834388383, 866964848, 1695191950, 745183293, 1143511498, 1112731797, 478721193, 1202162389, 991159735, 1952364329, 519344323, 1667102296, 770412991, 548632788, 714042223,
+ 1674045273, 1471598258, 1286989824, 1590771096, 308832070, 959354209, 72802865, 670621648, 269167950, 1598436917, 2023498746, 1198213061, 2006856683, 1029832956, 1719009954, 1198254803, 1188748563, 1989240516, 927524181, 1711765426,
+ 1394929399, 769005536, 2047006719, 1915435344, 618681206, 1431814151, 42021322, 1106678970, 107160610, 1199317660, 185592115, 1870214195, 205008108, 1834318089, 948686793, 946311527, 1262399341, 131405125, 1321897861, 1459138745,
+ 821481684, 852388468, 603907009, 20643769, 1737931879, 37141933, 2088576982, 366700722, 1761289401, 625991894, 741078359, 817417567, 969305448, 1152416171, 1101933540, 399456957, 2074896270, 1971484382, 747592875, 1160333307,
+ 1738353358, 2113434968, 1896952705, 1908093581, 1155544307, 117766047, 2034767768, 1316120929, 1507433029, 2045407567, 765386206, 1031625002, 1220915309, 325667019, 1916602098, 16411608, 47463938, 1379995885, 1221108420, 721046824,
+ 1431492783, 1569479928, 909415369, 204514903, 933673987, 1565700239, 341674967, 602907378, 5309142, 849489374, 180599971, 1480437960, 532467027, 1958396887, 106223060, 1025117441, 935689637, 1752088215, 1704561346, 1568395337,
+ 1868289345, 569949159, 1045658065, 274746405, 890461390, 507848158, 793505636, 460893030, 1179525294, 388855203, 1113693824, 13887419, 1909681194, 1082499152, 1466632447, 1281443423, 612289854, 373305330, 568652142, 1383640563,
+ 1073695485, 745777837, 624939139, 1289308008, 1928550562, 148113917, 462743614, 1826880531, 1571598133, 1415390230, 1480273562, 1331593955, 540006359, 261556590, 1690167792, 283430575, 1194709162, 1781233744, 649754857, 1434046375,
+ 1135793759, 932423857, 1170759710, 1048943084, 692845661, 1620562432, 2036750157, 270410557, 617995659, 1347284277, 1771614266, 30992839, 655445946, 22762734, 1695617313, 867628573, 1577034674, 227870124, 2063408339, 1512163910,
+ 787913688, 1758748737, 1553547892, 2072440819, 632611704, 873623623, 2097057488, 1879635915, 1404727477, 1840896199, 1609955669, 186112992, 196401930, 130001148, 814302898, 1420810050, 226906236, 1435859758, 221330186, 329049266,
+ 820933470, 260792255, 1401058771, 210908782, 1774652096, 886978116, 1807085904, 508041515, 767233910, 26687179, 318750634, 910677024, 117260224, 2074840378, 301350822, 464795711, 2053899162, 1335298265, 737518341, 777433215,
+ 1147341731, 1981481446, 1628389501, 1537459540, 1121432739, 1392162662, 1800522575, 644293952, 1273223611, 1906345724, 28256901, 1467376771, 372465453, 78348530, 135678410, 1061864942, 260267972, 1184561748, 287497702, 1154842325,
+ 1629914848, 2084953915, 799717076, 1382484003, 2045821218, 933603111, 84924801, 892939912, 279252402, 651750790, 238566180, 942977997, 1822612008, 1849675857, 939497524, 436630343, 549253917, 1028937430, 579174666, 2124749673,
+ 880456526, 1451442832, 1350653461, 1546104436, 858045289, 2129513521, 1181191604, 727587915, 1619598456, 969076419, 1212628403, 1361078114, 368541415, 333906659, 41714278, 1390274260, 1563717683, 973769771, 1078197595, 918378387,
+ 1672192305, 1094531762, 92620223, 2125958841, 1620803320, 915948205, 174965839, 27377406, 435236973, 1038830638, 1834161399, 305750851, 330474090, 730422541, 1634445325, 840106059, 767880329, 109526756, 2027814180, 367923081,
+ 1983379601, 1293091635, 705851791, 226723092, 1067775613, 2082760612, 951663731, 260670135, 1111213862, 1891630185, 1379259015, 176024101, 594814862, 1870859970, 1689946986, 1290969161, 244975305, 1296857499, 1811088032, 1873900475,
+ 1949896838, 1907793490, 592006699, 1312471120, 509744705, 869853078, 70894786, 503368137, 1686479103, 1602967659, 1214950832, 1131661227, 768185796, 592234826, 1727583308, 949222447, 1760851607, 487888229, 1614780688, 1618378831,
+ 602368560, 2028116487, 183679578, 1561251584, 986240059, 1525451290, 977907387, 432609664, 1528031307, 116766659, 987761406, 1630293700, 90063199, 114202152, 543952312, 855107605, 812328969, 88823122, 1092881031, 304131252,
+ 1505022272, 894769708, 1849495275, 1607515830, 1032748996, 472872107, 1593359038, 1027760887, 1074205225, 1657001479, 1524491858, 387061281, 107095939, 1038018856, 798445606, 1486594282, 1878434988, 1558695709, 2033003588, 373226849,
+ 2133066804, 399991238, 1132597050, 1965358941, 1551661799, 3522194, 935939763, 2070467093, 500734709, 533101409, 1068798385, 998931662, 1500102591, 779093898, 66579049, 1121960111, 749415493, 502323961, 538932155, 259768753,
+ 753296935, 87897457, 539429964, 1675300017, 1232992084, 420106224, 1685350721, 346598567, 1610244183, 1597506096, 1079859867, 944382193, 1770497338, 764935753, 1776794410, 866854601, 365854486, 304211060, 344860208, 1361012693,
+ 1450892344, 622170346, 70003859, 1681866717, 435288306, 687941098, 308700094, 1367731096, 1834285819, 255226842, 193873940, 1833603743, 848402819, 152273285, 231181585, 1754447491, 1838218199, 834410115, 229905664, 2052321529,
+ 338532526, 77482422, 12937811, 35859252, 1645969422, 1501181424, 438711458, 1496078411, 419109342, 1455756978, 1234944834, 1287171290, 470090505, 1900162831, 1130850177, 1772760484, 381571915, 1605369007, 514914429, 994291574,
+ 1502557594, 1099847920, 1627355806, 1148699143, 1519017268, 946489895, 106595511, 921573402, 181567810, 1575380740, 1719573683, 1561730727, 1920182565, 1510133268, 1102603775, 1175885101, 802730854, 185979744, 1058937717, 1716853034,
+ 31596852, 462857778, 1335652095, 47036070, 178901145, 1399673078, 222529745, 128036841, 1708126014, 923768127, 1980923963, 1413860940, 1382551511, 208160226, 1892370478, 2091626028, 1793190956, 1417601340, 515811664, 2076612603,
+ 993525189, 1127173529, 245334962, 134453363, 1206302514, 1344125357, 1139159604, 651536866, 22136821, 1536213818, 2143324534, 879878312, 1944679691, 119285206, 832081018, 1566878909, 876130333, 656954306, 226726100, 937976428,
+ 1202009920, 1938258683, 2014129292, 1274436639, 1102423908, 1485740112, 879552408, 1712269139, 650513248, 1068587688, 434850545, 382422699, 919736727, 2022291557, 1319798607, 2139976479, 772059719, 1033910502, 1120963974, 340231765,
+ 1471131758, 1767380006, 47452797, 1313871880, 399114073, 1462921857, 671848647, 31574181, 230340298, 239990424, 590690783, 1714295540, 833019845, 398244682, 522160389, 900852, 1045627895, 1545555937, 226986415, 208433088,
+ 1502480836, 1611500622, 1933923245, 1588715179, 1655277291, 1749972876, 1386258142, 935490932, 173822937, 702380578, 348131466, 81402251, 875481479, 72939206, 2033828953, 1302272656, 64795664, 2010549018, 1652108025, 58217952,
+ 1871684562, 190536346, 244709448, 949010757, 320137025, 729474445, 133790520, 740536012, 316479300, 1191513656, 1802197319, 785398708, 1816641611, 2052328978, 930367387, 1374125186, 303845878, 852835634, 454359988, 2131761201,
+ 1757028186, 536063430, 1765354961, 726869128, 1209784819, 1790557628, 783427298, 2094085507, 1323798820, 846127236, 1065481253, 572240371, 1745543275, 1011417836, 1970797151, 748527394, 343119399, 723323690, 925975225, 901789102,
+ 1726987516, 535828217, 387611445, 464171383, 1170510314, 1166227930, 1807172811, 1942089394, 985305323, 1368235387, 1691486500, 1568900638, 1876255297, 1249183285, 1710305778, 1763785295, 1733366374, 1444076976, 1629633514, 2105321510,
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+
+type verify_data[DATA_SIZE] =
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+ 1924603748, 1926717418, 1927367009, 1928309762, 1928550562, 1930662128, 1930880552, 1931282005, 1931493432, 1932108837, 1933532372, 1933923245, 1935271536, 1936668087, 1938258683, 1939683211, 1942089394, 1943137808, 1943651015, 1944679691,
+ 1945110368, 1946004194, 1948121717, 1949896838, 1950124297, 1951228823, 1952177514, 1952364329, 1952805989, 1953450944, 1953919896, 1955436051, 1957728250, 1957877704, 1958396887, 1959222232, 1959292396, 1961619988, 1961647235, 1962689485,
+ 1963053072, 1965358941, 1965855212, 1967705762, 1968608155, 1968623233, 1969729134, 1970797151, 1971484382, 1971654864, 1977865396, 1980923963, 1981481446, 1983379601, 1984143440, 1984152603, 1985895474, 1986921372, 1989240516, 1992941115,
+ 1994402695, 1997381015, 2001056977, 2002881120, 2004664325, 2004770236, 2005021017, 2005653265, 2005817027, 2006320950, 2006856683, 2009244921, 2010549018, 2011827638, 2014090929, 2014129292, 2015847175, 2016161810, 2016464961, 2017191527,
+ 2018336444, 2022291557, 2022973269, 2023498746, 2024853642, 2027445678, 2027814180, 2027828650, 2027909489, 2028116487, 2029133999, 2029909894, 2033003588, 2033828953, 2034767768, 2036061488, 2036750157, 2037182006, 2038925801, 2039012903,
+ 2041942843, 2042861943, 2044016080, 2045407567, 2045821218, 2046759770, 2047006719, 2047769687, 2048205721, 2048560397, 2049698913, 2052321529, 2052328978, 2052343947, 2053899162, 2054212564, 2055783490, 2060969286, 2061144988, 2063408339,
+ 2064145552, 2064308502, 2066440075, 2066865713, 2067100479, 2067499753, 2068343250, 2068743361, 2069178089, 2070467093, 2072440819, 2073482870, 2074840378, 2074896270, 2076612603, 2077667592, 2078528215, 2079492652, 2080735477, 2081544705,
+ 2082760612, 2084953915, 2085323316, 2087660971, 2088576982, 2088786920, 2088955494, 2089981667, 2090025563, 2090543533, 2090570016, 2090684129, 2091626028, 2093472294, 2094085507, 2094159153, 2094591332, 2094864173, 2097057488, 2098829619,
+ 2100497812, 2103236982, 2105321510, 2105638337, 2105718728, 2105814934, 2108439398, 2109052886, 2109530615, 2109851473, 2113434968, 2114587535, 2115445751, 2116495484, 2117880007, 2118203528, 2118433006, 2118805956, 2118821565, 2119425672,
+ 2122262571, 2122852959, 2123379476, 2124749673, 2125958841, 2126029304, 2126940990, 2126963607, 2128078174, 2128826472, 2129513521, 2129930580, 2130252471, 2130879949, 2131761201, 2131797509, 2133066804, 2135673182, 2139976479, 2140091269,
+ 2140756121, 2141591317, 2142357746, 2143324534, 2143343312, 2143968639, 2145073408, 2145930822
+};
+
diff --git a/sw/app/qsort/qsort_gendata.pl b/sw/app/qsort/qsort_gendata.pl
new file mode 100755
index 00000000..92fc8fa0
--- /dev/null
+++ b/sw/app/qsort/qsort_gendata.pl
@@ -0,0 +1,132 @@
+#!/usr/bin/perl -w
+#==========================================================================
+# qsort_gendata.pl
+#
+# Author : Christopher Batten (cbatten@mit.edu)
+# Date : April 29, 2005
+#
+(our $usageMsg = <<'ENDMSG') =~ s/^\#//gm;
+#
+# Simple script which creates an input data set and the reference data
+# for the qsort benchmark.
+#
+ENDMSG
+
+use strict "vars";
+use warnings;
+no warnings("once");
+use Getopt::Long;
+
+#--------------------------------------------------------------------------
+# Command line processing
+#--------------------------------------------------------------------------
+
+our %opts;
+
+sub usage()
+{
+
+ print "\n";
+ print " Usage: qsort_gendata.pl [options] \n";
+ print "\n";
+ print " Options:\n";
+ print " --help print this message\n";
+ print " --size size of input data [250]\n";
+ print " --seed random seed [1]\n";
+ print "$usageMsg";
+
+ exit();
+}
+
+sub processCommandLine()
+{
+
+ $opts{"help"} = 0;
+ $opts{"size"} = 250;
+ $opts{"seed"} = 1;
+ Getopt::Long::GetOptions( \%opts, 'help|?', 'size:i', 'seed:i' ) or usage();
+ $opts{"help"} and usage();
+
+}
+
+#--------------------------------------------------------------------------
+# Helper Functions
+#--------------------------------------------------------------------------
+
+sub printArray
+{
+ my $arrayName = $_[0];
+ my $arrayRef = $_[1];
+
+ my $numCols = 20;
+ my $arrayLen = scalar(@{$arrayRef});
+
+ print "type ".$arrayName."[DATA_SIZE] = \n";
+ print "{\n";
+
+ if ( $arrayLen <= $numCols ) {
+ print " ";
+ for ( my $i = 0; $i < $arrayLen; $i++ ) {
+ print sprintf("%3d",$arrayRef->[$i]);
+ if ( $i != $arrayLen-1 ) {
+ print ", ";
+ }
+ }
+ print "\n";
+ }
+
+ else {
+ my $numRows = int($arrayLen/$numCols);
+ for ( my $j = 0; $j < $numRows; $j++ ) {
+ print " ";
+ for ( my $i = 0; $i < $numCols; $i++ ) {
+ my $index = $j*$numCols + $i;
+ print sprintf("%3d",$arrayRef->[$index]);
+ if ( $index != $arrayLen-1 ) {
+ print ", ";
+ }
+ }
+ print "\n";
+ }
+
+ if ( $arrayLen > ($numRows*$numCols) ) {
+ print " ";
+ for ( my $i = 0; $i < ($arrayLen-($numRows*$numCols)); $i++ ) {
+ my $index = $numCols*$numRows + $i;
+ print sprintf("%3d",$arrayRef->[$index]);
+ if ( $index != $arrayLen-1 ) {
+ print ", ";
+ }
+ }
+ print "\n";
+ }
+
+ }
+
+ print "};\n\n";
+}
+
+#--------------------------------------------------------------------------
+# Main
+#--------------------------------------------------------------------------
+
+sub main()
+{
+
+ processCommandLine();
+ srand($opts{"seed"});
+
+ my @values;
+ for ( my $i = 0; $i < $opts{"size"}; $i++ ) {
+ push( @values, int(rand((1<<31)-1)) );
+ }
+ my @sorted = sort { $a <=> $b } @values;
+
+ print "\n\#define DATA_SIZE ".$opts{"size"}." \n\n";
+ printArray( "input_data", \@values );
+ printArray( "verify_data", \@sorted );
+
+}
+
+main();
+
diff --git a/sw/app/qsort/qsort_main.c b/sw/app/qsort/qsort_main.c
new file mode 100644
index 00000000..c4cd061c
--- /dev/null
+++ b/sw/app/qsort/qsort_main.c
@@ -0,0 +1,175 @@
+// See LICENSE for license details.
+
+//**************************************************************************
+// Quicksort benchmark
+//--------------------------------------------------------------------------
+//
+// This benchmark uses quicksort to sort an array of integers. The
+// implementation is largely adapted from Numerical Recipes for C. The
+// input data (and reference data) should be generated using the
+// qsort_gendata.pl perl script and dumped to a file named
+// dataset1.h.
+
+#include "util.h"
+#include <string.h>
+#include <assert.h>
+
+
+#define NUM_COUNTERS 2
+static uintptr_t counters[NUM_COUNTERS];
+static char* counter_names[NUM_COUNTERS];
+
+
+void setStats(int enable)
+{
+ int i = 0;
+#define READ_CTR(name) do { \
+ while (i >= NUM_COUNTERS) ; \
+ uintptr_t csr = read_csr(name); \
+ if (!enable) { csr -= counters[i]; counter_names[i] = #name; } \
+ counters[i++] = csr; \
+ } while (0)
+
+ READ_CTR(mcycle);
+ READ_CTR(minstret);
+
+#undef READ_CTR
+}
+
+// The INSERTION_THRESHOLD is the size of the subarray when the
+// algorithm switches to using an insertion sort instead of
+// quick sort.
+
+#define INSERTION_THRESHOLD 10
+
+// NSTACK is the required auxiliary storage.
+// It must be at least 2*lg(DATA_SIZE)
+
+#define NSTACK 50
+
+//--------------------------------------------------------------------------
+// Input/Reference Data
+
+#define type int
+#include "dataset1.h"
+
+// Swap macro for swapping two values.
+
+#define SWAP(a,b) do { typeof(a) temp=(a);(a)=(b);(b)=temp; } while (0)
+#define SWAP_IF_GREATER(a, b) do { if ((a) > (b)) SWAP(a, b); } while (0)
+
+//--------------------------------------------------------------------------
+// Quicksort function
+
+static void insertion_sort(size_t n, type arr[])
+{
+ type *i, *j;
+ type value;
+ for (i = arr+1; i < arr+n; i++)
+ {
+ value = *i;
+ j = i;
+ while (value < *(j-1))
+ {
+ *j = *(j-1);
+ if (--j == arr)
+ break;
+ }
+ *j = value;
+ }
+}
+
+static void selection_sort(size_t n, type arr[])
+{
+ for (type* i = arr; i < arr+n-1; i++)
+ for (type* j = i+1; j < arr+n; j++)
+ SWAP_IF_GREATER(*i, *j);
+}
+
+void sort(size_t n, type arr[])
+{
+ type* ir = arr+n;
+ type* l = arr+1;
+ type* stack[NSTACK];
+ type** stackp = stack;
+
+ for (;;)
+ {
+ // Insertion sort when subarray small enough.
+ if ( ir-l < INSERTION_THRESHOLD )
+ {
+ insertion_sort(ir - l + 1, l - 1);
+
+ if ( stackp == stack ) break;
+
+ // Pop stack and begin a new round of partitioning.
+ ir = *stackp--;
+ l = *stackp--;
+ }
+ else
+ {
+ // Choose median of left, center, and right elements as
+ // partitioning element a. Also rearrange so that a[l-1] <= a[l] <= a[ir-].
+ SWAP(arr[((l-arr) + (ir-arr))/2-1], l[0]);
+ SWAP_IF_GREATER(l[-1], ir[-1]);
+ SWAP_IF_GREATER(l[0], ir[-1]);
+ SWAP_IF_GREATER(l[-1], l[0]);
+
+ // Initialize pointers for partitioning.
+ type* i = l+1;
+ type* j = ir;
+
+ // Partitioning element.
+ type a = l[0];
+
+ for (;;) { // Beginning of innermost loop.
+ while (*i++ < a); // Scan up to find element > a.
+ while (*(j-- - 2) > a); // Scan down to find element < a.
+ if (j < i) break; // Pointers crossed. Partitioning complete.
+ SWAP(i[-1], j[-1]); // Exchange elements.
+ } // End of innermost loop.
+
+ // Insert partitioning element.
+ l[0] = j[-1];
+ j[-1] = a;
+ stackp += 2;
+
+ // Push pointers to larger subarray on stack,
+ // process smaller subarray immediately.
+
+ if ( ir-i+1 >= j-l )
+ {
+ stackp[0] = ir;
+ stackp[-1] = i;
+ ir = j-1;
+ }
+ else
+ {
+ stackp[0] = j-1;
+ stackp[-1] = l;
+ l = i;
+ }
+ }
+ }
+}
+
+//--------------------------------------------------------------------------
+// Main
+
+int main( int argc, char* argv[] )
+{
+#if PREALLOCATE
+ // If needed we preallocate everything in the caches
+ sort(DATA_SIZE, verify_data);
+ if (verify(DATA_SIZE, input_data, input_data))
+ return 1;
+#endif
+
+ // Do the sort
+ setStats(1);
+ sort( DATA_SIZE, input_data );
+ setStats(0);
+
+ // Check the results
+ return verify( DATA_SIZE, input_data, verify_data );
+}
diff --git a/sw/app/rsort/dataset1.h b/sw/app/rsort/dataset1.h
new file mode 100644
index 00000000..dd1c6340
--- /dev/null
+++ b/sw/app/rsort/dataset1.h
@@ -0,0 +1,219 @@
+// See LICENSE for license details.
+
+
+#define DATA_SIZE 2048
+
+type input_data[DATA_SIZE] =
+{
+ 89400484, 976015092, 1792756324, 721524505, 1214379246, 3794415, 402845420, 2126940990, 1611680320, 786566648, 754215794, 1231249235, 284658041, 137796456, 2041942843, 329767814, 1255524953, 465119445, 1731949250, 301663421,
+ 1335861008, 452888789, 14125900, 1231149357, 2002881120, 730845665, 1913581092, 1275331596, 843738737, 1931282005, 1492488573, 490920543, 2066865713, 25885333, 238278880, 1898582764, 250731366, 1612593993, 637659983, 1388759892,
+ 916073297, 1075762632, 675549432, 937987129, 1417415680, 1508705426, 1663890071, 1746476698, 686797873, 2109530615, 1459500136, 324215873, 1881253854, 1496277718, 810387144, 1212974417, 1020037994, 585169793, 2017191527, 556328195,
+ 1160036198, 1391095995, 1223583276, 1094283114, 436580096, 190215907, 603159718, 1513255537, 1631935240, 1440145706, 1303736105, 806638567, 1100041120, 1185825535, 1414141069, 2014090929, 419476096, 1273955724, 175753599, 1223475486,
+ 574236644, 2046759770, 492507266, 1721767511, 726141970, 1256152080, 2029909894, 1382429941, 1939683211, 791188057, 519699747, 1051184301, 1962689485, 706913763, 1776471922, 672906535, 2005817027, 1274190723, 2119425672, 835063788,
+ 421198539, 1169327477, 2064145552, 1396662140, 1218522465, 2105638337, 754247044, 2143968639, 1395289708, 1750443194, 1412540552, 170281493, 389233190, 448284065, 240618723, 2145930822, 1846605728, 1353999206, 140536987, 1821559709,
+ 619972089, 1514278798, 750919339, 2143343312, 304427548, 545066288, 1946004194, 1538069400, 1904770864, 924541465, 567779677, 893302687, 1239665569, 1157666831, 2105814934, 1505475223, 1636203720, 9736243, 518073650, 1063743848,
+ 1029176122, 215018112, 1073871430, 1858933377, 866478506, 1491477359, 477407584, 895562064, 954441852, 638167485, 1550159640, 614612685, 1453397990, 1334857284, 683536723, 168771888, 481561285, 755798022, 2016161810, 1162679490,
+ 619428858, 1390306889, 256860662, 365275089, 1322281086, 1134185180, 1302724177, 621921213, 837554186, 1711761015, 754896618, 1723143470, 978247260, 1548804416, 598016845, 1631405417, 790929190, 1602517354, 770957259, 198186681,
+ 1256015513, 2126029304, 135012885, 583112200, 2118203528, 1834388383, 866964848, 1695191950, 745183293, 1143511498, 1112731797, 478721193, 1202162389, 991159735, 1952364329, 519344323, 1667102296, 770412991, 548632788, 714042223,
+ 1674045273, 1471598258, 1286989824, 1590771096, 308832070, 959354209, 72802865, 670621648, 269167950, 1598436917, 2023498746, 1198213061, 2006856683, 1029832956, 1719009954, 1198254803, 1188748563, 1989240516, 927524181, 1711765426,
+ 1394929399, 769005536, 2047006719, 1915435344, 618681206, 1431814151, 42021322, 1106678970, 107160610, 1199317660, 185592115, 1870214195, 205008108, 1834318089, 948686793, 946311527, 1262399341, 131405125, 1321897861, 1459138745,
+ 821481684, 852388468, 603907009, 20643769, 1737931879, 37141933, 2088576982, 366700722, 1761289401, 625991894, 741078359, 817417567, 969305448, 1152416171, 1101933540, 399456957, 2074896270, 1971484382, 747592875, 1160333307,
+ 1738353358, 2113434968, 1896952705, 1908093581, 1155544307, 117766047, 2034767768, 1316120929, 1507433029, 2045407567, 765386206, 1031625002, 1220915309, 325667019, 1916602098, 16411608, 47463938, 1379995885, 1221108420, 721046824,
+ 1431492783, 1569479928, 909415369, 204514903, 933673987, 1565700239, 341674967, 602907378, 5309142, 849489374, 180599971, 1480437960, 532467027, 1958396887, 106223060, 1025117441, 935689637, 1752088215, 1704561346, 1568395337,
+ 1868289345, 569949159, 1045658065, 274746405, 890461390, 507848158, 793505636, 460893030, 1179525294, 388855203, 1113693824, 13887419, 1909681194, 1082499152, 1466632447, 1281443423, 612289854, 373305330, 568652142, 1383640563,
+ 1073695485, 745777837, 624939139, 1289308008, 1928550562, 148113917, 462743614, 1826880531, 1571598133, 1415390230, 1480273562, 1331593955, 540006359, 261556590, 1690167792, 283430575, 1194709162, 1781233744, 649754857, 1434046375,
+ 1135793759, 932423857, 1170759710, 1048943084, 692845661, 1620562432, 2036750157, 270410557, 617995659, 1347284277, 1771614266, 30992839, 655445946, 22762734, 1695617313, 867628573, 1577034674, 227870124, 2063408339, 1512163910,
+ 787913688, 1758748737, 1553547892, 2072440819, 632611704, 873623623, 2097057488, 1879635915, 1404727477, 1840896199, 1609955669, 186112992, 196401930, 130001148, 814302898, 1420810050, 226906236, 1435859758, 221330186, 329049266,
+ 820933470, 260792255, 1401058771, 210908782, 1774652096, 886978116, 1807085904, 508041515, 767233910, 26687179, 318750634, 910677024, 117260224, 2074840378, 301350822, 464795711, 2053899162, 1335298265, 737518341, 777433215,
+ 1147341731, 1981481446, 1628389501, 1537459540, 1121432739, 1392162662, 1800522575, 644293952, 1273223611, 1906345724, 28256901, 1467376771, 372465453, 78348530, 135678410, 1061864942, 260267972, 1184561748, 287497702, 1154842325,
+ 1629914848, 2084953915, 799717076, 1382484003, 2045821218, 933603111, 84924801, 892939912, 279252402, 651750790, 238566180, 942977997, 1822612008, 1849675857, 939497524, 436630343, 549253917, 1028937430, 579174666, 2124749673,
+ 880456526, 1451442832, 1350653461, 1546104436, 858045289, 2129513521, 1181191604, 727587915, 1619598456, 969076419, 1212628403, 1361078114, 368541415, 333906659, 41714278, 1390274260, 1563717683, 973769771, 1078197595, 918378387,
+ 1672192305, 1094531762, 92620223, 2125958841, 1620803320, 915948205, 174965839, 27377406, 435236973, 1038830638, 1834161399, 305750851, 330474090, 730422541, 1634445325, 840106059, 767880329, 109526756, 2027814180, 367923081,
+ 1983379601, 1293091635, 705851791, 226723092, 1067775613, 2082760612, 951663731, 260670135, 1111213862, 1891630185, 1379259015, 176024101, 594814862, 1870859970, 1689946986, 1290969161, 244975305, 1296857499, 1811088032, 1873900475,
+ 1949896838, 1907793490, 592006699, 1312471120, 509744705, 869853078, 70894786, 503368137, 1686479103, 1602967659, 1214950832, 1131661227, 768185796, 592234826, 1727583308, 949222447, 1760851607, 487888229, 1614780688, 1618378831,
+ 602368560, 2028116487, 183679578, 1561251584, 986240059, 1525451290, 977907387, 432609664, 1528031307, 116766659, 987761406, 1630293700, 90063199, 114202152, 543952312, 855107605, 812328969, 88823122, 1092881031, 304131252,
+ 1505022272, 894769708, 1849495275, 1607515830, 1032748996, 472872107, 1593359038, 1027760887, 1074205225, 1657001479, 1524491858, 387061281, 107095939, 1038018856, 798445606, 1486594282, 1878434988, 1558695709, 2033003588, 373226849,
+ 2133066804, 399991238, 1132597050, 1965358941, 1551661799, 3522194, 935939763, 2070467093, 500734709, 533101409, 1068798385, 998931662, 1500102591, 779093898, 66579049, 1121960111, 749415493, 502323961, 538932155, 259768753,
+ 753296935, 87897457, 539429964, 1675300017, 1232992084, 420106224, 1685350721, 346598567, 1610244183, 1597506096, 1079859867, 944382193, 1770497338, 764935753, 1776794410, 866854601, 365854486, 304211060, 344860208, 1361012693,
+ 1450892344, 622170346, 70003859, 1681866717, 435288306, 687941098, 308700094, 1367731096, 1834285819, 255226842, 193873940, 1833603743, 848402819, 152273285, 231181585, 1754447491, 1838218199, 834410115, 229905664, 2052321529,
+ 338532526, 77482422, 12937811, 35859252, 1645969422, 1501181424, 438711458, 1496078411, 419109342, 1455756978, 1234944834, 1287171290, 470090505, 1900162831, 1130850177, 1772760484, 381571915, 1605369007, 514914429, 994291574,
+ 1502557594, 1099847920, 1627355806, 1148699143, 1519017268, 946489895, 106595511, 921573402, 181567810, 1575380740, 1719573683, 1561730727, 1920182565, 1510133268, 1102603775, 1175885101, 802730854, 185979744, 1058937717, 1716853034,
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+
+type verify_data[DATA_SIZE] =
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+ 1746476698, 1746904676, 1747861289, 1749972876, 1750197960, 1750443194, 1750955971, 1752088215, 1752318678, 1752598186, 1753125385, 1754447491, 1755204784, 1757028186, 1758748737, 1760851607, 1761289401, 1763785295, 1764436465, 1765354961,
+ 1765830270, 1767380006, 1768795266, 1770497338, 1771614266, 1771924274, 1772760484, 1774218355, 1774652096, 1774796872, 1775331228, 1775608361, 1775805177, 1776471922, 1776794410, 1778544166, 1781233744, 1781891230, 1783233173, 1783943137,
+ 1784682542, 1787338655, 1787391786, 1788389051, 1790557628, 1792756324, 1793190956, 1793747608, 1797641070, 1799210492, 1800186189, 1800522575, 1802197319, 1802327778, 1803183394, 1806061681, 1807085904, 1807172811, 1808237662, 1811088032,
+ 1815408878, 1816641611, 1817156134, 1820281480, 1821482472, 1821559709, 1822279764, 1822612008, 1823053058, 1826590258, 1826628136, 1826880531, 1827651881, 1833543700, 1833603743, 1834161399, 1834254978, 1834285819, 1834318089, 1834388383,
+ 1834852613, 1835203128, 1835860030, 1835977906, 1836119534, 1837280287, 1838218199, 1839063567, 1840896199, 1846605728, 1847908587, 1848681194, 1849495275, 1849657867, 1849675857, 1852181952, 1855359256, 1858637614, 1858933377, 1859683061,
+ 1860435620, 1860839427, 1862876260, 1864952910, 1866094167, 1868151949, 1868289345, 1869264274, 1870214195, 1870859970, 1871060346, 1871684562, 1873900475, 1874026715, 1874855959, 1876255297, 1878253960, 1878434988, 1879635915, 1880483834,
+ 1880577483, 1881253854, 1883168929, 1883999260, 1886317932, 1890889527, 1890938638, 1891630185, 1891904961, 1892370478, 1893095488, 1896952705, 1897691227, 1897907456, 1898582764, 1900162831, 1900613055, 1901537567, 1902501708, 1902595458,
+ 1904243956, 1904514273, 1904576737, 1904770864, 1905279500, 1906345724, 1907793490, 1908093581, 1909681194, 1910978116, 1912065710, 1913489530, 1913581092, 1913926325, 1914764659, 1914809801, 1915435344, 1916602098, 1918354829, 1920182565,
+ 1924603748, 1926717418, 1927367009, 1928309762, 1928550562, 1930662128, 1930880552, 1931282005, 1931493432, 1932108837, 1933532372, 1933923245, 1935271536, 1936668087, 1938258683, 1939683211, 1942089394, 1943137808, 1943651015, 1944679691,
+ 1945110368, 1946004194, 1948121717, 1949896838, 1950124297, 1951228823, 1952177514, 1952364329, 1952805989, 1953450944, 1953919896, 1955436051, 1957728250, 1957877704, 1958396887, 1959222232, 1959292396, 1961619988, 1961647235, 1962689485,
+ 1963053072, 1965358941, 1965855212, 1967705762, 1968608155, 1968623233, 1969729134, 1970797151, 1971484382, 1971654864, 1977865396, 1980923963, 1981481446, 1983379601, 1984143440, 1984152603, 1985895474, 1986921372, 1989240516, 1992941115,
+ 1994402695, 1997381015, 2001056977, 2002881120, 2004664325, 2004770236, 2005021017, 2005653265, 2005817027, 2006320950, 2006856683, 2009244921, 2010549018, 2011827638, 2014090929, 2014129292, 2015847175, 2016161810, 2016464961, 2017191527,
+ 2018336444, 2022291557, 2022973269, 2023498746, 2024853642, 2027445678, 2027814180, 2027828650, 2027909489, 2028116487, 2029133999, 2029909894, 2033003588, 2033828953, 2034767768, 2036061488, 2036750157, 2037182006, 2038925801, 2039012903,
+ 2041942843, 2042861943, 2044016080, 2045407567, 2045821218, 2046759770, 2047006719, 2047769687, 2048205721, 2048560397, 2049698913, 2052321529, 2052328978, 2052343947, 2053899162, 2054212564, 2055783490, 2060969286, 2061144988, 2063408339,
+ 2064145552, 2064308502, 2066440075, 2066865713, 2067100479, 2067499753, 2068343250, 2068743361, 2069178089, 2070467093, 2072440819, 2073482870, 2074840378, 2074896270, 2076612603, 2077667592, 2078528215, 2079492652, 2080735477, 2081544705,
+ 2082760612, 2084953915, 2085323316, 2087660971, 2088576982, 2088786920, 2088955494, 2089981667, 2090025563, 2090543533, 2090570016, 2090684129, 2091626028, 2093472294, 2094085507, 2094159153, 2094591332, 2094864173, 2097057488, 2098829619,
+ 2100497812, 2103236982, 2105321510, 2105638337, 2105718728, 2105814934, 2108439398, 2109052886, 2109530615, 2109851473, 2113434968, 2114587535, 2115445751, 2116495484, 2117880007, 2118203528, 2118433006, 2118805956, 2118821565, 2119425672,
+ 2122262571, 2122852959, 2123379476, 2124749673, 2125958841, 2126029304, 2126940990, 2126963607, 2128078174, 2128826472, 2129513521, 2129930580, 2130252471, 2130879949, 2131761201, 2131797509, 2133066804, 2135673182, 2139976479, 2140091269,
+ 2140756121, 2141591317, 2142357746, 2143324534, 2143343312, 2143968639, 2145073408, 2145930822
+};
+
diff --git a/sw/app/rsort/rsort.c b/sw/app/rsort/rsort.c
new file mode 100644
index 00000000..32f7196b
--- /dev/null
+++ b/sw/app/rsort/rsort.c
@@ -0,0 +1,145 @@
+// See LICENSE for license details.
+
+//**************************************************************************
+// Quicksort benchmark
+//--------------------------------------------------------------------------
+//
+// This benchmark uses quicksort to sort an array of integers. The
+// implementation is largely adapted from Numerical Recipes for C. The
+// input data (and reference data) should be generated using the
+// qsort_gendata.pl perl script and dumped to a file named
+// dataset1.h
+
+#include "util.h"
+#include <string.h>
+#include <limits.h>
+
+
+
+#define NUM_COUNTERS 2
+static uintptr_t counters[NUM_COUNTERS];
+static char* counter_names[NUM_COUNTERS];
+
+
+void setStats(int enable)
+{
+ int i = 0;
+#define READ_CTR(name) do { \
+ while (i >= NUM_COUNTERS) ; \
+ uintptr_t csr = read_csr(name); \
+ if (!enable) { csr -= counters[i]; counter_names[i] = #name; } \
+ counters[i++] = csr; \
+ } while (0)
+
+ READ_CTR(mcycle);
+ READ_CTR(minstret);
+
+#undef READ_CTR
+}
+
+//--------------------------------------------------------------------------
+// Input/Reference Data
+
+#define type unsigned int
+#include "dataset1.h"
+
+#define LOG_BASE 8
+#define BASE (1 << LOG_BASE)
+
+#if 0
+# define fetch_add(ptr, inc) __sync_fetch_and_add(ptr, inc)
+#else
+# define fetch_add(ptr, inc) ((*(ptr) += (inc)) - (inc))
+#endif
+
+void sort(size_t n, type* arrIn, type* scratchIn)
+{
+ size_t log_exp = 0;
+ size_t buckets[BASE];
+ size_t *bucket = buckets;
+ asm("":"+r"(bucket));
+ type *arr = arrIn, *scratch = scratchIn, *p;
+ size_t *b;
+
+ while (log_exp < CHAR_BIT * sizeof(type))
+ {
+ for (b = bucket; b < bucket + BASE; b++)
+ *b = 0;
+
+ for (p = arr; p < &arr[n-3]; p += 4)
+ {
+ type a0 = p[0];
+ type a1 = p[1];
+ type a2 = p[2];
+ type a3 = p[3];
+ fetch_add(&bucket[(a0 >> log_exp) % BASE], 1);
+ fetch_add(&bucket[(a1 >> log_exp) % BASE], 1);
+ fetch_add(&bucket[(a2 >> log_exp) % BASE], 1);
+ fetch_add(&bucket[(a3 >> log_exp) % BASE], 1);
+ }
+ for ( ; p < &arr[n]; p++)
+ bucket[(*p >> log_exp) % BASE]++;
+
+ size_t prev = bucket[0];
+ prev += fetch_add(&bucket[1], prev);
+ for (b = &bucket[2]; b < bucket + BASE; b += 2)
+ {
+ prev += fetch_add(&b[0], prev);
+ prev += fetch_add(&b[1], prev);
+ }
+ static_assert(BASE % 2 == 0);
+
+ for (p = &arr[n-1]; p >= &arr[3]; p -= 4)
+ {
+ type a0 = p[-0];
+ type a1 = p[-1];
+ type a2 = p[-2];
+ type a3 = p[-3];
+ size_t* pb0 = &bucket[(a0 >> log_exp) % BASE];
+ size_t* pb1 = &bucket[(a1 >> log_exp) % BASE];
+ size_t* pb2 = &bucket[(a2 >> log_exp) % BASE];
+ size_t* pb3 = &bucket[(a3 >> log_exp) % BASE];
+ type* s0 = scratch + fetch_add(pb0, -1);
+ type* s1 = scratch + fetch_add(pb1, -1);
+ type* s2 = scratch + fetch_add(pb2, -1);
+ type* s3 = scratch + fetch_add(pb3, -1);
+ s0[-1] = a0;
+ s1[-1] = a1;
+ s2[-1] = a2;
+ s3[-1] = a3;
+ }
+ for ( ; p >= &arr[0]; p--)
+ scratch[--bucket[(*p >> log_exp) % BASE]] = *p;
+
+ type* tmp = arr;
+ arr = scratch;
+ scratch = tmp;
+
+ log_exp += LOG_BASE;
+ }
+ if (arr != arrIn)
+ memcpy(arr, scratch, n*sizeof(type));
+}
+
+//--------------------------------------------------------------------------
+// Main
+
+int main( int argc, char* argv[] )
+{
+ static type scratch[DATA_SIZE];
+
+#if PREALLOCATE
+ // If needed we preallocate everything in the caches
+ sort(DATA_SIZE, verify_data, scratch);
+ if (verify(DATA_SIZE, input_data, input_data))
+ return 1;
+#endif
+
+ // Do the sort
+ setStats(1);
+ sort(DATA_SIZE, input_data, scratch);
+ setStats(0);
+
+ // Check the results
+ return verify( DATA_SIZE, input_data, verify_data );
+}
diff --git a/sw/app/spmv/dataset1.h b/sw/app/spmv/dataset1.h
new file mode 100644
index 00000000..52e49c5b
--- /dev/null
+++ b/sw/app/spmv/dataset1.h
@@ -0,0 +1,6312 @@
+#define R 500
+#define C 500
+#define NNZ 2399
+const double val[2399] = {
+ 566,
+ 508,
+ 850,
+ 780,
+ 944,
+ 598,
+ 772,
+ 880,
+ 764,
+ 656,
+ 138,
+ 757,
+ 929,
+ 234,
+ 168,
+ 629,
+ 639,
+ 434,
+ 849,
+ 793,
+ 203,
+ 811,
+ 250,
+ 770,
+ 322,
+ 535,
+ 826,
+ 609,
+ 899,
+ 926,
+ 211,
+ 755,
+ 900,
+ 691,
+ 386,
+ 821,
+ 454,
+ 791,
+ 849,
+ 256,
+ 821,
+ 29,
+ 679,
+ 944,
+ 55,
+ 689,
+ 453,
+ 631,
+ 799,
+ 854,
+ 545,
+ 97,
+ 337,
+ 258,
+ 695,
+ 667,
+ 581,
+ 104,
+ 491,
+ 517,
+ 761,
+ 369,
+ 316,
+ 42,
+ 86,
+ 432,
+ 954,
+ 736,
+ 333,
+ 321,
+ 184,
+ 920,
+ 258,
+ 949,
+ 604,
+ 907,
+ 70,
+ 453,
+ 796,
+ 102,
+ 3,
+ 105,
+ 371,
+ 388,
+ 153,
+ 908,
+ 176,
+ 567,
+ 334,
+ 973,
+ 911,
+ 323,
+ 681,
+ 300,
+ 265,
+ 711,
+ 871,
+ 870,
+ 463,
+ 969,
+ 535,
+ 688,
+ 276,
+ 908,
+ 384,
+ 988,
+ 256,
+ 416,
+ 258,
+ 523,
+ 80,
+ 911,
+ 241,
+ 191,
+ 411,
+ 127,
+ 894,
+ 259,
+ 664,
+ 129,
+ 609,
+ 146,
+ 763,
+ 109,
+ 369,
+ 881,
+ 878,
+ 224,
+ 635,
+ 498,
+ 460,
+ 363,
+ 481,
+ 222,
+ 761,
+ 489,
+ 753,
+ 62,
+ 261,
+ 389,
+ 351,
+ 189,
+ 319,
+ 557,
+ 5,
+ 485,
+ 806,
+ 119,
+ 366,
+ 85,
+ 123,
+ 918,
+ 66,
+ 205,
+ 786,
+ 313,
+ 555,
+ 22,
+ 760,
+ 904,
+ 255,
+ 912,
+ 950,
+ 676,
+ 342,
+ 736,
+ 251,
+ 170,
+ 923,
+ 790,
+ 312,
+ 716,
+ 648,
+ 57,
+ 676,
+ 972,
+ 250,
+ 215,
+ 792,
+ 798,
+ 915,
+ 61,
+ 381,
+ 897,
+ 686,
+ 568,
+ 393,
+ 969,
+ 893,
+ 205,
+ 721,
+ 684,
+ 38,
+ 667,
+ 704,
+ 750,
+ 364,
+ 123,
+ 158,
+ 892,
+ 306,
+ 409,
+ 188,
+ 394,
+ 554,
+ 602,
+ 59,
+ 9,
+ 987,
+ 897,
+ 332,
+ 873,
+ 770,
+ 632,
+ 434,
+ 598,
+ 599,
+ 207,
+ 211,
+ 410,
+ 768,
+ 708,
+ 462,
+ 687,
+ 300,
+ 864,
+ 839,
+ 183,
+ 21,
+ 282,
+ 990,
+ 578,
+ 952,
+ 42,
+ 149,
+ 235,
+ 777,
+ 156,
+ 568,
+ 400,
+ 783,
+ 238,
+ 390,
+ 108,
+ 422,
+ 392,
+ 414,
+ 338,
+ 524,
+ 535,
+ 893,
+ 160,
+ 163,
+ 798,
+ 836,
+ 662,
+ 181,
+ 946,
+ 774,
+ 113,
+ 438,
+ 721,
+ 631,
+ 577,
+ 739,
+ 62,
+ 928,
+ 523,
+ 352,
+ 603,
+ 974,
+ 291,
+ 47,
+ 875,
+ 260,
+ 754,
+ 13,
+ 890,
+ 989,
+ 104,
+ 22,
+ 36,
+ 803,
+ 39,
+ 241,
+ 95,
+ 589,
+ 603,
+ 230,
+ 471,
+ 978,
+ 617,
+ 603,
+ 652,
+ 21,
+ 755,
+ 294,
+ 753,
+ 609,
+ 494,
+ 93,
+ 387,
+ 243,
+ 128,
+ 777,
+ 636,
+ 303,
+ 665,
+ 761,
+ 355,
+ 611,
+ 605,
+ 627,
+ 834,
+ 616,
+ 59,
+ 109,
+ 268,
+ 638,
+ 117,
+ 338,
+ 89,
+ 95,
+ 4,
+ 64,
+ 575,
+ 300,
+ 783,
+ 453,
+ 878,
+ 939,
+ 984,
+ 338,
+ 344,
+ 138,
+ 291,
+ 440,
+ 748,
+ 277,
+ 628,
+ 511,
+ 894,
+ 68,
+ 412,
+ 958,
+ 540,
+ 672,
+ 935,
+ 316,
+ 519,
+ 4,
+ 613,
+ 501,
+ 908,
+ 984,
+ 820,
+ 424,
+ 726,
+ 592,
+ 526,
+ 869,
+ 330,
+ 419,
+ 28,
+ 540,
+ 143,
+ 279,
+ 79,
+ 712,
+ 760,
+ 306,
+ 806,
+ 507,
+ 807,
+ 716,
+ 729,
+ 163,
+ 151,
+ 256,
+ 873,
+ 90,
+ 374,
+ 89,
+ 122,
+ 819,
+ 253,
+ 961,
+ 62,
+ 208,
+ 830,
+ 365,
+ 231,
+ 905,
+ 961,
+ 340,
+ 928,
+ 911,
+ 83,
+ 118,
+ 864,
+ 310,
+ 699,
+ 138,
+ 221,
+ 928,
+ 130,
+ 775,
+ 425,
+ 783,
+ 519,
+ 852,
+ 187,
+ 795,
+ 772,
+ 627,
+ 709,
+ 81,
+ 264,
+ 359,
+ 149,
+ 692,
+ 178,
+ 247,
+ 51,
+ 869,
+ 30,
+ 659,
+ 190,
+ 494,
+ 80,
+ 531,
+ 883,
+ 557,
+ 170,
+ 759,
+ 331,
+ 588,
+ 939,
+ 953,
+ 407,
+ 453,
+ 223,
+ 919,
+ 147,
+ 666,
+ 165,
+ 204,
+ 924,
+ 178,
+ 361,
+ 766,
+ 455,
+ 232,
+ 86,
+ 194,
+ 536,
+ 942,
+ 671,
+ 595,
+ 420,
+ 543,
+ 490,
+ 570,
+ 547,
+ 273,
+ 465,
+ 776,
+ 845,
+ 753,
+ 591,
+ 22,
+ 320,
+ 569,
+ 964,
+ 701,
+ 483,
+ 100,
+ 757,
+ 514,
+ 850,
+ 50,
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+ 993,
+ 79,
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+ 790,
+ 410,
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+ 494,
+ 245,
+ 881,
+ 676,
+ 484,
+ 821,
+ 183,
+ 45,
+ 343,
+ 76,
+ 423,
+ 855,
+ 188,
+ 16,
+ 355,
+ 159,
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+ 705,
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+ 997,
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+ 831,
+ 644,
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+ 395,
+ 485,
+ 457,
+ 879,
+ 478,
+ 900,
+ 187,
+ 699,
+ 559,
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+ 947,
+ 137,
+ 637,
+ 150,
+ 700,
+ 729,
+ 166,
+ 120,
+ 325,
+ 841,
+ 956,
+ 74,
+ 576,
+ 532,
+ 396,
+ 157,
+ 327,
+ 601,
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+ 681,
+ 813,
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+ 936,
+ 466,
+ 706,
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+ 769,
+ 71,
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+ 37,
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+ 111,
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+ 168,
+ 566,
+ 809,
+ 268,
+ 110,
+ 766,
+ 381,
+ 754,
+ 592,
+ 582,
+ 283,
+ 0,
+ 298,
+ 246,
+ 854,
+ 1,
+ 663,
+ 430,
+ 801,
+ 700,
+ 519,
+ 357,
+ 169,
+ 8,
+ 136,
+ 246,
+ 613,
+ 300,
+ 148,
+ 884,
+ 563,
+ 392,
+ 99,
+ 846,
+ 824,
+ 322,
+ 293,
+ 341,
+ 555,
+ 193,
+ 718,
+ 570,
+ 822,
+ 222,
+ 854,
+ 12,
+ 226,
+ 16,
+ 516,
+ 920,
+ 639,
+ 838,
+ 670,
+ 529,
+ 485,
+ 959,
+ 912,
+ 543,
+ 706,
+ 877,
+ 863,
+ 852,
+ 351,
+ 912,
+ 640,
+ 705,
+ 697,
+ 687,
+ 241,
+ 287,
+ 290,
+ 930,
+ 964,
+ 1
+};
+const int idx[2399] = {
+ 220,
+ 336,
+ 347,
+ 422,
+ 44,
+ 128,
+ 145,
+ 234,
+ 259,
+ 315,
+ 64,
+ 103,
+ 378,
+ 469,
+ 477,
+ 33,
+ 108,
+ 126,
+ 173,
+ 196,
+ 328,
+ 331,
+ 52,
+ 55,
+ 109,
+ 306,
+ 337,
+ 412,
+ 443,
+ 364,
+ 456,
+ 487,
+ 496,
+ 299,
+ 23,
+ 259,
+ 67,
+ 196,
+ 409,
+ 51,
+ 77,
+ 147,
+ 301,
+ 362,
+ 26,
+ 106,
+ 239,
+ 39,
+ 81,
+ 118,
+ 187,
+ 290,
+ 339,
+ 395,
+ 443,
+ 36,
+ 45,
+ 195,
+ 210,
+ 244,
+ 273,
+ 22,
+ 92,
+ 215,
+ 306,
+ 364,
+ 66,
+ 216,
+ 5,
+ 25,
+ 145,
+ 171,
+ 330,
+ 401,
+ 412,
+ 75,
+ 148,
+ 180,
+ 204,
+ 231,
+ 432,
+ 443,
+ 100,
+ 232,
+ 400,
+ 467,
+ 114,
+ 284,
+ 300,
+ 330,
+ 370,
+ 49,
+ 135,
+ 183,
+ 191,
+ 268,
+ 423,
+ 491,
+ 104,
+ 280,
+ 393,
+ 442,
+ 443,
+ 461,
+ 136,
+ 175,
+ 205,
+ 216,
+ 466,
+ 5,
+ 85,
+ 429,
+ 491,
+ 0,
+ 36,
+ 78,
+ 95,
+ 161,
+ 169,
+ 219,
+ 231,
+ 250,
+ 336,
+ 341,
+ 360,
+ 495,
+ 59,
+ 134,
+ 213,
+ 319,
+ 409,
+ 93,
+ 104,
+ 256,
+ 223,
+ 226,
+ 8,
+ 115,
+ 185,
+ 216,
+ 320,
+ 399,
+ 461,
+ 14,
+ 60,
+ 87,
+ 93,
+ 134,
+ 170,
+ 391,
+ 399,
+ 416,
+ 455,
+ 3,
+ 86,
+ 99,
+ 304,
+ 471,
+ 488,
+ 0,
+ 102,
+ 132,
+ 179,
+ 303,
+ 312,
+ 313,
+ 320,
+ 389,
+ 279,
+ 473,
+ 180,
+ 303,
+ 310,
+ 326,
+ 7,
+ 136,
+ 239,
+ 256,
+ 276,
+ 350,
+ 21,
+ 32,
+ 79,
+ 209,
+ 270,
+ 314,
+ 463,
+ 87,
+ 134,
+ 188,
+ 212,
+ 418,
+ 13,
+ 76,
+ 124,
+ 179,
+ 409,
+ 411,
+ 19,
+ 299,
+ 207,
+ 266,
+ 329,
+ 468,
+ 29,
+ 45,
+ 265,
+ 310,
+ 384,
+ 429,
+ 480,
+ 191,
+ 347,
+ 61,
+ 66,
+ 219,
+ 228,
+ 277,
+ 289,
+ 308,
+ 402,
+ 409,
+ 133,
+ 382,
+ 488,
+ 18,
+ 310,
+ 439,
+ 206,
+ 257,
+ 290,
+ 356,
+ 443,
+ 43,
+ 140,
+ 184,
+ 187,
+ 278,
+ 286,
+ 341,
+ 354,
+ 126,
+ 201,
+ 208,
+ 239,
+ 454,
+ 485,
+ 40,
+ 87,
+ 222,
+ 367,
+ 398,
+ 457,
+ 299,
+ 423,
+ 440,
+ 44,
+ 115,
+ 126,
+ 147,
+ 291,
+ 411,
+ 64,
+ 480,
+ 1,
+ 67,
+ 80,
+ 91,
+ 163,
+ 239,
+ 42,
+ 350,
+ 361,
+ 427,
+ 67,
+ 169,
+ 270,
+ 15,
+ 44,
+ 223,
+ 378,
+ 452,
+ 471,
+ 31,
+ 67,
+ 274,
+ 292,
+ 457,
+ 58,
+ 107,
+ 183,
+ 222,
+ 347,
+ 407,
+ 27,
+ 65,
+ 84,
+ 208,
+ 273,
+ 385,
+ 441,
+ 43,
+ 97,
+ 226,
+ 305,
+ 360,
+ 492,
+ 26,
+ 88,
+ 284,
+ 369,
+ 476,
+ 21,
+ 48,
+ 478,
+ 230,
+ 312,
+ 409,
+ 475,
+ 42,
+ 53,
+ 78,
+ 259,
+ 268,
+ 489,
+ 3,
+ 37,
+ 60,
+ 141,
+ 132,
+ 150,
+ 157,
+ 328,
+ 353,
+ 357,
+ 422,
+ 466,
+ 480,
+ 154,
+ 455,
+ 295,
+ 411,
+ 249,
+ 320,
+ 359,
+ 381,
+ 401,
+ 451,
+ 210,
+ 231,
+ 253,
+ 323,
+ 330,
+ 5,
+ 55,
+ 79,
+ 105,
+ 298,
+ 496,
+ 160,
+ 229,
+ 425,
+ 30,
+ 63,
+ 115,
+ 129,
+ 280,
+ 458,
+ 31,
+ 68,
+ 254,
+ 360,
+ 420,
+ 490,
+ 2,
+ 172,
+ 180,
+ 209,
+ 223,
+ 228,
+ 265,
+ 357,
+ 369,
+ 380,
+ 443,
+ 453,
+ 483,
+ 36,
+ 110,
+ 129,
+ 135,
+ 246,
+ 305,
+ 36,
+ 211,
+ 239,
+ 254,
+ 392,
+ 403,
+ 494,
+ 255,
+ 332,
+ 485,
+ 110,
+ 360,
+ 498,
+ 0,
+ 11,
+ 37,
+ 106,
+ 182,
+ 308,
+ 14,
+ 41,
+ 75,
+ 218,
+ 256,
+ 259,
+ 294,
+ 462,
+ 218,
+ 231,
+ 248,
+ 392,
+ 427,
+ 21,
+ 234,
+ 406,
+ 29,
+ 171,
+ 248,
+ 255,
+ 352,
+ 34,
+ 57,
+ 122,
+ 173,
+ 254,
+ 308,
+ 380,
+ 393,
+ 278,
+ 28,
+ 62,
+ 129,
+ 296,
+ 455,
+ 474,
+ 15,
+ 47,
+ 128,
+ 133,
+ 300,
+ 390,
+ 459,
+ 468,
+ 35,
+ 48,
+ 70,
+ 287,
+ 299,
+ 318,
+ 22,
+ 108,
+ 171,
+ 195,
+ 460,
+ 496,
+ 188,
+ 21,
+ 31,
+ 86,
+ 338,
+ 420,
+ 422,
+ 486,
+ 495,
+ 245,
+ 445,
+ 22,
+ 85,
+ 92,
+ 337,
+ 381,
+ 387,
+ 7,
+ 9,
+ 231,
+ 425,
+ 430,
+ 56,
+ 196,
+ 344,
+ 354,
+ 377,
+ 91,
+ 107,
+ 177,
+ 221,
+ 295,
+ 321,
+ 5,
+ 35,
+ 48,
+ 90,
+ 290,
+ 432,
+ 447,
+ 51,
+ 322,
+ 324,
+ 364,
+ 482,
+ 59,
+ 303,
+ 334,
+ 444,
+ 450,
+ 55,
+ 125,
+ 319,
+ 380,
+ 394,
+ 431,
+ 82,
+ 112,
+ 157,
+ 187,
+ 261,
+ 326,
+ 347,
+ 366,
+ 18,
+ 124,
+ 490,
+ 8,
+ 218,
+ 291,
+ 35,
+ 132,
+ 322,
+ 425,
+ 147,
+ 150,
+ 242,
+ 472,
+ 186,
+ 195,
+ 201,
+ 216,
+ 251,
+ 458,
+ 33,
+ 46,
+ 153,
+ 297,
+ 298,
+ 311,
+ 322,
+ 399,
+ 426,
+ 65,
+ 230,
+ 9,
+ 32,
+ 69,
+ 391,
+ 70,
+ 126,
+ 147,
+ 222,
+ 86,
+ 261,
+ 412,
+ 183,
+ 474,
+ 110,
+ 125,
+ 172,
+ 185,
+ 402,
+ 363,
+ 403,
+ 462,
+ 40,
+ 274,
+ 386,
+ 449,
+ 333,
+ 340,
+ 421,
+ 424,
+ 410,
+ 30,
+ 86,
+ 262,
+ 374,
+ 23,
+ 72,
+ 9,
+ 47,
+ 86,
+ 93,
+ 286,
+ 304,
+ 402,
+ 420,
+ 118,
+ 265,
+ 276,
+ 283,
+ 455,
+ 20,
+ 36,
+ 391,
+ 115,
+ 137,
+ 305,
+ 334,
+ 10,
+ 188,
+ 237,
+ 271,
+ 393,
+ 422,
+ 497,
+ 21,
+ 30,
+ 99,
+ 109,
+ 175,
+ 198,
+ 467,
+ 3,
+ 19,
+ 63,
+ 82,
+ 115,
+ 149,
+ 265,
+ 24,
+ 151,
+ 217,
+ 252,
+ 307,
+ 421,
+ 146,
+ 333,
+ 381,
+ 434,
+ 32,
+ 311,
+ 361,
+ 93,
+ 142,
+ 152,
+ 395,
+ 422,
+ 467,
+ 91,
+ 181,
+ 244,
+ 294,
+ 332,
+ 390,
+ 97,
+ 177,
+ 296,
+ 323,
+ 428,
+ 27,
+ 215,
+ 318,
+ 66,
+ 193,
+ 216,
+ 333,
+ 416,
+ 127,
+ 171,
+ 209,
+ 219,
+ 333,
+ 377,
+ 401,
+ 9,
+ 103,
+ 129,
+ 135,
+ 290,
+ 438,
+ 33,
+ 107,
+ 221,
+ 351,
+ 392,
+ 406,
+ 91,
+ 170,
+ 182,
+ 313,
+ 419,
+ 465,
+ 28,
+ 74,
+ 175,
+ 231,
+ 270,
+ 30,
+ 34,
+ 240,
+ 253,
+ 63,
+ 133,
+ 337,
+ 369,
+ 416,
+ 255,
+ 445,
+ 145,
+ 350,
+ 416,
+ 183,
+ 257,
+ 414,
+ 136,
+ 164,
+ 255,
+ 300,
+ 434,
+ 438,
+ 447,
+ 60,
+ 157,
+ 396,
+ 412,
+ 25,
+ 343,
+ 42,
+ 105,
+ 361,
+ 472,
+ 34,
+ 74,
+ 136,
+ 436,
+ 474,
+ 94,
+ 177,
+ 205,
+ 225,
+ 227,
+ 319,
+ 23,
+ 245,
+ 383,
+ 426,
+ 31,
+ 190,
+ 215,
+ 228,
+ 324,
+ 416,
+ 7,
+ 12,
+ 260,
+ 470,
+ 13,
+ 290,
+ 9,
+ 44,
+ 117,
+ 166,
+ 186,
+ 260,
+ 361,
+ 372,
+ 224,
+ 241,
+ 369,
+ 1,
+ 87,
+ 297,
+ 457,
+ 29,
+ 98,
+ 118,
+ 158,
+ 226,
+ 286,
+ 74,
+ 167,
+ 241,
+ 328,
+ 370,
+ 412,
+ 454,
+ 1,
+ 37,
+ 183,
+ 228,
+ 311,
+ 336,
+ 345,
+ 413,
+ 430,
+ 446,
+ 211,
+ 327,
+ 375,
+ 84,
+ 195,
+ 219,
+ 430,
+ 447,
+ 195,
+ 384,
+ 50,
+ 93,
+ 224,
+ 349,
+ 479,
+ 6,
+ 56,
+ 105,
+ 118,
+ 170,
+ 286,
+ 468,
+ 466,
+ 153,
+ 224,
+ 240,
+ 400,
+ 444,
+ 63,
+ 158,
+ 196,
+ 237,
+ 284,
+ 296,
+ 405,
+ 407,
+ 480,
+ 26,
+ 56,
+ 233,
+ 428,
+ 370,
+ 398,
+ 491,
+ 159,
+ 184,
+ 488,
+ 131,
+ 134,
+ 138,
+ 276,
+ 344,
+ 372,
+ 428,
+ 494,
+ 269,
+ 486,
+ 136,
+ 139,
+ 163,
+ 201,
+ 253,
+ 272,
+ 374,
+ 398,
+ 487,
+ 307,
+ 375,
+ 487,
+ 168,
+ 284,
+ 346,
+ 420,
+ 451,
+ 134,
+ 175,
+ 284,
+ 88,
+ 105,
+ 286,
+ 448,
+ 96,
+ 117,
+ 177,
+ 240,
+ 285,
+ 325,
+ 455,
+ 51,
+ 228,
+ 298,
+ 421,
+ 150,
+ 433,
+ 182,
+ 362,
+ 410,
+ 58,
+ 262,
+ 352,
+ 439,
+ 43,
+ 70,
+ 134,
+ 278,
+ 152,
+ 210,
+ 283,
+ 310,
+ 333,
+ 334,
+ 469,
+ 20,
+ 42,
+ 69,
+ 222,
+ 283,
+ 320,
+ 330,
+ 376,
+ 218,
+ 285,
+ 413,
+ 434,
+ 5,
+ 175,
+ 180,
+ 265,
+ 440,
+ 474,
+ 241,
+ 255,
+ 377,
+ 479,
+ 307,
+ 317,
+ 457,
+ 0,
+ 232,
+ 342,
+ 496,
+ 25,
+ 292,
+ 105,
+ 169,
+ 208,
+ 300,
+ 439,
+ 21,
+ 65,
+ 120,
+ 249,
+ 273,
+ 191,
+ 302,
+ 376,
+ 56,
+ 92,
+ 240,
+ 371,
+ 391,
+ 446,
+ 489,
+ 84,
+ 241,
+ 322,
+ 473,
+ 475,
+ 16,
+ 92,
+ 214,
+ 239,
+ 50,
+ 158,
+ 175,
+ 452,
+ 51,
+ 360,
+ 25,
+ 39,
+ 90,
+ 99,
+ 133,
+ 408,
+ 491,
+ 430,
+ 12,
+ 64,
+ 76,
+ 189,
+ 481,
+ 128,
+ 306,
+ 442,
+ 77,
+ 276,
+ 337,
+ 356,
+ 380,
+ 389,
+ 445,
+ 61,
+ 158,
+ 194,
+ 445,
+ 303,
+ 398,
+ 143,
+ 163,
+ 199,
+ 343,
+ 236,
+ 246,
+ 340,
+ 382,
+ 446,
+ 38,
+ 154,
+ 196,
+ 202,
+ 266,
+ 367,
+ 369,
+ 117,
+ 136,
+ 250,
+ 272,
+ 413,
+ 481,
+ 0,
+ 199,
+ 205,
+ 412,
+ 39,
+ 177,
+ 198,
+ 369,
+ 448,
+ 91,
+ 153,
+ 167,
+ 187,
+ 203,
+ 265,
+ 328,
+ 218,
+ 222,
+ 261,
+ 413,
+ 419,
+ 447,
+ 128,
+ 228,
+ 498,
+ 0,
+ 148,
+ 198,
+ 486,
+ 497,
+ 50,
+ 398,
+ 457,
+ 283,
+ 460,
+ 43,
+ 116,
+ 246,
+ 248,
+ 305,
+ 447,
+ 106,
+ 131,
+ 317,
+ 126,
+ 199,
+ 235,
+ 293,
+ 34,
+ 108,
+ 226,
+ 3,
+ 108,
+ 129,
+ 155,
+ 174,
+ 162,
+ 239,
+ 490,
+ 124,
+ 214,
+ 346,
+ 469,
+ 497,
+ 274,
+ 316,
+ 122,
+ 144,
+ 149,
+ 290,
+ 337,
+ 362,
+ 371,
+ 466,
+ 67,
+ 248,
+ 276,
+ 332,
+ 360,
+ 387,
+ 405,
+ 31,
+ 56,
+ 65,
+ 90,
+ 200,
+ 64,
+ 176,
+ 203,
+ 215,
+ 236,
+ 240,
+ 337,
+ 383,
+ 198,
+ 411,
+ 431,
+ 36,
+ 90,
+ 350,
+ 356,
+ 497,
+ 33,
+ 120,
+ 130,
+ 183,
+ 409,
+ 493,
+ 8,
+ 35,
+ 254,
+ 277,
+ 321,
+ 341,
+ 388,
+ 423,
+ 497,
+ 143,
+ 163,
+ 391,
+ 446,
+ 492,
+ 9,
+ 270,
+ 42,
+ 52,
+ 116,
+ 396,
+ 456,
+ 478,
+ 491,
+ 143,
+ 148,
+ 286,
+ 328,
+ 384,
+ 35,
+ 127,
+ 351,
+ 452,
+ 7,
+ 46,
+ 259,
+ 35,
+ 290,
+ 370,
+ 420,
+ 104,
+ 258,
+ 278,
+ 340,
+ 481,
+ 169,
+ 264,
+ 368,
+ 232,
+ 471,
+ 1,
+ 135,
+ 211,
+ 152,
+ 174,
+ 177,
+ 187,
+ 292,
+ 411,
+ 430,
+ 461,
+ 4,
+ 92,
+ 205,
+ 237,
+ 247,
+ 333,
+ 53,
+ 91,
+ 289,
+ 334,
+ 425,
+ 491,
+ 118,
+ 175,
+ 490,
+ 36,
+ 361,
+ 33,
+ 186,
+ 213,
+ 471,
+ 3,
+ 73,
+ 163,
+ 409,
+ 235,
+ 384,
+ 410,
+ 470,
+ 480,
+ 59,
+ 469,
+ 97,
+ 344,
+ 372,
+ 33,
+ 107,
+ 179,
+ 397,
+ 470,
+ 291,
+ 340,
+ 361,
+ 385,
+ 25,
+ 111,
+ 158,
+ 331,
+ 471,
+ 28,
+ 87,
+ 307,
+ 69,
+ 105,
+ 159,
+ 284,
+ 311,
+ 312,
+ 359,
+ 465,
+ 17,
+ 133,
+ 302,
+ 324,
+ 274,
+ 325,
+ 421,
+ 252,
+ 4,
+ 96,
+ 409,
+ 206,
+ 246,
+ 288,
+ 58,
+ 81,
+ 150,
+ 226,
+ 232,
+ 380,
+ 168,
+ 229,
+ 367,
+ 210,
+ 248,
+ 405,
+ 420,
+ 163,
+ 212,
+ 320,
+ 340,
+ 448,
+ 68,
+ 222,
+ 439,
+ 494,
+ 70,
+ 94,
+ 116,
+ 471,
+ 284,
+ 380,
+ 13,
+ 26,
+ 120,
+ 276,
+ 394,
+ 432,
+ 492,
+ 281,
+ 297,
+ 300,
+ 355,
+ 29,
+ 32,
+ 156,
+ 182,
+ 467,
+ 203,
+ 234,
+ 420,
+ 429,
+ 210,
+ 224,
+ 248,
+ 273,
+ 326,
+ 349,
+ 37,
+ 202,
+ 377,
+ 380,
+ 43,
+ 55,
+ 139,
+ 141,
+ 170,
+ 232,
+ 292,
+ 322,
+ 77,
+ 214,
+ 241,
+ 279,
+ 326,
+ 18,
+ 46,
+ 55,
+ 107,
+ 227,
+ 238,
+ 250,
+ 146,
+ 168,
+ 402,
+ 444,
+ 459,
+ 487,
+ 495,
+ 6,
+ 121,
+ 256,
+ 303,
+ 457,
+ 461,
+ 69,
+ 122,
+ 193,
+ 204,
+ 240,
+ 347,
+ 412,
+ 418,
+ 476,
+ 169,
+ 187,
+ 400,
+ 97,
+ 290,
+ 364,
+ 394,
+ 153,
+ 184,
+ 187,
+ 9,
+ 13,
+ 65,
+ 89,
+ 120,
+ 221,
+ 484,
+ 6,
+ 120,
+ 180,
+ 419,
+ 15,
+ 86,
+ 104,
+ 193,
+ 276,
+ 324,
+ 437,
+ 443,
+ 62,
+ 97,
+ 193,
+ 288,
+ 315,
+ 318,
+ 414,
+ 24,
+ 170,
+ 189,
+ 196,
+ 216,
+ 228,
+ 270,
+ 420,
+ 214,
+ 407,
+ 466,
+ 2,
+ 77,
+ 127,
+ 188,
+ 230,
+ 310,
+ 464,
+ 469,
+ 80,
+ 204,
+ 138,
+ 171,
+ 252,
+ 424,
+ 0,
+ 95,
+ 363,
+ 395,
+ 408,
+ 430,
+ 96,
+ 143,
+ 289,
+ 97,
+ 183,
+ 341,
+ 399,
+ 460,
+ 84,
+ 243,
+ 498,
+ 28,
+ 65,
+ 77,
+ 84,
+ 139,
+ 147,
+ 171,
+ 214,
+ 256,
+ 348,
+ 408,
+ 444,
+ 449,
+ 457,
+ 120,
+ 342,
+ 38,
+ 217,
+ 465,
+ 8,
+ 212,
+ 268,
+ 346,
+ 486,
+ 491,
+ 49,
+ 77,
+ 90,
+ 222,
+ 291,
+ 383,
+ 130,
+ 405,
+ 431,
+ 473,
+ 78,
+ 290,
+ 351,
+ 189,
+ 304,
+ 498,
+ 336,
+ 10,
+ 219,
+ 257,
+ 402,
+ 437,
+ 65,
+ 69,
+ 168,
+ 198,
+ 65,
+ 241,
+ 242,
+ 290,
+ 360,
+ 402,
+ 254,
+ 256,
+ 398,
+ 407,
+ 66,
+ 97,
+ 164,
+ 222,
+ 316,
+ 390,
+ 429,
+ 24,
+ 81,
+ 133,
+ 207,
+ 313,
+ 67,
+ 108,
+ 204,
+ 303,
+ 494,
+ 43,
+ 194,
+ 198,
+ 285,
+ 294,
+ 347,
+ 356,
+ 394,
+ 83,
+ 92,
+ 147,
+ 167,
+ 386,
+ 20,
+ 225,
+ 400,
+ 172,
+ 363,
+ 99,
+ 64,
+ 373,
+ 377,
+ 6,
+ 63,
+ 206,
+ 107,
+ 149,
+ 230,
+ 428,
+ 41,
+ 56,
+ 77,
+ 78,
+ 311,
+ 413,
+ 476,
+ 477,
+ 81,
+ 130,
+ 145,
+ 167,
+ 247,
+ 416,
+ 56,
+ 289,
+ 339,
+ 27,
+ 47,
+ 132,
+ 309,
+ 392,
+ 36,
+ 55,
+ 73,
+ 352,
+ 358,
+ 25,
+ 58,
+ 352,
+ 430,
+ 58,
+ 171,
+ 221,
+ 334,
+ 379,
+ 453,
+ 288,
+ 479,
+ 109,
+ 134,
+ 143,
+ 174,
+ 285,
+ 313,
+ 468,
+ 495,
+ 258,
+ 289,
+ 334,
+ 382,
+ 483,
+ 46,
+ 136,
+ 264,
+ 417,
+ 458,
+ 36,
+ 59,
+ 88,
+ 173,
+ 310,
+ 316,
+ 354,
+ 471,
+ 46,
+ 225,
+ 262,
+ 335,
+ 364,
+ 468,
+ 121,
+ 341,
+ 349,
+ 7,
+ 14,
+ 21,
+ 99,
+ 135,
+ 142,
+ 207,
+ 209,
+ 272,
+ 294,
+ 456,
+ 491,
+ 208,
+ 248,
+ 321,
+ 43,
+ 129,
+ 188,
+ 362,
+ 191,
+ 279,
+ 294,
+ 307,
+ 324,
+ 362,
+ 140,
+ 422,
+ 56,
+ 169,
+ 188,
+ 232,
+ 328,
+ 449,
+ 14,
+ 134,
+ 369,
+ 375,
+ 48,
+ 164,
+ 224,
+ 260,
+ 20,
+ 93,
+ 157,
+ 219,
+ 262,
+ 274,
+ 362,
+ 473,
+ 484,
+ 103,
+ 125,
+ 140,
+ 174,
+ 175,
+ 191,
+ 226,
+ 358,
+ 408,
+ 450,
+ 20,
+ 94,
+ 289,
+ 310,
+ 311,
+ 448,
+ 478,
+ 36,
+ 175,
+ 185,
+ 337,
+ 391,
+ 48,
+ 72,
+ 184,
+ 233,
+ 345,
+ 485,
+ 231,
+ 242,
+ 339,
+ 451,
+ 456,
+ 152,
+ 158,
+ 398,
+ 458,
+ 488,
+ 151,
+ 240,
+ 357,
+ 1,
+ 33,
+ 139,
+ 141,
+ 177,
+ 223,
+ 289,
+ 479,
+ 90,
+ 115,
+ 461,
+ 480,
+ 24,
+ 26,
+ 44,
+ 72,
+ 213,
+ 361,
+ 445,
+ 34,
+ 119,
+ 470,
+ 19,
+ 56,
+ 405,
+ 464,
+ 47,
+ 112,
+ 163,
+ 235,
+ 342,
+ 462,
+ 103,
+ 192,
+ 225,
+ 23,
+ 458,
+ 68,
+ 270,
+ 363,
+ 422,
+ 427,
+ 449,
+ 450,
+ 477,
+ 105,
+ 131,
+ 139,
+ 198,
+ 212,
+ 413,
+ 429,
+ 435,
+ 43,
+ 278,
+ 19,
+ 113,
+ 192,
+ 327,
+ 347,
+ 44,
+ 67,
+ 160,
+ 225,
+ 263,
+ 330,
+ 344,
+ 158,
+ 274,
+ 303,
+ 317,
+ 350,
+ 379,
+ 409,
+ 33,
+ 53,
+ 217,
+ 273,
+ 304,
+ 352,
+ 461,
+ 495,
+ 101,
+ 168,
+ 370,
+ 395,
+ 458,
+ 156,
+ 301,
+ 319,
+ 324,
+ 347,
+ 73,
+ 127,
+ 253,
+ 272,
+ 128,
+ 212,
+ 237,
+ 257,
+ 351,
+ 77,
+ 106,
+ 216,
+ 270,
+ 368,
+ 371,
+ 400,
+ 223,
+ 355,
+ 384,
+ 30,
+ 268,
+ 307,
+ 368,
+ 79,
+ 300,
+ 317,
+ 327,
+ 15,
+ 376,
+ 31,
+ 80,
+ 160,
+ 206,
+ 227,
+ 103,
+ 231,
+ 435,
+ 481,
+ 499,
+ 182,
+ 186,
+ 189,
+ 442,
+ 7,
+ 59,
+ 65,
+ 117,
+ 225,
+ 298,
+ 304,
+ 364,
+ 457,
+ 489,
+ 186,
+ 198,
+ 265,
+ 309,
+ 336,
+ 391,
+ 457,
+ 314,
+ 418,
+ 81,
+ 133,
+ 186,
+ 190,
+ 227,
+ 258,
+ 277,
+ 419,
+ 492,
+ 82,
+ 222,
+ 239,
+ 315,
+ 71,
+ 92,
+ 122,
+ 220,
+ 252,
+ 272,
+ 311,
+ 391,
+ 433,
+ 97,
+ 137,
+ 244,
+ 267,
+ 426,
+ 34,
+ 202,
+ 234,
+ 426,
+ 428,
+ 51,
+ 109,
+ 267,
+ 377,
+ 382,
+ 107,
+ 166,
+ 203,
+ 337,
+ 0,
+ 127,
+ 247,
+ 404,
+ 64,
+ 94,
+ 373,
+ 430,
+ 448,
+ 17,
+ 37,
+ 57,
+ 102,
+ 352,
+ 354,
+ 114,
+ 174,
+ 193,
+ 241,
+ 284,
+ 74,
+ 94,
+ 213,
+ 238,
+ 475,
+ 476,
+ 140,
+ 247,
+ 280,
+ 302,
+ 328,
+ 49,
+ 197,
+ 201,
+ 222,
+ 280,
+ 457,
+ 167,
+ 445,
+ 465,
+ 478,
+ 499,
+ 25,
+ 215,
+ 438,
+ 8,
+ 129,
+ 153,
+ 171,
+ 316,
+ 328,
+ 158,
+ 215,
+ 303,
+ 328,
+ 353,
+ 479,
+ 62,
+ 251,
+ 271,
+ 4,
+ 119,
+ 262,
+ 303,
+ 311,
+ 405,
+ 419,
+ 277,
+ 461,
+ 236,
+ 248,
+ 445,
+ 15,
+ 108,
+ 227,
+ 309,
+ 362,
+ 378,
+ 424,
+ 78,
+ 94,
+ 109,
+ 118,
+ 124,
+ 247,
+ 253,
+ 315,
+ 478,
+ 13,
+ 154,
+ 170,
+ 331,
+ 365,
+ 386,
+ 264,
+ 268,
+ 300,
+ 305,
+ 429,
+ 463,
+ 499,
+ 52,
+ 105,
+ 135,
+ 181,
+ 111,
+ 156,
+ 183,
+ 231,
+ 350,
+ 388,
+ 461,
+ 291,
+ 360,
+ 80,
+ 106,
+ 138,
+ 197,
+ 242,
+ 255,
+ 260,
+ 381,
+ 415,
+ 447,
+ 499,
+ 41,
+ 266,
+ 341,
+ 391,
+ 410,
+ 448,
+ 495,
+ 58,
+ 146,
+ 286,
+ 351,
+ 419,
+ 436,
+ 464,
+ 483,
+ 251,
+ 252,
+ 444,
+ 492,
+ 184,
+ 200,
+ 57,
+ 75,
+ 170,
+ 186,
+ 187,
+ 275,
+ 314,
+ 364,
+ 407,
+ 162,
+ 173,
+ 232,
+ 211,
+ 355,
+ 445,
+ 448,
+ 308,
+ 98,
+ 280,
+ 397,
+ 431,
+ 112,
+ 122,
+ 157,
+ 209,
+ 338,
+ 388,
+ 429,
+ 112,
+ 213,
+ 349,
+ 470,
+ 69,
+ 70,
+ 119,
+ 222,
+ 251,
+ 453,
+ 81,
+ 173,
+ 482,
+ 105,
+ 147,
+ 10,
+ 229,
+ 462,
+ 467,
+ 98,
+ 421,
+ 479,
+ 203,
+ 498,
+ 499,
+ 93,
+ 130,
+ 142,
+ 270,
+ 278,
+ 336,
+ 419,
+ 73,
+ 134,
+ 142,
+ 177,
+ 192,
+ 335,
+ 490,
+ 45,
+ 140,
+ 143,
+ 195,
+ 274,
+ 284,
+ 324,
+ 56,
+ 94,
+ 171,
+ 28,
+ 135,
+ 258,
+ 277,
+ 284,
+ 333,
+ 370,
+ 421,
+ 432,
+ 465,
+ 31,
+ 46,
+ 222,
+ 331,
+ 387,
+ 432,
+ 18,
+ 56,
+ 82,
+ 95,
+ 258,
+ 261,
+ 356,
+ 378,
+ 484,
+ 60,
+ 285,
+ 298,
+ 347,
+ 0,
+ 200,
+ 307,
+ 372,
+ 2,
+ 89,
+ 201,
+ 291,
+ 298,
+ 382,
+ 455,
+ 121,
+ 145,
+ 155,
+ 47,
+ 226,
+ 236,
+ 396,
+ 398,
+ 137,
+ 311,
+ 381,
+ 429,
+ 45,
+ 109,
+ 141,
+ 173,
+ 207,
+ 464,
+ 471,
+ 499,
+ 37,
+ 45,
+ 268,
+ 447,
+ 496,
+ 41,
+ 163,
+ 387,
+ 484,
+ 30,
+ 48,
+ 91,
+ 146,
+ 261,
+ 313,
+ 401,
+ 11,
+ 78,
+ 122,
+ 144,
+ 450,
+ 499,
+ 75,
+ 82,
+ 131,
+ 218,
+ 257,
+ 285,
+ 294,
+ 362,
+ 442,
+ 213,
+ 255,
+ 291,
+ 492,
+ 63,
+ 80,
+ 282,
+ 418,
+ 1,
+ 60,
+ 87,
+ 102,
+ 111,
+ 180,
+ 272,
+ 281,
+ 324,
+ 380,
+ 458,
+ 185,
+ 216,
+ 475,
+ 12,
+ 62,
+ 109,
+ 143,
+ 195,
+ 257,
+ 271,
+ 324,
+ 385,
+ 410,
+ 226,
+ 330,
+ 404,
+ 54,
+ 158,
+ 374,
+ 221,
+ 320,
+ 340,
+ 86,
+ 93,
+ 236,
+ 94,
+ 159,
+ 238,
+ 242,
+ 318,
+ 356,
+ 40,
+ 75,
+ 168,
+ 211,
+ 294,
+ 32,
+ 164,
+ 174,
+ 198,
+ 421,
+ 13,
+ 102,
+ 314,
+ 379,
+ 418,
+ 439,
+ 485,
+ 6,
+ 53,
+ 104,
+ 123,
+ 208,
+ 436,
+ 452,
+ 59,
+ 141,
+ 204,
+ 402,
+ 498,
+ 134,
+ 335,
+ 429,
+ 240,
+ 391,
+ 461,
+ 14,
+ 16,
+ 46,
+ 371,
+ 376,
+ 37,
+ 172,
+ 227,
+ 343,
+ 397,
+ 435,
+ 39,
+ 136,
+ 202,
+ 262,
+ 339,
+ 445,
+ 474,
+ 145,
+ 272,
+ 342,
+ 121,
+ 127,
+ 12,
+ 125,
+ 155,
+ 186,
+ 234,
+ 64,
+ 96,
+ 97,
+ 108,
+ 213,
+ 350,
+ 410,
+ 485,
+ 35,
+ 56,
+ 57,
+ 167,
+ 169,
+ 399,
+ 478,
+ 60,
+ 103,
+ 307,
+ 92,
+ 104,
+ 150,
+ 211,
+ 260,
+ 8,
+ 64,
+ 73,
+ 222,
+ 273,
+ 423,
+ 179,
+ 184,
+ 190,
+ 193,
+ 265,
+ 271,
+ 305,
+ 318,
+ 344,
+ 14,
+ 75,
+ 124,
+ 317,
+ 343,
+ 404,
+ 4,
+ 141,
+ 167,
+ 212,
+ 496
+};
+const double x[500] = {
+ 737,
+ 519,
+ 538,
+ 486,
+ 557,
+ 31,
+ 651,
+ 101,
+ 310,
+ 729,
+ 721,
+ 164,
+ 577,
+ 411,
+ 104,
+ 891,
+ 988,
+ 370,
+ 788,
+ 898,
+ 576,
+ 674,
+ 7,
+ 10,
+ 91,
+ 253,
+ 9,
+ 54,
+ 105,
+ 36,
+ 799,
+ 188,
+ 651,
+ 92,
+ 766,
+ 394,
+ 8,
+ 823,
+ 242,
+ 334,
+ 639,
+ 462,
+ 111,
+ 847,
+ 919,
+ 681,
+ 392,
+ 657,
+ 358,
+ 203,
+ 453,
+ 897,
+ 965,
+ 316,
+ 759,
+ 894,
+ 893,
+ 44,
+ 743,
+ 736,
+ 970,
+ 473,
+ 229,
+ 120,
+ 485,
+ 174,
+ 405,
+ 514,
+ 984,
+ 200,
+ 723,
+ 867,
+ 259,
+ 997,
+ 191,
+ 340,
+ 75,
+ 763,
+ 579,
+ 216,
+ 154,
+ 331,
+ 338,
+ 184,
+ 786,
+ 56,
+ 235,
+ 880,
+ 810,
+ 544,
+ 522,
+ 358,
+ 219,
+ 566,
+ 632,
+ 422,
+ 636,
+ 760,
+ 657,
+ 117,
+ 138,
+ 228,
+ 163,
+ 336,
+ 572,
+ 722,
+ 438,
+ 280,
+ 234,
+ 454,
+ 967,
+ 148,
+ 325,
+ 142,
+ 790,
+ 3,
+ 497,
+ 770,
+ 936,
+ 101,
+ 696,
+ 108,
+ 255,
+ 140,
+ 320,
+ 29,
+ 36,
+ 228,
+ 468,
+ 24,
+ 183,
+ 844,
+ 513,
+ 856,
+ 102,
+ 9,
+ 526,
+ 50,
+ 73,
+ 366,
+ 599,
+ 246,
+ 662,
+ 473,
+ 651,
+ 568,
+ 575,
+ 972,
+ 352,
+ 341,
+ 897,
+ 15,
+ 73,
+ 764,
+ 768,
+ 879,
+ 886,
+ 906,
+ 718,
+ 621,
+ 529,
+ 282,
+ 339,
+ 165,
+ 137,
+ 999,
+ 215,
+ 33,
+ 639,
+ 999,
+ 906,
+ 210,
+ 62,
+ 655,
+ 996,
+ 675,
+ 552,
+ 333,
+ 176,
+ 426,
+ 891,
+ 638,
+ 571,
+ 715,
+ 18,
+ 708,
+ 795,
+ 26,
+ 31,
+ 250,
+ 18,
+ 949,
+ 183,
+ 968,
+ 394,
+ 580,
+ 766,
+ 686,
+ 162,
+ 134,
+ 185,
+ 943,
+ 919,
+ 577,
+ 539,
+ 180,
+ 750,
+ 285,
+ 591,
+ 881,
+ 381,
+ 118,
+ 852,
+ 696,
+ 617,
+ 941,
+ 767,
+ 592,
+ 650,
+ 74,
+ 961,
+ 881,
+ 891,
+ 71,
+ 905,
+ 575,
+ 598,
+ 523,
+ 477,
+ 561,
+ 948,
+ 762,
+ 570,
+ 773,
+ 146,
+ 894,
+ 203,
+ 610,
+ 471,
+ 669,
+ 189,
+ 473,
+ 650,
+ 606,
+ 385,
+ 288,
+ 360,
+ 648,
+ 115,
+ 836,
+ 139,
+ 530,
+ 248,
+ 331,
+ 286,
+ 849,
+ 812,
+ 356,
+ 884,
+ 33,
+ 57,
+ 147,
+ 297,
+ 826,
+ 916,
+ 581,
+ 0,
+ 918,
+ 81,
+ 12,
+ 956,
+ 309,
+ 550,
+ 15,
+ 243,
+ 294,
+ 893,
+ 290,
+ 227,
+ 826,
+ 843,
+ 789,
+ 744,
+ 494,
+ 742,
+ 643,
+ 126,
+ 861,
+ 444,
+ 506,
+ 417,
+ 215,
+ 246,
+ 9,
+ 244,
+ 283,
+ 595,
+ 635,
+ 494,
+ 612,
+ 737,
+ 311,
+ 896,
+ 834,
+ 222,
+ 121,
+ 595,
+ 680,
+ 309,
+ 729,
+ 263,
+ 142,
+ 804,
+ 262,
+ 343,
+ 179,
+ 649,
+ 118,
+ 360,
+ 536,
+ 669,
+ 429,
+ 359,
+ 667,
+ 313,
+ 671,
+ 506,
+ 951,
+ 461,
+ 291,
+ 359,
+ 237,
+ 727,
+ 143,
+ 968,
+ 769,
+ 97,
+ 842,
+ 752,
+ 803,
+ 299,
+ 154,
+ 384,
+ 23,
+ 567,
+ 339,
+ 778,
+ 492,
+ 116,
+ 320,
+ 967,
+ 526,
+ 66,
+ 761,
+ 908,
+ 345,
+ 885,
+ 193,
+ 894,
+ 547,
+ 124,
+ 18,
+ 254,
+ 947,
+ 192,
+ 111,
+ 384,
+ 204,
+ 338,
+ 574,
+ 749,
+ 816,
+ 717,
+ 457,
+ 353,
+ 163,
+ 979,
+ 896,
+ 679,
+ 342,
+ 932,
+ 100,
+ 216,
+ 531,
+ 320,
+ 122,
+ 594,
+ 956,
+ 638,
+ 450,
+ 733,
+ 643,
+ 293,
+ 891,
+ 633,
+ 901,
+ 815,
+ 676,
+ 307,
+ 144,
+ 286,
+ 106,
+ 182,
+ 605,
+ 575,
+ 129,
+ 390,
+ 212,
+ 843,
+ 225,
+ 544,
+ 468,
+ 203,
+ 223,
+ 862,
+ 795,
+ 36,
+ 348,
+ 743,
+ 528,
+ 904,
+ 126,
+ 802,
+ 82,
+ 156,
+ 369,
+ 986,
+ 332,
+ 977,
+ 570,
+ 421,
+ 345,
+ 401,
+ 480,
+ 63,
+ 518,
+ 667,
+ 31,
+ 909,
+ 552,
+ 994,
+ 314,
+ 891,
+ 642,
+ 439,
+ 132,
+ 670,
+ 402,
+ 263,
+ 140,
+ 549,
+ 905,
+ 712,
+ 299,
+ 986,
+ 86,
+ 709,
+ 786,
+ 47,
+ 679,
+ 864,
+ 13,
+ 140,
+ 659,
+ 479,
+ 838,
+ 988,
+ 846,
+ 855,
+ 367,
+ 935,
+ 657,
+ 453,
+ 400,
+ 851,
+ 749,
+ 500,
+ 673,
+ 523,
+ 708,
+ 568,
+ 76,
+ 18,
+ 589,
+ 689,
+ 195,
+ 504,
+ 402,
+ 835,
+ 705,
+ 187,
+ 615,
+ 482,
+ 160,
+ 609,
+ 761,
+ 907,
+ 294,
+ 538,
+ 545
+};
+const int ptr[501] = {
+ 0,
+ 4,
+ 8,
+ 10,
+ 15,
+ 22,
+ 29,
+ 33,
+ 34,
+ 36,
+ 39,
+ 44,
+ 44,
+ 47,
+ 55,
+ 61,
+ 66,
+ 68,
+ 75,
+ 82,
+ 86,
+ 91,
+ 98,
+ 104,
+ 109,
+ 113,
+ 126,
+ 131,
+ 134,
+ 136,
+ 143,
+ 153,
+ 159,
+ 168,
+ 170,
+ 174,
+ 176,
+ 180,
+ 187,
+ 192,
+ 198,
+ 200,
+ 204,
+ 211,
+ 213,
+ 222,
+ 225,
+ 228,
+ 233,
+ 241,
+ 247,
+ 253,
+ 256,
+ 262,
+ 264,
+ 270,
+ 274,
+ 277,
+ 283,
+ 288,
+ 294,
+ 301,
+ 307,
+ 312,
+ 315,
+ 319,
+ 325,
+ 329,
+ 332,
+ 338,
+ 340,
+ 342,
+ 348,
+ 353,
+ 359,
+ 362,
+ 366,
+ 368,
+ 374,
+ 387,
+ 393,
+ 400,
+ 403,
+ 406,
+ 412,
+ 420,
+ 425,
+ 428,
+ 433,
+ 441,
+ 442,
+ 448,
+ 456,
+ 462,
+ 468,
+ 469,
+ 477,
+ 479,
+ 485,
+ 490,
+ 495,
+ 501,
+ 508,
+ 513,
+ 518,
+ 524,
+ 532,
+ 535,
+ 538,
+ 542,
+ 546,
+ 552,
+ 561,
+ 563,
+ 567,
+ 571,
+ 574,
+ 576,
+ 581,
+ 584,
+ 588,
+ 592,
+ 593,
+ 597,
+ 599,
+ 607,
+ 612,
+ 615,
+ 619,
+ 626,
+ 633,
+ 640,
+ 646,
+ 650,
+ 653,
+ 659,
+ 665,
+ 670,
+ 673,
+ 678,
+ 685,
+ 691,
+ 697,
+ 703,
+ 708,
+ 712,
+ 717,
+ 719,
+ 722,
+ 725,
+ 732,
+ 736,
+ 738,
+ 742,
+ 747,
+ 753,
+ 757,
+ 763,
+ 767,
+ 769,
+ 769,
+ 777,
+ 780,
+ 784,
+ 790,
+ 797,
+ 807,
+ 810,
+ 813,
+ 815,
+ 817,
+ 822,
+ 829,
+ 830,
+ 835,
+ 844,
+ 848,
+ 851,
+ 854,
+ 862,
+ 864,
+ 873,
+ 876,
+ 881,
+ 884,
+ 888,
+ 895,
+ 899,
+ 901,
+ 904,
+ 908,
+ 912,
+ 919,
+ 927,
+ 931,
+ 937,
+ 941,
+ 944,
+ 948,
+ 950,
+ 955,
+ 960,
+ 963,
+ 970,
+ 975,
+ 979,
+ 983,
+ 985,
+ 992,
+ 993,
+ 998,
+ 1001,
+ 1008,
+ 1012,
+ 1014,
+ 1018,
+ 1023,
+ 1030,
+ 1036,
+ 1040,
+ 1045,
+ 1052,
+ 1058,
+ 1061,
+ 1066,
+ 1069,
+ 1071,
+ 1077,
+ 1080,
+ 1084,
+ 1087,
+ 1090,
+ 1092,
+ 1095,
+ 1100,
+ 1102,
+ 1110,
+ 1117,
+ 1122,
+ 1130,
+ 1133,
+ 1138,
+ 1142,
+ 1144,
+ 1146,
+ 1153,
+ 1158,
+ 1160,
+ 1167,
+ 1172,
+ 1176,
+ 1179,
+ 1183,
+ 1188,
+ 1191,
+ 1193,
+ 1196,
+ 1204,
+ 1210,
+ 1216,
+ 1219,
+ 1221,
+ 1225,
+ 1229,
+ 1234,
+ 1236,
+ 1239,
+ 1244,
+ 1248,
+ 1253,
+ 1256,
+ 1264,
+ 1268,
+ 1271,
+ 1272,
+ 1275,
+ 1278,
+ 1284,
+ 1287,
+ 1291,
+ 1296,
+ 1300,
+ 1304,
+ 1306,
+ 1313,
+ 1317,
+ 1322,
+ 1326,
+ 1332,
+ 1336,
+ 1344,
+ 1349,
+ 1356,
+ 1363,
+ 1368,
+ 1369,
+ 1378,
+ 1381,
+ 1385,
+ 1388,
+ 1395,
+ 1399,
+ 1407,
+ 1414,
+ 1422,
+ 1425,
+ 1433,
+ 1435,
+ 1438,
+ 1439,
+ 1445,
+ 1448,
+ 1450,
+ 1453,
+ 1456,
+ 1470,
+ 1472,
+ 1475,
+ 1481,
+ 1487,
+ 1491,
+ 1494,
+ 1497,
+ 1498,
+ 1503,
+ 1507,
+ 1513,
+ 1517,
+ 1524,
+ 1529,
+ 1534,
+ 1542,
+ 1547,
+ 1550,
+ 1550,
+ 1552,
+ 1553,
+ 1556,
+ 1559,
+ 1563,
+ 1571,
+ 1577,
+ 1580,
+ 1585,
+ 1590,
+ 1594,
+ 1598,
+ 1600,
+ 1602,
+ 1610,
+ 1615,
+ 1620,
+ 1628,
+ 1634,
+ 1637,
+ 1649,
+ 1652,
+ 1656,
+ 1662,
+ 1664,
+ 1670,
+ 1674,
+ 1678,
+ 1687,
+ 1697,
+ 1704,
+ 1709,
+ 1715,
+ 1720,
+ 1725,
+ 1728,
+ 1736,
+ 1740,
+ 1747,
+ 1750,
+ 1754,
+ 1760,
+ 1763,
+ 1765,
+ 1773,
+ 1781,
+ 1783,
+ 1788,
+ 1795,
+ 1802,
+ 1810,
+ 1815,
+ 1820,
+ 1824,
+ 1829,
+ 1836,
+ 1839,
+ 1843,
+ 1847,
+ 1849,
+ 1854,
+ 1859,
+ 1863,
+ 1873,
+ 1880,
+ 1882,
+ 1891,
+ 1895,
+ 1899,
+ 1904,
+ 1909,
+ 1914,
+ 1919,
+ 1923,
+ 1927,
+ 1932,
+ 1938,
+ 1943,
+ 1949,
+ 1954,
+ 1960,
+ 1965,
+ 1968,
+ 1974,
+ 1980,
+ 1983,
+ 1990,
+ 1992,
+ 1995,
+ 2002,
+ 2011,
+ 2017,
+ 2024,
+ 2028,
+ 2035,
+ 2037,
+ 2048,
+ 2055,
+ 2063,
+ 2067,
+ 2069,
+ 2078,
+ 2081,
+ 2085,
+ 2086,
+ 2090,
+ 2097,
+ 2101,
+ 2107,
+ 2110,
+ 2112,
+ 2116,
+ 2119,
+ 2122,
+ 2129,
+ 2136,
+ 2143,
+ 2146,
+ 2156,
+ 2162,
+ 2171,
+ 2175,
+ 2179,
+ 2186,
+ 2189,
+ 2194,
+ 2198,
+ 2206,
+ 2211,
+ 2215,
+ 2222,
+ 2228,
+ 2237,
+ 2241,
+ 2245,
+ 2256,
+ 2259,
+ 2269,
+ 2272,
+ 2275,
+ 2278,
+ 2279,
+ 2281,
+ 2287,
+ 2292,
+ 2297,
+ 2304,
+ 2311,
+ 2316,
+ 2319,
+ 2322,
+ 2327,
+ 2333,
+ 2340,
+ 2343,
+ 2345,
+ 2350,
+ 2358,
+ 2365,
+ 2365,
+ 2368,
+ 2373,
+ 2379,
+ 2388,
+ 2394,
+ 2399
+};
+const double verify_data[500] = {
+ 1636962,
+ 1714376,
+ 142636,
+ 1151015,
+ 1672341,
+ 2790420,
+ 1447201,
+ 422892,
+ 30953,
+ 1030287,
+ 1335188,
+ 0,
+ 605334,
+ 2278445,
+ 858848,
+ 245423,
+ 950882,
+ 705076,
+ 1312024,
+ 1084284,
+ 1837558,
+ 1201746,
+ 2360392,
+ 1488940,
+ 688178,
+ 2632122,
+ 1481444,
+ 660854,
+ 346453,
+ 982949,
+ 1400599,
+ 1093225,
+ 2856372,
+ 1078398,
+ 1074402,
+ 579548,
+ 1820752,
+ 2638601,
+ 2072665,
+ 749887,
+ 687788,
+ 478788,
+ 1482258,
+ 1207317,
+ 1397243,
+ 794364,
+ 1002505,
+ 1651686,
+ 1028801,
+ 1189726,
+ 1513197,
+ 1214956,
+ 738475,
+ 633771,
+ 1207042,
+ 680857,
+ 899314,
+ 2277406,
+ 773143,
+ 1986687,
+ 907216,
+ 907940,
+ 1539019,
+ 1043338,
+ 681730,
+ 219905,
+ 1397298,
+ 2184201,
+ 1537202,
+ 266744,
+ 563005,
+ 1827909,
+ 1105928,
+ 2286680,
+ 887533,
+ 343193,
+ 238910,
+ 1678393,
+ 2600003,
+ 417502,
+ 1551071,
+ 798273,
+ 398719,
+ 2056881,
+ 1296314,
+ 917292,
+ 190534,
+ 882078,
+ 1979139,
+ 50621,
+ 1048185,
+ 1967771,
+ 1911887,
+ 1895897,
+ 23343,
+ 2658748,
+ 285864,
+ 1027049,
+ 975769,
+ 2488413,
+ 832738,
+ 844130,
+ 1379856,
+ 1785889,
+ 2463463,
+ 782430,
+ 982466,
+ 609500,
+ 706251,
+ 1981399,
+ 1861430,
+ 2146667,
+ 250104,
+ 1166284,
+ 1295022,
+ 189599,
+ 855191,
+ 1005718,
+ 969658,
+ 707377,
+ 561273,
+ 86496,
+ 717937,
+ 97767,
+ 1893638,
+ 779229,
+ 429727,
+ 99564,
+ 1863565,
+ 2267656,
+ 950026,
+ 780700,
+ 581248,
+ 393282,
+ 2134865,
+ 1244700,
+ 1894843,
+ 954212,
+ 1439102,
+ 779512,
+ 1459287,
+ 881497,
+ 2202043,
+ 1447401,
+ 1249637,
+ 765168,
+ 488244,
+ 837127,
+ 1236555,
+ 2281259,
+ 1995666,
+ 25783,
+ 534020,
+ 1486259,
+ 1268571,
+ 875283,
+ 744594,
+ 1410335,
+ 757320,
+ 0,
+ 1922627,
+ 399058,
+ 1490594,
+ 1475527,
+ 1587557,
+ 1695667,
+ 644546,
+ 536038,
+ 224304,
+ 414120,
+ 2029077,
+ 3930385,
+ 377416,
+ 1059074,
+ 1960417,
+ 1439575,
+ 368749,
+ 460183,
+ 2479302,
+ 105204,
+ 1426355,
+ 649313,
+ 2194338,
+ 918200,
+ 1591449,
+ 2229266,
+ 434520,
+ 684504,
+ 1009270,
+ 222922,
+ 600674,
+ 1011867,
+ 1321434,
+ 836127,
+ 2493805,
+ 1448674,
+ 1269364,
+ 1304961,
+ 98554,
+ 2423810,
+ 1570229,
+ 302458,
+ 2806045,
+ 1534004,
+ 1463827,
+ 1085011,
+ 120989,
+ 1701753,
+ 110302,
+ 938429,
+ 1186733,
+ 2255246,
+ 425960,
+ 376311,
+ 341394,
+ 1061333,
+ 2025091,
+ 522270,
+ 598604,
+ 1000824,
+ 2254049,
+ 1857539,
+ 346425,
+ 1345187,
+ 550497,
+ 1251096,
+ 943720,
+ 681558,
+ 555972,
+ 779590,
+ 299796,
+ 1445763,
+ 459865,
+ 774572,
+ 489448,
+ 2407693,
+ 1574903,
+ 1630452,
+ 1907397,
+ 555045,
+ 1902494,
+ 1172223,
+ 142555,
+ 445864,
+ 1376151,
+ 1200389,
+ 327553,
+ 1548402,
+ 1106503,
+ 888650,
+ 41081,
+ 1245270,
+ 845610,
+ 1232215,
+ 387441,
+ 434475,
+ 1204003,
+ 1333189,
+ 1672468,
+ 567827,
+ 11392,
+ 631046,
+ 1299298,
+ 719608,
+ 714169,
+ 362247,
+ 1308257,
+ 530903,
+ 398202,
+ 885445,
+ 2606806,
+ 1354354,
+ 438760,
+ 194928,
+ 712863,
+ 1010340,
+ 2245646,
+ 376041,
+ 876890,
+ 1683404,
+ 955032,
+ 1065455,
+ 925034,
+ 1731713,
+ 1152271,
+ 2093865,
+ 1221433,
+ 629438,
+ 2054936,
+ 2643313,
+ 1322567,
+ 1492288,
+ 1844514,
+ 1802382,
+ 871,
+ 1350044,
+ 967406,
+ 756881,
+ 574442,
+ 1295864,
+ 1815978,
+ 2822668,
+ 2201377,
+ 2729436,
+ 616018,
+ 2318346,
+ 332717,
+ 289665,
+ 97812,
+ 1881483,
+ 1003188,
+ 702530,
+ 409314,
+ 645118,
+ 3645947,
+ 723792,
+ 503126,
+ 1609036,
+ 1647277,
+ 587437,
+ 735899,
+ 666552,
+ 27354,
+ 1045106,
+ 397951,
+ 1087090,
+ 1173872,
+ 1629962,
+ 1334261,
+ 1855668,
+ 2856970,
+ 1341188,
+ 336968,
+ 0,
+ 521349,
+ 53118,
+ 881926,
+ 154917,
+ 942966,
+ 1237636,
+ 820836,
+ 579583,
+ 1436861,
+ 2025006,
+ 634434,
+ 829152,
+ 298073,
+ 205380,
+ 1622350,
+ 1171051,
+ 848451,
+ 2417009,
+ 2016092,
+ 390510,
+ 2721874,
+ 359761,
+ 309038,
+ 1061522,
+ 297026,
+ 1311767,
+ 305305,
+ 854945,
+ 1773244,
+ 2656339,
+ 896058,
+ 1069160,
+ 1552917,
+ 1421821,
+ 440874,
+ 216699,
+ 1654864,
+ 521705,
+ 807422,
+ 1242602,
+ 1329872,
+ 308130,
+ 526463,
+ 27937,
+ 1450630,
+ 1621987,
+ 799154,
+ 1378289,
+ 2519996,
+ 1149046,
+ 579937,
+ 1841561,
+ 1895047,
+ 1009234,
+ 1922198,
+ 2570006,
+ 409696,
+ 442495,
+ 277484,
+ 979605,
+ 1392287,
+ 1023715,
+ 1881778,
+ 2432703,
+ 2297384,
+ 542451,
+ 1368100,
+ 833048,
+ 1038108,
+ 742376,
+ 1542317,
+ 2230186,
+ 1249077,
+ 884020,
+ 1286059,
+ 1102407,
+ 1651393,
+ 1787846,
+ 1370154,
+ 2734166,
+ 2935249,
+ 447485,
+ 736859,
+ 828966,
+ 1547038,
+ 765990,
+ 1427773,
+ 255456,
+ 134871,
+ 1597546,
+ 2173052,
+ 1187286,
+ 2364828,
+ 1220233,
+ 1760369,
+ 75080,
+ 2799969,
+ 1363310,
+ 2347168,
+ 272279,
+ 33698,
+ 1192053,
+ 342501,
+ 356092,
+ 136578,
+ 1701048,
+ 2216796,
+ 1340150,
+ 1852854,
+ 580862,
+ 407410,
+ 1860346,
+ 200649,
+ 954363,
+ 955621,
+ 2234154,
+ 2007706,
+ 646339,
+ 2712491,
+ 1259244,
+ 2368138,
+ 1550431,
+ 1160903,
+ 987838,
+ 650293,
+ 833228,
+ 368144,
+ 1998925,
+ 1733716,
+ 1050000,
+ 1061635,
+ 1144649,
+ 1260205,
+ 851043,
+ 1417512,
+ 2826918,
+ 1059350,
+ 1522135,
+ 1039943,
+ 703837,
+ 1035006,
+ 19505,
+ 211545,
+ 1461101,
+ 1238659,
+ 1414306,
+ 1151385,
+ 2169011,
+ 1101116,
+ 1118290,
+ 335296,
+ 1502266,
+ 1405699,
+ 1762457,
+ 530338,
+ 246108,
+ 484583,
+ 2164048,
+ 1614511,
+ 0,
+ 1446940,
+ 575450,
+ 2043329,
+ 2057251,
+ 774670,
+ 1084124
+};
diff --git a/sw/app/spmv/spmv_gendata.scala b/sw/app/spmv/spmv_gendata.scala
new file mode 100644
index 00000000..f777445f
--- /dev/null
+++ b/sw/app/spmv/spmv_gendata.scala
@@ -0,0 +1,48 @@
+#!/usr/bin/env scala
+!#
+
+val m = args(0).toInt
+val n = args(1).toInt
+val approx_nnz = args(2).toInt
+
+val pnnz = approx_nnz.toDouble/(m*n)
+val idx = collection.mutable.ArrayBuffer[Int]()
+val p = collection.mutable.ArrayBuffer(0)
+
+for (i <- 0 until m) {
+ for (j <- 0 until n) {
+ if (util.Random.nextDouble < pnnz)
+ idx += j
+ }
+ p += idx.length
+}
+
+val nnz = idx.length
+val v = Array.tabulate(n)(i => util.Random.nextInt(1000))
+val d = Array.tabulate(nnz)(i => util.Random.nextInt(1000))
+
+def printVec(t: String, name: String, data: Seq[Int]) = {
+ println("const " + t + " " + name + "[" + data.length + "] = {")
+ println(" "+data.map(_.toString).reduceLeft(_+",\n "+_))
+ println("};")
+}
+
+def spmv(p: Seq[Int], d: Seq[Int], idx: Seq[Int], v: Seq[Int]) = {
+ val y = collection.mutable.ArrayBuffer[Int]()
+ for (i <- 0 until p.length-1) {
+ var yi = 0
+ for (k <- p(i) until p(i+1))
+ yi = yi + d(k)*v(idx(k))
+ y += yi
+ }
+ y
+}
+
+println("#define R " + m)
+println("#define C " + n)
+println("#define NNZ " + nnz)
+printVec("double", "val", d)
+printVec("int", "idx", idx)
+printVec("double", "x", v)
+printVec("int", "ptr", p)
+printVec("double", "verify_data", spmv(p, d, idx, v))
diff --git a/sw/app/spmv/spmv_main.c b/sw/app/spmv/spmv_main.c
new file mode 100644
index 00000000..28a218e3
--- /dev/null
+++ b/sw/app/spmv/spmv_main.c
@@ -0,0 +1,73 @@
+// See LICENSE for license details.
+
+//**************************************************************************
+// Double-precision sparse matrix-vector multiplication benchmark
+//--------------------------------------------------------------------------
+
+#include "util.h"
+
+
+#define NUM_COUNTERS 2
+static uintptr_t counters[NUM_COUNTERS];
+static char* counter_names[NUM_COUNTERS];
+
+
+void setStats(int enable)
+{
+ int i = 0;
+#define READ_CTR(name) do { \
+ while (i >= NUM_COUNTERS) ; \
+ uintptr_t csr = read_csr(name); \
+ if (!enable) { csr -= counters[i]; counter_names[i] = #name; } \
+ counters[i++] = csr; \
+ } while (0)
+
+ READ_CTR(mcycle);
+ READ_CTR(minstret);
+
+#undef READ_CTR
+}
+//--------------------------------------------------------------------------
+// Input/Reference Data
+
+#include "dataset1.h"
+
+void spmv(int r, const double* val, const int* idx, const double* x,
+ const int* ptr, double* y)
+{
+ for (int i = 0; i < r; i++)
+ {
+ int k;
+ double yi0 = 0, yi1 = 0, yi2 = 0, yi3 = 0;
+ for (k = ptr[i]; k < ptr[i+1]-3; k+=4)
+ {
+ yi0 += val[k+0]*x[idx[k+0]];
+ yi1 += val[k+1]*x[idx[k+1]];
+ yi2 += val[k+2]*x[idx[k+2]];
+ yi3 += val[k+3]*x[idx[k+3]];
+ }
+ for ( ; k < ptr[i+1]; k++)
+ {
+ yi0 += val[k]*x[idx[k]];
+ }
+ y[i] = (yi0+yi1)+(yi2+yi3);
+ }
+}
+
+//--------------------------------------------------------------------------
+// Main
+
+int main( int argc, char* argv[] )
+{
+ double y[R];
+
+#if PREALLOCATE
+ spmv(R, val, idx, x, ptr, y);
+#endif
+
+ setStats(1);
+ spmv(R, val, idx, x, ptr, y);
+ setStats(0);
+
+ return verifyDouble(R, y, verify_data);
+}
diff --git a/sw/app/towers/towers_main.c b/sw/app/towers/towers_main.c
new file mode 100644
index 00000000..c609d7c5
--- /dev/null
+++ b/sw/app/towers/towers_main.c
@@ -0,0 +1,256 @@
+// See LICENSE for license details.
+
+//**************************************************************************
+// Towers of Hanoi benchmark
+//--------------------------------------------------------------------------
+//
+// Towers of Hanoi is a classic puzzle problem. The game consists of
+// three pegs and a set of discs. Each disc is a different size, and
+// initially all of the discs are on the left most peg with the smallest
+// disc on top and the largest disc on the bottom. The goal is to move all
+// of the discs onto the right most peg. The catch is that you are only
+// allowed to move one disc at a time and you can never place a larger
+// disc on top of a smaller disc.
+//
+// This implementation starts with NUM_DISC discs and uses a recursive
+// algorithm to sovel the puzzle.
+
+#include "util.h"
+
+
+#define NUM_COUNTERS 2
+static uintptr_t counters[NUM_COUNTERS];
+static char* counter_names[NUM_COUNTERS];
+
+
+void setStats(int enable)
+{
+ int i = 0;
+#define READ_CTR(name) do { \
+ while (i >= NUM_COUNTERS) ; \
+ uintptr_t csr = read_csr(name); \
+ if (!enable) { csr -= counters[i]; counter_names[i] = #name; } \
+ counters[i++] = csr; \
+ } while (0)
+
+ READ_CTR(mcycle);
+ READ_CTR(minstret);
+
+#undef READ_CTR
+}
+
+// This is the number of discs in the puzzle.
+
+#define NUM_DISCS 7
+
+//--------------------------------------------------------------------------
+// List data structure and functions
+
+struct Node
+{
+ int val;
+ struct Node* next;
+};
+
+struct List
+{
+ int size;
+ struct Node* head;
+};
+
+struct List g_nodeFreeList;
+struct Node g_nodePool[NUM_DISCS];
+
+int list_getSize( struct List* list )
+{
+ return list->size;
+}
+
+void list_init( struct List* list )
+{
+ list->size = 0;
+ list->head = 0;
+}
+
+void list_push( struct List* list, int val )
+{
+ struct Node* newNode;
+
+ // Pop the next free node off the free list
+ newNode = g_nodeFreeList.head;
+ g_nodeFreeList.head = g_nodeFreeList.head->next;
+
+ // Push the new node onto the given list
+ newNode->next = list->head;
+ list->head = newNode;
+
+ // Assign the value
+ list->head->val = val;
+
+ // Increment size
+ list->size++;
+
+}
+
+int list_pop( struct List* list )
+{
+ struct Node* freedNode;
+ int val;
+
+ // Get the value from the->head of given list
+ val = list->head->val;
+
+ // Pop the head node off the given list
+ freedNode = list->head;
+ list->head = list->head->next;
+
+ // Push the freed node onto the free list
+ freedNode->next = g_nodeFreeList.head;
+ g_nodeFreeList.head = freedNode;
+
+ // Decrement size
+ list->size--;
+
+ return val;
+}
+
+void list_clear( struct List* list )
+{
+ while ( list_getSize(list) > 0 )
+ list_pop(list);
+}
+
+//--------------------------------------------------------------------------
+// Tower data structure and functions
+
+struct Towers
+{
+ int numDiscs;
+ int numMoves;
+ struct List pegA;
+ struct List pegB;
+ struct List pegC;
+};
+
+void towers_init( struct Towers* this, int n )
+{
+ int i;
+
+ this->numDiscs = n;
+ this->numMoves = 0;
+
+ list_init( &(this->pegA) );
+ list_init( &(this->pegB) );
+ list_init( &(this->pegC) );
+
+ for ( i = 0; i < n; i++ )
+ list_push( &(this->pegA), n-i );
+
+}
+
+void towers_clear( struct Towers* this )
+{
+
+ list_clear( &(this->pegA) );
+ list_clear( &(this->pegB) );
+ list_clear( &(this->pegC) );
+
+ towers_init( this, this->numDiscs );
+
+}
+
+void towers_solve_h( struct Towers* this, int n,
+ struct List* startPeg,
+ struct List* tempPeg,
+ struct List* destPeg )
+{
+ int val;
+
+ if ( n == 1 ) {
+ val = list_pop(startPeg);
+ list_push(destPeg,val);
+ this->numMoves++;
+ }
+ else {
+ towers_solve_h( this, n-1, startPeg, destPeg, tempPeg );
+ towers_solve_h( this, 1, startPeg, tempPeg, destPeg );
+ towers_solve_h( this, n-1, tempPeg, startPeg, destPeg );
+ }
+
+}
+
+void towers_solve( struct Towers* this )
+{
+ towers_solve_h( this, this->numDiscs, &(this->pegA), &(this->pegB), &(this->pegC) );
+}
+
+int towers_verify( struct Towers* this )
+{
+ struct Node* ptr;
+ int numDiscs = 0;
+
+ if ( list_getSize(&this->pegA) != 0 ) {
+ return 2;
+ }
+
+ if ( list_getSize(&this->pegB) != 0 ) {
+ return 3;
+ }
+
+ if ( list_getSize(&this->pegC) != this->numDiscs ) {
+ return 4;
+ }
+
+ for ( ptr = this->pegC.head; ptr != 0; ptr = ptr->next ) {
+ numDiscs++;
+ if ( ptr->val != numDiscs ) {
+ return 5;
+ }
+ }
+
+ if ( this->numMoves != ((1 << this->numDiscs) - 1) ) {
+ return 6;
+ }
+
+ return 0;
+}
+
+//--------------------------------------------------------------------------
+// Main
+
+int main( int argc, char* argv[] )
+{
+ struct Towers towers;
+ int i;
+
+ // Initialize free list
+
+ list_init( &g_nodeFreeList );
+ g_nodeFreeList.head = &(g_nodePool[0]);
+ g_nodeFreeList.size = NUM_DISCS;
+ g_nodePool[NUM_DISCS-1].next = 0;
+ g_nodePool[NUM_DISCS-1].val = 99;
+ for ( i = 0; i < (NUM_DISCS-1); i++ ) {
+ g_nodePool[i].next = &(g_nodePool[i+1]);
+ g_nodePool[i].val = i;
+ }
+
+ towers_init( &towers, NUM_DISCS );
+
+ // If needed we preallocate everything in the caches
+
+#if PREALLOCATE
+ towers_solve( &towers );
+#endif
+
+ // Solve it
+
+ towers_clear( &towers );
+ setStats(1);
+ towers_solve( &towers );
+ setStats(0);
+
+ // Check the results
+ return towers_verify( &towers );
+}
+
diff --git a/sw/app/vvadd/dataset1-large.h b/sw/app/vvadd/dataset1-large.h
new file mode 100644
index 00000000..5a008c12
--- /dev/null
+++ b/sw/app/vvadd/dataset1-large.h
@@ -0,0 +1,167 @@
+// See LICENSE for license details.
+
+
+#define DATA_SIZE 1000
+
+int input1_data[DATA_SIZE] =
+{
+ 41, 833, 564, 187, 749, 350, 132, 949, 584, 805, 621, 6, 931, 890, 392, 694, 961, 110, 116, 296,
+ 426, 314, 659, 774, 319, 678, 875, 376, 474, 938, 539, 569, 203, 280, 759, 606, 511, 657, 195, 81,
+ 267, 229, 337, 944, 902, 241, 913, 826, 933, 985, 195, 960, 566, 350, 649, 657, 181, 111, 859, 65,
+ 288, 349, 141, 905, 886, 264, 576, 979, 761, 241, 478, 499, 403, 222, 444, 721, 676, 317, 224, 937,
+ 288, 119, 615, 606, 389, 351, 455, 278, 367, 358, 584, 62, 985, 403, 346, 517, 559, 908, 775, 255,
+ 778, 598, 143, 33, 125, 941, 933, 799, 553, 431, 648, 952, 287, 19, 49, 86, 95, 441, 587, 614,
+ 382, 280, 808, 971, 819, 344, 450, 512, 965, 347, 808, 882, 537, 946, 701, 356, 567, 891, 22, 568,
+ 665, 423, 434, 158, 2, 84, 247, 49, 435, 792, 869, 486, 414, 369, 548, 518, 888, 682, 284, 264,
+ 499, 290, 897, 215, 731, 688, 251, 786, 555, 302, 528, 544, 322, 947, 287, 824, 304, 788, 733, 959,
+ 366, 722, 294, 975, 653, 748, 91, 378, 105, 102, 381, 651, 825, 840, 356, 148, 54, 140, 955, 343,
+ 533, 757, 521, 837, 592, 13, 173, 63, 121, 133, 758, 372, 951, 39, 129, 110, 847, 437, 255, 269,
+ 409, 628, 399, 549, 753, 564, 171, 19, 727, 501, 777, 43, 753, 81, 202, 853, 153, 760, 357, 943,
+ 922, 328, 496, 442, 516, 641, 276, 786, 113, 842, 907, 275, 237, 32, 784, 565, 357, 803, 819, 751,
+ 280, 85, 458, 454, 710, 459, 41, 253, 377, 508, 700, 860, 480, 741, 499, 709, 49, 371, 873, 945,
+ 992, 526, 721, 435, 232, 497, 697, 30, 348, 250, 350, 250, 573, 784, 749, 502, 823, 826, 170, 160,
+ 674, 32, 202, 143, 853, 90, 394, 107, 855, 106, 157, 6, 765, 204, 194, 574, 218, 526, 177, 239,
+ 698, 757, 706, 49, 84, 799, 893, 512, 373, 492, 14, 621, 83, 103, 794, 921, 643, 880, 834, 239,
+ 462, 114, 561, 529, 10, 997, 904, 387, 407, 105, 559, 936, 512, 409, 302, 202, 427, 613, 359, 521,
+ 684, 22, 185, 312, 107, 274, 387, 242, 486, 105, 698, 899, 770, 644, 80, 161, 407, 946, 30, 768,
+ 870, 113, 148, 62, 147, 838, 845, 432, 141, 211, 817, 821, 562, 364, 615, 495, 812, 916, 159, 430,
+ 803, 180, 544, 840, 458, 786, 872, 795, 806, 758, 104, 401, 254, 984, 136, 729, 584, 794, 414, 528,
+ 707, 554, 378, 766, 977, 236, 947, 229, 165, 505, 105, 704, 796, 140, 303, 795, 635, 560, 119, 8,
+ 532, 814, 37, 584, 739, 619, 767, 478, 57, 958, 784, 985, 837, 307, 67, 824, 996, 749, 171, 826,
+ 621, 155, 826, 43, 694, 80, 236, 747, 744, 265, 124, 731, 941, 425, 370, 320, 269, 542, 763, 752,
+ 915, 14, 1, 906, 995, 809, 560, 873, 972, 289, 509, 558, 970, 405, 579, 293, 251, 849, 129, 452,
+ 716, 86, 678, 181, 240, 335, 793, 641, 1, 320, 987, 646, 754, 958, 203, 142, 180, 299, 165, 761,
+ 974, 646, 559, 619, 422, 260, 565, 542, 492, 991, 745, 207, 372, 932, 664, 34, 533, 478, 908, 203,
+ 33, 214, 365, 892, 781, 680, 705, 688, 947, 386, 50, 101, 474, 399, 679, 330, 952, 471, 477, 725,
+ 713, 937, 529, 870, 77, 545, 907, 853, 143, 979, 239, 105, 365, 98, 54, 98, 440, 764, 315, 336,
+ 697, 774, 726, 324, 282, 536, 622, 594, 890, 75, 290, 496, 726, 449, 548, 135, 644, 838, 290, 767,
+ 162, 415, 491, 985, 116, 617, 859, 235, 282, 571, 913, 560, 194, 242, 782, 985, 728, 344, 430, 613,
+ 759, 176, 309, 333, 354, 310, 699, 46, 487, 503, 100, 393, 268, 314, 75, 345, 987, 600, 908, 384,
+ 92, 545, 277, 668, 351, 853, 863, 312, 100, 532, 567, 836, 370, 989, 461, 912, 182, 268, 160, 771,
+ 22, 854, 644, 17, 779, 911, 855, 137, 983, 717, 565, 719, 253, 785, 154, 196, 253, 447, 899, 5,
+ 325, 616, 309, 175, 159, 123, 838, 715, 550, 230, 82, 627, 324, 927, 103, 17, 966, 159, 177, 593,
+ 372, 393, 599, 745, 377, 865, 591, 553, 440, 345, 593, 290, 908, 544, 377, 456, 781, 110, 495, 896,
+ 806, 700, 548, 340, 29, 829, 630, 546, 613, 972, 116, 313, 904, 971, 607, 794, 169, 896, 507, 916,
+ 431, 339, 147, 224, 112, 580, 834, 134, 948, 201, 488, 396, 797, 478, 769, 574, 485, 339, 721, 451,
+ 821, 744, 0, 594, 277, 120, 680, 757, 555, 847, 517, 379, 505, 904, 246, 243, 394, 430, 214, 244,
+ 524, 399, 172, 304, 620, 594, 535, 698, 159, 750, 809, 454, 75, 93, 167, 16, 853, 494, 324, 78,
+ 52, 112, 10, 342, 730, 680, 287, 961, 92, 626, 912, 616, 860, 744, 744, 478, 615, 508, 914, 810,
+ 288, 974, 129, 581, 548, 868, 981, 270, 623, 653, 626, 990, 386, 323, 472, 164, 239, 189, 865, 231,
+ 356, 152, 825, 328, 390, 848, 38, 402, 616, 546, 206, 2, 783, 890, 815, 831, 665, 410, 94, 246,
+ 422, 211, 675, 9, 374, 426, 64, 53, 758, 811, 500, 437, 335, 328, 237, 415, 468, 684, 565, 305,
+ 449, 597, 136, 882, 383, 938, 268, 115, 908, 50, 952, 366, 397, 257, 231, 667, 35, 990, 443, 213,
+ 389, 13, 621, 52, 612, 934, 953, 828, 462, 621, 812, 522, 672, 57, 313, 352, 55, 972, 753, 416,
+ 879, 864, 572, 163, 721, 12, 643, 507, 968, 781, 840, 242, 630, 810, 795, 435, 885, 599, 696, 643,
+ 93, 710, 785, 112, 581, 12, 923, 615, 652, 359, 261, 233, 609, 686, 539, 118, 560, 739, 20, 317,
+ 976, 573, 386, 772, 663, 504, 212, 888, 907, 420, 737, 516, 25, 219, 797, 716, 452, 692, 683, 459,
+ 815, 323, 612, 247, 116, 352, 281, 738, 290, 909, 645, 625, 932, 220, 685, 373, 876, 646, 412, 955
+};
+
+int input2_data[DATA_SIZE] =
+{
+ 454, 335, 1, 989, 365, 572, 64, 153, 216, 140, 210, 572, 339, 593, 898, 228, 12, 883, 750, 646,
+ 500, 436, 701, 812, 981, 150, 696, 564, 272, 258, 647, 509, 88, 703, 669, 375, 551, 936, 592, 569,
+ 952, 800, 584, 643, 368, 489, 328, 313, 592, 388, 543, 649, 979, 997, 814, 79, 208, 998, 629, 847,
+ 704, 997, 253, 715, 430, 415, 538, 700, 4, 494, 100, 864, 693, 416, 296, 285, 620, 78, 351, 540,
+ 646, 169, 527, 289, 796, 801, 720, 758, 745, 92, 989, 271, 853, 788, 531, 222, 461, 241, 358, 332,
+ 684, 740, 446, 311, 743, 557, 479, 557, 925, 796, 357, 891, 666, 514, 557, 870, 853, 440, 61, 678,
+ 396, 9, 17, 170, 291, 380, 536, 185, 917, 539, 983, 887, 54, 612, 951, 479, 151, 7, 641, 335,
+ 730, 95, 728, 280, 395, 688, 911, 476, 815, 729, 265, 127, 236, 214, 180, 6, 503, 596, 173, 643,
+ 346, 599, 68, 849, 658, 619, 121, 131, 828, 667, 433, 487, 753, 125, 626, 14, 10, 403, 106, 703,
+ 818, 964, 406, 874, 856, 86, 60, 660, 667, 153, 121, 98, 412, 236, 12, 423, 965, 216, 621, 361,
+ 921, 715, 647, 299, 886, 682, 36, 493, 551, 537, 969, 643, 434, 415, 303, 438, 860, 203, 478, 988,
+ 675, 719, 990, 338, 450, 633, 155, 646, 452, 427, 509, 988, 426, 12, 483, 142, 339, 390, 50, 171,
+ 601, 105, 968, 121, 879, 81, 870, 600, 603, 871, 887, 610, 404, 234, 745, 526, 275, 441, 226, 752,
+ 943, 726, 709, 201, 54, 758, 53, 397, 41, 141, 416, 747, 219, 478, 770, 180, 482, 691, 725, 173,
+ 186, 914, 1, 963, 247, 464, 362, 521, 233, 120, 40, 779, 195, 161, 743, 439, 355, 403, 141, 633,
+ 289, 782, 320, 636, 118, 852, 70, 816, 388, 954, 36, 16, 698, 695, 677, 598, 883, 824, 746, 462,
+ 511, 534, 440, 428, 732, 726, 702, 547, 86, 798, 215, 21, 651, 59, 429, 657, 96, 973, 659, 966,
+ 524, 62, 625, 303, 714, 409, 55, 728, 305, 436, 901, 592, 691, 796, 497, 177, 940, 995, 480, 158,
+ 822, 611, 680, 14, 111, 797, 185, 0, 718, 96, 749, 739, 814, 435, 326, 37, 33, 605, 935, 27,
+ 88, 441, 339, 344, 554, 365, 954, 639, 396, 991, 249, 338, 832, 974, 393, 266, 470, 348, 336, 419,
+ 249, 215, 542, 903, 636, 729, 581, 820, 671, 979, 418, 670, 920, 568, 745, 662, 139, 385, 927, 173,
+ 457, 316, 183, 477, 196, 399, 416, 805, 996, 270, 735, 696, 825, 528, 50, 623, 537, 87, 294, 867,
+ 110, 398, 781, 646, 375, 943, 897, 589, 44, 288, 845, 742, 99, 522, 443, 432, 165, 930, 28, 461,
+ 323, 272, 376, 340, 898, 158, 168, 443, 193, 631, 935, 274, 781, 185, 619, 292, 933, 156, 827, 88,
+ 987, 629, 649, 32, 1, 744, 399, 915, 791, 554, 984, 530, 600, 401, 683, 540, 903, 120, 995, 521,
+ 622, 224, 895, 530, 820, 651, 226, 96, 262, 569, 238, 126, 610, 191, 238, 796, 884, 573, 108, 140,
+ 789, 852, 23, 704, 890, 480, 52, 372, 201, 546, 408, 119, 645, 464, 81, 293, 52, 880, 224, 744,
+ 735, 886, 167, 1, 532, 321, 169, 485, 101, 177, 42, 708, 654, 915, 625, 242, 822, 795, 641, 252,
+ 245, 151, 876, 333, 601, 938, 775, 397, 233, 755, 454, 424, 210, 962, 900, 923, 655, 529, 595, 90,
+ 464, 685, 70, 754, 32, 494, 25, 389, 488, 37, 409, 639, 27, 950, 539, 80, 303, 723, 734, 125,
+ 552, 248, 107, 362, 48, 869, 144, 841, 724, 335, 470, 263, 343, 809, 677, 339, 336, 410, 465, 56,
+ 590, 485, 406, 993, 746, 238, 525, 336, 256, 134, 546, 722, 367, 943, 106, 629, 396, 208, 429, 523,
+ 130, 355, 990, 673, 991, 719, 449, 84, 616, 211, 707, 737, 847, 452, 316, 974, 746, 796, 522, 618,
+ 115, 727, 226, 165, 200, 830, 742, 187, 705, 671, 785, 886, 962, 657, 293, 620, 144, 173, 796, 72,
+ 678, 80, 793, 685, 637, 967, 241, 898, 693, 372, 601, 721, 398, 553, 72, 174, 978, 325, 558, 185,
+ 505, 859, 651, 573, 321, 349, 400, 890, 844, 885, 933, 980, 448, 989, 50, 332, 900, 716, 747, 444,
+ 6, 394, 285, 703, 450, 652, 771, 485, 534, 559, 481, 507, 434, 343, 42, 784, 865, 421, 415, 871,
+ 539, 162, 105, 481, 595, 115, 350, 964, 287, 232, 154, 602, 539, 943, 872, 121, 652, 811, 747, 362,
+ 340, 910, 206, 572, 505, 973, 961, 354, 627, 849, 971, 910, 410, 770, 63, 874, 396, 482, 619, 646,
+ 557, 328, 67, 884, 512, 972, 6, 513, 882, 562, 764, 366, 506, 786, 831, 382, 638, 452, 72, 83,
+ 59, 932, 929, 924, 961, 69, 797, 985, 854, 885, 600, 389, 232, 793, 179, 773, 689, 775, 494, 139,
+ 234, 431, 780, 371, 22, 653, 741, 815, 428, 139, 603, 315, 344, 889, 317, 260, 861, 377, 511, 304,
+ 70, 35, 854, 576, 490, 326, 303, 431, 813, 708, 388, 962, 967, 442, 49, 831, 251, 321, 741, 179,
+ 176, 117, 523, 764, 952, 704, 531, 804, 23, 611, 846, 375, 854, 971, 24, 639, 318, 723, 662, 647,
+ 281, 158, 294, 885, 734, 866, 471, 296, 673, 472, 439, 5, 155, 506, 948, 600, 445, 222, 784, 349,
+ 943, 150, 366, 444, 604, 720, 340, 972, 911, 321, 435, 50, 78, 761, 950, 238, 27, 226, 201, 176,
+ 877, 450, 879, 99, 143, 31, 812, 771, 527, 488, 797, 194, 293, 966, 276, 345, 413, 197, 386, 116,
+ 322, 680, 538, 553, 960, 874, 48, 506, 898, 539, 495, 764, 805, 286, 432, 836, 192, 825, 778, 586,
+ 359, 352, 746, 11, 749, 5, 408, 643, 441, 368, 97, 169, 359, 527, 672, 69, 880, 298, 300, 327,
+ 923, 829, 816, 497, 243, 981, 917, 713, 653, 503, 406, 543, 108, 304, 464, 954, 86, 802, 446, 28
+};
+
+int verify_data[DATA_SIZE] =
+{
+ 495, 1168, 565, 1176, 1114, 922, 196, 1102, 800, 945, 831, 578, 1270, 1483, 1290, 922, 973, 993, 866, 942,
+ 926, 750, 1360, 1586, 1300, 828, 1571, 940, 746, 1196, 1186, 1078, 291, 983, 1428, 981, 1062, 1593, 787, 650,
+ 1219, 1029, 921, 1587, 1270, 730, 1241, 1139, 1525, 1373, 738, 1609, 1545, 1347, 1463, 736, 389, 1109, 1488, 912,
+ 992, 1346, 394, 1620, 1316, 679, 1114, 1679, 765, 735, 578, 1363, 1096, 638, 740, 1006, 1296, 395, 575, 1477,
+ 934, 288, 1142, 895, 1185, 1152, 1175, 1036, 1112, 450, 1573, 333, 1838, 1191, 877, 739, 1020, 1149, 1133, 587,
+ 1462, 1338, 589, 344, 868, 1498, 1412, 1356, 1478, 1227, 1005, 1843, 953, 533, 606, 956, 948, 881, 648, 1292,
+ 778, 289, 825, 1141, 1110, 724, 986, 697, 1882, 886, 1791, 1769, 591, 1558, 1652, 835, 718, 898, 663, 903,
+ 1395, 518, 1162, 438, 397, 772, 1158, 525, 1250, 1521, 1134, 613, 650, 583, 728, 524, 1391, 1278, 457, 907,
+ 845, 889, 965, 1064, 1389, 1307, 372, 917, 1383, 969, 961, 1031, 1075, 1072, 913, 838, 314, 1191, 839, 1662,
+ 1184, 1686, 700, 1849, 1509, 834, 151, 1038, 772, 255, 502, 749, 1237, 1076, 368, 571, 1019, 356, 1576, 704,
+ 1454, 1472, 1168, 1136, 1478, 695, 209, 556, 672, 670, 1727, 1015, 1385, 454, 432, 548, 1707, 640, 733, 1257,
+ 1084, 1347, 1389, 887, 1203, 1197, 326, 665, 1179, 928, 1286, 1031, 1179, 93, 685, 995, 492, 1150, 407, 1114,
+ 1523, 433, 1464, 563, 1395, 722, 1146, 1386, 716, 1713, 1794, 885, 641, 266, 1529, 1091, 632, 1244, 1045, 1503,
+ 1223, 811, 1167, 655, 764, 1217, 94, 650, 418, 649, 1116, 1607, 699, 1219, 1269, 889, 531, 1062, 1598, 1118,
+ 1178, 1440, 722, 1398, 479, 961, 1059, 551, 581, 370, 390, 1029, 768, 945, 1492, 941, 1178, 1229, 311, 793,
+ 963, 814, 522, 779, 971, 942, 464, 923, 1243, 1060, 193, 22, 1463, 899, 871, 1172, 1101, 1350, 923, 701,
+ 1209, 1291, 1146, 477, 816, 1525, 1595, 1059, 459, 1290, 229, 642, 734, 162, 1223, 1578, 739, 1853, 1493, 1205,
+ 986, 176, 1186, 832, 724, 1406, 959, 1115, 712, 541, 1460, 1528, 1203, 1205, 799, 379, 1367, 1608, 839, 679,
+ 1506, 633, 865, 326, 218, 1071, 572, 242, 1204, 201, 1447, 1638, 1584, 1079, 406, 198, 440, 1551, 965, 795,
+ 958, 554, 487, 406, 701, 1203, 1799, 1071, 537, 1202, 1066, 1159, 1394, 1338, 1008, 761, 1282, 1264, 495, 849,
+ 1052, 395, 1086, 1743, 1094, 1515, 1453, 1615, 1477, 1737, 522, 1071, 1174, 1552, 881, 1391, 723, 1179, 1341, 701,
+ 1164, 870, 561, 1243, 1173, 635, 1363, 1034, 1161, 775, 840, 1400, 1621, 668, 353, 1418, 1172, 647, 413, 875,
+ 642, 1212, 818, 1230, 1114, 1562, 1664, 1067, 101, 1246, 1629, 1727, 936, 829, 510, 1256, 1161, 1679, 199, 1287,
+ 944, 427, 1202, 383, 1592, 238, 404, 1190, 937, 896, 1059, 1005, 1722, 610, 989, 612, 1202, 698, 1590, 840,
+ 1902, 643, 650, 938, 996, 1553, 959, 1788, 1763, 843, 1493, 1088, 1570, 806, 1262, 833, 1154, 969, 1124, 973,
+ 1338, 310, 1573, 711, 1060, 986, 1019, 737, 263, 889, 1225, 772, 1364, 1149, 441, 938, 1064, 872, 273, 901,
+ 1763, 1498, 582, 1323, 1312, 740, 617, 914, 693, 1537, 1153, 326, 1017, 1396, 745, 327, 585, 1358, 1132, 947,
+ 768, 1100, 532, 893, 1313, 1001, 874, 1173, 1048, 563, 92, 809, 1128, 1314, 1304, 572, 1774, 1266, 1118, 977,
+ 958, 1088, 1405, 1203, 678, 1483, 1682, 1250, 376, 1734, 693, 529, 575, 1060, 954, 1021, 1095, 1293, 910, 426,
+ 1161, 1459, 796, 1078, 314, 1030, 647, 983, 1378, 112, 699, 1135, 753, 1399, 1087, 215, 947, 1561, 1024, 892,
+ 714, 663, 598, 1347, 164, 1486, 1003, 1076, 1006, 906, 1383, 823, 537, 1051, 1459, 1324, 1064, 754, 895, 669,
+ 1349, 661, 715, 1326, 1100, 548, 1224, 382, 743, 637, 646, 1115, 635, 1257, 181, 974, 1383, 808, 1337, 907,
+ 222, 900, 1267, 1341, 1342, 1572, 1312, 396, 716, 743, 1274, 1573, 1217, 1441, 777, 1886, 928, 1064, 682, 1389,
+ 137, 1581, 870, 182, 979, 1741, 1597, 324, 1688, 1388, 1350, 1605, 1215, 1442, 447, 816, 397, 620, 1695, 77,
+ 1003, 696, 1102, 860, 796, 1090, 1079, 1613, 1243, 602, 683, 1348, 722, 1480, 175, 191, 1944, 484, 735, 778,
+ 877, 1252, 1250, 1318, 698, 1214, 991, 1443, 1284, 1230, 1526, 1270, 1356, 1533, 427, 788, 1681, 826, 1242, 1340,
+ 812, 1094, 833, 1043, 479, 1481, 1401, 1031, 1147, 1531, 597, 820, 1338, 1314, 649, 1578, 1034, 1317, 922, 1787,
+ 970, 501, 252, 705, 707, 695, 1184, 1098, 1235, 433, 642, 998, 1336, 1421, 1641, 695, 1137, 1150, 1468, 813,
+ 1161, 1654, 206, 1166, 782, 1093, 1641, 1111, 1182, 1696, 1488, 1289, 915, 1674, 309, 1117, 790, 912, 833, 890,
+ 1081, 727, 239, 1188, 1132, 1566, 541, 1211, 1041, 1312, 1573, 820, 581, 879, 998, 398, 1491, 946, 396, 161,
+ 111, 1044, 939, 1266, 1691, 749, 1084, 1946, 946, 1511, 1512, 1005, 1092, 1537, 923, 1251, 1304, 1283, 1408, 949,
+ 522, 1405, 909, 952, 570, 1521, 1722, 1085, 1051, 792, 1229, 1305, 730, 1212, 789, 424, 1100, 566, 1376, 535,
+ 426, 187, 1679, 904, 880, 1174, 341, 833, 1429, 1254, 594, 964, 1750, 1332, 864, 1662, 916, 731, 835, 425,
+ 598, 328, 1198, 773, 1326, 1130, 595, 857, 781, 1422, 1346, 812, 1189, 1299, 261, 1054, 786, 1407, 1227, 952,
+ 730, 755, 430, 1767, 1117, 1804, 739, 411, 1581, 522, 1391, 371, 552, 763, 1179, 1267, 480, 1212, 1227, 562,
+ 1332, 163, 987, 496, 1216, 1654, 1293, 1800, 1373, 942, 1247, 572, 750, 818, 1263, 590, 82, 1198, 954, 592,
+ 1756, 1314, 1451, 262, 864, 43, 1455, 1278, 1495, 1269, 1637, 436, 923, 1776, 1071, 780, 1298, 796, 1082, 759,
+ 415, 1390, 1323, 665, 1541, 886, 971, 1121, 1550, 898, 756, 997, 1414, 972, 971, 954, 752, 1564, 798, 903,
+ 1335, 925, 1132, 783, 1412, 509, 620, 1531, 1348, 788, 834, 685, 384, 746, 1469, 785, 1332, 990, 983, 786,
+ 1738, 1152, 1428, 744, 359, 1333, 1198, 1451, 943, 1412, 1051, 1168, 1040, 524, 1149, 1327, 962, 1448, 858, 983
+};
+
diff --git a/sw/app/vvadd/dataset1.h b/sw/app/vvadd/dataset1.h
new file mode 100644
index 00000000..a34cb960
--- /dev/null
+++ b/sw/app/vvadd/dataset1.h
@@ -0,0 +1,62 @@
+// See LICENSE for license details.
+
+
+#define DATA_SIZE 300
+
+int input1_data[DATA_SIZE] =
+{
+ 41, 833, 564, 187, 749, 350, 132, 949, 584, 805, 621, 6, 931, 890, 392, 694, 961, 110, 116, 296,
+ 426, 314, 659, 774, 319, 678, 875, 376, 474, 938, 539, 569, 203, 280, 759, 606, 511, 657, 195, 81,
+ 267, 229, 337, 944, 902, 241, 913, 826, 933, 985, 195, 960, 566, 350, 649, 657, 181, 111, 859, 65,
+ 288, 349, 141, 905, 886, 264, 576, 979, 761, 241, 478, 499, 403, 222, 444, 721, 676, 317, 224, 937,
+ 288, 119, 615, 606, 389, 351, 455, 278, 367, 358, 584, 62, 985, 403, 346, 517, 559, 908, 775, 255,
+ 778, 598, 143, 33, 125, 941, 933, 799, 553, 431, 648, 952, 287, 19, 49, 86, 95, 441, 587, 614,
+ 382, 280, 808, 971, 819, 344, 450, 512, 965, 347, 808, 882, 537, 946, 701, 356, 567, 891, 22, 568,
+ 665, 423, 434, 158, 2, 84, 247, 49, 435, 792, 869, 486, 414, 369, 548, 518, 888, 682, 284, 264,
+ 499, 290, 897, 215, 731, 688, 251, 786, 555, 302, 528, 544, 322, 947, 287, 824, 304, 788, 733, 959,
+ 366, 722, 294, 975, 653, 748, 91, 378, 105, 102, 381, 651, 825, 840, 356, 148, 54, 140, 955, 343,
+ 533, 757, 521, 837, 592, 13, 173, 63, 121, 133, 758, 372, 951, 39, 129, 110, 847, 437, 255, 269,
+ 409, 628, 399, 549, 753, 564, 171, 19, 727, 501, 777, 43, 753, 81, 202, 853, 153, 760, 357, 943,
+ 922, 328, 496, 442, 516, 641, 276, 786, 113, 842, 907, 275, 237, 32, 784, 565, 357, 803, 819, 751,
+ 280, 85, 458, 454, 710, 459, 41, 253, 377, 508, 700, 860, 480, 741, 499, 709, 49, 371, 873, 945,
+ 992, 526, 721, 435, 232, 497, 697, 30, 348, 250, 350, 250, 573, 784, 749, 502, 823, 826, 170, 160
+};
+
+int input2_data[DATA_SIZE] =
+{
+ 454, 335, 1, 989, 365, 572, 64, 153, 216, 140, 210, 572, 339, 593, 898, 228, 12, 883, 750, 646,
+ 500, 436, 701, 812, 981, 150, 696, 564, 272, 258, 647, 509, 88, 703, 669, 375, 551, 936, 592, 569,
+ 952, 800, 584, 643, 368, 489, 328, 313, 592, 388, 543, 649, 979, 997, 814, 79, 208, 998, 629, 847,
+ 704, 997, 253, 715, 430, 415, 538, 700, 4, 494, 100, 864, 693, 416, 296, 285, 620, 78, 351, 540,
+ 646, 169, 527, 289, 796, 801, 720, 758, 745, 92, 989, 271, 853, 788, 531, 222, 461, 241, 358, 332,
+ 684, 740, 446, 311, 743, 557, 479, 557, 925, 796, 357, 891, 666, 514, 557, 870, 853, 440, 61, 678,
+ 396, 9, 17, 170, 291, 380, 536, 185, 917, 539, 983, 887, 54, 612, 951, 479, 151, 7, 641, 335,
+ 730, 95, 728, 280, 395, 688, 911, 476, 815, 729, 265, 127, 236, 214, 180, 6, 503, 596, 173, 643,
+ 346, 599, 68, 849, 658, 619, 121, 131, 828, 667, 433, 487, 753, 125, 626, 14, 10, 403, 106, 703,
+ 818, 964, 406, 874, 856, 86, 60, 660, 667, 153, 121, 98, 412, 236, 12, 423, 965, 216, 621, 361,
+ 921, 715, 647, 299, 886, 682, 36, 493, 551, 537, 969, 643, 434, 415, 303, 438, 860, 203, 478, 988,
+ 675, 719, 990, 338, 450, 633, 155, 646, 452, 427, 509, 988, 426, 12, 483, 142, 339, 390, 50, 171,
+ 601, 105, 968, 121, 879, 81, 870, 600, 603, 871, 887, 610, 404, 234, 745, 526, 275, 441, 226, 752,
+ 943, 726, 709, 201, 54, 758, 53, 397, 41, 141, 416, 747, 219, 478, 770, 180, 482, 691, 725, 173,
+ 186, 914, 1, 963, 247, 464, 362, 521, 233, 120, 40, 779, 195, 161, 743, 439, 355, 403, 141, 633
+};
+
+int verify_data[DATA_SIZE] =
+{
+ 495, 1168, 565, 1176, 1114, 922, 196, 1102, 800, 945, 831, 578, 1270, 1483, 1290, 922, 973, 993, 866, 942,
+ 926, 750, 1360, 1586, 1300, 828, 1571, 940, 746, 1196, 1186, 1078, 291, 983, 1428, 981, 1062, 1593, 787, 650,
+ 1219, 1029, 921, 1587, 1270, 730, 1241, 1139, 1525, 1373, 738, 1609, 1545, 1347, 1463, 736, 389, 1109, 1488, 912,
+ 992, 1346, 394, 1620, 1316, 679, 1114, 1679, 765, 735, 578, 1363, 1096, 638, 740, 1006, 1296, 395, 575, 1477,
+ 934, 288, 1142, 895, 1185, 1152, 1175, 1036, 1112, 450, 1573, 333, 1838, 1191, 877, 739, 1020, 1149, 1133, 587,
+ 1462, 1338, 589, 344, 868, 1498, 1412, 1356, 1478, 1227, 1005, 1843, 953, 533, 606, 956, 948, 881, 648, 1292,
+ 778, 289, 825, 1141, 1110, 724, 986, 697, 1882, 886, 1791, 1769, 591, 1558, 1652, 835, 718, 898, 663, 903,
+ 1395, 518, 1162, 438, 397, 772, 1158, 525, 1250, 1521, 1134, 613, 650, 583, 728, 524, 1391, 1278, 457, 907,
+ 845, 889, 965, 1064, 1389, 1307, 372, 917, 1383, 969, 961, 1031, 1075, 1072, 913, 838, 314, 1191, 839, 1662,
+ 1184, 1686, 700, 1849, 1509, 834, 151, 1038, 772, 255, 502, 749, 1237, 1076, 368, 571, 1019, 356, 1576, 704,
+ 1454, 1472, 1168, 1136, 1478, 695, 209, 556, 672, 670, 1727, 1015, 1385, 454, 432, 548, 1707, 640, 733, 1257,
+ 1084, 1347, 1389, 887, 1203, 1197, 326, 665, 1179, 928, 1286, 1031, 1179, 93, 685, 995, 492, 1150, 407, 1114,
+ 1523, 433, 1464, 563, 1395, 722, 1146, 1386, 716, 1713, 1794, 885, 641, 266, 1529, 1091, 632, 1244, 1045, 1503,
+ 1223, 811, 1167, 655, 764, 1217, 94, 650, 418, 649, 1116, 1607, 699, 1219, 1269, 889, 531, 1062, 1598, 1118,
+ 1178, 1440, 722, 1398, 479, 961, 1059, 551, 581, 370, 390, 1029, 768, 945, 1492, 941, 1178, 1229, 311, 793
+};
+
diff --git a/sw/app/vvadd/vvadd_gendata.pl b/sw/app/vvadd/vvadd_gendata.pl
new file mode 100755
index 00000000..f23cdf4e
--- /dev/null
+++ b/sw/app/vvadd/vvadd_gendata.pl
@@ -0,0 +1,139 @@
+#!/usr/bin/perl -w
+#==========================================================================
+# vvadd_gendata.pl
+#
+# Author : Christopher Batten (cbatten@mit.edu)
+# Date : April 29, 2005
+#
+(our $usageMsg = <<'ENDMSG') =~ s/^\#//gm;
+#
+# Simple script which creates an input data set and the reference data
+# for the vvadd benchmark.
+#
+ENDMSG
+
+use strict "vars";
+use warnings;
+no warnings("once");
+use Getopt::Long;
+
+#--------------------------------------------------------------------------
+# Command line processing
+#--------------------------------------------------------------------------
+
+our %opts;
+
+sub usage()
+{
+
+ print "\n";
+ print " Usage: vvadd_gendata.pl [options] \n";
+ print "\n";
+ print " Options:\n";
+ print " --help print this message\n";
+ print " --size size of input data [1000]\n";
+ print " --seed random seed [1]\n";
+ print "$usageMsg";
+
+ exit();
+}
+
+sub processCommandLine()
+{
+
+ $opts{"help"} = 0;
+ $opts{"size"} = 1000;
+ $opts{"seed"} = 1;
+ Getopt::Long::GetOptions( \%opts, 'help|?', 'size:i', 'seed:i' ) or usage();
+ $opts{"help"} and usage();
+
+}
+
+#--------------------------------------------------------------------------
+# Helper Functions
+#--------------------------------------------------------------------------
+
+sub printArray
+{
+ my $arrayName = $_[0];
+ my $arrayRef = $_[1];
+
+ my $numCols = 20;
+ my $arrayLen = scalar(@{$arrayRef});
+
+ print "int ".$arrayName."[DATA_SIZE] = \n";
+ print "{\n";
+
+ if ( $arrayLen <= $numCols ) {
+ print " ";
+ for ( my $i = 0; $i < $arrayLen; $i++ ) {
+ print sprintf("%3d",$arrayRef->[$i]);
+ if ( $i != $arrayLen-1 ) {
+ print ", ";
+ }
+ }
+ print "\n";
+ }
+
+ else {
+ my $numRows = int($arrayLen/$numCols);
+ for ( my $j = 0; $j < $numRows; $j++ ) {
+ print " ";
+ for ( my $i = 0; $i < $numCols; $i++ ) {
+ my $index = $j*$numCols + $i;
+ print sprintf("%3d",$arrayRef->[$index]);
+ if ( $index != $arrayLen-1 ) {
+ print ", ";
+ }
+ }
+ print "\n";
+ }
+
+ if ( $arrayLen > ($numRows*$numCols) ) {
+ print " ";
+ for ( my $i = 0; $i < ($arrayLen-($numRows*$numCols)); $i++ ) {
+ my $index = $numCols*$numRows + $i;
+ print sprintf("%3d",$arrayRef->[$index]);
+ if ( $index != $arrayLen-1 ) {
+ print ", ";
+ }
+ }
+ print "\n";
+ }
+
+ }
+
+ print "};\n\n";
+}
+
+#--------------------------------------------------------------------------
+# Main
+#--------------------------------------------------------------------------
+
+sub main()
+{
+
+ processCommandLine();
+ srand($opts{"seed"});
+
+ my @values1;
+ my @values2;
+ my @sum;
+ for ( my $i = 0; $i < $opts{"size"}; $i++ ) {
+ my $value1 = int(rand(999));
+ my $value2 = int(rand(999));
+ push( @values1, $value1 );
+ push( @values2, $value2 );
+ push( @sum, $value1 + $value2 );
+ }
+
+
+ print "\n\#define DATA_SIZE ".$opts{"size"}." \n\n";
+ printArray( "input1_data", \@values1 );
+ printArray( "input2_data", \@values2 );
+ printArray( "verify_data", \@sum );
+
+}
+
+main();
+
diff --git a/sw/app/vvadd/vvadd_main.c b/sw/app/vvadd/vvadd_main.c
new file mode 100644
index 00000000..adb5637f
--- /dev/null
+++ b/sw/app/vvadd/vvadd_main.c
@@ -0,0 +1,70 @@
+// See LICENSE for license details.
+
+//**************************************************************************
+// Vector-vector add benchmark
+//--------------------------------------------------------------------------
+//
+// This benchmark uses adds to vectors and writes the results to a
+// third vector. The input data (and reference data) should be
+// generated using the vvadd_gendata.pl perl script and dumped
+// to a file named dataset1.h.
+
+#include "util.h"
+
+
+#define NUM_COUNTERS 2
+static uintptr_t counters[NUM_COUNTERS];
+static char* counter_names[NUM_COUNTERS];
+
+
+void setStats(int enable)
+{
+ int i = 0;
+#define READ_CTR(name) do { \
+ while (i >= NUM_COUNTERS) ; \
+ uintptr_t csr = read_csr(name); \
+ if (!enable) { csr -= counters[i]; counter_names[i] = #name; } \
+ counters[i++] = csr; \
+ } while (0)
+
+ READ_CTR(mcycle);
+ READ_CTR(minstret);
+
+#undef READ_CTR
+}
+
+//--------------------------------------------------------------------------
+// Input/Reference Data
+
+#include "dataset1.h"
+
+//--------------------------------------------------------------------------
+// vvadd function
+
+void vvadd( int n, int a[], int b[], int c[] )
+{
+ int i;
+ for ( i = 0; i < n; i++ )
+ c[i] = a[i] + b[i];
+}
+
+//--------------------------------------------------------------------------
+// Main
+
+int main( int argc, char* argv[] )
+{
+ int results_data[DATA_SIZE];
+
+#if PREALLOCATE
+ // If needed we preallocate everything in the caches
+ vvadd( DATA_SIZE, input1_data, input2_data, results_data );
+#endif
+
+ // Do the vvadd
+ setStats(1);
+ vvadd( DATA_SIZE, input1_data, input2_data, results_data );
+ setStats(0);
+
+ // Check the results
+ return verify( DATA_SIZE, results_data, verify_data );
+}
diff --git a/sw/bsp/config/fpga_platform_config.h b/sw/bsp/config/fpga_platform_config.h
new file mode 100644
index 00000000..6c11bb82
--- /dev/null
+++ b/sw/bsp/config/fpga_platform_config.h
@@ -0,0 +1,48 @@
+// Copyright (c) 2020 Thales.
+//
+// Copyright and related rights are licensed under the Apache
+// License, Version 2.0 (the "License"); you may not use this file except in
+// compliance with the License. You may obtain a copy of the License at
+// https://www.apache.org/licenses/LICENSE-2.0. Unless required by applicable law
+// or agreed to in writing, software, hardware and materials distributed under
+// this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR
+// CONDITIONS OF ANY KIND, either express or implied. See the License for the
+// specific language governing permissions and limitations under the License.
+//
+// Author: Sebastien Jacq - sjthales on github.com
+//
+// Additional contributions by:
+//
+//
+// file Name: CVA6 FPGA configurtion
+// Project Name: CVA6 softcore
+// Language: C header
+//
+// Description: File which defines the FPGA platform, i.e base address for each
+// peripheral and others information relating to FPAG platform.
+//
+// =========================================================================== #
+// Revisions :
+// Date Version Author Description
+// 2020-10-06 0.1 S.Jacq Created
+// =========================================================================== #
+
+#ifndef __FPGA_PLATFORM_CONFIG_H
+#define __FPGA_PLATFORM_CONFIG_H
+
+
+/***************************************************************************//**
+ * Platform frequency
+ */
+
+#define FPGA_UART_0_FREQUENCY 50000000
+
+
+/***************************************************************************//**
+ * Peripheral base address
+ */
+#define FPGA_UART_0_BASE 0x10000000
+
+
+
+#endif /* FPGA_PLATFORM_CONFIG */
diff --git a/sw/bsp/config/link.ld b/sw/bsp/config/link.ld
new file mode 100644
index 00000000..02259558
--- /dev/null
+++ b/sw/bsp/config/link.ld
@@ -0,0 +1,320 @@
+/* Copyright (c) 2020 Thales.
+ Copyright (C) 2014-2020 Free Software Foundation, Inc.
+ Copyright (C) 2019 ETH Zürich and University of Bologna
+ Copyright (C) 2020 OpenHW Group
+ Copying and distribution of this script, with or without modification,
+ are permitted in any medium without royalty provided the copyright
+ notice and this notice are preserved. */
+
+/* This linker script is adapted from the default linker script for upstream
+ RISC-V GCC. It has been modified for use in verification of CORE-V cores.
+*/
+// Additional contributions by:
+// Sebastien Jacq - sjthales on github.com
+//
+// Description: linkerscript for the CV32A6 platform
+//
+// =========================================================================== //
+// Revisions :
+// Date Version Author Description
+// 2020-10-06 0.1 S.Jacq modification of the Test for CV32A6 softcore
+// =========================================================================== //
+
+OUTPUT_FORMAT("elf32-littleriscv", "elf32-littleriscv",
+ "elf32-littleriscv")
+OUTPUT_ARCH(riscv)
+ENTRY(_start)
+
+/* CORE-V */
+MEMORY
+{
+ /* Our testbench is a bit weird in that we initialize the RAM (thus
+ allowing initialized sections to be placed there). Infact we dump all
+ sections to ram. */
+
+ ram (rwxai) : ORIGIN = 0x80000000, LENGTH = 0x40000
+ dbg (rwxai) : ORIGIN = 0x1A110800, LENGTH = 0x1000
+}
+
+SECTIONS
+{
+ /* CORE-V Debugger Code: This section address must be the same as the
+ DM_HaltAddress parameter in the RTL */
+ .debugger (ORIGIN(dbg)):
+ {
+ KEEP(*(.debugger));
+ } >dbg
+ .debugger_exception (0x1A111000):
+ {
+ KEEP(*(.debugger_exception));
+ } >dbg
+ /* Debugger Stack*/
+ .debugger_stack : ALIGN(16)
+ {
+ PROVIDE(__debugger_stack_start = .);
+ . = 0x80;
+ } >dbg
+
+ /* CORE-V: we want a fixed entry point */
+ PROVIDE(__boot_address = 0x80000080);
+
+ /* CORE-V: interrupt vectors */
+ .vectors (ORIGIN(ram)):
+ {
+ PROVIDE(__vector_start = .);
+ KEEP(*(.vectors));
+ } >ram
+
+ /* CORE-V: crt0 init code */
+ .init (__boot_address):
+ {
+ KEEP (*(SORT_NONE(.init)))
+ KEEP (*(.text.start))
+ } >ram
+
+ /* Read-only sections, merged into text segment: */
+ PROVIDE (__executable_start = SEGMENT_START("text-segment", 0x10000)); . = SEGMENT_START("text-segment", 0x10000) + SIZEOF_HEADERS;
+ .interp : { *(.interp) } >ram
+ .note.gnu.build-id : { *(.note.gnu.build-id) } >ram
+ .hash : { *(.hash) } >ram
+ .gnu.hash : { *(.gnu.hash) } >ram
+ .dynsym : { *(.dynsym) } >ram
+ .dynstr : { *(.dynstr) } >ram
+ .gnu.version : { *(.gnu.version) } >ram
+ .gnu.version_d : { *(.gnu.version_d) } >ram
+ .gnu.version_r : { *(.gnu.version_r) } >ram
+ .rela.dyn :
+ {
+ *(.rela.init)
+ *(.rela.text .rela.text.* .rela.gnu.linkonce.t.*)
+ *(.rela.fini)
+ *(.rela.rodata .rela.rodata.* .rela.gnu.linkonce.r.*)
+ *(.rela.data .rela.data.* .rela.gnu.linkonce.d.*)
+ *(.rela.tdata .rela.tdata.* .rela.gnu.linkonce.td.*)
+ *(.rela.tbss .rela.tbss.* .rela.gnu.linkonce.tb.*)
+ *(.rela.ctors)
+ *(.rela.dtors)
+ *(.rela.got)
+ *(.rela.sdata .rela.sdata.* .rela.gnu.linkonce.s.*)
+ *(.rela.sbss .rela.sbss.* .rela.gnu.linkonce.sb.*)
+ *(.rela.sdata2 .rela.sdata2.* .rela.gnu.linkonce.s2.*)
+ *(.rela.sbss2 .rela.sbss2.* .rela.gnu.linkonce.sb2.*)
+ *(.rela.bss .rela.bss.* .rela.gnu.linkonce.b.*)
+ PROVIDE_HIDDEN (__rela_iplt_start = .);
+ *(.rela.iplt)
+ PROVIDE_HIDDEN (__rela_iplt_end = .);
+ } >ram
+ .rela.plt :
+ {
+ *(.rela.plt)
+ } >ram
+
+ .plt : { *(.plt) }
+ .iplt : { *(.iplt) }
+ .text :
+ {
+ *(.text.unlikely .text.*_unlikely .text.unlikely.*)
+ *(.text.exit .text.exit.*)
+ *(.text.startup .text.startup.*)
+ *(.text.hot .text.hot.*)
+ *(SORT(.text.sorted.*))
+ *(.text .stub .text.* .gnu.linkonce.t.*)
+ /* .gnu.warning sections are handled specially by elf.em. */
+ *(.gnu.warning)
+ } >ram
+ .fini :
+ {
+ KEEP (*(SORT_NONE(.fini)))
+ } >ram
+ PROVIDE (__etext = .);
+ PROVIDE (_etext = .);
+ PROVIDE (etext = .);
+ .rodata : { *(.rodata .rodata.* .gnu.linkonce.r.*) } >ram
+ .rodata1 : { *(.rodata1) } >ram
+ .sdata2 :
+ {
+ *(.sdata2 .sdata2.* .gnu.linkonce.s2.*)
+ } >ram
+ .sbss2 : { *(.sbss2 .sbss2.* .gnu.linkonce.sb2.*) } >ram
+ .eh_frame_hdr : { *(.eh_frame_hdr) *(.eh_frame_entry .eh_frame_entry.*) } >ram
+ .eh_frame : ONLY_IF_RO { KEEP (*(.eh_frame)) *(.eh_frame.*) } >ram
+ .gcc_except_table : ONLY_IF_RO { *(.gcc_except_table .gcc_except_table.*) } >ram
+ .gnu_extab : ONLY_IF_RO { *(.gnu_extab*) } >ram
+ /* These sections are generated by the Sun/Oracle C++ compiler. */
+ .exception_ranges : ONLY_IF_RO { *(.exception_ranges*) }
+ /* Adjust the address for the data segment. We want to adjust up to
+ the same address within the page on the next page up. */
+ . = DATA_SEGMENT_ALIGN (CONSTANT (MAXPAGESIZE), CONSTANT (COMMONPAGESIZE));
+ /* Exception handling */
+ .eh_frame : ONLY_IF_RW { KEEP (*(.eh_frame)) *(.eh_frame.*) } >ram
+ .gnu_extab : ONLY_IF_RW { *(.gnu_extab) } >ram
+ .gcc_except_table : ONLY_IF_RW { *(.gcc_except_table .gcc_except_table.*) } >ram
+ .exception_ranges : ONLY_IF_RW { *(.exception_ranges*) } >ram
+ /* Thread Local Storage sections */
+ .tdata :
+ {
+ PROVIDE_HIDDEN (__tdata_start = .);
+ *(.tdata .tdata.* .gnu.linkonce.td.*)
+ } >ram
+ .tbss : { *(.tbss .tbss.* .gnu.linkonce.tb.*) *(.tcommon) } >ram
+ .preinit_array :
+ {
+ PROVIDE_HIDDEN (__preinit_array_start = .);
+ KEEP (*(.preinit_array))
+ PROVIDE_HIDDEN (__preinit_array_end = .);
+ } >ram
+ .init_array :
+ {
+ PROVIDE_HIDDEN (__init_array_start = .);
+ KEEP (*(SORT_BY_INIT_PRIORITY(.init_array.*) SORT_BY_INIT_PRIORITY(.ctors.*)))
+ KEEP (*(.init_array EXCLUDE_FILE (*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o ) .ctors))
+ PROVIDE_HIDDEN (__init_array_end = .);
+ } >ram
+ .fini_array :
+ {
+ PROVIDE_HIDDEN (__fini_array_start = .);
+ KEEP (*(SORT_BY_INIT_PRIORITY(.fini_array.*) SORT_BY_INIT_PRIORITY(.dtors.*)))
+ KEEP (*(.fini_array EXCLUDE_FILE (*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o ) .dtors))
+ PROVIDE_HIDDEN (__fini_array_end = .);
+ } >ram
+ .ctors :
+ {
+ /* gcc uses crtbegin.o to find the start of
+ the constructors, so we make sure it is
+ first. Because this is a wildcard, it
+ doesn't matter if the user does not
+ actually link against crtbegin.o; the
+ linker won't look for a file to match a
+ wildcard. The wildcard also means that it
+ doesn't matter which directory crtbegin.o
+ is in. */
+ KEEP (*crtbegin.o(.ctors))
+ KEEP (*crtbegin?.o(.ctors))
+ /* We don't want to include the .ctor section from
+ the crtend.o file until after the sorted ctors.
+ The .ctor section from the crtend file contains the
+ end of ctors marker and it must be last */
+ KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .ctors))
+ KEEP (*(SORT(.ctors.*)))
+ KEEP (*(.ctors))
+ } >ram
+ .dtors :
+ {
+ KEEP (*crtbegin.o(.dtors))
+ KEEP (*crtbegin?.o(.dtors))
+ KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .dtors))
+ KEEP (*(SORT(.dtors.*)))
+ KEEP (*(.dtors))
+ } >ram
+ .jcr : { KEEP (*(.jcr)) }
+ .data.rel.ro : { *(.data.rel.ro.local* .gnu.linkonce.d.rel.ro.local.*) *(.data.rel.ro .data.rel.ro.* .gnu.linkonce.d.rel.ro.*) }
+ .dynamic : { *(.dynamic) }
+ . = DATA_SEGMENT_RELRO_END (0, .);
+ .data :
+ {
+ __DATA_BEGIN__ = .;
+ *(.data .data.* .gnu.linkonce.d.*)
+ SORT(CONSTRUCTORS)
+ } >ram
+ .data1 : { *(.data1) } >ram
+ .got : { *(.got.plt) *(.igot.plt) *(.got) *(.igot) }
+ /* We want the small data sections together, so single-instruction offsets
+ can access them all, and initialized data all before uninitialized, so
+ we can shorten the on-disk segment size. */
+ .sdata :
+ {
+ __SDATA_BEGIN__ = .;
+ *(.srodata.cst16) *(.srodata.cst8) *(.srodata.cst4) *(.srodata.cst2) *(.srodata .srodata.*)
+ *(.sdata .sdata.* .gnu.linkonce.s.*)
+ } >ram
+ _edata = .; PROVIDE (edata = .);
+ . = .;
+ __bss_start = .;
+ .sbss :
+ {
+ *(.dynsbss)
+ *(.sbss .sbss.* .gnu.linkonce.sb.*)
+ *(.scommon)
+ } >ram
+ .bss :
+ {
+ *(.dynbss)
+ *(.bss .bss.* .gnu.linkonce.b.*)
+ *(COMMON)
+ /* Align here to ensure that the .bss section occupies space up to
+ _end. Align after .bss to ensure correct alignment even if the
+ .bss section disappears because there are no input sections.
+ FIXME: Why do we need it? When there is no .bss section, we do not
+ pad the .data section. */
+ . = ALIGN(. != 0 ? 32 / 8 : 1);
+ } >ram
+ . = ALIGN(32 / 8);
+ . = SEGMENT_START("ldata-segment", .);
+ . = ALIGN(32 / 8);
+ __bss_end = .;
+ __global_pointer$ = MIN(__SDATA_BEGIN__ + 0x800,
+ MAX(__DATA_BEGIN__ + 0x800, __bss_end - 0x800));
+ _end = .; PROVIDE (end = .);
+ . = DATA_SEGMENT_END (.);
+
+ /* Heap grows upward towards end of ram */
+ .heap : ALIGN(16)
+ {
+ PROVIDE(__heap_start = .);
+ /* If end of ram is not 16-byte aligned, align to previous 16-byte
+ boundary */
+ PROVIDE(__heap_end = ALIGN(ORIGIN(ram) + LENGTH(ram) - __heap_start - 15, 16));
+ . = __heap_end;
+ } >ram
+
+ /* Stack grows downward from end of ram */
+ .stack (__heap_start) : ALIGN(16) /* this is a requirement of the ABI(?) */
+ {
+ PROVIDE(__stack_start = __heap_start);
+ . = __heap_end;
+ PROVIDE(__stack_end = .);
+ } >ram
+
+ /* Stabs debugging sections. */
+ .stab 0 : { *(.stab) }
+ .stabstr 0 : { *(.stabstr) }
+ .stab.excl 0 : { *(.stab.excl) }
+ .stab.exclstr 0 : { *(.stab.exclstr) }
+ .stab.index 0 : { *(.stab.index) }
+ .stab.indexstr 0 : { *(.stab.indexstr) }
+ .comment 0 : { *(.comment) }
+ .gnu.build.attributes : { *(.gnu.build.attributes .gnu.build.attributes.*) }
+ /* DWARF debug sections.
+ Symbols in the DWARF debugging sections are relative to the beginning
+ of the section so we begin them at 0. */
+ /* DWARF 1 */
+ .debug 0 : { *(.debug) }
+ .line 0 : { *(.line) }
+ /* GNU DWARF 1 extensions */
+ .debug_srcinfo 0 : { *(.debug_srcinfo) }
+ .debug_sfnames 0 : { *(.debug_sfnames) }
+ /* DWARF 1.1 and DWARF 2 */
+ .debug_aranges 0 : { *(.debug_aranges) }
+ .debug_pubnames 0 : { *(.debug_pubnames) }
+ /* DWARF 2 */
+ .debug_info 0 : { *(.debug_info .gnu.linkonce.wi.*) }
+ .debug_abbrev 0 : { *(.debug_abbrev) }
+ .debug_line 0 : { *(.debug_line .debug_line.* .debug_line_end) }
+ .debug_frame 0 : { *(.debug_frame) }
+ .debug_str 0 : { *(.debug_str) }
+ .debug_loc 0 : { *(.debug_loc) }
+ .debug_macinfo 0 : { *(.debug_macinfo) }
+ /* SGI/MIPS DWARF 2 extensions */
+ .debug_weaknames 0 : { *(.debug_weaknames) }
+ .debug_funcnames 0 : { *(.debug_funcnames) }
+ .debug_typenames 0 : { *(.debug_typenames) }
+ .debug_varnames 0 : { *(.debug_varnames) }
+ /* DWARF 3 */
+ .debug_pubtypes 0 : { *(.debug_pubtypes) }
+ .debug_ranges 0 : { *(.debug_ranges) }
+ /* DWARF Extension. */
+ .debug_macro 0 : { *(.debug_macro) }
+ .debug_addr 0 : { *(.debug_addr) }
+ .gnu.attributes 0 : { KEEP (*(.gnu.attributes)) }
+ /DISCARD/ : { *(.note.GNU-stack) *(.gnu_debuglink) *(.gnu.lto_*) }
+}
diff --git a/sw/bsp/hal/crt0.S b/sw/bsp/hal/crt0.S
new file mode 100644
index 00000000..b4ab3ca5
--- /dev/null
+++ b/sw/bsp/hal/crt0.S
@@ -0,0 +1,75 @@
+/* Copyright (c) 2017 SiFive Inc. All rights reserved.
+ * Copyright (c) 2019 ETH Zürich and University of Bologna
+ * This copyrighted material is made available to anyone wishing to use,
+ * modify, copy, or redistribute it subject to the terms and conditions
+ * of the FreeBSD License. This program is distributed in the hope that
+ * it will be useful, but WITHOUT ANY WARRANTY expressed or implied,
+ * including the implied warranties of MERCHANTABILITY or FITNESS FOR
+ * A PARTICULAR PURPOSE. A copy of this license is available at
+ * http://www.opensource.org/licenses.
+ */
+/* Make sure the vector table gets linked into the binary. */
+.global vector_table
+
+/* Entry point for bare metal programs */
+.section .text.start
+.global _start
+.type _start, @function
+
+_start:
+/* initialize global pointer */
+.option push
+.option norelax
+1: auipc gp, %pcrel_hi(__global_pointer$)
+ addi gp, gp, %pcrel_lo(1b)
+.option pop
+
+
+
+
+/* initialize stack pointer */
+ la sp, __stack_end
+
+/* set vector table address */
+ la a0, __vector_start
+ ori a0, a0, 1 /*vector mode = vectored */
+ csrw mtvec, a0
+
+/* clear the bss segment */
+ la a0, _edata
+ la a2, _end
+ sub a2, a2, a0
+ li a1, 0
+ call memset
+
+/* new-style constructors and destructors */
+ la a0, __libc_fini_array
+ call atexit
+ call __libc_init_array
+
+/* call main */
+// lw a0, 0(sp) /* a0 = argc */
+// addi a1, sp, __SIZEOF_POINTER__ /* a1 = argv */
+// li a2, 0 /* a2 = envp = NULL */
+// Initialize these variables to 0. Cannot use argc or argv
+// since the stack is not initialized
+ li a0, 0
+ li a1, 0
+ li a2, 0
+
+ call main
+ tail exit
+
+.size _start, .-_start
+
+.global _init
+.type _init, @function
+.global _fini
+.type _fini, @function
+_init:
+_fini:
+ /* These don't have to do anything since we use init_array/fini_array. Prevent
+ missing symbol error */
+ ret
+.size _init, .-_init
+.size _fini, .-_fini
diff --git a/sw/bsp/hal/encoding.h b/sw/bsp/hal/encoding.h
new file mode 100644
index 00000000..06e4ca97
--- /dev/null
+++ b/sw/bsp/hal/encoding.h
@@ -0,0 +1,251 @@
+
+#ifndef RISCV_CSR_ENCODING_H
+#define RISCV_CSR_ENCODING_H
+
+#define MSTATUS_UIE 0x00000001
+#define MSTATUS_SIE 0x00000002
+#define MSTATUS_HIE 0x00000004
+#define MSTATUS_MIE 0x00000008
+#define MSTATUS_UPIE 0x00000010
+#define MSTATUS_SPIE 0x00000020
+#define MSTATUS_HPIE 0x00000040
+#define MSTATUS_MPIE 0x00000080
+#define MSTATUS_SPP 0x00000100
+#define MSTATUS_HPP 0x00000600
+#define MSTATUS_MPP 0x00001800
+#define MSTATUS_FS 0x00006000
+#define MSTATUS_XS 0x00018000
+#define MSTATUS_MPRV 0x00020000
+#define MSTATUS_SUM 0x00040000
+#define MSTATUS_MXR 0x00080000
+#define MSTATUS_TVM 0x00100000
+#define MSTATUS_TW 0x00200000
+#define MSTATUS_TSR 0x00400000
+#define MSTATUS32_SD 0x80000000
+#define MSTATUS64_SD 0x8000000000000000
+
+#define MCAUSE32_CAUSE 0x7FFFFFFF
+#define MCAUSE64_CAUSE 0x7FFFFFFFFFFFFFFF
+#define MCAUSE32_INT 0x80000000
+#define MCAUSE64_INT 0x8000000000000000
+
+#define SSTATUS_UIE 0x00000001
+#define SSTATUS_SIE 0x00000002
+#define SSTATUS_UPIE 0x00000010
+#define SSTATUS_SPIE 0x00000020
+#define SSTATUS_SPP 0x00000100
+#define SSTATUS_FS 0x00006000
+#define SSTATUS_XS 0x00018000
+#define SSTATUS_SUM 0x00040000
+#define SSTATUS_MXR 0x00080000
+#define SSTATUS32_SD 0x80000000
+#define SSTATUS64_SD 0x8000000000000000
+
+#define DCSR_XDEBUGVER (3U<<30)
+#define DCSR_NDRESET (1<<29)
+#define DCSR_FULLRESET (1<<28)
+#define DCSR_EBREAKM (1<<15)
+#define DCSR_EBREAKH (1<<14)
+#define DCSR_EBREAKS (1<<13)
+#define DCSR_EBREAKU (1<<12)
+#define DCSR_STOPCYCLE (1<<10)
+#define DCSR_STOPTIME (1<<9)
+#define DCSR_CAUSE (7<<6)
+#define DCSR_DEBUGINT (1<<5)
+#define DCSR_HALT (1<<3)
+#define DCSR_STEP (1<<2)
+#define DCSR_PRV (3<<0)
+
+#define DCSR_CAUSE_NONE 0
+#define DCSR_CAUSE_SWBP 1
+#define DCSR_CAUSE_HWBP 2
+#define DCSR_CAUSE_DEBUGINT 3
+#define DCSR_CAUSE_STEP 4
+#define DCSR_CAUSE_HALT 5
+
+#define MCONTROL_TYPE(xlen) (0xfULL<<((xlen)-4))
+#define MCONTROL_DMODE(xlen) (1ULL<<((xlen)-5))
+#define MCONTROL_MASKMAX(xlen) (0x3fULL<<((xlen)-11))
+
+#define MCONTROL_SELECT (1U<<19)
+#define MCONTROL_TIMING (1U<<18)
+#define MCONTROL_ACTION (0x3fU<<12)
+#define MCONTROL_CHAIN (1U<<11)
+#define MCONTROL_MATCH (0xfU<<7)
+#define MCONTROL_M (1U<<6)
+#define MCONTROL_H (1U<<5)
+#define MCONTROL_S (1U<<4)
+#define MCONTROL_U (1U<<3)
+#define MCONTROL_EXECUTE (1U<<2)
+#define MCONTROL_STORE (1U<<1)
+#define MCONTROL_LOAD (1U<<0)
+
+#define MCONTROL_TYPE_NONE 0
+#define MCONTROL_TYPE_MATCH 2
+
+#define MCONTROL_ACTION_DEBUG_EXCEPTION 0
+#define MCONTROL_ACTION_DEBUG_MODE 1
+#define MCONTROL_ACTION_TRACE_START 2
+#define MCONTROL_ACTION_TRACE_STOP 3
+#define MCONTROL_ACTION_TRACE_EMIT 4
+
+#define MCONTROL_MATCH_EQUAL 0
+#define MCONTROL_MATCH_NAPOT 1
+#define MCONTROL_MATCH_GE 2
+#define MCONTROL_MATCH_LT 3
+#define MCONTROL_MATCH_MASK_LOW 4
+#define MCONTROL_MATCH_MASK_HIGH 5
+
+#define MIP_SSIP (1U << IRQ_S_SOFT)
+#define MIP_HSIP (1U << IRQ_H_SOFT)
+#define MIP_MSIP (1U << IRQ_M_SOFT)
+#define MIP_STIP (1U << IRQ_S_TIMER)
+#define MIP_HTIP (1U << IRQ_H_TIMER)
+#define MIP_MTIP (1U << IRQ_M_TIMER)
+#define MIP_SEIP (1U << IRQ_S_EXT)
+#define MIP_HEIP (1U << IRQ_H_EXT)
+#define MIP_MEIP (1U << IRQ_M_EXT)
+
+#define SIP_SSIP MIP_SSIP
+#define SIP_STIP MIP_STIP
+
+#define PRV_U 0
+#define PRV_S 1
+#define PRV_H 2
+#define PRV_M 3
+
+#define SPTBR32_MODE 0x80000000
+#define SPTBR32_ASID 0x7FC00000
+#define SPTBR32_PPN 0x003FFFFF
+#define SPTBR64_MODE 0xF000000000000000
+#define SPTBR64_ASID 0x0FFFF00000000000
+#define SPTBR64_PPN 0x00000FFFFFFFFFFF
+
+#define SPTBR_MODE_OFF 0
+#define SPTBR_MODE_SV32 1
+#define SPTBR_MODE_SV39 8
+#define SPTBR_MODE_SV48 9
+#define SPTBR_MODE_SV57 10
+#define SPTBR_MODE_SV64 11
+
+#define PMP_R 0x01
+#define PMP_W 0x02
+#define PMP_X 0x04
+#define PMP_A 0x18
+#define PMP_L 0x80
+#define PMP_SHIFT 2
+
+#define PMP_TOR 0x08
+#define PMP_NA4 0x10
+#define PMP_NAPOT 0x18
+
+#define IRQ_S_SOFT 1
+#define IRQ_H_SOFT 2
+#define IRQ_M_SOFT 3
+#define IRQ_S_TIMER 5
+#define IRQ_H_TIMER 6
+#define IRQ_M_TIMER 7
+#define IRQ_S_EXT 9
+#define IRQ_H_EXT 10
+#define IRQ_M_EXT 11
+#define IRQ_COP 12
+#define IRQ_HOST 13
+
+#define DEFAULT_RSTVEC 0x00001000
+#define CLINT_BASE 0x02000000
+#define CLINT_SIZE 0x000c0000
+#define EXT_IO_BASE 0x40000000
+#define DRAM_BASE 0x80000000
+
+// page table entry (PTE) fields
+#define PTE_V 0x001 // Valid
+#define PTE_R 0x002 // Read
+#define PTE_W 0x004 // Write
+#define PTE_X 0x008 // Execute
+#define PTE_U 0x010 // User
+#define PTE_G 0x020 // Global
+#define PTE_A 0x040 // Accessed
+#define PTE_D 0x080 // Dirty
+#define PTE_SOFT 0x300 // Reserved for Software
+
+#define PTE_PPN_SHIFT 10
+
+#define PTE_TABLE(PTE) (((PTE) & (PTE_V | PTE_R | PTE_W | PTE_X)) == PTE_V)
+
+#ifdef __riscv
+
+#if __riscv_xlen == 64
+# define MSTATUS_SD MSTATUS64_SD
+# define SSTATUS_SD SSTATUS64_SD
+# define RISCV_PGLEVEL_BITS 9
+# define SPTBR_MODE SPTBR64_MODE
+# define MCAUSE_INT MCAUSE64_INT //ML added- should we be using later encoding.h?
+# define MCAUSE_CAUSE MCAUSE64_CAUSE //ML added- should we be using later encoding.h?
+#else
+# define MSTATUS_SD MSTATUS32_SD
+# define SSTATUS_SD SSTATUS32_SD
+# define RISCV_PGLEVEL_BITS 10
+# define SPTBR_MODE SPTBR32_MODE
+# define MCAUSE_INT MCAUSE32_INT //ML added- should we be using later encoding.h?
+# define MCAUSE_CAUSE MCAUSE32_CAUSE //ML added- should we be using later encoding.h?
+#endif
+#define RISCV_PGSHIFT 12
+#define RISCV_PGSIZE (1 << RISCV_PGSHIFT)
+
+#ifndef __ASSEMBLER__
+
+#ifdef __GNUC__
+
+#define read_reg(reg) ({ unsigned long __tmp; \
+ asm volatile ("mv %0, " #reg : "=r"(__tmp)); \
+ __tmp; })
+
+#define read_csr(reg) ({ unsigned long __tmp; \
+ asm volatile ("csrr %0, " #reg : "=r"(__tmp)); \
+ __tmp; })
+
+#define write_csr(reg, val) ({ \
+ asm volatile ("csrw " #reg ", %0" :: "rK"(val)); })
+
+#define swap_csr(reg, val) ({ unsigned long __tmp; \
+ asm volatile ("csrrw %0, " #reg ", %1" : "=r"(__tmp) : "rK"(val)); \
+ __tmp; })
+
+#define set_csr(reg, bit) ({ unsigned long __tmp; \
+ asm volatile ("csrrs %0, " #reg ", %1" : "=r"(__tmp) : "rK"(bit)); \
+ __tmp; })
+
+#define clear_csr(reg, bit) ({ unsigned long __tmp; \
+ asm volatile ("csrrc %0, " #reg ", %1" : "=r"(__tmp) : "rK"(bit)); \
+ __tmp; })
+
+#if 0
+#define csr_write(csr, val) \
+({ \
+ unsigned long __v = (unsigned long)(val); \
+ asm volatile ("csrw " __ASM_STR(csr) ", %0" \
+ : : "rK" (__v) \
+ : "memory"); \
+})
+
+#define csr_write(csr, val) \
+({ \
+ unsigned long __v = (unsigned long)(val); \
+ __asm__ __volatile__ ("csrw " __ASM_STR(csr) ", %0" \
+ : : "rK" (__v) \
+ : "memory"); \
+})
+#endif
+
+#define rdtime() read_csr(time)
+#define rdcycle() read_csr(cycle)
+#define rdinstret() read_csr(instret)
+
+#endif //__GNUC__
+
+#endif //__ASSEMBLER__
+
+#endif //__riscv
+
+#endif // RISCV_CSR_ENCODING_H
+
diff --git a/sw/bsp/hal/hal_assert.h b/sw/bsp/hal/hal_assert.h
new file mode 100644
index 00000000..a7287283
--- /dev/null
+++ b/sw/bsp/hal/hal_assert.h
@@ -0,0 +1,19 @@
+
+#ifndef HAL_ASSERT_HEADER
+#define HAL_ASSERT_HEADER
+
+
+/***************************************************************************//**
+ * ASSERT() implementation.
+ ******************************************************************************/
+/* Disable assertions if we do not recognize the compiler. */
+
+#define ASSERT(CHECK)
+
+
+#define HAL_ASSERT(CHECK)
+
+
+
+
+#endif /* HAL_ASSERT_HEADER */
diff --git a/sw/bsp/hal/handlers.S b/sw/bsp/hal/handlers.S
new file mode 100644
index 00000000..ebd676f7
--- /dev/null
+++ b/sw/bsp/hal/handlers.S
@@ -0,0 +1,130 @@
+/*
+* Copyright 2019 ETH Zürich and University of Bologna
+*
+* Licensed under the Apache License, Version 2.0 (the "License");
+* you may not use this file except in compliance with the License.
+* You may obtain a copy of the License at
+*
+* http://www.apache.org/licenses/LICENSE-2.0
+*
+* Unless required by applicable law or agreed to in writing, software
+* distributed under the License is distributed on an "AS IS" BASIS,
+* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+* See the License for the specific language governing permissions and
+* limitations under the License.
+*/
+
+/* Exception codes */
+#define EXCEPTION_ILLEGAL_INSN 2
+#define EXCEPTION_BREAKPOINT 3
+#define EXCEPTION_ECALL_M 11
+
+.section .text.handlers
+.global __no_irq_handler
+.global sw_irq_handler
+.global verification_irq_handler
+
+/* exception handling */
+__no_irq_handler:
+ la a0, no_exception_handler_msg
+ jal ra, puts
+ j __no_irq_handler
+
+sw_irq_handler:
+ /* While we are still using puts in handlers, save all caller saved
+ regs. Eventually, some of these saves could be deferred. */
+ addi sp,sp,-64
+ sw ra, 0(sp)
+ sw a0, 4(sp)
+ sw a1, 8(sp)
+ sw a2, 12(sp)
+ sw a3, 16(sp)
+ sw a4, 20(sp)
+ sw a5, 24(sp)
+ sw a6, 28(sp)
+ sw a7, 32(sp)
+ sw t0, 36(sp)
+ sw t1, 40(sp)
+ sw t2, 44(sp)
+ sw t3, 48(sp)
+ sw t4, 52(sp)
+ sw t5, 56(sp)
+ sw t6, 60(sp)
+ csrr t0, mcause
+ li t1, EXCEPTION_ILLEGAL_INSN
+ beq t0, t1, handle_illegal_insn
+ li t1, EXCEPTION_ECALL_M
+ beq t0, t1, handle_ecall
+ li t1, EXCEPTION_BREAKPOINT
+ beq t0, t1, handle_ebreak
+ j handle_unknown
+
+handle_ecall:
+ jal ra, handle_syscall
+ j end_handler_incr_mepc
+
+handle_ebreak:
+ /* TODO support debug handling requirements. */
+ la a0, ebreak_msg
+ jal ra, puts
+ j end_handler_incr_mepc
+
+handle_illegal_insn:
+ la a0, illegal_insn_msg
+ jal ra, puts
+ j end_handler_incr_mepc
+
+handle_unknown:
+ la a0, unknown_msg
+ jal ra, puts
+ /* We don't know what interrupt/exception is being handled, so don't
+ increment mepc. */
+ j end_handler_ret
+
+end_handler_incr_mepc:
+ csrr t0, mepc
+ lb t1, 0(t0)
+ li a0, 0x3
+ and t1, t1, a0
+ /* Increment mepc by 2 or 4 depending on whether the instruction at mepc
+ is compressed or not. */
+ bne t1, a0, end_handler_incr_mepc2
+ addi t0, t0, 2
+end_handler_incr_mepc2:
+ addi t0, t0, 2
+ csrw mepc, t0
+end_handler_ret:
+ lw ra, 0(sp)
+ lw a0, 4(sp)
+ lw a1, 8(sp)
+ lw a2, 12(sp)
+ lw a3, 16(sp)
+ lw a4, 20(sp)
+ lw a5, 24(sp)
+ lw a6, 28(sp)
+ lw a7, 32(sp)
+ lw t0, 36(sp)
+ lw t1, 40(sp)
+ lw t2, 44(sp)
+ lw t3, 48(sp)
+ lw t4, 52(sp)
+ lw t5, 56(sp)
+ lw t6, 60(sp)
+ addi sp,sp,64
+ mret
+/* this interrupt can be generated for verification purposes, random or when the
+ PC is equal to a given value*/
+verification_irq_handler:
+ mret
+
+.section .rodata
+illegal_insn_msg:
+ .string "illegal instruction exception handler entered\n"
+ecall_msg:
+ .string "ecall exception handler entered\n"
+ebreak_msg:
+ .string "ebreak exception handler entered\n"
+unknown_msg:
+ .string "unknown exception handler entered\n"
+no_exception_handler_msg:
+ .string "no exception handler installed\n"
diff --git a/sw/bsp/hal/plic.h b/sw/bsp/hal/plic.h
new file mode 100644
index 00000000..93747f01
--- /dev/null
+++ b/sw/bsp/hal/plic.h
@@ -0,0 +1,365 @@
+/*******************************************************************************
+ * Copyright (c) 2020 Thales.
+ * Copyright 2019-2020 Microchip FPGA Embedded Systems Solutions.
+ *
+ * SPDX-License-Identifier: MIT
+ *
+ * MPFS HAL Embedded Software
+ *
+ */
+/*******************************************************************************
+ *
+ * @author Microchip-FPGA Embedded Systems Solutions
+ *
+ * Definitions and functions associated with PLIC interrupts.
+ */
+// Additional contributions by:
+// Sebastien Jacq - sjthales on github.com
+//
+// Description: Definitions and functions associated with PLIC interrupts
+// for the CVA6 platform
+//
+// =========================================================================== //
+// Revisions :
+// Date Version Author Description
+// 2020-10-06 0.1 S.Jacq modification of the Test for CVA6 softcore
+// =========================================================================== //
+
+#ifndef MSS_PLIC_H
+#define MSS_PLIC_H
+
+#include <stdint.h>
+#include "encoding.h"
+
+#include "hal_assert.h"
+
+/*
+ *Return value from External IRQ handler. This will be used to disable the
+ *Return External interrupt.
+ */
+#define EXT_IRQ_KEEP_ENABLED 0U
+#define EXT_IRQ_DISABLE 1U
+
+
+
+/***************************************************************************//**
+ * PLIC source Interrupt numbers:
+ */
+
+typedef enum
+{
+ NoInterrupt_IRQHandler = 0,
+ UART_0_PLIC_IRQHandler = 1,
+ QSPI_0_PLIC_IRQHandler = 2,
+ ETH_0_PLIC_IRQHandler = 3,
+ External_4_IRQHandler = 4,
+ External_5_IRQHandler = 5,
+ External_6_IRQHandler = 6,
+ External_7_IRQHandler = 7,
+ External_8_IRQHandler = 8,
+ External_9_IRQHandler = 9,
+ External_10_IRQHandler = 10,
+ External_11_IRQHandler = 11,
+ External_12_IRQHandler = 12,
+ External_13_IRQHandler = 13,
+ External_14_IRQHandler = 14,
+ External_15_IRQHandler = 15,
+ External_16_IRQHandler = 16,
+ External_17_IRQHandler = 17,
+ External_18_IRQHandler = 18,
+ External_19_IRQHandler = 19,
+ External_20_IRQHandler = 20,
+ External_21_IRQHandler = 21,
+ External_22_IRQHandler = 22,
+ External_23_IRQHandler = 23,
+ External_24_IRQHandler = 24,
+ External_25_IRQHandler = 25,
+ External_26_IRQHandler = 26,
+ External_27_IRQHandler = 27,
+ External_28_IRQHandler = 28,
+ External_29_IRQHandler = 29,
+ External_30_IRQHandler = 30
+} PLIC_IRQn_Type;
+
+
+#define MAX_PLIC_INT External_30_IRQHandler
+
+typedef struct
+{
+ volatile uint32_t PRIORITY_THRESHOLD;
+ volatile uint32_t CLAIM_COMPLETE;
+ volatile uint32_t reserved[(0x1000/4)-2];
+} IRQ_Target_Type;
+
+typedef struct
+{
+ volatile uint32_t ENABLES[31U];
+} Target_Enables_Type;
+
+
+#define PLIC_SET_UP_REGISTERS 2U
+#define PLIC_NUM_SOURCES 30U
+#define PLIC_NUM_PRIORITIES 7U
+#define NUM_CLAIM_REGS 2U
+
+
+
+typedef struct
+{
+
+ volatile uint32_t RESERVED0;
+ /*-------------------- Source Priority --------------------*/
+ volatile uint32_t SOURCE_PRIORITY[PLIC_NUM_SOURCES];
+ volatile uint32_t RESERVED1[(0x1000/4) - (PLIC_NUM_SOURCES + 1)];
+
+ /*-------------------- Pending array --------------------*/
+ volatile const uint32_t PENDING_ARRAY[PLIC_SET_UP_REGISTERS];
+ volatile uint32_t RESERVED2[(0x1000/4) - PLIC_SET_UP_REGISTERS];
+
+ /*-------------------- Target enables --------------------*/
+ //volatile Target_Enables_Type TARGET_ENABLES[PLIC_SET_UP_REGISTERS];
+ //volatile uint32_t RESERVED3[(0x200000-0x2000) - PLIC_SET_UP_REGISTERS];
+
+ /*-----------------Target Mode Enables--------------------*/
+ volatile uint32_t HART0_MMODE_ENA[PLIC_SET_UP_REGISTERS];
+ volatile uint32_t RESERVED3a[(0x80/4) - PLIC_SET_UP_REGISTERS];
+
+ volatile uint32_t HART0_SMODE_ENA[PLIC_SET_UP_REGISTERS];
+ volatile uint32_t RESERVED3[(0x80/4) - PLIC_SET_UP_REGISTERS];
+
+ volatile uint32_t RESERVED4[(0x200000-0x2000)/4 - PLIC_SET_UP_REGISTERS];
+
+ /*--- Target Priority threshold and claim/complete---------*/
+ IRQ_Target_Type TARGET[NUM_CLAIM_REGS];
+
+
+
+} PLIC_Type;
+
+
+
+
+#define TARGET_OFFSET_HART0_M 0U
+#define TARGET_OFFSET_HART0_S 1U
+
+/***************************************************************************//**
+ * PLIC: Platform Level Interrupt Controller
+ */
+#define PLIC_BASE_ADDR 0x0C000000UL
+
+#define PLIC ((PLIC_Type *)PLIC_BASE_ADDR)
+
+/*-------------------------------------------------------------------------*//**
+ * The function PLIC_init() initializes the PLIC controller and enables the
+ * global external interrupt bit.
+ */
+
+/*-----------------Hart Mode Enables--------------------*/
+
+static inline void PLIC_init(void)
+{
+ uint32_t inc;
+ uint64_t hart_id = read_csr(mhartid);
+
+ /* Disable all interrupts for the current hart. */
+ for(inc = 0UL; inc < PLIC_SET_UP_REGISTERS; inc++)
+ {
+ PLIC->HART0_MMODE_ENA[inc] = 0U;
+ PLIC->HART0_SMODE_ENA[inc] = 0U;
+ }
+
+ PLIC->TARGET[TARGET_OFFSET_HART0_M].PRIORITY_THRESHOLD = 0U;
+ /* Disable supervisor level */
+ PLIC->TARGET[TARGET_OFFSET_HART0_S].PRIORITY_THRESHOLD = 7U;
+
+ /* Enable machine external interrupts. */
+ set_csr(mie, MIP_MEIP);
+}
+
+
+/***************************************************************************//**
+ * The function PLIC_EnableIRQ() enables the external interrupt for the
+ * interrupt number indicated by the parameter IRQn.
+ */
+static inline void PLIC_EnableIRQ(PLIC_IRQn_Type IRQn)
+{
+ uint64_t hart_id = read_csr(mhartid);
+
+ uint32_t current;
+
+ switch(hart_id)
+ {
+ case 0:
+ current = PLIC->HART0_MMODE_ENA[IRQn / 32U];
+ current |= (uint32_t)1 << (IRQn % 32U);
+ PLIC->HART0_MMODE_ENA[IRQn / 32U] = current;
+ break;
+ default:
+ break;
+ }
+}
+
+/***************************************************************************//**
+ * The function PLIC_DisableIRQ() disables the external interrupt for the
+ * interrupt number indicated by the parameter IRQn.
+ * NOTE:
+ * This function can be used to disable the external interrupt from outside
+ * external interrupt handler function.
+ * This function MUST NOT be used from within the External Interrupt
+ * handler.
+ * If you wish to disable the external interrupt while the interrupt handler
+ * for that external interrupt is executing then you must use the return
+ * value EXT_IRQ_DISABLE to return from the extern interrupt handler.
+ */
+static inline void PLIC_DisableIRQ(PLIC_IRQn_Type IRQn)
+{
+ uint32_t current;
+ uint64_t hart_id = read_csr(mhartid);
+
+ switch(hart_id)
+ {
+ case 0:
+ current = PLIC->HART0_MMODE_ENA[IRQn / 32U];
+ current &= ~((uint32_t)1 << (IRQn % 32U));
+ PLIC->HART0_MMODE_ENA[IRQn / 32U] = current;
+ break;
+ default:
+ break;
+ }
+}
+
+/***************************************************************************//**
+ * The function PLIC_SetPriority() sets the priority for the external interrupt
+ * for the interrupt number indicated by the parameter IRQn.
+ */
+static inline void PLIC_SetPriority(PLIC_IRQn_Type IRQn, uint32_t priority)
+{
+ if((IRQn > NoInterrupt_IRQHandler) && (IRQn < PLIC_NUM_SOURCES))
+ {
+ PLIC->SOURCE_PRIORITY[IRQn-1] = priority;
+ }
+}
+
+/***************************************************************************//**
+ * The function PLIC_GetPriority() returns the priority for the external
+ * interrupt for the interrupt number indicated by the parameter IRQn.
+ */
+static inline uint32_t PLIC_GetPriority(PLIC_IRQn_Type IRQn)
+{
+ uint32_t ret_val = 0U;
+
+ if((IRQn > NoInterrupt_IRQHandler) && (IRQn < PLIC_NUM_SOURCES))
+ {
+ ret_val = PLIC->SOURCE_PRIORITY[IRQn-1];
+ }
+
+ return(ret_val);
+}
+
+
+/*static inline uint32_t PLIC_pending(PLIC_IRQn_Type IRQn)
+{
+ return (PLIC->PENDING_ARRAY[IRQn/32U] & (0x01U<<(IRQn%32U)));
+}*/
+
+/***************************************************************************//**
+ * The function PLIC_ClaimIRQ() claims the interrupt from the PLIC controller.
+ */
+static inline uint32_t PLIC_ClaimIRQ(void)
+{
+ unsigned long hart_id = read_csr(mhartid);
+
+ return PLIC->TARGET[hart_id].CLAIM_COMPLETE;
+}
+
+/***************************************************************************//**
+ * The function PLIC_CompleteIRQ() indicates to the PLIC controller the
+ * interrupt is processed and claim is complete.
+ */
+static inline void PLIC_CompleteIRQ(uint32_t source)
+{
+ unsigned long hart_id = read_csr(mhartid);
+
+ PLIC->TARGET[hart_id].CLAIM_COMPLETE = source;
+}
+
+/***************************************************************************//**
+ *
+ * The function PLIC_SetPriority_Threshold() sets the threshold for a particular
+ * hart. The default threshold on reset is 0.
+ * The PFSoC Core Complex supports setting of an interrupt priority threshold
+ * via the threshold register. The threshold is a WARL field, where the PFSoC
+ * Core Complex supports a maximum threshold of 7.
+ * The PFSoC Core Complex will mask all PLIC interrupts of a priority less than
+ * or equal to threshold. For example, a threshold value of zero permits all
+ * interrupts with non-zero priority, whereas a value of 7 masks all
+ * interrupts.
+ */
+static inline void PLIC_SetPriority_Threshold(uint32_t threshold)
+{
+ uint64_t hart_id = read_csr(mhartid);
+ //const unsigned long lookup[5U] = {0U, 1U, 3U, 5U, 7U};
+
+ //ASSERT(threshold <= 7);
+
+ PLIC->TARGET[hart_id].PRIORITY_THRESHOLD = threshold;
+}
+
+/***************************************************************************//**
+ * PLIC_ClearPendingIRQ(void)
+ * This is only called by the startup hart and only once
+ * Clears any pending interrupts as PLIC can be in unknown state on startup
+ */
+static inline void PLIC_ClearPendingIRQ(void)
+{
+ volatile uint32_t int_num = PLIC_ClaimIRQ();
+ volatile int32_t wait_possible_int;
+
+ while ( int_num != NoInterrupt_IRQHandler)
+ {
+ uint8_t disable = EXT_IRQ_KEEP_ENABLED;
+
+ PLIC_CompleteIRQ(int_num);
+ wait_possible_int = 0xFU;
+ while (wait_possible_int)
+ {
+ wait_possible_int--;
+ }
+ int_num = PLIC_ClaimIRQ(); /* obtain interrupt, auto clears */
+ }
+}
+
+/***************************************************************************//**
+ * This function is only called from one hart on startup
+ */
+static inline void PLIC_init_on_reset(void)
+{
+ uint32_t inc;
+
+ /* default all priorities so effectively disabled */
+ for(inc = 0U; inc < PLIC_NUM_SOURCES; ++inc)
+ {
+ /* priority must be greater than threshold to be enabled, so setting to
+ * 7 disables */
+ PLIC->SOURCE_PRIORITY[inc] = 0U;
+ }
+
+ for(inc = 0U; inc < NUM_CLAIM_REGS; ++inc)
+ {
+ PLIC->TARGET[inc].PRIORITY_THRESHOLD = 7U;
+ }
+
+ /* and clear all the enables */
+ for(inc = 0UL; inc < PLIC_SET_UP_REGISTERS; inc++)
+ {
+ PLIC->HART0_MMODE_ENA[inc] = 0U;
+ PLIC->HART0_SMODE_ENA[inc] = 0U;
+ }
+
+ /* clear any pending interrupts- in case already there */
+ PLIC_ClearPendingIRQ();
+}
+
+
+#endif /* MSS_PLIC_H */
+
diff --git a/sw/bsp/hal/riscv_hal_stubs.c b/sw/bsp/hal/riscv_hal_stubs.c
new file mode 100755
index 00000000..4f5ace51
--- /dev/null
+++ b/sw/bsp/hal/riscv_hal_stubs.c
@@ -0,0 +1,197 @@
+/*******************************************************************************
+ * Copyright (c) 2020 Thales.
+ * Copyright 2019-2020 Microchip FPGA Embedded Systems Solutions.
+ *
+ * SPDX-License-Identifier: MIT
+ *
+ * MPFS HAL Embedded Software
+ *
+ */
+
+/*******************************************************************************
+ *
+ * @author Microchip-FPGA Embedded Systems Solutions
+ * @brief MPFS MSS Interrupt Function stubs.
+ *
+ */
+// Additional contributions by:
+// Sebastien Jacq - sjthales on github.com
+//
+// Description: The functions below will only be linked with the application
+// code if the user does not provide an implementation for these
+// functions. These functions are defined with weak linking so that
+// they can be overridden by a function with same prototype in the
+// user's application code.
+//
+// =========================================================================== //
+// Revisions :
+// Date Version Author Description
+// 2020-10-06 0.1 S.Jacq modification of the Test for CVA6 softcore
+// =========================================================================== //
+
+
+
+#include <unistd.h>
+
+
+__attribute__((weak)) uint8_t NoInterrupt_IRQHandler(void)
+{
+ return(0);
+}
+
+__attribute__((weak)) uint8_t UART_0_PLIC_IRQHandler(void)
+{
+ return(0);
+}
+
+__attribute__((weak)) uint8_t QSPI_0_PLIC_IRQHandler(void)
+{
+ return(0);
+}
+
+__attribute__((weak)) uint8_t ETH_0_PLIC_IRQHandler(void)
+{
+ return(0);
+}
+
+__attribute__((weak)) uint8_t External_4_IRQHandler(void)
+{
+ return(0);
+}
+
+__attribute__((weak)) uint8_t External_5_IRQHandler(void)
+{
+ return(0);
+}
+
+__attribute__((weak)) uint8_t External_6_IRQHandler(void)
+{
+ return(0);
+}
+
+__attribute__((weak)) uint8_t External_7_IRQHandler(void)
+{
+ return(0);
+}
+
+__attribute__((weak)) uint8_t External_8_IRQHandler(void)
+{
+ return(0);
+}
+
+__attribute__((weak)) uint8_t External_9_IRQHandler(void)
+{
+ return(0);
+}
+
+__attribute__((weak)) uint8_t External_10_IRQHandler(void)
+{
+ return(0);
+}
+
+__attribute__((weak)) uint8_t External_11_IRQHandler(void)
+{
+ return(0);
+}
+
+__attribute__((weak)) uint8_t External_12_IRQHandler(void)
+{
+ return(0);
+}
+
+__attribute__((weak)) uint8_t External_13_IRQHandler(void)
+{
+ return(0);
+}
+
+__attribute__((weak)) uint8_t External_14_IRQHandler(void)
+{
+ return(0);
+}
+
+__attribute__((weak)) uint8_t External_15_IRQHandler(void)
+{
+ return(0);
+}
+
+__attribute__((weak)) uint8_t External_16_IRQHandler(void)
+{
+ return(0);
+}
+
+__attribute__((weak)) uint8_t External_17_IRQHandler(void)
+{
+ return(0);
+}
+
+__attribute__((weak)) uint8_t External_18_IRQHandler(void)
+{
+ return(0);
+}
+
+__attribute__((weak)) uint8_t External_19_IRQHandler(void)
+{
+ return(0);
+}
+
+__attribute__((weak)) uint8_t External_20_IRQHandler(void)
+{
+ return(0);
+}
+
+__attribute__((weak)) uint8_t External_21_IRQHandler(void)
+{
+ return(0);
+}
+
+__attribute__((weak)) uint8_t External_22_IRQHandler(void)
+{
+ return(0);
+}
+
+__attribute__((weak)) uint8_t External_23_IRQHandler(void)
+{
+ return(0);
+}
+
+__attribute__((weak)) uint8_t External_24_IRQHandler(void)
+{
+ return(0);
+}
+
+__attribute__((weak)) uint8_t External_25_IRQHandler(void)
+{
+ return(0);
+}
+
+__attribute__((weak)) uint8_t External_26_IRQHandler(void)
+{
+ return(0);
+}
+
+__attribute__((weak)) uint8_t External_27_IRQHandler(void)
+{
+ return(0);
+}
+
+__attribute__((weak)) uint8_t External_28_IRQHandler(void)
+{
+ return(0);
+}
+
+__attribute__((weak)) uint8_t External_29_IRQHandler(void)
+{
+ return(0);
+}
+
+__attribute__((weak)) uint8_t External_30_IRQHandler(void)
+{
+ return(0);
+}
+
+__attribute__((weak)) uint8_t External_31_IRQHandler(void)
+{
+ return(0);
+}
+
+
diff --git a/sw/bsp/hal/syscalls.c b/sw/bsp/hal/syscalls.c
new file mode 100644
index 00000000..9f73838f
--- /dev/null
+++ b/sw/bsp/hal/syscalls.c
@@ -0,0 +1,438 @@
+/* An extremely minimalist syscalls.c for newlib
+ * Based on riscv newlib libgloss/riscv/sys_*.c
+ *
+ * Copyright (c) 2020 Thales.
+ * Copyright 2019 Clifford Wolf
+ * Copyright 2019 ETH Zürich and University of Bologna
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES WITH
+ * REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY
+ * AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT,
+ * INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM
+ * LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR
+ * OTHER TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
+ * PERFORMANCE OF THIS SOFTWARE.
+ */
+// Additional contributions by:
+// Sebastien Jacq - sjthales on github.com
+//
+// =========================================================================== //
+// Revisions :
+// Date Version Author Description
+// 2020-10-06 0.1 S.Jacq modification of the Test for CVA6 softcore
+// =========================================================================== //
+
+#include <sys/stat.h>
+#include <sys/timeb.h>
+#include <sys/times.h>
+#include <sys/utime.h>
+#include <newlib.h>
+#include <unistd.h>
+#include <errno.h>
+#include <machine/syscall.h>
+#include <assert.h>
+#undef errno
+extern int errno;
+
+/* write to this reg for outputting strings */
+#define STDOUT_REG 0x10000000
+/* write test result of program to this reg */
+#define RESULT_REG 0x20000000
+/* write exit value of program to this reg */
+#define EXIT_REG 0x80040000
+
+#define STDOUT_FILENO 1
+
+/* It turns out that older newlib versions use different symbol names which goes
+ * against newlib recommendations. Anyway this is fixed in later version.
+ */
+#if __NEWLIB__ <= 2 && __NEWLIB_MINOR__ <= 5
+#define _sbrk sbrk
+#define _write write
+#define _close close
+#define _lseek lseek
+#define _read read
+#define _fstat fstat
+#define _isatty isatty
+#endif
+
+/************************************************************************************/
+/********************** STDIO_THRU_UART ********************************/
+/************************************************************************************/
+#ifdef STDIO_THRU_UART
+#include "uart.h"
+
+#ifndef STDIO_BAUD_RATE
+#define STDIO_BAUD_RATE UART_115200_BAUD
+#endif
+
+static uart_instance_t * const gp_my_uart = &g_uart_0;
+
+/*------------------------------------------------------------------------------
+ * Global flag used to indicate if the UART driver needs to be initialized.
+ */
+static int g_stdio_uart_init_done = 0;
+
+#endif /* STDIO_THRU_UART */
+/***********************************************************************************/
+/********************** END STDIO_THRU_UART ********************************/
+/************************************************************************************/
+
+
+
+/* Upstream newlib now defines this in libgloss/riscv/internal_syscall.h. */
+long
+__syscall_error(long a0)
+{
+ errno = -a0;
+ return -1;
+}
+
+void unimplemented_syscall()
+{
+ const char *p = "Unimplemented system call called!\n";
+ while (*p)
+ *(volatile int *)STDOUT_REG = *(p++);
+}
+
+int nanosleep(const struct timespec *rqtp, struct timespec *rmtp)
+{
+ errno = ENOSYS;
+ return -1;
+}
+
+int _access(const char *file, int mode)
+{
+ errno = ENOSYS;
+ return -1;
+}
+
+int _chdir(const char *path)
+{
+ errno = ENOSYS;
+ return -1;
+}
+
+int _chmod(const char *path, mode_t mode)
+{
+ errno = ENOSYS;
+ return -1;
+}
+
+int _chown(const char *path, uid_t owner, gid_t group)
+{
+ errno = ENOSYS;
+ return -1;
+}
+
+int _close(int file)
+{
+ return -1;
+}
+
+int _execve(const char *name, char *const argv[], char *const env[])
+{
+ errno = ENOMEM;
+ return -1;
+}
+
+void _exit(int exit_status)
+{
+ *(volatile int *)EXIT_REG = exit_status;
+ asm volatile("wfi");
+ /* _exit should not return */
+ while (1) {};
+}
+
+int _faccessat(int dirfd, const char *file, int mode, int flags)
+{
+ errno = ENOSYS;
+ return -1;
+}
+
+int _fork(void)
+{
+ errno = EAGAIN;
+ return -1;
+}
+
+int _fstat(int file, struct stat *st)
+{
+ st->st_mode = S_IFCHR;
+ return 0;
+ // errno = -ENOSYS;
+ // return -1;
+}
+
+int _fstatat(int dirfd, const char *file, struct stat *st, int flags)
+{
+ errno = ENOSYS;
+ return -1;
+}
+
+int _ftime(struct timeb *tp)
+{
+ errno = ENOSYS;
+ return -1;
+}
+
+char *_getcwd(char *buf, size_t size)
+{
+ errno = -ENOSYS;
+ return NULL;
+}
+
+int _getpid()
+{
+ return 1;
+}
+
+int _gettimeofday(struct timeval *tp, void *tzp)
+{
+ errno = -ENOSYS;
+ return -1;
+}
+
+int _isatty(int file)
+{
+ return (file == STDOUT_FILENO);
+}
+
+int _kill(int pid, int sig)
+{
+ errno = EINVAL;
+ return -1;
+}
+
+int _link(const char *old_name, const char *new_name)
+{
+ errno = EMLINK;
+ return -1;
+}
+
+off_t _lseek(int file, off_t ptr, int dir)
+{
+ return 0;
+}
+
+int _lstat(const char *file, struct stat *st)
+{
+ errno = ENOSYS;
+ return -1;
+}
+
+int _open(const char *name, int flags, int mode)
+{
+ return -1;
+}
+
+int _openat(int dirfd, const char *name, int flags, int mode)
+{
+ errno = ENOSYS;
+ return -1;
+}
+
+ssize_t _read(int file, void *ptr, size_t len)
+{
+ return 0;
+}
+
+int _stat(const char *file, struct stat *st)
+{
+ st->st_mode = S_IFCHR;
+ return 0;
+ // errno = ENOSYS;
+ // return -1;
+}
+
+long _sysconf(int name)
+{
+
+ return -1;
+}
+
+clock_t _times(struct tms *buf)
+{
+ return -1;
+}
+
+int _unlink(const char *name)
+{
+ errno = ENOENT;
+ return -1;
+}
+
+int _utime(const char *path, const struct utimbuf *times)
+{
+ errno = ENOSYS;
+ return -1;
+}
+
+int _wait(int *status)
+{
+ errno = ECHILD;
+ return -1;
+}
+
+ssize_t _write(int file, const void *ptr, size_t len)
+{
+
+#ifdef STDIO_THRU_UART
+ /*--------------------------------------------------------------------------
+ * Initialize the UART driver if it is the first time this function is
+ * called.
+ */
+
+ if(!g_stdio_uart_init_done)
+ {
+ UART_init(gp_my_uart,
+ STDIO_BAUD_RATE,
+ UART_DATA_8_BITS | UART_NO_PARITY | UART_ONE_STOP_BIT);
+
+ g_stdio_uart_init_done = 1;
+ }
+
+ /*--------------------------------------------------------------------------
+ * Output text to the UART.
+ */
+ UART_polled_tx(gp_my_uart, (uint8_t *)ptr, len);
+
+ return len;
+
+
+#else /* STDIO_THRU_UART */
+
+ const char *cptr = (char *)ptr;
+ if (file != STDOUT_FILENO)
+ {
+ errno = ENOSYS;
+ return -1;
+ }
+
+ const void *eptr = cptr + len;
+ while (cptr != eptr)
+ *(volatile int *)STDOUT_REG = *cptr++;
+ return len;
+#endif /* STDIO_THRU_UART */
+
+}
+
+extern char __heap_start[];
+extern char __heap_end[];
+static char *brk = __heap_start;
+
+int _brk(void *addr)
+{
+ brk = addr;
+ return 0;
+}
+
+void *_sbrk(ptrdiff_t incr)
+{
+ char *old_brk = brk;
+ register long sp asm("sp");
+
+ char *new_brk = brk += incr;
+ if (new_brk < (char *) sp && new_brk < __heap_end)
+ {
+ brk = new_brk;
+
+ return old_brk;
+ }
+ else
+ {
+ errno = ENOMEM;
+ return (void *) -1;
+ }
+}
+
+void handle_syscall (long a0,
+ long a1,
+ long a2,
+ long a3,
+ __attribute__((unused)) long a4,
+ __attribute__((unused)) long a5,
+ __attribute__((unused)) long a6,
+ long a7) {
+ #ifdef __riscv_32e
+ register long syscall_id asm("t0");
+ #else
+ long syscall_id = a7;
+ #endif
+
+ switch (syscall_id) {
+ case SYS_exit:
+ _exit (a0);
+ break;
+ case SYS_read:
+ _read (a0, (void *) a1, a2);
+ break;
+ case SYS_write:
+ _write (a0, (const void *) a1, a2);
+ break;
+ case SYS_getpid:
+ _getpid ();
+ break;
+ case SYS_kill:
+ _kill (a0, a1);
+ break;
+ case SYS_open:
+ _open ((const char *) a0, a1, a2);
+ break;
+ case SYS_openat:
+ _openat (a0, (const char *) a1, a2, a3);
+ break;
+ case SYS_close:
+ _close (a0);
+ break;
+ case SYS_lseek:
+ _lseek (a0, a1, a2);
+ break;
+ case SYS_brk:
+ _brk ((void *) a0);
+ break;
+ case SYS_link:
+ _link ((const char *) a0, (const char *) a1);
+ break;
+ case SYS_unlink:
+ _unlink ((const char *) a0);
+ break;
+ case SYS_chdir:
+ _chdir ((const char *) a0);
+ break;
+ case SYS_getcwd:
+ _getcwd ((char *) a0, a1);
+ break;
+ case SYS_stat:
+ _stat ((const char *) a0, (struct stat *) a1);
+ break;
+ case SYS_fstat:
+ _fstat (a0, (struct stat *) a1);
+ break;
+ case SYS_lstat:
+ _lstat ((const char *) a0, (struct stat *) a1);
+ break;
+ case SYS_fstatat:
+ _fstatat (a0, (const char *) a1, (struct stat *) a2, a3);
+ break;
+ case SYS_access:
+ _access ((const char *) a0, a1);
+ break;
+ case SYS_faccessat:
+ _faccessat (a0, (const char *) a1, a2, a3);
+ break;
+ case SYS_gettimeofday:
+ _gettimeofday ((struct timeval *) a0, (void *) a1);
+ break;
+ case SYS_times:
+ _times ((struct tms *) a0);
+ break;
+ default:
+ unimplemented_syscall ();
+ break;
+ }
+}
diff --git a/sw/bsp/hal/vectors.S b/sw/bsp/hal/vectors.S
new file mode 100644
index 00000000..53280060
--- /dev/null
+++ b/sw/bsp/hal/vectors.S
@@ -0,0 +1,64 @@
+/*
+* Copyright (c) 2020 Thales.
+* Copyright 2019 ETH Zürich and University of Bologna
+*
+* Licensed under the Apache License, Version 2.0 (the "License");
+* you may not use this file except in compliance with the License.
+* You may obtain a copy of the License at
+*
+* http://www.apache.org/licenses/LICENSE-2.0
+*
+* Unless required by applicable law or agreed to in writing, software
+* distributed under the License is distributed on an "AS IS" BASIS,
+* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+* See the License for the specific language governing permissions and
+* limitations under the License.
+*/
+// Additional contributions by:
+// Sebastien Jacq - sjthales on github.com
+//
+// Description: interrupt vector table
+//
+// =========================================================================== //
+// Revisions :
+// Date Version Author Description
+// 2020-10-06 0.1 S.Jacq modification of the Test for CVA6 softcore
+// =========================================================================== //
+
+.section .vectors, "ax"
+.option norvc
+.global vector_table
+
+vector_table:
+ j sw_irq_handler
+ j UART_0_PLIC_IRQHandler
+ j __no_irq_handler
+ j __no_irq_handler
+ j __no_irq_handler
+ j __no_irq_handler
+ j __no_irq_handler
+ j __no_irq_handler
+ j __no_irq_handler
+ j __no_irq_handler
+ j __no_irq_handler
+ j __no_irq_handler
+ j __no_irq_handler
+ j __no_irq_handler
+ j __no_irq_handler
+ j __no_irq_handler
+ j __no_irq_handler
+ j __no_irq_handler
+ j __no_irq_handler
+ j __no_irq_handler
+ j __no_irq_handler
+ j __no_irq_handler
+ j __no_irq_handler
+ j __no_irq_handler
+ j __no_irq_handler
+ j __no_irq_handler
+ j __no_irq_handler
+ j __no_irq_handler
+ j __no_irq_handler
+ j __no_irq_handler
+ j __no_irq_handler
+ j verification_irq_handler
diff --git a/sw/utils/bin2mem.py b/sw/utils/bin2mem.py
new file mode 100755
index 00000000..a8700696
--- /dev/null
+++ b/sw/utils/bin2mem.py
@@ -0,0 +1,60 @@
+#!/usr/bin/env python
+
+# Copyright (c) 2020 Thales.
+#
+# Copyright and related rights are licensed under the Apache
+# License, Version 2.0 (the "License"); you may not use this file except in
+# compliance with the License. You may obtain a copy of the License at
+# https://www.apache.org/licenses/LICENSE-2.0. Unless required by applicable law
+# or agreed to in writing, software, hardware and materials distributed under
+# this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR
+# CONDITIONS OF ANY KIND, either express or implied. See the License for the
+# specific language governing permissions and limitations under the License.
+#
+# Author: Sebastien Jacq - sjthales on github.com
+#
+# Additional contributions by:
+#
+#
+# script Name: bin2mem
+# Project Name: CVA6 softcore
+# Language: Python
+#
+# Description: Script to generate mem data file for simulation from binary
+# application file.
+#
+# =========================================================================== #
+# Revisions :
+# Date Version Author Description
+# 2020-10-06 0.1 S.Jacq Created
+# =========================================================================== #
+
+import sys
+import math
+import binascii
+
+###############################################################################
+# Start of file
+###############################################################################
+if(len(sys.argv) < 2):
+ print "Usage bin2mem.py FILENAME"
+ quit()
+
+filename = sys.argv[1].strip('.bin') + ".mem"
+
+mem_file = open(filename, 'wb')
+
+with open(sys.argv[1], "rb") as f:
+ bytes_read = f.read(8)
+ while bytes_read:
+ bytes_read_inv = bytes_read[::-1]
+ mem_file.write("%s\n" %binascii.hexlify(bytes_read_inv) )
+ bytes_read = f.read(8)
+
+###############################################################################
+# close all files
+###############################################################################
+
+mem_file.close()
+
+
diff --git a/tb/ariane_tb.sv b/tb/ariane_tb.sv
index eb280754..b89f4223 100644
--- a/tb/ariane_tb.sv
+++ b/tb/ariane_tb.sv
@@ -1,3 +1,4 @@
+// Copyright (c) 2020 Thales.
// Copyright 2018 ETH Zurich and University of Bologna.
// Copyright and related rights are licensed under the Solderpad Hardware
// License, Version 0.51 (the "License"); you may not use this file except in
@@ -10,145 +11,127 @@
//
// Author: Florian Zaruba, ETH Zurich
// Date: 15/04/2017
+//
+// Additional contributions by:
+// Sebastien Jacq - sjthales on github.com
+//
// Description: Top level testbench module. Instantiates the top level DUT, configures
// the virtual interfaces and starts the test passed by +UVM_TEST+
-
+//
+// =========================================================================== //
+// Revisions :
+// Date Version Author Description
+// 2020-10-06 0.1 S.Jacq modification of the Test for CVA6 softcore
+// =========================================================================== //
import ariane_pkg::*;
-import uvm_pkg::*;
+import jtag_pkg::*;
-`include "uvm_macros.svh"
+`define EXIT_SUCCESS 0
+`define EXIT_FAIL 1
+`define EXIT_ERROR -1
-`define MAIN_MEM(P) dut.i_sram.genblk1[0].genblk1.i_ram.Mem_DP[(``P``)]
+module ariane_tb;
-import "DPI-C" function read_elf(input string filename);
-import "DPI-C" function byte get_section(output longint address, output longint len);
-import "DPI-C" context function byte read_section(input longint address, inout byte buffer[]);
+ logic [255:0][31:0] jtag_data;
-module ariane_tb;
+ jtag_pkg::debug_mode_if_t debug_mode_if = new;
+
+ logic [8:0] jtag_conf_reg, jtag_conf_rego; //22bits but actually only the last 9bits are used
+ localparam BEGIN_MEM_INSTR = 32'h80000080;
- static uvm_cmdline_processor uvcl = uvm_cmdline_processor::get_inst();
+ int exit_status = `EXIT_ERROR;
localparam int unsigned CLOCK_PERIOD = 20ns;
- // toggle with RTC period
- localparam int unsigned RTC_CLOCK_PERIOD = 30.517us;
- localparam NUM_WORDS = 2**25;
+ localparam NUM_WORDS = 2**18;
logic clk_i;
logic rst_ni;
logic rtc_i;
- longint unsigned cycles;
- longint unsigned max_cycles;
+ logic jtag_TDO_driven;
- logic [31:0] exit_o;
+ logic jtag_TRSTn = 1'b0;
+ logic jtag_TCK = 1'b0;
+ logic jtag_TDI = 1'b0;
+ logic jtag_TMS = 1'b0;
+ logic jtag_TDO_data;
- string binary = "";
+ string binary_mem ;
+ // Device under test instance
ariane_testharness #(
.NUM_WORDS ( NUM_WORDS ),
- .InclSimDTM ( 1'b1 ),
.StallRandomOutput ( 1'b1 ),
.StallRandomInput ( 1'b1 )
) dut (
.clk_i,
.rst_ni,
.rtc_i,
- .exit_o
- );
-
-`ifdef SPIKE_TANDEM
- spike #(
- .Size ( NUM_WORDS * 8 )
- ) i_spike (
- .clk_i,
- .rst_ni,
- .clint_tick_i ( rtc_i ),
- .commit_instr_i ( dut.i_ariane.commit_instr_id_commit ),
- .commit_ack_i ( dut.i_ariane.commit_ack ),
- .exception_i ( dut.i_ariane.ex_commit ),
- .waddr_i ( dut.i_ariane.waddr_commit_id ),
- .wdata_i ( dut.i_ariane.wdata_commit_id ),
- .priv_lvl_i ( dut.i_ariane.priv_lvl )
+ .jtag_TCK,
+ .jtag_TMS,
+ .jtag_TDI,
+ .jtag_TRSTn,
+ .jtag_TDO_data,
+ .jtag_TDO_driven
);
- initial begin
- $display("Running binary in tandem mode");
- end
-`endif
// Clock process
initial begin
clk_i = 1'b0;
- rst_ni = 1'b0;
repeat(8)
#(CLOCK_PERIOD/2) clk_i = ~clk_i;
- rst_ni = 1'b1;
forever begin
#(CLOCK_PERIOD/2) clk_i = 1'b1;
#(CLOCK_PERIOD/2) clk_i = 1'b0;
-
- //if (cycles > max_cycles)
- // $fatal(1, "Simulation reached maximum cycle count of %d", max_cycles);
-
- cycles++;
end
end
- initial begin
- forever begin
- rtc_i = 1'b0;
- #(RTC_CLOCK_PERIOD/2) rtc_i = 1'b1;
- #(RTC_CLOCK_PERIOD/2) rtc_i = 1'b0;
- end
- end
- initial begin
- forever begin
+ // testbench driver process
+ initial
+ begin
+ logic [1:0] dm_op;
+ logic [31:0] dm_data;
+ logic [6:0] dm_addr;
+ logic error;
+ automatic logic [9:0] FC_CORE_ID = {5'd0,5'd0};
- wait (exit_o[0]);
+ $display("[TB] %t - Asserting hard reset", $realtime);
+ rst_ni = 1'b0;
- if ((exit_o >> 1)) begin
- `uvm_error( "Core Test", $sformatf("*** FAILED *** (tohost = %0d)", (exit_o >> 1)))
- end else begin
- `uvm_info( "Core Test", $sformatf("*** SUCCESS *** (tohost = %0d)", (exit_o >> 1)), UVM_LOW)
- end
+ #10ns
+
+ jtag_pkg::jtag_reset(jtag_TCK, jtag_TMS, jtag_TRSTn, jtag_TDI);
+ jtag_pkg::jtag_softreset(jtag_TCK, jtag_TMS, jtag_TRSTn, jtag_TDI);
+ #5us;
+
+ rst_ni = 1'b1;
- $finish();
- end
- end
+ debug_mode_if.init_dmi_access(jtag_TCK, jtag_TMS, jtag_TRSTn, jtag_TDI);
+
+ debug_mode_if.set_dmactive(1'b1, jtag_TCK, jtag_TMS, jtag_TRSTn, jtag_TDI, jtag_TDO_data);
+
+ debug_mode_if.set_hartsel(FC_CORE_ID, jtag_TCK, jtag_TMS, jtag_TRSTn, jtag_TDI, jtag_TDO_data);
+
+ $display("[TB] %t - Halting the Core", $realtime);
+ debug_mode_if.halt_harts(jtag_TCK, jtag_TMS, jtag_TRSTn, jtag_TDI, jtag_TDO_data);
+
+
+ $value$plusargs("binary_mem=%s", binary_mem);
+ $display("Loading application to memory from %s", binary_mem);
+ $readmemh(binary_mem, dut.i_sram.genblk1[0].genblk1.i_ram.Mem_DP);
+
+
+ // write dpc to addr_i so that we know where we resume
+ $display("[TB] %t - Writing the boot address into dpc", $realtime);
+ debug_mode_if.write_reg_abstract_cmd(riscv::CSR_DPC, BEGIN_MEM_INSTR, jtag_TCK, jtag_TMS, jtag_TRSTn, jtag_TDI, jtag_TDO_data);
+
+
+ // we have set dpc and loaded the binary, we can go now
+ $display("[TB] %t - Resuming the CORE", $realtime);
+ debug_mode_if.resume_harts(jtag_TCK, jtag_TMS, jtag_TRSTn, jtag_TDI, jtag_TDO_data);
- // for faster simulation we can directly preload the ELF
- // Note that we are loosing the capabilities to use risc-fesvr though
- initial begin
- automatic logic [7:0][7:0] mem_row;
- longint address, len;
- byte buffer[];
- void'(uvcl.get_arg_value("+PRELOAD=", binary));
-
- if (binary != "") begin
- `uvm_info( "Core Test", $sformatf("Preloading ELF: %s", binary), UVM_LOW)
-
- void'(read_elf(binary));
- // wait with preloading, otherwise randomization will overwrite the existing value
- wait(rst_ni);
-
- // while there are more sections to process
- while (get_section(address, len)) begin
- automatic int num_words = (len+7)/8;
- `uvm_info( "Core Test", $sformatf("Loading Address: %x, Length: %x", address, len),
-UVM_LOW)
- buffer = new [num_words*8];
- void'(read_section(address, buffer));
- // preload memories
- // 64-bit
- for (int i = 0; i < num_words; i++) begin
- mem_row = '0;
- for (int j = 0; j < 8; j++) begin
- mem_row[j] = buffer[i*8 + j];
- end
- `MAIN_MEM((address[28:0] >> 3) + i) = mem_row;
- end
- end
- end
end
+
endmodule
diff --git a/tb/ariane_testharness.sv b/tb/ariane_testharness.sv
index ba8f9aa8..e06ddc1f 100644
--- a/tb/ariane_testharness.sv
+++ b/tb/ariane_testharness.sv
@@ -1,3 +1,4 @@
+// Copyright (c) 2020 Thales.
// Copyright 2018 ETH Zurich and University of Bologna.
// Copyright and related rights are licensed under the Solderpad Hardware
// License, Version 0.51 (the "License"); you may not use this file except in
@@ -10,26 +11,36 @@
//
// Author: Florian Zaruba, ETH Zurich
// Date: 19.03.2017
+//
+// Additional contributions by:
+// Sebastien Jacq - sjthales on github.com
+//
// Description: Test-harness for Ariane
// Instantiates an AXI-Bus and memories
+//
+// =========================================================================== //
+// Revisions :
+// Date Version Author Description
+// 2020-10-06 0.1 S.Jacq modification for CVA6 softcore
+// =========================================================================== //
module ariane_testharness #(
parameter int unsigned AXI_USER_WIDTH = 1,
parameter int unsigned AXI_ADDRESS_WIDTH = 64,
parameter int unsigned AXI_DATA_WIDTH = 64,
-`ifdef DROMAJO
- parameter bit InclSimDTM = 1'b0,
-`else
- parameter bit InclSimDTM = 1'b1,
-`endif
parameter int unsigned NUM_WORDS = 2**25, // memory size
parameter bit StallRandomOutput = 1'b0,
parameter bit StallRandomInput = 1'b0
) (
- input logic clk_i,
- input logic rtc_i,
- input logic rst_ni,
- output logic [31:0] exit_o
+ input logic clk_i,
+ input logic rtc_i,
+ input logic rst_ni,
+ input logic jtag_TCK,
+ input logic jtag_TMS,
+ input logic jtag_TDI,
+ input logic jtag_TRSTn,
+ output logic jtag_TDO_data,
+ output logic jtag_TDO_driven
);
// disable test-enable
@@ -42,37 +53,23 @@ module ariane_testharness #(
logic init_done;
logic [31:0] jtag_exit, dmi_exit;
- logic jtag_TCK;
- logic jtag_TMS;
- logic jtag_TDI;
- logic jtag_TRSTn;
- logic jtag_TDO_data;
- logic jtag_TDO_driven;
-
logic debug_req_valid;
logic debug_req_ready;
logic debug_resp_valid;
logic debug_resp_ready;
logic jtag_req_valid;
- logic [6:0] jtag_req_bits_addr;
- logic [1:0] jtag_req_bits_op;
- logic [31:0] jtag_req_bits_data;
+
logic jtag_resp_ready;
logic jtag_resp_valid;
- logic dmi_req_valid;
- logic dmi_resp_ready;
- logic dmi_resp_valid;
-
dm::dmi_req_t jtag_dmi_req;
- dm::dmi_req_t dmi_req;
-
dm::dmi_req_t debug_req;
dm::dmi_resp_t debug_resp;
assign test_en = 1'b0;
+
AXI_BUS #(
.AXI_ADDR_WIDTH ( AXI_ADDRESS_WIDTH ),
.AXI_DATA_WIDTH ( AXI_DATA_WIDTH ),
@@ -100,34 +97,10 @@ module ariane_testharness #(
// ---------------
assign init_done = rst_ni;
- initial begin
- if (!$value$plusargs("jtag_rbb_enable=%b", jtag_enable)) jtag_enable = 'h0;
- if (riscv::XLEN != 32 & riscv::XLEN != 64) $error("XLEN different from 32 and 64");
- end
-
- // debug if MUX
- assign debug_req_valid = (jtag_enable[0]) ? jtag_req_valid : dmi_req_valid;
- assign debug_resp_ready = (jtag_enable[0]) ? jtag_resp_ready : dmi_resp_ready;
- assign debug_req = (jtag_enable[0]) ? jtag_dmi_req : dmi_req;
- assign exit_o = (jtag_enable[0]) ? jtag_exit : dmi_exit;
- assign jtag_resp_valid = (jtag_enable[0]) ? debug_resp_valid : 1'b0;
- assign dmi_resp_valid = (jtag_enable[0]) ? 1'b0 : debug_resp_valid;
-
- // SiFive's SimJTAG Module
- // Converts to DPI calls
- SimJTAG i_SimJTAG (
- .clock ( clk_i ),
- .reset ( ~rst_ni ),
- .enable ( jtag_enable[0] ),
- .init_done ( init_done ),
- .jtag_TCK ( jtag_TCK ),
- .jtag_TMS ( jtag_TMS ),
- .jtag_TDI ( jtag_TDI ),
- .jtag_TRSTn ( jtag_TRSTn ),
- .jtag_TDO_data ( jtag_TDO_data ),
- .jtag_TDO_driven ( jtag_TDO_driven ),
- .exit ( jtag_exit )
- );
+ assign debug_req_valid = jtag_req_valid;
+ assign debug_resp_ready = jtag_resp_ready;
+ assign debug_req = jtag_dmi_req;
+ assign jtag_resp_valid = debug_resp_valid;
dmi_jtag i_dmi_jtag (
.clk_i ( clk_i ),
@@ -148,52 +121,6 @@ module ariane_testharness #(
.tdo_oe_o ( jtag_TDO_driven )
);
- // SiFive's SimDTM Module
- // Converts to DPI calls
- logic [1:0] debug_req_bits_op;
- assign dmi_req.op = dm::dtm_op_e'(debug_req_bits_op);
-
- if (InclSimDTM) begin
- SimDTM i_SimDTM (
- .clk ( clk_i ),
- .reset ( ~rst_ni ),
- .debug_req_valid ( dmi_req_valid ),
- .debug_req_ready ( debug_req_ready ),
- .debug_req_bits_addr ( dmi_req.addr ),
- .debug_req_bits_op ( debug_req_bits_op ),
- .debug_req_bits_data ( dmi_req.data ),
- .debug_resp_valid ( dmi_resp_valid ),
- .debug_resp_ready ( dmi_resp_ready ),
- .debug_resp_bits_resp ( debug_resp.resp ),
- .debug_resp_bits_data ( debug_resp.data ),
- .exit ( dmi_exit )
- );
- end else begin
- assign dmi_req_valid = '0;
- assign debug_req_bits_op = '0;
- assign dmi_exit = 1'b0;
- end
-
- // this delay window allows the core to read and execute init code
- // from the bootrom before the first debug request can interrupt
- // core. this is needed in cases where an fsbl is involved that
- // expects a0 and a1 to be initialized with the hart id and a
- // pointer to the dev tree, respectively.
- localparam int unsigned DmiDelCycles = 500;
-
- logic debug_req_core_ungtd;
- int dmi_del_cnt_d, dmi_del_cnt_q;
-
- assign dmi_del_cnt_d = (dmi_del_cnt_q) ? dmi_del_cnt_q - 1 : 0;
- assign debug_req_core = (dmi_del_cnt_q) ? 1'b0 : debug_req_core_ungtd;
-
- always_ff @(posedge clk_i or negedge rst_ni) begin : p_dmi_del_cnt
- if(!rst_ni) begin
- dmi_del_cnt_q <= DmiDelCycles;
- end else begin
- dmi_del_cnt_q <= dmi_del_cnt_d;
- end
- end
ariane_axi::req_t dm_axi_m_req;
ariane_axi::resp_t dm_axi_m_resp;
@@ -225,7 +152,7 @@ module ariane_testharness #(
.testmode_i ( test_en ),
.ndmreset_o ( ndmreset ),
.dmactive_o ( ), // active debug session
- .debug_req_o ( debug_req_core_ungtd ),
+ .debug_req_o ( debug_req_core ),
.unavailable_i ( '0 ),
.hartinfo_i ( {ariane_pkg::DebugHartInfo} ),
.slave_req_i ( dm_slave_req ),
@@ -324,21 +251,13 @@ module ariane_testharness #(
.data_i ( rom_rdata )
);
-`ifdef DROMAJO
- dromajo_bootrom i_bootrom (
- .clk_i ( clk_i ),
- .req_i ( rom_req ),
- .addr_i ( rom_addr ),
- .rdata_o ( rom_rdata )
- );
-`else
bootrom i_bootrom (
.clk_i ( clk_i ),
.req_i ( rom_req ),
.addr_i ( rom_addr ),
.rdata_o ( rom_rdata )
);
-`endif
+
// ------------------------------
// Memory + Exclusive Access
// ------------------------------
@@ -527,9 +446,6 @@ module ariane_testharness #(
sram #(
.DATA_WIDTH ( AXI_DATA_WIDTH ),
-`ifdef DROMAJO
- .DROMAJO_RAM (1),
-`endif
.NUM_WORDS ( NUM_WORDS )
) i_sram (
.clk_i ( clk_i ),
@@ -555,8 +471,6 @@ module ariane_testharness #(
.AXI_DATA_WIDTH ( AXI_DATA_WIDTH ),
.AXI_USER_WIDTH ( AXI_USER_WIDTH ),
.AXI_ID_WIDTH ( ariane_soc::IdWidth )
- // .MASTER_SLICE_DEPTH ( 0 ),
- // .SLAVE_SLICE_DEPTH ( 0 )
) i_axi_xbar (
.clk ( clk_i ),
.rst_n ( ndmreset_n ),
@@ -631,16 +545,7 @@ module ariane_testharness #(
.AxiAddrWidth ( AXI_ADDRESS_WIDTH ),
.AxiDataWidth ( AXI_DATA_WIDTH ),
.AxiIdWidth ( ariane_soc::IdWidthSlave ),
-`ifndef VERILATOR
- // disable UART when using Spike, as we need to rely on the mockuart
- `ifdef SPIKE_TANDEM
- .InclUART ( 1'b0 ),
- `else
.InclUART ( 1'b1 ),
- `endif
-`else
- .InclUART ( 1'b0 ),
-`endif
.InclSPI ( 1'b0 ),
.InclEthernet ( 1'b0 )
) i_ariane_peripherals (
@@ -689,12 +594,7 @@ module ariane_testharness #(
.irq_i ( irqs ),
.ipi_i ( ipi ),
.time_irq_i ( timer_irq ),
-// Disable Debug when simulating with Spike
-`ifdef SPIKE_TANDEM
- .debug_req_i ( 1'b0 ),
-`else
.debug_req_i ( debug_req_core ),
-`endif
.axi_req_o ( axi_ariane_req ),
.axi_resp_i ( axi_ariane_resp )
);
@@ -721,70 +621,4 @@ module ariane_testharness #(
$warning("B Response Errored");
end
end
-
-`ifdef AXI_SVA
- // AXI 4 Assertion IP integration - You will need to get your own copy of this IP if you want
- // to use it
- Axi4PC #(
- .DATA_WIDTH(ariane_axi::DataWidth),
- .WID_WIDTH(ariane_soc::IdWidthSlave),
- .RID_WIDTH(ariane_soc::IdWidthSlave),
- .AWUSER_WIDTH(ariane_axi::UserWidth),
- .WUSER_WIDTH(ariane_axi::UserWidth),
- .BUSER_WIDTH(ariane_axi::UserWidth),
- .ARUSER_WIDTH(ariane_axi::UserWidth),
- .RUSER_WIDTH(ariane_axi::UserWidth),
- .ADDR_WIDTH(ariane_axi::AddrWidth)
- ) i_Axi4PC (
- .ACLK(clk_i),
- .ARESETn(ndmreset_n),
- .AWID(dram.aw_id),
- .AWADDR(dram.aw_addr),
- .AWLEN(dram.aw_len),
- .AWSIZE(dram.aw_size),
- .AWBURST(dram.aw_burst),
- .AWLOCK(dram.aw_lock),
- .AWCACHE(dram.aw_cache),
- .AWPROT(dram.aw_prot),
- .AWQOS(dram.aw_qos),
- .AWREGION(dram.aw_region),
- .AWUSER(dram.aw_user),
- .AWVALID(dram.aw_valid),
- .AWREADY(dram.aw_ready),
- .WLAST(dram.w_last),
- .WDATA(dram.w_data),
- .WSTRB(dram.w_strb),
- .WUSER(dram.w_user),
- .WVALID(dram.w_valid),
- .WREADY(dram.w_ready),
- .BID(dram.b_id),
- .BRESP(dram.b_resp),
- .BUSER(dram.b_user),
- .BVALID(dram.b_valid),
- .BREADY(dram.b_ready),
- .ARID(dram.ar_id),
- .ARADDR(dram.ar_addr),
- .ARLEN(dram.ar_len),
- .ARSIZE(dram.ar_size),
- .ARBURST(dram.ar_burst),
- .ARLOCK(dram.ar_lock),
- .ARCACHE(dram.ar_cache),
- .ARPROT(dram.ar_prot),
- .ARQOS(dram.ar_qos),
- .ARREGION(dram.ar_region),
- .ARUSER(dram.ar_user),
- .ARVALID(dram.ar_valid),
- .ARREADY(dram.ar_ready),
- .RID(dram.r_id),
- .RLAST(dram.r_last),
- .RDATA(dram.r_data),
- .RRESP(dram.r_resp),
- .RUSER(dram.r_user),
- .RVALID(dram.r_valid),
- .RREADY(dram.r_ready),
- .CACTIVE('0),
- .CSYSREQ('0),
- .CSYSACK('0)
- );
-`endif
endmodule
diff --git a/tb/jtag_pkg.sv b/tb/jtag_pkg.sv
new file mode 100644
index 00000000..dcec049b
--- /dev/null
+++ b/tb/jtag_pkg.sv
@@ -0,0 +1,2908 @@
+// Copyright (c) 2020 Thales.
+// Copyright 2018 ETH Zurich and University of Bologna.
+// Copyright and related rights are licensed under the Solderpad Hardware
+// License, Version 0.51 (the "License"); you may not use this file except in
+// compliance with the License. You may obtain a copy of the License at
+// http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law
+// or agreed to in writing, software, hardware and materials distributed under
+// this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR
+// CONDITIONS OF ANY KIND, either express or implied. See the License for the
+// specific language governing permissions and limitations under the License.
+
+/*
+ * jtag_pkg.sv
+ * Francesco Conti <fconti@iis.ee.ethz.ch>
+ * Antonio Pullini <pullinia@iis.ee.ethz.ch>
+ * Sebastien Jacq - sjthales on github.com
+ */
+
+import ariane_pkg::*;
+
+package jtag_pkg;
+
+ parameter int unsigned JTAG_SOC_INSTR_WIDTH = 5;
+ parameter logic [JTAG_SOC_INSTR_WIDTH-1:0] JTAG_SOC_IDCODE = 5'b00001;
+ parameter logic [JTAG_SOC_INSTR_WIDTH-1:0] JTAG_SOC_DTMCSR = 5'b10000;
+ parameter logic [JTAG_SOC_INSTR_WIDTH-1:0] JTAG_SOC_DMIACCESS = 5'b10001;
+ parameter logic [JTAG_SOC_INSTR_WIDTH-1:0] JTAG_SOC_AXIREG = 5'b00100;// NOT IN SPEC
+ parameter logic [JTAG_SOC_INSTR_WIDTH-1:0] JTAG_SOC_BBMUXREG = 5'b00101;// NOT IN SPEC
+ parameter logic [JTAG_SOC_INSTR_WIDTH-1:0] JTAG_SOC_CONFREG = 5'b00110;// NOT IN SPEC
+ parameter logic [JTAG_SOC_INSTR_WIDTH-1:0] JTAG_SOC_TESTMODEREG = 5'b01000;// NOT IN SPEC
+ parameter logic [JTAG_SOC_INSTR_WIDTH-1:0] JTAG_SOC_BISTREG = 5'b01001;// NOT IN SPEC
+ parameter logic [JTAG_SOC_INSTR_WIDTH-1:0] JTAG_SOC_BYPASS = 5'b11111;
+ parameter int unsigned JTAG_SOC_IDCODE_WIDTH = 32;
+ parameter int unsigned JTAG_SOC_BBMUXREG_WIDTH = 21;
+ parameter int unsigned JTAG_SOC_CLKGATEREG_WIDTH = 11;
+ parameter int unsigned JTAG_SOC_CONFREG_WIDTH = 16;
+ parameter int unsigned JTAG_SOC_TESTMODEREG_WIDTH = 4;
+ parameter int unsigned JTAG_SOC_BISTREG_WIDTH = 20;
+
+ parameter int unsigned JTAG_CLUSTER_INSTR_WIDTH = 5;
+ parameter logic [JTAG_CLUSTER_INSTR_WIDTH-1:0] JTAG_CLUSTER_IDCODE = 5'b0010;
+ parameter logic [JTAG_CLUSTER_INSTR_WIDTH-1:0] JTAG_CLUSTER_SAMPLE_PRELOAD = 5'b0001;
+ parameter logic [JTAG_CLUSTER_INSTR_WIDTH-1:0] JTAG_CLUSTER_EXTEST = 5'b0000;
+ parameter logic [JTAG_CLUSTER_INSTR_WIDTH-1:0] JTAG_CLUSTER_DEBUG = 5'b1000;
+ parameter logic [JTAG_CLUSTER_INSTR_WIDTH-1:0] JTAG_CLUSTER_MBIST = 5'b1001;
+ parameter logic [JTAG_CLUSTER_INSTR_WIDTH-1:0] JTAG_CLUSTER_BYPASS = 5'b1111;
+ parameter int unsigned JTAG_CLUSTER_IDCODE_WIDTH = 32;
+
+ parameter int unsigned JTAG_IDCODE_WIDTH = JTAG_SOC_IDCODE_WIDTH;
+ parameter int unsigned JTAG_INSTR_WIDTH = JTAG_SOC_INSTR_WIDTH;
+
+ parameter DMI_SIZE = 32+7+2;
+
+ task automatic jtag_wait_halfperiod(input int cycles);
+ //#(50000*cycles);
+ #(100*cycles);
+ endtask
+
+ task automatic jtag_clock(
+ input int cycles,
+ ref logic s_tck
+ );
+ for(int i=0; i<cycles; i=i+1) begin
+ s_tck = 1'b0;
+ jtag_wait_halfperiod(1);
+ s_tck = 1'b1;
+ jtag_wait_halfperiod(1);
+ s_tck = 1'b0;
+ end
+ endtask
+
+ task automatic jtag_reset(
+ ref logic s_tck,
+ ref logic s_tms,
+ ref logic s_trstn,
+ ref logic s_tdi
+ );
+ s_tms = 1'b0;
+ s_tck = 1'b0;
+ s_trstn = 1'b0;
+ s_tdi = 1'b0;
+ jtag_wait_halfperiod(2);
+ s_trstn = 1'b1;
+ endtask
+
+ task automatic jtag_softreset(
+ ref logic s_tck,
+ ref logic s_tms,
+ ref logic s_trstn,
+ ref logic s_tdi
+ );
+ s_tms = 1'b1;
+ s_trstn = 1'b1;
+ s_tdi = 1'b0;
+ jtag_clock(5, s_tck); //enter RST
+ s_tms = 1'b0;
+ jtag_clock(1, s_tck); // back to IDLE
+ $display("[JTAG] SoftReset Done(%t)",$realtime);
+
+ endtask
+
+ class JTAG_reg #(int unsigned size = 32, logic [(JTAG_CLUSTER_INSTR_WIDTH+JTAG_SOC_INSTR_WIDTH)-1:0] instr = 'h0);
+
+ task idle(
+ ref logic s_tck,
+ ref logic s_tms,
+ ref logic s_trstn,
+ ref logic s_tdi
+ );
+ s_trstn = 1'b1;
+ // from SHIFT_DR to RUN_TEST : tms sequence 10
+ s_tms = 1'b1;
+ s_tdi = 1'b0;
+ jtag_clock(1, s_tck);
+ s_tms = 1'b0;
+ jtag_clock(1, s_tck);
+ endtask
+
+ task update_and_goto_shift(
+ ref logic s_tck,
+ ref logic s_tms,
+ ref logic s_trstn,
+ ref logic s_tdi
+ );
+ s_trstn = 1'b1;
+ // from SHIFT_DR to RUN_TEST : tms sequence 110
+ s_tms = 1'b1;
+ s_tdi = 1'b0;
+ jtag_clock(1, s_tck);
+ s_tms = 1'b1;
+ jtag_clock(1, s_tck);
+ s_tms = 1'b0;
+ jtag_clock(1, s_tck);
+ jtag_clock(1, s_tck);
+ endtask
+
+ task jtag_goto_SHIFT_IR(
+ ref logic s_tck,
+ ref logic s_tms,
+ ref logic s_trstn,
+ ref logic s_tdi
+ );
+ s_trstn = 1'b1;
+ s_tdi = 1'b0;
+ // from IDLE to SHIFT_IR : tms sequence 1100
+ s_tms = 1'b1;
+ jtag_clock(2, s_tck);
+ s_tms = 1'b0;
+ jtag_clock(2, s_tck);
+ endtask
+
+ task jtag_goto_SHIFT_DR(
+ ref logic s_tck,
+ ref logic s_tms,
+ ref logic s_trstn,
+ ref logic s_tdi
+ );
+ s_trstn = 1'b1;
+ s_tdi = 1'b0;
+ // from IDLE to SHIFT_IR : tms sequence 100
+ s_tms = 1'b1;
+ jtag_clock(1, s_tck);
+ s_tms = 1'b0;
+ jtag_clock(2, s_tck);
+ endtask
+
+ task jtag_goto_UPDATE_DR_FROM_SHIFT_DR(
+ ref logic s_tck,
+ ref logic s_tms,
+ ref logic s_trstn,
+ ref logic s_tdi
+ );
+ //$display("I am at jtag_goto_UPDATE_DR_FROM_SHIFT_DR (%t)",$realtime);
+ s_trstn = 1'b1;
+ s_tdi = 1'b1;
+ // from SHIFT DR to UPDATE DR : tms sequence 11
+ s_tms = 1'b1;
+ jtag_clock(1, s_tck);
+ // back to Idle : tms sequence 0
+ s_tms = 1'b0;
+ //wait a bit
+ jtag_clock(50, s_tck);
+ endtask
+
+ task jtag_goto_CAPTURE_DR_FROM_UPDATE_DR_GETDATA(
+ output logic [DMI_SIZE-1:0] dataout,
+ ref logic s_tck,
+ ref logic s_tms,
+ ref logic s_trstn,
+ ref logic s_tdi,
+ ref logic s_tdo
+ );
+ //$display("I am at jtag_goto_CAPTURE_DR_FROM_UPDATE_DR_GETDATA (%t)",$realtime);
+ s_trstn = 1'b1;
+ s_tdi = 1'b1;
+ // from UPDATE DR to CAPTURE DR : tms sequence 10
+ s_tms = 1'b1;
+ jtag_clock(1, s_tck);
+ s_tms = 1'b0;
+ jtag_clock(1, s_tck);
+ //back to Idle: tms sequence 110
+ s_tms = 1'b1;
+ jtag_clock(2, s_tck);
+ s_tms = 1'b0;
+ jtag_clock(1, s_tck);
+ // go to SHIFT DR: tms sequence 100
+ s_tms = 1'b1;
+ jtag_clock(1, s_tck);
+ s_tms = 1'b0;
+ jtag_clock(2, s_tck);
+ s_tms = 1'b0;
+ for(int i=0; i<DMI_SIZE; i=i+1) begin
+ if (i == (DMI_SIZE-1))
+ s_tms = 1'b1;
+ s_tdi = 1'b0;
+ jtag_clock(1, s_tck);
+ dataout[i] = s_tdo;
+ end
+
+ endtask
+
+ task jtag_goto_CAPTURE_DR_FROM_SHIFT_DR_GETDATA(
+ output logic [DMI_SIZE-1:0] dataout,
+ ref logic s_tck,
+ ref logic s_tms,
+ ref logic s_trstn,
+ ref logic s_tdi,
+ ref logic s_tdo
+ );
+ //$display("I am at jtag_goto_CAPTURE_DR_FROM_SHIFT_DR_GETDATA (%t)",$realtime);
+ s_trstn = 1'b1;
+ s_tdi = 1'b1;
+ // from UPDATE DR to CAPTURE DR : tms sequence 110
+ s_tms = 1'b1;
+ jtag_clock(2, s_tck);
+ s_tms = 1'b0;
+ jtag_clock(1, s_tck);
+ // go to SHIFT DR
+ s_tms = 1'b0;
+ jtag_clock(1, s_tck);
+ s_tms = 1'b0;
+ for(int i=0; i<DMI_SIZE; i=i+1) begin
+ if (i == (DMI_SIZE-1))
+ s_tms = 1'b1;
+ s_tdi = 1'b0;
+ jtag_clock(1, s_tck);
+ dataout[i] = s_tdo;
+ end
+
+ endtask
+
+ task jtag_shift_SHIFT_IR(
+ ref logic s_tck,
+ ref logic s_tms,
+ ref logic s_trstn,
+ ref logic s_tdi
+ );
+ s_trstn = 1'b1;
+ s_tms = 1'b0;
+ for(int i=0; i<JTAG_SOC_INSTR_WIDTH + JTAG_CLUSTER_INSTR_WIDTH; i=i+1) begin
+ if (i==(JTAG_SOC_INSTR_WIDTH+JTAG_CLUSTER_INSTR_WIDTH-1))
+ s_tms = 1'b1;
+ s_tdi = instr[i];
+ jtag_clock(1, s_tck);
+ end
+ endtask
+
+ task jtag_shift_NBITS_SHIFT_DR (
+ input int unsigned numbits,
+ input logic[size-1:0] datain,
+ output logic[size-1:0] dataout,
+ ref logic s_tck,
+ ref logic s_tms,
+ ref logic s_trstn,
+ ref logic s_tdi,
+ ref logic s_tdo
+ );
+ s_trstn = 1'b1;
+ s_tms = 1'b0;
+ for(int i=0; i<numbits; i=i+1) begin
+ if (i == (numbits-1))
+ s_tms = 1'b1;
+ s_tdi = datain[i];
+ jtag_clock(1, s_tck);
+ dataout[i] = s_tdo;
+ end
+ endtask
+
+ task shift_nbits_noex(
+ input int unsigned numbits,
+ input logic[size-1:0] datain,
+ output logic[size-1:0] dataout,
+ ref logic s_tck,
+ ref logic s_tms,
+ ref logic s_trstn,
+ ref logic s_tdi,
+ ref logic s_tdo
+ );
+ s_trstn = 1'b1;
+ s_tms = 1'b0;
+ for(int i=0; i<numbits; i=i+1) begin
+ s_tdi = datain[i];
+ jtag_clock(1, s_tck);
+ dataout[i] = s_tdo;
+ end
+ endtask
+
+ task start_shift(
+ ref logic s_tck,
+ ref logic s_tms,
+ ref logic s_trstn,
+ ref logic s_tdi
+ );
+ this.jtag_goto_SHIFT_DR(s_tck, s_tms, s_trstn, s_tdi);
+ endtask
+
+ task shift_nbits(
+ input int unsigned numbits,
+ input logic[size-1:0] datain,
+ output logic[size-1:0] dataout,
+ ref logic s_tck,
+ ref logic s_tms,
+ ref logic s_trstn,
+ ref logic s_tdi,
+ ref logic s_tdo
+ );
+ this.jtag_shift_NBITS_SHIFT_DR(numbits, datain, dataout, s_tck, s_tms, s_trstn, s_tdi, s_tdo);
+ endtask
+
+ task setIR(
+ ref logic s_tck,
+ ref logic s_tms,
+ ref logic s_trstn,
+ ref logic s_tdi
+ );
+ this.jtag_goto_SHIFT_IR(s_tck, s_tms, s_trstn, s_tdi);
+ this.jtag_shift_SHIFT_IR(s_tck, s_tms, s_trstn, s_tdi);
+ this.idle(s_tck, s_tms, s_trstn, s_tdi);
+ endtask
+
+ task shift(
+ input logic[size-1:0] datain,
+ output logic[size-1:0] dataout,
+ ref logic s_tck,
+ ref logic s_tms,
+ ref logic s_trstn,
+ ref logic s_tdi,
+ ref logic s_tdo
+ );
+ this.jtag_goto_SHIFT_DR(s_tck, s_tms, s_trstn, s_tdi);
+ this.jtag_shift_NBITS_SHIFT_DR(size, datain, dataout, s_tck, s_tms, s_trstn, s_tdi, s_tdo);
+ this.idle(s_tck, s_tms, s_trstn, s_tdi);
+ endtask
+
+ endclass
+
+ task automatic jtag_get_idcode(
+ ref logic s_tck,
+ ref logic s_tms,
+ ref logic s_trstn,
+ ref logic s_tdi,
+ ref logic s_tdo
+ );
+ automatic JTAG_reg #(.size(JTAG_IDCODE_WIDTH), .instr({JTAG_SOC_IDCODE, JTAG_SOC_BYPASS})) jtag_idcode = new;
+ //as we have two tap in Daisy Chain, always one bit more for the bypass --> NOT in pulpino
+ logic [31:0] s_idcode;
+ jtag_idcode.setIR(s_tck, s_tms, s_trstn, s_tdi);
+ jtag_idcode.shift('0, s_idcode, s_tck, s_tms, s_trstn, s_tdi, s_tdo);
+ $display("[JTAG] Tap ID: %h (%t)",s_idcode[31:0], $realtime);
+ if(s_idcode[31:0] !== 32'h249511C3) begin
+ $display("[JTAG] Tap ID Test FAILED (%t)", $realtime);
+ end else begin
+ $display("[JTAG] Tap ID Test PASSED (%t)", $realtime);
+ end
+ endtask
+
+ task automatic jtag_bypass_test(
+ ref logic s_tck,
+ ref logic s_tms,
+ ref logic s_trstn,
+ ref logic s_tdi,
+ ref logic s_tdo
+ );
+ automatic JTAG_reg #(.size(256), .instr({JTAG_SOC_BYPASS, JTAG_SOC_BYPASS})) jtag_bypass = new;
+ logic [255:0] result_data;
+ automatic logic [255:0] test_data = { 32'hDEADBEEF, 32'h0BADF00D, 32'h01234567, 32'h89ABCDEF,
+ 32'hAAAABBBB, 32'hCCCCDDDD, 32'hEEEEFFFF, 32'h00001111};
+ jtag_bypass.setIR(s_tck, s_tms, s_trstn, s_tdi);
+ jtag_bypass.shift(test_data, result_data, s_tck, s_tms, s_trstn, s_tdi, s_tdo);
+ if (test_data[254:0] === result_data[255:1])
+ //if (test_data[31:0] === result_data[32:1])
+ $display("[JTAG] Bypass Test Passed (%t)", $realtime);
+ else
+ begin
+ $display("[JTAG] Bypass Test Failed");
+ $display("[JTAG] LSB WORD TEST = %h (%t)",test_data[31:0], $realtime);
+ $display("[JTAG] LSB WORD RES = %h (%t)",result_data[32:1], $realtime);
+ end
+ endtask
+
+ class test_mode_if_t;
+
+ task init(
+ ref logic s_tck,
+ ref logic s_tms,
+ ref logic s_trstn,
+ ref logic s_tdi
+ );
+ JTAG_reg #(.size(256), .instr({JTAG_SOC_BYPASS, JTAG_SOC_CONFREG})) jtag_soc_dbg = new;
+ jtag_soc_dbg.setIR(s_tck, s_tms, s_trstn, s_tdi);
+ $display("[test_mode_if] %t - Init", $realtime);
+ endtask
+
+ task set_confreg(
+ input logic [8:0] confreg,
+ output logic [8:0] dataout,
+ ref logic s_tck,
+ ref logic s_tms,
+ ref logic s_trstn,
+ ref logic s_tdi,
+ ref logic s_tdo
+ );
+ logic [8+1:0] confreg_int, dataout_int; //extra bit for bypass
+ JTAG_reg #(.size(256), .instr({JTAG_SOC_BYPASS, JTAG_SOC_CONFREG})) jtag_soc_dbg = new;
+
+ confreg_int = {1'b0, confreg};
+
+ jtag_soc_dbg.start_shift(s_tck, s_tms, s_trstn, s_tdi);
+ jtag_soc_dbg.shift_nbits(9+1, confreg_int, dataout_int, s_tck, s_tms, s_trstn, s_tdi, s_tdo);
+ jtag_soc_dbg.idle(s_tck, s_tms, s_trstn, s_tdi);
+ dataout = dataout_int[8:0];
+ $display("[test_mode_if] %t - Setting confreg to value %X.", $realtime, confreg);
+ endtask
+
+ task get_confreg(
+ input logic [8:0] confreg,
+ output bit [8:0] rec,
+ ref logic s_tck,
+ ref logic s_tms,
+ ref logic s_trstn,
+ ref logic s_tdi,
+ ref logic s_tdo
+ );
+ logic [8+1:0] dataout; //extra bit for bypass
+ JTAG_reg #(.size(256), .instr({JTAG_SOC_BYPASS, JTAG_SOC_CONFREG})) jtag_soc_dbg = new;
+ jtag_soc_dbg.start_shift(s_tck, s_tms, s_trstn, s_tdi);
+ jtag_soc_dbg.shift_nbits(9+1, confreg, dataout, s_tck, s_tms, s_trstn, s_tdi, s_tdo);
+ jtag_soc_dbg.idle(s_tck, s_tms, s_trstn, s_tdi);
+ rec = dataout [8:0];
+ // `DEBUG_MANAGER_INST.printf(STDOUT, 0, $sformatf("%s[TEST_MODE_IF] %s%t - %sGet confreg value = %X%s\n", `ESC_BLUE_BOLD, `ESC_WHITE, $realtime, `ESC_MAGENTA, rec, `ESC_DEFAULT));
+ endtask
+
+ endclass
+
+ class debug_mode_if_t;
+
+
+ task init_dmi_access(
+ ref logic s_tck,
+ ref logic s_tms,
+ ref logic s_trstn,
+ ref logic s_tdi
+ );
+ JTAG_reg #(.size(32+1), .instr({JTAG_SOC_DMIACCESS, JTAG_SOC_BYPASS})) jtag_soc_dbg = new;
+ jtag_soc_dbg.setIR(s_tck, s_tms, s_trstn, s_tdi);
+
+ endtask
+
+ task init_dtmcs(
+ ref logic s_tck,
+ ref logic s_tms,
+ ref logic s_trstn,
+ ref logic s_tdi
+ );
+
+ JTAG_reg #(.size(32+1), .instr({JTAG_SOC_DTMCSR, JTAG_SOC_BYPASS})) jtag_soc_dbg = new;
+ jtag_soc_dbg.setIR(s_tck, s_tms, s_trstn, s_tdi);
+
+ endtask
+
+
+ task dump_dm_info(
+ ref logic s_tck,
+ ref logic s_tms,
+ ref logic s_trstn,
+ ref logic s_tdi,
+ ref logic s_tdo
+ );
+
+ typedef struct packed {
+ logic [31:18] zero1;
+ logic dmihardreset;
+ logic dmireset;
+ logic zero0;
+ logic [14:12] idle;
+ logic [11:10] dmistat;
+ logic [9:4] abits;
+ logic [3:0] version;
+ } dtmcs_t;
+
+ dm::dmstatus_t dmstatus;
+ dtmcs_t dtmcs;
+
+ $display("[TB] %t - Init", $realtime);
+ this.init_dtmcs(s_tck, s_tms, s_trstn, s_tdi);
+
+ this.read_dtmcs(dtmcs, s_tck, s_tms, s_trstn, s_tdi, s_tdo);
+
+ $display("[TB] %t - Debug Module dtmcs %x: \n\
+ dmihardreset %x \n\
+ dmireset %x \n\
+ idle %x \n\
+ dmistat %x \n\
+ abits %x \n\
+ version %x \n",
+ $realtime, dtmcs, dtmcs.dmihardreset, dtmcs.dmireset, dtmcs.idle,
+ dtmcs.dmistat, dtmcs.abits, dtmcs.version);
+
+ this.init_dmi_access(s_tck, s_tms, s_trstn, s_tdi);
+
+ this.read_debug_reg(dm::DMStatus, dmstatus,
+ s_tck, s_tms, s_trstn, s_tdi, s_tdo);
+
+ $display("[TB] %t - Debug Module Debug Version: \n\
+ impebreak %x\n\
+ allhavereset %x\n\
+ anyhavereset %x\n\
+ allrunning %x\n\
+ anyrunning %x\n\
+ allhalted %x\n\
+ anyhalted %x\n\
+ version %x\n\
+ ", $realtime, dmstatus.impebreak, dmstatus.allhavereset, dmstatus.anyhavereset,
+ dmstatus.allrunning, dmstatus.anyrunning, dmstatus.allhalted, dmstatus.anyhalted,
+ dmstatus.version);
+
+ endtask
+
+
+ task set_haltreq(
+ input logic haltreq,
+ ref logic s_tck,
+ ref logic s_tms,
+ ref logic s_trstn,
+ ref logic s_tdi,
+ ref logic s_tdo
+ );
+
+ logic [1:0] dm_op;
+ logic [6:0] dm_addr;
+ logic [31:0] dm_data;
+ dm::dmcontrol_t dmcontrol;
+
+ // TODO: we probably don't need to rescan IR
+ this.init_dmi_access(s_tck, s_tms, s_trstn, s_tdi);
+ this.read_debug_reg(dm::DMControl, dmcontrol,
+ s_tck, s_tms, s_trstn, s_tdi, s_tdo);
+
+ dmcontrol.haltreq = haltreq;
+
+ this.write_debug_reg(dm::DMControl, dmcontrol,
+ s_tck, s_tms, s_trstn, s_tdi, s_tdo);
+
+
+ //wait the core to be stalled
+ dm_data = '0;
+ while(dm_data[8] == 1'b0) begin //anyhalted
+ this.set_dmi(
+ 2'b01, //read
+ 7'h11, //dmstatus
+ 32'h0, //whatever
+ {dm_addr, dm_data, dm_op},
+ s_tck,
+ s_tms,
+ s_trstn,
+ s_tdi,
+ s_tdo
+ );
+ end
+
+ endtask
+
+ task set_resumereq(
+ input logic resumereq,
+ ref logic s_tck,
+ ref logic s_tms,
+ ref logic s_trstn,
+ ref logic s_tdi,
+ ref logic s_tdo
+ );
+
+ logic [1:0] dm_op;
+ logic [6:0] dm_addr;
+ logic [31:0] dm_data;
+ dm::dmcontrol_t dmcontrol;
+
+ // TODO: we probably don't need to rescan IR
+ this.init_dmi_access(s_tck, s_tms, s_trstn, s_tdi);
+ this.read_debug_reg(dm::DMControl, dmcontrol,
+ s_tck, s_tms, s_trstn, s_tdi, s_tdo);
+
+ dmcontrol.resumereq = resumereq;
+
+ this.write_debug_reg(dm::DMControl, dmcontrol,
+ s_tck, s_tms, s_trstn, s_tdi, s_tdo);
+
+ endtask
+
+
+ task halt_harts(
+ ref logic s_tck,
+ ref logic s_tms,
+ ref logic s_trstn,
+ ref logic s_tdi,
+ ref logic s_tdo
+ );
+
+ dm::dmcontrol_t dmcontrol;
+ dm::dmstatus_t dmstatus;
+
+ // stop the hart by setting haltreq
+ this.read_debug_reg(dm::DMControl, dmcontrol,
+ s_tck, s_tms, s_trstn, s_tdi, s_tdo);
+
+ dmcontrol.haltreq = 1'b1;
+
+ this.write_debug_reg(dm::DMControl, dmcontrol,
+ s_tck, s_tms, s_trstn, s_tdi, s_tdo);
+
+ // wait until hart is halted
+ do begin
+ this.read_debug_reg(dm::DMStatus, dmstatus,
+ s_tck, s_tms, s_trstn, s_tdi, s_tdo);
+
+ end while(dmstatus.allhalted != 1'b1);
+
+ // clear haltreq
+ dmcontrol.haltreq = 1'b0;
+ this.write_debug_reg(dm::DMControl, dmcontrol,
+ s_tck, s_tms, s_trstn, s_tdi, s_tdo);
+
+ endtask
+
+
+ task resume_harts(
+ ref logic s_tck,
+ ref logic s_tms,
+ ref logic s_trstn,
+ ref logic s_tdi,
+ ref logic s_tdo
+ );
+
+ dm::dmcontrol_t dmcontrol;
+ dm::dmstatus_t dmstatus;
+
+ // resume the hart by setting resumereq
+ this.read_debug_reg(dm::DMControl, dmcontrol,
+ s_tck, s_tms, s_trstn, s_tdi, s_tdo);
+
+ dmcontrol.resumereq = 1'b1;
+
+ this.write_debug_reg(dm::DMControl, dmcontrol,
+ s_tck, s_tms, s_trstn, s_tdi, s_tdo);
+
+ // wait until hart resumed
+ do begin
+ this.read_debug_reg(dm::DMStatus, dmstatus,
+ s_tck, s_tms, s_trstn, s_tdi, s_tdo);
+
+ end while(dmstatus.allresumeack != 1'b1);
+
+ // clear resumereq
+ dmcontrol.resumereq = 1'b0;
+ this.write_debug_reg(dm::DMControl, dmcontrol,
+ s_tck, s_tms, s_trstn, s_tdi, s_tdo);
+
+ endtask
+
+ task block_until_any_halt(
+ ref logic s_tck,
+ ref logic s_tms,
+ ref logic s_trstn,
+ ref logic s_tdi,
+ ref logic s_tdo
+ );
+
+ dm::dmstatus_t dmstatus;
+
+ do begin
+ this.read_debug_reg(dm::DMStatus, dmstatus,
+ s_tck, s_tms, s_trstn, s_tdi, s_tdo);
+ end while(dmstatus.anyhalted == 1'b0);
+
+ endtask
+
+ task writeArg (
+ input logic arg,
+ input logic [31:0] val,
+ ref logic s_tck,
+ ref logic s_tms,
+ ref logic s_trstn,
+ ref logic s_tdi,
+ ref logic s_tdo
+ );
+
+
+ logic [1:0] dm_op;
+ logic [6:0] dm_addr;
+ logic [31:0] dm_data;
+
+ dm_addr = arg ? 7'd8 : 7'd4;
+
+ this.set_dmi(
+ 2'b10, //write
+ dm_addr, //data0 or data1
+ val, //whatever
+ {dm_addr, dm_data, dm_op},
+ s_tck,
+ s_tms,
+ s_trstn,
+ s_tdi,
+ s_tdo
+ );
+ endtask
+
+ task writePrgramBuff (
+ input logic [2:0] arg,
+ input logic [31:0] val,
+ ref logic s_tck,
+ ref logic s_tms,
+ ref logic s_trstn,
+ ref logic s_tdi,
+ ref logic s_tdo
+ );
+
+
+ logic [1:0] dm_op;
+ logic [6:0] dm_addr;
+ logic [31:0] dm_data;
+
+ dm_addr = 7'h20 + arg;
+
+ this.set_dmi(
+ 2'b10, //write
+ dm_addr, //progbuffer_i
+ val, //whatever
+ {dm_addr, dm_data, dm_op},
+ s_tck,
+ s_tms,
+ s_trstn,
+ s_tdi,
+ s_tdo
+ );
+
+ endtask
+
+ // wait for abstract command to finish, no error checking
+ task wait_command (
+ input logic [31:0] command,
+ ref logic s_tck,
+ ref logic s_tms,
+ ref logic s_trstn,
+ ref logic s_tdi,
+ ref logic s_tdo
+ );
+
+ dm::abstractcs_t abstractcs;
+
+ // wait until we get a result
+ do begin
+ this.read_debug_reg(dm::AbstractCS, abstractcs,
+ s_tck, s_tms, s_trstn, s_tdi, s_tdo);
+ end while(abstractcs.busy == 1'b1);
+
+ assert(abstractcs.cmderr == dm::CmdErrNone)
+ else $error("Access to register %x failed with error %x",
+ command[15:0],
+ abstractcs.cmderr);
+
+ // if we got an error we need to clear it for the following accesses
+ if (abstractcs.cmderr != dm::CmdErrNone) begin
+ abstractcs = '{default:0, cmderr:abstractcs.cmderr};
+ this.write_debug_reg(dm::AbstractCS, abstractcs,
+ s_tck, s_tms, s_trstn, s_tdi, s_tdo);
+
+
+ this.read_debug_reg(dm::AbstractCS, abstractcs,
+ s_tck, s_tms, s_trstn, s_tdi, s_tdo);
+
+ assert(abstractcs.cmderr == dm::CmdErrNone)
+ else begin
+ $error("cmderr bit didn't get cleared");
+ end
+ end
+
+ endtask
+
+
+ task set_command (
+ input logic [31:0] command,
+ ref logic s_tck,
+ ref logic s_tms,
+ ref logic s_trstn,
+ ref logic s_tdi,
+ ref logic s_tdo
+ );
+
+
+ logic [1:0] dm_op;
+ logic [6:0] dm_addr;
+ logic [31:0] dm_data;
+
+ this.set_dmi(
+ 2'b10, //write
+ 7'h17, //command
+ command, //whatever
+ {dm_addr, dm_data, dm_op},
+ s_tck,
+ s_tms,
+ s_trstn,
+ s_tdi,
+ s_tdo
+ );
+
+ this.wait_command(
+ command,
+ s_tck,
+ s_tms,
+ s_trstn,
+ s_tdi,
+ s_tdo
+ );
+
+ endtask
+
+ task read_dtmcs(
+ output logic [31:0] dtmcs,
+ ref logic s_tck,
+ ref logic s_tms,
+ ref logic s_trstn,
+ ref logic s_tdi,
+ ref logic s_tdo
+ );
+ logic [31+1:0] dataout;
+ JTAG_reg #(.size(32+1), .instr({JTAG_SOC_DTMCSR, JTAG_SOC_BYPASS})) jtag_soc_dbg = new;
+ jtag_soc_dbg.start_shift(s_tck, s_tms, s_trstn, s_tdi);
+ jtag_soc_dbg.shift_nbits(32+1, '0, dataout, s_tck, s_tms, s_trstn, s_tdi, s_tdo);
+ jtag_soc_dbg.idle(s_tck, s_tms, s_trstn, s_tdi);
+ dtmcs = dataout[32:1];
+ endtask
+
+ task write_dtmcs(
+ input logic [31:0] dtmcs,
+ ref logic s_tck,
+ ref logic s_tms,
+ ref logic s_trstn,
+ ref logic s_tdi,
+ ref logic s_tdo
+ );
+ logic [31+1:0] dataout;
+ JTAG_reg #(.size(32+1), .instr({JTAG_SOC_DTMCSR, JTAG_SOC_BYPASS})) jtag_soc_dbg = new;
+ jtag_soc_dbg.start_shift(s_tck, s_tms, s_trstn, s_tdi);
+ jtag_soc_dbg.shift_nbits(32+1, {dtmcs, 1'b0}, dataout, s_tck, s_tms, s_trstn, s_tdi, s_tdo);
+ jtag_soc_dbg.idle(s_tck, s_tms, s_trstn, s_tdi);
+
+ endtask
+
+
+ task test_read_sbcs(
+ ref logic s_tck,
+ ref logic s_tms,
+ ref logic s_trstn,
+ ref logic s_tdi,
+ ref logic s_tdo
+ );
+
+ dm::sbcs_t sbcs;
+
+ this.read_debug_reg(dm::SBCS, sbcs,
+ s_tck, s_tms, s_trstn, s_tdi, s_tdo);
+
+
+ $display("[TB] %t - Debug Module System Bus Access Control and Status: \n\
+ sbbusy %x\n\
+ sbreadonaddr %x\n\
+ sbaccess %x\n\
+ sbautoincrement %x\n\
+ sbreadondata %x\n\
+ sberror %x\n\
+ sbasize %x\n\
+ sbaccess32 %x\
+ ", $realtime, sbcs.sbbusy, sbcs.sbreadonaddr, sbcs.sbaccess, sbcs.sbautoincrement,
+ sbcs.sbreadondata, sbcs.sberror, sbcs.sbasize, sbcs.sbaccess32);
+
+ assert(sbcs.sbbusy == 1'b0)
+ else $error("sb is busy even though we are idling");
+ assert(sbcs.sberror == 2'b0)
+ else $error("sb is in some error state");
+ assert(sbcs.sbasize == 6'd32)
+ else $error("sbasize is not XLEN=32");
+ assert(sbcs.sbaccess32 == 1'b1)
+ else $error("sbaccess32 is should be supported");
+ assert(sbcs.sbaccess16 == 1'b0)
+ else $error("sbaccess16 is signaled as supported");
+ assert(sbcs.sbaccess8 == 1'b0)
+ else $error("sbaccess8 is signaled as supported");
+
+ endtask
+
+ task test_read_abstractcs(
+ ref logic s_tck,
+ ref logic s_tms,
+ ref logic s_trstn,
+ ref logic s_tdi,
+ ref logic s_tdo
+ );
+
+ dm::abstractcs_t abstractcs;
+
+ read_debug_reg(dm::AbstractCS, abstractcs, s_tck, s_tms, s_trstn, s_tdi, s_tdo);
+ $display("[TB] %t - Abstractcs is %x (progbufsize %x, busy %x, cmderr %x, datacount %x)",
+ $realtime, abstractcs, abstractcs.progbufsize, abstractcs.busy,
+ abstractcs.cmderr, abstractcs.datacount);
+
+ assert(abstractcs.progbufsize == 5'h8)
+ else $error("progbufsize is not 8 (might be ok)");
+ assert(abstractcs.datacount == 4'h2)
+ else $error("datacount is not 2 (might be ok)");
+
+ endtask
+
+ task set_dmi(
+ input logic [1:0] op_i,
+ input logic [6:0] address_i,
+ input logic [31:0] data_i,
+ output logic [DMI_SIZE-1:0] data_o,
+ ref logic s_tck,
+ ref logic s_tms,
+ ref logic s_trstn,
+ ref logic s_tdi,
+ ref logic s_tdo
+ );
+ logic [DMI_SIZE-1:0] buffer;
+ logic [DMI_SIZE-1:0] buffer_riscv;
+ JTAG_reg #(.size(DMI_SIZE), .instr({JTAG_SOC_DMIACCESS, JTAG_SOC_BYPASS})) jtag_soc_dbg = new;
+ jtag_soc_dbg.start_shift(s_tck, s_tms, s_trstn, s_tdi);
+ jtag_soc_dbg.shift_nbits(DMI_SIZE, {address_i,data_i,op_i}, buffer, s_tck, s_tms, s_trstn, s_tdi, s_tdo);
+ jtag_soc_dbg.jtag_goto_UPDATE_DR_FROM_SHIFT_DR(s_tck, s_tms, s_trstn, s_tdi);
+ jtag_soc_dbg.jtag_goto_CAPTURE_DR_FROM_UPDATE_DR_GETDATA(buffer, s_tck, s_tms, s_trstn, s_tdi,s_tdo);
+ buffer_riscv = buffer[DMI_SIZE-1:0];
+ //while(buffer_riscv[1:0] == 2'b11) begin
+ // //$display("buffer is set_dmi is %x (OP %x address %x datain %x) (%t)",buffer, buffer[1:0], buffer[8:2], buffer[DMI_SIZE-1:9], $realtime);
+ // jtag_soc_dbg.jtag_goto_CAPTURE_DR_FROM_SHIFT_DR_GETDATA(buffer, s_tck, s_tms, s_trstn, s_tdi,s_tdo);
+ // buffer_riscv = buffer[DMI_SIZE:1];
+ //end
+ //$display("dataout is set_dmi is %x (OP %x address %x datain %x) (%t)",buffer, buffer[1:0], buffer[40:34], buffer[33:2], $realtime);
+ data_o[1:0] = buffer_riscv[1:0];
+ data_o[40:34] = buffer_riscv[40:34];
+ data_o[33:2] = buffer_riscv[33:2];
+ jtag_soc_dbg.idle(s_tck, s_tms, s_trstn, s_tdi);
+
+ endtask
+
+ task set_dmi_ini(
+ input logic [1:0] op_i,
+ input logic [6:0] address_i,
+ input logic [31:0] data_i,
+ output logic [DMI_SIZE-1:0] data_o,
+ ref logic s_tck,
+ ref logic s_tms,
+ ref logic s_trstn,
+ ref logic s_tdi,
+ ref logic s_tdo
+ );
+ logic [DMI_SIZE-1+1:0] buffer;
+ logic [DMI_SIZE-1:0] buffer_riscv;
+ JTAG_reg #(.size(DMI_SIZE+1), .instr({JTAG_SOC_DMIACCESS, JTAG_SOC_BYPASS})) jtag_soc_dbg = new;
+ jtag_soc_dbg.start_shift(s_tck, s_tms, s_trstn, s_tdi);
+ jtag_soc_dbg.shift_nbits(DMI_SIZE+1, {address_i,data_i,op_i, 1'b0}, buffer, s_tck, s_tms, s_trstn, s_tdi, s_tdo);
+ jtag_soc_dbg.jtag_goto_UPDATE_DR_FROM_SHIFT_DR(s_tck, s_tms, s_trstn, s_tdi);
+ jtag_soc_dbg.jtag_goto_CAPTURE_DR_FROM_UPDATE_DR_GETDATA(buffer, s_tck, s_tms, s_trstn, s_tdi,s_tdo);
+ buffer_riscv = buffer[DMI_SIZE:1];
+ //while(buffer_riscv[1:0] == 2'b11) begin
+ // //$display("buffer is set_dmi is %x (OP %x address %x datain %x) (%t)",buffer, buffer[1:0], buffer[8:2], buffer[DMI_SIZE-1:9], $realtime);
+ // jtag_soc_dbg.jtag_goto_CAPTURE_DR_FROM_SHIFT_DR_GETDATA(buffer, s_tck, s_tms, s_trstn, s_tdi,s_tdo);
+ // buffer_riscv = buffer[DMI_SIZE:1];
+ //end
+ //$display("dataout is set_dmi is %x (OP %x address %x datain %x) (%t)",buffer, buffer[1:0], buffer[40:34], buffer[33:2], $realtime);
+ data_o[1:0] = buffer_riscv[1:0];
+ data_o[40:34] = buffer_riscv[40:34];
+ data_o[33:2] = buffer_riscv[33:2];
+ jtag_soc_dbg.idle(s_tck, s_tms, s_trstn, s_tdi);
+
+ endtask
+
+ task dmi_reset(
+ ref logic s_tck,
+ ref logic s_tms,
+ ref logic s_trstn,
+ ref logic s_tdi,
+ ref logic s_tdo
+ );
+ logic [31:0] buffer;
+ init_dtmcs(s_tck, s_tms, s_trstn, s_tdi);
+
+ this.read_dtmcs(
+ buffer,
+ s_tck,
+ s_tms,
+ s_trstn,
+ s_tdi,
+ s_tdo
+ );
+ buffer[16] = 1'b1;
+ this.write_dtmcs(
+ buffer,
+ s_tck,
+ s_tms,
+ s_trstn,
+ s_tdi,
+ s_tdo
+ );
+ buffer[16] = 1'b0;
+ this.write_dtmcs(
+ buffer,
+ s_tck,
+ s_tms,
+ s_trstn,
+ s_tdi,
+ s_tdo
+ );
+ endtask
+
+ task set_dmactive(
+ input logic dmactive,
+ ref logic s_tck,
+ ref logic s_tms,
+ ref logic s_trstn,
+ ref logic s_tdi,
+ ref logic s_tdo
+ );
+
+ logic [1:0] dm_op;
+ logic [31:0] dm_data;
+ logic [6:0] dm_addr;
+
+ this.set_dmi(
+ 2'b10, //Write
+ 7'h10, //DMControl
+ {1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 10'b0, 10'b0, 2'b0, 1'b0, 1'b0, 1'b0, dmactive},
+ {dm_addr, dm_data, dm_op},
+ s_tck,
+ s_tms,
+ s_trstn,
+ s_tdi,
+ s_tdo
+ );
+
+ endtask
+
+ task set_hartsel(
+ input logic [19:0] hartsel,
+ ref logic s_tck,
+ ref logic s_tms,
+ ref logic s_trstn,
+ ref logic s_tdi,
+ ref logic s_tdo
+ );
+
+ dm::dmcontrol_t dmcontrol;
+
+ this.read_debug_reg(dm::DMControl, dmcontrol,
+ s_tck, s_tms, s_trstn, s_tdi, s_tdo);
+
+ dmcontrol.hartsello = hartsel[9:0];
+ dmcontrol.hartselhi = hartsel[19:10];
+
+ this.write_debug_reg(dm::DMControl, dmcontrol,
+ s_tck, s_tms, s_trstn, s_tdi, s_tdo);
+
+ endtask
+
+
+ task set_sbreadonaddr(
+ input logic sbreadonaddr,
+ ref logic s_tck,
+ ref logic s_tms,
+ ref logic s_trstn,
+ ref logic s_tdi,
+ ref logic s_tdo
+ );
+
+ dm::sbcs_t sbcs;
+
+ this.read_debug_reg(dm::SBCS, sbcs,
+ s_tck, s_tms, s_trstn, s_tdi, s_tdo);
+
+ sbcs.sbreadonaddr = sbreadonaddr;
+
+ this.write_debug_reg(dm::SBCS, sbcs,
+ s_tck, s_tms, s_trstn, s_tdi, s_tdo);
+
+ endtask
+
+ task set_sbautoincrement(
+ input logic sbautoincrement,
+ ref logic s_tck,
+ ref logic s_tms,
+ ref logic s_trstn,
+ ref logic s_tdi,
+ ref logic s_tdo
+ );
+
+ dm::sbcs_t sbcs;
+
+ this.read_debug_reg(dm::SBCS, sbcs,
+ s_tck, s_tms, s_trstn, s_tdi, s_tdo);
+
+ sbcs.sbautoincrement = sbautoincrement;
+
+
+ this.write_debug_reg(dm::SBCS, sbcs,
+ s_tck, s_tms, s_trstn, s_tdi, s_tdo);
+
+ endtask
+
+ // access (read) debug module register according to riscv-debug p. 71
+ task read_debug_reg(
+ input logic [6:0] dmi_addr_i,
+ output logic [31:0] data_o,
+ ref logic s_tck,
+ ref logic s_tms,
+ ref logic s_trstn,
+ ref logic s_tdi,
+ ref logic s_tdo
+ );
+
+ logic [1:0] dmi_op;
+ logic [31:0] dmi_data;
+ logic [6:0] dmi_addr;
+
+ // TODO: widen wait between Capture-DR and Update-DR when failing
+ do begin
+ this.set_dmi(
+ 2'b01, //read
+ dmi_addr_i,
+ 32'h0, // don't care
+ {dmi_addr, dmi_data, dmi_op},
+ s_tck,
+ s_tms,
+ s_trstn,
+ s_tdi,
+ s_tdo
+ );
+ if (dmi_op == 2'h2) begin
+ $display("[TB] %t dmi previous operation failed, not handled", $realtime);
+ dmi_op = 2'h0; // TODO: for now we just force completion
+ end
+
+ if (dmi_op == 2'h3) begin
+ $display("[TB] %t retrying debug reg access", $realtime);
+ this.dmi_reset(s_tck,s_tms,s_trstn,s_tdi,s_tdo);
+ this.init_dmi_access(s_tck,s_tms,s_trstn,s_tdi);
+ end
+
+ end while (dmi_op != 2'h0);
+
+ data_o = dmi_data;
+ endtask
+
+ // access (write) debug module register according to riscv-debug p. 71
+ task write_debug_reg(
+ input logic [6:0] dmi_addr_i,
+ input logic [31:0] dmi_data_i,
+ ref logic s_tck,
+ ref logic s_tms,
+ ref logic s_trstn,
+ ref logic s_tdi,
+ ref logic s_tdo
+ );
+
+ logic [1:0] dmi_op;
+ logic [31:0] dmi_data;
+ logic [6:0] dmi_addr;
+ dm::dmcontrol_t dmcontrol;
+ int dmsane;
+
+ // According to riscv-debug p. 22 we are only allowed to write at most
+ // one bit to resumereq, hartreset, ackhavereset,setresethaltreq and
+ // clrresethaltreq. Others must be 0. This assert is for programming
+ // errors.
+ if(dmi_addr_i == dm::DMControl) begin
+ dmcontrol = dmi_data_i;
+ dmsane = dmcontrol.resumereq + dmcontrol.hartreset +
+ dmcontrol.ackhavereset + dmcontrol.setresethaltreq +
+ dmcontrol.clrresethaltreq;
+
+ assert (dmsane <= 1)
+ else
+ $error("bad write to dmcontrol: only one of the following may be set to 1: resumereq %b,",
+ dmcontrol.resumereq,
+ "hartreset %b,", dmcontrol.hartreset,
+ "ackhavereset %b,", dmcontrol.ackhavereset,
+ "setresethaltreq %b,", dmcontrol.setresethaltreq,
+ "clrresethaltreq %b", dmcontrol.clrresethaltreq);
+ end
+
+
+ // TODO: widen wait between Capture-DR and Update-DR when failing
+ do begin
+ this.set_dmi(
+ 2'b10, //write
+ dmi_addr_i,
+ dmi_data_i,
+ {dmi_addr, dmi_data, dmi_op},
+ s_tck,
+ s_tms,
+ s_trstn,
+ s_tdi,
+ s_tdo
+ );
+ if (dmi_op == 2'h2) begin
+ $display("[TB] %t dmi previous operation failed, not handled", $realtime);
+ dmi_op = 2'h0; // TODO: for now we just force completion
+ end
+
+ if (dmi_op == 2'h3) begin
+ $display("[TB] %t retrying debug reg access", $realtime);
+ this.dmi_reset(s_tck,s_tms,s_trstn,s_tdi,s_tdo);
+ this.init_dmi_access(s_tck,s_tms,s_trstn,s_tdi);
+ end
+
+ end while (dmi_op != 2'h0);
+
+ endtask
+
+
+ // access (read) csr, gpr by means of abstract command
+ task read_reg_abstract_cmd(
+ input logic [15:0] regno_i,
+ output logic [31:0] data_o,
+ ref logic s_tck,
+ ref logic s_tms,
+ ref logic s_trstn,
+ ref logic s_tdi,
+ ref logic s_tdo
+ );
+
+ logic [1:0] dmi_op;
+ logic [31:0] dmi_data;
+ logic [31:0] dmi_command;
+ logic [6:0] dmi_addr;
+
+ // load regno into data0
+ dmi_command = {8'h0, 1'b0, 3'd2, 1'b0, 1'b0, 1'b1, 1'b0, regno_i};
+ this.set_command(
+ dmi_command,
+ s_tck,
+ s_tms,
+ s_trstn,
+ s_tdi,
+ s_tdo
+ );
+
+ this.read_debug_reg(
+ dm::Data0,
+ dmi_data,
+ s_tck,
+ s_tms,
+ s_trstn,
+ s_tdi,
+ s_tdo
+ );
+
+ data_o = dmi_data;
+ endtask
+
+
+ // access (write) csr, gpr by means of abstract command
+ task write_reg_abstract_cmd(
+ input logic [15:0] regno_i,
+ input logic [31:0] data_i,
+ ref logic s_tck,
+ ref logic s_tms,
+ ref logic s_trstn,
+ ref logic s_tdi,
+ ref logic s_tdo
+ );
+
+ logic [1:0] dmi_op;
+ logic [31:0] dmi_data;
+ logic [31:0] dmi_command;
+ logic [6:0] dmi_addr;
+
+ //write data_i into data0
+ this.write_debug_reg(
+ dm::Data0,
+ data_i,
+ s_tck,
+ s_tms,
+ s_trstn,
+ s_tdi,
+ s_tdo
+ );
+
+ // write data0 to regno_i
+ dmi_command = {8'h0, 1'b0, 3'd2, 1'b0, 1'b0, 1'b1, 1'b1, regno_i};
+ this.set_command(
+ dmi_command,
+ s_tck,
+ s_tms,
+ s_trstn,
+ s_tdi,
+ s_tdo
+ );
+
+ endtask
+
+ // Before starting an abstract command, haltreq=resumereq=ackhavereset=0
+ // must be ensured, which is what this task asserts (see debug spec p.11).
+ // We use this to catch programming mistakes, not to test functionality
+ task assert_rdy_for_abstract_cmd(
+ ref logic s_tck,
+ ref logic s_tms,
+ ref logic s_trstn,
+ ref logic s_tdi,
+ ref logic s_tdo
+ );
+
+ dm::dmcontrol_t dmcontrol;
+ this.read_debug_reg(dm::DMControl, dmcontrol,
+ s_tck, s_tms, s_trstn, s_tdi, s_tdo);
+
+ assert(dmcontrol.haltreq == 1'b0)
+ else $error("haltreq is not zero");
+ assert(dmcontrol.resumereq == 1'b0)
+ else $error("resumereq is not zero");
+ assert(dmcontrol.ackhavereset == 1'b0)
+ else $error("ackhavereset is not zero");
+
+ endtask
+
+ // access csr, gpr by means of program buffer
+ task read_reg_prog_buff(
+ input logic [15:0] regno_i,
+ output logic [31:0] data_o,
+ ref logic s_tck,
+ ref logic s_tms,
+ ref logic s_trstn,
+ ref logic s_tdi,
+ ref logic s_tdo
+ );
+
+ logic [1:0] dmi_op;
+ logic [31:0] dmi_data;
+ logic [31:0] dmi_command;
+ logic [6:0] dmi_addr;
+
+ // load regno into data0
+ dmi_command = {8'h0, 1'b0, 3'd2, 1'b0, 1'b0, 1'b1, 1'b0, regno_i};
+ this.set_command(
+ dmi_command,
+ s_tck,
+ s_tms,
+ s_trstn,
+ s_tdi,
+ s_tdo
+ );
+
+ this.read_debug_reg(
+ dm::Data0,
+ dmi_data,
+ s_tck,
+ s_tms,
+ s_trstn,
+ s_tdi,
+ s_tdo
+ );
+
+ data_o = dmi_data;
+ endtask
+
+
+ task readMem(
+ input logic [31:0] addr_i,
+ output logic [31:0] data_o,
+ ref logic s_tck,
+ ref logic s_tms,
+ ref logic s_trstn,
+ ref logic s_tdi,
+ ref logic s_tdo
+ );
+
+ logic [1:0] dm_op;
+ logic [31:0] dm_data;
+ logic [6:0] dm_addr;
+
+ //NOTE sbreadonaddr must be 1
+
+ dm_op = '1; //error
+
+ while(dm_op == '1) begin
+ //Write the Address
+ this.set_dmi(
+ 2'b10, //write
+ 7'h39, //sbaddress0,
+ addr_i, //address
+ {dm_addr, dm_data, dm_op},
+ s_tck,
+ s_tms,
+ s_trstn,
+ s_tdi,
+ s_tdo
+ );
+ // $display("(sbaddress0) dm_addr %x dm_data %x dm_op %x at time %t", dm_addr, dm_data, dm_op, $realtime,);
+ if(dm_op == '1) begin
+ $display("dmi_reset at time %t",$realtime);
+ this.dmi_reset(s_tck,s_tms,s_trstn,s_tdi,s_tdo);
+ this.init_dmi_access(s_tck,s_tms,s_trstn,s_tdi);
+ end
+
+ end
+
+ dm_op = '1; //error
+
+ while(dm_op == '1) begin
+
+ this.set_dmi(
+ 2'b01, //read
+ 7'h3C, //sbdata0,
+ 32'h0, //whatever
+ {dm_addr, dm_data, dm_op},
+ s_tck,
+ s_tms,
+ s_trstn,
+ s_tdi,
+ s_tdo
+ );
+ // $display("(sbdata0) dm_addr %x dm_data %x dm_op %x at time %t", dm_addr, dm_data, dm_op, $realtime);
+ if(dm_op == '1) begin
+ $display("dmi_reset at time %t",$realtime);
+ this.dmi_reset(s_tck,s_tms,s_trstn,s_tdi,s_tdo);
+ this.init_dmi_access(s_tck,s_tms,s_trstn,s_tdi);
+ end
+
+ end
+ data_o = dm_data;
+
+
+ endtask
+
+ task writeMem(
+ input logic [31:0] addr_i,
+ input logic [31:0] data_i,
+ ref logic s_tck,
+ ref logic s_tms,
+ ref logic s_trstn,
+ ref logic s_tdi,
+ ref logic s_tdo
+ );
+
+ logic [1:0] dm_op;
+ logic [31:0] dm_data;
+ logic [6:0] dm_addr;
+
+ //NOTE sbreadonaddr must be 1
+
+ //Write the Address
+ this.set_dmi(
+ 2'b10, //write
+ 7'h39, //sbaddress0,
+ addr_i, //address
+ {dm_addr, dm_data, dm_op},
+ s_tck,
+ s_tms,
+ s_trstn,
+ s_tdi,
+ s_tdo
+ );
+
+ this.set_dmi(
+ 2'b10, //write
+ 7'h3C, //sbdata0,
+ data_i, //data_i
+ {dm_addr, dm_data, dm_op},
+ s_tck,
+ s_tms,
+ s_trstn,
+ s_tdi,
+ s_tdo
+ );
+
+ endtask
+
+
+ task load_L2(
+ input int num_stim,
+ ref logic [63:0] stimuli [100000:0],
+ ref logic s_tck,
+ ref logic s_tms,
+ ref logic s_trstn,
+ ref logic s_tdi,
+ ref logic s_tdo
+ );
+
+ logic [31:0] jtag_data;
+ logic [31:0] jtag_addr;
+ logic [31:0] spi_addr;
+ logic [31:0] spi_addr_old;
+ logic more_stim = 1;
+ logic [1:0] dm_op;
+ logic [31:0] dm_data;
+ logic [6:0] dm_addr;
+
+ spi_addr = stimuli[num_stim][63:32]; // assign address
+ jtag_data = stimuli[num_stim][31:0]; // assign data
+
+ this.set_sbreadonaddr(1'b0, s_tck, s_tms, s_trstn, s_tdi, s_tdo);
+ this.set_sbautoincrement(1'b0, s_tck, s_tms, s_trstn, s_tdi, s_tdo);
+
+ $display("[JTAG] Loading L2 with debug module jtag interface");
+
+ spi_addr_old = spi_addr - 32'h4;
+
+ while (more_stim) begin // loop until we have no more stimuli
+
+ jtag_addr = stimuli[num_stim][63:32];
+ for (int i=0;i<256;i=i+1) begin
+ spi_addr = stimuli[num_stim][63:32]; // assign address
+ jtag_data = stimuli[num_stim][31:0]; // assign data
+
+ if (spi_addr != (spi_addr_old + 32'h4))
+ begin
+ spi_addr_old = spi_addr - 32'h4;
+ break;
+ end
+ else begin
+ num_stim = num_stim + 1;
+ end
+ if (num_stim > $size(stimuli) || stimuli[num_stim]===64'bx ) begin // make sure we have more stimuli
+ more_stim = 0; // if not set variable to 0, will prevent additional stimuli to be applied
+ break;
+ end
+ spi_addr_old = spi_addr;
+
+ this.set_dmi(
+ 2'b10, //write
+ 7'h39, //sbaddress0,
+ spi_addr[31:0], //bootaddress
+ {dm_addr, dm_data, dm_op},
+ s_tck,
+ s_tms,
+ s_trstn,
+ s_tdi,
+ s_tdo
+ );
+
+ this.set_dmi(
+ 2'b10, //write
+ 7'h3C, //sbdata0,
+ jtag_data, //data
+ {dm_addr, dm_data, dm_op},
+ s_tck,
+ s_tms,
+ s_trstn,
+ s_tdi,
+ s_tdo
+ );
+
+ end
+ $display("[JTAG] Loading L2 - Written up to %x (%t)", spi_addr[31:0]+4, $realtime);
+
+ end
+ this.set_sbreadonaddr(1'b1, s_tck, s_tms, s_trstn, s_tdi, s_tdo);
+ this.set_sbautoincrement(1'b0, s_tck, s_tms, s_trstn, s_tdi, s_tdo);
+
+ endtask
+
+
+ task load_L2_ini(
+ input int num_stim,
+ ref logic [95:0] stimuli [100000:0],
+ ref logic s_tck,
+ ref logic s_tms,
+ ref logic s_trstn,
+ ref logic s_tdi,
+ ref logic s_tdo
+ );
+
+ logic [1:0][31:0] jtag_data;
+ logic [31:0] jtag_addr;
+ logic [31:0] spi_addr;
+ logic [31:0] spi_addr_old;
+ logic more_stim = 1;
+ logic [1:0] dm_op;
+ logic [31:0] dm_data;
+ logic [6:0] dm_addr;
+
+ spi_addr = stimuli[num_stim][95:64]; // assign address
+ jtag_data[0] = stimuli[num_stim][63:0]; // assign data
+
+ this.set_sbreadonaddr(1'b0, s_tck, s_tms, s_trstn, s_tdi, s_tdo);
+ this.set_sbautoincrement(1'b0, s_tck, s_tms, s_trstn, s_tdi, s_tdo);
+
+ $display("[JTAG] Loading L2 with debug module jtag interface");
+
+ spi_addr_old = spi_addr - 32'h8;
+
+ while (more_stim) begin // loop until we have no more stimuli
+
+ jtag_addr = stimuli[num_stim][95:64];
+ for (int i=0;i<256;i=i+2) begin
+ spi_addr = stimuli[num_stim][95:64]; // assign address
+ jtag_data[0] = stimuli[num_stim][31:0]; // assign data
+ jtag_data[1] = stimuli[num_stim][63:32]; // assign data
+
+ if (spi_addr != (spi_addr_old + 32'h8))
+ begin
+ spi_addr_old = spi_addr - 32'h8;
+ break;
+ end
+ else begin
+ num_stim = num_stim + 1;
+ end
+ if (num_stim > $size(stimuli) || stimuli[num_stim]===96'bx ) begin // make sure we have more stimuli
+ more_stim = 0; // if not set variable to 0, will prevent additional stimuli to be applied
+ break;
+ end
+ spi_addr_old = spi_addr;
+
+ this.set_dmi(
+ 2'b10, //write
+ 7'h39, //sbaddress0,
+ spi_addr[31:0], //bootaddress
+ {dm_addr, dm_data, dm_op},
+ s_tck,
+ s_tms,
+ s_trstn,
+ s_tdi,
+ s_tdo
+ );
+
+ this.set_dmi(
+ 2'b10, //write
+ 7'h3C, //sbdata0,
+ jtag_data[0], //data
+ {dm_addr, dm_data, dm_op},
+ s_tck,
+ s_tms,
+ s_trstn,
+ s_tdi,
+ s_tdo
+ );
+ //$display("[JTAG] Loading L2 - Written %x at %x (%t)", jtag_data[0], spi_addr[31:0], $realtime);
+ this.set_dmi(
+ 2'b10, //write
+ 7'h39, //sbaddress0,
+ spi_addr[31:0]+4, //bootaddress
+ {dm_addr, dm_data, dm_op},
+ s_tck,
+ s_tms,
+ s_trstn,
+ s_tdi,
+ s_tdo
+ );
+
+ this.set_dmi(
+ 2'b10, //write
+ 7'h3C, //sbdata0,
+ jtag_data[1], //data
+ {dm_addr, dm_data, dm_op},
+ s_tck,
+ s_tms,
+ s_trstn,
+ s_tdi,
+ s_tdo
+ );
+ end
+ $display("[JTAG] Loading L2 - Written up to %x (%t)", spi_addr[31:0]+4, $realtime);
+
+ end
+ this.set_sbreadonaddr(1'b1, s_tck, s_tms, s_trstn, s_tdi, s_tdo);
+ this.set_sbautoincrement(1'b0, s_tck, s_tms, s_trstn, s_tdi, s_tdo);
+
+ endtask
+
+ // discover harts by writting all ones to hartsel and reading it back
+ task test_discover_harts(
+ output logic error,
+ ref logic s_tck,
+ ref logic s_tms,
+ ref logic s_trstn,
+ ref logic s_tdi,
+ ref logic s_tdo
+ );
+
+ dm::dmcontrol_t dmcontrol;
+ dm::dmstatus_t dmstatus;
+ logic [9:0] hartsello;
+
+ int hartcount = 0;
+
+ error = 1'b0;
+
+ this.read_debug_reg(dm::DMControl, dmcontrol,
+ s_tck, s_tms, s_trstn, s_tdi, s_tdo);
+ dmcontrol.hartsello = 10'h3ff;
+ dmcontrol.hartselhi = 10'h3ff;
+
+ this.write_debug_reg(dm::DMControl, dmcontrol,
+ s_tck, s_tms, s_trstn, s_tdi, s_tdo);
+
+ this.read_debug_reg(dm::DMControl, dmcontrol,
+ s_tck, s_tms, s_trstn, s_tdi, s_tdo);
+
+ $display("[TB] %t hartsel bits usuable %x",
+ $realtime, {dmcontrol.hartselhi, dmcontrol.hartsello});
+
+ // some simulators don't like direct indexing
+ hartsello = dmcontrol.hartsello;
+ assert(hartsello[0] === 1'b1)
+ else $info("test assumes atleast one usuable bit in hartsel");
+
+ for (int i = 0; i < {dmcontrol.hartselhi, dmcontrol.hartsello}; i++) begin
+ set_hartsel(i, s_tck, s_tms, s_trstn, s_tdi, s_tdo);
+ this.read_debug_reg(dm::DMStatus, dmstatus,
+ s_tck, s_tms, s_trstn, s_tdi, s_tdo);
+
+ if(dmstatus.anynonexistent === 1'b1) // no more harts
+ break;
+
+ if(dmstatus.anyunavail !== 1'b1) // selected hart not here
+ hartcount++;
+
+ end
+
+ assert (hartcount === 1)
+ else begin
+ $error("bad number of available harts in system detected: expected %x, received %x",
+ 1, hartcount);
+ error = 1'b1;
+ end
+
+ endtask
+
+
+ // access csr, gpr by means of abstract command
+ task test_gpr_read_write_abstract(
+ output logic error,
+ ref logic s_tck,
+ ref logic s_tms,
+ ref logic s_trstn,
+ ref logic s_tdi,
+ ref logic s_tdo
+ );
+
+ logic [1:0] dmi_op;
+ logic [31:0] dmi_data;
+ logic [31:0] dmi_command;
+ logic [6:0] dmi_addr;
+
+ error = 1'b0;
+
+ //write beefdead into data0
+ this.writeArg(
+ 0,
+ 32'hbeefdead,
+ s_tck,
+ s_tms,
+ s_trstn,
+ s_tdi,
+ s_tdo
+ );
+
+ //Copy data0 to each register from x2 to x31 (abstract command)
+ for (logic [15:0] regno = 16'h1002; regno < 16'h1020; regno=regno+1) begin
+ dmi_data = {8'h0, 1'b0, 3'd2, 1'b0, 1'b0, 1'b1, 1'b1, regno};
+ this.set_command(
+ dmi_data,
+ s_tck,
+ s_tms,
+ s_trstn,
+ s_tdi,
+ s_tdo
+ );
+ end
+
+ // write ffff_ffff in data0 (some random value so that we can determine
+ // whether we really load something form the gprs into data0 or if its
+ // just the value from before)
+ this.writeArg(
+ 0,
+ 32'hffff_ffff,
+ s_tck,
+ s_tms,
+ s_trstn,
+ s_tdi,
+ s_tdo
+ );
+
+ for (logic [15:0] regno = 16'h1002; regno < 16'h1020; regno=regno+1) begin
+ dmi_data = {8'h0, 1'b0, 3'd2, 1'b0, 1'b0, 1'b1, 1'b1, regno};
+ this.set_command(
+ dmi_data,
+ s_tck,
+ s_tms,
+ s_trstn,
+ s_tdi,
+ s_tdo
+ );
+ // load regno into data0
+ dmi_command = {8'h0, 1'b0, 3'd2, 1'b0, 1'b0, 1'b1, 1'b0, regno};
+ this.set_command(
+ dmi_command,
+ s_tck,
+ s_tms,
+ s_trstn,
+ s_tdi,
+ s_tdo
+ );
+
+
+ // this command was tested separately to work
+ // get out data0
+ this.set_dmi(
+ 2'b01, //read
+ 7'h04, //data0
+ 32'h0, //whatever
+ {dmi_addr, dmi_data, dmi_op},
+ s_tck,
+ s_tms,
+ s_trstn,
+ s_tdi,
+ s_tdo
+ );
+
+ assert(dmi_data === 'hbeefdead)
+ else begin
+ $error("expected %x, received %x in gpr %x",
+ 'hbeefdead, dmi_data, regno);
+ error = 1'b1;
+ end
+ end
+
+ endtask
+
+ // access csr, gpr by means of abstract command in this version we employ
+ // our precise read and write commands which closely follow what is
+ // recommended in the debug spec
+ task test_gpr_read_write_abstract_high_level(
+ output logic error,
+ ref logic s_tck,
+ ref logic s_tms,
+ ref logic s_trstn,
+ ref logic s_tdi,
+ ref logic s_tdo
+ );
+
+ logic [1:0] dmi_op;
+ logic [31:0] dmi_data;
+ logic [31:0] dmi_command;
+ logic [6:0] dmi_addr;
+
+ error = 1'b0;
+
+ assert_rdy_for_abstract_cmd(s_tck, s_tms, s_trstn, s_tdi, s_tdo);
+
+ //Copy data0 to each register from x2 to x31 (abstract command)
+ for (logic [15:0] regno = 16'h1002; regno < 16'h1020; regno=regno+1) begin
+ this.write_reg_abstract_cmd(
+ regno,
+ 32'hbeefdead, // TODO: want different values for regs
+ s_tck,
+ s_tms,
+ s_trstn,
+ s_tdi,
+ s_tdo
+ );
+
+ end
+
+ // write ffff_ffff in data0 (some random value so that we can determine
+ // whether we really load something form the gprs into data0 or if its
+ // just the value from before)
+ this.write_debug_reg(
+ dm::Data0,
+ 32'hffff_ffff,
+ s_tck,
+ s_tms,
+ s_trstn,
+ s_tdi,
+ s_tdo
+ );
+
+ for (logic [15:0] regno = 16'h1002; regno < 16'h1020; regno=regno+1) begin
+ read_reg_abstract_cmd(
+ regno,
+ dmi_data,
+ s_tck,
+ s_tms,
+ s_trstn,
+ s_tdi,
+ s_tdo
+ );
+ assert(dmi_data === 'hbeefdead)
+ else begin
+ $error("expected %x, received %x in gpr %x",
+ 'hbeefdead, dmi_data, regno);
+ error = 1'b1;
+ end
+ end
+
+ endtask
+
+
+ task test_wfi_in_program_buffer(
+ output logic error,
+ ref logic s_tck,
+ ref logic s_tms,
+ ref logic s_trstn,
+ ref logic s_tdi,
+ ref logic s_tdo
+ );
+
+ logic [31:0] dm_data;
+ this.write_debug_reg(
+ dm::ProgBuf0,
+ riscv::wfi(), //wfi
+ s_tck,
+ s_tms,
+ s_trstn,
+ s_tdi,
+ s_tdo
+ );
+
+ this.write_debug_reg(
+ dm::ProgBuf0 + 1, //progrbuff1
+ riscv::ebreak(), //ebreak
+ s_tck,
+ s_tms,
+ s_trstn,
+ s_tdi,
+ s_tdo
+ );
+ //execute the program buffer
+ dm_data = {8'h0, 1'b0, 3'd2, 1'b0, 1'b1, 1'b0, 1'b0, 16'h0};
+
+ this.set_command(
+ dm_data,
+ s_tck,
+ s_tms,
+ s_trstn,
+ s_tdi,
+ s_tdo
+ );
+ error = 1'b0;
+ endtask
+
+
+ task test_abstract_cmds_prog_buf(
+ output logic error,
+ input logic [31:0] address_i,
+ ref logic s_tck,
+ ref logic s_tms,
+ ref logic s_trstn,
+ ref logic s_tdi,
+ ref logic s_tdo
+ );
+
+ logic [1:0] dm_op;
+ logic [31:0] dm_data;
+ logic [6:0] dm_addr;
+ logic [31:0] key_word = 32'hda41de;
+
+ //write key_word in data0
+ this.write_debug_reg(
+ dm::Data0,
+ key_word,
+ s_tck,
+ s_tms,
+ s_trstn,
+ s_tdi,
+ s_tdo
+ );
+
+ assert_rdy_for_abstract_cmd(s_tck, s_tms, s_trstn, s_tdi, s_tdo);
+
+ //Copy data0 to each register from x2 to x31 by means of Access Register abstract commands
+ for (logic [15:0] regno = 16'h1002; regno < 16'h1020; regno=regno+1) begin
+ dm_data = {8'h0, 1'b0, 3'd2, 1'b0, 1'b0, 1'b1, 1'b1, regno};
+
+ this.set_command(
+ dm_data,
+ s_tck,
+ s_tms,
+ s_trstn,
+ s_tdi,
+ s_tdo
+ );
+ //$display("[TB] %t Access Register at regno %d",$realtime(), regno[4:0]);
+
+ end
+
+ //Put address_i is x1 by writing it to data0 and then Access Register
+ this.write_debug_reg(
+ dm::Data0,
+ address_i,
+ s_tck,
+ s_tms,
+ s_trstn,
+ s_tdi,
+ s_tdo
+ );
+
+ dm_data = {8'h0, 1'b0, 3'd2, 1'b0, 1'b0, 1'b1, 1'b1, 16'h1001};
+ this.set_command(
+ dm_data,
+ s_tck,
+ s_tms,
+ s_trstn,
+ s_tdi,
+ s_tdo
+ );
+
+ //increase every registers x2-x31 by 2-31 store them to *(x1++)
+ for (logic [15:0] regno = 16'h1002; regno < 16'h1020; regno=regno+1) begin
+ this.write_debug_reg(
+ dm::ProgBuf0,
+ { 7'h0, regno[4:0], regno[4:0], 3'b000, regno[4:0], 7'h13 }, // addi xi, xi, i
+ s_tck,
+ s_tms,
+ s_trstn,
+ s_tdi,
+ s_tdo
+ );
+
+ this.write_debug_reg(
+ dm::ProgBuf0 + 1,
+ riscv::store(3'b010, regno[4:0], 5'h1, 12'h0), // sw xi, 0(x1)
+ //{ 7'h0, regno[4:0], 5'h1, 1'b0, 2'b10, 5'h0, 7'h23 },
+ s_tck,
+ s_tms,
+ s_trstn,
+ s_tdi,
+ s_tdo
+ );
+
+ this.write_debug_reg(
+ dm::ProgBuf0 + 2,
+ { 12'h4, 5'h1, 3'b000, 5'h1, 7'h13 }, // addi x1, x1, 4
+ s_tck,
+ s_tms,
+ s_trstn,
+ s_tdi,
+ s_tdo
+ );
+
+ this.write_debug_reg(
+ dm::ProgBuf0 + 3,
+ riscv::ebreak(), //ebreak
+ s_tck,
+ s_tms,
+ s_trstn,
+ s_tdi,
+ s_tdo
+ );
+ //execute the program buffer
+ dm_data = {8'h0, 1'b0, 3'd2, 1'b0, 1'b1, 1'b0, 1'b0, 16'h0};
+
+ this.set_command(
+ dm_data,
+ s_tck,
+ s_tms,
+ s_trstn,
+ s_tdi,
+ s_tdo
+ );
+ //$display("[TB] %t Store of the value in reg %d",$realtime(), regno[4:0]);
+ end
+
+ //Now read them from memory the previous store values
+
+ error = 1'b0;
+ for (int incAddr = 2; incAddr < 32; incAddr=incAddr+1) begin
+ this.readMem(address_i + (incAddr-2)*4, dm_data, s_tck, s_tms, s_trstn, s_tdi, s_tdo);
+ // $display("[TB] %t Read %x from %x",$realtime(), dm_data, address_i + (incAddr-2)*4);
+ assert(dm_data === key_word + incAddr)
+ else begin
+ $error("read %x from %x instead of %x",
+ dm_data, address_i + (incAddr-2)*4, key_word + incAddr);
+ error = 1'b1;
+ end
+ end
+
+ endtask
+
+
+ task test_read_write_dpc(
+ output logic error,
+ ref logic s_tck,
+ ref logic s_tms,
+ ref logic s_trstn,
+ ref logic s_tdi,
+ ref logic s_tdo
+ );
+
+ logic [1:0] dm_op;
+ logic [31:0] dm_data;
+ logic [31:0] saved;
+ logic [6:0] dm_addr;
+ logic [31:0] key_word = 32'hbeefdead;
+
+ error = 1'b0;
+
+ assert_rdy_for_abstract_cmd(s_tck, s_tms, s_trstn, s_tdi, s_tdo);
+
+ this.read_reg_abstract_cmd(
+ riscv::CSR_DPC,
+ saved,
+ s_tck,
+ s_tms,
+ s_trstn,
+ s_tdi,
+ s_tdo
+ );
+
+ this.write_reg_abstract_cmd(
+ riscv::CSR_DPC,
+ key_word,
+ s_tck,
+ s_tms,
+ s_trstn,
+ s_tdi,
+ s_tdo
+ );
+
+ this.read_reg_abstract_cmd(
+ riscv::CSR_DPC,
+ dm_data,
+ s_tck,
+ s_tms,
+ s_trstn,
+ s_tdi,
+ s_tdo
+ );
+
+ assert(key_word === dm_data)
+ else begin
+ $error("read %x instead of %x", dm_data, key_word);
+ error = 1'b1;
+ end;
+
+ this.write_reg_abstract_cmd(
+ riscv::CSR_DPC,
+ saved,
+ s_tck,
+ s_tms,
+ s_trstn,
+ s_tdi,
+ s_tdo
+ );
+
+ endtask
+
+ task test_wfi_wakeup(
+ output logic error,
+ input logic [31:0] addr_i,
+ ref logic s_tck,
+ ref logic s_tms,
+ ref logic s_trstn,
+ ref logic s_tdi,
+ ref logic s_tdo
+ );
+
+ logic [31:0] dm_dpc;
+ riscv::dcsr_t dcsr;
+ dm::dmstatus_t dmstatus;
+
+ error = 1'b0;
+
+ // check if our hart is halted
+ this.read_debug_reg(dm::DMStatus, dmstatus,
+ s_tck, s_tms, s_trstn, s_tdi, s_tdo);
+ assert(dmstatus.allhalted == 1'b1)
+ else begin
+ $error("allhalted flag is not set when entering test");
+ error = 1'b1;
+ end
+
+ // write short program to single step through
+ this.writeMem(addr_i, riscv::wfi(), // wfi
+ s_tck, s_tms, s_trstn, s_tdi, s_tdo);
+ this.writeMem(addr_i + 4, { 7'h0, 5'b1, 5'b1, 3'b000, 5'b1, 7'h13 }, // addi xi, xi, i
+ s_tck, s_tms, s_trstn, s_tdi, s_tdo);
+ this.writeMem(addr_i + 8, { 7'h0, 5'b1, 5'b1, 3'b000, 5'b1, 7'h13 }, // addi xi, xi, i
+ s_tck, s_tms, s_trstn, s_tdi, s_tdo);
+ this.writeMem(addr_i + 12, { 7'h0, 5'b1, 5'b1, 3'b000, 5'b1, 7'h13 }, // addi xi, xi, i
+ s_tck, s_tms, s_trstn, s_tdi, s_tdo);
+ this.writeMem(addr_i + 16, {20'b0, 5'b0, 7'b1101111}, // J zero offset
+ s_tck, s_tms, s_trstn, s_tdi, s_tdo);
+
+ assert_rdy_for_abstract_cmd(s_tck, s_tms, s_trstn, s_tdi, s_tdo);
+
+ // write dpc to addr_i so that we know where we resume
+ this.write_reg_abstract_cmd(riscv::CSR_DPC, addr_i,
+ s_tck, s_tms, s_trstn, s_tdi, s_tdo);
+
+ // resume the core
+ this.resume_harts(s_tck, s_tms, s_trstn, s_tdi, s_tdo);
+
+ this.halt_harts(s_tck, s_tms, s_trstn, s_tdi, s_tdo);
+ // The core should be in the WFI
+
+ this.read_reg_abstract_cmd(riscv::CSR_DPC, dm_dpc,
+ s_tck, s_tms, s_trstn, s_tdi, s_tdo);
+
+ // check if dpc, dcause and flag bits are ok
+ assert(addr_i + 4 === dm_dpc) // did dpc increment?
+ else begin
+ $error("dpc is %x, expected %x", dm_dpc, addr_i + 4);
+ error = 1'b1;
+ end;
+
+ // restore dpc to entry point
+ this.write_reg_abstract_cmd(riscv::CSR_DPC, addr_i,
+ s_tck, s_tms, s_trstn, s_tdi, s_tdo);
+
+ endtask
+
+
+ task test_single_stepping_abstract_cmd(
+ output logic error,
+ input logic [31:0] addr_i,
+ ref logic s_tck,
+ ref logic s_tms,
+ ref logic s_trstn,
+ ref logic s_tdi,
+ ref logic s_tdo
+ );
+
+ logic [1:0] dm_op;
+ logic [31:0] dm_data;
+ riscv::dcsr_t dcsr;
+ dm::dmstatus_t dmstatus;
+ logic [6:0] dm_addr;
+
+ error = 1'b0;
+
+ // check if our hart is halted
+ this.read_debug_reg(dm::DMStatus, dmstatus,
+ s_tck, s_tms, s_trstn, s_tdi, s_tdo);
+ assert(dmstatus.allhalted == 1'b1)
+ else begin
+ $error("allhalted flag is not set when entering test");
+ error = 1'b1;
+ end
+
+ // write short program to single step through
+ this.writeMem(addr_i, { 7'h0, 5'b1, 5'b1, 3'b000, 5'b1, 7'h13 }, // addi xi, xi, i
+ s_tck, s_tms, s_trstn, s_tdi, s_tdo);
+ this.writeMem(addr_i + 4, { 7'h0, 5'b1, 5'b1, 3'b000, 5'b1, 7'h13 }, // addi xi, xi, i
+ s_tck, s_tms, s_trstn, s_tdi, s_tdo);
+ this.writeMem(addr_i + 8, { 7'h0, 5'b1, 5'b1, 3'b000, 5'b1, 7'h13 }, // addi xi, xi, i
+ s_tck, s_tms, s_trstn, s_tdi, s_tdo);
+ this.writeMem(addr_i + 12, { 7'h0, 5'b1, 5'b1, 3'b000, 5'b1, 7'h13 }, // addi xi, xi, i
+ s_tck, s_tms, s_trstn, s_tdi, s_tdo);
+ this.writeMem(addr_i + 16, {20'b0, 5'b0, 7'b1101111}, // J zero offset
+ s_tck, s_tms, s_trstn, s_tdi, s_tdo);
+
+ assert_rdy_for_abstract_cmd(s_tck, s_tms, s_trstn, s_tdi, s_tdo);
+
+ // set step flag in dcsr
+ this.read_reg_abstract_cmd(riscv::CSR_DCSR, dcsr,
+ s_tck, s_tms, s_trstn, s_tdi, s_tdo);
+ dcsr.step = 1;
+ this.write_reg_abstract_cmd(riscv::CSR_DCSR, dcsr,
+ s_tck, s_tms, s_trstn, s_tdi, s_tdo);
+ this.read_reg_abstract_cmd(riscv::CSR_DCSR, dcsr,
+ s_tck, s_tms, s_trstn, s_tdi, s_tdo);
+ assert(dcsr.step == 1)
+ else begin
+ $error("couldn't enter single stepping mode");
+ error = 1'b1;
+ end;
+
+ // write dpc to addr_i so that we know where we resume
+ this.write_reg_abstract_cmd(riscv::CSR_DPC, addr_i,
+ s_tck, s_tms, s_trstn, s_tdi, s_tdo);
+
+ this.read_reg_abstract_cmd(riscv::CSR_DPC, dm_data, s_tck, s_tms,
+ s_trstn, s_tdi, s_tdo);
+
+ for (int i = 1; i < 4; i++) begin
+ // Make a single step. Like openocd we halt the hart manually even
+ // though it might suffice to just check if allhalted is set.
+ this.resume_harts(s_tck, s_tms, s_trstn, s_tdi, s_tdo);
+ this.halt_harts(s_tck, s_tms, s_trstn, s_tdi, s_tdo);
+ // this.block_until_any_halt(s_tck, s_tms, s_trstn, s_tdi, s_tdo);
+
+ this.read_reg_abstract_cmd(riscv::CSR_DPC, dm_data,
+ s_tck, s_tms, s_trstn, s_tdi, s_tdo);
+ // check if dpc, dcause and flag bits are ok
+ assert(addr_i + 4*i === dm_data) // did dpc increment?
+ else begin
+ $error("dpc is %x, expected %x", dm_data, addr_i + 4);
+ error = 1'b1;
+ end;
+ this.read_reg_abstract_cmd(riscv::CSR_DCSR, dcsr,
+ s_tck, s_tms, s_trstn, s_tdi, s_tdo);
+ assert(3'h4 === dcsr.cause) // is cause properly given as "step"?
+ else begin
+ $error("debug cause is %x, expected %x", dcsr.cause, 3'h4);
+ error = 1'b1;
+ end;
+ end
+
+ // clear step flag in dcsr
+ this.read_reg_abstract_cmd(riscv::CSR_DCSR, dcsr,
+ s_tck, s_tms, s_trstn, s_tdi, s_tdo);
+ dcsr.step = 0;
+ this.write_reg_abstract_cmd(riscv::CSR_DCSR, dcsr,
+ s_tck, s_tms, s_trstn, s_tdi, s_tdo);
+
+
+ endtask
+
+
+ task test_single_stepping_edge_cases(
+ output logic error,
+ input logic [31:0] addr_i,
+ ref logic s_tck,
+ ref logic s_tms,
+ ref logic s_trstn,
+ ref logic s_tdi,
+ ref logic s_tdo
+ );
+
+ logic [1:0] dm_op;
+ logic [31:0] dm_data;
+ riscv::dcsr_t dcsr;
+ dm::dmstatus_t dmstatus;
+ logic [6:0] dm_addr;
+ // records the sequence of expected pc changes
+ int pc_offsets[];
+
+ error = 1'b0;
+
+ // check if our hart is halted
+ this.read_debug_reg(dm::DMStatus, dmstatus,
+ s_tck, s_tms, s_trstn, s_tdi, s_tdo);
+ assert(dmstatus.allhalted == 1'b1)
+ else begin
+ $error("allhalted flag is not set when entering test");
+ error = 1'b1;
+ end
+
+ // write short program to single step through
+ pc_offsets = {4, 8, 16, 20, 24, 28, 32};
+ this.writeMem(addr_i + 0, riscv::nop(),
+ s_tck, s_tms, s_trstn, s_tdi, s_tdo);
+ this.writeMem(addr_i + 4, riscv::nop(),
+ s_tck, s_tms, s_trstn, s_tdi, s_tdo);
+ this.writeMem(addr_i + 8, riscv::branch(5'h0, 5'h0, 3'b0, 12'h4), // branch to + 16
+ s_tck, s_tms, s_trstn, s_tdi, s_tdo);
+ this.writeMem(addr_i + 12, riscv::nop(),
+ s_tck, s_tms, s_trstn, s_tdi, s_tdo);
+ this.writeMem(addr_i + 16, { 7'h0, 5'b1, 5'b1, 3'b000, 5'b1, 7'h13 }, // addi xi, xi, i
+ s_tck, s_tms, s_trstn, s_tdi, s_tdo);
+ this.writeMem(addr_i + 20, { 7'h0, 5'b1, 5'b1, 3'b000, 5'b1, 7'h13 }, // addi xi, xi, i
+ s_tck, s_tms, s_trstn, s_tdi, s_tdo);
+ this.writeMem(addr_i + 24, riscv::wfi(), // step over wfi
+ s_tck, s_tms, s_trstn, s_tdi, s_tdo);
+ this.writeMem(addr_i + 28, { 7'h0, 5'b1, 5'b1, 3'b000, 5'b1, 7'h13 }, // addi xi, xi, i
+ s_tck, s_tms, s_trstn, s_tdi, s_tdo);
+ this.writeMem(addr_i + 32, {20'b0, 5'b0, 7'b1101111}, // J zero offset
+ s_tck, s_tms, s_trstn, s_tdi, s_tdo);
+
+
+ assert_rdy_for_abstract_cmd(s_tck, s_tms, s_trstn, s_tdi, s_tdo);
+
+ // set step flag in dcsr
+ this.read_reg_abstract_cmd(riscv::CSR_DCSR, dcsr,
+ s_tck, s_tms, s_trstn, s_tdi, s_tdo);
+ dcsr.step = 1;
+ this.write_reg_abstract_cmd(riscv::CSR_DCSR, dcsr,
+ s_tck, s_tms, s_trstn, s_tdi, s_tdo);
+ this.read_reg_abstract_cmd(riscv::CSR_DCSR, dcsr,
+ s_tck, s_tms, s_trstn, s_tdi, s_tdo);
+ assert(dcsr.step == 1)
+ else begin
+ $error("couldn't enter single stepping mode");
+ error = 1'b1;
+ end;
+
+ // write dpc to addr_i so that we know where we resume
+ this.write_reg_abstract_cmd(riscv::CSR_DPC, addr_i,
+ s_tck, s_tms, s_trstn, s_tdi, s_tdo);
+
+ this.read_reg_abstract_cmd(riscv::CSR_DPC, dm_data, s_tck, s_tms,
+ s_trstn, s_tdi, s_tdo);
+
+ for (int i = 0; i < $size(pc_offsets); i++) begin
+ // Make a single step. Like openocd we halt the hart manually even
+ // though it might suffice to just check if allhalted is set.
+ this.resume_harts(s_tck, s_tms, s_trstn, s_tdi, s_tdo);
+ this.halt_harts(s_tck, s_tms, s_trstn, s_tdi, s_tdo);
+ // this.block_until_any_halt(s_tck, s_tms, s_trstn, s_tdi, s_tdo);
+
+ this.read_reg_abstract_cmd(riscv::CSR_DPC, dm_data,
+ s_tck, s_tms, s_trstn, s_tdi, s_tdo);
+ // check if dpc, dcause and flag bits are ok
+ assert(addr_i + pc_offsets[i] === dm_data) // did dpc increment?
+ else begin
+ $error("dpc is %x, expected %x", dm_data, addr_i + pc_offsets[i]);
+ error = 1'b1;
+ end;
+ this.read_reg_abstract_cmd(riscv::CSR_DCSR, dcsr,
+ s_tck, s_tms, s_trstn, s_tdi, s_tdo);
+ assert(dm::CauseSingleStep === dcsr.cause) // is cause properly given as "step"?
+ else begin
+ $error("debug cause is %x, expected %x", dcsr.cause, dm::CauseSingleStep);
+ error = 1'b1;
+ end;
+ end
+
+ // clear step flag in dcsr
+ this.read_reg_abstract_cmd(riscv::CSR_DCSR, dcsr,
+ s_tck, s_tms, s_trstn, s_tdi, s_tdo);
+ dcsr.step = 0;
+ this.write_reg_abstract_cmd(riscv::CSR_DCSR, dcsr,
+ s_tck, s_tms, s_trstn, s_tdi, s_tdo);
+
+
+ endtask
+
+
+ task test_halt_resume(
+ output logic error,
+ ref logic s_tck,
+ ref logic s_tms,
+ ref logic s_trstn,
+ ref logic s_tdi,
+ ref logic s_tdo
+ );
+ dm::dmstatus_t dmstatus;
+ error = 1'b0;
+
+ // check if our hart is halted
+ this.read_debug_reg(dm::DMStatus, dmstatus,
+ s_tck, s_tms, s_trstn, s_tdi, s_tdo);
+ assert(dmstatus.allhalted == 1'b1)
+ else begin
+ $error("allhalted flag is not set when entering test");
+ error = 1'b1;
+ end
+
+ // resume core and check flags
+ this.resume_harts(s_tck, s_tms, s_trstn, s_tdi, s_tdo);
+
+ this.read_debug_reg(dm::DMStatus, dmstatus,
+ s_tck, s_tms, s_trstn, s_tdi, s_tdo);
+ assert(dmstatus.allrunning == 1'b1)
+ else begin
+ $error("allrunning flag is not set after resume request");
+ error = 1'b1;
+ end
+
+ // halt core and check flags
+ this.halt_harts(s_tck, s_tms, s_trstn, s_tdi, s_tdo);
+ this.read_debug_reg(dm::DMStatus, dmstatus,
+ s_tck, s_tms, s_trstn, s_tdi, s_tdo);
+ assert(dmstatus.allhalted == 1'b1)
+ else begin
+ $error("allhalted flag is not set after halt request");
+ error = 1'b1;
+ end
+
+ endtask
+
+ task test_debug_cause_values(
+ output logic error,
+ input logic [31:0] addr_i,
+ ref logic s_tck,
+ ref logic s_tms,
+ ref logic s_trstn,
+ ref logic s_tdi,
+ ref logic s_tdo
+ );
+ dm::dmstatus_t dmstatus;
+ riscv::dcsr_t dcsr;
+
+ error = 1'b0;
+
+
+ // check if our hart is halted
+ this.read_debug_reg(dm::DMStatus, dmstatus,
+ s_tck, s_tms, s_trstn, s_tdi, s_tdo);
+ assert(dmstatus.allhalted == 1'b1)
+ else begin
+ $error("allhalted flag is not set when entering test");
+ error = 1'b1;
+ end
+
+ //Write while(1) to BEGIN_L2_INSTR
+ this.writeMem(addr_i, {25'b0, 7'b1101111},
+ s_tck, s_tms, s_trstn, s_tdi, s_tdo);
+
+ // // check if debug cause is haltrequest
+ this.resume_harts(s_tck, s_tms, s_trstn, s_tdi, s_tdo);
+ this.halt_harts(s_tck, s_tms, s_trstn, s_tdi, s_tdo);
+ this.read_reg_abstract_cmd(riscv::CSR_DCSR, dcsr,
+ s_tck, s_tms, s_trstn, s_tdi, s_tdo);
+ assert(dm::CauseRequest === dcsr.cause)
+ else begin
+ $error("debug cause is %x, expected %x", dcsr.cause, dm::CauseRequest);
+ error = 1'b1;
+ end;
+
+ // check if debug request is haltrequest
+ this.read_reg_abstract_cmd(riscv::CSR_DCSR, dcsr,
+ s_tck, s_tms, s_trstn, s_tdi, s_tdo);
+ dcsr.step = 1;
+ this.write_reg_abstract_cmd(riscv::CSR_DCSR, dcsr,
+ s_tck, s_tms, s_trstn, s_tdi, s_tdo);
+
+ this.resume_harts(s_tck, s_tms, s_trstn, s_tdi, s_tdo);
+ this.block_until_any_halt(s_tck, s_tms, s_trstn, s_tdi, s_tdo);
+ //this.halt_harts(s_tck, s_tms, s_trstn, s_tdi, s_tdo);
+
+ this.read_reg_abstract_cmd(riscv::CSR_DCSR, dcsr,
+ s_tck, s_tms, s_trstn, s_tdi, s_tdo);
+ assert(dm::CauseSingleStep === dcsr.cause)
+ else begin
+ $error("debug cause is %x, expected %x", dcsr.cause, dm::CauseSingleStep);
+ error = 1'b1;
+ end;
+
+ this.read_reg_abstract_cmd(riscv::CSR_DCSR, dcsr,
+ s_tck, s_tms, s_trstn, s_tdi, s_tdo);
+ dcsr.step = 0;
+ this.write_reg_abstract_cmd(riscv::CSR_DCSR, dcsr,
+ s_tck, s_tms, s_trstn, s_tdi, s_tdo);
+
+ // check if debug request is breakpoint
+ this.writeMem(addr_i + 0, { 7'h0, 5'b1, 5'b1, 3'b000, 5'b1, 7'h13 }, // addi xi, xi, i
+ s_tck, s_tms, s_trstn, s_tdi, s_tdo);
+ this.writeMem(addr_i + 4, { 7'h0, 5'b1, 5'b1, 3'b000, 5'b1, 7'h13 }, // addi xi, xi, i
+ s_tck, s_tms, s_trstn, s_tdi, s_tdo);
+ this.writeMem(addr_i + 8, riscv::ebreak(),
+ s_tck, s_tms, s_trstn, s_tdi, s_tdo);
+ this.writeMem(addr_i + 12, {20'b0, 5'b0, 7'b1101111}, // J zero offset
+ s_tck, s_tms, s_trstn, s_tdi, s_tdo);
+
+ // force ebreak in m-mode to enter debug mode
+ this.read_reg_abstract_cmd(riscv::CSR_DCSR, dcsr,
+ s_tck, s_tms, s_trstn, s_tdi, s_tdo);
+ dcsr.ebreakm = 1;
+ this.write_reg_abstract_cmd(riscv::CSR_DCSR, dcsr,
+ s_tck, s_tms, s_trstn, s_tdi, s_tdo);
+ this.resume_harts(s_tck, s_tms, s_trstn, s_tdi, s_tdo);
+ // TODO: delay here until entering park loop...
+ // check halted?
+
+ this.read_reg_abstract_cmd(riscv::CSR_DCSR, dcsr,
+ s_tck, s_tms, s_trstn, s_tdi, s_tdo);
+ assert(dm::CauseBreakpoint === dcsr.cause)
+ else begin
+ $error("debug cause is %x, expected %x", dcsr.cause, dm::CauseBreakpoint);
+ error = 1'b1;
+ end;
+
+ this.read_reg_abstract_cmd(riscv::CSR_DCSR, dcsr,
+ s_tck, s_tms, s_trstn, s_tdi, s_tdo);
+ dcsr.ebreakm = 0;
+ this.write_reg_abstract_cmd(riscv::CSR_DCSR, dcsr,
+ s_tck, s_tms, s_trstn, s_tdi, s_tdo);
+
+
+ endtask
+
+
+ task test_ebreak_in_program_buffer(
+ output logic error,
+ ref logic s_tck,
+ ref logic s_tms,
+ ref logic s_trstn,
+ ref logic s_tdi,
+ ref logic s_tdo
+ );
+
+ logic [31:0] dm_data;
+ logic [31:0] dpc_save, dpc;
+ riscv::dcsr_t dcsr_save, dcsr;
+ dm::dmstatus_t dmstatus;
+
+ error = 1'b0;
+
+ // check if our hart is halted
+ this.read_debug_reg(dm::DMStatus, dmstatus,
+ s_tck, s_tms, s_trstn, s_tdi, s_tdo);
+ assert(dmstatus.allhalted == 1'b1)
+ else begin
+ $error("allhalted flag is not set when entering test");
+ error = 1'b1;
+ end
+
+ // save dpc, dcsr.cause
+ this.read_reg_abstract_cmd(riscv::CSR_DPC, dpc_save, s_tck, s_tms,
+ s_trstn, s_tdi, s_tdo);
+
+ this.read_reg_abstract_cmd(riscv::CSR_DCSR, dcsr_save, s_tck, s_tms,
+ s_trstn, s_tdi, s_tdo);
+
+ // write to program buffer
+ this.write_debug_reg(dm::ProgBuf0, riscv::nop(),
+ s_tck, s_tms, s_trstn, s_tdi, s_tdo);
+ this.write_debug_reg(dm::ProgBuf0 + 1, riscv::ebreak(),
+ s_tck, s_tms, s_trstn, s_tdi, s_tdo);
+
+ //execute the program buffer
+ dm_data = {8'h0, 1'b0, 3'd2, 1'b0, 1'b1, 1'b0, 1'b0, 16'h0};
+ this.set_command(dm_data, s_tck, s_tms, s_trstn, s_tdi, s_tdo);
+
+ // check that dpc and dcsr.cause didn't change
+ this.read_reg_abstract_cmd(riscv::CSR_DPC, dpc, s_tck, s_tms,
+ s_trstn, s_tdi, s_tdo);
+
+ this.read_reg_abstract_cmd(riscv::CSR_DCSR, dcsr, s_tck, s_tms,
+ s_trstn, s_tdi, s_tdo);
+ assert(dpc == dpc_save)
+ else begin
+ $error("dpc changed from %x to %x", dpc_save, dpc);
+ error = 1'b1;
+ end
+
+ assert(dcsr.cause == dcsr_save.cause)
+ else begin
+ $error("dcsr changed from %x to %x", dcsr.cause, dcsr_save.cause);
+ error = 1'b1;
+ end
+
+ endtask
+
+ task test_bad_aarsize (
+ output logic error,
+ ref logic s_tck,
+ ref logic s_tms,
+ ref logic s_trstn,
+ ref logic s_tdi,
+ ref logic s_tdo
+ );
+ // assert busy == 0 and cmderr != 0,1
+ logic [1:0] dm_op;
+ logic [6:0] dm_addr;
+ logic [31:0] dm_data;
+ dm::abstractcs_t abstractcs;
+ dm::ac_ar_cmd_t command;
+
+ // abstract command with aarsize = 3
+ command = '{default:0, aarsize:3'd3, postexec:1'b0,
+ transfer:1'b1, write:1'b0, regno:16'h1002};
+
+ this.set_dmi(
+ 2'b10, //write
+ dm::Command,
+ {8'h0, command},
+ {dm_addr, dm_data, dm_op},
+ s_tck,
+ s_tms,
+ s_trstn,
+ s_tdi,
+ s_tdo
+ );
+
+ do begin
+ this.read_debug_reg(dm::AbstractCS, abstractcs,
+ s_tck, s_tms, s_trstn, s_tdi, s_tdo);
+ end while(abstractcs.busy == 1'b1);
+
+ assert(abstractcs.busy == 1'b0 && abstractcs.cmderr == dm::CmdErrNotSupported)
+ else begin
+ $error("Abstract cmd with 64 bit is signaled as supported");
+ error = 1'b1;
+ end
+
+ // try to clear the error bit
+ abstractcs = 0;
+ abstractcs.cmderr = dm::CmdErrNotSupported;
+
+ this.write_debug_reg(dm::AbstractCS, abstractcs,
+ s_tck, s_tms, s_trstn, s_tdi, s_tdo);
+
+ // test if it really got cleared
+ this.read_debug_reg(dm::AbstractCS, abstractcs,
+ s_tck, s_tms, s_trstn, s_tdi, s_tdo);
+
+ assert(abstractcs.cmderr == dm::CmdErrNone)
+ else begin
+ $error("cmderr bit didn't get cleared");
+ error = 1'b1;
+ end
+
+ endtask
+
+
+ task test_read_write_csr (
+ output logic error,
+ ref logic s_tck,
+ ref logic s_tms,
+ ref logic s_trstn,
+ ref logic s_tdi,
+ ref logic s_tdo
+ );
+
+ dm::abstractcs_t abstractcs;
+ logic [31:0] regs [];
+ logic [31:0] contents;
+
+
+ regs = {riscv::CSR_DPC, riscv::CSR_MSTATUS, riscv::CSR_MISA};
+
+ for (int i = 0; i < $size(regs); i++) begin
+ this.read_reg_abstract_cmd(regs[i], contents, s_tck, s_tms,
+ s_trstn, s_tdi, s_tdo);
+
+ this.read_reg_abstract_cmd(riscv::CSR_MISA, contents, s_tck, s_tms,
+ s_trstn, s_tdi, s_tdo);
+
+ end
+
+
+ endtask
+
+ // This runs all test dm tests there are. For that to work we have to run
+ // these before we load the binary into the L2 since we make ram and
+ // registers dirty. begin_l2_instr contains the boot address which is
+ // required when this tests ends so that the program can properly resume
+ // after this tests are run once the binary is loaded into l2.
+ task run_dm_tests (
+ int fc_core_id,
+ int begin_l2_instr, // required to restart booting process
+ output logic error,
+ ref logic s_tck,
+ ref logic s_tms,
+ ref logic s_trstn,
+ ref logic s_tdi,
+ ref logic s_tdo
+ );
+ logic [31:0] dm_data;
+
+
+ dump_dm_info(s_tck, s_tms, s_trstn, s_tdi, s_tdo);
+ // $display("[TB] %t - TEST discover harts", $realtime);
+ // debug_mode_if.test_discover_harts(dm_data[0],
+ // s_tck, s_tms, s_trstn, s_tdi, s_tdo);
+ // if (error)
+ // $display("[TB] %t FAIL", $realtime);
+ // else
+ // $display("[TB] %t OK", $realtime);
+
+ set_hartsel(fc_core_id, s_tck, s_tms, s_trstn, s_tdi, s_tdo);
+
+ set_sbreadonaddr(1'b1, s_tck, s_tms, s_trstn, s_tdi, s_tdo);
+
+ // check if we can read sbcs and some of its entries
+ test_read_sbcs(s_tck, s_tms, s_trstn, s_tdi, s_tdo);
+
+
+ // Make sure that we get into an infinite loop on BEGIN_L2_INSTR
+ // this is for our test setup
+ // Write while(1) to BEGIN_L2_INSTR
+ writeMem(begin_l2_instr, {25'b0, 7'b1101111},
+ s_tck, s_tms, s_trstn, s_tdi, s_tdo);
+
+ $display("[TB] %t - Resuming the CORE", $realtime);
+ resume_harts(s_tck, s_tms, s_trstn, s_tdi, s_tdo);
+
+ $display("[TB] %t - Halting the Core", $realtime);
+ halt_harts(s_tck, s_tms, s_trstn, s_tdi, s_tdo);
+
+ // simple check whether we can read abstractcs and if progbufsize and
+ // datacount are ok
+ test_read_abstractcs(s_tck, s_tms, s_trstn, s_tdi, s_tdo);
+
+ // for the following tests we need the cpu to be fetching and running
+ $display("[TB] %t - TEST halt resume functionality", $realtime);
+ test_halt_resume(error, s_tck, s_tms, s_trstn, s_tdi, s_tdo);
+ if (error)
+ $display("[TB] %t FAIL", $realtime);
+ else
+ $display("[TB] %t OK", $realtime);
+
+ $display("[TB] %t - TEST wfi wake up logic",$realtime);
+ test_wfi_wakeup(error, begin_l2_instr,
+ s_tck, s_tms, s_trstn, s_tdi, s_tdo);
+ $display("[TB] %t OK", $realtime); //otherwise we wouldn't get here
+
+ $display("[TB] %t - TEST read/write gpr with abstract command and proper waiting logic",
+ $realtime);
+ test_gpr_read_write_abstract_high_level(error, s_tck, s_tms,
+ s_trstn, s_tdi, s_tdo);
+ if (error)
+ $display("[TB] %t FAIL", $realtime);
+ else
+ $display("[TB] %t OK", $realtime);
+
+ $display("[TB] %t - TEST dumping register values using abstract command", $realtime);
+ read_reg_abstract_cmd(riscv::CSR_DCSR, dm_data, s_tck, s_tms,
+ s_trstn, s_tdi, s_tdo);
+ $display("[TB] %t dcsr is %x", $realtime, dm_data);
+ read_reg_abstract_cmd(riscv::CSR_DPC, dm_data, s_tck, s_tms,
+ s_trstn, s_tdi, s_tdo);
+ $display("[TB] %t dpc is %x", $realtime, dm_data);
+ read_reg_abstract_cmd(riscv::CSR_MTVEC, dm_data, s_tck, s_tms,
+ s_trstn, s_tdi, s_tdo);
+ $display("[TB] %t mtvec is %x", $realtime, dm_data);
+ read_reg_abstract_cmd(riscv::CSR_MCAUSE, dm_data, s_tck, s_tms,
+ s_trstn, s_tdi, s_tdo);
+ $display("[TB] %t mcause is %x", $realtime, dm_data);
+ read_reg_abstract_cmd('h1002, dm_data, s_tck, s_tms,
+ s_trstn, s_tdi, s_tdo);
+ $display("[TB] %t x2 is %x", $realtime, dm_data);
+
+ $display("[TB] %t - TEST bad abstract command (aarsize > 2)", $realtime);
+ test_bad_aarsize (error, s_tck, s_tms, s_trstn, s_tdi, s_tdo);
+ if(error)
+ $display("[TB] %t FAIL", $realtime);
+ else
+ $display("[TB] %t OK", $realtime);
+
+ $display("[TB] %t - TEST abstract commands and program buffer", $realtime);
+ test_abstract_cmds_prog_buf(error, begin_l2_instr,
+ s_tck, s_tms, s_trstn, s_tdi, s_tdo);
+ if(error)
+ $display("[TB] %t FAIL", $realtime);
+ else
+ $display("[TB] %t OK", $realtime);
+
+ $display("[TB] %t - TEST read/write dpc" , $realtime);
+ test_read_write_dpc(error, s_tck, s_tms,
+ s_trstn, s_tdi, s_tdo);
+ if(error)
+ $display("[TB] %t FAIL", $realtime);
+ else
+ $display("[TB] %t OK", $realtime);
+
+ $display("[TB] %t - TEST read/write csr" , $realtime);
+ test_read_write_csr(error, s_tck, s_tms,
+ s_trstn, s_tdi, s_tdo);
+
+ $display("[TB] %t - TEST read/write csr with program buffer (TODO)", $realtime);
+ $display("[TB] %t - TEST dret outside debug mode (TODO)", $realtime);
+
+ $display("[TB] %t - TEST ebreak in program buffer", $realtime);
+ test_ebreak_in_program_buffer(error,
+ s_tck, s_tms, s_trstn, s_tdi, s_tdo);
+ if(error)
+ $display("[TB] %t FAIL", $realtime);
+ else
+ $display("[TB] %t OK", $realtime);
+
+
+ $display("[TB] %t - TEST debug cause values", $realtime);
+ test_debug_cause_values(error, begin_l2_instr,
+ s_tck, s_tms, s_trstn, s_tdi, s_tdo);
+ if(error)
+ $display("[TB] %t FAIL", $realtime);
+ else
+ $display("[TB] %t OK", $realtime);
+
+ $display("[TB] %t - TEST single stepping", $realtime);
+ test_single_stepping_abstract_cmd(error, begin_l2_instr,
+ s_tck, s_tms, s_trstn, s_tdi, s_tdo);
+ if(error)
+ $display("[TB] %t FAIL", $realtime);
+ else
+ $display("[TB] %t OK", $realtime);
+
+ $display("[TB] %t - TEST single stepping edge cases", $realtime);
+ test_single_stepping_edge_cases(error, begin_l2_instr,
+ s_tck, s_tms, s_trstn, s_tdi, s_tdo);
+ if(error)
+ $display("[TB] %t FAIL", $realtime);
+ else
+ $display("[TB] %t OK", $realtime);
+
+ $display("[TB] %t - TEST wfi in program buffer", $realtime);
+ test_wfi_in_program_buffer(error, s_tck, s_tms,
+ s_trstn, s_tdi, s_tdo);
+ $display("[TB] %t OK", $realtime); //otherwise we wouldn't get here
+
+ $display("[TB] %t - TEST halt request during wfi (TODO)", $realtime);
+
+
+ // allows the jtag booting process to smoothly continue once we leave
+ // this test
+ $display("[TB] %t - Writing the boot address into dpc", $realtime);
+ write_reg_abstract_cmd(riscv::CSR_DPC, begin_l2_instr,
+ s_tck, s_tms, s_trstn, s_tdi, s_tdo);
+
+ endtask
+ endclass
+
+endpackage
+
+// Local Variables:
+// verilog-indent-level: 3
+// End:
--
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