diff --git a/.gitlab-ci.yml b/.gitlab-ci.yml
index 2367ea40339df6d6937716212268598779d13982..1802b219c56639a54eb374c563f9cbc09dc88f10 100644
--- a/.gitlab-ci.yml
+++ b/.gitlab-ci.yml
@@ -29,7 +29,7 @@ variables:
 stages:
   - build
   - standard
-  - serpent
+  - wb
 
 ###################################
 # prepare
@@ -52,28 +52,28 @@ build:
 asm-quest:
   stage: standard
   script:
-    - make -j${NUM_JOBS} run-asm-tests batch-mode=1
+    - make -j${NUM_JOBS} run-asm-tests batch-mode=1 defines=WB_DCACHE
   dependencies:
     - build
 
 amo-quest:
   stage: standard
   script:
-    - make -j${NUM_JOBS} run-amo-tests batch-mode=1
+    - make -j${NUM_JOBS} run-amo-tests batch-mode=1 defines=WB_DCACHE
   dependencies:
     - build
 
 fp-quest:
   stage: standard
   script:
-    - make -j${NUM_JOBS} run-fp-tests batch-mode=1
+    - make -j${NUM_JOBS} run-fp-tests batch-mode=1 defines=WB_DCACHE
   dependencies:
     - build
 
 bench-quest:
   stage: standard
   script:
-    - make -j${NUM_JOBS} run-benchmarks batch-mode=1
+    - make -j${NUM_JOBS} run-benchmarks batch-mode=1 defines=WB_DCACHE
   dependencies:
     - build
 
@@ -81,7 +81,7 @@ bench-quest:
 asm1-ver:
   stage: standard
   script:
-    - make -j${NUM_JOBS} run-asm-tests1-verilator
+    - make -j${NUM_JOBS} run-asm-tests1-verilator defines=WB_DCACHE
   dependencies:
     - build
 
@@ -89,7 +89,7 @@ asm1-ver:
 asm2-ver:
   stage: standard
   script:
-    - make -j${NUM_JOBS} run-asm-tests2-verilator
+    - make -j${NUM_JOBS} run-asm-tests2-verilator defines=WB_DCACHE
   dependencies:
     - build
 
@@ -97,7 +97,7 @@ asm2-ver:
 mul-ver:
   stage: standard
   script:
-    - make -j${NUM_JOBS} run-mul-verilator
+    - make -j${NUM_JOBS} run-mul-verilator defines=WB_DCACHE
   dependencies:
     - build
 
@@ -105,7 +105,7 @@ mul-ver:
 amo-ver:
   stage: standard
   script:
-    - make -j${NUM_JOBS} run-amo-verilator
+    - make -j${NUM_JOBS} run-amo-verilator defines=WB_DCACHE
   dependencies:
     - build
 
@@ -113,21 +113,21 @@ amo-ver:
 fp-ver:
   stage: standard
   script:
-    - make -j${NUM_JOBS} run-fp-verilator 
+    - make -j${NUM_JOBS} run-fp-verilator defines=WB_DCACHE
   dependencies:
     - build
 
 bench-ver:
   stage: standard
   script:
-    - make -j${NUM_JOBS} run-benchmarks-verilator
+    - make -j${NUM_JOBS} run-benchmarks-verilator defines=WB_DCACHE
   dependencies:
     - build
 
 bench-ver:
   stage: standard
   script:
-    - make -j${NUM_JOBS} run-benchmarks-verilator
+    - make -j${NUM_JOBS} run-benchmarks-verilator defines=WT_DCACHE
   dependencies:
     - build
 
@@ -149,96 +149,96 @@ serdiv-quest:
     - build
 
 ###################################
-# tests with serpent cache system
+# tests with write-through cache system
 
 s-asm-quest:
-  stage: serpent
+  stage: write-through
   script:
-    - make -j${NUM_JOBS} run-asm-tests defines=PITON_ARIANE+AXI64_CACHE_PORTS batch-mode=1
+    - make -j${NUM_JOBS} run-asm-tests defines=WT_DCACHE batch-mode=1
   dependencies:
     - build
 
 # atomics
 s-amo-quest:
-  stage: serpent
+  stage: write-through
   script:
-    - make -j${NUM_JOBS} run-amo-tests defines=PITON_ARIANE+AXI64_CACHE_PORTS batch-mode=1
+    - make -j${NUM_JOBS} run-amo-tests defines=WT_DCACHE batch-mode=1
   dependencies:
     - build
 
-# floating point    
+# floating point
 s-fp-quest:
-  stage: serpent
+  stage: write-through
   script:
-    - make -j${NUM_JOBS} run-fp-tests defines=PITON_ARIANE+AXI64_CACHE_PORTS batch-mode=1
+    - make -j${NUM_JOBS} run-fp-tests defines=WT_DCACHE batch-mode=1
   dependencies:
     - build
 
 s-bench-quest:
-  stage: serpent
+  stage: write-through
   script:
-    - make -j${NUM_JOBS} run-benchmarks defines=PITON_ARIANE+AXI64_CACHE_PORTS batch-mode=1
+    - make -j${NUM_JOBS} run-benchmarks defines=WT_DCACHE batch-mode=1
   dependencies:
     - build
 
 # rv64ui-p-* tests
 s-asm1-ver:
-  stage: serpent
+  stage: write-through
   script:
-    - make -j${NUM_JOBS} run-asm-tests1-verilator defines=PITON_ARIANE+AXI64_CACHE_PORTS
+    - make -j${NUM_JOBS} run-asm-tests1-verilator defines=WT_DCACHE
   dependencies:
     - build
 
 # rv64ui-v-* tests
 s-asm2-ver:
-  stage: serpent
+  stage: write-through
   script:
-    - make -j${NUM_JOBS} run-asm-tests2-verilator defines=PITON_ARIANE+AXI64_CACHE_PORTS
+    - make -j${NUM_JOBS} run-asm-tests2-verilator defines=WT_DCACHE
   dependencies:
     - build
 
 # rv64um-*-* tests
 mul-ver:
-  stage: serpent
+  stage: write-through
   script:
-    - make -j${NUM_JOBS} run-mul-verilator defines=PITON_ARIANE+AXI64_CACHE_PORTS
+    - make -j${NUM_JOBS} run-mul-verilator defines=WT_DCACHE
   dependencies:
     - build
 
 # atomics
 amo-ver:
-  stage: serpent
+  stage: write-through
   script:
-    - make -j${NUM_JOBS} run-amo-verilator defines=PITON_ARIANE+AXI64_CACHE_PORTS
+    - make -j${NUM_JOBS} run-amo-verilator defines=WT_DCACHE
   dependencies:
     - build
 
 # floating point
 s-fp-ver:
-  stage: serpent
+  stage: write-through
   script:
-    - make -j${NUM_JOBS} run-fp-verilator defines=PITON_ARIANE+AXI64_CACHE_PORTS
+    - make -j${NUM_JOBS} run-fp-verilator defines=WT_DCACHE
   dependencies:
     - build
 
 s-bench-ver:
-  stage: serpent
+  stage: write-through
   script:
-    - make -j${NUM_JOBS} run-benchmarks-verilator defines=PITON_ARIANE+AXI64_CACHE_PORTS
+    - make -j${NUM_JOBS} run-benchmarks-verilator defines=WT_DCACHE
   dependencies:
     - build
 
 s-icache-quest:
-  stage: serpent
+  stage: write-through
   script:
-    - cd tb/tb_serpent_icache/
+    - cd tb/tb_wt_icache/
     - make simc
     - "grep 'CI: PASSED' summary.rep"
 
 s-dcache-quest:
-  stage: serpent
+  stage: write-through
   script:
-    - cd tb/tb_serpent_dcache/
+    - cd tb/tb_wT_dcache/
     - make simc
     - "grep 'CI: PASSED' RD0_summary.rep"
     - "grep 'CI: PASSED' RD1_summary.rep"
@@ -247,9 +247,9 @@ s-dcache-quest:
     - build
 
 # s-torture:
-#   stage: serpent
+#   stage: write-through
 #   script:
-#     - make torture-rtest           defines=PITON_ARIANE+AXI64_CACHE_PORTS batch-mode=1
-#     - make torture-rtest-verilator defines=PITON_ARIANE+AXI64_CACHE_PORTS
+#     - make torture-rtest           defines=WT_DCACHE batch-mode=1
+#     - make torture-rtest-verilator defines=WT_DCACHE
 #   dependencies:
 #     - build
diff --git a/.travis.yml b/.travis.yml
index 5c6fdea07dfbcbef307c3f5a6498f22c884e8daa..5a353ae24900825eb34d66d1862ec89c9aee3482 100644
--- a/.travis.yml
+++ b/.travis.yml
@@ -81,34 +81,34 @@ jobs:
         - ci/install-dtc.sh
         - ci/install-spike.sh
     - stage: test
-      name: run riscv benchmarks
+      name: run riscv benchmarks (Write-Back Cache)
       script:
         - ci/build-riscv-tests.sh
-        - make -j${NUM_JOBS} run-benchmarks-verilator
+        - make -j${NUM_JOBS} run-benchmarks-verilator defines=WB_DCACHE
     # rv64ui-p-* tests
     - stage: test
-      name: run asm tests1
+      name: run asm tests1 (Write-Back Cache)
       script:
         - ci/build-riscv-tests.sh
-        - make -j${NUM_JOBS} run-asm-tests1-verilator
+        - make -j${NUM_JOBS} run-asm-tests1-verilator defines=WB_DCACHE
     # rv64ui-v-* tests
     - stage: test
-      name: run asm tests2
+      name: run asm tests2 (Write-Back Cache)
       script:
         - ci/build-riscv-tests.sh
-        - make -j${NUM_JOBS} run-asm-tests2-verilator
+        - make -j${NUM_JOBS} run-asm-tests2-verilator defines=WB_DCACHE
     # rv64um-*-* tests
     - stage: test
-      name: run mul tests
+      name: run mul tests (Write-Back Cache)
       script:
         - ci/build-riscv-tests.sh
-        - make -j${NUM_JOBS} run-mul-verilator
+        - make -j${NUM_JOBS} run-mul-verilator defines=WB_DCACHE
     # amo tests
     - stage: test
-      name: run amo tests
+      name: run amo tests (Write-Back Cache)
       script:
         - ci/build-riscv-tests.sh
-        - make -j${NUM_JOBS} run-amo-verilator
+        - make -j${NUM_JOBS} run-amo-verilator defines=WB_DCACHE
     - stage: test
       name: run torture
       script:
@@ -118,37 +118,35 @@ jobs:
         - make torture-rtest-verilator
 
     - stage: test
-      name: run riscv benchmarks (serpent)
+      name: run riscv benchmarks (Write-through Cache)
       script:
         - ci/build-riscv-tests.sh
-        - make -j${NUM_JOBS} run-benchmarks-verilator  defines=PITON_ARIANE+AXI64_CACHE_PORTS
+        - make -j${NUM_JOBS} run-benchmarks-verilator  defines=WT_DCACHE
     # rv64ui-p-* tests
     - stage: test
-      name: run asm tests1 (serpent)
+      name: run asm tests1 (Write-through Cache)
       script:
         - ci/build-riscv-tests.sh
-        - make -j${NUM_JOBS} run-asm-tests1-verilator  defines=PITON_ARIANE+AXI64_CACHE_PORTS
+        - make -j${NUM_JOBS} run-asm-tests1-verilator  defines=WT_DCACHE
     # rv64ui-v-* tests
     - stage: test
-      name: run asm tests2 (serpent)
+      name: run asm tests2 (Write-through Cache)
       script:
         - ci/build-riscv-tests.sh
-        - make -j${NUM_JOBS} run-asm-tests2-verilator  defines=PITON_ARIANE+AXI64_CACHE_PORTS
+        - make -j${NUM_JOBS} run-asm-tests2-verilator  defines=WT_DCACHE
     # amo tests
     - stage: test
       name: run amo tests
       script:
         - ci/build-riscv-tests.sh
-        - make -j${NUM_JOBS} run-amo-verilator defines=PITON_ARIANE+AXI64_CACHE_PORTS
+        - make -j${NUM_JOBS} run-amo-verilator defines=WT_DCACHE
     - stage: test
-      name: run torture (serpent)
+      name: run torture (Write-through Cache)
       script:
         - ci/get-torture.sh
         - make clean
-        - make torture-gen defines=PITON_ARIANE+AXI64_CACHE_PORTS
-        - make torture-rtest-verilator defines=PITON_ARIANE+AXI64_CACHE_PORTS
-
-
+        - make torture-gen defines=WT_DCACHE
+        - make torture-rtest-verilator defines=WT_DCACHE
 
 # extra time during long builds
 install: travis_wait
diff --git a/Flist.ariane b/Flist.ariane
index 5b902caf3495cb8cf3c159b5da645f9fcb27b9f2..726b4fe1b0f7a869d9a66434c2cfb118f2d57aa0 100644
--- a/Flist.ariane
+++ b/Flist.ariane
@@ -59,7 +59,7 @@ src/riscv-dbg/src/dm_pkg.sv
 include/riscv_pkg.sv
 include/ariane_pkg.sv
 include/ariane_axi_pkg.sv
-include/serpent_cache_pkg.sv
+include/wt_cache_pkg.sv
 //include/std_cache_pkg.sv
 include/axi_intf.sv
 src/util/instruction_tracer_pkg.sv
@@ -109,14 +109,14 @@ src/amo_buffer.sv
 src/store_unit.sv
 src/tlb.sv
 src/commit_stage.sv
-src/cache_subsystem/serpent_dcache_ctrl.sv
-src/cache_subsystem/serpent_dcache_mem.sv
-src/cache_subsystem/serpent_dcache_missunit.sv
-src/cache_subsystem/serpent_dcache_wbuffer.sv
-src/cache_subsystem/serpent_dcache.sv
-src/cache_subsystem/serpent_icache.sv
-src/cache_subsystem/serpent_l15_adapter.sv
-src/cache_subsystem/serpent_cache_subsystem.sv
+src/cache_subsystem/wt_dcache_ctrl.sv
+src/cache_subsystem/wt_dcache_mem.sv
+src/cache_subsystem/wt_dcache_missunit.sv
+src/cache_subsystem/wt_dcache_wbuffer.sv
+src/cache_subsystem/wt_dcache.sv
+src/cache_subsystem/wt_icache.sv
+src/cache_subsystem/wt_l15_adapter.sv
+src/cache_subsystem/wt_cache_subsystem.sv
 src/clint/clint.sv
 src/clint/axi_lite_interface.sv
 src/riscv-dbg/src/dm_csrs.sv
diff --git a/Makefile b/Makefile
index 5e66ea8edf81e2e9fdf12e168e5b591d245c9046..8b560c31668c785a5ac42bbe8faf22000eb36e40 100644
--- a/Makefile
+++ b/Makefile
@@ -21,7 +21,7 @@ verilator      ?= verilator
 # traget option
 target-options ?=
 # additional definess
-defines        ?=
+defines        ?= WT_DCACHE
 # test name for torture runs (binary name)
 test-location  ?= output/test
 # set to either nothing or -log
@@ -55,7 +55,7 @@ ariane_pkg := include/riscv_pkg.sv                          \
 			  src/riscv-dbg/src/dm_pkg.sv                   \
 			  include/ariane_pkg.sv                         \
 			  include/std_cache_pkg.sv                      \
-			  include/serpent_cache_pkg.sv                  \
+			  include/wt_cache_pkg.sv                       \
 			  src/axi/src/axi_pkg.sv                        \
 			  src/register_interface/src/reg_intf.sv        \
 			  include/axi_intf.sv                           \
diff --git a/README.md b/README.md
index 30fef013c78c6b133928b3681bf23205a0ca0b99..7bd82332189b101b339ee5340fc1c5aed36dcbe0 100644
--- a/README.md
+++ b/README.md
@@ -220,23 +220,16 @@ You can read or write device memory by using:
 
 ### Preliminary Support for OpenPiton Cache System
 
-Ariane has preliminary support for the OpenPiton distributed cache system from Princeton University. To this end, a different L1 cache subsystem (`src/cache_subsystem/serpent_cache_subsystem.sv`) has been developed that follows a write-through protocol and that has support for cache invalidations and atomics.
+Ariane has preliminary support for the OpenPiton distributed cache system from Princeton University. To this end, a different L1 cache subsystem (`src/cache_subsystem/wt_cache_subsystem.sv`) has been developed that follows a write-through protocol and that has support for cache invalidations and atomics.
 
-The corresponding integration patches will be released on [OpenPiton GitHub repository](https://github.com/PrincetonUniversity/openpiton). Check the README in that repository to see how to use Ariane in the OpenPiton setting.
+The corresponding integration patches will be released on [OpenPiton GitHub repository](https://github.com/PrincetonUniversity/openpiton). Check the `README` in that repository to see how to use Ariane in the OpenPiton setting.
 
-To activate the different cache system, compile your code with the macro `PITON_ARIANE`.
-
-> For testing purposes, this L1 cache subsystem also supports AXI memory plugs in order to verify it within the Ariane CI environment. In order to use this feature, the macro `AXI64_CACHE_PORTS` has to be defined. Note however, that atomics are not supported in this configuration.
-
-> Note that OpenPiton support is currently WIP, and although simple C programs run on one or several OpenPiton tiles, advanced features such as cache coherency are not fully verified yet.
-
-Also, we are working on SMP Linux support on that platform - stay tuned!
+To activate the different cache system, compile your code with the macro `WT_DCACHE` (set by default).
 
 ## Planned Improvements
 
 Check-out the issue tab which also loosely tracks planned improvements.
 
-> Atomics are implemented for a single core environment. They will semantically fail in a multi-core setup (unless you are using the serpent flavor of Ariane in combination with the OpenPiton cache subsystem, see previous section).
 
 ## Going Beyond
 
diff --git a/ci/install-verilator.sh b/ci/install-verilator.sh
index 5a5228d7da47f45f3ec86ce7ba2bca9077b46ad5..c17f6306bd8d7f0f4a8f544f385b188edb6cee2c 100755
--- a/ci/install-verilator.sh
+++ b/ci/install-verilator.sh
@@ -9,11 +9,11 @@ fi
 
 if [ ! -e "$VERILATOR_ROOT/bin/verilator" ]; then
     echo "Installing Verilator"
-    rm verilator*.t*gz
+    rm -f verilator*.tgz
     wget https://www.veripool.org/ftp/verilator-4.008.tgz
-    tar xzf verilator*.t*gz
-    rm verilator*.t*gz
-    cd verilator-*
+    tar xzf verilator*.tgz
+    rm -f verilator*.tgz
+    cd verilator*
     mkdir -p $VERILATOR_ROOT
     # copy scripts
     autoconf && ./configure --prefix="$VERILATOR_ROOT" && make -j${NUM_JOBS}
diff --git a/fpga/src/genesysii.svh b/fpga/src/genesysii.svh
index 4c72931ad9c6dc18a29dc81d27232dae3257ece7..abf5beeba22139244e211a21bc220e0b2f0cbb2e 100644
--- a/fpga/src/genesysii.svh
+++ b/fpga/src/genesysii.svh
@@ -13,12 +13,13 @@
 
 `define GENESYSII
 
-`define PITON_FPGA_SYNTH
 `define ARIANE_DATA_WIDTH 64
 
 // Instantiate protocl checker
 // `define PROTOCOL_CHECKER
 
-// Use OpenPiton Caches
-`define PITON_ARIANE
-`define AXI64_CACHE_PORTS
\ No newline at end of file
+// write-back cache
+// `define WB_DCACHE
+
+// write-through cache
+`define WT_DCACHE
diff --git a/include/ariane_pkg.sv b/include/ariane_pkg.sv
index f874b393f965a6f2cc328851c29357be396eae2f..ed270ed0b0adc399f57d24ae28e34b234f85fd69 100644
--- a/include/ariane_pkg.sv
+++ b/include/ariane_pkg.sv
@@ -20,10 +20,8 @@
 // configuration in case Ariane is
 // instantiated in OpenPiton
 `ifdef PITON_ARIANE
-`ifndef AXI64_CACHE_PORTS
   `include "l15.tmp.h"
 `endif
-`endif
 
 package ariane_pkg;
 
@@ -51,7 +49,7 @@ package ariane_pkg;
     // depth of store-buffers, this needs to be a power of two
     localparam int unsigned DEPTH_SPEC   = 4;
 
-`ifdef PITON_ARIANE
+`ifdef WT_DCACHE
     // in this case we can use a small commit queue since we have a write buffer in the dcache
     // we could in principle do without the commit queue in this case, but the timing degrades if we do that due
     // to longer paths into the commit stage
@@ -63,15 +61,9 @@ package ariane_pkg;
 
 
 `ifdef PITON_ARIANE
-    `ifdef AXI64_CACHE_PORTS
-    // Floating-point extensions configuration
-    localparam bit RVF = 1'b0; // Is F extension enabled
-    localparam bit RVD = 1'b0; // Is D extension enabled
-    `else
     // Floating-point extensions configuration
     localparam bit RVF = 1'b0; // Is F extension enabled
     localparam bit RVD = 1'b0; // Is D extension enabled
-    `endif
 `else
     // Floating-point extensions configuration
     localparam bit RVF = 1'b0; // Is F extension enabled
@@ -279,9 +271,7 @@ package ariane_pkg;
     // Cache config
     // ---------------
 
-    // if serpent pulp is used standalone (outside of openpiton)
-    // we just use the default config of ariane
-    // otherwise we have to propagate the openpiton L15 configuration from l15.h
+// for usage in OpenPiton we have to propagate the openpiton L15 configuration from l15.h
 `ifdef PITON_ARIANE
 
 `ifndef CONFIG_L1I_CACHELINE_WIDTH
diff --git a/include/serpent_cache_pkg.sv b/include/wt_cache_pkg.sv
similarity index 99%
rename from include/serpent_cache_pkg.sv
rename to include/wt_cache_pkg.sv
index 693288b0d39d6f2f15df9f0ca0976030e4a004e5..a3382861eb1ab2dfdedc3b3eaea495aa00456d03 100644
--- a/include/serpent_cache_pkg.sv
+++ b/include/wt_cache_pkg.sv
@@ -16,13 +16,11 @@
 // configuration in case Ariane is
 // instantiated in OpenPiton
 `ifdef PITON_ARIANE
-`ifndef AXI64_CACHE_PORTS
   `include "l15.tmp.h"
   `include "define.tmp.h"
 `endif
-`endif
 
-package serpent_cache_pkg;
+package wt_cache_pkg;
 
   // these parames need to coincide with the
   // L1.5 parameterization, do not change
@@ -359,4 +357,4 @@ package serpent_cache_pkg;
     return out;
   endfunction : paddrSizeAlign
 
-endpackage : serpent_cache_pkg
+endpackage
diff --git a/openpiton/ariane_verilog_wrap.sv b/openpiton/ariane_verilog_wrap.sv
index 869de9ec05668b3defffaf9edf435b46f23bf9bb..2ef30be09404acbbf30c21de8d3af995361a2dc4 100644
--- a/openpiton/ariane_verilog_wrap.sv
+++ b/openpiton/ariane_verilog_wrap.sv
@@ -12,13 +12,6 @@
 // Date: 19.03.2017
 // Description: Ariane Top-level wrapper to break out SV structs to logic vectors.
 
-// default to AXI64 cache ports if not using the
-// serpent PULP extension
-`ifndef PITON_ARIANE
-`ifndef AXI64_CACHE_PORTS
-  `define AXI64_CACHE_PORTS
-`endif
-`endif
 
 module ariane_verilog_wrap #(
   parameter logic [63:0] DmBaseAddress = 64'h0,            // debug module base address
@@ -39,31 +32,31 @@ module ariane_verilog_wrap #(
   input                       time_irq_i,   // timer interrupt in (async)
   input                       debug_req_i,  // debug request (async)
 
-`ifdef AXI64_CACHE_PORTS
+`ifdef PITON_ARIANE
+  // L15 (memory side)
+  output [$size(wt_cache_pkg::l15_req_t)-1:0]  l15_req_o,
+  input  [$size(wt_cache_pkg::l15_rtrn_t)-1:0] l15_rtrn_i
+`else
   // AXI (memory side)
   output [$size(ariane_axi::req_t)-1:0]             axi_req_o,
   input  [$size(ariane_axi::resp_t)-1:0]            axi_resp_i
-`else
-  // L15 (memory side)
-  output [$size(serpent_cache_pkg::l15_req_t)-1:0]  l15_req_o,
-  input  [$size(serpent_cache_pkg::l15_rtrn_t)-1:0] l15_rtrn_i
 `endif
  );
 
 // assign bitvector to packed struct and vice versa
-`ifdef AXI64_CACHE_PORTS
+`ifdef PITON_ARIANE
+  // L15 (memory side)
+  wt_cache_pkg::l15_req_t  l15_req;
+  wt_cache_pkg::l15_rtrn_t l15_rtrn;
+
+  assign l15_req_o = l15_req;
+  assign l15_rtrn  = l15_rtrn_i;
+`else
   ariane_axi::req_t             axi_req;
   ariane_axi::resp_t            axi_resp;
 
   assign axi_req_o = axi_req;
   assign axi_resp  = axi_resp_i;
-`else
-  // L15 (memory side)
-  serpent_cache_pkg::l15_req_t  l15_req;
-  serpent_cache_pkg::l15_rtrn_t l15_rtrn;
-
-  assign l15_req_o = l15_req;
-  assign l15_rtrn  = l15_rtrn_i;
 `endif
 
 
@@ -76,7 +69,7 @@ module ariane_verilog_wrap #(
   // logic wake_up_d, wake_up_q;
   // logic rst_n;
 
-  // assign wake_up_d = wake_up_q || ((l15_rtrn.l15_returntype == serpent_cache_pkg::L15_INT_RET) && l15_rtrn.l15_val);
+  // assign wake_up_d = wake_up_q || ((l15_rtrn.l15_returntype == wt_cache_pkg::L15_INT_RET) && l15_rtrn.l15_val);
 
   // always_ff @(posedge clk_i or negedge reset_l) begin : p_regs
   //   if(~reset_l) begin
@@ -171,12 +164,12 @@ module ariane_verilog_wrap #(
     .ipi_i       ( ipi        ),
     .time_irq_i  ( time_irq   ),
     .debug_req_i ( debug_req  ),
-`ifdef AXI64_CACHE_PORTS
-    .axi_req_o   ( axi_req   ),
-    .axi_resp_i  ( axi_resp  )
-`else
+`ifdef PITON_ARIANE
     .l15_req_o   ( l15_req   ),
     .l15_rtrn_i  ( l15_rtrn  )
+`else
+    .axi_req_o   ( axi_req   ),
+    .axi_resp_i  ( axi_resp  )
 `endif
   );
 
diff --git a/src/ariane.sv b/src/ariane.sv
index d14cec9f60a0e2dfa9167480877826991a2023ed..d6ad485c40a1cfbdad6d3e7af2377bb466f295c1 100644
--- a/src/ariane.sv
+++ b/src/ariane.sv
@@ -13,27 +13,18 @@
 // Description: Ariane Top-level module
 
 import ariane_pkg::*;
-//pragma translate_off
+// pragma translate_off
 `ifndef VERILATOR
 import instruction_tracer_pkg::*;
 `endif
-//pragma translate_on
+// pragma translate_on
 
-// default to AXI64 cache ports if not using the
-// serpent PULP extension
-`ifndef PITON_ARIANE
-`ifndef AXI64_CACHE_PORTS
-  `define AXI64_CACHE_PORTS
-`endif
-`endif
 
 module ariane #(
   parameter logic [63:0] DmBaseAddress = 64'h0,            // debug module base address
   parameter int unsigned AxiIdWidth    = 4,
-`ifdef PITON_ARIANE
   parameter bit          SwapEndianess = 0,                // swap endianess in l15 adapter
   parameter logic [63:0] CachedAddrEnd = 64'h80_0000_0000, // end of cached region
-`endif
   parameter logic [63:0] CachedAddrBeg = 64'h00_8000_0000  // begin of cached region
 ) (
   input  logic                         clk_i,
@@ -48,14 +39,14 @@ module ariane #(
   // Timer facilities
   input  logic                         time_irq_i,   // timer interrupt in (async)
   input  logic                         debug_req_i,  // debug request (async)
-`ifdef AXI64_CACHE_PORTS
+`ifdef PITON_ARIANE
+  // L15 (memory side)
+  output wt_cache_pkg::l15_req_t       l15_req_o,
+  input  wt_cache_pkg::l15_rtrn_t      l15_rtrn_i
+`else
   // memory side, AXI Master
   output ariane_axi::req_t             axi_req_o,
   input  ariane_axi::resp_t            axi_resp_i
-`else
-  // L15 (memory side)
-  output serpent_cache_pkg::l15_req_t  l15_req_o,
-  input  serpent_cache_pkg::l15_rtrn_t l15_rtrn_i
 `endif
 );
 
@@ -335,7 +326,7 @@ module ariane #(
     .trans_id_i                 ( {flu_trans_id_ex_id,  load_trans_id_ex_id,  store_trans_id_ex_id,   fpu_trans_id_ex_id }),
     .wbdata_i                   ( {flu_result_ex_id,    load_result_ex_id,    store_result_ex_id,       fpu_result_ex_id }),
     .ex_ex_i                    ( {flu_exception_ex_id, load_exception_ex_id, store_exception_ex_id, fpu_exception_ex_id }),
-    .wb_valid_i                 ( {flu_valid_ex_id,     load_valid_ex_id,     store_valid_ex_id,         fpu_valid_ex_id }),
+    .wt_valid_i                 ( {flu_valid_ex_id,     load_valid_ex_id,     store_valid_ex_id,         fpu_valid_ex_id }),
 
     .waddr_i                    ( waddr_commit_id              ),
     .wdata_i                    ( wdata_commit_id              ),
@@ -584,12 +575,10 @@ module ariane #(
   // Cache Subsystem
   // -------------------
 
-`ifdef PITON_ARIANE
+`ifdef WT_DCACHE
   // this is a cache subsystem that is compatible with OpenPiton
-  serpent_cache_subsystem #(
-`ifdef AXI64_CACHE_PORTS
+  wt_cache_subsystem #(
     .AxiIdWidth           ( AxiIdWidth    ),
-`endif
     .CachedAddrBeg        ( CachedAddrBeg ),
     .CachedAddrEnd        ( CachedAddrEnd ),
     .SwapEndianess        ( SwapEndianess )
@@ -618,13 +607,13 @@ module ariane #(
     .dcache_req_ports_o    ( dcache_req_ports_cache_ex   ),
     // write buffer status
     .wbuffer_empty_o       ( dcache_commit_wbuffer_empty ),
-`ifdef AXI64_CACHE_PORTS
+`ifdef PITON_ARIANE
+    .l15_req_o             ( l15_req_o                   ),
+    .l15_rtrn_i            ( l15_rtrn_i                  )
+`else
     // memory side
     .axi_req_o             ( axi_req_o                   ),
     .axi_resp_i            ( axi_resp_i                  )
-`else
-    .l15_req_o             ( l15_req_o                   ),
-    .l15_rtrn_i            ( l15_rtrn_i                  )
 `endif
   );
 `else
diff --git a/src/cache_subsystem/serpent_axi_adapter.sv b/src/cache_subsystem/wt_axi_adapter.sv
similarity index 92%
rename from src/cache_subsystem/serpent_axi_adapter.sv
rename to src/cache_subsystem/wt_axi_adapter.sv
index f9d7735204a9df3a7fb0bb89b33cde0c86ea7ca2..024cf901ad9ca9b76eb9ec16ecda669e1bb4c1a7 100644
--- a/src/cache_subsystem/serpent_axi_adapter.sv
+++ b/src/cache_subsystem/wt_axi_adapter.sv
@@ -14,11 +14,11 @@
 //
 
 import ariane_pkg::*;
-import serpent_cache_pkg::*;
+import wt_cache_pkg::*;
 
-module serpent_axi_adapter #(
+module wt_axi_adapter #(
   parameter int unsigned ReqFifoDepth  = 2,
-  parameter int unsigned MetaFifoDepth = serpent_cache_pkg::DCACHE_MAX_TX,
+  parameter int unsigned MetaFifoDepth = wt_cache_pkg::DCACHE_MAX_TX,
   parameter int unsigned AxiIdWidth    = 4
 ) (
    input logic                  clk_i,
@@ -77,9 +77,9 @@ logic [2:0] amo_off_d, amo_off_q;
 // AMO generates r beat
 logic amo_gen_r_d, amo_gen_r_q;
 
-logic [serpent_cache_pkg::CACHE_ID_WIDTH-1:0] icache_rtrn_tid_d, icache_rtrn_tid_q;
-logic [serpent_cache_pkg::CACHE_ID_WIDTH-1:0] dcache_rtrn_tid_d, dcache_rtrn_tid_q;
-logic [serpent_cache_pkg::CACHE_ID_WIDTH-1:0] dcache_rtrn_rd_tid, dcache_rtrn_wr_tid;
+logic [wt_cache_pkg::CACHE_ID_WIDTH-1:0] icache_rtrn_tid_d, icache_rtrn_tid_q;
+logic [wt_cache_pkg::CACHE_ID_WIDTH-1:0] dcache_rtrn_tid_d, dcache_rtrn_tid_q;
+logic [wt_cache_pkg::CACHE_ID_WIDTH-1:0] dcache_rtrn_rd_tid, dcache_rtrn_wr_tid;
 logic dcache_rd_pop, dcache_wr_pop;
 logic icache_rd_full, icache_rd_empty;
 logic dcache_rd_full, dcache_rd_empty;
@@ -161,16 +161,16 @@ always_comb begin : p_axi_req
     end else begin
       unique case (dcache_data.rtype)
         //////////////////////////////////////
-        serpent_cache_pkg::DCACHE_LOAD_REQ: begin
+        wt_cache_pkg::DCACHE_LOAD_REQ: begin
           axi_rd_req   = 1'b1;
         end
         //////////////////////////////////////
-        serpent_cache_pkg::DCACHE_STORE_REQ: begin
+        wt_cache_pkg::DCACHE_STORE_REQ: begin
           axi_wr_req   = 1'b1;
-          axi_wr_be    = serpent_cache_pkg::toByteEnable8(dcache_data.paddr[2:0], dcache_data.size[1:0]);
+          axi_wr_be    = wt_cache_pkg::toByteEnable8(dcache_data.paddr[2:0], dcache_data.size[1:0]);
         end
         //////////////////////////////////////
-        serpent_cache_pkg::DCACHE_ATOMIC_REQ: begin
+        wt_cache_pkg::DCACHE_ATOMIC_REQ: begin
           // default
           // push back an invalidation here.
           // since we only keep one read tx in flight, and since
@@ -178,7 +178,7 @@ always_comb begin : p_axi_req
           // an atomic, this is safe.
           invalidate   = arb_gnt;
           axi_wr_req   = 1'b1;
-          axi_wr_be    = serpent_cache_pkg::toByteEnable8(dcache_data.paddr[2:0], dcache_data.size[1:0]);
+          axi_wr_be    = wt_cache_pkg::toByteEnable8(dcache_data.paddr[2:0], dcache_data.size[1:0]);
           amo_gen_r_d  = 1'b1;
           // need to use a separate ID here, so concat an additional bit
           axi_wr_id_in[1] = 1'b1;
@@ -269,7 +269,7 @@ logic icache_rtrn_rd_en, dcache_rtrn_rd_en;
 logic icache_rtrn_vld_d, icache_rtrn_vld_q, dcache_rtrn_vld_d, dcache_rtrn_vld_q;
 
 fifo_v3 #(
-  .DATA_WIDTH ( serpent_cache_pkg::CACHE_ID_WIDTH ),
+  .DATA_WIDTH ( wt_cache_pkg::CACHE_ID_WIDTH ),
   .DEPTH      ( MetaFifoDepth                     )
 ) i_rd_icache_id (
   .clk_i      ( clk_i                   ),
@@ -286,7 +286,7 @@ fifo_v3 #(
 );
 
 fifo_v3 #(
-  .DATA_WIDTH ( serpent_cache_pkg::CACHE_ID_WIDTH ),
+  .DATA_WIDTH ( wt_cache_pkg::CACHE_ID_WIDTH ),
   .DEPTH      ( MetaFifoDepth                     )
 ) i_rd_dcache_id (
   .clk_i      ( clk_i                   ),
@@ -303,7 +303,7 @@ fifo_v3 #(
 );
 
 fifo_v3 #(
-  .DATA_WIDTH ( serpent_cache_pkg::CACHE_ID_WIDTH ),
+  .DATA_WIDTH ( wt_cache_pkg::CACHE_ID_WIDTH ),
   .DEPTH      ( MetaFifoDepth                     )
 ) i_wr_dcache_id (
   .clk_i      ( clk_i                   ),
@@ -353,14 +353,14 @@ fifo_v3 #(
 logic icache_first_d, icache_first_q, dcache_first_d, dcache_first_q;
 logic [ICACHE_LINE_WIDTH/64-1:0][63:0] icache_rd_shift_d, icache_rd_shift_q;
 logic [DCACHE_LINE_WIDTH/64-1:0][63:0] dcache_rd_shift_d, dcache_rd_shift_q;
-serpent_cache_pkg::dcache_in_t dcache_rtrn_type_d, dcache_rtrn_type_q;
-serpent_cache_pkg::cache_inval_t dcache_rtrn_inv_d, dcache_rtrn_inv_q;
+wt_cache_pkg::dcache_in_t dcache_rtrn_type_d, dcache_rtrn_type_q;
+wt_cache_pkg::cache_inval_t dcache_rtrn_inv_d, dcache_rtrn_inv_q;
 logic dcache_sc_rtrn, axi_rd_last;
 
 always_comb begin : p_axi_rtrn_shift
   // output directly from regs
   icache_rtrn_o              = '0;
-  icache_rtrn_o.rtype        = serpent_cache_pkg::ICACHE_IFILL_ACK;
+  icache_rtrn_o.rtype        = wt_cache_pkg::ICACHE_IFILL_ACK;
   icache_rtrn_o.tid          = icache_rtrn_tid_q;
   icache_rtrn_o.data         = icache_rd_shift_q;
   icache_rtrn_vld_o          = icache_rtrn_vld_q;
@@ -422,7 +422,7 @@ always_comb begin : p_axi_rtrn_decode
   dcache_rd_pop       = 1'b0;
   dcache_wr_pop       = 1'b0;
   dcache_rtrn_inv_d   = '0;
-  dcache_rtrn_type_d  = serpent_cache_pkg::DCACHE_LOAD_ACK;
+  dcache_rtrn_type_d  = wt_cache_pkg::DCACHE_LOAD_ACK;
   b_pop               = 1'b0;
   dcache_sc_rtrn      = 1'b0;
 
@@ -435,7 +435,7 @@ always_comb begin : p_axi_rtrn_decode
   // write-through cache architecture, which is aligned with the openpiton
   // cache subsystem.
   if (invalidate) begin
-      dcache_rtrn_type_d     = serpent_cache_pkg::DCACHE_INV_REQ;
+      dcache_rtrn_type_d     = wt_cache_pkg::DCACHE_INV_REQ;
       dcache_rtrn_vld_d      = 1'b1;
 
       dcache_rtrn_inv_d.all  = 1'b1;
@@ -450,7 +450,7 @@ always_comb begin : p_axi_rtrn_decode
 
     // if this was an atomic op
     if (axi_rd_id_out[1]) begin
-      dcache_rtrn_type_d     = serpent_cache_pkg::DCACHE_ATOMIC_ACK;
+      dcache_rtrn_type_d     = wt_cache_pkg::DCACHE_ATOMIC_ACK;
 
       // check if transaction was issued over write channel and pop that ID
       if (~dcache_wr_empty) begin
@@ -469,7 +469,7 @@ always_comb begin : p_axi_rtrn_decode
 
     // this was an atomic
     if (wr_id_out[1]) begin
-      dcache_rtrn_type_d = serpent_cache_pkg::DCACHE_ATOMIC_ACK;
+      dcache_rtrn_type_d = wt_cache_pkg::DCACHE_ATOMIC_ACK;
 
       // silently discard b response if we already popped the fifo
       // with a R beat (iff the amo transaction generated an R beat)
@@ -480,7 +480,7 @@ always_comb begin : p_axi_rtrn_decode
       end
     end else begin
       // regular response
-      dcache_rtrn_type_d = serpent_cache_pkg::DCACHE_STORE_ACK;
+      dcache_rtrn_type_d = wt_cache_pkg::DCACHE_STORE_ACK;
       dcache_rtrn_vld_d  = 1'b1;
       dcache_wr_pop      = 1'b1;
     end
@@ -510,7 +510,7 @@ always_ff @(posedge clk_i) begin : p_rd_buf
     dcache_rtrn_vld_q  <= '0;
     icache_rtrn_tid_q  <= '0;
     dcache_rtrn_tid_q  <= '0;
-    dcache_rtrn_type_q <= serpent_cache_pkg::DCACHE_LOAD_ACK;
+    dcache_rtrn_type_q <= wt_cache_pkg::DCACHE_LOAD_ACK;
     dcache_rtrn_inv_q  <= '0;
     amo_off_q          <= '0;
     amo_gen_r_q        <= 1'b0;
@@ -582,4 +582,4 @@ axi_shim #(
 `endif
 //pragma translate_on
 
-endmodule // serpent_l15_adapter
\ No newline at end of file
+endmodule // wt_l15_adapter
\ No newline at end of file
diff --git a/src/cache_subsystem/serpent_cache_subsystem.sv b/src/cache_subsystem/wt_cache_subsystem.sv
similarity index 92%
rename from src/cache_subsystem/serpent_cache_subsystem.sv
rename to src/cache_subsystem/wt_cache_subsystem.sv
index 89ec1bc57fd94d4ba7a3f52b2005a639e7b1649c..eb5eef0232afa15a20c9b1baf142be266cf8d7a1 100644
--- a/src/cache_subsystem/serpent_cache_subsystem.sv
+++ b/src/cache_subsystem/wt_cache_subsystem.sv
@@ -14,17 +14,15 @@
 //              coherent memory system.
 //
 //              Define PITON_ARIANE if you want to use this cache.
-//              Define AXI64_CACHE_PORTS if you want to use this cache
-//              with a standard 64bit AXI interace instead of the openpiton
+//              Define WT_DCACHE if you want to use this cache
+//              with a standard 64 bit AXI interface instead of the OpenPiton
 //              L1.5 interface.
 
 import ariane_pkg::*;
-import serpent_cache_pkg::*;
+import wt_cache_pkg::*;
 
-module serpent_cache_subsystem #(
-`ifdef AXI64_CACHE_PORTS
+module wt_cache_subsystem #(
   parameter int unsigned AxiIdWidth    = 10,
-`endif
   parameter logic [63:0] CachedAddrBeg = 64'h00_8000_0000, // begin of cached region
   parameter logic [63:0] CachedAddrEnd = 64'h80_0000_0000, // end of cached region
   parameter bit          SwapEndianess = 0                 // swap endianess in l15 adapter
@@ -55,36 +53,34 @@ module serpent_cache_subsystem #(
   output dcache_req_o_t   [2:0]          dcache_req_ports_o,     // to/from LSU
   // writebuffer status
   output logic                           wbuffer_empty_o,
-`ifdef AXI64_CACHE_PORTS
-  // memory side
-  output ariane_axi::req_t               axi_req_o,
-  input  ariane_axi::resp_t              axi_resp_i
-`else
+`ifdef PITON_ARIANE
   // L15 (memory side)
   output l15_req_t                       l15_req_o,
   input  l15_rtrn_t                      l15_rtrn_i
+`else
+  // memory side
+  output ariane_axi::req_t               axi_req_o,
+  input  ariane_axi::resp_t              axi_resp_i
 `endif
   // TODO: interrupt interface
 );
 
 logic icache_adapter_data_req, adapter_icache_data_ack, adapter_icache_rtrn_vld;
-serpent_cache_pkg::icache_req_t  icache_adapter;
-serpent_cache_pkg::icache_rtrn_t adapter_icache;
+wt_cache_pkg::icache_req_t  icache_adapter;
+wt_cache_pkg::icache_rtrn_t adapter_icache;
 
 
 logic dcache_adapter_data_req, adapter_dcache_data_ack, adapter_dcache_rtrn_vld;
-serpent_cache_pkg::dcache_req_t  dcache_adapter;
-serpent_cache_pkg::dcache_rtrn_t adapter_dcache;
+wt_cache_pkg::dcache_req_t  dcache_adapter;
+wt_cache_pkg::dcache_rtrn_t adapter_dcache;
 
-serpent_icache #(
-`ifdef AXI64_CACHE_PORTS
+wt_icache #(
     .Axi64BitCompliant  ( 1'b1          ),
-`endif
     // use ID 0 for icache reads
     .RdTxId             ( 0             ),
     .CachedAddrBeg      ( CachedAddrBeg ),
     .CachedAddrEnd      ( CachedAddrEnd )
-  ) i_serpent_icache (
+  ) i_wt_icache (
     .clk_i              ( clk_i                   ),
     .rst_ni             ( rst_ni                  ),
     .flush_i            ( icache_flush_i          ),
@@ -106,16 +102,14 @@ serpent_icache #(
 // Ports 0/1 for PTW and LD unit are read only.
 // they have equal prio and are RR arbited
 // Port 2 is write only and goes into the merging write buffer
-serpent_dcache #(
-`ifdef AXI64_CACHE_PORTS
+wt_dcache #(
     .Axi64BitCompliant  ( 1'b1          ),
-`endif
     // use ID 1 for dcache reads and amos. note that the writebuffer
     // uses all IDs up to DCACHE_MAX_TX-1 for write transactions.
     .RdAmoTxId       ( 1             ),
     .CachedAddrBeg   ( CachedAddrBeg ),
     .CachedAddrEnd   ( CachedAddrEnd )
-  ) i_serpent_dcache (
+  ) i_wt_dcache (
     .clk_i           ( clk_i                   ),
     .rst_ni          ( rst_ni                  ),
     .enable_i        ( dcache_enable_i         ),
@@ -140,9 +134,9 @@ serpent_dcache #(
 // L15 cache interface (derived from OpenSPARC CCX).
 ///////////////////////////////////////////////////////
 
-`ifdef AXI64_CACHE_PORTS
-  serpent_axi_adapter #(
-      .AxiIdWidth   ( AxiIdWidth )
+`ifdef PITON_ARIANE
+  wt_l15_adapter #(
+      .SwapEndianess   ( SwapEndianess )
     ) i_adapter (
       .clk_i              ( clk_i                   ),
       .rst_ni             ( rst_ni                  ),
@@ -156,12 +150,12 @@ serpent_dcache #(
       .dcache_data_i      ( dcache_adapter          ),
       .dcache_rtrn_vld_o  ( adapter_dcache_rtrn_vld ),
       .dcache_rtrn_o      ( adapter_dcache          ),
-      .axi_req_o          ( axi_req_o               ),
-      .axi_resp_i         ( axi_resp_i              )
+      .l15_req_o          ( l15_req_o               ),
+      .l15_rtrn_i         ( l15_rtrn_i              )
     );
 `else
-  serpent_l15_adapter #(
-      .SwapEndianess   ( SwapEndianess )
+  wt_axi_adapter #(
+      .AxiIdWidth   ( AxiIdWidth )
     ) i_adapter (
       .clk_i              ( clk_i                   ),
       .rst_ni             ( rst_ni                  ),
@@ -175,8 +169,8 @@ serpent_dcache #(
       .dcache_data_i      ( dcache_adapter          ),
       .dcache_rtrn_vld_o  ( adapter_dcache_rtrn_vld ),
       .dcache_rtrn_o      ( adapter_dcache          ),
-      .l15_req_o          ( l15_req_o               ),
-      .l15_rtrn_i         ( l15_rtrn_i              )
+      .axi_req_o          ( axi_req_o               ),
+      .axi_resp_i         ( axi_resp_i              )
     );
 `endif
 
@@ -207,4 +201,4 @@ serpent_dcache #(
 //pragma translate_on
 
 
-endmodule // serpent_cache_subsystem
+endmodule // wt_cache_subsystem
diff --git a/src/cache_subsystem/serpent_dcache.sv b/src/cache_subsystem/wt_dcache.sv
similarity index 97%
rename from src/cache_subsystem/serpent_dcache.sv
rename to src/cache_subsystem/wt_dcache.sv
index 5bea217fb927c1bcf3edb0c9e730870e23d5dab8..f57a506e6f54d30d518be0195ff0db0e601a1cfa 100644
--- a/src/cache_subsystem/serpent_dcache.sv
+++ b/src/cache_subsystem/wt_dcache.sv
@@ -13,9 +13,9 @@
 // Description: Instruction cache that is compatible with openpiton.
 
 import ariane_pkg::*;
-import serpent_cache_pkg::*;
+import wt_cache_pkg::*;
 
-module serpent_dcache #(
+module wt_dcache #(
     parameter bit                         Axi64BitCompliant  = 1'b0,             // set this to 1 when using in conjunction with 64bit AXI bus adapter
     // ID to be used for read and AMO transactions.
     // note that the write buffer uses all IDs up to DCACHE_MAX_TX-1 for write transactions
@@ -109,11 +109,11 @@ module serpent_dcache #(
 // miss handling unit
 ///////////////////////////////////////////////////////
 
-    serpent_dcache_missunit #(
+    wt_dcache_missunit #(
         .Axi64BitCompliant ( Axi64BitCompliant ),
         .AmoTxId           ( RdAmoTxId         ),
         .NumPorts          ( NumPorts          )
-    ) i_serpent_dcache_missunit (
+    ) i_wt_dcache_missunit (
         .clk_i              ( clk_i              ),
         .rst_ni             ( rst_ni             ),
         .enable_i           ( enable_i           ),
@@ -169,11 +169,11 @@ module serpent_dcache #(
         // set these to high prio ports
         assign rd_prio[k] = 1'b1;
 
-        serpent_dcache_ctrl #(
+        wt_dcache_ctrl #(
                 .RdTxId        ( RdAmoTxId     ),
                 .CachedAddrBeg ( CachedAddrBeg ),
                 .CachedAddrEnd ( CachedAddrEnd )
-        ) i_serpent_dcache_ctrl (
+        ) i_wt_dcache_ctrl (
                 .clk_i           ( clk_i             ),
                 .rst_ni          ( rst_ni            ),
                 .cache_en_i      ( cache_en          ),
@@ -215,10 +215,10 @@ module serpent_dcache #(
     // set read port to low priority
     assign rd_prio[2] = 1'b0;
 
-    serpent_dcache_wbuffer #(
+    wt_dcache_wbuffer #(
             .CachedAddrBeg ( CachedAddrBeg ),
             .CachedAddrEnd ( CachedAddrEnd )
-    ) i_serpent_dcache_wbuffer (
+    ) i_wt_dcache_wbuffer (
             .clk_i           ( clk_i               ),
             .rst_ni          ( rst_ni              ),
             .empty_o         ( wbuffer_empty_o     ),
@@ -270,10 +270,10 @@ module serpent_dcache #(
 // memory arrays, arbitration and tag comparison
 ///////////////////////////////////////////////////////
 
-    serpent_dcache_mem #(
+    wt_dcache_mem #(
             .Axi64BitCompliant ( Axi64BitCompliant ),
             .NumPorts          ( NumPorts          )
-    ) i_serpent_dcache_mem (
+    ) i_wt_dcache_mem (
             .clk_i             ( clk_i              ),
             .rst_ni            ( rst_ni             ),
             // read ports
@@ -329,4 +329,4 @@ module serpent_dcache #(
 `endif
 //pragma translate_on
 
-endmodule // serpent_dcache
+endmodule // wt_dcache
diff --git a/src/cache_subsystem/serpent_dcache_ctrl.sv b/src/cache_subsystem/wt_dcache_ctrl.sv
similarity index 99%
rename from src/cache_subsystem/serpent_dcache_ctrl.sv
rename to src/cache_subsystem/wt_dcache_ctrl.sv
index c86d89cfb91d9c16860fe83249d543a671580936..1a865585121d69faa742edcc9fe72ebf396410b5 100644
--- a/src/cache_subsystem/serpent_dcache_ctrl.sv
+++ b/src/cache_subsystem/wt_dcache_ctrl.sv
@@ -14,9 +14,9 @@
 
 
 import ariane_pkg::*;
-import serpent_cache_pkg::*;
+import wt_cache_pkg::*;
 
-module serpent_dcache_ctrl #(
+module wt_dcache_ctrl #(
     parameter logic [CACHE_ID_WIDTH-1:0]  RdTxId        = 1,                // ID to use for read transactions
     parameter logic [63:0]                CachedAddrBeg = 64'h00_8000_0000, // begin of cached region
     parameter logic [63:0]                CachedAddrEnd = 64'h80_0000_0000  // end of cached region
@@ -271,4 +271,4 @@ end
 `endif
 //pragma translate_on
 
-endmodule // serpent_dcache_ctrl
\ No newline at end of file
+endmodule // wt_dcache_ctrl
\ No newline at end of file
diff --git a/src/cache_subsystem/serpent_dcache_mem.sv b/src/cache_subsystem/wt_dcache_mem.sv
similarity index 96%
rename from src/cache_subsystem/serpent_dcache_mem.sv
rename to src/cache_subsystem/wt_dcache_mem.sv
index 9b88efb6debba347f8c22ce31a0fe15a23a1bee9..fae6b7c281ee1f1bf327f9c4fdc3ae886154b86d 100644
--- a/src/cache_subsystem/serpent_dcache_mem.sv
+++ b/src/cache_subsystem/wt_dcache_mem.sv
@@ -10,7 +10,7 @@
 //
 // Author: Michael Schaffner <schaffner@iis.ee.ethz.ch>, ETH Zurich
 // Date: 13.09.2018
-// Description: Memory arrays, arbiter and tag comparison for serpent dcache.
+// Description: Memory arrays, arbiter and tag comparison for wb dcache.
 //
 //
 // Notes: 1) all ports can trigger a readout of all ways, and the way where the tag hits is selected
@@ -26,9 +26,9 @@
 //           low prio ports (rd_prio_i[port_nr] = '1b0)
 
 import ariane_pkg::*;
-import serpent_cache_pkg::*;
+import wt_cache_pkg::*;
 
-module serpent_dcache_mem #(
+module wt_dcache_mem #(
     parameter bit          Axi64BitCompliant  = 1'b0, // set this to 1 when using in conjunction with 64bit AXI bus adapter
     parameter int unsigned NumPorts           = 3
 ) (
@@ -235,10 +235,10 @@ module serpent_dcache_mem #(
 
     if (Axi64BitCompliant) begin
         assign wr_cl_off     = (wr_cl_nc_i) ? '0 : wr_cl_off_i[DCACHE_OFFSET_WIDTH-1:3];
-    end else begin  
+    end else begin
         assign wr_cl_off     = wr_cl_off_i[DCACHE_OFFSET_WIDTH-1:3];
     end
-      
+
     assign rdata         = (wr_cl_vld_i)  ? wr_cl_data_i[wr_cl_off*64 +: 64] :
                                             rdata_cl[rd_hit_idx];
 
@@ -262,7 +262,7 @@ module serpent_dcache_mem #(
             // Data RAM
             sram #(
                 .DATA_WIDTH ( ariane_pkg::DCACHE_SET_ASSOC * 64 ),
-                .NUM_WORDS  ( serpent_cache_pkg::DCACHE_NUM_WORDS    )
+                .NUM_WORDS  ( wt_cache_pkg::DCACHE_NUM_WORDS    )
             ) i_data_sram (
                 .clk_i      ( clk_i               ),
                 .rst_ni     ( rst_ni              ),
@@ -284,7 +284,7 @@ module serpent_dcache_mem #(
             sram #(
                 // tag + valid bit
                 .DATA_WIDTH ( ariane_pkg::DCACHE_TAG_WIDTH + 1 ),
-                .NUM_WORDS  ( serpent_cache_pkg::DCACHE_NUM_WORDS   )
+                .NUM_WORDS  ( wt_cache_pkg::DCACHE_NUM_WORDS   )
             ) i_tag_sram (
                 .clk_i     ( clk_i               ),
                 .rst_ni    ( rst_ni              ),
@@ -335,8 +335,8 @@ module serpent_dcache_mem #(
             else $fatal(1,"[l1 dcache] wbuffer_hit_oh signal must be hot1");
 
     // this is only used for verification!
-    logic                                    vld_mirror[serpent_cache_pkg::DCACHE_NUM_WORDS-1:0][ariane_pkg::DCACHE_SET_ASSOC-1:0];
-    logic [ariane_pkg::DCACHE_TAG_WIDTH-1:0] tag_mirror[serpent_cache_pkg::DCACHE_NUM_WORDS-1:0][ariane_pkg::DCACHE_SET_ASSOC-1:0];
+    logic                                    vld_mirror[wt_cache_pkg::DCACHE_NUM_WORDS-1:0][ariane_pkg::DCACHE_SET_ASSOC-1:0];
+    logic [ariane_pkg::DCACHE_TAG_WIDTH-1:0] tag_mirror[wt_cache_pkg::DCACHE_NUM_WORDS-1:0][ariane_pkg::DCACHE_SET_ASSOC-1:0];
     logic [ariane_pkg::DCACHE_SET_ASSOC-1:0] tag_write_duplicate_test;
 
     always_ff @(posedge clk_i or negedge rst_ni) begin : p_mirror
@@ -376,4 +376,4 @@ module serpent_dcache_mem #(
 `endif
 //pragma translate_on
 
-endmodule // serpent_dcache_mem
+endmodule // wt_dcache_mem
diff --git a/src/cache_subsystem/serpent_dcache_missunit.sv b/src/cache_subsystem/wt_dcache_missunit.sv
similarity index 98%
rename from src/cache_subsystem/serpent_dcache_missunit.sv
rename to src/cache_subsystem/wt_dcache_missunit.sv
index a6174bf83449549c5ebc89dee9538d2477816bf4..f03926d4da759914b37efb44fa0678f8d502b315 100644
--- a/src/cache_subsystem/serpent_dcache_missunit.sv
+++ b/src/cache_subsystem/wt_dcache_missunit.sv
@@ -10,14 +10,14 @@
 //
 // Author: Michael Schaffner <schaffner@iis.ee.ethz.ch>, ETH Zurich
 // Date: 13.09.2018
-// Description: miss controller for serpent dcache. Note that the current assumption
+// Description: miss controller for wb dcache. Note that the current assumption
 // is that the port with the highest index issues writes instead of reads.
 
 
 import ariane_pkg::*;
-import serpent_cache_pkg::*;
+import wt_cache_pkg::*;
 
-module serpent_dcache_missunit #(
+module wt_dcache_missunit #(
     parameter bit                         Axi64BitCompliant  = 1'b0, // set this to 1 when using in conjunction with 64bit AXI bus adapter
     parameter logic [CACHE_ID_WIDTH-1:0]  AmoTxId            = 1,    // TX id to be used for AMOs
     parameter int unsigned                NumPorts           = 3     // number of miss ports
@@ -116,7 +116,7 @@ module serpent_dcache_missunit #(
 
     assign cache_en_o      = enable_q;
     assign cnt_d           = (flush_en) ? cnt_q + 1 : '0;
-    assign flush_done      = (cnt_q == serpent_cache_pkg::DCACHE_NUM_WORDS-1);
+    assign flush_done      = (cnt_q == wt_cache_pkg::DCACHE_NUM_WORDS-1);
 
     assign miss_req_masked_d = ( lock_reqs  ) ? miss_req_masked_q      :
                                ( mask_reads ) ? miss_we_i & miss_req_i : miss_req_i;
@@ -216,7 +216,7 @@ module serpent_dcache_missunit #(
           assign amo_rtrn_mux = mem_rtrn_i.data[amo_req_i.operand_a[DCACHE_OFFSET_WIDTH-1:3]*64 +: 64];
       end
     endgenerate
-    
+
     // always sign extend 32bit values
     assign amo_resp_o.result = (amo_req_i.size==2'b10) ? {{32{amo_rtrn_mux[amo_req_i.operand_a[2]*32 + 31]}},
                                                               amo_rtrn_mux[amo_req_i.operand_a[2]*32 +: 32]} :
@@ -231,7 +231,7 @@ module serpent_dcache_missunit #(
     assign mem_data_o.amo_op = (amo_sel) ? amo_req_i.amo_op    : AMO_NONE;
 
     assign tmp_paddr         = (amo_sel) ? amo_req_i.operand_a : miss_paddr_i[miss_port_idx];
-    assign mem_data_o.paddr  = serpent_cache_pkg::paddrSizeAlign(tmp_paddr, mem_data_o.size);
+    assign mem_data_o.paddr  = wt_cache_pkg::paddrSizeAlign(tmp_paddr, mem_data_o.size);
 
 ///////////////////////////////////////////////////////
 // responses from memory
@@ -510,4 +510,4 @@ end
 `endif
 //pragma translate_on
 
-endmodule // serpent_dcache_missunit
\ No newline at end of file
+endmodule // wt_dcache_missunit
\ No newline at end of file
diff --git a/src/cache_subsystem/serpent_dcache_wbuffer.sv b/src/cache_subsystem/wt_dcache_wbuffer.sv
similarity index 99%
rename from src/cache_subsystem/serpent_dcache_wbuffer.sv
rename to src/cache_subsystem/wt_dcache_wbuffer.sv
index 215b43df06372f17fa65faa640fbb673c4f40861..a410589f5a877b130f8709a576f0fc090a94b1eb 100644
--- a/src/cache_subsystem/serpent_dcache_wbuffer.sv
+++ b/src/cache_subsystem/wt_dcache_wbuffer.sv
@@ -10,7 +10,7 @@
 //
 // Author: Michael Schaffner <schaffner@iis.ee.ethz.ch>, ETH Zurich
 // Date: 13.09.2018
-// Description: coalescing write buffer for serpent dcache
+// Description: coalescing write buffer for wb dcache
 //
 // A couple of notes:
 //
@@ -49,9 +49,9 @@
 //    word has been evicted from the write buffer.
 
 import ariane_pkg::*;
-import serpent_cache_pkg::*;
+import wt_cache_pkg::*;
 
-module serpent_dcache_wbuffer #(
+module wt_dcache_wbuffer #(
     parameter logic [63:0] CachedAddrBeg = 64'h00_8000_0000, // begin of cached region
     parameter logic [63:0] CachedAddrEnd = 64'h80_0000_0000  // end of cached region
 ) (
@@ -550,4 +550,4 @@ end
 `endif
 //pragma translate_on
 
-endmodule // serpent_dcache_wbuffer
\ No newline at end of file
+endmodule // wt_dcache_wbuffer
\ No newline at end of file
diff --git a/src/cache_subsystem/serpent_icache.sv b/src/cache_subsystem/wt_icache.sv
similarity index 98%
rename from src/cache_subsystem/serpent_icache.sv
rename to src/cache_subsystem/wt_icache.sv
index b2b1b11496fcfed3ea9c621c6db9d2f6cb310dc7..6a2fc55bc736e385426ef4d2fa7a2e570edbe67d 100644
--- a/src/cache_subsystem/serpent_icache.sv
+++ b/src/cache_subsystem/wt_icache.sv
@@ -25,9 +25,9 @@
 //
 
 import ariane_pkg::*;
-import serpent_cache_pkg::*;
+import wt_cache_pkg::*;
 
-module serpent_icache  #(
+module wt_icache  #(
     parameter logic [CACHE_ID_WIDTH-1:0]  RdTxId             = 0,                // ID to be used for read transactions
     parameter bit                         Axi64BitCompliant  = 1'b0,             // set this to 1 when using in conjunction with 64bit AXI bus adapter
     parameter logic [63:0]                CachedAddrBeg      = 64'h00_8000_0000, // begin of cached region
@@ -530,8 +530,8 @@ module serpent_icache  #(
          else $fatal(1,"[l1 icache] cl_hit signal must be hot1");
 
     // this is only used for verification!
-    logic                                    vld_mirror[serpent_cache_pkg::ICACHE_NUM_WORDS-1:0][ariane_pkg::ICACHE_SET_ASSOC-1:0];        
-    logic [ariane_pkg::ICACHE_TAG_WIDTH-1:0] tag_mirror[serpent_cache_pkg::ICACHE_NUM_WORDS-1:0][ariane_pkg::ICACHE_SET_ASSOC-1:0];        
+    logic                                    vld_mirror[wt_cache_pkg::ICACHE_NUM_WORDS-1:0][ariane_pkg::ICACHE_SET_ASSOC-1:0];
+    logic [ariane_pkg::ICACHE_TAG_WIDTH-1:0] tag_mirror[wt_cache_pkg::ICACHE_NUM_WORDS-1:0][ariane_pkg::ICACHE_SET_ASSOC-1:0];
     logic [ariane_pkg::ICACHE_SET_ASSOC-1:0] tag_write_duplicate_test;
 
     always_ff @(posedge clk_i or negedge rst_ni) begin : p_mirror
@@ -543,19 +543,19 @@ module serpent_icache  #(
                 if(vld_req[i] & vld_we) begin
                     vld_mirror[vld_addr][i] <= vld_wdata[i];
                     tag_mirror[vld_addr][i] <= cl_tag_q;
-                end 
-            end       
+                end
+            end
         end
     end
 
     generate
         for (genvar i = 0; i < ICACHE_SET_ASSOC; i++) begin
             assign tag_write_duplicate_test[i] = (tag_mirror[vld_addr][i] == cl_tag_q) & vld_mirror[vld_addr][i] & (|vld_wdata);
-        end 
+        end
     endgenerate
 
     tag_write_duplicate: assert property (
-        @(posedge clk_i) disable iff (~rst_ni) |vld_req |-> vld_we |-> ~(|tag_write_duplicate_test))     
+        @(posedge clk_i) disable iff (~rst_ni) |vld_req |-> vld_we |-> ~(|tag_write_duplicate_test))
             else $fatal(1,"[l1 icache] cannot allocate a CL that is already present in the cache");
 
 
@@ -567,4 +567,4 @@ module serpent_icache  #(
 `endif
 //pragma translate_on
 
-endmodule // serpent_icache
+endmodule // wt_icache
diff --git a/src/cache_subsystem/serpent_l15_adapter.sv b/src/cache_subsystem/wt_l15_adapter.sv
similarity index 99%
rename from src/cache_subsystem/serpent_l15_adapter.sv
rename to src/cache_subsystem/wt_l15_adapter.sv
index 41e605a7fc01de26f13eb4757df5d40295a04035..95ad16136d2dc64afde25d3327369fc9c24a2570 100644
--- a/src/cache_subsystem/serpent_l15_adapter.sv
+++ b/src/cache_subsystem/wt_l15_adapter.sv
@@ -49,10 +49,10 @@
 //
 
 import ariane_pkg::*;
-import serpent_cache_pkg::*;
+import wt_cache_pkg::*;
 
-module serpent_l15_adapter #(
-  parameter bit          SwapEndianess = 1               
+module wt_l15_adapter #(
+  parameter bit          SwapEndianess = 1
 ) (
    input logic                  clk_i,
    input logic                  rst_ni,
@@ -390,4 +390,4 @@ fifo_v2 #(
 `endif
 //pragma translate_on
 
-endmodule // serpent_l15_adapter
\ No newline at end of file
+endmodule // wt_l15_adapter
\ No newline at end of file
diff --git a/src/common_cells b/src/common_cells
index c5e93e3e10abc719fed12dd92d41c1af9a0054c6..337f54a7cdfdad78b124cbdd2a627db3e0939141 160000
--- a/src/common_cells
+++ b/src/common_cells
@@ -1 +1 @@
-Subproject commit c5e93e3e10abc719fed12dd92d41c1af9a0054c6
+Subproject commit 337f54a7cdfdad78b124cbdd2a627db3e0939141
diff --git a/src/controller.sv b/src/controller.sv
index 5bbd0971de341e6c8b9085e7d6f25e16136b8bba..3f064baeb84be99fac23127e6d3ec58c0513e178 100644
--- a/src/controller.sv
+++ b/src/controller.sv
@@ -80,12 +80,12 @@ module controller (
             flush_unissued_instr_o = 1'b1;
             flush_id_o             = 1'b1;
             flush_ex_o             = 1'b1;
-// this is not needed in the case since we 
+// this is not needed in the case since we
 // have a write-through cache in this case
-`ifndef PITON_ARIANE
+`ifndef WT_DCACHE
             flush_dcache           = 1'b1;
             fence_active_d         = 1'b1;
-`endif            
+`endif
         end
 
         // ---------------------------------
@@ -98,17 +98,17 @@ module controller (
             flush_id_o             = 1'b1;
             flush_ex_o             = 1'b1;
             flush_icache_o         = 1'b1;
-// this is not needed in the case since we 
+// this is not needed in the case since we
 // have a write-through cache in this case
-`ifndef PITON_ARIANE
+`ifndef WT_DCACHE
             flush_dcache           = 1'b1;
             fence_active_d         = 1'b1;
 `endif
         end
 
-// this is not needed in the case since we 
+// this is not needed in the case since we
 // have a write-through cache in this case
-`ifndef PITON_ARIANE
+`ifndef WT_DCACHE
         // wait for the acknowledge here
         if (flush_dcache_ack_i && fence_active_q) begin
             fence_active_d = 1'b0;
@@ -171,7 +171,7 @@ module controller (
     // Registers
     // ----------------------
     always_ff @(posedge clk_i or negedge rst_ni) begin
-        if(~rst_ni) begin
+        if (~rst_ni) begin
             fence_active_q <= 1'b0;
             flush_dcache_o <= 1'b0;
         end else begin
diff --git a/src/csr_regfile.sv b/src/csr_regfile.sv
index 7d94ea71b1127baf3b30b3a2c9c4d6c2d783c71c..309cb4e0feea1d76e8bc1fb9ed68f684be267f34 100644
--- a/src/csr_regfile.sv
+++ b/src/csr_regfile.sv
@@ -971,7 +971,7 @@ module csr_regfile #(
     assign icache_en_o      = icache_q[0];
 `else
     assign icache_en_o      = icache_q[0] & (~debug_mode_q);
-    `endif
+`endif
     assign dcache_en_o      = dcache_q[0];
 
     // determine if mprv needs to be considered if in debug mode
diff --git a/src/issue_stage.sv b/src/issue_stage.sv
index 8e4ade577f28f42c90198f0834b3c614f77c00a3..c80d71083bbd3abe2840ce03f509a64da2061ce3 100644
--- a/src/issue_stage.sv
+++ b/src/issue_stage.sv
@@ -60,7 +60,7 @@ module issue_stage #(
     input branchpredict_t                            resolved_branch_i,
     input logic [NR_WB_PORTS-1:0][63:0]              wbdata_i,
     input exception_t [NR_WB_PORTS-1:0]              ex_ex_i, // exception from execute stage
-    input logic [NR_WB_PORTS-1:0]                    wb_valid_i,
+    input logic [NR_WB_PORTS-1:0]                    wt_valid_i,
 
     // commit port
     input  logic [NR_COMMIT_PORTS-1:0][4:0]          waddr_i,
diff --git a/src/scoreboard.sv b/src/scoreboard.sv
index 13bc00b514547c97c5b45b1b96188d37c016188f..049783682ffadb0e5870a34b865c0ea89c7e5287 100644
--- a/src/scoreboard.sv
+++ b/src/scoreboard.sv
@@ -62,7 +62,7 @@ module scoreboard #(
     input logic [NR_WB_PORTS-1:0][TRANS_ID_BITS-1:0]  trans_id_i,  // transaction ID at which to write the result back
     input logic [NR_WB_PORTS-1:0][63:0]               wbdata_i,    // write data in
     input exception_t [NR_WB_PORTS-1:0]               ex_i,        // exception from a functional unit (e.g.: ld/st exception)
-    input logic [NR_WB_PORTS-1:0]                     wb_valid_i   // data in is valid
+    input logic [NR_WB_PORTS-1:0]                     wt_valid_i   // data in is valid
 );
     localparam int unsigned BITS_ENTRIES      = $clog2(NR_ENTRIES);
 
@@ -128,7 +128,7 @@ module scoreboard #(
         for (int unsigned i = 0; i < NR_WB_PORTS; i++) begin
             // check if this instruction was issued (e.g.: it could happen after a flush that there is still
             // something in the pipeline e.g. an incomplete memory operation)
-            if (wb_valid_i[i] && mem_n[trans_id_i[i]].issued) begin
+            if (wt_valid_i[i] && mem_n[trans_id_i[i]].issued) begin
                 mem_n[trans_id_i[i]].sbe.valid  = 1'b1;
                 mem_n[trans_id_i[i]].sbe.result = wbdata_i[i];
                 // save the target address of a branch (needed for debug in commit stage)
@@ -238,22 +238,22 @@ module scoreboard #(
         // provide a direct combinational path from WB a.k.a forwarding
         // make sure that we are not forwarding a result that got an exception
         for (int unsigned j = 0; j < NR_WB_PORTS; j++) begin
-            if (mem_q[trans_id_i[j]].sbe.rd == rs1_i && wb_valid_i[j] && ~ex_i[j].valid
+            if (mem_q[trans_id_i[j]].sbe.rd == rs1_i && wt_valid_i[j] && ~ex_i[j].valid
                && (is_rd_fpr(mem_q[trans_id_i[j]].sbe.op) == is_rs1_fpr(issue_instr_o.op))) begin
                 rs1_o = wbdata_i[j];
-                rs1_valid_o = wb_valid_i[j];
+                rs1_valid_o = wt_valid_i[j];
                 break;
             end
-            if (mem_q[trans_id_i[j]].sbe.rd == rs2_i && wb_valid_i[j] && ~ex_i[j].valid
+            if (mem_q[trans_id_i[j]].sbe.rd == rs2_i && wt_valid_i[j] && ~ex_i[j].valid
                && (is_rd_fpr(mem_q[trans_id_i[j]].sbe.op) == is_rs2_fpr(issue_instr_o.op))) begin
                 rs2_o = wbdata_i[j];
-                rs2_valid_o = wb_valid_i[j];
+                rs2_valid_o = wt_valid_i[j];
                 break;
             end
-            if (mem_q[trans_id_i[j]].sbe.rd == rs3_i && wb_valid_i[j] && ~ex_i[j].valid
+            if (mem_q[trans_id_i[j]].sbe.rd == rs3_i && wt_valid_i[j] && ~ex_i[j].valid
                && (is_rd_fpr(mem_q[trans_id_i[j]].sbe.op) == is_imm_fpr(issue_instr_o.op))) begin
                 rs3_o = wbdata_i[j];
-                rs3_valid_o = wb_valid_i[j];
+                rs3_valid_o = wt_valid_i[j];
                 break;
             end
         end
@@ -309,7 +309,7 @@ module scoreboard #(
     for (genvar i = 0; i < NR_WB_PORTS; i++) begin
         for (genvar j = 0; j < NR_WB_PORTS; j++)  begin
             assert property (
-                @(posedge clk_i) wb_valid_i[i] && wb_valid_i[j] && (i != j) |-> (trans_id_i[i] != trans_id_i[j]))
+                @(posedge clk_i) wt_valid_i[i] && wt_valid_i[j] && (i != j) |-> (trans_id_i[i] != trans_id_i[j]))
                 else $error ("Two or more functional units are retiring instructions with the same transaction id!");
         end
     end
diff --git a/tb/ariane_testharness.sv b/tb/ariane_testharness.sv
index 386922f2ed09168a155a69c3bf4771e49db25bca..b8c785752474105602e556885ac029c83d2e2447 100644
--- a/tb/ariane_testharness.sv
+++ b/tb/ariane_testharness.sv
@@ -637,12 +637,10 @@ module ariane_testharness #(
     ariane_axi::resp_t   axi_ariane_resp;
 
     ariane #(
-`ifdef PITON_ARIANE
         .AxiIdWidth    ( ariane_axi::IdWidth                             ),
         .SwapEndianess ( 0                                               ),
-        .CachedAddrEnd ( (ariane_soc::DRAMBase + ariane_soc::DRAMLength) ),
-`endif
         .CachedAddrBeg ( ariane_soc::DRAMBase                            ),
+        .CachedAddrEnd ( (ariane_soc::DRAMBase + ariane_soc::DRAMLength) ),
         .DmBaseAddress ( ariane_soc::DebugBase                           )
     ) i_ariane (
         .clk_i                ( clk_i               ),
diff --git a/tb/tb_serpent_dcache/wave.do b/tb/tb_serpent_dcache/wave.do
deleted file mode 100644
index cdf0b0634f7afbdd1e5aba4cfd38b4e69bcd5445..0000000000000000000000000000000000000000
--- a/tb/tb_serpent_dcache/wave.do
+++ /dev/null
@@ -1,474 +0,0 @@
-onerror {resume}
-quietly WaveActivateNextPane {} 0
-add wave -noupdate /tb/KILL_RATE
-add wave -noupdate /tb/MEM_BYTES
-add wave -noupdate /tb/MEM_RAND_HIT_RATE
-add wave -noupdate /tb/MEM_RAND_INV_RATE
-add wave -noupdate /tb/MEM_WORDS
-add wave -noupdate /tb/NC_ADDR_BEGIN
-add wave -noupdate /tb/amo_ack_o
-add wave -noupdate /tb/amo_rand_en
-add wave -noupdate /tb/amo_req_i
-add wave -noupdate /tb/clk_i
-add wave -noupdate /tb/enable_i
-add wave -noupdate /tb/end_of_sim
-add wave -noupdate /tb/flush_ack_o
-add wave -noupdate /tb/flush_i
-add wave -noupdate /tb/inv_rand_en
-add wave -noupdate /tb/mem_array
-add wave -noupdate /tb/mem_data_ack_i
-add wave -noupdate /tb/mem_data_o
-add wave -noupdate /tb/mem_data_req_o
-add wave -noupdate /tb/mem_rand_en
-add wave -noupdate -expand /tb/mem_rtrn_i
-add wave -noupdate /tb/mem_rtrn_vld_i
-add wave -noupdate /tb/miss_o
-add wave -noupdate /tb/req_ports_i
-add wave -noupdate /tb/req_ports_o
-add wave -noupdate /tb/rst_ni
-add wave -noupdate /tb/seq_done
-add wave -noupdate /tb/seq_last
-add wave -noupdate /tb/seq_num_resp
-add wave -noupdate /tb/seq_run
-add wave -noupdate /tb/seq_type
-add wave -noupdate /tb/test_name
-add wave -noupdate /tb/wbuffer_empty_o
-add wave -noupdate -divider Programs
-add wave -noupdate -group Writeport /tb/i_tb_writeport/clk_i
-add wave -noupdate -group Writeport /tb/i_tb_writeport/rst_ni
-add wave -noupdate -group Writeport /tb/i_tb_writeport/req_rate_i
-add wave -noupdate -group Writeport /tb/i_tb_writeport/seq_type_i
-add wave -noupdate -group Writeport /tb/i_tb_writeport/seq_run_i
-add wave -noupdate -group Writeport /tb/i_tb_writeport/seq_num_vect_i
-add wave -noupdate -group Writeport /tb/i_tb_writeport/seq_last_i
-add wave -noupdate -group Writeport /tb/i_tb_writeport/dut_req_port_i
-add wave -noupdate -group Writeport /tb/i_tb_writeport/MEM_WORDS
-add wave -noupdate -group Writeport /tb/i_tb_writeport/RND_SEED
-add wave -noupdate -group Writeport /tb/i_tb_writeport/VERBOSE
-add wave -noupdate -group Writeport /tb/i_tb_writeport/test_name_i
-add wave -noupdate -group Writeport /tb/i_tb_writeport/paddr
-add wave -noupdate -group Writeport /tb/i_tb_writeport/seq_done_o
-add wave -noupdate -group Writeport /tb/i_tb_writeport/dut_req_port_o
-add wave -noupdate -group {Readport 0} /tb/i_tb_readport0/clk_i
-add wave -noupdate -group {Readport 0} /tb/i_tb_readport0/rst_ni
-add wave -noupdate -group {Readport 0} /tb/i_tb_readport0/seq_type_i
-add wave -noupdate -group {Readport 0} /tb/i_tb_readport0/seq_run_i
-add wave -noupdate -group {Readport 0} /tb/i_tb_readport0/seq_num_resp_i
-add wave -noupdate -group {Readport 0} /tb/i_tb_readport0/seq_last_i
-add wave -noupdate -group {Readport 0} /tb/i_tb_readport0/seq_done_o
-add wave -noupdate -group {Readport 0} -expand /tb/i_tb_readport0/dut_req_port_o
-add wave -noupdate -group {Readport 0} -expand /tb/i_tb_readport0/dut_req_port_i
-add wave -noupdate -group {Readport 0} /tb/i_tb_readport0/paddr
-add wave -noupdate -group {Readport 0} /tb/i_tb_readport0/seq_end_req
-add wave -noupdate -group {Readport 0} /tb/i_tb_readport0/seq_end_ack
-add wave -noupdate -group {Readport 0} /tb/i_tb_readport0/tag_q
-add wave -noupdate -group {Readport 0} /tb/i_tb_readport0/tag_vld_q
-add wave -noupdate -group {Readport 1} /tb/i_tb_readport1/clk_i
-add wave -noupdate -group {Readport 1} /tb/i_tb_readport1/rst_ni
-add wave -noupdate -group {Readport 1} /tb/i_tb_readport1/seq_type_i
-add wave -noupdate -group {Readport 1} /tb/i_tb_readport1/seq_run_i
-add wave -noupdate -group {Readport 1} /tb/i_tb_readport1/seq_num_resp_i
-add wave -noupdate -group {Readport 1} /tb/i_tb_readport1/seq_last_i
-add wave -noupdate -group {Readport 1} /tb/i_tb_readport1/seq_done_o
-add wave -noupdate -group {Readport 1} -expand /tb/i_tb_readport1/dut_req_port_o
-add wave -noupdate -group {Readport 1} -expand /tb/i_tb_readport1/dut_req_port_i
-add wave -noupdate -group {Readport 1} /tb/i_tb_readport1/paddr
-add wave -noupdate -group {Readport 1} /tb/i_tb_readport1/seq_end_req
-add wave -noupdate -group {Readport 1} /tb/i_tb_readport1/seq_end_ack
-add wave -noupdate -group {Readport 1} /tb/i_tb_readport1/tag_q
-add wave -noupdate -group {Readport 1} /tb/i_tb_readport1/tag_vld_q
-add wave -noupdate -group i_tb_mem /tb/i_tb_mem/clk_i
-add wave -noupdate -group i_tb_mem /tb/i_tb_mem/rst_ni
-add wave -noupdate -group i_tb_mem /tb/i_tb_mem/mem_rand_en_i
-add wave -noupdate -group i_tb_mem /tb/i_tb_mem/inv_rand_en_i
-add wave -noupdate -group i_tb_mem /tb/i_tb_mem/amo_rand_en_i
-add wave -noupdate -group i_tb_mem /tb/i_tb_mem/mem_data_req_i
-add wave -noupdate -group i_tb_mem /tb/i_tb_mem/mem_data_i
-add wave -noupdate -group i_tb_mem /tb/i_tb_mem/seq_last_i
-add wave -noupdate -group i_tb_mem /tb/i_tb_mem/check_en_i
-add wave -noupdate -group i_tb_mem /tb/i_tb_mem/commit_en_i
-add wave -noupdate -group i_tb_mem /tb/i_tb_mem/commit_be_i
-add wave -noupdate -group i_tb_mem /tb/i_tb_mem/commit_paddr_i
-add wave -noupdate -group i_tb_mem /tb/i_tb_mem/write_en_i
-add wave -noupdate -group i_tb_mem /tb/i_tb_mem/write_be_i
-add wave -noupdate -group i_tb_mem /tb/i_tb_mem/write_data_i
-add wave -noupdate -group i_tb_mem /tb/i_tb_mem/write_paddr_i
-add wave -noupdate -group i_tb_mem /tb/i_tb_mem/MEM_RAND_HIT_RATE
-add wave -noupdate -group i_tb_mem /tb/i_tb_mem/MEM_RAND_INV_RATE
-add wave -noupdate -group i_tb_mem /tb/i_tb_mem/MEM_WORDS
-add wave -noupdate -group i_tb_mem /tb/i_tb_mem/NC_ADDR_BEGIN
-add wave -noupdate -group i_tb_mem /tb/i_tb_mem/NC_ADDR_GE_LT
-add wave -noupdate -group i_tb_mem /tb/i_tb_mem/mem_ready_q
-add wave -noupdate -group i_tb_mem /tb/i_tb_mem/mem_inv_q
-add wave -noupdate -group i_tb_mem /tb/i_tb_mem/rand_addr_q
-add wave -noupdate -group i_tb_mem /tb/i_tb_mem/outfifo_data
-add wave -noupdate -group i_tb_mem /tb/i_tb_mem/outfifo_pop
-add wave -noupdate -group i_tb_mem /tb/i_tb_mem/outfifo_push
-add wave -noupdate -group i_tb_mem /tb/i_tb_mem/outfifo_full
-add wave -noupdate -group i_tb_mem /tb/i_tb_mem/outfifo_empty
-add wave -noupdate -group i_tb_mem /tb/i_tb_mem/infifo_data
-add wave -noupdate -group i_tb_mem /tb/i_tb_mem/infifo_pop
-add wave -noupdate -group i_tb_mem /tb/i_tb_mem/infifo_push
-add wave -noupdate -group i_tb_mem /tb/i_tb_mem/infifo_full
-add wave -noupdate -group i_tb_mem /tb/i_tb_mem/infifo_empty
-add wave -noupdate -group i_tb_mem /tb/i_tb_mem/initialized_q
-add wave -noupdate -group i_tb_mem /tb/i_tb_mem/write_en
-add wave -noupdate -group i_tb_mem -color Magenta /tb/i_tb_mem/mem_array_q
-add wave -noupdate -group i_tb_mem -color Magenta /tb/i_tb_mem/mem_array_shadow_q
-add wave -noupdate -group i_tb_mem -color Magenta /tb/i_tb_mem/mem_array_dirty_q
-add wave -noupdate -group i_tb_mem /tb/i_tb_mem/mem_rtrn_vld_o
-add wave -noupdate -group i_tb_mem /tb/i_tb_mem/mem_rtrn_o
-add wave -noupdate -group i_tb_mem /tb/i_tb_mem/mem_data_ack_o
-add wave -noupdate -group i_tb_mem /tb/i_tb_mem/mem_array_o
-add wave -noupdate -divider Modules
-add wave -noupdate -group i_dut /tb/i_dut/clk_i
-add wave -noupdate -group i_dut /tb/i_dut/rst_ni
-add wave -noupdate -group i_dut /tb/i_dut/enable_i
-add wave -noupdate -group i_dut /tb/i_dut/flush_i
-add wave -noupdate -group i_dut /tb/i_dut/amo_req_i
-add wave -noupdate -group i_dut /tb/i_dut/req_ports_i
-add wave -noupdate -group i_dut /tb/i_dut/mem_rtrn_vld_i
-add wave -noupdate -group i_dut /tb/i_dut/mem_rtrn_i
-add wave -noupdate -group i_dut /tb/i_dut/mem_data_ack_i
-add wave -noupdate -group i_dut /tb/i_dut/NC_ADDR_BEGIN
-add wave -noupdate -group i_dut /tb/i_dut/NC_ADDR_GE_LT
-add wave -noupdate -group i_dut /tb/i_dut/NUM_PORTS
-add wave -noupdate -group i_dut /tb/i_dut/cache_en
-add wave -noupdate -group i_dut /tb/i_dut/flush_en
-add wave -noupdate -group i_dut /tb/i_dut/wr_cl_vld
-add wave -noupdate -group i_dut /tb/i_dut/wr_cl_tag
-add wave -noupdate -group i_dut /tb/i_dut/wr_cl_idx
-add wave -noupdate -group i_dut /tb/i_dut/wr_cl_off
-add wave -noupdate -group i_dut /tb/i_dut/wr_cl_data
-add wave -noupdate -group i_dut /tb/i_dut/wr_cl_data_be
-add wave -noupdate -group i_dut /tb/i_dut/wr_vld_bits
-add wave -noupdate -group i_dut /tb/i_dut/wr_req
-add wave -noupdate -group i_dut /tb/i_dut/wr_ack
-add wave -noupdate -group i_dut /tb/i_dut/wr_idx
-add wave -noupdate -group i_dut /tb/i_dut/wr_off
-add wave -noupdate -group i_dut /tb/i_dut/wr_data
-add wave -noupdate -group i_dut /tb/i_dut/wr_data_be
-add wave -noupdate -group i_dut /tb/i_dut/miss_req
-add wave -noupdate -group i_dut /tb/i_dut/miss_ack
-add wave -noupdate -group i_dut /tb/i_dut/miss_nc
-add wave -noupdate -group i_dut /tb/i_dut/miss_we
-add wave -noupdate -group i_dut /tb/i_dut/miss_wdata
-add wave -noupdate -group i_dut /tb/i_dut/miss_paddr
-add wave -noupdate -group i_dut /tb/i_dut/miss_vld_bits
-add wave -noupdate -group i_dut /tb/i_dut/miss_size
-add wave -noupdate -group i_dut /tb/i_dut/miss_wr_id
-add wave -noupdate -group i_dut /tb/i_dut/miss_rtrn_vld
-add wave -noupdate -group i_dut /tb/i_dut/miss_rtrn_id
-add wave -noupdate -group i_dut /tb/i_dut/rd_req
-add wave -noupdate -group i_dut /tb/i_dut/rd_ack
-add wave -noupdate -group i_dut /tb/i_dut/rd_tag
-add wave -noupdate -group i_dut /tb/i_dut/rd_idx
-add wave -noupdate -group i_dut /tb/i_dut/rd_off
-add wave -noupdate -group i_dut /tb/i_dut/rd_data
-add wave -noupdate -group i_dut /tb/i_dut/rd_vld_bits
-add wave -noupdate -group i_dut /tb/i_dut/rd_hit_oh
-add wave -noupdate -group i_dut /tb/i_dut/wbuffer_data
-add wave -noupdate -group i_dut /tb/i_dut/flush_ack_o
-add wave -noupdate -group i_dut /tb/i_dut/miss_o
-add wave -noupdate -group i_dut /tb/i_dut/wbuffer_empty_o
-add wave -noupdate -group i_dut /tb/i_dut/amo_ack_o
-add wave -noupdate -group i_dut /tb/i_dut/req_ports_o
-add wave -noupdate -group i_dut /tb/i_dut/mem_data_req_o
-add wave -noupdate -group i_dut /tb/i_dut/mem_data_o
-add wave -noupdate -group i_wbuffer /tb/i_dut/i_serpent_dcache_wbuffer/clk_i
-add wave -noupdate -group i_wbuffer /tb/i_dut/i_serpent_dcache_wbuffer/rst_ni
-add wave -noupdate -group i_wbuffer /tb/i_dut/i_serpent_dcache_wbuffer/cache_en_i
-add wave -noupdate -group i_wbuffer -color Magenta /tb/i_dut/i_serpent_dcache_wbuffer/req_port_i
-add wave -noupdate -group i_wbuffer -color Magenta /tb/i_dut/i_serpent_dcache_wbuffer/req_port_o
-add wave -noupdate -group i_wbuffer /tb/i_dut/i_serpent_dcache_wbuffer/miss_ack_i
-add wave -noupdate -group i_wbuffer /tb/i_dut/i_serpent_dcache_wbuffer/miss_rtrn_vld_i
-add wave -noupdate -group i_wbuffer /tb/i_dut/i_serpent_dcache_wbuffer/miss_rtrn_id_i
-add wave -noupdate -group i_wbuffer /tb/i_dut/i_serpent_dcache_wbuffer/rd_ack_i
-add wave -noupdate -group i_wbuffer /tb/i_dut/i_serpent_dcache_wbuffer/rd_data_i
-add wave -noupdate -group i_wbuffer /tb/i_dut/i_serpent_dcache_wbuffer/rd_vld_bits_i
-add wave -noupdate -group i_wbuffer /tb/i_dut/i_serpent_dcache_wbuffer/rd_hit_oh_i
-add wave -noupdate -group i_wbuffer /tb/i_dut/i_serpent_dcache_wbuffer/wr_ack_i
-add wave -noupdate -group i_wbuffer /tb/i_dut/i_serpent_dcache_wbuffer/empty_o
-add wave -noupdate -group i_wbuffer /tb/i_dut/i_serpent_dcache_wbuffer/miss_paddr_o
-add wave -noupdate -group i_wbuffer /tb/i_dut/i_serpent_dcache_wbuffer/miss_req_o
-add wave -noupdate -group i_wbuffer /tb/i_dut/i_serpent_dcache_wbuffer/miss_we_o
-add wave -noupdate -group i_wbuffer /tb/i_dut/i_serpent_dcache_wbuffer/miss_wdata_o
-add wave -noupdate -group i_wbuffer /tb/i_dut/i_serpent_dcache_wbuffer/miss_vld_bits_o
-add wave -noupdate -group i_wbuffer /tb/i_dut/i_serpent_dcache_wbuffer/miss_nc_o
-add wave -noupdate -group i_wbuffer /tb/i_dut/i_serpent_dcache_wbuffer/miss_size_o
-add wave -noupdate -group i_wbuffer /tb/i_dut/i_serpent_dcache_wbuffer/miss_wr_id_o
-add wave -noupdate -group i_wbuffer /tb/i_dut/i_serpent_dcache_wbuffer/rd_tag_o
-add wave -noupdate -group i_wbuffer /tb/i_dut/i_serpent_dcache_wbuffer/rd_idx_o
-add wave -noupdate -group i_wbuffer /tb/i_dut/i_serpent_dcache_wbuffer/rd_off_o
-add wave -noupdate -group i_wbuffer /tb/i_dut/i_serpent_dcache_wbuffer/rd_req_o
-add wave -noupdate -group i_wbuffer /tb/i_dut/i_serpent_dcache_wbuffer/wr_req_o
-add wave -noupdate -group i_wbuffer /tb/i_dut/i_serpent_dcache_wbuffer/wr_idx_o
-add wave -noupdate -group i_wbuffer /tb/i_dut/i_serpent_dcache_wbuffer/wr_off_o
-add wave -noupdate -group i_wbuffer /tb/i_dut/i_serpent_dcache_wbuffer/wr_data_o
-add wave -noupdate -group i_wbuffer /tb/i_dut/i_serpent_dcache_wbuffer/wr_data_be_o
-add wave -noupdate -group i_wbuffer /tb/i_dut/i_serpent_dcache_wbuffer/wbuffer_data_o
-add wave -noupdate -group i_wbuffer /tb/i_dut/i_serpent_dcache_wbuffer/NC_ADDR_BEGIN
-add wave -noupdate -group i_wbuffer /tb/i_dut/i_serpent_dcache_wbuffer/NC_ADDR_GE_LT
-add wave -noupdate -group i_wbuffer /tb/i_dut/i_serpent_dcache_wbuffer/tx_stat_d
-add wave -noupdate -group i_wbuffer /tb/i_dut/i_serpent_dcache_wbuffer/tx_stat_q
-add wave -noupdate -group i_wbuffer /tb/i_dut/i_serpent_dcache_wbuffer/wbuffer_q
-add wave -noupdate -group i_wbuffer /tb/i_dut/i_serpent_dcache_wbuffer/wbuffer_d
-add wave -noupdate -group i_wbuffer /tb/i_dut/i_serpent_dcache_wbuffer/valid
-add wave -noupdate -group i_wbuffer -color Magenta /tb/i_dut/i_serpent_dcache_wbuffer/debug_paddr
-add wave -noupdate -group i_wbuffer /tb/i_dut/i_serpent_dcache_wbuffer/dirty
-add wave -noupdate -group i_wbuffer /tb/i_dut/i_serpent_dcache_wbuffer/tocheck
-add wave -noupdate -group i_wbuffer /tb/i_dut/i_serpent_dcache_wbuffer/wbuffer_hit_oh
-add wave -noupdate -group i_wbuffer /tb/i_dut/i_serpent_dcache_wbuffer/inval_hit
-add wave -noupdate -group i_wbuffer /tb/i_dut/i_serpent_dcache_wbuffer/bdirty
-add wave -noupdate -group i_wbuffer /tb/i_dut/i_serpent_dcache_wbuffer/next_ptr
-add wave -noupdate -group i_wbuffer /tb/i_dut/i_serpent_dcache_wbuffer/dirty_ptr
-add wave -noupdate -group i_wbuffer /tb/i_dut/i_serpent_dcache_wbuffer/hit_ptr
-add wave -noupdate -group i_wbuffer /tb/i_dut/i_serpent_dcache_wbuffer/wr_ptr
-add wave -noupdate -group i_wbuffer /tb/i_dut/i_serpent_dcache_wbuffer/check_ptr_d
-add wave -noupdate -group i_wbuffer /tb/i_dut/i_serpent_dcache_wbuffer/check_ptr_q
-add wave -noupdate -group i_wbuffer /tb/i_dut/i_serpent_dcache_wbuffer/rtrn_ptr
-add wave -noupdate -group i_wbuffer /tb/i_dut/i_serpent_dcache_wbuffer/tx_cnt_q
-add wave -noupdate -group i_wbuffer /tb/i_dut/i_serpent_dcache_wbuffer/tx_cnt_d
-add wave -noupdate -group i_wbuffer /tb/i_dut/i_serpent_dcache_wbuffer/tx_id_q
-add wave -noupdate -group i_wbuffer /tb/i_dut/i_serpent_dcache_wbuffer/tx_id_d
-add wave -noupdate -group i_wbuffer /tb/i_dut/i_serpent_dcache_wbuffer/rtrn_id
-add wave -noupdate -group i_wbuffer /tb/i_dut/i_serpent_dcache_wbuffer/bdirty_off
-add wave -noupdate -group i_wbuffer /tb/i_dut/i_serpent_dcache_wbuffer/tx_be
-add wave -noupdate -group i_wbuffer /tb/i_dut/i_serpent_dcache_wbuffer/wr_paddr
-add wave -noupdate -group i_wbuffer /tb/i_dut/i_serpent_dcache_wbuffer/rd_paddr
-add wave -noupdate -group i_wbuffer /tb/i_dut/i_serpent_dcache_wbuffer/check_en_d
-add wave -noupdate -group i_wbuffer /tb/i_dut/i_serpent_dcache_wbuffer/check_en_q
-add wave -noupdate -group i_wbuffer /tb/i_dut/i_serpent_dcache_wbuffer/full
-add wave -noupdate -group i_wbuffer /tb/i_dut/i_serpent_dcache_wbuffer/dirty_rd_en
-add wave -noupdate -group i_wbuffer /tb/i_dut/i_serpent_dcache_wbuffer/rdy
-add wave -noupdate -group i_wbuffer /tb/i_dut/i_serpent_dcache_wbuffer/rtrn_empty
-add wave -noupdate -group i_wbuffer /tb/i_dut/i_serpent_dcache_wbuffer/evict
-add wave -noupdate -group i_wbuffer /tb/i_dut/i_serpent_dcache_wbuffer/nc_pending_d
-add wave -noupdate -group i_wbuffer /tb/i_dut/i_serpent_dcache_wbuffer/nc_pending_q
-add wave -noupdate -group i_wbuffer /tb/i_dut/i_serpent_dcache_wbuffer/addr_is_nc
-add wave -noupdate -group i_missunit /tb/i_dut/i_serpent_dcache_missunit/clk_i
-add wave -noupdate -group i_missunit /tb/i_dut/i_serpent_dcache_missunit/rst_ni
-add wave -noupdate -group i_missunit /tb/i_dut/i_serpent_dcache_missunit/enable_i
-add wave -noupdate -group i_missunit /tb/i_dut/i_serpent_dcache_missunit/flush_i
-add wave -noupdate -group i_missunit /tb/i_dut/i_serpent_dcache_missunit/wbuffer_empty_i
-add wave -noupdate -group i_missunit /tb/i_dut/i_serpent_dcache_missunit/amo_req_i
-add wave -noupdate -group i_missunit -expand /tb/i_dut/i_serpent_dcache_missunit/miss_req_i
-add wave -noupdate -group i_missunit /tb/i_dut/i_serpent_dcache_missunit/miss_nc_i
-add wave -noupdate -group i_missunit /tb/i_dut/i_serpent_dcache_missunit/miss_we_i
-add wave -noupdate -group i_missunit /tb/i_dut/i_serpent_dcache_missunit/miss_wdata_i
-add wave -noupdate -group i_missunit /tb/i_dut/i_serpent_dcache_missunit/miss_paddr_i
-add wave -noupdate -group i_missunit /tb/i_dut/i_serpent_dcache_missunit/miss_vld_bits_i
-add wave -noupdate -group i_missunit /tb/i_dut/i_serpent_dcache_missunit/miss_size_i
-add wave -noupdate -group i_missunit /tb/i_dut/i_serpent_dcache_missunit/miss_wr_id_i
-add wave -noupdate -group i_missunit /tb/i_dut/i_serpent_dcache_missunit/mem_rtrn_vld_i
-add wave -noupdate -group i_missunit /tb/i_dut/i_serpent_dcache_missunit/mem_rtrn_i
-add wave -noupdate -group i_missunit /tb/i_dut/i_serpent_dcache_missunit/mem_data_ack_i
-add wave -noupdate -group i_missunit /tb/i_dut/i_serpent_dcache_missunit/flush_ack_o
-add wave -noupdate -group i_missunit /tb/i_dut/i_serpent_dcache_missunit/miss_o
-add wave -noupdate -group i_missunit /tb/i_dut/i_serpent_dcache_missunit/cache_en_o
-add wave -noupdate -group i_missunit /tb/i_dut/i_serpent_dcache_missunit/flush_en_o
-add wave -noupdate -group i_missunit /tb/i_dut/i_serpent_dcache_missunit/amo_ack_o
-add wave -noupdate -group i_missunit /tb/i_dut/i_serpent_dcache_missunit/miss_ack_o
-add wave -noupdate -group i_missunit /tb/i_dut/i_serpent_dcache_missunit/miss_replay_o
-add wave -noupdate -group i_missunit /tb/i_dut/i_serpent_dcache_missunit/miss_rtrn_vld_o
-add wave -noupdate -group i_missunit /tb/i_dut/i_serpent_dcache_missunit/miss_rtrn_id_o
-add wave -noupdate -group i_missunit /tb/i_dut/i_serpent_dcache_missunit/wr_cl_vld_o
-add wave -noupdate -group i_missunit /tb/i_dut/i_serpent_dcache_missunit/wr_cl_nc_o
-add wave -noupdate -group i_missunit /tb/i_dut/i_serpent_dcache_missunit/wr_cl_we_o
-add wave -noupdate -group i_missunit /tb/i_dut/i_serpent_dcache_missunit/wr_cl_tag_o
-add wave -noupdate -group i_missunit /tb/i_dut/i_serpent_dcache_missunit/wr_cl_idx_o
-add wave -noupdate -group i_missunit /tb/i_dut/i_serpent_dcache_missunit/wr_cl_off_o
-add wave -noupdate -group i_missunit /tb/i_dut/i_serpent_dcache_missunit/wr_cl_data_o
-add wave -noupdate -group i_missunit /tb/i_dut/i_serpent_dcache_missunit/wr_cl_data_be_o
-add wave -noupdate -group i_missunit /tb/i_dut/i_serpent_dcache_missunit/wr_vld_bits_o
-add wave -noupdate -group i_missunit /tb/i_dut/i_serpent_dcache_missunit/mem_data_req_o
-add wave -noupdate -group i_missunit /tb/i_dut/i_serpent_dcache_missunit/mem_data_o
-add wave -noupdate -group i_missunit /tb/i_dut/i_serpent_dcache_missunit/NUM_PORTS
-add wave -noupdate -group i_missunit /tb/i_dut/i_serpent_dcache_missunit/state_d
-add wave -noupdate -group i_missunit /tb/i_dut/i_serpent_dcache_missunit/state_q
-add wave -noupdate -group i_missunit /tb/i_dut/i_serpent_dcache_missunit/mshr_d
-add wave -noupdate -group i_missunit /tb/i_dut/i_serpent_dcache_missunit/mshr_q
-add wave -noupdate -group i_missunit /tb/i_dut/i_serpent_dcache_missunit/repl_way
-add wave -noupdate -group i_missunit /tb/i_dut/i_serpent_dcache_missunit/inv_way
-add wave -noupdate -group i_missunit /tb/i_dut/i_serpent_dcache_missunit/rnd_way
-add wave -noupdate -group i_missunit /tb/i_dut/i_serpent_dcache_missunit/mshr_vld_d
-add wave -noupdate -group i_missunit /tb/i_dut/i_serpent_dcache_missunit/mshr_vld_q
-add wave -noupdate -group i_missunit /tb/i_dut/i_serpent_dcache_missunit/mshr_allocate
-add wave -noupdate -group i_missunit /tb/i_dut/i_serpent_dcache_missunit/update_lfsr
-add wave -noupdate -group i_missunit /tb/i_dut/i_serpent_dcache_missunit/all_ways_valid
-add wave -noupdate -group i_missunit /tb/i_dut/i_serpent_dcache_missunit/enable_d
-add wave -noupdate -group i_missunit /tb/i_dut/i_serpent_dcache_missunit/enable_q
-add wave -noupdate -group i_missunit /tb/i_dut/i_serpent_dcache_missunit/flush_ack_d
-add wave -noupdate -group i_missunit /tb/i_dut/i_serpent_dcache_missunit/flush_ack_q
-add wave -noupdate -group i_missunit /tb/i_dut/i_serpent_dcache_missunit/amo_sel
-add wave -noupdate -group i_missunit /tb/i_dut/i_serpent_dcache_missunit/flush_done
-add wave -noupdate -group i_missunit /tb/i_dut/i_serpent_dcache_missunit/mask_reads
-add wave -noupdate -group i_missunit /tb/i_dut/i_serpent_dcache_missunit/miss_is_write
-add wave -noupdate -group i_missunit /tb/i_dut/i_serpent_dcache_missunit/amo_data
-add wave -noupdate -group i_missunit /tb/i_dut/i_serpent_dcache_missunit/miss_port_idx
-add wave -noupdate -group i_missunit /tb/i_dut/i_serpent_dcache_missunit/cnt_d
-add wave -noupdate -group i_missunit /tb/i_dut/i_serpent_dcache_missunit/cnt_q
-add wave -noupdate -group i_missunit /tb/i_dut/i_serpent_dcache_missunit/miss_req
-add wave -noupdate -group i_missunit /tb/i_dut/i_serpent_dcache_missunit/inv_vld
-add wave -noupdate -group i_missunit /tb/i_dut/i_serpent_dcache_missunit/cl_write_en
-add wave -noupdate -group i_missunit /tb/i_dut/i_serpent_dcache_missunit/load_ack
-add wave -noupdate -group i_missunit /tb/i_dut/i_serpent_dcache_missunit/store_ack
-add wave -noupdate -group i_missunit /tb/i_dut/i_serpent_dcache_missunit/amo_ack
-add wave -noupdate -expand -group i_mem /tb/i_dut/i_serpent_dcache_mem/clk_i
-add wave -noupdate -expand -group i_mem /tb/i_dut/i_serpent_dcache_mem/rst_ni
-add wave -noupdate -expand -group i_mem /tb/i_dut/i_serpent_dcache_mem/rd_tag_i
-add wave -noupdate -expand -group i_mem /tb/i_dut/i_serpent_dcache_mem/rd_idx_i
-add wave -noupdate -expand -group i_mem /tb/i_dut/i_serpent_dcache_mem/rd_off_i
-add wave -noupdate -expand -group i_mem /tb/i_dut/i_serpent_dcache_mem/rd_req_i
-add wave -noupdate -expand -group i_mem /tb/i_dut/i_serpent_dcache_mem/wr_cl_vld_i
-add wave -noupdate -expand -group i_mem /tb/i_dut/i_serpent_dcache_mem/wr_cl_tag_i
-add wave -noupdate -expand -group i_mem /tb/i_dut/i_serpent_dcache_mem/wr_cl_idx_i
-add wave -noupdate -expand -group i_mem /tb/i_dut/i_serpent_dcache_mem/wr_cl_off_i
-add wave -noupdate -expand -group i_mem /tb/i_dut/i_serpent_dcache_mem/wr_cl_data_i
-add wave -noupdate -expand -group i_mem /tb/i_dut/i_serpent_dcache_mem/wr_cl_data_be_i
-add wave -noupdate -expand -group i_mem -expand /tb/i_dut/i_serpent_dcache_mem/wr_vld_bits_i
-add wave -noupdate -expand -group i_mem /tb/i_dut/i_serpent_dcache_mem/wr_req_i
-add wave -noupdate -expand -group i_mem /tb/i_dut/i_serpent_dcache_mem/wr_idx_i
-add wave -noupdate -expand -group i_mem /tb/i_dut/i_serpent_dcache_mem/wr_off_i
-add wave -noupdate -expand -group i_mem /tb/i_dut/i_serpent_dcache_mem/wr_data_i
-add wave -noupdate -expand -group i_mem /tb/i_dut/i_serpent_dcache_mem/wr_data_be_i
-add wave -noupdate -expand -group i_mem /tb/i_dut/i_serpent_dcache_mem/wbuffer_data_i
-add wave -noupdate -expand -group i_mem /tb/i_dut/i_serpent_dcache_mem/rd_ack_o
-add wave -noupdate -expand -group i_mem /tb/i_dut/i_serpent_dcache_mem/rd_vld_bits_o
-add wave -noupdate -expand -group i_mem /tb/i_dut/i_serpent_dcache_mem/rd_hit_oh_o
-add wave -noupdate -expand -group i_mem /tb/i_dut/i_serpent_dcache_mem/rd_data_o
-add wave -noupdate -expand -group i_mem /tb/i_dut/i_serpent_dcache_mem/wr_ack_o
-add wave -noupdate -expand -group i_mem /tb/i_dut/i_serpent_dcache_mem/NUM_PORTS
-add wave -noupdate -expand -group i_mem /tb/i_dut/i_serpent_dcache_mem/bank_req
-add wave -noupdate -expand -group i_mem /tb/i_dut/i_serpent_dcache_mem/bank_we
-add wave -noupdate -expand -group i_mem /tb/i_dut/i_serpent_dcache_mem/bank_be
-add wave -noupdate -expand -group i_mem /tb/i_dut/i_serpent_dcache_mem/bank_idx
-add wave -noupdate -expand -group i_mem /tb/i_dut/i_serpent_dcache_mem/bank_idx_d
-add wave -noupdate -expand -group i_mem /tb/i_dut/i_serpent_dcache_mem/bank_idx_q
-add wave -noupdate -expand -group i_mem /tb/i_dut/i_serpent_dcache_mem/bank_off_d
-add wave -noupdate -expand -group i_mem /tb/i_dut/i_serpent_dcache_mem/bank_off_q
-add wave -noupdate -expand -group i_mem /tb/i_dut/i_serpent_dcache_mem/bank_wdata
-add wave -noupdate -expand -group i_mem /tb/i_dut/i_serpent_dcache_mem/bank_rdata
-add wave -noupdate -expand -group i_mem /tb/i_dut/i_serpent_dcache_mem/rdata_cl
-add wave -noupdate -expand -group i_mem /tb/i_dut/i_serpent_dcache_mem/vld_req
-add wave -noupdate -expand -group i_mem /tb/i_dut/i_serpent_dcache_mem/vld_we
-add wave -noupdate -expand -group i_mem /tb/i_dut/i_serpent_dcache_mem/vld_wdata
-add wave -noupdate -expand -group i_mem /tb/i_dut/i_serpent_dcache_mem/tag_rdata
-add wave -noupdate -expand -group i_mem /tb/i_dut/i_serpent_dcache_mem/vld_addr
-add wave -noupdate -expand -group i_mem /tb/i_dut/i_serpent_dcache_mem/vld_sel_d
-add wave -noupdate -expand -group i_mem /tb/i_dut/i_serpent_dcache_mem/vld_sel_q
-add wave -noupdate -expand -group i_mem /tb/i_dut/i_serpent_dcache_mem/wbuffer_hit_oh
-add wave -noupdate -expand -group i_mem /tb/i_dut/i_serpent_dcache_mem/wbuffer_be
-add wave -noupdate -expand -group i_mem /tb/i_dut/i_serpent_dcache_mem/wbuffer_rdata
-add wave -noupdate -expand -group i_mem /tb/i_dut/i_serpent_dcache_mem/rdata
-add wave -noupdate -expand -group i_mem /tb/i_dut/i_serpent_dcache_mem/wbuffer_cmp_addr
-add wave -noupdate -expand -group i_mem /tb/i_dut/i_serpent_dcache_mem/wbuffer_bvalid
-add wave -noupdate -expand -group i_mem /tb/i_dut/i_serpent_dcache_mem/wbuffer_data
-add wave -noupdate -expand -group i_mem /tb/i_dut/i_serpent_dcache_mem/vld_tag_rdata
-add wave -noupdate -group i_ctrl0 {/tb/i_dut/genblk1[0]/i_serpent_dcache_ctrl/clk_i}
-add wave -noupdate -group i_ctrl0 {/tb/i_dut/genblk1[0]/i_serpent_dcache_ctrl/rst_ni}
-add wave -noupdate -group i_ctrl0 {/tb/i_dut/genblk1[0]/i_serpent_dcache_ctrl/flush_i}
-add wave -noupdate -group i_ctrl0 {/tb/i_dut/genblk1[0]/i_serpent_dcache_ctrl/cache_en_i}
-add wave -noupdate -group i_ctrl0 -expand {/tb/i_dut/genblk1[0]/i_serpent_dcache_ctrl/req_port_i}
-add wave -noupdate -group i_ctrl0 {/tb/i_dut/genblk1[0]/i_serpent_dcache_ctrl/miss_ack_i}
-add wave -noupdate -group i_ctrl0 {/tb/i_dut/genblk1[0]/i_serpent_dcache_ctrl/miss_replay_i}
-add wave -noupdate -group i_ctrl0 {/tb/i_dut/genblk1[0]/i_serpent_dcache_ctrl/miss_rtrn_vld_i}
-add wave -noupdate -group i_ctrl0 {/tb/i_dut/genblk1[0]/i_serpent_dcache_ctrl/rd_ack_i}
-add wave -noupdate -group i_ctrl0 {/tb/i_dut/genblk1[0]/i_serpent_dcache_ctrl/rd_data_i}
-add wave -noupdate -group i_ctrl0 {/tb/i_dut/genblk1[0]/i_serpent_dcache_ctrl/rd_vld_bits_i}
-add wave -noupdate -group i_ctrl0 {/tb/i_dut/genblk1[0]/i_serpent_dcache_ctrl/rd_hit_oh_i}
-add wave -noupdate -group i_ctrl0 {/tb/i_dut/genblk1[0]/i_serpent_dcache_ctrl/req_port_o}
-add wave -noupdate -group i_ctrl0 {/tb/i_dut/genblk1[0]/i_serpent_dcache_ctrl/miss_req_o}
-add wave -noupdate -group i_ctrl0 {/tb/i_dut/genblk1[0]/i_serpent_dcache_ctrl/miss_we_o}
-add wave -noupdate -group i_ctrl0 {/tb/i_dut/genblk1[0]/i_serpent_dcache_ctrl/miss_wdata_o}
-add wave -noupdate -group i_ctrl0 {/tb/i_dut/genblk1[0]/i_serpent_dcache_ctrl/miss_vld_bits_o}
-add wave -noupdate -group i_ctrl0 {/tb/i_dut/genblk1[0]/i_serpent_dcache_ctrl/miss_paddr_o}
-add wave -noupdate -group i_ctrl0 {/tb/i_dut/genblk1[0]/i_serpent_dcache_ctrl/miss_nc_o}
-add wave -noupdate -group i_ctrl0 {/tb/i_dut/genblk1[0]/i_serpent_dcache_ctrl/miss_size_o}
-add wave -noupdate -group i_ctrl0 {/tb/i_dut/genblk1[0]/i_serpent_dcache_ctrl/miss_wr_id_o}
-add wave -noupdate -group i_ctrl0 {/tb/i_dut/genblk1[0]/i_serpent_dcache_ctrl/rd_tag_o}
-add wave -noupdate -group i_ctrl0 {/tb/i_dut/genblk1[0]/i_serpent_dcache_ctrl/rd_idx_o}
-add wave -noupdate -group i_ctrl0 {/tb/i_dut/genblk1[0]/i_serpent_dcache_ctrl/rd_off_o}
-add wave -noupdate -group i_ctrl0 {/tb/i_dut/genblk1[0]/i_serpent_dcache_ctrl/rd_req_o}
-add wave -noupdate -group i_ctrl0 {/tb/i_dut/genblk1[0]/i_serpent_dcache_ctrl/NC_ADDR_BEGIN}
-add wave -noupdate -group i_ctrl0 {/tb/i_dut/genblk1[0]/i_serpent_dcache_ctrl/NC_ADDR_GE_LT}
-add wave -noupdate -group i_ctrl0 {/tb/i_dut/genblk1[0]/i_serpent_dcache_ctrl/state_d}
-add wave -noupdate -group i_ctrl0 {/tb/i_dut/genblk1[0]/i_serpent_dcache_ctrl/state_q}
-add wave -noupdate -group i_ctrl0 {/tb/i_dut/genblk1[0]/i_serpent_dcache_ctrl/address_tag_d}
-add wave -noupdate -group i_ctrl0 {/tb/i_dut/genblk1[0]/i_serpent_dcache_ctrl/address_tag_q}
-add wave -noupdate -group i_ctrl0 {/tb/i_dut/genblk1[0]/i_serpent_dcache_ctrl/address_idx_d}
-add wave -noupdate -group i_ctrl0 {/tb/i_dut/genblk1[0]/i_serpent_dcache_ctrl/address_idx_q}
-add wave -noupdate -group i_ctrl0 {/tb/i_dut/genblk1[0]/i_serpent_dcache_ctrl/address_off_d}
-add wave -noupdate -group i_ctrl0 {/tb/i_dut/genblk1[0]/i_serpent_dcache_ctrl/address_off_q}
-add wave -noupdate -group i_ctrl0 {/tb/i_dut/genblk1[0]/i_serpent_dcache_ctrl/vld_data_d}
-add wave -noupdate -group i_ctrl0 {/tb/i_dut/genblk1[0]/i_serpent_dcache_ctrl/vld_data_q}
-add wave -noupdate -group i_ctrl0 {/tb/i_dut/genblk1[0]/i_serpent_dcache_ctrl/save_tag}
-add wave -noupdate -group i_ctrl0 {/tb/i_dut/genblk1[0]/i_serpent_dcache_ctrl/rd_req_d}
-add wave -noupdate -group i_ctrl0 {/tb/i_dut/genblk1[0]/i_serpent_dcache_ctrl/rd_req_q}
-add wave -noupdate -group i_ctrl0 {/tb/i_dut/genblk1[0]/i_serpent_dcache_ctrl/data_size_d}
-add wave -noupdate -group i_ctrl0 {/tb/i_dut/genblk1[0]/i_serpent_dcache_ctrl/data_size_q}
-add wave -noupdate -group i_ctrl1 {/tb/i_dut/genblk1[1]/i_serpent_dcache_ctrl/clk_i}
-add wave -noupdate -group i_ctrl1 {/tb/i_dut/genblk1[1]/i_serpent_dcache_ctrl/rst_ni}
-add wave -noupdate -group i_ctrl1 {/tb/i_dut/genblk1[1]/i_serpent_dcache_ctrl/flush_i}
-add wave -noupdate -group i_ctrl1 {/tb/i_dut/genblk1[1]/i_serpent_dcache_ctrl/cache_en_i}
-add wave -noupdate -group i_ctrl1 {/tb/i_dut/genblk1[1]/i_serpent_dcache_ctrl/req_port_i}
-add wave -noupdate -group i_ctrl1 {/tb/i_dut/genblk1[1]/i_serpent_dcache_ctrl/miss_ack_i}
-add wave -noupdate -group i_ctrl1 {/tb/i_dut/genblk1[1]/i_serpent_dcache_ctrl/miss_replay_i}
-add wave -noupdate -group i_ctrl1 {/tb/i_dut/genblk1[1]/i_serpent_dcache_ctrl/miss_rtrn_vld_i}
-add wave -noupdate -group i_ctrl1 {/tb/i_dut/genblk1[1]/i_serpent_dcache_ctrl/rd_ack_i}
-add wave -noupdate -group i_ctrl1 {/tb/i_dut/genblk1[1]/i_serpent_dcache_ctrl/rd_data_i}
-add wave -noupdate -group i_ctrl1 {/tb/i_dut/genblk1[1]/i_serpent_dcache_ctrl/rd_vld_bits_i}
-add wave -noupdate -group i_ctrl1 {/tb/i_dut/genblk1[1]/i_serpent_dcache_ctrl/rd_hit_oh_i}
-add wave -noupdate -group i_ctrl1 {/tb/i_dut/genblk1[1]/i_serpent_dcache_ctrl/req_port_o}
-add wave -noupdate -group i_ctrl1 {/tb/i_dut/genblk1[1]/i_serpent_dcache_ctrl/miss_req_o}
-add wave -noupdate -group i_ctrl1 {/tb/i_dut/genblk1[1]/i_serpent_dcache_ctrl/miss_we_o}
-add wave -noupdate -group i_ctrl1 {/tb/i_dut/genblk1[1]/i_serpent_dcache_ctrl/miss_wdata_o}
-add wave -noupdate -group i_ctrl1 {/tb/i_dut/genblk1[1]/i_serpent_dcache_ctrl/miss_vld_bits_o}
-add wave -noupdate -group i_ctrl1 {/tb/i_dut/genblk1[1]/i_serpent_dcache_ctrl/miss_paddr_o}
-add wave -noupdate -group i_ctrl1 {/tb/i_dut/genblk1[1]/i_serpent_dcache_ctrl/miss_nc_o}
-add wave -noupdate -group i_ctrl1 {/tb/i_dut/genblk1[1]/i_serpent_dcache_ctrl/miss_size_o}
-add wave -noupdate -group i_ctrl1 {/tb/i_dut/genblk1[1]/i_serpent_dcache_ctrl/miss_wr_id_o}
-add wave -noupdate -group i_ctrl1 {/tb/i_dut/genblk1[1]/i_serpent_dcache_ctrl/rd_tag_o}
-add wave -noupdate -group i_ctrl1 {/tb/i_dut/genblk1[1]/i_serpent_dcache_ctrl/rd_idx_o}
-add wave -noupdate -group i_ctrl1 {/tb/i_dut/genblk1[1]/i_serpent_dcache_ctrl/rd_off_o}
-add wave -noupdate -group i_ctrl1 {/tb/i_dut/genblk1[1]/i_serpent_dcache_ctrl/rd_req_o}
-add wave -noupdate -group i_ctrl1 {/tb/i_dut/genblk1[1]/i_serpent_dcache_ctrl/NC_ADDR_BEGIN}
-add wave -noupdate -group i_ctrl1 {/tb/i_dut/genblk1[1]/i_serpent_dcache_ctrl/NC_ADDR_GE_LT}
-add wave -noupdate -group i_ctrl1 {/tb/i_dut/genblk1[1]/i_serpent_dcache_ctrl/state_d}
-add wave -noupdate -group i_ctrl1 {/tb/i_dut/genblk1[1]/i_serpent_dcache_ctrl/state_q}
-add wave -noupdate -group i_ctrl1 {/tb/i_dut/genblk1[1]/i_serpent_dcache_ctrl/address_tag_d}
-add wave -noupdate -group i_ctrl1 {/tb/i_dut/genblk1[1]/i_serpent_dcache_ctrl/address_tag_q}
-add wave -noupdate -group i_ctrl1 {/tb/i_dut/genblk1[1]/i_serpent_dcache_ctrl/address_idx_d}
-add wave -noupdate -group i_ctrl1 {/tb/i_dut/genblk1[1]/i_serpent_dcache_ctrl/address_idx_q}
-add wave -noupdate -group i_ctrl1 {/tb/i_dut/genblk1[1]/i_serpent_dcache_ctrl/address_off_d}
-add wave -noupdate -group i_ctrl1 {/tb/i_dut/genblk1[1]/i_serpent_dcache_ctrl/address_off_q}
-add wave -noupdate -group i_ctrl1 {/tb/i_dut/genblk1[1]/i_serpent_dcache_ctrl/vld_data_d}
-add wave -noupdate -group i_ctrl1 {/tb/i_dut/genblk1[1]/i_serpent_dcache_ctrl/vld_data_q}
-add wave -noupdate -group i_ctrl1 {/tb/i_dut/genblk1[1]/i_serpent_dcache_ctrl/save_tag}
-add wave -noupdate -group i_ctrl1 {/tb/i_dut/genblk1[1]/i_serpent_dcache_ctrl/rd_req_d}
-add wave -noupdate -group i_ctrl1 {/tb/i_dut/genblk1[1]/i_serpent_dcache_ctrl/rd_req_q}
-add wave -noupdate -group i_ctrl1 {/tb/i_dut/genblk1[1]/i_serpent_dcache_ctrl/data_size_d}
-add wave -noupdate -group i_ctrl1 {/tb/i_dut/genblk1[1]/i_serpent_dcache_ctrl/data_size_q}
-TreeUpdate [SetDefaultTree]
-quietly WaveActivateNextPane
-add wave -noupdate {/tb/i_tb_mem/mem_array_q[6741]}
-add wave -noupdate {/tb/i_tb_mem/mem_array_shadow_q[6741]}
-add wave -noupdate {/tb/i_tb_mem/mem_array_dirty_q[6741]}
-TreeUpdate [SetDefaultTree]
-WaveRestoreCursors {{Cursor 1} {31432807547 ps} 0} {{Cursor 2} {29040000 ps} 0} {{Cursor 3} {1027790000 ps} 0}
-quietly wave cursor active 2
-configure wave -namecolwidth 375
-configure wave -valuecolwidth 224
-configure wave -justifyvalue left
-configure wave -signalnamewidth 1
-configure wave -snapdistance 10
-configure wave -datasetprefix 0
-configure wave -rowmargin 4
-configure wave -childrowmargin 2
-configure wave -gridoffset 0
-configure wave -gridperiod 1
-configure wave -griddelta 40
-configure wave -timeline 0
-configure wave -timelineunits ps
-update
-WaveRestoreZoom {0 ps} {103267500 ps}
diff --git a/tb/tb_serpent_dcache/.gitignore b/tb/tb_wt_dcache/.gitignore
similarity index 100%
rename from tb/tb_serpent_dcache/.gitignore
rename to tb/tb_wt_dcache/.gitignore
diff --git a/tb/tb_serpent_dcache/Makefile b/tb/tb_wt_dcache/Makefile
similarity index 100%
rename from tb/tb_serpent_dcache/Makefile
rename to tb/tb_wt_dcache/Makefile
diff --git a/tb/tb_serpent_dcache/hdl/tb.sv b/tb/tb_wt_dcache/hdl/tb.sv
similarity index 93%
rename from tb/tb_serpent_dcache/hdl/tb.sv
rename to tb/tb_wt_dcache/hdl/tb.sv
index 9c0a388e0fb5f305f54077603bc6666280305a05..b1729c0f4555a39a97019e09582da9aa33db6011 100644
--- a/tb/tb_serpent_dcache/hdl/tb.sv
+++ b/tb/tb_wt_dcache/hdl/tb.sv
@@ -24,7 +24,7 @@
 `include "tb.svh"
 
 import ariane_pkg::*;
-import serpent_cache_pkg::*;
+import wt_cache_pkg::*;
 import tb_pkg::*;
 
 module tb;
@@ -51,6 +51,10 @@ module tb;
 
   parameter Verbose           = 0;
 
+  // number of vectors per test
+  parameter nReadVectors      = 20000;
+  parameter nWriteVectors     = 20000;
+
 ///////////////////////////////////////////////////////////////////////////////
 // MUT signal declarations
 ///////////////////////////////////////////////////////////////////////////////
@@ -199,9 +203,10 @@ module tb;
 // MUT
 ///////////////////////////////////////////////////////////////////////////////
 
-  serpent_dcache  #(
-    .CachedAddrBeg ( CachedAddrBeg ),
-    .CachedAddrEnd ( CachedAddrEnd )
+  wt_dcache  #(
+    .CachedAddrBeg     ( CachedAddrBeg ),
+    .CachedAddrEnd     ( CachedAddrEnd ),
+    .Axi64BitCompliant ( 1'b1          )
   ) i_dut (
     .clk_i           ( clk_i           ),
     .rst_ni          ( rst_ni          ),
@@ -226,12 +231,12 @@ module tb;
 ///////////////////////////////////////////////////////////////////////////////
 
   // get actual paddr from read controllers
-  assign act_paddr[0] = {i_dut.genblk1[0].i_serpent_dcache_ctrl.address_tag_d,
-                         i_dut.genblk1[0].i_serpent_dcache_ctrl.address_idx_q,
-                         i_dut.genblk1[0].i_serpent_dcache_ctrl.address_off_q};
-  assign act_paddr[1] = {i_dut.genblk1[1].i_serpent_dcache_ctrl.address_tag_d,
-                         i_dut.genblk1[1].i_serpent_dcache_ctrl.address_idx_q,
-                         i_dut.genblk1[1].i_serpent_dcache_ctrl.address_off_q};
+  assign act_paddr[0] = {i_dut.genblk1[0].i_wt_dcache_ctrl.address_tag_d,
+                         i_dut.genblk1[0].i_wt_dcache_ctrl.address_idx_q,
+                         i_dut.genblk1[0].i_wt_dcache_ctrl.address_off_q};
+  assign act_paddr[1] = {i_dut.genblk1[1].i_wt_dcache_ctrl.address_tag_d,
+                         i_dut.genblk1[1].i_wt_dcache_ctrl.address_idx_q,
+                         i_dut.genblk1[1].i_wt_dcache_ctrl.address_off_q};
 
   // generate fifo queues for expected responses
   generate
@@ -356,9 +361,9 @@ module tb;
   assign write_be    = req_ports_i[2].data_be;
 
   // generate write buffer commit signals based on internal eviction status
-  assign commit_be    = i_dut.i_serpent_dcache_wbuffer.wr_data_be_o;
-  assign commit_paddr = i_dut.i_serpent_dcache_wbuffer.wr_paddr;
-  assign commit_en    = i_dut.i_serpent_dcache_wbuffer.evict;
+  assign commit_be    = i_dut.i_wt_dcache_wbuffer.wr_data_be_o;
+  assign commit_paddr = i_dut.i_wt_dcache_wbuffer.wr_paddr;
+  assign commit_en    = i_dut.i_wt_dcache_wbuffer.evict;
 
   // TODO: implement AMO agent
   assign amo_req_i.req       = '0;
@@ -425,7 +430,7 @@ module tb;
     enable_i     = 0;
     seq_type     = '{default: RANDOM_SEQ};
     req_rate     = '{default: 7'd50};
-    runSeq(10000);
+    runSeq(nReadVectors);
     flushCache();
     memCheck();
     ///////////////////////////////////////////////
@@ -434,7 +439,7 @@ module tb;
     enable_i     = 0;
     seq_type     = '{default: LINEAR_SEQ};
     req_rate     = '{default: 7'd50};
-    runSeq(10000);
+    runSeq(nReadVectors);
     flushCache();
     memCheck();
     ///////////////////////////////////////////////
@@ -443,7 +448,7 @@ module tb;
     enable_i     = 1;
     seq_type     = '{default: RANDOM_SEQ};
     req_rate     = '{default: 7'd50};
-    runSeq(10000);
+    runSeq(nReadVectors);
     flushCache();
     memCheck();
     ///////////////////////////////////////////////
@@ -452,7 +457,7 @@ module tb;
     enable_i     = 1;
     seq_type     = '{default: LINEAR_SEQ};
     req_rate     = '{default: 7'd50};
-    runSeq(10000);
+    runSeq(nReadVectors);
     flushCache();
     memCheck();
     ///////////////////////////////////////////////
@@ -463,7 +468,7 @@ module tb;
     mem_rand_en  = 1;
     seq_type     = '{default: RANDOM_SEQ};
     req_rate     = '{default: 7'd50};
-    runSeq(10000);
+    runSeq(nReadVectors);
     flushCache();
     memCheck();
     ///////////////////////////////////////////////
@@ -474,7 +479,7 @@ module tb;
     mem_rand_en  = 1;
     seq_type     = '{default: LINEAR_SEQ};
     req_rate     = '{default: 7'd50};
-    runSeq(10000);
+    runSeq(nReadVectors);
     flushCache();
     memCheck();
     ///////////////////////////////////////////////
@@ -486,7 +491,7 @@ module tb;
     inv_rand_en  = 1;
     seq_type     = '{default: RANDOM_SEQ};
     req_rate     = '{default: 7'd50};
-    runSeq(10000);
+    runSeq(nReadVectors);
     flushCache();
     memCheck();
     ///////////////////////////////////////////////
@@ -498,7 +503,7 @@ module tb;
     inv_rand_en  = 0;
     seq_type     = '{default: RANDOM_SEQ};
     req_rate     = '{default: 7'd25};
-    runSeq(10000,10000);
+    runSeq(nReadVectors,nWriteVectors);
     flushCache();
     memCheck();
     ///////////////////////////////////////////////
@@ -510,7 +515,7 @@ module tb;
     inv_rand_en  = 0;
     seq_type     = '{default: RANDOM_SEQ};
     req_rate     = '{default: 7'd25};
-    runSeq(10000,20000);// last sequence flag, terminates agents
+    runSeq(nReadVectors,2*nWriteVectors);
     flushCache();
     memCheck();
     ///////////////////////////////////////////////
@@ -522,7 +527,7 @@ module tb;
     inv_rand_en  = 1;
     seq_type     = '{default: RANDOM_SEQ};
     req_rate     = '{default: 7'd25};
-    runSeq(10000,20000);
+    runSeq(nReadVectors,2*nWriteVectors);
     flushCache();
     memCheck();
     ///////////////////////////////////////////////
@@ -534,7 +539,7 @@ module tb;
     inv_rand_en  = 0;
     seq_type     = '{LINEAR_SEQ, IDLE_SEQ, IDLE_SEQ};
     req_rate     = '{100, 0, 0};
-    runSeq(0,5000);
+    runSeq(0,nWriteVectors);
     flushCache();
     memCheck();
     ///////////////////////////////////////////////
@@ -560,7 +565,7 @@ module tb;
     inv_rand_en  = 0;
     seq_type     = '{BURST_SEQ, RANDOM_SEQ, RANDOM_SEQ};
     req_rate     = '{75, 0, 0};
-    runSeq(0,5000,0);
+    runSeq(0,nWriteVectors);
     flushCache();
     memCheck();
     ///////////////////////////////////////////////
@@ -572,7 +577,7 @@ module tb;
     inv_rand_en  = 1;
     seq_type     = '{BURST_SEQ, IDLE_SEQ, IDLE_SEQ};
     req_rate     = '{75, 0, 0};
-    runSeq(0,5000);
+    runSeq(0,nWriteVectors);
     flushCache();
     memCheck();
     ///////////////////////////////////////////////
@@ -584,7 +589,7 @@ module tb;
     inv_rand_en  = 1;
     seq_type     = '{RANDOM_SEQ, RANDOM_SEQ, RANDOM_SEQ};
     req_rate     = '{default:25};
-    runSeq(5000,5000);
+    runSeq(nReadVectors,nWriteVectors);
     flushCache();
     memCheck();
     ///////////////////////////////////////////////
@@ -596,7 +601,7 @@ module tb;
     inv_rand_en  = 0;
     seq_type     = '{WRAP_SEQ, IDLE_SEQ, WRAP_SEQ};
     req_rate     = '{100,0,20};
-    runSeq(5000,5000);
+    runSeq(nReadVectors,nWriteVectors);
     flushCache();
     memCheck();
     ///////////////////////////////////////////////
@@ -609,7 +614,7 @@ module tb;
     flush_rand_en = 1;
     seq_type      = '{RANDOM_SEQ, RANDOM_SEQ, RANDOM_SEQ};
     req_rate      = '{default:25};
-    runSeq(5000,5000,1);// last sequence flag, terminates agents
+    runSeq(nReadVectors,nWriteVectors,1);// last sequence flag, terminates agents
     flushCache();
     memCheck();
     ///////////////////////////////////////////////
diff --git a/tb/tb_serpent_dcache/hdl/tb_mem.sv b/tb/tb_wt_dcache/hdl/tb_mem.sv
similarity index 99%
rename from tb/tb_serpent_dcache/hdl/tb_mem.sv
rename to tb/tb_wt_dcache/hdl/tb_mem.sv
index 8c57de9689b0a2fc0c019d03d91cbccb0a4b03a3..3f1ba0b4d53511a66b74cf1aa15fa70a7c1e6c56 100644
--- a/tb/tb_serpent_dcache/hdl/tb_mem.sv
+++ b/tb/tb_wt_dcache/hdl/tb_mem.sv
@@ -17,7 +17,7 @@
 `include "tb.svh"
 
 import ariane_pkg::*;
-import serpent_cache_pkg::*;
+import wt_cache_pkg::*;
 import tb_pkg::*;
 
 module tb_mem #(
diff --git a/tb/tb_serpent_dcache/hdl/tb_pkg.sv b/tb/tb_wt_dcache/hdl/tb_pkg.sv
similarity index 100%
rename from tb/tb_serpent_dcache/hdl/tb_pkg.sv
rename to tb/tb_wt_dcache/hdl/tb_pkg.sv
diff --git a/tb/tb_serpent_dcache/hdl/tb_readport.sv b/tb/tb_wt_dcache/hdl/tb_readport.sv
similarity index 99%
rename from tb/tb_serpent_dcache/hdl/tb_readport.sv
rename to tb/tb_wt_dcache/hdl/tb_readport.sv
index cc71cd4edbffa85e681d0d4cd5abfa4b415a2355..498cad2671ecae63fae36dfd2898fca29851b1e0 100644
--- a/tb/tb_serpent_dcache/hdl/tb_readport.sv
+++ b/tb/tb_wt_dcache/hdl/tb_readport.sv
@@ -18,7 +18,7 @@
 `include "tb.svh"
 
 import ariane_pkg::*;
-import serpent_cache_pkg::*;
+import wt_cache_pkg::*;
 import tb_pkg::*;
 
 program tb_readport  #(
diff --git a/tb/tb_serpent_dcache/hdl/tb_writeport.sv b/tb/tb_wt_dcache/hdl/tb_writeport.sv
similarity index 99%
rename from tb/tb_serpent_dcache/hdl/tb_writeport.sv
rename to tb/tb_wt_dcache/hdl/tb_writeport.sv
index 205708393ce2c1303b2aca27554002f455bf1163..e9b1c19596e4b1d2c9a191379b1f17b11ceac776 100644
--- a/tb/tb_serpent_dcache/hdl/tb_writeport.sv
+++ b/tb/tb_wt_dcache/hdl/tb_writeport.sv
@@ -17,7 +17,7 @@
 `include "tb.svh"
 
 import ariane_pkg::*;
-import serpent_cache_pkg::*;
+import wt_cache_pkg::*;
 import tb_pkg::*;
 
 program tb_writeport  #(
diff --git a/tb/tb_serpent_dcache/tb.list b/tb/tb_wt_dcache/tb.list
similarity index 60%
rename from tb/tb_serpent_dcache/tb.list
rename to tb/tb_wt_dcache/tb.list
index 0f6de5f1b78029c39e9fa961d9c6fb22759cf2fb..abaa68cc63a7ae2e094e34aa4427437c5a9037f4 100644
--- a/tb/tb_serpent_dcache/tb.list
+++ b/tb/tb_wt_dcache/tb.list
@@ -1,13 +1,13 @@
 ../../include/riscv_pkg.sv
 ../../src/riscv-dbg/src/dm_pkg.sv
 ../../include/ariane_pkg.sv
-../../include/serpent_cache_pkg.sv
+../../include/wt_cache_pkg.sv
 ../../src/fpga-support/rtl/SyncSpRamBeNx64.sv
-../../src/cache_subsystem/serpent_dcache_ctrl.sv
-../../src/cache_subsystem/serpent_dcache_mem.sv
-../../src/cache_subsystem/serpent_dcache_missunit.sv
-../../src/cache_subsystem/serpent_dcache_wbuffer.sv
-../../src/cache_subsystem/serpent_dcache.sv
+../../src/cache_subsystem/wt_dcache_ctrl.sv
+../../src/cache_subsystem/wt_dcache_mem.sv
+../../src/cache_subsystem/wt_dcache_missunit.sv
+../../src/cache_subsystem/wt_dcache_wbuffer.sv
+../../src/cache_subsystem/wt_dcache.sv
 ../../src/common_cells/src/lfsr_8bit.sv
 ../../src/common_cells/src/fifo_v2.sv
 ../../src/common_cells/src/fifo_v3.sv
diff --git a/tb/tb_wt_dcache/wave.do b/tb/tb_wt_dcache/wave.do
new file mode 100644
index 0000000000000000000000000000000000000000..4a5053e2ff204bfe4cbb0358d7da2ce9832bf9ba
--- /dev/null
+++ b/tb/tb_wt_dcache/wave.do
@@ -0,0 +1,474 @@
+onerror {resume}
+quietly WaveActivateNextPane {} 0
+add wave -noupdate /tb/KILL_RATE
+add wave -noupdate /tb/MEM_BYTES
+add wave -noupdate /tb/MEM_RAND_HIT_RATE
+add wave -noupdate /tb/MEM_RAND_INV_RATE
+add wave -noupdate /tb/MEM_WORDS
+add wave -noupdate /tb/NC_ADDR_BEGIN
+add wave -noupdate /tb/amo_ack_o
+add wave -noupdate /tb/amo_rand_en
+add wave -noupdate /tb/amo_req_i
+add wave -noupdate /tb/clk_i
+add wave -noupdate /tb/enable_i
+add wave -noupdate /tb/end_of_sim
+add wave -noupdate /tb/flush_ack_o
+add wave -noupdate /tb/flush_i
+add wave -noupdate /tb/inv_rand_en
+add wave -noupdate /tb/mem_array
+add wave -noupdate /tb/mem_data_ack_i
+add wave -noupdate /tb/mem_data_o
+add wave -noupdate /tb/mem_data_req_o
+add wave -noupdate /tb/mem_rand_en
+add wave -noupdate -expand /tb/mem_rtrn_i
+add wave -noupdate /tb/mem_rtrn_vld_i
+add wave -noupdate /tb/miss_o
+add wave -noupdate /tb/req_ports_i
+add wave -noupdate /tb/req_ports_o
+add wave -noupdate /tb/rst_ni
+add wave -noupdate /tb/seq_done
+add wave -noupdate /tb/seq_last
+add wave -noupdate /tb/seq_num_resp
+add wave -noupdate /tb/seq_run
+add wave -noupdate /tb/seq_type
+add wave -noupdate /tb/test_name
+add wave -noupdate /tb/wbuffer_empty_o
+add wave -noupdate -divider Programs
+add wave -noupdate -group Writeport /tb/i_tb_writeport/clk_i
+add wave -noupdate -group Writeport /tb/i_tb_writeport/rst_ni
+add wave -noupdate -group Writeport /tb/i_tb_writeport/req_rate_i
+add wave -noupdate -group Writeport /tb/i_tb_writeport/seq_type_i
+add wave -noupdate -group Writeport /tb/i_tb_writeport/seq_run_i
+add wave -noupdate -group Writeport /tb/i_tb_writeport/seq_num_vect_i
+add wave -noupdate -group Writeport /tb/i_tb_writeport/seq_last_i
+add wave -noupdate -group Writeport /tb/i_tb_writeport/dut_req_port_i
+add wave -noupdate -group Writeport /tb/i_tb_writeport/MEM_WORDS
+add wave -noupdate -group Writeport /tb/i_tb_writeport/RND_SEED
+add wave -noupdate -group Writeport /tb/i_tb_writeport/VERBOSE
+add wave -noupdate -group Writeport /tb/i_tb_writeport/test_name_i
+add wave -noupdate -group Writeport /tb/i_tb_writeport/paddr
+add wave -noupdate -group Writeport /tb/i_tb_writeport/seq_done_o
+add wave -noupdate -group Writeport /tb/i_tb_writeport/dut_req_port_o
+add wave -noupdate -group {Readport 0} /tb/i_tb_readport0/clk_i
+add wave -noupdate -group {Readport 0} /tb/i_tb_readport0/rst_ni
+add wave -noupdate -group {Readport 0} /tb/i_tb_readport0/seq_type_i
+add wave -noupdate -group {Readport 0} /tb/i_tb_readport0/seq_run_i
+add wave -noupdate -group {Readport 0} /tb/i_tb_readport0/seq_num_resp_i
+add wave -noupdate -group {Readport 0} /tb/i_tb_readport0/seq_last_i
+add wave -noupdate -group {Readport 0} /tb/i_tb_readport0/seq_done_o
+add wave -noupdate -group {Readport 0} -expand /tb/i_tb_readport0/dut_req_port_o
+add wave -noupdate -group {Readport 0} -expand /tb/i_tb_readport0/dut_req_port_i
+add wave -noupdate -group {Readport 0} /tb/i_tb_readport0/paddr
+add wave -noupdate -group {Readport 0} /tb/i_tb_readport0/seq_end_req
+add wave -noupdate -group {Readport 0} /tb/i_tb_readport0/seq_end_ack
+add wave -noupdate -group {Readport 0} /tb/i_tb_readport0/tag_q
+add wave -noupdate -group {Readport 0} /tb/i_tb_readport0/tag_vld_q
+add wave -noupdate -group {Readport 1} /tb/i_tb_readport1/clk_i
+add wave -noupdate -group {Readport 1} /tb/i_tb_readport1/rst_ni
+add wave -noupdate -group {Readport 1} /tb/i_tb_readport1/seq_type_i
+add wave -noupdate -group {Readport 1} /tb/i_tb_readport1/seq_run_i
+add wave -noupdate -group {Readport 1} /tb/i_tb_readport1/seq_num_resp_i
+add wave -noupdate -group {Readport 1} /tb/i_tb_readport1/seq_last_i
+add wave -noupdate -group {Readport 1} /tb/i_tb_readport1/seq_done_o
+add wave -noupdate -group {Readport 1} -expand /tb/i_tb_readport1/dut_req_port_o
+add wave -noupdate -group {Readport 1} -expand /tb/i_tb_readport1/dut_req_port_i
+add wave -noupdate -group {Readport 1} /tb/i_tb_readport1/paddr
+add wave -noupdate -group {Readport 1} /tb/i_tb_readport1/seq_end_req
+add wave -noupdate -group {Readport 1} /tb/i_tb_readport1/seq_end_ack
+add wave -noupdate -group {Readport 1} /tb/i_tb_readport1/tag_q
+add wave -noupdate -group {Readport 1} /tb/i_tb_readport1/tag_vld_q
+add wave -noupdate -group i_tb_mem /tb/i_tb_mem/clk_i
+add wave -noupdate -group i_tb_mem /tb/i_tb_mem/rst_ni
+add wave -noupdate -group i_tb_mem /tb/i_tb_mem/mem_rand_en_i
+add wave -noupdate -group i_tb_mem /tb/i_tb_mem/inv_rand_en_i
+add wave -noupdate -group i_tb_mem /tb/i_tb_mem/amo_rand_en_i
+add wave -noupdate -group i_tb_mem /tb/i_tb_mem/mem_data_req_i
+add wave -noupdate -group i_tb_mem /tb/i_tb_mem/mem_data_i
+add wave -noupdate -group i_tb_mem /tb/i_tb_mem/seq_last_i
+add wave -noupdate -group i_tb_mem /tb/i_tb_mem/check_en_i
+add wave -noupdate -group i_tb_mem /tb/i_tb_mem/commit_en_i
+add wave -noupdate -group i_tb_mem /tb/i_tb_mem/commit_be_i
+add wave -noupdate -group i_tb_mem /tb/i_tb_mem/commit_paddr_i
+add wave -noupdate -group i_tb_mem /tb/i_tb_mem/write_en_i
+add wave -noupdate -group i_tb_mem /tb/i_tb_mem/write_be_i
+add wave -noupdate -group i_tb_mem /tb/i_tb_mem/write_data_i
+add wave -noupdate -group i_tb_mem /tb/i_tb_mem/write_paddr_i
+add wave -noupdate -group i_tb_mem /tb/i_tb_mem/MEM_RAND_HIT_RATE
+add wave -noupdate -group i_tb_mem /tb/i_tb_mem/MEM_RAND_INV_RATE
+add wave -noupdate -group i_tb_mem /tb/i_tb_mem/MEM_WORDS
+add wave -noupdate -group i_tb_mem /tb/i_tb_mem/NC_ADDR_BEGIN
+add wave -noupdate -group i_tb_mem /tb/i_tb_mem/NC_ADDR_GE_LT
+add wave -noupdate -group i_tb_mem /tb/i_tb_mem/mem_ready_q
+add wave -noupdate -group i_tb_mem /tb/i_tb_mem/mem_inv_q
+add wave -noupdate -group i_tb_mem /tb/i_tb_mem/rand_addr_q
+add wave -noupdate -group i_tb_mem /tb/i_tb_mem/outfifo_data
+add wave -noupdate -group i_tb_mem /tb/i_tb_mem/outfifo_pop
+add wave -noupdate -group i_tb_mem /tb/i_tb_mem/outfifo_push
+add wave -noupdate -group i_tb_mem /tb/i_tb_mem/outfifo_full
+add wave -noupdate -group i_tb_mem /tb/i_tb_mem/outfifo_empty
+add wave -noupdate -group i_tb_mem /tb/i_tb_mem/infifo_data
+add wave -noupdate -group i_tb_mem /tb/i_tb_mem/infifo_pop
+add wave -noupdate -group i_tb_mem /tb/i_tb_mem/infifo_push
+add wave -noupdate -group i_tb_mem /tb/i_tb_mem/infifo_full
+add wave -noupdate -group i_tb_mem /tb/i_tb_mem/infifo_empty
+add wave -noupdate -group i_tb_mem /tb/i_tb_mem/initialized_q
+add wave -noupdate -group i_tb_mem /tb/i_tb_mem/write_en
+add wave -noupdate -group i_tb_mem -color Magenta /tb/i_tb_mem/mem_array_q
+add wave -noupdate -group i_tb_mem -color Magenta /tb/i_tb_mem/mem_array_shadow_q
+add wave -noupdate -group i_tb_mem -color Magenta /tb/i_tb_mem/mem_array_dirty_q
+add wave -noupdate -group i_tb_mem /tb/i_tb_mem/mem_rtrn_vld_o
+add wave -noupdate -group i_tb_mem /tb/i_tb_mem/mem_rtrn_o
+add wave -noupdate -group i_tb_mem /tb/i_tb_mem/mem_data_ack_o
+add wave -noupdate -group i_tb_mem /tb/i_tb_mem/mem_array_o
+add wave -noupdate -divider Modules
+add wave -noupdate -group i_dut /tb/i_dut/clk_i
+add wave -noupdate -group i_dut /tb/i_dut/rst_ni
+add wave -noupdate -group i_dut /tb/i_dut/enable_i
+add wave -noupdate -group i_dut /tb/i_dut/flush_i
+add wave -noupdate -group i_dut /tb/i_dut/amo_req_i
+add wave -noupdate -group i_dut /tb/i_dut/req_ports_i
+add wave -noupdate -group i_dut /tb/i_dut/mem_rtrn_vld_i
+add wave -noupdate -group i_dut /tb/i_dut/mem_rtrn_i
+add wave -noupdate -group i_dut /tb/i_dut/mem_data_ack_i
+add wave -noupdate -group i_dut /tb/i_dut/NC_ADDR_BEGIN
+add wave -noupdate -group i_dut /tb/i_dut/NC_ADDR_GE_LT
+add wave -noupdate -group i_dut /tb/i_dut/NUM_PORTS
+add wave -noupdate -group i_dut /tb/i_dut/cache_en
+add wave -noupdate -group i_dut /tb/i_dut/flush_en
+add wave -noupdate -group i_dut /tb/i_dut/wr_cl_vld
+add wave -noupdate -group i_dut /tb/i_dut/wr_cl_tag
+add wave -noupdate -group i_dut /tb/i_dut/wr_cl_idx
+add wave -noupdate -group i_dut /tb/i_dut/wr_cl_off
+add wave -noupdate -group i_dut /tb/i_dut/wr_cl_data
+add wave -noupdate -group i_dut /tb/i_dut/wr_cl_data_be
+add wave -noupdate -group i_dut /tb/i_dut/wr_vld_bits
+add wave -noupdate -group i_dut /tb/i_dut/wr_req
+add wave -noupdate -group i_dut /tb/i_dut/wr_ack
+add wave -noupdate -group i_dut /tb/i_dut/wr_idx
+add wave -noupdate -group i_dut /tb/i_dut/wr_off
+add wave -noupdate -group i_dut /tb/i_dut/wr_data
+add wave -noupdate -group i_dut /tb/i_dut/wr_data_be
+add wave -noupdate -group i_dut /tb/i_dut/miss_req
+add wave -noupdate -group i_dut /tb/i_dut/miss_ack
+add wave -noupdate -group i_dut /tb/i_dut/miss_nc
+add wave -noupdate -group i_dut /tb/i_dut/miss_we
+add wave -noupdate -group i_dut /tb/i_dut/miss_wdata
+add wave -noupdate -group i_dut /tb/i_dut/miss_paddr
+add wave -noupdate -group i_dut /tb/i_dut/miss_vld_bits
+add wave -noupdate -group i_dut /tb/i_dut/miss_size
+add wave -noupdate -group i_dut /tb/i_dut/miss_wr_id
+add wave -noupdate -group i_dut /tb/i_dut/miss_rtrn_vld
+add wave -noupdate -group i_dut /tb/i_dut/miss_rtrn_id
+add wave -noupdate -group i_dut /tb/i_dut/rd_req
+add wave -noupdate -group i_dut /tb/i_dut/rd_ack
+add wave -noupdate -group i_dut /tb/i_dut/rd_tag
+add wave -noupdate -group i_dut /tb/i_dut/rd_idx
+add wave -noupdate -group i_dut /tb/i_dut/rd_off
+add wave -noupdate -group i_dut /tb/i_dut/rd_data
+add wave -noupdate -group i_dut /tb/i_dut/rd_vld_bits
+add wave -noupdate -group i_dut /tb/i_dut/rd_hit_oh
+add wave -noupdate -group i_dut /tb/i_dut/wbuffer_data
+add wave -noupdate -group i_dut /tb/i_dut/flush_ack_o
+add wave -noupdate -group i_dut /tb/i_dut/miss_o
+add wave -noupdate -group i_dut /tb/i_dut/wbuffer_empty_o
+add wave -noupdate -group i_dut /tb/i_dut/amo_ack_o
+add wave -noupdate -group i_dut /tb/i_dut/req_ports_o
+add wave -noupdate -group i_dut /tb/i_dut/mem_data_req_o
+add wave -noupdate -group i_dut /tb/i_dut/mem_data_o
+add wave -noupdate -group i_wbuffer /tb/i_dut/i_wt_dcache_wbuffer/clk_i
+add wave -noupdate -group i_wbuffer /tb/i_dut/i_wt_dcache_wbuffer/rst_ni
+add wave -noupdate -group i_wbuffer /tb/i_dut/i_wt_dcache_wbuffer/cache_en_i
+add wave -noupdate -group i_wbuffer -color Magenta /tb/i_dut/i_wt_dcache_wbuffer/req_port_i
+add wave -noupdate -group i_wbuffer -color Magenta /tb/i_dut/i_wt_dcache_wbuffer/req_port_o
+add wave -noupdate -group i_wbuffer /tb/i_dut/i_wt_dcache_wbuffer/miss_ack_i
+add wave -noupdate -group i_wbuffer /tb/i_dut/i_wt_dcache_wbuffer/miss_rtrn_vld_i
+add wave -noupdate -group i_wbuffer /tb/i_dut/i_wt_dcache_wbuffer/miss_rtrn_id_i
+add wave -noupdate -group i_wbuffer /tb/i_dut/i_wt_dcache_wbuffer/rd_ack_i
+add wave -noupdate -group i_wbuffer /tb/i_dut/i_wt_dcache_wbuffer/rd_data_i
+add wave -noupdate -group i_wbuffer /tb/i_dut/i_wt_dcache_wbuffer/rd_vld_bits_i
+add wave -noupdate -group i_wbuffer /tb/i_dut/i_wt_dcache_wbuffer/rd_hit_oh_i
+add wave -noupdate -group i_wbuffer /tb/i_dut/i_wt_dcache_wbuffer/wr_ack_i
+add wave -noupdate -group i_wbuffer /tb/i_dut/i_wt_dcache_wbuffer/empty_o
+add wave -noupdate -group i_wbuffer /tb/i_dut/i_wt_dcache_wbuffer/miss_paddr_o
+add wave -noupdate -group i_wbuffer /tb/i_dut/i_wt_dcache_wbuffer/miss_req_o
+add wave -noupdate -group i_wbuffer /tb/i_dut/i_wt_dcache_wbuffer/miss_we_o
+add wave -noupdate -group i_wbuffer /tb/i_dut/i_wt_dcache_wbuffer/miss_wdata_o
+add wave -noupdate -group i_wbuffer /tb/i_dut/i_wt_dcache_wbuffer/miss_vld_bits_o
+add wave -noupdate -group i_wbuffer /tb/i_dut/i_wt_dcache_wbuffer/miss_nc_o
+add wave -noupdate -group i_wbuffer /tb/i_dut/i_wt_dcache_wbuffer/miss_size_o
+add wave -noupdate -group i_wbuffer /tb/i_dut/i_wt_dcache_wbuffer/miss_wr_id_o
+add wave -noupdate -group i_wbuffer /tb/i_dut/i_wt_dcache_wbuffer/rd_tag_o
+add wave -noupdate -group i_wbuffer /tb/i_dut/i_wt_dcache_wbuffer/rd_idx_o
+add wave -noupdate -group i_wbuffer /tb/i_dut/i_wt_dcache_wbuffer/rd_off_o
+add wave -noupdate -group i_wbuffer /tb/i_dut/i_wt_dcache_wbuffer/rd_req_o
+add wave -noupdate -group i_wbuffer /tb/i_dut/i_wt_dcache_wbuffer/wr_req_o
+add wave -noupdate -group i_wbuffer /tb/i_dut/i_wt_dcache_wbuffer/wr_idx_o
+add wave -noupdate -group i_wbuffer /tb/i_dut/i_wt_dcache_wbuffer/wr_off_o
+add wave -noupdate -group i_wbuffer /tb/i_dut/i_wt_dcache_wbuffer/wr_data_o
+add wave -noupdate -group i_wbuffer /tb/i_dut/i_wt_dcache_wbuffer/wr_data_be_o
+add wave -noupdate -group i_wbuffer /tb/i_dut/i_wt_dcache_wbuffer/wbuffer_data_o
+add wave -noupdate -group i_wbuffer /tb/i_dut/i_wt_dcache_wbuffer/NC_ADDR_BEGIN
+add wave -noupdate -group i_wbuffer /tb/i_dut/i_wt_dcache_wbuffer/NC_ADDR_GE_LT
+add wave -noupdate -group i_wbuffer /tb/i_dut/i_wt_dcache_wbuffer/tx_stat_d
+add wave -noupdate -group i_wbuffer /tb/i_dut/i_wt_dcache_wbuffer/tx_stat_q
+add wave -noupdate -group i_wbuffer /tb/i_dut/i_wt_dcache_wbuffer/wbuffer_q
+add wave -noupdate -group i_wbuffer /tb/i_dut/i_wt_dcache_wbuffer/wbuffer_d
+add wave -noupdate -group i_wbuffer /tb/i_dut/i_wt_dcache_wbuffer/valid
+add wave -noupdate -group i_wbuffer -color Magenta /tb/i_dut/i_wt_dcache_wbuffer/debug_paddr
+add wave -noupdate -group i_wbuffer /tb/i_dut/i_wt_dcache_wbuffer/dirty
+add wave -noupdate -group i_wbuffer /tb/i_dut/i_wt_dcache_wbuffer/tocheck
+add wave -noupdate -group i_wbuffer /tb/i_dut/i_wt_dcache_wbuffer/wbuffer_hit_oh
+add wave -noupdate -group i_wbuffer /tb/i_dut/i_wt_dcache_wbuffer/inval_hit
+add wave -noupdate -group i_wbuffer /tb/i_dut/i_wt_dcache_wbuffer/bdirty
+add wave -noupdate -group i_wbuffer /tb/i_dut/i_wt_dcache_wbuffer/next_ptr
+add wave -noupdate -group i_wbuffer /tb/i_dut/i_wt_dcache_wbuffer/dirty_ptr
+add wave -noupdate -group i_wbuffer /tb/i_dut/i_wt_dcache_wbuffer/hit_ptr
+add wave -noupdate -group i_wbuffer /tb/i_dut/i_wt_dcache_wbuffer/wr_ptr
+add wave -noupdate -group i_wbuffer /tb/i_dut/i_wt_dcache_wbuffer/check_ptr_d
+add wave -noupdate -group i_wbuffer /tb/i_dut/i_wt_dcache_wbuffer/check_ptr_q
+add wave -noupdate -group i_wbuffer /tb/i_dut/i_wt_dcache_wbuffer/rtrn_ptr
+add wave -noupdate -group i_wbuffer /tb/i_dut/i_wt_dcache_wbuffer/tx_cnt_q
+add wave -noupdate -group i_wbuffer /tb/i_dut/i_wt_dcache_wbuffer/tx_cnt_d
+add wave -noupdate -group i_wbuffer /tb/i_dut/i_wt_dcache_wbuffer/tx_id_q
+add wave -noupdate -group i_wbuffer /tb/i_dut/i_wt_dcache_wbuffer/tx_id_d
+add wave -noupdate -group i_wbuffer /tb/i_dut/i_wt_dcache_wbuffer/rtrn_id
+add wave -noupdate -group i_wbuffer /tb/i_dut/i_wt_dcache_wbuffer/bdirty_off
+add wave -noupdate -group i_wbuffer /tb/i_dut/i_wt_dcache_wbuffer/tx_be
+add wave -noupdate -group i_wbuffer /tb/i_dut/i_wt_dcache_wbuffer/wr_paddr
+add wave -noupdate -group i_wbuffer /tb/i_dut/i_wt_dcache_wbuffer/rd_paddr
+add wave -noupdate -group i_wbuffer /tb/i_dut/i_wt_dcache_wbuffer/check_en_d
+add wave -noupdate -group i_wbuffer /tb/i_dut/i_wt_dcache_wbuffer/check_en_q
+add wave -noupdate -group i_wbuffer /tb/i_dut/i_wt_dcache_wbuffer/full
+add wave -noupdate -group i_wbuffer /tb/i_dut/i_wt_dcache_wbuffer/dirty_rd_en
+add wave -noupdate -group i_wbuffer /tb/i_dut/i_wt_dcache_wbuffer/rdy
+add wave -noupdate -group i_wbuffer /tb/i_dut/i_wt_dcache_wbuffer/rtrn_empty
+add wave -noupdate -group i_wbuffer /tb/i_dut/i_wt_dcache_wbuffer/evict
+add wave -noupdate -group i_wbuffer /tb/i_dut/i_wt_dcache_wbuffer/nc_pending_d
+add wave -noupdate -group i_wbuffer /tb/i_dut/i_wt_dcache_wbuffer/nc_pending_q
+add wave -noupdate -group i_wbuffer /tb/i_dut/i_wt_dcache_wbuffer/addr_is_nc
+add wave -noupdate -group i_missunit /tb/i_dut/i_wt_dcache_missunit/clk_i
+add wave -noupdate -group i_missunit /tb/i_dut/i_wt_dcache_missunit/rst_ni
+add wave -noupdate -group i_missunit /tb/i_dut/i_wt_dcache_missunit/enable_i
+add wave -noupdate -group i_missunit /tb/i_dut/i_wt_dcache_missunit/flush_i
+add wave -noupdate -group i_missunit /tb/i_dut/i_wt_dcache_missunit/wbuffer_empty_i
+add wave -noupdate -group i_missunit /tb/i_dut/i_wt_dcache_missunit/amo_req_i
+add wave -noupdate -group i_missunit -expand /tb/i_dut/i_wt_dcache_missunit/miss_req_i
+add wave -noupdate -group i_missunit /tb/i_dut/i_wt_dcache_missunit/miss_nc_i
+add wave -noupdate -group i_missunit /tb/i_dut/i_wt_dcache_missunit/miss_we_i
+add wave -noupdate -group i_missunit /tb/i_dut/i_wt_dcache_missunit/miss_wdata_i
+add wave -noupdate -group i_missunit /tb/i_dut/i_wt_dcache_missunit/miss_paddr_i
+add wave -noupdate -group i_missunit /tb/i_dut/i_wt_dcache_missunit/miss_vld_bits_i
+add wave -noupdate -group i_missunit /tb/i_dut/i_wt_dcache_missunit/miss_size_i
+add wave -noupdate -group i_missunit /tb/i_dut/i_wt_dcache_missunit/miss_wr_id_i
+add wave -noupdate -group i_missunit /tb/i_dut/i_wt_dcache_missunit/mem_rtrn_vld_i
+add wave -noupdate -group i_missunit /tb/i_dut/i_wt_dcache_missunit/mem_rtrn_i
+add wave -noupdate -group i_missunit /tb/i_dut/i_wt_dcache_missunit/mem_data_ack_i
+add wave -noupdate -group i_missunit /tb/i_dut/i_wt_dcache_missunit/flush_ack_o
+add wave -noupdate -group i_missunit /tb/i_dut/i_wt_dcache_missunit/miss_o
+add wave -noupdate -group i_missunit /tb/i_dut/i_wt_dcache_missunit/cache_en_o
+add wave -noupdate -group i_missunit /tb/i_dut/i_wt_dcache_missunit/flush_en_o
+add wave -noupdate -group i_missunit /tb/i_dut/i_wt_dcache_missunit/amo_ack_o
+add wave -noupdate -group i_missunit /tb/i_dut/i_wt_dcache_missunit/miss_ack_o
+add wave -noupdate -group i_missunit /tb/i_dut/i_wt_dcache_missunit/miss_replay_o
+add wave -noupdate -group i_missunit /tb/i_dut/i_wt_dcache_missunit/miss_rtrn_vld_o
+add wave -noupdate -group i_missunit /tb/i_dut/i_wt_dcache_missunit/miss_rtrn_id_o
+add wave -noupdate -group i_missunit /tb/i_dut/i_wt_dcache_missunit/wr_cl_vld_o
+add wave -noupdate -group i_missunit /tb/i_dut/i_wt_dcache_missunit/wr_cl_nc_o
+add wave -noupdate -group i_missunit /tb/i_dut/i_wt_dcache_missunit/wr_cl_we_o
+add wave -noupdate -group i_missunit /tb/i_dut/i_wt_dcache_missunit/wr_cl_tag_o
+add wave -noupdate -group i_missunit /tb/i_dut/i_wt_dcache_missunit/wr_cl_idx_o
+add wave -noupdate -group i_missunit /tb/i_dut/i_wt_dcache_missunit/wr_cl_off_o
+add wave -noupdate -group i_missunit /tb/i_dut/i_wt_dcache_missunit/wr_cl_data_o
+add wave -noupdate -group i_missunit /tb/i_dut/i_wt_dcache_missunit/wr_cl_data_be_o
+add wave -noupdate -group i_missunit /tb/i_dut/i_wt_dcache_missunit/wr_vld_bits_o
+add wave -noupdate -group i_missunit /tb/i_dut/i_wt_dcache_missunit/mem_data_req_o
+add wave -noupdate -group i_missunit /tb/i_dut/i_wt_dcache_missunit/mem_data_o
+add wave -noupdate -group i_missunit /tb/i_dut/i_wt_dcache_missunit/NUM_PORTS
+add wave -noupdate -group i_missunit /tb/i_dut/i_wt_dcache_missunit/state_d
+add wave -noupdate -group i_missunit /tb/i_dut/i_wt_dcache_missunit/state_q
+add wave -noupdate -group i_missunit /tb/i_dut/i_wt_dcache_missunit/mshr_d
+add wave -noupdate -group i_missunit /tb/i_dut/i_wt_dcache_missunit/mshr_q
+add wave -noupdate -group i_missunit /tb/i_dut/i_wt_dcache_missunit/repl_way
+add wave -noupdate -group i_missunit /tb/i_dut/i_wt_dcache_missunit/inv_way
+add wave -noupdate -group i_missunit /tb/i_dut/i_wt_dcache_missunit/rnd_way
+add wave -noupdate -group i_missunit /tb/i_dut/i_wt_dcache_missunit/mshr_vld_d
+add wave -noupdate -group i_missunit /tb/i_dut/i_wt_dcache_missunit/mshr_vld_q
+add wave -noupdate -group i_missunit /tb/i_dut/i_wt_dcache_missunit/mshr_allocate
+add wave -noupdate -group i_missunit /tb/i_dut/i_wt_dcache_missunit/update_lfsr
+add wave -noupdate -group i_missunit /tb/i_dut/i_wt_dcache_missunit/all_ways_valid
+add wave -noupdate -group i_missunit /tb/i_dut/i_wt_dcache_missunit/enable_d
+add wave -noupdate -group i_missunit /tb/i_dut/i_wt_dcache_missunit/enable_q
+add wave -noupdate -group i_missunit /tb/i_dut/i_wt_dcache_missunit/flush_ack_d
+add wave -noupdate -group i_missunit /tb/i_dut/i_wt_dcache_missunit/flush_ack_q
+add wave -noupdate -group i_missunit /tb/i_dut/i_wt_dcache_missunit/amo_sel
+add wave -noupdate -group i_missunit /tb/i_dut/i_wt_dcache_missunit/flush_done
+add wave -noupdate -group i_missunit /tb/i_dut/i_wt_dcache_missunit/mask_reads
+add wave -noupdate -group i_missunit /tb/i_dut/i_wt_dcache_missunit/miss_is_write
+add wave -noupdate -group i_missunit /tb/i_dut/i_wt_dcache_missunit/amo_data
+add wave -noupdate -group i_missunit /tb/i_dut/i_wt_dcache_missunit/miss_port_idx
+add wave -noupdate -group i_missunit /tb/i_dut/i_wt_dcache_missunit/cnt_d
+add wave -noupdate -group i_missunit /tb/i_dut/i_wt_dcache_missunit/cnt_q
+add wave -noupdate -group i_missunit /tb/i_dut/i_wt_dcache_missunit/miss_req
+add wave -noupdate -group i_missunit /tb/i_dut/i_wt_dcache_missunit/inv_vld
+add wave -noupdate -group i_missunit /tb/i_dut/i_wt_dcache_missunit/cl_write_en
+add wave -noupdate -group i_missunit /tb/i_dut/i_wt_dcache_missunit/load_ack
+add wave -noupdate -group i_missunit /tb/i_dut/i_wt_dcache_missunit/store_ack
+add wave -noupdate -group i_missunit /tb/i_dut/i_wt_dcache_missunit/amo_ack
+add wave -noupdate -expand -group i_mem /tb/i_dut/i_wt_dcache_mem/clk_i
+add wave -noupdate -expand -group i_mem /tb/i_dut/i_wt_dcache_mem/rst_ni
+add wave -noupdate -expand -group i_mem /tb/i_dut/i_wt_dcache_mem/rd_tag_i
+add wave -noupdate -expand -group i_mem /tb/i_dut/i_wt_dcache_mem/rd_idx_i
+add wave -noupdate -expand -group i_mem /tb/i_dut/i_wt_dcache_mem/rd_off_i
+add wave -noupdate -expand -group i_mem /tb/i_dut/i_wt_dcache_mem/rd_req_i
+add wave -noupdate -expand -group i_mem /tb/i_dut/i_wt_dcache_mem/wr_cl_vld_i
+add wave -noupdate -expand -group i_mem /tb/i_dut/i_wt_dcache_mem/wr_cl_tag_i
+add wave -noupdate -expand -group i_mem /tb/i_dut/i_wt_dcache_mem/wr_cl_idx_i
+add wave -noupdate -expand -group i_mem /tb/i_dut/i_wt_dcache_mem/wr_cl_off_i
+add wave -noupdate -expand -group i_mem /tb/i_dut/i_wt_dcache_mem/wr_cl_data_i
+add wave -noupdate -expand -group i_mem /tb/i_dut/i_wt_dcache_mem/wr_cl_data_be_i
+add wave -noupdate -expand -group i_mem -expand /tb/i_dut/i_wt_dcache_mem/wr_vld_bits_i
+add wave -noupdate -expand -group i_mem /tb/i_dut/i_wt_dcache_mem/wr_req_i
+add wave -noupdate -expand -group i_mem /tb/i_dut/i_wt_dcache_mem/wr_idx_i
+add wave -noupdate -expand -group i_mem /tb/i_dut/i_wt_dcache_mem/wr_off_i
+add wave -noupdate -expand -group i_mem /tb/i_dut/i_wt_dcache_mem/wr_data_i
+add wave -noupdate -expand -group i_mem /tb/i_dut/i_wt_dcache_mem/wr_data_be_i
+add wave -noupdate -expand -group i_mem /tb/i_dut/i_wt_dcache_mem/wbuffer_data_i
+add wave -noupdate -expand -group i_mem /tb/i_dut/i_wt_dcache_mem/rd_ack_o
+add wave -noupdate -expand -group i_mem /tb/i_dut/i_wt_dcache_mem/rd_vld_bits_o
+add wave -noupdate -expand -group i_mem /tb/i_dut/i_wt_dcache_mem/rd_hit_oh_o
+add wave -noupdate -expand -group i_mem /tb/i_dut/i_wt_dcache_mem/rd_data_o
+add wave -noupdate -expand -group i_mem /tb/i_dut/i_wt_dcache_mem/wr_ack_o
+add wave -noupdate -expand -group i_mem /tb/i_dut/i_wt_dcache_mem/NUM_PORTS
+add wave -noupdate -expand -group i_mem /tb/i_dut/i_wt_dcache_mem/bank_req
+add wave -noupdate -expand -group i_mem /tb/i_dut/i_wt_dcache_mem/bank_we
+add wave -noupdate -expand -group i_mem /tb/i_dut/i_wt_dcache_mem/bank_be
+add wave -noupdate -expand -group i_mem /tb/i_dut/i_wt_dcache_mem/bank_idx
+add wave -noupdate -expand -group i_mem /tb/i_dut/i_wt_dcache_mem/bank_idx_d
+add wave -noupdate -expand -group i_mem /tb/i_dut/i_wt_dcache_mem/bank_idx_q
+add wave -noupdate -expand -group i_mem /tb/i_dut/i_wt_dcache_mem/bank_off_d
+add wave -noupdate -expand -group i_mem /tb/i_dut/i_wt_dcache_mem/bank_off_q
+add wave -noupdate -expand -group i_mem /tb/i_dut/i_wt_dcache_mem/bank_wdata
+add wave -noupdate -expand -group i_mem /tb/i_dut/i_wt_dcache_mem/bank_rdata
+add wave -noupdate -expand -group i_mem /tb/i_dut/i_wt_dcache_mem/rdata_cl
+add wave -noupdate -expand -group i_mem /tb/i_dut/i_wt_dcache_mem/vld_req
+add wave -noupdate -expand -group i_mem /tb/i_dut/i_wt_dcache_mem/vld_we
+add wave -noupdate -expand -group i_mem /tb/i_dut/i_wt_dcache_mem/vld_wdata
+add wave -noupdate -expand -group i_mem /tb/i_dut/i_wt_dcache_mem/tag_rdata
+add wave -noupdate -expand -group i_mem /tb/i_dut/i_wt_dcache_mem/vld_addr
+add wave -noupdate -expand -group i_mem /tb/i_dut/i_wt_dcache_mem/vld_sel_d
+add wave -noupdate -expand -group i_mem /tb/i_dut/i_wt_dcache_mem/vld_sel_q
+add wave -noupdate -expand -group i_mem /tb/i_dut/i_wt_dcache_mem/wbuffer_hit_oh
+add wave -noupdate -expand -group i_mem /tb/i_dut/i_wt_dcache_mem/wbuffer_be
+add wave -noupdate -expand -group i_mem /tb/i_dut/i_wt_dcache_mem/wbuffer_rdata
+add wave -noupdate -expand -group i_mem /tb/i_dut/i_wt_dcache_mem/rdata
+add wave -noupdate -expand -group i_mem /tb/i_dut/i_wt_dcache_mem/wbuffer_cmp_addr
+add wave -noupdate -expand -group i_mem /tb/i_dut/i_wt_dcache_mem/wbuffer_bvalid
+add wave -noupdate -expand -group i_mem /tb/i_dut/i_wt_dcache_mem/wbuffer_data
+add wave -noupdate -expand -group i_mem /tb/i_dut/i_wt_dcache_mem/vld_tag_rdata
+add wave -noupdate -group i_ctrl0 {/tb/i_dut/genblk1[0]/i_wt_dcache_ctrl/clk_i}
+add wave -noupdate -group i_ctrl0 {/tb/i_dut/genblk1[0]/i_wt_dcache_ctrl/rst_ni}
+add wave -noupdate -group i_ctrl0 {/tb/i_dut/genblk1[0]/i_wt_dcache_ctrl/flush_i}
+add wave -noupdate -group i_ctrl0 {/tb/i_dut/genblk1[0]/i_wt_dcache_ctrl/cache_en_i}
+add wave -noupdate -group i_ctrl0 -expand {/tb/i_dut/genblk1[0]/i_wt_dcache_ctrl/req_port_i}
+add wave -noupdate -group i_ctrl0 {/tb/i_dut/genblk1[0]/i_wt_dcache_ctrl/miss_ack_i}
+add wave -noupdate -group i_ctrl0 {/tb/i_dut/genblk1[0]/i_wt_dcache_ctrl/miss_replay_i}
+add wave -noupdate -group i_ctrl0 {/tb/i_dut/genblk1[0]/i_wt_dcache_ctrl/miss_rtrn_vld_i}
+add wave -noupdate -group i_ctrl0 {/tb/i_dut/genblk1[0]/i_wt_dcache_ctrl/rd_ack_i}
+add wave -noupdate -group i_ctrl0 {/tb/i_dut/genblk1[0]/i_wt_dcache_ctrl/rd_data_i}
+add wave -noupdate -group i_ctrl0 {/tb/i_dut/genblk1[0]/i_wt_dcache_ctrl/rd_vld_bits_i}
+add wave -noupdate -group i_ctrl0 {/tb/i_dut/genblk1[0]/i_wt_dcache_ctrl/rd_hit_oh_i}
+add wave -noupdate -group i_ctrl0 {/tb/i_dut/genblk1[0]/i_wt_dcache_ctrl/req_port_o}
+add wave -noupdate -group i_ctrl0 {/tb/i_dut/genblk1[0]/i_wt_dcache_ctrl/miss_req_o}
+add wave -noupdate -group i_ctrl0 {/tb/i_dut/genblk1[0]/i_wt_dcache_ctrl/miss_we_o}
+add wave -noupdate -group i_ctrl0 {/tb/i_dut/genblk1[0]/i_wt_dcache_ctrl/miss_wdata_o}
+add wave -noupdate -group i_ctrl0 {/tb/i_dut/genblk1[0]/i_wt_dcache_ctrl/miss_vld_bits_o}
+add wave -noupdate -group i_ctrl0 {/tb/i_dut/genblk1[0]/i_wt_dcache_ctrl/miss_paddr_o}
+add wave -noupdate -group i_ctrl0 {/tb/i_dut/genblk1[0]/i_wt_dcache_ctrl/miss_nc_o}
+add wave -noupdate -group i_ctrl0 {/tb/i_dut/genblk1[0]/i_wt_dcache_ctrl/miss_size_o}
+add wave -noupdate -group i_ctrl0 {/tb/i_dut/genblk1[0]/i_wt_dcache_ctrl/miss_wr_id_o}
+add wave -noupdate -group i_ctrl0 {/tb/i_dut/genblk1[0]/i_wt_dcache_ctrl/rd_tag_o}
+add wave -noupdate -group i_ctrl0 {/tb/i_dut/genblk1[0]/i_wt_dcache_ctrl/rd_idx_o}
+add wave -noupdate -group i_ctrl0 {/tb/i_dut/genblk1[0]/i_wt_dcache_ctrl/rd_off_o}
+add wave -noupdate -group i_ctrl0 {/tb/i_dut/genblk1[0]/i_wt_dcache_ctrl/rd_req_o}
+add wave -noupdate -group i_ctrl0 {/tb/i_dut/genblk1[0]/i_wt_dcache_ctrl/NC_ADDR_BEGIN}
+add wave -noupdate -group i_ctrl0 {/tb/i_dut/genblk1[0]/i_wt_dcache_ctrl/NC_ADDR_GE_LT}
+add wave -noupdate -group i_ctrl0 {/tb/i_dut/genblk1[0]/i_wt_dcache_ctrl/state_d}
+add wave -noupdate -group i_ctrl0 {/tb/i_dut/genblk1[0]/i_wt_dcache_ctrl/state_q}
+add wave -noupdate -group i_ctrl0 {/tb/i_dut/genblk1[0]/i_wt_dcache_ctrl/address_tag_d}
+add wave -noupdate -group i_ctrl0 {/tb/i_dut/genblk1[0]/i_wt_dcache_ctrl/address_tag_q}
+add wave -noupdate -group i_ctrl0 {/tb/i_dut/genblk1[0]/i_wt_dcache_ctrl/address_idx_d}
+add wave -noupdate -group i_ctrl0 {/tb/i_dut/genblk1[0]/i_wt_dcache_ctrl/address_idx_q}
+add wave -noupdate -group i_ctrl0 {/tb/i_dut/genblk1[0]/i_wt_dcache_ctrl/address_off_d}
+add wave -noupdate -group i_ctrl0 {/tb/i_dut/genblk1[0]/i_wt_dcache_ctrl/address_off_q}
+add wave -noupdate -group i_ctrl0 {/tb/i_dut/genblk1[0]/i_wt_dcache_ctrl/vld_data_d}
+add wave -noupdate -group i_ctrl0 {/tb/i_dut/genblk1[0]/i_wt_dcache_ctrl/vld_data_q}
+add wave -noupdate -group i_ctrl0 {/tb/i_dut/genblk1[0]/i_wt_dcache_ctrl/save_tag}
+add wave -noupdate -group i_ctrl0 {/tb/i_dut/genblk1[0]/i_wt_dcache_ctrl/rd_req_d}
+add wave -noupdate -group i_ctrl0 {/tb/i_dut/genblk1[0]/i_wt_dcache_ctrl/rd_req_q}
+add wave -noupdate -group i_ctrl0 {/tb/i_dut/genblk1[0]/i_wt_dcache_ctrl/data_size_d}
+add wave -noupdate -group i_ctrl0 {/tb/i_dut/genblk1[0]/i_wt_dcache_ctrl/data_size_q}
+add wave -noupdate -group i_ctrl1 {/tb/i_dut/genblk1[1]/i_wt_dcache_ctrl/clk_i}
+add wave -noupdate -group i_ctrl1 {/tb/i_dut/genblk1[1]/i_wt_dcache_ctrl/rst_ni}
+add wave -noupdate -group i_ctrl1 {/tb/i_dut/genblk1[1]/i_wt_dcache_ctrl/flush_i}
+add wave -noupdate -group i_ctrl1 {/tb/i_dut/genblk1[1]/i_wt_dcache_ctrl/cache_en_i}
+add wave -noupdate -group i_ctrl1 {/tb/i_dut/genblk1[1]/i_wt_dcache_ctrl/req_port_i}
+add wave -noupdate -group i_ctrl1 {/tb/i_dut/genblk1[1]/i_wt_dcache_ctrl/miss_ack_i}
+add wave -noupdate -group i_ctrl1 {/tb/i_dut/genblk1[1]/i_wt_dcache_ctrl/miss_replay_i}
+add wave -noupdate -group i_ctrl1 {/tb/i_dut/genblk1[1]/i_wt_dcache_ctrl/miss_rtrn_vld_i}
+add wave -noupdate -group i_ctrl1 {/tb/i_dut/genblk1[1]/i_wt_dcache_ctrl/rd_ack_i}
+add wave -noupdate -group i_ctrl1 {/tb/i_dut/genblk1[1]/i_wt_dcache_ctrl/rd_data_i}
+add wave -noupdate -group i_ctrl1 {/tb/i_dut/genblk1[1]/i_wt_dcache_ctrl/rd_vld_bits_i}
+add wave -noupdate -group i_ctrl1 {/tb/i_dut/genblk1[1]/i_wt_dcache_ctrl/rd_hit_oh_i}
+add wave -noupdate -group i_ctrl1 {/tb/i_dut/genblk1[1]/i_wt_dcache_ctrl/req_port_o}
+add wave -noupdate -group i_ctrl1 {/tb/i_dut/genblk1[1]/i_wt_dcache_ctrl/miss_req_o}
+add wave -noupdate -group i_ctrl1 {/tb/i_dut/genblk1[1]/i_wt_dcache_ctrl/miss_we_o}
+add wave -noupdate -group i_ctrl1 {/tb/i_dut/genblk1[1]/i_wt_dcache_ctrl/miss_wdata_o}
+add wave -noupdate -group i_ctrl1 {/tb/i_dut/genblk1[1]/i_wt_dcache_ctrl/miss_vld_bits_o}
+add wave -noupdate -group i_ctrl1 {/tb/i_dut/genblk1[1]/i_wt_dcache_ctrl/miss_paddr_o}
+add wave -noupdate -group i_ctrl1 {/tb/i_dut/genblk1[1]/i_wt_dcache_ctrl/miss_nc_o}
+add wave -noupdate -group i_ctrl1 {/tb/i_dut/genblk1[1]/i_wt_dcache_ctrl/miss_size_o}
+add wave -noupdate -group i_ctrl1 {/tb/i_dut/genblk1[1]/i_wt_dcache_ctrl/miss_wr_id_o}
+add wave -noupdate -group i_ctrl1 {/tb/i_dut/genblk1[1]/i_wt_dcache_ctrl/rd_tag_o}
+add wave -noupdate -group i_ctrl1 {/tb/i_dut/genblk1[1]/i_wt_dcache_ctrl/rd_idx_o}
+add wave -noupdate -group i_ctrl1 {/tb/i_dut/genblk1[1]/i_wt_dcache_ctrl/rd_off_o}
+add wave -noupdate -group i_ctrl1 {/tb/i_dut/genblk1[1]/i_wt_dcache_ctrl/rd_req_o}
+add wave -noupdate -group i_ctrl1 {/tb/i_dut/genblk1[1]/i_wt_dcache_ctrl/NC_ADDR_BEGIN}
+add wave -noupdate -group i_ctrl1 {/tb/i_dut/genblk1[1]/i_wt_dcache_ctrl/NC_ADDR_GE_LT}
+add wave -noupdate -group i_ctrl1 {/tb/i_dut/genblk1[1]/i_wt_dcache_ctrl/state_d}
+add wave -noupdate -group i_ctrl1 {/tb/i_dut/genblk1[1]/i_wt_dcache_ctrl/state_q}
+add wave -noupdate -group i_ctrl1 {/tb/i_dut/genblk1[1]/i_wt_dcache_ctrl/address_tag_d}
+add wave -noupdate -group i_ctrl1 {/tb/i_dut/genblk1[1]/i_wt_dcache_ctrl/address_tag_q}
+add wave -noupdate -group i_ctrl1 {/tb/i_dut/genblk1[1]/i_wt_dcache_ctrl/address_idx_d}
+add wave -noupdate -group i_ctrl1 {/tb/i_dut/genblk1[1]/i_wt_dcache_ctrl/address_idx_q}
+add wave -noupdate -group i_ctrl1 {/tb/i_dut/genblk1[1]/i_wt_dcache_ctrl/address_off_d}
+add wave -noupdate -group i_ctrl1 {/tb/i_dut/genblk1[1]/i_wt_dcache_ctrl/address_off_q}
+add wave -noupdate -group i_ctrl1 {/tb/i_dut/genblk1[1]/i_wt_dcache_ctrl/vld_data_d}
+add wave -noupdate -group i_ctrl1 {/tb/i_dut/genblk1[1]/i_wt_dcache_ctrl/vld_data_q}
+add wave -noupdate -group i_ctrl1 {/tb/i_dut/genblk1[1]/i_wt_dcache_ctrl/save_tag}
+add wave -noupdate -group i_ctrl1 {/tb/i_dut/genblk1[1]/i_wt_dcache_ctrl/rd_req_d}
+add wave -noupdate -group i_ctrl1 {/tb/i_dut/genblk1[1]/i_wt_dcache_ctrl/rd_req_q}
+add wave -noupdate -group i_ctrl1 {/tb/i_dut/genblk1[1]/i_wt_dcache_ctrl/data_size_d}
+add wave -noupdate -group i_ctrl1 {/tb/i_dut/genblk1[1]/i_wt_dcache_ctrl/data_size_q}
+TreeUpdate [SetDefaultTree]
+quietly WaveActivateNextPane
+add wave -noupdate {/tb/i_tb_mem/mem_array_q[6741]}
+add wave -noupdate {/tb/i_tb_mem/mem_array_shadow_q[6741]}
+add wave -noupdate {/tb/i_tb_mem/mem_array_dirty_q[6741]}
+TreeUpdate [SetDefaultTree]
+WaveRestoreCursors {{Cursor 1} {31432807547 ps} 0} {{Cursor 2} {29040000 ps} 0} {{Cursor 3} {1027790000 ps} 0}
+quietly wave cursor active 2
+configure wave -namecolwidth 375
+configure wave -valuecolwidth 224
+configure wave -justifyvalue left
+configure wave -signalnamewidth 1
+configure wave -snapdistance 10
+configure wave -datasetprefix 0
+configure wave -rowmargin 4
+configure wave -childrowmargin 2
+configure wave -gridoffset 0
+configure wave -gridperiod 1
+configure wave -griddelta 40
+configure wave -timeline 0
+configure wave -timelineunits ps
+update
+WaveRestoreZoom {0 ps} {103267500 ps}
diff --git a/tb/tb_serpent_icache/.gitignore b/tb/tb_wt_icache/.gitignore
similarity index 100%
rename from tb/tb_serpent_icache/.gitignore
rename to tb/tb_wt_icache/.gitignore
diff --git a/tb/tb_serpent_icache/Makefile b/tb/tb_wt_icache/Makefile
similarity index 100%
rename from tb/tb_serpent_icache/Makefile
rename to tb/tb_wt_icache/Makefile
diff --git a/tb/tb_serpent_icache/hdl/mem_emul.sv b/tb/tb_wt_icache/hdl/mem_emul.sv
similarity index 99%
rename from tb/tb_serpent_icache/hdl/mem_emul.sv
rename to tb/tb_wt_icache/hdl/mem_emul.sv
index 89d3e3a3b1ee5839f91c25048043dbe1c27a51b2..23051a4a891c67252af2cdeb2d7397bfa2225256 100644
--- a/tb/tb_serpent_icache/hdl/mem_emul.sv
+++ b/tb/tb_wt_icache/hdl/mem_emul.sv
@@ -14,7 +14,7 @@
 //
 
 import ariane_pkg::*;
-import serpent_cache_pkg::*;
+import wt_cache_pkg::*;
 
 module mem_emul #(
   parameter              MemRandHitRate = 10, //in percent
diff --git a/tb/tb_serpent_icache/hdl/tb.sv b/tb/tb_wt_icache/hdl/tb.sv
similarity index 99%
rename from tb/tb_serpent_icache/hdl/tb.sv
rename to tb/tb_wt_icache/hdl/tb.sv
index dbf50148b8e120ba5596a95b6d640b82c8b291c2..7f7c4485b907379701c84782bd01cb5106ce490a 100644
--- a/tb/tb_serpent_icache/hdl/tb.sv
+++ b/tb/tb_wt_icache/hdl/tb.sv
@@ -22,7 +22,7 @@
 // (random offsets).
 
 import ariane_pkg::*;
-import serpent_cache_pkg::*;
+import wt_cache_pkg::*;
 import tb_pkg::*;
 
 `include "tb.svh"
@@ -239,7 +239,7 @@ module tb;
 // MUT
 ///////////////////////////////////////////////////////////////////////////////
 
-  serpent_icache  #(
+  wt_icache  #(
     .CachedAddrBeg(CachedAddrBeg),
     .CachedAddrEnd(CachedAddrEnd)
     ) dut (
diff --git a/tb/tb_serpent_icache/hdl/tb_pkg.sv b/tb/tb_wt_icache/hdl/tb_pkg.sv
similarity index 100%
rename from tb/tb_serpent_icache/hdl/tb_pkg.sv
rename to tb/tb_wt_icache/hdl/tb_pkg.sv
diff --git a/tb/tb_serpent_icache/hdl/tlb_emul.sv b/tb/tb_wt_icache/hdl/tlb_emul.sv
similarity index 98%
rename from tb/tb_serpent_icache/hdl/tlb_emul.sv
rename to tb/tb_wt_icache/hdl/tlb_emul.sv
index e296bc85b3f0c415294533312655a32e5b1fb2e1..5c839ff71e01a87672c83dff42c3ae781ce63ad2 100644
--- a/tb/tb_serpent_icache/hdl/tlb_emul.sv
+++ b/tb/tb_wt_icache/hdl/tlb_emul.sv
@@ -14,7 +14,7 @@
 //
 
 import ariane_pkg::*;
-import serpent_cache_pkg::*;
+import wt_cache_pkg::*;
 
 module tlb_emul #(
   parameter TlbRandHitRate = 10 //in percent
diff --git a/tb/tb_serpent_icache/tb.list b/tb/tb_wt_icache/tb.list
similarity index 82%
rename from tb/tb_serpent_icache/tb.list
rename to tb/tb_wt_icache/tb.list
index d2449aab0bc028a14888b02f41a3b892b2edacc0..7b1327f65b7778299a137b84c6ef07667f5bf7ac 100644
--- a/tb/tb_serpent_icache/tb.list
+++ b/tb/tb_wt_icache/tb.list
@@ -1,9 +1,9 @@
 ../../include/riscv_pkg.sv
 ../../src/riscv-dbg/src/dm_pkg.sv
 ../../include/ariane_pkg.sv
-../../include/serpent_cache_pkg.sv
+../../include/wt_cache_pkg.sv
 ../../src/fpga-support/rtl/SyncSpRamBeNx64.sv
-../../src/cache_subsystem/serpent_icache.sv
+../../src/cache_subsystem/wt_icache.sv
 ../../src/common_cells/src/lfsr_8bit.sv
 ../../src/common_cells/src/fifo_v2.sv
 ../../src/common_cells/src/fifo_v3.sv
diff --git a/tb/tb_serpent_icache/wave.do b/tb/tb_wt_icache/wave.do
similarity index 100%
rename from tb/tb_serpent_icache/wave.do
rename to tb/tb_wt_icache/wave.do