diff --git a/CHANGELOG.md b/CHANGELOG.md index f040d3115f1161de1c16b7647895c4ff140e2dc2..59bc9143567d5b234f36e812cabc03054eda1826 100644 --- a/CHANGELOG.md +++ b/CHANGELOG.md @@ -11,6 +11,10 @@ and this project adheres to [Semantic Versioning](http://semver.org/spec/v2.0.0. ### Changed - Rerouted the JTAG from PMOD to second channel of FTDI 2232 chip on Genesys 2 board +- Increase available RAM size on Genesys II board to 1 GiB +- Fixed problem which decoded compressed hints as illegal instructions +- Reduce clock frequency of FPGA to 30 MHz to accomodate FPU +- Official support for floating point unit ### 4.0.0 diff --git a/Makefile b/Makefile index cf1afed19f614c22b8275a896a24b5b3a42febd3..e48eed47c76b7230574cdc7a89a2ffaaf5078a52 100644 --- a/Makefile +++ b/Makefile @@ -32,6 +32,11 @@ elf-bin ?= tmp/riscv-tests/build/benchmarks/dhrystone.riscv mkfile_path := $(abspath $(lastword $(MAKEFILE_LIST))) root-dir := $(dir $(mkfile_path)) +support_verilator_4 := $(shell (verilator --version | grep '4\.') &> /dev/null; echo $$?) +ifeq ($(support_verilator_4), 0) + verilator_threads := 2 +endif + ifndef RISCV $(error RISCV not set - please point your RISCV variable to your RISCV installation) endif @@ -39,33 +44,30 @@ endif # Sources # Package files -> compile first ariane_pkg := include/riscv_pkg.sv \ - src/debug/dm_pkg.sv \ - include/ariane_pkg.sv \ - include/std_cache_pkg.sv \ - include/serpent_cache_pkg.sv \ - src/axi/src/axi_pkg.sv \ - src/register_interface/src/reg_intf.sv \ - include/axi_intf.sv \ - tb/ariane_soc_pkg.sv \ - include/ariane_axi_pkg.sv \ - src/fpu/src/pkg/fpnew_pkg.vhd \ - src/fpu/src/pkg/fpnew_fmts_pkg.vhd \ - src/fpu/src/pkg/fpnew_comps_pkg.vhd \ - src/fpu_div_sqrt_mvp/hdl/defs_div_sqrt_mvp.sv \ - src/fpu/src/pkg/fpnew_pkg_constants.vhd + src/debug/dm_pkg.sv \ + include/ariane_pkg.sv \ + include/std_cache_pkg.sv \ + include/serpent_cache_pkg.sv \ + src/axi/src/axi_pkg.sv \ + src/register_interface/src/reg_intf.sv \ + include/axi_intf.sv \ + tb/ariane_soc_pkg.sv \ + include/ariane_axi_pkg.sv \ + src/fpu/src/fpnew_pkg.sv \ + src/fpu_div_sqrt_mvp/hdl/defs_div_sqrt_mvp.sv ariane_pkg := $(addprefix $(root-dir), $(ariane_pkg)) # utility modules util := $(wildcard src/util/*.svh) \ - src/util/instruction_tracer_pkg.sv \ - src/util/instruction_tracer_if.sv \ - src/tech_cells_generic/src/cluster_clock_gating.sv \ - tb/common/mock_uart.sv \ - src/util/sram.sv + src/util/instruction_tracer_pkg.sv \ + src/util/instruction_tracer_if.sv \ + src/tech_cells_generic/src/cluster_clock_gating.sv \ + tb/common/mock_uart.sv \ + src/util/sram.sv util := $(addprefix $(root-dir), $(util)) # Test packages test_pkg := $(wildcard tb/test/*/*sequence_pkg.sv*) \ - $(wildcard tb/test/*/*_pkg.sv*) + $(wildcard tb/test/*/*_pkg.sv*) # DPI dpi := $(patsubst tb/dpi/%.cc,${dpi-library}/%.o,$(wildcard tb/dpi/*.cc)) dpi_hdr := $(wildcard tb/dpi/*.h) @@ -76,66 +78,63 @@ CFLAGS := -I$(QUESTASIM_HOME)/include \ # this list contains the standalone components src := $(filter-out src/ariane_regfile.sv, $(wildcard src/*.sv)) \ - $(wildcard src/fpu/src/utils/*.vhd) \ - $(wildcard src/fpu/src/ops/*.vhd) \ - $(wildcard src/fpu/src/subunits/*.vhd) \ - $(filter-out src/fpu_div_sqrt_mvp/hdl/defs_div_sqrt_mvp.sv, \ - $(wildcard src/fpu_div_sqrt_mvp/hdl/*.sv)) \ - $(wildcard src/frontend/*.sv) \ - $(filter-out src/cache_subsystem/std_no_dcache.sv, \ - $(wildcard src/cache_subsystem/*.sv)) \ - $(wildcard bootrom/*.sv) \ - $(wildcard src/clint/*.sv) \ - $(wildcard fpga/src/axi2apb/src/*.sv) \ - $(wildcard fpga/src/axi_slice/src/*.sv) \ - $(wildcard src/plic/*.sv) \ - $(wildcard src/axi_node/src/*.sv) \ - $(wildcard src/axi_mem_if/src/*.sv) \ - $(filter-out src/debug/dm_pkg.sv, $(wildcard src/debug/*.sv)) \ - $(wildcard src/debug/debug_rom/*.sv) \ - src/register_interface/src/apb_to_reg.sv \ - src/axi/src/axi_multicut.sv \ - src/fpu/src/fpnew.vhd \ - src/fpu/src/fpnew_top.vhd \ - src/common_cells/src/deprecated/generic_fifo.sv \ - src/common_cells/src/deprecated/pulp_sync.sv \ - src/common_cells/src/deprecated/find_first_one.sv \ - src/common_cells/src/rstgen_bypass.sv \ - src/common_cells/src/rstgen.sv \ - src/common_cells/src/stream_mux.sv \ - src/common_cells/src/stream_demux.sv \ - src/common_cells/src/stream_arbiter.sv \ - src/util/axi_master_connect.sv \ - src/util/axi_slave_connect.sv \ - src/util/axi_master_connect_rev.sv \ - src/util/axi_slave_connect_rev.sv \ - src/axi/src/axi_cut.sv \ - src/axi/src/axi_join.sv \ - src/axi/src/axi_delayer.sv \ - src/axi/src/axi_to_axi_lite.sv \ - src/fpga-support/rtl/SyncSpRamBeNx64.sv \ - src/common_cells/src/sync.sv \ - src/common_cells/src/cdc_2phase.sv \ - src/common_cells/src/spill_register.sv \ - src/common_cells/src/sync_wedge.sv \ - src/common_cells/src/edge_detect.sv \ - src/common_cells/src/fifo_v3.sv \ - src/common_cells/src/fifo_v2.sv \ - src/common_cells/src/fifo_v1.sv \ - src/common_cells/src/lzc.sv \ - src/common_cells/src/rrarbiter.sv \ - src/common_cells/src/ready_valid_delay.sv \ - src/common_cells/src/lfsr_8bit.sv \ - src/common_cells/src/lfsr_16bit.sv \ - src/common_cells/src/counter.sv \ - src/common_cells/src/pipe_reg_simple.sv \ - src/tech_cells_generic/src/cluster_clock_inverter.sv \ - src/tech_cells_generic/src/pulp_clock_mux2.sv \ - tb/ariane_testharness.sv \ - tb/ariane_peripherals.sv \ - tb/common/uart.sv \ - tb/common/SimDTM.sv \ - tb/common/SimJTAG.sv + $(filter-out src/fpu/src/fpnew_pkg.sv, $(wildcard src/fpu/src/*.sv)) \ + $(filter-out src/fpu_div_sqrt_mvp/hdl/defs_div_sqrt_mvp.sv, \ + $(wildcard src/fpu_div_sqrt_mvp/hdl/*.sv)) \ + $(wildcard src/frontend/*.sv) \ + $(filter-out src/cache_subsystem/std_no_dcache.sv, \ + $(wildcard src/cache_subsystem/*.sv)) \ + $(wildcard bootrom/*.sv) \ + $(wildcard src/clint/*.sv) \ + $(wildcard fpga/src/axi2apb/src/*.sv) \ + $(wildcard fpga/src/axi_slice/src/*.sv) \ + $(wildcard src/plic/*.sv) \ + $(wildcard src/axi_node/src/*.sv) \ + $(wildcard src/axi_mem_if/src/*.sv) \ + $(filter-out src/debug/dm_pkg.sv, $(wildcard src/debug/*.sv)) \ + $(wildcard src/debug/debug_rom/*.sv) \ + src/register_interface/src/apb_to_reg.sv \ + src/axi/src/axi_multicut.sv \ + src/common_cells/src/deprecated/generic_fifo.sv \ + src/common_cells/src/deprecated/pulp_sync.sv \ + src/common_cells/src/deprecated/find_first_one.sv \ + src/common_cells/src/rstgen_bypass.sv \ + src/common_cells/src/rstgen.sv \ + src/common_cells/src/stream_mux.sv \ + src/common_cells/src/stream_demux.sv \ + src/common_cells/src/stream_arbiter.sv \ + src/common_cells/src/stream_arbiter_flushable.sv \ + src/util/axi_master_connect.sv \ + src/util/axi_slave_connect.sv \ + src/util/axi_master_connect_rev.sv \ + src/util/axi_slave_connect_rev.sv \ + src/axi/src/axi_cut.sv \ + src/axi/src/axi_join.sv \ + src/axi/src/axi_delayer.sv \ + src/axi/src/axi_to_axi_lite.sv \ + src/fpga-support/rtl/SyncSpRamBeNx64.sv \ + src/common_cells/src/sync.sv \ + src/common_cells/src/cdc_2phase.sv \ + src/common_cells/src/spill_register.sv \ + src/common_cells/src/sync_wedge.sv \ + src/common_cells/src/edge_detect.sv \ + src/common_cells/src/fifo_v3.sv \ + src/common_cells/src/fifo_v2.sv \ + src/common_cells/src/fifo_v1.sv \ + src/common_cells/src/lzc.sv \ + src/common_cells/src/rrarbiter.sv \ + src/common_cells/src/stream_delay.sv \ + src/common_cells/src/lfsr_8bit.sv \ + src/common_cells/src/lfsr_16bit.sv \ + src/common_cells/src/counter.sv \ + src/common_cells/src/shift_reg.sv \ + src/tech_cells_generic/src/cluster_clock_inverter.sv \ + src/tech_cells_generic/src/pulp_clock_mux2.sv \ + tb/ariane_testharness.sv \ + tb/ariane_peripherals.sv \ + tb/common/uart.sv \ + tb/common/SimDTM.sv \ + tb/common/SimJTAG.sv src := $(addprefix $(root-dir), $(src)) @@ -154,14 +153,16 @@ riscv-benchmarks-dir := tmp/riscv-tests/build/benchmarks/ riscv-asm-tests-list := ci/riscv-asm-tests.list riscv-amo-tests-list := ci/riscv-amo-tests.list riscv-mul-tests-list := ci/riscv-mul-tests.list +riscv-fp-tests-list := ci/riscv-fp-tests.list riscv-benchmarks-list := ci/riscv-benchmarks.list riscv-asm-tests := $(shell xargs printf '\n%s' < $(riscv-asm-tests-list) | cut -b 1-) riscv-amo-tests := $(shell xargs printf '\n%s' < $(riscv-amo-tests-list) | cut -b 1-) riscv-mul-tests := $(shell xargs printf '\n%s' < $(riscv-mul-tests-list) | cut -b 1-) +riscv-fp-tests := $(shell xargs printf '\n%s' < $(riscv-fp-tests-list) | cut -b 1-) riscv-benchmarks := $(shell xargs printf '\n%s' < $(riscv-benchmarks-list) | cut -b 1-) # Search here for include files (e.g.: non-standalone components) -incdir := +incdir := src/common_cells/include/common_cells # Compile and sim flags compile_flag += +cover=bcfst+/dut -incr -64 -nologo -quiet -suppress 13262 -permissive +define+$(defines) uvm-flags += +UVM_NO_RELNOTES +UVM_VERBOSITY=LOW @@ -180,27 +181,27 @@ riscv-torture-bin := java -jar sbt-launch.jar # if defined, calls the questa targets in batch mode ifdef batch-mode - questa-flags += -c - questa-cmd := -do "coverage save -onexit tmp/$@.ucdb; run -a; quit -code [coverage attribute -name TESTSTATUS -concise]" - questa-cmd += -do " log -r /*; run -all;" + questa-flags += -c + questa-cmd := -do "coverage save -onexit tmp/$@.ucdb; run -a; quit -code [coverage attribute -name TESTSTATUS -concise]" + questa-cmd += -do " log -r /*; run -all;" else - questa-cmd := -do " log -r /*; run -all;" + questa-cmd := -do " log -r /*; run -all;" endif # we want to preload the memories ifdef preload - questa-cmd += +PRELOAD=$(preload) - elf-bin = none - # tandem verify with spike, this requires pre-loading - ifdef tandem - compile_flag += +define+TANDEM - questa-cmd += -gblso tb/riscv-isa-sim/install/lib/libriscv.so - endif + questa-cmd += +PRELOAD=$(preload) + elf-bin = none + # tandem verify with spike, this requires pre-loading + ifdef tandem + compile_flag += +define+TANDEM + questa-cmd += -gblso tb/riscv-isa-sim/install/lib/libriscv.so + endif endif # remote bitbang is enabled ifdef rbb - questa-cmd += +jtag_rbb_enable=1 + questa-cmd += +jtag_rbb_enable=1 else - questa-cmd += +jtag_rbb_enable=0 + questa-cmd += +jtag_rbb_enable=0 endif # Build the TB and module using QuestaSim @@ -211,11 +212,11 @@ build: $(library) $(library)/.build-srcs $(library)/.build-tb $(dpi-library)/ari # src files $(library)/.build-srcs: $(util) $(library) vlog$(questa_version) $(compile_flag) -work $(library) $(filter %.sv,$(ariane_pkg)) $(list_incdir) -suppress 2583 - vcom$(questa_version) $(compile_flag_vhd) -work $(library) -pedanticerrors $(filter %.vhd,$(ariane_pkg)) + # vcom$(questa_version) $(compile_flag_vhd) -work $(library) -pedanticerrors $(filter %.vhd,$(ariane_pkg)) vlog$(questa_version) $(compile_flag) -work $(library) $(filter %.sv,$(util)) $(list_incdir) -suppress 2583 # Suppress message that always_latch may not be checked thoroughly by QuestaSim. vcom$(questa_version) $(compile_flag_vhd) -work $(library) -pedanticerrors $(filter %.vhd,$(uart_src)) - vcom$(questa_version) $(compile_flag_vhd) -work $(library) -pedanticerrors $(filter %.vhd,$(src)) + # vcom$(questa_version) $(compile_flag_vhd) -work $(library) -pedanticerrors $(filter %.vhd,$(src)) vlog$(questa_version) $(compile_flag) -work $(library) -pedanticerrors $(filter %.sv,$(src)) $(list_incdir) -suppress 2583 touch $(library)/.build-srcs @@ -259,8 +260,13 @@ $(riscv-amo-tests): build $(riscv-mul-tests): build vsim${questa_version} +permissive $(questa-flags) $(questa-cmd) -lib $(library) +max-cycles=$(max_cycles) +UVM_TESTNAME=$(test_case) \ - +BASEDIR=$(riscv-test-dir) $(uvm-flags) +jtag_rbb_enable=0 -gblso $(RISCV)/lib/libfesvr.so -sv_lib $(dpi-library)/ariane_dpi \ - ${top_level}_optimized $(QUESTASIM_FLAGS) +permissive-off ++$(riscv-test-dir)/$@ ++$(target-options) | tee tmp/riscv-amo-tests-$@.log + +BASEDIR=$(riscv-test-dir) $(uvm-flags) +jtag_rbb_enable=0 -gblso $(RISCV)/lib/libfesvr.so -sv_lib $(dpi-library)/ariane_dpi \ + ${top_level}_optimized $(QUESTASIM_FLAGS) +permissive-off ++$(riscv-test-dir)/$@ ++$(target-options) | tee tmp/riscv-mul-tests-$@.log + +$(riscv-fp-tests): build + vsim${questa_version} +permissive $(questa-flags) $(questa-cmd) -lib $(library) +max-cycles=$(max_cycles) +UVM_TESTNAME=$(test_case) \ + +BASEDIR=$(riscv-test-dir) $(uvm-flags) +jtag_rbb_enable=0 -gblso $(RISCV)/lib/libfesvr.so -sv_lib $(dpi-library)/ariane_dpi \ + ${top_level}_optimized $(QUESTASIM_FLAGS) +permissive-off ++$(riscv-test-dir)/$@ ++$(target-options) | tee tmp/riscv-fp-tests-$@.log $(riscv-benchmarks): build vsim${questa_version} +permissive $(questa-flags) $(questa-cmd) -lib $(library) +max-cycles=$(max_cycles) +UVM_TESTNAME=$(test_case) \ @@ -277,6 +283,9 @@ run-amo-tests: $(riscv-amo-tests) run-mul-tests: $(riscv-mul-tests) $(MAKE) check-mul-tests +run-fp-tests: $(riscv-fp-tests) + $(MAKE) check-fp-tests + check-asm-tests: ci/check-tests.sh tmp/riscv-asm-tests- $(shell wc -l $(riscv-asm-tests-list) | awk -F " " '{ print $1 }') @@ -286,6 +295,9 @@ check-amo-tests: check-mul-tests: ci/check-tests.sh tmp/riscv-mul-tests- $(shell wc -l $(riscv-mul-tests-list) | awk -F " " '{ print $1 }') +check-fp-tests: + ci/check-tests.sh tmp/riscv-fp-tests- $(shell wc -l $(riscv-fp-tests-list) | awk -F " " '{ print $1 }') + # can use -jX to run ci tests in parallel using X processes run-benchmarks: $(riscv-benchmarks) $(MAKE) check-benchmarks @@ -294,34 +306,36 @@ check-benchmarks: ci/check-tests.sh tmp/riscv-benchmarks- $(shell wc -l $(riscv-benchmarks-list) | awk -F " " '{ print $1 }') # verilator-specific -verilate_command := $(verilator) \ - $(filter-out %.vhd, $(ariane_pkg)) \ - $(filter-out src/fpu_wrap.sv, $(filter-out %.vhd, $(src))) \ - +define+$(defines) \ - src/util/sram.sv \ - +incdir+src/axi_node \ - --unroll-count 256 \ - -Werror-PINMISSING \ - -Werror-IMPLICIT \ - -Wno-fatal \ - -Wno-PINCONNECTEMPTY \ - -Wno-ASSIGNDLY \ - -Wno-DECLFILENAME \ - -Wno-UNOPTFLAT \ - -Wno-UNUSED \ - -Wno-style \ - -Wno-lint \ - $(if $(DEBUG),--trace-structs --trace,) \ - -LDFLAGS "-L$(RISCV)/lib -Wl,-rpath,$(RISCV)/lib -lfesvr" \ - -CFLAGS "$(CFLAGS)" -Wall --cc --vpi \ - $(list_incdir) --top-module ariane_testharness \ - --Mdir $(ver-library) -O3 \ - --exe tb/ariane_tb.cpp tb/dpi/SimDTM.cc tb/dpi/SimJTAG.cc \ - tb/dpi/remote_bitbang.cc tb/dpi/msim_helper.cc +verilate_command := $(verilator) \ + $(filter-out %.vhd, $(ariane_pkg)) \ + $(filter-out src/fpu_wrap.sv, $(filter-out %.vhd, $(src))) \ + +define+$(defines) \ + src/util/sram.sv \ + +incdir+src/axi_node \ + $(if $(verilator_threads), --threads $(verilator_threads)) \ + --unroll-count 256 \ + -Werror-PINMISSING \ + -Werror-IMPLICIT \ + -Wno-fatal \ + -Wno-PINCONNECTEMPTY \ + -Wno-ASSIGNDLY \ + -Wno-DECLFILENAME \ + -Wno-UNUSED \ + -Wno-UNOPTFLAT \ + -Wno-style \ + $(if $(PROFILE),--stats --stats-vars --profile-cfuncs,) \ + -Wno-lint \ + $(if $(DEBUG),--trace-structs --trace,) \ + -LDFLAGS "-L$(RISCV)/lib -Wl,-rpath,$(RISCV)/lib -lfesvr$(if $(PROFILE), -g -pg,)" \ + -CFLAGS "$(CFLAGS)$(if $(PROFILE), -g -pg,)" -Wall --cc --vpi \ + $(list_incdir) --top-module ariane_testharness \ + --Mdir $(ver-library) -O3 \ + --exe tb/ariane_tb.cpp tb/dpi/SimDTM.cc tb/dpi/SimJTAG.cc \ + tb/dpi/remote_bitbang.cc tb/dpi/msim_helper.cc # User Verilator, at some point in the future this will be auto-generated verilate: - @echo "[Verilator] Building Model" + @echo "[Verilator] Building Model$(if $(PROFILE), for Profiling,)" $(verilate_command) cd $(ver-library) && $(MAKE) -j${NUM_JOBS} -f Variane_testharness.mk @@ -337,10 +351,13 @@ $(addsuffix -verilator,$(riscv-amo-tests)): verilate $(addsuffix -verilator,$(riscv-mul-tests)): verilate $(ver-library)/Variane_testharness $(riscv-test-dir)/$(subst -verilator,,$@) +$(addsuffix -verilator,$(riscv-fp-tests)): verilate + $(ver-library)/Variane_testharness $(riscv-test-dir)/$(subst -verilator,,$@) + $(addsuffix -verilator,$(riscv-benchmarks)): verilate $(ver-library)/Variane_testharness $(riscv-benchmarks-dir)/$(subst -verilator,,$@) -run-asm-tests-verilator: $(addsuffix -verilator, $(riscv-asm-tests)) $(addsuffix -verilator, $(riscv-amo-tests)) $(addsuffix -verilator, $(riscv-mul-tests)) +run-asm-tests-verilator: $(addsuffix -verilator, $(riscv-asm-tests)) $(addsuffix -verilator, $(riscv-amo-tests)) $(addsuffix -verilator, $(riscv-fp-tests)) $(addsuffix -verilator, $(riscv-fp-tests)) # split into two halfs for travis jobs (otherwise they will time out) run-asm-tests1-verilator: $(addsuffix -verilator, $(filter rv64ui-v-% ,$(riscv-asm-tests))) @@ -351,6 +368,8 @@ run-amo-verilator: $(addsuffix -verilator, $(riscv-amo-tests)) run-mul-verilator: $(addsuffix -verilator, $(riscv-mul-tests)) +run-fp-verilator: $(addsuffix -verilator, $(riscv-fp-tests)) + run-benchmarks-verilator: $(addsuffix -verilator,$(riscv-benchmarks)) # torture-specific @@ -401,10 +420,10 @@ check-torture: fpga: $(ariane_pkg) $(util) $(src) $(fpga_src) $(util) $(uart_src) @echo "[FPGA] Generate sources" - @echo read_vhdl {$(uart_src)} > fpga/scripts/add_sources.tcl + @echo read_vhdl {$(uart_src)} > fpga/scripts/add_sources.tcl @echo read_verilog -sv {$(ariane_pkg)} >> fpga/scripts/add_sources.tcl @echo read_verilog -sv {$(util)} >> fpga/scripts/add_sources.tcl - @echo read_verilog -sv {$(src)} >> fpga/scripts/add_sources.tcl + @echo read_verilog -sv {$(src)} >> fpga/scripts/add_sources.tcl @echo read_verilog -sv {$(fpga_src)} >> fpga/scripts/add_sources.tcl @echo "[FPGA] Generate Bitstream" cd fpga && make BOARD="genesys2" XILINX_PART="xc7k325tffg900-2" XILINX_BOARD="digilentinc.com:genesys2:part0:1.1" CLK_PERIOD_NS="20" diff --git a/README.md b/README.md index 5e5d6b2a1ec10927f2fe02fcb59d80b821ba8de5..1d629bde27029533e9588c21b136279781f153af 100644 --- a/README.md +++ b/README.md @@ -15,7 +15,6 @@ Table of Contents * [Table of Contents](#table-of-contents) * [Getting Started](#getting-started) * [Running User-Space Applications](#running-user-space-applications) - * [FPU Support](#fpu-support) * [FPGA Emulation](#fpga-emulation) * [Programming the Memory Configuration File](#programming-the-memory-configuration-file) * [Preparing the SD Card](#preparing-the-sd-card) @@ -102,10 +101,6 @@ $ make sim elf-bin=$RISCV/riscv64-unknown-elf/bin/pk target-options=hello.elf b > Be patient! RTL simulation is way slower than Spike. If you think that you ran into problems you can inspect the trace files. -### FPU Support - -> There is preliminary support for floating point extensions F and D. At the moment floating point support will only be available in QuestaSim as the FPU is written in VHDL. This is likely to change. The floating point extensions can be enabled by setting `RVF` and `RVD` to `1'b1` in the `include/ariane_pkg.sv` file. - ## FPGA Emulation We currently only provide support for the [Genesys 2 board](https://reference.digilentinc.com/reference/programmable-logic/genesys-2/reference-manual). We provide pre-build bitstream and memory configuration files for the Genesys 2 [here](https://github.com/pulp-platform/ariane/releases). @@ -168,7 +163,6 @@ To get started, connect the micro USB port that is labeled with JTAG to your mac Once attached to your system, the FTDI chip should be listed when you type `lsusb` -``` Bus 005 Device 019: ID 0403:6010 Future Technology Devices International, Ltd FT2232C/D/H Dual UART/FIFO IC ``` diff --git a/bootrom/ariane.dts b/bootrom/ariane.dts index 7ceb4bc1f8e070d4e36c6adce37f97982bb356b3..34153911ca40ef6cbf49b39b367c61e0c8d78de9 100644 --- a/bootrom/ariane.dts +++ b/bootrom/ariane.dts @@ -18,7 +18,7 @@ reg = <0>; status = "okay"; compatible = "eth, ariane", "riscv"; - riscv,isa = "rv64imacsu"; + riscv,isa = "rv64imafdc"; mmu-type = "riscv,sv39"; tlb-split; // HLIC - hart local interrupt controller diff --git a/ci/check-tests.sh b/ci/check-tests.sh index 2325d7f6da997b07341ba00e3dc0ec71a82203f0..72ae5f5d553c61746a6a68219300765495838f9f 100755 --- a/ci/check-tests.sh +++ b/ci/check-tests.sh @@ -12,7 +12,7 @@ cd $ROOT if [[ -z "$-" ]]; then GREEN='' RED='' - NC='' + NC='' else GREEN='\033[0;32m' RED='\033[0;31m' @@ -28,7 +28,7 @@ fi # get NUM_TOTAL number of tests NUM_TOTAL=$2 -echo "list containint tests: $2" +echo "list containing tests: $2" echo "checking files:" ls "${1}"*.log @@ -45,7 +45,7 @@ echo "NUM_FAILED: $NUM_FAILED" echo "NUM_FATAL: $NUM_FATAL" echo "NUM_ERROR: $NUM_ERROR" -if [[ $(($NUM_FAILED)) -gt 0 ]]; then +if [[ $(($NUM_FAILED)) -gt 0 ]]; then echo -e "${RED}FAILED $NUM_FAILED of $NUM_TOTAL tests ${NC}" exit 1; elif [[ $(($NUM_FATAL)) -ne 0 ]]; then @@ -60,4 +60,4 @@ elif [[ $(($NUM_PASSED)) -ne $(($NUM_TOTAL)) ]]; then else echo -e "${GREEN}PASSED all $NUM_TOTAL tests ${NC}" exit 0; -fi +fi diff --git a/ci/float.config b/ci/float.config new file mode 100644 index 0000000000000000000000000000000000000000..a0093d57cc3800f1d25007e32df1cb27a8880286 --- /dev/null +++ b/ci/float.config @@ -0,0 +1,52 @@ +torture.generator.nseqs 1000 +torture.generator.memsize 1024 +torture.generator.fprnd 0 +torture.generator.amo false +torture.generator.mul true +torture.generator.divider true +torture.generator.segment true +torture.generator.loop true +torture.generator.loop_size 64 + +torture.generator.mix.xmem 15 +torture.generator.mix.xbranch 25 +torture.generator.mix.xalu 15 +torture.generator.mix.fgen 20 +torture.generator.mix.fpmem 10 +torture.generator.mix.fax 10 +torture.generator.mix.fdiv 5 +torture.generator.mix.vec 0 + +torture.generator.vec.vf 1 +torture.generator.vec.seq 20 +torture.generator.vec.memsize 128 +torture.generator.vec.numsregs 64 +torture.generator.vec.mul false +torture.generator.vec.div false +torture.generator.vec.mix true +torture.generator.vec.fpu false +torture.generator.vec.fma false +torture.generator.vec.fcvt false +torture.generator.vec.fdiv false +torture.generator.vec.amo false +torture.generator.vec.seg false +torture.generator.vec.stride false +torture.generator.vec.pred_alu true +torture.generator.vec.pred_mem true + +torture.generator.vec.mix.valu 20 +torture.generator.vec.mix.vpop 60 +torture.generator.vec.mix.vmem 20 +torture.generator.vec.mix.vonly 0 + +torture.testrun.maxcycles 10000000 +torture.testrun.virtual false +torture.testrun.seek true +torture.testrun.dump false +torture.testrun.vec false + +torture.overnight.errors 1 +torture.overnight.minutes 1 +torture.overnight.outdir output/failedtests +torture.overnight.email your@email.address + diff --git a/ci/install-verilator.sh b/ci/install-verilator.sh index fcea0996095997eb324bc0511d1108eff7db4677..5a5228d7da47f45f3ec86ce7ba2bca9077b46ad5 100755 --- a/ci/install-verilator.sh +++ b/ci/install-verilator.sh @@ -9,14 +9,15 @@ fi if [ ! -e "$VERILATOR_ROOT/bin/verilator" ]; then echo "Installing Verilator" - wget https://www.veripool.org/ftp/verilator-3.924.tgz - tar xzf verilator*.t*gz - rm verilator*.t*gz + rm verilator*.t*gz + wget https://www.veripool.org/ftp/verilator-4.008.tgz + tar xzf verilator*.t*gz + rm verilator*.t*gz cd verilator-* mkdir -p $VERILATOR_ROOT # copy scripts - autoconf && ./configure --prefix="$VERILATOR_ROOT" && make -j${NUM_JOBS} - cp -r * $VERILATOR_ROOT/ + autoconf && ./configure --prefix="$VERILATOR_ROOT" && make -j${NUM_JOBS} + cp -r * $VERILATOR_ROOT/ make test else echo "Using Verilator from cached directory." diff --git a/ci/path-setup.sh b/ci/path-setup.sh index c77e20945fe23ca1ed2f324f339e27f63bf27612..4c043f3d8937cbcbea5ecac961c664f6253321d0 100644 --- a/ci/path-setup.sh +++ b/ci/path-setup.sh @@ -5,12 +5,12 @@ export CI_BUILD_DIR=$TOP/ariane-repo #customize this to your setup export QUESTASIM_HOME= export QUESTASIM_VERSION= -export QUESTASIM_FLAGS=-noautoldlibpath +export QUESTASIM_FLAGS= export CXX=g++-7 CC=gcc-7 # where to install the tools export RISCV=$TOP/riscv_install -export VERILATOR_ROOT=$TOP/verilator-3.924/ +export VERILATOR_ROOT=$TOP/verilator-4.008/ export PATH=$RISCV/bin:$VERILATOR_ROOT/bin:$PATH export LIBRARY_PATH=$RISCV/lib @@ -19,4 +19,4 @@ export C_INCLUDE_PATH=$RISCV/include:$VERILATOR_ROOT/include export CPLUS_INCLUDE_PATH=$RISCV/include:$VERILATOR_ROOT/include # number of parallel jobs to use for make commands and simulation -export NUM_JOBS=8 +export NUM_JOBS=8 \ No newline at end of file diff --git a/ci/riscv-asm-tests.list b/ci/riscv-asm-tests.list index 97e17655093721a2984003b734d18214d19cedaf..7cf0e1136aa37ea4389e62448e1b275a31e24ea8 100644 --- a/ci/riscv-asm-tests.list +++ b/ci/riscv-asm-tests.list @@ -78,26 +78,6 @@ rv64ui-v-or rv64ui-v-ori rv64ui-v-sub rv64ui-v-subw -rv64ui-v-xor -rv64ui-v-xori rv64ui-v-sll rv64ui-v-slli -rv64ui-v-slliw -rv64ui-v-slt -rv64ui-v-slti -rv64ui-v-sltiu -rv64ui-v-sltu -rv64ui-v-sra -rv64ui-v-srai -rv64ui-v-sraiw -rv64ui-v-sraw -rv64ui-v-srl -rv64ui-v-srli -rv64ui-v-srliw -rv64ui-v-srlw rv64ui-v-lb -rv64ui-v-lbu -rv64ui-v-ld -rv64ui-v-lh -rv64ui-v-lhu -rv64ui-v-lui diff --git a/ci/riscv-fp-tests.list b/ci/riscv-fp-tests.list new file mode 100644 index 0000000000000000000000000000000000000000..495ba983edf95a928b4fdf8419ab5545b5cce011 --- /dev/null +++ b/ci/riscv-fp-tests.list @@ -0,0 +1,38 @@ +rv64uf-p-fadd +rv64uf-p-fclass +rv64uf-p-fcmp +rv64uf-p-fcvt +rv64uf-p-fcvt_w +rv64uf-p-fdiv +rv64uf-p-fmadd +rv64uf-p-fmin +rv64uf-p-ldst +rv64uf-p-move +rv64uf-p-recoding +rv64uf-v-fadd +rv64uf-v-fclass +rv64uf-v-fcmp +rv64uf-v-fcvt +rv64uf-v-fcvt_w +rv64uf-v-fdiv +rv64uf-v-fmadd +rv64uf-v-fmin +rv64uf-v-ldst +rv64uf-v-move +rv64uf-v-recoding +rv64ud-p-fadd +rv64ud-p-fclass +rv64ud-p-fcmp +rv64ud-p-fcvt +rv64ud-p-fcvt_w +rv64ud-p-fdiv +rv64ud-p-fmadd +rv64ud-p-fmin +rv64ud-v-fadd +rv64ud-v-fclass +rv64ud-v-fcmp +rv64ud-v-fcvt +rv64ud-v-fcvt_w +rv64ud-v-fdiv +rv64ud-v-fmadd +rv64ud-v-fmin diff --git a/fpga/constraints/ariane.xdc b/fpga/constraints/ariane.xdc index 9ea40f9c0397ed2eaf18b488040da588f91f7de0..b60ab9110f7e1d93bc9055ed8ef082c9f90450aa 100644 --- a/fpga/constraints/ariane.xdc +++ b/fpga/constraints/ariane.xdc @@ -3,10 +3,10 @@ create_clock -period 100.000 -name tck -waveform {0.000 50.000} [get_ports tck] set_input_jitter tck 1.000 -set_max_delay -datapath_only -from [get_pins i_dmi_jtag/i_dmi_cdc/i_cdc_resp/i_src/data_src_q_reg*/C] -to [get_pins i_dmi_jtag/i_dmi_cdc/i_cdc_resp/i_dst/data_dst_q_reg*/D] 10.000 -set_max_delay -datapath_only -from [get_pins i_dmi_jtag/i_dmi_cdc/i_cdc_resp/i_src/req_src_q_reg/C] -to [get_pins i_dmi_jtag/i_dmi_cdc/i_cdc_resp/i_dst/req_dst_q_reg/D] 10.000 -set_max_delay -datapath_only -from [get_pins i_dmi_jtag/i_dmi_cdc/i_cdc_req/i_dst/ack_dst_q_reg/C] -to [get_pins i_dmi_jtag/i_dmi_cdc/i_cdc_req/i_src/ack_src_q_reg/D] 10.000 - - - +set_max_delay -datapath_only -from [get_pins i_dmi_jtag/i_dmi_cdc/i_cdc_resp/i_src/data_src_q_reg*/C] -to [get_pins i_dmi_jtag/i_dmi_cdc/i_cdc_resp/i_dst/data_dst_q_reg*/D] 20.000 +set_max_delay -datapath_only -from [get_pins i_dmi_jtag/i_dmi_cdc/i_cdc_resp/i_src/req_src_q_reg/C] -to [get_pins i_dmi_jtag/i_dmi_cdc/i_cdc_resp/i_dst/req_dst_q_reg/D] 20.000 +set_max_delay -datapath_only -from [get_pins i_dmi_jtag/i_dmi_cdc/i_cdc_req/i_dst/ack_dst_q_reg/C] -to [get_pins i_dmi_jtag/i_dmi_cdc/i_cdc_req/i_src/ack_src_q_reg/D] 20.000 +# set multicycle path on reset, on the FPGA we do not care about the reset anyway +set_multicycle_path -from [get_pins i_rstgen_main/i_rstgen_bypass/synch_regs_q_reg[3]/C] 4 +set_multicycle_path -from [get_pins i_rstgen_main/i_rstgen_bypass/synch_regs_q_reg[3]/C] 3 -hold diff --git a/fpga/constraints/genesys-2.xdc b/fpga/constraints/genesys-2.xdc index 65e0416f19e3e88705142ea673c2f22d802bf339..79668f4db55198ae19434ce7404d4e248835cae4 100644 --- a/fpga/constraints/genesys-2.xdc +++ b/fpga/constraints/genesys-2.xdc @@ -1,22 +1,12 @@ ## Buttons set_property -dict {PACKAGE_PIN R19 IOSTANDARD LVCMOS33} [get_ports cpu_resetn] -## PMOD Header JC -# set_property -dict {PACKAGE_PIN AC26 IOSTANDARD LVCMOS33} [get_ports tck] -# set_property -dict {PACKAGE_PIN AJ27 IOSTANDARD LVCMOS33} [get_ports tdi] -# set_property -dict {PACKAGE_PIN AH30 IOSTANDARD LVCMOS33} [get_ports tdo] -# set_property -dict {PACKAGE_PIN AK29 IOSTANDARD LVCMOS33} [get_ports tms] -# set_property -dict {PACKAGE_PIN AD26 IOSTANDARD LVCMOS33} [get_ports trst_n] -# accept sub-optimal placement -# set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets tck_IBUF] - - ## To use FTDI FT2232 JTAG -set_property -dict { PACKAGE_PIN Y29 IOSTANDARD LVCMOS33 } [get_ports { trst_n }]; -set_property -dict { PACKAGE_PIN AD27 IOSTANDARD LVCMOS33 } [get_ports { tck }]; -set_property -dict { PACKAGE_PIN W27 IOSTANDARD LVCMOS33 } [get_ports { tdi }]; -set_property -dict { PACKAGE_PIN W28 IOSTANDARD LVCMOS33 } [get_ports { tdo }]; -set_property -dict { PACKAGE_PIN W29 IOSTANDARD LVCMOS33 } [get_ports { tms }]; +set_property -dict { PACKAGE_PIN Y29 IOSTANDARD LVCMOS33 } [get_ports { trst_n }]; +set_property -dict { PACKAGE_PIN AD27 IOSTANDARD LVCMOS33 } [get_ports { tck }]; +set_property -dict { PACKAGE_PIN W27 IOSTANDARD LVCMOS33 } [get_ports { tdi }]; +set_property -dict { PACKAGE_PIN W28 IOSTANDARD LVCMOS33 } [get_ports { tdo }]; +set_property -dict { PACKAGE_PIN W29 IOSTANDARD LVCMOS33 } [get_ports { tms }]; ## UART set_property -dict {PACKAGE_PIN Y23 IOSTANDARD LVCMOS33} [get_ports tx] @@ -72,7 +62,8 @@ set_property -dict {PACKAGE_PIN AG12 IOSTANDARD LVCMOS15} [get_ports { eth_mdio ############################################# # Modified for 125MHz receive clock create_clock -period 8.000 -name eth_rxck [get_ports eth_rxck] -set_clock_groups -asynchronous -group [get_clocks eth_rxclk -include_generated_clocks] +set_clock_groups -asynchronous -group [get_clocks eth_rxck -include_generated_clocks] +set_clock_groups -asynchronous -group [get_clocks clk_out2_xlnx_clk_gen] ## SD Card set_property -dict {PACKAGE_PIN R28 IOSTANDARD LVCMOS33} [get_ports spi_clk_o] @@ -85,13 +76,12 @@ set_property BITSTREAM.CONFIG.SPI_BUSWIDTH 4 [current_design] ## JTAG # minimize routing delay -set_max_delay -to [get_ports { td } ] 5 -set_max_delay -from [get_ports { tms } ] 5 -set_max_delay -from [get_ports { trst_n } ] 5 -# reset signal -set_false_path -from [get_ports { trst_n } ] +set_max_delay -to [get_ports { tdo } ] 20 +set_max_delay -from [get_ports { tms } ] 20 +set_max_delay -from [get_ports { tdi } ] 20 +set_max_delay -from [get_ports { trst_n } ] 20 -# constrain clock domain crossing -set_false_path -from [get_clocks tck] -to [get_clocks clk_out1] -set_max_delay -from [get_clocks tck] -to [get_clocks clk_out1] 5 +# reset signal +set_false_path -from [get_ports { trst_n } ] +set_false_path -from [get_pins i_ddr/u_xlnx_mig_7_ddr3_mig/u_ddr3_infrastructure/rstdiv0_sync_r1_reg_rep/C] diff --git a/fpga/scripts/prologue.tcl b/fpga/scripts/prologue.tcl index ab456860d0041f69a19c448b81e37e0d46cd49ac..a78e2ec9b58e5d86e979255c50304cf107cc5cd3 100644 --- a/fpga/scripts/prologue.tcl +++ b/fpga/scripts/prologue.tcl @@ -22,4 +22,6 @@ set_property board_part $::env(XILINX_BOARD) [current_project] # set number of threads to 8 (maximum, unfortunately) set_param general.maxThreads 8 -set_msg_config -id {[Synth 8-5858]} -new_severity "info" +set_msg_config -id {[Synth 8-5858]} -new_severity "info" + +set_msg_config -id {[Synth 8-4480]} -limit 1000 \ No newline at end of file diff --git a/fpga/scripts/run.tcl b/fpga/scripts/run.tcl index eb21ba8b8714734831e424754670944124f7e7d4..e4f771733a862eaf0fef142e551ff513596569d2 100644 --- a/fpga/scripts/run.tcl +++ b/fpga/scripts/run.tcl @@ -29,13 +29,14 @@ source scripts/add_sources.tcl set_property top ${project}_xilinx [current_fileset] if {$::env(BOARD) eq "genesys2"} { - read_verilog -sv {src/genesysii.svh} + read_verilog -sv {src/genesysii.svh ../src/common_cells/include/common_cells/registers.svh} set file "src/genesysii.svh" + set registers "../src/common_cells/include/common_cells/registers.svh" } else { exit 1 } -set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]] +set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file" "*$registers"]] set_property -dict { file_type {Verilog Header} is_global_include 1} -objects $file_obj update_compile_order -fileset sources_1 @@ -46,6 +47,8 @@ add_files -fileset constrs_1 -norecurse constraints/$project.xdc # synth_design -retiming -rtl -name rtl_1 -verilog_define SYNTHESIS -verilog_define synth_design -rtl -name rtl_1 +set_property STEPS.SYNTH_DESIGN.ARGS.RETIMING true [get_runs synth_1] + launch_runs synth_1 wait_on_run synth_1 open_run synth_1 diff --git a/fpga/src/bootrom/ariane.dts b/fpga/src/bootrom/ariane.dts index 0f0fb0f578a891e36fbc398547fa1bc1658c53db..9711494c9f0c881e49fcc06907d582fee324839a 100644 --- a/fpga/src/bootrom/ariane.dts +++ b/fpga/src/bootrom/ariane.dts @@ -13,12 +13,12 @@ #size-cells = <0>; timebase-frequency = <25000000>; // 25 MHz CPU0: cpu@0 { - clock-frequency = <50000000>; // 50 MHz + clock-frequency = <30000000>; // 30 MHz device_type = "cpu"; reg = <0>; status = "okay"; compatible = "eth, ariane", "riscv"; - riscv,isa = "rv64imacsu"; + riscv,isa = "rv64imafdc"; mmu-type = "riscv,sv39"; tlb-split; // HLIC - hart local interrupt controller @@ -71,7 +71,7 @@ uart@10000000 { compatible = "ns16750"; reg = <0x0 0x10000000 0x0 0x1000>; - clock-frequency = <50000000>; + clock-frequency = <30000000>; current-speed = <115200>; interrupt-parent = <&PLIC0>; interrupts = <1>; diff --git a/fpga/src/bootrom/bootrom.h b/fpga/src/bootrom/bootrom.h index e4c45de4fc9fa57a88d5c306f0ba63ace71b5fc2..840467648d682ddfa2a0ad9cb7698aab07a2991d 100644 --- a/fpga/src/bootrom/bootrom.h +++ b/fpga/src/bootrom/bootrom.h @@ -10,7 +10,7 @@ uint32_t reset_vec[reset_vec_size] = { 0x03249663, 0x0210011b, 0x01a11113, - 0x24d000ef, + 0x25f000ef, 0x020004b7, 0x00100913, 0x0124a023, @@ -79,608 +79,616 @@ uint32_t reset_vec[reset_vec_size] = { 0x0207f793, 0x0023dfe5, 0x808200a7, + 0x0045959b, + 0x02b5553b, 0x100007b7, 0x00078223, 0xf8000713, 0x00e78623, - 0x8023476d, - 0x822300e7, - 0x470d0007, - 0x00e78623, - 0xfc700713, - 0x00e78423, - 0x02000713, - 0x00e78823, - 0x11418082, - 0xe406e022, - 0x4503842a, - 0xe5090004, - 0x640260a2, - 0x80820141, - 0xfa5ff0ef, - 0xb7f50405, - 0x00001797, - 0x98078793, - 0x00f57713, - 0x4703973e, - 0x81110007, - 0x80a397aa, - 0xc78300e5, - 0x80230007, - 0x808200f5, - 0xf0227179, - 0xe84aec26, - 0x892af406, - 0x54e14461, - 0x0089553b, - 0x7513002c, - 0xf0ef0ff5, - 0x4503fc3f, - 0x34610081, - 0xf55ff0ef, - 0x00914503, - 0xf4dff0ef, - 0xfe9410e3, - 0x740270a2, - 0x694264e2, - 0x80826145, - 0xf0227179, - 0xe84aec26, - 0x892af406, - 0x03800413, - 0x553354e1, + 0x0ff57713, + 0x0085551b, + 0x00e78023, + 0x0ff57513, + 0x00a78223, + 0x8623470d, + 0x071300e7, + 0x8423fc70, + 0x071300e7, + 0x88230200, + 0x808200e7, + 0xe0221141, + 0x842ae406, + 0x00044503, + 0x60a2e509, + 0x01416402, + 0xf0ef8082, + 0x0405f93f, + 0x1797b7f5, + 0x87930000, + 0x771396e7, + 0x973e00f5, + 0x00074703, + 0x97aa8111, + 0x00e580a3, + 0x0007c783, + 0x00f58023, + 0x71798082, + 0xec26f022, + 0xf406e84a, + 0x4461892a, + 0x553b54e1, 0x002c0089, 0x0ff57513, - 0xf81ff0ef, + 0xfc3ff0ef, 0x00814503, 0xf0ef3461, - 0x4503f13f, + 0x4503f43f, 0xf0ef0091, - 0x10e3f0bf, + 0x10e3f3bf, 0x70a2fe94, 0x64e27402, 0x61456942, - 0x11018082, - 0xec06002c, - 0xf55ff0ef, - 0x00814503, - 0xee9ff0ef, + 0x71798082, + 0xec26f022, + 0xf406e84a, + 0x0413892a, + 0x54e10380, + 0x00895533, + 0x7513002c, + 0xf0ef0ff5, + 0x4503f81f, + 0x34610081, + 0xf01ff0ef, 0x00914503, - 0xee1ff0ef, - 0x610560e2, - 0xc10c8082, - 0x41088082, - 0x15178082, - 0x11010000, - 0x5d250513, - 0xe822ec06, - 0xf0efe426, - 0x07b7f05f, - 0x47292000, - 0x47a9c3b8, - 0x37fd0001, - 0x0437fff5, - 0x07932000, - 0xd03c1040, - 0x15175064, - 0x05130000, - 0xf0ef5b25, - 0x2481eddf, - 0x02049513, - 0xf0ef9101, - 0x1517f53f, - 0x05130000, - 0xf0ef5ba5, - 0x0793ec5f, - 0xd03c1660, - 0x15175064, - 0x05130000, - 0xf0ef5865, - 0x2481eb1f, - 0x02049513, - 0xf0ef9101, - 0x1517f27f, - 0x05130000, - 0xf0ef58e5, - 0x4799e99f, - 0x6442d03c, - 0x64a260e2, + 0xef9ff0ef, + 0xfe9410e3, + 0x740270a2, + 0x694264e2, + 0x80826145, + 0x002c1101, + 0xf0efec06, + 0x4503f55f, + 0xf0ef0081, + 0x4503ed7f, + 0xf0ef0091, + 0x60e2ecff, + 0x80826105, + 0x8082c10c, + 0x80824108, 0x00001517, - 0x56850513, - 0xf06f6105, - 0x1101e81f, + 0x05131101, + 0xec065c05, + 0xe426e822, + 0xf05ff0ef, 0x200007b7, - 0xe822ec06, - 0x5779e426, - 0xd7a8dbb8, - 0x06400793, - 0x37fd0001, - 0x07b7fff5, - 0x07132000, - 0xd3b81060, - 0x849353f8, - 0x8b050647, - 0x57e0ff65, - 0x240153fc, - 0xe3958b85, + 0xc3b84729, + 0x000147a9, + 0xfff537fd, + 0x20000437, + 0x10400793, + 0x5064d03c, + 0x00001517, + 0x5a050513, + 0xeddff0ef, + 0x95132481, + 0x91010204, + 0xf53ff0ef, 0x00001517, - 0x53850513, - 0xe3bff0ef, - 0x15024088, - 0xf0ef9101, - 0x1517eb3f, + 0x5a850513, + 0xec5ff0ef, + 0x16600793, + 0x5064d03c, + 0x00001517, + 0x57450513, + 0xeb1ff0ef, + 0x95132481, + 0x91010204, + 0xf27ff0ef, + 0x00001517, + 0x57c50513, + 0xe99ff0ef, + 0xd03c4799, + 0x60e26442, + 0x151764a2, 0x05130000, - 0xf0ef51a5, - 0x07b7e25f, - 0x577d2000, - 0x0ff47513, - 0x644260e2, - 0x4719dbb8, - 0x64a2d3b8, - 0x80826105, - 0x10000793, - 0x06b7ec63, - 0x200007b7, + 0x61055565, + 0xe81ff06f, + 0x07b71101, + 0xec062000, + 0xe426e822, 0xdbb85779, - 0x200006b7, - 0x873b87aa, - 0x616340a7, - 0x079304b7, - 0x00010320, + 0x0793d7a8, + 0x00010640, 0xfff537fd, - 0x10600713, - 0x200007b7, - 0x0737d3b8, - 0x537c2000, - 0xfff58b85, - 0x20000537, - 0x20000837, - 0x0007869b, - 0x00b6ef63, 0x200007b7, - 0xdbb8577d, - 0xd3b84719, - 0x80824501, - 0x0007c703, - 0xd6b80785, - 0x5178bf4d, - 0xff798b05, - 0x06c82683, - 0x00f60733, - 0x00230785, - 0xb7e900d7, - 0x8082557d, - 0x0ff00513, - 0xf07ff06f, - 0xf4067179, - 0xf022e432, - 0x842eec26, - 0xf0ef84aa, - 0xe513febf, - 0xf0ef0404, - 0x551beedf, - 0x75130184, - 0xf0ef0ff5, - 0x551bee1f, - 0x75130104, - 0xf0ef0ff5, - 0x551bed5f, - 0x75130084, - 0xf0ef0ff5, - 0x7513ec9f, - 0xf0ef0ff4, - 0x6622ec1f, - 0x06400413, - 0xf0ef8532, - 0xf0efeb5f, - 0x179bfa7f, - 0xd79b0185, - 0xd4634187, - 0x147d0007, - 0x70a2f47d, - 0x64e27402, - 0x80826145, - 0xe8221101, - 0x1517842a, + 0x10600713, + 0x53f8d3b8, + 0x06478493, + 0xff658b05, + 0x53fc57e0, + 0x8b852401, + 0x1517e395, 0x05130000, - 0xec064165, - 0xf0efe42e, - 0x8522cfdf, - 0xcf7ff0ef, + 0xf0ef5265, + 0x4088e3bf, + 0x91011502, + 0xeb3ff0ef, 0x00001517, - 0x41050513, - 0xcebff0ef, - 0x852e65a2, - 0xda7ff0ef, - 0x60e26442, - 0x00001517, - 0x3c850513, - 0xf06f6105, - 0x1101cd1f, - 0x6409e822, - 0xec06e426, - 0x0413e04a, - 0x44857104, - 0x09500613, - 0x45014581, - 0xf35ff0ef, - 0x892a347d, - 0xf25ff0ef, - 0x15e3c00d, - 0x1517fe99, - 0x05130000, - 0x45853ce5, - 0xf89ff0ef, - 0x60e24505, - 0x64a26442, - 0x61056902, - 0x45018082, - 0x1101bfcd, - 0x08700613, - 0x1aa00593, - 0xec064521, - 0xe426e822, - 0xf0efe04a, - 0x892aeeff, + 0x50850513, + 0xe25ff0ef, + 0x200007b7, + 0x7513577d, + 0x60e20ff4, + 0xdbb86442, + 0xd3b84719, + 0x610564a2, + 0x07938082, + 0xec631000, + 0x07b706b7, + 0x57792000, + 0x06b7dbb8, + 0x87aa2000, + 0x40a7873b, + 0x04b76163, + 0x03200793, + 0x37fd0001, + 0x0713fff5, + 0x07b71060, + 0xd3b82000, + 0x20000737, + 0x8b85537c, + 0x0537fff5, + 0x08372000, + 0x869b2000, + 0xef630007, + 0x07b700b6, + 0x577d2000, + 0x4719dbb8, + 0x4501d3b8, + 0xc7038082, + 0x07850007, + 0xbf4dd6b8, + 0x8b055178, + 0x2683ff79, + 0x073306c8, + 0x078500f6, + 0x00d70023, + 0x557db7e9, + 0x05138082, + 0xf06f0ff0, + 0x7179f07f, + 0xe432f406, + 0xec26f022, + 0x84aa842e, + 0xfebff0ef, + 0x0404e513, + 0xeedff0ef, + 0x0184551b, + 0x0ff57513, 0xee1ff0ef, - 0xeddff0ef, - 0xed9ff0ef, - 0xf0ef84aa, - 0x842aed3f, - 0xecdff0ef, + 0x0104551b, + 0x0ff57513, + 0xed5ff0ef, + 0x0084551b, + 0x0ff57513, 0xec9ff0ef, - 0x45014785, - 0x00f91b63, - 0x986388bd, - 0x051b0124, - 0x05130004, - 0x3513f565, - 0x60e20015, - 0x64a26442, - 0x61056902, - 0x11418082, - 0x06500613, - 0x05134581, - 0xe4060370, - 0xf0efe022, - 0x842ae97f, - 0xe89ff0ef, + 0x0ff47513, + 0xec1ff0ef, + 0x04136622, + 0x85320640, + 0xeb5ff0ef, + 0xfa7ff0ef, + 0x0185179b, + 0x4187d79b, + 0x0007d463, + 0xf47d147d, + 0x740270a2, + 0x614564e2, + 0x11018082, + 0x842ae822, 0x00001517, - 0x051385a2, - 0xf0ef3405, - 0x051bef3f, - 0x60a20004, - 0x157d6402, - 0x00153513, - 0x80820141, - 0xe4261101, - 0xe822ec06, - 0xf0ef4485, - 0x0613fbdf, - 0x05b70770, - 0x05134000, - 0xf0ef0290, - 0x842ae53f, - 0x151785aa, + 0x40450513, + 0xe42eec06, + 0xcfdff0ef, + 0xf0ef8522, + 0x1517cf7f, + 0x05130000, + 0xf0ef3fe5, + 0x65a2cebf, + 0xf0ef852e, + 0x6442da7f, + 0x151760e2, 0x05130000, - 0xf0ef3065, - 0xf0efeb3f, - 0x0ce3e37f, - 0x051bfc94, - 0x60e20004, - 0x64a26442, + 0x61053b65, + 0xcd1ff06f, + 0xe8221101, + 0xe4266409, + 0xe04aec06, + 0x71040413, + 0x06134485, + 0x45810950, + 0xf0ef4501, + 0x347df35f, + 0xf0ef892a, + 0xc00df25f, + 0xfe9915e3, + 0x00001517, + 0x3bc50513, + 0xf0ef4585, + 0x4505f89f, + 0x644260e2, + 0x690264a2, + 0x80826105, + 0xbfcd4501, + 0x06131101, + 0x05930870, + 0x45211aa0, + 0xe822ec06, + 0xe04ae426, + 0xeefff0ef, + 0xf0ef892a, + 0xf0efee1f, + 0xf0efeddf, + 0x84aaed9f, + 0xed3ff0ef, + 0xf0ef842a, + 0xf0efecdf, + 0x4785ec9f, + 0x1b634501, + 0x88bd00f9, + 0x01249863, + 0x0004051b, + 0xf5650513, 0x00153513, + 0x644260e2, + 0x690264a2, 0x80826105, - 0xe4061141, - 0xf0efe022, - 0x1517c89f, - 0x05130000, - 0xf0ef2de5, - 0x4429b91f, - 0xf0ef347d, - 0xfc6de03f, - 0xeb7ff0ef, - 0xc91157fd, - 0xefbff0ef, - 0xc51157f9, - 0xf89ff0ef, - 0xc11157f5, - 0x60a24781, - 0x853e6402, - 0x80820141, - 0xd79b8de9, - 0xd51b0075, - 0x8d3d0045, - 0x15938d2d, - 0x8d2d0045, - 0x07f57513, - 0x579b8082, - 0x05220085, - 0x15428d5d, - 0x8da99141, + 0x06131141, + 0x45810650, + 0x03700513, + 0xe022e406, + 0xe97ff0ef, + 0xf0ef842a, + 0x1517e89f, + 0x85a20000, + 0x32e50513, + 0xef3ff0ef, + 0x0004051b, + 0x640260a2, + 0x3513157d, + 0x01410015, + 0x11018082, + 0xec06e426, + 0x4485e822, + 0xfbdff0ef, + 0x07700613, + 0x400005b7, + 0x02900513, + 0xe53ff0ef, + 0x85aa842a, + 0x00001517, + 0x2f450513, + 0xeb3ff0ef, + 0xe37ff0ef, + 0xfc940ce3, + 0x0004051b, + 0x644260e2, + 0x351364a2, + 0x61050015, + 0x11418082, + 0xe022e406, + 0xc89ff0ef, + 0x00001517, + 0x2cc50513, + 0xb91ff0ef, + 0x347d4429, + 0xe03ff0ef, + 0xf0effc6d, + 0x57fdeb7f, + 0xf0efc911, + 0x57f9efbf, + 0xf0efc511, + 0x57f5f89f, + 0x4781c111, + 0x640260a2, + 0x0141853e, + 0x8de98082, + 0x0075d79b, 0x0045d51b, - 0x8da9893d, - 0x00c59513, - 0x151b8d2d, - 0x551b0105, - 0x179b4105, - 0xd79b0105, - 0x67090107, - 0x979b1701, - 0x8ff90057, - 0x15428d3d, - 0x80829141, - 0xf54e7155, - 0x02061993, - 0xfd26e1a2, - 0xf94ae586, - 0xed56f152, - 0xe55ee95a, - 0x842e84aa, - 0x0209d993, - 0x567d4781, - 0x08000713, - 0x00f106b3, - 0x00c68023, - 0x9be30785, - 0x559bfee7, - 0xf5930184, - 0x45010ff5, - 0xf69ff0ef, - 0x0104559b, - 0x0ff5f593, - 0xf5dff0ef, - 0x0084559b, + 0x8d2d8d3d, + 0x00451593, + 0x75138d2d, + 0x808207f5, + 0x0085579b, + 0x8d5d0522, + 0x91411542, + 0xd51b8da9, + 0x893d0045, + 0x95138da9, + 0x8d2d00c5, + 0x0105151b, + 0x4105551b, + 0x0105179b, + 0x0107d79b, + 0x17016709, + 0x0057979b, + 0x8d3d8ff9, + 0x91411542, + 0x71558082, + 0x1993f54e, + 0xe1a20206, + 0xe586fd26, + 0xf152f94a, + 0xe95aed56, + 0x84aae55e, + 0xd993842e, + 0x47810209, + 0x0713567d, + 0x06b30800, + 0x802300f1, + 0x078500c6, + 0xfee79be3, + 0x0184559b, 0x0ff5f593, - 0xf51ff0ef, - 0x0ff47593, - 0xf49ff0ef, - 0x0015161b, - 0x00166613, - 0x0ff67613, - 0x454985a2, - 0xd15ff0ef, - 0x0a13e951, - 0x0a930fe0, - 0xf0ef3e80, - 0x1ee3cfff, - 0x8b13ff45, - 0x84262004, - 0x86224901, - 0x04000593, + 0xf0ef4501, + 0x559bf69f, + 0xf5930104, + 0xf0ef0ff5, + 0x559bf5df, + 0xf5930084, + 0xf0ef0ff5, + 0x7593f51f, + 0xf0ef0ff4, + 0x161bf49f, + 0x66130015, + 0x76130016, + 0x85a20ff6, + 0xf0ef4549, + 0xe951d15f, + 0x0fe00a13, + 0x3e800a93, + 0xcffff0ef, + 0xff451ee3, + 0x20048b13, + 0x49018426, + 0x05938622, + 0x850a0400, + 0xc67ff0ef, + 0x0b934481, + 0x07b30400, + 0xc5830094, + 0x854a0007, + 0xf0ef0485, + 0x892af13f, + 0xff7497e3, + 0x04040413, + 0xfd641ae3, + 0xcbfff0ef, + 0x0085151b, + 0x141384a2, + 0x90410305, + 0xcafff0ef, + 0x14428c49, + 0x29019041, + 0x07241a63, + 0x0359e7b3, + 0x1517e799, + 0x05130000, + 0xf0ef18a5, + 0x19fda17f, + 0xf93046e3, + 0x46054401, + 0x45314581, + 0xc87ff0ef, + 0xc7bff0ef, + 0xf0efa805, + 0xf0efc75f, + 0xf0efc71f, + 0xf0efc6df, + 0xf0efc69f, + 0xf0efc65f, + 0xf0efc61f, + 0xf0efc5df, + 0x1517c59f, + 0x05130000, + 0xf0ef1265, + 0x547d9d3f, + 0x60ae8522, + 0x74ea640e, + 0x79aa794a, + 0x6aea7a0a, + 0x6baa6b4a, + 0x80826169, + 0xb7655479, + 0xe0a2715d, + 0xe85af052, + 0xfc26e486, + 0xf44ef84a, + 0xe45eec56, + 0x0880e062, + 0x8b2e8a2a, + 0xdf3ff0ef, + 0x1517c51d, + 0x05130000, + 0xf0ef1025, + 0x54fd987f, + 0xfb040113, + 0x852660a6, + 0x74e26406, + 0x79a27942, + 0x6ae27a02, + 0x6ba26b42, + 0x61616c02, + 0x15178082, + 0x05130000, + 0xf0ef0fe5, + 0x710195bf, + 0x45854605, 0xf0ef850a, - 0x4481c67f, - 0x04000b93, - 0x009407b3, - 0x0007c583, - 0x0485854a, - 0xf13ff0ef, - 0x97e3892a, - 0x0413ff74, - 0x1ae30404, - 0xf0effd64, - 0x151bcbff, - 0x84a20085, - 0x03051413, - 0xf0ef9041, - 0x8c49caff, - 0x90411442, - 0x1a632901, - 0xe7b30724, - 0xe7990359, - 0x00001517, - 0x19c50513, - 0xa17ff0ef, - 0x46e319fd, - 0x4401f930, - 0x45814605, - 0xf0ef4531, - 0xf0efc87f, - 0xa805c7bf, - 0xc75ff0ef, - 0xc71ff0ef, - 0xc6dff0ef, - 0xc69ff0ef, - 0xc65ff0ef, - 0xc61ff0ef, - 0xc5dff0ef, - 0xc59ff0ef, + 0x890ae49f, + 0xc90584aa, 0x00001517, - 0x13850513, - 0x9d3ff0ef, - 0x8522547d, - 0x640e60ae, - 0x794a74ea, - 0x7a0a79aa, - 0x6b4a6aea, - 0x61696baa, - 0x54798082, - 0x715db765, - 0xf052e0a2, - 0xe486e85a, - 0xf84afc26, - 0xec56f44e, - 0xe062e45e, - 0x8a2a0880, - 0xf0ef8b2e, - 0xc51ddf3f, - 0x00001517, - 0x11450513, - 0x987ff0ef, - 0x011354fd, - 0x60a6fb04, - 0x64068526, - 0x794274e2, - 0x7a0279a2, - 0x6b426ae2, - 0x6c026ba2, - 0x80826161, + 0x0f850513, + 0x93dff0ef, 0x00001517, - 0x11050513, - 0x95bff0ef, - 0x46057101, - 0x850a4585, - 0xe49ff0ef, - 0x84aa890a, - 0x1517c905, + 0x10450513, + 0x931ff0ef, + 0xf0ef8526, + 0x15179adf, 0x05130000, - 0xf0ef10a5, - 0x151793df, + 0xf0ef0025, + 0x54f991ff, + 0x1517bf61, 0x05130000, - 0xf0ef1165, - 0x8526931f, - 0x9adff0ef, - 0x00001517, - 0x01450513, - 0x91fff0ef, - 0xbf6154f9, - 0x00001517, - 0x10c50513, - 0x90fff0ef, + 0xf0ef0fa5, + 0x151790ff, + 0x05130000, + 0xf0ef10e5, + 0x6502903f, + 0xf0ef4b91, + 0x151797df, + 0x05130000, + 0xf0ef10a5, + 0x45228eff, + 0x92bff0ef, 0x00001517, - 0x12050513, - 0x903ff0ef, - 0x4b916502, - 0x97dff0ef, + 0x10850513, + 0x8ddff0ef, + 0xf0ef4532, + 0x1517919f, + 0x05130000, + 0xf0ef1065, + 0x45428cbf, + 0x907ff0ef, 0x00001517, - 0x11c50513, - 0x8efff0ef, - 0xf0ef4522, - 0x151792bf, + 0x10450513, + 0x8b9ff0ef, + 0xf0ef4552, + 0x15178f5f, 0x05130000, - 0xf0ef11a5, - 0x45328ddf, - 0x919ff0ef, + 0xf0ef1025, + 0x65628a7f, + 0x923ff0ef, 0x00001517, - 0x11850513, - 0x8cbff0ef, - 0xf0ef4542, - 0x1517907f, + 0x10850513, + 0x895ff0ef, + 0xf0ef7502, + 0x1517911f, 0x05130000, - 0xf0ef1165, - 0x45528b9f, - 0x8f5ff0ef, + 0xf0ef1065, + 0x6526883f, + 0x8ffff0ef, 0x00001517, 0x11450513, - 0x8a7ff0ef, - 0xf0ef6562, - 0x1517923f, + 0x871ff0ef, + 0xf0ef4546, + 0x15178adf, 0x05130000, - 0xf0ef11a5, - 0x7502895f, - 0x911ff0ef, + 0xf0ef1225, + 0x455685ff, + 0x89bff0ef, 0x00001517, - 0x11850513, - 0x883ff0ef, - 0xf0ef6526, - 0x15178fff, + 0xf3050513, + 0x84dff0ef, + 0x04892583, + 0x46057101, + 0xf0ef850a, + 0x8a8ad39f, + 0x080489aa, + 0x1517c50d, 0x05130000, - 0xf0ef1265, - 0x4546871f, - 0x8adff0ef, - 0x00001517, - 0x13450513, - 0x85fff0ef, - 0xf0ef4556, - 0x151789bf, + 0xf0effe65, + 0x151782bf, 0x05130000, - 0xf0eff425, - 0x258384df, - 0x71010489, - 0x850a4605, - 0xd39ff0ef, - 0x89aa8a8a, - 0xc50d0804, + 0xf0efff25, + 0x854e81ff, + 0x89bff0ef, 0x00001517, - 0xff850513, - 0x82bff0ef, + 0xef050513, + 0x1517b5fd, + 0x05130000, + 0xf0ef0e65, + 0xf513803f, + 0xf0ef0ff9, + 0x15178bff, + 0x05130000, + 0xf0ef0ea5, + 0x8913feef, + 0x4503ff04, + 0x09050009, + 0x8a5ff0ef, + 0xfe991be3, 0x00001517, - 0x00450513, - 0x81fff0ef, - 0xf0ef854e, - 0x151789bf, + 0x0ec50513, + 0xfd0ff0ef, + 0x01090c13, + 0x00094503, + 0xf0ef0905, + 0x1be3887f, + 0x1517ff2c, 0x05130000, - 0xb5fdf025, + 0xf0ef0ee5, + 0x6888fb2f, + 0x02848913, + 0x07048c13, + 0x827ff0ef, 0x00001517, - 0x0f850513, + 0x0e450513, + 0xf98ff0ef, + 0xf0ef6c88, + 0x1517815f, + 0x05130000, + 0xf0ef0e25, + 0x7088f86f, 0x803ff0ef, - 0x0ff9f513, - 0x8bfff0ef, 0x00001517, - 0x0fc50513, - 0xfeeff0ef, - 0xff048913, + 0x0e050513, + 0xf74ff0ef, 0x00094503, 0xf0ef0905, - 0x1be38a5f, - 0x1517fe99, + 0x1be382ff, + 0x1517ff2c, 0x05130000, - 0xf0ef0fe5, - 0x0c13fd0f, - 0x45030109, - 0x09050009, - 0x887ff0ef, - 0xff2c1be3, + 0x2985e3e5, + 0xf58ff0ef, + 0x08048493, + 0xf57993e3, 0x00001517, - 0x10050513, - 0xfb2ff0ef, - 0x89136888, - 0x8c130284, - 0xf0ef0704, - 0x1517827f, - 0x05130000, - 0xf0ef0f65, - 0x6c88f98f, - 0x815ff0ef, + 0x0c050513, + 0xf44ff0ef, + 0x020aa583, + 0x8552865a, + 0xc33ff0ef, + 0xc50d84aa, 0x00001517, - 0x0f450513, - 0xf86ff0ef, - 0xf0ef7088, - 0x1517803f, - 0x05130000, - 0xf0ef0f25, - 0x4503f74f, - 0x09050009, - 0x82fff0ef, - 0xff2c1be3, + 0xee450513, + 0xf28ff0ef, 0x00001517, - 0xe5050513, - 0xf0ef2985, - 0x8493f58f, - 0x93e30804, - 0x1517f579, + 0xef050513, + 0xf1cff0ef, + 0xf0ef8526, + 0x1517f98f, 0x05130000, - 0xf0ef0d25, - 0xa583f44f, - 0x865a020a, - 0xf0ef8552, - 0x84aac33f, - 0x1517c50d, - 0x05130000, - 0xf0efef65, - 0x1517f28f, - 0x05130000, - 0xf0eff025, - 0x8526f1cf, - 0xf98ff0ef, + 0xb3f5dee5, 0x00001517, - 0xe0050513, - 0x1517b3f5, - 0x05130000, - 0xf0ef0a65, - 0xbbb5f00f, - 0xe4061141, - 0xec4ff0ef, + 0x09450513, + 0xf00ff0ef, + 0x65f1bbb5, + 0x01c9c537, + 0x85931141, + 0x05132005, + 0xe4063805, + 0xea4ff0ef, 0x00001517, - 0xda050513, - 0xeeaff0ef, + 0xd8050513, + 0xedcff0ef, 0x65a14505, 0xf0ef057e, - 0xe911d31f, + 0xe911d23f, 0x0010041b, 0x01f41413, 0x00000597, - 0x17058593, + 0x15058593, 0xa0018402, 0x00000000, 0x00000000, @@ -699,14 +707,6 @@ uint32_t reset_vec[reset_vec_size] = { 0x00000000, 0x00000000, 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, 0x33323130, 0x37363534, 0x42413938, @@ -845,7 +845,7 @@ uint32_t reset_vec[reset_vec_size] = { 0x03000000, 0x04000000, 0x4b000000, - 0x80f0fa02, + 0x80c3c901, 0x03000000, 0x04000000, 0x5b000000, @@ -871,8 +871,8 @@ uint32_t reset_vec[reset_vec_size] = { 0x0b000000, 0x72000000, 0x34367672, - 0x63616d69, - 0x00007573, + 0x66616d69, + 0x00006364, 0x03000000, 0x0b000000, 0x7c000000, @@ -930,7 +930,7 @@ uint32_t reset_vec[reset_vec_size] = { 0x00000000, 0x00000080, 0x00000000, - 0x00000008, + 0x00000040, 0x02000000, 0x01000000, 0x7364656c, @@ -1127,7 +1127,7 @@ uint32_t reset_vec[reset_vec_size] = { 0x03000000, 0x04000000, 0x4b000000, - 0x80f0fa02, + 0x80c3c901, 0x03000000, 0x04000000, 0x39010000, @@ -1271,8 +1271,8 @@ uint32_t reset_vec[reset_vec_size] = { 0x03000000, 0x06000000, 0xf9010000, - 0xe3e2e1ee, - 0x0000e5e4, + 0x023e1800, + 0x00007fe3, 0x03000000, 0x10000000, 0x67000000, diff --git a/fpga/src/bootrom/bootrom.sv b/fpga/src/bootrom/bootrom.sv index fce47b39013270e13e06f12626562137eeb7f314..b59bad47a6af14e19a9d0e44c512c33e64cb4712 100644 --- a/fpga/src/bootrom/bootrom.sv +++ b/fpga/src/bootrom/bootrom.sv @@ -254,7 +254,7 @@ module bootrom ( 64'h00000000_00000030, 64'h00000000_67000000, 64'h10000000_03000000, - 64'h0000e5e4_e3e2e1ee, + 64'h00007fe3_023e1800, 64'hf9010000_06000000, 64'h03000000_00000000, 64'h03000000_58010000, @@ -326,7 +326,7 @@ module bootrom ( 64'h47010000_04000000, 64'h03000000_00c20100, 64'h39010000_04000000, - 64'h03000000_80f0fa02, + 64'h03000000_80c3c901, 64'h4b000000_04000000, 64'h03000000_00100000, 64'h00000000_00000010, @@ -425,7 +425,7 @@ module bootrom ( 64'h0a000000_03000000, 64'h00000000_7364656c, 64'h01000000_02000000, - 64'h00000008_00000000, + 64'h00000040_00000000, 64'h00000080_00000000, 64'h67000000_10000000, 64'h03000000_00007972, @@ -454,7 +454,7 @@ module bootrom ( 64'h00003933_76732c76, 64'h63736972_7c000000, 64'h0b000000_03000000, - 64'h00007573_63616d69, + 64'h00006364_66616d69, 64'h34367672_72000000, 64'h0b000000_03000000, 64'h00000076_63736972, @@ -467,7 +467,7 @@ module bootrom ( 64'h67000000_04000000, 64'h03000000_00757063, 64'h5b000000_04000000, - 64'h03000000_80f0fa02, + 64'h03000000_80c3c901, 64'h4b000000_04000000, 64'h03000000_00000030, 64'h40757063_01000000, @@ -545,312 +545,312 @@ module bootrom ( 64'h00000000_00000000, 64'h00000000_00000000, 64'h00000000_00000000, - 64'h00000000_00000000, - 64'h00000000_00000000, - 64'h00000000_00000000, - 64'h00000000_00000000, 64'h00000000_a0018402, - 64'h17058593_00000597, + 64'h15058593_00000597, 64'h01f41413_0010041b, - 64'he911d31f_f0ef057e, - 64'h65a14505_eeaff0ef, - 64'hda050513_00001517, - 64'hec4ff0ef_e4061141, - 64'hbbb5f00f_f0ef0a65, - 64'h05130000_1517b3f5, - 64'he0050513_00001517, - 64'hf98ff0ef_8526f1cf, - 64'hf0eff025_05130000, - 64'h1517f28f_f0efef65, + 64'he911d23f_f0ef057e, + 64'h65a14505_edcff0ef, + 64'hd8050513_00001517, + 64'hea4ff0ef_e4063805, + 64'h05132005_85931141, + 64'h01c9c537_65f1bbb5, + 64'hf00ff0ef_09450513, + 64'h00001517_b3f5dee5, + 64'h05130000_1517f98f, + 64'hf0ef8526_f1cff0ef, + 64'hef050513_00001517, + 64'hf28ff0ef_ee450513, + 64'h00001517_c50d84aa, + 64'hc33ff0ef_8552865a, + 64'h020aa583_f44ff0ef, + 64'h0c050513_00001517, + 64'hf57993e3_08048493, + 64'hf58ff0ef_2985e3e5, + 64'h05130000_1517ff2c, + 64'h1be382ff_f0ef0905, + 64'h00094503_f74ff0ef, + 64'h0e050513_00001517, + 64'h803ff0ef_7088f86f, + 64'hf0ef0e25_05130000, + 64'h1517815f_f0ef6c88, + 64'hf98ff0ef_0e450513, + 64'h00001517_827ff0ef, + 64'h07048c13_02848913, + 64'h6888fb2f_f0ef0ee5, + 64'h05130000_1517ff2c, + 64'h1be3887f_f0ef0905, + 64'h00094503_01090c13, + 64'hfd0ff0ef_0ec50513, + 64'h00001517_fe991be3, + 64'h8a5ff0ef_09050009, + 64'h4503ff04_8913feef, + 64'hf0ef0ea5_05130000, + 64'h15178bff_f0ef0ff9, + 64'hf513803f_f0ef0e65, + 64'h05130000_1517b5fd, + 64'hef050513_00001517, + 64'h89bff0ef_854e81ff, + 64'hf0efff25_05130000, + 64'h151782bf_f0effe65, 64'h05130000_1517c50d, - 64'h84aac33f_f0ef8552, - 64'h865a020a_a583f44f, - 64'hf0ef0d25_05130000, - 64'h1517f579_93e30804, - 64'h8493f58f_f0ef2985, - 64'he5050513_00001517, - 64'hff2c1be3_82fff0ef, - 64'h09050009_4503f74f, - 64'hf0ef0f25_05130000, - 64'h1517803f_f0ef7088, - 64'hf86ff0ef_0f450513, - 64'h00001517_815ff0ef, - 64'h6c88f98f_f0ef0f65, - 64'h05130000_1517827f, - 64'hf0ef0704_8c130284, - 64'h89136888_fb2ff0ef, - 64'h10050513_00001517, - 64'hff2c1be3_887ff0ef, - 64'h09050009_45030109, - 64'h0c13fd0f_f0ef0fe5, - 64'h05130000_1517fe99, - 64'h1be38a5f_f0ef0905, - 64'h00094503_ff048913, - 64'hfeeff0ef_0fc50513, - 64'h00001517_8bfff0ef, - 64'h0ff9f513_803ff0ef, - 64'h0f850513_00001517, - 64'hb5fdf025_05130000, - 64'h151789bf_f0ef854e, - 64'h81fff0ef_00450513, - 64'h00001517_82bff0ef, - 64'hff850513_00001517, - 64'hc50d0804_89aa8a8a, - 64'hd39ff0ef_850a4605, - 64'h71010489_258384df, - 64'hf0eff425_05130000, - 64'h151789bf_f0ef4556, - 64'h85fff0ef_13450513, - 64'h00001517_8adff0ef, - 64'h4546871f_f0ef1265, - 64'h05130000_15178fff, - 64'hf0ef6526_883ff0ef, - 64'h11850513_00001517, - 64'h911ff0ef_7502895f, - 64'hf0ef11a5_05130000, - 64'h1517923f_f0ef6562, - 64'h8a7ff0ef_11450513, - 64'h00001517_8f5ff0ef, - 64'h45528b9f_f0ef1165, - 64'h05130000_1517907f, - 64'hf0ef4542_8cbff0ef, - 64'h11850513_00001517, - 64'h919ff0ef_45328ddf, - 64'hf0ef11a5_05130000, - 64'h151792bf_f0ef4522, - 64'h8efff0ef_11c50513, - 64'h00001517_97dff0ef, - 64'h4b916502_903ff0ef, - 64'h12050513_00001517, - 64'h90fff0ef_10c50513, - 64'h00001517_bf6154f9, - 64'h91fff0ef_01450513, - 64'h00001517_9adff0ef, - 64'h8526931f_f0ef1165, - 64'h05130000_151793df, + 64'h080489aa_8a8ad39f, + 64'hf0ef850a_46057101, + 64'h04892583_84dff0ef, + 64'hf3050513_00001517, + 64'h89bff0ef_455685ff, + 64'hf0ef1225_05130000, + 64'h15178adf_f0ef4546, + 64'h871ff0ef_11450513, + 64'h00001517_8ffff0ef, + 64'h6526883f_f0ef1065, + 64'h05130000_1517911f, + 64'hf0ef7502_895ff0ef, + 64'h10850513_00001517, + 64'h923ff0ef_65628a7f, + 64'hf0ef1025_05130000, + 64'h15178f5f_f0ef4552, + 64'h8b9ff0ef_10450513, + 64'h00001517_907ff0ef, + 64'h45428cbf_f0ef1065, + 64'h05130000_1517919f, + 64'hf0ef4532_8ddff0ef, + 64'h10850513_00001517, + 64'h92bff0ef_45228eff, 64'hf0ef10a5_05130000, - 64'h1517c905_84aa890a, - 64'he49ff0ef_850a4585, - 64'h46057101_95bff0ef, - 64'h11050513_00001517, - 64'h80826161_6c026ba2, - 64'h6b426ae2_7a0279a2, - 64'h794274e2_64068526, - 64'h60a6fb04_011354fd, - 64'h987ff0ef_11450513, - 64'h00001517_c51ddf3f, - 64'hf0ef8b2e_8a2a0880, - 64'he062e45e_ec56f44e, - 64'hf84afc26_e486e85a, - 64'hf052e0a2_715db765, - 64'h54798082_61696baa, - 64'h6b4a6aea_7a0a79aa, - 64'h794a74ea_640e60ae, - 64'h8522547d_9d3ff0ef, - 64'h13850513_00001517, - 64'hc59ff0ef_c5dff0ef, - 64'hc61ff0ef_c65ff0ef, - 64'hc69ff0ef_c6dff0ef, - 64'hc71ff0ef_c75ff0ef, - 64'ha805c7bf_f0efc87f, - 64'hf0ef4531_45814605, - 64'h4401f930_46e319fd, - 64'ha17ff0ef_19c50513, - 64'h00001517_e7990359, - 64'he7b30724_1a632901, - 64'h90411442_8c49caff, - 64'hf0ef9041_03051413, - 64'h84a20085_151bcbff, - 64'hf0effd64_1ae30404, - 64'h0413ff74_97e3892a, - 64'hf13ff0ef_0485854a, - 64'h0007c583_009407b3, - 64'h04000b93_4481c67f, - 64'hf0ef850a_04000593, - 64'h86224901_84262004, - 64'h8b13ff45_1ee3cfff, - 64'hf0ef3e80_0a930fe0, - 64'h0a13e951_d15ff0ef, - 64'h454985a2_0ff67613, - 64'h00166613_0015161b, - 64'hf49ff0ef_0ff47593, - 64'hf51ff0ef_0ff5f593, - 64'h0084559b_f5dff0ef, - 64'h0ff5f593_0104559b, - 64'hf69ff0ef_45010ff5, - 64'hf5930184_559bfee7, - 64'h9be30785_00c68023, - 64'h00f106b3_08000713, - 64'h567d4781_0209d993, - 64'h842e84aa_e55ee95a, - 64'hed56f152_f94ae586, - 64'hfd26e1a2_02061993, - 64'hf54e7155_80829141, - 64'h15428d3d_8ff90057, - 64'h979b1701_67090107, - 64'hd79b0105_179b4105, - 64'h551b0105_151b8d2d, - 64'h00c59513_8da9893d, - 64'h0045d51b_8da99141, - 64'h15428d5d_05220085, - 64'h579b8082_07f57513, - 64'h8d2d0045_15938d2d, - 64'h8d3d0045_d51b0075, - 64'hd79b8de9_80820141, - 64'h853e6402_60a24781, - 64'hc11157f5_f89ff0ef, - 64'hc51157f9_efbff0ef, - 64'hc91157fd_eb7ff0ef, - 64'hfc6de03f_f0ef347d, - 64'h4429b91f_f0ef2de5, - 64'h05130000_1517c89f, - 64'hf0efe022_e4061141, - 64'h80826105_00153513, - 64'h64a26442_60e20004, - 64'h051bfc94_0ce3e37f, - 64'hf0efeb3f_f0ef3065, - 64'h05130000_151785aa, - 64'h842ae53f_f0ef0290, - 64'h05134000_05b70770, - 64'h0613fbdf_f0ef4485, - 64'he822ec06_e4261101, - 64'h80820141_00153513, - 64'h157d6402_60a20004, - 64'h051bef3f_f0ef3405, - 64'h051385a2_00001517, - 64'he89ff0ef_842ae97f, - 64'hf0efe022_e4060370, - 64'h05134581_06500613, - 64'h11418082_61056902, - 64'h64a26442_60e20015, - 64'h3513f565_05130004, - 64'h051b0124_986388bd, - 64'h00f91b63_45014785, - 64'hec9ff0ef_ecdff0ef, - 64'h842aed3f_f0ef84aa, - 64'hed9ff0ef_eddff0ef, - 64'hee1ff0ef_892aeeff, - 64'hf0efe04a_e426e822, - 64'hec064521_1aa00593, - 64'h08700613_1101bfcd, - 64'h45018082_61056902, - 64'h64a26442_60e24505, - 64'hf89ff0ef_45853ce5, - 64'h05130000_1517fe99, - 64'h15e3c00d_f25ff0ef, - 64'h892a347d_f35ff0ef, - 64'h45014581_09500613, - 64'h44857104_0413e04a, - 64'hec06e426_6409e822, - 64'h1101cd1f_f06f6105, - 64'h3c850513_00001517, - 64'h60e26442_da7ff0ef, - 64'h852e65a2_cebff0ef, - 64'h41050513_00001517, - 64'hcf7ff0ef_8522cfdf, - 64'hf0efe42e_ec064165, - 64'h05130000_1517842a, - 64'he8221101_80826145, - 64'h64e27402_70a2f47d, - 64'h147d0007_d4634187, - 64'hd79b0185_179bfa7f, - 64'hf0efeb5f_f0ef8532, - 64'h06400413_6622ec1f, - 64'hf0ef0ff4_7513ec9f, - 64'hf0ef0ff5_75130084, - 64'h551bed5f_f0ef0ff5, - 64'h75130104_551bee1f, - 64'hf0ef0ff5_75130184, - 64'h551beedf_f0ef0404, - 64'he513febf_f0ef84aa, - 64'h842eec26_f022e432, - 64'hf4067179_f07ff06f, - 64'h0ff00513_8082557d, - 64'hb7e900d7_00230785, - 64'h00f60733_06c82683, - 64'hff798b05_5178bf4d, - 64'hd6b80785_0007c703, - 64'h80824501_d3b84719, - 64'hdbb8577d_200007b7, - 64'h00b6ef63_0007869b, - 64'h20000837_20000537, - 64'hfff58b85_537c2000, - 64'h0737d3b8_200007b7, - 64'h10600713_fff537fd, - 64'h00010320_079304b7, - 64'h616340a7_873b87aa, - 64'h200006b7_dbb85779, - 64'h200007b7_06b7ec63, - 64'h10000793_80826105, - 64'h64a2d3b8_4719dbb8, - 64'h644260e2_0ff47513, - 64'h577d2000_07b7e25f, - 64'hf0ef51a5_05130000, - 64'h1517eb3f_f0ef9101, - 64'h15024088_e3bff0ef, - 64'h53850513_00001517, - 64'he3958b85_240153fc, - 64'h57e0ff65_8b050647, - 64'h849353f8_d3b81060, - 64'h07132000_07b7fff5, - 64'h37fd0001_06400793, - 64'hd7a8dbb8_5779e426, - 64'he822ec06_200007b7, - 64'h1101e81f_f06f6105, - 64'h56850513_00001517, - 64'h64a260e2_6442d03c, - 64'h4799e99f_f0ef58e5, - 64'h05130000_1517f27f, - 64'hf0ef9101_02049513, - 64'h2481eb1f_f0ef5865, - 64'h05130000_15175064, - 64'hd03c1660_0793ec5f, - 64'hf0ef5ba5_05130000, - 64'h1517f53f_f0ef9101, - 64'h02049513_2481eddf, - 64'hf0ef5b25_05130000, - 64'h15175064_d03c1040, - 64'h07932000_0437fff5, - 64'h37fd0001_47a9c3b8, - 64'h47292000_07b7f05f, - 64'hf0efe426_e822ec06, - 64'h5d250513_11010000, - 64'h15178082_41088082, - 64'hc10c8082_610560e2, - 64'hee1ff0ef_00914503, - 64'hee9ff0ef_00814503, - 64'hf55ff0ef_ec06002c, - 64'h11018082_61456942, + 64'h151797df_f0ef4b91, + 64'h6502903f_f0ef10e5, + 64'h05130000_151790ff, + 64'hf0ef0fa5_05130000, + 64'h1517bf61_54f991ff, + 64'hf0ef0025_05130000, + 64'h15179adf_f0ef8526, + 64'h931ff0ef_10450513, + 64'h00001517_93dff0ef, + 64'h0f850513_00001517, + 64'hc90584aa_890ae49f, + 64'hf0ef850a_45854605, + 64'h710195bf_f0ef0fe5, + 64'h05130000_15178082, + 64'h61616c02_6ba26b42, + 64'h6ae27a02_79a27942, + 64'h74e26406_852660a6, + 64'hfb040113_54fd987f, + 64'hf0ef1025_05130000, + 64'h1517c51d_df3ff0ef, + 64'h8b2e8a2a_0880e062, + 64'he45eec56_f44ef84a, + 64'hfc26e486_e85af052, + 64'he0a2715d_b7655479, + 64'h80826169_6baa6b4a, + 64'h6aea7a0a_79aa794a, + 64'h74ea640e_60ae8522, + 64'h547d9d3f_f0ef1265, + 64'h05130000_1517c59f, + 64'hf0efc5df_f0efc61f, + 64'hf0efc65f_f0efc69f, + 64'hf0efc6df_f0efc71f, + 64'hf0efc75f_f0efa805, + 64'hc7bff0ef_c87ff0ef, + 64'h45314581_46054401, + 64'hf93046e3_19fda17f, + 64'hf0ef18a5_05130000, + 64'h1517e799_0359e7b3, + 64'h07241a63_29019041, + 64'h14428c49_cafff0ef, + 64'h90410305_141384a2, + 64'h0085151b_cbfff0ef, + 64'hfd641ae3_04040413, + 64'hff7497e3_892af13f, + 64'hf0ef0485_854a0007, + 64'hc5830094_07b30400, + 64'h0b934481_c67ff0ef, + 64'h850a0400_05938622, + 64'h49018426_20048b13, + 64'hff451ee3_cffff0ef, + 64'h3e800a93_0fe00a13, + 64'he951d15f_f0ef4549, + 64'h85a20ff6_76130016, + 64'h66130015_161bf49f, + 64'hf0ef0ff4_7593f51f, + 64'hf0ef0ff5_f5930084, + 64'h559bf5df_f0ef0ff5, + 64'hf5930104_559bf69f, + 64'hf0ef4501_0ff5f593, + 64'h0184559b_fee79be3, + 64'h078500c6_802300f1, + 64'h06b30800_0713567d, + 64'h47810209_d993842e, + 64'h84aae55e_e95aed56, + 64'hf152f94a_e586fd26, + 64'he1a20206_1993f54e, + 64'h71558082_91411542, + 64'h8d3d8ff9_0057979b, + 64'h17016709_0107d79b, + 64'h0105179b_4105551b, + 64'h0105151b_8d2d00c5, + 64'h95138da9_893d0045, + 64'hd51b8da9_91411542, + 64'h8d5d0522_0085579b, + 64'h808207f5_75138d2d, + 64'h00451593_8d2d8d3d, + 64'h0045d51b_0075d79b, + 64'h8de98082_0141853e, + 64'h640260a2_4781c111, + 64'h57f5f89f_f0efc511, + 64'h57f9efbf_f0efc911, + 64'h57fdeb7f_f0effc6d, + 64'he03ff0ef_347d4429, + 64'hb91ff0ef_2cc50513, + 64'h00001517_c89ff0ef, + 64'he022e406_11418082, + 64'h61050015_351364a2, + 64'h644260e2_0004051b, + 64'hfc940ce3_e37ff0ef, + 64'heb3ff0ef_2f450513, + 64'h00001517_85aa842a, + 64'he53ff0ef_02900513, + 64'h400005b7_07700613, + 64'hfbdff0ef_4485e822, + 64'hec06e426_11018082, + 64'h01410015_3513157d, + 64'h640260a2_0004051b, + 64'hef3ff0ef_32e50513, + 64'h85a20000_1517e89f, + 64'hf0ef842a_e97ff0ef, + 64'he022e406_03700513, + 64'h45810650_06131141, + 64'h80826105_690264a2, + 64'h644260e2_00153513, + 64'hf5650513_0004051b, + 64'h01249863_88bd00f9, + 64'h1b634501_4785ec9f, + 64'hf0efecdf_f0ef842a, + 64'hed3ff0ef_84aaed9f, + 64'hf0efeddf_f0efee1f, + 64'hf0ef892a_eefff0ef, + 64'he04ae426_e822ec06, + 64'h45211aa0_05930870, + 64'h06131101_bfcd4501, + 64'h80826105_690264a2, + 64'h644260e2_4505f89f, + 64'hf0ef4585_3bc50513, + 64'h00001517_fe9915e3, + 64'hc00df25f_f0ef892a, + 64'h347df35f_f0ef4501, + 64'h45810950_06134485, + 64'h71040413_e04aec06, + 64'he4266409_e8221101, + 64'hcd1ff06f_61053b65, + 64'h05130000_151760e2, + 64'h6442da7f_f0ef852e, + 64'h65a2cebf_f0ef3fe5, + 64'h05130000_1517cf7f, + 64'hf0ef8522_cfdff0ef, + 64'he42eec06_40450513, + 64'h00001517_842ae822, + 64'h11018082_614564e2, + 64'h740270a2_f47d147d, + 64'h0007d463_4187d79b, + 64'h0185179b_fa7ff0ef, + 64'heb5ff0ef_85320640, + 64'h04136622_ec1ff0ef, + 64'h0ff47513_ec9ff0ef, + 64'h0ff57513_0084551b, + 64'hed5ff0ef_0ff57513, + 64'h0104551b_ee1ff0ef, + 64'h0ff57513_0184551b, + 64'heedff0ef_0404e513, + 64'hfebff0ef_84aa842e, + 64'hec26f022_e432f406, + 64'h7179f07f_f06f0ff0, + 64'h05138082_557db7e9, + 64'h00d70023_078500f6, + 64'h073306c8_2683ff79, + 64'h8b055178_bf4dd6b8, + 64'h07850007_c7038082, + 64'h4501d3b8_4719dbb8, + 64'h577d2000_07b700b6, + 64'hef630007_869b2000, + 64'h08372000_0537fff5, + 64'h8b85537c_20000737, + 64'hd3b82000_07b71060, + 64'h0713fff5_37fd0001, + 64'h03200793_04b76163, + 64'h40a7873b_87aa2000, + 64'h06b7dbb8_57792000, + 64'h07b706b7_ec631000, + 64'h07938082_610564a2, + 64'hd3b84719_dbb86442, + 64'h60e20ff4_7513577d, + 64'h200007b7_e25ff0ef, + 64'h50850513_00001517, + 64'heb3ff0ef_91011502, + 64'h4088e3bf_f0ef5265, + 64'h05130000_1517e395, + 64'h8b852401_53fc57e0, + 64'hff658b05_06478493, + 64'h53f8d3b8_10600713, + 64'h200007b7_fff537fd, + 64'h00010640_0793d7a8, + 64'hdbb85779_e426e822, + 64'hec062000_07b71101, + 64'he81ff06f_61055565, + 64'h05130000_151764a2, + 64'h60e26442_d03c4799, + 64'he99ff0ef_57c50513, + 64'h00001517_f27ff0ef, + 64'h91010204_95132481, + 64'heb1ff0ef_57450513, + 64'h00001517_5064d03c, + 64'h16600793_ec5ff0ef, + 64'h5a850513_00001517, + 64'hf53ff0ef_91010204, + 64'h95132481_eddff0ef, + 64'h5a050513_00001517, + 64'h5064d03c_10400793, + 64'h20000437_fff537fd, + 64'h000147a9_c3b84729, + 64'h200007b7_f05ff0ef, + 64'he426e822_ec065c05, + 64'h05131101_00001517, + 64'h80824108_8082c10c, + 64'h80826105_60e2ecff, + 64'hf0ef0091_4503ed7f, + 64'hf0ef0081_4503f55f, + 64'hf0efec06_002c1101, + 64'h80826145_694264e2, + 64'h740270a2_fe9410e3, + 64'hef9ff0ef_00914503, + 64'hf01ff0ef_34610081, + 64'h4503f81f_f0ef0ff5, + 64'h7513002c_00895533, + 64'h54e10380_0413892a, + 64'hf406e84a_ec26f022, + 64'h71798082_61456942, 64'h64e27402_70a2fe94, - 64'h10e3f0bf_f0ef0091, - 64'h4503f13f_f0ef3461, - 64'h00814503_f81ff0ef, + 64'h10e3f3bf_f0ef0091, + 64'h4503f43f_f0ef3461, + 64'h00814503_fc3ff0ef, 64'h0ff57513_002c0089, - 64'h553354e1_03800413, - 64'h892af406_e84aec26, - 64'hf0227179_80826145, - 64'h694264e2_740270a2, - 64'hfe9410e3_f4dff0ef, - 64'h00914503_f55ff0ef, - 64'h34610081_4503fc3f, - 64'hf0ef0ff5_7513002c, - 64'h0089553b_54e14461, - 64'h892af406_e84aec26, - 64'hf0227179_808200f5, - 64'h80230007_c78300e5, - 64'h80a397aa_81110007, - 64'h4703973e_00f57713, - 64'h98078793_00001797, - 64'hb7f50405_fa5ff0ef, - 64'h80820141_640260a2, - 64'he5090004_4503842a, - 64'he406e022_11418082, - 64'h00e78823_02000713, - 64'h00e78423_fc700713, - 64'h00e78623_470d0007, - 64'h822300e7_8023476d, + 64'h553b54e1_4461892a, + 64'hf406e84a_ec26f022, + 64'h71798082_00f58023, + 64'h0007c783_00e580a3, + 64'h97aa8111_00074703, + 64'h973e00f5_771396e7, + 64'h87930000_1797b7f5, + 64'h0405f93f_f0ef8082, + 64'h01416402_60a2e509, + 64'h00044503_842ae406, + 64'he0221141_808200e7, + 64'h88230200_071300e7, + 64'h8423fc70_071300e7, + 64'h8623470d_00a78223, + 64'h0ff57513_00e78023, + 64'h0085551b_0ff57713, 64'h00e78623_f8000713, 64'h00078223_100007b7, + 64'h02b5553b_0045959b, 64'h808200a7_0023dfe5, 64'h0207f793_01474783, 64'h10000737_80820205, @@ -885,7 +885,7 @@ module bootrom ( 64'h4009091b_02000937, 64'h00448493_0124a023, 64'h00100913_020004b7, - 64'h24d000ef_01a11113, + 64'h25f000ef_01a11113, 64'h0210011b_03249663, 64'hf1402973_00000493, 64'h30491073_00800913 diff --git a/fpga/src/bootrom/src/main.c b/fpga/src/bootrom/src/main.c index 66af9c3af6af336ed4bd47b4e297c2072c6361d9..27c1b24acbf6a031607a99108120659c5953858b 100644 --- a/fpga/src/bootrom/src/main.c +++ b/fpga/src/bootrom/src/main.c @@ -5,7 +5,7 @@ int main() { - init_uart(); + init_uart(30000000, 115200); print_uart("Hello World!\r\n"); int res = gpt_find_boot_partition((uint8_t *)0x80000000UL, 2 * 16384); diff --git a/fpga/src/bootrom/src/uart.c b/fpga/src/bootrom/src/uart.c index 29ccffce6d5b428eacb5767b830682ba328218b3..b6ab19b7b3544655ef577dec7cc8a7a7f58bf3d7 100644 --- a/fpga/src/bootrom/src/uart.c +++ b/fpga/src/bootrom/src/uart.c @@ -23,12 +23,14 @@ void write_serial(char a) write_reg_u8(UART_THR, a); } -void init_uart() +void init_uart(uint32_t freq, uint32_t baud) { + uint32_t divisor = freq / (baud << 4); + write_reg_u8(UART_INTERRUPT_ENABLE, 0x00); // Disable all interrupts write_reg_u8(UART_LINE_CONTROL, 0x80); // Enable DLAB (set baud rate divisor) - write_reg_u8(UART_DLAB_LSB, 0x1B); // Set divisor to 27 (lo byte) 115200 baud - write_reg_u8(UART_DLAB_MSB, 0x00); // (hi byte) + write_reg_u8(UART_DLAB_LSB, divisor); // divisor (lo byte) + write_reg_u8(UART_DLAB_MSB, (divisor >> 8) & 0xFF); // divisor (hi byte) write_reg_u8(UART_LINE_CONTROL, 0x03); // 8 bits, no parity, one stop bit write_reg_u8(UART_FIFO_CONTROL, 0xC7); // Enable FIFO, clear them, with 14-byte threshold write_reg_u8(UART_MODEM_CONTROL, 0x20); // Autoflow mode diff --git a/fpga/xilinx/xlnx_clk_gen/tcl/run.tcl b/fpga/xilinx/xlnx_clk_gen/tcl/run.tcl index 094f9c77848f949140d708e2b9c14ae386f87906..82e564d7d3098bc9ab55d769ca57d293deb6c363 100644 --- a/fpga/xilinx/xlnx_clk_gen/tcl/run.tcl +++ b/fpga/xilinx/xlnx_clk_gen/tcl/run.tcl @@ -13,7 +13,7 @@ set_property -dict [list CONFIG.PRIM_IN_FREQ {200.000} \ CONFIG.CLKOUT2_USED {true} \ CONFIG.CLKOUT3_USED {true} \ CONFIG.CLKOUT4_USED {true} \ - CONFIG.CLKOUT1_REQUESTED_OUT_FREQ {50} \ + CONFIG.CLKOUT1_REQUESTED_OUT_FREQ {30} \ CONFIG.CLKOUT2_REQUESTED_OUT_FREQ {125} \ CONFIG.CLKOUT3_REQUESTED_OUT_FREQ {125} \ CONFIG.CLKOUT3_REQUESTED_PHASE {90.000} \ diff --git a/include/ariane_pkg.sv b/include/ariane_pkg.sv index b48bc082a96638a07eb85eefa23c0869072f1b1b..0c39f4bc11b9bbbaab9a789fac3e626c134391bb 100644 --- a/include/ariane_pkg.sv +++ b/include/ariane_pkg.sv @@ -62,8 +62,8 @@ package ariane_pkg; `endif // Floating-point extensions configuration - localparam bit RVF = 1'b0; // Is F extension enabled - localparam bit RVD = 1'b0; // Is D extension enabled + localparam bit RVF = 1'b1; // Is F extension enabled + localparam bit RVD = 1'b1; // Is D extension enabled localparam bit RVA = 1'b1; // Is A extension enabled // Transprecision floating-point extensions configuration @@ -73,14 +73,14 @@ package ariane_pkg; localparam bit XFVEC = 1'b0; // Is vectorial float extension (Xfvec) enabled // Transprecision float unit - localparam logic [30:0] LAT_COMP_FP32 = 'd3; - localparam logic [30:0] LAT_COMP_FP64 = 'd4; - localparam logic [30:0] LAT_COMP_FP16 = 'd3; - localparam logic [30:0] LAT_COMP_FP16ALT = 'd3; - localparam logic [30:0] LAT_COMP_FP8 = 'd2; - localparam logic [30:0] LAT_DIVSQRT = 'd2; - localparam logic [30:0] LAT_NONCOMP = 'd1; - localparam logic [30:0] LAT_CONV = 'd2; + localparam int unsigned LAT_COMP_FP32 = 'd2; + localparam int unsigned LAT_COMP_FP64 = 'd3; + localparam int unsigned LAT_COMP_FP16 = 'd1; + localparam int unsigned LAT_COMP_FP16ALT = 'd1; + localparam int unsigned LAT_COMP_FP8 = 'd1; + localparam int unsigned LAT_DIVSQRT = 'd2; + localparam int unsigned LAT_NONCOMP = 'd1; + localparam int unsigned LAT_CONV = 'd2; // -------------------------------------- // vvvv Don't change these by hand! vvvv diff --git a/openpiton/ariane_verilog_wrap.sv b/openpiton/ariane_verilog_wrap.sv index 869de9ec05668b3defffaf9edf435b46f23bf9bb..cb90761c93fef16ab8cfd61a6a1f8ed93155cc46 100644 --- a/openpiton/ariane_verilog_wrap.sv +++ b/openpiton/ariane_verilog_wrap.sv @@ -111,6 +111,20 @@ module ariane_verilog_wrap #( // reset gate this assign rst_n = wake_up_cnt_q[$high(wake_up_cnt_q)] & reset_l; + // reset_synchronizer #( + // .NUM_REGS(2) + // ) i_sync ( + // .clk_i ( clk_i ), + // .rst_ni ( rst_n ), + // .tmode_i ( 1'b0 ), + // .rst_no ( spc_grst_l ) + // ); + + synchronizer i_sync ( + .clk ( clk_i ), + .presyncdata ( rst_n ), + .syncdata ( spc_grst_l ) + ); ///////////////////////////// // synchronizers diff --git a/src/axi b/src/axi index de1af467229315ee6af31fea96664c7aae5638a9..d94d601e55213d770beceebfab7786adf7baf8ce 160000 --- a/src/axi +++ b/src/axi @@ -1 +1 @@ -Subproject commit de1af467229315ee6af31fea96664c7aae5638a9 +Subproject commit d94d601e55213d770beceebfab7786adf7baf8ce diff --git a/src/common_cells b/src/common_cells index b4769f4121ed42e99dd168122e036ce1f218637b..c5e93e3e10abc719fed12dd92d41c1af9a0054c6 160000 --- a/src/common_cells +++ b/src/common_cells @@ -1 +1 @@ -Subproject commit b4769f4121ed42e99dd168122e036ce1f218637b +Subproject commit c5e93e3e10abc719fed12dd92d41c1af9a0054c6 diff --git a/src/decoder.sv b/src/decoder.sv index 87c7ae07af14c40ba5ef85ab97dd590984a61a31..3d42c980cf1db805dda2c1011b19447ac4e03652 100644 --- a/src/decoder.sv +++ b/src/decoder.sv @@ -298,9 +298,9 @@ module decoder ( 5'b00000 : begin instruction_o.rs2 = instr.rvftype.rs1; // set rs2 = rs1 so we can map FMV to SGNJ in the unit if (instr.rvftype.repl) - instruction_o.op = FMV_F2X; // vfmv.x.vfmt - FPR to GPR Move - else instruction_o.op = FMV_X2F; // vfmv.vfmt.x - GPR to FPR Move + else + instruction_o.op = FMV_F2X; // vfmv.x.vfmt - FPR to GPR Move check_fprm = 1'b0; // no rounding for moves end 5'b00001 : begin diff --git a/src/fpu b/src/fpu index 0d4970af8fbe35e88a6d0395c51cfb58b6d1faf9..9fa89ab655dfe630c22360e21c259ee2091427f8 160000 --- a/src/fpu +++ b/src/fpu @@ -1 +1 @@ -Subproject commit 0d4970af8fbe35e88a6d0395c51cfb58b6d1faf9 +Subproject commit 9fa89ab655dfe630c22360e21c259ee2091427f8 diff --git a/src/fpu_div_sqrt_mvp b/src/fpu_div_sqrt_mvp index 3736c4c844074bd64c3c505c017181db71b738b4..d94bf84ff56fca7e3f8e0a719c8a493ec6c39153 160000 --- a/src/fpu_div_sqrt_mvp +++ b/src/fpu_div_sqrt_mvp @@ -1 +1 @@ -Subproject commit 3736c4c844074bd64c3c505c017181db71b738b4 +Subproject commit d94bf84ff56fca7e3f8e0a719c8a493ec6c39153 diff --git a/src/fpu_wrap.sv b/src/fpu_wrap.sv index 0b442b9068064c96cced67f54e9413aa2318d295..5ae17bfc9c04439bdbbc399d915d12d42973b489 100644 --- a/src/fpu_wrap.sv +++ b/src/fpu_wrap.sv @@ -15,598 +15,541 @@ import ariane_pkg::*; module fpu_wrap ( - input logic clk_i, - input logic rst_ni, - input logic flush_i, - input logic fpu_valid_i, - output logic fpu_ready_o, - input fu_data_t fu_data_i, - - input logic [1:0] fpu_fmt_i, - input logic [2:0] fpu_rm_i, - input logic [2:0] fpu_frm_i, - input logic [6:0] fpu_prec_i, - output logic [TRANS_ID_BITS-1:0] fpu_trans_id_o, - output logic [FLEN-1:0] result_o, - output logic fpu_valid_o, - output exception_t fpu_exception_o + input logic clk_i, + input logic rst_ni, + input logic flush_i, + input logic fpu_valid_i, + output logic fpu_ready_o, + input fu_data_t fu_data_i, + + input logic [1:0] fpu_fmt_i, + input logic [2:0] fpu_rm_i, + input logic [2:0] fpu_frm_i, + input logic [6:0] fpu_prec_i, + output logic [TRANS_ID_BITS-1:0] fpu_trans_id_o, + output logic [FLEN-1:0] result_o, + output logic fpu_valid_o, + output exception_t fpu_exception_o ); // this is a workaround // otherwise compilation might issue an error if FLEN=0 generate - if (FP_PRESENT) begin : fpu_gen - - logic [FLEN-1:0] operand_a_i; - logic [FLEN-1:0] operand_b_i; - logic [FLEN-1:0] operand_c_i; - assign operand_a_i = fu_data_i.operand_a[FLEN-1:0]; - assign operand_b_i = fu_data_i.operand_b[FLEN-1:0]; - assign operand_c_i = fu_data_i.imm[FLEN-1:0]; - - //----------------------------------- - // FPnew encoding from FPnew package - //----------------------------------- - localparam OPBITS = 4; - localparam FMTBITS = 3; - localparam IFMTBITS = 2; - - integer OP_NUMBITS, FMT_NUMBITS, IFMT_NUMBITS; - - logic [OPBITS-1:0] OP_FMADD; - logic [OPBITS-1:0] OP_FNMSUB; - logic [OPBITS-1:0] OP_ADD; - logic [OPBITS-1:0] OP_MUL; - logic [OPBITS-1:0] OP_DIV; - logic [OPBITS-1:0] OP_SQRT; - logic [OPBITS-1:0] OP_SGNJ; - logic [OPBITS-1:0] OP_MINMAX; - logic [OPBITS-1:0] OP_CMP; - logic [OPBITS-1:0] OP_CLASS; - logic [OPBITS-1:0] OP_F2I; - logic [OPBITS-1:0] OP_I2F; - logic [OPBITS-1:0] OP_F2F; - logic [OPBITS-1:0] OP_CPKAB; - logic [OPBITS-1:0] OP_CPKCD; - - logic [FMTBITS-1:0] FMT_FP32; - logic [FMTBITS-1:0] FMT_FP64; - logic [FMTBITS-1:0] FMT_FP16; - logic [FMTBITS-1:0] FMT_FP8; - logic [FMTBITS-1:0] FMT_FP16ALT; - logic [FMTBITS-1:0] FMT_CUST1; - logic [FMTBITS-1:0] FMT_CUST2; - logic [FMTBITS-1:0] FMT_CUST3; - - logic [IFMTBITS-1:0] IFMT_INT8; - logic [IFMTBITS-1:0] IFMT_INT16; - logic [IFMTBITS-1:0] IFMT_INT32; - logic [IFMTBITS-1:0] IFMT_INT64; - - // bind the constants from the fpnew entity - fpnew_pkg_constants i_fpnew_constants ( - .OP_NUMBITS ( OP_NUMBITS ), - .OP_FMADD ( OP_FMADD ), - .OP_FNMSUB ( OP_FNMSUB ), - .OP_ADD ( OP_ADD ), - .OP_MUL ( OP_MUL ), - .OP_DIV ( OP_DIV ), - .OP_SQRT ( OP_SQRT ), - .OP_SGNJ ( OP_SGNJ ), - .OP_MINMAX ( OP_MINMAX ), - .OP_CMP ( OP_CMP ), - .OP_CLASS ( OP_CLASS ), - .OP_F2I ( OP_F2I ), - .OP_I2F ( OP_I2F ), - .OP_F2F ( OP_F2F ), - .OP_CPKAB ( OP_CPKAB ), - .OP_CPKCD ( OP_CPKCD ), - .FMT_NUMBITS ( FMT_NUMBITS ), - .FMT_FP32 ( FMT_FP32 ), - .FMT_FP64 ( FMT_FP64 ), - .FMT_FP16 ( FMT_FP16 ), - .FMT_FP8 ( FMT_FP8 ), - .FMT_FP16ALT ( FMT_FP16ALT ), - .FMT_CUST1 ( FMT_CUST1 ), - .FMT_CUST2 ( FMT_CUST2 ), - .FMT_CUST3 ( FMT_CUST3 ), - .IFMT_NUMBITS ( IFMT_NUMBITS ), - .IFMT_INT8 ( IFMT_INT8 ), - .IFMT_INT16 ( IFMT_INT16 ), - .IFMT_INT32 ( IFMT_INT32 ), - .IFMT_INT64 ( IFMT_INT64 ) - ); - - // always_comb begin - // assert (OPBITS >= OP_NUMBITS) else $error("OPBITS is smaller than %0d", OP_NUMBITS); - // assert (FMTBITS >= FMT_NUMBITS) else $error("FMTBITS is smaller than %0d", FMT_NUMBITS); - // assert (IFMTBITS >= IFMT_NUMBITS) else $error("IFMTBITS is smaller than %0d", IFMT_NUMBITS); - // end - - //------------------------------------------------- - // Inputs to the FPU and protocol inversion buffer - //------------------------------------------------- - logic [FLEN-1:0] operand_a_d, operand_a_q, operand_a; - logic [FLEN-1:0] operand_b_d, operand_b_q, operand_b; - logic [FLEN-1:0] operand_c_d, operand_c_q, operand_c; - logic [OPBITS-1:0] fpu_op_d, fpu_op_q, fpu_op; - logic fpu_op_mod_d, fpu_op_mod_q, fpu_op_mod; - logic [FMTBITS-1:0] fpu_fmt_d, fpu_fmt_q, fpu_fmt; - logic [FMTBITS-1:0] fpu_fmt2_d, fpu_fmt2_q, fpu_fmt2; - logic [IFMTBITS-1:0] fpu_ifmt_d, fpu_ifmt_q, fpu_ifmt; - logic [2:0] fpu_rm_d, fpu_rm_q, fpu_rm; - logic fpu_vec_op_d, fpu_vec_op_q, fpu_vec_op; - - logic [TRANS_ID_BITS-1:0] fpu_tag_d, fpu_tag_q, fpu_tag; - - logic fpu_in_ready, fpu_in_valid; - logic fpu_out_ready, fpu_out_valid; - - logic [4:0] fpu_status; - - // FSM to handle protocol inversion - enum logic {READY, STALL} state_q, state_d; - logic hold_inputs; - logic use_hold; - - //----------------------------- - // Translate inputs - //----------------------------- - - always_comb begin : input_translation - - automatic logic vec_replication; // control honoring of replication flag - automatic logic replicate_c; // replicate operand C instead of B (for ADD/SUB) - automatic logic check_ah; // Decide for AH from RM field encoding - - // Default Values - operand_a_d = operand_a_i; - operand_b_d = operand_b_i; // immediates come through this port unless used as operand - operand_c_d = operand_c_i; // immediates come through this port unless used as operand - fpu_op_d = OP_SGNJ; // sign injection by default - fpu_op_mod_d = 1'b0; - fpu_fmt_d = FMT_FP32; - fpu_fmt2_d = FMT_FP32; - fpu_ifmt_d = IFMT_INT32; - fpu_rm_d = fpu_rm_i; - fpu_vec_op_d = fu_data_i.fu == FPU_VEC; - fpu_tag_d = fu_data_i.trans_id; - vec_replication = fpu_rm_i[0]; // replication bit is sent via rm field - replicate_c = 1'b0; - check_ah = 1'b0; // whether set scalar AH encoding from MSB of rm_i - - // Scalar Rounding Modes - some ops encode inside RM but use smaller range - if (!(fpu_rm_i inside {[3'b000:3'b100]})) - fpu_rm_d = fpu_frm_i; - - // Vectorial ops always consult FRM - if (fpu_vec_op_d) - fpu_rm_d = fpu_frm_i; - - // Formats + if (FP_PRESENT) begin : fpu_gen + + logic [FLEN-1:0] operand_a_i; + logic [FLEN-1:0] operand_b_i; + logic [FLEN-1:0] operand_c_i; + assign operand_a_i = fu_data_i.operand_a[FLEN-1:0]; + assign operand_b_i = fu_data_i.operand_b[FLEN-1:0]; + assign operand_c_i = fu_data_i.imm[FLEN-1:0]; + + //----------------------------------- + // FPnew config from FPnew package + //----------------------------------- + localparam OPBITS = 64; + localparam FMTBITS = $clog2(fpnew_pkg::NUM_FP_FORMATS); + localparam IFMTBITS = $clog2(fpnew_pkg::NUM_INT_FORMATS); + + // Features (enabled formats, vectors etc.) + localparam fpnew_pkg::fpu_features_t FPU_FEATURES = '{ + Width: 64, + EnableVectors: ariane_pkg::XFVEC, + EnableNanBox: 1'b1, + FpFmtMask: {RVF, RVD, XF16, XF8, XF16ALT}, + IntFmtMask: {XFVEC && XF8, XFVEC && (XF16 || XF16ALT), 1'b1, 1'b1} + }; + + // Implementation (number of registers etc) + localparam fpnew_pkg::fpu_implementation_t FPU_IMPLEMENTATION = '{ + PipeRegs: '{// FP32, FP64, FP16, FP8, FP16alt + '{LAT_COMP_FP32, LAT_COMP_FP64, LAT_COMP_FP16, LAT_COMP_FP8, LAT_COMP_FP16ALT}, // ADDMUL + '{default: LAT_DIVSQRT}, // DIVSQRT + '{default: LAT_NONCOMP}, // NONCOMP + '{default: LAT_CONV}}, // CONV + UnitTypes: '{'{default: fpnew_pkg::PARALLEL}, // ADDMUL + '{default: fpnew_pkg::MERGED}, // DIVSQRT + '{default: fpnew_pkg::PARALLEL}, // NONCOMP + '{default: fpnew_pkg::MERGED}}, // CONV + PipeConfig: fpnew_pkg::AFTER + }; + + //------------------------------------------------- + // Inputs to the FPU and protocol inversion buffer + //------------------------------------------------- + logic [FLEN-1:0] operand_a_d, operand_a_q, operand_a; + logic [FLEN-1:0] operand_b_d, operand_b_q, operand_b; + logic [FLEN-1:0] operand_c_d, operand_c_q, operand_c; + logic [OPBITS-1:0] fpu_op_d, fpu_op_q, fpu_op; + logic fpu_op_mod_d, fpu_op_mod_q, fpu_op_mod; + logic [FMTBITS-1:0] fpu_srcfmt_d, fpu_srcfmt_q, fpu_srcfmt; + logic [FMTBITS-1:0] fpu_dstfmt_d, fpu_dstfmt_q, fpu_dstfmt; + logic [IFMTBITS-1:0] fpu_ifmt_d, fpu_ifmt_q, fpu_ifmt; + logic [2:0] fpu_rm_d, fpu_rm_q, fpu_rm; + logic fpu_vec_op_d, fpu_vec_op_q, fpu_vec_op; + + logic [TRANS_ID_BITS-1:0] fpu_tag_d, fpu_tag_q, fpu_tag; + + logic fpu_in_ready, fpu_in_valid; + logic fpu_out_ready, fpu_out_valid; + + logic [4:0] fpu_status; + + // FSM to handle protocol inversion + enum logic {READY, STALL} state_q, state_d; + logic hold_inputs; + logic use_hold; + + //----------------------------- + // Translate inputs + //----------------------------- + + always_comb begin : input_translation + + automatic logic vec_replication; // control honoring of replication flag + automatic logic replicate_c; // replicate operand C instead of B (for ADD/SUB) + automatic logic check_ah; // Decide for AH from RM field encoding + + // Default Values + operand_a_d = operand_a_i; + operand_b_d = operand_b_i; // immediates come through this port unless used as operand + operand_c_d = operand_c_i; // immediates come through this port unless used as operand + fpu_op_d = fpnew_pkg::SGNJ; // sign injection by default + fpu_op_mod_d = 1'b0; + fpu_dstfmt_d = fpnew_pkg::FP32; + fpu_ifmt_d = fpnew_pkg::INT32; + fpu_rm_d = fpu_rm_i; + fpu_vec_op_d = fu_data_i.fu == FPU_VEC; + fpu_tag_d = fu_data_i.trans_id; + vec_replication = fpu_rm_i[0]; // replication bit is sent via rm field + replicate_c = 1'b0; + check_ah = 1'b0; // whether set scalar AH encoding from MSB of rm_i + + // Scalar Rounding Modes - some ops encode inside RM but use smaller range + if (!(fpu_rm_i inside {[3'b000:3'b100]})) + fpu_rm_d = fpu_frm_i; + + // Vectorial ops always consult FRM + if (fpu_vec_op_d) + fpu_rm_d = fpu_frm_i; + + // Formats + unique case (fpu_fmt_i) + // FP32 + 2'b00 : fpu_dstfmt_d = fpnew_pkg::FP32; + // FP64 or FP16ALT (vectorial) + 2'b01 : fpu_dstfmt_d = fpu_vec_op_d ? fpnew_pkg::FP16ALT : fpnew_pkg::FP64; + // FP16 or FP16ALT (scalar) + 2'b10 : begin + if (!fpu_vec_op_d && fpu_rm_i==3'b101) + fpu_dstfmt_d = fpnew_pkg::FP16ALT; + else + fpu_dstfmt_d = fpnew_pkg::FP16; + end + // FP8 + default : fpu_dstfmt_d = fpnew_pkg::FP8; + endcase + + // By default, set src=dst + fpu_srcfmt_d = fpu_dstfmt_d; + + // Operations (this can modify the rounding mode field and format!) + unique case (fu_data_i.operator) + // Addition + FADD : begin + fpu_op_d = fpnew_pkg::ADD; + replicate_c = 1'b1; // second operand is in C + end + // Subtraction is modified ADD + FSUB : begin + fpu_op_d = fpnew_pkg::ADD; + fpu_op_mod_d = 1'b1; + replicate_c = 1'b1; // second operand is in C + end + // Multiplication + FMUL : fpu_op_d = fpnew_pkg::MUL; + // Division + FDIV : fpu_op_d = fpnew_pkg::DIV; + // Min/Max - OP is encoded in rm (000-001) + FMIN_MAX : begin + fpu_op_d = fpnew_pkg::MINMAX; + fpu_rm_d = {1'b0, fpu_rm_i[1:0]}; // mask out AH encoding bit + check_ah = 1'b1; // AH has RM MSB encoding + end + // Square Root + FSQRT : fpu_op_d = fpnew_pkg::SQRT; + // Fused Multiply Add + FMADD : fpu_op_d = fpnew_pkg::FMADD; + // Fused Multiply Subtract is modified FMADD + FMSUB : begin + fpu_op_d = fpnew_pkg::FMADD; + fpu_op_mod_d = 1'b1; + end + // Fused Negated Multiply Subtract + FNMSUB : fpu_op_d = fpnew_pkg::FNMSUB; + // Fused Negated Multiply Add is modified FNMSUB + FNMADD : begin + fpu_op_d = fpnew_pkg::FNMSUB; + fpu_op_mod_d = 1'b1; + end + // Float to Int Cast - Op encoded in lowest two imm bits or rm + FCVT_F2I : begin + fpu_op_d = fpnew_pkg::F2I; + // Vectorial Ops encoded in R bit + if (fpu_vec_op_d) begin + fpu_op_mod_d = fpu_rm_i[0]; + vec_replication = 1'b0; // no replication, R bit used for op unique case (fpu_fmt_i) - // FP32 - 2'b00 : fpu_fmt_d = FMT_FP32; - // FP64 or FP16ALT (vectorial) - 2'b01 : fpu_fmt_d = fpu_vec_op_d ? FMT_FP16ALT : FMT_FP64; - // FP16 or FP16ALT (scalar) - 2'b10 : begin - if (!fpu_vec_op_d && fpu_rm_i==3'b101) - fpu_fmt_d = FMT_FP16ALT; - else - fpu_fmt_d = FMT_FP16; - end - // FP8 - default : fpu_fmt_d = FMT_FP8; + 2'b00 : fpu_ifmt_d = fpnew_pkg::INT32; + 2'b01, + 2'b10 : fpu_ifmt_d = fpnew_pkg::INT16; + 2'b11 : fpu_ifmt_d = fpnew_pkg::INT8; + endcase + // Scalar casts encoded in imm + end else begin + fpu_op_mod_d = operand_c_i[0]; + if (operand_c_i[1]) + fpu_ifmt_d = fpnew_pkg::INT64; + else + fpu_ifmt_d = fpnew_pkg::INT32; + end + end + // Int to Float Cast - Op encoded in lowest two imm bits or rm + FCVT_I2F : begin + fpu_op_d = fpnew_pkg::I2F; + // Vectorial Ops encoded in R bit + if (fpu_vec_op_d) begin + fpu_op_mod_d = fpu_rm_i[0]; + vec_replication = 1'b0; // no replication, R bit used for op + unique case (fpu_fmt_i) + 2'b00 : fpu_ifmt_d = fpnew_pkg::INT32; + 2'b01, + 2'b10 : fpu_ifmt_d = fpnew_pkg::INT16; + 2'b11 : fpu_ifmt_d = fpnew_pkg::INT8; + endcase + // Scalar casts encoded in imm + end else begin + fpu_op_mod_d = operand_c_i[0]; + if (operand_c_i[1]) + fpu_ifmt_d = fpnew_pkg::INT64; + else + fpu_ifmt_d = fpnew_pkg::INT32; + end + end + // Float to Float Cast - Source format encoded in lowest two/three imm bits + FCVT_F2F : begin + fpu_op_d = fpnew_pkg::F2F; + // Vectorial ops encoded in lowest two imm bits + if (fpu_vec_op_d) begin + vec_replication = 1'b0; // no replication for casts (not needed) + unique case (operand_c_i[1:0]) + 2'b00: fpu_srcfmt_d = fpnew_pkg::FP32; + 2'b01: fpu_srcfmt_d = fpnew_pkg::FP16ALT; + 2'b10: fpu_srcfmt_d = fpnew_pkg::FP16; + 2'b11: fpu_srcfmt_d = fpnew_pkg::FP8; endcase + // Scalar ops encoded in lowest three imm bits + end else begin + unique case (operand_c_i[2:0]) + 3'b000: fpu_srcfmt_d = fpnew_pkg::FP32; + 3'b001: fpu_srcfmt_d = fpnew_pkg::FP64; + 3'b010: fpu_srcfmt_d = fpnew_pkg::FP16; + 3'b110: fpu_srcfmt_d = fpnew_pkg::FP16ALT; + 3'b011: fpu_srcfmt_d = fpnew_pkg::FP8; + endcase + end + end + // Scalar Sign Injection - op encoded in rm (000-010) + FSGNJ : begin + fpu_op_d = fpnew_pkg::SGNJ; + fpu_rm_d = {1'b0, fpu_rm_i[1:0]}; // mask out AH encoding bit + check_ah = 1'b1; // AH has RM MSB encoding + end + // Move from FPR to GPR - mapped to SGNJ-passthrough since no recoding + FMV_F2X : begin + fpu_op_d = fpnew_pkg::SGNJ; + fpu_rm_d = 3'b011; // passthrough without checking nan-box + fpu_op_mod_d = 1'b1; // no NaN-Boxing + check_ah = 1'b1; // AH has RM MSB encoding + vec_replication = 1'b0; // no replication, we set second operand + end + // Move from GPR to FPR - mapped to NOP since no recoding + FMV_X2F : begin + fpu_op_d = fpnew_pkg::SGNJ; + fpu_rm_d = 3'b011; // passthrough without checking nan-box + check_ah = 1'b1; // AH has RM MSB encoding + vec_replication = 1'b0; // no replication, we set second operand + end + // Scalar Comparisons - op encoded in rm (000-010) + FCMP : begin + fpu_op_d = fpnew_pkg::CMP; + fpu_rm_d = {1'b0, fpu_rm_i[1:0]}; // mask out AH encoding bit + check_ah = 1'b1; // AH has RM MSB encoding + end + // Classification + FCLASS : begin + fpu_op_d = fpnew_pkg::CLASSIFY; + fpu_rm_d = {1'b0, fpu_rm_i[1:0]}; // mask out AH encoding bit - CLASS doesn't care anyways + check_ah = 1'b1; // AH has RM MSB encoding + end + // Vectorial Minimum - set up scalar encoding in rm + VFMIN : begin + fpu_op_d = fpnew_pkg::MINMAX; + fpu_rm_d = 3'b000; // min + end + // Vectorial Maximum - set up scalar encoding in rm + VFMAX : begin + fpu_op_d = fpnew_pkg::MINMAX; + fpu_rm_d = 3'b001; // max + end + // Vectorial Sign Injection - set up scalar encoding in rm + VFSGNJ : begin + fpu_op_d = fpnew_pkg::SGNJ; + fpu_rm_d = 3'b000; // sgnj + end + // Vectorial Negated Sign Injection - set up scalar encoding in rm + VFSGNJN : begin + fpu_op_d = fpnew_pkg::SGNJ; + fpu_rm_d = 3'b001; // sgnjn + end + // Vectorial Xored Sign Injection - set up scalar encoding in rm + VFSGNJX : begin + fpu_op_d = fpnew_pkg::SGNJ; + fpu_rm_d = 3'b010; // sgnjx + end + // Vectorial Equals - set up scalar encoding in rm + VFEQ : begin + fpu_op_d = fpnew_pkg::CMP; + fpu_rm_d = 3'b010; // eq + end + // Vectorial Not Equals - set up scalar encoding in rm + VFNE : begin + fpu_op_d = fpnew_pkg::CMP; + fpu_op_mod_d = 1'b1; // invert output + fpu_rm_d = 3'b010; // eq + end + // Vectorial Less Than - set up scalar encoding in rm + VFLT : begin + fpu_op_d = fpnew_pkg::CMP; + fpu_rm_d = 3'b001; // lt + end + // Vectorial Greater or Equal - set up scalar encoding in rm + VFGE : begin + fpu_op_d = fpnew_pkg::CMP; + fpu_op_mod_d = 1'b1; // invert output + fpu_rm_d = 3'b001; // lt + end + // Vectorial Less or Equal - set up scalar encoding in rm + VFLE : begin + fpu_op_d = fpnew_pkg::CMP; + fpu_rm_d = 3'b000; // le + end + // Vectorial Greater Than - set up scalar encoding in rm + VFGT : begin + fpu_op_d = fpnew_pkg::CMP; + fpu_op_mod_d = 1'b1; // invert output + fpu_rm_d = 3'b000; // le + end + // Vectorial Convert-and-Pack from FP32, lower 4 entries + VFCPKAB_S : begin + fpu_op_d = fpnew_pkg::CPKAB; + fpu_op_mod_d = fpu_rm_i[0]; // A/B selection from R bit + vec_replication = 1'b0; // no replication, R bit used for op + fpu_srcfmt_d = fpnew_pkg::FP32; // Cast from FP32 + end + // Vectorial Convert-and-Pack from FP32, upper 4 entries + VFCPKCD_S : begin + fpu_op_d = fpnew_pkg::CPKCD; + fpu_op_mod_d = fpu_rm_i[0]; // C/D selection from R bit + vec_replication = 1'b0; // no replication, R bit used for op + fpu_srcfmt_d = fpnew_pkg::FP64; // Cast from FP64 + end + // Vectorial Convert-and-Pack from FP64, lower 4 entries + VFCPKAB_S : begin + fpu_op_d = fpnew_pkg::CPKAB; + fpu_op_mod_d = fpu_rm_i[0]; // A/B selection from R bit + vec_replication = 1'b0; // no replication, R bit used for op + fpu_srcfmt_d = fpnew_pkg::FP64; // Cast from FP64 + end + // Vectorial Convert-and-Pack from FP64, upper 4 entries + VFCPKCD_S : begin + fpu_op_d = fpnew_pkg::CPKCD; + fpu_op_mod_d = fpu_rm_i[0]; // C/D selection from R bit + vec_replication = 1'b0; // no replication, R bit used for op + fpu_srcfmt_d = fpnew_pkg::FP64; // Cast from FP64 + end + // No changes per default + default : ; //nothing + endcase + + // Scalar AH encoding fixing + if (!fpu_vec_op_d && check_ah) + if (fpu_rm_i[2]) + fpu_dstfmt_d = fpnew_pkg::FP16ALT; + + // Replication + if (fpu_vec_op_d && vec_replication) begin + if (replicate_c) begin + unique case (fpu_dstfmt_d) + fpnew_pkg::FP32 : operand_c_d = RVD ? {2{operand_c_i[31:0]}} : operand_c_i; + fpnew_pkg::FP16, + fpnew_pkg::FP16ALT : operand_c_d = RVD ? {4{operand_c_i[15:0]}} : {2{operand_c_i[15:0]}}; + fpnew_pkg::FP8 : operand_c_d = RVD ? {8{operand_c_i[7:0]}} : {4{operand_c_i[7:0]}}; + endcase // fpu_dstfmt_d + end else begin + unique case (fpu_dstfmt_d) + fpnew_pkg::FP32 : operand_b_d = RVD ? {2{operand_b_i[31:0]}} : operand_b_i; + fpnew_pkg::FP16, + fpnew_pkg::FP16ALT : operand_b_d = RVD ? {4{operand_b_i[15:0]}} : {2{operand_b_i[15:0]}}; + fpnew_pkg::FP8 : operand_b_d = RVD ? {8{operand_b_i[7:0]}} : {4{operand_b_i[7:0]}}; + endcase // fpu_dstfmt_d + end + end + end - // Operations (this can modify the rounding mode field and format!) - unique case (fu_data_i.operator) - // Addition - FADD : begin - fpu_op_d = OP_ADD; - replicate_c = 1'b1; // second operand is in C - end - // Subtraction is modified ADD - FSUB : begin - fpu_op_d = OP_ADD; - fpu_op_mod_d = 1'b1; - replicate_c = 1'b1; // second operand is in C - end - // Multiplication - FMUL : fpu_op_d = OP_MUL; - // Division - FDIV : fpu_op_d = OP_DIV; - // Min/Max - OP is encoded in rm (000-001) - FMIN_MAX : begin - fpu_op_d = OP_MINMAX; - fpu_rm_d = {1'b0, fpu_rm_i[1:0]}; // mask out AH encoding bit - check_ah = 1'b1; // AH has RM MSB encoding - end - // Square Root - FSQRT : fpu_op_d = OP_SQRT; - // Fused Multiply Add - FMADD : fpu_op_d = OP_FMADD; - // Fused Multiply Subtract is modified FMADD - FMSUB : begin - fpu_op_d = OP_FMADD; - fpu_op_mod_d = 1'b1; - end - // Fused Negated Multiply Subtract - FNMSUB : fpu_op_d = OP_FNMSUB; - // Fused Negated Multiply Add is modified FNMSUB - FNMADD : begin - fpu_op_d = OP_FNMSUB; - fpu_op_mod_d = 1'b1; - end - // Float to Int Cast - Op encoded in lowest two imm bits or rm - FCVT_F2I : begin - fpu_op_d = OP_F2I; - // Vectorial Ops encoded in R bit - if (fpu_vec_op_d) begin - fpu_op_mod_d = fpu_rm_i[0]; - vec_replication = 1'b0; // no replication, R bit used for op - unique case (fpu_fmt_i) - 2'b00 : fpu_ifmt_d = IFMT_INT32; - 2'b01, - 2'b10 : fpu_ifmt_d = IFMT_INT16; - 2'b11 : fpu_ifmt_d = IFMT_INT8; - endcase - // Scalar casts encoded in imm - end else begin - fpu_op_mod_d = operand_c_i[0]; - if (operand_c_i[1]) - fpu_ifmt_d = IFMT_INT64; - else - fpu_ifmt_d = IFMT_INT32; - end - end - // Int to Float Cast - Op encoded in lowest two imm bits or rm - FCVT_I2F : begin - fpu_op_d = OP_I2F; - // Vectorial Ops encoded in R bit - if (fpu_vec_op_d) begin - fpu_op_mod_d = fpu_rm_i[0]; - vec_replication = 1'b0; // no replication, R bit used for op - unique case (fpu_fmt_i) - 2'b00 : fpu_ifmt_d = IFMT_INT32; - 2'b01, - 2'b10 : fpu_ifmt_d = IFMT_INT16; - 2'b11 : fpu_ifmt_d = IFMT_INT8; - endcase - // Scalar casts encoded in imm - end else begin - fpu_op_mod_d = operand_c_i[0]; - if (operand_c_i[1]) - fpu_ifmt_d = IFMT_INT64; - else - fpu_ifmt_d = IFMT_INT32; - end - end - // Float to Float Cast - Source format encoded in lowest two/three imm bits - FCVT_F2F : begin - fpu_op_d = OP_F2F; - // Vectorial ops encoded in lowest two imm bits - if (fpu_vec_op_d) begin - vec_replication = 1'b0; // no replication for casts (not needed) - unique case (operand_c_i[1:0]) - 2'b00: fpu_fmt2_d = FMT_FP32; - 2'b01: fpu_fmt2_d = FMT_FP16ALT; - 2'b10: fpu_fmt2_d = FMT_FP16; - 2'b11: fpu_fmt2_d = FMT_FP8; - endcase - // Scalar ops encoded in lowest three imm bits - end else begin - unique case (operand_c_i[2:0]) - 3'b000: fpu_fmt2_d = FMT_FP32; - 3'b001: fpu_fmt2_d = FMT_FP64; - 3'b010: fpu_fmt2_d = FMT_FP16; - 3'b110: fpu_fmt2_d = FMT_FP16ALT; - 3'b011: fpu_fmt2_d = FMT_FP8; - endcase - end - end - // Scalar Sign Injection - op encoded in rm (000-010) - FSGNJ : begin - fpu_op_d = OP_SGNJ; - fpu_rm_d = {1'b0, fpu_rm_i[1:0]}; // mask out AH encoding bit - check_ah = 1'b1; // AH has RM MSB encoding - end - // Move from FPR to GPR - mapped to SGNJ-passthrough since no recoding - FMV_F2X : begin - fpu_op_d = OP_SGNJ; - fpu_rm_d = 3'b011; // passthrough without checking nan-box - fpu_op_mod_d = 1'b1; // no NaN-Boxing - check_ah = 1'b1; // AH has RM MSB encoding - vec_replication = 1'b0; // no replication, we set second operand - end - // Move from GPR to FPR - mapped to NOP since no recoding - FMV_X2F : begin - fpu_op_d = OP_SGNJ; - fpu_rm_d = 3'b011; // passthrough without checking nan-box - check_ah = 1'b1; // AH has RM MSB encoding - vec_replication = 1'b0; // no replication, we set second operand - end - // Scalar Comparisons - op encoded in rm (000-010) - FCMP : begin - fpu_op_d = OP_CMP; - fpu_rm_d = {1'b0, fpu_rm_i[1:0]}; // mask out AH encoding bit - check_ah = 1'b1; // AH has RM MSB encoding - end - // Classification - FCLASS : begin - fpu_op_d = OP_CLASS; - fpu_rm_d = {1'b0, fpu_rm_i[1:0]}; // mask out AH encoding bit - CLASS doesn't care anyways - check_ah = 1'b1; // AH has RM MSB encoding - end - // Vectorial Minimum - set up scalar encoding in rm - VFMIN : begin - fpu_op_d = OP_MINMAX; - fpu_rm_d = 3'b000; // min - end - // Vectorial Maximum - set up scalar encoding in rm - VFMAX : begin - fpu_op_d = OP_MINMAX; - fpu_rm_d = 3'b001; // max - end - // Vectorial Sign Injection - set up scalar encoding in rm - VFSGNJ : begin - fpu_op_d = OP_SGNJ; - fpu_rm_d = 3'b000; // sgnj - end - // Vectorial Negated Sign Injection - set up scalar encoding in rm - VFSGNJN : begin - fpu_op_d = OP_SGNJ; - fpu_rm_d = 3'b001; // sgnjn - end - // Vectorial Xored Sign Injection - set up scalar encoding in rm - VFSGNJX : begin - fpu_op_d = OP_SGNJ; - fpu_rm_d = 3'b010; // sgnjx - end - // Vectorial Equals - set up scalar encoding in rm - VFEQ : begin - fpu_op_d = OP_CMP; - fpu_rm_d = 3'b010; // eq - end - // Vectorial Not Equals - set up scalar encoding in rm - VFNE : begin - fpu_op_d = OP_CMP; - fpu_op_mod_d = 1'b1; // invert output - fpu_rm_d = 3'b010; // eq - end - // Vectorial Less Than - set up scalar encoding in rm - VFLT : begin - fpu_op_d = OP_CMP; - fpu_rm_d = 3'b001; // lt - end - // Vectorial Greater or Equal - set up scalar encoding in rm - VFGE : begin - fpu_op_d = OP_CMP; - fpu_op_mod_d = 1'b1; // invert output - fpu_rm_d = 3'b001; // lt - end - // Vectorial Less or Equal - set up scalar encoding in rm - VFLE : begin - fpu_op_d = OP_CMP; - fpu_rm_d = 3'b000; // le - end - // Vectorial Greater Than - set up scalar encoding in rm - VFGT : begin - fpu_op_d = OP_CMP; - fpu_op_mod_d = 1'b1; // invert output - fpu_rm_d = 3'b000; // le - end - // Vectorial Convert-and-Pack from FP32, lower 4 entries - VFCPKAB_S : begin - fpu_op_d = OP_CPKAB; - fpu_op_mod_d = fpu_rm_i[0]; // A/B selection from R bit - vec_replication = 1'b0; // no replication, R bit used for op - fpu_fmt2_d = FMT_FP32; // Cast from FP32 - end - // Vectorial Convert-and-Pack from FP32, upper 4 entries - VFCPKCD_S : begin - fpu_op_d = OP_CPKCD; - fpu_op_mod_d = fpu_rm_i[0]; // C/D selection from R bit - vec_replication = 1'b0; // no replication, R bit used for op - fpu_fmt2_d = FMT_FP64; // Cast from FP64 - end - // Vectorial Convert-and-Pack from FP64, lower 4 entries - VFCPKAB_S : begin - fpu_op_d = OP_CPKAB; - fpu_op_mod_d = fpu_rm_i[0]; // A/B selection from R bit - vec_replication = 1'b0; // no replication, R bit used for op - fpu_fmt2_d = FMT_FP64; // Cast from FP64 - end - // Vectorial Convert-and-Pack from FP64, upper 4 entries - VFCPKCD_S : begin - fpu_op_d = OP_CPKCD; - fpu_op_mod_d = fpu_rm_i[0]; // C/D selection from R bit - vec_replication = 1'b0; // no replication, R bit used for op - fpu_fmt2_d = FMT_FP64; // Cast from FP64 - end - - // No changes per default - default : ; //nothing - endcase - // Scalar AH encoding fixing - if (!fpu_vec_op_d && check_ah) - if (fpu_rm_i[2]) - fpu_fmt_d = FMT_FP16ALT; - - // Replication - if (fpu_vec_op_d && vec_replication) begin - if (replicate_c) begin - unique case (fpu_fmt_d) - FMT_FP32 : operand_c_d = RVD ? {2{operand_c_i[31:0]}} : operand_c_i; - FMT_FP16, - FMT_FP16ALT : operand_c_d = RVD ? {4{operand_c_i[15:0]}} : {2{operand_c_i[15:0]}}; - FMT_FP8 : operand_c_d = RVD ? {8{operand_c_i[7:0]}} : {4{operand_c_i[7:0]}}; - endcase // fpu_fmt_d - end else begin - unique case (fpu_fmt_d) - FMT_FP32 : operand_b_d = RVD ? {2{operand_b_i[31:0]}} : operand_b_i; - FMT_FP16, - FMT_FP16ALT : operand_b_d = RVD ? {4{operand_b_i[15:0]}} : {2{operand_b_i[15:0]}}; - FMT_FP8 : operand_b_d = RVD ? {8{operand_b_i[7:0]}} : {4{operand_b_i[7:0]}}; - endcase // fpu_fmt_d - end - end - end - - - //--------------------------------------------------------- - // Upstream protocol inversion: InValid depends on InReady - //--------------------------------------------------------- - - always_comb begin : p_inputFSM - // Default Values - fpu_ready_o = 1'b0; - fpu_in_valid = 1'b0; - hold_inputs = 1'b0; // hold register disabled - use_hold = 1'b0; // inputs go directly to unit - state_d = state_q; // stay in the same state - - // FSM - unique case (state_q) - // Default state, ready for instructions - READY : begin - fpu_ready_o = 1'b1; // Act as if FPU ready - fpu_in_valid = fpu_valid_i; // Forward input valid to FPU - // There is a transaction but the FPU can't handle it - if (fpu_valid_i & ~fpu_in_ready) begin - fpu_ready_o = 1'b0; // No token given to Issue - hold_inputs = 1'b1; // save inputs to the holding register - state_d = STALL; // stall future incoming requests - end - end - // We're stalling the upstream (ready=0) - STALL : begin - fpu_in_valid = 1'b1; // we have data for the FPU - use_hold = 1'b1; // the data comes from the hold reg - // Wait until it's consumed - if (fpu_in_ready) begin - fpu_ready_o = 1'b1; // Give a token to issue - state_d = READY; // accept future requests - end - end - // Default: emit default values - default : ; - endcase + //--------------------------------------------------------- + // Upstream protocol inversion: InValid depends on InReady + //--------------------------------------------------------- + + always_comb begin : p_inputFSM + // Default Values + fpu_ready_o = 1'b0; + fpu_in_valid = 1'b0; + hold_inputs = 1'b0; // hold register disabled + use_hold = 1'b0; // inputs go directly to unit + state_d = state_q; // stay in the same state + + // FSM + unique case (state_q) + // Default state, ready for instructions + READY : begin + fpu_ready_o = 1'b1; // Act as if FPU ready + fpu_in_valid = fpu_valid_i; // Forward input valid to FPU + // There is a transaction but the FPU can't handle it + if (fpu_valid_i & ~fpu_in_ready) begin + fpu_ready_o = 1'b0; // No token given to Issue + hold_inputs = 1'b1; // save inputs to the holding register + state_d = STALL; // stall future incoming requests + end + end + // We're stalling the upstream (ready=0) + STALL : begin + fpu_in_valid = 1'b1; // we have data for the FPU + use_hold = 1'b1; // the data comes from the hold reg + // Wait until it's consumed + if (fpu_in_ready) begin + fpu_ready_o = 1'b1; // Give a token to issue + state_d = READY; // accept future requests + end + end + // Default: emit default values + default : ; + endcase - // Flushing will override issue and go back to idle - if (flush_i) begin - state_d = READY; - end - - end - - // Buffer register and FSM state holding - always_ff @(posedge clk_i or negedge rst_ni) begin : fp_hold_reg - if(~rst_ni) begin - state_q <= READY; - operand_a_q <= '0; - operand_b_q <= '0; - operand_c_q <= '0; - fpu_op_q <= '0; - fpu_op_mod_q <= '0; - fpu_fmt_q <= '0; - fpu_fmt2_q <= '0; - fpu_ifmt_q <= '0; - fpu_rm_q <= '0; - fpu_vec_op_q <= '0; - fpu_tag_q <= '0; - end else begin - state_q <= state_d; - // Hold register is [TRIGGERED] by FSM - if (hold_inputs) begin - operand_a_q <= operand_a_d; - operand_b_q <= operand_b_d; - operand_c_q <= operand_c_d; - fpu_op_q <= fpu_op_d; - fpu_op_mod_q <= fpu_op_mod_d; - fpu_fmt_q <= fpu_fmt_d; - fpu_fmt2_q <= fpu_fmt2_d; - fpu_ifmt_q <= fpu_ifmt_d; - fpu_rm_q <= fpu_rm_d; - fpu_vec_op_q <= fpu_vec_op_d; - fpu_tag_q <= fpu_tag_d; - end - end - end - - // Select FPU input data: from register if valid data in register, else directly from input - assign operand_a = use_hold ? operand_a_q : operand_a_d; - assign operand_b = use_hold ? operand_b_q : operand_b_d; - assign operand_c = use_hold ? operand_c_q : operand_c_d; - assign fpu_op = use_hold ? fpu_op_q : fpu_op_d; - assign fpu_op_mod = use_hold ? fpu_op_mod_q : fpu_op_mod_d; - assign fpu_fmt = use_hold ? fpu_fmt_q : fpu_fmt_d; - assign fpu_fmt2 = use_hold ? fpu_fmt2_q : fpu_fmt2_d; - assign fpu_ifmt = use_hold ? fpu_ifmt_q : fpu_ifmt_d; - assign fpu_rm = use_hold ? fpu_rm_q : fpu_rm_d; - assign fpu_vec_op = use_hold ? fpu_vec_op_q : fpu_vec_op_d; - assign fpu_tag = use_hold ? fpu_tag_q : fpu_tag_d; - - //--------------- - // FPU instance - //--------------- - fpnew_top #( - .WIDTH ( FLEN ), - .TAG_WIDTH ( TRANS_ID_BITS ), - .RV64 ( 1'b1 ), - .RVF ( RVF ), - .RVD ( RVD ), - .Xf16 ( XF16 ), - .Xf16alt ( XF16ALT ), - .Xf8 ( XF8 ), - .Xfvec ( XFVEC ), - // TODO MOVE THESE VALUES TO PACKAGE - .LATENCY_COMP_F ( LAT_COMP_FP32 ), - .LATENCY_COMP_D ( LAT_COMP_FP64 ), - .LATENCY_COMP_Xf16 ( LAT_COMP_FP16 ), - .LATENCY_COMP_Xf16alt ( LAT_COMP_FP16ALT ), - .LATENCY_COMP_Xf8 ( LAT_COMP_FP8 ), - .LATENCY_DIVSQRT ( LAT_DIVSQRT ), - .LATENCY_NONCOMP ( LAT_NONCOMP ), - .LATENCY_CONV ( LAT_CONV ) - ) fpnew_top_i ( - .Clk_CI ( clk_i ), - .Reset_RBI ( rst_ni ), - .A_DI ( operand_a ), - .B_DI ( operand_b ), - .C_DI ( operand_c ), - .RoundMode_SI ( fpu_rm ), - .Op_SI ( fpu_op ), - .OpMod_SI ( fpu_op_mod ), - .VectorialOp_SI ( fpu_vec_op ), - .FpFmt_SI ( fpu_fmt ), - .FpFmt2_SI ( fpu_fmt2 ), - .IntFmt_SI ( fpu_ifmt ), - .Tag_DI ( fpu_tag ), - .PrecCtl_SI ( fpu_prec_i ), - .InValid_SI ( fpu_in_valid ), - .InReady_SO ( fpu_in_ready ), - .Flush_SI ( flush_i ), - .Z_DO ( result_o ), - .Status_DO ( fpu_status ), - .Tag_DO ( fpu_trans_id_o ), - .OutValid_SO ( fpu_out_valid ), - .OutReady_SI ( fpu_out_ready ) - ); - - // Pack status flag into exception cause, tval ignored in wb, exception is always invalid - assign fpu_exception_o.cause = {59'h0, fpu_status}; - assign fpu_exception_o.valid = 1'b0; - - // Donwstream write port is dedicated to FPU and always ready - assign fpu_out_ready = 1'b1; - - // Downstream valid from unit - assign fpu_valid_o = fpu_out_valid; + // Flushing will override issue and go back to idle + if (flush_i) begin + state_d = READY; + end end + + // Buffer register and FSM state holding + always_ff @(posedge clk_i or negedge rst_ni) begin : fp_hold_reg + if(~rst_ni) begin + state_q <= READY; + operand_a_q <= '0; + operand_b_q <= '0; + operand_c_q <= '0; + fpu_op_q <= '0; + fpu_op_mod_q <= '0; + fpu_srcfmt_q <= '0; + fpu_dstfmt_q <= '0; + fpu_ifmt_q <= '0; + fpu_rm_q <= '0; + fpu_vec_op_q <= '0; + fpu_tag_q <= '0; + end else begin + state_q <= state_d; + // Hold register is [TRIGGERED] by FSM + if (hold_inputs) begin + operand_a_q <= operand_a_d; + operand_b_q <= operand_b_d; + operand_c_q <= operand_c_d; + fpu_op_q <= fpu_op_d; + fpu_op_mod_q <= fpu_op_mod_d; + fpu_srcfmt_q <= fpu_srcfmt_d; + fpu_dstfmt_q <= fpu_dstfmt_d; + fpu_ifmt_q <= fpu_ifmt_d; + fpu_rm_q <= fpu_rm_d; + fpu_vec_op_q <= fpu_vec_op_d; + fpu_tag_q <= fpu_tag_d; + end + end + end + + // Select FPU input data: from register if valid data in register, else directly from input + assign operand_a = use_hold ? operand_a_q : operand_a_d; + assign operand_b = use_hold ? operand_b_q : operand_b_d; + assign operand_c = use_hold ? operand_c_q : operand_c_d; + assign fpu_op = use_hold ? fpu_op_q : fpu_op_d; + assign fpu_op_mod = use_hold ? fpu_op_mod_q : fpu_op_mod_d; + assign fpu_srcfmt = use_hold ? fpu_srcfmt_q : fpu_srcfmt_d; + assign fpu_dstfmt = use_hold ? fpu_dstfmt_q : fpu_dstfmt_d; + assign fpu_ifmt = use_hold ? fpu_ifmt_q : fpu_ifmt_d; + assign fpu_rm = use_hold ? fpu_rm_q : fpu_rm_d; + assign fpu_vec_op = use_hold ? fpu_vec_op_q : fpu_vec_op_d; + assign fpu_tag = use_hold ? fpu_tag_q : fpu_tag_d; + + // Consolidate operands + logic [2:0][FLEN-1:0] fpu_operands; + + assign fpu_operands[0] = operand_a; + assign fpu_operands[1] = operand_b; + assign fpu_operands[2] = operand_c; + + //--------------- + // FPU instance + //--------------- + + fpnew_top #( + .Features ( FPU_FEATURES ), + .Implementation ( FPU_IMPLEMENTATION ), + .TagType ( logic [TRANS_ID_BITS-1:0] ) + ) i_fpnew_bulk ( + .clk_i, + .rst_ni, + .operands_i ( fpu_operands ), + .rnd_mode_i ( fpnew_pkg::roundmode_e'(fpu_rm) ), + .op_i ( fpnew_pkg::operation_e'(fpu_op) ), + .op_mod_i ( fpu_op_mod ), + .src_fmt_i ( fpnew_pkg::fp_format_e'(fpu_srcfmt) ), + .dst_fmt_i ( fpnew_pkg::fp_format_e'(fpu_dstfmt) ), + .int_fmt_i ( fpnew_pkg::int_format_e'(fpu_ifmt) ), + .vectorial_op_i ( fpu_vec_op ), + .tag_i ( fpu_tag ), + .in_valid_i ( fpu_in_valid ), + .in_ready_o ( fpu_in_ready ), + .flush_i, + .result_o, + .status_o ( fpu_status ), + .tag_o ( fpu_trans_id_o ), + .out_valid_o ( fpu_out_valid ), + .out_ready_i ( fpu_out_ready ), + .busy_o ( /* unused */ ) + ); + + // Pack status flag into exception cause, tval ignored in wb, exception is always invalid + assign fpu_exception_o.cause = {59'h0, fpu_status}; + assign fpu_exception_o.valid = 1'b0; + + // Donwstream write port is dedicated to FPU and always ready + assign fpu_out_ready = 1'b1; + + // Downstream valid from unit + assign fpu_valid_o = fpu_out_valid; + + end endgenerate endmodule diff --git a/src/load_store_unit.sv b/src/load_store_unit.sv index 5f475b62ab18659de31fae85664404bb78e64c24..97502afccbf8f72c8785d2f88f5d00bff181d063 100644 --- a/src/load_store_unit.sv +++ b/src/load_store_unit.sv @@ -205,7 +205,7 @@ module load_store_unit #( // ---------------------------- // Output Pipeline Register // ---------------------------- - pipe_reg_simple #( + shift_reg #( .dtype ( logic[$bits(ld_valid) + $bits(ld_trans_id) + $bits(ld_result) + $bits(ld_ex) - 1: 0]), .Depth ( NR_LOAD_PIPE_REGS ) ) i_pipe_reg_load ( @@ -215,7 +215,7 @@ module load_store_unit #( .d_o ( {load_valid_o, load_trans_id_o, load_result_o, load_exception_o} ) ); - pipe_reg_simple #( + shift_reg #( .dtype ( logic[$bits(st_valid) + $bits(st_trans_id) + $bits(st_result) + $bits(st_ex) - 1: 0]), .Depth ( NR_STORE_PIPE_REGS ) ) i_pipe_reg_store (