From b7346252bdd4127bdb9705bb3658d8db6899fb8e Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?s=C3=A9bastien=20jacq?= <57099003+sjthales@users.noreply.github.com> Date: Mon, 7 Dec 2020 09:55:05 +0100 Subject: [PATCH] Update README.md --- README.md | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/README.md b/README.md index 8e2632d3..832b1e96 100644 --- a/README.md +++ b/README.md @@ -232,7 +232,7 @@ Below is described steps to run Coremark application on CV32A6 FPGA platform, st ## Get started with Coremark application -1. First, make sure the digilent **JTAG-HS2 debug adapter** is properly connected to the **PMOD JE** connector and that the USBAUART adapter is properly connected to the **PMOD JB** connector of the Zybo Z7-20 board. +1. First, make sure the digilent **JTAG-HS2 debug adapter** is properly connected to the **PMOD JE** connector and that the USBUART adapter is properly connected to the **PMOD JB** connector of the Zybo Z7-20 board.  2. Compile coremark application in `sw/app` 3. Generate the bitstream of the FPGA platform: -- GitLab