diff --git a/src/ariane.sv b/src/ariane.sv index 7726a772b962be83d8e5a01320ac02e525353aad..5ea04ec5f7d4bdb3ad3e4c35e48f4409a47a78f5 100644 --- a/src/ariane.sv +++ b/src/ariane.sv @@ -101,6 +101,7 @@ module ariane import ariane_pkg::*; #( // ISSUE -> verifier // -------------- logic has_mem_access_is_verif; + logic has_ctrl_flow_is_icache; // -------------- // ISSUE <-> EX @@ -376,6 +377,7 @@ module ariane import ariane_pkg::*; #( .commit_instr_o ( commit_instr_id_commit ), .commit_ack_i ( commit_ack ), .has_mem_access_o ( has_mem_access_is_verif ), + .has_control_flow_o ( has_ctrl_flow_is_icache ), .* ); diff --git a/src/issue_stage.sv b/src/issue_stage.sv index 54c4122187c426f63891f2dcb6892c39d133fcd0..c20e8b2c6393a50cafa720e7c68c13b0dd84e207 100644 --- a/src/issue_stage.sv +++ b/src/issue_stage.sv @@ -73,7 +73,8 @@ module issue_stage import ariane_pkg::*; #( input logic [NR_COMMIT_PORTS-1:0] commit_ack_i, // to verifier - output has_mem_access_o + output logic has_control_flow_o, + output logic has_mem_access_o ); // --------------------------------------------------- // Scoreboard (SB) <-> Issue and Read Operands (IRO) diff --git a/src/scoreboard.sv b/src/scoreboard.sv index a20b0ef1cabe3b5ba59230f1ce2f8e3cc7fc021a..e5876d03813fd124d0182ad8430fa7eebc8bd093 100644 --- a/src/scoreboard.sv +++ b/src/scoreboard.sv @@ -63,6 +63,7 @@ module scoreboard #( input logic [NR_WB_PORTS-1:0] wt_valid_i, // data in is valid // to verifier + output logic has_control_flow_o, output logic has_mem_access_o ); localparam int unsigned BITS_ENTRIES = $clog2(NR_ENTRIES); @@ -81,6 +82,7 @@ module scoreboard #( logic [$clog2(NR_COMMIT_PORTS):0] num_commit; logic [NR_ENTRIES-1:0] has_mem_access_n, has_mem_access_q; + logic [NR_ENTRIES-1:0] is_cf_n, is_cf_q; // the issue queue is full don't issue any new instructions // works since aligned to power of 2 @@ -96,8 +98,9 @@ module scoreboard #( end end - // check instructions in the scoreboard for memory operations + // check instructions in the scoreboard for memory operations and ctrl flow assign has_mem_access_o = (|has_mem_access_q); + assign has_control_flow_o = (|is_cf_q); // an instruction is ready for issue if we have place in the issue FIFO and it the decoder says it is valid always_comb begin @@ -117,6 +120,7 @@ module scoreboard #( mem_n = mem_q; issue_en = 1'b0; has_mem_access_n = has_mem_access_q; + is_cf_n = is_cf_q; // if we got a acknowledge from the issue stage, put this scoreboard entry in the queue if (decoded_instr_valid_i && decoded_instr_ack_o && !flush_unissued_instr_i) begin @@ -128,6 +132,7 @@ module scoreboard #( decoded_instr_i // decoded instruction record }; has_mem_access_n[issue_pointer_q] = decoded_instr_i.fu inside {ariane_pkg::LOAD, ariane_pkg::STORE}; + is_cf_n[issue_pointer_q] = decoded_instr_i.fu == ariane_pkg::CTRL_FLOW && decoded_instr_i.op != ariane_pkg::ADD; end // ------------ @@ -159,6 +164,8 @@ module scoreboard #( if (mem_n[trans_id_i[i]].sbe.fu != ariane_pkg::STORE) has_mem_access_n[trans_id_i[i]] = 1'b0; + + is_cf_n[trans_id_i[i]] = 1'b0; end end @@ -172,6 +179,7 @@ module scoreboard #( mem_n[commit_pointer_q[i]].issued = 1'b0; mem_n[commit_pointer_q[i]].sbe.valid = 1'b0; has_mem_access_n[commit_pointer_q[i]] = 1'b0; + is_cf_n[commit_pointer_q[i]] = 1'b0; end end @@ -185,6 +193,7 @@ module scoreboard #( mem_n[i].sbe.valid = 1'b0; mem_n[i].sbe.ex.valid = 1'b0; has_mem_access_n[i] = 1'b0; + is_cf_n[i] = 1'b0; end end end @@ -373,12 +382,14 @@ module scoreboard #( commit_pointer_q <= '0; issue_pointer_q <= '0; has_mem_access_q <= '0; + is_cf_q <= '0; end else begin issue_cnt_q <= issue_cnt_n; issue_pointer_q <= issue_pointer_n; mem_q <= mem_n; commit_pointer_q <= commit_pointer_n; has_mem_access_q <= has_mem_access_n; + is_cf_q <= is_cf_n; end end