From 609df61a62a4197ca78fb7738eb448aa7a6978d7 Mon Sep 17 00:00:00 2001
From: Alban Gruin <alban.gruin@irit.fr>
Date: Thu, 18 Mar 2021 13:14:39 +0100
Subject: [PATCH] decoder: add logic output to say if there is a memory
instruction
Signed-off-by: Alban Gruin <alban.gruin@irit.fr>
---
src/ariane.sv | 9 +++++++++
src/id_stage.sv | 23 ++++++++++++++++++-----
src/verifier.sv | 3 +++
3 files changed, 30 insertions(+), 5 deletions(-)
diff --git a/src/ariane.sv b/src/ariane.sv
index 4fc9e1a5..4463e622 100644
--- a/src/ariane.sv
+++ b/src/ariane.sv
@@ -89,6 +89,11 @@ module ariane import ariane_pkg::*; #(
logic is_ctrl_fow_id_issue;
logic issue_instr_issue_id;
+ // --------------
+ // ID -> verifier
+ // --------------
+ logic has_mem_access_id_verif;
+
// --------------
// ISSUE <-> EX
// --------------
@@ -286,6 +291,7 @@ module ariane import ariane_pkg::*; #(
.issue_entry_o ( issue_entry_id_issue ),
.issue_entry_valid_o ( issue_entry_valid_id_issue ),
.is_ctrl_flow_o ( is_ctrl_fow_id_issue ),
+ .is_mem_instr_o ( has_mem_access_id_verif ),
.issue_instr_ack_i ( issue_instr_issue_id ),
.priv_lvl_i ( priv_lvl ),
@@ -626,6 +632,9 @@ module ariane import ariane_pkg::*; #(
// IF
.if_has_mem_access_i (has_mem_access_if_verif),
+ // ID
+ .id_has_mem_access_i (has_mem_access_id_verif),
+
// CO
.commit_instr_i (commit_instr_id_commit),
.commit_ack_i (commit_ack)
diff --git a/src/id_stage.sv b/src/id_stage.sv
index 9d661040..7edc74a9 100644
--- a/src/id_stage.sv
+++ b/src/id_stage.sv
@@ -37,7 +37,8 @@ module id_stage (
input logic debug_mode_i, // we are in debug mode
input logic tvm_i,
input logic tw_i,
- input logic tsr_i
+ input logic tsr_i,
+ output logic is_mem_instr_o
);
// ID/ISSUE register stage
struct packed {
@@ -53,6 +54,8 @@ module id_stage (
logic [31:0] instruction;
logic is_compressed;
+ logic is_mem_instr_n, is_mem_instr_q;
+
// ---------------------------------------------------------
// 1. Check if they are compressed and expand in case they are
// ---------------------------------------------------------
@@ -94,25 +97,33 @@ module id_stage (
assign issue_entry_valid_o = issue_q.valid;
assign is_ctrl_flow_o = issue_q.is_ctrl_flow;
+ assign is_mem_instr_o = is_mem_instr_q;
+
always_comb begin
issue_n = issue_q;
fetch_entry_ready_o = 1'b0;
+ is_mem_instr_n = is_mem_instr_q;
// Clear the valid flag if issue has acknowledged the instruction
- if (issue_instr_ack_i)
+ if (issue_instr_ack_i) begin
issue_n.valid = 1'b0;
+ is_mem_instr_n = 1'b0;
+ end
// if we have a space in the register and the fetch is valid, go get it
// or the issue stage is currently acknowledging an instruction, which means that we will have space
// for a new instruction
if ((!issue_q.valid || issue_instr_ack_i) && fetch_entry_valid_i) begin
- fetch_entry_ready_o = 1'b1;
- issue_n = '{1'b1, decoded_instruction, is_control_flow_instr};
+ fetch_entry_ready_o = 1'b1;
+ issue_n = '{1'b1, decoded_instruction, is_control_flow_instr};
+ is_mem_instr_n = (decoded_instruction.fu == ariane_pkg::LOAD || decoded_instruction.fu == ariane_pkg::STORE);
end
// invalidate the pipeline register on a flush
- if (flush_i)
+ if (flush_i) begin
issue_n.valid = 1'b0;
+ is_mem_instr_n = 1'b0;
+ end
end
// -------------------------
// Registers (ID <-> Issue)
@@ -120,8 +131,10 @@ module id_stage (
always_ff @(posedge clk_i or negedge rst_ni) begin
if(~rst_ni) begin
issue_q <= '0;
+ is_mem_instr_q <= '0;
end else begin
issue_q <= issue_n;
+ is_mem_instr_q <= is_mem_instr_n;
end
end
endmodule
diff --git a/src/verifier.sv b/src/verifier.sv
index 24fdfdb5..cc4278b8 100644
--- a/src/verifier.sv
+++ b/src/verifier.sv
@@ -9,6 +9,9 @@ module verifier #(
// Frontend
input logic if_has_mem_access_i,
+ // ID
+ input logic id_has_mem_access_i,
+
// CO
input ariane_pkg::scoreboard_entry_t [NR_COMMIT_PORTS-1:0] commit_instr_i,
input logic [NR_COMMIT_PORTS-1:0] commit_ack_i
--
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