diff --git a/src/frontend/bht.sv b/src/frontend/bht.sv
index 9eae69d3559a21f07f8af295c91c3e5044e47c7b..e57c34bb7fa0de0fbcf2d4b8b22036f6a34b1e5f 100644
--- a/src/frontend/bht.sv
+++ b/src/frontend/bht.sv
@@ -34,8 +34,6 @@ module bht #(
     localparam ROW_ADDR_BITS = $clog2(ariane_pkg::INSTR_PER_FETCH);
     // number of bits we should use for prediction
     localparam PREDICTION_BITS = $clog2(NR_ROWS) + OFFSET + ROW_ADDR_BITS;
-    // we are not interested in all bits of the address
-    unread i_unread (.d_i(|vpc_i));
 
     struct packed {
         logic       valid;
diff --git a/src/frontend/btb.sv b/src/frontend/btb.sv
index 86eeadc0ac34e6079c9238da41a36b23708cf199..23f365fd460c91e22542f154b2221ffabd955ba1 100644
--- a/src/frontend/btb.sv
+++ b/src/frontend/btb.sv
@@ -36,8 +36,6 @@ module btb #(
     localparam PREDICTION_BITS = $clog2(NR_ROWS) + OFFSET + ROW_ADDR_BITS;
     // prevent aliasing to degrade performance
     localparam ANTIALIAS_BITS = 8;
-    // we are not interested in all bits of the address
-    unread i_unread (.d_i(|vpc_i));
 
     // typedef for all branch target entries
     // we may want to try to put a tag field that fills the rest of the PC in-order to mitigate aliasing effects
diff --git a/src/frontend/instr_queue.sv b/src/frontend/instr_queue.sv
index 15f3269db11af574f1296eecdccb19eab4892fdd..84df044d9528fc4532798cf5de4f9fdee6490956 100644
--- a/src/frontend/instr_queue.sv
+++ b/src/frontend/instr_queue.sv
@@ -374,12 +374,6 @@ module instr_queue (
     .pop_i      ( pop_address                  )
   );
 
-  unread i_unread_address_fifo (.d_i(|{empty_address, address_queue_usage}));
-  unread i_unread_branch_mask (.d_i(|branch_mask_extended));
-  unread i_unread_lzc (.d_i(|{branch_empty}));
-  unread i_unread_fifo_pos (.d_i(|fifo_pos_extended)); // we don't care about the lower signals
-  unread i_unread_instr_fifo (.d_i(|instr_queue_usage));
-
   always_ff @(posedge clk_i or negedge rst_ni) begin
     if (!rst_ni) begin
       idx_ds_q        <= 'b1;