From dbcec1ab3055e6c7b71a5e01fb00a225ffd47070 Mon Sep 17 00:00:00 2001
From: Alban Gruin <alban.gruin@irit.fr>
Date: Tue, 23 Mar 2021 16:02:46 +0100
Subject: [PATCH] [WIP] cache: add a signal to stall the I$
Signed-off-by: Alban Gruin <alban.gruin@irit.fr>
---
src/ariane.sv | 6 +++++-
src/cache_subsystem/wt_cache_subsystem.sv | 4 +++-
src/cache_subsystem/wt_icache.sv | 3 ++-
src/verifier.sv | 3 ++-
4 files changed, 12 insertions(+), 4 deletions(-)
diff --git a/src/ariane.sv b/src/ariane.sv
index b745effe..eaefd779 100644
--- a/src/ariane.sv
+++ b/src/ariane.sv
@@ -240,6 +240,7 @@ module ariane import ariane_pkg::*; #(
icache_areq_o_t icache_areq_cache_ex;
icache_dreq_i_t icache_dreq_if_cache;
icache_dreq_o_t icache_dreq_cache_if;
+ logic icache_stall_ctrl;
amo_req_t amo_req;
amo_resp_t amo_resp;
@@ -652,7 +653,9 @@ module ariane import ariane_pkg::*; #(
// CO
.commit_instr_i (commit_instr_id_commit),
- .commit_ack_i (commit_ack)
+ .commit_ack_i (commit_ack),
+
+ .should_lock_icache_o (icache_stall_ctrl)
);
// -------------------
@@ -675,6 +678,7 @@ module ariane import ariane_pkg::*; #(
.icache_areq_o ( icache_areq_cache_ex ),
.icache_dreq_i ( icache_dreq_if_cache ),
.icache_dreq_o ( icache_dreq_cache_if ),
+ .icache_stall_i ( icache_stall_ctrl ),
// D$
.dcache_enable_i ( dcache_en_csr_nbdcache ),
.dcache_flush_i ( dcache_flush_ctrl_cache ),
diff --git a/src/cache_subsystem/wt_cache_subsystem.sv b/src/cache_subsystem/wt_cache_subsystem.sv
index 5a0662dc..3dc470d6 100644
--- a/src/cache_subsystem/wt_cache_subsystem.sv
+++ b/src/cache_subsystem/wt_cache_subsystem.sv
@@ -34,6 +34,7 @@ module wt_cache_subsystem import ariane_pkg::*; import wt_cache_pkg::*; #(
// data requests
input icache_dreq_i_t icache_dreq_i, // to/from frontend
output icache_dreq_o_t icache_dreq_o,
+ input logic icache_stall_i,
// D$
// Cache management
input logic dcache_enable_i, // from CSR
@@ -88,7 +89,8 @@ module wt_cache_subsystem import ariane_pkg::*; import wt_cache_pkg::*; #(
.mem_rtrn_i ( adapter_icache ),
.mem_data_req_o ( icache_adapter_data_req ),
.mem_data_ack_i ( adapter_icache_data_ack ),
- .mem_data_o ( icache_adapter )
+ .mem_data_o ( icache_adapter ),
+ .stall_req_i ( icache_stall_i )
);
diff --git a/src/cache_subsystem/wt_icache.sv b/src/cache_subsystem/wt_icache.sv
index b127eb6a..0b3cd9db 100644
--- a/src/cache_subsystem/wt_icache.sv
+++ b/src/cache_subsystem/wt_icache.sv
@@ -46,7 +46,8 @@ module wt_icache import ariane_pkg::*; import wt_cache_pkg::*; #(
input icache_rtrn_t mem_rtrn_i,
output logic mem_data_req_o,
input logic mem_data_ack_i,
- output icache_req_t mem_data_o
+ output icache_req_t mem_data_o,
+ input logic stall_req_i
);
// signals
diff --git a/src/verifier.sv b/src/verifier.sv
index f0875db2..80d20591 100644
--- a/src/verifier.sv
+++ b/src/verifier.sv
@@ -33,7 +33,8 @@ module verifier #(
// Bus accesses (I$ misses and memory instructions in the pipeline)
logic has_mem_access;
assign has_mem_access = if_has_mem_access_i | id_has_mem_access_i | is_has_mem_access_i | (~no_st_pending_commit_i);
- assign should_lock_icache_o = has_mem_access & icache_miss_i;
+ // assign should_lock_icache_o = has_mem_access & icache_miss_i;
+ assign should_lock_icache_o = has_mem_access;
// CO
logic [NR_COMMIT_PORTS-1:0][BITS_ENTRIES-1:0] commit_id_n, commit_id_q;
--
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