From 2f29415f8be41b39dcf593baff631d42a0cc2aa9 Mon Sep 17 00:00:00 2001
From: Jonathan <jonathan.certes@irit.fr>
Date: Tue, 14 Dec 2021 09:58:02 +0100
Subject: [PATCH] Exemple Hello World
---
README.md | 2 +
hello_world/Makefile | 43 +
hello_world/README | 71 +
hello_world/gdbinit.gdb | 56 +
hello_world/hw/Makefile | 25 +
hello_world/hw/connexions.v | 38 +
hello_world/hw/constraints_zybo.xdc | 146 +
hello_world/hw/design_0.pdf | 1493 ++
hello_world/hw/flipflop.v | 35 +
hello_world/hw/schematic.tcl | 94 +
hello_world/sdcard/Makefile | 8 +
hello_world/sdcard/boot.bif | 5 +
hello_world/sw/Makefile | 9 +
hello_world/sw/app/Makefile | 15 +
hello_world/sw/app/Rules.mk | 49 +
hello_world/sw/app/embeddedsw-master/README | 1 +
.../sw/app/embeddedsw-master/bspconfig.h | 12 +
.../sw/app/embeddedsw-master/xbasic_types.h | 287 +
.../sw/app/embeddedsw-master/xil_assert.h | 169 +
.../sw/app/embeddedsw-master/xil_cache.c | 1616 ++
.../sw/app/embeddedsw-master/xil_cache.h | 96 +
.../sw/app/embeddedsw-master/xil_cache_l.h | 75 +
.../sw/app/embeddedsw-master/xil_errata.h | 105 +
.../sw/app/embeddedsw-master/xil_exception.h | 377 +
hello_world/sw/app/embeddedsw-master/xil_io.h | 403 +
.../sw/app/embeddedsw-master/xil_mmu.c | 204 +
.../sw/app/embeddedsw-master/xil_mmu.h | 93 +
.../sw/app/embeddedsw-master/xil_printf.h | 52 +
.../sw/app/embeddedsw-master/xil_types.h | 197 +
hello_world/sw/app/embeddedsw-master/xl2cc.h | 146 +
.../sw/app/embeddedsw-master/xparameters.h | 1765 ++
.../sw/app/embeddedsw-master/xparameters_ps.h | 312 +
.../sw/app/embeddedsw-master/xpseudo_asm.h | 60 +
.../app/embeddedsw-master/xpseudo_asm_gcc.h | 232 +
.../sw/app/embeddedsw-master/xreg_cortexa9.h | 565 +
.../sw/app/embeddedsw-master/xstatus.h | 406 +
.../sw/app/embeddedsw-master/xuartps_hw.c | 154 +
.../sw/app/embeddedsw-master/xuartps_hw.h | 425 +
hello_world/sw/app/gpio.c | 165 +
hello_world/sw/app/gpio.h | 52 +
hello_world/sw/app/ldscript.ld | 94 +
hello_world/sw/app/main.c | 61 +
hello_world/sw/app/startup.s | 28 +
hello_world/sw/app/stdio.c | 175 +
hello_world/sw/fsbl/Makefile | 64 +
hello_world/sw/fsbl/Xilinx.spec | 2 +
hello_world/sw/fsbl/fsbl.h | 557 +
hello_world/sw/fsbl/fsbl_debug.h | 76 +
hello_world/sw/fsbl/fsbl_handoff.S | 215 +
hello_world/sw/fsbl/fsbl_hooks.c | 158 +
hello_world/sw/fsbl/fsbl_hooks.h | 75 +
hello_world/sw/fsbl/image_mover.c | 1346 ++
hello_world/sw/fsbl/image_mover.h | 155 +
hello_world/sw/fsbl/lscript.ld | 307 +
hello_world/sw/fsbl/main.c | 1541 ++
hello_world/sw/fsbl/md5.c | 484 +
hello_world/sw/fsbl/md5.h | 114 +
hello_world/sw/fsbl/nand.c | 289 +
hello_world/sw/fsbl/nand.h | 85 +
hello_world/sw/fsbl/nor.c | 138 +
hello_world/sw/fsbl/nor.h | 81 +
hello_world/sw/fsbl/pcap.c | 810 +
hello_world/sw/fsbl/pcap.h | 102 +
hello_world/sw/fsbl/qspi.c | 875 +
hello_world/sw/fsbl/qspi.h | 131 +
hello_world/sw/fsbl/rsa.c | 355 +
hello_world/sw/fsbl/rsa.h | 74 +
hello_world/sw/fsbl/sd.c | 185 +
hello_world/sw/fsbl/sd.h | 73 +
hello_world/sw/fsbl/zynq_fsbl_bsp/Makefile | 35 +
.../include/_profile_timer_hw.h | 306 +
.../ps7_cortexa9_0/include/bspconfig.h | 40 +
.../ps7_cortexa9_0/include/diskio.h | 79 +
.../zynq_fsbl_bsp/ps7_cortexa9_0/include/ff.h | 395 +
.../ps7_cortexa9_0/include/ffconf.h | 380 +
.../ps7_cortexa9_0/include/integer.h | 36 +
.../ps7_cortexa9_0/include/mblaze_nt_types.h | 48 +
.../ps7_cortexa9_0/include/profile.h | 125 +
.../ps7_cortexa9_0/include/sleep.h | 113 +
.../ps7_cortexa9_0/include/smc.h | 108 +
.../ps7_cortexa9_0/include/vectors.h | 82 +
.../ps7_cortexa9_0/include/xadcps.h | 587 +
.../ps7_cortexa9_0/include/xadcps_hw.h | 496 +
.../ps7_cortexa9_0/include/xbasic_types.h | 125 +
.../ps7_cortexa9_0/include/xbram.h | 221 +
.../ps7_cortexa9_0/include/xbram_hw.h | 403 +
.../ps7_cortexa9_0/include/xcoresightpsdcc.h | 72 +
.../ps7_cortexa9_0/include/xcpu_cortexa9.h | 45 +
.../ps7_cortexa9_0/include/xddrps.h | 60 +
.../ps7_cortexa9_0/include/xdebug.h | 40 +
.../ps7_cortexa9_0/include/xdevcfg.h | 397 +
.../ps7_cortexa9_0/include/xdevcfg_hw.h | 389 +
.../ps7_cortexa9_0/include/xdmaps.h | 347 +
.../ps7_cortexa9_0/include/xdmaps_hw.h | 287 +
.../ps7_cortexa9_0/include/xemacps.h | 849 +
.../ps7_cortexa9_0/include/xemacps_bd.h | 782 +
.../ps7_cortexa9_0/include/xemacps_bdring.h | 235 +
.../ps7_cortexa9_0/include/xemacps_hw.h | 666 +
.../ps7_cortexa9_0/include/xenv.h | 181 +
.../ps7_cortexa9_0/include/xenv_standalone.h | 362 +
.../ps7_cortexa9_0/include/xgpiops.h | 286 +
.../ps7_cortexa9_0/include/xgpiops_hw.h | 166 +
.../ps7_cortexa9_0/include/xil_assert.h | 189 +
.../ps7_cortexa9_0/include/xil_cache.h | 116 +
.../ps7_cortexa9_0/include/xil_cache_l.h | 95 +
.../include/xil_cache_vxworks.h | 87 +
.../ps7_cortexa9_0/include/xil_errata.h | 125 +
.../ps7_cortexa9_0/include/xil_exception.h | 283 +
.../ps7_cortexa9_0/include/xil_hal.h | 63 +
.../ps7_cortexa9_0/include/xil_io.h | 339 +
.../ps7_cortexa9_0/include/xil_macroback.h | 1054 ++
.../ps7_cortexa9_0/include/xil_mem.h | 66 +
.../include/xil_misc_psreset_api.h | 271 +
.../ps7_cortexa9_0/include/xil_mmu.h | 104 +
.../ps7_cortexa9_0/include/xil_printf.h | 48 +
.../ps7_cortexa9_0/include/xil_sleeptimer.h | 126 +
.../ps7_cortexa9_0/include/xil_testcache.h | 65 +
.../ps7_cortexa9_0/include/xil_testio.h | 88 +
.../ps7_cortexa9_0/include/xil_testmem.h | 152 +
.../ps7_cortexa9_0/include/xil_types.h | 217 +
.../ps7_cortexa9_0/include/xil_util.h | 112 +
.../ps7_cortexa9_0/include/xilrsa.h | 250 +
.../ps7_cortexa9_0/include/xl2cc.h | 166 +
.../ps7_cortexa9_0/include/xl2cc_counter.h | 108 +
.../ps7_cortexa9_0/include/xparameters.h | 617 +
.../ps7_cortexa9_0/include/xparameters_ps.h | 332 +
.../ps7_cortexa9_0/include/xplatform_info.h | 118 +
.../ps7_cortexa9_0/include/xpm_counter.h | 570 +
.../ps7_cortexa9_0/include/xpseudo_asm.h | 80 +
.../ps7_cortexa9_0/include/xpseudo_asm_gcc.h | 250 +
.../ps7_cortexa9_0/include/xqspips.h | 802 +
.../ps7_cortexa9_0/include/xqspips_hw.h | 419 +
.../ps7_cortexa9_0/include/xreg_cortexa9.h | 585 +
.../ps7_cortexa9_0/include/xscugic.h | 610 +
.../ps7_cortexa9_0/include/xscugic_hw.h | 718 +
.../ps7_cortexa9_0/include/xscutimer.h | 362 +
.../ps7_cortexa9_0/include/xscutimer_hw.h | 281 +
.../ps7_cortexa9_0/include/xscuwdt.h | 377 +
.../ps7_cortexa9_0/include/xscuwdt_hw.h | 176 +
.../ps7_cortexa9_0/include/xsdps.h | 282 +
.../ps7_cortexa9_0/include/xsdps_hw.h | 1317 ++
.../ps7_cortexa9_0/include/xstatus.h | 533 +
.../ps7_cortexa9_0/include/xtime_l.h | 102 +
.../ps7_cortexa9_0/include/xttcps.h | 536 +
.../ps7_cortexa9_0/include/xttcps_hw.h | 227 +
.../ps7_cortexa9_0/include/xuartps.h | 515 +
.../ps7_cortexa9_0/include/xuartps_hw.h | 445 +
.../ps7_cortexa9_0/include/xusbps.h | 1092 ++
.../ps7_cortexa9_0/include/xusbps_endpoint.h | 509 +
.../ps7_cortexa9_0/include/xusbps_hw.h | 520 +
.../libsrc/bram_v4_3/src/Makefile | 28 +
.../libsrc/bram_v4_3/src/xbram.c | 143 +
.../libsrc/bram_v4_3/src/xbram.h | 221 +
.../libsrc/bram_v4_3/src/xbram_g.c | 119 +
.../libsrc/bram_v4_3/src/xbram_hw.h | 403 +
.../libsrc/bram_v4_3/src/xbram_intr.c | 232 +
.../libsrc/bram_v4_3/src/xbram_selftest.c | 555 +
.../libsrc/bram_v4_3/src/xbram_sinit.c | 99 +
.../libsrc/coresightps_dcc_v1_6/src/Makefile | 40 +
.../src/xcoresightpsdcc.c | 184 +
.../src/xcoresightpsdcc.h | 72 +
.../libsrc/cpu_cortexa9_v2_8/src/Makefile | 25 +
.../cpu_cortexa9_v2_8/src/xcpu_cortexa9.h | 45 +
.../libsrc/ddrps_v1_0/src/Makefile | 40 +
.../libsrc/ddrps_v1_0/src/xddrps.h | 60 +
.../libsrc/devcfg_v3_5/src/Makefile | 40 +
.../libsrc/devcfg_v3_5/src/xdevcfg.c | 939 +
.../libsrc/devcfg_v3_5/src/xdevcfg.h | 397 +
.../libsrc/devcfg_v3_5/src/xdevcfg_g.c | 47 +
.../libsrc/devcfg_v3_5/src/xdevcfg_hw.c | 107 +
.../libsrc/devcfg_v3_5/src/xdevcfg_hw.h | 389 +
.../libsrc/devcfg_v3_5/src/xdevcfg_intr.c | 304 +
.../libsrc/devcfg_v3_5/src/xdevcfg_selftest.c | 108 +
.../libsrc/devcfg_v3_5/src/xdevcfg_sinit.c | 88 +
.../libsrc/dmaps_v2_5/src/Makefile | 41 +
.../libsrc/dmaps_v2_5/src/xdmaps.c | 1979 ++
.../libsrc/dmaps_v2_5/src/xdmaps.h | 347 +
.../libsrc/dmaps_v2_5/src/xdmaps_g.c | 51 +
.../libsrc/dmaps_v2_5/src/xdmaps_hw.c | 110 +
.../libsrc/dmaps_v2_5/src/xdmaps_hw.h | 287 +
.../libsrc/dmaps_v2_5/src/xdmaps_selftest.c | 104 +
.../libsrc/dmaps_v2_5/src/xdmaps_sinit.c | 98 +
.../libsrc/emacps_v3_10/src/Makefile | 40 +
.../libsrc/emacps_v3_10/src/xemacps.c | 487 +
.../libsrc/emacps_v3_10/src/xemacps.h | 849 +
.../libsrc/emacps_v3_10/src/xemacps_bd.h | 782 +
.../libsrc/emacps_v3_10/src/xemacps_bdring.c | 1096 ++
.../libsrc/emacps_v3_10/src/xemacps_bdring.h | 235 +
.../libsrc/emacps_v3_10/src/xemacps_control.c | 1153 ++
.../libsrc/emacps_v3_10/src/xemacps_g.c | 48 +
.../libsrc/emacps_v3_10/src/xemacps_hw.c | 117 +
.../libsrc/emacps_v3_10/src/xemacps_hw.h | 666 +
.../libsrc/emacps_v3_10/src/xemacps_intr.c | 262 +
.../libsrc/emacps_v3_10/src/xemacps_sinit.c | 91 +
.../libsrc/gpiops_v3_6/src/Makefile | 40 +
.../libsrc/gpiops_v3_6/src/xgpiops.c | 828 +
.../libsrc/gpiops_v3_6/src/xgpiops.h | 286 +
.../libsrc/gpiops_v3_6/src/xgpiops_g.c | 47 +
.../libsrc/gpiops_v3_6/src/xgpiops_hw.c | 260 +
.../libsrc/gpiops_v3_6/src/xgpiops_hw.h | 166 +
.../libsrc/gpiops_v3_6/src/xgpiops_intr.c | 825 +
.../libsrc/gpiops_v3_6/src/xgpiops_selftest.c | 132 +
.../libsrc/gpiops_v3_6/src/xgpiops_sinit.c | 95 +
.../libsrc/qspips_v3_6/src/Makefile | 40 +
.../libsrc/qspips_v3_6/src/xqspips.c | 1609 ++
.../libsrc/qspips_v3_6/src/xqspips.h | 802 +
.../libsrc/qspips_v3_6/src/xqspips_g.c | 49 +
.../libsrc/qspips_v3_6/src/xqspips_hw.c | 218 +
.../libsrc/qspips_v3_6/src/xqspips_hw.h | 419 +
.../libsrc/qspips_v3_6/src/xqspips_options.c | 424 +
.../libsrc/qspips_v3_6/src/xqspips_selftest.c | 133 +
.../libsrc/qspips_v3_6/src/xqspips_sinit.c | 94 +
.../libsrc/scugic_v4_1/src/Makefile | 40 +
.../libsrc/scugic_v4_1/src/xscugic.c | 1180 ++
.../libsrc/scugic_v4_1/src/xscugic.h | 610 +
.../libsrc/scugic_v4_1/src/xscugic_g.c | 49 +
.../libsrc/scugic_v4_1/src/xscugic_hw.c | 872 +
.../libsrc/scugic_v4_1/src/xscugic_hw.h | 718 +
.../libsrc/scugic_v4_1/src/xscugic_intr.c | 183 +
.../libsrc/scugic_v4_1/src/xscugic_selftest.c | 112 +
.../libsrc/scugic_v4_1/src/xscugic_sinit.c | 99 +
.../libsrc/scutimer_v2_1/src/Makefile | 40 +
.../libsrc/scutimer_v2_1/src/xscutimer.c | 280 +
.../libsrc/scutimer_v2_1/src/xscutimer.h | 362 +
.../libsrc/scutimer_v2_1/src/xscutimer_g.c | 47 +
.../libsrc/scutimer_v2_1/src/xscutimer_hw.h | 281 +
.../scutimer_v2_1/src/xscutimer_selftest.c | 133 +
.../scutimer_v2_1/src/xscutimer_sinit.c | 90 +
.../libsrc/scuwdt_v2_1/src/Makefile | 40 +
.../libsrc/scuwdt_v2_1/src/xscuwdt.c | 211 +
.../libsrc/scuwdt_v2_1/src/xscuwdt.h | 377 +
.../libsrc/scuwdt_v2_1/src/xscuwdt_g.c | 47 +
.../libsrc/scuwdt_v2_1/src/xscuwdt_hw.h | 176 +
.../libsrc/scuwdt_v2_1/src/xscuwdt_selftest.c | 125 +
.../libsrc/scuwdt_v2_1/src/xscuwdt_sinit.c | 90 +
.../libsrc/sdps_v3_8/src/Makefile | 40 +
.../libsrc/sdps_v3_8/src/xsdps.c | 2040 ++
.../libsrc/sdps_v3_8/src/xsdps.h | 282 +
.../libsrc/sdps_v3_8/src/xsdps_g.c | 54 +
.../libsrc/sdps_v3_8/src/xsdps_hw.h | 1317 ++
.../libsrc/sdps_v3_8/src/xsdps_options.c | 1600 ++
.../libsrc/sdps_v3_8/src/xsdps_sinit.c | 94 +
.../libsrc/standalone_v7_1/src/Makefile | 81 +
.../libsrc/standalone_v7_1/src/_exit.c | 38 +
.../libsrc/standalone_v7_1/src/_open.c | 48 +
.../libsrc/standalone_v7_1/src/_sbrk.c | 59 +
.../libsrc/standalone_v7_1/src/abort.c | 36 +
.../libsrc/standalone_v7_1/src/asm_vectors.S | 197 +
.../libsrc/standalone_v7_1/src/boot.S | 490 +
.../libsrc/standalone_v7_1/src/bspconfig.h | 40 +
.../libsrc/standalone_v7_1/src/changelog.txt | 618 +
.../libsrc/standalone_v7_1/src/close.c | 43 +
.../libsrc/standalone_v7_1/src/config.make | 3 +
.../standalone_v7_1/src/cpputest_time.c | 47 +
.../libsrc/standalone_v7_1/src/cpu_init.S | 74 +
.../libsrc/standalone_v7_1/src/errno.c | 45 +
.../libsrc/standalone_v7_1/src/fcntl.c | 40 +
.../libsrc/standalone_v7_1/src/fstat.c | 44 +
.../libsrc/standalone_v7_1/src/getpid.c | 45 +
.../libsrc/standalone_v7_1/src/inbyte.c | 14 +
.../libsrc/standalone_v7_1/src/isatty.c | 50 +
.../libsrc/standalone_v7_1/src/kill.c | 54 +
.../libsrc/standalone_v7_1/src/lseek.c | 55 +
.../libsrc/standalone_v7_1/src/open.c | 47 +
.../libsrc/standalone_v7_1/src/outbyte.c | 15 +
.../libsrc/standalone_v7_1/src/print.c | 36 +
.../standalone_v7_1/src/profile/Makefile | 72 +
.../src/profile/_profile_clean.c | 41 +
.../src/profile/_profile_init.c | 84 +
.../src/profile/_profile_timer_hw.c | 381 +
.../src/profile/_profile_timer_hw.h | 306 +
.../standalone_v7_1/src/profile/dummy.S | 58 +
.../src/profile/mblaze_nt_types.h | 48 +
.../standalone_v7_1/src/profile/profile.h | 125 +
.../standalone_v7_1/src/profile/profile_cg.c | 165 +
.../src/profile/profile_config.h | 50 +
.../src/profile/profile_hist.c | 65 +
.../src/profile/profile_mcount_arm.S | 39 +
.../src/profile/profile_mcount_mb.S | 63 +
.../src/profile/profile_mcount_ppc.S | 65 +
.../libsrc/standalone_v7_1/src/putnum.c | 59 +
.../libsrc/standalone_v7_1/src/read.c | 98 +
.../libsrc/standalone_v7_1/src/sbrk.c | 55 +
.../libsrc/standalone_v7_1/src/sleep.c | 86 +
.../libsrc/standalone_v7_1/src/sleep.h | 113 +
.../libsrc/standalone_v7_1/src/smc.h | 108 +
.../standalone_v7_1/src/translation_table.S | 224 +
.../libsrc/standalone_v7_1/src/unlink.c | 44 +
.../libsrc/standalone_v7_1/src/usleep.c | 101 +
.../libsrc/standalone_v7_1/src/vectors.c | 225 +
.../libsrc/standalone_v7_1/src/vectors.h | 82 +
.../libsrc/standalone_v7_1/src/write.c | 115 +
.../libsrc/standalone_v7_1/src/xbasic_types.h | 125 +
.../libsrc/standalone_v7_1/src/xdebug.h | 40 +
.../libsrc/standalone_v7_1/src/xenv.h | 181 +
.../standalone_v7_1/src/xenv_standalone.h | 362 +
.../libsrc/standalone_v7_1/src/xil-crt0.S | 153 +
.../libsrc/standalone_v7_1/src/xil_assert.c | 141 +
.../libsrc/standalone_v7_1/src/xil_assert.h | 189 +
.../libsrc/standalone_v7_1/src/xil_cache.c | 1635 ++
.../libsrc/standalone_v7_1/src/xil_cache.h | 116 +
.../libsrc/standalone_v7_1/src/xil_cache_l.h | 95 +
.../standalone_v7_1/src/xil_cache_vxworks.h | 87 +
.../libsrc/standalone_v7_1/src/xil_errata.h | 125 +
.../standalone_v7_1/src/xil_exception.c | 377 +
.../standalone_v7_1/src/xil_exception.h | 283 +
.../libsrc/standalone_v7_1/src/xil_hal.h | 63 +
.../libsrc/standalone_v7_1/src/xil_io.c | 96 +
.../libsrc/standalone_v7_1/src/xil_io.h | 339 +
.../standalone_v7_1/src/xil_macroback.h | 1054 ++
.../libsrc/standalone_v7_1/src/xil_mem.c | 83 +
.../libsrc/standalone_v7_1/src/xil_mem.h | 66 +
.../src/xil_misc_psreset_api.c | 518 +
.../src/xil_misc_psreset_api.h | 271 +
.../libsrc/standalone_v7_1/src/xil_mmu.c | 225 +
.../libsrc/standalone_v7_1/src/xil_mmu.h | 104 +
.../libsrc/standalone_v7_1/src/xil_printf.c | 442 +
.../libsrc/standalone_v7_1/src/xil_printf.h | 48 +
.../standalone_v7_1/src/xil_sleepcommon.c | 100 +
.../standalone_v7_1/src/xil_sleeptimer.c | 163 +
.../standalone_v7_1/src/xil_sleeptimer.h | 126 +
.../standalone_v7_1/src/xil_testcache.c | 365 +
.../standalone_v7_1/src/xil_testcache.h | 65 +
.../libsrc/standalone_v7_1/src/xil_testio.c | 293 +
.../libsrc/standalone_v7_1/src/xil_testio.h | 88 +
.../libsrc/standalone_v7_1/src/xil_testmem.c | 862 +
.../libsrc/standalone_v7_1/src/xil_testmem.h | 152 +
.../libsrc/standalone_v7_1/src/xil_types.h | 217 +
.../libsrc/standalone_v7_1/src/xil_util.c | 389 +
.../libsrc/standalone_v7_1/src/xil_util.h | 112 +
.../libsrc/standalone_v7_1/src/xl2cc.h | 166 +
.../standalone_v7_1/src/xl2cc_counter.c | 163 +
.../standalone_v7_1/src/xl2cc_counter.h | 108 +
.../standalone_v7_1/src/xparameters_ps.h | 332 +
.../standalone_v7_1/src/xplatform_info.c | 160 +
.../standalone_v7_1/src/xplatform_info.h | 118 +
.../libsrc/standalone_v7_1/src/xpm_counter.c | 291 +
.../libsrc/standalone_v7_1/src/xpm_counter.h | 570 +
.../libsrc/standalone_v7_1/src/xpseudo_asm.h | 80 +
.../standalone_v7_1/src/xpseudo_asm_gcc.h | 250 +
.../standalone_v7_1/src/xreg_cortexa9.h | 585 +
.../libsrc/standalone_v7_1/src/xstatus.h | 533 +
.../libsrc/standalone_v7_1/src/xtime_l.c | 116 +
.../libsrc/standalone_v7_1/src/xtime_l.h | 102 +
.../libsrc/ttcps_v3_10/src/Makefile | 40 +
.../libsrc/ttcps_v3_10/src/xttcps.c | 555 +
.../libsrc/ttcps_v3_10/src/xttcps.h | 536 +
.../libsrc/ttcps_v3_10/src/xttcps_g.c | 58 +
.../libsrc/ttcps_v3_10/src/xttcps_hw.h | 227 +
.../libsrc/ttcps_v3_10/src/xttcps_options.c | 212 +
.../libsrc/ttcps_v3_10/src/xttcps_selftest.c | 103 +
.../libsrc/ttcps_v3_10/src/xttcps_sinit.c | 92 +
.../libsrc/uartps_v3_8/src/Makefile | 40 +
.../libsrc/uartps_v3_8/src/xuartps.c | 640 +
.../libsrc/uartps_v3_8/src/xuartps.h | 515 +
.../libsrc/uartps_v3_8/src/xuartps_g.c | 49 +
.../libsrc/uartps_v3_8/src/xuartps_hw.c | 174 +
.../libsrc/uartps_v3_8/src/xuartps_hw.h | 445 +
.../libsrc/uartps_v3_8/src/xuartps_intr.c | 445 +
.../libsrc/uartps_v3_8/src/xuartps_options.c | 758 +
.../libsrc/uartps_v3_8/src/xuartps_selftest.c | 160 +
.../libsrc/uartps_v3_8/src/xuartps_sinit.c | 93 +
.../libsrc/usbps_v2_4/src/Makefile | 41 +
.../libsrc/usbps_v2_4/src/xusbps.c | 358 +
.../libsrc/usbps_v2_4/src/xusbps.h | 1092 ++
.../libsrc/usbps_v2_4/src/xusbps_endpoint.c | 1448 ++
.../libsrc/usbps_v2_4/src/xusbps_endpoint.h | 509 +
.../libsrc/usbps_v2_4/src/xusbps_g.c | 47 +
.../libsrc/usbps_v2_4/src/xusbps_hw.c | 116 +
.../libsrc/usbps_v2_4/src/xusbps_hw.h | 520 +
.../libsrc/usbps_v2_4/src/xusbps_intr.c | 466 +
.../libsrc/usbps_v2_4/src/xusbps_sinit.c | 93 +
.../libsrc/xadcps_v2_3/src/Makefile | 40 +
.../libsrc/xadcps_v2_3/src/xadcps.c | 1828 ++
.../libsrc/xadcps_v2_3/src/xadcps.h | 587 +
.../libsrc/xadcps_v2_3/src/xadcps_g.c | 47 +
.../libsrc/xadcps_v2_3/src/xadcps_hw.h | 496 +
.../libsrc/xadcps_v2_3/src/xadcps_intr.c | 244 +
.../libsrc/xadcps_v2_3/src/xadcps_selftest.c | 135 +
.../libsrc/xadcps_v2_3/src/xadcps_sinit.c | 97 +
.../libsrc/xilffs_v4_2/src/Makefile | 81 +
.../libsrc/xilffs_v4_2/src/diskio.c | 523 +
.../libsrc/xilffs_v4_2/src/ff.c | 6564 +++++++
.../libsrc/xilffs_v4_2/src/ffsystem.c | 171 +
.../libsrc/xilffs_v4_2/src/ffunicode.c | 15597 ++++++++++++++++
.../libsrc/xilffs_v4_2/src/include/diskio.h | 79 +
.../libsrc/xilffs_v4_2/src/include/ff.h | 395 +
.../libsrc/xilffs_v4_2/src/include/ffconf.h | 380 +
.../libsrc/xilffs_v4_2/src/include/integer.h | 36 +
.../libsrc/xilrsa_v1_5/src/Makefile | 50 +
.../libsrc/xilrsa_v1_5/src/include/xilrsa.h | 250 +
.../libsrc/xilrsa_v1_5/src/librsa.a | Bin 0 -> 12530 bytes
hello_world/sw/fsbl/zynq_fsbl_bsp/system.mss | 269 +
openocd_zynq.tcl | 25 +
vivadoMakefile.tcl | 258 +
395 files changed, 132333 insertions(+)
create mode 100644 hello_world/Makefile
create mode 100644 hello_world/README
create mode 100644 hello_world/gdbinit.gdb
create mode 100644 hello_world/hw/Makefile
create mode 100644 hello_world/hw/connexions.v
create mode 100644 hello_world/hw/constraints_zybo.xdc
create mode 100644 hello_world/hw/design_0.pdf
create mode 100644 hello_world/hw/flipflop.v
create mode 100644 hello_world/hw/schematic.tcl
create mode 100644 hello_world/sdcard/Makefile
create mode 100644 hello_world/sdcard/boot.bif
create mode 100644 hello_world/sw/Makefile
create mode 100644 hello_world/sw/app/Makefile
create mode 100644 hello_world/sw/app/Rules.mk
create mode 100644 hello_world/sw/app/embeddedsw-master/README
create mode 100644 hello_world/sw/app/embeddedsw-master/bspconfig.h
create mode 100644 hello_world/sw/app/embeddedsw-master/xbasic_types.h
create mode 100644 hello_world/sw/app/embeddedsw-master/xil_assert.h
create mode 100644 hello_world/sw/app/embeddedsw-master/xil_cache.c
create mode 100644 hello_world/sw/app/embeddedsw-master/xil_cache.h
create mode 100644 hello_world/sw/app/embeddedsw-master/xil_cache_l.h
create mode 100644 hello_world/sw/app/embeddedsw-master/xil_errata.h
create mode 100644 hello_world/sw/app/embeddedsw-master/xil_exception.h
create mode 100644 hello_world/sw/app/embeddedsw-master/xil_io.h
create mode 100644 hello_world/sw/app/embeddedsw-master/xil_mmu.c
create mode 100644 hello_world/sw/app/embeddedsw-master/xil_mmu.h
create mode 100644 hello_world/sw/app/embeddedsw-master/xil_printf.h
create mode 100644 hello_world/sw/app/embeddedsw-master/xil_types.h
create mode 100644 hello_world/sw/app/embeddedsw-master/xl2cc.h
create mode 100644 hello_world/sw/app/embeddedsw-master/xparameters.h
create mode 100644 hello_world/sw/app/embeddedsw-master/xparameters_ps.h
create mode 100644 hello_world/sw/app/embeddedsw-master/xpseudo_asm.h
create mode 100644 hello_world/sw/app/embeddedsw-master/xpseudo_asm_gcc.h
create mode 100644 hello_world/sw/app/embeddedsw-master/xreg_cortexa9.h
create mode 100644 hello_world/sw/app/embeddedsw-master/xstatus.h
create mode 100644 hello_world/sw/app/embeddedsw-master/xuartps_hw.c
create mode 100644 hello_world/sw/app/embeddedsw-master/xuartps_hw.h
create mode 100644 hello_world/sw/app/gpio.c
create mode 100644 hello_world/sw/app/gpio.h
create mode 100644 hello_world/sw/app/ldscript.ld
create mode 100644 hello_world/sw/app/main.c
create mode 100644 hello_world/sw/app/startup.s
create mode 100644 hello_world/sw/app/stdio.c
create mode 100644 hello_world/sw/fsbl/Makefile
create mode 100644 hello_world/sw/fsbl/Xilinx.spec
create mode 100644 hello_world/sw/fsbl/fsbl.h
create mode 100644 hello_world/sw/fsbl/fsbl_debug.h
create mode 100644 hello_world/sw/fsbl/fsbl_handoff.S
create mode 100644 hello_world/sw/fsbl/fsbl_hooks.c
create mode 100644 hello_world/sw/fsbl/fsbl_hooks.h
create mode 100644 hello_world/sw/fsbl/image_mover.c
create mode 100644 hello_world/sw/fsbl/image_mover.h
create mode 100644 hello_world/sw/fsbl/lscript.ld
create mode 100644 hello_world/sw/fsbl/main.c
create mode 100644 hello_world/sw/fsbl/md5.c
create mode 100644 hello_world/sw/fsbl/md5.h
create mode 100644 hello_world/sw/fsbl/nand.c
create mode 100644 hello_world/sw/fsbl/nand.h
create mode 100644 hello_world/sw/fsbl/nor.c
create mode 100644 hello_world/sw/fsbl/nor.h
create mode 100644 hello_world/sw/fsbl/pcap.c
create mode 100644 hello_world/sw/fsbl/pcap.h
create mode 100644 hello_world/sw/fsbl/qspi.c
create mode 100644 hello_world/sw/fsbl/qspi.h
create mode 100644 hello_world/sw/fsbl/rsa.c
create mode 100644 hello_world/sw/fsbl/rsa.h
create mode 100644 hello_world/sw/fsbl/sd.c
create mode 100644 hello_world/sw/fsbl/sd.h
create mode 100644 hello_world/sw/fsbl/zynq_fsbl_bsp/Makefile
create mode 100644 hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/include/_profile_timer_hw.h
create mode 100644 hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/include/bspconfig.h
create mode 100644 hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/include/diskio.h
create mode 100644 hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/include/ff.h
create mode 100644 hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/include/ffconf.h
create mode 100644 hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/include/integer.h
create mode 100644 hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/include/mblaze_nt_types.h
create mode 100644 hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/include/profile.h
create mode 100644 hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/include/sleep.h
create mode 100644 hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/include/smc.h
create mode 100644 hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/include/vectors.h
create mode 100644 hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/include/xadcps.h
create mode 100644 hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/include/xadcps_hw.h
create mode 100644 hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/include/xbasic_types.h
create mode 100644 hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/include/xbram.h
create mode 100644 hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/include/xbram_hw.h
create mode 100644 hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/include/xcoresightpsdcc.h
create mode 100644 hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/include/xcpu_cortexa9.h
create mode 100644 hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/include/xddrps.h
create mode 100644 hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/include/xdebug.h
create mode 100644 hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/include/xdevcfg.h
create mode 100644 hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/include/xdevcfg_hw.h
create mode 100644 hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/include/xdmaps.h
create mode 100644 hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/include/xdmaps_hw.h
create mode 100644 hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/include/xemacps.h
create mode 100644 hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/include/xemacps_bd.h
create mode 100644 hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/include/xemacps_bdring.h
create mode 100644 hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/include/xemacps_hw.h
create mode 100644 hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/include/xenv.h
create mode 100644 hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/include/xenv_standalone.h
create mode 100644 hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/include/xgpiops.h
create mode 100644 hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/include/xgpiops_hw.h
create mode 100644 hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/include/xil_assert.h
create mode 100644 hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/include/xil_cache.h
create mode 100644 hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/include/xil_cache_l.h
create mode 100644 hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/include/xil_cache_vxworks.h
create mode 100644 hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/include/xil_errata.h
create mode 100644 hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/include/xil_exception.h
create mode 100644 hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/include/xil_hal.h
create mode 100644 hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/include/xil_io.h
create mode 100644 hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/include/xil_macroback.h
create mode 100644 hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/include/xil_mem.h
create mode 100644 hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/include/xil_misc_psreset_api.h
create mode 100644 hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/include/xil_mmu.h
create mode 100644 hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/include/xil_printf.h
create mode 100644 hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/include/xil_sleeptimer.h
create mode 100644 hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/include/xil_testcache.h
create mode 100644 hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/include/xil_testio.h
create mode 100644 hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/include/xil_testmem.h
create mode 100644 hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/include/xil_types.h
create mode 100644 hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/include/xil_util.h
create mode 100644 hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/include/xilrsa.h
create mode 100644 hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/include/xl2cc.h
create mode 100644 hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/include/xl2cc_counter.h
create mode 100644 hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/include/xparameters.h
create mode 100644 hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/include/xparameters_ps.h
create mode 100644 hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/include/xplatform_info.h
create mode 100644 hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/include/xpm_counter.h
create mode 100644 hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/include/xpseudo_asm.h
create mode 100644 hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/include/xpseudo_asm_gcc.h
create mode 100644 hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/include/xqspips.h
create mode 100644 hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/include/xqspips_hw.h
create mode 100644 hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/include/xreg_cortexa9.h
create mode 100644 hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/include/xscugic.h
create mode 100644 hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/include/xscugic_hw.h
create mode 100644 hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/include/xscutimer.h
create mode 100644 hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/include/xscutimer_hw.h
create mode 100644 hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/include/xscuwdt.h
create mode 100644 hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/include/xscuwdt_hw.h
create mode 100644 hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/include/xsdps.h
create mode 100644 hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/include/xsdps_hw.h
create mode 100644 hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/include/xstatus.h
create mode 100644 hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/include/xtime_l.h
create mode 100644 hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/include/xttcps.h
create mode 100644 hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/include/xttcps_hw.h
create mode 100644 hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/include/xuartps.h
create mode 100644 hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/include/xuartps_hw.h
create mode 100644 hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/include/xusbps.h
create mode 100644 hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/include/xusbps_endpoint.h
create mode 100644 hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/include/xusbps_hw.h
create mode 100644 hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/bram_v4_3/src/Makefile
create mode 100644 hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/bram_v4_3/src/xbram.c
create mode 100644 hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/bram_v4_3/src/xbram.h
create mode 100644 hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/bram_v4_3/src/xbram_g.c
create mode 100644 hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/bram_v4_3/src/xbram_hw.h
create mode 100644 hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/bram_v4_3/src/xbram_intr.c
create mode 100644 hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/bram_v4_3/src/xbram_selftest.c
create mode 100644 hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/bram_v4_3/src/xbram_sinit.c
create mode 100644 hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/coresightps_dcc_v1_6/src/Makefile
create mode 100644 hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/coresightps_dcc_v1_6/src/xcoresightpsdcc.c
create mode 100644 hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/coresightps_dcc_v1_6/src/xcoresightpsdcc.h
create mode 100644 hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/cpu_cortexa9_v2_8/src/Makefile
create mode 100644 hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/cpu_cortexa9_v2_8/src/xcpu_cortexa9.h
create mode 100644 hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/ddrps_v1_0/src/Makefile
create mode 100644 hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/ddrps_v1_0/src/xddrps.h
create mode 100644 hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/devcfg_v3_5/src/Makefile
create mode 100644 hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/devcfg_v3_5/src/xdevcfg.c
create mode 100644 hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/devcfg_v3_5/src/xdevcfg.h
create mode 100644 hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/devcfg_v3_5/src/xdevcfg_g.c
create mode 100644 hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/devcfg_v3_5/src/xdevcfg_hw.c
create mode 100644 hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/devcfg_v3_5/src/xdevcfg_hw.h
create mode 100644 hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/devcfg_v3_5/src/xdevcfg_intr.c
create mode 100644 hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/devcfg_v3_5/src/xdevcfg_selftest.c
create mode 100644 hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/devcfg_v3_5/src/xdevcfg_sinit.c
create mode 100644 hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/dmaps_v2_5/src/Makefile
create mode 100644 hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/dmaps_v2_5/src/xdmaps.c
create mode 100644 hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/dmaps_v2_5/src/xdmaps.h
create mode 100644 hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/dmaps_v2_5/src/xdmaps_g.c
create mode 100644 hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/dmaps_v2_5/src/xdmaps_hw.c
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create mode 100644 hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v7_1/src/xil_testmem.h
create mode 100644 hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v7_1/src/xil_types.h
create mode 100644 hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v7_1/src/xil_util.c
create mode 100644 hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v7_1/src/xil_util.h
create mode 100644 hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v7_1/src/xl2cc.h
create mode 100644 hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v7_1/src/xl2cc_counter.c
create mode 100644 hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v7_1/src/xl2cc_counter.h
create mode 100644 hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v7_1/src/xparameters_ps.h
create mode 100644 hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v7_1/src/xplatform_info.c
create mode 100644 hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v7_1/src/xplatform_info.h
create mode 100644 hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v7_1/src/xpm_counter.c
create mode 100644 hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v7_1/src/xpm_counter.h
create mode 100644 hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v7_1/src/xpseudo_asm.h
create mode 100644 hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v7_1/src/xpseudo_asm_gcc.h
create mode 100644 hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v7_1/src/xreg_cortexa9.h
create mode 100644 hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v7_1/src/xstatus.h
create mode 100644 hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v7_1/src/xtime_l.c
create mode 100644 hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v7_1/src/xtime_l.h
create mode 100644 hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/ttcps_v3_10/src/Makefile
create mode 100644 hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/ttcps_v3_10/src/xttcps.c
create mode 100644 hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/ttcps_v3_10/src/xttcps.h
create mode 100644 hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/ttcps_v3_10/src/xttcps_g.c
create mode 100644 hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/ttcps_v3_10/src/xttcps_hw.h
create mode 100644 hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/ttcps_v3_10/src/xttcps_options.c
create mode 100644 hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/ttcps_v3_10/src/xttcps_selftest.c
create mode 100644 hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/ttcps_v3_10/src/xttcps_sinit.c
create mode 100644 hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/uartps_v3_8/src/Makefile
create mode 100644 hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/uartps_v3_8/src/xuartps.c
create mode 100644 hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/uartps_v3_8/src/xuartps.h
create mode 100644 hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/uartps_v3_8/src/xuartps_g.c
create mode 100644 hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/uartps_v3_8/src/xuartps_hw.c
create mode 100644 hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/uartps_v3_8/src/xuartps_hw.h
create mode 100644 hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/uartps_v3_8/src/xuartps_intr.c
create mode 100644 hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/uartps_v3_8/src/xuartps_options.c
create mode 100644 hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/uartps_v3_8/src/xuartps_selftest.c
create mode 100644 hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/uartps_v3_8/src/xuartps_sinit.c
create mode 100644 hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/usbps_v2_4/src/Makefile
create mode 100644 hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/usbps_v2_4/src/xusbps.c
create mode 100644 hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/usbps_v2_4/src/xusbps.h
create mode 100644 hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/usbps_v2_4/src/xusbps_endpoint.c
create mode 100644 hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/usbps_v2_4/src/xusbps_endpoint.h
create mode 100644 hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/usbps_v2_4/src/xusbps_g.c
create mode 100644 hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/usbps_v2_4/src/xusbps_hw.c
create mode 100644 hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/usbps_v2_4/src/xusbps_hw.h
create mode 100644 hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/usbps_v2_4/src/xusbps_intr.c
create mode 100644 hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/usbps_v2_4/src/xusbps_sinit.c
create mode 100644 hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/xadcps_v2_3/src/Makefile
create mode 100644 hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/xadcps_v2_3/src/xadcps.c
create mode 100644 hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/xadcps_v2_3/src/xadcps.h
create mode 100644 hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/xadcps_v2_3/src/xadcps_g.c
create mode 100644 hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/xadcps_v2_3/src/xadcps_hw.h
create mode 100644 hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/xadcps_v2_3/src/xadcps_intr.c
create mode 100644 hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/xadcps_v2_3/src/xadcps_selftest.c
create mode 100644 hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/xadcps_v2_3/src/xadcps_sinit.c
create mode 100644 hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/xilffs_v4_2/src/Makefile
create mode 100644 hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/xilffs_v4_2/src/diskio.c
create mode 100644 hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/xilffs_v4_2/src/ff.c
create mode 100644 hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/xilffs_v4_2/src/ffsystem.c
create mode 100644 hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/xilffs_v4_2/src/ffunicode.c
create mode 100644 hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/xilffs_v4_2/src/include/diskio.h
create mode 100644 hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/xilffs_v4_2/src/include/ff.h
create mode 100644 hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/xilffs_v4_2/src/include/ffconf.h
create mode 100644 hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/xilffs_v4_2/src/include/integer.h
create mode 100644 hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/xilrsa_v1_5/src/Makefile
create mode 100644 hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/xilrsa_v1_5/src/include/xilrsa.h
create mode 100644 hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/xilrsa_v1_5/src/librsa.a
create mode 100644 hello_world/sw/fsbl/zynq_fsbl_bsp/system.mss
create mode 100644 openocd_zynq.tcl
create mode 100755 vivadoMakefile.tcl
diff --git a/README.md b/README.md
index 48a28e8..12eddf5 100644
--- a/README.md
+++ b/README.md
@@ -1,2 +1,4 @@
# Co-design avec Zybo
+Contient des exemples de co-design Hardware/Software fonctionnant sur la board
+de développement Digilent Zybo.
diff --git a/hello_world/Makefile b/hello_world/Makefile
new file mode 100644
index 0000000..b203140
--- /dev/null
+++ b/hello_world/Makefile
@@ -0,0 +1,43 @@
+
+# zybo:
+OCD = ../openocd_zynq.tcl
+
+#===============================================================================
+
+all: openocd
+
+
+openocd: ${OCD} hw/design_0_wrapper.bit gdbinit.gdb
+ make -C sw
+ # TO BE RUN IN AN OTHER TERMINAL:
+ # gdb-multiarch -ex "set architecture armv7" -ex "target extended-remote localhost:3333" --command="gdbinit.gdb"
+ #
+ /usr/bin/openocd -f $<
+
+
+qemu: gdbinit.gdb
+ make -C sw
+ # TO BE RUN IN AN OTHER TERMINAL:
+ # gdb-multiarch -ex "target remote localhost:1234" --command="gdbinit.gdb"
+ #
+ qemu-system-arm -machine xilinx-zynq-a9 -cpu cortex-a9 -m 1132M -nographic \
+ -serial null -serial mon:stdio -gdb tcp::1234
+
+
+sdcard: hw/design_0_wrapper.bit
+ make -C sw
+ make -C sdcard
+ # copy file sdcard/boot.bin on the SD card and boot the Zybo ; connect to the
+ # board with:
+ # pyserial-miniterm /dev/ttyUSB1 115200
+
+
+hw/design_0_wrapper.bit:
+ make -C hw
+
+#===============================================================================
+
+clean:
+ make -C sw clean
+ make -C hw clean
+ make -C sdcard clean
diff --git a/hello_world/README b/hello_world/README
new file mode 100644
index 0000000..6d83d20
--- /dev/null
+++ b/hello_world/README
@@ -0,0 +1,71 @@
+
+Hello World sur la Zybo.
+
+Permet de tester le printf() sur l'UART.
+Pour le visualiser, il faut démarrer sur la carte SD et se connecter avec la
+commande:
+$ pyserial-miniterm /dev/ttyUSB1 115200
+
+
+Permet de synthétiser le schéma représenté sur le document hw/design_0.pdf:
+
+1) Software + GPIO:
+- La LED_0 est allumée.
+- Un appui sur le bouton BTN_0 est vu par le Zynq sur le GPIO configuré en
+ entrée: EMIO[1].
+- Dans le main(), dans une boucle infinie, la valeur lue sur le GPIO EMIO[1] est
+ inversée puis appliquée sur GPIO configuré en sortie: EMIO[0].
+- EMIO[0] est connecté à la LED_0 qui s'éteint.
+
+2) Hardware:
+- La LED_1 est éteinte.
+- Un appui sur le bouton BTN_1 est connecté à une flip-flop et recopié sur la
+ LED_1 à chaque front montant de l'horloge.
+- L'horloge est fournie par le Zynq.
+
+
+3 modes de fonctionnement:
+
+1) Via une carte SD:
+ - faire "make sdcard" et copier le fichier sdcard/boot.bin sur la carte SD
+ - placer le jumper sur la board pour sélectionner le démarrage sur la carte SD
+ - démarrer la board
+ - se connecter à l'UART avec "pyserial-miniterm /dev/ttyUSB1 115200"
+ - reset de la board pour voir le printf("Hello World").
+
+2) Via openOCD:
+ (note: printf() ne fonctionne pas car openOCD utilise la liaison série pour
+ communiquer avec la board)
+ - placer le jumper sur la board pour sélectionner le démarrage sur le JTAG
+ - démarrer la board
+ - faire "make openocd"
+ - lancer gdb dans un autre terminal avec la commande:
+ $ gdb-multiarch -ex "set architecture armv7" \
+ -ex "target extended-remote localhost:3333" \
+ --command="gdbinit.gdb"
+ - dans gdb, faire "continue" pour sortir du breakpoint au niveau du main()
+
+3) Via QEMU (logiciel seulement):
+ (note: printf() ne fonctionne pas car le FSBL s'arrête avant d'avoir configuré
+ l'UART ; il est possible de re-configurer les registres a-posteriori)
+ - faire "make qemu"
+ - lancer gdb dans un autre terminal avec la commande:
+ $ gdb-multiarch -ex "target remote localhost:1234" --command="gdbinit.gdb"
+ - dans gdb, attendre le timeout du FSBL qui n'arrive pas à démarrer les
+ périphériques.
+
+
+Testé avec:
+- Vivado v2019.2 (64-bit)
+- arm-none-eabi-gcc (15:8-2019-q3-1+b1) 8.3.1 20190703 (release)
+- GNU ld (2.35.2-2+14+b2) 2.35.2
+- Xilinx Bootgen v2019.2
+- QEMU emulator version 5.2.0
+- Open On-Chip Debugger 0.11.0-rc2
+- GNU gdb (Debian 10.1-1.7) 10.1.90.20210103-git
+- python3-serial 3.5~b0-1
+
+
+TODO:
+- Faire fonctionner l'UART à la fois via la carte SD et via QEMU.
+
diff --git a/hello_world/gdbinit.gdb b/hello_world/gdbinit.gdb
new file mode 100644
index 0000000..01529df
--- /dev/null
+++ b/hello_world/gdbinit.gdb
@@ -0,0 +1,56 @@
+
+#
+# Copyright (C) 2021 Jonathan Certes
+#
+# This program is free software: you can redistribute it and/or modify it under
+# the terms of the GNU General Public License as published by the Free Software
+# Foundation, either version 3 of the License, or (at your option) any later
+# version.
+#
+# This program is distributed in the hope that it will be useful, but WITHOUT
+# ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS
+# FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License along with
+# this program. If not, see <http://www.gnu.org/licenses/>.
+#
+
+set architecture armv7
+
+monitor reset halt
+monitor pld load 0 ./hw/design_0_wrapper.bit
+monitor gdb_sync
+
+# now controlling gdb:
+file sw/fsbl/main.elf
+load sw/fsbl/main.elf
+break _boot
+jump _boot
+#layout regs
+
+# add a breakpoint in each entry of the exception vectors table:
+break *0x00
+break *0x04
+break *0x08
+break *0x0c
+break *0x10
+break *0x14
+break *0x18
+break *0x1c
+
+# run until we reach Loop (ps7_init terminated properly) or FsblHookFallback (an
+# error occurred, case of qemu since all devices cannot be initialized):
+break Loop
+break FsblHookFallback
+continue
+continue
+
+# load the application:
+file sw/app/main.elf
+load sw/app/main.elf
+break _start
+jump _start
+
+break main
+continue
+
diff --git a/hello_world/hw/Makefile b/hello_world/hw/Makefile
new file mode 100644
index 0000000..6ebea0d
--- /dev/null
+++ b/hello_world/hw/Makefile
@@ -0,0 +1,25 @@
+
+HDL = connexions.v flipflop.v
+SCHEM = schematic.tcl
+TOP = design_0_wrapper
+
+# zybo:
+FPGA = xc7z010clg400-1
+XDC = constraints_zybo.xdc
+
+#===============================================================================
+
+all : ${TOP}.bit ps7_init.h ps7_init.c
+
+${TOP}.bit ps7_init.h ps7_init.c : ${HDL} ${SCHEM} ${XDC}
+ ../../vivadoMakefile.tcl \
+ --hdl ${HDL} --schem ${SCHEM} \
+ --fpga ${FPGA} --constr ${XDC} --top ${TOP}
+ # find ps7_init files:
+ test -L ps7_init.c || ln -s "$$(find . -name ps7_init.c)"
+ test -L ps7_init.h || ln -s "$$(find . -name ps7_init.h)"
+
+clean :
+ $(RM) -r ./vivado.workspace/ ./NA/
+ $(RM) vivado_*.backup.log vivado.log vivado_*.backup.jou vivado.jou
+ $(RM) ${TOP}.bit ps7_init.h ps7_init.c
diff --git a/hello_world/hw/connexions.v b/hello_world/hw/connexions.v
new file mode 100644
index 0000000..b84133a
--- /dev/null
+++ b/hello_world/hw/connexions.v
@@ -0,0 +1,38 @@
+
+/*
+ Copyright (C) 2021 Jonathan Certes
+
+ This program is free software: you can redistribute it and/or modify it under
+ the terms of the GNU General Public License as published by the Free Software
+ Foundation, either version 3 of the License, or (at your option) any later
+ version.
+
+ This program is distributed in the hope that it will be useful, but WITHOUT
+ ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS
+ FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details.
+
+ You should have received a copy of the GNU General Public License along with
+ this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+/**
+ * \brief
+ * Establishes the connexions between Z7 EMIO GPIO and external ports.
+ *
+ * \details
+ * - <tt> led_0 </tt> is connected to <tt> gpio_o[0] </tt>
+ * - <tt> gpio_i[1] </tt> is connected to <tt> btn_0 </tt>
+ */
+module connexions
+(
+ input [1:0] gpio_o,
+ output [1:0] gpio_i,
+
+ input btn_0,
+ output led_0
+);
+
+ assign led_0 = gpio_o[0];
+ assign gpio_i[1] = btn_0;
+
+endmodule
diff --git a/hello_world/hw/constraints_zybo.xdc b/hello_world/hw/constraints_zybo.xdc
new file mode 100644
index 0000000..830ae2b
--- /dev/null
+++ b/hello_world/hw/constraints_zybo.xdc
@@ -0,0 +1,146 @@
+## This file is a general .xdc for the ZYBO Rev B board
+## To use it in a project:
+## - uncomment the lines corresponding to used pins
+## - rename the used signals according to the project
+
+
+##Clock signal
+#set_property -dict { PACKAGE_PIN L16 IOSTANDARD LVCMOS33 } [get_ports { clk }]; #IO_L11P_T1_SRCC_35 Sch=sysclk
+#create_clock -add -name sys_clk_pin -period 10.00 -waveform {0 5} [get_ports { clk }]; #set
+
+
+##Switches
+#set_property -dict { PACKAGE_PIN G15 IOSTANDARD LVCMOS33 } [get_ports { sw_0 }]; #IO_L19N_T3_VREF_35 Sch=SW0
+#set_property -dict { PACKAGE_PIN P15 IOSTANDARD LVCMOS33 } [get_ports { sw_1 }]; #IO_L24P_T3_34 Sch=SW1
+#set_property -dict { PACKAGE_PIN W13 IOSTANDARD LVCMOS33 } [get_ports { sw_2 }]; #IO_L4N_T0_34 Sch=SW2
+#set_property -dict { PACKAGE_PIN T16 IOSTANDARD LVCMOS33 } [get_ports { sw_3 }]; #IO_L9P_T1_DQS_34 Sch=SW3
+
+
+##Buttons
+set_property -dict { PACKAGE_PIN R18 IOSTANDARD LVCMOS33 } [get_ports { btn_0 }]; #IO_L20N_T3_34 Sch=BTN0
+set_property -dict { PACKAGE_PIN P16 IOSTANDARD LVCMOS33 } [get_ports { btn_1 }]; #IO_L24N_T3_34 Sch=BTN1
+#set_property -dict { PACKAGE_PIN V16 IOSTANDARD LVCMOS33 } [get_ports { btn_2 }]; #IO_L18P_T2_34 Sch=BTN2
+#set_property -dict { PACKAGE_PIN Y16 IOSTANDARD LVCMOS33 } [get_ports { btn_3 }]; #IO_L7P_T1_34 Sch=BTN3
+
+
+##LEDs
+set_property -dict { PACKAGE_PIN M14 IOSTANDARD LVCMOS33 } [get_ports { led_0 }]; #IO_L23P_T3_35 Sch=LED0
+set_property -dict { PACKAGE_PIN M15 IOSTANDARD LVCMOS33 } [get_ports { led_1 }]; #IO_L23N_T3_35 Sch=LED1
+#set_property -dict { PACKAGE_PIN G14 IOSTANDARD LVCMOS33 } [get_ports { led_2 }]; #IO_0_35 Sch=LED2
+#set_property -dict { PACKAGE_PIN D18 IOSTANDARD LVCMOS33 } [get_ports { led_3 }]; #IO_L3N_T0_DQS_AD1N_35 Sch=LED3
+
+
+##I2S Audio Codec
+#set_property -dict { PACKAGE_PIN K18 IOSTANDARD LVCMOS33 } [get_ports ac_bclk]; #IO_L12N_T1_MRCC_35 Sch=AC_BCLK
+#set_property -dict { PACKAGE_PIN T19 IOSTANDARD LVCMOS33 } [get_ports ac_mclk]; #IO_25_34 Sch=AC_MCLK
+#set_property -dict { PACKAGE_PIN P18 IOSTANDARD LVCMOS33 } [get_ports ac_muten]; #IO_L23N_T3_34 Sch=AC_MUTEN
+#set_property -dict { PACKAGE_PIN M17 IOSTANDARD LVCMOS33 } [get_ports ac_pbdat]; #IO_L8P_T1_AD10P_35 Sch=AC_PBDAT
+#set_property -dict { PACKAGE_PIN L17 IOSTANDARD LVCMOS33 } [get_ports ac_pblrc]; #IO_L11N_T1_SRCC_35 Sch=AC_PBLRC
+#set_property -dict { PACKAGE_PIN K17 IOSTANDARD LVCMOS33 } [get_ports ac_recdat]; #IO_L12P_T1_MRCC_35 Sch=AC_RECDAT
+#set_property -dict { PACKAGE_PIN M18 IOSTANDARD LVCMOS33 } [get_ports ac_reclrc]; #IO_L8N_T1_AD10N_35 Sch=AC_RECLRC
+
+
+##Audio Codec/external EEPROM IIC bus
+#set_property -dict { PACKAGE_PIN N18 IOSTANDARD LVCMOS33 } [get_ports ac_scl]; #IO_L13P_T2_MRCC_34 Sch=AC_SCL
+#set_property -dict { PACKAGE_PIN N17 IOSTANDARD LVCMOS33 } [get_ports ac_sda]; #IO_L23P_T3_34 Sch=AC_SDA
+
+
+##Additional Ethernet signals
+#set_property -dict { PACKAGE_PIN F16 IOSTANDARD LVCMOS33 } [get_ports eth_int_b]; #IO_L6P_T0_35 Sch=ETH_INT_B
+#set_property -dict { PACKAGE_PIN E17 IOSTANDARD LVCMOS33 } [get_ports eth_rst_b]; #IO_L3P_T0_DQS_AD1P_35 Sch=ETH_RST_B
+
+
+##HDMI Signals
+#set_property -dict { PACKAGE_PIN H17 IOSTANDARD TMDS_33 } [get_ports hdmi_clk_n]; #IO_L13N_T2_MRCC_35 Sch=HDMI_CLK_N
+#set_property -dict { PACKAGE_PIN H16 IOSTANDARD TMDS_33 } [get_ports hdmi_clk_p]; #IO_L13P_T2_MRCC_35 Sch=HDMI_CLK_P
+#set_property -dict { PACKAGE_PIN D20 IOSTANDARD TMDS_33 } [get_ports { hdmi_d_n[0] }]; #IO_L4N_T0_35 Sch=HDMI_D0_N
+#set_property -dict { PACKAGE_PIN D19 IOSTANDARD TMDS_33 } [get_ports { hdmi_d_p[0] }]; #IO_L4P_T0_35 Sch=HDMI_D0_P
+#set_property -dict { PACKAGE_PIN B20 IOSTANDARD TMDS_33 } [get_ports { hdmi_d_n[1] }]; #IO_L1N_T0_AD0N_35 Sch=HDMI_D1_N
+#set_property -dict { PACKAGE_PIN C20 IOSTANDARD TMDS_33 } [get_ports { hdmi_d_p[1] }]; #IO_L1P_T0_AD0P_35 Sch=HDMI_D1_P
+#set_property -dict { PACKAGE_PIN A20 IOSTANDARD TMDS_33 } [get_ports { hdmi_d_n[2] }]; #IO_L2N_T0_AD8N_35 Sch=HDMI_D2_N
+#set_property -dict { PACKAGE_PIN B19 IOSTANDARD TMDS_33 } [get_ports { hdmi_d_p[2] }]; #IO_L2P_T0_AD8P_35 Sch=HDMI_D2_P
+#set_property -dict { PACKAGE_PIN E19 IOSTANDARD LVCMOS33 } [get_ports hdmi_cec]; #IO_L5N_T0_AD9N_35 Sch=HDMI_CEC
+#set_property -dict { PACKAGE_PIN E18 IOSTANDARD LVCMOS33 } [get_ports hdmi_hpd]; #IO_L5P_T0_AD9P_35 Sch=HDMI_HPD
+#set_property -dict { PACKAGE_PIN F17 IOSTANDARD LVCMOS33 } [get_ports hdmi_out_en]; #IO_L6N_T0_VREF_35 Sch=HDMI_OUT_EN
+#set_property -dict { PACKAGE_PIN G17 IOSTANDARD LVCMOS33 } [get_ports hdmi_scl]; #IO_L16P_T2_35 Sch=HDMI_SCL
+#set_property -dict { PACKAGE_PIN G18 IOSTANDARD LVCMOS33 } [get_ports hdmi_sda]; #IO_L16N_T2_35 Sch=HDMI_SDA
+
+
+##Pmod Header JA (XADC)
+#set_property -dict { PACKAGE_PIN N16 IOSTANDARD LVCMOS33 } [get_ports { xa_n[0] }]; #IO_L21N_T3_DQS_AD14N_35 Sch=JA1_R_N
+#set_property -dict { PACKAGE_PIN N15 IOSTANDARD LVCMOS33 } [get_ports { xa_p[0] }]; #IO_L21P_T3_DQS_AD14P_35 Sch=JA1_R_p
+#set_property -dict { PACKAGE_PIN L15 IOSTANDARD LVCMOS33 } [get_ports { xa_n[1] }]; #IO_L22N_T3_AD7N_35 Sch=JA2_R_N
+#set_property -dict { PACKAGE_PIN L14 IOSTANDARD LVCMOS33 } [get_ports { xa_p[1] }]; #IO_L22P_T3_AD7P_35 Sch=JA2_R_P
+#set_property -dict { PACKAGE_PIN J16 IOSTANDARD LVCMOS33 } [get_ports { xa_n[2] }]; #IO_L24N_T3_AD15N_35 Sch=JA3_R_N
+#set_property -dict { PACKAGE_PIN K16 IOSTANDARD LVCMOS33 } [get_ports { xa_p[2] }]; #IO_L24P_T3_AD15P_35 Sch=JA3_R_P
+#set_property -dict { PACKAGE_PIN J14 IOSTANDARD LVCMOS33 } [get_ports { xa_n[3] }]; #IO_L20N_T3_AD6N_35 Sch=JA4_R_N
+#set_property -dict { PACKAGE_PIN K14 IOSTANDARD LVCMOS33 } [get_ports { xa_p[3] }]; #IO_L20P_T3_AD6P_35 Sch=JA4_R_P
+
+
+##Pmod Header JB
+#set_property -dict { PACKAGE_PIN U20 IOSTANDARD LVCMOS33 } [get_ports { jb_n[0] }]; #IO_L15N_T2_DQS_34 Sch=JB1_N
+#set_property -dict { PACKAGE_PIN T20 IOSTANDARD LVCMOS33 } [get_ports { jb_p[0] }]; #IO_L15P_T2_DQS_34 Sch=JB1_p
+#set_property -dict { PACKAGE_PIN W20 IOSTANDARD LVCMOS33 } [get_ports { jb_n[1] }]; #IO_L16N_T2_34 Sch=JB2_N
+#set_property -dict { PACKAGE_PIN V20 IOSTANDARD LVCMOS33 } [get_ports { jb_p[1] }]; #IO_L16P_T2_34 Sch=JB2_P
+#set_property -dict { PACKAGE_PIN Y19 IOSTANDARD LVCMOS33 } [get_ports { jb_n[2] }]; #IO_L17N_T2_34 Sch=JB3_N
+#set_property -dict { PACKAGE_PIN Y18 IOSTANDARD LVCMOS33 } [get_ports { jb_p[2] }]; #IO_L17P_T2_34 Sch=JB3_P
+#set_property -dict { PACKAGE_PIN W19 IOSTANDARD LVCMOS33 } [get_ports { jb_n[3] }]; #IO_L22N_T3_34 Sch=JB4_N
+#set_property -dict { PACKAGE_PIN W18 IOSTANDARD LVCMOS33 } [get_ports { jb_p[3] }]; #IO_L22P_T3_34 Sch=JB4_P
+
+
+##Pmod Header JC
+#set_property -dict { PACKAGE_PIN W15 IOSTANDARD LVCMOS33 } [get_ports { jc_n[0] }]; #IO_L10N_T1_34 Sch=JC1_N
+#set_property -dict { PACKAGE_PIN V15 IOSTANDARD LVCMOS33 } [get_ports { jc_p[0] }]; #IO_L10P_T1_34 Sch=JC1_P
+#set_property -dict { PACKAGE_PIN T10 IOSTANDARD LVCMOS33 } [get_ports { jc_n[1] }]; #IO_L1N_T0_34 Sch=JC2_N
+#set_property -dict { PACKAGE_PIN T11 IOSTANDARD LVCMOS33 } [get_ports { jc_p[1] }]; #IO_L1P_T0_34 Sch=JC2_P
+#set_property -dict { PACKAGE_PIN Y14 IOSTANDARD LVCMOS33 } [get_ports { jc_n[2] }]; #IO_L8N_T1_34 Sch=JC3_N
+#set_property -dict { PACKAGE_PIN W14 IOSTANDARD LVCMOS33 } [get_ports { jc_p[2] }]; #IO_L8P_T1_34 Sch=JC3_P
+#set_property -dict { PACKAGE_PIN U12 IOSTANDARD LVCMOS33 } [get_ports { jc_n[3] }]; #IO_L2N_T0_34 Sch=JC4_N
+#set_property -dict { PACKAGE_PIN T12 IOSTANDARD LVCMOS33 } [get_ports { jc_p[3] }]; #IO_L2P_T0_34 Sch=JC4_P
+
+
+##Pmod Header JD
+#set_property -dict { PACKAGE_PIN T15 IOSTANDARD LVCMOS33 } [get_ports { jd_n[0] }]; #IO_L5N_T0_34 Sch=JD1_N
+#set_property -dict { PACKAGE_PIN T14 IOSTANDARD LVCMOS33 } [get_ports { jd_p[0] }]; #IO_L5P_T0_34 Sch=JD1_P
+#set_property -dict { PACKAGE_PIN R14 IOSTANDARD LVCMOS33 } [get_ports { jd_n[1] }]; #IO_L6N_T0_VREF_34 Sch=JD2_N
+#set_property -dict { PACKAGE_PIN P14 IOSTANDARD LVCMOS33 } [get_ports { jd_p[1] }]; #IO_L6P_T0_34 Sch=JD2_P
+#set_property -dict { PACKAGE_PIN U15 IOSTANDARD LVCMOS33 } [get_ports { jd_n[2] }]; #IO_L11N_T1_SRCC_34 Sch=JD3_N
+#set_property -dict { PACKAGE_PIN U14 IOSTANDARD LVCMOS33 } [get_ports { jd_p[2] }]; #IO_L11P_T1_SRCC_34 Sch=JD3_P
+#set_property -dict { PACKAGE_PIN V18 IOSTANDARD LVCMOS33 } [get_ports { jd_n[3] }]; #IO_L21N_T3_DQS_34 Sch=JD4_N
+#set_property -dict { PACKAGE_PIN V17 IOSTANDARD LVCMOS33 } [get_ports { jd_p[3] }]; #IO_L21P_T3_DQS_34 Sch=JD4_P
+
+
+##Pmod Header JE
+#set_property -dict { PACKAGE_PIN V12 IOSTANDARD LVCMOS33 } [get_ports { data_out[0] }]; #IO_L4P_T0_34 Sch=JE1
+#set_property -dict { PACKAGE_PIN W16 IOSTANDARD LVCMOS33 } [get_ports { data_out[1] }]; #IO_L18N_T2_34 Sch=JE2
+#set_property -dict { PACKAGE_PIN J15 IOSTANDARD LVCMOS33 } [get_ports { data_out[2] }]; #IO_25_35 Sch=JE3
+#set_property -dict { PACKAGE_PIN H15 IOSTANDARD LVCMOS33 } [get_ports { data_out[3] }]; #IO_L19P_T3_35 Sch=JE4
+#set_property -dict { PACKAGE_PIN V13 IOSTANDARD LVCMOS33 } [get_ports { data_out[4] }]; #IO_L3N_T0_DQS_34 Sch=JE7
+#set_property -dict { PACKAGE_PIN U17 IOSTANDARD LVCMOS33 } [get_ports { data_out[5] }]; #IO_L9N_T1_DQS_34 Sch=JE8
+#set_property -dict { PACKAGE_PIN T17 IOSTANDARD LVCMOS33 } [get_ports { data_out[6] }]; #IO_L20P_T3_34 Sch=JE9
+#set_property -dict { PACKAGE_PIN Y17 IOSTANDARD LVCMOS33 } [get_ports { data_out[7] }]; #IO_L7N_T1_34 Sch=JE10
+
+
+##USB-OTG overcurrent detect pin
+#set_property -dict { PACKAGE_PIN U13 IOSTANDARD LVCMOS33 } [get_ports otg_oc]; #IO_L3P_T0_DQS_PUDC_B_34 Sch=OTG_OC
+
+
+##VGA Connector
+#set_property -dict { PACKAGE_PIN M19 IOSTANDARD LVCMOS33 } [get_ports { vga_r[0] }]; #IO_L7P_T1_AD2P_35 Sch=VGA_R1
+#set_property -dict { PACKAGE_PIN L20 IOSTANDARD LVCMOS33 } [get_ports { vga_r[1] }]; #IO_L9N_T1_DQS_AD3N_35 Sch=VGA_R2
+#set_property -dict { PACKAGE_PIN J20 IOSTANDARD LVCMOS33 } [get_ports { vga_r[2] }]: #IO_L17P_T2_AD5P_35 Sch=VGA_R3
+#set_property -dict { PACKAGE_PIN G20 IOSTANDARD LVCMOS33 } [get_ports { vga_r[3] }]; #IO_L18N_T2_AD13N_35 Sch=VGA_R4
+#set_property -dict { PACKAGE_PIN F19 IOSTANDARD LVCMOS33 } [get_ports { vga_r[4] }]; #IO_L15P_T2_DQS_AD12P_35 Sch=VGA_R5
+#set_property -dict { PACKAGE_PIN H18 IOSTANDARD LVCMOS33 } [get_ports { vga_g[0] }]; #IO_L14N_T2_AD4N_SRCC_35 Sch=VGA_G0
+#set_property -dict { PACKAGE_PIN N20 IOSTANDARD LVCMOS33 } [get_ports { vga_g[1] }]; #IO_L14P_T2_SRCC_34 Sch=VGA_G1
+#set_property -dict { PACKAGE_PIN L19 IOSTANDARD LVCMOS33 } [get_ports { vga_g[2] }]; #IO_L9P_T1_DQS_AD3P_35 Sch=VGA_G2
+#set_property -dict { PACKAGE_PIN J19 IOSTANDARD LVCMOS33 } [get_ports { vga_g[3] }]; #IO_L10N_T1_AD11N_35 Sch=VGA_G3
+#set_property -dict { PACKAGE_PIN H20 IOSTANDARD LVCMOS33 } [get_ports { vga_g[4] }]; #IO_L17N_T2_AD5N_35 Sch=VGA_G4
+#set_property -dict { PACKAGE_PIN F20 IOSTANDARD LVCMOS33 } [get_ports { vga_g[5] }]; #IO_L15N_T2_DQS_AD12N_35 Sch=VGA=G5
+#set_property -dict { PACKAGE_PIN P20 IOSTANDARD LVCMOS33 } [get_ports { vga_b[0] }]; #IO_L14N_T2_SRCC_34 Sch=VGA_B1
+#set_property -dict { PACKAGE_PIN M20 IOSTANDARD LVCMOS33 } [get_ports { vga_b[1] }]; #IO_L7N_T1_AD2N_35 Sch=VGA_B2
+#set_property -dict { PACKAGE_PIN K19 IOSTANDARD LVCMOS33 } [get_ports { vga_b[2] }]; #IO_L10P_T1_AD11P_35 Sch=VGA_B3
+#set_property -dict { PACKAGE_PIN J18 IOSTANDARD LVCMOS33 } [get_ports { vga_b[3] }]; #IO_L14P_T2_AD4P_SRCC_35 Sch=VGA_B4
+#set_property -dict { PACKAGE_PIN G19 IOSTANDARD LVCMOS33 } [get_ports { vga_b[4] }]; #IO_L18P_T2_AD13P_35 Sch=VGA_B5
+#set_property -dict { PACKAGE_PIN P19 IOSTANDARD LVCMOS33 } [get_ports vga_hs]; #IO_L13N_T2_MRCC_34 Sch=VGA_HS
+#set_property -dict { PACKAGE_PIN R19 IOSTANDARD LVCMOS33 } [get_ports vga_vs]; #IO_0_34 Sch=VGA_VS
diff --git a/hello_world/hw/design_0.pdf b/hello_world/hw/design_0.pdf
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diff --git a/hello_world/hw/flipflop.v b/hello_world/hw/flipflop.v
new file mode 100644
index 0000000..ad0e083
--- /dev/null
+++ b/hello_world/hw/flipflop.v
@@ -0,0 +1,35 @@
+
+/*
+ Copyright (C) 2021 Jonathan Certes
+
+ This program is free software: you can redistribute it and/or modify it under
+ the terms of the GNU General Public License as published by the Free Software
+ Foundation, either version 3 of the License, or (at your option) any later
+ version.
+
+ This program is distributed in the hope that it will be useful, but WITHOUT
+ ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS
+ FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details.
+
+ You should have received a copy of the GNU General Public License along with
+ this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+`timescale 1ns / 1ps
+
+/******************************************************************************/
+
+module flipflop(
+ input clk,
+ input btn,
+ output led
+);
+
+ reg r_led;
+ always @( posedge(clk) ) begin
+ r_led = btn;
+ end
+ assign led = r_led;
+
+endmodule
+
diff --git a/hello_world/hw/schematic.tcl b/hello_world/hw/schematic.tcl
new file mode 100644
index 0000000..872b02e
--- /dev/null
+++ b/hello_world/hw/schematic.tcl
@@ -0,0 +1,94 @@
+
+#
+# Copyright (C) 2021 Jonathan Certes
+#
+# This program is free software: you can redistribute it and/or modify it under
+# the terms of the GNU General Public License as published by the Free Software
+# Foundation, either version 3 of the License, or (at your option) any later
+# version.
+#
+# This program is distributed in the hope that it will be useful, but WITHOUT
+# ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS
+# FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License along with
+# this program. If not, see <http://www.gnu.org/licenses/>.
+#
+
+#
+# This script must be sourced when a bd_design has been created.
+#
+
+set_property source_mgmt_mode All [current_project]
+
+## IMPORTANT! Use digilent pre-configuration for the board:
+set_property board_part "digilentinc.com:zybo:part0:2.0" [current_project]
+
+
+##
+# ports from the FPGA we are going to use, see constraints file:
+#
+create_bd_port -dir "I" "btn_0"
+create_bd_port -dir "I" "btn_1"
+#
+create_bd_port -dir "O" "led_0"
+create_bd_port -dir "O" "led_1"
+
+
+##
+# adding zynq processing system to the design:
+#
+set theInstName "processing_system7_0"
+create_bd_cell -type "ip" \
+ -vlnv "xilinx.com:ip:processing_system7:5.5" \
+ ${theInstName}
+# run block automation:
+apply_bd_automation -rule "xilinx.com:bd_rule:processing_system7" -config {
+ make_external "FIXED_IO, DDR"
+ apply_board_preset 1
+ Master "Disable"
+ Slave "Disable"
+} [get_bd_cells ${theInstName}]
+# connect clock:
+connect_bd_net [get_bd_pins "${theInstName}/FCLK_CLK0"] \
+ [get_bd_pins "${theInstName}/M_AXI_GP0_ACLK"]
+# enables EMIO GPIO and sets its size:
+set_property -dict {
+ CONFIG.PCW_QSPI_GRP_SINGLE_SS_ENABLE 1
+ CONFIG.PCW_GPIO_EMIO_GPIO_ENABLE 1
+ CONFIG.PCW_GPIO_EMIO_GPIO_IO 2
+} [get_bd_cells ${theInstName}]
+# save its instance name:
+set theZynq ${theInstName}
+
+
+##
+# instantiating a module:
+#
+set theInstName "i_connexions"
+create_bd_cell -type "module" -reference "connexions" ${theInstName}
+#
+connect_bd_net [get_bd_pins "${theInstName}/gpio_o"] \
+ [get_bd_pins "${theZynq}/GPIO_O"]
+connect_bd_net [get_bd_pins "${theZynq}/GPIO_I"] \
+ [get_bd_pins "${theInstName}/gpio_i"]
+#
+connect_bd_net [get_bd_ports "btn_0"] [get_bd_pins "${theInstName}/btn_0"]
+connect_bd_net [get_bd_pins "${theInstName}/led_0"] [get_bd_ports "led_0"]
+
+
+##
+# instantiating a module:
+#
+set theInstName "i_flipflop"
+create_bd_cell -type "module" -reference "flipflop" ${theInstName}
+# using clock from the PS7:
+connect_bd_net [get_bd_pins "${theZynq}/FCLK_CLK0"] \
+ [get_bd_pins "${theInstName}/clk"]
+#
+connect_bd_net [get_bd_ports "btn_1"] [get_bd_pins "${theInstName}/btn"]
+connect_bd_net [get_bd_pins "${theInstName}/led"] [get_bd_ports "led_1"]
+
+
+regenerate_bd_layout
+
diff --git a/hello_world/sdcard/Makefile b/hello_world/sdcard/Makefile
new file mode 100644
index 0000000..77e2eee
--- /dev/null
+++ b/hello_world/sdcard/Makefile
@@ -0,0 +1,8 @@
+
+all: boot.bin
+
+boot.bin: boot.bif ../sw/fsbl/main.elf ../sw/app/main.elf ../hw/design_0_wrapper.bit
+ bootgen -w on -image $< -o i $@
+
+clean:
+ $(RM) boot.bin
diff --git a/hello_world/sdcard/boot.bif b/hello_world/sdcard/boot.bif
new file mode 100644
index 0000000..0ee580a
--- /dev/null
+++ b/hello_world/sdcard/boot.bif
@@ -0,0 +1,5 @@
+image : {
+ [bootloader]../sw/fsbl/main.elf
+ ../hw/design_0_wrapper.bit
+ ../sw/app/main.elf
+}
diff --git a/hello_world/sw/Makefile b/hello_world/sw/Makefile
new file mode 100644
index 0000000..54cc8d6
--- /dev/null
+++ b/hello_world/sw/Makefile
@@ -0,0 +1,9 @@
+
+all:
+ make -C fsbl
+ make -C app
+
+clean:
+ make -C fsbl clean
+ make -C app clean
+
diff --git a/hello_world/sw/app/Makefile b/hello_world/sw/app/Makefile
new file mode 100644
index 0000000..3b1eaa1
--- /dev/null
+++ b/hello_world/sw/app/Makefile
@@ -0,0 +1,15 @@
+
+LD = ldscript.ld
+
+# main application:
+SRC += main.c startup.s stdio.c gpio.c
+
+# xilinx zynq library:
+SRC += $(wildcard embeddedsw-master/*.c)
+
+# rootname for output binary:
+BIN = main
+
+#===============================================================================
+
+include Rules.mk
diff --git a/hello_world/sw/app/Rules.mk b/hello_world/sw/app/Rules.mk
new file mode 100644
index 0000000..2d108ae
--- /dev/null
+++ b/hello_world/sw/app/Rules.mk
@@ -0,0 +1,49 @@
+
+#
+ifndef LD
+ echo "You must specify a linker script in variable LD."
+ exit 1
+endif
+#
+ifndef SRC
+ echo "You must specify the source to compile in variable SRC."
+ exit 1
+endif
+#
+ifndef BIN
+ echo "You must specify the binary name in variable BIN."
+ exit 1
+endif
+
+#===============================================================================
+
+INCLUDE = $(addprefix -I , $(sort $(dir ${SRC})))
+CCOUT = $(addsuffix .o, $(basename ${SRC}))
+
+ARMGNU = arm-none-eabi-
+ARCH = -mcpu=cortex-a9
+ASOPS = -g
+COPS = -g -no-pie -Wall -O0 -nostdlib
+LOPS = -L "/usr/lib/arm-none-eabi/newlib/" -lc \
+ -L "/usr/lib/gcc/arm-none-eabi/8.3.1/" -lgcc -lnosys
+
+#===============================================================================
+
+all : ${BIN}.elf
+
+
+${BIN}.elf : ${LD} ${CCOUT}
+ $(ARMGNU)ld -T ${LD} ${CCOUT} -o $@ ${LOPS}
+
+
+%.o : %.c
+ $(ARMGNU)gcc ${ARCH} ${INCLUDE} -c ${COPS} $^ -o $@
+
+%.o : %.s
+ $(ARMGNU)as ${ARCH} ${ASOPS} $^ -o $@
+
+
+clean :
+ $(RM) ${CCOUT}
+ $(RM) ${BIN}.elf
+
diff --git a/hello_world/sw/app/embeddedsw-master/README b/hello_world/sw/app/embeddedsw-master/README
new file mode 100644
index 0000000..6327aef
--- /dev/null
+++ b/hello_world/sw/app/embeddedsw-master/README
@@ -0,0 +1 @@
+Downloaded from repository: https://github.com/Xilinx/embeddedsw
diff --git a/hello_world/sw/app/embeddedsw-master/bspconfig.h b/hello_world/sw/app/embeddedsw-master/bspconfig.h
new file mode 100644
index 0000000..9d62f94
--- /dev/null
+++ b/hello_world/sw/app/embeddedsw-master/bspconfig.h
@@ -0,0 +1,12 @@
+/******************************************************************************
+* Copyright (c) 2010 - 2020 Xilinx, Inc. All rights reserved.
+* SPDX-License-Identifier: MIT
+ ******************************************************************************/
+
+
+
+
+#define MICROBLAZE_PVR_NONE
+#define EL3 1
+#define EL1_NONSECURE 0
+#define HYP_GUEST 0
diff --git a/hello_world/sw/app/embeddedsw-master/xbasic_types.h b/hello_world/sw/app/embeddedsw-master/xbasic_types.h
new file mode 100644
index 0000000..3acda9c
--- /dev/null
+++ b/hello_world/sw/app/embeddedsw-master/xbasic_types.h
@@ -0,0 +1,287 @@
+/******************************************************************************
+* Copyright (C) 2002 - 2020 Xilinx, Inc. All rights reserved.
+* SPDX-License-Identifier: MIT
+******************************************************************************/
+
+/*****************************************************************************/
+/**
+*
+* @file xbasic_types.h
+* @addtogroup common_v1_1
+* @{
+*
+* This file contains basic types for Xilinx software IP. These types do not
+* follow the standard naming convention with respect to using the component
+* name in front of each name because they are considered to be primitives.
+*
+* @note
+*
+* This file contains items which are architecture dependent.
+*
+* <pre>
+* MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ----- ---- -------- -------------------------------------------------------
+* 1.00a rmm 12/14/01 First release
+* rmm 05/09/03 Added "xassert always" macros to rid ourselves of diab
+* compiler warnings
+* 1.00a rpm 11/07/03 Added XNullHandler function as a stub interrupt handler
+* 1.00a rpm 07/21/04 Added XExceptionHandler typedef for processor exceptions
+* 1.00a xd 11/03/04 Improved support for doxygen.
+* 1.00a wre 01/25/07 Added Linux style data types u32, u16, u8, TRUE, FALSE
+* 1.00a rpm 04/02/07 Added ifndef KERNEL around u32, u16, u8 data types
+* </pre>
+*
+******************************************************************************/
+
+#ifndef XBASIC_TYPES_H /* prevent circular inclusions */
+#define XBASIC_TYPES_H /* by using protection macros */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+
+/***************************** Include Files *********************************/
+
+
+/************************** Constant Definitions *****************************/
+
+#ifndef TRUE
+# define TRUE 1
+#endif
+
+#ifndef FALSE
+# define FALSE 0
+#endif
+
+#ifndef NULL
+#define NULL 0
+#endif
+
+/** Xilinx NULL, TRUE and FALSE legacy support. Deprecated. */
+#define XNULL NULL
+#define XTRUE TRUE
+#define XFALSE FALSE
+
+
+#define XCOMPONENT_IS_READY 0x11111111 /**< component has been initialized */
+#define XCOMPONENT_IS_STARTED 0x22222222 /**< component has been started */
+
+/* the following constants and declarations are for unit test purposes and are
+ * designed to be used in test applications.
+ */
+#define XTEST_PASSED 0
+#define XTEST_FAILED 1
+
+#define XASSERT_NONE 0
+#define XASSERT_OCCURRED 1
+
+extern unsigned int XAssertStatus;
+extern void XAssert(char *, int);
+
+/**************************** Type Definitions *******************************/
+
+/** @name Legacy types
+ * Deprecated legacy types.
+ * @{
+ */
+typedef unsigned char Xuint8; /**< unsigned 8-bit */
+typedef char Xint8; /**< signed 8-bit */
+typedef unsigned short Xuint16; /**< unsigned 16-bit */
+typedef short Xint16; /**< signed 16-bit */
+typedef unsigned long Xuint32; /**< unsigned 32-bit */
+typedef long Xint32; /**< signed 32-bit */
+typedef float Xfloat32; /**< 32-bit floating point */
+typedef double Xfloat64; /**< 64-bit double precision FP */
+typedef unsigned long Xboolean; /**< boolean (XTRUE or XFALSE) */
+
+#if !defined __XUINT64__
+typedef struct
+{
+ Xuint32 Upper;
+ Xuint32 Lower;
+} Xuint64;
+#endif
+
+/** @name New types
+ * New simple types.
+ * @{
+ */
+#ifndef __KERNEL__
+#ifndef XIL_TYPES_H
+typedef Xuint32 u32;
+typedef Xuint16 u16;
+typedef Xuint8 u8;
+#endif
+#else
+#include <linux/types.h>
+#endif
+
+/*@}*/
+
+/**
+ * This data type defines an interrupt handler for a device.
+ * The argument points to the instance of the component
+ */
+typedef void (*XInterruptHandler) (void *InstancePtr);
+
+/**
+ * This data type defines an exception handler for a processor.
+ * The argument points to the instance of the component
+ */
+typedef void (*XExceptionHandler) (void *InstancePtr);
+
+/**
+ * This data type defines a callback to be invoked when an
+ * assert occurs. The callback is invoked only when asserts are enabled
+ */
+typedef void (*XAssertCallback) (char *FilenamePtr, int LineNumber);
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/*****************************************************************************/
+/**
+* Return the most significant half of the 64 bit data type.
+*
+* @param x is the 64 bit word.
+*
+* @return The upper 32 bits of the 64 bit word.
+*
+* @note None.
+*
+******************************************************************************/
+#define XUINT64_MSW(x) ((x).Upper)
+
+/*****************************************************************************/
+/**
+* Return the least significant half of the 64 bit data type.
+*
+* @param x is the 64 bit word.
+*
+* @return The lower 32 bits of the 64 bit word.
+*
+* @note None.
+*
+******************************************************************************/
+#define XUINT64_LSW(x) ((x).Lower)
+
+
+#ifndef NDEBUG
+
+/*****************************************************************************/
+/**
+* This assert macro is to be used for functions that do not return anything
+* (void). This in conjunction with the XWaitInAssert boolean can be used to
+* accommodate tests so that asserts which fail allow execution to continue.
+*
+* @param expression is the expression to evaluate. If it evaluates to
+* false, the assert occurs.
+*
+* @return Returns void unless the XWaitInAssert variable is true, in which
+* case no return is made and an infinite loop is entered.
+*
+* @note None.
+*
+******************************************************************************/
+#define XASSERT_VOID(expression) \
+{ \
+ if (expression) \
+ { \
+ XAssertStatus = XASSERT_NONE; \
+ } \
+ else \
+ { \
+ XAssert(__FILE__, __LINE__); \
+ XAssertStatus = XASSERT_OCCURRED; \
+ return; \
+ } \
+}
+
+/*****************************************************************************/
+/**
+* This assert macro is to be used for functions that do return a value. This in
+* conjunction with the XWaitInAssert boolean can be used to accommodate tests so
+* that asserts which fail allow execution to continue.
+*
+* @param expression is the expression to evaluate. If it evaluates to false,
+* the assert occurs.
+*
+* @return Returns 0 unless the XWaitInAssert variable is true, in which case
+* no return is made and an infinite loop is entered.
+*
+* @note None.
+*
+******************************************************************************/
+#define XASSERT_NONVOID(expression) \
+{ \
+ if (expression) \
+ { \
+ XAssertStatus = XASSERT_NONE; \
+ } \
+ else \
+ { \
+ XAssert(__FILE__, __LINE__); \
+ XAssertStatus = XASSERT_OCCURRED; \
+ return 0; \
+ } \
+}
+
+/*****************************************************************************/
+/**
+* Always assert. This assert macro is to be used for functions that do not
+* return anything (void). Use for instances where an assert should always
+* occur.
+*
+* @return Returns void unless the XWaitInAssert variable is true, in which case
+* no return is made and an infinite loop is entered.
+*
+* @note None.
+*
+******************************************************************************/
+#define XASSERT_VOID_ALWAYS() \
+{ \
+ XAssert(__FILE__, __LINE__); \
+ XAssertStatus = XASSERT_OCCURRED; \
+ return; \
+}
+
+/*****************************************************************************/
+/**
+* Always assert. This assert macro is to be used for functions that do return
+* a value. Use for instances where an assert should always occur.
+*
+* @return Returns void unless the XWaitInAssert variable is true, in which case
+* no return is made and an infinite loop is entered.
+*
+* @note None.
+*
+******************************************************************************/
+#define XASSERT_NONVOID_ALWAYS() \
+{ \
+ XAssert(__FILE__, __LINE__); \
+ XAssertStatus = XASSERT_OCCURRED; \
+ return 0; \
+}
+
+
+#else
+
+#define XASSERT_VOID(expression)
+#define XASSERT_VOID_ALWAYS()
+#define XASSERT_NONVOID(expression)
+#define XASSERT_NONVOID_ALWAYS()
+#endif
+
+/************************** Function Prototypes ******************************/
+
+void XAssertSetCallback(XAssertCallback Routine);
+void XNullHandler(void *NullParameter);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* end of protection macro */
+/** @} */
diff --git a/hello_world/sw/app/embeddedsw-master/xil_assert.h b/hello_world/sw/app/embeddedsw-master/xil_assert.h
new file mode 100644
index 0000000..251207f
--- /dev/null
+++ b/hello_world/sw/app/embeddedsw-master/xil_assert.h
@@ -0,0 +1,169 @@
+/******************************************************************************
+* Copyright (c) 2009 - 2020 Xilinx, Inc. All rights reserved.
+* SPDX-License-Identifier: MIT
+******************************************************************************/
+
+/*****************************************************************************/
+/**
+*
+* @file xil_assert.h
+*
+* @addtogroup common_assert_apis Assert APIs and Macros
+*
+* The xil_assert.h file contains assert related functions and macros.
+* Assert APIs/Macros specifies that a application program satisfies certain
+* conditions at particular points in its execution. These function can be
+* used by application programs to ensure that, application code is satisfying
+* certain conditions.
+*
+* @{
+* <pre>
+* MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ----- ---- -------- -------------------------------------------------------
+* 1.00a hbm 07/14/09 First release
+* 6.0 kvn 05/31/16 Make Xil_AsserWait a global variable
+* </pre>
+*
+******************************************************************************/
+
+#ifndef XIL_ASSERT_H /* prevent circular inclusions */
+#define XIL_ASSERT_H /* by using protection macros */
+
+#include "xil_types.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+
+/***************************** Include Files *********************************/
+
+
+/************************** Constant Definitions *****************************/
+
+#define XIL_ASSERT_NONE 0U
+#define XIL_ASSERT_OCCURRED 1U
+#define XNULL NULL
+
+extern u32 Xil_AssertStatus;
+extern s32 Xil_AssertWait;
+extern void Xil_Assert(const char8 *File, s32 Line);
+void XNullHandler(void *NullParameter);
+
+/**
+ * This data type defines a callback to be invoked when an
+ * assert occurs. The callback is invoked only when asserts are enabled
+ */
+typedef void (*Xil_AssertCallback) (const char8 *File, s32 Line);
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+#ifndef NDEBUG
+
+/*****************************************************************************/
+/**
+* @brief This assert macro is to be used for void functions. This in
+* conjunction with the Xil_AssertWait boolean can be used to
+* accommodate tests so that asserts which fail allow execution to
+* continue.
+*
+* @param Expression: expression to be evaluated. If it evaluates to
+* false, the assert occurs.
+*
+* @return Returns void unless the Xil_AssertWait variable is true, in which
+* case no return is made and an infinite loop is entered.
+*
+******************************************************************************/
+#define Xil_AssertVoid(Expression) \
+{ \
+ if (Expression) { \
+ Xil_AssertStatus = XIL_ASSERT_NONE; \
+ } else { \
+ Xil_Assert(__FILE__, __LINE__); \
+ Xil_AssertStatus = XIL_ASSERT_OCCURRED; \
+ return; \
+ } \
+}
+
+/*****************************************************************************/
+/**
+* @brief This assert macro is to be used for functions that do return a
+* value. This in conjunction with the Xil_AssertWait boolean can be
+* used to accommodate tests so that asserts which fail allow execution
+* to continue.
+*
+* @param Expression: expression to be evaluated. If it evaluates to false,
+* the assert occurs.
+*
+* @return Returns 0 unless the Xil_AssertWait variable is true, in which
+* case no return is made and an infinite loop is entered.
+*
+******************************************************************************/
+#define Xil_AssertNonvoid(Expression) \
+{ \
+ if (Expression) { \
+ Xil_AssertStatus = XIL_ASSERT_NONE; \
+ } else { \
+ Xil_Assert(__FILE__, __LINE__); \
+ Xil_AssertStatus = XIL_ASSERT_OCCURRED; \
+ return 0; \
+ } \
+}
+
+/*****************************************************************************/
+/**
+* @brief Always assert. This assert macro is to be used for void functions.
+* Use for instances where an assert should always occur.
+*
+* @return Returns void unless the Xil_AssertWait variable is true, in which
+* case no return is made and an infinite loop is entered.
+*
+******************************************************************************/
+#define Xil_AssertVoidAlways() \
+{ \
+ Xil_Assert(__FILE__, __LINE__); \
+ Xil_AssertStatus = XIL_ASSERT_OCCURRED; \
+ return; \
+}
+
+/*****************************************************************************/
+/**
+* @brief Always assert. This assert macro is to be used for functions that
+* do return a value. Use for instances where an assert should always
+* occur.
+*
+* @return Returns void unless the Xil_AssertWait variable is true, in which
+* case no return is made and an infinite loop is entered.
+*
+******************************************************************************/
+#define Xil_AssertNonvoidAlways() \
+{ \
+ Xil_Assert(__FILE__, __LINE__); \
+ Xil_AssertStatus = XIL_ASSERT_OCCURRED; \
+ return 0; \
+}
+
+
+#else
+
+#define Xil_AssertVoid(Expression)
+#define Xil_AssertVoidAlways()
+#define Xil_AssertNonvoid(Expression)
+#define Xil_AssertNonvoidAlways()
+
+#endif
+
+/************************** Function Prototypes ******************************/
+
+void Xil_AssertSetCallback(Xil_AssertCallback Routine);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* end of protection macro */
+/**
+* @} End of "addtogroup common_assert_apis".
+*/
diff --git a/hello_world/sw/app/embeddedsw-master/xil_cache.c b/hello_world/sw/app/embeddedsw-master/xil_cache.c
new file mode 100644
index 0000000..4cbe9d9
--- /dev/null
+++ b/hello_world/sw/app/embeddedsw-master/xil_cache.c
@@ -0,0 +1,1616 @@
+/******************************************************************************
+* Copyright (c) 2010 - 2020 Xilinx, Inc. All rights reserved.
+* SPDX-License-Identifier: MIT
+******************************************************************************/
+
+/*****************************************************************************/
+/**
+*
+* @file xil_cache.c
+*
+* Contains required functions for the ARM cache functionality.
+*
+* <pre>
+* MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ----- ---- -------- -----------------------------------------------
+* 1.00a ecm 01/29/10 First release
+* 1.00a ecm 06/24/10 Moved the L1 and L2 specific function prototypes
+* to xil_cache_mach.h to give access to sophisticated users
+* 3.02a sdm 04/07/11 Updated Flush/InvalidateRange APIs to flush/invalidate
+* L1 and L2 caches in a single loop and used dsb, L2 sync
+* at the end of the loop.
+* 3.04a sdm 01/02/12 Remove redundant dsb/dmb instructions in cache maintenance
+* APIs.
+* 3.07a asa 07/16/12 Corrected the L1 and L2 cache invalidation order.
+* 3.07a sgd 09/18/12 Corrected the L2 cache enable and disable sequence.
+* 3.10a srt 04/18/13 Implemented ARM Erratas. Please refer to file
+* 'xil_errata.h' for errata description
+* 3.10a asa 05/13/13 Modified cache disable APIs. The L2 cache disable
+* operation was being done with L1 Data cache disabled. This is
+* fixed so that L2 cache disable operation happens independent of
+* L1 cache disable operation. This fixes CR #706464.
+* Changes are done to do a L2 cache sync (poll reg7_?cache_?sync).
+* This is done to fix the CR #700542.
+* 3.11a asa 09/23/13 Modified the Xil_DCacheFlushRange and
+* Xil_DCacheInvalidateRange to fix potential issues. Fixed other
+* relevant cache APIs to disable and enable back the interrupts.
+* This fixes CR #663885.
+* 3.11a asa 09/28/13 Made changes for L2 cache sync operation. It is found
+* out that for L2 cache flush/clean/invalidation by cache lines
+* does not need a cache sync as these are atomic nature. Similarly
+* figured out that for complete L2 cache flush/invalidation by way
+* we need to wait for some more time in a loop till the status
+* shows that the cache operation is completed.
+* 4.00 pkp 24/01/14 Modified Xil_DCacheInvalidateRange to fix the bug. Few
+* cache lines were missed to invalidate when unaligned address
+* invalidation was accommodated. That fixes CR #766768.
+* Also in Xil_L1DCacheInvalidate, while invalidating all L1D cache
+* stack memory which contains return address was invalidated. So
+* stack memory was flushed first and then L1D cache is invalidated.
+* This is done to fix CR #763829
+* 4.01 asa 05/09/14 Made changes in cortexa9/xil_cache.c to fix CR# 798230.
+* 4.02 pkp 06/27/14 Added notes to Xil_L1DCacheInvalidateRange function for
+* explanation of CR#785243
+* 5.00 kvn 12/15/14 Xil_L2CacheInvalidate was modified to fix CR# 838835. L2 Cache
+* has stack memory which has return address. Before invalidating
+* cache, stack memory was flushed first and L2 Cache is invalidated.
+* 5.01 pkp 05/12/15 Xil_DCacheInvalidateRange and Xil_DCacheFlushRange is modified
+* to remove unnecessary dsb in the APIs. Instead of using dsb
+* for L2 Cache, L2CacheSync has been used for each L2 cache line
+* and single dsb has been used for L1 cache. Also L2CacheSync is
+* added into Xil_L2CacheInvalidateRange API. Xil_L1DCacheInvalidate
+* and Xil_L2CacheInvalidate APIs are modified to flush the complete
+* stack instead of just System Stack
+* 5.03 pkp 10/07/15 L2 Cache functionalities are avoided for the OpenAMP slave
+* application(when USE_AMP flag is defined for BSP) as master CPU
+* would be utilizing L2 cache for its operation
+* 6.6 mus 12/07/17 Errata 753970 is not applicable for the PL130 cache controller
+* version r0p2, which is present in zynq. So,removed the handling
+* related to same.It fixes CR#989132.
+* 6.6 asa 16/01/18 Changes made in Xil_L1DCacheInvalidate and Xil_L2CacheInvalidate
+* routines to ensure the stack data flushed only when the respective
+* caches are enabled. This fixes CR-992023.
+*
+* </pre>
+*
+******************************************************************************/
+
+/***************************** Include Files *********************************/
+
+#include "xil_cache.h"
+#include "xil_cache_l.h"
+#include "xil_io.h"
+#include "xpseudo_asm.h"
+#include "xparameters.h"
+#include "xreg_cortexa9.h"
+#include "xl2cc.h"
+#include "xil_errata.h"
+#include "xil_exception.h"
+#include "xparameters_ps.h"
+
+/************************** Function Prototypes ******************************/
+
+/************************** Variable Definitions *****************************/
+
+#define IRQ_FIQ_MASK 0xC0U /* Mask IRQ and FIQ interrupts in cpsr */
+
+#ifdef __GNUC__
+ extern s32 _stack_end;
+ extern s32 __undef_stack;
+#endif
+
+#ifndef USE_AMP
+/****************************************************************************
+*
+* Access L2 Debug Control Register.
+*
+* @param Value, value to be written to Debug Control Register.
+*
+* @return None.
+*
+* @note None.
+*
+****************************************************************************/
+#ifdef __GNUC__
+static inline void Xil_L2WriteDebugCtrl(u32 Value)
+#else
+static void Xil_L2WriteDebugCtrl(u32 Value)
+#endif
+{
+#if defined(CONFIG_PL310_ERRATA_588369) || defined(CONFIG_PL310_ERRATA_727915)
+ Xil_Out32(XPS_L2CC_BASEADDR + XPS_L2CC_DEBUG_CTRL_OFFSET, Value);
+#else
+ (void)(Value);
+#endif
+}
+
+/****************************************************************************
+*
+* Perform L2 Cache Sync Operation.
+*
+* @param None.
+*
+* @return None.
+*
+* @note None.
+*
+****************************************************************************/
+#ifdef __GNUC__
+static inline void Xil_L2CacheSync(void)
+#else
+static void Xil_L2CacheSync(void)
+#endif
+{
+ Xil_Out32(XPS_L2CC_BASEADDR + XPS_L2CC_CACHE_SYNC_OFFSET, 0x0U);
+}
+#endif
+/****************************************************************************/
+/**
+* @brief Enable the Data cache.
+*
+* @param None.
+*
+* @return None.
+*
+* @note None.
+*
+****************************************************************************/
+void Xil_DCacheEnable(void)
+{
+ Xil_L1DCacheEnable();
+#ifndef USE_AMP
+ Xil_L2CacheEnable();
+#endif
+}
+
+/****************************************************************************/
+/**
+* @brief Disable the Data cache.
+*
+* @param None.
+*
+* @return None.
+*
+* @note None.
+*
+****************************************************************************/
+void Xil_DCacheDisable(void)
+{
+#ifndef USE_AMP
+ Xil_L2CacheDisable();
+#endif
+ Xil_L1DCacheDisable();
+}
+
+/****************************************************************************/
+/**
+* @brief Invalidate the entire Data cache.
+*
+* @param None.
+*
+* @return None.
+*
+* @note None.
+*
+****************************************************************************/
+void Xil_DCacheInvalidate(void)
+{
+ u32 currmask;
+
+ currmask = mfcpsr();
+ mtcpsr(currmask | IRQ_FIQ_MASK);
+#ifndef USE_AMP
+ Xil_L2CacheInvalidate();
+#endif
+ Xil_L1DCacheInvalidate();
+
+ mtcpsr(currmask);
+}
+
+/*****************************************************************************/
+/**
+* @brief Invalidate a Data cache line. If the byte specified by the address
+* (adr) is cached by the Data cache, the cacheline containing that
+* byte is invalidated. If the cacheline is modified (dirty), the
+* modified contents are lost and are NOT written to the system memory
+* before the line is invalidated.
+*
+* @param adr: 32bit address of the data to be flushed.
+*
+* @return None.
+*
+* @note The bottom 4 bits are set to 0, forced by architecture.
+*
+****************************************************************************/
+void Xil_DCacheInvalidateLine(u32 adr)
+{
+ u32 currmask;
+
+ currmask = mfcpsr();
+ mtcpsr(currmask | IRQ_FIQ_MASK);
+#ifndef USE_AMP
+ Xil_L2CacheInvalidateLine(adr);
+#endif
+ Xil_L1DCacheInvalidateLine(adr);
+
+ mtcpsr(currmask);
+}
+
+
+/*****************************************************************************/
+/**
+* @brief Invalidate the Data cache for the given address range.
+* If the bytes specified by the address range are cached by the Data
+* cache, the cachelines containing those bytes are invalidated. If
+* the cachelines are modified (dirty), the modified contents are lost
+* and NOT written to the system memory before the lines are
+* invalidated.
+*
+* In this function, if start address or end address is not aligned to
+* cache-line, particular cache-line containing unaligned start or end
+* address is flush first and then invalidated the others as
+* invalidating the same unaligned cache line may result into loss of
+* data. This issue raises few possibilities.
+*
+* If the address to be invalidated is not cache-line aligned, the
+* following choices are available:
+* 1. Invalidate the cache line when required and do not bother much
+* for the side effects. Though it sounds good, it can result in
+* hard-to-debug issues. The problem is, if some other variable are
+* allocated in the same cache line and had been recently updated
+* (in cache), the invalidation would result in loss of data.
+* 2. Flush the cache line first. This will ensure that if any other
+* variable present in the same cache line and updated recently are
+* flushed out to memory. Then it can safely be invalidated. Again it
+* sounds good, but this can result in issues. For example, when the
+* invalidation happens in a typical ISR (after a DMA transfer has
+* updated the memory), then flushing the cache line means, losing
+* data that were updated recently before the ISR got invoked.
+*
+* Linux prefers the second one. To have uniform implementation
+* (across standalone and Linux), the second option is implemented.
+* This being the case, following needs to be taken care of:
+* 1. Whenever possible, the addresses must be cache line aligned.
+* Please nore that, not just start address, even the end address must
+* be cache line aligned. If that is taken care of, this will always
+* work.
+* 2. Avoid situations where invalidation has to be done after the
+* data is updated by peripheral/DMA directly into the memory. It is
+* not tough to achieve (may be a bit risky). The common use case to
+* do invalidation is when a DMA happens. Generally for such use
+* cases, buffers can be allocated first and then start the DMA. The
+* practice that needs to be followed here is, immediately after
+* buffer allocation and before starting the DMA, do the invalidation.
+* With this approach, invalidation need not to be done after the DMA
+* transfer is over.
+*
+* This is going to always work if done carefully.
+* However, the concern is, there is no guarantee that invalidate has
+* not needed to be done after DMA is complete. For example, because
+* of some reasons if the first cache line or last cache line
+* (assuming the buffer in question comprises of multiple cache lines)
+* are brought into cache (between the time it is invalidated and DMA
+* completes) because of some speculative prefetching or reading data
+* for a variable present in the same cache line, then we will have to
+* invalidate the cache after DMA is complete.
+*
+*
+* @param adr: 32bit start address of the range to be invalidated.
+* @param len: Length of the range to be invalidated in bytes.
+*
+* @return None.
+*
+* @note None.
+*
+****************************************************************************/
+void Xil_DCacheInvalidateRange(INTPTR adr, u32 len)
+{
+ const u32 cacheline = 32U;
+ u32 end;
+ u32 tempadr = adr;
+ u32 tempend;
+ u32 currmask;
+ volatile u32 *L2CCOffset = (volatile u32 *)(XPS_L2CC_BASEADDR +
+ XPS_L2CC_CACHE_INVLD_PA_OFFSET);
+
+ currmask = mfcpsr();
+ mtcpsr(currmask | IRQ_FIQ_MASK);
+
+ if (len != 0U) {
+ end = tempadr + len;
+ tempend = end;
+ /* Select L1 Data cache in CSSR */
+ mtcp(XREG_CP15_CACHE_SIZE_SEL, 0U);
+
+ if ((tempadr & (cacheline-1U)) != 0U) {
+ tempadr &= (~(cacheline - 1U));
+
+ Xil_L1DCacheFlushLine(tempadr);
+#ifndef USE_AMP
+ /* Disable Write-back and line fills */
+ Xil_L2WriteDebugCtrl(0x3U);
+ Xil_L2CacheFlushLine(tempadr);
+ /* Enable Write-back and line fills */
+ Xil_L2WriteDebugCtrl(0x0U);
+ Xil_L2CacheSync();
+#endif
+ tempadr += cacheline;
+ }
+ if ((tempend & (cacheline-1U)) != 0U) {
+ tempend &= (~(cacheline - 1U));
+
+ Xil_L1DCacheFlushLine(tempend);
+#ifndef USE_AMP
+ /* Disable Write-back and line fills */
+ Xil_L2WriteDebugCtrl(0x3U);
+ Xil_L2CacheFlushLine(tempend);
+ /* Enable Write-back and line fills */
+ Xil_L2WriteDebugCtrl(0x0U);
+ Xil_L2CacheSync();
+#endif
+ }
+
+ while (tempadr < tempend) {
+#ifndef USE_AMP
+ /* Invalidate L2 cache line */
+ *L2CCOffset = tempadr;
+ Xil_L2CacheSync();
+#endif
+
+ /* Invalidate L1 Data cache line */
+#if defined (__GNUC__) || defined (__ICCARM__)
+ asm_cp15_inval_dc_line_mva_poc(tempadr);
+#else
+ { volatile register u32 Reg
+ __asm(XREG_CP15_INVAL_DC_LINE_MVA_POC);
+ Reg = tempadr; }
+#endif
+ tempadr += cacheline;
+ }
+ }
+
+ dsb();
+ mtcpsr(currmask);
+}
+
+/****************************************************************************/
+/**
+* @brief Flush the entire Data cache.
+*
+* @param None.
+*
+* @return None.
+*
+* @note None.
+*
+****************************************************************************/
+void Xil_DCacheFlush(void)
+{
+ u32 currmask;
+
+ currmask = mfcpsr();
+ mtcpsr(currmask | IRQ_FIQ_MASK);
+ Xil_L1DCacheFlush();
+#ifndef USE_AMP
+ Xil_L2CacheFlush();
+#endif
+ mtcpsr(currmask);
+}
+
+
+/****************************************************************************/
+/**
+* @brief Flush a Data cache line. If the byte specified by the address (adr)
+* is cached by the Data cache, the cacheline containing that byte is
+* invalidated. If the cacheline is modified (dirty), the entire
+* contents of the cacheline are written to system memory before the
+* line is invalidated.
+*
+* @param adr: 32bit address of the data to be flushed.
+*
+* @return None.
+*
+* @note The bottom 4 bits are set to 0, forced by architecture.
+*
+****************************************************************************/
+void Xil_DCacheFlushLine(u32 adr)
+{
+ u32 currmask;
+
+ currmask = mfcpsr();
+ mtcpsr(currmask | IRQ_FIQ_MASK);
+ Xil_L1DCacheFlushLine(adr);
+#ifndef USE_AMP
+ /* Disable Write-back and line fills */
+ Xil_L2WriteDebugCtrl(0x3U);
+
+ Xil_L2CacheFlushLine(adr);
+
+ /* Enable Write-back and line fills */
+ Xil_L2WriteDebugCtrl(0x0U);
+ Xil_L2CacheSync();
+#endif
+ mtcpsr(currmask);
+}
+
+/****************************************************************************/
+/**
+* @brief Flush the Data cache for the given address range.
+* If the bytes specified by the address range are cached by the
+* data cache, the cachelines containing those bytes are invalidated.
+* If the cachelines are modified (dirty), they are written to the
+* system memory before the lines are invalidated.
+*
+* @param adr: 32bit start address of the range to be flushed.
+* @param len: Length of the range to be flushed in bytes.
+*
+* @return None.
+*
+* @note None.
+*
+****************************************************************************/
+void Xil_DCacheFlushRange(INTPTR adr, u32 len)
+{
+ u32 LocalAddr = adr;
+ const u32 cacheline = 32U;
+ u32 end;
+ u32 currmask;
+ volatile u32 *L2CCOffset = (volatile u32 *)(XPS_L2CC_BASEADDR +
+ XPS_L2CC_CACHE_INV_CLN_PA_OFFSET);
+
+ currmask = mfcpsr();
+ mtcpsr(currmask | IRQ_FIQ_MASK);
+
+ if (len != 0U) {
+ /* Back the starting address up to the start of a cache line
+ * perform cache operations until adr+len
+ */
+ end = LocalAddr + len;
+ LocalAddr &= ~(cacheline - 1U);
+
+ while (LocalAddr < end) {
+
+ /* Flush L1 Data cache line */
+#if defined (__GNUC__) || defined (__ICCARM__)
+ asm_cp15_clean_inval_dc_line_mva_poc(LocalAddr);
+#else
+ { volatile register u32 Reg
+ __asm(XREG_CP15_CLEAN_INVAL_DC_LINE_MVA_POC);
+ Reg = LocalAddr; }
+#endif
+#ifndef USE_AMP
+ /* Flush L2 cache line */
+ *L2CCOffset = LocalAddr;
+ Xil_L2CacheSync();
+#endif
+ LocalAddr += cacheline;
+ }
+ }
+ dsb();
+ mtcpsr(currmask);
+}
+/****************************************************************************/
+/**
+* @brief Store a Data cache line. If the byte specified by the address (adr)
+* is cached by the Data cache and the cacheline is modified (dirty),
+* the entire contents of the cacheline are written to system memory.
+* After the store completes, the cacheline is marked as unmodified
+* (not dirty).
+*
+* @param adr: 32bit address of the data to be stored.
+*
+* @return None.
+*
+* @note The bottom 4 bits are set to 0, forced by architecture.
+*
+****************************************************************************/
+void Xil_DCacheStoreLine(u32 adr)
+{
+ u32 currmask;
+
+ currmask = mfcpsr();
+ mtcpsr(currmask | IRQ_FIQ_MASK);
+
+ Xil_L1DCacheStoreLine(adr);
+#ifndef USE_AMP
+ Xil_L2CacheStoreLine(adr);
+#endif
+ mtcpsr(currmask);
+}
+
+/***************************************************************************/
+/**
+* @brief Enable the instruction cache.
+*
+* @param None.
+*
+* @return None.
+*
+* @note None.
+*
+****************************************************************************/
+void Xil_ICacheEnable(void)
+{
+ Xil_L1ICacheEnable();
+#ifndef USE_AMP
+ Xil_L2CacheEnable();
+#endif
+}
+
+/***************************************************************************/
+/**
+* @brief Disable the instruction cache.
+*
+* @param None.
+*
+* @return None.
+*
+* @note None.
+*
+****************************************************************************/
+void Xil_ICacheDisable(void)
+{
+#ifndef USE_AMP
+ Xil_L2CacheDisable();
+#endif
+ Xil_L1ICacheDisable();
+}
+
+
+/****************************************************************************/
+/**
+* @brief Invalidate the entire instruction cache.
+*
+* @param None.
+*
+* @return None.
+*
+* @note None.
+*
+****************************************************************************/
+void Xil_ICacheInvalidate(void)
+{
+ u32 currmask;
+
+ currmask = mfcpsr();
+ mtcpsr(currmask | IRQ_FIQ_MASK);
+#ifndef USE_AMP
+ Xil_L2CacheInvalidate();
+#endif
+ Xil_L1ICacheInvalidate();
+
+ mtcpsr(currmask);
+}
+
+/****************************************************************************/
+/**
+* @brief Invalidate an instruction cache line. If the instruction specified
+* by the address is cached by the instruction cache, the cacheline
+* containing that instruction is invalidated.
+*
+* @param adr: 32bit address of the instruction to be invalidated.
+*
+* @return None.
+*
+* @note The bottom 4 bits are set to 0, forced by architecture.
+*
+****************************************************************************/
+void Xil_ICacheInvalidateLine(u32 adr)
+{
+ u32 currmask;
+
+ currmask = mfcpsr();
+ mtcpsr(currmask | IRQ_FIQ_MASK);
+#ifndef USE_AMP
+ Xil_L2CacheInvalidateLine(adr);
+#endif
+ Xil_L1ICacheInvalidateLine(adr);
+ mtcpsr(currmask);
+}
+
+/****************************************************************************/
+/**
+* @brief Invalidate the instruction cache for the given address range.
+* If the instructions specified by the address range are cached by
+* the instrunction cache, the cachelines containing those
+* instructions are invalidated.
+*
+* @param adr: 32bit start address of the range to be invalidated.
+* @param len: Length of the range to be invalidated in bytes.
+*
+* @return None.
+*
+* @note None.
+*
+****************************************************************************/
+void Xil_ICacheInvalidateRange(INTPTR adr, u32 len)
+{
+ u32 LocalAddr = adr;
+ const u32 cacheline = 32U;
+ u32 end;
+ volatile u32 *L2CCOffset = (volatile u32 *)(XPS_L2CC_BASEADDR +
+ XPS_L2CC_CACHE_INVLD_PA_OFFSET);
+
+ u32 currmask;
+
+ currmask = mfcpsr();
+ mtcpsr(currmask | IRQ_FIQ_MASK);
+ if (len != 0U) {
+ /* Back the starting address up to the start of a cache line
+ * perform cache operations until adr+len
+ */
+ end = LocalAddr + len;
+ LocalAddr = LocalAddr & ~(cacheline - 1U);
+
+ /* Select cache L0 I-cache in CSSR */
+ mtcp(XREG_CP15_CACHE_SIZE_SEL, 1U);
+
+ while (LocalAddr < end) {
+#ifndef USE_AMP
+ /* Invalidate L2 cache line */
+ *L2CCOffset = LocalAddr;
+ dsb();
+#endif
+
+ /* Invalidate L1 I-cache line */
+#if defined (__GNUC__) || defined (__ICCARM__)
+ asm_cp15_inval_ic_line_mva_pou(LocalAddr);
+#else
+ { volatile register u32 Reg
+ __asm(XREG_CP15_INVAL_IC_LINE_MVA_POU);
+ Reg = LocalAddr; }
+#endif
+
+ LocalAddr += cacheline;
+ }
+ }
+
+ /* Wait for L1 and L2 invalidate to complete */
+ dsb();
+ mtcpsr(currmask);
+}
+
+/****************************************************************************/
+/**
+* @brief Enable the level 1 Data cache.
+*
+* @param None.
+*
+* @return None.
+*
+* @note None.
+*
+****************************************************************************/
+void Xil_L1DCacheEnable(void)
+{
+ register u32 CtrlReg;
+
+ /* enable caches only if they are disabled */
+#ifdef __GNUC__
+ CtrlReg = mfcp(XREG_CP15_SYS_CONTROL);
+#elif defined (__ICCARM__)
+ mfcp(XREG_CP15_SYS_CONTROL, CtrlReg);
+#else
+ { volatile register u32 Reg __asm(XREG_CP15_SYS_CONTROL);
+ CtrlReg = Reg; }
+#endif
+ if ((CtrlReg & (XREG_CP15_CONTROL_C_BIT)) != 0U) {
+ return;
+ }
+
+ /* clean and invalidate the Data cache */
+ Xil_L1DCacheInvalidate();
+
+ /* enable the Data cache */
+ CtrlReg |= (XREG_CP15_CONTROL_C_BIT);
+
+ mtcp(XREG_CP15_SYS_CONTROL, CtrlReg);
+}
+
+/***************************************************************************/
+/**
+* @brief Disable the level 1 Data cache.
+*
+* @param None.
+*
+* @return None.
+*
+* @note None.
+*
+****************************************************************************/
+void Xil_L1DCacheDisable(void)
+{
+ register u32 CtrlReg;
+
+ /* clean and invalidate the Data cache */
+ Xil_L1DCacheFlush();
+
+#ifdef __GNUC__
+ /* disable the Data cache */
+ CtrlReg = mfcp(XREG_CP15_SYS_CONTROL);
+#elif defined (__ICCARM__)
+ mfcp(XREG_CP15_SYS_CONTROL, CtrlReg);
+#else
+ { volatile register u32 Reg __asm(XREG_CP15_SYS_CONTROL);
+ CtrlReg = Reg; }
+#endif
+
+ CtrlReg &= ~(XREG_CP15_CONTROL_C_BIT);
+
+ mtcp(XREG_CP15_SYS_CONTROL, CtrlReg);
+}
+
+/****************************************************************************/
+/**
+* @brief Invalidate the level 1 Data cache.
+*
+* @param None.
+*
+* @return None.
+*
+* @note In Cortex A9, there is no cp instruction for invalidating
+* the whole D-cache. This function invalidates each line by
+* set/way.
+*
+****************************************************************************/
+void Xil_L1DCacheInvalidate(void)
+{
+ register u32 CsidReg, C7Reg;
+ u32 CacheSize, LineSize, NumWays;
+ u32 Way, WayIndex, Set, SetIndex, NumSet;
+ u32 currmask;
+
+#ifdef __GNUC__
+ u32 stack_start,stack_end,stack_size;
+ register u32 CtrlReg;
+#endif
+
+ currmask = mfcpsr();
+ mtcpsr(currmask | IRQ_FIQ_MASK);
+
+#ifdef __GNUC__
+ stack_end = (u32)&_stack_end;
+ stack_start = (u32)&__undef_stack;
+ stack_size=stack_start-stack_end;
+
+ /* Check for the cache status. If cache is enabled, then only
+ * flush stack memory to save return address. If cache is disabled,
+ * don't flush anything as it might result in flushing stale date into
+ * memory which is undesirable.
+ * */
+ CtrlReg = mfcp(XREG_CP15_SYS_CONTROL);
+ if ((CtrlReg & (XREG_CP15_CONTROL_C_BIT)) != 0U) {
+ Xil_DCacheFlushRange(stack_end, stack_size);
+ }
+#endif
+
+ /* Select cache level 0 and D cache in CSSR */
+ mtcp(XREG_CP15_CACHE_SIZE_SEL, 0U);
+
+#ifdef __GNUC__
+ CsidReg = mfcp(XREG_CP15_CACHE_SIZE_ID);
+#elif defined (__ICCARM__)
+ mfcp(XREG_CP15_CACHE_SIZE_ID, CsidReg);
+#else
+ { volatile register u32 Reg __asm(XREG_CP15_CACHE_SIZE_ID);
+ CsidReg = Reg; }
+#endif
+ /* Determine Cache Size */
+ CacheSize = (CsidReg >> 13U) & 0x1FFU;
+ CacheSize +=1U;
+ CacheSize *=128U; /* to get number of bytes */
+
+ /* Number of Ways */
+ NumWays = (CsidReg & 0x3ffU) >> 3U;
+ NumWays += 1U;
+
+ /* Get the cacheline size, way size, index size from csidr */
+ LineSize = (CsidReg & 0x07U) + 4U;
+
+ NumSet = CacheSize/NumWays;
+ NumSet /= (0x00000001U << LineSize);
+
+ Way = 0U;
+ Set = 0U;
+
+ /* Invalidate all the cachelines */
+ for (WayIndex =0U; WayIndex < NumWays; WayIndex++) {
+ for (SetIndex =0U; SetIndex < NumSet; SetIndex++) {
+ C7Reg = Way | Set;
+
+ /* Invalidate by Set/Way */
+#if defined (__GNUC__) || defined (__ICCARM__)
+ asm_cp15_inval_dc_line_sw(C7Reg);
+#else
+ /*mtcp(XREG_CP15_INVAL_DC_LINE_SW, C7Reg), */
+ { volatile register u32 Reg
+ __asm(XREG_CP15_INVAL_DC_LINE_SW);
+ Reg = C7Reg; }
+#endif
+ Set += (0x00000001U << LineSize);
+ }
+ Set=0U;
+ Way += 0x40000000U;
+ }
+
+ /* Wait for L1 invalidate to complete */
+ dsb();
+ mtcpsr(currmask);
+}
+
+/****************************************************************************/
+/**
+* @brief Invalidate a level 1 Data cache line. If the byte specified by the
+* address (Addr) is cached by the Data cache, the cacheline
+* containing that byte is invalidated. If the cacheline is modified
+* (dirty), the modified contents are lost and are NOT written to
+* system memory before the line is invalidated.
+*
+* @param adr: 32bit address of the data to be invalidated.
+*
+* @return None.
+*
+* @note The bottom 5 bits are set to 0, forced by architecture.
+*
+****************************************************************************/
+void Xil_L1DCacheInvalidateLine(u32 adr)
+{
+ mtcp(XREG_CP15_CACHE_SIZE_SEL, 0U);
+ mtcp(XREG_CP15_INVAL_DC_LINE_MVA_POC, (adr & (~0x1FU)));
+
+ /* Wait for L1 invalidate to complete */
+ dsb();
+}
+
+/****************************************************************************/
+/**
+* @brief Invalidate the level 1 Data cache for the given address range.
+* If the bytes specified by the address range are cached by the Data
+* cache, the cachelines containing those bytes are invalidated. If the
+* cachelines are modified (dirty), the modified contents are lost and
+* NOT written to the system memory before the lines are invalidated.
+*
+* @param adr: 32bit start address of the range to be invalidated.
+* @param len: Length of the range to be invalidated in bytes.
+*
+* @return None.
+*
+* @note None.
+*
+****************************************************************************/
+void Xil_L1DCacheInvalidateRange(u32 adr, u32 len)
+{
+ u32 LocalAddr = adr;
+ const u32 cacheline = 32U;
+ u32 end;
+ u32 currmask;
+
+ currmask = mfcpsr();
+ mtcpsr(currmask | IRQ_FIQ_MASK);
+
+ if (len != 0U) {
+ /* Back the starting address up to the start of a cache line
+ * perform cache operations until adr+len
+ */
+ end = LocalAddr + len;
+ LocalAddr = LocalAddr & ~(cacheline - 1U);
+
+ /* Select cache L0 D-cache in CSSR */
+ mtcp(XREG_CP15_CACHE_SIZE_SEL, 0);
+
+ while (LocalAddr < end) {
+
+#if defined (__GNUC__) || defined (__ICCARM__)
+ asm_cp15_inval_dc_line_mva_poc(LocalAddr);
+#else
+ { volatile register u32 Reg
+ __asm(XREG_CP15_INVAL_DC_LINE_MVA_POC);
+ Reg = LocalAddr; }
+#endif
+ LocalAddr += cacheline;
+ }
+ }
+
+ /* Wait for L1 invalidate to complete */
+ dsb();
+ mtcpsr(currmask);
+}
+
+/****************************************************************************/
+/**
+* @brief Flush the level 1 Data cache.
+*
+* @param None.
+*
+* @return None.
+*
+* @note In Cortex A9, there is no cp instruction for flushing
+* the whole D-cache. Need to flush each line.
+*
+****************************************************************************/
+void Xil_L1DCacheFlush(void)
+{
+ register u32 CsidReg, C7Reg;
+ u32 CacheSize, LineSize, NumWays;
+ u32 Way;
+ u32 WayIndex, Set, SetIndex, NumSet;
+ u32 currmask;
+
+ currmask = mfcpsr();
+ mtcpsr(currmask | IRQ_FIQ_MASK);
+
+ /* Select cache level 0 and D cache in CSSR */
+ mtcp(XREG_CP15_CACHE_SIZE_SEL, 0);
+
+#ifdef __GNUC__
+ CsidReg = mfcp(XREG_CP15_CACHE_SIZE_ID);
+#elif defined (__ICCARM__)
+ mfcp(XREG_CP15_CACHE_SIZE_ID, CsidReg);
+#else
+ { volatile register u32 Reg __asm(XREG_CP15_CACHE_SIZE_ID);
+ CsidReg = Reg; }
+#endif
+
+ /* Determine Cache Size */
+
+ CacheSize = (CsidReg >> 13U) & 0x1FFU;
+ CacheSize +=1U;
+ CacheSize *=128U; /* to get number of bytes */
+
+ /* Number of Ways */
+ NumWays = (CsidReg & 0x3ffU) >> 3U;
+ NumWays += 1U;
+
+ /* Get the cacheline size, way size, index size from csidr */
+ LineSize = (CsidReg & 0x07U) + 4U;
+
+ NumSet = CacheSize/NumWays;
+ NumSet /= (0x00000001U << LineSize);
+
+ Way = 0U;
+ Set = 0U;
+
+ /* Invalidate all the cachelines */
+ for (WayIndex =0U; WayIndex < NumWays; WayIndex++) {
+ for (SetIndex =0U; SetIndex < NumSet; SetIndex++) {
+ C7Reg = Way | Set;
+ /* Flush by Set/Way */
+
+#if defined (__GNUC__) || defined (__ICCARM__)
+ asm_cp15_clean_inval_dc_line_sw(C7Reg);
+#else
+ { volatile register u32 Reg
+ __asm(XREG_CP15_CLEAN_INVAL_DC_LINE_SW);
+ Reg = C7Reg; }
+#endif
+ Set += (0x00000001U << LineSize);
+ }
+ Set = 0U;
+ Way += 0x40000000U;
+ }
+
+ /* Wait for L1 flush to complete */
+ dsb();
+ mtcpsr(currmask);
+}
+
+/****************************************************************************/
+/**
+* @brief Flush a level 1 Data cache line. If the byte specified by the
+* address (adr) is cached by the Data cache, the cacheline containing
+* that byte is invalidated. If the cacheline is modified (dirty), the
+* entire contents of the cacheline are written to system memory
+* before the line is invalidated.
+*
+* @param adr: 32bit address of the data to be flushed.
+*
+* @return None.
+*
+* @note The bottom 5 bits are set to 0, forced by architecture.
+*
+****************************************************************************/
+void Xil_L1DCacheFlushLine(u32 adr)
+{
+ mtcp(XREG_CP15_CACHE_SIZE_SEL, 0U);
+ mtcp(XREG_CP15_CLEAN_INVAL_DC_LINE_MVA_POC, (adr & (~0x1FU)));
+
+ /* Wait for L1 flush to complete */
+ dsb();
+}
+
+/****************************************************************************/
+/**
+* @brief Flush the level 1 Data cache for the given address range.
+* If the bytes specified by the address range are cached by the Data
+* cache, the cacheline containing those bytes are invalidated. If the
+* cachelines are modified (dirty), they are written to system memory
+* before the lines are invalidated.
+*
+* @param adr: 32bit start address of the range to be flushed.
+* @param len: Length of the range to be flushed in bytes.
+*
+* @return None.
+*
+* @note None.
+*
+****************************************************************************/
+void Xil_L1DCacheFlushRange(u32 adr, u32 len)
+{
+ u32 LocalAddr = adr;
+ const u32 cacheline = 32U;
+ u32 end;
+ u32 currmask;
+
+ currmask = mfcpsr();
+ mtcpsr(currmask | IRQ_FIQ_MASK);
+
+ if (len != 0U) {
+ /* Back the starting address up to the start of a cache line
+ * perform cache operations until adr+len
+ */
+ end = LocalAddr + len;
+ LocalAddr = LocalAddr & ~(cacheline - 1U);
+
+ /* Select cache L0 D-cache in CSSR */
+ mtcp(XREG_CP15_CACHE_SIZE_SEL, 0U);
+
+ while (LocalAddr < end) {
+
+#if defined (__GNUC__) || defined (__ICCARM__)
+ asm_cp15_clean_inval_dc_line_mva_poc(LocalAddr);
+#else
+ { volatile register u32 Reg
+ __asm(XREG_CP15_CLEAN_INVAL_DC_LINE_MVA_POC);
+ Reg = LocalAddr; }
+#endif
+ LocalAddr += cacheline;
+ }
+ }
+
+ /* Wait for L1 flush to complete */
+ dsb();
+ mtcpsr(currmask);
+}
+
+/****************************************************************************/
+/**
+* @brief Store a level 1 Data cache line. If the byte specified by the
+* address (adr) is cached by the Data cache and the cacheline is
+* modified (dirty), the entire contents of the cacheline are written
+* to system memory. After the store completes, the cacheline is
+* marked as unmodified (not dirty).
+*
+* @param Address to be stored.
+*
+* @return None.
+*
+* @note The bottom 5 bits are set to 0, forced by architecture.
+*
+****************************************************************************/
+void Xil_L1DCacheStoreLine(u32 adr)
+{
+ mtcp(XREG_CP15_CACHE_SIZE_SEL, 0U);
+ mtcp(XREG_CP15_CLEAN_DC_LINE_MVA_POC, (adr & (~0x1FU)));
+
+ /* Wait for L1 store to complete */
+ dsb();
+}
+
+
+/****************************************************************************/
+/**
+* @brief Enable the level 1 instruction cache.
+*
+* @param None.
+*
+* @return None.
+*
+* @note None.
+*
+****************************************************************************/
+void Xil_L1ICacheEnable(void)
+{
+ register u32 CtrlReg;
+
+ /* enable caches only if they are disabled */
+#ifdef __GNUC__
+ CtrlReg = mfcp(XREG_CP15_SYS_CONTROL);
+#elif defined (__ICCARM__)
+ mfcp(XREG_CP15_SYS_CONTROL, CtrlReg);
+#else
+ { volatile register u32 Reg __asm(XREG_CP15_SYS_CONTROL);
+ CtrlReg = Reg; }
+#endif
+ if ((CtrlReg & (XREG_CP15_CONTROL_I_BIT)) != 0U) {
+ return;
+ }
+
+ /* invalidate the instruction cache */
+ mtcp(XREG_CP15_INVAL_IC_POU, 0U);
+
+ /* enable the instruction cache */
+ CtrlReg |= (XREG_CP15_CONTROL_I_BIT);
+
+ mtcp(XREG_CP15_SYS_CONTROL, CtrlReg);
+}
+
+/****************************************************************************/
+/**
+* @brief Disable level 1 the instruction cache.
+*
+* @param None.
+*
+* @return None.
+*
+* @note None.
+*
+****************************************************************************/
+void Xil_L1ICacheDisable(void)
+{
+ register u32 CtrlReg;
+
+ dsb();
+
+ /* invalidate the instruction cache */
+ mtcp(XREG_CP15_INVAL_IC_POU, 0U);
+
+ /* disable the instruction cache */
+#ifdef __GNUC__
+ CtrlReg = mfcp(XREG_CP15_SYS_CONTROL);
+#elif defined (__ICCARM__)
+ mfcp(XREG_CP15_SYS_CONTROL, CtrlReg);
+#else
+ { volatile register u32 Reg __asm(XREG_CP15_SYS_CONTROL);
+ CtrlReg = Reg; }
+#endif
+ CtrlReg &= ~(XREG_CP15_CONTROL_I_BIT);
+
+ mtcp(XREG_CP15_SYS_CONTROL, CtrlReg);
+}
+
+/****************************************************************************/
+/**
+* @brief Invalidate the entire level 1 instruction cache.
+*
+* @param None.
+*
+* @return None.
+*
+* @note None.
+*
+****************************************************************************/
+void Xil_L1ICacheInvalidate(void)
+{
+ mtcp(XREG_CP15_CACHE_SIZE_SEL, 1U);
+ /* invalidate the instruction cache */
+ mtcp(XREG_CP15_INVAL_IC_POU, 0U);
+
+ /* Wait for L1 invalidate to complete */
+ dsb();
+}
+
+/****************************************************************************/
+/**
+* @brief Invalidate a level 1 instruction cache line. If the instruction
+* specified by the address is cached by the instruction cache, the
+* cacheline containing that instruction is invalidated.
+*
+* @param adr: 32bit address of the instruction to be invalidated.
+*
+* @return None.
+*
+* @note The bottom 5 bits are set to 0, forced by architecture.
+*
+****************************************************************************/
+void Xil_L1ICacheInvalidateLine(u32 adr)
+{
+ mtcp(XREG_CP15_CACHE_SIZE_SEL, 1U);
+ mtcp(XREG_CP15_INVAL_IC_LINE_MVA_POU, (adr & (~0x1FU)));
+
+ /* Wait for L1 invalidate to complete */
+ dsb();
+}
+
+/****************************************************************************/
+/**
+* @brief Invalidate the level 1 instruction cache for the given address
+* range. If the instrucions specified by the address range are cached
+* by the instruction cache, the cacheline containing those bytes are
+* invalidated.
+*
+* @param adr: 32bit start address of the range to be invalidated.
+* @param len: Length of the range to be invalidated in bytes.
+*
+* @return None.
+*
+* @note None.
+*
+****************************************************************************/
+void Xil_L1ICacheInvalidateRange(u32 adr, u32 len)
+{
+ u32 LocalAddr = adr;
+ const u32 cacheline = 32U;
+ u32 end;
+ u32 currmask;
+
+ currmask = mfcpsr();
+ mtcpsr(currmask | IRQ_FIQ_MASK);
+
+ if (len != 0U) {
+ /* Back the starting address up to the start of a cache line
+ * perform cache operations until adr+len
+ */
+ end = LocalAddr + len;
+ LocalAddr = LocalAddr & ~(cacheline - 1U);
+
+ /* Select cache L0 I-cache in CSSR */
+ mtcp(XREG_CP15_CACHE_SIZE_SEL, 1U);
+
+ while (LocalAddr < end) {
+
+#if defined (__GNUC__) || defined (__ICCARM__)
+ asm_cp15_inval_ic_line_mva_pou(LocalAddr);
+#else
+ { volatile register u32 Reg
+ __asm(XREG_CP15_INVAL_IC_LINE_MVA_POU);
+ Reg = LocalAddr; }
+#endif
+ LocalAddr += cacheline;
+ }
+ }
+
+ /* Wait for L1 invalidate to complete */
+ dsb();
+ mtcpsr(currmask);
+}
+
+#ifndef USE_AMP
+/****************************************************************************/
+/**
+* @brief Enable the L2 cache.
+*
+* @param None.
+*
+* @return None.
+*
+* @note None.
+*
+****************************************************************************/
+void Xil_L2CacheEnable(void)
+{
+ register u32 L2CCReg;
+
+ L2CCReg = Xil_In32(XPS_L2CC_BASEADDR + XPS_L2CC_CNTRL_OFFSET);
+
+ /* only enable if L2CC is currently disabled */
+ if ((L2CCReg & 0x01U) == 0U) {
+ /* set up the way size and latencies */
+ L2CCReg = Xil_In32(XPS_L2CC_BASEADDR +
+ XPS_L2CC_AUX_CNTRL_OFFSET);
+ L2CCReg &= XPS_L2CC_AUX_REG_ZERO_MASK;
+ L2CCReg |= XPS_L2CC_AUX_REG_DEFAULT_MASK;
+ Xil_Out32(XPS_L2CC_BASEADDR + XPS_L2CC_AUX_CNTRL_OFFSET,
+ L2CCReg);
+ Xil_Out32(XPS_L2CC_BASEADDR + XPS_L2CC_TAG_RAM_CNTRL_OFFSET,
+ XPS_L2CC_TAG_RAM_DEFAULT_MASK);
+ Xil_Out32(XPS_L2CC_BASEADDR + XPS_L2CC_DATA_RAM_CNTRL_OFFSET,
+ XPS_L2CC_DATA_RAM_DEFAULT_MASK);
+
+ /* Clear the pending interrupts */
+ L2CCReg = Xil_In32(XPS_L2CC_BASEADDR +
+ XPS_L2CC_ISR_OFFSET);
+ Xil_Out32(XPS_L2CC_BASEADDR + XPS_L2CC_IAR_OFFSET, L2CCReg);
+
+ Xil_L2CacheInvalidate();
+ /* Enable the L2CC */
+ L2CCReg = Xil_In32(XPS_L2CC_BASEADDR +
+ XPS_L2CC_CNTRL_OFFSET);
+ Xil_Out32(XPS_L2CC_BASEADDR + XPS_L2CC_CNTRL_OFFSET,
+ (L2CCReg | (0x01U)));
+
+ Xil_L2CacheSync();
+ /* synchronize the processor */
+ dsb();
+
+ }
+}
+
+/****************************************************************************/
+/**
+* @brief Disable the L2 cache.
+*
+* @param None.
+*
+* @return None.
+*
+* @note None.
+*
+****************************************************************************/
+void Xil_L2CacheDisable(void)
+{
+ register u32 L2CCReg;
+
+ L2CCReg = Xil_In32(XPS_L2CC_BASEADDR + XPS_L2CC_CNTRL_OFFSET);
+
+ if((L2CCReg & 0x1U) != 0U) {
+
+ /* Clean and Invalidate L2 Cache */
+ Xil_L2CacheFlush();
+
+ /* Disable the L2CC */
+ L2CCReg = Xil_In32(XPS_L2CC_BASEADDR + XPS_L2CC_CNTRL_OFFSET);
+ Xil_Out32(XPS_L2CC_BASEADDR + XPS_L2CC_CNTRL_OFFSET,
+ (L2CCReg & (~0x01U)));
+ /* Wait for the cache operations to complete */
+
+ dsb();
+ }
+}
+
+/*****************************************************************************/
+/**
+* @brief Invalidate the entire level 2 cache.
+*
+* @param None.
+*
+* @return None.
+*
+* @note None.
+*
+****************************************************************************/
+void Xil_L2CacheInvalidate(void)
+{
+ #ifdef __GNUC__
+ u32 stack_start,stack_end,stack_size;
+ register u32 L2CCReg;
+ stack_end = (u32)&_stack_end;
+ stack_start = (u32)&__undef_stack;
+ stack_size=stack_start-stack_end;
+
+ /* Check for the cache status. If cache is enabled, then only
+ * flush stack memory to save return address. If cache is disabled,
+ * don't flush anything as it might result in flushing stale date into
+ * memory which is undesirable.
+ */
+ L2CCReg = Xil_In32(XPS_L2CC_BASEADDR + XPS_L2CC_CNTRL_OFFSET);
+ if ((L2CCReg & 0x01U) != 0U) {
+ /*Flush stack memory to save return address*/
+ Xil_DCacheFlushRange(stack_end, stack_size);
+ }
+
+ #endif
+ u32 ResultDCache;
+ /* Invalidate the caches */
+ Xil_Out32(XPS_L2CC_BASEADDR + XPS_L2CC_CACHE_INVLD_WAY_OFFSET,
+ 0x0000FFFFU);
+ ResultDCache = Xil_In32(XPS_L2CC_BASEADDR + XPS_L2CC_CACHE_INVLD_WAY_OFFSET)
+ & 0x0000FFFFU;
+ while(ResultDCache != (u32)0U) {
+ ResultDCache = Xil_In32(XPS_L2CC_BASEADDR + XPS_L2CC_CACHE_INVLD_WAY_OFFSET)
+ & 0x0000FFFFU;
+ }
+
+ /* Wait for the invalidate to complete */
+ Xil_L2CacheSync();
+
+ /* synchronize the processor */
+ dsb();
+}
+
+/*****************************************************************************/
+/**
+* @brief Invalidate a level 2 cache line. If the byte specified by the
+* address (adr) is cached by the Data cache, the cacheline containing
+* that byte is invalidated. If the cacheline is modified (dirty),
+* the modified contents are lost and are NOT written to system memory
+* before the line is invalidated.
+*
+* @param adr: 32bit address of the data/instruction to be invalidated.
+*
+* @return None.
+*
+* @note The bottom 4 bits are set to 0, forced by architecture.
+*
+****************************************************************************/
+void Xil_L2CacheInvalidateLine(u32 adr)
+{
+ Xil_Out32(XPS_L2CC_BASEADDR + XPS_L2CC_CACHE_INVLD_PA_OFFSET, (u32)adr);
+ /* synchronize the processor */
+ dsb();
+}
+
+/****************************************************************************/
+/**
+* @brief Invalidate the level 2 cache for the given address range.
+* If the bytes specified by the address range are cached by the L2
+* cache, the cacheline containing those bytes are invalidated. If the
+* cachelines are modified (dirty), the modified contents are lost and
+* are NOT written to system memory before the lines are invalidated.
+*
+* @param adr: 32bit start address of the range to be invalidated.
+* @param len: Length of the range to be invalidated in bytes.
+*
+* @return None.
+*
+* @note None.
+*
+****************************************************************************/
+void Xil_L2CacheInvalidateRange(u32 adr, u32 len)
+{
+ u32 LocalAddr = adr;
+ const u32 cacheline = 32U;
+ u32 end;
+ volatile u32 *L2CCOffset = (volatile u32 *)(XPS_L2CC_BASEADDR +
+ XPS_L2CC_CACHE_INVLD_PA_OFFSET);
+
+ u32 currmask;
+
+ currmask = mfcpsr();
+ mtcpsr(currmask | IRQ_FIQ_MASK);
+
+ if (len != 0U) {
+ /* Back the starting address up to the start of a cache line
+ * perform cache operations until adr+len
+ */
+ end = LocalAddr + len;
+ LocalAddr = LocalAddr & ~(cacheline - 1U);
+
+ /* Disable Write-back and line fills */
+ Xil_L2WriteDebugCtrl(0x3U);
+
+ while (LocalAddr < end) {
+ *L2CCOffset = LocalAddr;
+ Xil_L2CacheSync();
+ LocalAddr += cacheline;
+ }
+
+ /* Enable Write-back and line fills */
+ Xil_L2WriteDebugCtrl(0x0U);
+ }
+
+ /* synchronize the processor */
+ dsb();
+ mtcpsr(currmask);
+}
+
+/****************************************************************************/
+/**
+* @brief Flush the entire level 2 cache.
+*
+* @param None.
+*
+* @return None.
+*
+* @note None.
+*
+****************************************************************************/
+void Xil_L2CacheFlush(void)
+{
+ u32 ResultL2Cache;
+
+ /* Flush the caches */
+
+ /* Disable Write-back and line fills */
+ Xil_L2WriteDebugCtrl(0x3U);
+
+ Xil_Out32(XPS_L2CC_BASEADDR + XPS_L2CC_CACHE_INV_CLN_WAY_OFFSET,
+ 0x0000FFFFU);
+ ResultL2Cache = Xil_In32(XPS_L2CC_BASEADDR + XPS_L2CC_CACHE_INV_CLN_WAY_OFFSET)
+ & 0x0000FFFFU;
+
+ while(ResultL2Cache != (u32)0U) {
+ ResultL2Cache = Xil_In32(XPS_L2CC_BASEADDR + XPS_L2CC_CACHE_INV_CLN_WAY_OFFSET)
+ & 0x0000FFFFU;
+ }
+
+ Xil_L2CacheSync();
+ /* Enable Write-back and line fills */
+ Xil_L2WriteDebugCtrl(0x0U);
+
+ /* synchronize the processor */
+ dsb();
+}
+
+/****************************************************************************/
+/**
+* @brief Flush a level 2 cache line. If the byte specified by the address
+* (adr) is cached by the L2 cache, the cacheline containing that
+* byte is invalidated. If the cacheline is modified (dirty), the
+* entire contents of the cacheline are written to system memory
+* before the line is invalidated.
+*
+* @param adr: 32bit address of the data/instruction to be flushed.
+*
+* @return None.
+*
+* @note The bottom 4 bits are set to 0, forced by architecture.
+*
+****************************************************************************/
+void Xil_L2CacheFlushLine(u32 adr)
+{
+#ifdef CONFIG_PL310_ERRATA_588369
+ Xil_Out32(XPS_L2CC_BASEADDR + XPS_L2CC_CACHE_CLEAN_PA_OFFSET, adr);
+ Xil_Out32(XPS_L2CC_BASEADDR + XPS_L2CC_CACHE_INVLD_PA_OFFSET, adr);
+#else
+ Xil_Out32(XPS_L2CC_BASEADDR + XPS_L2CC_CACHE_INV_CLN_PA_OFFSET, adr);
+#endif
+ /* synchronize the processor */
+ dsb();
+}
+
+/****************************************************************************/
+/**
+* @brief Flush the level 2 cache for the given address range.
+* If the bytes specified by the address range are cached by the L2
+* cache, the cacheline containing those bytes are invalidated. If the
+* cachelines are modified (dirty), they are written to the system
+* memory before the lines are invalidated.
+*
+* @param adr: 32bit start address of the range to be flushed.
+* @param len: Length of the range to be flushed in bytes.
+*
+* @return None.
+*
+* @note None.
+*
+****************************************************************************/
+void Xil_L2CacheFlushRange(u32 adr, u32 len)
+{
+ u32 LocalAddr = adr;
+ const u32 cacheline = 32U;
+ u32 end;
+ volatile u32 *L2CCOffset = (volatile u32 *)(XPS_L2CC_BASEADDR +
+ XPS_L2CC_CACHE_INV_CLN_PA_OFFSET);
+
+ u32 currmask;
+
+ currmask = mfcpsr();
+ mtcpsr(currmask | IRQ_FIQ_MASK);
+ if (len != 0U) {
+ /* Back the starting address up to the start of a cache line
+ * perform cache operations until adr+len
+ */
+ end = LocalAddr + len;
+ LocalAddr = LocalAddr & ~(cacheline - 1U);
+
+ /* Disable Write-back and line fills */
+ Xil_L2WriteDebugCtrl(0x3U);
+
+ while (LocalAddr < end) {
+ *L2CCOffset = LocalAddr;
+ Xil_L2CacheSync();
+ LocalAddr += cacheline;
+ }
+
+ /* Enable Write-back and line fills */
+ Xil_L2WriteDebugCtrl(0x0U);
+ }
+ /* synchronize the processor */
+ dsb();
+ mtcpsr(currmask);
+}
+
+/****************************************************************************/
+/**
+* @brief Store a level 2 cache line. If the byte specified by the address
+* (adr) is cached by the L2 cache and the cacheline is modified
+* (dirty), the entire contents of the cacheline are written to
+* system memory. After the store completes, the cacheline is marked
+* as unmodified (not dirty).
+*
+* @param adr: 32bit address of the data/instruction to be stored.
+*
+* @return None.
+*
+* @note The bottom 4 bits are set to 0, forced by architecture.
+*
+****************************************************************************/
+void Xil_L2CacheStoreLine(u32 adr)
+{
+ Xil_Out32(XPS_L2CC_BASEADDR + XPS_L2CC_CACHE_CLEAN_PA_OFFSET, adr);
+ /* synchronize the processor */
+ dsb();
+}
+#endif
diff --git a/hello_world/sw/app/embeddedsw-master/xil_cache.h b/hello_world/sw/app/embeddedsw-master/xil_cache.h
new file mode 100644
index 0000000..abc4346
--- /dev/null
+++ b/hello_world/sw/app/embeddedsw-master/xil_cache.h
@@ -0,0 +1,96 @@
+/******************************************************************************
+* Copyright (c) 2010 - 2020 Xilinx, Inc. All rights reserved.
+* SPDX-License-Identifier: MIT
+******************************************************************************/
+
+/*****************************************************************************/
+/**
+*
+* @file xil_cache.h
+*
+* @addtogroup a9_cache_apis Cortex A9 Processor Cache Functions
+*
+* Cache functions provide access to cache related operations such as flush
+* and invalidate for instruction and data caches. It gives option to perform
+* the cache operations on a single cacheline, a range of memory and an entire
+* cache.
+*
+* @{
+*
+* <pre>
+* MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ----- ---- -------- -----------------------------------------------
+* 1.00a ecm 01/29/10 First release
+* 3.04a sdm 01/02/12 Remove redundant dsb/dmb instructions in cache maintenance
+* APIs.
+* 6.8 aru 09/06/18 Removed compilation warnings for ARMCC toolchain.
+* </pre>
+*
+******************************************************************************/
+#ifndef XIL_CACHE_H
+#define XIL_CACHE_H
+
+#include "xil_types.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#ifdef __GNUC__
+
+#define asm_cp15_inval_dc_line_mva_poc(param) __asm__ __volatile__("mcr " \
+ XREG_CP15_INVAL_DC_LINE_MVA_POC :: "r" (param));
+
+#define asm_cp15_clean_inval_dc_line_mva_poc(param) __asm__ __volatile__("mcr " \
+ XREG_CP15_CLEAN_INVAL_DC_LINE_MVA_POC :: "r" (param));
+
+#define asm_cp15_inval_ic_line_mva_pou(param) __asm__ __volatile__("mcr " \
+ XREG_CP15_INVAL_IC_LINE_MVA_POU :: "r" (param));
+
+#define asm_cp15_inval_dc_line_sw(param) __asm__ __volatile__("mcr " \
+ XREG_CP15_INVAL_DC_LINE_SW :: "r" (param));
+
+#define asm_cp15_clean_inval_dc_line_sw(param) __asm__ __volatile__("mcr " \
+ XREG_CP15_CLEAN_INVAL_DC_LINE_SW :: "r" (param));
+
+#elif defined (__ICCARM__)
+
+#define asm_cp15_inval_dc_line_mva_poc(param) __asm volatile ("mcr " \
+ XREG_CP15_INVAL_DC_LINE_MVA_POC :: "r" (param));
+
+#define asm_cp15_clean_inval_dc_line_mva_poc(param) __asm volatile ("mcr " \
+ XREG_CP15_CLEAN_INVAL_DC_LINE_MVA_POC :: "r" (param));
+
+#define asm_cp15_inval_ic_line_mva_pou(param) __asm volatile ("mcr " \
+ XREG_CP15_INVAL_IC_LINE_MVA_POU :: "r" (param));
+
+#define asm_cp15_inval_dc_line_sw(param) __asm volatile ("mcr " \
+ XREG_CP15_INVAL_DC_LINE_SW :: "r" (param));
+
+#define asm_cp15_clean_inval_dc_line_sw(param) __asm volatile ("mcr " \
+ XREG_CP15_CLEAN_INVAL_DC_LINE_SW :: "r" (param));
+
+#endif
+
+void Xil_DCacheEnable(void);
+void Xil_DCacheDisable(void);
+void Xil_DCacheInvalidate(void);
+void Xil_DCacheInvalidateRange(INTPTR adr, u32 len);
+void Xil_DCacheFlush(void);
+void Xil_DCacheFlushRange(INTPTR adr, u32 len);
+
+void Xil_ICacheEnable(void);
+void Xil_ICacheDisable(void);
+void Xil_ICacheInvalidate(void);
+void Xil_ICacheInvalidateRange(INTPTR adr, u32 len);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
+/**
+* @} End of "addtogroup a9_cache_apis".
+*/
diff --git a/hello_world/sw/app/embeddedsw-master/xil_cache_l.h b/hello_world/sw/app/embeddedsw-master/xil_cache_l.h
new file mode 100644
index 0000000..21c8ced
--- /dev/null
+++ b/hello_world/sw/app/embeddedsw-master/xil_cache_l.h
@@ -0,0 +1,75 @@
+/******************************************************************************
+* Copyright (c) 2010 - 2020 Xilinx, Inc. All rights reserved.
+* SPDX-License-Identifier: MIT
+******************************************************************************/
+
+/*****************************************************************************/
+/**
+*
+* @file xil_cache_l.h
+*
+* Contains L1 and L2 specific functions for the ARM cache functionality
+* used by xcache.c. This functionality is being made available here for
+* more sophisticated users.
+*
+* @addtogroup a9_cache_apis
+* @{
+* <pre>
+* MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ----- ---- -------- -----------------------------------------------
+* 1.00a ecm 01/24/10 First release
+* 6.8 aru 09/06/18 Removed compilation warnings for ARMCC toolchain.
+* </pre>
+*
+******************************************************************************/
+#ifndef XIL_CACHE_MACH_H
+#define XIL_CACHE_MACH_H
+
+#include "xil_types.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/************************** Function Prototypes ******************************/
+
+void Xil_DCacheInvalidateLine(u32 adr);
+void Xil_DCacheFlushLine(u32 adr);
+void Xil_DCacheStoreLine(u32 adr);
+void Xil_ICacheInvalidateLine(u32 adr);
+
+void Xil_L1DCacheEnable(void);
+void Xil_L1DCacheDisable(void);
+void Xil_L1DCacheInvalidate(void);
+void Xil_L1DCacheInvalidateLine(u32 adr);
+void Xil_L1DCacheInvalidateRange(u32 adr, u32 len);
+void Xil_L1DCacheFlush(void);
+void Xil_L1DCacheFlushLine(u32 adr);
+void Xil_L1DCacheFlushRange(u32 adr, u32 len);
+void Xil_L1DCacheStoreLine(u32 adr);
+
+void Xil_L1ICacheEnable(void);
+void Xil_L1ICacheDisable(void);
+void Xil_L1ICacheInvalidate(void);
+void Xil_L1ICacheInvalidateLine(u32 adr);
+void Xil_L1ICacheInvalidateRange(u32 adr, u32 len);
+
+void Xil_L2CacheEnable(void);
+void Xil_L2CacheDisable(void);
+void Xil_L2CacheInvalidate(void);
+void Xil_L2CacheInvalidateLine(u32 adr);
+void Xil_L2CacheInvalidateRange(u32 adr, u32 len);
+void Xil_L2CacheFlush(void);
+void Xil_L2CacheFlushLine(u32 adr);
+void Xil_L2CacheFlushRange(u32 adr, u32 len);
+void Xil_L2CacheStoreLine(u32 adr);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
+/**
+* @} End of "addtogroup a9_cache_apis".
+*/
diff --git a/hello_world/sw/app/embeddedsw-master/xil_errata.h b/hello_world/sw/app/embeddedsw-master/xil_errata.h
new file mode 100644
index 0000000..8ca2380
--- /dev/null
+++ b/hello_world/sw/app/embeddedsw-master/xil_errata.h
@@ -0,0 +1,105 @@
+/******************************************************************************
+* Copyright (c) 2013 - 2020 Xilinx, Inc. All rights reserved.
+* SPDX-License-Identifier: MIT
+******************************************************************************/
+
+/*****************************************************************************/
+/**
+*
+* @file xil_errata.h
+*
+* @addtogroup a9_errata Cortex A9 Processor and pl310 Errata Support
+* @{
+* Various ARM errata are handled in the standalone BSP. The implementation for
+* errata handling follows ARM guidelines and is based on the open source Linux
+* support for these errata.
+*
+* @note
+* The errata handling is enabled by default. To disable handling of all the
+* errata globally, un-define the macro ENABLE_ARM_ERRATA in xil_errata.h. To
+* disable errata on a per-erratum basis, un-define relevant macros in
+* xil_errata.h.
+*
+* <pre>
+* MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ----- ---- -------- -----------------------------------------------
+* 1.00a srt 04/18/13 First release
+* 6.6 mus 12/07/17 Removed errata 753970, It fixes CR#989132.
+* </pre>
+*
+******************************************************************************/
+#ifndef XIL_ERRATA_H
+#define XIL_ERRATA_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * @name errata_definitions
+ *
+ * The errata conditions handled in the standalone BSP are listed below
+ * @{
+ */
+
+#define ENABLE_ARM_ERRATA 1
+
+#ifdef ENABLE_ARM_ERRATA
+
+/**
+ * Errata No: 742230
+ * Description: DMB operation may be faulty
+ */
+#define CONFIG_ARM_ERRATA_742230 1
+
+/**
+ * Errata No: 743622
+ * Description: Faulty hazard checking in the Store Buffer may lead
+ * to data corruption.
+ */
+#define CONFIG_ARM_ERRATA_743622 1
+
+/**
+ * Errata No: 775420
+ * Description: A data cache maintenance operation which aborts,
+ * might lead to deadlock
+ */
+#define CONFIG_ARM_ERRATA_775420 1
+
+/**
+ * Errata No: 794073
+ * Description: Speculative instruction fetches with MMU disabled
+ * might not comply with architectural requirements
+ */
+#define CONFIG_ARM_ERRATA_794073 1
+
+
+/** PL310 L2 Cache Errata */
+
+/**
+ * Errata No: 588369
+ * Description: Clean & Invalidate maintenance operations do not
+ * invalidate clean lines
+ */
+#define CONFIG_PL310_ERRATA_588369 1
+
+/**
+ * Errata No: 727915
+ * Description: Background Clean and Invalidate by Way operation
+ * can cause data corruption
+ */
+#define CONFIG_PL310_ERRATA_727915 1
+
+/*@}*/
+#endif /* ENABLE_ARM_ERRATA */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* XIL_ERRATA_H */
+/**
+* @} End of "addtogroup a9_errata".
+*/
diff --git a/hello_world/sw/app/embeddedsw-master/xil_exception.h b/hello_world/sw/app/embeddedsw-master/xil_exception.h
new file mode 100644
index 0000000..ea7b749
--- /dev/null
+++ b/hello_world/sw/app/embeddedsw-master/xil_exception.h
@@ -0,0 +1,377 @@
+/******************************************************************************
+* Copyright (c) 2015 - 2020 Xilinx, Inc. All rights reserved.
+* SPDX-License-Identifier: MIT
+******************************************************************************/
+
+/*****************************************************************************/
+/**
+*
+* @file xil_exception.h
+*
+* This header file contains ARM Cortex A53,A9,R5 specific exception related APIs.
+* For exception related functions that can be used across all Xilinx supported
+* processors, please use xil_exception.h.
+*
+* @addtogroup arm_exception_apis ARM Processor Exception Handling
+* @{
+* ARM processors specific exception related APIs for cortex A53,A9 and R5 can
+* utilized for enabling/disabling IRQ, registering/removing handler for
+* exceptions or initializing exception vector table with null handler.
+*
+* <pre>
+* MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ----- -------- -------- -----------------------------------------------
+* 5.2 pkp 28/05/15 First release
+* 6.0 mus 27/07/16 Consolidated file for a53,a9 and r5 processors
+* 6.7 mna 26/04/18 Add API Xil_GetExceptionRegisterHandler.
+* 6.7 asa 18/05/18 Update signature of API Xil_GetExceptionRegisterHandler.
+* 7.0 mus 01/03/19 Tweak Xil_ExceptionEnableMask and
+* Xil_ExceptionDisableMask macros to support legacy
+* examples for Cortexa72 EL3 exception level.
+* 7.3 mus 04/15/20 Added Xil_EnableNestedInterrupts and
+* Xil_DisableNestedInterrupts macros for ARMv8.
+* For Cortexa72, these macro's would not be supported
+* at EL3, as Cortexa72 is using GIC-500(GICv3), which
+* triggeres only FIQ at EL3. Fix for CR#1062506
+* </pre>
+*
+******************************************************************************/
+
+#ifndef XIL_EXCEPTION_H /* prevent circular inclusions */
+#define XIL_EXCEPTION_H /* by using protection macros */
+
+/***************************** Include Files ********************************/
+
+#include "xil_types.h"
+#include "xpseudo_asm.h"
+#include "bspconfig.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/************************** Constant Definitions ****************************/
+
+#define XIL_EXCEPTION_FIQ XREG_CPSR_FIQ_ENABLE
+#define XIL_EXCEPTION_IRQ XREG_CPSR_IRQ_ENABLE
+#define XIL_EXCEPTION_ALL (XREG_CPSR_FIQ_ENABLE | XREG_CPSR_IRQ_ENABLE)
+
+#define XIL_EXCEPTION_ID_FIRST 0U
+#if defined (__aarch64__)
+#define XIL_EXCEPTION_ID_SYNC_INT 1U
+#define XIL_EXCEPTION_ID_IRQ_INT 2U
+#define XIL_EXCEPTION_ID_FIQ_INT 3U
+#define XIL_EXCEPTION_ID_SERROR_ABORT_INT 4U
+#define XIL_EXCEPTION_ID_LAST 5U
+#else
+#define XIL_EXCEPTION_ID_RESET 0U
+#define XIL_EXCEPTION_ID_UNDEFINED_INT 1U
+#define XIL_EXCEPTION_ID_SWI_INT 2U
+#define XIL_EXCEPTION_ID_PREFETCH_ABORT_INT 3U
+#define XIL_EXCEPTION_ID_DATA_ABORT_INT 4U
+#define XIL_EXCEPTION_ID_IRQ_INT 5U
+#define XIL_EXCEPTION_ID_FIQ_INT 6U
+#define XIL_EXCEPTION_ID_LAST 6U
+#endif
+
+/*
+ * XIL_EXCEPTION_ID_INT is defined for all Xilinx processors.
+ */
+#if defined (versal) && !defined(ARMR5) && EL3
+#define XIL_EXCEPTION_ID_INT XIL_EXCEPTION_ID_FIQ_INT
+#else
+#define XIL_EXCEPTION_ID_INT XIL_EXCEPTION_ID_IRQ_INT
+#endif
+
+/**************************** Type Definitions ******************************/
+
+/**
+ * This typedef is the exception handler function.
+ */
+typedef void (*Xil_ExceptionHandler)(void *data);
+typedef void (*Xil_InterruptHandler)(void *data);
+
+/***************** Macros (Inline Functions) Definitions ********************/
+
+/****************************************************************************/
+/**
+* @brief Enable Exceptions.
+*
+* @param Mask: Value for enabling the exceptions.
+*
+* @return None.
+*
+* @note If bit is 0, exception is enabled.
+* C-Style signature: void Xil_ExceptionEnableMask(Mask)
+*
+******************************************************************************/
+#if defined (versal) && !defined(ARMR5) && EL3
+/*
+ * Cortexa72 processor in versal is coupled with GIC-500, and GIC-500 supports
+ * only FIQ at EL3. Hence, tweaking this macro to always enable FIQ
+ * ignoring argument passed by user.
+ */
+#define Xil_ExceptionEnableMask(Mask) \
+ mtcpsr(mfcpsr() & ~ ((XIL_EXCEPTION_FIQ) & XIL_EXCEPTION_ALL))
+#elif defined (__GNUC__) || defined (__ICCARM__)
+#define Xil_ExceptionEnableMask(Mask) \
+ mtcpsr(mfcpsr() & ~ ((Mask) & XIL_EXCEPTION_ALL))
+#else
+#define Xil_ExceptionEnableMask(Mask) \
+ { \
+ register u32 Reg __asm("cpsr"); \
+ mtcpsr((Reg) & (~((Mask) & XIL_EXCEPTION_ALL))); \
+ }
+#endif
+/****************************************************************************/
+/**
+* @brief Enable the IRQ exception.
+*
+* @return None.
+*
+* @note None.
+*
+******************************************************************************/
+#if defined (versal) && !defined(ARMR5) && EL3
+#define Xil_ExceptionEnable() \
+ Xil_ExceptionEnableMask(XIL_EXCEPTION_FIQ)
+#else
+#define Xil_ExceptionEnable() \
+ Xil_ExceptionEnableMask(XIL_EXCEPTION_IRQ)
+#endif
+
+/****************************************************************************/
+/**
+* @brief Disable Exceptions.
+*
+* @param Mask: Value for disabling the exceptions.
+*
+* @return None.
+*
+* @note If bit is 1, exception is disabled.
+* C-Style signature: Xil_ExceptionDisableMask(Mask)
+*
+******************************************************************************/
+#if defined (versal) && !defined(ARMR5) && EL3
+/*
+ * Cortexa72 processor in versal is coupled with GIC-500, and GIC-500 supports
+ * only FIQ at EL3. Hence, tweaking this macro to always disable FIQ
+ * ignoring argument passed by user.
+ */
+#define Xil_ExceptionDisableMask(Mask) \
+ mtcpsr(mfcpsr() | ((XIL_EXCEPTION_FIQ) & XIL_EXCEPTION_ALL))
+#elif defined (__GNUC__) || defined (__ICCARM__)
+#define Xil_ExceptionDisableMask(Mask) \
+ mtcpsr(mfcpsr() | ((Mask) & XIL_EXCEPTION_ALL))
+#else
+#define Xil_ExceptionDisableMask(Mask) \
+ { \
+ register u32 Reg __asm("cpsr"); \
+ mtcpsr((Reg) | ((Mask) & XIL_EXCEPTION_ALL)); \
+ }
+#endif
+/****************************************************************************/
+/**
+* Disable the IRQ exception.
+*
+* @return None.
+*
+* @note None.
+*
+******************************************************************************/
+#define Xil_ExceptionDisable() \
+ Xil_ExceptionDisableMask(XIL_EXCEPTION_IRQ)
+
+#if ( defined (PLATFORM_ZYNQMP) && EL3 )
+/****************************************************************************/
+/**
+* @brief Enable nested interrupts by clearing the I bit in DAIF.This
+* macro is defined for Cortex-A53 64 bit mode BSP configured to run
+* at EL3.. However,it is not defined for Versal Cortex-A72 BSP
+* configured to run at EL3. Reason is, Cortex-A72 is coupled
+* with GIC-500(GICv3 specifications) and it triggers only FIQ at EL3.
+*
+* @return None.
+*
+* @note This macro is supposed to be used from interrupt handlers. In the
+* interrupt handler the interrupts are disabled by default (I bit
+* is set as 1). To allow nesting of interrupts, this macro should be
+* used. It clears the I bit. Once that bit is cleared and provided the
+* preemption of interrupt conditions are met in the GIC, nesting of
+* interrupts will start happening.
+* Caution: This macro must be used with caution. Before calling this
+* macro, the user must ensure that the source of the current IRQ
+* is appropriately cleared. Otherwise, as soon as we clear the I
+* bit, there can be an infinite loop of interrupts with an
+* eventual crash (all the stack space getting consumed).
+******************************************************************************/
+#define Xil_EnableNestedInterrupts() \
+ __asm__ __volatile__ ("mrs X1, ELR_EL3"); \
+ __asm__ __volatile__ ("mrs X2, SPSR_EL3"); \
+ __asm__ __volatile__ ("stp X1,X2, [sp,#-0x10]!"); \
+ __asm__ __volatile__ ("mrs X1, DAIF"); \
+ __asm__ __volatile__ ("bic X1,X1,#(0x1<<7)"); \
+ __asm__ __volatile__ ("msr DAIF, X1"); \
+
+/****************************************************************************/
+/**
+* @brief Disable the nested interrupts by setting the I bit in DAIF. This
+* macro is defined for Cortex-A53 64 bit mode BSP configured to run
+* at EL3.
+*
+* @return None.
+*
+* @note This macro is meant to be called in the interrupt service routines.
+* This macro cannot be used independently. It can only be used when
+* nesting of interrupts have been enabled by using the macro
+* Xil_EnableNestedInterrupts(). In a typical flow, the user first
+* calls the Xil_EnableNestedInterrupts in the ISR at the appropriate
+* point. The user then must call this macro before exiting the interrupt
+* service routine. This macro puts the ARM back in IRQ mode and
+* hence sets back the I bit.
+******************************************************************************/
+#define Xil_DisableNestedInterrupts() \
+ __asm__ __volatile__ ("ldp X1,X2, [sp,#0x10]!"); \
+ __asm__ __volatile__ ("msr ELR_EL3, X1"); \
+ __asm__ __volatile__ ("msr SPSR_EL3, X2"); \
+ __asm__ __volatile__ ("mrs X1, DAIF"); \
+ __asm__ __volatile__ ("orr X1, X1, #(0x1<<7)"); \
+ __asm__ __volatile__ ("msr DAIF, X1"); \
+
+#elif EL1_NONSECURE
+/****************************************************************************/
+/**
+* @brief Enable nested interrupts by clearing the I bit in DAIF.This
+* macro is defined for Cortex-A53 64 bit mode and Cortex-A72 64 bit
+* BSP configured to run at EL1 NON SECURE
+*
+* @return None.
+*
+* @note This macro is supposed to be used from interrupt handlers. In the
+* interrupt handler the interrupts are disabled by default (I bit
+* is set as 1). To allow nesting of interrupts, this macro should be
+* used. It clears the I bit. Once that bit is cleared and provided the
+* preemption of interrupt conditions are met in the GIC, nesting of
+* interrupts will start happening.
+* Caution: This macro must be used with caution. Before calling this
+* macro, the user must ensure that the source of the current IRQ
+* is appropriately cleared. Otherwise, as soon as we clear the I
+* bit, there can be an infinite loop of interrupts with an
+* eventual crash (all the stack space getting consumed).
+******************************************************************************/
+#define Xil_EnableNestedInterrupts() \
+ __asm__ __volatile__ ("mrs X1, ELR_EL1"); \
+ __asm__ __volatile__ ("mrs X2, SPSR_EL1"); \
+ __asm__ __volatile__ ("stp X1,X2, [sp,#-0x10]!"); \
+ __asm__ __volatile__ ("mrs X1, DAIF"); \
+ __asm__ __volatile__ ("bic X1,X1,#(0x1<<7)"); \
+ __asm__ __volatile__ ("msr DAIF, X1"); \
+
+/****************************************************************************/
+/**
+* @brief Disable the nested interrupts by setting the I bit in DAIF. This
+* macro is defined for Cortex-A53 64 bit mode and Cortex-A72 64 bit
+* BSP configured to run at EL1 NON SECURE
+*
+* @return None.
+*
+* @note This macro is meant to be called in the interrupt service routines.
+* This macro cannot be used independently. It can only be used when
+* nesting of interrupts have been enabled by using the macro
+* Xil_EnableNestedInterrupts(). In a typical flow, the user first
+* calls the Xil_EnableNestedInterrupts in the ISR at the appropriate
+* point. The user then must call this macro before exiting the interrupt
+* service routine. This macro puts the ARM back in IRQ mode and
+* hence sets back the I bit.
+******************************************************************************/
+#define Xil_DisableNestedInterrupts() \
+ __asm__ __volatile__ ("ldp X1,X2, [sp,#0x10]!"); \
+ __asm__ __volatile__ ("msr ELR_EL1, X1"); \
+ __asm__ __volatile__ ("msr SPSR_EL1, X2"); \
+ __asm__ __volatile__ ("mrs X1, DAIF"); \
+ __asm__ __volatile__ ("orr X1, X1, #(0x1<<7)"); \
+ __asm__ __volatile__ ("msr DAIF, X1"); \
+
+#elif (!defined (__aarch64__) && !defined (ARMA53_32))
+/****************************************************************************/
+/**
+* @brief Enable nested interrupts by clearing the I and F bits in CPSR. This
+* API is defined for cortex-a9 and cortex-r5.
+*
+* @return None.
+*
+* @note This macro is supposed to be used from interrupt handlers. In the
+* interrupt handler the interrupts are disabled by default (I and F
+* are 1). To allow nesting of interrupts, this macro should be
+* used. It clears the I and F bits by changing the ARM mode to
+* system mode. Once these bits are cleared and provided the
+* preemption of interrupt conditions are met in the GIC, nesting of
+* interrupts will start happening.
+* Caution: This macro must be used with caution. Before calling this
+* macro, the user must ensure that the source of the current IRQ
+* is appropriately cleared. Otherwise, as soon as we clear the I and
+* F bits, there can be an infinite loop of interrupts with an
+* eventual crash (all the stack space getting consumed).
+******************************************************************************/
+#define Xil_EnableNestedInterrupts() \
+ __asm__ __volatile__ ("stmfd sp!, {lr}"); \
+ __asm__ __volatile__ ("mrs lr, spsr"); \
+ __asm__ __volatile__ ("stmfd sp!, {lr}"); \
+ __asm__ __volatile__ ("msr cpsr_c, #0x1F"); \
+ __asm__ __volatile__ ("stmfd sp!, {lr}");
+/****************************************************************************/
+/**
+* @brief Disable the nested interrupts by setting the I and F bits. This API
+* is defined for cortex-a9 and cortex-r5.
+*
+* @return None.
+*
+* @note This macro is meant to be called in the interrupt service routines.
+* This macro cannot be used independently. It can only be used when
+* nesting of interrupts have been enabled by using the macro
+* Xil_EnableNestedInterrupts(). In a typical flow, the user first
+* calls the Xil_EnableNestedInterrupts in the ISR at the appropriate
+* point. The user then must call this macro before exiting the interrupt
+* service routine. This macro puts the ARM back in IRQ/FIQ mode and
+* hence sets back the I and F bits.
+******************************************************************************/
+#define Xil_DisableNestedInterrupts() \
+ __asm__ __volatile__ ("ldmfd sp!, {lr}"); \
+ __asm__ __volatile__ ("msr cpsr_c, #0x92"); \
+ __asm__ __volatile__ ("ldmfd sp!, {lr}"); \
+ __asm__ __volatile__ ("msr spsr_cxsf, lr"); \
+ __asm__ __volatile__ ("ldmfd sp!, {lr}"); \
+
+#endif
+/************************** Variable Definitions ****************************/
+
+/************************** Function Prototypes *****************************/
+
+extern void Xil_ExceptionRegisterHandler(u32 Exception_id,
+ Xil_ExceptionHandler Handler,
+ void *Data);
+
+extern void Xil_ExceptionRemoveHandler(u32 Exception_id);
+extern void Xil_GetExceptionRegisterHandler(u32 Exception_id,
+ Xil_ExceptionHandler *Handler, void **Data);
+
+extern void Xil_ExceptionInit(void);
+#if defined (__aarch64__)
+void Xil_SyncAbortHandler(void *CallBackRef);
+void Xil_SErrorAbortHandler(void *CallBackRef);
+#else
+extern void Xil_DataAbortHandler(void *CallBackRef);
+extern void Xil_PrefetchAbortHandler(void *CallBackRef);
+extern void Xil_UndefinedExceptionHandler(void *CallBackRef);
+#endif
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+
+#endif /* XIL_EXCEPTION_H */
+/**
+* @} End of "addtogroup arm_exception_apis".
+*/
diff --git a/hello_world/sw/app/embeddedsw-master/xil_io.h b/hello_world/sw/app/embeddedsw-master/xil_io.h
new file mode 100644
index 0000000..a10fd45
--- /dev/null
+++ b/hello_world/sw/app/embeddedsw-master/xil_io.h
@@ -0,0 +1,403 @@
+/******************************************************************************
+* Copyright (c) 2014 - 2020 Xilinx, Inc. All rights reserved.
+* SPDX-License-Identifier: MIT
+******************************************************************************/
+
+/*****************************************************************************/
+/**
+*
+* @file xil_io.h
+*
+* @addtogroup common_io_interfacing_apis Register IO interfacing APIs
+*
+* The xil_io.h file contains the interface for the general I/O component, which
+* encapsulates the Input/Output functions for the processors that do not
+* require any special I/O handling.
+*
+* @{
+* <pre>
+* MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ----- -------- -------- -----------------------------------------------
+* 5.00 pkp 05/29/14 First release
+* 6.00 mus 08/19/16 Remove checking of __LITTLE_ENDIAN__ flag for
+* ARM processors
+* 7.20 har 01/03/20 Added Xil_SecureOut32 for avoiding blindwrite for
+* CR-1049218
+* 7.30 kpt 09/21/20 Moved Xil_EndianSwap16 and Xil_EndianSwap32 to
+* xil_io.h and made them as static inline
+* am 10/13/20 Changed the return type of Xil_SecureOut32 function
+* from u32 to int
+*
+* </pre>
+******************************************************************************/
+
+#ifndef XIL_IO_H /* prevent circular inclusions */
+#define XIL_IO_H /* by using protection macros */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/***************************** Include Files *********************************/
+
+#include "xil_types.h"
+#include "xil_printf.h"
+#include "xstatus.h"
+
+#if defined (__MICROBLAZE__)
+#include "mb_interface.h"
+#else
+#include "xpseudo_asm.h"
+#endif
+
+/************************** Function Prototypes ******************************/
+#ifdef ENABLE_SAFETY
+extern u32 XStl_RegUpdate(u32 RegAddr, u32 RegVal);
+#endif
+
+/***************** Macros (Inline Functions) Definitions *********************/
+#if defined __GNUC__
+#if defined (__MICROBLAZE__)
+# define INST_SYNC mbar(0)
+# define DATA_SYNC mbar(1)
+# else
+# define SYNCHRONIZE_IO dmb()
+# define INST_SYNC isb()
+# define DATA_SYNC dsb()
+# endif
+#else
+# define SYNCHRONIZE_IO
+# define INST_SYNC
+# define DATA_SYNC
+# define INST_SYNC
+# define DATA_SYNC
+#endif
+
+#if defined (__GNUC__) || defined (__ICCARM__) || defined (__MICROBLAZE__)
+#define INLINE inline
+#else
+#define INLINE __inline
+#endif
+
+/*****************************************************************************/
+/**
+*
+* @brief Performs an input operation for a memory location by reading
+* from the specified address and returning the 8 bit Value read from
+* that address.
+*
+* @param Addr: contains the address to perform the input operation
+*
+* @return The 8 bit Value read from the specified input address.
+
+*
+******************************************************************************/
+static INLINE u8 Xil_In8(UINTPTR Addr)
+{
+ return *(volatile u8 *) Addr;
+}
+
+/*****************************************************************************/
+/**
+*
+* @brief Performs an input operation for a memory location by reading from
+* the specified address and returning the 16 bit Value read from that
+* address.
+*
+* @param Addr: contains the address to perform the input operation
+*
+* @return The 16 bit Value read from the specified input address.
+*
+******************************************************************************/
+static INLINE u16 Xil_In16(UINTPTR Addr)
+{
+ return *(volatile u16 *) Addr;
+}
+
+/*****************************************************************************/
+/**
+*
+* @brief Performs an input operation for a memory location by
+* reading from the specified address and returning the 32 bit Value
+* read from that address.
+*
+* @param Addr: contains the address to perform the input operation
+*
+* @return The 32 bit Value read from the specified input address.
+*
+******************************************************************************/
+static INLINE u32 Xil_In32(UINTPTR Addr)
+{
+ return *(volatile u32 *) Addr;
+}
+
+/*****************************************************************************/
+/**
+*
+* @brief Performs an input operation for a memory location by reading the
+* 64 bit Value read from that address.
+*
+*
+* @param Addr: contains the address to perform the input operation
+*
+* @return The 64 bit Value read from the specified input address.
+*
+******************************************************************************/
+static INLINE u64 Xil_In64(UINTPTR Addr)
+{
+ return *(volatile u64 *) Addr;
+}
+
+/*****************************************************************************/
+/**
+*
+* @brief Performs an output operation for an memory location by
+* writing the 8 bit Value to the the specified address.
+*
+* @param Addr: contains the address to perform the output operation
+* @param Value: contains the 8 bit Value to be written at the specified
+* address.
+*
+* @return None.
+*
+******************************************************************************/
+static INLINE void Xil_Out8(UINTPTR Addr, u8 Value)
+{
+ volatile u8 *LocalAddr = (volatile u8 *)Addr;
+ *LocalAddr = Value;
+}
+
+/*****************************************************************************/
+/**
+*
+* @brief Performs an output operation for a memory location by writing the
+* 16 bit Value to the the specified address.
+*
+* @param Addr contains the address to perform the output operation
+* @param Value contains the Value to be written at the specified address.
+*
+* @return None.
+*
+******************************************************************************/
+static INLINE void Xil_Out16(UINTPTR Addr, u16 Value)
+{
+ volatile u16 *LocalAddr = (volatile u16 *)Addr;
+ *LocalAddr = Value;
+}
+
+/*****************************************************************************/
+/**
+*
+* @brief Performs an output operation for a memory location by writing the
+* 32 bit Value to the the specified address.
+*
+* @param Addr contains the address to perform the output operation
+* @param Value contains the 32 bit Value to be written at the specified
+* address.
+*
+* @return None.
+*
+******************************************************************************/
+static INLINE void Xil_Out32(UINTPTR Addr, u32 Value)
+{
+#ifndef ENABLE_SAFETY
+ volatile u32 *LocalAddr = (volatile u32 *)Addr;
+ *LocalAddr = Value;
+#else
+ XStl_RegUpdate(Addr, Value);
+#endif
+}
+
+/*****************************************************************************/
+/**
+*
+* @brief Performs an output operation for a memory location by writing the
+* 64 bit Value to the the specified address.
+*
+* @param Addr contains the address to perform the output operation
+* @param Value contains 64 bit Value to be written at the specified address.
+*
+* @return None.
+*
+******************************************************************************/
+static INLINE void Xil_Out64(UINTPTR Addr, u64 Value)
+{
+ volatile u64 *LocalAddr = (volatile u64 *)Addr;
+ *LocalAddr = Value;
+}
+
+/*****************************************************************************/
+/**
+ *
+ * @brief Performs an output operation for a memory location by writing the
+ * 32 bit Value to the the specified address and then reading it
+ * back to verify the value written in the register.
+ *
+ * @param Addr contains the address to perform the output operation
+ * @param Value contains 32 bit Value to be written at the specified address
+ *
+ * @return Returns Status
+ * - XST_SUCCESS on success
+ * - XST_FAILURE on failure
+ *
+ *****************************************************************************/
+static INLINE int Xil_SecureOut32(UINTPTR Addr, u32 Value)
+{
+ int Status = XST_FAILURE;
+ u32 ReadReg;
+ u32 ReadRegTemp;
+
+ Xil_Out32(Addr, Value);
+
+ ReadReg = Xil_In32(Addr);
+ ReadRegTemp = Xil_In32(Addr);
+
+ if( (ReadReg == Value) && (ReadRegTemp == Value) ) {
+ Status = XST_SUCCESS;
+ }
+
+ return Status;
+}
+
+/*****************************************************************************/
+/**
+*
+* @brief Perform a 16-bit endian conversion.
+*
+* @param Data: 16 bit value to be converted
+*
+* @return 16 bit Data with converted endianness
+*
+******************************************************************************/
+static INLINE __attribute__((always_inline)) u16 Xil_EndianSwap16(u16 Data)
+{
+ return (u16) (((Data & 0xFF00U) >> 8U) | ((Data & 0x00FFU) << 8U));
+}
+
+/*****************************************************************************/
+/**
+*
+* @brief Perform a 32-bit endian conversion.
+*
+* @param Data: 32 bit value to be converted
+*
+* @return 32 bit data with converted endianness
+*
+******************************************************************************/
+static INLINE __attribute__((always_inline)) u32 Xil_EndianSwap32(u32 Data)
+{
+ u16 LoWord;
+ u16 HiWord;
+
+ /* get each of the half words from the 32 bit word */
+
+ LoWord = (u16) (Data & 0x0000FFFFU);
+ HiWord = (u16) ((Data & 0xFFFF0000U) >> 16U);
+
+ /* byte swap each of the 16 bit half words */
+
+ LoWord = (((LoWord & 0xFF00U) >> 8U) | ((LoWord & 0x00FFU) << 8U));
+ HiWord = (((HiWord & 0xFF00U) >> 8U) | ((HiWord & 0x00FFU) << 8U));
+
+ /* swap the half words before returning the value */
+
+ return ((((u32)LoWord) << (u32)16U) | (u32)HiWord);
+}
+
+#if defined (__MICROBLAZE__)
+#ifdef __LITTLE_ENDIAN__
+# define Xil_In16LE Xil_In16
+# define Xil_In32LE Xil_In32
+# define Xil_Out16LE Xil_Out16
+# define Xil_Out32LE Xil_Out32
+# define Xil_Htons Xil_EndianSwap16
+# define Xil_Htonl Xil_EndianSwap32
+# define Xil_Ntohs Xil_EndianSwap16
+# define Xil_Ntohl Xil_EndianSwap32
+# else
+# define Xil_In16BE Xil_In16
+# define Xil_In32BE Xil_In32
+# define Xil_Out16BE Xil_Out16
+# define Xil_Out32BE Xil_Out32
+# define Xil_Htons(Data) (Data)
+# define Xil_Htonl(Data) (Data)
+# define Xil_Ntohs(Data) (Data)
+# define Xil_Ntohl(Data) (Data)
+#endif
+#else
+# define Xil_In16LE Xil_In16
+# define Xil_In32LE Xil_In32
+# define Xil_Out16LE Xil_Out16
+# define Xil_Out32LE Xil_Out32
+# define Xil_Htons Xil_EndianSwap16
+# define Xil_Htonl Xil_EndianSwap32
+# define Xil_Ntohs Xil_EndianSwap16
+# define Xil_Ntohl Xil_EndianSwap32
+#endif
+
+#if defined (__MICROBLAZE__)
+#ifdef __LITTLE_ENDIAN__
+static INLINE u16 Xil_In16BE(UINTPTR Addr)
+#else
+static INLINE u16 Xil_In16LE(UINTPTR Addr)
+#endif
+#else
+static INLINE u16 Xil_In16BE(UINTPTR Addr)
+#endif
+{
+ u16 value = Xil_In16(Addr);
+ return Xil_EndianSwap16(value);
+}
+
+#if defined (__MICROBLAZE__)
+#ifdef __LITTLE_ENDIAN__
+static INLINE u32 Xil_In32BE(UINTPTR Addr)
+#else
+static INLINE u32 Xil_In32LE(UINTPTR Addr)
+#endif
+#else
+static INLINE u32 Xil_In32BE(UINTPTR Addr)
+#endif
+{
+ u32 value = Xil_In32(Addr);
+ return Xil_EndianSwap32(value);
+}
+
+#if defined (__MICROBLAZE__)
+#ifdef __LITTLE_ENDIAN__
+static INLINE void Xil_Out16BE(UINTPTR Addr, u16 Value)
+#else
+static INLINE void Xil_Out16LE(UINTPTR Addr, u16 Value)
+#endif
+#else
+static INLINE void Xil_Out16BE(UINTPTR Addr, u16 Value)
+#endif
+{
+ Value = Xil_EndianSwap16(Value);
+ Xil_Out16(Addr, Value);
+}
+
+#if defined (__MICROBLAZE__)
+#ifdef __LITTLE_ENDIAN__
+static INLINE void Xil_Out32BE(UINTPTR Addr, u32 Value)
+#else
+static INLINE void Xil_Out32LE(UINTPTR Addr, u32 Value)
+#endif
+#else
+static INLINE void Xil_Out32BE(UINTPTR Addr, u32 Value)
+#endif
+{
+ Value = Xil_EndianSwap32(Value);
+ Xil_Out32(Addr, Value);
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* end of protection macro */
+/**
+* @} End of "addtogroup common_io_interfacing_apis".
+*/
diff --git a/hello_world/sw/app/embeddedsw-master/xil_mmu.c b/hello_world/sw/app/embeddedsw-master/xil_mmu.c
new file mode 100644
index 0000000..c552a71
--- /dev/null
+++ b/hello_world/sw/app/embeddedsw-master/xil_mmu.c
@@ -0,0 +1,204 @@
+/******************************************************************************
+* Copyright (c) 2012 - 2021 Xilinx, Inc. All rights reserved.
+* SPDX-License-Identifier: MIT
+******************************************************************************/
+
+/*****************************************************************************/
+/**
+* @file xil_mmu.c
+*
+* This file provides APIs for enabling/disabling MMU and setting the memory
+* attributes for sections, in the MMU translation table.
+*
+* <pre>
+* MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ----- ---- -------- ---------------------------------------------------
+* 1.00a sdm 01/12/12 Initial version
+* 3.05a asa 03/10/12 Modified the Xil_EnableMMU to invalidate the caches
+* before enabling back.
+* 3.05a asa 04/15/12 Modified the Xil_SetTlbAttributes routine so that
+* translation table and branch predictor arrays are
+* invalidated, D-cache flushed before the attribute
+* change is applied. This is done so that the user
+* need not call Xil_DisableMMU before calling
+* Xil_SetTlbAttributes.
+* 3.10a srt 04/18/13 Implemented ARM Erratas. Please refer to file
+* 'xil_errata.h' for errata description
+* 3.11a asa 09/23/13 Modified Xil_SetTlbAttributes to flush the complete
+* D cache after the translation table update. Removed the
+* redundant TLB invalidation in the same API at the beginning.
+* 6.8 aru 09/06/18 Removed compilation warnings for ARMCC toolchain.
+* It fixes CR#1008309.
+* </pre>
+*
+* @note
+*
+* None.
+*
+******************************************************************************/
+
+/***************************** Include Files *********************************/
+
+#include "xil_cache.h"
+#include "xpseudo_asm.h"
+#include "xil_types.h"
+#include "xil_mmu.h"
+#include "xil_errata.h"
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/**************************** Type Definitions *******************************/
+
+/************************** Constant Definitions *****************************/
+#define ARM_AR_MEM_TTB_SECT_SIZE 1024*1024
+#define ARM_AR_MEM_TTB_SECT_SIZE_MASK (~(ARM_AR_MEM_TTB_SECT_SIZE-1UL))
+/************************** Variable Definitions *****************************/
+
+// extern u32 MMUTable;
+extern void Xil_SetTlbAttributes(INTPTR Addr, u32 attrib);
+
+/************************** Function Prototypes ******************************/
+
+/*****************************************************************************/
+/**
+* @brief This function sets the memory attributes for a section covering 1MB
+* of memory in the translation table.
+*
+* @param Addr: 32-bit address for which memory attributes need to be set.
+* @param attrib: Attribute for the given memory region. xil_mmu.h contains
+* definitions of commonly used memory attributes which can be
+* utilized for this function.
+*
+*
+* @return None.
+*
+* @note The MMU or D-cache does not need to be disabled before changing a
+* translation table entry.
+*
+******************************************************************************/
+// void Xil_SetTlbAttributes(INTPTR Addr, u32 attrib)
+// {
+// u32 *ptr;
+// u32 section;
+//
+// section = Addr / 0x100000U;
+// ptr = &MMUTable;
+// ptr += section;
+// if(ptr != NULL) {
+// *ptr = (Addr & 0xFFF00000U) | attrib;
+// }
+//
+// Xil_DCacheFlush();
+//
+// mtcp(XREG_CP15_INVAL_UTLB_UNLOCKED, 0U);
+// /* Invalidate all branch predictors */
+// mtcp(XREG_CP15_INVAL_BRANCH_ARRAY, 0U);
+//
+// dsb(); /* ensure completion of the BP and TLB invalidation */
+// isb(); /* synchronize context on this processor */
+// }
+
+/*****************************************************************************/
+/**
+* @brief Enable MMU for cortex A9 processor. This function invalidates the
+* instruction and data caches, and then enables MMU.
+*
+* @return None.
+*
+******************************************************************************/
+void Xil_EnableMMU(void)
+{
+ u32 Reg;
+ Xil_DCacheInvalidate();
+ Xil_ICacheInvalidate();
+
+#ifdef __GNUC__
+ Reg = mfcp(XREG_CP15_SYS_CONTROL);
+#elif defined (__ICCARM__)
+ mfcp(XREG_CP15_SYS_CONTROL, Reg);
+#else
+ { volatile register u32 Cp15Reg __asm(XREG_CP15_SYS_CONTROL);
+ Reg = Cp15Reg; }
+#endif
+ Reg |= (u32)0x05U;
+ mtcp(XREG_CP15_SYS_CONTROL, Reg);
+
+ dsb();
+ isb();
+}
+
+/*****************************************************************************/
+/**
+* @brief Disable MMU for Cortex A9 processors. This function invalidates
+* the TLBs, Branch Predictor Array and flushed the D Caches before
+* disabling the MMU.
+*
+* @return None.
+*
+* @note When the MMU is disabled, all the memory accesses are treated as
+* strongly ordered.
+******************************************************************************/
+void Xil_DisableMMU(void)
+{
+ u32 Reg;
+
+ mtcp(XREG_CP15_INVAL_UTLB_UNLOCKED, 0U);
+ mtcp(XREG_CP15_INVAL_BRANCH_ARRAY, 0U);
+ Xil_DCacheFlush();
+
+#ifdef __GNUC__
+ Reg = mfcp(XREG_CP15_SYS_CONTROL);
+#elif defined (__ICCARM__)
+ mfcp(XREG_CP15_SYS_CONTROL, Reg);
+#else
+ { volatile register u32 Cp15Reg __asm(XREG_CP15_SYS_CONTROL);
+ Reg = Cp15Reg; }
+#endif
+ Reg &= (u32)(~0x05U);
+#ifdef CONFIG_ARM_ERRATA_794073
+ /* Disable Branch Prediction */
+ Reg &= (u32)(~0x800U);
+#endif
+ mtcp(XREG_CP15_SYS_CONTROL, Reg);
+}
+
+/*****************************************************************************/
+/**
+* @brief Memory mapping for Cortex A9 processor.
+*
+* @param PhysAddr is physical address.
+* @param size is size of region.
+* @param flags is flags used to set translation table.
+*
+* @return Pointer to virtual address.
+*
+* @note: Previously this was implemented in libmetal. Move to embeddedsw as this
+* functionality is specific to A9 processor.
+*
+******************************************************************************/
+// void* Xil_MemMap(UINTPTR PhysAddr, size_t size, u32 flags)
+// {
+// u32 Sectionoffset;
+// u32 Ttbaddr;
+//
+// if (!flags)
+// return (void*)PhysAddr;
+//
+// /* Ensure alignment on a section boundary */
+// PhysAddr &= ARM_AR_MEM_TTB_SECT_SIZE_MASK;
+//
+// /* Loop through entire region of memory (one MMU section at a time).
+// Each section requires a TTB entry. */
+// for (Sectionoffset = 0; Sectionoffset < size;
+// Sectionoffset += ARM_AR_MEM_TTB_SECT_SIZE) {
+// /* Calculate translation table entry for this memory section */
+// Ttbaddr = (PhysAddr + Sectionoffset);
+//
+// /* Write translation table entry value to entry address */
+// Xil_SetTlbAttributes(Ttbaddr, flags);
+// }
+// return (void*)PhysAddr;
+// }
+
diff --git a/hello_world/sw/app/embeddedsw-master/xil_mmu.h b/hello_world/sw/app/embeddedsw-master/xil_mmu.h
new file mode 100644
index 0000000..7d074a4
--- /dev/null
+++ b/hello_world/sw/app/embeddedsw-master/xil_mmu.h
@@ -0,0 +1,93 @@
+/******************************************************************************
+* Copyright (c) 2012 - 2021 Xilinx, Inc. All rights reserved.
+* SPDX-License-Identifier: MIT
+******************************************************************************/
+
+/*****************************************************************************/
+/**
+* @file xil_mmu.h
+*
+* @addtogroup a9_mmu_apis Cortex A9 Processor MMU Functions
+*
+* MMU functions equip users to enable MMU, disable MMU and modify default
+* memory attributes of MMU table as per the need.
+*
+* @{
+*
+* <pre>
+* MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ----- ---- -------- ---------------------------------------------------
+* 1.00a sdm 01/12/12 Initial version
+* 4.2 pkp 07/21/14 Included xil_types.h file which contains definition for
+* u32 which resolves issue of CR#805869
+* 5.4 pkp 23/11/15 Added attribute definitions for Xil_SetTlbAttributes API
+* 6.8 aru 09/06/18 Removed compilation warnings for ARMCC toolchain.
+* </pre>
+*
+*
+******************************************************************************/
+
+/**
+*@cond nocomments
+*/
+
+#ifndef XIL_MMU_H
+#define XIL_MMU_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif /* __cplusplus */
+
+/***************************** Include Files *********************************/
+
+#include "xil_types.h"
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/**************************** Type Definitions *******************************/
+
+/************************** Constant Definitions *****************************/
+
+/* Memory type */
+#define NORM_NONCACHE 0x11DE2 /* Normal Non-cacheable */
+#define STRONG_ORDERED 0xC02 /* Strongly ordered */
+#define DEVICE_MEMORY 0xC06 /* Device memory */
+#define RESERVED 0x0 /* reserved memory */
+
+/* Normal write-through cacheable shareable */
+#define NORM_WT_CACHE 0x16DEA
+
+/* Normal write back cacheable shareable */
+#define NORM_WB_CACHE 0x15DE6
+
+/* shareability attribute */
+#define SHAREABLE (0x1 << 16)
+#define NON_SHAREABLE (~(0x1 << 16))
+
+/* Execution type */
+#define EXECUTE_NEVER ((0x1 << 4) | (0x1 << 0))
+
+/**
+*@endcond
+*/
+
+/************************** Variable Definitions *****************************/
+
+/************************** Function Prototypes ******************************/
+
+void Xil_SetTlbAttributes(INTPTR Addr, u32 attrib);
+void Xil_EnableMMU(void);
+void Xil_DisableMMU(void);
+void* Xil_MemMap(UINTPTR PhysAddr, size_t size, u32 flags);
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+
+#endif /* XIL_MMU_H */
+/**
+* @} End of "addtogroup a9_mmu_apis".
+*/
+
diff --git a/hello_world/sw/app/embeddedsw-master/xil_printf.h b/hello_world/sw/app/embeddedsw-master/xil_printf.h
new file mode 100644
index 0000000..0da371f
--- /dev/null
+++ b/hello_world/sw/app/embeddedsw-master/xil_printf.h
@@ -0,0 +1,52 @@
+/******************************************************************************
+* Copyright (c) 1995 - 2020 Xilinx, Inc. All rights reserved.
+* SPDX-License-Identifier: MIT
+*******************************************************************************/
+ #ifndef XIL_PRINTF_H
+ #define XIL_PRINTF_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <ctype.h>
+#include <string.h>
+#include <stdarg.h>
+#include "xil_types.h"
+#include "xparameters.h"
+#include "bspconfig.h"
+#if defined (__aarch64__) && HYP_GUEST && EL1_NONSECURE && XEN_USE_PV_CONSOLE
+#include "xen_console.h"
+#endif
+
+/*----------------------------------------------------*/
+/* Use the following parameter passing structure to */
+/* make xil_printf re-entrant. */
+/*----------------------------------------------------*/
+
+struct params_s;
+
+
+/*---------------------------------------------------*/
+/* The purpose of this routine is to output data the */
+/* same as the standard printf function without the */
+/* overhead most run-time libraries involve. Usually */
+/* the printf brings in many kilobytes of code and */
+/* that is unacceptable in most embedded systems. */
+/*---------------------------------------------------*/
+
+typedef char8* charptr;
+typedef s32 (*func_ptr)(int c);
+
+/* */
+
+void xil_printf( const char8 *ctrl1, ...);
+void print( const char8 *ptr);
+extern void outbyte (char8 c);
+extern char8 inbyte(void);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* end of protection macro */
diff --git a/hello_world/sw/app/embeddedsw-master/xil_types.h b/hello_world/sw/app/embeddedsw-master/xil_types.h
new file mode 100644
index 0000000..8ea44a4
--- /dev/null
+++ b/hello_world/sw/app/embeddedsw-master/xil_types.h
@@ -0,0 +1,197 @@
+/******************************************************************************
+* Copyright (c) 2010 - 2020 Xilinx, Inc. All rights reserved.
+* SPDX-License-Identifier: MIT
+******************************************************************************/
+
+/*****************************************************************************/
+/**
+*
+* @file xil_types.h
+*
+* @addtogroup common_types Basic Data types for Xilinx® Software IP
+*
+* The xil_types.h file contains basic types for Xilinx software IP. These data types
+* are applicable for all processors supported by Xilinx.
+* @{
+* <pre>
+* MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ----- ---- -------- -------------------------------------------------------
+* 1.00a hbm 07/14/09 First release
+* 3.03a sdm 05/30/11 Added Xuint64 typedef and XUINT64_MSW/XUINT64_LSW macros
+* 5.00 pkp 05/29/14 Made changes for 64 bit architecture
+* srt 07/14/14 Use standard definitions from stdint.h and stddef.h
+* Define LONG and ULONG datatypes and mask values
+* 7.00 mus 01/07/19 Add cpp extern macro
+* 7.1 aru 08/19/19 Shift the value in UPPER_32_BITS only if it
+* is 64-bit processor
+* </pre>
+*
+******************************************************************************/
+
+#ifndef XIL_TYPES_H /* prevent circular inclusions */
+#define XIL_TYPES_H /* by using protection macros */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <stdint.h>
+#include <stddef.h>
+
+/************************** Constant Definitions *****************************/
+
+#ifndef TRUE
+# define TRUE 1U
+#endif
+
+#ifndef FALSE
+# define FALSE 0U
+#endif
+
+#ifndef NULL
+#define NULL 0U
+#endif
+
+#define XIL_COMPONENT_IS_READY 0x11111111U /**< In device drivers, This macro will be
+ assigend to "IsReady" member of driver
+ instance to indicate that driver
+ instance is initialized and ready to use. */
+#define XIL_COMPONENT_IS_STARTED 0x22222222U /**< In device drivers, This macro will be assigend to
+ "IsStarted" member of driver instance
+ to indicate that driver instance is
+ started and it can be enabled. */
+
+/* @name New types
+ * New simple types.
+ * @{
+ */
+#ifndef __KERNEL__
+#ifndef XBASIC_TYPES_H
+/*
+ * guarded against xbasic_types.h.
+ */
+typedef uint8_t u8;
+typedef uint16_t u16;
+typedef uint32_t u32;
+/** @}*/
+#define __XUINT64__
+typedef struct
+{
+ u32 Upper;
+ u32 Lower;
+} Xuint64;
+
+
+/*****************************************************************************/
+/**
+* @brief Return the most significant half of the 64 bit data type.
+*
+* @param x is the 64 bit word.
+*
+* @return The upper 32 bits of the 64 bit word.
+*
+******************************************************************************/
+#define XUINT64_MSW(x) ((x).Upper)
+
+/*****************************************************************************/
+/**
+* @brief Return the least significant half of the 64 bit data type.
+*
+* @param x is the 64 bit word.
+*
+* @return The lower 32 bits of the 64 bit word.
+*
+******************************************************************************/
+#define XUINT64_LSW(x) ((x).Lower)
+
+#endif /* XBASIC_TYPES_H */
+
+/*
+ * xbasic_types.h does not typedef s* or u64
+ */
+/** @{ */
+typedef char char8;
+typedef int8_t s8;
+typedef int16_t s16;
+typedef int32_t s32;
+typedef int64_t s64;
+typedef uint64_t u64;
+typedef int sint32;
+
+typedef intptr_t INTPTR;
+typedef uintptr_t UINTPTR;
+typedef ptrdiff_t PTRDIFF;
+/** @}*/
+#if !defined(LONG) || !defined(ULONG)
+typedef long LONG;
+typedef unsigned long ULONG;
+#endif
+
+#define ULONG64_HI_MASK 0xFFFFFFFF00000000U
+#define ULONG64_LO_MASK ~ULONG64_HI_MASK
+
+#else
+#include <linux/types.h>
+#endif
+
+/** @{ */
+/**
+ * This data type defines an interrupt handler for a device.
+ * The argument points to the instance of the component
+ */
+typedef void (*XInterruptHandler) (void *InstancePtr);
+
+/**
+ * This data type defines an exception handler for a processor.
+ * The argument points to the instance of the component
+ */
+typedef void (*XExceptionHandler) (void *InstancePtr);
+
+/**
+ * @brief Returns 32-63 bits of a number.
+ * @param n : Number being accessed.
+ * @return Bits 32-63 of number.
+ *
+ * @note A basic shift-right of a 64- or 32-bit quantity.
+ * Use this to suppress the "right shift count >= width of type"
+ * warning when that quantity is 32-bits.
+ */
+#if defined (__aarch64__) || defined (__arch64__)
+#define UPPER_32_BITS(n) ((u32)(((n) >> 16) >> 16))
+#else
+#define UPPER_32_BITS(n) 0U
+#endif
+/**
+ * @brief Returns 0-31 bits of a number
+ * @param n : Number being accessed.
+ * @return Bits 0-31 of number
+ */
+#define LOWER_32_BITS(n) ((u32)(n))
+
+
+
+
+/************************** Constant Definitions *****************************/
+
+#ifndef TRUE
+#define TRUE 1U
+#endif
+
+#ifndef FALSE
+#define FALSE 0U
+#endif
+
+#ifndef NULL
+#define NULL 0U
+#endif
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* end of protection macro */
+/**
+* @} End of "addtogroup common_types".
+*/
diff --git a/hello_world/sw/app/embeddedsw-master/xl2cc.h b/hello_world/sw/app/embeddedsw-master/xl2cc.h
new file mode 100644
index 0000000..8b59e34
--- /dev/null
+++ b/hello_world/sw/app/embeddedsw-master/xl2cc.h
@@ -0,0 +1,146 @@
+/******************************************************************************
+* Copyright (c) 2011 - 2020 Xilinx, Inc. All rights reserved.
+* SPDX-License-Identifier: MIT
+******************************************************************************/
+
+/*****************************************************************************/
+/**
+* @file xl2cc.h
+*
+* This file contains the address definitions for the PL310 Level-2 Cache
+* Controller.
+*
+* <pre>
+* MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ----- ---- -------- ---------------------------------------------------
+* 1.00a sdm 02/01/10 Initial version
+* 3.10a srt 04/18/13 Implemented ARM Erratas. Please refer to file
+* 'xil_errata.h' for errata description
+* </pre>
+*
+* @note
+*
+* None.
+*
+******************************************************************************/
+
+#ifndef _XL2CC_H_
+#define _XL2CC_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/************************** Constant Definitions *****************************/
+/* L2CC Register Offsets */
+#define XPS_L2CC_ID_OFFSET 0x0000U
+#define XPS_L2CC_TYPE_OFFSET 0x0004U
+#define XPS_L2CC_CNTRL_OFFSET 0x0100U
+#define XPS_L2CC_AUX_CNTRL_OFFSET 0x0104U
+#define XPS_L2CC_TAG_RAM_CNTRL_OFFSET 0x0108U
+#define XPS_L2CC_DATA_RAM_CNTRL_OFFSET 0x010CU
+
+#define XPS_L2CC_EVNT_CNTRL_OFFSET 0x0200U
+#define XPS_L2CC_EVNT_CNT1_CTRL_OFFSET 0x0204U
+#define XPS_L2CC_EVNT_CNT0_CTRL_OFFSET 0x0208U
+#define XPS_L2CC_EVNT_CNT1_VAL_OFFSET 0x020CU
+#define XPS_L2CC_EVNT_CNT0_VAL_OFFSET 0x0210U
+
+#define XPS_L2CC_IER_OFFSET 0x0214U /* Interrupt Mask */
+#define XPS_L2CC_IPR_OFFSET 0x0218U /* Masked interrupt status */
+#define XPS_L2CC_ISR_OFFSET 0x021CU /* Raw Interrupt Status */
+#define XPS_L2CC_IAR_OFFSET 0x0220U /* Interrupt Clear */
+
+#define XPS_L2CC_CACHE_SYNC_OFFSET 0x0730U /* Cache Sync */
+#define XPS_L2CC_DUMMY_CACHE_SYNC_OFFSET 0x0740U /* Dummy Register for Cache Sync */
+#define XPS_L2CC_CACHE_INVLD_PA_OFFSET 0x0770U /* Cache Invalid by PA */
+#define XPS_L2CC_CACHE_INVLD_WAY_OFFSET 0x077CU /* Cache Invalid by Way */
+#define XPS_L2CC_CACHE_CLEAN_PA_OFFSET 0x07B0U /* Cache Clean by PA */
+#define XPS_L2CC_CACHE_CLEAN_INDX_OFFSET 0x07B8U /* Cache Clean by Index */
+#define XPS_L2CC_CACHE_CLEAN_WAY_OFFSET 0x07BCU /* Cache Clean by Way */
+#define XPS_L2CC_CACHE_INV_CLN_PA_OFFSET 0x07F0U /* Cache Invalidate and Clean by PA */
+#define XPS_L2CC_CACHE_INV_CLN_INDX_OFFSET 0x07F8U /* Cache Invalidate and Clean by Index */
+#define XPS_L2CC_CACHE_INV_CLN_WAY_OFFSET 0x07FCU /* Cache Invalidate and Clean by Way */
+
+#define XPS_L2CC_CACHE_DLCKDWN_0_WAY_OFFSET 0x0900U /* Cache Data Lockdown 0 by Way */
+#define XPS_L2CC_CACHE_ILCKDWN_0_WAY_OFFSET 0x0904U /* Cache Instruction Lockdown 0 by Way */
+#define XPS_L2CC_CACHE_DLCKDWN_1_WAY_OFFSET 0x0908U /* Cache Data Lockdown 1 by Way */
+#define XPS_L2CC_CACHE_ILCKDWN_1_WAY_OFFSET 0x090CU /* Cache Instruction Lockdown 1 by Way */
+#define XPS_L2CC_CACHE_DLCKDWN_2_WAY_OFFSET 0x0910U /* Cache Data Lockdown 2 by Way */
+#define XPS_L2CC_CACHE_ILCKDWN_2_WAY_OFFSET 0x0914U /* Cache Instruction Lockdown 2 by Way */
+#define XPS_L2CC_CACHE_DLCKDWN_3_WAY_OFFSET 0x0918U /* Cache Data Lockdown 3 by Way */
+#define XPS_L2CC_CACHE_ILCKDWN_3_WAY_OFFSET 0x091CU /* Cache Instruction Lockdown 3 by Way */
+#define XPS_L2CC_CACHE_DLCKDWN_4_WAY_OFFSET 0x0920U /* Cache Data Lockdown 4 by Way */
+#define XPS_L2CC_CACHE_ILCKDWN_4_WAY_OFFSET 0x0924U /* Cache Instruction Lockdown 4 by Way */
+#define XPS_L2CC_CACHE_DLCKDWN_5_WAY_OFFSET 0x0928U /* Cache Data Lockdown 5 by Way */
+#define XPS_L2CC_CACHE_ILCKDWN_5_WAY_OFFSET 0x092CU /* Cache Instruction Lockdown 5 by Way */
+#define XPS_L2CC_CACHE_DLCKDWN_6_WAY_OFFSET 0x0930U /* Cache Data Lockdown 6 by Way */
+#define XPS_L2CC_CACHE_ILCKDWN_6_WAY_OFFSET 0x0934U /* Cache Instruction Lockdown 6 by Way */
+#define XPS_L2CC_CACHE_DLCKDWN_7_WAY_OFFSET 0x0938U /* Cache Data Lockdown 7 by Way */
+#define XPS_L2CC_CACHE_ILCKDWN_7_WAY_OFFSET 0x093CU /* Cache Instruction Lockdown 7 by Way */
+
+#define XPS_L2CC_CACHE_LCKDWN_LINE_ENABLE_OFFSET 0x0950U /* Cache Lockdown Line Enable */
+#define XPS_L2CC_CACHE_UUNLOCK_ALL_WAY_OFFSET 0x0954U /* Cache Unlock All Lines by Way */
+
+#define XPS_L2CC_ADDR_FILTER_START_OFFSET 0x0C00U /* Start of address filtering */
+#define XPS_L2CC_ADDR_FILTER_END_OFFSET 0x0C04U /* Start of address filtering */
+
+#define XPS_L2CC_DEBUG_CTRL_OFFSET 0x0F40U /* Debug Control Register */
+
+/* XPS_L2CC_CNTRL_OFFSET bit masks */
+#define XPS_L2CC_ENABLE_MASK 0x00000001U /* enables the L2CC */
+
+/* XPS_L2CC_AUX_CNTRL_OFFSET bit masks */
+#define XPS_L2CC_AUX_EBRESPE_MASK 0x40000000U /* Early BRESP Enable */
+#define XPS_L2CC_AUX_IPFE_MASK 0x20000000U /* Instruction Prefetch Enable */
+#define XPS_L2CC_AUX_DPFE_MASK 0x10000000U /* Data Prefetch Enable */
+#define XPS_L2CC_AUX_NSIC_MASK 0x08000000U /* Non-secure interrupt access control */
+#define XPS_L2CC_AUX_NSLE_MASK 0x04000000U /* Non-secure lockdown enable */
+#define XPS_L2CC_AUX_CRP_MASK 0x02000000U /* Cache replacement policy */
+#define XPS_L2CC_AUX_FWE_MASK 0x01800000U /* Force write allocate */
+#define XPS_L2CC_AUX_SAOE_MASK 0x00400000U /* Shared attribute override enable */
+#define XPS_L2CC_AUX_PE_MASK 0x00200000U /* Parity enable */
+#define XPS_L2CC_AUX_EMBE_MASK 0x00100000U /* Event monitor bus enable */
+#define XPS_L2CC_AUX_WAY_SIZE_MASK 0x000E0000U /* Way-size */
+#define XPS_L2CC_AUX_ASSOC_MASK 0x00010000U /* Associativity */
+#define XPS_L2CC_AUX_SAIE_MASK 0x00002000U /* Shared attribute invalidate enable */
+#define XPS_L2CC_AUX_EXCL_CACHE_MASK 0x00001000U /* Exclusive cache configuration */
+#define XPS_L2CC_AUX_SBDLE_MASK 0x00000800U /* Store buffer device limitation Enable */
+#define XPS_L2CC_AUX_HPSODRE_MASK 0x00000400U /* High Priority for SO and Dev Reads Enable */
+#define XPS_L2CC_AUX_FLZE_MASK 0x00000001U /* Full line of zero enable */
+
+#define XPS_L2CC_AUX_REG_DEFAULT_MASK 0x72360000U /* Enable all prefetching, */
+ /* Cache replacement policy, Parity enable, */
+ /* Event monitor bus enable and Way Size (64 KB) */
+#define XPS_L2CC_AUX_REG_ZERO_MASK 0xFFF1FFFFU /* */
+
+#define XPS_L2CC_TAG_RAM_DEFAULT_MASK 0x00000111U /* latency for TAG RAM */
+#define XPS_L2CC_DATA_RAM_DEFAULT_MASK 0x00000121U /* latency for DATA RAM */
+
+/* Interrupt bit masks */
+#define XPS_L2CC_IXR_DECERR_MASK 0x00000100U /* DECERR from L3 */
+#define XPS_L2CC_IXR_SLVERR_MASK 0x00000080U /* SLVERR from L3 */
+#define XPS_L2CC_IXR_ERRRD_MASK 0x00000040U /* Error on L2 data RAM (Read) */
+#define XPS_L2CC_IXR_ERRRT_MASK 0x00000020U /* Error on L2 tag RAM (Read) */
+#define XPS_L2CC_IXR_ERRWD_MASK 0x00000010U /* Error on L2 data RAM (Write) */
+#define XPS_L2CC_IXR_ERRWT_MASK 0x00000008U /* Error on L2 tag RAM (Write) */
+#define XPS_L2CC_IXR_PARRD_MASK 0x00000004U /* Parity Error on L2 data RAM (Read) */
+#define XPS_L2CC_IXR_PARRT_MASK 0x00000002U /* Parity Error on L2 tag RAM (Read) */
+#define XPS_L2CC_IXR_ECNTR_MASK 0x00000001U /* Event Counter1/0 Overflow Increment */
+
+/* Address filtering mask and enable bit */
+#define XPS_L2CC_ADDR_FILTER_VALID_MASK 0xFFF00000U /* Address filtering valid bits*/
+#define XPS_L2CC_ADDR_FILTER_ENABLE_MASK 0x00000001U /* Address filtering enable bit*/
+
+/* Debug control bits */
+#define XPS_L2CC_DEBUG_SPIDEN_MASK 0x00000004U /* Debug SPIDEN bit */
+#define XPS_L2CC_DEBUG_DWB_MASK 0x00000002U /* Debug DWB bit, forces write through */
+#define XPS_L2CC_DEBUG_DCL_MASK 0x00000002U /* Debug DCL bit, disables cache line fill */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* protection macro */
diff --git a/hello_world/sw/app/embeddedsw-master/xparameters.h b/hello_world/sw/app/embeddedsw-master/xparameters.h
new file mode 100644
index 0000000..07ffae0
--- /dev/null
+++ b/hello_world/sw/app/embeddedsw-master/xparameters.h
@@ -0,0 +1,1765 @@
+#ifndef XPARAMETERS_H /* prevent circular inclusions */
+#define XPARAMETERS_H /* by using protection macros */
+
+
+/* Definitions for PMU Microblaze */
+#define XPAR_MICROBLAZE_ADDR_TAG_BITS 0
+#define XPAR_MICROBLAZE_ALLOW_DCACHE_WR 1
+#define XPAR_MICROBLAZE_ALLOW_ICACHE_WR 1
+#define XPAR_MICROBLAZE_ASYNC_INTERRUPT 1
+#define XPAR_MICROBLAZE_BASE_VECTORS 0xffd00000
+#define XPAR_MICROBLAZE_BRANCH_TARGET_CACHE_SIZE 0
+#define XPAR_MICROBLAZE_CACHE_BYTE_SIZE 8192
+#define XPAR_MICROBLAZE_DATA_SIZE 32
+#define XPAR_MICROBLAZE_DCACHE_ADDR_TAG 0
+#define XPAR_MICROBLAZE_DCACHE_ALWAYS_USED 0
+#define XPAR_MICROBLAZE_DCACHE_BASEADDR 0x00000000
+#define XPAR_MICROBLAZE_DCACHE_BYTE_SIZE 8192
+#define XPAR_MICROBLAZE_DCACHE_DATA_WIDTH 0
+#define XPAR_MICROBLAZE_DCACHE_FORCE_TAG_LUTRAM 0
+#define XPAR_MICROBLAZE_DCACHE_HIGHADDR 0x3FFFFFFF
+#define XPAR_MICROBLAZE_DCACHE_LINE_LEN 4
+#define XPAR_MICROBLAZE_DCACHE_USE_WRITEBACK 0
+#define XPAR_MICROBLAZE_DCACHE_VICTIMS 0
+#define XPAR_MICROBLAZE_DDR_RESERVE_EA 0x7FFFFFFF
+#define XPAR_MICROBLAZE_DDR_RESERVE_SA 0x7FF00000
+#define XPAR_MICROBLAZE_DEBUG_ENABLED 1
+#define XPAR_MICROBLAZE_DIV_ZERO_EXCEPTION 0
+#define XPAR_MICROBLAZE_DYNAMIC_BUS_SIZING 0
+#define XPAR_MICROBLAZE_ECC_USE_CE_EXCEPTION 0
+#define XPAR_MICROBLAZE_EDGE_IS_POSITIVE 0
+#define XPAR_MICROBLAZE_ENABLE_DISCRETE_PORTS 1
+#define XPAR_MICROBLAZE_ENDIANNESS 1
+#define XPAR_MICROBLAZE_FAULT_TOLERANT 1
+#define XPAR_MICROBLAZE_FPU_EXCEPTION 0
+#define XPAR_MICROBLAZE_FREQ 180000000
+#define XPAR_MICROBLAZE_FSL_EXCEPTION 0
+#define XPAR_MICROBLAZE_FSL_LINKS 0
+#define XPAR_MICROBLAZE_ICACHE_ALWAYS_USED 0
+#define XPAR_MICROBLAZE_ICACHE_BASEADDR 0x00000000
+#define XPAR_MICROBLAZE_ICACHE_DATA_WIDTH 0
+#define XPAR_MICROBLAZE_ICACHE_FORCE_TAG_LUTRAM 0
+#define XPAR_MICROBLAZE_ICACHE_HIGHADDR 0x3FFFFFFF
+#define XPAR_MICROBLAZE_ICACHE_LINE_LEN 4
+#define XPAR_MICROBLAZE_ICACHE_STREAMS 0
+#define XPAR_MICROBLAZE_ICACHE_VICTIMS 0
+#define XPAR_MICROBLAZE_ILL_OPCODE_EXCEPTION 1
+#define XPAR_MICROBLAZE_INTERRUPT_IS_EDGE 0
+#define XPAR_MICROBLAZE_LOCKSTEP_SELECT 0
+#define XPAR_MICROBLAZE_LOCKSTEP_SLAVE 0
+#define XPAR_MICROBLAZE_MMU_DTLB_SIZE 4
+#define XPAR_MICROBLAZE_MMU_ITLB_SIZE 2
+#define XPAR_MICROBLAZE_MMU_PRIVILEGED_INSTR 0
+#define XPAR_MICROBLAZE_MMU_TLB_ACCESS 3
+#define XPAR_MICROBLAZE_MMU_ZONES 16
+#define XPAR_MICROBLAZE_NUMBER_OF_PC_BRK 1
+#define XPAR_MICROBLAZE_NUMBER_OF_RD_ADDR_BRK 1
+#define XPAR_MICROBLAZE_NUMBER_OF_WR_ADDR_BRK 1
+#define XPAR_MICROBLAZE_OPCODE_0X0_ILLEGAL 1
+#define XPAR_MICROBLAZE_PC_WIDTH 32
+#define XPAR_MICROBLAZE_PSU_DEVICE PSSa
+#define XPAR_MICROBLAZE_PSU_EP 1
+#define XPAR_MICROBLAZE_PVR 0
+#define XPAR_MICROBLAZE_PVR_USER1 0x00
+#define XPAR_MICROBLAZE_PVR_USER2 0x00000000
+#define XPAR_MICROBLAZE_RESET_MSR 0x00000000
+#define XPAR_MICROBLAZE_SCO 0
+#define XPAR_MICROBLAZE_TRACE 1
+#define XPAR_MICROBLAZE_UNALIGNED_EXCEPTIONS 1
+#define XPAR_MICROBLAZE_USE_BARREL 1
+#define XPAR_MICROBLAZE_USE_BRANCH_TARGET_CACHE 0
+#define XPAR_MICROBLAZE_USE_CONFIG_RESET 0
+#define XPAR_MICROBLAZE_USE_DCACHE 0
+#define XPAR_MICROBLAZE_USE_DIV 0
+#define XPAR_MICROBLAZE_USE_EXTENDED_FSL_INSTR 0
+#define XPAR_MICROBLAZE_USE_EXT_BRK 0
+#define XPAR_MICROBLAZE_USE_EXT_NM_BRK 0
+#define XPAR_MICROBLAZE_USE_FPU 0
+#define XPAR_MICROBLAZE_USE_HW_MUL 0
+#define XPAR_MICROBLAZE_USE_ICACHE 0
+#define XPAR_MICROBLAZE_USE_INTERRUPT 1
+#define XPAR_MICROBLAZE_USE_MMU 0
+#define XPAR_MICROBLAZE_USE_MSR_INSTR 1
+#define XPAR_MICROBLAZE_USE_PCMP_INSTR 1
+#define XPAR_MICROBLAZE_USE_REORDER_INSTR 1
+#define XPAR_MICROBLAZE_USE_STACK_PROTECTION 1
+#define XPAR_MICROBLAZE_G_USE_EXCEPTIONS 1
+#define XPAR_MICROBLAZE_IS_CACHE_COHERENT 0
+#define XPAR_MICROBLAZE_PMU_BOARD_INTERFACE custom
+
+/******************************************************************/
+
+#define XPAR_CPU_CORE_CLOCK_FREQ_HZ XPAR_MICROBLAZE_FREQ
+
+/******************************************************************/
+
+#define XPAR_CPU_ID 6
+#define XPAR_PSU_PMU_ID 6
+#define XPAR_PSU_PMU_ADDR_TAG_BITS 0
+#define XPAR_PSU_PMU_ALLOW_DCACHE_WR 1
+#define XPAR_PSU_PMU_ALLOW_ICACHE_WR 1
+#define XPAR_PSU_PMU_ASYNC_INTERRUPT 1
+#define XPAR_PSU_PMU_BASE_VECTORS 0xffd00000
+#define XPAR_PSU_PMU_BRANCH_TARGET_CACHE_SIZE 0
+#define XPAR_PSU_PMU_CACHE_BYTE_SIZE 8192
+#define XPAR_PSU_PMU_DATA_SIZE 32
+#define XPAR_PSU_PMU_DCACHE_ADDR_TAG 0
+#define XPAR_PSU_PMU_DCACHE_ALWAYS_USED 0
+#define XPAR_PSU_PMU_DCACHE_BASEADDR 0x00000000
+#define XPAR_PSU_PMU_DCACHE_BYTE_SIZE 8192
+#define XPAR_PSU_PMU_DCACHE_DATA_WIDTH 0
+#define XPAR_PSU_PMU_DCACHE_FORCE_TAG_LUTRAM 0
+#define XPAR_PSU_PMU_DCACHE_HIGHADDR 0x3FFFFFFF
+#define XPAR_PSU_PMU_DCACHE_LINE_LEN 4
+#define XPAR_PSU_PMU_DCACHE_USE_WRITEBACK 0
+#define XPAR_PSU_PMU_DCACHE_VICTIMS 0
+#define XPAR_PSU_PMU_DDR_RESERVE_EA 0x7FFFFFFF
+#define XPAR_PSU_PMU_DDR_RESERVE_SA 0x7FF00000
+#define XPAR_PSU_PMU_DEBUG_ENABLED 1
+#define XPAR_PSU_PMU_DIV_ZERO_EXCEPTION 0
+#define XPAR_PSU_PMU_DYNAMIC_BUS_SIZING 0
+#define XPAR_PSU_PMU_ECC_USE_CE_EXCEPTION 0
+#define XPAR_PSU_PMU_EDGE_IS_POSITIVE 0
+#define XPAR_PSU_PMU_ENABLE_DISCRETE_PORTS 1
+#define XPAR_PSU_PMU_ENDIANNESS 1
+#define XPAR_PSU_PMU_FAULT_TOLERANT 1
+#define XPAR_PSU_PMU_FPU_EXCEPTION 0
+#define XPAR_PSU_PMU_FREQ 180000000
+#define XPAR_PSU_PMU_FSL_EXCEPTION 0
+#define XPAR_PSU_PMU_FSL_LINKS 0
+#define XPAR_PSU_PMU_ICACHE_ALWAYS_USED 0
+#define XPAR_PSU_PMU_ICACHE_BASEADDR 0x00000000
+#define XPAR_PSU_PMU_ICACHE_DATA_WIDTH 0
+#define XPAR_PSU_PMU_ICACHE_FORCE_TAG_LUTRAM 0
+#define XPAR_PSU_PMU_ICACHE_HIGHADDR 0x3FFFFFFF
+#define XPAR_PSU_PMU_ICACHE_LINE_LEN 4
+#define XPAR_PSU_PMU_ICACHE_STREAMS 0
+#define XPAR_PSU_PMU_ICACHE_VICTIMS 0
+#define XPAR_PSU_PMU_ILL_OPCODE_EXCEPTION 1
+#define XPAR_PSU_PMU_INTERRUPT_IS_EDGE 0
+#define XPAR_PSU_PMU_LOCKSTEP_SELECT 0
+#define XPAR_PSU_PMU_LOCKSTEP_SLAVE 0
+#define XPAR_PSU_PMU_MMU_DTLB_SIZE 4
+#define XPAR_PSU_PMU_MMU_ITLB_SIZE 2
+#define XPAR_PSU_PMU_MMU_PRIVILEGED_INSTR 0
+#define XPAR_PSU_PMU_MMU_TLB_ACCESS 3
+#define XPAR_PSU_PMU_MMU_ZONES 16
+#define XPAR_PSU_PMU_NUMBER_OF_PC_BRK 1
+#define XPAR_PSU_PMU_NUMBER_OF_RD_ADDR_BRK 1
+#define XPAR_PSU_PMU_NUMBER_OF_WR_ADDR_BRK 1
+#define XPAR_PSU_PMU_OPCODE_0X0_ILLEGAL 1
+#define XPAR_PSU_PMU_PC_WIDTH 32
+#define XPAR_PSU_PMU_PSU_DEVICE PSSa
+#define XPAR_PSU_PMU_PSU_EP 1
+#define XPAR_PSU_PMU_PVR 0
+#define XPAR_PSU_PMU_PVR_USER1 0x00
+#define XPAR_PSU_PMU_PVR_USER2 0x00000000
+#define XPAR_PSU_PMU_RESET_MSR 0x00000000
+#define XPAR_PSU_PMU_SCO 0
+#define XPAR_PSU_PMU_TRACE 1
+#define XPAR_PSU_PMU_UNALIGNED_EXCEPTIONS 1
+#define XPAR_PSU_PMU_USE_BARREL 1
+#define XPAR_PSU_PMU_USE_BRANCH_TARGET_CACHE 0
+#define XPAR_PSU_PMU_USE_CONFIG_RESET 0
+#define XPAR_PSU_PMU_USE_DCACHE 0
+#define XPAR_PSU_PMU_USE_DIV 0
+#define XPAR_PSU_PMU_USE_EXTENDED_FSL_INSTR 0
+#define XPAR_PSU_PMU_USE_EXT_BRK 0
+#define XPAR_PSU_PMU_USE_EXT_NM_BRK 0
+#define XPAR_PSU_PMU_USE_FPU 0
+#define XPAR_PSU_PMU_USE_HW_MUL 0
+#define XPAR_PSU_PMU_USE_ICACHE 0
+#define XPAR_PSU_PMU_USE_INTERRUPT 1
+#define XPAR_PSU_PMU_USE_MMU 0
+#define XPAR_PSU_PMU_USE_MSR_INSTR 1
+#define XPAR_PSU_PMU_USE_PCMP_INSTR 1
+#define XPAR_PSU_PMU_USE_REORDER_INSTR 1
+#define XPAR_PSU_PMU_USE_STACK_PROTECTION 1
+#define XPAR_PSU_PMU_G_USE_EXCEPTIONS 1
+#define XPAR_PSU_PMU_IS_CACHE_COHERENT 0
+#define XPAR_PSU_PMU_PMU_BOARD_INTERFACE custom
+
+/******************************************************************/
+
+
+#define XPAR_PSU_PSS_REF_CLK_FREQ_HZ 33330000U
+
+#define PSU_PMU 1U
+#define XPS_BOARD_ZCU102
+
+
+/* Number of Fabric Resets */
+#define XPAR_NUM_FABRIC_RESETS 1
+
+#define STDIN_BASEADDRESS 0xFF000000
+#define STDOUT_BASEADDRESS 0xFF000000
+
+/******************************************************************/
+
+/* Platform specific definitions */
+
+/* Definitions for sleep timer configuration */
+#define XSLEEP_TIMER_IS_DEFAULT_TIMER
+
+
+/******************************************************************/
+/* Definitions for driver AVBUF */
+#define XPAR_XAVBUF_NUM_INSTANCES 1
+
+/* Definitions for peripheral PSU_DP */
+#define XPAR_PSU_DP_DEVICE_ID 0
+#define XPAR_PSU_DP_BASEADDR 0xFD4A0000
+#define XPAR_PSU_DP_HIGHADDR 0xFD4AFFFF
+
+
+/******************************************************************/
+
+/* Canonical definitions for peripheral PSU_DP */
+#define XPAR_XAVBUF_0_DEVICE_ID XPAR_PSU_DP_DEVICE_ID
+#define XPAR_XAVBUF_0_BASEADDR 0xFD4A0000
+#define XPAR_XAVBUF_0_HIGHADDR 0xFD4AFFFF
+
+
+/******************************************************************/
+
+/* Definitions for driver AXIPMON */
+#define XPAR_XAXIPMON_NUM_INSTANCES 4U
+
+/* Definitions for peripheral PSU_APM_0 */
+#define XPAR_PSU_APM_0_DEVICE_ID 0U
+#define XPAR_PSU_APM_0_BASEADDR 0xFD0B0000U
+#define XPAR_PSU_APM_0_HIGHADDR 0xFD0BFFFFU
+#define XPAR_PSU_APM_0_GLOBAL_COUNT_WIDTH 32U
+#define XPAR_PSU_APM_0_METRICS_SAMPLE_COUNT_WIDTH 32U
+#define XPAR_PSU_APM_0_ENABLE_EVENT_COUNT 1U
+#define XPAR_PSU_APM_0_NUM_MONITOR_SLOTS 6U
+#define XPAR_PSU_APM_0_NUM_OF_COUNTERS 10U
+#define XPAR_PSU_APM_0_HAVE_SAMPLED_METRIC_CNT 1U
+#define XPAR_PSU_APM_0_ENABLE_EVENT_LOG 0U
+#define XPAR_PSU_APM_0_FIFO_AXIS_DEPTH 32U
+#define XPAR_PSU_APM_0_FIFO_AXIS_TDATA_WIDTH 56U
+#define XPAR_PSU_APM_0_FIFO_AXIS_TID_WIDTH 1U
+#define XPAR_PSU_APM_0_METRIC_COUNT_SCALE 1U
+#define XPAR_PSU_APM_0_ENABLE_ADVANCED 1U
+#define XPAR_PSU_APM_0_ENABLE_PROFILE 0U
+#define XPAR_PSU_APM_0_ENABLE_TRACE 0U
+#define XPAR_PSU_APM_0_S_AXI4_BASEADDR 0x00000000U
+#define XPAR_PSU_APM_0_S_AXI4_HIGHADDR 0x00000000U
+#define XPAR_PSU_APM_0_ENABLE_32BIT_FILTER_ID 1U
+
+
+/* Definitions for peripheral PSU_APM_1 */
+#define XPAR_PSU_APM_1_DEVICE_ID 1U
+#define XPAR_PSU_APM_1_BASEADDR 0xFFA00000U
+#define XPAR_PSU_APM_1_HIGHADDR 0xFFA0FFFFU
+#define XPAR_PSU_APM_1_GLOBAL_COUNT_WIDTH 32U
+#define XPAR_PSU_APM_1_METRICS_SAMPLE_COUNT_WIDTH 32U
+#define XPAR_PSU_APM_1_ENABLE_EVENT_COUNT 1U
+#define XPAR_PSU_APM_1_NUM_MONITOR_SLOTS 1U
+#define XPAR_PSU_APM_1_NUM_OF_COUNTERS 3U
+#define XPAR_PSU_APM_1_HAVE_SAMPLED_METRIC_CNT 1U
+#define XPAR_PSU_APM_1_ENABLE_EVENT_LOG 0U
+#define XPAR_PSU_APM_1_FIFO_AXIS_DEPTH 32U
+#define XPAR_PSU_APM_1_FIFO_AXIS_TDATA_WIDTH 56U
+#define XPAR_PSU_APM_1_FIFO_AXIS_TID_WIDTH 1U
+#define XPAR_PSU_APM_1_METRIC_COUNT_SCALE 1U
+#define XPAR_PSU_APM_1_ENABLE_ADVANCED 1U
+#define XPAR_PSU_APM_1_ENABLE_PROFILE 0U
+#define XPAR_PSU_APM_1_ENABLE_TRACE 0U
+#define XPAR_PSU_APM_1_S_AXI4_BASEADDR 0x00000000U
+#define XPAR_PSU_APM_1_S_AXI4_HIGHADDR 0x00000000U
+#define XPAR_PSU_APM_1_ENABLE_32BIT_FILTER_ID 1U
+
+
+/* Definitions for peripheral PSU_APM_2 */
+#define XPAR_PSU_APM_2_DEVICE_ID 2U
+#define XPAR_PSU_APM_2_BASEADDR 0xFFA10000U
+#define XPAR_PSU_APM_2_HIGHADDR 0xFFA1FFFFU
+#define XPAR_PSU_APM_2_GLOBAL_COUNT_WIDTH 32U
+#define XPAR_PSU_APM_2_METRICS_SAMPLE_COUNT_WIDTH 32U
+#define XPAR_PSU_APM_2_ENABLE_EVENT_COUNT 1U
+#define XPAR_PSU_APM_2_NUM_MONITOR_SLOTS 1U
+#define XPAR_PSU_APM_2_NUM_OF_COUNTERS 3U
+#define XPAR_PSU_APM_2_HAVE_SAMPLED_METRIC_CNT 1U
+#define XPAR_PSU_APM_2_ENABLE_EVENT_LOG 0U
+#define XPAR_PSU_APM_2_FIFO_AXIS_DEPTH 32U
+#define XPAR_PSU_APM_2_FIFO_AXIS_TDATA_WIDTH 56U
+#define XPAR_PSU_APM_2_FIFO_AXIS_TID_WIDTH 1U
+#define XPAR_PSU_APM_2_METRIC_COUNT_SCALE 1U
+#define XPAR_PSU_APM_2_ENABLE_ADVANCED 1U
+#define XPAR_PSU_APM_2_ENABLE_PROFILE 0U
+#define XPAR_PSU_APM_2_ENABLE_TRACE 0U
+#define XPAR_PSU_APM_2_S_AXI4_BASEADDR 0x00000000U
+#define XPAR_PSU_APM_2_S_AXI4_HIGHADDR 0x00000000U
+#define XPAR_PSU_APM_2_ENABLE_32BIT_FILTER_ID 1U
+
+
+/* Definitions for peripheral PSU_APM_5 */
+#define XPAR_PSU_APM_5_DEVICE_ID 3U
+#define XPAR_PSU_APM_5_BASEADDR 0xFD490000U
+#define XPAR_PSU_APM_5_HIGHADDR 0xFD49FFFFU
+#define XPAR_PSU_APM_5_GLOBAL_COUNT_WIDTH 32U
+#define XPAR_PSU_APM_5_METRICS_SAMPLE_COUNT_WIDTH 32U
+#define XPAR_PSU_APM_5_ENABLE_EVENT_COUNT 1U
+#define XPAR_PSU_APM_5_NUM_MONITOR_SLOTS 1U
+#define XPAR_PSU_APM_5_NUM_OF_COUNTERS 3U
+#define XPAR_PSU_APM_5_HAVE_SAMPLED_METRIC_CNT 1U
+#define XPAR_PSU_APM_5_ENABLE_EVENT_LOG 0U
+#define XPAR_PSU_APM_5_FIFO_AXIS_DEPTH 32U
+#define XPAR_PSU_APM_5_FIFO_AXIS_TDATA_WIDTH 56U
+#define XPAR_PSU_APM_5_FIFO_AXIS_TID_WIDTH 1U
+#define XPAR_PSU_APM_5_METRIC_COUNT_SCALE 1U
+#define XPAR_PSU_APM_5_ENABLE_ADVANCED 1U
+#define XPAR_PSU_APM_5_ENABLE_PROFILE 0U
+#define XPAR_PSU_APM_5_ENABLE_TRACE 0U
+#define XPAR_PSU_APM_5_S_AXI4_BASEADDR 0x00000000U
+#define XPAR_PSU_APM_5_S_AXI4_HIGHADDR 0x00000000U
+#define XPAR_PSU_APM_5_ENABLE_32BIT_FILTER_ID 1U
+
+
+/******************************************************************/
+
+/* Canonical definitions for peripheral PSU_APM_0 */
+#define XPAR_AXIPMON_0_DEVICE_ID XPAR_PSU_APM_0_DEVICE_ID
+#define XPAR_AXIPMON_0_BASEADDR 0xFD0B0000U
+#define XPAR_AXIPMON_0_HIGHADDR 0xFD0BFFFFU
+#define XPAR_AXIPMON_0_GLOBAL_COUNT_WIDTH 32U
+#define XPAR_AXIPMON_0_METRICS_SAMPLE_COUNT_WIDTH 32U
+#define XPAR_AXIPMON_0_ENABLE_EVENT_COUNT 1U
+#define XPAR_AXIPMON_0_NUM_MONITOR_SLOTS 6U
+#define XPAR_AXIPMON_0_NUM_OF_COUNTERS 10U
+#define XPAR_AXIPMON_0_HAVE_SAMPLED_METRIC_CNT 1U
+#define XPAR_AXIPMON_0_ENABLE_EVENT_LOG 0U
+#define XPAR_AXIPMON_0_FIFO_AXIS_DEPTH 32U
+#define XPAR_AXIPMON_0_FIFO_AXIS_TDATA_WIDTH 56U
+#define XPAR_AXIPMON_0_FIFO_AXIS_TID_WIDTH 1U
+#define XPAR_AXIPMON_0_METRIC_COUNT_SCALE 1U
+#define XPAR_AXIPMON_0_ENABLE_ADVANCED 1U
+#define XPAR_AXIPMON_0_ENABLE_PROFILE 0U
+#define XPAR_AXIPMON_0_ENABLE_TRACE 0U
+#define XPAR_AXIPMON_0_S_AXI4_BASEADDR 0x00000000U
+#define XPAR_AXIPMON_0_S_AXI4_HIGHADDR 0x00000000U
+#define XPAR_AXIPMON_0_ENABLE_32BIT_FILTER_ID 1U
+
+/* Canonical definitions for peripheral PSU_APM_1 */
+#define XPAR_AXIPMON_1_DEVICE_ID XPAR_PSU_APM_1_DEVICE_ID
+#define XPAR_AXIPMON_1_BASEADDR 0xFFA00000U
+#define XPAR_AXIPMON_1_HIGHADDR 0xFFA0FFFFU
+#define XPAR_AXIPMON_1_GLOBAL_COUNT_WIDTH 32U
+#define XPAR_AXIPMON_1_METRICS_SAMPLE_COUNT_WIDTH 32U
+#define XPAR_AXIPMON_1_ENABLE_EVENT_COUNT 1U
+#define XPAR_AXIPMON_1_NUM_MONITOR_SLOTS 1U
+#define XPAR_AXIPMON_1_NUM_OF_COUNTERS 3U
+#define XPAR_AXIPMON_1_HAVE_SAMPLED_METRIC_CNT 1U
+#define XPAR_AXIPMON_1_ENABLE_EVENT_LOG 0U
+#define XPAR_AXIPMON_1_FIFO_AXIS_DEPTH 32U
+#define XPAR_AXIPMON_1_FIFO_AXIS_TDATA_WIDTH 56U
+#define XPAR_AXIPMON_1_FIFO_AXIS_TID_WIDTH 1U
+#define XPAR_AXIPMON_1_METRIC_COUNT_SCALE 1U
+#define XPAR_AXIPMON_1_ENABLE_ADVANCED 1U
+#define XPAR_AXIPMON_1_ENABLE_PROFILE 0U
+#define XPAR_AXIPMON_1_ENABLE_TRACE 0U
+#define XPAR_AXIPMON_1_S_AXI4_BASEADDR 0x00000000U
+#define XPAR_AXIPMON_1_S_AXI4_HIGHADDR 0x00000000U
+#define XPAR_AXIPMON_1_ENABLE_32BIT_FILTER_ID 1U
+
+/* Canonical definitions for peripheral PSU_APM_2 */
+#define XPAR_AXIPMON_2_DEVICE_ID XPAR_PSU_APM_2_DEVICE_ID
+#define XPAR_AXIPMON_2_BASEADDR 0xFFA10000U
+#define XPAR_AXIPMON_2_HIGHADDR 0xFFA1FFFFU
+#define XPAR_AXIPMON_2_GLOBAL_COUNT_WIDTH 32U
+#define XPAR_AXIPMON_2_METRICS_SAMPLE_COUNT_WIDTH 32U
+#define XPAR_AXIPMON_2_ENABLE_EVENT_COUNT 1U
+#define XPAR_AXIPMON_2_NUM_MONITOR_SLOTS 1U
+#define XPAR_AXIPMON_2_NUM_OF_COUNTERS 3U
+#define XPAR_AXIPMON_2_HAVE_SAMPLED_METRIC_CNT 1U
+#define XPAR_AXIPMON_2_ENABLE_EVENT_LOG 0U
+#define XPAR_AXIPMON_2_FIFO_AXIS_DEPTH 32U
+#define XPAR_AXIPMON_2_FIFO_AXIS_TDATA_WIDTH 56U
+#define XPAR_AXIPMON_2_FIFO_AXIS_TID_WIDTH 1U
+#define XPAR_AXIPMON_2_METRIC_COUNT_SCALE 1U
+#define XPAR_AXIPMON_2_ENABLE_ADVANCED 1U
+#define XPAR_AXIPMON_2_ENABLE_PROFILE 0U
+#define XPAR_AXIPMON_2_ENABLE_TRACE 0U
+#define XPAR_AXIPMON_2_S_AXI4_BASEADDR 0x00000000U
+#define XPAR_AXIPMON_2_S_AXI4_HIGHADDR 0x00000000U
+#define XPAR_AXIPMON_2_ENABLE_32BIT_FILTER_ID 1U
+
+/* Canonical definitions for peripheral PSU_APM_5 */
+#define XPAR_AXIPMON_3_DEVICE_ID XPAR_PSU_APM_5_DEVICE_ID
+#define XPAR_AXIPMON_3_BASEADDR 0xFD490000U
+#define XPAR_AXIPMON_3_HIGHADDR 0xFD49FFFFU
+#define XPAR_AXIPMON_3_GLOBAL_COUNT_WIDTH 32U
+#define XPAR_AXIPMON_3_METRICS_SAMPLE_COUNT_WIDTH 32U
+#define XPAR_AXIPMON_3_ENABLE_EVENT_COUNT 1U
+#define XPAR_AXIPMON_3_NUM_MONITOR_SLOTS 1U
+#define XPAR_AXIPMON_3_NUM_OF_COUNTERS 3U
+#define XPAR_AXIPMON_3_HAVE_SAMPLED_METRIC_CNT 1U
+#define XPAR_AXIPMON_3_ENABLE_EVENT_LOG 0U
+#define XPAR_AXIPMON_3_FIFO_AXIS_DEPTH 32U
+#define XPAR_AXIPMON_3_FIFO_AXIS_TDATA_WIDTH 56U
+#define XPAR_AXIPMON_3_FIFO_AXIS_TID_WIDTH 1U
+#define XPAR_AXIPMON_3_METRIC_COUNT_SCALE 1U
+#define XPAR_AXIPMON_3_ENABLE_ADVANCED 1U
+#define XPAR_AXIPMON_3_ENABLE_PROFILE 0U
+#define XPAR_AXIPMON_3_ENABLE_TRACE 0U
+#define XPAR_AXIPMON_3_S_AXI4_BASEADDR 0x00000000U
+#define XPAR_AXIPMON_3_S_AXI4_HIGHADDR 0x00000000U
+#define XPAR_AXIPMON_3_ENABLE_32BIT_FILTER_ID 1U
+
+
+/******************************************************************/
+
+/* Definitions for driver CANPS */
+#define XPAR_XCANPS_NUM_INSTANCES 1
+
+/* Definitions for peripheral PSU_CAN_1 */
+#define XPAR_PSU_CAN_1_DEVICE_ID 0
+#define XPAR_PSU_CAN_1_BASEADDR 0xFF070000
+#define XPAR_PSU_CAN_1_HIGHADDR 0xFF07FFFF
+#define XPAR_PSU_CAN_1_CAN_CLK_FREQ_HZ 99990005
+
+
+/******************************************************************/
+
+/* Canonical definitions for peripheral PSU_CAN_1 */
+#define XPAR_XCANPS_0_DEVICE_ID XPAR_PSU_CAN_1_DEVICE_ID
+#define XPAR_XCANPS_0_BASEADDR 0xFF070000
+#define XPAR_XCANPS_0_HIGHADDR 0xFF07FFFF
+#define XPAR_XCANPS_0_CAN_CLK_FREQ_HZ 99990005
+
+
+/******************************************************************/
+
+/* Definitions for driver CSUDMA */
+#define XPAR_XCSUDMA_NUM_INSTANCES 1
+
+/* Definitions for peripheral PSU_CSUDMA */
+#define XPAR_PSU_CSUDMA_DEVICE_ID 0
+#define XPAR_PSU_CSUDMA_BASEADDR 0xFFC80000
+#define XPAR_PSU_CSUDMA_HIGHADDR 0xFFC9FFFF
+#define XPAR_PSU_CSUDMA_CSUDMA_CLK_FREQ_HZ 0
+
+
+/******************************************************************/
+
+#define XPAR_PSU_CSUDMA_DMATYPE 0
+/* Canonical definitions for peripheral PSU_CSUDMA */
+#define XPAR_XCSUDMA_0_DEVICE_ID XPAR_PSU_CSUDMA_DEVICE_ID
+#define XPAR_XCSUDMA_0_BASEADDR 0xFFC80000
+#define XPAR_XCSUDMA_0_HIGHADDR 0xFFC9FFFF
+#define XPAR_XCSUDMA_0_CSUDMA_CLK_FREQ_HZ 0
+
+
+/******************************************************************/
+
+/* Definitions for driver DDRCPSU */
+#define XPAR_XDDRCPSU_NUM_INSTANCES 1
+
+/* Definitions for peripheral PSU_DDRC_0 */
+#define XPAR_PSU_DDRC_0_DEVICE_ID 0
+#define XPAR_PSU_DDRC_0_BASEADDR 0xFD070000
+#define XPAR_PSU_DDRC_0_HIGHADDR 0xFD070FFF
+#define XPAR_PSU_DDRC_0_HAS_ECC 0
+#define XPAR_PSU_DDRC_0_DDRC_CLK_FREQ_HZ 533280029
+
+
+/******************************************************************/
+
+#define XPAR_PSU_DDRC_0_DDR4_ADDR_MAPPING 0
+#define XPAR_PSU_DDRC_0_DDR_FREQ_MHZ 1066.560059
+#define XPAR_PSU_DDRC_0_VIDEO_BUFFER_SIZE 0
+#define XPAR_PSU_DDRC_0_BRC_MAPPING 0
+#define XPAR_DYNAMIC_DDR_ENABLED
+#define XPAR_PSU_DDRC_0_DDR_MEMORY_TYPE 4
+#define XPAR_PSU_DDRC_0_DDR_MEMORY_ADDRESS_MAP 0
+#define XPAR_PSU_DDRC_0_DDR_DATA_MASK_AND_DBI 7
+#define XPAR_PSU_DDRC_0_DDR_ADDRESS_MIRRORING 0
+#define XPAR_PSU_DDRC_0_DDR_2ND_CLOCK 0
+#define XPAR_PSU_DDRC_0_DDR_PARITY 0
+#define XPAR_PSU_DDRC_0_DDR_POWER_DOWN_ENABLE 0
+#define XPAR_PSU_DDRC_0_CLOCK_STOP 0
+#define XPAR_PSU_DDRC_0_DDR_LOW_POWER_AUTO_SELF_REFRESH 0
+#define XPAR_PSU_DDRC_0_DDR_TEMP_CONTROLLED_REFRESH 0
+#define XPAR_PSU_DDRC_0_DDR_MAX_OPERATING_TEMPARATURE 0
+#define XPAR_PSU_DDRC_0_DDR_FINE_GRANULARITY_REFRESH_MODE 0
+#define XPAR_PSU_DDRC_0_DDR_SELF_REFRESH_ABORT 0
+/* Canonical definitions for peripheral PSU_DDRC_0 */
+#define XPAR_DDRCPSU_0_DEVICE_ID XPAR_PSU_DDRC_0_DEVICE_ID
+#define XPAR_DDRCPSU_0_BASEADDR 0xFD070000
+#define XPAR_DDRCPSU_0_HIGHADDR 0xFD070FFF
+#define XPAR_DDRCPSU_0_DDRC_CLK_FREQ_HZ 533280029
+
+
+/******************************************************************/
+
+#define XPAR_DDRCPSU_0_DDR4_ADDR_MAPPING 0
+#define XPAR_DDRCPSU_0_DDR_FREQ_MHZ 1066.560059
+#define XPAR_DDRCPSU_0_VIDEO_BUFFER_SIZE 0
+#define XPAR_DDRCPSU_0_BRC_MAPPING 0
+#define XPAR_DDRCPSU_0_DDR_MEMORY_TYPE 4
+#define XPAR_DDRCPSU_0_DDR_MEMORY_ADDRESS_MAP 0
+#define XPAR_DDRCPSU_0_DDR_DATA_MASK_AND_DBI 7
+#define XPAR_DDRCPSU_0_DDR_ADDRESS_MIRRORING 0
+#define XPAR_DDRCPSU_0_DDR_2ND_CLOCK 0
+#define XPAR_DDRCPSU_0_DDR_PARITY 0
+#define XPAR_DDRCPSU_0_DDR_POWER_DOWN_ENABLE 0
+#define XPAR_DDRCPSU_0_CLOCK_STOP 0
+#define XPAR_DDRCPSU_0_DDR_LOW_POWER_AUTO_SELF_REFRESH 0
+#define XPAR_DDRCPSU_0_DDR_TEMP_CONTROLLED_REFRESH 0
+#define XPAR_DDRCPSU_0_DDR_MAX_OPERATING_TEMPARATURE 0
+#define XPAR_DDRCPSU_0_DDR_FINE_GRANULARITY_REFRESH_MODE 0
+#define XPAR_DDRCPSU_0_DDR_SELF_REFRESH_ABORT 0
+/* Definitions for driver DPDMA */
+#define XPAR_XDPDMA_NUM_INSTANCES 1
+
+/* Definitions for peripheral PSU_DPDMA */
+#define XPAR_PSU_DPDMA_DEVICE_ID 0
+#define XPAR_PSU_DPDMA_BASEADDR 0xFD4C0000
+#define XPAR_PSU_DPDMA_HIGHADDR 0xFD4CFFFF
+
+
+/******************************************************************/
+
+/* Canonical definitions for peripheral PSU_DPDMA */
+#define XPAR_XDPDMA_0_DEVICE_ID XPAR_PSU_DPDMA_DEVICE_ID
+#define XPAR_XDPDMA_0_BASEADDR 0xFD4C0000
+#define XPAR_XDPDMA_0_HIGHADDR 0xFD4CFFFF
+
+
+/******************************************************************/
+
+/* Definitions for driver EMACPS */
+#define XPAR_XEMACPS_NUM_INSTANCES 1
+
+/* Definitions for peripheral PSU_ETHERNET_3 */
+#define XPAR_PSU_ETHERNET_3_DEVICE_ID 0
+#define XPAR_PSU_ETHERNET_3_BASEADDR 0xFF0E0000
+#define XPAR_PSU_ETHERNET_3_HIGHADDR 0xFF0EFFFF
+#define XPAR_PSU_ETHERNET_3_ENET_CLK_FREQ_HZ 124987511
+#define XPAR_PSU_ETHERNET_3_ENET_SLCR_1000MBPS_DIV0 12
+#define XPAR_PSU_ETHERNET_3_ENET_SLCR_1000MBPS_DIV1 1
+#define XPAR_PSU_ETHERNET_3_ENET_SLCR_100MBPS_DIV0 60
+#define XPAR_PSU_ETHERNET_3_ENET_SLCR_100MBPS_DIV1 1
+#define XPAR_PSU_ETHERNET_3_ENET_SLCR_10MBPS_DIV0 60
+#define XPAR_PSU_ETHERNET_3_ENET_SLCR_10MBPS_DIV1 10
+#define XPAR_PSU_ETHERNET_3_ENET_TSU_CLK_FREQ_HZ 249975021
+
+
+/******************************************************************/
+
+#define XPAR_PSU_ETHERNET_3_IS_CACHE_COHERENT 0
+#define XPAR_XEMACPS_0_IS_CACHE_COHERENT 0
+#define XPAR_PSU_ETHERNET_3_REF_CLK 0xff
+/* Canonical definitions for peripheral PSU_ETHERNET_3 */
+#define XPAR_XEMACPS_0_DEVICE_ID XPAR_PSU_ETHERNET_3_DEVICE_ID
+#define XPAR_XEMACPS_0_BASEADDR 0xFF0E0000
+#define XPAR_XEMACPS_0_HIGHADDR 0xFF0EFFFF
+#define XPAR_XEMACPS_0_ENET_CLK_FREQ_HZ 124987511
+#define XPAR_XEMACPS_0_ENET_SLCR_1000Mbps_DIV0 12
+#define XPAR_XEMACPS_0_ENET_SLCR_1000Mbps_DIV1 1
+#define XPAR_XEMACPS_0_ENET_SLCR_100Mbps_DIV0 60
+#define XPAR_XEMACPS_0_ENET_SLCR_100Mbps_DIV1 1
+#define XPAR_XEMACPS_0_ENET_SLCR_10Mbps_DIV0 60
+#define XPAR_XEMACPS_0_ENET_SLCR_10Mbps_DIV1 10
+#define XPAR_XEMACPS_0_ENET_TSU_CLK_FREQ_HZ 249975021
+
+
+/******************************************************************/
+
+
+/* Definitions for peripheral PSU_AFI_0 */
+#define XPAR_PSU_AFI_0_S_AXI_BASEADDR 0xFD360000
+#define XPAR_PSU_AFI_0_S_AXI_HIGHADDR 0xFD36FFFF
+
+
+/* Definitions for peripheral PSU_AFI_1 */
+#define XPAR_PSU_AFI_1_S_AXI_BASEADDR 0xFD370000
+#define XPAR_PSU_AFI_1_S_AXI_HIGHADDR 0xFD37FFFF
+
+
+/* Definitions for peripheral PSU_AFI_2 */
+#define XPAR_PSU_AFI_2_S_AXI_BASEADDR 0xFD380000
+#define XPAR_PSU_AFI_2_S_AXI_HIGHADDR 0xFD38FFFF
+
+
+/* Definitions for peripheral PSU_AFI_3 */
+#define XPAR_PSU_AFI_3_S_AXI_BASEADDR 0xFD390000
+#define XPAR_PSU_AFI_3_S_AXI_HIGHADDR 0xFD39FFFF
+
+
+/* Definitions for peripheral PSU_AFI_4 */
+#define XPAR_PSU_AFI_4_S_AXI_BASEADDR 0xFD3A0000
+#define XPAR_PSU_AFI_4_S_AXI_HIGHADDR 0xFD3AFFFF
+
+
+/* Definitions for peripheral PSU_AFI_5 */
+#define XPAR_PSU_AFI_5_S_AXI_BASEADDR 0xFD3B0000
+#define XPAR_PSU_AFI_5_S_AXI_HIGHADDR 0xFD3BFFFF
+
+
+/* Definitions for peripheral PSU_AFI_6 */
+#define XPAR_PSU_AFI_6_S_AXI_BASEADDR 0xFF9B0000
+#define XPAR_PSU_AFI_6_S_AXI_HIGHADDR 0xFF9BFFFF
+
+
+/* Definitions for peripheral PSU_APU */
+#define XPAR_PSU_APU_S_AXI_BASEADDR 0xFD5C0000
+#define XPAR_PSU_APU_S_AXI_HIGHADDR 0xFD5CFFFF
+
+
+/* Definitions for peripheral PSU_BBRAM_0 */
+#define XPAR_PSU_BBRAM_0_S_AXI_BASEADDR 0xFFCD0000
+#define XPAR_PSU_BBRAM_0_S_AXI_HIGHADDR 0xFFCDFFFF
+
+
+/* Definitions for peripheral PSU_CCI_GPV */
+#define XPAR_PSU_CCI_GPV_S_AXI_BASEADDR 0xFD6E0000
+#define XPAR_PSU_CCI_GPV_S_AXI_HIGHADDR 0xFD6EFFFF
+
+
+/* Definitions for peripheral PSU_CCI_REG */
+#define XPAR_PSU_CCI_REG_S_AXI_BASEADDR 0xFD5E0000
+#define XPAR_PSU_CCI_REG_S_AXI_HIGHADDR 0xFD5EFFFF
+
+
+/* Definitions for peripheral PSU_CRL_APB */
+#define XPAR_PSU_CRL_APB_S_AXI_BASEADDR 0xFF5E0000
+#define XPAR_PSU_CRL_APB_S_AXI_HIGHADDR 0xFF85FFFF
+
+
+/* Definitions for peripheral PSU_CSU_0 */
+#define XPAR_PSU_CSU_0_S_AXI_BASEADDR 0xFFCA0000
+#define XPAR_PSU_CSU_0_S_AXI_HIGHADDR 0xFFCAFFFF
+
+
+/* Definitions for peripheral PSU_CTRL_IPI */
+#define XPAR_PSU_CTRL_IPI_S_AXI_BASEADDR 0xFF380000
+#define XPAR_PSU_CTRL_IPI_S_AXI_HIGHADDR 0xFF3FFFFF
+
+
+/* Definitions for peripheral PSU_DDR_0 */
+#define XPAR_PSU_DDR_0_S_AXI_BASEADDR 0x00000000
+#define XPAR_PSU_DDR_0_S_AXI_HIGHADDR 0x7FFFFFFF
+
+
+/* Definitions for peripheral PSU_DDR_PHY */
+#define XPAR_PSU_DDR_PHY_S_AXI_BASEADDR 0xFD080000
+#define XPAR_PSU_DDR_PHY_S_AXI_HIGHADDR 0xFD08FFFF
+
+
+/* Definitions for peripheral PSU_DDR_QOS_CTRL */
+#define XPAR_PSU_DDR_QOS_CTRL_S_AXI_BASEADDR 0xFD090000
+#define XPAR_PSU_DDR_QOS_CTRL_S_AXI_HIGHADDR 0xFD09FFFF
+
+
+/* Definitions for peripheral PSU_DDR_XMPU0_CFG */
+#define XPAR_PSU_DDR_XMPU0_CFG_S_AXI_BASEADDR 0xFD000000
+#define XPAR_PSU_DDR_XMPU0_CFG_S_AXI_HIGHADDR 0xFD00FFFF
+
+
+/* Definitions for peripheral PSU_DDR_XMPU1_CFG */
+#define XPAR_PSU_DDR_XMPU1_CFG_S_AXI_BASEADDR 0xFD010000
+#define XPAR_PSU_DDR_XMPU1_CFG_S_AXI_HIGHADDR 0xFD01FFFF
+
+
+/* Definitions for peripheral PSU_DDR_XMPU2_CFG */
+#define XPAR_PSU_DDR_XMPU2_CFG_S_AXI_BASEADDR 0xFD020000
+#define XPAR_PSU_DDR_XMPU2_CFG_S_AXI_HIGHADDR 0xFD02FFFF
+
+
+/* Definitions for peripheral PSU_DDR_XMPU3_CFG */
+#define XPAR_PSU_DDR_XMPU3_CFG_S_AXI_BASEADDR 0xFD030000
+#define XPAR_PSU_DDR_XMPU3_CFG_S_AXI_HIGHADDR 0xFD03FFFF
+
+
+/* Definitions for peripheral PSU_DDR_XMPU4_CFG */
+#define XPAR_PSU_DDR_XMPU4_CFG_S_AXI_BASEADDR 0xFD040000
+#define XPAR_PSU_DDR_XMPU4_CFG_S_AXI_HIGHADDR 0xFD04FFFF
+
+
+/* Definitions for peripheral PSU_DDR_XMPU5_CFG */
+#define XPAR_PSU_DDR_XMPU5_CFG_S_AXI_BASEADDR 0xFD050000
+#define XPAR_PSU_DDR_XMPU5_CFG_S_AXI_HIGHADDR 0xFD05FFFF
+
+
+/* Definitions for peripheral PSU_EFUSE */
+#define XPAR_PSU_EFUSE_S_AXI_BASEADDR 0xFFCC0000
+#define XPAR_PSU_EFUSE_S_AXI_HIGHADDR 0xFFCCFFFF
+
+
+/* Definitions for peripheral PSU_FPD_GPV */
+#define XPAR_PSU_FPD_GPV_S_AXI_BASEADDR 0xFD700000
+#define XPAR_PSU_FPD_GPV_S_AXI_HIGHADDR 0xFD7FFFFF
+
+
+/* Definitions for peripheral PSU_FPD_SLCR */
+#define XPAR_PSU_FPD_SLCR_S_AXI_BASEADDR 0xFD610000
+#define XPAR_PSU_FPD_SLCR_S_AXI_HIGHADDR 0xFD68FFFF
+
+
+/* Definitions for peripheral PSU_FPD_SLCR_SECURE */
+#define XPAR_PSU_FPD_SLCR_SECURE_S_AXI_BASEADDR 0xFD690000
+#define XPAR_PSU_FPD_SLCR_SECURE_S_AXI_HIGHADDR 0xFD6CFFFF
+
+
+/* Definitions for peripheral PSU_FPD_XMPU_CFG */
+#define XPAR_PSU_FPD_XMPU_CFG_S_AXI_BASEADDR 0xFD5D0000
+#define XPAR_PSU_FPD_XMPU_CFG_S_AXI_HIGHADDR 0xFD5DFFFF
+
+
+/* Definitions for peripheral PSU_FPD_XMPU_SINK */
+#define XPAR_PSU_FPD_XMPU_SINK_S_AXI_BASEADDR 0xFD4F0000
+#define XPAR_PSU_FPD_XMPU_SINK_S_AXI_HIGHADDR 0xFD4FFFFF
+
+
+/* Definitions for peripheral PSU_GPU */
+#define XPAR_PSU_GPU_S_AXI_BASEADDR 0xFD4B0000
+#define XPAR_PSU_GPU_S_AXI_HIGHADDR 0xFD4BFFFF
+
+
+/* Definitions for peripheral PSU_IOU_SCNTR */
+#define XPAR_PSU_IOU_SCNTR_S_AXI_BASEADDR 0xFF250000
+#define XPAR_PSU_IOU_SCNTR_S_AXI_HIGHADDR 0xFF25FFFF
+
+
+/* Definitions for peripheral PSU_IOU_SCNTRS */
+#define XPAR_PSU_IOU_SCNTRS_S_AXI_BASEADDR 0xFF260000
+#define XPAR_PSU_IOU_SCNTRS_S_AXI_HIGHADDR 0xFF26FFFF
+
+
+/* Definitions for peripheral PSU_IOUSECURE_SLCR */
+#define XPAR_PSU_IOUSECURE_SLCR_S_AXI_BASEADDR 0xFF240000
+#define XPAR_PSU_IOUSECURE_SLCR_S_AXI_HIGHADDR 0xFF24FFFF
+
+
+/* Definitions for peripheral PSU_IOUSLCR_0 */
+#define XPAR_PSU_IOUSLCR_0_S_AXI_BASEADDR 0xFF180000
+#define XPAR_PSU_IOUSLCR_0_S_AXI_HIGHADDR 0xFF23FFFF
+
+
+/* Definitions for peripheral PSU_LPD_SLCR */
+#define XPAR_PSU_LPD_SLCR_S_AXI_BASEADDR 0xFF410000
+#define XPAR_PSU_LPD_SLCR_S_AXI_HIGHADDR 0xFF4AFFFF
+
+
+/* Definitions for peripheral PSU_LPD_SLCR_SECURE */
+#define XPAR_PSU_LPD_SLCR_SECURE_S_AXI_BASEADDR 0xFF4B0000
+#define XPAR_PSU_LPD_SLCR_SECURE_S_AXI_HIGHADDR 0xFF4DFFFF
+
+
+/* Definitions for peripheral PSU_LPD_XPPU */
+#define XPAR_PSU_LPD_XPPU_S_AXI_BASEADDR 0xFF980000
+#define XPAR_PSU_LPD_XPPU_S_AXI_HIGHADDR 0xFF99FFFF
+
+
+/* Definitions for peripheral PSU_LPD_XPPU_SINK */
+#define XPAR_PSU_LPD_XPPU_SINK_S_AXI_BASEADDR 0xFF9C0000
+#define XPAR_PSU_LPD_XPPU_SINK_S_AXI_HIGHADDR 0xFF9CFFFF
+
+
+/* Definitions for peripheral PSU_MBISTJTAG */
+#define XPAR_PSU_MBISTJTAG_S_AXI_BASEADDR 0xFFCF0000
+#define XPAR_PSU_MBISTJTAG_S_AXI_HIGHADDR 0xFFCFFFFF
+
+
+/* Definitions for peripheral PSU_MESSAGE_BUFFERS */
+#define XPAR_PSU_MESSAGE_BUFFERS_S_AXI_BASEADDR 0xFF990000
+#define XPAR_PSU_MESSAGE_BUFFERS_S_AXI_HIGHADDR 0xFF99FFFF
+
+
+/* Definitions for peripheral PSU_OCM */
+#define XPAR_PSU_OCM_S_AXI_BASEADDR 0xFF960000
+#define XPAR_PSU_OCM_S_AXI_HIGHADDR 0xFF96FFFF
+
+
+/* Definitions for peripheral PSU_OCM_RAM_0 */
+#define XPAR_PSU_OCM_RAM_0_S_AXI_BASEADDR 0xFFFC0000
+#define XPAR_PSU_OCM_RAM_0_S_AXI_HIGHADDR 0xFFFFFFFF
+
+
+/* Definitions for peripheral PSU_OCM_XMPU_CFG */
+#define XPAR_PSU_OCM_XMPU_CFG_S_AXI_BASEADDR 0xFFA70000
+#define XPAR_PSU_OCM_XMPU_CFG_S_AXI_HIGHADDR 0xFFA7FFFF
+
+
+/* Definitions for peripheral PSU_PMU_GLOBAL_0 */
+#define XPAR_PSU_PMU_GLOBAL_0_S_AXI_BASEADDR 0xFFD80000
+#define XPAR_PSU_PMU_GLOBAL_0_S_AXI_HIGHADDR 0xFFDBFFFF
+
+
+/* Definitions for peripheral PSU_PMU_IOMODULE */
+#define XPAR_PSU_PMU_IOMODULE_S_AXI_BASEADDR 0xFFD40000
+#define XPAR_PSU_PMU_IOMODULE_S_AXI_HIGHADDR 0xFFD5FFFF
+
+
+/* Definitions for peripheral PSU_PMU_RAM */
+#define XPAR_PSU_PMU_RAM_S_AXI_BASEADDR 0xFFDC0000
+#define XPAR_PSU_PMU_RAM_S_AXI_HIGHADDR 0xFFDDFFFF
+
+
+/* Definitions for peripheral PSU_QSPI_LINEAR_0 */
+#define XPAR_PSU_QSPI_LINEAR_0_S_AXI_BASEADDR 0xC0000000
+#define XPAR_PSU_QSPI_LINEAR_0_S_AXI_HIGHADDR 0xDFFFFFFF
+
+
+/* Definitions for peripheral PSU_R5_0_ATCM_GLOBAL */
+#define XPAR_PSU_R5_0_ATCM_GLOBAL_S_AXI_BASEADDR 0xFFE00000
+#define XPAR_PSU_R5_0_ATCM_GLOBAL_S_AXI_HIGHADDR 0xFFE0FFFF
+
+
+/* Definitions for peripheral PSU_R5_0_BTCM_GLOBAL */
+#define XPAR_PSU_R5_0_BTCM_GLOBAL_S_AXI_BASEADDR 0xFFE20000
+#define XPAR_PSU_R5_0_BTCM_GLOBAL_S_AXI_HIGHADDR 0xFFE2FFFF
+
+
+/* Definitions for peripheral PSU_R5_1_ATCM_GLOBAL */
+#define XPAR_PSU_R5_1_ATCM_GLOBAL_S_AXI_BASEADDR 0xFFE90000
+#define XPAR_PSU_R5_1_ATCM_GLOBAL_S_AXI_HIGHADDR 0xFFE9FFFF
+
+
+/* Definitions for peripheral PSU_R5_1_BTCM_GLOBAL */
+#define XPAR_PSU_R5_1_BTCM_GLOBAL_S_AXI_BASEADDR 0xFFEB0000
+#define XPAR_PSU_R5_1_BTCM_GLOBAL_S_AXI_HIGHADDR 0xFFEBFFFF
+
+
+/* Definitions for peripheral PSU_R5_TCM_RAM_GLOBAL */
+#define XPAR_PSU_R5_TCM_RAM_GLOBAL_S_AXI_BASEADDR 0xFFE00000
+#define XPAR_PSU_R5_TCM_RAM_GLOBAL_S_AXI_HIGHADDR 0xFFE3FFFF
+
+
+/* Definitions for peripheral PSU_RPU */
+#define XPAR_PSU_RPU_S_AXI_BASEADDR 0xFF9A0000
+#define XPAR_PSU_RPU_S_AXI_HIGHADDR 0xFF9AFFFF
+
+
+/* Definitions for peripheral PSU_RSA */
+#define XPAR_PSU_RSA_S_AXI_BASEADDR 0xFFCE0000
+#define XPAR_PSU_RSA_S_AXI_HIGHADDR 0xFFCEFFFF
+
+
+/* Definitions for peripheral PSU_SATA */
+#define XPAR_PSU_SATA_S_AXI_BASEADDR 0xFD0C0000
+#define XPAR_PSU_SATA_S_AXI_HIGHADDR 0xFD0CFFFF
+
+
+/* Definitions for peripheral PSU_SERDES */
+#define XPAR_PSU_SERDES_S_AXI_BASEADDR 0xFD400000
+#define XPAR_PSU_SERDES_S_AXI_HIGHADDR 0xFD47FFFF
+
+
+/* Definitions for peripheral PSU_SIOU */
+#define XPAR_PSU_SIOU_S_AXI_BASEADDR 0xFD3D0000
+#define XPAR_PSU_SIOU_S_AXI_HIGHADDR 0xFD3DFFFF
+
+
+/* Definitions for peripheral PSU_SMMU_GPV */
+#define XPAR_PSU_SMMU_GPV_S_AXI_BASEADDR 0xFD800000
+#define XPAR_PSU_SMMU_GPV_S_AXI_HIGHADDR 0xFDFFFFFF
+
+
+/* Definitions for peripheral PSU_SMMU_REG */
+#define XPAR_PSU_SMMU_REG_S_AXI_BASEADDR 0xFD5F0000
+#define XPAR_PSU_SMMU_REG_S_AXI_HIGHADDR 0xFD5FFFFF
+
+
+/* Definitions for peripheral PSU_USB_0 */
+#define XPAR_PSU_USB_0_S_AXI_BASEADDR 0xFF9D0000
+#define XPAR_PSU_USB_0_S_AXI_HIGHADDR 0xFF9DFFFF
+
+
+/******************************************************************/
+
+/* Definitions for driver GPIOPS */
+#define XPAR_XGPIOPS_NUM_INSTANCES 1
+
+/* Definitions for peripheral PSU_GPIO_0 */
+#define XPAR_PSU_GPIO_0_DEVICE_ID 0
+#define XPAR_PSU_GPIO_0_BASEADDR 0xFF0A0000
+#define XPAR_PSU_GPIO_0_HIGHADDR 0xFF0AFFFF
+
+
+/******************************************************************/
+
+/* Canonical definitions for peripheral PSU_GPIO_0 */
+#define XPAR_XGPIOPS_0_DEVICE_ID XPAR_PSU_GPIO_0_DEVICE_ID
+#define XPAR_XGPIOPS_0_BASEADDR 0xFF0A0000
+#define XPAR_XGPIOPS_0_HIGHADDR 0xFF0AFFFF
+
+
+/******************************************************************/
+
+/* Definitions for driver IICPS */
+#define XPAR_XIICPS_NUM_INSTANCES 2
+
+/* Definitions for peripheral PSU_I2C_0 */
+#define XPAR_PSU_I2C_0_DEVICE_ID 0
+#define XPAR_PSU_I2C_0_BASEADDR 0xFF020000
+#define XPAR_PSU_I2C_0_HIGHADDR 0xFF02FFFF
+#define XPAR_PSU_I2C_0_I2C_CLK_FREQ_HZ 99990005
+
+
+/* Definitions for peripheral PSU_I2C_1 */
+#define XPAR_PSU_I2C_1_DEVICE_ID 1
+#define XPAR_PSU_I2C_1_BASEADDR 0xFF030000
+#define XPAR_PSU_I2C_1_HIGHADDR 0xFF03FFFF
+#define XPAR_PSU_I2C_1_I2C_CLK_FREQ_HZ 99990005
+
+
+/******************************************************************/
+
+/* Canonical definitions for peripheral PSU_I2C_0 */
+#define XPAR_XIICPS_0_DEVICE_ID XPAR_PSU_I2C_0_DEVICE_ID
+#define XPAR_XIICPS_0_BASEADDR 0xFF020000
+#define XPAR_XIICPS_0_HIGHADDR 0xFF02FFFF
+#define XPAR_XIICPS_0_I2C_CLK_FREQ_HZ 99990005
+
+/* Canonical definitions for peripheral PSU_I2C_1 */
+#define XPAR_XIICPS_1_DEVICE_ID XPAR_PSU_I2C_1_DEVICE_ID
+#define XPAR_XIICPS_1_BASEADDR 0xFF030000
+#define XPAR_XIICPS_1_HIGHADDR 0xFF03FFFF
+#define XPAR_XIICPS_1_I2C_CLK_FREQ_HZ 99990005
+
+
+/******************************************************************/
+
+/* Definition for input Clock */
+#define XPAR_PSU_I2C_0_REF_CLK I2C0_REF
+/* Definition for input Clock */
+#define XPAR_PSU_I2C_1_REF_CLK I2C1_REF
+#define XPAR_XIPIPSU_NUM_INSTANCES 4U
+
+/* Parameter definitions for peripheral psu_ipi_3 */
+#define XPAR_PSU_IPI_3_DEVICE_ID 0U
+#define XPAR_PSU_IPI_3_S_AXI_BASEADDR 0xFF330000U
+#define XPAR_PSU_IPI_3_BIT_MASK 0x00010000U
+#define XPAR_PSU_IPI_3_BUFFER_INDEX 7U
+#define XPAR_PSU_IPI_3_INT_ID 0U
+
+/* Parameter definitions for peripheral psu_ipi_4 */
+#define XPAR_PSU_IPI_4_DEVICE_ID 1U
+#define XPAR_PSU_IPI_4_S_AXI_BASEADDR 0xFF331000U
+#define XPAR_PSU_IPI_4_BIT_MASK 0x00020000U
+#define XPAR_PSU_IPI_4_BUFFER_INDEX 7U
+#define XPAR_PSU_IPI_4_INT_ID 0U
+
+/* Parameter definitions for peripheral psu_ipi_5 */
+#define XPAR_PSU_IPI_5_DEVICE_ID 2U
+#define XPAR_PSU_IPI_5_S_AXI_BASEADDR 0xFF332000U
+#define XPAR_PSU_IPI_5_BIT_MASK 0x00040000U
+#define XPAR_PSU_IPI_5_BUFFER_INDEX 7U
+#define XPAR_PSU_IPI_5_INT_ID 0U
+
+/* Parameter definitions for peripheral psu_ipi_6 */
+#define XPAR_PSU_IPI_6_DEVICE_ID 3U
+#define XPAR_PSU_IPI_6_S_AXI_BASEADDR 0xFF333000U
+#define XPAR_PSU_IPI_6_BIT_MASK 0x00080000U
+#define XPAR_PSU_IPI_6_BUFFER_INDEX 7U
+#define XPAR_PSU_IPI_6_INT_ID 0U
+
+/* Canonical definitions for peripheral psu_ipi_3 */
+#define XPAR_XIPIPSU_0_DEVICE_ID XPAR_PSU_IPI_3_DEVICE_ID
+#define XPAR_XIPIPSU_0_BASE_ADDRESS XPAR_PSU_IPI_3_S_AXI_BASEADDR
+#define XPAR_XIPIPSU_0_BIT_MASK XPAR_PSU_IPI_3_BIT_MASK
+#define XPAR_XIPIPSU_0_BUFFER_INDEX XPAR_PSU_IPI_3_BUFFER_INDEX
+#define XPAR_XIPIPSU_0_INT_ID XPAR_PSU_IPI_3_INT_ID
+
+/* Canonical definitions for peripheral psu_ipi_4 */
+#define XPAR_XIPIPSU_1_DEVICE_ID XPAR_PSU_IPI_4_DEVICE_ID
+#define XPAR_XIPIPSU_1_BASE_ADDRESS XPAR_PSU_IPI_4_S_AXI_BASEADDR
+#define XPAR_XIPIPSU_1_BIT_MASK XPAR_PSU_IPI_4_BIT_MASK
+#define XPAR_XIPIPSU_1_BUFFER_INDEX XPAR_PSU_IPI_4_BUFFER_INDEX
+#define XPAR_XIPIPSU_1_INT_ID XPAR_PSU_IPI_4_INT_ID
+
+/* Canonical definitions for peripheral psu_ipi_5 */
+#define XPAR_XIPIPSU_2_DEVICE_ID XPAR_PSU_IPI_5_DEVICE_ID
+#define XPAR_XIPIPSU_2_BASE_ADDRESS XPAR_PSU_IPI_5_S_AXI_BASEADDR
+#define XPAR_XIPIPSU_2_BIT_MASK XPAR_PSU_IPI_5_BIT_MASK
+#define XPAR_XIPIPSU_2_BUFFER_INDEX XPAR_PSU_IPI_5_BUFFER_INDEX
+#define XPAR_XIPIPSU_2_INT_ID XPAR_PSU_IPI_5_INT_ID
+
+/* Canonical definitions for peripheral psu_ipi_6 */
+#define XPAR_XIPIPSU_3_DEVICE_ID XPAR_PSU_IPI_6_DEVICE_ID
+#define XPAR_XIPIPSU_3_BASE_ADDRESS XPAR_PSU_IPI_6_S_AXI_BASEADDR
+#define XPAR_XIPIPSU_3_BIT_MASK XPAR_PSU_IPI_6_BIT_MASK
+#define XPAR_XIPIPSU_3_BUFFER_INDEX XPAR_PSU_IPI_6_BUFFER_INDEX
+#define XPAR_XIPIPSU_3_INT_ID XPAR_PSU_IPI_6_INT_ID
+
+#define XPAR_XIPIPSU_NUM_TARGETS 7U
+
+#define XPAR_PSU_IPI_0_BIT_MASK 0x00000001U
+#define XPAR_PSU_IPI_0_BUFFER_INDEX 2U
+#define XPAR_PSU_IPI_1_BIT_MASK 0x00000100U
+#define XPAR_PSU_IPI_1_BUFFER_INDEX 0U
+#define XPAR_PSU_IPI_2_BIT_MASK 0x00000200U
+#define XPAR_PSU_IPI_2_BUFFER_INDEX 1U
+#define XPAR_PSU_IPI_3_BIT_MASK 0x00010000U
+#define XPAR_PSU_IPI_3_BUFFER_INDEX 7U
+#define XPAR_PSU_IPI_4_BIT_MASK 0x00020000U
+#define XPAR_PSU_IPI_4_BUFFER_INDEX 7U
+#define XPAR_PSU_IPI_5_BIT_MASK 0x00040000U
+#define XPAR_PSU_IPI_5_BUFFER_INDEX 7U
+#define XPAR_PSU_IPI_6_BIT_MASK 0x00080000U
+#define XPAR_PSU_IPI_6_BUFFER_INDEX 7U
+/* Target List for referring to processor IPI Targets */
+
+#define XPAR_XIPIPS_TARGET_PSU_CORTEXA53_0_CH0_MASK XPAR_PSU_IPI_0_BIT_MASK
+#define XPAR_XIPIPS_TARGET_PSU_CORTEXA53_0_CH0_INDEX 0U
+
+#define XPAR_XIPIPS_TARGET_PSU_CORTEXA53_1_CH0_MASK XPAR_PSU_IPI_0_BIT_MASK
+#define XPAR_XIPIPS_TARGET_PSU_CORTEXA53_1_CH0_INDEX 0U
+
+#define XPAR_XIPIPS_TARGET_PSU_CORTEXA53_2_CH0_MASK XPAR_PSU_IPI_0_BIT_MASK
+#define XPAR_XIPIPS_TARGET_PSU_CORTEXA53_2_CH0_INDEX 0U
+
+#define XPAR_XIPIPS_TARGET_PSU_CORTEXA53_3_CH0_MASK XPAR_PSU_IPI_0_BIT_MASK
+#define XPAR_XIPIPS_TARGET_PSU_CORTEXA53_3_CH0_INDEX 0U
+
+#define XPAR_XIPIPS_TARGET_PSU_CORTEXR5_0_CH0_MASK XPAR_PSU_IPI_1_BIT_MASK
+#define XPAR_XIPIPS_TARGET_PSU_CORTEXR5_0_CH0_INDEX 1U
+
+#define XPAR_XIPIPS_TARGET_PSU_CORTEXR5_1_CH0_MASK XPAR_PSU_IPI_2_BIT_MASK
+#define XPAR_XIPIPS_TARGET_PSU_CORTEXR5_1_CH0_INDEX 2U
+
+#define XPAR_XIPIPS_TARGET_PSU_PMU_0_CH0_MASK XPAR_PSU_IPI_3_BIT_MASK
+#define XPAR_XIPIPS_TARGET_PSU_PMU_0_CH0_INDEX 3U
+#define XPAR_XIPIPS_TARGET_PSU_PMU_0_CH1_MASK XPAR_PSU_IPI_4_BIT_MASK
+#define XPAR_XIPIPS_TARGET_PSU_PMU_0_CH1_INDEX 4U
+#define XPAR_XIPIPS_TARGET_PSU_PMU_0_CH2_MASK XPAR_PSU_IPI_5_BIT_MASK
+#define XPAR_XIPIPS_TARGET_PSU_PMU_0_CH2_INDEX 5U
+#define XPAR_XIPIPS_TARGET_PSU_PMU_0_CH3_MASK XPAR_PSU_IPI_6_BIT_MASK
+#define XPAR_XIPIPS_TARGET_PSU_PMU_0_CH3_INDEX 6U
+
+/* Definitions for driver PCIEPSU */
+#define XPAR_XPCIEPSU_NUM_INSTANCES 6
+
+/* Definitions for peripheral PSU_PCIE */
+#define XPAR_PSU_PCIE_DEVICE_ID 0
+#define XPAR_PSU_PCIE_BASEADDR 0xFD0E0000
+#define XPAR_PSU_PCIE_HIGHADDR 0xFD0EFFFF
+
+
+/* Definitions for peripheral PSU_PCIE_ATTRIB_0 */
+#define XPAR_PSU_PCIE_ATTRIB_0_DEVICE_ID 1
+#define XPAR_PSU_PCIE_ATTRIB_0_BASEADDR 0xFD480000
+#define XPAR_PSU_PCIE_ATTRIB_0_HIGHADDR 0xFD48FFFF
+
+
+/* Definitions for peripheral PSU_PCIE_DMA */
+#define XPAR_PSU_PCIE_DMA_DEVICE_ID 2
+#define XPAR_PSU_PCIE_DMA_BASEADDR 0xFD0F0000
+#define XPAR_PSU_PCIE_DMA_HIGHADDR 0xFD0FFFFF
+
+
+/* Definitions for peripheral PSU_PCIE_HIGH1 */
+#define XPAR_PSU_PCIE_HIGH1_DEVICE_ID 3
+#define XPAR_PSU_PCIE_HIGH1_BASEADDR 0x600000000
+#define XPAR_PSU_PCIE_HIGH1_HIGHADDR 0x7FFFFFFFF
+
+
+/* Definitions for peripheral PSU_PCIE_HIGH2 */
+#define XPAR_PSU_PCIE_HIGH2_DEVICE_ID 4
+#define XPAR_PSU_PCIE_HIGH2_BASEADDR 0x8000000000
+#define XPAR_PSU_PCIE_HIGH2_HIGHADDR 0xBFFFFFFFFF
+
+
+/* Definitions for peripheral PSU_PCIE_LOW */
+#define XPAR_PSU_PCIE_LOW_DEVICE_ID 5
+#define XPAR_PSU_PCIE_LOW_BASEADDR 0xE0000000
+#define XPAR_PSU_PCIE_LOW_HIGHADDR 0xEFFFFFFF
+
+
+/******************************************************************/
+
+#define XPAR_PSU_PCIE_PCIE_MODE 0x1
+
+/* Canonical definitions for peripheral PSU_PCIE */
+#define XPAR_XPCIEPSU_0_DEVICE_ID XPAR_PSU_PCIE_DEVICE_ID
+#define XPAR_XPCIEPSU_0_BASEADDR 0xFD0E0000
+#define XPAR_XPCIEPSU_0_HIGHADDR 0xFD0EFFFF
+#define XPAR_XPCIEPSU_0_PCIE_MODE Root Port
+
+/* Canonical definitions for peripheral PSU_PCIE_ATTRIB_0 */
+#define XPAR_XPCIEPSU_1_DEVICE_ID XPAR_PSU_PCIE_ATTRIB_0_DEVICE_ID
+#define XPAR_XPCIEPSU_1_BASEADDR 0xFD480000
+#define XPAR_XPCIEPSU_1_HIGHADDR 0xFD48FFFF
+#define XPAR_XPCIEPSU_1_PCIE_MODE 0
+
+/* Canonical definitions for peripheral PSU_PCIE_DMA */
+#define XPAR_XPCIEPSU_2_DEVICE_ID XPAR_PSU_PCIE_DMA_DEVICE_ID
+#define XPAR_XPCIEPSU_2_BASEADDR 0xFD0F0000
+#define XPAR_XPCIEPSU_2_HIGHADDR 0xFD0FFFFF
+#define XPAR_XPCIEPSU_2_PCIE_MODE 0
+
+/* Canonical definitions for peripheral PSU_PCIE_HIGH1 */
+#define XPAR_XPCIEPSU_3_DEVICE_ID XPAR_PSU_PCIE_HIGH1_DEVICE_ID
+#define XPAR_XPCIEPSU_3_BASEADDR 0x600000000
+#define XPAR_XPCIEPSU_3_HIGHADDR 0x7FFFFFFFF
+#define XPAR_XPCIEPSU_3_PCIE_MODE 0
+
+/* Canonical definitions for peripheral PSU_PCIE_HIGH2 */
+#define XPAR_XPCIEPSU_4_DEVICE_ID XPAR_PSU_PCIE_HIGH2_DEVICE_ID
+#define XPAR_XPCIEPSU_4_BASEADDR 0x8000000000
+#define XPAR_XPCIEPSU_4_HIGHADDR 0xBFFFFFFFFF
+#define XPAR_XPCIEPSU_4_PCIE_MODE 0
+
+/* Canonical definitions for peripheral PSU_PCIE_LOW */
+#define XPAR_XPCIEPSU_5_DEVICE_ID XPAR_PSU_PCIE_LOW_DEVICE_ID
+#define XPAR_XPCIEPSU_5_BASEADDR 0xE0000000
+#define XPAR_XPCIEPSU_5_HIGHADDR 0xEFFFFFFF
+#define XPAR_XPCIEPSU_5_PCIE_MODE 0
+
+
+/******************************************************************/
+
+/* Definitions for driver QSPIPSU */
+#define XPAR_XQSPIPSU_NUM_INSTANCES 1
+
+/* Definitions for peripheral PSU_QSPI_0 */
+#define XPAR_PSU_QSPI_0_DEVICE_ID 0
+#define XPAR_PSU_QSPI_0_BASEADDR 0xFF0F0000
+#define XPAR_PSU_QSPI_0_HIGHADDR 0xFF0FFFFF
+#define XPAR_PSU_QSPI_0_QSPI_CLK_FREQ_HZ 124987511
+#define XPAR_PSU_QSPI_0_QSPI_MODE 2
+#define XPAR_PSU_QSPI_0_QSPI_BUS_WIDTH 2
+
+
+/******************************************************************/
+
+#define XPAR_PSU_QSPI_0_IS_CACHE_COHERENT 0
+#define XPAR_PSU_QSPI_0_REF_CLK 0xff
+/* Canonical definitions for peripheral PSU_QSPI_0 */
+#define XPAR_XQSPIPSU_0_DEVICE_ID XPAR_PSU_QSPI_0_DEVICE_ID
+#define XPAR_XQSPIPSU_0_BASEADDR 0xFF0F0000
+#define XPAR_XQSPIPSU_0_HIGHADDR 0xFF0FFFFF
+#define XPAR_XQSPIPSU_0_QSPI_CLK_FREQ_HZ 124987511
+#define XPAR_XQSPIPSU_0_QSPI_MODE 2
+#define XPAR_XQSPIPSU_0_QSPI_BUS_WIDTH 2
+#define XPAR_XQSPIPSU_0_IS_CACHE_COHERENT 0
+
+
+/******************************************************************/
+
+/* Definitions for driver RESETPS and CLOCKPS */
+#define XPAR_XCRPSU_NUM_INSTANCES 1U
+
+/* Definitions for peripheral PSU_CR_0 */
+#define XPAR_PSU_CR_DEVICE_ID 0
+
+/******************************************************************/
+
+/* Definitions for peripheral PSU_CRF_APB */
+#define XPAR_PSU_CRF_APB_S_AXI_BASEADDR 0xFD1A0000
+#define XPAR_PSU_CRF_APB_S_AXI_HIGHADDR 0xFD2DFFFF
+
+
+/******************************************************************/
+
+/* Canonical definitions for peripheral PSU_CR_0 */
+#define XPAR_XCRPSU_0_DEVICE_ID 0
+
+/******************************************************************/
+
+
+/* Definitions for peripheral PSU_PMU_IOMODULE */
+#define XPAR_PSU_PMU_IOMODULE_S_AXI_BASEADDR 0xFFD40000
+#define XPAR_PSU_PMU_IOMODULE_S_AXI_HIGHADDR 0xFFD5FFFF
+
+
+/* Definitions for peripheral PSU_LPD_SLCR */
+#define XPAR_PSU_LPD_SLCR_S_AXI_BASEADDR 0xFF410000
+#define XPAR_PSU_LPD_SLCR_S_AXI_HIGHADDR 0xFF4AFFFF
+
+
+/******************************************************************/
+
+/* Definitions for driver RTCPSU */
+#define XPAR_XRTCPSU_NUM_INSTANCES 1
+
+/* Definitions for peripheral PSU_RTC */
+#define XPAR_PSU_RTC_DEVICE_ID 0
+#define XPAR_PSU_RTC_BASEADDR 0xFFA60000
+#define XPAR_PSU_RTC_HIGHADDR 0xFFA6FFFF
+
+
+/******************************************************************/
+
+/* Canonical definitions for peripheral PSU_RTC */
+#define XPAR_XRTCPSU_0_DEVICE_ID XPAR_PSU_RTC_DEVICE_ID
+#define XPAR_XRTCPSU_0_BASEADDR 0xFFA60000
+#define XPAR_XRTCPSU_0_HIGHADDR 0xFFA6FFFF
+
+
+/******************************************************************/
+
+/* Definitions for driver SDPS */
+#define XPAR_XSDPS_NUM_INSTANCES 1
+
+/* Definitions for peripheral PSU_SD_1 */
+#define XPAR_PSU_SD_1_DEVICE_ID 0
+#define XPAR_PSU_SD_1_BASEADDR 0xFF170000
+#define XPAR_PSU_SD_1_HIGHADDR 0xFF17FFFF
+#define XPAR_PSU_SD_1_SDIO_CLK_FREQ_HZ 187481262
+#define XPAR_PSU_SD_1_HAS_CD 1
+#define XPAR_PSU_SD_1_HAS_WP 1
+#define XPAR_PSU_SD_1_BUS_WIDTH 8
+#define XPAR_PSU_SD_1_MIO_BANK 1
+#define XPAR_PSU_SD_1_HAS_EMIO 0
+
+
+/******************************************************************/
+
+#define XPAR_PSU_SD_1_IS_CACHE_COHERENT 0
+#define XPAR_PSU_SD_1_REF_CLK 0xff
+/* Canonical definitions for peripheral PSU_SD_1 */
+#define XPAR_XSDPS_0_DEVICE_ID XPAR_PSU_SD_1_DEVICE_ID
+#define XPAR_XSDPS_0_BASEADDR 0xFF170000
+#define XPAR_XSDPS_0_HIGHADDR 0xFF17FFFF
+#define XPAR_XSDPS_0_SDIO_CLK_FREQ_HZ 187481262
+#define XPAR_XSDPS_0_HAS_CD 1
+#define XPAR_XSDPS_0_HAS_WP 1
+#define XPAR_XSDPS_0_BUS_WIDTH 8
+#define XPAR_XSDPS_0_MIO_BANK 1
+#define XPAR_XSDPS_0_HAS_EMIO 0
+#define XPAR_XSDPS_0_IS_CACHE_COHERENT 0
+
+
+/******************************************************************/
+
+/* Definitions for driver SYSMONPSU */
+#define XPAR_XSYSMONPSU_NUM_INSTANCES 1
+
+/* Definitions for peripheral PSU_AMS */
+#define XPAR_PSU_AMS_DEVICE_ID 0
+#define XPAR_PSU_AMS_BASEADDR 0xFFA50000
+#define XPAR_PSU_AMS_HIGHADDR 0xFFA5FFFF
+
+
+/******************************************************************/
+
+#define XPAR_PSU_AMS_REF_FREQMHZ 49.995003
+/* Canonical definitions for peripheral PSU_AMS */
+#define XPAR_XSYSMONPSU_0_DEVICE_ID XPAR_PSU_AMS_DEVICE_ID
+#define XPAR_XSYSMONPSU_0_BASEADDR 0xFFA50000
+#define XPAR_XSYSMONPSU_0_HIGHADDR 0xFFA5FFFF
+
+
+/******************************************************************/
+
+#define XPAR_XSYSMONPSU_0_REF_FREQMHZ 49.995003
+/* Definitions for driver TTCPS */
+#define XPAR_XTTCPS_NUM_INSTANCES 12U
+
+/* Definitions for peripheral PSU_TTC_0 */
+#define XPAR_PSU_TTC_0_DEVICE_ID 0U
+#define XPAR_PSU_TTC_0_BASEADDR 0XFF110000U
+#define XPAR_PSU_TTC_0_TTC_CLK_FREQ_HZ 100000000U
+#define XPAR_PSU_TTC_0_TTC_CLK_CLKSRC 0U
+#define XPAR_PSU_TTC_1_DEVICE_ID 1U
+#define XPAR_PSU_TTC_1_BASEADDR 0XFF110004U
+#define XPAR_PSU_TTC_1_TTC_CLK_FREQ_HZ 100000000U
+#define XPAR_PSU_TTC_1_TTC_CLK_CLKSRC 0U
+#define XPAR_PSU_TTC_2_DEVICE_ID 2U
+#define XPAR_PSU_TTC_2_BASEADDR 0XFF110008U
+#define XPAR_PSU_TTC_2_TTC_CLK_FREQ_HZ 100000000U
+#define XPAR_PSU_TTC_2_TTC_CLK_CLKSRC 0U
+
+
+/* Definitions for peripheral PSU_TTC_1 */
+#define XPAR_PSU_TTC_3_DEVICE_ID 3U
+#define XPAR_PSU_TTC_3_BASEADDR 0XFF120000U
+#define XPAR_PSU_TTC_3_TTC_CLK_FREQ_HZ 100000000U
+#define XPAR_PSU_TTC_3_TTC_CLK_CLKSRC 0U
+#define XPAR_PSU_TTC_4_DEVICE_ID 4U
+#define XPAR_PSU_TTC_4_BASEADDR 0XFF120004U
+#define XPAR_PSU_TTC_4_TTC_CLK_FREQ_HZ 100000000U
+#define XPAR_PSU_TTC_4_TTC_CLK_CLKSRC 0U
+#define XPAR_PSU_TTC_5_DEVICE_ID 5U
+#define XPAR_PSU_TTC_5_BASEADDR 0XFF120008U
+#define XPAR_PSU_TTC_5_TTC_CLK_FREQ_HZ 100000000U
+#define XPAR_PSU_TTC_5_TTC_CLK_CLKSRC 0U
+
+
+/* Definitions for peripheral PSU_TTC_2 */
+#define XPAR_PSU_TTC_6_DEVICE_ID 6U
+#define XPAR_PSU_TTC_6_BASEADDR 0XFF130000U
+#define XPAR_PSU_TTC_6_TTC_CLK_FREQ_HZ 100000000U
+#define XPAR_PSU_TTC_6_TTC_CLK_CLKSRC 0U
+#define XPAR_PSU_TTC_7_DEVICE_ID 7U
+#define XPAR_PSU_TTC_7_BASEADDR 0XFF130004U
+#define XPAR_PSU_TTC_7_TTC_CLK_FREQ_HZ 100000000U
+#define XPAR_PSU_TTC_7_TTC_CLK_CLKSRC 0U
+#define XPAR_PSU_TTC_8_DEVICE_ID 8U
+#define XPAR_PSU_TTC_8_BASEADDR 0XFF130008U
+#define XPAR_PSU_TTC_8_TTC_CLK_FREQ_HZ 100000000U
+#define XPAR_PSU_TTC_8_TTC_CLK_CLKSRC 0U
+
+
+/* Definitions for peripheral PSU_TTC_3 */
+#define XPAR_PSU_TTC_9_DEVICE_ID 9U
+#define XPAR_PSU_TTC_9_BASEADDR 0XFF140000U
+#define XPAR_PSU_TTC_9_TTC_CLK_FREQ_HZ 100000000U
+#define XPAR_PSU_TTC_9_TTC_CLK_CLKSRC 0U
+#define XPAR_PSU_TTC_10_DEVICE_ID 10U
+#define XPAR_PSU_TTC_10_BASEADDR 0XFF140004U
+#define XPAR_PSU_TTC_10_TTC_CLK_FREQ_HZ 100000000U
+#define XPAR_PSU_TTC_10_TTC_CLK_CLKSRC 0U
+#define XPAR_PSU_TTC_11_DEVICE_ID 11U
+#define XPAR_PSU_TTC_11_BASEADDR 0XFF140008U
+#define XPAR_PSU_TTC_11_TTC_CLK_FREQ_HZ 100000000U
+#define XPAR_PSU_TTC_11_TTC_CLK_CLKSRC 0U
+
+
+/******************************************************************/
+
+/* Canonical definitions for peripheral PSU_TTC_0 */
+#define XPAR_XTTCPS_0_DEVICE_ID XPAR_PSU_TTC_0_DEVICE_ID
+#define XPAR_XTTCPS_0_BASEADDR 0xFF110000U
+#define XPAR_XTTCPS_0_TTC_CLK_FREQ_HZ 100000000U
+#define XPAR_XTTCPS_0_TTC_CLK_CLKSRC 0U
+
+#define XPAR_XTTCPS_1_DEVICE_ID XPAR_PSU_TTC_1_DEVICE_ID
+#define XPAR_XTTCPS_1_BASEADDR 0xFF110004U
+#define XPAR_XTTCPS_1_TTC_CLK_FREQ_HZ 100000000U
+#define XPAR_XTTCPS_1_TTC_CLK_CLKSRC 0U
+
+#define XPAR_XTTCPS_2_DEVICE_ID XPAR_PSU_TTC_2_DEVICE_ID
+#define XPAR_XTTCPS_2_BASEADDR 0xFF110008U
+#define XPAR_XTTCPS_2_TTC_CLK_FREQ_HZ 100000000U
+#define XPAR_XTTCPS_2_TTC_CLK_CLKSRC 0U
+
+/* Canonical definitions for peripheral PSU_TTC_1 */
+#define XPAR_XTTCPS_3_DEVICE_ID XPAR_PSU_TTC_3_DEVICE_ID
+#define XPAR_XTTCPS_3_BASEADDR 0xFF120000U
+#define XPAR_XTTCPS_3_TTC_CLK_FREQ_HZ 100000000U
+#define XPAR_XTTCPS_3_TTC_CLK_CLKSRC 0U
+
+#define XPAR_XTTCPS_4_DEVICE_ID XPAR_PSU_TTC_4_DEVICE_ID
+#define XPAR_XTTCPS_4_BASEADDR 0xFF120004U
+#define XPAR_XTTCPS_4_TTC_CLK_FREQ_HZ 100000000U
+#define XPAR_XTTCPS_4_TTC_CLK_CLKSRC 0U
+
+#define XPAR_XTTCPS_5_DEVICE_ID XPAR_PSU_TTC_5_DEVICE_ID
+#define XPAR_XTTCPS_5_BASEADDR 0xFF120008U
+#define XPAR_XTTCPS_5_TTC_CLK_FREQ_HZ 100000000U
+#define XPAR_XTTCPS_5_TTC_CLK_CLKSRC 0U
+
+/* Canonical definitions for peripheral PSU_TTC_2 */
+#define XPAR_XTTCPS_6_DEVICE_ID XPAR_PSU_TTC_6_DEVICE_ID
+#define XPAR_XTTCPS_6_BASEADDR 0xFF130000U
+#define XPAR_XTTCPS_6_TTC_CLK_FREQ_HZ 100000000U
+#define XPAR_XTTCPS_6_TTC_CLK_CLKSRC 0U
+
+#define XPAR_XTTCPS_7_DEVICE_ID XPAR_PSU_TTC_7_DEVICE_ID
+#define XPAR_XTTCPS_7_BASEADDR 0xFF130004U
+#define XPAR_XTTCPS_7_TTC_CLK_FREQ_HZ 100000000U
+#define XPAR_XTTCPS_7_TTC_CLK_CLKSRC 0U
+
+#define XPAR_XTTCPS_8_DEVICE_ID XPAR_PSU_TTC_8_DEVICE_ID
+#define XPAR_XTTCPS_8_BASEADDR 0xFF130008U
+#define XPAR_XTTCPS_8_TTC_CLK_FREQ_HZ 100000000U
+#define XPAR_XTTCPS_8_TTC_CLK_CLKSRC 0U
+
+/* Canonical definitions for peripheral PSU_TTC_3 */
+#define XPAR_XTTCPS_9_DEVICE_ID XPAR_PSU_TTC_9_DEVICE_ID
+#define XPAR_XTTCPS_9_BASEADDR 0xFF140000U
+#define XPAR_XTTCPS_9_TTC_CLK_FREQ_HZ 100000000U
+#define XPAR_XTTCPS_9_TTC_CLK_CLKSRC 0U
+
+#define XPAR_XTTCPS_10_DEVICE_ID XPAR_PSU_TTC_10_DEVICE_ID
+#define XPAR_XTTCPS_10_BASEADDR 0xFF140004U
+#define XPAR_XTTCPS_10_TTC_CLK_FREQ_HZ 100000000U
+#define XPAR_XTTCPS_10_TTC_CLK_CLKSRC 0U
+
+#define XPAR_XTTCPS_11_DEVICE_ID XPAR_PSU_TTC_11_DEVICE_ID
+#define XPAR_XTTCPS_11_BASEADDR 0xFF140008U
+#define XPAR_XTTCPS_11_TTC_CLK_FREQ_HZ 100000000U
+#define XPAR_XTTCPS_11_TTC_CLK_CLKSRC 0U
+
+
+/******************************************************************/
+
+/* Definitions for driver UARTPS */
+#define XPAR_XUARTPS_NUM_INSTANCES 2
+
+/* Definitions for peripheral PSU_UART_0 */
+#define XPAR_PSU_UART_0_DEVICE_ID 0
+#define XPAR_PSU_UART_0_BASEADDR 0xFF000000
+#define XPAR_PSU_UART_0_HIGHADDR 0xFF00FFFF
+#define XPAR_PSU_UART_0_UART_CLK_FREQ_HZ 99990005
+#define XPAR_PSU_UART_0_HAS_MODEM 0
+
+
+/* Definitions for peripheral PSU_UART_1 */
+#define XPAR_PSU_UART_1_DEVICE_ID 1
+#define XPAR_PSU_UART_1_BASEADDR 0xFF010000
+#define XPAR_PSU_UART_1_HIGHADDR 0xFF01FFFF
+#define XPAR_PSU_UART_1_UART_CLK_FREQ_HZ 99990005
+#define XPAR_PSU_UART_1_HAS_MODEM 0
+
+
+/******************************************************************/
+
+/* Canonical definitions for peripheral PSU_UART_0 */
+#define XPAR_XUARTPS_0_DEVICE_ID XPAR_PSU_UART_0_DEVICE_ID
+#define XPAR_XUARTPS_0_BASEADDR 0xFF000000
+#define XPAR_XUARTPS_0_HIGHADDR 0xFF00FFFF
+#define XPAR_XUARTPS_0_UART_CLK_FREQ_HZ 99990005
+#define XPAR_XUARTPS_0_HAS_MODEM 0
+
+/* Canonical definitions for peripheral PSU_UART_1 */
+#define XPAR_XUARTPS_1_DEVICE_ID XPAR_PSU_UART_1_DEVICE_ID
+#define XPAR_XUARTPS_1_BASEADDR 0xFF010000
+#define XPAR_XUARTPS_1_HIGHADDR 0xFF01FFFF
+#define XPAR_XUARTPS_1_UART_CLK_FREQ_HZ 99990005
+#define XPAR_XUARTPS_1_HAS_MODEM 0
+
+
+/******************************************************************/
+
+/* Definition for input Clock */
+#define XPAR_PSU_UART_0_REF_CLK UART0_REF
+/* Definition for input Clock */
+#define XPAR_PSU_UART_1_REF_CLK UART1_REF
+/* Definitions for driver USBPSU */
+#define XPAR_XUSBPSU_NUM_INSTANCES 1
+
+/* Definitions for peripheral PSU_USB_XHCI_0 */
+#define XPAR_PSU_USB_XHCI_0_DEVICE_ID 0
+#define XPAR_PSU_USB_XHCI_0_BASEADDR 0xFE200000
+#define XPAR_PSU_USB_XHCI_0_HIGHADDR 0xFE20FFFF
+
+
+/******************************************************************/
+
+#define XPAR_PSU_USB_XHCI_0_IS_CACHE_COHERENT 0
+#define XPAR_PSU_USB_XHCI_0_REF_CLK 0xff
+#define XPAR_PSU_USB_XHCI_0_SUPER_SPEED 1
+/* Canonical definitions for peripheral PSU_USB_XHCI_0 */
+#define XPAR_XUSBPSU_0_DEVICE_ID XPAR_PSU_USB_XHCI_0_DEVICE_ID
+#define XPAR_XUSBPSU_0_BASEADDR 0xFE200000
+#define XPAR_XUSBPSU_0_HIGHADDR 0xFE20FFFF
+
+
+/******************************************************************/
+
+/* Definitions for driver WDTPS */
+#define XPAR_XWDTPS_NUM_INSTANCES 3
+
+/* Definitions for peripheral PSU_CSU_WDT */
+#define XPAR_PSU_CSU_WDT_DEVICE_ID 0
+#define XPAR_PSU_CSU_WDT_BASEADDR 0xFFCB0000
+#define XPAR_PSU_CSU_WDT_HIGHADDR 0xFFCBFFFF
+#define XPAR_PSU_CSU_WDT_WDT_CLK_FREQ_HZ 100000000
+
+
+/* Definitions for peripheral PSU_WDT_0 */
+#define XPAR_PSU_WDT_0_DEVICE_ID 1
+#define XPAR_PSU_WDT_0_BASEADDR 0xFF150000
+#define XPAR_PSU_WDT_0_HIGHADDR 0xFF15FFFF
+#define XPAR_PSU_WDT_0_WDT_CLK_FREQ_HZ 99990005
+
+
+/* Definitions for peripheral PSU_WDT_1 */
+#define XPAR_PSU_WDT_1_DEVICE_ID 2
+#define XPAR_PSU_WDT_1_BASEADDR 0xFD4D0000
+#define XPAR_PSU_WDT_1_HIGHADDR 0xFD4DFFFF
+#define XPAR_PSU_WDT_1_WDT_CLK_FREQ_HZ 99990005
+
+
+/******************************************************************/
+
+/* Canonical definitions for peripheral PSU_CSU_WDT */
+#define XPAR_XWDTPS_0_DEVICE_ID XPAR_PSU_CSU_WDT_DEVICE_ID
+#define XPAR_XWDTPS_0_BASEADDR 0xFFCB0000
+#define XPAR_XWDTPS_0_HIGHADDR 0xFFCBFFFF
+#define XPAR_XWDTPS_0_WDT_CLK_FREQ_HZ 100000000
+
+/* Canonical definitions for peripheral PSU_WDT_0 */
+#define XPAR_XWDTPS_1_DEVICE_ID XPAR_PSU_WDT_0_DEVICE_ID
+#define XPAR_XWDTPS_1_BASEADDR 0xFF150000
+#define XPAR_XWDTPS_1_HIGHADDR 0xFF15FFFF
+#define XPAR_XWDTPS_1_WDT_CLK_FREQ_HZ 99990005
+
+/* Canonical definitions for peripheral PSU_WDT_1 */
+#define XPAR_XWDTPS_2_DEVICE_ID XPAR_PSU_WDT_1_DEVICE_ID
+#define XPAR_XWDTPS_2_BASEADDR 0xFD4D0000
+#define XPAR_XWDTPS_2_HIGHADDR 0xFD4DFFFF
+#define XPAR_XWDTPS_2_WDT_CLK_FREQ_HZ 99990005
+
+
+/******************************************************************/
+
+/* Definitions for driver ZDMA */
+#define XPAR_XZDMA_NUM_INSTANCES 16
+
+/* Definitions for peripheral PSU_ADMA_0 */
+#define XPAR_PSU_ADMA_0_DEVICE_ID 0
+#define XPAR_PSU_ADMA_0_BASEADDR 0xFFA80000
+#define XPAR_PSU_ADMA_0_DMA_MODE 1
+#define XPAR_PSU_ADMA_0_HIGHADDR 0xFFA8FFFF
+#define XPAR_PSU_ADMA_0_ZDMA_CLK_FREQ_HZ 0
+
+
+/* Definitions for peripheral PSU_ADMA_1 */
+#define XPAR_PSU_ADMA_1_DEVICE_ID 1
+#define XPAR_PSU_ADMA_1_BASEADDR 0xFFA90000
+#define XPAR_PSU_ADMA_1_DMA_MODE 1
+#define XPAR_PSU_ADMA_1_HIGHADDR 0xFFA9FFFF
+#define XPAR_PSU_ADMA_1_ZDMA_CLK_FREQ_HZ 0
+
+
+/* Definitions for peripheral PSU_ADMA_2 */
+#define XPAR_PSU_ADMA_2_DEVICE_ID 2
+#define XPAR_PSU_ADMA_2_BASEADDR 0xFFAA0000
+#define XPAR_PSU_ADMA_2_DMA_MODE 1
+#define XPAR_PSU_ADMA_2_HIGHADDR 0xFFAAFFFF
+#define XPAR_PSU_ADMA_2_ZDMA_CLK_FREQ_HZ 0
+
+
+/* Definitions for peripheral PSU_ADMA_3 */
+#define XPAR_PSU_ADMA_3_DEVICE_ID 3
+#define XPAR_PSU_ADMA_3_BASEADDR 0xFFAB0000
+#define XPAR_PSU_ADMA_3_DMA_MODE 1
+#define XPAR_PSU_ADMA_3_HIGHADDR 0xFFABFFFF
+#define XPAR_PSU_ADMA_3_ZDMA_CLK_FREQ_HZ 0
+
+
+/* Definitions for peripheral PSU_ADMA_4 */
+#define XPAR_PSU_ADMA_4_DEVICE_ID 4
+#define XPAR_PSU_ADMA_4_BASEADDR 0xFFAC0000
+#define XPAR_PSU_ADMA_4_DMA_MODE 1
+#define XPAR_PSU_ADMA_4_HIGHADDR 0xFFACFFFF
+#define XPAR_PSU_ADMA_4_ZDMA_CLK_FREQ_HZ 0
+
+
+/* Definitions for peripheral PSU_ADMA_5 */
+#define XPAR_PSU_ADMA_5_DEVICE_ID 5
+#define XPAR_PSU_ADMA_5_BASEADDR 0xFFAD0000
+#define XPAR_PSU_ADMA_5_DMA_MODE 1
+#define XPAR_PSU_ADMA_5_HIGHADDR 0xFFADFFFF
+#define XPAR_PSU_ADMA_5_ZDMA_CLK_FREQ_HZ 0
+
+
+/* Definitions for peripheral PSU_ADMA_6 */
+#define XPAR_PSU_ADMA_6_DEVICE_ID 6
+#define XPAR_PSU_ADMA_6_BASEADDR 0xFFAE0000
+#define XPAR_PSU_ADMA_6_DMA_MODE 1
+#define XPAR_PSU_ADMA_6_HIGHADDR 0xFFAEFFFF
+#define XPAR_PSU_ADMA_6_ZDMA_CLK_FREQ_HZ 0
+
+
+/* Definitions for peripheral PSU_ADMA_7 */
+#define XPAR_PSU_ADMA_7_DEVICE_ID 7
+#define XPAR_PSU_ADMA_7_BASEADDR 0xFFAF0000
+#define XPAR_PSU_ADMA_7_DMA_MODE 1
+#define XPAR_PSU_ADMA_7_HIGHADDR 0xFFAFFFFF
+#define XPAR_PSU_ADMA_7_ZDMA_CLK_FREQ_HZ 0
+
+
+/* Definitions for peripheral PSU_GDMA_0 */
+#define XPAR_PSU_GDMA_0_DEVICE_ID 8
+#define XPAR_PSU_GDMA_0_BASEADDR 0xFD500000
+#define XPAR_PSU_GDMA_0_DMA_MODE 0
+#define XPAR_PSU_GDMA_0_HIGHADDR 0xFD50FFFF
+#define XPAR_PSU_GDMA_0_ZDMA_CLK_FREQ_HZ 0
+
+
+/* Definitions for peripheral PSU_GDMA_1 */
+#define XPAR_PSU_GDMA_1_DEVICE_ID 9
+#define XPAR_PSU_GDMA_1_BASEADDR 0xFD510000
+#define XPAR_PSU_GDMA_1_DMA_MODE 0
+#define XPAR_PSU_GDMA_1_HIGHADDR 0xFD51FFFF
+#define XPAR_PSU_GDMA_1_ZDMA_CLK_FREQ_HZ 0
+
+
+/* Definitions for peripheral PSU_GDMA_2 */
+#define XPAR_PSU_GDMA_2_DEVICE_ID 10
+#define XPAR_PSU_GDMA_2_BASEADDR 0xFD520000
+#define XPAR_PSU_GDMA_2_DMA_MODE 0
+#define XPAR_PSU_GDMA_2_HIGHADDR 0xFD52FFFF
+#define XPAR_PSU_GDMA_2_ZDMA_CLK_FREQ_HZ 0
+
+
+/* Definitions for peripheral PSU_GDMA_3 */
+#define XPAR_PSU_GDMA_3_DEVICE_ID 11
+#define XPAR_PSU_GDMA_3_BASEADDR 0xFD530000
+#define XPAR_PSU_GDMA_3_DMA_MODE 0
+#define XPAR_PSU_GDMA_3_HIGHADDR 0xFD53FFFF
+#define XPAR_PSU_GDMA_3_ZDMA_CLK_FREQ_HZ 0
+
+
+/* Definitions for peripheral PSU_GDMA_4 */
+#define XPAR_PSU_GDMA_4_DEVICE_ID 12
+#define XPAR_PSU_GDMA_4_BASEADDR 0xFD540000
+#define XPAR_PSU_GDMA_4_DMA_MODE 0
+#define XPAR_PSU_GDMA_4_HIGHADDR 0xFD54FFFF
+#define XPAR_PSU_GDMA_4_ZDMA_CLK_FREQ_HZ 0
+
+
+/* Definitions for peripheral PSU_GDMA_5 */
+#define XPAR_PSU_GDMA_5_DEVICE_ID 13
+#define XPAR_PSU_GDMA_5_BASEADDR 0xFD550000
+#define XPAR_PSU_GDMA_5_DMA_MODE 0
+#define XPAR_PSU_GDMA_5_HIGHADDR 0xFD55FFFF
+#define XPAR_PSU_GDMA_5_ZDMA_CLK_FREQ_HZ 0
+
+
+/* Definitions for peripheral PSU_GDMA_6 */
+#define XPAR_PSU_GDMA_6_DEVICE_ID 14
+#define XPAR_PSU_GDMA_6_BASEADDR 0xFD560000
+#define XPAR_PSU_GDMA_6_DMA_MODE 0
+#define XPAR_PSU_GDMA_6_HIGHADDR 0xFD56FFFF
+#define XPAR_PSU_GDMA_6_ZDMA_CLK_FREQ_HZ 0
+
+
+/* Definitions for peripheral PSU_GDMA_7 */
+#define XPAR_PSU_GDMA_7_DEVICE_ID 15
+#define XPAR_PSU_GDMA_7_BASEADDR 0xFD570000
+#define XPAR_PSU_GDMA_7_DMA_MODE 0
+#define XPAR_PSU_GDMA_7_HIGHADDR 0xFD57FFFF
+#define XPAR_PSU_GDMA_7_ZDMA_CLK_FREQ_HZ 0
+
+
+/******************************************************************/
+
+#define XPAR_PSU_ADMA_0_IS_CACHE_COHERENT 0
+#define XPAR_PSU_ADMA_1_IS_CACHE_COHERENT 0
+#define XPAR_PSU_ADMA_2_IS_CACHE_COHERENT 0
+#define XPAR_PSU_ADMA_3_IS_CACHE_COHERENT 0
+#define XPAR_PSU_ADMA_4_IS_CACHE_COHERENT 0
+#define XPAR_PSU_ADMA_5_IS_CACHE_COHERENT 0
+#define XPAR_PSU_ADMA_6_IS_CACHE_COHERENT 0
+#define XPAR_PSU_ADMA_7_IS_CACHE_COHERENT 0
+#define XPAR_PSU_GDMA_0_IS_CACHE_COHERENT 0
+#define XPAR_PSU_GDMA_1_IS_CACHE_COHERENT 0
+#define XPAR_PSU_GDMA_2_IS_CACHE_COHERENT 0
+#define XPAR_PSU_GDMA_3_IS_CACHE_COHERENT 0
+#define XPAR_PSU_GDMA_4_IS_CACHE_COHERENT 0
+#define XPAR_PSU_GDMA_5_IS_CACHE_COHERENT 0
+#define XPAR_PSU_GDMA_6_IS_CACHE_COHERENT 0
+#define XPAR_PSU_GDMA_7_IS_CACHE_COHERENT 0
+/* Canonical definitions for peripheral PSU_ADMA_0 */
+#define XPAR_XZDMA_0_DEVICE_ID XPAR_PSU_ADMA_0_DEVICE_ID
+#define XPAR_XZDMA_0_BASEADDR 0xFFA80000
+#define XPAR_XZDMA_0_DMA_MODE 1
+#define XPAR_XZDMA_0_HIGHADDR 0xFFA8FFFF
+#define XPAR_XZDMA_0_ZDMA_CLK_FREQ_HZ 0
+
+/* Canonical definitions for peripheral PSU_ADMA_1 */
+#define XPAR_XZDMA_1_DEVICE_ID XPAR_PSU_ADMA_1_DEVICE_ID
+#define XPAR_XZDMA_1_BASEADDR 0xFFA90000
+#define XPAR_XZDMA_1_DMA_MODE 1
+#define XPAR_XZDMA_1_HIGHADDR 0xFFA9FFFF
+#define XPAR_XZDMA_1_ZDMA_CLK_FREQ_HZ 0
+
+/* Canonical definitions for peripheral PSU_ADMA_2 */
+#define XPAR_XZDMA_2_DEVICE_ID XPAR_PSU_ADMA_2_DEVICE_ID
+#define XPAR_XZDMA_2_BASEADDR 0xFFAA0000
+#define XPAR_XZDMA_2_DMA_MODE 1
+#define XPAR_XZDMA_2_HIGHADDR 0xFFAAFFFF
+#define XPAR_XZDMA_2_ZDMA_CLK_FREQ_HZ 0
+
+/* Canonical definitions for peripheral PSU_ADMA_3 */
+#define XPAR_XZDMA_3_DEVICE_ID XPAR_PSU_ADMA_3_DEVICE_ID
+#define XPAR_XZDMA_3_BASEADDR 0xFFAB0000
+#define XPAR_XZDMA_3_DMA_MODE 1
+#define XPAR_XZDMA_3_HIGHADDR 0xFFABFFFF
+#define XPAR_XZDMA_3_ZDMA_CLK_FREQ_HZ 0
+
+/* Canonical definitions for peripheral PSU_ADMA_4 */
+#define XPAR_XZDMA_4_DEVICE_ID XPAR_PSU_ADMA_4_DEVICE_ID
+#define XPAR_XZDMA_4_BASEADDR 0xFFAC0000
+#define XPAR_XZDMA_4_DMA_MODE 1
+#define XPAR_XZDMA_4_HIGHADDR 0xFFACFFFF
+#define XPAR_XZDMA_4_ZDMA_CLK_FREQ_HZ 0
+
+/* Canonical definitions for peripheral PSU_ADMA_5 */
+#define XPAR_XZDMA_5_DEVICE_ID XPAR_PSU_ADMA_5_DEVICE_ID
+#define XPAR_XZDMA_5_BASEADDR 0xFFAD0000
+#define XPAR_XZDMA_5_DMA_MODE 1
+#define XPAR_XZDMA_5_HIGHADDR 0xFFADFFFF
+#define XPAR_XZDMA_5_ZDMA_CLK_FREQ_HZ 0
+
+/* Canonical definitions for peripheral PSU_ADMA_6 */
+#define XPAR_XZDMA_6_DEVICE_ID XPAR_PSU_ADMA_6_DEVICE_ID
+#define XPAR_XZDMA_6_BASEADDR 0xFFAE0000
+#define XPAR_XZDMA_6_DMA_MODE 1
+#define XPAR_XZDMA_6_HIGHADDR 0xFFAEFFFF
+#define XPAR_XZDMA_6_ZDMA_CLK_FREQ_HZ 0
+
+/* Canonical definitions for peripheral PSU_ADMA_7 */
+#define XPAR_XZDMA_7_DEVICE_ID XPAR_PSU_ADMA_7_DEVICE_ID
+#define XPAR_XZDMA_7_BASEADDR 0xFFAF0000
+#define XPAR_XZDMA_7_DMA_MODE 1
+#define XPAR_XZDMA_7_HIGHADDR 0xFFAFFFFF
+#define XPAR_XZDMA_7_ZDMA_CLK_FREQ_HZ 0
+
+/* Canonical definitions for peripheral PSU_GDMA_0 */
+#define XPAR_XZDMA_8_DEVICE_ID XPAR_PSU_GDMA_0_DEVICE_ID
+#define XPAR_XZDMA_8_BASEADDR 0xFD500000
+#define XPAR_XZDMA_8_DMA_MODE 0
+#define XPAR_XZDMA_8_HIGHADDR 0xFD50FFFF
+#define XPAR_XZDMA_8_ZDMA_CLK_FREQ_HZ 0
+
+/* Canonical definitions for peripheral PSU_GDMA_1 */
+#define XPAR_XZDMA_9_DEVICE_ID XPAR_PSU_GDMA_1_DEVICE_ID
+#define XPAR_XZDMA_9_BASEADDR 0xFD510000
+#define XPAR_XZDMA_9_DMA_MODE 0
+#define XPAR_XZDMA_9_HIGHADDR 0xFD51FFFF
+#define XPAR_XZDMA_9_ZDMA_CLK_FREQ_HZ 0
+
+/* Canonical definitions for peripheral PSU_GDMA_2 */
+#define XPAR_XZDMA_10_DEVICE_ID XPAR_PSU_GDMA_2_DEVICE_ID
+#define XPAR_XZDMA_10_BASEADDR 0xFD520000
+#define XPAR_XZDMA_10_DMA_MODE 0
+#define XPAR_XZDMA_10_HIGHADDR 0xFD52FFFF
+#define XPAR_XZDMA_10_ZDMA_CLK_FREQ_HZ 0
+
+/* Canonical definitions for peripheral PSU_GDMA_3 */
+#define XPAR_XZDMA_11_DEVICE_ID XPAR_PSU_GDMA_3_DEVICE_ID
+#define XPAR_XZDMA_11_BASEADDR 0xFD530000
+#define XPAR_XZDMA_11_DMA_MODE 0
+#define XPAR_XZDMA_11_HIGHADDR 0xFD53FFFF
+#define XPAR_XZDMA_11_ZDMA_CLK_FREQ_HZ 0
+
+/* Canonical definitions for peripheral PSU_GDMA_4 */
+#define XPAR_XZDMA_12_DEVICE_ID XPAR_PSU_GDMA_4_DEVICE_ID
+#define XPAR_XZDMA_12_BASEADDR 0xFD540000
+#define XPAR_XZDMA_12_DMA_MODE 0
+#define XPAR_XZDMA_12_HIGHADDR 0xFD54FFFF
+#define XPAR_XZDMA_12_ZDMA_CLK_FREQ_HZ 0
+
+/* Canonical definitions for peripheral PSU_GDMA_5 */
+#define XPAR_XZDMA_13_DEVICE_ID XPAR_PSU_GDMA_5_DEVICE_ID
+#define XPAR_XZDMA_13_BASEADDR 0xFD550000
+#define XPAR_XZDMA_13_DMA_MODE 0
+#define XPAR_XZDMA_13_HIGHADDR 0xFD55FFFF
+#define XPAR_XZDMA_13_ZDMA_CLK_FREQ_HZ 0
+
+/* Canonical definitions for peripheral PSU_GDMA_6 */
+#define XPAR_XZDMA_14_DEVICE_ID XPAR_PSU_GDMA_6_DEVICE_ID
+#define XPAR_XZDMA_14_BASEADDR 0xFD560000
+#define XPAR_XZDMA_14_DMA_MODE 0
+#define XPAR_XZDMA_14_HIGHADDR 0xFD56FFFF
+#define XPAR_XZDMA_14_ZDMA_CLK_FREQ_HZ 0
+
+/* Canonical definitions for peripheral PSU_GDMA_7 */
+#define XPAR_XZDMA_15_DEVICE_ID XPAR_PSU_GDMA_7_DEVICE_ID
+#define XPAR_XZDMA_15_BASEADDR 0xFD570000
+#define XPAR_XZDMA_15_DMA_MODE 0
+#define XPAR_XZDMA_15_HIGHADDR 0xFD57FFFF
+#define XPAR_XZDMA_15_ZDMA_CLK_FREQ_HZ 0
+
+
+/******************************************************************/
+
+
+/* Xilinx processor macro for Secure Library (Xilskey) */
+
+#define XPAR_XSK_ARM_PLATFORM 1
+
+#define XSK_OVERRIDE_SYSMON_CFG
+
+
+#endif /* end of protection macro */
diff --git a/hello_world/sw/app/embeddedsw-master/xparameters_ps.h b/hello_world/sw/app/embeddedsw-master/xparameters_ps.h
new file mode 100644
index 0000000..b5db175
--- /dev/null
+++ b/hello_world/sw/app/embeddedsw-master/xparameters_ps.h
@@ -0,0 +1,312 @@
+/******************************************************************************
+* Copyright (c) 2010 - 2020 Xilinx, Inc. All rights reserved.
+* SPDX-License-Identifier: MIT
+******************************************************************************/
+
+/*****************************************************************************/
+/**
+* @file xparameters_ps.h
+*
+* This file contains the address definitions for the hard peripherals
+* attached to the ARM Cortex A9 core.
+*
+* <pre>
+* MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ----- ------- -------- ---------------------------------------------------
+* 1.00a ecm/sdm 02/01/10 Initial version
+* 3.04a sdm 02/02/12 Removed some of the defines as they are being generated through
+* driver tcl
+* 5.0 pkp 01/16/15 Added interrupt ID definition of ttc for TEST APP
+* 6.6 srm 10/18/17 Added ARMA9 macro to identify CortexA9
+*
+* </pre>
+*
+* @note
+*
+* None.
+*
+******************************************************************************/
+
+#ifndef _XPARAMETERS_PS_H_
+#define _XPARAMETERS_PS_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**************************** Include Files *******************************/
+
+
+/************************** Constant Definitions *****************************/
+
+/*
+ * This block contains constant declarations for the peripherals
+ * within the hardblock
+ */
+
+/* Canonical definitions for DDR MEMORY */
+#define XPAR_DDR_MEM_BASEADDR 0x00000000U
+#define XPAR_DDR_MEM_HIGHADDR 0x3FFFFFFFU
+
+/* Canonical definitions for Interrupts */
+#define XPAR_XUARTPS_0_INTR XPS_UART0_INT_ID
+#define XPAR_XUARTPS_1_INTR XPS_UART1_INT_ID
+#define XPAR_XUSBPS_0_INTR XPS_USB0_INT_ID
+#define XPAR_XUSBPS_1_INTR XPS_USB1_INT_ID
+#define XPAR_XIICPS_0_INTR XPS_I2C0_INT_ID
+#define XPAR_XIICPS_1_INTR XPS_I2C1_INT_ID
+#define XPAR_XSPIPS_0_INTR XPS_SPI0_INT_ID
+#define XPAR_XSPIPS_1_INTR XPS_SPI1_INT_ID
+#define XPAR_XCANPS_0_INTR XPS_CAN0_INT_ID
+#define XPAR_XCANPS_1_INTR XPS_CAN1_INT_ID
+#define XPAR_XGPIOPS_0_INTR XPS_GPIO_INT_ID
+#define XPAR_XEMACPS_0_INTR XPS_GEM0_INT_ID
+#define XPAR_XEMACPS_0_WAKE_INTR XPS_GEM0_WAKE_INT_ID
+#define XPAR_XEMACPS_1_INTR XPS_GEM1_INT_ID
+#define XPAR_XEMACPS_1_WAKE_INTR XPS_GEM1_WAKE_INT_ID
+#define XPAR_XSDIOPS_0_INTR XPS_SDIO0_INT_ID
+#define XPAR_XQSPIPS_0_INTR XPS_QSPI_INT_ID
+#define XPAR_XSDIOPS_1_INTR XPS_SDIO1_INT_ID
+#define XPAR_XWDTPS_0_INTR XPS_WDT_INT_ID
+#define XPAR_XDCFG_0_INTR XPS_DVC_INT_ID
+#define XPAR_SCUTIMER_INTR XPS_SCU_TMR_INT_ID
+#define XPAR_SCUWDT_INTR XPS_SCU_WDT_INT_ID
+#define XPAR_XTTCPS_0_INTR XPS_TTC0_0_INT_ID
+#define XPAR_XTTCPS_1_INTR XPS_TTC0_1_INT_ID
+#define XPAR_XTTCPS_2_INTR XPS_TTC0_2_INT_ID
+#define XPAR_XTTCPS_3_INTR XPS_TTC1_0_INT_ID
+#define XPAR_XTTCPS_4_INTR XPS_TTC1_1_INT_ID
+#define XPAR_XTTCPS_5_INTR XPS_TTC1_2_INT_ID
+#define XPAR_XDMAPS_0_FAULT_INTR XPS_DMA0_ABORT_INT_ID
+#define XPAR_XDMAPS_0_DONE_INTR_0 XPS_DMA0_INT_ID
+#define XPAR_XDMAPS_0_DONE_INTR_1 XPS_DMA1_INT_ID
+#define XPAR_XDMAPS_0_DONE_INTR_2 XPS_DMA2_INT_ID
+#define XPAR_XDMAPS_0_DONE_INTR_3 XPS_DMA3_INT_ID
+#define XPAR_XDMAPS_0_DONE_INTR_4 XPS_DMA4_INT_ID
+#define XPAR_XDMAPS_0_DONE_INTR_5 XPS_DMA5_INT_ID
+#define XPAR_XDMAPS_0_DONE_INTR_6 XPS_DMA6_INT_ID
+#define XPAR_XDMAPS_0_DONE_INTR_7 XPS_DMA7_INT_ID
+
+
+#define XPAR_XQSPIPS_0_LINEAR_BASEADDR XPS_QSPI_LINEAR_BASEADDR
+#define XPAR_XPARPORTPS_CTRL_BASEADDR XPS_PARPORT_CRTL_BASEADDR
+
+
+
+/* Canonical definitions for DMAC */
+
+
+/* Canonical definitions for WDT */
+
+/* Canonical definitions for SLCR */
+#define XPAR_XSLCR_NUM_INSTANCES 1U
+#define XPAR_XSLCR_0_DEVICE_ID 0U
+#define XPAR_XSLCR_0_BASEADDR XPS_SYS_CTRL_BASEADDR
+
+/* Canonical definitions for SCU GIC */
+#define XPAR_SCUGIC_NUM_INSTANCES 1U
+#define XPAR_SCUGIC_SINGLE_DEVICE_ID 0U
+#define XPAR_SCUGIC_CPU_BASEADDR (XPS_SCU_PERIPH_BASE + 0x00000100U)
+#define XPAR_SCUGIC_DIST_BASEADDR (XPS_SCU_PERIPH_BASE + 0x00001000U)
+#define XPAR_SCUGIC_ACK_BEFORE 0U
+
+/* Canonical definitions for Global Timer */
+#define XPAR_GLOBAL_TMR_NUM_INSTANCES 1U
+#define XPAR_GLOBAL_TMR_DEVICE_ID 0U
+#define XPAR_GLOBAL_TMR_BASEADDR (XPS_SCU_PERIPH_BASE + 0x00000200U)
+#define XPAR_GLOBAL_TMR_INTR XPS_GLOBAL_TMR_INT_ID
+
+
+/* Xilinx Parallel Flash Library (XilFlash) User Settings */
+#define XPAR_AXI_EMC
+
+
+#define XPAR_CPU_CORTEXA9_CORE_CLOCK_FREQ_HZ XPAR_CPU_CORTEXA9_0_CPU_CLK_FREQ_HZ
+
+
+/*
+ * This block contains constant declarations for the peripherals
+ * within the hardblock. These have been put for bacwards compatibility
+ */
+
+#define XPS_PERIPHERAL_BASEADDR 0xE0000000U
+#define XPS_UART0_BASEADDR 0xE0000000U
+#define XPS_UART1_BASEADDR 0xE0001000U
+#define XPS_USB0_BASEADDR 0xE0002000U
+#define XPS_USB1_BASEADDR 0xE0003000U
+#define XPS_I2C0_BASEADDR 0xE0004000U
+#define XPS_I2C1_BASEADDR 0xE0005000U
+#define XPS_SPI0_BASEADDR 0xE0006000U
+#define XPS_SPI1_BASEADDR 0xE0007000U
+#define XPS_CAN0_BASEADDR 0xE0008000U
+#define XPS_CAN1_BASEADDR 0xE0009000U
+#define XPS_GPIO_BASEADDR 0xE000A000U
+#define XPS_GEM0_BASEADDR 0xE000B000U
+#define XPS_GEM1_BASEADDR 0xE000C000U
+#define XPS_QSPI_BASEADDR 0xE000D000U
+#define XPS_PARPORT_CRTL_BASEADDR 0xE000E000U
+#define XPS_SDIO0_BASEADDR 0xE0100000U
+#define XPS_SDIO1_BASEADDR 0xE0101000U
+#define XPS_IOU_BUS_CFG_BASEADDR 0xE0200000U
+#define XPS_NAND_BASEADDR 0xE1000000U
+#define XPS_PARPORT0_BASEADDR 0xE2000000U
+#define XPS_PARPORT1_BASEADDR 0xE4000000U
+#define XPS_QSPI_LINEAR_BASEADDR 0xFC000000U
+#define XPS_SYS_CTRL_BASEADDR 0xF8000000U /* AKA SLCR */
+#define XPS_TTC0_BASEADDR 0xF8001000U
+#define XPS_TTC1_BASEADDR 0xF8002000U
+#define XPS_DMAC0_SEC_BASEADDR 0xF8003000U
+#define XPS_DMAC0_NON_SEC_BASEADDR 0xF8004000U
+#define XPS_WDT_BASEADDR 0xF8005000U
+#define XPS_DDR_CTRL_BASEADDR 0xF8006000U
+#define XPS_DEV_CFG_APB_BASEADDR 0xF8007000U
+#define XPS_AFI0_BASEADDR 0xF8008000U
+#define XPS_AFI1_BASEADDR 0xF8009000U
+#define XPS_AFI2_BASEADDR 0xF800A000U
+#define XPS_AFI3_BASEADDR 0xF800B000U
+#define XPS_OCM_BASEADDR 0xF800C000U
+#define XPS_EFUSE_BASEADDR 0xF800D000U
+#define XPS_CORESIGHT_BASEADDR 0xF8800000U
+#define XPS_TOP_BUS_CFG_BASEADDR 0xF8900000U
+#define XPS_SCU_PERIPH_BASE 0xF8F00000U
+#define XPS_L2CC_BASEADDR 0xF8F02000U
+#define XPS_SAM_RAM_BASEADDR 0xFFFC0000U
+#define XPS_FPGA_AXI_S0_BASEADDR 0x40000000U
+#define XPS_FPGA_AXI_S1_BASEADDR 0x80000000U
+#define XPS_IOU_S_SWITCH_BASEADDR 0xE0000000U
+#define XPS_PERIPH_APB_BASEADDR 0xF8000000U
+
+/* Shared Peripheral Interrupts (SPI) */
+#define XPS_CORE_PARITY0_INT_ID 32U
+#define XPS_CORE_PARITY1_INT_ID 33U
+#define XPS_L2CC_INT_ID 34U
+#define XPS_OCMINTR_INT_ID 35U
+#define XPS_ECC_INT_ID 36U
+#define XPS_PMU0_INT_ID 37U
+#define XPS_PMU1_INT_ID 38U
+#define XPS_SYSMON_INT_ID 39U
+#define XPS_DVC_INT_ID 40U
+#define XPS_WDT_INT_ID 41U
+#define XPS_TTC0_0_INT_ID 42U
+#define XPS_TTC0_1_INT_ID 43U
+#define XPS_TTC0_2_INT_ID 44U
+#define XPS_DMA0_ABORT_INT_ID 45U
+#define XPS_DMA0_INT_ID 46U
+#define XPS_DMA1_INT_ID 47U
+#define XPS_DMA2_INT_ID 48U
+#define XPS_DMA3_INT_ID 49U
+#define XPS_SMC_INT_ID 50U
+#define XPS_QSPI_INT_ID 51U
+#define XPS_GPIO_INT_ID 52U
+#define XPS_USB0_INT_ID 53U
+#define XPS_GEM0_INT_ID 54U
+#define XPS_GEM0_WAKE_INT_ID 55U
+#define XPS_SDIO0_INT_ID 56U
+#define XPS_I2C0_INT_ID 57U
+#define XPS_SPI0_INT_ID 58U
+#define XPS_UART0_INT_ID 59U
+#define XPS_CAN0_INT_ID 60U
+#define XPS_FPGA0_INT_ID 61U
+#define XPS_FPGA1_INT_ID 62U
+#define XPS_FPGA2_INT_ID 63U
+#define XPS_FPGA3_INT_ID 64U
+#define XPS_FPGA4_INT_ID 65U
+#define XPS_FPGA5_INT_ID 66U
+#define XPS_FPGA6_INT_ID 67U
+#define XPS_FPGA7_INT_ID 68U
+#define XPS_TTC1_0_INT_ID 69U
+#define XPS_TTC1_1_INT_ID 70U
+#define XPS_TTC1_2_INT_ID 71U
+#define XPS_DMA4_INT_ID 72U
+#define XPS_DMA5_INT_ID 73U
+#define XPS_DMA6_INT_ID 74U
+#define XPS_DMA7_INT_ID 75U
+#define XPS_USB1_INT_ID 76U
+#define XPS_GEM1_INT_ID 77U
+#define XPS_GEM1_WAKE_INT_ID 78U
+#define XPS_SDIO1_INT_ID 79U
+#define XPS_I2C1_INT_ID 80U
+#define XPS_SPI1_INT_ID 81U
+#define XPS_UART1_INT_ID 82U
+#define XPS_CAN1_INT_ID 83U
+#define XPS_FPGA8_INT_ID 84U
+#define XPS_FPGA9_INT_ID 85U
+#define XPS_FPGA10_INT_ID 86U
+#define XPS_FPGA11_INT_ID 87U
+#define XPS_FPGA12_INT_ID 88U
+#define XPS_FPGA13_INT_ID 89U
+#define XPS_FPGA14_INT_ID 90U
+#define XPS_FPGA15_INT_ID 91U
+
+/* Private Peripheral Interrupts (PPI) */
+#define XPS_GLOBAL_TMR_INT_ID 27U /* SCU Global Timer interrupt */
+#define XPS_FIQ_INT_ID 28U /* FIQ from FPGA fabric */
+#define XPS_SCU_TMR_INT_ID 29U /* SCU Private Timer interrupt */
+#define XPS_SCU_WDT_INT_ID 30U /* SCU Private WDT interrupt */
+#define XPS_IRQ_INT_ID 31U /* IRQ from FPGA fabric */
+
+
+/* REDEFINES for TEST APP */
+/* Definitions for UART */
+#define XPAR_PS7_UART_0_INTR XPS_UART0_INT_ID
+#define XPAR_PS7_UART_1_INTR XPS_UART1_INT_ID
+#define XPAR_PS7_USB_0_INTR XPS_USB0_INT_ID
+#define XPAR_PS7_USB_1_INTR XPS_USB1_INT_ID
+#define XPAR_PS7_I2C_0_INTR XPS_I2C0_INT_ID
+#define XPAR_PS7_I2C_1_INTR XPS_I2C1_INT_ID
+#define XPAR_PS7_SPI_0_INTR XPS_SPI0_INT_ID
+#define XPAR_PS7_SPI_1_INTR XPS_SPI1_INT_ID
+#define XPAR_PS7_CAN_0_INTR XPS_CAN0_INT_ID
+#define XPAR_PS7_CAN_1_INTR XPS_CAN1_INT_ID
+#define XPAR_PS7_GPIO_0_INTR XPS_GPIO_INT_ID
+#define XPAR_PS7_ETHERNET_0_INTR XPS_GEM0_INT_ID
+#define XPAR_PS7_ETHERNET_0_WAKE_INTR XPS_GEM0_WAKE_INT_ID
+#define XPAR_PS7_ETHERNET_1_INTR XPS_GEM1_INT_ID
+#define XPAR_PS7_ETHERNET_1_WAKE_INTR XPS_GEM1_WAKE_INT_ID
+#define XPAR_PS7_QSPI_0_INTR XPS_QSPI_INT_ID
+#define XPAR_PS7_WDT_0_INTR XPS_WDT_INT_ID
+#define XPAR_PS7_SCUWDT_0_INTR XPS_SCU_WDT_INT_ID
+#define XPAR_PS7_SCUTIMER_0_INTR XPS_SCU_TMR_INT_ID
+#define XPAR_PS7_XADC_0_INTR XPS_SYSMON_INT_ID
+#define XPAR_PS7_TTC_0_INTR XPS_TTC0_0_INT_ID
+#define XPAR_PS7_TTC_1_INTR XPS_TTC0_1_INT_ID
+#define XPAR_PS7_TTC_2_INTR XPS_TTC0_2_INT_ID
+#define XPAR_PS7_TTC_3_INTR XPS_TTC1_0_INT_ID
+#define XPAR_PS7_TTC_4_INTR XPS_TTC1_1_INT_ID
+#define XPAR_PS7_TTC_5_INTR XPS_TTC1_2_INT_ID
+
+#define XPAR_XADCPS_INT_ID XPS_SYSMON_INT_ID
+
+/* For backwards compatibility */
+#define XPAR_XUARTPS_0_CLOCK_HZ XPAR_XUARTPS_0_UART_CLK_FREQ_HZ
+#define XPAR_XUARTPS_1_CLOCK_HZ XPAR_XUARTPS_1_UART_CLK_FREQ_HZ
+#define XPAR_XTTCPS_0_CLOCK_HZ XPAR_XTTCPS_0_TTC_CLK_FREQ_HZ
+#define XPAR_XTTCPS_1_CLOCK_HZ XPAR_XTTCPS_1_TTC_CLK_FREQ_HZ
+#define XPAR_XTTCPS_2_CLOCK_HZ XPAR_XTTCPS_2_TTC_CLK_FREQ_HZ
+#define XPAR_XTTCPS_3_CLOCK_HZ XPAR_XTTCPS_3_TTC_CLK_FREQ_HZ
+#define XPAR_XTTCPS_4_CLOCK_HZ XPAR_XTTCPS_4_TTC_CLK_FREQ_HZ
+#define XPAR_XTTCPS_5_CLOCK_HZ XPAR_XTTCPS_5_TTC_CLK_FREQ_HZ
+#define XPAR_XIICPS_0_CLOCK_HZ XPAR_XIICPS_0_I2C_CLK_FREQ_HZ
+#define XPAR_XIICPS_1_CLOCK_HZ XPAR_XIICPS_1_I2C_CLK_FREQ_HZ
+
+#define XPAR_XQSPIPS_0_CLOCK_HZ XPAR_XQSPIPS_0_QSPI_CLK_FREQ_HZ
+
+#ifdef XPAR_CPU_CORTEXA9_0_CPU_CLK_FREQ_HZ
+#define XPAR_CPU_CORTEXA9_CORE_CLOCK_FREQ_HZ XPAR_CPU_CORTEXA9_0_CPU_CLK_FREQ_HZ
+#endif
+
+#ifdef XPAR_CPU_CORTEXA9_1_CPU_CLK_FREQ_HZ
+#define XPAR_CPU_CORTEXA9_CORE_CLOCK_FREQ_HZ XPAR_CPU_CORTEXA9_1_CPU_CLK_FREQ_HZ
+#endif
+
+#define XPAR_SCUTIMER_DEVICE_ID 0U
+#define XPAR_SCUWDT_DEVICE_ID 0U
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* protection macro */
diff --git a/hello_world/sw/app/embeddedsw-master/xpseudo_asm.h b/hello_world/sw/app/embeddedsw-master/xpseudo_asm.h
new file mode 100644
index 0000000..6d07851
--- /dev/null
+++ b/hello_world/sw/app/embeddedsw-master/xpseudo_asm.h
@@ -0,0 +1,60 @@
+/******************************************************************************
+* Copyright (c) 2009 - 2020 Xilinx, Inc. All rights reserved.
+* SPDX-License-Identifier: MIT
+******************************************************************************/
+
+/*****************************************************************************/
+/**
+*
+* @file xpseudo_asm.h
+*
+* @addtogroup a9_specific Cortex A9 Processor Specific Include Files
+*
+* The xpseudo_asm.h includes xreg_cortexa9.h and xpseudo_asm_gcc.h.
+*
+* The xreg_cortexa9.h file contains definitions for inline assembler code.
+* It provides inline definitions for Cortex A9 GPRs, SPRs, MPE registers,
+* co-processor registers and Debug registers.
+*
+* The xpseudo_asm_gcc.h contains the definitions for the most often used inline
+* assembler instructions, available as macros. These can be very useful for
+* tasks such as setting or getting special purpose registers, synchronization,
+* or cache manipulation etc. These inline assembler instructions can be used
+* from drivers and user applications written in C.
+*
+* @{
+* <pre>
+* MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ----- ---- -------- -----------------------------------------------
+* 1.00a ecm 10/18/09 First release
+* 3.04a sdm 01/02/12 Remove redundant dsb in mcr instruction.
+* 6.8 aru 09/06/18 Removed compilation warnings for ARMCC toolchain.
+* </pre>
+*
+******************************************************************************/
+#ifndef XPSEUDO_ASM_H
+#define XPSEUDO_ASM_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include "xreg_cortexa9.h"
+#ifdef __GNUC__
+ #include "xpseudo_asm_gcc.h"
+#elif defined (__ICCARM__)
+ #include "xpseudo_asm_iccarm.h"
+#else
+ #include "xpseudo_asm_rvct.h"
+#endif
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* XPSEUDO_ASM_H */
+/**
+* @} End of "addtogroup a9_specific".
+*/
diff --git a/hello_world/sw/app/embeddedsw-master/xpseudo_asm_gcc.h b/hello_world/sw/app/embeddedsw-master/xpseudo_asm_gcc.h
new file mode 100644
index 0000000..765feed
--- /dev/null
+++ b/hello_world/sw/app/embeddedsw-master/xpseudo_asm_gcc.h
@@ -0,0 +1,232 @@
+/******************************************************************************
+* Copyright (c) 2014 - 2020 Xilinx, Inc. All rights reserved.
+* SPDX-License-Identifier: MIT
+******************************************************************************/
+
+/*****************************************************************************/
+/**
+*
+* @file xpseudo_asm_gcc.h
+*
+* This header file contains macros for using inline assembler code. It is
+* written specifically for the GNU compiler.
+*
+* <pre>
+* MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ----- -------- -------- -----------------------------------------------
+* 5.00 pkp 05/21/14 First release
+* 6.0 mus 07/27/16 Consolidated file for a53,a9 and r5 processors
+* 7.2 asa 04/03/20 Renamed the str macro to strw.
+* 7.2 dp 04/30/20 Added clobber "cc" to mtcpsr for aarch32 processors
+* </pre>
+*
+******************************************************************************/
+
+#ifndef XPSEUDO_ASM_GCC_H /* prevent circular inclusions */
+#define XPSEUDO_ASM_GCC_H /* by using protection macros */
+
+/***************************** Include Files ********************************/
+
+#include "xil_types.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif /* __cplusplus */
+
+/************************** Constant Definitions ****************************/
+
+/**************************** Type Definitions ******************************/
+
+/***************** Macros (Inline Functions) Definitions ********************/
+
+/* necessary for pre-processor */
+#define stringify(s) tostring(s)
+#define tostring(s) #s
+
+#if defined (__aarch64__)
+/* pseudo assembler instructions */
+#define mfcpsr() ({u32 rval = 0U; \
+ asm volatile("mrs %0, DAIF" : "=r" (rval));\
+ rval;\
+ })
+
+#define mtcpsr(v) __asm__ __volatile__ ("msr DAIF, %0" : : "r" (v))
+
+#define cpsiei() //__asm__ __volatile__("cpsie i\n")
+#define cpsidi() //__asm__ __volatile__("cpsid i\n")
+
+#define cpsief() //__asm__ __volatile__("cpsie f\n")
+#define cpsidf() //__asm__ __volatile__("cpsid f\n")
+
+
+
+#define mtgpr(rn, v) /*__asm__ __volatile__(\
+ "mov r" stringify(rn) ", %0 \n"\
+ : : "r" (v)\
+ )*/
+
+#define mfgpr(rn) /*({u32 rval; \
+ __asm__ __volatile__(\
+ "mov %0,r" stringify(rn) "\n"\
+ : "=r" (rval)\
+ );\
+ rval;\
+ })*/
+
+/* memory synchronization operations */
+
+/* Instruction Synchronization Barrier */
+#define isb() __asm__ __volatile__ ("isb sy")
+
+/* Data Synchronization Barrier */
+#define dsb() __asm__ __volatile__("dsb sy")
+
+/* Data Memory Barrier */
+#define dmb() __asm__ __volatile__("dmb sy")
+
+
+/* Memory Operations */
+#define ldr(adr) ({u64 rval; \
+ __asm__ __volatile__(\
+ "ldr %0,[%1]"\
+ : "=r" (rval) : "r" (adr)\
+ );\
+ rval;\
+ })
+
+#define mfelrel3() ({u64 rval = 0U; \
+ asm volatile("mrs %0, ELR_EL3" : "=r" (rval));\
+ rval;\
+ })
+
+#define mtelrel3(v) __asm__ __volatile__ ("msr ELR_EL3, %0" : : "r" (v))
+
+#else
+
+/* pseudo assembler instructions */
+#define mfcpsr() ({u32 rval = 0U; \
+ __asm__ __volatile__(\
+ "mrs %0, cpsr\n"\
+ : "=r" (rval)\
+ );\
+ rval;\
+ })
+
+#define mtcpsr(v) __asm__ __volatile__(\
+ "msr cpsr,%0\n"\
+ : : "r" (v) : "cc" \
+ )
+
+#define cpsiei() __asm__ __volatile__("cpsie i\n")
+#define cpsidi() __asm__ __volatile__("cpsid i\n")
+
+#define cpsief() __asm__ __volatile__("cpsie f\n")
+#define cpsidf() __asm__ __volatile__("cpsid f\n")
+
+
+
+#define mtgpr(rn, v) __asm__ __volatile__(\
+ "mov r" stringify(rn) ", %0 \n"\
+ : : "r" (v)\
+ )
+
+#define mfgpr(rn) ({u32 rval; \
+ __asm__ __volatile__(\
+ "mov %0,r" stringify(rn) "\n"\
+ : "=r" (rval)\
+ );\
+ rval;\
+ })
+
+/* memory synchronization operations */
+
+/* Instruction Synchronization Barrier */
+#define isb() __asm__ __volatile__ ("isb" : : : "memory")
+
+/* Data Synchronization Barrier */
+#define dsb() __asm__ __volatile__ ("dsb" : : : "memory")
+
+/* Data Memory Barrier */
+#define dmb() __asm__ __volatile__ ("dmb" : : : "memory")
+
+
+/* Memory Operations */
+#define ldr(adr) ({u32 rval; \
+ __asm__ __volatile__(\
+ "ldr %0,[%1]"\
+ : "=r" (rval) : "r" (adr)\
+ );\
+ rval;\
+ })
+
+#endif
+
+#define ldrb(adr) ({u8 rval; \
+ __asm__ __volatile__(\
+ "ldrb %0,[%1]"\
+ : "=r" (rval) : "r" (adr)\
+ );\
+ rval;\
+ })
+
+#define strw(adr, val) __asm__ __volatile__(\
+ "str %0,[%1]\n"\
+ : : "r" (val), "r" (adr)\
+ )
+
+#define strb(adr, val) __asm__ __volatile__(\
+ "strb %0,[%1]\n"\
+ : : "r" (val), "r" (adr)\
+ )
+
+/* Count leading zeroes (clz) */
+#define clz(arg) ({u8 rval; \
+ __asm__ __volatile__(\
+ "clz %0,%1"\
+ : "=r" (rval) : "r" (arg)\
+ );\
+ rval;\
+ })
+
+#if defined (__aarch64__)
+#define mtcpdc(reg,val) __asm__ __volatile__("dc " #reg ",%0" : : "r" (val))
+#define mtcpic(reg,val) __asm__ __volatile__("ic " #reg ",%0" : : "r" (val))
+
+#define mtcpicall(reg) __asm__ __volatile__("ic " #reg)
+#define mtcptlbi(reg) __asm__ __volatile__("tlbi " #reg)
+#define mtcpat(reg,val) __asm__ __volatile__("at " #reg ",%0" : : "r" (val))
+/* CP15 operations */
+#define mfcp(reg) ({u64 rval = 0U;\
+ __asm__ __volatile__("mrs %0, " #reg : "=r" (rval));\
+ rval;\
+ })
+
+#define mtcp(reg,val) __asm__ __volatile__("msr " #reg ",%0" : : "r" (val))
+
+#else
+/* CP15 operations */
+#define mtcp(rn, v) __asm__ __volatile__(\
+ "mcr " rn "\n"\
+ : : "r" (v)\
+ );
+
+#define mfcp(rn) ({u32 rval = 0U; \
+ __asm__ __volatile__(\
+ "mrc " rn "\n"\
+ : "=r" (rval)\
+ );\
+ rval;\
+ })
+#endif
+
+/************************** Variable Definitions ****************************/
+
+/************************** Function Prototypes *****************************/
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+
+#endif /* XPSEUDO_ASM_GCC_H */
diff --git a/hello_world/sw/app/embeddedsw-master/xreg_cortexa9.h b/hello_world/sw/app/embeddedsw-master/xreg_cortexa9.h
new file mode 100644
index 0000000..06506d6
--- /dev/null
+++ b/hello_world/sw/app/embeddedsw-master/xreg_cortexa9.h
@@ -0,0 +1,565 @@
+/******************************************************************************
+* Copyright (c) 2009 - 2020 Xilinx, Inc. All rights reserved.
+* SPDX-License-Identifier: MIT
+******************************************************************************/
+
+/*****************************************************************************/
+/**
+*
+* @file xreg_cortexa9.h
+*
+* This header file contains definitions for using inline assembler code. It is
+* written specifically for the GNU, ARMCC compiler.
+*
+* All of the ARM Cortex A9 GPRs, SPRs, and Debug Registers are defined along
+* with the positions of the bits within the registers.
+*
+* <pre>
+* MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ----- -------- -------- -----------------------------------------------
+* 1.00a ecm/sdm 10/20/09 First release
+* </pre>
+*
+******************************************************************************/
+#ifndef XREG_CORTEXA9_H
+#define XREG_CORTEXA9_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif /* __cplusplus */
+
+/* GPRs */
+#define XREG_GPR0 r0
+#define XREG_GPR1 r1
+#define XREG_GPR2 r2
+#define XREG_GPR3 r3
+#define XREG_GPR4 r4
+#define XREG_GPR5 r5
+#define XREG_GPR6 r6
+#define XREG_GPR7 r7
+#define XREG_GPR8 r8
+#define XREG_GPR9 r9
+#define XREG_GPR10 r10
+#define XREG_GPR11 r11
+#define XREG_GPR12 r12
+#define XREG_GPR13 r13
+#define XREG_GPR14 r14
+#define XREG_GPR15 r15
+#define XREG_CPSR cpsr
+
+/* Coprocessor number defines */
+#define XREG_CP0 0
+#define XREG_CP1 1
+#define XREG_CP2 2
+#define XREG_CP3 3
+#define XREG_CP4 4
+#define XREG_CP5 5
+#define XREG_CP6 6
+#define XREG_CP7 7
+#define XREG_CP8 8
+#define XREG_CP9 9
+#define XREG_CP10 10
+#define XREG_CP11 11
+#define XREG_CP12 12
+#define XREG_CP13 13
+#define XREG_CP14 14
+#define XREG_CP15 15
+
+/* Coprocessor control register defines */
+#define XREG_CR0 cr0
+#define XREG_CR1 cr1
+#define XREG_CR2 cr2
+#define XREG_CR3 cr3
+#define XREG_CR4 cr4
+#define XREG_CR5 cr5
+#define XREG_CR6 cr6
+#define XREG_CR7 cr7
+#define XREG_CR8 cr8
+#define XREG_CR9 cr9
+#define XREG_CR10 cr10
+#define XREG_CR11 cr11
+#define XREG_CR12 cr12
+#define XREG_CR13 cr13
+#define XREG_CR14 cr14
+#define XREG_CR15 cr15
+
+/* Current Processor Status Register (CPSR) Bits */
+#define XREG_CPSR_THUMB_MODE 0x20
+#define XREG_CPSR_MODE_BITS 0x1F
+#define XREG_CPSR_SYSTEM_MODE 0x1F
+#define XREG_CPSR_UNDEFINED_MODE 0x1B
+#define XREG_CPSR_DATA_ABORT_MODE 0x17
+#define XREG_CPSR_SVC_MODE 0x13
+#define XREG_CPSR_IRQ_MODE 0x12
+#define XREG_CPSR_FIQ_MODE 0x11
+#define XREG_CPSR_USER_MODE 0x10
+
+#define XREG_CPSR_IRQ_ENABLE 0x80
+#define XREG_CPSR_FIQ_ENABLE 0x40
+
+#define XREG_CPSR_N_BIT 0x80000000
+#define XREG_CPSR_Z_BIT 0x40000000
+#define XREG_CPSR_C_BIT 0x20000000
+#define XREG_CPSR_V_BIT 0x10000000
+
+
+/* CP15 defines */
+#if defined (__GNUC__) || defined (__ICCARM__)
+/* C0 Register defines */
+#define XREG_CP15_MAIN_ID "p15, 0, %0, c0, c0, 0"
+#define XREG_CP15_CACHE_TYPE "p15, 0, %0, c0, c0, 1"
+#define XREG_CP15_TCM_TYPE "p15, 0, %0, c0, c0, 2"
+#define XREG_CP15_TLB_TYPE "p15, 0, %0, c0, c0, 3"
+#define XREG_CP15_MULTI_PROC_AFFINITY "p15, 0, %0, c0, c0, 5"
+
+#define XREG_CP15_PROC_FEATURE_0 "p15, 0, %0, c0, c1, 0"
+#define XREG_CP15_PROC_FEATURE_1 "p15, 0, %0, c0, c1, 1"
+#define XREG_CP15_DEBUG_FEATURE_0 "p15, 0, %0, c0, c1, 2"
+#define XREG_CP15_MEMORY_FEATURE_0 "p15, 0, %0, c0, c1, 4"
+#define XREG_CP15_MEMORY_FEATURE_1 "p15, 0, %0, c0, c1, 5"
+#define XREG_CP15_MEMORY_FEATURE_2 "p15, 0, %0, c0, c1, 6"
+#define XREG_CP15_MEMORY_FEATURE_3 "p15, 0, %0, c0, c1, 7"
+
+#define XREG_CP15_INST_FEATURE_0 "p15, 0, %0, c0, c2, 0"
+#define XREG_CP15_INST_FEATURE_1 "p15, 0, %0, c0, c2, 1"
+#define XREG_CP15_INST_FEATURE_2 "p15, 0, %0, c0, c2, 2"
+#define XREG_CP15_INST_FEATURE_3 "p15, 0, %0, c0, c2, 3"
+#define XREG_CP15_INST_FEATURE_4 "p15, 0, %0, c0, c2, 4"
+
+#define XREG_CP15_CACHE_SIZE_ID "p15, 1, %0, c0, c0, 0"
+#define XREG_CP15_CACHE_LEVEL_ID "p15, 1, %0, c0, c0, 1"
+#define XREG_CP15_AUXILARY_ID "p15, 1, %0, c0, c0, 7"
+
+#define XREG_CP15_CACHE_SIZE_SEL "p15, 2, %0, c0, c0, 0"
+
+/* C1 Register Defines */
+#define XREG_CP15_SYS_CONTROL "p15, 0, %0, c1, c0, 0"
+#define XREG_CP15_AUX_CONTROL "p15, 0, %0, c1, c0, 1"
+#define XREG_CP15_CP_ACCESS_CONTROL "p15, 0, %0, c1, c0, 2"
+
+#define XREG_CP15_SECURE_CONFIG "p15, 0, %0, c1, c1, 0"
+#define XREG_CP15_SECURE_DEBUG_ENABLE "p15, 0, %0, c1, c1, 1"
+#define XREG_CP15_NS_ACCESS_CONTROL "p15, 0, %0, c1, c1, 2"
+#define XREG_CP15_VIRTUAL_CONTROL "p15, 0, %0, c1, c1, 3"
+
+#else /* RVCT */
+/* C0 Register defines */
+#define XREG_CP15_MAIN_ID "cp15:0:c0:c0:0"
+#define XREG_CP15_CACHE_TYPE "cp15:0:c0:c0:1"
+#define XREG_CP15_TCM_TYPE "cp15:0:c0:c0:2"
+#define XREG_CP15_TLB_TYPE "cp15:0:c0:c0:3"
+#define XREG_CP15_MULTI_PROC_AFFINITY "cp15:0:c0:c0:5"
+
+#define XREG_CP15_PROC_FEATURE_0 "cp15:0:c0:c1:0"
+#define XREG_CP15_PROC_FEATURE_1 "cp15:0:c0:c1:1"
+#define XREG_CP15_DEBUG_FEATURE_0 "cp15:0:c0:c1:2"
+#define XREG_CP15_MEMORY_FEATURE_0 "cp15:0:c0:c1:4"
+#define XREG_CP15_MEMORY_FEATURE_1 "cp15:0:c0:c1:5"
+#define XREG_CP15_MEMORY_FEATURE_2 "cp15:0:c0:c1:6"
+#define XREG_CP15_MEMORY_FEATURE_3 "cp15:0:c0:c1:7"
+
+#define XREG_CP15_INST_FEATURE_0 "cp15:0:c0:c2:0"
+#define XREG_CP15_INST_FEATURE_1 "cp15:0:c0:c2:1"
+#define XREG_CP15_INST_FEATURE_2 "cp15:0:c0:c2:2"
+#define XREG_CP15_INST_FEATURE_3 "cp15:0:c0:c2:3"
+#define XREG_CP15_INST_FEATURE_4 "cp15:0:c0:c2:4"
+
+#define XREG_CP15_CACHE_SIZE_ID "cp15:1:c0:c0:0"
+#define XREG_CP15_CACHE_LEVEL_ID "cp15:1:c0:c0:1"
+#define XREG_CP15_AUXILARY_ID "cp15:1:c0:c0:7"
+
+#define XREG_CP15_CACHE_SIZE_SEL "cp15:2:c0:c0:0"
+
+/* C1 Register Defines */
+#define XREG_CP15_SYS_CONTROL "cp15:0:c1:c0:0"
+#define XREG_CP15_AUX_CONTROL "cp15:0:c1:c0:1"
+#define XREG_CP15_CP_ACCESS_CONTROL "cp15:0:c1:c0:2"
+
+#define XREG_CP15_SECURE_CONFIG "cp15:0:c1:c1:0"
+#define XREG_CP15_SECURE_DEBUG_ENABLE "cp15:0:c1:c1:1"
+#define XREG_CP15_NS_ACCESS_CONTROL "cp15:0:c1:c1:2"
+#define XREG_CP15_VIRTUAL_CONTROL "cp15:0:c1:c1:3"
+#endif
+
+/* XREG_CP15_CONTROL bit defines */
+#define XREG_CP15_CONTROL_TE_BIT 0x40000000U
+#define XREG_CP15_CONTROL_AFE_BIT 0x20000000U
+#define XREG_CP15_CONTROL_TRE_BIT 0x10000000U
+#define XREG_CP15_CONTROL_NMFI_BIT 0x08000000U
+#define XREG_CP15_CONTROL_EE_BIT 0x02000000U
+#define XREG_CP15_CONTROL_HA_BIT 0x00020000U
+#define XREG_CP15_CONTROL_RR_BIT 0x00004000U
+#define XREG_CP15_CONTROL_V_BIT 0x00002000U
+#define XREG_CP15_CONTROL_I_BIT 0x00001000U
+#define XREG_CP15_CONTROL_Z_BIT 0x00000800U
+#define XREG_CP15_CONTROL_SW_BIT 0x00000400U
+#define XREG_CP15_CONTROL_B_BIT 0x00000080U
+#define XREG_CP15_CONTROL_C_BIT 0x00000004U
+#define XREG_CP15_CONTROL_A_BIT 0x00000002U
+#define XREG_CP15_CONTROL_M_BIT 0x00000001U
+
+#if defined (__GNUC__) || defined (__ICCARM__)
+/* C2 Register Defines */
+#define XREG_CP15_TTBR0 "p15, 0, %0, c2, c0, 0"
+#define XREG_CP15_TTBR1 "p15, 0, %0, c2, c0, 1"
+#define XREG_CP15_TTB_CONTROL "p15, 0, %0, c2, c0, 2"
+
+/* C3 Register Defines */
+#define XREG_CP15_DOMAIN_ACCESS_CTRL "p15, 0, %0, c3, c0, 0"
+
+/* C4 Register Defines */
+/* Not Used */
+
+/* C5 Register Defines */
+#define XREG_CP15_DATA_FAULT_STATUS "p15, 0, %0, c5, c0, 0"
+#define XREG_CP15_INST_FAULT_STATUS "p15, 0, %0, c5, c0, 1"
+
+#define XREG_CP15_AUX_DATA_FAULT_STATUS "p15, 0, %0, c5, c1, 0"
+#define XREG_CP15_AUX_INST_FAULT_STATUS "p15, 0, %0, c5, c1, 1"
+
+/* C6 Register Defines */
+#define XREG_CP15_DATA_FAULT_ADDRESS "p15, 0, %0, c6, c0, 0"
+#define XREG_CP15_INST_FAULT_ADDRESS "p15, 0, %0, c6, c0, 2"
+
+/* C7 Register Defines */
+#define XREG_CP15_NOP "p15, 0, %0, c7, c0, 4"
+
+#define XREG_CP15_INVAL_IC_POU_IS "p15, 0, %0, c7, c1, 0"
+#define XREG_CP15_INVAL_BRANCH_ARRAY_IS "p15, 0, %0, c7, c1, 6"
+
+#define XREG_CP15_PHYS_ADDR "p15, 0, %0, c7, c4, 0"
+
+#define XREG_CP15_INVAL_IC_POU "p15, 0, %0, c7, c5, 0"
+#define XREG_CP15_INVAL_IC_LINE_MVA_POU "p15, 0, %0, c7, c5, 1"
+
+/* The CP15 register access below has been deprecated in favor of the new
+ * isb instruction in Cortex A9.
+ */
+#define XREG_CP15_INST_SYNC_BARRIER "p15, 0, %0, c7, c5, 4"
+#define XREG_CP15_INVAL_BRANCH_ARRAY "p15, 0, %0, c7, c5, 6"
+
+#define XREG_CP15_INVAL_DC_LINE_MVA_POC "p15, 0, %0, c7, c6, 1"
+#define XREG_CP15_INVAL_DC_LINE_SW "p15, 0, %0, c7, c6, 2"
+
+#define XREG_CP15_VA_TO_PA_CURRENT_0 "p15, 0, %0, c7, c8, 0"
+#define XREG_CP15_VA_TO_PA_CURRENT_1 "p15, 0, %0, c7, c8, 1"
+#define XREG_CP15_VA_TO_PA_CURRENT_2 "p15, 0, %0, c7, c8, 2"
+#define XREG_CP15_VA_TO_PA_CURRENT_3 "p15, 0, %0, c7, c8, 3"
+
+#define XREG_CP15_VA_TO_PA_OTHER_0 "p15, 0, %0, c7, c8, 4"
+#define XREG_CP15_VA_TO_PA_OTHER_1 "p15, 0, %0, c7, c8, 5"
+#define XREG_CP15_VA_TO_PA_OTHER_2 "p15, 0, %0, c7, c8, 6"
+#define XREG_CP15_VA_TO_PA_OTHER_3 "p15, 0, %0, c7, c8, 7"
+
+#define XREG_CP15_CLEAN_DC_LINE_MVA_POC "p15, 0, %0, c7, c10, 1"
+#define XREG_CP15_CLEAN_DC_LINE_SW "p15, 0, %0, c7, c10, 2"
+
+/* The next two CP15 register accesses below have been deprecated in favor
+ * of the new dsb and dmb instructions in Cortex A9.
+ */
+#define XREG_CP15_DATA_SYNC_BARRIER "p15, 0, %0, c7, c10, 4"
+#define XREG_CP15_DATA_MEMORY_BARRIER "p15, 0, %0, c7, c10, 5"
+
+#define XREG_CP15_CLEAN_DC_LINE_MVA_POU "p15, 0, %0, c7, c11, 1"
+
+#define XREG_CP15_NOP2 "p15, 0, %0, c7, c13, 1"
+
+#define XREG_CP15_CLEAN_INVAL_DC_LINE_MVA_POC "p15, 0, %0, c7, c14, 1"
+#define XREG_CP15_CLEAN_INVAL_DC_LINE_SW "p15, 0, %0, c7, c14, 2"
+
+/* C8 Register Defines */
+#define XREG_CP15_INVAL_TLB_IS "p15, 0, %0, c8, c3, 0"
+#define XREG_CP15_INVAL_TLB_MVA_IS "p15, 0, %0, c8, c3, 1"
+#define XREG_CP15_INVAL_TLB_ASID_IS "p15, 0, %0, c8, c3, 2"
+#define XREG_CP15_INVAL_TLB_MVA_ASID_IS "p15, 0, %0, c8, c3, 3"
+
+#define XREG_CP15_INVAL_ITLB_UNLOCKED "p15, 0, %0, c8, c5, 0"
+#define XREG_CP15_INVAL_ITLB_MVA "p15, 0, %0, c8, c5, 1"
+#define XREG_CP15_INVAL_ITLB_ASID "p15, 0, %0, c8, c5, 2"
+
+#define XREG_CP15_INVAL_DTLB_UNLOCKED "p15, 0, %0, c8, c6, 0"
+#define XREG_CP15_INVAL_DTLB_MVA "p15, 0, %0, c8, c6, 1"
+#define XREG_CP15_INVAL_DTLB_ASID "p15, 0, %0, c8, c6, 2"
+
+#define XREG_CP15_INVAL_UTLB_UNLOCKED "p15, 0, %0, c8, c7, 0"
+#define XREG_CP15_INVAL_UTLB_MVA "p15, 0, %0, c8, c7, 1"
+#define XREG_CP15_INVAL_UTLB_ASID "p15, 0, %0, c8, c7, 2"
+#define XREG_CP15_INVAL_UTLB_MVA_ASID "p15, 0, %0, c8, c7, 3"
+
+/* C9 Register Defines */
+#define XREG_CP15_PERF_MONITOR_CTRL "p15, 0, %0, c9, c12, 0"
+#define XREG_CP15_COUNT_ENABLE_SET "p15, 0, %0, c9, c12, 1"
+#define XREG_CP15_COUNT_ENABLE_CLR "p15, 0, %0, c9, c12, 2"
+#define XREG_CP15_V_FLAG_STATUS "p15, 0, %0, c9, c12, 3"
+#define XREG_CP15_SW_INC "p15, 0, %0, c9, c12, 4"
+#define XREG_CP15_EVENT_CNTR_SEL "p15, 0, %0, c9, c12, 5"
+
+#define XREG_CP15_PERF_CYCLE_COUNTER "p15, 0, %0, c9, c13, 0"
+#define XREG_CP15_EVENT_TYPE_SEL "p15, 0, %0, c9, c13, 1"
+#define XREG_CP15_PERF_MONITOR_COUNT "p15, 0, %0, c9, c13, 2"
+
+#define XREG_CP15_USER_ENABLE "p15, 0, %0, c9, c14, 0"
+#define XREG_CP15_INTR_ENABLE_SET "p15, 0, %0, c9, c14, 1"
+#define XREG_CP15_INTR_ENABLE_CLR "p15, 0, %0, c9, c14, 2"
+
+/* C10 Register Defines */
+#define XREG_CP15_TLB_LOCKDWN "p15, 0, %0, c10, c0, 0"
+
+#define XREG_CP15_PRI_MEM_REMAP "p15, 0, %0, c10, c2, 0"
+#define XREG_CP15_NORM_MEM_REMAP "p15, 0, %0, c10, c2, 1"
+
+/* C11 Register Defines */
+/* Not used */
+
+/* C12 Register Defines */
+#define XREG_CP15_VEC_BASE_ADDR "p15, 0, %0, c12, c0, 0"
+#define XREG_CP15_MONITOR_VEC_BASE_ADDR "p15, 0, %0, c12, c0, 1"
+
+#define XREG_CP15_INTERRUPT_STATUS "p15, 0, %0, c12, c1, 0"
+#define XREG_CP15_VIRTUALIZATION_INTR "p15, 0, %0, c12, c1, 1"
+
+/* C13 Register Defines */
+#define XREG_CP15_CONTEXT_ID "p15, 0, %0, c13, c0, 1"
+#define USER_RW_THREAD_PID "p15, 0, %0, c13, c0, 2"
+#define USER_RO_THREAD_PID "p15, 0, %0, c13, c0, 3"
+#define USER_PRIV_THREAD_PID "p15, 0, %0, c13, c0, 4"
+
+/* C14 Register Defines */
+/* not used */
+
+/* C15 Register Defines */
+#define XREG_CP15_POWER_CTRL "p15, 0, %0, c15, c0, 0"
+#define XREG_CP15_CONFIG_BASE_ADDR "p15, 4, %0, c15, c0, 0"
+
+#define XREG_CP15_READ_TLB_ENTRY "p15, 5, %0, c15, c4, 2"
+#define XREG_CP15_WRITE_TLB_ENTRY "p15, 5, %0, c15, c4, 4"
+
+#define XREG_CP15_MAIN_TLB_VA "p15, 5, %0, c15, c5, 2"
+
+#define XREG_CP15_MAIN_TLB_PA "p15, 5, %0, c15, c6, 2"
+
+#define XREG_CP15_MAIN_TLB_ATTR "p15, 5, %0, c15, c7, 2"
+
+#else
+/* C2 Register Defines */
+#define XREG_CP15_TTBR0 "cp15:0:c2:c0:0"
+#define XREG_CP15_TTBR1 "cp15:0:c2:c0:1"
+#define XREG_CP15_TTB_CONTROL "cp15:0:c2:c0:2"
+
+/* C3 Register Defines */
+#define XREG_CP15_DOMAIN_ACCESS_CTRL "cp15:0:c3:c0:0"
+
+/* C4 Register Defines */
+/* Not Used */
+
+/* C5 Register Defines */
+#define XREG_CP15_DATA_FAULT_STATUS "cp15:0:c5:c0:0"
+#define XREG_CP15_INST_FAULT_STATUS "cp15:0:c5:c0:1"
+
+#define XREG_CP15_AUX_DATA_FAULT_STATUS "cp15:0:c5:c1:0"
+#define XREG_CP15_AUX_INST_FAULT_STATUS "cp15:0:c5:c1:1"
+
+/* C6 Register Defines */
+#define XREG_CP15_DATA_FAULT_ADDRESS "cp15:0:c6:c0:0"
+#define XREG_CP15_INST_FAULT_ADDRESS "cp15:0:c6:c0:2"
+
+/* C7 Register Defines */
+#define XREG_CP15_NOP "cp15:0:c7:c0:4"
+
+#define XREG_CP15_INVAL_IC_POU_IS "cp15:0:c7:c1:0"
+#define XREG_CP15_INVAL_BRANCH_ARRAY_IS "cp15:0:c7:c1:6"
+
+#define XREG_CP15_PHYS_ADDR "cp15:0:c7:c4:0"
+
+#define XREG_CP15_INVAL_IC_POU "cp15:0:c7:c5:0"
+#define XREG_CP15_INVAL_IC_LINE_MVA_POU "cp15:0:c7:c5:1"
+
+/* The CP15 register access below has been deprecated in favor of the new
+ * isb instruction in Cortex A9.
+ */
+#define XREG_CP15_INST_SYNC_BARRIER "cp15:0:c7:c5:4"
+#define XREG_CP15_INVAL_BRANCH_ARRAY "cp15:0:c7:c5:6"
+
+#define XREG_CP15_INVAL_DC_LINE_MVA_POC "cp15:0:c7:c6:1"
+#define XREG_CP15_INVAL_DC_LINE_SW "cp15:0:c7:c6:2"
+
+#define XREG_CP15_VA_TO_PA_CURRENT_0 "cp15:0:c7:c8:0"
+#define XREG_CP15_VA_TO_PA_CURRENT_1 "cp15:0:c7:c8:1"
+#define XREG_CP15_VA_TO_PA_CURRENT_2 "cp15:0:c7:c8:2"
+#define XREG_CP15_VA_TO_PA_CURRENT_3 "cp15:0:c7:c8:3"
+
+#define XREG_CP15_VA_TO_PA_OTHER_0 "cp15:0:c7:c8:4"
+#define XREG_CP15_VA_TO_PA_OTHER_1 "cp15:0:c7:c8:5"
+#define XREG_CP15_VA_TO_PA_OTHER_2 "cp15:0:c7:c8:6"
+#define XREG_CP15_VA_TO_PA_OTHER_3 "cp15:0:c7:c8:7"
+
+#define XREG_CP15_CLEAN_DC_LINE_MVA_POC "cp15:0:c7:c10:1"
+#define XREG_CP15_CLEAN_DC_LINE_SW "cp15:0:c7:c10:2"
+
+/* The next two CP15 register accesses below have been deprecated in favor
+ * of the new dsb and dmb instructions in Cortex A9.
+ */
+#define XREG_CP15_DATA_SYNC_BARRIER "cp15:0:c7:c10:4"
+#define XREG_CP15_DATA_MEMORY_BARRIER "cp15:0:c7:c10:5"
+
+#define XREG_CP15_CLEAN_DC_LINE_MVA_POU "cp15:0:c7:c11:1"
+
+#define XREG_CP15_NOP2 "cp15:0:c7:c13:1"
+
+#define XREG_CP15_CLEAN_INVAL_DC_LINE_MVA_POC "cp15:0:c7:c14:1"
+#define XREG_CP15_CLEAN_INVAL_DC_LINE_SW "cp15:0:c7:c14:2"
+
+/* C8 Register Defines */
+#define XREG_CP15_INVAL_TLB_IS "cp15:0:c8:c3:0"
+#define XREG_CP15_INVAL_TLB_MVA_IS "cp15:0:c8:c3:1"
+#define XREG_CP15_INVAL_TLB_ASID_IS "cp15:0:c8:c3:2"
+#define XREG_CP15_INVAL_TLB_MVA_ASID_IS "cp15:0:c8:c3:3"
+
+#define XREG_CP15_INVAL_ITLB_UNLOCKED "cp15:0:c8:c5:0"
+#define XREG_CP15_INVAL_ITLB_MVA "cp15:0:c8:c5:1"
+#define XREG_CP15_INVAL_ITLB_ASID "cp15:0:c8:c5:2"
+
+#define XREG_CP15_INVAL_DTLB_UNLOCKED "cp15:0:c8:c6:0"
+#define XREG_CP15_INVAL_DTLB_MVA "cp15:0:c8:c6:1"
+#define XREG_CP15_INVAL_DTLB_ASID "cp15:0:c8:c6:2"
+
+#define XREG_CP15_INVAL_UTLB_UNLOCKED "cp15:0:c8:c7:0"
+#define XREG_CP15_INVAL_UTLB_MVA "cp15:0:c8:c7:1"
+#define XREG_CP15_INVAL_UTLB_ASID "cp15:0:c8:c7:2"
+#define XREG_CP15_INVAL_UTLB_MVA_ASID "cp15:0:c8:c7:3"
+
+/* C9 Register Defines */
+#define XREG_CP15_PERF_MONITOR_CTRL "cp15:0:c9:c12:0"
+#define XREG_CP15_COUNT_ENABLE_SET "cp15:0:c9:c12:1"
+#define XREG_CP15_COUNT_ENABLE_CLR "cp15:0:c9:c12:2"
+#define XREG_CP15_V_FLAG_STATUS "cp15:0:c9:c12:3"
+#define XREG_CP15_SW_INC "cp15:0:c9:c12:4"
+#define XREG_CP15_EVENT_CNTR_SEL "cp15:0:c9:c12:5"
+
+#define XREG_CP15_PERF_CYCLE_COUNTER "cp15:0:c9:c13:0"
+#define XREG_CP15_EVENT_TYPE_SEL "cp15:0:c9:c13:1"
+#define XREG_CP15_PERF_MONITOR_COUNT "cp15:0:c9:c13:2"
+
+#define XREG_CP15_USER_ENABLE "cp15:0:c9:c14:0"
+#define XREG_CP15_INTR_ENABLE_SET "cp15:0:c9:c14:1"
+#define XREG_CP15_INTR_ENABLE_CLR "cp15:0:c9:c14:2"
+
+/* C10 Register Defines */
+#define XREG_CP15_TLB_LOCKDWN "cp15:0:c10:c0:0"
+
+#define XREG_CP15_PRI_MEM_REMAP "cp15:0:c10:c2:0"
+#define XREG_CP15_NORM_MEM_REMAP "cp15:0:c10:c2:1"
+
+/* C11 Register Defines */
+/* Not used */
+
+/* C12 Register Defines */
+#define XREG_CP15_VEC_BASE_ADDR "cp15:0:c12:c0:0"
+#define XREG_CP15_MONITOR_VEC_BASE_ADDR "cp15:0:c12:c0:1"
+
+#define XREG_CP15_INTERRUPT_STATUS "cp15:0:c12:c1:0"
+#define XREG_CP15_VIRTUALIZATION_INTR "cp15:0:c12:c1:1"
+
+/* C13 Register Defines */
+#define XREG_CP15_CONTEXT_ID "cp15:0:c13:c0:1"
+#define USER_RW_THREAD_PID "cp15:0:c13:c0:2"
+#define USER_RO_THREAD_PID "cp15:0:c13:c0:3"
+#define USER_PRIV_THREAD_PID "cp15:0:c13:c0:4"
+
+/* C14 Register Defines */
+/* not used */
+
+/* C15 Register Defines */
+#define XREG_CP15_POWER_CTRL "cp15:0:c15:c0:0"
+#define XREG_CP15_CONFIG_BASE_ADDR "cp15:4:c15:c0:0"
+
+#define XREG_CP15_READ_TLB_ENTRY "cp15:5:c15:c4:2"
+#define XREG_CP15_WRITE_TLB_ENTRY "cp15:5:c15:c4:4"
+
+#define XREG_CP15_MAIN_TLB_VA "cp15:5:c15:c5:2"
+
+#define XREG_CP15_MAIN_TLB_PA "cp15:5:c15:c6:2"
+
+#define XREG_CP15_MAIN_TLB_ATTR "cp15:5:c15:c7:2"
+#endif
+
+
+/* MPE register definitions */
+#define XREG_FPSID c0
+#define XREG_FPSCR c1
+#define XREG_MVFR1 c6
+#define XREG_MVFR0 c7
+#define XREG_FPEXC c8
+#define XREG_FPINST c9
+#define XREG_FPINST2 c10
+
+/* FPSID bits */
+#define XREG_FPSID_IMPLEMENTER_BIT (24)
+#define XREG_FPSID_IMPLEMENTER_MASK (0xFF << FPSID_IMPLEMENTER_BIT)
+#define XREG_FPSID_SOFTWARE (1<<23)
+#define XREG_FPSID_ARCH_BIT (16)
+#define XREG_FPSID_ARCH_MASK (0xF << FPSID_ARCH_BIT)
+#define XREG_FPSID_PART_BIT (8)
+#define XREG_FPSID_PART_MASK (0xFF << FPSID_PART_BIT)
+#define XREG_FPSID_VARIANT_BIT (4)
+#define XREG_FPSID_VARIANT_MASK (0xF << FPSID_VARIANT_BIT)
+#define XREG_FPSID_REV_BIT (0)
+#define XREG_FPSID_REV_MASK (0xF << FPSID_REV_BIT)
+
+/* FPSCR bits */
+#define XREG_FPSCR_N_BIT (1 << 31)
+#define XREG_FPSCR_Z_BIT (1 << 30)
+#define XREG_FPSCR_C_BIT (1 << 29)
+#define XREG_FPSCR_V_BIT (1 << 28)
+#define XREG_FPSCR_QC (1 << 27)
+#define XREG_FPSCR_AHP (1 << 26)
+#define XREG_FPSCR_DEFAULT_NAN (1 << 25)
+#define XREG_FPSCR_FLUSHTOZERO (1 << 24)
+#define XREG_FPSCR_ROUND_NEAREST (0 << 22)
+#define XREG_FPSCR_ROUND_PLUSINF (1 << 22)
+#define XREG_FPSCR_ROUND_MINUSINF (2 << 22)
+#define XREG_FPSCR_ROUND_TOZERO (3 << 22)
+#define XREG_FPSCR_RMODE_BIT (22)
+#define XREG_FPSCR_RMODE_MASK (3 << FPSCR_RMODE_BIT)
+#define XREG_FPSCR_STRIDE_BIT (20)
+#define XREG_FPSCR_STRIDE_MASK (3 << FPSCR_STRIDE_BIT)
+#define XREG_FPSCR_LENGTH_BIT (16)
+#define XREG_FPSCR_LENGTH_MASK (7 << FPSCR_LENGTH_BIT)
+#define XREG_FPSCR_IDC (1 << 7)
+#define XREG_FPSCR_IXC (1 << 4)
+#define XREG_FPSCR_UFC (1 << 3)
+#define XREG_FPSCR_OFC (1 << 2)
+#define XREG_FPSCR_DZC (1 << 1)
+#define XREG_FPSCR_IOC (1 << 0)
+
+/* MVFR0 bits */
+#define XREG_MVFR0_RMODE_BIT (28)
+#define XREG_MVFR0_RMODE_MASK (0xF << XREG_MVFR0_RMODE_BIT)
+#define XREG_MVFR0_SHORT_VEC_BIT (24)
+#define XREG_MVFR0_SHORT_VEC_MASK (0xF << XREG_MVFR0_SHORT_VEC_BIT)
+#define XREG_MVFR0_SQRT_BIT (20)
+#define XREG_MVFR0_SQRT_MASK (0xF << XREG_MVFR0_SQRT_BIT)
+#define XREG_MVFR0_DIVIDE_BIT (16)
+#define XREG_MVFR0_DIVIDE_MASK (0xF << XREG_MVFR0_DIVIDE_BIT)
+#define XREG_MVFR0_EXEC_TRAP_BIT (12)
+#define XREG_MVFR0_EXEC_TRAP_MASK (0xF << XREG_MVFR0_EXEC_TRAP_BIT)
+#define XREG_MVFR0_DP_BIT (8)
+#define XREG_MVFR0_DP_MASK (0xF << XREG_MVFR0_DP_BIT)
+#define XREG_MVFR0_SP_BIT (4)
+#define XREG_MVFR0_SP_MASK (0xF << XREG_MVFR0_SP_BIT)
+#define XREG_MVFR0_A_SIMD_BIT (0)
+#define XREG_MVFR0_A_SIMD_MASK (0xF << MVFR0_A_SIMD_BIT)
+
+/* FPEXC bits */
+#define XREG_FPEXC_EX (1 << 31)
+#define XREG_FPEXC_EN (1 << 30)
+#define XREG_FPEXC_DEX (1 << 29)
+
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+
+#endif /* XREG_CORTEXA9_H */
diff --git a/hello_world/sw/app/embeddedsw-master/xstatus.h b/hello_world/sw/app/embeddedsw-master/xstatus.h
new file mode 100644
index 0000000..9acdcf0
--- /dev/null
+++ b/hello_world/sw/app/embeddedsw-master/xstatus.h
@@ -0,0 +1,406 @@
+/******************************************************************************
+* Copyright (C) 2002 - 2020 Xilinx, Inc. All rights reserved.
+* SPDX-License-Identifier: MIT
+******************************************************************************/
+
+/*****************************************************************************/
+/**
+*
+* @file xstatus.h
+* @addtogroup common_v1_1
+* @{
+*
+* This file contains Xilinx software status codes. Status codes have their
+* own data type called int. These codes are used throughout the Xilinx
+* device drivers.
+*
+******************************************************************************/
+
+#ifndef XSTATUS_H /* prevent circular inclusions */
+#define XSTATUS_H /* by using protection macros */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/***************************** Include Files *********************************/
+
+#include "xbasic_types.h"
+
+/************************** Constant Definitions *****************************/
+
+/*********************** Common statuses 0 - 500 *****************************/
+
+#define XST_SUCCESS 0L
+#define XST_FAILURE 1L
+#define XST_DEVICE_NOT_FOUND 2L
+#define XST_DEVICE_BLOCK_NOT_FOUND 3L
+#define XST_INVALID_VERSION 4L
+#define XST_DEVICE_IS_STARTED 5L
+#define XST_DEVICE_IS_STOPPED 6L
+#define XST_FIFO_ERROR 7L /* an error occurred during an
+ operation with a FIFO such as
+ an underrun or overrun, this
+ error requires the device to
+ be reset */
+#define XST_RESET_ERROR 8L /* an error occurred which requires
+ the device to be reset */
+#define XST_DMA_ERROR 9L /* a DMA error occurred, this error
+ typically requires the device
+ using the DMA to be reset */
+#define XST_NOT_POLLED 10L /* the device is not configured for
+ polled mode operation */
+#define XST_FIFO_NO_ROOM 11L /* a FIFO did not have room to put
+ the specified data into */
+#define XST_BUFFER_TOO_SMALL 12L /* the buffer is not large enough
+ to hold the expected data */
+#define XST_NO_DATA 13L /* there was no data available */
+#define XST_REGISTER_ERROR 14L /* a register did not contain the
+ expected value */
+#define XST_INVALID_PARAM 15L /* an invalid parameter was passed
+ into the function */
+#define XST_NOT_SGDMA 16L /* the device is not configured for
+ scatter-gather DMA operation */
+#define XST_LOOPBACK_ERROR 17L /* a loopback test failed */
+#define XST_NO_CALLBACK 18L /* a callback has not yet been
+ registered */
+#define XST_NO_FEATURE 19L /* device is not configured with
+ the requested feature */
+#define XST_NOT_INTERRUPT 20L /* device is not configured for
+ interrupt mode operation */
+#define XST_DEVICE_BUSY 21L /* device is busy */
+#define XST_ERROR_COUNT_MAX 22L /* the error counters of a device
+ have maxed out */
+#define XST_IS_STARTED 23L /* used when part of device is
+ already started i.e.
+ sub channel */
+#define XST_IS_STOPPED 24L /* used when part of device is
+ already stopped i.e.
+ sub channel */
+#define XST_DATA_LOST 26L /* driver defined error */
+#define XST_RECV_ERROR 27L /* generic receive error */
+#define XST_SEND_ERROR 28L /* generic transmit error */
+#define XST_NOT_ENABLED 29L /* a requested service is not
+ available because it has not
+ been enabled */
+
+/***************** Utility Component statuses 401 - 500 *********************/
+
+#define XST_MEMTEST_FAILED 401L /* memory test failed */
+
+
+/***************** Common Components statuses 501 - 1000 *********************/
+
+/********************* Packet Fifo statuses 501 - 510 ************************/
+
+#define XST_PFIFO_LACK_OF_DATA 501L /* not enough data in FIFO */
+#define XST_PFIFO_NO_ROOM 502L /* not enough room in FIFO */
+#define XST_PFIFO_BAD_REG_VALUE 503L /* self test, a register value
+ was invalid after reset */
+#define XST_PFIFO_ERROR 504L /* generic packet FIFO error */
+#define XST_PFIFO_DEADLOCK 505L /* packet FIFO is reporting
+ * empty and full simultaneously
+ */
+
+/************************** DMA statuses 511 - 530 ***************************/
+
+#define XST_DMA_TRANSFER_ERROR 511L /* self test, DMA transfer
+ failed */
+#define XST_DMA_RESET_REGISTER_ERROR 512L /* self test, a register value
+ was invalid after reset */
+#define XST_DMA_SG_LIST_EMPTY 513L /* scatter gather list contains
+ no buffer descriptors ready
+ to be processed */
+#define XST_DMA_SG_IS_STARTED 514L /* scatter gather not stopped */
+#define XST_DMA_SG_IS_STOPPED 515L /* scatter gather not running */
+#define XST_DMA_SG_LIST_FULL 517L /* all the buffer descriptors of
+ the scatter gather list are
+ being used */
+#define XST_DMA_SG_BD_LOCKED 518L /* the scatter gather buffer
+ descriptor which is to be
+ copied over in the scatter
+ list is locked */
+#define XST_DMA_SG_NOTHING_TO_COMMIT 519L /* no buffer descriptors have been
+ put into the scatter gather
+ list to be committed */
+#define XST_DMA_SG_COUNT_EXCEEDED 521L /* the packet count threshold
+ specified was larger than the
+ total # of buffer descriptors
+ in the scatter gather list */
+#define XST_DMA_SG_LIST_EXISTS 522L /* the scatter gather list has
+ already been created */
+#define XST_DMA_SG_NO_LIST 523L /* no scatter gather list has
+ been created */
+#define XST_DMA_SG_BD_NOT_COMMITTED 524L /* the buffer descriptor which was
+ being started was not committed
+ to the list */
+#define XST_DMA_SG_NO_DATA 525L /* the buffer descriptor to start
+ has already been used by the
+ hardware so it can't be reused
+ */
+#define XST_DMA_SG_LIST_ERROR 526L /* general purpose list access
+ error */
+#define XST_DMA_BD_ERROR 527L /* general buffer descriptor
+ error */
+
+/************************** IPIF statuses 531 - 550 ***************************/
+
+#define XST_IPIF_REG_WIDTH_ERROR 531L /* an invalid register width
+ was passed into the function */
+#define XST_IPIF_RESET_REGISTER_ERROR 532L /* the value of a register at
+ reset was not valid */
+#define XST_IPIF_DEVICE_STATUS_ERROR 533L /* a write to the device interrupt
+ status register did not read
+ back correctly */
+#define XST_IPIF_DEVICE_ACK_ERROR 534L /* the device interrupt status
+ register did not reset when
+ acked */
+#define XST_IPIF_DEVICE_ENABLE_ERROR 535L /* the device interrupt enable
+ register was not updated when
+ other registers changed */
+#define XST_IPIF_IP_STATUS_ERROR 536L /* a write to the IP interrupt
+ status register did not read
+ back correctly */
+#define XST_IPIF_IP_ACK_ERROR 537L /* the IP interrupt status register
+ did not reset when acked */
+#define XST_IPIF_IP_ENABLE_ERROR 538L /* IP interrupt enable register was
+ not updated correctly when other
+ registers changed */
+#define XST_IPIF_DEVICE_PENDING_ERROR 539L /* The device interrupt pending
+ register did not indicate the
+ expected value */
+#define XST_IPIF_DEVICE_ID_ERROR 540L /* The device interrupt ID register
+ did not indicate the expected
+ value */
+#define XST_IPIF_ERROR 541L /* generic ipif error */
+
+/****************** Device specific statuses 1001 - 4095 *********************/
+
+/********************* Ethernet statuses 1001 - 1050 *************************/
+
+#define XST_EMAC_MEMORY_SIZE_ERROR 1001L /* Memory space is not big enough
+ * to hold the minimum number of
+ * buffers or descriptors */
+#define XST_EMAC_MEMORY_ALLOC_ERROR 1002L /* Memory allocation failed */
+#define XST_EMAC_MII_READ_ERROR 1003L /* MII read error */
+#define XST_EMAC_MII_BUSY 1004L /* An MII operation is in progress */
+#define XST_EMAC_OUT_OF_BUFFERS 1005L /* Driver is out of buffers */
+#define XST_EMAC_PARSE_ERROR 1006L /* Invalid driver init string */
+#define XST_EMAC_COLLISION_ERROR 1007L /* Excess deferral or late
+ * collision on polled send */
+
+/*********************** UART statuses 1051 - 1075 ***************************/
+#define XST_UART
+
+#define XST_UART_INIT_ERROR 1051L
+#define XST_UART_START_ERROR 1052L
+#define XST_UART_CONFIG_ERROR 1053L
+#define XST_UART_TEST_FAIL 1054L
+#define XST_UART_BAUD_ERROR 1055L
+#define XST_UART_BAUD_RANGE 1056L
+
+
+/************************ IIC statuses 1076 - 1100 ***************************/
+
+#define XST_IIC_SELFTEST_FAILED 1076 /* self test failed */
+#define XST_IIC_BUS_BUSY 1077 /* bus found busy */
+#define XST_IIC_GENERAL_CALL_ADDRESS 1078 /* mastersend attempted with */
+ /* general call address */
+#define XST_IIC_STAND_REG_RESET_ERROR 1079 /* A non parameterizable reg */
+ /* value after reset not valid */
+#define XST_IIC_TX_FIFO_REG_RESET_ERROR 1080 /* Tx fifo included in design */
+ /* value after reset not valid */
+#define XST_IIC_RX_FIFO_REG_RESET_ERROR 1081 /* Rx fifo included in design */
+ /* value after reset not valid */
+#define XST_IIC_TBA_REG_RESET_ERROR 1082 /* 10 bit addr incl in design */
+ /* value after reset not valid */
+#define XST_IIC_CR_READBACK_ERROR 1083 /* Read of the control register */
+ /* didn't return value written */
+#define XST_IIC_DTR_READBACK_ERROR 1084 /* Read of the data Tx reg */
+ /* didn't return value written */
+#define XST_IIC_DRR_READBACK_ERROR 1085 /* Read of the data Receive reg */
+ /* didn't return value written */
+#define XST_IIC_ADR_READBACK_ERROR 1086 /* Read of the data Tx reg */
+ /* didn't return value written */
+#define XST_IIC_TBA_READBACK_ERROR 1087 /* Read of the 10 bit addr reg */
+ /* didn't return written value */
+#define XST_IIC_NOT_SLAVE 1088 /* The device isn't a slave */
+
+/*********************** ATMC statuses 1101 - 1125 ***************************/
+
+#define XST_ATMC_ERROR_COUNT_MAX 1101L /* the error counters in the ATM
+ controller hit the max value
+ which requires the statistics
+ to be cleared */
+
+/*********************** Flash statuses 1126 - 1150 **************************/
+
+#define XST_FLASH_BUSY 1126L /* Flash is erasing or programming
+ */
+#define XST_FLASH_READY 1127L /* Flash is ready for commands */
+#define XST_FLASH_ERROR 1128L /* Flash had detected an internal
+ error. Use XFlash_DeviceControl
+ to retrieve device specific codes
+ */
+#define XST_FLASH_ERASE_SUSPENDED 1129L /* Flash is in suspended erase state
+ */
+#define XST_FLASH_WRITE_SUSPENDED 1130L /* Flash is in suspended write state
+ */
+#define XST_FLASH_PART_NOT_SUPPORTED 1131L /* Flash type not supported by
+ driver */
+#define XST_FLASH_NOT_SUPPORTED 1132L /* Operation not supported */
+#define XST_FLASH_TOO_MANY_REGIONS 1133L /* Too many erase regions */
+#define XST_FLASH_TIMEOUT_ERROR 1134L /* Programming or erase operation
+ aborted due to a timeout */
+#define XST_FLASH_ADDRESS_ERROR 1135L /* Accessed flash outside its
+ addressible range */
+#define XST_FLASH_ALIGNMENT_ERROR 1136L /* Write alignment error */
+#define XST_FLASH_BLOCKING_CALL_ERROR 1137L /* Couldn't return immediately from
+ write/erase function with
+ XFL_NON_BLOCKING_WRITE/ERASE
+ option cleared */
+#define XST_FLASH_CFI_QUERY_ERROR 1138L /* Failed to query the device */
+
+/*********************** SPI statuses 1151 - 1175 ****************************/
+
+#define XST_SPI_MODE_FAULT 1151 /* master was selected as slave */
+#define XST_SPI_TRANSFER_DONE 1152 /* data transfer is complete */
+#define XST_SPI_TRANSMIT_UNDERRUN 1153 /* slave underruns transmit register */
+#define XST_SPI_RECEIVE_OVERRUN 1154 /* device overruns receive register */
+#define XST_SPI_NO_SLAVE 1155 /* no slave has been selected yet */
+#define XST_SPI_TOO_MANY_SLAVES 1156 /* more than one slave is being
+ * selected */
+#define XST_SPI_NOT_MASTER 1157 /* operation is valid only as master */
+#define XST_SPI_SLAVE_ONLY 1158 /* device is configured as slave-only
+ */
+#define XST_SPI_SLAVE_MODE_FAULT 1159 /* slave was selected while disabled */
+#define XST_SPI_SLAVE_MODE 1160 /* device has been addressed as slave */
+#define XST_SPI_RECEIVE_NOT_EMPTY 1161 /* device received data in slave mode */
+
+#define XST_SPI_COMMAND_ERROR 1162 /* unrecognised command - qspi only */
+
+/********************** OPB Arbiter statuses 1176 - 1200 *********************/
+
+#define XST_OPBARB_INVALID_PRIORITY 1176 /* the priority registers have either
+ * one master assigned to two or more
+ * priorities, or one master not
+ * assigned to any priority
+ */
+#define XST_OPBARB_NOT_SUSPENDED 1177 /* an attempt was made to modify the
+ * priority levels without first
+ * suspending the use of priority
+ * levels
+ */
+#define XST_OPBARB_PARK_NOT_ENABLED 1178 /* bus parking by id was enabled but
+ * bus parking was not enabled
+ */
+#define XST_OPBARB_NOT_FIXED_PRIORITY 1179 /* the arbiter must be in fixed
+ * priority mode to allow the
+ * priorities to be changed
+ */
+
+/************************ Intc statuses 1201 - 1225 **************************/
+
+#define XST_INTC_FAIL_SELFTEST 1201 /* self test failed */
+#define XST_INTC_CONNECT_ERROR 1202 /* interrupt already in use */
+
+/********************** TmrCtr statuses 1226 - 1250 **************************/
+
+#define XST_TMRCTR_TIMER_FAILED 1226 /* self test failed */
+
+/********************** WdtTb statuses 1251 - 1275 ***************************/
+
+#define XST_WDTTB_TIMER_FAILED 1251L
+
+/********************** PlbArb statuses 1276 - 1300 **************************/
+
+#define XST_PLBARB_FAIL_SELFTEST 1276L
+
+/********************** Plb2Opb statuses 1301 - 1325 *************************/
+
+#define XST_PLB2OPB_FAIL_SELFTEST 1301L
+
+/********************** Opb2Plb statuses 1326 - 1350 *************************/
+
+#define XST_OPB2PLB_FAIL_SELFTEST 1326L
+
+/********************** SysAce statuses 1351 - 1360 **************************/
+
+#define XST_SYSACE_NO_LOCK 1351L /* No MPU lock has been granted */
+
+/********************** PCI Bridge statuses 1361 - 1375 **********************/
+
+#define XST_PCI_INVALID_ADDRESS 1361L
+
+/********************** FlexRay constants 1400 - 1409 *************************/
+
+#define XST_FR_TX_ERROR 1400
+#define XST_FR_TX_BUSY 1401
+#define XST_FR_BUF_LOCKED 1402
+#define XST_FR_NO_BUF 1403
+
+/****************** USB constants 1410 - 1420 *******************************/
+
+#define XST_USB_ALREADY_CONFIGURED 1410
+#define XST_USB_BUF_ALIGN_ERROR 1411
+#define XST_USB_NO_DESC_AVAILABLE 1412
+#define XST_USB_BUF_TOO_BIG 1413
+#define XST_USB_NO_BUF 1414
+
+/****************** HWICAP constants 1421 - 1429 *****************************/
+
+#define XST_HWICAP_WRITE_DONE 1421
+
+
+/****************** AXI VDMA constants 1430 - 1440 *****************************/
+
+#define XST_VDMA_MISMATCH_ERROR 1430
+
+/*********************** NAND Flash statuses 1441 - 1459 *********************/
+
+#define XST_NAND_BUSY 1441L /* Flash is erasing or
+ * programming
+ */
+#define XST_NAND_READY 1442L /* Flash is ready for commands
+ */
+#define XST_NAND_ERROR 1443L /* Flash had detected an
+ * internal error.
+ */
+#define XST_NAND_PART_NOT_SUPPORTED 1444L /* Flash type not supported by
+ * driver
+ */
+#define XST_NAND_OPT_NOT_SUPPORTED 1445L /* Operation not supported
+ */
+#define XST_NAND_TIMEOUT_ERROR 1446L /* Programming or erase
+ * operation aborted due to a
+ * timeout
+ */
+#define XST_NAND_ADDRESS_ERROR 1447L /* Accessed flash outside its
+ * addressible range
+ */
+#define XST_NAND_ALIGNMENT_ERROR 1448L /* Write alignment error
+ */
+#define XST_NAND_PARAM_PAGE_ERROR 1449L /* Failed to read parameter
+ * page of the device
+ */
+#define XST_NAND_CACHE_ERROR 1450L /* Flash page buffer error
+ */
+
+#define XST_NAND_WRITE_PROTECTED 1451L /* Flash is write protected
+ */
+
+/**************************** Type Definitions *******************************/
+
+typedef int XStatus;
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+
+/************************** Function Prototypes ******************************/
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* end of protection macro */
+/** @} */
diff --git a/hello_world/sw/app/embeddedsw-master/xuartps_hw.c b/hello_world/sw/app/embeddedsw-master/xuartps_hw.c
new file mode 100644
index 0000000..7639afa
--- /dev/null
+++ b/hello_world/sw/app/embeddedsw-master/xuartps_hw.c
@@ -0,0 +1,154 @@
+/******************************************************************************
+* Copyright (C) 2010 - 2020 Xilinx, Inc. All rights reserved.
+* SPDX-License-Identifier: MIT
+******************************************************************************/
+
+/****************************************************************************/
+/**
+*
+* @file xuartps_hw.c
+* @addtogroup uartps_v3_10
+* @{
+*
+*
+* <pre>
+* MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ----- ------ -------- ----------------------------------------------
+* 1.00 drg/jz 01/12/10 First Release
+* 1.05a hk 08/22/13 Added reset function
+* 3.00 kvn 02/13/15 Modified code for MISRA-C:2012 compliance.
+* </pre>
+*
+*****************************************************************************/
+
+/***************************** Include Files ********************************/
+#include "xuartps_hw.h"
+
+/************************** Constant Definitions ****************************/
+
+
+/***************** Macros (Inline Functions) Definitions ********************/
+
+
+/************************** Function Prototypes ******************************/
+
+
+/************************** Variable Definitions *****************************/
+
+/****************************************************************************/
+/**
+*
+* This function sends one byte using the device. This function operates in
+* polled mode and blocks until the data has been put into the TX FIFO register.
+*
+* @param BaseAddress contains the base address of the device.
+* @param Data contains the byte to be sent.
+*
+* @return None.
+*
+* @note None.
+*
+*****************************************************************************/
+void XUartPs_SendByte(u32 BaseAddress, u8 Data)
+{
+ /* Wait until there is space in TX FIFO */
+ while (XUartPs_IsTransmitFull(BaseAddress)) {
+ ;
+ }
+
+ /* Write the byte into the TX FIFO */
+ XUartPs_WriteReg(BaseAddress, XUARTPS_FIFO_OFFSET, (u32)Data);
+}
+
+/****************************************************************************/
+/**
+*
+* This function receives a byte from the device. It operates in polled mode
+* and blocks until a byte has received.
+*
+* @param BaseAddress contains the base address of the device.
+*
+* @return The data byte received.
+*
+* @note None.
+*
+*****************************************************************************/
+u8 XUartPs_RecvByte(u32 BaseAddress)
+{
+ u32 RecievedByte;
+ /* Wait until there is data */
+ while (!XUartPs_IsReceiveData(BaseAddress)) {
+ ;
+ }
+ RecievedByte = XUartPs_ReadReg(BaseAddress, XUARTPS_FIFO_OFFSET);
+ /* Return the byte received */
+ return (u8)RecievedByte;
+}
+
+/****************************************************************************/
+/**
+*
+* This function resets UART
+*
+* @param BaseAddress contains the base address of the device.
+*
+* @return None
+*
+* @note None.
+*
+*****************************************************************************/
+void XUartPs_ResetHw(u32 BaseAddress)
+{
+
+ /* Disable interrupts */
+ XUartPs_WriteReg(BaseAddress, XUARTPS_IDR_OFFSET, XUARTPS_IXR_MASK);
+
+ /* Disable receive and transmit */
+ XUartPs_WriteReg(BaseAddress, XUARTPS_CR_OFFSET,
+ ((u32)XUARTPS_CR_RX_DIS | (u32)XUARTPS_CR_TX_DIS));
+
+ /*
+ * Software reset of receive and transmit
+ * This clears the FIFO.
+ */
+ XUartPs_WriteReg(BaseAddress, XUARTPS_CR_OFFSET,
+ ((u32)XUARTPS_CR_TXRST | (u32)XUARTPS_CR_RXRST));
+
+ /* Clear status flags - SW reset wont clear sticky flags. */
+ XUartPs_WriteReg(BaseAddress, XUARTPS_ISR_OFFSET, XUARTPS_IXR_MASK);
+
+ /*
+ * Mode register reset value : All zeroes
+ * Normal mode, even parity, 1 stop bit
+ */
+ XUartPs_WriteReg(BaseAddress, XUARTPS_MR_OFFSET,
+ XUARTPS_MR_CHMODE_NORM);
+
+ /* Rx and TX trigger register reset values */
+ XUartPs_WriteReg(BaseAddress, XUARTPS_RXWM_OFFSET,
+ XUARTPS_RXWM_RESET_VAL);
+ XUartPs_WriteReg(BaseAddress, XUARTPS_TXWM_OFFSET,
+ XUARTPS_TXWM_RESET_VAL);
+
+ /* Rx timeout disabled by default */
+ XUartPs_WriteReg(BaseAddress, XUARTPS_RXTOUT_OFFSET,
+ XUARTPS_RXTOUT_DISABLE);
+
+ /* Baud rate generator and dividor reset values */
+ XUartPs_WriteReg(BaseAddress, XUARTPS_BAUDGEN_OFFSET,
+ XUARTPS_BAUDGEN_RESET_VAL);
+ XUartPs_WriteReg(BaseAddress, XUARTPS_BAUDDIV_OFFSET,
+ XUARTPS_BAUDDIV_RESET_VAL);
+
+ /*
+ * Control register reset value -
+ * RX and TX are disable by default
+ */
+ XUartPs_WriteReg(BaseAddress, XUARTPS_CR_OFFSET,
+ ((u32)XUARTPS_CR_RX_DIS | (u32)XUARTPS_CR_TX_DIS |
+ (u32)XUARTPS_CR_STOPBRK));
+
+}
+/** @} */
diff --git a/hello_world/sw/app/embeddedsw-master/xuartps_hw.h b/hello_world/sw/app/embeddedsw-master/xuartps_hw.h
new file mode 100644
index 0000000..6d38311
--- /dev/null
+++ b/hello_world/sw/app/embeddedsw-master/xuartps_hw.h
@@ -0,0 +1,425 @@
+/******************************************************************************
+* Copyright (C) 2010 - 2020 Xilinx, Inc. All rights reserved.
+* SPDX-License-Identifier: MIT
+******************************************************************************/
+
+/*****************************************************************************/
+/**
+*
+* @file xuartps_hw.h
+* @addtogroup uartps_v3_10
+* @{
+*
+* This header file contains the hardware interface of an XUartPs device.
+*
+* <pre>
+* MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ----- ------ -------- ----------------------------------------------
+* 1.00 drg/jz 01/12/10 First Release
+* 1.03a sg 09/04/12 Added defines for XUARTPS_IXR_TOVR, XUARTPS_IXR_TNFUL
+* and XUARTPS_IXR_TTRIG.
+* Modified the names of these defines
+* XUARTPS_MEDEMSR_DCDX to XUARTPS_MODEMSR_DDCD
+* XUARTPS_MEDEMSR_RIX to XUARTPS_MODEMSR_TERI
+* XUARTPS_MEDEMSR_DSRX to XUARTPS_MODEMSR_DDSR
+* XUARTPS_MEDEMSR_CTSX to XUARTPS_MODEMSR_DCTS
+* 1.05a hk 08/22/13 Added prototype for uart reset and related
+* constant definitions.
+* 3.00 kvn 02/13/15 Modified code for MISRA-C:2012 compliance.
+* 3.1 kvn 04/10/15 Modified code for latest RTL changes.
+* 3.6 ms 02/16/18 Updates flow control mode offset value in
+* modem control register.
+*
+* </pre>
+*
+******************************************************************************/
+#ifndef XUARTPS_HW_H /* prevent circular inclusions */
+#define XUARTPS_HW_H /* by using protection macros */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/***************************** Include Files *********************************/
+
+#include "xil_types.h"
+#include "xil_assert.h"
+#include "xil_io.h"
+
+/************************** Constant Definitions *****************************/
+
+/** @name Register Map
+ *
+ * Register offsets for the UART.
+ * @{
+ */
+#define XUARTPS_CR_OFFSET 0x0000U /**< Control Register [8:0] */
+#define XUARTPS_MR_OFFSET 0x0004U /**< Mode Register [9:0] */
+#define XUARTPS_IER_OFFSET 0x0008U /**< Interrupt Enable [12:0] */
+#define XUARTPS_IDR_OFFSET 0x000CU /**< Interrupt Disable [12:0] */
+#define XUARTPS_IMR_OFFSET 0x0010U /**< Interrupt Mask [12:0] */
+#define XUARTPS_ISR_OFFSET 0x0014U /**< Interrupt Status [12:0]*/
+#define XUARTPS_BAUDGEN_OFFSET 0x0018U /**< Baud Rate Generator [15:0] */
+#define XUARTPS_RXTOUT_OFFSET 0x001CU /**< RX Timeout [7:0] */
+#define XUARTPS_RXWM_OFFSET 0x0020U /**< RX FIFO Trigger Level [5:0] */
+#define XUARTPS_MODEMCR_OFFSET 0x0024U /**< Modem Control [5:0] */
+#define XUARTPS_MODEMSR_OFFSET 0x0028U /**< Modem Status [8:0] */
+#define XUARTPS_SR_OFFSET 0x002CU /**< Channel Status [14:0] */
+#define XUARTPS_FIFO_OFFSET 0x0030U /**< FIFO [7:0] */
+#define XUARTPS_BAUDDIV_OFFSET 0x0034U /**< Baud Rate Divider [7:0] */
+#define XUARTPS_FLOWDEL_OFFSET 0x0038U /**< Flow Delay [5:0] */
+#define XUARTPS_TXWM_OFFSET 0x0044U /**< TX FIFO Trigger Level [5:0] */
+#define XUARTPS_RXBS_OFFSET 0x0048U /**< RX FIFO Byte Status [11:0] */
+/* @} */
+
+/** @name Control Register
+ *
+ * The Control register (CR) controls the major functions of the device.
+ *
+ * Control Register Bit Definition
+ */
+
+#define XUARTPS_CR_STOPBRK 0x00000100U /**< Stop transmission of break */
+#define XUARTPS_CR_STARTBRK 0x00000080U /**< Set break */
+#define XUARTPS_CR_TORST 0x00000040U /**< RX timeout counter restart */
+#define XUARTPS_CR_TX_DIS 0x00000020U /**< TX disabled. */
+#define XUARTPS_CR_TX_EN 0x00000010U /**< TX enabled */
+#define XUARTPS_CR_RX_DIS 0x00000008U /**< RX disabled. */
+#define XUARTPS_CR_RX_EN 0x00000004U /**< RX enabled */
+#define XUARTPS_CR_EN_DIS_MASK 0x0000003CU /**< Enable/disable Mask */
+#define XUARTPS_CR_TXRST 0x00000002U /**< TX logic reset */
+#define XUARTPS_CR_RXRST 0x00000001U /**< RX logic reset */
+/* @}*/
+
+
+/** @name Mode Register
+ *
+ * The mode register (MR) defines the mode of transfer as well as the data
+ * format. If this register is modified during transmission or reception,
+ * data validity cannot be guaranteed.
+ *
+ * Mode Register Bit Definition
+ * @{
+ */
+#define XUARTPS_MR_CCLK 0x00000400U /**< Input clock selection */
+#define XUARTPS_MR_CHMODE_R_LOOP 0x00000300U /**< Remote loopback mode */
+#define XUARTPS_MR_CHMODE_L_LOOP 0x00000200U /**< Local loopback mode */
+#define XUARTPS_MR_CHMODE_ECHO 0x00000100U /**< Auto echo mode */
+#define XUARTPS_MR_CHMODE_NORM 0x00000000U /**< Normal mode */
+#define XUARTPS_MR_CHMODE_SHIFT 8U /**< Mode shift */
+#define XUARTPS_MR_CHMODE_MASK 0x00000300U /**< Mode mask */
+#define XUARTPS_MR_STOPMODE_2_BIT 0x00000080U /**< 2 stop bits */
+#define XUARTPS_MR_STOPMODE_1_5_BIT 0x00000040U /**< 1.5 stop bits */
+#define XUARTPS_MR_STOPMODE_1_BIT 0x00000000U /**< 1 stop bit */
+#define XUARTPS_MR_STOPMODE_SHIFT 6U /**< Stop bits shift */
+#define XUARTPS_MR_STOPMODE_MASK 0x000000A0U /**< Stop bits mask */
+#define XUARTPS_MR_PARITY_NONE 0x00000020U /**< No parity mode */
+#define XUARTPS_MR_PARITY_MARK 0x00000018U /**< Mark parity mode */
+#define XUARTPS_MR_PARITY_SPACE 0x00000010U /**< Space parity mode */
+#define XUARTPS_MR_PARITY_ODD 0x00000008U /**< Odd parity mode */
+#define XUARTPS_MR_PARITY_EVEN 0x00000000U /**< Even parity mode */
+#define XUARTPS_MR_PARITY_SHIFT 3U /**< Parity setting shift */
+#define XUARTPS_MR_PARITY_MASK 0x00000038U /**< Parity mask */
+#define XUARTPS_MR_CHARLEN_6_BIT 0x00000006U /**< 6 bits data */
+#define XUARTPS_MR_CHARLEN_7_BIT 0x00000004U /**< 7 bits data */
+#define XUARTPS_MR_CHARLEN_8_BIT 0x00000000U /**< 8 bits data */
+#define XUARTPS_MR_CHARLEN_SHIFT 1U /**< Data Length shift */
+#define XUARTPS_MR_CHARLEN_MASK 0x00000006U /**< Data length mask */
+#define XUARTPS_MR_CLKSEL 0x00000001U /**< Input clock selection */
+/* @} */
+
+
+/** @name Interrupt Registers
+ *
+ * Interrupt control logic uses the interrupt enable register (IER) and the
+ * interrupt disable register (IDR) to set the value of the bits in the
+ * interrupt mask register (IMR). The IMR determines whether to pass an
+ * interrupt to the interrupt status register (ISR).
+ * Writing a 1 to IER Enbables an interrupt, writing a 1 to IDR disables an
+ * interrupt. IMR and ISR are read only, and IER and IDR are write only.
+ * Reading either IER or IDR returns 0x00.
+ *
+ * All four registers have the same bit definitions.
+ *
+ * @{
+ */
+#define XUARTPS_IXR_RBRK 0x00002000U /**< Rx FIFO break detect interrupt */
+#define XUARTPS_IXR_TOVR 0x00001000U /**< Tx FIFO Overflow interrupt */
+#define XUARTPS_IXR_TNFUL 0x00000800U /**< Tx FIFO Nearly Full interrupt */
+#define XUARTPS_IXR_TTRIG 0x00000400U /**< Tx Trig interrupt */
+#define XUARTPS_IXR_DMS 0x00000200U /**< Modem status change interrupt */
+#define XUARTPS_IXR_TOUT 0x00000100U /**< Timeout error interrupt */
+#define XUARTPS_IXR_PARITY 0x00000080U /**< Parity error interrupt */
+#define XUARTPS_IXR_FRAMING 0x00000040U /**< Framing error interrupt */
+#define XUARTPS_IXR_OVER 0x00000020U /**< Overrun error interrupt */
+#define XUARTPS_IXR_TXFULL 0x00000010U /**< TX FIFO full interrupt. */
+#define XUARTPS_IXR_TXEMPTY 0x00000008U /**< TX FIFO empty interrupt. */
+#define XUARTPS_IXR_RXFULL 0x00000004U /**< RX FIFO full interrupt. */
+#define XUARTPS_IXR_RXEMPTY 0x00000002U /**< RX FIFO empty interrupt. */
+#define XUARTPS_IXR_RXOVR 0x00000001U /**< RX FIFO trigger interrupt. */
+#define XUARTPS_IXR_MASK 0x00003FFFU /**< Valid bit mask */
+/* @} */
+
+
+/** @name Baud Rate Generator Register
+ *
+ * The baud rate generator control register (BRGR) is a 16 bit register that
+ * controls the receiver bit sample clock and baud rate.
+ * Valid values are 1 - 65535.
+ *
+ * Bit Sample Rate = CCLK / BRGR, where the CCLK is selected by the MR_CCLK bit
+ * in the MR register.
+ * @{
+ */
+#define XUARTPS_BAUDGEN_DISABLE 0x00000000U /**< Disable clock */
+#define XUARTPS_BAUDGEN_MASK 0x0000FFFFU /**< Valid bits mask */
+#define XUARTPS_BAUDGEN_RESET_VAL 0x0000028BU /**< Reset value */
+
+/** @name Baud Divisor Rate register
+ *
+ * The baud rate divider register (BDIV) controls how much the bit sample
+ * rate is divided by. It sets the baud rate.
+ * Valid values are 0x04 to 0xFF. Writing a value less than 4 will be ignored.
+ *
+ * Baud rate = CCLK / ((BAUDDIV + 1) x BRGR), where the CCLK is selected by
+ * the MR_CCLK bit in the MR register.
+ * @{
+ */
+#define XUARTPS_BAUDDIV_MASK 0x000000FFU /**< 8 bit baud divider mask */
+#define XUARTPS_BAUDDIV_RESET_VAL 0x0000000FU /**< Reset value */
+/* @} */
+
+
+/** @name Receiver Timeout Register
+ *
+ * Use the receiver timeout register (RTR) to detect an idle condition on
+ * the receiver data line.
+ *
+ * @{
+ */
+#define XUARTPS_RXTOUT_DISABLE 0x00000000U /**< Disable time out */
+#define XUARTPS_RXTOUT_MASK 0x000000FFU /**< Valid bits mask */
+
+/** @name Receiver FIFO Trigger Level Register
+ *
+ * Use the Receiver FIFO Trigger Level Register (RTRIG) to set the value at
+ * which the RX FIFO triggers an interrupt event.
+ * @{
+ */
+
+#define XUARTPS_RXWM_DISABLE 0x00000000U /**< Disable RX trigger interrupt */
+#define XUARTPS_RXWM_MASK 0x0000003FU /**< Valid bits mask */
+#define XUARTPS_RXWM_RESET_VAL 0x00000020U /**< Reset value */
+/* @} */
+
+/** @name Transmit FIFO Trigger Level Register
+ *
+ * Use the Transmit FIFO Trigger Level Register (TTRIG) to set the value at
+ * which the TX FIFO triggers an interrupt event.
+ * @{
+ */
+
+#define XUARTPS_TXWM_MASK 0x0000003FU /**< Valid bits mask */
+#define XUARTPS_TXWM_RESET_VAL 0x00000020U /**< Reset value */
+/* @} */
+
+/** @name Modem Control Register
+ *
+ * This register (MODEMCR) controls the interface with the modem or data set,
+ * or a peripheral device emulating a modem.
+ *
+ * @{
+ */
+#define XUARTPS_MODEMCR_FCM 0x00000020U /**< Flow control mode */
+#define XUARTPS_MODEMCR_RTS 0x00000002U /**< Request to send */
+#define XUARTPS_MODEMCR_DTR 0x00000001U /**< Data terminal ready */
+/* @} */
+
+/** @name Modem Status Register
+ *
+ * This register (MODEMSR) indicates the current state of the control lines
+ * from a modem, or another peripheral device, to the CPU. In addition, four
+ * bits of the modem status register provide change information. These bits
+ * are set to a logic 1 whenever a control input from the modem changes state.
+ *
+ * Note: Whenever the DCTS, DDSR, TERI, or DDCD bit is set to logic 1, a modem
+ * status interrupt is generated and this is reflected in the modem status
+ * register.
+ *
+ * @{
+ */
+#define XUARTPS_MODEMSR_FCMS 0x00000100U /**< Flow control mode (FCMS) */
+#define XUARTPS_MODEMSR_DCD 0x00000080U /**< Complement of DCD input */
+#define XUARTPS_MODEMSR_RI 0x00000040U /**< Complement of RI input */
+#define XUARTPS_MODEMSR_DSR 0x00000020U /**< Complement of DSR input */
+#define XUARTPS_MODEMSR_CTS 0x00000010U /**< Complement of CTS input */
+#define XUARTPS_MODEMSR_DDCD 0x00000008U /**< Delta DCD indicator */
+#define XUARTPS_MODEMSR_TERI 0x00000004U /**< Trailing Edge Ring Indicator */
+#define XUARTPS_MODEMSR_DDSR 0x00000002U /**< Change of DSR */
+#define XUARTPS_MODEMSR_DCTS 0x00000001U /**< Change of CTS */
+/* @} */
+
+/** @name Channel Status Register
+ *
+ * The channel status register (CSR) is provided to enable the control logic
+ * to monitor the status of bits in the channel interrupt status register,
+ * even if these are masked out by the interrupt mask register.
+ *
+ * @{
+ */
+#define XUARTPS_SR_TNFUL 0x00004000U /**< TX FIFO Nearly Full Status */
+#define XUARTPS_SR_TTRIG 0x00002000U /**< TX FIFO Trigger Status */
+#define XUARTPS_SR_FLOWDEL 0x00001000U /**< RX FIFO fill over flow delay */
+#define XUARTPS_SR_TACTIVE 0x00000800U /**< TX active */
+#define XUARTPS_SR_RACTIVE 0x00000400U /**< RX active */
+#define XUARTPS_SR_TXFULL 0x00000010U /**< TX FIFO full */
+#define XUARTPS_SR_TXEMPTY 0x00000008U /**< TX FIFO empty */
+#define XUARTPS_SR_RXFULL 0x00000004U /**< RX FIFO full */
+#define XUARTPS_SR_RXEMPTY 0x00000002U /**< RX FIFO empty */
+#define XUARTPS_SR_RXOVR 0x00000001U /**< RX FIFO fill over trigger */
+/* @} */
+
+/** @name Flow Delay Register
+ *
+ * Operation of the flow delay register (FLOWDEL) is very similar to the
+ * receive FIFO trigger register. An internal trigger signal activates when the
+ * FIFO is filled to the level set by this register. This trigger will not
+ * cause an interrupt, although it can be read through the channel status
+ * register. In hardware flow control mode, RTS is deactivated when the trigger
+ * becomes active. RTS only resets when the FIFO level is four less than the
+ * level of the flow delay trigger and the flow delay trigger is not activated.
+ * A value less than 4 disables the flow delay.
+ * @{
+ */
+#define XUARTPS_FLOWDEL_MASK XUARTPS_RXWM_MASK /**< Valid bit mask */
+/* @} */
+
+/** @name Receiver FIFO Byte Status Register
+ *
+ * The Receiver FIFO Status register is used to have a continuous
+ * monitoring of the raw unmasked byte status information. The register
+ * contains frame, parity and break status information for the top
+ * four bytes in the RX FIFO.
+ *
+ * Receiver FIFO Byte Status Register Bit Definition
+ * @{
+ */
+#define XUARTPS_RXBS_BYTE3_BRKE 0x00000800U /**< Byte3 Break Error */
+#define XUARTPS_RXBS_BYTE3_FRME 0x00000400U /**< Byte3 Frame Error */
+#define XUARTPS_RXBS_BYTE3_PARE 0x00000200U /**< Byte3 Parity Error */
+#define XUARTPS_RXBS_BYTE2_BRKE 0x00000100U /**< Byte2 Break Error */
+#define XUARTPS_RXBS_BYTE2_FRME 0x00000080U /**< Byte2 Frame Error */
+#define XUARTPS_RXBS_BYTE2_PARE 0x00000040U /**< Byte2 Parity Error */
+#define XUARTPS_RXBS_BYTE1_BRKE 0x00000020U /**< Byte1 Break Error */
+#define XUARTPS_RXBS_BYTE1_FRME 0x00000010U /**< Byte1 Frame Error */
+#define XUARTPS_RXBS_BYTE1_PARE 0x00000008U /**< Byte1 Parity Error */
+#define XUARTPS_RXBS_BYTE0_BRKE 0x00000004U /**< Byte0 Break Error */
+#define XUARTPS_RXBS_BYTE0_FRME 0x00000002U /**< Byte0 Frame Error */
+#define XUARTPS_RXBS_BYTE0_PARE 0x00000001U /**< Byte0 Parity Error */
+#define XUARTPS_RXBS_MASK 0x00000007U /**< 3 bit RX byte status mask */
+/* @} */
+
+
+/*
+ * Defines for backwards compatibility, will be removed
+ * in the next version of the driver
+ */
+#define XUARTPS_MEDEMSR_DCDX XUARTPS_MODEMSR_DDCD
+#define XUARTPS_MEDEMSR_RIX XUARTPS_MODEMSR_TERI
+#define XUARTPS_MEDEMSR_DSRX XUARTPS_MODEMSR_DDSR
+#define XUARTPS_MEDEMSR_CTSX XUARTPS_MODEMSR_DCTS
+
+
+
+/**************************** Type Definitions *******************************/
+
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/****************************************************************************/
+/**
+* Read a UART register.
+*
+* @param BaseAddress contains the base address of the device.
+* @param RegOffset contains the offset from the base address of the
+* device.
+*
+* @return The value read from the register.
+*
+* @note C-Style signature:
+* u32 XUartPs_ReadReg(u32 BaseAddress, int RegOffset)
+*
+******************************************************************************/
+#define XUartPs_ReadReg(BaseAddress, RegOffset) \
+ Xil_In32((BaseAddress) + (u32)(RegOffset))
+
+/***************************************************************************/
+/**
+* Write a UART register.
+*
+* @param BaseAddress contains the base address of the device.
+* @param RegOffset contains the offset from the base address of the
+* device.
+* @param RegisterValue is the value to be written to the register.
+*
+* @return None.
+*
+* @note C-Style signature:
+* void XUartPs_WriteReg(u32 BaseAddress, int RegOffset,
+* u16 RegisterValue)
+*
+******************************************************************************/
+#define XUartPs_WriteReg(BaseAddress, RegOffset, RegisterValue) \
+ Xil_Out32((BaseAddress) + (u32)(RegOffset), (u32)(RegisterValue))
+
+/****************************************************************************/
+/**
+* Determine if there is receive data in the receiver and/or FIFO.
+*
+* @param BaseAddress contains the base address of the device.
+*
+* @return TRUE if there is receive data, FALSE otherwise.
+*
+* @note C-Style signature:
+* u32 XUartPs_IsReceiveData(u32 BaseAddress)
+*
+******************************************************************************/
+#define XUartPs_IsReceiveData(BaseAddress) \
+ !((Xil_In32((BaseAddress) + XUARTPS_SR_OFFSET) & \
+ (u32)XUARTPS_SR_RXEMPTY) == (u32)XUARTPS_SR_RXEMPTY)
+
+/****************************************************************************/
+/**
+* Determine if a byte of data can be sent with the transmitter.
+*
+* @param BaseAddress contains the base address of the device.
+*
+* @return TRUE if the TX FIFO is full, FALSE if a byte can be put in the
+* FIFO.
+*
+* @note C-Style signature:
+* u32 XUartPs_IsTransmitFull(u32 BaseAddress)
+*
+******************************************************************************/
+#define XUartPs_IsTransmitFull(BaseAddress) \
+ ((Xil_In32((BaseAddress) + XUARTPS_SR_OFFSET) & \
+ (u32)XUARTPS_SR_TXFULL) == (u32)XUARTPS_SR_TXFULL)
+
+/************************** Function Prototypes ******************************/
+
+void XUartPs_SendByte(u32 BaseAddress, u8 Data);
+
+u8 XUartPs_RecvByte(u32 BaseAddress);
+
+void XUartPs_ResetHw(u32 BaseAddress);
+
+/************************** Variable Definitions *****************************/
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* end of protection macro */
+/** @} */
diff --git a/hello_world/sw/app/gpio.c b/hello_world/sw/app/gpio.c
new file mode 100644
index 0000000..ccdf7d0
--- /dev/null
+++ b/hello_world/sw/app/gpio.c
@@ -0,0 +1,165 @@
+
+/*
+ Copyright (C) 2021 Jonathan Certes
+
+ This program is free software: you can redistribute it and/or modify it under
+ the terms of the GNU General Public License as published by the Free Software
+ Foundation, either version 3 of the License, or (at your option) any later
+ version.
+
+ This program is distributed in the hope that it will be useful, but WITHOUT
+ ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS
+ FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details.
+
+ You should have received a copy of the GNU General Public License along with
+ this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include "gpio.h"
+
+/******************************************************************************/
+
+/**
+ * \brief
+ * Updates two <tt> uint8_t </tt>, which addresses are given as arguments, to
+ * be both the bank index and the bit index for a given GPIO.
+ *
+ * \details
+ * The appropriate bank is deduced from the GPIO index:
+ * - Bank0, 32-bit bank controlling MIO pins[31:0] : indexes from 0 to 31
+ * - Bank1, 22-bit bank controlling MIO pins[53:32] : indexes from 32 to 53
+ * - Bank2, 32-bit bank controlling EMIO signals[31:0] : indexes from 54 to 85
+ * - Bank3, 32-bit bank controlling EMIO signals[63:32] : indexes from 86 to 117
+ */
+void gpio_getBankAndBitIndex(
+ uint8_t theGpioIndex, //!< integer that refers to a GPIO pin index
+ uint8_t * theBank, //!< address of the bank index to update
+ uint8_t * theBitIndex //!< address of the bit index to update
+) {
+ if ( theGpioIndex < 32 ) {
+ *theBank = 0;
+ *theBitIndex = theGpioIndex;
+ } else if ( theGpioIndex < 54 ) {
+ *theBank = 1;
+ *theBitIndex = theGpioIndex - 32;
+ } else if ( theGpioIndex < 86 ) {
+ *theBank = 2;
+ *theBitIndex = theGpioIndex - 54;
+ } else {
+ *theBank = 3;
+ *theBitIndex = theGpioIndex - 86;
+ }
+}
+
+/******************************************************************************/
+
+/**
+ * \brief
+ * Sets the direction of a GPIO from the \ref XGPIOPS_DIRM_OFFSET register of
+ * the appropriate bank.
+ */
+void gpio_setDirection(
+ uint8_t theGpioIndex, //!< integer that refers to the GPIO index
+ uint8_t theDirection //!< output if non-zero
+) {
+ uint8_t theBank; // bank index for the GPIO
+ uint8_t theBitIndex; // bit index in the bank for the GPIO
+ uint32_t * theAddress; // register address to read the GPIO value from
+
+ gpio_getBankAndBitIndex(theGpioIndex, &theBank, &theBitIndex);
+
+ theAddress = (uint32_t *)(XGPIOPS_BASE_ADDR + XGPIOPS_DIRM_OFFSET)
+ + 0x10*theBank;
+
+ if ( theDirection != 0 ) {
+ *theAddress = (*theAddress & ~(1 << theBitIndex)) | (1 << theBitIndex);
+ } else {
+ *theAddress = (*theAddress & ~(1 << theBitIndex)) | (0 << theBitIndex);
+ }
+
+ return;
+}
+
+/******************************************************************************/
+
+/**
+ * \brief
+ * Sets the output enable bit of a GPIO from the \ref XGPIOPS_OUTEN_OFFSET
+ * register of the appropriate bank.
+ */
+void gpio_setOuputEnable(
+ uint8_t theGpioIndex, //!< integer that refers to the GPIO index
+ uint8_t theEnable //!< enabled if non-zero
+) {
+ uint8_t theBank; // bank index for the GPIO
+ uint8_t theBitIndex; // bit index in the bank for the GPIO
+ uint32_t * theAddress; // register address to read the GPIO value from
+
+ gpio_getBankAndBitIndex(theGpioIndex, &theBank, &theBitIndex);
+
+ theAddress = (uint32_t *)(XGPIOPS_BASE_ADDR + XGPIOPS_OUTEN_OFFSET)
+ + 0x10*theBank;
+
+ if ( theEnable != 0 ) {
+ *theAddress = (*theAddress & ~(1 << theBitIndex)) | (1 << theBitIndex);
+ } else {
+ *theAddress = (*theAddress & ~(1 << theBitIndex)) | (0 << theBitIndex);
+ }
+
+ return;
+}
+
+/******************************************************************************/
+
+/**
+ * \brief
+ * Reads the value of a GPIO from the \ref XGPIOPS_DATA_OFFSET register of the
+ * appropriate bank.
+ *
+ * \returns
+ * The value of the GPIO.
+ */
+uint32_t gpio_read(
+ uint8_t theGpioIndex //!< integer that refers to the GPIO index
+) {
+ uint8_t theBank; // bank index for the GPIO
+ uint8_t theBitIndex; // bit index in the bank for the GPIO
+ uint32_t * theAddress; // register address to read the GPIO value from
+
+ gpio_getBankAndBitIndex(theGpioIndex, &theBank, &theBitIndex);
+
+ theAddress = (uint32_t *)(XGPIOPS_BASE_ADDR + XGPIOPS_DATA_OFFSET) + theBank;
+
+ return ((*theAddress & (1 << theBitIndex)) >> theBitIndex);
+}
+
+/******************************************************************************/
+
+/**
+ * \brief
+ * Writes the value of a GPIO in the \ref XGPIOPS_DATA_OFFSET register of the
+ * appropriate bank.
+ */
+void gpio_write(
+ uint8_t theGpioIndex, //!< integer that refers to the GPIO index
+ uint8_t theValue //!< sets the GPIO if non-zero
+) {
+ uint8_t theBank; // bank index for the GPIO
+ uint8_t theBitIndex; // bit index in the bank for the GPIO
+ uint32_t * theAddress; // register address to read the GPIO value from
+
+ gpio_getBankAndBitIndex(theGpioIndex, &theBank, &theBitIndex);
+
+ theAddress = (uint32_t *)(XGPIOPS_BASE_ADDR + XGPIOPS_DATA_OFFSET) + theBank;
+
+ if ( theValue != 0 ) {
+ *theAddress = (*theAddress & ~(1 << theBitIndex)) | (1 << theBitIndex);
+ } else {
+ *theAddress = (*theAddress & ~(1 << theBitIndex)) | (0 << theBitIndex);
+ }
+
+ return;
+}
+
+/******************************************************************************/
+
diff --git a/hello_world/sw/app/gpio.h b/hello_world/sw/app/gpio.h
new file mode 100644
index 0000000..58b57d8
--- /dev/null
+++ b/hello_world/sw/app/gpio.h
@@ -0,0 +1,52 @@
+
+/*
+ Copyright (C) 2021 Jonathan Certes
+
+ This program is free software: you can redistribute it and/or modify it under
+ the terms of the GNU General Public License as published by the Free Software
+ Foundation, either version 3 of the License, or (at your option) any later
+ version.
+
+ This program is distributed in the hope that it will be useful, but WITHOUT
+ ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS
+ FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details.
+
+ You should have received a copy of the GNU General Public License along with
+ this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef __GPIO_H
+ #define __GPIO_H
+
+ #include <stdint.h>
+
+ /**
+ * Base address of XGPIOPS registers
+ */
+ #define XGPIOPS_BASE_ADDR 0xE000A000U
+
+ /**
+ * Offset for data register
+ */
+ #define XGPIOPS_DATA_OFFSET 0x00000040U
+ /**
+ * Offset for direction mode register
+ */
+ #define XGPIOPS_DIRM_OFFSET 0x00000204U
+ /**
+ * Offset for output enable register
+ */
+ #define XGPIOPS_OUTEN_OFFSET 0x00000208U
+ /**
+ * Offset for interrupt enable/unmask
+ */
+ #define XGPIOPS_INTEN_OFFSET 0x00000210U
+
+/******************************************************************************/
+
+ void gpio_setDirection(uint8_t theGpioIndex, uint8_t theDirection);
+ void gpio_setOuputEnable(uint8_t theGpioIndex, uint8_t theEnable);
+ uint32_t gpio_read(uint8_t theGpioIndex);
+ void gpio_write(uint8_t theGpioIndex, uint8_t theValue);
+
+#endif
diff --git a/hello_world/sw/app/ldscript.ld b/hello_world/sw/app/ldscript.ld
new file mode 100644
index 0000000..7800187
--- /dev/null
+++ b/hello_world/sw/app/ldscript.ld
@@ -0,0 +1,94 @@
+
+/* dedicated memories in the DDR: */
+STACK_LENGTH = 0x2000;
+HEAP_LENGTH = 0x2000;
+CODE_LOADER_LENGTH = 0x20000;
+UNDEF_STACK_LENGTH = 0x400; /* used by xilinx functions that flush the cache */
+
+
+/* Define Memories in the system */
+MEMORY
+{
+ ps7_ddr_0 : ORIGIN = 0x100000, LENGTH = 0x1FF00000
+ ps7_qspi_linear_0 : ORIGIN = 0xFC000000, LENGTH = 0x1000000
+ ps7_ram_0 : ORIGIN = 0x0, LENGTH = 0x30000
+ ps7_ram_1 : ORIGIN = 0xFFFF0000, LENGTH = 0xFE00
+}
+
+
+/* Specify the default entry point to the program */
+ENTRY(_start)
+
+
+/* Define the sections, and where they are mapped in memory */
+SECTIONS
+{
+
+ .startup : {
+ . = ALIGN(4);
+ *startup.o(.text)
+ } > ps7_ddr_0
+
+
+ /*****************************************************************************
+ /* Rest of the code, bare metal application:
+ */
+ .text : {
+ /* location where to read the challenge */
+ PROVIDE(__challenge_low = .);
+ *challenge.o(.data)
+ PROVIDE(__challenge_top = .);
+
+ /* memory region to be attested by sw_att */
+ PROVIDE(__attested_low = .);
+ . = ALIGN(4);
+ *attested.o(*)
+ PROVIDE(__attested_top = .);
+
+ /* rest of the code */
+ . = ALIGN(4);
+ *(.text)
+ *(.data)
+ *(.rodata)
+ *(.rodata.*)
+ *(.bss COMMON)
+ } > ps7_ddr_0
+
+ .ARM.exidx : {
+ PROVIDE(__exidx_start = .);
+ . = ALIGN(4);
+ *(.ARM.exidx*)
+ *(.gnu.linkonce.armexidix.*.*)
+ PROVIDE(__exidx_end = .);
+ } > ps7_ddr_0
+
+
+ /*****************************************************************************
+ * heap and stack
+ */
+ .heap (NOLOAD) : {
+ PROVIDE(__heap_low = .);
+ . = . + HEAP_LENGTH;
+ PROVIDE(__heap_top = .);
+ } > ps7_ddr_0
+
+ .stack (NOLOAD) : {
+ PROVIDE(__stack_low = .);
+ PROVIDE(_stack_end = .); /* used by xilinx, identical to __stack_low */
+ . = . + STACK_LENGTH;
+ PROVIDE(__stack_top = .);
+ } > ps7_ddr_0
+
+
+ /*****************************************************************************
+ * undef stack is used by xilinx functions that flush the cache
+ */
+ .undef_stack (NOLOAD) : {
+ PROVIDE(_undef_stack_end = .);
+ . = . + UNDEF_STACK_LENGTH;
+ . = ALIGN(16);
+ PROVIDE(__undef_stack = .);
+ } > ps7_ddr_0
+
+}
+
diff --git a/hello_world/sw/app/main.c b/hello_world/sw/app/main.c
new file mode 100644
index 0000000..e4d82bc
--- /dev/null
+++ b/hello_world/sw/app/main.c
@@ -0,0 +1,61 @@
+
+/*
+ Copyright (C) 2021 Jonathan Certes
+
+ This program is free software: you can redistribute it and/or modify it under
+ the terms of the GNU General Public License as published by the Free Software
+ Foundation, either version 3 of the License, or (at your option) any later
+ version.
+
+ This program is distributed in the hope that it will be useful, but WITHOUT
+ ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS
+ FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details.
+
+ You should have received a copy of the GNU General Public License along with
+ this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include <stdio.h>
+#include "gpio.h"
+
+/**
+ * \brief
+ * Integer that refers to the input pin index: <tt> EMIO[1] </tt>. See details
+ * of \ref gpio_read().
+ */
+#define GPIO_INPUT_INDEX 55
+
+/**
+ * \brief
+ * Integer that refers to the output pin index: <tt> EMIO[0] </tt>. See details
+ * of \ref gpio_read().
+ */
+#define GPIO_OUTPUT_INDEX 54
+
+/******************************************************************************/
+
+/**
+ * \brief
+ * GPIO output is set to the opposite value as the GPIO input.
+ */
+int main (
+ void
+) {
+ uint32_t theInputValue; // what is read on GPIO input
+
+ gpio_setDirection(GPIO_OUTPUT_INDEX, 1);
+ gpio_setOuputEnable(GPIO_OUTPUT_INDEX, 1);
+ //
+ gpio_setDirection(GPIO_INPUT_INDEX, 0);
+
+ printf("Hello World.\n");
+
+ while ( 1 ) {
+ // sets the output to the opposite value as the input:
+ theInputValue = gpio_read(GPIO_INPUT_INDEX);
+ gpio_write(GPIO_OUTPUT_INDEX, !theInputValue);
+ }
+
+ return 0;
+}
+
diff --git a/hello_world/sw/app/startup.s b/hello_world/sw/app/startup.s
new file mode 100644
index 0000000..8140b2e
--- /dev/null
+++ b/hello_world/sw/app/startup.s
@@ -0,0 +1,28 @@
+
+#
+# Copyright (C) 2021 Jonathan Certes
+#
+# This program is free software: you can redistribute it and/or modify it under
+# the terms of the GNU General Public License as published by the Free Software
+# Foundation, either version 3 of the License, or (at your option) any later
+# version.
+#
+# This program is distributed in the hope that it will be useful, but WITHOUT
+# ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS
+# FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License along with
+# this program. If not, see <http://www.gnu.org/licenses/>.
+#
+
+.extern __stack_top
+.extern main
+
+.global _start
+
+_start:
+ ldr sp, =__stack_top
+ mov fp, sp
+ bl main
+ b .
+
diff --git a/hello_world/sw/app/stdio.c b/hello_world/sw/app/stdio.c
new file mode 100644
index 0000000..f29da80
--- /dev/null
+++ b/hello_world/sw/app/stdio.c
@@ -0,0 +1,175 @@
+
+/*
+ Copyright (C) 2021 Jonathan Certes
+
+ This program is free software: you can redistribute it and/or modify it under
+ the terms of the GNU General Public License as published by the Free Software
+ Foundation, either version 3 of the License, or (at your option) any later
+ version.
+
+ This program is distributed in the hope that it will be useful, but WITHOUT
+ ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS
+ FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details.
+
+ You should have received a copy of the GNU General Public License along with
+ this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include <stdio.h>
+#include <xuartps_hw.h>
+#include <sys/stat.h>
+
+/**
+ * \defgroup system System calls
+ *
+ * \brief
+ * Overloading system calls so that we can call <tt> scanf() </tt> and <tt>
+ * printf() </tt> and make them read/write on UART 1.
+ *
+ * \details
+ * Works when linking with arm-none-eabi newlib.
+ *
+ * \{
+ */
+
+#define UART1_BASE 0xE0001000U //!< Base address of UART1 registers
+
+/**
+ * This symbol is defined in the linker script: beginning of the heap.
+ * Useful for function \ref _sbrk() called by <tt> printf() </tt>.
+ */
+extern int __heap_low;
+
+/******************************************************************************/
+/******************************************************************************/
+
+/**
+ * Returns the status of an open file. The minimal version of this should
+ * identify all files as character special devices. This forces one-byte-read at
+ * a time.
+ */
+int _fstat(int file, struct stat *st) {
+ st->st_mode = S_IFCHR;
+ return 0;
+}
+
+/******************************************************************************/
+
+/**
+ * Repositions the file offset of the open file associated with the file
+ * descriptor fd to the argument offset according to the directive whence.
+ * Here we can simply return 0, which implies the file is empty.
+ */
+int _lseek(int file, int offset, int whence) {
+ return 0;
+}
+
+/******************************************************************************/
+
+/**
+ * Closes a file descriptor fd.
+ * Since no file should have gotten open()-ed, we can just return an error on
+ * close.
+ */
+int _close(int fd) {
+ return -1;
+}
+
+/******************************************************************************/
+
+/**
+ * Writes up to count bytes from the buffer starting at buf to the file referred
+ * to by the file descriptor fd.
+ * Functions like printf() rely on write to write bytes to STDOUT. In our case,
+ * we will want those bytes to be written to serial instead.
+ */
+int _write(
+ int fd,
+ const void *buf,
+ size_t count
+) {
+ char theChar;
+ size_t i;
+
+ (void)fd; // Parameter is not used, suppresses unused argument warning
+
+ for ( i = 0; i < count; i++ ) {
+ theChar = *(uint8_t*)buf;
+ if ( theChar == '\n' ) {
+ XUartPs_SendByte(UART1_BASE, '\r'); // UART1 is connected to USB on Zybo
+ }
+ XUartPs_SendByte(UART1_BASE, theChar);
+ (uint8_t*)buf++;
+ }
+
+ return i;
+}
+
+/******************************************************************************/
+
+/**
+ * Attempts to read up to count bytes from file descriptor fd into the buffer at
+ * buf.
+ * Similarly to write, we want read to read bytes from serial.
+ */
+int _read(
+ int fd,
+ char *buf,
+ int count
+) {
+ int read = 0;
+
+ while (!XUartPs_IsReceiveData(UART1_BASE)) {
+ // do nothing
+ }
+
+ for ( int i = 0; i < count; i++ ) {
+
+ if ( XUartPs_IsReceiveData(UART1_BASE) ) {
+ *buf = (char)( XUartPs_ReadReg(UART1_BASE, XUARTPS_FIFO_OFFSET) );
+ buf++;
+ read++;
+ }
+
+ }
+
+ return read;
+}
+
+/******************************************************************************/
+
+/**
+ * Increases the program’s data space by increment bytes. In other words, it
+ * increases the size of the heap.
+ * Newlib's printf implementations allocates data on the heap and depends on a
+ * working malloc implementation.
+ */
+void * _sbrk(int incr) {
+ static unsigned char *heap = NULL;
+ unsigned char *prev_heap;
+
+ if (heap == NULL) {
+ heap = (unsigned char *)&__heap_low;
+ }
+ prev_heap = heap;
+
+ heap += incr;
+
+ return prev_heap;
+}
+
+/******************************************************************************/
+
+/**
+ * Always tell <tt> printf() </tt> that its printing into a tty, which has
+ * direct connexion to input/output peripherals.
+ */
+int _isatty(int file) {
+ return 1;
+}
+
+/******************************************************************************/
+
+/**
+ * \}
+ */
diff --git a/hello_world/sw/fsbl/Makefile b/hello_world/sw/fsbl/Makefile
new file mode 100644
index 0000000..7e0ead6
--- /dev/null
+++ b/hello_world/sw/fsbl/Makefile
@@ -0,0 +1,64 @@
+# Auto Generated by Xilinx generate_app. Modify at your own risk
+
+CC := arm-none-eabi-gcc
+CC_FLAGS := -MMD -MP -mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=softfp -g
+CFLAGS :=
+LN_FLAGS := -mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=softfp -Wl,-build-id=none \
+ -specs=Xilinx.spec -lrsa \
+ -Wl,--start-group,-lxil,-lgcc,-lc,--end-group \
+ -Wl,--start-group,-lxilffs,-lxil,-lgcc,-lc,--end-group \
+ -Wl,--start-group,-lrsa,-lxil,-lgcc,-lc,--end-group \
+ -Wl,--gc-sections
+
+c_SOURCES := $(wildcard *.c) ps7_init.c
+S_SOURCES := $(wildcard *.S)
+s_SOURCES := $(wildcard *.s)
+INCLUDES := $(wildcard *.h)
+OBJS := $(sort $(patsubst %.c, %.o, $(c_SOURCES)))
+OBJS += $(sort $(patsubst %.S, %.o, $(S_SOURCES)))
+OBJS += $(sort $(patsubst %.s, %.o, $(s_SOURCES)))
+LSCRIPT := -T lscript.ld
+
+CURRENT_DIR = $(shell pwd)
+DEPFILES := $(patsubst %.o, %.d, $(OBJS))
+LIBS := zynq_fsbl_bsp/ps7_cortexa9_0/lib/libxil.a
+EXEC := main.elf
+
+INCLUDEPATH := -I zynq_fsbl_bsp/ps7_cortexa9_0/include -I .
+LIBPATH := -L zynq_fsbl_bsp/ps7_cortexa9_0/lib -L .
+
+#===============================================================================
+
+all: $(EXEC)
+
+
+$(EXEC): $(LIBS) $(OBJS) $(INCLUDES)
+ $(CC) -o $@ $(OBJS) $(CC_FLAGS) $(CFLAGS) $(LN_FLAGS) $(LIBPATH) $(LSCRIPT)
+
+$(LIBS):
+ $(MAKE) -C zynq_fsbl_bsp
+
+%.o:%.c ps7_init.h
+ $(CC) $(CC_FLAGS) $(CFLAGS) -c $< -o $@ $(INCLUDEPATH)
+
+%.o:%.S
+ $(CC) $(CC_FLAGS) $(CFLAGS) -c $< -o $@ $(INCLUDEPATH)
+
+%.o:%.s
+ $(CC) $(CC_FLAGS) $(CFLAGS) -c $< -o $@ $(INCLUDEPATH)
+
+
+# we get the ps7_init files from a synthesis of the hardware:
+ps7_init.c ps7_init.h: ../../hw/ps7_init.c ../../hw/ps7_init.h
+ cp -f $^ .
+
+../../hw/ps7_init.c ../../hw/ps7_init.h:
+ $(MAKE) -C ../../hw/
+
+
+clean:
+ rm -rf $(OBJS) $(LIBS) $(EXEC) *.o *.d
+ $(MAKE) -C zynq_fsbl_bsp clean
+ $(RM) ps7_init.c ps7_init.h
+
+-include $(DEPFILES)
diff --git a/hello_world/sw/fsbl/Xilinx.spec b/hello_world/sw/fsbl/Xilinx.spec
new file mode 100644
index 0000000..8eea377
--- /dev/null
+++ b/hello_world/sw/fsbl/Xilinx.spec
@@ -0,0 +1,2 @@
+*startfile:
+crti%O%s crtbegin%O%s
diff --git a/hello_world/sw/fsbl/fsbl.h b/hello_world/sw/fsbl/fsbl.h
new file mode 100644
index 0000000..d4b1cea
--- /dev/null
+++ b/hello_world/sw/fsbl/fsbl.h
@@ -0,0 +1,557 @@
+/******************************************************************************
+*
+* Copyright (C) 2012 - 2018 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+* THE SOFTWARE.
+*
+*
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file fsbl.h
+*
+* Contains the function prototypes, defines and macros for the
+* First Stage Boot Loader (FSBL) functionality
+*
+* <pre>
+* MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ----- ---- -------- -------------------------------------------------------
+* 1.00a jz 03/04/11 Initial release
+* 2.00a mb 06/06/12 Removed the qspi define, will be picked from
+* xparameters.h file
+* 3.00a np/mb 08/08/12 Added the error codes for the FSBL hook errors.
+* Added the debug levels
+* 4.00a sgd 02/28/13 Removed DDR initialization check
+* Removed DDR ECC initialization code
+* Modified hand off address check to 1MB
+* Added RSA authentication support
+* Removed LPBK_DLY_ADJ register setting code as we use
+* divisor 8
+* Removed check for Fabric is already initialized
+*
+* CR's fixed and description
+* 689026: FSBL doesn't hold PL resets active during
+* bit download
+* Resolution: PL resets are released just before
+* handoff
+*
+* 689077: FSBL hangs at Handoff clearing the
+* TX UART buffer
+* Resolution: STDOUT_BASEADDRESS macro value changes
+* based UART select, hence used STDOUT_BASEADDRESS
+* as UART base address
+*
+* 695578: FSBL failed to load standalone application
+* in secure bootmode
+* Resolution: Application will be placed at load address
+* instead of DDR temporary address
+*
+* 699475: FSBL functionality is broken and its
+* not able to boot in QSPI/NAND bootmode
+* Resolution: New flags are added DevCfg driver
+* for handling loopback
+* XDCFG_CONCURRENT_NONSEC_READ_WRITE
+* XDCFG_CONCURRENT_SECURE_READ_WRITE
+*
+* 683145: Define stack area for FIQ, UNDEF modes
+* in linker file
+* Resolution: FSBL linker modified to create stack area
+* for FIQ, UNDEF
+*
+* 705664: FSBL fails to decrypt the bitstream when
+* the image is AES encrypted using non-zero key value
+* Resolution: Fabric cleaning will not be done
+* for AES-E-Fuse encryption
+*
+* Watchdog disabled for AES E-Fuse encryption
+*
+* 5.00a sgd 05/17/13 Fallback support for E-Fuse encryption
+* Added QSPI Flash Size > 128Mbit support
+* QSPI Dual Stack support
+* Added Md5 checksum support
+*
+* CR's fixed and description
+* 692045 FSBL: Linker script of FSBL has PHDR workaround,
+* this needs to be fixed
+* Resolution: Removed PHDR from Linker file
+*
+* 704287 FSBL: fsbl.h file has a few error codes that
+* are not used by FSBL, that needs to be removed
+* Resolution: Removed unused error codes
+*
+* 704379 FSBL: Check if DDR is in proper state before
+* handoff
+* Resolution: Added DDR initialization check
+*
+* 709077 If FSBL_DEBUG and FSBL_DEBUG_INFO are defined,
+* the debug level is FSBL_DEBUG only.
+*
+* 710128 FSBL: Linux boot failing without load attribute
+* set for Linux partitions in BIF
+* Resolution: FSBL will load partitions with valid load
+* address and stop loading if any invalid load address
+*
+* 708728 Issues seen while making HP interconnect
+* 32 bit wide
+* Resolution: ps7_post_config function generated by PCW
+* will be called after Bit stream download
+* Added MMC support
+* 6.00a kc 07/31/2013 CR's fixed and description
+* 724166 FSBL doesn’t use PPK authenticated by Boot ROM
+* for authenticating the Partition images
+* Resolution: FSBL now uses the PPK left by Boot ROM in
+* OCM for authencating the SPK
+*
+* 724165 Partition Header used by FSBL is not
+* authenticated
+* Resolution: FSBL now authenticates the partition header
+*
+* 691150 ps7_init does not check for peripheral
+* initialization failures or timeout on polls
+* Resolution: Return value of ps7_init() is now checked
+* by FSBL and prints the error string
+*
+* 708316 PS7_init.tcl file should have Error mechanism
+* for all mask_poll
+* Resolution: Return value of ps7_init() is now checked
+* by FSBL and prints the error string
+*
+* 732062 FSBL fails to build if UART not available
+* Resolution: Added define to call xil_printf only
+* if uart is defined
+*
+* 722979 Provide customer-friendly changelogs in FSBL
+* Resolution: Added CR description for all the files
+*
+* 732865 Backward compatibility for ps7_init function
+* Resolution: Added a new define for ps7_init success
+* and value is defined based on ps7_init define
+*
+* Fix for CR#739711 - FSBL not able to read Large
+* QSPI (512M) in IO Mode
+* Resolution: Modified the address calculation
+* algorithm in dual parallel mode for QSPI
+*
+* 7.00a kc 10/18/13 Integrated SD/MMC driver
+* 10/23/13 Support for armcc compiler added
+* 741003 FSBL has to check the HMAC error status after
+* decryption
+* Resolution: Added code for checking the error status
+* after PCAP completion
+* 739968 FSBL should do the QSPI config settings for
+* Dual parallel configuration in IO mode
+* Resolution: Added QSPI config settings in qspi.c
+* 724620 FSBL: How to handle PCAP_MODE after bitstream
+* configuration.
+* Resolution: PCAP_MODE and PCAP_PR bits are now cleared
+* after PCAP transfer completion
+* 726178 In the 14.6 FSBL function FabricInit() PROG_B
+* is kept active for 5mS.
+* Resolution: PROG_B is now kept active for 5ms only in case
+* if efuse is the aes key source.
+* 755245 FSBL does not load partition if eMMC has only
+* one partition
+* Resolution: Changed the if condition for MMC
+* 12/04/13 764382 FSBL: How to handle PCAP_MODE after bitstream
+* configuration
+* Resolution: Reverted back the changes of 724620. PCAP_MODE
+* and PCAP_PR bits are not changed
+* 8.00a kc 01/16/13 767798 Fsbl MD5 Checksum failiure for encrypted images
+* Resolution: For checksum enabled partitions, total
+* total partition image length is copied now.
+* 761895 FSBL should authenticate image only if
+* partition owner was not set to u-boot
+* Resolution: Partition owner check added in
+* image_mover.c
+* 02/20/14 775631 - FSBL: FsblGetGlobalTimer() is not proper
+* Resolution: Function argument is updated from value
+* to pointer to reflect updated value
+* 9.00a kc 04/16/14 773866 - SetPpk() will fail on secure fallback
+* unless FSBL* and FSBL are identical in length
+* Resolution: PPK is set only once now.
+* 785778 - FSBL takes 8 seconds to
+* authenticate (RSA) a bitstream on zc706
+* Resolution: Data Caches are enabled only for
+* authentication.
+* 791245 - Use of xilrsa in fsbl
+* Resolution: Rsa library is removed from fsbl source
+* and xilrsa is used from BSP
+* 10.00a kc 07/15/14 804595 Zynq FSBL - Issues with
+* fallback image offset handling using MD5
+* Resolution: Updated the checksum offset to add with
+* image base address
+* 782309 Fallback support for AES
+* encryption with E-Fuse - Enhancement
+* Resolution: Same as 773866
+* 809336 Minor code cleanup
+* Resolution Minor code changes
+* kc 08/27/14 820356 - FSBL compilation fails with IAR compiler
+* Resolution: Change of __asm__ to __asm
+* 11.00a kv 10/08/14 826030 - FSBL:LinearBootDeviceFlag is not initialized
+* in IO mode case.Due to which the variable is
+* remaining in unknown state.
+* Resolution: LinearBootDeviceFlag is initialized 0
+* in main.c
+* 12.00a ssc 12/11/14 839182 - FSBL -In the file sd.c, f_mount is called with
+* two arguments but f_mount is expecting the 3 arguments
+* from build 2015.1_1210_1, causing compilation error.
+* Resolution: Arguments for f_mount in InitSD() are
+* changed as per new signature.
+* 13.00a ssc 04/10/15 846899 - FSBL -In the file pcap.c, to clear DMA done
+* count, devcfg.INT_STS register is written to, which is
+* not correct.
+* Resolution: Corresponding fields in the devcfg.STATUS
+* register are written to, for clearing DMA done count.
+* 14.00a gan 01/13/16 869081 -(2016.1)FSBL -In qspi.c, FSBL picks the qspi
+* read command from LQSPI_CFG register instead of hard
+* coded read command (0x6B).
+* 15.00a gan 07/21/16 953654 -(2016.3)FSBL -In pcap.c/pcap.h/main.c,
+* Fabric Initialization sequence is modified to check
+* the PL power before sequence starts and checking INIT_B
+* reset status twice in case of failure.
+* 16.00a gan 08/02/16 Fix for CR# 955897 -(2016.3)FSBL -
+* In pcap.c, check pl power through MCTRL register
+* for 3.0 and later versions of silicon.
+* 17.00a bsv 27/03/18 Fix for CR# 996973 Add code under JTAG_ENABLE_LEVEL_SHIFTERS macro
+* to enable level shifters in jtag boot mode.
+* 18.00a ka 10/29/18 Fix for CR# 1006294 Added macro for FORCE_USE_AES_EXCLUDE
+*
+* </pre>
+*
+* </pre>
+*
+* @note
+*
+* Flags in FSBL
+*
+* FSBL_PERF
+*
+* This Flag can be set at compilation time. This flag is set for
+* measuring the performance of FSBL.That is the time taken to execute is
+* measured.when this flag is set.Execution time with reference to
+* global timer is taken here
+*
+* Total Execution time is the time taken for executing FSBL till handoff
+* to any application .
+* If there is a bitstream in the partition header then the
+* execution time includes the copying of the bitstream to DDR
+* (in case of SD/NAND bootmode)
+* and programming the devcfg dma is accounted.
+*
+* FSBL provides two debug levels
+* DEBUG GENERAL - fsbl_printf under this category will appear only when the
+* FSBL_DEBUG flag is set during compilation
+* DEBUG_INFO - fsbl_printf under this category will appear when the
+* FSBL_DEBUG_INFO flag is set during compilation
+* For a more detailed output log can be used.
+* FSBL_DEBUG_RSA - Define this macro to print more detailed values used in
+* RSA functions
+* These macros are input to the fsbl_printf function
+*
+* DEBUG LEVELS
+* FSBL_DEBUG level is level 1, when this flag is set all the fsbl_prints
+* that are with the DEBUG_GENERAL argument are shown
+* FSBL_DEBUG_INFO is level 2, when this flag is set during the
+* compilation , the fsbl_printf with DEBUG_INFO will appear on the com port
+*
+* DEFAULT LEVEL
+* By default no print messages will appear.
+*
+* NON_PS_INSTANTIATED_BITSTREAM
+*
+* FSBL will not enable the level shifters for a NON PS instantiated
+* Bitstream.This flag can be set during compilation for a NON PS instantiated
+* bitstream
+*
+* ECC_ENABLE
+* This flag will be defined in the ps7_init.h file when ECC is enabled
+* in the DDR configuration (XPS GUI)
+*
+* RSA_SUPPORT
+* This flag is used to enable authentication feature
+* Default this macro disabled, reason to avoid increase in code size
+*
+* MMC_SUPPORT
+* This flag is used to enable MMC support feature
+*
+* JTAG_ENABLE_LEVEL_SHIFTERS
+* FSBL will not enable the level shifters for jtag boot mode. This flag can be
+* set during compilation for jtag boot mode to enable level shifters.
+*
+* FORCE_USE_AES_EXCLUDE
+* Defining this flag will exclude the feature, forcing every partition to be
+* encrypted when EFUSE_SEC_EN bit is set.
+* This flag can be set/unset during compilation.
+* By default this flag is unset/undefined which enables the above feature
+* Note : Changing the default behaviour is not recommended from
+* Security perspective.
+*
+*******************************************************************************/
+#ifndef XIL_FSBL_H
+#define XIL_FSBL_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/***************************** Include Files *********************************/
+#include "xil_io.h"
+#include "xparameters.h"
+#include "xpseudo_asm.h"
+#include "xil_printf.h"
+#include "pcap.h"
+#include "fsbl_debug.h"
+#include "ps7_init.h"
+#ifdef FSBL_PERF
+#include "xtime_l.h"
+#include <stdio.h>
+#endif
+
+
+/************************** Constant Definitions *****************************/
+/*
+ * SDK release version
+ */
+#define SDK_RELEASE_YEAR 2019
+#define SDK_RELEASE_QUARTER 2
+
+#define WORD_LENGTH_SHIFT 2
+
+/*
+ * On a Successful handoff to an application FSBL sets this SUCCESS code
+ */
+#define SUCCESSFUL_HANDOFF 0x1 /* Successful Handoff */
+
+/*
+ * Backward compatibility for ps7_init
+ */
+#ifdef NEW_PS7_ERR_CODE
+#define FSBL_PS7_INIT_SUCCESS PS7_INIT_SUCCESS
+#else
+#define FSBL_PS7_INIT_SUCCESS (1)
+#endif
+
+/*
+ * ERROR CODES
+ * The following are the Error codes that FSBL uses
+ * If the Debug prints are enabled only then the error codes will be
+ * seen on the com port.Without the debug prints enabled no error codes will
+ * be visible.There are not saved in any register
+ * Boot Mode States used for error and status output
+ * Error codes are defined below
+ */
+#define ILLEGAL_BOOT_MODE 0xA000 /**< Illegal boot mode */
+#define ILLEGAL_RETURN 0xA001 /**< Illegal return */
+#define PCAP_INIT_FAIL 0xA002 /**< Pcap driver Init Failed */
+#define DECRYPTION_FAIL 0xA003 /**< Decryption Failed */
+#define BITSTREAM_DOWNLOAD_FAIL 0xA004 /**< Bitstream download fail */
+#define DMA_TRANSFER_FAIL 0xA005 /**< DMA Transfer Fail */
+#define INVALID_FLASH_ADDRESS 0xA006 /**< Invalid Flash Address */
+#define DDR_INIT_FAIL 0xA007 /**< DDR Init Fail */
+#define NO_DDR 0xA008 /**< DDR missing */
+#define SD_INIT_FAIL 0xA009 /**< SD Init fail */
+#define NAND_INIT_FAIL 0xA00A /**< Nand Init Fail */
+#define PARTITION_MOVE_FAIL 0xA00B /**< Partition move fail */
+#define AUTHENTICATION_FAIL 0xA00C /**< Authentication fail */
+#define INVALID_HEADER_FAIL 0xA00D /**< Invalid header fail */
+#define GET_HEADER_INFO_FAIL 0xA00E /**< Get header fail */
+#define INVALID_LOAD_ADDRESS_FAIL 0xA00F /**< Invalid load address fail */
+#define PARTITION_CHECKSUM_FAIL 0xA010 /**< Partition checksum fail */
+#define RSA_SUPPORT_NOT_ENABLED_FAIL 0xA011 /**< RSA not enabled fail */
+#define PS7_INIT_FAIL 0xA012 /**< ps7 Init Fail */
+#define PARTITION_LOAD_FAIL 0xA013 /**< Partition load fail*/
+/*
+ * FSBL Exception error codes
+ */
+#define EXCEPTION_ID_UNDEFINED_INT 0xA301 /**< Undefined INT Exception */
+#define EXCEPTION_ID_SWI_INT 0xA302 /**< SWI INT Exception */
+#define EXCEPTION_ID_PREFETCH_ABORT_INT 0xA303 /**< Prefetch Abort xception */
+#define EXCEPTION_ID_DATA_ABORT_INT 0xA304 /**< Data Abort Exception */
+#define EXCEPTION_ID_IRQ_INT 0xA305 /**< IRQ Exception Occurred */
+#define EXCEPTION_ID_FIQ_INT 0xA306 /**< FIQ Exception Occurred */
+
+/*
+ * FSBL hook routine failures
+ */
+#define FSBL_HANDOFF_HOOK_FAIL 0xA401 /**< FSBL handoff hook failed */
+#define FSBL_BEFORE_BSTREAM_HOOK_FAIL 0xA402 /**< FSBL before bit stream
+ download hook failed */
+#define FSBL_AFTER_BSTREAM_HOOK_FAIL 0xA403 /**< FSBL after bitstream
+ download hook failed */
+
+/*
+ * Watchdog related Error codes
+ */
+#define WDT_RESET_OCCURED 0xA501 /**< WDT Reset happened in FSBL */
+#define WDT_INIT_FAIL 0xA502 /**< WDT driver INIT failed */
+
+/*
+ * SLCR Registers
+ */
+#define PS_RST_CTRL_REG (XPS_SYS_CTRL_BASEADDR + 0x200)
+#define FPGA_RESET_REG (XPS_SYS_CTRL_BASEADDR + 0x240)
+#define RESET_REASON_REG (XPS_SYS_CTRL_BASEADDR + 0x250)
+#define RESET_REASON_CLR (XPS_SYS_CTRL_BASEADDR + 0x254)
+#define REBOOT_STATUS_REG (XPS_SYS_CTRL_BASEADDR + 0x258)
+#define BOOT_MODE_REG (XPS_SYS_CTRL_BASEADDR + 0x25C)
+#define PS_LVL_SHFTR_EN (XPS_SYS_CTRL_BASEADDR + 0x900)
+
+/*
+ * Efuse Status Register
+ */
+#define EFUSE_STATUS_REG (0xF800D010) /**< Efuse Status Register */
+#define EFUSE_STATUS_RSA_ENABLE_MASK (0x400) /**< Status of RSA enable */
+
+/*
+ * PS reset control register define
+ */
+#define PS_RST_MASK 0x1 /**< PS software reset */
+
+/*
+ * SLCR BOOT Mode Register defines
+ */
+#define BOOT_MODES_MASK 0x00000007 /**< FLASH types */
+
+/*
+ * Boot Modes
+ */
+#define JTAG_MODE 0x00000000 /**< JTAG Boot Mode */
+#define QSPI_MODE 0x00000001 /**< QSPI Boot Mode */
+#define NOR_FLASH_MODE 0x00000002 /**< NOR Boot Mode */
+#define NAND_FLASH_MODE 0x00000004 /**< NAND Boot Mode */
+#define SD_MODE 0x00000005 /**< SD Boot Mode */
+#define MMC_MODE 0x00000006 /**< MMC Boot Device */
+
+#define RESET_REASON_SRST 0x00000020 /**< Reason for reset is SRST */
+#define RESET_REASON_SWDT 0x00000001 /**< Reason for reset is SWDT */
+
+/*
+ * Golden image offset
+ */
+#define GOLDEN_IMAGE_OFFSET 0x8000
+
+/*
+ * Silicon Version
+ */
+#define SILICON_VERSION_1 0
+#define SILICON_VERSION_2 1
+#define SILICON_VERSION_3 2
+#define SILICON_VERSION_3_1 3
+
+/*
+ * DDR start address for storing the data temporarily(1M)
+ * Need to finalize correct logic
+ */
+#ifdef XPAR_PS7_DDR_0_S_AXI_BASEADDR
+#define DDR_START_ADDR XPAR_PS7_DDR_0_S_AXI_BASEADDR
+#define DDR_END_ADDR XPAR_PS7_DDR_0_S_AXI_HIGHADDR
+#else
+/*
+ * In case of PL DDR, this macros defined based PL DDR address
+ */
+#define DDR_START_ADDR 0x00
+#define DDR_END_ADDR 0x00
+#endif
+
+#define DDR_TEMP_START_ADDR DDR_START_ADDR
+/*
+ * DDR test pattern
+ */
+#define DDR_TEST_PATTERN 0xAA55AA55
+#define DDR_TEST_OFFSET 0x100000
+/*
+ *
+ */
+#define QSPI_DUAL_FLASH_SIZE 0x2000000; /*32MB*/
+#define QSPI_SINGLE_FLASH_SIZE 0x1000000; /*16MB*/
+#define NAND_FLASH_SIZE 0x8000000; /*128MB*/
+#define NOR_FLASH_SIZE 0x2000000; /*32MB*/
+#define LQSPI_CFG_OFFSET 0xA0
+#define LQSPI_CFG_DUAL_FLASH_MASK 0x40000000
+
+/*
+ * These are the SLCR lock and unlock macros
+ */
+#define SlcrUnlock() Xil_Out32(XPS_SYS_CTRL_BASEADDR + 0x08, 0xDF0DDF0D)
+#define SlcrLock() Xil_Out32(XPS_SYS_CTRL_BASEADDR + 0x04, 0x767B767B)
+
+#define IMAGE_HEADER_CHECKSUM_COUNT 10
+
+/* Boot ROM Image defines */
+#define IMAGE_WIDTH_CHECK_OFFSET (0x020) /**< 0xaa995566 Width Detection word */
+#define IMAGE_IDENT_OFFSET (0x024) /**< 0x584C4E58 "XLNX" */
+#define IMAGE_ENC_FLAG_OFFSET (0x028) /**< 0xA5C3C5A3 */
+#define IMAGE_USR_DEF_OFFSET (0x02C) /**< undefined could be used as */
+#define IMAGE_SOURCE_ADDR_OFFSET (0x030) /**< start address of image */
+#define IMAGE_BYTE_LEN_OFFSET (0x034) /**< length of image> in bytes */
+#define IMAGE_DEST_ADDR_OFFSET (0x038) /**< destination address in OCM */
+#define IMAGE_EXECUTE_ADDR_OFFSET (0x03c) /**< address to start executing at */
+#define IMAGE_TOT_BYTE_LEN_OFFSET (0x040) /**< total length of image in bytes */
+#define IMAGE_QSPI_CFG_WORD_OFFSET (0x044) /**< QSPI configuration data */
+#define IMAGE_CHECKSUM_OFFSET (0x048) /**< Header Checksum offset */
+#define IMAGE_IDENT (0x584C4E58) /**< XLNX pattern */
+
+/* Reboot status register defines:
+ * 0xF0000000 for FSBL fallback mask to notify Boot Rom
+ * 0x60000000 for FSBL to mark that FSBL has not handoff yet
+ * 0x00FFFFFF for user application to use across soft reset
+ */
+#define FSBL_FAIL_MASK 0xF0000000
+#define FSBL_IN_MASK 0x60000000
+
+/* The address that holds the base address for the image Boot ROM found */
+#define BASEADDR_HOLDER 0xFFFFFFF8
+
+/**************************** Type Definitions *******************************/
+
+/************************** Function Prototypes ******************************/
+
+void OutputStatus(u32 State);
+void FsblFallback(void);
+
+int FsblSetNextPartition(int Num);
+void *(memcpy_rom)(void * s1, const void * s2, u32 n);
+char *strcpy_rom(char *Dest, const char *Src);
+
+void ClearFSBLIn(void);
+void MarkFSBLIn(void);
+void FsblHandoff(u32 FsblStartAddr);
+u32 GetResetReason(void);
+
+#ifdef FSBL_PERF
+void FsblGetGlobalTime (XTime * tCur);
+void FsblMeasurePerfTime (XTime tCur, XTime tEnd);
+#endif
+void GetSiliconVersion(void);
+void FsblHandoffExit(u32 FsblStartAddr);
+void FsblHandoffJtagExit();
+/************************** Variable Definitions *****************************/
+extern int SkipPartition;
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* end of protection macro */
diff --git a/hello_world/sw/fsbl/fsbl_debug.h b/hello_world/sw/fsbl/fsbl_debug.h
new file mode 100644
index 0000000..cb84848
--- /dev/null
+++ b/hello_world/sw/fsbl/fsbl_debug.h
@@ -0,0 +1,76 @@
+/******************************************************************************
+*
+* Copyright (C) 2012 - 2014 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+* THE SOFTWARE.
+*
+*
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file fsbl_debug.h
+*
+* This file contains the debug verbose information for FSBL print functionality
+*
+* <pre>
+* MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ----- ---- -------- -------------------------------------------------------
+* 3.00a mb 01/09/12 Initial release
+*
+* </pre>
+*
+* @note
+*
+******************************************************************************/
+
+#ifndef _FSBL_DEBUG_H
+#define _FSBL_DEBUG_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+
+#define DEBUG_GENERAL 0x00000001 /* general debug messages */
+#define DEBUG_INFO 0x00000002 /* More debug information */
+
+#if defined (FSBL_DEBUG_INFO)
+#define fsbl_dbg_current_types ((DEBUG_INFO) | (DEBUG_GENERAL))
+#elif defined (FSBL_DEBUG)
+#define fsbl_dbg_current_types (DEBUG_GENERAL)
+#else
+#define fsbl_dbg_current_types 0
+#endif
+
+#ifdef STDOUT_BASEADDRESS
+#define fsbl_printf(type,...) \
+ if (((type) & fsbl_dbg_current_types)) {xil_printf (__VA_ARGS__); }
+#else
+#define fsbl_printf(type, ...)
+#endif
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _FSBL_DEBUG_H */
diff --git a/hello_world/sw/fsbl/fsbl_handoff.S b/hello_world/sw/fsbl/fsbl_handoff.S
new file mode 100644
index 0000000..ca4e77d
--- /dev/null
+++ b/hello_world/sw/fsbl/fsbl_handoff.S
@@ -0,0 +1,215 @@
+#ifdef __GNUC__
+/******************************************************************************
+*
+* Copyright (C) 2012 - 2014 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+* THE SOFTWARE.
+*
+*
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file handoff.S
+*
+* Contains the code that does the handoff to the loaded application. This
+* code lives high in the ROM.
+*
+* <pre>
+* MODIFICATION HISTORY:
+*
+* Ver Who Date.word Changes
+* ----- ---- -------- -------------------------------------------------------
+* 1.00a ecm 03/01/10 Initial release
+* 7.00a kc 10/23/13 Added support for armcc compiler
+* </pre>
+*
+* @note
+* Assumes that the starting address of the FSBL is provided by the calling routine
+* in R0.
+*
+******************************************************************************/
+
+.globl FsblHandoffJtagExit
+
+.globl FsblHandoffExit
+
+.section .handoff,"axS"
+
+/***************************** Include Files *********************************/
+
+/************************** Constant Definitions *****************************/
+
+/**************************** Type Definitions *******************************/
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/************************** Function Prototypes ******************************/
+
+/************************** Variable Definitions *****************************/
+
+FsblHandoffJtagExit:
+ mcr 15,0,r0,cr7,cr5,0 /* Invalidate Instruction cache */
+ mcr 15,0,r0,cr7,cr5,6 /* Invalidate branch predictor array */
+
+ dsb
+ isb /* make sure it completes */
+
+ ldr r4, =0
+ mcr 15,0,r4,cr1,cr0,0 /* disable the ICache and MMU */
+
+ isb /* make sure it completes */
+Loop:
+ wfe
+ b Loop
+
+FsblHandoffExit:
+ mov lr, r0 /* move the destination address into link register */
+
+ mcr 15,0,r0,cr7,cr5,0 /* Invalidate Instruction cache */
+ mcr 15,0,r0,cr7,cr5,6 /* Invalidate branch predictor array */
+
+ dsb
+ isb /* make sure it completes */
+
+ ldr r4, =0
+ mcr 15,0,r4,cr1,cr0,0 /* disable the ICache and MMU */
+
+ isb /* make sure it completes */
+
+
+ bx lr /* force the switch, destination should have been in r0 */
+
+.Ldone: b .Ldone /* Paranoia: we should never get here */
+.end
+
+#elif defined (__IASMARM__)
+
+ PUBLIC FsblHandoffJtagExit
+
+ PUBLIC FsblHandoffExit
+
+ SECTION .handoff:CODE:NOROOT(2)
+
+/***************************** Include Files *********************************/
+
+/************************** Constant Definitions *****************************/
+
+/**************************** Type Definitions *******************************/
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/************************** Function Prototypes ******************************/
+
+/************************** Variable Definitions *****************************/
+
+FsblHandoffJtagExit
+ mcr p15,0,r0,c7,c5,0 ;/* Invalidate Instruction cache */
+ mcr p15,0,r0,c7,c5,6 ;/* Invalidate branch predictor array */
+
+ dsb
+ isb ;/* make sure it completes */
+
+ ldr r4, =0
+ mcr p15,0,r4,c1,c0,0 ;/* disable the ICache and MMU */
+
+ isb ;/* make sure it completes */
+Loop
+ wfe
+ b Loop
+
+FsblHandoffExit
+ mov lr, r0 ;/* move the destination address into link register */
+
+ mcr p15,0,r0,c7,c5,0 ;/* Invalidate Instruction cache */
+ mcr p15,0,r0,c7,c5,6 ;/* Invalidate branch predictor array */
+
+ dsb
+ isb ;/* make sure it completes */
+
+ ldr r4, =0
+ mcr p15,0,r4,c1,c0,0 ;/* disable the ICache and MMU */
+
+ isb ;/* make sure it completes */
+
+
+ bx lr ;/* force the switch, destination should have been in r0 */
+
+.Ldone
+ b .Ldone ;/* Paranoia: we should never get here */
+
+ END
+
+
+#else
+ EXPORT FsblHandoffJtagExit
+
+ EXPORT FsblHandoffExit
+
+ AREA |.handoff|,CODE
+
+;/***************************** Include Files *********************************/
+
+;/************************** Constant Definitions *****************************/
+
+;/**************************** Type Definitions *******************************/
+
+;/***************** Macros (Inline Functions) Definitions *********************/
+
+;/************************** Function Prototypes ******************************/
+
+;/************************** Variable Definitions *****************************/
+
+
+FsblHandoffJtagExit
+ mcr p15,0,r0,c7,c5,0 ;/* Invalidate Instruction cache */
+ mcr p15,0,r0,c7,c5,6 ;/* Invalidate branch predictor array */
+
+ dsb
+ isb ;/* make sure it completes */
+
+ ldr r4, =0
+ mcr p15,0,r4,c1,c0,0 ;/* disable the ICache and MMU */
+
+ isb ;/* make sure it completes */
+Loop
+ wfe
+ b Loop
+
+FsblHandoffExit
+ mov lr, r0 ;/* move the destination address into link register */
+
+ mcr p15,0,r0,c7,c5,0 ;/* Invalidate Instruction cache */
+ mcr p15,0,r0,c7,c5,6 ;/* Invalidate branch predictor array */
+
+ dsb
+ isb ;/* make sure it completes */
+
+ ldr r4, =0
+ mcr p15,0,r4,c1,c0,0 ;/* disable the ICache and MMU */
+
+ isb ;/* make sure it completes */
+
+
+ bx lr ;/* force the switch, destination should have been in r0 */
+
+Ldone b Ldone ;/* Paranoia: we should never get here */
+ END
+#endif
diff --git a/hello_world/sw/fsbl/fsbl_hooks.c b/hello_world/sw/fsbl/fsbl_hooks.c
new file mode 100644
index 0000000..5236bd6
--- /dev/null
+++ b/hello_world/sw/fsbl/fsbl_hooks.c
@@ -0,0 +1,158 @@
+/******************************************************************************
+*
+* Copyright (C) 2012 - 2014 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+* THE SOFTWARE.
+*
+*
+*
+******************************************************************************/
+
+/*****************************************************************************
+*
+* @file fsbl_hooks.c
+*
+* This file provides functions that serve as user hooks. The user can add the
+* additional functionality required into these routines. This would help retain
+* the normal FSBL flow unchanged.
+*
+* <pre>
+* MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ----- ---- -------- -------------------------------------------------------
+* 3.00a np 08/03/12 Initial release
+* </pre>
+*
+* @note
+*
+******************************************************************************/
+
+
+#include "fsbl.h"
+#include "xstatus.h"
+#include "fsbl_hooks.h"
+
+/************************** Variable Definitions *****************************/
+
+
+/************************** Function Prototypes ******************************/
+
+
+/******************************************************************************
+* This function is the hook which will be called before the bitstream download.
+* The user can add all the customized code required to be executed before the
+* bitstream download to this routine.
+*
+* @param None
+*
+* @return
+* - XST_SUCCESS to indicate success
+* - XST_FAILURE.to indicate failure
+*
+****************************************************************************/
+u32 FsblHookBeforeBitstreamDload(void)
+{
+ u32 Status;
+
+ Status = XST_SUCCESS;
+
+ /*
+ * User logic to be added here. Errors to be stored in the status variable
+ * and returned
+ */
+ fsbl_printf(DEBUG_INFO,"In FsblHookBeforeBitstreamDload function \r\n");
+
+ return (Status);
+}
+
+/******************************************************************************
+* This function is the hook which will be called after the bitstream download.
+* The user can add all the customized code required to be executed after the
+* bitstream download to this routine.
+*
+* @param None
+*
+* @return
+* - XST_SUCCESS to indicate success
+* - XST_FAILURE.to indicate failure
+*
+****************************************************************************/
+u32 FsblHookAfterBitstreamDload(void)
+{
+ u32 Status;
+
+ Status = XST_SUCCESS;
+
+ /*
+ * User logic to be added here.
+ * Errors to be stored in the status variable and returned
+ */
+ fsbl_printf(DEBUG_INFO, "In FsblHookAfterBitstreamDload function \r\n");
+
+ return (Status);
+}
+
+/******************************************************************************
+* This function is the hook which will be called before the FSBL does a handoff
+* to the application. The user can add all the customized code required to be
+* executed before the handoff to this routine.
+*
+* @param None
+*
+* @return
+* - XST_SUCCESS to indicate success
+* - XST_FAILURE.to indicate failure
+*
+****************************************************************************/
+u32 FsblHookBeforeHandoff(void)
+{
+ u32 Status;
+
+ Status = XST_SUCCESS;
+
+ /*
+ * User logic to be added here.
+ * Errors to be stored in the status variable and returned
+ */
+ fsbl_printf(DEBUG_INFO,"In FsblHookBeforeHandoff function \r\n");
+
+ return (Status);
+}
+
+
+/******************************************************************************
+* This function is the hook which will be called in case FSBL fall back
+*
+* @param None
+*
+* @return None
+*
+****************************************************************************/
+void FsblHookFallback(void)
+{
+ /*
+ * User logic to be added here.
+ * Errors to be stored in the status variable and returned
+ */
+ fsbl_printf(DEBUG_INFO,"In FsblHookFallback function \r\n");
+ while(1);
+}
+
+
diff --git a/hello_world/sw/fsbl/fsbl_hooks.h b/hello_world/sw/fsbl/fsbl_hooks.h
new file mode 100644
index 0000000..34b2bd2
--- /dev/null
+++ b/hello_world/sw/fsbl/fsbl_hooks.h
@@ -0,0 +1,75 @@
+/******************************************************************************
+*
+* Copyright (C) 2012 - 2014 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+* THE SOFTWARE.
+*
+*
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file fsbl_hooks.h
+*
+* Contains the function prototypes, defines and macros required by fsbl_hooks.c
+*
+* <pre>
+* MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ----- ---- -------- -------------------------------------------------------
+* 3.00a np/mb 10/08/12 Initial release
+* Corrected the prototype
+*
+* </pre>
+*
+* @note
+*
+******************************************************************************/
+#ifndef FSBL_HOOKS_H_
+#define FSBL_HOOKS_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/***************************** Include Files *********************************/
+#include "fsbl.h"
+
+
+/************************** Function Prototypes ******************************/
+
+/* FSBL hook function which is called before bitstream download */
+u32 FsblHookBeforeBitstreamDload(void);
+
+/* FSBL hook function which is called after bitstream download */
+u32 FsblHookAfterBitstreamDload(void);
+
+/* FSBL hook function which is called before handoff to the application */
+u32 FsblHookBeforeHandoff(void);
+
+/* FSBL hook function which is called in FSBL fallback */
+void FsblHookFallback(void);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* end of protection macro */
diff --git a/hello_world/sw/fsbl/image_mover.c b/hello_world/sw/fsbl/image_mover.c
new file mode 100644
index 0000000..c6735bf
--- /dev/null
+++ b/hello_world/sw/fsbl/image_mover.c
@@ -0,0 +1,1346 @@
+/******************************************************************************
+*
+* Copyright (C) 2011 - 2018 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+* THE SOFTWARE.
+*
+*
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file image_mover.c
+*
+* Move partitions to either DDR to execute or to program FPGA.
+* It performs partition walk.
+*
+* <pre>
+* MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ----- ---- -------- -------------------------------------------------------
+* 1.00a jz 05/24/11 Initial release
+* 2.00a jz 06/30/11 Updated partition header defs for 64-byte
+* alignment change in data2mem tool
+* 2.00a mb 05/25/12 Updated for standalone based bsp FSBL
+* Nand/SD encryption and review comments
+* 3.00a np 08/30/12 Added FSBL user hook calls
+* (before and after bitstream download.)
+* 4.00a sgd 02/28/13 Fix for CR#691148 Secure bootmode error in devcfg test
+* Fix for CR#695578 FSBL failed to load standalone
+* application in secure bootmode
+*
+* 4.00a sgd 04/23/13 Fix for CR#710128 FSBL failed to load standalone
+* application in secure bootmode
+* 5.00a kc 07/30/13 Fix for CR#724165 Partition Header used by FSBL
+* is not authenticated
+* Fix for CR#724166 FSBL doesn�t use PPK authenticated
+* by Boot ROM for authenticating the Partition images
+* Fix for CR#732062 FSBL fails to build if UART not
+* available
+* 7.00a kc 10/30/13 Fix for CR#755245 FSBL does not load partition
+* if eMMC has only one partition
+* 8.00a kc 01/16/13 Fix for CR#767798 FSBL MD5 Checksum failure
+* for encrypted images
+* Fix for CR#761895 FSBL should authenticate image
+* only if partition owner was not set to u-boot
+* 9.00a kc 04/16/14 Fix for CR#785778 FSBL takes 8 seconds to
+* authenticate (RSA) a bitstream on zc706
+* 10.00a kc 07/15/14 Fix for CR#804595 Zynq FSBL - Issues with
+* fallback image offset handling using MD5
+* Fix for PR#782309 Fallback support for AES
+* encryption with E-Fuse - Enhancement
+* 11.00a ka 10/12/18 Fix for CR#1006294 Zynq FSBL - Zynq FSBL does not check
+* USE_AES_ONLY eFuse
+*
+* </pre>
+*
+* @note
+* A partition is either an executable or a bitstream to program FPGA
+*
+******************************************************************************/
+
+/***************************** Include Files *********************************/
+#include "fsbl.h"
+#include "image_mover.h"
+#include "xil_printf.h"
+#include "xreg_cortexa9.h"
+#include "pcap.h"
+#include "fsbl_hooks.h"
+#include "md5.h"
+
+#ifdef XPAR_XWDTPS_0_BASEADDR
+#include "xwdtps.h"
+#endif
+
+#ifdef RSA_SUPPORT
+#include "rsa.h"
+#include "xil_cache.h"
+#endif
+/************************** Constant Definitions *****************************/
+
+/* We are 32-bit machine */
+#define MAXIMUM_IMAGE_WORD_LEN 0x40000000
+#define MD5_CHECKSUM_SIZE 16
+
+/**************************** Type Definitions *******************************/
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/************************** Function Prototypes ******************************/
+u32 ValidateParition(u32 StartAddr, u32 Length, u32 ChecksumOffset);
+u32 GetPartitionChecksum(u32 ChecksumOffset, u8 *Checksum);
+u32 CalcPartitionChecksum(u32 SourceAddr, u32 DataLength, u8 *Checksum);
+
+/************************** Variable Definitions *****************************/
+/*
+ * Partition information flags
+ */
+u8 EncryptedPartitionFlag;
+u8 PLPartitionFlag;
+u8 PSPartitionFlag;
+u8 SignedPartitionFlag;
+u8 PartitionChecksumFlag;
+u8 BitstreamFlag;
+u8 ApplicationFlag;
+
+u32 ExecutionAddress;
+ImageMoverType MoveImage;
+
+/*
+ * Header array
+ */
+PartHeader PartitionHeader[MAX_PARTITION_NUMBER];
+u32 PartitionCount;
+u32 FsblLength;
+
+#ifdef XPAR_XWDTPS_0_BASEADDR
+extern XWdtPs Watchdog; /* Instance of WatchDog Timer */
+#endif
+
+extern u32 Silicon_Version;
+extern u32 FlashReadBaseAddress;
+extern u8 LinearBootDeviceFlag;
+extern XDcfg *DcfgInstPtr;
+
+/*****************************************************************************/
+/**
+*
+* This function
+*
+* @param
+*
+* @return
+*
+*
+* @note None
+*
+****************************************************************************/
+u32 LoadBootImage(void)
+{
+ u32 RebootStatusRegister = 0;
+ u32 MultiBootReg = 0;
+ u32 ImageStartAddress = 0;
+ u32 PartitionNum;
+ u32 PartitionDataLength;
+ u32 PartitionImageLength;
+ u32 PartitionTotalSize;
+ u32 PartitionExecAddr;
+ u32 PartitionAttr;
+ u32 ExecAddress = 0;
+ u32 PartitionLoadAddr;
+ u32 PartitionStartAddr;
+ u32 PartitionChecksumOffset;
+ u8 ExecAddrFlag = 0 ;
+ u32 Status;
+ PartHeader *HeaderPtr;
+ u32 EfuseStatusRegValue;
+#ifdef RSA_SUPPORT
+ u32 HeaderSize;
+#endif
+#ifndef FORCE_USE_AES_EXCLUDE
+ u32 EncOnly;
+#endif
+ /*
+ * Resetting the Flags
+ */
+ BitstreamFlag = 0;
+ ApplicationFlag = 0;
+
+ RebootStatusRegister = Xil_In32(REBOOT_STATUS_REG);
+ fsbl_printf(DEBUG_INFO,
+ "Reboot status register: 0x%08lx\r\n",RebootStatusRegister);
+
+ if (Silicon_Version == SILICON_VERSION_1) {
+ /*
+ * Clear out fallback mask from previous run
+ * We start from the first partition again
+ */
+ if ((RebootStatusRegister & FSBL_FAIL_MASK) ==
+ FSBL_FAIL_MASK) {
+ fsbl_printf(DEBUG_INFO,
+ "Reboot status shows previous run falls back\r\n");
+ RebootStatusRegister &= ~(FSBL_FAIL_MASK);
+ Xil_Out32(REBOOT_STATUS_REG, RebootStatusRegister);
+ }
+
+ /*
+ * Read the image start address
+ */
+ ImageStartAddress = *(u32 *)BASEADDR_HOLDER;
+ } else {
+ /*
+ * read the multiboot register
+ */
+ MultiBootReg = XDcfg_ReadReg(DcfgInstPtr->Config.BaseAddr,
+ XDCFG_MULTIBOOT_ADDR_OFFSET);
+
+ fsbl_printf(DEBUG_INFO,"Multiboot Register: 0x%08lx\r\n",MultiBootReg);
+
+ /*
+ * Compute the image start address
+ */
+ ImageStartAddress = (MultiBootReg & PCAP_MBOOT_REG_REBOOT_OFFSET_MASK)
+ * GOLDEN_IMAGE_OFFSET;
+ }
+
+ fsbl_printf(DEBUG_INFO,"Image Start Address: 0x%08lx\r\n",ImageStartAddress);
+
+ /*
+ * Get partitions header information
+ */
+ Status = GetPartitionHeaderInfo(ImageStartAddress);
+ if (Status != XST_SUCCESS) {
+ fsbl_printf(DEBUG_GENERAL, "Partition Header Load Failed\r\n");
+ OutputStatus(GET_HEADER_INFO_FAIL);
+ FsblFallback();
+ }
+
+ /*
+ * RSA is not implemented in 1.0 and 2.0
+ * silicon
+ */
+ if ((Silicon_Version != SILICON_VERSION_1) &&
+ (Silicon_Version != SILICON_VERSION_2)) {
+ /*
+ * Read Efuse Status Register
+ */
+ EfuseStatusRegValue = Xil_In32(EFUSE_STATUS_REG);
+ if (EfuseStatusRegValue & EFUSE_STATUS_RSA_ENABLE_MASK) {
+ fsbl_printf(DEBUG_GENERAL,"RSA enabled for Chip\r\n");
+#ifdef RSA_SUPPORT
+ /*
+ * Set the Ppk
+ */
+ SetPpk();
+
+ /*
+ * Read partition header with signature
+ */
+ Status = GetImageHeaderAndSignature(ImageStartAddress,
+ (u32 *)DDR_TEMP_START_ADDR);
+ if (Status != XST_SUCCESS) {
+ fsbl_printf(DEBUG_GENERAL,
+ "Read Partition Header signature Failed\r\n");
+ OutputStatus(GET_HEADER_INFO_FAIL);
+ FsblFallback();
+ }
+ HeaderSize=TOTAL_HEADER_SIZE+RSA_SIGNATURE_SIZE;
+
+ Status = AuthenticatePartition((u8 *)DDR_TEMP_START_ADDR, HeaderSize);
+ if (Status != XST_SUCCESS) {
+ fsbl_printf(DEBUG_GENERAL,
+ "Partition Header signature Failed\r\n");
+ OutputStatus(GET_HEADER_INFO_FAIL);
+ FsblFallback();
+ }
+#else
+ /*
+ * In case user not enabled RSA authentication feature
+ */
+ fsbl_printf(DEBUG_GENERAL,"RSA_SUPPORT_NOT_ENABLED_FAIL\r\n");
+ OutputStatus(RSA_SUPPORT_NOT_ENABLED_FAIL);
+ FsblFallback();
+#endif
+ }
+ }
+
+#ifdef MMC_SUPPORT
+ /*
+ * In case of MMC support
+ * boot image preset in MMC will not have FSBL partition
+ */
+ PartitionNum = 0;
+#else
+ /*
+ * First partition header was ignored by FSBL
+ * As it contain FSBL partition information
+ */
+ PartitionNum = 1;
+#endif
+
+ while (PartitionNum < PartitionCount) {
+
+ fsbl_printf(DEBUG_INFO, "Partition Number: %lu\r\n", PartitionNum);
+
+ HeaderPtr = &PartitionHeader[PartitionNum];
+
+ /*
+ * Print partition header information
+ */
+ HeaderDump(HeaderPtr);
+
+ /*
+ * Validate partition header
+ */
+ Status = ValidateHeader(HeaderPtr);
+ if (Status != XST_SUCCESS) {
+ fsbl_printf(DEBUG_GENERAL, "INVALID_HEADER_FAIL\r\n");
+ OutputStatus(INVALID_HEADER_FAIL);
+ FsblFallback();
+ }
+
+ /*
+ * Load partition header information in to local variables
+ */
+ PartitionDataLength = HeaderPtr->DataWordLen;
+ PartitionImageLength = HeaderPtr->ImageWordLen;
+ PartitionExecAddr = HeaderPtr->ExecAddr;
+ PartitionAttr = HeaderPtr->PartitionAttr;
+ PartitionLoadAddr = HeaderPtr->LoadAddr;
+ PartitionChecksumOffset = HeaderPtr->CheckSumOffset;
+ PartitionStartAddr = HeaderPtr->PartitionStart;
+ PartitionTotalSize = HeaderPtr->PartitionWordLen;
+
+ /*
+ * Partition owner should be FSBL to validate the partition
+ */
+ if ((PartitionAttr & ATTRIBUTE_PARTITION_OWNER_MASK) !=
+ ATTRIBUTE_PARTITION_OWNER_FSBL) {
+ /*
+ * if FSBL is not the owner of partition,
+ * skip this partition, continue with next partition
+ */
+ fsbl_printf(DEBUG_INFO, "Skipping partition %0lx\r\n",
+ PartitionNum);
+ /*
+ * Increment partition number
+ */
+ PartitionNum++;
+ continue;
+ }
+
+ if (PartitionAttr & ATTRIBUTE_PL_IMAGE_MASK) {
+ fsbl_printf(DEBUG_INFO, "Bitstream\r\n");
+ PLPartitionFlag = 1;
+ PSPartitionFlag = 0;
+ BitstreamFlag = 1;
+ if (ApplicationFlag == 1) {
+#ifdef STDOUT_BASEADDRESS
+ xil_printf("\r\nFSBL Warning !!!"
+ "Bitstream not loaded into PL\r\n");
+ xil_printf("Partition order invalid\r\n");
+#endif
+ break;
+ }
+ }
+
+ if (PartitionAttr & ATTRIBUTE_PS_IMAGE_MASK) {
+ fsbl_printf(DEBUG_INFO, "Application\r\n");
+ PSPartitionFlag = 1;
+ PLPartitionFlag = 0;
+ ApplicationFlag = 1;
+ }
+
+ /*
+ * Encrypted partition will have different value
+ * for Image length and data length
+ */
+ if (PartitionDataLength != PartitionImageLength) {
+ fsbl_printf(DEBUG_INFO, "Encrypted\r\n");
+ EncryptedPartitionFlag = 1;
+ } else {
+ EncryptedPartitionFlag = 0;
+ }
+
+#ifndef FORCE_USE_AES_EXCLUDE
+ EncOnly = XDcfg_ReadReg(DcfgInstPtr->Config.BaseAddr,
+ XDCFG_STATUS_OFFSET) &
+ XDCFG_STATUS_EFUSE_SEC_EN_MASK;
+ if ((EncOnly != 0) &&
+ (EncryptedPartitionFlag == 0)) {
+ fsbl_printf(DEBUG_GENERAL,"EFUSE_SEC_EN bit is set,"
+ " Encryption is mandatory\r\n");
+ OutputStatus(PARTITION_LOAD_FAIL);
+ FsblFallback();
+ }
+#endif
+ /*
+ * Check for partition checksum check
+ */
+ if (PartitionAttr & ATTRIBUTE_CHECKSUM_TYPE_MASK) {
+ PartitionChecksumFlag = 1;
+ } else {
+ PartitionChecksumFlag = 0;
+ }
+
+ /*
+ * RSA signature check
+ */
+ if (PartitionAttr & ATTRIBUTE_RSA_PRESENT_MASK) {
+ fsbl_printf(DEBUG_INFO, "RSA Signed\r\n");
+ SignedPartitionFlag = 1;
+ } else {
+ SignedPartitionFlag = 0;
+ }
+
+ /*
+ * Load address check
+ * Loop will break when PS load address zero and partition is
+ * un-signed or un-encrypted
+ */
+ if ((PSPartitionFlag == 1) && (PartitionLoadAddr < DDR_START_ADDR)) {
+ if ((PartitionLoadAddr == 0) &&
+ (!((SignedPartitionFlag == 1) ||
+ (EncryptedPartitionFlag == 1)))) {
+ break;
+ } else {
+ fsbl_printf(DEBUG_GENERAL,
+ "INVALID_LOAD_ADDRESS_FAIL\r\n");
+ OutputStatus(INVALID_LOAD_ADDRESS_FAIL);
+ FsblFallback();
+ }
+ }
+
+ if (PSPartitionFlag && (PartitionLoadAddr > DDR_END_ADDR)) {
+ fsbl_printf(DEBUG_GENERAL,
+ "INVALID_LOAD_ADDRESS_FAIL\r\n");
+ OutputStatus(INVALID_LOAD_ADDRESS_FAIL);
+ FsblFallback();
+ }
+
+ /*
+ * Load execution address of first PS partition
+ */
+ if (PSPartitionFlag && (!ExecAddrFlag)) {
+ ExecAddrFlag++;
+ ExecAddress = PartitionExecAddr;
+ }
+
+ /*
+ * FSBL user hook call before bitstream download
+ */
+ if (PLPartitionFlag) {
+ Status = FsblHookBeforeBitstreamDload();
+ if (Status != XST_SUCCESS) {
+ fsbl_printf(DEBUG_GENERAL,"FSBL_BEFORE_BSTREAM_HOOK_FAIL\r\n");
+ OutputStatus(FSBL_BEFORE_BSTREAM_HOOK_FAIL);
+ FsblFallback();
+ }
+ }
+
+ /*
+ * Move partitions from boot device
+ */
+ Status = PartitionMove(ImageStartAddress, HeaderPtr);
+ if (Status != XST_SUCCESS) {
+ fsbl_printf(DEBUG_GENERAL,"PARTITION_MOVE_FAIL\r\n");
+ OutputStatus(PARTITION_MOVE_FAIL);
+ FsblFallback();
+ }
+
+ if ((SignedPartitionFlag) || (PartitionChecksumFlag)) {
+ if(PLPartitionFlag) {
+ /*
+ * PL partition loaded in to DDR temporary address
+ * for authentication and checksum verification
+ */
+ PartitionStartAddr = DDR_TEMP_START_ADDR;
+ } else {
+ PartitionStartAddr = PartitionLoadAddr;
+ }
+
+ if (PartitionChecksumFlag) {
+ /*
+ * Validate the partition data with checksum
+ */
+ Status = ValidateParition(PartitionStartAddr,
+ (PartitionTotalSize << WORD_LENGTH_SHIFT),
+ ImageStartAddress +
+ (PartitionChecksumOffset << WORD_LENGTH_SHIFT));
+ if (Status != XST_SUCCESS) {
+ fsbl_printf(DEBUG_GENERAL,"PARTITION_CHECKSUM_FAIL\r\n");
+ OutputStatus(PARTITION_CHECKSUM_FAIL);
+ FsblFallback();
+ }
+
+ fsbl_printf(DEBUG_INFO, "Partition Validation Done\r\n");
+ }
+
+ /*
+ * Authentication Partition
+ */
+ if (SignedPartitionFlag == 1 ) {
+#ifdef RSA_SUPPORT
+ Xil_DCacheEnable();
+ Status = AuthenticatePartition((u8*)PartitionStartAddr,
+ (PartitionTotalSize << WORD_LENGTH_SHIFT));
+ if (Status != XST_SUCCESS) {
+ Xil_DCacheFlush();
+ Xil_DCacheDisable();
+ fsbl_printf(DEBUG_GENERAL,"AUTHENTICATION_FAIL\r\n");
+ OutputStatus(AUTHENTICATION_FAIL);
+ FsblFallback();
+ }
+ fsbl_printf(DEBUG_INFO,"Authentication Done\r\n");
+ Xil_DCacheFlush();
+ Xil_DCacheDisable();
+#else
+ /*
+ * In case user not enabled RSA authentication feature
+ */
+ fsbl_printf(DEBUG_GENERAL,"RSA_SUPPORT_NOT_ENABLED_FAIL\r\n");
+ OutputStatus(RSA_SUPPORT_NOT_ENABLED_FAIL);
+ FsblFallback();
+#endif
+ }
+
+ /*
+ * Decrypt PS partition
+ */
+ if (EncryptedPartitionFlag && PSPartitionFlag) {
+ Status = DecryptPartition(PartitionStartAddr,
+ PartitionDataLength,
+ PartitionImageLength);
+ if (Status != XST_SUCCESS) {
+ fsbl_printf(DEBUG_GENERAL,"DECRYPTION_FAIL\r\n");
+ OutputStatus(DECRYPTION_FAIL);
+ FsblFallback();
+ }
+ }
+
+ /*
+ * Load Signed PL partition in Fabric
+ */
+ if (PLPartitionFlag) {
+ Status = PcapLoadPartition((u32*)PartitionStartAddr,
+ (u32*)PartitionLoadAddr,
+ PartitionImageLength,
+ PartitionDataLength,
+ EncryptedPartitionFlag);
+ if (Status != XST_SUCCESS) {
+ fsbl_printf(DEBUG_GENERAL,"BITSTREAM_DOWNLOAD_FAIL\r\n");
+ OutputStatus(BITSTREAM_DOWNLOAD_FAIL);
+ FsblFallback();
+ }
+ }
+ }
+
+
+ /*
+ * FSBL user hook call after bitstream download
+ */
+ if (PLPartitionFlag) {
+ Status = FsblHookAfterBitstreamDload();
+ if (Status != XST_SUCCESS) {
+ fsbl_printf(DEBUG_GENERAL,"FSBL_AFTER_BSTREAM_HOOK_FAIL\r\n");
+ OutputStatus(FSBL_AFTER_BSTREAM_HOOK_FAIL);
+ FsblFallback();
+ }
+ }
+ /*
+ * Increment partition number
+ */
+ PartitionNum++;
+ }
+
+ return ExecAddress;
+}
+
+/*****************************************************************************/
+/**
+*
+* This function loads all partition header information in global array
+*
+* @param ImageAddress is the start address of the image
+*
+* @return - XST_SUCCESS if Get partition Header information successful
+* - XST_FAILURE if Get Partition Header information failed
+*
+* @note None
+*
+****************************************************************************/
+u32 GetPartitionHeaderInfo(u32 ImageBaseAddress)
+{
+ u32 PartitionHeaderOffset;
+ u32 Status;
+
+
+ /*
+ * Get the length of the FSBL from BootHeader
+ */
+ Status = GetFsblLength(ImageBaseAddress, &FsblLength);
+ if (Status != XST_SUCCESS) {
+ fsbl_printf(DEBUG_GENERAL, "Get Header Start Address Failed\r\n");
+ return XST_FAILURE;
+ }
+
+ /*
+ * Get the start address of the partition header table
+ */
+ Status = GetPartitionHeaderStartAddr(ImageBaseAddress,
+ &PartitionHeaderOffset);
+ if (Status != XST_SUCCESS) {
+ fsbl_printf(DEBUG_GENERAL, "Get Header Start Address Failed\r\n");
+ return XST_FAILURE;
+ }
+
+ /*
+ * Header offset on flash
+ */
+ PartitionHeaderOffset += ImageBaseAddress;
+
+ fsbl_printf(DEBUG_INFO,"Partition Header Offset:0x%08lx\r\n",
+ PartitionHeaderOffset);
+
+ /*
+ * Load all partitions header data in to global variable
+ */
+ Status = LoadPartitionsHeaderInfo(PartitionHeaderOffset,
+ &PartitionHeader[0]);
+ if (Status != XST_SUCCESS) {
+ fsbl_printf(DEBUG_GENERAL, "Header Information Load Failed\r\n");
+ return XST_FAILURE;
+ }
+
+ /*
+ * Get partitions count from partitions header information
+ */
+ PartitionCount = GetPartitionCount(&PartitionHeader[0]);
+
+ fsbl_printf(DEBUG_INFO, "Partition Count: %lu\r\n", PartitionCount);
+
+ /*
+ * Partition Count check
+ */
+ if (PartitionCount >= MAX_PARTITION_NUMBER) {
+ fsbl_printf(DEBUG_GENERAL, "Invalid Partition Count\r\n");
+ return XST_FAILURE;
+#ifndef MMC_SUPPORT
+ } else if (PartitionCount <= 1) {
+ fsbl_printf(DEBUG_GENERAL, "There is no partition to load\r\n");
+ return XST_FAILURE;
+#endif
+ }
+
+ return XST_SUCCESS;
+}
+
+
+/*****************************************************************************/
+/**
+*
+* This function goes to the partition header of the specified partition
+*
+* @param ImageAddress is the start address of the image
+*
+* @return Offset Partition header address of the image
+*
+* @return - XST_SUCCESS if Get Partition Header start address successful
+* - XST_FAILURE if Get Partition Header start address failed
+*
+* @note None
+*
+****************************************************************************/
+u32 GetPartitionHeaderStartAddr(u32 ImageAddress, u32 *Offset)
+{
+ u32 Status;
+
+ Status = MoveImage(ImageAddress + IMAGE_PHDR_OFFSET, (u32)Offset, 4);
+ if (Status != XST_SUCCESS) {
+ fsbl_printf(DEBUG_GENERAL,"Move Image failed\r\n");
+ return XST_FAILURE;
+ }
+
+ return XST_SUCCESS;
+}
+
+/*****************************************************************************/
+/**
+*
+* This function goes to the partition header of the specified partition
+*
+* @param ImageAddress is the start address of the image
+*
+* @return Offset to Image header table address of the image
+*
+* @return - XST_SUCCESS if Get Partition Header start address successful
+* - XST_FAILURE if Get Partition Header start address failed
+*
+* @note None
+*
+****************************************************************************/
+u32 GetImageHeaderStartAddr(u32 ImageAddress, u32 *Offset)
+{
+ u32 Status;
+
+ Status = MoveImage(ImageAddress + IMAGE_HDR_OFFSET, (u32)Offset, 4);
+ if (Status != XST_SUCCESS) {
+ fsbl_printf(DEBUG_GENERAL,"Move Image failed\r\n");
+ return XST_FAILURE;
+ }
+
+ return XST_SUCCESS;
+}
+/*****************************************************************************/
+/**
+*
+* This function gets the length of the FSBL
+*
+* @param ImageAddress is the start address of the image
+*
+* @return FsblLength is the length of the fsbl
+*
+* @return - XST_SUCCESS if fsbl length reading is successful
+* - XST_FAILURE if fsbl length reading failed
+*
+* @note None
+*
+****************************************************************************/
+u32 GetFsblLength(u32 ImageAddress, u32 *FsblLength)
+{
+ u32 Status;
+
+ Status = MoveImage(ImageAddress + IMAGE_TOT_BYTE_LEN_OFFSET,
+ (u32)FsblLength, 4);
+ if (Status != XST_SUCCESS) {
+ fsbl_printf(DEBUG_GENERAL,"Move Image failed reading FsblLength\r\n");
+ return XST_FAILURE;
+ }
+
+ return XST_SUCCESS;
+}
+
+#ifdef RSA_SUPPORT
+/*****************************************************************************/
+/**
+*
+* This function goes to read the image headers and its signature. Image
+* header consists of image header table, image headers, partition
+* headers
+*
+* @param ImageBaseAddress is the start address of the image header
+*
+* @return Offset Partition header address of the image
+*
+* @return - XST_SUCCESS if Get Partition Header start address successful
+* - XST_FAILURE if Get Partition Header start address failed
+*
+* @note None
+*
+****************************************************************************/
+u32 GetImageHeaderAndSignature(u32 ImageBaseAddress, u32 *Offset)
+{
+ u32 Status;
+ u32 ImageHeaderOffset;
+
+ /*
+ * Get the start address of the partition header table
+ */
+ Status = GetImageHeaderStartAddr(ImageBaseAddress, &ImageHeaderOffset);
+ if (Status != XST_SUCCESS) {
+ fsbl_printf(DEBUG_GENERAL, "Get Header Start Address Failed\r\n");
+ return XST_FAILURE;
+ }
+
+ Status = MoveImage(ImageBaseAddress+ImageHeaderOffset, (u32)Offset,
+ TOTAL_HEADER_SIZE + RSA_SIGNATURE_SIZE);
+ if (Status != XST_SUCCESS) {
+ fsbl_printf(DEBUG_GENERAL,"Move Image failed\r\n");
+ return XST_FAILURE;
+ }
+
+ return XST_SUCCESS;
+}
+#endif
+/*****************************************************************************/
+/**
+*
+* This function get the header information of the all the partitions and load into
+* global array
+*
+* @param PartHeaderOffset Offset address where the header information present
+*
+* @param Header Partition header pointer
+*
+* @return - XST_SUCCESS if Load Partitions Header information successful
+* - XST_FAILURE if Load Partitions Header information failed
+*
+* @note None
+*
+****************************************************************************/
+u32 LoadPartitionsHeaderInfo(u32 PartHeaderOffset, PartHeader *Header)
+{
+ u32 Status;
+
+ Status = MoveImage(PartHeaderOffset, (u32)Header, sizeof(PartHeader)*MAX_PARTITION_NUMBER);
+ if (Status != XST_SUCCESS) {
+ fsbl_printf(DEBUG_GENERAL,"Move Image failed\r\n");
+ return XST_FAILURE;
+ }
+
+ return XST_SUCCESS;
+}
+
+
+/*****************************************************************************/
+/**
+*
+* This function dumps the partition header.
+*
+* @param Header Partition header pointer
+*
+* @return None
+*
+* @note None
+*
+******************************************************************************/
+void HeaderDump(PartHeader *Header)
+{
+ fsbl_printf(DEBUG_INFO, "Header Dump\r\n");
+ fsbl_printf(DEBUG_INFO, "Image Word Len: 0x%08lx\r\n",
+ Header->ImageWordLen);
+ fsbl_printf(DEBUG_INFO, "Data Word Len: 0x%08lx\r\n",
+ Header->DataWordLen);
+ fsbl_printf(DEBUG_INFO, "Partition Word Len:0x%08lx\r\n",
+ Header->PartitionWordLen);
+ fsbl_printf(DEBUG_INFO, "Load Addr: 0x%08lx\r\n",
+ Header->LoadAddr);
+ fsbl_printf(DEBUG_INFO, "Exec Addr: 0x%08lx\r\n",
+ Header->ExecAddr);
+ fsbl_printf(DEBUG_INFO, "Partition Start: 0x%08lx\r\n",
+ Header->PartitionStart);
+ fsbl_printf(DEBUG_INFO, "Partition Attr: 0x%08lx\r\n",
+ Header->PartitionAttr);
+ fsbl_printf(DEBUG_INFO, "Partition Checksum Offset: 0x%08lx\r\n",
+ Header->CheckSumOffset);
+ fsbl_printf(DEBUG_INFO, "Section Count: 0x%08lx\r\n",
+ Header->SectionCount);
+ fsbl_printf(DEBUG_INFO, "Checksum: 0x%08lx\r\n",
+ Header->CheckSum);
+}
+
+
+/******************************************************************************/
+/**
+*
+* This function calculates the partitions count from header information
+*
+* @param Header Partition header pointer
+*
+* @return Count Partition count
+*
+* @note None
+*
+*******************************************************************************/
+u32 GetPartitionCount(PartHeader *Header)
+{
+ u32 Count=0;
+ struct HeaderArray *Hap;
+
+ for(Count = 0; Count < MAX_PARTITION_NUMBER; Count++) {
+ Hap = (struct HeaderArray *)&Header[Count];
+ if(IsLastPartition(Hap)!=XST_FAILURE)
+ break;
+ }
+
+ return Count;
+}
+
+/******************************************************************************/
+/**
+* This function check whether the current partition is the end of partitions
+*
+* The partition is the end of the partitions if it looks like this:
+* 0x00000000
+* 0x00000000
+* ....
+* 0x00000000
+* 0x00000000
+* 0xFFFFFFFF
+*
+* @param H is a pointer to struct HeaderArray
+*
+* @return
+* - XST_SUCCESS if it is the last partition
+* - XST_FAILURE if it is not last partition
+*
+****************************************************************************/
+u32 IsLastPartition(struct HeaderArray *H)
+{
+ int Index;
+
+ if (H->Fields[PARTITION_HDR_CHECKSUM_WORD_COUNT] != 0xFFFFFFFF) {
+ return XST_FAILURE;
+ }
+
+ for (Index = 0; Index < PARTITION_HDR_WORD_COUNT - 1; Index++) {
+
+ if (H->Fields[Index] != 0x0) {
+ return XST_FAILURE;
+ }
+ }
+
+ return XST_SUCCESS;
+}
+
+
+/******************************************************************************/
+/**
+*
+* This function validates the partition header.
+*
+* @param Header Partition header pointer
+*
+* @return
+* - XST_FAILURE if bad header.
+* - XST_SUCCESS if successful.
+*
+* @note None
+*
+*******************************************************************************/
+u32 ValidateHeader(PartHeader *Header)
+{
+ struct HeaderArray *Hap;
+
+ Hap = (struct HeaderArray *)Header;
+
+ /*
+ * If there are no partitions to load, fail
+ */
+ if (IsEmptyHeader(Hap) == XST_SUCCESS) {
+ fsbl_printf(DEBUG_GENERAL, "IMAGE_HAS_NO_PARTITIONS\r\n");
+ return XST_FAILURE;
+ }
+
+ /*
+ * Validate partition header checksum
+ */
+ if (ValidatePartitionHeaderChecksum(Hap) != XST_SUCCESS) {
+ fsbl_printf(DEBUG_GENERAL, "PARTITION_HEADER_CORRUPTION\r\n");
+ return XST_FAILURE;
+ }
+
+ /*
+ * Validate partition data size
+ */
+ if (Header->ImageWordLen > MAXIMUM_IMAGE_WORD_LEN) {
+ fsbl_printf(DEBUG_GENERAL, "INVALID_PARTITION_LENGTH\r\n");
+ return XST_FAILURE;
+ }
+
+ return XST_SUCCESS;
+}
+
+
+/******************************************************************************/
+/**
+* This function check whether the current partition header is empty.
+* A partition header is considered empty if image word length is 0 and the
+* last word is 0.
+*
+* @param H is a pointer to struct HeaderArray
+*
+* @return
+* - XST_SUCCESS , If the partition header is empty
+* - XST_FAILURE , If the partition header is NOT empty
+*
+* @note Caller is responsible to make sure the address is valid.
+*
+*
+****************************************************************************/
+u32 IsEmptyHeader(struct HeaderArray *H)
+{
+ int Index;
+
+ for (Index = 0; Index < PARTITION_HDR_WORD_COUNT; Index++) {
+ if (H->Fields[Index] != 0x0) {
+ return XST_FAILURE;
+ }
+ }
+
+ return XST_SUCCESS;
+}
+
+
+/******************************************************************************/
+/**
+*
+* This function checks the header checksum If the header checksum is not valid
+* XST_FAILURE is returned.
+*
+* @param H is a pointer to struct HeaderArray
+*
+* @return
+* - XST_SUCCESS is header checksum is ok
+* - XST_FAILURE if the header checksum is not correct
+*
+* @note None.
+*
+****************************************************************************/
+u32 ValidatePartitionHeaderChecksum(struct HeaderArray *H)
+{
+ u32 Checksum;
+ u32 Count;
+
+ Checksum = 0;
+
+ for (Count = 0; Count < PARTITION_HDR_CHECKSUM_WORD_COUNT; Count++) {
+ /*
+ * Read the word from the header
+ */
+ Checksum += H->Fields[Count];
+ }
+
+ /*
+ * Invert checksum, last bit of error checking
+ */
+ Checksum ^= 0xFFFFFFFF;
+
+ /*
+ * Validate the checksum
+ */
+ if (H->Fields[PARTITION_HDR_CHECKSUM_WORD_COUNT] != Checksum) {
+ fsbl_printf(DEBUG_GENERAL, "Error: Checksum 0x%8.8lx != 0x%8.8lx\r\n",
+ Checksum, H->Fields[PARTITION_HDR_CHECKSUM_WORD_COUNT]);
+ return XST_FAILURE;
+ }
+
+ return XST_SUCCESS;
+}
+
+
+/******************************************************************************/
+/**
+*
+* This function load the partition from boot device
+*
+* @param ImageBaseAddress Base address on flash
+* @param Header Partition header pointer
+*
+* @return
+* - XST_SUCCESS if partition move successful
+* - XST_FAILURE if check failed move failed
+*
+* @note None
+*
+*******************************************************************************/
+u32 PartitionMove(u32 ImageBaseAddress, PartHeader *Header)
+{
+ u32 SourceAddr;
+ u32 Status;
+ u8 SecureTransferFlag = 0;
+ u32 LoadAddr;
+ u32 ImageWordLen;
+ u32 DataWordLen;
+
+ SourceAddr = ImageBaseAddress;
+ SourceAddr += Header->PartitionStart<<WORD_LENGTH_SHIFT;
+ LoadAddr = Header->LoadAddr;
+ ImageWordLen = Header->ImageWordLen;
+ DataWordLen = Header->DataWordLen;
+
+ /*
+ * Add flash base address for linear boot devices
+ */
+ if (LinearBootDeviceFlag) {
+ SourceAddr += FlashReadBaseAddress;
+ }
+
+ /*
+ * Partition encrypted
+ */
+ if(EncryptedPartitionFlag) {
+ SecureTransferFlag = 1;
+ }
+
+ /*
+ * For Signed or checksum enabled partition,
+ * Total partition image need to copied to DDR
+ */
+ if (SignedPartitionFlag || PartitionChecksumFlag) {
+ ImageWordLen = Header->PartitionWordLen;
+ DataWordLen = Header->PartitionWordLen;
+ }
+
+ /*
+ * Encrypted and Signed PS partition need to be loaded on to DDR
+ * without decryption
+ */
+ if (PSPartitionFlag &&
+ (SignedPartitionFlag || PartitionChecksumFlag) &&
+ EncryptedPartitionFlag) {
+ SecureTransferFlag = 0;
+ }
+
+ /*
+ * CPU is used for data transfer in case of non-linear
+ * boot device
+ */
+ if (!LinearBootDeviceFlag) {
+ /*
+ * PL partition copied to DDR temporary location
+ */
+ if (PLPartitionFlag) {
+ LoadAddr = DDR_TEMP_START_ADDR;
+ }
+
+ Status = MoveImage(SourceAddr,
+ LoadAddr,
+ (ImageWordLen << WORD_LENGTH_SHIFT));
+ if(Status != XST_SUCCESS) {
+ fsbl_printf(DEBUG_GENERAL, "Move Image Failed\r\n");
+ return XST_FAILURE;
+ }
+
+ /*
+ * As image present at load address
+ */
+ SourceAddr = LoadAddr;
+ }
+
+ if ((LinearBootDeviceFlag && PLPartitionFlag &&
+ (SignedPartitionFlag || PartitionChecksumFlag)) ||
+ (LinearBootDeviceFlag && PSPartitionFlag) ||
+ ((!LinearBootDeviceFlag) && PSPartitionFlag && SecureTransferFlag)) {
+ /*
+ * PL signed partition copied to DDR temporary location
+ * using non-secure PCAP for linear boot device
+ */
+ if(PLPartitionFlag){
+ SecureTransferFlag = 0;
+ LoadAddr = DDR_TEMP_START_ADDR;
+ }
+
+ /*
+ * Data transfer using PCAP
+ */
+ Status = PcapDataTransfer((u32*)SourceAddr,
+ (u32*)LoadAddr,
+ ImageWordLen,
+ DataWordLen,
+ SecureTransferFlag);
+ if(Status != XST_SUCCESS) {
+ fsbl_printf(DEBUG_GENERAL, "PCAP Data Transfer Failed\r\n");
+ return XST_FAILURE;
+ }
+
+ /*
+ * As image present at load address
+ */
+ SourceAddr = LoadAddr;
+ }
+
+ /*
+ * Load Bitstream partition in to fabric only
+ * if checksum and authentication bits are not set
+ */
+ if (PLPartitionFlag && (!(SignedPartitionFlag || PartitionChecksumFlag))) {
+ Status = PcapLoadPartition((u32*)SourceAddr,
+ (u32*)Header->LoadAddr,
+ Header->ImageWordLen,
+ Header->DataWordLen,
+ EncryptedPartitionFlag);
+ if(Status != XST_SUCCESS) {
+ fsbl_printf(DEBUG_GENERAL, "PCAP Bitstream Download Failed\r\n");
+ return XST_FAILURE;
+ }
+ }
+
+ return XST_SUCCESS;
+}
+
+
+/******************************************************************************/
+/**
+*
+* This function load the decrypts partition
+*
+* @param StartAddr Source start address
+* @param DataLength Data length in words
+* @param ImageLength Image length in words
+*
+* @return
+* - XST_SUCCESS if decryption successful
+* - XST_FAILURE if decryption failed
+*
+* @note None
+*
+*******************************************************************************/
+u32 DecryptPartition(u32 StartAddr, u32 DataLength, u32 ImageLength)
+{
+ u32 Status;
+ u8 SecureTransferFlag =1;
+
+ /*
+ * Data transfer using PCAP
+ */
+ Status = PcapDataTransfer((u32*)StartAddr,
+ (u32*)StartAddr,
+ ImageLength,
+ DataLength,
+ SecureTransferFlag);
+ if (Status != XST_SUCCESS) {
+ fsbl_printf(DEBUG_GENERAL,"PCAP Data Transfer failed \r\n");
+ return XST_FAILURE;
+ }
+
+ return XST_SUCCESS;
+}
+
+/******************************************************************************/
+/**
+*
+* This function Validate Partition Data by using checksum preset in image
+*
+* @param Partition header pointer
+* @param Partition check sum offset
+* @return
+* - XST_SUCCESS if partition data is ok
+* - XST_FAILURE if partition data is corrupted
+*
+* @note None
+*
+*******************************************************************************/
+u32 ValidateParition(u32 StartAddr, u32 Length, u32 ChecksumOffset)
+{
+ u8 Checksum[MD5_CHECKSUM_SIZE];
+ u8 CalcChecksum[MD5_CHECKSUM_SIZE];
+ u32 Status;
+ u32 Index;
+
+#ifdef XPAR_XWDTPS_0_BASEADDR
+ /*
+ * Prevent WDT reset
+ */
+ XWdtPs_RestartWdt(&Watchdog);
+#endif
+
+ /*
+ * Get checksum from flash
+ */
+ Status = GetPartitionChecksum(ChecksumOffset, &Checksum[0]);
+ if(Status != XST_SUCCESS) {
+ return XST_FAILURE;
+ }
+
+ fsbl_printf(DEBUG_INFO, "Actual checksum\r\n");
+
+ for (Index = 0; Index < MD5_CHECKSUM_SIZE; Index++) {
+ fsbl_printf(DEBUG_INFO, "0x%0x ",Checksum[Index]);
+ }
+
+ fsbl_printf(DEBUG_INFO, "\r\n");
+
+ /*
+ * Calculate checksum for the partition
+ */
+ Status = CalcPartitionChecksum(StartAddr, Length, &CalcChecksum[0]);
+ if(Status != XST_SUCCESS) {
+ return XST_FAILURE;
+ }
+
+ fsbl_printf(DEBUG_INFO, "Calculated checksum\r\n");
+
+ for (Index = 0; Index < MD5_CHECKSUM_SIZE; Index++) {
+ fsbl_printf(DEBUG_INFO, "0x%0x ",CalcChecksum[Index]);
+ }
+
+ fsbl_printf(DEBUG_INFO, "\r\n");
+
+ /*
+ * Compare actual checksum with the calculated checksum
+ */
+ for (Index = 0; Index < MD5_CHECKSUM_SIZE; Index++) {
+ if(Checksum[Index] != CalcChecksum[Index]) {
+ fsbl_printf(DEBUG_GENERAL, "Error: "
+ "Partition DataChecksum 0x%0x!= 0x%0x\r\n",
+ Checksum[Index], CalcChecksum[Index]);
+ return XST_FAILURE;
+ }
+ }
+
+ return XST_SUCCESS;
+}
+
+
+/******************************************************************************/
+/**
+*
+* This function gets partition checksum from flash
+*
+* @param Check sum offset
+* @param Checksum pointer
+* @return
+* - XST_SUCCESS if checksum read success
+* - XST_FAILURE if unable get checksum
+*
+* @note None
+*
+*******************************************************************************/
+u32 GetPartitionChecksum(u32 ChecksumOffset, u8 *Checksum)
+{
+ u32 Status;
+
+ Status = MoveImage(ChecksumOffset, (u32)Checksum, MD5_CHECKSUM_SIZE);
+ if(Status != XST_SUCCESS) {
+ return XST_FAILURE;
+ }
+
+ return XST_SUCCESS;
+}
+
+
+/******************************************************************************/
+/**
+*
+* This function calculates the checksum preset in image
+*
+* @param Start address
+* @param Length of the data
+* @param Checksum pointer
+*
+* @return
+* - XST_SUCCESS if Checksum calculate successful
+* - XST_FAILURE if Checksum calculate failed
+*
+* @note None
+*
+*******************************************************************************/
+u32 CalcPartitionChecksum(u32 SourceAddr, u32 DataLength, u8 *Checksum)
+{
+ /*
+ * Calculate checksum using MD5 algorithm
+ */
+ md5((u8*)SourceAddr, DataLength, Checksum, 0 );
+
+ return XST_SUCCESS;
+}
+
diff --git a/hello_world/sw/fsbl/image_mover.h b/hello_world/sw/fsbl/image_mover.h
new file mode 100644
index 0000000..55f573f
--- /dev/null
+++ b/hello_world/sw/fsbl/image_mover.h
@@ -0,0 +1,155 @@
+/******************************************************************************
+*
+* Copyright (C) 2012 - 2014 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+* THE SOFTWARE.
+*
+*
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file image_mover.h
+*
+* This file contains the interface for moving the image from FLASH to OCM
+
+*
+* <pre>
+* MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ----- ---- -------- -------------------------------------------------------
+* 1.00a jz 03/04/11 Initial release
+* 2.00a jz 06/04/11 partition header expands to 12 words
+* 5.00a kc 07/30/13 Added defines for image header information
+* 8.00a kc 01/16/13 Added defines for partition owner attribute
+* </pre>
+*
+* @note
+*
+******************************************************************************/
+#ifndef ___IMAGE_MOVER_H___
+#define ___IMAGE_MOVER_H___
+
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/***************************** Include Files *********************************/
+#include "fsbl.h"
+
+/************************** Constant Definitions *****************************/
+#define PARTITION_NUMBER_SHIFT 24
+#define MAX_PARTITION_NUMBER (0xE)
+
+/* Boot Image Header defines */
+#define IMAGE_HDR_OFFSET 0x098 /* Start of image header table */
+#define IMAGE_PHDR_OFFSET 0x09C /* Start of partition headers */
+#define IMAGE_HEADER_SIZE (64)
+#define IMAGE_HEADER_TABLE_SIZE (64)
+#define TOTAL_PARTITION_HEADER_SIZE (MAX_PARTITION_NUMBER * IMAGE_HEADER_SIZE)
+#define TOTAL_IMAGE_HEADER_SIZE (MAX_PARTITION_NUMBER * IMAGE_HEADER_SIZE)
+#define TOTAL_HEADER_SIZE (IMAGE_HEADER_TABLE_SIZE + \
+ TOTAL_IMAGE_HEADER_SIZE + \
+ TOTAL_PARTITION_HEADER_SIZE + 64)
+
+/* Partition Header defines */
+#define PARTITION_IMAGE_WORD_LEN_OFFSET 0x00 /* Word length of image */
+#define PARTITION_DATA_WORD_LEN_OFFSET 0x04 /* Word length of data */
+#define PARTITION_WORD_LEN_OFFSET 0x08 /* Word length of partition */
+#define PARTITION_LOAD_ADDRESS_OFFSET 0x0C /* Load addr in DDR */
+#define PARTITION_EXEC_ADDRESS_OFFSET 0x10 /* Addr to start executing */
+#define PARTITION_ADDR_OFFSET 0x14 /* Partition word offset */
+#define PARTITION_ATTRIBUTE_OFFSET 0x18 /* Partition type */
+#define PARTITION_HDR_CHECKSUM_OFFSET 0x3C /* Header Checksum offset */
+#define PARTITION_HDR_CHECKSUM_WORD_COUNT 0xF /* Checksum word count */
+#define PARTITION_HDR_WORD_COUNT 0x10 /* Header word len */
+#define PARTITION_HDR_TOTAL_LEN 0x40 /* One partition hdr length*/
+
+/* Attribute word defines */
+#define ATTRIBUTE_IMAGE_TYPE_MASK 0xF0 /* Destination Device type */
+#define ATTRIBUTE_PS_IMAGE_MASK 0x10 /* Code partition */
+#define ATTRIBUTE_PL_IMAGE_MASK 0x20 /* Bit stream partition */
+#define ATTRIBUTE_CHECKSUM_TYPE_MASK 0x7000 /* Checksum Type */
+#define ATTRIBUTE_RSA_PRESENT_MASK 0x8000 /* RSA Signature Present */
+#define ATTRIBUTE_PARTITION_OWNER_MASK 0x30000 /* Partition Owner */
+
+#define ATTRIBUTE_PARTITION_OWNER_FSBL 0x00000 /* FSBL Partition Owner */
+
+
+/**************************** Type Definitions *******************************/
+typedef u32 (*ImageMoverType)( u32 SourceAddress,
+ u32 DestinationAddress,
+ u32 LengthBytes);
+
+typedef struct StructPartHeader {
+ u32 ImageWordLen; /* 0x0 */
+ u32 DataWordLen; /* 0x4 */
+ u32 PartitionWordLen; /* 0x8 */
+ u32 LoadAddr; /* 0xC */
+ u32 ExecAddr; /* 0x10 */
+ u32 PartitionStart; /* 0x14 */
+ u32 PartitionAttr; /* 0x18 */
+ u32 SectionCount; /* 0x1C */
+ u32 CheckSumOffset; /* 0x20 */
+ u32 Pads1[1];
+ u32 ACOffset; /* 0x28 */
+ u32 Pads2[4];
+ u32 CheckSum; /* 0x3C */
+}PartHeader;
+
+struct HeaderArray {
+ u32 Fields[16];
+};
+
+
+/***************** Macros (Inline Functions) Definitions *********************/
+#define MoverIn32 Xil_In32
+#define MoverOut32 Xil_Out32
+
+/************************** Function Prototypes ******************************/
+u32 LoadBootImage(void);
+u32 GetPartitionHeaderInfo(u32 ImageBaseAddress);
+u32 PartitionMove(u32 ImageBaseAddress, PartHeader *Header);
+u32 ValidatePartitionHeaderChecksum(struct HeaderArray *H);
+u32 GetPartitionHeaderStartAddr(u32 ImageAddress, u32 *Offset);
+u32 GetImageHeaderAndSignature(u32 ImageAddress, u32 *Offset);
+u32 GetFsblLength(u32 ImageAddress, u32 *FsblLength);
+u32 LoadPartitionsHeaderInfo(u32 PartHeaderOffset, PartHeader *Header);
+u32 IsEmptyHeader(struct HeaderArray *H);
+u32 IsLastPartition(struct HeaderArray *H);
+void HeaderDump(PartHeader *Header);
+u32 GetPartitionCount(PartHeader *Header);
+u32 ValidateHeader(PartHeader *Header);
+u32 DecryptPartition(u32 StartAddr, u32 DataLength, u32 ImageLength);
+
+/************************** Variable Definitions *****************************/
+
+#ifdef __cplusplus
+}
+#endif
+
+
+#endif /* ___IMAGE_MOVER_H___ */
+
+
+
+
diff --git a/hello_world/sw/fsbl/lscript.ld b/hello_world/sw/fsbl/lscript.ld
new file mode 100644
index 0000000..ff8a106
--- /dev/null
+++ b/hello_world/sw/fsbl/lscript.ld
@@ -0,0 +1,307 @@
+/******************************************************************************
+*
+* Copyright (C) 2012 - 2014 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+* THE SOFTWARE.
+*
+*
+*
+******************************************************************************/
+
+_STACK_SIZE = DEFINED(_STACK_SIZE) ? _STACK_SIZE : 0x6000;
+_HEAP_SIZE = DEFINED(_HEAP_SIZE) ? _HEAP_SIZE : 0x2000;
+
+_RSA_AC_SIZE = DEFINED(_RSA_AC_SIZE) ? _RSA_AC_SIZE : 0x1000;
+
+_ABORT_STACK_SIZE = DEFINED(_ABORT_STACK_SIZE) ? _ABORT_STACK_SIZE : 1024;
+_SUPERVISOR_STACK_SIZE = DEFINED(_SUPERVISOR_STACK_SIZE) ? _SUPERVISOR_STACK_SIZE : 2048;
+_FIQ_STACK_SIZE = DEFINED(_FIQ_STACK_SIZE) ? _FIQ_STACK_SIZE : 1024;
+_UNDEF_STACK_SIZE = DEFINED(_UNDEF_STACK_SIZE) ? _UNDEF_STACK_SIZE : 1024;
+
+/* Define Memories in the system */
+
+MEMORY
+{
+ ps7_ram_0_S_AXI_BASEADDR : ORIGIN = 0x00000000, LENGTH = 0x00030000
+ ps7_ram_1_S_AXI_BASEADDR : ORIGIN = 0xFFFF0000, LENGTH = 0x0000FE00
+}
+
+/* Specify the default entry point to the program */
+
+ENTRY(_vector_table)
+
+
+SECTIONS
+{
+.text : {
+ *(.vectors)
+ *(.boot)
+ *(.text)
+ *(.text.*)
+ *(.gnu.linkonce.t.*)
+ *(.plt)
+ *(.gnu_warning)
+ *(.gcc_execpt_table)
+ *(.glue_7)
+ *(.glue_7t)
+ *(.vfp11_veneer)
+ *(.ARM.extab)
+ *(.gnu.linkonce.armextab.*)
+} > ps7_ram_0_S_AXI_BASEADDR
+
+.init : {
+ KEEP (*(.init))
+} > ps7_ram_0_S_AXI_BASEADDR
+
+.fini : {
+ KEEP (*(.fini))
+} > ps7_ram_0_S_AXI_BASEADDR
+
+.rodata : {
+ __rodata_start = .;
+ *(.rodata)
+ *(.rodata.*)
+ *(.gnu.linkonce.r.*)
+ __rodata_end = .;
+} > ps7_ram_0_S_AXI_BASEADDR
+
+.rodata1 : {
+ __rodata1_start = .;
+ *(.rodata1)
+ *(.rodata1.*)
+ __rodata1_end = .;
+} > ps7_ram_0_S_AXI_BASEADDR
+
+.sdata2 : {
+ __sdata2_start = .;
+ *(.sdata2)
+ *(.sdata2.*)
+ *(.gnu.linkonce.s2.*)
+ __sdata2_end = .;
+} > ps7_ram_0_S_AXI_BASEADDR
+
+.sbss2 : {
+ __sbss2_start = .;
+ *(.sbss2)
+ *(.sbss2.*)
+ *(.gnu.linkonce.sb2.*)
+ __sbss2_end = .;
+} > ps7_ram_0_S_AXI_BASEADDR
+
+.data : {
+ __data_start = .;
+ *(.data)
+ *(.data.*)
+ *(.gnu.linkonce.d.*)
+ *(.jcr)
+ *(.got)
+ *(.got.plt)
+ __data_end = .;
+} > ps7_ram_0_S_AXI_BASEADDR
+
+.data1 : {
+ __data1_start = .;
+ *(.data1)
+ *(.data1.*)
+ __data1_end = .;
+} > ps7_ram_0_S_AXI_BASEADDR
+
+.got : {
+ *(.got)
+} > ps7_ram_0_S_AXI_BASEADDR
+
+.ctors : {
+ __CTOR_LIST__ = .;
+ ___CTORS_LIST___ = .;
+ KEEP (*crtbegin.o(.ctors))
+ KEEP (*(EXCLUDE_FILE(*crtend.o) .ctors))
+ KEEP (*(SORT(.ctors.*)))
+ KEEP (*(.ctors))
+ __CTOR_END__ = .;
+ ___CTORS_END___ = .;
+} > ps7_ram_0_S_AXI_BASEADDR
+
+.dtors : {
+ __DTOR_LIST__ = .;
+ ___DTORS_LIST___ = .;
+ KEEP (*crtbegin.o(.dtors))
+ KEEP (*(EXCLUDE_FILE(*crtend.o) .dtors))
+ KEEP (*(SORT(.dtors.*)))
+ KEEP (*(.dtors))
+ __DTOR_END__ = .;
+ ___DTORS_END___ = .;
+} > ps7_ram_0_S_AXI_BASEADDR
+
+.fixup : {
+ __fixup_start = .;
+ *(.fixup)
+ __fixup_end = .;
+} > ps7_ram_0_S_AXI_BASEADDR
+
+.eh_frame : {
+ *(.eh_frame)
+} > ps7_ram_0_S_AXI_BASEADDR
+
+.eh_framehdr : {
+ __eh_framehdr_start = .;
+ *(.eh_framehdr)
+ __eh_framehdr_end = .;
+} > ps7_ram_0_S_AXI_BASEADDR
+
+.gcc_except_table : {
+ *(.gcc_except_table)
+} > ps7_ram_0_S_AXI_BASEADDR
+
+.mmu_tbl (ALIGN(0x4000)): {
+ __mmu_tbl_start = .;
+ *(.mmu_tbl)
+ __mmu_tbl_end = .;
+} > ps7_ram_0_S_AXI_BASEADDR
+
+.ARM.exidx : {
+ __exidx_start = .;
+ *(.ARM.exidx*)
+ *(.gnu.linkonce.armexidix.*.*)
+ __exidx_end = .;
+} > ps7_ram_0_S_AXI_BASEADDR
+
+.preinit_array : {
+ __preinit_array_start = .;
+ KEEP (*(SORT(.preinit_array.*)))
+ KEEP (*(.preinit_array))
+ __preinit_array_end = .;
+} > ps7_ram_0_S_AXI_BASEADDR
+
+.init_array : {
+ __init_array_start = .;
+ KEEP (*(SORT(.init_array.*)))
+ KEEP (*(.init_array))
+ __init_array_end = .;
+} > ps7_ram_0_S_AXI_BASEADDR
+
+.fini_array : {
+ __fini_array_start = .;
+ KEEP (*(SORT(.fini_array.*)))
+ KEEP (*(.fini_array))
+ __fini_array_end = .;
+} > ps7_ram_0_S_AXI_BASEADDR
+
+.rsa_ac : {
+ . = ALIGN(64);
+ __rsa_ac_start = .;
+ . += _RSA_AC_SIZE;
+ __rsa_ac_end = .;
+} > ps7_ram_0_S_AXI_BASEADDR
+
+.ARM.attributes : {
+ __ARM.attributes_start = .;
+ *(.ARM.attributes)
+ __ARM.attributes_end = .;
+} > ps7_ram_0_S_AXI_BASEADDR
+
+.sdata : {
+ __sdata_start = .;
+ *(.sdata)
+ *(.sdata.*)
+ *(.gnu.linkonce.s.*)
+ __sdata_end = .;
+} > ps7_ram_0_S_AXI_BASEADDR
+
+.sbss (NOLOAD) : {
+ __sbss_start = .;
+ *(.sbss)
+ *(.sbss.*)
+ *(.gnu.linkonce.sb.*)
+ __sbss_end = .;
+} > ps7_ram_0_S_AXI_BASEADDR
+
+.tdata : {
+ __tdata_start = .;
+ *(.tdata)
+ *(.tdata.*)
+ *(.gnu.linkonce.td.*)
+ __tdata_end = .;
+} > ps7_ram_0_S_AXI_BASEADDR
+
+.tbss : {
+ __tbss_start = .;
+ *(.tbss)
+ *(.tbss.*)
+ *(.gnu.linkonce.tb.*)
+ __tbss_end = .;
+} > ps7_ram_0_S_AXI_BASEADDR
+
+.bss (NOLOAD) : {
+ __bss_start = .;
+ __bss_start__ = .;
+ *(.bss)
+ *(.bss.*)
+ *(.gnu.linkonce.b.*)
+ *(COMMON)
+ __bss_end = .;
+ __bss_end__ = .;
+} > ps7_ram_0_S_AXI_BASEADDR
+
+_SDA_BASE_ = __sdata_start + ((__sbss_end - __sdata_start) / 2 );
+
+_SDA2_BASE_ = __sdata2_start + ((__sbss2_end - __sdata2_start) / 2 );
+
+/* Generate Stack and Heap definitions */
+
+.heap (NOLOAD) : {
+ . = ALIGN(16);
+ _heap = .;
+ HeapBase = .;
+ _heap_start = .;
+ . += _HEAP_SIZE;
+ _heap_end = .;
+ HeapLimit = .;
+} > ps7_ram_0_S_AXI_BASEADDR
+
+.stack (NOLOAD) : {
+ . = ALIGN(16);
+ _stack_end = .;
+ . += _STACK_SIZE;
+ _stack = .;
+ __stack = _stack;
+ . = ALIGN(16);
+ _irq_stack_end = .;
+ . += _STACK_SIZE;
+ __irq_stack = .;
+ _supervisor_stack_end = .;
+ . += _SUPERVISOR_STACK_SIZE;
+ . = ALIGN(16);
+ __supervisor_stack = .;
+ _abort_stack_end = .;
+ . += _ABORT_STACK_SIZE;
+ . = ALIGN(16);
+ __abort_stack = .;
+ _fiq_stack_end = .;
+ . += _FIQ_STACK_SIZE;
+ . = ALIGN(16);
+ __fiq_stack = .;
+ _undef_stack_end = .;
+ . += _UNDEF_STACK_SIZE;
+ . = ALIGN(16);
+ __undef_stack = .;
+} > ps7_ram_1_S_AXI_BASEADDR
+
+_end = .;
+}
+
diff --git a/hello_world/sw/fsbl/main.c b/hello_world/sw/fsbl/main.c
new file mode 100644
index 0000000..43b5ce1
--- /dev/null
+++ b/hello_world/sw/fsbl/main.c
@@ -0,0 +1,1541 @@
+/******************************************************************************
+*
+* Copyright (C) 2012 - 2018 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+* THE SOFTWARE.
+*
+*
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file main.c
+*
+* The main file for the First Stage Boot Loader (FSBL).
+*
+* <pre>
+* MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ----- ---- -------- -------------------------------------------------------
+* 1.00a jz 06/04/11 Initial release
+* 2.00a mb 25/05/12 standalone based FSBL
+* 3.00a np/mb 08/03/12 Added call to FSBL user hook - before handoff.
+* DDR ECC initialization added
+* fsbl print with verbose added
+* Performance measurement added
+* Flushed the UART Tx buffer
+* Added the performance time for ECC DDR init
+* Added clearing of ECC Error Code
+* Added the watchdog timer value
+* 4.00a sgd 02/28/13 Code Cleanup
+* Fix for CR#681014 - ECC init in FSBL should not
+* call fabric_init()
+* Fix for CR#689077 - FSBL hangs at Handoff clearing the
+* TX UART buffer when using UART0
+* instead of UART1
+* Fix for CR#694038 - FSBL debug logs always prints 14.3
+* as the Revision number - this is
+* incorrect
+* Fix for CR#694039 - FSBL prints "unsupported silicon
+* version for v3.0" 3.0 Silicon
+* Fix for CR#699475 - FSBL functionality is broken and
+* its not able to boot in QSPI/NAND
+* bootmode
+* Removed DDR initialization check
+* Removed DDR ECC initialization code
+* Modified hand off address check to 1MB
+* Added RSA authentication support
+* Watchdog disabled for AES E-Fuse encryption
+* 5.00a sgd 05/17/13 Fallback support for E-Fuse encryption
+* Fix for CR#708728 - Issues seen while making HP
+* interconnect 32 bit wide
+* 6.00a kc 07/30/13 Fix for CR#708316 - PS7_init.tcl file should have
+* Error mechanism for all mask_poll
+* Fix for CR#691150 - ps7_init does not check for
+* peripheral initialization failures
+* or timeout on polls
+* Fix for CR#724165 - Partition Header used by FSBL is
+* not authenticated
+* Fix for CR#724166 - FSBL doesn’t use PPK authenticated
+* by Boot ROM for authenticating
+* the Partition images
+* Fix for CR#722979 - Provide customer-friendly
+* changelogs in FSBL
+* Fix for CR#732865 - Backward compatibility for ps7_init
+* function
+* 7.00a kc 10/18/13 Integrated SD/MMC driver
+* 8.00a kc 02/20/14 Fix for CR#775631 - FSBL: FsblGetGlobalTimer()
+* is not proper
+* 9.00a kc 04/16/14 Fix for CR#724166 - SetPpk() will fail on secure
+* fallback unless FSBL* and FSBL
+* are identical in length
+* 10.00a kc 07/24/14 Fix for CR#809336 - Minor code cleanup
+* kc 08/27/14 Fix for CR#820356 - FSBL compilation fails with
+* IAR compiler
+* 11.00a kv 10/08/14 Fix for CR#826030 - LinearBootDeviceFlag should
+* be initialized to 0 in IO mode
+* case
+* 15.00a gan 07/21/16 Fix for CR# 953654 -(2016.3)FSBL -
+* In pcap.c/pcap.h/main.c,
+* Fabric Initialization sequence
+* is modified to check the PL power
+* before sequence starts and checking
+* INIT_B reset status twice in case
+* of failure.
+* 16.00a bsv 03/26/18 Fix for CR# 996973 Add code under JTAG_ENABLE_LEVEL_SHIFTERS macro
+* to enable level shifters in jtag boot mode.
+* </pre>
+*
+* @note
+* FSBL runs from OCM, Based on the boot mode selected, FSBL will copy
+* the partitions from the flash device. If the partition is bitstream then
+* the bitstream is programmed in the Fabric and for an partition that is
+* an application , FSBL will copy the application into DDR and does a
+* handoff.The application should not be starting at the OCM address,
+* FSBL does not remap the DDR. Application should use DDR starting from 1MB
+*
+* FSBL can be stitched along with bitstream and application using bootgen
+*
+* Refer to fsbl.h file for details on the compilation flags supported in FSBL
+*
+******************************************************************************/
+
+/***************************** Include Files *********************************/
+
+#include "fsbl.h"
+#include "qspi.h"
+#include "nand.h"
+#include "nor.h"
+#include "sd.h"
+#include "pcap.h"
+#include "image_mover.h"
+#include "xparameters.h"
+#include "xil_cache.h"
+#include "xil_exception.h"
+#include "xstatus.h"
+#include "fsbl_hooks.h"
+#include "xtime_l.h"
+
+#ifdef XPAR_XWDTPS_0_BASEADDR
+#include "xwdtps.h"
+#endif
+
+#ifdef STDOUT_BASEADDRESS
+#ifdef XPAR_XUARTPS_0_BASEADDR
+#include "xuartps_hw.h"
+#endif
+#endif
+
+#ifdef RSA_SUPPORT
+#include "rsa.h"
+#endif
+
+/************************** Constant Definitions *****************************/
+
+#ifdef XPAR_XWDTPS_0_BASEADDR
+#define WDT_DEVICE_ID XPAR_XWDTPS_0_DEVICE_ID
+#define WDT_EXPIRE_TIME 100
+#define WDT_CRV_SHIFT 12
+#endif
+
+/**************************** Type Definitions *******************************/
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+#ifdef XPAR_XWDTPS_0_BASEADDR
+XWdtPs Watchdog; /* Instance of WatchDog Timer */
+#endif
+/************************** Function Prototypes ******************************/
+extern int ps7_init();
+extern char* getPS7MessageInfo(unsigned key);
+#ifdef PS7_POST_CONFIG
+extern int ps7_post_config();
+#endif
+
+static void Update_MultiBootRegister(void);
+/* Exception handlers */
+static void RegisterHandlers(void);
+static void Undef_Handler (void);
+static void SVC_Handler (void);
+static void PreFetch_Abort_Handler (void);
+static void Data_Abort_Handler (void);
+static void IRQ_Handler (void);
+static void FIQ_Handler (void);
+
+
+#ifdef XPAR_XWDTPS_0_BASEADDR
+int InitWatchDog(void);
+u32 ConvertTime_WdtCounter(u32 seconds);
+void CheckWDTReset(void);
+#endif
+
+u32 NextValidImageCheck(void);
+
+u32 DDRInitCheck(void);
+
+/************************** Variable Definitions *****************************/
+/*
+ * Base Address for the Read Functionality for Image Processing
+ */
+u32 FlashReadBaseAddress = 0;
+/*
+ * Silicon Version
+ */
+u32 Silicon_Version;
+
+/*
+ * Boot Device flag
+ */
+u8 LinearBootDeviceFlag=0;
+
+u32 PcapCtrlRegVal;
+
+u8 SystemInitFlag;
+
+extern ImageMoverType MoveImage;
+extern XDcfg *DcfgInstPtr;
+extern u8 BitstreamFlag;
+#ifdef XPAR_PS7_QSPI_LINEAR_0_S_AXI_BASEADDR
+extern u32 QspiFlashSize;
+#endif
+/*****************************************************************************/
+/**
+*
+* This is the main function for the FSBL ROM code.
+*
+*
+* @param None.
+*
+* @return
+* - XST_SUCCESS to indicate success
+* - XST_FAILURE.to indicate failure
+*
+* @note
+*
+****************************************************************************/
+int main(void)
+{
+ u32 BootModeRegister = 0;
+ u32 HandoffAddress = 0;
+ u32 Status = XST_SUCCESS;
+ u32 RegVal;
+ /*
+ * PCW initialization for MIO,PLL,CLK and DDR
+ */
+ Status = ps7_init();
+ if (Status != FSBL_PS7_INIT_SUCCESS) {
+ fsbl_printf(DEBUG_GENERAL,"PS7_INIT_FAIL : %s\r\n",
+ getPS7MessageInfo(Status));
+ OutputStatus(PS7_INIT_FAIL);
+ /*
+ * Calling FsblHookFallback instead of Fallback
+ * since, devcfg driver is not yet initialized
+ */
+ FsblHookFallback();
+ }
+
+ /*
+ * Unlock SLCR for SLCR register write
+ */
+ SlcrUnlock();
+
+ /* If Performance measurement is required
+ * then read the Global Timer value , Please note that the
+ * time taken for mio, clock and ddr initialisation
+ * done in the ps7_init function is not accounted in the FSBL
+ *
+ */
+#ifdef FSBL_PERF
+ XTime tCur = 0;
+ FsblGetGlobalTime(&tCur);
+#endif
+
+ /*
+ * Flush the Caches
+ */
+ Xil_DCacheFlush();
+
+ /*
+ * Disable Data Cache
+ */
+ Xil_DCacheDisable();
+
+ /*
+ * Register the Exception handlers
+ */
+ RegisterHandlers();
+
+ /*
+ * Print the FSBL Banner
+ */
+ fsbl_printf(DEBUG_GENERAL,"\n\rXilinx First Stage Boot Loader \n\r");
+ fsbl_printf(DEBUG_GENERAL,"Release %d.%d %s-%s\r\n",
+ SDK_RELEASE_YEAR, SDK_RELEASE_QUARTER,
+ __DATE__,__TIME__);
+
+#ifdef XPAR_PS7_DDR_0_S_AXI_BASEADDR
+
+ /*
+ * DDR Read/write test
+ */
+ Status = DDRInitCheck();
+ if (Status == XST_FAILURE) {
+ fsbl_printf(DEBUG_GENERAL,"DDR_INIT_FAIL \r\n");
+ /* Error Handling here */
+ OutputStatus(DDR_INIT_FAIL);
+ /*
+ * Calling FsblHookFallback instead of Fallback
+ * since, devcfg driver is not yet initialized
+ */
+ FsblHookFallback();
+ }
+
+
+ /*
+ * PCAP initialization
+ */
+ Status = InitPcap();
+ if (Status == XST_FAILURE) {
+ fsbl_printf(DEBUG_GENERAL,"PCAP_INIT_FAIL \n\r");
+ OutputStatus(PCAP_INIT_FAIL);
+ /*
+ * Calling FsblHookFallback instead of Fallback
+ * since, devcfg driver is not yet initialized
+ */
+ FsblHookFallback();
+ }
+
+ fsbl_printf(DEBUG_INFO,"Devcfg driver initialized \r\n");
+
+ /*
+ * Get the Silicon Version
+ */
+ GetSiliconVersion();
+
+#ifdef XPAR_XWDTPS_0_BASEADDR
+ /*
+ * Check if WDT Reset has occurred or not
+ */
+ CheckWDTReset();
+
+ /*
+ * Initialize the Watchdog Timer so that it is ready to use
+ */
+ Status = InitWatchDog();
+ if (Status == XST_FAILURE) {
+ fsbl_printf(DEBUG_GENERAL,"WATCHDOG_INIT_FAIL \n\r");
+ OutputStatus(WDT_INIT_FAIL);
+ FsblFallback();
+ }
+ fsbl_printf(DEBUG_INFO,"Watchdog driver initialized \r\n");
+#endif
+
+ /*
+ * Get PCAP controller settings
+ */
+ PcapCtrlRegVal = XDcfg_GetControlRegister(DcfgInstPtr);
+
+ /*
+ * Check for AES source key
+ */
+ if (PcapCtrlRegVal & XDCFG_CTRL_PCFG_AES_FUSE_MASK) {
+ /*
+ * For E-Fuse AES encryption Watch dog Timer disabled and
+ * User not allowed to do system reset
+ */
+#ifdef XPAR_XWDTPS_0_BASEADDR
+ fsbl_printf(DEBUG_INFO,"Watchdog Timer Disabled\r\n");
+ XWdtPs_Stop(&Watchdog);
+#endif
+ fsbl_printf(DEBUG_INFO,"User not allowed to do "
+ "any system resets\r\n");
+ }
+
+ /*
+ * Store FSBL run state in Reboot Status Register
+ */
+ MarkFSBLIn();
+
+ /*
+ * Read bootmode register
+ */
+ BootModeRegister = Xil_In32(BOOT_MODE_REG);
+ BootModeRegister &= BOOT_MODES_MASK;
+
+ /*
+ * QSPI BOOT MODE
+ */
+#ifdef XPAR_PS7_QSPI_LINEAR_0_S_AXI_BASEADDR
+
+#ifdef MMC_SUPPORT
+ /*
+ * To support MMC boot
+ * QSPI boot mode detection ignored
+ */
+ if (BootModeRegister == QSPI_MODE) {
+ BootModeRegister = MMC_MODE;
+ }
+#endif
+
+ if (BootModeRegister == QSPI_MODE) {
+ fsbl_printf(DEBUG_GENERAL,"Boot mode is QSPI\n\r");
+ InitQspi();
+ MoveImage = QspiAccess;
+ fsbl_printf(DEBUG_INFO,"QSPI Init Done \r\n");
+ } else
+#endif
+
+ /*
+ * NAND BOOT MODE
+ */
+#ifdef XPAR_PS7_NAND_0_BASEADDR
+ if (BootModeRegister == NAND_FLASH_MODE) {
+ /*
+ * Boot ROM always initialize the nand at lower speed
+ * This is the chance to put it to an optimum speed for your nand
+ * device
+ */
+ fsbl_printf(DEBUG_GENERAL,"Boot mode is NAND\n");
+
+ Status = InitNand();
+ if (Status != XST_SUCCESS) {
+ fsbl_printf(DEBUG_GENERAL,"NAND_INIT_FAIL \r\n");
+ /*
+ * Error Handling here
+ */
+ OutputStatus(NAND_INIT_FAIL);
+ FsblFallback();
+ }
+ MoveImage = NandAccess;
+ fsbl_printf(DEBUG_INFO,"NAND Init Done \r\n");
+ } else
+#endif
+
+ /*
+ * NOR BOOT MODE
+ */
+ if (BootModeRegister == NOR_FLASH_MODE) {
+ fsbl_printf(DEBUG_GENERAL,"Boot mode is NOR\n\r");
+ /*
+ * Boot ROM always initialize the nor at lower speed
+ * This is the chance to put it to an optimum speed for your nor
+ * device
+ */
+ InitNor();
+ fsbl_printf(DEBUG_INFO,"NOR Init Done \r\n");
+ MoveImage = NorAccess;
+ } else
+
+ /*
+ * SD BOOT MODE
+ */
+#if defined(XPAR_PS7_SD_0_S_AXI_BASEADDR) || defined(XPAR_XSDPS_0_BASEADDR)
+
+ if (BootModeRegister == SD_MODE) {
+ fsbl_printf(DEBUG_GENERAL,"Boot mode is SD\r\n");
+
+ /*
+ * SD initialization returns file open error or success
+ */
+ Status = InitSD("BOOT.BIN");
+ if (Status != XST_SUCCESS) {
+ fsbl_printf(DEBUG_GENERAL,"SD_INIT_FAIL\r\n");
+ OutputStatus(SD_INIT_FAIL);
+ FsblFallback();
+ }
+ MoveImage = SDAccess;
+ fsbl_printf(DEBUG_INFO,"SD Init Done \r\n");
+ } else
+
+ if (BootModeRegister == MMC_MODE) {
+ fsbl_printf(DEBUG_GENERAL,"Booting Device is MMC\r\n");
+
+ /*
+ * MMC initialization returns file open error or success
+ */
+ Status = InitSD("BOOT.BIN");
+ if (Status != XST_SUCCESS) {
+ fsbl_printf(DEBUG_GENERAL,"MMC_INIT_FAIL\r\n");
+ OutputStatus(SD_INIT_FAIL);
+ FsblFallback();
+ }
+ MoveImage = SDAccess;
+ fsbl_printf(DEBUG_INFO,"MMC Init Done \r\n");
+ } else
+
+#endif
+
+ /*
+ * JTAG BOOT MODE
+ */
+ if (BootModeRegister == JTAG_MODE) {
+ fsbl_printf(DEBUG_GENERAL,"Boot mode is JTAG\r\n");
+
+ RegVal = Xil_In32(XPS_DEV_CFG_APB_BASEADDR + XDCFG_INT_STS_OFFSET);
+ /** If bitstream was loaded in jtag boot mode prior to running FSBL */
+ if(RegVal & XDCFG_IXR_PCFG_DONE_MASK)
+ {
+#ifdef PS7_POST_CONFIG
+ ps7_post_config();
+ /*
+ * Unlock SLCR for SLCR register write
+ */
+ SlcrUnlock();
+#endif
+ }
+ /*
+ * Stop the Watchdog before JTAG handoff
+ */
+#ifdef XPAR_XWDTPS_0_BASEADDR
+ XWdtPs_Stop(&Watchdog);
+#endif
+ /*
+ * Clear our mark in reboot status register
+ */
+ ClearFSBLIn();
+
+ /*
+ * SLCR lock
+ */
+ SlcrLock();
+
+ FsblHandoffJtagExit();
+ } else {
+ fsbl_printf(DEBUG_GENERAL,"ILLEGAL_BOOT_MODE \r\n");
+ OutputStatus(ILLEGAL_BOOT_MODE);
+ /*
+ * fallback starts, no return
+ */
+ FsblFallback();
+ }
+
+ fsbl_printf(DEBUG_INFO,"Flash Base Address: 0x%08lx\r\n", FlashReadBaseAddress);
+
+ /*
+ * Check for valid flash address
+ */
+ if ((FlashReadBaseAddress != XPS_QSPI_LINEAR_BASEADDR) &&
+ (FlashReadBaseAddress != XPS_NAND_BASEADDR) &&
+ (FlashReadBaseAddress != XPS_NOR_BASEADDR) &&
+ (FlashReadBaseAddress != XPS_SDIO0_BASEADDR)) {
+ fsbl_printf(DEBUG_GENERAL,"INVALID_FLASH_ADDRESS \r\n");
+ OutputStatus(INVALID_FLASH_ADDRESS);
+ FsblFallback();
+ }
+
+ /*
+ * NOR and QSPI (parallel) are linear boot devices
+ */
+ if ((FlashReadBaseAddress == XPS_NOR_BASEADDR)) {
+ fsbl_printf(DEBUG_INFO, "Linear Boot Device\r\n");
+ LinearBootDeviceFlag = 1;
+ }
+
+#ifdef XPAR_XWDTPS_0_BASEADDR
+ /*
+ * Prevent WDT reset
+ */
+ XWdtPs_RestartWdt(&Watchdog);
+#endif
+
+ /*
+ * This used only in case of E-Fuse encryption
+ * For image search
+ */
+ SystemInitFlag = 1;
+
+ /*
+ * Load boot image
+ */
+ HandoffAddress = LoadBootImage();
+
+ fsbl_printf(DEBUG_INFO,"Handoff Address: 0x%08lx\r\n",HandoffAddress);
+
+ /*
+ * For Performance measurement
+ */
+#ifdef FSBL_PERF
+ XTime tEnd = 0;
+ fsbl_printf(DEBUG_GENERAL,"Total Execution time is ");
+ FsblMeasurePerfTime(tCur,tEnd);
+#endif
+
+ /*
+ * FSBL handoff to valid handoff address or
+ * exit in JTAG
+ */
+ FsblHandoff(HandoffAddress);
+
+#else
+ OutputStatus(NO_DDR);
+ FsblFallback();
+#endif
+
+ return Status;
+}
+
+/******************************************************************************/
+/**
+*
+* This function reset the CPU and goes for Boot ROM fallback handling
+*
+* @param None
+*
+* @return None
+*
+* @note None
+*
+****************************************************************************/
+void FsblFallback(void)
+{
+ u32 RebootStatusReg;
+ u32 Status;
+ u32 HandoffAddr;
+ u32 BootModeRegister;
+
+ /*
+ * Read bootmode register
+ */
+ BootModeRegister = Xil_In32(BOOT_MODE_REG);
+ BootModeRegister &= BOOT_MODES_MASK;
+
+ /*
+ * Fallback support check
+ */
+ if (!((BootModeRegister == QSPI_MODE) ||
+ (BootModeRegister == NAND_FLASH_MODE) ||
+ (BootModeRegister == NOR_FLASH_MODE))) {
+ fsbl_printf(DEBUG_INFO,"\r\n"
+ "This Boot Mode Doesn't Support Fallback\r\n");
+ ClearFSBLIn();
+ FsblHookFallback();
+ }
+
+ /*
+ * update the Multiboot Register for Golden search hunt
+ */
+ Update_MultiBootRegister();
+
+ /*
+ * Notify Boot ROM something is wrong
+ */
+ RebootStatusReg = Xil_In32(REBOOT_STATUS_REG);
+
+ /*
+ * Set the FSBL Fail mask
+ */
+ Xil_Out32(REBOOT_STATUS_REG, RebootStatusReg | FSBL_FAIL_MASK);
+
+ /*
+ * Barrier for synchronization
+ */
+ __asm(
+ "dsb\n\t"
+ "isb"
+ );
+
+ /*
+ * Check for AES source key
+ */
+ if (PcapCtrlRegVal & XDCFG_CTRL_PCFG_AES_FUSE_MASK) {
+ /*
+ * Next valid image search can happen only
+ * when system initialization done
+ */
+ if (SystemInitFlag == 1) {
+ /*
+ * Clean the Fabric
+ */
+ Status = FabricInit();
+ if(Status != XST_SUCCESS){
+ ClearFSBLIn();
+ FsblHookFallback();
+ }
+
+#ifdef RSA_SUPPORT
+
+ /*
+ * Making sure PPK is set for efuse error cases
+ */
+ SetPpk();
+#endif
+
+ /*
+ * Search for next valid image
+ */
+ Status = NextValidImageCheck();
+ if(Status != XST_SUCCESS){
+ fsbl_printf(DEBUG_INFO,"\r\nNo Image Found\r\n");
+ ClearFSBLIn();
+ FsblHookFallback();
+ }
+
+ /*
+ * Load next valid image
+ */
+ HandoffAddr = LoadBootImage();
+
+ /*
+ * Handoff to next image
+ */
+ FsblHandoff(HandoffAddr);
+ } else {
+ fsbl_printf(DEBUG_INFO,"System Initialization Failed\r\n");
+ fsbl_printf(DEBUG_INFO,"\r\nNo Image Search\r\n");
+ ClearFSBLIn();
+ FsblHookFallback();
+ }
+ }
+
+ /*
+ * Reset PS, so Boot ROM will restart
+ */
+ Xil_Out32(PS_RST_CTRL_REG, PS_RST_MASK);
+}
+
+
+/******************************************************************************/
+/**
+*
+* This function hands the A9/PS to the loaded user code.
+*
+* @param none
+*
+* @return none
+*
+* @note This function does not return.
+*
+****************************************************************************/
+void FsblHandoff(u32 FsblStartAddr)
+{
+ u32 Status;
+
+ /*
+ * Enable level shifter
+ */
+ if(BitstreamFlag) {
+ /*
+ * FSBL will not enable the level shifters for a NON PS instantiated
+ * Bitstream
+ * CR# 671028
+ * This flag can be set during compilation for a NON PS instantiated
+ * bitstream
+ */
+#ifndef NON_PS_INSTANTIATED_BITSTREAM
+#ifdef PS7_POST_CONFIG
+ ps7_post_config();
+ /*
+ * Unlock SLCR for SLCR register write
+ */
+ SlcrUnlock();
+#else
+ /*
+ * Set Level Shifters DT618760
+ */
+ Xil_Out32(PS_LVL_SHFTR_EN, LVL_PL_PS);
+ fsbl_printf(DEBUG_INFO,"Enabling Level Shifters PL to PS "
+ "Address = 0x%x Value = 0x%x \n\r",
+ PS_LVL_SHFTR_EN, Xil_In32(PS_LVL_SHFTR_EN));
+
+ /*
+ * Enable AXI interface
+ */
+ Xil_Out32(FPGA_RESET_REG, 0);
+ fsbl_printf(DEBUG_INFO,"AXI Interface enabled \n\r");
+ fsbl_printf(DEBUG_INFO, "FPGA Reset Register "
+ "Address = 0x%x , Value = 0x%x \r\n",
+ FPGA_RESET_REG ,Xil_In32(FPGA_RESET_REG));
+#endif
+#endif
+ }
+
+ /*
+ * FSBL user hook call before handoff to the application
+ */
+ Status = FsblHookBeforeHandoff();
+ if (Status != XST_SUCCESS) {
+ fsbl_printf(DEBUG_GENERAL,"FSBL_HANDOFF_HOOK_FAIL\r\n");
+ OutputStatus(FSBL_HANDOFF_HOOK_FAIL);
+ FsblFallback();
+ }
+
+#ifdef XPAR_XWDTPS_0_BASEADDR
+ XWdtPs_Stop(&Watchdog);
+#endif
+
+ /*
+ * Clear our mark in reboot status register
+ */
+ ClearFSBLIn();
+
+ if(FsblStartAddr == 0) {
+ /*
+ * SLCR lock
+ */
+ SlcrLock();
+
+ fsbl_printf(DEBUG_INFO,"No Execution Address JTAG handoff \r\n");
+ FsblHandoffJtagExit();
+ } else {
+ fsbl_printf(DEBUG_GENERAL,"SUCCESSFUL_HANDOFF\r\n");
+ OutputStatus(SUCCESSFUL_HANDOFF);
+ FsblHandoffExit(FsblStartAddr);
+ }
+
+ OutputStatus(ILLEGAL_RETURN);
+
+ FsblFallback();
+}
+
+/******************************************************************************/
+/**
+*
+* This function outputs the status for the provided State in the boot process.
+*
+* @param State is where in the boot process the output is desired.
+*
+* @return None.
+*
+* @note None.
+*
+****************************************************************************/
+void OutputStatus(u32 State)
+{
+#ifdef STDOUT_BASEADDRESS
+#ifdef XPAR_XUARTPS_0_BASEADDR
+ u32 UartReg = 0;
+#endif
+
+ fsbl_printf(DEBUG_GENERAL,"FSBL Status = 0x%.4lx\r\n", State);
+ /*
+ * The TX buffer needs to be flushed out
+ * If this is not done some of the prints will not appear on the
+ * serial output
+ */
+#ifdef XPAR_XUARTPS_0_BASEADDR
+ UartReg = Xil_In32(STDOUT_BASEADDRESS + XUARTPS_SR_OFFSET);
+ while ((UartReg & XUARTPS_SR_TXEMPTY) != XUARTPS_SR_TXEMPTY) {
+ UartReg = Xil_In32(STDOUT_BASEADDRESS + XUARTPS_SR_OFFSET);
+ }
+#endif
+#endif
+}
+
+/******************************************************************************/
+/**
+*
+* This function handles the error and lockdown processing and outputs the status
+* for the provided State in the boot process.
+*
+* This function is called upon exceptions.
+*
+* @param State - where in the boot process the error occurred.
+*
+* @return None.
+*
+* @note This function does not return, the PS block is reset
+*
+****************************************************************************/
+void ErrorLockdown(u32 State)
+{
+ /*
+ * Store the error status
+ */
+ OutputStatus(State);
+
+ /*
+ * Fall back
+ */
+ FsblFallback();
+}
+
+/******************************************************************************/
+/**
+*
+* This function copies a memory region to another memory region
+*
+* @param s1 is starting address for destination
+* @param s2 is starting address for the source
+* @param n is the number of bytes to copy
+*
+* @return Starting address for destination
+*
+****************************************************************************/
+void *(memcpy_rom)(void * s1, const void * s2, u32 n)
+{
+ char *dst = (char *)s1;
+ const char *src = (char *)s2;
+
+ /*
+ * Loop and copy
+ */
+ while (n-- != 0)
+ *dst++ = *src++;
+ return s1;
+}
+/******************************************************************************/
+/**
+*
+* This function copies a string to another, the source string must be null-
+* terminated.
+*
+* @param Dest is starting address for the destination string
+* @param Src is starting address for the source string
+*
+* @return Starting address for the destination string
+*
+****************************************************************************/
+char *strcpy_rom(char *Dest, const char *Src)
+{
+ unsigned i;
+ for (i=0; Src[i] != '\0'; ++i)
+ Dest[i] = Src[i];
+ Dest[i] = '\0';
+ return Dest;
+}
+
+
+/******************************************************************************/
+/**
+*
+* This function sets FSBL is running mask in reboot status register
+*
+* @param None.
+*
+* @return None.
+*
+* @note None.
+*
+****************************************************************************/
+void MarkFSBLIn(void)
+{
+ Xil_Out32(REBOOT_STATUS_REG,
+ Xil_In32(REBOOT_STATUS_REG) | FSBL_IN_MASK);
+}
+
+
+/******************************************************************************/
+/**
+*
+* This function clears FSBL is running mask in reboot status register
+*
+* @param None.
+*
+* @return None.
+*
+* @note None.
+*
+****************************************************************************/
+void ClearFSBLIn(void)
+{
+ Xil_Out32(REBOOT_STATUS_REG,
+ (Xil_In32(REBOOT_STATUS_REG)) & ~(FSBL_FAIL_MASK));
+}
+
+/******************************************************************************/
+/**
+*
+* This function Registers the Exception Handlers
+*
+* @param None.
+*
+* @return None.
+*
+* @note None.
+*
+****************************************************************************/
+static void RegisterHandlers(void)
+{
+ Xil_ExceptionInit();
+
+ /*
+ * Initialize the vector table. Register the stub Handler for each
+ * exception.
+ */
+ Xil_ExceptionRegisterHandler(XIL_EXCEPTION_ID_UNDEFINED_INT,
+ (Xil_ExceptionHandler)Undef_Handler,
+ (void *) 0);
+ Xil_ExceptionRegisterHandler(XIL_EXCEPTION_ID_SWI_INT,
+ (Xil_ExceptionHandler)SVC_Handler,
+ (void *) 0);
+ Xil_ExceptionRegisterHandler(XIL_EXCEPTION_ID_PREFETCH_ABORT_INT,
+ (Xil_ExceptionHandler)PreFetch_Abort_Handler,
+ (void *) 0);
+ Xil_ExceptionRegisterHandler(XIL_EXCEPTION_ID_DATA_ABORT_INT,
+ (Xil_ExceptionHandler)Data_Abort_Handler,
+ (void *) 0);
+ Xil_ExceptionRegisterHandler(XIL_EXCEPTION_ID_IRQ_INT,
+ (Xil_ExceptionHandler)IRQ_Handler,(void *) 0);
+ Xil_ExceptionRegisterHandler(XIL_EXCEPTION_ID_FIQ_INT,
+ (Xil_ExceptionHandler)FIQ_Handler,(void *) 0);
+
+ Xil_ExceptionEnable();
+
+}
+
+static void Undef_Handler (void)
+{
+ fsbl_printf(DEBUG_GENERAL,"UNDEFINED_HANDLER\r\n");
+ ErrorLockdown (EXCEPTION_ID_UNDEFINED_INT);
+}
+
+static void SVC_Handler (void)
+{
+ fsbl_printf(DEBUG_GENERAL,"SVC_HANDLER \r\n");
+ ErrorLockdown (EXCEPTION_ID_SWI_INT);
+}
+
+static void PreFetch_Abort_Handler (void)
+{
+ fsbl_printf(DEBUG_GENERAL,"PREFETCH_ABORT_HANDLER \r\n");
+ ErrorLockdown (EXCEPTION_ID_PREFETCH_ABORT_INT);
+}
+
+static void Data_Abort_Handler (void)
+{
+ fsbl_printf(DEBUG_GENERAL,"DATA_ABORT_HANDLER \r\n");
+ ErrorLockdown (EXCEPTION_ID_DATA_ABORT_INT);
+}
+
+static void IRQ_Handler (void)
+{
+ fsbl_printf(DEBUG_GENERAL,"IRQ_HANDLER \r\n");
+ ErrorLockdown (EXCEPTION_ID_IRQ_INT);
+}
+
+static void FIQ_Handler (void)
+{
+ fsbl_printf(DEBUG_GENERAL,"FIQ_HANDLER \r\n");
+ ErrorLockdown (EXCEPTION_ID_FIQ_INT);
+}
+
+
+/******************************************************************************/
+/**
+*
+* This function Updates the Multi boot Register to enable golden image
+* search for boot rom
+*
+* @param None
+*
+* @return
+* return none
+*
+****************************************************************************/
+static void Update_MultiBootRegister(void)
+{
+ u32 MultiBootReg = 0;
+
+ if (Silicon_Version != SILICON_VERSION_1) {
+ /*
+ * Read the mulitboot register
+ */
+ MultiBootReg = XDcfg_ReadReg(DcfgInstPtr->Config.BaseAddr,
+ XDCFG_MULTIBOOT_ADDR_OFFSET);
+
+ /*
+ * Incrementing multiboot register by one
+ */
+ MultiBootReg++;
+
+ XDcfg_WriteReg(DcfgInstPtr->Config.BaseAddr,
+ XDCFG_MULTIBOOT_ADDR_OFFSET,
+ MultiBootReg);
+
+ fsbl_printf(DEBUG_INFO,"Updated MultiBootReg = 0x%08lx\r\n",
+ MultiBootReg);
+ }
+}
+
+
+/******************************************************************************
+*
+* This function reset the CPU and goes for Boot ROM fallback handling
+*
+* @param None
+*
+* @return None
+*
+* @note None
+*
+*******************************************************************************/
+
+u32 GetResetReason(void)
+{
+ u32 Regval;
+
+ /* We are using REBOOT_STATUS_REG, we have to use bits 23:16 */
+ /* for storing the RESET_REASON register value*/
+ Regval = ((Xil_In32(REBOOT_STATUS_REG) >> 16) & 0xFF);
+
+ return Regval;
+}
+
+
+/******************************************************************************
+*
+* This function Gets the ticks from the Global Timer
+*
+* @param Current time
+*
+* @return
+* None
+*
+* @note None
+*
+*******************************************************************************/
+#ifdef FSBL_PERF
+void FsblGetGlobalTime (XTime *tCur)
+{
+ XTime_GetTime(tCur);
+}
+
+
+/******************************************************************************
+*
+* This function Measures the execution time
+*
+* @param Current time , End time
+*
+* @return
+* None
+*
+* @note None
+*
+*******************************************************************************/
+void FsblMeasurePerfTime (XTime tCur, XTime tEnd)
+{
+ double tDiff = 0.0;
+ double tPerfSeconds;
+ XTime_GetTime(&tEnd);
+ tDiff = (double)tEnd - (double)tCur;
+
+ /*
+ * Convert tPerf into Seconds
+ */
+ tPerfSeconds = tDiff/COUNTS_PER_SECOND;
+
+#if defined(STDOUT_BASEADDRESS)
+ printf("%f seconds \r\n",tPerfSeconds);
+#endif
+
+}
+#endif
+
+/******************************************************************************
+*
+* This function initializes the Watchdog driver and starts the timer
+*
+* @param None
+*
+* @return
+* - XST_SUCCESS if the Watchdog driver is initialized
+* - XST_FAILURE if Watchdog driver initialization fails
+*
+* @note None
+*
+*******************************************************************************/
+#ifdef XPAR_XWDTPS_0_BASEADDR
+int InitWatchDog(void)
+{
+ u32 Status = XST_SUCCESS;
+ XWdtPs_Config *ConfigPtr; /* Config structure of the WatchDog Timer */
+ u32 CounterValue = 1;
+
+ ConfigPtr = XWdtPs_LookupConfig(WDT_DEVICE_ID);
+ Status = XWdtPs_CfgInitialize(&Watchdog,
+ ConfigPtr,
+ ConfigPtr->BaseAddress);
+ if (Status != XST_SUCCESS) {
+ fsbl_printf(DEBUG_INFO,"Watchdog Driver init Failed \n\r");
+ return XST_FAILURE;
+ }
+
+ /*
+ * Setting the divider value
+ */
+ XWdtPs_SetControlValue(&Watchdog,
+ XWDTPS_CLK_PRESCALE,
+ XWDTPS_CCR_PSCALE_4096);
+ /*
+ * Convert time to Watchdog counter reset value
+ */
+ CounterValue = ConvertTime_WdtCounter(WDT_EXPIRE_TIME);
+
+ /*
+ * Set the Watchdog counter reset value
+ */
+ XWdtPs_SetControlValue(&Watchdog,
+ XWDTPS_COUNTER_RESET,
+ CounterValue);
+ /*
+ * enable reset output, as we are only using this as a basic counter
+ */
+ XWdtPs_EnableOutput(&Watchdog, XWDTPS_RESET_SIGNAL);
+
+ /*
+ * Start the Watchdog timer
+ */
+ XWdtPs_Start(&Watchdog);
+
+ XWdtPs_RestartWdt(&Watchdog);
+
+ return XST_SUCCESS;
+}
+
+
+/******************************************************************************/
+/**
+*
+* This function checks whether WDT reset has happened during FSBL run
+*
+* If WDT reset happened during FSBL run, then need to fallback
+*
+* @param None.
+*
+* @return
+* None
+*
+* @note None
+*
+****************************************************************************/
+void CheckWDTReset(void)
+{
+ u32 ResetReason;
+ u32 RebootStatusRegister;
+
+ RebootStatusRegister = Xil_In32(REBOOT_STATUS_REG);
+
+ /*
+ * For 1.0 Silicon the reason for Reset is in the ResetReason Register
+ * Hence this register can be read to know the cause for previous reset
+ * that happened.
+ * Check if that reset is a Software WatchDog reset that happened
+ */
+ if (Silicon_Version == SILICON_VERSION_1) {
+ ResetReason = Xil_In32(RESET_REASON_REG);
+ } else {
+ ResetReason = GetResetReason();
+ }
+ /*
+ * If the FSBL_IN_MASK Has not been cleared, WDT happened
+ * before FSBL exits
+ */
+ if ((ResetReason & RESET_REASON_SWDT) == RESET_REASON_SWDT ) {
+ if ((RebootStatusRegister & FSBL_FAIL_MASK) == FSBL_IN_MASK) {
+ /*
+ * Clear the SWDT Reset bit
+ */
+ ResetReason &= ~RESET_REASON_SWDT;
+ if (Silicon_Version == SILICON_VERSION_1) {
+ /*
+ * for 1.0 Silicon we need to write
+ * 1 to the RESET REASON Clear register
+ */
+ Xil_Out32(RESET_REASON_CLR, 1);
+ } else {
+ Xil_Out32(REBOOT_STATUS_REG, ResetReason);
+ }
+
+ fsbl_printf(DEBUG_GENERAL,"WDT_RESET_OCCURED \n\r");
+ }
+ }
+}
+
+
+/******************************************************************************
+*
+* This function converts time into Watchdog counter value
+*
+* @param watchdog expire time in seconds
+*
+* @return
+* Counter value for Watchdog
+*
+* @note None
+*
+*******************************************************************************/
+u32 ConvertTime_WdtCounter(u32 seconds)
+{
+ double time = 0.0;
+ double CounterValue;
+ u32 Crv = 0;
+ u32 Prescaler,PrescalerValue;
+
+ Prescaler = XWdtPs_GetControlValue(&Watchdog, XWDTPS_CLK_PRESCALE);
+
+ if (Prescaler == XWDTPS_CCR_PSCALE_0008)
+ PrescalerValue = 8;
+ if (Prescaler == XWDTPS_CCR_PSCALE_0064)
+ PrescalerValue = 64;
+ if (Prescaler == XWDTPS_CCR_PSCALE_4096)
+ PrescalerValue = 4096;
+
+ time = (double)(PrescalerValue) / (double)XPAR_PS7_WDT_0_WDT_CLK_FREQ_HZ;
+
+ CounterValue = seconds / time;
+
+ Crv = (u32)CounterValue;
+ Crv >>= WDT_CRV_SHIFT;
+
+ return Crv;
+}
+
+#endif
+
+
+/******************************************************************************
+*
+* This function Gets the Silicon Version stores in global variable
+*
+* @param None
+*
+* @return None
+*
+* @note None
+*
+*******************************************************************************/
+void GetSiliconVersion(void)
+{
+ /*
+ * Get the silicon version
+ */
+ Silicon_Version = XDcfg_GetPsVersion(DcfgInstPtr);
+ if(Silicon_Version == SILICON_VERSION_3_1) {
+ fsbl_printf(DEBUG_GENERAL,"Silicon Version 3.1\r\n");
+ } else {
+ fsbl_printf(DEBUG_GENERAL,"Silicon Version %lu.0\r\n",
+ Silicon_Version + 1);
+ }
+}
+
+
+/******************************************************************************
+*
+* This function HeaderChecksum will calculates the header checksum and
+* compares with checksum read from flash
+*
+* @param FlashOffsetAddress Flash offset address
+*
+* @return
+* - XST_SUCCESS if ID matches
+* - XST_FAILURE if ID mismatches
+*
+* @note None
+*
+*******************************************************************************/
+u32 HeaderChecksum(u32 FlashOffsetAddress){
+ u32 Checksum = 0;
+ u32 Count;
+ u32 TempValue = 0;
+
+ for (Count = 0; Count < IMAGE_HEADER_CHECKSUM_COUNT; Count++) {
+ /*
+ * Read the word from the header
+ */
+ MoveImage(FlashOffsetAddress + IMAGE_WIDTH_CHECK_OFFSET + (Count*4), (u32)&TempValue, 4);
+
+ /*
+ * Update checksum
+ */
+ Checksum += TempValue;
+ }
+
+ /*
+ * Invert checksum, last bit of error checking
+ */
+ Checksum ^= 0xFFFFFFFF;
+ MoveImage(FlashOffsetAddress + IMAGE_CHECKSUM_OFFSET, (u32)&TempValue, 4);
+
+ /*
+ * Validate the checksum
+ */
+ if (TempValue != Checksum){
+ fsbl_printf(DEBUG_INFO, "Checksum = %8.8lx\r\n", Checksum);
+ return XST_FAILURE;
+ }
+
+ return XST_SUCCESS;
+}
+
+
+/******************************************************************************
+*
+* This function ImageCheckID will do check for XLNX pattern
+*
+* @param FlashOffsetAddress Flash offset address
+*
+* @return
+* - XST_SUCCESS if ID matches
+* - XST_FAILURE if ID mismatches
+*
+* @note None
+*
+*******************************************************************************/
+u32 ImageCheckID(u32 FlashOffsetAddress){
+ u32 ID;
+
+ /*
+ * Read in the header info
+ */
+ MoveImage(FlashOffsetAddress + IMAGE_IDENT_OFFSET, (u32)&ID, 4);
+
+ /*
+ * Check the ID, make sure image is XLNX format
+ */
+ if (ID != IMAGE_IDENT){
+ return XST_FAILURE;
+ }
+
+ return XST_SUCCESS;
+}
+
+
+/******************************************************************************
+*
+* This function NextValidImageCheck search for valid boot image
+*
+* @param None
+*
+* @return
+* - XST_SUCCESS if valid image found
+* - XST_FAILURE if no image found
+*
+* @note None
+*
+*******************************************************************************/
+u32 NextValidImageCheck(void)
+{
+ u32 ImageBaseAddr;
+ u32 MultiBootReg;
+ u32 BootDevMaxSize=0;
+
+ fsbl_printf(DEBUG_GENERAL, "Searching For Next Valid Image");
+
+ /*
+ * Setting variable with maximum flash size based on boot mode
+ */
+#ifdef XPAR_PS7_QSPI_LINEAR_0_S_AXI_BASEADDR
+ if (FlashReadBaseAddress == XPS_QSPI_LINEAR_BASEADDR) {
+ BootDevMaxSize = QspiFlashSize;
+ }
+#endif
+
+ if (FlashReadBaseAddress == XPS_NAND_BASEADDR) {
+ BootDevMaxSize = NAND_FLASH_SIZE;
+ }
+
+ if (FlashReadBaseAddress == XPS_NOR_BASEADDR) {
+ BootDevMaxSize = NOR_FLASH_SIZE;
+ }
+
+ /*
+ * Read the multiboot register
+ */
+ MultiBootReg = XDcfg_ReadReg(DcfgInstPtr->Config.BaseAddr,
+ XDCFG_MULTIBOOT_ADDR_OFFSET);
+
+ /*
+ * Compute the image start address
+ */
+ ImageBaseAddr = (MultiBootReg & PCAP_MBOOT_REG_REBOOT_OFFSET_MASK)
+ * GOLDEN_IMAGE_OFFSET;
+
+ /*
+ * Valid image search continue till end of the flash
+ * With increment 32KB in each iteration
+ */
+ while (ImageBaseAddr < BootDevMaxSize) {
+
+ fsbl_printf(DEBUG_INFO,".");
+
+ /*
+ * Valid image search using XLNX pattern at fixed offset
+ * and header checksum
+ */
+ if ((ImageCheckID(ImageBaseAddr) == XST_SUCCESS) &&
+ (HeaderChecksum(ImageBaseAddr) == XST_SUCCESS)) {
+
+ fsbl_printf(DEBUG_GENERAL, "\r\nImage found, offset: 0x%.8lx\r\n",
+ ImageBaseAddr);
+ /*
+ * Update multiboot register
+ */
+ XDcfg_WriteReg(DcfgInstPtr->Config.BaseAddr,
+ XDCFG_MULTIBOOT_ADDR_OFFSET,
+ MultiBootReg);
+
+ return XST_SUCCESS;
+ }
+
+ /*
+ * Increment mulitboot count
+ */
+ MultiBootReg++;
+
+ /*
+ * Compute the image start address
+ */
+ ImageBaseAddr = (MultiBootReg & PCAP_MBOOT_REG_REBOOT_OFFSET_MASK)
+ * GOLDEN_IMAGE_OFFSET;
+ }
+
+ return XST_FAILURE;
+}
+
+/******************************************************************************/
+/**
+*
+* This function Checks for the ddr initialization completion
+*
+* @param None.
+*
+* @return
+* - XST_SUCCESS if the initialization is successful
+* - XST_FAILURE if the initialization is NOT successful
+*
+* @note None.
+*
+****************************************************************************/
+u32 DDRInitCheck(void)
+{
+ u32 ReadVal;
+
+ /*
+ * Write and Read from the DDR location for sanity checks
+ */
+ Xil_Out32(DDR_START_ADDR, DDR_TEST_PATTERN);
+ ReadVal = Xil_In32(DDR_START_ADDR);
+ if (ReadVal != DDR_TEST_PATTERN) {
+ return XST_FAILURE;
+ }
+
+ /*
+ * Write and Read from the DDR location for sanity checks
+ */
+ Xil_Out32(DDR_START_ADDR + DDR_TEST_OFFSET, DDR_TEST_PATTERN);
+ ReadVal = Xil_In32(DDR_START_ADDR + DDR_TEST_OFFSET);
+ if (ReadVal != DDR_TEST_PATTERN) {
+ return XST_FAILURE;
+ }
+
+ return XST_SUCCESS;
+}
diff --git a/hello_world/sw/fsbl/md5.c b/hello_world/sw/fsbl/md5.c
new file mode 100644
index 0000000..0fdda9b
--- /dev/null
+++ b/hello_world/sw/fsbl/md5.c
@@ -0,0 +1,484 @@
+/* Copyright (C) 1995-1998 Eric Young (eay@cryptsoft.com)
+ * All rights reserved.
+ *
+ * This package is an SSL implementation written
+ * by Eric Young (eay@cryptsoft.com).
+ * The implementation was written so as to conform with Netscapes SSL.
+ *
+ * This library is free for commercial and non-commercial use as long as
+ * the following conditions are adhered to. The following conditions
+ * apply to all code found in this distribution, be it the RC4, RSA,
+ * lhash, DES, etc., code; not just the SSL code. The SSL documentation
+ * included with this distribution is covered by the same copyright terms
+ * except that the holder is Tim Hudson (tjh@cryptsoft.com).
+ *
+ * Copyright remains Eric Young's, and as such any Copyright notices in
+ * the code are not to be removed.
+ * If this package is used in a product, Eric Young should be given attribution
+ * as the author of the parts of the library used.
+ * This can be in the form of a textual message at program startup or
+ * in documentation (online or textual) provided with the package.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * 3. All advertising materials mentioning features or use of this software
+ * must display the following acknowledgement:
+ * "This product includes cryptographic software written by
+ * Eric Young (eay@cryptsoft.com)"
+ * The word 'cryptographic' can be left out if the routines from the library
+ * being used are not cryptographic related :-).
+ * 4. If you include any Windows specific code (or a derivative thereof) from
+ * the apps directory (application code) you must include an acknowledgement:
+ * "This product includes software written by Tim Hudson (tjh@cryptsoft.com)"
+ *
+ * THIS SOFTWARE IS PROVIDED BY ERIC YOUNG ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ *
+ * The licence and distribution terms for any publicly available version or
+ * derivative of this code cannot be changed. i.e. this code cannot simply be
+ * copied and put under another distribution licence
+ * [including the GNU Public Licence.]
+ */
+/*****************************************************************************/
+/**
+*
+* @file md5.c
+*
+* Contains code to calculate checksum using md5 algorithm
+*
+* <pre>
+* MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ----- ---- -------- -------------------------------------------------------
+* 5.00a sgd 05/17/13 Initial release
+*
+*
+* </pre>
+*
+* @note
+*
+******************************************************************************/
+/****************************** Include Files *********************************/
+
+#include "md5.h"
+
+/******************************************************************************/
+/**
+*
+* This function sets the memory
+*
+* @param dest
+*
+* @param ch
+*
+* @param count
+*
+* @return None
+*
+* @note None
+*
+****************************************************************************/
+inline void * MD5Memset( void *dest, int ch, u32 count )
+{
+ register char *dst8 = (char*)dest;
+
+ while( count-- )
+ *dst8++ = ch;
+
+ return dest;
+}
+
+/******************************************************************************/
+/**
+*
+* This function copy the memory
+*
+* @param dest
+*
+* @param ch
+*
+* @param count
+*
+* @return None
+*
+* @note None
+*
+****************************************************************************/
+inline void * MD5Memcpy( void *dest, const void *src,
+ u32 count, boolean doByteSwap )
+{
+ register char * dst8 = (char*)dest;
+ register char * src8 = (char*)src;
+
+ if( doByteSwap == FALSE ) {
+ while( count-- )
+ *dst8++ = *src8++;
+ } else {
+ count /= sizeof( u32 );
+
+ while( count-- ) {
+ dst8[ 0 ] = src8[ 3 ];
+ dst8[ 1 ] = src8[ 2 ];
+ dst8[ 2 ] = src8[ 1 ];
+ dst8[ 3 ] = src8[ 0 ];
+
+ dst8 += 4;
+ src8 += 4;
+ }
+ }
+
+ return dest;
+}
+
+/******************************************************************************/
+/**
+*
+* This function is the core of the MD5 algorithm,
+* this alters an existing MD5 hash to
+* reflect the addition of 16 longwords of new data. MD5Update blocks
+* the data and converts bytes into longwords for this routine.
+*
+* Use binary integer part of the sine of integers (Radians) as constants.
+* Calculated as:
+*
+* for( i = 0; i < 63; i++ )
+* k[ i ] := floor( abs( sin( i + 1 ) ) × pow( 2, 32 ) )
+*
+* Following number is the per-round shift amount.
+*
+* @param dest
+*
+* @param ch
+*
+* @param count
+*
+* @return None
+*
+* @note None
+*
+****************************************************************************/
+void MD5Transform( u32 *buffer, u32 *intermediate )
+{
+ register u32 a, b, c, d;
+
+ a = buffer[ 0 ];
+ b = buffer[ 1 ];
+ c = buffer[ 2 ];
+ d = buffer[ 3 ];
+
+ MD5_STEP( F1, a, b, c, d, intermediate[ 0 ] + 0xd76aa478, 7 );
+ MD5_STEP( F1, d, a, b, c, intermediate[ 1 ] + 0xe8c7b756, 12 );
+ MD5_STEP( F1, c, d, a, b, intermediate[ 2 ] + 0x242070db, 17 );
+ MD5_STEP( F1, b, c, d, a, intermediate[ 3 ] + 0xc1bdceee, 22 );
+ MD5_STEP( F1, a, b, c, d, intermediate[ 4 ] + 0xf57c0faf, 7 );
+ MD5_STEP( F1, d, a, b, c, intermediate[ 5 ] + 0x4787c62a, 12 );
+ MD5_STEP( F1, c, d, a, b, intermediate[ 6 ] + 0xa8304613, 17 );
+ MD5_STEP( F1, b, c, d, a, intermediate[ 7 ] + 0xfd469501, 22 );
+ MD5_STEP( F1, a, b, c, d, intermediate[ 8 ] + 0x698098d8, 7 );
+ MD5_STEP( F1, d, a, b, c, intermediate[ 9 ] + 0x8b44f7af, 12 );
+ MD5_STEP( F1, c, d, a, b, intermediate[ 10 ] + 0xffff5bb1, 17 );
+ MD5_STEP( F1, b, c, d, a, intermediate[ 11 ] + 0x895cd7be, 22 );
+ MD5_STEP( F1, a, b, c, d, intermediate[ 12 ] + 0x6b901122, 7 );
+ MD5_STEP( F1, d, a, b, c, intermediate[ 13 ] + 0xfd987193, 12 );
+ MD5_STEP( F1, c, d, a, b, intermediate[ 14 ] + 0xa679438e, 17 );
+ MD5_STEP( F1, b, c, d, a, intermediate[ 15 ] + 0x49b40821, 22 );
+
+ MD5_STEP( F2, a, b, c, d, intermediate[ 1 ] + 0xf61e2562, 5 );
+ MD5_STEP( F2, d, a, b, c, intermediate[ 6 ] + 0xc040b340, 9 );
+ MD5_STEP( F2, c, d, a, b, intermediate[ 11 ] + 0x265e5a51, 14 );
+ MD5_STEP( F2, b, c, d, a, intermediate[ 0 ] + 0xe9b6c7aa, 20 );
+ MD5_STEP( F2, a, b, c, d, intermediate[ 5 ] + 0xd62f105d, 5 );
+ MD5_STEP( F2, d, a, b, c, intermediate[ 10 ] + 0x02441453, 9 );
+ MD5_STEP( F2, c, d, a, b, intermediate[ 15 ] + 0xd8a1e681, 14 );
+ MD5_STEP( F2, b, c, d, a, intermediate[ 4 ] + 0xe7d3fbc8, 20 );
+ MD5_STEP( F2, a, b, c, d, intermediate[ 9 ] + 0x21e1cde6, 5 );
+ MD5_STEP( F2, d, a, b, c, intermediate[ 14 ] + 0xc33707d6, 9 );
+ MD5_STEP( F2, c, d, a, b, intermediate[ 3 ] + 0xf4d50d87, 14 );
+ MD5_STEP( F2, b, c, d, a, intermediate[ 8 ] + 0x455a14ed, 20 );
+ MD5_STEP( F2, a, b, c, d, intermediate[ 13 ] + 0xa9e3e905, 5 );
+ MD5_STEP( F2, d, a, b, c, intermediate[ 2 ] + 0xfcefa3f8, 9 );
+ MD5_STEP( F2, c, d, a, b, intermediate[ 7 ] + 0x676f02d9, 14 );
+ MD5_STEP( F2, b, c, d, a, intermediate[ 12 ] + 0x8d2a4c8a, 20 );
+
+ MD5_STEP( F3, a, b, c, d, intermediate[ 5 ] + 0xfffa3942, 4 );
+ MD5_STEP( F3, d, a, b, c, intermediate[ 8 ] + 0x8771f681, 11 );
+ MD5_STEP( F3, c, d, a, b, intermediate[ 11 ] + 0x6d9d6122, 16 );
+ MD5_STEP( F3, b, c, d, a, intermediate[ 14 ] + 0xfde5380c, 23 );
+ MD5_STEP( F3, a, b, c, d, intermediate[ 1 ] + 0xa4beea44, 4 );
+ MD5_STEP( F3, d, a, b, c, intermediate[ 4 ] + 0x4bdecfa9, 11 );
+ MD5_STEP( F3, c, d, a, b, intermediate[ 7 ] + 0xf6bb4b60, 16 );
+ MD5_STEP( F3, b, c, d, a, intermediate[ 10 ] + 0xbebfbc70, 23 );
+ MD5_STEP( F3, a, b, c, d, intermediate[ 13 ] + 0x289b7ec6, 4 );
+ MD5_STEP( F3, d, a, b, c, intermediate[ 0 ] + 0xeaa127fa, 11 );
+ MD5_STEP( F3, c, d, a, b, intermediate[ 3 ] + 0xd4ef3085, 16 );
+ MD5_STEP( F3, b, c, d, a, intermediate[ 6 ] + 0x04881d05, 23 );
+ MD5_STEP( F3, a, b, c, d, intermediate[ 9 ] + 0xd9d4d039, 4 );
+ MD5_STEP( F3, d, a, b, c, intermediate[ 12 ] + 0xe6db99e5, 11 );
+ MD5_STEP( F3, c, d, a, b, intermediate[ 15 ] + 0x1fa27cf8, 16 );
+ MD5_STEP( F3, b, c, d, a, intermediate[ 2 ] + 0xc4ac5665, 23 );
+
+ MD5_STEP( F4, a, b, c, d, intermediate[ 0 ] + 0xf4292244, 6 );
+ MD5_STEP( F4, d, a, b, c, intermediate[ 7 ] + 0x432aff97, 10 );
+ MD5_STEP( F4, c, d, a, b, intermediate[ 14 ] + 0xab9423a7, 15 );
+ MD5_STEP( F4, b, c, d, a, intermediate[ 5 ] + 0xfc93a039, 21 );
+ MD5_STEP( F4, a, b, c, d, intermediate[ 12 ] + 0x655b59c3, 6 );
+ MD5_STEP( F4, d, a, b, c, intermediate[ 3 ] + 0x8f0ccc92, 10 );
+ MD5_STEP( F4, c, d, a, b, intermediate[ 10 ] + 0xffeff47d, 15 );
+ MD5_STEP( F4, b, c, d, a, intermediate[ 1 ] + 0x85845dd1, 21 );
+ MD5_STEP( F4, a, b, c, d, intermediate[ 8 ] + 0x6fa87e4f, 6 );
+ MD5_STEP( F4, d, a, b, c, intermediate[ 15 ] + 0xfe2ce6e0, 10 );
+ MD5_STEP( F4, c, d, a, b, intermediate[ 6 ] + 0xa3014314, 15 );
+ MD5_STEP( F4, b, c, d, a, intermediate[ 13 ] + 0x4e0811a1, 21 );
+ MD5_STEP( F4, a, b, c, d, intermediate[ 4 ] + 0xf7537e82, 6 );
+ MD5_STEP( F4, d, a, b, c, intermediate[ 11 ] + 0xbd3af235, 10 );
+ MD5_STEP( F4, c, d, a, b, intermediate[ 2 ] + 0x2ad7d2bb, 15 );
+ MD5_STEP( F4, b, c, d, a, intermediate[ 9 ] + 0xeb86d391, 21 );
+
+ buffer[ 0 ] += a;
+ buffer[ 1 ] += b;
+ buffer[ 2 ] += c;
+ buffer[ 3 ] += d;
+
+}
+
+/******************************************************************************/
+/**
+*
+* This function Start MD5 accumulation
+* Set bit count to 0 and buffer to mysterious initialization constants
+*
+* @param
+*
+* @return None
+*
+* @note None
+*
+****************************************************************************/
+inline void MD5Init( MD5Context *context )
+{
+
+ context->buffer[ 0 ] = 0x67452301;
+ context->buffer[ 1 ] = 0xefcdab89;
+ context->buffer[ 2 ] = 0x98badcfe;
+ context->buffer[ 3 ] = 0x10325476;
+
+ context->bits[ 0 ] = 0;
+ context->bits[ 1 ] = 0;
+
+}
+
+
+/******************************************************************************/
+/**
+*
+* This function updates context to reflect the concatenation of another
+* buffer full of bytes
+*
+* @param
+*
+* @param
+*
+* @param
+*
+* @param
+*
+* @return None
+*
+* @note None
+*
+****************************************************************************/
+inline void MD5Update( MD5Context *context, u8 *buffer,
+ u32 len, boolean doByteSwap )
+{
+ register u32 temp;
+ register u8 * p;
+
+ /*
+ * Update bitcount
+ */
+
+ temp = context->bits[ 0 ];
+
+ if( ( context->bits[ 0 ] = temp + ( (u32)len << 3 ) ) < temp ) {
+ /*
+ * Carry from low to high
+ */
+ context->bits[ 1 ]++;
+ }
+
+ context->bits[ 1 ] += len >> 29;
+
+ /*
+ * Bytes already in shsInfo->data
+ */
+
+ temp = ( temp >> 3 ) & 0x3f;
+
+ /*
+ * Handle any leading odd-sized chunks
+ */
+
+ if( temp ) {
+ p = (u8 *)context->intermediate + temp;
+
+ temp = MD5_SIGNATURE_BYTE_SIZE - temp;
+
+ if( len < temp ) {
+ MD5Memcpy( p, buffer, len, doByteSwap );
+ return;
+ }
+
+ MD5Memcpy( p, buffer, temp, doByteSwap );
+
+ MD5Transform( context->buffer, (u32 *)context->intermediate );
+
+ buffer += temp;
+ len -= temp;
+
+ }
+
+ /*
+ * Process data in 64-byte, 512 bit, chunks
+ */
+
+ while( len >= MD5_SIGNATURE_BYTE_SIZE ) {
+ MD5Memcpy( context->intermediate, buffer, MD5_SIGNATURE_BYTE_SIZE,
+ doByteSwap );
+
+ MD5Transform( context->buffer, (u32 *)context->intermediate );
+
+ buffer += MD5_SIGNATURE_BYTE_SIZE;
+ len -= MD5_SIGNATURE_BYTE_SIZE;
+
+ }
+
+ /*
+ * Handle any remaining bytes of data
+ */
+ MD5Memcpy( context->intermediate, buffer, len, doByteSwap );
+
+}
+
+/******************************************************************************/
+/**
+*
+* This function final wrap-up - pad to 64-byte boundary with the bit pattern
+* 1 0* (64-bit count of bits processed, MSB-first
+*
+* @param
+*
+* @param
+*
+* @param
+*
+* @param
+*
+* @return None
+*
+* @note None
+*
+****************************************************************************/
+inline void MD5Final( MD5Context *context, u8 *digest,
+ boolean doByteSwap )
+{
+ u32 count;
+ u8 * p;
+
+ /*
+ * Compute number of bytes mod 64
+ */
+ count = ( context->bits[ 0 ] >> 3 ) & 0x3F;
+
+ /*
+ * Set the first char of padding to 0x80. This is safe since there is
+ * always at least one byte free
+ */
+ p = context->intermediate + count;
+ *p++ = 0x80;
+
+ /*
+ * Bytes of padding needed to make 64 bytes
+ */
+ count = MD5_SIGNATURE_BYTE_SIZE - 1 - count;
+
+ /*
+ * Pad out to 56 mod 64
+ */
+ if( count < 8 ) {
+ /*
+ * Two lots of padding: Pad the first block to 64 bytes
+ */
+ MD5Memset( p, 0, count );
+
+ MD5Transform( context->buffer, (u32 *)context->intermediate );
+
+ /*
+ * Now fill the next block with 56 bytes
+ */
+ MD5Memset( context->intermediate, 0, 56 );
+ } else {
+ /*
+ * Pad block to 56 bytes
+ */
+ MD5Memset( p, 0, count - 8 );
+ }
+
+ /*
+ * Append length in bits and transform
+ */
+ ( (u32 *)context->intermediate )[ 14 ] = context->bits[ 0 ];
+ ( (u32 *)context->intermediate )[ 15 ] = context->bits[ 1 ];
+
+ MD5Transform( context->buffer, (u32 *)context->intermediate );
+
+ /*
+ * Now return the digest
+ */
+ MD5Memcpy( digest, context->buffer, 16, doByteSwap );
+}
+
+/******************************************************************************/
+/**
+*
+* This function calculate and store in 'digest' the MD5 digest of 'len' bytes at
+* 'input'. 'digest' must have enough space to hold 16 bytes
+*
+* @param
+*
+* @param
+*
+* @param
+*
+* @param
+*
+* @return None
+*
+* @note None
+*
+****************************************************************************/
+void md5( u8 *input, u32 len, u8 *digest, boolean doByteSwap )
+{
+ MD5Context context;
+
+ MD5Init( &context );
+
+ MD5Update( &context, input, len, doByteSwap );
+
+ MD5Final( &context, digest, doByteSwap );
+}
diff --git a/hello_world/sw/fsbl/md5.h b/hello_world/sw/fsbl/md5.h
new file mode 100644
index 0000000..773eff1
--- /dev/null
+++ b/hello_world/sw/fsbl/md5.h
@@ -0,0 +1,114 @@
+/******************************************************************************
+*
+* Copyright (C) 2012 - 2014 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+* THE SOFTWARE.
+*
+*
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file md5.h
+*
+*
+* <pre>
+* MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ----- ---- -------- -------------------------------------------------------
+* 5.00a sgd 05/17/13 Initial release
+*
+* </pre>
+*
+* @note
+*
+******************************************************************************/
+#ifndef ___MD5_H___
+#define ___MD5_H___
+
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/***************************** Include Files *********************************/
+
+#include "xil_types.h"
+
+/************************** Constant Definitions *****************************/
+
+#define MD5_SIGNATURE_BYTE_SIZE 64
+
+/**************************** Type Definitions *******************************/
+
+typedef u8 boolean;
+typedef u8 signature[ MD5_SIGNATURE_BYTE_SIZE ];
+
+struct MD5Context
+ {
+ u32 buffer[ 4 ];
+ u32 bits[ 2 ];
+ signature intermediate;
+ };
+typedef struct MD5Context MD5Context;
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/*
+ * The four core functions - F1 is optimized somewhat
+ */
+#define F1( x, y, z ) ( z ^ ( x & ( y ^ z ) ) )
+#define F2( x, y, z ) F1( z, x, y )
+#define F3( x, y, z ) ( x ^ y ^ z )
+#define F4( x, y, z ) ( y ^ ( x | ~z ) )
+
+
+/*
+ * This is the central step in the MD5 algorithm
+ */
+#define MD5_STEP( f, w, x, y, z, data, s ) \
+ ( w += f( x, y, z ) + data, w = w << s | w >> ( 32 - s ), w += x )
+
+
+/************************** Function Prototypes ******************************/
+
+void * MD5Memset( void *dest, int ch, u32 count );
+
+void * MD5Memcpy( void *dest, const void *src, u32 count, boolean doByteSwap );
+
+void MD5Transform( u32 *buffer, u32 *intermediate );
+
+void MD5Init( MD5Context *context );
+
+void MD5Update( MD5Context *context, u8 *buffer, u32 len, boolean doByteSwap );
+
+void MD5Final( MD5Context *context, u8 *digest, boolean doByteSwap );
+
+void md5( u8 *input, u32 len, u8 *digest, boolean doByteSwap );
+
+/************************** Variable Definitions *****************************/
+
+#ifdef __cplusplus
+}
+#endif
+
+
+#endif /* ___MD5_H___ */
diff --git a/hello_world/sw/fsbl/nand.c b/hello_world/sw/fsbl/nand.c
new file mode 100644
index 0000000..484c184
--- /dev/null
+++ b/hello_world/sw/fsbl/nand.c
@@ -0,0 +1,289 @@
+/******************************************************************************
+*
+* Copyright (C) 2012 - 2014 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+* THE SOFTWARE.
+*
+*
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file nand.c
+*
+* Contains code for the NAND FLASH functionality. Bad Block management
+* is simple: skip the bad blocks and keep going.
+*
+* <pre>
+* MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ----- ---- -------- -------------------------------------------------------
+* 1.00a ecm 01/10/10 Initial release
+* 2.00a mb 25/05/12 fsbl changes for standalone bsp based
+* 3.00a sgd 30/01/13 Code cleanup
+* 5.00a sgd 17/05/13 Support for Multi Boot
+* </pre>
+*
+* @note
+*
+******************************************************************************/
+
+/***************************** Include Files *********************************/
+#include "xparameters.h"
+#include "fsbl.h"
+#ifdef XPAR_PS7_NAND_0_BASEADDR
+#include "nand.h"
+#include "xnandps_bbm.h"
+
+
+/************************** Constant Definitions *****************************/
+
+#define NAND_DEVICE_ID XPAR_XNANDPS_0_DEVICE_ID
+
+/**************************** Type Definitions *******************************/
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/************************** Function Prototypes ******************************/
+static u32 XNandPs_CalculateLength(XNandPs *NandInstPtr,
+ u64 Offset,
+ u32 Length);
+
+/************************** Variable Definitions *****************************/
+
+extern u32 FlashReadBaseAddress;
+extern u32 FlashOffsetAddress;
+
+XNandPs *NandInstPtr;
+XNandPs NandInstance; /* XNand Instance. */
+
+/******************************************************************************/
+/**
+*
+* This function initializes the controller for the NAND FLASH interface.
+*
+* @param none
+*
+* @return
+* - XST_SUCCESS if the controller initializes correctly
+* - XST_FAILURE if the controller fails to initializes correctly
+*
+* @note none.
+*
+****************************************************************************/
+u32 InitNand(void)
+{
+
+ u32 Status;
+ XNandPs_Config *ConfigPtr;
+
+ /*
+ * Set up pointers to instance and the config structure
+ */
+ NandInstPtr = &NandInstance;
+
+ /*
+ * Initialize the flash driver.
+ */
+ ConfigPtr = XNandPs_LookupConfig(NAND_DEVICE_ID);
+
+ if (ConfigPtr == NULL) {
+ fsbl_printf(DEBUG_GENERAL,"Nand Driver failed \n \r");
+ return XST_FAILURE;
+ }
+
+ Status = XNandPs_CfgInitialize(NandInstPtr, ConfigPtr,
+ ConfigPtr->SmcBase,ConfigPtr->FlashBase);
+ if (Status != XST_SUCCESS) {
+ fsbl_printf(DEBUG_GENERAL,"NAND initialization failed \n \r");
+ return XST_FAILURE;
+ }
+
+ /*
+ * Set up base address for access
+ */
+ FlashReadBaseAddress = XPS_NAND_BASEADDR;
+
+ fsbl_printf(DEBUG_INFO,"InitNand: Geometry = 0x%x\r\n",
+ NandInstPtr->Geometry.FlashWidth);
+
+ if (Status != XST_SUCCESS) {
+ fsbl_printf(DEBUG_GENERAL,"InitNand: Status = 0x%.8x\r\n",
+ Status);
+ return XST_FAILURE;
+ }
+
+ /*
+ * set up the FLASH access pointers
+ */
+ fsbl_printf(DEBUG_INFO,"Nand driver initialized \n\r");
+
+ return XST_SUCCESS;
+}
+
+/******************************************************************************/
+/**
+*
+* This function provides the NAND FLASH interface for the Simplified header
+* functionality. This function handles bad blocks.
+*
+* The source address is the absolute good address, bad blocks are skipped
+* without incrementing the source address.
+*
+* @param SourceAddress is address in FLASH data space, absolute good address
+* @param DestinationAddress is address in OCM data space
+*
+* @return XST_SUCCESS if the transfer completes correctly
+* XST_FAILURE if the transfer fails to completes correctly
+*
+* @note none.
+*
+****************************************************************************/
+u32 NandAccess(u32 SourceAddress, u32 DestinationAddress, u32 LengthBytes)
+{
+ u32 ActLen;
+ u32 BlockOffset;
+ u32 Block;
+ u32 Status;
+ u32 BytesLeft = LengthBytes;
+ u32 BlockSize = NandInstPtr->Geometry.BlockSize;
+ u8 *BufPtr = (u8 *)DestinationAddress;
+ u32 ReadLen;
+ u32 BlockReadLen;
+ u32 Offset;
+ u32 TmpAddress = 0 ;
+ u32 BlockCount = 0;
+ u32 BadBlocks = 0;
+
+ /*
+ * First get bad blocks before the source address
+ */
+ while (TmpAddress < SourceAddress) {
+ while (XNandPs_IsBlockBad(NandInstPtr, BlockCount) ==
+ XST_SUCCESS) {
+ BlockCount ++;
+ BadBlocks ++;
+ }
+
+ TmpAddress += BlockSize;
+ BlockCount ++;
+ }
+
+ Offset = SourceAddress + BadBlocks * BlockSize;
+
+ /*
+ * Calculate the actual length including bad blocks
+ */
+ ActLen = XNandPs_CalculateLength(NandInstPtr, Offset, LengthBytes);
+
+ /*
+ * Check if the actual length cross flash size
+ */
+ if (Offset + ActLen > NandInstPtr->Geometry.DeviceSize) {
+ return XST_FAILURE;
+ }
+
+ while (BytesLeft > 0) {
+ BlockOffset = Offset & (BlockSize - 1);
+ Block = (Offset & ~(BlockSize - 1))/BlockSize;
+ BlockReadLen = BlockSize - BlockOffset;
+
+ Status = XNandPs_IsBlockBad(NandInstPtr, Block);
+ if (Status == XST_SUCCESS) {
+ /* Move to next block */
+ Offset += BlockReadLen;
+ continue;
+ }
+
+ /*
+ * Check if we cross block boundary
+ */
+ if (BytesLeft < BlockReadLen) {
+ ReadLen = BytesLeft;
+ } else {
+ ReadLen = BlockReadLen;
+ }
+
+ /*
+ * Read from the NAND flash
+ */
+ Status = XNandPs_Read(NandInstPtr, Offset, ReadLen, BufPtr, NULL);
+ if (Status != XST_SUCCESS) {
+ return Status;
+ }
+ BytesLeft -= ReadLen;
+ Offset += ReadLen;
+ BufPtr += ReadLen;
+ }
+
+ return XST_SUCCESS;
+}
+
+/*****************************************************************************/
+/**
+*
+* This function returns the length including bad blocks from a given offset and
+* length.
+*
+* @param NandInstPtr is the pointer to the XNandPs instance.
+* @param Offset is the flash data address to read from.
+* @param Length is number of bytes to read.
+*
+* @return
+* - Return actual length including bad blocks.
+*
+* @note None.
+*
+******************************************************************************/
+static u32 XNandPs_CalculateLength(XNandPs *NandInstPtr,
+ u64 Offset,
+ u32 Length)
+{
+ u32 BlockSize = NandInstPtr->Geometry.BlockSize;
+ u32 CurBlockLen;
+ u32 CurBlock;
+ u32 Status;
+ u32 TempLen = 0;
+ u32 ActLen = 0;
+
+ while (TempLen < Length) {
+ CurBlockLen = BlockSize - (Offset & (BlockSize - 1));
+ CurBlock = (Offset & ~(BlockSize - 1))/BlockSize;
+
+ /*
+ * Check if the block is bad
+ */
+ Status = XNandPs_IsBlockBad(NandInstPtr, CurBlock);
+ if (Status != XST_SUCCESS) {
+ /* Good Block */
+ TempLen += CurBlockLen;
+ }
+ ActLen += CurBlockLen;
+ Offset += CurBlockLen;
+ if (Offset >= NandInstPtr->Geometry.DeviceSize) {
+ break;
+ }
+ }
+
+ return ActLen;
+}
+
+#endif
diff --git a/hello_world/sw/fsbl/nand.h b/hello_world/sw/fsbl/nand.h
new file mode 100644
index 0000000..1542c77
--- /dev/null
+++ b/hello_world/sw/fsbl/nand.h
@@ -0,0 +1,85 @@
+/******************************************************************************
+*
+* Copyright (C) 2012 - 2014 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+* THE SOFTWARE.
+*
+*
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file nand.h
+*
+* This file contains the interface for the NAND FLASH functionality
+*
+* <pre>
+* MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ----- ---- -------- -------------------------------------------------------
+* 1.00a ecm 01/10/10 Initial release
+* 2.00a mb 30/05/12 added the flag XPAR_PS7_NAND_0_BASEADDR
+* 10.00a kc 08/04/14 Fix for CR#809336 - Removed smc.h
+* </pre>
+*
+* @note
+*
+******************************************************************************/
+#ifndef ___NAND_H___
+#define ___NAND_H___
+
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/***************************** Include Files *********************************/
+
+
+#ifdef XPAR_PS7_NAND_0_BASEADDR
+
+#include "xnandps.h"
+#include "xnandps_bbm.h"
+/**************************** Type Definitions *******************************/
+
+/************************** Constant Definitions *****************************/
+
+/**************************** Type Definitions *******************************/
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/************************** Function Prototypes ******************************/
+u32 InitNand(void);
+
+u32 NandAccess( u32 SourceAddress,
+ u32 DestinationAddress,
+ u32 LengthWords);
+#endif
+/************************** Variable Definitions *****************************/
+
+
+#ifdef __cplusplus
+}
+#endif
+
+
+#endif /* ___NAND_H___ */
+
diff --git a/hello_world/sw/fsbl/nor.c b/hello_world/sw/fsbl/nor.c
new file mode 100644
index 0000000..1253fe6
--- /dev/null
+++ b/hello_world/sw/fsbl/nor.c
@@ -0,0 +1,138 @@
+/******************************************************************************
+*
+* Copyright (C) 2012 - 2014 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+* THE SOFTWARE.
+*
+*
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file nor.c
+*
+* Contains code for the NOR FLASH functionality.
+*
+* <pre>
+* MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ----- ---- -------- -------------------------------------------------------
+* 1.00a ecm 01/10/10 Initial release
+* 2.00a mb 25/05/12 mio init removed
+* 3.00a sgd 30/01/13 Code cleanup
+*
+* </pre>
+*
+* @note
+*
+******************************************************************************/
+
+/***************************** Include Files *********************************/
+#include "fsbl.h"
+#include "nor.h"
+#include "xstatus.h"
+
+/************************** Constant Definitions *****************************/
+
+/**************************** Type Definitions *******************************/
+
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/************************** Function Prototypes ******************************/
+
+/************************** Variable Definitions *****************************/
+
+extern u32 FlashReadBaseAddress;
+
+/******************************************************************************/
+/******************************************************************************/
+/**
+*
+* This function initializes the controller for the NOR FLASH interface.
+*
+* @param None
+*
+* @return None
+*
+* @note None.
+*
+****************************************************************************/
+void InitNor(void)
+{
+
+ /*
+ * Set up the base address for access
+ */
+ FlashReadBaseAddress = XPS_NOR_BASEADDR;
+}
+
+/******************************************************************************/
+/**
+*
+* This function provides the NOR FLASH interface for the Simplified header
+* functionality.
+*
+* @param SourceAddress is address in FLASH data space
+* @param DestinationAddress is address in OCM data space
+* @param LengthBytes is the data length to transfer in bytes
+*
+* @return
+* - XST_SUCCESS if the write completes correctly
+* - XST_FAILURE if the write fails to completes correctly
+*
+* @note None.
+*
+****************************************************************************/
+u32 NorAccess(u32 SourceAddress, u32 DestinationAddress, u32 LengthBytes)
+{
+ u32 Data;
+ u32 Count;
+ u32 *SourceAddr;
+ u32 *DestAddr;
+ u32 LengthWords;
+
+ /*
+ * check for non-word tail
+ * add bytes to cover the end
+ */
+ if ((LengthBytes%4) != 0){
+
+ LengthBytes += (4 - (LengthBytes & 0x00000003));
+ }
+
+ LengthWords = LengthBytes >> WORD_LENGTH_SHIFT;
+
+ SourceAddr = (u32 *)(SourceAddress + FlashReadBaseAddress);
+ DestAddr = (u32 *)(DestinationAddress);
+
+ /*
+ * Word transfers, endianism isn't an issue
+ */
+ for (Count=0; Count < LengthWords; Count++){
+
+ Data = Xil_In32((u32)(SourceAddr++));
+ Xil_Out32((u32)(DestAddr++), Data);
+ }
+
+ return XST_SUCCESS;
+}
+
diff --git a/hello_world/sw/fsbl/nor.h b/hello_world/sw/fsbl/nor.h
new file mode 100644
index 0000000..49aae66
--- /dev/null
+++ b/hello_world/sw/fsbl/nor.h
@@ -0,0 +1,81 @@
+/******************************************************************************
+*
+* Copyright (C) 2012 - 2014 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+* THE SOFTWARE.
+*
+*
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file nor.h
+*
+* This file contains the interface for the NOR FLASH functionality
+*
+* <pre>
+* MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ----- ---- -------- -------------------------------------------------------
+* 1.00a ecm 01/10/10 Initial release
+* 10.00a kc 08/04/14 Fix for CR#809336 - Removed smc.h
+*
+* </pre>
+*
+* @note
+*
+******************************************************************************/
+#ifndef ___NOR_H___
+#define ___NOR_H___
+
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/***************************** Include Files *********************************/
+
+/************************** Constant Definitions *****************************/
+
+#define XPS_NOR_BASEADDR XPS_PARPORT0_BASEADDR
+
+/**************************** Type Definitions *******************************/
+
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/************************** Function Prototypes ******************************/
+
+
+void InitNor(void);
+
+u32 NorAccess( u32 SourceAddress,
+ u32 DestinationAddress,
+ u32 LengthBytes);
+
+/************************** Variable Definitions *****************************/
+#ifdef __cplusplus
+}
+#endif
+
+
+#endif /* ___NOR_H___ */
+
diff --git a/hello_world/sw/fsbl/pcap.c b/hello_world/sw/fsbl/pcap.c
new file mode 100644
index 0000000..ea8d7e6
--- /dev/null
+++ b/hello_world/sw/fsbl/pcap.c
@@ -0,0 +1,810 @@
+/*****************************************************************************
+*
+* Copyright (C) 2012 - 2016 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+* THE SOFTWARE.
+*
+*
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file pcap.c
+*
+* Contains code for enabling and accessing the PCAP
+*
+* <pre>
+* MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ----- ---- -------- -------------------------------------------------------
+* 1.00a ecm 02/10/10 Initial release
+* 2.00a jz 05/28/11 Add SD support
+* 2.00a mb 25/05/12 using the EDK provided devcfg driver
+* Nand/SD encryption and review comments
+* 3.00a mb 16/08/12 Added the poll function
+* Removed the FPGA_RST_CTRL define
+* Added the flag for NON PS instantiated bitstream
+* 4.00a sgd 02/28/13 Fix for CR#681014 - ECC init in FSBL should not call
+* fabric_init()
+* Fix for CR#689026 - FSBL doesn't hold PL resets active
+* during bit download
+* Fix for CR#699475 - FSBL functionality is broken and
+* its not able to boot in QSPI/NAND
+* bootmode
+* Fix for CR#705664 - FSBL fails to decrypt the
+* bitstream when the image is AES
+* encrypted using non-zero key value
+* 6.00a kc 08/30/13 Fix for CR#722979 - Provide customer-friendly
+* changelogs in FSBL
+* 7.00a kc 10/25/13 Fix for CR#724620 - How to handle PCAP_MODE after
+* bitstream configuration
+* Fix for CR#726178 - FabricInit() PROG_B is kept active
+* for 5mS.
+* Fix for CR#731839 - FSBL has to check the
+* HMAC error status after decryption
+* 12/04/13 Fix for CR#764382 - How to handle PCAP_MODE after
+* bitstream configuration - PCAP_MODE
+* and PCAP_PR bits are not modified
+* 8.00a kc 2/20/14 Fix for CR#775631 - FSBL: FsblGetGlobalTimer()
+* is not proper
+* 10.00a kc 07/24/14 Fix for CR#809336 - Minor code cleanup
+* 13.00a ssc 04/10/15 Fix for CR#846899 - Corrected logic to clear
+* DMA done count
+* 15.00a gan 07/21/16 Fix for CR# 953654 -(2016.3)FSBL -
+* In pcap.c/pcap.h/main.h,
+* Fabric Initialization sequence
+* is modified to check the PL power
+* before sequence starts and checking
+* INIT_B reset status twice in case
+* of failure.
+* 16.00a gan 08/02/16 Fix for CR# 955897 -(2016.3)FSBL -
+* In pcap.c, check pl power
+* through MCTRL register for
+* 3.0 and later versions of silicon.
+* </pre>
+*
+* @note
+*
+******************************************************************************/
+
+/***************************** Include Files *********************************/
+
+#include "pcap.h"
+#include "nand.h" /* For NAND geometry information */
+#include "fsbl.h"
+#include "image_mover.h" /* For MoveImage */
+#include "xparameters.h"
+#include "xil_exception.h"
+#include "xdevcfg.h"
+#include "sleep.h"
+#include "xtime_l.h"
+
+#ifdef XPAR_XWDTPS_0_BASEADDR
+#include "xwdtps.h"
+#endif
+/************************** Constant Definitions *****************************/
+/*
+ * The following constants map to the XPAR parameters created in the
+ * xparameters.h file. They are only defined here such that a user can easily
+ * change all the needed parameters in one place.
+ */
+
+#define DCFG_DEVICE_ID XPAR_XDCFG_0_DEVICE_ID
+
+/**************************** Type Definitions *******************************/
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/************************** Function Prototypes ******************************/
+extern int XDcfgPollDone(u32 MaskValue, u32 MaxCount);
+
+/************************** Variable Definitions *****************************/
+/* Devcfg driver instance */
+static XDcfg DcfgInstance;
+XDcfg *DcfgInstPtr;
+extern u32 Silicon_Version;
+#ifdef XPAR_XWDTPS_0_BASEADDR
+extern XWdtPs Watchdog; /* Instance of WatchDog Timer */
+#endif
+
+/******************************************************************************/
+/**
+*
+* This function transfer data using PCAP
+*
+* @param SourceDataPtr is a pointer to where the data is read from
+* @param DestinationDataPtr is a pointer to where the data is written to
+* @param SourceLength is the length of the data to be moved in words
+* @param DestinationLength is the length of the data to be moved in words
+* @param SecureTransfer indicated the encryption key location, 0 for
+* non-encrypted
+*
+* @return
+* - XST_SUCCESS if the transfer is successful
+* - XST_FAILURE if the transfer fails
+*
+* @note None
+*
+****************************************************************************/
+u32 PcapDataTransfer(u32 *SourceDataPtr, u32 *DestinationDataPtr,
+ u32 SourceLength, u32 DestinationLength, u32 SecureTransfer)
+{
+ u32 Status;
+ u32 IntrStsReg;
+ u32 PcapTransferType = XDCFG_CONCURRENT_NONSEC_READ_WRITE;
+
+ /*
+ * Check for secure transfer
+ */
+ if (SecureTransfer) {
+ PcapTransferType = XDCFG_CONCURRENT_SECURE_READ_WRITE;
+ }
+
+#ifdef FSBL_PERF
+ XTime tXferCur = 0;
+ FsblGetGlobalTime(&tXferCur);
+#endif
+
+ /*
+ * Clear the PCAP status registers
+ */
+ Status = ClearPcapStatus();
+ if (Status != XST_SUCCESS) {
+ fsbl_printf(DEBUG_INFO,"PCAP_CLEAR_STATUS_FAIL \r\n");
+ return XST_FAILURE;
+ }
+
+#ifdef XPAR_XWDTPS_0_BASEADDR
+ /*
+ * Prevent WDT reset
+ */
+ XWdtPs_RestartWdt(&Watchdog);
+#endif
+
+ /*
+ * PCAP single DMA transfer setup
+ */
+ SourceDataPtr = (u32*)((u32)SourceDataPtr | PCAP_LAST_TRANSFER);
+ DestinationDataPtr = (u32*)((u32)DestinationDataPtr | PCAP_LAST_TRANSFER);
+
+ /*
+ * Transfer using Device Configuration
+ */
+ Status = XDcfg_Transfer(DcfgInstPtr, (u8 *)SourceDataPtr,
+ SourceLength,
+ (u8 *)DestinationDataPtr,
+ DestinationLength, PcapTransferType);
+ if (Status != XST_SUCCESS) {
+ fsbl_printf(DEBUG_INFO,"Status of XDcfg_Transfer = %lu \r \n",Status);
+ return XST_FAILURE;
+ }
+
+ /*
+ * Dump the PCAP registers
+ */
+ PcapDumpRegisters();
+
+ /*
+ * Poll for the DMA done
+ */
+ Status = XDcfgPollDone(XDCFG_IXR_DMA_DONE_MASK, MAX_COUNT);
+ if (Status != XST_SUCCESS) {
+ fsbl_printf(DEBUG_INFO,"PCAP_DMA_DONE_FAIL \r\n");
+ return XST_FAILURE;
+ }
+
+ fsbl_printf(DEBUG_INFO,"DMA Done ! \n\r");
+
+ /*
+ * Check for errors
+ */
+ IntrStsReg = XDcfg_IntrGetStatus(DcfgInstPtr);
+ if (IntrStsReg & FSBL_XDCFG_IXR_ERROR_FLAGS_MASK) {
+ fsbl_printf(DEBUG_INFO,"Errors in PCAP \r\n");
+ return XST_FAILURE;
+ }
+
+ /*
+ * For Performance measurement
+ */
+#ifdef FSBL_PERF
+ XTime tXferEnd = 0;
+ fsbl_printf(DEBUG_GENERAL,"Time taken is ");
+ FsblMeasurePerfTime(tXferCur,tXferEnd);
+#endif
+
+ return XST_SUCCESS;
+}
+
+
+/******************************************************************************/
+/**
+*
+* This function loads PL partition using PCAP
+*
+* @param SourceDataPtr is a pointer to where the data is read from
+* @param DestinationDataPtr is a pointer to where the data is written to
+* @param SourceLength is the length of the data to be moved in words
+* @param DestinationLength is the length of the data to be moved in words
+* @param SecureTransfer indicated the encryption key location, 0 for
+* non-encrypted
+*
+* @return
+* - XST_SUCCESS if the transfer is successful
+* - XST_FAILURE if the transfer fails
+*
+* @note None
+*
+****************************************************************************/
+u32 PcapLoadPartition(u32 *SourceDataPtr, u32 *DestinationDataPtr,
+ u32 SourceLength, u32 DestinationLength, u32 SecureTransfer)
+{
+ u32 Status;
+ u32 IntrStsReg;
+ u32 PcapTransferType = XDCFG_NON_SECURE_PCAP_WRITE;
+
+ /*
+ * Check for secure transfer
+ */
+ if (SecureTransfer) {
+ PcapTransferType = XDCFG_SECURE_PCAP_WRITE;
+ }
+
+#ifdef FSBL_PERF
+ XTime tXferCur = 0;
+ FsblGetGlobalTime(&tXferCur);
+#endif
+
+ /*
+ * Clear the PCAP status registers
+ */
+ Status = ClearPcapStatus();
+ if (Status != XST_SUCCESS) {
+ fsbl_printf(DEBUG_INFO,"PCAP_CLEAR_STATUS_FAIL \r\n");
+ return XST_FAILURE;
+ }
+
+ /*
+ * For Bitstream case destination address will be 0xFFFFFFFF
+ */
+ DestinationDataPtr = (u32*)XDCFG_DMA_INVALID_ADDRESS;
+
+ /*
+ * New Bitstream download initialization sequence
+ */
+ Status = FabricInit();
+ if (Status != XST_SUCCESS) {
+ return XST_FAILURE;
+ }
+
+
+#ifdef XPAR_XWDTPS_0_BASEADDR
+ /*
+ * Prevent WDT reset
+ */
+ XWdtPs_RestartWdt(&Watchdog);
+#endif
+
+ /*
+ * PCAP single DMA transfer setup
+ */
+ SourceDataPtr = (u32*)((u32)SourceDataPtr | PCAP_LAST_TRANSFER);
+ DestinationDataPtr = (u32*)((u32)DestinationDataPtr | PCAP_LAST_TRANSFER);
+
+ /*
+ * Transfer using Device Configuration
+ */
+ Status = XDcfg_Transfer(DcfgInstPtr, (u8 *)SourceDataPtr,
+ SourceLength,
+ (u8 *)DestinationDataPtr,
+ DestinationLength, PcapTransferType);
+ if (Status != XST_SUCCESS) {
+ fsbl_printf(DEBUG_INFO,"Status of XDcfg_Transfer = %lu \r \n",Status);
+ return XST_FAILURE;
+ }
+
+
+ /*
+ * Dump the PCAP registers
+ */
+ PcapDumpRegisters();
+
+
+ /*
+ * Poll for the DMA done
+ */
+ Status = XDcfgPollDone(XDCFG_IXR_DMA_DONE_MASK, MAX_COUNT);
+ if (Status != XST_SUCCESS) {
+ fsbl_printf(DEBUG_INFO,"PCAP_DMA_DONE_FAIL \r\n");
+ return XST_FAILURE;
+ }
+
+ fsbl_printf(DEBUG_INFO,"DMA Done ! \n\r");
+
+ /*
+ * Poll for FPGA Done
+ */
+ Status = XDcfgPollDone(XDCFG_IXR_PCFG_DONE_MASK, MAX_COUNT);
+ if (Status != XST_SUCCESS) {
+ fsbl_printf(DEBUG_INFO,"PCAP_FPGA_DONE_FAIL\r\n");
+ return XST_FAILURE;
+ }
+
+ fsbl_printf(DEBUG_INFO,"FPGA Done ! \n\r");
+
+ /*
+ * Check for errors
+ */
+ IntrStsReg = XDcfg_IntrGetStatus(DcfgInstPtr);
+ if (IntrStsReg & FSBL_XDCFG_IXR_ERROR_FLAGS_MASK) {
+ fsbl_printf(DEBUG_INFO,"Errors in PCAP \r\n");
+ return XST_FAILURE;
+ }
+
+ /*
+ * For Performance measurement
+ */
+#ifdef FSBL_PERF
+ XTime tXferEnd = 0;
+ fsbl_printf(DEBUG_GENERAL,"Time taken is ");
+ FsblMeasurePerfTime(tXferCur,tXferEnd);
+#endif
+
+ return XST_SUCCESS;
+}
+
+/******************************************************************************/
+/**
+*
+* This function Initializes the PCAP driver.
+*
+* @param none
+*
+* @return
+* - XST_SUCCESS if the pcap driver initialization is successful
+* - XST_FAILURE if the pcap driver initialization fails
+*
+* @note none
+*
+****************************************************************************/
+int InitPcap(void)
+{
+ XDcfg_Config *ConfigPtr;
+ int Status = XST_SUCCESS;
+ DcfgInstPtr = &DcfgInstance;
+
+ /*
+ * Initialize the Device Configuration Interface driver.
+ */
+ ConfigPtr = XDcfg_LookupConfig(DCFG_DEVICE_ID);
+
+ Status = XDcfg_CfgInitialize(DcfgInstPtr, ConfigPtr,
+ ConfigPtr->BaseAddr);
+ if (Status != XST_SUCCESS) {
+ fsbl_printf(DEBUG_INFO, "XDcfg_CfgInitialize failed \n\r");
+ return XST_FAILURE;
+ }
+
+ return XST_SUCCESS;
+}
+/******************************************************************************/
+/**
+*
+* This function programs the Fabric for use.
+*
+* @param None
+*
+* @return
+* - XST_SUCCESS if the Fabric initialization is successful
+* - XST_FAILURE if the Fabric initialization fails
+* @note None
+*
+****************************************************************************/
+u32 FabricInit(void)
+{
+ u32 PcapReg;
+ u32 PcapCtrlRegVal;
+ u32 StatusReg;
+ u32 MctrlReg;
+ u32 PcfgInit;
+ u32 TimerExpired=0;
+ XTime tCur=0;
+ XTime tEnd=0;
+
+
+ /*
+ * Set Level Shifters DT618760 - PS to PL enabling
+ */
+ Xil_Out32(PS_LVL_SHFTR_EN, LVL_PS_PL);
+ fsbl_printf(DEBUG_INFO,"Level Shifter Value = 0x%lx \r\n",
+ Xil_In32(PS_LVL_SHFTR_EN));
+
+ /*
+ * Get DEVCFG controller settings
+ */
+ PcapReg = XDcfg_ReadReg(DcfgInstPtr->Config.BaseAddr,
+ XDCFG_CTRL_OFFSET);
+
+ /*
+ * Check the PL power status
+ */
+ if(Silicon_Version >= SILICON_VERSION_3)
+ {
+ MctrlReg = XDcfg_GetMiscControlRegister(DcfgInstPtr);
+
+ if((MctrlReg & XDCFG_MCTRL_PCAP_PCFG_POR_B_MASK) !=
+ XDCFG_MCTRL_PCAP_PCFG_POR_B_MASK)
+ {
+ fsbl_printf(DEBUG_INFO,"Fabric not powered up\r\n");
+ return XST_FAILURE;
+ }
+ }
+
+
+ /*
+ * Setting PCFG_PROG_B signal to high
+ */
+ XDcfg_WriteReg(DcfgInstPtr->Config.BaseAddr, XDCFG_CTRL_OFFSET,
+ (PcapReg | XDCFG_CTRL_PCFG_PROG_B_MASK));
+
+ /*
+ * Check for AES source key
+ */
+ PcapCtrlRegVal = XDcfg_GetControlRegister(DcfgInstPtr);
+ if (PcapCtrlRegVal & XDCFG_CTRL_PCFG_AES_FUSE_MASK) {
+ /*
+ * 5msec delay
+ */
+ usleep(5000);
+ }
+
+ /*
+ * Setting PCFG_PROG_B signal to low
+ */
+ XDcfg_WriteReg(DcfgInstPtr->Config.BaseAddr, XDCFG_CTRL_OFFSET,
+ (PcapReg & ~XDCFG_CTRL_PCFG_PROG_B_MASK));
+
+ /*
+ * Check for AES source key
+ */
+ if (PcapCtrlRegVal & XDCFG_CTRL_PCFG_AES_FUSE_MASK) {
+ /*
+ * 5msec delay
+ */
+ usleep(5000);
+ }
+
+ /*
+ * Polling the PCAP_INIT status for Reset or timeout
+ */
+
+ XTime_GetTime(&tCur);
+ do
+ {
+ PcfgInit = (XDcfg_GetStatusRegister(DcfgInstPtr) &
+ XDCFG_STATUS_PCFG_INIT_MASK);
+ if(PcfgInit == 0)
+ {
+ break;
+ }
+ XTime_GetTime(&tEnd);
+ if((u64)((u64)tCur + (COUNTS_PER_MILLI_SECOND*30)) > (u64)tEnd)
+ {
+ TimerExpired = 1;
+ }
+
+ } while(!TimerExpired);
+
+ if(TimerExpired == 1)
+ {
+ TimerExpired = 0;
+ /*
+ * Came here due to expiration and PCAP_INIT is set.
+ * Retry PCFG_PROG_B High -> Low again
+ */
+
+ /*
+ * Setting PCFG_PROG_B signal to high
+ */
+ XDcfg_WriteReg(DcfgInstPtr->Config.BaseAddr, XDCFG_CTRL_OFFSET,
+ (PcapReg | XDCFG_CTRL_PCFG_PROG_B_MASK));
+
+ /*
+ * Check for AES source key
+ */
+ PcapCtrlRegVal = XDcfg_GetControlRegister(DcfgInstPtr);
+ if (PcapCtrlRegVal & XDCFG_CTRL_PCFG_AES_FUSE_MASK) {
+ /*
+ * 5msec delay
+ */
+ usleep(5000);
+ }
+
+ /*
+ * Setting PCFG_PROG_B signal to low
+ */
+ XDcfg_WriteReg(DcfgInstPtr->Config.BaseAddr, XDCFG_CTRL_OFFSET,
+ (PcapReg & ~XDCFG_CTRL_PCFG_PROG_B_MASK));
+
+ /*
+ * Check for AES source key
+ */
+ if (PcapCtrlRegVal & XDCFG_CTRL_PCFG_AES_FUSE_MASK) {
+ /*
+ * 5msec delay
+ */
+ usleep(5000);
+ }
+ /*
+ * Polling the PCAP_INIT status for Reset or timeout (second iteration)
+ */
+
+ XTime_GetTime(&tCur);
+ do
+ {
+ PcfgInit = (XDcfg_GetStatusRegister(DcfgInstPtr) &
+ XDCFG_STATUS_PCFG_INIT_MASK);
+ if(PcfgInit == 0)
+ {
+ break;
+ }
+ XTime_GetTime(&tEnd);
+ if((u64)((u64)tCur + (COUNTS_PER_MILLI_SECOND*30)) > (u64)tEnd)
+ {
+ TimerExpired = 1;
+ }
+
+ } while(!TimerExpired);
+
+ if(TimerExpired == 1)
+ {
+ /*
+ * Came here due to PCAP_INIT is not getting reset
+ * for PCFG_PROG_B signal High -> Low
+ */
+ fsbl_printf(DEBUG_INFO,"Fabric Init failed\r\n");
+ return XST_FAILURE;
+ }
+ }
+
+ /*
+ * Setting PCFG_PROG_B signal to high
+ */
+ XDcfg_WriteReg(DcfgInstPtr->Config.BaseAddr, XDCFG_CTRL_OFFSET,
+ (PcapReg | XDCFG_CTRL_PCFG_PROG_B_MASK));
+
+ /*
+ * Polling the PCAP_INIT status for Set
+ */
+ while(!(XDcfg_GetStatusRegister(DcfgInstPtr) &
+ XDCFG_STATUS_PCFG_INIT_MASK));
+
+ /*
+ * Get Device configuration status
+ */
+ StatusReg = XDcfg_GetStatusRegister(DcfgInstPtr);
+ fsbl_printf(DEBUG_INFO,"Devcfg Status register = 0x%lx \r\n",StatusReg);
+
+ fsbl_printf(DEBUG_INFO,"PCAP:Fabric is Initialized done\r\n");
+
+ return XST_SUCCESS;
+}
+/******************************************************************************/
+/**
+*
+* This function Clears the PCAP status registers.
+*
+* @param None
+*
+* @return
+* - XST_SUCCESS if the pcap status registers are cleared
+* - XST_FAILURE if errors are there
+* - XST_DEVICE_BUSY if Pcap device is busy
+* @note None
+*
+****************************************************************************/
+u32 ClearPcapStatus(void)
+{
+
+ u32 StatusReg;
+ u32 IntStatusReg;
+
+ /*
+ * Clear it all, so if Boot ROM comes back, it can proceed
+ */
+ XDcfg_IntrClear(DcfgInstPtr, 0xFFFFFFFF);
+
+ /*
+ * Get PCAP Interrupt Status Register
+ */
+ IntStatusReg = XDcfg_IntrGetStatus(DcfgInstPtr);
+ if (IntStatusReg & FSBL_XDCFG_IXR_ERROR_FLAGS_MASK) {
+ fsbl_printf(DEBUG_INFO,"FATAL errors in PCAP %lx\r\n",
+ IntStatusReg);
+ return XST_FAILURE;
+ }
+
+ /*
+ * Read the PCAP status register for DMA status
+ */
+ StatusReg = XDcfg_GetStatusRegister(DcfgInstPtr);
+
+ fsbl_printf(DEBUG_INFO,"PCAP:StatusReg = 0x%.8lx\r\n", StatusReg);
+
+ /*
+ * If the queue is full, return w/ XST_DEVICE_BUSY
+ */
+ if ((StatusReg & XDCFG_STATUS_DMA_CMD_Q_F_MASK) ==
+ XDCFG_STATUS_DMA_CMD_Q_F_MASK) {
+
+ fsbl_printf(DEBUG_INFO,"PCAP_DEVICE_BUSY\r\n");
+ return XST_DEVICE_BUSY;
+ }
+
+ fsbl_printf(DEBUG_INFO,"PCAP:device ready\r\n");
+
+ /*
+ * There are unacknowledged DMA commands outstanding
+ */
+ if ((StatusReg & XDCFG_STATUS_DMA_CMD_Q_E_MASK) !=
+ XDCFG_STATUS_DMA_CMD_Q_E_MASK) {
+
+ IntStatusReg = XDcfg_IntrGetStatus(DcfgInstPtr);
+
+ if ((IntStatusReg & XDCFG_IXR_DMA_DONE_MASK) !=
+ XDCFG_IXR_DMA_DONE_MASK){
+ /*
+ * Error state, transfer cannot occur
+ */
+ fsbl_printf(DEBUG_INFO,"PCAP:IntStatus indicates error\r\n");
+ return XST_FAILURE;
+ }
+ else {
+ /*
+ * clear out the status
+ */
+ XDcfg_IntrClear(DcfgInstPtr, XDCFG_IXR_DMA_DONE_MASK);
+ }
+ }
+
+ if ((StatusReg & XDCFG_STATUS_DMA_DONE_CNT_MASK) != 0) {
+ XDcfg_SetStatusRegister(DcfgInstPtr, StatusReg |
+ XDCFG_STATUS_DMA_DONE_CNT_MASK);
+ }
+
+ fsbl_printf(DEBUG_INFO,"PCAP:Clear done\r\n");
+
+ return XST_SUCCESS;
+}
+
+/******************************************************************************/
+/**
+*
+* This function prints PCAP register status.
+*
+* @param none
+*
+* @return none
+*
+* @note none
+*
+****************************************************************************/
+void PcapDumpRegisters (void) {
+
+ fsbl_printf(DEBUG_INFO,"PCAP register dump:\r\n");
+
+ fsbl_printf(DEBUG_INFO,"PCAP CTRL 0x%x: 0x%08lx\r\n",
+ XPS_DEV_CFG_APB_BASEADDR + XDCFG_CTRL_OFFSET,
+ Xil_In32(XPS_DEV_CFG_APB_BASEADDR + XDCFG_CTRL_OFFSET));
+ fsbl_printf(DEBUG_INFO,"PCAP LOCK 0x%x: 0x%08lx\r\n",
+ XPS_DEV_CFG_APB_BASEADDR + XDCFG_LOCK_OFFSET,
+ Xil_In32(XPS_DEV_CFG_APB_BASEADDR + XDCFG_LOCK_OFFSET));
+ fsbl_printf(DEBUG_INFO,"PCAP CONFIG 0x%x: 0x%08lx\r\n",
+ XPS_DEV_CFG_APB_BASEADDR + XDCFG_CFG_OFFSET,
+ Xil_In32(XPS_DEV_CFG_APB_BASEADDR + XDCFG_CFG_OFFSET));
+ fsbl_printf(DEBUG_INFO,"PCAP ISR 0x%x: 0x%08lx\r\n",
+ XPS_DEV_CFG_APB_BASEADDR + XDCFG_INT_STS_OFFSET,
+ Xil_In32(XPS_DEV_CFG_APB_BASEADDR + XDCFG_INT_STS_OFFSET));
+ fsbl_printf(DEBUG_INFO,"PCAP IMR 0x%x: 0x%08lx\r\n",
+ XPS_DEV_CFG_APB_BASEADDR + XDCFG_INT_MASK_OFFSET,
+ Xil_In32(XPS_DEV_CFG_APB_BASEADDR + XDCFG_INT_MASK_OFFSET));
+ fsbl_printf(DEBUG_INFO,"PCAP STATUS 0x%x: 0x%08lx\r\n",
+ XPS_DEV_CFG_APB_BASEADDR + XDCFG_STATUS_OFFSET,
+ Xil_In32(XPS_DEV_CFG_APB_BASEADDR + XDCFG_STATUS_OFFSET));
+ fsbl_printf(DEBUG_INFO,"PCAP DMA SRC ADDR 0x%x: 0x%08lx\r\n",
+ XPS_DEV_CFG_APB_BASEADDR + XDCFG_DMA_SRC_ADDR_OFFSET,
+ Xil_In32(XPS_DEV_CFG_APB_BASEADDR + XDCFG_DMA_SRC_ADDR_OFFSET));
+ fsbl_printf(DEBUG_INFO,"PCAP DMA DEST ADDR 0x%x: 0x%08lx\r\n",
+ XPS_DEV_CFG_APB_BASEADDR + XDCFG_DMA_DEST_ADDR_OFFSET,
+ Xil_In32(XPS_DEV_CFG_APB_BASEADDR + XDCFG_DMA_DEST_ADDR_OFFSET));
+ fsbl_printf(DEBUG_INFO,"PCAP DMA SRC LEN 0x%x: 0x%08lx\r\n",
+ XPS_DEV_CFG_APB_BASEADDR + XDCFG_DMA_SRC_LEN_OFFSET,
+ Xil_In32(XPS_DEV_CFG_APB_BASEADDR + XDCFG_DMA_SRC_LEN_OFFSET));
+ fsbl_printf(DEBUG_INFO,"PCAP DMA DEST LEN 0x%x: 0x%08lx\r\n",
+ XPS_DEV_CFG_APB_BASEADDR + XDCFG_DMA_DEST_LEN_OFFSET,
+ Xil_In32(XPS_DEV_CFG_APB_BASEADDR + XDCFG_DMA_DEST_LEN_OFFSET));
+ fsbl_printf(DEBUG_INFO,"PCAP ROM SHADOW CTRL 0x%x: 0x%08lx\r\n",
+ XPS_DEV_CFG_APB_BASEADDR + XDCFG_ROM_SHADOW_OFFSET,
+ Xil_In32(XPS_DEV_CFG_APB_BASEADDR + XDCFG_ROM_SHADOW_OFFSET));
+ fsbl_printf(DEBUG_INFO,"PCAP MBOOT 0x%x: 0x%08lx\r\n",
+ XPS_DEV_CFG_APB_BASEADDR + XDCFG_MULTIBOOT_ADDR_OFFSET,
+ Xil_In32(XPS_DEV_CFG_APB_BASEADDR + XDCFG_MULTIBOOT_ADDR_OFFSET));
+ fsbl_printf(DEBUG_INFO,"PCAP SW ID 0x%x: 0x%08lx\r\n",
+ XPS_DEV_CFG_APB_BASEADDR + XDCFG_SW_ID_OFFSET,
+ Xil_In32(XPS_DEV_CFG_APB_BASEADDR + XDCFG_SW_ID_OFFSET));
+ fsbl_printf(DEBUG_INFO,"PCAP UNLOCK 0x%x: 0x%08lx\r\n",
+ XPS_DEV_CFG_APB_BASEADDR + XDCFG_UNLOCK_OFFSET,
+ Xil_In32(XPS_DEV_CFG_APB_BASEADDR + XDCFG_UNLOCK_OFFSET));
+ fsbl_printf(DEBUG_INFO,"PCAP MCTRL 0x%x: 0x%08lx\r\n",
+ XPS_DEV_CFG_APB_BASEADDR + XDCFG_MCTRL_OFFSET,
+ Xil_In32(XPS_DEV_CFG_APB_BASEADDR + XDCFG_MCTRL_OFFSET));
+}
+
+/******************************************************************************/
+/**
+*
+* This function Polls for the DMA done or FPGA done.
+*
+* @param none
+*
+* @return
+* - XST_SUCCESS if polling for DMA/FPGA done is successful
+* - XST_FAILURE if polling for DMA/FPGA done fails
+*
+* @note none
+*
+****************************************************************************/
+int XDcfgPollDone(u32 MaskValue, u32 MaxCount)
+{
+ int Count = MaxCount;
+ u32 IntrStsReg = 0;
+
+ /*
+ * poll for the DMA done
+ */
+ IntrStsReg = XDcfg_IntrGetStatus(DcfgInstPtr);
+ while ((IntrStsReg & MaskValue) !=
+ MaskValue) {
+ IntrStsReg = XDcfg_IntrGetStatus(DcfgInstPtr);
+ Count -=1;
+
+ if (IntrStsReg & FSBL_XDCFG_IXR_ERROR_FLAGS_MASK) {
+ fsbl_printf(DEBUG_INFO,"FATAL errors in PCAP %lx\r\n",
+ IntrStsReg);
+ PcapDumpRegisters();
+ return XST_FAILURE;
+ }
+
+ if(!Count) {
+ fsbl_printf(DEBUG_GENERAL,"PCAP transfer timed out \r\n");
+ return XST_FAILURE;
+ }
+ if (Count > (MAX_COUNT-100)) {
+ fsbl_printf(DEBUG_GENERAL,".");
+ }
+ }
+
+ fsbl_printf(DEBUG_GENERAL,"\n\r");
+
+ XDcfg_IntrClear(DcfgInstPtr, IntrStsReg & MaskValue);
+
+ return XST_SUCCESS;
+}
diff --git a/hello_world/sw/fsbl/pcap.h b/hello_world/sw/fsbl/pcap.h
new file mode 100644
index 0000000..c286267
--- /dev/null
+++ b/hello_world/sw/fsbl/pcap.h
@@ -0,0 +1,102 @@
+/******************************************************************************
+*
+* Copyright (C) 2012 - 2014 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+* THE SOFTWARE.
+*
+*
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file pcap.h
+*
+* This file contains the interface for intiializing and accessing the PCAP
+*
+*
+* <pre>
+* MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ----- ---- -------- -------------------------------------------------------
+* 1.00a ecm 02/10/10 Initial release
+* 2.00a mb 16/08/12 Added the macros and function prototypes
+* 15.00a gan 07/21/16 953654 -(2016.3)FSBL -In pcap.c/pcap.h/main.c,
+* Fabric Initialization sequence is modified to check
+* the PL power before sequence starts and checking INIT_B
+* reset status twice in case of failure.
+* </pre>
+*
+* @note
+*
+******************************************************************************/
+#ifndef ___PCAP_H___
+#define ___PCAP_H___
+
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/***************************** Include Files *********************************/
+#include "xdevcfg.h"
+
+/************************** Function Prototypes ******************************/
+
+
+/* Multiboot register offset mask */
+#define PCAP_MBOOT_REG_REBOOT_OFFSET_MASK 0x1FFF
+#define PCAP_CTRL_PCFG_AES_FUSE_EFUSE_MASK 0x1000
+/*Miscellaneous Control Register mask*/
+#define XDCFG_MCTRL_PCAP_PCFG_POR_B_MASK 0x00000100
+#define COUNTS_PER_MILLI_SECOND (COUNTS_PER_SECOND/1000)
+
+#define PCAP_LAST_TRANSFER 1
+#define MAX_COUNT 1000000000
+#define LVL_PL_PS 0x0000000F
+#define LVL_PS_PL 0x0000000A
+
+/* Fix for #672779 */
+#define FSBL_XDCFG_IXR_ERROR_FLAGS_MASK (XDCFG_IXR_AXI_WERR_MASK | \
+ XDCFG_IXR_AXI_RTO_MASK | \
+ XDCFG_IXR_AXI_RERR_MASK | \
+ XDCFG_IXR_RX_FIFO_OV_MASK | \
+ XDCFG_IXR_DMA_CMD_ERR_MASK |\
+ XDCFG_IXR_DMA_Q_OV_MASK | \
+ XDCFG_IXR_P2D_LEN_ERR_MASK |\
+ XDCFG_IXR_PCFG_HMAC_ERR_MASK)
+
+int InitPcap(void);
+void PcapDumpRegisters(void);
+u32 ClearPcapStatus(void);
+u32 FabricInit(void);
+int XDcfgPollDone(u32 MaskValue, u32 MaxCount);
+u32 PcapLoadPartition(u32 *SourceData, u32 *DestinationData, u32 SourceLength,
+ u32 DestinationLength, u32 Flags);
+u32 PcapDataTransfer(u32 *SourceData, u32 *DestinationData, u32 SourceLength,
+ u32 DestinationLength, u32 Flags);
+/************************** Variable Definitions *****************************/
+#ifdef __cplusplus
+}
+#endif
+
+
+#endif /* ___PCAP_H___ */
+
diff --git a/hello_world/sw/fsbl/qspi.c b/hello_world/sw/fsbl/qspi.c
new file mode 100644
index 0000000..97c49f3
--- /dev/null
+++ b/hello_world/sw/fsbl/qspi.c
@@ -0,0 +1,875 @@
+/******************************************************************************
+*
+* Copyright (C) 2012 - 2016 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+* THE SOFTWARE.
+*
+*
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file qspi.c
+*
+* Contains code for the QSPI FLASH functionality.
+*
+* <pre>
+* MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ----- ---- -------- -------------------------------------------------------
+* 1.00a ecm 01/10/10 Initial release
+* 3.00a mb 25/06/12 InitQspi, data is read first and required config bits
+* are set
+* 4.00a sg 02/28/13 Cleanup
+* Removed LPBK_DLY_ADJ register setting code as we use
+* divisor 8
+* 5.00a sgd 05/17/13 Added Flash Size > 128Mbit support
+* Dual Stack support
+* Fix for CR:721674 - FSBL- Failed to boot from Dual
+* stacked QSPI
+* 6.00a kc 08/30/13 Fix for CR#722979 - Provide customer-friendly
+* changelogs in FSBL
+* Fix for CR#739711 - FSBL not able to read Large QSPI
+* (512M) in IO Mode
+* 7.00a kc 10/25/13 Fix for CR#739968 - FSBL should do the QSPI config
+* settings for Dual parallel
+* configuration in IO mode
+* 14.0 gan 01/13/16 Fix for CR#869081 - (2016.1)FSBL picks the qspi read
+* command from LQSPI_CFG register
+* instead of hard coded read
+* command (0x6B).
+*
+* </pre>
+*
+* @note
+*
+******************************************************************************/
+
+/***************************** Include Files *********************************/
+
+#include "qspi.h"
+#include "image_mover.h"
+
+#ifdef XPAR_PS7_QSPI_LINEAR_0_S_AXI_BASEADDR
+#include "xqspips_hw.h"
+#include "xqspips.h"
+
+/************************** Constant Definitions *****************************/
+
+/*
+ * The following constants map to the XPAR parameters created in the
+ * xparameters.h file. They are defined here such that a user can easily
+ * change all the needed parameters in one place.
+ */
+#define QSPI_DEVICE_ID XPAR_XQSPIPS_0_DEVICE_ID
+
+/*
+ * The following constants define the commands which may be sent to the FLASH
+ * device.
+ */
+#define QUAD_READ_CMD 0x6B
+#define READ_ID_CMD 0x9F
+
+#define WRITE_ENABLE_CMD 0x06
+#define BANK_REG_RD 0x16
+#define BANK_REG_WR 0x17
+/* Bank register is called Extended Address Reg in Micron */
+#define EXTADD_REG_RD 0xC8
+#define EXTADD_REG_WR 0xC5
+
+#define COMMAND_OFFSET 0 /* FLASH instruction */
+#define ADDRESS_1_OFFSET 1 /* MSB byte of address to read or write */
+#define ADDRESS_2_OFFSET 2 /* Middle byte of address to read or write */
+#define ADDRESS_3_OFFSET 3 /* LSB byte of address to read or write */
+#define DATA_OFFSET 4 /* Start of Data for Read/Write */
+#define DUMMY_OFFSET 4 /* Dummy byte offset for fast, dual and quad
+ reads */
+#define DUMMY_SIZE 1 /* Number of dummy bytes for fast, dual and
+ quad reads */
+#define RD_ID_SIZE 4 /* Read ID command + 3 bytes ID response */
+#define BANK_SEL_SIZE 2 /* BRWR or EARWR command + 1 byte bank value */
+#define WRITE_ENABLE_CMD_SIZE 1 /* WE command */
+/*
+ * The following constants specify the extra bytes which are sent to the
+ * FLASH on the QSPI interface, that are not data, but control information
+ * which includes the command and address
+ */
+#define OVERHEAD_SIZE 4
+
+/*
+ * The following constants specify the max amount of data and the size of the
+ * the buffer required to hold the data and overhead to transfer the data to
+ * and from the FLASH.
+ */
+#define DATA_SIZE 4096
+
+/*
+ * The following defines are for dual flash interface.
+ */
+#define LQSPI_CR_FAST_READ 0x0000000B
+#define LQSPI_CR_FAST_DUAL_READ 0x0000003B
+#define LQSPI_CR_FAST_QUAD_READ 0x0000006B /* Fast Quad Read output */
+#define LQSPI_CR_1_DUMMY_BYTE 0x00000100 /* 1 Dummy Byte between
+ address and return data */
+
+#define SINGLE_QSPI_CONFIG_FAST_READ (XQSPIPS_LQSPI_CR_LINEAR_MASK | \
+ LQSPI_CR_1_DUMMY_BYTE | \
+ LQSPI_CR_FAST_READ)
+
+#define SINGLE_QSPI_CONFIG_FAST_DUAL_READ (XQSPIPS_LQSPI_CR_LINEAR_MASK | \
+ LQSPI_CR_1_DUMMY_BYTE | \
+ LQSPI_CR_FAST_DUAL_READ)
+
+#define SINGLE_QSPI_CONFIG_FAST_QUAD_READ (XQSPIPS_LQSPI_CR_LINEAR_MASK | \
+ LQSPI_CR_1_DUMMY_BYTE | \
+ LQSPI_CR_FAST_QUAD_READ)
+
+#define DUAL_QSPI_CONFIG_FAST_QUAD_READ (XQSPIPS_LQSPI_CR_LINEAR_MASK | \
+ XQSPIPS_LQSPI_CR_TWO_MEM_MASK | \
+ XQSPIPS_LQSPI_CR_SEP_BUS_MASK | \
+ LQSPI_CR_1_DUMMY_BYTE | \
+ LQSPI_CR_FAST_QUAD_READ)
+
+#define DUAL_STACK_CONFIG_FAST_READ (XQSPIPS_LQSPI_CR_TWO_MEM_MASK | \
+ LQSPI_CR_1_DUMMY_BYTE | \
+ LQSPI_CR_FAST_READ)
+
+#define DUAL_STACK_CONFIG_FAST_DUAL_READ (XQSPIPS_LQSPI_CR_TWO_MEM_MASK | \
+ LQSPI_CR_1_DUMMY_BYTE | \
+ LQSPI_CR_FAST_DUAL_READ)
+
+#define DUAL_STACK_CONFIG_FAST_QUAD_READ (XQSPIPS_LQSPI_CR_TWO_MEM_MASK | \
+ LQSPI_CR_1_DUMMY_BYTE | \
+ LQSPI_CR_FAST_QUAD_READ)
+
+#define SINGLE_QSPI_IO_CONFIG_FAST_READ (LQSPI_CR_1_DUMMY_BYTE | \
+ LQSPI_CR_FAST_READ)
+
+#define SINGLE_QSPI_IO_CONFIG_FAST_DUAL_READ (LQSPI_CR_1_DUMMY_BYTE | \
+ LQSPI_CR_FAST_DUAL_READ)
+
+#define SINGLE_QSPI_IO_CONFIG_FAST_QUAD_READ (LQSPI_CR_1_DUMMY_BYTE | \
+ LQSPI_CR_FAST_QUAD_READ)
+
+#define DUAL_QSPI_IO_CONFIG_FAST_QUAD_READ (XQSPIPS_LQSPI_CR_TWO_MEM_MASK | \
+ XQSPIPS_LQSPI_CR_SEP_BUS_MASK | \
+ LQSPI_CR_1_DUMMY_BYTE | \
+ LQSPI_CR_FAST_QUAD_READ)
+
+#define QSPI_BUSWIDTH_ONE 0U
+#define QSPI_BUSWIDTH_TWO 1U
+#define QSPI_BUSWIDTH_FOUR 2U
+
+/**************************** Type Definitions *******************************/
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/************************** Function Prototypes ******************************/
+
+/************************** Variable Definitions *****************************/
+
+XQspiPs QspiInstance;
+XQspiPs *QspiInstancePtr;
+u32 QspiFlashSize;
+u32 QspiFlashMake;
+extern u32 FlashReadBaseAddress;
+extern u8 LinearBootDeviceFlag;
+
+/*
+ * The following variables are used to read and write to the eeprom and they
+ * are global to avoid having large buffers on the stack
+ */
+u8 ReadBuffer[DATA_SIZE + DATA_OFFSET + DUMMY_SIZE];
+u8 WriteBuffer[DATA_OFFSET + DUMMY_SIZE];
+
+/******************************************************************************/
+/**
+*
+* This function initializes the controller for the QSPI interface.
+*
+* @param None
+*
+* @return None
+*
+* @note None
+*
+****************************************************************************/
+u32 InitQspi(void)
+{
+ XQspiPs_Config *QspiConfig;
+ int Status;
+ u32 ConfigCmd;
+
+ QspiInstancePtr = &QspiInstance;
+
+ /*
+ * Set up the base address for access
+ */
+ FlashReadBaseAddress = XPS_QSPI_LINEAR_BASEADDR;
+
+ /*
+ * Initialize the QSPI driver so that it's ready to use
+ */
+ QspiConfig = XQspiPs_LookupConfig(QSPI_DEVICE_ID);
+ if (NULL == QspiConfig) {
+ return XST_FAILURE;
+ }
+
+ Status = XQspiPs_CfgInitialize(QspiInstancePtr, QspiConfig,
+ QspiConfig->BaseAddress);
+ if (Status != XST_SUCCESS) {
+ return XST_FAILURE;
+ }
+
+ /*
+ * Set Manual Chip select options and drive HOLD_B pin high.
+ */
+ XQspiPs_SetOptions(QspiInstancePtr, XQSPIPS_FORCE_SSELECT_OPTION |
+ XQSPIPS_HOLD_B_DRIVE_OPTION);
+
+ /*
+ * Set the prescaler for QSPI clock
+ */
+ XQspiPs_SetClkPrescaler(QspiInstancePtr, XQSPIPS_CLK_PRESCALE_8);
+
+ /*
+ * Assert the FLASH chip select.
+ */
+ XQspiPs_SetSlaveSelect(QspiInstancePtr);
+
+ /*
+ * Read Flash ID and extract Manufacture and Size information
+ */
+ Status = FlashReadID();
+ if (Status != XST_SUCCESS) {
+ return XST_FAILURE;
+ }
+
+ if (XPAR_XQSPIPS_0_QSPI_MODE == SINGLE_FLASH_CONNECTION) {
+
+ fsbl_printf(DEBUG_INFO,"QSPI is in single flash connection\r\n");
+ /*
+ * For Flash size <128Mbit controller configured in linear mode
+ */
+ if (QspiFlashSize <= FLASH_SIZE_16MB) {
+ LinearBootDeviceFlag = 1;
+
+ /*
+ * Enable linear mode
+ */
+ XQspiPs_SetOptions(QspiInstancePtr, XQSPIPS_LQSPI_MODE_OPTION |
+ XQSPIPS_HOLD_B_DRIVE_OPTION);
+
+ switch (XPAR_XQSPIPS_0_QSPI_BUS_WIDTH) {
+
+ case QSPI_BUSWIDTH_ONE:
+ {
+ fsbl_printf(DEBUG_INFO,"QSPI is in 1-bit mode\r\n");
+ ConfigCmd = SINGLE_QSPI_CONFIG_FAST_READ;
+ }
+ break;
+
+ case QSPI_BUSWIDTH_TWO:
+ {
+ fsbl_printf(DEBUG_INFO,"QSPI is in 2-bit mode\r\n");
+ ConfigCmd = SINGLE_QSPI_CONFIG_FAST_DUAL_READ;
+ }
+ break;
+
+ case QSPI_BUSWIDTH_FOUR:
+ {
+ fsbl_printf(DEBUG_INFO,"QSPI is in 4-bit mode\r\n");
+ ConfigCmd = SINGLE_QSPI_CONFIG_FAST_QUAD_READ;
+ }
+ break;
+
+ }
+
+ /*
+ * Single linear read
+ */
+ XQspiPs_SetLqspiConfigReg(QspiInstancePtr, ConfigCmd);
+
+ /*
+ * Enable the controller
+ */
+ XQspiPs_Enable(QspiInstancePtr);
+ } else {
+
+ switch (XPAR_XQSPIPS_0_QSPI_BUS_WIDTH) {
+
+ case QSPI_BUSWIDTH_ONE:
+ {
+ fsbl_printf(DEBUG_INFO,"QSPI is in 1-bit mode\r\n");
+ ConfigCmd = SINGLE_QSPI_IO_CONFIG_FAST_READ;
+ }
+ break;
+
+ case QSPI_BUSWIDTH_TWO:
+ {
+ fsbl_printf(DEBUG_INFO,"QSPI is in 2-bit mode\r\n");
+ ConfigCmd = SINGLE_QSPI_IO_CONFIG_FAST_DUAL_READ;
+ }
+ break;
+
+ case QSPI_BUSWIDTH_FOUR:
+ {
+ fsbl_printf(DEBUG_INFO,"QSPI is in 4-bit mode\r\n");
+ ConfigCmd = SINGLE_QSPI_IO_CONFIG_FAST_QUAD_READ;
+ }
+ break;
+
+ }
+ /*
+ * Single flash IO read
+ */
+ XQspiPs_SetLqspiConfigReg(QspiInstancePtr, ConfigCmd);
+
+ /*
+ * Enable the controller
+ */
+ XQspiPs_Enable(QspiInstancePtr);
+ }
+ }
+
+ if (XPAR_XQSPIPS_0_QSPI_MODE == DUAL_PARALLEL_CONNECTION) {
+
+ fsbl_printf(DEBUG_INFO,"QSPI is in Dual Parallel connection\r\n");
+ /*
+ * For Single Flash size <128Mbit controller configured in linear mode
+ */
+ if (QspiFlashSize <= FLASH_SIZE_16MB) {
+ /*
+ * Setting linear access flag
+ */
+ LinearBootDeviceFlag = 1;
+
+ /*
+ * Enable linear mode
+ */
+ XQspiPs_SetOptions(QspiInstancePtr, XQSPIPS_LQSPI_MODE_OPTION |
+ XQSPIPS_HOLD_B_DRIVE_OPTION);
+
+ /*
+ * Dual linear read
+ */
+ XQspiPs_SetLqspiConfigReg(QspiInstancePtr, DUAL_QSPI_CONFIG_FAST_QUAD_READ);
+
+ /*
+ * Enable the controller
+ */
+ XQspiPs_Enable(QspiInstancePtr);
+ } else {
+ /*
+ * Dual flash IO read
+ */
+ XQspiPs_SetLqspiConfigReg(QspiInstancePtr, DUAL_QSPI_IO_CONFIG_FAST_QUAD_READ);
+
+ /*
+ * Enable the controller
+ */
+ XQspiPs_Enable(QspiInstancePtr);
+
+ }
+
+ /*
+ * Total flash size is two time of single flash size
+ */
+ QspiFlashSize = 2 * QspiFlashSize;
+ }
+
+ /*
+ * It is expected to same flash size for both chip selection
+ */
+ if (XPAR_XQSPIPS_0_QSPI_MODE == DUAL_STACK_CONNECTION) {
+
+ fsbl_printf(DEBUG_INFO,"QSPI is in Dual Stack connection\r\n");
+
+ QspiFlashSize = 2 * QspiFlashSize;
+
+ /*
+ * Enable two flash memories on separate buses
+ */
+ switch (XPAR_XQSPIPS_0_QSPI_BUS_WIDTH) {
+
+ case QSPI_BUSWIDTH_ONE:
+ {
+ fsbl_printf(DEBUG_INFO,"QSPI is in 1-bit mode\r\n");
+ ConfigCmd = DUAL_STACK_CONFIG_FAST_READ;
+ }
+ break;
+
+ case QSPI_BUSWIDTH_TWO:
+ {
+ fsbl_printf(DEBUG_INFO,"QSPI is in 2-bit mode\r\n");
+ ConfigCmd = DUAL_STACK_CONFIG_FAST_DUAL_READ;
+ }
+ break;
+
+ case QSPI_BUSWIDTH_FOUR:
+ {
+ fsbl_printf(DEBUG_INFO,"QSPI is in 4-bit mode\r\n");
+ ConfigCmd = DUAL_STACK_CONFIG_FAST_QUAD_READ;
+ }
+ break;
+
+ }
+ XQspiPs_SetLqspiConfigReg(QspiInstancePtr, ConfigCmd);
+ }
+
+ return XST_SUCCESS;
+}
+
+/******************************************************************************
+*
+* This function reads serial FLASH ID connected to the SPI interface.
+* It then deduces the make and size of the flash and obtains the
+* connection mode to point to corresponding parameters in the flash
+* configuration table. The flash driver will function based on this and
+* it presently supports Micron and Spansion - 128, 256 and 512Mbit and
+* Winbond 128Mbit
+*
+* @param none
+*
+* @return XST_SUCCESS if read id, otherwise XST_FAILURE.
+*
+* @note None.
+*
+******************************************************************************/
+u32 FlashReadID(void)
+{
+ u32 Status;
+
+ /*
+ * Read ID in Auto mode.
+ */
+ WriteBuffer[COMMAND_OFFSET] = READ_ID_CMD;
+ WriteBuffer[ADDRESS_1_OFFSET] = 0x00; /* 3 dummy bytes */
+ WriteBuffer[ADDRESS_2_OFFSET] = 0x00;
+ WriteBuffer[ADDRESS_3_OFFSET] = 0x00;
+
+ Status = XQspiPs_PolledTransfer(QspiInstancePtr, WriteBuffer, ReadBuffer,
+ RD_ID_SIZE);
+ if (Status != XST_SUCCESS) {
+ return XST_FAILURE;
+ }
+
+ fsbl_printf(DEBUG_INFO,"Single Flash Information\r\n");
+
+ fsbl_printf(DEBUG_INFO,"FlashID=0x%x 0x%x 0x%x\r\n", ReadBuffer[1],
+ ReadBuffer[2],
+ ReadBuffer[3]);
+
+ /*
+ * Deduce flash make
+ */
+ if (ReadBuffer[1] == MICRON_ID) {
+ QspiFlashMake = MICRON_ID;
+ fsbl_printf(DEBUG_INFO, "MICRON ");
+ } else if(ReadBuffer[1] == SPANSION_ID) {
+ QspiFlashMake = SPANSION_ID;
+ fsbl_printf(DEBUG_INFO, "SPANSION ");
+ } else if(ReadBuffer[1] == WINBOND_ID) {
+ QspiFlashMake = WINBOND_ID;
+ fsbl_printf(DEBUG_INFO, "WINBOND ");
+ } else if(ReadBuffer[1] == MACRONIX_ID) {
+ QspiFlashMake = MACRONIX_ID;
+ fsbl_printf(DEBUG_INFO, "MACRONIX ");
+ } else if(ReadBuffer[0] == ISSI_ID) {
+ QspiFlashMake = ISSI_ID;
+ fsbl_printf(DEBUG_INFO, "ISSI ");
+ }
+
+ /*
+ * Deduce flash Size
+ */
+ if (ReadBuffer[2] == FLASH_SIZE_ID_8M) {
+ QspiFlashSize = FLASH_SIZE_8M;
+ fsbl_printf(DEBUG_INFO, "8M Bits\r\n");
+ } else if (ReadBuffer[2] == FLASH_SIZE_ID_16M) {
+ QspiFlashSize = FLASH_SIZE_16M;
+ fsbl_printf(DEBUG_INFO, "16M Bits\r\n");
+ } else if (ReadBuffer[2] == FLASH_SIZE_ID_32M) {
+ QspiFlashSize = FLASH_SIZE_32M;
+ fsbl_printf(DEBUG_INFO, "32M Bits\r\n");
+ } else if (ReadBuffer[2] == FLASH_SIZE_ID_64M) {
+ QspiFlashSize = FLASH_SIZE_64M;
+ fsbl_printf(DEBUG_INFO, "64M Bits\r\n");
+ } else if (ReadBuffer[3] == FLASH_SIZE_ID_128M) {
+ QspiFlashSize = FLASH_SIZE_128M;
+ fsbl_printf(DEBUG_INFO, "128M Bits\r\n");
+ } else if (ReadBuffer[3] == FLASH_SIZE_ID_256M) {
+ QspiFlashSize = FLASH_SIZE_256M;
+ fsbl_printf(DEBUG_INFO, "256M Bits\r\n");
+ } else if ((ReadBuffer[3] == FLASH_SIZE_ID_512M)
+ || (ReadBuffer[3] == MACRONIX_FLASH_SIZE_ID_512M)) {
+ QspiFlashSize = FLASH_SIZE_512M;
+ fsbl_printf(DEBUG_INFO, "512M Bits\r\n");
+ } else if ((ReadBuffer[3] == FLASH_SIZE_ID_1G)
+ || (ReadBuffer[3] == MACRONIX_FLASH_SIZE_ID_1G)) {
+ QspiFlashSize = FLASH_SIZE_1G;
+ fsbl_printf(DEBUG_INFO, "1G Bits\r\n");
+ }
+
+ return XST_SUCCESS;
+}
+
+
+/******************************************************************************
+*
+* This function reads from the serial FLASH connected to the
+* QSPI interface.
+*
+* @param Address contains the address to read data from in the FLASH.
+* @param ByteCount contains the number of bytes to read.
+*
+* @return None.
+*
+* @note None.
+*
+******************************************************************************/
+void FlashRead(u32 Address, u32 ByteCount)
+{
+ /*
+ * Setup the write command with the specified address and data for the
+ * FLASH
+ */
+ u32 LqspiCrReg;
+ u8 ReadCommand;
+
+ LqspiCrReg = XQspiPs_GetLqspiConfigReg(QspiInstancePtr);
+ ReadCommand = (u8) (LqspiCrReg & XQSPIPS_LQSPI_CR_INST_MASK);
+ WriteBuffer[COMMAND_OFFSET] = ReadCommand;
+ WriteBuffer[ADDRESS_1_OFFSET] = (u8)((Address & 0xFF0000) >> 16);
+ WriteBuffer[ADDRESS_2_OFFSET] = (u8)((Address & 0xFF00) >> 8);
+ WriteBuffer[ADDRESS_3_OFFSET] = (u8)(Address & 0xFF);
+
+ ByteCount += DUMMY_SIZE;
+
+ /*
+ * Send the read command to the FLASH to read the specified number
+ * of bytes from the FLASH, send the read command and address and
+ * receive the specified number of bytes of data in the data buffer
+ */
+ XQspiPs_PolledTransfer(QspiInstancePtr, WriteBuffer, ReadBuffer,
+ ByteCount + OVERHEAD_SIZE);
+}
+
+/******************************************************************************/
+/**
+*
+* This function provides the QSPI FLASH interface for the Simplified header
+* functionality.
+*
+* @param SourceAddress is address in FLASH data space
+* @param DestinationAddress is address in DDR data space
+* @param LengthBytes is the length of the data in Bytes
+*
+* @return
+* - XST_SUCCESS if the write completes correctly
+* - XST_FAILURE if the write fails to completes correctly
+*
+* @note none.
+*
+****************************************************************************/
+u32 QspiAccess( u32 SourceAddress, u32 DestinationAddress, u32 LengthBytes)
+{
+ u8 *BufferPtr;
+ u32 Length = 0;
+ u32 BankSel = 0;
+ u32 LqspiCrReg;
+ u32 Status;
+ u8 BankSwitchFlag = 1;
+
+ /*
+ * Linear access check
+ */
+ if (LinearBootDeviceFlag == 1) {
+ /*
+ * Check for non-word tail, add bytes to cover the end
+ */
+ if ((LengthBytes%4) != 0){
+ LengthBytes += (4 - (LengthBytes & 0x00000003));
+ }
+
+ memcpy((void*)DestinationAddress,
+ (const void*)(SourceAddress + FlashReadBaseAddress),
+ (size_t)LengthBytes);
+ } else {
+ /*
+ * Non Linear access
+ */
+ BufferPtr = (u8*)DestinationAddress;
+
+ /*
+ * Dual parallel connection actual flash is half
+ */
+ if (XPAR_XQSPIPS_0_QSPI_MODE == DUAL_PARALLEL_CONNECTION) {
+ SourceAddress = SourceAddress/2;
+ }
+
+ while(LengthBytes > 0) {
+ /*
+ * Local of DATA_SIZE size used for read/write buffer
+ */
+ if(LengthBytes > DATA_SIZE) {
+ Length = DATA_SIZE;
+ } else {
+ Length = LengthBytes;
+ }
+
+ /*
+ * Dual stack connection
+ */
+ if (XPAR_XQSPIPS_0_QSPI_MODE == DUAL_STACK_CONNECTION) {
+ /*
+ * Get the current LQSPI configuration value
+ */
+ LqspiCrReg = XQspiPs_GetLqspiConfigReg(QspiInstancePtr);
+
+ /*
+ * Select lower or upper Flash based on sector address
+ */
+ if (SourceAddress >= (QspiFlashSize/2)) {
+ /*
+ * Set selection to U_PAGE
+ */
+ XQspiPs_SetLqspiConfigReg(QspiInstancePtr,
+ LqspiCrReg | XQSPIPS_LQSPI_CR_U_PAGE_MASK);
+
+ /*
+ * Subtract first flash size when accessing second flash
+ */
+ SourceAddress = SourceAddress - (QspiFlashSize/2);
+
+ fsbl_printf(DEBUG_INFO, "stacked - upper CS \n\r");
+
+ /*
+ * Assert the FLASH chip select.
+ */
+ XQspiPs_SetSlaveSelect(QspiInstancePtr);
+ }
+ }
+
+ /*
+ * Select bank
+ */
+ if ((SourceAddress >= FLASH_SIZE_16MB) && (BankSwitchFlag == 1)) {
+ BankSel = SourceAddress/FLASH_SIZE_16MB;
+
+ fsbl_printf(DEBUG_INFO, "Bank Selection %lu\n\r", BankSel);
+
+ Status = SendBankSelect(BankSel);
+ if (Status != XST_SUCCESS) {
+ fsbl_printf(DEBUG_INFO, "Bank Selection Failed\n\r");
+ return XST_FAILURE;
+ }
+
+ BankSwitchFlag = 0;
+ }
+
+ /*
+ * If data to be read spans beyond the current bank, then
+ * calculate length in current bank else no change in length
+ */
+ if (XPAR_XQSPIPS_0_QSPI_MODE == DUAL_PARALLEL_CONNECTION) {
+ /*
+ * In dual parallel mode, check should be for half
+ * the length.
+ */
+ if((SourceAddress & BANKMASK) != ((SourceAddress + (Length/2)) & BANKMASK))
+ {
+ Length = (SourceAddress & BANKMASK) + FLASH_SIZE_16MB - SourceAddress;
+ /*
+ * Above length calculated is for single flash
+ * Length should be doubled since dual parallel
+ */
+ Length = Length * 2;
+ BankSwitchFlag = 1;
+ }
+ } else {
+ if((SourceAddress & BANKMASK) != ((SourceAddress + Length) & BANKMASK))
+ {
+ Length = (SourceAddress & BANKMASK) + FLASH_SIZE_16MB - SourceAddress;
+ BankSwitchFlag = 1;
+ }
+ }
+
+ /*
+ * Copying the image to local buffer
+ */
+ FlashRead(SourceAddress, Length);
+
+ /*
+ * Moving the data from local buffer to DDR destination address
+ */
+ memcpy(BufferPtr, &ReadBuffer[DATA_OFFSET + DUMMY_SIZE], Length);
+
+ /*
+ * Updated the variables
+ */
+ LengthBytes -= Length;
+
+ /*
+ * For Dual parallel connection address increment should be half
+ */
+ if (XPAR_XQSPIPS_0_QSPI_MODE == DUAL_PARALLEL_CONNECTION) {
+ SourceAddress += Length/2;
+ } else {
+ SourceAddress += Length;
+ }
+
+ BufferPtr = (u8*)((u32)BufferPtr + Length);
+ }
+
+ /*
+ * Reset Bank selection to zero
+ */
+ Status = SendBankSelect(0);
+ if (Status != XST_SUCCESS) {
+ fsbl_printf(DEBUG_INFO, "Bank Selection Reset Failed\n\r");
+ return XST_FAILURE;
+ }
+
+ if (XPAR_XQSPIPS_0_QSPI_MODE == DUAL_STACK_CONNECTION) {
+
+ /*
+ * Reset selection to L_PAGE
+ */
+ XQspiPs_SetLqspiConfigReg(QspiInstancePtr,
+ LqspiCrReg & (~XQSPIPS_LQSPI_CR_U_PAGE_MASK));
+
+ fsbl_printf(DEBUG_INFO, "stacked - lower CS \n\r");
+
+ /*
+ * Assert the FLASH chip select.
+ */
+ XQspiPs_SetSlaveSelect(QspiInstancePtr);
+ }
+ }
+
+ return XST_SUCCESS;
+}
+
+
+
+/******************************************************************************
+*
+* This functions selects the current bank
+*
+* @param BankSel is the bank to be selected in the flash device(s).
+*
+* @return XST_SUCCESS if bank selected
+* XST_FAILURE if selection failed
+* @note None.
+*
+******************************************************************************/
+u32 SendBankSelect(u8 BankSel)
+{
+ u32 Status;
+
+ /*
+ * bank select commands for Micron and Spansion are different
+ * Macronix bank select is same as Micron
+ */
+ if (QspiFlashMake == MICRON_ID || QspiFlashMake == MACRONIX_ID) {
+ /*
+ * For micron command WREN should be sent first
+ * except for some specific feature set
+ */
+ WriteBuffer[COMMAND_OFFSET] = WRITE_ENABLE_CMD;
+ Status = XQspiPs_PolledTransfer(QspiInstancePtr, WriteBuffer, NULL,
+ WRITE_ENABLE_CMD_SIZE);
+ if (Status != XST_SUCCESS) {
+ return XST_FAILURE;
+ }
+
+ /*
+ * Send the Extended address register write command
+ * written, no receive buffer required
+ */
+ WriteBuffer[COMMAND_OFFSET] = EXTADD_REG_WR;
+ WriteBuffer[ADDRESS_1_OFFSET] = BankSel;
+ Status = XQspiPs_PolledTransfer(QspiInstancePtr, WriteBuffer, NULL,
+ BANK_SEL_SIZE);
+ if (Status != XST_SUCCESS) {
+ return XST_FAILURE;
+ }
+ }
+
+ if (QspiFlashMake == SPANSION_ID) {
+ WriteBuffer[COMMAND_OFFSET] = BANK_REG_WR;
+ WriteBuffer[ADDRESS_1_OFFSET] = BankSel;
+
+ /*
+ * Send the Extended address register write command
+ * written, no receive buffer required
+ */
+ Status = XQspiPs_PolledTransfer(QspiInstancePtr, WriteBuffer, NULL,
+ BANK_SEL_SIZE);
+ if (Status != XST_SUCCESS) {
+ return XST_FAILURE;
+ }
+ }
+
+ /*
+ * For testing - Read bank to verify
+ */
+ if (QspiFlashMake == SPANSION_ID) {
+ WriteBuffer[COMMAND_OFFSET] = BANK_REG_RD;
+ WriteBuffer[ADDRESS_1_OFFSET] = 0x00;
+
+ /*
+ * Send the Extended address register write command
+ * written, no receive buffer required
+ */
+ Status = XQspiPs_PolledTransfer(QspiInstancePtr, WriteBuffer, ReadBuffer,
+ BANK_SEL_SIZE);
+ if (Status != XST_SUCCESS) {
+ return XST_FAILURE;
+ }
+ }
+
+ if (QspiFlashMake == MICRON_ID || QspiFlashMake == MACRONIX_ID) {
+ WriteBuffer[COMMAND_OFFSET] = EXTADD_REG_RD;
+ WriteBuffer[ADDRESS_1_OFFSET] = 0x00;
+
+ /*
+ * Send the Extended address register write command
+ * written, no receive buffer required
+ */
+ Status = XQspiPs_PolledTransfer(QspiInstancePtr, WriteBuffer, ReadBuffer,
+ BANK_SEL_SIZE);
+ if (Status != XST_SUCCESS) {
+ return XST_FAILURE;
+ }
+ }
+
+ if (ReadBuffer[1] != BankSel) {
+ fsbl_printf(DEBUG_INFO, "BankSel %d != Register Read %d\n\r", BankSel,
+ ReadBuffer[1]);
+ return XST_FAILURE;
+ }
+
+ return XST_SUCCESS;
+}
+#endif
+
diff --git a/hello_world/sw/fsbl/qspi.h b/hello_world/sw/fsbl/qspi.h
new file mode 100644
index 0000000..a4a4190
--- /dev/null
+++ b/hello_world/sw/fsbl/qspi.h
@@ -0,0 +1,131 @@
+/******************************************************************************
+*
+* Copyright (C) 2012 - 2014 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+* THE SOFTWARE.
+*
+*
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file qspi.h
+*
+* This file contains the interface for the QSPI FLASH functionality
+*
+* <pre>
+* MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ----- ---- -------- -------------------------------------------------------
+* 1.00a ecm 01/10/10 Initial release
+* 3.00a mb 01/09/12 Added the Delay Values defines for qspi
+* 5.00a sgd 05/17/13 Added Flash Size > 128Mbit support
+* Dual Stack support
+* </pre>
+*
+* @note
+*
+******************************************************************************/
+#ifndef ___QSPI_H___
+#define ___QSPI_H___
+
+#include "fsbl.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/***************************** Include Files *********************************/
+#include "fsbl.h"
+
+/************************** Constant Definitions *****************************/
+#define SINGLE_FLASH_CONNECTION 0
+#define DUAL_STACK_CONNECTION 1
+#define DUAL_PARALLEL_CONNECTION 2
+#define FLASH_SIZE_16MB 0x1000000
+
+/*
+ * Bank mask
+ */
+#define BANKMASK 0xF000000
+
+/*
+ * Identification of Flash
+ * Micron:
+ * Byte 0 is Manufacturer ID;
+ * Byte 1 is first byte of Device ID - 0xBB or 0xBA
+ * Byte 2 is second byte of Device ID describes flash size:
+ * 128Mbit : 0x18; 256Mbit : 0x19; 512Mbit : 0x20
+ * Spansion:
+ * Byte 0 is Manufacturer ID;
+ * Byte 1 is Device ID - Memory Interface type - 0x20 or 0x02
+ * Byte 2 is second byte of Device ID describes flash size:
+ * 128Mbit : 0x18; 256Mbit : 0x19; 512Mbit : 0x20
+ */
+
+#define MICRON_ID 0x20
+#define SPANSION_ID 0x01
+#define WINBOND_ID 0xEF
+#define MACRONIX_ID 0xC2
+#define ISSI_ID 0x9D
+
+#define FLASH_SIZE_ID_8M 0x14
+#define FLASH_SIZE_ID_16M 0x15
+#define FLASH_SIZE_ID_32M 0x16
+#define FLASH_SIZE_ID_64M 0x17
+#define FLASH_SIZE_ID_128M 0x18
+#define FLASH_SIZE_ID_256M 0x19
+#define FLASH_SIZE_ID_512M 0x20
+#define FLASH_SIZE_ID_1G 0x21
+/* Macronix size constants are different for 512M and 1G */
+#define MACRONIX_FLASH_SIZE_ID_512M 0x1A
+#define MACRONIX_FLASH_SIZE_ID_1G 0x1B
+
+/*
+ * Size in bytes
+ */
+#define FLASH_SIZE_8M 0x0100000
+#define FLASH_SIZE_16M 0x0200000
+#define FLASH_SIZE_32M 0x0400000
+#define FLASH_SIZE_64M 0x0800000
+#define FLASH_SIZE_128M 0x1000000
+#define FLASH_SIZE_256M 0x2000000
+#define FLASH_SIZE_512M 0x4000000
+#define FLASH_SIZE_1G 0x8000000
+
+/************************** Function Prototypes ******************************/
+u32 InitQspi(void);
+
+u32 QspiAccess( u32 SourceAddress,
+ u32 DestinationAddress,
+ u32 LengthBytes);
+
+u32 FlashReadID(void);
+u32 SendBankSelect(u8 BankSel);
+/************************** Variable Definitions *****************************/
+
+
+#ifdef __cplusplus
+}
+#endif
+
+
+#endif /* ___QSPI_H___ */
+
diff --git a/hello_world/sw/fsbl/rsa.c b/hello_world/sw/fsbl/rsa.c
new file mode 100644
index 0000000..4e1007f
--- /dev/null
+++ b/hello_world/sw/fsbl/rsa.c
@@ -0,0 +1,355 @@
+/******************************************************************************
+*
+* Copyright (C) 2012 - 2014 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+* THE SOFTWARE.
+*
+*
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file rsa.c
+*
+* Contains code for the RSA authentication
+*
+* <pre>
+* MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ----- ---- -------- -------------------------------------------------------
+* 4.00a sgd 02/28/13 Initial release
+* 6.00a kc 07/30/13 Added FSBL_DEBUG_RSA to print more RSA buffers
+* Fix for CR#724165 - Partition Header used by FSBL is
+* not authenticated
+* Fix for CR#724166 - FSBL doesn’t use PPK authenticated
+* by Boot ROM for authenticating
+* the Partition images
+* Fix for CR#722979 - Provide customer-friendly
+* changelogs in FSBL
+* 9.00a kc 04/16/14 Fix for CR#724166 - SetPpk() will fail on secure
+* fallback unless FSBL* and FSBL are
+* identical in length
+* Fix for CR#791245 - Use of xilrsa in FSBL
+* </pre>
+*
+* @note
+*
+******************************************************************************/
+
+/***************************** Include Files *********************************/
+#ifdef RSA_SUPPORT
+#include "fsbl.h"
+#include "rsa.h"
+#include "xilrsa.h"
+
+#ifdef XPAR_XWDTPS_0_BASEADDR
+#include "xwdtps.h"
+#endif
+
+/************************** Constant Definitions *****************************/
+
+/**************************** Type Definitions *******************************/
+
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+
+/************************** Function Prototypes ******************************/
+#ifdef XPAR_XWDTPS_0_BASEADDR
+extern XWdtPs Watchdog; /* Instance of WatchDog Timer */
+#endif
+
+
+/************************** Variable Definitions *****************************/
+
+static u8 *PpkModular;
+static u8 *PpkModularEx;
+static u32 PpkExp;
+static u32 PpkAlreadySet=0;
+
+extern u32 FsblLength;
+
+void FsblPrintArray (u8 *Buf, u32 Len, char *Str)
+{
+#ifdef FSBL_DEBUG_RSA
+ int Index;
+ fsbl_printf(DEBUG_INFO, "%s START\r\n", Str);
+ for (Index=0;Index<Len;Index++)
+ {
+ fsbl_printf(DEBUG_INFO, "%02x",Buf[Index]);
+ if ((Index+1)%16 == 0){
+ fsbl_printf(DEBUG_INFO, "\r\n");
+ }
+ }
+ fsbl_printf(DEBUG_INFO, "\r\n %s END\r\n",Str);
+#endif
+ return;
+}
+
+
+/*****************************************************************************/
+/**
+*
+* This function is used to set ppk pointer to ppk in OCM
+*
+* @param None
+*
+* @return
+*
+* @note None
+*
+******************************************************************************/
+
+void SetPpk(void )
+{
+ u32 PadSize;
+ u8 *PpkPtr;
+
+ /*
+ * Set PPK only if is not already set
+ */
+ if(PpkAlreadySet == 0)
+ {
+
+ /*
+ * Set PpkPtr to PPK in OCM
+ */
+
+ /*
+ * Skip FSBL Length
+ */
+ PpkPtr = (u8 *)(FsblLength);
+ /*
+ * Skip to 64 byte Boundary
+ */
+ PadSize = ((u32)PpkPtr % 64);
+ if(PadSize != 0)
+ {
+ PpkPtr += (64 - PadSize);
+ }
+
+ /*
+ * Increment the pointer by authentication Header size
+ */
+ PpkPtr += RSA_HEADER_SIZE;
+
+ /*
+ * Increment the pointer by Magic word size
+ */
+ PpkPtr += RSA_MAGIC_WORD_SIZE;
+
+ /*
+ * Set pointer to PPK
+ */
+ PpkModular = (u8 *)PpkPtr;
+ PpkPtr += RSA_PPK_MODULAR_SIZE;
+ PpkModularEx = (u8 *)PpkPtr;
+ PpkPtr += RSA_PPK_MODULAR_EXT_SIZE;
+ PpkExp = *((u32 *)PpkPtr);
+
+ /*
+ * Setting variable to avoid resetting PPK pointers
+ */
+ PpkAlreadySet=1;
+ }
+
+ return;
+}
+
+
+/*****************************************************************************/
+/**
+*
+* This function Authenticate Partition Signature
+*
+* @param Partition header pointer
+*
+* @return
+* - XST_SUCCESS if Authentication passed
+* - XST_FAILURE if Authentication failed
+*
+* @note None
+*
+******************************************************************************/
+u32 AuthenticatePartition(u8 *Buffer, u32 Size)
+{
+ u8 DecryptSignature[256];
+ u8 HashSignature[32];
+ u8 *SpkModular;
+ u8 *SpkModularEx;
+ u32 SpkExp;
+ u8 *SignaturePtr;
+ u32 Status;
+
+#ifdef XPAR_XWDTPS_0_BASEADDR
+ /*
+ * Prevent WDT reset
+ */
+ XWdtPs_RestartWdt(&Watchdog);
+#endif
+
+ /*
+ * Point to Authentication Certificate
+ */
+ SignaturePtr = (u8 *)(Buffer + Size - RSA_SIGNATURE_SIZE);
+
+ /*
+ * Increment the pointer by authentication Header size
+ */
+ SignaturePtr += RSA_HEADER_SIZE;
+
+ /*
+ * Increment the pointer by Magic word size
+ */
+ SignaturePtr += RSA_MAGIC_WORD_SIZE;
+
+ /*
+ * Increment the pointer beyond the PPK
+ */
+ SignaturePtr += RSA_PPK_MODULAR_SIZE;
+ SignaturePtr += RSA_PPK_MODULAR_EXT_SIZE;
+ SignaturePtr += RSA_PPK_EXPO_SIZE;
+
+ /*
+ * Calculate Hash Signature
+ */
+ sha_256((u8 *)SignaturePtr, (RSA_SPK_MODULAR_EXT_SIZE +
+ RSA_SPK_EXPO_SIZE + RSA_SPK_MODULAR_SIZE),
+ HashSignature);
+ FsblPrintArray(HashSignature, 32, "SPK Hash Calculated");
+
+ /*
+ * Extract SPK signature
+ */
+ SpkModular = (u8 *)SignaturePtr;
+ SignaturePtr += RSA_SPK_MODULAR_SIZE;
+ SpkModularEx = (u8 *)SignaturePtr;
+ SignaturePtr += RSA_SPK_MODULAR_EXT_SIZE;
+ SpkExp = *((u32 *)SignaturePtr);
+ SignaturePtr += RSA_SPK_EXPO_SIZE;
+
+ /*
+ * Decrypt SPK Signature
+ */
+ rsa2048_pubexp((RSA_NUMBER)DecryptSignature,
+ (RSA_NUMBER)SignaturePtr,
+ (u32)PpkExp,
+ (RSA_NUMBER)PpkModular,
+ (RSA_NUMBER)PpkModularEx);
+ FsblPrintArray(DecryptSignature, RSA_SPK_SIGNATURE_SIZE,
+ "SPK Decrypted Hash");
+
+
+ Status = RecreatePaddingAndCheck(DecryptSignature, HashSignature);
+ if (Status != XST_SUCCESS) {
+ fsbl_printf(DEBUG_INFO, "Partition SPK Signature "
+ "Authentication failed\r\n");
+ return XST_FAILURE;
+ }
+ SignaturePtr += RSA_SPK_SIGNATURE_SIZE;
+
+ /*
+ * Decrypt Partition Signature
+ */
+ rsa2048_pubexp((RSA_NUMBER)DecryptSignature,
+ (RSA_NUMBER)SignaturePtr,
+ (u32)SpkExp,
+ (RSA_NUMBER)SpkModular,
+ (RSA_NUMBER)SpkModularEx);
+ FsblPrintArray(DecryptSignature, RSA_PARTITION_SIGNATURE_SIZE,
+ "Partition Decrypted Hash");
+
+ /*
+ * Partition Authentication
+ * Calculate Hash Signature
+ */
+ sha_256((u8 *)Buffer,
+ (Size - RSA_PARTITION_SIGNATURE_SIZE),
+ HashSignature);
+ FsblPrintArray(HashSignature, 32,
+ "Partition Hash Calculated");
+
+ Status = RecreatePaddingAndCheck(DecryptSignature, HashSignature);
+ if (Status != XST_SUCCESS) {
+ fsbl_printf(DEBUG_INFO, "Partition Signature "
+ "Authentication failed\r\n");
+ return XST_FAILURE;
+ }
+
+ return XST_SUCCESS;
+}
+
+
+/*****************************************************************************/
+/**
+*
+* This function recreates the and check signature
+*
+* @param Partition signature
+* @param Partition hash value which includes boot header, partition data
+* @return
+* - XST_SUCCESS if check passed
+* - XST_FAILURE if check failed
+*
+* @note None
+*
+******************************************************************************/
+u32 RecreatePaddingAndCheck(u8 *signature, u8 *hash)
+{
+ u8 T_padding[] = {0x30, 0x31, 0x30, 0x0D, 0x06, 0x09, 0x60, 0x86, 0x48,
+ 0x01, 0x65, 0x03, 0x04, 0x02, 0x01, 0x05, 0x00, 0x04, 0x20 };
+ u8 * pad_ptr = signature + 256;
+ u32 pad = 256 - 3 - 19 - 32;
+ u32 ii;
+
+ /*
+ * Re-Create PKCS#1v1.5 Padding
+ * MSB ----------------------------------------------------LSB
+ * 0x0 || 0x1 || 0xFF(for 202 bytes) || 0x0 || T_padding || SHA256 Hash
+ */
+ if (*--pad_ptr != 0x00 || *--pad_ptr != 0x01) {
+ return XST_FAILURE;
+ }
+
+ for (ii = 0; ii < pad; ii++) {
+ if (*--pad_ptr != 0xFF) {
+ return XST_FAILURE;
+ }
+ }
+
+ if (*--pad_ptr != 0x00) {
+ return XST_FAILURE;
+ }
+
+ for (ii = 0; ii < sizeof(T_padding); ii++) {
+ if (*--pad_ptr != T_padding[ii]) {
+ return XST_FAILURE;
+ }
+ }
+
+ for (ii = 0; ii < 32; ii++) {
+ if (*--pad_ptr != hash[ii])
+ return XST_FAILURE;
+ }
+
+ return XST_SUCCESS;
+}
+#endif
diff --git a/hello_world/sw/fsbl/rsa.h b/hello_world/sw/fsbl/rsa.h
new file mode 100644
index 0000000..958f06b
--- /dev/null
+++ b/hello_world/sw/fsbl/rsa.h
@@ -0,0 +1,74 @@
+/******************************************************************************
+*
+* Copyright (C) 2012 - 2014 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+* THE SOFTWARE.
+*
+*
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file rsa.h
+*
+* This file contains the RSA algorithm functions
+*
+* <pre>
+* MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ----- ---- -------- -------------------------------------------------------
+* 4.00a sg 02/28/13 Initial release
+*
+* </pre>
+*
+* @note
+*
+******************************************************************************/
+#ifndef ___RSA_H___
+#define ___RSA_H___
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+/***************************** Include Files *********************************/
+
+
+#define RSA_PPK_MODULAR_SIZE 256
+#define RSA_PPK_MODULAR_EXT_SIZE 256
+#define RSA_PPK_EXPO_SIZE 64
+#define RSA_SPK_MODULAR_SIZE 256
+#define RSA_SPK_MODULAR_EXT_SIZE 256
+#define RSA_SPK_EXPO_SIZE 64
+#define RSA_SPK_SIGNATURE_SIZE 256
+#define RSA_PARTITION_SIGNATURE_SIZE 256
+#define RSA_SIGNATURE_SIZE 0x6C0 /* Signature size in bytes */
+#define RSA_HEADER_SIZE 4 /* Signature header size in bytes */
+#define RSA_MAGIC_WORD_SIZE 60 /* Magic word size in bytes */
+
+void SetPpk(void );
+u32 AuthenticatePartition(u8 *Buffer, u32 Size);
+u32 RecreatePaddingAndCheck(u8 *signature, u8 *hash);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* ___RSA_H___ */
diff --git a/hello_world/sw/fsbl/sd.c b/hello_world/sw/fsbl/sd.c
new file mode 100644
index 0000000..b6058f1
--- /dev/null
+++ b/hello_world/sw/fsbl/sd.c
@@ -0,0 +1,185 @@
+/******************************************************************************
+*
+* Copyright (C) 2012 - 2014 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+* THE SOFTWARE.
+*
+*
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file sd.c
+*
+* Contains code for the SD card FLASH functionality.
+*
+* <pre>
+* MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ----- ---- -------- -------------------------------------------------------
+* 1.00a jz 04/28/11 Initial release
+* 7.00a kc 10/18/13 Integrated SD/MMC driver
+* 12.00a ssc 12/11/14 Fix for CR# 839182
+*
+* </pre>
+*
+* @note
+*
+******************************************************************************/
+
+/***************************** Include Files *********************************/
+#include "xparameters.h"
+#include "fsbl.h"
+
+#if defined(XPAR_PS7_SD_0_S_AXI_BASEADDR) || defined(XPAR_XSDPS_0_BASEADDR)
+
+#ifndef XPAR_PS7_SD_0_S_AXI_BASEADDR
+#define XPAR_PS7_SD_0_S_AXI_BASEADDR XPAR_XSDPS_0_BASEADDR
+#endif
+
+#include "xstatus.h"
+
+#include "ff.h"
+#include "sd.h"
+
+/************************** Constant Definitions *****************************/
+
+/**************************** Type Definitions *******************************/
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/************************** Function Prototypes ******************************/
+
+/************************** Variable Definitions *****************************/
+
+extern u32 FlashReadBaseAddress;
+
+
+static FIL fil; /* File object */
+static FATFS fatfs;
+static char buffer[32];
+static char *boot_file = buffer;
+
+/******************************************************************************/
+/******************************************************************************/
+/**
+*
+* This function initializes the controller for the SD FLASH interface.
+*
+* @param filename of the file that is to be used
+*
+* @return
+* - XST_SUCCESS if the controller initializes correctly
+* - XST_FAILURE if the controller fails to initializes correctly
+*
+* @note None.
+*
+****************************************************************************/
+u32 InitSD(const char *filename)
+{
+
+ FRESULT rc;
+ TCHAR *path = "0:/"; /* Logical drive number is 0 */
+
+ /* Register volume work area, initialize device */
+ rc = f_mount(&fatfs, path, 0);
+ fsbl_printf(DEBUG_INFO,"SD: rc= %.8x\n\r", rc);
+
+ if (rc != FR_OK) {
+ return XST_FAILURE;
+ }
+
+ strcpy_rom(buffer, filename);
+ boot_file = (char *)buffer;
+ FlashReadBaseAddress = XPAR_PS7_SD_0_S_AXI_BASEADDR;
+
+ rc = f_open(&fil, boot_file, FA_READ);
+ if (rc) {
+ fsbl_printf(DEBUG_GENERAL,"SD: Unable to open file %s: %d\n", boot_file, rc);
+ return XST_FAILURE;
+ }
+
+ return XST_SUCCESS;
+
+}
+
+/******************************************************************************/
+/**
+*
+* This function provides the SD FLASH interface for the Simplified header
+* functionality.
+*
+* @param SourceAddress is address in FLASH data space
+* @param DestinationAddress is address in OCM data space
+* @param LengthBytes is the number of bytes to move
+*
+* @return
+* - XST_SUCCESS if the write completes correctly
+* - XST_FAILURE if the write fails to completes correctly
+*
+* @note None.
+*
+****************************************************************************/
+u32 SDAccess( u32 SourceAddress, u32 DestinationAddress, u32 LengthBytes)
+{
+
+ FRESULT rc; /* Result code */
+ UINT br;
+
+ rc = f_lseek(&fil, SourceAddress);
+ if (rc) {
+ fsbl_printf(DEBUG_INFO,"SD: Unable to seek to %lx\n", SourceAddress);
+ return XST_FAILURE;
+ }
+
+ rc = f_read(&fil, (void*)DestinationAddress, LengthBytes, &br);
+
+ if (rc) {
+ fsbl_printf(DEBUG_GENERAL,"*** ERROR: f_read returned %d\r\n", rc);
+ }
+
+ return XST_SUCCESS;
+
+} /* End of SDAccess */
+
+
+/******************************************************************************/
+/**
+*
+* This function closes the file object
+*
+* @param None
+*
+* @return None.
+*
+* @note None.
+*
+****************************************************************************/
+void ReleaseSD(void) {
+
+ f_close(&fil);
+ return;
+
+
+}
+#endif
+
+
diff --git a/hello_world/sw/fsbl/sd.h b/hello_world/sw/fsbl/sd.h
new file mode 100644
index 0000000..8e84160
--- /dev/null
+++ b/hello_world/sw/fsbl/sd.h
@@ -0,0 +1,73 @@
+/******************************************************************************
+*
+* Copyright (C) 2012 - 2014 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+* THE SOFTWARE.
+*
+*
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file sd.h
+*
+* This file contains the interface for the Secure Digital (SD) card
+*
+* <pre>
+* MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ----- ---- -------- -------------------------------------------------------
+* 1.00a bh 03/10/11 Initial release
+* 7.00a kc 10/18/13 Integrated SD/MMC driver
+*
+* </pre>
+*
+* @note
+*
+******************************************************************************/
+#ifndef ___SD_H___
+#define ___SD_H___
+
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+
+/************************** Function Prototypes ******************************/
+
+#if defined(XPAR_PS7_SD_0_S_AXI_BASEADDR) || defined(XPAR_XSDPS_0_BASEADDR)
+u32 InitSD(const char *);
+
+u32 SDAccess( u32 SourceAddress,
+ u32 DestinationAddress,
+ u32 LengthWords);
+
+void ReleaseSD(void);
+#endif
+/************************** Variable Definitions *****************************/
+#ifdef __cplusplus
+}
+#endif
+
+
+#endif /* ___SD_H___ */
+
diff --git a/hello_world/sw/fsbl/zynq_fsbl_bsp/Makefile b/hello_world/sw/fsbl/zynq_fsbl_bsp/Makefile
new file mode 100644
index 0000000..55da498
--- /dev/null
+++ b/hello_world/sw/fsbl/zynq_fsbl_bsp/Makefile
@@ -0,0 +1,35 @@
+# Makefile generated by Xilinx.
+
+PROCESSOR = ps7_cortexa9_0
+LIBRARIES = ${PROCESSOR}/lib/libxil.a
+BSP_MAKEFILES := $(wildcard $(PROCESSOR)/libsrc/*/src/Makefile)
+SUBDIRS := $(patsubst %/Makefile, %, $(BSP_MAKEFILES))
+
+ifneq (,$(findstring win,$(RDI_PLATFORM)))
+ SHELL = CMD
+endif
+
+all: libs
+ @echo 'Finished building libraries'
+
+include: $(addsuffix /make.include,$(SUBDIRS))
+
+libs: $(addsuffix /make.libs,$(SUBDIRS))
+
+clean: $(addsuffix /make.clean,$(SUBDIRS))
+
+$(PROCESSOR)/lib/libxil.a: $(PROCESSOR)/lib/libxil_init.a
+ cp -f $< $@
+
+%/make.include: $(if $(wildcard $(PROCESSOR)/lib/libxil_init.a),$(PROCESSOR)/lib/libxil.a,)
+ @echo "Running Make include in $(subst /make.include,,$@)"
+ $(MAKE) -C $(subst /make.include,,$@) -s include "SHELL=$(SHELL)" "COMPILER=arm-none-eabi-gcc" "ASSEMBLER=arm-none-eabi-as" "ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS= -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=softfp -nostartfiles -g -Wall -Wextra"
+
+%/make.libs: include
+ @echo "Running Make libs in $(subst /make.libs,,$@)"
+ $(MAKE) -C $(subst /make.libs,,$@) -s libs "SHELL=$(SHELL)" "COMPILER=arm-none-eabi-gcc" "ASSEMBLER=arm-none-eabi-as" "ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS= -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=softfp -nostartfiles -g -Wall -Wextra"
+
+%/make.clean:
+ $(MAKE) -C $(subst /make.clean,,$@) -s clean
+clean:
+ rm -f ${PROCESSOR}/lib/libxil.a
diff --git a/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/include/_profile_timer_hw.h b/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/include/_profile_timer_hw.h
new file mode 100644
index 0000000..01e2b50
--- /dev/null
+++ b/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/include/_profile_timer_hw.h
@@ -0,0 +1,306 @@
+/******************************************************************************
+*
+* Copyright (C) 2004 - 2014 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+* THE SOFTWARE.
+*
+*
+*
+******************************************************************************
+*
+* _program_timer_hw.h:
+* Timer related functions
+*
+******************************************************************************/
+
+#ifndef PROFILE_TIMER_HW_H
+#define PROFILE_TIMER_HW_H
+
+#include "profile.h"
+
+#ifdef PROC_PPC
+#if defined __GNUC__
+# define SYNCHRONIZE_IO __asm__ volatile ("eieio")
+#elif defined __DCC__
+# define SYNCHRONIZE_IO __asm volatile(" eieio")
+#else
+# define SYNCHRONIZE_IO
+#endif
+#endif
+
+#ifdef PROC_PPC
+#define ProfIo_In32(InputPtr) { (*(volatile u32 *)(InputPtr)); SYNCHRONIZE_IO; }
+#define ProfIo_Out32(OutputPtr, Value) { (*(volatile u32 *)(OutputPtr) = Value); SYNCHRONIZE_IO; }
+#else
+#define ProfIo_In32(InputPtr) (*(volatile u32 *)(InputPtr));
+#define ProfIo_Out32(OutputPtr, Value) { (*(volatile u32 *)(OutputPtr) = (Value)); }
+#endif
+
+#define ProfTmrCtr_mWriteReg(BaseAddress, TmrCtrNumber, RegOffset, ValueToWrite)\
+ ProfIo_Out32(((u32)(BaseAddress) + (u32)XTmrCtr_Offsets[(TmrCtrNumber)] + \
+ (u32)(RegOffset)), (u32)(ValueToWrite))
+
+#define ProfTimerCtr_mReadReg(BaseAddress, TmrCtrNumber, RegOffset) \
+ ProfIo_In32((u32)(BaseAddress) + (u32)XTmrCtr_Offsets[(TmrCtrNumber)] + (u32)(RegOffset))
+
+#define ProfTmrCtr_mSetControlStatusReg(BaseAddress, TmrCtrNumber, RegisterValue)\
+ ProfTmrCtr_mWriteReg((BaseAddress), (TmrCtrNumber), XTC_TCSR_OFFSET, \
+ (RegisterValue))
+
+#define ProfTmrCtr_mGetControlStatusReg(BaseAddress, TmrCtrNumber) \
+ ProfTimerCtr_mReadReg((u32)(BaseAddress), (TmrCtrNumber), XTC_TCSR_OFFSET)
+
+
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#ifdef PROC_PPC
+#include "xexception_l.h"
+#include "xtime_l.h"
+#include "xpseudo_asm.h"
+#endif
+
+#ifdef TIMER_CONNECT_INTC
+#include "xintc_l.h"
+#include "xintc.h"
+#endif /* TIMER_CONNECT_INTC */
+
+#if (!defined PPC_PIT_INTERRUPT && !defined PROC_CORTEXA9)
+#include "xtmrctr_l.h"
+#endif
+
+#ifdef PROC_CORTEXA9
+#include "xscutimer_hw.h"
+#include "xscugic.h"
+#endif
+
+extern u32 timer_clk_ticks ;
+
+/*--------------------------------------------------------------------
+ * PowerPC Target - Timer related functions
+ *-------------------------------------------------------------------- */
+#ifdef PROC_PPC
+
+#ifdef PPC_PIT_INTERRUPT
+u32 timer_lo_clk_ticks ; /* Clk ticks when Timer is disabled in CG */
+#endif
+
+#ifdef PROC_PPC440
+#define XREG_TCR_PIT_INTERRUPT_ENABLE XREG_TCR_DEC_INTERRUPT_ENABLE
+#define XREG_TSR_PIT_INTERRUPT_STATUS XREG_TSR_DEC_INTERRUPT_STATUS
+#define XREG_SPR_PIT XREG_SPR_DEC
+#define XEXC_ID_PIT_INT XEXC_ID_DEC_INT
+#endif
+
+/* --------------------------------------------------------------------
+ * Disable the Timer - During Profiling
+ *
+ * For PIT Timer -
+ * 1. XTime_PITDisableInterrupt() ;
+ * 2. Store the remaining timer clk tick
+ * 3. Stop the PIT Timer
+ *-------------------------------------------------------------------- */
+
+#ifdef PPC_PIT_INTERRUPT
+#define disable_timer() \
+ { \
+ u32 val; \
+ val=mfspr(XREG_SPR_TCR); \
+ mtspr(XREG_SPR_TCR, val & (~XREG_TCR_PIT_INTERRUPT_ENABLE)); \
+ timer_lo_clk_ticks = mfspr(XREG_SPR_PIT); \
+ mtspr(XREG_SPR_PIT, 0); \
+ }
+#else
+#define disable_timer() \
+ { \
+ u32 addr = (PROFILE_TIMER_BASEADDR) + XTmrCtr_Offsets[(0)] + XTC_TCSR_OFFSET; \
+ u32 tmp_v = ProfIo_In32(addr); \
+ tmp_v = tmp_v & (~XTC_CSR_ENABLE_TMR_MASK); \
+ ProfIo_Out32((PROFILE_TIMER_BASEADDR) + XTmrCtr_Offsets[(0)] + XTC_TCSR_OFFSET, tmp_v); \
+ }
+#endif
+
+
+
+/* --------------------------------------------------------------------
+ * Enable the Timer
+ *
+ * For PIT Timer -
+ * 1. Load the remaining timer clk ticks
+ * 2. XTime_PITEnableInterrupt() ;
+ *-------------------------------------------------------------------- */
+#ifdef PPC_PIT_INTERRUPT
+#define enable_timer() \
+ { \
+ u32 val; \
+ val=mfspr(XREG_SPR_TCR); \
+ mtspr(XREG_SPR_PIT, timer_lo_clk_ticks); \
+ mtspr(XREG_SPR_TCR, val | XREG_TCR_PIT_INTERRUPT_ENABLE); \
+ }
+#else
+#define enable_timer() \
+ { \
+ u32 addr = (PROFILE_TIMER_BASEADDR) + XTmrCtr_Offsets[(0)] + XTC_TCSR_OFFSET; \
+ u32 tmp_v = ProfIo_In32(addr); \
+ tmp_v = tmp_v | XTC_CSR_ENABLE_TMR_MASK; \
+ ProfIo_Out32((PROFILE_TIMER_BASEADDR) + XTmrCtr_Offsets[(0)] + XTC_TCSR_OFFSET, tmp_v); \
+ }
+#endif
+
+
+
+/* --------------------------------------------------------------------
+ * Send Ack to Timer Interrupt
+ *
+ * For PIT Timer -
+ * 1. Load the timer clk ticks
+ * 2. Enable AutoReload and Interrupt
+ * 3. Clear PIT Timer Status bits
+ *-------------------------------------------------------------------- */
+#ifdef PPC_PIT_INTERRUPT
+#define timer_ack() \
+ { \
+ u32 val; \
+ mtspr(XREG_SPR_PIT, timer_clk_ticks); \
+ mtspr(XREG_SPR_TSR, XREG_TSR_PIT_INTERRUPT_STATUS); \
+ val=mfspr(XREG_SPR_TCR); \
+ mtspr(XREG_SPR_TCR, val| XREG_TCR_PIT_INTERRUPT_ENABLE| XREG_TCR_AUTORELOAD_ENABLE); \
+ }
+#else
+#define timer_ack() \
+ { \
+ u32 csr; \
+ csr = ProfTmrCtr_mGetControlStatusReg(PROFILE_TIMER_BASEADDR, 0); \
+ ProfTmrCtr_mSetControlStatusReg(PROFILE_TIMER_BASEADDR, 0, csr); \
+ }
+#endif
+
+/*-------------------------------------------------------------------- */
+#endif /* PROC_PPC */
+/* -------------------------------------------------------------------- */
+
+
+
+
+/* --------------------------------------------------------------------
+ * MicroBlaze Target - Timer related functions
+ *-------------------------------------------------------------------- */
+#ifdef PROC_MICROBLAZE
+
+/* --------------------------------------------------------------------
+ * Disable the Timer during Call-Graph Data collection
+ *
+ *-------------------------------------------------------------------- */
+#define disable_timer() \
+ { \
+ u32 Addr = ((u32)PROFILE_TIMER_BASEADDR); \
+ Addr += (u32)XTmrCtr_Offsets[(u16)(0)]; \
+ Addr += (u32)XTC_TCSR_OFFSET; \
+ u32 tmp_v = ProfIo_In32(Addr); \
+ tmp_v = tmp_v & (u32)(~XTC_CSR_ENABLE_TMR_MASK); \
+ u32 OutAddr = (u32)PROFILE_TIMER_BASEADDR; \
+ OutAddr += (u32)XTmrCtr_Offsets[(u16)(0)]; \
+ OutAddr += (u32)XTC_TCSR_OFFSET; \
+ ProfIo_Out32(OutAddr, (u32)tmp_v); \
+ }
+
+
+/* --------------------------------------------------------------------
+ * Enable the Timer after Call-Graph Data collection
+ *
+ *-------------------------------------------------------------------- */
+#define enable_timer() \
+ { \
+ u32 Addr = ((u32)PROFILE_TIMER_BASEADDR); \
+ Addr += (u32)XTmrCtr_Offsets[(u16)(0)]; \
+ Addr += (u32)XTC_TCSR_OFFSET; \
+ u32 tmp_v = (u32)ProfIo_In32(Addr); \
+ tmp_v = tmp_v | (u32)XTC_CSR_ENABLE_TMR_MASK; \
+ ProfIo_Out32((u32)(PROFILE_TIMER_BASEADDR) + (u32)XTmrCtr_Offsets[(u16)(0)] + (u32)XTC_TCSR_OFFSET, (u32)tmp_v); \
+ }
+
+
+/* --------------------------------------------------------------------
+ * Send Ack to Timer Interrupt
+ *
+ *-------------------------------------------------------------------- */
+#define timer_ack() \
+ { \
+ u32 csr; \
+ csr = ProfTmrCtr_mGetControlStatusReg((u32)PROFILE_TIMER_BASEADDR, (u16)0); \
+ ProfTmrCtr_mSetControlStatusReg((u32)PROFILE_TIMER_BASEADDR, (u16)0, (u32)csr); \
+ }
+
+/*-------------------------------------------------------------------- */
+#endif /* PROC_MICROBLAZE */
+/*-------------------------------------------------------------------- */
+
+/* --------------------------------------------------------------------
+ * Cortex A9 Target - Timer related functions
+ *-------------------------------------------------------------------- */
+#ifdef PROC_CORTEXA9
+
+/* --------------------------------------------------------------------
+ * Disable the Timer during Call-Graph Data collection
+ *
+ *-------------------------------------------------------------------- */
+#define disable_timer() \
+{ \
+ u32 Reg; \
+ Reg = Xil_In32(PROFILE_TIMER_BASEADDR + XSCUTIMER_CONTROL_OFFSET); \
+ Reg &= (~XSCUTIMER_CONTROL_ENABLE_MASK);\
+ Xil_Out32(PROFILE_TIMER_BASEADDR + XSCUTIMER_CONTROL_OFFSET, Reg);\
+}
+
+
+/* --------------------------------------------------------------------
+ * Enable the Timer after Call-Graph Data collection
+ *
+ *-------------------------------------------------------------------- */
+#define enable_timer() \
+{ \
+ u32 Reg; \
+ Reg = Xil_In32(PROFILE_TIMER_BASEADDR + XSCUTIMER_CONTROL_OFFSET); \
+ Reg |= XSCUTIMER_CONTROL_ENABLE_MASK; \
+ Xil_Out32(PROFILE_TIMER_BASEADDR + XSCUTIMER_CONTROL_OFFSET, Reg);\
+}
+
+
+/* --------------------------------------------------------------------
+ * Send Ack to Timer Interrupt
+ *
+ *-------------------------------------------------------------------- */
+#define timer_ack() \
+{ \
+ Xil_Out32((u32)PROFILE_TIMER_BASEADDR + (u32)XSCUTIMER_ISR_OFFSET, \
+ (u32)XSCUTIMER_ISR_EVENT_FLAG_MASK);\
+}
+
+/*-------------------------------------------------------------------- */
+#endif /* PROC_CORTEXA9 */
+/*-------------------------------------------------------------------- */
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff --git a/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/include/bspconfig.h b/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/include/bspconfig.h
new file mode 100644
index 0000000..5387688
--- /dev/null
+++ b/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/include/bspconfig.h
@@ -0,0 +1,40 @@
+
+/*******************************************************************
+*
+* CAUTION: This file is automatically generated by HSI.
+* Version: 2019.2
+* DO NOT EDIT.
+*
+* Copyright (C) 2010-2021 Xilinx, Inc. All Rights Reserved.*
+*Permission is hereby granted, free of charge, to any person obtaining a copy
+*of this software and associated documentation files (the Software), to deal
+*in the Software without restriction, including without limitation the rights
+*to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+*copies of the Software, and to permit persons to whom the Software is
+*furnished to do so, subject to the following conditions:
+*
+*The above copyright notice and this permission notice shall be included in
+*all copies or substantial portions of the Software.
+*
+*THE SOFTWARE IS PROVIDED AS IS, WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+*IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+*FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+*THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+*WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT
+*OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+*
+
+*
+* Description: Configurations for Standalone BSP
+*
+*******************************************************************/
+
+#ifndef BSPCONFIG_H /* prevent circular inclusions */
+#define BSPCONFIG_H /* by using protection macros */
+
+#define MICROBLAZE_PVR_NONE
+
+/* Definition for hard-float ABI */
+#define FPU_HARD_FLOAT_ABI_ENABLED 1
+
+#endif /*end of __BSPCONFIG_H_*/
diff --git a/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/include/diskio.h b/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/include/diskio.h
new file mode 100644
index 0000000..edd697a
--- /dev/null
+++ b/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/include/diskio.h
@@ -0,0 +1,79 @@
+/*-----------------------------------------------------------------------/
+/ Low level disk interface module include file (C)ChaN, 2014 /
+/-----------------------------------------------------------------------*/
+
+#ifndef DISKIO_DEFINED
+#define DISKIO_DEFINED
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#define USE_WRITE 1 /* 1: Enable disk_write function */
+#define USE_IOCTL 1 /* 1: Enable disk_ioctl function */
+
+#include "integer.h"
+#include "xil_types.h"
+
+/* Status of Disk Functions */
+typedef BYTE DSTATUS;
+
+/* Results of Disk Functions */
+typedef enum {
+ RES_OK = 0, /* 0: Successful */
+ RES_ERROR, /* 1: R/W Error */
+ RES_WRPRT, /* 2: Write Protected */
+ RES_NOTRDY, /* 3: Not Ready */
+ RES_PARERR /* 4: Invalid Parameter */
+} DRESULT;
+
+
+/*---------------------------------------*/
+/* Prototypes for disk control functions */
+
+DSTATUS disk_initialize (BYTE pdrv);
+DSTATUS disk_status (BYTE pdrv);
+DRESULT disk_read (BYTE pdrv, BYTE* buff, DWORD sector, UINT count);
+DRESULT disk_write (BYTE pdrv, const BYTE* buff, DWORD sector, UINT count);
+DRESULT disk_ioctl (BYTE pdrv, BYTE cmd, void* buff);
+
+
+/* Disk Status Bits (DSTATUS) */
+
+#define STA_NOINIT 0x01U /* Drive not initialized */
+#define STA_NODISK 0x02U /* No medium in the drive */
+#define STA_PROTECT 0x04U /* Write protected */
+
+
+/* Command code for disk_ioctrl function */
+
+/* Generic command (used by FatFs) */
+#define CTRL_SYNC 0U /* Flush disk cache (for write functions) */
+#define GET_SECTOR_COUNT 1U /* Get media size (for only f_mkfs()) */
+#define GET_SECTOR_SIZE 2U /* Get sector size (for multiple sector size (_MAX_SS >= 1024)) */
+#define GET_BLOCK_SIZE 3U /* Get erase block size (for only f_mkfs()) */
+#define CTRL_ERASE_SECTOR 4U /* Force erased a block of sectors (for only _USE_ERASE) */
+
+/* Generic command (not used by FatFs) */
+#define CTRL_POWER 5U /* Get/Set power status */
+#define CTRL_LOCK 6U /* Lock/Unlock media removal */
+#define CTRL_EJECT 7U /* Eject media */
+#define CTRL_FORMAT 8U /* Create physical format on the media */
+
+/* MMC/SDC specific ioctl command */
+#define MMC_GET_TYPE 10U /* Get card type */
+#define MMC_GET_CSD 11U /* Get CSD */
+#define MMC_GET_CID 12U /* Get CID */
+#define MMC_GET_OCR 13U /* Get OCR */
+#define MMC_GET_SDSTAT 14U /* Get SD status */
+
+/* ATA/CF specific ioctl command */
+#define ATA_GET_REV 20U /* Get F/W revision */
+#define ATA_GET_MODEL 21U /* Get model name */
+#define ATA_GET_SN 22U /* Get serial number */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff --git a/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/include/ff.h b/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/include/ff.h
new file mode 100644
index 0000000..967451e
--- /dev/null
+++ b/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/include/ff.h
@@ -0,0 +1,395 @@
+/*----------------------------------------------------------------------------/
+/ FatFs - Generic FAT Filesystem module R0.13b /
+/-----------------------------------------------------------------------------/
+/
+/ Copyright (C) 2018, ChaN, all right reserved.
+/
+/ FatFs module is an open source software. Redistribution and use of FatFs in
+/ source and binary forms, with or without modification, are permitted provided
+/ that the following condition is met:
+
+/ 1. Redistributions of source code must retain the above copyright notice,
+/ this condition and the following disclaimer.
+/
+/ This software is provided by the copyright holder and contributors "AS IS"
+/ and any warranties related to this software are DISCLAIMED.
+/ The copyright owner or contributors be NOT LIABLE for any damages caused
+/ by use of this software.
+/
+/----------------------------------------------------------------------------*/
+
+
+#ifndef FF_DEFINED
+#define FF_DEFINED 63463 /* Revision ID */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include "xil_types.h"
+#include "integer.h" /* Basic integer types */
+#include "ffconf.h" /* FatFs configuration options */
+
+#if FF_DEFINED != FFCONF_DEF
+#error Wrong configuration file (ffconf.h).
+#endif
+
+
+
+/* Definitions of volume management */
+
+#if FF_MULTI_PARTITION /* Multiple partition configuration */
+typedef struct {
+ BYTE pd; /* Physical drive number */
+ BYTE pt; /* Partition: 0:Auto detect, 1-4:Forced partition) */
+} PARTITION;
+extern PARTITION VolToPart[]; /* Volume - Partition resolution table */
+#endif
+
+#if FF_STR_VOLUME_ID
+#ifndef FF_VOLUME_STRS
+extern const char* VolumeStr[FF_VOLUMES]; /* User defied volume ID */
+#endif
+#endif
+
+
+
+/* Type of path name strings on FatFs API */
+
+#ifndef _INC_TCHAR
+#define _INC_TCHAR
+
+#if FF_USE_LFN && FF_LFN_UNICODE == 1 /* Unicode in UTF-16 encoding */
+typedef WCHAR TCHAR;
+#define _T(x) L ## x
+#define _TEXT(x) L ## x
+#elif FF_USE_LFN && FF_LFN_UNICODE == 2 /* Unicode in UTF-8 encoding */
+typedef char TCHAR;
+#define _T(x) u8 ## x
+#define _TEXT(x) u8 ## x
+#elif FF_USE_LFN && FF_LFN_UNICODE == 3 /* Unicode in UTF-32 encoding */
+typedef DWORD TCHAR;
+#define _T(x) U ## x
+#define _TEXT(x) U ## x
+#elif FF_USE_LFN && (FF_LFN_UNICODE < 0 || FF_LFN_UNICODE > 3)
+#error Wrong FF_LFN_UNICODE setting
+#else /* ANSI/OEM code in SBCS/DBCS */
+typedef char TCHAR;
+#define _T(x) x
+#define _TEXT(x) x
+#endif
+
+#endif
+
+
+
+/* Type of file size variables */
+
+#if FF_FS_EXFAT
+typedef QWORD FSIZE_t;
+#else
+typedef DWORD FSIZE_t;
+#endif
+
+
+
+/* Filesystem object structure (FATFS) */
+
+typedef struct {
+ BYTE fs_type; /* Filesystem type (0:N/A) */
+ BYTE pdrv; /* Physical drive number */
+ BYTE n_fats; /* Number of FATs (1 or 2) */
+ BYTE wflag; /* win[] flag (b0:dirty) */
+ BYTE fsi_flag; /* FSINFO flags (b7:disabled, b0:dirty) */
+ WORD id; /* Volume mount ID */
+ WORD n_rootdir; /* Number of root directory entries (FAT12/16) */
+ WORD csize; /* Cluster size [sectors] */
+#if FF_MAX_SS != FF_MIN_SS
+ WORD ssize; /* Sector size (512, 1024, 2048 or 4096) */
+#endif
+#if FF_USE_LFN
+ WCHAR* lfnbuf; /* LFN working buffer */
+#endif
+#if FF_FS_EXFAT
+ BYTE* dirbuf; /* Directory entry block scratchpad buffer for exFAT */
+#endif
+#if FF_FS_REENTRANT
+ FF_SYNC_t sobj; /* Identifier of sync object */
+#endif
+#if !FF_FS_READONLY
+ DWORD last_clst; /* Last allocated cluster */
+ DWORD free_clst; /* Number of free clusters */
+#endif
+#if FF_FS_RPATH
+ DWORD cdir; /* Current directory start cluster (0:root) */
+#if FF_FS_EXFAT
+ DWORD cdc_scl; /* Containing directory start cluster (invalid when cdir is 0) */
+ DWORD cdc_size; /* b31-b8:Size of containing directory, b7-b0: Chain status */
+ DWORD cdc_ofs; /* Offset in the containing directory (invalid when cdir is 0) */
+#endif
+#endif
+ DWORD n_fatent; /* Number of FAT entries (number of clusters + 2) */
+ DWORD fsize; /* Size of an FAT [sectors] */
+ DWORD volbase; /* Volume base sector */
+ DWORD fatbase; /* FAT base sector */
+ DWORD dirbase; /* Root directory base sector/cluster */
+ DWORD database; /* Data base sector */
+ DWORD winsect; /* Current sector appearing in the win[] */
+#ifdef __ICCARM__
+#pragma data_alignment = 32
+ BYTE win[FF_MAX_SS];
+#else
+#ifdef __aarch64__
+ BYTE win[FF_MAX_SS] __attribute__ ((aligned(64))); /* Disk access window for Directory, FAT (and file data at tiny cfg) */
+#else
+ BYTE win[FF_MAX_SS] __attribute__ ((aligned(32))); /* Disk access window for Directory, FAT (and file data at tiny cfg) */
+#endif
+#endif
+} FATFS;
+
+
+
+/* Object ID and allocation information (FFOBJID) */
+
+typedef struct {
+ FATFS* fs; /* Pointer to the hosting volume of this object */
+ WORD id; /* Hosting volume mount ID */
+ BYTE attr; /* Object attribute */
+ BYTE stat; /* Object chain status (b1-0: =0:not contiguous, =2:contiguous, =3:flagmented in this session, b2:sub-directory stretched) */
+ DWORD sclust; /* Object data start cluster (0:no cluster or root directory) */
+ FSIZE_t objsize; /* Object size (valid when sclust != 0) */
+#if FF_FS_EXFAT
+ DWORD n_cont; /* Size of first fragment - 1 (valid when stat == 3) */
+ DWORD n_frag; /* Size of last fragment needs to be written to FAT (valid when not zero) */
+ DWORD c_scl; /* Containing directory start cluster (valid when sclust != 0) */
+ DWORD c_size; /* b31-b8:Size of containing directory, b7-b0: Chain status (valid when c_scl != 0) */
+ DWORD c_ofs; /* Offset in the containing directory (valid when file object and sclust != 0) */
+#endif
+#if FF_FS_LOCK
+ UINT lockid; /* File lock ID origin from 1 (index of file semaphore table Files[]) */
+#endif
+} FFOBJID;
+
+
+
+/* File object structure (FIL) */
+
+typedef struct {
+ FFOBJID obj; /* Object identifier (must be the 1st member to detect invalid object pointer) */
+ BYTE flag; /* File status flags */
+ BYTE err; /* Abort flag (error code) */
+ FSIZE_t fptr; /* File read/write pointer (Zeroed on file open) */
+ DWORD clust; /* Current cluster of fpter (invalid when fptr is 0) */
+ DWORD sect; /* Sector number appearing in buf[] (0:invalid) */
+#if !FF_FS_READONLY
+ DWORD dir_sect; /* Sector number containing the directory entry (not used at exFAT) */
+ BYTE* dir_ptr; /* Pointer to the directory entry in the win[] (not used at exFAT) */
+#endif
+#if FF_USE_FASTSEEK
+ DWORD* cltbl; /* Pointer to the cluster link map table (nulled on open, set by application) */
+#endif
+#if !FF_FS_TINY
+#ifdef __ICCARM__
+#pragma data_alignment = 32
+ BYTE buf[FF_MAX_SS]; /* File private data read/write window */
+#else
+#ifdef __aarch64__
+ BYTE buf[FF_MAX_SS] __attribute__ ((aligned(64))); /* File private data read/write window */
+#else
+ BYTE buf[FF_MAX_SS] __attribute__ ((aligned(32))); /* File private data read/write window */
+#endif
+#endif
+#endif
+} FIL;
+
+
+
+/* Directory object structure (DIR) */
+
+typedef struct {
+ FFOBJID obj; /* Object identifier */
+ DWORD dptr; /* Current read/write offset */
+ DWORD clust; /* Current cluster */
+ DWORD sect; /* Current sector (0:Read operation has terminated) */
+ BYTE* dir; /* Pointer to the directory item in the win[] */
+ BYTE fn[12]; /* SFN (in/out) {body[8],ext[3],status[1]} */
+#if FF_USE_LFN
+ DWORD blk_ofs; /* Offset of current entry block being processed (0xFFFFFFFF:Invalid) */
+#endif
+#if FF_USE_FIND
+ const TCHAR* pat; /* Pointer to the name matching pattern */
+#endif
+} DIR;
+
+
+
+/* File information structure (FILINFO) */
+
+typedef struct {
+ FSIZE_t fsize; /* File size */
+ WORD fdate; /* Modified date */
+ WORD ftime; /* Modified time */
+ BYTE fattrib; /* File attribute */
+#if FF_USE_LFN
+ TCHAR altname[FF_SFN_BUF + 1];/* Altenative file name */
+ TCHAR fname[FF_LFN_BUF + 1]; /* Primary file name */
+#else
+ TCHAR fname[12 + 1]; /* File name */
+#endif
+} FILINFO;
+
+
+
+/* File function return code (FRESULT) */
+
+typedef enum {
+ FR_OK = 0, /* (0) Succeeded */
+ FR_DISK_ERR, /* (1) A hard error occurred in the low level disk I/O layer */
+ FR_INT_ERR, /* (2) Assertion failed */
+ FR_NOT_READY, /* (3) The physical drive cannot work */
+ FR_NO_FILE, /* (4) Could not find the file */
+ FR_NO_PATH, /* (5) Could not find the path */
+ FR_INVALID_NAME, /* (6) The path name format is invalid */
+ FR_DENIED, /* (7) Access denied due to prohibited access or directory full */
+ FR_EXIST, /* (8) Access denied due to prohibited access */
+ FR_INVALID_OBJECT, /* (9) The file/directory object is invalid */
+ FR_WRITE_PROTECTED, /* (10) The physical drive is write protected */
+ FR_INVALID_DRIVE, /* (11) The logical drive number is invalid */
+ FR_NOT_ENABLED, /* (12) The volume has no work area */
+ FR_NO_FILESYSTEM, /* (13) There is no valid FAT volume */
+ FR_MKFS_ABORTED, /* (14) The f_mkfs() aborted due to any problem */
+ FR_TIMEOUT, /* (15) Could not get a grant to access the volume within defined period */
+ FR_LOCKED, /* (16) The operation is rejected according to the file sharing policy */
+ FR_NOT_ENOUGH_CORE, /* (17) LFN working buffer could not be allocated */
+ FR_TOO_MANY_OPEN_FILES, /* (18) Number of open files > FF_FS_LOCK */
+ FR_INVALID_PARAMETER /* (19) Given parameter is invalid */
+} FRESULT;
+
+
+
+/*--------------------------------------------------------------*/
+/* FatFs module application interface */
+
+FRESULT f_open (FIL* fp, const TCHAR* path, BYTE mode); /* Open or create a file */
+FRESULT f_close (FIL* fp); /* Close an open file object */
+FRESULT f_read (FIL* fp, void* buff, UINT btr, UINT* br); /* Read data from the file */
+FRESULT f_write (FIL* fp, const void* buff, UINT btw, UINT* bw); /* Write data to the file */
+FRESULT f_lseek (FIL* fp, FSIZE_t ofs); /* Move file pointer of the file object */
+FRESULT f_truncate (FIL* fp); /* Truncate the file */
+FRESULT f_sync (FIL* fp); /* Flush cached data of the writing file */
+FRESULT f_opendir (DIR* dp, const TCHAR* path); /* Open a directory */
+FRESULT f_closedir (DIR* dp); /* Close an open directory */
+FRESULT f_readdir (DIR* dp, FILINFO* fno); /* Read a directory item */
+FRESULT f_findfirst (DIR* dp, FILINFO* fno, const TCHAR* path, const TCHAR* pattern); /* Find first file */
+FRESULT f_findnext (DIR* dp, FILINFO* fno); /* Find next file */
+FRESULT f_mkdir (const TCHAR* path); /* Create a sub directory */
+FRESULT f_unlink (const TCHAR* path); /* Delete an existing file or directory */
+FRESULT f_rename (const TCHAR* path_old, const TCHAR* path_new); /* Rename/Move a file or directory */
+FRESULT f_stat (const TCHAR* path, FILINFO* fno); /* Get file status */
+FRESULT f_chmod (const TCHAR* path, BYTE attr, BYTE mask); /* Change attribute of a file/dir */
+FRESULT f_utime (const TCHAR* path, const FILINFO* fno); /* Change timestamp of a file/dir */
+FRESULT f_chdir (const TCHAR* path); /* Change current directory */
+FRESULT f_chdrive (const TCHAR* path); /* Change current drive */
+FRESULT f_getcwd (TCHAR* buff, UINT len); /* Get current directory */
+FRESULT f_getfree (const TCHAR* path, DWORD* nclst, FATFS** fatfs); /* Get number of free clusters on the drive */
+FRESULT f_getlabel (const TCHAR* path, TCHAR* label, DWORD* vsn); /* Get volume label */
+FRESULT f_setlabel (const TCHAR* label); /* Set volume label */
+FRESULT f_forward (FIL* fp, UINT(*func)(const BYTE*,UINT), UINT btf, UINT* bf); /* Forward data to the stream */
+FRESULT f_expand (FIL* fp, FSIZE_t szf, BYTE opt); /* Allocate a contiguous block to the file */
+FRESULT f_mount (FATFS* fs, const TCHAR* path, BYTE opt); /* Mount/Unmount a logical drive */
+FRESULT f_mkfs (const TCHAR* path, BYTE opt, DWORD au, void* work, UINT len); /* Create a FAT volume */
+FRESULT f_fdisk (BYTE pdrv, const DWORD* szt, void* work); /* Divide a physical drive into some partitions */
+FRESULT f_setcp (WORD cp); /* Set current code page */
+int f_putc (TCHAR c, FIL* fp); /* Put a character to the file */
+int f_puts (const TCHAR* str, FIL* cp); /* Put a string to the file */
+int f_printf (FIL* fp, const TCHAR* str, ...); /* Put a formatted string to the file */
+TCHAR* f_gets (TCHAR* buff, int len, FIL* fp); /* Get a string from the file */
+
+#define f_eof(fp) ((int)((fp)->fptr == (fp)->obj.objsize))
+#define f_error(fp) ((fp)->err)
+#define f_tell(fp) ((fp)->fptr)
+#define f_size(fp) ((fp)->obj.objsize)
+#define f_rewind(fp) f_lseek((fp), 0)
+#define f_rewinddir(dp) f_readdir((dp), 0)
+#define f_rmdir(path) f_unlink(path)
+#define f_unmount(path) f_mount(0, path, 0)
+
+#ifndef EOF
+#define EOF (-1)
+#endif
+
+
+
+
+/*--------------------------------------------------------------*/
+/* Additional user defined functions */
+
+/* RTC function */
+#if !FF_FS_READONLY && !FF_FS_NORTC
+DWORD get_fattime (void);
+#endif
+
+/* LFN support functions */
+#if FF_USE_LFN >= 1 /* Code conversion (defined in unicode.c) */
+WCHAR ff_oem2uni (WCHAR oem, WORD cp); /* OEM code to Unicode conversion */
+WCHAR ff_uni2oem (DWORD uni, WORD cp); /* Unicode to OEM code conversion */
+DWORD ff_wtoupper (DWORD uni); /* Unicode upper-case conversion */
+#endif
+#if FF_USE_LFN == 3 /* Dynamic memory allocation */
+void* ff_memalloc (UINT msize); /* Allocate memory block */
+void ff_memfree (void* mblock); /* Free memory block */
+#endif
+
+/* Sync functions */
+#if FF_FS_REENTRANT
+int ff_cre_syncobj (BYTE vol, FF_SYNC_t* sobj); /* Create a sync object */
+int ff_req_grant (FF_SYNC_t sobj); /* Lock sync object */
+void ff_rel_grant (FF_SYNC_t sobj); /* Unlock sync object */
+int ff_del_syncobj (FF_SYNC_t sobj); /* Delete a sync object */
+#endif
+
+
+
+
+/*--------------------------------------------------------------*/
+/* Flags and offset address */
+
+
+/* File access mode and open method flags (3rd argument of f_open) */
+#define FA_READ 0x01
+#define FA_WRITE 0x02
+#define FA_OPEN_EXISTING 0x00
+#define FA_CREATE_NEW 0x04
+#define FA_CREATE_ALWAYS 0x08
+#define FA_OPEN_ALWAYS 0x10
+#define FA_OPEN_APPEND 0x30
+
+/* Fast seek controls (2nd argument of f_lseek) */
+#define CREATE_LINKMAP ((FSIZE_t)0 - 1)
+
+/* Format options (2nd argument of f_mkfs) */
+#define FM_FAT 0x01
+#define FM_FAT32 0x02
+#define FM_EXFAT 0x04
+#define FM_ANY 0x07
+#define FM_SFD 0x08
+
+/* Filesystem type (FATFS.fs_type) */
+#define FS_FAT12 1
+#define FS_FAT16 2
+#define FS_FAT32 3
+#define FS_EXFAT 4
+
+/* File attribute bits for directory entry (FILINFO.fattrib) */
+#define AM_RDO 0x01 /* Read only */
+#define AM_HID 0x02 /* Hidden */
+#define AM_SYS 0x04 /* System */
+#define AM_DIR 0x10 /* Directory */
+#define AM_ARC 0x20 /* Archive */
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* FF_DEFINED */
diff --git a/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/include/ffconf.h b/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/include/ffconf.h
new file mode 100644
index 0000000..cd9ec37
--- /dev/null
+++ b/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/include/ffconf.h
@@ -0,0 +1,380 @@
+/*---------------------------------------------------------------------------/
+/ FatFs - Configuration file
+/---------------------------------------------------------------------------*/
+
+
+#define FFCONF_DEF 63463 /* Revision ID */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include "xparameters.h"
+
+/*---------------------------------------------------------------------------/
+/ Function Configurations
+/---------------------------------------------------------------------------*/
+
+#ifdef FILE_SYSTEM_READ_ONLY
+#define FF_FS_READONLY 1 /* 1:Read only */
+#else
+#define FF_FS_READONLY 0 /* 0:Read/Write */
+#endif
+/* This option switches read-only configuration. (0:Read/Write or 1:Read-only)
+/ Read-only configuration removes writing API functions, f_write(), f_sync(),
+/ f_unlink(), f_mkdir(), f_chmod(), f_rename(), f_truncate(), f_getfree()
+/ and optional writing functions as well. */
+
+
+#define FF_FS_MINIMIZE 0
+/* This option defines minimization level to remove some basic API functions.
+/
+/ 0: Basic functions are fully enabled.
+/ 1: f_stat(), f_getfree(), f_unlink(), f_mkdir(), f_truncate() and f_rename()
+/ are removed.
+/ 2: f_opendir(), f_readdir() and f_closedir() are removed in addition to 1.
+/ 3: f_lseek() function is removed in addition to 2. */
+
+
+#if FILE_SYSTEM_USE_STRFUNC == 0
+#define FF_USE_STRFUNC 0 /* 0:Disable */
+#elif FILE_SYSTEM_USE_STRFUNC == 1
+#define FF_USE_STRFUNC 1 /* 1:Enable */
+#elif FILE_SYSTEM_USE_STRFUNC == 2
+#define FF_USE_STRFUNC 2 /* 2:Enable */
+#endif
+/* This option switches string functions, f_gets(), f_putc(), f_puts() and f_printf().
+/
+/ 0: Disable string functions.
+/ 1: Enable without LF-CRLF conversion.
+/ 2: Enable with LF-CRLF conversion. */
+
+
+#define FF_USE_FIND 0
+/* This option switches filtered directory read functions, f_findfirst() and
+/ f_findnext(). (0:Disable, 1:Enable 2:Enable with matching altname[] too) */
+
+#ifdef FILE_SYSTEM_USE_MKFS
+#define FF_USE_MKFS 1 /* 1:Enable */
+#else
+#define FF_USE_MKFS 0 /* 0:Disable */
+#endif
+/* This option switches f_mkfs() function. (0:Disable or 1:Enable) */
+
+
+#define FF_USE_FASTSEEK 0
+/* This option switches fast seek function. (0:Disable or 1:Enable) */
+
+
+#define FF_USE_EXPAND 0
+/* This option switches f_expand function. (0:Disable or 1:Enable) */
+
+
+#ifdef FILE_SYSTEM_USE_CHMOD
+#define FF_USE_CHMOD 1 /* 1:Enable */
+#else
+#define FF_USE_CHMOD 0 /* 0:Disable */
+#endif
+/* This option switches attribute manipulation functions, f_chmod() and f_utime().
+/ (0:Disable or 1:Enable) Also FF_FS_READONLY needs to be 0 to enable this option. */
+
+
+#define FF_USE_LABEL 0
+/* This option switches volume label functions, f_getlabel() and f_setlabel().
+/ (0:Disable or 1:Enable) */
+
+
+#define FF_USE_FORWARD 0
+/* This option switches f_forward() function. (0:Disable or 1:Enable) */
+
+
+/*---------------------------------------------------------------------------/
+/ Locale and Namespace Configurations
+/---------------------------------------------------------------------------*/
+
+#define FF_CODE_PAGE 932
+/* This option specifies the OEM code page to be used on the target system.
+/ Incorrect code page setting can cause a file open failure.
+/
+/ 437 - U.S.
+/ 720 - Arabic
+/ 737 - Greek
+/ 771 - KBL
+/ 775 - Baltic
+/ 850 - Latin 1
+/ 852 - Latin 2
+/ 855 - Cyrillic
+/ 857 - Turkish
+/ 860 - Portuguese
+/ 861 - Icelandic
+/ 862 - Hebrew
+/ 863 - Canadian French
+/ 864 - Arabic
+/ 865 - Nordic
+/ 866 - Russian
+/ 869 - Greek 2
+/ 932 - Japanese (DBCS)
+/ 936 - Simplified Chinese (DBCS)
+/ 949 - Korean (DBCS)
+/ 950 - Traditional Chinese (DBCS)
+/ 0 - Include all code pages above and configured by f_setcp()
+*/
+
+
+#ifdef FILE_SYSTEM_USE_LFN
+#define FF_USE_LFN FILE_SYSTEM_USE_LFN /* 0 to 3 */
+#else
+#define FF_USE_LFN 0 /* 0 to 3 */
+#endif
+#define FF_MAX_LFN 255
+/* The FF_USE_LFN switches the support for LFN (long file name).
+/
+/ 0: Disable LFN. FF_MAX_LFN has no effect.
+/ 1: Enable LFN with static working buffer on the BSS. Always NOT thread-safe.
+/ 2: Enable LFN with dynamic working buffer on the STACK.
+/ 3: Enable LFN with dynamic working buffer on the HEAP.
+/
+/ To enable the LFN, ffunicode.c needs to be added to the project. The LFN function
+/ requiers certain internal working buffer occupies (FF_MAX_LFN + 1) * 2 bytes and
+/ additional (FF_MAX_LFN + 44) / 15 * 32 bytes when exFAT is enabled.
+/ The FF_MAX_LFN defines size of the working buffer in UTF-16 code unit and it can
+/ be in range of 12 to 255. It is recommended to be set 255 to fully support LFN
+/ specification.
+/ When use stack for the working buffer, take care on stack overflow. When use heap
+/ memory for the working buffer, memory management functions, ff_memalloc() and
+/ ff_memfree() in ffsystem.c, need to be added to the project. */
+
+
+#define FF_LFN_UNICODE 0
+/* This option switches the character encoding on the API when LFN is enabled.
+/
+/ 0: ANSI/OEM in current CP (TCHAR = char)
+/ 1: Unicode in UTF-16 (TCHAR = WCHAR)
+/ 2: Unicode in UTF-8 (TCHAR = char)
+/ 3: Unicode in UTF-32 (TCHAR = DWORD)
+/
+/ Also behavior of string I/O functions will be affected by this option.
+/ When LFN is not enabled, this option has no effect. */
+
+
+#define FF_LFN_BUF 255
+#define FF_SFN_BUF 12
+/* This set of options defines size of file name members in the FILINFO structure
+/ which is used to read out directory items. These values should be suffcient for
+/ the file names to read. The maximum possible length of the read file name depends
+/ on character encoding. When LFN is not enabled, these options have no effect. */
+
+
+#define FF_STRF_ENCODE 3
+/* When FF_LFN_UNICODE >= 1 with LFN enabled, string I/O functions, f_gets(),
+/ f_putc(), f_puts and f_printf() convert the character encoding in it.
+/ This option selects assumption of character encoding ON THE FILE to be
+/ read/written via those functions.
+/
+/ 0: ANSI/OEM in current CP
+/ 1: Unicode in UTF-16LE
+/ 2: Unicode in UTF-16BE
+/ 3: Unicode in UTF-8
+*/
+
+
+#if FILE_SYSTEM_SET_FS_RPATH == 0
+#define FF_FS_RPATH 0U
+#elif FILE_SYSTEM_SET_FS_RPATH == 1
+#define FF_FS_RPATH 1U
+#elif FILE_SYSTEM_SET_FS_RPATH == 2
+#define FF_FS_RPATH 2U
+#endif
+/* This option configures support for relative path.
+/
+/ 0: Disable relative path and remove related functions.
+/ 1: Enable relative path. f_chdir() and f_chdrive() are available.
+/ 2: f_getcwd() function is available in addition to 1.
+*/
+
+
+/*---------------------------------------------------------------------------/
+/ Drive/Volume Configurations
+/---------------------------------------------------------------------------*/
+
+#if FILE_SYSTEM_NUM_LOGIC_VOL == 1
+#define FF_VOLUMES 1U
+#elif FILE_SYSTEM_NUM_LOGIC_VOL == 2
+#define FF_VOLUMES 2U
+#elif FILE_SYSTEM_NUM_LOGIC_VOL == 3
+#define FF_VOLUMES 3U
+#elif FILE_SYSTEM_NUM_LOGIC_VOL == 4
+#define FF_VOLUMES 4U
+#elif FILE_SYSTEM_NUM_LOGIC_VOL == 5
+#define FF_VOLUMES 5U
+#elif FILE_SYSTEM_NUM_LOGIC_VOL == 6
+#define FF_VOLUMES 6U
+#elif FILE_SYSTEM_NUM_LOGIC_VOL == 7
+#define FF_VOLUMES 7U
+#elif FILE_SYSTEM_NUM_LOGIC_VOL == 8
+#define FF_VOLUMES 8U
+#elif FILE_SYSTEM_NUM_LOGIC_VOL == 9
+#define FF_VOLUMES 9U
+#else
+#define FF_VOLUMES 10U
+#endif
+/* Number of volumes (logical drives) to be used. (1-10) */
+
+
+#define FF_STR_VOLUME_ID 0
+#define FF_VOLUME_STRS "RAM","NAND","CF","SD","SD2","USB","USB2","USB3"
+/* FF_STR_VOLUME_ID switches support for volume ID in arbitrary strings.
+/ When FF_STR_VOLUME_ID is set to 1 or 2, arbitrary strings can be used as drive
+/ number in the path name. FF_VOLUME_STRS defines the volume ID strings for each
+/ logical drives. Number of items must not be less than FF_VOLUMES. Valid
+/ characters for the volume ID strings are A-Z, a-z and 0-9, however, they are
+/ compared in case-insensitive. If FF_STR_VOLUME_ID >= 1 and FF_VOLUME_STRS is
+/ not defined, a user defined volume string table needs to be defined as:
+/
+/ const char* VolumeStr[FF_VOLUMES] = {"ram","flash","sd","usb",...
+*/
+
+
+#ifdef FILE_SYSTEM_MULTI_PARTITION
+#define FF_MULTI_PARTITION 1 /* 1:Enable multiple partition */
+#else
+#define FF_MULTI_PARTITION 0 /* 0:Single partition */
+#endif
+/* This option switches support for multiple volumes on the physical drive.
+/ By default (0), each logical drive number is bound to the same physical drive
+/ number and only an FAT volume found on the physical drive will be mounted.
+/ When this function is enabled (1), each logical drive number can be bound to
+/ arbitrary physical drive and partition listed in the VolToPart[]. Also f_fdisk()
+/ function will be available. */
+
+
+#define FF_MIN_SS 512
+#define FF_MAX_SS 512
+/* This set of options configures the range of sector size to be supported. (512,
+/ 1024, 2048 or 4096) Always set both 512 for most systems, generic memory card and
+/ harddisk. But a larger value may be required for on-board flash memory and some
+/ type of optical media. When FF_MAX_SS is larger than FF_MIN_SS, FatFs is configured
+/ for variable sector size mode and disk_ioctl() function needs to implement
+/ GET_SECTOR_SIZE command. */
+
+
+#define FF_USE_TRIM 0
+/* This option switches support for ATA-TRIM. (0:Disable or 1:Enable)
+/ To enable Trim function, also CTRL_TRIM command should be implemented to the
+/ disk_ioctl() function. */
+
+
+#define FF_FS_NOFSINFO 0
+/* If you need to know correct free space on the FAT32 volume, set bit 0 of this
+/ option, and f_getfree() function at first time after volume mount will force
+/ a full FAT scan. Bit 1 controls the use of last allocated cluster number.
+/
+/ bit0=0: Use free cluster count in the FSINFO if available.
+/ bit0=1: Do not trust free cluster count in the FSINFO.
+/ bit1=0: Use last allocated cluster number in the FSINFO if available.
+/ bit1=1: Do not trust last allocated cluster number in the FSINFO.
+*/
+
+
+
+/*---------------------------------------------------------------------------/
+/ System Configurations
+/---------------------------------------------------------------------------*/
+
+#define FF_FS_TINY 0
+/* This option switches tiny buffer configuration. (0:Normal or 1:Tiny)
+/ At the tiny configuration, size of file object (FIL) is shrunk FF_MAX_SS bytes.
+/ Instead of private sector buffer eliminated from the file object, common sector
+/ buffer in the filesystem object (FATFS) is used for the file data transfer. */
+
+
+#ifdef FILE_SYSTEM_FS_EXFAT
+#define FF_FS_EXFAT 1
+#else
+#define FF_FS_EXFAT 0
+#endif
+/* This option switches support for exFAT filesystem. (0:Disable or 1:Enable)
+/ To enable exFAT, also LFN needs to be enabled.
+/ Note that enabling exFAT discards ANSI C (C89) compatibility. */
+
+
+#define FF_FS_NORTC 0
+#define FF_NORTC_MON 1
+#define FF_NORTC_MDAY 1
+#define FF_NORTC_YEAR 2018
+/* The option FF_FS_NORTC switches timestamp functiton. If the system does not have
+/ any RTC function or valid timestamp is not needed, set FF_FS_NORTC = 1 to disable
+/ the timestamp function. Every object modified by FatFs will have a fixed timestamp
+/ defined by FF_NORTC_MON, FF_NORTC_MDAY and FF_NORTC_YEAR in local time.
+/ To enable timestamp function (FF_FS_NORTC = 0), get_fattime() function need to be
+/ added to the project to read current time form real-time clock. FF_NORTC_MON,
+/ FF_NORTC_MDAY and FF_NORTC_YEAR have no effect.
+/ These options have no effect at read-only configuration (FF_FS_READONLY = 1). */
+
+
+#define FF_FS_LOCK 0
+/* The option FF_FS_LOCK switches file lock function to control duplicated file open
+/ and illegal operation to open objects. This option must be 0 when FF_FS_READONLY
+/ is 1.
+/
+/ 0: Disable file lock function. To avoid volume corruption, application program
+/ should avoid illegal open, remove and rename to the open objects.
+/ >0: Enable file lock function. The value defines how many files/sub-directories
+/ can be opened simultaneously under file lock control. Note that the file
+/ lock control is independent of re-entrancy. */
+
+
+#define FF_FS_REENTRANT 0
+#define FF_FS_TIMEOUT 1000
+#define FF_SYNC_t HANDLE
+/* The option FF_FS_REENTRANT switches the re-entrancy (thread safe) of the FatFs
+/ module itself. Note that regardless of this option, file access to different
+/ volume is always re-entrant and volume control functions, f_mount(), f_mkfs()
+/ and f_fdisk() function, are always not re-entrant. Only file/directory access
+/ to the same volume is under control of this function.
+/
+/ 0: Disable re-entrancy. FF_FS_TIMEOUT and FF_SYNC_t have no effect.
+/ 1: Enable re-entrancy. Also user provided synchronization handlers,
+/ ff_req_grant(), ff_rel_grant(), ff_del_syncobj() and ff_cre_syncobj()
+/ function, must be added to the project. Samples are available in
+/ option/syscall.c.
+/
+/ The FF_FS_TIMEOUT defines timeout period in unit of time tick.
+/ The FF_SYNC_t defines O/S dependent sync object type. e.g. HANDLE, ID, OS_EVENT*,
+/ SemaphoreHandle_t and etc. A header file for O/S definitions needs to be
+/ included somewhere in the scope of ff.h. */
+
+/* #include <windows.h> // O/S definitions */
+
+#ifdef FILE_SYSTEM_WORD_ACCESS
+#define FF_WORD_ACCESS 1
+#else
+#define FF_WORD_ACCESS 0
+#endif
+/* The FF_WORD_ACCESS option is an only platform dependent option. It defines
+/ which access method is used to the word data on the FAT volume.
+/
+/ 0: Byte-by-byte access. Always compatible with all platforms.
+/ 1: Word access. Do not choose this unless under both the following conditions.
+/
+/ * Address misaligned memory access is always allowed for ALL instructions.
+/ * Byte order on the memory is little-endian.
+/
+/ If it is the case, FF_WORD_ACCESS can also be set to 1 to improve performance and
+/ reduce code size. Following table shows an example of some processor types.
+/
+/ ARM7TDMI 0 ColdFire 0 V850E 0
+/ Cortex-M3 0 Z80 0/1 V850ES 0/1
+/ Cortex-M0 0 RX600(LE) 0/1 TLCS-870 0/1
+/ AVR 0/1 RX600(BE) 0 TLCS-900 0/1
+/ AVR32 0 RL78 0 R32C 0
+/ PIC18 0/1 SH-2 0 M16C 0/1
+/ PIC24 0 H8S 0 MSP430 0
+/ PIC32 0 H8/300H 0 x86 0/1
+*/
+
+#ifdef __cplusplus
+}
+#endif
+
+/*--- End of configuration options ---*/
diff --git a/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/include/integer.h b/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/include/integer.h
new file mode 100644
index 0000000..b3c70ca
--- /dev/null
+++ b/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/include/integer.h
@@ -0,0 +1,36 @@
+/*-------------------------------------------*/
+/* Integer type definitions for FatFs module */
+/*-------------------------------------------*/
+
+#ifndef FF_INTEGER
+#define FF_INTEGER
+
+#ifdef _WIN32 /* FatFs development platform */
+
+#include <windows.h>
+typedef unsigned __int64 QWORD;
+
+#else /* Embedded platform */
+
+/* These types MUST be 16-bit or 32-bit */
+typedef int INT;
+typedef unsigned int UINT;
+
+/* This type MUST be 8-bit */
+typedef unsigned char BYTE;
+
+/* These types MUST be 16-bit */
+typedef short SHORT;
+typedef unsigned short WORD;
+typedef unsigned short WCHAR;
+
+/* These types MUST be 32-bit */
+typedef long LONG;
+typedef unsigned long DWORD;
+
+/* This type MUST be 64-bit (Remove this for ANSI C (C89) compatibility) */
+typedef unsigned long long QWORD;
+
+#endif
+
+#endif
diff --git a/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/include/mblaze_nt_types.h b/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/include/mblaze_nt_types.h
new file mode 100644
index 0000000..b6cfb84
--- /dev/null
+++ b/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/include/mblaze_nt_types.h
@@ -0,0 +1,48 @@
+/******************************************************************************
+*
+* Copyright (C) 2002 - 2014 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+* THE SOFTWARE.
+*
+*
+*
+******************************************************************************/
+
+
+#ifndef _MBLAZE_NT_TYPES_H
+#define _MBLAZE_NT_TYPES_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+typedef char byte;
+typedef short half;
+typedef int word;
+typedef unsigned char ubyte;
+typedef unsigned short uhalf;
+typedef unsigned int uword;
+typedef ubyte boolean;
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff --git a/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/include/profile.h b/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/include/profile.h
new file mode 100644
index 0000000..8b105c1
--- /dev/null
+++ b/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/include/profile.h
@@ -0,0 +1,125 @@
+/******************************************************************************
+*
+* Copyright (C) 2002 - 2014 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+* THE SOFTWARE.
+*
+*
+*
+******************************************************************************/
+
+#ifndef PROFILE_H
+#define PROFILE_H 1
+
+#include <stdio.h>
+#include "xil_types.h"
+#include "profile_config.h"
+
+#ifdef PROC_MICROBLAZE
+#include "mblaze_nt_types.h"
+#endif
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+void _system_init( void ) ;
+void _system_clean( void ) ;
+void mcount(u32 frompc, u32 selfpc);
+void profile_intr_handler( void ) ;
+void _profile_init( void );
+
+
+
+/****************************************************************************
+ * Profiling on hardware - Hash table maintained on hardware and data sent
+ * to xmd for gmon.out generation.
+ ****************************************************************************/
+/*
+ * histogram counters are unsigned shorts (according to the kernel).
+ */
+#define HISTCOUNTER u16
+
+struct tostruct {
+ u32 selfpc;
+ s32 count;
+ s16 link;
+ u16 pad;
+};
+
+struct fromstruct {
+ u32 frompc ;
+ s16 link ;
+ u16 pad ;
+} ;
+
+/*
+ * general rounding functions.
+ */
+#define ROUNDDOWN(x,y) (((x)/(y))*(y))
+#define ROUNDUP(x,y) ((((x)+(y)-1)/(y))*(y))
+
+/*
+ * The profiling data structures are housed in this structure.
+ */
+struct gmonparam {
+ s32 state;
+
+ /* Histogram Information */
+ u16 *kcount; /* No. of bins in histogram */
+ u32 kcountsize; /* Histogram samples */
+
+ /* Call-graph Information */
+ struct fromstruct *froms;
+ u32 fromssize;
+ struct tostruct *tos;
+ u32 tossize;
+
+ /* Initialization I/Ps */
+ u32 lowpc;
+ u32 highpc;
+ u32 textsize;
+ /* u32 cg_froms, */
+ /* u32 cg_tos, */
+};
+extern struct gmonparam *_gmonparam;
+extern s32 n_gmon_sections;
+
+/*
+ * Possible states of profiling.
+ */
+#define GMON_PROF_ON 0
+#define GMON_PROF_BUSY 1
+#define GMON_PROF_ERROR 2
+#define GMON_PROF_OFF 3
+
+/*
+ * Sysctl definitions for extracting profiling information from the kernel.
+ */
+#define GPROF_STATE 0 /* int: profiling enabling variable */
+#define GPROF_COUNT 1 /* struct: profile tick count buffer */
+#define GPROF_FROMS 2 /* struct: from location hash bucket */
+#define GPROF_TOS 3 /* struct: destination/count structure */
+#define GPROF_GMONPARAM 4 /* struct: profiling parameters (see above) */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* PROFILE_H */
diff --git a/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/include/sleep.h b/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/include/sleep.h
new file mode 100644
index 0000000..9245419
--- /dev/null
+++ b/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/include/sleep.h
@@ -0,0 +1,113 @@
+/******************************************************************************
+*
+* Copyright (C) 2014 - 2017 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+* THE SOFTWARE.
+*
+*
+*
+******************************************************************************/
+
+/*****************************************************************************/
+/**
+* @file sleep.h
+*
+* This header file contains ARM Cortex A53,A9,R5,Microblaze specific sleep
+* related APIs.
+*
+* <pre>
+* MODIFICATION HISTORY :
+*
+* Ver Who Date Changes
+* ----- ---- -------- -------------------------------------------------------
+* 6.6 srm 11/02/17 Added processor specific sleep routines
+* function prototypes.
+*
+* </pre>
+*
+******************************************************************************/
+
+#ifndef SLEEP_H
+#define SLEEP_H
+
+#include "xil_types.h"
+#include "xil_io.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*****************************************************************************/
+/**
+*
+* This macro polls an address periodically until a condition is met or till the
+* timeout occurs.
+* The minimum timeout for calling this macro is 100us. If the timeout is less
+* than 100us, it still waits for 100us. Also the unit for the timeout is 100us.
+* If the timeout is not a multiple of 100us, it waits for a timeout of
+* the next usec value which is a multiple of 100us.
+*
+* @param IO_func - accessor function to read the register contents.
+* Depends on the register width.
+* @param ADDR - Address to be polled
+* @param VALUE - variable to read the value
+* @param COND - Condition to checked (usually involves VALUE)
+* @param TIMEOUT_US - timeout in micro seconds
+*
+* @return 0 - when the condition is met
+* -1 - when the condition is not met till the timeout period
+*
+* @note none
+*
+*****************************************************************************/
+#define Xil_poll_timeout(IO_func, ADDR, VALUE, COND, TIMEOUT_US) \
+ ( { \
+ u64 timeout = TIMEOUT_US/100; \
+ if(TIMEOUT_US%100!=0) \
+ timeout++; \
+ for(;;) { \
+ VALUE = IO_func(ADDR); \
+ if(COND) \
+ break; \
+ else { \
+ usleep(100); \
+ timeout--; \
+ if(timeout==0) \
+ break; \
+ } \
+ } \
+ (timeout>0) ? 0 : -1; \
+ } )
+
+void usleep(unsigned long useconds);
+void sleep(unsigned int seconds);
+int usleep_R5(unsigned long useconds);
+unsigned sleep_R5(unsigned int seconds);
+int usleep_MB(unsigned long useconds);
+unsigned sleep_MB(unsigned int seconds);
+int usleep_A53(unsigned long useconds);
+unsigned sleep_A53(unsigned int seconds);
+int usleep_A9(unsigned long useconds);
+unsigned sleep_A9(unsigned int seconds);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff --git a/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/include/smc.h b/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/include/smc.h
new file mode 100644
index 0000000..94d4c0e
--- /dev/null
+++ b/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/include/smc.h
@@ -0,0 +1,108 @@
+/******************************************************************************
+*
+* Copyright (C) 2010 - 2015 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+* THE SOFTWARE.
+*
+*
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+* @file smc.h
+*
+* <pre>
+* MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ----- ---- -------- ---------------------------------------------------
+* 1.00a sdm 11/03/09 Initial release.
+* 4.2 pkp 08/04/14 Removed function definition of XSmc_NorInit and XSmc_NorInit
+* as smc.c is removed
+* </pre>
+*
+* @note None.
+*
+******************************************************************************/
+
+#ifndef SMC_H /* prevent circular inclusions */
+#define SMC_H /* by using protection macros */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/***************************** Include Files *********************************/
+
+#include "xparameters.h"
+#include "xil_io.h"
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/**************************** Type Definitions *******************************/
+
+/************************** Constant Definitions *****************************/
+
+/* Memory controller configuration register offset */
+#define XSMCPSS_MC_STATUS 0x000U /* Controller status reg, RO */
+#define XSMCPSS_MC_INTERFACE_CONFIG 0x004U /* Interface config reg, RO */
+#define XSMCPSS_MC_SET_CONFIG 0x008U /* Set configuration reg, WO */
+#define XSMCPSS_MC_CLR_CONFIG 0x00CU /* Clear config reg, WO */
+#define XSMCPSS_MC_DIRECT_CMD 0x010U /* Direct command reg, WO */
+#define XSMCPSS_MC_SET_CYCLES 0x014U /* Set cycles register, WO */
+#define XSMCPSS_MC_SET_OPMODE 0x018U /* Set opmode register, WO */
+#define XSMCPSS_MC_REFRESH_PERIOD_0 0x020U /* Refresh period_0 reg, RW */
+#define XSMCPSS_MC_REFRESH_PERIOD_1 0x024U /* Refresh period_1 reg, RW */
+
+/* Chip select configuration register offset */
+#define XSMCPSS_CS_IF0_CHIP_0_OFFSET 0x100U /* Interface 0 chip 0 config */
+#define XSMCPSS_CS_IF0_CHIP_1_OFFSET 0x120U /* Interface 0 chip 1 config */
+#define XSMCPSS_CS_IF0_CHIP_2_OFFSET 0x140U /* Interface 0 chip 2 config */
+#define XSMCPSS_CS_IF0_CHIP_3_OFFSET 0x160U /* Interface 0 chip 3 config */
+#define XSMCPSS_CS_IF1_CHIP_0_OFFSET 0x180U /* Interface 1 chip 0 config */
+#define XSMCPSS_CS_IF1_CHIP_1_OFFSET 0x1A0U /* Interface 1 chip 1 config */
+#define XSMCPSS_CS_IF1_CHIP_2_OFFSET 0x1C0U /* Interface 1 chip 2 config */
+#define XSMCPSS_CS_IF1_CHIP_3_OFFSET 0x1E0U /* Interface 1 chip 3 config */
+
+/* User configuration register offset */
+#define XSMCPSS_UC_STATUS_OFFSET 0x200U /* User status reg, RO */
+#define XSMCPSS_UC_CONFIG_OFFSET 0x204U /* User config reg, WO */
+
+/* Integration test register offset */
+#define XSMCPSS_IT_OFFSET 0xE00U
+
+/* ID configuration register offset */
+#define XSMCPSS_ID_PERIP_0_OFFSET 0xFE0U
+#define XSMCPSS_ID_PERIP_1_OFFSET 0xFE4U
+#define XSMCPSS_ID_PERIP_2_OFFSET 0xFE8U
+#define XSMCPSS_ID_PERIP_3_OFFSET 0xFECU
+#define XSMCPSS_ID_PCELL_0_OFFSET 0xFF0U
+#define XSMCPSS_ID_PCELL_1_OFFSET 0xFF4U
+#define XSMCPSS_ID_PCELL_2_OFFSET 0xFF8U
+#define XSMCPSS_ID_PCELL_3_OFFSET 0xFFCU
+
+/************************** Variable Definitions *****************************/
+
+/************************** Function Prototypes ******************************/
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+
+#endif /* SMC_H */
diff --git a/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/include/vectors.h b/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/include/vectors.h
new file mode 100644
index 0000000..2647862
--- /dev/null
+++ b/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/include/vectors.h
@@ -0,0 +1,82 @@
+/******************************************************************************
+*
+* Copyright (C) 2009 - 2016 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+* THE SOFTWARE.
+*
+*
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+* @file vectors.h
+*
+* This file contains the C level vector prototypes for the ARM Cortex A9 core.
+*
+* <pre>
+* MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ----- ---- -------- ---------------------------------------------------
+* 1.00a ecm 10/20/10 Initial version, moved over from bsp area
+* 6.0 mus 07/27/16 Consolidated vectors for a9,a53 and r5 processors
+* </pre>
+*
+* @note
+*
+* None.
+*
+******************************************************************************/
+
+#ifndef _VECTORS_H_
+#define _VECTORS_H_
+
+/***************************** Include Files *********************************/
+
+#include "xil_types.h"
+#include "xil_assert.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/**************************** Type Definitions *******************************/
+
+/************************** Constant Definitions *****************************/
+
+/************************** Function Prototypes ******************************/
+
+void FIQInterrupt(void);
+void IRQInterrupt(void);
+#if !defined (__aarch64__)
+void SWInterrupt(void);
+void DataAbortInterrupt(void);
+void PrefetchAbortInterrupt(void);
+void UndefinedException(void);
+#else
+void SynchronousInterrupt(void);
+void SErrorInterrupt(void);
+#endif
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* protection macro */
diff --git a/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/include/xadcps.h b/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/include/xadcps.h
new file mode 100644
index 0000000..ef4fde4
--- /dev/null
+++ b/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/include/xadcps.h
@@ -0,0 +1,587 @@
+/******************************************************************************
+*
+* Copyright (C) 2011 - 2014 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+* THE SOFTWARE.
+*
+*
+*
+******************************************************************************/
+/****************************************************************************/
+/**
+*
+* @file xadcps.h
+* @addtogroup xadcps_v2_3
+* @{
+* @details
+*
+* The XAdcPs driver supports the Xilinx XADC/ADC device.
+*
+* The XADC/ADC device has the following features:
+* - 10-bit, 200-KSPS (kilo samples per second)
+* Analog-to-Digital Converter (ADC)
+* - Monitoring of on-chip supply voltages and temperature
+* - 1 dedicated differential analog-input pair and
+* 16 auxiliary differential analog-input pairs
+* - Automatic alarms based on user defined limits for the on-chip
+* supply voltages and temperature
+* - Automatic Channel Sequencer, programmable averaging, programmable
+* acquisition time for the external inputs, unipolar or differential
+* input selection for the external inputs
+* - Inbuilt Calibration
+* - Optional interrupt request generation
+*
+*
+* The user should refer to the hardware device specification for detailed
+* information about the device.
+*
+* This header file contains the prototypes of driver functions that can
+* be used to access the XADC/ADC device.
+*
+*
+* <b> XADC Channel Sequencer Modes </b>
+*
+* The XADC Channel Sequencer supports the following operating modes:
+*
+* - <b> Default </b>: This is the default mode after power up.
+* In this mode of operation the XADC operates in
+* a sequence mode, monitoring the on chip sensors:
+* Temperature, VCCINT, and VCCAUX.
+* - <b> One pass through sequence </b>: In this mode the XADC
+* converts the channels enabled in the Sequencer Channel Enable
+* registers for a single pass and then stops.
+* - <b> Continuous cycling of sequence </b>: In this mode the XADC
+* converts the channels enabled in the Sequencer Channel Enable
+* registers continuously.
+* - <b> Single channel mode</b>: In this mode the XADC Channel
+* Sequencer is disabled and the XADC operates in a
+* Single Channel Mode.
+* The XADC can operate either in a Continuous or Event
+* driven sampling mode in the single channel mode.
+* - <b> Simultaneous Sampling Mode</b>: In this mode the XADC Channel
+* Sequencer will automatically sequence through eight fixed pairs
+* of auxiliary analog input channels for simulataneous conversion.
+* - <b> Independent ADC mode</b>: In this mode the first ADC (A) is used to
+* is used to implement a fixed monitoring mode similar to the
+* default mode but the alarm fucntions ar eenabled.
+* The second ADC (B) is available to be used with external analog
+* input channels only.
+*
+* Read the XADC spec for more information about the sequencer modes.
+*
+* <b> Initialization and Configuration </b>
+*
+* The device driver enables higher layer software (e.g., an application) to
+* communicate to the XADC/ADC device.
+*
+* XAdcPs_CfgInitialize() API is used to initialize the XADC/ADC
+* device. The user needs to first call the XAdcPs_LookupConfig() API which
+* returns the Configuration structure pointer which is passed as a parameter to
+* the XAdcPs_CfgInitialize() API.
+*
+*
+* <b>Interrupts</b>
+*
+* The XADC/ADC device supports interrupt driven mode and the default
+* operation mode is polling mode.
+*
+* The interrupt mode is available only if hardware is configured to support
+* interrupts.
+*
+* This driver does not provide a Interrupt Service Routine (ISR) for the device.
+* It is the responsibility of the application to provide one if needed. Refer to
+* the interrupt example provided with this driver for details on using the
+* device in interrupt mode.
+*
+*
+* <b> Virtual Memory </b>
+*
+* This driver supports Virtual Memory. The RTOS is responsible for calculating
+* the correct device base address in Virtual Memory space.
+*
+*
+* <b> Threads </b>
+*
+* This driver is not thread safe. Any needs for threads or thread mutual
+* exclusion must be satisfied by the layer above this driver.
+*
+*
+* <b> Asserts </b>
+*
+* Asserts are used within all Xilinx drivers to enforce constraints on argument
+* values. Asserts can be turned off on a system-wide basis by defining, at
+* compile time, the NDEBUG identifier. By default, asserts are turned on and it
+* is recommended that users leave asserts on during development.
+*
+*
+* <b> Building the driver </b>
+*
+* The XAdcPs driver is composed of several source files. This allows the user
+* to build and link only those parts of the driver that are necessary.
+*
+* <b> Limitations of the driver </b>
+*
+* XADC/ADC device can be accessed through the JTAG port and the PLB
+* interface. The driver implementation does not support the simultaneous access
+* of the device by both these interfaces. The user has to care of this situation
+* in the user application code.
+*
+* <br><br>
+*
+* <pre>
+*
+* MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ----- ----- -------- -----------------------------------------------------
+* 1.00a ssb 12/22/11 First release based on the XPS/AXI xadc driver
+* 1.01a bss 02/18/13 Modified XAdcPs_SetSeqChEnables,XAdcPs_SetSeqAvgEnables
+* XAdcPs_SetSeqInputMode and XAdcPs_SetSeqAcqTime APIs
+* in xadcps.c to fix CR #693371
+* 1.03a bss 11/01/13 Modified xadcps_hw.h to use correct Register offsets
+* CR#749687
+* 2.1 bss 08/05/14 Added declarations for XAdcPs_SetSequencerEvent,
+* XAdcPs_GetSamplingMode, XAdcPs_SetMuxMode,
+* XAdcPs_SetPowerdownMode and XAdcPs_GetPowerdownMode
+* functions.
+* Modified Assert for XAdcPs_SetSingleChParams in
+* xadcps.c to fix CR #807563.
+* 2.2 bss 04/27/14 Modified to use correct Device Config base address in
+* xadcps.c (CR#854437).
+* ms 01/23/17 Added xil_printf statement in main function for all
+* examples to ensure that "Successfully ran" and "Failed"
+* strings are available in all examples. This is a fix
+* for CR-965028.
+* ms 03/17/17 Added readme.txt file in examples folder for doxygen
+* generation.
+* ms 04/05/17 Modified Comment lines in functions of xadcps
+* examples to recognize it as documentation block
+* for doxygen generation.
+* 2.3 mn 07/09/18 Fix Doxygen warning
+*
+* </pre>
+*
+*****************************************************************************/
+#ifndef XADCPS_H /* Prevent circular inclusions */
+#define XADCPS_H /* by using protection macros */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/***************************** Include Files ********************************/
+
+#include "xil_types.h"
+#include "xil_assert.h"
+#include "xstatus.h"
+#include "xadcps_hw.h"
+
+/************************** Constant Definitions ****************************/
+
+
+/**
+ * @name Indexes for the different channels.
+ * @{
+ */
+#define XADCPS_CH_TEMP 0x0 /**< On Chip Temperature */
+#define XADCPS_CH_VCCINT 0x1 /**< VCCINT */
+#define XADCPS_CH_VCCAUX 0x2 /**< VCCAUX */
+#define XADCPS_CH_VPVN 0x3 /**< VP/VN Dedicated analog inputs */
+#define XADCPS_CH_VREFP 0x4 /**< VREFP */
+#define XADCPS_CH_VREFN 0x5 /**< VREFN */
+#define XADCPS_CH_VBRAM 0x6 /**< On-chip VBRAM Data Reg, 7 series */
+#define XADCPS_CH_SUPPLY_CALIB 0x07 /**< Supply Calib Data Reg */
+#define XADCPS_CH_ADC_CALIB 0x08 /**< ADC Offset Channel Reg */
+#define XADCPS_CH_GAINERR_CALIB 0x09 /**< Gain Error Channel Reg */
+#define XADCPS_CH_VCCPINT 0x0D /**< On-chip PS VCCPINT Channel , Zynq */
+#define XADCPS_CH_VCCPAUX 0x0E /**< On-chip PS VCCPAUX Channel , Zynq */
+#define XADCPS_CH_VCCPDRO 0x0F /**< On-chip PS VCCPDRO Channel , Zynq */
+#define XADCPS_CH_AUX_MIN 16 /**< Channel number for 1st Aux Channel */
+#define XADCPS_CH_AUX_MAX 31 /**< Channel number for Last Aux channel */
+
+/*@}*/
+
+
+/**
+ * @name Indexes for reading the Calibration Coefficient Data.
+ * @{
+ */
+#define XADCPS_CALIB_SUPPLY_COEFF 0 /**< Supply Offset Calib Coefficient */
+#define XADCPS_CALIB_ADC_COEFF 1 /**< ADC Offset Calib Coefficient */
+#define XADCPS_CALIB_GAIN_ERROR_COEFF 2 /**< Gain Error Calib Coefficient*/
+/*@}*/
+
+
+/**
+ * @name Indexes for reading the Minimum/Maximum Measurement Data.
+ * @{
+ */
+#define XADCPS_MAX_TEMP 0 /**< Maximum Temperature Data */
+#define XADCPS_MAX_VCCINT 1 /**< Maximum VCCINT Data */
+#define XADCPS_MAX_VCCAUX 2 /**< Maximum VCCAUX Data */
+#define XADCPS_MAX_VBRAM 3 /**< Maximum VBRAM Data */
+#define XADCPS_MIN_TEMP 4 /**< Minimum Temperature Data */
+#define XADCPS_MIN_VCCINT 5 /**< Minimum VCCINT Data */
+#define XADCPS_MIN_VCCAUX 6 /**< Minimum VCCAUX Data */
+#define XADCPS_MIN_VBRAM 7 /**< Minimum VBRAM Data */
+#define XADCPS_MAX_VCCPINT 8 /**< Maximum VCCPINT Register , Zynq */
+#define XADCPS_MAX_VCCPAUX 9 /**< Maximum VCCPAUX Register , Zynq */
+#define XADCPS_MAX_VCCPDRO 0xA /**< Maximum VCCPDRO Register , Zynq */
+#define XADCPS_MIN_VCCPINT 0xC /**< Minimum VCCPINT Register , Zynq */
+#define XADCPS_MIN_VCCPAUX 0xD /**< Minimum VCCPAUX Register , Zynq */
+#define XADCPS_MIN_VCCPDRO 0xE /**< Minimum VCCPDRO Register , Zynq */
+
+/*@}*/
+
+
+/**
+ * @name Alarm Threshold(Limit) Register (ATR) indexes.
+ * @{
+ */
+#define XADCPS_ATR_TEMP_UPPER 0 /**< High user Temperature */
+#define XADCPS_ATR_VCCINT_UPPER 1 /**< VCCINT high voltage limit register */
+#define XADCPS_ATR_VCCAUX_UPPER 2 /**< VCCAUX high voltage limit register */
+#define XADCPS_ATR_OT_UPPER 3 /**< VCCAUX high voltage limit register */
+#define XADCPS_ATR_TEMP_LOWER 4 /**< Upper Over Temperature limit Reg */
+#define XADCPS_ATR_VCCINT_LOWER 5 /**< VCCINT high voltage limit register */
+#define XADCPS_ATR_VCCAUX_LOWER 6 /**< VCCAUX low voltage limit register */
+#define XADCPS_ATR_OT_LOWER 7 /**< Lower Over Temperature limit */
+#define XADCPS_ATR_VBRAM_UPPER_ 8 /**< VRBAM Upper Alarm Reg, 7 Series */
+#define XADCPS_ATR_VCCPINT_UPPER 9 /**< VCCPINT Upper Alarm Reg, Zynq */
+#define XADCPS_ATR_VCCPAUX_UPPER 0xA /**< VCCPAUX Upper Alarm Reg, Zynq */
+#define XADCPS_ATR_VCCPDRO_UPPER 0xB /**< VCCPDRO Upper Alarm Reg, Zynq */
+#define XADCPS_ATR_VBRAM_LOWER 0xC /**< VRBAM Lower Alarm Reg, 7 Series */
+#define XADCPS_ATR_VCCPINT_LOWER 0xD /**< VCCPINT Lower Alarm Reg , Zynq */
+#define XADCPS_ATR_VCCPAUX_LOWER 0xE /**< VCCPAUX Lower Alarm Reg , Zynq */
+#define XADCPS_ATR_VCCPDRO_LOWER 0xF /**< VCCPDRO Lower Alarm Reg , Zynq */
+
+/*@}*/
+
+
+/**
+ * @name Averaging to be done for the channels.
+ * @{
+ */
+#define XADCPS_AVG_0_SAMPLES 0 /**< No Averaging */
+#define XADCPS_AVG_16_SAMPLES 1 /**< Average 16 samples */
+#define XADCPS_AVG_64_SAMPLES 2 /**< Average 64 samples */
+#define XADCPS_AVG_256_SAMPLES 3 /**< Average 256 samples */
+
+/*@}*/
+
+
+/**
+ * @name Channel Sequencer Modes of operation
+ * @{
+ */
+#define XADCPS_SEQ_MODE_SAFE 0 /**< Default Safe Mode */
+#define XADCPS_SEQ_MODE_ONEPASS 1 /**< Onepass through Sequencer */
+#define XADCPS_SEQ_MODE_CONTINPASS 2 /**< Continuous Cycling Sequencer */
+#define XADCPS_SEQ_MODE_SINGCHAN 3 /**< Single channel -No Sequencing */
+#define XADCPS_SEQ_MODE_SIMUL_SAMPLING 4 /**< Simultaneous sampling */
+#define XADCPS_SEQ_MODE_INDEPENDENT 8 /**< Independent mode */
+
+/*@}*/
+
+
+
+/**
+ * @name Power Down Modes
+ * @{
+ */
+#define XADCPS_PD_MODE_NONE 0 /**< No Power Down */
+#define XADCPS_PD_MODE_ADCB 1 /**< Power Down ADC B */
+#define XADCPS_PD_MODE_XADC 2 /**< Power Down ADC A and ADC B */
+/*@}*/
+
+/**************************** Type Definitions ******************************/
+
+/**
+ * This typedef contains configuration information for the XADC/ADC
+ * device.
+ */
+typedef struct {
+ u16 DeviceId; /**< Unique ID of device */
+ u32 BaseAddress; /**< Device base address */
+} XAdcPs_Config;
+
+
+/**
+ * The driver's instance data. The user is required to allocate a variable
+ * of this type for every XADC/ADC device in the system. A pointer to
+ * a variable of this type is then passed to the driver API functions.
+ */
+typedef struct {
+ XAdcPs_Config Config; /**< XAdcPs_Config of current device */
+ u32 IsReady; /**< Device is initialized and ready */
+
+} XAdcPs;
+
+/***************** Macros (Inline Functions) Definitions ********************/
+
+/****************************************************************************/
+/**
+*
+* This macro checks if the XADC device is in Event Sampling mode.
+*
+* @param InstancePtr is a pointer to the XAdcPs instance.
+*
+* @return
+* - TRUE if the device is in Event Sampling Mode.
+* - FALSE if the device is in Continuous Sampling Mode.
+*
+* @note C-Style signature:
+* int XAdcPs_IsEventSamplingMode(XAdcPs *InstancePtr);
+*
+*****************************************************************************/
+#define XAdcPs_IsEventSamplingModeSet(InstancePtr) \
+ (((XAdcPs_ReadInternalReg(InstancePtr, \
+ XADCPS_CFR0_OFFSET) & XADCPS_CFR0_EC_MASK) ? \
+ TRUE : FALSE))
+
+
+/****************************************************************************/
+/**
+*
+* This macro checks if the XADC device is in External Mux mode.
+*
+* @param InstancePtr is a pointer to the XAdcPs instance.
+*
+* @return
+* - TRUE if the device is in External Mux Mode.
+* - FALSE if the device is NOT in External Mux Mode.
+*
+* @note C-Style signature:
+* int XAdcPs_IsExternalMuxMode(XAdcPs *InstancePtr);
+*
+*****************************************************************************/
+#define XAdcPs_IsExternalMuxModeSet(InstancePtr) \
+ (((XAdcPs_ReadInternalReg(InstancePtr, \
+ XADCPS_CFR0_OFFSET) & XADCPS_CFR0_MUX_MASK) ? \
+ TRUE : FALSE))
+
+/****************************************************************************/
+/**
+*
+* This macro converts XADC Raw Data to Temperature(centigrades).
+*
+* @param AdcData is the Raw ADC Data from XADC.
+*
+* @return The Temperature in centigrades.
+*
+* @note C-Style signature:
+* float XAdcPs_RawToTemperature(u32 AdcData);
+*
+*****************************************************************************/
+#define XAdcPs_RawToTemperature(AdcData) \
+ ((((float)(AdcData)/65536.0f)/0.00198421639f ) - 273.15f)
+
+/****************************************************************************/
+/**
+*
+* This macro converts XADC/ADC Raw Data to Voltage(volts).
+*
+* @param AdcData is the XADC/ADC Raw Data.
+*
+* @return The Voltage in volts.
+*
+* @note C-Style signature:
+* float XAdcPs_RawToVoltage(u32 AdcData);
+*
+*****************************************************************************/
+#define XAdcPs_RawToVoltage(AdcData) \
+ ((((float)(AdcData))* (3.0f))/65536.0f)
+
+/****************************************************************************/
+/**
+*
+* This macro converts Temperature in centigrades to XADC/ADC Raw Data.
+*
+* @param Temperature is the Temperature in centigrades to be
+* converted to XADC/ADC Raw Data.
+*
+* @return The XADC/ADC Raw Data.
+*
+* @note C-Style signature:
+* int XAdcPs_TemperatureToRaw(float Temperature);
+*
+*****************************************************************************/
+#define XAdcPs_TemperatureToRaw(Temperature) \
+ ((int)(((Temperature) + 273.15f)*65536.0f*0.00198421639f))
+
+/****************************************************************************/
+/**
+*
+* This macro converts Voltage in Volts to XADC/ADC Raw Data.
+*
+* @param Voltage is the Voltage in volts to be converted to
+* XADC/ADC Raw Data.
+*
+* @return The XADC/ADC Raw Data.
+*
+* @note C-Style signature:
+* int XAdcPs_VoltageToRaw(float Voltage);
+*
+*****************************************************************************/
+#define XAdcPs_VoltageToRaw(Voltage) \
+ ((int)((Voltage)*65536.0f/3.0f))
+
+
+/****************************************************************************/
+/**
+*
+* This macro is used for writing to the XADC Registers using the
+* command FIFO.
+*
+* @param InstancePtr is a pointer to the XAdcPs instance.
+* @param Data is the value to be written to XADC register.
+*
+* @return None.
+*
+* @note C-Style signature:
+* void XAdcPs_WriteFifo(XAdcPs *InstancePtr, u32 Data);
+*
+*****************************************************************************/
+#define XAdcPs_WriteFifo(InstancePtr, Data) \
+ XAdcPs_WriteReg((InstancePtr)->Config.BaseAddress, \
+ XADCPS_CMDFIFO_OFFSET, Data);
+
+
+/****************************************************************************/
+/**
+*
+* This macro is used for reading from the XADC Registers using the
+* data FIFO.
+*
+* @param InstancePtr is a pointer to the XAdcPs instance.
+*
+* @return Data read from the FIFO
+*
+* @note C-Style signature:
+* u32 XAdcPs_ReadFifo(XAdcPs *InstancePtr);
+*
+*****************************************************************************/
+#define XAdcPs_ReadFifo(InstancePtr) \
+ XAdcPs_ReadReg((InstancePtr)->Config.BaseAddress, \
+ XADCPS_RDFIFO_OFFSET);
+
+
+/************************** Function Prototypes *****************************/
+
+
+
+/**
+ * Functions in xadcps_sinit.c
+ */
+XAdcPs_Config *XAdcPs_LookupConfig(u16 DeviceId);
+
+/**
+ * Functions in xadcps.c
+ */
+int XAdcPs_CfgInitialize(XAdcPs *InstancePtr,
+ XAdcPs_Config *ConfigPtr,
+ u32 EffectiveAddr);
+
+
+u32 XAdcPs_GetStatus(XAdcPs *InstancePtr);
+
+u32 XAdcPs_GetAlarmOutputStatus(XAdcPs *InstancePtr);
+
+void XAdcPs_StartAdcConversion(XAdcPs *InstancePtr);
+
+void XAdcPs_Reset(XAdcPs *InstancePtr);
+
+u16 XAdcPs_GetAdcData(XAdcPs *InstancePtr, u8 Channel);
+
+u16 XAdcPs_GetCalibCoefficient(XAdcPs *InstancePtr, u8 CoeffType);
+
+u16 XAdcPs_GetMinMaxMeasurement(XAdcPs *InstancePtr, u8 MeasurementType);
+
+void XAdcPs_SetAvg(XAdcPs *InstancePtr, u8 Average);
+u8 XAdcPs_GetAvg(XAdcPs *InstancePtr);
+
+int XAdcPs_SetSingleChParams(XAdcPs *InstancePtr,
+ u8 Channel,
+ int IncreaseAcqCycles,
+ int IsEventMode,
+ int IsDifferentialMode);
+
+
+void XAdcPs_SetAlarmEnables(XAdcPs *InstancePtr, u16 AlmEnableMask);
+u16 XAdcPs_GetAlarmEnables(XAdcPs *InstancePtr);
+
+void XAdcPs_SetCalibEnables(XAdcPs *InstancePtr, u16 Calibration);
+u16 XAdcPs_GetCalibEnables(XAdcPs *InstancePtr);
+
+void XAdcPs_SetSequencerMode(XAdcPs *InstancePtr, u8 SequencerMode);
+u8 XAdcPs_GetSequencerMode(XAdcPs *InstancePtr);
+
+void XAdcPs_SetAdcClkDivisor(XAdcPs *InstancePtr, u8 Divisor);
+u8 XAdcPs_GetAdcClkDivisor(XAdcPs *InstancePtr);
+
+int XAdcPs_SetSeqChEnables(XAdcPs *InstancePtr, u32 ChEnableMask);
+u32 XAdcPs_GetSeqChEnables(XAdcPs *InstancePtr);
+
+int XAdcPs_SetSeqAvgEnables(XAdcPs *InstancePtr, u32 AvgEnableChMask);
+u32 XAdcPs_GetSeqAvgEnables(XAdcPs *InstancePtr);
+
+int XAdcPs_SetSeqInputMode(XAdcPs *InstancePtr, u32 InputModeChMask);
+u32 XAdcPs_GetSeqInputMode(XAdcPs *InstancePtr);
+
+int XAdcPs_SetSeqAcqTime(XAdcPs *InstancePtr, u32 AcqCyclesChMask);
+u32 XAdcPs_GetSeqAcqTime(XAdcPs *InstancePtr);
+
+void XAdcPs_SetAlarmThreshold(XAdcPs *InstancePtr, u8 AlarmThrReg, u16 Value);
+u16 XAdcPs_GetAlarmThreshold(XAdcPs *InstancePtr, u8 AlarmThrReg);
+
+void XAdcPs_EnableUserOverTemp(XAdcPs *InstancePtr);
+void XAdcPs_DisableUserOverTemp(XAdcPs *InstancePtr);
+
+void XAdcPs_SetSequencerEvent(XAdcPs *InstancePtr, int IsEventMode);
+
+int XAdcPs_GetSamplingMode(XAdcPs *InstancePtr);
+
+void XAdcPs_SetMuxMode(XAdcPs *InstancePtr, int MuxMode, u8 Channel);
+
+void XAdcPs_SetPowerdownMode(XAdcPs *InstancePtr, u32 Mode);
+
+u32 XAdcPs_GetPowerdownMode(XAdcPs *InstancePtr);
+
+/**
+ * Functions in xadcps_selftest.c
+ */
+int XAdcPs_SelfTest(XAdcPs *InstancePtr);
+
+/**
+ * Functions in xadcps_intr.c
+ */
+void XAdcPs_IntrEnable(XAdcPs *InstancePtr, u32 Mask);
+void XAdcPs_IntrDisable(XAdcPs *InstancePtr, u32 Mask);
+u32 XAdcPs_IntrGetEnabled(XAdcPs *InstancePtr);
+
+u32 XAdcPs_IntrGetStatus(XAdcPs *InstancePtr);
+void XAdcPs_IntrClear(XAdcPs *InstancePtr, u32 Mask);
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* End of protection macro. */
+/** @} */
diff --git a/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/include/xadcps_hw.h b/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/include/xadcps_hw.h
new file mode 100644
index 0000000..717fc90
--- /dev/null
+++ b/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/include/xadcps_hw.h
@@ -0,0 +1,496 @@
+/******************************************************************************
+*
+* Copyright (C) 2011 - 2014 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+* THE SOFTWARE.
+*
+*
+*
+******************************************************************************/
+/****************************************************************************/
+/**
+*
+* @file xadcps_hw.h
+* @addtogroup xadcps_v2_3
+* @{
+*
+* This header file contains identifiers and basic driver functions (or
+* macros) that can be used to access the XADC device through the Device
+* Config Interface of the Zynq.
+*
+*
+* Refer to the device specification for more information about this driver.
+*
+* @note None.
+*
+*
+* <pre>
+*
+* MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ----- ----- -------- -----------------------------------------------------
+* 1.00a bss 12/22/11 First release based on the XPS/AXI xadc driver
+* 1.03a bss 11/01/13 Modified macros to use correct Register offsets
+* CR#749687
+*
+* </pre>
+*
+*****************************************************************************/
+#ifndef XADCPS_HW_H /* Prevent circular inclusions */
+#define XADCPS_HW_H /* by using protection macros */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/***************************** Include Files ********************************/
+
+#include "xil_types.h"
+#include "xil_assert.h"
+#include "xil_io.h"
+
+/************************** Constant Definitions ****************************/
+
+
+/**@name Register offsets of XADC in the Device Config
+ *
+ * The following constants provide access to each of the registers of the
+ * XADC device.
+ * @{
+ */
+
+#define XADCPS_CFG_OFFSET 0x00 /**< Configuration Register */
+#define XADCPS_INT_STS_OFFSET 0x04 /**< Interrupt Status Register */
+#define XADCPS_INT_MASK_OFFSET 0x08 /**< Interrupt Mask Register */
+#define XADCPS_MSTS_OFFSET 0x0C /**< Misc status register */
+#define XADCPS_CMDFIFO_OFFSET 0x10 /**< Command FIFO Register */
+#define XADCPS_RDFIFO_OFFSET 0x14 /**< Read FIFO Register */
+#define XADCPS_MCTL_OFFSET 0x18 /**< Misc control register */
+
+/* @} */
+
+
+
+
+
+/** @name XADC Config Register Bit definitions
+ * @{
+ */
+#define XADCPS_CFG_ENABLE_MASK 0x80000000 /**< Enable access from PS mask */
+#define XADCPS_CFG_CFIFOTH_MASK 0x00F00000 /**< Command FIFO Threshold mask */
+#define XADCPS_CFG_DFIFOTH_MASK 0x000F0000 /**< Data FIFO Threshold mask */
+#define XADCPS_CFG_WEDGE_MASK 0x00002000 /**< Write Edge Mask */
+#define XADCPS_CFG_REDGE_MASK 0x00001000 /**< Read Edge Mask */
+#define XADCPS_CFG_TCKRATE_MASK 0x00000300 /**< Clock freq control */
+#define XADCPS_CFG_IGAP_MASK 0x0000001F /**< Idle Gap between
+ * successive commands */
+/* @} */
+
+
+/** @name XADC Interrupt Status/Mask Register Bit definitions
+ *
+ * The definitions are same for the Interrupt Status Register and
+ * Interrupt Mask Register. They are defined only once.
+ * @{
+ */
+#define XADCPS_INTX_ALL_MASK 0x000003FF /**< Alarm Signals Mask */
+#define XADCPS_INTX_CFIFO_LTH_MASK 0x00000200 /**< CMD FIFO less than threshold */
+#define XADCPS_INTX_DFIFO_GTH_MASK 0x00000100 /**< Data FIFO greater than threshold */
+#define XADCPS_INTX_OT_MASK 0x00000080 /**< Over temperature Alarm Status */
+#define XADCPS_INTX_ALM_ALL_MASK 0x0000007F /**< Alarm Signals Mask */
+#define XADCPS_INTX_ALM6_MASK 0x00000040 /**< Alarm 6 Mask */
+#define XADCPS_INTX_ALM5_MASK 0x00000020 /**< Alarm 5 Mask */
+#define XADCPS_INTX_ALM4_MASK 0x00000010 /**< Alarm 4 Mask */
+#define XADCPS_INTX_ALM3_MASK 0x00000008 /**< Alarm 3 Mask */
+#define XADCPS_INTX_ALM2_MASK 0x00000004 /**< Alarm 2 Mask */
+#define XADCPS_INTX_ALM1_MASK 0x00000002 /**< Alarm 1 Mask */
+#define XADCPS_INTX_ALM0_MASK 0x00000001 /**< Alarm 0 Mask */
+
+/* @} */
+
+
+/** @name XADC Miscellaneous Register Bit definitions
+ * @{
+ */
+#define XADCPS_MSTS_CFIFO_LVL_MASK 0x000F0000 /**< Command FIFO Level mask */
+#define XADCPS_MSTS_DFIFO_LVL_MASK 0x0000F000 /**< Data FIFO Level Mask */
+#define XADCPS_MSTS_CFIFOF_MASK 0x00000800 /**< Command FIFO Full Mask */
+#define XADCPS_MSTS_CFIFOE_MASK 0x00000400 /**< Command FIFO Empty Mask */
+#define XADCPS_MSTS_DFIFOF_MASK 0x00000200 /**< Data FIFO Full Mask */
+#define XADCPS_MSTS_DFIFOE_MASK 0x00000100 /**< Data FIFO Empty Mask */
+#define XADCPS_MSTS_OT_MASK 0x00000080 /**< Over Temperature Mask */
+#define XADCPS_MSTS_ALM_MASK 0x0000007F /**< Alarms Mask */
+/* @} */
+
+
+/** @name XADC Miscellaneous Control Register Bit definitions
+ * @{
+ */
+#define XADCPS_MCTL_RESET_MASK 0x00000010 /**< Reset XADC */
+#define XADCPS_MCTL_FLUSH_MASK 0x00000001 /**< Flush the FIFOs */
+/* @} */
+
+
+/**@name Internal Register offsets of the XADC
+ *
+ * The following constants provide access to each of the internal registers of
+ * the XADC device.
+ * @{
+ */
+
+/*
+ * XADC Internal Channel Registers
+ */
+#define XADCPS_TEMP_OFFSET 0x00 /**< On-chip Temperature Reg */
+#define XADCPS_VCCINT_OFFSET 0x01 /**< On-chip VCCINT Data Reg */
+#define XADCPS_VCCAUX_OFFSET 0x02 /**< On-chip VCCAUX Data Reg */
+#define XADCPS_VPVN_OFFSET 0x03 /**< ADC out of VP/VN */
+#define XADCPS_VREFP_OFFSET 0x04 /**< On-chip VREFP Data Reg */
+#define XADCPS_VREFN_OFFSET 0x05 /**< On-chip VREFN Data Reg */
+#define XADCPS_VBRAM_OFFSET 0x06 /**< On-chip VBRAM , 7 Series */
+#define XADCPS_ADC_A_SUPPLY_CALIB_OFFSET 0x08 /**< ADC A Supply Offset Reg */
+#define XADCPS_ADC_A_OFFSET_CALIB_OFFSET 0x09 /**< ADC A Offset Data Reg */
+#define XADCPS_ADC_A_GAINERR_CALIB_OFFSET 0x0A /**< ADC A Gain Error Reg */
+#define XADCPS_VCCPINT_OFFSET 0x0D /**< On-chip VCCPINT Reg, Zynq */
+#define XADCPS_VCCPAUX_OFFSET 0x0E /**< On-chip VCCPAUX Reg, Zynq */
+#define XADCPS_VCCPDRO_OFFSET 0x0F /**< On-chip VCCPDRO Reg, Zynq */
+
+/*
+ * XADC External Channel Registers
+ */
+#define XADCPS_AUX00_OFFSET 0x10 /**< ADC out of VAUXP0/VAUXN0 */
+#define XADCPS_AUX01_OFFSET 0x11 /**< ADC out of VAUXP1/VAUXN1 */
+#define XADCPS_AUX02_OFFSET 0x12 /**< ADC out of VAUXP2/VAUXN2 */
+#define XADCPS_AUX03_OFFSET 0x13 /**< ADC out of VAUXP3/VAUXN3 */
+#define XADCPS_AUX04_OFFSET 0x14 /**< ADC out of VAUXP4/VAUXN4 */
+#define XADCPS_AUX05_OFFSET 0x15 /**< ADC out of VAUXP5/VAUXN5 */
+#define XADCPS_AUX06_OFFSET 0x16 /**< ADC out of VAUXP6/VAUXN6 */
+#define XADCPS_AUX07_OFFSET 0x17 /**< ADC out of VAUXP7/VAUXN7 */
+#define XADCPS_AUX08_OFFSET 0x18 /**< ADC out of VAUXP8/VAUXN8 */
+#define XADCPS_AUX09_OFFSET 0x19 /**< ADC out of VAUXP9/VAUXN9 */
+#define XADCPS_AUX10_OFFSET 0x1A /**< ADC out of VAUXP10/VAUXN10 */
+#define XADCPS_AUX11_OFFSET 0x1B /**< ADC out of VAUXP11/VAUXN11 */
+#define XADCPS_AUX12_OFFSET 0x1C /**< ADC out of VAUXP12/VAUXN12 */
+#define XADCPS_AUX13_OFFSET 0x1D /**< ADC out of VAUXP13/VAUXN13 */
+#define XADCPS_AUX14_OFFSET 0x1E /**< ADC out of VAUXP14/VAUXN14 */
+#define XADCPS_AUX15_OFFSET 0x1F /**< ADC out of VAUXP15/VAUXN15 */
+
+/*
+ * XADC Registers for Maximum/Minimum data captured for the
+ * on chip Temperature/VCCINT/VCCAUX data.
+ */
+#define XADCPS_MAX_TEMP_OFFSET 0x20 /**< Max Temperature Reg */
+#define XADCPS_MAX_VCCINT_OFFSET 0x21 /**< Max VCCINT Register */
+#define XADCPS_MAX_VCCAUX_OFFSET 0x22 /**< Max VCCAUX Register */
+#define XADCPS_MAX_VCCBRAM_OFFSET 0x23 /**< Max BRAM Register, 7 series */
+#define XADCPS_MIN_TEMP_OFFSET 0x24 /**< Min Temperature Reg */
+#define XADCPS_MIN_VCCINT_OFFSET 0x25 /**< Min VCCINT Register */
+#define XADCPS_MIN_VCCAUX_OFFSET 0x26 /**< Min VCCAUX Register */
+#define XADCPS_MIN_VCCBRAM_OFFSET 0x27 /**< Min BRAM Register, 7 series */
+#define XADCPS_MAX_VCCPINT_OFFSET 0x28 /**< Max VCCPINT Register, Zynq */
+#define XADCPS_MAX_VCCPAUX_OFFSET 0x29 /**< Max VCCPAUX Register, Zynq */
+#define XADCPS_MAX_VCCPDRO_OFFSET 0x2A /**< Max VCCPDRO Register, Zynq */
+#define XADCPS_MIN_VCCPINT_OFFSET 0x2C /**< Min VCCPINT Register, Zynq */
+#define XADCPS_MIN_VCCPAUX_OFFSET 0x2D /**< Min VCCPAUX Register, Zynq */
+#define XADCPS_MIN_VCCPDRO_OFFSET 0x2E /**< Min VCCPDRO Register,Zynq */
+ /* Undefined 0x2F to 0x3E */
+#define XADCPS_FLAG_OFFSET 0x3F /**< Flag Register */
+
+/*
+ * XADC Configuration Registers
+ */
+#define XADCPS_CFR0_OFFSET 0x40 /**< Configuration Register 0 */
+#define XADCPS_CFR1_OFFSET 0x41 /**< Configuration Register 1 */
+#define XADCPS_CFR2_OFFSET 0x42 /**< Configuration Register 2 */
+
+/* Test Registers 0x43 to 0x47 */
+
+/*
+ * XADC Sequence Registers
+ */
+#define XADCPS_SEQ00_OFFSET 0x48 /**< Seq Reg 00 Adc Channel Selection */
+#define XADCPS_SEQ01_OFFSET 0x49 /**< Seq Reg 01 Adc Channel Selection */
+#define XADCPS_SEQ02_OFFSET 0x4A /**< Seq Reg 02 Adc Average Enable */
+#define XADCPS_SEQ03_OFFSET 0x4B /**< Seq Reg 03 Adc Average Enable */
+#define XADCPS_SEQ04_OFFSET 0x4C /**< Seq Reg 04 Adc Input Mode Select */
+#define XADCPS_SEQ05_OFFSET 0x4D /**< Seq Reg 05 Adc Input Mode Select */
+#define XADCPS_SEQ06_OFFSET 0x4E /**< Seq Reg 06 Adc Acquisition Select */
+#define XADCPS_SEQ07_OFFSET 0x4F /**< Seq Reg 07 Adc Acquisition Select */
+
+/*
+ * XADC Alarm Threshold/Limit Registers (ATR)
+ */
+#define XADCPS_ATR_TEMP_UPPER_OFFSET 0x50 /**< Temp Upper Alarm Register */
+#define XADCPS_ATR_VCCINT_UPPER_OFFSET 0x51 /**< VCCINT Upper Alarm Reg */
+#define XADCPS_ATR_VCCAUX_UPPER_OFFSET 0x52 /**< VCCAUX Upper Alarm Reg */
+#define XADCPS_ATR_OT_UPPER_OFFSET 0x53 /**< Over Temp Upper Alarm Reg */
+#define XADCPS_ATR_TEMP_LOWER_OFFSET 0x54 /**< Temp Lower Alarm Register */
+#define XADCPS_ATR_VCCINT_LOWER_OFFSET 0x55 /**< VCCINT Lower Alarm Reg */
+#define XADCPS_ATR_VCCAUX_LOWER_OFFSET 0x56 /**< VCCAUX Lower Alarm Reg */
+#define XADCPS_ATR_OT_LOWER_OFFSET 0x57 /**< Over Temp Lower Alarm Reg */
+#define XADCPS_ATR_VBRAM_UPPER_OFFSET 0x58 /**< VBRAM Upper Alarm, 7 series */
+#define XADCPS_ATR_VCCPINT_UPPER_OFFSET 0x59 /**< VCCPINT Upper Alarm, Zynq */
+#define XADCPS_ATR_VCCPAUX_UPPER_OFFSET 0x5A /**< VCCPAUX Upper Alarm, Zynq */
+#define XADCPS_ATR_VCCPDRO_UPPER_OFFSET 0x5B /**< VCCPDRO Upper Alarm, Zynq */
+#define XADCPS_ATR_VBRAM_LOWER_OFFSET 0x5C /**< VRBAM Lower Alarm, 7 Series */
+#define XADCPS_ATR_VCCPINT_LOWER_OFFSET 0x5D /**< VCCPINT Lower Alarm, Zynq */
+#define XADCPS_ATR_VCCPAUX_LOWER_OFFSET 0x5E /**< VCCPAUX Lower Alarm, Zynq */
+#define XADCPS_ATR_VCCPDRO_LOWER_OFFSET 0x5F /**< VCCPDRO Lower Alarm, Zynq */
+
+/* Undefined 0x60 to 0x7F */
+
+/*@}*/
+
+
+
+/**
+ * @name Configuration Register 0 (CFR0) mask(s)
+ * @{
+ */
+#define XADCPS_CFR0_CAL_AVG_MASK 0x8000 /**< Averaging enable Mask */
+#define XADCPS_CFR0_AVG_VALID_MASK 0x3000 /**< Averaging bit Mask */
+#define XADCPS_CFR0_AVG1_MASK 0x0000 /**< No Averaging */
+#define XADCPS_CFR0_AVG16_MASK 0x1000 /**< Average 16 samples */
+#define XADCPS_CFR0_AVG64_MASK 0x2000 /**< Average 64 samples */
+#define XADCPS_CFR0_AVG256_MASK 0x3000 /**< Average 256 samples */
+#define XADCPS_CFR0_AVG_SHIFT 12 /**< Averaging bits shift */
+#define XADCPS_CFR0_MUX_MASK 0x0800 /**< External Mask Enable */
+#define XADCPS_CFR0_DU_MASK 0x0400 /**< Bipolar/Unipolar mode */
+#define XADCPS_CFR0_EC_MASK 0x0200 /**< Event driven/
+ * Continuous mode selection
+ */
+#define XADCPS_CFR0_ACQ_MASK 0x0100 /**< Add acquisition by 6 ADCCLK */
+#define XADCPS_CFR0_CHANNEL_MASK 0x001F /**< Channel number bit Mask */
+
+/*@}*/
+
+/**
+ * @name Configuration Register 1 (CFR1) mask(s)
+ * @{
+ */
+#define XADCPS_CFR1_SEQ_VALID_MASK 0xF000 /**< Sequence bit Mask */
+#define XADCPS_CFR1_SEQ_SAFEMODE_MASK 0x0000 /**< Default Safe Mode */
+#define XADCPS_CFR1_SEQ_ONEPASS_MASK 0x1000 /**< Onepass through Seq */
+#define XADCPS_CFR1_SEQ_CONTINPASS_MASK 0x2000 /**< Continuous Cycling Seq */
+#define XADCPS_CFR1_SEQ_SINGCHAN_MASK 0x3000 /**< Single channel - No Seq */
+#define XADCPS_CFR1_SEQ_SIMUL_SAMPLING_MASK 0x4000 /**< Simulataneous Sampling Mask */
+#define XADCPS_CFR1_SEQ_INDEPENDENT_MASK 0x8000 /**< Independent Mode */
+#define XADCPS_CFR1_SEQ_SHIFT 12 /**< Sequence bit shift */
+#define XADCPS_CFR1_ALM_VCCPDRO_MASK 0x0800 /**< Alm 6 - VCCPDRO, Zynq */
+#define XADCPS_CFR1_ALM_VCCPAUX_MASK 0x0400 /**< Alm 5 - VCCPAUX, Zynq */
+#define XADCPS_CFR1_ALM_VCCPINT_MASK 0x0200 /**< Alm 4 - VCCPINT, Zynq */
+#define XADCPS_CFR1_ALM_VBRAM_MASK 0x0100 /**< Alm 3 - VBRAM, 7 series */
+#define XADCPS_CFR1_CAL_VALID_MASK 0x00F0 /**< Valid Calibration Mask */
+#define XADCPS_CFR1_CAL_PS_GAIN_OFFSET_MASK 0x0080 /**< Calibration 3 -Power
+ Supply Gain/Offset
+ Enable */
+#define XADCPS_CFR1_CAL_PS_OFFSET_MASK 0x0040 /**< Calibration 2 -Power
+ Supply Offset Enable */
+#define XADCPS_CFR1_CAL_ADC_GAIN_OFFSET_MASK 0x0020 /**< Calibration 1 -ADC Gain
+ Offset Enable */
+#define XADCPS_CFR1_CAL_ADC_OFFSET_MASK 0x0010 /**< Calibration 0 -ADC Offset
+ Enable */
+#define XADCPS_CFR1_CAL_DISABLE_MASK 0x0000 /**< No Calibration */
+#define XADCPS_CFR1_ALM_ALL_MASK 0x0F0F /**< Mask for all alarms */
+#define XADCPS_CFR1_ALM_VCCAUX_MASK 0x0008 /**< Alarm 2 - VCCAUX Enable */
+#define XADCPS_CFR1_ALM_VCCINT_MASK 0x0004 /**< Alarm 1 - VCCINT Enable */
+#define XADCPS_CFR1_ALM_TEMP_MASK 0x0002 /**< Alarm 0 - Temperature */
+#define XADCPS_CFR1_OT_MASK 0x0001 /**< Over Temperature Enable */
+
+/*@}*/
+
+/**
+ * @name Configuration Register 2 (CFR2) mask(s)
+ * @{
+ */
+#define XADCPS_CFR2_CD_VALID_MASK 0xFF00 /**<Clock Divisor bit Mask */
+#define XADCPS_CFR2_CD_SHIFT 8 /**<Num of shift on division */
+#define XADCPS_CFR2_CD_MIN 8 /**<Minimum value of divisor */
+#define XADCPS_CFR2_CD_MAX 255 /**<Maximum value of divisor */
+
+#define XADCPS_CFR2_CD_MIN 8 /**<Minimum value of divisor */
+#define XADCPS_CFR2_PD_MASK 0x0030 /**<Power Down Mask */
+#define XADCPS_CFR2_PD_XADC_MASK 0x0030 /**<Power Down XADC Mask */
+#define XADCPS_CFR2_PD_ADC1_MASK 0x0020 /**<Power Down ADC1 Mask */
+#define XADCPS_CFR2_PD_SHIFT 4 /**<Power Down Shift */
+/*@}*/
+
+/**
+ * @name Sequence Register (SEQ) Bit Definitions
+ * @{
+ */
+#define XADCPS_SEQ_CH_CALIB 0x00000001 /**< ADC Calibration Channel */
+#define XADCPS_SEQ_CH_VCCPINT 0x00000020 /**< VCCPINT, Zynq Only */
+#define XADCPS_SEQ_CH_VCCPAUX 0x00000040 /**< VCCPAUX, Zynq Only */
+#define XADCPS_SEQ_CH_VCCPDRO 0x00000080 /**< VCCPDRO, Zynq Only */
+#define XADCPS_SEQ_CH_TEMP 0x00000100 /**< On Chip Temperature Channel */
+#define XADCPS_SEQ_CH_VCCINT 0x00000200 /**< VCCINT Channel */
+#define XADCPS_SEQ_CH_VCCAUX 0x00000400 /**< VCCAUX Channel */
+#define XADCPS_SEQ_CH_VPVN 0x00000800 /**< VP/VN analog inputs Channel */
+#define XADCPS_SEQ_CH_VREFP 0x00001000 /**< VREFP Channel */
+#define XADCPS_SEQ_CH_VREFN 0x00002000 /**< VREFN Channel */
+#define XADCPS_SEQ_CH_VBRAM 0x00004000 /**< VBRAM Channel, 7 series */
+#define XADCPS_SEQ_CH_AUX00 0x00010000 /**< 1st Aux Channel */
+#define XADCPS_SEQ_CH_AUX01 0x00020000 /**< 2nd Aux Channel */
+#define XADCPS_SEQ_CH_AUX02 0x00040000 /**< 3rd Aux Channel */
+#define XADCPS_SEQ_CH_AUX03 0x00080000 /**< 4th Aux Channel */
+#define XADCPS_SEQ_CH_AUX04 0x00100000 /**< 5th Aux Channel */
+#define XADCPS_SEQ_CH_AUX05 0x00200000 /**< 6th Aux Channel */
+#define XADCPS_SEQ_CH_AUX06 0x00400000 /**< 7th Aux Channel */
+#define XADCPS_SEQ_CH_AUX07 0x00800000 /**< 8th Aux Channel */
+#define XADCPS_SEQ_CH_AUX08 0x01000000 /**< 9th Aux Channel */
+#define XADCPS_SEQ_CH_AUX09 0x02000000 /**< 10th Aux Channel */
+#define XADCPS_SEQ_CH_AUX10 0x04000000 /**< 11th Aux Channel */
+#define XADCPS_SEQ_CH_AUX11 0x08000000 /**< 12th Aux Channel */
+#define XADCPS_SEQ_CH_AUX12 0x10000000 /**< 13th Aux Channel */
+#define XADCPS_SEQ_CH_AUX13 0x20000000 /**< 14th Aux Channel */
+#define XADCPS_SEQ_CH_AUX14 0x40000000 /**< 15th Aux Channel */
+#define XADCPS_SEQ_CH_AUX15 0x80000000 /**< 16th Aux Channel */
+
+#define XADCPS_SEQ00_CH_VALID_MASK 0x7FE1 /**< Mask for the valid channels */
+#define XADCPS_SEQ01_CH_VALID_MASK 0xFFFF /**< Mask for the valid channels */
+
+#define XADCPS_SEQ02_CH_VALID_MASK 0x7FE0 /**< Mask for the valid channels */
+#define XADCPS_SEQ03_CH_VALID_MASK 0xFFFF /**< Mask for the valid channels */
+
+#define XADCPS_SEQ04_CH_VALID_MASK 0x0800 /**< Mask for the valid channels */
+#define XADCPS_SEQ05_CH_VALID_MASK 0xFFFF /**< Mask for the valid channels */
+
+#define XADCPS_SEQ06_CH_VALID_MASK 0x0800 /**< Mask for the valid channels */
+#define XADCPS_SEQ07_CH_VALID_MASK 0xFFFF /**< Mask for the valid channels */
+
+
+#define XADCPS_SEQ_CH_AUX_SHIFT 16 /**< Shift for the Aux Channel */
+
+/*@}*/
+
+/**
+ * @name OT Upper Alarm Threshold Register Bit Definitions
+ * @{
+ */
+
+#define XADCPS_ATR_OT_UPPER_ENB_MASK 0x000F /**< Mask for OT enable */
+#define XADCPS_ATR_OT_UPPER_VAL_MASK 0xFFF0 /**< Mask for OT value */
+#define XADCPS_ATR_OT_UPPER_VAL_SHIFT 4 /**< Shift for OT value */
+#define XADCPS_ATR_OT_UPPER_ENB_VAL 0x0003 /**< Value for OT enable */
+#define XADCPS_ATR_OT_UPPER_VAL_MAX 0x0FFF /**< Max OT value */
+
+/*@}*/
+
+
+/**
+ * @name JTAG DRP Bit Definitions
+ * @{
+ */
+#define XADCPS_JTAG_DATA_MASK 0x0000FFFF /**< Mask for the Data */
+#define XADCPS_JTAG_ADDR_MASK 0x03FF0000 /**< Mask for the Addr */
+#define XADCPS_JTAG_ADDR_SHIFT 16 /**< Shift for the Addr */
+#define XADCPS_JTAG_CMD_MASK 0x3C000000 /**< Mask for the Cmd */
+#define XADCPS_JTAG_CMD_WRITE_MASK 0x08000000 /**< Mask for CMD Write */
+#define XADCPS_JTAG_CMD_READ_MASK 0x04000000 /**< Mask for CMD Read */
+#define XADCPS_JTAG_CMD_SHIFT 26 /**< Shift for the Cmd */
+
+/*@}*/
+
+/** @name Unlock Register Definitions
+ * @{
+ */
+ #define XADCPS_UNLK_OFFSET 0x034 /**< Unlock Register */
+ #define XADCPS_UNLK_VALUE 0x757BDF0D /**< Unlock Value */
+
+ /* @} */
+
+
+/**************************** Type Definitions *******************************/
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/*****************************************************************************/
+/**
+*
+* Read a register of the XADC device. This macro provides register
+* access to all registers using the register offsets defined above.
+*
+* @param BaseAddress contains the base address of the device.
+* @param RegOffset is the offset of the register to read.
+*
+* @return The contents of the register.
+*
+* @note C-style Signature:
+* u32 XAdcPs_ReadReg(u32 BaseAddress, u32 RegOffset);
+*
+******************************************************************************/
+#define XAdcPs_ReadReg(BaseAddress, RegOffset) \
+ (Xil_In32((BaseAddress) + (RegOffset)))
+
+/*****************************************************************************/
+/**
+*
+* Write a register of the XADC device. This macro provides
+* register access to all registers using the register offsets defined above.
+*
+* @param BaseAddress contains the base address of the device.
+* @param RegOffset is the offset of the register to write.
+* @param Data is the value to write to the register.
+*
+* @return None.
+*
+* @note C-style Signature:
+* void XAdcPs_WriteReg(u32 BaseAddress,
+* u32 RegOffset,u32 Data)
+*
+******************************************************************************/
+#define XAdcPs_WriteReg(BaseAddress, RegOffset, Data) \
+ (Xil_Out32((BaseAddress) + (RegOffset), (Data)))
+
+/************************** Function Prototypes ******************************/
+
+
+/*****************************************************************************/
+/**
+*
+* Formats the data to be written to the the XADC registers.
+*
+* @param RegOffset is the offset of the Register
+* @param Data is the data to be written to the Register if it is
+* a write.
+* @param ReadWrite specifies whether it is a Read or a Write.
+* Use 0 for Read, 1 for Write.
+*
+* @return None.
+*
+* @note C-style Signature:
+* void XAdcPs_FormatWriteData(u32 RegOffset,
+* u16 Data, int ReadWrite)
+*
+******************************************************************************/
+#define XAdcPs_FormatWriteData(RegOffset, Data, ReadWrite) \
+ ((ReadWrite ? XADCPS_JTAG_CMD_WRITE_MASK : XADCPS_JTAG_CMD_READ_MASK ) | \
+ ((RegOffset << XADCPS_JTAG_ADDR_SHIFT) & XADCPS_JTAG_ADDR_MASK) | \
+ (Data & XADCPS_JTAG_DATA_MASK))
+
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* End of protection macro. */
+/** @} */
diff --git a/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/include/xbasic_types.h b/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/include/xbasic_types.h
new file mode 100644
index 0000000..e9a0256
--- /dev/null
+++ b/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/include/xbasic_types.h
@@ -0,0 +1,125 @@
+/******************************************************************************
+*
+* Copyright (C) 2010 - 2019 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+* THE SOFTWARE.
+*
+*
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xbasic_types.h
+*
+*
+* @note Dummy File for backwards compatibility
+*
+
+*
+* <pre>
+* MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ----- ---- -------- -------------------------------------------------------
+* 1.00a adk 1/31/14 Added in bsp common folder for backward compatibility
+* 7.0 aru 01/21/19 Modified the typedef of u32,u16,u8
+* 7.0 aru 02/06/19 Included stdint.h and stddef.h
+* </pre>
+*
+******************************************************************************/
+
+#ifndef XBASIC_TYPES_H /* prevent circular inclusions */
+#define XBASIC_TYPES_H /* by using protection macros */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <stdint.h>
+#include <stddef.h>
+
+/** @name Legacy types
+ * Deprecated legacy types.
+ * @{
+ */
+typedef uint8_t Xuint8; /**< unsigned 8-bit */
+typedef char Xint8; /**< signed 8-bit */
+typedef uint16_t Xuint16; /**< unsigned 16-bit */
+typedef short Xint16; /**< signed 16-bit */
+typedef uint32_t Xuint32; /**< unsigned 32-bit */
+typedef long Xint32; /**< signed 32-bit */
+typedef float Xfloat32; /**< 32-bit floating point */
+typedef double Xfloat64; /**< 64-bit double precision FP */
+typedef unsigned long Xboolean; /**< boolean (XTRUE or XFALSE) */
+
+#if !defined __XUINT64__
+typedef struct
+{
+ Xuint32 Upper;
+ Xuint32 Lower;
+} Xuint64;
+#endif
+
+/** @name New types
+ * New simple types.
+ * @{
+ */
+#ifndef __KERNEL__
+#ifndef XIL_TYPES_H
+typedef Xuint32 u32;
+typedef Xuint16 u16;
+typedef Xuint8 u8;
+#endif
+#else
+#include <linux/types.h>
+#endif
+
+#ifndef TRUE
+# define TRUE 1U
+#endif
+
+#ifndef FALSE
+# define FALSE 0U
+#endif
+
+#ifndef NULL
+#define NULL 0U
+#endif
+
+/*
+ * Xilinx NULL, TRUE and FALSE legacy support. Deprecated.
+ * Please use NULL, TRUE and FALSE
+ */
+#define XNULL NULL
+#define XTRUE TRUE
+#define XFALSE FALSE
+
+/*
+ * This file is deprecated and users
+ * should use xil_types.h and xil_assert.h\n\r
+ */
+#warning The xbasics_type.h file is deprecated and users should use xil_types.h and xil_assert.
+#warning Please refer the Standalone BSP UG647 for further details
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* end of protection macro */
diff --git a/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/include/xbram.h b/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/include/xbram.h
new file mode 100644
index 0000000..0288074
--- /dev/null
+++ b/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/include/xbram.h
@@ -0,0 +1,221 @@
+/******************************************************************************
+*
+* Copyright (C) 2010 - 2019 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+* THE SOFTWARE.
+*
+*
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+* @file xbram.h
+* @addtogroup bram_v4_2
+* @{
+* @details
+*
+* If ECC is not enabled, this driver exists only to allow the tools to
+* create a memory test application and to populate xparameters.h with memory
+* range constants. In this case there is no source code.
+*
+* If ECC is enabled, this file contains the software API definition of the
+* Xilinx BRAM Interface Controller (XBram) device driver.
+*
+* The Xilinx BRAM controller is a soft IP core designed for Xilinx
+* FPGAs and contains the following general features:
+* - LMB v2.0 bus interfaces with byte enable support
+* - Used in conjunction with bram_block peripheral to provide fast BRAM
+* memory solution for MicroBlaze ILMB and DLMB ports
+* - Supports byte, half-word, and word transfers
+* - Supports optional BRAM error correction and detection.
+*
+* The driver provides interrupt management functions. Implementation of
+* interrupt handlers is left to the user. Refer to the provided interrupt
+* example in the examples directory for details.
+*
+* This driver is intended to be RTOS and processor independent. Any needs for
+* dynamic memory management, threads or thread mutual exclusion, virtual
+* memory, or cache control must be satisfied by the layer above this driver.
+*
+* <b>Initialization & Configuration</b>
+*
+* The XBram_Config structure is used by the driver to configure
+* itself. This configuration structure is typically created by the tool-chain
+* based on HW build properties.
+*
+* To support multiple runtime loading and initialization strategies employed
+* by various operating systems, the driver instance can be initialized as
+* follows:
+*
+* - XBram_CfgInitialize(InstancePtr, CfgPtr, EffectiveAddr) -
+* Uses a configuration structure provided by the caller. If running in a
+* system with address translation, the provided virtual memory base address
+* replaces the physical address present in the configuration structure.
+*
+* @note
+*
+* This API utilizes 32 bit I/O to the BRAM registers. With less
+* than 32 bits, the unused bits from registers are read as zero and written as
+* don't cares.
+*
+* <pre>
+* MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ----- ---- -------- -----------------------------------------------
+* 3.00a sa 05/11/10 Added ECC support
+* 3.01a sa 01/13/12 Changed Selftest API from
+* XBram_SelfTest(XBram *InstancePtr) to
+* XBram_SelfTest(XBram *InstancePtr, u8 IntMask) and
+* fixed a problem with interrupt generation for CR 639274
+* Modified Selftest example to return XST_SUCCESS when
+* ECC is not enabled and return XST_FAILURE when ECC is
+* enabled and Control Base Address is zero (CR 636581)
+* Modified Selftest to use correct CorrectableCounterBits
+* for CR 635655
+* Updated to check CorrectableFailingDataRegs in the case
+* of LMB BRAM.
+* Added CorrectableFailingDataRegs and
+* UncorrectableFailingDataRegs to the config structure to
+* distinguish between AXI BRAM and LMB BRAM.
+* These registers are not present in the current version of
+* the AXI BRAM Controller.
+* 3.02a sa 04/16/12 Added test of byte and halfword read-modify-write
+* 3.02a sa 04/16/12 Modified driver tcl to sort the address parameters
+* to support both xps and vivado designs.
+* 3.02a adk 24/4/13 Modified the tcl file to avoid warnings
+* when ecc is disabled cr:705002.
+* 3.03a bss 05/22/13 Added Xil_DCacheFlushRange in xbram_selftest.c to
+* flush the Cache after writing to BRAM in InjectErrors
+* API(CR #719011)
+* 4.0 adk 19/12/13 Updated as per the New Tcl API's
+* 4.1 sk 11/10/15 Used UINTPTR instead of u32 for Baseaddress CR# 867425.
+* Changed the prototype of XBram_CfgInitialize API.
+* ms 01/23/17 Modified xil_printf statement in main function for all
+* examples to ensure that "Successfully ran" and "Failed"
+* strings are available in all examples. This is a fix
+* for CR-965028.
+* ms 03/17/17 Added readme.txt file in examples folder for doxygen
+* generation.
+* 4.2 ms 04/18/17 Modified tcl file to add suffix U for all macro
+* definitions of bram in xparameters.h
+* ms 08/07/17 Fixed compilation warnings in xbram_sinit.c
+* 4.3 aru 03/23/19 Used UINTPTR instead of u32 for MemBaseAddress and
+* MemHighAddress.
+* </pre>
+*****************************************************************************/
+#ifndef XBRAM_H /* prevent circular inclusions */
+#define XBRAM_H /* by using protection macros */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/***************************** Include Files ********************************/
+
+#include "xil_types.h"
+#include "xil_assert.h"
+#include "xstatus.h"
+#include "xbram_hw.h"
+
+/************************** Constant Definitions ****************************/
+
+
+/**************************** Type Definitions ******************************/
+
+/**
+ * This typedef contains configuration information for the device.
+ */
+typedef struct {
+ u16 DeviceId; /**< Unique ID of device */
+ u32 DataWidth; /**< BRAM data width */
+ int EccPresent; /**< Is ECC supported in H/W */
+ int FaultInjectionPresent; /**< Is Fault Injection
+ * supported in H/W */
+ int CorrectableFailingRegisters; /**< Is Correctable Failing Registers
+ * supported in H/W */
+ int CorrectableFailingDataRegs; /**< Is Correctable Failing Data
+ * Registers supported in H/W */
+ int UncorrectableFailingRegisters; /**< Is Un-correctable Failing
+ * Registers supported in H/W */
+ int UncorrectableFailingDataRegs; /**< Is Un-correctable Failing Data
+ * Registers supported in H/W */
+ int EccStatusInterruptPresent; /**< Are ECC status and interrupts
+ * supported in H/W */
+ int CorrectableCounterBits; /**< Number of bits in the
+ * Correctable Error Counter */
+ int EccOnOffRegister; /**< Is ECC on/off register supported
+ * in h/w */
+ int EccOnOffResetValue; /**< Reset value of the ECC on/off
+ * register in h/w */
+ int WriteAccess; /**< Is write access enabled in
+ * h/w */
+ UINTPTR MemBaseAddress; /**< Device memory base address */
+ UINTPTR MemHighAddress; /**< Device memory high address */
+ UINTPTR CtrlBaseAddress; /**< Device register base address.*/
+ UINTPTR CtrlHighAddress; /**< Device register base address.*/
+} XBram_Config;
+
+/**
+ * The XBram driver instance data. The user is required to
+ * allocate a variable of this type for every BRAM device in the
+ * system. A pointer to a variable of this type is then passed to the driver
+ * API functions.
+ */
+typedef struct {
+ XBram_Config Config; /* BRAM config structure */
+ u32 IsReady; /* Device is initialized and ready */
+} XBram;
+
+/***************** Macros (Inline Functions) Definitions ********************/
+
+
+/************************** Function Prototypes *****************************/
+
+/*
+ * Functions in xbram_sinit.c
+ */
+XBram_Config *XBram_LookupConfig(u16 DeviceId);
+
+/*
+ * Functions implemented in xbram.c
+ */
+int XBram_CfgInitialize(XBram *InstancePtr, XBram_Config *Config,
+ UINTPTR EffectiveAddr);
+
+/*
+ * Functions implemented in xbram_selftest.c
+ */
+int XBram_SelfTest(XBram *InstancePtr, u8 IntMask);
+
+/*
+ * Functions implemented in xbram_intr.c
+ */
+void XBram_InterruptEnable(XBram *InstancePtr, u32 Mask);
+void XBram_InterruptDisable(XBram *InstancePtr, u32 Mask);
+void XBram_InterruptClear(XBram *InstancePtr, u32 Mask);
+u32 XBram_InterruptGetEnabled(XBram *InstancePtr);
+u32 XBram_InterruptGetStatus(XBram *InstancePtr);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* end of protection macro */
+/** @} */
diff --git a/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/include/xbram_hw.h b/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/include/xbram_hw.h
new file mode 100644
index 0000000..be3fbc2
--- /dev/null
+++ b/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/include/xbram_hw.h
@@ -0,0 +1,403 @@
+/******************************************************************************
+*
+* Copyright (C) 2011 - 2015 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+* THE SOFTWARE.
+*
+*
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xbram_hw.h
+* @addtogroup bram_v4_2
+* @{
+*
+* This header file contains identifiers and driver functions (or
+* macros) that can be used to access the device. The user should refer to the
+* hardware device specification for more details of the device operation.
+*
+* <pre>
+* MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ----- ---- -------- -----------------------------------------------
+* 1.00a sa 24/11/10 First release
+* </pre>
+*
+******************************************************************************/
+#ifndef XBRAM_HW_H /* prevent circular inclusions */
+#define XBRAM_HW_H /* by using protection macros */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/***************************** Include Files *********************************/
+
+#include "xil_types.h"
+#include "xil_assert.h"
+#include "xil_io.h"
+
+/************************** Constant Definitions *****************************/
+
+/** @name Registers
+ *
+ * Register offsets for this device.
+ * @{
+ */
+
+#define XBRAM_ECC_STATUS_OFFSET 0x0 /**< ECC status Register */
+#define XBRAM_ECC_EN_IRQ_OFFSET 0x4 /**< ECC interrupt enable Register */
+#define XBRAM_ECC_ON_OFF_OFFSET 0x8 /**< ECC on/off register */
+#define XBRAM_CE_CNT_OFFSET 0xC /**< Correctable error counter Register */
+
+#define XBRAM_CE_FFD_0_OFFSET 0x100 /**< Correctable error first failing
+ * data Register, 31-0 */
+#define XBRAM_CE_FFD_1_OFFSET 0x104 /**< Correctable error first failing
+ * data Register, 63-32 */
+#define XBRAM_CE_FFD_2_OFFSET 0x108 /**< Correctable error first failing
+ * data Register, 95-64 */
+#define XBRAM_CE_FFD_3_OFFSET 0x10C /**< Correctable error first failing
+ * data Register, 127-96 */
+#define XBRAM_CE_FFD_4_OFFSET 0x110 /**< Correctable error first failing
+ * data Register, 159-128 */
+#define XBRAM_CE_FFD_5_OFFSET 0x114 /**< Correctable error first failing
+ * data Register, 191-160 */
+#define XBRAM_CE_FFD_6_OFFSET 0x118 /**< Correctable error first failing
+ * data Register, 223-192 */
+#define XBRAM_CE_FFD_7_OFFSET 0x11C /**< Correctable error first failing
+ * data Register, 255-224 */
+#define XBRAM_CE_FFD_8_OFFSET 0x120 /**< Correctable error first failing
+ * data Register, 287-256 */
+#define XBRAM_CE_FFD_9_OFFSET 0x124 /**< Correctable error first failing
+ * data Register, 319-288 */
+#define XBRAM_CE_FFD_10_OFFSET 0x128 /**< Correctable error first failing
+ * data Register, 351-320 */
+#define XBRAM_CE_FFD_11_OFFSET 0x12C /**< Correctable error first failing
+ * data Register, 383-352 */
+#define XBRAM_CE_FFD_12_OFFSET 0x130 /**< Correctable error first failing
+ * data Register, 415-384 */
+#define XBRAM_CE_FFD_13_OFFSET 0x134 /**< Correctable error first failing
+ * data Register, 447-416 */
+#define XBRAM_CE_FFD_14_OFFSET 0x138 /**< Correctable error first failing
+ * data Register, 479-448 */
+#define XBRAM_CE_FFD_15_OFFSET 0x13C /**< Correctable error first failing
+ * data Register, 511-480 */
+#define XBRAM_CE_FFD_16_OFFSET 0x140 /**< Correctable error first failing
+ * data Register, 543-512 */
+#define XBRAM_CE_FFD_17_OFFSET 0x144 /**< Correctable error first failing
+ * data Register, 575-544 */
+#define XBRAM_CE_FFD_18_OFFSET 0x148 /**< Correctable error first failing
+ * data Register, 607-576 */
+#define XBRAM_CE_FFD_19_OFFSET 0x14C /**< Correctable error first failing
+ * data Register, 639-608 */
+#define XBRAM_CE_FFD_20_OFFSET 0x150 /**< Correctable error first failing
+ * data Register, 671-640 */
+#define XBRAM_CE_FFD_21_OFFSET 0x154 /**< Correctable error first failing
+ * data Register, 703-672 */
+#define XBRAM_CE_FFD_22_OFFSET 0x158 /**< Correctable error first failing
+ * data Register, 735-704 */
+#define XBRAM_CE_FFD_23_OFFSET 0x15C /**< Correctable error first failing
+ * data Register, 767-736 */
+#define XBRAM_CE_FFD_24_OFFSET 0x160 /**< Correctable error first failing
+ * data Register, 799-768 */
+#define XBRAM_CE_FFD_25_OFFSET 0x164 /**< Correctable error first failing
+ * data Register, 831-800 */
+#define XBRAM_CE_FFD_26_OFFSET 0x168 /**< Correctable error first failing
+ * data Register, 863-832 */
+#define XBRAM_CE_FFD_27_OFFSET 0x16C /**< Correctable error first failing
+ * data Register, 895-864 */
+#define XBRAM_CE_FFD_28_OFFSET 0x170 /**< Correctable error first failing
+ * data Register, 927-896 */
+#define XBRAM_CE_FFD_29_OFFSET 0x174 /**< Correctable error first failing
+ * data Register, 959-928 */
+#define XBRAM_CE_FFD_30_OFFSET 0x178 /**< Correctable error first failing
+ * data Register, 991-960 */
+#define XBRAM_CE_FFD_31_OFFSET 0x17C /**< Correctable error first failing
+ * data Register, 1023-992 */
+
+#define XBRAM_CE_FFE_0_OFFSET 0x180 /**< Correctable error first failing
+ * ECC Register, 31-0 */
+#define XBRAM_CE_FFE_1_OFFSET 0x184 /**< Correctable error first failing
+ * ECC Register, 63-32 */
+#define XBRAM_CE_FFE_2_OFFSET 0x188 /**< Correctable error first failing
+ * ECC Register, 95-64 */
+#define XBRAM_CE_FFE_3_OFFSET 0x18C /**< Correctable error first failing
+ * ECC Register, 127-96 */
+#define XBRAM_CE_FFE_4_OFFSET 0x190 /**< Correctable error first failing
+ * ECC Register, 159-128 */
+#define XBRAM_CE_FFE_5_OFFSET 0x194 /**< Correctable error first failing
+ * ECC Register, 191-160 */
+#define XBRAM_CE_FFE_6_OFFSET 0x198 /**< Correctable error first failing
+ * ECC Register, 223-192 */
+#define XBRAM_CE_FFE_7_OFFSET 0x19C /**< Correctable error first failing
+ * ECC Register, 255-224 */
+
+#define XBRAM_CE_FFA_0_OFFSET 0x1C0 /**< Correctable error first failing
+ * address Register 31-0 */
+#define XBRAM_CE_FFA_1_OFFSET 0x1C4 /**< Correctable error first failing
+ * address Register 63-32 */
+
+#define XBRAM_UE_FFD_0_OFFSET 0x200 /**< Uncorrectable error first failing
+ * data Register, 31-0 */
+#define XBRAM_UE_FFD_1_OFFSET 0x204 /**< Uncorrectable error first failing
+ * data Register, 63-32 */
+#define XBRAM_UE_FFD_2_OFFSET 0x208 /**< Uncorrectable error first failing
+ * data Register, 95-64 */
+#define XBRAM_UE_FFD_3_OFFSET 0x20C /**< Uncorrectable error first failing
+ * data Register, 127-96 */
+#define XBRAM_UE_FFD_4_OFFSET 0x210 /**< Uncorrectable error first failing
+ * data Register, 159-128 */
+#define XBRAM_UE_FFD_5_OFFSET 0x214 /**< Uncorrectable error first failing
+ * data Register, 191-160 */
+#define XBRAM_UE_FFD_6_OFFSET 0x218 /**< Uncorrectable error first failing
+ * data Register, 223-192 */
+#define XBRAM_UE_FFD_7_OFFSET 0x21C /**< Uncorrectable error first failing
+ * data Register, 255-224 */
+#define XBRAM_UE_FFD_8_OFFSET 0x220 /**< Uncorrectable error first failing
+ * data Register, 287-256 */
+#define XBRAM_UE_FFD_9_OFFSET 0x224 /**< Uncorrectable error first failing
+ * data Register, 319-288 */
+#define XBRAM_UE_FFD_10_OFFSET 0x228 /**< Uncorrectable error first failing
+ * data Register, 351-320 */
+#define XBRAM_UE_FFD_11_OFFSET 0x22C /**< Uncorrectable error first failing
+ * data Register, 383-352 */
+#define XBRAM_UE_FFD_12_OFFSET 0x230 /**< Uncorrectable error first failing
+ * data Register, 415-384 */
+#define XBRAM_UE_FFD_13_OFFSET 0x234 /**< Uncorrectable error first failing
+ * data Register, 447-416 */
+#define XBRAM_UE_FFD_14_OFFSET 0x238 /**< Uncorrectable error first failing
+ * data Register, 479-448 */
+#define XBRAM_UE_FFD_15_OFFSET 0x23C /**< Uncorrectable error first failing
+ * data Register, 511-480 */
+#define XBRAM_UE_FFD_16_OFFSET 0x240 /**< Uncorrectable error first failing
+ * data Register, 543-512 */
+#define XBRAM_UE_FFD_17_OFFSET 0x244 /**< Uncorrectable error first failing
+ * data Register, 575-544 */
+#define XBRAM_UE_FFD_18_OFFSET 0x248 /**< Uncorrectable error first failing
+ * data Register, 607-576 */
+#define XBRAM_UE_FFD_19_OFFSET 0x24C /**< Uncorrectable error first failing
+ * data Register, 639-608 */
+#define XBRAM_UE_FFD_20_OFFSET 0x250 /**< Uncorrectable error first failing
+ * data Register, 671-640 */
+#define XBRAM_UE_FFD_21_OFFSET 0x254 /**< Uncorrectable error first failing
+ * data Register, 703-672 */
+#define XBRAM_UE_FFD_22_OFFSET 0x258 /**< Uncorrectable error first failing
+ * data Register, 735-704 */
+#define XBRAM_UE_FFD_23_OFFSET 0x25C /**< Uncorrectable error first failing
+ * data Register, 767-736 */
+#define XBRAM_UE_FFD_24_OFFSET 0x260 /**< Uncorrectable error first failing
+ * data Register, 799-768 */
+#define XBRAM_UE_FFD_25_OFFSET 0x264 /**< Uncorrectable error first failing
+ * data Register, 831-800 */
+#define XBRAM_UE_FFD_26_OFFSET 0x268 /**< Uncorrectable error first failing
+ * data Register, 863-832 */
+#define XBRAM_UE_FFD_27_OFFSET 0x26C /**< Uncorrectable error first failing
+ * data Register, 895-864 */
+#define XBRAM_UE_FFD_28_OFFSET 0x270 /**< Uncorrectable error first failing
+ * data Register, 927-896 */
+#define XBRAM_UE_FFD_29_OFFSET 0x274 /**< Uncorrectable error first failing
+ * data Register, 959-928 */
+#define XBRAM_UE_FFD_30_OFFSET 0x278 /**< Uncorrectable error first failing
+ * data Register, 991-960 */
+#define XBRAM_UE_FFD_31_OFFSET 0x27C /**< Uncorrectable error first failing
+ * data Register, 1023-992 */
+
+#define XBRAM_UE_FFE_0_OFFSET 0x280 /**< Uncorrectable error first failing
+ * ECC Register, 31-0 */
+#define XBRAM_UE_FFE_1_OFFSET 0x284 /**< Uncorrectable error first failing
+ * ECC Register, 63-32 */
+#define XBRAM_UE_FFE_2_OFFSET 0x288 /**< Uncorrectable error first failing
+ * ECC Register, 95-64 */
+#define XBRAM_UE_FFE_3_OFFSET 0x28C /**< Uncorrectable error first failing
+ * ECC Register, 127-96 */
+#define XBRAM_UE_FFE_4_OFFSET 0x290 /**< Uncorrectable error first failing
+ * ECC Register, 159-128 */
+#define XBRAM_UE_FFE_5_OFFSET 0x294 /**< Uncorrectable error first failing
+ * ECC Register, 191-160 */
+#define XBRAM_UE_FFE_6_OFFSET 0x298 /**< Uncorrectable error first failing
+ * ECC Register, 223-192 */
+#define XBRAM_UE_FFE_7_OFFSET 0x29C /**< Uncorrectable error first failing
+ * ECC Register, 255-224 */
+
+#define XBRAM_UE_FFA_0_OFFSET 0x2C0 /**< Uncorrectable error first failing
+ * address Register 31-0 */
+#define XBRAM_UE_FFA_1_OFFSET 0x2C4 /**< Uncorrectable error first failing
+ * address Register 63-32 */
+
+#define XBRAM_FI_D_0_OFFSET 0x300 /**< Fault injection Data Register,
+ * 31-0 */
+#define XBRAM_FI_D_1_OFFSET 0x304 /**< Fault injection Data Register,
+ * 63-32 */
+#define XBRAM_FI_D_2_OFFSET 0x308 /**< Fault injection Data Register,
+ * 95-64 */
+#define XBRAM_FI_D_3_OFFSET 0x30C /**< Fault injection Data Register,
+ * 127-96 */
+#define XBRAM_FI_D_4_OFFSET 0x310 /**< Fault injection Data Register,
+ * 159-128 */
+#define XBRAM_FI_D_5_OFFSET 0x314 /**< Fault injection Data Register,
+ * 191-160 */
+#define XBRAM_FI_D_6_OFFSET 0x318 /**< Fault injection Data Register,
+ * 223-192 */
+#define XBRAM_FI_D_7_OFFSET 0x31C /**< Fault injection Data Register,
+ * 255-224 */
+#define XBRAM_FI_D_8_OFFSET 0x320 /**< Fault injection Data Register,
+ * 287-256 */
+#define XBRAM_FI_D_9_OFFSET 0x324 /**< Fault injection Data Register,
+ * 319-288 */
+#define XBRAM_FI_D_10_OFFSET 0x328 /**< Fault injection Data Register,
+ * 351-320 */
+#define XBRAM_FI_D_11_OFFSET 0x32C /**< Fault injection Data Register,
+ * 383-352 */
+#define XBRAM_FI_D_12_OFFSET 0x330 /**< Fault injection Data Register,
+ * 415-384 */
+#define XBRAM_FI_D_13_OFFSET 0x334 /**< Fault injection Data Register,
+ * 447-416 */
+#define XBRAM_FI_D_14_OFFSET 0x338 /**< Fault injection Data Register,
+ * 479-448 */
+#define XBRAM_FI_D_15_OFFSET 0x33C /**< Fault injection Data Register,
+ * 511-480 */
+#define XBRAM_FI_D_16_OFFSET 0x340 /**< Fault injection Data Register,
+ * 543-512 */
+#define XBRAM_FI_D_17_OFFSET 0x344 /**< Fault injection Data Register,
+ * 575-544 */
+#define XBRAM_FI_D_18_OFFSET 0x348 /**< Fault injection Data Register,
+ * 607-576 */
+#define XBRAM_FI_D_19_OFFSET 0x34C /**< Fault injection Data Register,
+ * 639-608 */
+#define XBRAM_FI_D_20_OFFSET 0x350 /**< Fault injection Data Register,
+ * 671-640 */
+#define XBRAM_FI_D_21_OFFSET 0x354 /**< Fault injection Data Register,
+ * 703-672 */
+#define XBRAM_FI_D_22_OFFSET 0x358 /**< Fault injection Data Register,
+ * 735-704 */
+#define XBRAM_FI_D_23_OFFSET 0x35C /**< Fault injection Data Register,
+ * 767-736 */
+#define XBRAM_FI_D_24_OFFSET 0x360 /**< Fault injection Data Register,
+ * 799-768 */
+#define XBRAM_FI_D_25_OFFSET 0x364 /**< Fault injection Data Register,
+ * 831-800 */
+#define XBRAM_FI_D_26_OFFSET 0x368 /**< Fault injection Data Register,
+ * 863-832 */
+#define XBRAM_FI_D_27_OFFSET 0x36C /**< Fault injection Data Register,
+ * 895-864 */
+#define XBRAM_FI_D_28_OFFSET 0x370 /**< Fault injection Data Register,
+ * 927-896 */
+#define XBRAM_FI_D_29_OFFSET 0x374 /**< Fault injection Data Register,
+ * 959-928 */
+#define XBRAM_FI_D_30_OFFSET 0x378 /**< Fault injection Data Register,
+ * 991-960 */
+#define XBRAM_FI_D_31_OFFSET 0x37C /**< Fault injection Data Register,
+ * 1023-992 */
+
+#define XBRAM_FI_ECC_0_OFFSET 0x380 /**< Fault injection ECC Register,
+ * 31-0 */
+#define XBRAM_FI_ECC_1_OFFSET 0x384 /**< Fault injection ECC Register,
+ * 63-32 */
+#define XBRAM_FI_ECC_2_OFFSET 0x388 /**< Fault injection ECC Register,
+ * 95-64 */
+#define XBRAM_FI_ECC_3_OFFSET 0x38C /**< Fault injection ECC Register,
+ * 127-96 */
+#define XBRAM_FI_ECC_4_OFFSET 0x390 /**< Fault injection ECC Register,
+ * 159-128 */
+#define XBRAM_FI_ECC_5_OFFSET 0x394 /**< Fault injection ECC Register,
+ * 191-160 */
+#define XBRAM_FI_ECC_6_OFFSET 0x398 /**< Fault injection ECC Register,
+ * 223-192 */
+#define XBRAM_FI_ECC_7_OFFSET 0x39C /**< Fault injection ECC Register,
+ * 255-224 */
+
+
+/* @} */
+
+/** @name Interrupt Status and Enable Register bitmaps and masks
+ *
+ * Bit definitions for the ECC status register and ECC interrupt enable register.
+ * @{
+ */
+#define XBRAM_IR_CE_MASK 0x2 /**< Mask for the correctable error */
+#define XBRAM_IR_UE_MASK 0x1 /**< Mask for the uncorrectable error */
+#define XBRAM_IR_ALL_MASK 0x3 /**< Mask of all bits */
+/*@}*/
+
+
+/**************************** Type Definitions *******************************/
+
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+#define XBram_In32 Xil_In32
+#define XBram_Out32 Xil_Out32
+
+#define XBram_In16 Xil_In16
+#define XBram_Out16 Xil_Out16
+
+#define XBram_In8 Xil_In8
+#define XBram_Out8 Xil_Out8
+
+
+/****************************************************************************/
+/**
+*
+* Write a value to a BRAM register. A 32 bit write is performed.
+*
+* @param BaseAddress is the base address of the BRAM device register.
+* @param RegOffset is the register offset from the base to write to.
+* @param Data is the data written to the register.
+*
+* @return None.
+*
+* @note C-style signature:
+* void XBram_WriteReg(u32 BaseAddress, u32 RegOffset, u32 Data)
+*
+****************************************************************************/
+#define XBram_WriteReg(BaseAddress, RegOffset, Data) \
+ XBram_Out32((BaseAddress) + (RegOffset), (u32)(Data))
+
+/****************************************************************************/
+/**
+*
+* Read a value from a BRAM register. A 32 bit read is performed.
+*
+* @param BaseAddress is the base address of the BRAM device registers.
+* @param RegOffset is the register offset from the base to read from.
+*
+* @return Data read from the register.
+*
+* @note C-style signature:
+* u32 XBram_ReadReg(u32 BaseAddress, u32 RegOffset)
+*
+****************************************************************************/
+#define XBram_ReadReg(BaseAddress, RegOffset) \
+ XBram_In32((BaseAddress) + (RegOffset))
+
+/************************** Function Prototypes ******************************/
+
+/************************** Variable Definitions *****************************/
+
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* end of protection macro */
+/** @} */
diff --git a/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/include/xcoresightpsdcc.h b/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/include/xcoresightpsdcc.h
new file mode 100644
index 0000000..3e5d80e
--- /dev/null
+++ b/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/include/xcoresightpsdcc.h
@@ -0,0 +1,72 @@
+/******************************************************************************
+*
+* Copyright (C) 2015 - 2019 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+* THE SOFTWARE.
+*
+*
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xcoresightpsdcc.h
+* @addtogroup coresightps_dcc_v1_6
+* @{
+* @details
+*
+* CoreSight driver component.
+*
+* The coresight is a part of debug communication channel (DCC) group. Jtag UART
+* for ARM uses DCC. Each ARM core has its own DCC, so one need to select an
+* ARM target in XSDB console before running the jtag terminal command. Using the
+* coresight driver component, the output stream can be directed to a log file.
+*
+* @note None.
+*
+*
+* <pre>
+* MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ----- ----- -------- -----------------------------------------------
+* 1.00 kvn 02/14/15 First release
+* 1.1 kvn 06/12/15 Add support for Zynq Ultrascale+ MP.
+* kvn 08/18/15 Modified Makefile according to compiler changes.
+* 1.3 asa 07/01/16 Made changes to ensure that the file does not compile
+* for MB BSPs. Instead it throws up a warning. This
+* fixes the CR#953056.
+* 1.5 sne 01/19/19 Fixed MISRA-C Violations CR#1025101.
+*
+* </pre>
+*
+******************************************************************************/
+
+/***************************** Include Files *********************************/
+#ifndef XCORESIGHTPSDCC_H /* prevent circular inclusions */
+#define XCORESIGHTPSDCC_H /* by using protection macros */
+#ifndef __MICROBLAZE__
+#include <xil_types.h>
+
+void XCoresightPs_DccSendByte(u32 BaseAddress, u8 Data);
+
+u8 XCoresightPs_DccRecvByte(u32 BaseAddress);
+#endif
+#endif
+/** @} */
diff --git a/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/include/xcpu_cortexa9.h b/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/include/xcpu_cortexa9.h
new file mode 100644
index 0000000..4f12056
--- /dev/null
+++ b/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/include/xcpu_cortexa9.h
@@ -0,0 +1,45 @@
+/******************************************************************************
+*
+* Copyright (C) 2011 - 2018 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+* THE SOFTWARE.
+*
+*
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xcpu_cortexa9.h
+* @addtogroup cpu_cortexa9_v2_7
+* @{
+* @details
+*
+* dummy file
+* MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ----- ---- -------- ---------------------------------------------------------
+* 2.5 ms 04/18/17 Modified tcl file to add suffix U for XPAR_CPU_ID
+* parameter of cpu_cortexa9 in xparameters.h
+# 2.7 mus 07/03/18 Updated tcl to not to add default flags forcefully into
+# extra compiler flags. Now, user can remove default flags
+# from extra compiler flags. It fixes CR#998768.
+******************************************************************************/
+/** @} */
diff --git a/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/include/xddrps.h b/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/include/xddrps.h
new file mode 100644
index 0000000..8b1d991
--- /dev/null
+++ b/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/include/xddrps.h
@@ -0,0 +1,60 @@
+/*******************************************************************************
+ *
+ * Copyright (C) 2015 Xilinx, Inc. All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ *
+ *
+ *
+*******************************************************************************/
+/******************************************************************************/
+/**
+ *
+ * @file xddrps.h
+ * @addtogroup ddrps_v1_0
+ * @{
+ * @details
+ *
+ * The Xilinx DdrPs driver. This driver supports the Xilinx ddrps
+ * IP core.
+ *
+ * @note None.
+ *
+ * <pre>
+ * MODIFICATION HISTORY:
+ *
+ * Ver Who Date Changes
+ * ----- ---- -------- -----------------------------------------------
+ * 1.0 nsk 08/06/15 First Release
+ * 1.0 nsk 08/20/15 Updated define_addr_params in ddrps.tcl
+ * to support PBD Designs (CR #876857)
+ *
+ * </pre>
+ *
+*******************************************************************************/
+
+#ifndef XDDRPS_H_
+/* Prevent circular inclusions by using protection macros. */
+#define XDDRPS_H_
+
+/******************************* Include Files ********************************/
+
+
+#endif /* XDDRPS_H_ */
+/** @} */
diff --git a/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/include/xdebug.h b/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/include/xdebug.h
new file mode 100644
index 0000000..b09c02d
--- /dev/null
+++ b/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/include/xdebug.h
@@ -0,0 +1,40 @@
+#ifndef XDEBUG /* prevent circular inclusions */
+#define XDEBUG /* by using protection macros */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#if defined(DEBUG) && !defined(NDEBUG)
+
+#ifndef XDEBUG_WARNING
+#define XDEBUG_WARNING
+#warning DEBUG is enabled
+#endif
+
+int printf(const char *format, ...);
+
+#define XDBG_DEBUG_ERROR 0x00000001U /* error condition messages */
+#define XDBG_DEBUG_GENERAL 0x00000002U /* general debug messages */
+#define XDBG_DEBUG_ALL 0xFFFFFFFFU /* all debugging data */
+
+#define xdbg_current_types (XDBG_DEBUG_GENERAL)
+
+#define xdbg_stmnt(x) x
+
+#define xdbg_printf(type, ...) (((type) & xdbg_current_types) ? printf (__VA_ARGS__) : 0)
+
+
+#else /* defined(DEBUG) && !defined(NDEBUG) */
+
+#define xdbg_stmnt(x)
+
+#define xdbg_printf(...)
+
+#endif /* defined(DEBUG) && !defined(NDEBUG) */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* XDEBUG */
diff --git a/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/include/xdevcfg.h b/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/include/xdevcfg.h
new file mode 100644
index 0000000..05105ce
--- /dev/null
+++ b/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/include/xdevcfg.h
@@ -0,0 +1,397 @@
+/******************************************************************************
+*
+* Copyright (C) 2010 - 2017 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+* THE SOFTWARE.
+*
+*
+*
+******************************************************************************/
+/****************************************************************************/
+/**
+*
+* @file xdevcfg.h
+* @addtogroup devcfg_v3_5
+* @{
+* @details
+*
+* The is the main header file for the Device Configuration Interface of the Zynq
+* device. The device configuration interface has three main functionality.
+* 1. AXI-PCAP
+* 2. Security Policy
+* 3. XADC
+* This current version of the driver supports only the AXI-PCAP and Security
+* Policy blocks. There is a separate driver for XADC.
+*
+* AXI-PCAP is used for download/upload an encrypted or decrypted bitstream.
+* DMA embedded in the AXI PCAP provides the master interface to
+* the Device configuration block for any DMA transfers. The data transfer can
+* take place between the Tx/RxFIFOs of AXI-PCAP and memory (on chip
+* RAM/DDR/peripheral memory).
+*
+* The current driver only supports the downloading the FPGA bitstream and
+* readback of the decrypted image (sort of loopback).
+* The driver does not know what information needs to be written to the FPGA to
+* readback FPGA configuration register or memory data. The application above the
+* driver should take care of creating the data that needs to be downloaded to
+* the FPGA so that the bitstream can be readback.
+* This driver also does not support the reading of the internal registers of the
+* PCAP. The driver has no knowledge of the PCAP internals.
+*
+* <b> Initialization and Configuration </b>
+*
+* The device driver enables higher layer software (e.g., an application) to
+* communicate with the Device Configuration device.
+*
+* XDcfg_CfgInitialize() API is used to initialize the Device Configuration
+* Interface. The user needs to first call the XDcfg_LookupConfig() API which
+* returns the Configuration structure pointer which is passed as a parameter to
+* the XDcfg_CfgInitialize() API.
+*
+* <b>Interrupts</b>
+* The Driver implements an interrupt handler to support the interrupts provided
+* by this interface.
+*
+* <b> Threads </b>
+*
+* This driver is not thread safe. Any needs for threads or thread mutual
+* exclusion must be satisfied by the layer above this driver.
+*
+* <b> Asserts </b>
+*
+* Asserts are used within all Xilinx drivers to enforce constraints on argument
+* values. Asserts can be turned off on a system-wide basis by defining, at
+* compile time, the NDEBUG identifier. By default, asserts are turned on and it
+* is recommended that users leave asserts on during development.
+*
+* <b> Building the driver </b>
+*
+* The XDcfg driver is composed of several source files. This allows the user
+* to build and link only those parts of the driver that are necessary.
+*
+* <br><br>
+*
+* <pre>
+* MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ----- --- -------- ---------------------------------------------
+* 1.00a hvm 02/07/11 First release
+* 2.00a nm 05/31/12 Updated the driver for CR 660835 so that input length for
+* source/destination to the XDcfg_InitiateDma, XDcfg_Transfer
+* APIs is words (32 bit) and not bytes.
+* Updated the notes for XDcfg_InitiateDma/XDcfg_Transfer APIs
+* to add information that 2 LSBs of the Source/Destination
+* address when equal to 2�b01 indicate the last DMA command
+* of an overall transfer.
+* Destination Address passed to this API for secure transfers
+* instead of using 0xFFFFFFFF for CR 662197. This issue was
+* resulting in the failure of secure transfers of
+* non-bitstream images.
+* 2.01a nm 07/07/12 Updated the XDcfg_IntrClear function to directly
+* set the mask instead of oring it with the
+* value read from the interrupt status register
+* Added defines for the PS Version bits,
+* removed the FIFO Flush bits from the
+* Miscellaneous Control Reg.
+* Added XDcfg_GetPsVersion, XDcfg_SelectIcapInterface
+* and XDcfg_SelectPcapInterface APIs for CR 643295
+* The user has to call the XDcfg_SelectIcapInterface API
+* for the PL reconfiguration using AXI HwIcap.
+* Updated the XDcfg_Transfer API to clear the
+* QUARTER_PCAP_RATE_EN bit in the control register for
+* non secure writes for CR 675543.
+* 2.02a nm 01/31/13 Fixed CR# 679335.
+* Added Setting and Clearing the internal PCAP loopback.
+* Removed code for enabling/disabling AES engine as BootROM
+* locks down this setting.
+* Fixed CR# 681976.
+* Skip Checking the PCFG_INIT in case of non-secure DMA
+* loopback.
+* Fixed CR# 699558.
+* XDcfg_Transfer fails to transfer data in loopback mode.
+* Fixed CR# 701348.
+* Peripheral test fails with Running
+* DcfgSelfTestExample() in SECURE bootmode.
+* 2.03a nm 04/19/13 Fixed CR# 703728.
+* Updated the register definitions as per the latest TRM
+* version UG585 (v1.4) November 16, 2012.
+* 3.0 adk 10/12/13 Updated as per the New Tcl API's
+* 3.0 kpc 21/02/14 Added function prototype for XDcfg_ClearControlRegister
+* 3.2 sb 08/25/14 Fixed XDcfg_PcapReadback() function
+* updated driver code with != instead of ==,
+* while checking for Interrupt Status with DMA and
+* PCAP Done Mask
+* ((XDcfg_ReadReg(InstancePtr->Config.BaseAddr,
+* XDCFG_INT_STS_OFFSET) &
+* XDCFG_IXR_D_P_DONE_MASK) !=
+* XDCFG_IXR_D_P_DONE_MASK);
+* A new example has been added to read back the
+* configuration registers from the PL region.
+* xdevcfg_reg_readback_example.c
+* 3.3 sk 04/06/15 Modified XDcfg_ReadMultiBootConfig Macro CR# 851335.
+* ms 03/17/17 Added readme.txt file in examples folder for doxygen
+* generation.
+* ms 04/10/17 Modified filename tag in interrupt and polled examples
+* to include them in doxygen examples.
+* 3.5 ms 04/18/17 Modified tcl file to add suffix U for all macros
+* definitions of devcfg in xparameters.h
+* ms 08/07/17 Fixed compilation warnings in xdevcfg_sinit.c
+* </pre>
+*
+******************************************************************************/
+#ifndef XDCFG_H /* prevent circular inclusions */
+#define XDCFG_H /* by using protection macros */
+
+/***************************** Include Files *********************************/
+
+#include "xdevcfg_hw.h"
+#include "xstatus.h"
+#include "xil_assert.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/************************** Constant Definitions *****************************/
+
+/* Types of PCAP transfers */
+
+#define XDCFG_NON_SECURE_PCAP_WRITE 1
+#define XDCFG_SECURE_PCAP_WRITE 2
+#define XDCFG_PCAP_READBACK 3
+#define XDCFG_CONCURRENT_SECURE_READ_WRITE 4
+#define XDCFG_CONCURRENT_NONSEC_READ_WRITE 5
+
+
+/**************************** Type Definitions *******************************/
+/**
+* The handler data type allows the user to define a callback function to
+* respond to interrupt events in the system. This function is executed
+* in interrupt context, so amount of processing should be minimized.
+*
+* @param CallBackRef is the callback reference passed in by the upper
+* layer when setting the callback functions, and passed back to
+* the upper layer when the callback is invoked. Its type is
+* unimportant to the driver component, so it is a void pointer.
+* @param Status is the Interrupt status of the XDcfg device.
+*/
+typedef void (*XDcfg_IntrHandler) (void *CallBackRef, u32 Status);
+
+/**
+ * This typedef contains configuration information for the device.
+ */
+typedef struct {
+ u16 DeviceId; /**< Unique ID of device */
+ u32 BaseAddr; /**< Base address of the device */
+} XDcfg_Config;
+
+/**
+ * The XDcfg driver instance data.
+ */
+typedef struct {
+ XDcfg_Config Config; /**< Hardware Configuration */
+ u32 IsReady; /**< Device is initialized and ready */
+ u32 IsStarted; /**< Device Configuration Interface
+ * is running
+ */
+ XDcfg_IntrHandler StatusHandler; /* Event handler function */
+ void *CallBackRef; /* Callback reference for event handler */
+} XDcfg;
+
+/****************************************************************************/
+/**
+*
+* Unlock the Device Config Interface block.
+*
+* @param InstancePtr is a pointer to the instance of XDcfg driver.
+*
+* @return None.
+*
+* @note C-style signature:
+* void XDcfg_Unlock(XDcfg* InstancePtr)
+*
+*****************************************************************************/
+#define XDcfg_Unlock(InstancePtr) \
+ XDcfg_WriteReg((InstancePtr)->Config.BaseAddr, \
+ XDCFG_UNLOCK_OFFSET, XDCFG_UNLOCK_DATA)
+
+
+
+/****************************************************************************/
+/**
+*
+* Get the version number of the PS from the Miscellaneous Control Register.
+*
+* @param InstancePtr is a pointer to the instance of XDcfg driver.
+*
+* @return Version of the PS.
+*
+* @note C-style signature:
+* void XDcfg_GetPsVersion(XDcfg* InstancePtr)
+*
+*****************************************************************************/
+#define XDcfg_GetPsVersion(InstancePtr) \
+ ((XDcfg_ReadReg((InstancePtr)->Config.BaseAddr, \
+ XDCFG_MCTRL_OFFSET)) & \
+ XDCFG_MCTRL_PCAP_PS_VERSION_MASK) >> \
+ XDCFG_MCTRL_PCAP_PS_VERSION_SHIFT
+
+
+
+/****************************************************************************/
+/**
+*
+* Read the multiboot config register value.
+*
+* @param InstancePtr is a pointer to the instance of XDcfg driver.
+*
+* @return None.
+*
+* @note C-style signature:
+* u32 XDcfg_ReadMultiBootConfig(XDcfg* InstancePtr)
+*
+*****************************************************************************/
+#define XDcfg_ReadMultiBootConfig(InstancePtr) \
+ XDcfg_ReadReg((InstancePtr)->Config.BaseAddr, \
+ XDCFG_MULTIBOOT_ADDR_OFFSET)
+
+
+/****************************************************************************/
+/**
+*
+* Selects ICAP interface for reconfiguration after the initial configuration
+* of the PL.
+*
+* @param InstancePtr is a pointer to the instance of XDcfg driver.
+*
+* @return None.
+*
+* @note C-style signature:
+* void XDcfg_SelectIcapInterface(XDcfg* InstancePtr)
+*
+*****************************************************************************/
+#define XDcfg_SelectIcapInterface(InstancePtr) \
+ XDcfg_WriteReg((InstancePtr)->Config.BaseAddr, XDCFG_CTRL_OFFSET, \
+ ((XDcfg_ReadReg((InstancePtr)->Config.BaseAddr, XDCFG_CTRL_OFFSET)) \
+ & ( ~XDCFG_CTRL_PCAP_PR_MASK)))
+
+/****************************************************************************/
+/**
+*
+* Selects PCAP interface for reconfiguration after the initial configuration
+* of the PL.
+*
+* @param InstancePtr is a pointer to the instance of XDcfg driver.
+*
+* @return None.
+*
+* @note C-style signature:
+* void XDcfg_SelectPcapInterface(XDcfg* InstancePtr)
+*
+*****************************************************************************/
+#define XDcfg_SelectPcapInterface(InstancePtr) \
+ XDcfg_WriteReg((InstancePtr)->Config.BaseAddr, XDCFG_CTRL_OFFSET, \
+ ((XDcfg_ReadReg((InstancePtr)->Config.BaseAddr, XDCFG_CTRL_OFFSET)) \
+ | XDCFG_CTRL_PCAP_PR_MASK))
+
+
+
+/************************** Function Prototypes ******************************/
+
+/*
+ * Lookup configuration in xdevcfg_sinit.c.
+ */
+XDcfg_Config *XDcfg_LookupConfig(u16 DeviceId);
+
+/*
+ * Selftest function in xdevcfg_selftest.c
+ */
+int XDcfg_SelfTest(XDcfg *InstancePtr);
+
+/*
+ * Interface functions in xdevcfg.c
+ */
+int XDcfg_CfgInitialize(XDcfg *InstancePtr,
+ XDcfg_Config *ConfigPtr, u32 EffectiveAddress);
+
+void XDcfg_EnablePCAP(XDcfg *InstancePtr);
+
+void XDcfg_DisablePCAP(XDcfg *InstancePtr);
+
+void XDcfg_SetControlRegister(XDcfg *InstancePtr, u32 Mask);
+
+void XDcfg_ClearControlRegister(XDcfg *InstancePtr, u32 Mask);
+
+u32 XDcfg_GetControlRegister(XDcfg *InstancePtr);
+
+void XDcfg_SetLockRegister(XDcfg *InstancePtr, u32 Data);
+
+u32 XDcfg_GetLockRegister(XDcfg *InstancePtr);
+
+void XDcfg_SetConfigRegister(XDcfg *InstancePtr, u32 Data);
+
+u32 XDcfg_GetConfigRegister(XDcfg *InstancePtr);
+
+void XDcfg_SetStatusRegister(XDcfg *InstancePtr, u32 Data);
+
+u32 XDcfg_GetStatusRegister(XDcfg *InstancePtr);
+
+void XDcfg_SetRomShadowRegister(XDcfg *InstancePtr, u32 Data);
+
+u32 XDcfg_GetSoftwareIdRegister(XDcfg *InstancePtr);
+
+void XDcfg_SetMiscControlRegister(XDcfg *InstancePtr, u32 Mask);
+
+u32 XDcfg_GetMiscControlRegister(XDcfg *InstancePtr);
+
+u32 XDcfg_IsDmaBusy(XDcfg *InstancePtr);
+
+void XDcfg_InitiateDma(XDcfg *InstancePtr, u32 SourcePtr, u32 DestPtr,
+ u32 SrcWordLength, u32 DestWordLength);
+
+u32 XDcfg_Transfer(XDcfg *InstancePtr,
+ void *SourcePtr, u32 SrcWordLength,
+ void *DestPtr, u32 DestWordLength,
+ u32 TransferType);
+
+/*
+ * Interrupt related function prototypes implemented in xdevcfg_intr.c
+ */
+void XDcfg_IntrEnable(XDcfg *InstancePtr, u32 Mask);
+
+void XDcfg_IntrDisable(XDcfg *InstancePtr, u32 Mask);
+
+u32 XDcfg_IntrGetEnabled(XDcfg *InstancePtr);
+
+u32 XDcfg_IntrGetStatus(XDcfg *InstancePtr);
+
+void XDcfg_IntrClear(XDcfg *InstancePtr, u32 Mask);
+
+void XDcfg_InterruptHandler(XDcfg *InstancePtr);
+
+void XDcfg_SetHandler(XDcfg *InstancePtr, void *CallBackFunc,
+ void *CallBackRef);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* end of protection macro */
+/** @} */
diff --git a/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/include/xdevcfg_hw.h b/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/include/xdevcfg_hw.h
new file mode 100644
index 0000000..56a9f41
--- /dev/null
+++ b/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/include/xdevcfg_hw.h
@@ -0,0 +1,389 @@
+/******************************************************************************
+*
+* Copyright (C) 2010 - 2015 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+* THE SOFTWARE.
+*
+*
+*
+******************************************************************************/
+/****************************************************************************/
+/**
+*
+* @file xdevcfg_hw.h
+* @addtogroup devcfg_v3_3
+* @{
+*
+* This file contains the hardware interface to the Device Config Interface.
+*
+* <pre>
+* MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ----- --- -------- ---------------------------------------------
+* 1.00a hvm 02/07/11 First release
+* 2.01a nm 08/01/12 Added defines for the PS Version bits,
+* removed the FIFO Flush bits from the
+* Miscellaneous Control Reg
+* 2.03a nm 04/19/13 Fixed CR# 703728.
+* Updated the register definitions as per the latest TRM
+* version UG585 (v1.4) November 16, 2012.
+* 2.04a kpc 10/07/13 Added function prototype.
+* 3.00a kpc 25/02/14 Corrected the XDCFG_BASE_ADDRESS macro value.
+* </pre>
+*
+******************************************************************************/
+#ifndef XDCFG_HW_H /* prevent circular inclusions */
+#define XDCFG_HW_H /* by using protection macros */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/***************************** Include Files *********************************/
+
+#include "xil_types.h"
+#include "xil_io.h"
+
+/************************** Constant Definitions *****************************/
+
+/** @name Register Map
+ * Offsets of registers from the start of the device
+ * @{
+ */
+
+#define XDCFG_CTRL_OFFSET 0x00 /**< Control Register */
+#define XDCFG_LOCK_OFFSET 0x04 /**< Lock Register */
+#define XDCFG_CFG_OFFSET 0x08 /**< Configuration Register */
+#define XDCFG_INT_STS_OFFSET 0x0C /**< Interrupt Status Register */
+#define XDCFG_INT_MASK_OFFSET 0x10 /**< Interrupt Mask Register */
+#define XDCFG_STATUS_OFFSET 0x14 /**< Status Register */
+#define XDCFG_DMA_SRC_ADDR_OFFSET 0x18 /**< DMA Source Address Register */
+#define XDCFG_DMA_DEST_ADDR_OFFSET 0x1C /**< DMA Destination Address Reg */
+#define XDCFG_DMA_SRC_LEN_OFFSET 0x20 /**< DMA Source Transfer Length */
+#define XDCFG_DMA_DEST_LEN_OFFSET 0x24 /**< DMA Destination Transfer */
+#define XDCFG_ROM_SHADOW_OFFSET 0x28 /**< DMA ROM Shadow Register */
+#define XDCFG_MULTIBOOT_ADDR_OFFSET 0x2C /**< Multi BootAddress Pointer */
+#define XDCFG_SW_ID_OFFSET 0x30 /**< Software ID Register */
+#define XDCFG_UNLOCK_OFFSET 0x34 /**< Unlock Register */
+#define XDCFG_MCTRL_OFFSET 0x80 /**< Miscellaneous Control Reg */
+
+/* @} */
+
+/** @name Control Register Bit definitions
+ * @{
+ */
+
+#define XDCFG_CTRL_FORCE_RST_MASK 0x80000000 /**< Force into
+ * Secure Reset
+ */
+#define XDCFG_CTRL_PCFG_PROG_B_MASK 0x40000000 /**< Program signal to
+ * Reset FPGA
+ */
+#define XDCFG_CTRL_PCFG_POR_CNT_4K_MASK 0x20000000 /**< Control PL POR timer */
+#define XDCFG_CTRL_PCAP_PR_MASK 0x08000000 /**< Enable PCAP for PR */
+#define XDCFG_CTRL_PCAP_MODE_MASK 0x04000000 /**< Enable PCAP */
+#define XDCFG_CTRL_PCAP_RATE_EN_MASK 0x02000000 /**< Enable PCAP send data
+ * to FPGA every 4 PCAP
+ * cycles
+ */
+#define XDCFG_CTRL_MULTIBOOT_EN_MASK 0x01000000 /**< Multiboot Enable */
+#define XDCFG_CTRL_JTAG_CHAIN_DIS_MASK 0x00800000 /**< JTAG Chain Disable */
+#define XDCFG_CTRL_USER_MODE_MASK 0x00008000 /**< User Mode Mask */
+#define XDCFG_CTRL_PCFG_AES_FUSE_MASK 0x00001000 /**< AES key source */
+#define XDCFG_CTRL_PCFG_AES_EN_MASK 0x00000E00 /**< AES Enable Mask */
+#define XDCFG_CTRL_SEU_EN_MASK 0x00000100 /**< SEU Enable Mask */
+#define XDCFG_CTRL_SEC_EN_MASK 0x00000080 /**< Secure/Non Secure
+ * Status mask
+ */
+#define XDCFG_CTRL_SPNIDEN_MASK 0x00000040 /**< Secure Non Invasive
+ * Debug Enable
+ */
+#define XDCFG_CTRL_SPIDEN_MASK 0x00000020 /**< Secure Invasive
+ * Debug Enable
+ */
+#define XDCFG_CTRL_NIDEN_MASK 0x00000010 /**< Non-Invasive Debug
+ * Enable
+ */
+#define XDCFG_CTRL_DBGEN_MASK 0x00000008 /**< Invasive Debug
+ * Enable
+ */
+#define XDCFG_CTRL_DAP_EN_MASK 0x00000007 /**< DAP Enable Mask */
+
+/* @} */
+
+/** @name Lock register bit definitions
+ * @{
+ */
+
+#define XDCFG_LOCK_AES_EFUSE_MASK 0x00000010 /**< Lock AES Efuse bit */
+#define XDCFG_LOCK_AES_EN_MASK 0x00000008 /**< Lock AES_EN update */
+#define XDCFG_LOCK_SEU_MASK 0x00000004 /**< Lock SEU_En update */
+#define XDCFG_LOCK_SEC_MASK 0x00000002 /**< Lock SEC_EN and
+ * USER_MODE
+ */
+#define XDCFG_LOCK_DBG_MASK 0x00000001 /**< This bit locks
+ * security config
+ * including: DAP_En,
+ * DBGEN,,
+ * NIDEN, SPNIEN
+ */
+/*@}*/
+
+
+
+/** @name Config Register Bit definitions
+ * @{
+ */
+#define XDCFG_CFG_RFIFO_TH_MASK 0x00000C00 /**< Read FIFO
+ * Threshold Mask
+ */
+#define XDCFG_CFG_WFIFO_TH_MASK 0x00000300 /**< Write FIFO Threshold
+ * Mask
+ */
+#define XDCFG_CFG_RCLK_EDGE_MASK 0x00000080 /**< Read data active
+ * clock edge
+ */
+#define XDCFG_CFG_WCLK_EDGE_MASK 0x00000040 /**< Write data active
+ * clock edge
+ */
+#define XDCFG_CFG_DISABLE_SRC_INC_MASK 0x00000020 /**< Disable Source address
+ * increment mask
+ */
+#define XDCFG_CFG_DISABLE_DST_INC_MASK 0x00000010 /**< Disable Destination
+ * address increment
+ * mask
+ */
+/* @} */
+
+
+/** @name Interrupt Status/Mask Register Bit definitions
+ * @{
+ */
+#define XDCFG_IXR_PSS_GTS_USR_B_MASK 0x80000000 /**< Tri-state IO during
+ * HIZ
+ */
+#define XDCFG_IXR_PSS_FST_CFG_B_MASK 0x40000000 /**< First configuration
+ * done
+ */
+#define XDCFG_IXR_PSS_GPWRDWN_B_MASK 0x20000000 /**< Global power down */
+#define XDCFG_IXR_PSS_GTS_CFG_B_MASK 0x10000000 /**< Tri-state IO during
+ * configuration
+ */
+#define XDCFG_IXR_PSS_CFG_RESET_B_MASK 0x08000000 /**< PL configuration
+ * reset
+ */
+#define XDCFG_IXR_AXI_WTO_MASK 0x00800000 /**< AXI Write Address
+ * or Data or response
+ * timeout
+ */
+#define XDCFG_IXR_AXI_WERR_MASK 0x00400000 /**< AXI Write response
+ * error
+ */
+#define XDCFG_IXR_AXI_RTO_MASK 0x00200000 /**< AXI Read Address or
+ * response timeout
+ */
+#define XDCFG_IXR_AXI_RERR_MASK 0x00100000 /**< AXI Read response
+ * error
+ */
+#define XDCFG_IXR_RX_FIFO_OV_MASK 0x00040000 /**< Rx FIFO Overflow */
+#define XDCFG_IXR_WR_FIFO_LVL_MASK 0x00020000 /**< Tx FIFO less than
+ * threshold */
+#define XDCFG_IXR_RD_FIFO_LVL_MASK 0x00010000 /**< Rx FIFO greater than
+ * threshold */
+#define XDCFG_IXR_DMA_CMD_ERR_MASK 0x00008000 /**< Illegal DMA command */
+#define XDCFG_IXR_DMA_Q_OV_MASK 0x00004000 /**< DMA command queue
+ * overflow
+ */
+#define XDCFG_IXR_DMA_DONE_MASK 0x00002000 /**< DMA Command Done */
+#define XDCFG_IXR_D_P_DONE_MASK 0x00001000 /**< DMA and PCAP
+ * transfers Done
+ */
+#define XDCFG_IXR_P2D_LEN_ERR_MASK 0x00000800 /**< PCAP to DMA transfer
+ * length error
+ */
+#define XDCFG_IXR_PCFG_HMAC_ERR_MASK 0x00000040 /**< HMAC error mask */
+#define XDCFG_IXR_PCFG_SEU_ERR_MASK 0x00000020 /**< SEU Error mask */
+#define XDCFG_IXR_PCFG_POR_B_MASK 0x00000010 /**< FPGA POR mask */
+#define XDCFG_IXR_PCFG_CFG_RST_MASK 0x00000008 /**< FPGA Reset mask */
+#define XDCFG_IXR_PCFG_DONE_MASK 0x00000004 /**< Done Signal Mask */
+#define XDCFG_IXR_PCFG_INIT_PE_MASK 0x00000002 /**< Detect Positive edge
+ * of Init Signal
+ */
+#define XDCFG_IXR_PCFG_INIT_NE_MASK 0x00000001 /**< Detect Negative edge
+ * of Init Signal
+ */
+#define XDCFG_IXR_ERROR_FLAGS_MASK (XDCFG_IXR_AXI_WTO_MASK | \
+ XDCFG_IXR_AXI_WERR_MASK | \
+ XDCFG_IXR_AXI_RTO_MASK | \
+ XDCFG_IXR_AXI_RERR_MASK | \
+ XDCFG_IXR_RX_FIFO_OV_MASK | \
+ XDCFG_IXR_DMA_CMD_ERR_MASK |\
+ XDCFG_IXR_DMA_Q_OV_MASK | \
+ XDCFG_IXR_P2D_LEN_ERR_MASK |\
+ XDCFG_IXR_PCFG_HMAC_ERR_MASK)
+
+
+#define XDCFG_IXR_ALL_MASK 0x00F7F8EF
+
+
+
+/* @} */
+
+
+/** @name Status Register Bit definitions
+ * @{
+ */
+#define XDCFG_STATUS_DMA_CMD_Q_F_MASK 0x80000000 /**< DMA command
+ * Queue full
+ */
+#define XDCFG_STATUS_DMA_CMD_Q_E_MASK 0x40000000 /**< DMA command
+ * Queue empty
+ */
+#define XDCFG_STATUS_DMA_DONE_CNT_MASK 0x30000000 /**< Number of
+ * completed DMA
+ * transfers
+ */
+#define XDCFG_STATUS_RX_FIFO_LVL_MASK 0x01F000000 /**< Rx FIFO level */
+#define XDCFG_STATUS_TX_FIFO_LVL_MASK 0x0007F000 /**< Tx FIFO level */
+
+#define XDCFG_STATUS_PSS_GTS_USR_B 0x00000800 /**< Tri-state IO
+ * during HIZ
+ */
+#define XDCFG_STATUS_PSS_FST_CFG_B 0x00000400 /**< First PL config
+ * done
+ */
+#define XDCFG_STATUS_PSS_GPWRDWN_B 0x00000200 /**< Global power down */
+#define XDCFG_STATUS_PSS_GTS_CFG_B 0x00000100 /**< Tri-state IO during
+ * config
+ */
+#define XDCFG_STATUS_SECURE_RST_MASK 0x00000080 /**< Secure Reset
+ * POR Status
+ */
+#define XDCFG_STATUS_ILLEGAL_APB_ACCESS_MASK 0x00000040 /**< Illegal APB
+ * access
+ */
+#define XDCFG_STATUS_PSS_CFG_RESET_B 0x00000020 /**< PL config
+ * reset status
+ */
+#define XDCFG_STATUS_PCFG_INIT_MASK 0x00000010 /**< FPGA Init
+ * Status
+ */
+#define XDCFG_STATUS_EFUSE_BBRAM_KEY_DISABLE_MASK 0x00000008
+ /**< BBRAM key
+ * disable
+ */
+#define XDCFG_STATUS_EFUSE_SEC_EN_MASK 0x00000004 /**< Efuse Security
+ * Enable Status
+ */
+#define XDCFG_STATUS_EFUSE_JTAG_DIS_MASK 0x00000002 /**< EFuse JTAG
+ * Disable
+ * status
+ */
+/* @} */
+
+
+/** @name DMA Source/Destination Transfer Length Register Bit definitions
+ * @{
+ */
+#define XDCFG_DMA_LEN_MASK 0x7FFFFFF /**< Length Mask */
+/*@}*/
+
+
+
+
+/** @name Miscellaneous Control Register Bit definitions
+ * @{
+ */
+#define XDCFG_MCTRL_PCAP_PS_VERSION_MASK 0xF0000000 /**< PS Version Mask */
+#define XDCFG_MCTRL_PCAP_PS_VERSION_SHIFT 28 /**< PS Version Shift */
+#define XDCFG_MCTRL_PCAP_LPBK_MASK 0x00000010 /**< PCAP loopback mask */
+/* @} */
+
+/** @name FIFO Threshold Bit definitions
+ * @{
+ */
+
+#define XDCFG_CFG_FIFO_QUARTER 0x0 /**< Quarter empty */
+#define XDCFG_CFG_FIFO_HALF 0x1 /**< Half empty */
+#define XDCFG_CFG_FIFO_3QUARTER 0x2 /**< 3/4 empty */
+#define XDCFG_CFG_FIFO_EMPTY 0x4 /**< Empty */
+/* @}*/
+
+
+/* Miscellaneous constant values */
+#define XDCFG_DMA_INVALID_ADDRESS 0xFFFFFFFF /**< Invalid DMA address */
+#define XDCFG_UNLOCK_DATA 0x757BDF0D /**< First APB access data*/
+#define XDCFG_BASE_ADDRESS 0xF8007000 /**< Device Config base
+ * address
+ */
+#define XDCFG_CONFIG_RESET_VALUE 0x508 /**< Config reg reset value */
+
+/**************************** Type Definitions *******************************/
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/****************************************************************************/
+/**
+*
+* Read the given register.
+*
+* @param BaseAddr is the base address of the device
+* @param RegOffset is the register offset to be read
+*
+* @return The 32-bit value of the register
+*
+* @note C-style signature:
+* u32 XDcfg_ReadReg(u32 BaseAddr, u32 RegOffset)
+*
+*****************************************************************************/
+#define XDcfg_ReadReg(BaseAddr, RegOffset) \
+ Xil_In32((BaseAddr) + (RegOffset))
+
+/****************************************************************************/
+/**
+*
+* Write to the given register.
+*
+* @param BaseAddr is the base address of the device
+* @param RegOffset is the register offset to be written
+* @param Data is the 32-bit value to write to the register
+*
+* @return None.
+*
+* @note C-style signature:
+* void XDcfg_WriteReg(u32 BaseAddr, u32 RegOffset, u32 Data)
+*
+*****************************************************************************/
+#define XDcfg_WriteReg(BaseAddr, RegOffset, Data) \
+ Xil_Out32((BaseAddr) + (RegOffset), (Data))
+
+/************************** Function Prototypes ******************************/
+/*
+ * Perform reset operation to the devcfg interface
+ */
+void XDcfg_ResetHw(u32 BaseAddr);
+/************************** Variable Definitions *****************************/
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* end of protection macro */
+/** @} */
diff --git a/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/include/xdmaps.h b/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/include/xdmaps.h
new file mode 100644
index 0000000..831a2dd
--- /dev/null
+++ b/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/include/xdmaps.h
@@ -0,0 +1,347 @@
+/******************************************************************************
+*
+* Copyright (C) 2009 - 2019 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+* THE SOFTWARE.
+*
+*
+*
+******************************************************************************/
+/****************************************************************************/
+/**
+*
+* @file xdmaps.h
+* @addtogroup dmaps_v2_5
+* @{
+* @details
+*
+*
+* <pre>
+* MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ----- ------ -------- ----------------------------------------------
+* 1.00 hbm 08/19/10 First Release
+* 1.01a nm 12/20/12 Added definition XDMAPS_CHANNELS_PER_DEV which specifies
+* the maximum number of channels.
+* Replaced the usage of XPAR_XDMAPS_CHANNELS_PER_DEV
+* with XDMAPS_CHANNELS_PER_DEV defined in xdmaps_hw.h.
+* Added the tcl file to automatically generate the
+* xparameters.h
+* 1.02a sg 05/16/12 Made changes for doxygen and moved some function
+* header from the xdmaps.h file to xdmaps.c file
+* Other cleanup for coding guidelines and CR 657109
+* and CR 657898
+* The xdmaps_example_no_intr.c example is removed
+* as it is using interrupts and is similar to
+* the interrupt example - CR 652477
+* 1.03a sg 07/16/2012 changed inline to __inline for CR665681
+* 1.04a nm 10/22/2012 Fixed CR# 681671.
+* 1.05a nm 04/15/2013 Fixed CR# 704396. Removed warnings when compiled
+* with -Wall and -Wextra option in bsp.
+* 05/01/2013 Fixed CR# 700189. Changed XDmaPs_BuildDmaProg()
+* function description.
+* Fixed CR# 704396. Removed unused variables
+* UseM2MByte & MemBurstLen from XDmaPs_BuildDmaProg()
+* function.
+* 1.07a asa 11/02/13. Made changes to fix compilation issues for iarcc.
+* Removed the PDBG prints. By default they were always
+* defined out and never used. The PDBG is non-standard for
+* Xilinx drivers and no other driver does something similar.
+* Since there is no easy way to fix compilation issues with
+* the IARCC compiler around PDBG, it is better to remove it.
+* Users can always use xil_printfs if they want to debug.
+* 2.0 adk 10/12/13 Updated as per the New Tcl API's
+* 2.01 kpc 08/23/14 Fixed the IAR compiler reported errors
+* 2.2 mus 08/12/16 Declared all inline functions in xdmaps.c as extern, to avoid
+* linker error for IAR compiler
+* 2.3 ms 01/23/17 Modified xil_printf statement in main function for all
+* examples to ensure that "Successfully ran" and "Failed"
+* strings are available in all examples. This is a fix
+* for CR-965028.
+* ms 03/17/17 Added readme.txt file in examples folder for doxygen
+* generation.
+* 2.4 adk 13/08/18 Fixed armcc compiler warnings in the driver CR-1008310.
+* </pre>
+*
+*****************************************************************************/
+
+#ifndef XDMAPS_H /* prevent circular inclusions */
+#define XDMAPS_H /* by using protection macros */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/***************************** Include Files ********************************/
+
+#include "xparameters.h"
+#include "xil_types.h"
+#include "xil_assert.h"
+#include "xstatus.h"
+
+#include "xdmaps_hw.h"
+
+/************************** Constant Definitions ****************************/
+
+/**************************** Type Definitions ******************************/
+
+/**
+ * This typedef contains configuration information for the device.
+ */
+typedef struct {
+ u16 DeviceId; /**< Unique ID of device */
+ u32 BaseAddress; /**< Base address of device (IPIF) */
+} XDmaPs_Config;
+
+
+/** DMA channle control structure. It's for AXI bus transaction.
+ * This struct will be translated into a 32-bit channel control register value.
+ */
+typedef struct {
+ unsigned int EndianSwapSize; /**< Endian swap size. */
+ unsigned int DstCacheCtrl; /**< Destination cache control */
+ unsigned int DstProtCtrl; /**< Destination protection control */
+ unsigned int DstBurstLen; /**< Destination burst length */
+ unsigned int DstBurstSize; /**< Destination burst size */
+ unsigned int DstInc; /**< Destination incrementing or fixed
+ * address */
+ unsigned int SrcCacheCtrl; /**< Source cache control */
+ unsigned int SrcProtCtrl; /**< Source protection control */
+ unsigned int SrcBurstLen; /**< Source burst length */
+ unsigned int SrcBurstSize; /**< Source burst size */
+ unsigned int SrcInc; /**< Source incrementing or fixed
+ * address */
+} XDmaPs_ChanCtrl;
+
+/** DMA block descriptor stucture.
+ */
+typedef struct {
+ u32 SrcAddr; /**< Source starting address */
+ u32 DstAddr; /**< Destination starting address */
+ unsigned int Length; /**< Number of bytes for the block */
+} XDmaPs_BD;
+
+/**
+ * A DMA command consisits of a channel control struct, a block descriptor,
+ * a user defined program, a pointer pointing to generated DMA program, and
+ * execution result.
+ *
+ */
+typedef struct {
+ XDmaPs_ChanCtrl ChanCtrl; /**< Channel Control Struct */
+ XDmaPs_BD BD; /**< Together with SgLength field,
+ * it's a scatter-gather list.
+ */
+ void *UserDmaProg; /**< If user wants the driver to
+ * execute their own DMA program,
+ * this field points to the DMA
+ * program.
+ */
+ int UserDmaProgLength; /**< The length of user defined
+ * DMA program.
+ */
+
+ void *GeneratedDmaProg; /**< The DMA program genreated
+ * by the driver. This field will be
+ * set if a user invokes the DMA
+ * program generation function. Or
+ * the DMA command is finished and
+ * a user informs the driver not to
+ * release the program buffer.
+ * This field has two purposes, one
+ * is to ask the driver to generate
+ * a DMA program while the DMAC is
+ * performaning DMA transactions. The
+ * other purpose is to debug the
+ * driver.
+ */
+ int GeneratedDmaProgLength; /**< The length of the DMA program
+ * generated by the driver
+ */
+ int DmaStatus; /**< 0 on success, otherwise error code
+ */
+ u32 ChanFaultType; /**< Channel fault type in case of fault
+ */
+ u32 ChanFaultPCAddr; /**< Channel fault PC address
+ */
+} XDmaPs_Cmd;
+
+/**
+ * It's the done handler a user can set for a channel
+ */
+typedef void (*XDmaPsDoneHandler) (unsigned int Channel,
+ XDmaPs_Cmd *DmaCmd,
+ void *CallbackRef);
+
+/**
+ * It's the fault handler a user can set for a channel
+ */
+typedef void (*XDmaPsFaultHandler) (unsigned int Channel,
+ XDmaPs_Cmd *DmaCmd,
+ void *CallbackRef);
+
+#define XDMAPS_MAX_CHAN_BUFS 2
+#define XDMAPS_CHAN_BUF_LEN 128
+
+/**
+ * The XDmaPs_ProgBuf is the struct for a DMA program buffer.
+ */
+typedef struct {
+ char Buf[XDMAPS_CHAN_BUF_LEN]; /**< The actual buffer the holds the
+ * content */
+ unsigned Len; /**< The actual length of the DMA
+ * program in bytes. */
+ int Allocated; /**< A tag indicating whether the
+ * buffer is allocated or not */
+} XDmaPs_ProgBuf;
+
+/**
+ * The XDmaPs_ChannelData is a struct to book keep individual channel of
+ * the DMAC.
+ */
+typedef struct {
+ unsigned DevId; /**< Device id indicating which DMAC */
+ unsigned ChanId; /**< Channel number of the DMAC */
+ XDmaPs_ProgBuf ProgBufPool[XDMAPS_MAX_CHAN_BUFS]; /**< A pool of
+ program buffers*/
+ XDmaPsDoneHandler DoneHandler; /**< Done interrupt handler */
+ void *DoneRef; /**< Done interrupt callback data */
+ XDmaPs_Cmd *DmaCmdToHw; /**< DMA command being executed */
+ XDmaPs_Cmd *DmaCmdFromHw; /**< DMA command that is finished.
+ * This field is for debugging purpose
+ */
+ int HoldDmaProg; /**< A tag indicating whether to hold the
+ * DMA program after the DMA is done.
+ */
+
+} XDmaPs_ChannelData;
+
+/**
+ * The XDmaPs driver instance data structure. A pointer to an instance data
+ * structure is passed around by functions to refer to a specific driver
+ * instance.
+ */
+typedef struct {
+ XDmaPs_Config Config; /**< Configuration data structure */
+ int IsReady; /**< Device is Ready */
+ int CacheLength; /**< icache length */
+ XDmaPsFaultHandler FaultHandler; /**< fault interrupt handler */
+ void *FaultRef; /**< fault call back data */
+ XDmaPs_ChannelData Chans[XDMAPS_CHANNELS_PER_DEV];
+ /**<
+ * channel data
+ */
+} XDmaPs;
+
+/*
+ * Functions implemented in xdmaps.c
+ */
+int XDmaPs_CfgInitialize(XDmaPs *InstPtr,
+ XDmaPs_Config *Config,
+ u32 EffectiveAddr);
+
+int XDmaPs_Start(XDmaPs *InstPtr, unsigned int Channel,
+ XDmaPs_Cmd *Cmd,
+ int HoldDmaProg);
+
+int XDmaPs_IsActive(XDmaPs *InstPtr, unsigned int Channel);
+int XDmaPs_GenDmaProg(XDmaPs *InstPtr, unsigned int Channel,
+ XDmaPs_Cmd *Cmd);
+int XDmaPs_FreeDmaProg(XDmaPs *InstPtr, unsigned int Channel,
+ XDmaPs_Cmd *Cmd);
+void XDmaPs_Print_DmaProg(XDmaPs_Cmd *Cmd);
+
+
+int XDmaPs_ResetManager(XDmaPs *InstPtr);
+int XDmaPs_ResetChannel(XDmaPs *InstPtr, unsigned int Channel);
+
+
+int XDmaPs_SetDoneHandler(XDmaPs *InstPtr,
+ unsigned Channel,
+ XDmaPsDoneHandler DoneHandler,
+ void *CallbackRef);
+
+int XDmaPs_SetFaultHandler(XDmaPs *InstPtr,
+ XDmaPsFaultHandler FaultHandler,
+ void *CallbackRef);
+
+void XDmaPs_Print_DmaProg(XDmaPs_Cmd *Cmd);
+int XDmaPs_Instr_DMARMB(char *DmaProg);
+int XDmaPs_Instr_DMAWMB(char *DmaProg);
+
+/**
+ * To avoid linking error,Declare all inline functions as extern for
+ * IAR compiler
+ */
+#ifdef __ICCARM__
+extern INLINE int XDmaPs_Instr_DMAEND(char *DmaProg);
+extern INLINE void XDmaPs_Memcpy4(char *Dst, char *Src);
+extern INLINE int XDmaPs_Instr_DMAGO(char *DmaProg, unsigned int Cn,
+ u32 Imm, unsigned int Ns);
+extern INLINE int XDmaPs_Instr_DMALD(char *DmaProg);
+extern INLINE int XDmaPs_Instr_DMALP(char *DmaProg, unsigned Lc,
+ unsigned LoopIterations);
+extern INLINE int XDmaPs_Instr_DMALPEND(char *DmaProg, char *BodyStart, unsigned Lc);
+extern INLINE int XDmaPs_Instr_DMAMOV(char *DmaProg, unsigned Rd, u32 Imm);
+extern INLINE int XDmaPs_Instr_DMANOP(char *DmaProg);
+extern INLINE int XDmaPs_Instr_DMASEV(char *DmaProg, unsigned int EventNumber);
+extern INLINE int XDmaPs_Instr_DMAST(char *DmaProg);
+extern INLINE unsigned XDmaPs_ToEndianSwapSizeBits(unsigned int EndianSwapSize);
+extern INLINE unsigned XDmaPs_ToBurstSizeBits(unsigned BurstSize);
+#endif
+
+/**
+ * Driver done interrupt service routines for the channels.
+ * We need this done ISR mainly because the driver needs to release the
+ * DMA program buffer. This is the one that connects the GIC
+ */
+void XDmaPs_DoneISR_0(XDmaPs *InstPtr);
+void XDmaPs_DoneISR_1(XDmaPs *InstPtr);
+void XDmaPs_DoneISR_2(XDmaPs *InstPtr);
+void XDmaPs_DoneISR_3(XDmaPs *InstPtr);
+void XDmaPs_DoneISR_4(XDmaPs *InstPtr);
+void XDmaPs_DoneISR_5(XDmaPs *InstPtr);
+void XDmaPs_DoneISR_6(XDmaPs *InstPtr);
+void XDmaPs_DoneISR_7(XDmaPs *InstPtr);
+
+/**
+ * Driver fault interrupt service routine
+ */
+void XDmaPs_FaultISR(XDmaPs *InstPtr);
+
+
+/*
+ * Static loopup function implemented in xdmaps_sinit.c
+ */
+XDmaPs_Config *XDmaPs_LookupConfig(u16 DeviceId);
+
+
+/*
+ * self-test functions in xdmaps_selftest.c
+ */
+int XDmaPs_SelfTest(XDmaPs *InstPtr);
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* end of protection macro */
+/** @} */
diff --git a/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/include/xdmaps_hw.h b/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/include/xdmaps_hw.h
new file mode 100644
index 0000000..d901a94
--- /dev/null
+++ b/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/include/xdmaps_hw.h
@@ -0,0 +1,287 @@
+/******************************************************************************
+*
+* Copyright (C) 2009 - 2019 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+* THE SOFTWARE.
+*
+*
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xdmaps_hw.h
+* @addtogroup dmaps_v2_5
+* @{
+*
+* This header file contains the hardware interface of an XDmaPs device.
+*
+* <pre>
+* MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ----- ---- -------- ----------------------------------------------
+* 1.00a hbm 08/18/10 First Release
+* 1.01a nm 12/20/12 Added definition XDMAPS_CHANNELS_PER_DEV which specifies
+* the maximum number of channels.
+* Replaced the usage of XPAR_XDMAPS_CHANNELS_PER_DEV
+* with XDMAPS_CHANNELS_PER_DEV defined in xdmaps_hw.h
+* 1.02a sg 05/16/12 Made changes for doxygen
+* 1.06a kpc 07/10/13 Added function prototype
+* </pre>
+*
+******************************************************************************/
+
+#ifndef XDMAPS_HW_H /* prevent circular inclusions */
+#define XDMAPS_HW_H /* by using protection macros */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/***************************** Include Files *********************************/
+
+#include "xil_types.h"
+#include "xil_assert.h"
+#include "xil_io.h"
+
+/************************** Constant Definitions *****************************/
+
+/** @name Register Map
+ *
+ * Register offsets for the DMAC.
+ * @{
+ */
+
+#define XDMAPS_DS_OFFSET 0x000 /* DMA Status Register */
+#define XDMAPS_DPC_OFFSET 0x004 /* DMA Program Counter Rregister */
+#define XDMAPS_INTEN_OFFSET 0X020 /* DMA Interrupt Enable Register */
+#define XDMAPS_ES_OFFSET 0x024 /* DMA Event Status Register */
+#define XDMAPS_INTSTATUS_OFFSET 0x028 /* DMA Interrupt Status Register
+ */
+#define XDMAPS_INTCLR_OFFSET 0x02c /* DMA Interrupt Clear Register */
+#define XDMAPS_FSM_OFFSET 0x030 /* DMA Fault Status DMA Manager
+ * Register
+ */
+#define XDMAPS_FSC_OFFSET 0x034 /* DMA Fault Status DMA Chanel Register
+ */
+#define XDMAPS_FTM_OFFSET 0x038 /* DMA Fault Type DMA Manager Register */
+
+#define XDMAPS_FTC0_OFFSET 0x040 /* DMA Fault Type for DMA Channel 0 */
+/*
+ * The offset for the rest of the FTC registers is calculated as
+ * FTC0 + dev_chan_num * 4
+ */
+#define XDmaPs_FTCn_OFFSET(ch) (XDMAPS_FTC0_OFFSET + (ch) * 4)
+
+#define XDMAPS_CS0_OFFSET 0x100 /* Channel Status for DMA Channel 0 */
+/*
+ * The offset for the rest of the CS registers is calculated as
+ * CS0 + * dev_chan_num * 0x08
+ */
+#define XDmaPs_CSn_OFFSET(ch) (XDMAPS_CS0_OFFSET + (ch) * 8)
+
+#define XDMAPS_CPC0_OFFSET 0x104 /* Channel Program Counter for DMA
+ * Channel 0
+ */
+/*
+ * The offset for the rest of the CPC registers is calculated as
+ * CPC0 + dev_chan_num * 0x08
+ */
+#define XDmaPs_CPCn_OFFSET(ch) (XDMAPS_CPC0_OFFSET + (ch) * 8)
+
+#define XDMAPS_SA_0_OFFSET 0x400 /* Source Address Register for DMA
+ * Channel 0
+ */
+/* The offset for the rest of the SA registers is calculated as
+ * SA_0 + dev_chan_num * 0x20
+ */
+#define XDmaPs_SA_n_OFFSET(ch) (XDMAPS_SA_0_OFFSET + (ch) * 0x20)
+
+#define XDMAPS_DA_0_OFFSET 0x404 /* Destination Address Register for
+ * DMA Channel 0
+ */
+/* The offset for the rest of the DA registers is calculated as
+ * DA_0 + dev_chan_num * 0x20
+ */
+#define XDmaPs_DA_n_OFFSET(ch) (XDMAPS_DA_0_OFFSET + (ch) * 0x20)
+
+#define XDMAPS_CC_0_OFFSET 0x408 /* Channel Control Register for
+ * DMA Channel 0
+ */
+/*
+ * The offset for the rest of the CC registers is calculated as
+ * CC_0 + dev_chan_num * 0x20
+ */
+#define XDmaPs_CC_n_OFFSET(ch) (XDMAPS_CC_0_OFFSET + (ch) * 0x20)
+
+#define XDMAPS_LC0_0_OFFSET 0x40C /* Loop Counter 0 for DMA Channel 0 */
+/*
+ * The offset for the rest of the LC0 registers is calculated as
+ * LC_0 + dev_chan_num * 0x20
+ */
+#define XDmaPs_LC0_n_OFFSET(ch) (XDMAPS_LC0_0_OFFSET + (ch) * 0x20)
+#define XDMAPS_LC1_0_OFFSET 0x410 /* Loop Counter 1 for DMA Channel 0 */
+/*
+ * The offset for the rest of the LC1 registers is calculated as
+ * LC_0 + dev_chan_num * 0x20
+ */
+#define XDmaPs_LC1_n_OFFSET(ch) (XDMAPS_LC1_0_OFFSET + (ch) * 0x20)
+
+#define XDMAPS_DBGSTATUS_OFFSET 0xD00 /* Debug Status Register */
+#define XDMAPS_DBGCMD_OFFSET 0xD04 /* Debug Command Register */
+#define XDMAPS_DBGINST0_OFFSET 0xD08 /* Debug Instruction 0 Register */
+#define XDMAPS_DBGINST1_OFFSET 0xD0C /* Debug Instruction 1 Register */
+
+#define XDMAPS_CR0_OFFSET 0xE00 /* Configuration Register 0 */
+#define XDMAPS_CR1_OFFSET 0xE04 /* Configuration Register 1 */
+#define XDMAPS_CR2_OFFSET 0xE08 /* Configuration Register 2 */
+#define XDMAPS_CR3_OFFSET 0xE0C /* Configuration Register 3 */
+#define XDMAPS_CR4_OFFSET 0xE10 /* Configuration Register 4 */
+#define XDMAPS_CRDN_OFFSET 0xE14 /* Configuration Register Dn */
+
+#define XDMAPS_PERIPH_ID_0_OFFSET 0xFE0 /* Peripheral Identification
+ * Register 0
+ */
+#define XDMAPS_PERIPH_ID_1_OFFSET 0xFE4 /* Peripheral Identification
+ * Register 1
+ */
+#define XDMAPS_PERIPH_ID_2_OFFSET 0xFE8 /* Peripheral Identification
+ * Register 2
+ */
+#define XDMAPS_PERIPH_ID_3_OFFSET 0xFEC /* Peripheral Identification
+ * Register 3
+ */
+#define XDMAPS_PCELL_ID_0_OFFSET 0xFF0 /* PrimeCell Identification
+ * Register 0
+ */
+#define XDMAPS_PCELL_ID_1_OFFSET 0xFF4 /* PrimeCell Identification
+ * Register 1
+ */
+#define XDMAPS_PCELL_ID_2_OFFSET 0xFF8 /* PrimeCell Identification
+ * Register 2
+ */
+#define XDMAPS_PCELL_ID_3_OFFSET 0xFFC /* PrimeCell Identification
+ * Register 3
+ */
+
+/*
+ * Some useful register masks
+ */
+#define XDMAPS_DS_DMA_STATUS 0x0F /* DMA status mask */
+#define XDMAPS_DS_DMA_STATUS_STOPPED 0x00 /* debug status busy mask */
+
+#define XDMAPS_DBGSTATUS_BUSY 0x01 /* debug status busy mask */
+
+#define XDMAPS_CS_ACTIVE_MASK 0x07 /* channel status active mask,
+ * llast 3 bits of CS register
+ */
+
+#define XDMAPS_CR1_I_CACHE_LEN_MASK 0x07 /* i_cache_len mask */
+
+
+/*
+ * XDMAPS_DBGINST0 - constructs the word for the Debug Instruction-0 Register.
+ * @b1: Instruction byte 1
+ * @b0: Instruction byte 0
+ * @ch: Channel number
+ * @dbg_th: Debug thread encoding: 0 = DMA manager thread, 1 = DMA channel
+ */
+#define XDmaPs_DBGINST0(b1, b0, ch, dbg_th) \
+ (((b1) << 24) | ((b0) << 16) | (((ch) & 0x7) << 8) | ((dbg_th & 0x1)))
+
+/* @} */
+
+/** @name Control Register
+ *
+ * The Control register (CR) controls the major functions of the device.
+ *
+ * Control Register Bit Definition
+ */
+
+/* @}*/
+
+
+#define XDMAPS_CHANNELS_PER_DEV 8
+
+
+/** @name Mode Register
+ *
+ * The mode register (MR) defines the mode of transfer as well as the data
+ * format. If this register is modified during transmission or reception,
+ * data validity cannot be guaranteed.
+ *
+ * Mode Register Bit Definition
+ * @{
+ */
+
+/* @} */
+
+
+/** @name Interrupt Registers
+ *
+ * Interrupt control logic uses the interrupt enable register (IER) and the
+ * interrupt disable register (IDR) to set the value of the bits in the
+ * interrupt mask register (IMR). The IMR determines whether to pass an
+ * interrupt to the interrupt status register (ISR).
+ * Writing a 1 to IER Enbables an interrupt, writing a 1 to IDR disables an
+ * interrupt. IMR and ISR are read only, and IER and IDR are write only.
+ * Reading either IER or IDR returns 0x00.
+ *
+ * All four registers have the same bit definitions.
+ *
+ * @{
+ */
+
+/* @} */
+#define XDMAPS_INTCLR_ALL_MASK 0xFF
+
+#define XDmaPs_ReadReg(BaseAddress, RegOffset) \
+ Xil_In32((BaseAddress) + (RegOffset))
+
+/***************************************************************************/
+/**
+* Write a DMAC register.
+*
+* @param BaseAddress contains the base address of the device.
+* @param RegOffset contains the offset from the base address of the device.
+* @param RegisterValue is the value to be written to the register.
+*
+* @return None.
+*
+* @note
+* C-Style signature:
+* void XDmaPs_WriteReg(u32 BaseAddress, int RegOffset,
+* u32 RegisterValue)
+******************************************************************************/
+#define XDmaPs_WriteReg(BaseAddress, RegOffset, RegisterValue) \
+ Xil_Out32((BaseAddress) + (RegOffset), (RegisterValue))
+/************************** Variable Definitions *****************************/
+
+/************************** Function Prototypes *****************************/
+/*
+ * Perform reset operation to the dmaps interface
+ */
+void XDmaPs_ResetHw(u32 BaseAddr);
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* end of protection macro */
+/** @} */
diff --git a/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/include/xemacps.h b/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/include/xemacps.h
new file mode 100644
index 0000000..3943595
--- /dev/null
+++ b/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/include/xemacps.h
@@ -0,0 +1,849 @@
+/******************************************************************************
+*
+* Copyright (C) 2010 - 2019 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+* THE SOFTWARE.
+*
+*
+*
+******************************************************************************/
+/****************************************************************************/
+/**
+ *
+ * @file xemacps.h
+* @addtogroup emacps_v3_10
+* @{
+* @details
+ *
+ * The Xilinx Embedded Processor Block Ethernet driver.
+ *
+ * For a full description of XEMACPS features, please see the hardware spec.
+ * This driver supports the following features:
+ * - Memory mapped access to host interface registers
+ * - Statistics counter registers for RMON/MIB
+ * - API for interrupt driven frame transfers for hardware configured DMA
+ * - Virtual memory support
+ * - Unicast, broadcast, and multicast receive address filtering
+ * - Full and half duplex operation
+ * - Automatic PAD & FCS insertion and stripping
+ * - Flow control
+ * - Support up to four 48bit addresses
+ * - Address checking for four specific 48bit addresses
+ * - VLAN frame support
+ * - Pause frame support
+ * - Large frame support up to 1536 bytes
+ * - Checksum offload
+ *
+ * <b>Driver Description</b>
+ *
+ * The device driver enables higher layer software (e.g., an application) to
+ * communicate to the XEmacPs. The driver handles transmission and reception
+ * of Ethernet frames, as well as configuration and control. No pre or post
+ * processing of frame data is performed. The driver does not validate the
+ * contents of an incoming frame in addition to what has already occurred in
+ * hardware.
+ * A single device driver can support multiple devices even when those devices
+ * have significantly different configurations.
+ *
+ * <b>Initialization & Configuration</b>
+ *
+ * The XEmacPs_Config structure is used by the driver to configure itself.
+ * This configuration structure is typically created by the tool-chain based
+ * on hardware build properties.
+ *
+ * The driver instance can be initialized in
+ *
+ * - XEmacPs_CfgInitialize(InstancePtr, CfgPtr, EffectiveAddress): Uses a
+ * configuration structure provided by the caller. If running in a system
+ * with address translation, the provided virtual memory base address
+ * replaces the physical address present in the configuration structure.
+ *
+ * The device supports DMA only as current development plan. No FIFO mode is
+ * supported. The driver expects to start the DMA channels and expects that
+ * the user has set up the buffer descriptor lists.
+ *
+ * <b>Interrupts and Asynchronous Callbacks</b>
+ *
+ * The driver has no dependencies on the interrupt controller. When an
+ * interrupt occurs, the handler will perform a small amount of
+ * housekeeping work, determine the source of the interrupt, and call the
+ * appropriate callback function. All callbacks are registered by the user
+ * level application.
+ *
+ * <b>Virtual Memory</b>
+ *
+ * All virtual to physical memory mappings must occur prior to accessing the
+ * driver API.
+ *
+ * For DMA transactions, user buffers supplied to the driver must be in terms
+ * of their physical address.
+ *
+ * <b>DMA</b>
+ *
+ * The DMA engine uses buffer descriptors (BDs) to describe Ethernet frames.
+ * These BDs are typically chained together into a list the hardware follows
+ * when transferring data in and out of the packet buffers. Each BD describes
+ * a memory region containing either a full or partial Ethernet packet.
+ *
+ * Interrupt coalescing is not supported from this built-in DMA engine.
+ *
+ * This API requires the user to understand how the DMA operates. The
+ * following paragraphs provide some explanation, but the user is encouraged
+ * to read documentation in xemacps_bdring.h as well as study example code
+ * that accompanies this driver.
+ *
+ * The API is designed to get BDs to and from the DMA engine in the most
+ * efficient means possible. The first step is to establish a memory region
+ * to contain all BDs for a specific channel. This is done with
+ * XEmacPs_BdRingCreate(). This function sets up a BD ring that hardware will
+ * follow as BDs are processed. The ring will consist of a user defined number
+ * of BDs which will all be partially initialized. For example on the transmit
+ * channel, the driver will initialize all BDs' so that they are configured
+ * for transmit. The more fields that can be permanently setup at
+ * initialization, then the fewer accesses will be needed to each BD while
+ * the DMA engine is in operation resulting in better throughput and CPU
+ * utilization. The best case initialization would require the user to set
+ * only a frame buffer address and length prior to submitting the BD to the
+ * engine.
+ *
+ * BDs move through the engine with the help of functions
+ * XEmacPs_BdRingAlloc(), XEmacPs_BdRingToHw(), XEmacPs_BdRingFromHw(),
+ * and XEmacPs_BdRingFree().
+ * All these functions handle BDs that are in place. That is, there are no
+ * copies of BDs kept anywhere and any BD the user interacts with is an actual
+ * BD from the same ring hardware accesses.
+ *
+ * BDs in the ring go through a series of states as follows:
+ * 1. Idle. The driver controls BDs in this state.
+ * 2. The user has data to transfer. XEmacPs_BdRingAlloc() is called to
+ * reserve BD(s). Once allocated, the user may setup the BD(s) with
+ * frame buffer address, length, and other attributes. The user controls
+ * BDs in this state.
+ * 3. The user submits BDs to the DMA engine with XEmacPs_BdRingToHw. BDs
+ * in this state are either waiting to be processed by hardware, are in
+ * process, or have been processed. The DMA engine controls BDs in this
+ * state.
+ * 4. Processed BDs are retrieved with XEmacEpv_BdRingFromHw() by the
+ * user. Once retrieved, the user can examine each BD for the outcome of
+ * the DMA transfer. The user controls BDs in this state. After examining
+ * the BDs the user calls XEmacPs_BdRingFree() which places the BDs back
+ * into state 1.
+ *
+ * Each of the four BD accessor functions operate on a set of BDs. A set is
+ * defined as a segment of the BD ring consisting of one or more BDs. The user
+ * views the set as a pointer to the first BD along with the number of BDs for
+ * that set. The set can be navigated by using macros XEmacPs_BdNext(). The
+ * user must exercise extreme caution when changing BDs in a set as there is
+ * nothing to prevent doing a mBdNext past the end of the set and modifying a
+ * BD out of bounds.
+ *
+ * XEmacPs_BdRingAlloc() + XEmacPs_BdRingToHw(), as well as
+ * XEmacPs_BdRingFromHw() + XEmacPs_BdRingFree() are designed to be used in
+ * tandem. The same BD set retrieved with BdRingAlloc should be the same one
+ * provided to hardware with BdRingToHw. Same goes with BdRingFromHw and
+ * BdRIngFree.
+ *
+ * <b>Alignment & Data Cache Restrictions</b>
+ *
+ * Due to the design of the hardware, all RX buffers, BDs need to be 4-byte
+ * aligned. Please reference xemacps_bd.h for cache related macros.
+ *
+ * DMA Tx:
+ *
+ * - If frame buffers exist in cached memory, then they must be flushed
+ * prior to committing them to hardware.
+ *
+ * DMA Rx:
+ *
+ * - If frame buffers exist in cached memory, then the cache must be
+ * invalidated for the memory region containing the frame prior to data
+ * access
+ *
+ * Both cache invalidate/flush are taken care of in driver code.
+ *
+ * <b>Buffer Copying</b>
+ *
+ * The driver is designed for a zero-copy buffer scheme. That is, the driver
+ * will not copy buffers. This avoids potential throughput bottlenecks within
+ * the driver. If byte copying is required, then the transfer will take longer
+ * to complete.
+ *
+ * <b>Checksum Offloading</b>
+ *
+ * The Embedded Processor Block Ethernet can be configured to perform IP, TCP
+ * and UDP checksum offloading in both receive and transmit directions.
+ *
+ * IP packets contain a 16-bit checksum field, which is the 16-bit 1s
+ * complement of the 1s complement sum of all 16-bit words in the header.
+ * TCP and UDP packets contain a 16-bit checksum field, which is the 16-bit
+ * 1s complement of the 1s complement sum of all 16-bit words in the header,
+ * the data and a conceptual pseudo header.
+ *
+ * To calculate these checksums in software requires each byte of the packet
+ * to be read. For TCP and UDP this can use a large amount of processing power.
+ * Offloading the checksum calculation to hardware can result in significant
+ * performance improvements.
+ *
+ * The transmit checksum offload is only available to use DMA in packet buffer
+ * mode. This is because the complete frame to be transmitted must be read
+ * into the packet buffer memory before the checksum can be calculated and
+ * written to the header at the beginning of the frame.
+ *
+ * For IP, TCP or UDP receive checksum offload to be useful, the operating
+ * system containing the protocol stack must be aware that this offload is
+ * available so that it can make use of the fact that the hardware has verified
+ * the checksum.
+ *
+ * When receive checksum offloading is enabled in the hardware, the IP header
+ * checksum is checked, where the packet meets the following criteria:
+ *
+ * 1. If present, the VLAN header must be four octets long and the CFI bit
+ * must not be set.
+ * 2. Encapsulation must be RFC 894 Ethernet Type Encoding or RFC 1042 SNAP
+ * encoding.
+ * 3. IP v4 packet.
+ * 4. IP header is of a valid length.
+ * 5. Good IP header checksum.
+ * 6. No IP fragmentation.
+ * 7. TCP or UDP packet.
+ *
+ * When an IP, TCP or UDP frame is received, the receive buffer descriptor
+ * gives an indication if the hardware was able to verify the checksums.
+ * There is also an indication if the frame had SNAP encapsulation. These
+ * indication bits will replace the type ID match indication bits when the
+ * receive checksum offload is enabled.
+ *
+ * If any of the checksums are verified incorrect by the hardware, the packet
+ * is discarded and the appropriate statistics counter incremented.
+ *
+ * <b>PHY Interfaces</b>
+ *
+ * RGMII 1.3 is the only interface supported.
+ *
+ * <b>Asserts</b>
+ *
+ * Asserts are used within all Xilinx drivers to enforce constraints on
+ * parameters. Asserts can be turned off on a system-wide basis by defining,
+ * at compile time, the NDEBUG identifier. By default, asserts are turned on
+ * and it is recommended that users leave asserts on during development. For
+ * deployment use -DNDEBUG compiler switch to remove assert code.
+ *
+ * @note
+ *
+ * Xilinx drivers are typically composed of two parts, one is the driver
+ * and the other is the adapter. The driver is independent of OS and processor
+ * and is intended to be highly portable. The adapter is OS-specific and
+ * facilitates communication between the driver and an OS.
+ * This driver is intended to be RTOS and processor independent. Any needs for
+ * dynamic memory management, threads or thread mutual exclusion, or cache
+ * control must be satisfied bythe layer above this driver.
+ *
+ * <pre>
+ * MODIFICATION HISTORY:
+ *
+ * Ver Who Date Changes
+ * ----- ---- -------- -------------------------------------------------------
+ * 1.00a wsy 01/10/10 First release
+ * 1.00a asa 11/21/11 The function XEmacPs_BdRingFromHwTx in file
+ * xemacps_bdring.c is modified. Earlier it was checking for
+ * "BdLimit"(passed argument) number of BDs for finding out
+ * which BDs are successfully processed. Now one more check
+ * is added. It looks for BDs till the current BD pointer
+ * reaches HwTail. By doing this processing time is saved.
+ * 1.00a asa 01/24/12 The function XEmacPs_BdRingFromHwTx in file
+ * xemacps_bdring.c is modified. Now start of packet is
+ * searched for returning the number of BDs processed.
+ * 1.02a asa 11/05/12 Added a new API for deleting an entry from the HASH
+ * registers. Added a new API to set the bust length.
+ * Added some new hash-defines.
+ * 1.03a asa 01/23/12 Fix for CR #692702 which updates error handling for
+ * Rx errors. Under heavy Rx traffic, there will be a large
+ * number of errors related to receive buffer not available.
+ * Because of a HW bug (SI #692601), under such heavy errors,
+ * the Rx data path can become unresponsive. To reduce the
+ * probabilities for hitting this HW bug, the SW writes to
+ * bit 18 to flush a packet from Rx DPRAM immediately. The
+ * changes for it are done in the function
+ * XEmacPs_IntrHandler.
+ * 1.05a asa 09/23/13 Cache operations on BDs are not required and hence
+ * removed. It is expected that all BDs are allocated in
+ * from uncached area.
+ * 1.06a asa 11/02/13 Changed the value for XEMACPS_RXBUF_LEN_MASK from 0x3fff
+ * to 0x1fff. This fixes the CR#744902.
+ * Made changes in example file xemacps_example.h to fix compilation
+ * issues with iarcc compiler.
+ * 2.0 adk 10/12/13 Updated as per the New Tcl API's
+ * 2.1 adk 11/08/14 Fixed the CR#811288. Changes are made in the driver tcl file.
+ * 2.1 bss 09/08/14 Modified driver tcl to fix CR#820349 to export phy
+ * address in xparameters.h when GMII to RGMII converter
+ * is present in hw.
+ * 2.1 srt 07/15/14 Add support for Zynq Ultrascale Mp GEM specification and 64-bit
+ * changes.
+ * 2.2 adk 29/10/14 Fixed CR#827686 when PCS/PMA core is configured with
+ * 1000BASE-X mode export proper values to the xparameters.h
+ * file. Changes are made in the driver tcl file.
+ * 3.0 adk 08/1/15 Don't include gem in peripheral test when gem is
+ * configured with PCS/PMA Core. Changes are made in the
+ * test app tcl(CR:827686).
+ * 3.0 kvn 02/13/15 Modified code for MISRA-C:2012 compliance.
+ * 3.0 hk 03/18/15 Added support for jumbo frames. Increase AHB burst.
+ * Disable extended mode. Perform all 64 bit changes under
+ * check for arch64.
+ * Remove "used bit set" from TX error interrupt masks.
+ * 3.1 hk 07/27/15 Do not call error handler with '0' error code when
+ * there is no error. CR# 869403
+ * 08/10/15 Update upper 32 bit tx and rx queue ptr registers.
+ * 3.2 hk 02/22/16 Added SGMII support for Zynq Ultrascale+ MPSoC.
+ * 3.4 ms 01/23/17 Modified xil_printf statement in main function for all
+ * examples to ensure that "Successfully ran" and "Failed"
+ * strings are available in all examples. This is a fix
+ * for CR-965028.
+ * ms 03/17/17 Modified text file in examples folder for doxygen
+ * generation.
+ * ms 04/05/17 Added tabspace for return statements in functions of
+ * xemacps_ieee1588_example.c for proper documentation
+ * while generating doxygen.
+ * 3.5 hk 08/14/17 Update cache coherency information of the interface in
+ * its config structure.
+ * 3.6 rb 09/08/17 HwCnt variable (in XEmacPs_BdRing structure) is
+ * changed to volatile.
+ * Add API XEmacPs_BdRingPtrReset() to reset pointers
+ * 3.8 hk 07/19/18 Fixed CPP, GCC and doxygen warnings - CR-1006327
+ * hk 09/17/18 Fix PTP interrupt masks and cleanup comments.
+ * 3.9 hk 01/23/19 Add RX watermark support
+ *
+ * </pre>
+ *
+ ****************************************************************************/
+
+#ifndef XEMACPS_H /* prevent circular inclusions */
+#define XEMACPS_H /* by using protection macros */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/***************************** Include Files ********************************/
+
+#include "xil_types.h"
+#include "xil_assert.h"
+#include "xstatus.h"
+#include "xemacps_hw.h"
+#include "xemacps_bd.h"
+#include "xemacps_bdring.h"
+
+/************************** Constant Definitions ****************************/
+
+/*
+ * Device information
+ */
+#define XEMACPS_DEVICE_NAME "xemacps"
+#define XEMACPS_DEVICE_DESC "Xilinx PS 10/100/1000 MAC"
+
+
+/** @name Configuration options
+ *
+ * Device configuration options. See the XEmacPs_SetOptions(),
+ * XEmacPs_ClearOptions() and XEmacPs_GetOptions() for information on how to
+ * use options.
+ *
+ * The default state of the options are noted and are what the device and
+ * driver will be set to after calling XEmacPs_Reset() or
+ * XEmacPs_Initialize().
+ *
+ * @{
+ */
+
+#define XEMACPS_PROMISC_OPTION 0x00000001U
+/**< Accept all incoming packets.
+ * This option defaults to disabled (cleared) */
+
+#define XEMACPS_FRAME1536_OPTION 0x00000002U
+/**< Frame larger than 1516 support for Tx & Rx.
+ * This option defaults to disabled (cleared) */
+
+#define XEMACPS_VLAN_OPTION 0x00000004U
+/**< VLAN Rx & Tx frame support.
+ * This option defaults to disabled (cleared) */
+
+#define XEMACPS_FLOW_CONTROL_OPTION 0x00000010U
+/**< Enable recognition of flow control frames on Rx
+ * This option defaults to enabled (set) */
+
+#define XEMACPS_FCS_STRIP_OPTION 0x00000020U
+/**< Strip FCS and PAD from incoming frames. Note: PAD from VLAN frames is not
+ * stripped.
+ * This option defaults to enabled (set) */
+
+#define XEMACPS_FCS_INSERT_OPTION 0x00000040U
+/**< Generate FCS field and add PAD automatically for outgoing frames.
+ * This option defaults to disabled (cleared) */
+
+#define XEMACPS_LENTYPE_ERR_OPTION 0x00000080U
+/**< Enable Length/Type error checking for incoming frames. When this option is
+ * set, the MAC will filter frames that have a mismatched type/length field
+ * and if XEMACPS_REPORT_RXERR_OPTION is set, the user is notified when these
+ * types of frames are encountered. When this option is cleared, the MAC will
+ * allow these types of frames to be received.
+ *
+ * This option defaults to disabled (cleared) */
+
+#define XEMACPS_TRANSMITTER_ENABLE_OPTION 0x00000100U
+/**< Enable the transmitter.
+ * This option defaults to enabled (set) */
+
+#define XEMACPS_RECEIVER_ENABLE_OPTION 0x00000200U
+/**< Enable the receiver
+ * This option defaults to enabled (set) */
+
+#define XEMACPS_BROADCAST_OPTION 0x00000400U
+/**< Allow reception of the broadcast address
+ * This option defaults to enabled (set) */
+
+#define XEMACPS_MULTICAST_OPTION 0x00000800U
+/**< Allows reception of multicast addresses programmed into hash
+ * This option defaults to disabled (clear) */
+
+#define XEMACPS_RX_CHKSUM_ENABLE_OPTION 0x00001000U
+/**< Enable the RX checksum offload
+ * This option defaults to enabled (set) */
+
+#define XEMACPS_TX_CHKSUM_ENABLE_OPTION 0x00002000U
+/**< Enable the TX checksum offload
+ * This option defaults to enabled (set) */
+
+#define XEMACPS_JUMBO_ENABLE_OPTION 0x00004000U
+#define XEMACPS_SGMII_ENABLE_OPTION 0x00008000U
+
+#define XEMACPS_DEFAULT_OPTIONS \
+ ((u32)XEMACPS_FLOW_CONTROL_OPTION | \
+ (u32)XEMACPS_FCS_INSERT_OPTION | \
+ (u32)XEMACPS_FCS_STRIP_OPTION | \
+ (u32)XEMACPS_BROADCAST_OPTION | \
+ (u32)XEMACPS_LENTYPE_ERR_OPTION | \
+ (u32)XEMACPS_TRANSMITTER_ENABLE_OPTION | \
+ (u32)XEMACPS_RECEIVER_ENABLE_OPTION | \
+ (u32)XEMACPS_RX_CHKSUM_ENABLE_OPTION | \
+ (u32)XEMACPS_TX_CHKSUM_ENABLE_OPTION)
+
+/**< Default options set when device is initialized or reset */
+/*@}*/
+
+/** @name Callback identifiers
+ *
+ * These constants are used as parameters to XEmacPs_SetHandler()
+ * @{
+ */
+#define XEMACPS_HANDLER_DMASEND 1U
+#define XEMACPS_HANDLER_DMARECV 2U
+#define XEMACPS_HANDLER_ERROR 3U
+/*@}*/
+
+/* Constants to determine the configuration of the hardware device. They are
+ * used to allow the driver to verify it can operate with the hardware.
+ */
+#define XEMACPS_MDIO_DIV_DFT MDC_DIV_32 /**< Default MDIO clock divisor */
+
+/* The next few constants help upper layers determine the size of memory
+ * pools used for Ethernet buffers and descriptor lists.
+ */
+#define XEMACPS_MAC_ADDR_SIZE 6U /* size of Ethernet header */
+
+#define XEMACPS_MTU 1500U /* max MTU size of Ethernet frame */
+#define XEMACPS_MTU_JUMBO 10240U /* max MTU size of jumbo frame */
+#define XEMACPS_HDR_SIZE 14U /* size of Ethernet header */
+#define XEMACPS_HDR_VLAN_SIZE 18U /* size of Ethernet header with VLAN */
+#define XEMACPS_TRL_SIZE 4U /* size of Ethernet trailer (FCS) */
+#define XEMACPS_MAX_FRAME_SIZE (XEMACPS_MTU + XEMACPS_HDR_SIZE + \
+ XEMACPS_TRL_SIZE)
+#define XEMACPS_MAX_VLAN_FRAME_SIZE (XEMACPS_MTU + XEMACPS_HDR_SIZE + \
+ XEMACPS_HDR_VLAN_SIZE + XEMACPS_TRL_SIZE)
+#define XEMACPS_MAX_VLAN_FRAME_SIZE_JUMBO (XEMACPS_MTU_JUMBO + XEMACPS_HDR_SIZE + \
+ XEMACPS_HDR_VLAN_SIZE + XEMACPS_TRL_SIZE)
+
+/* DMACR Bust length hash defines */
+
+#define XEMACPS_SINGLE_BURST 0x00000001
+#define XEMACPS_4BYTE_BURST 0x00000004
+#define XEMACPS_8BYTE_BURST 0x00000008
+#define XEMACPS_16BYTE_BURST 0x00000010
+
+
+/**************************** Type Definitions ******************************/
+/** @name Typedefs for callback functions
+ *
+ * These callbacks are invoked in interrupt context.
+ * @{
+ */
+/**
+ * Callback invoked when frame(s) have been sent or received in interrupt
+ * driven DMA mode. To set the send callback, invoke XEmacPs_SetHandler().
+ *
+ * @param CallBackRef is user data assigned when the callback was set.
+ *
+ * @note
+ * See xemacps_hw.h for bitmasks definitions and the device hardware spec for
+ * further information on their meaning.
+ *
+ */
+typedef void (*XEmacPs_Handler) (void *CallBackRef);
+
+/**
+ * Callback when an asynchronous error occurs. To set this callback, invoke
+ * XEmacPs_SetHandler() with XEMACPS_HANDLER_ERROR in the HandlerType
+ * parameter.
+ *
+ * @param CallBackRef is user data assigned when the callback was set.
+ * @param Direction defines either receive or transmit error(s) has occurred.
+ * @param ErrorWord definition varies with Direction
+ *
+ */
+typedef void (*XEmacPs_ErrHandler) (void *CallBackRef, u8 Direction,
+ u32 ErrorWord);
+
+/*@}*/
+
+/**
+ * This typedef contains configuration information for a device.
+ */
+typedef struct {
+ u16 DeviceId; /**< Unique ID of device */
+ UINTPTR BaseAddress;/**< Physical base address of IPIF registers */
+ u8 IsCacheCoherent; /**< Applicable only to A53 in EL1 mode;
+ * describes whether Cache Coherent or not */
+} XEmacPs_Config;
+
+
+/**
+ * The XEmacPs driver instance data. The user is required to allocate a
+ * structure of this type for every XEmacPs device in the system. A pointer
+ * to a structure of this type is then passed to the driver API functions.
+ */
+typedef struct XEmacPs_Instance {
+ XEmacPs_Config Config; /* Hardware configuration */
+ u32 IsStarted; /* Device is currently started */
+ u32 IsReady; /* Device is initialized and ready */
+ u32 Options; /* Current options word */
+
+ XEmacPs_BdRing TxBdRing; /* Transmit BD ring */
+ XEmacPs_BdRing RxBdRing; /* Receive BD ring */
+
+ XEmacPs_Handler SendHandler;
+ XEmacPs_Handler RecvHandler;
+ void *SendRef;
+ void *RecvRef;
+
+ XEmacPs_ErrHandler ErrorHandler;
+ void *ErrorRef;
+ u32 Version;
+ u32 RxBufMask;
+ u32 MaxMtuSize;
+ u32 MaxFrameSize;
+ u32 MaxVlanFrameSize;
+
+} XEmacPs;
+
+
+/***************** Macros (Inline Functions) Definitions ********************/
+
+/****************************************************************************/
+/**
+* Retrieve the Tx ring object. This object can be used in the various Ring
+* API functions.
+*
+* @param InstancePtr is the DMA channel to operate on.
+*
+* @return TxBdRing attribute
+*
+* @note
+* C-style signature:
+* XEmacPs_BdRing XEmacPs_GetTxRing(XEmacPs *InstancePtr)
+*
+*****************************************************************************/
+#define XEmacPs_GetTxRing(InstancePtr) ((InstancePtr)->TxBdRing)
+
+/****************************************************************************/
+/**
+* Retrieve the Rx ring object. This object can be used in the various Ring
+* API functions.
+*
+* @param InstancePtr is the DMA channel to operate on.
+*
+* @return RxBdRing attribute
+*
+* @note
+* C-style signature:
+* XEmacPs_BdRing XEmacPs_GetRxRing(XEmacPs *InstancePtr)
+*
+*****************************************************************************/
+#define XEmacPs_GetRxRing(InstancePtr) ((InstancePtr)->RxBdRing)
+
+/****************************************************************************/
+/**
+*
+* Enable interrupts specified in <i>Mask</i>. The corresponding interrupt for
+* each bit set to 1 in <i>Mask</i>, will be enabled.
+*
+* @param InstancePtr is a pointer to the instance to be worked on.
+* @param Mask contains a bit mask of interrupts to enable. The mask can
+* be formed using a set of bitwise or'd values.
+*
+* @note
+* The state of the transmitter and receiver are not modified by this function.
+* C-style signature
+* void XEmacPs_IntEnable(XEmacPs *InstancePtr, u32 Mask)
+*
+*****************************************************************************/
+#define XEmacPs_IntEnable(InstancePtr, Mask) \
+ XEmacPs_WriteReg((InstancePtr)->Config.BaseAddress, \
+ XEMACPS_IER_OFFSET, \
+ ((Mask) & XEMACPS_IXR_ALL_MASK));
+
+/****************************************************************************/
+/**
+*
+* Disable interrupts specified in <i>Mask</i>. The corresponding interrupt for
+* each bit set to 1 in <i>Mask</i>, will be enabled.
+*
+* @param InstancePtr is a pointer to the instance to be worked on.
+* @param Mask contains a bit mask of interrupts to disable. The mask can
+* be formed using a set of bitwise or'd values.
+*
+* @note
+* The state of the transmitter and receiver are not modified by this function.
+* C-style signature
+* void XEmacPs_IntDisable(XEmacPs *InstancePtr, u32 Mask)
+*
+*****************************************************************************/
+#define XEmacPs_IntDisable(InstancePtr, Mask) \
+ XEmacPs_WriteReg((InstancePtr)->Config.BaseAddress, \
+ XEMACPS_IDR_OFFSET, \
+ ((Mask) & XEMACPS_IXR_ALL_MASK));
+
+/****************************************************************************/
+/**
+*
+* Enable interrupts specified in <i>Mask</i>. The corresponding interrupt for
+* each bit set to 1 in <i>Mask</i>, will be enabled.
+*
+* @param InstancePtr is a pointer to the instance to be worked on.
+* @param Mask contains a bit mask of interrupts to enable. The mask can
+* be formed using a set of bitwise or'd values.
+*
+* @note
+* The state of the transmitter and receiver are not modified by this function.
+* C-style signature
+* void XEmacPs_IntQ1Enable(XEmacPs *InstancePtr, u32 Mask)
+*
+*****************************************************************************/
+#define XEmacPs_IntQ1Enable(InstancePtr, Mask) \
+ XEmacPs_WriteReg((InstancePtr)->Config.BaseAddress, \
+ XEMACPS_INTQ1_IER_OFFSET, \
+ ((Mask) & XEMACPS_INTQ1_IXR_ALL_MASK));
+
+/****************************************************************************/
+/**
+*
+* Disable interrupts specified in <i>Mask</i>. The corresponding interrupt for
+* each bit set to 1 in <i>Mask</i>, will be enabled.
+*
+* @param InstancePtr is a pointer to the instance to be worked on.
+* @param Mask contains a bit mask of interrupts to disable. The mask can
+* be formed using a set of bitwise or'd values.
+*
+* @note
+* The state of the transmitter and receiver are not modified by this function.
+* C-style signature
+* void XEmacPs_IntDisable(XEmacPs *InstancePtr, u32 Mask)
+*
+*****************************************************************************/
+#define XEmacPs_IntQ1Disable(InstancePtr, Mask) \
+ XEmacPs_WriteReg((InstancePtr)->Config.BaseAddress, \
+ XEMACPS_INTQ1_IDR_OFFSET, \
+ ((Mask) & XEMACPS_INTQ1_IXR_ALL_MASK));
+
+/****************************************************************************/
+/**
+*
+* This macro triggers trasmit circuit to send data currently in TX buffer(s).
+*
+* @param InstancePtr is a pointer to the XEmacPs instance to be worked on.
+*
+* @return
+*
+* @note
+*
+* Signature: void XEmacPs_Transmit(XEmacPs *InstancePtr)
+*
+*****************************************************************************/
+#define XEmacPs_Transmit(InstancePtr) \
+ XEmacPs_WriteReg((InstancePtr)->Config.BaseAddress, \
+ XEMACPS_NWCTRL_OFFSET, \
+ (XEmacPs_ReadReg((InstancePtr)->Config.BaseAddress, \
+ XEMACPS_NWCTRL_OFFSET) | XEMACPS_NWCTRL_STARTTX_MASK))
+
+/****************************************************************************/
+/**
+*
+* This macro determines if the device is configured with checksum offloading
+* on the receive channel
+*
+* @param InstancePtr is a pointer to the XEmacPs instance to be worked on.
+*
+* @return
+*
+* Boolean TRUE if the device is configured with checksum offloading, or
+* FALSE otherwise.
+*
+* @note
+*
+* Signature: u32 XEmacPs_IsRxCsum(XEmacPs *InstancePtr)
+*
+*****************************************************************************/
+#define XEmacPs_IsRxCsum(InstancePtr) \
+ ((XEmacPs_ReadReg((InstancePtr)->Config.BaseAddress, \
+ XEMACPS_NWCFG_OFFSET) & XEMACPS_NWCFG_RXCHKSUMEN_MASK) != 0U \
+ ? TRUE : FALSE)
+
+/****************************************************************************/
+/**
+*
+* This macro determines if the device is configured with checksum offloading
+* on the transmit channel
+*
+* @param InstancePtr is a pointer to the XEmacPs instance to be worked on.
+*
+* @return
+*
+* Boolean TRUE if the device is configured with checksum offloading, or
+* FALSE otherwise.
+*
+* @note
+*
+* Signature: u32 XEmacPs_IsTxCsum(XEmacPs *InstancePtr)
+*
+*****************************************************************************/
+#define XEmacPs_IsTxCsum(InstancePtr) \
+ ((XEmacPs_ReadReg((InstancePtr)->Config.BaseAddress, \
+ XEMACPS_DMACR_OFFSET) & XEMACPS_DMACR_TCPCKSUM_MASK) != 0U \
+ ? TRUE : FALSE)
+
+/************************** Function Prototypes *****************************/
+
+/****************************************************************************/
+/**
+*
+* This macro sets RX watermark register.
+*
+* @param InstancePtr is a pointer to the XEmacPs instance to be worked on.
+* @param High is the non-zero RX high watermark value. When SRAM fill level
+* is above this, a pause frame will be sent.
+* @param Low is the non-zero RX low watermark value. When SRAM fill level
+* is below this, a zero length pause frame will be sent IF the last
+* pause frame sent was non-zero.
+*
+* @return None
+*
+* @note
+*
+* Signature: void XEmacPs_SetRXWatermark(XEmacPs *InstancePtr, u16 High,
+* u16 Low)
+*
+*****************************************************************************/
+#define XEmacPs_SetRXWatermark(InstancePtr, High, Low) \
+ XEmacPs_WriteReg((InstancePtr)->Config.BaseAddress, \
+ XEMACPS_RXWATERMARK_OFFSET, \
+ (High & XEMACPS_RXWM_HIGH_MASK) | \
+ ((Low << XEMACPS_RXWM_LOW_SHFT_MSK) & XEMACPS_RXWM_LOW_MASK) |)
+
+/****************************************************************************/
+/**
+*
+* This macro gets RX watermark register.
+*
+* @param InstancePtr is a pointer to the XEmacPs instance to be worked on.
+*
+* @return RX watermark register value
+*
+* @note
+*
+* Signature: void XEmacPs_GetRXWatermark(XEmacPs *InstancePtr)
+*
+*****************************************************************************/
+#define XEmacPs_GetRXWatermark(InstancePtr) \
+ XEmacPs_ReadReg((InstancePtr)->Config.BaseAddress, \
+ XEMACPS_RXWATERMARK_OFFSET)
+/*
+ * Initialization functions in xemacps.c
+ */
+LONG XEmacPs_CfgInitialize(XEmacPs *InstancePtr, XEmacPs_Config *CfgPtr,
+ UINTPTR EffectiveAddress);
+void XEmacPs_Start(XEmacPs *InstancePtr);
+void XEmacPs_Stop(XEmacPs *InstancePtr);
+void XEmacPs_Reset(XEmacPs *InstancePtr);
+void XEmacPs_SetQueuePtr(XEmacPs *InstancePtr, UINTPTR QPtr, u8 QueueNum,
+ u16 Direction);
+
+/*
+ * Lookup configuration in xemacps_sinit.c
+ */
+XEmacPs_Config *XEmacPs_LookupConfig(u16 DeviceId);
+
+/*
+ * Interrupt-related functions in xemacps_intr.c
+ * DMA only and FIFO is not supported. This DMA does not support coalescing.
+ */
+LONG XEmacPs_SetHandler(XEmacPs *InstancePtr, u32 HandlerType,
+ void *FuncPointer, void *CallBackRef);
+void XEmacPs_IntrHandler(void *XEmacPsPtr);
+
+/*
+ * MAC configuration/control functions in XEmacPs_control.c
+ */
+LONG XEmacPs_SetOptions(XEmacPs *InstancePtr, u32 Options);
+LONG XEmacPs_ClearOptions(XEmacPs *InstancePtr, u32 Options);
+u32 XEmacPs_GetOptions(XEmacPs *InstancePtr);
+
+LONG XEmacPs_SetMacAddress(XEmacPs *InstancePtr, void *AddressPtr, u8 Index);
+LONG XEmacPs_DeleteHash(XEmacPs *InstancePtr, void *AddressPtr);
+void XEmacPs_GetMacAddress(XEmacPs *InstancePtr, void *AddressPtr, u8 Index);
+
+LONG XEmacPs_SetHash(XEmacPs *InstancePtr, void *AddressPtr);
+void XEmacPs_ClearHash(XEmacPs *InstancePtr);
+void XEmacPs_GetHash(XEmacPs *InstancePtr, void *AddressPtr);
+
+void XEmacPs_SetMdioDivisor(XEmacPs *InstancePtr,
+ XEmacPs_MdcDiv Divisor);
+void XEmacPs_SetOperatingSpeed(XEmacPs *InstancePtr, u16 Speed);
+u16 XEmacPs_GetOperatingSpeed(XEmacPs *InstancePtr);
+LONG XEmacPs_PhyRead(XEmacPs *InstancePtr, u32 PhyAddress,
+ u32 RegisterNum, u16 *PhyDataPtr);
+LONG XEmacPs_PhyWrite(XEmacPs *InstancePtr, u32 PhyAddress,
+ u32 RegisterNum, u16 PhyData);
+LONG XEmacPs_SetTypeIdCheck(XEmacPs *InstancePtr, u32 Id_Check, u8 Index);
+
+LONG XEmacPs_SendPausePacket(XEmacPs *InstancePtr);
+void XEmacPs_DMABLengthUpdate(XEmacPs *InstancePtr, s32 BLength);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* end of protection macro */
+/** @} */
diff --git a/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/include/xemacps_bd.h b/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/include/xemacps_bd.h
new file mode 100644
index 0000000..452d484
--- /dev/null
+++ b/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/include/xemacps_bd.h
@@ -0,0 +1,782 @@
+/******************************************************************************
+*
+* Copyright (C) 2010 - 2019 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+* THE SOFTWARE.
+*
+*
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+ *
+ * @file xemacps_bd.h
+* @addtogroup emacps_v3_10
+* @{
+ *
+ * This header provides operations to manage buffer descriptors in support
+ * of scatter-gather DMA.
+ *
+ * The API exported by this header defines abstracted macros that allow the
+ * user to read/write specific BD fields.
+ *
+ * <b>Buffer Descriptors</b>
+ *
+ * A buffer descriptor (BD) defines a DMA transaction. The macros defined by
+ * this header file allow access to most fields within a BD to tailor a DMA
+ * transaction according to user and hardware requirements. See the hardware
+ * IP DMA spec for more information on BD fields and how they affect transfers.
+ *
+ * The XEmacPs_Bd structure defines a BD. The organization of this structure
+ * is driven mainly by the hardware for use in scatter-gather DMA transfers.
+ *
+ * <b>Performance</b>
+ *
+ * Limiting I/O to BDs can improve overall performance of the DMA channel.
+ *
+ * <pre>
+ * MODIFICATION HISTORY:
+ *
+ * Ver Who Date Changes
+ * ----- ---- -------- -------------------------------------------------------
+ * 1.00a wsy 01/10/10 First release
+ * 2.1 srt 07/15/14 Add support for Zynq Ultrascale MP GEM specification
+ * and 64-bit changes.
+ * 3.0 kvn 02/13/15 Modified code for MISRA-C:2012 compliance.
+ * 3.0 hk 02/20/15 Added support for jumbo frames.
+ * Disable extended mode. Perform all 64 bit changes under
+ * check for arch64.
+ * 3.2 hk 11/18/15 Change BD typedef and number of words.
+ * 3.8 hk 08/18/18 Remove duplicate definition of XEmacPs_BdSetLength
+ * 3.8 mus 11/05/18 Support 64 bit DMA addresses for Microblaze-X platform.
+ *
+ * </pre>
+ *
+ * ***************************************************************************
+ */
+
+#ifndef XEMACPS_BD_H /* prevent circular inclusions */
+#define XEMACPS_BD_H /* by using protection macros */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/***************************** Include Files *********************************/
+
+#include <string.h>
+#include "xil_types.h"
+#include "xil_assert.h"
+
+/************************** Constant Definitions *****************************/
+
+/**************************** Type Definitions *******************************/
+#ifdef __aarch64__
+/* Minimum BD alignment */
+#define XEMACPS_DMABD_MINIMUM_ALIGNMENT 64U
+#define XEMACPS_BD_NUM_WORDS 4U
+#else
+/* Minimum BD alignment */
+#define XEMACPS_DMABD_MINIMUM_ALIGNMENT 4U
+#define XEMACPS_BD_NUM_WORDS 2U
+#endif
+
+/**
+ * The XEmacPs_Bd is the type for buffer descriptors (BDs).
+ */
+typedef u32 XEmacPs_Bd[XEMACPS_BD_NUM_WORDS];
+
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/*****************************************************************************/
+/**
+ * Zero out BD fields
+ *
+ * @param BdPtr is the BD pointer to operate on
+ *
+ * @return Nothing
+ *
+ * @note
+ * C-style signature:
+ * void XEmacPs_BdClear(XEmacPs_Bd* BdPtr)
+ *
+ *****************************************************************************/
+#define XEmacPs_BdClear(BdPtr) \
+ memset((BdPtr), 0, sizeof(XEmacPs_Bd))
+
+/****************************************************************************/
+/**
+*
+* Read the given Buffer Descriptor word.
+*
+* @param BaseAddress is the base address of the BD to read
+* @param Offset is the word offset to be read
+*
+* @return The 32-bit value of the field
+*
+* @note
+* C-style signature:
+* u32 XEmacPs_BdRead(UINTPTR BaseAddress, UINTPTR Offset)
+*
+*****************************************************************************/
+#define XEmacPs_BdRead(BaseAddress, Offset) \
+ (*(u32 *)((UINTPTR)((void*)(BaseAddress)) + (u32)(Offset)))
+
+/****************************************************************************/
+/**
+*
+* Write the given Buffer Descriptor word.
+*
+* @param BaseAddress is the base address of the BD to write
+* @param Offset is the word offset to be written
+* @param Data is the 32-bit value to write to the field
+*
+* @return None.
+*
+* @note
+* C-style signature:
+* void XEmacPs_BdWrite(UINTPTR BaseAddress, UINTPTR Offset, UINTPTR Data)
+*
+*****************************************************************************/
+#define XEmacPs_BdWrite(BaseAddress, Offset, Data) \
+ (*(u32 *)((UINTPTR)(void*)(BaseAddress) + (u32)(Offset)) = (u32)(Data))
+
+/*****************************************************************************/
+/**
+ * Set the BD's Address field (word 0).
+ *
+ * @param BdPtr is the BD pointer to operate on
+ * @param Addr is the value to write to BD's status field.
+ *
+ * @note :
+ *
+ * C-style signature:
+ * void XEmacPs_BdSetAddressTx(XEmacPs_Bd* BdPtr, UINTPTR Addr)
+ *
+ *****************************************************************************/
+#if defined(__aarch64__) || defined(__arch64__)
+#define XEmacPs_BdSetAddressTx(BdPtr, Addr) \
+ XEmacPs_BdWrite((BdPtr), XEMACPS_BD_ADDR_OFFSET, \
+ (u32)((Addr) & ULONG64_LO_MASK)); \
+ XEmacPs_BdWrite((BdPtr), XEMACPS_BD_ADDR_HI_OFFSET, \
+ (u32)(((Addr) & ULONG64_HI_MASK) >> 32U));
+#else
+#define XEmacPs_BdSetAddressTx(BdPtr, Addr) \
+ XEmacPs_BdWrite((BdPtr), XEMACPS_BD_ADDR_OFFSET, (u32)(Addr))
+#endif
+
+/*****************************************************************************/
+/**
+ * Set the BD's Address field (word 0).
+ *
+ * @param BdPtr is the BD pointer to operate on
+ * @param Addr is the value to write to BD's status field.
+ *
+ * @note : Due to some bits are mixed within receive BD's address field,
+ * read-modify-write is performed.
+ *
+ * C-style signature:
+ * void XEmacPs_BdSetAddressRx(XEmacPs_Bd* BdPtr, UINTPTR Addr)
+ *
+ *****************************************************************************/
+#ifdef __aarch64__
+#define XEmacPs_BdSetAddressRx(BdPtr, Addr) \
+ XEmacPs_BdWrite((BdPtr), XEMACPS_BD_ADDR_OFFSET, \
+ ((XEmacPs_BdRead((BdPtr), XEMACPS_BD_ADDR_OFFSET) & \
+ ~XEMACPS_RXBUF_ADD_MASK) | ((u32)((Addr) & ULONG64_LO_MASK)))); \
+ XEmacPs_BdWrite((BdPtr), XEMACPS_BD_ADDR_HI_OFFSET, \
+ (u32)(((Addr) & ULONG64_HI_MASK) >> 32U));
+#else
+#define XEmacPs_BdSetAddressRx(BdPtr, Addr) \
+ XEmacPs_BdWrite((BdPtr), XEMACPS_BD_ADDR_OFFSET, \
+ ((XEmacPs_BdRead((BdPtr), XEMACPS_BD_ADDR_OFFSET) & \
+ ~XEMACPS_RXBUF_ADD_MASK) | (UINTPTR)(Addr)))
+#endif
+
+/*****************************************************************************/
+/**
+ * Set the BD's Status field (word 1).
+ *
+ * @param BdPtr is the BD pointer to operate on
+ * @param Data is the value to write to BD's status field.
+ *
+ * @note
+ * C-style signature:
+ * void XEmacPs_BdSetStatus(XEmacPs_Bd* BdPtr, UINTPTR Data)
+ *
+ *****************************************************************************/
+#define XEmacPs_BdSetStatus(BdPtr, Data) \
+ XEmacPs_BdWrite((BdPtr), XEMACPS_BD_STAT_OFFSET, \
+ XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) | (Data))
+
+
+/*****************************************************************************/
+/**
+ * Retrieve the BD's Packet DMA transfer status word (word 1).
+ *
+ * @param BdPtr is the BD pointer to operate on
+ *
+ * @return Status word
+ *
+ * @note
+ * C-style signature:
+ * u32 XEmacPs_BdGetStatus(XEmacPs_Bd* BdPtr)
+ *
+ * Due to the BD bit layout differences in transmit and receive. User's
+ * caution is required.
+ *****************************************************************************/
+#define XEmacPs_BdGetStatus(BdPtr) \
+ XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET)
+
+
+/*****************************************************************************/
+/**
+ * Get the address (bits 0..31) of the BD's buffer address (word 0)
+ *
+ * @param BdPtr is the BD pointer to operate on
+ *
+ * @note
+ * C-style signature:
+ * UINTPTR XEmacPs_BdGetBufAddr(XEmacPs_Bd* BdPtr)
+ *
+ *****************************************************************************/
+#if defined(__aarch64__) || defined(__arch64__)
+#define XEmacPs_BdGetBufAddr(BdPtr) \
+ (XEmacPs_BdRead((BdPtr), XEMACPS_BD_ADDR_OFFSET) | \
+ (XEmacPs_BdRead((BdPtr), XEMACPS_BD_ADDR_HI_OFFSET)) << 32U)
+#else
+#define XEmacPs_BdGetBufAddr(BdPtr) \
+ (XEmacPs_BdRead((BdPtr), XEMACPS_BD_ADDR_OFFSET))
+#endif
+
+/*****************************************************************************/
+/**
+ * Set transfer length in bytes for the given BD. The length must be set each
+ * time a BD is submitted to hardware.
+ *
+ * @param BdPtr is the BD pointer to operate on
+ * @param LenBytes is the number of bytes to transfer.
+ *
+ * @note
+ * C-style signature:
+ * void XEmacPs_BdSetLength(XEmacPs_Bd* BdPtr, u32 LenBytes)
+ *
+ *****************************************************************************/
+#define XEmacPs_BdSetLength(BdPtr, LenBytes) \
+ XEmacPs_BdWrite((BdPtr), XEMACPS_BD_STAT_OFFSET, \
+ ((XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) & \
+ ~XEMACPS_TXBUF_LEN_MASK) | (LenBytes)))
+
+
+/*****************************************************************************/
+/**
+ * Retrieve the BD length field.
+ *
+ * For Tx channels, the returned value is the same as that written with
+ * XEmacPs_BdSetLength().
+ *
+ * For Rx channels, the returned value is the size of the received packet.
+ *
+ * @param BdPtr is the BD pointer to operate on
+ *
+ * @return Length field processed by hardware or set by
+ * XEmacPs_BdSetLength().
+ *
+ * @note
+ * C-style signature:
+ * UINTPTR XEmacPs_BdGetLength(XEmacPs_Bd* BdPtr)
+ * XEAMCPS_RXBUF_LEN_MASK is same as XEMACPS_TXBUF_LEN_MASK.
+ *
+ *****************************************************************************/
+#define XEmacPs_BdGetLength(BdPtr) \
+ (XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) & \
+ XEMACPS_RXBUF_LEN_MASK)
+
+/*****************************************************************************/
+/**
+ * Retrieve the RX frame size.
+ *
+ * The returned value is the size of the received packet.
+ * This API supports jumbo frame sizes if enabled.
+ *
+ * @param InstancePtr is the pointer to XEmacps instance
+ *
+ * @param BdPtr is the BD pointer to operate on
+ *
+ * @return Length field processed by hardware or set by
+ * XEmacPs_BdSetLength().
+ *
+ * @note
+ * C-style signature:
+ * UINTPTR XEmacPs_GetRxFrameSize(XEmacPs* InstancePtr, XEmacPs_Bd* BdPtr)
+ * RxBufMask is dependent on whether jumbo is enabled or not.
+ *
+ *****************************************************************************/
+#define XEmacPs_GetRxFrameSize(InstancePtr, BdPtr) \
+ (XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) & \
+ (InstancePtr)->RxBufMask)
+
+/*****************************************************************************/
+/**
+ * Test whether the given BD has been marked as the last BD of a packet.
+ *
+ * @param BdPtr is the BD pointer to operate on
+ *
+ * @return TRUE if BD represents the "Last" BD of a packet, FALSE otherwise
+ *
+ * @note
+ * C-style signature:
+ * UINTPTR XEmacPs_BdIsLast(XEmacPs_Bd* BdPtr)
+ *
+ *****************************************************************************/
+#define XEmacPs_BdIsLast(BdPtr) \
+ ((XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) & \
+ XEMACPS_RXBUF_EOF_MASK)!=0U ? TRUE : FALSE)
+
+
+/*****************************************************************************/
+/**
+ * Tell the DMA engine that the given transmit BD marks the end of the current
+ * packet to be processed.
+ *
+ * @param BdPtr is the BD pointer to operate on
+ *
+ * @note
+ * C-style signature:
+ * void XEmacPs_BdSetLast(XEmacPs_Bd* BdPtr)
+ *
+ *****************************************************************************/
+#define XEmacPs_BdSetLast(BdPtr) \
+ (XEmacPs_BdWrite((BdPtr), XEMACPS_BD_STAT_OFFSET, \
+ XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) | \
+ XEMACPS_TXBUF_LAST_MASK))
+
+
+/*****************************************************************************/
+/**
+ * Tell the DMA engine that the current packet does not end with the given
+ * BD.
+ *
+ * @param BdPtr is the BD pointer to operate on
+ *
+ * @note
+ * C-style signature:
+ * void XEmacPs_BdClearLast(XEmacPs_Bd* BdPtr)
+ *
+ *****************************************************************************/
+#define XEmacPs_BdClearLast(BdPtr) \
+ (XEmacPs_BdWrite((BdPtr), XEMACPS_BD_STAT_OFFSET, \
+ XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) & \
+ ~XEMACPS_TXBUF_LAST_MASK))
+
+
+/*****************************************************************************/
+/**
+ * Set this bit to mark the last descriptor in the receive buffer descriptor
+ * list.
+ *
+ * @param BdPtr is the BD pointer to operate on
+ *
+ * @note
+ * C-style signature:
+ * void XEmacPs_BdSetRxWrap(XEmacPs_Bd* BdPtr)
+ *
+ *****************************************************************************/
+/*#define XEmacPs_BdSetRxWrap(BdPtr) \
+ (XEmacPs_BdWrite((BdPtr), XEMACPS_BD_ADDR_OFFSET, \
+ XEmacPs_BdRead((BdPtr), XEMACPS_BD_ADDR_OFFSET) | \
+ XEMACPS_RXBUF_WRAP_MASK))
+*/
+
+/*****************************************************************************/
+/**
+ * Determine the wrap bit of the receive BD which indicates end of the
+ * BD list.
+ *
+ * @param BdPtr is the BD pointer to operate on
+ *
+ * @note
+ * C-style signature:
+ * u8 XEmacPs_BdIsRxWrap(XEmacPs_Bd* BdPtr)
+ *
+ *****************************************************************************/
+#define XEmacPs_BdIsRxWrap(BdPtr) \
+ ((XEmacPs_BdRead((BdPtr), XEMACPS_BD_ADDR_OFFSET) & \
+ XEMACPS_RXBUF_WRAP_MASK)!=0U ? TRUE : FALSE)
+
+
+/*****************************************************************************/
+/**
+ * Sets this bit to mark the last descriptor in the transmit buffer
+ * descriptor list.
+ *
+ * @param BdPtr is the BD pointer to operate on
+ *
+ * @note
+ * C-style signature:
+ * void XEmacPs_BdSetTxWrap(XEmacPs_Bd* BdPtr)
+ *
+ *****************************************************************************/
+/*#define XEmacPs_BdSetTxWrap(BdPtr) \
+ (XEmacPs_BdWrite((BdPtr), XEMACPS_BD_STAT_OFFSET, \
+ XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) | \
+ XEMACPS_TXBUF_WRAP_MASK))
+*/
+
+/*****************************************************************************/
+/**
+ * Determine the wrap bit of the transmit BD which indicates end of the
+ * BD list.
+ *
+ * @param BdPtr is the BD pointer to operate on
+ *
+ * @note
+ * C-style signature:
+ * u8 XEmacPs_BdGetTxWrap(XEmacPs_Bd* BdPtr)
+ *
+ *****************************************************************************/
+#define XEmacPs_BdIsTxWrap(BdPtr) \
+ ((XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) & \
+ XEMACPS_TXBUF_WRAP_MASK)!=0U ? TRUE : FALSE)
+
+
+/*****************************************************************************/
+/*
+ * Must clear this bit to enable the MAC to write data to the receive
+ * buffer. Hardware sets this bit once it has successfully written a frame to
+ * memory. Once set, software has to clear the bit before the buffer can be
+ * used again. This macro clear the new bit of the receive BD.
+ *
+ * @param BdPtr is the BD pointer to operate on
+ *
+ * @note
+ * C-style signature:
+ * void XEmacPs_BdClearRxNew(XEmacPs_Bd* BdPtr)
+ *
+ *****************************************************************************/
+#define XEmacPs_BdClearRxNew(BdPtr) \
+ (XEmacPs_BdWrite((BdPtr), XEMACPS_BD_ADDR_OFFSET, \
+ XEmacPs_BdRead((BdPtr), XEMACPS_BD_ADDR_OFFSET) & \
+ ~XEMACPS_RXBUF_NEW_MASK))
+
+
+/*****************************************************************************/
+/**
+ * Determine the new bit of the receive BD.
+ *
+ * @param BdPtr is the BD pointer to operate on
+ *
+ * @note
+ * C-style signature:
+ * UINTPTR XEmacPs_BdIsRxNew(XEmacPs_Bd* BdPtr)
+ *
+ *****************************************************************************/
+#define XEmacPs_BdIsRxNew(BdPtr) \
+ ((XEmacPs_BdRead((BdPtr), XEMACPS_BD_ADDR_OFFSET) & \
+ XEMACPS_RXBUF_NEW_MASK)!=0U ? TRUE : FALSE)
+
+
+/*****************************************************************************/
+/**
+ * Software sets this bit to disable the buffer to be read by the hardware.
+ * Hardware sets this bit for the first buffer of a frame once it has been
+ * successfully transmitted. This macro sets this bit of transmit BD to avoid
+ * confusion.
+ *
+ * @param BdPtr is the BD pointer to operate on
+ *
+ * @note
+ * C-style signature:
+ * void XEmacPs_BdSetTxUsed(XEmacPs_Bd* BdPtr)
+ *
+ *****************************************************************************/
+#define XEmacPs_BdSetTxUsed(BdPtr) \
+ (XEmacPs_BdWrite((BdPtr), XEMACPS_BD_STAT_OFFSET, \
+ XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) | \
+ XEMACPS_TXBUF_USED_MASK))
+
+
+/*****************************************************************************/
+/**
+ * Software clears this bit to enable the buffer to be read by the hardware.
+ * Hardware sets this bit for the first buffer of a frame once it has been
+ * successfully transmitted. This macro clears this bit of transmit BD.
+ *
+ * @param BdPtr is the BD pointer to operate on
+ *
+ * @note
+ * C-style signature:
+ * void XEmacPs_BdClearTxUsed(XEmacPs_Bd* BdPtr)
+ *
+ *****************************************************************************/
+#define XEmacPs_BdClearTxUsed(BdPtr) \
+ (XEmacPs_BdWrite((BdPtr), XEMACPS_BD_STAT_OFFSET, \
+ XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) & \
+ ~XEMACPS_TXBUF_USED_MASK))
+
+
+/*****************************************************************************/
+/**
+ * Determine the used bit of the transmit BD.
+ *
+ * @param BdPtr is the BD pointer to operate on
+ *
+ * @note
+ * C-style signature:
+ * UINTPTR XEmacPs_BdIsTxUsed(XEmacPs_Bd* BdPtr)
+ *
+ *****************************************************************************/
+#define XEmacPs_BdIsTxUsed(BdPtr) \
+ ((XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) & \
+ XEMACPS_TXBUF_USED_MASK)!=0U ? TRUE : FALSE)
+
+
+/*****************************************************************************/
+/**
+ * Determine if a frame fails to be transmitted due to too many retries.
+ *
+ * @param BdPtr is the BD pointer to operate on
+ *
+ * @note
+ * C-style signature:
+ * UINTPTR XEmacPs_BdIsTxRetry(XEmacPs_Bd* BdPtr)
+ *
+ *****************************************************************************/
+#define XEmacPs_BdIsTxRetry(BdPtr) \
+ ((XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) & \
+ XEMACPS_TXBUF_RETRY_MASK)!=0U ? TRUE : FALSE)
+
+
+/*****************************************************************************/
+/**
+ * Determine if a frame fails to be transmitted due to data can not be
+ * feteched in time or buffers are exhausted.
+ *
+ * @param BdPtr is the BD pointer to operate on
+ *
+ * @note
+ * C-style signature:
+ * UINTPTR XEmacPs_BdIsTxUrun(XEmacPs_Bd* BdPtr)
+ *
+ *****************************************************************************/
+#define XEmacPs_BdIsTxUrun(BdPtr) \
+ ((XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) & \
+ XEMACPS_TXBUF_URUN_MASK)!=0U ? TRUE : FALSE)
+
+
+/*****************************************************************************/
+/**
+ * Determine if a frame fails to be transmitted due to buffer is exhausted
+ * mid-frame.
+ *
+ * @param BdPtr is the BD pointer to operate on
+ *
+ * @note
+ * C-style signature:
+ * UINTPTR XEmacPs_BdIsTxExh(XEmacPs_Bd* BdPtr)
+ *
+ *****************************************************************************/
+#define XEmacPs_BdIsTxExh(BdPtr) \
+ ((XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) & \
+ XEMACPS_TXBUF_EXH_MASK)!=0U ? TRUE : FALSE)
+
+
+/*****************************************************************************/
+/**
+ * Sets this bit, no CRC will be appended to the current frame. This control
+ * bit must be set for the first buffer in a frame and will be ignored for
+ * the subsequent buffers of a frame.
+ *
+ * @param BdPtr is the BD pointer to operate on
+ *
+ * @note
+ * This bit must be clear when using the transmit checksum generation offload,
+ * otherwise checksum generation and substitution will not occur.
+ *
+ * C-style signature:
+ * UINTPTR XEmacPs_BdSetTxNoCRC(XEmacPs_Bd* BdPtr)
+ *
+ *****************************************************************************/
+#define XEmacPs_BdSetTxNoCRC(BdPtr) \
+ (XEmacPs_BdWrite((BdPtr), XEMACPS_BD_STAT_OFFSET, \
+ XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) | \
+ XEMACPS_TXBUF_NOCRC_MASK))
+
+
+/*****************************************************************************/
+/**
+ * Clear this bit, CRC will be appended to the current frame. This control
+ * bit must be set for the first buffer in a frame and will be ignored for
+ * the subsequent buffers of a frame.
+ *
+ * @param BdPtr is the BD pointer to operate on
+ *
+ * @note
+ * This bit must be clear when using the transmit checksum generation offload,
+ * otherwise checksum generation and substitution will not occur.
+ *
+ * C-style signature:
+ * UINTPTR XEmacPs_BdClearTxNoCRC(XEmacPs_Bd* BdPtr)
+ *
+ *****************************************************************************/
+#define XEmacPs_BdClearTxNoCRC(BdPtr) \
+ (XEmacPs_BdWrite((BdPtr), XEMACPS_BD_STAT_OFFSET, \
+ XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) & \
+ ~XEMACPS_TXBUF_NOCRC_MASK))
+
+
+/*****************************************************************************/
+/**
+ * Determine the broadcast bit of the receive BD.
+ *
+ * @param BdPtr is the BD pointer to operate on
+ *
+ * @note
+ * C-style signature:
+ * UINTPTR XEmacPs_BdIsRxBcast(XEmacPs_Bd* BdPtr)
+ *
+ *****************************************************************************/
+#define XEmacPs_BdIsRxBcast(BdPtr) \
+ ((XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) & \
+ XEMACPS_RXBUF_BCAST_MASK)!=0U ? TRUE : FALSE)
+
+
+/*****************************************************************************/
+/**
+ * Determine the multicast hash bit of the receive BD.
+ *
+ * @param BdPtr is the BD pointer to operate on
+ *
+ * @note
+ * C-style signature:
+ * UINTPTR XEmacPs_BdIsRxMultiHash(XEmacPs_Bd* BdPtr)
+ *
+ *****************************************************************************/
+#define XEmacPs_BdIsRxMultiHash(BdPtr) \
+ ((XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) & \
+ XEMACPS_RXBUF_MULTIHASH_MASK)!=0U ? TRUE : FALSE)
+
+
+/*****************************************************************************/
+/**
+ * Determine the unicast hash bit of the receive BD.
+ *
+ * @param BdPtr is the BD pointer to operate on
+ *
+ * @note
+ * C-style signature:
+ * UINTPTR XEmacPs_BdIsRxUniHash(XEmacPs_Bd* BdPtr)
+ *
+ *****************************************************************************/
+#define XEmacPs_BdIsRxUniHash(BdPtr) \
+ ((XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) & \
+ XEMACPS_RXBUF_UNIHASH_MASK)!=0U ? TRUE : FALSE)
+
+
+/*****************************************************************************/
+/**
+ * Determine if the received frame is a VLAN Tagged frame.
+ *
+ * @param BdPtr is the BD pointer to operate on
+ *
+ * @note
+ * C-style signature:
+ * UINTPTR XEmacPs_BdIsRxVlan(XEmacPs_Bd* BdPtr)
+ *
+ *****************************************************************************/
+#define XEmacPs_BdIsRxVlan(BdPtr) \
+ ((XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) & \
+ XEMACPS_RXBUF_VLAN_MASK)!=0U ? TRUE : FALSE)
+
+
+/*****************************************************************************/
+/**
+ * Determine if the received frame has Type ID of 8100h and null VLAN
+ * identifier(Priority tag).
+ *
+ * @param BdPtr is the BD pointer to operate on
+ *
+ * @note
+ * C-style signature:
+ * UINTPTR XEmacPs_BdIsRxPri(XEmacPs_Bd* BdPtr)
+ *
+ *****************************************************************************/
+#define XEmacPs_BdIsRxPri(BdPtr) \
+ ((XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) & \
+ XEMACPS_RXBUF_PRI_MASK)!=0U ? TRUE : FALSE)
+
+
+/*****************************************************************************/
+/**
+ * Determine if the received frame's Concatenation Format Indicator (CFI) of
+ * the frames VLANTCI field was set.
+ *
+ * @param BdPtr is the BD pointer to operate on
+ *
+ * @note
+ * C-style signature:
+ * UINTPTR XEmacPs_BdIsRxCFI(XEmacPs_Bd* BdPtr)
+ *
+ *****************************************************************************/
+#define XEmacPs_BdIsRxCFI(BdPtr) \
+ ((XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) & \
+ XEMACPS_RXBUF_CFI_MASK)!=0U ? TRUE : FALSE)
+
+
+/*****************************************************************************/
+/**
+ * Determine the End Of Frame (EOF) bit of the receive BD.
+ *
+ * @param BdPtr is the BD pointer to operate on
+ *
+ * @note
+ * C-style signature:
+ * UINTPTR XEmacPs_BdGetRxEOF(XEmacPs_Bd* BdPtr)
+ *
+ *****************************************************************************/
+#define XEmacPs_BdIsRxEOF(BdPtr) \
+ ((XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) & \
+ XEMACPS_RXBUF_EOF_MASK)!=0U ? TRUE : FALSE)
+
+
+/*****************************************************************************/
+/**
+ * Determine the Start Of Frame (SOF) bit of the receive BD.
+ *
+ * @param BdPtr is the BD pointer to operate on
+ *
+ * @note
+ * C-style signature:
+ * UINTPTR XEmacPs_BdGetRxSOF(XEmacPs_Bd* BdPtr)
+ *
+ *****************************************************************************/
+#define XEmacPs_BdIsRxSOF(BdPtr) \
+ ((XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) & \
+ XEMACPS_RXBUF_SOF_MASK)!=0U ? TRUE : FALSE)
+
+
+/************************** Function Prototypes ******************************/
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* end of protection macro */
+/** @} */
diff --git a/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/include/xemacps_bdring.h b/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/include/xemacps_bdring.h
new file mode 100644
index 0000000..2bc74f7
--- /dev/null
+++ b/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/include/xemacps_bdring.h
@@ -0,0 +1,235 @@
+/******************************************************************************
+*
+* Copyright (C) 2010 - 2019 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+* THE SOFTWARE.
+*
+*
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xemacps_bdring.h
+* @addtogroup emacps_v3_10
+* @{
+*
+* The Xiline EmacPs Buffer Descriptor ring driver. This is part of EmacPs
+* DMA functionalities.
+*
+* <pre>
+* MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ----- ---- -------- -------------------------------------------------------
+* 1.00a wsy 01/10/10 First release
+* 2.1 srt 07/15/14 Add support for Zynq Ultrascale Mp architecture.
+* 3.0 kvn 02/13/15 Modified code for MISRA-C:2012 compliance.
+* 3.6 rb 09/08/17 HwCnt variable (in XEmacPs_BdRing structure) is
+* changed to volatile.
+*
+* </pre>
+*
+******************************************************************************/
+
+#ifndef XEMACPS_BDRING_H /* prevent curcular inclusions */
+#define XEMACPS_BDRING_H /* by using protection macros */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+
+/**************************** Type Definitions *******************************/
+
+/** This is an internal structure used to maintain the DMA list */
+typedef struct {
+ UINTPTR PhysBaseAddr;/**< Physical address of 1st BD in list */
+ UINTPTR BaseBdAddr; /**< Virtual address of 1st BD in list */
+ UINTPTR HighBdAddr; /**< Virtual address of last BD in the list */
+ u32 Length; /**< Total size of ring in bytes */
+ u32 RunState; /**< Flag to indicate DMA is started */
+ u32 Separation; /**< Number of bytes between the starting address
+ of adjacent BDs */
+ XEmacPs_Bd *FreeHead;
+ /**< First BD in the free group */
+ XEmacPs_Bd *PreHead;/**< First BD in the pre-work group */
+ XEmacPs_Bd *HwHead; /**< First BD in the work group */
+ XEmacPs_Bd *HwTail; /**< Last BD in the work group */
+ XEmacPs_Bd *PostHead;
+ /**< First BD in the post-work group */
+ XEmacPs_Bd *BdaRestart;
+ /**< BDA to load when channel is started */
+
+ volatile u32 HwCnt; /**< Number of BDs in work group */
+ u32 PreCnt; /**< Number of BDs in pre-work group */
+ u32 FreeCnt; /**< Number of allocatable BDs in the free group */
+ u32 PostCnt; /**< Number of BDs in post-work group */
+ u32 AllCnt; /**< Total Number of BDs for channel */
+} XEmacPs_BdRing;
+
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/*****************************************************************************/
+/**
+* Use this macro at initialization time to determine how many BDs will fit
+* in a BD list within the given memory constraints.
+*
+* The results of this macro can be provided to XEmacPs_BdRingCreate().
+*
+* @param Alignment specifies what byte alignment the BDs must fall on and
+* must be a power of 2 to get an accurate calculation (32, 64, 128,...)
+* @param Bytes is the number of bytes to be used to store BDs.
+*
+* @return Number of BDs that can fit in the given memory area
+*
+* @note
+* C-style signature:
+* u32 XEmacPs_BdRingCntCalc(u32 Alignment, u32 Bytes)
+*
+******************************************************************************/
+#define XEmacPs_BdRingCntCalc(Alignment, Bytes) \
+ (u32)((Bytes) / (sizeof(XEmacPs_Bd)))
+
+/*****************************************************************************/
+/**
+* Use this macro at initialization time to determine how many bytes of memory
+* is required to contain a given number of BDs at a given alignment.
+*
+* @param Alignment specifies what byte alignment the BDs must fall on. This
+* parameter must be a power of 2 to get an accurate calculation (32, 64,
+* 128,...)
+* @param NumBd is the number of BDs to calculate memory size requirements for
+*
+* @return The number of bytes of memory required to create a BD list with the
+* given memory constraints.
+*
+* @note
+* C-style signature:
+* u32 XEmacPs_BdRingMemCalc(u32 Alignment, u32 NumBd)
+*
+******************************************************************************/
+#define XEmacPs_BdRingMemCalc(Alignment, NumBd) \
+ (u32)(sizeof(XEmacPs_Bd) * (NumBd))
+
+/****************************************************************************/
+/**
+* Return the total number of BDs allocated by this channel with
+* XEmacPs_BdRingCreate().
+*
+* @param RingPtr is the DMA channel to operate on.
+*
+* @return The total number of BDs allocated for this channel.
+*
+* @note
+* C-style signature:
+* u32 XEmacPs_BdRingGetCnt(XEmacPs_BdRing* RingPtr)
+*
+*****************************************************************************/
+#define XEmacPs_BdRingGetCnt(RingPtr) ((RingPtr)->AllCnt)
+
+/****************************************************************************/
+/**
+* Return the number of BDs allocatable with XEmacPs_BdRingAlloc() for pre-
+* processing.
+*
+* @param RingPtr is the DMA channel to operate on.
+*
+* @return The number of BDs currently allocatable.
+*
+* @note
+* C-style signature:
+* u32 XEmacPs_BdRingGetFreeCnt(XEmacPs_BdRing* RingPtr)
+*
+*****************************************************************************/
+#define XEmacPs_BdRingGetFreeCnt(RingPtr) ((RingPtr)->FreeCnt)
+
+/****************************************************************************/
+/**
+* Return the next BD from BdPtr in a list.
+*
+* @param RingPtr is the DMA channel to operate on.
+* @param BdPtr is the BD to operate on.
+*
+* @return The next BD in the list relative to the BdPtr parameter.
+*
+* @note
+* C-style signature:
+* XEmacPs_Bd *XEmacPs_BdRingNext(XEmacPs_BdRing* RingPtr,
+* XEmacPs_Bd *BdPtr)
+*
+*****************************************************************************/
+#define XEmacPs_BdRingNext(RingPtr, BdPtr) \
+ (((UINTPTR)((void *)(BdPtr)) >= (RingPtr)->HighBdAddr) ? \
+ (XEmacPs_Bd*)((void*)(RingPtr)->BaseBdAddr) : \
+ (XEmacPs_Bd*)((UINTPTR)((void *)(BdPtr)) + (RingPtr)->Separation))
+
+/****************************************************************************/
+/**
+* Return the previous BD from BdPtr in the list.
+*
+* @param RingPtr is the DMA channel to operate on.
+* @param BdPtr is the BD to operate on
+*
+* @return The previous BD in the list relative to the BdPtr parameter.
+*
+* @note
+* C-style signature:
+* XEmacPs_Bd *XEmacPs_BdRingPrev(XEmacPs_BdRing* RingPtr,
+* XEmacPs_Bd *BdPtr)
+*
+*****************************************************************************/
+#define XEmacPs_BdRingPrev(RingPtr, BdPtr) \
+ (((UINTPTR)(BdPtr) <= (RingPtr)->BaseBdAddr) ? \
+ (XEmacPs_Bd*)(RingPtr)->HighBdAddr : \
+ (XEmacPs_Bd*)((UINTPTR)(BdPtr) - (RingPtr)->Separation))
+
+/************************** Function Prototypes ******************************/
+
+/*
+ * Scatter gather DMA related functions in xemacps_bdring.c
+ */
+LONG XEmacPs_BdRingCreate(XEmacPs_BdRing * RingPtr, UINTPTR PhysAddr,
+ UINTPTR VirtAddr, u32 Alignment, u32 BdCount);
+LONG XEmacPs_BdRingClone(XEmacPs_BdRing * RingPtr, XEmacPs_Bd * SrcBdPtr,
+ u8 Direction);
+LONG XEmacPs_BdRingAlloc(XEmacPs_BdRing * RingPtr, u32 NumBd,
+ XEmacPs_Bd ** BdSetPtr);
+LONG XEmacPs_BdRingUnAlloc(XEmacPs_BdRing * RingPtr, u32 NumBd,
+ XEmacPs_Bd * BdSetPtr);
+LONG XEmacPs_BdRingToHw(XEmacPs_BdRing * RingPtr, u32 NumBd,
+ XEmacPs_Bd * BdSetPtr);
+LONG XEmacPs_BdRingFree(XEmacPs_BdRing * RingPtr, u32 NumBd,
+ XEmacPs_Bd * BdSetPtr);
+u32 XEmacPs_BdRingFromHwTx(XEmacPs_BdRing * RingPtr, u32 BdLimit,
+ XEmacPs_Bd ** BdSetPtr);
+u32 XEmacPs_BdRingFromHwRx(XEmacPs_BdRing * RingPtr, u32 BdLimit,
+ XEmacPs_Bd ** BdSetPtr);
+LONG XEmacPs_BdRingCheck(XEmacPs_BdRing * RingPtr, u8 Direction);
+
+void XEmacPs_BdRingPtrReset(XEmacPs_BdRing * RingPtr, void *virtaddrloc);
+
+#ifdef __cplusplus
+}
+#endif
+
+
+#endif /* end of protection macros */
+/** @} */
diff --git a/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/include/xemacps_hw.h b/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/include/xemacps_hw.h
new file mode 100644
index 0000000..8b902d3
--- /dev/null
+++ b/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/include/xemacps_hw.h
@@ -0,0 +1,666 @@
+/******************************************************************************
+*
+* Copyright (C) 2010 - 2019 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+* THE SOFTWARE.
+*
+*
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xemacps_hw.h
+* @addtogroup emacps_v3_10
+* @{
+*
+* This header file contains identifiers and low-level driver functions (or
+* macros) that can be used to access the PS Ethernet MAC (XEmacPs) device.
+* High-level driver functions are defined in xemacps.h.
+*
+* @note
+*
+* <pre>
+* MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ----- ---- -------- -------------------------------------------------------
+* 1.00a wsy 01/10/10 First release.
+* 1.02a asa 11/05/12 Added hash defines for DMACR burst length configuration.
+* 1.05a kpc 28/06/13 Added XEmacPs_ResetHw function prototype
+* 1.06a asa 11/02/13 Changed the value for XEMACPS_RXBUF_LEN_MASK from 0x3fff
+* to 0x1fff. This fixes the CR#744902.
+* 2.1 srt 07/15/14 Add support for Zynq Ultrascale Mp GEM specification.
+* 3.0 kvn 12/16/14 Changed name of XEMACPS_NWCFG_LENGTHERRDSCRD_MASK to
+* XEMACPS_NWCFG_LENERRDSCRD_MASK as it exceeds 31 characters.
+* 3.0 kpc 1/23/15 Corrected the extended descriptor macro values.
+* 3.0 kvn 02/13/15 Modified code for MISRA-C:2012 compliance.
+* 3.0 hk 03/18/15 Added support for jumbo frames.
+* Remove "used bit set" from TX error interrupt masks.
+* 3.1 hk 08/10/15 Update upper 32 bit tx and rx queue ptr register offsets.
+* 3.2 hk 02/22/16 Added SGMII support for Zynq Ultrascale+ MPSoC.
+* 3.8 hk 09/17/18 Fix PTP interrupt masks.
+* 3.9 hk 01/23/19 Add RX watermark support
+* 3.10 hk 05/16/19 Clear status registers properly in reset
+* </pre>
+*
+******************************************************************************/
+
+#ifndef XEMACPS_HW_H /* prevent circular inclusions */
+#define XEMACPS_HW_H /* by using protection macros */
+
+/***************************** Include Files *********************************/
+
+#include "xil_types.h"
+#include "xil_assert.h"
+#include "xil_io.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/************************** Constant Definitions *****************************/
+
+#define XEMACPS_MAX_MAC_ADDR 4U /**< Maxmum number of mac address
+ supported */
+#define XEMACPS_MAX_TYPE_ID 4U /**< Maxmum number of type id supported */
+
+#ifdef __aarch64__
+#define XEMACPS_BD_ALIGNMENT 64U /**< Minimum buffer descriptor alignment
+ on the local bus */
+#else
+
+#define XEMACPS_BD_ALIGNMENT 4U /**< Minimum buffer descriptor alignment
+ on the local bus */
+#endif
+#define XEMACPS_RX_BUF_ALIGNMENT 4U /**< Minimum buffer alignment when using
+ options that impose alignment
+ restrictions on the buffer data on
+ the local bus */
+
+/** @name Direction identifiers
+ *
+ * These are used by several functions and callbacks that need
+ * to specify whether an operation specifies a send or receive channel.
+ * @{
+ */
+#define XEMACPS_SEND 1U /**< send direction */
+#define XEMACPS_RECV 2U /**< receive direction */
+/*@}*/
+
+/** @name MDC clock division
+ * currently supporting 8, 16, 32, 48, 64, 96, 128, 224.
+ * @{
+ */
+typedef enum { MDC_DIV_8 = 0U, MDC_DIV_16, MDC_DIV_32, MDC_DIV_48,
+ MDC_DIV_64, MDC_DIV_96, MDC_DIV_128, MDC_DIV_224
+} XEmacPs_MdcDiv;
+
+/*@}*/
+
+#define XEMACPS_RX_BUF_SIZE 1536U /**< Specify the receive buffer size in
+ bytes, 64, 128, ... 10240 */
+#define XEMACPS_RX_BUF_SIZE_JUMBO 10240U
+
+#define XEMACPS_RX_BUF_UNIT 64U /**< Number of receive buffer bytes as a
+ unit, this is HW setup */
+
+#define XEMACPS_MAX_RXBD 128U /**< Size of RX buffer descriptor queues */
+#define XEMACPS_MAX_TXBD 128U /**< Size of TX buffer descriptor queues */
+
+#define XEMACPS_MAX_HASH_BITS 64U /**< Maximum value for hash bits. 2**6 */
+
+/* Register offset definitions. Unless otherwise noted, register access is
+ * 32 bit. Names are self explained here.
+ */
+
+#define XEMACPS_NWCTRL_OFFSET 0x00000000U /**< Network Control reg */
+#define XEMACPS_NWCFG_OFFSET 0x00000004U /**< Network Config reg */
+#define XEMACPS_NWSR_OFFSET 0x00000008U /**< Network Status reg */
+
+#define XEMACPS_DMACR_OFFSET 0x00000010U /**< DMA Control reg */
+#define XEMACPS_TXSR_OFFSET 0x00000014U /**< TX Status reg */
+#define XEMACPS_RXQBASE_OFFSET 0x00000018U /**< RX Q Base address reg */
+#define XEMACPS_TXQBASE_OFFSET 0x0000001CU /**< TX Q Base address reg */
+#define XEMACPS_RXSR_OFFSET 0x00000020U /**< RX Status reg */
+
+#define XEMACPS_ISR_OFFSET 0x00000024U /**< Interrupt Status reg */
+#define XEMACPS_IER_OFFSET 0x00000028U /**< Interrupt Enable reg */
+#define XEMACPS_IDR_OFFSET 0x0000002CU /**< Interrupt Disable reg */
+#define XEMACPS_IMR_OFFSET 0x00000030U /**< Interrupt Mask reg */
+
+#define XEMACPS_PHYMNTNC_OFFSET 0x00000034U /**< Phy Maintaince reg */
+#define XEMACPS_RXPAUSE_OFFSET 0x00000038U /**< RX Pause Time reg */
+#define XEMACPS_TXPAUSE_OFFSET 0x0000003CU /**< TX Pause Time reg */
+
+#define XEMACPS_JUMBOMAXLEN_OFFSET 0x00000048U /**< Jumbo max length reg */
+
+#define XEMACPS_RXWATERMARK_OFFSET 0x0000007CU /**< RX watermark reg */
+
+#define XEMACPS_HASHL_OFFSET 0x00000080U /**< Hash Low address reg */
+#define XEMACPS_HASHH_OFFSET 0x00000084U /**< Hash High address reg */
+
+#define XEMACPS_LADDR1L_OFFSET 0x00000088U /**< Specific1 addr low reg */
+#define XEMACPS_LADDR1H_OFFSET 0x0000008CU /**< Specific1 addr high reg */
+#define XEMACPS_LADDR2L_OFFSET 0x00000090U /**< Specific2 addr low reg */
+#define XEMACPS_LADDR2H_OFFSET 0x00000094U /**< Specific2 addr high reg */
+#define XEMACPS_LADDR3L_OFFSET 0x00000098U /**< Specific3 addr low reg */
+#define XEMACPS_LADDR3H_OFFSET 0x0000009CU /**< Specific3 addr high reg */
+#define XEMACPS_LADDR4L_OFFSET 0x000000A0U /**< Specific4 addr low reg */
+#define XEMACPS_LADDR4H_OFFSET 0x000000A4U /**< Specific4 addr high reg */
+
+#define XEMACPS_MATCH1_OFFSET 0x000000A8U /**< Type ID1 Match reg */
+#define XEMACPS_MATCH2_OFFSET 0x000000ACU /**< Type ID2 Match reg */
+#define XEMACPS_MATCH3_OFFSET 0x000000B0U /**< Type ID3 Match reg */
+#define XEMACPS_MATCH4_OFFSET 0x000000B4U /**< Type ID4 Match reg */
+
+#define XEMACPS_STRETCH_OFFSET 0x000000BCU /**< IPG Stretch reg */
+
+#define XEMACPS_OCTTXL_OFFSET 0x00000100U /**< Octects transmitted Low
+ reg */
+#define XEMACPS_OCTTXH_OFFSET 0x00000104U /**< Octects transmitted High
+ reg */
+
+#define XEMACPS_TXCNT_OFFSET 0x00000108U /**< Error-free Frmaes
+ transmitted counter */
+#define XEMACPS_TXBCCNT_OFFSET 0x0000010CU /**< Error-free Broadcast
+ Frames counter*/
+#define XEMACPS_TXMCCNT_OFFSET 0x00000110U /**< Error-free Multicast
+ Frame counter */
+#define XEMACPS_TXPAUSECNT_OFFSET 0x00000114U /**< Pause Frames Transmitted
+ Counter */
+#define XEMACPS_TX64CNT_OFFSET 0x00000118U /**< Error-free 64 byte Frames
+ Transmitted counter */
+#define XEMACPS_TX65CNT_OFFSET 0x0000011CU /**< Error-free 65-127 byte
+ Frames Transmitted
+ counter */
+#define XEMACPS_TX128CNT_OFFSET 0x00000120U /**< Error-free 128-255 byte
+ Frames Transmitted
+ counter*/
+#define XEMACPS_TX256CNT_OFFSET 0x00000124U /**< Error-free 256-511 byte
+ Frames transmitted
+ counter */
+#define XEMACPS_TX512CNT_OFFSET 0x00000128U /**< Error-free 512-1023 byte
+ Frames transmitted
+ counter */
+#define XEMACPS_TX1024CNT_OFFSET 0x0000012CU /**< Error-free 1024-1518 byte
+ Frames transmitted
+ counter */
+#define XEMACPS_TX1519CNT_OFFSET 0x00000130U /**< Error-free larger than
+ 1519 byte Frames
+ transmitted counter */
+#define XEMACPS_TXURUNCNT_OFFSET 0x00000134U /**< TX under run error
+ counter */
+
+#define XEMACPS_SNGLCOLLCNT_OFFSET 0x00000138U /**< Single Collision Frame
+ Counter */
+#define XEMACPS_MULTICOLLCNT_OFFSET 0x0000013CU /**< Multiple Collision Frame
+ Counter */
+#define XEMACPS_EXCESSCOLLCNT_OFFSET 0x00000140U /**< Excessive Collision Frame
+ Counter */
+#define XEMACPS_LATECOLLCNT_OFFSET 0x00000144U /**< Late Collision Frame
+ Counter */
+#define XEMACPS_TXDEFERCNT_OFFSET 0x00000148U /**< Deferred Transmission
+ Frame Counter */
+#define XEMACPS_TXCSENSECNT_OFFSET 0x0000014CU /**< Transmit Carrier Sense
+ Error Counter */
+
+#define XEMACPS_OCTRXL_OFFSET 0x00000150U /**< Octects Received register
+ Low */
+#define XEMACPS_OCTRXH_OFFSET 0x00000154U /**< Octects Received register
+ High */
+
+#define XEMACPS_RXCNT_OFFSET 0x00000158U /**< Error-free Frames
+ Received Counter */
+#define XEMACPS_RXBROADCNT_OFFSET 0x0000015CU /**< Error-free Broadcast
+ Frames Received Counter */
+#define XEMACPS_RXMULTICNT_OFFSET 0x00000160U /**< Error-free Multicast
+ Frames Received Counter */
+#define XEMACPS_RXPAUSECNT_OFFSET 0x00000164U /**< Pause Frames
+ Received Counter */
+#define XEMACPS_RX64CNT_OFFSET 0x00000168U /**< Error-free 64 byte Frames
+ Received Counter */
+#define XEMACPS_RX65CNT_OFFSET 0x0000016CU /**< Error-free 65-127 byte
+ Frames Received Counter */
+#define XEMACPS_RX128CNT_OFFSET 0x00000170U /**< Error-free 128-255 byte
+ Frames Received Counter */
+#define XEMACPS_RX256CNT_OFFSET 0x00000174U /**< Error-free 256-512 byte
+ Frames Received Counter */
+#define XEMACPS_RX512CNT_OFFSET 0x00000178U /**< Error-free 512-1023 byte
+ Frames Received Counter */
+#define XEMACPS_RX1024CNT_OFFSET 0x0000017CU /**< Error-free 1024-1518 byte
+ Frames Received Counter */
+#define XEMACPS_RX1519CNT_OFFSET 0x00000180U /**< Error-free 1519-max byte
+ Frames Received Counter */
+#define XEMACPS_RXUNDRCNT_OFFSET 0x00000184U /**< Undersize Frames Received
+ Counter */
+#define XEMACPS_RXOVRCNT_OFFSET 0x00000188U /**< Oversize Frames Received
+ Counter */
+#define XEMACPS_RXJABCNT_OFFSET 0x0000018CU /**< Jabbers Received
+ Counter */
+#define XEMACPS_RXFCSCNT_OFFSET 0x00000190U /**< Frame Check Sequence
+ Error Counter */
+#define XEMACPS_RXLENGTHCNT_OFFSET 0x00000194U /**< Length Field Error
+ Counter */
+#define XEMACPS_RXSYMBCNT_OFFSET 0x00000198U /**< Symbol Error Counter */
+#define XEMACPS_RXALIGNCNT_OFFSET 0x0000019CU /**< Alignment Error Counter */
+#define XEMACPS_RXRESERRCNT_OFFSET 0x000001A0U /**< Receive Resource Error
+ Counter */
+#define XEMACPS_RXORCNT_OFFSET 0x000001A4U /**< Receive Overrun Counter */
+#define XEMACPS_RXIPCCNT_OFFSET 0x000001A8U /**< IP header Checksum Error
+ Counter */
+#define XEMACPS_RXTCPCCNT_OFFSET 0x000001ACU /**< TCP Checksum Error
+ Counter */
+#define XEMACPS_RXUDPCCNT_OFFSET 0x000001B0U /**< UDP Checksum Error
+ Counter */
+#define XEMACPS_LAST_OFFSET 0x000001B4U /**< Last statistic counter
+ offset, for clearing */
+
+#define XEMACPS_1588_SEC_OFFSET 0x000001D0U /**< 1588 second counter */
+#define XEMACPS_1588_NANOSEC_OFFSET 0x000001D4U /**< 1588 nanosecond counter */
+#define XEMACPS_1588_ADJ_OFFSET 0x000001D8U /**< 1588 nanosecond
+ adjustment counter */
+#define XEMACPS_1588_INC_OFFSET 0x000001DCU /**< 1588 nanosecond
+ increment counter */
+#define XEMACPS_PTP_TXSEC_OFFSET 0x000001E0U /**< 1588 PTP transmit second
+ counter */
+#define XEMACPS_PTP_TXNANOSEC_OFFSET 0x000001E4U /**< 1588 PTP transmit
+ nanosecond counter */
+#define XEMACPS_PTP_RXSEC_OFFSET 0x000001E8U /**< 1588 PTP receive second
+ counter */
+#define XEMACPS_PTP_RXNANOSEC_OFFSET 0x000001ECU /**< 1588 PTP receive
+ nanosecond counter */
+#define XEMACPS_PTPP_TXSEC_OFFSET 0x000001F0U /**< 1588 PTP peer transmit
+ second counter */
+#define XEMACPS_PTPP_TXNANOSEC_OFFSET 0x000001F4U /**< 1588 PTP peer transmit
+ nanosecond counter */
+#define XEMACPS_PTPP_RXSEC_OFFSET 0x000001F8U /**< 1588 PTP peer receive
+ second counter */
+#define XEMACPS_PTPP_RXNANOSEC_OFFSET 0x000001FCU /**< 1588 PTP peer receive
+ nanosecond counter */
+
+#define XEMACPS_INTQ1_STS_OFFSET 0x00000400U /**< Interrupt Q1 Status
+ reg */
+#define XEMACPS_TXQ1BASE_OFFSET 0x00000440U /**< TX Q1 Base address
+ reg */
+#define XEMACPS_RXQ1BASE_OFFSET 0x00000480U /**< RX Q1 Base address
+ reg */
+#define XEMACPS_MSBBUF_TXQBASE_OFFSET 0x000004C8U /**< MSB Buffer TX Q Base
+ reg */
+#define XEMACPS_MSBBUF_RXQBASE_OFFSET 0x000004D4U /**< MSB Buffer RX Q Base
+ reg */
+#define XEMACPS_INTQ1_IER_OFFSET 0x00000600U /**< Interrupt Q1 Enable
+ reg */
+#define XEMACPS_INTQ1_IDR_OFFSET 0x00000620U /**< Interrupt Q1 Disable
+ reg */
+#define XEMACPS_INTQ1_IMR_OFFSET 0x00000640U /**< Interrupt Q1 Mask
+ reg */
+
+/* Define some bit positions for registers. */
+
+/** @name network control register bit definitions
+ * @{
+ */
+#define XEMACPS_NWCTRL_FLUSH_DPRAM_MASK 0x00040000U /**< Flush a packet from
+ Rx SRAM */
+#define XEMACPS_NWCTRL_ZEROPAUSETX_MASK 0x00000800U /**< Transmit zero quantum
+ pause frame */
+#define XEMACPS_NWCTRL_PAUSETX_MASK 0x00000800U /**< Transmit pause frame */
+#define XEMACPS_NWCTRL_HALTTX_MASK 0x00000400U /**< Halt transmission
+ after current frame */
+#define XEMACPS_NWCTRL_STARTTX_MASK 0x00000200U /**< Start tx (tx_go) */
+
+#define XEMACPS_NWCTRL_STATWEN_MASK 0x00000080U /**< Enable writing to
+ stat counters */
+#define XEMACPS_NWCTRL_STATINC_MASK 0x00000040U /**< Increment statistic
+ registers */
+#define XEMACPS_NWCTRL_STATCLR_MASK 0x00000020U /**< Clear statistic
+ registers */
+#define XEMACPS_NWCTRL_MDEN_MASK 0x00000010U /**< Enable MDIO port */
+#define XEMACPS_NWCTRL_TXEN_MASK 0x00000008U /**< Enable transmit */
+#define XEMACPS_NWCTRL_RXEN_MASK 0x00000004U /**< Enable receive */
+#define XEMACPS_NWCTRL_LOOPEN_MASK 0x00000002U /**< local loopback */
+/*@}*/
+
+/** @name network configuration register bit definitions
+ * @{
+ */
+#define XEMACPS_NWCFG_BADPREAMBEN_MASK 0x20000000U /**< disable rejection of
+ non-standard preamble */
+#define XEMACPS_NWCFG_IPDSTRETCH_MASK 0x10000000U /**< enable transmit IPG */
+#define XEMACPS_NWCFG_SGMIIEN_MASK 0x08000000U /**< SGMII Enable */
+#define XEMACPS_NWCFG_FCSIGNORE_MASK 0x04000000U /**< disable rejection of
+ FCS error */
+#define XEMACPS_NWCFG_HDRXEN_MASK 0x02000000U /**< RX half duplex */
+#define XEMACPS_NWCFG_RXCHKSUMEN_MASK 0x01000000U /**< enable RX checksum
+ offload */
+#define XEMACPS_NWCFG_PAUSECOPYDI_MASK 0x00800000U /**< Do not copy pause
+ Frames to memory */
+#define XEMACPS_NWCFG_DWIDTH_64_MASK 0x00200000U /**< 64 bit Data bus width */
+#define XEMACPS_NWCFG_MDC_SHIFT_MASK 18U /**< shift bits for MDC */
+#define XEMACPS_NWCFG_MDCCLKDIV_MASK 0x001C0000U /**< MDC Mask PCLK divisor */
+#define XEMACPS_NWCFG_FCSREM_MASK 0x00020000U /**< Discard FCS from
+ received frames */
+#define XEMACPS_NWCFG_LENERRDSCRD_MASK 0x00010000U
+/**< RX length error discard */
+#define XEMACPS_NWCFG_RXOFFS_MASK 0x0000C000U /**< RX buffer offset */
+#define XEMACPS_NWCFG_PAUSEEN_MASK 0x00002000U /**< Enable pause RX */
+#define XEMACPS_NWCFG_RETRYTESTEN_MASK 0x00001000U /**< Retry test */
+#define XEMACPS_NWCFG_XTADDMACHEN_MASK 0x00000200U
+/**< External address match enable */
+#define XEMACPS_NWCFG_PCSSEL_MASK 0x00000800U /**< PCS Select */
+#define XEMACPS_NWCFG_1000_MASK 0x00000400U /**< 1000 Mbps */
+#define XEMACPS_NWCFG_1536RXEN_MASK 0x00000100U /**< Enable 1536 byte
+ frames reception */
+#define XEMACPS_NWCFG_UCASTHASHEN_MASK 0x00000080U /**< Receive unicast hash
+ frames */
+#define XEMACPS_NWCFG_MCASTHASHEN_MASK 0x00000040U /**< Receive multicast hash
+ frames */
+#define XEMACPS_NWCFG_BCASTDI_MASK 0x00000020U /**< Do not receive
+ broadcast frames */
+#define XEMACPS_NWCFG_COPYALLEN_MASK 0x00000010U /**< Copy all frames */
+#define XEMACPS_NWCFG_JUMBO_MASK 0x00000008U /**< Jumbo frames */
+#define XEMACPS_NWCFG_NVLANDISC_MASK 0x00000004U /**< Receive only VLAN
+ frames */
+#define XEMACPS_NWCFG_FDEN_MASK 0x00000002U/**< full duplex */
+#define XEMACPS_NWCFG_100_MASK 0x00000001U /**< 100 Mbps */
+#define XEMACPS_NWCFG_RESET_MASK 0x00080000U/**< reset value */
+/*@}*/
+
+/** @name network status register bit definitaions
+ * @{
+ */
+#define XEMACPS_NWSR_MDIOIDLE_MASK 0x00000004U /**< PHY management idle */
+#define XEMACPS_NWSR_MDIO_MASK 0x00000002U /**< Status of mdio_in */
+/*@}*/
+
+
+/** @name MAC address register word 1 mask
+ * @{
+ */
+#define XEMACPS_LADDR_MACH_MASK 0x0000FFFFU /**< Address bits[47:32]
+ bit[31:0] are in BOTTOM */
+/*@}*/
+
+
+/** @name DMA control register bit definitions
+ * @{
+ */
+#define XEMACPS_DMACR_ADDR_WIDTH_64 0x40000000U /**< 64 bit address bus */
+#define XEMACPS_DMACR_TXEXTEND_MASK 0x20000000U /**< Tx Extended desc mode */
+#define XEMACPS_DMACR_RXEXTEND_MASK 0x10000000U /**< Rx Extended desc mode */
+#define XEMACPS_DMACR_RXBUF_MASK 0x00FF0000U /**< Mask bit for RX buffer
+ size */
+#define XEMACPS_DMACR_RXBUF_SHIFT 16U /**< Shift bit for RX buffer
+ size */
+#define XEMACPS_DMACR_TCPCKSUM_MASK 0x00000800U /**< enable/disable TX
+ checksum offload */
+#define XEMACPS_DMACR_TXSIZE_MASK 0x00000400U /**< TX buffer memory size */
+#define XEMACPS_DMACR_RXSIZE_MASK 0x00000300U /**< RX buffer memory size */
+#define XEMACPS_DMACR_ENDIAN_MASK 0x00000080U /**< endian configuration */
+#define XEMACPS_DMACR_BLENGTH_MASK 0x0000001FU /**< buffer burst length */
+#define XEMACPS_DMACR_SINGLE_AHB_BURST 0x00000001U /**< single AHB bursts */
+#define XEMACPS_DMACR_INCR4_AHB_BURST 0x00000004U /**< 4 bytes AHB bursts */
+#define XEMACPS_DMACR_INCR8_AHB_BURST 0x00000008U /**< 8 bytes AHB bursts */
+#define XEMACPS_DMACR_INCR16_AHB_BURST 0x00000010U /**< 16 bytes AHB bursts */
+/*@}*/
+
+/** @name transmit status register bit definitions
+ * @{
+ */
+#define XEMACPS_TXSR_HRESPNOK_MASK 0x00000100U /**< Transmit hresp not OK */
+#define XEMACPS_TXSR_URUN_MASK 0x00000040U /**< Transmit underrun */
+#define XEMACPS_TXSR_TXCOMPL_MASK 0x00000020U /**< Transmit completed OK */
+#define XEMACPS_TXSR_BUFEXH_MASK 0x00000010U /**< Transmit buffs exhausted
+ mid frame */
+#define XEMACPS_TXSR_TXGO_MASK 0x00000008U /**< Status of go flag */
+#define XEMACPS_TXSR_RXOVR_MASK 0x00000004U /**< Retry limit exceeded */
+#define XEMACPS_TXSR_FRAMERX_MASK 0x00000002U /**< Collision tx frame */
+#define XEMACPS_TXSR_USEDREAD_MASK 0x00000001U /**< TX buffer used bit set */
+
+#define XEMACPS_TXSR_ERROR_MASK ((u32)XEMACPS_TXSR_HRESPNOK_MASK | \
+ (u32)XEMACPS_TXSR_URUN_MASK | \
+ (u32)XEMACPS_TXSR_BUFEXH_MASK | \
+ (u32)XEMACPS_TXSR_RXOVR_MASK | \
+ (u32)XEMACPS_TXSR_FRAMERX_MASK | \
+ (u32)XEMACPS_TXSR_USEDREAD_MASK)
+/*@}*/
+
+/**
+ * @name receive status register bit definitions
+ * @{
+ */
+#define XEMACPS_RXSR_HRESPNOK_MASK 0x00000008U /**< Receive hresp not OK */
+#define XEMACPS_RXSR_RXOVR_MASK 0x00000004U /**< Receive overrun */
+#define XEMACPS_RXSR_FRAMERX_MASK 0x00000002U /**< Frame received OK */
+#define XEMACPS_RXSR_BUFFNA_MASK 0x00000001U /**< RX buffer used bit set */
+
+#define XEMACPS_RXSR_ERROR_MASK ((u32)XEMACPS_RXSR_HRESPNOK_MASK | \
+ (u32)XEMACPS_RXSR_RXOVR_MASK | \
+ (u32)XEMACPS_RXSR_BUFFNA_MASK)
+
+#define XEMACPS_SR_ALL_MASK 0xFFFFFFFFU /**< Mask for full register */
+
+/*@}*/
+
+/**
+ * @name Interrupt Q1 status register bit definitions
+ * @{
+ */
+#define XEMACPS_INTQ1SR_TXCOMPL_MASK 0x00000080U /**< Transmit completed OK */
+#define XEMACPS_INTQ1SR_TXERR_MASK 0x00000040U /**< Transmit AMBA Error */
+
+#define XEMACPS_INTQ1_IXR_ALL_MASK ((u32)XEMACPS_INTQ1SR_TXCOMPL_MASK | \
+ (u32)XEMACPS_INTQ1SR_TXERR_MASK)
+
+/*@}*/
+
+/**
+ * @name interrupts bit definitions
+ * Bits definitions are same in XEMACPS_ISR_OFFSET,
+ * XEMACPS_IER_OFFSET, XEMACPS_IDR_OFFSET, and XEMACPS_IMR_OFFSET
+ * @{
+ */
+#define XEMACPS_IXR_PTPPSTX_MASK 0x02000000U /**< PTP Pdelay_resp TXed */
+#define XEMACPS_IXR_PTPPDRTX_MASK 0x01000000U /**< PTP Pdelay_req TXed */
+#define XEMACPS_IXR_PTPPSRX_MASK 0x00800000U /**< PTP Pdelay_resp RXed */
+#define XEMACPS_IXR_PTPPDRRX_MASK 0x00400000U /**< PTP Pdelay_req RXed */
+
+#define XEMACPS_IXR_PTPSTX_MASK 0x00200000U /**< PTP Sync TXed */
+#define XEMACPS_IXR_PTPDRTX_MASK 0x00100000U /**< PTP Delay_req TXed */
+#define XEMACPS_IXR_PTPSRX_MASK 0x00080000U /**< PTP Sync RXed */
+#define XEMACPS_IXR_PTPDRRX_MASK 0x00040000U /**< PTP Delay_req RXed */
+
+#define XEMACPS_IXR_PAUSETX_MASK 0x00004000U /**< Pause frame transmitted */
+#define XEMACPS_IXR_PAUSEZERO_MASK 0x00002000U /**< Pause time has reached
+ zero */
+#define XEMACPS_IXR_PAUSENZERO_MASK 0x00001000U /**< Pause frame received */
+#define XEMACPS_IXR_HRESPNOK_MASK 0x00000800U /**< hresp not ok */
+#define XEMACPS_IXR_RXOVR_MASK 0x00000400U /**< Receive overrun occurred */
+#define XEMACPS_IXR_TXCOMPL_MASK 0x00000080U /**< Frame transmitted ok */
+#define XEMACPS_IXR_TXEXH_MASK 0x00000040U /**< Transmit err occurred or
+ no buffers*/
+#define XEMACPS_IXR_RETRY_MASK 0x00000020U /**< Retry limit exceeded */
+#define XEMACPS_IXR_URUN_MASK 0x00000010U /**< Transmit underrun */
+#define XEMACPS_IXR_TXUSED_MASK 0x00000008U /**< Tx buffer used bit read */
+#define XEMACPS_IXR_RXUSED_MASK 0x00000004U /**< Rx buffer used bit read */
+#define XEMACPS_IXR_FRAMERX_MASK 0x00000002U /**< Frame received ok */
+#define XEMACPS_IXR_MGMNT_MASK 0x00000001U /**< PHY management complete */
+#define XEMACPS_IXR_ALL_MASK 0x00007FFFU /**< Everything! */
+
+#define XEMACPS_IXR_TX_ERR_MASK ((u32)XEMACPS_IXR_TXEXH_MASK | \
+ (u32)XEMACPS_IXR_RETRY_MASK | \
+ (u32)XEMACPS_IXR_URUN_MASK)
+
+
+#define XEMACPS_IXR_RX_ERR_MASK ((u32)XEMACPS_IXR_HRESPNOK_MASK | \
+ (u32)XEMACPS_IXR_RXUSED_MASK | \
+ (u32)XEMACPS_IXR_RXOVR_MASK)
+
+/*@}*/
+
+/** @name PHY Maintenance bit definitions
+ * @{
+ */
+#define XEMACPS_PHYMNTNC_OP_MASK 0x40020000U /**< operation mask bits */
+#define XEMACPS_PHYMNTNC_OP_R_MASK 0x20000000U /**< read operation */
+#define XEMACPS_PHYMNTNC_OP_W_MASK 0x10000000U /**< write operation */
+#define XEMACPS_PHYMNTNC_ADDR_MASK 0x0F800000U /**< Address bits */
+#define XEMACPS_PHYMNTNC_REG_MASK 0x007C0000U /**< register bits */
+#define XEMACPS_PHYMNTNC_DATA_MASK 0x00000FFFU /**< data bits */
+#define XEMACPS_PHYMNTNC_PHAD_SHFT_MSK 23U /**< Shift bits for PHYAD */
+#define XEMACPS_PHYMNTNC_PREG_SHFT_MSK 18U /**< Shift bits for PHREG */
+/*@}*/
+
+/** @name RX watermark bit definitions
+ * @{
+ */
+#define XEMACPS_RXWM_HIGH_MASK 0x0000FFFFU /**< RXWM high mask */
+#define XEMACPS_RXWM_LOW_MASK 0xFFFF0000U /**< RXWM low mask */
+#define XEMACPS_RXWM_LOW_SHFT_MSK 16U /**< Shift for RXWM low */
+/*@}*/
+
+/* Transmit buffer descriptor status words offset
+ * @{
+ */
+#define XEMACPS_BD_ADDR_OFFSET 0x00000000U /**< word 0/addr of BDs */
+#define XEMACPS_BD_STAT_OFFSET 0x00000004U /**< word 1/status of BDs */
+#define XEMACPS_BD_ADDR_HI_OFFSET 0x00000008U /**< word 2/addr of BDs */
+
+/*
+ * @}
+ */
+
+/* Transmit buffer descriptor status words bit positions.
+ * Transmit buffer descriptor consists of two 32-bit registers,
+ * the first - word0 contains a 32-bit address pointing to the location of
+ * the transmit data.
+ * The following register - word1, consists of various information to control
+ * the XEmacPs transmit process. After transmit, this is updated with status
+ * information, whether the frame was transmitted OK or why it had failed.
+ * @{
+ */
+#define XEMACPS_TXBUF_USED_MASK 0x80000000U /**< Used bit. */
+#define XEMACPS_TXBUF_WRAP_MASK 0x40000000U /**< Wrap bit, last descriptor */
+#define XEMACPS_TXBUF_RETRY_MASK 0x20000000U /**< Retry limit exceeded */
+#define XEMACPS_TXBUF_URUN_MASK 0x10000000U /**< Transmit underrun occurred */
+#define XEMACPS_TXBUF_EXH_MASK 0x08000000U /**< Buffers exhausted */
+#define XEMACPS_TXBUF_TCP_MASK 0x04000000U /**< Late collision. */
+#define XEMACPS_TXBUF_NOCRC_MASK 0x00010000U /**< No CRC */
+#define XEMACPS_TXBUF_LAST_MASK 0x00008000U /**< Last buffer */
+#define XEMACPS_TXBUF_LEN_MASK 0x00003FFFU /**< Mask for length field */
+/*
+ * @}
+ */
+
+/* Receive buffer descriptor status words bit positions.
+ * Receive buffer descriptor consists of two 32-bit registers,
+ * the first - word0 contains a 32-bit word aligned address pointing to the
+ * address of the buffer. The lower two bits make up the wrap bit indicating
+ * the last descriptor and the ownership bit to indicate it has been used by
+ * the XEmacPs.
+ * The following register - word1, contains status information regarding why
+ * the frame was received (the filter match condition) as well as other
+ * useful info.
+ * @{
+ */
+#define XEMACPS_RXBUF_BCAST_MASK 0x80000000U /**< Broadcast frame */
+#define XEMACPS_RXBUF_MULTIHASH_MASK 0x40000000U /**< Multicast hashed frame */
+#define XEMACPS_RXBUF_UNIHASH_MASK 0x20000000U /**< Unicast hashed frame */
+#define XEMACPS_RXBUF_EXH_MASK 0x08000000U /**< buffer exhausted */
+#define XEMACPS_RXBUF_AMATCH_MASK 0x06000000U /**< Specific address
+ matched */
+#define XEMACPS_RXBUF_IDFOUND_MASK 0x01000000U /**< Type ID matched */
+#define XEMACPS_RXBUF_IDMATCH_MASK 0x00C00000U /**< ID matched mask */
+#define XEMACPS_RXBUF_VLAN_MASK 0x00200000U /**< VLAN tagged */
+#define XEMACPS_RXBUF_PRI_MASK 0x00100000U /**< Priority tagged */
+#define XEMACPS_RXBUF_VPRI_MASK 0x000E0000U /**< Vlan priority */
+#define XEMACPS_RXBUF_CFI_MASK 0x00010000U /**< CFI frame */
+#define XEMACPS_RXBUF_EOF_MASK 0x00008000U /**< End of frame. */
+#define XEMACPS_RXBUF_SOF_MASK 0x00004000U /**< Start of frame. */
+#define XEMACPS_RXBUF_LEN_MASK 0x00001FFFU /**< Mask for length field */
+#define XEMACPS_RXBUF_LEN_JUMBO_MASK 0x00003FFFU /**< Mask for jumbo length */
+
+#define XEMACPS_RXBUF_WRAP_MASK 0x00000002U /**< Wrap bit, last BD */
+#define XEMACPS_RXBUF_NEW_MASK 0x00000001U /**< Used bit.. */
+#define XEMACPS_RXBUF_ADD_MASK 0xFFFFFFFCU /**< Mask for address */
+/*
+ * @}
+ */
+
+/*
+ * Define appropriate I/O access method to memory mapped I/O or other
+ * interface if necessary.
+ */
+
+#define XEmacPs_In32 Xil_In32
+#define XEmacPs_Out32 Xil_Out32
+
+
+/****************************************************************************/
+/**
+*
+* Read the given register.
+*
+* @param BaseAddress is the base address of the device
+* @param RegOffset is the register offset to be read
+*
+* @return The 32-bit value of the register
+*
+* @note
+* C-style signature:
+* u32 XEmacPs_ReadReg(u32 BaseAddress, u32 RegOffset)
+*
+*****************************************************************************/
+#define XEmacPs_ReadReg(BaseAddress, RegOffset) \
+ XEmacPs_In32((BaseAddress) + (u32)(RegOffset))
+
+
+/****************************************************************************/
+/**
+*
+* Write the given register.
+*
+* @param BaseAddress is the base address of the device
+* @param RegOffset is the register offset to be written
+* @param Data is the 32-bit value to write to the register
+*
+* @return None.
+*
+* @note
+* C-style signature:
+* void XEmacPs_WriteReg(u32 BaseAddress, u32 RegOffset,
+* u32 Data)
+*
+*****************************************************************************/
+#define XEmacPs_WriteReg(BaseAddress, RegOffset, Data) \
+ XEmacPs_Out32((BaseAddress) + (u32)(RegOffset), (u32)(Data))
+
+/************************** Function Prototypes *****************************/
+/*
+ * Perform reset operation to the emacps interface
+ */
+void XEmacPs_ResetHw(u32 BaseAddr);
+
+#ifdef __cplusplus
+ }
+#endif
+
+#endif /* end of protection macro */
+/** @} */
diff --git a/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/include/xenv.h b/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/include/xenv.h
new file mode 100644
index 0000000..a52b909
--- /dev/null
+++ b/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/include/xenv.h
@@ -0,0 +1,181 @@
+/******************************************************************************
+*
+* Copyright (C) 2002 - 2015 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+* THE SOFTWARE.
+*
+*
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xenv.h
+*
+* Defines common services that are typically found in a host operating.
+* environment. This include file simply includes an OS specific file based
+* on the compile-time constant BUILD_ENV_*, where * is the name of the target
+* environment.
+*
+* All services are defined as macros.
+*
+* <pre>
+* MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ----- ---- -------- -----------------------------------------------
+* 1.00b ch 10/24/02 Added XENV_LINUX
+* 1.00a rmm 04/17/02 First release
+* </pre>
+*
+******************************************************************************/
+
+#ifndef XENV_H /* prevent circular inclusions */
+#define XENV_H /* by using protection macros */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+ * Select which target environment we are operating under
+ */
+
+/* VxWorks target environment */
+#if defined XENV_VXWORKS
+#include "xenv_vxworks.h"
+
+/* Linux target environment */
+#elif defined XENV_LINUX
+#include "xenv_linux.h"
+
+/* Unit test environment */
+#elif defined XENV_UNITTEST
+#include "ut_xenv.h"
+
+/* Integration test environment */
+#elif defined XENV_INTTEST
+#include "int_xenv.h"
+
+/* Standalone environment selected */
+#else
+#include "xenv_standalone.h"
+#endif
+
+
+/*
+ * The following comments specify the types and macro wrappers that are
+ * expected to be defined by the target specific header files
+ */
+
+/**************************** Type Definitions *******************************/
+
+/*****************************************************************************/
+/**
+ *
+ * XENV_TIME_STAMP
+ *
+ * A structure that contains a time stamp used by other time stamp macros
+ * defined below. This structure is processor dependent.
+ */
+
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/*****************************************************************************/
+/**
+ *
+ * XENV_MEM_COPY(void *DestPtr, void *SrcPtr, unsigned Bytes)
+ *
+ * Copies a non-overlapping block of memory.
+ *
+ * @param DestPtr is the destination address to copy data to.
+ * @param SrcPtr is the source address to copy data from.
+ * @param Bytes is the number of bytes to copy.
+ *
+ * @return None
+ */
+
+/*****************************************************************************/
+/**
+ *
+ * XENV_MEM_FILL(void *DestPtr, char Data, unsigned Bytes)
+ *
+ * Fills an area of memory with constant data.
+ *
+ * @param DestPtr is the destination address to set.
+ * @param Data contains the value to set.
+ * @param Bytes is the number of bytes to set.
+ *
+ * @return None
+ */
+/*****************************************************************************/
+/**
+ *
+ * XENV_TIME_STAMP_GET(XTIME_STAMP *StampPtr)
+ *
+ * Samples the processor's or external timer's time base counter.
+ *
+ * @param StampPtr is the storage for the retrieved time stamp.
+ *
+ * @return None
+ */
+
+/*****************************************************************************/
+/**
+ *
+ * XENV_TIME_STAMP_DELTA_US(XTIME_STAMP *Stamp1Ptr, XTIME_STAMP* Stamp2Ptr)
+ *
+ * Computes the delta between the two time stamps.
+ *
+ * @param Stamp1Ptr - First sampled time stamp.
+ * @param Stamp1Ptr - Sedond sampled time stamp.
+ *
+ * @return An unsigned int value with units of microseconds.
+ */
+
+/*****************************************************************************/
+/**
+ *
+ * XENV_TIME_STAMP_DELTA_MS(XTIME_STAMP *Stamp1Ptr, XTIME_STAMP* Stamp2Ptr)
+ *
+ * Computes the delta between the two time stamps.
+ *
+ * @param Stamp1Ptr - First sampled time stamp.
+ * @param Stamp1Ptr - Sedond sampled time stamp.
+ *
+ * @return An unsigned int value with units of milliseconds.
+ */
+
+/*****************************************************************************//**
+ *
+ * XENV_USLEEP(unsigned delay)
+ *
+ * Delay the specified number of microseconds.
+ *
+ * @param delay is the number of microseconds to delay.
+ *
+ * @return None
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* end of protection macro */
diff --git a/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/include/xenv_standalone.h b/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/include/xenv_standalone.h
new file mode 100644
index 0000000..4468abb
--- /dev/null
+++ b/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/include/xenv_standalone.h
@@ -0,0 +1,362 @@
+/******************************************************************************
+*
+* Copyright (C) 2002 - 2015 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+* THE SOFTWARE.
+*
+*
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xenv_standalone.h
+*
+* Defines common services specified by xenv.h.
+*
+* @note
+* This file is not intended to be included directly by driver code.
+* Instead, the generic xenv.h file is intended to be included by driver
+* code.
+*
+* <pre>
+* MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ----- ---- -------- -----------------------------------------------
+* 1.00a wgr 02/28/07 Added cache handling macros.
+* 1.00a wgr 02/27/07 Simplified code. Deprecated old-style macro names.
+* 1.00a rmm 01/24/06 Implemented XENV_USLEEP. Assume implementation is being
+* used under Xilinx standalone BSP.
+* 1.00a xd 11/03/04 Improved support for doxygen.
+* 1.00a rmm 03/21/02 First release
+* 1.00a wgr 03/22/07 Converted to new coding style.
+* 1.00a rpm 06/29/07 Added udelay macro for standalone
+* 1.00a xd 07/19/07 Included xparameters.h as XPAR_ constants are referred
+* to in MICROBLAZE section
+* 1.00a ecm 09/19/08 updated for v7.20 of Microblaze, new functionality
+*
+* </pre>
+*
+*
+******************************************************************************/
+
+#ifndef XENV_STANDALONE_H
+#define XENV_STANDALONE_H
+
+#include "xil_types.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/***************************** Include Files *********************************/
+/******************************************************************************
+ *
+ * Get the processor dependent includes
+ *
+ ******************************************************************************/
+
+#include <string.h>
+
+#if defined __MICROBLAZE__
+# include "mb_interface.h"
+# include "xparameters.h" /* XPAR constants used below in MB section */
+
+#elif defined __PPC__
+# include "sleep.h"
+# include "xcache_l.h" /* also include xcache_l.h for caching macros */
+#endif
+
+/******************************************************************************
+ *
+ * MEMCPY / MEMSET related macros.
+ *
+ * The following are straight forward implementations of memset and memcpy.
+ *
+ * NOTE: memcpy may not work if source and target memory area are overlapping.
+ *
+ ******************************************************************************/
+/*****************************************************************************/
+/**
+ *
+ * Copies a non-overlapping block of memory.
+ *
+ * @param DestPtr
+ * Destination address to copy data to.
+ *
+ * @param SrcPtr
+ * Source address to copy data from.
+ *
+ * @param Bytes
+ * Number of bytes to copy.
+ *
+ * @return None.
+ *
+ * @note
+ * The use of XENV_MEM_COPY is deprecated. Use memcpy() instead.
+ *
+ * @note
+ * This implementation MAY BREAK work if source and target memory
+ * area are overlapping.
+ *
+ *****************************************************************************/
+
+#define XENV_MEM_COPY(DestPtr, SrcPtr, Bytes) \
+ memcpy((void *) DestPtr, (const void *) SrcPtr, (size_t) Bytes)
+
+
+
+/*****************************************************************************/
+/**
+ *
+ * Fills an area of memory with constant data.
+ *
+ * @param DestPtr
+ * Destination address to copy data to.
+ *
+ * @param Data
+ * Value to set.
+ *
+ * @param Bytes
+ * Number of bytes to copy.
+ *
+ * @return None.
+ *
+ * @note
+ * The use of XENV_MEM_FILL is deprecated. Use memset() instead.
+ *
+ *****************************************************************************/
+
+#define XENV_MEM_FILL(DestPtr, Data, Bytes) \
+ memset((void *) DestPtr, (s32) Data, (size_t) Bytes)
+
+
+
+/******************************************************************************
+ *
+ * TIME related macros
+ *
+ ******************************************************************************/
+
+/**
+ * A structure that contains a time stamp used by other time stamp macros
+ * defined below. This structure is processor dependent.
+ */
+typedef s32 XENV_TIME_STAMP;
+
+/*****************************************************************************/
+/**
+ *
+ * Time is derived from the 64 bit PPC timebase register
+ *
+ * @param StampPtr is the storage for the retrieved time stamp.
+ *
+ * @return None.
+ *
+ * @note
+ *
+ * Signature: void XENV_TIME_STAMP_GET(XTIME_STAMP *StampPtr)
+ * <br><br>
+ * This macro must be implemented by the user.
+ *
+ *****************************************************************************/
+#define XENV_TIME_STAMP_GET(StampPtr)
+
+/*****************************************************************************/
+/**
+ *
+ * This macro is not yet implemented and always returns 0.
+ *
+ * @param Stamp1Ptr is the first sampled time stamp.
+ * @param Stamp2Ptr is the second sampled time stamp.
+ *
+ * @return 0
+ *
+ * @note
+ *
+ * This macro must be implemented by the user.
+ *
+ *****************************************************************************/
+#define XENV_TIME_STAMP_DELTA_US(Stamp1Ptr, Stamp2Ptr) (0)
+
+/*****************************************************************************/
+/**
+ *
+ * This macro is not yet implemented and always returns 0.
+ *
+ * @param Stamp1Ptr is the first sampled time stamp.
+ * @param Stamp2Ptr is the second sampled time stamp.
+ *
+ * @return 0
+ *
+ * @note
+ *
+ * This macro must be implemented by the user.
+ *
+ *****************************************************************************/
+#define XENV_TIME_STAMP_DELTA_MS(Stamp1Ptr, Stamp2Ptr) (0)
+
+/*****************************************************************************/
+/**
+ * XENV_USLEEP(unsigned delay)
+ *
+ * Delay the specified number of microseconds. Not implemented without OS
+ * support.
+ *
+ * @param delay
+ * Number of microseconds to delay.
+ *
+ * @return None.
+ *
+ *****************************************************************************/
+
+#ifdef __PPC__
+#define XENV_USLEEP(delay) usleep(delay)
+#define udelay(delay) usleep(delay)
+#else
+#define XENV_USLEEP(delay)
+#define udelay(delay)
+#endif
+
+
+/******************************************************************************
+ *
+ * CACHE handling macros / mappings
+ *
+ ******************************************************************************/
+/******************************************************************************
+ *
+ * Processor independent macros
+ *
+ ******************************************************************************/
+
+#define XCACHE_ENABLE_CACHE() \
+ { XCACHE_ENABLE_DCACHE(); XCACHE_ENABLE_ICACHE(); }
+
+#define XCACHE_DISABLE_CACHE() \
+ { XCACHE_DISABLE_DCACHE(); XCACHE_DISABLE_ICACHE(); }
+
+
+/******************************************************************************
+ *
+ * MicroBlaze case
+ *
+ * NOTE: Currently the following macros will only work on systems that contain
+ * only ONE MicroBlaze processor. Also, the macros will only be enabled if the
+ * system is built using a xparameters.h file.
+ *
+ ******************************************************************************/
+
+#if defined __MICROBLAZE__
+
+/* Check if MicroBlaze data cache was built into the core.
+ */
+#if (XPAR_MICROBLAZE_USE_DCACHE == 1)
+# define XCACHE_ENABLE_DCACHE() microblaze_enable_dcache()
+# define XCACHE_DISABLE_DCACHE() microblaze_disable_dcache()
+# define XCACHE_INVALIDATE_DCACHE() microblaze_invalidate_dcache()
+
+# define XCACHE_INVALIDATE_DCACHE_RANGE(Addr, Len) \
+ microblaze_invalidate_dcache_range((s32)(Addr), (s32)(Len))
+
+#if (XPAR_MICROBLAZE_DCACHE_USE_WRITEBACK == 1)
+# define XCACHE_FLUSH_DCACHE() microblaze_flush_dcache()
+# define XCACHE_FLUSH_DCACHE_RANGE(Addr, Len) \
+ microblaze_flush_dcache_range((s32)(Addr), (s32)(Len))
+#else
+# define XCACHE_FLUSH_DCACHE() microblaze_invalidate_dcache()
+# define XCACHE_FLUSH_DCACHE_RANGE(Addr, Len) \
+ microblaze_invalidate_dcache_range((s32)(Addr), (s32)(Len))
+#endif /*XPAR_MICROBLAZE_DCACHE_USE_WRITEBACK*/
+
+#else
+# define XCACHE_ENABLE_DCACHE()
+# define XCACHE_DISABLE_DCACHE()
+# define XCACHE_INVALIDATE_DCACHE_RANGE(Addr, Len)
+# define XCACHE_FLUSH_DCACHE_RANGE(Addr, Len)
+#endif /*XPAR_MICROBLAZE_USE_DCACHE*/
+
+
+/* Check if MicroBlaze instruction cache was built into the core.
+ */
+#if (XPAR_MICROBLAZE_USE_ICACHE == 1)
+# define XCACHE_ENABLE_ICACHE() microblaze_enable_icache()
+# define XCACHE_DISABLE_ICACHE() microblaze_disable_icache()
+
+# define XCACHE_INVALIDATE_ICACHE() microblaze_invalidate_icache()
+
+# define XCACHE_INVALIDATE_ICACHE_RANGE(Addr, Len) \
+ microblaze_invalidate_icache_range((s32)(Addr), (s32)(Len))
+
+#else
+# define XCACHE_ENABLE_ICACHE()
+# define XCACHE_DISABLE_ICACHE()
+#endif /*XPAR_MICROBLAZE_USE_ICACHE*/
+
+
+/******************************************************************************
+ *
+ * PowerPC case
+ *
+ * Note that the XCACHE_ENABLE_xxx functions are hardcoded to enable a
+ * specific memory region (0x80000001). Each bit (0-30) in the regions
+ * bitmask stands for 128MB of memory. Bit 31 stands for the upper 2GB
+ * range.
+ *
+ * regions --> cached address range
+ * ------------|--------------------------------------------------
+ * 0x80000000 | [0, 0x7FFFFFF]
+ * 0x00000001 | [0xF8000000, 0xFFFFFFFF]
+ * 0x80000001 | [0, 0x7FFFFFF],[0xF8000000, 0xFFFFFFFF]
+ *
+ ******************************************************************************/
+
+#elif defined __PPC__
+
+#define XCACHE_ENABLE_DCACHE() XCache_EnableDCache(0x80000001)
+#define XCACHE_DISABLE_DCACHE() XCache_DisableDCache()
+#define XCACHE_ENABLE_ICACHE() XCache_EnableICache(0x80000001)
+#define XCACHE_DISABLE_ICACHE() XCache_DisableICache()
+
+#define XCACHE_INVALIDATE_DCACHE_RANGE(Addr, Len) \
+ XCache_InvalidateDCacheRange((u32)(Addr), (u32)(Len))
+
+#define XCACHE_FLUSH_DCACHE_RANGE(Addr, Len) \
+ XCache_FlushDCacheRange((u32)(Addr), (u32)(Len))
+
+#define XCACHE_INVALIDATE_ICACHE() XCache_InvalidateICache()
+
+
+/******************************************************************************
+ *
+ * Unknown processor / architecture
+ *
+ ******************************************************************************/
+
+#else
+/* #error "Unknown processor / architecture. Must be MicroBlaze or PowerPC." */
+#endif
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* #ifndef XENV_STANDALONE_H */
diff --git a/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/include/xgpiops.h b/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/include/xgpiops.h
new file mode 100644
index 0000000..c0bdd6c
--- /dev/null
+++ b/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/include/xgpiops.h
@@ -0,0 +1,286 @@
+/******************************************************************************
+*
+* Copyright (C) 2010 - 2019 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+* THE SOFTWARE.
+*
+*
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xgpiops.h
+* @addtogroup gpiops_v3_6
+* @{
+* @details
+*
+* The Xilinx PS GPIO driver. This driver supports the Xilinx PS GPIO
+* Controller.
+*
+* The GPIO Controller supports the following features:
+* - 4 banks
+* - Masked writes (There are no masked reads)
+* - Bypass mode
+* - Configurable Interrupts (Level/Edge)
+*
+* This driver is intended to be RTOS and processor independent. Any needs for
+* dynamic memory management, threads or thread mutual exclusion, virtual
+* memory, or cache control must be satisfied by the layer above this driver.
+
+* This driver supports all the features listed above, if applicable.
+*
+* <b>Driver Description</b>
+*
+* The device driver enables higher layer software (e.g., an application) to
+* communicate to the GPIO.
+*
+* <b>Interrupts</b>
+*
+* The driver provides interrupt management functions and an interrupt handler.
+* Users of this driver need to provide callback functions. An interrupt handler
+* example is available with the driver.
+*
+* <b>Threads</b>
+*
+* This driver is not thread safe. Any needs for threads or thread mutual
+* exclusion must be satisfied by the layer above this driver.
+*
+* <b>Asserts</b>
+*
+* Asserts are used within all Xilinx drivers to enforce constraints on argument
+* values. Asserts can be turned off on a system-wide basis by defining, at
+* compile time, the NDEBUG identifier. By default, asserts are turned on and it
+* is recommended that users leave asserts on during development.
+*
+* <b>Building the driver</b>
+*
+* The XGpioPs driver is composed of several source files. This allows the user
+* to build and link only those parts of the driver that are necessary.
+* <br><br>
+*
+* <pre>
+* MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ----- ---- -------- -----------------------------------------------
+* 1.00a sv 01/15/10 First Release
+* 1.01a sv 04/15/12 Removed the APIs XGpioPs_SetMode, XGpioPs_SetModePin
+* XGpioPs_GetMode, XGpioPs_GetModePin as they are not
+* relevant to Zynq device.The interrupts are disabled
+* for output pins on all banks during initialization.
+* 1.02a hk 08/22/13 Added low level reset API
+* 2.1 hk 04/29/14 Use Input data register DATA_RO for read. CR# 771667.
+* 2.2 sk 10/13/14 Used Pin number in Bank instead of pin number
+* passed to APIs. CR# 822636
+* 3.00 kvn 02/13/15 Modified code for MISRA-C:2012 compliance.
+* 3.1 kvn 04/13/15 Add support for Zynq Ultrascale+ MP. CR# 856980.
+* ms 03/17/17 Added readme.txt file in examples folder for doxygen
+* generation.
+* ms 04/05/17 Added tabspace for return statements in functions of
+* gpiops examples for proper documentation while
+* generating doxygen.
+* 3.3 ms 04/17/17 Added notes about gpio input and output pin description
+* for zcu102 and zc702 boards in polled and interrupt
+* example, configured Interrupt pin to input pin for
+* proper functioning of interrupt example.
+* 3.4 aru 08/17/18 Resolved MISRA-C mandatory violations. CR# 1007751
+* 3.5 sne 03/01/19 Fixes violations according to MISRAC-2012
+* in safety mode and modified the code such as
+* Use of mixed mode arithmetic,Declared the pointer param
+* as Pointer to const,Casting operation to a pointer,
+* Literal value requires a U suffix.
+* 3.5 sne 03/14/19 Added Versal support.
+* 3.6 mus 04/05/19 Replaced XPLAT_versal macro with XPLAT_VERSAL, to be in
+* sync with standalone BSP
+* 3.6 sne 06/12/19 Fixed IAR compiler warning.
+* 3.6 sne 08/14/19 Added interrupt handler support on versal.
+*
+* </pre>
+*
+******************************************************************************/
+#ifndef XGPIOPS_H /* prevent circular inclusions */
+#define XGPIOPS_H /* by using protection macros */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/***************************** Include Files *********************************/
+
+#include "xstatus.h"
+#include "xgpiops_hw.h"
+#include "xplatform_info.h"
+
+/************************** Constant Definitions *****************************/
+
+/** @name Interrupt types
+ * @{
+ * The following constants define the interrupt types that can be set for each
+ * GPIO pin.
+ */
+#define XGPIOPS_IRQ_TYPE_EDGE_RISING 0x00U /**< Interrupt on Rising edge */
+#define XGPIOPS_IRQ_TYPE_EDGE_FALLING 0x01U /**< Interrupt Falling edge */
+#define XGPIOPS_IRQ_TYPE_EDGE_BOTH 0x02U /**< Interrupt on both edges */
+#define XGPIOPS_IRQ_TYPE_LEVEL_HIGH 0x03U /**< Interrupt on high level */
+#define XGPIOPS_IRQ_TYPE_LEVEL_LOW 0x04U /**< Interrupt on low level */
+/*@}*/
+
+#define XGPIOPS_BANK_MAX_PINS (u32)32 /**< Max pins in a GPIO bank */
+#define XGPIOPS_BANK0 0x00U /**< GPIO Bank 0 */
+#define XGPIOPS_BANK1 0x01U /**< GPIO Bank 1 */
+#define XGPIOPS_BANK2 0x02U /**< GPIO Bank 2 */
+#define XGPIOPS_BANK3 0x03U /**< GPIO Bank 3 */
+
+#ifdef XPAR_PSU_GPIO_0_BASEADDR
+#define XGPIOPS_BANK4 0x04U /**< GPIO Bank 4 */
+#define XGPIOPS_BANK5 0x05U /**< GPIO Bank 5 */
+#endif
+
+#define XGPIOPS_MAX_BANKS_ZYNQMP 0x06U /**< Max banks in a
+ * Zynq Ultrascale+ MP GPIO device
+ */
+#define XGPIOPS_MAX_BANKS 0x04U /**< Max banks in a Zynq GPIO device */
+
+#define XGPIOPS_DEVICE_MAX_PIN_NUM_ZYNQMP (u32)174 /**< Max pins in the
+ * Zynq Ultrascale+ MP GPIO device
+ * 0 - 25, Bank 0
+ * 26 - 51, Bank 1
+ * 52 - 77, Bank 2
+ * 78 - 109, Bank 3
+ * 110 - 141, Bank 4
+ * 142 - 173, Bank 5
+ */
+#define XGPIOPS_DEVICE_MAX_PIN_NUM (u32)118 /**< Max pins in the Zynq GPIO device
+ * 0 - 31, Bank 0
+ * 32 - 53, Bank 1
+ * 54 - 85, Bank 2
+ * 86 - 117, Bank 3
+ */
+
+/**************************** Type Definitions *******************************/
+
+/****************************************************************************/
+/**
+ * This handler data type allows the user to define a callback function to
+ * handle the interrupts for the GPIO device. The application using this
+ * driver is expected to define a handler of this type, to support interrupt
+ * driven mode. The handler executes in an interrupt context such that minimal
+ * processing should be performed.
+ *
+ * @param CallBackRef is a callback reference passed in by the upper layer
+ * when setting the callback functions for a GPIO bank. It is
+ * passed back to the upper layer when the callback is invoked. Its
+ * type is not important to the driver component, so it is a void
+ * pointer.
+ * @param Bank is the bank for which the interrupt status has changed.
+ * @param Status is the Interrupt status of the GPIO bank.
+ *
+ *****************************************************************************/
+typedef void (*XGpioPs_Handler) (void *CallBackRef, u32 Bank, u32 Status);
+
+/**
+ * This typedef contains configuration information for a device.
+ */
+typedef struct {
+ u16 DeviceId; /**< Unique ID of device */
+ u32 BaseAddr; /**< Register base address */
+} XGpioPs_Config;
+
+/**
+ * The XGpioPs driver instance data. The user is required to allocate a
+ * variable of this type for the GPIO device in the system. A pointer
+ * to a variable of this type is then passed to the driver API functions.
+ */
+typedef struct {
+ XGpioPs_Config GpioConfig; /**< Device configuration */
+ u32 IsReady; /**< Device is initialized and ready */
+ XGpioPs_Handler Handler; /**< Status handlers for all banks */
+ void *CallBackRef; /**< Callback ref for bank handlers */
+ u32 Platform; /**< Platform data */
+ u32 MaxPinNum; /**< Max pins in the GPIO device */
+ u8 MaxBanks; /**< Max banks in a GPIO device */
+ u32 PmcGpio; /**< Flag for accessing PS GPIO for versal*/
+} XGpioPs;
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/************************** Function Prototypes ******************************/
+
+/* Functions in xgpiops.c */
+s32 XGpioPs_CfgInitialize(XGpioPs *InstancePtr, const XGpioPs_Config *ConfigPtr,
+ u32 EffectiveAddr);
+
+/* Bank APIs in xgpiops.c */
+u32 XGpioPs_Read(const XGpioPs *InstancePtr, u8 Bank);
+void XGpioPs_Write(const XGpioPs *InstancePtr, u8 Bank, u32 Data);
+void XGpioPs_SetDirection(const XGpioPs *InstancePtr, u8 Bank, u32 Direction);
+u32 XGpioPs_GetDirection(const XGpioPs *InstancePtr, u8 Bank);
+void XGpioPs_SetOutputEnable(const XGpioPs *InstancePtr, u8 Bank, u32 OpEnable);
+u32 XGpioPs_GetOutputEnable(const XGpioPs *InstancePtr, u8 Bank);
+#ifdef versal
+void XGpioPs_GetBankPin(const XGpioPs *InstancePtr,u8 PinNumber,u8 *BankNumber, u8 *PinNumberInBank);
+#else
+void XGpioPs_GetBankPin(u8 PinNumber,u8 *BankNumber, u8 *PinNumberInBank);
+#endif
+
+/* Pin APIs in xgpiops.c */
+u32 XGpioPs_ReadPin(const XGpioPs *InstancePtr, u32 Pin);
+void XGpioPs_WritePin(const XGpioPs *InstancePtr, u32 Pin, u32 Data);
+void XGpioPs_SetDirectionPin(const XGpioPs *InstancePtr, u32 Pin, u32 Direction);
+u32 XGpioPs_GetDirectionPin(const XGpioPs *InstancePtr, u32 Pin);
+void XGpioPs_SetOutputEnablePin(const XGpioPs *InstancePtr, u32 Pin, u32 OpEnable);
+u32 XGpioPs_GetOutputEnablePin(const XGpioPs *InstancePtr, u32 Pin);
+
+/* Diagnostic functions in xgpiops_selftest.c */
+s32 XGpioPs_SelfTest(const XGpioPs *InstancePtr);
+
+/* Functions in xgpiops_intr.c */
+/* Bank APIs in xgpiops_intr.c */
+void XGpioPs_IntrEnable(const XGpioPs *InstancePtr, u8 Bank, u32 Mask);
+void XGpioPs_IntrDisable(const XGpioPs *InstancePtr, u8 Bank, u32 Mask);
+u32 XGpioPs_IntrGetEnabled(const XGpioPs *InstancePtr, u8 Bank);
+u32 XGpioPs_IntrGetStatus(const XGpioPs *InstancePtr, u8 Bank);
+void XGpioPs_IntrClear(const XGpioPs *InstancePtr, u8 Bank, u32 Mask);
+void XGpioPs_SetIntrType(const XGpioPs *InstancePtr, u8 Bank, u32 IntrType,
+ u32 IntrPolarity, u32 IntrOnAny);
+void XGpioPs_GetIntrType(const XGpioPs *InstancePtr, u8 Bank, u32 *IntrType,
+ u32 *IntrPolarity, u32 *IntrOnAny);
+void XGpioPs_SetCallbackHandler(XGpioPs *InstancePtr, void *CallBackRef,
+ XGpioPs_Handler FuncPointer);
+void XGpioPs_IntrHandler(const XGpioPs *InstancePtr);
+
+/* Pin APIs in xgpiops_intr.c */
+void XGpioPs_SetIntrTypePin(const XGpioPs *InstancePtr, u32 Pin, u8 IrqType);
+u8 XGpioPs_GetIntrTypePin(const XGpioPs *InstancePtr, u32 Pin);
+
+void XGpioPs_IntrEnablePin(const XGpioPs *InstancePtr, u32 Pin);
+void XGpioPs_IntrDisablePin(const XGpioPs *InstancePtr, u32 Pin);
+u32 XGpioPs_IntrGetEnabledPin(const XGpioPs *InstancePtr, u32 Pin);
+u32 XGpioPs_IntrGetStatusPin(const XGpioPs *InstancePtr, u32 Pin);
+void XGpioPs_IntrClearPin(const XGpioPs *InstancePtr, u32 Pin);
+
+/* Functions in xgpiops_sinit.c */
+XGpioPs_Config *XGpioPs_LookupConfig(u16 DeviceId);
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* end of protection macro */
+/** @} */
diff --git a/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/include/xgpiops_hw.h b/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/include/xgpiops_hw.h
new file mode 100644
index 0000000..ff47048
--- /dev/null
+++ b/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/include/xgpiops_hw.h
@@ -0,0 +1,166 @@
+/******************************************************************************
+*
+* Copyright (C) 2010 - 2019 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+* THE SOFTWARE.
+*
+*
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xgpiops_hw.h
+* @addtogroup gpiops_v3_6
+* @{
+*
+* This header file contains the identifiers and basic driver functions (or
+* macros) that can be used to access the device. Other driver functions
+* are defined in xgpiops.h.
+*
+* <pre>
+* MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ----- ---- -------- -------------------------------------------------
+* 1.00a sv 01/15/10 First Release
+* 1.02a hk 08/22/13 Added low level reset API function prototype and
+* related constant definitions
+* 3.00 kvn 02/13/15 Modified code for MISRA-C:2012 compliance.
+* 3.1 kvn 04/13/15 Corrected reset values of banks.
+* 3.5 sne 03/14/19 Added versal support.
+* </pre>
+*
+******************************************************************************/
+#ifndef XGPIOPS_HW_H /* prevent circular inclusions */
+#define XGPIOPS_HW_H /* by using protection macros */
+
+#ifdef __cplusplus
+extern "C" {
+#endif /* __cplusplus */
+
+/***************************** Include Files *********************************/
+
+#include "xil_types.h"
+#include "xil_assert.h"
+#include "xil_io.h"
+
+/************************** Constant Definitions *****************************/
+
+/** @name Register offsets for the GPIO. Each register is 32 bits.
+ * @{
+ */
+#define XGPIOPS_DATA_LSW_OFFSET 0x00000000U /* Mask and Data Register LSW, WO */
+#define XGPIOPS_DATA_MSW_OFFSET 0x00000004U /* Mask and Data Register MSW, WO */
+#define XGPIOPS_DATA_OFFSET 0x00000040U /* Data Register, RW */
+#define XGPIOPS_DATA_RO_OFFSET 0x00000060U /* Data Register - Input, RO */
+#define XGPIOPS_DIRM_OFFSET 0x00000204U /* Direction Mode Register, RW */
+#define XGPIOPS_OUTEN_OFFSET 0x00000208U /* Output Enable Register, RW */
+#define XGPIOPS_INTMASK_OFFSET 0x0000020CU /* Interrupt Mask Register, RO */
+#define XGPIOPS_INTEN_OFFSET 0x00000210U /* Interrupt Enable Register, WO */
+#define XGPIOPS_INTDIS_OFFSET 0x00000214U /* Interrupt Disable Register, WO*/
+#define XGPIOPS_INTSTS_OFFSET 0x00000218U /* Interrupt Status Register, RO */
+#define XGPIOPS_INTTYPE_OFFSET 0x0000021CU /* Interrupt Type Register, RW */
+#define XGPIOPS_INTPOL_OFFSET 0x00000220U /* Interrupt Polarity Register, RW */
+#define XGPIOPS_INTANY_OFFSET 0x00000224U /* Interrupt On Any Register, RW */
+/* @} */
+
+/** @name Register offsets for each Bank.
+ * @{
+ */
+#define XGPIOPS_DATA_MASK_OFFSET 0x00000008U /* Data/Mask Registers offset */
+#define XGPIOPS_DATA_BANK_OFFSET 0x00000004U /* Data Registers offset */
+#define XGPIOPS_REG_MASK_OFFSET 0x00000040U /* Registers offset */
+/* @} */
+
+/* For backwards compatibility */
+#define XGPIOPS_BYPM_MASK_OFFSET (u32)0x40
+
+/** @name Interrupt type reset values for each bank
+ * @{
+ */
+#ifdef XPAR_PSU_GPIO_0_BASEADDR
+#define XGPIOPS_INTTYPE_BANK0_RESET 0x03FFFFFFU /* Resets specific to Zynq Ultrascale+ MP */
+#define XGPIOPS_INTTYPE_BANK1_RESET 0x03FFFFFFU
+#define XGPIOPS_INTTYPE_BANK2_RESET 0x03FFFFFFU
+#else
+#define XGPIOPS_INTTYPE_BANK0_RESET 0xFFFFFFFFU /* Resets specific to Zynq */
+#define XGPIOPS_INTTYPE_BANK1_RESET 0x003FFFFFU
+#define XGPIOPS_INTTYPE_BANK2_RESET 0xFFFFFFFFU
+#endif
+
+#define XGPIOPS_INTTYPE_BANK3_RESET 0xFFFFFFFFU /* Reset common to both platforms */
+#define XGPIOPS_INTTYPE_BANK4_RESET 0xFFFFFFFFU /* Resets specific to Zynq Ultrascale+ MP */
+#define XGPIOPS_INTTYPE_BANK5_RESET 0xFFFFFFFFU
+/* @} */
+#define XGPIOPS_PS_GPIO_BASEADDR 0xFF0B0000U /* Flag for Base Address for PS_GPIO in Versal */
+#define XGPIOPS_ZERO 0U /* Flag for 0 Value */
+#define XGPIOPS_ONE 1U /* Flag for 1 Value */
+#define XGPIOPS_TWO 2U /* Flag for 2 Value */
+#define XGPIOPS_THREE 3U /* Flag for 3 Value */
+#define XGPIOPS_FOUR 4U /* Flag for 4 Value */
+#define XGPIOPS_SIX 6U /* Flag for 6 Value */
+
+/**************************** Type Definitions *******************************/
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/****************************************************************************/
+/**
+*
+* This macro reads the given register.
+*
+* @param BaseAddr is the base address of the device.
+* @param RegOffset is the register offset to be read.
+*
+* @return The 32-bit value of the register
+*
+* @note None.
+*
+*****************************************************************************/
+#define XGpioPs_ReadReg(BaseAddr, RegOffset) \
+ Xil_In32((BaseAddr) + (u32)(RegOffset))
+
+/****************************************************************************/
+/**
+*
+* This macro writes to the given register.
+*
+* @param BaseAddr is the base address of the device.
+* @param RegOffset is the offset of the register to be written.
+* @param Data is the 32-bit value to write to the register.
+*
+* @return None.
+*
+* @note None.
+*
+*****************************************************************************/
+#define XGpioPs_WriteReg(BaseAddr, RegOffset, Data) \
+ Xil_Out32((BaseAddr) + (u32)(RegOffset), (u32)(Data))
+
+/************************** Function Prototypes ******************************/
+
+void XGpioPs_ResetHw(u32 BaseAddress);
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+
+#endif /* XGPIOPS_HW_H */
+/** @} */
diff --git a/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/include/xil_assert.h b/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/include/xil_assert.h
new file mode 100644
index 0000000..489c62c
--- /dev/null
+++ b/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/include/xil_assert.h
@@ -0,0 +1,189 @@
+/******************************************************************************
+*
+* Copyright (C) 2009 - 2018 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+* THE SOFTWARE.
+*
+*
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xil_assert.h
+*
+* @addtogroup common_assert_apis Assert APIs and Macros
+*
+* The xil_assert.h file contains assert related functions and macros.
+* Assert APIs/Macros specifies that a application program satisfies certain
+* conditions at particular points in its execution. These function can be
+* used by application programs to ensure that, application code is satisfying
+* certain conditions.
+*
+* @{
+* <pre>
+* MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ----- ---- -------- -------------------------------------------------------
+* 1.00a hbm 07/14/09 First release
+* 6.0 kvn 05/31/16 Make Xil_AsserWait a global variable
+* </pre>
+*
+******************************************************************************/
+
+#ifndef XIL_ASSERT_H /* prevent circular inclusions */
+#define XIL_ASSERT_H /* by using protection macros */
+
+#include "xil_types.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+
+/***************************** Include Files *********************************/
+
+
+/************************** Constant Definitions *****************************/
+
+#define XIL_ASSERT_NONE 0U
+#define XIL_ASSERT_OCCURRED 1U
+#define XNULL NULL
+
+extern u32 Xil_AssertStatus;
+extern s32 Xil_AssertWait;
+extern void Xil_Assert(const char8 *File, s32 Line);
+void XNullHandler(void *NullParameter);
+
+/**
+ * This data type defines a callback to be invoked when an
+ * assert occurs. The callback is invoked only when asserts are enabled
+ */
+typedef void (*Xil_AssertCallback) (const char8 *File, s32 Line);
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+#ifndef NDEBUG
+
+/*****************************************************************************/
+/**
+* @brief This assert macro is to be used for void functions. This in
+* conjunction with the Xil_AssertWait boolean can be used to
+* accommodate tests so that asserts which fail allow execution to
+* continue.
+*
+* @param Expression: expression to be evaluated. If it evaluates to
+* false, the assert occurs.
+*
+* @return Returns void unless the Xil_AssertWait variable is true, in which
+* case no return is made and an infinite loop is entered.
+*
+******************************************************************************/
+#define Xil_AssertVoid(Expression) \
+{ \
+ if (Expression) { \
+ Xil_AssertStatus = XIL_ASSERT_NONE; \
+ } else { \
+ Xil_Assert(__FILE__, __LINE__); \
+ Xil_AssertStatus = XIL_ASSERT_OCCURRED; \
+ return; \
+ } \
+}
+
+/*****************************************************************************/
+/**
+* @brief This assert macro is to be used for functions that do return a
+* value. This in conjunction with the Xil_AssertWait boolean can be
+* used to accommodate tests so that asserts which fail allow execution
+* to continue.
+*
+* @param Expression: expression to be evaluated. If it evaluates to false,
+* the assert occurs.
+*
+* @return Returns 0 unless the Xil_AssertWait variable is true, in which
+* case no return is made and an infinite loop is entered.
+*
+******************************************************************************/
+#define Xil_AssertNonvoid(Expression) \
+{ \
+ if (Expression) { \
+ Xil_AssertStatus = XIL_ASSERT_NONE; \
+ } else { \
+ Xil_Assert(__FILE__, __LINE__); \
+ Xil_AssertStatus = XIL_ASSERT_OCCURRED; \
+ return 0; \
+ } \
+}
+
+/*****************************************************************************/
+/**
+* @brief Always assert. This assert macro is to be used for void functions.
+* Use for instances where an assert should always occur.
+*
+* @return Returns void unless the Xil_AssertWait variable is true, in which
+* case no return is made and an infinite loop is entered.
+*
+******************************************************************************/
+#define Xil_AssertVoidAlways() \
+{ \
+ Xil_Assert(__FILE__, __LINE__); \
+ Xil_AssertStatus = XIL_ASSERT_OCCURRED; \
+ return; \
+}
+
+/*****************************************************************************/
+/**
+* @brief Always assert. This assert macro is to be used for functions that
+* do return a value. Use for instances where an assert should always
+* occur.
+*
+* @return Returns void unless the Xil_AssertWait variable is true, in which
+* case no return is made and an infinite loop is entered.
+*
+******************************************************************************/
+#define Xil_AssertNonvoidAlways() \
+{ \
+ Xil_Assert(__FILE__, __LINE__); \
+ Xil_AssertStatus = XIL_ASSERT_OCCURRED; \
+ return 0; \
+}
+
+
+#else
+
+#define Xil_AssertVoid(Expression)
+#define Xil_AssertVoidAlways()
+#define Xil_AssertNonvoid(Expression)
+#define Xil_AssertNonvoidAlways()
+
+#endif
+
+/************************** Function Prototypes ******************************/
+
+void Xil_AssertSetCallback(Xil_AssertCallback Routine);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* end of protection macro */
+/**
+* @} End of "addtogroup common_assert_apis".
+*/
diff --git a/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/include/xil_cache.h b/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/include/xil_cache.h
new file mode 100644
index 0000000..6304a00
--- /dev/null
+++ b/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/include/xil_cache.h
@@ -0,0 +1,116 @@
+/******************************************************************************
+*
+* Copyright (C) 2010 - 2018 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+* THE SOFTWARE.
+*
+*
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xil_cache.h
+*
+* @addtogroup a9_cache_apis Cortex A9 Processor Cache Functions
+*
+* Cache functions provide access to cache related operations such as flush
+* and invalidate for instruction and data caches. It gives option to perform
+* the cache operations on a single cacheline, a range of memory and an entire
+* cache.
+*
+* @{
+*
+* <pre>
+* MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ----- ---- -------- -----------------------------------------------
+* 1.00a ecm 01/29/10 First release
+* 3.04a sdm 01/02/12 Remove redundant dsb/dmb instructions in cache maintenance
+* APIs.
+* 6.8 aru 09/06/18 Removed compilation warnings for ARMCC toolchain.
+* </pre>
+*
+******************************************************************************/
+#ifndef XIL_CACHE_H
+#define XIL_CACHE_H
+
+#include "xil_types.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#ifdef __GNUC__
+
+#define asm_cp15_inval_dc_line_mva_poc(param) __asm__ __volatile__("mcr " \
+ XREG_CP15_INVAL_DC_LINE_MVA_POC :: "r" (param));
+
+#define asm_cp15_clean_inval_dc_line_mva_poc(param) __asm__ __volatile__("mcr " \
+ XREG_CP15_CLEAN_INVAL_DC_LINE_MVA_POC :: "r" (param));
+
+#define asm_cp15_inval_ic_line_mva_pou(param) __asm__ __volatile__("mcr " \
+ XREG_CP15_INVAL_IC_LINE_MVA_POU :: "r" (param));
+
+#define asm_cp15_inval_dc_line_sw(param) __asm__ __volatile__("mcr " \
+ XREG_CP15_INVAL_DC_LINE_SW :: "r" (param));
+
+#define asm_cp15_clean_inval_dc_line_sw(param) __asm__ __volatile__("mcr " \
+ XREG_CP15_CLEAN_INVAL_DC_LINE_SW :: "r" (param));
+
+#elif defined (__ICCARM__)
+
+#define asm_cp15_inval_dc_line_mva_poc(param) __asm volatile ("mcr " \
+ XREG_CP15_INVAL_DC_LINE_MVA_POC :: "r" (param));
+
+#define asm_cp15_clean_inval_dc_line_mva_poc(param) __asm volatile ("mcr " \
+ XREG_CP15_CLEAN_INVAL_DC_LINE_MVA_POC :: "r" (param));
+
+#define asm_cp15_inval_ic_line_mva_pou(param) __asm volatile ("mcr " \
+ XREG_CP15_INVAL_IC_LINE_MVA_POU :: "r" (param));
+
+#define asm_cp15_inval_dc_line_sw(param) __asm volatile ("mcr " \
+ XREG_CP15_INVAL_DC_LINE_SW :: "r" (param));
+
+#define asm_cp15_clean_inval_dc_line_sw(param) __asm volatile ("mcr " \
+ XREG_CP15_CLEAN_INVAL_DC_LINE_SW :: "r" (param));
+
+#endif
+
+void Xil_DCacheEnable(void);
+void Xil_DCacheDisable(void);
+void Xil_DCacheInvalidate(void);
+void Xil_DCacheInvalidateRange(INTPTR adr, u32 len);
+void Xil_DCacheFlush(void);
+void Xil_DCacheFlushRange(INTPTR adr, u32 len);
+
+void Xil_ICacheEnable(void);
+void Xil_ICacheDisable(void);
+void Xil_ICacheInvalidate(void);
+void Xil_ICacheInvalidateRange(INTPTR adr, u32 len);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
+/**
+* @} End of "addtogroup a9_cache_apis".
+*/
diff --git a/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/include/xil_cache_l.h b/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/include/xil_cache_l.h
new file mode 100644
index 0000000..60601b2
--- /dev/null
+++ b/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/include/xil_cache_l.h
@@ -0,0 +1,95 @@
+/******************************************************************************
+*
+* Copyright (C) 2010 - 2018 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+* THE SOFTWARE.
+*
+*
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xil_cache_l.h
+*
+* Contains L1 and L2 specific functions for the ARM cache functionality
+* used by xcache.c. This functionality is being made available here for
+* more sophisticated users.
+*
+* @addtogroup a9_cache_apis
+* @{
+* <pre>
+* MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ----- ---- -------- -----------------------------------------------
+* 1.00a ecm 01/24/10 First release
+* 6.8 aru 09/06/18 Removed compilation warnings for ARMCC toolchain.
+* </pre>
+*
+******************************************************************************/
+#ifndef XIL_CACHE_MACH_H
+#define XIL_CACHE_MACH_H
+
+#include "xil_types.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/************************** Function Prototypes ******************************/
+
+void Xil_DCacheInvalidateLine(u32 adr);
+void Xil_DCacheFlushLine(u32 adr);
+void Xil_DCacheStoreLine(u32 adr);
+void Xil_ICacheInvalidateLine(u32 adr);
+
+void Xil_L1DCacheEnable(void);
+void Xil_L1DCacheDisable(void);
+void Xil_L1DCacheInvalidate(void);
+void Xil_L1DCacheInvalidateLine(u32 adr);
+void Xil_L1DCacheInvalidateRange(u32 adr, u32 len);
+void Xil_L1DCacheFlush(void);
+void Xil_L1DCacheFlushLine(u32 adr);
+void Xil_L1DCacheFlushRange(u32 adr, u32 len);
+void Xil_L1DCacheStoreLine(u32 adr);
+
+void Xil_L1ICacheEnable(void);
+void Xil_L1ICacheDisable(void);
+void Xil_L1ICacheInvalidate(void);
+void Xil_L1ICacheInvalidateLine(u32 adr);
+void Xil_L1ICacheInvalidateRange(u32 adr, u32 len);
+
+void Xil_L2CacheEnable(void);
+void Xil_L2CacheDisable(void);
+void Xil_L2CacheInvalidate(void);
+void Xil_L2CacheInvalidateLine(u32 adr);
+void Xil_L2CacheInvalidateRange(u32 adr, u32 len);
+void Xil_L2CacheFlush(void);
+void Xil_L2CacheFlushLine(u32 adr);
+void Xil_L2CacheFlushRange(u32 adr, u32 len);
+void Xil_L2CacheStoreLine(u32 adr);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
+/**
+* @} End of "addtogroup a9_cache_apis".
+*/
diff --git a/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/include/xil_cache_vxworks.h b/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/include/xil_cache_vxworks.h
new file mode 100644
index 0000000..730d526
--- /dev/null
+++ b/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/include/xil_cache_vxworks.h
@@ -0,0 +1,87 @@
+/******************************************************************************
+*
+* Copyright (C) 2009 - 2015 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+* THE SOFTWARE.
+*
+*
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xil_cache_vxworks.h
+*
+* Contains the cache related functions for VxWorks that is wrapped by
+* xil_cache.
+*
+* <pre>
+* MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ----- ---- -------- -------------------------------------------------------
+* 1.00a hbm 12/11/09 Initial release
+*
+* </pre>
+*
+* @note
+*
+******************************************************************************/
+
+#ifndef XIL_CACHE_VXWORKS_H
+#define XIL_CACHE_VXWORKS_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include "vxWorks.h"
+#include "vxLib.h"
+#include "sysLibExtra.h"
+#include "cacheLib.h"
+
+#if (CPU_FAMILY==PPC)
+
+#define Xil_DCacheEnable() cacheEnable(DATA_CACHE)
+
+#define Xil_DCacheDisable() cacheDisable(DATA_CACHE)
+
+#define Xil_DCacheInvalidateRange(Addr, Len) \
+ cacheInvalidate(DATA_CACHE, (void *)(Addr), (Len))
+
+#define Xil_DCacheFlushRange(Addr, Len) \
+ cacheFlush(DATA_CACHE, (void *)(Addr), (Len))
+
+#define Xil_ICacheEnable() cacheEnable(INSTRUCTION_CACHE)
+
+#define Xil_ICacheDisable() cacheDisable(INSTRUCTION_CACHE)
+
+#define Xil_ICacheInvalidateRange(Addr, Len) \
+ cacheInvalidate(INSTRUCTION_CACHE, (void *)(Addr), (Len))
+
+
+#else
+#error "Unknown processor / architecture. Must be PPC for VxWorks."
+#endif
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff --git a/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/include/xil_errata.h b/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/include/xil_errata.h
new file mode 100644
index 0000000..1ce2d64
--- /dev/null
+++ b/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/include/xil_errata.h
@@ -0,0 +1,125 @@
+/******************************************************************************
+*
+* Copyright (C) 2013 - 2015 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+* THE SOFTWARE.
+*
+*
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xil_errata.h
+*
+* @addtogroup a9_errata Cortex A9 Processor and pl310 Errata Support
+* @{
+* Various ARM errata are handled in the standalone BSP. The implementation for
+* errata handling follows ARM guidelines and is based on the open source Linux
+* support for these errata.
+*
+* @note
+* The errata handling is enabled by default. To disable handling of all the
+* errata globally, un-define the macro ENABLE_ARM_ERRATA in xil_errata.h. To
+* disable errata on a per-erratum basis, un-define relevant macros in
+* xil_errata.h.
+*
+* <pre>
+* MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ----- ---- -------- -----------------------------------------------
+* 1.00a srt 04/18/13 First release
+* 6.6 mus 12/07/17 Removed errata 753970, It fixes CR#989132.
+* </pre>
+*
+******************************************************************************/
+#ifndef XIL_ERRATA_H
+#define XIL_ERRATA_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * @name errata_definitions
+ *
+ * The errata conditions handled in the standalone BSP are listed below
+ * @{
+ */
+
+#define ENABLE_ARM_ERRATA 1
+
+#ifdef ENABLE_ARM_ERRATA
+
+/**
+ * Errata No: 742230
+ * Description: DMB operation may be faulty
+ */
+#define CONFIG_ARM_ERRATA_742230 1
+
+/**
+ * Errata No: 743622
+ * Description: Faulty hazard checking in the Store Buffer may lead
+ * to data corruption.
+ */
+#define CONFIG_ARM_ERRATA_743622 1
+
+/**
+ * Errata No: 775420
+ * Description: A data cache maintenance operation which aborts,
+ * might lead to deadlock
+ */
+#define CONFIG_ARM_ERRATA_775420 1
+
+/**
+ * Errata No: 794073
+ * Description: Speculative instruction fetches with MMU disabled
+ * might not comply with architectural requirements
+ */
+#define CONFIG_ARM_ERRATA_794073 1
+
+
+/** PL310 L2 Cache Errata */
+
+/**
+ * Errata No: 588369
+ * Description: Clean & Invalidate maintenance operations do not
+ * invalidate clean lines
+ */
+#define CONFIG_PL310_ERRATA_588369 1
+
+/**
+ * Errata No: 727915
+ * Description: Background Clean and Invalidate by Way operation
+ * can cause data corruption
+ */
+#define CONFIG_PL310_ERRATA_727915 1
+
+/*@}*/
+#endif /* ENABLE_ARM_ERRATA */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* XIL_ERRATA_H */
+/**
+* @} End of "addtogroup a9_errata".
+*/
diff --git a/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/include/xil_exception.h b/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/include/xil_exception.h
new file mode 100644
index 0000000..0f03e0a
--- /dev/null
+++ b/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/include/xil_exception.h
@@ -0,0 +1,283 @@
+/******************************************************************************
+*
+* Copyright (C) 2015 - 2016 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+* THE SOFTWARE.
+*
+*
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xil_exception.h
+*
+* This header file contains ARM Cortex A53,A9,R5 specific exception related APIs.
+* For exception related functions that can be used across all Xilinx supported
+* processors, please use xil_exception.h.
+*
+* @addtogroup arm_exception_apis ARM Processor Exception Handling
+* @{
+* ARM processors specific exception related APIs for cortex A53,A9 and R5 can
+* utilized for enabling/disabling IRQ, registering/removing handler for
+* exceptions or initializing exception vector table with null handler.
+*
+* <pre>
+* MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ----- -------- -------- -----------------------------------------------
+* 5.2 pkp 28/05/15 First release
+* 6.0 mus 27/07/16 Consolidated file for a53,a9 and r5 processors
+* 6.7 mna 26/04/18 Add API Xil_GetExceptionRegisterHandler.
+* 6.7 asa 18/05/18 Update signature of API Xil_GetExceptionRegisterHandler.
+* 7.0 mus 01/03/19 Tweak Xil_ExceptionEnableMask and
+* Xil_ExceptionDisableMask macros to support legacy
+* examples for Cortexa72 EL3 exception level.
+* </pre>
+*
+******************************************************************************/
+
+#ifndef XIL_EXCEPTION_H /* prevent circular inclusions */
+#define XIL_EXCEPTION_H /* by using protection macros */
+
+/***************************** Include Files ********************************/
+
+#include "xil_types.h"
+#include "xpseudo_asm.h"
+#include "bspconfig.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/************************** Constant Definitions ****************************/
+
+#define XIL_EXCEPTION_FIQ XREG_CPSR_FIQ_ENABLE
+#define XIL_EXCEPTION_IRQ XREG_CPSR_IRQ_ENABLE
+#define XIL_EXCEPTION_ALL (XREG_CPSR_FIQ_ENABLE | XREG_CPSR_IRQ_ENABLE)
+
+#define XIL_EXCEPTION_ID_FIRST 0U
+#if defined (__aarch64__)
+#define XIL_EXCEPTION_ID_SYNC_INT 1U
+#define XIL_EXCEPTION_ID_IRQ_INT 2U
+#define XIL_EXCEPTION_ID_FIQ_INT 3U
+#define XIL_EXCEPTION_ID_SERROR_ABORT_INT 4U
+#define XIL_EXCEPTION_ID_LAST 5U
+#else
+#define XIL_EXCEPTION_ID_RESET 0U
+#define XIL_EXCEPTION_ID_UNDEFINED_INT 1U
+#define XIL_EXCEPTION_ID_SWI_INT 2U
+#define XIL_EXCEPTION_ID_PREFETCH_ABORT_INT 3U
+#define XIL_EXCEPTION_ID_DATA_ABORT_INT 4U
+#define XIL_EXCEPTION_ID_IRQ_INT 5U
+#define XIL_EXCEPTION_ID_FIQ_INT 6U
+#define XIL_EXCEPTION_ID_LAST 6U
+#endif
+
+/*
+ * XIL_EXCEPTION_ID_INT is defined for all Xilinx processors.
+ */
+#if defined (versal) && !defined(ARMR5) && EL3
+#define XIL_EXCEPTION_ID_INT XIL_EXCEPTION_ID_FIQ_INT
+#else
+#define XIL_EXCEPTION_ID_INT XIL_EXCEPTION_ID_IRQ_INT
+#endif
+
+/**************************** Type Definitions ******************************/
+
+/**
+ * This typedef is the exception handler function.
+ */
+typedef void (*Xil_ExceptionHandler)(void *data);
+typedef void (*Xil_InterruptHandler)(void *data);
+
+/***************** Macros (Inline Functions) Definitions ********************/
+
+/****************************************************************************/
+/**
+* @brief Enable Exceptions.
+*
+* @param Mask: Value for enabling the exceptions.
+*
+* @return None.
+*
+* @note If bit is 0, exception is enabled.
+* C-Style signature: void Xil_ExceptionEnableMask(Mask)
+*
+******************************************************************************/
+#if defined (versal) && !defined(ARMR5) && EL3
+/*
+ * Cortexa72 processor in versal is coupled with GIC-500, and GIC-500 supports
+ * only FIQ at EL3. Hence, tweaking this macro to always enable FIQ
+ * ignoring argument passed by user.
+ */
+#define Xil_ExceptionEnableMask(Mask) \
+ mtcpsr(mfcpsr() & ~ ((XIL_EXCEPTION_FIQ) & XIL_EXCEPTION_ALL))
+#elif defined (__GNUC__) || defined (__ICCARM__)
+#define Xil_ExceptionEnableMask(Mask) \
+ mtcpsr(mfcpsr() & ~ ((Mask) & XIL_EXCEPTION_ALL))
+#else
+#define Xil_ExceptionEnableMask(Mask) \
+ { \
+ register u32 Reg __asm("cpsr"); \
+ mtcpsr((Reg) & (~((Mask) & XIL_EXCEPTION_ALL))); \
+ }
+#endif
+/****************************************************************************/
+/**
+* @brief Enable the IRQ exception.
+*
+* @return None.
+*
+* @note None.
+*
+******************************************************************************/
+#if defined (versal) && !defined(ARMR5) && EL3
+#define Xil_ExceptionEnable() \
+ Xil_ExceptionEnableMask(XIL_EXCEPTION_FIQ)
+#else
+#define Xil_ExceptionEnable() \
+ Xil_ExceptionEnableMask(XIL_EXCEPTION_IRQ)
+#endif
+
+/****************************************************************************/
+/**
+* @brief Disable Exceptions.
+*
+* @param Mask: Value for disabling the exceptions.
+*
+* @return None.
+*
+* @note If bit is 1, exception is disabled.
+* C-Style signature: Xil_ExceptionDisableMask(Mask)
+*
+******************************************************************************/
+#if defined (versal) && !defined(ARMR5) && EL3
+/*
+ * Cortexa72 processor in versal is coupled with GIC-500, and GIC-500 supports
+ * only FIQ at EL3. Hence, tweaking this macro to always disable FIQ
+ * ignoring argument passed by user.
+ */
+#define Xil_ExceptionDisableMask(Mask) \
+ mtcpsr(mfcpsr() | ((XIL_EXCEPTION_FIQ) & XIL_EXCEPTION_ALL))
+#elif defined (__GNUC__) || defined (__ICCARM__)
+#define Xil_ExceptionDisableMask(Mask) \
+ mtcpsr(mfcpsr() | ((Mask) & XIL_EXCEPTION_ALL))
+#else
+#define Xil_ExceptionDisableMask(Mask) \
+ { \
+ register u32 Reg __asm("cpsr"); \
+ mtcpsr((Reg) | ((Mask) & XIL_EXCEPTION_ALL)); \
+ }
+#endif
+/****************************************************************************/
+/**
+* Disable the IRQ exception.
+*
+* @return None.
+*
+* @note None.
+*
+******************************************************************************/
+#define Xil_ExceptionDisable() \
+ Xil_ExceptionDisableMask(XIL_EXCEPTION_IRQ)
+
+#if !defined (__aarch64__) && !defined (ARMA53_32)
+/****************************************************************************/
+/**
+* @brief Enable nested interrupts by clearing the I and F bits in CPSR. This
+* API is defined for cortex-a9 and cortex-r5.
+*
+* @return None.
+*
+* @note This macro is supposed to be used from interrupt handlers. In the
+* interrupt handler the interrupts are disabled by default (I and F
+* are 1). To allow nesting of interrupts, this macro should be
+* used. It clears the I and F bits by changing the ARM mode to
+* system mode. Once these bits are cleared and provided the
+* preemption of interrupt conditions are met in the GIC, nesting of
+* interrupts will start happening.
+* Caution: This macro must be used with caution. Before calling this
+* macro, the user must ensure that the source of the current IRQ
+* is appropriately cleared. Otherwise, as soon as we clear the I and
+* F bits, there can be an infinite loop of interrupts with an
+* eventual crash (all the stack space getting consumed).
+******************************************************************************/
+#define Xil_EnableNestedInterrupts() \
+ __asm__ __volatile__ ("stmfd sp!, {lr}"); \
+ __asm__ __volatile__ ("mrs lr, spsr"); \
+ __asm__ __volatile__ ("stmfd sp!, {lr}"); \
+ __asm__ __volatile__ ("msr cpsr_c, #0x1F"); \
+ __asm__ __volatile__ ("stmfd sp!, {lr}");
+
+/****************************************************************************/
+/**
+* @brief Disable the nested interrupts by setting the I and F bits. This API
+* is defined for cortex-a9 and cortex-r5.
+*
+* @return None.
+*
+* @note This macro is meant to be called in the interrupt service routines.
+* This macro cannot be used independently. It can only be used when
+* nesting of interrupts have been enabled by using the macro
+* Xil_EnableNestedInterrupts(). In a typical flow, the user first
+* calls the Xil_EnableNestedInterrupts in the ISR at the appropriate
+* point. The user then must call this macro before exiting the interrupt
+* service routine. This macro puts the ARM back in IRQ/FIQ mode and
+* hence sets back the I and F bits.
+******************************************************************************/
+#define Xil_DisableNestedInterrupts() \
+ __asm__ __volatile__ ("ldmfd sp!, {lr}"); \
+ __asm__ __volatile__ ("msr cpsr_c, #0x92"); \
+ __asm__ __volatile__ ("ldmfd sp!, {lr}"); \
+ __asm__ __volatile__ ("msr spsr_cxsf, lr"); \
+ __asm__ __volatile__ ("ldmfd sp!, {lr}"); \
+
+#endif
+/************************** Variable Definitions ****************************/
+
+/************************** Function Prototypes *****************************/
+
+extern void Xil_ExceptionRegisterHandler(u32 Exception_id,
+ Xil_ExceptionHandler Handler,
+ void *Data);
+
+extern void Xil_ExceptionRemoveHandler(u32 Exception_id);
+extern void Xil_GetExceptionRegisterHandler(u32 Exception_id,
+ Xil_ExceptionHandler *Handler, void **Data);
+
+extern void Xil_ExceptionInit(void);
+#if defined (__aarch64__)
+void Xil_SyncAbortHandler(void *CallBackRef);
+void Xil_SErrorAbortHandler(void *CallBackRef);
+#else
+extern void Xil_DataAbortHandler(void *CallBackRef);
+extern void Xil_PrefetchAbortHandler(void *CallBackRef);
+extern void Xil_UndefinedExceptionHandler(void *CallBackRef);
+#endif
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+
+#endif /* XIL_EXCEPTION_H */
+/**
+* @} End of "addtogroup arm_exception_apis".
+*/
diff --git a/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/include/xil_hal.h b/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/include/xil_hal.h
new file mode 100644
index 0000000..be56e0e
--- /dev/null
+++ b/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/include/xil_hal.h
@@ -0,0 +1,63 @@
+/******************************************************************************
+*
+* Copyright (C) 2009 - 2015 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+* THE SOFTWARE.
+*
+*
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xil_hal.h
+*
+* Contains all the HAL header files.
+*
+* <pre>
+* MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ----- ---- -------- -------------------------------------------------------
+* 1.00a hbm 07/28/09 Initial release
+*
+* </pre>
+*
+* @note
+*
+******************************************************************************/
+
+#ifndef XIL_HAL_H
+#define XIL_HAL_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include "xil_cache.h"
+#include "xil_io.h"
+#include "xil_assert.h"
+#include "xil_exception.h"
+#include "xil_types.h"
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff --git a/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/include/xil_io.h b/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/include/xil_io.h
new file mode 100644
index 0000000..a475227
--- /dev/null
+++ b/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/include/xil_io.h
@@ -0,0 +1,339 @@
+/******************************************************************************
+*
+* Copyright (C) 2014 - 2016 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+* THE SOFTWARE.
+*
+*
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xil_io.h
+*
+* @addtogroup common_io_interfacing_apis Register IO interfacing APIs
+*
+* The xil_io.h file contains the interface for the general I/O component, which
+* encapsulates the Input/Output functions for the processors that do not
+* require any special I/O handling.
+*
+* @{
+* <pre>
+* MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ----- -------- -------- -----------------------------------------------
+* 5.00 pkp 05/29/14 First release
+* 6.00 mus 08/19/16 Remove checking of __LITTLE_ENDIAN__ flag for
+* ARM processors
+* </pre>
+******************************************************************************/
+
+#ifndef XIL_IO_H /* prevent circular inclusions */
+#define XIL_IO_H /* by using protection macros */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/***************************** Include Files *********************************/
+
+#include "xil_types.h"
+#include "xil_printf.h"
+
+#if defined (__MICROBLAZE__)
+#include "mb_interface.h"
+#else
+#include "xpseudo_asm.h"
+#endif
+
+/************************** Function Prototypes ******************************/
+u16 Xil_EndianSwap16(u16 Data);
+u32 Xil_EndianSwap32(u32 Data);
+#ifdef ENABLE_SAFETY
+extern u32 XStl_RegUpdate(u32 RegAddr, u32 RegVal);
+#endif
+
+/***************** Macros (Inline Functions) Definitions *********************/
+#if defined __GNUC__
+#if defined (__MICROBLAZE__)
+# define INST_SYNC mbar(0)
+# define DATA_SYNC mbar(1)
+# else
+# define SYNCHRONIZE_IO dmb()
+# define INST_SYNC isb()
+# define DATA_SYNC dsb()
+# endif
+#else
+# define SYNCHRONIZE_IO
+# define INST_SYNC
+# define DATA_SYNC
+# define INST_SYNC
+# define DATA_SYNC
+#endif
+
+#if defined (__GNUC__) || defined (__ICCARM__) || defined (__MICROBLAZE__)
+#define INLINE inline
+#else
+#define INLINE __inline
+#endif
+
+/*****************************************************************************/
+/**
+*
+* @brief Performs an input operation for a memory location by reading
+* from the specified address and returning the 8 bit Value read from
+* that address.
+*
+* @param Addr: contains the address to perform the input operation
+*
+* @return The 8 bit Value read from the specified input address.
+
+*
+******************************************************************************/
+static INLINE u8 Xil_In8(UINTPTR Addr)
+{
+ return *(volatile u8 *) Addr;
+}
+
+/*****************************************************************************/
+/**
+*
+* @brief Performs an input operation for a memory location by reading from
+* the specified address and returning the 16 bit Value read from that
+* address.
+*
+* @param Addr: contains the address to perform the input operation
+*
+* @return The 16 bit Value read from the specified input address.
+*
+******************************************************************************/
+static INLINE u16 Xil_In16(UINTPTR Addr)
+{
+ return *(volatile u16 *) Addr;
+}
+
+/*****************************************************************************/
+/**
+*
+* @brief Performs an input operation for a memory location by
+* reading from the specified address and returning the 32 bit Value
+* read from that address.
+*
+* @param Addr: contains the address to perform the input operation
+*
+* @return The 32 bit Value read from the specified input address.
+*
+******************************************************************************/
+static INLINE u32 Xil_In32(UINTPTR Addr)
+{
+ return *(volatile u32 *) Addr;
+}
+
+/*****************************************************************************/
+/**
+*
+* @brief Performs an input operation for a memory location by reading the
+* 64 bit Value read from that address.
+*
+*
+* @param Addr: contains the address to perform the input operation
+*
+* @return The 64 bit Value read from the specified input address.
+*
+******************************************************************************/
+static INLINE u64 Xil_In64(UINTPTR Addr)
+{
+ return *(volatile u64 *) Addr;
+}
+
+/*****************************************************************************/
+/**
+*
+* @brief Performs an output operation for an memory location by
+* writing the 8 bit Value to the the specified address.
+*
+* @param Addr: contains the address to perform the output operation
+* @param Value: contains the 8 bit Value to be written at the specified
+* address.
+*
+* @return None.
+*
+******************************************************************************/
+static INLINE void Xil_Out8(UINTPTR Addr, u8 Value)
+{
+ volatile u8 *LocalAddr = (volatile u8 *)Addr;
+ *LocalAddr = Value;
+}
+
+/*****************************************************************************/
+/**
+*
+* @brief Performs an output operation for a memory location by writing the
+* 16 bit Value to the the specified address.
+*
+* @param Addr contains the address to perform the output operation
+* @param Value contains the Value to be written at the specified address.
+*
+* @return None.
+*
+******************************************************************************/
+static INLINE void Xil_Out16(UINTPTR Addr, u16 Value)
+{
+ volatile u16 *LocalAddr = (volatile u16 *)Addr;
+ *LocalAddr = Value;
+}
+
+/*****************************************************************************/
+/**
+*
+* @brief Performs an output operation for a memory location by writing the
+* 32 bit Value to the the specified address.
+*
+* @param Addr contains the address to perform the output operation
+* @param Value contains the 32 bit Value to be written at the specified
+* address.
+*
+* @return None.
+*
+******************************************************************************/
+static INLINE void Xil_Out32(UINTPTR Addr, u32 Value)
+{
+#ifndef ENABLE_SAFETY
+ volatile u32 *LocalAddr = (volatile u32 *)Addr;
+ *LocalAddr = Value;
+#else
+ XStl_RegUpdate(Addr, Value);
+#endif
+}
+
+/*****************************************************************************/
+/**
+*
+* @brief Performs an output operation for a memory location by writing the
+* 64 bit Value to the the specified address.
+*
+* @param Addr contains the address to perform the output operation
+* @param Value contains 64 bit Value to be written at the specified address.
+*
+* @return None.
+*
+******************************************************************************/
+static INLINE void Xil_Out64(UINTPTR Addr, u64 Value)
+{
+ volatile u64 *LocalAddr = (volatile u64 *)Addr;
+ *LocalAddr = Value;
+}
+
+#if defined (__MICROBLAZE__)
+#ifdef __LITTLE_ENDIAN__
+# define Xil_In16LE Xil_In16
+# define Xil_In32LE Xil_In32
+# define Xil_Out16LE Xil_Out16
+# define Xil_Out32LE Xil_Out32
+# define Xil_Htons Xil_EndianSwap16
+# define Xil_Htonl Xil_EndianSwap32
+# define Xil_Ntohs Xil_EndianSwap16
+# define Xil_Ntohl Xil_EndianSwap32
+# else
+# define Xil_In16BE Xil_In16
+# define Xil_In32BE Xil_In32
+# define Xil_Out16BE Xil_Out16
+# define Xil_Out32BE Xil_Out32
+# define Xil_Htons(Data) (Data)
+# define Xil_Htonl(Data) (Data)
+# define Xil_Ntohs(Data) (Data)
+# define Xil_Ntohl(Data) (Data)
+#endif
+#else
+# define Xil_In16LE Xil_In16
+# define Xil_In32LE Xil_In32
+# define Xil_Out16LE Xil_Out16
+# define Xil_Out32LE Xil_Out32
+# define Xil_Htons Xil_EndianSwap16
+# define Xil_Htonl Xil_EndianSwap32
+# define Xil_Ntohs Xil_EndianSwap16
+# define Xil_Ntohl Xil_EndianSwap32
+#endif
+
+#if defined (__MICROBLAZE__)
+#ifdef __LITTLE_ENDIAN__
+static INLINE u16 Xil_In16BE(UINTPTR Addr)
+#else
+static INLINE u16 Xil_In16LE(UINTPTR Addr)
+#endif
+#else
+static INLINE u16 Xil_In16BE(UINTPTR Addr)
+#endif
+{
+ u16 value = Xil_In16(Addr);
+ return Xil_EndianSwap16(value);
+}
+
+#if defined (__MICROBLAZE__)
+#ifdef __LITTLE_ENDIAN__
+static INLINE u32 Xil_In32BE(UINTPTR Addr)
+#else
+static INLINE u32 Xil_In32LE(UINTPTR Addr)
+#endif
+#else
+static INLINE u32 Xil_In32BE(UINTPTR Addr)
+#endif
+{
+ u32 value = Xil_In32(Addr);
+ return Xil_EndianSwap32(value);
+}
+
+#if defined (__MICROBLAZE__)
+#ifdef __LITTLE_ENDIAN__
+static INLINE void Xil_Out16BE(UINTPTR Addr, u16 Value)
+#else
+static INLINE void Xil_Out16LE(UINTPTR Addr, u16 Value)
+#endif
+#else
+static INLINE void Xil_Out16BE(UINTPTR Addr, u16 Value)
+#endif
+{
+ Value = Xil_EndianSwap16(Value);
+ Xil_Out16(Addr, Value);
+}
+
+#if defined (__MICROBLAZE__)
+#ifdef __LITTLE_ENDIAN__
+static INLINE void Xil_Out32BE(UINTPTR Addr, u32 Value)
+#else
+static INLINE void Xil_Out32LE(UINTPTR Addr, u32 Value)
+#endif
+#else
+static INLINE void Xil_Out32BE(UINTPTR Addr, u32 Value)
+#endif
+{
+ Value = Xil_EndianSwap32(Value);
+ Xil_Out32(Addr, Value);
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* end of protection macro */
+/**
+* @} End of "addtogroup common_io_interfacing_apis".
+*/
diff --git a/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/include/xil_macroback.h b/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/include/xil_macroback.h
new file mode 100644
index 0000000..414970e
--- /dev/null
+++ b/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/include/xil_macroback.h
@@ -0,0 +1,1054 @@
+/******************************************************************************
+*
+* Copyright (C) 2010 - 2015 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+* THE SOFTWARE.
+*
+*
+*
+******************************************************************************/
+
+/*********************************************************************/
+/**
+ * @file xil_macroback.h
+ *
+ * This header file is meant to bring back the removed _m macros.
+ * This header file must be included last.
+ * The following macros are not defined here due to the driver change:
+ * XGpio_mSetDataDirection
+ * XGpio_mGetDataReg
+ * XGpio_mSetDataReg
+ * XIIC_RESET
+ * XIIC_CLEAR_STATS
+ * XSpi_mReset
+ * XSysAce_mSetCfgAddr
+ * XSysAce_mIsCfgDone
+ * XTft_mSetPixel
+ * XTft_mGetPixel
+ * XWdtTb_mEnableWdt
+ * XWdtTb_mDisbleWdt
+ * XWdtTb_mRestartWdt
+ * XWdtTb_mGetTimebaseReg
+ * XWdtTb_mHasReset
+ *
+ * Please refer the corresponding driver document for replacement.
+ *
+ *********************************************************************/
+
+#ifndef XIL_MACROBACK_H
+#define XIL_MACROBACK_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*********************************************************************/
+/**
+ * Macros for Driver XCan
+ *
+ *********************************************************************/
+#ifndef XCan_mReadReg
+#define XCan_mReadReg XCan_ReadReg
+#endif
+
+#ifndef XCan_mWriteReg
+#define XCan_mWriteReg XCan_WriteReg
+#endif
+
+#ifndef XCan_mIsTxDone
+#define XCan_mIsTxDone XCan_IsTxDone
+#endif
+
+#ifndef XCan_mIsTxFifoFull
+#define XCan_mIsTxFifoFull XCan_IsTxFifoFull
+#endif
+
+#ifndef XCan_mIsHighPriorityBufFull
+#define XCan_mIsHighPriorityBufFull XCan_IsHighPriorityBufFull
+#endif
+
+#ifndef XCan_mIsRxEmpty
+#define XCan_mIsRxEmpty XCan_IsRxEmpty
+#endif
+
+#ifndef XCan_mIsAcceptFilterBusy
+#define XCan_mIsAcceptFilterBusy XCan_IsAcceptFilterBusy
+#endif
+
+#ifndef XCan_mCreateIdValue
+#define XCan_mCreateIdValue XCan_CreateIdValue
+#endif
+
+#ifndef XCan_mCreateDlcValue
+#define XCan_mCreateDlcValue XCan_CreateDlcValue
+#endif
+
+/*********************************************************************/
+/**
+ * Macros for Driver XDmaCentral
+ *
+ *********************************************************************/
+#ifndef XDmaCentral_mWriteReg
+#define XDmaCentral_mWriteReg XDmaCentral_WriteReg
+#endif
+
+#ifndef XDmaCentral_mReadReg
+#define XDmaCentral_mReadReg XDmaCentral_ReadReg
+#endif
+
+/*********************************************************************/
+/**
+ * Macros for Driver XDsAdc
+ *
+ *********************************************************************/
+#ifndef XDsAdc_mWriteReg
+#define XDsAdc_mWriteReg XDsAdc_WriteReg
+#endif
+
+#ifndef XDsAdc_mReadReg
+#define XDsAdc_mReadReg XDsAdc_ReadReg
+#endif
+
+#ifndef XDsAdc_mIsEmpty
+#define XDsAdc_mIsEmpty XDsAdc_IsEmpty
+#endif
+
+#ifndef XDsAdc_mSetFstmReg
+#define XDsAdc_mSetFstmReg XDsAdc_SetFstmReg
+#endif
+
+#ifndef XDsAdc_mGetFstmReg
+#define XDsAdc_mGetFstmReg XDsAdc_GetFstmReg
+#endif
+
+#ifndef XDsAdc_mEnableConversion
+#define XDsAdc_mEnableConversion XDsAdc_EnableConversion
+#endif
+
+#ifndef XDsAdc_mDisableConversion
+#define XDsAdc_mDisableConversion XDsAdc_DisableConversion
+#endif
+
+#ifndef XDsAdc_mGetFifoOccyReg
+#define XDsAdc_mGetFifoOccyReg XDsAdc_GetFifoOccyReg
+#endif
+
+/*********************************************************************/
+/**
+ * Macros for Driver XDsDac
+ *
+ *********************************************************************/
+#ifndef XDsDac_mWriteReg
+#define XDsDac_mWriteReg XDsDac_WriteReg
+#endif
+
+#ifndef XDsDac_mReadReg
+#define XDsDac_mReadReg XDsDac_ReadReg
+#endif
+
+#ifndef XDsDac_mIsEmpty
+#define XDsDac_mIsEmpty XDsDac_IsEmpty
+#endif
+
+#ifndef XDsDac_mFifoIsFull
+#define XDsDac_mFifoIsFull XDsDac_FifoIsFull
+#endif
+
+#ifndef XDsDac_mGetVacancy
+#define XDsDac_mGetVacancy XDsDac_GetVacancy
+#endif
+
+/*********************************************************************/
+/**
+ * Macros for Driver XEmacLite
+ *
+ *********************************************************************/
+#ifndef XEmacLite_mReadReg
+#define XEmacLite_mReadReg XEmacLite_ReadReg
+#endif
+
+#ifndef XEmacLite_mWriteReg
+#define XEmacLite_mWriteReg XEmacLite_WriteReg
+#endif
+
+#ifndef XEmacLite_mGetTxStatus
+#define XEmacLite_mGetTxStatus XEmacLite_GetTxStatus
+#endif
+
+#ifndef XEmacLite_mSetTxStatus
+#define XEmacLite_mSetTxStatus XEmacLite_SetTxStatus
+#endif
+
+#ifndef XEmacLite_mGetRxStatus
+#define XEmacLite_mGetRxStatus XEmacLite_GetRxStatus
+#endif
+
+#ifndef XEmacLite_mSetRxStatus
+#define XEmacLite_mSetRxStatus XEmacLite_SetRxStatus
+#endif
+
+#ifndef XEmacLite_mIsTxDone
+#define XEmacLite_mIsTxDone XEmacLite_IsTxDone
+#endif
+
+#ifndef XEmacLite_mIsRxEmpty
+#define XEmacLite_mIsRxEmpty XEmacLite_IsRxEmpty
+#endif
+
+#ifndef XEmacLite_mNextTransmitAddr
+#define XEmacLite_mNextTransmitAddr XEmacLite_NextTransmitAddr
+#endif
+
+#ifndef XEmacLite_mNextReceiveAddr
+#define XEmacLite_mNextReceiveAddr XEmacLite_NextReceiveAddr
+#endif
+
+#ifndef XEmacLite_mIsMdioConfigured
+#define XEmacLite_mIsMdioConfigured XEmacLite_IsMdioConfigured
+#endif
+
+#ifndef XEmacLite_mIsLoopbackConfigured
+#define XEmacLite_mIsLoopbackConfigured XEmacLite_IsLoopbackConfigured
+#endif
+
+#ifndef XEmacLite_mGetReceiveDataLength
+#define XEmacLite_mGetReceiveDataLength XEmacLite_GetReceiveDataLength
+#endif
+
+#ifndef XEmacLite_mGetTxActive
+#define XEmacLite_mGetTxActive XEmacLite_GetTxActive
+#endif
+
+#ifndef XEmacLite_mSetTxActive
+#define XEmacLite_mSetTxActive XEmacLite_SetTxActive
+#endif
+
+/*********************************************************************/
+/**
+ * Macros for Driver XGpio
+ *
+ *********************************************************************/
+#ifndef XGpio_mWriteReg
+#define XGpio_mWriteReg XGpio_WriteReg
+#endif
+
+#ifndef XGpio_mReadReg
+#define XGpio_mReadReg XGpio_ReadReg
+#endif
+
+/*********************************************************************/
+/**
+ * Macros for Driver XHwIcap
+ *
+ *********************************************************************/
+#ifndef XHwIcap_mFifoWrite
+#define XHwIcap_mFifoWrite XHwIcap_FifoWrite
+#endif
+
+#ifndef XHwIcap_mFifoRead
+#define XHwIcap_mFifoRead XHwIcap_FifoRead
+#endif
+
+#ifndef XHwIcap_mSetSizeReg
+#define XHwIcap_mSetSizeReg XHwIcap_SetSizeReg
+#endif
+
+#ifndef XHwIcap_mGetControlReg
+#define XHwIcap_mGetControlReg XHwIcap_GetControlReg
+#endif
+
+#ifndef XHwIcap_mStartConfig
+#define XHwIcap_mStartConfig XHwIcap_StartConfig
+#endif
+
+#ifndef XHwIcap_mStartReadBack
+#define XHwIcap_mStartReadBack XHwIcap_StartReadBack
+#endif
+
+#ifndef XHwIcap_mGetStatusReg
+#define XHwIcap_mGetStatusReg XHwIcap_GetStatusReg
+#endif
+
+#ifndef XHwIcap_mIsTransferDone
+#define XHwIcap_mIsTransferDone XHwIcap_IsTransferDone
+#endif
+
+#ifndef XHwIcap_mIsDeviceBusy
+#define XHwIcap_mIsDeviceBusy XHwIcap_IsDeviceBusy
+#endif
+
+#ifndef XHwIcap_mIntrGlobalEnable
+#define XHwIcap_mIntrGlobalEnable XHwIcap_IntrGlobalEnable
+#endif
+
+#ifndef XHwIcap_mIntrGlobalDisable
+#define XHwIcap_mIntrGlobalDisable XHwIcap_IntrGlobalDisable
+#endif
+
+#ifndef XHwIcap_mIntrGetStatus
+#define XHwIcap_mIntrGetStatus XHwIcap_IntrGetStatus
+#endif
+
+#ifndef XHwIcap_mIntrDisable
+#define XHwIcap_mIntrDisable XHwIcap_IntrDisable
+#endif
+
+#ifndef XHwIcap_mIntrEnable
+#define XHwIcap_mIntrEnable XHwIcap_IntrEnable
+#endif
+
+#ifndef XHwIcap_mIntrGetEnabled
+#define XHwIcap_mIntrGetEnabled XHwIcap_IntrGetEnabled
+#endif
+
+#ifndef XHwIcap_mIntrClear
+#define XHwIcap_mIntrClear XHwIcap_IntrClear
+#endif
+
+#ifndef XHwIcap_mGetWrFifoVacancy
+#define XHwIcap_mGetWrFifoVacancy XHwIcap_GetWrFifoVacancy
+#endif
+
+#ifndef XHwIcap_mGetRdFifoOccupancy
+#define XHwIcap_mGetRdFifoOccupancy XHwIcap_GetRdFifoOccupancy
+#endif
+
+#ifndef XHwIcap_mSliceX2Col
+#define XHwIcap_mSliceX2Col XHwIcap_SliceX2Col
+#endif
+
+#ifndef XHwIcap_mSliceY2Row
+#define XHwIcap_mSliceY2Row XHwIcap_SliceY2Row
+#endif
+
+#ifndef XHwIcap_mSliceXY2Slice
+#define XHwIcap_mSliceXY2Slice XHwIcap_SliceXY2Slice
+#endif
+
+#ifndef XHwIcap_mReadReg
+#define XHwIcap_mReadReg XHwIcap_ReadReg
+#endif
+
+#ifndef XHwIcap_mWriteReg
+#define XHwIcap_mWriteReg XHwIcap_WriteReg
+#endif
+
+/*********************************************************************/
+/**
+ * Macros for Driver XIic
+ *
+ *********************************************************************/
+#ifndef XIic_mReadReg
+#define XIic_mReadReg XIic_ReadReg
+#endif
+
+#ifndef XIic_mWriteReg
+#define XIic_mWriteReg XIic_WriteReg
+#endif
+
+#ifndef XIic_mEnterCriticalRegion
+#define XIic_mEnterCriticalRegion XIic_IntrGlobalDisable
+#endif
+
+#ifndef XIic_mExitCriticalRegion
+#define XIic_mExitCriticalRegion XIic_IntrGlobalEnable
+#endif
+
+#ifndef XIIC_GINTR_DISABLE
+#define XIIC_GINTR_DISABLE XIic_IntrGlobalDisable
+#endif
+
+#ifndef XIIC_GINTR_ENABLE
+#define XIIC_GINTR_ENABLE XIic_IntrGlobalEnable
+#endif
+
+#ifndef XIIC_IS_GINTR_ENABLED
+#define XIIC_IS_GINTR_ENABLED XIic_IsIntrGlobalEnabled
+#endif
+
+#ifndef XIIC_WRITE_IISR
+#define XIIC_WRITE_IISR XIic_WriteIisr
+#endif
+
+#ifndef XIIC_READ_IISR
+#define XIIC_READ_IISR XIic_ReadIisr
+#endif
+
+#ifndef XIIC_WRITE_IIER
+#define XIIC_WRITE_IIER XIic_WriteIier
+#endif
+
+#ifndef XIic_mClearIisr
+#define XIic_mClearIisr XIic_ClearIisr
+#endif
+
+#ifndef XIic_mSend7BitAddress
+#define XIic_mSend7BitAddress XIic_Send7BitAddress
+#endif
+
+#ifndef XIic_mDynSend7BitAddress
+#define XIic_mDynSend7BitAddress XIic_DynSend7BitAddress
+#endif
+
+#ifndef XIic_mDynSendStartStopAddress
+#define XIic_mDynSendStartStopAddress XIic_DynSendStartStopAddress
+#endif
+
+#ifndef XIic_mDynSendStop
+#define XIic_mDynSendStop XIic_DynSendStop
+#endif
+
+#ifndef XIic_mSend10BitAddrByte1
+#define XIic_mSend10BitAddrByte1 XIic_Send10BitAddrByte1
+#endif
+
+#ifndef XIic_mSend10BitAddrByte2
+#define XIic_mSend10BitAddrByte2 XIic_Send10BitAddrByte2
+#endif
+
+#ifndef XIic_mSend7BitAddr
+#define XIic_mSend7BitAddr XIic_Send7BitAddr
+#endif
+
+#ifndef XIic_mDisableIntr
+#define XIic_mDisableIntr XIic_DisableIntr
+#endif
+
+#ifndef XIic_mEnableIntr
+#define XIic_mEnableIntr XIic_EnableIntr
+#endif
+
+#ifndef XIic_mClearIntr
+#define XIic_mClearIntr XIic_ClearIntr
+#endif
+
+#ifndef XIic_mClearEnableIntr
+#define XIic_mClearEnableIntr XIic_ClearEnableIntr
+#endif
+
+#ifndef XIic_mFlushRxFifo
+#define XIic_mFlushRxFifo XIic_FlushRxFifo
+#endif
+
+#ifndef XIic_mFlushTxFifo
+#define XIic_mFlushTxFifo XIic_FlushTxFifo
+#endif
+
+#ifndef XIic_mReadRecvByte
+#define XIic_mReadRecvByte XIic_ReadRecvByte
+#endif
+
+#ifndef XIic_mWriteSendByte
+#define XIic_mWriteSendByte XIic_WriteSendByte
+#endif
+
+#ifndef XIic_mSetControlRegister
+#define XIic_mSetControlRegister XIic_SetControlRegister
+#endif
+
+/*********************************************************************/
+/**
+ * Macros for Driver XIntc
+ *
+ *********************************************************************/
+#ifndef XIntc_mMasterEnable
+#define XIntc_mMasterEnable XIntc_MasterEnable
+#endif
+
+#ifndef XIntc_mMasterDisable
+#define XIntc_mMasterDisable XIntc_MasterDisable
+#endif
+
+#ifndef XIntc_mEnableIntr
+#define XIntc_mEnableIntr XIntc_EnableIntr
+#endif
+
+#ifndef XIntc_mDisableIntr
+#define XIntc_mDisableIntr XIntc_DisableIntr
+#endif
+
+#ifndef XIntc_mAckIntr
+#define XIntc_mAckIntr XIntc_AckIntr
+#endif
+
+#ifndef XIntc_mGetIntrStatus
+#define XIntc_mGetIntrStatus XIntc_GetIntrStatus
+#endif
+
+/*********************************************************************/
+/**
+ * Macros for Driver XLlDma
+ *
+ *********************************************************************/
+#ifndef XLlDma_mBdRead
+#define XLlDma_mBdRead XLlDma_BdRead
+#endif
+
+#ifndef XLlDma_mBdWrite
+#define XLlDma_mBdWrite XLlDma_BdWrite
+#endif
+
+#ifndef XLlDma_mWriteReg
+#define XLlDma_mWriteReg XLlDma_WriteReg
+#endif
+
+#ifndef XLlDma_mReadReg
+#define XLlDma_mReadReg XLlDma_ReadReg
+#endif
+
+#ifndef XLlDma_mBdClear
+#define XLlDma_mBdClear XLlDma_BdClear
+#endif
+
+#ifndef XLlDma_mBdSetStsCtrl
+#define XLlDma_mBdSetStsCtrl XLlDma_BdSetStsCtrl
+#endif
+
+#ifndef XLlDma_mBdGetStsCtrl
+#define XLlDma_mBdGetStsCtrl XLlDma_BdGetStsCtrl
+#endif
+
+#ifndef XLlDma_mBdSetLength
+#define XLlDma_mBdSetLength XLlDma_BdSetLength
+#endif
+
+#ifndef XLlDma_mBdGetLength
+#define XLlDma_mBdGetLength XLlDma_BdGetLength
+#endif
+
+#ifndef XLlDma_mBdSetId
+#define XLlDma_mBdSetId XLlDma_BdSetId
+#endif
+
+#ifndef XLlDma_mBdGetId
+#define XLlDma_mBdGetId XLlDma_BdGetId
+#endif
+
+#ifndef XLlDma_mBdSetBufAddr
+#define XLlDma_mBdSetBufAddr XLlDma_BdSetBufAddr
+#endif
+
+#ifndef XLlDma_mBdGetBufAddr
+#define XLlDma_mBdGetBufAddr XLlDma_BdGetBufAddr
+#endif
+
+#ifndef XLlDma_mBdGetLength
+#define XLlDma_mBdGetLength XLlDma_BdGetLength
+#endif
+
+#ifndef XLlDma_mGetTxRing
+#define XLlDma_mGetTxRing XLlDma_GetTxRing
+#endif
+
+#ifndef XLlDma_mGetRxRing
+#define XLlDma_mGetRxRing XLlDma_GetRxRing
+#endif
+
+#ifndef XLlDma_mGetCr
+#define XLlDma_mGetCr XLlDma_GetCr
+#endif
+
+#ifndef XLlDma_mSetCr
+#define XLlDma_mSetCr XLlDma_SetCr
+#endif
+
+#ifndef XLlDma_mBdRingCntCalc
+#define XLlDma_mBdRingCntCalc XLlDma_BdRingCntCalc
+#endif
+
+#ifndef XLlDma_mBdRingMemCalc
+#define XLlDma_mBdRingMemCalc XLlDma_BdRingMemCalc
+#endif
+
+#ifndef XLlDma_mBdRingGetCnt
+#define XLlDma_mBdRingGetCnt XLlDma_BdRingGetCnt
+#endif
+
+#ifndef XLlDma_mBdRingGetFreeCnt
+#define XLlDma_mBdRingGetFreeCnt XLlDma_BdRingGetFreeCnt
+#endif
+
+#ifndef XLlDma_mBdRingSnapShotCurrBd
+#define XLlDma_mBdRingSnapShotCurrBd XLlDma_BdRingSnapShotCurrBd
+#endif
+
+#ifndef XLlDma_mBdRingNext
+#define XLlDma_mBdRingNext XLlDma_BdRingNext
+#endif
+
+#ifndef XLlDma_mBdRingPrev
+#define XLlDma_mBdRingPrev XLlDma_BdRingPrev
+#endif
+
+#ifndef XLlDma_mBdRingGetSr
+#define XLlDma_mBdRingGetSr XLlDma_BdRingGetSr
+#endif
+
+#ifndef XLlDma_mBdRingSetSr
+#define XLlDma_mBdRingSetSr XLlDma_BdRingSetSr
+#endif
+
+#ifndef XLlDma_mBdRingGetCr
+#define XLlDma_mBdRingGetCr XLlDma_BdRingGetCr
+#endif
+
+#ifndef XLlDma_mBdRingSetCr
+#define XLlDma_mBdRingSetCr XLlDma_BdRingSetCr
+#endif
+
+#ifndef XLlDma_mBdRingBusy
+#define XLlDma_mBdRingBusy XLlDma_BdRingBusy
+#endif
+
+#ifndef XLlDma_mBdRingIntEnable
+#define XLlDma_mBdRingIntEnable XLlDma_BdRingIntEnable
+#endif
+
+#ifndef XLlDma_mBdRingIntDisable
+#define XLlDma_mBdRingIntDisable XLlDma_BdRingIntDisable
+#endif
+
+#ifndef XLlDma_mBdRingIntGetEnabled
+#define XLlDma_mBdRingIntGetEnabled XLlDma_BdRingIntGetEnabled
+#endif
+
+#ifndef XLlDma_mBdRingGetIrq
+#define XLlDma_mBdRingGetIrq XLlDma_BdRingGetIrq
+#endif
+
+#ifndef XLlDma_mBdRingAckIrq
+#define XLlDma_mBdRingAckIrq XLlDma_BdRingAckIrq
+#endif
+
+/*********************************************************************/
+/**
+ * Macros for Driver XMbox
+ *
+ *********************************************************************/
+#ifndef XMbox_mWriteReg
+#define XMbox_mWriteReg XMbox_WriteReg
+#endif
+
+#ifndef XMbox_mReadReg
+#define XMbox_mReadReg XMbox_ReadReg
+#endif
+
+#ifndef XMbox_mWriteMBox
+#define XMbox_mWriteMBox XMbox_WriteMBox
+#endif
+
+#ifndef XMbox_mReadMBox
+#define XMbox_mReadMBox XMbox_ReadMBox
+#endif
+
+#ifndef XMbox_mFSLReadMBox
+#define XMbox_mFSLReadMBox XMbox_FSLReadMBox
+#endif
+
+#ifndef XMbox_mFSLWriteMBox
+#define XMbox_mFSLWriteMBox XMbox_FSLWriteMBox
+#endif
+
+#ifndef XMbox_mFSLIsEmpty
+#define XMbox_mFSLIsEmpty XMbox_FSLIsEmpty
+#endif
+
+#ifndef XMbox_mFSLIsFull
+#define XMbox_mFSLIsFull XMbox_FSLIsFull
+#endif
+
+#ifndef XMbox_mIsEmpty
+#define XMbox_mIsEmpty XMbox_IsEmptyHw
+#endif
+
+#ifndef XMbox_mIsFull
+#define XMbox_mIsFull XMbox_IsFullHw
+#endif
+
+/*********************************************************************/
+/**
+ * Macros for Driver XMpmc
+ *
+ *********************************************************************/
+#ifndef XMpmc_mReadReg
+#define XMpmc_mReadReg XMpmc_ReadReg
+#endif
+
+#ifndef XMpmc_mWriteReg
+#define XMpmc_mWriteReg XMpmc_WriteReg
+#endif
+
+/*********************************************************************/
+/**
+ * Macros for Driver XMutex
+ *
+ *********************************************************************/
+#ifndef XMutex_mWriteReg
+#define XMutex_mWriteReg XMutex_WriteReg
+#endif
+
+#ifndef XMutex_mReadReg
+#define XMutex_mReadReg XMutex_ReadReg
+#endif
+
+/*********************************************************************/
+/**
+ * Macros for Driver XPcie
+ *
+ *********************************************************************/
+#ifndef XPcie_mReadReg
+#define XPcie_mReadReg XPcie_ReadReg
+#endif
+
+#ifndef XPcie_mWriteReg
+#define XPcie_mWriteReg XPcie_WriteReg
+#endif
+
+/*********************************************************************/
+/**
+ * Macros for Driver XSpi
+ *
+ *********************************************************************/
+#ifndef XSpi_mIntrGlobalEnable
+#define XSpi_mIntrGlobalEnable XSpi_IntrGlobalEnable
+#endif
+
+#ifndef XSpi_mIntrGlobalDisable
+#define XSpi_mIntrGlobalDisable XSpi_IntrGlobalDisable
+#endif
+
+#ifndef XSpi_mIsIntrGlobalEnabled
+#define XSpi_mIsIntrGlobalEnabled XSpi_IsIntrGlobalEnabled
+#endif
+
+#ifndef XSpi_mIntrGetStatus
+#define XSpi_mIntrGetStatus XSpi_IntrGetStatus
+#endif
+
+#ifndef XSpi_mIntrClear
+#define XSpi_mIntrClear XSpi_IntrClear
+#endif
+
+#ifndef XSpi_mIntrEnable
+#define XSpi_mIntrEnable XSpi_IntrEnable
+#endif
+
+#ifndef XSpi_mIntrDisable
+#define XSpi_mIntrDisable XSpi_IntrDisable
+#endif
+
+#ifndef XSpi_mIntrGetEnabled
+#define XSpi_mIntrGetEnabled XSpi_IntrGetEnabled
+#endif
+
+#ifndef XSpi_mSetControlReg
+#define XSpi_mSetControlReg XSpi_SetControlReg
+#endif
+
+#ifndef XSpi_mGetControlReg
+#define XSpi_mGetControlReg XSpi_GetControlReg
+#endif
+
+#ifndef XSpi_mGetStatusReg
+#define XSpi_mGetStatusReg XSpi_GetStatusReg
+#endif
+
+#ifndef XSpi_mSetSlaveSelectReg
+#define XSpi_mSetSlaveSelectReg XSpi_SetSlaveSelectReg
+#endif
+
+#ifndef XSpi_mGetSlaveSelectReg
+#define XSpi_mGetSlaveSelectReg XSpi_GetSlaveSelectReg
+#endif
+
+#ifndef XSpi_mEnable
+#define XSpi_mEnable XSpi_Enable
+#endif
+
+#ifndef XSpi_mDisable
+#define XSpi_mDisable XSpi_Disable
+#endif
+
+/*********************************************************************/
+/**
+ * Macros for Driver XSysAce
+ *
+ *********************************************************************/
+#ifndef XSysAce_mGetControlReg
+#define XSysAce_mGetControlReg XSysAce_GetControlReg
+#endif
+
+#ifndef XSysAce_mSetControlReg
+#define XSysAce_mSetControlReg XSysAce_SetControlReg
+#endif
+
+#ifndef XSysAce_mOrControlReg
+#define XSysAce_mOrControlReg XSysAce_OrControlReg
+#endif
+
+#ifndef XSysAce_mAndControlReg
+#define XSysAce_mAndControlReg XSysAce_AndControlReg
+#endif
+
+#ifndef XSysAce_mGetErrorReg
+#define XSysAce_mGetErrorReg XSysAce_GetErrorReg
+#endif
+
+#ifndef XSysAce_mGetStatusReg
+#define XSysAce_mGetStatusReg XSysAce_GetStatusReg
+#endif
+
+#ifndef XSysAce_mWaitForLock
+#define XSysAce_mWaitForLock XSysAce_WaitForLock
+#endif
+
+#ifndef XSysAce_mEnableIntr
+#define XSysAce_mEnableIntr XSysAce_EnableIntr
+#endif
+
+#ifndef XSysAce_mDisableIntr
+#define XSysAce_mDisableIntr XSysAce_DisableIntr
+#endif
+
+#ifndef XSysAce_mIsReadyForCmd
+#define XSysAce_mIsReadyForCmd XSysAce_IsReadyForCmd
+#endif
+
+#ifndef XSysAce_mIsMpuLocked
+#define XSysAce_mIsMpuLocked XSysAce_IsMpuLocked
+#endif
+
+#ifndef XSysAce_mIsIntrEnabled
+#define XSysAce_mIsIntrEnabled XSysAce_IsIntrEnabled
+#endif
+
+/*********************************************************************/
+/**
+ * Macros for Driver XSysMon
+ *
+ *********************************************************************/
+#ifndef XSysMon_mIsEventSamplingModeSet
+#define XSysMon_mIsEventSamplingModeSet XSysMon_IsEventSamplingModeSet
+#endif
+
+#ifndef XSysMon_mIsDrpBusy
+#define XSysMon_mIsDrpBusy XSysMon_IsDrpBusy
+#endif
+
+#ifndef XSysMon_mIsDrpLocked
+#define XSysMon_mIsDrpLocked XSysMon_IsDrpLocked
+#endif
+
+#ifndef XSysMon_mRawToTemperature
+#define XSysMon_mRawToTemperature XSysMon_RawToTemperature
+#endif
+
+#ifndef XSysMon_mRawToVoltage
+#define XSysMon_mRawToVoltage XSysMon_RawToVoltage
+#endif
+
+#ifndef XSysMon_mTemperatureToRaw
+#define XSysMon_mTemperatureToRaw XSysMon_TemperatureToRaw
+#endif
+
+#ifndef XSysMon_mVoltageToRaw
+#define XSysMon_mVoltageToRaw XSysMon_VoltageToRaw
+#endif
+
+#ifndef XSysMon_mReadReg
+#define XSysMon_mReadReg XSysMon_ReadReg
+#endif
+
+#ifndef XSysMon_mWriteReg
+#define XSysMon_mWriteReg XSysMon_WriteReg
+#endif
+
+/*********************************************************************/
+/**
+ * Macros for Driver XTmrCtr
+ *
+ *********************************************************************/
+#ifndef XTimerCtr_mReadReg
+#define XTimerCtr_mReadReg XTimerCtr_ReadReg
+#endif
+
+#ifndef XTmrCtr_mWriteReg
+#define XTmrCtr_mWriteReg XTmrCtr_WriteReg
+#endif
+
+#ifndef XTmrCtr_mSetControlStatusReg
+#define XTmrCtr_mSetControlStatusReg XTmrCtr_SetControlStatusReg
+#endif
+
+#ifndef XTmrCtr_mGetControlStatusReg
+#define XTmrCtr_mGetControlStatusReg XTmrCtr_GetControlStatusReg
+#endif
+
+#ifndef XTmrCtr_mGetTimerCounterReg
+#define XTmrCtr_mGetTimerCounterReg XTmrCtr_GetTimerCounterReg
+#endif
+
+#ifndef XTmrCtr_mSetLoadReg
+#define XTmrCtr_mSetLoadReg XTmrCtr_SetLoadReg
+#endif
+
+#ifndef XTmrCtr_mGetLoadReg
+#define XTmrCtr_mGetLoadReg XTmrCtr_GetLoadReg
+#endif
+
+#ifndef XTmrCtr_mEnable
+#define XTmrCtr_mEnable XTmrCtr_Enable
+#endif
+
+#ifndef XTmrCtr_mDisable
+#define XTmrCtr_mDisable XTmrCtr_Disable
+#endif
+
+#ifndef XTmrCtr_mEnableIntr
+#define XTmrCtr_mEnableIntr XTmrCtr_EnableIntr
+#endif
+
+#ifndef XTmrCtr_mDisableIntr
+#define XTmrCtr_mDisableIntr XTmrCtr_DisableIntr
+#endif
+
+#ifndef XTmrCtr_mLoadTimerCounterReg
+#define XTmrCtr_mLoadTimerCounterReg XTmrCtr_LoadTimerCounterReg
+#endif
+
+#ifndef XTmrCtr_mHasEventOccurred
+#define XTmrCtr_mHasEventOccurred XTmrCtr_HasEventOccurred
+#endif
+
+/*********************************************************************/
+/**
+ * Macros for Driver XUartLite
+ *
+ *********************************************************************/
+#ifndef XUartLite_mUpdateStats
+#define XUartLite_mUpdateStats XUartLite_UpdateStats
+#endif
+
+#ifndef XUartLite_mWriteReg
+#define XUartLite_mWriteReg XUartLite_WriteReg
+#endif
+
+#ifndef XUartLite_mReadReg
+#define XUartLite_mReadReg XUartLite_ReadReg
+#endif
+
+#ifndef XUartLite_mClearStats
+#define XUartLite_mClearStats XUartLite_ClearStats
+#endif
+
+#ifndef XUartLite_mSetControlReg
+#define XUartLite_mSetControlReg XUartLite_SetControlReg
+#endif
+
+#ifndef XUartLite_mGetStatusReg
+#define XUartLite_mGetStatusReg XUartLite_GetStatusReg
+#endif
+
+#ifndef XUartLite_mIsReceiveEmpty
+#define XUartLite_mIsReceiveEmpty XUartLite_IsReceiveEmpty
+#endif
+
+#ifndef XUartLite_mIsTransmitFull
+#define XUartLite_mIsTransmitFull XUartLite_IsTransmitFull
+#endif
+
+#ifndef XUartLite_mIsIntrEnabled
+#define XUartLite_mIsIntrEnabled XUartLite_IsIntrEnabled
+#endif
+
+#ifndef XUartLite_mEnableIntr
+#define XUartLite_mEnableIntr XUartLite_EnableIntr
+#endif
+
+#ifndef XUartLite_mDisableIntr
+#define XUartLite_mDisableIntr XUartLite_DisableIntr
+#endif
+
+/*********************************************************************/
+/**
+ * Macros for Driver XUartNs550
+ *
+ *********************************************************************/
+#ifndef XUartNs550_mUpdateStats
+#define XUartNs550_mUpdateStats XUartNs550_UpdateStats
+#endif
+
+#ifndef XUartNs550_mReadReg
+#define XUartNs550_mReadReg XUartNs550_ReadReg
+#endif
+
+#ifndef XUartNs550_mWriteReg
+#define XUartNs550_mWriteReg XUartNs550_WriteReg
+#endif
+
+#ifndef XUartNs550_mClearStats
+#define XUartNs550_mClearStats XUartNs550_ClearStats
+#endif
+
+#ifndef XUartNs550_mGetLineStatusReg
+#define XUartNs550_mGetLineStatusReg XUartNs550_GetLineStatusReg
+#endif
+
+#ifndef XUartNs550_mGetLineControlReg
+#define XUartNs550_mGetLineControlReg XUartNs550_GetLineControlReg
+#endif
+
+#ifndef XUartNs550_mSetLineControlReg
+#define XUartNs550_mSetLineControlReg XUartNs550_SetLineControlReg
+#endif
+
+#ifndef XUartNs550_mEnableIntr
+#define XUartNs550_mEnableIntr XUartNs550_EnableIntr
+#endif
+
+#ifndef XUartNs550_mDisableIntr
+#define XUartNs550_mDisableIntr XUartNs550_DisableIntr
+#endif
+
+#ifndef XUartNs550_mIsReceiveData
+#define XUartNs550_mIsReceiveData XUartNs550_IsReceiveData
+#endif
+
+#ifndef XUartNs550_mIsTransmitEmpty
+#define XUartNs550_mIsTransmitEmpty XUartNs550_IsTransmitEmpty
+#endif
+
+/*********************************************************************/
+/**
+ * Macros for Driver XUsb
+ *
+ *********************************************************************/
+#ifndef XUsb_mReadReg
+#define XUsb_mReadReg XUsb_ReadReg
+#endif
+
+#ifndef XUsb_mWriteReg
+#define XUsb_mWriteReg XUsb_WriteReg
+#endif
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff --git a/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/include/xil_mem.h b/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/include/xil_mem.h
new file mode 100644
index 0000000..4327b96
--- /dev/null
+++ b/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/include/xil_mem.h
@@ -0,0 +1,66 @@
+/******************************************************************************/
+/**
+* Copyright (C) 2015 - 2019 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+* THE SOFTWARE.
+*
+*
+*
+******************************************************************************/
+/****************************************************************************/
+/**
+* @file xil_mem.h
+*
+* @addtogroup common_mem_operation_api Customized APIs for Memory Operations
+*
+* The xil_mem.h file contains prototype for functions related
+* to memory operations. These APIs are applicable for all processors supported
+* by Xilinx.
+*
+* @{
+* <pre>
+* MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ----- -------- -------- -----------------------------------------------
+* 6.1 nsk 11/07/16 First release.
+* 7.0 mus 01/07/19 Add cpp extern macro
+*
+* </pre>
+*
+*****************************************************************************/
+#ifndef XIL_MEM_H /* prevent circular inclusions */
+#define XIL_MEM_H /* by using protection macros */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/************************** Function Prototypes *****************************/
+
+void Xil_MemCpy(void* dst, const void* src, u32 cnt);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* XIL_MEM_H */
+/**
+* @} End of "addtogroup common_mem_operation_api".
+*/
\ No newline at end of file
diff --git a/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/include/xil_misc_psreset_api.h b/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/include/xil_misc_psreset_api.h
new file mode 100644
index 0000000..76e2c1b
--- /dev/null
+++ b/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/include/xil_misc_psreset_api.h
@@ -0,0 +1,271 @@
+/******************************************************************************
+*
+* Copyright (C) 2013 - 2015 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+* THE SOFTWARE.
+*
+*
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+* @file xil_misc_psreset_api.h
+*
+* This file contains the various register definitions and function prototypes for
+* implementing the reset functionality of zynq ps devices
+*
+* MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ----- ---- -------- -------------------------------------------------------
+* 1.00b kpc 03/07/13 First release.
+* </pre>
+*
+******************************************************************************/
+
+#ifndef XIL_MISC_RESET_H /* prevent circular inclusions */
+#define XIL_MISC_RESET_H /* by using protection macros */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+
+/***************************** Include Files *********************************/
+#include "xil_types.h"
+#include "xil_io.h"
+
+/************************** Constant Definitions *****************************/
+#define XDDRC_CTRL_BASEADDR 0xF8006000U
+#define XSLCR_BASEADDR 0xF8000000U
+/**< OCM configuration register */
+#define XSLCR_OCM_CFG_ADDR (XSLCR_BASEADDR + 0x00000910U)
+/**< SLCR unlock register */
+#define XSLCR_UNLOCK_ADDR (XSLCR_BASEADDR + 0x00000008U)
+/**< SLCR GEM0 rx clock control register */
+#define XSLCR_GEM0_RCLK_CTRL_ADDR (XSLCR_BASEADDR + 0x00000138U)
+/**< SLCR GEM1 rx clock control register */
+#define XSLCR_GEM1_RCLK_CTRL_ADDR (XSLCR_BASEADDR + 0x0000013CU)
+/**< SLCR GEM0 clock control register */
+#define XSLCR_GEM0_CLK_CTRL_ADDR (XSLCR_BASEADDR + 0x00000140U)
+/**< SLCR GEM1 clock control register */
+#define XSLCR_GEM1_CLK_CTRL_ADDR (XSLCR_BASEADDR + 0x00000144U)
+/**< SLCR SMC clock control register */
+#define XSLCR_SMC_CLK_CTRL_ADDR (XSLCR_BASEADDR + 0x00000148U)
+/**< SLCR GEM reset control register */
+#define XSLCR_GEM_RST_CTRL_ADDR (XSLCR_BASEADDR + 0x00000214U)
+/**< SLCR USB0 clock control register */
+#define XSLCR_USB0_CLK_CTRL_ADDR (XSLCR_BASEADDR + 0x00000130U)
+/**< SLCR USB1 clock control register */
+#define XSLCR_USB1_CLK_CTRL_ADDR (XSLCR_BASEADDR + 0x00000134U)
+/**< SLCR USB1 reset control register */
+#define XSLCR_USB_RST_CTRL_ADDR (XSLCR_BASEADDR + 0x00000210U)
+/**< SLCR SMC reset control register */
+#define XSLCR_SMC_RST_CTRL_ADDR (XSLCR_BASEADDR + 0x00000234U)
+/**< SLCR Level shifter enable register */
+#define XSLCR_LVL_SHFTR_EN_ADDR (XSLCR_BASEADDR + 0x00000900U)
+/**< SLCR ARM pll control register */
+#define XSLCR_ARM_PLL_CTRL_ADDR (XSLCR_BASEADDR + 0x00000100U)
+/**< SLCR DDR pll control register */
+#define XSLCR_DDR_PLL_CTRL_ADDR (XSLCR_BASEADDR + 0x00000104U)
+/**< SLCR IO pll control register */
+#define XSLCR_IO_PLL_CTRL_ADDR (XSLCR_BASEADDR + 0x00000108U)
+/**< SLCR ARM pll configuration register */
+#define XSLCR_ARM_PLL_CFG_ADDR (XSLCR_BASEADDR + 0x00000110U)
+/**< SLCR DDR pll configuration register */
+#define XSLCR_DDR_PLL_CFG_ADDR (XSLCR_BASEADDR + 0x00000114U)
+/**< SLCR IO pll configuration register */
+#define XSLCR_IO_PLL_CFG_ADDR (XSLCR_BASEADDR + 0x00000118U)
+/**< SLCR ARM clock control register */
+#define XSLCR_ARM_CLK_CTRL_ADDR (XSLCR_BASEADDR + 0x00000120U)
+/**< SLCR DDR clock control register */
+#define XSLCR_DDR_CLK_CTRL_ADDR (XSLCR_BASEADDR + 0x00000124U)
+/**< SLCR MIO pin address register */
+#define XSLCR_MIO_PIN_00_ADDR (XSLCR_BASEADDR + 0x00000700U)
+/**< SLCR DMAC reset control address register */
+#define XSLCR_DMAC_RST_CTRL_ADDR (XSLCR_BASEADDR + 0x0000020CU)
+/**< SLCR USB reset control address register */
+/*#define XSLCR_USB_RST_CTRL_ADDR (XSLCR_BASEADDR + 0x00000210U)*/
+/**< SLCR GEM reset control address register */
+/*#define XSLCR_GEM_RST_CTRL_ADDR (XSLCR_BASEADDR + 0x00000214U)*/
+/**< SLCR SDIO reset control address register */
+#define XSLCR_SDIO_RST_CTRL_ADDR (XSLCR_BASEADDR + 0x00000218U)
+/**< SLCR SPI reset control address register */
+#define XSLCR_SPI_RST_CTRL_ADDR (XSLCR_BASEADDR + 0x0000021CU)
+/**< SLCR CAN reset control address register */
+#define XSLCR_CAN_RST_CTRL_ADDR (XSLCR_BASEADDR + 0x00000220U)
+/**< SLCR I2C reset control address register */
+#define XSLCR_I2C_RST_CTRL_ADDR (XSLCR_BASEADDR + 0x00000224U)
+/**< SLCR UART reset control address register */
+#define XSLCR_UART_RST_CTRL_ADDR (XSLCR_BASEADDR + 0x00000228U)
+/**< SLCR GPIO reset control address register */
+#define XSLCR_GPIO_RST_CTRL_ADDR (XSLCR_BASEADDR + 0x0000022CU)
+/**< SLCR LQSPI reset control address register */
+#define XSLCR_LQSPI_RST_CTRL_ADDR (XSLCR_BASEADDR + 0x00000230U)
+/**< SLCR SMC reset control address register */
+/*#define XSLCR_SMC_RST_CTRL_ADDR (XSLCR_BASEADDR + 0x00000234U)*/
+/**< SLCR OCM reset control address register */
+#define XSLCR_OCM_RST_CTRL_ADDR (XSLCR_BASEADDR + 0x00000238U)
+
+/**< SMC mem controller clear config register */
+#define XSMC_MEMC_CLR_CONFIG_OFFSET 0x0000000CU
+/**< SMC idlecount configuration register */
+#define XSMC_REFRESH_PERIOD_0_OFFSET 0x00000020U
+#define XSMC_REFRESH_PERIOD_1_OFFSET 0x00000024U
+/**< SMC ECC configuration register */
+#define XSMC_ECC_MEMCFG1_OFFSET 0x00000404U
+/**< SMC ECC command 1 register */
+#define XSMC_ECC_MEMCMD1_OFFSET 0x00000404U
+/**< SMC ECC command 2 register */
+#define XSMC_ECC_MEMCMD2_OFFSET 0x00000404U
+
+/**< SLCR unlock code */
+#define XSLCR_UNLOCK_CODE 0x0000DF0DU
+
+/**< SMC mem clear configuration mask */
+#define XSMC_MEMC_CLR_CONFIG_MASK 0x000005FU
+/**< SMC ECC memconfig 1 reset value */
+#define XSMC_ECC_MEMCFG1_RESET_VAL 0x0000043U
+/**< SMC ECC memcommand 1 reset value */
+#define XSMC_ECC_MEMCMD1_RESET_VAL 0x01300080U
+/**< SMC ECC memcommand 2 reset value */
+#define XSMC_ECC_MEMCMD2_RESET_VAL 0x01E00585U
+
+/**< DDR controller reset bit mask */
+#define XDDRPS_CTRL_RESET_MASK 0x00000001U
+/**< SLCR OCM configuration reset value*/
+#define XSLCR_OCM_CFG_RESETVAL 0x00000008U
+/**< SLCR OCM bank selection mask*/
+#define XSLCR_OCM_CFG_HIADDR_MASK 0x0000000FU
+/**< SLCR level shifter enable mask*/
+#define XSLCR_LVL_SHFTR_EN_MASK 0x0000000FU
+
+/**< SLCR PLL register reset values */
+#define XSLCR_ARM_PLL_CTRL_RESET_VAL 0x0001A008U
+#define XSLCR_DDR_PLL_CTRL_RESET_VAL 0x0001A008U
+#define XSLCR_IO_PLL_CTRL_RESET_VAL 0x0001A008U
+#define XSLCR_ARM_PLL_CFG_RESET_VAL 0x00177EA0U
+#define XSLCR_DDR_PLL_CFG_RESET_VAL 0x00177EA0U
+#define XSLCR_IO_PLL_CFG_RESET_VAL 0x00177EA0U
+#define XSLCR_ARM_CLK_CTRL_RESET_VAL 0x1F000400U
+#define XSLCR_DDR_CLK_CTRL_RESET_VAL 0x18400003U
+
+/**< SLCR MIO register default values */
+#define XSLCR_MIO_PIN_00_RESET_VAL 0x00001601U
+#define XSLCR_MIO_PIN_02_RESET_VAL 0x00000601U
+
+/**< SLCR Reset control registers default values */
+#define XSLCR_DMAC_RST_CTRL_VAL 0x00000001U
+#define XSLCR_GEM_RST_CTRL_VAL 0x000000F3U
+#define XSLCR_USB_RST_CTRL_VAL 0x00000003U
+#define XSLCR_I2C_RST_CTRL_VAL 0x00000003U
+#define XSLCR_SPI_RST_CTRL_VAL 0x0000000FU
+#define XSLCR_UART_RST_CTRL_VAL 0x0000000FU
+#define XSLCR_QSPI_RST_CTRL_VAL 0x00000003U
+#define XSLCR_GPIO_RST_CTRL_VAL 0x00000001U
+#define XSLCR_SMC_RST_CTRL_VAL 0x00000003U
+#define XSLCR_OCM_RST_CTRL_VAL 0x00000001U
+#define XSLCR_SDIO_RST_CTRL_VAL 0x00000033U
+#define XSLCR_CAN_RST_CTRL_VAL 0x00000003U
+/**************************** Type Definitions *******************************/
+
+/* the following data type is used to hold a null terminated version string
+ * consisting of the following format, "X.YYX"
+ */
+
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+
+/************************** Function Prototypes ******************************/
+/*
+ * Performs reset operation to the ddr interface
+ */
+void XDdr_ResetHw(void);
+/*
+ * Map the ocm region to post bootrom state
+ */
+void XOcm_Remap(void);
+/*
+ * Performs the smc interface reset
+ */
+void XSmc_ResetHw(u32 BaseAddress);
+/*
+ * updates the MIO registers with reset values
+ */
+void XSlcr_MioWriteResetValues(void);
+/*
+ * updates the PLL and clock registers with reset values
+ */
+void XSlcr_PllWriteResetValues(void);
+/*
+ * Disables the level shifters
+ */
+void XSlcr_DisableLevelShifters(void);
+/*
+ * provides softreset to the GPIO interface
+ */
+void XSlcr_GpioPsReset(void);
+/*
+ * provides softreset to the DMA interface
+ */
+void XSlcr_DmaPsReset(void);
+/*
+ * provides softreset to the SMC interface
+ */
+void XSlcr_SmcPsReset(void);
+/*
+ * provides softreset to the CAN interface
+ */
+void XSlcr_CanPsReset(void);
+/*
+ * provides softreset to the Uart interface
+ */
+void XSlcr_UartPsReset(void);
+/*
+ * provides softreset to the I2C interface
+ */
+void XSlcr_I2cPsReset(void);
+/*
+ * provides softreset to the SPI interface
+ */
+void XSlcr_SpiPsReset(void);
+/*
+ * provides softreset to the QSPI interface
+ */
+void XSlcr_QspiPsReset(void);
+/*
+ * provides softreset to the USB interface
+ */
+void XSlcr_UsbPsReset(void);
+/*
+ * provides softreset to the GEM interface
+ */
+void XSlcr_EmacPsReset(void);
+/*
+ * provides softreset to the OCM interface
+ */
+void XSlcr_OcmReset(void);
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* XIL_MISC_RESET_H */
diff --git a/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/include/xil_mmu.h b/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/include/xil_mmu.h
new file mode 100644
index 0000000..749bcdf
--- /dev/null
+++ b/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/include/xil_mmu.h
@@ -0,0 +1,104 @@
+/******************************************************************************
+*
+* Copyright (C) 2012 - 2018 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+* THE SOFTWARE.
+*
+*
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+* @file xil_mmu.h
+*
+* @addtogroup a9_mmu_apis Cortex A9 Processor MMU Functions
+*
+* MMU functions equip users to enable MMU, disable MMU and modify default
+* memory attributes of MMU table as per the need.
+*
+* @{
+*
+* <pre>
+* MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ----- ---- -------- ---------------------------------------------------
+* 1.00a sdm 01/12/12 Initial version
+* 4.2 pkp 07/21/14 Included xil_types.h file which contains definition for
+* u32 which resolves issue of CR#805869
+* 5.4 pkp 23/11/15 Added attribute definitions for Xil_SetTlbAttributes API
+* 6.8 aru 09/06/18 Removed compilation warnings for ARMCC toolchain.
+* </pre>
+*
+*
+******************************************************************************/
+
+#ifndef XIL_MMU_H
+#define XIL_MMU_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif /* __cplusplus */
+
+/***************************** Include Files *********************************/
+
+#include "xil_types.h"
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/**************************** Type Definitions *******************************/
+
+/************************** Constant Definitions *****************************/
+
+/* Memory type */
+#define NORM_NONCACHE 0x11DE2 /* Normal Non-cacheable */
+#define STRONG_ORDERED 0xC02 /* Strongly ordered */
+#define DEVICE_MEMORY 0xC06 /* Device memory */
+#define RESERVED 0x0 /* reserved memory */
+
+/* Normal write-through cacheable shareable */
+#define NORM_WT_CACHE 0x16DEA
+
+/* Normal write back cacheable shareable */
+#define NORM_WB_CACHE 0x15DE6
+
+/* shareability attribute */
+#define SHAREABLE (0x1 << 16)
+#define NON_SHAREABLE (~(0x1 << 16))
+
+/* Execution type */
+#define EXECUTE_NEVER ((0x1 << 4) | (0x1 << 0))
+
+/************************** Variable Definitions *****************************/
+
+/************************** Function Prototypes ******************************/
+
+void Xil_SetTlbAttributes(INTPTR Addr, u32 attrib);
+void Xil_EnableMMU(void);
+void Xil_DisableMMU(void);
+void* Xil_MemMap(UINTPTR PhysAddr, size_t size, u32 flags);
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+
+#endif /* XIL_MMU_H */
+/**
+* @} End of "addtogroup a9_mmu_apis".
+*/
diff --git a/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/include/xil_printf.h b/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/include/xil_printf.h
new file mode 100644
index 0000000..a0177fc
--- /dev/null
+++ b/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/include/xil_printf.h
@@ -0,0 +1,48 @@
+ #ifndef XIL_PRINTF_H
+ #define XIL_PRINTF_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <ctype.h>
+#include <string.h>
+#include <stdarg.h>
+#include "xil_types.h"
+#include "xparameters.h"
+#include "bspconfig.h"
+#if defined (__aarch64__) && HYP_GUEST && EL1_NONSECURE && XEN_USE_PV_CONSOLE
+#include "xen_console.h"
+#endif
+
+/*----------------------------------------------------*/
+/* Use the following parameter passing structure to */
+/* make xil_printf re-entrant. */
+/*----------------------------------------------------*/
+
+struct params_s;
+
+
+/*---------------------------------------------------*/
+/* The purpose of this routine is to output data the */
+/* same as the standard printf function without the */
+/* overhead most run-time libraries involve. Usually */
+/* the printf brings in many kilobytes of code and */
+/* that is unacceptable in most embedded systems. */
+/*---------------------------------------------------*/
+
+typedef char8* charptr;
+typedef s32 (*func_ptr)(int c);
+
+/* */
+
+void xil_printf( const char8 *ctrl1, ...);
+void print( const char8 *ptr);
+extern void outbyte (char8 c);
+extern char8 inbyte(void);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* end of protection macro */
diff --git a/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/include/xil_sleeptimer.h b/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/include/xil_sleeptimer.h
new file mode 100644
index 0000000..4c28d6d
--- /dev/null
+++ b/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/include/xil_sleeptimer.h
@@ -0,0 +1,126 @@
+/******************************************************************************
+*
+* Copyright (C) 2017 - 2019 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+* THE SOFTWARE.
+*
+*
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xil_sleeptimer.h
+*
+* This header file contains ARM Cortex A53,A9,R5 specific sleep related APIs.
+* For sleep related functions that can be used across all Xilinx supported
+* processors, please use xil_sleeptimer.h.
+*
+*
+* <pre>
+* MODIFICATION HISTORY :
+*
+* Ver Who Date Changes
+* ----- ---- -------- -------------------------------------------------------
+* 6.6 srm 10/18/17 First Release.
+* 7.0 mus 01/07/19 Add cpp extern macro
+*
+* </pre>
+*****************************************************************************/
+
+#ifndef XIL_SLEEPTIMER_H /* prevent circular inclusions */
+#define XIL_SLEEPTIMER_H /* by using protection macros */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**************************** Include Files ********************************/
+
+#include "xil_io.h"
+#include "xparameters.h"
+#include "bspconfig.h"
+
+/************************** Constant Definitions *****************************/
+
+#if defined (ARMR5) || (__aarch64__) || (ARMA53_32)
+#define XSLEEP_TIMER_REG_SHIFT 32U
+#define XSleep_ReadCounterVal Xil_In32
+#define XCntrVal u32
+#else
+#define XSLEEP_TIMER_REG_SHIFT 16U
+#define XSleep_ReadCounterVal Xil_In16
+#define XCntrVal u16
+#endif
+
+#if defined(ARMR5) || (defined (__aarch64__) && EL3==1) || defined (ARMA53_32)
+#if defined (versal)
+#define CRL_TTC_RST 0xFF5E0344U
+#define CRL_TTC_BASE_RST_MASK 0x1U
+#else
+#define RST_LPD_IOU2 0xFF5E0238U
+#define RST_LPD_IOU2_TTC_BASE_RESET_MASK 0x00000800U
+#endif
+#endif
+
+#if defined (SLEEP_TIMER_BASEADDR)
+/** @name Register Map
+*
+* Register offsets from the base address of the TTC device
+*
+* @{
+*/
+ #define XSLEEP_TIMER_TTC_CLK_CNTRL_OFFSET 0x00000000U
+ /**< Clock Control Register */
+ #define XSLEEP_TIMER_TTC_CNT_CNTRL_OFFSET 0x0000000CU
+ /**< Counter Control Register*/
+ #define XSLEEP_TIMER_TTC_COUNT_VALUE_OFFSET 0x00000018U
+ /**< Current Counter Value */
+/* @} */
+/** @name Clock Control Register
+* Clock Control Register definitions of TTC
+* @{
+*/
+ #define XSLEEP_TIMER_TTC_CLK_CNTRL_PS_EN_MASK 0x00000001U
+ /**< Prescale enable */
+/* @} */
+/** @name Counter Control Register
+* Counter Control Register definitions of TTC
+* @{
+*/
+#define XSLEEP_TIMER_TTC_CNT_CNTRL_DIS_MASK 0x00000001U
+ /**< Disable the counter */
+#define XSLEEP_TIMER_TTC_CNT_CNTRL_RST_MASK 0x00000010U
+ /**< Reset counter */
+/* @} */
+
+/**************************** Type Definitions *******************************/
+
+/************************** Function Prototypes ******************************/
+
+void Xil_SleepTTCCommon(u32 delay, u64 frequency);
+void XTime_StartTTCTimer();
+
+#endif
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* XIL_SLEEPTIMER_H */
diff --git a/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/include/xil_testcache.h b/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/include/xil_testcache.h
new file mode 100644
index 0000000..f9d7f19
--- /dev/null
+++ b/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/include/xil_testcache.h
@@ -0,0 +1,65 @@
+/******************************************************************************
+*
+* Copyright (C) 2009 - 2015 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+* THE SOFTWARE.
+*
+*
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xil_testcache.h
+*
+* @addtogroup common_test_utils
+* <h2>Cache test </h2>
+* The xil_testcache.h file contains utility functions to test cache.
+*
+* @{
+* <pre>
+* Ver Who Date Changes
+* ----- ---- -------- -----------------------------------------------
+* 1.00a hbm 07/29/09 First release
+* </pre>
+*
+******************************************************************************/
+
+#ifndef XIL_TESTCACHE_H /* prevent circular inclusions */
+#define XIL_TESTCACHE_H /* by using protection macros */
+
+#include "xil_types.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+extern s32 Xil_TestDCacheRange(void);
+extern s32 Xil_TestDCacheAll(void);
+extern s32 Xil_TestICacheRange(void);
+extern s32 Xil_TestICacheAll(void);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* end of protection macro */
+/**
+* @} End of "addtogroup common_test_utils".
+*/
\ No newline at end of file
diff --git a/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/include/xil_testio.h b/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/include/xil_testio.h
new file mode 100644
index 0000000..747c49a
--- /dev/null
+++ b/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/include/xil_testio.h
@@ -0,0 +1,88 @@
+/******************************************************************************
+*
+* Copyright (C) 2009 - 2015 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+* THE SOFTWARE.
+*
+*
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xil_testio.h
+*
+* @addtogroup common_test_utils Test Utilities
+* <h2>I/O test </h2>
+* The xil_testio.h file contains utility functions to test endian related memory
+* IO functions.
+*
+* A subset of the memory tests can be selected or all of the tests can be run
+* in order. If there is an error detected by a subtest, the test stops and the
+* failure code is returned. Further tests are not run even if all of the tests
+* are selected.
+*
+* @{
+* <pre>
+* MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ----- ---- -------- -----------------------------------------------
+* 1.00 hbm 08/05/09 First release
+* </pre>
+*
+******************************************************************************/
+
+#ifndef XIL_TESTIO_H /* prevent circular inclusions */
+#define XIL_TESTIO_H /* by using protection macros */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/***************************** Include Files *********************************/
+#include "xil_types.h"
+
+/************************** Constant Definitions *****************************/
+
+
+#define XIL_TESTIO_DEFAULT 0
+#define XIL_TESTIO_LE 1
+#define XIL_TESTIO_BE 2
+
+/**************************** Type Definitions *******************************/
+
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+
+/************************** Function Prototypes ******************************/
+
+extern s32 Xil_TestIO8(u8 *Addr, s32 Length, u8 Value);
+extern s32 Xil_TestIO16(u16 *Addr, s32 Length, u16 Value, s32 Kind, s32 Swap);
+extern s32 Xil_TestIO32(u32 *Addr, s32 Length, u32 Value, s32 Kind, s32 Swap);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* end of protection macro */
+/**
+* @} End of "addtogroup common_test_utils".
+*/
diff --git a/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/include/xil_testmem.h b/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/include/xil_testmem.h
new file mode 100644
index 0000000..6d9c597
--- /dev/null
+++ b/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/include/xil_testmem.h
@@ -0,0 +1,152 @@
+/******************************************************************************
+*
+* Copyright (C) 2009 - 2015 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+* THE SOFTWARE.
+*
+*
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xil_testmem.h
+* @addtogroup common_test_utils
+*
+* <h2>Memory test</h2>
+*
+* The xil_testmem.h file contains utility functions to test memory.
+* A subset of the memory tests can be selected or all of the tests can be run
+* in order. If there is an error detected by a subtest, the test stops and the
+* failure code is returned. Further tests are not run even if all of the tests
+* are selected.
+* Following list describes the supported memory tests:
+*
+* - XIL_TESTMEM_ALLMEMTESTS: This test runs all of the subtests.
+*
+* - XIL_TESTMEM_INCREMENT: This test
+* starts at 'XIL_TESTMEM_INIT_VALUE' and uses the incrementing value as the
+* test value for memory.
+*
+* - XIL_TESTMEM_WALKONES: Also known as the Walking ones test. This test
+* uses a walking '1' as the test value for memory.
+* @code
+* location 1 = 0x00000001
+* location 2 = 0x00000002
+* ...
+* @endcode
+*
+* - XIL_TESTMEM_WALKZEROS: Also known as the Walking zero's test.
+* This test uses the inverse value of the walking ones test
+* as the test value for memory.
+* @code
+* location 1 = 0xFFFFFFFE
+* location 2 = 0xFFFFFFFD
+* ...
+*@endcode
+*
+* - XIL_TESTMEM_INVERSEADDR: Also known as the inverse address test.
+* This test uses the inverse of the address of the location under test
+* as the test value for memory.
+*
+* - XIL_TESTMEM_FIXEDPATTERN: Also known as the fixed pattern test.
+* This test uses the provided patters as the test value for memory.
+* If zero is provided as the pattern the test uses '0xDEADBEEF".
+*
+* @warning
+* The tests are <b>DESTRUCTIVE</b>. Run before any initialized memory spaces
+* have been set up.
+* The address provided to the memory tests is not checked for
+* validity except for the NULL case. It is possible to provide a code-space
+* pointer for this test to start with and ultimately destroy executable code
+* causing random failures.
+*
+* @note
+* Used for spaces where the address range of the region is smaller than
+* the data width. If the memory range is greater than 2 ** width,
+* the patterns used in XIL_TESTMEM_WALKONES and XIL_TESTMEM_WALKZEROS will
+* repeat on a boundary of a power of two making it more difficult to detect
+* addressing errors. The XIL_TESTMEM_INCREMENT and XIL_TESTMEM_INVERSEADDR
+* tests suffer the same problem. Ideally, if large blocks of memory are to be
+* tested, break them up into smaller regions of memory to allow the test
+* patterns used not to repeat over the region tested.
+*
+* <pre>
+* MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ----- ---- -------- -----------------------------------------------
+* 1.00a hbm 08/25/09 First release
+* </pre>
+*
+******************************************************************************/
+
+#ifndef XIL_TESTMEM_H /* prevent circular inclusions */
+#define XIL_TESTMEM_H /* by using protection macros */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/***************************** Include Files *********************************/
+#include "xil_types.h"
+
+/************************** Constant Definitions *****************************/
+
+
+/**************************** Type Definitions *******************************/
+
+/* xutil_memtest defines */
+
+#define XIL_TESTMEM_INIT_VALUE 1U
+
+/** @name Memory subtests
+ * @{
+ */
+/**
+ * See the detailed description of the subtests in the file description.
+ */
+#define XIL_TESTMEM_ALLMEMTESTS 0x00U
+#define XIL_TESTMEM_INCREMENT 0x01U
+#define XIL_TESTMEM_WALKONES 0x02U
+#define XIL_TESTMEM_WALKZEROS 0x03U
+#define XIL_TESTMEM_INVERSEADDR 0x04U
+#define XIL_TESTMEM_FIXEDPATTERN 0x05U
+#define XIL_TESTMEM_MAXTEST XIL_TESTMEM_FIXEDPATTERN
+/* @} */
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+
+/************************** Function Prototypes ******************************/
+
+/* xutil_testmem prototypes */
+
+extern s32 Xil_TestMem32(u32 *Addr, u32 Words, u32 Pattern, u8 Subtest);
+extern s32 Xil_TestMem16(u16 *Addr, u32 Words, u16 Pattern, u8 Subtest);
+extern s32 Xil_TestMem8(u8 *Addr, u32 Words, u8 Pattern, u8 Subtest);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* end of protection macro */
+/**
+* @} End of "addtogroup common_test_utils".
+*/
diff --git a/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/include/xil_types.h b/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/include/xil_types.h
new file mode 100644
index 0000000..f88edf2
--- /dev/null
+++ b/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/include/xil_types.h
@@ -0,0 +1,217 @@
+/******************************************************************************
+*
+* Copyright (C) 2010 - 2019 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+* THE SOFTWARE.
+*
+*
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xil_types.h
+*
+* @addtogroup common_types Basic Data types for Xilinx® Software IP
+*
+* The xil_types.h file contains basic types for Xilinx software IP. These data types
+* are applicable for all processors supported by Xilinx.
+* @{
+* <pre>
+* MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ----- ---- -------- -------------------------------------------------------
+* 1.00a hbm 07/14/09 First release
+* 3.03a sdm 05/30/11 Added Xuint64 typedef and XUINT64_MSW/XUINT64_LSW macros
+* 5.00 pkp 05/29/14 Made changes for 64 bit architecture
+* srt 07/14/14 Use standard definitions from stdint.h and stddef.h
+* Define LONG and ULONG datatypes and mask values
+* 7.00 mus 01/07/19 Add cpp extern macro
+* 7.1 aru 08/19/19 Shift the value in UPPER_32_BITS only if it
+* is 64-bit processor
+* </pre>
+*
+******************************************************************************/
+
+#ifndef XIL_TYPES_H /* prevent circular inclusions */
+#define XIL_TYPES_H /* by using protection macros */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <stdint.h>
+#include <stddef.h>
+
+/************************** Constant Definitions *****************************/
+
+#ifndef TRUE
+# define TRUE 1U
+#endif
+
+#ifndef FALSE
+# define FALSE 0U
+#endif
+
+#ifndef NULL
+#define NULL 0U
+#endif
+
+#define XIL_COMPONENT_IS_READY 0x11111111U /**< In device drivers, This macro will be
+ assigend to "IsReady" member of driver
+ instance to indicate that driver
+ instance is initialized and ready to use. */
+#define XIL_COMPONENT_IS_STARTED 0x22222222U /**< In device drivers, This macro will be assigend to
+ "IsStarted" member of driver instance
+ to indicate that driver instance is
+ started and it can be enabled. */
+
+/* @name New types
+ * New simple types.
+ * @{
+ */
+#ifndef __KERNEL__
+#ifndef XBASIC_TYPES_H
+/*
+ * guarded against xbasic_types.h.
+ */
+typedef uint8_t u8;
+typedef uint16_t u16;
+typedef uint32_t u32;
+/** @}*/
+#define __XUINT64__
+typedef struct
+{
+ u32 Upper;
+ u32 Lower;
+} Xuint64;
+
+
+/*****************************************************************************/
+/**
+* @brief Return the most significant half of the 64 bit data type.
+*
+* @param x is the 64 bit word.
+*
+* @return The upper 32 bits of the 64 bit word.
+*
+******************************************************************************/
+#define XUINT64_MSW(x) ((x).Upper)
+
+/*****************************************************************************/
+/**
+* @brief Return the least significant half of the 64 bit data type.
+*
+* @param x is the 64 bit word.
+*
+* @return The lower 32 bits of the 64 bit word.
+*
+******************************************************************************/
+#define XUINT64_LSW(x) ((x).Lower)
+
+#endif /* XBASIC_TYPES_H */
+
+/*
+ * xbasic_types.h does not typedef s* or u64
+ */
+/** @{ */
+typedef char char8;
+typedef int8_t s8;
+typedef int16_t s16;
+typedef int32_t s32;
+typedef int64_t s64;
+typedef uint64_t u64;
+typedef int sint32;
+
+typedef intptr_t INTPTR;
+typedef uintptr_t UINTPTR;
+typedef ptrdiff_t PTRDIFF;
+/** @}*/
+#if !defined(LONG) || !defined(ULONG)
+typedef long LONG;
+typedef unsigned long ULONG;
+#endif
+
+#define ULONG64_HI_MASK 0xFFFFFFFF00000000U
+#define ULONG64_LO_MASK ~ULONG64_HI_MASK
+
+#else
+#include <linux/types.h>
+#endif
+
+/** @{ */
+/**
+ * This data type defines an interrupt handler for a device.
+ * The argument points to the instance of the component
+ */
+typedef void (*XInterruptHandler) (void *InstancePtr);
+
+/**
+ * This data type defines an exception handler for a processor.
+ * The argument points to the instance of the component
+ */
+typedef void (*XExceptionHandler) (void *InstancePtr);
+
+/**
+ * @brief Returns 32-63 bits of a number.
+ * @param n : Number being accessed.
+ * @return Bits 32-63 of number.
+ *
+ * @note A basic shift-right of a 64- or 32-bit quantity.
+ * Use this to suppress the "right shift count >= width of type"
+ * warning when that quantity is 32-bits.
+ */
+#if defined (__aarch64__) || defined (__arch64__)
+#define UPPER_32_BITS(n) ((u32)(((n) >> 16) >> 16))
+#else
+#define UPPER_32_BITS(n) 0U
+#endif
+/**
+ * @brief Returns 0-31 bits of a number
+ * @param n : Number being accessed.
+ * @return Bits 0-31 of number
+ */
+#define LOWER_32_BITS(n) ((u32)(n))
+
+
+
+
+/************************** Constant Definitions *****************************/
+
+#ifndef TRUE
+#define TRUE 1U
+#endif
+
+#ifndef FALSE
+#define FALSE 0U
+#endif
+
+#ifndef NULL
+#define NULL 0U
+#endif
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* end of protection macro */
+/**
+* @} End of "addtogroup common_types".
+*/
diff --git a/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/include/xil_util.h b/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/include/xil_util.h
new file mode 100644
index 0000000..41eae4b
--- /dev/null
+++ b/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/include/xil_util.h
@@ -0,0 +1,112 @@
+/******************************************************************************/
+/**
+* Copyright (C) 2019 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+* THE SOFTWARE.
+*
+*
+*
+******************************************************************************/
+/****************************************************************************/
+/**
+* @file xil_util.h
+*
+* This file contains xil utility functions declaration
+*
+* <pre>
+* MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ----- -------- -------- -----------------------------------------------
+* 6.4 mmd 04/21/19 First release.
+*
+* </pre>
+*
+*****************************************************************************/
+
+#ifndef XIL_UTIL_H_
+#define XIL_UTIL_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include "xil_types.h"
+#include "xil_io.h"
+#include "xstatus.h"
+
+/*************************** Constant Definitions *****************************/
+#define XIL_SIZE_OF_NIBBLE_IN_BITS 4U
+#define XIL_SIZE_OF_BYTE_IN_BITS 8U
+
+/* Maximum string length handled by Xil_ValidateHexStr function */
+#define XIL_MAX_HEX_STR_LEN 512U
+
+
+/****************** Macros (Inline Functions) Definitions *********************/
+
+/******************************************************************************/
+/**
+* This API ceils the provided float value.
+*
+* @param Value is a float variable which has to ceiled to nearest
+* integer.
+*
+* @return Returns ceiled value.
+*
+* @note one.
+*
+*******************************************************************************/
+#define Xil_Ceil(Value) \
+ (((Value > (u32)Value) || ((u32)Value == 0U)) ? \
+ (u32)((u32)Value + 1U) : (u32)Value)
+
+
+/*************************** Function Prototypes ******************************/
+
+/* Converts input character to nibble */
+u32 Xil_ConvertCharToNibble(u8 InChar, u8 *Num);
+
+/* Convert input hex string to array of 32-bits integers */
+u32 Xil_ConvertStringToHex(const char *Str, u32 *buf, u8 Len);
+
+/* Waits for specified event */
+u32 Xil_WaitForEvent(u32 RegAddr, u32 EventMask, u32 Event, u32 Timeout);
+
+/* Waits for specified events */
+u32 Xil_WaitForEvents(u32 EventsRegAddr, u32 EventsMask, u32 WaitEvents,
+ u32 Timeout, u32* Events);
+
+/* Validate input hex character */
+u32 Xil_IsValidHexChar(const char Ch);
+
+/* Validate the input string contains only hexadecimal characters */
+u32 Xil_ValidateHexStr(const char *HexStr);
+
+/* Convert string to hex numbers in little enidian format */
+u32 Xil_ConvertStringToHexLE(const char *Str, u8 *Buf, u32 Len);
+
+/* Returns length of the input string */
+u32 Xil_Strnlen(const char *Str, u32 MaxLen);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* XIL_UTIL_H_ */
diff --git a/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/include/xilrsa.h b/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/include/xilrsa.h
new file mode 100644
index 0000000..7eef0a9
--- /dev/null
+++ b/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/include/xilrsa.h
@@ -0,0 +1,250 @@
+/******************************************************************************
+*
+* Copyright (C) 2014 - 17 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+* THE SOFTWARE.
+*
+*
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xilrsa.h
+* @addtogroup xilrsa_apis XilRSA APIs and Descriptions
+* @{
+* @cond xilrsa_internal
+* This file contains the RSA algorithm functions
+*
+* <pre>
+* MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ----- ---- -------- -------------------------------------------------------
+* 1.0 hk 27/01/14 First release
+* 1.4 vns 07/06/17 Added dooxygen tags.
+*
+* </pre>
+*
+* @note
+*
+******************************************************************************/
+#ifndef ___XIL_RSA_H___
+#define ___XIL_RSA_H___
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+/***************************** Include Files *********************************/
+
+/*
+ * Digit size selection (32 or 16-bit). If supported by the CPU/compiler,
+ * 32-bit digits are approximately 4 times faster
+ */
+
+//#define RSA_DIGIT_16
+#define RSA_DIGIT_32
+
+/*
+ * RSA loop unrolling selection
+ * RSA main loop can be unrolled 2, 4 or 8 ways
+ */
+#define RSA_UNROLL 1
+
+/*
+ * Select if ARM-optimized code is to be used. Only GCC for ARM is supported
+ */
+//#define RSA_ARM_OPTIMIZED
+
+/*
+ * Check the compatibility of the selection
+ */
+#if defined(RSA_DIGIT_16) && defined(RSA_DIGIT_32)
+ #error Please select a digit size
+#endif
+#if !defined(RSA_DIGIT_16) && !defined(RSA_DIGIT_32)
+ #error Please select just one digit size
+#endif
+#if (!defined(__GNUC__) || !defined(__arm__)) && defined(RSA_ARM_OPTIMIZED)
+ #error Assembly level code is only supported for the GCC/ARM combination
+#endif
+#if (RSA_UNROLL != 1) && (RSA_UNROLL != 2) && (RSA_UNROLL != 4) && (RSA_UNROLL != 8)
+ #error Only 1, 2, 4, and 8 unrolling are supported
+#endif
+
+#ifdef RSA_DIGIT_16
+#define RSA_DIGIT unsigned short
+#define RSA_SDIGIT short
+#define RSA_DDIGIT unsigned long
+#endif
+#ifdef RSA_DIGIT_32
+#define RSA_DIGIT unsigned long
+#define RSA_SDIGIT long
+#define RSA_DDIGIT unsigned long long
+#endif
+
+#define RSA_NUMBER RSA_DIGIT *
+#define RSA_NBITS 2048
+#define RSA_NDIGITS (RSA_NBITS/(sizeof(RSA_DIGIT)*8))
+#define RSA_NBYTES (RSA_NDIGITS*sizeof(RSA_DIGIT))
+
+/*
+ * Double-digit to single digit conversion
+ */
+#define RSA_MSB(x) (x >> (sizeof(RSA_DIGIT)*8))
+#define RSA_LSB(x) (x & (RSA_DIGIT)~0)
+
+#define SHA_BLKSIZE 512
+#define SHA_BLKBYTES (SHA_BLKSIZE/8)
+#define SHA_BLKWORDS (SHA_BLKBYTES/4)
+
+#define SHA_VALSIZE 256
+#define SHA_VALBYTES (SHA_VALSIZE/8)
+#define SHA_VALWORDS (SHA_VALBYTES/4)
+
+/*
+ * SHA-256 context structure
+ * Includes SHA-256 state, coalescing buffer to collect the processed strings, and
+ * total byte length counter (used both to manage the buffer and for padding)
+ */
+ //! [sha2_context]
+typedef struct
+{
+ unsigned int state[8];
+ unsigned char buffer[SHA_BLKBYTES];
+ unsigned long long bytes;
+} sha2_context;
+//! [sha2_context]
+/** @}
+@endcond */
+
+/*
+ * RSA-2048 user interfaces
+ */
+/*****************************************************************************/
+/**
+ * @brief
+ * This function is used to encrypt the data using 2048 bit private key.
+ *
+ * @param modular A char pointer which contains the key modulus
+ * @param modular_ext A char pointer which contains the key modulus
+ * extension
+ * @param exponent A char pointer which contains the private key
+ * exponent
+ * @param result A char pointer which contains the encrypted data
+ *
+ * @return None
+ *
+ ******************************************************************************/
+void rsa2048_exp(const unsigned char *base, const unsigned char * modular,
+ const unsigned char *modular_ext, const unsigned char *exponent,
+ unsigned char *result);
+/*****************************************************************************/
+/**
+ * @brief
+ * This function is used to decrypt the data using 2048 bit public key
+ *
+ * @param a RSA_NUMBER containing the decrypted data.
+ * @param x RSA_NUMBER containing the input data
+ * @param e Unsigned number containing the public key exponent
+ * @param m RSA_NUMBER containing the public key modulus
+ * @param rrm RSA_NUMBER containing the public key modulus extension.
+ *
+ * @return None
+ *
+ ******************************************************************************/
+void rsa2048_pubexp(RSA_NUMBER a, RSA_NUMBER x,
+ unsigned long e, RSA_NUMBER m, RSA_NUMBER rrm);
+
+/*
+ * SHA-256 user interfaces
+ */
+/*****************************************************************************/
+/**
+ * @brief
+ * This function calculates the hash for the input data using SHA-256
+ * algorithm. This function internally calls the sha2_init, updates and
+ * finishes functions and updates the result.
+ *
+ * @param In Char pointer which contains the input data.
+ * @param Size Length of the input data
+ * @param Out Pointer to location where resulting hash will be
+ * written.
+ *
+ * @return None
+ *
+ ******************************************************************************/
+void sha_256(const unsigned char *in, const unsigned int size, unsigned char *out);
+/*****************************************************************************/
+/**
+ * @brief
+ * This function initializes the SHA2 context.
+ *
+ * @param ctx Pointer to sha2_context structure that stores status and
+ * buffer.
+ *
+ * @return None
+ *
+ ******************************************************************************/
+void sha2_starts(sha2_context *ctx);
+/*****************************************************************************/
+/**
+ * @brief
+ * This function adds the input data to SHA256 calculation.
+ *
+ * @param ctx Pointer to sha2_context structure that stores status and
+ * buffer.
+ * @param input Pointer to the data to add.
+ * @param Out Length of the input data.
+ *
+ * @return None
+ *
+ ******************************************************************************/
+void sha2_update(sha2_context *ctx, unsigned char* input, unsigned int ilen);
+/*****************************************************************************/
+/**
+ * @brief
+ * This function finishes the SHA calculation.
+ *
+ * @param ctx Pointer to sha2_context structure that stores status and
+ * buffer.
+ * @param output Pointer to the calculated hash data.
+ *
+ * @return None
+ *
+ *
+ ******************************************************************************/
+void sha2_finish(sha2_context *ctx, unsigned char* output);
+
+/*
+ * Preprocessing interface (pre-computation of R*R mod M)
+ */
+/**@cond xilrsa_internal */
+void modular_ext(const unsigned char *modular, unsigned char *res);
+/** @}
+@endcond */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* ___XIL_RSA_H___ */
+/** @} */
+
+
diff --git a/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/include/xl2cc.h b/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/include/xl2cc.h
new file mode 100644
index 0000000..c8c46c9
--- /dev/null
+++ b/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/include/xl2cc.h
@@ -0,0 +1,166 @@
+/******************************************************************************
+*
+* Copyright (C) 2011 - 2015 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+* THE SOFTWARE.
+*
+*
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+* @file xl2cc.h
+*
+* This file contains the address definitions for the PL310 Level-2 Cache
+* Controller.
+*
+* <pre>
+* MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ----- ---- -------- ---------------------------------------------------
+* 1.00a sdm 02/01/10 Initial version
+* 3.10a srt 04/18/13 Implemented ARM Erratas. Please refer to file
+* 'xil_errata.h' for errata description
+* </pre>
+*
+* @note
+*
+* None.
+*
+******************************************************************************/
+
+#ifndef _XL2CC_H_
+#define _XL2CC_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/************************** Constant Definitions *****************************/
+/* L2CC Register Offsets */
+#define XPS_L2CC_ID_OFFSET 0x0000U
+#define XPS_L2CC_TYPE_OFFSET 0x0004U
+#define XPS_L2CC_CNTRL_OFFSET 0x0100U
+#define XPS_L2CC_AUX_CNTRL_OFFSET 0x0104U
+#define XPS_L2CC_TAG_RAM_CNTRL_OFFSET 0x0108U
+#define XPS_L2CC_DATA_RAM_CNTRL_OFFSET 0x010CU
+
+#define XPS_L2CC_EVNT_CNTRL_OFFSET 0x0200U
+#define XPS_L2CC_EVNT_CNT1_CTRL_OFFSET 0x0204U
+#define XPS_L2CC_EVNT_CNT0_CTRL_OFFSET 0x0208U
+#define XPS_L2CC_EVNT_CNT1_VAL_OFFSET 0x020CU
+#define XPS_L2CC_EVNT_CNT0_VAL_OFFSET 0x0210U
+
+#define XPS_L2CC_IER_OFFSET 0x0214U /* Interrupt Mask */
+#define XPS_L2CC_IPR_OFFSET 0x0218U /* Masked interrupt status */
+#define XPS_L2CC_ISR_OFFSET 0x021CU /* Raw Interrupt Status */
+#define XPS_L2CC_IAR_OFFSET 0x0220U /* Interrupt Clear */
+
+#define XPS_L2CC_CACHE_SYNC_OFFSET 0x0730U /* Cache Sync */
+#define XPS_L2CC_DUMMY_CACHE_SYNC_OFFSET 0x0740U /* Dummy Register for Cache Sync */
+#define XPS_L2CC_CACHE_INVLD_PA_OFFSET 0x0770U /* Cache Invalid by PA */
+#define XPS_L2CC_CACHE_INVLD_WAY_OFFSET 0x077CU /* Cache Invalid by Way */
+#define XPS_L2CC_CACHE_CLEAN_PA_OFFSET 0x07B0U /* Cache Clean by PA */
+#define XPS_L2CC_CACHE_CLEAN_INDX_OFFSET 0x07B8U /* Cache Clean by Index */
+#define XPS_L2CC_CACHE_CLEAN_WAY_OFFSET 0x07BCU /* Cache Clean by Way */
+#define XPS_L2CC_CACHE_INV_CLN_PA_OFFSET 0x07F0U /* Cache Invalidate and Clean by PA */
+#define XPS_L2CC_CACHE_INV_CLN_INDX_OFFSET 0x07F8U /* Cache Invalidate and Clean by Index */
+#define XPS_L2CC_CACHE_INV_CLN_WAY_OFFSET 0x07FCU /* Cache Invalidate and Clean by Way */
+
+#define XPS_L2CC_CACHE_DLCKDWN_0_WAY_OFFSET 0x0900U /* Cache Data Lockdown 0 by Way */
+#define XPS_L2CC_CACHE_ILCKDWN_0_WAY_OFFSET 0x0904U /* Cache Instruction Lockdown 0 by Way */
+#define XPS_L2CC_CACHE_DLCKDWN_1_WAY_OFFSET 0x0908U /* Cache Data Lockdown 1 by Way */
+#define XPS_L2CC_CACHE_ILCKDWN_1_WAY_OFFSET 0x090CU /* Cache Instruction Lockdown 1 by Way */
+#define XPS_L2CC_CACHE_DLCKDWN_2_WAY_OFFSET 0x0910U /* Cache Data Lockdown 2 by Way */
+#define XPS_L2CC_CACHE_ILCKDWN_2_WAY_OFFSET 0x0914U /* Cache Instruction Lockdown 2 by Way */
+#define XPS_L2CC_CACHE_DLCKDWN_3_WAY_OFFSET 0x0918U /* Cache Data Lockdown 3 by Way */
+#define XPS_L2CC_CACHE_ILCKDWN_3_WAY_OFFSET 0x091CU /* Cache Instruction Lockdown 3 by Way */
+#define XPS_L2CC_CACHE_DLCKDWN_4_WAY_OFFSET 0x0920U /* Cache Data Lockdown 4 by Way */
+#define XPS_L2CC_CACHE_ILCKDWN_4_WAY_OFFSET 0x0924U /* Cache Instruction Lockdown 4 by Way */
+#define XPS_L2CC_CACHE_DLCKDWN_5_WAY_OFFSET 0x0928U /* Cache Data Lockdown 5 by Way */
+#define XPS_L2CC_CACHE_ILCKDWN_5_WAY_OFFSET 0x092CU /* Cache Instruction Lockdown 5 by Way */
+#define XPS_L2CC_CACHE_DLCKDWN_6_WAY_OFFSET 0x0930U /* Cache Data Lockdown 6 by Way */
+#define XPS_L2CC_CACHE_ILCKDWN_6_WAY_OFFSET 0x0934U /* Cache Instruction Lockdown 6 by Way */
+#define XPS_L2CC_CACHE_DLCKDWN_7_WAY_OFFSET 0x0938U /* Cache Data Lockdown 7 by Way */
+#define XPS_L2CC_CACHE_ILCKDWN_7_WAY_OFFSET 0x093CU /* Cache Instruction Lockdown 7 by Way */
+
+#define XPS_L2CC_CACHE_LCKDWN_LINE_ENABLE_OFFSET 0x0950U /* Cache Lockdown Line Enable */
+#define XPS_L2CC_CACHE_UUNLOCK_ALL_WAY_OFFSET 0x0954U /* Cache Unlock All Lines by Way */
+
+#define XPS_L2CC_ADDR_FILTER_START_OFFSET 0x0C00U /* Start of address filtering */
+#define XPS_L2CC_ADDR_FILTER_END_OFFSET 0x0C04U /* Start of address filtering */
+
+#define XPS_L2CC_DEBUG_CTRL_OFFSET 0x0F40U /* Debug Control Register */
+
+/* XPS_L2CC_CNTRL_OFFSET bit masks */
+#define XPS_L2CC_ENABLE_MASK 0x00000001U /* enables the L2CC */
+
+/* XPS_L2CC_AUX_CNTRL_OFFSET bit masks */
+#define XPS_L2CC_AUX_EBRESPE_MASK 0x40000000U /* Early BRESP Enable */
+#define XPS_L2CC_AUX_IPFE_MASK 0x20000000U /* Instruction Prefetch Enable */
+#define XPS_L2CC_AUX_DPFE_MASK 0x10000000U /* Data Prefetch Enable */
+#define XPS_L2CC_AUX_NSIC_MASK 0x08000000U /* Non-secure interrupt access control */
+#define XPS_L2CC_AUX_NSLE_MASK 0x04000000U /* Non-secure lockdown enable */
+#define XPS_L2CC_AUX_CRP_MASK 0x02000000U /* Cache replacement policy */
+#define XPS_L2CC_AUX_FWE_MASK 0x01800000U /* Force write allocate */
+#define XPS_L2CC_AUX_SAOE_MASK 0x00400000U /* Shared attribute override enable */
+#define XPS_L2CC_AUX_PE_MASK 0x00200000U /* Parity enable */
+#define XPS_L2CC_AUX_EMBE_MASK 0x00100000U /* Event monitor bus enable */
+#define XPS_L2CC_AUX_WAY_SIZE_MASK 0x000E0000U /* Way-size */
+#define XPS_L2CC_AUX_ASSOC_MASK 0x00010000U /* Associativity */
+#define XPS_L2CC_AUX_SAIE_MASK 0x00002000U /* Shared attribute invalidate enable */
+#define XPS_L2CC_AUX_EXCL_CACHE_MASK 0x00001000U /* Exclusive cache configuration */
+#define XPS_L2CC_AUX_SBDLE_MASK 0x00000800U /* Store buffer device limitation Enable */
+#define XPS_L2CC_AUX_HPSODRE_MASK 0x00000400U /* High Priority for SO and Dev Reads Enable */
+#define XPS_L2CC_AUX_FLZE_MASK 0x00000001U /* Full line of zero enable */
+
+#define XPS_L2CC_AUX_REG_DEFAULT_MASK 0x72360000U /* Enable all prefetching, */
+ /* Cache replacement policy, Parity enable, */
+ /* Event monitor bus enable and Way Size (64 KB) */
+#define XPS_L2CC_AUX_REG_ZERO_MASK 0xFFF1FFFFU /* */
+
+#define XPS_L2CC_TAG_RAM_DEFAULT_MASK 0x00000111U /* latency for TAG RAM */
+#define XPS_L2CC_DATA_RAM_DEFAULT_MASK 0x00000121U /* latency for DATA RAM */
+
+/* Interrupt bit masks */
+#define XPS_L2CC_IXR_DECERR_MASK 0x00000100U /* DECERR from L3 */
+#define XPS_L2CC_IXR_SLVERR_MASK 0x00000080U /* SLVERR from L3 */
+#define XPS_L2CC_IXR_ERRRD_MASK 0x00000040U /* Error on L2 data RAM (Read) */
+#define XPS_L2CC_IXR_ERRRT_MASK 0x00000020U /* Error on L2 tag RAM (Read) */
+#define XPS_L2CC_IXR_ERRWD_MASK 0x00000010U /* Error on L2 data RAM (Write) */
+#define XPS_L2CC_IXR_ERRWT_MASK 0x00000008U /* Error on L2 tag RAM (Write) */
+#define XPS_L2CC_IXR_PARRD_MASK 0x00000004U /* Parity Error on L2 data RAM (Read) */
+#define XPS_L2CC_IXR_PARRT_MASK 0x00000002U /* Parity Error on L2 tag RAM (Read) */
+#define XPS_L2CC_IXR_ECNTR_MASK 0x00000001U /* Event Counter1/0 Overflow Increment */
+
+/* Address filtering mask and enable bit */
+#define XPS_L2CC_ADDR_FILTER_VALID_MASK 0xFFF00000U /* Address filtering valid bits*/
+#define XPS_L2CC_ADDR_FILTER_ENABLE_MASK 0x00000001U /* Address filtering enable bit*/
+
+/* Debug control bits */
+#define XPS_L2CC_DEBUG_SPIDEN_MASK 0x00000004U /* Debug SPIDEN bit */
+#define XPS_L2CC_DEBUG_DWB_MASK 0x00000002U /* Debug DWB bit, forces write through */
+#define XPS_L2CC_DEBUG_DCL_MASK 0x00000002U /* Debug DCL bit, disables cache line fill */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* protection macro */
diff --git a/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/include/xl2cc_counter.h b/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/include/xl2cc_counter.h
new file mode 100644
index 0000000..0810d31
--- /dev/null
+++ b/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/include/xl2cc_counter.h
@@ -0,0 +1,108 @@
+/******************************************************************************
+*
+* Copyright (C) 2011 - 2018 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+* THE SOFTWARE.
+*
+*
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xl2cc_counter.h
+*
+* @addtogroup l2_event_counter_apis PL310 L2 Event Counters Functions
+*
+* xl2cc_counter.h contains APIs for configuring and controlling the event
+* counters in PL310 L2 cache controller.
+* PL310 has two event counters which can be used to count variety of events
+* like DRHIT, DRREQ, DWHIT, DWREQ, etc. xl2cc_counter.h contains definitions
+* for different configurations which can be used for the event counters to
+* count a set of events.
+*
+*
+* @{
+*
+* <pre>
+* MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ----- ---- -------- -----------------------------------------------
+* 1.00a sdm 07/11/11 First release
+* 3.07a asa 08/30/12 Updated for CR 675636 to provide the L2 Base Address
+* inside the APIs
+* 6.8 aru 09/06/18 Removed compilation warnings for ARMCC toolchain.
+* </pre>
+*
+******************************************************************************/
+
+#ifndef L2CCCOUNTER_H /* prevent circular inclusions */
+#define L2CCCOUNTER_H /* by using protection macros */
+
+/***************************** Include Files ********************************/
+
+#include "xpseudo_asm.h"
+#include "xil_types.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif /* __cplusplus */
+
+/************************** Constant Definitions ****************************/
+
+/*
+ * The following constants define the event codes for the event counters.
+ */
+#define XL2CC_CO 0x1
+#define XL2CC_DRHIT 0x2
+#define XL2CC_DRREQ 0x3
+#define XL2CC_DWHIT 0x4
+#define XL2CC_DWREQ 0x5
+#define XL2CC_DWTREQ 0x6
+#define XL2CC_IRHIT 0x7
+#define XL2CC_IRREQ 0x8
+#define XL2CC_WA 0x9
+#define XL2CC_IPFALLOC 0xa
+#define XL2CC_EPFHIT 0xb
+#define XL2CC_EPFALLOC 0xc
+#define XL2CC_SRRCVD 0xd
+#define XL2CC_SRCONF 0xe
+#define XL2CC_EPFRCVD 0xf
+
+/**************************** Type Definitions ******************************/
+
+/***************** Macros (Inline Functions) Definitions ********************/
+
+/************************** Variable Definitions ****************************/
+
+/************************** Function Prototypes *****************************/
+
+void XL2cc_EventCtrInit(s32 Event0, s32 Event1);
+void XL2cc_EventCtrStart(void);
+void XL2cc_EventCtrStop(u32 *EveCtr0, u32 *EveCtr1);
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+
+#endif /* L2CCCOUNTER_H */
+/**
+* @} End of "addtogroup l2_event_counter_apis".
+*/
diff --git a/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/include/xparameters.h b/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/include/xparameters.h
new file mode 100644
index 0000000..a62800e
--- /dev/null
+++ b/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/include/xparameters.h
@@ -0,0 +1,617 @@
+#ifndef XPARAMETERS_H /* prevent circular inclusions */
+#define XPARAMETERS_H /* by using protection macros */
+
+/* Definition for CPU ID */
+#define XPAR_CPU_ID 0U
+
+/* Definitions for peripheral PS7_CORTEXA9_0 */
+#define XPAR_PS7_CORTEXA9_0_CPU_CLK_FREQ_HZ 650000000
+
+
+/******************************************************************/
+
+/* Canonical definitions for peripheral PS7_CORTEXA9_0 */
+#define XPAR_CPU_CORTEXA9_0_CPU_CLK_FREQ_HZ 650000000
+
+
+/******************************************************************/
+
+#include "xparameters_ps.h"
+
+#define STDIN_BASEADDRESS 0xE0001000
+#define STDOUT_BASEADDRESS 0xE0001000
+
+/******************************************************************/
+
+/* Platform specific definitions */
+#define PLATFORM_ZYNQ
+
+/* Definitions for sleep timer configuration */
+#define XSLEEP_TIMER_IS_DEFAULT_TIMER
+
+
+/******************************************************************/
+/* Definitions for driver BRAM */
+#define XPAR_XBRAM_NUM_INSTANCES 4U
+
+/* Definitions for peripheral I_BRAM_CTRL_EX_STACK */
+#define XPAR_I_BRAM_CTRL_EX_STACK_DEVICE_ID 0U
+#define XPAR_I_BRAM_CTRL_EX_STACK_DATA_WIDTH 32U
+#define XPAR_I_BRAM_CTRL_EX_STACK_ECC 0U
+#define XPAR_I_BRAM_CTRL_EX_STACK_FAULT_INJECT 0U
+#define XPAR_I_BRAM_CTRL_EX_STACK_CE_FAILING_REGISTERS 0U
+#define XPAR_I_BRAM_CTRL_EX_STACK_UE_FAILING_REGISTERS 0U
+#define XPAR_I_BRAM_CTRL_EX_STACK_ECC_STATUS_REGISTERS 0U
+#define XPAR_I_BRAM_CTRL_EX_STACK_CE_COUNTER_WIDTH 0U
+#define XPAR_I_BRAM_CTRL_EX_STACK_ECC_ONOFF_REGISTER 0U
+#define XPAR_I_BRAM_CTRL_EX_STACK_ECC_ONOFF_RESET_VALUE 0U
+#define XPAR_I_BRAM_CTRL_EX_STACK_WRITE_ACCESS 0U
+#define XPAR_I_BRAM_CTRL_EX_STACK_S_AXI_BASEADDR 0x44000000U
+#define XPAR_I_BRAM_CTRL_EX_STACK_S_AXI_HIGHADDR 0x44001FFFU
+#define XPAR_I_BRAM_CTRL_EX_STACK_S_AXI_CTRL_BASEADDR 0xFFFFFFFFU
+#define XPAR_I_BRAM_CTRL_EX_STACK_S_AXI_CTRL_HIGHADDR 0xFFFFFFFFU
+
+
+/* Definitions for peripheral I_BRAM_CTRL_KEY */
+#define XPAR_I_BRAM_CTRL_KEY_DEVICE_ID 1U
+#define XPAR_I_BRAM_CTRL_KEY_DATA_WIDTH 32U
+#define XPAR_I_BRAM_CTRL_KEY_ECC 0U
+#define XPAR_I_BRAM_CTRL_KEY_FAULT_INJECT 0U
+#define XPAR_I_BRAM_CTRL_KEY_CE_FAILING_REGISTERS 0U
+#define XPAR_I_BRAM_CTRL_KEY_UE_FAILING_REGISTERS 0U
+#define XPAR_I_BRAM_CTRL_KEY_ECC_STATUS_REGISTERS 0U
+#define XPAR_I_BRAM_CTRL_KEY_CE_COUNTER_WIDTH 0U
+#define XPAR_I_BRAM_CTRL_KEY_ECC_ONOFF_REGISTER 0U
+#define XPAR_I_BRAM_CTRL_KEY_ECC_ONOFF_RESET_VALUE 0U
+#define XPAR_I_BRAM_CTRL_KEY_WRITE_ACCESS 0U
+#define XPAR_I_BRAM_CTRL_KEY_S_AXI_BASEADDR 0x40000000U
+#define XPAR_I_BRAM_CTRL_KEY_S_AXI_HIGHADDR 0x40000FFFU
+#define XPAR_I_BRAM_CTRL_KEY_S_AXI_CTRL_BASEADDR 0xFFFFFFFFU
+#define XPAR_I_BRAM_CTRL_KEY_S_AXI_CTRL_HIGHADDR 0xFFFFFFFFU
+
+
+/* Definitions for peripheral I_BRAM_CTRL_LOGIC_ANALYZER */
+#define XPAR_I_BRAM_CTRL_LOGIC_ANALYZER_DEVICE_ID 2U
+#define XPAR_I_BRAM_CTRL_LOGIC_ANALYZER_DATA_WIDTH 32U
+#define XPAR_I_BRAM_CTRL_LOGIC_ANALYZER_ECC 0U
+#define XPAR_I_BRAM_CTRL_LOGIC_ANALYZER_FAULT_INJECT 0U
+#define XPAR_I_BRAM_CTRL_LOGIC_ANALYZER_CE_FAILING_REGISTERS 0U
+#define XPAR_I_BRAM_CTRL_LOGIC_ANALYZER_UE_FAILING_REGISTERS 0U
+#define XPAR_I_BRAM_CTRL_LOGIC_ANALYZER_ECC_STATUS_REGISTERS 0U
+#define XPAR_I_BRAM_CTRL_LOGIC_ANALYZER_CE_COUNTER_WIDTH 0U
+#define XPAR_I_BRAM_CTRL_LOGIC_ANALYZER_ECC_ONOFF_REGISTER 0U
+#define XPAR_I_BRAM_CTRL_LOGIC_ANALYZER_ECC_ONOFF_RESET_VALUE 0U
+#define XPAR_I_BRAM_CTRL_LOGIC_ANALYZER_WRITE_ACCESS 0U
+#define XPAR_I_BRAM_CTRL_LOGIC_ANALYZER_S_AXI_BASEADDR 0x46000000U
+#define XPAR_I_BRAM_CTRL_LOGIC_ANALYZER_S_AXI_HIGHADDR 0x46001FFFU
+#define XPAR_I_BRAM_CTRL_LOGIC_ANALYZER_S_AXI_CTRL_BASEADDR 0xFFFFFFFFU
+#define XPAR_I_BRAM_CTRL_LOGIC_ANALYZER_S_AXI_CTRL_HIGHADDR 0xFFFFFFFFU
+
+
+/* Definitions for peripheral I_BRAM_CTRL_SW_ATT */
+#define XPAR_I_BRAM_CTRL_SW_ATT_DEVICE_ID 3U
+#define XPAR_I_BRAM_CTRL_SW_ATT_DATA_WIDTH 32U
+#define XPAR_I_BRAM_CTRL_SW_ATT_ECC 0U
+#define XPAR_I_BRAM_CTRL_SW_ATT_FAULT_INJECT 0U
+#define XPAR_I_BRAM_CTRL_SW_ATT_CE_FAILING_REGISTERS 0U
+#define XPAR_I_BRAM_CTRL_SW_ATT_UE_FAILING_REGISTERS 0U
+#define XPAR_I_BRAM_CTRL_SW_ATT_ECC_STATUS_REGISTERS 0U
+#define XPAR_I_BRAM_CTRL_SW_ATT_CE_COUNTER_WIDTH 0U
+#define XPAR_I_BRAM_CTRL_SW_ATT_ECC_ONOFF_REGISTER 0U
+#define XPAR_I_BRAM_CTRL_SW_ATT_ECC_ONOFF_RESET_VALUE 0U
+#define XPAR_I_BRAM_CTRL_SW_ATT_WRITE_ACCESS 0U
+#define XPAR_I_BRAM_CTRL_SW_ATT_S_AXI_BASEADDR 0x42000000U
+#define XPAR_I_BRAM_CTRL_SW_ATT_S_AXI_HIGHADDR 0x4200FFFFU
+#define XPAR_I_BRAM_CTRL_SW_ATT_S_AXI_CTRL_BASEADDR 0xFFFFFFFFU
+#define XPAR_I_BRAM_CTRL_SW_ATT_S_AXI_CTRL_HIGHADDR 0xFFFFFFFFU
+
+
+/******************************************************************/
+
+/* Canonical definitions for peripheral I_BRAM_CTRL_EX_STACK */
+#define XPAR_BRAM_0_DEVICE_ID XPAR_I_BRAM_CTRL_EX_STACK_DEVICE_ID
+#define XPAR_BRAM_0_DATA_WIDTH 32U
+#define XPAR_BRAM_0_ECC 0U
+#define XPAR_BRAM_0_FAULT_INJECT 0U
+#define XPAR_BRAM_0_CE_FAILING_REGISTERS 0U
+#define XPAR_BRAM_0_UE_FAILING_REGISTERS 0U
+#define XPAR_BRAM_0_ECC_STATUS_REGISTERS 0U
+#define XPAR_BRAM_0_CE_COUNTER_WIDTH 0U
+#define XPAR_BRAM_0_ECC_ONOFF_REGISTER 0U
+#define XPAR_BRAM_0_ECC_ONOFF_RESET_VALUE 0U
+#define XPAR_BRAM_0_WRITE_ACCESS 0U
+#define XPAR_BRAM_0_BASEADDR 0x44000000U
+#define XPAR_BRAM_0_HIGHADDR 0x44001FFFU
+#define XPAR_BRAM_0_CTRL_BASEADDR 0xFFFFFFFFU
+#define XPAR_BRAM_0_CTRL_HIGHADDR 0xFFFFFFFEU
+
+/* Canonical definitions for peripheral I_BRAM_CTRL_KEY */
+#define XPAR_BRAM_1_DEVICE_ID XPAR_I_BRAM_CTRL_KEY_DEVICE_ID
+#define XPAR_BRAM_1_DATA_WIDTH 32U
+#define XPAR_BRAM_1_ECC 0U
+#define XPAR_BRAM_1_FAULT_INJECT 0U
+#define XPAR_BRAM_1_CE_FAILING_REGISTERS 0U
+#define XPAR_BRAM_1_UE_FAILING_REGISTERS 0U
+#define XPAR_BRAM_1_ECC_STATUS_REGISTERS 0U
+#define XPAR_BRAM_1_CE_COUNTER_WIDTH 0U
+#define XPAR_BRAM_1_ECC_ONOFF_REGISTER 0U
+#define XPAR_BRAM_1_ECC_ONOFF_RESET_VALUE 0U
+#define XPAR_BRAM_1_WRITE_ACCESS 0U
+#define XPAR_BRAM_1_BASEADDR 0x40000000U
+#define XPAR_BRAM_1_HIGHADDR 0x40000FFFU
+#define XPAR_BRAM_1_CTRL_BASEADDR 0xFFFFFFFFU
+#define XPAR_BRAM_1_CTRL_HIGHADDR 0xFFFFFFFEU
+
+/* Canonical definitions for peripheral I_BRAM_CTRL_LOGIC_ANALYZER */
+#define XPAR_BRAM_2_DEVICE_ID XPAR_I_BRAM_CTRL_LOGIC_ANALYZER_DEVICE_ID
+#define XPAR_BRAM_2_DATA_WIDTH 32U
+#define XPAR_BRAM_2_ECC 0U
+#define XPAR_BRAM_2_FAULT_INJECT 0U
+#define XPAR_BRAM_2_CE_FAILING_REGISTERS 0U
+#define XPAR_BRAM_2_UE_FAILING_REGISTERS 0U
+#define XPAR_BRAM_2_ECC_STATUS_REGISTERS 0U
+#define XPAR_BRAM_2_CE_COUNTER_WIDTH 0U
+#define XPAR_BRAM_2_ECC_ONOFF_REGISTER 0U
+#define XPAR_BRAM_2_ECC_ONOFF_RESET_VALUE 0U
+#define XPAR_BRAM_2_WRITE_ACCESS 0U
+#define XPAR_BRAM_2_BASEADDR 0x46000000U
+#define XPAR_BRAM_2_HIGHADDR 0x46001FFFU
+#define XPAR_BRAM_2_CTRL_BASEADDR 0xFFFFFFFFU
+#define XPAR_BRAM_2_CTRL_HIGHADDR 0xFFFFFFFEU
+
+/* Canonical definitions for peripheral I_BRAM_CTRL_SW_ATT */
+#define XPAR_BRAM_3_DEVICE_ID XPAR_I_BRAM_CTRL_SW_ATT_DEVICE_ID
+#define XPAR_BRAM_3_DATA_WIDTH 32U
+#define XPAR_BRAM_3_ECC 0U
+#define XPAR_BRAM_3_FAULT_INJECT 0U
+#define XPAR_BRAM_3_CE_FAILING_REGISTERS 0U
+#define XPAR_BRAM_3_UE_FAILING_REGISTERS 0U
+#define XPAR_BRAM_3_ECC_STATUS_REGISTERS 0U
+#define XPAR_BRAM_3_CE_COUNTER_WIDTH 0U
+#define XPAR_BRAM_3_ECC_ONOFF_REGISTER 0U
+#define XPAR_BRAM_3_ECC_ONOFF_RESET_VALUE 0U
+#define XPAR_BRAM_3_WRITE_ACCESS 0U
+#define XPAR_BRAM_3_BASEADDR 0x42000000U
+#define XPAR_BRAM_3_HIGHADDR 0x4200FFFFU
+#define XPAR_BRAM_3_CTRL_BASEADDR 0xFFFFFFFFU
+#define XPAR_BRAM_3_CTRL_HIGHADDR 0xFFFFFFFEU
+
+
+/******************************************************************/
+
+
+/* Definitions for peripheral PS7_DDR_0 */
+#define XPAR_PS7_DDR_0_S_AXI_BASEADDR 0x00100000
+#define XPAR_PS7_DDR_0_S_AXI_HIGHADDR 0x1FFFFFFF
+
+
+/******************************************************************/
+
+/* Definitions for driver DEVCFG */
+#define XPAR_XDCFG_NUM_INSTANCES 1U
+
+/* Definitions for peripheral PS7_DEV_CFG_0 */
+#define XPAR_PS7_DEV_CFG_0_DEVICE_ID 0U
+#define XPAR_PS7_DEV_CFG_0_BASEADDR 0xF8007000U
+#define XPAR_PS7_DEV_CFG_0_HIGHADDR 0xF80070FFU
+
+
+/******************************************************************/
+
+/* Canonical definitions for peripheral PS7_DEV_CFG_0 */
+#define XPAR_XDCFG_0_DEVICE_ID XPAR_PS7_DEV_CFG_0_DEVICE_ID
+#define XPAR_XDCFG_0_BASEADDR 0xF8007000U
+#define XPAR_XDCFG_0_HIGHADDR 0xF80070FFU
+
+
+/******************************************************************/
+
+/* Definitions for driver DMAPS */
+#define XPAR_XDMAPS_NUM_INSTANCES 2
+
+/* Definitions for peripheral PS7_DMA_NS */
+#define XPAR_PS7_DMA_NS_DEVICE_ID 0
+#define XPAR_PS7_DMA_NS_BASEADDR 0xF8004000
+#define XPAR_PS7_DMA_NS_HIGHADDR 0xF8004FFF
+
+
+/* Definitions for peripheral PS7_DMA_S */
+#define XPAR_PS7_DMA_S_DEVICE_ID 1
+#define XPAR_PS7_DMA_S_BASEADDR 0xF8003000
+#define XPAR_PS7_DMA_S_HIGHADDR 0xF8003FFF
+
+
+/******************************************************************/
+
+/* Canonical definitions for peripheral PS7_DMA_NS */
+#define XPAR_XDMAPS_0_DEVICE_ID XPAR_PS7_DMA_NS_DEVICE_ID
+#define XPAR_XDMAPS_0_BASEADDR 0xF8004000
+#define XPAR_XDMAPS_0_HIGHADDR 0xF8004FFF
+
+/* Canonical definitions for peripheral PS7_DMA_S */
+#define XPAR_XDMAPS_1_DEVICE_ID XPAR_PS7_DMA_S_DEVICE_ID
+#define XPAR_XDMAPS_1_BASEADDR 0xF8003000
+#define XPAR_XDMAPS_1_HIGHADDR 0xF8003FFF
+
+
+/******************************************************************/
+
+/* Definitions for driver EMACPS */
+#define XPAR_XEMACPS_NUM_INSTANCES 1
+
+/* Definitions for peripheral PS7_ETHERNET_0 */
+#define XPAR_PS7_ETHERNET_0_DEVICE_ID 0
+#define XPAR_PS7_ETHERNET_0_BASEADDR 0xE000B000
+#define XPAR_PS7_ETHERNET_0_HIGHADDR 0xE000BFFF
+#define XPAR_PS7_ETHERNET_0_ENET_CLK_FREQ_HZ 125000000
+#define XPAR_PS7_ETHERNET_0_ENET_SLCR_1000MBPS_DIV0 8
+#define XPAR_PS7_ETHERNET_0_ENET_SLCR_1000MBPS_DIV1 1
+#define XPAR_PS7_ETHERNET_0_ENET_SLCR_100MBPS_DIV0 8
+#define XPAR_PS7_ETHERNET_0_ENET_SLCR_100MBPS_DIV1 5
+#define XPAR_PS7_ETHERNET_0_ENET_SLCR_10MBPS_DIV0 8
+#define XPAR_PS7_ETHERNET_0_ENET_SLCR_10MBPS_DIV1 50
+#define XPAR_PS7_ETHERNET_0_ENET_TSU_CLK_FREQ_HZ 0
+
+
+/******************************************************************/
+
+#define XPAR_PS7_ETHERNET_0_IS_CACHE_COHERENT 0
+#define XPAR_XEMACPS_0_IS_CACHE_COHERENT 0
+/* Canonical definitions for peripheral PS7_ETHERNET_0 */
+#define XPAR_XEMACPS_0_DEVICE_ID XPAR_PS7_ETHERNET_0_DEVICE_ID
+#define XPAR_XEMACPS_0_BASEADDR 0xE000B000
+#define XPAR_XEMACPS_0_HIGHADDR 0xE000BFFF
+#define XPAR_XEMACPS_0_ENET_CLK_FREQ_HZ 125000000
+#define XPAR_XEMACPS_0_ENET_SLCR_1000Mbps_DIV0 8
+#define XPAR_XEMACPS_0_ENET_SLCR_1000Mbps_DIV1 1
+#define XPAR_XEMACPS_0_ENET_SLCR_100Mbps_DIV0 8
+#define XPAR_XEMACPS_0_ENET_SLCR_100Mbps_DIV1 5
+#define XPAR_XEMACPS_0_ENET_SLCR_10Mbps_DIV0 8
+#define XPAR_XEMACPS_0_ENET_SLCR_10Mbps_DIV1 50
+#define XPAR_XEMACPS_0_ENET_TSU_CLK_FREQ_HZ 0
+
+
+/******************************************************************/
+
+
+/* Definitions for peripheral PS7_AFI_0 */
+#define XPAR_PS7_AFI_0_S_AXI_BASEADDR 0xF8008000
+#define XPAR_PS7_AFI_0_S_AXI_HIGHADDR 0xF8008FFF
+
+
+/* Definitions for peripheral PS7_AFI_1 */
+#define XPAR_PS7_AFI_1_S_AXI_BASEADDR 0xF8009000
+#define XPAR_PS7_AFI_1_S_AXI_HIGHADDR 0xF8009FFF
+
+
+/* Definitions for peripheral PS7_AFI_2 */
+#define XPAR_PS7_AFI_2_S_AXI_BASEADDR 0xF800A000
+#define XPAR_PS7_AFI_2_S_AXI_HIGHADDR 0xF800AFFF
+
+
+/* Definitions for peripheral PS7_AFI_3 */
+#define XPAR_PS7_AFI_3_S_AXI_BASEADDR 0xF800B000
+#define XPAR_PS7_AFI_3_S_AXI_HIGHADDR 0xF800BFFF
+
+
+/* Definitions for peripheral PS7_DDRC_0 */
+#define XPAR_PS7_DDRC_0_S_AXI_BASEADDR 0xF8006000
+#define XPAR_PS7_DDRC_0_S_AXI_HIGHADDR 0xF8006FFF
+
+
+/* Definitions for peripheral PS7_GLOBALTIMER_0 */
+#define XPAR_PS7_GLOBALTIMER_0_S_AXI_BASEADDR 0xF8F00200
+#define XPAR_PS7_GLOBALTIMER_0_S_AXI_HIGHADDR 0xF8F002FF
+
+
+/* Definitions for peripheral PS7_GPV_0 */
+#define XPAR_PS7_GPV_0_S_AXI_BASEADDR 0xF8900000
+#define XPAR_PS7_GPV_0_S_AXI_HIGHADDR 0xF89FFFFF
+
+
+/* Definitions for peripheral PS7_INTC_DIST_0 */
+#define XPAR_PS7_INTC_DIST_0_S_AXI_BASEADDR 0xF8F01000
+#define XPAR_PS7_INTC_DIST_0_S_AXI_HIGHADDR 0xF8F01FFF
+
+
+/* Definitions for peripheral PS7_IOP_BUS_CONFIG_0 */
+#define XPAR_PS7_IOP_BUS_CONFIG_0_S_AXI_BASEADDR 0xE0200000
+#define XPAR_PS7_IOP_BUS_CONFIG_0_S_AXI_HIGHADDR 0xE0200FFF
+
+
+/* Definitions for peripheral PS7_L2CACHEC_0 */
+#define XPAR_PS7_L2CACHEC_0_S_AXI_BASEADDR 0xF8F02000
+#define XPAR_PS7_L2CACHEC_0_S_AXI_HIGHADDR 0xF8F02FFF
+
+
+/* Definitions for peripheral PS7_OCMC_0 */
+#define XPAR_PS7_OCMC_0_S_AXI_BASEADDR 0xF800C000
+#define XPAR_PS7_OCMC_0_S_AXI_HIGHADDR 0xF800CFFF
+
+
+/* Definitions for peripheral PS7_PL310_0 */
+#define XPAR_PS7_PL310_0_S_AXI_BASEADDR 0xF8F02000
+#define XPAR_PS7_PL310_0_S_AXI_HIGHADDR 0xF8F02FFF
+
+
+/* Definitions for peripheral PS7_PMU_0 */
+#define XPAR_PS7_PMU_0_S_AXI_BASEADDR 0xF8891000
+#define XPAR_PS7_PMU_0_S_AXI_HIGHADDR 0xF8891FFF
+#define XPAR_PS7_PMU_0_PMU1_S_AXI_BASEADDR 0xF8893000
+#define XPAR_PS7_PMU_0_PMU1_S_AXI_HIGHADDR 0xF8893FFF
+
+
+/* Definitions for peripheral PS7_QSPI_LINEAR_0 */
+#define XPAR_PS7_QSPI_LINEAR_0_S_AXI_BASEADDR 0xFC000000
+#define XPAR_PS7_QSPI_LINEAR_0_S_AXI_HIGHADDR 0xFCFFFFFF
+
+
+/* Definitions for peripheral PS7_RAM_0 */
+#define XPAR_PS7_RAM_0_S_AXI_BASEADDR 0x00000000
+#define XPAR_PS7_RAM_0_S_AXI_HIGHADDR 0x0003FFFF
+
+
+/* Definitions for peripheral PS7_RAM_1 */
+#define XPAR_PS7_RAM_1_S_AXI_BASEADDR 0xFFFC0000
+#define XPAR_PS7_RAM_1_S_AXI_HIGHADDR 0xFFFFFFFF
+
+
+/* Definitions for peripheral PS7_SCUC_0 */
+#define XPAR_PS7_SCUC_0_S_AXI_BASEADDR 0xF8F00000
+#define XPAR_PS7_SCUC_0_S_AXI_HIGHADDR 0xF8F000FC
+
+
+/* Definitions for peripheral PS7_SLCR_0 */
+#define XPAR_PS7_SLCR_0_S_AXI_BASEADDR 0xF8000000
+#define XPAR_PS7_SLCR_0_S_AXI_HIGHADDR 0xF8000FFF
+
+
+/* Definitions for peripheral PS7_TRACE_0 */
+
+
+/******************************************************************/
+
+/* Definitions for driver GPIOPS */
+#define XPAR_XGPIOPS_NUM_INSTANCES 1
+
+/* Definitions for peripheral PS7_GPIO_0 */
+#define XPAR_PS7_GPIO_0_DEVICE_ID 0
+#define XPAR_PS7_GPIO_0_BASEADDR 0xE000A000
+#define XPAR_PS7_GPIO_0_HIGHADDR 0xE000AFFF
+
+
+/******************************************************************/
+
+/* Canonical definitions for peripheral PS7_GPIO_0 */
+#define XPAR_XGPIOPS_0_DEVICE_ID XPAR_PS7_GPIO_0_DEVICE_ID
+#define XPAR_XGPIOPS_0_BASEADDR 0xE000A000
+#define XPAR_XGPIOPS_0_HIGHADDR 0xE000AFFF
+
+
+/******************************************************************/
+
+/* Definitions for driver QSPIPS */
+#define XPAR_XQSPIPS_NUM_INSTANCES 1
+
+/* Definitions for peripheral PS7_QSPI_0 */
+#define XPAR_PS7_QSPI_0_DEVICE_ID 0
+#define XPAR_PS7_QSPI_0_BASEADDR 0xE000D000
+#define XPAR_PS7_QSPI_0_HIGHADDR 0xE000DFFF
+#define XPAR_PS7_QSPI_0_QSPI_CLK_FREQ_HZ 200000000
+#define XPAR_PS7_QSPI_0_QSPI_MODE 0
+#define XPAR_PS7_QSPI_0_QSPI_BUS_WIDTH 2
+
+
+/******************************************************************/
+
+/* Canonical definitions for peripheral PS7_QSPI_0 */
+#define XPAR_XQSPIPS_0_DEVICE_ID XPAR_PS7_QSPI_0_DEVICE_ID
+#define XPAR_XQSPIPS_0_BASEADDR 0xE000D000
+#define XPAR_XQSPIPS_0_HIGHADDR 0xE000DFFF
+#define XPAR_XQSPIPS_0_QSPI_CLK_FREQ_HZ 200000000
+#define XPAR_XQSPIPS_0_QSPI_MODE 0
+#define XPAR_XQSPIPS_0_QSPI_BUS_WIDTH 2
+
+
+/******************************************************************/
+
+/* Definitions for driver SCUGIC */
+#define XPAR_XSCUGIC_NUM_INSTANCES 1U
+
+/* Definitions for peripheral PS7_SCUGIC_0 */
+#define XPAR_PS7_SCUGIC_0_DEVICE_ID 0U
+#define XPAR_PS7_SCUGIC_0_BASEADDR 0xF8F00100U
+#define XPAR_PS7_SCUGIC_0_HIGHADDR 0xF8F001FFU
+#define XPAR_PS7_SCUGIC_0_DIST_BASEADDR 0xF8F01000U
+
+
+/******************************************************************/
+
+/* Canonical definitions for peripheral PS7_SCUGIC_0 */
+#define XPAR_SCUGIC_0_DEVICE_ID 0U
+#define XPAR_SCUGIC_0_CPU_BASEADDR 0xF8F00100U
+#define XPAR_SCUGIC_0_CPU_HIGHADDR 0xF8F001FFU
+#define XPAR_SCUGIC_0_DIST_BASEADDR 0xF8F01000U
+
+
+/******************************************************************/
+
+/* Definitions for driver SCUTIMER */
+#define XPAR_XSCUTIMER_NUM_INSTANCES 1
+
+/* Definitions for peripheral PS7_SCUTIMER_0 */
+#define XPAR_PS7_SCUTIMER_0_DEVICE_ID 0
+#define XPAR_PS7_SCUTIMER_0_BASEADDR 0xF8F00600
+#define XPAR_PS7_SCUTIMER_0_HIGHADDR 0xF8F0061F
+
+
+/******************************************************************/
+
+/* Canonical definitions for peripheral PS7_SCUTIMER_0 */
+#define XPAR_XSCUTIMER_0_DEVICE_ID XPAR_PS7_SCUTIMER_0_DEVICE_ID
+#define XPAR_XSCUTIMER_0_BASEADDR 0xF8F00600
+#define XPAR_XSCUTIMER_0_HIGHADDR 0xF8F0061F
+
+
+/******************************************************************/
+
+/* Definitions for driver SCUWDT */
+#define XPAR_XSCUWDT_NUM_INSTANCES 1
+
+/* Definitions for peripheral PS7_SCUWDT_0 */
+#define XPAR_PS7_SCUWDT_0_DEVICE_ID 0
+#define XPAR_PS7_SCUWDT_0_BASEADDR 0xF8F00620
+#define XPAR_PS7_SCUWDT_0_HIGHADDR 0xF8F006FF
+
+
+/******************************************************************/
+
+/* Canonical definitions for peripheral PS7_SCUWDT_0 */
+#define XPAR_SCUWDT_0_DEVICE_ID XPAR_PS7_SCUWDT_0_DEVICE_ID
+#define XPAR_SCUWDT_0_BASEADDR 0xF8F00620
+#define XPAR_SCUWDT_0_HIGHADDR 0xF8F006FF
+
+
+/******************************************************************/
+
+/* Definitions for driver SDPS */
+#define XPAR_XSDPS_NUM_INSTANCES 1
+
+/* Definitions for peripheral PS7_SD_0 */
+#define XPAR_PS7_SD_0_DEVICE_ID 0
+#define XPAR_PS7_SD_0_BASEADDR 0xE0100000
+#define XPAR_PS7_SD_0_HIGHADDR 0xE0100FFF
+#define XPAR_PS7_SD_0_SDIO_CLK_FREQ_HZ 50000000
+#define XPAR_PS7_SD_0_HAS_CD 1
+#define XPAR_PS7_SD_0_HAS_WP 1
+#define XPAR_PS7_SD_0_BUS_WIDTH 0
+#define XPAR_PS7_SD_0_MIO_BANK 0
+#define XPAR_PS7_SD_0_HAS_EMIO 0
+
+
+/******************************************************************/
+
+#define XPAR_PS7_SD_0_IS_CACHE_COHERENT 0
+/* Canonical definitions for peripheral PS7_SD_0 */
+#define XPAR_XSDPS_0_DEVICE_ID XPAR_PS7_SD_0_DEVICE_ID
+#define XPAR_XSDPS_0_BASEADDR 0xE0100000
+#define XPAR_XSDPS_0_HIGHADDR 0xE0100FFF
+#define XPAR_XSDPS_0_SDIO_CLK_FREQ_HZ 50000000
+#define XPAR_XSDPS_0_HAS_CD 1
+#define XPAR_XSDPS_0_HAS_WP 1
+#define XPAR_XSDPS_0_BUS_WIDTH 0
+#define XPAR_XSDPS_0_MIO_BANK 0
+#define XPAR_XSDPS_0_HAS_EMIO 0
+#define XPAR_XSDPS_0_IS_CACHE_COHERENT 0
+
+
+/******************************************************************/
+
+/* Definitions for driver TTCPS */
+#define XPAR_XTTCPS_NUM_INSTANCES 3U
+
+/* Definitions for peripheral PS7_TTC_0 */
+#define XPAR_PS7_TTC_0_DEVICE_ID 0U
+#define XPAR_PS7_TTC_0_BASEADDR 0XF8001000U
+#define XPAR_PS7_TTC_0_TTC_CLK_FREQ_HZ 108333336U
+#define XPAR_PS7_TTC_0_TTC_CLK_CLKSRC 0U
+#define XPAR_PS7_TTC_1_DEVICE_ID 1U
+#define XPAR_PS7_TTC_1_BASEADDR 0XF8001004U
+#define XPAR_PS7_TTC_1_TTC_CLK_FREQ_HZ 108333336U
+#define XPAR_PS7_TTC_1_TTC_CLK_CLKSRC 0U
+#define XPAR_PS7_TTC_2_DEVICE_ID 2U
+#define XPAR_PS7_TTC_2_BASEADDR 0XF8001008U
+#define XPAR_PS7_TTC_2_TTC_CLK_FREQ_HZ 108333336U
+#define XPAR_PS7_TTC_2_TTC_CLK_CLKSRC 0U
+
+
+/******************************************************************/
+
+/* Canonical definitions for peripheral PS7_TTC_0 */
+#define XPAR_XTTCPS_0_DEVICE_ID XPAR_PS7_TTC_0_DEVICE_ID
+#define XPAR_XTTCPS_0_BASEADDR 0xF8001000U
+#define XPAR_XTTCPS_0_TTC_CLK_FREQ_HZ 108333336U
+#define XPAR_XTTCPS_0_TTC_CLK_CLKSRC 0U
+
+#define XPAR_XTTCPS_1_DEVICE_ID XPAR_PS7_TTC_1_DEVICE_ID
+#define XPAR_XTTCPS_1_BASEADDR 0xF8001004U
+#define XPAR_XTTCPS_1_TTC_CLK_FREQ_HZ 108333336U
+#define XPAR_XTTCPS_1_TTC_CLK_CLKSRC 0U
+
+#define XPAR_XTTCPS_2_DEVICE_ID XPAR_PS7_TTC_2_DEVICE_ID
+#define XPAR_XTTCPS_2_BASEADDR 0xF8001008U
+#define XPAR_XTTCPS_2_TTC_CLK_FREQ_HZ 108333336U
+#define XPAR_XTTCPS_2_TTC_CLK_CLKSRC 0U
+
+
+/******************************************************************/
+
+/* Definitions for driver UARTPS */
+#define XPAR_XUARTPS_NUM_INSTANCES 1
+
+/* Definitions for peripheral PS7_UART_1 */
+#define XPAR_PS7_UART_1_DEVICE_ID 0
+#define XPAR_PS7_UART_1_BASEADDR 0xE0001000
+#define XPAR_PS7_UART_1_HIGHADDR 0xE0001FFF
+#define XPAR_PS7_UART_1_UART_CLK_FREQ_HZ 100000000
+#define XPAR_PS7_UART_1_HAS_MODEM 0
+
+
+/******************************************************************/
+
+/* Canonical definitions for peripheral PS7_UART_1 */
+#define XPAR_XUARTPS_0_DEVICE_ID XPAR_PS7_UART_1_DEVICE_ID
+#define XPAR_XUARTPS_0_BASEADDR 0xE0001000
+#define XPAR_XUARTPS_0_HIGHADDR 0xE0001FFF
+#define XPAR_XUARTPS_0_UART_CLK_FREQ_HZ 100000000
+#define XPAR_XUARTPS_0_HAS_MODEM 0
+
+
+/******************************************************************/
+
+/* Definitions for driver USBPS */
+#define XPAR_XUSBPS_NUM_INSTANCES 1
+
+/* Definitions for peripheral PS7_USB_0 */
+#define XPAR_PS7_USB_0_DEVICE_ID 0
+#define XPAR_PS7_USB_0_BASEADDR 0xE0002000
+#define XPAR_PS7_USB_0_HIGHADDR 0xE0002FFF
+
+
+/******************************************************************/
+
+/* Canonical definitions for peripheral PS7_USB_0 */
+#define XPAR_XUSBPS_0_DEVICE_ID XPAR_PS7_USB_0_DEVICE_ID
+#define XPAR_XUSBPS_0_BASEADDR 0xE0002000
+#define XPAR_XUSBPS_0_HIGHADDR 0xE0002FFF
+
+
+/******************************************************************/
+
+/* Definitions for driver XADCPS */
+#define XPAR_XADCPS_NUM_INSTANCES 1
+
+/* Definitions for peripheral PS7_XADC_0 */
+#define XPAR_PS7_XADC_0_DEVICE_ID 0
+#define XPAR_PS7_XADC_0_BASEADDR 0xF8007100
+#define XPAR_PS7_XADC_0_HIGHADDR 0xF8007120
+
+
+/******************************************************************/
+
+/* Canonical definitions for peripheral PS7_XADC_0 */
+#define XPAR_XADCPS_0_DEVICE_ID XPAR_PS7_XADC_0_DEVICE_ID
+#define XPAR_XADCPS_0_BASEADDR 0xF8007100
+#define XPAR_XADCPS_0_HIGHADDR 0xF8007120
+
+
+/******************************************************************/
+
+/* Xilinx FAT File System Library (XilFFs) User Settings */
+#define FILE_SYSTEM_INTERFACE_SD
+#define FILE_SYSTEM_USE_MKFS
+#define FILE_SYSTEM_NUM_LOGIC_VOL 2
+#define FILE_SYSTEM_USE_STRFUNC 0
+#define FILE_SYSTEM_SET_FS_RPATH 0
+#define FILE_SYSTEM_WORD_ACCESS
+#endif /* end of protection macro */
diff --git a/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/include/xparameters_ps.h b/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/include/xparameters_ps.h
new file mode 100644
index 0000000..4d35859
--- /dev/null
+++ b/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/include/xparameters_ps.h
@@ -0,0 +1,332 @@
+/******************************************************************************
+*
+* Copyright (C) 2010 - 2017 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+* THE SOFTWARE.
+*
+*
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+* @file xparameters_ps.h
+*
+* This file contains the address definitions for the hard peripherals
+* attached to the ARM Cortex A9 core.
+*
+* <pre>
+* MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ----- ------- -------- ---------------------------------------------------
+* 1.00a ecm/sdm 02/01/10 Initial version
+* 3.04a sdm 02/02/12 Removed some of the defines as they are being generated through
+* driver tcl
+* 5.0 pkp 01/16/15 Added interrupt ID definition of ttc for TEST APP
+* 6.6 srm 10/18/17 Added ARMA9 macro to identify CortexA9
+*
+* </pre>
+*
+* @note
+*
+* None.
+*
+******************************************************************************/
+
+#ifndef _XPARAMETERS_PS_H_
+#define _XPARAMETERS_PS_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**************************** Include Files *******************************/
+
+
+/************************** Constant Definitions *****************************/
+
+/*
+ * This block contains constant declarations for the peripherals
+ * within the hardblock
+ */
+
+/* Canonical definitions for DDR MEMORY */
+#define XPAR_DDR_MEM_BASEADDR 0x00000000U
+#define XPAR_DDR_MEM_HIGHADDR 0x3FFFFFFFU
+
+/* Canonical definitions for Interrupts */
+#define XPAR_XUARTPS_0_INTR XPS_UART0_INT_ID
+#define XPAR_XUARTPS_1_INTR XPS_UART1_INT_ID
+#define XPAR_XUSBPS_0_INTR XPS_USB0_INT_ID
+#define XPAR_XUSBPS_1_INTR XPS_USB1_INT_ID
+#define XPAR_XIICPS_0_INTR XPS_I2C0_INT_ID
+#define XPAR_XIICPS_1_INTR XPS_I2C1_INT_ID
+#define XPAR_XSPIPS_0_INTR XPS_SPI0_INT_ID
+#define XPAR_XSPIPS_1_INTR XPS_SPI1_INT_ID
+#define XPAR_XCANPS_0_INTR XPS_CAN0_INT_ID
+#define XPAR_XCANPS_1_INTR XPS_CAN1_INT_ID
+#define XPAR_XGPIOPS_0_INTR XPS_GPIO_INT_ID
+#define XPAR_XEMACPS_0_INTR XPS_GEM0_INT_ID
+#define XPAR_XEMACPS_0_WAKE_INTR XPS_GEM0_WAKE_INT_ID
+#define XPAR_XEMACPS_1_INTR XPS_GEM1_INT_ID
+#define XPAR_XEMACPS_1_WAKE_INTR XPS_GEM1_WAKE_INT_ID
+#define XPAR_XSDIOPS_0_INTR XPS_SDIO0_INT_ID
+#define XPAR_XQSPIPS_0_INTR XPS_QSPI_INT_ID
+#define XPAR_XSDIOPS_1_INTR XPS_SDIO1_INT_ID
+#define XPAR_XWDTPS_0_INTR XPS_WDT_INT_ID
+#define XPAR_XDCFG_0_INTR XPS_DVC_INT_ID
+#define XPAR_SCUTIMER_INTR XPS_SCU_TMR_INT_ID
+#define XPAR_SCUWDT_INTR XPS_SCU_WDT_INT_ID
+#define XPAR_XTTCPS_0_INTR XPS_TTC0_0_INT_ID
+#define XPAR_XTTCPS_1_INTR XPS_TTC0_1_INT_ID
+#define XPAR_XTTCPS_2_INTR XPS_TTC0_2_INT_ID
+#define XPAR_XTTCPS_3_INTR XPS_TTC1_0_INT_ID
+#define XPAR_XTTCPS_4_INTR XPS_TTC1_1_INT_ID
+#define XPAR_XTTCPS_5_INTR XPS_TTC1_2_INT_ID
+#define XPAR_XDMAPS_0_FAULT_INTR XPS_DMA0_ABORT_INT_ID
+#define XPAR_XDMAPS_0_DONE_INTR_0 XPS_DMA0_INT_ID
+#define XPAR_XDMAPS_0_DONE_INTR_1 XPS_DMA1_INT_ID
+#define XPAR_XDMAPS_0_DONE_INTR_2 XPS_DMA2_INT_ID
+#define XPAR_XDMAPS_0_DONE_INTR_3 XPS_DMA3_INT_ID
+#define XPAR_XDMAPS_0_DONE_INTR_4 XPS_DMA4_INT_ID
+#define XPAR_XDMAPS_0_DONE_INTR_5 XPS_DMA5_INT_ID
+#define XPAR_XDMAPS_0_DONE_INTR_6 XPS_DMA6_INT_ID
+#define XPAR_XDMAPS_0_DONE_INTR_7 XPS_DMA7_INT_ID
+
+
+#define XPAR_XQSPIPS_0_LINEAR_BASEADDR XPS_QSPI_LINEAR_BASEADDR
+#define XPAR_XPARPORTPS_CTRL_BASEADDR XPS_PARPORT_CRTL_BASEADDR
+
+
+
+/* Canonical definitions for DMAC */
+
+
+/* Canonical definitions for WDT */
+
+/* Canonical definitions for SLCR */
+#define XPAR_XSLCR_NUM_INSTANCES 1U
+#define XPAR_XSLCR_0_DEVICE_ID 0U
+#define XPAR_XSLCR_0_BASEADDR XPS_SYS_CTRL_BASEADDR
+
+/* Canonical definitions for SCU GIC */
+#define XPAR_SCUGIC_NUM_INSTANCES 1U
+#define XPAR_SCUGIC_SINGLE_DEVICE_ID 0U
+#define XPAR_SCUGIC_CPU_BASEADDR (XPS_SCU_PERIPH_BASE + 0x00000100U)
+#define XPAR_SCUGIC_DIST_BASEADDR (XPS_SCU_PERIPH_BASE + 0x00001000U)
+#define XPAR_SCUGIC_ACK_BEFORE 0U
+
+/* Canonical definitions for Global Timer */
+#define XPAR_GLOBAL_TMR_NUM_INSTANCES 1U
+#define XPAR_GLOBAL_TMR_DEVICE_ID 0U
+#define XPAR_GLOBAL_TMR_BASEADDR (XPS_SCU_PERIPH_BASE + 0x00000200U)
+#define XPAR_GLOBAL_TMR_INTR XPS_GLOBAL_TMR_INT_ID
+
+
+/* Xilinx Parallel Flash Library (XilFlash) User Settings */
+#define XPAR_AXI_EMC
+
+
+#define XPAR_CPU_CORTEXA9_CORE_CLOCK_FREQ_HZ XPAR_CPU_CORTEXA9_0_CPU_CLK_FREQ_HZ
+
+
+/*
+ * This block contains constant declarations for the peripherals
+ * within the hardblock. These have been put for bacwards compatibility
+ */
+
+#define XPS_PERIPHERAL_BASEADDR 0xE0000000U
+#define XPS_UART0_BASEADDR 0xE0000000U
+#define XPS_UART1_BASEADDR 0xE0001000U
+#define XPS_USB0_BASEADDR 0xE0002000U
+#define XPS_USB1_BASEADDR 0xE0003000U
+#define XPS_I2C0_BASEADDR 0xE0004000U
+#define XPS_I2C1_BASEADDR 0xE0005000U
+#define XPS_SPI0_BASEADDR 0xE0006000U
+#define XPS_SPI1_BASEADDR 0xE0007000U
+#define XPS_CAN0_BASEADDR 0xE0008000U
+#define XPS_CAN1_BASEADDR 0xE0009000U
+#define XPS_GPIO_BASEADDR 0xE000A000U
+#define XPS_GEM0_BASEADDR 0xE000B000U
+#define XPS_GEM1_BASEADDR 0xE000C000U
+#define XPS_QSPI_BASEADDR 0xE000D000U
+#define XPS_PARPORT_CRTL_BASEADDR 0xE000E000U
+#define XPS_SDIO0_BASEADDR 0xE0100000U
+#define XPS_SDIO1_BASEADDR 0xE0101000U
+#define XPS_IOU_BUS_CFG_BASEADDR 0xE0200000U
+#define XPS_NAND_BASEADDR 0xE1000000U
+#define XPS_PARPORT0_BASEADDR 0xE2000000U
+#define XPS_PARPORT1_BASEADDR 0xE4000000U
+#define XPS_QSPI_LINEAR_BASEADDR 0xFC000000U
+#define XPS_SYS_CTRL_BASEADDR 0xF8000000U /* AKA SLCR */
+#define XPS_TTC0_BASEADDR 0xF8001000U
+#define XPS_TTC1_BASEADDR 0xF8002000U
+#define XPS_DMAC0_SEC_BASEADDR 0xF8003000U
+#define XPS_DMAC0_NON_SEC_BASEADDR 0xF8004000U
+#define XPS_WDT_BASEADDR 0xF8005000U
+#define XPS_DDR_CTRL_BASEADDR 0xF8006000U
+#define XPS_DEV_CFG_APB_BASEADDR 0xF8007000U
+#define XPS_AFI0_BASEADDR 0xF8008000U
+#define XPS_AFI1_BASEADDR 0xF8009000U
+#define XPS_AFI2_BASEADDR 0xF800A000U
+#define XPS_AFI3_BASEADDR 0xF800B000U
+#define XPS_OCM_BASEADDR 0xF800C000U
+#define XPS_EFUSE_BASEADDR 0xF800D000U
+#define XPS_CORESIGHT_BASEADDR 0xF8800000U
+#define XPS_TOP_BUS_CFG_BASEADDR 0xF8900000U
+#define XPS_SCU_PERIPH_BASE 0xF8F00000U
+#define XPS_L2CC_BASEADDR 0xF8F02000U
+#define XPS_SAM_RAM_BASEADDR 0xFFFC0000U
+#define XPS_FPGA_AXI_S0_BASEADDR 0x40000000U
+#define XPS_FPGA_AXI_S1_BASEADDR 0x80000000U
+#define XPS_IOU_S_SWITCH_BASEADDR 0xE0000000U
+#define XPS_PERIPH_APB_BASEADDR 0xF8000000U
+
+/* Shared Peripheral Interrupts (SPI) */
+#define XPS_CORE_PARITY0_INT_ID 32U
+#define XPS_CORE_PARITY1_INT_ID 33U
+#define XPS_L2CC_INT_ID 34U
+#define XPS_OCMINTR_INT_ID 35U
+#define XPS_ECC_INT_ID 36U
+#define XPS_PMU0_INT_ID 37U
+#define XPS_PMU1_INT_ID 38U
+#define XPS_SYSMON_INT_ID 39U
+#define XPS_DVC_INT_ID 40U
+#define XPS_WDT_INT_ID 41U
+#define XPS_TTC0_0_INT_ID 42U
+#define XPS_TTC0_1_INT_ID 43U
+#define XPS_TTC0_2_INT_ID 44U
+#define XPS_DMA0_ABORT_INT_ID 45U
+#define XPS_DMA0_INT_ID 46U
+#define XPS_DMA1_INT_ID 47U
+#define XPS_DMA2_INT_ID 48U
+#define XPS_DMA3_INT_ID 49U
+#define XPS_SMC_INT_ID 50U
+#define XPS_QSPI_INT_ID 51U
+#define XPS_GPIO_INT_ID 52U
+#define XPS_USB0_INT_ID 53U
+#define XPS_GEM0_INT_ID 54U
+#define XPS_GEM0_WAKE_INT_ID 55U
+#define XPS_SDIO0_INT_ID 56U
+#define XPS_I2C0_INT_ID 57U
+#define XPS_SPI0_INT_ID 58U
+#define XPS_UART0_INT_ID 59U
+#define XPS_CAN0_INT_ID 60U
+#define XPS_FPGA0_INT_ID 61U
+#define XPS_FPGA1_INT_ID 62U
+#define XPS_FPGA2_INT_ID 63U
+#define XPS_FPGA3_INT_ID 64U
+#define XPS_FPGA4_INT_ID 65U
+#define XPS_FPGA5_INT_ID 66U
+#define XPS_FPGA6_INT_ID 67U
+#define XPS_FPGA7_INT_ID 68U
+#define XPS_TTC1_0_INT_ID 69U
+#define XPS_TTC1_1_INT_ID 70U
+#define XPS_TTC1_2_INT_ID 71U
+#define XPS_DMA4_INT_ID 72U
+#define XPS_DMA5_INT_ID 73U
+#define XPS_DMA6_INT_ID 74U
+#define XPS_DMA7_INT_ID 75U
+#define XPS_USB1_INT_ID 76U
+#define XPS_GEM1_INT_ID 77U
+#define XPS_GEM1_WAKE_INT_ID 78U
+#define XPS_SDIO1_INT_ID 79U
+#define XPS_I2C1_INT_ID 80U
+#define XPS_SPI1_INT_ID 81U
+#define XPS_UART1_INT_ID 82U
+#define XPS_CAN1_INT_ID 83U
+#define XPS_FPGA8_INT_ID 84U
+#define XPS_FPGA9_INT_ID 85U
+#define XPS_FPGA10_INT_ID 86U
+#define XPS_FPGA11_INT_ID 87U
+#define XPS_FPGA12_INT_ID 88U
+#define XPS_FPGA13_INT_ID 89U
+#define XPS_FPGA14_INT_ID 90U
+#define XPS_FPGA15_INT_ID 91U
+
+/* Private Peripheral Interrupts (PPI) */
+#define XPS_GLOBAL_TMR_INT_ID 27U /* SCU Global Timer interrupt */
+#define XPS_FIQ_INT_ID 28U /* FIQ from FPGA fabric */
+#define XPS_SCU_TMR_INT_ID 29U /* SCU Private Timer interrupt */
+#define XPS_SCU_WDT_INT_ID 30U /* SCU Private WDT interrupt */
+#define XPS_IRQ_INT_ID 31U /* IRQ from FPGA fabric */
+
+
+/* REDEFINES for TEST APP */
+/* Definitions for UART */
+#define XPAR_PS7_UART_0_INTR XPS_UART0_INT_ID
+#define XPAR_PS7_UART_1_INTR XPS_UART1_INT_ID
+#define XPAR_PS7_USB_0_INTR XPS_USB0_INT_ID
+#define XPAR_PS7_USB_1_INTR XPS_USB1_INT_ID
+#define XPAR_PS7_I2C_0_INTR XPS_I2C0_INT_ID
+#define XPAR_PS7_I2C_1_INTR XPS_I2C1_INT_ID
+#define XPAR_PS7_SPI_0_INTR XPS_SPI0_INT_ID
+#define XPAR_PS7_SPI_1_INTR XPS_SPI1_INT_ID
+#define XPAR_PS7_CAN_0_INTR XPS_CAN0_INT_ID
+#define XPAR_PS7_CAN_1_INTR XPS_CAN1_INT_ID
+#define XPAR_PS7_GPIO_0_INTR XPS_GPIO_INT_ID
+#define XPAR_PS7_ETHERNET_0_INTR XPS_GEM0_INT_ID
+#define XPAR_PS7_ETHERNET_0_WAKE_INTR XPS_GEM0_WAKE_INT_ID
+#define XPAR_PS7_ETHERNET_1_INTR XPS_GEM1_INT_ID
+#define XPAR_PS7_ETHERNET_1_WAKE_INTR XPS_GEM1_WAKE_INT_ID
+#define XPAR_PS7_QSPI_0_INTR XPS_QSPI_INT_ID
+#define XPAR_PS7_WDT_0_INTR XPS_WDT_INT_ID
+#define XPAR_PS7_SCUWDT_0_INTR XPS_SCU_WDT_INT_ID
+#define XPAR_PS7_SCUTIMER_0_INTR XPS_SCU_TMR_INT_ID
+#define XPAR_PS7_XADC_0_INTR XPS_SYSMON_INT_ID
+#define XPAR_PS7_TTC_0_INTR XPS_TTC0_0_INT_ID
+#define XPAR_PS7_TTC_1_INTR XPS_TTC0_1_INT_ID
+#define XPAR_PS7_TTC_2_INTR XPS_TTC0_2_INT_ID
+#define XPAR_PS7_TTC_3_INTR XPS_TTC1_0_INT_ID
+#define XPAR_PS7_TTC_4_INTR XPS_TTC1_1_INT_ID
+#define XPAR_PS7_TTC_5_INTR XPS_TTC1_2_INT_ID
+
+#define XPAR_XADCPS_INT_ID XPS_SYSMON_INT_ID
+
+/* For backwards compatibility */
+#define XPAR_XUARTPS_0_CLOCK_HZ XPAR_XUARTPS_0_UART_CLK_FREQ_HZ
+#define XPAR_XUARTPS_1_CLOCK_HZ XPAR_XUARTPS_1_UART_CLK_FREQ_HZ
+#define XPAR_XTTCPS_0_CLOCK_HZ XPAR_XTTCPS_0_TTC_CLK_FREQ_HZ
+#define XPAR_XTTCPS_1_CLOCK_HZ XPAR_XTTCPS_1_TTC_CLK_FREQ_HZ
+#define XPAR_XTTCPS_2_CLOCK_HZ XPAR_XTTCPS_2_TTC_CLK_FREQ_HZ
+#define XPAR_XTTCPS_3_CLOCK_HZ XPAR_XTTCPS_3_TTC_CLK_FREQ_HZ
+#define XPAR_XTTCPS_4_CLOCK_HZ XPAR_XTTCPS_4_TTC_CLK_FREQ_HZ
+#define XPAR_XTTCPS_5_CLOCK_HZ XPAR_XTTCPS_5_TTC_CLK_FREQ_HZ
+#define XPAR_XIICPS_0_CLOCK_HZ XPAR_XIICPS_0_I2C_CLK_FREQ_HZ
+#define XPAR_XIICPS_1_CLOCK_HZ XPAR_XIICPS_1_I2C_CLK_FREQ_HZ
+
+#define XPAR_XQSPIPS_0_CLOCK_HZ XPAR_XQSPIPS_0_QSPI_CLK_FREQ_HZ
+
+#ifdef XPAR_CPU_CORTEXA9_0_CPU_CLK_FREQ_HZ
+#define XPAR_CPU_CORTEXA9_CORE_CLOCK_FREQ_HZ XPAR_CPU_CORTEXA9_0_CPU_CLK_FREQ_HZ
+#endif
+
+#ifdef XPAR_CPU_CORTEXA9_1_CPU_CLK_FREQ_HZ
+#define XPAR_CPU_CORTEXA9_CORE_CLOCK_FREQ_HZ XPAR_CPU_CORTEXA9_1_CPU_CLK_FREQ_HZ
+#endif
+
+#define XPAR_SCUTIMER_DEVICE_ID 0U
+#define XPAR_SCUWDT_DEVICE_ID 0U
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* protection macro */
diff --git a/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/include/xplatform_info.h b/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/include/xplatform_info.h
new file mode 100644
index 0000000..a917354
--- /dev/null
+++ b/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/include/xplatform_info.h
@@ -0,0 +1,118 @@
+/******************************************************************************
+*
+* Copyright (C) 2014 - 2017 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+* THE SOFTWARE.
+*
+*
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xplatform_info.h
+*
+* @addtogroup common_platform_info APIs to Get Platform Information
+*
+* The xplatform_info.h file contains definitions for various available Xilinx®
+* platforms. Also, it contains prototype of APIs, which can be used to get the
+* platform information.
+*
+* @{
+* <pre>
+* MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ----- ---- --------- -------------------------------------------------------
+* 6.4 ms 05/23/17 Added PSU_PMU macro to support XGetPSVersion_Info
+* function for PMUFW.
+* </pre>
+*
+******************************************************************************/
+
+#ifndef XPLATFORM_INFO_H /* prevent circular inclusions */
+#define XPLATFORM_INFO_H /* by using protection macros */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/***************************** Include Files *********************************/
+
+#include "xil_types.h"
+
+/************************** Constant Definitions *****************************/
+#if defined (versal)
+#define XPAR_PMC_TAP_BASEADDR 0xF11A0000U
+#define XPAR_PMC_TAP_VERSION_OFFSET 0x00000004U
+#define XPLAT_PS_VERSION_ADDRESS (XPAR_PMC_TAP_BASEADDR + \
+ XPAR_PMC_TAP_VERSION_OFFSET)
+#else
+#define XPAR_CSU_BASEADDR 0xFFCA0000U
+#define XPAR_CSU_VER_OFFSET 0x00000044U
+#define XPLAT_PS_VERSION_ADDRESS (XPAR_CSU_BASEADDR + \
+ XPAR_CSU_VER_OFFSET)
+#endif
+#define XPLAT_ZYNQ_ULTRA_MP_SILICON 0x0
+#define XPLAT_ZYNQ_ULTRA_MP 0x1
+#define XPLAT_ZYNQ_ULTRA_MPVEL 0x2
+#define XPLAT_ZYNQ_ULTRA_MPQEMU 0x3
+#define XPLAT_ZYNQ 0x4
+#define XPLAT_MICROBLAZE 0x5
+#define XPLAT_VERSAL 0x6U
+
+#define XPS_VERSION_1 0x0
+#define XPS_VERSION_2 0x1
+#define XPLAT_INFO_MASK (0xF)
+
+#if defined (versal)
+#define XPS_VERSION_INFO_MASK 0xFF00U
+#define XPS_VERSION_INFO_SHIFT 0x8U
+#define XPLAT_INFO_SHIFT 0x18U
+#else
+#define XPS_VERSION_INFO_MASK (0xF)
+#define XPS_VERSION_INFO_SHIFT 0x0U
+#define XPLAT_INFO_SHIFT 0xCU
+#endif
+
+/**************************** Type Definitions *******************************/
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+
+u32 XGetPlatform_Info(void);
+
+#if defined (ARMR5) || (__aarch64__) || (ARMA53_32) || (PSU_PMU)
+u32 XGetPSVersion_Info();
+#endif
+
+#if defined (ARMR5) || (__aarch64__) || (ARMA53_32)
+u32 XGet_Zynq_UltraMp_Platform_info();
+#endif
+/************************** Function Prototypes ******************************/
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* end of protection macro */
+/**
+* @} End of "addtogroup common_platform_info".
+*/
diff --git a/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/include/xpm_counter.h b/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/include/xpm_counter.h
new file mode 100644
index 0000000..1288952
--- /dev/null
+++ b/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/include/xpm_counter.h
@@ -0,0 +1,570 @@
+/******************************************************************************
+*
+* Copyright (C) 2011 - 2018 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+* THE SOFTWARE.
+*
+*
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xpm_counter.h
+*
+* @addtogroup a9_event_counter_apis Cortex A9 Event Counters Functions
+*
+* Cortex A9 event counter functions can be utilized to configure and control
+* the Cortex-A9 performance monitor events.
+*
+* Cortex-A9 performance monitor has six event counters which can be used to
+* count a variety of events described in Coretx-A9 TRM. xpm_counter.h defines
+* configurations XPM_CNTRCFGx which can be used to program the event counters
+* to count a set of events.
+*
+* @note
+* It doesn't handle the Cortex-A9 cycle counter, as the cycle counter is
+* being used for time keeping.
+*
+* @{
+*
+* <pre>
+* MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ----- ---- -------- -----------------------------------------------
+* 1.00a sdm 07/11/11 First release
+* 6.8 aru 09/06/18 Removed compilation warnings for ARMCC toolchain.
+* </pre>
+*
+******************************************************************************/
+
+#ifndef XPMCOUNTER_H /* prevent circular inclusions */
+#define XPMCOUNTER_H /* by using protection macros */
+
+/***************************** Include Files ********************************/
+
+#include <stdint.h>
+#include "xpseudo_asm.h"
+#include "xil_types.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif /* __cplusplus */
+
+/************************** Constant Definitions ****************************/
+
+/* Number of performance counters */
+#define XPM_CTRCOUNT 6U
+
+/* The following constants define the Cortex-A9 Performance Monitor Events */
+
+/*
+ * Software increment. The register is incremented only on writes to the
+ * Software Increment Register
+ */
+#define XPM_EVENT_SOFTINCR 0x00U
+
+/*
+ * Instruction fetch that causes a refill at (at least) the lowest level(s) of
+ * instruction or unified cache. Includes the speculative linefills in the
+ * count
+ */
+#define XPM_EVENT_INSRFETCH_CACHEREFILL 0x01U
+
+/*
+ * Instruction fetch that causes a TLB refill at (at least) the lowest level of
+ * TLB. Includes the speculative requests in the count
+ */
+#define XPM_EVENT_INSTRFECT_TLBREFILL 0x02U
+
+/*
+ * Data read or write operation that causes a refill at (at least) the lowest
+ * level(s)of data or unified cache. Counts the number of allocations performed
+ * in the Data Cache due to a read or a write
+ */
+#define XPM_EVENT_DATA_CACHEREFILL 0x03U
+
+/*
+ * Data read or write operation that causes a cache access at (at least) the
+ * lowest level(s) of data or unified cache. This includes speculative reads
+ */
+#define XPM_EVENT_DATA_CACHEACCESS 0x04U
+
+/*
+ * Data read or write operation that causes a TLB refill at (at least) the
+ * lowest level of TLB. This does not include micro TLB misses due to PLD, PLI,
+ * CP15 Cache operation by MVA and CP15 VA to PA operations
+ */
+#define XPM_EVENT_DATA_TLBREFILL 0x05U
+
+/*
+ * Data read architecturally executed. Counts the number of data read
+ * instructions accepted by the Load Store Unit. This includes counting the
+ * speculative and aborted LDR/LDM, as well as the reads due to the SWP
+ * instructions
+ */
+#define XPM_EVENT_DATA_READS 0x06U
+
+/*
+ * Data write architecturally executed. Counts the number of data write
+ * instructions accepted by the Load Store Unit. This includes counting the
+ * speculative and aborted STR/STM, as well as the writes due to the SWP
+ * instructions
+ */
+#define XPM_EVENT_DATA_WRITE 0x07U
+
+/* Exception taken. Counts the number of exceptions architecturally taken.*/
+#define XPM_EVENT_EXCEPTION 0x09U
+
+/* Exception return architecturally executed.*/
+#define XPM_EVENT_EXCEPRETURN 0x0AU
+
+/*
+ * Change to ContextID retired. Counts the number of instructions
+ * architecturally executed writing into the ContextID Register
+ */
+#define XPM_EVENT_CHANGECONTEXT 0x0BU
+
+/*
+ * Software change of PC, except by an exception, architecturally executed.
+ * Count the number of PC changes architecturally executed, excluding the PC
+ * changes due to taken exceptions
+ */
+#define XPM_EVENT_SW_CHANGEPC 0x0CU
+
+/*
+ * Immediate branch architecturally executed (taken or not taken). This includes
+ * the branches which are flushed due to a previous load/store which aborts
+ * late
+ */
+#define XPM_EVENT_IMMEDBRANCH 0x0DU
+
+/*
+ * Unaligned access architecturally executed. Counts the number of aborted
+ * unaligned accessed architecturally executed, and the number of not-aborted
+ * unaligned accesses, including the speculative ones
+ */
+#define XPM_EVENT_UNALIGNEDACCESS 0x0FU
+
+/*
+ * Branch mispredicted/not predicted. Counts the number of mispredicted or
+ * not-predicted branches executed. This includes the branches which are flushed
+ * due to a previous load/store which aborts late
+ */
+#define XPM_EVENT_BRANCHMISS 0x10U
+
+/*
+ * Counts clock cycles when the Cortex-A9 processor is not in WFE/WFI. This
+ * event is not exported on the PMUEVENT bus
+ */
+#define XPM_EVENT_CLOCKCYCLES 0x11U
+
+/*
+ * Branches or other change in program flow that could have been predicted by
+ * the branch prediction resources of the processor. This includes the branches
+ * which are flushed due to a previous load/store which aborts late
+ */
+#define XPM_EVENT_BRANCHPREDICT 0x12U
+
+/*
+ * Java bytecode execute. Counts the number of Java bytecodes being decoded,
+ * including speculative ones
+ */
+#define XPM_EVENT_JAVABYTECODE 0x40U
+
+/*
+ * Software Java bytecode executed. Counts the number of software java bytecodes
+ * being decoded, including speculative ones
+ */
+#define XPM_EVENT_SWJAVABYTECODE 0x41U
+
+/*
+ * Jazelle backward branches executed. Counts the number of Jazelle taken
+ * branches being executed. This includes the branches which are flushed due
+ * to a previous load/store which aborts late
+ */
+#define XPM_EVENT_JAVABACKBRANCH 0x42U
+
+/*
+ * Coherent linefill miss Counts the number of coherent linefill requests
+ * performed by the Cortex-A9 processor which also miss in all the other
+ * Cortex-A9 processors, meaning that the request is sent to the external
+ * memory
+ */
+#define XPM_EVENT_COHERLINEMISS 0x50U
+
+/*
+ * Coherent linefill hit. Counts the number of coherent linefill requests
+ * performed by the Cortex-A9 processor which hit in another Cortex-A9
+ * processor, meaning that the linefill data is fetched directly from the
+ * relevant Cortex-A9 cache
+ */
+#define XPM_EVENT_COHERLINEHIT 0x51U
+
+/*
+ * Instruction cache dependent stall cycles. Counts the number of cycles where
+ * the processor is ready to accept new instructions, but does not receive any
+ * due to the instruction side not being able to provide any and the
+ * instruction cache is currently performing at least one linefill
+ */
+#define XPM_EVENT_INSTRSTALL 0x60U
+
+/*
+ * Data cache dependent stall cycles. Counts the number of cycles where the core
+ * has some instructions that it cannot issue to any pipeline, and the Load
+ * Store unit has at least one pending linefill request, and no pending
+ */
+#define XPM_EVENT_DATASTALL 0x61U
+
+/*
+ * Main TLB miss stall cycles. Counts the number of cycles where the processor
+ * is stalled waiting for the completion of translation table walks from the
+ * main TLB. The processor stalls can be due to the instruction side not being
+ * able to provide the instructions, or to the data side not being able to
+ * provide the necessary data, due to them waiting for the main TLB translation
+ * table walk to complete
+ */
+#define XPM_EVENT_MAINTLBSTALL 0x62U
+
+/*
+ * Counts the number of STREX instructions architecturally executed and
+ * passed
+ */
+#define XPM_EVENT_STREXPASS 0x63U
+
+/*
+ * Counts the number of STREX instructions architecturally executed and
+ * failed
+ */
+#define XPM_EVENT_STREXFAIL 0x64U
+
+/*
+ * Data eviction. Counts the number of eviction requests due to a linefill in
+ * the data cache
+ */
+#define XPM_EVENT_DATAEVICT 0x65U
+
+/*
+ * Counts the number of cycles where the issue stage does not dispatch any
+ * instruction because it is empty or cannot dispatch any instructions
+ */
+#define XPM_EVENT_NODISPATCH 0x66U
+
+/*
+ * Counts the number of cycles where the issue stage is empty
+ */
+#define XPM_EVENT_ISSUEEMPTY 0x67U
+
+/*
+ * Counts the number of instructions going through the Register Renaming stage.
+ * This number is an approximate number of the total number of instructions
+ * speculatively executed, and even more approximate of the total number of
+ * instructions architecturally executed. The approximation depends mainly on
+ * the branch misprediction rate.
+ * The renaming stage can handle two instructions in the same cycle so the event
+ * is two bits long:
+ * - b00 no instructions renamed
+ * - b01 one instruction renamed
+ * - b10 two instructions renamed
+ */
+#define XPM_EVENT_INSTRRENAME 0x68U
+
+/*
+ * Counts the number of procedure returns whose condition codes do not fail,
+ * excluding all returns from exception. This count includes procedure returns
+ * which are flushed due to a previous load/store which aborts late.
+ * Only the following instructions are reported:
+ * - BX R14
+ * - MOV PC LR
+ * - POP {..,pc}
+ * - LDR pc,[sp],#offset
+ * The following instructions are not reported:
+ * - LDMIA R9!,{..,PC} (ThumbEE state only)
+ * - LDR PC,[R9],#offset (ThumbEE state only)
+ * - BX R0 (Rm != R14)
+ * - MOV PC,R0 (Rm != R14)
+ * - LDM SP,{...,PC} (writeback not specified)
+ * - LDR PC,[SP,#offset] (wrong addressing mode)
+ */
+#define XPM_EVENT_PREDICTFUNCRET 0x6EU
+
+/*
+ * Counts the number of instructions being executed in the main execution
+ * pipeline of the processor, the multiply pipeline and arithmetic logic unit
+ * pipeline. The counted instructions are still speculative
+ */
+#define XPM_EVENT_MAINEXEC 0x70U
+
+/*
+ * Counts the number of instructions being executed in the processor second
+ * execution pipeline (ALU). The counted instructions are still speculative
+ */
+#define XPM_EVENT_SECEXEC 0x71U
+
+/*
+ * Counts the number of instructions being executed in the Load/Store unit. The
+ * counted instructions are still speculative
+ */
+#define XPM_EVENT_LDRSTR 0x72U
+
+/*
+ * Counts the number of Floating-point instructions going through the Register
+ * Rename stage. Instructions are still speculative in this stage.
+ *Two floating-point instructions can be renamed in the same cycle so the event
+ * is two bitslong:
+ *0b00 no floating-point instruction renamed
+ *0b01 one floating-point instruction renamed
+ *0b10 two floating-point instructions renamed
+ */
+#define XPM_EVENT_FLOATRENAME 0x73U
+
+/*
+ * Counts the number of Neon instructions going through the Register Rename
+ * stage.Instructions are still speculative in this stage.
+ * Two NEON instructions can be renamed in the same cycle so the event is two
+ * bits long:
+ *0b00 no NEON instruction renamed
+ *0b01 one NEON instruction renamed
+ *0b10 two NEON instructions renamed
+ */
+#define XPM_EVENT_NEONRENAME 0x74U
+
+/*
+ * Counts the number of cycles where the processor is stalled because PLD slots
+ * are all full
+ */
+#define XPM_EVENT_PLDSTALL 0x80U
+
+/*
+ * Counts the number of cycles when the processor is stalled and the data side
+ * is stalled too because it is full and executing writes to the external
+ * memory
+ */
+#define XPM_EVENT_WRITESTALL 0x81U
+
+/*
+ * Counts the number of stall cycles due to main TLB misses on requests issued
+ * by the instruction side
+ */
+#define XPM_EVENT_INSTRTLBSTALL 0x82U
+
+/*
+ * Counts the number of stall cycles due to main TLB misses on requests issued
+ * by the data side
+ */
+#define XPM_EVENT_DATATLBSTALL 0x83U
+
+/*
+ * Counts the number of stall cycles due to micro TLB misses on the instruction
+ * side. This event does not include main TLB miss stall cycles that are already
+ * counted in the corresponding main TLB event
+ */
+#define XPM_EVENT_INSTR_uTLBSTALL 0x84U
+
+/*
+ * Counts the number of stall cycles due to micro TLB misses on the data side.
+ * This event does not include main TLB miss stall cycles that are already
+ * counted in the corresponding main TLB event
+ */
+#define XPM_EVENT_DATA_uTLBSTALL 0x85U
+
+/*
+ * Counts the number of stall cycles because of the execution of a DMB memory
+ * barrier. This includes all DMB instructions being executed, even
+ * speculatively
+ */
+#define XPM_EVENT_DMB_STALL 0x86U
+
+/*
+ * Counts the number of cycles during which the integer core clock is enabled
+ */
+#define XPM_EVENT_INT_CLKEN 0x8AU
+
+/*
+ * Counts the number of cycles during which the Data Engine clock is enabled
+ */
+#define XPM_EVENT_DE_CLKEN 0x8BU
+
+/*
+ * Counts the number of ISB instructions architecturally executed
+ */
+#define XPM_EVENT_INSTRISB 0x90U
+
+/*
+ * Counts the number of DSB instructions architecturally executed
+ */
+#define XPM_EVENT_INSTRDSB 0x91U
+
+/*
+ * Counts the number of DMB instructions speculatively executed
+ */
+#define XPM_EVENT_INSTRDMB 0x92U
+
+/*
+ * Counts the number of external interrupts executed by the processor
+ */
+#define XPM_EVENT_EXTINT 0x93U
+
+/*
+ * PLE cache line request completed
+ */
+#define XPM_EVENT_PLE_LRC 0xA0U
+
+/*
+ * PLE cache line request skipped
+ */
+#define XPM_EVENT_PLE_LRS 0xA1U
+
+/*
+ * PLE FIFO flush
+ */
+#define XPM_EVENT_PLE_FLUSH 0xA2U
+
+/*
+ * PLE request complete
+ */
+#define XPM_EVENT_PLE_CMPL 0xA3U
+
+/*
+ * PLE FIFO overflow
+ */
+#define XPM_EVENT_PLE_OVFL 0xA4U
+
+/*
+ * PLE request programmed
+ */
+#define XPM_EVENT_PLE_PROG 0xA5U
+
+/*
+ * The following constants define the configurations for Cortex-A9 Performance
+ * Monitor Events. Each configuration configures the event counters for a set
+ * of events.
+ * -----------------------------------------------
+ * Config PmCtr0... PmCtr5
+ * -----------------------------------------------
+ * XPM_CNTRCFG1 { XPM_EVENT_SOFTINCR,
+ * XPM_EVENT_INSRFETCH_CACHEREFILL,
+ * XPM_EVENT_INSTRFECT_TLBREFILL,
+ * XPM_EVENT_DATA_CACHEREFILL,
+ * XPM_EVENT_DATA_CACHEACCESS,
+ * XPM_EVENT_DATA_TLBREFILL }
+ *
+ * XPM_CNTRCFG2 { XPM_EVENT_DATA_READS,
+ * XPM_EVENT_DATA_WRITE,
+ * XPM_EVENT_EXCEPTION,
+ * XPM_EVENT_EXCEPRETURN,
+ * XPM_EVENT_CHANGECONTEXT,
+ * XPM_EVENT_SW_CHANGEPC }
+ *
+ * XPM_CNTRCFG3 { XPM_EVENT_IMMEDBRANCH,
+ * XPM_EVENT_UNALIGNEDACCESS,
+ * XPM_EVENT_BRANCHMISS,
+ * XPM_EVENT_CLOCKCYCLES,
+ * XPM_EVENT_BRANCHPREDICT,
+ * XPM_EVENT_JAVABYTECODE }
+ *
+ * XPM_CNTRCFG4 { XPM_EVENT_SWJAVABYTECODE,
+ * XPM_EVENT_JAVABACKBRANCH,
+ * XPM_EVENT_COHERLINEMISS,
+ * XPM_EVENT_COHERLINEHIT,
+ * XPM_EVENT_INSTRSTALL,
+ * XPM_EVENT_DATASTALL }
+ *
+ * XPM_CNTRCFG5 { XPM_EVENT_MAINTLBSTALL,
+ * XPM_EVENT_STREXPASS,
+ * XPM_EVENT_STREXFAIL,
+ * XPM_EVENT_DATAEVICT,
+ * XPM_EVENT_NODISPATCH,
+ * XPM_EVENT_ISSUEEMPTY }
+ *
+ * XPM_CNTRCFG6 { XPM_EVENT_INSTRRENAME,
+ * XPM_EVENT_PREDICTFUNCRET,
+ * XPM_EVENT_MAINEXEC,
+ * XPM_EVENT_SECEXEC,
+ * XPM_EVENT_LDRSTR,
+ * XPM_EVENT_FLOATRENAME }
+ *
+ * XPM_CNTRCFG7 { XPM_EVENT_NEONRENAME,
+ * XPM_EVENT_PLDSTALL,
+ * XPM_EVENT_WRITESTALL,
+ * XPM_EVENT_INSTRTLBSTALL,
+ * XPM_EVENT_DATATLBSTALL,
+ * XPM_EVENT_INSTR_uTLBSTALL }
+ *
+ * XPM_CNTRCFG8 { XPM_EVENT_DATA_uTLBSTALL,
+ * XPM_EVENT_DMB_STALL,
+ * XPM_EVENT_INT_CLKEN,
+ * XPM_EVENT_DE_CLKEN,
+ * XPM_EVENT_INSTRISB,
+ * XPM_EVENT_INSTRDSB }
+ *
+ * XPM_CNTRCFG9 { XPM_EVENT_INSTRDMB,
+ * XPM_EVENT_EXTINT,
+ * XPM_EVENT_PLE_LRC,
+ * XPM_EVENT_PLE_LRS,
+ * XPM_EVENT_PLE_FLUSH,
+ * XPM_EVENT_PLE_CMPL }
+ *
+ * XPM_CNTRCFG10 { XPM_EVENT_PLE_OVFL,
+ * XPM_EVENT_PLE_PROG,
+ * XPM_EVENT_PLE_LRC,
+ * XPM_EVENT_PLE_LRS,
+ * XPM_EVENT_PLE_FLUSH,
+ * XPM_EVENT_PLE_CMPL }
+ *
+ * XPM_CNTRCFG11 { XPM_EVENT_DATASTALL,
+ * XPM_EVENT_INSRFETCH_CACHEREFILL,
+ * XPM_EVENT_INSTRFECT_TLBREFILL,
+ * XPM_EVENT_DATA_CACHEREFILL,
+ * XPM_EVENT_DATA_CACHEACCESS,
+ * XPM_EVENT_DATA_TLBREFILL }
+ */
+#define XPM_CNTRCFG1 0
+#define XPM_CNTRCFG2 1
+#define XPM_CNTRCFG3 2
+#define XPM_CNTRCFG4 3
+#define XPM_CNTRCFG5 4
+#define XPM_CNTRCFG6 5
+#define XPM_CNTRCFG7 6
+#define XPM_CNTRCFG8 7
+#define XPM_CNTRCFG9 8
+#define XPM_CNTRCFG10 9
+#define XPM_CNTRCFG11 10
+
+/**************************** Type Definitions ******************************/
+
+/***************** Macros (Inline Functions) Definitions ********************/
+
+/************************** Variable Definitions ****************************/
+
+/************************** Function Prototypes *****************************/
+
+/* Interface functions to access performance counters from abstraction layer */
+void Xpm_SetEvents(s32 PmcrCfg);
+void Xpm_GetEventCounters(u32 *PmCtrValue);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
+/**
+* @} End of "addtogroup a9_event_counter_apis".
+*/
diff --git a/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/include/xpseudo_asm.h b/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/include/xpseudo_asm.h
new file mode 100644
index 0000000..9cc27a3
--- /dev/null
+++ b/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/include/xpseudo_asm.h
@@ -0,0 +1,80 @@
+/******************************************************************************
+*
+* Copyright (C) 2009 - 2018 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+* THE SOFTWARE.
+*
+*
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xpseudo_asm.h
+*
+* @addtogroup a9_specific Cortex A9 Processor Specific Include Files
+*
+* The xpseudo_asm.h includes xreg_cortexa9.h and xpseudo_asm_gcc.h.
+*
+* The xreg_cortexa9.h file contains definitions for inline assembler code.
+* It provides inline definitions for Cortex A9 GPRs, SPRs, MPE registers,
+* co-processor registers and Debug registers.
+*
+* The xpseudo_asm_gcc.h contains the definitions for the most often used inline
+* assembler instructions, available as macros. These can be very useful for
+* tasks such as setting or getting special purpose registers, synchronization,
+* or cache manipulation etc. These inline assembler instructions can be used
+* from drivers and user applications written in C.
+*
+* @{
+* <pre>
+* MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ----- ---- -------- -----------------------------------------------
+* 1.00a ecm 10/18/09 First release
+* 3.04a sdm 01/02/12 Remove redundant dsb in mcr instruction.
+* 6.8 aru 09/06/18 Removed compilation warnings for ARMCC toolchain.
+* </pre>
+*
+******************************************************************************/
+#ifndef XPSEUDO_ASM_H
+#define XPSEUDO_ASM_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include "xreg_cortexa9.h"
+#ifdef __GNUC__
+ #include "xpseudo_asm_gcc.h"
+#elif defined (__ICCARM__)
+ #include "xpseudo_asm_iccarm.h"
+#else
+ #include "xpseudo_asm_rvct.h"
+#endif
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* XPSEUDO_ASM_H */
+/**
+* @} End of "addtogroup a9_specific".
+*/
diff --git a/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/include/xpseudo_asm_gcc.h b/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/include/xpseudo_asm_gcc.h
new file mode 100644
index 0000000..ed3b8ff
--- /dev/null
+++ b/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/include/xpseudo_asm_gcc.h
@@ -0,0 +1,250 @@
+/******************************************************************************
+*
+* Copyright (C) 2014 - 2016 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+* THE SOFTWARE.
+*
+*
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xpseudo_asm_gcc.h
+*
+* This header file contains macros for using inline assembler code. It is
+* written specifically for the GNU compiler.
+*
+* <pre>
+* MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ----- -------- -------- -----------------------------------------------
+* 5.00 pkp 05/21/14 First release
+* 6.0 mus 07/27/16 Consolidated file for a53,a9 and r5 processors
+* </pre>
+*
+******************************************************************************/
+
+#ifndef XPSEUDO_ASM_GCC_H /* prevent circular inclusions */
+#define XPSEUDO_ASM_GCC_H /* by using protection macros */
+
+/***************************** Include Files ********************************/
+
+#include "xil_types.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif /* __cplusplus */
+
+/************************** Constant Definitions ****************************/
+
+/**************************** Type Definitions ******************************/
+
+/***************** Macros (Inline Functions) Definitions ********************/
+
+/* necessary for pre-processor */
+#define stringify(s) tostring(s)
+#define tostring(s) #s
+
+#if defined (__aarch64__)
+/* pseudo assembler instructions */
+#define mfcpsr() ({u32 rval = 0U; \
+ asm volatile("mrs %0, DAIF" : "=r" (rval));\
+ rval;\
+ })
+
+#define mtcpsr(v) __asm__ __volatile__ ("msr DAIF, %0" : : "r" (v))
+
+#define cpsiei() //__asm__ __volatile__("cpsie i\n")
+#define cpsidi() //__asm__ __volatile__("cpsid i\n")
+
+#define cpsief() //__asm__ __volatile__("cpsie f\n")
+#define cpsidf() //__asm__ __volatile__("cpsid f\n")
+
+
+
+#define mtgpr(rn, v) /*__asm__ __volatile__(\
+ "mov r" stringify(rn) ", %0 \n"\
+ : : "r" (v)\
+ )*/
+
+#define mfgpr(rn) /*({u32 rval; \
+ __asm__ __volatile__(\
+ "mov %0,r" stringify(rn) "\n"\
+ : "=r" (rval)\
+ );\
+ rval;\
+ })*/
+
+/* memory synchronization operations */
+
+/* Instruction Synchronization Barrier */
+#define isb() __asm__ __volatile__ ("isb sy")
+
+/* Data Synchronization Barrier */
+#define dsb() __asm__ __volatile__("dsb sy")
+
+/* Data Memory Barrier */
+#define dmb() __asm__ __volatile__("dmb sy")
+
+
+/* Memory Operations */
+#define ldr(adr) ({u64 rval; \
+ __asm__ __volatile__(\
+ "ldr %0,[%1]"\
+ : "=r" (rval) : "r" (adr)\
+ );\
+ rval;\
+ })
+
+#define mfelrel3() ({u64 rval = 0U; \
+ asm volatile("mrs %0, ELR_EL3" : "=r" (rval));\
+ rval;\
+ })
+
+#define mtelrel3(v) __asm__ __volatile__ ("msr ELR_EL3, %0" : : "r" (v))
+
+#else
+
+/* pseudo assembler instructions */
+#define mfcpsr() ({u32 rval = 0U; \
+ __asm__ __volatile__(\
+ "mrs %0, cpsr\n"\
+ : "=r" (rval)\
+ );\
+ rval;\
+ })
+
+#define mtcpsr(v) __asm__ __volatile__(\
+ "msr cpsr,%0\n"\
+ : : "r" (v)\
+ )
+
+#define cpsiei() __asm__ __volatile__("cpsie i\n")
+#define cpsidi() __asm__ __volatile__("cpsid i\n")
+
+#define cpsief() __asm__ __volatile__("cpsie f\n")
+#define cpsidf() __asm__ __volatile__("cpsid f\n")
+
+
+
+#define mtgpr(rn, v) __asm__ __volatile__(\
+ "mov r" stringify(rn) ", %0 \n"\
+ : : "r" (v)\
+ )
+
+#define mfgpr(rn) ({u32 rval; \
+ __asm__ __volatile__(\
+ "mov %0,r" stringify(rn) "\n"\
+ : "=r" (rval)\
+ );\
+ rval;\
+ })
+
+/* memory synchronization operations */
+
+/* Instruction Synchronization Barrier */
+#define isb() __asm__ __volatile__ ("isb" : : : "memory")
+
+/* Data Synchronization Barrier */
+#define dsb() __asm__ __volatile__ ("dsb" : : : "memory")
+
+/* Data Memory Barrier */
+#define dmb() __asm__ __volatile__ ("dmb" : : : "memory")
+
+
+/* Memory Operations */
+#define ldr(adr) ({u32 rval; \
+ __asm__ __volatile__(\
+ "ldr %0,[%1]"\
+ : "=r" (rval) : "r" (adr)\
+ );\
+ rval;\
+ })
+
+#endif
+
+#define ldrb(adr) ({u8 rval; \
+ __asm__ __volatile__(\
+ "ldrb %0,[%1]"\
+ : "=r" (rval) : "r" (adr)\
+ );\
+ rval;\
+ })
+
+#define str(adr, val) __asm__ __volatile__(\
+ "str %0,[%1]\n"\
+ : : "r" (val), "r" (adr)\
+ )
+
+#define strb(adr, val) __asm__ __volatile__(\
+ "strb %0,[%1]\n"\
+ : : "r" (val), "r" (adr)\
+ )
+
+/* Count leading zeroes (clz) */
+#define clz(arg) ({u8 rval; \
+ __asm__ __volatile__(\
+ "clz %0,%1"\
+ : "=r" (rval) : "r" (arg)\
+ );\
+ rval;\
+ })
+
+#if defined (__aarch64__)
+#define mtcpdc(reg,val) __asm__ __volatile__("dc " #reg ",%0" : : "r" (val))
+#define mtcpic(reg,val) __asm__ __volatile__("ic " #reg ",%0" : : "r" (val))
+
+#define mtcpicall(reg) __asm__ __volatile__("ic " #reg)
+#define mtcptlbi(reg) __asm__ __volatile__("tlbi " #reg)
+#define mtcpat(reg,val) __asm__ __volatile__("at " #reg ",%0" : : "r" (val))
+/* CP15 operations */
+#define mfcp(reg) ({u64 rval = 0U;\
+ __asm__ __volatile__("mrs %0, " #reg : "=r" (rval));\
+ rval;\
+ })
+
+#define mtcp(reg,val) __asm__ __volatile__("msr " #reg ",%0" : : "r" (val))
+
+#else
+/* CP15 operations */
+#define mtcp(rn, v) __asm__ __volatile__(\
+ "mcr " rn "\n"\
+ : : "r" (v)\
+ );
+
+#define mfcp(rn) ({u32 rval = 0U; \
+ __asm__ __volatile__(\
+ "mrc " rn "\n"\
+ : "=r" (rval)\
+ );\
+ rval;\
+ })
+#endif
+
+/************************** Variable Definitions ****************************/
+
+/************************** Function Prototypes *****************************/
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+
+#endif /* XPSEUDO_ASM_GCC_H */
diff --git a/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/include/xqspips.h b/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/include/xqspips.h
new file mode 100644
index 0000000..43b6ffe
--- /dev/null
+++ b/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/include/xqspips.h
@@ -0,0 +1,802 @@
+/******************************************************************************
+*
+* Copyright (C) 2010 - 2019 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+* THE SOFTWARE.
+*
+*
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xqspips.h
+* @addtogroup qspips_v3_6
+* @{
+* @details
+*
+* This file contains the implementation of the XQspiPs driver. It supports only
+* master mode. User documentation for the driver functions is contained in this
+* file in the form of comment blocks at the front of each function.
+*
+* A QSPI device connects to an QSPI bus through a 4-wire serial interface.
+* The QSPI bus is a full-duplex, synchronous bus that facilitates communication
+* between one master and one slave. The device is always full-duplex,
+* which means that for every byte sent, one is received, and vice-versa.
+* The master controls the clock, so it can regulate when it wants to
+* send or receive data. The slave is under control of the master, it must
+* respond quickly since it has no control of the clock and must send/receive
+* data as fast or as slow as the master does.
+*
+* <b> Linear Mode </b>
+* The Linear Quad-SPI Controller extends the existing Quad-SPI Controller�s
+* functionality by adding a linear addressing scheme that allows the SPI flash
+* memory subsystem to behave like a typical ROM device. The new feature hides
+* the normal SPI protocol from a master reading from the SPI flash memory. The
+* feature improves both the user friendliness and the overall read memory
+* throughput over that of the current Quad-SPI Controller by lessening the
+* amount of software overheads required and by the use of the faster AXI
+* interface.
+*
+* <b>Initialization & Configuration</b>
+*
+* The XQspiPs_Config structure is used by the driver to configure itself. This
+* configuration structure is typically created by the tool-chain based on HW
+* build properties.
+*
+* To support multiple runtime loading and initialization strategies employed by
+* various operating systems, the driver instance can be initialized in the
+* following way:
+* - XQspiPs_LookupConfig(DeviceId) - Use the device identifier to find
+* static configuration structure defined in xqspips_g.c. This is setup
+* by the tools. For some operating systems the config structure will be
+* initialized by the software and this call is not needed.
+* - XQspiPs_CfgInitialize(InstancePtr, CfgPtr, EffectiveAddr) - Uses a
+* configuration structure provided by the caller. If running in a system
+* with address translation, the provided virtual memory base address
+* replaces the physical address present in the configuration structure.
+*
+* <b>Multiple Masters</b>
+*
+* More than one master can exist, but arbitration is the responsibility of
+* the higher layer software. The device driver does not perform any type of
+* arbitration.
+*
+* <b>Modes of Operation</b>
+*
+* There are four modes to perform a data transfer and the selection of a mode
+* is based on Chip Select(CS) and Start. These two options individually, can
+* be controlled either by software(Manual) or hardware(Auto).
+* - Auto CS: Chip select is automatically asserted as soon as the first word
+* is written into the TXFIFO and de asserted when the TXFIFO becomes
+* empty
+* - Manual CS: Software must assert and de assert CS.
+* - Auto Start: Data transmission starts as soon as there is data in the
+* TXFIFO and stalls when the TXFIFO is empty
+* - Manual Start: Software must start data transmission at the beginning of
+* the transaction or whenever the TXFIFO has become empty
+*
+* The preferred combination is Manual CS and Auto Start.
+* In this combination, the software asserts CS before loading any data into
+* TXFIFO. In Auto Start mode, whenever data is in TXFIFO, controller sends it
+* out until TXFIFO becomes empty. The software reads the RXFIFO whenever the
+* data is available. If no further data, software disables CS.
+*
+* Risks/challenges of other combinations:
+* - Manual CS and Manual Start: Manual Start bit should be set after each
+* TXFIFO write otherwise there could be a race condition where the TXFIFO
+* becomes empty before the new word is written. In that case the
+* transmission stops.
+* - Auto CS with Manual or Auto Start: It is very difficult for software to
+* keep the TXFIFO filled. Whenever the TXFIFO runs empty, CS is de asserted.
+* This results in a single transaction to be split into multiple pieces each
+* with its own chip select. This will result in garbage data to be sent.
+*
+* <b>Interrupts</b>
+*
+* The user must connect the interrupt handler of the driver,
+* XQspiPs_InterruptHandler, to an interrupt system such that it will be
+* called when an interrupt occurs. This function does not save and restore
+* the processor context such that the user must provide this processing.
+*
+* The driver handles the following interrupts:
+* - Data Transmit Register/FIFO Underflow
+* - Data Receive Register/FIFO Not Empty
+* - Data Transmit Register/FIFO Overwater
+* - Data Receive Register/FIFO Overrun
+*
+* The Data Transmit Register/FIFO Overwater interrupt -- indicates that the
+* QSPI device has transmitted the data available to transmit, and now its data
+* register and FIFO is ready to accept more data. The driver uses this
+* interrupt to indicate progress while sending data. The driver may have
+* more data to send, in which case the data transmit register and FIFO is
+* filled for subsequent transmission. When this interrupt arrives and all
+* the data has been sent, the driver invokes the status callback with a
+* value of XST_SPI_TRANSFER_DONE to inform the upper layer software that
+* all data has been sent.
+*
+* The Data Transmit Register/FIFO Underflow interrupt -- indicates that,
+* as slave, the QSPI device was required to transmit but there was no data
+* available to transmit in the transmit register (or FIFO). This may not
+* be an error if the master is not expecting data. But in the case where
+* the master is expecting data, this serves as a notification of such a
+* condition. The driver reports this condition to the upper layer
+* software through the status handler.
+*
+* The Data Receive Register/FIFO Overrun interrupt -- indicates that the QSPI
+* device received data and subsequently dropped the data because the data
+* receive register and FIFO was full. The driver reports this condition to the
+* upper layer software through the status handler. This likely indicates a
+* problem with the higher layer protocol, or a problem with the slave
+* performance.
+*
+*
+* <b>Polled Operation</b>
+*
+* Transfer in polled mode is supported through a separate interface function
+* XQspiPs_PolledTransfer(). Unlike the transfer function in the interrupt mode,
+* this function blocks until all data has been sent/received.
+*
+* <b>Device Busy</b>
+*
+* Some operations are disallowed when the device is busy. The driver tracks
+* whether a device is busy. The device is considered busy when a data transfer
+* request is outstanding, and is considered not busy only when that transfer
+* completes (or is aborted with a mode fault error).
+*
+* <b>Device Configuration</b>
+*
+* The device can be configured in various ways during the FPGA implementation
+* process. Configuration parameters are stored in the xqspips_g.c file or
+* passed in via XQspiPs_CfgInitialize(). A table is defined where each entry
+* contains configuration information for an QSPI device, including the base
+* address for the device.
+*
+* <b>RTOS Independence</b>
+*
+* This driver is intended to be RTOS and processor independent. It works with
+* physical addresses only. Any needs for dynamic memory management, threads or
+* thread mutual exclusion, virtual memory, or cache control must be satisfied
+* by the layer above this driver.
+*
+* NOTE: This driver was always tested with endianness set to little-endian.
+*
+* <pre>
+* MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ----- --- -------- -----------------------------------------------
+* 1.00a sdm 11/25/10 First release, based on the PS SPI driver...
+* 1.01a sdm 11/22/11 Added TCL file for generating QSPI parameters
+* in xparameters.h
+* 2.00a kka 07/25/12 Added a few register defines for CR 670297
+* Removed code related to mode fault for CR 671468
+* The XQspiPs_SetSlaveSelect has been modified to remove
+* the argument of the slave select as the QSPI controller
+* only supports one slave.
+* XQspiPs_GetSlaveSelect API has been removed
+* Added a flag ShiftReadData to the instance structure
+*. and is used in the XQspiPs_GetReadData API.
+* The ShiftReadData Flag indicates whether the data
+* read from the Rx FIFO needs to be shifted
+* in cases where the data is less than 4 bytes
+* Removed the selection for the following options:
+* Master mode (XQSPIPS_MASTER_OPTION) and
+* Flash interface mode (XQSPIPS_FLASH_MODE_OPTION) option
+* as the QSPI driver supports the Master mode
+* and Flash Interface mode and doesnot support
+* Slave mode or the legacy mode.
+* Modified the XQspiPs_PolledTransfer and XQspiPs_Transfer
+* APIs so that the last argument (IsInst) specifying whether
+* it is instruction or data has been removed. The first byte
+* in the SendBufPtr argument of these APIs specify the
+* instruction to be sent to the Flash Device.
+* This version of the driver fixes CRs 670197/663787/
+* 670297/671468.
+* Added the option for setting the Holdb_dr bit in the
+* configuration options, XQSPIPS_HOLD_B_DRIVE_OPTION
+* is the option to be used for setting this bit in the
+* configuration register.
+* The XQspiPs_PolledTransfer function has been updated
+* to fill the data to fifo depth.
+* 2.01a sg 02/03/13 Added flash opcodes for DUAL_IO_READ,QUAD_IO_READ.
+* Added macros for Set/Get Rx Watermark. Changed QSPI
+* Enable/Disable macro argument from BaseAddress to
+* Instance Pointer. Added DelayNss argument to SetDelays
+* and GetDelays API's.
+* Created macros XQspiPs_IsManualStart and
+* XQspiPs_IsManualChipSelect.
+* Changed QSPI transfer logic for polled and interrupt
+* modes to be based on filled tx fifo count and receive
+* based on it. RXNEMPTY interrupt is not used.
+* Added assertions to XQspiPs_LqspiRead function.
+* SetDelays and GetDelays API's include DelayNss parameter.
+* Added defines for DelayNss,Rx Watermark,Interrupts
+* which need write to clear. Removed Read zeros mask from
+* LQSPI Config register. Renamed Fixed burst error to
+* data FSM error in LQSPI Status register.
+*
+* 2.02a hk 05/07/13 Added ConnectionMode to config structure.
+* Corresponds to C_QSPI_MODE - 0:Single, 1:Stacked, 2:Parallel
+* Added enable and disable to the XQspiPs_LqspiRead() function
+* Removed XQspi_Reset() in Set_Options() function when
+* LQSPI_MODE_OPTION is set.
+* Added instructions for bank selection, die erase and
+* flag status register to the flash instruction table
+* Handling for instructions not in flash instruction
+* table added. Checking for Tx FIFO empty when switching from
+* TXD1/2/3 to TXD0 added. If WRSR instruction is sent with
+* byte count 3 (spansion), instruction size and TXD register
+* changed accordingly. CR# 712502 and 703869.
+* Added prefix to constant definitions for ConnectionMode
+* Added (#ifdef linear base address) in the Linear read function.
+* Changed XPAR_XQSPIPS_0_LINEAR_BASEADDR to
+* XPAR_PS7_QSPI_LINEAR_0_S_AXI_BASEADDR in
+* XQspiPs_LqspiRead function. Fix for CR#718141.
+*
+* 2.03a hk 09/17/13 Modified polled and interrupt transfers to make use of
+* thresholds. This is to improve performance.
+* Added API's for QSPI reset and
+* linear mode initialization for boot.
+* Added RX and TX threshold reset to one in XQspiPs_Abort.
+* Added RX threshold reset(1) after transfer in polled and
+* interrupt transfers. Made changes to make sure threshold
+* change is done only when no transfer is in progress.
+* Updated linear init API for parallel and stacked modes.
+* CR#737760.
+* 3.1 hk 08/13/14 When writing to the configuration register, set/reset
+* required bits leaving reserved bits untouched. CR# 796813.
+* 3.2 sk 02/05/15 Add SLCR reset in abort function as a workaround because
+* controller does not update FIFO status flags as expected
+* when thresholds are used.
+* 3.3 sk 11/07/15 Modified the API prototypes according to MISRAC standards
+* to remove compilation warnings. CR# 868893.
+* ms 03/17/17 Added readme.txt file in examples folder for doxygen
+* generation.
+* ms 04/05/17 Modified Comment lines in functions of qspips
+* examples to recognize it as documentation block
+* and modified filename tag in
+* xqspips_dual_flash_stack_lqspi_example.c to include it in
+* doxygen examples.
+* 3.4 nsk 31/07/17 Added QSPI_BUS_WIDTH parameter in xparameters.h file
+* 3.5 tjs 08/21/18 Fixed compilation warnings for the ARMCC.
+* 3.5 tjs 07/16/18 Added support for low density ISSI flash parts.
+* 3.6 akm 03/28/19 Fixed memory leak issue while reading from qspi.(CR#1016357)
+* 3.6 akm 04/15/19 Modified FlashQuadEnable, FlashWrie and FlashErase APIs,
+* to wait for the on going operation to complete before
+* performing the next operation.
+* 3.6 akm 04/15/19 Modified the mask in XQspiPs_GetReadData() API to retrieve
+* configuration register values of both the Flashes in dual
+* parellel connection.
+*
+* </pre>
+*
+******************************************************************************/
+#ifndef XQSPIPS_H /* prevent circular inclusions */
+#define XQSPIPS_H /* by using protection macros */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/***************************** Include Files *********************************/
+
+#include "xstatus.h"
+#include "xqspips_hw.h"
+#include <string.h>
+
+/************************** Constant Definitions *****************************/
+
+/** @name Configuration options
+ *
+ * The following options are supported to enable/disable certain features of
+ * an QSPI device. Each of the options is a bit mask, so more than one may be
+ * specified.
+ *
+ *
+ * The <b>Active Low Clock option</b> configures the device's clock polarity.
+ * Setting this option means the clock is active low and the SCK signal idles
+ * high. By default, the clock is active high and SCK idles low.
+ *
+ * The <b>Clock Phase option</b> configures the QSPI device for one of two
+ * transfer formats. A clock phase of 0, the default, means data is valid on
+ * the first SCK edge (rising or falling) after the slave select (SS) signal
+ * has been asserted. A clock phase of 1 means data is valid on the second SCK
+ * edge (rising or falling) after SS has been asserted.
+ *
+ *
+ * The <b>QSPI Force Slave Select option</b> is used to enable manual control of
+ * the slave select signal.
+ * 0: The SPI_SS signal is controlled by the QSPI controller during
+ * transfers. (Default)
+ * 1: The SPI_SS signal is forced active (driven low) regardless of any
+ * transfers in progress.
+ *
+ * NOTE: The driver will handle setting and clearing the Slave Select when
+ * the user sets the "FORCE_SSELECT_OPTION". Using this option will allow the
+ * QSPI clock to be set to a faster speed. If the QSPI clock is too fast, the
+ * processor cannot empty and refill the FIFOs before the TX FIFO is empty
+ * When the QSPI hardware is controlling the Slave Select signals, this
+ * will cause slave to be de-selected and terminate the transfer.
+ *
+ * The <b>Manual Start option</b> is used to enable manual control of
+ * the Start command to perform data transfer.
+ * 0: The Start command is controlled by the QSPI controller during
+ * transfers(Default). Data transmission starts as soon as there is data in
+ * the TXFIFO and stalls when the TXFIFO is empty
+ * 1: The Start command must be issued by software to perform data transfer.
+ * Bit 15 of Configuration register is used to issue Start command. This bit
+ * must be set whenever TXFIFO is filled with new data.
+ *
+ * NOTE: The driver will set the Manual Start Enable bit in Configuration
+ * Register, if Manual Start option is selected. Software will issue
+ * Manual Start command whenever TXFIFO is filled with data. When there is
+ * no further data, driver will clear the Manual Start Enable bit.
+ *
+ * @{
+ */
+#define XQSPIPS_CLK_ACTIVE_LOW_OPTION 0x2 /**< Active Low Clock option */
+#define XQSPIPS_CLK_PHASE_1_OPTION 0x4 /**< Clock Phase one option */
+#define XQSPIPS_FORCE_SSELECT_OPTION 0x10 /**< Force Slave Select */
+#define XQSPIPS_MANUAL_START_OPTION 0x20 /**< Manual Start enable */
+#define XQSPIPS_LQSPI_MODE_OPTION 0x80 /**< Linear QPSI mode */
+#define XQSPIPS_HOLD_B_DRIVE_OPTION 0x100 /**< Drive HOLD_B Pin */
+/*@}*/
+
+
+/** @name QSPI Clock Prescaler options
+ * The QSPI Clock Prescaler Configuration bits are used to program master mode
+ * bit rate. The bit rate can be programmed in divide-by-two decrements from
+ * pclk/2 to pclk/256.
+ *
+ * @{
+ */
+#define XQSPIPS_CLK_PRESCALE_2 0x00 /**< PCLK/2 Prescaler */
+#define XQSPIPS_CLK_PRESCALE_4 0x01 /**< PCLK/4 Prescaler */
+#define XQSPIPS_CLK_PRESCALE_8 0x02 /**< PCLK/8 Prescaler */
+#define XQSPIPS_CLK_PRESCALE_16 0x03 /**< PCLK/16 Prescaler */
+#define XQSPIPS_CLK_PRESCALE_32 0x04 /**< PCLK/32 Prescaler */
+#define XQSPIPS_CLK_PRESCALE_64 0x05 /**< PCLK/64 Prescaler */
+#define XQSPIPS_CLK_PRESCALE_128 0x06 /**< PCLK/128 Prescaler */
+#define XQSPIPS_CLK_PRESCALE_256 0x07 /**< PCLK/256 Prescaler */
+
+/*@}*/
+
+
+/** @name Callback events
+ *
+ * These constants specify the handler events that are passed to
+ * a handler from the driver. These constants are not bit masks such that
+ * only one will be passed at a time to the handler.
+ *
+ * @{
+ */
+#define XQSPIPS_EVENT_TRANSFER_DONE 2 /**< Transfer done */
+#define XQSPIPS_EVENT_TRANSMIT_UNDERRUN 3 /**< TX FIFO empty */
+#define XQSPIPS_EVENT_RECEIVE_OVERRUN 4 /**< Receive data loss because
+ * RX FIFO full
+ */
+/*@}*/
+
+/** @name Flash commands
+ *
+ * The following constants define most of the commands supported by flash
+ * devices. Users can add more commands supported by the flash devices
+ *
+ * @{
+ */
+#define XQSPIPS_FLASH_OPCODE_WRSR 0x01 /* Write status register */
+#define XQSPIPS_FLASH_OPCODE_PP 0x02 /* Page program */
+#define XQSPIPS_FLASH_OPCODE_NORM_READ 0x03 /* Normal read data bytes */
+#define XQSPIPS_FLASH_OPCODE_WRDS 0x04 /* Write disable */
+#define XQSPIPS_FLASH_OPCODE_RDSR1 0x05 /* Read status register 1 */
+#define XQSPIPS_FLASH_OPCODE_WREN 0x06 /* Write enable */
+#define XQSPIPS_FLASH_OPCODE_FAST_READ 0x0B /* Fast read data bytes */
+#define XQSPIPS_FLASH_OPCODE_BE_4K 0x20 /* Erase 4KiB block */
+#define XQSPIPS_FLASH_OPCODE_RDSR2 0x35 /* Read status register 2 */
+#define XQSPIPS_FLASH_OPCODE_DUAL_READ 0x3B /* Dual read data bytes */
+#define XQSPIPS_FLASH_OPCODE_BE_32K 0x52 /* Erase 32KiB block */
+#define XQSPIPS_FLASH_OPCODE_QUAD_READ 0x6B /* Quad read data bytes */
+#define XQSPIPS_FLASH_OPCODE_ERASE_SUS 0x75 /* Erase suspend */
+#define XQSPIPS_FLASH_OPCODE_ERASE_RES 0x7A /* Erase resume */
+#define XQSPIPS_FLASH_OPCODE_RDID 0x9F /* Read JEDEC ID */
+#define XQSPIPS_FLASH_OPCODE_BE 0xC7 /* Erase whole flash block */
+#define XQSPIPS_FLASH_OPCODE_SE 0xD8 /* Sector erase (usually 64KB)*/
+#define XQSPIPS_FLASH_OPCODE_DUAL_IO_READ 0xBB /* Read data using Dual I/O */
+#define XQSPIPS_FLASH_OPCODE_QUAD_IO_READ 0xEB /* Read data using Quad I/O */
+#define XQSPIPS_FLASH_OPCODE_BRWR 0x17 /* Bank Register Write */
+#define XQSPIPS_FLASH_OPCODE_BRRD 0x16 /* Bank Register Read */
+/* Extende Address Register Write - Micron's equivalent of Bank Register */
+#define XQSPIPS_FLASH_OPCODE_EARWR 0xC5
+/* Extende Address Register Read - Micron's equivalent of Bank Register */
+#define XQSPIPS_FLASH_OPCODE_EARRD 0xC8
+#define XQSPIPS_FLASH_OPCODE_DIE_ERASE 0xC4
+#define XQSPIPS_FLASH_OPCODE_READ_FLAG_SR 0x70
+#define XQSPIPS_FLASH_OPCODE_CLEAR_FLAG_SR 0x50
+#define XQSPIPS_FLASH_OPCODE_READ_LOCK_REG 0xE8 /* Lock Reg Read */
+#define XQSPIPS_FLASH_OPCODE_WRITE_LOCK_REG 0xE5 /* Lock Reg Write */
+
+/*@}*/
+
+/** @name Instruction size
+ *
+ * The following constants define numbers 1 to 4.
+ * Used to identify whether TXD0,1,2 or 3 is to be used.
+ *
+ * @{
+ */
+#define XQSPIPS_SIZE_ONE 1
+#define XQSPIPS_SIZE_TWO 2
+#define XQSPIPS_SIZE_THREE 3
+#define XQSPIPS_SIZE_FOUR 4
+
+/*@}*/
+
+/** @name ConnectionMode
+ *
+ * The following constants are the possible values of ConnectionMode in
+ * Config structure.
+ *
+ * @{
+ */
+#define XQSPIPS_CONNECTION_MODE_SINGLE 0
+#define XQSPIPS_CONNECTION_MODE_STACKED 1
+#define XQSPIPS_CONNECTION_MODE_PARALLEL 2
+
+/*@}*/
+
+/** @name FIFO threshold value
+ *
+ * This is the Rx FIFO threshold (in words) that was found to be most
+ * optimal in terms of performance
+ *
+ * @{
+ */
+#define XQSPIPS_RXFIFO_THRESHOLD_OPT 32
+
+/*@}*/
+
+/**************************** Type Definitions *******************************/
+/**
+ * The handler data type allows the user to define a callback function to
+ * handle the asynchronous processing for the QSPI device. The application
+ * using this driver is expected to define a handler of this type to support
+ * interrupt driven mode. The handler executes in an interrupt context, so
+ * only minimal processing should be performed.
+ *
+ * @param CallBackRef is the callback reference passed in by the upper
+ * layer when setting the callback functions, and passed back to
+ * the upper layer when the callback is invoked. Its type is
+ * not important to the driver, so it is a void pointer.
+ * @param StatusEvent holds one or more status events that have occurred.
+ * See the XQspiPs_SetStatusHandler() for details on the status
+ * events that can be passed in the callback.
+ * @param ByteCount indicates how many bytes of data were successfully
+ * transferred. This may be less than the number of bytes
+ * requested if the status event indicates an error.
+ */
+typedef void (*XQspiPs_StatusHandler) (void *CallBackRef, u32 StatusEvent,
+ unsigned ByteCount);
+
+/**
+ * This typedef contains configuration information for the device.
+ */
+typedef struct {
+ u16 DeviceId; /**< Unique ID of device */
+ u32 BaseAddress; /**< Base address of the device */
+ u32 InputClockHz; /**< Input clock frequency */
+ u8 ConnectionMode; /**< Single, Stacked and Parallel mode */
+} XQspiPs_Config;
+
+/**
+ * The XQspiPs driver instance data. The user is required to allocate a
+ * variable of this type for every QSPI device in the system. A pointer
+ * to a variable of this type is then passed to the driver API functions.
+ */
+typedef struct {
+ XQspiPs_Config Config; /**< Configuration structure */
+ u32 IsReady; /**< Device is initialized and ready */
+
+ u8 *SendBufferPtr; /**< Buffer to send (state) */
+ u8 *RecvBufferPtr; /**< Buffer to receive (state) */
+ int RequestedBytes; /**< Number of bytes to transfer (state) */
+ int RemainingBytes; /**< Number of bytes left to transfer(state) */
+ u32 IsBusy; /**< A transfer is in progress (state) */
+ XQspiPs_StatusHandler StatusHandler;
+ void *StatusRef; /**< Callback reference for status handler */
+ u32 ShiftReadData; /**< Flag to indicate whether the data
+ * read from the Rx FIFO needs to be shifted
+ * in cases where the data is less than 4
+ * bytes
+ */
+} XQspiPs;
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/****************************************************************************/
+/*
+*
+* Check in OptionsTable if Manual Start Option is enabled or disabled.
+*
+* @param InstancePtr is a pointer to the XQspiPs instance.
+*
+* @return
+* - TRUE if option is set
+* - FALSE if option is not set
+*
+* @note C-Style signature:
+* u8 XQspiPs_IsManualStart(XQspiPs *InstancePtr);
+*
+*****************************************************************************/
+#define XQspiPs_IsManualStart(InstancePtr) \
+ ((XQspiPs_GetOptions(InstancePtr) & \
+ XQSPIPS_MANUAL_START_OPTION) ? TRUE : FALSE)
+
+/****************************************************************************/
+/*
+*
+* Check in OptionsTable if Manual Chip Select Option is enabled or disabled.
+*
+* @param InstancePtr is a pointer to the XSpiPs instance.
+*
+* @return
+* - TRUE if option is set
+* - FALSE if option is not set
+*
+* @note C-Style signature:
+* u8 XQspiPs_IsManualChipSelect(XQspiPs *InstancePtr);
+*
+*****************************************************************************/
+#define XQspiPs_IsManualChipSelect(InstancePtr) \
+ ((XQspiPs_GetOptions(InstancePtr) & \
+ XQSPIPS_FORCE_SSELECT_OPTION) ? TRUE : FALSE)
+
+/****************************************************************************/
+/**
+*
+* Set the contents of the slave idle count register.
+*
+* @param InstancePtr is a pointer to the XQspiPs instance.
+* @param RegisterValue is the value to be written, valid values are
+* 0-255.
+*
+* @return None
+*
+* @note C-Style signature:
+* void XQspiPs_SetSlaveIdle(XQspiPs *InstancePtr,
+* u32 RegisterValue)
+*
+*****************************************************************************/
+#define XQspiPs_SetSlaveIdle(InstancePtr, RegisterValue) \
+ XQspiPs_Out32(((InstancePtr)->Config.BaseAddress) + \
+ XQSPIPS_SICR_OFFSET, (RegisterValue))
+
+/****************************************************************************/
+/**
+*
+* Get the contents of the slave idle count register. Use the XQSPIPS_SICR_*
+* constants defined in xqspips_hw.h to interpret the bit-mask returned.
+*
+* @param InstancePtr is a pointer to the XQspiPs instance.
+*
+* @return An 8-bit value representing Slave Idle Count.
+*
+* @note C-Style signature:
+* u32 XQspiPs_GetSlaveIdle(XQspiPs *InstancePtr)
+*
+*****************************************************************************/
+#define XQspiPs_GetSlaveIdle(InstancePtr) \
+ XQspiPs_In32(((InstancePtr)->Config.BaseAddress) + \
+ XQSPIPS_SICR_OFFSET)
+
+/****************************************************************************/
+/**
+*
+* Set the contents of the transmit FIFO watermark register.
+*
+* @param InstancePtr is a pointer to the XQspiPs instance.
+* @param RegisterValue is the value to be written, valid values are 1-63.
+*
+* @return None.
+*
+* @note C-Style signature:
+* void XQspiPs_SetTXWatermark(XQspiPs *InstancePtr,
+* u32 RegisterValue)
+*
+*****************************************************************************/
+#define XQspiPs_SetTXWatermark(InstancePtr, RegisterValue) \
+ XQspiPs_Out32(((InstancePtr)->Config.BaseAddress) + \
+ XQSPIPS_TXWR_OFFSET, (RegisterValue))
+
+/****************************************************************************/
+/**
+*
+* Get the contents of the transmit FIFO watermark register.
+* Valid values are in the range 1-63.
+*
+* @param InstancePtr is a pointer to the XQspiPs instance.
+*
+* @return A 6-bit value representing Tx Watermark level.
+*
+* @note C-Style signature:
+* u32 XQspiPs_GetTXWatermark(XQspiPs *InstancePtr)
+*
+*****************************************************************************/
+#define XQspiPs_GetTXWatermark(InstancePtr) \
+ XQspiPs_In32((InstancePtr->Config.BaseAddress) + XQSPIPS_TXWR_OFFSET)
+
+/****************************************************************************/
+/**
+*
+* Set the contents of the receive FIFO watermark register.
+*
+* @param InstancePtr is a pointer to the XQspiPs instance.
+* @param RegisterValue is the value to be written, valid values are 1-63.
+*
+* @return None.
+*
+* @note C-Style signature:
+* void XQspiPs_SetRXWatermark(XQspiPs *InstancePtr,
+* u32 RegisterValue)
+*
+*****************************************************************************/
+#define XQspiPs_SetRXWatermark(InstancePtr, RegisterValue) \
+ XQspiPs_Out32(((InstancePtr)->Config.BaseAddress) + \
+ XQSPIPS_RXWR_OFFSET, (RegisterValue))
+
+/****************************************************************************/
+/**
+*
+* Get the contents of the receive FIFO watermark register.
+* Valid values are in the range 1-63.
+*
+* @param InstancePtr is a pointer to the XQspiPs instance.
+*
+* @return A 6-bit value representing Rx Watermark level.
+*
+* @note C-Style signature:
+* u32 XQspiPs_GetRXWatermark(XQspiPs *InstancePtr)
+*
+*****************************************************************************/
+#define XQspiPs_GetRXWatermark(InstancePtr) \
+ XQspiPs_In32((InstancePtr->Config.BaseAddress) + XQSPIPS_RXWR_OFFSET)
+
+/****************************************************************************/
+/**
+*
+* Enable the device and uninhibit master transactions.
+*
+* @param InstancePtr is a pointer to the XQspiPs instance.
+*
+* @return None.
+*
+* @note C-Style signature:
+* void XQspiPs_Enable(XQspiPs *InstancePtr)
+*
+*****************************************************************************/
+#define XQspiPs_Enable(InstancePtr) \
+ XQspiPs_Out32((InstancePtr->Config.BaseAddress) + XQSPIPS_ER_OFFSET, \
+ XQSPIPS_ER_ENABLE_MASK)
+
+/****************************************************************************/
+/**
+*
+* Disable the device.
+*
+* @param InstancePtr is a pointer to the XQspiPs instance.
+*
+* @return None.
+*
+* @note C-Style signature:
+* void XQspiPs_Disable(XQspiPs *InstancePtr)
+*
+*****************************************************************************/
+#define XQspiPs_Disable(InstancePtr) \
+ XQspiPs_Out32((InstancePtr->Config.BaseAddress) + XQSPIPS_ER_OFFSET, 0)
+
+/****************************************************************************/
+/**
+*
+* Set the contents of the Linear QSPI Configuration register.
+*
+* @param InstancePtr is a pointer to the XQspiPs instance.
+* @param RegisterValue is the value to be written to the Linear QSPI
+* configuration register.
+*
+* @return None.
+*
+* @note C-Style signature:
+* void XQspiPs_SetLqspiConfigReg(XQspiPs *InstancePtr,
+* u32 RegisterValue)
+*
+*****************************************************************************/
+#define XQspiPs_SetLqspiConfigReg(InstancePtr, RegisterValue) \
+ XQspiPs_Out32(((InstancePtr)->Config.BaseAddress) + \
+ XQSPIPS_LQSPI_CR_OFFSET, (RegisterValue))
+
+/****************************************************************************/
+/**
+*
+* Get the contents of the Linear QSPI Configuration register.
+*
+* @param InstancePtr is a pointer to the XQspiPs instance.
+*
+* @return A 32-bit value representing the contents of the LQSPI Config
+* register.
+*
+* @note C-Style signature:
+* u32 XQspiPs_GetLqspiConfigReg(u32 *InstancePtr)
+*
+*****************************************************************************/
+#define XQspiPs_GetLqspiConfigReg(InstancePtr) \
+ XQspiPs_In32((InstancePtr->Config.BaseAddress) + \
+ XQSPIPS_LQSPI_CR_OFFSET)
+
+/************************** Function Prototypes ******************************/
+
+/*
+ * Initialization function, implemented in xqspips_sinit.c
+ */
+XQspiPs_Config *XQspiPs_LookupConfig(u16 DeviceId);
+
+/*
+ * Functions implemented in xqspips.c
+ */
+int XQspiPs_CfgInitialize(XQspiPs *InstancePtr, XQspiPs_Config *Config,
+ u32 EffectiveAddr);
+void XQspiPs_Reset(XQspiPs *InstancePtr);
+void XQspiPs_Abort(XQspiPs *InstancePtr);
+
+s32 XQspiPs_Transfer(XQspiPs *InstancePtr, u8 *SendBufPtr, u8 *RecvBufPtr,
+ u32 ByteCount);
+s32 XQspiPs_PolledTransfer(XQspiPs *InstancePtr, u8 *SendBufPtr,
+ u8 *RecvBufPtr, u32 ByteCount);
+int XQspiPs_LqspiRead(XQspiPs *InstancePtr, u8 *RecvBufPtr,
+ u32 Address, unsigned ByteCount);
+
+int XQspiPs_SetSlaveSelect(XQspiPs *InstancePtr);
+
+void XQspiPs_SetStatusHandler(XQspiPs *InstancePtr, void *CallBackRef,
+ XQspiPs_StatusHandler FuncPtr);
+void XQspiPs_InterruptHandler(void *InstancePtr);
+
+/*
+ * Functions for selftest, in xqspips_selftest.c
+ */
+int XQspiPs_SelfTest(XQspiPs *InstancePtr);
+
+/*
+ * Functions for options, in xqspips_options.c
+ */
+s32 XQspiPs_SetOptions(XQspiPs *InstancePtr, u32 Options);
+u32 XQspiPs_GetOptions(XQspiPs *InstancePtr);
+
+s32 XQspiPs_SetClkPrescaler(XQspiPs *InstancePtr, u8 Prescaler);
+u8 XQspiPs_GetClkPrescaler(XQspiPs *InstancePtr);
+
+int XQspiPs_SetDelays(XQspiPs *InstancePtr, u8 DelayNss, u8 DelayBtwn,
+ u8 DelayAfter, u8 DelayInit);
+void XQspiPs_GetDelays(XQspiPs *InstancePtr, u8 *DelayNss, u8 *DelayBtwn,
+ u8 *DelayAfter, u8 *DelayInit);
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* end of protection macro */
+/** @} */
diff --git a/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/include/xqspips_hw.h b/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/include/xqspips_hw.h
new file mode 100644
index 0000000..33d17d9
--- /dev/null
+++ b/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/include/xqspips_hw.h
@@ -0,0 +1,419 @@
+/******************************************************************************
+*
+* Copyright (C) 2010 - 2019 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+* THE SOFTWARE.
+*
+*
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xqspips_hw.h
+* @addtogroup qspips_v3_6
+* @{
+*
+* This header file contains the identifiers and basic HW access driver
+* functions (or macros) that can be used to access the device. Other driver
+* functions are defined in xqspips.h.
+*
+* <pre>
+* MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ----- --- -------- -----------------------------------------------
+* 1.00 sdm 11/25/10 First release
+* 2.00a ka 07/25/12 Added a few register defines for CR 670297
+* and removed some defines of reserved fields for
+* CR 671468
+* Added define XQSPIPS_CR_HOLD_B_MASK for Holdb_dr
+* bit in Configuration register.
+* 2.01a sg 02/03/13 Added defines for DelayNss,Rx Watermark,Interrupts
+* which need write to clear. Removed Read zeros mask from
+* LQSPI Config register.
+* 2.03a hk 08/22/13 Added prototypes of API's for QSPI reset and
+* linear mode initialization for boot. Added related
+* constant definitions.
+* 3.1 hk 08/13/14 Changed definition of CR reset value masks to set/reset
+* required bits leaving reserved bits untouched. CR# 796813.
+* 3.2 sk 02/05/15 Add SLCR reset in abort function as a workaround because
+* controller does not update FIFO status flags as expected
+* when thresholds are used.
+* 3.6 akm 03/28/19 Fixed memory leak issue while reading from qspi.(CR#1016357)
+*
+* </pre>
+*
+******************************************************************************/
+#ifndef XQSPIPS_HW_H /* prevent circular inclusions */
+#define XQSPIPS_HW_H /* by using protection macros */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/***************************** Include Files *********************************/
+
+#include "xil_types.h"
+#include "xil_assert.h"
+#include "xil_io.h"
+#include "xparameters.h"
+
+/************************** Constant Definitions *****************************/
+
+/** @name Register Map
+ *
+ * Register offsets from the base address of an QSPI device.
+ * @{
+ */
+#define XQSPIPS_CR_OFFSET 0x00 /**< Configuration Register */
+#define XQSPIPS_SR_OFFSET 0x04 /**< Interrupt Status */
+#define XQSPIPS_IER_OFFSET 0x08 /**< Interrupt Enable */
+#define XQSPIPS_IDR_OFFSET 0x0c /**< Interrupt Disable */
+#define XQSPIPS_IMR_OFFSET 0x10 /**< Interrupt Enabled Mask */
+#define XQSPIPS_ER_OFFSET 0x14 /**< Enable/Disable Register */
+#define XQSPIPS_DR_OFFSET 0x18 /**< Delay Register */
+#define XQSPIPS_TXD_00_OFFSET 0x1C /**< Transmit 4-byte inst/data */
+#define XQSPIPS_RXD_OFFSET 0x20 /**< Data Receive Register */
+#define XQSPIPS_SICR_OFFSET 0x24 /**< Slave Idle Count */
+#define XQSPIPS_TXWR_OFFSET 0x28 /**< Transmit FIFO Watermark */
+#define XQSPIPS_RXWR_OFFSET 0x2C /**< Receive FIFO Watermark */
+#define XQSPIPS_GPIO_OFFSET 0x30 /**< GPIO Register */
+#define XQSPIPS_LPBK_DLY_ADJ_OFFSET 0x38 /**< Loopback Delay Adjust Reg */
+#define XQSPIPS_TXD_01_OFFSET 0x80 /**< Transmit 1-byte inst */
+#define XQSPIPS_TXD_10_OFFSET 0x84 /**< Transmit 2-byte inst */
+#define XQSPIPS_TXD_11_OFFSET 0x88 /**< Transmit 3-byte inst */
+#define XQSPIPS_LQSPI_CR_OFFSET 0xA0 /**< Linear QSPI config register */
+#define XQSPIPS_LQSPI_SR_OFFSET 0xA4 /**< Linear QSPI status register */
+#define XQSPIPS_MOD_ID_OFFSET 0xFC /**< Module ID register */
+
+/* @} */
+
+/** @name Configuration Register
+ *
+ * This register contains various control bits that
+ * affect the operation of the QSPI device. Read/Write.
+ * @{
+ */
+
+#define XQSPIPS_CR_IFMODE_MASK 0x80000000 /**< Flash mem interface mode */
+#define XQSPIPS_CR_ENDIAN_MASK 0x04000000 /**< Tx/Rx FIFO endianness */
+#define XQSPIPS_CR_MANSTRT_MASK 0x00010000 /**< Manual Transmission Start */
+#define XQSPIPS_CR_MANSTRTEN_MASK 0x00008000 /**< Manual Transmission Start
+ Enable */
+#define XQSPIPS_CR_SSFORCE_MASK 0x00004000 /**< Force Slave Select */
+#define XQSPIPS_CR_SSCTRL_MASK 0x00000400 /**< Slave Select Decode */
+#define XQSPIPS_CR_SSCTRL_SHIFT 10 /**< Slave Select Decode shift */
+#define XQSPIPS_CR_DATA_SZ_MASK 0x000000C0 /**< Size of word to be
+ transferred */
+#define XQSPIPS_CR_PRESC_MASK 0x00000038 /**< Prescaler Setting */
+#define XQSPIPS_CR_PRESC_SHIFT 3 /**< Prescaler shift */
+#define XQSPIPS_CR_PRESC_MAXIMUM 0x07 /**< Prescaler maximum value */
+
+#define XQSPIPS_CR_CPHA_MASK 0x00000004 /**< Phase Configuration */
+#define XQSPIPS_CR_CPOL_MASK 0x00000002 /**< Polarity Configuration */
+
+#define XQSPIPS_CR_MSTREN_MASK 0x00000001 /**< Master Mode Enable */
+
+#define XQSPIPS_CR_HOLD_B_MASK 0x00080000 /**< HOLD_B Pin Drive Enable */
+
+#define XQSPIPS_CR_REF_CLK_MASK 0x00000100 /**< Ref clk bit - should be 0 */
+
+/* Deselect the Slave select line and set the transfer size to 32 at reset */
+#define XQSPIPS_CR_RESET_MASK_SET XQSPIPS_CR_IFMODE_MASK | \
+ XQSPIPS_CR_SSCTRL_MASK | \
+ XQSPIPS_CR_DATA_SZ_MASK | \
+ XQSPIPS_CR_MSTREN_MASK | \
+ XQSPIPS_CR_SSFORCE_MASK | \
+ XQSPIPS_CR_HOLD_B_MASK
+#define XQSPIPS_CR_RESET_MASK_CLR XQSPIPS_CR_CPOL_MASK | \
+ XQSPIPS_CR_CPHA_MASK | \
+ XQSPIPS_CR_PRESC_MASK | \
+ XQSPIPS_CR_MANSTRTEN_MASK | \
+ XQSPIPS_CR_MANSTRT_MASK | \
+ XQSPIPS_CR_ENDIAN_MASK | \
+ XQSPIPS_CR_REF_CLK_MASK
+/* @} */
+
+
+/** @name QSPI Interrupt Registers
+ *
+ * <b>QSPI Status Register</b>
+ *
+ * This register holds the interrupt status flags for an QSPI device. Some
+ * of the flags are level triggered, which means that they are set as long
+ * as the interrupt condition exists. Other flags are edge triggered,
+ * which means they are set once the interrupt condition occurs and remain
+ * set until they are cleared by software. The interrupts are cleared by
+ * writing a '1' to the interrupt bit position in the Status Register.
+ * Read/Write.
+ *
+ * <b>QSPI Interrupt Enable Register</b>
+ *
+ * This register is used to enable chosen interrupts for an QSPI device.
+ * Writing a '1' to a bit in this register sets the corresponding bit in the
+ * QSPI Interrupt Mask register. Write only.
+ *
+ * <b>QSPI Interrupt Disable Register </b>
+ *
+ * This register is used to disable chosen interrupts for an QSPI device.
+ * Writing a '1' to a bit in this register clears the corresponding bit in the
+ * QSPI Interrupt Mask register. Write only.
+ *
+ * <b>QSPI Interrupt Mask Register</b>
+ *
+ * This register shows the enabled/disabled interrupts of an QSPI device.
+ * Read only.
+ *
+ * All four registers have the same bit definitions. They are only defined once
+ * for each of the Interrupt Enable Register, Interrupt Disable Register,
+ * Interrupt Mask Register, and Channel Interrupt Status Register
+ * @{
+ */
+
+#define XQSPIPS_IXR_TXUF_MASK 0x00000040 /**< QSPI Tx FIFO Underflow */
+#define XQSPIPS_IXR_RXFULL_MASK 0x00000020 /**< QSPI Rx FIFO Full */
+#define XQSPIPS_IXR_RXNEMPTY_MASK 0x00000010 /**< QSPI Rx FIFO Not Empty */
+#define XQSPIPS_IXR_TXFULL_MASK 0x00000008 /**< QSPI Tx FIFO Full */
+#define XQSPIPS_IXR_TXOW_MASK 0x00000004 /**< QSPI Tx FIFO Overwater */
+#define XQSPIPS_IXR_RXOVR_MASK 0x00000001 /**< QSPI Rx FIFO Overrun */
+#define XQSPIPS_IXR_DFLT_MASK 0x00000025 /**< QSPI default interrupts
+ mask */
+#define XQSPIPS_IXR_WR_TO_CLR_MASK 0x00000041 /**< Interrupts which
+ need write to clear */
+#define XQSPIPS_ISR_RESET_STATE 0x00000004 /**< Default to tx/rx empty */
+#define XQSPIPS_IXR_DISABLE_ALL 0x0000007D /**< Disable all interrupts */
+/* @} */
+
+
+/** @name Enable Register
+ *
+ * This register is used to enable or disable an QSPI device.
+ * Read/Write
+ * @{
+ */
+#define XQSPIPS_ER_ENABLE_MASK 0x00000001 /**< QSPI Enable Bit Mask */
+/* @} */
+
+
+/** @name Delay Register
+ *
+ * This register is used to program timing delays in
+ * slave mode. Read/Write
+ * @{
+ */
+#define XQSPIPS_DR_NSS_MASK 0xFF000000 /**< Delay to de-assert slave select
+ between two words mask */
+#define XQSPIPS_DR_NSS_SHIFT 24 /**< Delay to de-assert slave select
+ between two words shift */
+#define XQSPIPS_DR_BTWN_MASK 0x00FF0000 /**< Delay Between Transfers
+ mask */
+#define XQSPIPS_DR_BTWN_SHIFT 16 /**< Delay Between Transfers shift */
+#define XQSPIPS_DR_AFTER_MASK 0x0000FF00 /**< Delay After Transfers mask */
+#define XQSPIPS_DR_AFTER_SHIFT 8 /**< Delay After Transfers shift */
+#define XQSPIPS_DR_INIT_MASK 0x000000FF /**< Delay Initially mask */
+/* @} */
+
+/** @name Slave Idle Count Registers
+ *
+ * This register defines the number of pclk cycles the slave waits for a the
+ * QSPI clock to become stable in quiescent state before it can detect the start
+ * of the next transfer in CPHA = 1 mode.
+ * Read/Write
+ *
+ * @{
+ */
+#define XQSPIPS_SICR_MASK 0x000000FF /**< Slave Idle Count Mask */
+/* @} */
+
+
+/** @name Transmit FIFO Watermark Register
+ *
+ * This register defines the watermark setting for the Transmit FIFO.
+ *
+ * @{
+ */
+#define XQSPIPS_TXWR_MASK 0x0000003F /**< Transmit Watermark Mask */
+#define XQSPIPS_TXWR_RESET_VALUE 0x00000001 /**< Transmit Watermark
+ * register reset value */
+
+/* @} */
+
+/** @name Receive FIFO Watermark Register
+ *
+ * This register defines the watermark setting for the Receive FIFO.
+ *
+ * @{
+ */
+#define XQSPIPS_RXWR_MASK 0x0000003F /**< Receive Watermark Mask */
+#define XQSPIPS_RXWR_RESET_VALUE 0x00000001 /**< Receive Watermark
+ * register reset value */
+
+/* @} */
+
+/** @name FIFO Depth
+ *
+ * This macro provides the depth of transmit FIFO and receive FIFO.
+ *
+ * @{
+ */
+#define XQSPIPS_FIFO_DEPTH 63 /**< FIFO depth (words) */
+/* @} */
+
+
+/** @name Linear QSPI Configuration Register
+ *
+ * This register contains various control bits that
+ * affect the operation of the Linear QSPI controller. Read/Write.
+ *
+ * @{
+ */
+#define XQSPIPS_LQSPI_CR_LINEAR_MASK 0x80000000 /**< LQSPI mode enable */
+#define XQSPIPS_LQSPI_CR_TWO_MEM_MASK 0x40000000 /**< Both memories or one */
+#define XQSPIPS_LQSPI_CR_SEP_BUS_MASK 0x20000000 /**< Separate memory bus */
+#define XQSPIPS_LQSPI_CR_U_PAGE_MASK 0x10000000 /**< Upper memory page */
+#define XQSPIPS_LQSPI_CR_MODE_EN_MASK 0x02000000 /**< Enable mode bits */
+#define XQSPIPS_LQSPI_CR_MODE_ON_MASK 0x01000000 /**< Mode on */
+#define XQSPIPS_LQSPI_CR_MODE_BITS_MASK 0x00FF0000 /**< Mode value for dual I/O
+ or quad I/O */
+#define XQSPIPS_LQSPI_CR_DUMMY_MASK 0x00000700 /**< Number of dummy bytes
+ between addr and return
+ read data */
+#define XQSPIPS_LQSPI_CR_INST_MASK 0x000000FF /**< Read instr code */
+#define XQSPIPS_LQSPI_CR_RST_STATE 0x8000016B /**< Default CR value */
+/* @} */
+
+/** @name Linear QSPI Status Register
+ *
+ * This register contains various status bits of the Linear QSPI controller.
+ * Read/Write.
+ *
+ * @{
+ */
+#define XQSPIPS_LQSPI_SR_D_FSM_ERR_MASK 0x00000004 /**< AXI Data FSM Error
+ received */
+#define XQSPIPS_LQSPI_SR_WR_RECVD_MASK 0x00000002 /**< AXI write command
+ received */
+/* @} */
+
+
+/** @name Loopback Delay Adjust Register
+ *
+ * This register contains various bit masks of Loopback Delay Adjust Register.
+ *
+ * @{
+ */
+
+#define XQSPIPS_LPBK_DLY_ADJ_USE_LPBK_MASK 0x00000020 /**< Loopback Bit */
+
+/* @} */
+
+
+/** @name SLCR Register
+ *
+ * Register offsets from SLCR base address.
+ *
+ * @{
+ */
+
+#define SLCR_LOCK 0x00000004 /**< SLCR Write Protection Lock */
+#define SLCR_UNLOCK 0x00000008 /**< SLCR Write Protection Unlock */
+#define LQSPI_RST_CTRL 0x00000230 /**< Quad SPI Software Reset Control */
+#define SLCR_LOCKSTA 0x0000000C /**< SLCR Write Protection status */
+
+/* @} */
+
+
+/** @name SLCR Register
+ *
+ * Bit Masks of above SLCR Registers .
+ *
+ * @{
+ */
+
+#ifndef XPAR_XSLCR_0_BASEADDR
+#define XPAR_XSLCR_0_BASEADDR 0xF8000000
+#endif
+#define SLCR_LOCK_MASK 0x767B /**< Write Protection Lock mask*/
+#define SLCR_UNLOCK_MASK 0xDF0D /**< SLCR Write Protection Unlock */
+#define LQSPI_RST_CTRL_MASK 0x3 /**< Quad SPI Software Reset Control */
+
+/* @} */
+
+
+/**************************** Type Definitions *******************************/
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+#define XQspiPs_In32 Xil_In32
+#define XQspiPs_Out32 Xil_Out32
+#define XQSPIPS_DUMMY_TX_DATA 0xFFFFFFFF
+
+/****************************************************************************/
+/**
+* Read a register.
+*
+* @param BaseAddress contains the base address of the device.
+* @param RegOffset contains the offset from the 1st register of the
+* device to the target register.
+*
+* @return The value read from the register.
+*
+* @note C-Style signature:
+* u32 XQspiPs_ReadReg(u32 BaseAddress. int RegOffset)
+*
+******************************************************************************/
+#define XQspiPs_ReadReg(BaseAddress, RegOffset) \
+ XQspiPs_In32((BaseAddress) + (RegOffset))
+
+/***************************************************************************/
+/**
+* Write to a register.
+*
+* @param BaseAddress contains the base address of the device.
+* @param RegOffset contains the offset from the 1st register of the
+* device to target register.
+* @param RegisterValue is the value to be written to the register.
+*
+* @return None.
+*
+* @note C-Style signature:
+* void XQspiPs_WriteReg(u32 BaseAddress, int RegOffset,
+* u32 RegisterValue)
+*
+******************************************************************************/
+#define XQspiPs_WriteReg(BaseAddress, RegOffset, RegisterValue) \
+ XQspiPs_Out32((BaseAddress) + (RegOffset), (RegisterValue))
+
+/************************** Function Prototypes ******************************/
+
+/*
+ * Functions implemented in xqspips_hw.c
+ */
+void XQspiPs_ResetHw(u32 BaseAddress);
+void XQspiPs_LinearInit(u32 BaseAddress);
+
+/************************** Variable Definitions *****************************/
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* end of protection macro */
+/** @} */
diff --git a/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/include/xreg_cortexa9.h b/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/include/xreg_cortexa9.h
new file mode 100644
index 0000000..7638ca1
--- /dev/null
+++ b/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/include/xreg_cortexa9.h
@@ -0,0 +1,585 @@
+/******************************************************************************
+*
+* Copyright (C) 2009 - 2015 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+* THE SOFTWARE.
+*
+*
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xreg_cortexa9.h
+*
+* This header file contains definitions for using inline assembler code. It is
+* written specifically for the GNU, ARMCC compiler.
+*
+* All of the ARM Cortex A9 GPRs, SPRs, and Debug Registers are defined along
+* with the positions of the bits within the registers.
+*
+* <pre>
+* MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ----- -------- -------- -----------------------------------------------
+* 1.00a ecm/sdm 10/20/09 First release
+* </pre>
+*
+******************************************************************************/
+#ifndef XREG_CORTEXA9_H
+#define XREG_CORTEXA9_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif /* __cplusplus */
+
+/* GPRs */
+#define XREG_GPR0 r0
+#define XREG_GPR1 r1
+#define XREG_GPR2 r2
+#define XREG_GPR3 r3
+#define XREG_GPR4 r4
+#define XREG_GPR5 r5
+#define XREG_GPR6 r6
+#define XREG_GPR7 r7
+#define XREG_GPR8 r8
+#define XREG_GPR9 r9
+#define XREG_GPR10 r10
+#define XREG_GPR11 r11
+#define XREG_GPR12 r12
+#define XREG_GPR13 r13
+#define XREG_GPR14 r14
+#define XREG_GPR15 r15
+#define XREG_CPSR cpsr
+
+/* Coprocessor number defines */
+#define XREG_CP0 0
+#define XREG_CP1 1
+#define XREG_CP2 2
+#define XREG_CP3 3
+#define XREG_CP4 4
+#define XREG_CP5 5
+#define XREG_CP6 6
+#define XREG_CP7 7
+#define XREG_CP8 8
+#define XREG_CP9 9
+#define XREG_CP10 10
+#define XREG_CP11 11
+#define XREG_CP12 12
+#define XREG_CP13 13
+#define XREG_CP14 14
+#define XREG_CP15 15
+
+/* Coprocessor control register defines */
+#define XREG_CR0 cr0
+#define XREG_CR1 cr1
+#define XREG_CR2 cr2
+#define XREG_CR3 cr3
+#define XREG_CR4 cr4
+#define XREG_CR5 cr5
+#define XREG_CR6 cr6
+#define XREG_CR7 cr7
+#define XREG_CR8 cr8
+#define XREG_CR9 cr9
+#define XREG_CR10 cr10
+#define XREG_CR11 cr11
+#define XREG_CR12 cr12
+#define XREG_CR13 cr13
+#define XREG_CR14 cr14
+#define XREG_CR15 cr15
+
+/* Current Processor Status Register (CPSR) Bits */
+#define XREG_CPSR_THUMB_MODE 0x20
+#define XREG_CPSR_MODE_BITS 0x1F
+#define XREG_CPSR_SYSTEM_MODE 0x1F
+#define XREG_CPSR_UNDEFINED_MODE 0x1B
+#define XREG_CPSR_DATA_ABORT_MODE 0x17
+#define XREG_CPSR_SVC_MODE 0x13
+#define XREG_CPSR_IRQ_MODE 0x12
+#define XREG_CPSR_FIQ_MODE 0x11
+#define XREG_CPSR_USER_MODE 0x10
+
+#define XREG_CPSR_IRQ_ENABLE 0x80
+#define XREG_CPSR_FIQ_ENABLE 0x40
+
+#define XREG_CPSR_N_BIT 0x80000000
+#define XREG_CPSR_Z_BIT 0x40000000
+#define XREG_CPSR_C_BIT 0x20000000
+#define XREG_CPSR_V_BIT 0x10000000
+
+
+/* CP15 defines */
+#if defined (__GNUC__) || defined (__ICCARM__)
+/* C0 Register defines */
+#define XREG_CP15_MAIN_ID "p15, 0, %0, c0, c0, 0"
+#define XREG_CP15_CACHE_TYPE "p15, 0, %0, c0, c0, 1"
+#define XREG_CP15_TCM_TYPE "p15, 0, %0, c0, c0, 2"
+#define XREG_CP15_TLB_TYPE "p15, 0, %0, c0, c0, 3"
+#define XREG_CP15_MULTI_PROC_AFFINITY "p15, 0, %0, c0, c0, 5"
+
+#define XREG_CP15_PROC_FEATURE_0 "p15, 0, %0, c0, c1, 0"
+#define XREG_CP15_PROC_FEATURE_1 "p15, 0, %0, c0, c1, 1"
+#define XREG_CP15_DEBUG_FEATURE_0 "p15, 0, %0, c0, c1, 2"
+#define XREG_CP15_MEMORY_FEATURE_0 "p15, 0, %0, c0, c1, 4"
+#define XREG_CP15_MEMORY_FEATURE_1 "p15, 0, %0, c0, c1, 5"
+#define XREG_CP15_MEMORY_FEATURE_2 "p15, 0, %0, c0, c1, 6"
+#define XREG_CP15_MEMORY_FEATURE_3 "p15, 0, %0, c0, c1, 7"
+
+#define XREG_CP15_INST_FEATURE_0 "p15, 0, %0, c0, c2, 0"
+#define XREG_CP15_INST_FEATURE_1 "p15, 0, %0, c0, c2, 1"
+#define XREG_CP15_INST_FEATURE_2 "p15, 0, %0, c0, c2, 2"
+#define XREG_CP15_INST_FEATURE_3 "p15, 0, %0, c0, c2, 3"
+#define XREG_CP15_INST_FEATURE_4 "p15, 0, %0, c0, c2, 4"
+
+#define XREG_CP15_CACHE_SIZE_ID "p15, 1, %0, c0, c0, 0"
+#define XREG_CP15_CACHE_LEVEL_ID "p15, 1, %0, c0, c0, 1"
+#define XREG_CP15_AUXILARY_ID "p15, 1, %0, c0, c0, 7"
+
+#define XREG_CP15_CACHE_SIZE_SEL "p15, 2, %0, c0, c0, 0"
+
+/* C1 Register Defines */
+#define XREG_CP15_SYS_CONTROL "p15, 0, %0, c1, c0, 0"
+#define XREG_CP15_AUX_CONTROL "p15, 0, %0, c1, c0, 1"
+#define XREG_CP15_CP_ACCESS_CONTROL "p15, 0, %0, c1, c0, 2"
+
+#define XREG_CP15_SECURE_CONFIG "p15, 0, %0, c1, c1, 0"
+#define XREG_CP15_SECURE_DEBUG_ENABLE "p15, 0, %0, c1, c1, 1"
+#define XREG_CP15_NS_ACCESS_CONTROL "p15, 0, %0, c1, c1, 2"
+#define XREG_CP15_VIRTUAL_CONTROL "p15, 0, %0, c1, c1, 3"
+
+#else /* RVCT */
+/* C0 Register defines */
+#define XREG_CP15_MAIN_ID "cp15:0:c0:c0:0"
+#define XREG_CP15_CACHE_TYPE "cp15:0:c0:c0:1"
+#define XREG_CP15_TCM_TYPE "cp15:0:c0:c0:2"
+#define XREG_CP15_TLB_TYPE "cp15:0:c0:c0:3"
+#define XREG_CP15_MULTI_PROC_AFFINITY "cp15:0:c0:c0:5"
+
+#define XREG_CP15_PROC_FEATURE_0 "cp15:0:c0:c1:0"
+#define XREG_CP15_PROC_FEATURE_1 "cp15:0:c0:c1:1"
+#define XREG_CP15_DEBUG_FEATURE_0 "cp15:0:c0:c1:2"
+#define XREG_CP15_MEMORY_FEATURE_0 "cp15:0:c0:c1:4"
+#define XREG_CP15_MEMORY_FEATURE_1 "cp15:0:c0:c1:5"
+#define XREG_CP15_MEMORY_FEATURE_2 "cp15:0:c0:c1:6"
+#define XREG_CP15_MEMORY_FEATURE_3 "cp15:0:c0:c1:7"
+
+#define XREG_CP15_INST_FEATURE_0 "cp15:0:c0:c2:0"
+#define XREG_CP15_INST_FEATURE_1 "cp15:0:c0:c2:1"
+#define XREG_CP15_INST_FEATURE_2 "cp15:0:c0:c2:2"
+#define XREG_CP15_INST_FEATURE_3 "cp15:0:c0:c2:3"
+#define XREG_CP15_INST_FEATURE_4 "cp15:0:c0:c2:4"
+
+#define XREG_CP15_CACHE_SIZE_ID "cp15:1:c0:c0:0"
+#define XREG_CP15_CACHE_LEVEL_ID "cp15:1:c0:c0:1"
+#define XREG_CP15_AUXILARY_ID "cp15:1:c0:c0:7"
+
+#define XREG_CP15_CACHE_SIZE_SEL "cp15:2:c0:c0:0"
+
+/* C1 Register Defines */
+#define XREG_CP15_SYS_CONTROL "cp15:0:c1:c0:0"
+#define XREG_CP15_AUX_CONTROL "cp15:0:c1:c0:1"
+#define XREG_CP15_CP_ACCESS_CONTROL "cp15:0:c1:c0:2"
+
+#define XREG_CP15_SECURE_CONFIG "cp15:0:c1:c1:0"
+#define XREG_CP15_SECURE_DEBUG_ENABLE "cp15:0:c1:c1:1"
+#define XREG_CP15_NS_ACCESS_CONTROL "cp15:0:c1:c1:2"
+#define XREG_CP15_VIRTUAL_CONTROL "cp15:0:c1:c1:3"
+#endif
+
+/* XREG_CP15_CONTROL bit defines */
+#define XREG_CP15_CONTROL_TE_BIT 0x40000000U
+#define XREG_CP15_CONTROL_AFE_BIT 0x20000000U
+#define XREG_CP15_CONTROL_TRE_BIT 0x10000000U
+#define XREG_CP15_CONTROL_NMFI_BIT 0x08000000U
+#define XREG_CP15_CONTROL_EE_BIT 0x02000000U
+#define XREG_CP15_CONTROL_HA_BIT 0x00020000U
+#define XREG_CP15_CONTROL_RR_BIT 0x00004000U
+#define XREG_CP15_CONTROL_V_BIT 0x00002000U
+#define XREG_CP15_CONTROL_I_BIT 0x00001000U
+#define XREG_CP15_CONTROL_Z_BIT 0x00000800U
+#define XREG_CP15_CONTROL_SW_BIT 0x00000400U
+#define XREG_CP15_CONTROL_B_BIT 0x00000080U
+#define XREG_CP15_CONTROL_C_BIT 0x00000004U
+#define XREG_CP15_CONTROL_A_BIT 0x00000002U
+#define XREG_CP15_CONTROL_M_BIT 0x00000001U
+
+#if defined (__GNUC__) || defined (__ICCARM__)
+/* C2 Register Defines */
+#define XREG_CP15_TTBR0 "p15, 0, %0, c2, c0, 0"
+#define XREG_CP15_TTBR1 "p15, 0, %0, c2, c0, 1"
+#define XREG_CP15_TTB_CONTROL "p15, 0, %0, c2, c0, 2"
+
+/* C3 Register Defines */
+#define XREG_CP15_DOMAIN_ACCESS_CTRL "p15, 0, %0, c3, c0, 0"
+
+/* C4 Register Defines */
+/* Not Used */
+
+/* C5 Register Defines */
+#define XREG_CP15_DATA_FAULT_STATUS "p15, 0, %0, c5, c0, 0"
+#define XREG_CP15_INST_FAULT_STATUS "p15, 0, %0, c5, c0, 1"
+
+#define XREG_CP15_AUX_DATA_FAULT_STATUS "p15, 0, %0, c5, c1, 0"
+#define XREG_CP15_AUX_INST_FAULT_STATUS "p15, 0, %0, c5, c1, 1"
+
+/* C6 Register Defines */
+#define XREG_CP15_DATA_FAULT_ADDRESS "p15, 0, %0, c6, c0, 0"
+#define XREG_CP15_INST_FAULT_ADDRESS "p15, 0, %0, c6, c0, 2"
+
+/* C7 Register Defines */
+#define XREG_CP15_NOP "p15, 0, %0, c7, c0, 4"
+
+#define XREG_CP15_INVAL_IC_POU_IS "p15, 0, %0, c7, c1, 0"
+#define XREG_CP15_INVAL_BRANCH_ARRAY_IS "p15, 0, %0, c7, c1, 6"
+
+#define XREG_CP15_PHYS_ADDR "p15, 0, %0, c7, c4, 0"
+
+#define XREG_CP15_INVAL_IC_POU "p15, 0, %0, c7, c5, 0"
+#define XREG_CP15_INVAL_IC_LINE_MVA_POU "p15, 0, %0, c7, c5, 1"
+
+/* The CP15 register access below has been deprecated in favor of the new
+ * isb instruction in Cortex A9.
+ */
+#define XREG_CP15_INST_SYNC_BARRIER "p15, 0, %0, c7, c5, 4"
+#define XREG_CP15_INVAL_BRANCH_ARRAY "p15, 0, %0, c7, c5, 6"
+
+#define XREG_CP15_INVAL_DC_LINE_MVA_POC "p15, 0, %0, c7, c6, 1"
+#define XREG_CP15_INVAL_DC_LINE_SW "p15, 0, %0, c7, c6, 2"
+
+#define XREG_CP15_VA_TO_PA_CURRENT_0 "p15, 0, %0, c7, c8, 0"
+#define XREG_CP15_VA_TO_PA_CURRENT_1 "p15, 0, %0, c7, c8, 1"
+#define XREG_CP15_VA_TO_PA_CURRENT_2 "p15, 0, %0, c7, c8, 2"
+#define XREG_CP15_VA_TO_PA_CURRENT_3 "p15, 0, %0, c7, c8, 3"
+
+#define XREG_CP15_VA_TO_PA_OTHER_0 "p15, 0, %0, c7, c8, 4"
+#define XREG_CP15_VA_TO_PA_OTHER_1 "p15, 0, %0, c7, c8, 5"
+#define XREG_CP15_VA_TO_PA_OTHER_2 "p15, 0, %0, c7, c8, 6"
+#define XREG_CP15_VA_TO_PA_OTHER_3 "p15, 0, %0, c7, c8, 7"
+
+#define XREG_CP15_CLEAN_DC_LINE_MVA_POC "p15, 0, %0, c7, c10, 1"
+#define XREG_CP15_CLEAN_DC_LINE_SW "p15, 0, %0, c7, c10, 2"
+
+/* The next two CP15 register accesses below have been deprecated in favor
+ * of the new dsb and dmb instructions in Cortex A9.
+ */
+#define XREG_CP15_DATA_SYNC_BARRIER "p15, 0, %0, c7, c10, 4"
+#define XREG_CP15_DATA_MEMORY_BARRIER "p15, 0, %0, c7, c10, 5"
+
+#define XREG_CP15_CLEAN_DC_LINE_MVA_POU "p15, 0, %0, c7, c11, 1"
+
+#define XREG_CP15_NOP2 "p15, 0, %0, c7, c13, 1"
+
+#define XREG_CP15_CLEAN_INVAL_DC_LINE_MVA_POC "p15, 0, %0, c7, c14, 1"
+#define XREG_CP15_CLEAN_INVAL_DC_LINE_SW "p15, 0, %0, c7, c14, 2"
+
+/* C8 Register Defines */
+#define XREG_CP15_INVAL_TLB_IS "p15, 0, %0, c8, c3, 0"
+#define XREG_CP15_INVAL_TLB_MVA_IS "p15, 0, %0, c8, c3, 1"
+#define XREG_CP15_INVAL_TLB_ASID_IS "p15, 0, %0, c8, c3, 2"
+#define XREG_CP15_INVAL_TLB_MVA_ASID_IS "p15, 0, %0, c8, c3, 3"
+
+#define XREG_CP15_INVAL_ITLB_UNLOCKED "p15, 0, %0, c8, c5, 0"
+#define XREG_CP15_INVAL_ITLB_MVA "p15, 0, %0, c8, c5, 1"
+#define XREG_CP15_INVAL_ITLB_ASID "p15, 0, %0, c8, c5, 2"
+
+#define XREG_CP15_INVAL_DTLB_UNLOCKED "p15, 0, %0, c8, c6, 0"
+#define XREG_CP15_INVAL_DTLB_MVA "p15, 0, %0, c8, c6, 1"
+#define XREG_CP15_INVAL_DTLB_ASID "p15, 0, %0, c8, c6, 2"
+
+#define XREG_CP15_INVAL_UTLB_UNLOCKED "p15, 0, %0, c8, c7, 0"
+#define XREG_CP15_INVAL_UTLB_MVA "p15, 0, %0, c8, c7, 1"
+#define XREG_CP15_INVAL_UTLB_ASID "p15, 0, %0, c8, c7, 2"
+#define XREG_CP15_INVAL_UTLB_MVA_ASID "p15, 0, %0, c8, c7, 3"
+
+/* C9 Register Defines */
+#define XREG_CP15_PERF_MONITOR_CTRL "p15, 0, %0, c9, c12, 0"
+#define XREG_CP15_COUNT_ENABLE_SET "p15, 0, %0, c9, c12, 1"
+#define XREG_CP15_COUNT_ENABLE_CLR "p15, 0, %0, c9, c12, 2"
+#define XREG_CP15_V_FLAG_STATUS "p15, 0, %0, c9, c12, 3"
+#define XREG_CP15_SW_INC "p15, 0, %0, c9, c12, 4"
+#define XREG_CP15_EVENT_CNTR_SEL "p15, 0, %0, c9, c12, 5"
+
+#define XREG_CP15_PERF_CYCLE_COUNTER "p15, 0, %0, c9, c13, 0"
+#define XREG_CP15_EVENT_TYPE_SEL "p15, 0, %0, c9, c13, 1"
+#define XREG_CP15_PERF_MONITOR_COUNT "p15, 0, %0, c9, c13, 2"
+
+#define XREG_CP15_USER_ENABLE "p15, 0, %0, c9, c14, 0"
+#define XREG_CP15_INTR_ENABLE_SET "p15, 0, %0, c9, c14, 1"
+#define XREG_CP15_INTR_ENABLE_CLR "p15, 0, %0, c9, c14, 2"
+
+/* C10 Register Defines */
+#define XREG_CP15_TLB_LOCKDWN "p15, 0, %0, c10, c0, 0"
+
+#define XREG_CP15_PRI_MEM_REMAP "p15, 0, %0, c10, c2, 0"
+#define XREG_CP15_NORM_MEM_REMAP "p15, 0, %0, c10, c2, 1"
+
+/* C11 Register Defines */
+/* Not used */
+
+/* C12 Register Defines */
+#define XREG_CP15_VEC_BASE_ADDR "p15, 0, %0, c12, c0, 0"
+#define XREG_CP15_MONITOR_VEC_BASE_ADDR "p15, 0, %0, c12, c0, 1"
+
+#define XREG_CP15_INTERRUPT_STATUS "p15, 0, %0, c12, c1, 0"
+#define XREG_CP15_VIRTUALIZATION_INTR "p15, 0, %0, c12, c1, 1"
+
+/* C13 Register Defines */
+#define XREG_CP15_CONTEXT_ID "p15, 0, %0, c13, c0, 1"
+#define USER_RW_THREAD_PID "p15, 0, %0, c13, c0, 2"
+#define USER_RO_THREAD_PID "p15, 0, %0, c13, c0, 3"
+#define USER_PRIV_THREAD_PID "p15, 0, %0, c13, c0, 4"
+
+/* C14 Register Defines */
+/* not used */
+
+/* C15 Register Defines */
+#define XREG_CP15_POWER_CTRL "p15, 0, %0, c15, c0, 0"
+#define XREG_CP15_CONFIG_BASE_ADDR "p15, 4, %0, c15, c0, 0"
+
+#define XREG_CP15_READ_TLB_ENTRY "p15, 5, %0, c15, c4, 2"
+#define XREG_CP15_WRITE_TLB_ENTRY "p15, 5, %0, c15, c4, 4"
+
+#define XREG_CP15_MAIN_TLB_VA "p15, 5, %0, c15, c5, 2"
+
+#define XREG_CP15_MAIN_TLB_PA "p15, 5, %0, c15, c6, 2"
+
+#define XREG_CP15_MAIN_TLB_ATTR "p15, 5, %0, c15, c7, 2"
+
+#else
+/* C2 Register Defines */
+#define XREG_CP15_TTBR0 "cp15:0:c2:c0:0"
+#define XREG_CP15_TTBR1 "cp15:0:c2:c0:1"
+#define XREG_CP15_TTB_CONTROL "cp15:0:c2:c0:2"
+
+/* C3 Register Defines */
+#define XREG_CP15_DOMAIN_ACCESS_CTRL "cp15:0:c3:c0:0"
+
+/* C4 Register Defines */
+/* Not Used */
+
+/* C5 Register Defines */
+#define XREG_CP15_DATA_FAULT_STATUS "cp15:0:c5:c0:0"
+#define XREG_CP15_INST_FAULT_STATUS "cp15:0:c5:c0:1"
+
+#define XREG_CP15_AUX_DATA_FAULT_STATUS "cp15:0:c5:c1:0"
+#define XREG_CP15_AUX_INST_FAULT_STATUS "cp15:0:c5:c1:1"
+
+/* C6 Register Defines */
+#define XREG_CP15_DATA_FAULT_ADDRESS "cp15:0:c6:c0:0"
+#define XREG_CP15_INST_FAULT_ADDRESS "cp15:0:c6:c0:2"
+
+/* C7 Register Defines */
+#define XREG_CP15_NOP "cp15:0:c7:c0:4"
+
+#define XREG_CP15_INVAL_IC_POU_IS "cp15:0:c7:c1:0"
+#define XREG_CP15_INVAL_BRANCH_ARRAY_IS "cp15:0:c7:c1:6"
+
+#define XREG_CP15_PHYS_ADDR "cp15:0:c7:c4:0"
+
+#define XREG_CP15_INVAL_IC_POU "cp15:0:c7:c5:0"
+#define XREG_CP15_INVAL_IC_LINE_MVA_POU "cp15:0:c7:c5:1"
+
+/* The CP15 register access below has been deprecated in favor of the new
+ * isb instruction in Cortex A9.
+ */
+#define XREG_CP15_INST_SYNC_BARRIER "cp15:0:c7:c5:4"
+#define XREG_CP15_INVAL_BRANCH_ARRAY "cp15:0:c7:c5:6"
+
+#define XREG_CP15_INVAL_DC_LINE_MVA_POC "cp15:0:c7:c6:1"
+#define XREG_CP15_INVAL_DC_LINE_SW "cp15:0:c7:c6:2"
+
+#define XREG_CP15_VA_TO_PA_CURRENT_0 "cp15:0:c7:c8:0"
+#define XREG_CP15_VA_TO_PA_CURRENT_1 "cp15:0:c7:c8:1"
+#define XREG_CP15_VA_TO_PA_CURRENT_2 "cp15:0:c7:c8:2"
+#define XREG_CP15_VA_TO_PA_CURRENT_3 "cp15:0:c7:c8:3"
+
+#define XREG_CP15_VA_TO_PA_OTHER_0 "cp15:0:c7:c8:4"
+#define XREG_CP15_VA_TO_PA_OTHER_1 "cp15:0:c7:c8:5"
+#define XREG_CP15_VA_TO_PA_OTHER_2 "cp15:0:c7:c8:6"
+#define XREG_CP15_VA_TO_PA_OTHER_3 "cp15:0:c7:c8:7"
+
+#define XREG_CP15_CLEAN_DC_LINE_MVA_POC "cp15:0:c7:c10:1"
+#define XREG_CP15_CLEAN_DC_LINE_SW "cp15:0:c7:c10:2"
+
+/* The next two CP15 register accesses below have been deprecated in favor
+ * of the new dsb and dmb instructions in Cortex A9.
+ */
+#define XREG_CP15_DATA_SYNC_BARRIER "cp15:0:c7:c10:4"
+#define XREG_CP15_DATA_MEMORY_BARRIER "cp15:0:c7:c10:5"
+
+#define XREG_CP15_CLEAN_DC_LINE_MVA_POU "cp15:0:c7:c11:1"
+
+#define XREG_CP15_NOP2 "cp15:0:c7:c13:1"
+
+#define XREG_CP15_CLEAN_INVAL_DC_LINE_MVA_POC "cp15:0:c7:c14:1"
+#define XREG_CP15_CLEAN_INVAL_DC_LINE_SW "cp15:0:c7:c14:2"
+
+/* C8 Register Defines */
+#define XREG_CP15_INVAL_TLB_IS "cp15:0:c8:c3:0"
+#define XREG_CP15_INVAL_TLB_MVA_IS "cp15:0:c8:c3:1"
+#define XREG_CP15_INVAL_TLB_ASID_IS "cp15:0:c8:c3:2"
+#define XREG_CP15_INVAL_TLB_MVA_ASID_IS "cp15:0:c8:c3:3"
+
+#define XREG_CP15_INVAL_ITLB_UNLOCKED "cp15:0:c8:c5:0"
+#define XREG_CP15_INVAL_ITLB_MVA "cp15:0:c8:c5:1"
+#define XREG_CP15_INVAL_ITLB_ASID "cp15:0:c8:c5:2"
+
+#define XREG_CP15_INVAL_DTLB_UNLOCKED "cp15:0:c8:c6:0"
+#define XREG_CP15_INVAL_DTLB_MVA "cp15:0:c8:c6:1"
+#define XREG_CP15_INVAL_DTLB_ASID "cp15:0:c8:c6:2"
+
+#define XREG_CP15_INVAL_UTLB_UNLOCKED "cp15:0:c8:c7:0"
+#define XREG_CP15_INVAL_UTLB_MVA "cp15:0:c8:c7:1"
+#define XREG_CP15_INVAL_UTLB_ASID "cp15:0:c8:c7:2"
+#define XREG_CP15_INVAL_UTLB_MVA_ASID "cp15:0:c8:c7:3"
+
+/* C9 Register Defines */
+#define XREG_CP15_PERF_MONITOR_CTRL "cp15:0:c9:c12:0"
+#define XREG_CP15_COUNT_ENABLE_SET "cp15:0:c9:c12:1"
+#define XREG_CP15_COUNT_ENABLE_CLR "cp15:0:c9:c12:2"
+#define XREG_CP15_V_FLAG_STATUS "cp15:0:c9:c12:3"
+#define XREG_CP15_SW_INC "cp15:0:c9:c12:4"
+#define XREG_CP15_EVENT_CNTR_SEL "cp15:0:c9:c12:5"
+
+#define XREG_CP15_PERF_CYCLE_COUNTER "cp15:0:c9:c13:0"
+#define XREG_CP15_EVENT_TYPE_SEL "cp15:0:c9:c13:1"
+#define XREG_CP15_PERF_MONITOR_COUNT "cp15:0:c9:c13:2"
+
+#define XREG_CP15_USER_ENABLE "cp15:0:c9:c14:0"
+#define XREG_CP15_INTR_ENABLE_SET "cp15:0:c9:c14:1"
+#define XREG_CP15_INTR_ENABLE_CLR "cp15:0:c9:c14:2"
+
+/* C10 Register Defines */
+#define XREG_CP15_TLB_LOCKDWN "cp15:0:c10:c0:0"
+
+#define XREG_CP15_PRI_MEM_REMAP "cp15:0:c10:c2:0"
+#define XREG_CP15_NORM_MEM_REMAP "cp15:0:c10:c2:1"
+
+/* C11 Register Defines */
+/* Not used */
+
+/* C12 Register Defines */
+#define XREG_CP15_VEC_BASE_ADDR "cp15:0:c12:c0:0"
+#define XREG_CP15_MONITOR_VEC_BASE_ADDR "cp15:0:c12:c0:1"
+
+#define XREG_CP15_INTERRUPT_STATUS "cp15:0:c12:c1:0"
+#define XREG_CP15_VIRTUALIZATION_INTR "cp15:0:c12:c1:1"
+
+/* C13 Register Defines */
+#define XREG_CP15_CONTEXT_ID "cp15:0:c13:c0:1"
+#define USER_RW_THREAD_PID "cp15:0:c13:c0:2"
+#define USER_RO_THREAD_PID "cp15:0:c13:c0:3"
+#define USER_PRIV_THREAD_PID "cp15:0:c13:c0:4"
+
+/* C14 Register Defines */
+/* not used */
+
+/* C15 Register Defines */
+#define XREG_CP15_POWER_CTRL "cp15:0:c15:c0:0"
+#define XREG_CP15_CONFIG_BASE_ADDR "cp15:4:c15:c0:0"
+
+#define XREG_CP15_READ_TLB_ENTRY "cp15:5:c15:c4:2"
+#define XREG_CP15_WRITE_TLB_ENTRY "cp15:5:c15:c4:4"
+
+#define XREG_CP15_MAIN_TLB_VA "cp15:5:c15:c5:2"
+
+#define XREG_CP15_MAIN_TLB_PA "cp15:5:c15:c6:2"
+
+#define XREG_CP15_MAIN_TLB_ATTR "cp15:5:c15:c7:2"
+#endif
+
+
+/* MPE register definitions */
+#define XREG_FPSID c0
+#define XREG_FPSCR c1
+#define XREG_MVFR1 c6
+#define XREG_MVFR0 c7
+#define XREG_FPEXC c8
+#define XREG_FPINST c9
+#define XREG_FPINST2 c10
+
+/* FPSID bits */
+#define XREG_FPSID_IMPLEMENTER_BIT (24)
+#define XREG_FPSID_IMPLEMENTER_MASK (0xFF << FPSID_IMPLEMENTER_BIT)
+#define XREG_FPSID_SOFTWARE (1<<23)
+#define XREG_FPSID_ARCH_BIT (16)
+#define XREG_FPSID_ARCH_MASK (0xF << FPSID_ARCH_BIT)
+#define XREG_FPSID_PART_BIT (8)
+#define XREG_FPSID_PART_MASK (0xFF << FPSID_PART_BIT)
+#define XREG_FPSID_VARIANT_BIT (4)
+#define XREG_FPSID_VARIANT_MASK (0xF << FPSID_VARIANT_BIT)
+#define XREG_FPSID_REV_BIT (0)
+#define XREG_FPSID_REV_MASK (0xF << FPSID_REV_BIT)
+
+/* FPSCR bits */
+#define XREG_FPSCR_N_BIT (1 << 31)
+#define XREG_FPSCR_Z_BIT (1 << 30)
+#define XREG_FPSCR_C_BIT (1 << 29)
+#define XREG_FPSCR_V_BIT (1 << 28)
+#define XREG_FPSCR_QC (1 << 27)
+#define XREG_FPSCR_AHP (1 << 26)
+#define XREG_FPSCR_DEFAULT_NAN (1 << 25)
+#define XREG_FPSCR_FLUSHTOZERO (1 << 24)
+#define XREG_FPSCR_ROUND_NEAREST (0 << 22)
+#define XREG_FPSCR_ROUND_PLUSINF (1 << 22)
+#define XREG_FPSCR_ROUND_MINUSINF (2 << 22)
+#define XREG_FPSCR_ROUND_TOZERO (3 << 22)
+#define XREG_FPSCR_RMODE_BIT (22)
+#define XREG_FPSCR_RMODE_MASK (3 << FPSCR_RMODE_BIT)
+#define XREG_FPSCR_STRIDE_BIT (20)
+#define XREG_FPSCR_STRIDE_MASK (3 << FPSCR_STRIDE_BIT)
+#define XREG_FPSCR_LENGTH_BIT (16)
+#define XREG_FPSCR_LENGTH_MASK (7 << FPSCR_LENGTH_BIT)
+#define XREG_FPSCR_IDC (1 << 7)
+#define XREG_FPSCR_IXC (1 << 4)
+#define XREG_FPSCR_UFC (1 << 3)
+#define XREG_FPSCR_OFC (1 << 2)
+#define XREG_FPSCR_DZC (1 << 1)
+#define XREG_FPSCR_IOC (1 << 0)
+
+/* MVFR0 bits */
+#define XREG_MVFR0_RMODE_BIT (28)
+#define XREG_MVFR0_RMODE_MASK (0xF << XREG_MVFR0_RMODE_BIT)
+#define XREG_MVFR0_SHORT_VEC_BIT (24)
+#define XREG_MVFR0_SHORT_VEC_MASK (0xF << XREG_MVFR0_SHORT_VEC_BIT)
+#define XREG_MVFR0_SQRT_BIT (20)
+#define XREG_MVFR0_SQRT_MASK (0xF << XREG_MVFR0_SQRT_BIT)
+#define XREG_MVFR0_DIVIDE_BIT (16)
+#define XREG_MVFR0_DIVIDE_MASK (0xF << XREG_MVFR0_DIVIDE_BIT)
+#define XREG_MVFR0_EXEC_TRAP_BIT (12)
+#define XREG_MVFR0_EXEC_TRAP_MASK (0xF << XREG_MVFR0_EXEC_TRAP_BIT)
+#define XREG_MVFR0_DP_BIT (8)
+#define XREG_MVFR0_DP_MASK (0xF << XREG_MVFR0_DP_BIT)
+#define XREG_MVFR0_SP_BIT (4)
+#define XREG_MVFR0_SP_MASK (0xF << XREG_MVFR0_SP_BIT)
+#define XREG_MVFR0_A_SIMD_BIT (0)
+#define XREG_MVFR0_A_SIMD_MASK (0xF << MVFR0_A_SIMD_BIT)
+
+/* FPEXC bits */
+#define XREG_FPEXC_EX (1 << 31)
+#define XREG_FPEXC_EN (1 << 30)
+#define XREG_FPEXC_DEX (1 << 29)
+
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+
+#endif /* XREG_CORTEXA9_H */
diff --git a/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/include/xscugic.h b/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/include/xscugic.h
new file mode 100644
index 0000000..10dc3dc
--- /dev/null
+++ b/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/include/xscugic.h
@@ -0,0 +1,610 @@
+/******************************************************************************
+*
+* Copyright (C) 2010 - 2019 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+* THE SOFTWARE.
+*
+*
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xscugic.h
+* @addtogroup scugic_v4_0
+* @{
+* @details
+*
+* The generic interrupt controller driver component.
+*
+* The interrupt controller driver uses the idea of priority for the various
+* handlers. Priority is an integer within the range of 1 and 31 inclusive with
+* default of 1 being the highest priority interrupt source. The priorities
+* of the various sources can be dynamically altered as needed through
+* hardware configuration.
+*
+* The generic interrupt controller supports the following
+* features:
+*
+* - specific individual interrupt enabling/disabling
+* - specific individual interrupt acknowledging
+* - attaching specific callback function to handle interrupt source
+* - assigning desired priority to interrupt source if default is not
+* acceptable.
+*
+* Details about connecting the interrupt handler of the driver are contained
+* in the source file specific to interrupt processing, xscugic_intr.c.
+*
+* This driver is intended to be RTOS and processor independent. It works with
+* physical addresses only. Any needs for dynamic memory management, threads
+* or thread mutual exclusion, virtual memory, or cache control must be
+* satisfied by the layer above this driver.
+*
+* <b>Interrupt Vector Tables</b>
+*
+* The device ID of the interrupt controller device is used by the driver as a
+* direct index into the configuration data table. The user should populate the
+* vector table with handlers and callbacks at run-time using the
+* XScuGic_Connect() and XScuGic_Disconnect() functions.
+*
+* Each vector table entry corresponds to a device that can generate an
+* interrupt. Each entry contains an interrupt handler function and an
+* argument to be passed to the handler when an interrupt occurs. The
+* user must use XScuGic_Connect() when the interrupt handler takes an
+* argument other than the base address.
+*
+* <b>Nested Interrupts Processing</b>
+*
+* Nested interrupts are not supported by this driver.
+*
+* NOTE:
+* The generic interrupt controller is not a part of the snoop control unit
+* as indicated by the prefix "scu" in the name of the driver.
+* It is an independent module in APU.
+*
+* <pre>
+* MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ----- ---- -------- ---------------------------------------------------------
+* 1.00a drg 01/19/00 First release
+* 1.01a sdm 11/09/11 The XScuGic and XScuGic_Config structures have changed.
+* The HandlerTable (of type XScuGic_VectorTableEntry) is
+* moved to XScuGic_Config structure from XScuGic structure.
+*
+* The "Config" entry in XScuGic structure is made as
+* pointer for better efficiency.
+*
+* A new file named as xscugic_hw.c is now added. It is
+* to implement low level driver routines without using
+* any xscugic instance pointer. They are useful when the
+* user wants to use xscugic through device id or
+* base address. The driver routines provided are explained
+* below.
+* XScuGic_DeviceInitialize that takes device id as
+* argument and initializes the device (without calling
+* XScuGic_CfgInitialize).
+* XScuGic_DeviceInterruptHandler that takes device id
+* as argument and calls appropriate handlers from the
+* HandlerTable.
+* XScuGic_RegisterHandler that registers a new handler
+* by taking xscugic hardware base address as argument.
+* LookupConfigByBaseAddress is used to return the
+* corresponding config structure from XScuGic_ConfigTable
+* based on the scugic base address passed.
+* 1.02a sdm 12/20/11 Removed AckBeforeService from the XScuGic_Config
+* structure.
+* 1.03a srt 02/27/13 Moved Offset calculation macros from *.c and *_hw.c to
+* *_hw.h
+* Added APIs
+* - XScuGic_SetPriTrigTypeByDistAddr()
+* - XScuGic_GetPriTrigTypeByDistAddr()
+* (CR 702687)
+* Added support to direct interrupts to the appropriate CPU. Earlier
+* interrupts were directed to CPU1 (hard coded). Now depending
+* upon the CPU selected by the user (xparameters.h), interrupts
+* will be directed to the relevant CPU. This fixes CR 699688.
+* 1.04a hk 05/04/13 Assigned EffectiveAddr to CpuBaseAddress in
+* XScuGic_CfgInitialize. Fix for CR#704400 to remove warnings.
+* Moved functions XScuGic_SetPriTrigTypeByDistAddr and
+* XScuGic_GetPriTrigTypeByDistAddr to xscugic_hw.c.
+* This is fix for CR#705621.
+* 1.05a hk 06/26/13 Modified tcl to export external interrupts correctly to
+* xparameters.h. Fix for CR's 690505, 708928 & 719359.
+* 2.0 adk 12/10/13 Updated as per the New Tcl API's
+* 2.1 adk 25/04/14 Fixed the CR:789373 changes are made in the driver tcl file.
+* 3.00 kvn 02/13/15 Modified code for MISRA-C:2012 compliance.
+* 3.2 asa 02/29/16 Modified DistributorInit function for Zynq AMP case. The
+* distributor is left uninitialized for Zynq AMP. It is assumed
+* that the distributor will be initialized by Linux master. However
+* for CortexR5 case, the earlier code is left unchanged where the
+* the interrupt processor target registers in the distributor is
+* initialized with the corresponding CPU ID on which the application
+* built over the scugic driver runs.
+* These changes fix CR#937243.
+*
+* 3.4 asa 04/07/16 Created a new static function DoDistributorInit to simplify
+* the flow and avoid code duplication. Changes are made for
+* USE_AMP use case for R5. In a scenario (in R5 split mode) when
+* one R5 is operating with A53 in open amp config and other
+* R5 running baremetal app, the existing code
+* had the potential to stop the whole AMP solution to work (if
+* for some reason the R5 running the baremetal app tasked to
+* initialize the Distributor hangs or crashes before initializing).
+* Changes are made so that the R5 under AMP first checks if
+* the distributor is enabled or not and if not, it does the
+* standard Distributor initialization.
+* This fixes the CR#952962.
+* 3.6 ms 01/23/17 Modified xil_printf statement in main function for all
+* examples to ensure that "Successfully ran" and "Failed"
+* strings are available in all examples. This is a fix
+* for CR-965028.
+* kvn 02/17/17 Add support for changing GIC CPU master at run time.
+* kvn 02/28/17 Make the CpuId as static variable and Added new
+* XScugiC_GetCpuId to access CpuId.
+* ms 03/17/17 Added readme.txt file in examples folder for doxygen
+* generation.
+* 3.7 ms 04/11/17 Modified tcl file to add suffix U for all macro
+* definitions of scugic in xparameters.h
+* 3.8 mus 07/05/17 Updated scugic.tcl to add support for interrupts connected
+* through util_reduced_vector IP(OR gate)
+* mus 07/05/17 Updated xdefine_zynq_canonical_xpars proc to initialize
+* the HandlerTable in XScuGic_ConfigTable to 0, it removes
+* the compilation warning in xscugic_g.c. Fix for CR#978736.
+* mus 07/25/17 Updated xdefine_gic_params proc to export correct canonical
+* definitions for pl to ps interrupts.Fix for CR#980534
+* 3.9 mus 02/21/18 Added new API's XScuGic_UnmapAllInterruptsFromCpu and
+* XScuGic_InterruptUnmapFromCpu, These API's can be used
+* by applications to unmap specific/all interrupts from
+* target CPU.
+* 3.10 aru 08/23/18 Resolved MISRA-C:2012 compliance mandatory violations
+* 4.0 mus 11/22/18 Fixed bugs in software interrupt generation through
+* XScuGic_SoftwareIntr API
+* 4.1 asa 03/30/19 Made changes not to direct each interrupt to all
+* available CPUs by default. This was breaking AMP
+* behavior. Instead every time an interrupt enable
+* request is received, the interrupt was mapped to
+* the respective CPU. There were several other changes
+* made to implement this. This set of changes was to
+* fix CR-1024716.
+* 4.1 mus 06/19/19 Added API's XScuGic_MarkCoreAsleep and
+* XScuGic_MarkCoreAwake to mark processor core as
+* asleep or awake. Fix for CR#1027220.
+*
+* </pre>
+*
+******************************************************************************/
+
+#ifndef XSCUGIC_H /* prevent circular inclusions */
+#define XSCUGIC_H /* by using protection macros */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+
+/***************************** Include Files *********************************/
+
+#include "xstatus.h"
+#include "xil_io.h"
+#include "xscugic_hw.h"
+#include "xil_exception.h"
+
+/************************** Constant Definitions *****************************/
+
+#define EFUSE_STATUS_OFFSET 0x10
+#define EFUSE_STATUS_CPU_MASK 0x80
+
+#if !defined (ARMR5) && !defined (__aarch64__) && !defined (ARMA53_32)
+#define ARMA9
+#endif
+
+#define XSCUGIC500_DCTLR_ARE_NS_ENABLE 0x20
+#define XSCUGIC500_DCTLR_ARE_S_ENABLE 0x10
+/**************************** Type Definitions *******************************/
+
+/* The following data type defines each entry in an interrupt vector table.
+ * The callback reference is the base address of the interrupting device
+ * for the low level driver and an instance pointer for the high level driver.
+ */
+typedef struct
+{
+ Xil_InterruptHandler Handler;
+ void *CallBackRef;
+} XScuGic_VectorTableEntry;
+
+/**
+ * This typedef contains configuration information for the device.
+ */
+typedef struct
+{
+ u16 DeviceId; /**< Unique ID of device */
+ u32 CpuBaseAddress; /**< CPU Interface Register base address */
+ u32 DistBaseAddress; /**< Distributor Register base address */
+ XScuGic_VectorTableEntry HandlerTable[XSCUGIC_MAX_NUM_INTR_INPUTS];/**<
+ Vector table of interrupt handlers */
+} XScuGic_Config;
+
+/**
+ * The XScuGic driver instance data. The user is required to allocate a
+ * variable of this type for every intc device in the system. A pointer
+ * to a variable of this type is then passed to the driver API functions.
+ */
+typedef struct
+{
+ XScuGic_Config *Config; /**< Configuration table entry */
+ u32 IsReady; /**< Device is initialized and ready */
+ u32 UnhandledInterrupts; /**< Intc Statistics */
+} XScuGic;
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/****************************************************************************/
+/**
+*
+* Write the given CPU Interface register
+*
+* @param InstancePtr is a pointer to the instance to be worked on.
+* @param RegOffset is the register offset to be written
+* @param Data is the 32-bit value to write to the register
+*
+* @return None.
+*
+* @note
+* C-style signature:
+* void XScuGic_CPUWriteReg(XScuGic *InstancePtr, u32 RegOffset, u32 Data)
+*
+*****************************************************************************/
+#define XScuGic_CPUWriteReg(InstancePtr, RegOffset, Data) \
+(XScuGic_WriteReg(((InstancePtr)->Config->CpuBaseAddress), (RegOffset), \
+ ((u32)(Data))))
+
+/****************************************************************************/
+/**
+*
+* Read the given CPU Interface register
+*
+* @param InstancePtr is a pointer to the instance to be worked on.
+* @param RegOffset is the register offset to be read
+*
+* @return The 32-bit value of the register
+*
+* @note
+* C-style signature:
+* u32 XScuGic_CPUReadReg(XScuGic *InstancePtr, u32 RegOffset)
+*
+*****************************************************************************/
+#define XScuGic_CPUReadReg(InstancePtr, RegOffset) \
+ (XScuGic_ReadReg(((InstancePtr)->Config->CpuBaseAddress), (RegOffset)))
+
+/****************************************************************************/
+/**
+*
+* Write the given Distributor Interface register
+*
+* @param InstancePtr is a pointer to the instance to be worked on.
+* @param RegOffset is the register offset to be written
+* @param Data is the 32-bit value to write to the register
+*
+* @return None.
+*
+* @note
+* C-style signature:
+* void XScuGic_DistWriteReg(XScuGic *InstancePtr, u32 RegOffset, u32 Data)
+*
+*****************************************************************************/
+#define XScuGic_DistWriteReg(InstancePtr, RegOffset, Data) \
+(XScuGic_WriteReg(((InstancePtr)->Config->DistBaseAddress), (RegOffset), \
+ ((u32)(Data))))
+
+/****************************************************************************/
+/**
+*
+* Read the given Distributor Interface register
+*
+* @param InstancePtr is a pointer to the instance to be worked on.
+* @param RegOffset is the register offset to be read
+*
+* @return The 32-bit value of the register
+*
+* @note
+* C-style signature:
+* u32 XScuGic_DistReadReg(XScuGic *InstancePtr, u32 RegOffset)
+*
+*****************************************************************************/
+#define XScuGic_DistReadReg(InstancePtr, RegOffset) \
+(XScuGic_ReadReg(((InstancePtr)->Config->DistBaseAddress), (RegOffset)))
+
+/****************************************************************************/
+/**
+*
+* Write the given ReDistributor Interface register
+*
+* @param InstancePtr is a pointer to the instance to be worked on.
+* @param RegOffset is the register offset to be written
+* @param Data is the 32-bit value to write to the register
+*
+* @return None.
+*
+* @note
+* C-style signature:
+* void XScuGic_DistWriteReg(XScuGic *InstancePtr, u32 RegOffset, u32 Data)
+*
+*****************************************************************************/
+#define XScuGic_ReDistWriteReg(InstancePtr, RegOffset, Data) \
+(XScuGic_WriteReg(((InstancePtr)->Config->DistBaseAddress)+ \
+ XSCUGIC_RDIST_OFFSET, (RegOffset), ((u32)(Data))))
+
+/****************************************************************************/
+/**
+*
+* Read the given ReDistributor Interface register
+*
+* @param InstancePtr is a pointer to the instance to be worked on.
+* @param RegOffset is the register offset to be read
+*
+* @return The 32-bit value of the register
+*
+* @note
+* C-style signature:
+* u32 XScuGic_DistReadReg(XScuGic *InstancePtr, u32 RegOffset)
+*
+*****************************************************************************/
+#define XScuGic_ReDistReadReg(InstancePtr, RegOffset) \
+(XScuGic_ReadReg((((InstancePtr)->Config->DistBaseAddress)+ \
+XSCUGIC_RDIST_OFFSET), (RegOffset)))
+
+/****************************************************************************/
+/**
+*
+* Write the given ReDistributor SGI PPI Interface register
+*
+* @param InstancePtr is a pointer to the instance to be worked on.
+* @param RegOffset is the register offset to be written
+* @param Data is the 32-bit value to write to the register
+*
+* @return None.
+*
+* @note
+* C-style signature:
+* void XScuGic_DistWriteReg(XScuGic *InstancePtr, u32 RegOffset, u32 Data)
+*
+*****************************************************************************/
+#define XScuGic_ReDistSGIPPIWriteReg(InstancePtr, RegOffset, Data) \
+(XScuGic_WriteReg(((InstancePtr)->Config->DistBaseAddress)+ \
+ XSCUGIC_RDIST_SGI_PPI_OFFSET, (RegOffset), ((u32)(Data))))
+
+/****************************************************************************/
+/**
+*
+* Read the given ReDistributor SGI PPI Interface register
+*
+* @param InstancePtr is a pointer to the instance to be worked on.
+* @param RegOffset is the register offset to be read
+*
+* @return The 32-bit value of the register
+*
+* @note
+* C-style signature:
+* u32 XScuGic_DistReadReg(XScuGic *InstancePtr, u32 RegOffset)
+*
+*****************************************************************************/
+#define XScuGic_ReDistSGIPPIReadReg(InstancePtr, RegOffset) \
+(XScuGic_ReadReg((((InstancePtr)->Config->DistBaseAddress)+ \
+ XSCUGIC_RDIST_SGI_PPI_OFFSET), (RegOffset)))
+
+/****************************************************************************/
+/**
+* This function enables system register interface for GIC CPU Interface
+*
+* @param value to be written
+*
+* @return None.
+*
+* @note None.
+*
+*****************************************************************************/
+#define XScuGic_Enable_SystemReg_CPU_Interface_EL3() mtcp(S3_6_C12_C12_5, 0xF);
+#define XScuGic_Enable_SystemReg_CPU_Interface_EL1() mtcp(S3_0_C12_C12_5, 0xF);
+/****************************************************************************/
+/**
+* This function enables Grou0 interrupts
+*
+* @param None.
+*
+* @return None.
+*
+* @note None.
+*
+*****************************************************************************/
+#define XScuGic_Enable_Group0_Interrupts() mtcp(S3_0_C12_C12_6,0x1);
+/****************************************************************************/
+/**
+* This function enables Group1 interrupts
+*
+* @param None.
+*
+* @return None.
+*
+* @note None.
+*
+*****************************************************************************/
+#if defined (__aarch64__)
+#if EL1_NONSECURE
+#define XScuGic_Enable_Group1_Interrupts() \
+ mtcp (S3_0_C12_C12_7, 0x1 | mfcp(S3_0_C12_C12_7) );
+#else
+#define XScuGic_Enable_Group1_Interrupts() \
+ mtcp (S3_6_C12_C12_7, 0x1 | mfcp(S3_6_C12_C12_7) );
+#endif
+#endif
+/****************************************************************************/
+/**
+* This function writes to ICC_SGI0R_EL1
+*
+* @param value to be written
+*
+* @return None.
+*
+* @note None.
+*
+*****************************************************************************/
+#define XScuGic_WriteICC_SGI0R_EL1(val) mtcp(S3_0_C12_C11_7,val)
+
+/****************************************************************************/
+/**
+* This function writes to ICC_SGI1R_EL1
+*
+* @param value to be written
+*
+* @return None.
+*
+* @note None.
+*
+*****************************************************************************/
+#define XScuGic_WriteICC_SGI1R_EL1(val) mtcp(S3_0_C12_C11_5,val)
+
+/****************************************************************************/
+/**
+* This function reads ICC_SGI1R_EL1 register
+*
+* @param None
+*
+* @return Value of ICC_SGI1R_EL1 register
+*
+* @note None.
+*
+*****************************************************************************/
+#define XScuGic_ReadICC_SGI1R_EL1() mfcp(S3_0_C12_C11_5)
+/****************************************************************************/
+/**
+* This function sets interrupt priority filter
+*
+* @param None.
+*
+* @return None.
+*
+* @note None.
+*
+*****************************************************************************/
+#define XScuGic_set_priority_filter(val) __asm__ __volatile__("msr S3_0_C4_C6_0,%0" : : "r" (val))
+/****************************************************************************/
+/**
+* This function returns interrupt id of highest priority pending interrupt
+*
+* @param None.
+*
+* @return None.
+*
+* @note None.
+*
+*****************************************************************************/
+#if defined (__aarch64__)
+#if EL3
+#define XScuGic_get_IntID() mfcp(S3_0_C12_C8_0)
+#else
+#define XScuGic_get_IntID() mfcp(S3_0_C12_C12_0)
+#endif
+#endif
+/****************************************************************************/
+/**
+* This function acks the interrupt
+*
+* @param None.
+*
+* @return None.
+*
+* @note None.
+*
+*****************************************************************************/
+#if defined (__aarch64__)
+#if EL3
+#define XScuGic_ack_Int(val) mtcp(S3_0_C12_C8_1,val)
+#else
+#define XScuGic_ack_Int(val) mtcp(S3_0_C12_C12_1,val)
+#endif
+#endif
+/****************************************************************************/
+/**
+* This macro returns bit position for the specific interrupt's trigger type
+* configuration within GICR_ICFGR0/GICR_ICFGR1 register
+*
+* @param None.
+*
+* @return None.
+*
+* @note None.
+*
+*****************************************************************************/
+#define XScuGic_Get_Rdist_Int_Trigger_Index(IntrId) (((Int_Id%16) & 0x1f) << 2) +1
+/************************** Function Prototypes ******************************/
+
+/*
+ * Required functions in xscugic.c
+ */
+
+s32 XScuGic_Connect(XScuGic *InstancePtr, u32 Int_Id,
+ Xil_InterruptHandler Handler, void *CallBackRef);
+void XScuGic_Disconnect(XScuGic *InstancePtr, u32 Int_Id);
+
+void XScuGic_Enable(XScuGic *InstancePtr, u32 Int_Id);
+void XScuGic_Disable(XScuGic *InstancePtr, u32 Int_Id);
+
+s32 XScuGic_CfgInitialize(XScuGic *InstancePtr, XScuGic_Config *ConfigPtr,
+ u32 EffectiveAddr);
+
+s32 XScuGic_SoftwareIntr(XScuGic *InstancePtr, u32 Int_Id, u32 Cpu_Id);
+
+void XScuGic_GetPriorityTriggerType(XScuGic *InstancePtr, u32 Int_Id,
+ u8 *Priority, u8 *Trigger);
+void XScuGic_SetPriorityTriggerType(XScuGic *InstancePtr, u32 Int_Id,
+ u8 Priority, u8 Trigger);
+void XScuGic_InterruptMaptoCpu(XScuGic *InstancePtr, u8 Cpu_Id, u32 Int_Id);
+void XScuGic_InterruptUnmapFromCpu(XScuGic *InstancePtr, u8 Cpu_Id, u32 Int_Id);
+void XScuGic_UnmapAllInterruptsFromCpu(XScuGic *InstancePtr, u8 Cpu_Id);
+void XScuGic_Stop(XScuGic *InstancePtr);
+void XScuGic_SetCpuID(u32 CpuCoreId);
+u32 XScuGic_GetCpuID(void);
+/*
+ * Initialization functions in xscugic_sinit.c
+ */
+XScuGic_Config *XScuGic_LookupConfig(u16 DeviceId);
+
+/*
+ * Interrupt functions in xscugic_intr.c
+ */
+void XScuGic_InterruptHandler(XScuGic *InstancePtr);
+
+/*
+ * Self-test functions in xscugic_selftest.c
+ */
+s32 XScuGic_SelfTest(XScuGic *InstancePtr);
+
+void XScuGic_EnableSGI_PPI(XScuGic *InstancePtr,u32 ID);
+void XScuGic_SetPPI_SGI_Priority(XScuGic *InstancePtr,u32 ID, u32 priority);
+#if defined (GICv3)
+void XScuGic_MarkCoreAsleep(XScuGic *InstancePtr);
+void XScuGic_MarkCoreAwake(XScuGic *InstancePtr);
+#endif
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* end of protection macro */
+/** @} */
diff --git a/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/include/xscugic_hw.h b/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/include/xscugic_hw.h
new file mode 100644
index 0000000..6254168
--- /dev/null
+++ b/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/include/xscugic_hw.h
@@ -0,0 +1,718 @@
+/******************************************************************************
+*
+* Copyright (C) 2010 - 2019 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+* THE SOFTWARE.
+*
+*
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xscugic_hw.h
+* @addtogroup scugic_v4_0
+* @{
+*
+* This header file contains identifiers and HW access functions (or
+* macros) that can be used to access the device. The user should refer to the
+* hardware device specification for more details of the device operation.
+* The driver functions/APIs are defined in xscugic.h.
+*
+* This GIC device has two parts, a distributor and CPU interface(s). Each part
+* has separate register definition sections.
+*
+*
+* <pre>
+* MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ----- ---- -------- -----------------------------------------------------
+* 1.00a drg 01/19/10 First release
+* 1.01a sdm 11/09/11 "xil_exception.h" added as include.
+* Macros XScuGic_EnableIntr and XScuGic_DisableIntr are
+* added to enable or disable interrupts based on
+* Distributor Register base address. Normally users use
+* XScuGic instance and call XScuGic_Enable or
+* XScuGic_Disable to enable/disable interrupts. These
+* new macros are provided when user does not want to
+* use an instance pointer but still wants to enable or
+* disable interrupts.
+* Function prototypes for functions (present in newly
+* added file xscugic_hw.c) are added.
+* 1.03a srt 02/27/13 Moved Offset calculation macros from *_hw.c (CR
+* 702687).
+* 1.04a hk 05/04/13 Fix for CR#705621. Moved function prototypes
+* XScuGic_SetPriTrigTypeByDistAddr and
+* XScuGic_GetPriTrigTypeByDistAddr here from xscugic.h
+* 3.0 pkp 12/09/14 changed XSCUGIC_MAX_NUM_INTR_INPUTS for
+* Zynq Ultrascale Mp
+* 3.0 kvn 02/13/14 Modified code for MISRA-C:2012 compliance.
+* 3.2 pkp 11/09/15 Corrected the interrupt processsor target mask value
+* for CPU interface 2 i.e. XSCUGIC_SPI_CPU2_MASK
+* 3.9 mus 02/21/18 Added new API's XScuGic_InterruptUnmapFromCpuByDistAddr
+* and XScuGic_UnmapAllInterruptsFromCpuByDistAddr, These
+* API's can be used by applications to unmap specific/all
+* interrupts from target CPU. It fixes CR#992490.
+* 3.10 aru 08/23/18 Resolved MISRA-C:2012 compliance mandatory violations
+* 4.1 asa 03/30/19 Removed macros for XScuGic_EnableIntr, and
+* XScuGic_DisableIntr. These are now C functions. This
+* change was to fix CR-1024716.
+* 4.1 mus 06/12/19 Updated XSCUGIC_MAX_NUM_INTR_INPUTS for Versal.
+*
+* </pre>
+*
+******************************************************************************/
+
+#ifndef XSCUGIC_HW_H /* prevent circular inclusions */
+#define XSCUGIC_HW_H /* by using protection macros */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/***************************** Include Files *********************************/
+
+#include "xil_types.h"
+#include "xil_assert.h"
+#include "xil_io.h"
+#include "xil_exception.h"
+#include "bspconfig.h"
+
+/************************** Constant Definitions *****************************/
+#if defined (versal) && !defined(ARMR5)
+#define GICv3
+#endif
+
+/*
+ * The maximum number of interrupts supported by the hardware.
+ */
+#ifdef PLATFORM_ZYNQ
+#define XSCUGIC_MAX_NUM_INTR_INPUTS 95U /* Maximum number of interrupt defined by Zynq */
+#elif defined (versal)
+#define XSCUGIC_MAX_NUM_INTR_INPUTS 192U
+#else
+#define XSCUGIC_MAX_NUM_INTR_INPUTS 195U /* Maximum number of interrupt defined by Zynq Ultrascale Mp */
+#endif
+
+/*
+ * First Interrupt Id for SPI interrupts.
+ */
+#define XSCUGIC_SPI_INT_ID_START 0x20
+/*
+ * The maximum priority value that can be used in the GIC.
+ */
+#define XSCUGIC_MAX_INTR_PRIO_VAL 248U
+#define XSCUGIC_INTR_PRIO_MASK 0x000000F8U
+
+/** @name Distributor Interface Register Map
+ *
+ * Define the offsets from the base address for all Distributor registers of
+ * the interrupt controller, some registers may be reserved in the hardware
+ * device.
+ * @{
+ */
+#define XSCUGIC_DIST_EN_OFFSET 0x00000000U /**< Distributor Enable
+ Register */
+#define XSCUGIC_IC_TYPE_OFFSET 0x00000004U /**< Interrupt Controller
+ Type Register */
+#define XSCUGIC_DIST_IDENT_OFFSET 0x00000008U /**< Implementor ID
+ Register */
+#define XSCUGIC_SECURITY_OFFSET 0x00000080U /**< Interrupt Security
+ Register */
+#define XSCUGIC_ENABLE_SET_OFFSET 0x00000100U /**< Enable Set
+ Register */
+#define XSCUGIC_DISABLE_OFFSET 0x00000180U /**< Enable Clear Register */
+#define XSCUGIC_PENDING_SET_OFFSET 0x00000200U /**< Pending Set
+ Register */
+#define XSCUGIC_PENDING_CLR_OFFSET 0x00000280U /**< Pending Clear
+ Register */
+#define XSCUGIC_ACTIVE_OFFSET 0x00000300U /**< Active Status Register */
+#define XSCUGIC_PRIORITY_OFFSET 0x00000400U /**< Priority Level Register */
+#define XSCUGIC_SPI_TARGET_OFFSET 0x00000800U /**< SPI Target
+ Register 0x800-0x8FB */
+#define XSCUGIC_INT_CFG_OFFSET 0x00000C00U /**< Interrupt Configuration
+ Register 0xC00-0xCFC */
+#define XSCUGIC_PPI_STAT_OFFSET 0x00000D00U /**< PPI Status Register */
+#define XSCUGIC_SPI_STAT_OFFSET 0x00000D04U /**< SPI Status Register
+ 0xd04-0xd7C */
+#define XSCUGIC_AHB_CONFIG_OFFSET 0x00000D80U /**< AHB Configuration
+ Register */
+#define XSCUGIC_SFI_TRIG_OFFSET 0x00000F00U /**< Software Triggered
+ Interrupt Register */
+#define XSCUGIC_PERPHID_OFFSET 0x00000FD0U /**< Peripheral ID Reg */
+#if defined (GICv3)
+#define XSCUGIC_PCELLID_OFFSET 0x0000FFF0U /**< Pcell ID Register */
+#else
+#define XSCUGIC_PCELLID_OFFSET 0x00000FF0U /**< Pcell ID Register */
+#endif
+/* @} */
+
+/** @name Distributor Enable Register
+ * Controls if the distributor response to external interrupt inputs.
+ * @{
+ */
+#if defined (GICv3)
+#define XSCUGIC_EN_INT_MASK 0x00000003U /**< Interrupt In Enable */
+#else
+#define XSCUGIC_EN_INT_MASK 0x00000001U /**< Interrupt In Enable */
+#endif
+/* @} */
+
+/** @name Interrupt Controller Type Register
+ * @{
+ */
+#define XSCUGIC_LSPI_MASK 0x0000F800U /**< Number of Lockable
+ Shared Peripheral
+ Interrupts*/
+#define XSCUGIC_DOMAIN_MASK 0x00000400U /**< Number os Security domains*/
+#define XSCUGIC_CPU_NUM_MASK 0x000000E0U /**< Number of CPU Interfaces */
+#define XSCUGIC_NUM_INT_MASK 0x0000001FU /**< Number of Interrupt IDs */
+/* @} */
+
+/** @name Implementor ID Register
+ * Implementor and revision information.
+ * @{
+ */
+#define XSCUGIC_REV_MASK 0x00FFF000U /**< Revision Number */
+#define XSCUGIC_IMPL_MASK 0x00000FFFU /**< Implementor */
+/* @} */
+
+/** @name Interrupt Security Registers
+ * Each bit controls the security level of an interrupt, either secure or non
+ * secure. These registers can only be accessed using secure read and write.
+ * There are registers for each of the CPU interfaces at offset 0x080. A
+ * register set for the SPI interrupts is available to all CPU interfaces.
+ * There are up to 32 of these registers staring at location 0x084.
+ * @{
+ */
+#define XSCUGIC_INT_NS_MASK 0x00000001U /**< Each bit corresponds to an
+ INT_ID */
+/* @} */
+
+/** @name Enable Set Register
+ * Each bit controls the enabling of an interrupt, a 0 is disabled, a 1 is
+ * enabled. Writing a 0 has no effect. Use the ENABLE_CLR register to set a
+ * bit to 0.
+ * There are registers for each of the CPU interfaces at offset 0x100. With up
+ * to 8 registers aliased to the same address. A register set for the SPI
+ * interrupts is available to all CPU interfaces.
+ * There are up to 32 of these registers staring at location 0x104.
+ * @{
+ */
+#define XSCUGIC_INT_EN_MASK 0x00000001U /**< Each bit corresponds to an
+ INT_ID */
+/* @} */
+
+/** @name Enable Clear Register
+ * Each bit controls the disabling of an interrupt, a 0 is disabled, a 1 is
+ * enabled. Writing a 0 has no effect. Writing a 1 disables an interrupt and
+ * sets the corresponding bit to 0.
+ * There are registers for each of the CPU interfaces at offset 0x180. With up
+ * to 8 registers aliased to the same address.
+ * A register set for the SPI interrupts is available to all CPU interfaces.
+ * There are up to 32 of these registers staring at location 0x184.
+ * @{
+ */
+#define XSCUGIC_INT_CLR_MASK 0x00000001U /**< Each bit corresponds to an
+ INT_ID */
+/* @} */
+
+/** @name Pending Set Register
+ * Each bit controls the Pending or Active and Pending state of an interrupt, a
+ * 0 is not pending, a 1 is pending. Writing a 0 has no effect. Writing a 1 sets
+ * an interrupt to the pending state.
+ * There are registers for each of the CPU interfaces at offset 0x200. With up
+ * to 8 registers aliased to the same address.
+ * A register set for the SPI interrupts is available to all CPU interfaces.
+ * There are up to 32 of these registers staring at location 0x204.
+ * @{
+ */
+#define XSCUGIC_PEND_SET_MASK 0x00000001U /**< Each bit corresponds to an
+ INT_ID */
+/* @} */
+
+/** @name Pending Clear Register
+ * Each bit can clear the Pending or Active and Pending state of an interrupt, a
+ * 0 is not pending, a 1 is pending. Writing a 0 has no effect. Writing a 1
+ * clears the pending state of an interrupt.
+ * There are registers for each of the CPU interfaces at offset 0x280. With up
+ * to 8 registers aliased to the same address.
+ * A register set for the SPI interrupts is available to all CPU interfaces.
+ * There are up to 32 of these registers staring at location 0x284.
+ * @{
+ */
+#define XSCUGIC_PEND_CLR_MASK 0x00000001U /**< Each bit corresponds to an
+ INT_ID */
+/* @} */
+
+/** @name Active Status Register
+ * Each bit provides the Active status of an interrupt, a
+ * 0 is not Active, a 1 is Active. This is a read only register.
+ * There are registers for each of the CPU interfaces at offset 0x300. With up
+ * to 8 registers aliased to each address.
+ * A register set for the SPI interrupts is available to all CPU interfaces.
+ * There are up to 32 of these registers staring at location 0x380.
+ * @{
+ */
+#define XSCUGIC_ACTIVE_MASK 0x00000001U /**< Each bit corresponds to an
+ INT_ID */
+/* @} */
+
+/** @name Priority Level Register
+ * Each byte in a Priority Level Register sets the priority level of an
+ * interrupt. Reading the register provides the priority level of an interrupt.
+ * There are registers for each of the CPU interfaces at offset 0x400 through
+ * 0x41C. With up to 8 registers aliased to each address.
+ * 0 is highest priority, 0xFF is lowest.
+ * A register set for the SPI interrupts is available to all CPU interfaces.
+ * There are up to 255 of these registers staring at location 0x420.
+ * @{
+ */
+#define XSCUGIC_PRIORITY_MASK 0x000000FFU /**< Each Byte corresponds to an
+ INT_ID */
+#define XSCUGIC_PRIORITY_MAX 0x000000FFU /**< Highest value of a priority
+ actually the lowest priority*/
+/* @} */
+
+/** @name SPI Target Register 0x800-0x8FB
+ * Each byte references a separate SPI and programs which of the up to 8 CPU
+ * interfaces are sent a Pending interrupt.
+ * There are registers for each of the CPU interfaces at offset 0x800 through
+ * 0x81C. With up to 8 registers aliased to each address.
+ * A register set for the SPI interrupts is available to all CPU interfaces.
+ * There are up to 255 of these registers staring at location 0x820.
+ *
+ * This driver does not support multiple CPU interfaces. These are included
+ * for complete documentation.
+ * @{
+ */
+#define XSCUGIC_SPI_CPU7_MASK 0x00000080U /**< CPU 7 Mask*/
+#define XSCUGIC_SPI_CPU6_MASK 0x00000040U /**< CPU 6 Mask*/
+#define XSCUGIC_SPI_CPU5_MASK 0x00000020U /**< CPU 5 Mask*/
+#define XSCUGIC_SPI_CPU4_MASK 0x00000010U /**< CPU 4 Mask*/
+#define XSCUGIC_SPI_CPU3_MASK 0x00000008U /**< CPU 3 Mask*/
+#define XSCUGIC_SPI_CPU2_MASK 0x00000004U /**< CPU 2 Mask*/
+#define XSCUGIC_SPI_CPU1_MASK 0x00000002U /**< CPU 1 Mask*/
+#define XSCUGIC_SPI_CPU0_MASK 0x00000001U /**< CPU 0 Mask*/
+/* @} */
+
+/** @name Interrupt Configuration Register 0xC00-0xCFC
+ * The interrupt configuration registers program an SFI to be active HIGH level
+ * sensitive or rising edge sensitive.
+ * Each bit pair describes the configuration for an INT_ID.
+ * SFI Read Only b10 always
+ * PPI Read Only depending on how the PPIs are configured.
+ * b01 Active HIGH level sensitive
+ * b11 Rising edge sensitive
+ * SPI LSB is read only.
+ * b01 Active HIGH level sensitive
+ * b11 Rising edge sensitive/
+ * There are registers for each of the CPU interfaces at offset 0xC00 through
+ * 0xC04. With up to 8 registers aliased to each address.
+ * A register set for the SPI interrupts is available to all CPU interfaces.
+ * There are up to 255 of these registers staring at location 0xC08.
+ * @{
+ */
+#define XSCUGIC_INT_CFG_MASK 0x00000003U /**< */
+/* @} */
+
+/** @name PPI Status Register
+ * Enables an external AMBA master to access the status of the PPI inputs.
+ * A CPU can only read the status of its local PPI signals and cannot read the
+ * status for other CPUs.
+ * This register is aliased for each CPU interface.
+ * @{
+ */
+#define XSCUGIC_PPI_C15_MASK 0x00008000U /**< PPI Status */
+#define XSCUGIC_PPI_C14_MASK 0x00004000U /**< PPI Status */
+#define XSCUGIC_PPI_C13_MASK 0x00002000U /**< PPI Status */
+#define XSCUGIC_PPI_C12_MASK 0x00001000U /**< PPI Status */
+#define XSCUGIC_PPI_C11_MASK 0x00000800U /**< PPI Status */
+#define XSCUGIC_PPI_C10_MASK 0x00000400U /**< PPI Status */
+#define XSCUGIC_PPI_C09_MASK 0x00000200U /**< PPI Status */
+#define XSCUGIC_PPI_C08_MASK 0x00000100U /**< PPI Status */
+#define XSCUGIC_PPI_C07_MASK 0x00000080U /**< PPI Status */
+#define XSCUGIC_PPI_C06_MASK 0x00000040U /**< PPI Status */
+#define XSCUGIC_PPI_C05_MASK 0x00000020U /**< PPI Status */
+#define XSCUGIC_PPI_C04_MASK 0x00000010U /**< PPI Status */
+#define XSCUGIC_PPI_C03_MASK 0x00000008U /**< PPI Status */
+#define XSCUGIC_PPI_C02_MASK 0x00000004U /**< PPI Status */
+#define XSCUGIC_PPI_C01_MASK 0x00000002U /**< PPI Status */
+#define XSCUGIC_PPI_C00_MASK 0x00000001U /**< PPI Status */
+/* @} */
+
+/** @name SPI Status Register 0xd04-0xd7C
+ * Enables an external AMBA master to access the status of the SPI inputs.
+ * There are up to 63 registers if the maximum number of SPI inputs are
+ * configured.
+ * @{
+ */
+#define XSCUGIC_SPI_N_MASK 0x00000001U /**< Each bit corresponds to an SPI
+ input */
+/* @} */
+
+/** @name AHB Configuration Register
+ * Provides the status of the CFGBIGEND input signal and allows the endianness
+ * of the GIC to be set.
+ * @{
+ */
+#define XSCUGIC_AHB_END_MASK 0x00000004U /**< 0-GIC uses little Endian,
+ 1-GIC uses Big Endian */
+#define XSCUGIC_AHB_ENDOVR_MASK 0x00000002U /**< 0-Uses CFGBIGEND control,
+ 1-use the AHB_END bit */
+#define XSCUGIC_AHB_TIE_OFF_MASK 0x00000001U /**< State of CFGBIGEND */
+
+/* @} */
+
+/** @name Software Triggered Interrupt Register
+ * Controls issuing of software interrupts.
+ * @{
+ */
+#define XSCUGIC_SFI_SELFTRIG_MASK 0x02010000U
+#define XSCUGIC_SFI_TRIG_TRGFILT_MASK 0x03000000U /**< Target List filter
+ b00-Use the target List
+ b01-All CPUs except requester
+ b10-To Requester
+ b11-reserved */
+#define XSCUGIC_SFI_TRIG_CPU_MASK 0x00FF0000U /**< CPU Target list */
+#define XSCUGIC_SFI_TRIG_SATT_MASK 0x00008000U /**< 0= Use a secure interrupt */
+#define XSCUGIC_SFI_TRIG_INTID_MASK 0x0000000FU /**< Set to the INTID
+ signaled to the CPU*/
+/* @} */
+
+/** @name CPU Interface Register Map
+ *
+ * Define the offsets from the base address for all CPU registers of the
+ * interrupt controller, some registers may be reserved in the hardware device.
+ * @{
+ */
+#define XSCUGIC_CONTROL_OFFSET 0x00000000U /**< CPU Interface Control
+ Register */
+#define XSCUGIC_CPU_PRIOR_OFFSET 0x00000004U /**< Priority Mask Reg */
+#define XSCUGIC_BIN_PT_OFFSET 0x00000008U /**< Binary Point Register */
+#define XSCUGIC_INT_ACK_OFFSET 0x0000000CU /**< Interrupt ACK Reg */
+#define XSCUGIC_EOI_OFFSET 0x00000010U /**< End of Interrupt Reg */
+#define XSCUGIC_RUN_PRIOR_OFFSET 0x00000014U /**< Running Priority Reg */
+#define XSCUGIC_HI_PEND_OFFSET 0x00000018U /**< Highest Pending Interrupt
+ Register */
+#define XSCUGIC_ALIAS_BIN_PT_OFFSET 0x0000001CU /**< Aliased non-Secure
+ Binary Point Register */
+
+/**< 0x00000020 to 0x00000FBC are reserved and should not be read or written
+ * to. */
+/* @} */
+
+
+/** @name Control Register
+ * CPU Interface Control register definitions
+ * All bits are defined here although some are not available in the non-secure
+ * mode.
+ * @{
+ */
+#define XSCUGIC_CNTR_SBPR_MASK 0x00000010U /**< Secure Binary Pointer,
+ 0=separate registers,
+ 1=both use bin_pt_s */
+#define XSCUGIC_CNTR_FIQEN_MASK 0x00000008U /**< Use nFIQ_C for secure
+ interrupts,
+ 0= use IRQ for both,
+ 1=Use FIQ for secure, IRQ for non*/
+#define XSCUGIC_CNTR_ACKCTL_MASK 0x00000004U /**< Ack control for secure or non secure */
+#define XSCUGIC_CNTR_EN_NS_MASK 0x00000002U /**< Non Secure enable */
+#define XSCUGIC_CNTR_EN_S_MASK 0x00000001U /**< Secure enable, 0=Disabled, 1=Enabled */
+/* @} */
+
+/** @name Priority Mask Register
+ * Priority Mask register definitions
+ * The CPU interface does not send interrupt if the level of the interrupt is
+ * lower than the level of the register.
+ * @{
+ */
+/*#define XSCUGIC_PRIORITY_MASK 0x000000FFU*/ /**< All interrupts */
+/* @} */
+
+/** @name Binary Point Register
+ * Binary Point register definitions
+ * @{
+ */
+
+#define XSCUGIC_BIN_PT_MASK 0x00000007U /**< Binary point mask value
+ Value Secure Non-secure
+ b000 0xFE 0xFF
+ b001 0xFC 0xFE
+ b010 0xF8 0xFC
+ b011 0xF0 0xF8
+ b100 0xE0 0xF0
+ b101 0xC0 0xE0
+ b110 0x80 0xC0
+ b111 0x00 0x80
+ */
+/*@}*/
+
+/** @name Interrupt Acknowledge Register
+ * Interrupt Acknowledge register definitions
+ * Identifies the current Pending interrupt, and the CPU ID for software
+ * interrupts.
+ */
+#define XSCUGIC_ACK_INTID_MASK 0x000003FFU /**< Interrupt ID */
+#define XSCUGIC_CPUID_MASK 0x00000C00U /**< CPU ID */
+/* @} */
+
+/** @name End of Interrupt Register
+ * End of Interrupt register definitions
+ * Allows the CPU to signal the GIC when it completes an interrupt service
+ * routine.
+ */
+#define XSCUGIC_EOI_INTID_MASK 0x000003FFU /**< Interrupt ID */
+
+/* @} */
+
+/** @name Running Priority Register
+ * Running Priority register definitions
+ * Identifies the interrupt priority level of the highest priority active
+ * interrupt.
+ */
+#define XSCUGIC_RUN_PRIORITY_MASK 0x000000FFU /**< Interrupt Priority */
+/* @} */
+
+#if defined (GICv3)
+#define XSCUGIC_IROUTER_BASE_OFFSET 0x6000U
+#endif
+/*
+ * Highest Pending Interrupt register definitions
+ * Identifies the interrupt priority of the highest priority pending interrupt
+ */
+#define XSCUGIC_PEND_INTID_MASK 0x000003FFU /**< Pending Interrupt ID */
+/*#define XSCUGIC_CPUID_MASK 0x00000C00U */ /**< CPU ID */
+/* @} */
+#if defined (GICv3)
+/** @name ReDistributor Interface Register Map
+ *
+ * @{
+ */
+#define XSCUGIC_RDIST_OFFSET 0x80000U
+#define XSCUGIC_RDIST_BASE_ADDRESS (XPAR_SCUGIC_0_DIST_BASEADDR + XSCUGIC_RDIST_OFFSET)
+#define XSCUGIC_RDIST_SGI_PPI_OFFSET 0x90000U
+#define XSCUGIC_RDIST_SGI_PPI_BASE_ADDRESS (XPAR_SCUGIC_0_DIST_BASEADDR + XSCUGIC_RDIST_SGI_PPI_OFFSET)
+#define XSCUGIC_RDIST_ISENABLE_OFFSET 0x100U
+#define XSCUGIC_RDIST_IPRIORITYR_OFFSET 0x400U
+#define XSCUGIC_RDIST_IGROUPR_OFFSET 0x80U
+#define XSCUGIC_RDIST_GRPMODR_OFFSET 0xD00U
+#define XSCUGIC_RDIST_INT_CONFIG_OFFSET 0xC00U
+#define XSCUGIC_RDIST_WAKER_OFFSET 0x14U
+#define XSCUGIC_SGIR_EL1_INITID_SHIFT 24U
+
+/*
+ * GICR_IGROUPR register definitions
+ */
+#if EL3
+#define XSCUGIC_DEFAULT_SECURITY 0x0U
+#else
+#define XSCUGIC_DEFAULT_SECURITY 0xFFFFFFFFU
+#endif
+/*
+ * GICR_WAKER register definitions
+ */
+#define XSCUGIC_RDIST_WAKER_LOW_POWER_STATE_MASK 0x7
+#endif
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/****************************************************************************/
+/**
+*
+* Read the Interrupt Configuration Register offset for an interrupt id.
+*
+* @param InterruptID is the interrupt number.
+*
+* @return The 32-bit value of the offset
+*
+* @note
+*
+*****************************************************************************/
+#define XSCUGIC_INT_CFG_OFFSET_CALC(InterruptID) \
+ ((u32)XSCUGIC_INT_CFG_OFFSET + (((InterruptID)/16U) * 4U))
+
+/****************************************************************************/
+/**
+*
+* Read the Interrupt Priority Register offset for an interrupt id.
+*
+* @param InterruptID is the interrupt number.
+*
+* @return The 32-bit value of the offset
+*
+* @note
+*
+*****************************************************************************/
+#define XSCUGIC_PRIORITY_OFFSET_CALC(InterruptID) \
+ ((u32)XSCUGIC_PRIORITY_OFFSET + (((InterruptID)/4U) * 4U))
+
+/****************************************************************************/
+/**
+*
+* Read the Interrupt Routing Register offset for an interrupt id.
+*
+* @param InterruptID is the interrupt number.
+*
+* @return The 32-bit value of the offset
+*
+* @note
+*
+*****************************************************************************/
+#define XSCUGIC_IROUTER_OFFSET_CALC(InterruptID) \
+ ((u32)XSCUGIC_IROUTER_BASE_OFFSET + (InterruptID * 8))
+
+/****************************************************************************/
+/**
+*
+* Read the SPI Target Register offset for an interrupt id.
+*
+* @param InterruptID is the interrupt number.
+*
+* @return The 32-bit value of the offset
+*
+* @note
+*
+*****************************************************************************/
+#define XSCUGIC_SPI_TARGET_OFFSET_CALC(InterruptID) \
+ ((u32)XSCUGIC_SPI_TARGET_OFFSET + (((InterruptID)/4U) * 4U))
+/****************************************************************************/
+/**
+*
+* Read the SPI Target Register offset for an interrupt id.
+*
+* @param InterruptID is the interrupt number.
+*
+* @return The 32-bit value of the offset
+*
+* @note
+*
+*****************************************************************************/
+#define XSCUGIC_SECURITY_TARGET_OFFSET_CALC(InterruptID) \
+ ((u32)XSCUGIC_SECURITY_OFFSET + (((InterruptID)/32U)*4U))
+
+/****************************************************************************/
+/**
+*
+* Read the Re-distributor Interrupt configuration register offset
+*
+* @param InterruptID is the interrupt number.
+*
+* @return The 32-bit value of the offset
+*
+* @note
+*
+*****************************************************************************/
+#define XSCUGIC_RDIST_INT_CONFIG_OFFSET_CALC(InterruptID) \
+ ((u32)XSCUGIC_RDIST_INT_CONFIG_OFFSET + ((InterruptID /16)*4))
+
+/****************************************************************************/
+/**
+*
+* Read the Re-distributor Interrupt Priority register offset
+*
+* @param InterruptID is the interrupt number.
+*
+* @return The 32-bit value of the offset
+*
+* @note
+*
+*****************************************************************************/
+#define XSCUGIC_RDIST_INT_PRIORITY_OFFSET_CALC(InterruptID) \
+ ((u32)XSCUGIC_RDIST_IPRIORITYR_OFFSET + (InterruptID * 4))
+/****************************************************************************/
+/**
+*
+* Read the Interrupt Clear-Enable Register offset for an interrupt ID
+*
+* @param Register is the register offset for the clear/enable bank.
+* @param InterruptID is the interrupt number.
+*
+* @return The 32-bit value of the offset
+*
+* @note
+*
+*****************************************************************************/
+#define XSCUGIC_EN_DIS_OFFSET_CALC(Register, InterruptID) \
+ ((Register) + (((InterruptID)/32U) * 4U))
+
+/****************************************************************************/
+/**
+*
+* Read the given Intc register.
+*
+* @param BaseAddress is the base address of the device.
+* @param RegOffset is the register offset to be read
+*
+* @return The 32-bit value of the register
+*
+* @note
+* C-style signature:
+* u32 XScuGic_ReadReg(u32 BaseAddress, u32 RegOffset)
+*
+*****************************************************************************/
+#define XScuGic_ReadReg(BaseAddress, RegOffset) \
+ (Xil_In32((BaseAddress) + (RegOffset)))
+
+
+/****************************************************************************/
+/**
+*
+* Write the given Intc register.
+*
+* @param BaseAddress is the base address of the device.
+* @param RegOffset is the register offset to be written
+* @param Data is the 32-bit value to write to the register
+*
+* @return None.
+*
+* @note
+* C-style signature:
+* void XScuGic_WriteReg(u32 BaseAddress, u32 RegOffset, u32 Data)
+*
+*****************************************************************************/
+#define XScuGic_WriteReg(BaseAddress, RegOffset, Data) \
+ (Xil_Out32(((BaseAddress) + (RegOffset)), ((u32)(Data))))
+
+
+/************************** Function Prototypes ******************************/
+
+void XScuGic_DeviceInterruptHandler(void *DeviceId);
+s32 XScuGic_DeviceInitialize(u32 DeviceId);
+void XScuGic_RegisterHandler(u32 BaseAddress, s32 InterruptID,
+ Xil_InterruptHandler Handler, void *CallBackRef);
+void XScuGic_SetPriTrigTypeByDistAddr(u32 DistBaseAddress, u32 Int_Id,
+ u8 Priority, u8 Trigger);
+void XScuGic_GetPriTrigTypeByDistAddr(u32 DistBaseAddress, u32 Int_Id,
+ u8 *Priority, u8 *Trigger);
+void XScuGic_InterruptMapFromCpuByDistAddr(u32 DistBaseAddress,
+ u8 Cpu_Id, u32 Int_Id);
+void XScuGic_InterruptUnmapFromCpuByDistAddr(u32 DistBaseAddress,
+ u8 Cpu_Id, u32 Int_Id);
+void XScuGic_UnmapAllInterruptsFromCpuByDistAddr(u32 DistBaseAddress,
+ u8 Cpu_Id);
+void XScuGic_EnableIntr (u32 DistBaseAddress, u32 Int_Id);
+void XScuGic_DisableIntr (u32 DistBaseAddress, u32 Int_Id);
+/************************** Variable Definitions *****************************/
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* end of protection macro */
+/** @} */
diff --git a/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/include/xscutimer.h b/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/include/xscutimer.h
new file mode 100644
index 0000000..a3c0be8
--- /dev/null
+++ b/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/include/xscutimer.h
@@ -0,0 +1,362 @@
+/******************************************************************************
+*
+* Copyright (C) 2010 - 2015 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+* THE SOFTWARE.
+*
+*
+*
+******************************************************************************/
+/****************************************************************************/
+/**
+*
+* @file xscutimer.h
+* @addtogroup scutimer_v2_1
+* @{
+* @details
+*
+* The timer driver supports the Cortex A9 private timer.
+*
+* The timer driver supports the following features:
+* - Normal mode and Auto reload mode
+* - Interrupts (Interrupt handler is not provided in this driver. Application
+* has to register it's own handler)
+*
+* <b> Initialization and Configuration </b>
+*
+* The device driver enables higher layer software (e.g., an application) to
+* communicate with the Timer.
+*
+* XScuTimer_CfgInitialize() API is used to initialize the Timer. The
+* user needs to first call the XScuTimer_LookupConfig() API which returns
+* the Configuration structure pointer which is passed as a parameter to
+* the XScuTimer_CfgInitialize() API.
+*
+* <b> Interrupts </b>
+*
+* The Timer hardware supports interrupts.
+*
+* This driver does not provide a Interrupt Service Routine (ISR) for the device.
+* It is the responsibility of the application to provide one if needed. Refer to
+* the interrupt example provided with this driver for details on using the
+* Timer in interrupt mode.
+*
+* <b> Virtual Memory </b>
+*
+* This driver supports Virtual Memory. The RTOS is responsible for calculating
+* the correct device base address in Virtual Memory space.
+*
+* <b> Threads </b>
+*
+* This driver is not thread safe. Any needs for threads or thread mutual
+* exclusion must be satisfied by the layer above this driver.
+*
+* <b> Asserts </b>
+*
+* Asserts are used within all Xilinx drivers to enforce constraints on argument
+* values. Asserts can be turned off on a system-wide basis by defining, at
+* compile time, the NDEBUG identifier. By default, asserts are turned on and it
+* is recommended that users leave asserts on during development.
+*
+* <b> Building the driver </b>
+*
+* The XScuTimer driver is composed of several source files. This allows the user
+* to build and link only those parts of the driver that are necessary.
+*
+* <br><br>
+*
+* NOTE:
+* The timer is not a part of the snoop control unit as indicated by the
+* prefix "scu" in the name of the driver.
+* It is an independent module in APU.
+*
+* <pre>
+* MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ----- --- -------- ---------------------------------------------
+* 1.00a nm 03/10/10 First release
+* 1.02a sg 07/17/12 Included xil_assert.h for CR 667947. This is an issue
+* when the xstatus.h in the common driver overwrites
+* the xstatus.h of the standalone BSP during the
+* libgen.
+* 2.1 sk 02/26/15 Modified the code for MISRA-C:2012 compliance.
+* ms 03/17/17 Added readme.txt file in examples folder for doxygen
+* generation.
+* </pre>
+*
+******************************************************************************/
+#ifndef XSCUTIMER_H /* prevent circular inclusions */
+#define XSCUTIMER_H /* by using protection macros */
+
+/***************************** Include Files *********************************/
+
+#include "xstatus.h"
+#include "xscutimer_hw.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/************************** Constant Definitions *****************************/
+
+/**************************** Type Definitions *******************************/
+
+/**
+ * This typedef contains configuration information for the device.
+ */
+typedef struct {
+ u16 DeviceId; /**< Unique ID of device */
+ u32 BaseAddr; /**< Base address of the device */
+} XScuTimer_Config;
+
+/**
+ * The XScuTimer driver instance data. The user is required to allocate a
+ * variable of this type for every timer device in the system.
+ * A pointer to a variable of this type is then passed to the driver API
+ * functions.
+ */
+typedef struct {
+ XScuTimer_Config Config; /**< Hardware Configuration */
+ u32 IsReady; /**< Device is initialized and ready */
+ u32 IsStarted; /**< Device timer is running */
+} XScuTimer;
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/****************************************************************************/
+/**
+*
+* Check if the timer has expired.
+*
+* @param InstancePtr is a pointer to the XScuTimer instance.
+*
+* @return
+* - TRUE if the timer has expired.
+* - FALSE if the timer has not expired.
+*
+* @note C-style signature:
+* int XScuTimer_IsExpired(XScuTimer *InstancePtr)
+*
+******************************************************************************/
+#define XScuTimer_IsExpired(InstancePtr) \
+ ((XScuTimer_ReadReg((InstancePtr)->Config.BaseAddr, \
+ XSCUTIMER_ISR_OFFSET) & \
+ XSCUTIMER_ISR_EVENT_FLAG_MASK) == \
+ XSCUTIMER_ISR_EVENT_FLAG_MASK)
+
+/****************************************************************************/
+/**
+*
+* Re-start the timer. This macro will read the timer load register
+* and writes the same value to load register to update the counter register.
+*
+* @param InstancePtr is a pointer to the XScuTimer instance.
+*
+* @return None.
+*
+* @note C-style signature:
+* void XScuTimer_RestartTimer(XScuTimer *InstancePtr)
+*
+******************************************************************************/
+#define XScuTimer_RestartTimer(InstancePtr) \
+ XScuTimer_LoadTimer((InstancePtr), \
+ XScuTimer_ReadReg((InstancePtr)->Config.BaseAddr, \
+ XSCUTIMER_LOAD_OFFSET))
+
+/****************************************************************************/
+/**
+*
+* Write to the timer load register. This will also update the
+* timer counter register with the new value. This macro can be used to
+* change the time-out value.
+*
+* @param InstancePtr is a pointer to the XScuTimer instance.
+* @param Value is the count to be loaded in to the load register.
+*
+* @return None.
+*
+* @note C-style signature:
+* void XScuTimer_LoadTimer(XScuTimer *InstancePtr, u32 Value)
+*
+******************************************************************************/
+#define XScuTimer_LoadTimer(InstancePtr, Value) \
+ XScuTimer_WriteReg((InstancePtr)->Config.BaseAddr, \
+ XSCUTIMER_LOAD_OFFSET, (Value))
+
+/****************************************************************************/
+/**
+*
+* Returns the current timer counter register value. It can be called at any
+* time.
+*
+* @param InstancePtr is a pointer to the XScuTimer instance.
+*
+* @return Contents of the timer counter register.
+*
+* @note C-style signature:
+ u32 XScuTimer_GetCounterValue(XScuTimer *InstancePtr)
+*
+******************************************************************************/
+#define XScuTimer_GetCounterValue(InstancePtr) \
+ XScuTimer_ReadReg((InstancePtr)->Config.BaseAddr, \
+ XSCUTIMER_COUNTER_OFFSET)
+
+/****************************************************************************/
+/**
+*
+* Enable auto-reload mode.
+*
+* @param InstancePtr is a pointer to the XScuTimer instance.
+*
+* @return None.
+*
+* @note C-style signature:
+* void XScuTimer_EnableAutoReload(XScuTimer *InstancePtr)
+*
+******************************************************************************/
+#define XScuTimer_EnableAutoReload(InstancePtr) \
+ XScuTimer_WriteReg((InstancePtr)->Config.BaseAddr, \
+ XSCUTIMER_CONTROL_OFFSET, \
+ (XScuTimer_ReadReg((InstancePtr)->Config.BaseAddr, \
+ XSCUTIMER_CONTROL_OFFSET) | \
+ XSCUTIMER_CONTROL_AUTO_RELOAD_MASK))
+
+/****************************************************************************/
+/**
+*
+* Disable auto-reload mode.
+*
+* @param InstancePtr is a pointer to the XScuTimer instance.
+*
+* @return None.
+*
+* @note C-style signature:
+* void XScuTimer_DisableAutoReload(XScuTimer *InstancePtr)
+*
+******************************************************************************/
+#define XScuTimer_DisableAutoReload(InstancePtr) \
+ XScuTimer_WriteReg((InstancePtr)->Config.BaseAddr, \
+ XSCUTIMER_CONTROL_OFFSET, \
+ (XScuTimer_ReadReg((InstancePtr)->Config.BaseAddr, \
+ XSCUTIMER_CONTROL_OFFSET) & \
+ ~(XSCUTIMER_CONTROL_AUTO_RELOAD_MASK)))
+
+/****************************************************************************/
+/**
+*
+* Enable the Timer interrupt.
+*
+* @param InstancePtr is a pointer to the XScuTimer instance.
+*
+* @return None.
+*
+* @note C-style signature:
+* void XScuTimer_EnableInterrupt(XScuTimer *InstancePtr)
+*
+******************************************************************************/
+#define XScuTimer_EnableInterrupt(InstancePtr) \
+ XScuTimer_WriteReg((InstancePtr)->Config.BaseAddr, \
+ XSCUTIMER_CONTROL_OFFSET, \
+ (XScuTimer_ReadReg((InstancePtr)->Config.BaseAddr, \
+ XSCUTIMER_CONTROL_OFFSET) | \
+ XSCUTIMER_CONTROL_IRQ_ENABLE_MASK))
+
+/****************************************************************************/
+/**
+*
+* Disable the Timer interrupt.
+*
+* @param InstancePtr is a pointer to the XScuTimer instance.
+*
+* @return None.
+*
+* @note C-style signature:
+* void XScuTimer_DisableInterrupt(XScuTimer *InstancePtr)
+*
+******************************************************************************/
+#define XScuTimer_DisableInterrupt(InstancePtr) \
+ XScuTimer_WriteReg((InstancePtr)->Config.BaseAddr, \
+ XSCUTIMER_CONTROL_OFFSET, \
+ (XScuTimer_ReadReg((InstancePtr)->Config.BaseAddr, \
+ XSCUTIMER_CONTROL_OFFSET) & \
+ ~(XSCUTIMER_CONTROL_IRQ_ENABLE_MASK)))
+
+/*****************************************************************************/
+/**
+*
+* This function reads the interrupt status.
+*
+* @param InstancePtr is a pointer to the XScuTimer instance.
+*
+* @return None.
+*
+* @note C-style signature:
+* void XScuTimer_GetInterruptStatus(XScuTimer *InstancePtr)
+*
+******************************************************************************/
+#define XScuTimer_GetInterruptStatus(InstancePtr) \
+ XScuTimer_ReadReg((InstancePtr)->Config.BaseAddr, \
+ XSCUTIMER_ISR_OFFSET)
+
+/*****************************************************************************/
+/**
+*
+* This function clears the interrupt status.
+*
+* @param InstancePtr is a pointer to the XScuTimer instance.
+*
+* @return None.
+*
+* @note C-style signature:
+* void XScuTimer_ClearInterruptStatus(XScuTimer *InstancePtr)
+*
+******************************************************************************/
+#define XScuTimer_ClearInterruptStatus(InstancePtr) \
+ XScuTimer_WriteReg((InstancePtr)->Config.BaseAddr, \
+ XSCUTIMER_ISR_OFFSET, XSCUTIMER_ISR_EVENT_FLAG_MASK)
+
+/************************** Function Prototypes ******************************/
+
+/*
+ * Lookup configuration in xscutimer_sinit.c
+ */
+XScuTimer_Config *XScuTimer_LookupConfig(u16 DeviceId);
+
+/*
+ * Selftest function in xscutimer_selftest.c
+ */
+s32 XScuTimer_SelfTest(XScuTimer *InstancePtr);
+
+/*
+ * Interface functions in xscutimer.c
+ */
+s32 XScuTimer_CfgInitialize(XScuTimer *InstancePtr,
+ XScuTimer_Config *ConfigPtr, u32 EffectiveAddress);
+void XScuTimer_Start(XScuTimer *InstancePtr);
+void XScuTimer_Stop(XScuTimer *InstancePtr);
+void XScuTimer_SetPrescaler(XScuTimer *InstancePtr, u8 PrescalerValue);
+u8 XScuTimer_GetPrescaler(XScuTimer *InstancePtr);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* end of protection macro */
+/** @} */
diff --git a/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/include/xscutimer_hw.h b/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/include/xscutimer_hw.h
new file mode 100644
index 0000000..a8b2302
--- /dev/null
+++ b/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/include/xscutimer_hw.h
@@ -0,0 +1,281 @@
+/******************************************************************************
+*
+* Copyright (C) 2010 - 2015 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+* THE SOFTWARE.
+*
+*
+*
+******************************************************************************/
+/****************************************************************************/
+/**
+*
+* @file xscutimer_hw.h
+* @addtogroup scutimer_v2_1
+* @{
+*
+* This file contains the hardware interface to the Timer.
+*
+* <pre>
+* MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ----- --- -------- ---------------------------------------------
+* 1.00a nm 03/10/10 First release
+* 1.01a sdm 02/02/12 Added low level macros to read/write load, counter, control
+* and interrupt registers
+* 1.02a sg 07/17/12 Included xil_assert.h for CR 667947. This is an issue
+* when the xstatus.h in the common driver overwrites
+* the xstatus.h of the standalone BSP during the
+* libgen.
+* 2.1 sk 02/26/15 Modified the code for MISRA-C:2012 compliance.
+* </pre>
+*
+******************************************************************************/
+#ifndef XSCUTIMER_HW_H /* prevent circular inclusions */
+#define XSCUTIMER_HW_H /* by using protection macros */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/***************************** Include Files *********************************/
+#include "xil_types.h"
+#include "xil_io.h"
+#include "xil_assert.h"
+/************************** Constant Definitions *****************************/
+
+/** @name Register Map
+ * Offsets of registers from the start of the device
+ * @{
+ */
+
+#define XSCUTIMER_LOAD_OFFSET 0x00U /**< Timer Load Register */
+#define XSCUTIMER_COUNTER_OFFSET 0x04U /**< Timer Counter Register */
+#define XSCUTIMER_CONTROL_OFFSET 0x08U /**< Timer Control Register */
+#define XSCUTIMER_ISR_OFFSET 0x0CU /**< Timer Interrupt
+ Status Register */
+/* @} */
+
+/** @name Timer Control register
+ * This register bits control the prescaler, Intr enable,
+ * auto-reload and timer enable.
+ * @{
+ */
+
+#define XSCUTIMER_CONTROL_PRESCALER_MASK 0x0000FF00U /**< Prescaler */
+#define XSCUTIMER_CONTROL_PRESCALER_SHIFT 8U
+#define XSCUTIMER_CONTROL_IRQ_ENABLE_MASK 0x00000004U /**< Intr enable */
+#define XSCUTIMER_CONTROL_AUTO_RELOAD_MASK 0x00000002U /**< Auto-reload */
+#define XSCUTIMER_CONTROL_ENABLE_MASK 0x00000001U /**< Timer enable */
+/* @} */
+
+/** @name Interrupt Status register
+ * This register indicates the Timer counter register has reached zero.
+ * @{
+ */
+
+#define XSCUTIMER_ISR_EVENT_FLAG_MASK 0x00000001U /**< Event flag */
+/*@}*/
+
+/**************************** Type Definitions *******************************/
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/****************************************************************************/
+/**
+*
+* Write to the timer load register. This will also update the
+* timer counter register with the new value. This macro can be used to
+* change the time-out value.
+*
+* @param BaseAddr is the base address of the scu timer.
+* @param Value is the count to be loaded in to the load register.
+*
+* @return None.
+*
+* @note C-style signature:
+* void XScuTimer_SetLoadReg(u32 BaseAddr, u32 Value)
+*
+******************************************************************************/
+#define XScuTimer_SetLoadReg(BaseAddr, Value) \
+ XScuTimer_WriteReg(BaseAddr, XSCUTIMER_LOAD_OFFSET, (Value))
+
+/****************************************************************************/
+/**
+*
+* Returns the current timer load register value.
+*
+* @param BaseAddr is the base address of the scu timer.
+*
+* @return Contents of the timer load register.
+*
+* @note C-style signature:
+* u32 XScuTimer_GetLoadReg(u32 BaseAddr)
+*
+******************************************************************************/
+#define XScuTimer_GetLoadReg(BaseAddr) \
+ XScuTimer_ReadReg(BaseAddr, XSCUTIMER_LOAD_OFFSET)
+
+/****************************************************************************/
+/**
+*
+* Write to the timer counter register.
+*
+* @param BaseAddr is the base address of the scu timer.
+* @param Value is the count to be loaded in to the counter register.
+*
+* @return None.
+*
+* @note C-style signature:
+* void XScuTimer_SetCounterReg(u32 BaseAddr, u32 Value)
+*
+******************************************************************************/
+#define XScuTimer_SetCounterReg(BaseAddr, Value) \
+ XScuTimer_WriteReg(BaseAddr, XSCUTIMER_COUNTER_OFFSET, (Value))
+
+/****************************************************************************/
+/**
+*
+* Returns the current timer counter register value.
+*
+* @param BaseAddr is the base address of the scu timer.
+*
+* @return Contents of the timer counter register.
+*
+* @note C-style signature:
+ u32 XScuTimer_GetCounterReg(u32 BaseAddr)
+*
+******************************************************************************/
+#define XScuTimer_GetCounterReg(BaseAddr) \
+ XScuTimer_ReadReg(BaseAddr, XSCUTIMER_COUNTER_OFFSET)
+
+/****************************************************************************/
+/**
+*
+* Write to the timer load register. This will also update the
+* timer counter register with the new value. This macro can be used to
+* change the time-out value.
+*
+* @param BaseAddr is the base address of the scu timer.
+* @param Value is the count to be loaded in to the load register.
+*
+* @return None.
+*
+* @note C-style signature:
+* void XScuTimer_SetControlReg(u32 BaseAddr, u32 Value)
+*
+******************************************************************************/
+#define XScuTimer_SetControlReg(BaseAddr, Value) \
+ XScuTimer_WriteReg(BaseAddr, XSCUTIMER_CONTROL_OFFSET, (Value))
+
+/****************************************************************************/
+/**
+*
+* Returns the current timer load register value.
+*
+* @param BaseAddr is the base address of the scu timer.
+*
+* @return Contents of the timer load register.
+*
+* @note C-style signature:
+ u32 XScuTimer_GetControlReg(u32 BaseAddr)
+*
+******************************************************************************/
+#define XScuTimer_GetControlReg(BaseAddr) \
+ XScuTimer_ReadReg(BaseAddr, XSCUTIMER_CONTROL_OFFSET)
+
+/****************************************************************************/
+/**
+*
+* Write to the timer counter register.
+*
+* @param BaseAddr is the base address of the scu timer.
+* @param Value is the count to be loaded in to the counter register.
+*
+* @return None.
+*
+* @note C-style signature:
+* void XScuTimer_SetIntrReg(u32 BaseAddr, u32 Value)
+*
+******************************************************************************/
+#define XScuTimer_SetIntrReg(BaseAddr, Value) \
+ XScuTimer_WriteReg(BaseAddr, XSCUTIMER_ISR_OFFSET, (Value))
+
+/****************************************************************************/
+/**
+*
+* Returns the current timer counter register value.
+*
+* @param BaseAddr is the base address of the scu timer.
+*
+* @return Contents of the timer counter register.
+*
+* @note C-style signature:
+ u32 XScuTimer_GetIntrReg(u32 BaseAddr)
+*
+******************************************************************************/
+#define XScuTimer_GetIntrReg(BaseAddr) \
+ XScuTimer_ReadReg(BaseAddr, XSCUTIMER_ISR_OFFSET)
+
+/****************************************************************************/
+/**
+*
+* Read from the given Timer register.
+*
+* @param BaseAddr is the base address of the device
+* @param RegOffset is the register offset to be read
+*
+* @return The 32-bit value of the register
+*
+* @note C-style signature:
+* u32 XScuTimer_ReadReg(u32 BaseAddr, u32 RegOffset)
+*
+*****************************************************************************/
+#define XScuTimer_ReadReg(BaseAddr, RegOffset) \
+ Xil_In32((BaseAddr) + (RegOffset))
+
+/****************************************************************************/
+/**
+*
+* Write to the given Timer register.
+*
+* @param BaseAddr is the base address of the device
+* @param RegOffset is the register offset to be written
+* @param Data is the 32-bit value to write to the register
+*
+* @return None.
+*
+* @note C-style signature:
+* void XScuTimer_WriteReg(u32 BaseAddr, u32 RegOffset, u32 Data)
+*
+*****************************************************************************/
+#define XScuTimer_WriteReg(BaseAddr, RegOffset, Data) \
+ Xil_Out32((BaseAddr) + (RegOffset), (Data))
+
+/************************** Function Prototypes ******************************/
+
+/************************** Variable Definitions *****************************/
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* end of protection macro */
+/** @} */
diff --git a/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/include/xscuwdt.h b/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/include/xscuwdt.h
new file mode 100644
index 0000000..61a73dd
--- /dev/null
+++ b/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/include/xscuwdt.h
@@ -0,0 +1,377 @@
+/******************************************************************************
+*
+* Copyright (C) 2010 - 2015 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+* THE SOFTWARE.
+*
+*
+*
+******************************************************************************/
+/****************************************************************************/
+/**
+*
+* @file xscuwdt.h
+* @addtogroup scuwdt_v2_1
+* @{
+* @details
+*
+* The Xilinx SCU watchdog timer driver (XScuWdt) supports the Xilinx SCU private
+* watchdog timer hardware.
+*
+* The XScuWdt driver supports the following features:
+* - Watchdog mode
+* - Timer mode
+* - Auto reload (timer mode only)
+*
+* The watchdog counter register is a down counter and starts decrementing when
+* the watchdog is started.
+* In watchdog mode, when the counter reaches 0, the Reset flag is set in the
+* Reset status register and the WDRESETREQ pin is asserted, causing a system
+* reset. The Reset flag is not reset by normal processor reset and is cleared
+* when written with a value of 1. This enables the user to differentiate a
+* normal reset and a reset caused by watchdog time-out. The user needs to call
+* XScuWdt_RestartWdt() periodically, to avoid the watchdog from being timed-out.
+*
+* The IsWdtExpired function can be used to check if the watchdog was the cause
+* of the last reset. In this situation, call Initialize then call IsWdtExpired.
+* If the result is true, watchdog timeout caused the last system reset. The
+* application then needs to clear the Reset flag.
+*
+* In timer mode, when the counter reaches 0, the Event flag is set in the
+* Interrupt status register and if interrupts are enabled, interrupt ID 30 is
+* set as pending in the interrupt distributor. The IsTimerExpired function
+* is used to check if the watchdog counter has decremented to 0 in timer mode.
+* If auto-reload mode is enabled, the Counter register is automatically reloaded
+* from the Load register.
+*
+* <b> Initialization and Configuration </b>
+*
+* The device driver enables higher layer software (e.g., an application) to
+* communicate with the Watchdog Timer.
+*
+* XScuWdt_CfgInitialize() API is used to initialize the Watchdog Timer. The
+* user needs to first call the XScuWdt_LookupConfig() API which returns
+* the Configuration structure pointer which is passed as a parameter to
+* the XScuWdt_CfgInitialize() API.
+*
+* <b>Interrupts</b>
+*
+* The SCU Watchdog Timer supports interrupts in Timer mode.
+*
+* This driver does not provide a Interrupt Service Routine (ISR) for the device.
+* It is the responsibility of the application to provide one if needed. Refer to
+* the interrupt example provided with this driver for details on using the
+* Timer in interrupt mode.
+*
+* <b> Virtual Memory </b>
+*
+* This driver supports Virtual Memory. The RTOS is responsible for calculating
+* the correct device base address in Virtual Memory space.
+*
+* <b> Threads </b>
+*
+* This driver is not thread safe. Any needs for threads or thread mutual
+* exclusion must be satisfied by the layer above this driver.
+*
+* <b> Asserts </b>
+*
+* Asserts are used within all Xilinx drivers to enforce constraints on argument
+* values. Asserts can be turned off on a system-wide basis by defining, at
+* compile time, the NDEBUG identifier. By default, asserts are turned on and it
+* is recommended that users leave asserts on during development.
+*
+* <b> Building the driver </b>
+*
+* The XScuWdt driver is composed of several source files. This allows the user
+* to build and link only those parts of the driver that are necessary.
+*
+* <br><br>
+*
+* NOTE:
+* The watchdog timer is not a part of the snoop control unit as indicated
+* by the prefix "scu" in the name of the driver.
+* It is an independent module in APU.
+*
+* <pre>
+* MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ----- --- -------- ---------------------------------------------
+* 1.00a sdm 01/15/10 First release
+* 1.02a sg 07/17/12 Included xil_assert.h for CR 667947. This is an issue
+* when the xstatus.h in the common driver overwrites
+* the xstatus.h of the standalone BSP during the
+* libgen.
+* 2.1 sk 02/26/15 Modified the code for MISRA-C:2012 compliance.
+* ms 03/17/17 Added readme.txt file in examples folder for doxygen
+* generation.
+* </pre>
+*
+******************************************************************************/
+#ifndef XSCUWDT_H /* prevent circular inclusions */
+#define XSCUWDT_H /* by using protection macros */
+
+/***************************** Include Files *********************************/
+
+#include "xstatus.h"
+#include "xscuwdt_hw.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/************************** Constant Definitions *****************************/
+
+/**************************** Type Definitions *******************************/
+
+/**
+ * This typedef contains configuration information for the device.
+ */
+typedef struct {
+ u16 DeviceId; /**< Unique ID of device */
+ u32 BaseAddr; /**< Base address of the device */
+} XScuWdt_Config;
+
+/**
+ * The XScuWdt driver instance data. The user is required to allocate a
+ * variable of this type for every watchdog/timer device in the system.
+ * A pointer to a variable of this type is then passed to the driver API
+ * functions.
+ */
+typedef struct {
+ XScuWdt_Config Config;/**< Hardware Configuration */
+ u32 IsReady; /**< Device is initialized and ready */
+ u32 IsStarted; /**< Device watchdog timer is running */
+} XScuWdt;
+
+/***************** Macros (Inline Functions) Definitions *********************/
+/****************************************************************************/
+/**
+*
+* This function is used to check if the watchdog has timed-out and the last
+* reset was caused by the watchdog reset.
+*
+* @param InstancePtr is a pointer to the XScuWdt instance.
+*
+* @return
+* - TRUE if the watchdog has expired.
+* - FALSE if the watchdog has not expired.
+*
+* @note C-style signature:
+* int XScuWdt_IsWdtExpired(XScuWdt *InstancePtr)
+*
+******************************************************************************/
+#define XScuWdt_IsWdtExpired(InstancePtr) \
+ ((XScuWdt_ReadReg((InstancePtr)->Config.BaseAddr, \
+ XSCUWDT_RST_STS_OFFSET) & \
+ XSCUWDT_RST_STS_RESET_FLAG_MASK) == XSCUWDT_RST_STS_RESET_FLAG_MASK)
+
+/****************************************************************************/
+/**
+*
+* This function is used to check if the watchdog counter has reached 0 in timer
+* mode.
+*
+* @param InstancePtr is a pointer to the XScuWdt instance.
+*
+* @return
+* - TRUE if the watchdog has expired.
+* - FALSE if the watchdog has not expired.
+*
+* @note C-style signature:
+* int XScuWdt_IsTimerExpired(XScuWdt *InstancePtr)
+*
+******************************************************************************/
+#define XScuWdt_IsTimerExpired(InstancePtr) \
+ ((XScuWdt_ReadReg((InstancePtr)->Config.BaseAddr, \
+ XSCUWDT_ISR_OFFSET) & \
+ XSCUWDT_ISR_EVENT_FLAG_MASK) == XSCUWDT_ISR_EVENT_FLAG_MASK)
+
+/****************************************************************************/
+/**
+*
+* Re-start the watchdog timer. This macro will read the watchdog load register
+* and write the same value to load register to update the counter register.
+* An application needs to call this function periodically to keep the watchdog
+* from asserting the WDRESETREQ reset request output pin.
+*
+* @param InstancePtr is a pointer to the XScuWdt instance.
+*
+* @return None.
+*
+* @note C-style signature:
+* void XScuWdt_RestartWdt(XScuWdt *InstancePtr)
+*
+******************************************************************************/
+#define XScuWdt_RestartWdt(InstancePtr) \
+ XScuWdt_LoadWdt((InstancePtr), \
+ (XScuWdt_ReadReg((InstancePtr)->Config.BaseAddr, \
+ XSCUWDT_LOAD_OFFSET)))
+
+/****************************************************************************/
+/**
+*
+* Write to the watchdog timer load register. This will also update the
+* watchdog counter register with the new value. This macro can be used to
+* change the time-out value.
+*
+* @param InstancePtr is a pointer to the XScuWdt instance.
+* @param Value is the value to be written to the Watchdog Load register.
+*
+* @return None.
+*
+* @note C-style signature:
+* void XScuWdt_LoadWdt(XScuWdt *InstancePtr, u32 Value)
+*
+******************************************************************************/
+#define XScuWdt_LoadWdt(InstancePtr, Value) \
+ XScuWdt_WriteReg((InstancePtr)->Config.BaseAddr, \
+ XSCUWDT_LOAD_OFFSET, (Value))
+
+/****************************************************************************/
+/**
+*
+* Put the watchdog timer in Watchdog mode by setting the WD mode bit of the
+* Watchdog control register.
+*
+* @param InstancePtr is a pointer to the XScuWdt instance.
+*
+* @return None.
+*
+* @note C-style signature:
+* void XScuWdt_SetWdMode(XScuWdt *InstancePtr)
+*
+******************************************************************************/
+#define XScuWdt_SetWdMode(InstancePtr) \
+ XScuWdt_WriteReg((InstancePtr)->Config.BaseAddr, \
+ XSCUWDT_CONTROL_OFFSET, \
+ (XScuWdt_ReadReg((InstancePtr)->Config.BaseAddr, \
+ XSCUWDT_CONTROL_OFFSET) | \
+ (XSCUWDT_CONTROL_WD_MODE_MASK)))
+
+/****************************************************************************/
+/**
+*
+* Put the watchdog timer in Timer mode by writing 0x12345678 and 0x87654321
+* successively to the Watchdog Disable Register.
+* The software must write 0x12345678 and 0x87654321 successively to the
+* Watchdog Disable Register so that the watchdog mode bit in the Watchdog
+* Control Register is set to zero.
+*
+* @param InstancePtr is a pointer to the XScuWdt instance.
+*
+* @return None.
+*
+* @note C-style signature:
+* void XScuWdt_SetTimerMode(XScuWdt *InstancePtr)
+*
+******************************************************************************/
+#define XScuWdt_SetTimerMode(InstancePtr) \
+{ \
+ XScuWdt_WriteReg((InstancePtr)->Config.BaseAddr, \
+ XSCUWDT_DISABLE_OFFSET, \
+ XSCUWDT_DISABLE_VALUE1); \
+ XScuWdt_WriteReg((InstancePtr)->Config.BaseAddr, \
+ XSCUWDT_DISABLE_OFFSET, \
+ XSCUWDT_DISABLE_VALUE2); \
+}
+
+/****************************************************************************/
+/**
+*
+* Get the contents of the watchdog control register.
+*
+* @param InstancePtr is a pointer to the XScuWdt instance.
+*
+* @return Contents of the watchdog control register.
+*
+* @note C-style signature:
+ u32 XScuWdt_GetControlReg(XScuWdt *InstancePtr)
+*
+******************************************************************************/
+#define XScuWdt_GetControlReg(InstancePtr) \
+ XScuWdt_ReadReg((InstancePtr)->Config.BaseAddr, \
+ XSCUWDT_CONTROL_OFFSET)
+
+/****************************************************************************/
+/**
+*
+* Write to the watchdog control register.
+*
+* @param InstancePtr is a pointer to the XScuWdt instance.
+* @param ControlReg is the value to be written to the watchdog control
+* register.
+*
+* @return None.
+*
+* @note C-style signature:
+ void XScuWdt_SetControlReg(XScuWdt *InstancePtr, u32 ControlReg)
+*
+******************************************************************************/
+#define XScuWdt_SetControlReg(InstancePtr, ControlReg) \
+ XScuWdt_WriteReg((InstancePtr)->Config.BaseAddr, \
+ XSCUWDT_CONTROL_OFFSET, (ControlReg))
+
+/****************************************************************************/
+/**
+*
+* Enable auto-reload mode.
+*
+* @param InstancePtr is a pointer to the XScuWdt instance.
+*
+* @return None.
+*
+* @note C-style signature:
+* void XScuWdt_EnableAutoReload(XScuWdt *InstancePtr)
+*
+******************************************************************************/
+#define XScuWdt_EnableAutoReload(InstancePtr) \
+ XScuWdt_SetControlReg((InstancePtr), \
+ (XScuWdt_GetControlReg(InstancePtr) | \
+ XSCUWDT_CONTROL_AUTO_RELOAD_MASK))
+
+/************************** Function Prototypes ******************************/
+
+/*
+ * Lookup configuration in xscuwdt_sinit.c.
+ */
+XScuWdt_Config *XScuWdt_LookupConfig(u16 DeviceId);
+
+/*
+ * Selftest function in xscuwdt_selftest.c
+ */
+s32 XScuWdt_SelfTest(XScuWdt *InstancePtr);
+
+/*
+ * Interface functions in xscuwdt.c
+ */
+s32 XScuWdt_CfgInitialize(XScuWdt *InstancePtr,
+ XScuWdt_Config *ConfigPtr, u32 EffectiveAddress);
+
+void XScuWdt_Start(XScuWdt *InstancePtr);
+
+void XScuWdt_Stop(XScuWdt *InstancePtr);
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* end of protection macro */
+/** @} */
diff --git a/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/include/xscuwdt_hw.h b/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/include/xscuwdt_hw.h
new file mode 100644
index 0000000..efe0a3a
--- /dev/null
+++ b/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/include/xscuwdt_hw.h
@@ -0,0 +1,176 @@
+/******************************************************************************
+*
+* Copyright (C) 2010 - 2015 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+* THE SOFTWARE.
+*
+*
+*
+******************************************************************************/
+/****************************************************************************/
+/**
+*
+* @file xscuwdt_hw.h
+* @addtogroup scuwdt_v2_1
+* @{
+*
+* This file contains the hardware interface to the Xilinx SCU private Watch Dog
+* Timer (XSCUWDT).
+*
+* <pre>
+* MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ----- --- -------- ---------------------------------------------
+* 1.00a sdm 01/15/10 First release
+* 1.01a bss 02/27/12 Updated the register offsets to start at 0x0 instead
+* of 0x20 as the base address obtained from the tools
+* starts at 0x20.
+* 1.02a sg 07/17/12 Included xil_assert.h for CR 667947. This is an issue
+* when the xstatus.h in the common driver overwrites
+* the xstatus.h of the standalone BSP during the
+* libgen.
+* 2.1 sk 02/26/15 Modified the code for MISRA-C:2012 compliance.
+* </pre>
+*
+******************************************************************************/
+#ifndef XSCUWDT_HW_H /* prevent circular inclusions */
+#define XSCUWDT_HW_H /* by using protection macros */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/***************************** Include Files *********************************/
+
+#include "xil_types.h"
+#include "xil_io.h"
+#include "xil_assert.h"
+/************************** Constant Definitions *****************************/
+
+/** @name Register Map
+ * Offsets of registers from the start of the device. The WDT registers start at
+ * an offset 0x20
+ * @{
+ */
+
+#define XSCUWDT_LOAD_OFFSET 0x00U /**< Watchdog Load Register */
+#define XSCUWDT_COUNTER_OFFSET 0x04U /**< Watchdog Counter Register */
+#define XSCUWDT_CONTROL_OFFSET 0x08U /**< Watchdog Control Register */
+#define XSCUWDT_ISR_OFFSET 0x0CU /**< Watchdog Interrupt Status Register */
+#define XSCUWDT_RST_STS_OFFSET 0x10U /**< Watchdog Reset Status Register */
+#define XSCUWDT_DISABLE_OFFSET 0x14U /**< Watchdog Disable Register */
+/* @} */
+
+/** @name Watchdog Control register
+ * This register bits control the prescaler, WD/Timer mode, Intr enable,
+ * auto-reload, watchdog enable.
+ * @{
+ */
+
+#define XSCUWDT_CONTROL_PRESCALER_MASK 0x0000FF00U /**< Prescaler */
+#define XSCUWDT_CONTROL_PRESCALER_SHIFT 8U
+#define XSCUWDT_CONTROL_WD_MODE_MASK 0x00000008U /**< Watchdog/Timer mode */
+#define XSCUWDT_CONTROL_IT_ENABLE_MASK 0x00000004U /**< Intr enable (in
+ timer mode) */
+#define XSCUWDT_CONTROL_AUTO_RELOAD_MASK 0x00000002U /**< Auto-reload (in
+ timer mode) */
+#define XSCUWDT_CONTROL_WD_ENABLE_MASK 0x00000001U /**< Watchdog enable */
+/* @} */
+
+/** @name Interrupt Status register
+ * This register indicates the Counter register has reached zero in Counter
+ * mode.
+ * @{
+ */
+
+#define XSCUWDT_ISR_EVENT_FLAG_MASK 0x00000001U /**< Event flag */
+/*@}*/
+
+/** @name Reset Status register
+ * This register indicates the Counter register has reached zero in Watchdog
+ * mode and a reset request is sent.
+ * @{
+ */
+
+#define XSCUWDT_RST_STS_RESET_FLAG_MASK 0x00000001U /**< Time out occurred */
+/*@}*/
+
+/** @name Disable register
+ * This register is used to switch from watchdog mode to timer mode.
+ * The software must write 0x12345678 and 0x87654321 successively to the
+ * Watchdog Disable Register so that the watchdog mode bit in the Watchdog
+ * Control Register is set to zero.
+ * @{
+ */
+#define XSCUWDT_DISABLE_VALUE1 0x12345678U /**< Watchdog mode disable
+ value 1 */
+#define XSCUWDT_DISABLE_VALUE2 0x87654321U /**< Watchdog mode disable
+ value 2 */
+/*@}*/
+
+/**************************** Type Definitions *******************************/
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/****************************************************************************/
+/**
+*
+* Read the given register.
+*
+* @param BaseAddr is the base address of the device
+* @param RegOffset is the register offset to be read
+*
+* @return The 32-bit value of the register
+*
+* @note C-style signature:
+* u32 XScuWdt_ReadReg(u32 BaseAddr, u32 RegOffset)
+*
+*****************************************************************************/
+#define XScuWdt_ReadReg(BaseAddr, RegOffset) \
+ Xil_In32((BaseAddr) + ((u32)RegOffset))
+
+/****************************************************************************/
+/**
+*
+* Write the given register.
+*
+* @param BaseAddr is the base address of the device
+* @param RegOffset is the register offset to be written
+* @param Data is the 32-bit value to write to the register
+*
+* @return None.
+*
+* @note C-style signature:
+* void XScuWdt_WriteReg(u32 BaseAddr, u32 RegOffset, u32 Data)
+*
+*****************************************************************************/
+#define XScuWdt_WriteReg(BaseAddr, RegOffset, Data) \
+ Xil_Out32((BaseAddr) + ((u32)RegOffset), ((u32)Data))
+
+/************************** Function Prototypes ******************************/
+
+/************************** Variable Definitions *****************************/
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* end of protection macro */
+/** @} */
diff --git a/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/include/xsdps.h b/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/include/xsdps.h
new file mode 100644
index 0000000..24cc271
--- /dev/null
+++ b/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/include/xsdps.h
@@ -0,0 +1,282 @@
+/******************************************************************************
+*
+* Copyright (C) 2013 - 2019 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+* THE SOFTWARE.
+*
+*
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xsdps.h
+* @addtogroup sdps_v3_8
+* @{
+* @details
+*
+* This file contains the implementation of XSdPs driver.
+* This driver is used initialize read from and write to the SD card.
+* Features such as switching bus width to 4-bit and switching to high speed,
+* changing clock frequency, block size etc. are supported.
+* SD 2.0 uses 1/4 bus width and speeds of 25/50KHz. Initialization, however
+* is done using 1-bit bus width and 400KHz clock frequency.
+* SD commands are classified as broadcast and addressed. Commands can be
+* those with response only (using only command line) or
+* response + data (using command and data lines).
+* Only one command can be sent at a time. During a data transfer however,
+* when dsta lines are in use, certain commands (which use only the command
+* line) can be sent, most often to obtain status.
+* This driver does not support multi card slots at present.
+*
+* Initialization:
+* This includes initialization on the host controller side to select
+* clock frequency, bus power and default transfer related parameters.
+* The default voltage is 3.3V.
+* On the SD card side, the initialization and identification state diagram is
+* implemented. This resets the card, gives it a unique address/ID and
+* identifies key card related specifications.
+*
+* Data transfer:
+* The SD card is put in transfer state to read from or write to it.
+* The default block size is 512 bytes and if supported,
+* default bus width is 4-bit and bus speed is High speed.
+* The read and write functions are implemented in polled mode using ADMA2.
+*
+* At any point, when key parameters such as block size or
+* clock/speed or bus width are modified, this driver takes care of
+* maintaining the same selection on host and card.
+* All error bits in host controller are monitored by the driver and in the
+* event one of them is set, driver will clear the interrupt status and
+* communicate failure to the upper layer.
+*
+* File system use:
+* This driver can be used with xilffs library to read and write files to SD.
+* (Please refer to procedure in diskio.c). The file system read/write example
+* in polled mode can used for reference.
+*
+* There is no example for using SD driver without file system at present.
+* However, the driver can be used without the file system. The glue layer
+* in filesystem can be used as reference for the same. The block count
+* passed to the read/write function in one call is limited by the ADMA2
+* descriptor table and hence care will have to be taken to call read/write
+* API's in a loop for large file sizes.
+*
+* Interrupt mode is not supported because it offers no improvement when used
+* with file system.
+*
+* eMMC support:
+* SD driver supports SD and eMMC based on the "enable MMC" parameter in SDK.
+* The features of eMMC supported by the driver will depend on those supported
+* by the host controller. The current driver supports read/write on eMMC card
+* using 4-bit and high speed mode currently.
+*
+* Features not supported include - card write protect, password setting,
+* lock/unlock, interrupts, SDMA mode, programmed I/O mode and
+* 64-bit addressed ADMA2, erase/pre-erase commands.
+*
+* <pre>
+* MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ----- --- -------- -----------------------------------------------
+* 1.00a hk/sg 10/17/13 Initial release
+* 2.0 hk 03/07/14 Version number revised.
+* 2.1 hk 04/18/14 Increase sleep for eMMC switch command.
+* Add sleep for microblaze designs. CR# 781117.
+* 2.2 hk 07/28/14 Make changes to enable use of data cache.
+* 2.3 sk 09/23/14 Send command for relative card address
+* when re-initialization is done.CR# 819614.
+* Use XSdPs_Change_ClkFreq API whenever changing
+* clock.CR# 816586.
+* 2.4 sk 12/04/14 Added support for micro SD without
+* WP/CD. CR# 810655.
+* Checked for DAT Inhibit mask instead of CMD
+* Inhibit mask in Cmd Transfer API.
+* Added Support for SD Card v1.0
+* 2.5 sg 07/09/15 Added SD 3.0 features
+* kvn 07/15/15 Modified the code according to MISRAC-2012.
+* 2.6 sk 10/12/15 Added support for SD card v1.0 CR# 840601.
+* 2.7 sk 11/24/15 Considered the slot type befoe checking CD/WP pins.
+* sk 12/10/15 Added support for MMC cards.
+* 01/08/16 Added workaround for issue in auto tuning mode
+* of SDR50, SDR104 and HS200.
+* sk 02/16/16 Corrected the Tuning logic.
+* sk 03/01/16 Removed Bus Width check for eMMC. CR# 938311.
+* 2.8 sk 04/20/16 Added new workaround for auto tuning.
+* 05/03/16 Standard Speed for SD to 19MHz in ZynqMPSoC. CR#951024
+* 3.0 sk 06/09/16 Added support for mkfs to calculate sector count.
+* sk 07/16/16 Added support for UHS modes.
+* sk 07/07/16 Used usleep API for both arm and microblaze.
+* sk 07/16/16 Added Tap delays accordingly to different SD/eMMC
+* operating modes.
+* sk 08/13/16 Removed sleep.h from xsdps.h as a temporary fix for
+* CR#956899.
+* 3.1 mi 09/07/16 Removed compilation warnings with extra compiler flags.
+* sk 10/13/16 Reduced the delay during power cycle to 1ms as per spec
+* sk 10/19/16 Used emmc_hwreset pin to reset eMMC.
+* sk 11/07/16 Enable Rst_n bit in ext_csd reg if not enabled.
+* sk 11/16/16 Issue DLL reset at 31 iteration to load new zero value.
+* 3.2 sk 11/30/16 Modified the voltage switching sequence as per spec.
+* sk 02/01/17 Added HSD and DDR mode support for eMMC.
+* sk 02/01/17 Consider bus width parameter from design for switching
+* vns 02/09/17 Added ARMA53_32 support for ZynqMP CR#968397
+* sk 03/20/17 Add support for EL1 non-secure mode.
+* 3.3 mn 05/17/17 Add support for 64bit DMA addressing
+* mn 08/07/17 Modify driver to support 64-bit DMA in arm64 only
+* mn 08/17/17 Enabled CCI support for A53 by adding cache coherency
+* information.
+* mn 09/06/17 Resolved compilation errors with IAR toolchain
+* 3.6 mn 08/01/18 Add support for using 64Bit DMA with 32-Bit Processor
+* 3.7 mn 02/01/19 Add support for idling of SDIO
+* 3.8 mn 04/12/19 Modified TapDelay code for supporting ZynqMP and Versal
+* mn 09/17/19 Modified ADMA handling API for 32bit and 64bit addresses
+*
+* </pre>
+*
+******************************************************************************/
+
+
+#ifndef SDPS_H_
+#define SDPS_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include "xil_printf.h"
+#include "xil_cache.h"
+#include "xstatus.h"
+#include "xsdps_hw.h"
+#include "xplatform_info.h"
+#include <string.h>
+
+/************************** Constant Definitions *****************************/
+
+#define XSDPS_CT_ERROR 0x2L /**< Command timeout flag */
+#define MAX_TUNING_COUNT 40U /**< Maximum Tuning count */
+#define MAX_TIMEOUT 0x1FFFFFFFU /**< Maximum Timeout */
+
+/**************************** Type Definitions *******************************/
+
+typedef void (*XSdPs_ConfigTap) (u32 Bank, u32 DeviceId, u32 CardType);
+
+/**
+ * This typedef contains configuration information for the device.
+ */
+typedef struct {
+ u16 DeviceId; /**< Unique ID of device */
+ u32 BaseAddress; /**< Base address of the device */
+ u32 InputClockHz; /**< Input clock frequency */
+ u32 CardDetect; /**< Card Detect */
+ u32 WriteProtect; /**< Write Protect */
+ u32 BusWidth; /**< Bus Width */
+ u32 BankNumber; /**< MIO Bank selection for SD */
+ u32 HasEMIO; /**< If SD is connected to EMIO */
+ u8 IsCacheCoherent; /**< If SD is Cache Coherent or not */
+} XSdPs_Config;
+
+/* ADMA2 32-Bit descriptor table */
+typedef struct {
+ u16 Attribute; /**< Attributes of descriptor */
+ u16 Length; /**< Length of current dma transfer */
+ u32 Address; /**< Address of current dma transfer */
+#ifdef __ICCARM__
+#pragma data_alignment = 32
+} XSdPs_Adma2Descriptor32;
+#else
+} __attribute__((__packed__))XSdPs_Adma2Descriptor32;
+#endif
+
+/* ADMA2 64-Bit descriptor table */
+typedef struct {
+ u16 Attribute; /**< Attributes of descriptor */
+ u16 Length; /**< Length of current dma transfer */
+ u64 Address; /**< Address of current dma transfer */
+#ifdef __ICCARM__
+#pragma data_alignment = 32
+} XSdPs_Adma2Descriptor64;
+#else
+} __attribute__((__packed__))XSdPs_Adma2Descriptor64;
+#endif
+
+/**
+ * The XSdPs driver instance data. The user is required to allocate a
+ * variable of this type for every SD device in the system. A pointer
+ * to a variable of this type is then passed to the driver API functions.
+ */
+typedef struct {
+ XSdPs_Config Config; /**< Configuration structure */
+ u32 IsReady; /**< Device is initialized and ready */
+ u32 Host_Caps; /**< Capabilities of host controller */
+ u32 Host_CapsExt; /**< Extended Capabilities */
+ u32 HCS; /**< High capacity support in card */
+ u8 CardType; /**< Type of card - SD/MMC/eMMC */
+ u8 Card_Version; /**< Card version */
+ u8 HC_Version; /**< Host controller version */
+ u8 BusWidth; /**< Current operating bus width */
+ u32 BusSpeed; /**< Current operating bus speed */
+ u8 Switch1v8; /**< 1.8V Switch support */
+ u32 CardID[4]; /**< Card ID Register */
+ u32 RelCardAddr; /**< Relative Card Address */
+ u32 CardSpecData[4]; /**< Card Specific Data Register */
+ u32 SectorCount; /**< Sector Count */
+ u32 SdCardConfig; /**< Sd Card Configuration Register */
+ u32 Mode; /**< Bus Speed Mode */
+ u32 OTapDelay; /**< Output Tap Delay */
+ u32 ITapDelay; /**< Input Tap Delay */
+ u64 Dma64BitAddr; /**< 64 Bit DMA Address */
+} XSdPs;
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/************************** Function Prototypes ******************************/
+XSdPs_Config *XSdPs_LookupConfig(u16 DeviceId);
+s32 XSdPs_CfgInitialize(XSdPs *InstancePtr, XSdPs_Config *ConfigPtr,
+ u32 EffectiveAddr);
+s32 XSdPs_SdCardInitialize(XSdPs *InstancePtr);
+s32 XSdPs_ReadPolled(XSdPs *InstancePtr, u32 Arg, u32 BlkCnt, u8 *Buff);
+s32 XSdPs_WritePolled(XSdPs *InstancePtr, u32 Arg, u32 BlkCnt, const u8 *Buff);
+s32 XSdPs_SetBlkSize(XSdPs *InstancePtr, u16 BlkSize);
+s32 XSdPs_Select_Card (XSdPs *InstancePtr);
+s32 XSdPs_Change_ClkFreq(XSdPs *InstancePtr, u32 SelFreq);
+s32 XSdPs_Change_BusWidth(XSdPs *InstancePtr);
+s32 XSdPs_Change_BusSpeed(XSdPs *InstancePtr);
+s32 XSdPs_Get_BusWidth(XSdPs *InstancePtr, u8 *ReadBuff);
+s32 XSdPs_Get_BusSpeed(XSdPs *InstancePtr, u8 *ReadBuff);
+s32 XSdPs_Get_Status(XSdPs *InstancePtr, u8 *SdStatReg);
+s32 XSdPs_Pullup(XSdPs *InstancePtr);
+s32 XSdPs_MmcCardInitialize(XSdPs *InstancePtr);
+s32 XSdPs_CardInitialize(XSdPs *InstancePtr);
+s32 XSdPs_Get_Mmc_ExtCsd(XSdPs *InstancePtr, u8 *ReadBuff);
+s32 XSdPs_Set_Mmc_ExtCsd(XSdPs *InstancePtr, u32 Arg);
+void XSdPs_Idle(XSdPs *InstancePtr);
+#if defined (ARMR5) || defined (__aarch64__) || defined (ARMA53_32) || defined (__MICROBLAZE__)
+void XSdPs_Identify_UhsMode(XSdPs *InstancePtr, u8 *ReadBuff);
+void XSdPs_ddr50_tapdelay(u32 Bank, u32 DeviceId, u32 CardType);
+void XSdPs_hsd_sdr25_tapdelay(u32 Bank, u32 DeviceId, u32 CardType);
+void XSdPs_sdr104_hs200_tapdelay(u32 Bank, u32 DeviceId, u32 CardType);
+#endif
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* SD_H_ */
+/** @} */
diff --git a/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/include/xsdps_hw.h b/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/include/xsdps_hw.h
new file mode 100644
index 0000000..8097d04
--- /dev/null
+++ b/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/include/xsdps_hw.h
@@ -0,0 +1,1317 @@
+/******************************************************************************
+*
+* Copyright (C) 2013 - 2019 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+* THE SOFTWARE.
+*
+*
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xsdps_hw.h
+* @addtogroup sdps_v3_8
+* @{
+*
+* This header file contains the identifiers and basic HW access driver
+* functions (or macros) that can be used to access the device. Other driver
+* functions are defined in xsdps.h.
+*
+* <pre>
+* MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ----- --- -------- -----------------------------------------------
+* 1.00a hk/sg 10/17/13 Initial release
+* 2.5 sg 07/09/15 Added SD 3.0 features
+* kvn 07/15/15 Modified the code according to MISRAC-2012.
+* 2.7 sk 12/10/15 Added support for MMC cards.
+* sk 03/02/16 Configured the Tap Delay values for eMMC HS200 mode.
+* 2.8 sk 04/20/16 Added new workaround for auto tuning.
+* 3.0 sk 06/09/16 Added support for mkfs to calculate sector count.
+* sk 07/16/16 Added support for UHS modes.
+* sk 07/16/16 Added Tap delays accordingly to different SD/eMMC
+* operating modes.
+* 3.1 sk 11/07/16 Enable Rst_n bit in ext_csd reg if not enabled.
+* 3.2 sk 03/20/17 Add support for EL1 non-secure mode.
+* 3.3 mn 08/22/17 Updated for Word Access System support
+* mn 09/06/17 Added support for ARMCC toolchain
+* 3.4 mn 01/22/18 Separated out SDR104 and HS200 clock defines
+* 3.6 mn 07/06/18 Fix Doxygen warnings for sdps driver
+* 3.8 mn 04/12/19 Modified TapDelay code for supporting ZynqMP and Versal
+* mn 05/21/19 Set correct tap delays for Versal
+* mn 05/21/19 Disable DLL Reset code for Versal
+* mn 05/21/19 Enable SD UHS Mode support by default for Versal
+* mn 07/03/19 Update Input Tap Delays for Versal
+*
+* </pre>
+*
+******************************************************************************/
+
+#ifndef SD_HW_H_
+#define SD_HW_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/***************************** Include Files *********************************/
+
+#include "xil_types.h"
+#include "xil_assert.h"
+#include "xil_io.h"
+#include "xparameters.h"
+
+/************************** Constant Definitions *****************************/
+
+/* Enable UHS Mode support by default for Versal */
+#ifdef versal
+#define UHS_MODE_ENABLE
+#endif
+/** @name Register Map
+ *
+ * Register offsets from the base address of an SD device.
+ * @{
+ */
+
+#define XSDPS_SDMA_SYS_ADDR_OFFSET 0x00U /**< SDMA System Address
+ Register */
+#define XSDPS_SDMA_SYS_ADDR_LO_OFFSET XSDPS_SDMA_SYS_ADDR_OFFSET
+ /**< SDMA System Address
+ Low Register */
+#define XSDPS_ARGMT2_LO_OFFSET 0x00U /**< Argument2 Low Register */
+#define XSDPS_SDMA_SYS_ADDR_HI_OFFSET 0x02U /**< SDMA System Address
+ High Register */
+#define XSDPS_ARGMT2_HI_OFFSET 0x02U /**< Argument2 High Register */
+
+#define XSDPS_BLK_SIZE_OFFSET 0x04U /**< Block Size Register */
+#define XSDPS_BLK_CNT_OFFSET 0x06U /**< Block Count Register */
+#define XSDPS_ARGMT_OFFSET 0x08U /**< Argument Register */
+#define XSDPS_ARGMT1_LO_OFFSET XSDPS_ARGMT_OFFSET
+ /**< Argument1 Register */
+#define XSDPS_ARGMT1_HI_OFFSET 0x0AU /**< Argument1 Register */
+
+#define XSDPS_XFER_MODE_OFFSET 0x0CU /**< Transfer Mode Register */
+#define XSDPS_CMD_OFFSET 0x0EU /**< Command Register */
+#define XSDPS_RESP0_OFFSET 0x10U /**< Response0 Register */
+#define XSDPS_RESP1_OFFSET 0x14U /**< Response1 Register */
+#define XSDPS_RESP2_OFFSET 0x18U /**< Response2 Register */
+#define XSDPS_RESP3_OFFSET 0x1CU /**< Response3 Register */
+#define XSDPS_BUF_DAT_PORT_OFFSET 0x20U /**< Buffer Data Port */
+#define XSDPS_PRES_STATE_OFFSET 0x24U /**< Present State */
+#define XSDPS_HOST_CTRL1_OFFSET 0x28U /**< Host Control 1 */
+#define XSDPS_POWER_CTRL_OFFSET 0x29U /**< Power Control */
+#define XSDPS_BLK_GAP_CTRL_OFFSET 0x2AU /**< Block Gap Control */
+#define XSDPS_WAKE_UP_CTRL_OFFSET 0x2BU /**< Wake Up Control */
+#define XSDPS_CLK_CTRL_OFFSET 0x2CU /**< Clock Control */
+#define XSDPS_TIMEOUT_CTRL_OFFSET 0x2EU /**< Timeout Control */
+#define XSDPS_SW_RST_OFFSET 0x2FU /**< Software Reset */
+#define XSDPS_NORM_INTR_STS_OFFSET 0x30U /**< Normal Interrupt
+ Status Register */
+#define XSDPS_ERR_INTR_STS_OFFSET 0x32U /**< Error Interrupt
+ Status Register */
+#define XSDPS_NORM_INTR_STS_EN_OFFSET 0x34U /**< Normal Interrupt
+ Status Enable Register */
+#define XSDPS_ERR_INTR_STS_EN_OFFSET 0x36U /**< Error Interrupt
+ Status Enable Register */
+#define XSDPS_NORM_INTR_SIG_EN_OFFSET 0x38U /**< Normal Interrupt
+ Signal Enable Register */
+#define XSDPS_ERR_INTR_SIG_EN_OFFSET 0x3AU /**< Error Interrupt
+ Signal Enable Register */
+
+#define XSDPS_AUTO_CMD12_ERR_STS_OFFSET 0x3CU /**< Auto CMD12 Error Status
+ Register */
+#define XSDPS_HOST_CTRL2_OFFSET 0x3EU /**< Host Control2 Register */
+#define XSDPS_CAPS_OFFSET 0x40U /**< Capabilities Register */
+#define XSDPS_CAPS_EXT_OFFSET 0x44U /**< Capabilities Extended */
+#define XSDPS_MAX_CURR_CAPS_OFFSET 0x48U /**< Maximum Current
+ Capabilities Register */
+#define XSDPS_MAX_CURR_CAPS_EXT_OFFSET 0x4CU /**< Maximum Current
+ Capabilities Ext Register */
+#define XSDPS_FE_ERR_INT_STS_OFFSET 0x52U /**< Force Event for
+ Error Interrupt Status */
+#define XSDPS_FE_AUTO_CMD12_EIS_OFFSET 0x50U /**< Auto CM12 Error Interrupt
+ Status Register */
+#define XSDPS_ADMA_ERR_STS_OFFSET 0x54U /**< ADMA Error Status
+ Register */
+#define XSDPS_ADMA_SAR_OFFSET 0x58U /**< ADMA System Address
+ Register */
+#define XSDPS_ADMA_SAR_EXT_OFFSET 0x5CU /**< ADMA System Address
+ Extended Register */
+#define XSDPS_PRE_VAL_1_OFFSET 0x60U /**< Preset Value Register */
+#define XSDPS_PRE_VAL_2_OFFSET 0x64U /**< Preset Value Register */
+#define XSDPS_PRE_VAL_3_OFFSET 0x68U /**< Preset Value Register */
+#define XSDPS_PRE_VAL_4_OFFSET 0x6CU /**< Preset Value Register */
+#define XSDPS_BOOT_TOUT_CTRL_OFFSET 0x70U /**< Boot timeout control
+ register */
+
+#define XSDPS_SHARED_BUS_CTRL_OFFSET 0xE0U /**< Shared Bus Control
+ Register */
+#define XSDPS_SLOT_INTR_STS_OFFSET 0xFCU /**< Slot Interrupt Status
+ Register */
+#define XSDPS_HOST_CTRL_VER_OFFSET 0xFEU /**< Host Controller Version
+ Register */
+
+/* @} */
+
+/** @name Control Register - Host control, Power control,
+ * Block Gap control and Wakeup control
+ *
+ * This register contains bits for various configuration options of
+ * the SD host controller. Read/Write apart from the reserved bits.
+ * @{
+ */
+
+#define XSDPS_HC_LED_MASK 0x00000001U /**< LED Control */
+#define XSDPS_HC_WIDTH_MASK 0x00000002U /**< Bus width */
+#define XSDPS_HC_BUS_WIDTH_4 0x00000002U
+#define XSDPS_HC_SPEED_MASK 0x00000004U /**< High Speed */
+#define XSDPS_HC_DMA_MASK 0x00000018U /**< DMA Mode Select */
+#define XSDPS_HC_DMA_SDMA_MASK 0x00000000U /**< SDMA Mode */
+#define XSDPS_HC_DMA_ADMA1_MASK 0x00000008U /**< ADMA1 Mode */
+#define XSDPS_HC_DMA_ADMA2_32_MASK 0x00000010U /**< ADMA2 Mode - 32 bit */
+#define XSDPS_HC_DMA_ADMA2_64_MASK 0x00000018U /**< ADMA2 Mode - 64 bit */
+#define XSDPS_HC_EXT_BUS_WIDTH 0x00000020U /**< Bus width - 8 bit */
+#define XSDPS_HC_CARD_DET_TL_MASK 0x00000040U /**< Card Detect Tst Lvl */
+#define XSDPS_HC_CARD_DET_SD_MASK 0x00000080U /**< Card Detect Sig Det */
+
+#define XSDPS_PC_BUS_PWR_MASK 0x00000001U /**< Bus Power Control */
+#define XSDPS_PC_BUS_VSEL_MASK 0x0000000EU /**< Bus Voltage Select */
+#define XSDPS_PC_BUS_VSEL_3V3_MASK 0x0000000EU /**< Bus Voltage 3.3V */
+#define XSDPS_PC_BUS_VSEL_3V0_MASK 0x0000000CU /**< Bus Voltage 3.0V */
+#define XSDPS_PC_BUS_VSEL_1V8_MASK 0x0000000AU /**< Bus Voltage 1.8V */
+#define XSDPS_PC_EMMC_HW_RST_MASK 0x00000010U /**< HW reset for eMMC */
+
+#define XSDPS_BGC_STP_REQ_MASK 0x00000001U /**< Block Gap Stop Req */
+#define XSDPS_BGC_CNT_REQ_MASK 0x00000002U /**< Block Gap Cont Req */
+#define XSDPS_BGC_RWC_MASK 0x00000004U /**< Block Gap Rd Wait */
+#define XSDPS_BGC_INTR_MASK 0x00000008U /**< Block Gap Intr */
+#define XSDPS_BGC_SPI_MODE_MASK 0x00000010U /**< Block Gap SPI Mode */
+#define XSDPS_BGC_BOOT_EN_MASK 0x00000020U /**< Block Gap Boot Enb */
+#define XSDPS_BGC_ALT_BOOT_EN_MASK 0x00000040U /**< Block Gap Alt BootEn */
+#define XSDPS_BGC_BOOT_ACK_MASK 0x00000080U /**< Block Gap Boot Ack */
+
+#define XSDPS_WC_WUP_ON_INTR_MASK 0x00000001U /**< Wakeup Card Intr */
+#define XSDPS_WC_WUP_ON_INSRT_MASK 0x00000002U /**< Wakeup Card Insert */
+#define XSDPS_WC_WUP_ON_REM_MASK 0x00000004U /**< Wakeup Card Removal */
+
+/* @} */
+
+/** @name Control Register - Clock control, Timeout control & Software reset
+ *
+ * This register contains bits for configuration options of clock, timeout and
+ * software reset.
+ * Read/Write except for Inter_Clock_Stable bit (read only) and reserved bits.
+ * @{
+ */
+
+#define XSDPS_CC_INT_CLK_EN_MASK 0x00000001U
+#define XSDPS_CC_INT_CLK_STABLE_MASK 0x00000002U
+#define XSDPS_CC_SD_CLK_EN_MASK 0x00000004U
+#define XSDPS_CC_SD_CLK_GEN_SEL_MASK 0x00000020U
+#define XSDPS_CC_SDCLK_FREQ_SEL_EXT_MASK 0x000000C0U
+#define XSDPS_CC_SDCLK_FREQ_SEL_MASK 0x0000FF00U
+#define XSDPS_CC_SDCLK_FREQ_D256_MASK 0x00008000U
+#define XSDPS_CC_SDCLK_FREQ_D128_MASK 0x00004000U
+#define XSDPS_CC_SDCLK_FREQ_D64_MASK 0x00002000U
+#define XSDPS_CC_SDCLK_FREQ_D32_MASK 0x00001000U
+#define XSDPS_CC_SDCLK_FREQ_D16_MASK 0x00000800U
+#define XSDPS_CC_SDCLK_FREQ_D8_MASK 0x00000400U
+#define XSDPS_CC_SDCLK_FREQ_D4_MASK 0x00000200U
+#define XSDPS_CC_SDCLK_FREQ_D2_MASK 0x00000100U
+#define XSDPS_CC_SDCLK_FREQ_BASE_MASK 0x00000000U
+#define XSDPS_CC_MAX_DIV_CNT 256U
+#define XSDPS_CC_EXT_MAX_DIV_CNT 2046U
+#define XSDPS_CC_EXT_DIV_SHIFT 6U
+
+#define XSDPS_TC_CNTR_VAL_MASK 0x0000000FU
+
+#define XSDPS_SWRST_ALL_MASK 0x00000001U
+#define XSDPS_SWRST_CMD_LINE_MASK 0x00000002U
+#define XSDPS_SWRST_DAT_LINE_MASK 0x00000004U
+
+#define XSDPS_CC_MAX_NUM_OF_DIV 9U
+#define XSDPS_CC_DIV_SHIFT 8U
+
+/* @} */
+
+/** @name SD Interrupt Registers
+ *
+ * <b> Normal and Error Interrupt Status Register </b>
+ * This register shows the normal and error interrupt status.
+ * Status enable register affects reads of this register.
+ * If Signal enable register is set and the corresponding status bit is set,
+ * interrupt is generated.
+ * Write to clear except
+ * Error_interrupt and Card_Interrupt bits - Read only
+ *
+ * <b> Normal and Error Interrupt Status Enable Register </b>
+ * Setting this register bits enables Interrupt status.
+ * Read/Write except Fixed_to_0 bit (Read only)
+ *
+ * <b> Normal and Error Interrupt Signal Enable Register </b>
+ * This register is used to select which interrupt status is
+ * indicated to the Host System as the interrupt.
+ * Read/Write except Fixed_to_0 bit (Read only)
+ *
+ * All three registers have same bit definitions
+ * @{
+ */
+
+#define XSDPS_INTR_CC_MASK 0x00000001U /**< Command Complete */
+#define XSDPS_INTR_TC_MASK 0x00000002U /**< Transfer Complete */
+#define XSDPS_INTR_BGE_MASK 0x00000004U /**< Block Gap Event */
+#define XSDPS_INTR_DMA_MASK 0x00000008U /**< DMA Interrupt */
+#define XSDPS_INTR_BWR_MASK 0x00000010U /**< Buffer Write Ready */
+#define XSDPS_INTR_BRR_MASK 0x00000020U /**< Buffer Read Ready */
+#define XSDPS_INTR_CARD_INSRT_MASK 0x00000040U /**< Card Insert */
+#define XSDPS_INTR_CARD_REM_MASK 0x00000080U /**< Card Remove */
+#define XSDPS_INTR_CARD_MASK 0x00000100U /**< Card Interrupt */
+#define XSDPS_INTR_INT_A_MASK 0x00000200U /**< INT A Interrupt */
+#define XSDPS_INTR_INT_B_MASK 0x00000400U /**< INT B Interrupt */
+#define XSDPS_INTR_INT_C_MASK 0x00000800U /**< INT C Interrupt */
+#define XSDPS_INTR_RE_TUNING_MASK 0x00001000U /**< Re-Tuning Interrupt */
+#define XSDPS_INTR_BOOT_ACK_RECV_MASK 0x00002000U /**< Boot Ack Recv
+ Interrupt */
+#define XSDPS_INTR_BOOT_TERM_MASK 0x00004000U /**< Boot Terminate
+ Interrupt */
+#define XSDPS_INTR_ERR_MASK 0x00008000U /**< Error Interrupt */
+#define XSDPS_NORM_INTR_ALL_MASK 0x0000FFFFU
+
+#define XSDPS_INTR_ERR_CT_MASK 0x00000001U /**< Command Timeout
+ Error */
+#define XSDPS_INTR_ERR_CCRC_MASK 0x00000002U /**< Command CRC Error */
+#define XSDPS_INTR_ERR_CEB_MASK 0x00000004U /**< Command End Bit
+ Error */
+#define XSDPS_INTR_ERR_CI_MASK 0x00000008U /**< Command Index Error */
+#define XSDPS_INTR_ERR_DT_MASK 0x00000010U /**< Data Timeout Error */
+#define XSDPS_INTR_ERR_DCRC_MASK 0x00000020U /**< Data CRC Error */
+#define XSDPS_INTR_ERR_DEB_MASK 0x00000040U /**< Data End Bit Error */
+#define XSDPS_INTR_ERR_CUR_LMT_MASK 0x00000080U /**< Current Limit Error */
+#define XSDPS_INTR_ERR_AUTO_CMD12_MASK 0x00000100U /**< Auto CMD12 Error */
+#define XSDPS_INTR_ERR_ADMA_MASK 0x00000200U /**< ADMA Error */
+#define XSDPS_INTR_ERR_TR_MASK 0x00001000U /**< Tuning Error */
+#define XSDPS_INTR_VEND_SPF_ERR_MASK 0x0000E000U /**< Vendor Specific
+ Error */
+#define XSDPS_ERROR_INTR_ALL_MASK 0x0000F3FFU /**< Mask for error bits */
+/* @} */
+
+/** @name Block Size and Block Count Register
+ *
+ * This register contains the block count for current transfer,
+ * block size and SDMA buffer size.
+ * Read/Write except for reserved bits.
+ * @{
+ */
+
+#define XSDPS_BLK_SIZE_MASK 0x00000FFFU /**< Transfer Block Size */
+#define XSDPS_SDMA_BUFF_SIZE_MASK 0x00007000U /**< Host SDMA Buffer Size */
+#define XSDPS_BLK_SIZE_1024 0x400U
+#define XSDPS_BLK_SIZE_2048 0x800U
+#define XSDPS_BLK_CNT_MASK 0x0000FFFFU /**< Block Count for
+ Current Transfer */
+
+/* @} */
+
+/** @name Transfer Mode and Command Register
+ *
+ * The Transfer Mode register is used to control the data transfers and
+ * Command register is used for command generation
+ * Read/Write except for reserved bits.
+ * @{
+ */
+
+#define XSDPS_TM_DMA_EN_MASK 0x00000001U /**< DMA Enable */
+#define XSDPS_TM_BLK_CNT_EN_MASK 0x00000002U /**< Block Count Enable */
+#define XSDPS_TM_AUTO_CMD12_EN_MASK 0x00000004U /**< Auto CMD12 Enable */
+#define XSDPS_TM_DAT_DIR_SEL_MASK 0x00000010U /**< Data Transfer
+ Direction Select */
+#define XSDPS_TM_MUL_SIN_BLK_SEL_MASK 0x00000020U /**< Multi/Single
+ Block Select */
+
+#define XSDPS_CMD_RESP_SEL_MASK 0x00000003U /**< Response Type
+ Select */
+#define XSDPS_CMD_RESP_NONE_MASK 0x00000000U /**< No Response */
+#define XSDPS_CMD_RESP_L136_MASK 0x00000001U /**< Response length 138 */
+#define XSDPS_CMD_RESP_L48_MASK 0x00000002U /**< Response length 48 */
+#define XSDPS_CMD_RESP_L48_BSY_CHK_MASK 0x00000003U /**< Response length 48 &
+ check busy after
+ response */
+#define XSDPS_CMD_CRC_CHK_EN_MASK 0x00000008U /**< Command CRC Check
+ Enable */
+#define XSDPS_CMD_INX_CHK_EN_MASK 0x00000010U /**< Command Index Check
+ Enable */
+#define XSDPS_DAT_PRESENT_SEL_MASK 0x00000020U /**< Data Present Select */
+#define XSDPS_CMD_TYPE_MASK 0x000000C0U /**< Command Type */
+#define XSDPS_CMD_TYPE_NORM_MASK 0x00000000U /**< CMD Type - Normal */
+#define XSDPS_CMD_TYPE_SUSPEND_MASK 0x00000040U /**< CMD Type - Suspend */
+#define XSDPS_CMD_TYPE_RESUME_MASK 0x00000080U /**< CMD Type - Resume */
+#define XSDPS_CMD_TYPE_ABORT_MASK 0x000000C0U /**< CMD Type - Abort */
+#define XSDPS_CMD_MASK 0x00003F00U /**< Command Index Mask -
+ Set to CMD0-63,
+ AMCD0-63 */
+
+/* @} */
+
+/** @name Auto CMD Error Status Register
+ *
+ * This register is read only register which contains
+ * information about the error status of Auto CMD 12 and 23.
+ * Read Only
+ * @{
+ */
+#define XSDPS_AUTO_CMD12_NT_EX_MASK 0x0001U /**< Auto CMD12 Not
+ executed */
+#define XSDPS_AUTO_CMD_TOUT_MASK 0x0002U /**< Auto CMD Timeout
+ Error */
+#define XSDPS_AUTO_CMD_CRC_MASK 0x0004U /**< Auto CMD CRC Error */
+#define XSDPS_AUTO_CMD_EB_MASK 0x0008U /**< Auto CMD End Bit
+ Error */
+#define XSDPS_AUTO_CMD_IND_MASK 0x0010U /**< Auto CMD Index Error */
+#define XSDPS_AUTO_CMD_CNI_ERR_MASK 0x0080U /**< Command not issued by
+ Auto CMD12 Error */
+/* @} */
+
+/** @name Host Control2 Register
+ *
+ * This register contains extended configuration bits.
+ * Read Write
+ * @{
+ */
+#define XSDPS_HC2_UHS_MODE_MASK 0x0007U /**< UHS Mode select bits */
+#define XSDPS_HC2_UHS_MODE_SDR12_MASK 0x0000U /**< SDR12 UHS Mode */
+#define XSDPS_HC2_UHS_MODE_SDR25_MASK 0x0001U /**< SDR25 UHS Mode */
+#define XSDPS_HC2_UHS_MODE_SDR50_MASK 0x0002U /**< SDR50 UHS Mode */
+#define XSDPS_HC2_UHS_MODE_SDR104_MASK 0x0003U /**< SDR104 UHS Mode */
+#define XSDPS_HC2_UHS_MODE_DDR50_MASK 0x0004U /**< DDR50 UHS Mode */
+#define XSDPS_HC2_1V8_EN_MASK 0x0008U /**< 1.8V Signal Enable */
+#define XSDPS_HC2_DRV_STR_SEL_MASK 0x0030U /**< Driver Strength
+ Selection */
+#define XSDPS_HC2_DRV_STR_B_MASK 0x0000U /**< Driver Strength B */
+#define XSDPS_HC2_DRV_STR_A_MASK 0x0010U /**< Driver Strength A */
+#define XSDPS_HC2_DRV_STR_C_MASK 0x0020U /**< Driver Strength C */
+#define XSDPS_HC2_DRV_STR_D_MASK 0x0030U /**< Driver Strength D */
+#define XSDPS_HC2_EXEC_TNG_MASK 0x0040U /**< Execute Tuning */
+#define XSDPS_HC2_SAMP_CLK_SEL_MASK 0x0080U /**< Sampling Clock
+ Selection */
+#define XSDPS_HC2_ASYNC_INTR_EN_MASK 0x4000U /**< Asynchronous Interrupt
+ Enable */
+#define XSDPS_HC2_PRE_VAL_EN_MASK 0x8000U /**< Preset Value Enable */
+
+/* @} */
+
+/** @name Capabilities Register
+ *
+ * Capabilities register is a read only register which contains
+ * information about the host controller.
+ * Sufficient if read once after power on.
+ * Read Only
+ * @{
+ */
+#define XSDPS_CAP_TOUT_CLK_FREQ_MASK 0x0000003FU /**< Timeout clock freq
+ select */
+#define XSDPS_CAP_TOUT_CLK_UNIT_MASK 0x00000080U /**< Timeout clock unit -
+ MHz/KHz */
+#define XSDPS_CAP_MAX_BLK_LEN_MASK 0x00030000U /**< Max block length */
+#define XSDPS_CAP_MAX_BLK_LEN_512B_MASK 0x00000000U /**< Max block 512 bytes */
+#define XSDPS_CAP_MAX_BL_LN_1024_MASK 0x00010000U /**< Max block 1024 bytes */
+#define XSDPS_CAP_MAX_BL_LN_2048_MASK 0x00020000U /**< Max block 2048 bytes */
+#define XSDPS_CAP_MAX_BL_LN_4096_MASK 0x00030000U /**< Max block 4096 bytes */
+
+#define XSDPS_CAP_EXT_MEDIA_BUS_MASK 0x00040000U /**< Extended media bus */
+#define XSDPS_CAP_ADMA2_MASK 0x00080000U /**< ADMA2 support */
+#define XSDPS_CAP_HIGH_SPEED_MASK 0x00200000U /**< High speed support */
+#define XSDPS_CAP_SDMA_MASK 0x00400000U /**< SDMA support */
+#define XSDPS_CAP_SUSP_RESUME_MASK 0x00800000U /**< Suspend/Resume
+ support */
+#define XSDPS_CAP_VOLT_3V3_MASK 0x01000000U /**< 3.3V support */
+#define XSDPS_CAP_VOLT_3V0_MASK 0x02000000U /**< 3.0V support */
+#define XSDPS_CAP_VOLT_1V8_MASK 0x04000000U /**< 1.8V support */
+
+#define XSDPS_CAP_SYS_BUS_64_MASK 0x10000000U /**< 64 bit system bus
+ support */
+/* Spec 2.0 */
+#define XSDPS_CAP_INTR_MODE_MASK 0x08000000U /**< Interrupt mode
+ support */
+#define XSDPS_CAP_SPI_MODE_MASK 0x20000000U /**< SPI mode */
+#define XSDPS_CAP_SPI_BLOCK_MODE_MASK 0x40000000U /**< SPI block mode */
+
+
+/* Spec 3.0 */
+#define XSDPS_CAPS_ASYNC_INTR_MASK 0x20000000U /**< Async Interrupt
+ support */
+#define XSDPS_CAPS_SLOT_TYPE_MASK 0xC0000000U /**< Slot Type */
+#define XSDPS_CAPS_REM_CARD 0x00000000U /**< Removable Slot */
+#define XSDPS_CAPS_EMB_SLOT 0x40000000U /**< Embedded Slot */
+#define XSDPS_CAPS_SHR_BUS 0x80000000U /**< Shared Bus Slot */
+
+#define XSDPS_ECAPS_SDR50_MASK 0x00000001U /**< SDR50 Mode support */
+#define XSDPS_ECAPS_SDR104_MASK 0x00000002U /**< SDR104 Mode support */
+#define XSDPS_ECAPS_DDR50_MASK 0x00000004U /**< DDR50 Mode support */
+#define XSDPS_ECAPS_DRV_TYPE_A_MASK 0x00000010U /**< DriverType A support */
+#define XSDPS_ECAPS_DRV_TYPE_C_MASK 0x00000020U /**< DriverType C support */
+#define XSDPS_ECAPS_DRV_TYPE_D_MASK 0x00000040U /**< DriverType D support */
+#define XSDPS_ECAPS_TMR_CNT_MASK 0x00000F00U /**< Timer Count for
+ Re-tuning */
+#define XSDPS_ECAPS_USE_TNG_SDR50_MASK 0x00002000U /**< SDR50 Mode needs
+ tuning */
+#define XSDPS_ECAPS_RE_TNG_MODES_MASK 0x0000C000U /**< Re-tuning modes
+ support */
+#define XSDPS_ECAPS_RE_TNG_MODE1_MASK 0x00000000U /**< Re-tuning mode 1 */
+#define XSDPS_ECAPS_RE_TNG_MODE2_MASK 0x00004000U /**< Re-tuning mode 2 */
+#define XSDPS_ECAPS_RE_TNG_MODE3_MASK 0x00008000U /**< Re-tuning mode 3 */
+#define XSDPS_ECAPS_CLK_MULT_MASK 0x00FF0000U /**< Clock Multiplier value
+ for Programmable clock
+ mode */
+#define XSDPS_ECAPS_SPI_MODE_MASK 0x01000000U /**< SPI mode */
+#define XSDPS_ECAPS_SPI_BLK_MODE_MASK 0x02000000U /**< SPI block mode */
+
+/* @} */
+
+/** @name Present State Register
+ *
+ * Gives the current status of the host controller
+ * Read Only
+ * @{
+ */
+
+#define XSDPS_PSR_INHIBIT_CMD_MASK 0x00000001U /**< Command inhibit - CMD */
+#define XSDPS_PSR_INHIBIT_DAT_MASK 0x00000002U /**< Command Inhibit - DAT */
+#define XSDPS_PSR_DAT_ACTIVE_MASK 0x00000004U /**< DAT line active */
+#define XSDPS_PSR_RE_TUNING_REQ_MASK 0x00000008U /**< Re-tuning request */
+#define XSDPS_PSR_WR_ACTIVE_MASK 0x00000100U /**< Write transfer active */
+#define XSDPS_PSR_RD_ACTIVE_MASK 0x00000200U /**< Read transfer active */
+#define XSDPS_PSR_BUFF_WR_EN_MASK 0x00000400U /**< Buffer write enable */
+#define XSDPS_PSR_BUFF_RD_EN_MASK 0x00000800U /**< Buffer read enable */
+#define XSDPS_PSR_CARD_INSRT_MASK 0x00010000U /**< Card inserted */
+#define XSDPS_PSR_CARD_STABLE_MASK 0x00020000U /**< Card state stable */
+#define XSDPS_PSR_CARD_DPL_MASK 0x00040000U /**< Card detect pin level */
+#define XSDPS_PSR_WPS_PL_MASK 0x00080000U /**< Write protect switch
+ pin level */
+#define XSDPS_PSR_DAT30_SG_LVL_MASK 0x00F00000U /**< Data 3:0 signal lvl */
+#define XSDPS_PSR_CMD_SG_LVL_MASK 0x01000000U /**< Cmd Line signal lvl */
+#define XSDPS_PSR_DAT74_SG_LVL_MASK 0x1E000000U /**< Data 7:4 signal lvl */
+
+/* @} */
+
+/** @name Maximum Current Capabilities Register
+ *
+ * This register is read only register which contains
+ * information about current capabilities at each voltage levels.
+ * Read Only
+ * @{
+ */
+#define XSDPS_MAX_CUR_CAPS_1V8_MASK 0x00000F00U /**< Maximum Current
+ Capability at 1.8V */
+#define XSDPS_MAX_CUR_CAPS_3V0_MASK 0x000000F0U /**< Maximum Current
+ Capability at 3.0V */
+#define XSDPS_MAX_CUR_CAPS_3V3_MASK 0x0000000FU /**< Maximum Current
+ Capability at 3.3V */
+/* @} */
+
+
+/** @name Force Event for Auto CMD Error Status Register
+ *
+ * This register is write only register which contains
+ * control bits to generate events for Auto CMD error status.
+ * Write Only
+ * @{
+ */
+#define XSDPS_FE_AUTO_CMD12_NT_EX_MASK 0x0001U /**< Auto CMD12 Not
+ executed */
+#define XSDPS_FE_AUTO_CMD_TOUT_MASK 0x0002U /**< Auto CMD Timeout
+ Error */
+#define XSDPS_FE_AUTO_CMD_CRC_MASK 0x0004U /**< Auto CMD CRC Error */
+#define XSDPS_FE_AUTO_CMD_EB_MASK 0x0008U /**< Auto CMD End Bit
+ Error */
+#define XSDPS_FE_AUTO_CMD_IND_MASK 0x0010U /**< Auto CMD Index Error */
+#define XSDPS_FE_AUTO_CMD_CNI_ERR_MASK 0x0080U /**< Command not issued by
+ Auto CMD12 Error */
+/* @} */
+
+
+
+/** @name Force Event for Error Interrupt Status Register
+ *
+ * This register is write only register which contains
+ * control bits to generate events of error interrupt status register.
+ * Write Only
+ * @{
+ */
+#define XSDPS_FE_INTR_ERR_CT_MASK 0x0001U /**< Command Timeout
+ Error */
+#define XSDPS_FE_INTR_ERR_CCRC_MASK 0x0002U /**< Command CRC Error */
+#define XSDPS_FE_INTR_ERR_CEB_MASK 0x0004U /**< Command End Bit
+ Error */
+#define XSDPS_FE_INTR_ERR_CI_MASK 0x0008U /**< Command Index Error */
+#define XSDPS_FE_INTR_ERR_DT_MASK 0x0010U /**< Data Timeout Error */
+#define XSDPS_FE_INTR_ERR_DCRC_MASK 0x0020U /**< Data CRC Error */
+#define XSDPS_FE_INTR_ERR_DEB_MASK 0x0040U /**< Data End Bit Error */
+#define XSDPS_FE_INTR_ERR_CUR_LMT_MASK 0x0080U /**< Current Limit Error */
+#define XSDPS_FE_INTR_ERR_AUTO_CMD_MASK 0x0100U /**< Auto CMD Error */
+#define XSDPS_FE_INTR_ERR_ADMA_MASK 0x0200U /**< ADMA Error */
+#define XSDPS_FE_INTR_ERR_TR_MASK 0x1000U /**< Target Response */
+#define XSDPS_FE_INTR_VEND_SPF_ERR_MASK 0xE000U /**< Vendor Specific
+ Error */
+
+/* @} */
+
+/** @name ADMA Error Status Register
+ *
+ * This register is read only register which contains
+ * status information about ADMA errors.
+ * Read Only
+ * @{
+ */
+#define XSDPS_ADMA_ERR_MM_LEN_MASK 0x04U /**< ADMA Length Mismatch
+ Error */
+#define XSDPS_ADMA_ERR_STATE_MASK 0x03U /**< ADMA Error State */
+#define XSDPS_ADMA_ERR_STATE_STOP_MASK 0x00U /**< ADMA Error State
+ STOP */
+#define XSDPS_ADMA_ERR_STATE_FDS_MASK 0x01U /**< ADMA Error State
+ FDS */
+#define XSDPS_ADMA_ERR_STATE_TFR_MASK 0x03U /**< ADMA Error State
+ TFR */
+/* @} */
+
+/** @name Preset Values Register
+ *
+ * This register is read only register which contains
+ * preset values for each of speed modes.
+ * Read Only
+ * @{
+ */
+#define XSDPS_PRE_VAL_SDCLK_FSEL_MASK 0x03FFU /**< SDCLK Frequency
+ Select Value */
+#define XSDPS_PRE_VAL_CLK_GEN_SEL_MASK 0x0400U /**< Clock Generator
+ Mode Select */
+#define XSDPS_PRE_VAL_DRV_STR_SEL_MASK 0xC000U /**< Driver Strength
+ Select Value */
+
+/* @} */
+
+/** @name Slot Interrupt Status Register
+ *
+ * This register is read only register which contains
+ * interrupt slot signal for each slot.
+ * Read Only
+ * @{
+ */
+#define XSDPS_SLOT_INTR_STS_INT_MASK 0x0007U /**< Interrupt Signal
+ mask */
+
+/* @} */
+
+/** @name Host Controller Version Register
+ *
+ * This register is read only register which contains
+ * Host Controller and Vendor Specific version.
+ * Read Only
+ * @{
+ */
+#define XSDPS_HC_VENDOR_VER 0xFF00U /**< Vendor
+ Specification
+ version mask */
+#define XSDPS_HC_SPEC_VER_MASK 0x00FFU /**< Host
+ Specification
+ version mask */
+#define XSDPS_HC_SPEC_V3 0x0002U
+#define XSDPS_HC_SPEC_V2 0x0001U
+#define XSDPS_HC_SPEC_V1 0x0000U
+
+/** @name Block size mask for 512 bytes
+ *
+ * Block size mask for 512 bytes - This is the default block size.
+ * @{
+ */
+
+#define XSDPS_BLK_SIZE_512_MASK 0x200U
+
+/* @} */
+
+/** @name Commands
+ *
+ * Constant definitions for commands and response related to SD
+ * @{
+ */
+
+#define XSDPS_APP_CMD_PREFIX 0x8000U
+#define CMD0 0x0000U
+#define CMD1 0x0100U
+#define CMD2 0x0200U
+#define CMD3 0x0300U
+#define CMD4 0x0400U
+#define CMD5 0x0500U
+#define CMD6 0x0600U
+#define ACMD6 (XSDPS_APP_CMD_PREFIX + 0x0600U)
+#define CMD7 0x0700U
+#define CMD8 0x0800U
+#define CMD9 0x0900U
+#define CMD10 0x0A00U
+#define CMD11 0x0B00U
+#define CMD12 0x0C00U
+#define ACMD13 (XSDPS_APP_CMD_PREFIX + 0x0D00U)
+#define CMD16 0x1000U
+#define CMD17 0x1100U
+#define CMD18 0x1200U
+#define CMD19 0x1300U
+#define CMD21 0x1500U
+#define CMD23 0x1700U
+#define ACMD23 (XSDPS_APP_CMD_PREFIX + 0x1700U)
+#define CMD24 0x1800U
+#define CMD25 0x1900U
+#define CMD41 0x2900U
+#define ACMD41 (XSDPS_APP_CMD_PREFIX + 0x2900U)
+#define ACMD42 (XSDPS_APP_CMD_PREFIX + 0x2A00U)
+#define ACMD51 (XSDPS_APP_CMD_PREFIX + 0x3300U)
+#define CMD52 0x3400U
+#define CMD55 0x3700U
+#define CMD58 0x3A00U
+
+#define RESP_NONE (u32)XSDPS_CMD_RESP_NONE_MASK
+#define RESP_R1 (u32)XSDPS_CMD_RESP_L48_MASK | (u32)XSDPS_CMD_CRC_CHK_EN_MASK | \
+ (u32)XSDPS_CMD_INX_CHK_EN_MASK
+
+#define RESP_R1B (u32)XSDPS_CMD_RESP_L48_BSY_CHK_MASK | \
+ (u32)XSDPS_CMD_CRC_CHK_EN_MASK | (u32)XSDPS_CMD_INX_CHK_EN_MASK
+
+#define RESP_R2 (u32)XSDPS_CMD_RESP_L136_MASK | (u32)XSDPS_CMD_CRC_CHK_EN_MASK
+#define RESP_R3 (u32)XSDPS_CMD_RESP_L48_MASK
+
+#define RESP_R6 (u32)XSDPS_CMD_RESP_L48_BSY_CHK_MASK | \
+ (u32)XSDPS_CMD_CRC_CHK_EN_MASK | (u32)XSDPS_CMD_INX_CHK_EN_MASK
+
+/* @} */
+
+/* Card Interface Conditions Definitions */
+#define XSDPS_CIC_CHK_PATTERN 0xAAU
+#define XSDPS_CIC_VOLT_MASK (0xFU<<8)
+#define XSDPS_CIC_VOLT_2V7_3V6 (1U<<8)
+#define XSDPS_CIC_VOLT_LOW (1U<<9)
+
+/* Operation Conditions Register Definitions */
+#define XSDPS_OCR_PWRUP_STS (1U<<31)
+#define XSDPS_OCR_CC_STS (1U<<30)
+#define XSDPS_OCR_S18 (1U<<24)
+#define XSDPS_OCR_3V5_3V6 (1U<<23)
+#define XSDPS_OCR_3V4_3V5 (1U<<22)
+#define XSDPS_OCR_3V3_3V4 (1U<<21)
+#define XSDPS_OCR_3V2_3V3 (1U<<20)
+#define XSDPS_OCR_3V1_3V2 (1U<<19)
+#define XSDPS_OCR_3V0_3V1 (1U<<18)
+#define XSDPS_OCR_2V9_3V0 (1U<<17)
+#define XSDPS_OCR_2V8_2V9 (1U<<16)
+#define XSDPS_OCR_2V7_2V8 (1U<<15)
+#define XSDPS_OCR_1V7_1V95 (1U<<7)
+#define XSDPS_OCR_HIGH_VOL 0x00FF8000U
+#define XSDPS_OCR_LOW_VOL 0x00000080U
+
+/* SD Card Configuration Register Definitions */
+#define XSDPS_SCR_REG_LEN 8U
+#define XSDPS_SCR_STRUCT_MASK (0xFU<<28)
+#define XSDPS_SCR_SPEC_MASK (0xFU<<24)
+#define XSDPS_SCR_SPEC_1V0 0U
+#define XSDPS_SCR_SPEC_1V1 (1U<<24)
+#define XSDPS_SCR_SPEC_2V0_3V0 (2U<<24)
+#define XSDPS_SCR_MEM_VAL_AF_ERASE (1U<<23)
+#define XSDPS_SCR_SEC_SUPP_MASK (7U<<20)
+#define XSDPS_SCR_SEC_SUPP_NONE 0U
+#define XSDPS_SCR_SEC_SUPP_1V1 (2U<<20)
+#define XSDPS_SCR_SEC_SUPP_2V0 (3U<<20)
+#define XSDPS_SCR_SEC_SUPP_3V0 (4U<<20)
+#define XSDPS_SCR_BUS_WIDTH_MASK (0xFU<<16)
+#define XSDPS_SCR_BUS_WIDTH_1 (1U<<16)
+#define XSDPS_SCR_BUS_WIDTH_4 (4U<<16)
+#define XSDPS_SCR_SPEC3_MASK (1U<<12)
+#define XSDPS_SCR_SPEC3_2V0 0U
+#define XSDPS_SCR_SPEC3_3V0 (1U<<12)
+#define XSDPS_SCR_CMD_SUPP_MASK 0x3U
+#define XSDPS_SCR_CMD23_SUPP (1U<<1)
+#define XSDPS_SCR_CMD20_SUPP (1U<<0)
+
+/* Card Status Register Definitions */
+#define XSDPS_CD_STS_OUT_OF_RANGE (1U<<31)
+#define XSDPS_CD_STS_ADDR_ERR (1U<<30)
+#define XSDPS_CD_STS_BLK_LEN_ERR (1U<<29)
+#define XSDPS_CD_STS_ER_SEQ_ERR (1U<<28)
+#define XSDPS_CD_STS_ER_PRM_ERR (1U<<27)
+#define XSDPS_CD_STS_WP_VIO (1U<<26)
+#define XSDPS_CD_STS_IS_LOCKED (1U<<25)
+#define XSDPS_CD_STS_LOCK_UNLOCK_FAIL (1U<<24)
+#define XSDPS_CD_STS_CMD_CRC_ERR (1U<<23)
+#define XSDPS_CD_STS_ILGL_CMD (1U<<22)
+#define XSDPS_CD_STS_CARD_ECC_FAIL (1U<<21)
+#define XSDPS_CD_STS_CC_ERR (1U<<20)
+#define XSDPS_CD_STS_ERR (1U<<19)
+#define XSDPS_CD_STS_CSD_OVRWR (1U<<16)
+#define XSDPS_CD_STS_WP_ER_SKIP (1U<<15)
+#define XSDPS_CD_STS_CARD_ECC_DIS (1U<<14)
+#define XSDPS_CD_STS_ER_RST (1U<<13)
+#define XSDPS_CD_STS_CUR_STATE (0xFU<<9)
+#define XSDPS_CD_STS_RDY_FOR_DATA (1U<<8)
+#define XSDPS_CD_STS_APP_CMD (1U<<5)
+#define XSDPS_CD_STS_AKE_SEQ_ERR (1U<<2)
+
+/* Switch Function Definitions CMD6 */
+#define XSDPS_SWITCH_SD_RESP_LEN 64U
+
+#define XSDPS_SWITCH_FUNC_SWITCH (1U<<31)
+#define XSDPS_SWITCH_FUNC_CHECK 0U
+
+#define XSDPS_MODE_FUNC_GRP1 1U
+#define XSDPS_MODE_FUNC_GRP2 2U
+#define XSDPS_MODE_FUNC_GRP3 3U
+#define XSDPS_MODE_FUNC_GRP4 4U
+#define XSDPS_MODE_FUNC_GRP5 5U
+#define XSDPS_MODE_FUNC_GRP6 6U
+
+#define XSDPS_FUNC_GRP_DEF_VAL 0xFU
+#define XSDPS_FUNC_ALL_GRP_DEF_VAL 0xFFFFFFU
+
+#define XSDPS_ACC_MODE_DEF_SDR12 0U
+#define XSDPS_ACC_MODE_HS_SDR25 1U
+#define XSDPS_ACC_MODE_SDR50 2U
+#define XSDPS_ACC_MODE_SDR104 3U
+#define XSDPS_ACC_MODE_DDR50 4U
+
+#define XSDPS_CMD_SYS_ARG_SHIFT 4U
+#define XSDPS_CMD_SYS_DEF 0U
+#define XSDPS_CMD_SYS_eC 1U
+#define XSDPS_CMD_SYS_OTP 3U
+#define XSDPS_CMD_SYS_ASSD 4U
+#define XSDPS_CMD_SYS_VEND 5U
+
+#define XSDPS_DRV_TYPE_ARG_SHIFT 8U
+#define XSDPS_DRV_TYPE_B 0U
+#define XSDPS_DRV_TYPE_A 1U
+#define XSDPS_DRV_TYPE_C 2U
+#define XSDPS_DRV_TYPE_D 3U
+
+#define XSDPS_CUR_LIM_ARG_SHIFT 12U
+#define XSDPS_CUR_LIM_200 0U
+#define XSDPS_CUR_LIM_400 1U
+#define XSDPS_CUR_LIM_600 2U
+#define XSDPS_CUR_LIM_800 3U
+
+#define CSD_SPEC_VER_MASK 0x3C0000U
+#define READ_BLK_LEN_MASK 0x00000F00U
+#define C_SIZE_MULT_MASK 0x00000380U
+#define C_SIZE_LOWER_MASK 0xFFC00000U
+#define C_SIZE_UPPER_MASK 0x00000003U
+#define CSD_STRUCT_MASK 0x00C00000U
+#define CSD_V2_C_SIZE_MASK 0x3FFFFF00U
+
+/* EXT_CSD field definitions */
+#define XSDPS_EXT_CSD_SIZE 512U
+
+#define EXT_CSD_WR_REL_PARAM_EN (1U<<2)
+
+#define EXT_CSD_BOOT_WP_B_PWR_WP_DIS (0x40U)
+#define EXT_CSD_BOOT_WP_B_PERM_WP_DIS (0x10U)
+#define EXT_CSD_BOOT_WP_B_PERM_WP_EN (0x04U)
+#define EXT_CSD_BOOT_WP_B_PWR_WP_EN (0x01U)
+
+#define EXT_CSD_PART_CONFIG_ACC_MASK (0x7U)
+#define EXT_CSD_PART_CONFIG_ACC_BOOT0 (0x1U)
+#define EXT_CSD_PART_CONFIG_ACC_RPMB (0x3U)
+#define EXT_CSD_PART_CONFIG_ACC_GP0 (0x4U)
+
+#define EXT_CSD_PART_SUPPORT_PART_EN (0x1U)
+
+#define EXT_CSD_CMD_SET_NORMAL (1U<<0)
+#define EXT_CSD_CMD_SET_SECURE (1U<<1)
+#define EXT_CSD_CMD_SET_CPSECURE (1U<<2)
+
+#define EXT_CSD_CARD_TYPE_26 (1U<<0) /* Card can run at 26MHz */
+#define EXT_CSD_CARD_TYPE_52 (1U<<1) /* Card can run at 52MHz */
+#define EXT_CSD_CARD_TYPE_MASK 0x3FU /* Mask out reserved bits */
+#define EXT_CSD_CARD_TYPE_DDR_1_8V (1U<<2) /* Card can run at 52MHz */
+ /* DDR mode @1.8V or 3V I/O */
+#define EXT_CSD_CARD_TYPE_DDR_1_2V (1U<<3) /* Card can run at 52MHz */
+ /* DDR mode @1.2V I/O */
+#define EXT_CSD_CARD_TYPE_DDR_52 (EXT_CSD_CARD_TYPE_DDR_1_8V \
+ | EXT_CSD_CARD_TYPE_DDR_1_2V)
+#define EXT_CSD_CARD_TYPE_SDR_1_8V (1U<<4) /* Card can run at 200MHz */
+#define EXT_CSD_CARD_TYPE_SDR_1_2V (1U<<5) /* Card can run at 200MHz */
+ /* SDR mode @1.2V I/O */
+#define EXT_CSD_BUS_WIDTH_BYTE 183U
+#define EXT_CSD_BUS_WIDTH_1_BIT 0U /* Card is in 1 bit mode */
+#define EXT_CSD_BUS_WIDTH_4_BIT 1U /* Card is in 4 bit mode */
+#define EXT_CSD_BUS_WIDTH_8_BIT 2U /* Card is in 8 bit mode */
+#define EXT_CSD_BUS_WIDTH_DDR_4_BIT 5U /* Card is in 4 bit DDR mode */
+#define EXT_CSD_BUS_WIDTH_DDR_8_BIT 6U /* Card is in 8 bit DDR mode */
+
+#define EXT_CSD_HS_TIMING_BYTE 185U
+#define EXT_CSD_HS_TIMING_DEF 0U
+#define EXT_CSD_HS_TIMING_HIGH 1U /* Card is in high speed mode */
+#define EXT_CSD_HS_TIMING_HS200 2U /* Card is in HS200 mode */
+
+#define EXT_CSD_RST_N_FUN_BYTE 162U
+#define EXT_CSD_RST_N_FUN_TEMP_DIS 0U /* RST_n signal is temporarily disabled */
+#define EXT_CSD_RST_N_FUN_PERM_EN 1U /* RST_n signal is permanently enabled */
+#define EXT_CSD_RST_N_FUN_PERM_DIS 2U /* RST_n signal is permanently disabled */
+
+#define XSDPS_EXT_CSD_CMD_SET 0U
+#define XSDPS_EXT_CSD_SET_BITS 1U
+#define XSDPS_EXT_CSD_CLR_BITS 2U
+#define XSDPS_EXT_CSD_WRITE_BYTE 3U
+
+#define XSDPS_MMC_DEF_SPEED_ARG (((u32)XSDPS_EXT_CSD_WRITE_BYTE << 24) \
+ | ((u32)EXT_CSD_HS_TIMING_BYTE << 16) \
+ | ((u32)EXT_CSD_HS_TIMING_DEF << 8))
+
+#define XSDPS_MMC_HIGH_SPEED_ARG (((u32)XSDPS_EXT_CSD_WRITE_BYTE << 24) \
+ | ((u32)EXT_CSD_HS_TIMING_BYTE << 16) \
+ | ((u32)EXT_CSD_HS_TIMING_HIGH << 8))
+
+#define XSDPS_MMC_HS200_ARG (((u32)XSDPS_EXT_CSD_WRITE_BYTE << 24) \
+ | ((u32)EXT_CSD_HS_TIMING_BYTE << 16) \
+ | ((u32)EXT_CSD_HS_TIMING_HS200 << 8))
+
+#define XSDPS_MMC_1_BIT_BUS_ARG (((u32)XSDPS_EXT_CSD_WRITE_BYTE << 24) \
+ | ((u32)EXT_CSD_BUS_WIDTH_BYTE << 16) \
+ | ((u32)EXT_CSD_BUS_WITH_1_BIT << 8))
+
+#define XSDPS_MMC_4_BIT_BUS_ARG (((u32)XSDPS_EXT_CSD_WRITE_BYTE << 24) \
+ | ((u32)EXT_CSD_BUS_WIDTH_BYTE << 16) \
+ | ((u32)EXT_CSD_BUS_WIDTH_4_BIT << 8))
+
+#define XSDPS_MMC_8_BIT_BUS_ARG (((u32)XSDPS_EXT_CSD_WRITE_BYTE << 24) \
+ | ((u32)EXT_CSD_BUS_WIDTH_BYTE << 16) \
+ | ((u32)EXT_CSD_BUS_WIDTH_8_BIT << 8))
+
+#define XSDPS_MMC_DDR_4_BIT_BUS_ARG (((u32)XSDPS_EXT_CSD_WRITE_BYTE << 24) \
+ | ((u32)EXT_CSD_BUS_WIDTH_BYTE << 16) \
+ | ((u32)EXT_CSD_BUS_WIDTH_DDR_4_BIT << 8))
+
+#define XSDPS_MMC_DDR_8_BIT_BUS_ARG (((u32)XSDPS_EXT_CSD_WRITE_BYTE << 24) \
+ | ((u32)EXT_CSD_BUS_WIDTH_BYTE << 16) \
+ | ((u32)EXT_CSD_BUS_WIDTH_DDR_8_BIT << 8))
+
+#define XSDPS_MMC_RST_FUN_EN_ARG (((u32)XSDPS_EXT_CSD_WRITE_BYTE << 24) \
+ | ((u32)EXT_CSD_RST_N_FUN_BYTE << 16) \
+ | ((u32)EXT_CSD_RST_N_FUN_PERM_EN << 8))
+
+#define XSDPS_MMC_DELAY_FOR_SWITCH 1000U
+
+/* @} */
+
+/* @400KHz, in usec */
+#define XSDPS_74CLK_DELAY 2960U
+#define XSDPS_100CLK_DELAY 4000U
+#define XSDPS_INIT_DELAY 10000U
+
+#define XSDPS_DEF_VOLT_LVL XSDPS_PC_BUS_VSEL_3V0_MASK
+#define XSDPS_CARD_DEF_ADDR 0x1234U
+
+#define XSDPS_CARD_SD 1U
+#define XSDPS_CARD_MMC 2U
+#define XSDPS_CARD_SDIO 3U
+#define XSDPS_CARD_SDCOMBO 4U
+#define XSDPS_CHIP_EMMC 5U
+
+
+/** @name ADMA2 Descriptor related definitions
+ *
+ * ADMA2 Descriptor related definitions
+ * @{
+ */
+
+#define XSDPS_DESC_MAX_LENGTH 65536U
+
+#define XSDPS_DESC_VALID (0x1U << 0)
+#define XSDPS_DESC_END (0x1U << 1)
+#define XSDPS_DESC_INT (0x1U << 2)
+#define XSDPS_DESC_TRAN (0x2U << 4)
+
+/* @} */
+
+/* For changing clock frequencies */
+#define XSDPS_CLK_400_KHZ 400000U /**< 400 KHZ */
+#define XSDPS_CLK_50_MHZ 50000000U /**< 50 MHZ */
+#define XSDPS_CLK_52_MHZ 52000000U /**< 52 MHZ */
+#define XSDPS_SD_VER_1_0 0x1U /**< SD ver 1 */
+#define XSDPS_SD_VER_2_0 0x2U /**< SD ver 2 */
+#define XSDPS_SCR_BLKCNT 1U
+#define XSDPS_SCR_BLKSIZE 8U
+#define XSDPS_1_BIT_WIDTH 0x1U
+#define XSDPS_4_BIT_WIDTH 0x2U
+#define XSDPS_8_BIT_WIDTH 0x3U
+#define XSDPS_UHS_SPEED_MODE_SDR12 0x0U
+#define XSDPS_UHS_SPEED_MODE_SDR25 0x1U
+#define XSDPS_UHS_SPEED_MODE_SDR50 0x2U
+#define XSDPS_UHS_SPEED_MODE_SDR104 0x3U
+#define XSDPS_UHS_SPEED_MODE_DDR50 0x4U
+#define XSDPS_HIGH_SPEED_MODE 0x5U
+#define XSDPS_DEFAULT_SPEED_MODE 0x6U
+#define XSDPS_HS200_MODE 0x7U
+#define XSDPS_DDR52_MODE 0x4U
+#define XSDPS_SWITCH_CMD_BLKCNT 1U
+#define XSDPS_SWITCH_CMD_BLKSIZE 64U
+#define XSDPS_SWITCH_CMD_HS_GET 0x00FFFFF0U
+#define XSDPS_SWITCH_CMD_HS_SET 0x80FFFFF1U
+#define XSDPS_SWITCH_CMD_SDR12_SET 0x80FFFFF0U
+#define XSDPS_SWITCH_CMD_SDR25_SET 0x80FFFFF1U
+#define XSDPS_SWITCH_CMD_SDR50_SET 0x80FFFFF2U
+#define XSDPS_SWITCH_CMD_SDR104_SET 0x80FFFFF3U
+#define XSDPS_SWITCH_CMD_DDR50_SET 0x80FFFFF4U
+#define XSDPS_EXT_CSD_CMD_BLKCNT 1U
+#define XSDPS_EXT_CSD_CMD_BLKSIZE 512U
+#define XSDPS_TUNING_CMD_BLKCNT 1U
+#define XSDPS_TUNING_CMD_BLKSIZE 64U
+
+#define XSDPS_HIGH_SPEED_MAX_CLK 50000000U
+#define XSDPS_UHS_SDR104_MAX_CLK 208000000U
+#define XSDPS_UHS_SDR50_MAX_CLK 100000000U
+#define XSDPS_UHS_DDR50_MAX_CLK 50000000U
+#define XSDPS_UHS_SDR25_MAX_CLK 50000000U
+#define XSDPS_UHS_SDR12_MAX_CLK 25000000U
+
+#define SD_DRIVER_TYPE_B 0x01U
+#define SD_DRIVER_TYPE_A 0x02U
+#define SD_DRIVER_TYPE_C 0x04U
+#define SD_DRIVER_TYPE_D 0x08U
+#define SD_SET_CURRENT_LIMIT_200 0U
+#define SD_SET_CURRENT_LIMIT_400 1U
+#define SD_SET_CURRENT_LIMIT_600 2U
+#define SD_SET_CURRENT_LIMIT_800 3U
+
+#define SD_MAX_CURRENT_200 (1U << SD_SET_CURRENT_LIMIT_200)
+#define SD_MAX_CURRENT_400 (1U << SD_SET_CURRENT_LIMIT_400)
+#define SD_MAX_CURRENT_600 (1U << SD_SET_CURRENT_LIMIT_600)
+#define SD_MAX_CURRENT_800 (1U << SD_SET_CURRENT_LIMIT_800)
+
+#define XSDPS_SD_SDR12_MAX_CLK 25000000U
+#define XSDPS_SD_SDR25_MAX_CLK 50000000U
+#define XSDPS_SD_SDR50_MAX_CLK 100000000U
+#define XSDPS_SD_DDR50_MAX_CLK 50000000U
+#define XSDPS_SD_SDR104_MAX_CLK 208000000U
+/*
+ * XSDPS_SD_INPUT_MAX_CLK is set to 175000000 in order to keep it smaller
+ * than the clock value coming from the core. This value is kept to safely
+ * switch to SDR104 mode if the SD card supports it.
+ */
+#define XSDPS_SD_INPUT_MAX_CLK 175000000U
+
+#define XSDPS_MMC_HS200_MAX_CLK 200000000U
+#define XSDPS_MMC_HSD_MAX_CLK 52000000U
+#define XSDPS_MMC_DDR_MAX_CLK 52000000U
+
+#define XSDPS_CARD_STATE_IDLE 0U
+#define XSDPS_CARD_STATE_RDY 1U
+#define XSDPS_CARD_STATE_IDEN 2U
+#define XSDPS_CARD_STATE_STBY 3U
+#define XSDPS_CARD_STATE_TRAN 4U
+#define XSDPS_CARD_STATE_DATA 5U
+#define XSDPS_CARD_STATE_RCV 6U
+#define XSDPS_CARD_STATE_PROG 7U
+#define XSDPS_CARD_STATE_DIS 8U
+#define XSDPS_CARD_STATE_BTST 9U
+#define XSDPS_CARD_STATE_SLP 10U
+
+#define XSDPS_SLOT_REM 0U
+#define XSDPS_SLOT_EMB 1U
+
+#define XSDPS_WIDTH_8 8U
+#define XSDPS_WIDTH_4 4U
+
+
+#if defined (ARMR5) || defined (__aarch64__) || defined (ARMA53_32) || defined (__MICROBLAZE__)
+#ifdef versal
+#define SD_ITAPDLY_SEL_MASK 0x000000FFU
+#define SD_OTAPDLY_SEL_MASK 0x0000003FU
+#define SD_ITAPDLY 0x0000F0F8U
+#define SD_OTAPDLY 0x0000F0FCU
+#define SD_ITAPCHGWIN 0x00000200U
+#define SD_ITAPDLYENA 0x00000100U
+#define SD_OTAPDLYENA 0x00000040U
+#define SD_OTAPDLYSEL_HS200_B0 0x00000002U
+#define SD_OTAPDLYSEL_HS200_B2 0x00000002U
+#define SD_ITAPDLYSEL_SD50 0x0000000EU
+#define SD_OTAPDLYSEL_SD50 0x00000003U
+#define SD_ITAPDLYSEL_SD_DDR50 0x00000036U
+#define SD_ITAPDLYSEL_EMMC_DDR50 0x0000001EU
+#define SD_OTAPDLYSEL_SD_DDR50 0x00000003U
+#define SD_OTAPDLYSEL_EMMC_DDR50 0x00000005U
+#define SD_ITAPDLYSEL_HSD 0x0000002CU
+#define SD_OTAPDLYSEL_SD_HSD 0x00000004U
+#define SD_OTAPDLYSEL_EMMC_HSD 0x00000005U
+#else
+#define SD0_ITAPDLY_SEL_MASK 0x000000FFU
+#define SD0_OTAPDLY_SEL_MASK 0x0000003FU
+#define SD1_ITAPDLY_SEL_MASK 0x00FF0000U
+#define SD1_OTAPDLY_SEL_MASK 0x003F0000U
+#define SD_DLL_CTRL 0x00000358U
+#define SD_ITAPDLY 0x00000314U
+#define SD_OTAPDLY 0x00000318U
+#define SD0_DLL_RST 0x00000004U
+#define SD1_DLL_RST 0x00040000U
+#define SD0_ITAPCHGWIN 0x00000200U
+#define SD0_ITAPDLYENA 0x00000100U
+#define SD0_OTAPDLYENA 0x00000040U
+#define SD1_ITAPCHGWIN 0x02000000U
+#define SD1_ITAPDLYENA 0x01000000U
+#define SD1_OTAPDLYENA 0x00400000U
+#define SD_OTAPDLYSEL_HS200_B0 0x00000003U
+#define SD_OTAPDLYSEL_HS200_B2 0x00000002U
+#define SD_ITAPDLYSEL_SD50 0x00000014U
+#define SD_OTAPDLYSEL_SD50 0x00000003U
+#define SD_ITAPDLYSEL_SD_DDR50 0x0000003DU
+#define SD_ITAPDLYSEL_EMMC_DDR50 0x00000012U
+#define SD_OTAPDLYSEL_SD_DDR50 0x00000004U
+#define SD_OTAPDLYSEL_EMMC_DDR50 0x00000006U
+#define SD_ITAPDLYSEL_HSD 0x00000015U
+#define SD_OTAPDLYSEL_SD_HSD 0x00000005U
+#define SD_OTAPDLYSEL_EMMC_HSD 0x00000006U
+#endif
+
+#endif
+
+#ifdef __MICROBLAZE__
+#define XPS_SYS_CTRL_BASEADDR 0xFF180000U
+#endif
+
+/**************************** Type Definitions *******************************/
+
+/***************** Macros (Inline Functions) Definitions *********************/
+#define XSdPs_In64 Xil_In64
+#define XSdPs_Out64 Xil_Out64
+
+#define XSdPs_In32 Xil_In32
+#define XSdPs_Out32 Xil_Out32
+
+#define XSdPs_In16 Xil_In16
+#define XSdPs_Out16 Xil_Out16
+
+#define XSdPs_In8 Xil_In8
+#define XSdPs_Out8 Xil_Out8
+
+/****************************************************************************/
+/**
+* Read a register.
+*
+* @param InstancePtr is the pointer to the sdps instance.
+* @param RegOffset contains the offset from the 1st register of the
+* device to the target register.
+*
+* @return The value read from the register.
+*
+* @note C-Style signature:
+* u32 XSdPs_ReadReg(XSdPs *InstancePtr. s32 RegOffset)
+*
+******************************************************************************/
+#define XSdPs_ReadReg64(InstancePtr, RegOffset) \
+ XSdPs_In64((InstancePtr->Config.BaseAddress) + RegOffset)
+
+/***************************************************************************/
+/**
+* Write to a register.
+*
+* @param InstancePtr is the pointer to the sdps instance.
+* @param RegOffset contains the offset from the 1st register of the
+* device to target register.
+* @param RegisterValue is the value to be written to the register.
+*
+* @return None.
+*
+* @note C-Style signature:
+* void XSdPs_WriteReg(XSdPs *InstancePtr, s32 RegOffset,
+* u64 RegisterValue)
+*
+******************************************************************************/
+#define XSdPs_WriteReg64(InstancePtr, RegOffset, RegisterValue) \
+ XSdPs_Out64((InstancePtr->Config.BaseAddress) + (RegOffset), \
+ (RegisterValue))
+
+/****************************************************************************/
+/**
+* Read a register.
+*
+* @param BaseAddress contains the base address of the device.
+* @param RegOffset contains the offset from the 1st register of the
+* device to the target register.
+*
+* @return The value read from the register.
+*
+* @note C-Style signature:
+* u32 XSdPs_ReadReg(u32 BaseAddress. int RegOffset)
+*
+******************************************************************************/
+#define XSdPs_ReadReg(BaseAddress, RegOffset) \
+ XSdPs_In32((BaseAddress) + (RegOffset))
+
+/***************************************************************************/
+/**
+* Write to a register.
+*
+* @param BaseAddress contains the base address of the device.
+* @param RegOffset contains the offset from the 1st register of the
+* device to target register.
+* @param RegisterValue is the value to be written to the register.
+*
+* @return None.
+*
+* @note C-Style signature:
+* void XSdPs_WriteReg(u32 BaseAddress, int RegOffset,
+* u32 RegisterValue)
+*
+******************************************************************************/
+#define XSdPs_WriteReg(BaseAddress, RegOffset, RegisterValue) \
+ XSdPs_Out32((BaseAddress) + (RegOffset), (RegisterValue))
+
+/****************************************************************************/
+/**
+* Read a register.
+*
+* @param BaseAddress contains the base address of the device.
+* @param RegOffset contains the offset from the 1st register of the
+* device to the target register.
+*
+* @return The value read from the register.
+*
+* @note C-Style signature:
+* u16 XSdPs_ReadReg(u32 BaseAddress. int RegOffset)
+*
+******************************************************************************/
+static INLINE u16 XSdPs_ReadReg16(u32 BaseAddress, u8 RegOffset)
+{
+#if defined (__MICROBLAZE__)
+ u32 Reg;
+ BaseAddress += RegOffset & 0xFC;
+ Reg = XSdPs_In32(BaseAddress);
+ Reg >>= ((RegOffset & 0x3)*8);
+ return (u16)Reg;
+#else
+ return XSdPs_In16((BaseAddress) + (RegOffset));
+#endif
+}
+
+/***************************************************************************/
+/**
+* Write to a register.
+*
+* @param BaseAddress contains the base address of the device.
+* @param RegOffset contains the offset from the 1st register of the
+* device to target register.
+* @param RegisterValue is the value to be written to the register.
+*
+* @return None.
+*
+* @note C-Style signature:
+* void XSdPs_WriteReg(u32 BaseAddress, int RegOffset,
+* u16 RegisterValue)
+*
+******************************************************************************/
+
+static INLINE void XSdPs_WriteReg16(u32 BaseAddress, u8 RegOffset, u16 RegisterValue)
+{
+#if defined (__MICROBLAZE__)
+ u32 Reg;
+ BaseAddress += RegOffset & 0xFC;
+ Reg = XSdPs_In32(BaseAddress);
+ Reg &= ~(0xFFFF<<((RegOffset & 0x3)*8));
+ Reg |= RegisterValue <<((RegOffset & 0x3)*8);
+ XSdPs_Out32(BaseAddress, Reg);
+#else
+ XSdPs_Out16((BaseAddress) + (RegOffset), (RegisterValue));
+#endif
+}
+
+/****************************************************************************/
+/**
+* Read a register.
+*
+* @param BaseAddress contains the base address of the device.
+* @param RegOffset contains the offset from the 1st register of the
+* device to the target register.
+*
+* @return The value read from the register.
+*
+* @note C-Style signature:
+* u8 XSdPs_ReadReg(u32 BaseAddress. int RegOffset)
+*
+******************************************************************************/
+static INLINE u8 XSdPs_ReadReg8(u32 BaseAddress, u8 RegOffset)
+{
+#if defined (__MICROBLAZE__)
+ u32 Reg;
+ BaseAddress += RegOffset & 0xFC;
+ Reg = XSdPs_In32(BaseAddress);
+ Reg >>= ((RegOffset & 0x3)*8);
+ return (u8)Reg;
+#else
+ return XSdPs_In8((BaseAddress) + (RegOffset));
+#endif
+}
+/***************************************************************************/
+/**
+* Write to a register.
+*
+* @param BaseAddress contains the base address of the device.
+* @param RegOffset contains the offset from the 1st register of the
+* device to target register.
+* @param RegisterValue is the value to be written to the register.
+*
+* @return None.
+*
+* @note C-Style signature:
+* void XSdPs_WriteReg(u32 BaseAddress, int RegOffset,
+* u8 RegisterValue)
+*
+******************************************************************************/
+static INLINE void XSdPs_WriteReg8(u32 BaseAddress, u8 RegOffset, u8 RegisterValue)
+{
+#if defined (__MICROBLAZE__)
+ u32 Reg;
+ BaseAddress += RegOffset & 0xFC;
+ Reg = XSdPs_In32(BaseAddress);
+ Reg &= ~(0xFF<<((RegOffset & 0x3)*8));
+ Reg |= RegisterValue <<((RegOffset & 0x3)*8);
+ XSdPs_Out32(BaseAddress, Reg);
+#else
+ XSdPs_Out8((BaseAddress) + (RegOffset), (RegisterValue));
+#endif
+}
+/***************************************************************************/
+/**
+* Macro to get present status register
+*
+* @param BaseAddress contains the base address of the device.
+*
+* @return None.
+*
+* @note C-Style signature:
+* void XSdPs_WriteReg(u32 BaseAddress, int RegOffset,
+* u8 RegisterValue)
+*
+******************************************************************************/
+#define XSdPs_GetPresentStatusReg(BaseAddress) \
+ XSdPs_In32((BaseAddress) + (XSDPS_PRES_STATE_OFFSET))
+
+/************************** Function Prototypes ******************************/
+
+/************************** Variable Definitions *****************************/
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* SD_HW_H_ */
+/** @} */
diff --git a/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/include/xstatus.h b/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/include/xstatus.h
new file mode 100644
index 0000000..9a6ed89
--- /dev/null
+++ b/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/include/xstatus.h
@@ -0,0 +1,533 @@
+/******************************************************************************
+*
+* Copyright (C) 2002 - 2019 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+* THE SOFTWARE.
+*
+*
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xstatus.h
+*
+* @addtogroup common_status_codes Xilinx® software status codes
+*
+* The xstatus.h file contains the Xilinx® software status codes.These codes are
+* used throughout the Xilinx device drivers.
+*
+* @{
+******************************************************************************/
+
+#ifndef XSTATUS_H /* prevent circular inclusions */
+#define XSTATUS_H /* by using protection macros */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/***************************** Include Files *********************************/
+
+#include "xil_types.h"
+#include "xil_assert.h"
+
+/************************** Constant Definitions *****************************/
+
+/*********************** Common statuses 0 - 500 *****************************/
+/**
+@name Common Status Codes for All Device Drivers
+@{
+*/
+#define XST_SUCCESS 0L
+#define XST_FAILURE 1L
+#define XST_DEVICE_NOT_FOUND 2L
+#define XST_DEVICE_BLOCK_NOT_FOUND 3L
+#define XST_INVALID_VERSION 4L
+#define XST_DEVICE_IS_STARTED 5L
+#define XST_DEVICE_IS_STOPPED 6L
+#define XST_FIFO_ERROR 7L /*!< An error occurred during an
+ operation with a FIFO such as
+ an underrun or overrun, this
+ error requires the device to
+ be reset */
+#define XST_RESET_ERROR 8L /*!< An error occurred which requires
+ the device to be reset */
+#define XST_DMA_ERROR 9L /*!< A DMA error occurred, this error
+ typically requires the device
+ using the DMA to be reset */
+#define XST_NOT_POLLED 10L /*!< The device is not configured for
+ polled mode operation */
+#define XST_FIFO_NO_ROOM 11L /*!< A FIFO did not have room to put
+ the specified data into */
+#define XST_BUFFER_TOO_SMALL 12L /*!< The buffer is not large enough
+ to hold the expected data */
+#define XST_NO_DATA 13L /*!< There was no data available */
+#define XST_REGISTER_ERROR 14L /*!< A register did not contain the
+ expected value */
+#define XST_INVALID_PARAM 15L /*!< An invalid parameter was passed
+ into the function */
+#define XST_NOT_SGDMA 16L /*!< The device is not configured for
+ scatter-gather DMA operation */
+#define XST_LOOPBACK_ERROR 17L /*!< A loopback test failed */
+#define XST_NO_CALLBACK 18L /*!< A callback has not yet been
+ registered */
+#define XST_NO_FEATURE 19L /*!< Device is not configured with
+ the requested feature */
+#define XST_NOT_INTERRUPT 20L /*!< Device is not configured for
+ interrupt mode operation */
+#define XST_DEVICE_BUSY 21L /*!< Device is busy */
+#define XST_ERROR_COUNT_MAX 22L /*!< The error counters of a device
+ have maxed out */
+#define XST_IS_STARTED 23L /*!< Used when part of device is
+ already started i.e.
+ sub channel */
+#define XST_IS_STOPPED 24L /*!< Used when part of device is
+ already stopped i.e.
+ sub channel */
+#define XST_DATA_LOST 26L /*!< Driver defined error */
+#define XST_RECV_ERROR 27L /*!< Generic receive error */
+#define XST_SEND_ERROR 28L /*!< Generic transmit error */
+#define XST_NOT_ENABLED 29L /*!< A requested service is not
+ available because it has not
+ been enabled */
+#define XST_NO_ACCESS 30L /* Generic access error */
+#define XST_TIMEOUT 31L /*!< Event timeout occurred */
+
+/** @} */
+/***************** Utility Component statuses 401 - 500 *********************/
+/**
+@name Utility Component Status Codes 401 - 500
+@{
+*/
+#define XST_MEMTEST_FAILED 401L /*!< Memory test failed */
+
+/** @} */
+/***************** Common Components statuses 501 - 1000 *********************/
+/**
+@name Packet Fifo Status Codes 501 - 510
+@{
+*/
+/********************* Packet Fifo statuses 501 - 510 ************************/
+
+#define XST_PFIFO_LACK_OF_DATA 501L /*!< Not enough data in FIFO */
+#define XST_PFIFO_NO_ROOM 502L /*!< Not enough room in FIFO */
+#define XST_PFIFO_BAD_REG_VALUE 503L /*!< Self test, a register value
+ was invalid after reset */
+#define XST_PFIFO_ERROR 504L /*!< Generic packet FIFO error */
+#define XST_PFIFO_DEADLOCK 505L /*!< Packet FIFO is reporting
+ * empty and full simultaneously
+ */
+/** @} */
+/**
+@name DMA Status Codes 511 - 530
+@{
+*/
+/************************** DMA statuses 511 - 530 ***************************/
+
+#define XST_DMA_TRANSFER_ERROR 511L /*!< Self test, DMA transfer
+ failed */
+#define XST_DMA_RESET_REGISTER_ERROR 512L /*!< Self test, a register value
+ was invalid after reset */
+#define XST_DMA_SG_LIST_EMPTY 513L /*!< Scatter gather list contains
+ no buffer descriptors ready
+ to be processed */
+#define XST_DMA_SG_IS_STARTED 514L /*!< Scatter gather not stopped */
+#define XST_DMA_SG_IS_STOPPED 515L /*!< Scatter gather not running */
+#define XST_DMA_SG_LIST_FULL 517L /*!< All the buffer descriptors of
+ the scatter gather list are
+ being used */
+#define XST_DMA_SG_BD_LOCKED 518L /*!< The scatter gather buffer
+ descriptor which is to be
+ copied over in the scatter
+ list is locked */
+#define XST_DMA_SG_NOTHING_TO_COMMIT 519L /*!< No buffer descriptors have been
+ put into the scatter gather
+ list to be committed */
+#define XST_DMA_SG_COUNT_EXCEEDED 521L /*!< The packet count threshold
+ specified was larger than the
+ total # of buffer descriptors
+ in the scatter gather list */
+#define XST_DMA_SG_LIST_EXISTS 522L /*!< The scatter gather list has
+ already been created */
+#define XST_DMA_SG_NO_LIST 523L /*!< No scatter gather list has
+ been created */
+#define XST_DMA_SG_BD_NOT_COMMITTED 524L /*!< The buffer descriptor which was
+ being started was not committed
+ to the list */
+#define XST_DMA_SG_NO_DATA 525L /*!< The buffer descriptor to start
+ has already been used by the
+ hardware so it can't be reused
+ */
+#define XST_DMA_SG_LIST_ERROR 526L /*!< General purpose list access
+ error */
+#define XST_DMA_BD_ERROR 527L /*!< General buffer descriptor
+ error */
+/** @} */
+/**
+@name IPIF Status Codes Codes 531 - 550
+@{
+*/
+/************************** IPIF statuses 531 - 550 ***************************/
+
+#define XST_IPIF_REG_WIDTH_ERROR 531L /*!< An invalid register width
+ was passed into the function */
+#define XST_IPIF_RESET_REGISTER_ERROR 532L /*!< The value of a register at
+ reset was not valid */
+#define XST_IPIF_DEVICE_STATUS_ERROR 533L /*!< A write to the device interrupt
+ status register did not read
+ back correctly */
+#define XST_IPIF_DEVICE_ACK_ERROR 534L /*!< The device interrupt status
+ register did not reset when
+ acked */
+#define XST_IPIF_DEVICE_ENABLE_ERROR 535L /*!< The device interrupt enable
+ register was not updated when
+ other registers changed */
+#define XST_IPIF_IP_STATUS_ERROR 536L /*!< A write to the IP interrupt
+ status register did not read
+ back correctly */
+#define XST_IPIF_IP_ACK_ERROR 537L /*!< The IP interrupt status register
+ did not reset when acked */
+#define XST_IPIF_IP_ENABLE_ERROR 538L /*!< IP interrupt enable register was
+ not updated correctly when other
+ registers changed */
+#define XST_IPIF_DEVICE_PENDING_ERROR 539L /*!< The device interrupt pending
+ register did not indicate the
+ expected value */
+#define XST_IPIF_DEVICE_ID_ERROR 540L /*!< The device interrupt ID register
+ did not indicate the expected
+ value */
+#define XST_IPIF_ERROR 541L /*!< Generic ipif error */
+/** @} */
+
+/****************** Device specific statuses 1001 - 4095 *********************/
+/**
+@name Ethernet Status Codes 1001 - 1050
+@{
+*/
+/********************* Ethernet statuses 1001 - 1050 *************************/
+
+#define XST_EMAC_MEMORY_SIZE_ERROR 1001L /*!< Memory space is not big enough
+ * to hold the minimum number of
+ * buffers or descriptors */
+#define XST_EMAC_MEMORY_ALLOC_ERROR 1002L /*!< Memory allocation failed */
+#define XST_EMAC_MII_READ_ERROR 1003L /*!< MII read error */
+#define XST_EMAC_MII_BUSY 1004L /*!< An MII operation is in progress */
+#define XST_EMAC_OUT_OF_BUFFERS 1005L /*!< Driver is out of buffers */
+#define XST_EMAC_PARSE_ERROR 1006L /*!< Invalid driver init string */
+#define XST_EMAC_COLLISION_ERROR 1007L /*!< Excess deferral or late
+ * collision on polled send */
+/** @} */
+/**
+@name UART Status Codes 1051 - 1075
+@{
+*/
+/*********************** UART statuses 1051 - 1075 ***************************/
+#define XST_UART
+
+#define XST_UART_INIT_ERROR 1051L
+#define XST_UART_START_ERROR 1052L
+#define XST_UART_CONFIG_ERROR 1053L
+#define XST_UART_TEST_FAIL 1054L
+#define XST_UART_BAUD_ERROR 1055L
+#define XST_UART_BAUD_RANGE 1056L
+
+/** @} */
+/**
+@name IIC Status Codes 1076 - 1100
+@{
+*/
+/************************ IIC statuses 1076 - 1100 ***************************/
+
+#define XST_IIC_SELFTEST_FAILED 1076 /*!< self test failed */
+#define XST_IIC_BUS_BUSY 1077 /*!< bus found busy */
+#define XST_IIC_GENERAL_CALL_ADDRESS 1078 /*!< mastersend attempted with */
+ /* general call address */
+#define XST_IIC_STAND_REG_RESET_ERROR 1079 /*!< A non parameterizable reg */
+ /* value after reset not valid */
+#define XST_IIC_TX_FIFO_REG_RESET_ERROR 1080 /*!< Tx fifo included in design */
+ /* value after reset not valid */
+#define XST_IIC_RX_FIFO_REG_RESET_ERROR 1081 /*!< Rx fifo included in design */
+ /* value after reset not valid */
+#define XST_IIC_TBA_REG_RESET_ERROR 1082 /*!< 10 bit addr incl in design */
+ /* value after reset not valid */
+#define XST_IIC_CR_READBACK_ERROR 1083 /*!< Read of the control register */
+ /* didn't return value written */
+#define XST_IIC_DTR_READBACK_ERROR 1084 /*!< Read of the data Tx reg */
+ /* didn't return value written */
+#define XST_IIC_DRR_READBACK_ERROR 1085 /*!< Read of the data Receive reg */
+ /* didn't return value written */
+#define XST_IIC_ADR_READBACK_ERROR 1086 /*!< Read of the data Tx reg */
+ /* didn't return value written */
+#define XST_IIC_TBA_READBACK_ERROR 1087 /*!< Read of the 10 bit addr reg */
+ /* didn't return written value */
+#define XST_IIC_NOT_SLAVE 1088 /*!< The device isn't a slave */
+#define XST_IIC_ARB_LOST 1089 /*!< Arbitration lost for master */
+/** @} */
+/**
+@name ATMC Status Codes 1101 - 1125
+@{
+*/
+/*********************** ATMC statuses 1101 - 1125 ***************************/
+
+#define XST_ATMC_ERROR_COUNT_MAX 1101L /*!< the error counters in the ATM
+ controller hit the max value
+ which requires the statistics
+ to be cleared */
+/** @} */
+/**
+@name Flash Status Codes 1126 - 1150
+@{
+*/
+/*********************** Flash statuses 1126 - 1150 **************************/
+
+#define XST_FLASH_BUSY 1126L /*!< Flash is erasing or programming
+ */
+#define XST_FLASH_READY 1127L /*!< Flash is ready for commands */
+#define XST_FLASH_ERROR 1128L /*!< Flash had detected an internal
+ error. Use XFlash_DeviceControl
+ to retrieve device specific codes
+ */
+#define XST_FLASH_ERASE_SUSPENDED 1129L /*!< Flash is in suspended erase state
+ */
+#define XST_FLASH_WRITE_SUSPENDED 1130L /*!< Flash is in suspended write state
+ */
+#define XST_FLASH_PART_NOT_SUPPORTED 1131L /*!< Flash type not supported by
+ driver */
+#define XST_FLASH_NOT_SUPPORTED 1132L /*!< Operation not supported */
+#define XST_FLASH_TOO_MANY_REGIONS 1133L /*!< Too many erase regions */
+#define XST_FLASH_TIMEOUT_ERROR 1134L /*!< Programming or erase operation
+ aborted due to a timeout */
+#define XST_FLASH_ADDRESS_ERROR 1135L /*!< Accessed flash outside its
+ addressible range */
+#define XST_FLASH_ALIGNMENT_ERROR 1136L /*!< Write alignment error */
+#define XST_FLASH_BLOCKING_CALL_ERROR 1137L /*!< Couldn't return immediately from
+ write/erase function with
+ XFL_NON_BLOCKING_WRITE/ERASE
+ option cleared */
+#define XST_FLASH_CFI_QUERY_ERROR 1138L /*!< Failed to query the device */
+/** @} */
+/**
+@name SPI Status Codes 1151 - 1175
+@{
+*/
+/*********************** SPI statuses 1151 - 1175 ****************************/
+
+#define XST_SPI_MODE_FAULT 1151 /*!< master was selected as slave */
+#define XST_SPI_TRANSFER_DONE 1152 /*!< data transfer is complete */
+#define XST_SPI_TRANSMIT_UNDERRUN 1153 /*!< slave underruns transmit register */
+#define XST_SPI_RECEIVE_OVERRUN 1154 /*!< device overruns receive register */
+#define XST_SPI_NO_SLAVE 1155 /*!< no slave has been selected yet */
+#define XST_SPI_TOO_MANY_SLAVES 1156 /*!< more than one slave is being
+ * selected */
+#define XST_SPI_NOT_MASTER 1157 /*!< operation is valid only as master */
+#define XST_SPI_SLAVE_ONLY 1158 /*!< device is configured as slave-only
+ */
+#define XST_SPI_SLAVE_MODE_FAULT 1159 /*!< slave was selected while disabled */
+#define XST_SPI_SLAVE_MODE 1160 /*!< device has been addressed as slave */
+#define XST_SPI_RECEIVE_NOT_EMPTY 1161 /*!< device received data in slave mode */
+
+#define XST_SPI_COMMAND_ERROR 1162 /*!< unrecognised command - qspi only */
+#define XST_SPI_POLL_DONE 1163 /*!< controller completed polling the
+ device for status */
+/** @} */
+/**
+@name OPB Arbiter Status Codes 1176 - 1200
+@{
+*/
+/********************** OPB Arbiter statuses 1176 - 1200 *********************/
+
+#define XST_OPBARB_INVALID_PRIORITY 1176 /*!< the priority registers have either
+ * one master assigned to two or more
+ * priorities, or one master not
+ * assigned to any priority
+ */
+#define XST_OPBARB_NOT_SUSPENDED 1177 /*!< an attempt was made to modify the
+ * priority levels without first
+ * suspending the use of priority
+ * levels
+ */
+#define XST_OPBARB_PARK_NOT_ENABLED 1178 /*!< bus parking by id was enabled but
+ * bus parking was not enabled
+ */
+#define XST_OPBARB_NOT_FIXED_PRIORITY 1179 /*!< the arbiter must be in fixed
+ * priority mode to allow the
+ * priorities to be changed
+ */
+/** @} */
+/**
+@name INTC Status Codes 1201 - 1225
+@{
+*/
+/************************ Intc statuses 1201 - 1225 **************************/
+
+#define XST_INTC_FAIL_SELFTEST 1201 /*!< self test failed */
+#define XST_INTC_CONNECT_ERROR 1202 /*!< interrupt already in use */
+/** @} */
+/**
+@name TmrCtr Status Codes 1226 - 1250
+@{
+*/
+/********************** TmrCtr statuses 1226 - 1250 **************************/
+
+#define XST_TMRCTR_TIMER_FAILED 1226 /*!< self test failed */
+/** @} */
+/**
+@name WdtTb Status Codes 1251 - 1275
+@{
+*/
+/********************** WdtTb statuses 1251 - 1275 ***************************/
+
+#define XST_WDTTB_TIMER_FAILED 1251L
+/** @} */
+/**
+@name PlbArb status Codes 1276 - 1300
+@{
+*/
+/********************** PlbArb statuses 1276 - 1300 **************************/
+
+#define XST_PLBARB_FAIL_SELFTEST 1276L
+/** @} */
+/**
+@name Plb2Opb Status Codes 1301 - 1325
+@{
+*/
+/********************** Plb2Opb statuses 1301 - 1325 *************************/
+
+#define XST_PLB2OPB_FAIL_SELFTEST 1301L
+/** @} */
+/**
+@name Opb2Plb Status 1326 - 1350
+@{
+*/
+/********************** Opb2Plb statuses 1326 - 1350 *************************/
+
+#define XST_OPB2PLB_FAIL_SELFTEST 1326L
+/** @} */
+/**
+@name SysAce Status Codes 1351 - 1360
+@{
+*/
+/********************** SysAce statuses 1351 - 1360 **************************/
+
+#define XST_SYSACE_NO_LOCK 1351L /*!< No MPU lock has been granted */
+/** @} */
+/**
+@name PCI Bridge Status Codes 1361 - 1375
+@{
+*/
+/********************** PCI Bridge statuses 1361 - 1375 **********************/
+
+#define XST_PCI_INVALID_ADDRESS 1361L
+/** @} */
+/**
+@name FlexRay Constants 1400 - 1409
+@{
+*/
+/********************** FlexRay constants 1400 - 1409 *************************/
+
+#define XST_FR_TX_ERROR 1400
+#define XST_FR_TX_BUSY 1401
+#define XST_FR_BUF_LOCKED 1402
+#define XST_FR_NO_BUF 1403
+/** @} */
+/**
+@name USB constants 1410 - 1420
+@{
+*/
+/****************** USB constants 1410 - 1420 *******************************/
+
+#define XST_USB_ALREADY_CONFIGURED 1410
+#define XST_USB_BUF_ALIGN_ERROR 1411
+#define XST_USB_NO_DESC_AVAILABLE 1412
+#define XST_USB_BUF_TOO_BIG 1413
+#define XST_USB_NO_BUF 1414
+/** @} */
+/**
+@name HWICAP constants 1421 - 1429
+@{
+*/
+/****************** HWICAP constants 1421 - 1429 *****************************/
+
+#define XST_HWICAP_WRITE_DONE 1421
+
+/** @} */
+/**
+@name AXI VDMA constants 1430 - 1440
+@{
+*/
+/****************** AXI VDMA constants 1430 - 1440 *****************************/
+
+#define XST_VDMA_MISMATCH_ERROR 1430
+/** @} */
+/**
+@name NAND Flash Status Codes 1441 - 1459
+@{
+*/
+/*********************** NAND Flash statuses 1441 - 1459 *********************/
+
+#define XST_NAND_BUSY 1441L /*!< Flash is erasing or
+ * programming
+ */
+#define XST_NAND_READY 1442L /*!< Flash is ready for commands
+ */
+#define XST_NAND_ERROR 1443L /*!< Flash had detected an
+ * internal error.
+ */
+#define XST_NAND_PART_NOT_SUPPORTED 1444L /*!< Flash type not supported by
+ * driver
+ */
+#define XST_NAND_OPT_NOT_SUPPORTED 1445L /*!< Operation not supported
+ */
+#define XST_NAND_TIMEOUT_ERROR 1446L /*!< Programming or erase
+ * operation aborted due to a
+ * timeout
+ */
+#define XST_NAND_ADDRESS_ERROR 1447L /*!< Accessed flash outside its
+ * addressible range
+ */
+#define XST_NAND_ALIGNMENT_ERROR 1448L /*!< Write alignment error
+ */
+#define XST_NAND_PARAM_PAGE_ERROR 1449L /*!< Failed to read parameter
+ * page of the device
+ */
+#define XST_NAND_CACHE_ERROR 1450L /*!< Flash page buffer error
+ */
+
+#define XST_NAND_WRITE_PROTECTED 1451L /*!< Flash is write protected
+ */
+/** @} */
+
+/**************************** Type Definitions *******************************/
+
+typedef s32 XStatus;
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+
+/************************** Function Prototypes ******************************/
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* end of protection macro */
+/**
+* @} End of "addtogroup common_status_codes".
+*/
diff --git a/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/include/xtime_l.h b/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/include/xtime_l.h
new file mode 100644
index 0000000..8392419
--- /dev/null
+++ b/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/include/xtime_l.h
@@ -0,0 +1,102 @@
+/******************************************************************************
+*
+* Copyright (C) 2009 - 2018 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+* THE SOFTWARE.
+*
+*
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+* @file xtime_l.h
+* @addtogroup a9_time_apis Cortex A9 Time Functions
+*
+* xtime_l.h provides access to the 64-bit Global Counter in the PMU. This
+* counter increases by one at every two processor cycles. These functions can
+* be used to get/set time in the global timer.
+*
+* @{
+* <pre>
+* MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ----- ------ -------- ---------------------------------------------------
+* 1.00a rp/sdm 11/03/09 Initial release.
+* 3.06a sgd 05/15/12 Updated get/set time functions to make use Global Timer
+* 3.06a asa 06/17/12 Reverted back the changes to make use Global Timer.
+* 3.07a sgd 07/05/12 Updated get/set time functions to make use Global Timer
+* 6.6 srm 10/23/17 Updated the macros to support user configurable sleep
+* implementation
+* 6.8 aru 09/06/18 Removed compilation warnings for ARMCC toolchain.
+* </pre>
+*
+******************************************************************************/
+
+#ifndef XTIME_H /* prevent circular inclusions */
+#define XTIME_H /* by using protection macros */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/***************************** Include Files *********************************/
+
+#include "xil_types.h"
+#include "xparameters.h"
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/**************************** Type Definitions *******************************/
+
+typedef u64 XTime;
+
+/************************** Constant Definitions *****************************/
+#define GLOBAL_TMR_BASEADDR XPAR_GLOBAL_TMR_BASEADDR
+#define GTIMER_COUNTER_LOWER_OFFSET 0x00U
+#define GTIMER_COUNTER_UPPER_OFFSET 0x04U
+#define GTIMER_CONTROL_OFFSET 0x08U
+
+#if defined (SLEEP_TIMER_BASEADDR)
+#define COUNTS_PER_SECOND (SLEEP_TIMER_FREQUENCY)
+#else
+/* Global Timer is always clocked at half of the CPU frequency */
+#define COUNTS_PER_SECOND (XPAR_CPU_CORTEXA9_CORE_CLOCK_FREQ_HZ /2)
+#endif
+
+#if defined (XSLEEP_TIMER_IS_DEFAULT_TIMER)
+#ifdef __GNUC__
+#pragma message ("For the sleep routines, Global timer is being used")
+#endif
+#endif
+/************************** Variable Definitions *****************************/
+
+/************************** Function Prototypes ******************************/
+
+void XTime_SetTime(XTime Xtime_Global);
+void XTime_GetTime(XTime *Xtime_Global);
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+
+#endif /* XTIME_H */
+/**
+* @} End of "addtogroup a9_time_apis".
+*/
diff --git a/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/include/xttcps.h b/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/include/xttcps.h
new file mode 100644
index 0000000..67969ba
--- /dev/null
+++ b/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/include/xttcps.h
@@ -0,0 +1,536 @@
+/******************************************************************************
+*
+* Copyright (C) 2010 - 2019 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+* THE SOFTWARE.
+*
+*
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xttcps.h
+* @addtogroup ttcps_v3_10
+* @{
+* @details
+*
+* This is the driver for one 16-bit timer counter in the Triple Timer Counter
+* (TTC) module in the Ps block.
+*
+* The TTC module provides three independent timer/counter modules that can each
+* be clocked using either the system clock (pclk) or an externally driven
+* clock (ext_clk). In addition, each counter can independently prescale its
+* selected clock input (divided by 2 to 65536). Counters can be set to
+* decrement or increment.
+*
+* Each of the counters can be programmed to generate interrupt pulses:
+* . At a regular, predefined period, that is on a timed interval
+* . When the counter registers overflow
+* . When the count matches any one of the three 'match' registers
+*
+* Therefore, up to six different events can trigger a timer interrupt: three
+* match interrupts, an overflow interrupt, an interval interrupt and an event
+* timer interrupt. Note that the overflow interrupt and the interval interrupt
+* are mutually exclusive.
+*
+* <b>Initialization & Configuration</b>
+*
+* An XTtcPs_Config structure is used to configure a driver instance.
+* Information in the XTtcPs_Config structure is the hardware properties
+* about the device.
+*
+* A driver instance is initialized through
+* XTtcPs_CfgInitialize(InstancePtr, CfgPtr, EffectiveAddr). Where CfgPtr
+* is a pointer to the XTtcPs_Config structure, it can be looked up statically
+* through XTtcPs_LookupConfig(DeviceID), or passed in by the caller. The
+* EffectiveAddr can be the static base address of the device or virtual
+* mapped address if address translation is supported.
+*
+* <b>Interrupts</b>
+*
+* Interrupt handler is not provided by the driver, as handling of interrupt
+* is application specific.
+*
+* <b>stack usage(in bytes)</b>
+*
+* XTtcPs_LookupConfig : 32
+* XTtcPs_CfgInitialize : 80
+* XTtcPs_SetMatchValue : 32
+* XTtcPs_GetMatchValue : 48
+* XTtcPs_SetPrescaler : 48
+* XTtcPs_GetPrescaler : 48
+* XTtcPs_CalcIntervalFromFreq : 48
+* XTtcPs_SetOptions : 48
+* XTtcPs_GetOptions : 48
+* XTtcPs_SelfTest : 48
+* XTtcPs_InterruptHandler : 48
+* XTtcPs_SetStatusHandler : 48
+*
+* <b>Memory foot-print(in bytes)</b>
+*
+* XTtcPs_LookupConfig : 72
+* XTtcPs_CfgInitialize : 304
+* XTtcPs_SetMatchValue : 168
+* XTtcPs_GetMatchValue : 176
+* XTtcPs_SetPrescaler : 172
+* XTtcPs_GetPrescaler : 152
+* XTtcPs_CalcIntervalFromFreq : 228
+* XTtcPs_SetOptions : 424
+* XTtcPs_GetOptions : 200
+* XTtcPs_SelfTest : 148
+* XTtcPs_InterruptHandler : 88
+* XTtcPs_SetStatusHandler : 140
+*
+* <b>Execution Time(in usec)</b>
+*
+* XTtcPs_LookupConfig : 8.31
+* TtcPs_CfgInitialize : 1.30
+* XTtcPs_SetMatchValue : 1.10
+* XTtcPs_GetMatchValue : 1.00
+* XTtcPs_SetPrescaler : 1.09
+* XTtcPs_GetPrescaler : 1.00
+* XTtcPs_CalcIntervalFromFreq : 1.29
+* XTtcPs_SetOptions: 1.91
+* XTtcPs_GetOptions: 2.55
+* XTtcPs_SelfTest: .85
+*
+* <b>Assumptions of Use</b>
+
+* 1.The default setting for a timer/counter is:
+* - Overflow Mode
+* - Internal clock (pclk) selected
+* - Counter disabled
+* - All Interrupts disabled
+* - Output waveforms disabled
+*
+* <b>Compiler Name</b>
+*
+* gcc
+*
+* <b>Compiler version</b>
+*
+* 8.2.0
+*
+* <b>Compiler options</b>
+*
+* -DARMR5 -Wall -O0 -g3 -c -fmessage-length=0 -MT"$@" -mcpu=cortex-r5 -mfloat-abi=hard -mfpu=vfpv3-d16 -I<include_path>
+* -Wall -O0 -g3 -c -fmessage-length=0 -MT"$@" -mcpu=cortex-a72 -I<include_path>
+* -Wall -O0 -g3 -c -fmessage-length=0 -MT"$@" -I<include_path>
+*
+* <b>User Defined data types</b>
+*
+* u8 1 byte
+* u16 2 bytes
+* u32 4 bytes / 1 word
+* u64 8 bytes / double word
+*
+*
+* <pre>
+* MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ----- ------ -------- -----------------------------------------------------
+* 1.00a drg/jz 01/20/10 First release..
+* 2.0 adk 12/10/13 Updated as per the New Tcl API's
+* 3.0 pkp 12/09/14 Added support for Zynq Ultrascale Mp.Also code
+* modified for MISRA-C:2012 compliance.
+* 3.2 mus 10/28/16 Modified XTtcPs_GetCounterValue and XTtcPs_SetInterval
+* macros to return 32 bit values for zynq ultrascale+mpsoc
+* ms 01/23/17 Modified xil_printf statement in main function for all
+* examples to ensure that "Successfully ran" and "Failed"
+* strings are available in all examples. This is a fix
+* for CR-965028.
+* ms 03/17/17 Added readme.txt file in examples folder for doxygen
+* generation.
+* 3.4 ms 04/18/17 Modified tcl file to add suffix U for all macros
+* definitions of ttcps in xparameters.h
+* 3.5 srm 10/06/17 Added new typedef XMatchRegValue for match register width
+* 3.8 aru 12/19/18 Modified in XTtcPs_ClearInterruptStatus function to clear
+* Interrupt status register by reading instead of writing it.
+* </pre>
+*
+******************************************************************************/
+
+#ifndef XTTCPS_H /* prevent circular inclusions */
+#define XTTCPS_H /* by using protection macros */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/***************************** Include Files *********************************/
+
+#include "xttcps_hw.h"
+#include "xstatus.h"
+
+/*****************************************************************************/
+typedef void (*XTtcPs_StatusHandler) (const void *CallBackRef, u32 StatusEvent);
+
+
+/************************** Constant Definitions *****************************/
+
+
+/*
+ * Maximum Value for interval counter
+ */
+ #if defined(ARMA9)
+ #define XTTCPS_MAX_INTERVAL_COUNT 0xFFFFU
+ #else
+ #define XTTCPS_MAX_INTERVAL_COUNT 0xFFFFFFFFU
+ #endif
+
+/** @name Configuration options
+ *
+ * Options for the device. Each of the options is bit field, so more than one
+ * options can be specified.
+ *
+ * @{
+ */
+#define XTTCPS_OPTION_EXTERNAL_CLK 0x00000001U /**< External clock source */
+#define XTTCPS_OPTION_CLK_EDGE_NEG 0x00000002U /**< Clock on trailing edge for
+ external clock*/
+#define XTTCPS_OPTION_INTERVAL_MODE 0x00000004U /**< Interval mode */
+#define XTTCPS_OPTION_DECREMENT 0x00000008U /**< Decrement the counter */
+#define XTTCPS_OPTION_MATCH_MODE 0x00000010U /**< Match mode */
+#define XTTCPS_OPTION_WAVE_DISABLE 0x00000020U /**< No waveform output */
+#define XTTCPS_OPTION_WAVE_POLARITY 0x00000040U /**< Waveform polarity */
+/*@}*/
+/**************************** Type Definitions *******************************/
+
+/**
+ * This typedef contains configuration information for the device.
+ */
+typedef struct {
+ u16 DeviceId; /**< Unique ID for device */
+ u32 BaseAddress; /**< Base address for device */
+ u32 InputClockHz; /**< Input clock frequency */
+} XTtcPs_Config;
+
+/**
+ * The XTtcPs driver instance data. The user is required to allocate a
+ * variable of this type for each PS timer/counter device in the system. A
+ * pointer to a variable of this type is then passed to various driver API
+ * functions.
+ */
+typedef struct {
+ XTtcPs_Config Config; /**< Configuration structure */
+ u32 IsReady; /**< Device is initialized and ready */
+ XTtcPs_StatusHandler StatusHandler;
+ void *StatusRef; /**< Callback reference for status handler */
+} XTtcPs;
+
+/**
+ * This typedef contains interval count and Match register value
+ */
+#if defined(ARMA9)
+typedef u16 XInterval;
+typedef u16 XMatchRegValue;
+#else
+typedef u32 XInterval;
+typedef u32 XMatchRegValue;
+#endif
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/*
+ * Internal helper macros
+ */
+#define InstReadReg(InstancePtr, RegOffset) \
+ (Xil_In32(((InstancePtr)->Config.BaseAddress) + (u32)(RegOffset)))
+
+#define InstWriteReg(InstancePtr, RegOffset, Data) \
+ (Xil_Out32(((InstancePtr)->Config.BaseAddress) + (u32)(RegOffset), (u32)(Data)))
+
+/*****************************************************************************/
+/**
+*
+* This function starts the counter/timer without resetting the counter value.
+*
+* @param InstancePtr is a pointer to the XTtcPs instance.
+*
+* @return None
+*
+* @note C-style signature:
+* void XTtcPs_Start(XTtcPs *InstancePtr)
+*
+****************************************************************************/
+#define XTtcPs_Start(InstancePtr) \
+ InstWriteReg((InstancePtr), XTTCPS_CNT_CNTRL_OFFSET, \
+ (InstReadReg((InstancePtr), XTTCPS_CNT_CNTRL_OFFSET) & \
+ ~XTTCPS_CNT_CNTRL_DIS_MASK))
+
+/*****************************************************************************/
+/**
+*
+* This function stops the counter/timer. This macro may be called at any time
+* to stop the counter. The counter holds the last value until it is reset,
+* restarted or enabled.
+*
+* @param InstancePtr is a pointer to the XTtcPs instance.
+*
+* @return None
+*
+* @note C-style signature:
+* void XTtcPs_Stop(XTtcPs *InstancePtr)
+*
+****************************************************************************/
+#define XTtcPs_Stop(InstancePtr) \
+ InstWriteReg((InstancePtr), XTTCPS_CNT_CNTRL_OFFSET, \
+ (InstReadReg((InstancePtr), XTTCPS_CNT_CNTRL_OFFSET) | \
+ XTTCPS_CNT_CNTRL_DIS_MASK))
+
+/*****************************************************************************/
+/**
+*
+* This function checks whether the timer counter has already started.
+*
+* @param InstancePtr is a pointer to the XTtcPs instance
+*
+* @return Non-zero if the device has started, '0' otherwise.
+*
+* @note C-style signature:
+* int XTtcPs_IsStarted(XTtcPs *InstancePtr)
+*
+****************************************************************************/
+#define XTtcPs_IsStarted(InstancePtr) \
+ ((InstReadReg((InstancePtr), XTTCPS_CNT_CNTRL_OFFSET) & \
+ XTTCPS_CNT_CNTRL_DIS_MASK) == 0U)
+
+/*****************************************************************************/
+/**
+*
+* This function returns the current 16-bit counter value. It may be called at
+* any time.
+*
+* @param InstancePtr is a pointer to the XTtcPs instance.
+*
+* @return zynq:16 bit counter value.
+* zynq ultrascale+mpsoc:32 bit counter value.
+*
+* @note C-style signature:
+* zynq: u16 XTtcPs_GetCounterValue(XTtcPs *InstancePtr)
+* zynq ultrascale+mpsoc: u32 XTtcPs_GetCounterValue(XTtcPs *InstancePtr)
+*
+****************************************************************************/
+#if defined(ARMA9)
+/*
+ * ttc supports 16 bit counter for zynq
+ */
+#define XTtcPs_GetCounterValue(InstancePtr) \
+ (u16)InstReadReg((InstancePtr), XTTCPS_COUNT_VALUE_OFFSET)
+#else
+/*
+ * ttc supports 32 bit counter for zynq ultrascale+mpsoc
+ */
+#define XTtcPs_GetCounterValue(InstancePtr) \
+ InstReadReg((InstancePtr), XTTCPS_COUNT_VALUE_OFFSET)
+#endif
+
+/*****************************************************************************/
+/**
+*
+* This function sets the interval value to be used in interval mode.
+*
+* @param InstancePtr is a pointer to the XTtcPs instance.
+* @param Value is the 16-bit value to be set in the interval register.
+*
+* @return None
+*
+* @note C-style signature:
+* void XTtcPs_SetInterval(XTtcPs *InstancePtr, XInterval Value)
+*
+****************************************************************************/
+#define XTtcPs_SetInterval(InstancePtr, Value) \
+ InstWriteReg((InstancePtr), XTTCPS_INTERVAL_VAL_OFFSET, (Value))
+
+/*****************************************************************************/
+/**
+*
+* This function gets the interval value from the interval register.
+*
+* @param InstancePtr is a pointer to the XTtcPs instance.
+*
+* @return zynq:16 bit interval value.
+* zynq ultrascale+mpsoc:32 bit interval value.
+*
+* @note C-style signature:
+* zynq: u16 XTtcPs_GetInterval(XTtcPs *InstancePtr)
+* zynq ultrascale+mpsoc: u32 XTtcPs_GetInterval(XTtcPs *InstancePtr)
+*
+****************************************************************************/
+#if defined(ARMA9)
+/*
+ * ttc supports 16 bit interval counter for zynq
+ */
+#define XTtcPs_GetInterval(InstancePtr) \
+ (u16)InstReadReg((InstancePtr), XTTCPS_INTERVAL_VAL_OFFSET)
+#else
+/*
+ * ttc supports 32 bit interval counter for zynq ultrascale+mpsoc
+ */
+#define XTtcPs_GetInterval(InstancePtr) \
+ InstReadReg((InstancePtr), XTTCPS_INTERVAL_VAL_OFFSET)
+#endif
+/*****************************************************************************/
+/**
+*
+* This macro resets the count register. It may be called at any time. The
+* counter is reset to either 0 or 0xFFFF, or the interval value, depending on
+* the increment/decrement mode. The state of the counter, as started or
+* stopped, is not affected by calling reset.
+*
+* @param InstancePtr is a pointer to the XTtcPs instance.
+*
+* @return None
+*
+* @note C-style signature:
+* void XTtcPs_ResetCounterValue(XTtcPs *InstancePtr)
+*
+****************************************************************************/
+#define XTtcPs_ResetCounterValue(InstancePtr) \
+ InstWriteReg((InstancePtr), XTTCPS_CNT_CNTRL_OFFSET, \
+ (InstReadReg((InstancePtr), XTTCPS_CNT_CNTRL_OFFSET) | \
+ (u32)XTTCPS_CNT_CNTRL_RST_MASK))
+
+/*****************************************************************************/
+/**
+*
+* This function enables the interrupts.
+*
+* @param InstancePtr is a pointer to the XTtcPs instance.
+* @param InterruptMask defines which interrupt should be enabled.
+* Constants are defined in xttcps_hw.h as XTTCPS_IXR_*.
+* This is a bit mask, all set bits will be enabled, cleared bits
+* will not be disabled.
+*
+* @return None.
+*
+* @note
+* C-style signature:
+* void XTtcPs_EnableInterrupts(XTtcPs *InstancePtr, u32 InterruptMask)
+*
+******************************************************************************/
+#define XTtcPs_EnableInterrupts(InstancePtr, InterruptMask) \
+ InstWriteReg((InstancePtr), XTTCPS_IER_OFFSET, \
+ (InstReadReg((InstancePtr), XTTCPS_IER_OFFSET) | \
+ (InterruptMask)))
+
+/*****************************************************************************/
+/**
+*
+* This function disables the interrupts.
+*
+* @param InstancePtr is a pointer to the XTtcPs instance.
+* @param InterruptMask defines which interrupt should be disabled.
+* Constants are defined in xttcps_hw.h as XTTCPS_IXR_*.
+* This is a bit mask, all set bits will be disabled, cleared bits
+* will not be disabled.
+*
+* @return None.
+*
+* @note
+* C-style signature:
+* void XTtcPs_DisableInterrupts(XTtcPs *InstancePtr, u32 InterruptMask)
+*
+******************************************************************************/
+#define XTtcPs_DisableInterrupts(InstancePtr, InterruptMask) \
+ InstWriteReg((InstancePtr), XTTCPS_IER_OFFSET, \
+ (InstReadReg((InstancePtr), XTTCPS_IER_OFFSET) & \
+ ~(InterruptMask)))
+
+/*****************************************************************************/
+/**
+*
+* This function reads the interrupt status.
+*
+* @param InstancePtr is a pointer to the XTtcPs instance.
+*
+* @return None.
+*
+* @note C-style signature:
+* u32 XTtcPs_GetInterruptStatus(XTtcPs *InstancePtr)
+*
+******************************************************************************/
+#define XTtcPs_GetInterruptStatus(InstancePtr) \
+ InstReadReg((InstancePtr), XTTCPS_ISR_OFFSET)
+
+/*****************************************************************************/
+/**
+*
+* This function clears the interrupt status.
+*
+* @param InstancePtr is a pointer to the XTtcPs instance.
+* @param InterruptMask defines which interrupt should be cleared.
+* Constants are defined in xttcps_hw.h as XTTCPS_IXR_*.
+* This is a bit mask, all set bits will be cleared, cleared bits
+* will not be cleared.
+*
+* @return None.
+*
+* @note
+* C-style signature:
+* void XTtcPs_ClearInterruptStatus(XTtcPs *InstancePtr, u32 InterruptMask)
+*
+******************************************************************************/
+#define XTtcPs_ClearInterruptStatus(InstancePtr, InterruptMask) \
+ InstReadReg((InstancePtr), XTTCPS_ISR_OFFSET)
+
+
+/************************** Function Prototypes ******************************/
+
+/*
+ * Initialization functions in xttcps_sinit.c
+ */
+XTtcPs_Config *XTtcPs_LookupConfig(u16 DeviceId);
+
+/*
+ * Required functions, in xttcps.c
+ */
+s32 XTtcPs_CfgInitialize(XTtcPs *InstancePtr,
+ XTtcPs_Config * ConfigPtr, u32 EffectiveAddr);
+
+void XTtcPs_SetMatchValue(XTtcPs *InstancePtr, u8 MatchIndex, XMatchRegValue Value);
+XMatchRegValue XTtcPs_GetMatchValue(XTtcPs *InstancePtr, u8 MatchIndex);
+
+void XTtcPs_SetPrescaler(XTtcPs *InstancePtr, u8 PrescalerValue);
+u8 XTtcPs_GetPrescaler(XTtcPs *InstancePtr);
+
+void XTtcPs_CalcIntervalFromFreq(XTtcPs *InstancePtr, u32 Freq,
+ XInterval *Interval, u8 *Prescaler);
+
+/*
+ * Functions for options, in file xttcps_options.c
+ */
+s32 XTtcPs_SetOptions(XTtcPs *InstancePtr, u32 Options);
+u32 XTtcPs_GetOptions(XTtcPs *InstancePtr);
+
+/*
+ * Function for self-test, in file xttcps_selftest.c
+ */
+s32 XTtcPs_SelfTest(XTtcPs *InstancePtr);
+u32 XTtcPs_InterruptHandler(XTtcPs *InstancePtr);
+void XTtcPs_SetStatusHandler(XTtcPs *InstancePtr, void *CallBackRef,
+ XTtcPs_StatusHandler FuncPointer);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* end of protection macro */
+/** @} */
diff --git a/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/include/xttcps_hw.h b/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/include/xttcps_hw.h
new file mode 100644
index 0000000..f07527d
--- /dev/null
+++ b/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/include/xttcps_hw.h
@@ -0,0 +1,227 @@
+/******************************************************************************
+*
+* Copyright (C) 2010 - 2019 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+* THE SOFTWARE.
+*
+*
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xttcps_hw.h
+* @addtogroup ttcps_v3_10
+* @{
+*
+* This file defines the hardware interface to one of the three timer counters
+* in the Ps block.
+*
+*
+* <pre>
+* MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ----- ------ -------- -------------------------------------------------
+* 1.00a drg/jz 01/21/10 First release
+* 3.00 kvn 02/13/15 Modified code for MISRA-C:2012 compliance.
+* 3.5 srm 10/06/17 Updated XTTCPS_COUNT_VALUE_MASK,
+* XTTCPS_INTERVAL_VAL_MASK, XTTCPS_MATCH_MASK macros to
+* mask 16 bit values for zynq and 32 bit values for
+* zynq ultrascale+mpsoc "
+* </pre>
+*
+******************************************************************************/
+
+#ifndef XTTCPS_HW_H /* prevent circular inclusions */
+#define XTTCPS_HW_H /* by using protection macros */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/***************************** Include Files *********************************/
+
+#include "xil_types.h"
+#include "xil_assert.h"
+#include "xil_io.h"
+
+/************************** Constant Definitions *****************************/
+/*
+ * Flag for a9 processor
+ */
+ #if !defined (ARMR5) && !defined (__aarch64__) && !defined (ARMA53_32)
+ #define ARMA9
+ #endif
+
+/** @name Register Map
+ *
+ * Register offsets from the base address of the device.
+ *
+ * @{
+ */
+#define XTTCPS_CLK_CNTRL_OFFSET 0x00000000U /**< Clock Control Register */
+#define XTTCPS_CNT_CNTRL_OFFSET 0x0000000CU /**< Counter Control Register*/
+#define XTTCPS_COUNT_VALUE_OFFSET 0x00000018U /**< Current Counter Value */
+#define XTTCPS_INTERVAL_VAL_OFFSET 0x00000024U /**< Interval Count Value */
+#define XTTCPS_MATCH_0_OFFSET 0x00000030U /**< Match 1 value */
+#define XTTCPS_MATCH_1_OFFSET 0x0000003CU /**< Match 2 value */
+#define XTTCPS_MATCH_2_OFFSET 0x00000048U /**< Match 3 value */
+#define XTTCPS_ISR_OFFSET 0x00000054U /**< Interrupt Status Register */
+#define XTTCPS_IER_OFFSET 0x00000060U /**< Interrupt Enable Register */
+/* @} */
+
+/** @name Clock Control Register
+ * Clock Control Register definitions
+ * @{
+ */
+#define XTTCPS_CLK_CNTRL_PS_EN_MASK 0x00000001U /**< Prescale enable */
+#define XTTCPS_CLK_CNTRL_PS_VAL_MASK 0x0000001EU /**< Prescale value */
+#define XTTCPS_CLK_CNTRL_PS_VAL_SHIFT 1U /**< Prescale shift */
+#define XTTCPS_CLK_CNTRL_PS_DISABLE 16U /**< Prescale disable */
+#define XTTCPS_CLK_CNTRL_SRC_MASK 0x00000020U /**< Clock source */
+#define XTTCPS_CLK_CNTRL_EXT_EDGE_MASK 0x00000040U /**< External Clock edge */
+/* @} */
+
+/** @name Counter Control Register
+ * Counter Control Register definitions
+ * @{
+ */
+#define XTTCPS_CNT_CNTRL_DIS_MASK 0x00000001U /**< Disable the counter */
+#define XTTCPS_CNT_CNTRL_INT_MASK 0x00000002U /**< Interval mode */
+#define XTTCPS_CNT_CNTRL_DECR_MASK 0x00000004U /**< Decrement mode */
+#define XTTCPS_CNT_CNTRL_MATCH_MASK 0x00000008U /**< Match mode */
+#define XTTCPS_CNT_CNTRL_RST_MASK 0x00000010U /**< Reset counter */
+#define XTTCPS_CNT_CNTRL_EN_WAVE_MASK 0x00000020U /**< Enable waveform */
+#define XTTCPS_CNT_CNTRL_POL_WAVE_MASK 0x00000040U /**< Waveform polarity */
+#define XTTCPS_CNT_CNTRL_RESET_VALUE 0x00000021U /**< Reset value */
+/* @} */
+
+/** @name Current Counter Value Register
+ * Current Counter Value Register definitions
+ * @{
+ */
+#if defined(ARMA9)
+#define XTTCPS_COUNT_VALUE_MASK 0x0000FFFFU /**< 16-bit counter value */
+#else
+#define XTTCPS_COUNT_VALUE_MASK 0xFFFFFFFFU /**< 32-bit counter value */
+#endif
+/* @} */
+
+/** @name Interval Value Register
+ * Interval Value Register is the maximum value the counter will count up or
+ * down to.
+ * @{
+ */
+#if defined(ARMA9)
+#define XTTCPS_INTERVAL_VAL_MASK 0x0000FFFFU /**< 16-bit Interval value*/
+#else
+#define XTTCPS_INTERVAL_VAL_MASK 0xFFFFFFFFU /**< 32-bit Interval value*/
+#endif
+/* @} */
+
+/** @name Match Registers
+ * Definitions for Match registers, each timer counter has three match
+ * registers.
+ * @{
+ */
+#if defined(ARMA9)
+#define XTTCPS_MATCH_MASK 0x0000FFFFU /**< 16-bit Match value */
+#else
+#define XTTCPS_MATCH_MASK 0xFFFFFFFFU /**< 32-bit Match value */
+#endif
+#define XTTCPS_NUM_MATCH_REG 3U /**< Num of Match reg */
+/* @} */
+
+/** @name Interrupt Registers
+ * Following register bit mask is for all interrupt registers.
+ *
+ * @{
+ */
+#define XTTCPS_IXR_INTERVAL_MASK 0x00000001U /**< Interval Interrupt */
+#define XTTCPS_IXR_MATCH_0_MASK 0x00000002U /**< Match 1 Interrupt */
+#define XTTCPS_IXR_MATCH_1_MASK 0x00000004U /**< Match 2 Interrupt */
+#define XTTCPS_IXR_MATCH_2_MASK 0x00000008U /**< Match 3 Interrupt */
+#define XTTCPS_IXR_CNT_OVR_MASK 0x00000010U /**< Counter Overflow */
+#define XTTCPS_IXR_ALL_MASK 0x0000001FU /**< All valid Interrupts */
+/* @} */
+
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/****************************************************************************/
+/**
+*
+* Read the given Timer Counter register.
+*
+* @param BaseAddress is the base address of the timer counter device.
+* @param RegOffset is the register offset to be read
+*
+* @return The 32-bit value of the register
+*
+* @note C-style signature:
+* u32 XTtcPs_ReadReg(u32 BaseAddress, u32 RegOffset)
+*
+*****************************************************************************/
+#define XTtcPs_ReadReg(BaseAddress, RegOffset) \
+ (Xil_In32((BaseAddress) + (u32)(RegOffset)))
+
+/****************************************************************************/
+/**
+*
+* Write the given Timer Counter register.
+*
+* @param BaseAddress is the base address of the timer counter device.
+* @param RegOffset is the register offset to be written
+* @param Data is the 32-bit value to write to the register
+*
+* @return None.
+*
+* @note C-style signature:
+* void XTtcPs_WriteReg(XTtcPs BaseAddress, u32 RegOffset,
+* u32 Data)
+*
+*****************************************************************************/
+#define XTtcPs_WriteReg(BaseAddress, RegOffset, Data) \
+ (Xil_Out32((BaseAddress) + (u32)(RegOffset), (u32)(Data)))
+
+/****************************************************************************/
+/**
+*
+* Calculate a match register offset using the Match Register index.
+*
+* @param MatchIndex is the 0-2 value of the match register
+*
+* @return MATCH_N_OFFSET.
+*
+* @note C-style signature:
+* u32 XTtcPs_Match_N_Offset(u8 MatchIndex)
+*
+*****************************************************************************/
+#define XTtcPs_Match_N_Offset(MatchIndex) \
+ ((u32)XTTCPS_MATCH_0_OFFSET + ((u32)(12U) * (u32)(MatchIndex)))
+
+/************************** Function Prototypes ******************************/
+
+/************************** Variable Definitions *****************************/
+#ifdef __cplusplus
+}
+#endif
+#endif /* end of protection macro */
+/** @} */
diff --git a/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/include/xuartps.h b/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/include/xuartps.h
new file mode 100644
index 0000000..45618b1
--- /dev/null
+++ b/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/include/xuartps.h
@@ -0,0 +1,515 @@
+/******************************************************************************
+*
+* Copyright (C) 2010 - 2018 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+* THE SOFTWARE.
+*
+*
+*
+******************************************************************************/
+/****************************************************************************/
+/**
+*
+* @file xuartps.h
+* @addtogroup uartps_v3_8
+* @{
+* @details
+*
+* This driver supports the following features:
+*
+* - Dynamic data format (baud rate, data bits, stop bits, parity)
+* - Polled mode
+* - Interrupt driven mode
+* - Transmit and receive FIFOs (32 byte FIFO depth)
+* - Access to the external modem control lines
+*
+* <b>Initialization & Configuration</b>
+*
+* The XUartPs_Config structure is used by the driver to configure itself.
+* Fields inside this structure are properties of XUartPs based on its hardware
+* build.
+*
+* To support multiple runtime loading and initialization strategies employed
+* by various operating systems, the driver instance can be initialized in the
+* following way:
+*
+* - XUartPs_CfgInitialize(InstancePtr, CfgPtr, EffectiveAddr) - Uses a
+* configuration structure provided by the caller. If running in a system
+* with address translation, the parameter EffectiveAddr should be the
+* virtual address.
+*
+* <b>Baud Rate</b>
+*
+* The UART has an internal baud rate generator, which furnishes the baud rate
+* clock for both the receiver and the transmitter. Ther input clock frequency
+* can be either the master clock or the master clock divided by 8, configured
+* through the mode register.
+*
+* Accompanied with the baud rate divider register, the baud rate is determined
+* by:
+* <pre>
+* baud_rate = input_clock / (bgen * (bdiv + 1)
+* </pre>
+* where bgen is the value of the baud rate generator, and bdiv is the value of
+* baud rate divider.
+*
+* <b>Interrupts</b>
+*
+* The FIFOs are not flushed when the driver is initialized, but a function is
+* provided to allow the user to reset the FIFOs if desired.
+*
+* The driver defaults to no interrupts at initialization such that interrupts
+* must be enabled if desired. An interrupt is generated for one of the
+* following conditions.
+*
+* - A change in the modem signals
+* - Data in the receive FIFO for a configuable time without receiver activity
+* - A parity error
+* - A framing error
+* - An overrun error
+* - Transmit FIFO is full
+* - Transmit FIFO is empty
+* - Receive FIFO is full
+* - Receive FIFO is empty
+* - Data in the receive FIFO equal to the receive threshold
+*
+* The application can control which interrupts are enabled using the
+* XUartPs_SetInterruptMask() function.
+*
+* In order to use interrupts, it is necessary for the user to connect the
+* driver interrupt handler, XUartPs_InterruptHandler(), to the interrupt
+* system of the application. A separate handler should be provided by the
+* application to communicate with the interrupt system, and conduct
+* application specific interrupt handling. An application registers its own
+* handler through the XUartPs_SetHandler() function.
+*
+* <b>Data Transfer</b>
+*
+* The functions, XUartPs_Send() and XUartPs_Recv(), are provided in the
+* driver to allow data to be sent and received. They can be used in either
+* polled or interrupt mode.
+*
+* @note
+*
+* The default configuration for the UART after initialization is:
+*
+* - 9,600 bps or XPAR_DFT_BAUDRATE if defined
+* - 8 data bits
+* - 1 stop bit
+* - no parity
+* - FIFO's are enabled with a receive threshold of 8 bytes
+* - The RX timeout is enabled with a timeout of 1 (4 char times)
+*
+* <pre>
+* MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ----- ------ -------- ----------------------------------------------
+* 1.00a drg/jz 01/12/10 First Release
+* 1.00a sdm 09/27/11 Fixed compiler warnings and also a bug
+* in XUartPs_SetFlowDelay where the value was not
+* being written to the register.
+* 1.01a sdm 12/20/11 Removed the InputClockHz parameter from the XUartPs
+* instance structure and the driver is updated to use
+* InputClockHz parameter from the XUartPs_Config config
+* structure.
+* Added a parameter to XUartPs_Config structure which
+* specifies whether the user has selected Modem pins
+* to be connected to MIO or FMIO.
+* Added the tcl file to generate the xparameters.h
+* 1.02a sg 05/16/12 Changed XUARTPS_RXWM_MASK to 0x3F for CR 652540 fix.
+* 1.03a sg 07/16/12 Updated XUARTPS_FORMAT_7_BITS and XUARTPS_FORMAT_6_BITS
+* with the correct values for CR 666724
+* Added defines for XUARTPS_IXR_TOVR, XUARTPS_IXR_TNFUL
+* and XUARTPS_IXR_TTRIG.
+* Modified the name of these defines
+* XUARTPS_MEDEMSR_DCDX to XUARTPS_MODEMSR_DDCD
+* XUARTPS_MEDEMSR_RIX to XUARTPS_MODEMSR_TERI
+* XUARTPS_MEDEMSR_DSRX to XUARTPS_MODEMSR_DDSR
+* XUARTPS_MEDEMSR_CTSX to XUARTPS_MODEMSR_DCTS
+* 1.05a hk 08/22/13 Added API for uart reset and related
+* constant definitions.
+* 2.0 hk 03/07/14 Version number revised.
+* 2.1 hk 04/16/14 Change XUARTPS_MAX_RATE to 921600. CR# 780625.
+* 2.2 hk 06/23/14 SW reset of RX and TX should be done when changing
+* baud rate. CR# 804281.
+* 3.0 vm 12/09/14 Modified source code according to misrac guideline.
+* Support for Zynq Ultrascale Mp added.
+* 3.1 kvn 04/10/15 Modified code for latest RTL changes. Also added
+* platform variable in driver instance structure.
+* 3.1 adk 14/03/16 Include interrupt examples in the peripheral test when
+* uart is connected to a valid interrupt controller CR#946803.
+* 3.2 rk 07/20/16 Modified the logic for transmission break bit set
+* 3.4 ms 01/23/17 Added xil_printf statement in main function for all
+* examples to ensure that "Successfully ran" and "Failed"
+* strings are available in all examples. This is a fix
+* for CR-965028.
+* ms 03/17/17 Added readme.txt file in examples folder for doxygen
+* generation.
+* 3.6 ms 02/16/18 Updates the flow control mode offset value in modem
+* control register.
+* 3.7 aru 08/17/18 Resolved MISRA-C:2012 compliance mandatory violations.
+*
+* </pre>
+*
+*****************************************************************************/
+
+#ifndef XUARTPS_H /* prevent circular inclusions */
+#define XUARTPS_H /* by using protection macros */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/***************************** Include Files ********************************/
+
+#include "xil_types.h"
+#include "xil_assert.h"
+#include "xstatus.h"
+#include "xuartps_hw.h"
+#include "xplatform_info.h"
+
+/************************** Constant Definitions ****************************/
+
+/*
+ * The following constants indicate the max and min baud rates and these
+ * numbers are based only on the testing that has been done. The hardware
+ * is capable of other baud rates.
+ */
+#define XUARTPS_MAX_RATE 921600U
+#define XUARTPS_MIN_RATE 110U
+
+#define XUARTPS_DFT_BAUDRATE 115200U /* Default baud rate */
+
+/** @name Configuration options
+ * @{
+ */
+/**
+ * These constants specify the options that may be set or retrieved
+ * with the driver, each is a unique bit mask such that multiple options
+ * may be specified. These constants indicate the available options
+ * in active state.
+ *
+ */
+
+#define XUARTPS_OPTION_SET_BREAK 0x0080U /**< Starts break transmission */
+#define XUARTPS_OPTION_STOP_BREAK 0x0040U /**< Stops break transmission */
+#define XUARTPS_OPTION_RESET_TMOUT 0x0020U /**< Reset the receive timeout */
+#define XUARTPS_OPTION_RESET_TX 0x0010U /**< Reset the transmitter */
+#define XUARTPS_OPTION_RESET_RX 0x0008U /**< Reset the receiver */
+#define XUARTPS_OPTION_ASSERT_RTS 0x0004U /**< Assert the RTS bit */
+#define XUARTPS_OPTION_ASSERT_DTR 0x0002U /**< Assert the DTR bit */
+#define XUARTPS_OPTION_SET_FCM 0x0001U /**< Turn on flow control mode */
+/*@}*/
+
+
+/** @name Channel Operational Mode
+ *
+ * The UART can operate in one of four modes: Normal, Local Loopback, Remote
+ * Loopback, or automatic echo.
+ *
+ * @{
+ */
+
+#define XUARTPS_OPER_MODE_NORMAL (u8)0x00U /**< Normal Mode */
+#define XUARTPS_OPER_MODE_AUTO_ECHO (u8)0x01U /**< Auto Echo Mode */
+#define XUARTPS_OPER_MODE_LOCAL_LOOP (u8)0x02U /**< Local Loopback Mode */
+#define XUARTPS_OPER_MODE_REMOTE_LOOP (u8)0x03U /**< Remote Loopback Mode */
+
+/* @} */
+
+/** @name Data format values
+ *
+ * These constants specify the data format that the driver supports.
+ * The data format includes the number of data bits, the number of stop
+ * bits and parity.
+ *
+ * @{
+ */
+#define XUARTPS_FORMAT_8_BITS 0U /**< 8 data bits */
+#define XUARTPS_FORMAT_7_BITS 2U /**< 7 data bits */
+#define XUARTPS_FORMAT_6_BITS 3U /**< 6 data bits */
+
+#define XUARTPS_FORMAT_NO_PARITY 4U /**< No parity */
+#define XUARTPS_FORMAT_MARK_PARITY 3U /**< Mark parity */
+#define XUARTPS_FORMAT_SPACE_PARITY 2U /**< parity */
+#define XUARTPS_FORMAT_ODD_PARITY 1U /**< Odd parity */
+#define XUARTPS_FORMAT_EVEN_PARITY 0U /**< Even parity */
+
+#define XUARTPS_FORMAT_2_STOP_BIT 2U /**< 2 stop bits */
+#define XUARTPS_FORMAT_1_5_STOP_BIT 1U /**< 1.5 stop bits */
+#define XUARTPS_FORMAT_1_STOP_BIT 0U /**< 1 stop bit */
+/*@}*/
+
+/** @name Callback events
+ *
+ * These constants specify the handler events that an application can handle
+ * using its specific handler function. Note that these constants are not bit
+ * mask, so only one event can be passed to an application at a time.
+ *
+ * @{
+ */
+#define XUARTPS_EVENT_RECV_DATA 1U /**< Data receiving done */
+#define XUARTPS_EVENT_RECV_TOUT 2U /**< A receive timeout occurred */
+#define XUARTPS_EVENT_SENT_DATA 3U /**< Data transmission done */
+#define XUARTPS_EVENT_RECV_ERROR 4U /**< A receive error detected */
+#define XUARTPS_EVENT_MODEM 5U /**< Modem status changed */
+#define XUARTPS_EVENT_PARE_FRAME_BRKE 6U /**< A receive parity, frame, break
+ * error detected */
+#define XUARTPS_EVENT_RECV_ORERR 7U /**< A receive overrun error detected */
+/*@}*/
+
+
+/**************************** Type Definitions ******************************/
+
+/**
+ * This typedef contains configuration information for the device.
+ */
+typedef struct {
+ u16 DeviceId; /**< Unique ID of device */
+ u32 BaseAddress; /**< Base address of device (IPIF) */
+ u32 InputClockHz;/**< Input clock frequency */
+ s32 ModemPinsConnected; /** Specifies whether modem pins are connected
+ * to MIO or FMIO */
+} XUartPs_Config;
+
+/* Keep track of state information about a data buffer in the interrupt mode. */
+typedef struct {
+ u8 *NextBytePtr;
+ u32 RequestedBytes;
+ u32 RemainingBytes;
+} XUartPsBuffer;
+
+/**
+ * Keep track of data format setting of a device.
+ */
+typedef struct {
+ u32 BaudRate; /**< In bps, ie 1200 */
+ u32 DataBits; /**< Number of data bits */
+ u32 Parity; /**< Parity */
+ u8 StopBits; /**< Number of stop bits */
+} XUartPsFormat;
+
+/******************************************************************************/
+/**
+ * This data type defines a handler that an application defines to communicate
+ * with interrupt system to retrieve state information about an application.
+ *
+ * @param CallBackRef is a callback reference passed in by the upper layer
+ * when setting the handler, and is passed back to the upper layer
+ * when the handler is called. It is used to find the device driver
+ * instance.
+ * @param Event contains one of the event constants indicating events that
+ * have occurred.
+ * @param EventData contains the number of bytes sent or received at the
+ * time of the call for send and receive events and contains the
+ * modem status for modem events.
+ *
+ ******************************************************************************/
+typedef void (*XUartPs_Handler) (void *CallBackRef, u32 Event,
+ u32 EventData);
+
+/**
+ * The XUartPs driver instance data structure. A pointer to an instance data
+ * structure is passed around by functions to refer to a specific driver
+ * instance.
+ */
+typedef struct {
+ XUartPs_Config Config; /* Configuration data structure */
+ u32 InputClockHz; /* Input clock frequency */
+ u32 IsReady; /* Device is initialized and ready */
+ u32 BaudRate; /* Current baud rate */
+
+ XUartPsBuffer SendBuffer;
+ XUartPsBuffer ReceiveBuffer;
+
+ XUartPs_Handler Handler;
+ void *CallBackRef; /* Callback reference for event handler */
+ u32 Platform;
+ u8 is_rxbs_error;
+} XUartPs;
+
+
+/***************** Macros (Inline Functions) Definitions ********************/
+
+/****************************************************************************/
+/**
+* Get the UART Channel Status Register.
+*
+* @param InstancePtr is a pointer to the XUartPs instance.
+*
+* @return The value read from the register.
+*
+* @note C-Style signature:
+* u16 XUartPs_GetChannelStatus(XUartPs *InstancePtr)
+*
+******************************************************************************/
+#define XUartPs_GetChannelStatus(InstancePtr) \
+ Xil_In32(((InstancePtr)->Config.BaseAddress) + (u32)XUARTPS_SR_OFFSET)
+
+/****************************************************************************/
+/**
+* Get the UART Mode Control Register.
+*
+* @param InstancePtr is a pointer to the XUartPs instance.
+*
+* @return The value read from the register.
+*
+* @note C-Style signature:
+* u32 XUartPs_GetControl(XUartPs *InstancePtr)
+*
+******************************************************************************/
+#define XUartPs_GetModeControl(InstancePtr) \
+ Xil_In32(((InstancePtr)->Config.BaseAddress) + (u32)XUARTPS_CR_OFFSET)
+
+/****************************************************************************/
+/**
+* Set the UART Mode Control Register.
+*
+* @param InstancePtr is a pointer to the XUartPs instance.
+* @param RegisterValue is the value to be written to the register.
+*
+* @return None.
+*
+* @note C-Style signature:
+* void XUartPs_SetModeControl(XUartPs *InstancePtr, u16 RegisterValue)
+*
+******************************************************************************/
+#define XUartPs_SetModeControl(InstancePtr, RegisterValue) \
+ Xil_Out32(((InstancePtr)->Config.BaseAddress) + (u32)XUARTPS_CR_OFFSET, \
+ (u32)(RegisterValue))
+
+/****************************************************************************/
+/**
+* Enable the transmitter and receiver of the UART.
+*
+* @param InstancePtr is a pointer to the XUartPs instance.
+*
+* @return None.
+*
+* @note C-Style signature:
+* void XUartPs_EnableUart(XUartPs *InstancePtr)
+*
+******************************************************************************/
+#define XUartPs_EnableUart(InstancePtr) \
+ Xil_Out32(((InstancePtr)->Config.BaseAddress + (u32)XUARTPS_CR_OFFSET), \
+ ((Xil_In32((InstancePtr)->Config.BaseAddress + (u32)XUARTPS_CR_OFFSET) & \
+ (u32)(~XUARTPS_CR_EN_DIS_MASK)) | ((u32)XUARTPS_CR_RX_EN | (u32)XUARTPS_CR_TX_EN)))
+
+/****************************************************************************/
+/**
+* Disable the transmitter and receiver of the UART.
+*
+* @param InstancePtr is a pointer to the XUartPs instance.
+*
+* @return None.
+*
+* @note C-Style signature:
+* void XUartPs_DisableUart(XUartPs *InstancePtr)
+*
+******************************************************************************/
+#define XUartPs_DisableUart(InstancePtr) \
+ Xil_Out32(((InstancePtr)->Config.BaseAddress + (u32)XUARTPS_CR_OFFSET), \
+ (((Xil_In32((InstancePtr)->Config.BaseAddress + (u32)XUARTPS_CR_OFFSET)) & \
+ (u32)(~XUARTPS_CR_EN_DIS_MASK)) | ((u32)XUARTPS_CR_RX_DIS | (u32)XUARTPS_CR_TX_DIS)))
+
+/****************************************************************************/
+/**
+* Determine if the transmitter FIFO is empty.
+*
+* @param InstancePtr is a pointer to the XUartPs instance.
+*
+* @return
+* - TRUE if a byte can be sent
+* - FALSE if the Transmitter Fifo is not empty
+*
+* @note C-Style signature:
+* u32 XUartPs_IsTransmitEmpty(XUartPs InstancePtr)
+*
+******************************************************************************/
+#define XUartPs_IsTransmitEmpty(InstancePtr) \
+ ((Xil_In32(((InstancePtr)->Config.BaseAddress) + (u32)XUARTPS_SR_OFFSET) & \
+ (u32)XUARTPS_SR_TXEMPTY) == (u32)XUARTPS_SR_TXEMPTY)
+
+
+/************************** Function Prototypes *****************************/
+
+/* Static lookup function implemented in xuartps_sinit.c */
+XUartPs_Config *XUartPs_LookupConfig(u16 DeviceId);
+
+/* Interface functions implemented in xuartps.c */
+s32 XUartPs_CfgInitialize(XUartPs *InstancePtr,
+ XUartPs_Config * Config, u32 EffectiveAddr);
+
+u32 XUartPs_Send(XUartPs *InstancePtr,u8 *BufferPtr,
+ u32 NumBytes);
+
+u32 XUartPs_Recv(XUartPs *InstancePtr,u8 *BufferPtr,
+ u32 NumBytes);
+
+s32 XUartPs_SetBaudRate(XUartPs *InstancePtr, u32 BaudRate);
+
+/* Options functions in xuartps_options.c */
+void XUartPs_SetOptions(XUartPs *InstancePtr, u16 Options);
+
+u16 XUartPs_GetOptions(XUartPs *InstancePtr);
+
+void XUartPs_SetFifoThreshold(XUartPs *InstancePtr, u8 TriggerLevel);
+
+u8 XUartPs_GetFifoThreshold(XUartPs *InstancePtr);
+
+u16 XUartPs_GetModemStatus(XUartPs *InstancePtr);
+
+u32 XUartPs_IsSending(XUartPs *InstancePtr);
+
+u8 XUartPs_GetOperMode(XUartPs *InstancePtr);
+
+void XUartPs_SetOperMode(XUartPs *InstancePtr, u8 OperationMode);
+
+u8 XUartPs_GetFlowDelay(XUartPs *InstancePtr);
+
+void XUartPs_SetFlowDelay(XUartPs *InstancePtr, u8 FlowDelayValue);
+
+u8 XUartPs_GetRecvTimeout(XUartPs *InstancePtr);
+
+void XUartPs_SetRecvTimeout(XUartPs *InstancePtr, u8 RecvTimeout);
+
+s32 XUartPs_SetDataFormat(XUartPs *InstancePtr, XUartPsFormat * FormatPtr);
+
+void XUartPs_GetDataFormat(XUartPs *InstancePtr, XUartPsFormat * FormatPtr);
+
+/* interrupt functions in xuartps_intr.c */
+u32 XUartPs_GetInterruptMask(XUartPs *InstancePtr);
+
+void XUartPs_SetInterruptMask(XUartPs *InstancePtr, u32 Mask);
+
+void XUartPs_InterruptHandler(XUartPs *InstancePtr);
+
+void XUartPs_SetHandler(XUartPs *InstancePtr, XUartPs_Handler FuncPtr,
+ void *CallBackRef);
+
+/* self-test functions in xuartps_selftest.c */
+s32 XUartPs_SelfTest(XUartPs *InstancePtr);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* end of protection macro */
+/** @} */
diff --git a/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/include/xuartps_hw.h b/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/include/xuartps_hw.h
new file mode 100644
index 0000000..f627472
--- /dev/null
+++ b/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/include/xuartps_hw.h
@@ -0,0 +1,445 @@
+/******************************************************************************
+*
+* Copyright (C) 2010 - 2017 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+* THE SOFTWARE.
+*
+*
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xuartps_hw.h
+* @addtogroup uartps_v3_8
+* @{
+*
+* This header file contains the hardware interface of an XUartPs device.
+*
+* <pre>
+* MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ----- ------ -------- ----------------------------------------------
+* 1.00 drg/jz 01/12/10 First Release
+* 1.03a sg 09/04/12 Added defines for XUARTPS_IXR_TOVR, XUARTPS_IXR_TNFUL
+* and XUARTPS_IXR_TTRIG.
+* Modified the names of these defines
+* XUARTPS_MEDEMSR_DCDX to XUARTPS_MODEMSR_DDCD
+* XUARTPS_MEDEMSR_RIX to XUARTPS_MODEMSR_TERI
+* XUARTPS_MEDEMSR_DSRX to XUARTPS_MODEMSR_DDSR
+* XUARTPS_MEDEMSR_CTSX to XUARTPS_MODEMSR_DCTS
+* 1.05a hk 08/22/13 Added prototype for uart reset and related
+* constant definitions.
+* 3.00 kvn 02/13/15 Modified code for MISRA-C:2012 compliance.
+* 3.1 kvn 04/10/15 Modified code for latest RTL changes.
+* 3.6 ms 02/16/18 Updates flow control mode offset value in
+* modem control register.
+*
+* </pre>
+*
+******************************************************************************/
+#ifndef XUARTPS_HW_H /* prevent circular inclusions */
+#define XUARTPS_HW_H /* by using protection macros */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/***************************** Include Files *********************************/
+
+#include "xil_types.h"
+#include "xil_assert.h"
+#include "xil_io.h"
+
+/************************** Constant Definitions *****************************/
+
+/** @name Register Map
+ *
+ * Register offsets for the UART.
+ * @{
+ */
+#define XUARTPS_CR_OFFSET 0x0000U /**< Control Register [8:0] */
+#define XUARTPS_MR_OFFSET 0x0004U /**< Mode Register [9:0] */
+#define XUARTPS_IER_OFFSET 0x0008U /**< Interrupt Enable [12:0] */
+#define XUARTPS_IDR_OFFSET 0x000CU /**< Interrupt Disable [12:0] */
+#define XUARTPS_IMR_OFFSET 0x0010U /**< Interrupt Mask [12:0] */
+#define XUARTPS_ISR_OFFSET 0x0014U /**< Interrupt Status [12:0]*/
+#define XUARTPS_BAUDGEN_OFFSET 0x0018U /**< Baud Rate Generator [15:0] */
+#define XUARTPS_RXTOUT_OFFSET 0x001CU /**< RX Timeout [7:0] */
+#define XUARTPS_RXWM_OFFSET 0x0020U /**< RX FIFO Trigger Level [5:0] */
+#define XUARTPS_MODEMCR_OFFSET 0x0024U /**< Modem Control [5:0] */
+#define XUARTPS_MODEMSR_OFFSET 0x0028U /**< Modem Status [8:0] */
+#define XUARTPS_SR_OFFSET 0x002CU /**< Channel Status [14:0] */
+#define XUARTPS_FIFO_OFFSET 0x0030U /**< FIFO [7:0] */
+#define XUARTPS_BAUDDIV_OFFSET 0x0034U /**< Baud Rate Divider [7:0] */
+#define XUARTPS_FLOWDEL_OFFSET 0x0038U /**< Flow Delay [5:0] */
+#define XUARTPS_TXWM_OFFSET 0x0044U /**< TX FIFO Trigger Level [5:0] */
+#define XUARTPS_RXBS_OFFSET 0x0048U /**< RX FIFO Byte Status [11:0] */
+/* @} */
+
+/** @name Control Register
+ *
+ * The Control register (CR) controls the major functions of the device.
+ *
+ * Control Register Bit Definition
+ */
+
+#define XUARTPS_CR_STOPBRK 0x00000100U /**< Stop transmission of break */
+#define XUARTPS_CR_STARTBRK 0x00000080U /**< Set break */
+#define XUARTPS_CR_TORST 0x00000040U /**< RX timeout counter restart */
+#define XUARTPS_CR_TX_DIS 0x00000020U /**< TX disabled. */
+#define XUARTPS_CR_TX_EN 0x00000010U /**< TX enabled */
+#define XUARTPS_CR_RX_DIS 0x00000008U /**< RX disabled. */
+#define XUARTPS_CR_RX_EN 0x00000004U /**< RX enabled */
+#define XUARTPS_CR_EN_DIS_MASK 0x0000003CU /**< Enable/disable Mask */
+#define XUARTPS_CR_TXRST 0x00000002U /**< TX logic reset */
+#define XUARTPS_CR_RXRST 0x00000001U /**< RX logic reset */
+/* @}*/
+
+
+/** @name Mode Register
+ *
+ * The mode register (MR) defines the mode of transfer as well as the data
+ * format. If this register is modified during transmission or reception,
+ * data validity cannot be guaranteed.
+ *
+ * Mode Register Bit Definition
+ * @{
+ */
+#define XUARTPS_MR_CCLK 0x00000400U /**< Input clock selection */
+#define XUARTPS_MR_CHMODE_R_LOOP 0x00000300U /**< Remote loopback mode */
+#define XUARTPS_MR_CHMODE_L_LOOP 0x00000200U /**< Local loopback mode */
+#define XUARTPS_MR_CHMODE_ECHO 0x00000100U /**< Auto echo mode */
+#define XUARTPS_MR_CHMODE_NORM 0x00000000U /**< Normal mode */
+#define XUARTPS_MR_CHMODE_SHIFT 8U /**< Mode shift */
+#define XUARTPS_MR_CHMODE_MASK 0x00000300U /**< Mode mask */
+#define XUARTPS_MR_STOPMODE_2_BIT 0x00000080U /**< 2 stop bits */
+#define XUARTPS_MR_STOPMODE_1_5_BIT 0x00000040U /**< 1.5 stop bits */
+#define XUARTPS_MR_STOPMODE_1_BIT 0x00000000U /**< 1 stop bit */
+#define XUARTPS_MR_STOPMODE_SHIFT 6U /**< Stop bits shift */
+#define XUARTPS_MR_STOPMODE_MASK 0x000000A0U /**< Stop bits mask */
+#define XUARTPS_MR_PARITY_NONE 0x00000020U /**< No parity mode */
+#define XUARTPS_MR_PARITY_MARK 0x00000018U /**< Mark parity mode */
+#define XUARTPS_MR_PARITY_SPACE 0x00000010U /**< Space parity mode */
+#define XUARTPS_MR_PARITY_ODD 0x00000008U /**< Odd parity mode */
+#define XUARTPS_MR_PARITY_EVEN 0x00000000U /**< Even parity mode */
+#define XUARTPS_MR_PARITY_SHIFT 3U /**< Parity setting shift */
+#define XUARTPS_MR_PARITY_MASK 0x00000038U /**< Parity mask */
+#define XUARTPS_MR_CHARLEN_6_BIT 0x00000006U /**< 6 bits data */
+#define XUARTPS_MR_CHARLEN_7_BIT 0x00000004U /**< 7 bits data */
+#define XUARTPS_MR_CHARLEN_8_BIT 0x00000000U /**< 8 bits data */
+#define XUARTPS_MR_CHARLEN_SHIFT 1U /**< Data Length shift */
+#define XUARTPS_MR_CHARLEN_MASK 0x00000006U /**< Data length mask */
+#define XUARTPS_MR_CLKSEL 0x00000001U /**< Input clock selection */
+/* @} */
+
+
+/** @name Interrupt Registers
+ *
+ * Interrupt control logic uses the interrupt enable register (IER) and the
+ * interrupt disable register (IDR) to set the value of the bits in the
+ * interrupt mask register (IMR). The IMR determines whether to pass an
+ * interrupt to the interrupt status register (ISR).
+ * Writing a 1 to IER Enbables an interrupt, writing a 1 to IDR disables an
+ * interrupt. IMR and ISR are read only, and IER and IDR are write only.
+ * Reading either IER or IDR returns 0x00.
+ *
+ * All four registers have the same bit definitions.
+ *
+ * @{
+ */
+#define XUARTPS_IXR_RBRK 0x00002000U /**< Rx FIFO break detect interrupt */
+#define XUARTPS_IXR_TOVR 0x00001000U /**< Tx FIFO Overflow interrupt */
+#define XUARTPS_IXR_TNFUL 0x00000800U /**< Tx FIFO Nearly Full interrupt */
+#define XUARTPS_IXR_TTRIG 0x00000400U /**< Tx Trig interrupt */
+#define XUARTPS_IXR_DMS 0x00000200U /**< Modem status change interrupt */
+#define XUARTPS_IXR_TOUT 0x00000100U /**< Timeout error interrupt */
+#define XUARTPS_IXR_PARITY 0x00000080U /**< Parity error interrupt */
+#define XUARTPS_IXR_FRAMING 0x00000040U /**< Framing error interrupt */
+#define XUARTPS_IXR_OVER 0x00000020U /**< Overrun error interrupt */
+#define XUARTPS_IXR_TXFULL 0x00000010U /**< TX FIFO full interrupt. */
+#define XUARTPS_IXR_TXEMPTY 0x00000008U /**< TX FIFO empty interrupt. */
+#define XUARTPS_IXR_RXFULL 0x00000004U /**< RX FIFO full interrupt. */
+#define XUARTPS_IXR_RXEMPTY 0x00000002U /**< RX FIFO empty interrupt. */
+#define XUARTPS_IXR_RXOVR 0x00000001U /**< RX FIFO trigger interrupt. */
+#define XUARTPS_IXR_MASK 0x00003FFFU /**< Valid bit mask */
+/* @} */
+
+
+/** @name Baud Rate Generator Register
+ *
+ * The baud rate generator control register (BRGR) is a 16 bit register that
+ * controls the receiver bit sample clock and baud rate.
+ * Valid values are 1 - 65535.
+ *
+ * Bit Sample Rate = CCLK / BRGR, where the CCLK is selected by the MR_CCLK bit
+ * in the MR register.
+ * @{
+ */
+#define XUARTPS_BAUDGEN_DISABLE 0x00000000U /**< Disable clock */
+#define XUARTPS_BAUDGEN_MASK 0x0000FFFFU /**< Valid bits mask */
+#define XUARTPS_BAUDGEN_RESET_VAL 0x0000028BU /**< Reset value */
+
+/** @name Baud Divisor Rate register
+ *
+ * The baud rate divider register (BDIV) controls how much the bit sample
+ * rate is divided by. It sets the baud rate.
+ * Valid values are 0x04 to 0xFF. Writing a value less than 4 will be ignored.
+ *
+ * Baud rate = CCLK / ((BAUDDIV + 1) x BRGR), where the CCLK is selected by
+ * the MR_CCLK bit in the MR register.
+ * @{
+ */
+#define XUARTPS_BAUDDIV_MASK 0x000000FFU /**< 8 bit baud divider mask */
+#define XUARTPS_BAUDDIV_RESET_VAL 0x0000000FU /**< Reset value */
+/* @} */
+
+
+/** @name Receiver Timeout Register
+ *
+ * Use the receiver timeout register (RTR) to detect an idle condition on
+ * the receiver data line.
+ *
+ * @{
+ */
+#define XUARTPS_RXTOUT_DISABLE 0x00000000U /**< Disable time out */
+#define XUARTPS_RXTOUT_MASK 0x000000FFU /**< Valid bits mask */
+
+/** @name Receiver FIFO Trigger Level Register
+ *
+ * Use the Receiver FIFO Trigger Level Register (RTRIG) to set the value at
+ * which the RX FIFO triggers an interrupt event.
+ * @{
+ */
+
+#define XUARTPS_RXWM_DISABLE 0x00000000U /**< Disable RX trigger interrupt */
+#define XUARTPS_RXWM_MASK 0x0000003FU /**< Valid bits mask */
+#define XUARTPS_RXWM_RESET_VAL 0x00000020U /**< Reset value */
+/* @} */
+
+/** @name Transmit FIFO Trigger Level Register
+ *
+ * Use the Transmit FIFO Trigger Level Register (TTRIG) to set the value at
+ * which the TX FIFO triggers an interrupt event.
+ * @{
+ */
+
+#define XUARTPS_TXWM_MASK 0x0000003FU /**< Valid bits mask */
+#define XUARTPS_TXWM_RESET_VAL 0x00000020U /**< Reset value */
+/* @} */
+
+/** @name Modem Control Register
+ *
+ * This register (MODEMCR) controls the interface with the modem or data set,
+ * or a peripheral device emulating a modem.
+ *
+ * @{
+ */
+#define XUARTPS_MODEMCR_FCM 0x00000020U /**< Flow control mode */
+#define XUARTPS_MODEMCR_RTS 0x00000002U /**< Request to send */
+#define XUARTPS_MODEMCR_DTR 0x00000001U /**< Data terminal ready */
+/* @} */
+
+/** @name Modem Status Register
+ *
+ * This register (MODEMSR) indicates the current state of the control lines
+ * from a modem, or another peripheral device, to the CPU. In addition, four
+ * bits of the modem status register provide change information. These bits
+ * are set to a logic 1 whenever a control input from the modem changes state.
+ *
+ * Note: Whenever the DCTS, DDSR, TERI, or DDCD bit is set to logic 1, a modem
+ * status interrupt is generated and this is reflected in the modem status
+ * register.
+ *
+ * @{
+ */
+#define XUARTPS_MODEMSR_FCMS 0x00000100U /**< Flow control mode (FCMS) */
+#define XUARTPS_MODEMSR_DCD 0x00000080U /**< Complement of DCD input */
+#define XUARTPS_MODEMSR_RI 0x00000040U /**< Complement of RI input */
+#define XUARTPS_MODEMSR_DSR 0x00000020U /**< Complement of DSR input */
+#define XUARTPS_MODEMSR_CTS 0x00000010U /**< Complement of CTS input */
+#define XUARTPS_MODEMSR_DDCD 0x00000008U /**< Delta DCD indicator */
+#define XUARTPS_MODEMSR_TERI 0x00000004U /**< Trailing Edge Ring Indicator */
+#define XUARTPS_MODEMSR_DDSR 0x00000002U /**< Change of DSR */
+#define XUARTPS_MODEMSR_DCTS 0x00000001U /**< Change of CTS */
+/* @} */
+
+/** @name Channel Status Register
+ *
+ * The channel status register (CSR) is provided to enable the control logic
+ * to monitor the status of bits in the channel interrupt status register,
+ * even if these are masked out by the interrupt mask register.
+ *
+ * @{
+ */
+#define XUARTPS_SR_TNFUL 0x00004000U /**< TX FIFO Nearly Full Status */
+#define XUARTPS_SR_TTRIG 0x00002000U /**< TX FIFO Trigger Status */
+#define XUARTPS_SR_FLOWDEL 0x00001000U /**< RX FIFO fill over flow delay */
+#define XUARTPS_SR_TACTIVE 0x00000800U /**< TX active */
+#define XUARTPS_SR_RACTIVE 0x00000400U /**< RX active */
+#define XUARTPS_SR_TXFULL 0x00000010U /**< TX FIFO full */
+#define XUARTPS_SR_TXEMPTY 0x00000008U /**< TX FIFO empty */
+#define XUARTPS_SR_RXFULL 0x00000004U /**< RX FIFO full */
+#define XUARTPS_SR_RXEMPTY 0x00000002U /**< RX FIFO empty */
+#define XUARTPS_SR_RXOVR 0x00000001U /**< RX FIFO fill over trigger */
+/* @} */
+
+/** @name Flow Delay Register
+ *
+ * Operation of the flow delay register (FLOWDEL) is very similar to the
+ * receive FIFO trigger register. An internal trigger signal activates when the
+ * FIFO is filled to the level set by this register. This trigger will not
+ * cause an interrupt, although it can be read through the channel status
+ * register. In hardware flow control mode, RTS is deactivated when the trigger
+ * becomes active. RTS only resets when the FIFO level is four less than the
+ * level of the flow delay trigger and the flow delay trigger is not activated.
+ * A value less than 4 disables the flow delay.
+ * @{
+ */
+#define XUARTPS_FLOWDEL_MASK XUARTPS_RXWM_MASK /**< Valid bit mask */
+/* @} */
+
+/** @name Receiver FIFO Byte Status Register
+ *
+ * The Receiver FIFO Status register is used to have a continuous
+ * monitoring of the raw unmasked byte status information. The register
+ * contains frame, parity and break status information for the top
+ * four bytes in the RX FIFO.
+ *
+ * Receiver FIFO Byte Status Register Bit Definition
+ * @{
+ */
+#define XUARTPS_RXBS_BYTE3_BRKE 0x00000800U /**< Byte3 Break Error */
+#define XUARTPS_RXBS_BYTE3_FRME 0x00000400U /**< Byte3 Frame Error */
+#define XUARTPS_RXBS_BYTE3_PARE 0x00000200U /**< Byte3 Parity Error */
+#define XUARTPS_RXBS_BYTE2_BRKE 0x00000100U /**< Byte2 Break Error */
+#define XUARTPS_RXBS_BYTE2_FRME 0x00000080U /**< Byte2 Frame Error */
+#define XUARTPS_RXBS_BYTE2_PARE 0x00000040U /**< Byte2 Parity Error */
+#define XUARTPS_RXBS_BYTE1_BRKE 0x00000020U /**< Byte1 Break Error */
+#define XUARTPS_RXBS_BYTE1_FRME 0x00000010U /**< Byte1 Frame Error */
+#define XUARTPS_RXBS_BYTE1_PARE 0x00000008U /**< Byte1 Parity Error */
+#define XUARTPS_RXBS_BYTE0_BRKE 0x00000004U /**< Byte0 Break Error */
+#define XUARTPS_RXBS_BYTE0_FRME 0x00000002U /**< Byte0 Frame Error */
+#define XUARTPS_RXBS_BYTE0_PARE 0x00000001U /**< Byte0 Parity Error */
+#define XUARTPS_RXBS_MASK 0x00000007U /**< 3 bit RX byte status mask */
+/* @} */
+
+
+/*
+ * Defines for backwards compatibility, will be removed
+ * in the next version of the driver
+ */
+#define XUARTPS_MEDEMSR_DCDX XUARTPS_MODEMSR_DDCD
+#define XUARTPS_MEDEMSR_RIX XUARTPS_MODEMSR_TERI
+#define XUARTPS_MEDEMSR_DSRX XUARTPS_MODEMSR_DDSR
+#define XUARTPS_MEDEMSR_CTSX XUARTPS_MODEMSR_DCTS
+
+
+
+/**************************** Type Definitions *******************************/
+
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/****************************************************************************/
+/**
+* Read a UART register.
+*
+* @param BaseAddress contains the base address of the device.
+* @param RegOffset contains the offset from the base address of the
+* device.
+*
+* @return The value read from the register.
+*
+* @note C-Style signature:
+* u32 XUartPs_ReadReg(u32 BaseAddress, int RegOffset)
+*
+******************************************************************************/
+#define XUartPs_ReadReg(BaseAddress, RegOffset) \
+ Xil_In32((BaseAddress) + (u32)(RegOffset))
+
+/***************************************************************************/
+/**
+* Write a UART register.
+*
+* @param BaseAddress contains the base address of the device.
+* @param RegOffset contains the offset from the base address of the
+* device.
+* @param RegisterValue is the value to be written to the register.
+*
+* @return None.
+*
+* @note C-Style signature:
+* void XUartPs_WriteReg(u32 BaseAddress, int RegOffset,
+* u16 RegisterValue)
+*
+******************************************************************************/
+#define XUartPs_WriteReg(BaseAddress, RegOffset, RegisterValue) \
+ Xil_Out32((BaseAddress) + (u32)(RegOffset), (u32)(RegisterValue))
+
+/****************************************************************************/
+/**
+* Determine if there is receive data in the receiver and/or FIFO.
+*
+* @param BaseAddress contains the base address of the device.
+*
+* @return TRUE if there is receive data, FALSE otherwise.
+*
+* @note C-Style signature:
+* u32 XUartPs_IsReceiveData(u32 BaseAddress)
+*
+******************************************************************************/
+#define XUartPs_IsReceiveData(BaseAddress) \
+ !((Xil_In32((BaseAddress) + XUARTPS_SR_OFFSET) & \
+ (u32)XUARTPS_SR_RXEMPTY) == (u32)XUARTPS_SR_RXEMPTY)
+
+/****************************************************************************/
+/**
+* Determine if a byte of data can be sent with the transmitter.
+*
+* @param BaseAddress contains the base address of the device.
+*
+* @return TRUE if the TX FIFO is full, FALSE if a byte can be put in the
+* FIFO.
+*
+* @note C-Style signature:
+* u32 XUartPs_IsTransmitFull(u32 BaseAddress)
+*
+******************************************************************************/
+#define XUartPs_IsTransmitFull(BaseAddress) \
+ ((Xil_In32((BaseAddress) + XUARTPS_SR_OFFSET) & \
+ (u32)XUARTPS_SR_TXFULL) == (u32)XUARTPS_SR_TXFULL)
+
+/************************** Function Prototypes ******************************/
+
+void XUartPs_SendByte(u32 BaseAddress, u8 Data);
+
+u8 XUartPs_RecvByte(u32 BaseAddress);
+
+void XUartPs_ResetHw(u32 BaseAddress);
+
+/************************** Variable Definitions *****************************/
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* end of protection macro */
+/** @} */
diff --git a/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/include/xusbps.h b/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/include/xusbps.h
new file mode 100644
index 0000000..250cb95
--- /dev/null
+++ b/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/include/xusbps.h
@@ -0,0 +1,1092 @@
+/******************************************************************************
+*
+* Copyright (C) 2010 - 2015 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+* THE SOFTWARE.
+*
+*
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+ *
+ * @file xusbps.h
+* @addtogroup usbps_v2_4
+* @{
+* @details
+ *
+ * This file contains the implementation of the XUsbPs driver. It is the
+ * driver for an USB controller in DEVICE or HOST mode.
+ *
+ * <h2>Introduction</h2>
+ *
+ * The Spartan-3AF Embedded Peripheral Block contains a USB controller for
+ * communication with serial peripherals or hosts. The USB controller supports
+ * Host, Device and On the Go (OTG) applications.
+ *
+ * <h2>USB Controller Features</h2>
+ *
+ * - Supports Low Speed USB 1.1 (1.5Mbps), Full Speed USB 1.1 (12Mbps), and
+ * High Speed USB 2.0 (480Mbps) data speeds
+ * - Supports Device, Host and OTG operational modes
+ * - ULPI transceiver interface for USB 2.0 operation
+ * - Integrated USB Full and Low speed serial transceiver interfaces for lowest
+ * cost connections
+ *
+ * <h2>Initialization & Configuration</h2>
+ *
+ * The configuration of the USB driver happens in multiple stages:
+ *
+ * - (a) Configuration of the basic parameters:
+ * In this stage the basic parameters for the driver are configured,
+ * including the base address and the controller ID.
+ *
+ * - (b) Configuration of the DEVICE endpoints (if applicable):
+ * If DEVICE mode is desired, the endpoints of the controller need to be
+ * configured using the XUsbPs_DeviceConfig data structure. Once the
+ * endpoint configuration is set up in the data structure, The user then
+ * needs to allocate the required amount of DMAable memory and
+ * finalize the configuration of the XUsbPs_DeviceConfig data structure,
+ * e.g. setting the DMAMemVirt and DMAMemPhys members.
+ *
+ * - (c) Configuration of the DEVICE modes:
+ * In the second stage the parameters for DEVICE are configured.
+ * The caller only needs to configure the modes that are
+ * actually used. Configuration is done with the:
+ * XUsbPs_ConfigureDevice()
+ * Configuration parameters are defined and passed
+ * into these functions using the:
+ * XUsbPs_DeviceConfig data structures.
+ *
+ *
+ * <h2>USB Device Endpoints</h2>
+ *
+ * The USB core supports up to 4 endpoints. Each endpoint has two directions,
+ * an OUT (RX) and an IN (TX) direction. Note that the direction is viewed from
+ * the host's perspective. Endpoint 0 defaults to be the control endpoint and
+ * does not need to be set up. Other endpoints need to be configured and set up
+ * depending on the application. Only endpoints that are actuelly used by the
+ * application need to be initialized.
+ * See the example code (xusbps_intr_example.c) for more information.
+ *
+ *
+ * <h2>Interrupt Handling</h2>
+ *
+ * The USB core uses one interrupt line to report interrupts to the CPU.
+ * Interrupts are handled by the driver's interrupt handler function
+ * XUsbPs_IntrHandler().
+ * It has to be registered with the OS's interrupt subsystem. The driver's
+ * interrupt handler divides incoming interrupts into two categories:
+ *
+ * - General device interrupts
+ * - Endopint related interrupts
+ *
+ * The user (typically the adapter layer) can register general interrupt
+ * handler functions and endpoint specific interrupt handler functions with the
+ * driver to receive those interrupts by calling the
+ * XUsbPs_IntrSetHandler()
+ * and
+ * XUsbPs_EpSetHandler()
+ * functions respectively. Calling these functions with a NULL pointer as the
+ * argument for the function pointer will "clear" the handler function.
+ *
+ * The user can register one handler function for the generic interrupts and
+ * two handler functions for each endpoint, one for the RX (OUT) and one for
+ * the TX (IN) direction. For some applications it may be useful to register a
+ * single endpoint handler function for muliple endpoints/directions.
+ *
+ * When a callback function is called by the driver, parameters identifying the
+ * type of the interrupt will be passed into the handler functions. For general
+ * interrupts the interrupt mask will be passed into the handler function. For
+ * endpoint interrupts the parameters include the number of the endpoint, the
+ * direction (OUT/IN) and the type of the interrupt.
+ *
+ *
+ * <h2>Data buffer handling</h2>
+ *
+ * Data buffers are sent to and received from endpoint using the
+ * XUsbPs_EpBufferSend(), XUsbPs_EpBufferSendWithZLT()
+ * and
+ * XUsbPs_EpBufferReceive()
+ * functions.
+ *
+ * User data buffer size is limited to 16 Kbytes. If the user wants to send a
+ * data buffer that is bigger than this limit it needs to break down the data
+ * buffer into multiple fragments and send the fragments individually.
+ *
+ * From the controller perspective Data buffers can be aligned at any boundary.
+ * if the buffers are from cache region then the buffer and buffer size should
+ * be aligned to cache line aligned
+ *
+ *
+ * <h3>Zero copy</h3>
+ *
+ * The driver uses a zero copy mechanism which imposes certain restrictions to
+ * the way the user can handle the data buffers.
+ *
+ * One restriction is that the user needs to release a buffer after it is done
+ * processing the data in the buffer.
+ *
+ * Similarly, when the user sends a data buffer it MUST not re-use the buffer
+ * until it is notified by the driver that the buffer has been transmitted. The
+ * driver will notify the user via the registered endpoint interrupt handling
+ * function by sending a XUSBPS_EP_EVENT_DATA_TX event.
+ *
+ *
+ * <h2>DMA</h2>
+ *
+ * The driver uses DMA internally to move data from/to memory. This behaviour
+ * is transparent to the user. Keeping the DMA handling hidden from the user
+ * has the advantage that the same API can be used with USB cores that do not
+ * support DMA.
+ *
+ *
+ * <pre>
+ * MODIFICATION HISTORY:
+ *
+ * Ver Who Date Changes
+ * ----- ---- -------- ----------------------------------------------------------
+ * 1.00a wgr 10/10/10 First release
+ * 1.02a wgr 05/16/12 Removed comments as they are showing up in SDK
+ * Tabs for CR 657898
+ * 1.03a nm 09/21/12 Fixed CR#678977. Added proper sequence for setup packet
+ * handling.
+ * 1.04a nm 10/23/12 Fixed CR# 679106.
+ * 11/02/12 Fixed CR# 683931. Mult bits are set properly in dQH.
+ * 2.00a kpc 04/03/14 Fixed CR#777763. Corrected the setup tripwire macro val.
+ * 2.1 kpc 04/28/14 Removed unused function prototypes
+ * 2.2 kpc 08/23/14 Exported XUsbPs_DeviceReset API as global for calling in
+ * code coverage tests.
+ * 2.3 kpc 02/19/14 Fixed CR#873972, CR#873974. Corrected the logic for proper
+ * moving of dTD Head/Tail Pointers. Invalidate the cache
+ * after buffer receive in Endpoint Buffer Handler.
+ * 2.4 sg 04/26/16 Fixed CR#949693, Corrected the logic for EP flush
+ * ms 03/17/17 Added readme.txt file in examples folder for doxygen
+ * generation.
+ * ms 04/10/17 Modified filename tag to include the file in doxygen
+ * examples.
+ * </pre>
+ *
+ ******************************************************************************/
+
+#ifndef XUSBPS_H
+#define XUSBPS_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/***************************** Include Files *********************************/
+
+#include "xusbps_hw.h"
+#include "xil_types.h"
+#include "xstatus.h"
+
+/************************** Constant Definitions *****************************/
+
+/**
+ * @name System hang prevention Timeout counter value.
+ *
+ * This value is used throughout the code to initialize a Timeout counter that
+ * is used when hard polling a register. The ides is to initialize the Timeout
+ * counter to a value that is longer than any expected Timeout but short enough
+ * so the system will continue to work and report an error while the user is
+ * still paying attention. A reasonable Timeout time would be about 10 seconds.
+ * The XUSBPS_TIMEOUT_COUNTER value should be chosen so a polling loop would
+ * run about 10 seconds before a Timeout is detected. For example:
+ *
+ * int Timeout = XUSBPS_TIMEOUT_COUNTER;
+ * while ((XUsbPs_ReadReg(InstancePtr->Config.BaseAddress,
+ * XUSBPS_CMD_OFFSET) &
+ * XUSBPS_CMD_RST_MASK) && --Timeout) {
+ * ;
+ * }
+ * if (0 == Timeout) {
+ * return XST_FAILURE;
+ * }
+ *
+ */
+#define XUSBPS_TIMEOUT_COUNTER 1000000
+
+
+/**
+ * @name Endpoint Direction (bitmask)
+ * Definitions to be used with Endpoint related function that require a
+ * 'Direction' parameter.
+ *
+ * NOTE:
+ * The direction is always defined from the perspective of the HOST! This
+ * means that an IN endpoint on the controller is used for sending data while
+ * the OUT endpoint on the controller is used for receiving data.
+ * @{
+ */
+#define XUSBPS_EP_DIRECTION_IN 0x01 /**< Endpoint direction IN. */
+#define XUSBPS_EP_DIRECTION_OUT 0x02 /**< Endpoint direction OUT. */
+/* @} */
+
+
+/**
+ * @name Endpoint Type
+ * Definitions to be used with Endpoint related functions that require a 'Type'
+ * parameter.
+ * @{
+ */
+#define XUSBPS_EP_TYPE_NONE 0 /**< Endpoint is not used. */
+#define XUSBPS_EP_TYPE_CONTROL 1 /**< Endpoint for Control Transfers */
+#define XUSBPS_EP_TYPE_ISOCHRONOUS 2 /**< Endpoint for isochronous data */
+#define XUSBPS_EP_TYPE_BULK 3 /**< Endpoint for BULK Transfers. */
+#define XUSBPS_EP_TYPE_INTERRUPT 4 /**< Endpoint for interrupt Transfers */
+/* @} */
+
+/**
+ * Endpoint Max Packet Length in DeviceConfig is a coded value, ch9.6.6.
+ *
+ * @{
+ */
+#define ENDPOINT_MAXP_LENGTH 0x400
+#define ENDPOINT_MAXP_MULT_MASK 0xC00
+#define ENDPOINT_MAXP_MULT_SHIFT 10
+/* @} */
+
+/**
+ * @name Field names for status retrieval
+ * Definitions for the XUsbPs_GetStatus() function call 'StatusType'
+ * parameter.
+ * @{
+ */
+#define XUSBPS_EP_STS_ADDRESS 1 /**< Address of controller. */
+#define XUSBPS_EP_STS_CONTROLLER_STATE 2 /**< Current controller state. */
+/* @} */
+
+
+
+/**
+ * @name USB Default alternate setting
+ *
+ * @{
+ */
+#define XUSBPS_DEFAULT_ALT_SETTING 0 /**< The default alternate setting is 0 */
+/* @} */
+
+/**
+ * @name Endpoint event types
+ * Definitions that are used to identify events that occur on endpoints. Passed
+ * to the endpoint event handler functions registered with
+ * XUsbPs_EpSetHandler().
+ * @{
+ */
+#define XUSBPS_EP_EVENT_SETUP_DATA_RECEIVED 0x01
+ /**< Setup data has been received on the endpoint. */
+#define XUSBPS_EP_EVENT_DATA_RX 0x02
+ /**< Data frame has been received on the endpoint. */
+#define XUSBPS_EP_EVENT_DATA_TX 0x03
+ /**< Data frame has been sent on the endpoint. */
+/* @} */
+
+
+/*
+ * Maximum packet size for endpoint, 1024
+ * @{
+ */
+#define XUSBPS_MAX_PACKET_SIZE 1024
+ /**< Maximum value can be put into the queue head */
+/* @} */
+/**************************** Type Definitions *******************************/
+
+/******************************************************************************
+ * This data type defines the callback function to be used for Endpoint
+ * handlers.
+ *
+ * @param CallBackRef is the Callback reference passed in by the upper
+ * layer when setting the handler, and is passed back to the upper
+ * layer when the handler is called.
+ * @param EpNum is the Number of the endpoint that caused the event.
+ * @param EventType is the type of the event that occurred on the endpoint.
+ * @param Data is a pointer to user data pointer specified when callback
+ * was registered.
+ */
+typedef void (*XUsbPs_EpHandlerFunc)(void *CallBackRef,
+ u8 EpNum, u8 EventType, void *Data);
+
+
+/******************************************************************************
+ * This data type defines the callback function to be used for the general
+ * interrupt handler.
+ *
+ * @param CallBackRef is the Callback reference passed in by the upper
+ * layer when setting the handler, and is passed back to the upper
+ * layer when the handler is called.
+ * @param IrqMask is the Content of the interrupt status register. This
+ * value can be used by the callback function to distinguish the
+ * individual interrupt types.
+ */
+typedef void (*XUsbPs_IntrHandlerFunc)(void *CallBackRef, u32 IrqMask);
+
+
+/******************************************************************************/
+
+/* The following type definitions are used for referencing Queue Heads and
+ * Transfer Descriptors. The structures themselves are not used, however, the
+ * types are used in the API to avoid using (void *) pointers.
+ */
+typedef u8 XUsbPs_dQH[XUSBPS_dQH_ALIGN];
+typedef u8 XUsbPs_dTD[XUSBPS_dTD_ALIGN];
+
+
+/**
+ * The following data structures are used internally by the L0/L1 driver.
+ * Their contents MUST NOT be changed by the upper layers.
+ */
+
+/**
+ * The following data structure represents OUT endpoint.
+ */
+typedef struct {
+ XUsbPs_dQH *dQH;
+ /**< Pointer to the Queue Head structure of the endpoint. */
+
+ XUsbPs_dTD *dTDs;
+ /**< Pointer to the first dTD of the dTD list for this
+ * endpoint. */
+
+ XUsbPs_dTD *dTDCurr;
+ /**< Buffer to the currently processed descriptor. */
+
+ u8 *dTDBufs;
+ /**< Pointer to the first buffer of the buffer list for this
+ * endpoint. */
+
+ XUsbPs_EpHandlerFunc HandlerFunc;
+ /**< Handler function for this endpoint. */
+ void *HandlerRef;
+ /**< User data reference for the handler. */
+} XUsbPs_EpOut;
+
+
+/**
+ * The following data structure represents IN endpoint.
+ */
+typedef struct {
+ XUsbPs_dQH *dQH;
+ /**< Pointer to the Queue Head structure of the endpoint. */
+
+ XUsbPs_dTD *dTDs;
+ /**< List of pointers to the Transfer Descriptors of the
+ * endpoint. */
+
+ XUsbPs_dTD *dTDHead;
+ /**< Buffer to the next available descriptor in the list. */
+
+ XUsbPs_dTD *dTDTail;
+ /**< Buffer to the last unsent descriptor in the list*/
+
+ XUsbPs_EpHandlerFunc HandlerFunc;
+ /**< Handler function for this endpoint. */
+ void *HandlerRef;
+ /**< User data reference for the handler. */
+} XUsbPs_EpIn;
+
+
+/**
+ * The following data structure represents an endpoint used internally
+ * by the L0/L1 driver.
+ */
+typedef struct {
+ /* Each endpoint has an OUT and an IN component.
+ */
+ XUsbPs_EpOut Out; /**< OUT endpoint structure */
+ XUsbPs_EpIn In; /**< IN endpoint structure */
+} XUsbPs_Endpoint;
+
+
+
+/**
+ * The following structure is used by the user to receive Setup Data from an
+ * endpoint. Using this structure simplifies the process of interpreting the
+ * setup data in the core's data fields.
+ *
+ * The naming scheme for the members of this structure is different from the
+ * naming scheme found elsewhere in the code. The members of this structure are
+ * defined in the Chapter 9 USB reference guide. Using this naming scheme makes
+ * it easier for people familiar with the standard to read the code.
+ */
+typedef struct {
+ u8 bmRequestType; /**< bmRequestType in setup data */
+ u8 bRequest; /**< bRequest in setup data */
+ u16 wValue; /**< wValue in setup data */
+ u16 wIndex; /**< wIndex in setup data */
+ u16 wLength; /**< wLength in setup data */
+}
+XUsbPs_SetupData;
+
+
+/**
+ * Data structures used to configure endpoints.
+ */
+typedef struct {
+ u32 Type;
+ /**< Endpoint type:
+ - XUSBPS_EP_TYPE_CONTROL
+ - XUSBPS_EP_TYPE_ISOCHRONOUS
+ - XUSBPS_EP_TYPE_BULK
+ - XUSBPS_EP_TYPE_INTERRUPT */
+
+ u32 NumBufs;
+ /**< Number of buffers to be handled by this endpoint. */
+ u32 BufSize;
+ /**< Buffer size. Only relevant for OUT (receive) Endpoints. */
+
+ u16 MaxPacketSize;
+ /**< Maximum packet size for this endpoint. This number will
+ * define the maximum number of bytes sent on the wire per
+ * transaction. Range: 0..1024 */
+} XUsbPs_EpSetup;
+
+
+/**
+ * Endpoint configuration structure.
+ */
+typedef struct {
+ XUsbPs_EpSetup Out; /**< OUT component of endpoint. */
+ XUsbPs_EpSetup In; /**< IN component of endpoint. */
+} XUsbPs_EpConfig;
+
+
+/**
+ * The XUsbPs_DeviceConfig structure contains the configuration information to
+ * configure the USB controller for DEVICE mode. This data structure is used
+ * with the XUsbPs_ConfigureDevice() function call.
+ */
+typedef struct {
+ u8 NumEndpoints; /**< Number of Endpoints for the controller.
+ This number depends on the runtime
+ configuration of driver. The driver may
+ configure fewer endpoints than are available
+ in the core. */
+
+ XUsbPs_EpConfig EpCfg[XUSBPS_MAX_ENDPOINTS];
+ /**< List of endpoint configurations. */
+
+
+ u32 DMAMemPhys; /**< Physical base address of DMAable memory
+ allocated for the driver. */
+
+ /* The following members are used internally by the L0/L1 driver. They
+ * MUST NOT be accesses and/or modified in any way by the upper layers.
+ *
+ * The reason for having these members is that we generally try to
+ * avoid allocating memory in the L0/L1 driver as we want to be OS
+ * independent. In order to avoid allocating memory for this data
+ * structure wihin L0/L1 we put it into the XUsbPs_DeviceConfig
+ * structure which is allocated by the caller.
+ */
+ XUsbPs_Endpoint Ep[XUSBPS_MAX_ENDPOINTS];
+ /**< List of endpoint metadata structures. */
+
+ u32 PhysAligned; /**< 64 byte aligned base address of the DMA
+ memory block. Will be computed and set by
+ the L0/L1 driver. */
+} XUsbPs_DeviceConfig;
+
+
+/**
+ * The XUsbPs_Config structure contains configuration information for the USB
+ * controller.
+ *
+ * This structure only contains the basic configuration for the controller. The
+ * caller also needs to initialize the controller for the DEVICE mode
+ * using the XUsbPs_DeviceConfig data structures with the
+ * XUsbPs_ConfigureDevice() function call
+ */
+typedef struct {
+ u16 DeviceID; /**< Unique ID of controller. */
+ u32 BaseAddress; /**< Core register base address. */
+} XUsbPs_Config;
+
+
+/**
+ * The XUsbPs driver instance data. The user is required to allocate a
+ * variable of this type for every USB controller in the system. A pointer to a
+ * variable of this type is then passed to the driver API functions.
+ */
+typedef struct {
+ XUsbPs_Config Config; /**< Configuration structure */
+
+ int CurrentAltSetting; /**< Current alternative setting of interface */
+
+ void *UserDataPtr; /**< Data pointer to be used by upper layers to
+ store application dependent data structures.
+ The upper layers are responsible to allocated
+ and free the memory. The driver will not
+ mofidy this data pointer. */
+
+ /**
+ * The following structures hold the configuration for DEVICE mode
+ * of the controller. They are initialized using the
+ * XUsbPs_ConfigureDevice() function call.
+ */
+ XUsbPs_DeviceConfig DeviceConfig;
+ /**< Configuration for the DEVICE mode. */
+
+ XUsbPs_IntrHandlerFunc HandlerFunc;
+ /**< Handler function for the controller. */
+ void *HandlerRef;
+ /**< User data reference for the handler. */
+ u32 HandlerMask;
+ /**< User interrupt mask. Defines which interrupts will cause
+ * the callback to be called. */
+} XUsbPs;
+
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/******************************************************************************
+ *
+ * USB CONTROLLER RELATED MACROS
+ *
+ ******************************************************************************/
+/*****************************************************************************/
+/**
+ * This macro returns the current frame number.
+ *
+ * @param InstancePtr is a pointer to the XUsbPs instance of the
+ * controller.
+ *
+ * @return The current frame number.
+ *
+ * @note C-style signature:
+ * u32 XUsbPs_GetFrameNum(const XUsbPs *InstancePtr)
+ *
+ ******************************************************************************/
+#define XUsbPs_GetFrameNum(InstancePtr) \
+ XUsbPs_ReadReg((InstancePtr)->Config.BaseAddress, XUSBPS_FRAME_OFFSET)
+
+
+/*****************************************************************************/
+/**
+ * This macro starts the USB engine.
+ *
+ * @param InstancePtr is a pointer to the XUsbPs instance of the
+ * controller.
+ *
+ * @note C-style signature:
+ * void XUsbPs_Start(XUsbPs *InstancePtr)
+ *
+ ******************************************************************************/
+#define XUsbPs_Start(InstancePtr) \
+ XUsbPs_SetBits(InstancePtr, XUSBPS_CMD_OFFSET, XUSBPS_CMD_RS_MASK)
+
+
+/*****************************************************************************/
+/**
+ * This macro stops the USB engine.
+ *
+ * @param InstancePtr is a pointer to the XUsbPs instance of the
+ * controller.
+ *
+ * @note C-style signature:
+ * void XUsbPs_Stop(XUsbPs *InstancePtr)
+ *
+ ******************************************************************************/
+#define XUsbPs_Stop(InstancePtr) \
+ XUsbPs_ClrBits(InstancePtr, XUSBPS_CMD_OFFSET, XUSBPS_CMD_RS_MASK)
+
+
+/*****************************************************************************/
+/**
+ * This macro forces the USB engine to be in Full Speed (FS) mode.
+ *
+ * @param InstancePtr is a pointer to the XUsbPs instance of the
+ * controller.
+ *
+ * @note C-style signature:
+ * void XUsbPs_ForceFS(XUsbPs *InstancePtr)
+ *
+ ******************************************************************************/
+#define XUsbPs_ForceFS(InstancePtr) \
+ XUsbPs_SetBits(InstancePtr, XUSBPS_PORTSCR1_OFFSET, \
+ XUSBPS_PORTSCR_PFSC_MASK)
+
+
+/*****************************************************************************/
+/**
+ * This macro starts the USB Timer 0, with repeat option for period of
+ * one second.
+ *
+ * @param InstancePtr is a pointer to XUsbPs instance of the controller.
+ * @param Interval is the interval for Timer0 to generate an interrupt
+ *
+ * @note C-style signature:
+ * void XUsbPs_StartTimer0(XUsbPs *InstancePtr, u32 Interval)
+ *
+ ******************************************************************************/
+#define XUsbPs_StartTimer0(InstancePtr, Interval) \
+{ \
+ XUsbPs_WriteReg((InstancePtr)->Config.BaseAddress, \
+ XUSBPS_TIMER0_LD_OFFSET, (Interval)); \
+ XUsbPs_SetBits(InstancePtr, XUSBPS_TIMER0_CTL_OFFSET, \
+ XUSBPS_TIMER_RUN_MASK | \
+ XUSBPS_TIMER_RESET_MASK | \
+ XUSBPS_TIMER_REPEAT_MASK); \
+} \
+
+
+/*****************************************************************************/
+/**
+* This macro stops Timer 0.
+*
+* @param InstancePtr is a pointer to XUsbPs instance of the controller.
+*
+* @note C-style signature:
+* void XUsbPs_StopTimer0(XUsbPs *InstancePtr)
+*
+******************************************************************************/
+#define XUsbPs_StopTimer0(InstancePtr) \
+ XUsbPs_ClrBits(InstancePtr, XUSBPS_TIMER0_CTL_OFFSET, \
+ XUSBPS_TIMER_RUN_MASK)
+
+
+/*****************************************************************************/
+/**
+* This macro reads Timer 0.
+*
+* @param InstancePtr is a pointer to XUsbPs instance of the controller.
+*
+* @note C-style signature:
+* void XUsbPs_ReadTimer0(XUsbPs *InstancePtr)
+*
+******************************************************************************/
+#define XUsbPs_ReadTimer0(InstancePtr) \
+ XUsbPs_ReadReg((InstancePtr)->Config.BaseAddress, \
+ XUSBPS_TIMER0_CTL_OFFSET) & \
+ XUSBPS_TIMER_COUNTER_MASK
+
+
+/*****************************************************************************/
+/**
+* This macro force remote wakeup on host
+*
+* @param InstancePtr is a pointer to XUsbPs instance of the controller.
+*
+* @note C-style signature:
+* void XUsbPs_RemoteWakeup(XUsbPs *InstancePtr)
+*
+******************************************************************************/
+#define XUsbPs_RemoteWakeup(InstancePtr) \
+ XUsbPs_SetBits(InstancePtr, XUSBPS_PORTSCR1_OFFSET, \
+ XUSBPS_PORTSCR_FPR_MASK)
+
+
+/******************************************************************************
+ *
+ * ENDPOINT RELATED MACROS
+ *
+ ******************************************************************************/
+/*****************************************************************************/
+/**
+* This macro enables the given endpoint for the given direction.
+*
+* @param InstancePtr is a pointer to the XUsbPs instance of the
+* controller.
+* @param EpNum is number of the endpoint to enable.
+* @param Dir is direction of the endpoint (bitfield):
+* - XUSBPS_EP_DIRECTION_OUT
+* - XUSBPS_EP_DIRECTION_IN
+*
+* @note C-style signature:
+* void XUsbPs_EpEnable(XUsbPs *InstancePtr, u8 EpNum, u8 Dir)
+*
+******************************************************************************/
+#define XUsbPs_EpEnable(InstancePtr, EpNum, Dir) \
+ XUsbPs_SetBits(InstancePtr, XUSBPS_EPCRn_OFFSET(EpNum), \
+ ((Dir) & XUSBPS_EP_DIRECTION_OUT ? XUSBPS_EPCR_RXE_MASK : 0) | \
+ ((Dir) & XUSBPS_EP_DIRECTION_IN ? XUSBPS_EPCR_TXE_MASK : 0))
+
+
+/*****************************************************************************/
+/**
+* This macro disables the given endpoint for the given direction.
+*
+* @param InstancePtr is a pointer to the XUsbPs instance of the
+* controller.
+* @param EpNum is the number of the endpoint to disable.
+* @param Dir is the direction of the endpoint (bitfield):
+* - XUSBPS_EP_DIRECTION_OUT
+* - XUSBPS_EP_DIRECTION_IN
+*
+* @note C-style signature:
+* void XUsbPs_EpDisable(XUsbPs *InstancePtr, u8 EpNum, u8 Dir)
+*
+******************************************************************************/
+#define XUsbPs_EpDisable(InstancePtr, EpNum, Dir) \
+ XUsbPs_ClrBits(InstancePtr, XUSBPS_EPCRn_OFFSET(EpNum), \
+ ((Dir) & XUSBPS_EP_DIRECTION_OUT ? XUSBPS_EPCR_RXE_MASK : 0) | \
+ ((Dir) & XUSBPS_EP_DIRECTION_IN ? XUSBPS_EPCR_TXE_MASK : 0))
+
+
+/*****************************************************************************/
+/**
+* This macro stalls the given endpoint for the given direction, and flush
+* the buffers.
+*
+* @param InstancePtr is a pointer to the XUsbPs instance of the
+* controller.
+* @param EpNum is number of the endpoint to stall.
+* @param Dir is the direction of the endpoint (bitfield):
+* - XUSBPS_EP_DIRECTION_OUT
+* - XUSBPS_EP_DIRECTION_IN
+*
+* @note C-style signature:
+* void XUsbPs_EpStall(XUsbPs *InstancePtr, u8 EpNum, u8 Dir)
+*
+******************************************************************************/
+#define XUsbPs_EpStall(InstancePtr, EpNum, Dir) \
+ XUsbPs_SetBits(InstancePtr, XUSBPS_EPCRn_OFFSET(EpNum), \
+ ((Dir) & XUSBPS_EP_DIRECTION_OUT ? XUSBPS_EPCR_RXS_MASK : 0) | \
+ ((Dir) & XUSBPS_EP_DIRECTION_IN ? XUSBPS_EPCR_TXS_MASK : 0))
+
+
+/*****************************************************************************/
+/**
+* This macro unstalls the given endpoint for the given direction.
+*
+* @param InstancePtr is a pointer to the XUsbPs instance of the
+* controller.
+* @param EpNum is the Number of the endpoint to unstall.
+* @param Dir is the Direction of the endpoint (bitfield):
+* - XUSBPS_EP_DIRECTION_OUT
+* - XUSBPS_EP_DIRECTION_IN
+*
+* @note C-style signature:
+* void XUsbPs_EpUnStall(XUsbPs *InstancePtr, u8 EpNum, u8 Dir)
+*
+******************************************************************************/
+#define XUsbPs_EpUnStall(InstancePtr, EpNum, Dir) \
+ XUsbPs_ClrBits(InstancePtr, XUSBPS_EPCRn_OFFSET(EpNum), \
+ ((Dir) & XUSBPS_EP_DIRECTION_OUT ? XUSBPS_EPCR_RXS_MASK : 0) | \
+ ((Dir) & XUSBPS_EP_DIRECTION_IN ? XUSBPS_EPCR_TXS_MASK : 0))
+
+
+/*****************************************************************************/
+/**
+* This macro flush an endpoint upon interface disable
+*
+* @param InstancePtr is a pointer to the XUsbPs instance of the
+* controller.
+* @param EpNum is the number of the endpoint to flush.
+* @param Dir is the direction of the endpoint (bitfield):
+* - XUSBPS_EP_DIRECTION_OUT
+* - XUSBPS_EP_DIRECTION_IN
+*
+* @note C-style signature:
+* void XUsbPs_EpFlush(XUsbPs *InstancePtr, u8 EpNum, u8 Dir)
+*
+******************************************************************************/
+#define XUsbPs_EpFlush(InstancePtr, EpNum, Dir) \
+ XUsbPs_SetBits(InstancePtr, XUSBPS_EPFLUSH_OFFSET, \
+ 1 << (EpNum + ((Dir) & XUSBPS_EP_DIRECTION_OUT ? \
+ XUSBPS_EPFLUSH_RX_SHIFT:XUSBPS_EPFLUSH_TX_SHIFT))) \
+
+/*****************************************************************************/
+/**
+* This macro enables the interrupts defined by the bit mask.
+*
+* @param InstancePtr is a pointer to XUsbPs instance of the controller.
+* @param IntrMask is the Bit mask of interrupts to be enabled.
+*
+* @note C-style signature:
+* void XUsbPs_IntrEnable(XUsbPs *InstancePtr, u32 IntrMask)
+*
+******************************************************************************/
+#define XUsbPs_IntrEnable(InstancePtr, IntrMask) \
+ XUsbPs_SetBits(InstancePtr, XUSBPS_IER_OFFSET, IntrMask)
+
+
+/*****************************************************************************/
+/**
+* This function disables the interrupts defined by the bit mask.
+*
+*
+* @param InstancePtr is a pointer to XUsbPs instance of the controller.
+* @param IntrMask is a Bit mask of interrupts to be disabled.
+*
+* @note C-style signature:
+* void XUsbPs_IntrDisable(XUsbPs *InstancePtr, u32 IntrMask)
+*
+******************************************************************************/
+#define XUsbPs_IntrDisable(InstancePtr, IntrMask) \
+ XUsbPs_ClrBits(InstancePtr, XUSBPS_IER_OFFSET, IntrMask)
+
+
+/*****************************************************************************/
+/**
+* This macro enables the endpoint NAK interrupts defined by the bit mask.
+*
+* @param InstancePtr is a pointer to XUsbPs instance of the controller.
+* @param NakIntrMask is the Bit mask of endpoint NAK interrupts to be
+* enabled.
+* @note C-style signature:
+* void XUsbPs_NakIntrEnable(XUsbPs *InstancePtr, u32 NakIntrMask)
+*
+******************************************************************************/
+#define XUsbPs_NakIntrEnable(InstancePtr, NakIntrMask) \
+ XUsbPs_SetBits(InstancePtr, XUSBPS_EPNAKIER_OFFSET, NakIntrMask)
+
+
+/*****************************************************************************/
+/**
+* This macro disables the endpoint NAK interrupts defined by the bit mask.
+*
+* @param InstancePtr is a pointer to XUsbPs instance of the controller.
+* @param NakIntrMask is a Bit mask of endpoint NAK interrupts to be
+* disabled.
+*
+* @note
+* C-style signature:
+* void XUsbPs_NakIntrDisable(XUsbPs *InstancePtr, u32 NakIntrMask)
+*
+******************************************************************************/
+#define XUsbPs_NakIntrDisable(InstancePtr, NakIntrMask) \
+ XUsbPs_ClrBits(InstancePtr, XUSBPS_EPNAKIER_OFFSET, NakIntrMask)
+
+
+/*****************************************************************************/
+/**
+* This function clears the endpoint NAK interrupts status defined by the
+* bit mask.
+*
+* @param InstancePtr is a pointer to XUsbPs instance of the controller.
+* @param NakIntrMask is the Bit mask of endpoint NAK interrupts to be cleared.
+*
+* @note C-style signature:
+* void XUsbPs_NakIntrClear(XUsbPs *InstancePtr, u32 NakIntrMask)
+*
+******************************************************************************/
+#define XUsbPs_NakIntrClear(InstancePtr, NakIntrMask) \
+ XUsbPs_WriteReg((InstancePtr)->Config.BaseAddress, \
+ XUSBPS_EPNAKISR_OFFSET, NakIntrMask)
+
+
+
+/*****************************************************************************/
+/**
+* This macro sets the Interrupt Threshold value in the control register
+*
+* @param InstancePtr is a pointer to XUsbPs instance of the controller.
+* @param Threshold is the Interrupt threshold to be set.
+* Allowed values:
+* - XUSBPS_CMD_ITHRESHOLD_0 - Immediate interrupt
+* - XUSBPS_CMD_ITHRESHOLD_1 - 1 Frame
+* - XUSBPS_CMD_ITHRESHOLD_2 - 2 Frames
+* - XUSBPS_CMD_ITHRESHOLD_4 - 4 Frames
+* - XUSBPS_CMD_ITHRESHOLD_8 - 8 Frames
+* - XUSBPS_CMD_ITHRESHOLD_16 - 16 Frames
+* - XUSBPS_CMD_ITHRESHOLD_32 - 32 Frames
+* - XUSBPS_CMD_ITHRESHOLD_64 - 64 Frames
+*
+* @note
+* C-style signature:
+* void XUsbPs_SetIntrThreshold(XUsbPs *InstancePtr, u8 Threshold)
+*
+******************************************************************************/
+#define XUsbPs_SetIntrThreshold(InstancePtr, Threshold) \
+ XUsbPs_WriteReg((InstancePtr)->Config.BaseAddress, \
+ XUSBPS_CMD_OFFSET, (Threshold))\
+
+
+/*****************************************************************************/
+/**
+* This macro sets the Tripwire bit in the USB command register.
+*
+* @param InstancePtr is a pointer to XUsbPs instance of the controller.
+*
+* @note C-style signature:
+* void XUsbPs_SetTripwire(XUsbPs *InstancePtr)
+*
+******************************************************************************/
+#define XUsbPs_SetSetupTripwire(InstancePtr) \
+ XUsbPs_SetBits(InstancePtr, XUSBPS_CMD_OFFSET, \
+ XUSBPS_CMD_SUTW_MASK)
+
+
+/*****************************************************************************/
+/**
+* This macro clears the Tripwire bit in the USB command register.
+*
+* @param InstancePtr is a pointer to XUsbPs instance of the controller.
+*
+* @note C-style signature:
+* void XUsbPs_ClrTripwire(XUsbPs *InstancePtr)
+*
+******************************************************************************/
+#define XUsbPs_ClrSetupTripwire(InstancePtr) \
+ XUsbPs_ClrBits(InstancePtr, XUSBPS_CMD_OFFSET, \
+ XUSBPS_CMD_SUTW_MASK)
+
+
+/*****************************************************************************/
+/**
+* This macro checks if the Tripwire bit in the USB command register is set.
+*
+* @param InstancePtr is a pointer to XUsbPs instance of the controller.
+*
+* @return
+* - TRUE: The tripwire bit is still set.
+* - FALSE: The tripwire bit has been cleared.
+*
+* @note C-style signature:
+* int XUsbPs_TripwireIsSet(XUsbPs *InstancePtr)
+*
+******************************************************************************/
+#define XUsbPs_SetupTripwireIsSet(InstancePtr) \
+ (XUsbPs_ReadReg((InstancePtr)->Config.BaseAddress, \
+ XUSBPS_CMD_OFFSET) & \
+ XUSBPS_CMD_SUTW_MASK ? TRUE : FALSE)
+
+
+/******************************************************************************
+*
+* GENERAL REGISTER / BIT MANIPULATION MACROS
+*
+******************************************************************************/
+/****************************************************************************/
+/**
+* This macro sets the given bit mask in the register.
+*
+* @param InstancePtr is a pointer to XUsbPs instance of the controller.
+* @param RegOffset is the register offset to be written.
+* @param Bits is the Bits to be set in the register
+*
+* @return None.
+*
+* @note C-style signature:
+* void XUsbPs_SetBits(u32 BaseAddress, u32 RegOffset, u32 Bits)
+*
+*****************************************************************************/
+#define XUsbPs_SetBits(InstancePtr, RegOffset, Bits) \
+ XUsbPs_WriteReg((InstancePtr)->Config.BaseAddress, RegOffset, \
+ XUsbPs_ReadReg((InstancePtr)->Config.BaseAddress, \
+ RegOffset) | (Bits));
+
+
+/****************************************************************************/
+/**
+*
+* This macro clears the given bits in the register.
+*
+* @param InstancePtr is a pointer to XUsbPs instance of the controller.
+* @param RegOffset is the register offset to be written.
+* @param Bits are the bits to be cleared in the register
+*
+* @return None.
+*
+* @note
+* C-style signature:
+* void XUsbPs_ClrBits(u32 BaseAddress, u32 RegOffset, u32 Bits)
+*
+*****************************************************************************/
+#define XUsbPs_ClrBits(InstancePtr, RegOffset, Bits) \
+ XUsbPs_WriteReg((InstancePtr)->Config.BaseAddress, RegOffset, \
+ XUsbPs_ReadReg((InstancePtr)->Config.BaseAddress, \
+ RegOffset) & ~(Bits));
+
+
+/************************** Function Prototypes ******************************/
+
+/**
+ * Setup / Initialize functions.
+ *
+ * Implemented in file xusbps.c
+ */
+int XUsbPs_CfgInitialize(XUsbPs *InstancePtr,
+ const XUsbPs_Config *ConfigPtr, u32 BaseAddress);
+
+int XUsbPs_ConfigureDevice(XUsbPs *InstancePtr,
+ const XUsbPs_DeviceConfig *CfgPtr);
+
+/**
+ * Common functions used for DEVICE/HOST mode.
+ */
+int XUsbPs_Reset(XUsbPs *InstancePtr);
+
+void XUsbPs_DeviceReset(XUsbPs *InstancePtr);
+
+/**
+ * DEVICE mode specific functions.
+ */
+int XUsbPs_BusReset(XUsbPs *InstancePtr);
+int XUsbPs_SetDeviceAddress(XUsbPs *InstancePtr, u8 Address);
+
+
+/**
+ * Handling Suspend and Resume.
+ *
+ * Implemented in xusbps.c
+ */
+int XUsbPs_Suspend(const XUsbPs *InstancePtr);
+int XUsbPs_Resume(const XUsbPs *InstancePtr);
+int XUsbPs_RequestHostResume(const XUsbPs *InstancePtr);
+
+
+/*
+ * Functions for managing Endpoints / Transfers
+ *
+ * Implemented in file xusbps_endpoint.c
+ */
+int XUsbPs_EpBufferSend(XUsbPs *InstancePtr, u8 EpNum,
+ const u8 *BufferPtr, u32 BufferLen);
+int XUsbPs_EpBufferSendWithZLT(XUsbPs *InstancePtr, u8 EpNum,
+ const u8 *BufferPtr, u32 BufferLen);
+int XUsbPs_EpBufferReceive(XUsbPs *InstancePtr, u8 EpNum,
+ u8 **BufferPtr, u32 *BufferLenPtr, u32 *Handle);
+void XUsbPs_EpBufferRelease(u32 Handle);
+
+int XUsbPs_EpSetHandler(XUsbPs *InstancePtr, u8 EpNum, u8 Direction,
+ XUsbPs_EpHandlerFunc CallBackFunc,
+ void *CallBackRef);
+int XUsbPs_EpGetSetupData(XUsbPs *InstancePtr, int EpNum,
+ XUsbPs_SetupData *SetupDataPtr);
+
+int XUsbPs_EpPrime(XUsbPs *InstancePtr, u8 EpNum, u8 Direction);
+
+int XUsbPs_ReconfigureEp(XUsbPs *InstancePtr, XUsbPs_DeviceConfig *CfgPtr,
+ int EpNum, unsigned short NewDirection, int DirectionChanged);
+
+/*
+ * Interrupt handling functions
+ *
+ * Implemented in file xusbps_intr.c
+ */
+void XUsbPs_IntrHandler(void *InstancePtr);
+
+int XUsbPs_IntrSetHandler(XUsbPs *InstancePtr,
+ XUsbPs_IntrHandlerFunc CallBackFunc,
+ void *CallBackRef, u32 Mask);
+/*
+ * Helper functions for static configuration.
+ * Implemented in xusbps_sinit.c
+ */
+XUsbPs_Config *XUsbPs_LookupConfig(u16 DeviceId);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* XUSBPS_H */
+/** @} */
diff --git a/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/include/xusbps_endpoint.h b/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/include/xusbps_endpoint.h
new file mode 100644
index 0000000..0455b70
--- /dev/null
+++ b/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/include/xusbps_endpoint.h
@@ -0,0 +1,509 @@
+/******************************************************************************
+*
+* Copyright (C) 2010 - 2015 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+* THE SOFTWARE.
+*
+*
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+ *
+ * @file xusbps_endpoint.h
+* @addtogroup usbps_v2_4
+* @{
+ *
+ * This is an internal file containung the definitions for endpoints. It is
+ * included by the xusbps_endpoint.c which is implementing the endpoint
+ * functions and by xusbps_intr.c.
+ *
+ * <pre>
+ * MODIFICATION HISTORY:
+ *
+ * Ver Who Date Changes
+ * ----- ---- -------- --------------------------------------------------------
+ * 1.00a wgr 10/10/10 First release
+ * </pre>
+ *
+ ******************************************************************************/
+#ifndef XUSBPS_ENDPOINT_H
+#define XUSBPS_ENDPOINT_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/***************************** Include Files *********************************/
+
+#include "xil_cache.h"
+#include "xusbps.h"
+#include "xil_types.h"
+
+/**************************** Type Definitions *******************************/
+
+/************************** Constant Definitions *****************************/
+
+
+/**
+ * Endpoint Device Transfer Descriptor
+ *
+ * The dTD describes to the device controller the location and quantity of data
+ * to be sent/received for given transfer. The driver does not attempt to
+ * modify any field in an active dTD except the Next Link Pointer.
+ */
+#define XUSBPS_dTDNLP 0x00 /**< Pointer to the next descriptor */
+#define XUSBPS_dTDTOKEN 0x04 /**< Descriptor Token */
+#define XUSBPS_dTDBPTR0 0x08 /**< Buffer Pointer 0 */
+#define XUSBPS_dTDBPTR1 0x0C /**< Buffer Pointer 1 */
+#define XUSBPS_dTDBPTR2 0x10 /**< Buffer Pointer 2 */
+#define XUSBPS_dTDBPTR3 0x14 /**< Buffer Pointer 3 */
+#define XUSBPS_dTDBPTR4 0x18 /**< Buffer Pointer 4 */
+#define XUSBPS_dTDBPTR(n) (XUSBPS_dTDBPTR0 + (n) * 0x04)
+#define XUSBPS_dTDRSRVD 0x1C /**< Reserved field */
+
+/* We use the reserved field in the dTD to store user data. */
+#define XUSBPS_dTDUSERDATA XUSBPS_dTDRSRVD /**< Reserved field */
+
+
+/** @name dTD Next Link Pointer (dTDNLP) bit positions.
+ * @{
+ */
+#define XUSBPS_dTDNLP_T_MASK 0x00000001
+ /**< USB dTD Next Link Pointer Terminate Bit */
+#define XUSBPS_dTDNLP_ADDR_MASK 0xFFFFFFE0
+ /**< USB dTD Next Link Pointer Address [31:5] */
+/* @} */
+
+
+/** @name dTD Token (dTDTOKEN) bit positions.
+ * @{
+ */
+#define XUSBPS_dTDTOKEN_XERR_MASK 0x00000008 /**< dTD Transaction Error */
+#define XUSBPS_dTDTOKEN_BUFERR_MASK 0x00000020 /**< dTD Data Buffer Error */
+#define XUSBPS_dTDTOKEN_HALT_MASK 0x00000040 /**< dTD Halted Flag */
+#define XUSBPS_dTDTOKEN_ACTIVE_MASK 0x00000080 /**< dTD Active Bit */
+#define XUSBPS_dTDTOKEN_MULTO_MASK 0x00000C00 /**< Multiplier Override Field [1:0] */
+#define XUSBPS_dTDTOKEN_IOC_MASK 0x00008000 /**< Interrupt on Complete Bit */
+#define XUSBPS_dTDTOKEN_LEN_MASK 0x7FFF0000 /**< Transfer Length Field */
+/* @} */
+
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/*****************************************************************************/
+/**
+ *
+ * IMPORTANT NOTE:
+ * ===============
+ *
+ * Many of the following macros modify Device Queue Head (dQH) data structures
+ * and Device Transfer Descriptor (dTD) data structures. Those structures can
+ * potentially reside in CACHED memory. Therefore, it's the callers
+ * responsibility to ensure cache coherency by using provided
+ *
+ * XUsbPs_dQHInvalidateCache()
+ * XUsbPs_dQHFlushCache()
+ * XUsbPs_dTDInvalidateCache()
+ * XUsbPs_dTDFlushCache()
+ *
+ * function calls.
+ *
+ ******************************************************************************/
+#define XUsbPs_dTDInvalidateCache(dTDPtr) \
+ Xil_DCacheInvalidateRange((unsigned int)dTDPtr, sizeof(XUsbPs_dTD))
+
+#define XUsbPs_dTDFlushCache(dTDPtr) \
+ Xil_DCacheFlushRange((unsigned int)dTDPtr, sizeof(XUsbPs_dTD))
+
+#define XUsbPs_dQHInvalidateCache(dQHPtr) \
+ Xil_DCacheInvalidateRange((unsigned int)dQHPtr, sizeof(XUsbPs_dQH))
+
+#define XUsbPs_dQHFlushCache(dQHPtr) \
+ Xil_DCacheFlushRange((unsigned int)dQHPtr, sizeof(XUsbPs_dQH))
+
+/*****************************************************************************/
+/**
+ *
+ * This macro sets the Transfer Length for the given Transfer Descriptor.
+ *
+ * @param dTDPtr is pointer to the dTD element.
+ * @param Len is the length to be set. Range: 0..16384
+ *
+ * @note C-style signature:
+ * void XUsbPs_dTDSetTransferLen(u32 dTDPtr, u32 Len)
+ *
+ ******************************************************************************/
+#define XUsbPs_dTDSetTransferLen(dTDPtr, Len) \
+ XUsbPs_WritedTD(dTDPtr, XUSBPS_dTDTOKEN, \
+ (XUsbPs_ReaddTD(dTDPtr, XUSBPS_dTDTOKEN) & \
+ ~XUSBPS_dTDTOKEN_LEN_MASK) | ((Len) << 16))
+
+
+/*****************************************************************************/
+/**
+ *
+ * This macro gets the Next Link pointer of the given Transfer Descriptor.
+ *
+ * @param dTDPtr is pointer to the dTD element.
+ *
+ * @return TransferLength field of the descriptor.
+ *
+ * @note C-style signature:
+ * u32 XUsbPs_dTDGetTransferLen(u32 dTDPtr)
+ *
+ ******************************************************************************/
+#define XUsbPs_dTDGetNLP(dTDPtr) \
+ (XUsbPs_dTD *) ((XUsbPs_ReaddTD(dTDPtr, XUSBPS_dTDNLP)\
+ & XUSBPS_dTDNLP_ADDR_MASK))
+
+
+/*****************************************************************************/
+/**
+ *
+ * This macro sets the Next Link pointer of the given Transfer Descriptor.
+ *
+ * @param dTDPtr is a pointer to the dTD element.
+ * @param NLP is the Next Link Pointer
+ *
+ * @note C-style signature:
+ * void XUsbPs_dTDSetTransferLen(u32 dTDPtr, u32 Len)
+ *
+ ******************************************************************************/
+#define XUsbPs_dTDSetNLP(dTDPtr, NLP) \
+ XUsbPs_WritedTD(dTDPtr, XUSBPS_dTDNLP, \
+ (XUsbPs_ReaddTD(dTDPtr, XUSBPS_dTDNLP) & \
+ ~XUSBPS_dTDNLP_ADDR_MASK) | \
+ ((NLP) & XUSBPS_dTDNLP_ADDR_MASK))
+
+
+/*****************************************************************************/
+/**
+ *
+ * This macro gets the Transfer Length for the given Transfer Descriptor.
+ *
+ * @param dTDPtr is a pointer to the dTD element.
+ *
+ * @return TransferLength field of the descriptor.
+ *
+ * @note C-style signature:
+ * u32 XUsbPs_dTDGetTransferLen(u32 dTDPtr)
+ *
+ ******************************************************************************/
+#define XUsbPs_dTDGetTransferLen(dTDPtr) \
+ (u32) ((XUsbPs_ReaddTD(dTDPtr, XUSBPS_dTDTOKEN) \
+ & XUSBPS_dTDTOKEN_LEN_MASK) >> 16)
+
+
+/*****************************************************************************/
+/**
+ *
+ * This macro sets the Interrupt On Complete (IOC) bit for the given Transfer
+ * Descriptor.
+ *
+ * @param dTDPtr is a pointer to the dTD element.
+ *
+ * @note C-style signature:
+ * void XUsbPs_dTDSetIOC(u32 dTDPtr)
+ *
+ ******************************************************************************/
+#define XUsbPs_dTDSetIOC(dTDPtr) \
+ XUsbPs_WritedTD(dTDPtr, XUSBPS_dTDTOKEN, \
+ XUsbPs_ReaddTD(dTDPtr, XUSBPS_dTDTOKEN) | \
+ XUSBPS_dTDTOKEN_IOC_MASK)
+
+
+/*****************************************************************************/
+/**
+ *
+ * This macro sets the Terminate bit for the given Transfer Descriptor.
+ *
+ * @param dTDPtr is a pointer to the dTD element.
+ *
+ * @note C-style signature:
+ * void XUsbPs_dTDSetTerminate(u32 dTDPtr)
+ *
+ ******************************************************************************/
+#define XUsbPs_dTDSetTerminate(dTDPtr) \
+ XUsbPs_WritedTD(dTDPtr, XUSBPS_dTDNLP, \
+ XUsbPs_ReaddTD(dTDPtr, XUSBPS_dTDNLP) | \
+ XUSBPS_dTDNLP_T_MASK)
+
+
+/*****************************************************************************/
+/**
+ *
+ * This macro clears the Terminate bit for the given Transfer Descriptor.
+ *
+ * @param dTDPtr is a pointer to the dTD element.
+ *
+ * @note C-style signature:
+ * void XUsbPs_dTDClrTerminate(u32 dTDPtr)
+ *
+ ******************************************************************************/
+#define XUsbPs_dTDClrTerminate(dTDPtr) \
+ XUsbPs_WritedTD(dTDPtr, XUSBPS_dTDNLP, \
+ XUsbPs_ReaddTD(dTDPtr, XUSBPS_dTDNLP) & \
+ ~XUSBPS_dTDNLP_T_MASK)
+
+
+/*****************************************************************************/
+/**
+ *
+ * This macro checks if the given descriptor is active.
+ *
+ * @param dTDPtr is a pointer to the dTD element.
+ *
+ * @return
+ * - TRUE: The buffer is active.
+ * - FALSE: The buffer is not active.
+ *
+ * @note C-style signature:
+ * int XUsbPs_dTDIsActive(u32 dTDPtr)
+ *
+ ******************************************************************************/
+#define XUsbPs_dTDIsActive(dTDPtr) \
+ ((XUsbPs_ReaddTD(dTDPtr, XUSBPS_dTDTOKEN) & \
+ XUSBPS_dTDTOKEN_ACTIVE_MASK) ? TRUE : FALSE)
+
+
+/*****************************************************************************/
+/**
+ *
+ * This macro sets the Active bit for the given Transfer Descriptor.
+ *
+ * @param dTDPtr is a pointer to the dTD element.
+ *
+ * @note C-style signature:
+ * void XUsbPs_dTDSetActive(u32 dTDPtr)
+ *
+ ******************************************************************************/
+#define XUsbPs_dTDSetActive(dTDPtr) \
+ XUsbPs_WritedTD(dTDPtr, XUSBPS_dTDTOKEN, \
+ XUsbPs_ReaddTD(dTDPtr, XUSBPS_dTDTOKEN) | \
+ XUSBPS_dTDTOKEN_ACTIVE_MASK)
+
+
+/*****************************************************************************/
+/**
+ *
+ * This macro reads the content of a field in a Transfer Descriptor.
+ *
+ * @param dTDPtr is a pointer to the dTD element.
+ * @param Id is the field ID inside the dTD element to read.
+ *
+ * @note C-style signature:
+ * u32 XUsbPs_ReaddTD(u32 dTDPtr, u32 Id)
+ *
+ ******************************************************************************/
+#define XUsbPs_ReaddTD(dTDPtr, Id) (*(u32 *)((u32)(dTDPtr) + (u32)(Id)))
+
+/*****************************************************************************/
+/**
+ *
+ * This macro writes a value to a field in a Transfer Descriptor.
+ *
+ * @param dTDPtr is pointer to the dTD element.
+ * @param Id is the field ID inside the dTD element to read.
+ * @param Val is the value to write to the field.
+ *
+ * @note C-style signature:
+ * u32 XUsbPs_WritedTD(u32 dTDPtr, u32 Id, u32 Val)
+ *
+ ******************************************************************************/
+#define XUsbPs_WritedTD(dTDPtr, Id, Val) \
+ (*(u32 *) ((u32)(dTDPtr) + (u32)(Id)) = (u32)(Val))
+
+
+/******************************************************************************/
+/**
+ * Endpoint Device Queue Head
+ *
+ * Device queue heads are arranged in an array in a continuous area of memory
+ * pointed to by the ENDPOINTLISTADDR pointer. The device controller will index
+ * into this array based upon the endpoint number received from the USB bus.
+ * All information necessary to respond to transactions for all primed
+ * transfers is contained in this list so the Device Controller can readily
+ * respond to incoming requests without having to traverse a linked list.
+ *
+ * The device Endpoint Queue Head (dQH) is where all transfers are managed. The
+ * dQH is a 48-byte data structure, but must be aligned on a 64-byte boundary.
+ * During priming of an endpoint, the dTD (device transfer descriptor) is
+ * copied into the overlay area of the dQH, which starts at the nextTD pointer
+ * DWord and continues through the end of the buffer pointers DWords. After a
+ * transfer is complete, the dTD status DWord is updated in the dTD pointed to
+ * by the currentTD pointer. While a packet is in progress, the overlay area of
+ * the dQH is used as a staging area for the dTD so that the Device Controller
+ * can access needed information with little minimal latency.
+ *
+ * @note
+ * Software must ensure that no interface data structure reachable by the
+ * Device Controller spans a 4K-page boundary. The first element of the
+ * Endpoint Queue Head List must be aligned on a 4K boundary.
+ */
+#define XUSBPS_dQHCFG 0x00 /**< dQH Configuration */
+#define XUSBPS_dQHCPTR 0x04 /**< dQH Current dTD Pointer */
+#define XUSBPS_dQHdTDNLP 0x08 /**< dTD Next Link Ptr in dQH
+ overlay */
+#define XUSBPS_dQHdTDTOKEN 0x0C /**< dTD Token in dQH overlay */
+#define XUSBPS_dQHSUB0 0x28 /**< USB dQH Setup Buffer 0 */
+#define XUSBPS_dQHSUB1 0x2C /**< USB dQH Setup Buffer 1 */
+
+
+/** @name dQH Configuration (dQHCFG) bit positions.
+ * @{
+ */
+#define XUSBPS_dQHCFG_IOS_MASK 0x00008000
+ /**< USB dQH Interrupt on Setup Bit */
+#define XUSBPS_dQHCFG_MPL_MASK 0x07FF0000
+ /**< USB dQH Maximum Packet Length
+ * Field [10:0] */
+#define XUSBPS_dQHCFG_MPL_SHIFT 16
+#define XUSBPS_dQHCFG_ZLT_MASK 0x20000000
+ /**< USB dQH Zero Length Termination
+ * Select Bit */
+#define XUSBPS_dQHCFG_MULT_MASK 0xC0000000
+ /* USB dQH Number of Transactions Field
+ * [1:0] */
+#define XUSBPS_dQHCFG_MULT_SHIFT 30
+/* @} */
+
+
+/*****************************************************************************/
+/**
+ *
+ * This macro sets the Maximum Packet Length field of the give Queue Head.
+ *
+ * @param dQHPtr is a pointer to the dQH element.
+ * @param Len is the length to be set.
+ *
+ * @note C-style signature:
+ * void XUsbPs_dQHSetMaxPacketLen(u32 dQHPtr, u32 Len)
+ *
+ ******************************************************************************/
+#define XUsbPs_dQHSetMaxPacketLen(dQHPtr, Len) \
+ XUsbPs_WritedQH(dQHPtr, XUSBPS_dQHCFG, \
+ (XUsbPs_ReaddQH(dQHPtr, XUSBPS_dQHCFG) & \
+ ~XUSBPS_dQHCFG_MPL_MASK) | ((Len) << 16))
+
+/*****************************************************************************/
+/**
+ *
+ * This macro sets the Interrupt On Setup (IOS) bit for an endpoint.
+ *
+ * @param dQHPtr is a pointer to the dQH element.
+ *
+ * @note C-style signature:
+ * void XUsbPs_dQHSetIOS(u32 dQHPtr)
+ *
+ ******************************************************************************/
+#define XUsbPs_dQHSetIOS(dQHPtr) \
+ XUsbPs_WritedQH(dQHPtr, XUSBPS_dQHCFG, \
+ XUsbPs_ReaddQH(dQHPtr, XUSBPS_dQHCFG) | \
+ XUSBPS_dQHCFG_IOS_MASK)
+
+/*****************************************************************************/
+/**
+ *
+ * This macro clears the Interrupt On Setup (IOS) bit for an endpoint.
+ *
+ * @param dQHPtr is a pointer to the dQH element.
+ *
+ * @note C-style signature:
+ * void XUsbPs_dQHClrIOS(u32 dQHPtr)
+ *
+ ******************************************************************************/
+#define XUsbPs_dQHClrIOS(dQHPtr) \
+ XUsbPs_WritedQH(dQHPtr, XUSBPS_dQHCFG, \
+ XUsbPs_ReaddQH(dQHPtr, XUSBPS_dQHCFG) & \
+ ~XUSBPS_dQHCFG_IOS_MASK)
+
+/*****************************************************************************/
+/**
+ *
+ * This macro enables Zero Length Termination for the endpoint.
+ *
+ * @param dQHPtr is a pointer to the dQH element.
+ *
+ * @note C-style signature:
+ * void XUsbPs_dQHEnableZLT(u32 dQHPtr)
+ *
+ *
+ ******************************************************************************/
+#define XUsbPs_dQHEnableZLT(dQHPtr) \
+ XUsbPs_WritedQH(dQHPtr, XUSBPS_dQHCFG, \
+ XUsbPs_ReaddQH(dQHPtr, XUSBPS_dQHCFG) & \
+ ~XUSBPS_dQHCFG_ZLT_MASK)
+
+
+/*****************************************************************************/
+/**
+ *
+ * This macro disables Zero Length Termination for the endpoint.
+ *
+ * @param dQHPtr is a pointer to the dQH element.
+ *
+ * @note C-style signature:
+ * void XUsbPs_dQHDisableZLT(u32 dQHPtr)
+ *
+ *
+ ******************************************************************************/
+#define XUsbPs_dQHDisableZLT(dQHPtr) \
+ XUsbPs_WritedQH(dQHPtr, XUSBPS_dQHCFG, \
+ XUsbPs_ReaddQH(dQHPtr, XUSBPS_dQHCFG) | \
+ XUSBPS_dQHCFG_ZLT_MASK)
+
+/*****************************************************************************/
+/**
+ *
+ * This macro reads the content of a field in a Queue Head.
+ *
+ * @param dQHPtr is a pointer to the dQH element.
+ * @param Id is the Field ID inside the dQH element to read.
+ *
+ * @note C-style signature:
+ * u32 XUsbPs_ReaddQH(u32 dQHPtr, u32 Id)
+ *
+ ******************************************************************************/
+#define XUsbPs_ReaddQH(dQHPtr, Id) (*(u32 *)((u32)(dQHPtr) + (u32) (Id)))
+
+/*****************************************************************************/
+/**
+ *
+ * This macro writes a value to a field in a Queue Head.
+ *
+ * @param dQHPtr is a pointer to the dQH element.
+ * @param Id is the Field ID inside the dQH element to read.
+ * @param Val is the Value to write to the field.
+ *
+ * @note C-style signature:
+ * u32 XUsbPs_WritedQH(u32 dQHPtr, u32 Id, u32 Val)
+ *
+ ******************************************************************************/
+#define XUsbPs_WritedQH(dQHPtr, Id, Val) \
+ (*(u32 *) ((u32)(dQHPtr) + (u32)(Id)) = (u32)(Val))
+
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* XUSBPS_ENDPOINT_H */
+/** @} */
diff --git a/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/include/xusbps_hw.h b/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/include/xusbps_hw.h
new file mode 100644
index 0000000..751a8d1
--- /dev/null
+++ b/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/include/xusbps_hw.h
@@ -0,0 +1,520 @@
+/******************************************************************************
+*
+* Copyright (C) 2010 - 2015 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+* THE SOFTWARE.
+*
+*
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+ *
+ * @file xusbps_hw.h
+* @addtogroup usbps_v2_4
+* @{
+ *
+ * This header file contains identifiers and low-level driver functions (or
+ * macros) that can be used to access the device. High-level driver functions
+ * are defined in xusbps.h.
+ *
+ * <pre>
+ * MODIFICATION HISTORY:
+ *
+ * Ver Who Date Changes
+ * ----- ---- -------- -----------------------------------------------
+ * 1.00a wgr 10/10/10 First release
+ * 1.04a nm 10/23/12 Fixed CR# 679106.
+ * 1.05a kpc 07/03/13 Added XUsbPs_ResetHw function prototype
+ * 2.00a kpc 04/03/14 Fixed CR#777764. Corrected max endpoint vale and masks
+ * </pre>
+ *
+ ******************************************************************************/
+#ifndef XUSBPS_HW_H
+#define XUSBPS_HW_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/***************************** Include Files *********************************/
+
+#include "xil_types.h"
+#include "xil_assert.h"
+#include "xil_io.h"
+
+/************************** Constant Definitions *****************************/
+
+
+#define XUSBPS_REG_SPACING 4
+
+/** @name Timer 0 Register offsets
+ *
+ * @{
+ */
+#define XUSBPS_TIMER0_LD_OFFSET 0x00000080
+#define XUSBPS_TIMER0_CTL_OFFSET 0x00000084
+/* @} */
+
+/** @name Timer Control Register bit mask
+ *
+ * @{
+ */
+#define XUSBPS_TIMER_RUN_MASK 0x80000000
+#define XUSBPS_TIMER_STOP_MASK 0x80000000
+#define XUSBPS_TIMER_RESET_MASK 0x40000000
+#define XUSBPS_TIMER_REPEAT_MASK 0x01000000
+/* @} */
+
+/** @name Timer Control Register bit mask
+ *
+ * @{
+ */
+#define XUSBPS_TIMER_COUNTER_MASK 0x00FFFFFF
+/* @} */
+
+/** @name Device Hardware Parameters
+ *
+ * @{
+ */
+#define XUSBPS_HWDEVICE_OFFSET 0x0000000C
+
+#define XUSBPS_EP_NUM_MASK 0x3E
+#define XUSBPS_EP_NUM_SHIFT 1
+/* @} */
+
+/** @name Capability Register offsets
+ */
+#define XUSBPS_HCSPARAMS_OFFSET 0x00000104
+
+/** @name Operational Register offsets.
+ * Register comments are tagged with "H:" and "D:" for Host and Device modes,
+ * respectively.
+ * Tags are only present for registers that have a different meaning DEVICE and
+ * HOST modes. Most registers are only valid for either DEVICE or HOST mode.
+ * Those registers don't have tags.
+ * @{
+ */
+#define XUSBPS_CMD_OFFSET 0x00000140 /**< Configuration */
+#define XUSBPS_ISR_OFFSET 0x00000144 /**< Interrupt Status */
+#define XUSBPS_IER_OFFSET 0x00000148 /**< Interrupt Enable */
+#define XUSBPS_FRAME_OFFSET 0x0000014C /**< USB Frame Index */
+#define XUSBPS_LISTBASE_OFFSET 0x00000154 /**< H: Periodic List Base Address */
+#define XUSBPS_DEVICEADDR_OFFSET 0x00000154 /**< D: Device Address */
+#define XUSBPS_ASYNCLISTADDR_OFFSET 0x00000158 /**< H: Async List Address */
+#define XUSBPS_EPLISTADDR_OFFSET 0x00000158 /**< D: Endpoint List Addr */
+#define XUSBPS_TTCTRL_OFFSET 0x0000015C /**< TT Control */
+#define XUSBPS_BURSTSIZE_OFFSET 0x00000160 /**< Burst Size */
+#define XUSBPS_TXFILL_OFFSET 0x00000164 /**< Tx Fill Tuning */
+#define XUSBPS_ULPIVIEW_OFFSET 0x00000170 /**< ULPI Viewport */
+#define XUSBPS_EPNAKISR_OFFSET 0x00000178 /**< Endpoint NAK IRQ Status */
+#define XUSBPS_EPNAKIER_OFFSET 0x0000017C /**< Endpoint NAK IRQ Enable */
+#define XUSBPS_PORTSCR1_OFFSET 0x00000184 /**< Port Control/Status 1 */
+
+/* NOTE: The Port Control / Status Register index is 1-based. */
+#define XUSBPS_PORTSCRn_OFFSET(n) \
+ (XUSBPS_PORTSCR1_OFFSET + (((n)-1) * XUSBPS_REG_SPACING))
+
+
+#define XUSBPS_OTGCSR_OFFSET 0x000001A4 /**< OTG Status and Control */
+#define XUSBPS_MODE_OFFSET 0x000001A8 /**< USB Mode */
+#define XUSBPS_EPSTAT_OFFSET 0x000001AC /**< Endpoint Setup Status */
+#define XUSBPS_EPPRIME_OFFSET 0x000001B0 /**< Endpoint Prime */
+#define XUSBPS_EPFLUSH_OFFSET 0x000001B4 /**< Endpoint Flush */
+#define XUSBPS_EPRDY_OFFSET 0x000001B8 /**< Endpoint Ready */
+#define XUSBPS_EPCOMPL_OFFSET 0x000001BC /**< Endpoint Complete */
+#define XUSBPS_EPCR0_OFFSET 0x000001C0 /**< Endpoint Control 0 */
+#define XUSBPS_EPCR1_OFFSET 0x000001C4 /**< Endpoint Control 1 */
+#define XUSBPS_EPCR2_OFFSET 0x000001C8 /**< Endpoint Control 2 */
+#define XUSBPS_EPCR3_OFFSET 0x000001CC /**< Endpoint Control 3 */
+#define XUSBPS_EPCR4_OFFSET 0x000001D0 /**< Endpoint Control 4 */
+
+#define XUSBPS_MAX_ENDPOINTS 12 /**< Number of supported Endpoints in
+ * this core. */
+#define XUSBPS_EP_OUT_MASK 0x00000FFF /**< OUR (RX) endpoint mask */
+#define XUSBPS_EP_IN_MASK 0x0FFF0000 /**< IN (TX) endpoint mask */
+#define XUSBPS_EP_ALL_MASK 0x0FFF0FFF /**< Mask used for endpoint control
+ * registers */
+#define XUSBPS_EPCRn_OFFSET(n) \
+ (XUSBPS_EPCR0_OFFSET + ((n) * XUSBPS_REG_SPACING))
+
+#define XUSBPS_EPFLUSH_RX_SHIFT 0
+#define XUSBPS_EPFLUSH_TX_SHIFT 16
+
+/* @} */
+
+
+
+/** @name Endpoint Control Register (EPCR) bit positions.
+ * @{
+ */
+
+/* Definitions for TX Endpoint bits */
+#define XUSBPS_EPCR_TXT_CONTROL_MASK 0x00000000 /**< Control Endpoint - TX */
+#define XUSBPS_EPCR_TXT_ISO_MASK 0x00040000 /**< Isochronous. Endpoint */
+#define XUSBPS_EPCR_TXT_BULK_MASK 0x00080000 /**< Bulk Endpoint - TX */
+#define XUSBPS_EPCR_TXT_INTR_MASK 0x000C0000 /**< Interrupt Endpoint */
+#define XUSBPS_EPCR_TXS_MASK 0x00010000 /**< Stall TX endpoint */
+#define XUSBPS_EPCR_TXE_MASK 0x00800000 /**< Transmit enable - TX */
+#define XUSBPS_EPCR_TXR_MASK 0x00400000 /**< Data Toggle Reset Bit */
+
+
+/* Definitions for RX Endpoint bits */
+#define XUSBPS_EPCR_RXT_CONTROL_MASK 0x00000000 /**< Control Endpoint - RX */
+#define XUSBPS_EPCR_RXT_ISO_MASK 0x00000004 /**< Isochronous Endpoint */
+#define XUSBPS_EPCR_RXT_BULK_MASK 0x00000008 /**< Bulk Endpoint - RX */
+#define XUSBPS_EPCR_RXT_INTR_MASK 0x0000000C /**< Interrupt Endpoint */
+#define XUSBPS_EPCR_RXS_MASK 0x00000001 /**< Stall RX endpoint. */
+#define XUSBPS_EPCR_RXE_MASK 0x00000080 /**< Transmit enable. - RX */
+#define XUSBPS_EPCR_RXR_MASK 0x00000040 /**< Data Toggle Reset Bit */
+/* @} */
+
+
+/** @name USB Command Register (CR) bit positions.
+ * @{
+ */
+#define XUSBPS_CMD_RS_MASK 0x00000001 /**< Run/Stop */
+#define XUSBPS_CMD_RST_MASK 0x00000002 /**< Controller RESET */
+#define XUSBPS_CMD_FS01_MASK 0x0000000C /**< Frame List Size bit 0,1 */
+#define XUSBPS_CMD_PSE_MASK 0x00000010 /**< Periodic Sched Enable */
+#define XUSBPS_CMD_ASE_MASK 0x00000020 /**< Async Sched Enable */
+#define XUSBPS_CMD_IAA_MASK 0x00000040 /**< IRQ Async Advance Doorbell */
+#define XUSBPS_CMD_ASP_MASK 0x00000300 /**< Async Sched Park Mode Cnt */
+#define XUSBPS_CMD_ASPE_MASK 0x00000800 /**< Async Sched Park Mode Enbl */
+#define XUSBPS_CMD_SUTW_MASK 0x00002000 /**< Setup TripWire */
+#define XUSBPS_CMD_ATDTW_MASK 0x00004000 /**< Add dTD TripWire */
+#define XUSBPS_CMD_FS2_MASK 0x00008000 /**< Frame List Size bit 2 */
+#define XUSBPS_CMD_ITC_MASK 0x00FF0000 /**< IRQ Threshold Control */
+/* @} */
+
+
+/**
+ * @name Interrupt Threshold
+ * These definitions are used by software to set the maximum rate at which the
+ * USB controller will generate interrupt requests. The interrupt interval is
+ * given in number of micro-frames.
+ *
+ * USB defines a full-speed 1 ms frame time indicated by a Start Of Frame (SOF)
+ * packet each and every 1ms. USB also defines a high-speed micro-frame with a
+ * 125us frame time. For each micro-frame a SOF (Start Of Frame) packet is
+ * generated. Data is sent in between the SOF packets. The interrupt threshold
+ * defines how many micro-frames the controller waits before issuing an
+ * interrupt after data has been received.
+ *
+ * For a threshold of 0 the controller will issue an interrupt immediately
+ * after the last byte of the data has been received. For a threshold n>0 the
+ * controller will wait for n micro-frames before issuing an interrupt.
+ *
+ * Therefore, a setting of 8 micro-frames (default) means that the controller
+ * will issue at most 1 interrupt per millisecond.
+ *
+ * @{
+ */
+#define XUSBPS_CMD_ITHRESHOLD_0 0x00 /**< Immediate interrupt. */
+#define XUSBPS_CMD_ITHRESHOLD_1 0x01 /**< 1 micro-frame */
+#define XUSBPS_CMD_ITHRESHOLD_2 0x02 /**< 2 micro-frames */
+#define XUSBPS_CMD_ITHRESHOLD_4 0x04 /**< 4 micro-frames */
+#define XUSBPS_CMD_ITHRESHOLD_8 0x08 /**< 8 micro-frames */
+#define XUSBPS_CMD_ITHRESHOLD_16 0x10 /**< 16 micro-frames */
+#define XUSBPS_CMD_ITHRESHOLD_32 0x20 /**< 32 micro-frames */
+#define XUSBPS_CMD_ITHRESHOLD_64 0x40 /**< 64 micro-frames */
+#define XUSBPS_CMD_ITHRESHOLD_MAX XUSBPS_CMD_ITHRESHOLD_64
+#define XUSBPS_CMD_ITHRESHOLD_DEFAULT XUSBPS_CMD_ITHRESHOLD_8
+/* @} */
+
+
+
+/** @name USB Interrupt Status Register (ISR) / Interrupt Enable Register (IER)
+ * bit positions.
+ * @{
+ */
+#define XUSBPS_IXR_UI_MASK 0x00000001 /**< USB Transaction Complete */
+#define XUSBPS_IXR_UE_MASK 0x00000002 /**< Transaction Error */
+#define XUSBPS_IXR_PC_MASK 0x00000004 /**< Port Change Detect */
+#define XUSBPS_IXR_FRE_MASK 0x00000008 /**< Frame List Rollover */
+#define XUSBPS_IXR_AA_MASK 0x00000020 /**< Async Advance */
+#define XUSBPS_IXR_UR_MASK 0x00000040 /**< RESET Received */
+#define XUSBPS_IXR_SR_MASK 0x00000080 /**< Start of Frame */
+#define XUSBPS_IXR_SLE_MASK 0x00000100 /**< Device Controller Suspend */
+#define XUSBPS_IXR_ULPI_MASK 0x00000400 /**< ULPI IRQ */
+#define XUSBPS_IXR_HCH_MASK 0x00001000 /**< Host Controller Halted
+ * Read Only */
+#define XUSBPS_IXR_RCL_MASK 0x00002000 /**< USB Reclamation Read Only */
+#define XUSBPS_IXR_PS_MASK 0x00004000 /**< Periodic Sched Status
+ * Read Only */
+#define XUSBPS_IXR_AS_MASK 0x00008000 /**< Async Sched Status Read only */
+#define XUSBPS_IXR_NAK_MASK 0x00010000 /**< NAK IRQ */
+#define XUSBPS_IXR_UA_MASK 0x00040000 /**< USB Host Async IRQ */
+#define XUSBPS_IXR_UP_MASK 0x00080000 /**< USB Host Periodic IRQ */
+#define XUSBPS_IXR_TI0_MASK 0x01000000 /**< Timer 0 Interrupt */
+#define XUSBPS_IXR_TI1_MASK 0x02000000 /**< Timer 1 Interrupt */
+
+#define XUSBPS_IXR_ALL (XUSBPS_IXR_UI_MASK | \
+ XUSBPS_IXR_UE_MASK | \
+ XUSBPS_IXR_PC_MASK | \
+ XUSBPS_IXR_FRE_MASK | \
+ XUSBPS_IXR_AA_MASK | \
+ XUSBPS_IXR_UR_MASK | \
+ XUSBPS_IXR_SR_MASK | \
+ XUSBPS_IXR_SLE_MASK | \
+ XUSBPS_IXR_ULPI_MASK | \
+ XUSBPS_IXR_HCH_MASK | \
+ XUSBPS_IXR_RCL_MASK | \
+ XUSBPS_IXR_PS_MASK | \
+ XUSBPS_IXR_AS_MASK | \
+ XUSBPS_IXR_NAK_MASK | \
+ XUSBPS_IXR_UA_MASK | \
+ XUSBPS_IXR_UP_MASK | \
+ XUSBPS_IXR_TI0_MASK | \
+ XUSBPS_IXR_TI1_MASK)
+ /**< Mask for ALL IRQ types */
+/* @} */
+
+
+/** @name USB Mode Register (MODE) bit positions.
+ * @{
+ */
+#define XUSBPS_MODE_CM_MASK 0x00000003 /**< Controller Mode Select */
+#define XUSBPS_MODE_CM_IDLE_MASK 0x00000000
+#define XUSBPS_MODE_CM_DEVICE_MASK 0x00000002
+#define XUSBPS_MODE_CM_HOST_MASK 0x00000003
+#define XUSBPS_MODE_ES_MASK 0x00000004 /**< USB Endian Select */
+#define XUSBPS_MODE_SLOM_MASK 0x00000008 /**< USB Setup Lockout Mode Disable */
+#define XUSBPS_MODE_SDIS_MASK 0x00000010
+#define XUSBPS_MODE_VALID_MASK 0x0000001F
+
+/* @} */
+
+
+/** @name USB Device Address Register (DEVICEADDR) bit positions.
+ * @{
+ */
+#define XUSBPS_DEVICEADDR_DEVICEAADV_MASK 0x01000000
+ /**< Device Addr Auto Advance */
+#define XUSBPS_DEVICEADDR_ADDR_MASK 0xFE000000
+ /**< Device Address */
+#define XUSBPS_DEVICEADDR_ADDR_SHIFT 25
+ /**< Address shift */
+#define XUSBPS_DEVICEADDR_MAX 127
+ /**< Biggest allowed address */
+/* @} */
+
+/** @name USB TT Control Register (TTCTRL) bit positions.
+ * @{
+ */
+#define XUSBPS_TTCTRL_HUBADDR_MASK 0x7F000000 /**< TT Hub Address */
+/* @} */
+
+
+/** @name USB Burst Size Register (BURSTSIZE) bit posisions.
+ * @{
+ */
+#define XUSBPS_BURSTSIZE_RX_MASK 0x000000FF /**< RX Burst Length */
+#define XUSBPS_BURSTSIZE_TX_MASK 0x0000FF00 /**< TX Burst Length */
+/* @} */
+
+
+/** @name USB Tx Fill Tuning Register (TXFILL) bit positions.
+ * @{
+ */
+#define XUSBPS_TXFILL_OVERHEAD_MASK 0x000000FF
+ /**< Scheduler Overhead */
+#define XUSBPS_TXFILL_HEALTH_MASK 0x00001F00
+ /**< Scheduler Health Cntr */
+#define XUSBPS_TXFILL_BURST_MASK 0x003F0000
+ /**< FIFO Burst Threshold */
+/* @} */
+
+
+/** @name USB ULPI Viewport Register (ULPIVIEW) bit positions.
+ * @{
+ */
+#define XUSBPS_ULPIVIEW_DATWR_MASK 0x000000FF /**< ULPI Data Write */
+#define XUSBPS_ULPIVIEW_DATRD_MASK 0x0000FF00 /**< ULPI Data Read */
+#define XUSBPS_ULPIVIEW_ADDR_MASK 0x00FF0000 /**< ULPI Data Address */
+#define XUSBPS_ULPIVIEW_PORT_MASK 0x07000000 /**< ULPI Port Number */
+#define XUSBPS_ULPIVIEW_SS_MASK 0x08000000 /**< ULPI Synchronous State */
+#define XUSBPS_ULPIVIEW_RW_MASK 0x20000000 /**< ULPI Read/Write Control */
+#define XUSBPS_ULPIVIEW_RUN_MASK 0x40000000 /**< ULPI Run */
+#define XUSBPS_ULPIVIEW_WU_MASK 0x80000000 /**< ULPI Wakeup */
+/* @} */
+
+
+/** @name Port Status Control Register bit positions.
+ * @{
+ */
+#define XUSBPS_PORTSCR_CCS_MASK 0x00000001 /**< Current Connect Status */
+#define XUSBPS_PORTSCR_CSC_MASK 0x00000002 /**< Connect Status Change */
+#define XUSBPS_PORTSCR_PE_MASK 0x00000004 /**< Port Enable/Disable */
+#define XUSBPS_PORTSCR_PEC_MASK 0x00000008 /**< Port Enable/Disable Change */
+#define XUSBPS_PORTSCR_OCA_MASK 0x00000010 /**< Over-current Active */
+#define XUSBPS_PORTSCR_OCC_MASK 0x00000020 /**< Over-current Change */
+#define XUSBPS_PORTSCR_FPR_MASK 0x00000040 /**< Force Port Resume */
+#define XUSBPS_PORTSCR_SUSP_MASK 0x00000080 /**< Suspend */
+#define XUSBPS_PORTSCR_PR_MASK 0x00000100 /**< Port Reset */
+#define XUSBPS_PORTSCR_HSP_MASK 0x00000200 /**< High Speed Port */
+#define XUSBPS_PORTSCR_LS_MASK 0x00000C00 /**< Line Status */
+#define XUSBPS_PORTSCR_PP_MASK 0x00001000 /**< Port Power */
+#define XUSBPS_PORTSCR_PO_MASK 0x00002000 /**< Port Owner */
+#define XUSBPS_PORTSCR_PIC_MASK 0x0000C000 /**< Port Indicator Control */
+#define XUSBPS_PORTSCR_PTC_MASK 0x000F0000 /**< Port Test Control */
+#define XUSBPS_PORTSCR_WKCN_MASK 0x00100000 /**< Wake on Connect Enable */
+#define XUSBPS_PORTSCR_WKDS_MASK 0x00200000 /**< Wake on Disconnect Enable */
+#define XUSBPS_PORTSCR_WKOC_MASK 0x00400000 /**< Wake on Over-current Enable */
+#define XUSBPS_PORTSCR_PHCD_MASK 0x00800000 /**< PHY Low Power Suspend -
+ * Clock Disable */
+#define XUSBPS_PORTSCR_PFSC_MASK 0x01000000 /**< Port Force Full Speed
+ * Connect */
+#define XUSBPS_PORTSCR_PSPD_MASK 0x0C000000 /**< Port Speed */
+/* @} */
+
+
+/** @name On-The-Go Status Control Register (OTGCSR) bit positions.
+ * @{
+ */
+#define XUSBPS_OTGSC_VD_MASK 0x00000001 /**< VBus Discharge Bit */
+#define XUSBPS_OTGSC_VC_MASK 0x00000002 /**< VBus Charge Bit */
+#define XUSBPS_OTGSC_HAAR_MASK 0x00000004 /**< HW Assist Auto Reset
+ * Enable Bit */
+#define XUSBPS_OTGSC_OT_MASK 0x00000008 /**< OTG Termination Bit */
+#define XUSBPS_OTGSC_DP_MASK 0x00000010 /**< Data Pulsing Pull-up
+ * Enable Bit */
+#define XUSBPS_OTGSC_IDPU_MASK 0x00000020 /**< ID Pull-up Enable Bit */
+#define XUSBPS_OTGSC_HADP_MASK 0x00000040 /**< HW Assist Data Pulse
+ * Enable Bit */
+#define XUSBPS_OTGSC_HABA_MASK 0x00000080 /**< USB Hardware Assist
+ * B Disconnect to A
+ * Connect Enable Bit */
+#define XUSBPS_OTGSC_ID_MASK 0x00000100 /**< ID Status Flag */
+#define XUSBPS_OTGSC_AVV_MASK 0x00000200 /**< USB A VBus Valid Interrupt Status Flag */
+#define XUSBPS_OTGSC_ASV_MASK 0x00000400 /**< USB A Session Valid Interrupt Status Flag */
+#define XUSBPS_OTGSC_BSV_MASK 0x00000800 /**< USB B Session Valid Status Flag */
+#define XUSBPS_OTGSC_BSE_MASK 0x00001000 /**< USB B Session End Status Flag */
+#define XUSBPS_OTGSC_1MST_MASK 0x00002000 /**< USB 1 Millisecond Timer Status Flag */
+#define XUSBPS_OTGSC_DPS_MASK 0x00004000 /**< Data Pulse Status Flag */
+#define XUSBPS_OTGSC_IDIS_MASK 0x00010000 /**< USB ID Interrupt Status Flag */
+#define XUSBPS_OTGSC_AVVIS_MASK 0x00020000 /**< USB A VBus Valid Interrupt Status Flag */
+#define XUSBPS_OTGSC_ASVIS_MASK 0x00040000 /**< USB A Session Valid Interrupt Status Flag */
+#define XUSBPS_OTGSC_BSVIS_MASK 0x00080000 /**< USB B Session Valid Interrupt Status Flag */
+#define XUSBPS_OTGSC_BSEIS_MASK 0x00100000 /**< USB B Session End Interrupt Status Flag */
+#define XUSBPS_OTGSC_1MSS_MASK 0x00200000 /**< 1 Millisecond Timer Interrupt Status Flag */
+#define XUSBPS_OTGSC_DPIS_MASK 0x00400000 /**< Data Pulse Interrupt Status Flag */
+#define XUSBPS_OTGSC_IDIE_MASK 0x01000000 /**< ID Interrupt Enable Bit */
+#define XUSBPS_OTGSC_AVVIE_MASK 0x02000000 /**< USB A VBus Valid Interrupt Enable Bit */
+#define XUSBPS_OTGSC_ASVIE_MASK 0x04000000 /**< USB A Session Valid Interrupt Enable Bit */
+#define XUSBPS_OTGSC_BSVIE_MASK 0x08000000 /**< USB B Session Valid Interrupt Enable Bit */
+#define XUSBPS_OTGSC_BSEE_MASK 0x10000000 /**< USB B Session End Interrupt Enable Bit */
+#define XUSBPS_OTGSC_1MSE_MASK 0x20000000 /**< 1 Millisecond Timer
+ * Interrupt Enable Bit */
+#define XUSBPS_OTGSC_DPIE_MASK 0x40000000 /**< Data Pulse Interrupt
+ * Enable Bit */
+
+#define XUSBPS_OTG_ISB_ALL (XUSBPS_OTGSC_IDIS_MASK |\
+ XUSBPS_OTGSC_AVVIS_MASK | \
+ XUSBPS_OTGSC_ASVIS_MASK | \
+ XUSBPS_OTGSC_BSVIS_MASK | \
+ XUSBPS_OTGSC_BSEIS_MASK | \
+ XUSBPS_OTGSC_1MSS_MASK | \
+ XUSBPS_OTGSC_DPIS_MASK)
+ /** Mask for All IRQ status masks */
+
+#define XUSBPS_OTG_IEB_ALL (XUSBPS_OTGSC_IDIE_MASK |\
+ XUSBPS_OTGSC_AVVIE_MASK | \
+ XUSBPS_OTGSC_ASVIE_MASK | \
+ XUSBPS_OTGSC_BSVIE_MASK | \
+ XUSBPS_OTGSC_BSEE_IEB_MASK | \
+ XUSBPS_OTGSC_1MSE_MASK | \
+ XUSBPS_OTGSC_DPIE_MASK)
+ /** Mask for All IRQ Enable masks */
+/* @} */
+
+
+/**< Alignment of the Device Queue Head List BASE. */
+#define XUSBPS_dQH_BASE_ALIGN 2048
+
+/**< Alignment of a Device Queue Head structure. */
+#define XUSBPS_dQH_ALIGN 64
+
+/**< Alignment of a Device Transfer Descriptor structure. */
+#define XUSBPS_dTD_ALIGN 32
+
+/**< Size of one RX buffer for a OUT Transfer Descriptor. */
+#define XUSBPS_dTD_BUF_SIZE 4096
+
+/**< Maximum size of one RX/TX buffer. */
+#define XUSBPS_dTD_BUF_MAX_SIZE 16*1024
+
+/**< Alignment requirement for Transfer Descriptor buffers. */
+#define XUSBPS_dTD_BUF_ALIGN 4096
+
+
+/**************************** Type Definitions *******************************/
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/****************************************************************************/
+/**
+*
+* This macro reads the given register.
+*
+* @param BaseAddress is the base address for the USB registers.
+* @param RegOffset is the register offset to be read.
+*
+* @return The 32-bit value of the register.
+*
+* @note C-style signature:
+* u32 XUsbPs_ReadReg(u32 BaseAddress, u32 RegOffset)
+*
+*****************************************************************************/
+#define XUsbPs_ReadReg(BaseAddress, RegOffset) \
+ Xil_In32(BaseAddress + (RegOffset))
+
+
+/****************************************************************************/
+/**
+*
+* This macro writes the given register.
+*
+* @param BaseAddress is the the base address for the USB registers.
+* @param RegOffset is the register offset to be written.
+* @param Data is the the 32-bit value to write to the register.
+*
+* @return None.
+*
+* @note C-style signature:
+* void XUsbPs_WriteReg(u32 BaseAddress, u32 RegOffset, u32 Data)
+*
+ *****************************************************************************/
+#define XUsbPs_WriteReg(BaseAddress, RegOffset, Data) \
+ Xil_Out32(BaseAddress + (RegOffset), (Data))
+
+
+/************************** Function Prototypes ******************************/
+/*
+ * Perform reset operation to the USB PS interface
+ */
+void XUsbPs_ResetHw(u32 BaseAddress);
+/************************** Variable Definitions ******************************/
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* XUSBPS_L_H */
+/** @} */
diff --git a/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/bram_v4_3/src/Makefile b/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/bram_v4_3/src/Makefile
new file mode 100644
index 0000000..dce15aa
--- /dev/null
+++ b/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/bram_v4_3/src/Makefile
@@ -0,0 +1,28 @@
+COMPILER=
+ARCHIVER=
+CP=cp
+COMPILER_FLAGS=
+EXTRA_COMPILER_FLAGS=
+LIB=libxil.a
+
+RELEASEDIR=../../../lib
+INCLUDEDIR=../../../include
+INCLUDES=-I./. -I${INCLUDEDIR}
+
+INCLUDEFILES=*.h
+
+LIBSOURCES=*.c
+OUTS = *.o
+OBJECTS = $(addsuffix .o, $(basename $(wildcard *.c)))
+
+libs:
+ echo "Compiling bram"
+ $(COMPILER) $(COMPILER_FLAGS) $(EXTRA_COMPILER_FLAGS) $(INCLUDES) $(LIBSOURCES)
+ $(ARCHIVER) -r ${RELEASEDIR}/${LIB} $(OBJECTS)
+ make clean
+
+include:
+ ${CP} ${INCLUDEFILES} ${INCLUDEDIR}
+
+clean:
+ rm -rf ${OBJECTS}
diff --git a/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/bram_v4_3/src/xbram.c b/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/bram_v4_3/src/xbram.c
new file mode 100644
index 0000000..7645abe
--- /dev/null
+++ b/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/bram_v4_3/src/xbram.c
@@ -0,0 +1,143 @@
+/******************************************************************************
+*
+* Copyright (C) 2010 - 2015 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+* THE SOFTWARE.
+*
+*
+*
+******************************************************************************/
+
+/**
+* @file xbram.c
+* @addtogroup bram_v4_2
+* @{
+*
+* The implementation of the XBram driver's basic functionality.
+* See xbram.h for more information about the driver.
+*
+* @note
+*
+* None
+*
+* <pre>
+* MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ----- ---- -------- -----------------------------------------------
+* 1.00a sa 05/11/10 First release
+* 3.01a sa 13/01/12 Added CorrectableFailingDataRegs and
+* UncorrectableFailingDataRegs in
+* XBram_CfgInitialize API.
+* 4.1 sk 11/10/15 Used UINTPTR instead of u32 for Baseaddress CR# 867425.
+* Changed the prototype of XBram_CfgInitialize API.
+*</pre>
+*
+*****************************************************************************/
+
+/***************************** Include Files ********************************/
+
+#include "xbram.h"
+#include "xstatus.h"
+
+/************************** Constant Definitions ****************************/
+
+/**************************** Type Definitions ******************************/
+
+/***************** Macros (Inline Functions) Definitions ********************/
+
+/************************** Variable Definitions ****************************/
+
+
+/************************** Function Prototypes *****************************/
+
+
+/****************************************************************************/
+/**
+* Initialize the XBram instance provided by the caller based on the given
+* configuration data.
+*
+* Nothing is done except to initialize the InstancePtr.
+*
+* @param InstancePtr is a pointer to an XBram instance.
+* The memory the pointer references must be pre-allocated by
+* the caller. Further calls to manipulate the driver through
+* the XBram API must be made with this pointer.
+* @param Config is a reference to a structure containing information
+* about a specific BRAM device. This function
+* initializes an InstancePtr object for a specific device
+* specified by the contents of Config. This function can
+* initialize multiple instance objects with the use of multiple
+* calls giving different Config information on each call.
+* @param EffectiveAddr is the device base address in the virtual memory
+* address space. The caller is responsible for keeping the
+* address mapping from EffectiveAddr to the device physical base
+* address unchanged once this function is invoked. Unexpected
+* errors may occur if the address mapping changes after this
+* function is called. If address translation is not used, use
+* Config->BaseAddress for this parameters, passing the physical
+* address instead.
+*
+* @return
+* - XST_SUCCESS Initialization was successful.
+*
+* @note None.
+*
+*****************************************************************************/
+int XBram_CfgInitialize(XBram *InstancePtr,
+ XBram_Config *Config,
+ UINTPTR EffectiveAddr)
+{
+ /*
+ * Assert arguments
+ */
+ Xil_AssertNonvoid(InstancePtr != NULL);
+
+ /*
+ * Set some default values.
+ */
+ InstancePtr->Config.CtrlBaseAddress = EffectiveAddr;
+ InstancePtr->Config.MemBaseAddress = Config->MemBaseAddress;
+ InstancePtr->Config.MemHighAddress = Config->MemHighAddress;
+ InstancePtr->Config.DataWidth = Config->DataWidth;
+ InstancePtr->Config.EccPresent = Config->EccPresent;
+ InstancePtr->Config.FaultInjectionPresent =
+ Config->FaultInjectionPresent;
+ InstancePtr->Config.CorrectableFailingRegisters =
+ Config->CorrectableFailingRegisters;
+ InstancePtr->Config.CorrectableFailingDataRegs =
+ Config->CorrectableFailingDataRegs;
+ InstancePtr->Config.UncorrectableFailingRegisters =
+ Config->UncorrectableFailingRegisters;
+ InstancePtr->Config.UncorrectableFailingDataRegs =
+ Config->UncorrectableFailingDataRegs;
+ InstancePtr->Config.EccStatusInterruptPresent =
+ Config->EccStatusInterruptPresent;
+ InstancePtr->Config.CorrectableCounterBits =
+ Config->CorrectableCounterBits;
+ InstancePtr->Config.WriteAccess = Config->WriteAccess;
+
+ /*
+ * Indicate the instance is now ready to use, initialized without error
+ */
+ InstancePtr->IsReady = XIL_COMPONENT_IS_READY;
+ return (XST_SUCCESS);
+}
+
+/** @} */
diff --git a/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/bram_v4_3/src/xbram.h b/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/bram_v4_3/src/xbram.h
new file mode 100644
index 0000000..0288074
--- /dev/null
+++ b/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/bram_v4_3/src/xbram.h
@@ -0,0 +1,221 @@
+/******************************************************************************
+*
+* Copyright (C) 2010 - 2019 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+* THE SOFTWARE.
+*
+*
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+* @file xbram.h
+* @addtogroup bram_v4_2
+* @{
+* @details
+*
+* If ECC is not enabled, this driver exists only to allow the tools to
+* create a memory test application and to populate xparameters.h with memory
+* range constants. In this case there is no source code.
+*
+* If ECC is enabled, this file contains the software API definition of the
+* Xilinx BRAM Interface Controller (XBram) device driver.
+*
+* The Xilinx BRAM controller is a soft IP core designed for Xilinx
+* FPGAs and contains the following general features:
+* - LMB v2.0 bus interfaces with byte enable support
+* - Used in conjunction with bram_block peripheral to provide fast BRAM
+* memory solution for MicroBlaze ILMB and DLMB ports
+* - Supports byte, half-word, and word transfers
+* - Supports optional BRAM error correction and detection.
+*
+* The driver provides interrupt management functions. Implementation of
+* interrupt handlers is left to the user. Refer to the provided interrupt
+* example in the examples directory for details.
+*
+* This driver is intended to be RTOS and processor independent. Any needs for
+* dynamic memory management, threads or thread mutual exclusion, virtual
+* memory, or cache control must be satisfied by the layer above this driver.
+*
+* <b>Initialization & Configuration</b>
+*
+* The XBram_Config structure is used by the driver to configure
+* itself. This configuration structure is typically created by the tool-chain
+* based on HW build properties.
+*
+* To support multiple runtime loading and initialization strategies employed
+* by various operating systems, the driver instance can be initialized as
+* follows:
+*
+* - XBram_CfgInitialize(InstancePtr, CfgPtr, EffectiveAddr) -
+* Uses a configuration structure provided by the caller. If running in a
+* system with address translation, the provided virtual memory base address
+* replaces the physical address present in the configuration structure.
+*
+* @note
+*
+* This API utilizes 32 bit I/O to the BRAM registers. With less
+* than 32 bits, the unused bits from registers are read as zero and written as
+* don't cares.
+*
+* <pre>
+* MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ----- ---- -------- -----------------------------------------------
+* 3.00a sa 05/11/10 Added ECC support
+* 3.01a sa 01/13/12 Changed Selftest API from
+* XBram_SelfTest(XBram *InstancePtr) to
+* XBram_SelfTest(XBram *InstancePtr, u8 IntMask) and
+* fixed a problem with interrupt generation for CR 639274
+* Modified Selftest example to return XST_SUCCESS when
+* ECC is not enabled and return XST_FAILURE when ECC is
+* enabled and Control Base Address is zero (CR 636581)
+* Modified Selftest to use correct CorrectableCounterBits
+* for CR 635655
+* Updated to check CorrectableFailingDataRegs in the case
+* of LMB BRAM.
+* Added CorrectableFailingDataRegs and
+* UncorrectableFailingDataRegs to the config structure to
+* distinguish between AXI BRAM and LMB BRAM.
+* These registers are not present in the current version of
+* the AXI BRAM Controller.
+* 3.02a sa 04/16/12 Added test of byte and halfword read-modify-write
+* 3.02a sa 04/16/12 Modified driver tcl to sort the address parameters
+* to support both xps and vivado designs.
+* 3.02a adk 24/4/13 Modified the tcl file to avoid warnings
+* when ecc is disabled cr:705002.
+* 3.03a bss 05/22/13 Added Xil_DCacheFlushRange in xbram_selftest.c to
+* flush the Cache after writing to BRAM in InjectErrors
+* API(CR #719011)
+* 4.0 adk 19/12/13 Updated as per the New Tcl API's
+* 4.1 sk 11/10/15 Used UINTPTR instead of u32 for Baseaddress CR# 867425.
+* Changed the prototype of XBram_CfgInitialize API.
+* ms 01/23/17 Modified xil_printf statement in main function for all
+* examples to ensure that "Successfully ran" and "Failed"
+* strings are available in all examples. This is a fix
+* for CR-965028.
+* ms 03/17/17 Added readme.txt file in examples folder for doxygen
+* generation.
+* 4.2 ms 04/18/17 Modified tcl file to add suffix U for all macro
+* definitions of bram in xparameters.h
+* ms 08/07/17 Fixed compilation warnings in xbram_sinit.c
+* 4.3 aru 03/23/19 Used UINTPTR instead of u32 for MemBaseAddress and
+* MemHighAddress.
+* </pre>
+*****************************************************************************/
+#ifndef XBRAM_H /* prevent circular inclusions */
+#define XBRAM_H /* by using protection macros */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/***************************** Include Files ********************************/
+
+#include "xil_types.h"
+#include "xil_assert.h"
+#include "xstatus.h"
+#include "xbram_hw.h"
+
+/************************** Constant Definitions ****************************/
+
+
+/**************************** Type Definitions ******************************/
+
+/**
+ * This typedef contains configuration information for the device.
+ */
+typedef struct {
+ u16 DeviceId; /**< Unique ID of device */
+ u32 DataWidth; /**< BRAM data width */
+ int EccPresent; /**< Is ECC supported in H/W */
+ int FaultInjectionPresent; /**< Is Fault Injection
+ * supported in H/W */
+ int CorrectableFailingRegisters; /**< Is Correctable Failing Registers
+ * supported in H/W */
+ int CorrectableFailingDataRegs; /**< Is Correctable Failing Data
+ * Registers supported in H/W */
+ int UncorrectableFailingRegisters; /**< Is Un-correctable Failing
+ * Registers supported in H/W */
+ int UncorrectableFailingDataRegs; /**< Is Un-correctable Failing Data
+ * Registers supported in H/W */
+ int EccStatusInterruptPresent; /**< Are ECC status and interrupts
+ * supported in H/W */
+ int CorrectableCounterBits; /**< Number of bits in the
+ * Correctable Error Counter */
+ int EccOnOffRegister; /**< Is ECC on/off register supported
+ * in h/w */
+ int EccOnOffResetValue; /**< Reset value of the ECC on/off
+ * register in h/w */
+ int WriteAccess; /**< Is write access enabled in
+ * h/w */
+ UINTPTR MemBaseAddress; /**< Device memory base address */
+ UINTPTR MemHighAddress; /**< Device memory high address */
+ UINTPTR CtrlBaseAddress; /**< Device register base address.*/
+ UINTPTR CtrlHighAddress; /**< Device register base address.*/
+} XBram_Config;
+
+/**
+ * The XBram driver instance data. The user is required to
+ * allocate a variable of this type for every BRAM device in the
+ * system. A pointer to a variable of this type is then passed to the driver
+ * API functions.
+ */
+typedef struct {
+ XBram_Config Config; /* BRAM config structure */
+ u32 IsReady; /* Device is initialized and ready */
+} XBram;
+
+/***************** Macros (Inline Functions) Definitions ********************/
+
+
+/************************** Function Prototypes *****************************/
+
+/*
+ * Functions in xbram_sinit.c
+ */
+XBram_Config *XBram_LookupConfig(u16 DeviceId);
+
+/*
+ * Functions implemented in xbram.c
+ */
+int XBram_CfgInitialize(XBram *InstancePtr, XBram_Config *Config,
+ UINTPTR EffectiveAddr);
+
+/*
+ * Functions implemented in xbram_selftest.c
+ */
+int XBram_SelfTest(XBram *InstancePtr, u8 IntMask);
+
+/*
+ * Functions implemented in xbram_intr.c
+ */
+void XBram_InterruptEnable(XBram *InstancePtr, u32 Mask);
+void XBram_InterruptDisable(XBram *InstancePtr, u32 Mask);
+void XBram_InterruptClear(XBram *InstancePtr, u32 Mask);
+u32 XBram_InterruptGetEnabled(XBram *InstancePtr);
+u32 XBram_InterruptGetStatus(XBram *InstancePtr);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* end of protection macro */
+/** @} */
diff --git a/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/bram_v4_3/src/xbram_g.c b/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/bram_v4_3/src/xbram_g.c
new file mode 100644
index 0000000..3e6b6d6
--- /dev/null
+++ b/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/bram_v4_3/src/xbram_g.c
@@ -0,0 +1,119 @@
+
+/*******************************************************************
+*
+* CAUTION: This file is automatically generated by HSI.
+* Version: 2019.2
+* DO NOT EDIT.
+*
+* Copyright (C) 2010-2021 Xilinx, Inc. All Rights Reserved.*
+*Permission is hereby granted, free of charge, to any person obtaining a copy
+*of this software and associated documentation files (the Software), to deal
+*in the Software without restriction, including without limitation the rights
+*to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+*copies of the Software, and to permit persons to whom the Software is
+*furnished to do so, subject to the following conditions:
+*
+*The above copyright notice and this permission notice shall be included in
+*all copies or substantial portions of the Software.
+*
+*THE SOFTWARE IS PROVIDED AS IS, WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+*IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+*FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+*THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+*WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT
+*OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+*
+
+*
+* Description: Driver configuration
+*
+*******************************************************************/
+
+#include "xparameters.h"
+#include "xbram.h"
+
+/*
+* The configuration table for devices
+*/
+
+XBram_Config XBram_ConfigTable[] =
+{
+ {
+ XPAR_I_BRAM_CTRL_EX_STACK_DEVICE_ID,
+ XPAR_I_BRAM_CTRL_EX_STACK_DATA_WIDTH,
+ XPAR_I_BRAM_CTRL_EX_STACK_ECC,
+ XPAR_I_BRAM_CTRL_EX_STACK_FAULT_INJECT,
+ XPAR_I_BRAM_CTRL_EX_STACK_CE_FAILING_REGISTERS,
+ 0,
+ XPAR_I_BRAM_CTRL_EX_STACK_UE_FAILING_REGISTERS,
+ 0,
+ XPAR_I_BRAM_CTRL_EX_STACK_ECC_STATUS_REGISTERS,
+ XPAR_I_BRAM_CTRL_EX_STACK_CE_COUNTER_WIDTH,
+ XPAR_I_BRAM_CTRL_EX_STACK_ECC_ONOFF_REGISTER,
+ XPAR_I_BRAM_CTRL_EX_STACK_ECC_ONOFF_RESET_VALUE,
+ XPAR_I_BRAM_CTRL_EX_STACK_WRITE_ACCESS,
+ XPAR_I_BRAM_CTRL_EX_STACK_S_AXI_BASEADDR,
+ XPAR_I_BRAM_CTRL_EX_STACK_S_AXI_HIGHADDR,
+ XPAR_I_BRAM_CTRL_EX_STACK_S_AXI_CTRL_BASEADDR,
+ XPAR_I_BRAM_CTRL_EX_STACK_S_AXI_CTRL_HIGHADDR
+ },
+ {
+ XPAR_I_BRAM_CTRL_KEY_DEVICE_ID,
+ XPAR_I_BRAM_CTRL_KEY_DATA_WIDTH,
+ XPAR_I_BRAM_CTRL_KEY_ECC,
+ XPAR_I_BRAM_CTRL_KEY_FAULT_INJECT,
+ XPAR_I_BRAM_CTRL_KEY_CE_FAILING_REGISTERS,
+ 0,
+ XPAR_I_BRAM_CTRL_KEY_UE_FAILING_REGISTERS,
+ 0,
+ XPAR_I_BRAM_CTRL_KEY_ECC_STATUS_REGISTERS,
+ XPAR_I_BRAM_CTRL_KEY_CE_COUNTER_WIDTH,
+ XPAR_I_BRAM_CTRL_KEY_ECC_ONOFF_REGISTER,
+ XPAR_I_BRAM_CTRL_KEY_ECC_ONOFF_RESET_VALUE,
+ XPAR_I_BRAM_CTRL_KEY_WRITE_ACCESS,
+ XPAR_I_BRAM_CTRL_KEY_S_AXI_BASEADDR,
+ XPAR_I_BRAM_CTRL_KEY_S_AXI_HIGHADDR,
+ XPAR_I_BRAM_CTRL_KEY_S_AXI_CTRL_BASEADDR,
+ XPAR_I_BRAM_CTRL_KEY_S_AXI_CTRL_HIGHADDR
+ },
+ {
+ XPAR_I_BRAM_CTRL_LOGIC_ANALYZER_DEVICE_ID,
+ XPAR_I_BRAM_CTRL_LOGIC_ANALYZER_DATA_WIDTH,
+ XPAR_I_BRAM_CTRL_LOGIC_ANALYZER_ECC,
+ XPAR_I_BRAM_CTRL_LOGIC_ANALYZER_FAULT_INJECT,
+ XPAR_I_BRAM_CTRL_LOGIC_ANALYZER_CE_FAILING_REGISTERS,
+ 0,
+ XPAR_I_BRAM_CTRL_LOGIC_ANALYZER_UE_FAILING_REGISTERS,
+ 0,
+ XPAR_I_BRAM_CTRL_LOGIC_ANALYZER_ECC_STATUS_REGISTERS,
+ XPAR_I_BRAM_CTRL_LOGIC_ANALYZER_CE_COUNTER_WIDTH,
+ XPAR_I_BRAM_CTRL_LOGIC_ANALYZER_ECC_ONOFF_REGISTER,
+ XPAR_I_BRAM_CTRL_LOGIC_ANALYZER_ECC_ONOFF_RESET_VALUE,
+ XPAR_I_BRAM_CTRL_LOGIC_ANALYZER_WRITE_ACCESS,
+ XPAR_I_BRAM_CTRL_LOGIC_ANALYZER_S_AXI_BASEADDR,
+ XPAR_I_BRAM_CTRL_LOGIC_ANALYZER_S_AXI_HIGHADDR,
+ XPAR_I_BRAM_CTRL_LOGIC_ANALYZER_S_AXI_CTRL_BASEADDR,
+ XPAR_I_BRAM_CTRL_LOGIC_ANALYZER_S_AXI_CTRL_HIGHADDR
+ },
+ {
+ XPAR_I_BRAM_CTRL_SW_ATT_DEVICE_ID,
+ XPAR_I_BRAM_CTRL_SW_ATT_DATA_WIDTH,
+ XPAR_I_BRAM_CTRL_SW_ATT_ECC,
+ XPAR_I_BRAM_CTRL_SW_ATT_FAULT_INJECT,
+ XPAR_I_BRAM_CTRL_SW_ATT_CE_FAILING_REGISTERS,
+ 0,
+ XPAR_I_BRAM_CTRL_SW_ATT_UE_FAILING_REGISTERS,
+ 0,
+ XPAR_I_BRAM_CTRL_SW_ATT_ECC_STATUS_REGISTERS,
+ XPAR_I_BRAM_CTRL_SW_ATT_CE_COUNTER_WIDTH,
+ XPAR_I_BRAM_CTRL_SW_ATT_ECC_ONOFF_REGISTER,
+ XPAR_I_BRAM_CTRL_SW_ATT_ECC_ONOFF_RESET_VALUE,
+ XPAR_I_BRAM_CTRL_SW_ATT_WRITE_ACCESS,
+ XPAR_I_BRAM_CTRL_SW_ATT_S_AXI_BASEADDR,
+ XPAR_I_BRAM_CTRL_SW_ATT_S_AXI_HIGHADDR,
+ XPAR_I_BRAM_CTRL_SW_ATT_S_AXI_CTRL_BASEADDR,
+ XPAR_I_BRAM_CTRL_SW_ATT_S_AXI_CTRL_HIGHADDR
+ }
+};
+
+
diff --git a/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/bram_v4_3/src/xbram_hw.h b/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/bram_v4_3/src/xbram_hw.h
new file mode 100644
index 0000000..be3fbc2
--- /dev/null
+++ b/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/bram_v4_3/src/xbram_hw.h
@@ -0,0 +1,403 @@
+/******************************************************************************
+*
+* Copyright (C) 2011 - 2015 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+* THE SOFTWARE.
+*
+*
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xbram_hw.h
+* @addtogroup bram_v4_2
+* @{
+*
+* This header file contains identifiers and driver functions (or
+* macros) that can be used to access the device. The user should refer to the
+* hardware device specification for more details of the device operation.
+*
+* <pre>
+* MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ----- ---- -------- -----------------------------------------------
+* 1.00a sa 24/11/10 First release
+* </pre>
+*
+******************************************************************************/
+#ifndef XBRAM_HW_H /* prevent circular inclusions */
+#define XBRAM_HW_H /* by using protection macros */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/***************************** Include Files *********************************/
+
+#include "xil_types.h"
+#include "xil_assert.h"
+#include "xil_io.h"
+
+/************************** Constant Definitions *****************************/
+
+/** @name Registers
+ *
+ * Register offsets for this device.
+ * @{
+ */
+
+#define XBRAM_ECC_STATUS_OFFSET 0x0 /**< ECC status Register */
+#define XBRAM_ECC_EN_IRQ_OFFSET 0x4 /**< ECC interrupt enable Register */
+#define XBRAM_ECC_ON_OFF_OFFSET 0x8 /**< ECC on/off register */
+#define XBRAM_CE_CNT_OFFSET 0xC /**< Correctable error counter Register */
+
+#define XBRAM_CE_FFD_0_OFFSET 0x100 /**< Correctable error first failing
+ * data Register, 31-0 */
+#define XBRAM_CE_FFD_1_OFFSET 0x104 /**< Correctable error first failing
+ * data Register, 63-32 */
+#define XBRAM_CE_FFD_2_OFFSET 0x108 /**< Correctable error first failing
+ * data Register, 95-64 */
+#define XBRAM_CE_FFD_3_OFFSET 0x10C /**< Correctable error first failing
+ * data Register, 127-96 */
+#define XBRAM_CE_FFD_4_OFFSET 0x110 /**< Correctable error first failing
+ * data Register, 159-128 */
+#define XBRAM_CE_FFD_5_OFFSET 0x114 /**< Correctable error first failing
+ * data Register, 191-160 */
+#define XBRAM_CE_FFD_6_OFFSET 0x118 /**< Correctable error first failing
+ * data Register, 223-192 */
+#define XBRAM_CE_FFD_7_OFFSET 0x11C /**< Correctable error first failing
+ * data Register, 255-224 */
+#define XBRAM_CE_FFD_8_OFFSET 0x120 /**< Correctable error first failing
+ * data Register, 287-256 */
+#define XBRAM_CE_FFD_9_OFFSET 0x124 /**< Correctable error first failing
+ * data Register, 319-288 */
+#define XBRAM_CE_FFD_10_OFFSET 0x128 /**< Correctable error first failing
+ * data Register, 351-320 */
+#define XBRAM_CE_FFD_11_OFFSET 0x12C /**< Correctable error first failing
+ * data Register, 383-352 */
+#define XBRAM_CE_FFD_12_OFFSET 0x130 /**< Correctable error first failing
+ * data Register, 415-384 */
+#define XBRAM_CE_FFD_13_OFFSET 0x134 /**< Correctable error first failing
+ * data Register, 447-416 */
+#define XBRAM_CE_FFD_14_OFFSET 0x138 /**< Correctable error first failing
+ * data Register, 479-448 */
+#define XBRAM_CE_FFD_15_OFFSET 0x13C /**< Correctable error first failing
+ * data Register, 511-480 */
+#define XBRAM_CE_FFD_16_OFFSET 0x140 /**< Correctable error first failing
+ * data Register, 543-512 */
+#define XBRAM_CE_FFD_17_OFFSET 0x144 /**< Correctable error first failing
+ * data Register, 575-544 */
+#define XBRAM_CE_FFD_18_OFFSET 0x148 /**< Correctable error first failing
+ * data Register, 607-576 */
+#define XBRAM_CE_FFD_19_OFFSET 0x14C /**< Correctable error first failing
+ * data Register, 639-608 */
+#define XBRAM_CE_FFD_20_OFFSET 0x150 /**< Correctable error first failing
+ * data Register, 671-640 */
+#define XBRAM_CE_FFD_21_OFFSET 0x154 /**< Correctable error first failing
+ * data Register, 703-672 */
+#define XBRAM_CE_FFD_22_OFFSET 0x158 /**< Correctable error first failing
+ * data Register, 735-704 */
+#define XBRAM_CE_FFD_23_OFFSET 0x15C /**< Correctable error first failing
+ * data Register, 767-736 */
+#define XBRAM_CE_FFD_24_OFFSET 0x160 /**< Correctable error first failing
+ * data Register, 799-768 */
+#define XBRAM_CE_FFD_25_OFFSET 0x164 /**< Correctable error first failing
+ * data Register, 831-800 */
+#define XBRAM_CE_FFD_26_OFFSET 0x168 /**< Correctable error first failing
+ * data Register, 863-832 */
+#define XBRAM_CE_FFD_27_OFFSET 0x16C /**< Correctable error first failing
+ * data Register, 895-864 */
+#define XBRAM_CE_FFD_28_OFFSET 0x170 /**< Correctable error first failing
+ * data Register, 927-896 */
+#define XBRAM_CE_FFD_29_OFFSET 0x174 /**< Correctable error first failing
+ * data Register, 959-928 */
+#define XBRAM_CE_FFD_30_OFFSET 0x178 /**< Correctable error first failing
+ * data Register, 991-960 */
+#define XBRAM_CE_FFD_31_OFFSET 0x17C /**< Correctable error first failing
+ * data Register, 1023-992 */
+
+#define XBRAM_CE_FFE_0_OFFSET 0x180 /**< Correctable error first failing
+ * ECC Register, 31-0 */
+#define XBRAM_CE_FFE_1_OFFSET 0x184 /**< Correctable error first failing
+ * ECC Register, 63-32 */
+#define XBRAM_CE_FFE_2_OFFSET 0x188 /**< Correctable error first failing
+ * ECC Register, 95-64 */
+#define XBRAM_CE_FFE_3_OFFSET 0x18C /**< Correctable error first failing
+ * ECC Register, 127-96 */
+#define XBRAM_CE_FFE_4_OFFSET 0x190 /**< Correctable error first failing
+ * ECC Register, 159-128 */
+#define XBRAM_CE_FFE_5_OFFSET 0x194 /**< Correctable error first failing
+ * ECC Register, 191-160 */
+#define XBRAM_CE_FFE_6_OFFSET 0x198 /**< Correctable error first failing
+ * ECC Register, 223-192 */
+#define XBRAM_CE_FFE_7_OFFSET 0x19C /**< Correctable error first failing
+ * ECC Register, 255-224 */
+
+#define XBRAM_CE_FFA_0_OFFSET 0x1C0 /**< Correctable error first failing
+ * address Register 31-0 */
+#define XBRAM_CE_FFA_1_OFFSET 0x1C4 /**< Correctable error first failing
+ * address Register 63-32 */
+
+#define XBRAM_UE_FFD_0_OFFSET 0x200 /**< Uncorrectable error first failing
+ * data Register, 31-0 */
+#define XBRAM_UE_FFD_1_OFFSET 0x204 /**< Uncorrectable error first failing
+ * data Register, 63-32 */
+#define XBRAM_UE_FFD_2_OFFSET 0x208 /**< Uncorrectable error first failing
+ * data Register, 95-64 */
+#define XBRAM_UE_FFD_3_OFFSET 0x20C /**< Uncorrectable error first failing
+ * data Register, 127-96 */
+#define XBRAM_UE_FFD_4_OFFSET 0x210 /**< Uncorrectable error first failing
+ * data Register, 159-128 */
+#define XBRAM_UE_FFD_5_OFFSET 0x214 /**< Uncorrectable error first failing
+ * data Register, 191-160 */
+#define XBRAM_UE_FFD_6_OFFSET 0x218 /**< Uncorrectable error first failing
+ * data Register, 223-192 */
+#define XBRAM_UE_FFD_7_OFFSET 0x21C /**< Uncorrectable error first failing
+ * data Register, 255-224 */
+#define XBRAM_UE_FFD_8_OFFSET 0x220 /**< Uncorrectable error first failing
+ * data Register, 287-256 */
+#define XBRAM_UE_FFD_9_OFFSET 0x224 /**< Uncorrectable error first failing
+ * data Register, 319-288 */
+#define XBRAM_UE_FFD_10_OFFSET 0x228 /**< Uncorrectable error first failing
+ * data Register, 351-320 */
+#define XBRAM_UE_FFD_11_OFFSET 0x22C /**< Uncorrectable error first failing
+ * data Register, 383-352 */
+#define XBRAM_UE_FFD_12_OFFSET 0x230 /**< Uncorrectable error first failing
+ * data Register, 415-384 */
+#define XBRAM_UE_FFD_13_OFFSET 0x234 /**< Uncorrectable error first failing
+ * data Register, 447-416 */
+#define XBRAM_UE_FFD_14_OFFSET 0x238 /**< Uncorrectable error first failing
+ * data Register, 479-448 */
+#define XBRAM_UE_FFD_15_OFFSET 0x23C /**< Uncorrectable error first failing
+ * data Register, 511-480 */
+#define XBRAM_UE_FFD_16_OFFSET 0x240 /**< Uncorrectable error first failing
+ * data Register, 543-512 */
+#define XBRAM_UE_FFD_17_OFFSET 0x244 /**< Uncorrectable error first failing
+ * data Register, 575-544 */
+#define XBRAM_UE_FFD_18_OFFSET 0x248 /**< Uncorrectable error first failing
+ * data Register, 607-576 */
+#define XBRAM_UE_FFD_19_OFFSET 0x24C /**< Uncorrectable error first failing
+ * data Register, 639-608 */
+#define XBRAM_UE_FFD_20_OFFSET 0x250 /**< Uncorrectable error first failing
+ * data Register, 671-640 */
+#define XBRAM_UE_FFD_21_OFFSET 0x254 /**< Uncorrectable error first failing
+ * data Register, 703-672 */
+#define XBRAM_UE_FFD_22_OFFSET 0x258 /**< Uncorrectable error first failing
+ * data Register, 735-704 */
+#define XBRAM_UE_FFD_23_OFFSET 0x25C /**< Uncorrectable error first failing
+ * data Register, 767-736 */
+#define XBRAM_UE_FFD_24_OFFSET 0x260 /**< Uncorrectable error first failing
+ * data Register, 799-768 */
+#define XBRAM_UE_FFD_25_OFFSET 0x264 /**< Uncorrectable error first failing
+ * data Register, 831-800 */
+#define XBRAM_UE_FFD_26_OFFSET 0x268 /**< Uncorrectable error first failing
+ * data Register, 863-832 */
+#define XBRAM_UE_FFD_27_OFFSET 0x26C /**< Uncorrectable error first failing
+ * data Register, 895-864 */
+#define XBRAM_UE_FFD_28_OFFSET 0x270 /**< Uncorrectable error first failing
+ * data Register, 927-896 */
+#define XBRAM_UE_FFD_29_OFFSET 0x274 /**< Uncorrectable error first failing
+ * data Register, 959-928 */
+#define XBRAM_UE_FFD_30_OFFSET 0x278 /**< Uncorrectable error first failing
+ * data Register, 991-960 */
+#define XBRAM_UE_FFD_31_OFFSET 0x27C /**< Uncorrectable error first failing
+ * data Register, 1023-992 */
+
+#define XBRAM_UE_FFE_0_OFFSET 0x280 /**< Uncorrectable error first failing
+ * ECC Register, 31-0 */
+#define XBRAM_UE_FFE_1_OFFSET 0x284 /**< Uncorrectable error first failing
+ * ECC Register, 63-32 */
+#define XBRAM_UE_FFE_2_OFFSET 0x288 /**< Uncorrectable error first failing
+ * ECC Register, 95-64 */
+#define XBRAM_UE_FFE_3_OFFSET 0x28C /**< Uncorrectable error first failing
+ * ECC Register, 127-96 */
+#define XBRAM_UE_FFE_4_OFFSET 0x290 /**< Uncorrectable error first failing
+ * ECC Register, 159-128 */
+#define XBRAM_UE_FFE_5_OFFSET 0x294 /**< Uncorrectable error first failing
+ * ECC Register, 191-160 */
+#define XBRAM_UE_FFE_6_OFFSET 0x298 /**< Uncorrectable error first failing
+ * ECC Register, 223-192 */
+#define XBRAM_UE_FFE_7_OFFSET 0x29C /**< Uncorrectable error first failing
+ * ECC Register, 255-224 */
+
+#define XBRAM_UE_FFA_0_OFFSET 0x2C0 /**< Uncorrectable error first failing
+ * address Register 31-0 */
+#define XBRAM_UE_FFA_1_OFFSET 0x2C4 /**< Uncorrectable error first failing
+ * address Register 63-32 */
+
+#define XBRAM_FI_D_0_OFFSET 0x300 /**< Fault injection Data Register,
+ * 31-0 */
+#define XBRAM_FI_D_1_OFFSET 0x304 /**< Fault injection Data Register,
+ * 63-32 */
+#define XBRAM_FI_D_2_OFFSET 0x308 /**< Fault injection Data Register,
+ * 95-64 */
+#define XBRAM_FI_D_3_OFFSET 0x30C /**< Fault injection Data Register,
+ * 127-96 */
+#define XBRAM_FI_D_4_OFFSET 0x310 /**< Fault injection Data Register,
+ * 159-128 */
+#define XBRAM_FI_D_5_OFFSET 0x314 /**< Fault injection Data Register,
+ * 191-160 */
+#define XBRAM_FI_D_6_OFFSET 0x318 /**< Fault injection Data Register,
+ * 223-192 */
+#define XBRAM_FI_D_7_OFFSET 0x31C /**< Fault injection Data Register,
+ * 255-224 */
+#define XBRAM_FI_D_8_OFFSET 0x320 /**< Fault injection Data Register,
+ * 287-256 */
+#define XBRAM_FI_D_9_OFFSET 0x324 /**< Fault injection Data Register,
+ * 319-288 */
+#define XBRAM_FI_D_10_OFFSET 0x328 /**< Fault injection Data Register,
+ * 351-320 */
+#define XBRAM_FI_D_11_OFFSET 0x32C /**< Fault injection Data Register,
+ * 383-352 */
+#define XBRAM_FI_D_12_OFFSET 0x330 /**< Fault injection Data Register,
+ * 415-384 */
+#define XBRAM_FI_D_13_OFFSET 0x334 /**< Fault injection Data Register,
+ * 447-416 */
+#define XBRAM_FI_D_14_OFFSET 0x338 /**< Fault injection Data Register,
+ * 479-448 */
+#define XBRAM_FI_D_15_OFFSET 0x33C /**< Fault injection Data Register,
+ * 511-480 */
+#define XBRAM_FI_D_16_OFFSET 0x340 /**< Fault injection Data Register,
+ * 543-512 */
+#define XBRAM_FI_D_17_OFFSET 0x344 /**< Fault injection Data Register,
+ * 575-544 */
+#define XBRAM_FI_D_18_OFFSET 0x348 /**< Fault injection Data Register,
+ * 607-576 */
+#define XBRAM_FI_D_19_OFFSET 0x34C /**< Fault injection Data Register,
+ * 639-608 */
+#define XBRAM_FI_D_20_OFFSET 0x350 /**< Fault injection Data Register,
+ * 671-640 */
+#define XBRAM_FI_D_21_OFFSET 0x354 /**< Fault injection Data Register,
+ * 703-672 */
+#define XBRAM_FI_D_22_OFFSET 0x358 /**< Fault injection Data Register,
+ * 735-704 */
+#define XBRAM_FI_D_23_OFFSET 0x35C /**< Fault injection Data Register,
+ * 767-736 */
+#define XBRAM_FI_D_24_OFFSET 0x360 /**< Fault injection Data Register,
+ * 799-768 */
+#define XBRAM_FI_D_25_OFFSET 0x364 /**< Fault injection Data Register,
+ * 831-800 */
+#define XBRAM_FI_D_26_OFFSET 0x368 /**< Fault injection Data Register,
+ * 863-832 */
+#define XBRAM_FI_D_27_OFFSET 0x36C /**< Fault injection Data Register,
+ * 895-864 */
+#define XBRAM_FI_D_28_OFFSET 0x370 /**< Fault injection Data Register,
+ * 927-896 */
+#define XBRAM_FI_D_29_OFFSET 0x374 /**< Fault injection Data Register,
+ * 959-928 */
+#define XBRAM_FI_D_30_OFFSET 0x378 /**< Fault injection Data Register,
+ * 991-960 */
+#define XBRAM_FI_D_31_OFFSET 0x37C /**< Fault injection Data Register,
+ * 1023-992 */
+
+#define XBRAM_FI_ECC_0_OFFSET 0x380 /**< Fault injection ECC Register,
+ * 31-0 */
+#define XBRAM_FI_ECC_1_OFFSET 0x384 /**< Fault injection ECC Register,
+ * 63-32 */
+#define XBRAM_FI_ECC_2_OFFSET 0x388 /**< Fault injection ECC Register,
+ * 95-64 */
+#define XBRAM_FI_ECC_3_OFFSET 0x38C /**< Fault injection ECC Register,
+ * 127-96 */
+#define XBRAM_FI_ECC_4_OFFSET 0x390 /**< Fault injection ECC Register,
+ * 159-128 */
+#define XBRAM_FI_ECC_5_OFFSET 0x394 /**< Fault injection ECC Register,
+ * 191-160 */
+#define XBRAM_FI_ECC_6_OFFSET 0x398 /**< Fault injection ECC Register,
+ * 223-192 */
+#define XBRAM_FI_ECC_7_OFFSET 0x39C /**< Fault injection ECC Register,
+ * 255-224 */
+
+
+/* @} */
+
+/** @name Interrupt Status and Enable Register bitmaps and masks
+ *
+ * Bit definitions for the ECC status register and ECC interrupt enable register.
+ * @{
+ */
+#define XBRAM_IR_CE_MASK 0x2 /**< Mask for the correctable error */
+#define XBRAM_IR_UE_MASK 0x1 /**< Mask for the uncorrectable error */
+#define XBRAM_IR_ALL_MASK 0x3 /**< Mask of all bits */
+/*@}*/
+
+
+/**************************** Type Definitions *******************************/
+
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+#define XBram_In32 Xil_In32
+#define XBram_Out32 Xil_Out32
+
+#define XBram_In16 Xil_In16
+#define XBram_Out16 Xil_Out16
+
+#define XBram_In8 Xil_In8
+#define XBram_Out8 Xil_Out8
+
+
+/****************************************************************************/
+/**
+*
+* Write a value to a BRAM register. A 32 bit write is performed.
+*
+* @param BaseAddress is the base address of the BRAM device register.
+* @param RegOffset is the register offset from the base to write to.
+* @param Data is the data written to the register.
+*
+* @return None.
+*
+* @note C-style signature:
+* void XBram_WriteReg(u32 BaseAddress, u32 RegOffset, u32 Data)
+*
+****************************************************************************/
+#define XBram_WriteReg(BaseAddress, RegOffset, Data) \
+ XBram_Out32((BaseAddress) + (RegOffset), (u32)(Data))
+
+/****************************************************************************/
+/**
+*
+* Read a value from a BRAM register. A 32 bit read is performed.
+*
+* @param BaseAddress is the base address of the BRAM device registers.
+* @param RegOffset is the register offset from the base to read from.
+*
+* @return Data read from the register.
+*
+* @note C-style signature:
+* u32 XBram_ReadReg(u32 BaseAddress, u32 RegOffset)
+*
+****************************************************************************/
+#define XBram_ReadReg(BaseAddress, RegOffset) \
+ XBram_In32((BaseAddress) + (RegOffset))
+
+/************************** Function Prototypes ******************************/
+
+/************************** Variable Definitions *****************************/
+
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* end of protection macro */
+/** @} */
diff --git a/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/bram_v4_3/src/xbram_intr.c b/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/bram_v4_3/src/xbram_intr.c
new file mode 100644
index 0000000..9d08f2a
--- /dev/null
+++ b/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/bram_v4_3/src/xbram_intr.c
@@ -0,0 +1,232 @@
+/******************************************************************************
+*
+* Copyright (C) 2010 - 2015 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+* THE SOFTWARE.
+*
+*
+*
+******************************************************************************/
+
+/*****************************************************************************/
+/**
+* @file xbram_intr.c
+* @addtogroup bram_v4_2
+* @{
+*
+* Implements BRAM interrupt processing functions for the
+* XBram driver. See xbram.h for more information
+* about the driver.
+*
+* The functions in this file require the hardware device to be built with
+* interrupt capabilities. The functions will assert if called using hardware
+* that does not have interrupt capabilities.
+*
+* <pre>
+* MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ----- ---- -------- -----------------------------------------------
+* 1.00a sa 05/11/10 Initial release
+* </pre>
+*
+*****************************************************************************/
+
+/***************************** Include Files ********************************/
+#include "xbram.h"
+
+
+/************************** Constant Definitions ****************************/
+
+/**************************** Type Definitions ******************************/
+
+/***************** Macros (Inline Functions) Definitions ********************/
+
+/************************** Variable Definitions ****************************/
+
+/************************** Function Prototypes *****************************/
+
+
+/****************************************************************************/
+/**
+* Enable interrupts. This function will assert if the hardware device has not
+* been built with interrupt capabilities.
+*
+* @param InstancePtr is the BRAM instance to operate on.
+* @param Mask is the mask to enable. Bit positions of 1 are enabled.
+* This mask is formed by OR'ing bits from XBRAM_IR*
+* bits which are contained in xbram_hw.h.
+*
+* @return None.
+*
+* @note None.
+*
+*****************************************************************************/
+void XBram_InterruptEnable(XBram *InstancePtr, u32 Mask)
+{
+ u32 Register;
+
+ Xil_AssertVoid(InstancePtr != NULL);
+ Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+ Xil_AssertVoid(InstancePtr->Config.CtrlBaseAddress != 0);
+
+ /*
+ * Read the interrupt enable register and only enable the specified
+ * interrupts without disabling or enabling any others.
+ */
+ Register = XBram_ReadReg(InstancePtr->Config.CtrlBaseAddress,
+ XBRAM_ECC_EN_IRQ_OFFSET);
+ XBram_WriteReg(InstancePtr->Config.CtrlBaseAddress,
+ XBRAM_ECC_EN_IRQ_OFFSET,
+ Register | Mask);
+}
+
+
+/****************************************************************************/
+/**
+* Disable interrupts. This function allows each specific interrupt to be
+* disabled. This function will assert if the hardware device has not been
+* built with interrupt capabilities.
+*
+* @param InstancePtr is the BRAM instance to operate on.
+* @param Mask is the mask to disable. Bits set to 1 are disabled. This
+* mask is formed by OR'ing bits from XBRAM_IR* bits
+* which are contained in xbram_hw.h.
+*
+* @return None.
+*
+* @note None.
+*
+*****************************************************************************/
+void XBram_InterruptDisable(XBram *InstancePtr, u32 Mask)
+{
+ u32 Register;
+
+ Xil_AssertVoid(InstancePtr != NULL);
+ Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+ Xil_AssertVoid(InstancePtr->Config.CtrlBaseAddress != 0);
+
+ /*
+ * Read the interrupt enable register and only disable the specified
+ * interrupts without enabling or disabling any others.
+ */
+ Register = XBram_ReadReg(InstancePtr->Config.CtrlBaseAddress,
+ XBRAM_ECC_EN_IRQ_OFFSET);
+ XBram_WriteReg(InstancePtr->Config.CtrlBaseAddress,
+ XBRAM_ECC_EN_IRQ_OFFSET,
+ Register & (~Mask));
+}
+
+/****************************************************************************/
+/**
+* Clear pending interrupts with the provided mask. This function should be
+* called after the software has serviced the interrupts that are pending.
+* This function will assert if the hardware device has not been built with
+* interrupt capabilities.
+*
+* @param InstancePtr is the BRAM instance to operate on.
+* @param Mask is the mask to clear pending interrupts for. Bit positions
+* of 1 are cleared. This mask is formed by OR'ing bits from
+* XBRAM_IR* bits which are contained in
+* xbram_hw.h.
+*
+* @return None.
+*
+* @note None.
+*
+*****************************************************************************/
+void XBram_InterruptClear(XBram *InstancePtr, u32 Mask)
+{
+ u32 Register;
+
+ Xil_AssertVoid(InstancePtr != NULL);
+ Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+ Xil_AssertVoid(InstancePtr->Config.CtrlBaseAddress != 0);
+
+ /*
+ * Read the interrupt status register and only clear the interrupts
+ * that are specified without affecting any others. Since the register
+ * is a toggle on write, make sure any bits to be written are already
+ * set.
+ */
+ Register = XBram_ReadReg(InstancePtr->Config.CtrlBaseAddress,
+ XBRAM_ECC_STATUS_OFFSET);
+ XBram_WriteReg(InstancePtr->Config.CtrlBaseAddress,
+ XBRAM_ECC_STATUS_OFFSET,
+ Register & Mask);
+
+
+}
+
+
+/****************************************************************************/
+/**
+* Returns the interrupt enable mask. This function will assert if the
+* hardware device has not been built with interrupt capabilities.
+*
+* @param InstancePtr is the BRAM instance to operate on.
+*
+* @return A mask of bits made from XBRAM_IR* bits which
+* are contained in xbram_hw.h.
+*
+* @return None.
+*
+* @note None.
+*
+*****************************************************************************/
+u32 XBram_InterruptGetEnabled(XBram * InstancePtr)
+{
+ Xil_AssertNonvoid(InstancePtr != NULL);
+ Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+ Xil_AssertNonvoid(InstancePtr->Config.CtrlBaseAddress != 0);
+
+ return XBram_ReadReg(InstancePtr->Config.CtrlBaseAddress,
+ XBRAM_ECC_EN_IRQ_OFFSET);
+}
+
+
+/****************************************************************************/
+/**
+* Returns the status of interrupt signals. Any bit in the mask set to 1
+* indicates that the channel associated with the bit has asserted an interrupt
+* condition. This function will assert if the hardware device has not been
+* built with interrupt capabilities.
+*
+* @param InstancePtr is the BRAM instance to operate on.
+*
+* @return A pointer to a mask of bits made from XBRAM_IR*
+* bits which are contained in xbram_hw.h.
+*
+* @note
+*
+* The interrupt status indicates the status of the device regardless if
+* the interrupts from the devices have been enabled or not through
+* XBram_InterruptEnable().
+*
+*****************************************************************************/
+u32 XBram_InterruptGetStatus(XBram * InstancePtr)
+{
+ Xil_AssertNonvoid(InstancePtr != NULL);
+ Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+ Xil_AssertNonvoid(InstancePtr->Config.CtrlBaseAddress != 0);
+
+ return XBram_ReadReg(InstancePtr->Config.CtrlBaseAddress,
+ XBRAM_ECC_EN_IRQ_OFFSET);
+}
+/** @} */
diff --git a/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/bram_v4_3/src/xbram_selftest.c b/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/bram_v4_3/src/xbram_selftest.c
new file mode 100644
index 0000000..220516f
--- /dev/null
+++ b/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/bram_v4_3/src/xbram_selftest.c
@@ -0,0 +1,555 @@
+/******************************************************************************
+*
+* Copyright (C) 2011 - 2019 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+* THE SOFTWARE.
+*
+*
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+* @file xbram_selftest.c
+* @addtogroup bram_v4_2
+* @{
+*
+* The implementation of the XBram driver's self test function. This SelfTest
+* is only applicable if ECC is enabled.
+* If ECC is not enabled then this function will return XST_SUCCESS.
+* See xbram.h for more information about the driver.
+* Temp change
+*
+* @note
+*
+* None
+*
+* <pre>
+* MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ----- ---- -------- -----------------------------------------------
+* 1.00a sa 11/24/10 First release
+* 3.01a sa 01/13/12 Changed Selftest API from
+* XBram_SelfTest(XBram *InstancePtr) to
+* XBram_SelfTest(XBram *InstancePtr, u8 IntMask) and
+* fixed a problem with interrupt generation for CR 639274
+* Modified Selftest example to return XST_SUCCESS when
+* ECC is not enabled and return XST_FAILURE when ECC is
+* enabled and Control Base Address is zero (CR 636581)
+* Modified Selftest to use correct CorrectableCounterBits
+* for CR 635655
+* Updated to check CorrectableFailingDataRegs in the case
+* of LMB BRAM.
+* 3.02a sa 04/16/12 Added test of byte and halfword read-modify-write
+* 3.03a bss 05/22/13 Added Xil_DCacheFlushRange in InjectErrors API to
+* flush the Cache after writing to BRAM (CR #719011)
+* 4.3 aru 04/09/19 Used UINTPTR instead of u32 for Addr in XBram_SelfTest()
+*
+* </pre>
+*****************************************************************************/
+
+/***************************** Include Files ********************************/
+#include "xbram.h"
+#include "xil_cache.h"
+/************************** Constant Definitions ****************************/
+#define TOTAL_BITS 39
+
+/**************************** Type Definitions ******************************/
+
+/***************** Macros (Inline Functions) Definitions ********************/
+#define RD(reg) XBram_ReadReg(InstancePtr->Config.CtrlBaseAddress, \
+ XBRAM_ ## reg)
+#define WR(reg, data) XBram_WriteReg(InstancePtr->Config.CtrlBaseAddress, \
+ XBRAM_ ## reg, data)
+
+#define CHECK(reg, data, result) if (result!=XST_SUCCESS || RD(reg)!=data) \
+ result = XST_FAILURE;
+
+/************************** Variable Definitions ****************************/
+static u32 PrngResult;
+
+/************************** Function Prototypes *****************************/
+static inline u32 PrngData(u32 *PrngResult);
+
+static inline u32 CalculateEcc(u32 Data);
+
+static void InjectErrors(XBram * InstancePtr, UINTPTR Addr,
+ int Index1, int Index2, int Width,
+ u32 *ActualData, u32 *ActualEcc);
+
+
+/*****************************************************************************/
+/**
+* Generate a pseudo random number.
+*
+* @param The PrngResult is the previous random number in the pseudo
+* random sequence, also known as the seed. It is modified to
+* the calculated pseudo random number by the function.
+*
+* @return The generated pseudo random number
+*
+* @note None.
+*
+******************************************************************************/
+static inline u32 PrngData(u32 *PrngResult)
+{
+ *PrngResult = *PrngResult * 0x77D15E25 + 0x3617C161;
+ return *PrngResult;
+}
+
+
+/*****************************************************************************/
+/**
+* Calculate ECC from Data.
+*
+* @param The Data Value
+*
+* @return The calculated ECC
+*
+* @note None.
+*
+******************************************************************************/
+static inline u32 CalculateEcc(u32 Data)
+{
+ unsigned char c[7], d[32];
+ u32 Result = 0;
+ int Index;
+
+ for (Index = 0; Index < 32; Index++) {
+ d[31 - Index] = Data & 1;
+ Data = Data >> 1;
+ }
+
+ c[0] = d[0] ^ d[1] ^ d[3] ^ d[4] ^ d[6] ^ d[8] ^ d[10] ^ d[11] ^
+ d[13] ^ d[15] ^ d[17] ^ d[19] ^ d[21] ^ d[23] ^ d[25] ^ d[26] ^
+ d[28] ^ d[30];
+
+ c[1] = d[0] ^ d[2] ^ d[3] ^ d[5] ^ d[6] ^ d[9] ^ d[10] ^ d[12] ^
+ d[13] ^ d[16] ^ d[17] ^ d[20] ^ d[21] ^ d[24] ^ d[25] ^ d[27] ^
+ d[28] ^ d[31];
+
+ c[2] = d[1] ^ d[2] ^ d[3] ^ d[7] ^ d[8] ^ d[9] ^ d[10] ^ d[14] ^
+ d[15] ^ d[16] ^ d[17] ^ d[22] ^ d[23] ^ d[24] ^ d[25] ^ d[29] ^
+ d[30] ^ d[31];
+
+ c[3] = d[4] ^ d[5] ^ d[6] ^ d[7] ^ d[8] ^ d[9] ^ d[10] ^ d[18] ^
+ d[19] ^ d[20] ^ d[21] ^ d[22] ^ d[23] ^ d[24] ^ d[25];
+
+ c[4] = d[11] ^ d[12] ^ d[13] ^ d[14] ^ d[15] ^ d[16] ^ d[17] ^ d[18] ^
+ d[19] ^ d[20] ^ d[21] ^ d[22] ^ d[23] ^ d[24] ^ d[25];
+
+ c[5] = d[26] ^ d[27] ^ d[28] ^ d[29] ^ d[30] ^ d[31];
+
+ c[6] = d[0] ^ d[1] ^ d[2] ^ d[3] ^ d[4] ^ d[5] ^ d[6] ^ d[7] ^
+ d[8] ^ d[9] ^ d[10] ^ d[11] ^ d[12] ^ d[13] ^ d[14] ^ d[15] ^
+ d[16] ^ d[17] ^ d[18] ^ d[19] ^ d[20] ^ d[21] ^ d[22] ^ d[23] ^
+ d[24] ^ d[25] ^ d[26] ^ d[27] ^ d[28] ^ d[29] ^ d[30] ^ d[31] ^
+ c[5] ^ c[4] ^ c[3] ^ c[2] ^ c[1] ^ c[0];
+
+ for (Index = 0; Index < 7; Index++) {
+ Result = Result << 1;
+ Result |= c[Index] & 1;
+ }
+
+ return Result;
+}
+
+/*****************************************************************************/
+/**
+* Get the expected actual data read in case of uncorrectable errors.
+*
+* @param The injected data value including errors (if any)
+* @param The syndrome (calculated ecc ^ actual ecc read)
+*
+* @return The actual data value read
+*
+* @note None.
+*
+******************************************************************************/
+static inline u32 UncorrectableData(u32 Data, u8 Syndrome)
+{
+ switch (Syndrome) {
+ case 0x03: return Data ^ 0x00000034;
+ case 0x05: return Data ^ 0x001a2000;
+ case 0x09: return Data ^ 0x0d000000;
+ case 0x0d: return Data ^ 0x00001a00;
+
+ case 0x11: return Data ^ 0x60000000;
+ case 0x13: return Data ^ 0x00000003;
+ case 0x15: return Data ^ 0x00018000;
+ case 0x19: return Data ^ 0x00c00000;
+ case 0x1d: return Data ^ 0x00000180;
+
+ case 0x21: return Data ^ 0x80000000;
+ case 0x23: return Data ^ 0x00000008;
+ case 0x25: return Data ^ 0x00040000;
+ case 0x29: return Data ^ 0x02000000;
+ case 0x2d: return Data ^ 0x00000400;
+
+ case 0x31: return Data ^ 0x10000000;
+ case 0x35: return Data ^ 0x00004000;
+ case 0x39: return Data ^ 0x00200000;
+ case 0x3d: return Data ^ 0x00000040;
+ }
+ return Data;
+}
+
+/*****************************************************************************/
+/**
+* Inject errors using the hardware fault injection functionality, and write
+* random data and read it back using the indicated location.
+*
+* @param InstancePtr is a pointer to the XBram instance to
+* be worked on.
+* @param The Addr is the indicated memory location to use
+* @param The Index1 is the bit location of the first injected error
+* @param The Index2 is the bit location of the second injected error
+* @param The Width is the data byte width
+* @param The ActualData is filled in with expected data for checking
+* @param The ActualEcc is filled in with expected ECC for checking
+*
+* @return None
+*
+* @note None.
+*
+******************************************************************************/
+static void InjectErrors(XBram * InstancePtr, UINTPTR Addr,
+ int Index1, int Index2, int Width,
+ u32 *ActualData, u32 *ActualEcc)
+{
+ u32 InjectedData = 0;
+ u32 InjectedEcc = 0;
+ u32 RandomData = PrngData(&PrngResult);
+
+ if (Index1 < 32) {
+ InjectedData = 1 << Index1;
+ } else {
+ InjectedEcc = 1 << (Index1 - 32);
+ }
+
+ if (Index2 < 32) {
+ InjectedData |= (1 << Index2);
+ } else {
+ InjectedEcc |= 1 << (Index2 - 32);
+ }
+
+ WR(FI_D_0_OFFSET, InjectedData);
+ WR(FI_ECC_0_OFFSET, InjectedEcc);
+
+ XBram_Out32(Addr, RandomData);
+ Xil_DCacheFlushRange(Addr, 4);
+ switch (Width) {
+ case 1: /* Byte - Write to do Read-Modify-Write */
+ XBram_Out8(Addr, PrngData(&PrngResult) & 0xFF);
+ break;
+ case 2: /* Halfword - Write to do Read-Modify-Write */
+ XBram_Out16(Addr, PrngData(&PrngResult) & 0xFFFF);
+ break;
+ case 4: /* Word - Read */
+ (void) XBram_In32(Addr);
+ break;
+ }
+ *ActualData = InjectedData ^ RandomData;
+ *ActualEcc = InjectedEcc ^ CalculateEcc(RandomData);
+}
+
+
+/*****************************************************************************/
+/**
+* Run a self-test on the driver/device. Unless fault injection is implemented
+* in hardware, this function only does a minimal test in which available
+* registers (if any) are written and read.
+*
+* With fault injection, all possible single-bit and double-bit errors are
+* injected, and checked to the extent possible, given the implemented hardware.
+*
+* @param InstancePtr is a pointer to the XBram instance.
+* @param IntMask is the interrupt mask to use. When testing
+* with interrupts, this should be set to allow interrupt
+* generation, otherwise it should be 0.
+*
+* @return
+* - XST_SUCCESS if fault injection/detection is working properly OR
+* if ECC is Not Enabled in the HW.
+* - XST_FAILURE if the injected fault is not correctly detected or
+* the Control Base Address is Zero when ECC is enabled.
+* .
+*
+* If the BRAM device is not present in the
+* hardware a bus error could be generated. Other indicators of a
+* bus error, such as registers in bridges or buses, may be
+* necessary to determine if this function caused a bus error.
+*
+* @note None.
+*
+******************************************************************************/
+int XBram_SelfTest(XBram *InstancePtr, u8 IntMask)
+{
+ Xil_AssertNonvoid(InstancePtr != NULL);
+ Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+
+
+ if (InstancePtr->Config.EccPresent == 0) {
+ return (XST_SUCCESS);
+ }
+
+ if (InstancePtr->Config.CtrlBaseAddress == 0) {
+ return (XST_SUCCESS);
+ }
+
+ /*
+ * Only 32-bit data width is supported as of yet. 64-bit and 128-bit
+ * widths will be supported in future.
+ */
+ if (InstancePtr->Config.DataWidth != 32)
+ return (XST_SUCCESS);
+
+ /*
+ * Read from the implemented readable registers in the hardware device.
+ */
+ if (InstancePtr->Config.CorrectableFailingRegisters) {
+ (void) RD(CE_FFA_0_OFFSET);
+ }
+ if (InstancePtr->Config.CorrectableFailingDataRegs) {
+ (void) RD(CE_FFD_0_OFFSET);
+ (void) RD(CE_FFE_0_OFFSET);
+ }
+ if (InstancePtr->Config.UncorrectableFailingRegisters) {
+ (void) RD(UE_FFA_0_OFFSET);
+ }
+ if (InstancePtr->Config.UncorrectableFailingDataRegs) {
+ (void) RD(UE_FFD_0_OFFSET);
+ (void) RD(UE_FFE_0_OFFSET);
+ }
+
+ /*
+ * Write and read the implemented read/write registers in the hardware
+ * device.
+ */
+ if (InstancePtr->Config.EccStatusInterruptPresent) {
+ WR(ECC_EN_IRQ_OFFSET, 0);
+ if (RD(ECC_EN_IRQ_OFFSET) != 0) {
+ return (XST_FAILURE);
+ }
+ }
+
+ if (InstancePtr->Config.CorrectableCounterBits > 0) {
+ u32 Value;
+
+ /* Calculate counter max value */
+ if (InstancePtr->Config.CorrectableCounterBits == 32) {
+ Value = 0xFFFFFFFF;
+ } else {
+ Value = (1 <<
+ InstancePtr->Config.CorrectableCounterBits) - 1;
+ }
+
+ WR(CE_CNT_OFFSET, Value);
+ if (RD(CE_CNT_OFFSET) != Value) {
+ return (XST_FAILURE);
+ }
+
+ WR(CE_CNT_OFFSET, 0);
+ if (RD(CE_CNT_OFFSET) != 0) {
+ return (XST_FAILURE);
+ }
+ }
+
+ /*
+ * If fault injection is implemented, inject all possible single-bit
+ * and double-bit errors, and check all observable effects.
+ */
+ if (InstancePtr->Config.FaultInjectionPresent &&
+ InstancePtr->Config.WriteAccess != 0) {
+
+ const UINTPTR Addr[2] = {InstancePtr->Config.MemBaseAddress &
+ (UINTPTR)0xfffffffffffffffc,
+ InstancePtr->Config.MemHighAddress &
+ (UINTPTR)0xfffffffffffffffc};
+ u32 SavedWords[2];
+ u32 ActualData;
+ u32 ActualEcc;
+ u32 CounterValue = 0;
+ u32 CounterMax;
+ int WordIndex = 0;
+ int Result = XST_SUCCESS;
+ int Index1;
+ int Index2;
+ int Width;
+
+ PrngResult = 42; /* Random seed */
+
+ /* Save two words in BRAM used for test */
+ SavedWords[0] = XBram_In32(Addr[0]);
+ SavedWords[1] = XBram_In32(Addr[1]);
+
+ for (Width = 1; Width <= 4; Width <<= 1) {
+ /* Calculate counter max value */
+ if (InstancePtr->Config.CorrectableCounterBits == 32) {
+ CounterMax = 0xFFFFFFFF;
+ } else {
+ CounterMax =(1 <<
+ InstancePtr->Config.CorrectableCounterBits) - 1;
+ }
+
+ /* Inject and check all single bit errors */
+ for (Index1 = 0; Index1 < TOTAL_BITS; Index1++) {
+ /* Save counter value */
+ if (InstancePtr->Config.CorrectableCounterBits > 0) {
+ CounterValue = RD(CE_CNT_OFFSET);
+ }
+
+ /* Inject single bit error */
+ InjectErrors(InstancePtr, Addr[WordIndex], Index1,
+ Index1, Width, &ActualData, &ActualEcc);
+
+ /* Check that CE is set */
+ if (InstancePtr->Config.EccStatusInterruptPresent) {
+ CHECK(ECC_STATUS_OFFSET,
+ XBRAM_IR_CE_MASK, Result);
+ }
+
+ /* Check that address, data, ECC are correct */
+ if (InstancePtr->Config.CorrectableFailingRegisters) {
+ CHECK(CE_FFA_0_OFFSET, Addr[WordIndex], Result);
+ }
+ /* Checks are only for LMB BRAM */
+ if (InstancePtr->Config.CorrectableFailingDataRegs) {
+ CHECK(CE_FFD_0_OFFSET, ActualData, Result);
+ CHECK(CE_FFE_0_OFFSET, ActualEcc, Result);
+ }
+
+ /* Check that counter has incremented */
+ if (InstancePtr->Config.CorrectableCounterBits > 0 &&
+ CounterValue < CounterMax) {
+ CHECK(CE_CNT_OFFSET,
+ CounterValue + 1, Result);
+ }
+
+ /* Restore correct data in the used word */
+ XBram_Out32(Addr[WordIndex], SavedWords[WordIndex]);
+
+ /* Allow interrupts to occur */
+ /* Clear status register */
+ if (InstancePtr->Config.EccStatusInterruptPresent) {
+ WR(ECC_EN_IRQ_OFFSET, IntMask);
+ WR(ECC_STATUS_OFFSET, XBRAM_IR_ALL_MASK);
+ WR(ECC_EN_IRQ_OFFSET, 0);
+ }
+
+ /* Switch to the other word */
+ WordIndex = WordIndex ^ 1;
+
+ if (Result != XST_SUCCESS) break;
+
+ }
+
+ if (Result != XST_SUCCESS) {
+ return XST_FAILURE;
+ }
+
+ for (Index1 = 0; Index1 < TOTAL_BITS; Index1++) {
+ for (Index2 = 0; Index2 < TOTAL_BITS; Index2++) {
+ if (Index1 != Index2) {
+ /* Inject double bit error */
+ InjectErrors(InstancePtr,
+ Addr[WordIndex],
+ Index1, Index2, Width,
+ &ActualData,
+ &ActualEcc);
+
+ /* Check that UE is set */
+ if (InstancePtr->Config.
+ EccStatusInterruptPresent) {
+ CHECK(ECC_STATUS_OFFSET,
+ XBRAM_IR_UE_MASK,
+ Result);
+ }
+
+ /* Check that address, data, ECC are correct */
+ if (InstancePtr->Config.
+ UncorrectableFailingRegisters) {
+ CHECK(UE_FFA_0_OFFSET, Addr[WordIndex],
+ Result);
+ CHECK(UE_FFD_0_OFFSET,
+ ActualData, Result);
+ CHECK(UE_FFE_0_OFFSET, ActualEcc,
+ Result);
+ }
+
+ /* Restore correct data in the used word */
+ XBram_Out32(Addr[WordIndex],
+ SavedWords[WordIndex]);
+
+ /* Allow interrupts to occur */
+ /* Clear status register */
+ if (InstancePtr->Config.
+ EccStatusInterruptPresent) {
+ WR(ECC_EN_IRQ_OFFSET, IntMask);
+ WR(ECC_STATUS_OFFSET,
+ XBRAM_IR_ALL_MASK);
+ WR(ECC_EN_IRQ_OFFSET, 0);
+ }
+
+ /* Switch to the other word */
+ WordIndex = WordIndex ^ 1;
+ }
+ if (Result != XST_SUCCESS) break;
+ }
+ if (Result != XST_SUCCESS) break;
+ }
+
+ /* Check saturation of correctable error counter */
+ if (InstancePtr->Config.CorrectableCounterBits > 0 &&
+ Result == XST_SUCCESS) {
+
+ WR(CE_CNT_OFFSET, CounterMax);
+
+ InjectErrors(InstancePtr, Addr[WordIndex], 0, 0,
+ 4, &ActualData, &ActualEcc);
+
+ CHECK(CE_CNT_OFFSET, CounterMax, Result);
+ }
+
+ /* Restore the two words used for test */
+ XBram_Out32(Addr[0], SavedWords[0]);
+ XBram_Out32(Addr[1], SavedWords[1]);
+
+ /* Clear the Status Register. */
+ if (InstancePtr->Config.EccStatusInterruptPresent) {
+ WR(ECC_STATUS_OFFSET, XBRAM_IR_ALL_MASK);
+ }
+
+ /* Set Correctable Counter to zero */
+ if (InstancePtr->Config.CorrectableCounterBits > 0) {
+ WR(CE_CNT_OFFSET, 0);
+ }
+
+ if (Result != XST_SUCCESS) break;
+
+ } /* Width loop */
+
+ return (Result);
+ }
+
+ return (XST_SUCCESS);
+}
+
+/** @} */
diff --git a/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/bram_v4_3/src/xbram_sinit.c b/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/bram_v4_3/src/xbram_sinit.c
new file mode 100644
index 0000000..678ca46
--- /dev/null
+++ b/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/bram_v4_3/src/xbram_sinit.c
@@ -0,0 +1,99 @@
+/******************************************************************************
+*
+* Copyright (C) 2010 - 2017 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+* THE SOFTWARE.
+*
+*
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+* @file xbram_sinit.c
+* @addtogroup bram_v4_2
+* @{
+*
+* The implementation of the XBram driver's static initialization
+* functionality.
+*
+* @note
+*
+* None
+*
+* <pre>
+* MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ----- ---- -------- -----------------------------------------------
+* 2.01a jvb 10/13/05 First release
+* 2.11a mta 03/21/07 Updated to new coding style
+* 4.2 ms 08/07/17 Fixed compilation warnings.
+* </pre>
+*
+*****************************************************************************/
+
+/***************************** Include Files ********************************/
+
+#include "xstatus.h"
+#include "xparameters.h"
+#include "xbram.h"
+
+/************************** Constant Definitions ****************************/
+
+/**************************** Type Definitions ******************************/
+
+/***************** Macros (Inline Functions) Definitions ********************/
+
+/************************** Variable Definitions ****************************/
+extern XBram_Config XBram_ConfigTable[];
+
+/************************** Function Prototypes *****************************/
+
+
+/*****************************************************************************/
+/**
+* Lookup the device configuration based on the unique device ID. The table
+* ConfigTable contains the configuration info for each device in the system.
+*
+* @param DeviceId is the device identifier to lookup.
+*
+* @return
+* - A pointer of data type XBram_Config which
+* points to the device configuration if DeviceID is found.
+* - NULL if DeviceID is not found.
+*
+* @note None.
+*
+******************************************************************************/
+XBram_Config *XBram_LookupConfig(u16 DeviceId)
+{
+ XBram_Config *CfgPtr = NULL;
+
+ u32 Index;
+
+ for (Index = 0U; Index < XPAR_XBRAM_NUM_INSTANCES; Index++) {
+ if (XBram_ConfigTable[Index].DeviceId == DeviceId) {
+ CfgPtr = &XBram_ConfigTable[Index];
+ break;
+ }
+ }
+
+ return CfgPtr;
+}
+/** @} */
diff --git a/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/coresightps_dcc_v1_6/src/Makefile b/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/coresightps_dcc_v1_6/src/Makefile
new file mode 100644
index 0000000..007162d
--- /dev/null
+++ b/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/coresightps_dcc_v1_6/src/Makefile
@@ -0,0 +1,40 @@
+COMPILER=
+ARCHIVER=
+CP=cp
+COMPILER_FLAGS=
+EXTRA_COMPILER_FLAGS=
+LIB=libxil.a
+
+CC_FLAGS = $(COMPILER_FLAGS)
+ECC_FLAGS = $(EXTRA_COMPILER_FLAGS)
+
+RELEASEDIR=../../../lib
+INCLUDEDIR=../../../include
+INCLUDES=-I./. -I${INCLUDEDIR}
+
+OUTS = *.o
+
+LIBSOURCES:=*.c
+INCLUDEFILES:=*.h
+
+OBJECTS = $(addsuffix .o, $(basename $(wildcard *.c)))
+
+libs: banner coresightps_dcc_comp_libs clean
+
+%.o: %.c
+ ${COMPILER} $(CC_FLAGS) $(ECC_FLAGS) $(INCLUDES) -o $@ $<
+
+banner:
+ echo "Compiling coresightps_dcc"
+
+coresightps_dcc_comp_libs: ${OBJECTS}
+ $(ARCHIVER) -r ${RELEASEDIR}/${LIB} ${OBJECTS}
+
+.PHONY: include
+include: coresightps_dcc_includes
+
+coresightps_dcc_includes:
+ ${CP} ${INCLUDEFILES} ${INCLUDEDIR}
+
+clean:
+ rm -rf ${OBJECTS}
diff --git a/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/coresightps_dcc_v1_6/src/xcoresightpsdcc.c b/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/coresightps_dcc_v1_6/src/xcoresightpsdcc.c
new file mode 100644
index 0000000..742430f
--- /dev/null
+++ b/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/coresightps_dcc_v1_6/src/xcoresightpsdcc.c
@@ -0,0 +1,184 @@
+/******************************************************************************
+*
+* Copyright (C) 2015-2019 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+* THE SOFTWARE.
+*
+*
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xcoresightpsdcc.c
+* @addtogroup coresightps_dcc_v1_6
+* @{
+*
+* Functions in this file are the minimum required functions for the
+* XCoreSightPs driver.
+*
+* @note None.
+*
+*
+* <pre>
+* MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ----- ----- -------- -----------------------------------------------
+* 1.00 kvn 02/14/15 First release
+* 1.1 kvn 06/12/15 Add support for Zynq Ultrascale+ MP.
+* kvn 08/18/15 Modified Makefile according to compiler changes.
+* 1.2 kvn 10/09/15 Add support for IAR Compiler.
+* 1.3 asa 07/01/16 Made changes to ensure that the file does not compile
+* for MB BSPs. Instead it throws up a warning. This
+* fixes the CR#953056.
+* 1.5 sne 01/19/19 Fixed MISRA-C Violations CR#1025101.
+*
+* </pre>
+*
+******************************************************************************/
+
+/***************************** Include Files *********************************/
+#ifdef __MICROBLAZE__
+#warning "The driver is supported only for ARM architecture"
+#else
+
+#include "xil_types.h"
+#include "xpseudo_asm.h"
+#include "xcoresightpsdcc.h"
+
+#ifdef __ICCARM__
+#define INLINE
+#else
+#define INLINE __inline
+#endif
+
+/* DCC Status Bits */
+#define XCORESIGHTPS_DCC_STATUS_RX (1 << 30)
+#define XCORESIGHTPS_DCC_STATUS_TX (1 << 29)
+
+static INLINE u32 XCoresightPs_DccGetStatus(void);
+
+/****************************************************************************/
+/**
+*
+* This functions sends a single byte using the DCC. It is blocking in that it
+* waits for the transmitter to become non-full before it writes the byte to
+* the transmit register.
+*
+* @param BaseAddress is a dummy parameter to match the function proto
+* of functions for other stdio devices.
+* @param Data is the byte of data to send
+*
+* @return None.
+*
+* @note None.
+*
+******************************************************************************/
+void XCoresightPs_DccSendByte(u32 BaseAddress, u8 Data)
+{
+ (void) BaseAddress;
+ while (XCoresightPs_DccGetStatus() & XCORESIGHTPS_DCC_STATUS_TX)
+ {dsb();}
+#ifdef __aarch64__
+ asm volatile ("msr dbgdtrtx_el0, %0" : : "r" (Data));
+#elif defined (__GNUC__) || defined (__ICCARM__)
+ asm volatile("mcr p14, 0, %0, c0, c5, 0"
+ : : "r" (Data));
+#else
+ {
+ volatile register u32 Reg __asm("cp14:0:c0:c5:0");
+ Reg = Data;
+ }
+#endif
+ isb();
+
+}
+
+/****************************************************************************/
+/**
+*
+* This functions receives a single byte using the DCC. It is blocking in that
+* it waits for the receiver to become non-empty before it reads from the
+* receive register.
+*
+* @param BaseAddress is a dummy parameter to match the function proto
+* of functions for other stdio devices.
+*
+* @return The byte of data received.
+*
+* @note None.
+*
+******************************************************************************/
+u8 XCoresightPs_DccRecvByte(u32 BaseAddress)
+{
+ u8 Data = 0U;
+ (void) BaseAddress;
+
+ while (!(XCoresightPs_DccGetStatus() & XCORESIGHTPS_DCC_STATUS_RX))
+ {dsb();}
+
+#ifdef __aarch64__
+ asm volatile ("mrs %0, dbgdtrrx_el0" : "=r" (Data));
+#elif defined (__GNUC__) || defined (__ICCARM__)
+ asm volatile("mrc p14, 0, %0, c0, c5, 0"
+ : "=r" (Data));
+#else
+ {
+ volatile register u32 Reg __asm("cp14:0:c0:c5:0");
+ Data = Reg;
+ }
+#endif
+ isb();
+
+ return Data;
+}
+
+
+/****************************************************************************/
+/**INLINE
+*
+* This functions read the status register of the DCC.
+*
+* @param BaseAddress is the base address of the device
+*
+* @return The contents of the Status Register.
+*
+* @note None.
+*
+******************************************************************************/
+static INLINE u32 XCoresightPs_DccGetStatus(void)
+{
+ u32 Status = 0U;
+
+#ifdef __aarch64__
+ asm volatile ("mrs %0, mdccsr_el0" : "=r" (Status));
+#elif defined (__GNUC__) || defined (__ICCARM__)
+ asm volatile("mrc p14, 0, %0, c0, c1, 0"
+ : "=r" (Status) : : "cc");
+#else
+ {
+ volatile register u32 Reg __asm("cp14:0:c0:c1:0");
+ Status = Reg;
+ }
+#endif
+ return Status;
+}
+#endif
+/** @} */
diff --git a/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/coresightps_dcc_v1_6/src/xcoresightpsdcc.h b/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/coresightps_dcc_v1_6/src/xcoresightpsdcc.h
new file mode 100644
index 0000000..3e5d80e
--- /dev/null
+++ b/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/coresightps_dcc_v1_6/src/xcoresightpsdcc.h
@@ -0,0 +1,72 @@
+/******************************************************************************
+*
+* Copyright (C) 2015 - 2019 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+* THE SOFTWARE.
+*
+*
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xcoresightpsdcc.h
+* @addtogroup coresightps_dcc_v1_6
+* @{
+* @details
+*
+* CoreSight driver component.
+*
+* The coresight is a part of debug communication channel (DCC) group. Jtag UART
+* for ARM uses DCC. Each ARM core has its own DCC, so one need to select an
+* ARM target in XSDB console before running the jtag terminal command. Using the
+* coresight driver component, the output stream can be directed to a log file.
+*
+* @note None.
+*
+*
+* <pre>
+* MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ----- ----- -------- -----------------------------------------------
+* 1.00 kvn 02/14/15 First release
+* 1.1 kvn 06/12/15 Add support for Zynq Ultrascale+ MP.
+* kvn 08/18/15 Modified Makefile according to compiler changes.
+* 1.3 asa 07/01/16 Made changes to ensure that the file does not compile
+* for MB BSPs. Instead it throws up a warning. This
+* fixes the CR#953056.
+* 1.5 sne 01/19/19 Fixed MISRA-C Violations CR#1025101.
+*
+* </pre>
+*
+******************************************************************************/
+
+/***************************** Include Files *********************************/
+#ifndef XCORESIGHTPSDCC_H /* prevent circular inclusions */
+#define XCORESIGHTPSDCC_H /* by using protection macros */
+#ifndef __MICROBLAZE__
+#include <xil_types.h>
+
+void XCoresightPs_DccSendByte(u32 BaseAddress, u8 Data);
+
+u8 XCoresightPs_DccRecvByte(u32 BaseAddress);
+#endif
+#endif
+/** @} */
diff --git a/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/cpu_cortexa9_v2_8/src/Makefile b/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/cpu_cortexa9_v2_8/src/Makefile
new file mode 100644
index 0000000..7ea505c
--- /dev/null
+++ b/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/cpu_cortexa9_v2_8/src/Makefile
@@ -0,0 +1,25 @@
+COMPILER=
+ARCHIVER=
+CP=cp
+COMPILER_FLAGS=
+EXTRA_COMPILER_FLAGS=
+LIB=libxil.a
+
+RELEASEDIR=../../../lib
+INCLUDEDIR=../../../include
+INCLUDES=-I${INCLUDEDIR}
+
+OUTS = *.o
+OBJECTS = $(addsuffix .o, $(basename $(wildcard *.c)))
+LIBSOURCES=*.c
+INCLUDEFILES=*.h
+
+libs:
+ echo "Compiling cpu_cortexa9"
+
+.PHONY: include
+include:
+ ${CP} $(INCLUDEFILES) $(INCLUDEDIR)
+
+clean:
+ rm -rf ${OBJECTS}
diff --git a/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/cpu_cortexa9_v2_8/src/xcpu_cortexa9.h b/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/cpu_cortexa9_v2_8/src/xcpu_cortexa9.h
new file mode 100644
index 0000000..4f12056
--- /dev/null
+++ b/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/cpu_cortexa9_v2_8/src/xcpu_cortexa9.h
@@ -0,0 +1,45 @@
+/******************************************************************************
+*
+* Copyright (C) 2011 - 2018 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+* THE SOFTWARE.
+*
+*
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xcpu_cortexa9.h
+* @addtogroup cpu_cortexa9_v2_7
+* @{
+* @details
+*
+* dummy file
+* MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ----- ---- -------- ---------------------------------------------------------
+* 2.5 ms 04/18/17 Modified tcl file to add suffix U for XPAR_CPU_ID
+* parameter of cpu_cortexa9 in xparameters.h
+# 2.7 mus 07/03/18 Updated tcl to not to add default flags forcefully into
+# extra compiler flags. Now, user can remove default flags
+# from extra compiler flags. It fixes CR#998768.
+******************************************************************************/
+/** @} */
diff --git a/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/ddrps_v1_0/src/Makefile b/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/ddrps_v1_0/src/Makefile
new file mode 100644
index 0000000..7b191dd
--- /dev/null
+++ b/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/ddrps_v1_0/src/Makefile
@@ -0,0 +1,40 @@
+COMPILER=
+ARCHIVER=
+CP=cp
+COMPILER_FLAGS=
+EXTRA_COMPILER_FLAGS=
+LIB=libxil.a
+
+CC_FLAGS = $(COMPILER_FLAGS)
+ECC_FLAGS = $(EXTRA_COMPILER_FLAGS)
+
+RELEASEDIR=../../../lib
+INCLUDEDIR=../../../include
+INCLUDES=-I./. -I${INCLUDEDIR}
+
+OUTS = *.o
+
+LIBSOURCES:=*.c
+INCLUDEFILES:=*.h
+
+OBJECTS = $(addsuffix .o, $(basename $(wildcard *.c)))
+
+libs: banner xddrps_libs clean
+
+%.o: %.c
+ ${COMPILER} $(CC_FLAGS) $(ECC_FLAGS) $(INCLUDES) -o $@ $<
+
+banner:
+ echo "Compiling ddrps"
+
+xddrps_libs: ${OBJECTS}
+ $(ARCHIVER) -r ${RELEASEDIR}/${LIB} ${OBJECTS}
+
+.PHONY: include
+include: xddrps_includes
+
+xddrps_includes:
+ ${CP} ${INCLUDEFILES} ${INCLUDEDIR}
+
+clean:
+ rm -rf ${OBJECTS}
diff --git a/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/ddrps_v1_0/src/xddrps.h b/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/ddrps_v1_0/src/xddrps.h
new file mode 100644
index 0000000..8b1d991
--- /dev/null
+++ b/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/ddrps_v1_0/src/xddrps.h
@@ -0,0 +1,60 @@
+/*******************************************************************************
+ *
+ * Copyright (C) 2015 Xilinx, Inc. All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ *
+ *
+ *
+*******************************************************************************/
+/******************************************************************************/
+/**
+ *
+ * @file xddrps.h
+ * @addtogroup ddrps_v1_0
+ * @{
+ * @details
+ *
+ * The Xilinx DdrPs driver. This driver supports the Xilinx ddrps
+ * IP core.
+ *
+ * @note None.
+ *
+ * <pre>
+ * MODIFICATION HISTORY:
+ *
+ * Ver Who Date Changes
+ * ----- ---- -------- -----------------------------------------------
+ * 1.0 nsk 08/06/15 First Release
+ * 1.0 nsk 08/20/15 Updated define_addr_params in ddrps.tcl
+ * to support PBD Designs (CR #876857)
+ *
+ * </pre>
+ *
+*******************************************************************************/
+
+#ifndef XDDRPS_H_
+/* Prevent circular inclusions by using protection macros. */
+#define XDDRPS_H_
+
+/******************************* Include Files ********************************/
+
+
+#endif /* XDDRPS_H_ */
+/** @} */
diff --git a/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/devcfg_v3_5/src/Makefile b/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/devcfg_v3_5/src/Makefile
new file mode 100644
index 0000000..25ff740
--- /dev/null
+++ b/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/devcfg_v3_5/src/Makefile
@@ -0,0 +1,40 @@
+COMPILER=
+ARCHIVER=
+CP=cp
+COMPILER_FLAGS=
+EXTRA_COMPILER_FLAGS=
+LIB=libxil.a
+
+CC_FLAGS = $(COMPILER_FLAGS)
+ECC_FLAGS = $(EXTRA_COMPILER_FLAGS)
+
+RELEASEDIR=../../../lib
+INCLUDEDIR=../../../include
+INCLUDES=-I./. -I${INCLUDEDIR}
+
+OUTS = *.o
+
+LIBSOURCES:=*.c
+INCLUDEFILES:=*.h
+
+OBJECTS = $(addsuffix .o, $(basename $(wildcard *.c)))
+
+libs: banner xdevcfg_libs clean
+
+%.o: %.c
+ ${COMPILER} $(CC_FLAGS) $(ECC_FLAGS) $(INCLUDES) -o $@ $<
+
+banner:
+ echo "Compiling devcfg"
+
+xdevcfg_libs: ${OBJECTS}
+ $(ARCHIVER) -r ${RELEASEDIR}/${LIB} ${OBJECTS}
+
+.PHONY: include
+include: xdevcfg_includes
+
+xdevcfg_includes:
+ ${CP} ${INCLUDEFILES} ${INCLUDEDIR}
+
+clean:
+ rm -rf ${OBJECTS}
diff --git a/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/devcfg_v3_5/src/xdevcfg.c b/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/devcfg_v3_5/src/xdevcfg.c
new file mode 100644
index 0000000..8b863ac
--- /dev/null
+++ b/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/devcfg_v3_5/src/xdevcfg.c
@@ -0,0 +1,939 @@
+/******************************************************************************
+*
+* Copyright (C) 2010 - 2015 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+* THE SOFTWARE.
+*
+*
+*
+******************************************************************************/
+/****************************************************************************/
+/**
+*
+* @file xdevcfg.c
+* @addtogroup devcfg_v3_5
+* @{
+*
+* This file contains the implementation of the interface functions for XDcfg
+* driver. Refer to the header file xdevcfg.h for more detailed information.
+*
+* <pre>
+* MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ----- --- -------- ---------------------------------------------
+* 1.00a hvm 02/07/11 First release
+* 2.00a nm 05/31/12 Updated the driver for CR 660835 so that input length for
+* source/destination to the XDcfg_InitiateDma, XDcfg_Transfer
+* APIs is words (32 bit) and not bytes.
+* Updated the notes for XDcfg_InitiateDma/XDcfg_Transfer APIs
+* to add information that 2 LSBs of the Source/Destination
+* address when equal to 2�b01 indicate the last DMA command
+* of an overall transfer.
+* Updated the XDcfg_Transfer function to use the
+* Destination Address passed to this API for secure transfers
+* instead of using 0xFFFFFFFF for CR 662197. This issue was
+* resulting in the failure of secure transfers of
+* non-bitstream images.
+* 2.01a nm 08/27/12 Updated the XDcfg_Transfer API to clear the
+* QUARTER_PCAP_RATE_EN bit in the control register for
+* non secure writes for CR 675543.
+* 2.02a nm 01/31/13 Fixed CR# 679335.
+* Added Setting and Clearing the internal PCAP loopback.
+* Removed code for enabling/disabling AES engine as BootROM
+* locks down this setting.
+* Fixed CR# 681976.
+* Skip Checking the PCFG_INIT in case of non-secure DMA
+* loopback.
+* Fixed CR# 699558.
+* XDcfg_Transfer fails to transfer data in loopback mode.
+* 2.03a nm 04/19/13 Fixed CR# 703728.
+* Updated the register definitions as per the latest TRM
+* version UG585 (v1.4) November 16, 2012.
+* 3.0 kpc 21/02/14 Implemented new function XDcfg_ClearControlRegister
+* 3.2 sb 08/25/14 Fixed XDcfg_PcapReadback() function
+* updated driver code with != instead of ==,
+* while checking for Interrupt Status with DMA and
+* PCAP Done Mask
+* ((XDcfg_ReadReg(InstancePtr->Config.BaseAddr,
+* XDCFG_INT_STS_OFFSET) &
+* XDCFG_IXR_D_P_DONE_MASK) !=
+* XDCFG_IXR_D_P_DONE_MASK);
+*
+*
+* </pre>
+*
+******************************************************************************/
+
+/***************************** Include Files *********************************/
+
+#include "xdevcfg.h"
+
+/************************** Constant Definitions *****************************/
+
+/**************************** Type Definitions *******************************/
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/************************** Function Prototypes ******************************/
+
+/************************** Variable Definitions *****************************/
+
+/****************************************************************************/
+/**
+*
+* Initialize the Device Config Interface driver. This function
+* must be called before other functions of the driver are called.
+*
+* @param InstancePtr is a pointer to the XDcfg instance.
+* @param ConfigPtr is the config structure.
+* @param EffectiveAddress is the base address for the device. It could be
+* a virtual address if address translation is supported in the
+* system, otherwise it is the physical address.
+*
+* @return
+* - XST_SUCCESS if initialization was successful.
+* - XST_DEVICE_IS_STARTED if the device has already been started.
+*
+* @note The very first APB access to the Device Configuration Interface
+* block needs to be a write to the UNLOCK register with the value
+* of 0x757BDF0D. This step is to be done once after reset, any
+* other APB access has to come after this. The APB access is
+* considered illegal if the step is not done or if it is done
+* incorrectly. Furthermore, if any of efuse_sec_cfg[5:0] is high,
+* the following additional actions would be carried out.
+* In other words, if all bits are low, the following steps are not
+* done.
+* 1. AES is disabled
+* 2. All APB writes disabled
+* 3. SoC debug fully enabled
+*
+******************************************************************************/
+int XDcfg_CfgInitialize(XDcfg *InstancePtr,
+ XDcfg_Config *ConfigPtr, u32 EffectiveAddress)
+{
+ Xil_AssertNonvoid(InstancePtr != NULL);
+ Xil_AssertNonvoid(ConfigPtr != NULL);
+
+ /*
+ * If the device is started, disallow the initialize and return a
+ * status indicating it is started. This allows the user to stop the
+ * device and reinitialize, but prevents a user from inadvertently
+ * initializing.
+ */
+ if (InstancePtr->IsStarted == XIL_COMPONENT_IS_STARTED) {
+ return XST_DEVICE_IS_STARTED;
+ }
+
+ /*
+ * Copy configuration into instance.
+ */
+ InstancePtr->Config.DeviceId = ConfigPtr->DeviceId;
+
+ /*
+ * Save the base address pointer such that the registers of the block
+ * can be accessed and indicate it has not been started yet.
+ */
+ InstancePtr->Config.BaseAddr = EffectiveAddress;
+ InstancePtr->IsStarted = 0;
+
+
+ /* Unlock the Device Configuration Interface */
+ XDcfg_Unlock(InstancePtr);
+
+ /*
+ * Indicate the instance is ready to use, successfully initialized.
+ */
+ InstancePtr->IsReady = XIL_COMPONENT_IS_READY;
+
+ return XST_SUCCESS;
+}
+
+/****************************************************************************/
+/**
+*
+* The functions enables the PCAP interface by setting the PCAP mode bit in the
+* control register.
+*
+* @param InstancePtr is a pointer to the XDcfg instance.
+*
+* @return None.
+*
+* @note Enable FPGA programming from PCAP interface. Enabling this bit
+* disables all the external interfaces from programming of FPGA
+* except for ICAP. The user needs to ensure that the FPGA is
+* programmed through either PCAP or ICAP.
+*
+*****************************************************************************/
+void XDcfg_EnablePCAP(XDcfg *InstancePtr)
+{
+ u32 CtrlReg;
+ /*
+ * Assert the arguments.
+ */
+ Xil_AssertVoid(InstancePtr != NULL);
+ Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+
+ CtrlReg = XDcfg_ReadReg(InstancePtr->Config.BaseAddr,
+ XDCFG_CTRL_OFFSET);
+
+ XDcfg_WriteReg(InstancePtr->Config.BaseAddr, XDCFG_CTRL_OFFSET,
+ (CtrlReg | XDCFG_CTRL_PCAP_MODE_MASK));
+
+}
+
+/****************************************************************************/
+/**
+*
+* The functions disables the PCAP interface by clearing the PCAP mode bit in
+* the control register.
+*
+* @param InstancePtr is a pointer to the XDcfg instance.
+*
+* @return None.
+*
+* @note None.
+*
+*****************************************************************************/
+void XDcfg_DisablePCAP(XDcfg *InstancePtr)
+{
+ u32 CtrlReg;
+ /*
+ * Assert the arguments.
+ */
+ Xil_AssertVoid(InstancePtr != NULL);
+ Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+
+ CtrlReg = XDcfg_ReadReg(InstancePtr->Config.BaseAddr,
+ XDCFG_CTRL_OFFSET);
+
+ XDcfg_WriteReg(InstancePtr->Config.BaseAddr, XDCFG_CTRL_OFFSET,
+ (CtrlReg & ( ~XDCFG_CTRL_PCAP_MODE_MASK)));
+
+}
+
+/****************************************************************************/
+/**
+*
+* The function sets the contents of the Control Register.
+*
+* @param InstancePtr is a pointer to the XDcfg instance.
+* @param Mask is the 32 bit mask data to be written to the Register.
+* The mask definitions are defined in the xdevcfg_hw.h file.
+*
+* @return None.
+*
+* @note None.
+*
+*****************************************************************************/
+void XDcfg_SetControlRegister(XDcfg *InstancePtr, u32 Mask)
+{
+ u32 CtrlReg;
+ /*
+ * Assert the arguments.
+ */
+ Xil_AssertVoid(InstancePtr != NULL);
+ Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+
+ CtrlReg = XDcfg_ReadReg(InstancePtr->Config.BaseAddr,
+ XDCFG_CTRL_OFFSET);
+
+ XDcfg_WriteReg(InstancePtr->Config.BaseAddr, XDCFG_CTRL_OFFSET,
+ (CtrlReg | Mask));
+
+}
+
+/****************************************************************************/
+/**
+*
+* The function Clears the specified bit positions of the Control Register.
+*
+* @param InstancePtr is a pointer to the XDcfg instance.
+* @param Mask is the 32 bit value which holds the bit positions to be cleared.
+*
+* @return None.
+*
+* @note None.
+*
+*****************************************************************************/
+void XDcfg_ClearControlRegister(XDcfg *InstancePtr, u32 Mask)
+{
+ u32 CtrlReg;
+ /*
+ * Assert the arguments.
+ */
+ Xil_AssertVoid(InstancePtr != NULL);
+ Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+
+ CtrlReg = XDcfg_ReadReg(InstancePtr->Config.BaseAddr,
+ XDCFG_CTRL_OFFSET);
+
+ XDcfg_WriteReg(InstancePtr->Config.BaseAddr, XDCFG_CTRL_OFFSET,
+ (CtrlReg & ~Mask));
+
+}
+
+/****************************************************************************/
+/**
+*
+* The function reads the contents of the Control Register.
+*
+* @param InstancePtr is a pointer to the XDcfg instance.
+*
+* @return A 32-bit value representing the contents of the Control
+* Register.
+* Use the XDCFG_CTRL_*_MASK constants defined in xdevcfg_hw.h to
+* interpret the returned value.
+*
+* @note None.
+*
+*****************************************************************************/
+u32 XDcfg_GetControlRegister(XDcfg *InstancePtr)
+{
+ /*
+ * Assert the arguments.
+ */
+ Xil_AssertNonvoid(InstancePtr != NULL);
+ Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+ /*
+ * Read the Control Register and return the value.
+ */
+ return XDcfg_ReadReg(InstancePtr->Config.BaseAddr, XDCFG_CTRL_OFFSET);
+}
+
+/****************************************************************************/
+/**
+*
+* The function sets the contents of the Lock Register. These bits
+* can only be set to a 1. They will be cleared after a Power On Reset.
+*
+* @param InstancePtr is a pointer to the XDcfg instance.
+* @param Data is the 32 bit data to be written to the Register.
+*
+* @return None.
+*
+* @note None.
+*
+*****************************************************************************/
+void XDcfg_SetLockRegister(XDcfg *InstancePtr, u32 Data)
+{
+ /*
+ * Assert the arguments.
+ */
+ Xil_AssertVoid(InstancePtr != NULL);
+ Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+ XDcfg_WriteReg(InstancePtr->Config.BaseAddr, XDCFG_LOCK_OFFSET, Data);
+
+}
+
+/****************************************************************************/
+/**
+*
+* The function reads the contents of the Lock Register.
+*
+* @param InstancePtr is a pointer to the XDcfg instance.
+*
+* @return A 32-bit value representing the contents of the Lock
+* Register.
+* Use the XDCFG_CR_*_MASK constants defined in xdevcfg_hw.h to
+* interpret the returned value.
+*
+* @note None.
+*
+*****************************************************************************/
+u32 XDcfg_GetLockRegister(XDcfg *InstancePtr)
+{
+ /*
+ * Assert the arguments.
+ */
+ Xil_AssertNonvoid(InstancePtr != NULL);
+ Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+ /*
+ * Read the Lock Register and return the value.
+ */
+ return XDcfg_ReadReg(InstancePtr->Config.BaseAddr, XDCFG_LOCK_OFFSET);
+}
+
+/****************************************************************************/
+/**
+*
+* The function sets the contents of the Configuration Register with the
+* given value.
+*
+* @param InstancePtr is a pointer to the XDcfg instance.
+* @param Data is the 32 bit data to be written to the Register.
+*
+* @return None.
+*
+* @note None.
+*
+*****************************************************************************/
+void XDcfg_SetConfigRegister(XDcfg *InstancePtr, u32 Data)
+{
+ /*
+ * Assert the arguments.
+ */
+ Xil_AssertVoid(InstancePtr != NULL);
+ Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+ XDcfg_WriteReg(InstancePtr->Config.BaseAddr, XDCFG_CFG_OFFSET, Data);
+
+}
+
+/****************************************************************************/
+/**
+*
+* The function reads the contents of the Configuration Register with the
+* given value.
+*
+* @param InstancePtr is a pointer to the XDcfg instance.
+*
+* @return A 32-bit value representing the contents of the Config
+* Register.
+* Use the XDCFG_CFG_*_MASK constants defined in xdevcfg_hw.h to
+* interpret the returned value.
+*
+* @note None.
+*
+*****************************************************************************/
+u32 XDcfg_GetConfigRegister(XDcfg *InstancePtr)
+{
+ /*
+ * Assert the arguments.
+ */
+ Xil_AssertNonvoid(InstancePtr != NULL);
+ Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+ return XDcfg_ReadReg(InstancePtr->Config.BaseAddr, XDCFG_CFG_OFFSET);
+
+}
+
+/****************************************************************************/
+/**
+*
+* The function sets the contents of the Status Register.
+*
+* @param InstancePtr is a pointer to the XDcfg instance.
+* @param Data is the 32 bit data to be written to the Register.
+*
+* @return None.
+*
+* @note None.
+*
+*****************************************************************************/
+void XDcfg_SetStatusRegister(XDcfg *InstancePtr, u32 Data)
+{
+ /*
+ * Assert the arguments.
+ */
+ Xil_AssertVoid(InstancePtr != NULL);
+ Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+ XDcfg_WriteReg(InstancePtr->Config.BaseAddr, XDCFG_STATUS_OFFSET, Data);
+
+}
+
+/****************************************************************************/
+/**
+*
+* The function reads the contents of the Status Register.
+*
+* @param InstancePtr is a pointer to the XDcfg instance.
+*
+* @return A 32-bit value representing the contents of the Status
+* Register.
+* Use the XDCFG_STATUS_*_MASK constants defined in
+* xdevcfg_hw.h to interpret the returned value.
+*
+* @note None.
+*
+*****************************************************************************/
+u32 XDcfg_GetStatusRegister(XDcfg *InstancePtr)
+{
+ /*
+ * Assert the arguments.
+ */
+ Xil_AssertNonvoid(InstancePtr != NULL);
+ Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+ /*
+ * Read the Status Register and return the value.
+ */
+ return XDcfg_ReadReg(InstancePtr->Config.BaseAddr, XDCFG_STATUS_OFFSET);
+}
+
+/****************************************************************************/
+/**
+*
+* The function sets the contents of the ROM Shadow Control Register.
+*
+* @param InstancePtr is a pointer to the XDcfg instance.
+* @param Data is the 32 bit data to be written to the Register.
+*
+* @return None.
+*
+* @note This register is can only be written and is used to control the
+* RAM shadow of 32 bit 4K page ROM pages in user mode
+*
+*****************************************************************************/
+void XDcfg_SetRomShadowRegister(XDcfg *InstancePtr, u32 Data)
+{
+ /*
+ * Assert the arguments.
+ */
+ Xil_AssertVoid(InstancePtr != NULL);
+ Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+ XDcfg_WriteReg(InstancePtr->Config.BaseAddr, XDCFG_ROM_SHADOW_OFFSET,
+ Data);
+
+}
+
+/****************************************************************************/
+/**
+*
+* The function reads the contents of the Software ID Register.
+*
+* @param InstancePtr is a pointer to the XDcfg instance.
+*
+* @return 32 Bit boot software ID.
+*
+* @note This register is locked for write once the system enters
+* usermode. Hence API for reading the register only is provided.
+*
+*****************************************************************************/
+u32 XDcfg_GetSoftwareIdRegister(XDcfg *InstancePtr)
+{
+ /*
+ * Assert the arguments.
+ */
+ Xil_AssertNonvoid(InstancePtr != NULL);
+ Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+ /*
+ * Read the Software ID Register and return the value.
+ */
+ return XDcfg_ReadReg(InstancePtr->Config.BaseAddr, XDCFG_SW_ID_OFFSET);
+}
+
+/****************************************************************************/
+/**
+*
+* The function sets the bit mask for the feature in Miscellaneous Control
+* Register.
+*
+* @param InstancePtr is a pointer to the XDcfg instance.
+* @param Mask is the bit-mask of the feature to be set.
+*
+* @return None.
+*
+* @note None
+*
+*****************************************************************************/
+void XDcfg_SetMiscControlRegister(XDcfg *InstancePtr, u32 Mask)
+{
+ u32 RegData;
+
+ /*
+ * Assert the arguments.
+ */
+ Xil_AssertVoid(InstancePtr != NULL);
+ Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+
+ RegData = XDcfg_ReadReg(InstancePtr->Config.BaseAddr,
+ XDCFG_MCTRL_OFFSET);
+
+ XDcfg_WriteReg(InstancePtr->Config.BaseAddr, XDCFG_MCTRL_OFFSET,
+ (RegData | Mask));
+}
+
+/****************************************************************************/
+/**
+*
+* The function reads the contents of the Miscellaneous Control Register.
+*
+* @param InstancePtr is a pointer to the XDcfg instance.
+*
+* @return 32 Bit boot software ID.
+*
+* @note This register is locked for write once the system enters
+* usermode. Hence API to reading the register only is provided.
+*
+*****************************************************************************/
+u32 XDcfg_GetMiscControlRegister(XDcfg *InstancePtr)
+{
+ /*
+ * Assert the arguments.
+ */
+ Xil_AssertNonvoid(InstancePtr != NULL);
+ Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+ /*
+ * Read the Miscellaneous Control Register and return the value.
+ */
+ return XDcfg_ReadReg(InstancePtr->Config.BaseAddr, XDCFG_MCTRL_OFFSET);
+}
+
+/******************************************************************************/
+/**
+*
+* This function checks if DMA command queue is full.
+*
+* @param InstancePtr is a pointer to the XDcfg instance.
+*
+* @return XST_SUCCESS is the DMA is busy
+* XST_FAILURE if the DMA is idle
+*
+* @note The DMA queue has a depth of two.
+*
+****************************************************************************/
+u32 XDcfg_IsDmaBusy(XDcfg *InstancePtr)
+{
+
+ u32 RegData;
+
+ Xil_AssertNonvoid(InstancePtr != NULL);
+ Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+ /* Read the PCAP status register for DMA status */
+ RegData = XDcfg_ReadReg(InstancePtr->Config.BaseAddr,
+ XDCFG_STATUS_OFFSET);
+
+ if ((RegData & XDCFG_STATUS_DMA_CMD_Q_F_MASK) ==
+ XDCFG_STATUS_DMA_CMD_Q_F_MASK){
+ return XST_SUCCESS;
+ }
+
+ return XST_FAILURE;
+}
+
+/******************************************************************************/
+/**
+*
+* This function initiates the DMA transfer.
+*
+* @param InstancePtr is a pointer to the XDcfg instance.
+* @param SourcePtr contains a pointer to the source memory where the data
+* is to be transferred from.
+* @param SrcWordLength is the number of words (32 bit) to be transferred
+* for the source transfer.
+* @param DestPtr contains a pointer to the destination memory
+* where the data is to be transferred to.
+* @param DestWordLength is the number of words (32 bit) to be transferred
+* for the Destination transfer.
+*
+* @return None.
+*
+* @note It is the responsibility of the caller function to ensure that
+* correct values are passed to this function.
+*
+* The 2 LSBs of the SourcePtr (Source)/ DestPtr (Destination)
+* address when equal to 2�b01 indicates the last DMA command of
+* an overall transfer.
+*
+****************************************************************************/
+void XDcfg_InitiateDma(XDcfg *InstancePtr, u32 SourcePtr, u32 DestPtr,
+ u32 SrcWordLength, u32 DestWordLength)
+{
+
+ XDcfg_WriteReg(InstancePtr->Config.BaseAddr,
+ XDCFG_DMA_SRC_ADDR_OFFSET,
+ SourcePtr);
+
+ XDcfg_WriteReg(InstancePtr->Config.BaseAddr,
+ XDCFG_DMA_DEST_ADDR_OFFSET,
+ DestPtr);
+
+ XDcfg_WriteReg(InstancePtr->Config.BaseAddr,
+ XDCFG_DMA_SRC_LEN_OFFSET,
+ SrcWordLength);
+
+ XDcfg_WriteReg(InstancePtr->Config.BaseAddr,
+ XDCFG_DMA_DEST_LEN_OFFSET,
+ DestWordLength);
+}
+
+/******************************************************************************/
+/**
+*
+* This function Implements the DMA Read Command. This command is used to
+* transfer the image data from FPGA to the external memory.
+*
+* @param InstancePtr is a pointer to the XDcfg instance.
+* @param SourcePtr contains a pointer to the source memory where the data
+* is to be transferred from.
+* @param SrcWordLength is the number of words (32 bit) to be transferred
+* for the source transfer.
+* @param DestPtr contains a pointer to the destination memory
+* where the data is to be transferred to.
+* @param DestWordLength is the number of words (32 bit) to be transferred
+* for the Destination transfer.
+*
+* @return - XST_INVALID_PARAM if source address/length is invalid.
+* - XST_SUCCESS if DMA transfer initiated properly.
+*
+* @note None.
+*
+****************************************************************************/
+static u32 XDcfg_PcapReadback(XDcfg *InstancePtr, u32 SourcePtr,
+ u32 SrcWordLength, u32 DestPtr,
+ u32 DestWordLength)
+{
+ u32 IntrReg;
+
+ /*
+ * Send READ Frame command to FPGA
+ */
+ XDcfg_InitiateDma(InstancePtr, SourcePtr, XDCFG_DMA_INVALID_ADDRESS,
+ SrcWordLength, 0);
+
+ /*
+ * Store the enabled interrupts to enable before the actual read
+ * transfer is initiated and Disable all the interrupts temporarily.
+ */
+ IntrReg = XDcfg_IntrGetEnabled(InstancePtr);
+ XDcfg_IntrDisable(InstancePtr, XDCFG_IXR_ALL_MASK);
+
+ /*
+ * Wait till you get the DMA done for the read command sent
+ */
+ while ((XDcfg_ReadReg(InstancePtr->Config.BaseAddr,
+ XDCFG_INT_STS_OFFSET) &
+ XDCFG_IXR_D_P_DONE_MASK) !=
+ XDCFG_IXR_D_P_DONE_MASK);
+ /*
+ * Enable the previously stored Interrupts .
+ */
+ XDcfg_IntrEnable(InstancePtr, IntrReg);
+
+ /*
+ * Initiate the DMA write command.
+ */
+ XDcfg_InitiateDma(InstancePtr, XDCFG_DMA_INVALID_ADDRESS, (u32)DestPtr,
+ 0, DestWordLength);
+
+ return XST_SUCCESS;
+}
+
+
+/****************************************************************************/
+/**
+*
+* This function starts the DMA transfer. This function only starts the
+* operation and returns before the operation may be completed.
+* If the interrupt is enabled, an interrupt will be generated when the
+* operation is completed, otherwise it is necessary to poll the Status register
+* to determine when it is completed. It is the responsibility of the caller to
+* determine when the operation is completed by handling the generated interrupt
+* or polling the Status Register.
+*
+* @param InstancePtr is a pointer to the XDcfg instance.
+* @param SourcePtr contains a pointer to the source memory where the data
+* is to be transferred from.
+* @param SrcWordLength is the number of words (32 bit) to be transferred
+* for the source transfer.
+* @param DestPtr contains a pointer to the destination memory
+* where the data is to be transferred to.
+* @param DestWordLength is the number of words (32 bit) to be transferred
+* for the Destination transfer.
+* @param TransferType contains the type of PCAP transfer being requested.
+* The definitions can be found in the xdevcfg.h file.
+* @return
+* - XST_SUCCESS.if DMA transfer initiated successfully
+* - XST_DEVICE_BUSY if DMA is busy
+* - XST_INVALID_PARAM if invalid Source / Destination address
+* is sent or an invalid Source / Destination length is
+* sent
+*
+* @note It is the responsibility of the caller to ensure that the cache
+* is flushed and invalidated both before the DMA operation is
+* started and after the DMA operation completes if the memory
+* pointed to is cached. The caller must also ensure that the
+* pointers contain physical address rather than a virtual address
+* if address translation is being used.
+*
+* The 2 LSBs of the SourcePtr (Source)/ DestPtr (Destination)
+* address when equal to 2�b01 indicates the last DMA command of
+* an overall transfer.
+*
+*****************************************************************************/
+u32 XDcfg_Transfer(XDcfg *InstancePtr,
+ void *SourcePtr, u32 SrcWordLength,
+ void *DestPtr, u32 DestWordLength,
+ u32 TransferType)
+{
+
+ u32 CtrlReg;
+
+ Xil_AssertNonvoid(InstancePtr != NULL);
+ Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+
+ if (XDcfg_IsDmaBusy(InstancePtr) == XST_SUCCESS) {
+ return XST_DEVICE_BUSY;
+ }
+
+ /*
+ * Check whether the fabric is in initialized state
+ */
+ if ((XDcfg_ReadReg(InstancePtr->Config.BaseAddr, XDCFG_STATUS_OFFSET)
+ & XDCFG_STATUS_PCFG_INIT_MASK) == 0) {
+ /*
+ * We don't need to check PCFG_INIT to be high for
+ * non-encrypted loopback transfers.
+ */
+ if (TransferType != XDCFG_CONCURRENT_NONSEC_READ_WRITE) {
+ return XST_FAILURE;
+ }
+ }
+
+ if ((TransferType == XDCFG_SECURE_PCAP_WRITE) ||
+ (TransferType == XDCFG_NON_SECURE_PCAP_WRITE)) {
+
+ /* Check for valid source pointer and length */
+ if ((!SourcePtr) || (SrcWordLength == 0)) {
+ return XST_INVALID_PARAM;
+ }
+
+ /* Clear internal PCAP loopback */
+ CtrlReg = XDcfg_ReadReg(InstancePtr->Config.BaseAddr,
+ XDCFG_MCTRL_OFFSET);
+ XDcfg_WriteReg(InstancePtr->Config.BaseAddr,
+ XDCFG_MCTRL_OFFSET, (CtrlReg &
+ ~(XDCFG_MCTRL_PCAP_LPBK_MASK)));
+
+ if (TransferType == XDCFG_NON_SECURE_PCAP_WRITE) {
+ /*
+ * Clear QUARTER_PCAP_RATE_EN bit
+ * so that the PCAP data is transmitted every clock
+ */
+ CtrlReg = XDcfg_ReadReg(InstancePtr->Config.BaseAddr,
+ XDCFG_CTRL_OFFSET);
+
+ XDcfg_WriteReg(InstancePtr->Config.BaseAddr,
+ XDCFG_CTRL_OFFSET, (CtrlReg &
+ ~XDCFG_CTRL_PCAP_RATE_EN_MASK));
+
+ }
+ if (TransferType == XDCFG_SECURE_PCAP_WRITE) {
+ /*
+ * AES engine handles only 8 bit data every clock cycle.
+ * Hence, Encrypted PCAP data which is 32 bit data can
+ * only be sent in every 4 clock cycles. Set the control
+ * register QUARTER_PCAP_RATE_EN bit to achieve this
+ * operation.
+ */
+ XDcfg_SetControlRegister(InstancePtr,
+ XDCFG_CTRL_PCAP_RATE_EN_MASK);
+ }
+
+ XDcfg_InitiateDma(InstancePtr, (u32)SourcePtr,
+ (u32)DestPtr, SrcWordLength, DestWordLength);
+
+ }
+
+ if (TransferType == XDCFG_PCAP_READBACK) {
+
+ if ((!DestPtr) || (DestWordLength == 0)) {
+
+ return XST_INVALID_PARAM;
+ }
+
+ /* Clear internal PCAP loopback */
+ CtrlReg = XDcfg_ReadReg(InstancePtr->Config.BaseAddr,
+ XDCFG_MCTRL_OFFSET);
+ XDcfg_WriteReg(InstancePtr->Config.BaseAddr,
+ XDCFG_MCTRL_OFFSET, (CtrlReg &
+ ~(XDCFG_MCTRL_PCAP_LPBK_MASK)));
+
+ /*
+ * For PCAP readback of FPGA configuration register or memory,
+ * the read command is first sent (written) to the FPGA fabric
+ * which responds by returning the required read data. Read data
+ * from the FPGA is captured if pcap_radata_v is active.A DMA
+ * read transfer is required to obtain the readback command,
+ * which is then sent to the FPGA, followed by a DMA write
+ * transfer to support this mode of operation.
+ */
+ return XDcfg_PcapReadback(InstancePtr,
+ (u32)SourcePtr, SrcWordLength,
+ (u32)DestPtr, DestWordLength);
+ }
+
+
+ if ((TransferType == XDCFG_CONCURRENT_SECURE_READ_WRITE) ||
+ (TransferType == XDCFG_CONCURRENT_NONSEC_READ_WRITE)) {
+
+ if ((!SourcePtr) || (SrcWordLength == 0) ||
+ (!DestPtr) || (DestWordLength == 0)) {
+ return XST_INVALID_PARAM;
+ }
+
+ if (TransferType == XDCFG_CONCURRENT_NONSEC_READ_WRITE) {
+ /* Enable internal PCAP loopback */
+ CtrlReg = XDcfg_ReadReg(InstancePtr->Config.BaseAddr,
+ XDCFG_MCTRL_OFFSET);
+ XDcfg_WriteReg(InstancePtr->Config.BaseAddr,
+ XDCFG_MCTRL_OFFSET, (CtrlReg |
+ XDCFG_MCTRL_PCAP_LPBK_MASK));
+
+ /*
+ * Clear QUARTER_PCAP_RATE_EN bit
+ * so that the PCAP data is transmitted every clock
+ */
+ CtrlReg = XDcfg_ReadReg(InstancePtr->Config.BaseAddr,
+ XDCFG_CTRL_OFFSET);
+
+ XDcfg_WriteReg(InstancePtr->Config.BaseAddr,
+ XDCFG_CTRL_OFFSET, (CtrlReg &
+ ~XDCFG_CTRL_PCAP_RATE_EN_MASK));
+
+ }
+ if (TransferType == XDCFG_CONCURRENT_SECURE_READ_WRITE) {
+ /* Clear internal PCAP loopback */
+ CtrlReg = XDcfg_ReadReg(InstancePtr->Config.BaseAddr,
+ XDCFG_MCTRL_OFFSET);
+ XDcfg_WriteReg(InstancePtr->Config.BaseAddr,
+ XDCFG_MCTRL_OFFSET, (CtrlReg &
+ ~(XDCFG_MCTRL_PCAP_LPBK_MASK)));
+
+ /*
+ * Set the QUARTER_PCAP_RATE_EN bit
+ * so that the PCAP data is transmitted every 4 clock
+ * cycles, this is required for encrypted data.
+ */
+ XDcfg_SetControlRegister(InstancePtr,
+ XDCFG_CTRL_PCAP_RATE_EN_MASK);
+ }
+
+ XDcfg_InitiateDma(InstancePtr, (u32)SourcePtr,
+ (u32)DestPtr, SrcWordLength, DestWordLength);
+ }
+
+ return XST_SUCCESS;
+}
+/** @} */
diff --git a/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/devcfg_v3_5/src/xdevcfg.h b/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/devcfg_v3_5/src/xdevcfg.h
new file mode 100644
index 0000000..05105ce
--- /dev/null
+++ b/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/devcfg_v3_5/src/xdevcfg.h
@@ -0,0 +1,397 @@
+/******************************************************************************
+*
+* Copyright (C) 2010 - 2017 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+* THE SOFTWARE.
+*
+*
+*
+******************************************************************************/
+/****************************************************************************/
+/**
+*
+* @file xdevcfg.h
+* @addtogroup devcfg_v3_5
+* @{
+* @details
+*
+* The is the main header file for the Device Configuration Interface of the Zynq
+* device. The device configuration interface has three main functionality.
+* 1. AXI-PCAP
+* 2. Security Policy
+* 3. XADC
+* This current version of the driver supports only the AXI-PCAP and Security
+* Policy blocks. There is a separate driver for XADC.
+*
+* AXI-PCAP is used for download/upload an encrypted or decrypted bitstream.
+* DMA embedded in the AXI PCAP provides the master interface to
+* the Device configuration block for any DMA transfers. The data transfer can
+* take place between the Tx/RxFIFOs of AXI-PCAP and memory (on chip
+* RAM/DDR/peripheral memory).
+*
+* The current driver only supports the downloading the FPGA bitstream and
+* readback of the decrypted image (sort of loopback).
+* The driver does not know what information needs to be written to the FPGA to
+* readback FPGA configuration register or memory data. The application above the
+* driver should take care of creating the data that needs to be downloaded to
+* the FPGA so that the bitstream can be readback.
+* This driver also does not support the reading of the internal registers of the
+* PCAP. The driver has no knowledge of the PCAP internals.
+*
+* <b> Initialization and Configuration </b>
+*
+* The device driver enables higher layer software (e.g., an application) to
+* communicate with the Device Configuration device.
+*
+* XDcfg_CfgInitialize() API is used to initialize the Device Configuration
+* Interface. The user needs to first call the XDcfg_LookupConfig() API which
+* returns the Configuration structure pointer which is passed as a parameter to
+* the XDcfg_CfgInitialize() API.
+*
+* <b>Interrupts</b>
+* The Driver implements an interrupt handler to support the interrupts provided
+* by this interface.
+*
+* <b> Threads </b>
+*
+* This driver is not thread safe. Any needs for threads or thread mutual
+* exclusion must be satisfied by the layer above this driver.
+*
+* <b> Asserts </b>
+*
+* Asserts are used within all Xilinx drivers to enforce constraints on argument
+* values. Asserts can be turned off on a system-wide basis by defining, at
+* compile time, the NDEBUG identifier. By default, asserts are turned on and it
+* is recommended that users leave asserts on during development.
+*
+* <b> Building the driver </b>
+*
+* The XDcfg driver is composed of several source files. This allows the user
+* to build and link only those parts of the driver that are necessary.
+*
+* <br><br>
+*
+* <pre>
+* MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ----- --- -------- ---------------------------------------------
+* 1.00a hvm 02/07/11 First release
+* 2.00a nm 05/31/12 Updated the driver for CR 660835 so that input length for
+* source/destination to the XDcfg_InitiateDma, XDcfg_Transfer
+* APIs is words (32 bit) and not bytes.
+* Updated the notes for XDcfg_InitiateDma/XDcfg_Transfer APIs
+* to add information that 2 LSBs of the Source/Destination
+* address when equal to 2�b01 indicate the last DMA command
+* of an overall transfer.
+* Destination Address passed to this API for secure transfers
+* instead of using 0xFFFFFFFF for CR 662197. This issue was
+* resulting in the failure of secure transfers of
+* non-bitstream images.
+* 2.01a nm 07/07/12 Updated the XDcfg_IntrClear function to directly
+* set the mask instead of oring it with the
+* value read from the interrupt status register
+* Added defines for the PS Version bits,
+* removed the FIFO Flush bits from the
+* Miscellaneous Control Reg.
+* Added XDcfg_GetPsVersion, XDcfg_SelectIcapInterface
+* and XDcfg_SelectPcapInterface APIs for CR 643295
+* The user has to call the XDcfg_SelectIcapInterface API
+* for the PL reconfiguration using AXI HwIcap.
+* Updated the XDcfg_Transfer API to clear the
+* QUARTER_PCAP_RATE_EN bit in the control register for
+* non secure writes for CR 675543.
+* 2.02a nm 01/31/13 Fixed CR# 679335.
+* Added Setting and Clearing the internal PCAP loopback.
+* Removed code for enabling/disabling AES engine as BootROM
+* locks down this setting.
+* Fixed CR# 681976.
+* Skip Checking the PCFG_INIT in case of non-secure DMA
+* loopback.
+* Fixed CR# 699558.
+* XDcfg_Transfer fails to transfer data in loopback mode.
+* Fixed CR# 701348.
+* Peripheral test fails with Running
+* DcfgSelfTestExample() in SECURE bootmode.
+* 2.03a nm 04/19/13 Fixed CR# 703728.
+* Updated the register definitions as per the latest TRM
+* version UG585 (v1.4) November 16, 2012.
+* 3.0 adk 10/12/13 Updated as per the New Tcl API's
+* 3.0 kpc 21/02/14 Added function prototype for XDcfg_ClearControlRegister
+* 3.2 sb 08/25/14 Fixed XDcfg_PcapReadback() function
+* updated driver code with != instead of ==,
+* while checking for Interrupt Status with DMA and
+* PCAP Done Mask
+* ((XDcfg_ReadReg(InstancePtr->Config.BaseAddr,
+* XDCFG_INT_STS_OFFSET) &
+* XDCFG_IXR_D_P_DONE_MASK) !=
+* XDCFG_IXR_D_P_DONE_MASK);
+* A new example has been added to read back the
+* configuration registers from the PL region.
+* xdevcfg_reg_readback_example.c
+* 3.3 sk 04/06/15 Modified XDcfg_ReadMultiBootConfig Macro CR# 851335.
+* ms 03/17/17 Added readme.txt file in examples folder for doxygen
+* generation.
+* ms 04/10/17 Modified filename tag in interrupt and polled examples
+* to include them in doxygen examples.
+* 3.5 ms 04/18/17 Modified tcl file to add suffix U for all macros
+* definitions of devcfg in xparameters.h
+* ms 08/07/17 Fixed compilation warnings in xdevcfg_sinit.c
+* </pre>
+*
+******************************************************************************/
+#ifndef XDCFG_H /* prevent circular inclusions */
+#define XDCFG_H /* by using protection macros */
+
+/***************************** Include Files *********************************/
+
+#include "xdevcfg_hw.h"
+#include "xstatus.h"
+#include "xil_assert.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/************************** Constant Definitions *****************************/
+
+/* Types of PCAP transfers */
+
+#define XDCFG_NON_SECURE_PCAP_WRITE 1
+#define XDCFG_SECURE_PCAP_WRITE 2
+#define XDCFG_PCAP_READBACK 3
+#define XDCFG_CONCURRENT_SECURE_READ_WRITE 4
+#define XDCFG_CONCURRENT_NONSEC_READ_WRITE 5
+
+
+/**************************** Type Definitions *******************************/
+/**
+* The handler data type allows the user to define a callback function to
+* respond to interrupt events in the system. This function is executed
+* in interrupt context, so amount of processing should be minimized.
+*
+* @param CallBackRef is the callback reference passed in by the upper
+* layer when setting the callback functions, and passed back to
+* the upper layer when the callback is invoked. Its type is
+* unimportant to the driver component, so it is a void pointer.
+* @param Status is the Interrupt status of the XDcfg device.
+*/
+typedef void (*XDcfg_IntrHandler) (void *CallBackRef, u32 Status);
+
+/**
+ * This typedef contains configuration information for the device.
+ */
+typedef struct {
+ u16 DeviceId; /**< Unique ID of device */
+ u32 BaseAddr; /**< Base address of the device */
+} XDcfg_Config;
+
+/**
+ * The XDcfg driver instance data.
+ */
+typedef struct {
+ XDcfg_Config Config; /**< Hardware Configuration */
+ u32 IsReady; /**< Device is initialized and ready */
+ u32 IsStarted; /**< Device Configuration Interface
+ * is running
+ */
+ XDcfg_IntrHandler StatusHandler; /* Event handler function */
+ void *CallBackRef; /* Callback reference for event handler */
+} XDcfg;
+
+/****************************************************************************/
+/**
+*
+* Unlock the Device Config Interface block.
+*
+* @param InstancePtr is a pointer to the instance of XDcfg driver.
+*
+* @return None.
+*
+* @note C-style signature:
+* void XDcfg_Unlock(XDcfg* InstancePtr)
+*
+*****************************************************************************/
+#define XDcfg_Unlock(InstancePtr) \
+ XDcfg_WriteReg((InstancePtr)->Config.BaseAddr, \
+ XDCFG_UNLOCK_OFFSET, XDCFG_UNLOCK_DATA)
+
+
+
+/****************************************************************************/
+/**
+*
+* Get the version number of the PS from the Miscellaneous Control Register.
+*
+* @param InstancePtr is a pointer to the instance of XDcfg driver.
+*
+* @return Version of the PS.
+*
+* @note C-style signature:
+* void XDcfg_GetPsVersion(XDcfg* InstancePtr)
+*
+*****************************************************************************/
+#define XDcfg_GetPsVersion(InstancePtr) \
+ ((XDcfg_ReadReg((InstancePtr)->Config.BaseAddr, \
+ XDCFG_MCTRL_OFFSET)) & \
+ XDCFG_MCTRL_PCAP_PS_VERSION_MASK) >> \
+ XDCFG_MCTRL_PCAP_PS_VERSION_SHIFT
+
+
+
+/****************************************************************************/
+/**
+*
+* Read the multiboot config register value.
+*
+* @param InstancePtr is a pointer to the instance of XDcfg driver.
+*
+* @return None.
+*
+* @note C-style signature:
+* u32 XDcfg_ReadMultiBootConfig(XDcfg* InstancePtr)
+*
+*****************************************************************************/
+#define XDcfg_ReadMultiBootConfig(InstancePtr) \
+ XDcfg_ReadReg((InstancePtr)->Config.BaseAddr, \
+ XDCFG_MULTIBOOT_ADDR_OFFSET)
+
+
+/****************************************************************************/
+/**
+*
+* Selects ICAP interface for reconfiguration after the initial configuration
+* of the PL.
+*
+* @param InstancePtr is a pointer to the instance of XDcfg driver.
+*
+* @return None.
+*
+* @note C-style signature:
+* void XDcfg_SelectIcapInterface(XDcfg* InstancePtr)
+*
+*****************************************************************************/
+#define XDcfg_SelectIcapInterface(InstancePtr) \
+ XDcfg_WriteReg((InstancePtr)->Config.BaseAddr, XDCFG_CTRL_OFFSET, \
+ ((XDcfg_ReadReg((InstancePtr)->Config.BaseAddr, XDCFG_CTRL_OFFSET)) \
+ & ( ~XDCFG_CTRL_PCAP_PR_MASK)))
+
+/****************************************************************************/
+/**
+*
+* Selects PCAP interface for reconfiguration after the initial configuration
+* of the PL.
+*
+* @param InstancePtr is a pointer to the instance of XDcfg driver.
+*
+* @return None.
+*
+* @note C-style signature:
+* void XDcfg_SelectPcapInterface(XDcfg* InstancePtr)
+*
+*****************************************************************************/
+#define XDcfg_SelectPcapInterface(InstancePtr) \
+ XDcfg_WriteReg((InstancePtr)->Config.BaseAddr, XDCFG_CTRL_OFFSET, \
+ ((XDcfg_ReadReg((InstancePtr)->Config.BaseAddr, XDCFG_CTRL_OFFSET)) \
+ | XDCFG_CTRL_PCAP_PR_MASK))
+
+
+
+/************************** Function Prototypes ******************************/
+
+/*
+ * Lookup configuration in xdevcfg_sinit.c.
+ */
+XDcfg_Config *XDcfg_LookupConfig(u16 DeviceId);
+
+/*
+ * Selftest function in xdevcfg_selftest.c
+ */
+int XDcfg_SelfTest(XDcfg *InstancePtr);
+
+/*
+ * Interface functions in xdevcfg.c
+ */
+int XDcfg_CfgInitialize(XDcfg *InstancePtr,
+ XDcfg_Config *ConfigPtr, u32 EffectiveAddress);
+
+void XDcfg_EnablePCAP(XDcfg *InstancePtr);
+
+void XDcfg_DisablePCAP(XDcfg *InstancePtr);
+
+void XDcfg_SetControlRegister(XDcfg *InstancePtr, u32 Mask);
+
+void XDcfg_ClearControlRegister(XDcfg *InstancePtr, u32 Mask);
+
+u32 XDcfg_GetControlRegister(XDcfg *InstancePtr);
+
+void XDcfg_SetLockRegister(XDcfg *InstancePtr, u32 Data);
+
+u32 XDcfg_GetLockRegister(XDcfg *InstancePtr);
+
+void XDcfg_SetConfigRegister(XDcfg *InstancePtr, u32 Data);
+
+u32 XDcfg_GetConfigRegister(XDcfg *InstancePtr);
+
+void XDcfg_SetStatusRegister(XDcfg *InstancePtr, u32 Data);
+
+u32 XDcfg_GetStatusRegister(XDcfg *InstancePtr);
+
+void XDcfg_SetRomShadowRegister(XDcfg *InstancePtr, u32 Data);
+
+u32 XDcfg_GetSoftwareIdRegister(XDcfg *InstancePtr);
+
+void XDcfg_SetMiscControlRegister(XDcfg *InstancePtr, u32 Mask);
+
+u32 XDcfg_GetMiscControlRegister(XDcfg *InstancePtr);
+
+u32 XDcfg_IsDmaBusy(XDcfg *InstancePtr);
+
+void XDcfg_InitiateDma(XDcfg *InstancePtr, u32 SourcePtr, u32 DestPtr,
+ u32 SrcWordLength, u32 DestWordLength);
+
+u32 XDcfg_Transfer(XDcfg *InstancePtr,
+ void *SourcePtr, u32 SrcWordLength,
+ void *DestPtr, u32 DestWordLength,
+ u32 TransferType);
+
+/*
+ * Interrupt related function prototypes implemented in xdevcfg_intr.c
+ */
+void XDcfg_IntrEnable(XDcfg *InstancePtr, u32 Mask);
+
+void XDcfg_IntrDisable(XDcfg *InstancePtr, u32 Mask);
+
+u32 XDcfg_IntrGetEnabled(XDcfg *InstancePtr);
+
+u32 XDcfg_IntrGetStatus(XDcfg *InstancePtr);
+
+void XDcfg_IntrClear(XDcfg *InstancePtr, u32 Mask);
+
+void XDcfg_InterruptHandler(XDcfg *InstancePtr);
+
+void XDcfg_SetHandler(XDcfg *InstancePtr, void *CallBackFunc,
+ void *CallBackRef);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* end of protection macro */
+/** @} */
diff --git a/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/devcfg_v3_5/src/xdevcfg_g.c b/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/devcfg_v3_5/src/xdevcfg_g.c
new file mode 100644
index 0000000..f5942e7
--- /dev/null
+++ b/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/devcfg_v3_5/src/xdevcfg_g.c
@@ -0,0 +1,47 @@
+
+/*******************************************************************
+*
+* CAUTION: This file is automatically generated by HSI.
+* Version: 2019.2
+* DO NOT EDIT.
+*
+* Copyright (C) 2010-2021 Xilinx, Inc. All Rights Reserved.*
+*Permission is hereby granted, free of charge, to any person obtaining a copy
+*of this software and associated documentation files (the Software), to deal
+*in the Software without restriction, including without limitation the rights
+*to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+*copies of the Software, and to permit persons to whom the Software is
+*furnished to do so, subject to the following conditions:
+*
+*The above copyright notice and this permission notice shall be included in
+*all copies or substantial portions of the Software.
+*
+*THE SOFTWARE IS PROVIDED AS IS, WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+*IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+*FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+*THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+*WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT
+*OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+*
+
+*
+* Description: Driver configuration
+*
+*******************************************************************/
+
+#include "xparameters.h"
+#include "xdevcfg.h"
+
+/*
+* The configuration table for devices
+*/
+
+XDcfg_Config XDcfg_ConfigTable[] =
+{
+ {
+ XPAR_PS7_DEV_CFG_0_DEVICE_ID,
+ XPAR_PS7_DEV_CFG_0_BASEADDR
+ }
+};
+
+
diff --git a/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/devcfg_v3_5/src/xdevcfg_hw.c b/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/devcfg_v3_5/src/xdevcfg_hw.c
new file mode 100644
index 0000000..3037099
--- /dev/null
+++ b/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/devcfg_v3_5/src/xdevcfg_hw.c
@@ -0,0 +1,107 @@
+/******************************************************************************
+*
+* Copyright (C) 2010 - 2015 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+* THE SOFTWARE.
+*
+*
+*
+******************************************************************************/
+/****************************************************************************/
+/**
+*
+* @file xdevcfg_hw.c
+* @addtogroup devcfg_v3_5
+* @{
+*
+* This file contains the implementation of the interface reset functionality
+* <pre>
+* MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ----- --- -------- ---------------------------------------------
+* 2.04a kpc 10/07/13 First release
+* </pre>
+*
+******************************************************************************/
+
+/***************************** Include Files *********************************/
+
+#include "xdevcfg_hw.h"
+
+/************************** Constant Definitions *****************************/
+
+/**************************** Type Definitions *******************************/
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/************************** Function Prototypes ******************************/
+
+/************************** Variable Definitions *****************************/
+
+/*****************************************************************************/
+/**
+* This function perform the reset sequence to the given devcfg interface by
+* configuring the appropriate control bits in the devcfg specifc registers
+* the devcfg reset squence involves the following steps
+* Disable all the interuupts
+* Clear the status
+* Update relevant config registers with reset values
+* Disbale the looopback mode and pcap rate enable
+*
+* @param BaseAddress of the interface
+*
+* @return N/A
+*
+* @note
+* This function will not modify the slcr registers that are relavant for
+* devcfg controller
+******************************************************************************/
+void XDcfg_ResetHw(u32 BaseAddr)
+{
+ u32 Regval = 0;
+
+ /* Mask the interrupts */
+ XDcfg_WriteReg(BaseAddr, XDCFG_INT_MASK_OFFSET,
+ XDCFG_IXR_ALL_MASK);
+ /* Clear the interuupt status */
+ Regval = XDcfg_ReadReg(BaseAddr, XDCFG_INT_STS_OFFSET);
+ XDcfg_WriteReg(BaseAddr, XDCFG_INT_STS_OFFSET, Regval);
+ /* Clear the source address register */
+ XDcfg_WriteReg(BaseAddr, XDCFG_DMA_SRC_ADDR_OFFSET, 0x0);
+ /* Clear the destination address register */
+ XDcfg_WriteReg(BaseAddr, XDCFG_DMA_DEST_ADDR_OFFSET, 0x0);
+ /* Clear the source length register */
+ XDcfg_WriteReg(BaseAddr, XDCFG_DMA_SRC_LEN_OFFSET, 0x0);
+ /* Clear the destination length register */
+ XDcfg_WriteReg(BaseAddr, XDCFG_DMA_DEST_LEN_OFFSET, 0x0);
+ /* Clear the loopback enable bit */
+ Regval = XDcfg_ReadReg(BaseAddr, XDCFG_MCTRL_OFFSET);
+ Regval = Regval & ~XDCFG_MCTRL_PCAP_LPBK_MASK;
+ XDcfg_WriteReg(BaseAddr, XDCFG_MCTRL_OFFSET, Regval);
+ /*Reset the configuration register to reset value */
+ XDcfg_WriteReg(BaseAddr, XDCFG_CFG_OFFSET,
+ XDCFG_CONFIG_RESET_VALUE);
+ /*Disable the PCAP rate enable bit */
+ Regval = XDcfg_ReadReg(BaseAddr, XDCFG_CTRL_OFFSET);
+ Regval = Regval & ~XDCFG_CTRL_PCAP_RATE_EN_MASK;
+ XDcfg_WriteReg(BaseAddr, XDCFG_CTRL_OFFSET, Regval);
+
+}
+/** @} */
diff --git a/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/devcfg_v3_5/src/xdevcfg_hw.h b/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/devcfg_v3_5/src/xdevcfg_hw.h
new file mode 100644
index 0000000..56a9f41
--- /dev/null
+++ b/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/devcfg_v3_5/src/xdevcfg_hw.h
@@ -0,0 +1,389 @@
+/******************************************************************************
+*
+* Copyright (C) 2010 - 2015 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+* THE SOFTWARE.
+*
+*
+*
+******************************************************************************/
+/****************************************************************************/
+/**
+*
+* @file xdevcfg_hw.h
+* @addtogroup devcfg_v3_3
+* @{
+*
+* This file contains the hardware interface to the Device Config Interface.
+*
+* <pre>
+* MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ----- --- -------- ---------------------------------------------
+* 1.00a hvm 02/07/11 First release
+* 2.01a nm 08/01/12 Added defines for the PS Version bits,
+* removed the FIFO Flush bits from the
+* Miscellaneous Control Reg
+* 2.03a nm 04/19/13 Fixed CR# 703728.
+* Updated the register definitions as per the latest TRM
+* version UG585 (v1.4) November 16, 2012.
+* 2.04a kpc 10/07/13 Added function prototype.
+* 3.00a kpc 25/02/14 Corrected the XDCFG_BASE_ADDRESS macro value.
+* </pre>
+*
+******************************************************************************/
+#ifndef XDCFG_HW_H /* prevent circular inclusions */
+#define XDCFG_HW_H /* by using protection macros */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/***************************** Include Files *********************************/
+
+#include "xil_types.h"
+#include "xil_io.h"
+
+/************************** Constant Definitions *****************************/
+
+/** @name Register Map
+ * Offsets of registers from the start of the device
+ * @{
+ */
+
+#define XDCFG_CTRL_OFFSET 0x00 /**< Control Register */
+#define XDCFG_LOCK_OFFSET 0x04 /**< Lock Register */
+#define XDCFG_CFG_OFFSET 0x08 /**< Configuration Register */
+#define XDCFG_INT_STS_OFFSET 0x0C /**< Interrupt Status Register */
+#define XDCFG_INT_MASK_OFFSET 0x10 /**< Interrupt Mask Register */
+#define XDCFG_STATUS_OFFSET 0x14 /**< Status Register */
+#define XDCFG_DMA_SRC_ADDR_OFFSET 0x18 /**< DMA Source Address Register */
+#define XDCFG_DMA_DEST_ADDR_OFFSET 0x1C /**< DMA Destination Address Reg */
+#define XDCFG_DMA_SRC_LEN_OFFSET 0x20 /**< DMA Source Transfer Length */
+#define XDCFG_DMA_DEST_LEN_OFFSET 0x24 /**< DMA Destination Transfer */
+#define XDCFG_ROM_SHADOW_OFFSET 0x28 /**< DMA ROM Shadow Register */
+#define XDCFG_MULTIBOOT_ADDR_OFFSET 0x2C /**< Multi BootAddress Pointer */
+#define XDCFG_SW_ID_OFFSET 0x30 /**< Software ID Register */
+#define XDCFG_UNLOCK_OFFSET 0x34 /**< Unlock Register */
+#define XDCFG_MCTRL_OFFSET 0x80 /**< Miscellaneous Control Reg */
+
+/* @} */
+
+/** @name Control Register Bit definitions
+ * @{
+ */
+
+#define XDCFG_CTRL_FORCE_RST_MASK 0x80000000 /**< Force into
+ * Secure Reset
+ */
+#define XDCFG_CTRL_PCFG_PROG_B_MASK 0x40000000 /**< Program signal to
+ * Reset FPGA
+ */
+#define XDCFG_CTRL_PCFG_POR_CNT_4K_MASK 0x20000000 /**< Control PL POR timer */
+#define XDCFG_CTRL_PCAP_PR_MASK 0x08000000 /**< Enable PCAP for PR */
+#define XDCFG_CTRL_PCAP_MODE_MASK 0x04000000 /**< Enable PCAP */
+#define XDCFG_CTRL_PCAP_RATE_EN_MASK 0x02000000 /**< Enable PCAP send data
+ * to FPGA every 4 PCAP
+ * cycles
+ */
+#define XDCFG_CTRL_MULTIBOOT_EN_MASK 0x01000000 /**< Multiboot Enable */
+#define XDCFG_CTRL_JTAG_CHAIN_DIS_MASK 0x00800000 /**< JTAG Chain Disable */
+#define XDCFG_CTRL_USER_MODE_MASK 0x00008000 /**< User Mode Mask */
+#define XDCFG_CTRL_PCFG_AES_FUSE_MASK 0x00001000 /**< AES key source */
+#define XDCFG_CTRL_PCFG_AES_EN_MASK 0x00000E00 /**< AES Enable Mask */
+#define XDCFG_CTRL_SEU_EN_MASK 0x00000100 /**< SEU Enable Mask */
+#define XDCFG_CTRL_SEC_EN_MASK 0x00000080 /**< Secure/Non Secure
+ * Status mask
+ */
+#define XDCFG_CTRL_SPNIDEN_MASK 0x00000040 /**< Secure Non Invasive
+ * Debug Enable
+ */
+#define XDCFG_CTRL_SPIDEN_MASK 0x00000020 /**< Secure Invasive
+ * Debug Enable
+ */
+#define XDCFG_CTRL_NIDEN_MASK 0x00000010 /**< Non-Invasive Debug
+ * Enable
+ */
+#define XDCFG_CTRL_DBGEN_MASK 0x00000008 /**< Invasive Debug
+ * Enable
+ */
+#define XDCFG_CTRL_DAP_EN_MASK 0x00000007 /**< DAP Enable Mask */
+
+/* @} */
+
+/** @name Lock register bit definitions
+ * @{
+ */
+
+#define XDCFG_LOCK_AES_EFUSE_MASK 0x00000010 /**< Lock AES Efuse bit */
+#define XDCFG_LOCK_AES_EN_MASK 0x00000008 /**< Lock AES_EN update */
+#define XDCFG_LOCK_SEU_MASK 0x00000004 /**< Lock SEU_En update */
+#define XDCFG_LOCK_SEC_MASK 0x00000002 /**< Lock SEC_EN and
+ * USER_MODE
+ */
+#define XDCFG_LOCK_DBG_MASK 0x00000001 /**< This bit locks
+ * security config
+ * including: DAP_En,
+ * DBGEN,,
+ * NIDEN, SPNIEN
+ */
+/*@}*/
+
+
+
+/** @name Config Register Bit definitions
+ * @{
+ */
+#define XDCFG_CFG_RFIFO_TH_MASK 0x00000C00 /**< Read FIFO
+ * Threshold Mask
+ */
+#define XDCFG_CFG_WFIFO_TH_MASK 0x00000300 /**< Write FIFO Threshold
+ * Mask
+ */
+#define XDCFG_CFG_RCLK_EDGE_MASK 0x00000080 /**< Read data active
+ * clock edge
+ */
+#define XDCFG_CFG_WCLK_EDGE_MASK 0x00000040 /**< Write data active
+ * clock edge
+ */
+#define XDCFG_CFG_DISABLE_SRC_INC_MASK 0x00000020 /**< Disable Source address
+ * increment mask
+ */
+#define XDCFG_CFG_DISABLE_DST_INC_MASK 0x00000010 /**< Disable Destination
+ * address increment
+ * mask
+ */
+/* @} */
+
+
+/** @name Interrupt Status/Mask Register Bit definitions
+ * @{
+ */
+#define XDCFG_IXR_PSS_GTS_USR_B_MASK 0x80000000 /**< Tri-state IO during
+ * HIZ
+ */
+#define XDCFG_IXR_PSS_FST_CFG_B_MASK 0x40000000 /**< First configuration
+ * done
+ */
+#define XDCFG_IXR_PSS_GPWRDWN_B_MASK 0x20000000 /**< Global power down */
+#define XDCFG_IXR_PSS_GTS_CFG_B_MASK 0x10000000 /**< Tri-state IO during
+ * configuration
+ */
+#define XDCFG_IXR_PSS_CFG_RESET_B_MASK 0x08000000 /**< PL configuration
+ * reset
+ */
+#define XDCFG_IXR_AXI_WTO_MASK 0x00800000 /**< AXI Write Address
+ * or Data or response
+ * timeout
+ */
+#define XDCFG_IXR_AXI_WERR_MASK 0x00400000 /**< AXI Write response
+ * error
+ */
+#define XDCFG_IXR_AXI_RTO_MASK 0x00200000 /**< AXI Read Address or
+ * response timeout
+ */
+#define XDCFG_IXR_AXI_RERR_MASK 0x00100000 /**< AXI Read response
+ * error
+ */
+#define XDCFG_IXR_RX_FIFO_OV_MASK 0x00040000 /**< Rx FIFO Overflow */
+#define XDCFG_IXR_WR_FIFO_LVL_MASK 0x00020000 /**< Tx FIFO less than
+ * threshold */
+#define XDCFG_IXR_RD_FIFO_LVL_MASK 0x00010000 /**< Rx FIFO greater than
+ * threshold */
+#define XDCFG_IXR_DMA_CMD_ERR_MASK 0x00008000 /**< Illegal DMA command */
+#define XDCFG_IXR_DMA_Q_OV_MASK 0x00004000 /**< DMA command queue
+ * overflow
+ */
+#define XDCFG_IXR_DMA_DONE_MASK 0x00002000 /**< DMA Command Done */
+#define XDCFG_IXR_D_P_DONE_MASK 0x00001000 /**< DMA and PCAP
+ * transfers Done
+ */
+#define XDCFG_IXR_P2D_LEN_ERR_MASK 0x00000800 /**< PCAP to DMA transfer
+ * length error
+ */
+#define XDCFG_IXR_PCFG_HMAC_ERR_MASK 0x00000040 /**< HMAC error mask */
+#define XDCFG_IXR_PCFG_SEU_ERR_MASK 0x00000020 /**< SEU Error mask */
+#define XDCFG_IXR_PCFG_POR_B_MASK 0x00000010 /**< FPGA POR mask */
+#define XDCFG_IXR_PCFG_CFG_RST_MASK 0x00000008 /**< FPGA Reset mask */
+#define XDCFG_IXR_PCFG_DONE_MASK 0x00000004 /**< Done Signal Mask */
+#define XDCFG_IXR_PCFG_INIT_PE_MASK 0x00000002 /**< Detect Positive edge
+ * of Init Signal
+ */
+#define XDCFG_IXR_PCFG_INIT_NE_MASK 0x00000001 /**< Detect Negative edge
+ * of Init Signal
+ */
+#define XDCFG_IXR_ERROR_FLAGS_MASK (XDCFG_IXR_AXI_WTO_MASK | \
+ XDCFG_IXR_AXI_WERR_MASK | \
+ XDCFG_IXR_AXI_RTO_MASK | \
+ XDCFG_IXR_AXI_RERR_MASK | \
+ XDCFG_IXR_RX_FIFO_OV_MASK | \
+ XDCFG_IXR_DMA_CMD_ERR_MASK |\
+ XDCFG_IXR_DMA_Q_OV_MASK | \
+ XDCFG_IXR_P2D_LEN_ERR_MASK |\
+ XDCFG_IXR_PCFG_HMAC_ERR_MASK)
+
+
+#define XDCFG_IXR_ALL_MASK 0x00F7F8EF
+
+
+
+/* @} */
+
+
+/** @name Status Register Bit definitions
+ * @{
+ */
+#define XDCFG_STATUS_DMA_CMD_Q_F_MASK 0x80000000 /**< DMA command
+ * Queue full
+ */
+#define XDCFG_STATUS_DMA_CMD_Q_E_MASK 0x40000000 /**< DMA command
+ * Queue empty
+ */
+#define XDCFG_STATUS_DMA_DONE_CNT_MASK 0x30000000 /**< Number of
+ * completed DMA
+ * transfers
+ */
+#define XDCFG_STATUS_RX_FIFO_LVL_MASK 0x01F000000 /**< Rx FIFO level */
+#define XDCFG_STATUS_TX_FIFO_LVL_MASK 0x0007F000 /**< Tx FIFO level */
+
+#define XDCFG_STATUS_PSS_GTS_USR_B 0x00000800 /**< Tri-state IO
+ * during HIZ
+ */
+#define XDCFG_STATUS_PSS_FST_CFG_B 0x00000400 /**< First PL config
+ * done
+ */
+#define XDCFG_STATUS_PSS_GPWRDWN_B 0x00000200 /**< Global power down */
+#define XDCFG_STATUS_PSS_GTS_CFG_B 0x00000100 /**< Tri-state IO during
+ * config
+ */
+#define XDCFG_STATUS_SECURE_RST_MASK 0x00000080 /**< Secure Reset
+ * POR Status
+ */
+#define XDCFG_STATUS_ILLEGAL_APB_ACCESS_MASK 0x00000040 /**< Illegal APB
+ * access
+ */
+#define XDCFG_STATUS_PSS_CFG_RESET_B 0x00000020 /**< PL config
+ * reset status
+ */
+#define XDCFG_STATUS_PCFG_INIT_MASK 0x00000010 /**< FPGA Init
+ * Status
+ */
+#define XDCFG_STATUS_EFUSE_BBRAM_KEY_DISABLE_MASK 0x00000008
+ /**< BBRAM key
+ * disable
+ */
+#define XDCFG_STATUS_EFUSE_SEC_EN_MASK 0x00000004 /**< Efuse Security
+ * Enable Status
+ */
+#define XDCFG_STATUS_EFUSE_JTAG_DIS_MASK 0x00000002 /**< EFuse JTAG
+ * Disable
+ * status
+ */
+/* @} */
+
+
+/** @name DMA Source/Destination Transfer Length Register Bit definitions
+ * @{
+ */
+#define XDCFG_DMA_LEN_MASK 0x7FFFFFF /**< Length Mask */
+/*@}*/
+
+
+
+
+/** @name Miscellaneous Control Register Bit definitions
+ * @{
+ */
+#define XDCFG_MCTRL_PCAP_PS_VERSION_MASK 0xF0000000 /**< PS Version Mask */
+#define XDCFG_MCTRL_PCAP_PS_VERSION_SHIFT 28 /**< PS Version Shift */
+#define XDCFG_MCTRL_PCAP_LPBK_MASK 0x00000010 /**< PCAP loopback mask */
+/* @} */
+
+/** @name FIFO Threshold Bit definitions
+ * @{
+ */
+
+#define XDCFG_CFG_FIFO_QUARTER 0x0 /**< Quarter empty */
+#define XDCFG_CFG_FIFO_HALF 0x1 /**< Half empty */
+#define XDCFG_CFG_FIFO_3QUARTER 0x2 /**< 3/4 empty */
+#define XDCFG_CFG_FIFO_EMPTY 0x4 /**< Empty */
+/* @}*/
+
+
+/* Miscellaneous constant values */
+#define XDCFG_DMA_INVALID_ADDRESS 0xFFFFFFFF /**< Invalid DMA address */
+#define XDCFG_UNLOCK_DATA 0x757BDF0D /**< First APB access data*/
+#define XDCFG_BASE_ADDRESS 0xF8007000 /**< Device Config base
+ * address
+ */
+#define XDCFG_CONFIG_RESET_VALUE 0x508 /**< Config reg reset value */
+
+/**************************** Type Definitions *******************************/
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/****************************************************************************/
+/**
+*
+* Read the given register.
+*
+* @param BaseAddr is the base address of the device
+* @param RegOffset is the register offset to be read
+*
+* @return The 32-bit value of the register
+*
+* @note C-style signature:
+* u32 XDcfg_ReadReg(u32 BaseAddr, u32 RegOffset)
+*
+*****************************************************************************/
+#define XDcfg_ReadReg(BaseAddr, RegOffset) \
+ Xil_In32((BaseAddr) + (RegOffset))
+
+/****************************************************************************/
+/**
+*
+* Write to the given register.
+*
+* @param BaseAddr is the base address of the device
+* @param RegOffset is the register offset to be written
+* @param Data is the 32-bit value to write to the register
+*
+* @return None.
+*
+* @note C-style signature:
+* void XDcfg_WriteReg(u32 BaseAddr, u32 RegOffset, u32 Data)
+*
+*****************************************************************************/
+#define XDcfg_WriteReg(BaseAddr, RegOffset, Data) \
+ Xil_Out32((BaseAddr) + (RegOffset), (Data))
+
+/************************** Function Prototypes ******************************/
+/*
+ * Perform reset operation to the devcfg interface
+ */
+void XDcfg_ResetHw(u32 BaseAddr);
+/************************** Variable Definitions *****************************/
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* end of protection macro */
+/** @} */
diff --git a/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/devcfg_v3_5/src/xdevcfg_intr.c b/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/devcfg_v3_5/src/xdevcfg_intr.c
new file mode 100644
index 0000000..16f7689
--- /dev/null
+++ b/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/devcfg_v3_5/src/xdevcfg_intr.c
@@ -0,0 +1,304 @@
+/******************************************************************************
+*
+* Copyright (C) 2010 - 2015 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+* THE SOFTWARE.
+*
+*
+*
+******************************************************************************/
+/****************************************************************************/
+/**
+*
+* @file xdevcfg_intr.c
+* @addtogroup devcfg_v3_5
+* @{
+*
+* Contains the implementation of interrupt related functions of the XDcfg
+* driver.
+*
+* <pre>
+* MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ----- --- -------- ---------------------------------------------
+* 1.00a hvm 02/07/11 First release
+* 2.01a nm 07/07/12 Updated the XDcfg_IntrClear function to directly
+* set the mask instead of oring it with the
+* value read from the interrupt status register
+* </pre>
+*
+******************************************************************************/
+
+/***************************** Include Files *********************************/
+
+#include "xdevcfg.h"
+
+/************************** Constant Definitions *****************************/
+
+/**************************** Type Definitions *******************************/
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/************************** Function Prototypes ******************************/
+
+/************************** Variable Definitions *****************************/
+
+/****************************************************************************/
+/**
+*
+* This function enables the specified interrupts in the device.
+*
+* @param InstancePtr is a pointer to the XDcfg instance.
+* @param Mask is the bit-mask of the interrupts to be enabled.
+* Bit positions of 1 will be enabled. Bit positions of 0 will
+* keep the previous setting. This mask is formed by OR'ing
+* XDCFG_INT_* bits defined in xdevcfg_hw.h.
+*
+* @return None.
+*
+* @note None.
+*
+*****************************************************************************/
+void XDcfg_IntrEnable(XDcfg *InstancePtr, u32 Mask)
+{
+ u32 RegValue;
+
+ /*
+ * Assert the arguments.
+ */
+ Xil_AssertVoid(InstancePtr != NULL);
+ Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+ /*
+ * Enable the specified interrupts in the Interrupt Mask Register.
+ */
+ RegValue = XDcfg_ReadReg(InstancePtr->Config.BaseAddr,
+ XDCFG_INT_MASK_OFFSET);
+ RegValue &= ~(Mask & XDCFG_IXR_ALL_MASK);
+ XDcfg_WriteReg(InstancePtr->Config.BaseAddr,
+ XDCFG_INT_MASK_OFFSET,
+ RegValue);
+}
+
+
+/****************************************************************************/
+/**
+*
+* This function disables the specified interrupts in the device.
+*
+* @param InstancePtr is a pointer to the XDcfg instance.
+* @param Mask is the bit-mask of the interrupts to be disabled.
+* Bit positions of 1 will be disabled. Bit positions of 0 will
+* keep the previous setting. This mask is formed by OR'ing
+* XDCFG_INT_* bits defined in xdevcfg_hw.h.
+*
+* @return None.
+*
+* @note None.
+*
+*****************************************************************************/
+void XDcfg_IntrDisable(XDcfg *InstancePtr, u32 Mask)
+{
+ u32 RegValue;
+
+ /*
+ * Assert the arguments.
+ */
+ Xil_AssertVoid(InstancePtr != NULL);
+ Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+ /*
+ * Disable the specified interrupts in the Interrupt Mask Register.
+ */
+ RegValue = XDcfg_ReadReg(InstancePtr->Config.BaseAddr,
+ XDCFG_INT_MASK_OFFSET);
+ RegValue |= (Mask & XDCFG_IXR_ALL_MASK);
+ XDcfg_WriteReg(InstancePtr->Config.BaseAddr,
+ XDCFG_INT_MASK_OFFSET,
+ RegValue);
+}
+/****************************************************************************/
+/**
+*
+* This function returns the enabled interrupts read from the Interrupt Mask
+* Register. Use the XDCFG_INT_* constants defined in xdevcfg_hw.h
+* to interpret the returned value.
+*
+* @param InstancePtr is a pointer to the XDcfg instance.
+*
+* @return A 32-bit value representing the contents of the IMR.
+*
+* @note None.
+*
+*****************************************************************************/
+u32 XDcfg_IntrGetEnabled(XDcfg *InstancePtr)
+{
+ /*
+ * Assert the arguments.
+ */
+ Xil_AssertNonvoid(InstancePtr != NULL);
+ Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+ /*
+ * Return the value read from the Interrupt Mask Register.
+ */
+ return (~ XDcfg_ReadReg(InstancePtr->Config.BaseAddr,
+ XDCFG_INT_MASK_OFFSET));
+}
+
+/****************************************************************************/
+/**
+*
+* This function returns the interrupt status read from Interrupt Status
+* Register. Use the XDCFG_INT_* constants defined in xdevcfg_hw.h
+* to interpret the returned value.
+*
+* @param InstancePtr is a pointer to the XDcfg instance.
+*
+* @return A 32-bit value representing the contents of the Interrupt
+* Status register.
+*
+* @note None.
+*
+*****************************************************************************/
+u32 XDcfg_IntrGetStatus(XDcfg *InstancePtr)
+{
+ /*
+ * Assert the arguments.
+ */
+ Xil_AssertNonvoid(InstancePtr != NULL);
+ Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+ /*
+ * Return the value read from the Interrupt Status register.
+ */
+ return XDcfg_ReadReg(InstancePtr->Config.BaseAddr,
+ XDCFG_INT_STS_OFFSET);
+}
+
+/****************************************************************************/
+/**
+*
+* This function clears the specified interrupts in the Interrupt Status
+* Register.
+*
+* @param InstancePtr is a pointer to the XDcfg instance.
+* @param Mask is the bit-mask of the interrupts to be cleared.
+* Bit positions of 1 will be cleared. Bit positions of 0 will not
+* change the previous interrupt status. This mask is formed by
+* OR'ing XDCFG_INT_* bits which are defined in xdevcfg_hw.h.
+*
+* @return None.
+*
+* @note None.
+*
+*****************************************************************************/
+void XDcfg_IntrClear(XDcfg *InstancePtr, u32 Mask)
+{
+ /*
+ * Assert the arguments.
+ */
+ Xil_AssertVoid(InstancePtr != NULL);
+ Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+ XDcfg_WriteReg(InstancePtr->Config.BaseAddr,
+ XDCFG_INT_STS_OFFSET,
+ Mask);
+
+}
+
+/*****************************************************************************/
+/**
+* The interrupt handler for the Device Config Interface.
+*
+* Events are signaled to upper layer for proper handling.
+*
+*
+* @param InstancePtr is a pointer to the XDcfg instance.
+*
+* @return None.
+*
+* @note None.
+*
+****************************************************************************/
+void XDcfg_InterruptHandler(XDcfg *InstancePtr)
+{
+ u32 IntrStatusReg;
+
+ /*
+ * Assert validates the input arguments.
+ */
+ Xil_AssertVoid(InstancePtr != NULL);
+ Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+ /*
+ * Read the Interrupt status register.
+ */
+ IntrStatusReg = XDcfg_ReadReg(InstancePtr->Config.BaseAddr,
+ XDCFG_INT_STS_OFFSET);
+
+ /*
+ * Write the status back to clear the interrupts so that no
+ * subsequent interrupts are missed while processing this interrupt.
+ * This also does the DMA acknowledgment automatically.
+ */
+ XDcfg_WriteReg(InstancePtr->Config.BaseAddr,
+ XDCFG_INT_STS_OFFSET, IntrStatusReg);
+
+ /*
+ * Signal application that there are events to handle.
+ */
+ InstancePtr->StatusHandler(InstancePtr->CallBackRef,
+ IntrStatusReg);
+
+}
+
+/****************************************************************************/
+/**
+*
+* This function sets the handler that will be called when an event (interrupt)
+* occurs that needs application's attention.
+*
+* @param InstancePtr is a pointer to the XDcfg instance
+* @param CallBackFunc is the address of the callback function.
+* @param CallBackRef is a user data item that will be passed to the
+* callback function when it is invoked.
+*
+* @return None.
+*
+* @note None.
+*
+*
+*****************************************************************************/
+void XDcfg_SetHandler(XDcfg *InstancePtr, void *CallBackFunc,
+ void *CallBackRef)
+{
+ /*
+ * Asserts validate the input arguments
+ * CallBackRef not checked, no way to know what is valid
+ */
+ Xil_AssertVoid(InstancePtr != NULL);
+ Xil_AssertVoid(CallBackFunc != NULL);
+ Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+ InstancePtr->StatusHandler = (XDcfg_IntrHandler) CallBackFunc;
+ InstancePtr->CallBackRef = CallBackRef;
+}
+/** @} */
diff --git a/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/devcfg_v3_5/src/xdevcfg_selftest.c b/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/devcfg_v3_5/src/xdevcfg_selftest.c
new file mode 100644
index 0000000..d01a504
--- /dev/null
+++ b/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/devcfg_v3_5/src/xdevcfg_selftest.c
@@ -0,0 +1,108 @@
+/******************************************************************************
+*
+* Copyright (C) 2010 - 2015 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+* THE SOFTWARE.
+*
+*
+*
+******************************************************************************/
+/****************************************************************************/
+/**
+*
+* @file xdevcfg_selftest.c
+* @addtogroup devcfg_v3_5
+* @{
+*
+* Contains diagnostic self-test functions for the XDcfg driver.
+*
+* <pre>
+* MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ----- --- -------- ---------------------------------------------
+* 1.00a hvm 02/07/11 First release
+* 2.02a nm 02/27/13 Fixed CR# 701348.
+* Peripheral test fails with Running
+* DcfgSelfTestExample() in SECURE bootmode.
+* </pre>
+*
+******************************************************************************/
+
+/***************************** Include Files *********************************/
+
+#include "xdevcfg.h"
+
+/************************** Constant Definitions *****************************/
+
+/**************************** Type Definitions *******************************/
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/************************** Function Prototypes ******************************/
+
+/************************** Variable Definitions *****************************/
+
+/****************************************************************************/
+/**
+*
+* Run a self-test on the Device Configuration Interface. This test does a
+* control register write and reads back the same value.
+*
+* @param InstancePtr is a pointer to the XDcfg instance.
+*
+* @return
+* - XST_SUCCESS if self-test was successful.
+* - XST_FAILURE if fails.
+*
+* @note None.
+*
+******************************************************************************/
+int XDcfg_SelfTest(XDcfg *InstancePtr)
+{
+ u32 OldCfgReg;
+ u32 CfgReg;
+ int Status = XST_SUCCESS;
+
+ /*
+ * Assert to ensure the inputs are valid and the instance has been
+ * initialized.
+ */
+ Xil_AssertNonvoid(InstancePtr != NULL);
+ Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+ OldCfgReg = XDcfg_GetControlRegister(InstancePtr);
+
+ XDcfg_SetControlRegister(InstancePtr, XDCFG_CTRL_NIDEN_MASK);
+
+ CfgReg = XDcfg_GetControlRegister(InstancePtr);
+
+ if ((CfgReg & XDCFG_CTRL_NIDEN_MASK) != XDCFG_CTRL_NIDEN_MASK) {
+
+ Status = XST_FAILURE;
+ }
+
+ /*
+ * Restore the original values of the register
+ */
+ XDcfg_SetControlRegister(InstancePtr, OldCfgReg);
+
+ return Status;
+}
+/** @} */
diff --git a/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/devcfg_v3_5/src/xdevcfg_sinit.c b/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/devcfg_v3_5/src/xdevcfg_sinit.c
new file mode 100644
index 0000000..175afa4
--- /dev/null
+++ b/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/devcfg_v3_5/src/xdevcfg_sinit.c
@@ -0,0 +1,88 @@
+/******************************************************************************
+*
+* Copyright (C) 2010 - 2017 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+* THE SOFTWARE.
+*
+*
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xdevcfg_sinit.c
+* @addtogroup devcfg_v3_5
+* @{
+*
+* This file contains method for static initialization (compile-time) of the
+* driver.
+*
+* <pre>
+* MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ----- --- -------- ---------------------------------------------
+* 1.00a hvm 02/07/11 First release
+* 3.5 ms 08/07/17 Fixed compilation warnings.
+* </pre>
+*
+******************************************************************************/
+
+/***************************** Include Files *********************************/
+
+#include "xdevcfg.h"
+#include "xparameters.h"
+
+/************************** Constant Definitions *****************************/
+
+/**************************** Type Definitions *******************************/
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/************************** Function Prototypes ******************************/
+
+/*****************************************************************************/
+/**
+* Lookup the device configuration based on the unique device ID. The table
+* contains the configuration info for each device in the system.
+*
+* @param DeviceId is the unique device ID of the device being looked up.
+*
+* @return A pointer to the configuration table entry corresponding to the
+* given device ID, or NULL if no match is found.
+*
+* @note None.
+*
+******************************************************************************/
+XDcfg_Config *XDcfg_LookupConfig(u16 DeviceId)
+{
+ extern XDcfg_Config XDcfg_ConfigTable[];
+ XDcfg_Config *CfgPtr = NULL;
+ u32 Index;
+
+ for (Index = 0U; Index < XPAR_XDCFG_NUM_INSTANCES; Index++) {
+ if (XDcfg_ConfigTable[Index].DeviceId == DeviceId) {
+ CfgPtr = &XDcfg_ConfigTable[Index];
+ break;
+ }
+ }
+
+ return (CfgPtr);
+}
+/** @} */
diff --git a/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/dmaps_v2_5/src/Makefile b/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/dmaps_v2_5/src/Makefile
new file mode 100644
index 0000000..d1240c5
--- /dev/null
+++ b/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/dmaps_v2_5/src/Makefile
@@ -0,0 +1,41 @@
+COMPILER=
+ARCHIVER=
+CP=cp
+COMPILER_FLAGS=
+EXTRA_COMPILER_FLAGS=
+LIB=libxil.a
+
+CC_FLAGS = $(COMPILER_FLAGS)
+ECC_FLAGS = $(EXTRA_COMPILER_FLAGS)
+
+RELEASEDIR=../../../lib
+INCLUDEDIR=../../../include
+INCLUDES=-I./. -I${INCLUDEDIR}
+
+OUTS = *.o
+
+LIBSOURCES:=*.c
+INCLUDEFILES:=*.h
+
+OBJECTS = $(addsuffix .o, $(basename $(wildcard *.c)))
+
+libs: banner xdmaps_libs clean
+
+%.o: %.c
+ ${COMPILER} $(CC_FLAGS) $(ECC_FLAGS) $(INCLUDES) -o $@ $<
+
+banner:
+ echo "Compiling dmaps"
+
+xdmaps_libs: ${OBJECTS}
+ $(ARCHIVER) -r ${RELEASEDIR}/${LIB} ${OBJECTS}
+
+.PHONY: include
+include: xdmaps_includes
+
+xdmaps_includes:
+ ${CP} ${INCLUDEFILES} ${INCLUDEDIR}
+
+clean:
+ rm -rf ${OBJECTS}
+
diff --git a/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/dmaps_v2_5/src/xdmaps.c b/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/dmaps_v2_5/src/xdmaps.c
new file mode 100644
index 0000000..fb273d0
--- /dev/null
+++ b/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/dmaps_v2_5/src/xdmaps.c
@@ -0,0 +1,1979 @@
+/******************************************************************************
+*
+* Copyright (C) 2009 - 2019 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+* THE SOFTWARE.
+*
+*
+*
+******************************************************************************/
+/****************************************************************************/
+/**
+*
+* @file xdmaps.c
+* @addtogroup dmaps_v2_5
+* @{
+*
+* This file contains the implementation of the interface functions for XDmaPs
+* driver. Refer to the header file xdmaps.h for more detailed information.
+*
+* <pre>
+* MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ----- ------ -------- ----------------------------------------------
+* 1.00 hbm 08/19/2010 First Release
+* 1.00 nm 05/25/2011 Updated for minor doxygen corrections
+* 1.02a sg 05/16/2012 Made changes for doxygen and moved some function
+* header from the xdmaps.h file to xdmaps.c file
+* Other cleanup for coding guidelines and CR 657109
+* and CR 657898
+* 1.03a sg 07/16/2012 changed inline to __inline for CR665681
+* 1.04a nm 10/22/2012 Fixed CR# 681671.
+* 1.05a nm 04/15/2013 Fixed CR# 704396. Removed warnings when compiled
+* with -Wall and -Wextra option in bsp.
+* 05/01/2013 Fixed CR# 700189. Changed XDmaPs_BuildDmaProg()
+* function description.
+* Fixed CR# 704396. Removed unused variables
+* UseM2MByte & MemBurstLen from XDmaPs_BuildDmaProg()
+* function.
+* 1.07a asa 11/02/13. Made changes to fix compilation issues for iarcc.
+* Removed the PDBG prints. By default they were always
+* defined out and never used. The PDBG is non-standard for
+* Xilinx drivers and no other driver does something similar.
+* Since there is no easy way to fix compilation issues with
+* the IARCC compiler around PDBG, it is better to remove it.
+* Users can always use xil_printfs if they want to debug.
+* 2.01 kpc 08/23/14 Fixed the IAR compiler reported errors
+* 2.2 mus 12/08/16 Remove definition of INLINE macro to avoid re-definition,
+* since it is being defined in xil_io.h
+* 2.3 kpc 14/10/16 Fixed the compiler error when optimization O0 is used.
+* 2.5 hk 08/16/19 Add a memory barrier before DMASEV as per specification.
+* </pre>
+*
+*****************************************************************************/
+
+/***************************** Include Files ********************************/
+
+#include <string.h>
+
+#include "xstatus.h"
+#include "xdmaps.h"
+#include "xil_io.h"
+#include "xil_cache.h"
+
+#include "xil_printf.h"
+
+
+/************************** Constant Definitions ****************************/
+
+/* The following constant defines the amount of error that is allowed for
+ * a specified baud rate. This error is the difference between the actual
+ * baud rate that will be generated using the specified clock and the
+ * desired baud rate.
+ */
+
+/**************************** Type Definitions ******************************/
+
+/***************** Macros (Inline Functions) Definitions ********************/
+
+
+/************************** Function Prototypes *****************************/
+static int XDmaPs_Exec_DMAKILL(u32 BaseAddr,
+ unsigned int Channel,
+ unsigned int Thread);
+
+static void XDmaPs_BufPool_Free(XDmaPs_ProgBuf *Pool, void *Buf);
+
+static int XDmaPs_Exec_DMAGO(u32 BaseAddr, unsigned int Channel, u32 DmaProg);
+
+static void XDmaPs_DoneISR_n(XDmaPs *InstPtr, unsigned Channel);
+static void *XDmaPs_BufPool_Allocate(XDmaPs_ProgBuf *Pool);
+static int XDmaPs_BuildDmaProg(unsigned Channel, XDmaPs_Cmd *Cmd,
+ unsigned CacheLength);
+
+static void XDmaPs_Print_DmaProgBuf(char *Buf, int Length);
+
+
+
+/************************** Variable Definitions ****************************/
+
+/****************************************************************************/
+/**
+*
+* Initializes a specific XDmaPs instance such that it is ready to be used.
+* The data format of the device is setup for 8 data bits, 1 stop bit, and no
+* parity by default. The baud rate is set to a default value specified by
+* Config->DefaultBaudRate if set, otherwise it is set to 19.2K baud. The
+* receive FIFO threshold is set for 8 bytes. The default operating mode of the
+* driver is polled mode.
+*
+* @param InstPtr is a pointer to the XDmaPs instance.
+* @param Config is a reference to a structure containing information
+* about a specific XDmaPs driver.
+* @param EffectiveAddr is the device base address in the virtual memory
+* address space. The caller is responsible for keeping the
+* address mapping from EffectiveAddr to the device physical base
+* address unchanged once this function is invoked. Unexpected
+* errors may occur if the address mapping changes after this
+* function is called. If address translation is not used, pass in
+* the physical address instead.
+*
+* @return
+*
+* - XST_SUCCESS on initialization completion
+*
+* @note None.
+*
+*****************************************************************************/
+int XDmaPs_CfgInitialize(XDmaPs *InstPtr,
+ XDmaPs_Config *Config,
+ u32 EffectiveAddr)
+{
+ int Status = XST_SUCCESS;
+ unsigned int CacheLength = 0;
+ u32 CfgReg;
+ unsigned Channel;
+ XDmaPs_ChannelData *ChanData;
+
+ /*
+ * Assert validates the input arguments
+ */
+ Xil_AssertNonvoid(InstPtr != NULL);
+ Xil_AssertNonvoid(Config != NULL);
+
+ /*
+ * Setup the driver instance using passed in parameters
+ */
+ InstPtr->Config.DeviceId = Config->DeviceId;
+ InstPtr->Config.BaseAddress = EffectiveAddr;
+
+ CfgReg = XDmaPs_ReadReg(EffectiveAddr, XDMAPS_CR1_OFFSET);
+ CacheLength = CfgReg & XDMAPS_CR1_I_CACHE_LEN_MASK;
+ if (CacheLength < 2 || CacheLength > 5)
+ CacheLength = 0;
+ else
+ CacheLength = 1 << CacheLength;
+
+ InstPtr->CacheLength = CacheLength;
+
+ memset(InstPtr->Chans, 0,
+ sizeof(XDmaPs_ChannelData[XDMAPS_CHANNELS_PER_DEV]));
+
+ for (Channel = 0; Channel < XDMAPS_CHANNELS_PER_DEV; Channel++) {
+ ChanData = InstPtr->Chans + Channel;
+ ChanData->ChanId = Channel;
+ ChanData->DevId = Config->DeviceId;
+ }
+
+ InstPtr->IsReady = 1;
+
+ return Status;
+}
+
+/****************************************************************************/
+/**
+*
+* Reset the DMA Manager.
+*
+* @param InstPtr is the DMA instance.
+*
+* @return 0 on success, -1 on time out
+*
+* @note None.
+*
+*****************************************************************************/
+int XDmaPs_ResetManager(XDmaPs *InstPtr)
+{
+ int Status;
+ Status = XDmaPs_Exec_DMAKILL(InstPtr->Config.BaseAddress,
+ 0, 0);
+
+ return Status;
+}
+
+/****************************************************************************/
+/**
+*
+* Reset the specified DMA Channel.
+*
+* @param InstPtr is the DMA instance.
+* @param Channel is the channel to be reset.
+*
+* @return 0 on success, -1 on time out
+*
+* @note None.
+*
+*****************************************************************************/
+int XDmaPs_ResetChannel(XDmaPs *InstPtr, unsigned int Channel)
+{
+ int Status;
+ Status = XDmaPs_Exec_DMAKILL(InstPtr->Config.BaseAddress,
+ Channel, 1);
+
+ return Status;
+
+}
+
+/*****************************************************************************/
+/**
+*
+* Driver fault interrupt service routine
+* This is the one that connects the GIC
+*
+* @param InstPtr is the DMA instance.
+*
+* @return None.
+*
+* @note None.
+*
+******************************************************************************/
+void XDmaPs_FaultISR(XDmaPs *InstPtr)
+{
+
+ void *DmaProgBuf;
+ u32 Fsm; /* Fault status DMA manager register value */
+ u32 Fsc; /* Fault status DMA channel register value */
+ u32 FaultType; /* Fault type DMA manager register value */
+
+ u32 BaseAddr = InstPtr->Config.BaseAddress;
+
+ u32 Pc; /* DMA Pc or channel Pc */
+ XDmaPs_ChannelData *ChanData;
+
+ unsigned Chan;
+ unsigned DevId;
+
+ XDmaPs_Cmd *DmaCmd;
+
+ Fsm = XDmaPs_ReadReg(BaseAddr, XDMAPS_FSM_OFFSET) & 0x01;
+ Fsc = XDmaPs_ReadReg(BaseAddr, XDMAPS_FSC_OFFSET) & 0xFF;
+
+
+ DevId = InstPtr->Config.DeviceId;
+
+ if (Fsm) {
+ /*
+ * if DMA manager is fault
+ */
+ FaultType = XDmaPs_ReadReg(BaseAddr, XDMAPS_FTM_OFFSET);
+ Pc = XDmaPs_ReadReg(BaseAddr, XDMAPS_DPC_OFFSET);
+
+ xil_printf("PL330 device %d fault with type: %x at Pc %x\n",
+ DevId,
+ FaultType, Pc);
+
+ /* kill the DMA manager thread */
+ /* Should we disable interrupt?*/
+ XDmaPs_Exec_DMAKILL(BaseAddr, 0, 0);
+ }
+
+ /*
+ * check which channel faults and kill the channel thread
+ */
+ for (Chan = 0;
+ Chan < XDMAPS_CHANNELS_PER_DEV;
+ Chan++) {
+ if (Fsc & (0x01 << Chan)) {
+ FaultType =
+ XDmaPs_ReadReg(BaseAddr,
+ XDmaPs_FTCn_OFFSET(Chan));
+ Pc = XDmaPs_ReadReg(BaseAddr,
+ XDmaPs_CPCn_OFFSET(Chan));
+
+ /* kill the channel thread */
+ /* Should we disable interrupt? */
+ XDmaPs_Exec_DMAKILL(BaseAddr, Chan, 1);
+
+ /*
+ * get the fault type and fault Pc and invoke the
+ * fault callback.
+ */
+ ChanData = InstPtr->Chans + Chan;
+
+ DmaCmd = ChanData->DmaCmdToHw;
+
+ /* Should we check DmaCmd is not null */
+ DmaCmd->DmaStatus = -1;
+ DmaCmd->ChanFaultType = FaultType;
+ DmaCmd->ChanFaultPCAddr = Pc;
+ ChanData->DmaCmdFromHw = DmaCmd;
+ ChanData->DmaCmdToHw = NULL;
+
+ if (!ChanData->HoldDmaProg) {
+ DmaProgBuf = (void *)DmaCmd->GeneratedDmaProg;
+ if (DmaProgBuf)
+ XDmaPs_BufPool_Free(ChanData->ProgBufPool,
+ DmaProgBuf);
+ DmaCmd->GeneratedDmaProg = NULL;
+ }
+
+ if (InstPtr->FaultHandler)
+ InstPtr->FaultHandler(Chan,
+ DmaCmd,
+ InstPtr->FaultRef);
+
+ }
+ }
+
+}
+
+/*****************************************************************************/
+/**
+*
+* Set the done handler for a channel.
+*
+* @param InstPtr is the DMA instance.
+* @param Channel is the channel number.
+* @param DoneHandler is the done interrupt handler.
+* @param CallbackRef is the callback reference data.
+*
+* @return None.
+*
+* @note None.
+*
+******************************************************************************/
+int XDmaPs_SetDoneHandler(XDmaPs *InstPtr,
+ unsigned Channel,
+ XDmaPsDoneHandler DoneHandler,
+ void *CallbackRef)
+{
+ XDmaPs_ChannelData *ChanData;
+
+ Xil_AssertNonvoid(InstPtr != NULL);
+
+ if (Channel >= XDMAPS_CHANNELS_PER_DEV)
+ return XST_FAILURE;
+
+
+ ChanData = InstPtr->Chans + Channel;
+
+ ChanData->DoneHandler = DoneHandler;
+ ChanData->DoneRef = CallbackRef;
+
+ return 0;
+}
+
+/*****************************************************************************/
+/**
+*
+* Set the fault handler for a channel.
+*
+* @param InstPtr is the DMA instance.
+* @param FaultHandler is the fault interrupt handler.
+* @param CallbackRef is the callback reference data.
+*
+* @return None.
+*
+* @note None.
+*
+******************************************************************************/
+int XDmaPs_SetFaultHandler(XDmaPs *InstPtr,
+ XDmaPsFaultHandler FaultHandler,
+ void *CallbackRef)
+{
+ Xil_AssertNonvoid(InstPtr != NULL);
+
+ InstPtr->FaultHandler = FaultHandler;
+ InstPtr->FaultRef = CallbackRef;
+
+ return XST_SUCCESS;
+}
+
+
+
+/****************************************************************************/
+/**
+* Construction function for DMAEND instruction. This function fills the program
+* buffer with the constructed instruction.
+*
+* @param DmaProg the DMA program buffer, it's the starting address for
+* the instruction being constructed
+*
+* @return The number of bytes for this instruction which is 1.
+*
+* @note None.
+*
+*****************************************************************************/
+static INLINE int XDmaPs_Instr_DMAEND(char *DmaProg)
+{
+ /*
+ * DMAEND encoding:
+ * 7 6 5 4 3 2 1 0
+ * 0 0 0 0 0 0 0 0
+ */
+ *DmaProg = 0x0;
+
+ return 1;
+}
+
+static INLINE void XDmaPs_Memcpy4(char *Dst, char *Src)
+{
+ *Dst = *Src;
+ *(Dst + 1) = *(Src + 1);
+ *(Dst + 2) = *(Src + 2);
+ *(Dst + 3) = *(Src + 3);
+}
+
+/****************************************************************************/
+/**
+*
+* Construction function for DMAGO instruction. This function fills the program
+* buffer with the constructed instruction.
+*
+* @param DmaProg is the DMA program buffer, it's the starting address
+* for the instruction being constructed
+* @param Cn is the Channel number, 0 - 7
+* @param Imm is 32-bit immediate number written to the Channel Program
+* Counter.
+* @param Ns is Non-secure flag. If Ns is 1, the DMA channel operates in
+* the Non-secure state. If Ns is 0, the execution depends on the
+* security state of the DMA manager:
+* DMA manager is in the Secure state, DMA channel operates in the
+* Secure state.
+* DMA manager is in the Non-secure state, DMAC aborts.
+*
+* @return The number of bytes for this instruction which is 6.
+*
+* @note None
+*
+*****************************************************************************/
+static INLINE int XDmaPs_Instr_DMAGO(char *DmaProg, unsigned int Cn,
+ u32 Imm, unsigned int Ns)
+{
+ /*
+ * DMAGO encoding:
+ * 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00
+ * 0 0 0 0 0 |cn[2:0]| 1 0 1 0 0 0 ns 0
+ *
+ * 47 ... 16
+ * imm[32:0]
+ */
+ *DmaProg = 0xA0 | ((Ns << 1) & 0x02);
+
+ *(DmaProg + 1) = (u8)(Cn & 0x07);
+
+ // *((u32 *)(DmaProg + 2)) = Imm;
+ XDmaPs_Memcpy4(DmaProg + 2, (char *)&Imm);
+
+ /* success */
+ return 6;
+}
+
+/****************************************************************************/
+/**
+*
+* Construction function for DMALD instruction. This function fills the program
+* buffer with the constructed instruction.
+*
+* @param DmaProg the DMA program buffer, it's the starting address for the
+* instruction being constructed
+*
+* @return The number of bytes for this instruction which is 1.
+*
+* @note None.
+*
+*****************************************************************************/
+static INLINE int XDmaPs_Instr_DMALD(char *DmaProg)
+{
+ /*
+ * DMALD encoding
+ * 7 6 5 4 3 2 1 0
+ * 0 0 0 0 0 1 bs x
+ *
+ * Note: this driver doesn't support conditional load or store,
+ * so the bs bit is 0 and x bit is 0.
+ */
+ *DmaProg = 0x04;
+ return 1;
+}
+
+/****************************************************************************/
+/**
+*
+* Construction function for DMALP instruction. This function fills the program
+* buffer with the constructed instruction.
+*
+* @param DmaProg is the DMA program buffer, it's the starting address
+* for the instruction being constructed
+* @param Lc is the Loop counter register, can either be 0 or 1.
+* @param LoopIterations: the number of interations, LoopInterations - 1
+* will be encoded in the DMALP instruction.
+*
+* @return The number of bytes for this instruction which is 2.
+*
+* @note None.
+*
+*****************************************************************************/
+static INLINE int XDmaPs_Instr_DMALP(char *DmaProg, unsigned Lc,
+ unsigned LoopIterations)
+{
+ /*
+ * DMALP encoding
+ * 15 ... 8 7 6 5 4 3 2 1 0
+ * | iter[7:0] |0 0 1 0 0 0 lc 0
+ */
+ *DmaProg = (u8)(0x20 | ((Lc & 1) << 1));
+ *(DmaProg + 1) = (u8)(LoopIterations - 1);
+ return 2;
+}
+
+/****************************************************************************/
+/**
+*
+* Construction function for DMALPEND instruction. This function fills the
+* program buffer with the constructed instruction.
+*
+* @param DmaProg is the DMA program buffer, it's the starting address
+* for the instruction being constructed
+* @param BodyStart is the starting address of the loop body. It is used
+* to calculate the bytes of backward jump.
+* @param Lc is the Loop counter register, can either be 0 or 1.
+*
+* @return The number of bytes for this instruction which is 2.
+*
+* @note None.
+*
+*****************************************************************************/
+static INLINE int XDmaPs_Instr_DMALPEND(char *DmaProg, char *BodyStart, unsigned Lc)
+{
+ /*
+ * DMALPEND encoding
+ * 15 ... 8 7 6 5 4 3 2 1 0
+ * | backward_jump[7:0] |0 0 1 nf 1 lc bs x
+ *
+ * lc: loop counter
+ * nf is for loop forever. The driver does not support loop forever,
+ * so nf is 1.
+ * The driver does not support conditional LPEND, so bs is 0, x is 0.
+ */
+ *DmaProg = 0x38 | ((Lc & 1) << 2);
+ *(DmaProg + 1) = (u8)(DmaProg - BodyStart);
+
+ return 2;
+}
+
+/*
+ * Register number for the DMAMOV instruction
+ */
+#define XDMAPS_MOV_SAR 0x0
+#define XDMAPS_MOV_CCR 0x1
+#define XDMAPS_MOV_DAR 0x2
+
+/****************************************************************************/
+/**
+*
+* Construction function for DMAMOV instruction. This function fills the
+* program buffer with the constructed instruction.
+*
+* @param DmaProg is the DMA program buffer, it's the starting address
+* for the instruction being constructed
+* @param Rd is the register id, 0 for SAR, 1 for CCR, and 2 for DAR
+* @param Imm is the 32-bit immediate number
+*
+* @return The number of bytes for this instruction which is 6.
+*
+* @note None.
+*
+*****************************************************************************/
+static INLINE int XDmaPs_Instr_DMAMOV(char *DmaProg, unsigned Rd, u32 Imm)
+{
+ /*
+ * DMAMOV encoding
+ * 15 4 3 2 1 10 ... 8 7 6 5 4 3 2 1 0
+ * 0 0 0 0 0 |rd[2:0]|1 0 1 1 1 1 0 0
+ *
+ * 47 ... 16
+ * imm[32:0]
+ *
+ * rd: b000 for SAR, b001 CCR, b010 DAR
+ */
+ *DmaProg = 0xBC;
+ *(DmaProg + 1) = Rd & 0x7;
+ // *((u32 *)(DmaProg + 2)) = Imm;
+ XDmaPs_Memcpy4(DmaProg + 2, (char *)&Imm);
+
+ return 6;
+}
+
+/****************************************************************************/
+/**
+*
+* Construction function for DMANOP instruction. This function fills the
+* program buffer with the constructed instruction.
+*
+* @param DmaProg is the DMA program buffer, it's the starting address
+* for the instruction being constructed
+* @return The number of bytes for this instruction which is 1.
+*
+* @note None.
+*
+*****************************************************************************/
+static INLINE int XDmaPs_Instr_DMANOP(char *DmaProg)
+{
+ /*
+ * DMANOP encoding
+ * 7 6 5 4 3 2 1 0
+ * 0 0 0 1 1 0 0 0
+ */
+ *DmaProg = 0x18;
+ return 1;
+}
+
+/****************************************************************************/
+/**
+*
+* Construction function for DMARMB instruction. This function fills the
+* program buffer with the constructed instruction.
+*
+* @param DmaProg is the DMA program buffer, it's the starting address
+* for the instruction being constructed
+*
+* @return The number of bytes for this instruction which is 1.
+*
+* @note None.
+*
+*****************************************************************************/
+int XDmaPs_Instr_DMARMB(char *DmaProg)
+{
+ /*
+ * DMARMB encoding
+ * 7 6 5 4 3 2 1 0
+ * 0 0 0 1 0 0 1 0
+ */
+ *DmaProg = 0x12;
+ return 1;
+}
+
+/****************************************************************************/
+/**
+*
+* Construction function for DMASEV instruction. This function fills the
+* program buffer with the constructed instruction.
+*
+* @param DmaProg is the DMA program buffer, it's the starting address
+* for the instruction being constructed
+* @param EventNumber is the Event number to signal.
+*
+* @return The number of bytes for this instruction which is 2.
+*
+* @note None.
+*
+*****************************************************************************/
+static INLINE int XDmaPs_Instr_DMASEV(char *DmaProg, unsigned int EventNumber)
+{
+ /*
+ * DMASEV encoding
+ * 15 4 3 2 1 10 9 8 7 6 5 4 3 2 1 0
+ * |event[4:0]| 0 0 0 0 0 1 1 0 1 0 0
+ */
+ *DmaProg = 0x34;
+ *(DmaProg + 1) = (u8)(EventNumber << 3);
+
+ return 2;
+}
+
+
+/****************************************************************************/
+/**
+*
+* Construction function for DMAST instruction. This function fills the
+* program buffer with the constructed instruction.
+*
+* @param DmaProg is the DMA program buffer, it's the starting address
+* for the instruction being constructed
+*
+* @return The number of bytes for this instruction which is 1.
+*
+* @note None.
+*
+*****************************************************************************/
+static INLINE int XDmaPs_Instr_DMAST(char *DmaProg)
+{
+ /*
+ * DMAST encoding
+ * 7 6 5 4 3 2 1 0
+ * 0 0 0 0 1 0 bs x
+ *
+ * Note: this driver doesn't support conditional load or store,
+ * so the bs bit is 0 and x bit is 0.
+ */
+ *DmaProg = 0x08;
+ return 1;
+}
+
+
+/****************************************************************************/
+/**
+*
+* Construction function for DMAWMB instruction. This function fills the
+* program buffer with the constructed instruction.
+*
+* @param DmaProg is the DMA program buffer, it's the starting address
+* for the instruction being constructed
+*
+* @return The number of bytes for this instruction which is 1.
+*
+* @note None.
+*
+*****************************************************************************/
+int XDmaPs_Instr_DMAWMB(char *DmaProg)
+{
+ /*
+ * DMAWMB encoding
+ * 7 6 5 4 3 2 1 0
+ * 0 0 0 1 0 0 1 0
+ */
+ *DmaProg = 0x13;
+ return 1;
+}
+
+/****************************************************************************/
+/**
+*
+* Conversion function from the endian swap size to the bit encoding of the CCR
+*
+* @param EndianSwapSize is the endian swap size, in terms of bits, it
+* could be 8, 16, 32, 64, or 128(We are using DMA assembly syntax)
+*
+* @return The endian swap size bit encoding for the CCR.
+*
+* @note None.
+*
+*****************************************************************************/
+static INLINE unsigned XDmaPs_ToEndianSwapSizeBits(unsigned int EndianSwapSize)
+{
+ switch (EndianSwapSize) {
+ case 0:
+ case 8:
+ return 0;
+ case 16:
+ return 1;
+ case 32:
+ return 2;
+ case 64:
+ return 3;
+ case 128:
+ return 4;
+ default:
+ return 0;
+ }
+
+}
+
+/****************************************************************************/
+/**
+*
+* Conversion function from the burst size to the bit encoding of the CCR
+*
+* @param BurstSize is the burst size. It's the data width.
+* In terms of bytes, it could be 1, 2, 4, 8, 16, 32, 64, or 128.
+* It must be no larger than the bus width.
+* (We are using DMA assembly syntax.)
+*
+* @note None.
+*
+*****************************************************************************/
+static INLINE unsigned XDmaPs_ToBurstSizeBits(unsigned BurstSize)
+{
+ switch (BurstSize) {
+ case 1:
+ return 0;
+ case 2:
+ return 1;
+ case 4:
+ return 2;
+ case 8:
+ return 3;
+ case 16:
+ return 4;
+ case 32:
+ return 5;
+ case 64:
+ return 6;
+ case 128:
+ return 7;
+ default:
+ return 0;
+ }
+}
+
+
+/****************************************************************************/
+/**
+*
+* Conversion function from PL330 bus transfer descriptors to CCR value. All the
+* values passed to the functions are in terms of assembly languages, not in
+* terms of the register bit encoding.
+*
+* @param ChanCtrl is the Instance of XDmaPs_ChanCtrl.
+*
+* @return The 32-bit CCR value.
+*
+* @note None.
+*
+*****************************************************************************/
+u32 XDmaPs_ToCCRValue(XDmaPs_ChanCtrl *ChanCtrl)
+{
+ /*
+ * Channel Control Register encoding
+ * [31:28] - endian_swap_size
+ * [27:25] - dst_cache_ctrl
+ * [24:22] - dst_prot_ctrl
+ * [21:18] - dst_burst_len
+ * [17:15] - dst_burst_size
+ * [14] - dst_inc
+ * [13:11] - src_cache_ctrl
+ * [10:8] - src_prot_ctrl
+ * [7:4] - src_burst_len
+ * [3:1] - src_burst_size
+ * [0] - src_inc
+ */
+
+ unsigned es =
+ XDmaPs_ToEndianSwapSizeBits(ChanCtrl->EndianSwapSize);
+
+ unsigned dst_burst_size =
+ XDmaPs_ToBurstSizeBits(ChanCtrl->DstBurstSize);
+ unsigned dst_burst_len = (ChanCtrl->DstBurstLen - 1) & 0x0F;
+ unsigned dst_cache_ctrl = (ChanCtrl->DstCacheCtrl & 0x03)
+ | ((ChanCtrl->DstCacheCtrl & 0x08) >> 1);
+ unsigned dst_prot_ctrl = ChanCtrl->DstProtCtrl & 0x07;
+ unsigned dst_inc_bit = ChanCtrl->DstInc & 1;
+
+ unsigned src_burst_size =
+ XDmaPs_ToBurstSizeBits(ChanCtrl->SrcBurstSize);
+ unsigned src_burst_len = (ChanCtrl->SrcBurstLen - 1) & 0x0F;
+ unsigned src_cache_ctrl = (ChanCtrl->SrcCacheCtrl & 0x03)
+ | ((ChanCtrl->SrcCacheCtrl & 0x08) >> 1);
+ unsigned src_prot_ctrl = ChanCtrl->SrcProtCtrl & 0x07;
+ unsigned src_inc_bit = ChanCtrl->SrcInc & 1;
+
+ u32 ccr_value = (es << 28)
+ | (dst_cache_ctrl << 25)
+ | (dst_prot_ctrl << 22)
+ | (dst_burst_len << 18)
+ | (dst_burst_size << 15)
+ | (dst_inc_bit << 14)
+ | (src_cache_ctrl << 11)
+ | (src_prot_ctrl << 8)
+ | (src_burst_len << 4)
+ | (src_burst_size << 1)
+ | (src_inc_bit);
+
+ return ccr_value;
+}
+
+/****************************************************************************/
+/**
+* Construct a loop with only DMALD and DMAST as the body using loop counter 0.
+* The function also makes sure the loop body and the lpend is in the same
+* cache line.
+*
+* @param DmaProgStart is the very start address of the DMA program.
+* This is used to calculate whether the loop is in a cache line.
+* @param CacheLength is the icache line length, in terms of bytes.
+* If it's zero, the performance enhancement feature will be
+* turned off.
+* @param DmaProgLoopStart The starting address of the loop (DMALP).
+* @param LoopCount The inner loop count. Loop count - 1 will be used to
+* initialize the loop counter.
+*
+* @return The number of bytes the loop has.
+*
+* @note None.
+*
+*****************************************************************************/
+int XDmaPs_ConstructSingleLoop(char *DmaProgStart,
+ int CacheLength,
+ char *DmaProgLoopStart,
+ int LoopCount)
+{
+ int CacheStartOffset;
+ int CacheEndOffset;
+ int NumNops;
+ char *DmaProgBuf = DmaProgLoopStart;
+
+ DmaProgBuf += XDmaPs_Instr_DMALP(DmaProgBuf, 0, LoopCount);
+
+ if (CacheLength > 0) {
+ /*
+ * the CacheLength > 0 switch is ued to turn on/off nop
+ * insertion
+ */
+ CacheStartOffset = DmaProgBuf - DmaProgStart;
+ CacheEndOffset = CacheStartOffset + 3;
+
+ /*
+ * check whether the body and lpend fit in one cache line
+ */
+ if (CacheStartOffset / CacheLength
+ != CacheEndOffset / CacheLength) {
+ /* insert the nops */
+ NumNops = CacheLength
+ - CacheStartOffset % CacheLength;
+ while (NumNops--) {
+ DmaProgBuf +=
+ XDmaPs_Instr_DMANOP(DmaProgBuf);
+ }
+ }
+ }
+
+ DmaProgBuf += XDmaPs_Instr_DMALD(DmaProgBuf);
+ DmaProgBuf += XDmaPs_Instr_DMAST(DmaProgBuf);
+ DmaProgBuf += XDmaPs_Instr_DMALPEND(DmaProgBuf,
+ DmaProgBuf - 2, 0);
+
+ return DmaProgBuf - DmaProgLoopStart;
+}
+
+/****************************************************************************/
+/**
+* Construct a nested loop with only DMALD and DMAST in the inner loop body.
+* It uses loop counter 1 for the outer loop and loop counter 0 for the
+* inner loop.
+*
+* @param DmaProgStart is the very start address of the DMA program.
+* This is used to calculate whether the loop is in a cache line.
+* @param CacheLength is the icache line length, in terms of bytes.
+* If it's zero, the performance enhancement feature will be
+* turned off.
+* @param DmaProgLoopStart The starting address of the loop (DMALP).
+* @param LoopCountOuter The outer loop count. Loop count - 1 will be
+* used to initialize the loop counter.
+* @param LoopCountInner The inner loop count. Loop count - 1 will be
+* used to initialize the loop counter.
+*
+* @return The number byes the nested loop program has.
+*
+* @note None.
+*
+*****************************************************************************/
+int XDmaPs_ConstructNestedLoop(char *DmaProgStart,
+ int CacheLength,
+ char *DmaProgLoopStart,
+ unsigned int LoopCountOuter,
+ unsigned int LoopCountInner)
+{
+ int CacheStartOffset;
+ int CacheEndOffset;
+ int NumNops;
+ char *InnerLoopStart;
+ char *DmaProgBuf = DmaProgLoopStart;
+
+ DmaProgBuf += XDmaPs_Instr_DMALP(DmaProgBuf, 1, LoopCountOuter);
+ InnerLoopStart = DmaProgBuf;
+
+ if (CacheLength > 0) {
+ /*
+ * the CacheLength > 0 switch is ued to turn on/off nop
+ * insertion
+ */
+ if (CacheLength < 8) {
+ /*
+ * if the cache line is too small to fit both loops
+ * just align the inner loop
+ */
+ DmaProgBuf +=
+ XDmaPs_ConstructSingleLoop(DmaProgStart,
+ CacheLength,
+ DmaProgBuf,
+ LoopCountInner);
+ /* outer loop end */
+ DmaProgBuf +=
+ XDmaPs_Instr_DMALPEND(DmaProgBuf,
+ InnerLoopStart,
+ 1);
+
+ /*
+ * the nested loop is constructed for
+ * smaller cache line
+ */
+ return DmaProgBuf - DmaProgLoopStart;
+ }
+
+ /*
+ * Now let's handle the case where a cache line can
+ * fit the nested loops.
+ */
+ CacheStartOffset = DmaProgBuf - DmaProgStart;
+ CacheEndOffset = CacheStartOffset + 7;
+
+ /*
+ * check whether the body and lpend fit in one cache line
+ */
+ if (CacheStartOffset / CacheLength
+ != CacheEndOffset / CacheLength) {
+ /* insert the nops */
+ NumNops = CacheLength
+ - CacheStartOffset % CacheLength;
+ while (NumNops--) {
+ DmaProgBuf +=
+ XDmaPs_Instr_DMANOP(DmaProgBuf);
+ }
+ }
+ }
+
+ /* insert the inner DMALP */
+ DmaProgBuf += XDmaPs_Instr_DMALP(DmaProgBuf, 0, LoopCountInner);
+
+ /* DMALD and DMAST instructions */
+ DmaProgBuf += XDmaPs_Instr_DMALD(DmaProgBuf);
+ DmaProgBuf += XDmaPs_Instr_DMAST(DmaProgBuf);
+
+ /* inner DMALPEND */
+ DmaProgBuf += XDmaPs_Instr_DMALPEND(DmaProgBuf,
+ DmaProgBuf - 2, 0);
+ /* outer DMALPEND */
+ DmaProgBuf += XDmaPs_Instr_DMALPEND(DmaProgBuf,
+ InnerLoopStart, 1);
+
+ /* return the number of bytes */
+ return DmaProgBuf - DmaProgLoopStart;
+}
+
+/*
+ * [31:28] endian_swap_size b0000
+ * [27:25] dst_cache_ctrl b000
+ * [24:22] dst_prot_ctrl b000
+ * [21:18] dst_burst_len b0000
+ * [17:15] dst_burst_size b000
+ * [14] dst_inc b0
+ * [27:25] src_cache_ctrl b000
+ * [24:22] src_prot_ctrl b000
+ * [21:18] src_burst_len b0000
+ * [17:15] src_burst_size b000
+ * [14] src_inc b0
+ */
+#define XDMAPS_CCR_SINGLE_BYTE (0x0)
+#define XDMAPS_CCR_M2M_SINGLE_BYTE ((0x1 << 14) | 0x1)
+
+
+/****************************************************************************/
+/**
+*
+* Construct the DMA program based on the descriptions of the DMA transfer.
+* The function handles memory to memory DMA transfers.
+* It also handles unalgined head and small amount of residue tail.
+*
+* @param Channel DMA channel number
+* @param Cmd is the DMA command.
+* @param CacheLength is the icache line length, in terms of bytes.
+* If it's zero, the performance enhancement feature will be
+* turned off.
+*
+* @returns The number of bytes for the program.
+*
+* @note None.
+*
+*****************************************************************************/
+static int XDmaPs_BuildDmaProg(unsigned Channel, XDmaPs_Cmd *Cmd,
+ unsigned CacheLength)
+{
+ /*
+ * unpack arguments
+ */
+ char *DmaProgBuf = (char *)Cmd->GeneratedDmaProg;
+ unsigned DevChan = Channel;
+ unsigned long DmaLength = Cmd->BD.Length;
+ u32 SrcAddr = Cmd->BD.SrcAddr;
+
+ unsigned SrcInc = Cmd->ChanCtrl.SrcInc;
+ u32 DstAddr = Cmd->BD.DstAddr;
+ unsigned DstInc = Cmd->ChanCtrl.DstInc;
+
+ char *DmaProgStart = DmaProgBuf;
+
+ unsigned int BurstBytes;
+ unsigned int LoopCount;
+ unsigned int LoopCount1 = 0;
+ unsigned int LoopResidue = 0;
+ unsigned int TailBytes;
+ unsigned int TailWords;
+ int DmaProgBytes;
+ u32 CCRValue;
+ unsigned int Unaligned;
+ unsigned int UnalignedCount;
+ unsigned int MemBurstSize = 1;
+ u32 MemAddr = 0;
+ unsigned int Index;
+ unsigned int SrcUnaligned = 0;
+ unsigned int DstUnaligned = 0;
+
+ XDmaPs_ChanCtrl *ChanCtrl;
+ XDmaPs_ChanCtrl WordChanCtrl;
+ static XDmaPs_ChanCtrl Mem2MemByteCC;
+
+ Mem2MemByteCC.EndianSwapSize = 0;
+ Mem2MemByteCC.DstCacheCtrl = 0;
+ Mem2MemByteCC.DstProtCtrl = 0;
+ Mem2MemByteCC.DstBurstLen = 1;
+ Mem2MemByteCC.DstBurstSize = 1;
+ Mem2MemByteCC.DstInc = 1;
+ Mem2MemByteCC.SrcCacheCtrl = 0;
+ Mem2MemByteCC.SrcProtCtrl = 0;
+ Mem2MemByteCC.SrcBurstLen = 1;
+ Mem2MemByteCC.SrcBurstSize = 1;
+ Mem2MemByteCC.SrcInc = 1;
+
+ ChanCtrl = &Cmd->ChanCtrl;
+
+ /* insert DMAMOV for SAR and DAR */
+ DmaProgBuf += XDmaPs_Instr_DMAMOV(DmaProgBuf,
+ XDMAPS_MOV_SAR,
+ SrcAddr);
+ DmaProgBuf += XDmaPs_Instr_DMAMOV(DmaProgBuf,
+ XDMAPS_MOV_DAR,
+ DstAddr);
+
+
+ if (ChanCtrl->SrcInc)
+ SrcUnaligned = SrcAddr % ChanCtrl->SrcBurstSize;
+
+ if (ChanCtrl->DstInc)
+ DstUnaligned = DstAddr % ChanCtrl->DstBurstSize;
+
+ if ((SrcUnaligned && DstInc) || (DstUnaligned && SrcInc)) {
+ ChanCtrl = &Mem2MemByteCC;
+ }
+
+ if (ChanCtrl->SrcInc) {
+ MemBurstSize = ChanCtrl->SrcBurstSize;
+ MemAddr = SrcAddr;
+
+ } else if (ChanCtrl->DstInc) {
+ MemBurstSize = ChanCtrl->DstBurstSize;
+ MemAddr = DstAddr;
+ }
+
+ /* check whether the head is aligned or not */
+ Unaligned = MemAddr % MemBurstSize;
+
+ if (Unaligned) {
+ /* if head is unaligned, transfer head in bytes */
+ UnalignedCount = MemBurstSize - Unaligned;
+ CCRValue = XDMAPS_CCR_SINGLE_BYTE
+ | (SrcInc & 1)
+ | ((DstInc & 1) << 14);
+
+ DmaProgBuf += XDmaPs_Instr_DMAMOV(DmaProgBuf,
+ XDMAPS_MOV_CCR,
+ CCRValue);
+
+ for (Index = 0; Index < UnalignedCount; Index++) {
+ DmaProgBuf += XDmaPs_Instr_DMALD(DmaProgBuf);
+ DmaProgBuf += XDmaPs_Instr_DMAST(DmaProgBuf);
+ }
+
+ DmaLength -= UnalignedCount;
+ }
+
+ /* now the burst transfer part */
+ CCRValue = XDmaPs_ToCCRValue(ChanCtrl);
+ DmaProgBuf += XDmaPs_Instr_DMAMOV(DmaProgBuf,
+ XDMAPS_MOV_CCR,
+ CCRValue);
+
+ BurstBytes = ChanCtrl->SrcBurstSize * ChanCtrl->SrcBurstLen;
+
+ LoopCount = DmaLength / BurstBytes;
+ TailBytes = DmaLength % BurstBytes;
+
+ /*
+ * the loop count register is 8-bit wide, so if we need
+ * a larger loop, we need to have nested loops
+ */
+ if (LoopCount > 256) {
+ LoopCount1 = LoopCount / 256;
+ if (LoopCount1 > 256) {
+ xil_printf("DMA operation cannot fit in a 2-level "
+ "loop for channel %d, please reduce the "
+ "DMA length or increase the burst size or "
+ "length",
+ Channel);
+ return 0;
+ }
+ LoopResidue = LoopCount % 256;
+
+ if (LoopCount1 > 1)
+ DmaProgBuf +=
+ XDmaPs_ConstructNestedLoop(DmaProgStart,
+ CacheLength,
+ DmaProgBuf,
+ LoopCount1,
+ 256);
+ else
+ DmaProgBuf +=
+ XDmaPs_ConstructSingleLoop(DmaProgStart,
+ CacheLength,
+ DmaProgBuf,
+ 256);
+
+ /* there will be some that cannot be covered by
+ * nested loops
+ */
+ LoopCount = LoopResidue;
+ }
+
+ if (LoopCount > 0) {
+ DmaProgBuf += XDmaPs_ConstructSingleLoop(DmaProgStart,
+ CacheLength,
+ DmaProgBuf,
+ LoopCount);
+ }
+
+ if (TailBytes) {
+ /* handle the tail */
+ TailWords = TailBytes / MemBurstSize;
+ TailBytes = TailBytes % MemBurstSize;
+
+ if (TailWords) {
+ WordChanCtrl = *ChanCtrl;
+ /*
+ * if we can transfer the tail in words, we will
+ * transfer words as much as possible
+ */
+ WordChanCtrl.SrcBurstSize = MemBurstSize;
+ WordChanCtrl.SrcBurstLen = 1;
+ WordChanCtrl.DstBurstSize = MemBurstSize;
+ WordChanCtrl.DstBurstLen = 1;
+
+
+ /*
+ * the burst length is 1
+ */
+ CCRValue = XDmaPs_ToCCRValue(&WordChanCtrl);
+
+ DmaProgBuf +=
+ XDmaPs_Instr_DMAMOV(DmaProgBuf,
+ XDMAPS_MOV_CCR,
+ CCRValue);
+ DmaProgBuf +=
+ XDmaPs_ConstructSingleLoop(DmaProgStart,
+ CacheLength,
+ DmaProgBuf,
+ TailWords);
+
+ }
+
+ if (TailBytes) {
+ /*
+ * for the rest, we'll tranfer in bytes
+ */
+ /*
+ * So far just to be safe, the tail bytes
+ * are transfered in a loop. We can optimize a little
+ * to perform a burst.
+ */
+ CCRValue = XDMAPS_CCR_SINGLE_BYTE
+ | (SrcInc & 1)
+ | ((DstInc & 1) << 14);
+
+ DmaProgBuf +=
+ XDmaPs_Instr_DMAMOV(DmaProgBuf,
+ XDMAPS_MOV_CCR,
+ CCRValue);
+
+ DmaProgBuf +=
+ XDmaPs_ConstructSingleLoop(DmaProgStart,
+ CacheLength,
+ DmaProgBuf,
+ TailBytes);
+
+ }
+ }
+
+ /* Add a memory barrier before DMASSEV as recommended by spec */
+ DmaProgBuf += XDmaPs_Instr_DMAWMB(DmaProgBuf);
+ DmaProgBuf += XDmaPs_Instr_DMASEV(DmaProgBuf, DevChan);
+ DmaProgBuf += XDmaPs_Instr_DMAEND(DmaProgBuf);
+
+ DmaProgBytes = DmaProgBuf - DmaProgStart;
+
+ Xil_DCacheFlushRange((u32)DmaProgStart, DmaProgBytes);
+
+ return DmaProgBytes;
+
+}
+
+
+/****************************************************************************/
+/**
+*
+* Generate a DMA program based for the DMA command, the buffer will be pointed
+* by the GeneratedDmaProg field of the command.
+*
+* @param InstPtr is then DMA instance.
+* @param Channel is the DMA channel number.
+* @param Cmd is the DMA command.
+*
+* @return - XST_SUCCESS on success.
+* - XST_FAILURE if it fails
+*
+* @note None.
+*
+*****************************************************************************/
+int XDmaPs_GenDmaProg(XDmaPs *InstPtr, unsigned int Channel, XDmaPs_Cmd *Cmd)
+{
+ void *Buf;
+ int ProgLen;
+ XDmaPs_ChannelData *ChanData;
+ XDmaPs_ChanCtrl *ChanCtrl;
+
+ Xil_AssertNonvoid(InstPtr != NULL);
+ Xil_AssertNonvoid(Cmd != NULL);
+
+
+ if (Channel > XDMAPS_CHANNELS_PER_DEV)
+ return XST_FAILURE;
+
+ ChanData = InstPtr->Chans + Channel;
+ ChanCtrl = &Cmd->ChanCtrl;
+
+ if (ChanCtrl->SrcBurstSize * ChanCtrl->SrcBurstLen
+ != ChanCtrl->DstBurstSize * ChanCtrl->DstBurstLen) {
+ return XST_FAILURE;
+ }
+
+
+ /*
+ * unaligned fixed address is not supported
+ */
+ if (!ChanCtrl->SrcInc && Cmd->BD.SrcAddr % ChanCtrl->SrcBurstSize) {
+ return XST_FAILURE;
+ }
+
+ if (!ChanCtrl->DstInc && Cmd->BD.DstAddr % ChanCtrl->DstBurstSize) {
+ return XST_FAILURE;
+ }
+
+ Buf = XDmaPs_BufPool_Allocate(ChanData->ProgBufPool);
+ if (Buf == NULL) {
+ return XST_FAILURE;
+ }
+
+ Cmd->GeneratedDmaProg = Buf;
+ ProgLen = XDmaPs_BuildDmaProg(Channel, Cmd,
+ InstPtr->CacheLength);
+ Cmd->GeneratedDmaProgLength = ProgLen;
+
+
+#ifdef XDMAPS_DEBUG
+ XDmaPs_Print_DmaProg(Cmd);
+#endif
+
+ if (ProgLen <= 0) {
+ /* something wrong, release the buffer */
+ XDmaPs_BufPool_Free(ChanData->ProgBufPool, Buf);
+ Cmd->GeneratedDmaProgLength = 0;
+ Cmd->GeneratedDmaProg = NULL;
+ return XST_FAILURE;
+ }
+
+ return XST_SUCCESS;
+}
+
+
+/****************************************************************************/
+/**
+ * Free the DMA program buffer that is pointed by the GeneratedDmaProg field
+ * of the command.
+ *
+ * @param InstPtr is then DMA instance.
+ * @param Channel is the DMA channel number.
+ * @param Cmd is the DMA command.
+ *
+ * @return XST_SUCCESS on success.
+ * XST_FAILURE if there is any error.
+ *
+ * @note None.
+ *
+ ****************************************************************************/
+int XDmaPs_FreeDmaProg(XDmaPs *InstPtr, unsigned int Channel, XDmaPs_Cmd *Cmd)
+{
+
+ void *Buf;
+ XDmaPs_ChannelData *ChanData;
+
+ Xil_AssertNonvoid(InstPtr != NULL);
+ Xil_AssertNonvoid(Cmd != NULL);
+
+ if (Channel > XDMAPS_CHANNELS_PER_DEV)
+ return XST_FAILURE;
+
+ Buf = (void *)Cmd->GeneratedDmaProg;
+ ChanData = InstPtr->Chans + Channel;
+
+ if (Buf) {
+ XDmaPs_BufPool_Free(ChanData->ProgBufPool, Buf);
+ Cmd->GeneratedDmaProg = 0;
+ Cmd->GeneratedDmaProgLength = 0;
+ }
+
+ return XST_SUCCESS;
+}
+
+
+/****************************************************************************/
+/**
+*
+* Start a DMA command. The command can only be invoked when the channel
+* is idle. The driver takes the command, generates DMA program if needed,
+* then pass the program to DMAC to execute.
+*
+* @param InstPtr is then DMA instance.
+* @param Channel is the DMA channel number.
+* @param Cmd is the DMA command.
+* @param HoldDmaProg is tag indicating whether the driver can release
+* the allocated DMA buffer or not. If a user wants to examine the
+* generated DMA program, the flag should be set to 1. After the
+* DMA program is finished, a user needs to explicity free the
+* buffer.
+*
+* @return
+* - XST_SUCCESS on success
+* - XST_DEVICE_BUSY if DMA is busy
+* - XST_FAILURE on other failures
+*
+* @note None.
+*
+****************************************************************************/
+int XDmaPs_Start(XDmaPs *InstPtr, unsigned int Channel,
+ XDmaPs_Cmd *Cmd,
+ int HoldDmaProg)
+{
+ int Status;
+ u32 DmaProg = 0;
+ u32 Inten;
+
+ Xil_AssertNonvoid(InstPtr != NULL);
+ Xil_AssertNonvoid(Cmd != NULL);
+
+
+ Cmd->DmaStatus = XST_FAILURE;
+
+ if (XDmaPs_IsActive(InstPtr, Channel))
+ return XST_DEVICE_BUSY;
+
+ if (!Cmd->UserDmaProg && !Cmd->GeneratedDmaProg) {
+ Status = XDmaPs_GenDmaProg(InstPtr, Channel, Cmd);
+ if (Status)
+ return XST_FAILURE;
+ }
+
+ InstPtr->Chans[Channel].HoldDmaProg = HoldDmaProg;
+
+ if (Cmd->UserDmaProg)
+ DmaProg = (u32)Cmd->UserDmaProg;
+ else if (Cmd->GeneratedDmaProg)
+ DmaProg = (u32)Cmd->GeneratedDmaProg;
+
+ if (DmaProg) {
+ /* enable the interrupt */
+ Inten = XDmaPs_ReadReg(InstPtr->Config.BaseAddress,
+ XDMAPS_INTEN_OFFSET);
+ Inten |= 0x01 << Channel; /* set the correpsonding bit */
+ XDmaPs_WriteReg(InstPtr->Config.BaseAddress,
+ XDMAPS_INTEN_OFFSET,
+ Inten);
+ Inten = XDmaPs_ReadReg(InstPtr->Config.BaseAddress,
+ XDMAPS_INTEN_OFFSET);
+
+ InstPtr->Chans[Channel].DmaCmdToHw = Cmd;
+
+ if (Cmd->ChanCtrl.SrcInc) {
+ Xil_DCacheFlushRange(Cmd->BD.SrcAddr, Cmd->BD.Length);
+ }
+ if (Cmd->ChanCtrl.DstInc) {
+ Xil_DCacheInvalidateRange(Cmd->BD.DstAddr,
+ Cmd->BD.Length);
+ }
+
+ Status = XDmaPs_Exec_DMAGO(InstPtr->Config.BaseAddress,
+ Channel, DmaProg);
+ }
+ else {
+ InstPtr->Chans[Channel].DmaCmdToHw = NULL;
+ Status = XST_FAILURE;
+ }
+
+ return Status;
+}
+
+/****************************************************************************/
+/**
+*
+* Checks whether the DMA channel is active or idle.
+*
+* @param InstPtr is the DMA instance.
+* @param Channel is the DMA channel number.
+*
+* @return 0: if the channel is idle
+* 1: otherwise
+*
+* @note None.
+*
+*****************************************************************************/
+int XDmaPs_IsActive(XDmaPs *InstPtr, unsigned int Channel)
+{
+ Xil_AssertNonvoid(InstPtr != NULL);
+
+ /* Need to assert Channel is in range */
+ if (Channel > XDMAPS_CHANNELS_PER_DEV)
+ return 0;
+
+ return InstPtr->Chans[Channel].DmaCmdToHw != NULL;
+}
+
+
+
+/****************************************************************************/
+/**
+*
+* Allocate a buffer of the DMA program buffer from the pool.
+*
+* @param Pool the DMA program pool.
+*
+* @return The allocated buffer, NULL if there is any error.
+*
+* @note None.
+*
+*****************************************************************************/
+static void *XDmaPs_BufPool_Allocate(XDmaPs_ProgBuf *Pool)
+{
+ int Index;
+
+ Xil_AssertNonvoid(Pool != NULL);
+
+ for (Index = 0; Index < XDMAPS_MAX_CHAN_BUFS; Index++) {
+ if (!Pool[Index].Allocated) {
+ Pool[Index].Allocated = 1;
+ return Pool[Index].Buf;
+ }
+ }
+
+ return NULL;
+
+}
+
+/*****************************************************************************/
+/**
+*
+* Driver done interrupt service routine for channel 0. We need this done ISR
+* mainly because the driver needs to release the DMA program buffer.
+* This is the one that connects the GIC
+*
+* @param InstPtr is the DMA instance.
+*
+* @return None.
+*
+* @note None.
+*
+******************************************************************************/
+void XDmaPs_DoneISR_0(XDmaPs *InstPtr)
+{
+ XDmaPs_DoneISR_n(InstPtr, 0);
+}
+
+/*****************************************************************************/
+/**
+*
+* Driver done interrupt service routine for channel 1. We need this done ISR
+* mainly because the driver needs to release the DMA program buffer.
+* This is the one that connects the GIC
+*
+* @param InstPtr is the DMA instance.
+*
+* @return None.
+*
+* @note None.
+*
+******************************************************************************/
+void XDmaPs_DoneISR_1(XDmaPs *InstPtr)
+{
+ XDmaPs_DoneISR_n(InstPtr, 1);
+}
+
+/*****************************************************************************/
+/**
+*
+* Driver done interrupt service routine for channel 2. We need this done ISR
+* mainly because the driver needs to release the DMA program buffer.
+* This is the one that connects the GIC
+*
+* @param InstPtr is the DMA instance.
+*
+* @return None.
+*
+* @note None.
+*
+******************************************************************************/
+void XDmaPs_DoneISR_2(XDmaPs *InstPtr)
+{
+ XDmaPs_DoneISR_n(InstPtr, 2);
+}
+
+/*****************************************************************************/
+/**
+*
+* Driver done interrupt service routine for channel 3. We need this done ISR
+* mainly because the driver needs to release the DMA program buffer.
+* This is the one that connects the GIC
+*
+* @param InstPtr is the DMA instance.
+*
+* @return None.
+*
+* @note None.
+*
+******************************************************************************/
+void XDmaPs_DoneISR_3(XDmaPs *InstPtr)
+{
+ XDmaPs_DoneISR_n(InstPtr, 3);
+}
+
+/*****************************************************************************/
+/**
+*
+* Driver done interrupt service routine for channel 4. We need this done ISR
+* mainly because the driver needs to release the DMA program buffer.
+* This is the one that connects the GIC
+*
+* @param InstPtr is the DMA instance.
+*
+* @return None.
+*
+* @note None.
+*
+******************************************************************************/
+void XDmaPs_DoneISR_4(XDmaPs *InstPtr)
+{
+ XDmaPs_DoneISR_n(InstPtr, 4);
+}
+
+/*****************************************************************************/
+/**
+*
+* Driver done interrupt service routine for channel 5. We need this done ISR
+* mainly because the driver needs to release the DMA program buffer.
+* This is the one that connects the GIC
+*
+* @param InstPtr is the DMA instance.
+*
+* @return None.
+*
+* @note None.
+*
+******************************************************************************/
+void XDmaPs_DoneISR_5(XDmaPs *InstPtr)
+{
+ XDmaPs_DoneISR_n(InstPtr, 5);
+}
+
+/*****************************************************************************/
+/**
+*
+* Driver done interrupt service routine for channel 6. We need this done ISR
+* mainly because the driver needs to release the DMA program buffer.
+* This is the one that connects the GIC
+*
+* @param InstPtr is the DMA instance.
+*
+* @return None.
+*
+* @note None.
+*
+******************************************************************************/
+void XDmaPs_DoneISR_6(XDmaPs *InstPtr)
+{
+ XDmaPs_DoneISR_n(InstPtr, 6);
+}
+
+/*****************************************************************************/
+/**
+*
+* Driver done interrupt service routine for channel 7. We need this done ISR
+* mainly because the driver needs to release the DMA program buffer.
+* This is the one that connects the GIC
+*
+* @param InstPtr is the DMA instance.
+*
+* @return None.
+*
+* @note None.
+*
+******************************************************************************/
+void XDmaPs_DoneISR_7(XDmaPs *InstPtr)
+{
+ XDmaPs_DoneISR_n(InstPtr, 7);
+}
+
+#ifndef XDMAPS_MAX_WAIT
+#define XDMAPS_MAX_WAIT 4000
+#endif
+
+/****************************************************************************/
+/**
+* Use the debug registers to kill the DMA thread.
+*
+* @param BaseAddr is DMA device base address.
+* @param Channel is the DMA channel number.
+* @param Thread is Debug thread encoding.
+* 0: DMA manager thread, 1: DMA channel.
+*
+* @return 0 on success, -1 on time out
+*
+* @note None.
+*
+*****************************************************************************/
+static int XDmaPs_Exec_DMAKILL(u32 BaseAddr,
+ unsigned int Channel,
+ unsigned int Thread)
+{
+ u32 DbgInst0;
+ int WaitCount;
+
+ DbgInst0 = XDmaPs_DBGINST0(0, 0x01, Channel, Thread);
+
+ /* wait while debug status is busy */
+ WaitCount = 0;
+ while ((XDmaPs_ReadReg(BaseAddr, XDMAPS_DBGSTATUS_OFFSET)
+ & XDMAPS_DBGSTATUS_BUSY)
+ && (WaitCount < XDMAPS_MAX_WAIT))
+ WaitCount++;
+
+ if (WaitCount >= XDMAPS_MAX_WAIT) {
+ /* wait time out */
+ xil_printf("PL330 device at %x debug status busy time out\n",
+ BaseAddr);
+
+ return -1;
+ }
+
+ /* write debug instruction 0 */
+ XDmaPs_WriteReg(BaseAddr, XDMAPS_DBGINST0_OFFSET, DbgInst0);
+
+ XDmaPs_WriteReg(BaseAddr, XDMAPS_DBGINST1_OFFSET, 0);
+
+
+ /* run the command in DbgInst0 and DbgInst1 */
+ XDmaPs_WriteReg(BaseAddr, XDMAPS_DBGCMD_OFFSET, 0);
+
+ return 0;
+}
+
+/****************************************************************************/
+/**
+*
+*
+* Free a buffer of the DMA program buffer.
+* @param Pool the DMA program pool.
+* @param Buf the DMA program buffer to be release.
+*
+* @return None
+*
+* @note None.
+*
+*****************************************************************************/
+static void XDmaPs_BufPool_Free(XDmaPs_ProgBuf *Pool, void *Buf)
+{
+ int Index;
+ Xil_AssertVoid(Pool != NULL);
+
+ for (Index = 0; Index < XDMAPS_MAX_CHAN_BUFS; Index++) {
+ if (Pool[Index].Buf == Buf) {
+ if (Pool[Index].Allocated) {
+ Pool[Index].Allocated = 0;
+ }
+ }
+ }
+}
+
+/*****************************************************************************/
+/**
+* XDmaPs_Exec_DMAGO - Execute the DMAGO to start a channel.
+*
+* @param BaseAddr PL330 device base address
+* @param Channel Channel number for the device
+* @param DmaProg DMA program starting address, this should be DMA address
+*
+* @return 0 on success, -1 on time out
+*
+* @note None.
+*
+****************************************************************************/
+static int XDmaPs_Exec_DMAGO(u32 BaseAddr, unsigned int Channel, u32 DmaProg)
+{
+ char DmaGoProg[8];
+ u32 DbgInst0;
+ u32 DbgInst1;
+
+ int WaitCount;
+
+ XDmaPs_Instr_DMAGO(DmaGoProg, Channel, DmaProg, 0);
+
+ DbgInst0 = XDmaPs_DBGINST0(*(DmaGoProg + 1), *DmaGoProg, 0, 0);
+ DbgInst1 = (u32)DmaProg;
+
+ /* wait while debug status is busy */
+ WaitCount = 0;
+ while ((XDmaPs_ReadReg(BaseAddr, XDMAPS_DBGSTATUS_OFFSET)
+ & XDMAPS_DBGSTATUS_BUSY)
+ && (WaitCount < XDMAPS_MAX_WAIT)) {
+
+ WaitCount++;
+ }
+
+ if (WaitCount >= XDMAPS_MAX_WAIT) {
+ xil_printf("PL330 device at %x debug status busy time out\r\n",
+ BaseAddr);
+ return -1;
+ }
+
+ /* write debug instruction 0 */
+ XDmaPs_WriteReg(BaseAddr, XDMAPS_DBGINST0_OFFSET, DbgInst0);
+ /* write debug instruction 1 */
+ XDmaPs_WriteReg(BaseAddr, XDMAPS_DBGINST1_OFFSET, DbgInst1);
+
+
+ /* wait while the DMA Manager is busy */
+ WaitCount = 0;
+ while ((XDmaPs_ReadReg(BaseAddr,
+ XDMAPS_DS_OFFSET) & XDMAPS_DS_DMA_STATUS)
+ != XDMAPS_DS_DMA_STATUS_STOPPED
+ && WaitCount <= XDMAPS_MAX_WAIT) {
+ WaitCount++;
+ }
+
+ if (WaitCount >= XDMAPS_MAX_WAIT) {
+ xil_printf("PL330 device at %x debug status busy time out\r\n",
+ BaseAddr);
+ return -1;
+ }
+
+ /* run the command in DbgInst0 and DbgInst1 */
+ XDmaPs_WriteReg(BaseAddr, XDMAPS_DBGCMD_OFFSET, 0);
+
+ return 0;
+}
+
+
+/****************************************************************************/
+/**
+*
+* It's the generic Done ISR.
+* @param InstPtr is the DMA instance.
+* @param Channel is the DMA channel numer.
+*
+* @return None.*
+*
+* @note None.
+*
+*****************************************************************************/
+static void XDmaPs_DoneISR_n(XDmaPs *InstPtr, unsigned Channel)
+{
+
+ void *DmaProgBuf;
+ XDmaPs_ChannelData *ChanData;
+ XDmaPs_Cmd *DmaCmd;
+ //u32 Value;
+
+ ChanData = InstPtr->Chans + Channel;
+
+ /*Value = XDmaPs_ReadReg(InstPtr->Config.BaseAddress,
+ XDMAPS_INTSTATUS_OFFSET);*/
+
+ /* clear the interrupt status */
+ XDmaPs_WriteReg(InstPtr->Config.BaseAddress,
+ XDMAPS_INTCLR_OFFSET,
+ 1 << ChanData->ChanId);
+
+ /*Value = XDmaPs_ReadReg(InstPtr->Config.BaseAddress,
+ XDMAPS_INTSTATUS_OFFSET);*/
+
+
+ DmaCmd = ChanData->DmaCmdToHw;
+ if (DmaCmd) {
+ if (!ChanData->HoldDmaProg) {
+ DmaProgBuf = (void *)DmaCmd->GeneratedDmaProg;
+ if (DmaProgBuf)
+ XDmaPs_BufPool_Free(ChanData->ProgBufPool,
+ DmaProgBuf);
+ DmaCmd->GeneratedDmaProg = NULL;
+ }
+
+ DmaCmd->DmaStatus = 0;
+ ChanData->DmaCmdToHw = NULL;
+ ChanData->DmaCmdFromHw = DmaCmd;
+
+ if (ChanData->DoneHandler)
+ ChanData->DoneHandler(Channel, DmaCmd,
+ ChanData->DoneRef);
+ }
+
+}
+
+
+/****************************************************************************/
+/**
+* Prints the content of the buffer in bytes
+* @param Buf is the buffer.
+* @param Length is the length of the DMA program.
+*
+* @return None.
+*
+* @note None.
+****************************************************************************/
+static void XDmaPs_Print_DmaProgBuf(char *Buf, int Length)
+{
+ int Index;
+ for (Index = 0; Index < Length; Index++)
+ xil_printf("[%x] %x\r\n", Index, Buf[Index]);
+
+}
+/****************************************************************************/
+/**
+* Print the Dma Prog Contents.
+*
+* @param Cmd is the command buffer.
+*
+* @return None.
+*
+* @note None.
+*
+*****************************************************************************/
+ void XDmaPs_Print_DmaProg(XDmaPs_Cmd *Cmd)
+{
+ if (Cmd->GeneratedDmaProg && Cmd->GeneratedDmaProgLength) {
+ xil_printf("Generated DMA program (%d):\r\n",
+ Cmd->GeneratedDmaProgLength);
+ XDmaPs_Print_DmaProgBuf((char *)Cmd->GeneratedDmaProg,
+ Cmd->GeneratedDmaProgLength);
+ }
+
+ if (Cmd->UserDmaProg && Cmd->UserDmaProgLength) {
+ xil_printf("User defined DMA program (%d):\r\n",
+ Cmd->UserDmaProgLength);
+ XDmaPs_Print_DmaProgBuf((char *)Cmd->UserDmaProg,
+ Cmd->UserDmaProgLength);
+ }
+}
+
+
+/** @} */
diff --git a/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/dmaps_v2_5/src/xdmaps.h b/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/dmaps_v2_5/src/xdmaps.h
new file mode 100644
index 0000000..831a2dd
--- /dev/null
+++ b/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/dmaps_v2_5/src/xdmaps.h
@@ -0,0 +1,347 @@
+/******************************************************************************
+*
+* Copyright (C) 2009 - 2019 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+* THE SOFTWARE.
+*
+*
+*
+******************************************************************************/
+/****************************************************************************/
+/**
+*
+* @file xdmaps.h
+* @addtogroup dmaps_v2_5
+* @{
+* @details
+*
+*
+* <pre>
+* MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ----- ------ -------- ----------------------------------------------
+* 1.00 hbm 08/19/10 First Release
+* 1.01a nm 12/20/12 Added definition XDMAPS_CHANNELS_PER_DEV which specifies
+* the maximum number of channels.
+* Replaced the usage of XPAR_XDMAPS_CHANNELS_PER_DEV
+* with XDMAPS_CHANNELS_PER_DEV defined in xdmaps_hw.h.
+* Added the tcl file to automatically generate the
+* xparameters.h
+* 1.02a sg 05/16/12 Made changes for doxygen and moved some function
+* header from the xdmaps.h file to xdmaps.c file
+* Other cleanup for coding guidelines and CR 657109
+* and CR 657898
+* The xdmaps_example_no_intr.c example is removed
+* as it is using interrupts and is similar to
+* the interrupt example - CR 652477
+* 1.03a sg 07/16/2012 changed inline to __inline for CR665681
+* 1.04a nm 10/22/2012 Fixed CR# 681671.
+* 1.05a nm 04/15/2013 Fixed CR# 704396. Removed warnings when compiled
+* with -Wall and -Wextra option in bsp.
+* 05/01/2013 Fixed CR# 700189. Changed XDmaPs_BuildDmaProg()
+* function description.
+* Fixed CR# 704396. Removed unused variables
+* UseM2MByte & MemBurstLen from XDmaPs_BuildDmaProg()
+* function.
+* 1.07a asa 11/02/13. Made changes to fix compilation issues for iarcc.
+* Removed the PDBG prints. By default they were always
+* defined out and never used. The PDBG is non-standard for
+* Xilinx drivers and no other driver does something similar.
+* Since there is no easy way to fix compilation issues with
+* the IARCC compiler around PDBG, it is better to remove it.
+* Users can always use xil_printfs if they want to debug.
+* 2.0 adk 10/12/13 Updated as per the New Tcl API's
+* 2.01 kpc 08/23/14 Fixed the IAR compiler reported errors
+* 2.2 mus 08/12/16 Declared all inline functions in xdmaps.c as extern, to avoid
+* linker error for IAR compiler
+* 2.3 ms 01/23/17 Modified xil_printf statement in main function for all
+* examples to ensure that "Successfully ran" and "Failed"
+* strings are available in all examples. This is a fix
+* for CR-965028.
+* ms 03/17/17 Added readme.txt file in examples folder for doxygen
+* generation.
+* 2.4 adk 13/08/18 Fixed armcc compiler warnings in the driver CR-1008310.
+* </pre>
+*
+*****************************************************************************/
+
+#ifndef XDMAPS_H /* prevent circular inclusions */
+#define XDMAPS_H /* by using protection macros */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/***************************** Include Files ********************************/
+
+#include "xparameters.h"
+#include "xil_types.h"
+#include "xil_assert.h"
+#include "xstatus.h"
+
+#include "xdmaps_hw.h"
+
+/************************** Constant Definitions ****************************/
+
+/**************************** Type Definitions ******************************/
+
+/**
+ * This typedef contains configuration information for the device.
+ */
+typedef struct {
+ u16 DeviceId; /**< Unique ID of device */
+ u32 BaseAddress; /**< Base address of device (IPIF) */
+} XDmaPs_Config;
+
+
+/** DMA channle control structure. It's for AXI bus transaction.
+ * This struct will be translated into a 32-bit channel control register value.
+ */
+typedef struct {
+ unsigned int EndianSwapSize; /**< Endian swap size. */
+ unsigned int DstCacheCtrl; /**< Destination cache control */
+ unsigned int DstProtCtrl; /**< Destination protection control */
+ unsigned int DstBurstLen; /**< Destination burst length */
+ unsigned int DstBurstSize; /**< Destination burst size */
+ unsigned int DstInc; /**< Destination incrementing or fixed
+ * address */
+ unsigned int SrcCacheCtrl; /**< Source cache control */
+ unsigned int SrcProtCtrl; /**< Source protection control */
+ unsigned int SrcBurstLen; /**< Source burst length */
+ unsigned int SrcBurstSize; /**< Source burst size */
+ unsigned int SrcInc; /**< Source incrementing or fixed
+ * address */
+} XDmaPs_ChanCtrl;
+
+/** DMA block descriptor stucture.
+ */
+typedef struct {
+ u32 SrcAddr; /**< Source starting address */
+ u32 DstAddr; /**< Destination starting address */
+ unsigned int Length; /**< Number of bytes for the block */
+} XDmaPs_BD;
+
+/**
+ * A DMA command consisits of a channel control struct, a block descriptor,
+ * a user defined program, a pointer pointing to generated DMA program, and
+ * execution result.
+ *
+ */
+typedef struct {
+ XDmaPs_ChanCtrl ChanCtrl; /**< Channel Control Struct */
+ XDmaPs_BD BD; /**< Together with SgLength field,
+ * it's a scatter-gather list.
+ */
+ void *UserDmaProg; /**< If user wants the driver to
+ * execute their own DMA program,
+ * this field points to the DMA
+ * program.
+ */
+ int UserDmaProgLength; /**< The length of user defined
+ * DMA program.
+ */
+
+ void *GeneratedDmaProg; /**< The DMA program genreated
+ * by the driver. This field will be
+ * set if a user invokes the DMA
+ * program generation function. Or
+ * the DMA command is finished and
+ * a user informs the driver not to
+ * release the program buffer.
+ * This field has two purposes, one
+ * is to ask the driver to generate
+ * a DMA program while the DMAC is
+ * performaning DMA transactions. The
+ * other purpose is to debug the
+ * driver.
+ */
+ int GeneratedDmaProgLength; /**< The length of the DMA program
+ * generated by the driver
+ */
+ int DmaStatus; /**< 0 on success, otherwise error code
+ */
+ u32 ChanFaultType; /**< Channel fault type in case of fault
+ */
+ u32 ChanFaultPCAddr; /**< Channel fault PC address
+ */
+} XDmaPs_Cmd;
+
+/**
+ * It's the done handler a user can set for a channel
+ */
+typedef void (*XDmaPsDoneHandler) (unsigned int Channel,
+ XDmaPs_Cmd *DmaCmd,
+ void *CallbackRef);
+
+/**
+ * It's the fault handler a user can set for a channel
+ */
+typedef void (*XDmaPsFaultHandler) (unsigned int Channel,
+ XDmaPs_Cmd *DmaCmd,
+ void *CallbackRef);
+
+#define XDMAPS_MAX_CHAN_BUFS 2
+#define XDMAPS_CHAN_BUF_LEN 128
+
+/**
+ * The XDmaPs_ProgBuf is the struct for a DMA program buffer.
+ */
+typedef struct {
+ char Buf[XDMAPS_CHAN_BUF_LEN]; /**< The actual buffer the holds the
+ * content */
+ unsigned Len; /**< The actual length of the DMA
+ * program in bytes. */
+ int Allocated; /**< A tag indicating whether the
+ * buffer is allocated or not */
+} XDmaPs_ProgBuf;
+
+/**
+ * The XDmaPs_ChannelData is a struct to book keep individual channel of
+ * the DMAC.
+ */
+typedef struct {
+ unsigned DevId; /**< Device id indicating which DMAC */
+ unsigned ChanId; /**< Channel number of the DMAC */
+ XDmaPs_ProgBuf ProgBufPool[XDMAPS_MAX_CHAN_BUFS]; /**< A pool of
+ program buffers*/
+ XDmaPsDoneHandler DoneHandler; /**< Done interrupt handler */
+ void *DoneRef; /**< Done interrupt callback data */
+ XDmaPs_Cmd *DmaCmdToHw; /**< DMA command being executed */
+ XDmaPs_Cmd *DmaCmdFromHw; /**< DMA command that is finished.
+ * This field is for debugging purpose
+ */
+ int HoldDmaProg; /**< A tag indicating whether to hold the
+ * DMA program after the DMA is done.
+ */
+
+} XDmaPs_ChannelData;
+
+/**
+ * The XDmaPs driver instance data structure. A pointer to an instance data
+ * structure is passed around by functions to refer to a specific driver
+ * instance.
+ */
+typedef struct {
+ XDmaPs_Config Config; /**< Configuration data structure */
+ int IsReady; /**< Device is Ready */
+ int CacheLength; /**< icache length */
+ XDmaPsFaultHandler FaultHandler; /**< fault interrupt handler */
+ void *FaultRef; /**< fault call back data */
+ XDmaPs_ChannelData Chans[XDMAPS_CHANNELS_PER_DEV];
+ /**<
+ * channel data
+ */
+} XDmaPs;
+
+/*
+ * Functions implemented in xdmaps.c
+ */
+int XDmaPs_CfgInitialize(XDmaPs *InstPtr,
+ XDmaPs_Config *Config,
+ u32 EffectiveAddr);
+
+int XDmaPs_Start(XDmaPs *InstPtr, unsigned int Channel,
+ XDmaPs_Cmd *Cmd,
+ int HoldDmaProg);
+
+int XDmaPs_IsActive(XDmaPs *InstPtr, unsigned int Channel);
+int XDmaPs_GenDmaProg(XDmaPs *InstPtr, unsigned int Channel,
+ XDmaPs_Cmd *Cmd);
+int XDmaPs_FreeDmaProg(XDmaPs *InstPtr, unsigned int Channel,
+ XDmaPs_Cmd *Cmd);
+void XDmaPs_Print_DmaProg(XDmaPs_Cmd *Cmd);
+
+
+int XDmaPs_ResetManager(XDmaPs *InstPtr);
+int XDmaPs_ResetChannel(XDmaPs *InstPtr, unsigned int Channel);
+
+
+int XDmaPs_SetDoneHandler(XDmaPs *InstPtr,
+ unsigned Channel,
+ XDmaPsDoneHandler DoneHandler,
+ void *CallbackRef);
+
+int XDmaPs_SetFaultHandler(XDmaPs *InstPtr,
+ XDmaPsFaultHandler FaultHandler,
+ void *CallbackRef);
+
+void XDmaPs_Print_DmaProg(XDmaPs_Cmd *Cmd);
+int XDmaPs_Instr_DMARMB(char *DmaProg);
+int XDmaPs_Instr_DMAWMB(char *DmaProg);
+
+/**
+ * To avoid linking error,Declare all inline functions as extern for
+ * IAR compiler
+ */
+#ifdef __ICCARM__
+extern INLINE int XDmaPs_Instr_DMAEND(char *DmaProg);
+extern INLINE void XDmaPs_Memcpy4(char *Dst, char *Src);
+extern INLINE int XDmaPs_Instr_DMAGO(char *DmaProg, unsigned int Cn,
+ u32 Imm, unsigned int Ns);
+extern INLINE int XDmaPs_Instr_DMALD(char *DmaProg);
+extern INLINE int XDmaPs_Instr_DMALP(char *DmaProg, unsigned Lc,
+ unsigned LoopIterations);
+extern INLINE int XDmaPs_Instr_DMALPEND(char *DmaProg, char *BodyStart, unsigned Lc);
+extern INLINE int XDmaPs_Instr_DMAMOV(char *DmaProg, unsigned Rd, u32 Imm);
+extern INLINE int XDmaPs_Instr_DMANOP(char *DmaProg);
+extern INLINE int XDmaPs_Instr_DMASEV(char *DmaProg, unsigned int EventNumber);
+extern INLINE int XDmaPs_Instr_DMAST(char *DmaProg);
+extern INLINE unsigned XDmaPs_ToEndianSwapSizeBits(unsigned int EndianSwapSize);
+extern INLINE unsigned XDmaPs_ToBurstSizeBits(unsigned BurstSize);
+#endif
+
+/**
+ * Driver done interrupt service routines for the channels.
+ * We need this done ISR mainly because the driver needs to release the
+ * DMA program buffer. This is the one that connects the GIC
+ */
+void XDmaPs_DoneISR_0(XDmaPs *InstPtr);
+void XDmaPs_DoneISR_1(XDmaPs *InstPtr);
+void XDmaPs_DoneISR_2(XDmaPs *InstPtr);
+void XDmaPs_DoneISR_3(XDmaPs *InstPtr);
+void XDmaPs_DoneISR_4(XDmaPs *InstPtr);
+void XDmaPs_DoneISR_5(XDmaPs *InstPtr);
+void XDmaPs_DoneISR_6(XDmaPs *InstPtr);
+void XDmaPs_DoneISR_7(XDmaPs *InstPtr);
+
+/**
+ * Driver fault interrupt service routine
+ */
+void XDmaPs_FaultISR(XDmaPs *InstPtr);
+
+
+/*
+ * Static loopup function implemented in xdmaps_sinit.c
+ */
+XDmaPs_Config *XDmaPs_LookupConfig(u16 DeviceId);
+
+
+/*
+ * self-test functions in xdmaps_selftest.c
+ */
+int XDmaPs_SelfTest(XDmaPs *InstPtr);
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* end of protection macro */
+/** @} */
diff --git a/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/dmaps_v2_5/src/xdmaps_g.c b/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/dmaps_v2_5/src/xdmaps_g.c
new file mode 100644
index 0000000..abe50eb
--- /dev/null
+++ b/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/dmaps_v2_5/src/xdmaps_g.c
@@ -0,0 +1,51 @@
+
+/*******************************************************************
+*
+* CAUTION: This file is automatically generated by HSI.
+* Version: 2019.2
+* DO NOT EDIT.
+*
+* Copyright (C) 2010-2021 Xilinx, Inc. All Rights Reserved.*
+*Permission is hereby granted, free of charge, to any person obtaining a copy
+*of this software and associated documentation files (the Software), to deal
+*in the Software without restriction, including without limitation the rights
+*to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+*copies of the Software, and to permit persons to whom the Software is
+*furnished to do so, subject to the following conditions:
+*
+*The above copyright notice and this permission notice shall be included in
+*all copies or substantial portions of the Software.
+*
+*THE SOFTWARE IS PROVIDED AS IS, WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+*IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+*FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+*THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+*WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT
+*OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+*
+
+*
+* Description: Driver configuration
+*
+*******************************************************************/
+
+#include "xparameters.h"
+#include "xdmaps.h"
+
+/*
+* The configuration table for devices
+*/
+
+XDmaPs_Config XDmaPs_ConfigTable[XPAR_XDMAPS_NUM_INSTANCES] =
+{
+ {
+ XPAR_PS7_DMA_NS_DEVICE_ID,
+ XPAR_PS7_DMA_NS_BASEADDR
+ },
+ {
+ XPAR_PS7_DMA_S_DEVICE_ID,
+ XPAR_PS7_DMA_S_BASEADDR
+ }
+};
+
+
diff --git a/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/dmaps_v2_5/src/xdmaps_hw.c b/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/dmaps_v2_5/src/xdmaps_hw.c
new file mode 100644
index 0000000..2344528
--- /dev/null
+++ b/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/dmaps_v2_5/src/xdmaps_hw.c
@@ -0,0 +1,110 @@
+/******************************************************************************
+*
+* Copyright (C) 2009 - 2019 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+* THE SOFTWARE.
+*
+*
+*
+******************************************************************************/
+/****************************************************************************/
+/**
+*
+* @file xdmaps_hw.c
+* @addtogroup dmaps_v2_5
+* @{
+*
+* This file contains the implementation of the interface reset functionality
+* for XDmaPs driver.
+*
+* <pre>
+* MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ----- ------ -------- ----------------------------------------------
+* 1.06a kpc 10/07/13 First release
+* </pre>
+*
+*****************************************************************************/
+
+/***************************** Include Files ********************************/
+#include "xdmaps_hw.h"
+
+/************************** Constant Definitions ****************************/
+
+/**************************** Type Definitions ******************************/
+
+/***************** Macros (Inline Functions) Definitions ********************/
+#ifndef XDMAPS_MAX_WAIT
+#define XDMAPS_MAX_WAIT 4000
+#endif
+/************************** Function Prototypes *****************************/
+
+/************************** Variable Definitions ****************************/
+
+/*****************************************************************************/
+/**
+* This function perform the reset sequence to the given dmaps interface by
+* configuring the appropriate control bits in the dmaps specifc registers
+* the dmaps reset squence involves the following steps
+* Disable all the interuupts
+* Clear the pending interrupts
+* Kill all the active channel threads
+* Kill the manager thread
+*
+* @param BaseAddress of the interface
+*
+* @return N/A
+*
+* @note
+* This function will not modify the slcr registers that are relavant for
+* dmaps controller
+******************************************************************************/
+void XDmaPs_ResetHw(u32 BaseAddress)
+{
+ u32 DbgInst;
+ u32 WaitCount = 0;
+ u32 ChanIndex;
+
+ /* Disable all the interrupts */
+ XDmaPs_WriteReg(BaseAddress, XDMAPS_INTEN_OFFSET, 0x00);
+ /* Clear the interrupts */
+ XDmaPs_WriteReg(BaseAddress, XDMAPS_INTCLR_OFFSET, XDMAPS_INTCLR_ALL_MASK);
+ /* Kill the dma channel threads */
+ for (ChanIndex=0; ChanIndex < XDMAPS_CHANNELS_PER_DEV; ChanIndex++) {
+ while ((XDmaPs_ReadReg(BaseAddress, XDMAPS_DBGSTATUS_OFFSET)
+ & XDMAPS_DBGSTATUS_BUSY)
+ && (WaitCount < XDMAPS_MAX_WAIT))
+ WaitCount++;
+
+ DbgInst = XDmaPs_DBGINST0(0, 0x01, ChanIndex, 1);
+ XDmaPs_WriteReg(BaseAddress, XDMAPS_DBGINST0_OFFSET, DbgInst);
+ XDmaPs_WriteReg(BaseAddress, XDMAPS_DBGINST1_OFFSET, 0x0);
+ XDmaPs_WriteReg(BaseAddress, XDMAPS_DBGCMD_OFFSET, 0x0);
+ }
+ /* Kill the manager thread */
+ DbgInst = XDmaPs_DBGINST0(0, 0x01, 0, 0);
+ XDmaPs_WriteReg(BaseAddress, XDMAPS_DBGINST0_OFFSET, DbgInst);
+ XDmaPs_WriteReg(BaseAddress, XDMAPS_DBGINST1_OFFSET, 0x0);
+ XDmaPs_WriteReg(BaseAddress, XDMAPS_DBGCMD_OFFSET, 0x0);
+}
+
+
+
+/** @} */
diff --git a/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/dmaps_v2_5/src/xdmaps_hw.h b/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/dmaps_v2_5/src/xdmaps_hw.h
new file mode 100644
index 0000000..d901a94
--- /dev/null
+++ b/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/dmaps_v2_5/src/xdmaps_hw.h
@@ -0,0 +1,287 @@
+/******************************************************************************
+*
+* Copyright (C) 2009 - 2019 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+* THE SOFTWARE.
+*
+*
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xdmaps_hw.h
+* @addtogroup dmaps_v2_5
+* @{
+*
+* This header file contains the hardware interface of an XDmaPs device.
+*
+* <pre>
+* MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ----- ---- -------- ----------------------------------------------
+* 1.00a hbm 08/18/10 First Release
+* 1.01a nm 12/20/12 Added definition XDMAPS_CHANNELS_PER_DEV which specifies
+* the maximum number of channels.
+* Replaced the usage of XPAR_XDMAPS_CHANNELS_PER_DEV
+* with XDMAPS_CHANNELS_PER_DEV defined in xdmaps_hw.h
+* 1.02a sg 05/16/12 Made changes for doxygen
+* 1.06a kpc 07/10/13 Added function prototype
+* </pre>
+*
+******************************************************************************/
+
+#ifndef XDMAPS_HW_H /* prevent circular inclusions */
+#define XDMAPS_HW_H /* by using protection macros */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/***************************** Include Files *********************************/
+
+#include "xil_types.h"
+#include "xil_assert.h"
+#include "xil_io.h"
+
+/************************** Constant Definitions *****************************/
+
+/** @name Register Map
+ *
+ * Register offsets for the DMAC.
+ * @{
+ */
+
+#define XDMAPS_DS_OFFSET 0x000 /* DMA Status Register */
+#define XDMAPS_DPC_OFFSET 0x004 /* DMA Program Counter Rregister */
+#define XDMAPS_INTEN_OFFSET 0X020 /* DMA Interrupt Enable Register */
+#define XDMAPS_ES_OFFSET 0x024 /* DMA Event Status Register */
+#define XDMAPS_INTSTATUS_OFFSET 0x028 /* DMA Interrupt Status Register
+ */
+#define XDMAPS_INTCLR_OFFSET 0x02c /* DMA Interrupt Clear Register */
+#define XDMAPS_FSM_OFFSET 0x030 /* DMA Fault Status DMA Manager
+ * Register
+ */
+#define XDMAPS_FSC_OFFSET 0x034 /* DMA Fault Status DMA Chanel Register
+ */
+#define XDMAPS_FTM_OFFSET 0x038 /* DMA Fault Type DMA Manager Register */
+
+#define XDMAPS_FTC0_OFFSET 0x040 /* DMA Fault Type for DMA Channel 0 */
+/*
+ * The offset for the rest of the FTC registers is calculated as
+ * FTC0 + dev_chan_num * 4
+ */
+#define XDmaPs_FTCn_OFFSET(ch) (XDMAPS_FTC0_OFFSET + (ch) * 4)
+
+#define XDMAPS_CS0_OFFSET 0x100 /* Channel Status for DMA Channel 0 */
+/*
+ * The offset for the rest of the CS registers is calculated as
+ * CS0 + * dev_chan_num * 0x08
+ */
+#define XDmaPs_CSn_OFFSET(ch) (XDMAPS_CS0_OFFSET + (ch) * 8)
+
+#define XDMAPS_CPC0_OFFSET 0x104 /* Channel Program Counter for DMA
+ * Channel 0
+ */
+/*
+ * The offset for the rest of the CPC registers is calculated as
+ * CPC0 + dev_chan_num * 0x08
+ */
+#define XDmaPs_CPCn_OFFSET(ch) (XDMAPS_CPC0_OFFSET + (ch) * 8)
+
+#define XDMAPS_SA_0_OFFSET 0x400 /* Source Address Register for DMA
+ * Channel 0
+ */
+/* The offset for the rest of the SA registers is calculated as
+ * SA_0 + dev_chan_num * 0x20
+ */
+#define XDmaPs_SA_n_OFFSET(ch) (XDMAPS_SA_0_OFFSET + (ch) * 0x20)
+
+#define XDMAPS_DA_0_OFFSET 0x404 /* Destination Address Register for
+ * DMA Channel 0
+ */
+/* The offset for the rest of the DA registers is calculated as
+ * DA_0 + dev_chan_num * 0x20
+ */
+#define XDmaPs_DA_n_OFFSET(ch) (XDMAPS_DA_0_OFFSET + (ch) * 0x20)
+
+#define XDMAPS_CC_0_OFFSET 0x408 /* Channel Control Register for
+ * DMA Channel 0
+ */
+/*
+ * The offset for the rest of the CC registers is calculated as
+ * CC_0 + dev_chan_num * 0x20
+ */
+#define XDmaPs_CC_n_OFFSET(ch) (XDMAPS_CC_0_OFFSET + (ch) * 0x20)
+
+#define XDMAPS_LC0_0_OFFSET 0x40C /* Loop Counter 0 for DMA Channel 0 */
+/*
+ * The offset for the rest of the LC0 registers is calculated as
+ * LC_0 + dev_chan_num * 0x20
+ */
+#define XDmaPs_LC0_n_OFFSET(ch) (XDMAPS_LC0_0_OFFSET + (ch) * 0x20)
+#define XDMAPS_LC1_0_OFFSET 0x410 /* Loop Counter 1 for DMA Channel 0 */
+/*
+ * The offset for the rest of the LC1 registers is calculated as
+ * LC_0 + dev_chan_num * 0x20
+ */
+#define XDmaPs_LC1_n_OFFSET(ch) (XDMAPS_LC1_0_OFFSET + (ch) * 0x20)
+
+#define XDMAPS_DBGSTATUS_OFFSET 0xD00 /* Debug Status Register */
+#define XDMAPS_DBGCMD_OFFSET 0xD04 /* Debug Command Register */
+#define XDMAPS_DBGINST0_OFFSET 0xD08 /* Debug Instruction 0 Register */
+#define XDMAPS_DBGINST1_OFFSET 0xD0C /* Debug Instruction 1 Register */
+
+#define XDMAPS_CR0_OFFSET 0xE00 /* Configuration Register 0 */
+#define XDMAPS_CR1_OFFSET 0xE04 /* Configuration Register 1 */
+#define XDMAPS_CR2_OFFSET 0xE08 /* Configuration Register 2 */
+#define XDMAPS_CR3_OFFSET 0xE0C /* Configuration Register 3 */
+#define XDMAPS_CR4_OFFSET 0xE10 /* Configuration Register 4 */
+#define XDMAPS_CRDN_OFFSET 0xE14 /* Configuration Register Dn */
+
+#define XDMAPS_PERIPH_ID_0_OFFSET 0xFE0 /* Peripheral Identification
+ * Register 0
+ */
+#define XDMAPS_PERIPH_ID_1_OFFSET 0xFE4 /* Peripheral Identification
+ * Register 1
+ */
+#define XDMAPS_PERIPH_ID_2_OFFSET 0xFE8 /* Peripheral Identification
+ * Register 2
+ */
+#define XDMAPS_PERIPH_ID_3_OFFSET 0xFEC /* Peripheral Identification
+ * Register 3
+ */
+#define XDMAPS_PCELL_ID_0_OFFSET 0xFF0 /* PrimeCell Identification
+ * Register 0
+ */
+#define XDMAPS_PCELL_ID_1_OFFSET 0xFF4 /* PrimeCell Identification
+ * Register 1
+ */
+#define XDMAPS_PCELL_ID_2_OFFSET 0xFF8 /* PrimeCell Identification
+ * Register 2
+ */
+#define XDMAPS_PCELL_ID_3_OFFSET 0xFFC /* PrimeCell Identification
+ * Register 3
+ */
+
+/*
+ * Some useful register masks
+ */
+#define XDMAPS_DS_DMA_STATUS 0x0F /* DMA status mask */
+#define XDMAPS_DS_DMA_STATUS_STOPPED 0x00 /* debug status busy mask */
+
+#define XDMAPS_DBGSTATUS_BUSY 0x01 /* debug status busy mask */
+
+#define XDMAPS_CS_ACTIVE_MASK 0x07 /* channel status active mask,
+ * llast 3 bits of CS register
+ */
+
+#define XDMAPS_CR1_I_CACHE_LEN_MASK 0x07 /* i_cache_len mask */
+
+
+/*
+ * XDMAPS_DBGINST0 - constructs the word for the Debug Instruction-0 Register.
+ * @b1: Instruction byte 1
+ * @b0: Instruction byte 0
+ * @ch: Channel number
+ * @dbg_th: Debug thread encoding: 0 = DMA manager thread, 1 = DMA channel
+ */
+#define XDmaPs_DBGINST0(b1, b0, ch, dbg_th) \
+ (((b1) << 24) | ((b0) << 16) | (((ch) & 0x7) << 8) | ((dbg_th & 0x1)))
+
+/* @} */
+
+/** @name Control Register
+ *
+ * The Control register (CR) controls the major functions of the device.
+ *
+ * Control Register Bit Definition
+ */
+
+/* @}*/
+
+
+#define XDMAPS_CHANNELS_PER_DEV 8
+
+
+/** @name Mode Register
+ *
+ * The mode register (MR) defines the mode of transfer as well as the data
+ * format. If this register is modified during transmission or reception,
+ * data validity cannot be guaranteed.
+ *
+ * Mode Register Bit Definition
+ * @{
+ */
+
+/* @} */
+
+
+/** @name Interrupt Registers
+ *
+ * Interrupt control logic uses the interrupt enable register (IER) and the
+ * interrupt disable register (IDR) to set the value of the bits in the
+ * interrupt mask register (IMR). The IMR determines whether to pass an
+ * interrupt to the interrupt status register (ISR).
+ * Writing a 1 to IER Enbables an interrupt, writing a 1 to IDR disables an
+ * interrupt. IMR and ISR are read only, and IER and IDR are write only.
+ * Reading either IER or IDR returns 0x00.
+ *
+ * All four registers have the same bit definitions.
+ *
+ * @{
+ */
+
+/* @} */
+#define XDMAPS_INTCLR_ALL_MASK 0xFF
+
+#define XDmaPs_ReadReg(BaseAddress, RegOffset) \
+ Xil_In32((BaseAddress) + (RegOffset))
+
+/***************************************************************************/
+/**
+* Write a DMAC register.
+*
+* @param BaseAddress contains the base address of the device.
+* @param RegOffset contains the offset from the base address of the device.
+* @param RegisterValue is the value to be written to the register.
+*
+* @return None.
+*
+* @note
+* C-Style signature:
+* void XDmaPs_WriteReg(u32 BaseAddress, int RegOffset,
+* u32 RegisterValue)
+******************************************************************************/
+#define XDmaPs_WriteReg(BaseAddress, RegOffset, RegisterValue) \
+ Xil_Out32((BaseAddress) + (RegOffset), (RegisterValue))
+/************************** Variable Definitions *****************************/
+
+/************************** Function Prototypes *****************************/
+/*
+ * Perform reset operation to the dmaps interface
+ */
+void XDmaPs_ResetHw(u32 BaseAddr);
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* end of protection macro */
+/** @} */
diff --git a/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/dmaps_v2_5/src/xdmaps_selftest.c b/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/dmaps_v2_5/src/xdmaps_selftest.c
new file mode 100644
index 0000000..ebfbae6
--- /dev/null
+++ b/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/dmaps_v2_5/src/xdmaps_selftest.c
@@ -0,0 +1,104 @@
+/******************************************************************************
+*
+* Copyright (C) 2009 - 2019 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+* THE SOFTWARE.
+*
+*
+*
+******************************************************************************/
+/****************************************************************************/
+/**
+*
+* @file xdmaps_selftest.c
+* @addtogroup dmaps_v2_5
+* @{
+*
+* This file contains the self-test functions for the XDmaPs driver.
+*
+* <pre>
+* MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ----- ------ -------- -----------------------------------------------
+* 1.00 hbm 03/29/2010 First Release
+* </pre>
+*
+******************************************************************************/
+
+/***************************** Include Files *********************************/
+
+#include "xstatus.h"
+#include "xdmaps.h"
+
+/************************** Constant Definitions *****************************/
+
+
+/**************************** Type Definitions *******************************/
+
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+
+/************************** Variable Definitions *****************************/
+
+
+/************************** Function Prototypes ******************************/
+
+
+/****************************************************************************/
+/**
+*
+* This function runs a self-test on the driver and hardware device. This self
+* test performs a local loopback and verifies data can be sent and received.
+*
+* The time for this test is proportional to the baud rate that has been set
+* prior to calling this function.
+*
+* The mode and control registers are restored before return.
+*
+* @param InstPtr is a pointer to the XDmaPs instance
+*
+* @return
+*
+* - XST_SUCCESS if the test was successful
+* - XST_FAILURE if the test failed
+*
+* @note
+*
+* This function can hang if the hardware is not functioning properly.
+*
+******************************************************************************/
+int XDmaPs_SelfTest(XDmaPs *InstPtr)
+{
+ u32 BaseAddr = InstPtr->Config.BaseAddress;
+ int i;
+
+ if (XDmaPs_ReadReg(BaseAddr, XDMAPS_DBGSTATUS_OFFSET)
+ & XDMAPS_DBGSTATUS_BUSY)
+ return XST_FAILURE;
+
+ for (i = 0; i < XDMAPS_CHANNELS_PER_DEV; i++) {
+ if (XDmaPs_ReadReg(BaseAddr,
+ XDmaPs_CSn_OFFSET(i)))
+ return XST_FAILURE;
+ }
+ return XST_SUCCESS;
+}
+/** @} */
diff --git a/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/dmaps_v2_5/src/xdmaps_sinit.c b/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/dmaps_v2_5/src/xdmaps_sinit.c
new file mode 100644
index 0000000..60f3e19
--- /dev/null
+++ b/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/dmaps_v2_5/src/xdmaps_sinit.c
@@ -0,0 +1,98 @@
+/******************************************************************************
+*
+* Copyright (C) 2009 - 2019 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+* THE SOFTWARE.
+*
+*
+*
+******************************************************************************/
+/****************************************************************************/
+/**
+*
+* @file xdmaps_sinit.c
+* @addtogroup dmaps_v2_5
+* @{
+*
+* The implementation of the XDmaPs driver's static initialzation
+* functionality.
+*
+* <pre>
+* MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ----- ---- -------- -----------------------------------------------
+* 1.00 hbm 08/13/10 First Release
+* </pre>
+*
+*****************************************************************************/
+
+/***************************** Include Files ********************************/
+
+#include "xstatus.h"
+#include "xparameters.h"
+#include "xdmaps.h"
+
+/************************** Constant Definitions ****************************/
+
+/**************************** Type Definitions ******************************/
+
+
+/***************** Macros (Inline Functions) Definitions ********************/
+
+
+/************************** Variable Definitions ****************************/
+extern XDmaPs_Config XDmaPs_ConfigTable[];
+
+/************************** Function Prototypes *****************************/
+
+/****************************************************************************/
+/**
+*
+* Looks up the device configuration based on the unique device ID. The table
+* contains the configuration info for each device in the system.
+*
+* @param DeviceId contains the ID of the device
+*
+* @return
+*
+* A pointer to the configuration structure or NULL if the specified device
+* is not in the system.
+*
+* @note
+*
+* None.
+*
+******************************************************************************/
+XDmaPs_Config *XDmaPs_LookupConfig(u16 DeviceId)
+{
+ XDmaPs_Config *CfgPtr = NULL;
+
+ int i;
+
+ for (i = 0; i < XPAR_XDMAPS_NUM_INSTANCES; i++) {
+ if (XDmaPs_ConfigTable[i].DeviceId == DeviceId) {
+ CfgPtr = &XDmaPs_ConfigTable[i];
+ break;
+ }
+ }
+
+ return CfgPtr;
+}
+/** @} */
diff --git a/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/emacps_v3_10/src/Makefile b/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/emacps_v3_10/src/Makefile
new file mode 100644
index 0000000..7002e62
--- /dev/null
+++ b/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/emacps_v3_10/src/Makefile
@@ -0,0 +1,40 @@
+COMPILER=
+ARCHIVER=
+CP=cp
+COMPILER_FLAGS=
+EXTRA_COMPILER_FLAGS=
+LIB=libxil.a
+
+CC_FLAGS = $(COMPILER_FLAGS)
+ECC_FLAGS = $(EXTRA_COMPILER_FLAGS)
+
+RELEASEDIR=../../../lib
+INCLUDEDIR=../../../include
+INCLUDES=-I./. -I${INCLUDEDIR}
+
+OUTS = *.o
+
+LIBSOURCES:=*.c
+INCLUDEFILES:=*.h
+
+OBJECTS = $(addsuffix .o, $(basename $(wildcard *.c)))
+
+libs: banner xemacps_libs clean
+
+%.o: %.c
+ ${COMPILER} $(CC_FLAGS) $(ECC_FLAGS) $(INCLUDES) -o $@ $<
+
+banner:
+ echo "Compiling emacps"
+
+xemacps_libs: ${OBJECTS}
+ $(ARCHIVER) -r ${RELEASEDIR}/${LIB} ${OBJECTS}
+
+.PHONY: include
+include: xemacps_includes
+
+xemacps_includes:
+ ${CP} ${INCLUDEFILES} ${INCLUDEDIR}
+
+clean:
+ rm -rf ${OBJECTS}
diff --git a/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/emacps_v3_10/src/xemacps.c b/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/emacps_v3_10/src/xemacps.c
new file mode 100644
index 0000000..659afe7
--- /dev/null
+++ b/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/emacps_v3_10/src/xemacps.c
@@ -0,0 +1,487 @@
+/******************************************************************************
+*
+* Copyright (C) 2010 - 2019 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+* THE SOFTWARE.
+*
+*
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xemacps.c
+* @addtogroup emacps_v3_10
+* @{
+*
+* The XEmacPs driver. Functions in this file are the minimum required functions
+* for this driver. See xemacps.h for a detailed description of the driver.
+*
+* <pre>
+* MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ----- ---- -------- -------------------------------------------------------
+* 1.00a wsy 01/10/10 First release
+* 2.1 srt 07/15/14 Add support for Zynq Ultrascale Mp GEM specification and
+* 64-bit changes.
+* 3.00 kvn 02/13/15 Modified code for MISRA-C:2012 compliance.
+* 3.0 hk 02/20/15 Added support for jumbo frames. Increase AHB burst.
+* Disable extended mode. Perform all 64 bit changes under
+* check for arch64.
+* 3.1 hk 08/10/15 Update upper 32 bit tx and rx queue ptr registers
+* 3.5 hk 08/14/17 Update cache coherency information of the interface in
+* its config structure.
+* 3.8 hk 09/17/18 Cleanup stale comments.
+* 3.8 mus 11/05/18 Support 64 bit DMA addresses for Microblaze-X platform.
+* 3.10 hk 05/16/19 Clear status registers properly in reset
+*
+* </pre>
+******************************************************************************/
+
+/***************************** Include Files *********************************/
+
+#include "xemacps.h"
+
+/************************** Constant Definitions *****************************/
+
+
+/**************************** Type Definitions *******************************/
+
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+
+/************************** Function Prototypes ******************************/
+
+void XEmacPs_StubHandler(void); /* Default handler routine */
+
+/************************** Variable Definitions *****************************/
+
+
+/*****************************************************************************/
+/**
+* Initialize a specific XEmacPs instance/driver. The initialization entails:
+* - Initialize fields of the XEmacPs instance structure
+* - Reset hardware and apply default options
+* - Configure the DMA channels
+*
+* The PHY is setup independently from the device. Use the MII or whatever other
+* interface may be present for setup.
+*
+* @param InstancePtr is a pointer to the instance to be worked on.
+* @param CfgPtr is the device configuration structure containing required
+* hardware build data.
+* @param EffectiveAddress is the base address of the device. If address
+* translation is not utilized, this parameter can be passed in using
+* CfgPtr->Config.BaseAddress to specify the physical base address.
+*
+* @return
+* - XST_SUCCESS if initialization was successful
+*
+******************************************************************************/
+LONG XEmacPs_CfgInitialize(XEmacPs *InstancePtr, XEmacPs_Config * CfgPtr,
+ UINTPTR EffectiveAddress)
+{
+ /* Verify arguments */
+ Xil_AssertNonvoid(InstancePtr != NULL);
+ Xil_AssertNonvoid(CfgPtr != NULL);
+
+ /* Set device base address and ID */
+ InstancePtr->Config.DeviceId = CfgPtr->DeviceId;
+ InstancePtr->Config.BaseAddress = EffectiveAddress;
+ InstancePtr->Config.IsCacheCoherent = CfgPtr->IsCacheCoherent;
+
+ /* Set callbacks to an initial stub routine */
+ InstancePtr->SendHandler = ((XEmacPs_Handler)((void*)XEmacPs_StubHandler));
+ InstancePtr->RecvHandler = ((XEmacPs_Handler)(void*)XEmacPs_StubHandler);
+ InstancePtr->ErrorHandler = ((XEmacPs_ErrHandler)(void*)XEmacPs_StubHandler);
+
+ /* Reset the hardware and set default options */
+ InstancePtr->IsReady = XIL_COMPONENT_IS_READY;
+ XEmacPs_Reset(InstancePtr);
+
+ return (LONG)(XST_SUCCESS);
+}
+
+
+/*****************************************************************************/
+/**
+* Start the Ethernet controller as follows:
+* - Enable transmitter if XTE_TRANSMIT_ENABLE_OPTION is set
+* - Enable receiver if XTE_RECEIVER_ENABLE_OPTION is set
+* - Start the SG DMA send and receive channels and enable the device
+* interrupt
+*
+* @param InstancePtr is a pointer to the instance to be worked on.
+*
+* @return N/A
+*
+* @note
+* Hardware is configured with scatter-gather DMA, the driver expects to start
+* the scatter-gather channels and expects that the user has previously set up
+* the buffer descriptor lists.
+*
+* This function makes use of internal resources that are shared between the
+* Start, Stop, and Set/ClearOptions functions. So if one task might be setting
+* device options while another is trying to start the device, the user is
+* required to provide protection of this shared data (typically using a
+* semaphore).
+*
+* This function must not be preempted by an interrupt that may service the
+* device.
+*
+******************************************************************************/
+void XEmacPs_Start(XEmacPs *InstancePtr)
+{
+ u32 Reg;
+
+ /* Assert bad arguments and conditions */
+ Xil_AssertVoid(InstancePtr != NULL);
+ Xil_AssertVoid(InstancePtr->IsReady == (u32)XIL_COMPONENT_IS_READY);
+
+ /* Start DMA */
+ /* When starting the DMA channels, both transmit and receive sides
+ * need an initialized BD list.
+ */
+ if (InstancePtr->Version == 2) {
+ Xil_AssertVoid(InstancePtr->RxBdRing.BaseBdAddr != 0);
+ Xil_AssertVoid(InstancePtr->TxBdRing.BaseBdAddr != 0);
+ XEmacPs_WriteReg(InstancePtr->Config.BaseAddress,
+ XEMACPS_RXQBASE_OFFSET,
+ InstancePtr->RxBdRing.BaseBdAddr);
+
+ XEmacPs_WriteReg(InstancePtr->Config.BaseAddress,
+ XEMACPS_TXQBASE_OFFSET,
+ InstancePtr->TxBdRing.BaseBdAddr);
+ }
+
+ /* clear any existed int status */
+ XEmacPs_WriteReg(InstancePtr->Config.BaseAddress, XEMACPS_ISR_OFFSET,
+ XEMACPS_IXR_ALL_MASK);
+
+ /* Enable transmitter if not already enabled */
+ if ((InstancePtr->Options & (u32)XEMACPS_TRANSMITTER_ENABLE_OPTION)!=0x00000000U) {
+ Reg = XEmacPs_ReadReg(InstancePtr->Config.BaseAddress,
+ XEMACPS_NWCTRL_OFFSET);
+ if ((!(Reg & XEMACPS_NWCTRL_TXEN_MASK))==TRUE) {
+ XEmacPs_WriteReg(InstancePtr->Config.BaseAddress,
+ XEMACPS_NWCTRL_OFFSET,
+ Reg | (u32)XEMACPS_NWCTRL_TXEN_MASK);
+ }
+ }
+
+ /* Enable receiver if not already enabled */
+ if ((InstancePtr->Options & XEMACPS_RECEIVER_ENABLE_OPTION) != 0x00000000U) {
+ Reg = XEmacPs_ReadReg(InstancePtr->Config.BaseAddress,
+ XEMACPS_NWCTRL_OFFSET);
+ if ((!(Reg & XEMACPS_NWCTRL_RXEN_MASK))==TRUE) {
+ XEmacPs_WriteReg(InstancePtr->Config.BaseAddress,
+ XEMACPS_NWCTRL_OFFSET,
+ Reg | (u32)XEMACPS_NWCTRL_RXEN_MASK);
+ }
+ }
+
+ /* Enable TX and RX interrupts */
+ XEmacPs_IntEnable(InstancePtr, (XEMACPS_IXR_TX_ERR_MASK |
+ XEMACPS_IXR_RX_ERR_MASK | (u32)XEMACPS_IXR_FRAMERX_MASK |
+ (u32)XEMACPS_IXR_TXCOMPL_MASK));
+
+ /* Enable TX Q1 Interrupts */
+ if (InstancePtr->Version > 2)
+ XEmacPs_IntQ1Enable(InstancePtr, XEMACPS_INTQ1_IXR_ALL_MASK);
+
+ /* Mark as started */
+ InstancePtr->IsStarted = XIL_COMPONENT_IS_STARTED;
+
+ return;
+}
+
+
+/*****************************************************************************/
+/**
+* Gracefully stop the Ethernet MAC as follows:
+* - Disable all interrupts from this device
+* - Stop DMA channels
+* - Disable the tansmitter and receiver
+*
+* Device options currently in effect are not changed.
+*
+* This function will disable all interrupts. Default interrupts settings that
+* had been enabled will be restored when XEmacPs_Start() is called.
+*
+* @param InstancePtr is a pointer to the instance to be worked on.
+*
+* @note
+* This function makes use of internal resources that are shared between the
+* Start, Stop, SetOptions, and ClearOptions functions. So if one task might be
+* setting device options while another is trying to start the device, the user
+* is required to provide protection of this shared data (typically using a
+* semaphore).
+*
+* Stopping the DMA channels causes this function to block until the DMA
+* operation is complete.
+*
+******************************************************************************/
+void XEmacPs_Stop(XEmacPs *InstancePtr)
+{
+ u32 Reg;
+
+ Xil_AssertVoid(InstancePtr != NULL);
+ Xil_AssertVoid(InstancePtr->IsReady == (u32)XIL_COMPONENT_IS_READY);
+
+ /* Disable all interrupts */
+ XEmacPs_WriteReg(InstancePtr->Config.BaseAddress, XEMACPS_IDR_OFFSET,
+ XEMACPS_IXR_ALL_MASK);
+
+ /* Disable the receiver & transmitter */
+ Reg = XEmacPs_ReadReg(InstancePtr->Config.BaseAddress,
+ XEMACPS_NWCTRL_OFFSET);
+ Reg &= (u32)(~XEMACPS_NWCTRL_RXEN_MASK);
+ Reg &= (u32)(~XEMACPS_NWCTRL_TXEN_MASK);
+ XEmacPs_WriteReg(InstancePtr->Config.BaseAddress,
+ XEMACPS_NWCTRL_OFFSET, Reg);
+
+ /* Mark as stopped */
+ InstancePtr->IsStarted = 0U;
+}
+
+
+/*****************************************************************************/
+/**
+* Perform a graceful reset of the Ethernet MAC. Resets the DMA channels, the
+* transmitter, and the receiver.
+*
+* Steps to reset
+* - Stops transmit and receive channels
+* - Stops DMA
+* - Configure transmit and receive buffer size to default
+* - Clear transmit and receive status register and counters
+* - Clear all interrupt sources
+* - Clear phy (if there is any previously detected) address
+* - Clear MAC addresses (1-4) as well as Type IDs and hash value
+*
+* All options are placed in their default state. Any frames in the
+* descriptor lists will remain in the lists. The side effect of doing
+* this is that after a reset and following a restart of the device, frames
+* were in the list before the reset may be transmitted or received.
+*
+* The upper layer software is responsible for re-configuring (if necessary)
+* and restarting the MAC after the reset. Note also that driver statistics
+* are not cleared on reset. It is up to the upper layer software to clear the
+* statistics if needed.
+*
+* When a reset is required, the driver notifies the upper layer software of
+* this need through the ErrorHandler callback and specific status codes.
+* The upper layer software is responsible for calling this Reset function
+* and then re-configuring the device.
+*
+* @param InstancePtr is a pointer to the instance to be worked on.
+*
+******************************************************************************/
+void XEmacPs_Reset(XEmacPs *InstancePtr)
+{
+ u32 Reg;
+ u8 i;
+ s8 EmacPs_zero_MAC[6] = { 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 };
+
+ Xil_AssertVoid(InstancePtr != NULL);
+ Xil_AssertVoid(InstancePtr->IsReady == (u32)XIL_COMPONENT_IS_READY);
+
+ /* Stop the device and reset hardware */
+ XEmacPs_Stop(InstancePtr);
+ InstancePtr->Options = XEMACPS_DEFAULT_OPTIONS;
+
+ InstancePtr->Version = XEmacPs_ReadReg(InstancePtr->Config.BaseAddress, 0xFC);
+
+ InstancePtr->Version = (InstancePtr->Version >> 16) & 0xFFF;
+
+ InstancePtr->MaxMtuSize = XEMACPS_MTU;
+ InstancePtr->MaxFrameSize = XEMACPS_MTU + XEMACPS_HDR_SIZE +
+ XEMACPS_TRL_SIZE;
+ InstancePtr->MaxVlanFrameSize = InstancePtr->MaxFrameSize +
+ XEMACPS_HDR_VLAN_SIZE;
+ InstancePtr->RxBufMask = XEMACPS_RXBUF_LEN_MASK;
+
+ /* Setup hardware with default values */
+ XEmacPs_WriteReg(InstancePtr->Config.BaseAddress,
+ XEMACPS_NWCTRL_OFFSET,
+ (XEMACPS_NWCTRL_STATCLR_MASK |
+ XEMACPS_NWCTRL_MDEN_MASK) &
+ (u32)(~XEMACPS_NWCTRL_LOOPEN_MASK));
+
+ Reg = XEmacPs_ReadReg(InstancePtr->Config.BaseAddress,
+ XEMACPS_NWCFG_OFFSET);
+ Reg &= XEMACPS_NWCFG_MDCCLKDIV_MASK;
+
+ Reg = Reg | (u32)XEMACPS_NWCFG_100_MASK |
+ (u32)XEMACPS_NWCFG_FDEN_MASK |
+ (u32)XEMACPS_NWCFG_UCASTHASHEN_MASK;
+
+ XEmacPs_WriteReg(InstancePtr->Config.BaseAddress,
+ XEMACPS_NWCFG_OFFSET, Reg);
+ if (InstancePtr->Version > 2) {
+ XEmacPs_WriteReg(InstancePtr->Config.BaseAddress, XEMACPS_NWCFG_OFFSET,
+ (XEmacPs_ReadReg(InstancePtr->Config.BaseAddress, XEMACPS_NWCFG_OFFSET) |
+ XEMACPS_NWCFG_DWIDTH_64_MASK));
+ }
+
+ XEmacPs_WriteReg(InstancePtr->Config.BaseAddress,
+ XEMACPS_DMACR_OFFSET,
+ (((((u32)XEMACPS_RX_BUF_SIZE / (u32)XEMACPS_RX_BUF_UNIT) +
+ (((((u32)XEMACPS_RX_BUF_SIZE %
+ (u32)XEMACPS_RX_BUF_UNIT))!=(u32)0) ? 1U : 0U)) <<
+ (u32)(XEMACPS_DMACR_RXBUF_SHIFT)) &
+ (u32)(XEMACPS_DMACR_RXBUF_MASK)) |
+ (u32)XEMACPS_DMACR_RXSIZE_MASK |
+ (u32)XEMACPS_DMACR_TXSIZE_MASK);
+
+
+ if (InstancePtr->Version > 2) {
+ XEmacPs_WriteReg(InstancePtr->Config.BaseAddress, XEMACPS_DMACR_OFFSET,
+ (XEmacPs_ReadReg(InstancePtr->Config.BaseAddress, XEMACPS_DMACR_OFFSET) |
+#if defined(__aarch64__) || defined(__arch64__)
+ (u32)XEMACPS_DMACR_ADDR_WIDTH_64 |
+#endif
+ (u32)XEMACPS_DMACR_INCR16_AHB_BURST));
+ }
+
+ XEmacPs_WriteReg(InstancePtr->Config.BaseAddress,
+ XEMACPS_TXSR_OFFSET, XEMACPS_SR_ALL_MASK);
+
+ XEmacPs_SetQueuePtr(InstancePtr, 0, 0x00U, (u16)XEMACPS_SEND);
+ if (InstancePtr->Version > 2)
+ XEmacPs_SetQueuePtr(InstancePtr, 0, 0x01U, (u16)XEMACPS_SEND);
+ XEmacPs_SetQueuePtr(InstancePtr, 0, 0x00U, (u16)XEMACPS_RECV);
+
+ XEmacPs_WriteReg(InstancePtr->Config.BaseAddress,
+ XEMACPS_RXSR_OFFSET, XEMACPS_SR_ALL_MASK);
+
+ XEmacPs_WriteReg(InstancePtr->Config.BaseAddress, XEMACPS_IDR_OFFSET,
+ XEMACPS_IXR_ALL_MASK);
+
+ Reg = XEmacPs_ReadReg(InstancePtr->Config.BaseAddress,
+ XEMACPS_ISR_OFFSET);
+ XEmacPs_WriteReg(InstancePtr->Config.BaseAddress, XEMACPS_ISR_OFFSET,
+ Reg);
+
+ XEmacPs_ClearHash(InstancePtr);
+
+ for (i = 1U; i < 5U; i++) {
+ (void)XEmacPs_SetMacAddress(InstancePtr, EmacPs_zero_MAC, i);
+ (void)XEmacPs_SetTypeIdCheck(InstancePtr, 0x00000000U, i);
+ }
+
+ /* clear all counters */
+ for (i = 0U; i < (u8)((XEMACPS_LAST_OFFSET - XEMACPS_OCTTXL_OFFSET) / 4U);
+ i++) {
+ (void)XEmacPs_ReadReg(InstancePtr->Config.BaseAddress,
+ XEMACPS_OCTTXL_OFFSET + (u32)(((u32)i) * ((u32)4)));
+ }
+
+ /* Disable the receiver */
+ Reg = XEmacPs_ReadReg(InstancePtr->Config.BaseAddress,
+ XEMACPS_NWCTRL_OFFSET);
+ Reg &= (u32)(~XEMACPS_NWCTRL_RXEN_MASK);
+ XEmacPs_WriteReg(InstancePtr->Config.BaseAddress,
+ XEMACPS_NWCTRL_OFFSET, Reg);
+
+ /* Sync default options with hardware but leave receiver and
+ * transmitter disabled. They get enabled with XEmacPs_Start() if
+ * XEMACPS_TRANSMITTER_ENABLE_OPTION and
+ * XEMACPS_RECEIVER_ENABLE_OPTION are set.
+ */
+ (void)XEmacPs_SetOptions(InstancePtr, InstancePtr->Options &
+ ~((u32)XEMACPS_TRANSMITTER_ENABLE_OPTION |
+ (u32)XEMACPS_RECEIVER_ENABLE_OPTION));
+
+ (void)XEmacPs_ClearOptions(InstancePtr, ~InstancePtr->Options);
+}
+
+
+/******************************************************************************/
+/**
+ * This is a stub for the asynchronous callbacks. The stub is here in case the
+ * upper layer forgot to set the handler(s). On initialization, all handlers are
+ * set to this callback. It is considered an error for this handler to be
+ * invoked.
+ *
+ ******************************************************************************/
+void XEmacPs_StubHandler(void)
+{
+ Xil_AssertVoidAlways();
+}
+
+/*****************************************************************************/
+/**
+* This function sets the start address of the transmit/receive buffer queue.
+*
+* @param InstancePtr is a pointer to the instance to be worked on.
+* @param QPtr is the address of the Queue to be written
+* @param QueueNum is the Buffer Queue Index
+* @param Direction indicates Transmit/Receive
+*
+* @note
+* The buffer queue addresses has to be set before starting the transfer, so
+* this function has to be called in prior to XEmacPs_Start()
+*
+******************************************************************************/
+void XEmacPs_SetQueuePtr(XEmacPs *InstancePtr, UINTPTR QPtr, u8 QueueNum,
+ u16 Direction)
+{
+ /* Assert bad arguments and conditions */
+ Xil_AssertVoid(InstancePtr != NULL);
+ Xil_AssertVoid(InstancePtr->IsReady == (u32)XIL_COMPONENT_IS_READY);
+
+ /* If already started, then there is nothing to do */
+ if (InstancePtr->IsStarted == (u32)XIL_COMPONENT_IS_STARTED) {
+ return;
+ }
+
+ if (QueueNum == 0x00U) {
+ if (Direction == XEMACPS_SEND) {
+ XEmacPs_WriteReg(InstancePtr->Config.BaseAddress,
+ XEMACPS_TXQBASE_OFFSET,
+ (QPtr & ULONG64_LO_MASK));
+ } else {
+ XEmacPs_WriteReg(InstancePtr->Config.BaseAddress,
+ XEMACPS_RXQBASE_OFFSET,
+ (QPtr & ULONG64_LO_MASK));
+ }
+ }
+ else {
+ XEmacPs_WriteReg(InstancePtr->Config.BaseAddress,
+ XEMACPS_TXQ1BASE_OFFSET,
+ (QPtr & ULONG64_LO_MASK));
+ }
+#ifdef __aarch64__
+ if (Direction == XEMACPS_SEND) {
+ /* Set the MSB of TX Queue start address */
+ XEmacPs_WriteReg(InstancePtr->Config.BaseAddress,
+ XEMACPS_MSBBUF_TXQBASE_OFFSET,
+ (u32)((QPtr & ULONG64_HI_MASK) >> 32U));
+ } else {
+ /* Set the MSB of RX Queue start address */
+ XEmacPs_WriteReg(InstancePtr->Config.BaseAddress,
+ XEMACPS_MSBBUF_RXQBASE_OFFSET,
+ (u32)((QPtr & ULONG64_HI_MASK) >> 32U));
+ }
+#endif
+}
+/** @} */
diff --git a/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/emacps_v3_10/src/xemacps.h b/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/emacps_v3_10/src/xemacps.h
new file mode 100644
index 0000000..3943595
--- /dev/null
+++ b/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/emacps_v3_10/src/xemacps.h
@@ -0,0 +1,849 @@
+/******************************************************************************
+*
+* Copyright (C) 2010 - 2019 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+* THE SOFTWARE.
+*
+*
+*
+******************************************************************************/
+/****************************************************************************/
+/**
+ *
+ * @file xemacps.h
+* @addtogroup emacps_v3_10
+* @{
+* @details
+ *
+ * The Xilinx Embedded Processor Block Ethernet driver.
+ *
+ * For a full description of XEMACPS features, please see the hardware spec.
+ * This driver supports the following features:
+ * - Memory mapped access to host interface registers
+ * - Statistics counter registers for RMON/MIB
+ * - API for interrupt driven frame transfers for hardware configured DMA
+ * - Virtual memory support
+ * - Unicast, broadcast, and multicast receive address filtering
+ * - Full and half duplex operation
+ * - Automatic PAD & FCS insertion and stripping
+ * - Flow control
+ * - Support up to four 48bit addresses
+ * - Address checking for four specific 48bit addresses
+ * - VLAN frame support
+ * - Pause frame support
+ * - Large frame support up to 1536 bytes
+ * - Checksum offload
+ *
+ * <b>Driver Description</b>
+ *
+ * The device driver enables higher layer software (e.g., an application) to
+ * communicate to the XEmacPs. The driver handles transmission and reception
+ * of Ethernet frames, as well as configuration and control. No pre or post
+ * processing of frame data is performed. The driver does not validate the
+ * contents of an incoming frame in addition to what has already occurred in
+ * hardware.
+ * A single device driver can support multiple devices even when those devices
+ * have significantly different configurations.
+ *
+ * <b>Initialization & Configuration</b>
+ *
+ * The XEmacPs_Config structure is used by the driver to configure itself.
+ * This configuration structure is typically created by the tool-chain based
+ * on hardware build properties.
+ *
+ * The driver instance can be initialized in
+ *
+ * - XEmacPs_CfgInitialize(InstancePtr, CfgPtr, EffectiveAddress): Uses a
+ * configuration structure provided by the caller. If running in a system
+ * with address translation, the provided virtual memory base address
+ * replaces the physical address present in the configuration structure.
+ *
+ * The device supports DMA only as current development plan. No FIFO mode is
+ * supported. The driver expects to start the DMA channels and expects that
+ * the user has set up the buffer descriptor lists.
+ *
+ * <b>Interrupts and Asynchronous Callbacks</b>
+ *
+ * The driver has no dependencies on the interrupt controller. When an
+ * interrupt occurs, the handler will perform a small amount of
+ * housekeeping work, determine the source of the interrupt, and call the
+ * appropriate callback function. All callbacks are registered by the user
+ * level application.
+ *
+ * <b>Virtual Memory</b>
+ *
+ * All virtual to physical memory mappings must occur prior to accessing the
+ * driver API.
+ *
+ * For DMA transactions, user buffers supplied to the driver must be in terms
+ * of their physical address.
+ *
+ * <b>DMA</b>
+ *
+ * The DMA engine uses buffer descriptors (BDs) to describe Ethernet frames.
+ * These BDs are typically chained together into a list the hardware follows
+ * when transferring data in and out of the packet buffers. Each BD describes
+ * a memory region containing either a full or partial Ethernet packet.
+ *
+ * Interrupt coalescing is not supported from this built-in DMA engine.
+ *
+ * This API requires the user to understand how the DMA operates. The
+ * following paragraphs provide some explanation, but the user is encouraged
+ * to read documentation in xemacps_bdring.h as well as study example code
+ * that accompanies this driver.
+ *
+ * The API is designed to get BDs to and from the DMA engine in the most
+ * efficient means possible. The first step is to establish a memory region
+ * to contain all BDs for a specific channel. This is done with
+ * XEmacPs_BdRingCreate(). This function sets up a BD ring that hardware will
+ * follow as BDs are processed. The ring will consist of a user defined number
+ * of BDs which will all be partially initialized. For example on the transmit
+ * channel, the driver will initialize all BDs' so that they are configured
+ * for transmit. The more fields that can be permanently setup at
+ * initialization, then the fewer accesses will be needed to each BD while
+ * the DMA engine is in operation resulting in better throughput and CPU
+ * utilization. The best case initialization would require the user to set
+ * only a frame buffer address and length prior to submitting the BD to the
+ * engine.
+ *
+ * BDs move through the engine with the help of functions
+ * XEmacPs_BdRingAlloc(), XEmacPs_BdRingToHw(), XEmacPs_BdRingFromHw(),
+ * and XEmacPs_BdRingFree().
+ * All these functions handle BDs that are in place. That is, there are no
+ * copies of BDs kept anywhere and any BD the user interacts with is an actual
+ * BD from the same ring hardware accesses.
+ *
+ * BDs in the ring go through a series of states as follows:
+ * 1. Idle. The driver controls BDs in this state.
+ * 2. The user has data to transfer. XEmacPs_BdRingAlloc() is called to
+ * reserve BD(s). Once allocated, the user may setup the BD(s) with
+ * frame buffer address, length, and other attributes. The user controls
+ * BDs in this state.
+ * 3. The user submits BDs to the DMA engine with XEmacPs_BdRingToHw. BDs
+ * in this state are either waiting to be processed by hardware, are in
+ * process, or have been processed. The DMA engine controls BDs in this
+ * state.
+ * 4. Processed BDs are retrieved with XEmacEpv_BdRingFromHw() by the
+ * user. Once retrieved, the user can examine each BD for the outcome of
+ * the DMA transfer. The user controls BDs in this state. After examining
+ * the BDs the user calls XEmacPs_BdRingFree() which places the BDs back
+ * into state 1.
+ *
+ * Each of the four BD accessor functions operate on a set of BDs. A set is
+ * defined as a segment of the BD ring consisting of one or more BDs. The user
+ * views the set as a pointer to the first BD along with the number of BDs for
+ * that set. The set can be navigated by using macros XEmacPs_BdNext(). The
+ * user must exercise extreme caution when changing BDs in a set as there is
+ * nothing to prevent doing a mBdNext past the end of the set and modifying a
+ * BD out of bounds.
+ *
+ * XEmacPs_BdRingAlloc() + XEmacPs_BdRingToHw(), as well as
+ * XEmacPs_BdRingFromHw() + XEmacPs_BdRingFree() are designed to be used in
+ * tandem. The same BD set retrieved with BdRingAlloc should be the same one
+ * provided to hardware with BdRingToHw. Same goes with BdRingFromHw and
+ * BdRIngFree.
+ *
+ * <b>Alignment & Data Cache Restrictions</b>
+ *
+ * Due to the design of the hardware, all RX buffers, BDs need to be 4-byte
+ * aligned. Please reference xemacps_bd.h for cache related macros.
+ *
+ * DMA Tx:
+ *
+ * - If frame buffers exist in cached memory, then they must be flushed
+ * prior to committing them to hardware.
+ *
+ * DMA Rx:
+ *
+ * - If frame buffers exist in cached memory, then the cache must be
+ * invalidated for the memory region containing the frame prior to data
+ * access
+ *
+ * Both cache invalidate/flush are taken care of in driver code.
+ *
+ * <b>Buffer Copying</b>
+ *
+ * The driver is designed for a zero-copy buffer scheme. That is, the driver
+ * will not copy buffers. This avoids potential throughput bottlenecks within
+ * the driver. If byte copying is required, then the transfer will take longer
+ * to complete.
+ *
+ * <b>Checksum Offloading</b>
+ *
+ * The Embedded Processor Block Ethernet can be configured to perform IP, TCP
+ * and UDP checksum offloading in both receive and transmit directions.
+ *
+ * IP packets contain a 16-bit checksum field, which is the 16-bit 1s
+ * complement of the 1s complement sum of all 16-bit words in the header.
+ * TCP and UDP packets contain a 16-bit checksum field, which is the 16-bit
+ * 1s complement of the 1s complement sum of all 16-bit words in the header,
+ * the data and a conceptual pseudo header.
+ *
+ * To calculate these checksums in software requires each byte of the packet
+ * to be read. For TCP and UDP this can use a large amount of processing power.
+ * Offloading the checksum calculation to hardware can result in significant
+ * performance improvements.
+ *
+ * The transmit checksum offload is only available to use DMA in packet buffer
+ * mode. This is because the complete frame to be transmitted must be read
+ * into the packet buffer memory before the checksum can be calculated and
+ * written to the header at the beginning of the frame.
+ *
+ * For IP, TCP or UDP receive checksum offload to be useful, the operating
+ * system containing the protocol stack must be aware that this offload is
+ * available so that it can make use of the fact that the hardware has verified
+ * the checksum.
+ *
+ * When receive checksum offloading is enabled in the hardware, the IP header
+ * checksum is checked, where the packet meets the following criteria:
+ *
+ * 1. If present, the VLAN header must be four octets long and the CFI bit
+ * must not be set.
+ * 2. Encapsulation must be RFC 894 Ethernet Type Encoding or RFC 1042 SNAP
+ * encoding.
+ * 3. IP v4 packet.
+ * 4. IP header is of a valid length.
+ * 5. Good IP header checksum.
+ * 6. No IP fragmentation.
+ * 7. TCP or UDP packet.
+ *
+ * When an IP, TCP or UDP frame is received, the receive buffer descriptor
+ * gives an indication if the hardware was able to verify the checksums.
+ * There is also an indication if the frame had SNAP encapsulation. These
+ * indication bits will replace the type ID match indication bits when the
+ * receive checksum offload is enabled.
+ *
+ * If any of the checksums are verified incorrect by the hardware, the packet
+ * is discarded and the appropriate statistics counter incremented.
+ *
+ * <b>PHY Interfaces</b>
+ *
+ * RGMII 1.3 is the only interface supported.
+ *
+ * <b>Asserts</b>
+ *
+ * Asserts are used within all Xilinx drivers to enforce constraints on
+ * parameters. Asserts can be turned off on a system-wide basis by defining,
+ * at compile time, the NDEBUG identifier. By default, asserts are turned on
+ * and it is recommended that users leave asserts on during development. For
+ * deployment use -DNDEBUG compiler switch to remove assert code.
+ *
+ * @note
+ *
+ * Xilinx drivers are typically composed of two parts, one is the driver
+ * and the other is the adapter. The driver is independent of OS and processor
+ * and is intended to be highly portable. The adapter is OS-specific and
+ * facilitates communication between the driver and an OS.
+ * This driver is intended to be RTOS and processor independent. Any needs for
+ * dynamic memory management, threads or thread mutual exclusion, or cache
+ * control must be satisfied bythe layer above this driver.
+ *
+ * <pre>
+ * MODIFICATION HISTORY:
+ *
+ * Ver Who Date Changes
+ * ----- ---- -------- -------------------------------------------------------
+ * 1.00a wsy 01/10/10 First release
+ * 1.00a asa 11/21/11 The function XEmacPs_BdRingFromHwTx in file
+ * xemacps_bdring.c is modified. Earlier it was checking for
+ * "BdLimit"(passed argument) number of BDs for finding out
+ * which BDs are successfully processed. Now one more check
+ * is added. It looks for BDs till the current BD pointer
+ * reaches HwTail. By doing this processing time is saved.
+ * 1.00a asa 01/24/12 The function XEmacPs_BdRingFromHwTx in file
+ * xemacps_bdring.c is modified. Now start of packet is
+ * searched for returning the number of BDs processed.
+ * 1.02a asa 11/05/12 Added a new API for deleting an entry from the HASH
+ * registers. Added a new API to set the bust length.
+ * Added some new hash-defines.
+ * 1.03a asa 01/23/12 Fix for CR #692702 which updates error handling for
+ * Rx errors. Under heavy Rx traffic, there will be a large
+ * number of errors related to receive buffer not available.
+ * Because of a HW bug (SI #692601), under such heavy errors,
+ * the Rx data path can become unresponsive. To reduce the
+ * probabilities for hitting this HW bug, the SW writes to
+ * bit 18 to flush a packet from Rx DPRAM immediately. The
+ * changes for it are done in the function
+ * XEmacPs_IntrHandler.
+ * 1.05a asa 09/23/13 Cache operations on BDs are not required and hence
+ * removed. It is expected that all BDs are allocated in
+ * from uncached area.
+ * 1.06a asa 11/02/13 Changed the value for XEMACPS_RXBUF_LEN_MASK from 0x3fff
+ * to 0x1fff. This fixes the CR#744902.
+ * Made changes in example file xemacps_example.h to fix compilation
+ * issues with iarcc compiler.
+ * 2.0 adk 10/12/13 Updated as per the New Tcl API's
+ * 2.1 adk 11/08/14 Fixed the CR#811288. Changes are made in the driver tcl file.
+ * 2.1 bss 09/08/14 Modified driver tcl to fix CR#820349 to export phy
+ * address in xparameters.h when GMII to RGMII converter
+ * is present in hw.
+ * 2.1 srt 07/15/14 Add support for Zynq Ultrascale Mp GEM specification and 64-bit
+ * changes.
+ * 2.2 adk 29/10/14 Fixed CR#827686 when PCS/PMA core is configured with
+ * 1000BASE-X mode export proper values to the xparameters.h
+ * file. Changes are made in the driver tcl file.
+ * 3.0 adk 08/1/15 Don't include gem in peripheral test when gem is
+ * configured with PCS/PMA Core. Changes are made in the
+ * test app tcl(CR:827686).
+ * 3.0 kvn 02/13/15 Modified code for MISRA-C:2012 compliance.
+ * 3.0 hk 03/18/15 Added support for jumbo frames. Increase AHB burst.
+ * Disable extended mode. Perform all 64 bit changes under
+ * check for arch64.
+ * Remove "used bit set" from TX error interrupt masks.
+ * 3.1 hk 07/27/15 Do not call error handler with '0' error code when
+ * there is no error. CR# 869403
+ * 08/10/15 Update upper 32 bit tx and rx queue ptr registers.
+ * 3.2 hk 02/22/16 Added SGMII support for Zynq Ultrascale+ MPSoC.
+ * 3.4 ms 01/23/17 Modified xil_printf statement in main function for all
+ * examples to ensure that "Successfully ran" and "Failed"
+ * strings are available in all examples. This is a fix
+ * for CR-965028.
+ * ms 03/17/17 Modified text file in examples folder for doxygen
+ * generation.
+ * ms 04/05/17 Added tabspace for return statements in functions of
+ * xemacps_ieee1588_example.c for proper documentation
+ * while generating doxygen.
+ * 3.5 hk 08/14/17 Update cache coherency information of the interface in
+ * its config structure.
+ * 3.6 rb 09/08/17 HwCnt variable (in XEmacPs_BdRing structure) is
+ * changed to volatile.
+ * Add API XEmacPs_BdRingPtrReset() to reset pointers
+ * 3.8 hk 07/19/18 Fixed CPP, GCC and doxygen warnings - CR-1006327
+ * hk 09/17/18 Fix PTP interrupt masks and cleanup comments.
+ * 3.9 hk 01/23/19 Add RX watermark support
+ *
+ * </pre>
+ *
+ ****************************************************************************/
+
+#ifndef XEMACPS_H /* prevent circular inclusions */
+#define XEMACPS_H /* by using protection macros */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/***************************** Include Files ********************************/
+
+#include "xil_types.h"
+#include "xil_assert.h"
+#include "xstatus.h"
+#include "xemacps_hw.h"
+#include "xemacps_bd.h"
+#include "xemacps_bdring.h"
+
+/************************** Constant Definitions ****************************/
+
+/*
+ * Device information
+ */
+#define XEMACPS_DEVICE_NAME "xemacps"
+#define XEMACPS_DEVICE_DESC "Xilinx PS 10/100/1000 MAC"
+
+
+/** @name Configuration options
+ *
+ * Device configuration options. See the XEmacPs_SetOptions(),
+ * XEmacPs_ClearOptions() and XEmacPs_GetOptions() for information on how to
+ * use options.
+ *
+ * The default state of the options are noted and are what the device and
+ * driver will be set to after calling XEmacPs_Reset() or
+ * XEmacPs_Initialize().
+ *
+ * @{
+ */
+
+#define XEMACPS_PROMISC_OPTION 0x00000001U
+/**< Accept all incoming packets.
+ * This option defaults to disabled (cleared) */
+
+#define XEMACPS_FRAME1536_OPTION 0x00000002U
+/**< Frame larger than 1516 support for Tx & Rx.
+ * This option defaults to disabled (cleared) */
+
+#define XEMACPS_VLAN_OPTION 0x00000004U
+/**< VLAN Rx & Tx frame support.
+ * This option defaults to disabled (cleared) */
+
+#define XEMACPS_FLOW_CONTROL_OPTION 0x00000010U
+/**< Enable recognition of flow control frames on Rx
+ * This option defaults to enabled (set) */
+
+#define XEMACPS_FCS_STRIP_OPTION 0x00000020U
+/**< Strip FCS and PAD from incoming frames. Note: PAD from VLAN frames is not
+ * stripped.
+ * This option defaults to enabled (set) */
+
+#define XEMACPS_FCS_INSERT_OPTION 0x00000040U
+/**< Generate FCS field and add PAD automatically for outgoing frames.
+ * This option defaults to disabled (cleared) */
+
+#define XEMACPS_LENTYPE_ERR_OPTION 0x00000080U
+/**< Enable Length/Type error checking for incoming frames. When this option is
+ * set, the MAC will filter frames that have a mismatched type/length field
+ * and if XEMACPS_REPORT_RXERR_OPTION is set, the user is notified when these
+ * types of frames are encountered. When this option is cleared, the MAC will
+ * allow these types of frames to be received.
+ *
+ * This option defaults to disabled (cleared) */
+
+#define XEMACPS_TRANSMITTER_ENABLE_OPTION 0x00000100U
+/**< Enable the transmitter.
+ * This option defaults to enabled (set) */
+
+#define XEMACPS_RECEIVER_ENABLE_OPTION 0x00000200U
+/**< Enable the receiver
+ * This option defaults to enabled (set) */
+
+#define XEMACPS_BROADCAST_OPTION 0x00000400U
+/**< Allow reception of the broadcast address
+ * This option defaults to enabled (set) */
+
+#define XEMACPS_MULTICAST_OPTION 0x00000800U
+/**< Allows reception of multicast addresses programmed into hash
+ * This option defaults to disabled (clear) */
+
+#define XEMACPS_RX_CHKSUM_ENABLE_OPTION 0x00001000U
+/**< Enable the RX checksum offload
+ * This option defaults to enabled (set) */
+
+#define XEMACPS_TX_CHKSUM_ENABLE_OPTION 0x00002000U
+/**< Enable the TX checksum offload
+ * This option defaults to enabled (set) */
+
+#define XEMACPS_JUMBO_ENABLE_OPTION 0x00004000U
+#define XEMACPS_SGMII_ENABLE_OPTION 0x00008000U
+
+#define XEMACPS_DEFAULT_OPTIONS \
+ ((u32)XEMACPS_FLOW_CONTROL_OPTION | \
+ (u32)XEMACPS_FCS_INSERT_OPTION | \
+ (u32)XEMACPS_FCS_STRIP_OPTION | \
+ (u32)XEMACPS_BROADCAST_OPTION | \
+ (u32)XEMACPS_LENTYPE_ERR_OPTION | \
+ (u32)XEMACPS_TRANSMITTER_ENABLE_OPTION | \
+ (u32)XEMACPS_RECEIVER_ENABLE_OPTION | \
+ (u32)XEMACPS_RX_CHKSUM_ENABLE_OPTION | \
+ (u32)XEMACPS_TX_CHKSUM_ENABLE_OPTION)
+
+/**< Default options set when device is initialized or reset */
+/*@}*/
+
+/** @name Callback identifiers
+ *
+ * These constants are used as parameters to XEmacPs_SetHandler()
+ * @{
+ */
+#define XEMACPS_HANDLER_DMASEND 1U
+#define XEMACPS_HANDLER_DMARECV 2U
+#define XEMACPS_HANDLER_ERROR 3U
+/*@}*/
+
+/* Constants to determine the configuration of the hardware device. They are
+ * used to allow the driver to verify it can operate with the hardware.
+ */
+#define XEMACPS_MDIO_DIV_DFT MDC_DIV_32 /**< Default MDIO clock divisor */
+
+/* The next few constants help upper layers determine the size of memory
+ * pools used for Ethernet buffers and descriptor lists.
+ */
+#define XEMACPS_MAC_ADDR_SIZE 6U /* size of Ethernet header */
+
+#define XEMACPS_MTU 1500U /* max MTU size of Ethernet frame */
+#define XEMACPS_MTU_JUMBO 10240U /* max MTU size of jumbo frame */
+#define XEMACPS_HDR_SIZE 14U /* size of Ethernet header */
+#define XEMACPS_HDR_VLAN_SIZE 18U /* size of Ethernet header with VLAN */
+#define XEMACPS_TRL_SIZE 4U /* size of Ethernet trailer (FCS) */
+#define XEMACPS_MAX_FRAME_SIZE (XEMACPS_MTU + XEMACPS_HDR_SIZE + \
+ XEMACPS_TRL_SIZE)
+#define XEMACPS_MAX_VLAN_FRAME_SIZE (XEMACPS_MTU + XEMACPS_HDR_SIZE + \
+ XEMACPS_HDR_VLAN_SIZE + XEMACPS_TRL_SIZE)
+#define XEMACPS_MAX_VLAN_FRAME_SIZE_JUMBO (XEMACPS_MTU_JUMBO + XEMACPS_HDR_SIZE + \
+ XEMACPS_HDR_VLAN_SIZE + XEMACPS_TRL_SIZE)
+
+/* DMACR Bust length hash defines */
+
+#define XEMACPS_SINGLE_BURST 0x00000001
+#define XEMACPS_4BYTE_BURST 0x00000004
+#define XEMACPS_8BYTE_BURST 0x00000008
+#define XEMACPS_16BYTE_BURST 0x00000010
+
+
+/**************************** Type Definitions ******************************/
+/** @name Typedefs for callback functions
+ *
+ * These callbacks are invoked in interrupt context.
+ * @{
+ */
+/**
+ * Callback invoked when frame(s) have been sent or received in interrupt
+ * driven DMA mode. To set the send callback, invoke XEmacPs_SetHandler().
+ *
+ * @param CallBackRef is user data assigned when the callback was set.
+ *
+ * @note
+ * See xemacps_hw.h for bitmasks definitions and the device hardware spec for
+ * further information on their meaning.
+ *
+ */
+typedef void (*XEmacPs_Handler) (void *CallBackRef);
+
+/**
+ * Callback when an asynchronous error occurs. To set this callback, invoke
+ * XEmacPs_SetHandler() with XEMACPS_HANDLER_ERROR in the HandlerType
+ * parameter.
+ *
+ * @param CallBackRef is user data assigned when the callback was set.
+ * @param Direction defines either receive or transmit error(s) has occurred.
+ * @param ErrorWord definition varies with Direction
+ *
+ */
+typedef void (*XEmacPs_ErrHandler) (void *CallBackRef, u8 Direction,
+ u32 ErrorWord);
+
+/*@}*/
+
+/**
+ * This typedef contains configuration information for a device.
+ */
+typedef struct {
+ u16 DeviceId; /**< Unique ID of device */
+ UINTPTR BaseAddress;/**< Physical base address of IPIF registers */
+ u8 IsCacheCoherent; /**< Applicable only to A53 in EL1 mode;
+ * describes whether Cache Coherent or not */
+} XEmacPs_Config;
+
+
+/**
+ * The XEmacPs driver instance data. The user is required to allocate a
+ * structure of this type for every XEmacPs device in the system. A pointer
+ * to a structure of this type is then passed to the driver API functions.
+ */
+typedef struct XEmacPs_Instance {
+ XEmacPs_Config Config; /* Hardware configuration */
+ u32 IsStarted; /* Device is currently started */
+ u32 IsReady; /* Device is initialized and ready */
+ u32 Options; /* Current options word */
+
+ XEmacPs_BdRing TxBdRing; /* Transmit BD ring */
+ XEmacPs_BdRing RxBdRing; /* Receive BD ring */
+
+ XEmacPs_Handler SendHandler;
+ XEmacPs_Handler RecvHandler;
+ void *SendRef;
+ void *RecvRef;
+
+ XEmacPs_ErrHandler ErrorHandler;
+ void *ErrorRef;
+ u32 Version;
+ u32 RxBufMask;
+ u32 MaxMtuSize;
+ u32 MaxFrameSize;
+ u32 MaxVlanFrameSize;
+
+} XEmacPs;
+
+
+/***************** Macros (Inline Functions) Definitions ********************/
+
+/****************************************************************************/
+/**
+* Retrieve the Tx ring object. This object can be used in the various Ring
+* API functions.
+*
+* @param InstancePtr is the DMA channel to operate on.
+*
+* @return TxBdRing attribute
+*
+* @note
+* C-style signature:
+* XEmacPs_BdRing XEmacPs_GetTxRing(XEmacPs *InstancePtr)
+*
+*****************************************************************************/
+#define XEmacPs_GetTxRing(InstancePtr) ((InstancePtr)->TxBdRing)
+
+/****************************************************************************/
+/**
+* Retrieve the Rx ring object. This object can be used in the various Ring
+* API functions.
+*
+* @param InstancePtr is the DMA channel to operate on.
+*
+* @return RxBdRing attribute
+*
+* @note
+* C-style signature:
+* XEmacPs_BdRing XEmacPs_GetRxRing(XEmacPs *InstancePtr)
+*
+*****************************************************************************/
+#define XEmacPs_GetRxRing(InstancePtr) ((InstancePtr)->RxBdRing)
+
+/****************************************************************************/
+/**
+*
+* Enable interrupts specified in <i>Mask</i>. The corresponding interrupt for
+* each bit set to 1 in <i>Mask</i>, will be enabled.
+*
+* @param InstancePtr is a pointer to the instance to be worked on.
+* @param Mask contains a bit mask of interrupts to enable. The mask can
+* be formed using a set of bitwise or'd values.
+*
+* @note
+* The state of the transmitter and receiver are not modified by this function.
+* C-style signature
+* void XEmacPs_IntEnable(XEmacPs *InstancePtr, u32 Mask)
+*
+*****************************************************************************/
+#define XEmacPs_IntEnable(InstancePtr, Mask) \
+ XEmacPs_WriteReg((InstancePtr)->Config.BaseAddress, \
+ XEMACPS_IER_OFFSET, \
+ ((Mask) & XEMACPS_IXR_ALL_MASK));
+
+/****************************************************************************/
+/**
+*
+* Disable interrupts specified in <i>Mask</i>. The corresponding interrupt for
+* each bit set to 1 in <i>Mask</i>, will be enabled.
+*
+* @param InstancePtr is a pointer to the instance to be worked on.
+* @param Mask contains a bit mask of interrupts to disable. The mask can
+* be formed using a set of bitwise or'd values.
+*
+* @note
+* The state of the transmitter and receiver are not modified by this function.
+* C-style signature
+* void XEmacPs_IntDisable(XEmacPs *InstancePtr, u32 Mask)
+*
+*****************************************************************************/
+#define XEmacPs_IntDisable(InstancePtr, Mask) \
+ XEmacPs_WriteReg((InstancePtr)->Config.BaseAddress, \
+ XEMACPS_IDR_OFFSET, \
+ ((Mask) & XEMACPS_IXR_ALL_MASK));
+
+/****************************************************************************/
+/**
+*
+* Enable interrupts specified in <i>Mask</i>. The corresponding interrupt for
+* each bit set to 1 in <i>Mask</i>, will be enabled.
+*
+* @param InstancePtr is a pointer to the instance to be worked on.
+* @param Mask contains a bit mask of interrupts to enable. The mask can
+* be formed using a set of bitwise or'd values.
+*
+* @note
+* The state of the transmitter and receiver are not modified by this function.
+* C-style signature
+* void XEmacPs_IntQ1Enable(XEmacPs *InstancePtr, u32 Mask)
+*
+*****************************************************************************/
+#define XEmacPs_IntQ1Enable(InstancePtr, Mask) \
+ XEmacPs_WriteReg((InstancePtr)->Config.BaseAddress, \
+ XEMACPS_INTQ1_IER_OFFSET, \
+ ((Mask) & XEMACPS_INTQ1_IXR_ALL_MASK));
+
+/****************************************************************************/
+/**
+*
+* Disable interrupts specified in <i>Mask</i>. The corresponding interrupt for
+* each bit set to 1 in <i>Mask</i>, will be enabled.
+*
+* @param InstancePtr is a pointer to the instance to be worked on.
+* @param Mask contains a bit mask of interrupts to disable. The mask can
+* be formed using a set of bitwise or'd values.
+*
+* @note
+* The state of the transmitter and receiver are not modified by this function.
+* C-style signature
+* void XEmacPs_IntDisable(XEmacPs *InstancePtr, u32 Mask)
+*
+*****************************************************************************/
+#define XEmacPs_IntQ1Disable(InstancePtr, Mask) \
+ XEmacPs_WriteReg((InstancePtr)->Config.BaseAddress, \
+ XEMACPS_INTQ1_IDR_OFFSET, \
+ ((Mask) & XEMACPS_INTQ1_IXR_ALL_MASK));
+
+/****************************************************************************/
+/**
+*
+* This macro triggers trasmit circuit to send data currently in TX buffer(s).
+*
+* @param InstancePtr is a pointer to the XEmacPs instance to be worked on.
+*
+* @return
+*
+* @note
+*
+* Signature: void XEmacPs_Transmit(XEmacPs *InstancePtr)
+*
+*****************************************************************************/
+#define XEmacPs_Transmit(InstancePtr) \
+ XEmacPs_WriteReg((InstancePtr)->Config.BaseAddress, \
+ XEMACPS_NWCTRL_OFFSET, \
+ (XEmacPs_ReadReg((InstancePtr)->Config.BaseAddress, \
+ XEMACPS_NWCTRL_OFFSET) | XEMACPS_NWCTRL_STARTTX_MASK))
+
+/****************************************************************************/
+/**
+*
+* This macro determines if the device is configured with checksum offloading
+* on the receive channel
+*
+* @param InstancePtr is a pointer to the XEmacPs instance to be worked on.
+*
+* @return
+*
+* Boolean TRUE if the device is configured with checksum offloading, or
+* FALSE otherwise.
+*
+* @note
+*
+* Signature: u32 XEmacPs_IsRxCsum(XEmacPs *InstancePtr)
+*
+*****************************************************************************/
+#define XEmacPs_IsRxCsum(InstancePtr) \
+ ((XEmacPs_ReadReg((InstancePtr)->Config.BaseAddress, \
+ XEMACPS_NWCFG_OFFSET) & XEMACPS_NWCFG_RXCHKSUMEN_MASK) != 0U \
+ ? TRUE : FALSE)
+
+/****************************************************************************/
+/**
+*
+* This macro determines if the device is configured with checksum offloading
+* on the transmit channel
+*
+* @param InstancePtr is a pointer to the XEmacPs instance to be worked on.
+*
+* @return
+*
+* Boolean TRUE if the device is configured with checksum offloading, or
+* FALSE otherwise.
+*
+* @note
+*
+* Signature: u32 XEmacPs_IsTxCsum(XEmacPs *InstancePtr)
+*
+*****************************************************************************/
+#define XEmacPs_IsTxCsum(InstancePtr) \
+ ((XEmacPs_ReadReg((InstancePtr)->Config.BaseAddress, \
+ XEMACPS_DMACR_OFFSET) & XEMACPS_DMACR_TCPCKSUM_MASK) != 0U \
+ ? TRUE : FALSE)
+
+/************************** Function Prototypes *****************************/
+
+/****************************************************************************/
+/**
+*
+* This macro sets RX watermark register.
+*
+* @param InstancePtr is a pointer to the XEmacPs instance to be worked on.
+* @param High is the non-zero RX high watermark value. When SRAM fill level
+* is above this, a pause frame will be sent.
+* @param Low is the non-zero RX low watermark value. When SRAM fill level
+* is below this, a zero length pause frame will be sent IF the last
+* pause frame sent was non-zero.
+*
+* @return None
+*
+* @note
+*
+* Signature: void XEmacPs_SetRXWatermark(XEmacPs *InstancePtr, u16 High,
+* u16 Low)
+*
+*****************************************************************************/
+#define XEmacPs_SetRXWatermark(InstancePtr, High, Low) \
+ XEmacPs_WriteReg((InstancePtr)->Config.BaseAddress, \
+ XEMACPS_RXWATERMARK_OFFSET, \
+ (High & XEMACPS_RXWM_HIGH_MASK) | \
+ ((Low << XEMACPS_RXWM_LOW_SHFT_MSK) & XEMACPS_RXWM_LOW_MASK) |)
+
+/****************************************************************************/
+/**
+*
+* This macro gets RX watermark register.
+*
+* @param InstancePtr is a pointer to the XEmacPs instance to be worked on.
+*
+* @return RX watermark register value
+*
+* @note
+*
+* Signature: void XEmacPs_GetRXWatermark(XEmacPs *InstancePtr)
+*
+*****************************************************************************/
+#define XEmacPs_GetRXWatermark(InstancePtr) \
+ XEmacPs_ReadReg((InstancePtr)->Config.BaseAddress, \
+ XEMACPS_RXWATERMARK_OFFSET)
+/*
+ * Initialization functions in xemacps.c
+ */
+LONG XEmacPs_CfgInitialize(XEmacPs *InstancePtr, XEmacPs_Config *CfgPtr,
+ UINTPTR EffectiveAddress);
+void XEmacPs_Start(XEmacPs *InstancePtr);
+void XEmacPs_Stop(XEmacPs *InstancePtr);
+void XEmacPs_Reset(XEmacPs *InstancePtr);
+void XEmacPs_SetQueuePtr(XEmacPs *InstancePtr, UINTPTR QPtr, u8 QueueNum,
+ u16 Direction);
+
+/*
+ * Lookup configuration in xemacps_sinit.c
+ */
+XEmacPs_Config *XEmacPs_LookupConfig(u16 DeviceId);
+
+/*
+ * Interrupt-related functions in xemacps_intr.c
+ * DMA only and FIFO is not supported. This DMA does not support coalescing.
+ */
+LONG XEmacPs_SetHandler(XEmacPs *InstancePtr, u32 HandlerType,
+ void *FuncPointer, void *CallBackRef);
+void XEmacPs_IntrHandler(void *XEmacPsPtr);
+
+/*
+ * MAC configuration/control functions in XEmacPs_control.c
+ */
+LONG XEmacPs_SetOptions(XEmacPs *InstancePtr, u32 Options);
+LONG XEmacPs_ClearOptions(XEmacPs *InstancePtr, u32 Options);
+u32 XEmacPs_GetOptions(XEmacPs *InstancePtr);
+
+LONG XEmacPs_SetMacAddress(XEmacPs *InstancePtr, void *AddressPtr, u8 Index);
+LONG XEmacPs_DeleteHash(XEmacPs *InstancePtr, void *AddressPtr);
+void XEmacPs_GetMacAddress(XEmacPs *InstancePtr, void *AddressPtr, u8 Index);
+
+LONG XEmacPs_SetHash(XEmacPs *InstancePtr, void *AddressPtr);
+void XEmacPs_ClearHash(XEmacPs *InstancePtr);
+void XEmacPs_GetHash(XEmacPs *InstancePtr, void *AddressPtr);
+
+void XEmacPs_SetMdioDivisor(XEmacPs *InstancePtr,
+ XEmacPs_MdcDiv Divisor);
+void XEmacPs_SetOperatingSpeed(XEmacPs *InstancePtr, u16 Speed);
+u16 XEmacPs_GetOperatingSpeed(XEmacPs *InstancePtr);
+LONG XEmacPs_PhyRead(XEmacPs *InstancePtr, u32 PhyAddress,
+ u32 RegisterNum, u16 *PhyDataPtr);
+LONG XEmacPs_PhyWrite(XEmacPs *InstancePtr, u32 PhyAddress,
+ u32 RegisterNum, u16 PhyData);
+LONG XEmacPs_SetTypeIdCheck(XEmacPs *InstancePtr, u32 Id_Check, u8 Index);
+
+LONG XEmacPs_SendPausePacket(XEmacPs *InstancePtr);
+void XEmacPs_DMABLengthUpdate(XEmacPs *InstancePtr, s32 BLength);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* end of protection macro */
+/** @} */
diff --git a/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/emacps_v3_10/src/xemacps_bd.h b/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/emacps_v3_10/src/xemacps_bd.h
new file mode 100644
index 0000000..452d484
--- /dev/null
+++ b/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/emacps_v3_10/src/xemacps_bd.h
@@ -0,0 +1,782 @@
+/******************************************************************************
+*
+* Copyright (C) 2010 - 2019 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+* THE SOFTWARE.
+*
+*
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+ *
+ * @file xemacps_bd.h
+* @addtogroup emacps_v3_10
+* @{
+ *
+ * This header provides operations to manage buffer descriptors in support
+ * of scatter-gather DMA.
+ *
+ * The API exported by this header defines abstracted macros that allow the
+ * user to read/write specific BD fields.
+ *
+ * <b>Buffer Descriptors</b>
+ *
+ * A buffer descriptor (BD) defines a DMA transaction. The macros defined by
+ * this header file allow access to most fields within a BD to tailor a DMA
+ * transaction according to user and hardware requirements. See the hardware
+ * IP DMA spec for more information on BD fields and how they affect transfers.
+ *
+ * The XEmacPs_Bd structure defines a BD. The organization of this structure
+ * is driven mainly by the hardware for use in scatter-gather DMA transfers.
+ *
+ * <b>Performance</b>
+ *
+ * Limiting I/O to BDs can improve overall performance of the DMA channel.
+ *
+ * <pre>
+ * MODIFICATION HISTORY:
+ *
+ * Ver Who Date Changes
+ * ----- ---- -------- -------------------------------------------------------
+ * 1.00a wsy 01/10/10 First release
+ * 2.1 srt 07/15/14 Add support for Zynq Ultrascale MP GEM specification
+ * and 64-bit changes.
+ * 3.0 kvn 02/13/15 Modified code for MISRA-C:2012 compliance.
+ * 3.0 hk 02/20/15 Added support for jumbo frames.
+ * Disable extended mode. Perform all 64 bit changes under
+ * check for arch64.
+ * 3.2 hk 11/18/15 Change BD typedef and number of words.
+ * 3.8 hk 08/18/18 Remove duplicate definition of XEmacPs_BdSetLength
+ * 3.8 mus 11/05/18 Support 64 bit DMA addresses for Microblaze-X platform.
+ *
+ * </pre>
+ *
+ * ***************************************************************************
+ */
+
+#ifndef XEMACPS_BD_H /* prevent circular inclusions */
+#define XEMACPS_BD_H /* by using protection macros */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/***************************** Include Files *********************************/
+
+#include <string.h>
+#include "xil_types.h"
+#include "xil_assert.h"
+
+/************************** Constant Definitions *****************************/
+
+/**************************** Type Definitions *******************************/
+#ifdef __aarch64__
+/* Minimum BD alignment */
+#define XEMACPS_DMABD_MINIMUM_ALIGNMENT 64U
+#define XEMACPS_BD_NUM_WORDS 4U
+#else
+/* Minimum BD alignment */
+#define XEMACPS_DMABD_MINIMUM_ALIGNMENT 4U
+#define XEMACPS_BD_NUM_WORDS 2U
+#endif
+
+/**
+ * The XEmacPs_Bd is the type for buffer descriptors (BDs).
+ */
+typedef u32 XEmacPs_Bd[XEMACPS_BD_NUM_WORDS];
+
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/*****************************************************************************/
+/**
+ * Zero out BD fields
+ *
+ * @param BdPtr is the BD pointer to operate on
+ *
+ * @return Nothing
+ *
+ * @note
+ * C-style signature:
+ * void XEmacPs_BdClear(XEmacPs_Bd* BdPtr)
+ *
+ *****************************************************************************/
+#define XEmacPs_BdClear(BdPtr) \
+ memset((BdPtr), 0, sizeof(XEmacPs_Bd))
+
+/****************************************************************************/
+/**
+*
+* Read the given Buffer Descriptor word.
+*
+* @param BaseAddress is the base address of the BD to read
+* @param Offset is the word offset to be read
+*
+* @return The 32-bit value of the field
+*
+* @note
+* C-style signature:
+* u32 XEmacPs_BdRead(UINTPTR BaseAddress, UINTPTR Offset)
+*
+*****************************************************************************/
+#define XEmacPs_BdRead(BaseAddress, Offset) \
+ (*(u32 *)((UINTPTR)((void*)(BaseAddress)) + (u32)(Offset)))
+
+/****************************************************************************/
+/**
+*
+* Write the given Buffer Descriptor word.
+*
+* @param BaseAddress is the base address of the BD to write
+* @param Offset is the word offset to be written
+* @param Data is the 32-bit value to write to the field
+*
+* @return None.
+*
+* @note
+* C-style signature:
+* void XEmacPs_BdWrite(UINTPTR BaseAddress, UINTPTR Offset, UINTPTR Data)
+*
+*****************************************************************************/
+#define XEmacPs_BdWrite(BaseAddress, Offset, Data) \
+ (*(u32 *)((UINTPTR)(void*)(BaseAddress) + (u32)(Offset)) = (u32)(Data))
+
+/*****************************************************************************/
+/**
+ * Set the BD's Address field (word 0).
+ *
+ * @param BdPtr is the BD pointer to operate on
+ * @param Addr is the value to write to BD's status field.
+ *
+ * @note :
+ *
+ * C-style signature:
+ * void XEmacPs_BdSetAddressTx(XEmacPs_Bd* BdPtr, UINTPTR Addr)
+ *
+ *****************************************************************************/
+#if defined(__aarch64__) || defined(__arch64__)
+#define XEmacPs_BdSetAddressTx(BdPtr, Addr) \
+ XEmacPs_BdWrite((BdPtr), XEMACPS_BD_ADDR_OFFSET, \
+ (u32)((Addr) & ULONG64_LO_MASK)); \
+ XEmacPs_BdWrite((BdPtr), XEMACPS_BD_ADDR_HI_OFFSET, \
+ (u32)(((Addr) & ULONG64_HI_MASK) >> 32U));
+#else
+#define XEmacPs_BdSetAddressTx(BdPtr, Addr) \
+ XEmacPs_BdWrite((BdPtr), XEMACPS_BD_ADDR_OFFSET, (u32)(Addr))
+#endif
+
+/*****************************************************************************/
+/**
+ * Set the BD's Address field (word 0).
+ *
+ * @param BdPtr is the BD pointer to operate on
+ * @param Addr is the value to write to BD's status field.
+ *
+ * @note : Due to some bits are mixed within receive BD's address field,
+ * read-modify-write is performed.
+ *
+ * C-style signature:
+ * void XEmacPs_BdSetAddressRx(XEmacPs_Bd* BdPtr, UINTPTR Addr)
+ *
+ *****************************************************************************/
+#ifdef __aarch64__
+#define XEmacPs_BdSetAddressRx(BdPtr, Addr) \
+ XEmacPs_BdWrite((BdPtr), XEMACPS_BD_ADDR_OFFSET, \
+ ((XEmacPs_BdRead((BdPtr), XEMACPS_BD_ADDR_OFFSET) & \
+ ~XEMACPS_RXBUF_ADD_MASK) | ((u32)((Addr) & ULONG64_LO_MASK)))); \
+ XEmacPs_BdWrite((BdPtr), XEMACPS_BD_ADDR_HI_OFFSET, \
+ (u32)(((Addr) & ULONG64_HI_MASK) >> 32U));
+#else
+#define XEmacPs_BdSetAddressRx(BdPtr, Addr) \
+ XEmacPs_BdWrite((BdPtr), XEMACPS_BD_ADDR_OFFSET, \
+ ((XEmacPs_BdRead((BdPtr), XEMACPS_BD_ADDR_OFFSET) & \
+ ~XEMACPS_RXBUF_ADD_MASK) | (UINTPTR)(Addr)))
+#endif
+
+/*****************************************************************************/
+/**
+ * Set the BD's Status field (word 1).
+ *
+ * @param BdPtr is the BD pointer to operate on
+ * @param Data is the value to write to BD's status field.
+ *
+ * @note
+ * C-style signature:
+ * void XEmacPs_BdSetStatus(XEmacPs_Bd* BdPtr, UINTPTR Data)
+ *
+ *****************************************************************************/
+#define XEmacPs_BdSetStatus(BdPtr, Data) \
+ XEmacPs_BdWrite((BdPtr), XEMACPS_BD_STAT_OFFSET, \
+ XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) | (Data))
+
+
+/*****************************************************************************/
+/**
+ * Retrieve the BD's Packet DMA transfer status word (word 1).
+ *
+ * @param BdPtr is the BD pointer to operate on
+ *
+ * @return Status word
+ *
+ * @note
+ * C-style signature:
+ * u32 XEmacPs_BdGetStatus(XEmacPs_Bd* BdPtr)
+ *
+ * Due to the BD bit layout differences in transmit and receive. User's
+ * caution is required.
+ *****************************************************************************/
+#define XEmacPs_BdGetStatus(BdPtr) \
+ XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET)
+
+
+/*****************************************************************************/
+/**
+ * Get the address (bits 0..31) of the BD's buffer address (word 0)
+ *
+ * @param BdPtr is the BD pointer to operate on
+ *
+ * @note
+ * C-style signature:
+ * UINTPTR XEmacPs_BdGetBufAddr(XEmacPs_Bd* BdPtr)
+ *
+ *****************************************************************************/
+#if defined(__aarch64__) || defined(__arch64__)
+#define XEmacPs_BdGetBufAddr(BdPtr) \
+ (XEmacPs_BdRead((BdPtr), XEMACPS_BD_ADDR_OFFSET) | \
+ (XEmacPs_BdRead((BdPtr), XEMACPS_BD_ADDR_HI_OFFSET)) << 32U)
+#else
+#define XEmacPs_BdGetBufAddr(BdPtr) \
+ (XEmacPs_BdRead((BdPtr), XEMACPS_BD_ADDR_OFFSET))
+#endif
+
+/*****************************************************************************/
+/**
+ * Set transfer length in bytes for the given BD. The length must be set each
+ * time a BD is submitted to hardware.
+ *
+ * @param BdPtr is the BD pointer to operate on
+ * @param LenBytes is the number of bytes to transfer.
+ *
+ * @note
+ * C-style signature:
+ * void XEmacPs_BdSetLength(XEmacPs_Bd* BdPtr, u32 LenBytes)
+ *
+ *****************************************************************************/
+#define XEmacPs_BdSetLength(BdPtr, LenBytes) \
+ XEmacPs_BdWrite((BdPtr), XEMACPS_BD_STAT_OFFSET, \
+ ((XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) & \
+ ~XEMACPS_TXBUF_LEN_MASK) | (LenBytes)))
+
+
+/*****************************************************************************/
+/**
+ * Retrieve the BD length field.
+ *
+ * For Tx channels, the returned value is the same as that written with
+ * XEmacPs_BdSetLength().
+ *
+ * For Rx channels, the returned value is the size of the received packet.
+ *
+ * @param BdPtr is the BD pointer to operate on
+ *
+ * @return Length field processed by hardware or set by
+ * XEmacPs_BdSetLength().
+ *
+ * @note
+ * C-style signature:
+ * UINTPTR XEmacPs_BdGetLength(XEmacPs_Bd* BdPtr)
+ * XEAMCPS_RXBUF_LEN_MASK is same as XEMACPS_TXBUF_LEN_MASK.
+ *
+ *****************************************************************************/
+#define XEmacPs_BdGetLength(BdPtr) \
+ (XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) & \
+ XEMACPS_RXBUF_LEN_MASK)
+
+/*****************************************************************************/
+/**
+ * Retrieve the RX frame size.
+ *
+ * The returned value is the size of the received packet.
+ * This API supports jumbo frame sizes if enabled.
+ *
+ * @param InstancePtr is the pointer to XEmacps instance
+ *
+ * @param BdPtr is the BD pointer to operate on
+ *
+ * @return Length field processed by hardware or set by
+ * XEmacPs_BdSetLength().
+ *
+ * @note
+ * C-style signature:
+ * UINTPTR XEmacPs_GetRxFrameSize(XEmacPs* InstancePtr, XEmacPs_Bd* BdPtr)
+ * RxBufMask is dependent on whether jumbo is enabled or not.
+ *
+ *****************************************************************************/
+#define XEmacPs_GetRxFrameSize(InstancePtr, BdPtr) \
+ (XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) & \
+ (InstancePtr)->RxBufMask)
+
+/*****************************************************************************/
+/**
+ * Test whether the given BD has been marked as the last BD of a packet.
+ *
+ * @param BdPtr is the BD pointer to operate on
+ *
+ * @return TRUE if BD represents the "Last" BD of a packet, FALSE otherwise
+ *
+ * @note
+ * C-style signature:
+ * UINTPTR XEmacPs_BdIsLast(XEmacPs_Bd* BdPtr)
+ *
+ *****************************************************************************/
+#define XEmacPs_BdIsLast(BdPtr) \
+ ((XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) & \
+ XEMACPS_RXBUF_EOF_MASK)!=0U ? TRUE : FALSE)
+
+
+/*****************************************************************************/
+/**
+ * Tell the DMA engine that the given transmit BD marks the end of the current
+ * packet to be processed.
+ *
+ * @param BdPtr is the BD pointer to operate on
+ *
+ * @note
+ * C-style signature:
+ * void XEmacPs_BdSetLast(XEmacPs_Bd* BdPtr)
+ *
+ *****************************************************************************/
+#define XEmacPs_BdSetLast(BdPtr) \
+ (XEmacPs_BdWrite((BdPtr), XEMACPS_BD_STAT_OFFSET, \
+ XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) | \
+ XEMACPS_TXBUF_LAST_MASK))
+
+
+/*****************************************************************************/
+/**
+ * Tell the DMA engine that the current packet does not end with the given
+ * BD.
+ *
+ * @param BdPtr is the BD pointer to operate on
+ *
+ * @note
+ * C-style signature:
+ * void XEmacPs_BdClearLast(XEmacPs_Bd* BdPtr)
+ *
+ *****************************************************************************/
+#define XEmacPs_BdClearLast(BdPtr) \
+ (XEmacPs_BdWrite((BdPtr), XEMACPS_BD_STAT_OFFSET, \
+ XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) & \
+ ~XEMACPS_TXBUF_LAST_MASK))
+
+
+/*****************************************************************************/
+/**
+ * Set this bit to mark the last descriptor in the receive buffer descriptor
+ * list.
+ *
+ * @param BdPtr is the BD pointer to operate on
+ *
+ * @note
+ * C-style signature:
+ * void XEmacPs_BdSetRxWrap(XEmacPs_Bd* BdPtr)
+ *
+ *****************************************************************************/
+/*#define XEmacPs_BdSetRxWrap(BdPtr) \
+ (XEmacPs_BdWrite((BdPtr), XEMACPS_BD_ADDR_OFFSET, \
+ XEmacPs_BdRead((BdPtr), XEMACPS_BD_ADDR_OFFSET) | \
+ XEMACPS_RXBUF_WRAP_MASK))
+*/
+
+/*****************************************************************************/
+/**
+ * Determine the wrap bit of the receive BD which indicates end of the
+ * BD list.
+ *
+ * @param BdPtr is the BD pointer to operate on
+ *
+ * @note
+ * C-style signature:
+ * u8 XEmacPs_BdIsRxWrap(XEmacPs_Bd* BdPtr)
+ *
+ *****************************************************************************/
+#define XEmacPs_BdIsRxWrap(BdPtr) \
+ ((XEmacPs_BdRead((BdPtr), XEMACPS_BD_ADDR_OFFSET) & \
+ XEMACPS_RXBUF_WRAP_MASK)!=0U ? TRUE : FALSE)
+
+
+/*****************************************************************************/
+/**
+ * Sets this bit to mark the last descriptor in the transmit buffer
+ * descriptor list.
+ *
+ * @param BdPtr is the BD pointer to operate on
+ *
+ * @note
+ * C-style signature:
+ * void XEmacPs_BdSetTxWrap(XEmacPs_Bd* BdPtr)
+ *
+ *****************************************************************************/
+/*#define XEmacPs_BdSetTxWrap(BdPtr) \
+ (XEmacPs_BdWrite((BdPtr), XEMACPS_BD_STAT_OFFSET, \
+ XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) | \
+ XEMACPS_TXBUF_WRAP_MASK))
+*/
+
+/*****************************************************************************/
+/**
+ * Determine the wrap bit of the transmit BD which indicates end of the
+ * BD list.
+ *
+ * @param BdPtr is the BD pointer to operate on
+ *
+ * @note
+ * C-style signature:
+ * u8 XEmacPs_BdGetTxWrap(XEmacPs_Bd* BdPtr)
+ *
+ *****************************************************************************/
+#define XEmacPs_BdIsTxWrap(BdPtr) \
+ ((XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) & \
+ XEMACPS_TXBUF_WRAP_MASK)!=0U ? TRUE : FALSE)
+
+
+/*****************************************************************************/
+/*
+ * Must clear this bit to enable the MAC to write data to the receive
+ * buffer. Hardware sets this bit once it has successfully written a frame to
+ * memory. Once set, software has to clear the bit before the buffer can be
+ * used again. This macro clear the new bit of the receive BD.
+ *
+ * @param BdPtr is the BD pointer to operate on
+ *
+ * @note
+ * C-style signature:
+ * void XEmacPs_BdClearRxNew(XEmacPs_Bd* BdPtr)
+ *
+ *****************************************************************************/
+#define XEmacPs_BdClearRxNew(BdPtr) \
+ (XEmacPs_BdWrite((BdPtr), XEMACPS_BD_ADDR_OFFSET, \
+ XEmacPs_BdRead((BdPtr), XEMACPS_BD_ADDR_OFFSET) & \
+ ~XEMACPS_RXBUF_NEW_MASK))
+
+
+/*****************************************************************************/
+/**
+ * Determine the new bit of the receive BD.
+ *
+ * @param BdPtr is the BD pointer to operate on
+ *
+ * @note
+ * C-style signature:
+ * UINTPTR XEmacPs_BdIsRxNew(XEmacPs_Bd* BdPtr)
+ *
+ *****************************************************************************/
+#define XEmacPs_BdIsRxNew(BdPtr) \
+ ((XEmacPs_BdRead((BdPtr), XEMACPS_BD_ADDR_OFFSET) & \
+ XEMACPS_RXBUF_NEW_MASK)!=0U ? TRUE : FALSE)
+
+
+/*****************************************************************************/
+/**
+ * Software sets this bit to disable the buffer to be read by the hardware.
+ * Hardware sets this bit for the first buffer of a frame once it has been
+ * successfully transmitted. This macro sets this bit of transmit BD to avoid
+ * confusion.
+ *
+ * @param BdPtr is the BD pointer to operate on
+ *
+ * @note
+ * C-style signature:
+ * void XEmacPs_BdSetTxUsed(XEmacPs_Bd* BdPtr)
+ *
+ *****************************************************************************/
+#define XEmacPs_BdSetTxUsed(BdPtr) \
+ (XEmacPs_BdWrite((BdPtr), XEMACPS_BD_STAT_OFFSET, \
+ XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) | \
+ XEMACPS_TXBUF_USED_MASK))
+
+
+/*****************************************************************************/
+/**
+ * Software clears this bit to enable the buffer to be read by the hardware.
+ * Hardware sets this bit for the first buffer of a frame once it has been
+ * successfully transmitted. This macro clears this bit of transmit BD.
+ *
+ * @param BdPtr is the BD pointer to operate on
+ *
+ * @note
+ * C-style signature:
+ * void XEmacPs_BdClearTxUsed(XEmacPs_Bd* BdPtr)
+ *
+ *****************************************************************************/
+#define XEmacPs_BdClearTxUsed(BdPtr) \
+ (XEmacPs_BdWrite((BdPtr), XEMACPS_BD_STAT_OFFSET, \
+ XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) & \
+ ~XEMACPS_TXBUF_USED_MASK))
+
+
+/*****************************************************************************/
+/**
+ * Determine the used bit of the transmit BD.
+ *
+ * @param BdPtr is the BD pointer to operate on
+ *
+ * @note
+ * C-style signature:
+ * UINTPTR XEmacPs_BdIsTxUsed(XEmacPs_Bd* BdPtr)
+ *
+ *****************************************************************************/
+#define XEmacPs_BdIsTxUsed(BdPtr) \
+ ((XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) & \
+ XEMACPS_TXBUF_USED_MASK)!=0U ? TRUE : FALSE)
+
+
+/*****************************************************************************/
+/**
+ * Determine if a frame fails to be transmitted due to too many retries.
+ *
+ * @param BdPtr is the BD pointer to operate on
+ *
+ * @note
+ * C-style signature:
+ * UINTPTR XEmacPs_BdIsTxRetry(XEmacPs_Bd* BdPtr)
+ *
+ *****************************************************************************/
+#define XEmacPs_BdIsTxRetry(BdPtr) \
+ ((XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) & \
+ XEMACPS_TXBUF_RETRY_MASK)!=0U ? TRUE : FALSE)
+
+
+/*****************************************************************************/
+/**
+ * Determine if a frame fails to be transmitted due to data can not be
+ * feteched in time or buffers are exhausted.
+ *
+ * @param BdPtr is the BD pointer to operate on
+ *
+ * @note
+ * C-style signature:
+ * UINTPTR XEmacPs_BdIsTxUrun(XEmacPs_Bd* BdPtr)
+ *
+ *****************************************************************************/
+#define XEmacPs_BdIsTxUrun(BdPtr) \
+ ((XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) & \
+ XEMACPS_TXBUF_URUN_MASK)!=0U ? TRUE : FALSE)
+
+
+/*****************************************************************************/
+/**
+ * Determine if a frame fails to be transmitted due to buffer is exhausted
+ * mid-frame.
+ *
+ * @param BdPtr is the BD pointer to operate on
+ *
+ * @note
+ * C-style signature:
+ * UINTPTR XEmacPs_BdIsTxExh(XEmacPs_Bd* BdPtr)
+ *
+ *****************************************************************************/
+#define XEmacPs_BdIsTxExh(BdPtr) \
+ ((XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) & \
+ XEMACPS_TXBUF_EXH_MASK)!=0U ? TRUE : FALSE)
+
+
+/*****************************************************************************/
+/**
+ * Sets this bit, no CRC will be appended to the current frame. This control
+ * bit must be set for the first buffer in a frame and will be ignored for
+ * the subsequent buffers of a frame.
+ *
+ * @param BdPtr is the BD pointer to operate on
+ *
+ * @note
+ * This bit must be clear when using the transmit checksum generation offload,
+ * otherwise checksum generation and substitution will not occur.
+ *
+ * C-style signature:
+ * UINTPTR XEmacPs_BdSetTxNoCRC(XEmacPs_Bd* BdPtr)
+ *
+ *****************************************************************************/
+#define XEmacPs_BdSetTxNoCRC(BdPtr) \
+ (XEmacPs_BdWrite((BdPtr), XEMACPS_BD_STAT_OFFSET, \
+ XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) | \
+ XEMACPS_TXBUF_NOCRC_MASK))
+
+
+/*****************************************************************************/
+/**
+ * Clear this bit, CRC will be appended to the current frame. This control
+ * bit must be set for the first buffer in a frame and will be ignored for
+ * the subsequent buffers of a frame.
+ *
+ * @param BdPtr is the BD pointer to operate on
+ *
+ * @note
+ * This bit must be clear when using the transmit checksum generation offload,
+ * otherwise checksum generation and substitution will not occur.
+ *
+ * C-style signature:
+ * UINTPTR XEmacPs_BdClearTxNoCRC(XEmacPs_Bd* BdPtr)
+ *
+ *****************************************************************************/
+#define XEmacPs_BdClearTxNoCRC(BdPtr) \
+ (XEmacPs_BdWrite((BdPtr), XEMACPS_BD_STAT_OFFSET, \
+ XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) & \
+ ~XEMACPS_TXBUF_NOCRC_MASK))
+
+
+/*****************************************************************************/
+/**
+ * Determine the broadcast bit of the receive BD.
+ *
+ * @param BdPtr is the BD pointer to operate on
+ *
+ * @note
+ * C-style signature:
+ * UINTPTR XEmacPs_BdIsRxBcast(XEmacPs_Bd* BdPtr)
+ *
+ *****************************************************************************/
+#define XEmacPs_BdIsRxBcast(BdPtr) \
+ ((XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) & \
+ XEMACPS_RXBUF_BCAST_MASK)!=0U ? TRUE : FALSE)
+
+
+/*****************************************************************************/
+/**
+ * Determine the multicast hash bit of the receive BD.
+ *
+ * @param BdPtr is the BD pointer to operate on
+ *
+ * @note
+ * C-style signature:
+ * UINTPTR XEmacPs_BdIsRxMultiHash(XEmacPs_Bd* BdPtr)
+ *
+ *****************************************************************************/
+#define XEmacPs_BdIsRxMultiHash(BdPtr) \
+ ((XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) & \
+ XEMACPS_RXBUF_MULTIHASH_MASK)!=0U ? TRUE : FALSE)
+
+
+/*****************************************************************************/
+/**
+ * Determine the unicast hash bit of the receive BD.
+ *
+ * @param BdPtr is the BD pointer to operate on
+ *
+ * @note
+ * C-style signature:
+ * UINTPTR XEmacPs_BdIsRxUniHash(XEmacPs_Bd* BdPtr)
+ *
+ *****************************************************************************/
+#define XEmacPs_BdIsRxUniHash(BdPtr) \
+ ((XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) & \
+ XEMACPS_RXBUF_UNIHASH_MASK)!=0U ? TRUE : FALSE)
+
+
+/*****************************************************************************/
+/**
+ * Determine if the received frame is a VLAN Tagged frame.
+ *
+ * @param BdPtr is the BD pointer to operate on
+ *
+ * @note
+ * C-style signature:
+ * UINTPTR XEmacPs_BdIsRxVlan(XEmacPs_Bd* BdPtr)
+ *
+ *****************************************************************************/
+#define XEmacPs_BdIsRxVlan(BdPtr) \
+ ((XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) & \
+ XEMACPS_RXBUF_VLAN_MASK)!=0U ? TRUE : FALSE)
+
+
+/*****************************************************************************/
+/**
+ * Determine if the received frame has Type ID of 8100h and null VLAN
+ * identifier(Priority tag).
+ *
+ * @param BdPtr is the BD pointer to operate on
+ *
+ * @note
+ * C-style signature:
+ * UINTPTR XEmacPs_BdIsRxPri(XEmacPs_Bd* BdPtr)
+ *
+ *****************************************************************************/
+#define XEmacPs_BdIsRxPri(BdPtr) \
+ ((XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) & \
+ XEMACPS_RXBUF_PRI_MASK)!=0U ? TRUE : FALSE)
+
+
+/*****************************************************************************/
+/**
+ * Determine if the received frame's Concatenation Format Indicator (CFI) of
+ * the frames VLANTCI field was set.
+ *
+ * @param BdPtr is the BD pointer to operate on
+ *
+ * @note
+ * C-style signature:
+ * UINTPTR XEmacPs_BdIsRxCFI(XEmacPs_Bd* BdPtr)
+ *
+ *****************************************************************************/
+#define XEmacPs_BdIsRxCFI(BdPtr) \
+ ((XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) & \
+ XEMACPS_RXBUF_CFI_MASK)!=0U ? TRUE : FALSE)
+
+
+/*****************************************************************************/
+/**
+ * Determine the End Of Frame (EOF) bit of the receive BD.
+ *
+ * @param BdPtr is the BD pointer to operate on
+ *
+ * @note
+ * C-style signature:
+ * UINTPTR XEmacPs_BdGetRxEOF(XEmacPs_Bd* BdPtr)
+ *
+ *****************************************************************************/
+#define XEmacPs_BdIsRxEOF(BdPtr) \
+ ((XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) & \
+ XEMACPS_RXBUF_EOF_MASK)!=0U ? TRUE : FALSE)
+
+
+/*****************************************************************************/
+/**
+ * Determine the Start Of Frame (SOF) bit of the receive BD.
+ *
+ * @param BdPtr is the BD pointer to operate on
+ *
+ * @note
+ * C-style signature:
+ * UINTPTR XEmacPs_BdGetRxSOF(XEmacPs_Bd* BdPtr)
+ *
+ *****************************************************************************/
+#define XEmacPs_BdIsRxSOF(BdPtr) \
+ ((XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) & \
+ XEMACPS_RXBUF_SOF_MASK)!=0U ? TRUE : FALSE)
+
+
+/************************** Function Prototypes ******************************/
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* end of protection macro */
+/** @} */
diff --git a/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/emacps_v3_10/src/xemacps_bdring.c b/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/emacps_v3_10/src/xemacps_bdring.c
new file mode 100644
index 0000000..6988629
--- /dev/null
+++ b/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/emacps_v3_10/src/xemacps_bdring.c
@@ -0,0 +1,1096 @@
+/******************************************************************************
+*
+* Copyright (C) 2010 - 2019 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+* THE SOFTWARE.
+*
+*
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xemacps_bdring.c
+* @addtogroup emacps_v3_10
+* @{
+*
+* This file implements buffer descriptor ring related functions.
+*
+* <pre>
+* MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ----- ---- -------- -------------------------------------------------------
+* 1.00a wsy 01/10/10 First release
+* 1.00a asa 11/21/11 The function XEmacPs_BdRingFromHwTx is modified.
+* Earlier it used to search in "BdLimit" number of BDs to
+* know which BDs are processed. Now one more check is
+* added. It looks for BDs till the current BD pointer
+* reaches HwTail. By doing this processing time is saved.
+* 1.00a asa 01/24/12 The function XEmacPs_BdRingFromHwTx in file
+* xemacps_bdring.c is modified. Now start of packet is
+* searched for returning the number of BDs processed.
+* 1.05a asa 09/23/13 Cache operations on BDs are not required and hence
+* removed. It is expected that all BDs are allocated in
+* from uncached area. Fix for CR #663885.
+* 2.1 srt 07/15/14 Add support for Zynq Ultrascale Mp architecture.
+* 3.0 kvn 02/13/15 Modified code for MISRA-C:2012 compliance.
+* 3.6 rb 09/08/17 Add XEmacPs_BdRingPtrReset() API to reset BD ring
+* pointers
+*
+* </pre>
+******************************************************************************/
+
+/***************************** Include Files *********************************/
+
+#include "xstatus.h"
+#include "xil_cache.h"
+#include "xemacps_hw.h"
+#include "xemacps_bd.h"
+#include "xemacps_bdring.h"
+
+/************************** Constant Definitions *****************************/
+
+/**************************** Type Definitions *******************************/
+
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/****************************************************************************
+ * Compute the virtual address of a descriptor from its physical address
+ *
+ * @param BdPtr is the physical address of the BD
+ *
+ * @returns Virtual address of BdPtr
+ *
+ * @note Assume BdPtr is always a valid BD in the ring
+ ****************************************************************************/
+#define XEMACPS_PHYS_TO_VIRT(BdPtr) \
+ ((UINTPTR)(BdPtr) + (RingPtr->BaseBdAddr - RingPtr->PhysBaseAddr))
+
+/****************************************************************************
+ * Compute the physical address of a descriptor from its virtual address
+ *
+ * @param BdPtr is the physical address of the BD
+ *
+ * @returns Physical address of BdPtr
+ *
+ * @note Assume BdPtr is always a valid BD in the ring
+ ****************************************************************************/
+#define XEMACPS_VIRT_TO_PHYS(BdPtr) \
+ ((UINTPTR)(BdPtr) - (RingPtr->BaseBdAddr - RingPtr->PhysBaseAddr))
+
+/****************************************************************************
+ * Move the BdPtr argument ahead an arbitrary number of BDs wrapping around
+ * to the beginning of the ring if needed.
+ *
+ * We know if a wrapaound should occur if the new BdPtr is greater than
+ * the high address in the ring OR if the new BdPtr crosses over the
+ * 0xFFFFFFFF to 0 boundary. The latter test is a valid one since we do not
+ * allow a BD space to span this boundary.
+ *
+ * @param RingPtr is the ring BdPtr appears in
+ * @param BdPtr on input is the starting BD position and on output is the
+ * final BD position
+ * @param NumBd is the number of BD spaces to increment
+ *
+ ****************************************************************************/
+#define XEMACPS_RING_SEEKAHEAD(RingPtr, BdPtr, NumBd) \
+ { \
+ UINTPTR Addr = (UINTPTR)(void *)(BdPtr); \
+ \
+ Addr += ((RingPtr)->Separation * (NumBd)); \
+ if ((Addr > (RingPtr)->HighBdAddr) || ((UINTPTR)(void *)(BdPtr) > Addr)) \
+ { \
+ Addr -= (RingPtr)->Length; \
+ } \
+ \
+ (BdPtr) = (XEmacPs_Bd*)(void *)Addr; \
+ }
+
+/****************************************************************************
+ * Move the BdPtr argument backwards an arbitrary number of BDs wrapping
+ * around to the end of the ring if needed.
+ *
+ * We know if a wrapaound should occur if the new BdPtr is less than
+ * the base address in the ring OR if the new BdPtr crosses over the
+ * 0xFFFFFFFF to 0 boundary. The latter test is a valid one since we do not
+ * allow a BD space to span this boundary.
+ *
+ * @param RingPtr is the ring BdPtr appears in
+ * @param BdPtr on input is the starting BD position and on output is the
+ * final BD position
+ * @param NumBd is the number of BD spaces to increment
+ *
+ ****************************************************************************/
+#define XEMACPS_RING_SEEKBACK(RingPtr, BdPtr, NumBd) \
+ { \
+ UINTPTR Addr = (UINTPTR)(void *)(BdPtr); \
+ \
+ Addr -= ((RingPtr)->Separation * (NumBd)); \
+ if ((Addr < (RingPtr)->BaseBdAddr) || ((UINTPTR)(void*)(BdPtr) < Addr)) \
+ { \
+ Addr += (RingPtr)->Length; \
+ } \
+ \
+ (BdPtr) = (XEmacPs_Bd*)(void*)Addr; \
+ }
+
+
+/************************** Function Prototypes ******************************/
+
+static void XEmacPs_BdSetRxWrap(UINTPTR BdPtr);
+static void XEmacPs_BdSetTxWrap(UINTPTR BdPtr);
+
+/************************** Variable Definitions *****************************/
+
+/*****************************************************************************/
+/**
+ * Using a memory segment allocated by the caller, create and setup the BD list
+ * for the given DMA channel.
+ *
+ * @param RingPtr is the instance to be worked on.
+ * @param PhysAddr is the physical base address of user memory region.
+ * @param VirtAddr is the virtual base address of the user memory region. If
+ * address translation is not being utilized, then VirtAddr should be
+ * equivalent to PhysAddr.
+ * @param Alignment governs the byte alignment of individual BDs. This function
+ * will enforce a minimum alignment of 4 bytes with no maximum as long
+ * as it is specified as a power of 2.
+ * @param BdCount is the number of BDs to setup in the user memory region. It
+ * is assumed the region is large enough to contain the BDs.
+ *
+ * @return
+ *
+ * - XST_SUCCESS if initialization was successful
+ * - XST_NO_FEATURE if the provided instance is a non DMA type
+ * channel.
+ * - XST_INVALID_PARAM under any of the following conditions:
+ * 1) PhysAddr and/or VirtAddr are not aligned to the given Alignment
+ * parameter.
+ * 2) Alignment parameter does not meet minimum requirements or is not a
+ * power of 2 value.
+ * 3) BdCount is 0.
+ * - XST_DMA_SG_LIST_ERROR if the memory segment containing the list spans
+ * over address 0x00000000 in virtual address space.
+ *
+ * @note
+ * Make sure to pass in the right alignment value.
+ *****************************************************************************/
+LONG XEmacPs_BdRingCreate(XEmacPs_BdRing * RingPtr, UINTPTR PhysAddr,
+ UINTPTR VirtAddr, u32 Alignment, u32 BdCount)
+{
+ u32 i;
+ UINTPTR BdVirtAddr;
+ UINTPTR BdPhyAddr;
+ UINTPTR VirtAddrLoc = VirtAddr;
+
+ /* In case there is a failure prior to creating list, make sure the
+ * following attributes are 0 to prevent calls to other functions
+ * from doing anything.
+ */
+ RingPtr->AllCnt = 0U;
+ RingPtr->FreeCnt = 0U;
+ RingPtr->HwCnt = 0U;
+ RingPtr->PreCnt = 0U;
+ RingPtr->PostCnt = 0U;
+
+ /* Make sure Alignment parameter meets minimum requirements */
+ if (Alignment < (u32)XEMACPS_DMABD_MINIMUM_ALIGNMENT) {
+ return (LONG)(XST_INVALID_PARAM);
+ }
+
+ /* Make sure Alignment is a power of 2 */
+ if (((Alignment - 0x00000001U) & Alignment)!=0x00000000U) {
+ return (LONG)(XST_INVALID_PARAM);
+ }
+
+ /* Make sure PhysAddr and VirtAddr are on same Alignment */
+ if (((PhysAddr % Alignment)!=(u32)0) || ((VirtAddrLoc % Alignment)!=(u32)0)) {
+ return (LONG)(XST_INVALID_PARAM);
+ }
+
+ /* Is BdCount reasonable? */
+ if (BdCount == 0x00000000U) {
+ return (LONG)(XST_INVALID_PARAM);
+ }
+
+ /* Figure out how many bytes will be between the start of adjacent BDs */
+ RingPtr->Separation = ((u32)sizeof(XEmacPs_Bd));
+
+ /* Must make sure the ring doesn't span address 0x00000000. If it does,
+ * then the next/prev BD traversal macros will fail.
+ */
+ if (VirtAddrLoc > ((VirtAddrLoc + (RingPtr->Separation * BdCount)) - (u32)1)) {
+ return (LONG)(XST_DMA_SG_LIST_ERROR);
+ }
+
+ /* Initial ring setup:
+ * - Clear the entire space
+ * - Setup each BD's BDA field with the physical address of the next BD
+ */
+ (void)memset((void *) VirtAddrLoc, 0, (RingPtr->Separation * BdCount));
+
+ BdVirtAddr = VirtAddrLoc;
+ BdPhyAddr = PhysAddr + RingPtr->Separation;
+ for (i = 1U; i < BdCount; i++) {
+ BdVirtAddr += RingPtr->Separation;
+ BdPhyAddr += RingPtr->Separation;
+ }
+
+ /* Setup and initialize pointers and counters */
+ RingPtr->RunState = (u32)(XST_DMA_SG_IS_STOPPED);
+ RingPtr->BaseBdAddr = VirtAddrLoc;
+ RingPtr->PhysBaseAddr = PhysAddr;
+ RingPtr->HighBdAddr = BdVirtAddr;
+ RingPtr->Length =
+ ((RingPtr->HighBdAddr - RingPtr->BaseBdAddr) + RingPtr->Separation);
+ RingPtr->AllCnt = (u32)BdCount;
+ RingPtr->FreeCnt = (u32)BdCount;
+ RingPtr->FreeHead = (XEmacPs_Bd *)(void *)VirtAddrLoc;
+ RingPtr->PreHead = (XEmacPs_Bd *)VirtAddrLoc;
+ RingPtr->HwHead = (XEmacPs_Bd *)VirtAddrLoc;
+ RingPtr->HwTail = (XEmacPs_Bd *)VirtAddrLoc;
+ RingPtr->PostHead = (XEmacPs_Bd *)VirtAddrLoc;
+ RingPtr->BdaRestart = (XEmacPs_Bd *)(void *)PhysAddr;
+
+ return (LONG)(XST_SUCCESS);
+}
+
+
+/*****************************************************************************/
+/**
+ * Clone the given BD into every BD in the list.
+ * every field of the source BD is replicated in every BD of the list.
+ *
+ * This function can be called only when all BDs are in the free group such as
+ * they are immediately after initialization with XEmacPs_BdRingCreate().
+ * This prevents modification of BDs while they are in use by hardware or the
+ * user.
+ *
+ * @param RingPtr is the pointer of BD ring instance to be worked on.
+ * @param SrcBdPtr is the source BD template to be cloned into the list. This
+ * BD will be modified.
+ * @param Direction is either XEMACPS_SEND or XEMACPS_RECV that indicates
+ * which direction.
+ *
+ * @return
+ * - XST_SUCCESS if the list was modified.
+ * - XST_DMA_SG_NO_LIST if a list has not been created.
+ * - XST_DMA_SG_LIST_ERROR if some of the BDs in this channel are under
+ * hardware or user control.
+ * - XST_DEVICE_IS_STARTED if the DMA channel has not been stopped.
+ *
+ *****************************************************************************/
+LONG XEmacPs_BdRingClone(XEmacPs_BdRing * RingPtr, XEmacPs_Bd * SrcBdPtr,
+ u8 Direction)
+{
+ u32 i;
+ UINTPTR CurBd;
+
+ /* Can't do this function if there isn't a ring */
+ if (RingPtr->AllCnt == 0x00000000U) {
+ return (LONG)(XST_DMA_SG_NO_LIST);
+ }
+
+ /* Can't do this function with the channel running */
+ if (RingPtr->RunState == (u32)XST_DMA_SG_IS_STARTED) {
+ return (LONG)(XST_DEVICE_IS_STARTED);
+ }
+
+ /* Can't do this function with some of the BDs in use */
+ if (RingPtr->FreeCnt != RingPtr->AllCnt) {
+ return (LONG)(XST_DMA_SG_LIST_ERROR);
+ }
+
+ if ((Direction != (u8)XEMACPS_SEND) && (Direction != (u8)XEMACPS_RECV)) {
+ return (LONG)(XST_INVALID_PARAM);
+ }
+
+ /* Starting from the top of the ring, save BD.Next, overwrite the entire
+ * BD with the template, then restore BD.Next
+ */
+ CurBd = RingPtr->BaseBdAddr;
+ for (i = 0U; i < RingPtr->AllCnt; i++) {
+ memcpy((void *)CurBd, SrcBdPtr, sizeof(XEmacPs_Bd));
+ CurBd += RingPtr->Separation;
+ }
+
+ CurBd -= RingPtr->Separation;
+
+ if (Direction == XEMACPS_RECV) {
+ XEmacPs_BdSetRxWrap(CurBd);
+ }
+ else {
+ XEmacPs_BdSetTxWrap(CurBd);
+ }
+
+ return (LONG)(XST_SUCCESS);
+}
+
+
+/*****************************************************************************/
+/**
+ * Reserve locations in the BD list. The set of returned BDs may be modified
+ * in preparation for future DMA transaction(s). Once the BDs are ready to be
+ * submitted to hardware, the user must call XEmacPs_BdRingToHw() in the same
+ * order which they were allocated here. Example:
+ *
+ * <pre>
+ * NumBd = 2,
+ * Status = XEmacPs_BdRingAlloc(MyRingPtr, NumBd, &MyBdSet),
+ *
+ * if (Status != XST_SUCCESS)
+ * {
+ * *Not enough BDs available for the request*
+ * }
+ *
+ * CurBd = MyBdSet,
+ * for (i=0; i<NumBd; i++)
+ * {
+ * * Prepare CurBd *.....
+ *
+ * * Onto next BD *
+ * CurBd = XEmacPs_BdRingNext(MyRingPtr, CurBd),
+ * }
+ *
+ * * Give list to hardware *
+ * Status = XEmacPs_BdRingToHw(MyRingPtr, NumBd, MyBdSet),
+ * </pre>
+ *
+ * A more advanced use of this function may allocate multiple sets of BDs.
+ * They must be allocated and given to hardware in the correct sequence:
+ * <pre>
+ * * Legal *
+ * XEmacPs_BdRingAlloc(MyRingPtr, NumBd1, &MySet1),
+ * XEmacPs_BdRingToHw(MyRingPtr, NumBd1, MySet1),
+ *
+ * * Legal *
+ * XEmacPs_BdRingAlloc(MyRingPtr, NumBd1, &MySet1),
+ * XEmacPs_BdRingAlloc(MyRingPtr, NumBd2, &MySet2),
+ * XEmacPs_BdRingToHw(MyRingPtr, NumBd1, MySet1),
+ * XEmacPs_BdRingToHw(MyRingPtr, NumBd2, MySet2),
+ *
+ * * Not legal *
+ * XEmacPs_BdRingAlloc(MyRingPtr, NumBd1, &MySet1),
+ * XEmacPs_BdRingAlloc(MyRingPtr, NumBd2, &MySet2),
+ * XEmacPs_BdRingToHw(MyRingPtr, NumBd2, MySet2),
+ * XEmacPs_BdRingToHw(MyRingPtr, NumBd1, MySet1),
+ * </pre>
+ *
+ * Use the API defined in xemacps_bd.h to modify individual BDs. Traversal
+ * of the BD set can be done using XEmacPs_BdRingNext() and
+ * XEmacPs_BdRingPrev().
+ *
+ * @param RingPtr is a pointer to the BD ring instance to be worked on.
+ * @param NumBd is the number of BDs to allocate
+ * @param BdSetPtr is an output parameter, it points to the first BD available
+ * for modification.
+ *
+ * @return
+ * - XST_SUCCESS if the requested number of BDs was returned in the BdSetPtr
+ * parameter.
+ * - XST_FAILURE if there were not enough free BDs to satisfy the request.
+ *
+ * @note This function should not be preempted by another XEmacPs_Bd function
+ * call that modifies the BD space. It is the caller's responsibility to
+ * provide a mutual exclusion mechanism.
+ *
+ * @note Do not modify more BDs than the number requested with the NumBd
+ * parameter. Doing so will lead to data corruption and system
+ * instability.
+ *
+ *****************************************************************************/
+LONG XEmacPs_BdRingAlloc(XEmacPs_BdRing * RingPtr, u32 NumBd,
+ XEmacPs_Bd ** BdSetPtr)
+{
+ LONG Status;
+ /* Enough free BDs available for the request? */
+ if (RingPtr->FreeCnt < NumBd) {
+ Status = (LONG)(XST_FAILURE);
+ } else {
+ /* Set the return argument and move FreeHead forward */
+ *BdSetPtr = RingPtr->FreeHead;
+ XEMACPS_RING_SEEKAHEAD(RingPtr, RingPtr->FreeHead, NumBd);
+ RingPtr->FreeCnt -= NumBd;
+ RingPtr->PreCnt += NumBd;
+ Status = (LONG)(XST_SUCCESS);
+ }
+ return Status;
+}
+
+/*****************************************************************************/
+/**
+ * Fully or partially undo an XEmacPs_BdRingAlloc() operation. Use this
+ * function if all the BDs allocated by XEmacPs_BdRingAlloc() could not be
+ * transferred to hardware with XEmacPs_BdRingToHw().
+ *
+ * This function helps out in situations when an unrelated error occurs after
+ * BDs have been allocated but before they have been given to hardware.
+ * An example of this type of error would be an OS running out of resources.
+ *
+ * This function is not the same as XEmacPs_BdRingFree(). The Free function
+ * returns BDs to the free list after they have been processed by hardware,
+ * while UnAlloc returns them before being processed by hardware.
+ *
+ * There are two scenarios where this function can be used. Full UnAlloc or
+ * Partial UnAlloc. A Full UnAlloc means all the BDs Alloc'd will be returned:
+ *
+ * <pre>
+ * Status = XEmacPs_BdRingAlloc(MyRingPtr, 10, &BdPtr),
+ * ...
+ * if (Error)
+ * {
+ * Status = XEmacPs_BdRingUnAlloc(MyRingPtr, 10, &BdPtr),
+ * }
+ * </pre>
+ *
+ * A partial UnAlloc means some of the BDs Alloc'd will be returned:
+ *
+ * <pre>
+ * Status = XEmacPs_BdRingAlloc(MyRingPtr, 10, &BdPtr),
+ * BdsLeft = 10,
+ * CurBdPtr = BdPtr,
+ *
+ * while (BdsLeft)
+ * {
+ * if (Error)
+ * {
+ * Status = XEmacPs_BdRingUnAlloc(MyRingPtr, BdsLeft, CurBdPtr),
+ * }
+ *
+ * CurBdPtr = XEmacPs_BdRingNext(MyRingPtr, CurBdPtr),
+ * BdsLeft--,
+ * }
+ * </pre>
+ *
+ * A partial UnAlloc must include the last BD in the list that was Alloc'd.
+ *
+ * @param RingPtr is a pointer to the instance to be worked on.
+ * @param NumBd is the number of BDs to allocate
+ * @param BdSetPtr is an output parameter, it points to the first BD available
+ * for modification.
+ *
+ * @return
+ * - XST_SUCCESS if the BDs were unallocated.
+ * - XST_FAILURE if NumBd parameter was greater that the number of BDs in
+ * the preprocessing state.
+ *
+ * @note This function should not be preempted by another XEmacPs_Bd function
+ * call that modifies the BD space. It is the caller's responsibility to
+ * provide a mutual exclusion mechanism.
+ *
+ *****************************************************************************/
+LONG XEmacPs_BdRingUnAlloc(XEmacPs_BdRing * RingPtr, u32 NumBd,
+ XEmacPs_Bd * BdSetPtr)
+{
+ LONG Status;
+ (void) BdSetPtr;
+ Xil_AssertNonvoid(RingPtr != NULL);
+ Xil_AssertNonvoid(BdSetPtr != NULL);
+
+ /* Enough BDs in the free state for the request? */
+ if (RingPtr->PreCnt < NumBd) {
+ Status = (LONG)(XST_FAILURE);
+ } else {
+ /* Set the return argument and move FreeHead backward */
+ XEMACPS_RING_SEEKBACK(RingPtr, (RingPtr->FreeHead), NumBd);
+ RingPtr->FreeCnt += NumBd;
+ RingPtr->PreCnt -= NumBd;
+ Status = (LONG)(XST_SUCCESS);
+ }
+ return Status;
+}
+
+
+/*****************************************************************************/
+/**
+ * Enqueue a set of BDs to hardware that were previously allocated by
+ * XEmacPs_BdRingAlloc(). Once this function returns, the argument BD set goes
+ * under hardware control. Any changes made to these BDs after this point will
+ * corrupt the BD list leading to data corruption and system instability.
+ *
+ * The set will be rejected if the last BD of the set does not mark the end of
+ * a packet (see XEmacPs_BdSetLast()).
+ *
+ * @param RingPtr is a pointer to the instance to be worked on.
+ * @param NumBd is the number of BDs in the set.
+ * @param BdSetPtr is the first BD of the set to commit to hardware.
+ *
+ * @return
+ * - XST_SUCCESS if the set of BDs was accepted and enqueued to hardware.
+ * - XST_FAILURE if the set of BDs was rejected because the last BD of the set
+ * did not have its "last" bit set.
+ * - XST_DMA_SG_LIST_ERROR if this function was called out of sequence with
+ * XEmacPs_BdRingAlloc().
+ *
+ * @note This function should not be preempted by another XEmacPs_Bd function
+ * call that modifies the BD space. It is the caller's responsibility to
+ * provide a mutual exclusion mechanism.
+ *
+ *****************************************************************************/
+LONG XEmacPs_BdRingToHw(XEmacPs_BdRing * RingPtr, u32 NumBd,
+ XEmacPs_Bd * BdSetPtr)
+{
+ XEmacPs_Bd *CurBdPtr;
+ u32 i;
+ LONG Status;
+ /* if no bds to process, simply return. */
+ if (0U == NumBd){
+ Status = (LONG)(XST_SUCCESS);
+ } else {
+ /* Make sure we are in sync with XEmacPs_BdRingAlloc() */
+ if ((RingPtr->PreCnt < NumBd) || (RingPtr->PreHead != BdSetPtr)) {
+ Status = (LONG)(XST_DMA_SG_LIST_ERROR);
+ } else {
+ CurBdPtr = BdSetPtr;
+ for (i = 0U; i < NumBd; i++) {
+ CurBdPtr = (XEmacPs_Bd *)((void *)XEmacPs_BdRingNext(RingPtr, CurBdPtr));
+ }
+ /* Adjust ring pointers & counters */
+ XEMACPS_RING_SEEKAHEAD(RingPtr, RingPtr->PreHead, NumBd);
+ RingPtr->PreCnt -= NumBd;
+ RingPtr->HwTail = CurBdPtr;
+ RingPtr->HwCnt += NumBd;
+
+ Status = (LONG)(XST_SUCCESS);
+ }
+ }
+ return Status;
+}
+
+
+/*****************************************************************************/
+/**
+ * Returns a set of BD(s) that have been processed by hardware. The returned
+ * BDs may be examined to determine the outcome of the DMA transaction(s).
+ * Once the BDs have been examined, the user must call XEmacPs_BdRingFree()
+ * in the same order which they were retrieved here. Example:
+ *
+ * <pre>
+ * NumBd = XEmacPs_BdRingFromHwTx(MyRingPtr, MaxBd, &MyBdSet),
+ * if (NumBd == 0)
+ * {
+ * * hardware has nothing ready for us yet*
+ * }
+ *
+ * CurBd = MyBdSet,
+ * for (i=0; i<NumBd; i++)
+ * {
+ * * Examine CurBd for post processing *.....
+ *
+ * * Onto next BD *
+ * CurBd = XEmacPs_BdRingNext(MyRingPtr, CurBd),
+ * }
+ *
+ * XEmacPs_BdRingFree(MyRingPtr, NumBd, MyBdSet), *Return list*
+ * }
+ * </pre>
+ *
+ * A more advanced use of this function may allocate multiple sets of BDs.
+ * They must be retrieved from hardware and freed in the correct sequence:
+ * <pre>
+ * * Legal *
+ * XEmacPs_BdRingFromHwTx(MyRingPtr, NumBd1, &MySet1),
+ * XEmacPs_BdRingFree(MyRingPtr, NumBd1, MySet1),
+ *
+ * * Legal *
+ * XEmacPs_BdRingFromHwTx(MyRingPtr, NumBd1, &MySet1),
+ * XEmacPs_BdRingFromHwTx(MyRingPtr, NumBd2, &MySet2),
+ * XEmacPs_BdRingFree(MyRingPtr, NumBd1, MySet1),
+ * XEmacPs_BdRingFree(MyRingPtr, NumBd2, MySet2),
+ *
+ * * Not legal *
+ * XEmacPs_BdRingFromHwTx(MyRingPtr, NumBd1, &MySet1),
+ * XEmacPs_BdRingFromHwTx(MyRingPtr, NumBd2, &MySet2),
+ * XEmacPs_BdRingFree(MyRingPtr, NumBd2, MySet2),
+ * XEmacPs_BdRingFree(MyRingPtr, NumBd1, MySet1),
+ * </pre>
+ *
+ * If hardware has only partially completed a packet spanning multiple BDs,
+ * then none of the BDs for that packet will be included in the results.
+ *
+ * @param RingPtr is a pointer to the instance to be worked on.
+ * @param BdLimit is the maximum number of BDs to return in the set.
+ * @param BdSetPtr is an output parameter, it points to the first BD available
+ * for examination.
+ *
+ * @return
+ * The number of BDs processed by hardware. A value of 0 indicates that no
+ * data is available. No more than BdLimit BDs will be returned.
+ *
+ * @note Treat BDs returned by this function as read-only.
+ *
+ * @note This function should not be preempted by another XEmacPs_Bd function
+ * call that modifies the BD space. It is the caller's responsibility to
+ * provide a mutual exclusion mechanism.
+ *
+ *****************************************************************************/
+u32 XEmacPs_BdRingFromHwTx(XEmacPs_BdRing * RingPtr, u32 BdLimit,
+ XEmacPs_Bd ** BdSetPtr)
+{
+ XEmacPs_Bd *CurBdPtr;
+ u32 BdStr = 0U;
+ u32 BdCount;
+ u32 BdPartialCount;
+ u32 Sop = 0U;
+ u32 Status;
+ u32 BdLimitLoc = BdLimit;
+ CurBdPtr = RingPtr->HwHead;
+ BdCount = 0U;
+ BdPartialCount = 0U;
+
+ /* If no BDs in work group, then there's nothing to search */
+ if (RingPtr->HwCnt == 0x00000000U) {
+ *BdSetPtr = NULL;
+ Status = 0U;
+ } else {
+
+ if (BdLimitLoc > RingPtr->HwCnt){
+ BdLimitLoc = RingPtr->HwCnt;
+ }
+ /* Starting at HwHead, keep moving forward in the list until:
+ * - A BD is encountered with its new/used bit set which means
+ * hardware has not completed processing of that BD.
+ * - RingPtr->HwTail is reached and RingPtr->HwCnt is reached.
+ * - The number of requested BDs has been processed
+ */
+ while (BdCount < BdLimitLoc) {
+ /* Read the status */
+ if(CurBdPtr != NULL){
+ BdStr = XEmacPs_BdRead(CurBdPtr, XEMACPS_BD_STAT_OFFSET);
+ }
+
+ if ((Sop == 0x00000000U) && ((BdStr & XEMACPS_TXBUF_USED_MASK)!=0x00000000U)){
+ Sop = 1U;
+ }
+ if (Sop == 0x00000001U) {
+ BdCount++;
+ BdPartialCount++;
+ }
+
+ /* hardware has processed this BD so check the "last" bit.
+ * If it is clear, then there are more BDs for the current
+ * packet. Keep a count of these partial packet BDs.
+ */
+ if ((Sop == 0x00000001U) && ((BdStr & XEMACPS_TXBUF_LAST_MASK)!=0x00000000U)) {
+ Sop = 0U;
+ BdPartialCount = 0U;
+ }
+
+ /* Move on to next BD in work group */
+ CurBdPtr = XEmacPs_BdRingNext(RingPtr, CurBdPtr);
+ }
+
+ /* Subtract off any partial packet BDs found */
+ BdCount -= BdPartialCount;
+
+ /* If BdCount is non-zero then BDs were found to return. Set return
+ * parameters, update pointers and counters, return success
+ */
+ if (BdCount > 0x00000000U) {
+ *BdSetPtr = RingPtr->HwHead;
+ RingPtr->HwCnt -= BdCount;
+ RingPtr->PostCnt += BdCount;
+ XEMACPS_RING_SEEKAHEAD(RingPtr, RingPtr->HwHead, BdCount);
+ Status = (BdCount);
+ } else {
+ *BdSetPtr = NULL;
+ Status = 0U;
+ }
+ }
+ return Status;
+}
+
+
+/*****************************************************************************/
+/**
+ * Returns a set of BD(s) that have been processed by hardware. The returned
+ * BDs may be examined to determine the outcome of the DMA transaction(s).
+ * Once the BDs have been examined, the user must call XEmacPs_BdRingFree()
+ * in the same order which they were retrieved here. Example:
+ *
+ * <pre>
+ * NumBd = XEmacPs_BdRingFromHwRx(MyRingPtr, MaxBd, &MyBdSet),
+ *
+ * if (NumBd == 0)
+ * {
+ * *hardware has nothing ready for us yet*
+ * }
+ *
+ * CurBd = MyBdSet,
+ * for (i=0; i<NumBd; i++)
+ * {
+ * * Examine CurBd for post processing *.....
+ *
+ * * Onto next BD *
+ * CurBd = XEmacPs_BdRingNext(MyRingPtr, CurBd),
+ * }
+ *
+ * XEmacPs_BdRingFree(MyRingPtr, NumBd, MyBdSet), * Return list *
+ * }
+ * </pre>
+ *
+ * A more advanced use of this function may allocate multiple sets of BDs.
+ * They must be retrieved from hardware and freed in the correct sequence:
+ * <pre>
+ * * Legal *
+ * XEmacPs_BdRingFromHwRx(MyRingPtr, NumBd1, &MySet1),
+ * XEmacPs_BdRingFree(MyRingPtr, NumBd1, MySet1),
+ *
+ * * Legal *
+ * XEmacPs_BdRingFromHwRx(MyRingPtr, NumBd1, &MySet1),
+ * XEmacPs_BdRingFromHwRx(MyRingPtr, NumBd2, &MySet2),
+ * XEmacPs_BdRingFree(MyRingPtr, NumBd1, MySet1),
+ * XEmacPs_BdRingFree(MyRingPtr, NumBd2, MySet2),
+ *
+ * * Not legal *
+ * XEmacPs_BdRingFromHwRx(MyRingPtr, NumBd1, &MySet1),
+ * XEmacPs_BdRingFromHwRx(MyRingPtr, NumBd2, &MySet2),
+ * XEmacPs_BdRingFree(MyRingPtr, NumBd2, MySet2),
+ * XEmacPs_BdRingFree(MyRingPtr, NumBd1, MySet1),
+ * </pre>
+ *
+ * If hardware has only partially completed a packet spanning multiple BDs,
+ * then none of the BDs for that packet will be included in the results.
+ *
+ * @param RingPtr is a pointer to the instance to be worked on.
+ * @param BdLimit is the maximum number of BDs to return in the set.
+ * @param BdSetPtr is an output parameter, it points to the first BD available
+ * for examination.
+ *
+ * @return
+ * The number of BDs processed by hardware. A value of 0 indicates that no
+ * data is available. No more than BdLimit BDs will be returned.
+ *
+ * @note Treat BDs returned by this function as read-only.
+ *
+ * @note This function should not be preempted by another XEmacPs_Bd function
+ * call that modifies the BD space. It is the caller's responsibility to
+ * provide a mutual exclusion mechanism.
+ *
+ *****************************************************************************/
+u32 XEmacPs_BdRingFromHwRx(XEmacPs_BdRing * RingPtr, u32 BdLimit,
+ XEmacPs_Bd ** BdSetPtr)
+{
+ XEmacPs_Bd *CurBdPtr;
+ u32 BdStr = 0U;
+ u32 BdCount;
+ u32 BdPartialCount;
+ u32 Status;
+
+ CurBdPtr = RingPtr->HwHead;
+ BdCount = 0U;
+ BdPartialCount = 0U;
+
+ /* If no BDs in work group, then there's nothing to search */
+ if (RingPtr->HwCnt == 0x00000000U) {
+ *BdSetPtr = NULL;
+ Status = 0U;
+ } else {
+
+ /* Starting at HwHead, keep moving forward in the list until:
+ * - A BD is encountered with its new/used bit set which means
+ * hardware has completed processing of that BD.
+ * - RingPtr->HwTail is reached and RingPtr->HwCnt is reached.
+ * - The number of requested BDs has been processed
+ */
+ while (BdCount < BdLimit) {
+
+ /* Read the status */
+ if(CurBdPtr!=NULL){
+ BdStr = XEmacPs_BdRead(CurBdPtr, XEMACPS_BD_STAT_OFFSET);
+ }
+ if ((!(XEmacPs_BdIsRxNew(CurBdPtr)))==TRUE) {
+ break;
+ }
+
+ BdCount++;
+
+ /* hardware has processed this BD so check the "last" bit. If
+ * it is clear, then there are more BDs for the current packet.
+ * Keep a count of these partial packet BDs.
+ */
+ if ((BdStr & XEMACPS_RXBUF_EOF_MASK)!=0x00000000U) {
+ BdPartialCount = 0U;
+ } else {
+ BdPartialCount++;
+ }
+
+ /* Move on to next BD in work group */
+ CurBdPtr = XEmacPs_BdRingNext(RingPtr, CurBdPtr);
+ }
+
+ /* Subtract off any partial packet BDs found */
+ BdCount -= BdPartialCount;
+
+ /* If BdCount is non-zero then BDs were found to return. Set return
+ * parameters, update pointers and counters, return success
+ */
+ if (BdCount > 0x00000000U) {
+ *BdSetPtr = RingPtr->HwHead;
+ RingPtr->HwCnt -= BdCount;
+ RingPtr->PostCnt += BdCount;
+ XEMACPS_RING_SEEKAHEAD(RingPtr, RingPtr->HwHead, BdCount);
+ Status = (BdCount);
+ }
+ else {
+ *BdSetPtr = NULL;
+ Status = 0U;
+ }
+}
+ return Status;
+}
+
+
+/*****************************************************************************/
+/**
+ * Frees a set of BDs that had been previously retrieved with
+ * XEmacPs_BdRingFromHw().
+ *
+ * @param RingPtr is a pointer to the instance to be worked on.
+ * @param NumBd is the number of BDs to free.
+ * @param BdSetPtr is the head of a list of BDs returned by
+ * XEmacPs_BdRingFromHw().
+ *
+ * @return
+ * - XST_SUCCESS if the set of BDs was freed.
+ * - XST_DMA_SG_LIST_ERROR if this function was called out of sequence with
+ * XEmacPs_BdRingFromHw().
+ *
+ * @note This function should not be preempted by another XEmacPs_Bd function
+ * call that modifies the BD space. It is the caller's responsibility to
+ * provide a mutual exclusion mechanism.
+ *
+ *****************************************************************************/
+LONG XEmacPs_BdRingFree(XEmacPs_BdRing * RingPtr, u32 NumBd,
+ XEmacPs_Bd * BdSetPtr)
+{
+ LONG Status;
+ /* if no bds to process, simply return. */
+ if (0x00000000U == NumBd){
+ Status = (LONG)(XST_SUCCESS);
+ } else {
+ /* Make sure we are in sync with XEmacPs_BdRingFromHw() */
+ if ((RingPtr->PostCnt < NumBd) || (RingPtr->PostHead != BdSetPtr)) {
+ Status = (LONG)(XST_DMA_SG_LIST_ERROR);
+ } else {
+ /* Update pointers and counters */
+ RingPtr->FreeCnt += NumBd;
+ RingPtr->PostCnt -= NumBd;
+ XEMACPS_RING_SEEKAHEAD(RingPtr, RingPtr->PostHead, NumBd);
+ Status = (LONG)(XST_SUCCESS);
+ }
+ }
+ return Status;
+}
+
+
+/*****************************************************************************/
+/**
+ * Check the internal data structures of the BD ring for the provided channel.
+ * The following checks are made:
+ *
+ * - Is the BD ring linked correctly in physical address space.
+ * - Do the internal pointers point to BDs in the ring.
+ * - Do the internal counters add up.
+ *
+ * The channel should be stopped prior to calling this function.
+ *
+ * @param RingPtr is a pointer to the instance to be worked on.
+ * @param Direction is either XEMACPS_SEND or XEMACPS_RECV that indicates
+ * which direction.
+ *
+ * @return
+ * - XST_SUCCESS if the set of BDs was freed.
+ * - XST_DMA_SG_NO_LIST if the list has not been created.
+ * - XST_IS_STARTED if the channel is not stopped.
+ * - XST_DMA_SG_LIST_ERROR if a problem is found with the internal data
+ * structures. If this value is returned, the channel should be reset to
+ * avoid data corruption or system instability.
+ *
+ * @note This function should not be preempted by another XEmacPs_Bd function
+ * call that modifies the BD space. It is the caller's responsibility to
+ * provide a mutual exclusion mechanism.
+ *
+ *****************************************************************************/
+LONG XEmacPs_BdRingCheck(XEmacPs_BdRing * RingPtr, u8 Direction)
+{
+ UINTPTR AddrV, AddrP;
+ u32 i;
+
+ if ((Direction != (u8)XEMACPS_SEND) && (Direction != (u8)XEMACPS_RECV)) {
+ return (LONG)(XST_INVALID_PARAM);
+ }
+
+ /* Is the list created */
+ if (RingPtr->AllCnt == 0x00000000U) {
+ return (LONG)(XST_DMA_SG_NO_LIST);
+ }
+
+ /* Can't check if channel is running */
+ if (RingPtr->RunState == (u32)XST_DMA_SG_IS_STARTED) {
+ return (LONG)(XST_IS_STARTED);
+ }
+
+ /* RunState doesn't make sense */
+ if (RingPtr->RunState != (u32)XST_DMA_SG_IS_STOPPED) {
+ return (LONG)(XST_DMA_SG_LIST_ERROR);
+ }
+
+ /* Verify internal pointers point to correct memory space */
+ AddrV = (UINTPTR) RingPtr->FreeHead;
+ if ((AddrV < RingPtr->BaseBdAddr) || (AddrV > RingPtr->HighBdAddr)) {
+ return (LONG)(XST_DMA_SG_LIST_ERROR);
+ }
+
+ AddrV = (UINTPTR) RingPtr->PreHead;
+ if ((AddrV < RingPtr->BaseBdAddr) || (AddrV > RingPtr->HighBdAddr)) {
+ return (LONG)(XST_DMA_SG_LIST_ERROR);
+ }
+
+ AddrV = (UINTPTR) RingPtr->HwHead;
+ if ((AddrV < RingPtr->BaseBdAddr) || (AddrV > RingPtr->HighBdAddr)) {
+ return (LONG)(XST_DMA_SG_LIST_ERROR);
+ }
+
+ AddrV = (UINTPTR) RingPtr->HwTail;
+ if ((AddrV < RingPtr->BaseBdAddr) || (AddrV > RingPtr->HighBdAddr)) {
+ return (LONG)(XST_DMA_SG_LIST_ERROR);
+ }
+
+ AddrV = (UINTPTR) RingPtr->PostHead;
+ if ((AddrV < RingPtr->BaseBdAddr) || (AddrV > RingPtr->HighBdAddr)) {
+ return (LONG)(XST_DMA_SG_LIST_ERROR);
+ }
+
+ /* Verify internal counters add up */
+ if ((RingPtr->HwCnt + RingPtr->PreCnt + RingPtr->FreeCnt +
+ RingPtr->PostCnt) != RingPtr->AllCnt) {
+ return (LONG)(XST_DMA_SG_LIST_ERROR);
+ }
+
+ /* Verify BDs are linked correctly */
+ AddrV = RingPtr->BaseBdAddr;
+ AddrP = RingPtr->PhysBaseAddr + RingPtr->Separation;
+
+ for (i = 1U; i < RingPtr->AllCnt; i++) {
+ /* Check BDA for this BD. It should point to next physical addr */
+ if (XEmacPs_BdRead(AddrV, XEMACPS_BD_ADDR_OFFSET) != AddrP) {
+ return (LONG)(XST_DMA_SG_LIST_ERROR);
+ }
+
+ /* Move on to next BD */
+ AddrV += RingPtr->Separation;
+ AddrP += RingPtr->Separation;
+ }
+
+ /* Last BD should have wrap bit set */
+ if (XEMACPS_SEND == Direction) {
+ if ((!XEmacPs_BdIsTxWrap(AddrV))==TRUE) {
+ return (LONG)(XST_DMA_SG_LIST_ERROR);
+ }
+ }
+ else { /* XEMACPS_RECV */
+ if ((!XEmacPs_BdIsRxWrap(AddrV))==TRUE) {
+ return (LONG)(XST_DMA_SG_LIST_ERROR);
+ }
+ }
+
+ /* No problems found */
+ return (LONG)(XST_SUCCESS);
+}
+
+/*****************************************************************************/
+/**
+ * Set this bit to mark the last descriptor in the receive buffer descriptor
+ * list.
+ *
+ * @param BdPtr is the BD pointer to operate on
+ *
+ * @note
+ * C-style signature:
+ * void XEmacPs_BdSetRxWrap(XEmacPs_Bd* BdPtr)
+ *
+ *****************************************************************************/
+static void XEmacPs_BdSetRxWrap(UINTPTR BdPtr)
+{
+ u32 DataValueRx;
+ u32 *TempPtr;
+
+ BdPtr += (u32)(XEMACPS_BD_ADDR_OFFSET);
+ TempPtr = (u32 *)BdPtr;
+ if(TempPtr != NULL) {
+ DataValueRx = *TempPtr;
+ DataValueRx |= XEMACPS_RXBUF_WRAP_MASK;
+ *TempPtr = DataValueRx;
+ }
+}
+
+/*****************************************************************************/
+/**
+ * Sets this bit to mark the last descriptor in the transmit buffer
+ * descriptor list.
+ *
+ * @param BdPtr is the BD pointer to operate on
+ *
+ * @note
+ * C-style signature:
+ * void XEmacPs_BdSetTxWrap(XEmacPs_Bd* BdPtr)
+ *
+ *****************************************************************************/
+static void XEmacPs_BdSetTxWrap(UINTPTR BdPtr)
+{
+ u32 DataValueTx;
+ u32 *TempPtr;
+
+ BdPtr += (u32)(XEMACPS_BD_STAT_OFFSET);
+ TempPtr = (u32 *)BdPtr;
+ if(TempPtr != NULL) {
+ DataValueTx = *TempPtr;
+ DataValueTx |= XEMACPS_TXBUF_WRAP_MASK;
+ *TempPtr = DataValueTx;
+ }
+}
+
+/*****************************************************************************/
+/**
+ * Reset BD ring head and tail pointers.
+ *
+ * @param RingPtr is the instance to be worked on.
+ * @param virtaddrloc is the virtual base address of the user memory region.
+ *
+ * @note
+ * Should be called after XEmacPs_Stop()
+ *
+ * @note
+ * C-style signature:
+ * void XEmacPs_BdRingPtrReset(XEmacPs_BdRing * RingPtr, void *virtaddrloc)
+ *
+ *****************************************************************************/
+void XEmacPs_BdRingPtrReset(XEmacPs_BdRing * RingPtr, void *virtaddrloc)
+{
+ RingPtr->FreeHead = virtaddrloc;
+ RingPtr->PreHead = virtaddrloc;
+ RingPtr->HwHead = virtaddrloc;
+ RingPtr->HwTail = virtaddrloc;
+ RingPtr->PostHead = virtaddrloc;
+}
+
+/** @} */
diff --git a/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/emacps_v3_10/src/xemacps_bdring.h b/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/emacps_v3_10/src/xemacps_bdring.h
new file mode 100644
index 0000000..2bc74f7
--- /dev/null
+++ b/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/emacps_v3_10/src/xemacps_bdring.h
@@ -0,0 +1,235 @@
+/******************************************************************************
+*
+* Copyright (C) 2010 - 2019 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+* THE SOFTWARE.
+*
+*
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xemacps_bdring.h
+* @addtogroup emacps_v3_10
+* @{
+*
+* The Xiline EmacPs Buffer Descriptor ring driver. This is part of EmacPs
+* DMA functionalities.
+*
+* <pre>
+* MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ----- ---- -------- -------------------------------------------------------
+* 1.00a wsy 01/10/10 First release
+* 2.1 srt 07/15/14 Add support for Zynq Ultrascale Mp architecture.
+* 3.0 kvn 02/13/15 Modified code for MISRA-C:2012 compliance.
+* 3.6 rb 09/08/17 HwCnt variable (in XEmacPs_BdRing structure) is
+* changed to volatile.
+*
+* </pre>
+*
+******************************************************************************/
+
+#ifndef XEMACPS_BDRING_H /* prevent curcular inclusions */
+#define XEMACPS_BDRING_H /* by using protection macros */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+
+/**************************** Type Definitions *******************************/
+
+/** This is an internal structure used to maintain the DMA list */
+typedef struct {
+ UINTPTR PhysBaseAddr;/**< Physical address of 1st BD in list */
+ UINTPTR BaseBdAddr; /**< Virtual address of 1st BD in list */
+ UINTPTR HighBdAddr; /**< Virtual address of last BD in the list */
+ u32 Length; /**< Total size of ring in bytes */
+ u32 RunState; /**< Flag to indicate DMA is started */
+ u32 Separation; /**< Number of bytes between the starting address
+ of adjacent BDs */
+ XEmacPs_Bd *FreeHead;
+ /**< First BD in the free group */
+ XEmacPs_Bd *PreHead;/**< First BD in the pre-work group */
+ XEmacPs_Bd *HwHead; /**< First BD in the work group */
+ XEmacPs_Bd *HwTail; /**< Last BD in the work group */
+ XEmacPs_Bd *PostHead;
+ /**< First BD in the post-work group */
+ XEmacPs_Bd *BdaRestart;
+ /**< BDA to load when channel is started */
+
+ volatile u32 HwCnt; /**< Number of BDs in work group */
+ u32 PreCnt; /**< Number of BDs in pre-work group */
+ u32 FreeCnt; /**< Number of allocatable BDs in the free group */
+ u32 PostCnt; /**< Number of BDs in post-work group */
+ u32 AllCnt; /**< Total Number of BDs for channel */
+} XEmacPs_BdRing;
+
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/*****************************************************************************/
+/**
+* Use this macro at initialization time to determine how many BDs will fit
+* in a BD list within the given memory constraints.
+*
+* The results of this macro can be provided to XEmacPs_BdRingCreate().
+*
+* @param Alignment specifies what byte alignment the BDs must fall on and
+* must be a power of 2 to get an accurate calculation (32, 64, 128,...)
+* @param Bytes is the number of bytes to be used to store BDs.
+*
+* @return Number of BDs that can fit in the given memory area
+*
+* @note
+* C-style signature:
+* u32 XEmacPs_BdRingCntCalc(u32 Alignment, u32 Bytes)
+*
+******************************************************************************/
+#define XEmacPs_BdRingCntCalc(Alignment, Bytes) \
+ (u32)((Bytes) / (sizeof(XEmacPs_Bd)))
+
+/*****************************************************************************/
+/**
+* Use this macro at initialization time to determine how many bytes of memory
+* is required to contain a given number of BDs at a given alignment.
+*
+* @param Alignment specifies what byte alignment the BDs must fall on. This
+* parameter must be a power of 2 to get an accurate calculation (32, 64,
+* 128,...)
+* @param NumBd is the number of BDs to calculate memory size requirements for
+*
+* @return The number of bytes of memory required to create a BD list with the
+* given memory constraints.
+*
+* @note
+* C-style signature:
+* u32 XEmacPs_BdRingMemCalc(u32 Alignment, u32 NumBd)
+*
+******************************************************************************/
+#define XEmacPs_BdRingMemCalc(Alignment, NumBd) \
+ (u32)(sizeof(XEmacPs_Bd) * (NumBd))
+
+/****************************************************************************/
+/**
+* Return the total number of BDs allocated by this channel with
+* XEmacPs_BdRingCreate().
+*
+* @param RingPtr is the DMA channel to operate on.
+*
+* @return The total number of BDs allocated for this channel.
+*
+* @note
+* C-style signature:
+* u32 XEmacPs_BdRingGetCnt(XEmacPs_BdRing* RingPtr)
+*
+*****************************************************************************/
+#define XEmacPs_BdRingGetCnt(RingPtr) ((RingPtr)->AllCnt)
+
+/****************************************************************************/
+/**
+* Return the number of BDs allocatable with XEmacPs_BdRingAlloc() for pre-
+* processing.
+*
+* @param RingPtr is the DMA channel to operate on.
+*
+* @return The number of BDs currently allocatable.
+*
+* @note
+* C-style signature:
+* u32 XEmacPs_BdRingGetFreeCnt(XEmacPs_BdRing* RingPtr)
+*
+*****************************************************************************/
+#define XEmacPs_BdRingGetFreeCnt(RingPtr) ((RingPtr)->FreeCnt)
+
+/****************************************************************************/
+/**
+* Return the next BD from BdPtr in a list.
+*
+* @param RingPtr is the DMA channel to operate on.
+* @param BdPtr is the BD to operate on.
+*
+* @return The next BD in the list relative to the BdPtr parameter.
+*
+* @note
+* C-style signature:
+* XEmacPs_Bd *XEmacPs_BdRingNext(XEmacPs_BdRing* RingPtr,
+* XEmacPs_Bd *BdPtr)
+*
+*****************************************************************************/
+#define XEmacPs_BdRingNext(RingPtr, BdPtr) \
+ (((UINTPTR)((void *)(BdPtr)) >= (RingPtr)->HighBdAddr) ? \
+ (XEmacPs_Bd*)((void*)(RingPtr)->BaseBdAddr) : \
+ (XEmacPs_Bd*)((UINTPTR)((void *)(BdPtr)) + (RingPtr)->Separation))
+
+/****************************************************************************/
+/**
+* Return the previous BD from BdPtr in the list.
+*
+* @param RingPtr is the DMA channel to operate on.
+* @param BdPtr is the BD to operate on
+*
+* @return The previous BD in the list relative to the BdPtr parameter.
+*
+* @note
+* C-style signature:
+* XEmacPs_Bd *XEmacPs_BdRingPrev(XEmacPs_BdRing* RingPtr,
+* XEmacPs_Bd *BdPtr)
+*
+*****************************************************************************/
+#define XEmacPs_BdRingPrev(RingPtr, BdPtr) \
+ (((UINTPTR)(BdPtr) <= (RingPtr)->BaseBdAddr) ? \
+ (XEmacPs_Bd*)(RingPtr)->HighBdAddr : \
+ (XEmacPs_Bd*)((UINTPTR)(BdPtr) - (RingPtr)->Separation))
+
+/************************** Function Prototypes ******************************/
+
+/*
+ * Scatter gather DMA related functions in xemacps_bdring.c
+ */
+LONG XEmacPs_BdRingCreate(XEmacPs_BdRing * RingPtr, UINTPTR PhysAddr,
+ UINTPTR VirtAddr, u32 Alignment, u32 BdCount);
+LONG XEmacPs_BdRingClone(XEmacPs_BdRing * RingPtr, XEmacPs_Bd * SrcBdPtr,
+ u8 Direction);
+LONG XEmacPs_BdRingAlloc(XEmacPs_BdRing * RingPtr, u32 NumBd,
+ XEmacPs_Bd ** BdSetPtr);
+LONG XEmacPs_BdRingUnAlloc(XEmacPs_BdRing * RingPtr, u32 NumBd,
+ XEmacPs_Bd * BdSetPtr);
+LONG XEmacPs_BdRingToHw(XEmacPs_BdRing * RingPtr, u32 NumBd,
+ XEmacPs_Bd * BdSetPtr);
+LONG XEmacPs_BdRingFree(XEmacPs_BdRing * RingPtr, u32 NumBd,
+ XEmacPs_Bd * BdSetPtr);
+u32 XEmacPs_BdRingFromHwTx(XEmacPs_BdRing * RingPtr, u32 BdLimit,
+ XEmacPs_Bd ** BdSetPtr);
+u32 XEmacPs_BdRingFromHwRx(XEmacPs_BdRing * RingPtr, u32 BdLimit,
+ XEmacPs_Bd ** BdSetPtr);
+LONG XEmacPs_BdRingCheck(XEmacPs_BdRing * RingPtr, u8 Direction);
+
+void XEmacPs_BdRingPtrReset(XEmacPs_BdRing * RingPtr, void *virtaddrloc);
+
+#ifdef __cplusplus
+}
+#endif
+
+
+#endif /* end of protection macros */
+/** @} */
diff --git a/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/emacps_v3_10/src/xemacps_control.c b/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/emacps_v3_10/src/xemacps_control.c
new file mode 100644
index 0000000..3a892f1
--- /dev/null
+++ b/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/emacps_v3_10/src/xemacps_control.c
@@ -0,0 +1,1153 @@
+/******************************************************************************
+*
+* Copyright (C) 2009 - 2019 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+* THE SOFTWARE.
+*
+*
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+ *
+ * @file xemacps_control.c
+* @addtogroup emacps_v3_10
+* @{
+ *
+ * Functions in this file implement general purpose command and control related
+ * functionality. See xemacps.h for a detailed description of the driver.
+ *
+ * <pre>
+ * MODIFICATION HISTORY:
+ *
+ * Ver Who Date Changes
+ * ----- ---- -------- -------------------------------------------------------
+ * 1.00a wsy 01/10/10 First release
+ * 1.02a asa 11/05/12 Added a new API for deleting an entry from the HASH
+ * register. Added a new API for setting the BURST length
+ * in DMACR register.
+ * 2.1 srt 07/15/14 Add support for Zynq Ultrascale Mp architecture.
+ * 3.0 kvn 02/13/15 Modified code for MISRA-C:2012 compliance.
+ * 3.0 hk 02/20/15 Added support for jumbo frames.
+ * 3.2 hk 02/22/16 Added SGMII support for Zynq Ultrascale+ MPSoC.
+ * </pre>
+ *****************************************************************************/
+
+/***************************** Include Files *********************************/
+
+#include "xemacps.h"
+
+/************************** Constant Definitions *****************************/
+
+
+/**************************** Type Definitions *******************************/
+
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+
+/************************** Function Prototypes ******************************/
+
+
+/************************** Variable Definitions *****************************/
+
+
+/*****************************************************************************/
+/**
+ * Set the MAC address for this driver/device. The address is a 48-bit value.
+ * The device must be stopped before calling this function.
+ *
+ * @param InstancePtr is a pointer to the instance to be worked on.
+ * @param AddressPtr is a pointer to a 6-byte MAC address.
+ * @param Index is a index to which MAC (1-4) address.
+ *
+ * @return
+ * - XST_SUCCESS if the MAC address was set successfully
+ * - XST_DEVICE_IS_STARTED if the device has not yet been stopped
+ *
+ *****************************************************************************/
+LONG XEmacPs_SetMacAddress(XEmacPs *InstancePtr, void *AddressPtr, u8 Index)
+{
+ u32 MacAddr;
+ u8 *Aptr = (u8 *)(void *)AddressPtr;
+ u8 IndexLoc = Index;
+ LONG Status;
+ Xil_AssertNonvoid(InstancePtr != NULL);
+ Xil_AssertNonvoid(Aptr != NULL);
+ Xil_AssertNonvoid(InstancePtr->IsReady == (u32)XIL_COMPONENT_IS_READY);
+ Xil_AssertNonvoid((IndexLoc <= (u8)XEMACPS_MAX_MAC_ADDR) && (IndexLoc > 0x00U));
+
+ /* Be sure device has been stopped */
+ if (InstancePtr->IsStarted == (u32)XIL_COMPONENT_IS_STARTED) {
+ Status = (LONG)(XST_DEVICE_IS_STARTED);
+ }
+ else{
+ /* Index ranges 1 to 4, for offset calculation is 0 to 3. */
+ IndexLoc--;
+
+ /* Set the MAC bits [31:0] in BOT */
+ MacAddr = *(Aptr);
+ MacAddr |= ((u32)(*(Aptr+1)) << 8U);
+ MacAddr |= ((u32)(*(Aptr+2)) << 16U);
+ MacAddr |= ((u32)(*(Aptr+3)) << 24U);
+ XEmacPs_WriteReg(InstancePtr->Config.BaseAddress,
+ ((u32)XEMACPS_LADDR1L_OFFSET + ((u32)IndexLoc * (u32)8)), MacAddr);
+
+ /* There are reserved bits in TOP so don't affect them */
+ MacAddr = XEmacPs_ReadReg(InstancePtr->Config.BaseAddress,
+ ((u32)XEMACPS_LADDR1H_OFFSET + ((u32)IndexLoc * (u32)8)));
+
+ MacAddr &= (u32)(~XEMACPS_LADDR_MACH_MASK);
+
+ /* Set MAC bits [47:32] in TOP */
+ MacAddr |= (u32)(*(Aptr+4));
+ MacAddr |= (u32)(*(Aptr+5)) << 8U;
+
+ XEmacPs_WriteReg(InstancePtr->Config.BaseAddress,
+ ((u32)XEMACPS_LADDR1H_OFFSET + ((u32)IndexLoc * (u32)8)), MacAddr);
+
+ Status = (LONG)(XST_SUCCESS);
+ }
+ return Status;
+}
+
+
+/*****************************************************************************/
+/**
+ * Get the MAC address for this driver/device.
+ *
+ * @param InstancePtr is a pointer to the instance to be worked on.
+ * @param AddressPtr is an output parameter, and is a pointer to a buffer into
+ * which the current MAC address will be copied.
+ * @param Index is a index to which MAC (1-4) address.
+ *
+ *****************************************************************************/
+void XEmacPs_GetMacAddress(XEmacPs *InstancePtr, void *AddressPtr, u8 Index)
+{
+ u32 MacAddr;
+ u8 *Aptr = (u8 *)(void *)AddressPtr;
+ u8 IndexLoc = Index;
+ Xil_AssertVoid(InstancePtr != NULL);
+ Xil_AssertVoid(Aptr != NULL);
+ Xil_AssertVoid(InstancePtr->IsReady == (u32)XIL_COMPONENT_IS_READY);
+ Xil_AssertVoid((IndexLoc <= (u8)XEMACPS_MAX_MAC_ADDR) && (IndexLoc > 0x00U));
+
+ /* Index ranges 1 to 4, for offset calculation is 0 to 3. */
+ IndexLoc--;
+
+ MacAddr = XEmacPs_ReadReg(InstancePtr->Config.BaseAddress,
+ ((u32)XEMACPS_LADDR1L_OFFSET + ((u32)IndexLoc * (u32)8)));
+ *Aptr = (u8) MacAddr;
+ *(Aptr+1) = (u8) (MacAddr >> 8U);
+ *(Aptr+2) = (u8) (MacAddr >> 16U);
+ *(Aptr+3) = (u8) (MacAddr >> 24U);
+
+ /* Read MAC bits [47:32] in TOP */
+ MacAddr = XEmacPs_ReadReg(InstancePtr->Config.BaseAddress,
+ ((u32)XEMACPS_LADDR1H_OFFSET + ((u32)IndexLoc * (u32)8)));
+ *(Aptr+4) = (u8) MacAddr;
+ *(Aptr+5) = (u8) (MacAddr >> 8U);
+}
+
+
+/*****************************************************************************/
+/**
+ * Set 48-bit MAC addresses in hash table.
+ * The device must be stopped before calling this function.
+ *
+ * The hash address register is 64 bits long and takes up two locations in
+ * the memory map. The least significant bits are stored in hash register
+ * bottom and the most significant bits in hash register top.
+ *
+ * The unicast hash enable and the multicast hash enable bits in the network
+ * configuration register enable the reception of hash matched frames. The
+ * destination address is reduced to a 6 bit index into the 64 bit hash
+ * register using the following hash function. The hash function is an XOR
+ * of every sixth bit of the destination address.
+ *
+ * <pre>
+ * hash_index[05] = da[05]^da[11]^da[17]^da[23]^da[29]^da[35]^da[41]^da[47]
+ * hash_index[04] = da[04]^da[10]^da[16]^da[22]^da[28]^da[34]^da[40]^da[46]
+ * hash_index[03] = da[03]^da[09]^da[15]^da[21]^da[27]^da[33]^da[39]^da[45]
+ * hash_index[02] = da[02]^da[08]^da[14]^da[20]^da[26]^da[32]^da[38]^da[44]
+ * hash_index[01] = da[01]^da[07]^da[13]^da[19]^da[25]^da[31]^da[37]^da[43]
+ * hash_index[00] = da[00]^da[06]^da[12]^da[18]^da[24]^da[30]^da[36]^da[42]
+ * </pre>
+ *
+ * da[0] represents the least significant bit of the first byte received,
+ * that is, the multicast/unicast indicator, and da[47] represents the most
+ * significant bit of the last byte received.
+ *
+ * If the hash index points to a bit that is set in the hash register then
+ * the frame will be matched according to whether the frame is multicast
+ * or unicast.
+ *
+ * A multicast match will be signaled if the multicast hash enable bit is
+ * set, da[0] is logic 1 and the hash index points to a bit set in the hash
+ * register.
+ *
+ * A unicast match will be signaled if the unicast hash enable bit is set,
+ * da[0] is logic 0 and the hash index points to a bit set in the hash
+ * register.
+ *
+ * To receive all multicast frames, the hash register should be set with
+ * all ones and the multicast hash enable bit should be set in the network
+ * configuration register.
+ *
+ *
+ * @param InstancePtr is a pointer to the instance to be worked on.
+ * @param AddressPtr is a pointer to a 6-byte MAC address.
+ *
+ * @return
+ * - XST_SUCCESS if the HASH MAC address was set successfully
+ * - XST_DEVICE_IS_STARTED if the device has not yet been stopped
+ * - XST_INVALID_PARAM if the HASH MAC address passed in does not meet
+ * requirement after calculation
+ *
+ * @note
+ * Having Aptr be unsigned type prevents the following operations from sign
+ * extending.
+ *****************************************************************************/
+LONG XEmacPs_SetHash(XEmacPs *InstancePtr, void *AddressPtr)
+{
+ u32 HashAddr;
+ u8 *Aptr = (u8 *)(void *)AddressPtr;
+ u8 Temp1, Temp2, Temp3, Temp4, Temp5, Temp6, Temp7, Temp8;
+ u32 Result;
+ LONG Status;
+
+ Xil_AssertNonvoid(InstancePtr != NULL);
+ Xil_AssertNonvoid(AddressPtr != NULL);
+ Xil_AssertNonvoid(InstancePtr->IsReady == (u32)XIL_COMPONENT_IS_READY);
+
+ /* Be sure device has been stopped */
+ if (InstancePtr->IsStarted == (u32)XIL_COMPONENT_IS_STARTED) {
+ Status = (LONG)(XST_DEVICE_IS_STARTED);
+ } else {
+ Temp1 = (*(Aptr+0)) & 0x3FU;
+ Temp2 = ((*(Aptr+0) >> 6U) & 0x03U) | ((*(Aptr+1) & 0x0FU) << 2U);
+
+ Temp3 = ((*(Aptr+1) >> 4U) & 0x0FU) | ((*(Aptr+2) & 0x3U) << 4U);
+ Temp4 = ((*(Aptr+2) >> 2U) & 0x3FU);
+ Temp5 = (*(Aptr+3)) & 0x3FU;
+ Temp6 = ((*(Aptr+3) >> 6U) & 0x03U) | ((*(Aptr+4) & 0x0FU) << 2U);
+ Temp7 = ((*(Aptr+4) >> 4U) & 0x0FU) | ((*(Aptr+5) & 0x03U) << 4U);
+ Temp8 = ((*(Aptr+5) >> 2U) & 0x3FU);
+
+ Result = (u32)((u32)Temp1 ^ (u32)Temp2 ^ (u32)Temp3 ^ (u32)Temp4 ^
+ (u32)Temp5 ^ (u32)Temp6 ^ (u32)Temp7 ^ (u32)Temp8);
+
+ if (Result >= (u32)XEMACPS_MAX_HASH_BITS) {
+ Status = (LONG)(XST_INVALID_PARAM);
+ } else {
+
+ if (Result < (u32)32) {
+ HashAddr = XEmacPs_ReadReg(InstancePtr->Config.BaseAddress,
+ XEMACPS_HASHL_OFFSET);
+ HashAddr |= (u32)(0x00000001U << Result);
+ XEmacPs_WriteReg(InstancePtr->Config.BaseAddress,
+ XEMACPS_HASHL_OFFSET, HashAddr);
+ } else {
+ HashAddr = XEmacPs_ReadReg(InstancePtr->Config.BaseAddress,
+ XEMACPS_HASHH_OFFSET);
+ HashAddr |= (u32)(0x00000001U << (u32)(Result - (u32)32));
+ XEmacPs_WriteReg(InstancePtr->Config.BaseAddress,
+ XEMACPS_HASHH_OFFSET, HashAddr);
+ }
+ Status = (LONG)(XST_SUCCESS);
+ }
+ }
+ return Status;
+}
+
+/*****************************************************************************/
+/**
+ * Delete 48-bit MAC addresses in hash table.
+ * The device must be stopped before calling this function.
+ *
+ * @param InstancePtr is a pointer to the instance to be worked on.
+ * @param AddressPtr is a pointer to a 6-byte MAC address.
+ *
+ * @return
+ * - XST_SUCCESS if the HASH MAC address was deleted successfully
+ * - XST_DEVICE_IS_STARTED if the device has not yet been stopped
+ * - XST_INVALID_PARAM if the HASH MAC address passed in does not meet
+ * requirement after calculation
+ *
+ * @note
+ * Having Aptr be unsigned type prevents the following operations from sign
+ * extending.
+ *****************************************************************************/
+LONG XEmacPs_DeleteHash(XEmacPs *InstancePtr, void *AddressPtr)
+{
+ u32 HashAddr;
+ u8 *Aptr = (u8 *)(void *)AddressPtr;
+ u8 Temp1, Temp2, Temp3, Temp4, Temp5, Temp6, Temp7, Temp8;
+ u32 Result;
+ LONG Status;
+
+ Xil_AssertNonvoid(InstancePtr != NULL);
+ Xil_AssertNonvoid(Aptr != NULL);
+ Xil_AssertNonvoid(InstancePtr->IsReady == (u32)XIL_COMPONENT_IS_READY);
+
+ /* Be sure device has been stopped */
+ if (InstancePtr->IsStarted == (u32)XIL_COMPONENT_IS_STARTED) {
+ Status = (LONG)(XST_DEVICE_IS_STARTED);
+ } else {
+ Temp1 = (*(Aptr+0)) & 0x3FU;
+ Temp2 = ((*(Aptr+0) >> 6U) & 0x03U) | ((*(Aptr+1) & 0x0FU) << 2U);
+ Temp3 = ((*(Aptr+1) >> 4U) & 0x0FU) | ((*(Aptr+2) & 0x03U) << 4U);
+ Temp4 = ((*(Aptr+2) >> 2U) & 0x3FU);
+ Temp5 = (*(Aptr+3)) & 0x3FU;
+ Temp6 = ((*(Aptr+3) >> 6U) & 0x03U) | ((*(Aptr+4) & 0x0FU) << 2U);
+ Temp7 = ((*(Aptr+4) >> 4U) & 0x0FU) | ((*(Aptr+5) & 0x03U) << 4U);
+ Temp8 = ((*(Aptr+5) >> 2U) & 0x3FU);
+
+ Result = (u32)((u32)Temp1 ^ (u32)Temp2 ^ (u32)Temp3 ^ (u32)Temp4 ^
+ (u32)Temp5 ^ (u32)Temp6 ^ (u32)Temp7 ^ (u32)Temp8);
+
+ if (Result >= (u32)(XEMACPS_MAX_HASH_BITS)) {
+ Status = (LONG)(XST_INVALID_PARAM);
+ } else {
+ if (Result < (u32)32) {
+ HashAddr = XEmacPs_ReadReg(InstancePtr->Config.BaseAddress,
+ XEMACPS_HASHL_OFFSET);
+ HashAddr &= (u32)(~(0x00000001U << Result));
+ XEmacPs_WriteReg(InstancePtr->Config.BaseAddress,
+ XEMACPS_HASHL_OFFSET, HashAddr);
+ } else {
+ HashAddr = XEmacPs_ReadReg(InstancePtr->Config.BaseAddress,
+ XEMACPS_HASHH_OFFSET);
+ HashAddr &= (u32)(~(0x00000001U << (u32)(Result - (u32)32)));
+ XEmacPs_WriteReg(InstancePtr->Config.BaseAddress,
+ XEMACPS_HASHH_OFFSET, HashAddr);
+ }
+ Status = (LONG)(XST_SUCCESS);
+ }
+ }
+ return Status;
+}
+/*****************************************************************************/
+/**
+ * Clear the Hash registers for the mac address pointed by AddressPtr.
+ *
+ * @param InstancePtr is a pointer to the instance to be worked on.
+ *
+ *****************************************************************************/
+void XEmacPs_ClearHash(XEmacPs *InstancePtr)
+{
+ Xil_AssertVoid(InstancePtr != NULL);
+ Xil_AssertVoid(InstancePtr->IsReady == (u32)XIL_COMPONENT_IS_READY);
+
+ XEmacPs_WriteReg(InstancePtr->Config.BaseAddress,
+ XEMACPS_HASHL_OFFSET, 0x0U);
+
+ /* write bits [63:32] in TOP */
+ XEmacPs_WriteReg(InstancePtr->Config.BaseAddress,
+ XEMACPS_HASHH_OFFSET, 0x0U);
+}
+
+
+/*****************************************************************************/
+/**
+ * Get the Hash address for this driver/device.
+ *
+ * @param InstancePtr is a pointer to the instance to be worked on.
+ * @param AddressPtr is an output parameter, and is a pointer to a buffer into
+ * which the current HASH MAC address will be copied.
+ *
+ *****************************************************************************/
+void XEmacPs_GetHash(XEmacPs *InstancePtr, void *AddressPtr)
+{
+ u32 *Aptr = (u32 *)(void *)AddressPtr;
+
+ Xil_AssertVoid(InstancePtr != NULL);
+ Xil_AssertVoid(AddressPtr != NULL);
+ Xil_AssertVoid(InstancePtr->IsReady == (u32)XIL_COMPONENT_IS_READY);
+
+ *(Aptr+0) = XEmacPs_ReadReg(InstancePtr->Config.BaseAddress,
+ XEMACPS_HASHL_OFFSET);
+
+ /* Read Hash bits [63:32] in TOP */
+ *(Aptr+1) = XEmacPs_ReadReg(InstancePtr->Config.BaseAddress,
+ XEMACPS_HASHH_OFFSET);
+}
+
+
+/*****************************************************************************/
+/**
+ * Set the Type ID match for this driver/device. The register is a 32-bit
+ * value. The device must be stopped before calling this function.
+ *
+ * @param InstancePtr is a pointer to the instance to be worked on.
+ * @param Id_Check is type ID to be configured.
+ * @param Index is a index to which Type ID (1-4).
+ *
+ * @return
+ * - XST_SUCCESS if the MAC address was set successfully
+ * - XST_DEVICE_IS_STARTED if the device has not yet been stopped
+ *
+ *****************************************************************************/
+LONG XEmacPs_SetTypeIdCheck(XEmacPs *InstancePtr, u32 Id_Check, u8 Index)
+{
+ u8 IndexLoc = Index;
+ LONG Status;
+ Xil_AssertNonvoid(InstancePtr != NULL);
+ Xil_AssertNonvoid(InstancePtr->IsReady == (u32)XIL_COMPONENT_IS_READY);
+ Xil_AssertNonvoid((IndexLoc <= (u8)XEMACPS_MAX_TYPE_ID) && (IndexLoc > 0x00U));
+
+ /* Be sure device has been stopped */
+ if (InstancePtr->IsStarted == (u32)XIL_COMPONENT_IS_STARTED) {
+ Status = (LONG)(XST_DEVICE_IS_STARTED);
+ } else {
+
+ /* Index ranges 1 to 4, for offset calculation is 0 to 3. */
+ IndexLoc--;
+
+ /* Set the ID bits in MATCHx register */
+ XEmacPs_WriteReg(InstancePtr->Config.BaseAddress,
+ ((u32)XEMACPS_MATCH1_OFFSET + ((u32)IndexLoc * (u32)4)), Id_Check);
+
+ Status = (LONG)(XST_SUCCESS);
+ }
+ return Status;
+}
+
+/*****************************************************************************/
+/**
+ * Set options for the driver/device. The driver should be stopped with
+ * XEmacPs_Stop() before changing options.
+ *
+ * @param InstancePtr is a pointer to the instance to be worked on.
+ * @param Options are the options to set. Multiple options can be set by OR'ing
+ * XTE_*_OPTIONS constants together. Options not specified are not
+ * affected.
+ *
+ * @return
+ * - XST_SUCCESS if the options were set successfully
+ * - XST_DEVICE_IS_STARTED if the device has not yet been stopped
+ *
+ * @note
+ * See xemacps.h for a description of the available options.
+ *
+ *****************************************************************************/
+LONG XEmacPs_SetOptions(XEmacPs *InstancePtr, u32 Options)
+{
+ u32 Reg; /* Generic register contents */
+ u32 RegNetCfg; /* Reflects original contents of NET_CONFIG */
+ u32 RegNewNetCfg; /* Reflects new contents of NET_CONFIG */
+ LONG Status;
+ Xil_AssertNonvoid(InstancePtr != NULL);
+ Xil_AssertNonvoid(InstancePtr->IsReady == (u32)XIL_COMPONENT_IS_READY);
+
+ /* Be sure device has been stopped */
+ if (InstancePtr->IsStarted == (u32)XIL_COMPONENT_IS_STARTED) {
+ Status = (LONG)(XST_DEVICE_IS_STARTED);
+ } else {
+
+ /* Many of these options will change the NET_CONFIG registers.
+ * To reduce the amount of IO to the device, group these options here
+ * and change them all at once.
+ */
+
+ /* Grab current register contents */
+ RegNetCfg = XEmacPs_ReadReg(InstancePtr->Config.BaseAddress,
+ XEMACPS_NWCFG_OFFSET);
+ RegNewNetCfg = RegNetCfg;
+
+ /*
+ * It is configured to max 1536.
+ */
+ if ((Options & XEMACPS_FRAME1536_OPTION) != 0x00000000U) {
+ RegNewNetCfg |= (XEMACPS_NWCFG_1536RXEN_MASK);
+ }
+
+ /* Turn on VLAN packet only, only VLAN tagged will be accepted */
+ if ((Options & XEMACPS_VLAN_OPTION) != 0x00000000U) {
+ RegNewNetCfg |= XEMACPS_NWCFG_NVLANDISC_MASK;
+ }
+
+ /* Turn on FCS stripping on receive packets */
+ if ((Options & XEMACPS_FCS_STRIP_OPTION) != 0x00000000U) {
+ RegNewNetCfg |= XEMACPS_NWCFG_FCSREM_MASK;
+ }
+
+ /* Turn on length/type field checking on receive packets */
+ if ((Options & XEMACPS_LENTYPE_ERR_OPTION) != 0x00000000U) {
+ RegNewNetCfg |= XEMACPS_NWCFG_LENERRDSCRD_MASK;
+ }
+
+ /* Turn on flow control */
+ if ((Options & XEMACPS_FLOW_CONTROL_OPTION) != 0x00000000U) {
+ RegNewNetCfg |= XEMACPS_NWCFG_PAUSEEN_MASK;
+ }
+
+ /* Turn on promiscuous frame filtering (all frames are received) */
+ if ((Options & XEMACPS_PROMISC_OPTION) != 0x00000000U) {
+ RegNewNetCfg |= XEMACPS_NWCFG_COPYALLEN_MASK;
+ }
+
+ /* Allow broadcast address reception */
+ if ((Options & XEMACPS_BROADCAST_OPTION) != 0x00000000U) {
+ RegNewNetCfg &= (u32)(~XEMACPS_NWCFG_BCASTDI_MASK);
+ }
+
+ /* Allow multicast address filtering */
+ if ((Options & XEMACPS_MULTICAST_OPTION) != 0x00000000U) {
+ RegNewNetCfg |= XEMACPS_NWCFG_MCASTHASHEN_MASK;
+ }
+
+ /* enable RX checksum offload */
+ if ((Options & XEMACPS_RX_CHKSUM_ENABLE_OPTION) != 0x00000000U) {
+ RegNewNetCfg |= XEMACPS_NWCFG_RXCHKSUMEN_MASK;
+ }
+
+ /* Enable jumbo frames */
+ if (((Options & XEMACPS_JUMBO_ENABLE_OPTION) != 0x00000000U) &&
+ (InstancePtr->Version > 2)) {
+ RegNewNetCfg |= XEMACPS_NWCFG_JUMBO_MASK;
+ XEmacPs_WriteReg(InstancePtr->Config.BaseAddress,
+ XEMACPS_JUMBOMAXLEN_OFFSET, XEMACPS_RX_BUF_SIZE_JUMBO);
+ Reg = XEmacPs_ReadReg(InstancePtr->Config.BaseAddress,
+ XEMACPS_DMACR_OFFSET);
+ Reg &= ~XEMACPS_DMACR_RXBUF_MASK;
+ Reg |= (((((u32)XEMACPS_RX_BUF_SIZE_JUMBO / (u32)XEMACPS_RX_BUF_UNIT) +
+ (((((u32)XEMACPS_RX_BUF_SIZE_JUMBO %
+ (u32)XEMACPS_RX_BUF_UNIT))!=(u32)0) ? 1U : 0U)) <<
+ (u32)(XEMACPS_DMACR_RXBUF_SHIFT)) &
+ (u32)(XEMACPS_DMACR_RXBUF_MASK));
+ XEmacPs_WriteReg(InstancePtr->Config.BaseAddress,
+ XEMACPS_DMACR_OFFSET, Reg);
+ InstancePtr->MaxMtuSize = XEMACPS_MTU_JUMBO;
+ InstancePtr->MaxFrameSize = XEMACPS_MTU_JUMBO +
+ XEMACPS_HDR_SIZE + XEMACPS_TRL_SIZE;
+ InstancePtr->MaxVlanFrameSize = InstancePtr->MaxFrameSize +
+ XEMACPS_HDR_VLAN_SIZE;
+ InstancePtr->RxBufMask = XEMACPS_RXBUF_LEN_JUMBO_MASK;
+ }
+
+ if (((Options & XEMACPS_SGMII_ENABLE_OPTION) != 0x00000000U) &&
+ (InstancePtr->Version > 2)) {
+ RegNewNetCfg |= (XEMACPS_NWCFG_SGMIIEN_MASK |
+ XEMACPS_NWCFG_PCSSEL_MASK);
+ }
+
+ /* Officially change the NET_CONFIG registers if it needs to be
+ * modified.
+ */
+ if (RegNetCfg != RegNewNetCfg) {
+ XEmacPs_WriteReg(InstancePtr->Config.BaseAddress,
+ XEMACPS_NWCFG_OFFSET, RegNewNetCfg);
+ }
+
+ /* Enable TX checksum offload */
+ if ((Options & XEMACPS_TX_CHKSUM_ENABLE_OPTION) != 0x00000000U) {
+ Reg = XEmacPs_ReadReg(InstancePtr->Config.BaseAddress,
+ XEMACPS_DMACR_OFFSET);
+ Reg |= XEMACPS_DMACR_TCPCKSUM_MASK;
+ XEmacPs_WriteReg(InstancePtr->Config.BaseAddress,
+ XEMACPS_DMACR_OFFSET, Reg);
+ }
+
+ /* Enable transmitter */
+ if ((Options & XEMACPS_TRANSMITTER_ENABLE_OPTION) != 0x00000000U) {
+ Reg = XEmacPs_ReadReg(InstancePtr->Config.BaseAddress,
+ XEMACPS_NWCTRL_OFFSET);
+ Reg |= XEMACPS_NWCTRL_TXEN_MASK;
+ XEmacPs_WriteReg(InstancePtr->Config.BaseAddress,
+ XEMACPS_NWCTRL_OFFSET, Reg);
+ }
+
+ /* Enable receiver */
+ if ((Options & XEMACPS_RECEIVER_ENABLE_OPTION) != 0x00000000U) {
+ Reg = XEmacPs_ReadReg(InstancePtr->Config.BaseAddress,
+ XEMACPS_NWCTRL_OFFSET);
+ Reg |= XEMACPS_NWCTRL_RXEN_MASK;
+ XEmacPs_WriteReg(InstancePtr->Config.BaseAddress,
+ XEMACPS_NWCTRL_OFFSET, Reg);
+ }
+
+ /* The remaining options not handled here are managed elsewhere in the
+ * driver. No register modifications are needed at this time. Reflecting
+ * the option in InstancePtr->Options is good enough for now.
+ */
+
+ /* Set options word to its new value */
+ InstancePtr->Options |= Options;
+
+ Status = (LONG)(XST_SUCCESS);
+ }
+ return Status;
+}
+
+
+/*****************************************************************************/
+/**
+ * Clear options for the driver/device
+ *
+ * @param InstancePtr is a pointer to the instance to be worked on.
+ * @param Options are the options to clear. Multiple options can be cleared by
+ * OR'ing XEMACPS_*_OPTIONS constants together. Options not specified
+ * are not affected.
+ *
+ * @return
+ * - XST_SUCCESS if the options were set successfully
+ * - XST_DEVICE_IS_STARTED if the device has not yet been stopped
+ *
+ * @note
+ * See xemacps.h for a description of the available options.
+ *
+ *****************************************************************************/
+LONG XEmacPs_ClearOptions(XEmacPs *InstancePtr, u32 Options)
+{
+ u32 Reg; /* Generic */
+ u32 RegNetCfg; /* Reflects original contents of NET_CONFIG */
+ u32 RegNewNetCfg; /* Reflects new contents of NET_CONFIG */
+ LONG Status;
+ Xil_AssertNonvoid(InstancePtr != NULL);
+ Xil_AssertNonvoid(InstancePtr->IsReady == (u32)XIL_COMPONENT_IS_READY);
+
+ /* Be sure device has been stopped */
+ if (InstancePtr->IsStarted == (u32)XIL_COMPONENT_IS_STARTED) {
+ Status = (LONG)(XST_DEVICE_IS_STARTED);
+ } else {
+
+ /* Many of these options will change the NET_CONFIG registers.
+ * To reduce the amount of IO to the device, group these options here
+ * and change them all at once.
+ */
+
+ /* Grab current register contents */
+ RegNetCfg = XEmacPs_ReadReg(InstancePtr->Config.BaseAddress,
+ XEMACPS_NWCFG_OFFSET);
+ RegNewNetCfg = RegNetCfg;
+
+ /* There is only RX configuration!?
+ * It is configured in two different length, up to 1536 and 10240 bytes
+ */
+ if ((Options & XEMACPS_FRAME1536_OPTION) != 0x00000000U) {
+ RegNewNetCfg &= (u32)(~XEMACPS_NWCFG_1536RXEN_MASK);
+ }
+
+ /* Turn off VLAN packet only */
+ if ((Options & XEMACPS_VLAN_OPTION) != 0x00000000U) {
+ RegNewNetCfg &= (u32)(~XEMACPS_NWCFG_NVLANDISC_MASK);
+ }
+
+ /* Turn off FCS stripping on receive packets */
+ if ((Options & XEMACPS_FCS_STRIP_OPTION) != 0x00000000U) {
+ RegNewNetCfg &= (u32)(~XEMACPS_NWCFG_FCSREM_MASK);
+ }
+
+ /* Turn off length/type field checking on receive packets */
+ if ((Options & XEMACPS_LENTYPE_ERR_OPTION) != 0x00000000U) {
+ RegNewNetCfg &= (u32)(~XEMACPS_NWCFG_LENERRDSCRD_MASK);
+ }
+
+ /* Turn off flow control */
+ if ((Options & XEMACPS_FLOW_CONTROL_OPTION) != 0x00000000U) {
+ RegNewNetCfg &= (u32)(~XEMACPS_NWCFG_PAUSEEN_MASK);
+ }
+
+ /* Turn off promiscuous frame filtering (all frames are received) */
+ if ((Options & XEMACPS_PROMISC_OPTION) != 0x00000000U) {
+ RegNewNetCfg &= (u32)(~XEMACPS_NWCFG_COPYALLEN_MASK);
+ }
+
+ /* Disallow broadcast address filtering => broadcast reception */
+ if ((Options & XEMACPS_BROADCAST_OPTION) != 0x00000000U) {
+ RegNewNetCfg |= XEMACPS_NWCFG_BCASTDI_MASK;
+ }
+
+ /* Disallow multicast address filtering */
+ if ((Options & XEMACPS_MULTICAST_OPTION) != 0x00000000U) {
+ RegNewNetCfg &= (u32)(~XEMACPS_NWCFG_MCASTHASHEN_MASK);
+ }
+
+ /* Disable RX checksum offload */
+ if ((Options & XEMACPS_RX_CHKSUM_ENABLE_OPTION) != 0x00000000U) {
+ RegNewNetCfg &= (u32)(~XEMACPS_NWCFG_RXCHKSUMEN_MASK);
+ }
+
+ /* Disable jumbo frames */
+ if (((Options & XEMACPS_JUMBO_ENABLE_OPTION) != 0x00000000U) &&
+ (InstancePtr->Version > 2)) {
+ RegNewNetCfg &= (u32)(~XEMACPS_NWCFG_JUMBO_MASK);
+ Reg = XEmacPs_ReadReg(InstancePtr->Config.BaseAddress,
+ XEMACPS_DMACR_OFFSET);
+ Reg &= ~XEMACPS_DMACR_RXBUF_MASK;
+ Reg |= (((((u32)XEMACPS_RX_BUF_SIZE / (u32)XEMACPS_RX_BUF_UNIT) +
+ (((((u32)XEMACPS_RX_BUF_SIZE %
+ (u32)XEMACPS_RX_BUF_UNIT))!=(u32)0) ? 1U : 0U)) <<
+ (u32)(XEMACPS_DMACR_RXBUF_SHIFT)) &
+ (u32)(XEMACPS_DMACR_RXBUF_MASK));
+ XEmacPs_WriteReg(InstancePtr->Config.BaseAddress,
+ XEMACPS_DMACR_OFFSET, Reg);
+ InstancePtr->MaxMtuSize = XEMACPS_MTU;
+ InstancePtr->MaxFrameSize = XEMACPS_MTU +
+ XEMACPS_HDR_SIZE + XEMACPS_TRL_SIZE;
+ InstancePtr->MaxVlanFrameSize = InstancePtr->MaxFrameSize +
+ XEMACPS_HDR_VLAN_SIZE;
+ InstancePtr->RxBufMask = XEMACPS_RXBUF_LEN_MASK;
+ }
+
+ if (((Options & XEMACPS_SGMII_ENABLE_OPTION) != 0x00000000U) &&
+ (InstancePtr->Version > 2)) {
+ RegNewNetCfg &= (u32)(~(XEMACPS_NWCFG_SGMIIEN_MASK |
+ XEMACPS_NWCFG_PCSSEL_MASK));
+ }
+
+ /* Officially change the NET_CONFIG registers if it needs to be
+ * modified.
+ */
+ if (RegNetCfg != RegNewNetCfg) {
+ XEmacPs_WriteReg(InstancePtr->Config.BaseAddress,
+ XEMACPS_NWCFG_OFFSET, RegNewNetCfg);
+ }
+
+ /* Disable TX checksum offload */
+ if ((Options & XEMACPS_TX_CHKSUM_ENABLE_OPTION) != 0x00000000U) {
+ Reg = XEmacPs_ReadReg(InstancePtr->Config.BaseAddress,
+ XEMACPS_DMACR_OFFSET);
+ Reg &= (u32)(~XEMACPS_DMACR_TCPCKSUM_MASK);
+ XEmacPs_WriteReg(InstancePtr->Config.BaseAddress,
+ XEMACPS_DMACR_OFFSET, Reg);
+ }
+
+ /* Disable transmitter */
+ if ((Options & XEMACPS_TRANSMITTER_ENABLE_OPTION) != 0x00000000U) {
+ Reg = XEmacPs_ReadReg(InstancePtr->Config.BaseAddress,
+ XEMACPS_NWCTRL_OFFSET);
+ Reg &= (u32)(~XEMACPS_NWCTRL_TXEN_MASK);
+ XEmacPs_WriteReg(InstancePtr->Config.BaseAddress,
+ XEMACPS_NWCTRL_OFFSET, Reg);
+ }
+
+ /* Disable receiver */
+ if ((Options & XEMACPS_RECEIVER_ENABLE_OPTION) != 0x00000000U) {
+ Reg = XEmacPs_ReadReg(InstancePtr->Config.BaseAddress,
+ XEMACPS_NWCTRL_OFFSET);
+ Reg &= (u32)(~XEMACPS_NWCTRL_RXEN_MASK);
+ XEmacPs_WriteReg(InstancePtr->Config.BaseAddress,
+ XEMACPS_NWCTRL_OFFSET, Reg);
+ }
+
+ /* The remaining options not handled here are managed elsewhere in the
+ * driver. No register modifications are needed at this time. Reflecting
+ * option in InstancePtr->Options is good enough for now.
+ */
+
+ /* Set options word to its new value */
+ InstancePtr->Options &= ~Options;
+
+ Status = (LONG)(XST_SUCCESS);
+ }
+ return Status;
+}
+
+
+/*****************************************************************************/
+/**
+ * Get current option settings
+ *
+ * @param InstancePtr is a pointer to the instance to be worked on.
+ *
+ * @return
+ * A bitmask of XTE_*_OPTION constants. Any bit set to 1 is to be interpreted
+ * as a set option.
+ *
+ * @note
+ * See xemacps.h for a description of the available options.
+ *
+ *****************************************************************************/
+u32 XEmacPs_GetOptions(XEmacPs *InstancePtr)
+{
+ Xil_AssertNonvoid(InstancePtr != NULL);
+ Xil_AssertNonvoid(InstancePtr->IsReady == (u32)XIL_COMPONENT_IS_READY);
+
+ return (InstancePtr->Options);
+}
+
+
+/*****************************************************************************/
+/**
+ * Send a pause packet
+ *
+ * @param InstancePtr is a pointer to the instance to be worked on.
+ *
+ * @return
+ * - XST_SUCCESS if pause frame transmission was initiated
+ * - XST_DEVICE_IS_STOPPED if the device has not been started.
+ *
+ *****************************************************************************/
+LONG XEmacPs_SendPausePacket(XEmacPs *InstancePtr)
+{
+ u32 Reg;
+ LONG Status;
+
+ Xil_AssertNonvoid(InstancePtr != NULL);
+ Xil_AssertNonvoid(InstancePtr->IsReady == (u32)XIL_COMPONENT_IS_READY);
+
+ /* Make sure device is ready for this operation */
+ if (InstancePtr->IsStarted != (u32)XIL_COMPONENT_IS_STARTED) {
+ Status = (LONG)(XST_DEVICE_IS_STOPPED);
+ } else {
+ /* Send flow control frame */
+ Reg = XEmacPs_ReadReg(InstancePtr->Config.BaseAddress,
+ XEMACPS_NWCTRL_OFFSET);
+ Reg |= XEMACPS_NWCTRL_PAUSETX_MASK;
+ XEmacPs_WriteReg(InstancePtr->Config.BaseAddress,
+ XEMACPS_NWCTRL_OFFSET, Reg);
+ Status = (LONG)(XST_SUCCESS);
+ }
+ return Status;
+}
+
+/*****************************************************************************/
+/**
+ * XEmacPs_GetOperatingSpeed gets the current operating link speed. This may
+ * be the value set by XEmacPs_SetOperatingSpeed() or a hardware default.
+ *
+ * @param InstancePtr references the TEMAC channel on which to operate.
+ *
+ * @return XEmacPs_GetOperatingSpeed returns the link speed in units of
+ * megabits per second.
+ *
+ * @note
+ *
+ *****************************************************************************/
+u16 XEmacPs_GetOperatingSpeed(XEmacPs *InstancePtr)
+{
+ u32 Reg;
+ u16 Status;
+
+ Xil_AssertNonvoid(InstancePtr != NULL);
+ Xil_AssertNonvoid(InstancePtr->IsReady == (u32)XIL_COMPONENT_IS_READY);
+
+ Reg = XEmacPs_ReadReg(InstancePtr->Config.BaseAddress,
+ XEMACPS_NWCFG_OFFSET);
+
+ if ((Reg & XEMACPS_NWCFG_1000_MASK) != 0x00000000U) {
+ Status = (u16)(1000);
+ } else {
+ if ((Reg & XEMACPS_NWCFG_100_MASK) != 0x00000000U) {
+ Status = (u16)(100);
+ } else {
+ Status = (u16)(10);
+ }
+ }
+ return Status;
+}
+
+
+/*****************************************************************************/
+/**
+ * XEmacPs_SetOperatingSpeed sets the current operating link speed. For any
+ * traffic to be passed, this speed must match the current MII/GMII/SGMII/RGMII
+ * link speed.
+ *
+ * @param InstancePtr references the TEMAC channel on which to operate.
+ * @param Speed is the speed to set in units of Mbps. Valid values are 10, 100,
+ * or 1000. XEmacPs_SetOperatingSpeed ignores invalid values.
+ *
+ * @note
+ *
+ *****************************************************************************/
+void XEmacPs_SetOperatingSpeed(XEmacPs *InstancePtr, u16 Speed)
+{
+ u32 Reg;
+ Xil_AssertVoid(InstancePtr != NULL);
+ Xil_AssertVoid(InstancePtr->IsReady == (u32)XIL_COMPONENT_IS_READY);
+ Xil_AssertVoid((Speed == (u16)10) || (Speed == (u16)100) || (Speed == (u16)1000));
+
+ Reg = XEmacPs_ReadReg(InstancePtr->Config.BaseAddress,
+ XEMACPS_NWCFG_OFFSET);
+ Reg &= (u32)(~(XEMACPS_NWCFG_1000_MASK | XEMACPS_NWCFG_100_MASK));
+
+ switch (Speed) {
+ case (u16)10:
+ break;
+
+ case (u16)100:
+ Reg |= XEMACPS_NWCFG_100_MASK;
+ break;
+
+ case (u16)1000:
+ Reg |= XEMACPS_NWCFG_1000_MASK;
+ break;
+ }
+
+ /* Set register and return */
+ XEmacPs_WriteReg(InstancePtr->Config.BaseAddress,
+ XEMACPS_NWCFG_OFFSET, Reg);
+}
+
+
+/*****************************************************************************/
+/**
+ * Set the MDIO clock divisor.
+ *
+ * Calculating the divisor:
+ *
+ * <pre>
+ * f[HOSTCLK]
+ * f[MDC] = -----------------
+ * (1 + Divisor) * 2
+ * </pre>
+ *
+ * where f[HOSTCLK] is the bus clock frequency in MHz, and f[MDC] is the
+ * MDIO clock frequency in MHz to the PHY. Typically, f[MDC] should not
+ * exceed 2.5 MHz. Some PHYs can tolerate faster speeds which means faster
+ * access. Here is the table to show values to generate MDC,
+ *
+ * <pre>
+ * 000 : divide pclk by 8 (pclk up to 20 MHz)
+ * 001 : divide pclk by 16 (pclk up to 40 MHz)
+ * 010 : divide pclk by 32 (pclk up to 80 MHz)
+ * 011 : divide pclk by 48 (pclk up to 120 MHz)
+ * 100 : divide pclk by 64 (pclk up to 160 MHz)
+ * 101 : divide pclk by 96 (pclk up to 240 MHz)
+ * 110 : divide pclk by 128 (pclk up to 320 MHz)
+ * 111 : divide pclk by 224 (pclk up to 540 MHz)
+ * </pre>
+ *
+ * @param InstancePtr is a pointer to the instance to be worked on.
+ * @param Divisor is the divisor to set. Range is 0b000 to 0b111.
+ *
+ *****************************************************************************/
+void XEmacPs_SetMdioDivisor(XEmacPs *InstancePtr, XEmacPs_MdcDiv Divisor)
+{
+ u32 Reg;
+ Xil_AssertVoid(InstancePtr != NULL);
+ Xil_AssertVoid(InstancePtr->IsReady == (u32)XIL_COMPONENT_IS_READY);
+ Xil_AssertVoid(Divisor <= (XEmacPs_MdcDiv)0x7); /* only last three bits are valid */
+
+ Reg = XEmacPs_ReadReg(InstancePtr->Config.BaseAddress,
+ XEMACPS_NWCFG_OFFSET);
+ /* clear these three bits, could be done with mask */
+ Reg &= (u32)(~XEMACPS_NWCFG_MDCCLKDIV_MASK);
+
+ Reg |= ((u32)Divisor << XEMACPS_NWCFG_MDC_SHIFT_MASK);
+
+ XEmacPs_WriteReg(InstancePtr->Config.BaseAddress,
+ XEMACPS_NWCFG_OFFSET, Reg);
+}
+
+
+/*****************************************************************************/
+/**
+* Read the current value of the PHY register indicated by the PhyAddress and
+* the RegisterNum parameters. The MAC provides the driver with the ability to
+* talk to a PHY that adheres to the Media Independent Interface (MII) as
+* defined in the IEEE 802.3 standard.
+*
+* Prior to PHY access with this function, the user should have setup the MDIO
+* clock with XEmacPs_SetMdioDivisor().
+*
+* @param InstancePtr is a pointer to the XEmacPs instance to be worked on.
+* @param PhyAddress is the address of the PHY to be read (supports multiple
+* PHYs)
+* @param RegisterNum is the register number, 0-31, of the specific PHY register
+* to read
+* @param PhyDataPtr is an output parameter, and points to a 16-bit buffer into
+* which the current value of the register will be copied.
+*
+* @return
+*
+* - XST_SUCCESS if the PHY was read from successfully
+* - XST_EMAC_MII_BUSY if there is another PHY operation in progress
+*
+* @note
+*
+* This function is not thread-safe. The user must provide mutually exclusive
+* access to this function if there are to be multiple threads that can call it.
+*
+* There is the possibility that this function will not return if the hardware
+* is broken (i.e., it never sets the status bit indicating that the read is
+* done). If this is of concern to the user, the user should provide a mechanism
+* suitable to their needs for recovery.
+*
+* For the duration of this function, all host interface reads and writes are
+* blocked to the current XEmacPs instance.
+*
+******************************************************************************/
+LONG XEmacPs_PhyRead(XEmacPs *InstancePtr, u32 PhyAddress,
+ u32 RegisterNum, u16 *PhyDataPtr)
+{
+ u32 Mgtcr;
+ volatile u32 Ipisr;
+ u32 IpReadTemp;
+ LONG Status;
+
+ Xil_AssertNonvoid(InstancePtr != NULL);
+
+ /* Make sure no other PHY operation is currently in progress */
+ if ((!(XEmacPs_ReadReg(InstancePtr->Config.BaseAddress,
+ XEMACPS_NWSR_OFFSET) &
+ XEMACPS_NWSR_MDIOIDLE_MASK))==TRUE) {
+ Status = (LONG)(XST_EMAC_MII_BUSY);
+ } else {
+
+ /* Construct Mgtcr mask for the operation */
+ Mgtcr = XEMACPS_PHYMNTNC_OP_MASK | XEMACPS_PHYMNTNC_OP_R_MASK |
+ (PhyAddress << XEMACPS_PHYMNTNC_PHAD_SHFT_MSK) |
+ (RegisterNum << XEMACPS_PHYMNTNC_PREG_SHFT_MSK);
+
+ /* Write Mgtcr and wait for completion */
+ XEmacPs_WriteReg(InstancePtr->Config.BaseAddress,
+ XEMACPS_PHYMNTNC_OFFSET, Mgtcr);
+
+ do {
+ Ipisr = XEmacPs_ReadReg(InstancePtr->Config.BaseAddress,
+ XEMACPS_NWSR_OFFSET);
+ IpReadTemp = Ipisr;
+ } while ((IpReadTemp & XEMACPS_NWSR_MDIOIDLE_MASK) == 0x00000000U);
+
+ /* Read data */
+ *PhyDataPtr = (u16)XEmacPs_ReadReg(InstancePtr->Config.BaseAddress,
+ XEMACPS_PHYMNTNC_OFFSET);
+ Status = (LONG)(XST_SUCCESS);
+ }
+ return Status;
+}
+
+
+/*****************************************************************************/
+/**
+* Write data to the specified PHY register. The Ethernet driver does not
+* require the device to be stopped before writing to the PHY. Although it is
+* probably a good idea to stop the device, it is the responsibility of the
+* application to deem this necessary. The MAC provides the driver with the
+* ability to talk to a PHY that adheres to the Media Independent Interface
+* (MII) as defined in the IEEE 802.3 standard.
+*
+* Prior to PHY access with this function, the user should have setup the MDIO
+* clock with XEmacPs_SetMdioDivisor().
+*
+* @param InstancePtr is a pointer to the XEmacPs instance to be worked on.
+* @param PhyAddress is the address of the PHY to be written (supports multiple
+* PHYs)
+* @param RegisterNum is the register number, 0-31, of the specific PHY register
+* to write
+* @param PhyData is the 16-bit value that will be written to the register
+*
+* @return
+*
+* - XST_SUCCESS if the PHY was written to successfully. Since there is no error
+* status from the MAC on a write, the user should read the PHY to verify the
+* write was successful.
+* - XST_EMAC_MII_BUSY if there is another PHY operation in progress
+*
+* @note
+*
+* This function is not thread-safe. The user must provide mutually exclusive
+* access to this function if there are to be multiple threads that can call it.
+*
+* There is the possibility that this function will not return if the hardware
+* is broken (i.e., it never sets the status bit indicating that the write is
+* done). If this is of concern to the user, the user should provide a mechanism
+* suitable to their needs for recovery.
+*
+* For the duration of this function, all host interface reads and writes are
+* blocked to the current XEmacPs instance.
+*
+******************************************************************************/
+LONG XEmacPs_PhyWrite(XEmacPs *InstancePtr, u32 PhyAddress,
+ u32 RegisterNum, u16 PhyData)
+{
+ u32 Mgtcr;
+ volatile u32 Ipisr;
+ u32 IpWriteTemp;
+ LONG Status;
+
+ Xil_AssertNonvoid(InstancePtr != NULL);
+
+ /* Make sure no other PHY operation is currently in progress */
+ if ((!(XEmacPs_ReadReg(InstancePtr->Config.BaseAddress,
+ XEMACPS_NWSR_OFFSET) &
+ XEMACPS_NWSR_MDIOIDLE_MASK))==TRUE) {
+ Status = (LONG)(XST_EMAC_MII_BUSY);
+ } else {
+ /* Construct Mgtcr mask for the operation */
+ Mgtcr = XEMACPS_PHYMNTNC_OP_MASK | XEMACPS_PHYMNTNC_OP_W_MASK |
+ (PhyAddress << XEMACPS_PHYMNTNC_PHAD_SHFT_MSK) |
+ (RegisterNum << XEMACPS_PHYMNTNC_PREG_SHFT_MSK) | (u32)PhyData;
+
+ /* Write Mgtcr and wait for completion */
+ XEmacPs_WriteReg(InstancePtr->Config.BaseAddress,
+ XEMACPS_PHYMNTNC_OFFSET, Mgtcr);
+
+ do {
+ Ipisr = XEmacPs_ReadReg(InstancePtr->Config.BaseAddress,
+ XEMACPS_NWSR_OFFSET);
+ IpWriteTemp = Ipisr;
+ } while ((IpWriteTemp & XEMACPS_NWSR_MDIOIDLE_MASK) == 0x00000000U);
+
+ Status = (LONG)(XST_SUCCESS);
+ }
+ return Status;
+}
+
+/*****************************************************************************/
+/**
+* API to update the Burst length in the DMACR register.
+*
+* @param InstancePtr is a pointer to the XEmacPs instance to be worked on.
+* @param BLength is the length in bytes for the dma burst.
+*
+* @return None
+*
+******************************************************************************/
+void XEmacPs_DMABLengthUpdate(XEmacPs *InstancePtr, s32 BLength)
+{
+ u32 Reg;
+ u32 RegUpdateVal = 0;
+
+ Xil_AssertVoid(InstancePtr != NULL);
+ Xil_AssertVoid((BLength == XEMACPS_SINGLE_BURST) ||
+ (BLength == XEMACPS_4BYTE_BURST) ||
+ (BLength == XEMACPS_8BYTE_BURST) ||
+ (BLength == XEMACPS_16BYTE_BURST));
+
+ switch (BLength) {
+ case XEMACPS_SINGLE_BURST:
+ RegUpdateVal = XEMACPS_DMACR_SINGLE_AHB_BURST;
+ break;
+
+ case XEMACPS_4BYTE_BURST:
+ RegUpdateVal = XEMACPS_DMACR_INCR4_AHB_BURST;
+ break;
+
+ case XEMACPS_8BYTE_BURST:
+ RegUpdateVal = XEMACPS_DMACR_INCR8_AHB_BURST;
+ break;
+
+ case XEMACPS_16BYTE_BURST:
+ RegUpdateVal = XEMACPS_DMACR_INCR16_AHB_BURST;
+ break;
+ }
+ Reg = XEmacPs_ReadReg(InstancePtr->Config.BaseAddress,
+ XEMACPS_DMACR_OFFSET);
+
+ Reg &= (u32)(~XEMACPS_DMACR_BLENGTH_MASK);
+ Reg |= RegUpdateVal;
+ XEmacPs_WriteReg(InstancePtr->Config.BaseAddress, XEMACPS_DMACR_OFFSET,
+ Reg);
+}
+/** @} */
diff --git a/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/emacps_v3_10/src/xemacps_g.c b/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/emacps_v3_10/src/xemacps_g.c
new file mode 100644
index 0000000..6d2ce3f
--- /dev/null
+++ b/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/emacps_v3_10/src/xemacps_g.c
@@ -0,0 +1,48 @@
+
+/*******************************************************************
+*
+* CAUTION: This file is automatically generated by HSI.
+* Version: 2019.2
+* DO NOT EDIT.
+*
+* Copyright (C) 2010-2021 Xilinx, Inc. All Rights Reserved.*
+*Permission is hereby granted, free of charge, to any person obtaining a copy
+*of this software and associated documentation files (the Software), to deal
+*in the Software without restriction, including without limitation the rights
+*to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+*copies of the Software, and to permit persons to whom the Software is
+*furnished to do so, subject to the following conditions:
+*
+*The above copyright notice and this permission notice shall be included in
+*all copies or substantial portions of the Software.
+*
+*THE SOFTWARE IS PROVIDED AS IS, WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+*IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+*FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+*THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+*WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT
+*OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+*
+
+*
+* Description: Driver configuration
+*
+*******************************************************************/
+
+#include "xparameters.h"
+#include "xemacps.h"
+
+/*
+* The configuration table for devices
+*/
+
+XEmacPs_Config XEmacPs_ConfigTable[XPAR_XEMACPS_NUM_INSTANCES] =
+{
+ {
+ XPAR_PS7_ETHERNET_0_DEVICE_ID,
+ XPAR_PS7_ETHERNET_0_BASEADDR,
+ XPAR_PS7_ETHERNET_0_IS_CACHE_COHERENT
+ }
+};
+
+
diff --git a/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/emacps_v3_10/src/xemacps_hw.c b/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/emacps_v3_10/src/xemacps_hw.c
new file mode 100644
index 0000000..a66ffa0
--- /dev/null
+++ b/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/emacps_v3_10/src/xemacps_hw.c
@@ -0,0 +1,117 @@
+/******************************************************************************
+*
+* Copyright (C) 2010 - 2019 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+* THE SOFTWARE.
+*
+*
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xemacps_hw.c
+* @addtogroup emacps_v3_10
+* @{
+*
+* This file contains the implementation of the ethernet interface reset sequence
+*
+* <pre>
+* MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ----- ---- -------- -------------------------------------------------------
+* 1.05a kpc 28/06/13 First release
+* 3.00 kvn 02/13/15 Modified code for MISRA-C:2012 compliance.
+* </pre>
+*
+******************************************************************************/
+
+/***************************** Include Files *********************************/
+
+#include "xemacps_hw.h"
+#include "xparameters.h"
+
+/************************** Constant Definitions *****************************/
+
+
+/**************************** Type Definitions *******************************/
+
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+
+/************************** Function Prototypes ******************************/
+
+/*****************************************************************************/
+/**
+* This function perform the reset sequence to the given emacps interface by
+* configuring the appropriate control bits in the emacps specific registers.
+* the emacps reset sequence involves the following steps
+* Disable all the interuupts
+* Clear the status registers
+* Disable Rx and Tx engines
+* Update the Tx and Rx descriptor queue registers with reset values
+* Update the other relevant control registers with reset value
+*
+* @param BaseAddr of the interface
+*
+* @return N/A
+*
+* @note
+* This function will not modify the slcr registers that are relevant for
+* emacps controller
+******************************************************************************/
+void XEmacPs_ResetHw(u32 BaseAddr)
+{
+ u32 RegVal;
+
+ /* Disable the interrupts */
+ XEmacPs_WriteReg(BaseAddr,XEMACPS_IDR_OFFSET,0x0U);
+
+ /* Stop transmission,disable loopback and Stop tx and Rx engines */
+ RegVal = XEmacPs_ReadReg(BaseAddr,XEMACPS_NWCTRL_OFFSET);
+ RegVal &= ~((u32)XEMACPS_NWCTRL_TXEN_MASK|
+ (u32)XEMACPS_NWCTRL_RXEN_MASK|
+ (u32)XEMACPS_NWCTRL_HALTTX_MASK|
+ (u32)XEMACPS_NWCTRL_LOOPEN_MASK);
+ /* Clear the statistic registers, flush the packets in DPRAM*/
+ RegVal |= (XEMACPS_NWCTRL_STATCLR_MASK|
+ XEMACPS_NWCTRL_FLUSH_DPRAM_MASK);
+ XEmacPs_WriteReg(BaseAddr,XEMACPS_NWCTRL_OFFSET,RegVal);
+ /* Clear the interrupt status */
+ XEmacPs_WriteReg(BaseAddr,XEMACPS_ISR_OFFSET,XEMACPS_IXR_ALL_MASK);
+ /* Clear the tx status */
+ XEmacPs_WriteReg(BaseAddr,XEMACPS_TXSR_OFFSET,(XEMACPS_TXSR_ERROR_MASK|
+ (u32)XEMACPS_TXSR_TXCOMPL_MASK|
+ (u32)XEMACPS_TXSR_TXGO_MASK));
+ /* Clear the rx status */
+ XEmacPs_WriteReg(BaseAddr,XEMACPS_RXSR_OFFSET,
+ XEMACPS_RXSR_FRAMERX_MASK);
+ /* Clear the tx base address */
+ XEmacPs_WriteReg(BaseAddr,XEMACPS_TXQBASE_OFFSET,0x0U);
+ /* Clear the rx base address */
+ XEmacPs_WriteReg(BaseAddr,XEMACPS_RXQBASE_OFFSET,0x0U);
+ /* Update the network config register with reset value */
+ XEmacPs_WriteReg(BaseAddr,XEMACPS_NWCFG_OFFSET,XEMACPS_NWCFG_RESET_MASK);
+ /* Update the hash address registers with reset value */
+ XEmacPs_WriteReg(BaseAddr,XEMACPS_HASHL_OFFSET,0x0U);
+ XEmacPs_WriteReg(BaseAddr,XEMACPS_HASHH_OFFSET,0x0U);
+}
+/** @} */
diff --git a/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/emacps_v3_10/src/xemacps_hw.h b/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/emacps_v3_10/src/xemacps_hw.h
new file mode 100644
index 0000000..8b902d3
--- /dev/null
+++ b/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/emacps_v3_10/src/xemacps_hw.h
@@ -0,0 +1,666 @@
+/******************************************************************************
+*
+* Copyright (C) 2010 - 2019 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+* THE SOFTWARE.
+*
+*
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xemacps_hw.h
+* @addtogroup emacps_v3_10
+* @{
+*
+* This header file contains identifiers and low-level driver functions (or
+* macros) that can be used to access the PS Ethernet MAC (XEmacPs) device.
+* High-level driver functions are defined in xemacps.h.
+*
+* @note
+*
+* <pre>
+* MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ----- ---- -------- -------------------------------------------------------
+* 1.00a wsy 01/10/10 First release.
+* 1.02a asa 11/05/12 Added hash defines for DMACR burst length configuration.
+* 1.05a kpc 28/06/13 Added XEmacPs_ResetHw function prototype
+* 1.06a asa 11/02/13 Changed the value for XEMACPS_RXBUF_LEN_MASK from 0x3fff
+* to 0x1fff. This fixes the CR#744902.
+* 2.1 srt 07/15/14 Add support for Zynq Ultrascale Mp GEM specification.
+* 3.0 kvn 12/16/14 Changed name of XEMACPS_NWCFG_LENGTHERRDSCRD_MASK to
+* XEMACPS_NWCFG_LENERRDSCRD_MASK as it exceeds 31 characters.
+* 3.0 kpc 1/23/15 Corrected the extended descriptor macro values.
+* 3.0 kvn 02/13/15 Modified code for MISRA-C:2012 compliance.
+* 3.0 hk 03/18/15 Added support for jumbo frames.
+* Remove "used bit set" from TX error interrupt masks.
+* 3.1 hk 08/10/15 Update upper 32 bit tx and rx queue ptr register offsets.
+* 3.2 hk 02/22/16 Added SGMII support for Zynq Ultrascale+ MPSoC.
+* 3.8 hk 09/17/18 Fix PTP interrupt masks.
+* 3.9 hk 01/23/19 Add RX watermark support
+* 3.10 hk 05/16/19 Clear status registers properly in reset
+* </pre>
+*
+******************************************************************************/
+
+#ifndef XEMACPS_HW_H /* prevent circular inclusions */
+#define XEMACPS_HW_H /* by using protection macros */
+
+/***************************** Include Files *********************************/
+
+#include "xil_types.h"
+#include "xil_assert.h"
+#include "xil_io.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/************************** Constant Definitions *****************************/
+
+#define XEMACPS_MAX_MAC_ADDR 4U /**< Maxmum number of mac address
+ supported */
+#define XEMACPS_MAX_TYPE_ID 4U /**< Maxmum number of type id supported */
+
+#ifdef __aarch64__
+#define XEMACPS_BD_ALIGNMENT 64U /**< Minimum buffer descriptor alignment
+ on the local bus */
+#else
+
+#define XEMACPS_BD_ALIGNMENT 4U /**< Minimum buffer descriptor alignment
+ on the local bus */
+#endif
+#define XEMACPS_RX_BUF_ALIGNMENT 4U /**< Minimum buffer alignment when using
+ options that impose alignment
+ restrictions on the buffer data on
+ the local bus */
+
+/** @name Direction identifiers
+ *
+ * These are used by several functions and callbacks that need
+ * to specify whether an operation specifies a send or receive channel.
+ * @{
+ */
+#define XEMACPS_SEND 1U /**< send direction */
+#define XEMACPS_RECV 2U /**< receive direction */
+/*@}*/
+
+/** @name MDC clock division
+ * currently supporting 8, 16, 32, 48, 64, 96, 128, 224.
+ * @{
+ */
+typedef enum { MDC_DIV_8 = 0U, MDC_DIV_16, MDC_DIV_32, MDC_DIV_48,
+ MDC_DIV_64, MDC_DIV_96, MDC_DIV_128, MDC_DIV_224
+} XEmacPs_MdcDiv;
+
+/*@}*/
+
+#define XEMACPS_RX_BUF_SIZE 1536U /**< Specify the receive buffer size in
+ bytes, 64, 128, ... 10240 */
+#define XEMACPS_RX_BUF_SIZE_JUMBO 10240U
+
+#define XEMACPS_RX_BUF_UNIT 64U /**< Number of receive buffer bytes as a
+ unit, this is HW setup */
+
+#define XEMACPS_MAX_RXBD 128U /**< Size of RX buffer descriptor queues */
+#define XEMACPS_MAX_TXBD 128U /**< Size of TX buffer descriptor queues */
+
+#define XEMACPS_MAX_HASH_BITS 64U /**< Maximum value for hash bits. 2**6 */
+
+/* Register offset definitions. Unless otherwise noted, register access is
+ * 32 bit. Names are self explained here.
+ */
+
+#define XEMACPS_NWCTRL_OFFSET 0x00000000U /**< Network Control reg */
+#define XEMACPS_NWCFG_OFFSET 0x00000004U /**< Network Config reg */
+#define XEMACPS_NWSR_OFFSET 0x00000008U /**< Network Status reg */
+
+#define XEMACPS_DMACR_OFFSET 0x00000010U /**< DMA Control reg */
+#define XEMACPS_TXSR_OFFSET 0x00000014U /**< TX Status reg */
+#define XEMACPS_RXQBASE_OFFSET 0x00000018U /**< RX Q Base address reg */
+#define XEMACPS_TXQBASE_OFFSET 0x0000001CU /**< TX Q Base address reg */
+#define XEMACPS_RXSR_OFFSET 0x00000020U /**< RX Status reg */
+
+#define XEMACPS_ISR_OFFSET 0x00000024U /**< Interrupt Status reg */
+#define XEMACPS_IER_OFFSET 0x00000028U /**< Interrupt Enable reg */
+#define XEMACPS_IDR_OFFSET 0x0000002CU /**< Interrupt Disable reg */
+#define XEMACPS_IMR_OFFSET 0x00000030U /**< Interrupt Mask reg */
+
+#define XEMACPS_PHYMNTNC_OFFSET 0x00000034U /**< Phy Maintaince reg */
+#define XEMACPS_RXPAUSE_OFFSET 0x00000038U /**< RX Pause Time reg */
+#define XEMACPS_TXPAUSE_OFFSET 0x0000003CU /**< TX Pause Time reg */
+
+#define XEMACPS_JUMBOMAXLEN_OFFSET 0x00000048U /**< Jumbo max length reg */
+
+#define XEMACPS_RXWATERMARK_OFFSET 0x0000007CU /**< RX watermark reg */
+
+#define XEMACPS_HASHL_OFFSET 0x00000080U /**< Hash Low address reg */
+#define XEMACPS_HASHH_OFFSET 0x00000084U /**< Hash High address reg */
+
+#define XEMACPS_LADDR1L_OFFSET 0x00000088U /**< Specific1 addr low reg */
+#define XEMACPS_LADDR1H_OFFSET 0x0000008CU /**< Specific1 addr high reg */
+#define XEMACPS_LADDR2L_OFFSET 0x00000090U /**< Specific2 addr low reg */
+#define XEMACPS_LADDR2H_OFFSET 0x00000094U /**< Specific2 addr high reg */
+#define XEMACPS_LADDR3L_OFFSET 0x00000098U /**< Specific3 addr low reg */
+#define XEMACPS_LADDR3H_OFFSET 0x0000009CU /**< Specific3 addr high reg */
+#define XEMACPS_LADDR4L_OFFSET 0x000000A0U /**< Specific4 addr low reg */
+#define XEMACPS_LADDR4H_OFFSET 0x000000A4U /**< Specific4 addr high reg */
+
+#define XEMACPS_MATCH1_OFFSET 0x000000A8U /**< Type ID1 Match reg */
+#define XEMACPS_MATCH2_OFFSET 0x000000ACU /**< Type ID2 Match reg */
+#define XEMACPS_MATCH3_OFFSET 0x000000B0U /**< Type ID3 Match reg */
+#define XEMACPS_MATCH4_OFFSET 0x000000B4U /**< Type ID4 Match reg */
+
+#define XEMACPS_STRETCH_OFFSET 0x000000BCU /**< IPG Stretch reg */
+
+#define XEMACPS_OCTTXL_OFFSET 0x00000100U /**< Octects transmitted Low
+ reg */
+#define XEMACPS_OCTTXH_OFFSET 0x00000104U /**< Octects transmitted High
+ reg */
+
+#define XEMACPS_TXCNT_OFFSET 0x00000108U /**< Error-free Frmaes
+ transmitted counter */
+#define XEMACPS_TXBCCNT_OFFSET 0x0000010CU /**< Error-free Broadcast
+ Frames counter*/
+#define XEMACPS_TXMCCNT_OFFSET 0x00000110U /**< Error-free Multicast
+ Frame counter */
+#define XEMACPS_TXPAUSECNT_OFFSET 0x00000114U /**< Pause Frames Transmitted
+ Counter */
+#define XEMACPS_TX64CNT_OFFSET 0x00000118U /**< Error-free 64 byte Frames
+ Transmitted counter */
+#define XEMACPS_TX65CNT_OFFSET 0x0000011CU /**< Error-free 65-127 byte
+ Frames Transmitted
+ counter */
+#define XEMACPS_TX128CNT_OFFSET 0x00000120U /**< Error-free 128-255 byte
+ Frames Transmitted
+ counter*/
+#define XEMACPS_TX256CNT_OFFSET 0x00000124U /**< Error-free 256-511 byte
+ Frames transmitted
+ counter */
+#define XEMACPS_TX512CNT_OFFSET 0x00000128U /**< Error-free 512-1023 byte
+ Frames transmitted
+ counter */
+#define XEMACPS_TX1024CNT_OFFSET 0x0000012CU /**< Error-free 1024-1518 byte
+ Frames transmitted
+ counter */
+#define XEMACPS_TX1519CNT_OFFSET 0x00000130U /**< Error-free larger than
+ 1519 byte Frames
+ transmitted counter */
+#define XEMACPS_TXURUNCNT_OFFSET 0x00000134U /**< TX under run error
+ counter */
+
+#define XEMACPS_SNGLCOLLCNT_OFFSET 0x00000138U /**< Single Collision Frame
+ Counter */
+#define XEMACPS_MULTICOLLCNT_OFFSET 0x0000013CU /**< Multiple Collision Frame
+ Counter */
+#define XEMACPS_EXCESSCOLLCNT_OFFSET 0x00000140U /**< Excessive Collision Frame
+ Counter */
+#define XEMACPS_LATECOLLCNT_OFFSET 0x00000144U /**< Late Collision Frame
+ Counter */
+#define XEMACPS_TXDEFERCNT_OFFSET 0x00000148U /**< Deferred Transmission
+ Frame Counter */
+#define XEMACPS_TXCSENSECNT_OFFSET 0x0000014CU /**< Transmit Carrier Sense
+ Error Counter */
+
+#define XEMACPS_OCTRXL_OFFSET 0x00000150U /**< Octects Received register
+ Low */
+#define XEMACPS_OCTRXH_OFFSET 0x00000154U /**< Octects Received register
+ High */
+
+#define XEMACPS_RXCNT_OFFSET 0x00000158U /**< Error-free Frames
+ Received Counter */
+#define XEMACPS_RXBROADCNT_OFFSET 0x0000015CU /**< Error-free Broadcast
+ Frames Received Counter */
+#define XEMACPS_RXMULTICNT_OFFSET 0x00000160U /**< Error-free Multicast
+ Frames Received Counter */
+#define XEMACPS_RXPAUSECNT_OFFSET 0x00000164U /**< Pause Frames
+ Received Counter */
+#define XEMACPS_RX64CNT_OFFSET 0x00000168U /**< Error-free 64 byte Frames
+ Received Counter */
+#define XEMACPS_RX65CNT_OFFSET 0x0000016CU /**< Error-free 65-127 byte
+ Frames Received Counter */
+#define XEMACPS_RX128CNT_OFFSET 0x00000170U /**< Error-free 128-255 byte
+ Frames Received Counter */
+#define XEMACPS_RX256CNT_OFFSET 0x00000174U /**< Error-free 256-512 byte
+ Frames Received Counter */
+#define XEMACPS_RX512CNT_OFFSET 0x00000178U /**< Error-free 512-1023 byte
+ Frames Received Counter */
+#define XEMACPS_RX1024CNT_OFFSET 0x0000017CU /**< Error-free 1024-1518 byte
+ Frames Received Counter */
+#define XEMACPS_RX1519CNT_OFFSET 0x00000180U /**< Error-free 1519-max byte
+ Frames Received Counter */
+#define XEMACPS_RXUNDRCNT_OFFSET 0x00000184U /**< Undersize Frames Received
+ Counter */
+#define XEMACPS_RXOVRCNT_OFFSET 0x00000188U /**< Oversize Frames Received
+ Counter */
+#define XEMACPS_RXJABCNT_OFFSET 0x0000018CU /**< Jabbers Received
+ Counter */
+#define XEMACPS_RXFCSCNT_OFFSET 0x00000190U /**< Frame Check Sequence
+ Error Counter */
+#define XEMACPS_RXLENGTHCNT_OFFSET 0x00000194U /**< Length Field Error
+ Counter */
+#define XEMACPS_RXSYMBCNT_OFFSET 0x00000198U /**< Symbol Error Counter */
+#define XEMACPS_RXALIGNCNT_OFFSET 0x0000019CU /**< Alignment Error Counter */
+#define XEMACPS_RXRESERRCNT_OFFSET 0x000001A0U /**< Receive Resource Error
+ Counter */
+#define XEMACPS_RXORCNT_OFFSET 0x000001A4U /**< Receive Overrun Counter */
+#define XEMACPS_RXIPCCNT_OFFSET 0x000001A8U /**< IP header Checksum Error
+ Counter */
+#define XEMACPS_RXTCPCCNT_OFFSET 0x000001ACU /**< TCP Checksum Error
+ Counter */
+#define XEMACPS_RXUDPCCNT_OFFSET 0x000001B0U /**< UDP Checksum Error
+ Counter */
+#define XEMACPS_LAST_OFFSET 0x000001B4U /**< Last statistic counter
+ offset, for clearing */
+
+#define XEMACPS_1588_SEC_OFFSET 0x000001D0U /**< 1588 second counter */
+#define XEMACPS_1588_NANOSEC_OFFSET 0x000001D4U /**< 1588 nanosecond counter */
+#define XEMACPS_1588_ADJ_OFFSET 0x000001D8U /**< 1588 nanosecond
+ adjustment counter */
+#define XEMACPS_1588_INC_OFFSET 0x000001DCU /**< 1588 nanosecond
+ increment counter */
+#define XEMACPS_PTP_TXSEC_OFFSET 0x000001E0U /**< 1588 PTP transmit second
+ counter */
+#define XEMACPS_PTP_TXNANOSEC_OFFSET 0x000001E4U /**< 1588 PTP transmit
+ nanosecond counter */
+#define XEMACPS_PTP_RXSEC_OFFSET 0x000001E8U /**< 1588 PTP receive second
+ counter */
+#define XEMACPS_PTP_RXNANOSEC_OFFSET 0x000001ECU /**< 1588 PTP receive
+ nanosecond counter */
+#define XEMACPS_PTPP_TXSEC_OFFSET 0x000001F0U /**< 1588 PTP peer transmit
+ second counter */
+#define XEMACPS_PTPP_TXNANOSEC_OFFSET 0x000001F4U /**< 1588 PTP peer transmit
+ nanosecond counter */
+#define XEMACPS_PTPP_RXSEC_OFFSET 0x000001F8U /**< 1588 PTP peer receive
+ second counter */
+#define XEMACPS_PTPP_RXNANOSEC_OFFSET 0x000001FCU /**< 1588 PTP peer receive
+ nanosecond counter */
+
+#define XEMACPS_INTQ1_STS_OFFSET 0x00000400U /**< Interrupt Q1 Status
+ reg */
+#define XEMACPS_TXQ1BASE_OFFSET 0x00000440U /**< TX Q1 Base address
+ reg */
+#define XEMACPS_RXQ1BASE_OFFSET 0x00000480U /**< RX Q1 Base address
+ reg */
+#define XEMACPS_MSBBUF_TXQBASE_OFFSET 0x000004C8U /**< MSB Buffer TX Q Base
+ reg */
+#define XEMACPS_MSBBUF_RXQBASE_OFFSET 0x000004D4U /**< MSB Buffer RX Q Base
+ reg */
+#define XEMACPS_INTQ1_IER_OFFSET 0x00000600U /**< Interrupt Q1 Enable
+ reg */
+#define XEMACPS_INTQ1_IDR_OFFSET 0x00000620U /**< Interrupt Q1 Disable
+ reg */
+#define XEMACPS_INTQ1_IMR_OFFSET 0x00000640U /**< Interrupt Q1 Mask
+ reg */
+
+/* Define some bit positions for registers. */
+
+/** @name network control register bit definitions
+ * @{
+ */
+#define XEMACPS_NWCTRL_FLUSH_DPRAM_MASK 0x00040000U /**< Flush a packet from
+ Rx SRAM */
+#define XEMACPS_NWCTRL_ZEROPAUSETX_MASK 0x00000800U /**< Transmit zero quantum
+ pause frame */
+#define XEMACPS_NWCTRL_PAUSETX_MASK 0x00000800U /**< Transmit pause frame */
+#define XEMACPS_NWCTRL_HALTTX_MASK 0x00000400U /**< Halt transmission
+ after current frame */
+#define XEMACPS_NWCTRL_STARTTX_MASK 0x00000200U /**< Start tx (tx_go) */
+
+#define XEMACPS_NWCTRL_STATWEN_MASK 0x00000080U /**< Enable writing to
+ stat counters */
+#define XEMACPS_NWCTRL_STATINC_MASK 0x00000040U /**< Increment statistic
+ registers */
+#define XEMACPS_NWCTRL_STATCLR_MASK 0x00000020U /**< Clear statistic
+ registers */
+#define XEMACPS_NWCTRL_MDEN_MASK 0x00000010U /**< Enable MDIO port */
+#define XEMACPS_NWCTRL_TXEN_MASK 0x00000008U /**< Enable transmit */
+#define XEMACPS_NWCTRL_RXEN_MASK 0x00000004U /**< Enable receive */
+#define XEMACPS_NWCTRL_LOOPEN_MASK 0x00000002U /**< local loopback */
+/*@}*/
+
+/** @name network configuration register bit definitions
+ * @{
+ */
+#define XEMACPS_NWCFG_BADPREAMBEN_MASK 0x20000000U /**< disable rejection of
+ non-standard preamble */
+#define XEMACPS_NWCFG_IPDSTRETCH_MASK 0x10000000U /**< enable transmit IPG */
+#define XEMACPS_NWCFG_SGMIIEN_MASK 0x08000000U /**< SGMII Enable */
+#define XEMACPS_NWCFG_FCSIGNORE_MASK 0x04000000U /**< disable rejection of
+ FCS error */
+#define XEMACPS_NWCFG_HDRXEN_MASK 0x02000000U /**< RX half duplex */
+#define XEMACPS_NWCFG_RXCHKSUMEN_MASK 0x01000000U /**< enable RX checksum
+ offload */
+#define XEMACPS_NWCFG_PAUSECOPYDI_MASK 0x00800000U /**< Do not copy pause
+ Frames to memory */
+#define XEMACPS_NWCFG_DWIDTH_64_MASK 0x00200000U /**< 64 bit Data bus width */
+#define XEMACPS_NWCFG_MDC_SHIFT_MASK 18U /**< shift bits for MDC */
+#define XEMACPS_NWCFG_MDCCLKDIV_MASK 0x001C0000U /**< MDC Mask PCLK divisor */
+#define XEMACPS_NWCFG_FCSREM_MASK 0x00020000U /**< Discard FCS from
+ received frames */
+#define XEMACPS_NWCFG_LENERRDSCRD_MASK 0x00010000U
+/**< RX length error discard */
+#define XEMACPS_NWCFG_RXOFFS_MASK 0x0000C000U /**< RX buffer offset */
+#define XEMACPS_NWCFG_PAUSEEN_MASK 0x00002000U /**< Enable pause RX */
+#define XEMACPS_NWCFG_RETRYTESTEN_MASK 0x00001000U /**< Retry test */
+#define XEMACPS_NWCFG_XTADDMACHEN_MASK 0x00000200U
+/**< External address match enable */
+#define XEMACPS_NWCFG_PCSSEL_MASK 0x00000800U /**< PCS Select */
+#define XEMACPS_NWCFG_1000_MASK 0x00000400U /**< 1000 Mbps */
+#define XEMACPS_NWCFG_1536RXEN_MASK 0x00000100U /**< Enable 1536 byte
+ frames reception */
+#define XEMACPS_NWCFG_UCASTHASHEN_MASK 0x00000080U /**< Receive unicast hash
+ frames */
+#define XEMACPS_NWCFG_MCASTHASHEN_MASK 0x00000040U /**< Receive multicast hash
+ frames */
+#define XEMACPS_NWCFG_BCASTDI_MASK 0x00000020U /**< Do not receive
+ broadcast frames */
+#define XEMACPS_NWCFG_COPYALLEN_MASK 0x00000010U /**< Copy all frames */
+#define XEMACPS_NWCFG_JUMBO_MASK 0x00000008U /**< Jumbo frames */
+#define XEMACPS_NWCFG_NVLANDISC_MASK 0x00000004U /**< Receive only VLAN
+ frames */
+#define XEMACPS_NWCFG_FDEN_MASK 0x00000002U/**< full duplex */
+#define XEMACPS_NWCFG_100_MASK 0x00000001U /**< 100 Mbps */
+#define XEMACPS_NWCFG_RESET_MASK 0x00080000U/**< reset value */
+/*@}*/
+
+/** @name network status register bit definitaions
+ * @{
+ */
+#define XEMACPS_NWSR_MDIOIDLE_MASK 0x00000004U /**< PHY management idle */
+#define XEMACPS_NWSR_MDIO_MASK 0x00000002U /**< Status of mdio_in */
+/*@}*/
+
+
+/** @name MAC address register word 1 mask
+ * @{
+ */
+#define XEMACPS_LADDR_MACH_MASK 0x0000FFFFU /**< Address bits[47:32]
+ bit[31:0] are in BOTTOM */
+/*@}*/
+
+
+/** @name DMA control register bit definitions
+ * @{
+ */
+#define XEMACPS_DMACR_ADDR_WIDTH_64 0x40000000U /**< 64 bit address bus */
+#define XEMACPS_DMACR_TXEXTEND_MASK 0x20000000U /**< Tx Extended desc mode */
+#define XEMACPS_DMACR_RXEXTEND_MASK 0x10000000U /**< Rx Extended desc mode */
+#define XEMACPS_DMACR_RXBUF_MASK 0x00FF0000U /**< Mask bit for RX buffer
+ size */
+#define XEMACPS_DMACR_RXBUF_SHIFT 16U /**< Shift bit for RX buffer
+ size */
+#define XEMACPS_DMACR_TCPCKSUM_MASK 0x00000800U /**< enable/disable TX
+ checksum offload */
+#define XEMACPS_DMACR_TXSIZE_MASK 0x00000400U /**< TX buffer memory size */
+#define XEMACPS_DMACR_RXSIZE_MASK 0x00000300U /**< RX buffer memory size */
+#define XEMACPS_DMACR_ENDIAN_MASK 0x00000080U /**< endian configuration */
+#define XEMACPS_DMACR_BLENGTH_MASK 0x0000001FU /**< buffer burst length */
+#define XEMACPS_DMACR_SINGLE_AHB_BURST 0x00000001U /**< single AHB bursts */
+#define XEMACPS_DMACR_INCR4_AHB_BURST 0x00000004U /**< 4 bytes AHB bursts */
+#define XEMACPS_DMACR_INCR8_AHB_BURST 0x00000008U /**< 8 bytes AHB bursts */
+#define XEMACPS_DMACR_INCR16_AHB_BURST 0x00000010U /**< 16 bytes AHB bursts */
+/*@}*/
+
+/** @name transmit status register bit definitions
+ * @{
+ */
+#define XEMACPS_TXSR_HRESPNOK_MASK 0x00000100U /**< Transmit hresp not OK */
+#define XEMACPS_TXSR_URUN_MASK 0x00000040U /**< Transmit underrun */
+#define XEMACPS_TXSR_TXCOMPL_MASK 0x00000020U /**< Transmit completed OK */
+#define XEMACPS_TXSR_BUFEXH_MASK 0x00000010U /**< Transmit buffs exhausted
+ mid frame */
+#define XEMACPS_TXSR_TXGO_MASK 0x00000008U /**< Status of go flag */
+#define XEMACPS_TXSR_RXOVR_MASK 0x00000004U /**< Retry limit exceeded */
+#define XEMACPS_TXSR_FRAMERX_MASK 0x00000002U /**< Collision tx frame */
+#define XEMACPS_TXSR_USEDREAD_MASK 0x00000001U /**< TX buffer used bit set */
+
+#define XEMACPS_TXSR_ERROR_MASK ((u32)XEMACPS_TXSR_HRESPNOK_MASK | \
+ (u32)XEMACPS_TXSR_URUN_MASK | \
+ (u32)XEMACPS_TXSR_BUFEXH_MASK | \
+ (u32)XEMACPS_TXSR_RXOVR_MASK | \
+ (u32)XEMACPS_TXSR_FRAMERX_MASK | \
+ (u32)XEMACPS_TXSR_USEDREAD_MASK)
+/*@}*/
+
+/**
+ * @name receive status register bit definitions
+ * @{
+ */
+#define XEMACPS_RXSR_HRESPNOK_MASK 0x00000008U /**< Receive hresp not OK */
+#define XEMACPS_RXSR_RXOVR_MASK 0x00000004U /**< Receive overrun */
+#define XEMACPS_RXSR_FRAMERX_MASK 0x00000002U /**< Frame received OK */
+#define XEMACPS_RXSR_BUFFNA_MASK 0x00000001U /**< RX buffer used bit set */
+
+#define XEMACPS_RXSR_ERROR_MASK ((u32)XEMACPS_RXSR_HRESPNOK_MASK | \
+ (u32)XEMACPS_RXSR_RXOVR_MASK | \
+ (u32)XEMACPS_RXSR_BUFFNA_MASK)
+
+#define XEMACPS_SR_ALL_MASK 0xFFFFFFFFU /**< Mask for full register */
+
+/*@}*/
+
+/**
+ * @name Interrupt Q1 status register bit definitions
+ * @{
+ */
+#define XEMACPS_INTQ1SR_TXCOMPL_MASK 0x00000080U /**< Transmit completed OK */
+#define XEMACPS_INTQ1SR_TXERR_MASK 0x00000040U /**< Transmit AMBA Error */
+
+#define XEMACPS_INTQ1_IXR_ALL_MASK ((u32)XEMACPS_INTQ1SR_TXCOMPL_MASK | \
+ (u32)XEMACPS_INTQ1SR_TXERR_MASK)
+
+/*@}*/
+
+/**
+ * @name interrupts bit definitions
+ * Bits definitions are same in XEMACPS_ISR_OFFSET,
+ * XEMACPS_IER_OFFSET, XEMACPS_IDR_OFFSET, and XEMACPS_IMR_OFFSET
+ * @{
+ */
+#define XEMACPS_IXR_PTPPSTX_MASK 0x02000000U /**< PTP Pdelay_resp TXed */
+#define XEMACPS_IXR_PTPPDRTX_MASK 0x01000000U /**< PTP Pdelay_req TXed */
+#define XEMACPS_IXR_PTPPSRX_MASK 0x00800000U /**< PTP Pdelay_resp RXed */
+#define XEMACPS_IXR_PTPPDRRX_MASK 0x00400000U /**< PTP Pdelay_req RXed */
+
+#define XEMACPS_IXR_PTPSTX_MASK 0x00200000U /**< PTP Sync TXed */
+#define XEMACPS_IXR_PTPDRTX_MASK 0x00100000U /**< PTP Delay_req TXed */
+#define XEMACPS_IXR_PTPSRX_MASK 0x00080000U /**< PTP Sync RXed */
+#define XEMACPS_IXR_PTPDRRX_MASK 0x00040000U /**< PTP Delay_req RXed */
+
+#define XEMACPS_IXR_PAUSETX_MASK 0x00004000U /**< Pause frame transmitted */
+#define XEMACPS_IXR_PAUSEZERO_MASK 0x00002000U /**< Pause time has reached
+ zero */
+#define XEMACPS_IXR_PAUSENZERO_MASK 0x00001000U /**< Pause frame received */
+#define XEMACPS_IXR_HRESPNOK_MASK 0x00000800U /**< hresp not ok */
+#define XEMACPS_IXR_RXOVR_MASK 0x00000400U /**< Receive overrun occurred */
+#define XEMACPS_IXR_TXCOMPL_MASK 0x00000080U /**< Frame transmitted ok */
+#define XEMACPS_IXR_TXEXH_MASK 0x00000040U /**< Transmit err occurred or
+ no buffers*/
+#define XEMACPS_IXR_RETRY_MASK 0x00000020U /**< Retry limit exceeded */
+#define XEMACPS_IXR_URUN_MASK 0x00000010U /**< Transmit underrun */
+#define XEMACPS_IXR_TXUSED_MASK 0x00000008U /**< Tx buffer used bit read */
+#define XEMACPS_IXR_RXUSED_MASK 0x00000004U /**< Rx buffer used bit read */
+#define XEMACPS_IXR_FRAMERX_MASK 0x00000002U /**< Frame received ok */
+#define XEMACPS_IXR_MGMNT_MASK 0x00000001U /**< PHY management complete */
+#define XEMACPS_IXR_ALL_MASK 0x00007FFFU /**< Everything! */
+
+#define XEMACPS_IXR_TX_ERR_MASK ((u32)XEMACPS_IXR_TXEXH_MASK | \
+ (u32)XEMACPS_IXR_RETRY_MASK | \
+ (u32)XEMACPS_IXR_URUN_MASK)
+
+
+#define XEMACPS_IXR_RX_ERR_MASK ((u32)XEMACPS_IXR_HRESPNOK_MASK | \
+ (u32)XEMACPS_IXR_RXUSED_MASK | \
+ (u32)XEMACPS_IXR_RXOVR_MASK)
+
+/*@}*/
+
+/** @name PHY Maintenance bit definitions
+ * @{
+ */
+#define XEMACPS_PHYMNTNC_OP_MASK 0x40020000U /**< operation mask bits */
+#define XEMACPS_PHYMNTNC_OP_R_MASK 0x20000000U /**< read operation */
+#define XEMACPS_PHYMNTNC_OP_W_MASK 0x10000000U /**< write operation */
+#define XEMACPS_PHYMNTNC_ADDR_MASK 0x0F800000U /**< Address bits */
+#define XEMACPS_PHYMNTNC_REG_MASK 0x007C0000U /**< register bits */
+#define XEMACPS_PHYMNTNC_DATA_MASK 0x00000FFFU /**< data bits */
+#define XEMACPS_PHYMNTNC_PHAD_SHFT_MSK 23U /**< Shift bits for PHYAD */
+#define XEMACPS_PHYMNTNC_PREG_SHFT_MSK 18U /**< Shift bits for PHREG */
+/*@}*/
+
+/** @name RX watermark bit definitions
+ * @{
+ */
+#define XEMACPS_RXWM_HIGH_MASK 0x0000FFFFU /**< RXWM high mask */
+#define XEMACPS_RXWM_LOW_MASK 0xFFFF0000U /**< RXWM low mask */
+#define XEMACPS_RXWM_LOW_SHFT_MSK 16U /**< Shift for RXWM low */
+/*@}*/
+
+/* Transmit buffer descriptor status words offset
+ * @{
+ */
+#define XEMACPS_BD_ADDR_OFFSET 0x00000000U /**< word 0/addr of BDs */
+#define XEMACPS_BD_STAT_OFFSET 0x00000004U /**< word 1/status of BDs */
+#define XEMACPS_BD_ADDR_HI_OFFSET 0x00000008U /**< word 2/addr of BDs */
+
+/*
+ * @}
+ */
+
+/* Transmit buffer descriptor status words bit positions.
+ * Transmit buffer descriptor consists of two 32-bit registers,
+ * the first - word0 contains a 32-bit address pointing to the location of
+ * the transmit data.
+ * The following register - word1, consists of various information to control
+ * the XEmacPs transmit process. After transmit, this is updated with status
+ * information, whether the frame was transmitted OK or why it had failed.
+ * @{
+ */
+#define XEMACPS_TXBUF_USED_MASK 0x80000000U /**< Used bit. */
+#define XEMACPS_TXBUF_WRAP_MASK 0x40000000U /**< Wrap bit, last descriptor */
+#define XEMACPS_TXBUF_RETRY_MASK 0x20000000U /**< Retry limit exceeded */
+#define XEMACPS_TXBUF_URUN_MASK 0x10000000U /**< Transmit underrun occurred */
+#define XEMACPS_TXBUF_EXH_MASK 0x08000000U /**< Buffers exhausted */
+#define XEMACPS_TXBUF_TCP_MASK 0x04000000U /**< Late collision. */
+#define XEMACPS_TXBUF_NOCRC_MASK 0x00010000U /**< No CRC */
+#define XEMACPS_TXBUF_LAST_MASK 0x00008000U /**< Last buffer */
+#define XEMACPS_TXBUF_LEN_MASK 0x00003FFFU /**< Mask for length field */
+/*
+ * @}
+ */
+
+/* Receive buffer descriptor status words bit positions.
+ * Receive buffer descriptor consists of two 32-bit registers,
+ * the first - word0 contains a 32-bit word aligned address pointing to the
+ * address of the buffer. The lower two bits make up the wrap bit indicating
+ * the last descriptor and the ownership bit to indicate it has been used by
+ * the XEmacPs.
+ * The following register - word1, contains status information regarding why
+ * the frame was received (the filter match condition) as well as other
+ * useful info.
+ * @{
+ */
+#define XEMACPS_RXBUF_BCAST_MASK 0x80000000U /**< Broadcast frame */
+#define XEMACPS_RXBUF_MULTIHASH_MASK 0x40000000U /**< Multicast hashed frame */
+#define XEMACPS_RXBUF_UNIHASH_MASK 0x20000000U /**< Unicast hashed frame */
+#define XEMACPS_RXBUF_EXH_MASK 0x08000000U /**< buffer exhausted */
+#define XEMACPS_RXBUF_AMATCH_MASK 0x06000000U /**< Specific address
+ matched */
+#define XEMACPS_RXBUF_IDFOUND_MASK 0x01000000U /**< Type ID matched */
+#define XEMACPS_RXBUF_IDMATCH_MASK 0x00C00000U /**< ID matched mask */
+#define XEMACPS_RXBUF_VLAN_MASK 0x00200000U /**< VLAN tagged */
+#define XEMACPS_RXBUF_PRI_MASK 0x00100000U /**< Priority tagged */
+#define XEMACPS_RXBUF_VPRI_MASK 0x000E0000U /**< Vlan priority */
+#define XEMACPS_RXBUF_CFI_MASK 0x00010000U /**< CFI frame */
+#define XEMACPS_RXBUF_EOF_MASK 0x00008000U /**< End of frame. */
+#define XEMACPS_RXBUF_SOF_MASK 0x00004000U /**< Start of frame. */
+#define XEMACPS_RXBUF_LEN_MASK 0x00001FFFU /**< Mask for length field */
+#define XEMACPS_RXBUF_LEN_JUMBO_MASK 0x00003FFFU /**< Mask for jumbo length */
+
+#define XEMACPS_RXBUF_WRAP_MASK 0x00000002U /**< Wrap bit, last BD */
+#define XEMACPS_RXBUF_NEW_MASK 0x00000001U /**< Used bit.. */
+#define XEMACPS_RXBUF_ADD_MASK 0xFFFFFFFCU /**< Mask for address */
+/*
+ * @}
+ */
+
+/*
+ * Define appropriate I/O access method to memory mapped I/O or other
+ * interface if necessary.
+ */
+
+#define XEmacPs_In32 Xil_In32
+#define XEmacPs_Out32 Xil_Out32
+
+
+/****************************************************************************/
+/**
+*
+* Read the given register.
+*
+* @param BaseAddress is the base address of the device
+* @param RegOffset is the register offset to be read
+*
+* @return The 32-bit value of the register
+*
+* @note
+* C-style signature:
+* u32 XEmacPs_ReadReg(u32 BaseAddress, u32 RegOffset)
+*
+*****************************************************************************/
+#define XEmacPs_ReadReg(BaseAddress, RegOffset) \
+ XEmacPs_In32((BaseAddress) + (u32)(RegOffset))
+
+
+/****************************************************************************/
+/**
+*
+* Write the given register.
+*
+* @param BaseAddress is the base address of the device
+* @param RegOffset is the register offset to be written
+* @param Data is the 32-bit value to write to the register
+*
+* @return None.
+*
+* @note
+* C-style signature:
+* void XEmacPs_WriteReg(u32 BaseAddress, u32 RegOffset,
+* u32 Data)
+*
+*****************************************************************************/
+#define XEmacPs_WriteReg(BaseAddress, RegOffset, Data) \
+ XEmacPs_Out32((BaseAddress) + (u32)(RegOffset), (u32)(Data))
+
+/************************** Function Prototypes *****************************/
+/*
+ * Perform reset operation to the emacps interface
+ */
+void XEmacPs_ResetHw(u32 BaseAddr);
+
+#ifdef __cplusplus
+ }
+#endif
+
+#endif /* end of protection macro */
+/** @} */
diff --git a/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/emacps_v3_10/src/xemacps_intr.c b/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/emacps_v3_10/src/xemacps_intr.c
new file mode 100644
index 0000000..76145d0
--- /dev/null
+++ b/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/emacps_v3_10/src/xemacps_intr.c
@@ -0,0 +1,262 @@
+/******************************************************************************
+*
+* Copyright (C) 2010 - 2019 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+* THE SOFTWARE.
+*
+*
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xemacps_intr.c
+* @addtogroup emacps_v3_10
+* @{
+*
+* Functions in this file implement general purpose interrupt processing related
+* functionality. See xemacps.h for a detailed description of the driver.
+*
+* <pre>
+* MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ----- ---- -------- -------------------------------------------------------
+* 1.00a wsy 01/10/10 First release
+* 1.03a asa 01/24/13 Fix for CR #692702 which updates error handling for
+* Rx errors. Under heavy Rx traffic, there will be a large
+* number of errors related to receive buffer not available.
+* Because of a HW bug (SI #692601), under such heavy errors,
+* the Rx data path can become unresponsive. To reduce the
+* probabilities for hitting this HW bug, the SW writes to
+* bit 18 to flush a packet from Rx DPRAM immediately. The
+* changes for it are done in the function
+* XEmacPs_IntrHandler.
+* 2.1 srt 07/15/14 Add support for Zynq Ultrascale Mp GEM specification
+* and 64-bit changes.
+* 3.0 kvn 02/13/15 Modified code for MISRA-C:2012 compliance.
+* 3.1 hk 07/27/15 Do not call error handler with '0' error code when
+* there is no error. CR# 869403
+* </pre>
+******************************************************************************/
+
+/***************************** Include Files *********************************/
+
+#include "xemacps.h"
+
+/************************** Constant Definitions *****************************/
+
+
+/**************************** Type Definitions *******************************/
+
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+
+/************************** Function Prototypes ******************************/
+
+
+/************************** Variable Definitions *****************************/
+
+
+/*****************************************************************************/
+/**
+ * Install an asynchronous handler function for the given HandlerType:
+ *
+ * @param InstancePtr is a pointer to the instance to be worked on.
+ * @param HandlerType indicates what interrupt handler type is.
+ * XEMACPS_HANDLER_DMASEND, XEMACPS_HANDLER_DMARECV and
+ * XEMACPS_HANDLER_ERROR.
+ * @param FuncPointer is the pointer to the callback function
+ * @param CallBackRef is the upper layer callback reference passed back when
+ * when the callback function is invoked.
+ *
+ * @return
+ *
+ * None.
+ *
+ * @note
+ * There is no assert on the CallBackRef since the driver doesn't know what
+ * it is.
+ *
+ *****************************************************************************/
+LONG XEmacPs_SetHandler(XEmacPs *InstancePtr, u32 HandlerType,
+ void *FuncPointer, void *CallBackRef)
+{
+ LONG Status;
+ Xil_AssertNonvoid(InstancePtr != NULL);
+ Xil_AssertNonvoid(FuncPointer != NULL);
+ Xil_AssertNonvoid(InstancePtr->IsReady == (u32)XIL_COMPONENT_IS_READY);
+
+ switch (HandlerType) {
+ case XEMACPS_HANDLER_DMASEND:
+ Status = (LONG)(XST_SUCCESS);
+ InstancePtr->SendHandler = ((XEmacPs_Handler)(void *)FuncPointer);
+ InstancePtr->SendRef = CallBackRef;
+ break;
+ case XEMACPS_HANDLER_DMARECV:
+ Status = (LONG)(XST_SUCCESS);
+ InstancePtr->RecvHandler = ((XEmacPs_Handler)(void *)FuncPointer);
+ InstancePtr->RecvRef = CallBackRef;
+ break;
+ case XEMACPS_HANDLER_ERROR:
+ Status = (LONG)(XST_SUCCESS);
+ InstancePtr->ErrorHandler = ((XEmacPs_ErrHandler)(void *)FuncPointer);
+ InstancePtr->ErrorRef = CallBackRef;
+ break;
+ default:
+ Status = (LONG)(XST_INVALID_PARAM);
+ break;
+ }
+ return Status;
+}
+
+/*****************************************************************************/
+/**
+* Master interrupt handler for EMAC driver. This routine will query the
+* status of the device, bump statistics, and invoke user callbacks.
+*
+* This routine must be connected to an interrupt controller using OS/BSP
+* specific methods.
+*
+* @param XEmacPsPtr is a pointer to the XEMACPS instance that has caused the
+* interrupt.
+*
+******************************************************************************/
+void XEmacPs_IntrHandler(void *XEmacPsPtr)
+{
+ u32 RegISR;
+ u32 RegSR;
+ u32 RegCtrl;
+ u32 RegQ1ISR = 0U;
+ XEmacPs *InstancePtr = (XEmacPs *) XEmacPsPtr;
+
+ Xil_AssertVoid(InstancePtr != NULL);
+ Xil_AssertVoid(InstancePtr->IsReady == (u32)XIL_COMPONENT_IS_READY);
+
+ /* This ISR will try to handle as many interrupts as it can in a single
+ * call. However, in most of the places where the user's error handler
+ * is called, this ISR exits because it is expected that the user will
+ * reset the device in nearly all instances.
+ */
+ RegISR = XEmacPs_ReadReg(InstancePtr->Config.BaseAddress,
+ XEMACPS_ISR_OFFSET);
+
+ /* Read Transmit Q1 ISR */
+
+ if (InstancePtr->Version > 2)
+ RegQ1ISR = XEmacPs_ReadReg(InstancePtr->Config.BaseAddress,
+ XEMACPS_INTQ1_STS_OFFSET);
+
+ /* Clear the interrupt status register */
+ XEmacPs_WriteReg(InstancePtr->Config.BaseAddress, XEMACPS_ISR_OFFSET,
+ RegISR);
+
+ /* Receive complete interrupt */
+ if ((RegISR & XEMACPS_IXR_FRAMERX_MASK) != 0x00000000U) {
+ /* Clear RX status register RX complete indication but preserve
+ * error bits if there is any */
+ XEmacPs_WriteReg(InstancePtr->Config.BaseAddress,
+ XEMACPS_RXSR_OFFSET,
+ ((u32)XEMACPS_RXSR_FRAMERX_MASK |
+ (u32)XEMACPS_RXSR_BUFFNA_MASK));
+ InstancePtr->RecvHandler(InstancePtr->RecvRef);
+ }
+
+ /* Transmit Q1 complete interrupt */
+ if ((InstancePtr->Version > 2) &&
+ ((RegQ1ISR & XEMACPS_INTQ1SR_TXCOMPL_MASK) != 0x00000000U)) {
+ /* Clear TX status register TX complete indication but preserve
+ * error bits if there is any */
+ XEmacPs_WriteReg(InstancePtr->Config.BaseAddress,
+ XEMACPS_INTQ1_STS_OFFSET,
+ XEMACPS_INTQ1SR_TXCOMPL_MASK);
+ XEmacPs_WriteReg(InstancePtr->Config.BaseAddress,
+ XEMACPS_TXSR_OFFSET,
+ ((u32)XEMACPS_TXSR_TXCOMPL_MASK |
+ (u32)XEMACPS_TXSR_USEDREAD_MASK));
+ InstancePtr->SendHandler(InstancePtr->SendRef);
+ }
+
+ /* Transmit complete interrupt */
+ if ((RegISR & XEMACPS_IXR_TXCOMPL_MASK) != 0x00000000U) {
+ /* Clear TX status register TX complete indication but preserve
+ * error bits if there is any */
+ XEmacPs_WriteReg(InstancePtr->Config.BaseAddress,
+ XEMACPS_TXSR_OFFSET,
+ ((u32)XEMACPS_TXSR_TXCOMPL_MASK |
+ (u32)XEMACPS_TXSR_USEDREAD_MASK));
+ InstancePtr->SendHandler(InstancePtr->SendRef);
+ }
+
+ /* Receive error conditions interrupt */
+ if ((RegISR & XEMACPS_IXR_RX_ERR_MASK) != 0x00000000U) {
+ /* Clear RX status register */
+ RegSR = XEmacPs_ReadReg(InstancePtr->Config.BaseAddress,
+ XEMACPS_RXSR_OFFSET);
+ XEmacPs_WriteReg(InstancePtr->Config.BaseAddress,
+ XEMACPS_RXSR_OFFSET, RegSR);
+
+ /* Fix for CR # 692702. Write to bit 18 of net_ctrl
+ * register to flush a packet out of Rx SRAM upon
+ * an error for receive buffer not available. */
+ if ((RegISR & XEMACPS_IXR_RXUSED_MASK) != 0x00000000U) {
+ RegCtrl =
+ XEmacPs_ReadReg(InstancePtr->Config.BaseAddress,
+ XEMACPS_NWCTRL_OFFSET);
+ RegCtrl |= (u32)XEMACPS_NWCTRL_FLUSH_DPRAM_MASK;
+ XEmacPs_WriteReg(InstancePtr->Config.BaseAddress,
+ XEMACPS_NWCTRL_OFFSET, RegCtrl);
+ }
+
+ if(RegSR != 0) {
+ InstancePtr->ErrorHandler(InstancePtr->ErrorRef,
+ XEMACPS_RECV, RegSR);
+ }
+ }
+
+ /* When XEMACPS_IXR_TXCOMPL_MASK is flagged, XEMACPS_IXR_TXUSED_MASK
+ * will be asserted the same time.
+ * Have to distinguish this bit to handle the real error condition.
+ */
+ /* Transmit Q1 error conditions interrupt */
+ if ((InstancePtr->Version > 2) &&
+ ((RegQ1ISR & XEMACPS_INTQ1SR_TXERR_MASK) != 0x00000000U) &&
+ ((RegQ1ISR & XEMACPS_INTQ1SR_TXCOMPL_MASK) != 0x00000000U)) {
+ /* Clear Interrupt Q1 status register */
+ XEmacPs_WriteReg(InstancePtr->Config.BaseAddress,
+ XEMACPS_INTQ1_STS_OFFSET, RegQ1ISR);
+ InstancePtr->ErrorHandler(InstancePtr->ErrorRef, XEMACPS_SEND,
+ RegQ1ISR);
+ }
+
+ /* Transmit error conditions interrupt */
+ if (((RegISR & XEMACPS_IXR_TX_ERR_MASK) != 0x00000000U) &&
+ (!(RegISR & XEMACPS_IXR_TXCOMPL_MASK) != 0x00000000U)) {
+ /* Clear TX status register */
+ RegSR = XEmacPs_ReadReg(InstancePtr->Config.BaseAddress,
+ XEMACPS_TXSR_OFFSET);
+ XEmacPs_WriteReg(InstancePtr->Config.BaseAddress,
+ XEMACPS_TXSR_OFFSET, RegSR);
+ InstancePtr->ErrorHandler(InstancePtr->ErrorRef, XEMACPS_SEND,
+ RegSR);
+ }
+
+}
+/** @} */
diff --git a/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/emacps_v3_10/src/xemacps_sinit.c b/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/emacps_v3_10/src/xemacps_sinit.c
new file mode 100644
index 0000000..2c1cd52
--- /dev/null
+++ b/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/emacps_v3_10/src/xemacps_sinit.c
@@ -0,0 +1,91 @@
+/******************************************************************************
+*
+* Copyright (C) 2010 - 2019 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+* THE SOFTWARE.
+*
+*
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xemacps_sinit.c
+* @addtogroup emacps_v3_10
+* @{
+*
+* This file contains lookup method by device ID when success, it returns
+* pointer to config table to be used to initialize the device.
+*
+* <pre>
+* MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ----- ---- -------- -------------------------------------------------------
+* 1.00a wsy 01/10/10 New
+* 3.00 kvn 02/13/15 Modified code for MISRA-C:2012 compliance.
+* </pre>
+*
+******************************************************************************/
+
+/***************************** Include Files *********************************/
+
+#include "xemacps.h"
+#include "xparameters.h"
+
+/************************** Constant Definitions *****************************/
+
+
+/**************************** Type Definitions *******************************/
+
+/*************************** Variable Definitions *****************************/
+extern XEmacPs_Config XEmacPs_ConfigTable[XPAR_XEMACPS_NUM_INSTANCES];
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+
+/************************** Function Prototypes ******************************/
+
+/*****************************************************************************/
+/**
+* Lookup the device configuration based on the unique device ID. The table
+* contains the configuration info for each device in the system.
+*
+* @param DeviceId is the unique device ID of the device being looked up.
+*
+* @return
+* A pointer to the configuration table entry corresponding to the given
+* device ID, or NULL if no match is found.
+*
+******************************************************************************/
+XEmacPs_Config *XEmacPs_LookupConfig(u16 DeviceId)
+{
+ XEmacPs_Config *CfgPtr = NULL;
+ u32 i;
+
+ for (i = 0U; i < (u32)XPAR_XEMACPS_NUM_INSTANCES; i++) {
+ if (XEmacPs_ConfigTable[i].DeviceId == DeviceId) {
+ CfgPtr = &XEmacPs_ConfigTable[i];
+ break;
+ }
+ }
+
+ return (XEmacPs_Config *)(CfgPtr);
+}
+/** @} */
diff --git a/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/gpiops_v3_6/src/Makefile b/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/gpiops_v3_6/src/Makefile
new file mode 100644
index 0000000..8601ce4
--- /dev/null
+++ b/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/gpiops_v3_6/src/Makefile
@@ -0,0 +1,40 @@
+COMPILER=
+ARCHIVER=
+CP=cp
+COMPILER_FLAGS=
+EXTRA_COMPILER_FLAGS=
+LIB=libxil.a
+
+CC_FLAGS = $(COMPILER_FLAGS)
+ECC_FLAGS = $(EXTRA_COMPILER_FLAGS)
+
+RELEASEDIR=../../../lib
+INCLUDEDIR=../../../include
+INCLUDES=-I./. -I${INCLUDEDIR}
+
+OUTS = *.o
+
+LIBSOURCES:=*.c
+INCLUDEFILES:=*.h
+
+OBJECTS = $(addsuffix .o, $(basename $(wildcard *.c)))
+
+libs: banner xgpiops_libs clean
+
+%.o: %.c
+ ${COMPILER} $(CC_FLAGS) $(ECC_FLAGS) $(INCLUDES) -o $@ $<
+
+banner:
+ echo "Compiling gpiops"
+
+xgpiops_libs: ${OBJECTS}
+ $(ARCHIVER) -r ${RELEASEDIR}/${LIB} ${OBJECTS}
+
+.PHONY: include
+include: xgpiops_includes
+
+xgpiops_includes:
+ ${CP} ${INCLUDEFILES} ${INCLUDEDIR}
+
+clean:
+ rm -rf ${OBJECTS}
diff --git a/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/gpiops_v3_6/src/xgpiops.c b/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/gpiops_v3_6/src/xgpiops.c
new file mode 100644
index 0000000..44bfa51
--- /dev/null
+++ b/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/gpiops_v3_6/src/xgpiops.c
@@ -0,0 +1,828 @@
+/******************************************************************************
+*
+* Copyright (C) 2010 - 2019 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+* THE SOFTWARE.
+*
+*
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xgpiops.c
+* @addtogroup gpiops_v3_6
+* @{
+*
+* The XGpioPs driver. Functions in this file are the minimum required functions
+* for this driver. See xgpiops.h for a detailed description of the driver.
+*
+* <pre>
+* MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ----- ---- -------- -----------------------------------------------
+* 1.00a sv 01/15/10 First Release
+* 1.01a sv 04/15/12 Removed the APIs XGpioPs_SetMode, XGpioPs_SetModePin
+* XGpioPs_GetMode, XGpioPs_GetModePin as they are not
+* relevant to Zynq device. The interrupts are disabled
+* for output pins on all banks during initialization.
+* 2.1 hk 04/29/14 Use Input data register DATA_RO for read. CR# 771667.
+* 3.00 kvn 02/13/15 Modified code for MISRA-C:2012 compliance.
+* 3.1 kvn 04/13/15 Add support for Zynq Ultrascale+ MP. CR# 856980.
+* 3.1 aru 07/13/18 Resolved doxygen reported warnings. CR# 1006331.
+* 3.4 aru 08/17/18 Resolved MISRA-C mandatory violations. CR# 1007751
+* 3.5 sne 03/01/19 Fixes violations according to MISRAC-2012
+* in safety mode and modified the code such as
+* Use of mixed mode arithmetic,Declared the pointer param
+* as Pointer to const,Casting operation to a pointer,
+* Literal value requires a U suffix.
+* 3.5 sne 03/13/19 Added Versal support.
+* </pre>
+*
+******************************************************************************/
+
+/***************************** Include Files *********************************/
+
+#include "xgpiops.h"
+
+/************************** Constant Definitions *****************************/
+/**************************** Type Definitions *******************************/
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/************************** Variable Definitions *****************************/
+
+
+/************************** Function Prototypes ******************************/
+
+extern void StubHandler(void *CallBackRef, u32 Bank, u32 Status);
+
+/*****************************************************************************/
+/*
+*
+* This function initializes a XGpioPs instance/driver.
+* All members of the XGpioPs instance structure are initialized and
+* StubHandlers are assigned to the Bank Status Handlers.
+*
+* @param InstancePtr is a pointer to the XGpioPs instance.
+* @param ConfigPtr points to the XGpioPs device configuration structure.
+* @param EffectiveAddr is the device base address in the virtual memory
+* address space. If the address translation is not used then the
+* physical address should be passed.
+* Unexpected errors may occur if the address mapping is changed
+* after this function is invoked.
+*
+* @return XST_SUCCESS always.
+*
+* @note None.
+*
+******************************************************************************/
+s32 XGpioPs_CfgInitialize(XGpioPs *InstancePtr, const XGpioPs_Config *ConfigPtr,
+ u32 EffectiveAddr)
+{
+ s32 Status = XST_SUCCESS;
+ u8 i;
+ Xil_AssertNonvoid(InstancePtr != NULL);
+ Xil_AssertNonvoid(ConfigPtr != NULL);
+ Xil_AssertNonvoid(EffectiveAddr != (u32)0);
+ /*
+ * Set some default values for instance data, don't indicate the device
+ * is ready to use until everything has been initialized successfully.
+ */
+ InstancePtr->IsReady = 0U;
+ InstancePtr->GpioConfig.BaseAddr = EffectiveAddr;
+ InstancePtr->GpioConfig.DeviceId = ConfigPtr->DeviceId;
+ InstancePtr->Handler = (XGpioPs_Handler)StubHandler;
+ InstancePtr->Platform = XGetPlatform_Info();
+
+ /* Initialize the Bank data based on platform */
+ if (InstancePtr->Platform == (u32)XPLAT_ZYNQ_ULTRA_MP) {
+ /*
+ * Max pins in the ZynqMP GPIO device
+ * 0 - 25, Bank 0
+ * 26 - 51, Bank 1
+ * 52 - 77, Bank 2
+ * 78 - 109, Bank 3
+ * 110 - 141, Bank 4
+ * 142 - 173, Bank 5
+ */
+ InstancePtr->MaxPinNum = (u32)174;
+ InstancePtr->MaxBanks = (u8)6;
+ }
+ else if (InstancePtr->Platform == (u32)XPLAT_VERSAL)
+ {
+ if(InstancePtr->PmcGpio == (u32)FALSE)
+ {
+ /* Max pins in the PS_GPIO devices
+ * 0 -25, Bank 0
+ * 26-57, Bank 3
+ */
+ InstancePtr->MaxPinNum = (u32)58;
+ InstancePtr->MaxBanks = (u8)4;
+ }
+ else
+ {
+ /* Max pins in the PMC_GPIO devices
+ * 0 - 25,Bank 0
+ * 26 - 51,Bank 1
+ * 52 - 83,Bank 3
+ * 84 - 115, Bank 4
+ */
+ InstancePtr->MaxPinNum = (u32)116;
+ InstancePtr->MaxBanks = (u8)5;
+ }
+ }
+ else {
+ /*
+ * Max pins in the GPIO device
+ * 0 - 31, Bank 0
+ * 32 - 53, Bank 1
+ * 54 - 85, Bank 2
+ * 86 - 117, Bank 3
+ */
+ InstancePtr->MaxPinNum = (u32)118;
+ InstancePtr->MaxBanks = (u8)4;
+ }
+
+ /*
+ * By default, interrupts are not masked in GPIO. Disable
+ * interrupts for all pins in all the 4 banks.
+ */
+ for (i=(u8)0U;i<InstancePtr->MaxBanks;i++) {
+ if (InstancePtr->Platform == XPLAT_VERSAL){
+ if(InstancePtr->PmcGpio == (u32)FALSE)
+ {
+ if((i== (u8)XGPIOPS_ONE)||(i== (u8)XGPIOPS_TWO))
+ {
+ continue;
+ }
+ XGpioPs_WriteReg(InstancePtr->GpioConfig.BaseAddr,
+ ((u32)(i) * XGPIOPS_REG_MASK_OFFSET) +
+ XGPIOPS_INTDIS_OFFSET, 0xFFFFFFFFU);
+ }
+ else
+ {
+ if(i==(u32)XGPIOPS_TWO)
+ {
+ continue;
+ }
+ XGpioPs_WriteReg(InstancePtr->GpioConfig.BaseAddr,
+ ((u32)(i) * XGPIOPS_REG_MASK_OFFSET) +
+ XGPIOPS_INTDIS_OFFSET, 0xFFFFFFFFU);
+
+ }
+ }
+ else
+ {
+ XGpioPs_WriteReg(InstancePtr->GpioConfig.BaseAddr,
+ ((u32)(i) * XGPIOPS_REG_MASK_OFFSET) +
+ XGPIOPS_INTDIS_OFFSET, 0xFFFFFFFFU);
+ }
+ }
+
+ /* Indicate the component is now ready to use. */
+ InstancePtr->IsReady = XIL_COMPONENT_IS_READY;
+
+ return Status;
+}
+
+/****************************************************************************/
+/**
+*
+* Read the Data register of the specified GPIO bank.
+*
+* @param InstancePtr is a pointer to the XGpioPs instance.
+* @param Bank is the bank number of the GPIO to operate on.
+* Valid values are 0-3 in Zynq and 0-5 in Zynq Ultrascale+ MP.
+*
+* @return Current value of the Data register.
+*
+* @note This function is used for reading the state of all the GPIO pins
+* of specified bank.
+*
+*****************************************************************************/
+u32 XGpioPs_Read(const XGpioPs *InstancePtr, u8 Bank)
+{
+ Xil_AssertNonvoid(InstancePtr != NULL);
+ Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+ Xil_AssertNonvoid(Bank < InstancePtr->MaxBanks);
+#ifdef versal
+ if(InstancePtr->PmcGpio == TRUE) {
+ Xil_AssertNonvoid(Bank != XGPIOPS_TWO);
+ } else {
+ Xil_AssertNonvoid((Bank !=XGPIOPS_ONE) && (Bank !=XGPIOPS_TWO));
+ }
+#endif
+
+ return XGpioPs_ReadReg(InstancePtr->GpioConfig.BaseAddr,
+ ((u32)(Bank) * XGPIOPS_DATA_BANK_OFFSET) +
+ XGPIOPS_DATA_RO_OFFSET);
+}
+
+/****************************************************************************/
+/**
+*
+* Read Data from the specified pin.
+*
+* @param InstancePtr is a pointer to the XGpioPs instance.
+* @param Pin is the pin number for which the data has to be read.
+* Valid values are 0-117 in Zynq and 0-173 in Zynq Ultrascale+ MP.
+* See xgpiops.h for the mapping of the pin numbers in the banks.
+*
+* @return Current value of the Pin (0 or 1).
+*
+* @note This function is used for reading the state of the specified
+* GPIO pin.
+*
+*****************************************************************************/
+u32 XGpioPs_ReadPin(const XGpioPs *InstancePtr, u32 Pin)
+{
+ u8 Bank;
+ u8 PinNumber;
+
+ Xil_AssertNonvoid(InstancePtr != NULL);
+ Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+ Xil_AssertNonvoid(Pin < InstancePtr->MaxPinNum);
+
+ /* Get the Bank number and Pin number within the bank. */
+#ifdef versal
+ XGpioPs_GetBankPin(InstancePtr,(u8)Pin, &Bank, &PinNumber);
+#else
+ XGpioPs_GetBankPin((u8)Pin, &Bank, &PinNumber);
+#endif
+ return (XGpioPs_ReadReg(InstancePtr->GpioConfig.BaseAddr,
+ ((u32)(Bank) * XGPIOPS_DATA_BANK_OFFSET) +
+ XGPIOPS_DATA_RO_OFFSET) >> (u32)PinNumber) & (u32)1;
+
+}
+
+/****************************************************************************/
+/**
+*
+* Write to the Data register of the specified GPIO bank.
+*
+* @param InstancePtr is a pointer to the XGpioPs instance.
+* @param Bank is the bank number of the GPIO to operate on.
+* Valid values are 0-3 in Zynq and 0-5 in Zynq Ultrascale+ MP.
+* @param Data is the value to be written to the Data register.
+*
+* @return None.
+*
+* @note This function is used for writing to all the GPIO pins of
+* the bank. The previous state of the pins is not maintained.
+*
+*****************************************************************************/
+void XGpioPs_Write(const XGpioPs *InstancePtr, u8 Bank, u32 Data)
+{
+ Xil_AssertVoid(InstancePtr != NULL);
+ Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+ Xil_AssertVoid(Bank < InstancePtr->MaxBanks);
+#ifdef versal
+ if(InstancePtr->PmcGpio == TRUE) {
+ Xil_AssertVoid(Bank != XGPIOPS_TWO);
+ } else {
+ Xil_AssertVoid((Bank !=XGPIOPS_ONE) && (Bank !=XGPIOPS_TWO));
+ }
+#endif
+
+ XGpioPs_WriteReg(InstancePtr->GpioConfig.BaseAddr,
+ ((u32)(Bank) * XGPIOPS_DATA_BANK_OFFSET) +
+ XGPIOPS_DATA_OFFSET, Data);
+}
+
+/****************************************************************************/
+/**
+*
+* Write data to the specified pin.
+*
+* @param InstancePtr is a pointer to the XGpioPs instance.
+* @param Pin is the pin number to which the Data is to be written.
+* Valid values are 0-117 in Zynq and 0-173 in Zynq Ultrascale+ MP.
+* @param Data is the data to be written to the specified pin (0 or 1).
+*
+* @return None.
+*
+* @note This function does a masked write to the specified pin of
+* the specified GPIO bank. The previous state of other pins
+* is maintained.
+*
+*****************************************************************************/
+void XGpioPs_WritePin(const XGpioPs *InstancePtr, u32 Pin, u32 Data)
+{
+ u32 RegOffset;
+ u32 Value;
+ u8 Bank;
+ u8 PinNumber;
+ u32 DataVar = Data;
+
+ Xil_AssertVoid(InstancePtr != NULL);
+ Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+ Xil_AssertVoid(Pin < InstancePtr->MaxPinNum);
+
+ /* Get the Bank number and Pin number within the bank. */
+#ifdef versal
+ XGpioPs_GetBankPin(InstancePtr,(u8)Pin, &Bank, &PinNumber);
+#else
+ XGpioPs_GetBankPin((u8)Pin, &Bank, &PinNumber);
+#endif
+
+ if (PinNumber > 15U) {
+ /* There are only 16 data bits in bit maskable register. */
+ PinNumber -= (u8)16;
+ RegOffset = XGPIOPS_DATA_MSW_OFFSET;
+ } else {
+ RegOffset = XGPIOPS_DATA_LSW_OFFSET;
+ }
+
+ /*
+ * Get the 32 bit value to be written to the Mask/Data register where
+ * the upper 16 bits is the mask and lower 16 bits is the data.
+ */
+ DataVar &= (u32)0x01;
+ Value = ~((u32)1 << (PinNumber + 16U)) & ((DataVar << PinNumber) | 0xFFFF0000U);
+ XGpioPs_WriteReg(InstancePtr->GpioConfig.BaseAddr,
+ ((u32)(Bank) * XGPIOPS_DATA_MASK_OFFSET) +
+ RegOffset, Value);
+
+}
+
+
+
+/****************************************************************************/
+/**
+*
+* Set the Direction of the pins of the specified GPIO Bank.
+*
+* @param InstancePtr is a pointer to the XGpioPs instance.
+* @param Bank is the bank number of the GPIO to operate on.
+* Valid values are 0-3 in Zynq and 0-5 in Zynq Ultrascale+ MP.
+* @param Direction is the 32 bit mask of the Pin direction to be set for
+* all the pins in the Bank. Bits with 0 are set to Input mode,
+* bits with 1 are set to Output Mode.
+*
+* @return None.
+*
+* @note This function is used for setting the direction of all the pins
+* in the specified bank. The previous state of the pins is
+* not maintained.
+*
+*****************************************************************************/
+void XGpioPs_SetDirection(const XGpioPs *InstancePtr, u8 Bank, u32 Direction)
+{
+ Xil_AssertVoid(InstancePtr != NULL);
+ Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+ Xil_AssertVoid(Bank < InstancePtr->MaxBanks);
+#ifdef versal
+ if(InstancePtr->PmcGpio == TRUE) {
+ Xil_AssertVoid(Bank != XGPIOPS_TWO);
+ } else {
+ Xil_AssertVoid((Bank !=XGPIOPS_ONE) && (Bank !=XGPIOPS_TWO));
+ }
+#endif
+
+ XGpioPs_WriteReg(InstancePtr->GpioConfig.BaseAddr,
+ ((u32)(Bank) * XGPIOPS_REG_MASK_OFFSET) +
+ XGPIOPS_DIRM_OFFSET, Direction);
+}
+
+/****************************************************************************/
+/**
+*
+* Set the Direction of the specified pin.
+*
+* @param InstancePtr is a pointer to the XGpioPs instance.
+* @param Pin is the pin number to which the Data is to be written.
+* Valid values are 0-117 in Zynq and 0-173 in Zynq Ultrascale+ MP.
+* @param Direction is the direction to be set for the specified pin.
+* Valid values are 0 for Input Direction, 1 for Output Direction.
+*
+* @return None.
+*
+*****************************************************************************/
+void XGpioPs_SetDirectionPin(const XGpioPs *InstancePtr, u32 Pin, u32 Direction)
+{
+ u8 Bank;
+ u8 PinNumber;
+ u32 DirModeReg;
+
+ Xil_AssertVoid(InstancePtr != NULL);
+ Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+ Xil_AssertVoid(Pin < InstancePtr->MaxPinNum);
+ Xil_AssertVoid(Direction <= (u32)1);
+
+ /* Get the Bank number and Pin number within the bank. */
+#ifdef versal
+ XGpioPs_GetBankPin(InstancePtr,(u8)Pin, &Bank, &PinNumber);
+#else
+ XGpioPs_GetBankPin((u8)Pin, &Bank, &PinNumber);
+#endif
+ DirModeReg = XGpioPs_ReadReg(InstancePtr->GpioConfig.BaseAddr,
+ ((u32)(Bank) * XGPIOPS_REG_MASK_OFFSET) +
+ XGPIOPS_DIRM_OFFSET);
+
+ if (Direction!=(u32)0) { /* Output Direction */
+ DirModeReg |= ((u32)1 << (u32)PinNumber);
+ } else { /* Input Direction */
+ DirModeReg &= ~ ((u32)1 << (u32)PinNumber);
+ }
+
+ XGpioPs_WriteReg(InstancePtr->GpioConfig.BaseAddr,
+ ((u32)(Bank) * XGPIOPS_REG_MASK_OFFSET) +
+ XGPIOPS_DIRM_OFFSET, DirModeReg);
+}
+
+/****************************************************************************/
+/**
+*
+* Get the Direction of the pins of the specified GPIO Bank.
+*
+* @param InstancePtr is a pointer to the XGpioPs instance.
+* @param Bank is the bank number of the GPIO to operate on.
+* Valid values are 0-3 in Zynq and 0-5 in Zynq Ultrascale+ MP.
+*
+* @return Returns a 32 bit mask of the Direction register. Bits with 0 are
+* in Input mode, bits with 1 are in Output Mode.
+*
+* @note None.
+*
+*****************************************************************************/
+u32 XGpioPs_GetDirection(const XGpioPs *InstancePtr, u8 Bank)
+{
+ Xil_AssertNonvoid(InstancePtr != NULL);
+ Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+ Xil_AssertNonvoid(Bank < InstancePtr->MaxBanks);
+#ifdef versal
+ if(InstancePtr->PmcGpio == TRUE) {
+ Xil_AssertNonvoid(Bank != XGPIOPS_TWO);
+ } else {
+ Xil_AssertNonvoid((Bank !=XGPIOPS_ONE) && (Bank !=XGPIOPS_TWO));
+ }
+#endif
+
+ return XGpioPs_ReadReg(InstancePtr->GpioConfig.BaseAddr,
+ ((u32)(Bank) * XGPIOPS_REG_MASK_OFFSET) +
+ XGPIOPS_DIRM_OFFSET);
+}
+
+/****************************************************************************/
+/**
+*
+* Get the Direction of the specified pin.
+*
+* @param InstancePtr is a pointer to the XGpioPs instance.
+* @param Pin is the pin number for which the Direction is to be
+* retrieved.
+* Valid values are 0-117 in Zynq and 0-173 in Zynq Ultrascale+ MP.
+*
+* @return Direction of the specified pin.
+* - 0 for Input Direction
+* - 1 for Output Direction
+*
+* @note None.
+*
+*****************************************************************************/
+u32 XGpioPs_GetDirectionPin(const XGpioPs *InstancePtr, u32 Pin)
+{
+ u8 Bank;
+ u8 PinNumber;
+
+ Xil_AssertNonvoid(InstancePtr != NULL);
+ Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+ Xil_AssertNonvoid(Pin < InstancePtr->MaxPinNum);
+
+ /* Get the Bank number and Pin number within the bank. */
+#ifdef versal
+ XGpioPs_GetBankPin(InstancePtr,(u8)Pin, &Bank, &PinNumber);
+#else
+ XGpioPs_GetBankPin((u8)Pin, &Bank, &PinNumber);
+#endif
+
+ return (XGpioPs_ReadReg(InstancePtr->GpioConfig.BaseAddr,
+ ((u32)(Bank) * XGPIOPS_REG_MASK_OFFSET) +
+ XGPIOPS_DIRM_OFFSET) >> (u32)PinNumber) & (u32)1;
+}
+
+/****************************************************************************/
+/**
+*
+* Set the Output Enable of the pins of the specified GPIO Bank.
+*
+* @param InstancePtr is a pointer to the XGpioPs instance.
+* @param Bank is the bank number of the GPIO to operate on.
+* Valid values are 0-3 in Zynq and 0-5 in Zynq Ultrascale+ MP.
+* @param OpEnable is the 32 bit mask of the Output Enables to be set for
+* all the pins in the Bank. The Output Enable of bits with 0 are
+* disabled, the Output Enable of bits with 1 are enabled.
+*
+* @return None.
+*
+* @note This function is used for setting the Output Enables of all the
+* pins in the specified bank. The previous state of the Output
+* Enables is not maintained.
+*
+*****************************************************************************/
+void XGpioPs_SetOutputEnable(const XGpioPs *InstancePtr, u8 Bank, u32 OpEnable)
+{
+ Xil_AssertVoid(InstancePtr != NULL);
+ Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+ Xil_AssertVoid(Bank < InstancePtr->MaxBanks);
+#ifdef versal
+ if(InstancePtr->PmcGpio == TRUE) {
+ Xil_AssertVoid(Bank != XGPIOPS_TWO);
+ } else {
+ Xil_AssertVoid((Bank !=XGPIOPS_ONE) && (Bank !=XGPIOPS_TWO));
+ }
+#endif
+
+ XGpioPs_WriteReg(InstancePtr->GpioConfig.BaseAddr,
+ ((u32)(Bank) * XGPIOPS_REG_MASK_OFFSET) +
+ XGPIOPS_OUTEN_OFFSET, OpEnable);
+}
+
+/****************************************************************************/
+/**
+*
+* Set the Output Enable of the specified pin.
+*
+* @param InstancePtr is a pointer to the XGpioPs instance.
+* @param Pin is the pin number to which the Data is to be written.
+* Valid values are 0-117 in Zynq and 0-173 in Zynq Ultrascale+ MP.
+* @param OpEnable specifies whether the Output Enable for the specified
+* pin should be enabled.
+* Valid values are 0 for Disabling Output Enable,
+* 1 for Enabling Output Enable.
+*
+* @return None.
+*
+* @note None.
+*
+*****************************************************************************/
+void XGpioPs_SetOutputEnablePin(const XGpioPs *InstancePtr, u32 Pin, u32 OpEnable)
+{
+ u8 Bank;
+ u8 PinNumber;
+ u32 OpEnableReg;
+
+ Xil_AssertVoid(InstancePtr != NULL);
+ Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+ Xil_AssertVoid(Pin < InstancePtr->MaxPinNum);
+ Xil_AssertVoid(OpEnable <= (u32)1);
+
+ /* Get the Bank number and Pin number within the bank. */
+#ifdef versal
+ XGpioPs_GetBankPin(InstancePtr,(u8)Pin, &Bank, &PinNumber);
+#else
+ XGpioPs_GetBankPin((u8)Pin, &Bank, &PinNumber);
+#endif
+
+ OpEnableReg = XGpioPs_ReadReg(InstancePtr->GpioConfig.BaseAddr,
+ ((u32)(Bank) * XGPIOPS_REG_MASK_OFFSET) +
+ XGPIOPS_OUTEN_OFFSET);
+
+ if (OpEnable != (u32)0) { /* Enable Output Enable */
+ OpEnableReg |= ((u32)1 << (u32)PinNumber);
+ } else { /* Disable Output Enable */
+ OpEnableReg &= ~ ((u32)1 << (u32)PinNumber);
+ }
+
+ XGpioPs_WriteReg(InstancePtr->GpioConfig.BaseAddr,
+ ((u32)(Bank) * XGPIOPS_REG_MASK_OFFSET) +
+ XGPIOPS_OUTEN_OFFSET, OpEnableReg);
+}
+/****************************************************************************/
+/**
+*
+* Get the Output Enable status of the pins of the specified GPIO Bank.
+*
+* @param InstancePtr is a pointer to the XGpioPs instance.
+* @param Bank is the bank number of the GPIO to operate on.
+* Valid values are 0-3 in Zynq and 0-5 in Zynq Ultrascale+ MP.
+*
+* @return Returns a a 32 bit mask of the Output Enable register.
+* Bits with 0 are in Disabled state, bits with 1 are in
+* Enabled State.
+*
+* @note None.
+*
+*****************************************************************************/
+u32 XGpioPs_GetOutputEnable(const XGpioPs *InstancePtr, u8 Bank)
+{
+ Xil_AssertNonvoid(InstancePtr != NULL);
+ Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+ Xil_AssertNonvoid(Bank < InstancePtr->MaxBanks);
+#ifdef versal
+ if(InstancePtr->PmcGpio == TRUE) {
+ Xil_AssertNonvoid(Bank != XGPIOPS_TWO);
+ } else {
+ Xil_AssertNonvoid((Bank !=XGPIOPS_ONE) && (Bank !=XGPIOPS_TWO));
+ }
+#endif
+
+ return XGpioPs_ReadReg(InstancePtr->GpioConfig.BaseAddr,
+ ((u32)(Bank) * XGPIOPS_REG_MASK_OFFSET) +
+ XGPIOPS_OUTEN_OFFSET);
+}
+
+/****************************************************************************/
+/**
+*
+* Get the Output Enable status of the specified pin.
+*
+* @param InstancePtr is a pointer to the XGpioPs instance.
+* @param Pin is the pin number for which the Output Enable status is to
+* be retrieved.
+* Valid values are 0-117 in Zynq and 0-173 in Zynq Ultrascale+ MP.
+*
+* @return Output Enable of the specified pin.
+* - 0 if Output Enable is disabled for this pin
+* - 1 if Output Enable is enabled for this pin
+*
+* @note None.
+*
+*****************************************************************************/
+u32 XGpioPs_GetOutputEnablePin(const XGpioPs *InstancePtr, u32 Pin)
+{
+ u8 Bank;
+ u8 PinNumber;
+
+ Xil_AssertNonvoid(InstancePtr != NULL);
+ Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+ Xil_AssertNonvoid(Pin < InstancePtr->MaxPinNum);
+
+ /* Get the Bank number and Pin number within the bank. */
+#ifdef versal
+ XGpioPs_GetBankPin(InstancePtr,(u8)Pin, &Bank, &PinNumber);
+#else
+ XGpioPs_GetBankPin((u8)Pin, &Bank, &PinNumber);
+#endif
+
+ return (XGpioPs_ReadReg(InstancePtr->GpioConfig.BaseAddr,
+ ((u32)(Bank) * XGPIOPS_REG_MASK_OFFSET) +
+ XGPIOPS_OUTEN_OFFSET) >> (u32)PinNumber) & (u32)1;
+}
+
+/****************************************************************************/
+/*
+*
+* Get the Bank number and the Pin number in the Bank, for the given PinNumber
+* in the GPIO device.
+*
+* @param PinNumber is the Pin number in the GPIO device.
+* @param BankNumber returns the Bank in which this GPIO pin is present.
+* Valid values are 0 to XGPIOPS_MAX_BANKS - 1.
+* @param PinNumberInBank returns the Pin Number within the Bank.
+*
+* @return None.
+*
+* @note None.
+*
+*****************************************************************************/
+#ifdef versal
+void XGpioPs_GetBankPin(const XGpioPs *InstancePtr,u8 PinNumber, u8 *BankNumber, u8 *PinNumberInBank)
+#else
+void XGpioPs_GetBankPin(u8 PinNumber, u8 *BankNumber, u8 *PinNumberInBank)
+#endif
+{
+ u32 XGpioPsPinTable[6] = {0};
+#ifdef versal
+ u8 i=(u8)0;
+#endif
+ u32 Platform = XGetPlatform_Info();
+
+ if (Platform == (u32)XPLAT_ZYNQ_ULTRA_MP) {
+ /*
+ * This structure defines the mapping of the pin numbers to the banks when
+ * the driver APIs are used for working on the individual pins.
+ */
+
+ XGpioPsPinTable[0] = (u32)25; /* 0 - 25, Bank 0 */
+ XGpioPsPinTable[1] = (u32)51; /* 26 - 51, Bank 1 */
+ XGpioPsPinTable[2] = (u32)77; /* 52 - 77, Bank 2 */
+ XGpioPsPinTable[3] = (u32)109; /* 78 - 109, Bank 3 */
+ XGpioPsPinTable[4] = (u32)141; /* 110 - 141, Bank 4 */
+ XGpioPsPinTable[5] = (u32)173; /* 142 - 173 Bank 5 */
+
+ *BankNumber = 0U;
+ while (*BankNumber < XGPIOPS_SIX) {
+ if (PinNumber <= XGpioPsPinTable[*BankNumber]) {
+ break;
+ }
+ (*BankNumber)++;
+ }
+ }
+#ifdef versal
+ else if(Platform == XPLAT_VERSAL)
+ {
+ if(InstancePtr->PmcGpio == (u32)(FALSE))
+ {
+ XGpioPsPinTable[0] = (u32)25; /* 0 - 25, Bank 0 */
+ XGpioPsPinTable[1] = (u32)57; /* 26 - 57, Bank 3 */
+ *BankNumber =0U;
+ if(PinNumber <= XGpioPsPinTable[*BankNumber])
+ {
+ *BankNumber = (u8)XGPIOPS_ZERO;
+ }
+ else
+ {
+ *BankNumber = (u8)XGPIOPS_THREE;
+ }
+
+ }
+ else
+ {
+ XGpioPsPinTable[0] = (u32)25; /* 0 - 25, Bank 0 */
+ XGpioPsPinTable[1] = (u32)51; /* 26 - 51, Bank 1 */
+ XGpioPsPinTable[2] = (u32)83; /* 52 - 83, Bank 3 */
+ XGpioPsPinTable[3] = (u32)115; /*84 - 115, Bank 4 */
+
+ *BankNumber =0U;
+ while(i < XGPIOPS_FOUR)
+ {
+ if(i <= (u8)XGPIOPS_ONE)
+ {
+ if (PinNumber <= XGpioPsPinTable[i])
+ {
+ *BankNumber = (u8)i;
+ break;
+ }
+ i++;
+ }
+ else
+ {
+ if (PinNumber <= XGpioPsPinTable[i])
+ {
+ *BankNumber = (u8)i+1U;
+ break;
+ }
+ i++;
+ }
+
+ }
+ }
+
+ }
+#endif
+ else {
+ XGpioPsPinTable[0] = (u32)31; /* 0 - 31, Bank 0 */
+ XGpioPsPinTable[1] = (u32)53; /* 32 - 53, Bank 1 */
+ XGpioPsPinTable[2] = (u32)85; /* 54 - 85, Bank 2 */
+ XGpioPsPinTable[3] = (u32)117; /* 86 - 117 Bank 3 */
+
+ *BankNumber = 0U;
+ while (*BankNumber < XGPIOPS_FOUR) {
+ if (PinNumber <= XGpioPsPinTable[*BankNumber]) {
+ break;
+ }
+ (*BankNumber)++;
+ }
+ }
+ if (*BankNumber == (u8)0) {
+ *PinNumberInBank = PinNumber;
+ }
+
+#ifdef versal
+ else if(Platform == XPLAT_VERSAL)
+ {
+ if(InstancePtr->PmcGpio == (u32)(FALSE))
+ {
+ *PinNumberInBank = (u8)((u32)PinNumber - (XGpioPsPinTable[0] + (u32)1));
+ }
+ else {
+ if((*BankNumber ==(u8)XGPIOPS_THREE) || (*BankNumber ==(u8)XGPIOPS_FOUR))
+ {
+ *PinNumberInBank = (u8)((u32)PinNumber %
+ (XGpioPsPinTable[*BankNumber - (u8)XGPIOPS_TWO] + (u32)1));
+ }
+ else
+ {
+ *PinNumberInBank = (u8)((u32)PinNumber %
+ (XGpioPsPinTable[*BankNumber - (u8)1] + (u32)1));
+ }
+ }
+
+ }
+#endif
+
+ else {
+ *PinNumberInBank = (u8)((u32)PinNumber %
+ (XGpioPsPinTable[*BankNumber - (u8)1] + (u32)1));
+ }
+}
+/** @} */
diff --git a/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/gpiops_v3_6/src/xgpiops.h b/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/gpiops_v3_6/src/xgpiops.h
new file mode 100644
index 0000000..c0bdd6c
--- /dev/null
+++ b/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/gpiops_v3_6/src/xgpiops.h
@@ -0,0 +1,286 @@
+/******************************************************************************
+*
+* Copyright (C) 2010 - 2019 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+* THE SOFTWARE.
+*
+*
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xgpiops.h
+* @addtogroup gpiops_v3_6
+* @{
+* @details
+*
+* The Xilinx PS GPIO driver. This driver supports the Xilinx PS GPIO
+* Controller.
+*
+* The GPIO Controller supports the following features:
+* - 4 banks
+* - Masked writes (There are no masked reads)
+* - Bypass mode
+* - Configurable Interrupts (Level/Edge)
+*
+* This driver is intended to be RTOS and processor independent. Any needs for
+* dynamic memory management, threads or thread mutual exclusion, virtual
+* memory, or cache control must be satisfied by the layer above this driver.
+
+* This driver supports all the features listed above, if applicable.
+*
+* <b>Driver Description</b>
+*
+* The device driver enables higher layer software (e.g., an application) to
+* communicate to the GPIO.
+*
+* <b>Interrupts</b>
+*
+* The driver provides interrupt management functions and an interrupt handler.
+* Users of this driver need to provide callback functions. An interrupt handler
+* example is available with the driver.
+*
+* <b>Threads</b>
+*
+* This driver is not thread safe. Any needs for threads or thread mutual
+* exclusion must be satisfied by the layer above this driver.
+*
+* <b>Asserts</b>
+*
+* Asserts are used within all Xilinx drivers to enforce constraints on argument
+* values. Asserts can be turned off on a system-wide basis by defining, at
+* compile time, the NDEBUG identifier. By default, asserts are turned on and it
+* is recommended that users leave asserts on during development.
+*
+* <b>Building the driver</b>
+*
+* The XGpioPs driver is composed of several source files. This allows the user
+* to build and link only those parts of the driver that are necessary.
+* <br><br>
+*
+* <pre>
+* MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ----- ---- -------- -----------------------------------------------
+* 1.00a sv 01/15/10 First Release
+* 1.01a sv 04/15/12 Removed the APIs XGpioPs_SetMode, XGpioPs_SetModePin
+* XGpioPs_GetMode, XGpioPs_GetModePin as they are not
+* relevant to Zynq device.The interrupts are disabled
+* for output pins on all banks during initialization.
+* 1.02a hk 08/22/13 Added low level reset API
+* 2.1 hk 04/29/14 Use Input data register DATA_RO for read. CR# 771667.
+* 2.2 sk 10/13/14 Used Pin number in Bank instead of pin number
+* passed to APIs. CR# 822636
+* 3.00 kvn 02/13/15 Modified code for MISRA-C:2012 compliance.
+* 3.1 kvn 04/13/15 Add support for Zynq Ultrascale+ MP. CR# 856980.
+* ms 03/17/17 Added readme.txt file in examples folder for doxygen
+* generation.
+* ms 04/05/17 Added tabspace for return statements in functions of
+* gpiops examples for proper documentation while
+* generating doxygen.
+* 3.3 ms 04/17/17 Added notes about gpio input and output pin description
+* for zcu102 and zc702 boards in polled and interrupt
+* example, configured Interrupt pin to input pin for
+* proper functioning of interrupt example.
+* 3.4 aru 08/17/18 Resolved MISRA-C mandatory violations. CR# 1007751
+* 3.5 sne 03/01/19 Fixes violations according to MISRAC-2012
+* in safety mode and modified the code such as
+* Use of mixed mode arithmetic,Declared the pointer param
+* as Pointer to const,Casting operation to a pointer,
+* Literal value requires a U suffix.
+* 3.5 sne 03/14/19 Added Versal support.
+* 3.6 mus 04/05/19 Replaced XPLAT_versal macro with XPLAT_VERSAL, to be in
+* sync with standalone BSP
+* 3.6 sne 06/12/19 Fixed IAR compiler warning.
+* 3.6 sne 08/14/19 Added interrupt handler support on versal.
+*
+* </pre>
+*
+******************************************************************************/
+#ifndef XGPIOPS_H /* prevent circular inclusions */
+#define XGPIOPS_H /* by using protection macros */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/***************************** Include Files *********************************/
+
+#include "xstatus.h"
+#include "xgpiops_hw.h"
+#include "xplatform_info.h"
+
+/************************** Constant Definitions *****************************/
+
+/** @name Interrupt types
+ * @{
+ * The following constants define the interrupt types that can be set for each
+ * GPIO pin.
+ */
+#define XGPIOPS_IRQ_TYPE_EDGE_RISING 0x00U /**< Interrupt on Rising edge */
+#define XGPIOPS_IRQ_TYPE_EDGE_FALLING 0x01U /**< Interrupt Falling edge */
+#define XGPIOPS_IRQ_TYPE_EDGE_BOTH 0x02U /**< Interrupt on both edges */
+#define XGPIOPS_IRQ_TYPE_LEVEL_HIGH 0x03U /**< Interrupt on high level */
+#define XGPIOPS_IRQ_TYPE_LEVEL_LOW 0x04U /**< Interrupt on low level */
+/*@}*/
+
+#define XGPIOPS_BANK_MAX_PINS (u32)32 /**< Max pins in a GPIO bank */
+#define XGPIOPS_BANK0 0x00U /**< GPIO Bank 0 */
+#define XGPIOPS_BANK1 0x01U /**< GPIO Bank 1 */
+#define XGPIOPS_BANK2 0x02U /**< GPIO Bank 2 */
+#define XGPIOPS_BANK3 0x03U /**< GPIO Bank 3 */
+
+#ifdef XPAR_PSU_GPIO_0_BASEADDR
+#define XGPIOPS_BANK4 0x04U /**< GPIO Bank 4 */
+#define XGPIOPS_BANK5 0x05U /**< GPIO Bank 5 */
+#endif
+
+#define XGPIOPS_MAX_BANKS_ZYNQMP 0x06U /**< Max banks in a
+ * Zynq Ultrascale+ MP GPIO device
+ */
+#define XGPIOPS_MAX_BANKS 0x04U /**< Max banks in a Zynq GPIO device */
+
+#define XGPIOPS_DEVICE_MAX_PIN_NUM_ZYNQMP (u32)174 /**< Max pins in the
+ * Zynq Ultrascale+ MP GPIO device
+ * 0 - 25, Bank 0
+ * 26 - 51, Bank 1
+ * 52 - 77, Bank 2
+ * 78 - 109, Bank 3
+ * 110 - 141, Bank 4
+ * 142 - 173, Bank 5
+ */
+#define XGPIOPS_DEVICE_MAX_PIN_NUM (u32)118 /**< Max pins in the Zynq GPIO device
+ * 0 - 31, Bank 0
+ * 32 - 53, Bank 1
+ * 54 - 85, Bank 2
+ * 86 - 117, Bank 3
+ */
+
+/**************************** Type Definitions *******************************/
+
+/****************************************************************************/
+/**
+ * This handler data type allows the user to define a callback function to
+ * handle the interrupts for the GPIO device. The application using this
+ * driver is expected to define a handler of this type, to support interrupt
+ * driven mode. The handler executes in an interrupt context such that minimal
+ * processing should be performed.
+ *
+ * @param CallBackRef is a callback reference passed in by the upper layer
+ * when setting the callback functions for a GPIO bank. It is
+ * passed back to the upper layer when the callback is invoked. Its
+ * type is not important to the driver component, so it is a void
+ * pointer.
+ * @param Bank is the bank for which the interrupt status has changed.
+ * @param Status is the Interrupt status of the GPIO bank.
+ *
+ *****************************************************************************/
+typedef void (*XGpioPs_Handler) (void *CallBackRef, u32 Bank, u32 Status);
+
+/**
+ * This typedef contains configuration information for a device.
+ */
+typedef struct {
+ u16 DeviceId; /**< Unique ID of device */
+ u32 BaseAddr; /**< Register base address */
+} XGpioPs_Config;
+
+/**
+ * The XGpioPs driver instance data. The user is required to allocate a
+ * variable of this type for the GPIO device in the system. A pointer
+ * to a variable of this type is then passed to the driver API functions.
+ */
+typedef struct {
+ XGpioPs_Config GpioConfig; /**< Device configuration */
+ u32 IsReady; /**< Device is initialized and ready */
+ XGpioPs_Handler Handler; /**< Status handlers for all banks */
+ void *CallBackRef; /**< Callback ref for bank handlers */
+ u32 Platform; /**< Platform data */
+ u32 MaxPinNum; /**< Max pins in the GPIO device */
+ u8 MaxBanks; /**< Max banks in a GPIO device */
+ u32 PmcGpio; /**< Flag for accessing PS GPIO for versal*/
+} XGpioPs;
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/************************** Function Prototypes ******************************/
+
+/* Functions in xgpiops.c */
+s32 XGpioPs_CfgInitialize(XGpioPs *InstancePtr, const XGpioPs_Config *ConfigPtr,
+ u32 EffectiveAddr);
+
+/* Bank APIs in xgpiops.c */
+u32 XGpioPs_Read(const XGpioPs *InstancePtr, u8 Bank);
+void XGpioPs_Write(const XGpioPs *InstancePtr, u8 Bank, u32 Data);
+void XGpioPs_SetDirection(const XGpioPs *InstancePtr, u8 Bank, u32 Direction);
+u32 XGpioPs_GetDirection(const XGpioPs *InstancePtr, u8 Bank);
+void XGpioPs_SetOutputEnable(const XGpioPs *InstancePtr, u8 Bank, u32 OpEnable);
+u32 XGpioPs_GetOutputEnable(const XGpioPs *InstancePtr, u8 Bank);
+#ifdef versal
+void XGpioPs_GetBankPin(const XGpioPs *InstancePtr,u8 PinNumber,u8 *BankNumber, u8 *PinNumberInBank);
+#else
+void XGpioPs_GetBankPin(u8 PinNumber,u8 *BankNumber, u8 *PinNumberInBank);
+#endif
+
+/* Pin APIs in xgpiops.c */
+u32 XGpioPs_ReadPin(const XGpioPs *InstancePtr, u32 Pin);
+void XGpioPs_WritePin(const XGpioPs *InstancePtr, u32 Pin, u32 Data);
+void XGpioPs_SetDirectionPin(const XGpioPs *InstancePtr, u32 Pin, u32 Direction);
+u32 XGpioPs_GetDirectionPin(const XGpioPs *InstancePtr, u32 Pin);
+void XGpioPs_SetOutputEnablePin(const XGpioPs *InstancePtr, u32 Pin, u32 OpEnable);
+u32 XGpioPs_GetOutputEnablePin(const XGpioPs *InstancePtr, u32 Pin);
+
+/* Diagnostic functions in xgpiops_selftest.c */
+s32 XGpioPs_SelfTest(const XGpioPs *InstancePtr);
+
+/* Functions in xgpiops_intr.c */
+/* Bank APIs in xgpiops_intr.c */
+void XGpioPs_IntrEnable(const XGpioPs *InstancePtr, u8 Bank, u32 Mask);
+void XGpioPs_IntrDisable(const XGpioPs *InstancePtr, u8 Bank, u32 Mask);
+u32 XGpioPs_IntrGetEnabled(const XGpioPs *InstancePtr, u8 Bank);
+u32 XGpioPs_IntrGetStatus(const XGpioPs *InstancePtr, u8 Bank);
+void XGpioPs_IntrClear(const XGpioPs *InstancePtr, u8 Bank, u32 Mask);
+void XGpioPs_SetIntrType(const XGpioPs *InstancePtr, u8 Bank, u32 IntrType,
+ u32 IntrPolarity, u32 IntrOnAny);
+void XGpioPs_GetIntrType(const XGpioPs *InstancePtr, u8 Bank, u32 *IntrType,
+ u32 *IntrPolarity, u32 *IntrOnAny);
+void XGpioPs_SetCallbackHandler(XGpioPs *InstancePtr, void *CallBackRef,
+ XGpioPs_Handler FuncPointer);
+void XGpioPs_IntrHandler(const XGpioPs *InstancePtr);
+
+/* Pin APIs in xgpiops_intr.c */
+void XGpioPs_SetIntrTypePin(const XGpioPs *InstancePtr, u32 Pin, u8 IrqType);
+u8 XGpioPs_GetIntrTypePin(const XGpioPs *InstancePtr, u32 Pin);
+
+void XGpioPs_IntrEnablePin(const XGpioPs *InstancePtr, u32 Pin);
+void XGpioPs_IntrDisablePin(const XGpioPs *InstancePtr, u32 Pin);
+u32 XGpioPs_IntrGetEnabledPin(const XGpioPs *InstancePtr, u32 Pin);
+u32 XGpioPs_IntrGetStatusPin(const XGpioPs *InstancePtr, u32 Pin);
+void XGpioPs_IntrClearPin(const XGpioPs *InstancePtr, u32 Pin);
+
+/* Functions in xgpiops_sinit.c */
+XGpioPs_Config *XGpioPs_LookupConfig(u16 DeviceId);
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* end of protection macro */
+/** @} */
diff --git a/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/gpiops_v3_6/src/xgpiops_g.c b/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/gpiops_v3_6/src/xgpiops_g.c
new file mode 100644
index 0000000..09fdf56
--- /dev/null
+++ b/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/gpiops_v3_6/src/xgpiops_g.c
@@ -0,0 +1,47 @@
+
+/*******************************************************************
+*
+* CAUTION: This file is automatically generated by HSI.
+* Version: 2019.2
+* DO NOT EDIT.
+*
+* Copyright (C) 2010-2021 Xilinx, Inc. All Rights Reserved.*
+*Permission is hereby granted, free of charge, to any person obtaining a copy
+*of this software and associated documentation files (the Software), to deal
+*in the Software without restriction, including without limitation the rights
+*to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+*copies of the Software, and to permit persons to whom the Software is
+*furnished to do so, subject to the following conditions:
+*
+*The above copyright notice and this permission notice shall be included in
+*all copies or substantial portions of the Software.
+*
+*THE SOFTWARE IS PROVIDED AS IS, WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+*IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+*FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+*THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+*WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT
+*OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+*
+
+*
+* Description: Driver configuration
+*
+*******************************************************************/
+
+#include "xparameters.h"
+#include "xgpiops.h"
+
+/*
+* The configuration table for devices
+*/
+
+XGpioPs_Config XGpioPs_ConfigTable[XPAR_XGPIOPS_NUM_INSTANCES] =
+{
+ {
+ XPAR_PS7_GPIO_0_DEVICE_ID,
+ XPAR_PS7_GPIO_0_BASEADDR
+ }
+};
+
+
diff --git a/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/gpiops_v3_6/src/xgpiops_hw.c b/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/gpiops_v3_6/src/xgpiops_hw.c
new file mode 100644
index 0000000..310c17d
--- /dev/null
+++ b/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/gpiops_v3_6/src/xgpiops_hw.c
@@ -0,0 +1,260 @@
+/******************************************************************************
+*
+* Copyright (C) 2013 - 2019 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+* THE SOFTWARE.
+*
+*
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xgpiops_hw.c
+* @addtogroup gpiops_v3_6
+* @{
+*
+* This file contains low level GPIO functions.
+*
+* <pre>
+* MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ----- ---- -------- -----------------------------------------------
+* 1.02a hk 08/22/13 First Release
+* 3.00 kvn 02/13/15 Modified code for MISRA-C:2012 compliance.
+* 3.1 kvn 04/13/15 Add support for Zynq Ultrascale+ MP. CR# 856980.
+* 3.5 sne 03/01/19 Fixes violations according to MISRAC-2012
+* in safety mode and modified the code such as
+* Use of mixed mode arithmetic,Declared the pointer param
+* as Pointer to const,Casting operation to a pointer,
+* Literal value requires a U suffix.
+* 3.5 sne 03/14/19 Added versal support.
+* </pre>
+*
+******************************************************************************/
+
+/***************************** Include Files *********************************/
+
+#include "xgpiops_hw.h"
+#include "xgpiops.h"
+
+/************************** Constant Definitions *****************************/
+
+/**************************** Type Definitions *******************************/
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/************************** Variable Definitions *****************************/
+
+/************************** Function Prototypes ******************************/
+
+
+/*****************************************************************************/
+/*
+*
+* This function resets the GPIO module by writing reset values to
+* all registers
+*
+* @param Base address of GPIO module
+*
+* @return None
+*
+* @note None.
+*
+******************************************************************************/
+void XGpioPs_ResetHw(u32 BaseAddress)
+{
+ u32 BankCount;
+ u32 Platform,MaxBanks;
+
+ Platform = XGetPlatform_Info();
+ if (Platform == (u32)XPLAT_ZYNQ_ULTRA_MP) {
+ MaxBanks = (u32)6;
+ }
+ else if(Platform == (u32)XPLAT_VERSAL)
+ {
+ if (BaseAddress == (u32)XGPIOPS_PS_GPIO_BASEADDR)
+ {
+ MaxBanks = (u32)4;
+ }
+ else
+ {
+ MaxBanks = (u32)5;
+ }
+ }
+ else {
+ MaxBanks = (u32)4;
+ }
+
+ if (Platform == (u32)XPLAT_VERSAL)
+ {
+ /* Write reset values to all mask data registers */
+ for(BankCount = 3U; BankCount < (u32)MaxBanks; BankCount++) {
+
+ XGpioPs_WriteReg(BaseAddress,
+ ((BankCount * XGPIOPS_DATA_MASK_OFFSET) +
+ XGPIOPS_DATA_LSW_OFFSET), 0x0U);
+ XGpioPs_WriteReg(BaseAddress,
+ ((BankCount * XGPIOPS_DATA_MASK_OFFSET) +
+ XGPIOPS_DATA_MSW_OFFSET), 0x0U);
+ }
+ /* Write reset values to all output data registers */
+ for(BankCount = 3U; BankCount < (u32)MaxBanks; BankCount++) {
+
+ XGpioPs_WriteReg(BaseAddress,
+ ((BankCount * XGPIOPS_DATA_BANK_OFFSET) +
+ XGPIOPS_DATA_OFFSET), 0x0U);
+ }
+
+ /* Reset all registers of all GPIO banks */
+ for(BankCount = 0U; BankCount < (u32)MaxBanks; BankCount++) {
+
+
+ if((BaseAddress == (u32)XGPIOPS_PS_GPIO_BASEADDR) && ((BankCount == (u32)XGPIOPS_ONE) ||(BankCount == (u32)XGPIOPS_TWO)))
+ {
+ continue;
+ }
+ else
+ {
+ if((BaseAddress != (u32)XGPIOPS_PS_GPIO_BASEADDR) && (BankCount == (u32)XGPIOPS_ONE))
+ {
+ continue;
+ }
+ }
+ XGpioPs_WriteReg(BaseAddress,
+ ((BankCount * XGPIOPS_REG_MASK_OFFSET) +
+ XGPIOPS_DIRM_OFFSET), 0x0U);
+ XGpioPs_WriteReg(BaseAddress,
+ ((BankCount * XGPIOPS_REG_MASK_OFFSET) +
+ XGPIOPS_OUTEN_OFFSET), 0x0U);
+ XGpioPs_WriteReg(BaseAddress,
+ ((BankCount * XGPIOPS_REG_MASK_OFFSET) +
+ XGPIOPS_INTMASK_OFFSET), 0x0U);
+ XGpioPs_WriteReg(BaseAddress,
+ ((BankCount * XGPIOPS_REG_MASK_OFFSET) +
+ XGPIOPS_INTEN_OFFSET), 0x0U);
+ XGpioPs_WriteReg(BaseAddress,
+ ((BankCount * XGPIOPS_REG_MASK_OFFSET) +
+ XGPIOPS_INTDIS_OFFSET), 0x0U);
+ XGpioPs_WriteReg(BaseAddress,
+ ((BankCount * XGPIOPS_REG_MASK_OFFSET) +
+ XGPIOPS_INTSTS_OFFSET), 0x0U);
+ XGpioPs_WriteReg(BaseAddress,
+ ((BankCount * XGPIOPS_REG_MASK_OFFSET) +
+ XGPIOPS_INTPOL_OFFSET), 0x0U);
+ XGpioPs_WriteReg(BaseAddress,
+ ((BankCount * XGPIOPS_REG_MASK_OFFSET) +
+ XGPIOPS_INTANY_OFFSET), 0x0U);
+
+ }
+
+ /* Bank 0 Int type */
+ XGpioPs_WriteReg(BaseAddress, XGPIOPS_INTTYPE_OFFSET,
+ XGPIOPS_INTTYPE_BANK0_RESET);
+ /* Bank 1 Int type */
+ XGpioPs_WriteReg(BaseAddress,
+ ((u32)XGPIOPS_REG_MASK_OFFSET + (u32)XGPIOPS_INTTYPE_OFFSET),
+ XGPIOPS_INTTYPE_BANK1_RESET);
+ /* Bank 3 Int type */
+ XGpioPs_WriteReg(BaseAddress,
+ (((u32)3 * XGPIOPS_REG_MASK_OFFSET) + XGPIOPS_INTTYPE_OFFSET),
+ XGPIOPS_INTTYPE_BANK3_RESET);
+ /* Bank 4 Int type */
+ XGpioPs_WriteReg(BaseAddress,
+ (((u32)4 * XGPIOPS_REG_MASK_OFFSET) + XGPIOPS_INTTYPE_OFFSET),
+ XGPIOPS_INTTYPE_BANK4_RESET);
+ }
+ else
+ {
+ /* Write reset values to all mask data registers */
+ for(BankCount = 2U; BankCount < (u32)MaxBanks; BankCount++) {
+
+ XGpioPs_WriteReg(BaseAddress,
+ ((BankCount * XGPIOPS_DATA_MASK_OFFSET) +
+ XGPIOPS_DATA_LSW_OFFSET), 0x0U);
+ XGpioPs_WriteReg(BaseAddress,
+ ((BankCount * XGPIOPS_DATA_MASK_OFFSET) +
+ XGPIOPS_DATA_MSW_OFFSET), 0x0U);
+ }
+ /* Write reset values to all output data registers */
+ for(BankCount = 2U; BankCount < (u32)MaxBanks; BankCount++) {
+
+ XGpioPs_WriteReg(BaseAddress,
+ ((BankCount * XGPIOPS_DATA_BANK_OFFSET) +
+ XGPIOPS_DATA_OFFSET), 0x0U);
+ }
+ /* Reset all registers of all GPIO banks */
+ for(BankCount = 0U; BankCount < (u32)MaxBanks; BankCount++) {
+
+ XGpioPs_WriteReg(BaseAddress,
+ ((BankCount * XGPIOPS_REG_MASK_OFFSET) +
+ XGPIOPS_DIRM_OFFSET), 0x0U);
+ XGpioPs_WriteReg(BaseAddress,
+ ((BankCount * XGPIOPS_REG_MASK_OFFSET) +
+ XGPIOPS_OUTEN_OFFSET), 0x0U);
+ XGpioPs_WriteReg(BaseAddress,
+ ((BankCount * XGPIOPS_REG_MASK_OFFSET) +
+ XGPIOPS_INTMASK_OFFSET), 0x0U);
+ XGpioPs_WriteReg(BaseAddress,
+ ((BankCount * XGPIOPS_REG_MASK_OFFSET) +
+ XGPIOPS_INTEN_OFFSET), 0x0U);
+ XGpioPs_WriteReg(BaseAddress,
+ ((BankCount * XGPIOPS_REG_MASK_OFFSET) +
+ XGPIOPS_INTDIS_OFFSET), 0x0U);
+ XGpioPs_WriteReg(BaseAddress,
+ ((BankCount * XGPIOPS_REG_MASK_OFFSET) +
+ XGPIOPS_INTSTS_OFFSET), 0x0U);
+ XGpioPs_WriteReg(BaseAddress,
+ ((BankCount * XGPIOPS_REG_MASK_OFFSET) +
+ XGPIOPS_INTPOL_OFFSET), 0x0U);
+ XGpioPs_WriteReg(BaseAddress,
+ ((BankCount * XGPIOPS_REG_MASK_OFFSET) +
+ XGPIOPS_INTANY_OFFSET), 0x0U);
+ }
+ /* Bank 0 Int type */
+ XGpioPs_WriteReg(BaseAddress, XGPIOPS_INTTYPE_OFFSET,
+ XGPIOPS_INTTYPE_BANK0_RESET);
+ /* Bank 1 Int type */
+ XGpioPs_WriteReg(BaseAddress,
+ ((u32)XGPIOPS_REG_MASK_OFFSET + (u32)XGPIOPS_INTTYPE_OFFSET),
+ XGPIOPS_INTTYPE_BANK1_RESET);
+ /* Bank 2 Int type */
+ XGpioPs_WriteReg(BaseAddress,
+ (((u32)2 * XGPIOPS_REG_MASK_OFFSET) + XGPIOPS_INTTYPE_OFFSET),
+ XGPIOPS_INTTYPE_BANK2_RESET);
+ /* Bank 3 Int type */
+ XGpioPs_WriteReg(BaseAddress,
+ (((u32)3 * XGPIOPS_REG_MASK_OFFSET) + XGPIOPS_INTTYPE_OFFSET),
+ XGPIOPS_INTTYPE_BANK3_RESET);
+
+ if (Platform == (u32)XPLAT_ZYNQ_ULTRA_MP) {
+ /* Bank 4 Int type */
+ XGpioPs_WriteReg(BaseAddress,
+ (((u32)4 * XGPIOPS_REG_MASK_OFFSET) + XGPIOPS_INTTYPE_OFFSET),
+ XGPIOPS_INTTYPE_BANK4_RESET);
+ /* Bank 5 Int type */
+ XGpioPs_WriteReg(BaseAddress,
+ (((u32)5 * XGPIOPS_REG_MASK_OFFSET) + XGPIOPS_INTTYPE_OFFSET),
+ XGPIOPS_INTTYPE_BANK5_RESET);
+ }
+ }
+
+}
+/** @} */
diff --git a/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/gpiops_v3_6/src/xgpiops_hw.h b/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/gpiops_v3_6/src/xgpiops_hw.h
new file mode 100644
index 0000000..ff47048
--- /dev/null
+++ b/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/gpiops_v3_6/src/xgpiops_hw.h
@@ -0,0 +1,166 @@
+/******************************************************************************
+*
+* Copyright (C) 2010 - 2019 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+* THE SOFTWARE.
+*
+*
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xgpiops_hw.h
+* @addtogroup gpiops_v3_6
+* @{
+*
+* This header file contains the identifiers and basic driver functions (or
+* macros) that can be used to access the device. Other driver functions
+* are defined in xgpiops.h.
+*
+* <pre>
+* MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ----- ---- -------- -------------------------------------------------
+* 1.00a sv 01/15/10 First Release
+* 1.02a hk 08/22/13 Added low level reset API function prototype and
+* related constant definitions
+* 3.00 kvn 02/13/15 Modified code for MISRA-C:2012 compliance.
+* 3.1 kvn 04/13/15 Corrected reset values of banks.
+* 3.5 sne 03/14/19 Added versal support.
+* </pre>
+*
+******************************************************************************/
+#ifndef XGPIOPS_HW_H /* prevent circular inclusions */
+#define XGPIOPS_HW_H /* by using protection macros */
+
+#ifdef __cplusplus
+extern "C" {
+#endif /* __cplusplus */
+
+/***************************** Include Files *********************************/
+
+#include "xil_types.h"
+#include "xil_assert.h"
+#include "xil_io.h"
+
+/************************** Constant Definitions *****************************/
+
+/** @name Register offsets for the GPIO. Each register is 32 bits.
+ * @{
+ */
+#define XGPIOPS_DATA_LSW_OFFSET 0x00000000U /* Mask and Data Register LSW, WO */
+#define XGPIOPS_DATA_MSW_OFFSET 0x00000004U /* Mask and Data Register MSW, WO */
+#define XGPIOPS_DATA_OFFSET 0x00000040U /* Data Register, RW */
+#define XGPIOPS_DATA_RO_OFFSET 0x00000060U /* Data Register - Input, RO */
+#define XGPIOPS_DIRM_OFFSET 0x00000204U /* Direction Mode Register, RW */
+#define XGPIOPS_OUTEN_OFFSET 0x00000208U /* Output Enable Register, RW */
+#define XGPIOPS_INTMASK_OFFSET 0x0000020CU /* Interrupt Mask Register, RO */
+#define XGPIOPS_INTEN_OFFSET 0x00000210U /* Interrupt Enable Register, WO */
+#define XGPIOPS_INTDIS_OFFSET 0x00000214U /* Interrupt Disable Register, WO*/
+#define XGPIOPS_INTSTS_OFFSET 0x00000218U /* Interrupt Status Register, RO */
+#define XGPIOPS_INTTYPE_OFFSET 0x0000021CU /* Interrupt Type Register, RW */
+#define XGPIOPS_INTPOL_OFFSET 0x00000220U /* Interrupt Polarity Register, RW */
+#define XGPIOPS_INTANY_OFFSET 0x00000224U /* Interrupt On Any Register, RW */
+/* @} */
+
+/** @name Register offsets for each Bank.
+ * @{
+ */
+#define XGPIOPS_DATA_MASK_OFFSET 0x00000008U /* Data/Mask Registers offset */
+#define XGPIOPS_DATA_BANK_OFFSET 0x00000004U /* Data Registers offset */
+#define XGPIOPS_REG_MASK_OFFSET 0x00000040U /* Registers offset */
+/* @} */
+
+/* For backwards compatibility */
+#define XGPIOPS_BYPM_MASK_OFFSET (u32)0x40
+
+/** @name Interrupt type reset values for each bank
+ * @{
+ */
+#ifdef XPAR_PSU_GPIO_0_BASEADDR
+#define XGPIOPS_INTTYPE_BANK0_RESET 0x03FFFFFFU /* Resets specific to Zynq Ultrascale+ MP */
+#define XGPIOPS_INTTYPE_BANK1_RESET 0x03FFFFFFU
+#define XGPIOPS_INTTYPE_BANK2_RESET 0x03FFFFFFU
+#else
+#define XGPIOPS_INTTYPE_BANK0_RESET 0xFFFFFFFFU /* Resets specific to Zynq */
+#define XGPIOPS_INTTYPE_BANK1_RESET 0x003FFFFFU
+#define XGPIOPS_INTTYPE_BANK2_RESET 0xFFFFFFFFU
+#endif
+
+#define XGPIOPS_INTTYPE_BANK3_RESET 0xFFFFFFFFU /* Reset common to both platforms */
+#define XGPIOPS_INTTYPE_BANK4_RESET 0xFFFFFFFFU /* Resets specific to Zynq Ultrascale+ MP */
+#define XGPIOPS_INTTYPE_BANK5_RESET 0xFFFFFFFFU
+/* @} */
+#define XGPIOPS_PS_GPIO_BASEADDR 0xFF0B0000U /* Flag for Base Address for PS_GPIO in Versal */
+#define XGPIOPS_ZERO 0U /* Flag for 0 Value */
+#define XGPIOPS_ONE 1U /* Flag for 1 Value */
+#define XGPIOPS_TWO 2U /* Flag for 2 Value */
+#define XGPIOPS_THREE 3U /* Flag for 3 Value */
+#define XGPIOPS_FOUR 4U /* Flag for 4 Value */
+#define XGPIOPS_SIX 6U /* Flag for 6 Value */
+
+/**************************** Type Definitions *******************************/
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/****************************************************************************/
+/**
+*
+* This macro reads the given register.
+*
+* @param BaseAddr is the base address of the device.
+* @param RegOffset is the register offset to be read.
+*
+* @return The 32-bit value of the register
+*
+* @note None.
+*
+*****************************************************************************/
+#define XGpioPs_ReadReg(BaseAddr, RegOffset) \
+ Xil_In32((BaseAddr) + (u32)(RegOffset))
+
+/****************************************************************************/
+/**
+*
+* This macro writes to the given register.
+*
+* @param BaseAddr is the base address of the device.
+* @param RegOffset is the offset of the register to be written.
+* @param Data is the 32-bit value to write to the register.
+*
+* @return None.
+*
+* @note None.
+*
+*****************************************************************************/
+#define XGpioPs_WriteReg(BaseAddr, RegOffset, Data) \
+ Xil_Out32((BaseAddr) + (u32)(RegOffset), (u32)(Data))
+
+/************************** Function Prototypes ******************************/
+
+void XGpioPs_ResetHw(u32 BaseAddress);
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+
+#endif /* XGPIOPS_HW_H */
+/** @} */
diff --git a/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/gpiops_v3_6/src/xgpiops_intr.c b/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/gpiops_v3_6/src/xgpiops_intr.c
new file mode 100644
index 0000000..1ad7302
--- /dev/null
+++ b/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/gpiops_v3_6/src/xgpiops_intr.c
@@ -0,0 +1,825 @@
+/******************************************************************************
+*
+* Copyright (C) 2010 - 2019 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+* THE SOFTWARE.
+*
+*
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xgpiops_intr.c
+* @addtogroup gpiops_v3_6
+* @{
+*
+* This file contains functions related to GPIO interrupt handling.
+*
+* <pre>
+* MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ----- ---- -------- -----------------------------------------------
+* 1.00a sv 01/18/10 First Release
+* 2.2 sk 10/13/14 Used Pin number in Bank instead of pin number
+* passed to API's. CR# 822636
+* 3.00 kvn 02/13/15 Modified code for MISRA-C:2012 compliance.
+* 3.1 kvn 04/13/15 Add support for Zynq Ultrascale+ MP. CR# 856980.
+* 3.1 aru 07/13/18 Ressolved doxygen reported warnings. CR# 1006331.
+* 3.4 aru 08/09/18 Ressolved cppcheck warnings.
+* 3.4 aru 08/17/18 Resolved MISRA-C mandatory violations. CR# 1007751
+* 3.5 sne 03/01/19 Fixes violations according to MISRAC-2012
+* in safety mode and modified the code such as
+* Use of mixed mode arithmetic,Declared the pointer param
+* as Pointer to const,Casting operation to a pointer,
+* Literal value requires a U suffix.
+* 3.5 sne 03/14/19 Added Versal support.
+* 3.5 sne 03/20/19 Fixed multiple interrupts problem CR#1024556.
+* 3.6 sne 06/12/19 Fixed IAR compiler warning.
+* 3.6 sne 08/14/19 Added interrupt handler support on versal.
+*
+* </pre>
+*
+******************************************************************************/
+
+/***************************** Include Files *********************************/
+
+#include "xgpiops.h"
+
+/************************** Constant Definitions *****************************/
+
+/**************************** Type Definitions *******************************/
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/************************** Variable Definitions *****************************/
+
+/************************** Function Prototypes ******************************/
+
+void StubHandler(const void *CallBackRef, u32 Bank, u32 Status);
+
+/****************************************************************************/
+/**
+*
+* This function enables the interrupts for the specified pins in the specified
+* bank.
+*
+* @param InstancePtr is a pointer to the XGpioPs instance.
+* @param Bank is the bank number of the GPIO to operate on.
+* Valid values are 0-3 in Zynq and 0-5 in Zynq Ultrascale+ MP.
+* @param Mask is the bit mask of the pins for which interrupts are to
+* be enabled. Bit positions of 1 will be enabled. Bit positions
+* of 0 will keep the previous setting.
+*
+* @return None.
+*
+* @note None.
+*
+*****************************************************************************/
+void XGpioPs_IntrEnable(const XGpioPs *InstancePtr, u8 Bank, u32 Mask)
+{
+ Xil_AssertVoid(InstancePtr != NULL);
+ Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+ Xil_AssertVoid(Bank < InstancePtr->MaxBanks);
+#ifdef versal
+ if(InstancePtr->PmcGpio == TRUE) {
+ Xil_AssertVoid(Bank != XGPIOPS_TWO);
+ } else {
+ Xil_AssertVoid((Bank !=XGPIOPS_ONE) && (Bank !=XGPIOPS_TWO));
+ }
+#endif
+
+ XGpioPs_WriteReg(InstancePtr->GpioConfig.BaseAddr,
+ ((u32)(Bank) * XGPIOPS_REG_MASK_OFFSET) +
+ XGPIOPS_INTEN_OFFSET, Mask);
+}
+
+/****************************************************************************/
+/**
+*
+* This function enables the interrupt for the specified pin.
+*
+* @param InstancePtr is a pointer to the XGpioPs instance.
+* @param Pin is the pin number for which the interrupt is to be enabled.
+* Valid values are 0-117 in Zynq and 0-173 in Zynq Ultrascale+ MP.
+*
+* @return None.
+*
+* @note None.
+*
+*****************************************************************************/
+void XGpioPs_IntrEnablePin(const XGpioPs *InstancePtr, u32 Pin)
+{
+ u8 Bank;
+ u8 PinNumber;
+ u32 IntrReg;
+
+ Xil_AssertVoid(InstancePtr != NULL);
+ Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+ Xil_AssertVoid(Pin < InstancePtr->MaxPinNum);
+
+ /* Get the Bank number and Pin number within the bank. */
+#ifdef versal
+ XGpioPs_GetBankPin(InstancePtr,(u8)Pin, &Bank, &PinNumber);
+#else
+ XGpioPs_GetBankPin((u8)Pin, &Bank, &PinNumber);
+#endif
+
+ IntrReg = ((u32)1 << (u32)PinNumber);
+ XGpioPs_WriteReg(InstancePtr->GpioConfig.BaseAddr,
+ ((u32)(Bank) * XGPIOPS_REG_MASK_OFFSET) +
+ XGPIOPS_INTEN_OFFSET, IntrReg);
+}
+
+/****************************************************************************/
+/**
+*
+* This function disables the interrupts for the specified pins in the specified
+* bank.
+*
+* @param InstancePtr is a pointer to the XGpioPs instance.
+* @param Bank is the bank number of the GPIO to operate on.
+* Valid values are 0-3 in Zynq and 0-5 in Zynq Ultrascale+ MP.
+* @param Mask is the bit mask of the pins for which interrupts are
+* to be disabled. Bit positions of 1 will be disabled. Bit
+* positions of 0 will keep the previous setting.
+*
+* @return None.
+*
+* @note None.
+*
+*****************************************************************************/
+void XGpioPs_IntrDisable(const XGpioPs *InstancePtr, u8 Bank, u32 Mask)
+{
+ Xil_AssertVoid(InstancePtr != NULL);
+ Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+ Xil_AssertVoid(Bank < InstancePtr->MaxBanks);
+#ifdef versal
+ if(InstancePtr->PmcGpio == TRUE) {
+ Xil_AssertVoid(Bank != XGPIOPS_TWO);
+ } else {
+ Xil_AssertVoid((Bank !=XGPIOPS_ONE) && (Bank !=XGPIOPS_TWO));
+ }
+#endif
+
+ XGpioPs_WriteReg(InstancePtr->GpioConfig.BaseAddr,
+ ((u32)(Bank) * XGPIOPS_REG_MASK_OFFSET) +
+ XGPIOPS_INTDIS_OFFSET, Mask);
+}
+
+/****************************************************************************/
+/**
+*
+* This function disables the interrupts for the specified pin.
+*
+* @param InstancePtr is a pointer to the XGpioPs instance.
+* @param Pin is the pin number for which the interrupt is to be disabled.
+* Valid values are 0-117 in Zynq and 0-173 in Zynq Ultrascale+ MP.
+*
+* @return None.
+*
+* @note None.
+*
+*****************************************************************************/
+void XGpioPs_IntrDisablePin(const XGpioPs *InstancePtr, u32 Pin)
+{
+ u8 Bank;
+ u8 PinNumber;
+ u32 IntrReg;
+
+ Xil_AssertVoid(InstancePtr != NULL);
+ Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+ Xil_AssertVoid(Pin < InstancePtr->MaxPinNum);
+
+ /* Get the Bank number and Pin number within the bank. */
+#ifdef versal
+ XGpioPs_GetBankPin(InstancePtr,(u8)Pin, &Bank, &PinNumber);
+#else
+ XGpioPs_GetBankPin((u8)Pin, &Bank, &PinNumber);
+#endif
+
+ IntrReg = ((u32)1 << (u32)PinNumber);
+ XGpioPs_WriteReg(InstancePtr->GpioConfig.BaseAddr,
+ ((u32)(Bank) * XGPIOPS_REG_MASK_OFFSET) +
+ XGPIOPS_INTDIS_OFFSET, IntrReg);
+}
+
+/****************************************************************************/
+/**
+*
+* This function returns the interrupt enable status for a bank.
+*
+* @param InstancePtr is a pointer to the XGpioPs instance.
+* @param Bank is the bank number of the GPIO to operate on.
+* Valid values are 0-3 in Zynq and 0-5 in Zynq Ultrascale+ MP.
+*
+* @return Enabled interrupt(s) in a 32-bit format. Bit positions with 1
+* indicate that the interrupt for that pin is enabled, bit
+* positions with 0 indicate that the interrupt for that pin is
+* disabled.
+*
+* @note None.
+*
+*****************************************************************************/
+u32 XGpioPs_IntrGetEnabled(const XGpioPs *InstancePtr, u8 Bank)
+{
+ u32 IntrMask;
+
+ Xil_AssertNonvoid(InstancePtr != NULL);
+ Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+ Xil_AssertNonvoid(Bank < InstancePtr->MaxBanks);
+#ifdef versal
+ if(InstancePtr->PmcGpio == TRUE) {
+ Xil_AssertNonvoid(Bank != XGPIOPS_TWO);
+ } else {
+ Xil_AssertNonvoid((Bank !=XGPIOPS_ONE) && (Bank !=XGPIOPS_TWO));
+ }
+#endif
+
+ IntrMask = XGpioPs_ReadReg(InstancePtr->GpioConfig.BaseAddr,
+ ((u32)(Bank) * XGPIOPS_REG_MASK_OFFSET) +
+ XGPIOPS_INTMASK_OFFSET);
+ return (~IntrMask);
+}
+
+/****************************************************************************/
+/**
+*
+* This function returns whether interrupts are enabled for the specified pin.
+*
+* @param InstancePtr is a pointer to the XGpioPs instance.
+* @param Pin is the pin number for which the interrupt enable status
+* is to be known.
+* Valid values are 0-117 in Zynq and 0-173 in Zynq Ultrascale+ MP.
+*
+* @return
+* - TRUE if the interrupt is enabled.
+* - FALSE if the interrupt is disabled.
+*
+* @note None.
+*
+*****************************************************************************/
+u32 XGpioPs_IntrGetEnabledPin(const XGpioPs *InstancePtr, u32 Pin)
+{
+ u8 Bank;
+ u8 PinNumber;
+ u32 IntrReg;
+
+ Xil_AssertNonvoid(InstancePtr != NULL);
+ Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+ Xil_AssertNonvoid(Pin < InstancePtr->MaxPinNum);
+
+ /* Get the Bank number and Pin number within the bank. */
+#ifdef versal
+ XGpioPs_GetBankPin(InstancePtr,(u8)Pin, &Bank, &PinNumber);
+#else
+ XGpioPs_GetBankPin((u8)Pin, &Bank, &PinNumber);
+#endif
+
+ IntrReg = XGpioPs_ReadReg(InstancePtr->GpioConfig.BaseAddr,
+ ((u32)(Bank) * XGPIOPS_REG_MASK_OFFSET) +
+ XGPIOPS_INTMASK_OFFSET);
+
+ return (((IntrReg & ((u32)1 << PinNumber)) != (u32)0)? FALSE : TRUE);
+}
+
+/****************************************************************************/
+/**
+*
+* This function returns interrupt status read from Interrupt Status Register.
+*
+* @param InstancePtr is a pointer to the XGpioPs instance.
+* @param Bank is the bank number of the GPIO to operate on.
+* Valid values are 0-3 in Zynq and 0-5 in Zynq Ultrascale+ MP.
+*
+* @return The value read from Interrupt Status Register.
+*
+* @note None.
+*
+*****************************************************************************/
+u32 XGpioPs_IntrGetStatus(const XGpioPs *InstancePtr, u8 Bank)
+{
+ Xil_AssertNonvoid(InstancePtr != NULL);
+ Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+ Xil_AssertNonvoid(Bank < InstancePtr->MaxBanks);
+#ifdef versal
+ if(InstancePtr->PmcGpio == TRUE) {
+ Xil_AssertNonvoid(Bank != XGPIOPS_TWO);
+ } else {
+ Xil_AssertNonvoid((Bank !=XGPIOPS_ONE) && (Bank !=XGPIOPS_TWO));
+ }
+#endif
+
+ return XGpioPs_ReadReg(InstancePtr->GpioConfig.BaseAddr,
+ ((u32)(Bank) * XGPIOPS_REG_MASK_OFFSET) +
+ XGPIOPS_INTSTS_OFFSET);
+}
+
+/****************************************************************************/
+/**
+*
+* This function returns interrupt enable status of the specified pin.
+*
+* @param InstancePtr is a pointer to the XGpioPs instance.
+* @param Pin is the pin number for which the interrupt enable status
+* is to be known.
+* Valid values are 0-117 in Zynq and 0-173 in Zynq Ultrascale+ MP.
+*
+* @return
+* - TRUE if the interrupt has occurred.
+* - FALSE if the interrupt has not occurred.
+*
+* @note None.
+*
+*****************************************************************************/
+u32 XGpioPs_IntrGetStatusPin(const XGpioPs *InstancePtr, u32 Pin)
+{
+ u8 Bank;
+ u8 PinNumber;
+ u32 IntrReg;
+
+ Xil_AssertNonvoid(InstancePtr != NULL);
+ Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+ Xil_AssertNonvoid(Pin < InstancePtr->MaxPinNum);
+
+ /* Get the Bank number and Pin number within the bank. */
+#ifdef versal
+ XGpioPs_GetBankPin(InstancePtr,(u8)Pin, &Bank, &PinNumber);
+#else
+ XGpioPs_GetBankPin((u8)Pin, &Bank, &PinNumber);
+#endif
+
+ IntrReg = XGpioPs_ReadReg(InstancePtr->GpioConfig.BaseAddr,
+ ((u32)(Bank) * XGPIOPS_REG_MASK_OFFSET) +
+ XGPIOPS_INTSTS_OFFSET);
+
+ return (((IntrReg & ((u32)1 << PinNumber)) != (u32)0)? TRUE : FALSE);
+}
+
+/****************************************************************************/
+/**
+*
+* This function clears pending interrupt(s) with the provided mask. This
+* function should be called after the software has serviced the interrupts
+* that are pending.
+*
+* @param InstancePtr is a pointer to the XGpioPs instance.
+* @param Bank is the bank number of the GPIO to operate on.
+* Valid values are 0-3 in Zynq and 0-5 in Zynq Ultrascale+ MP.
+* @param Mask is the mask of the interrupts to be cleared. Bit positions
+* of 1 will be cleared. Bit positions of 0 will not change the
+* previous interrupt status.
+*
+* @note None.
+*
+*****************************************************************************/
+void XGpioPs_IntrClear(const XGpioPs *InstancePtr, u8 Bank, u32 Mask)
+{
+ Xil_AssertVoid(InstancePtr != NULL);
+ Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+ Xil_AssertVoid(Bank < InstancePtr->MaxBanks);
+#ifdef versal
+ if(InstancePtr->PmcGpio == TRUE) {
+ Xil_AssertVoid(Bank != XGPIOPS_TWO);
+ } else {
+ Xil_AssertVoid((Bank !=XGPIOPS_ONE) && (Bank !=XGPIOPS_TWO));
+ }
+#endif
+
+ /* Clear the currently pending interrupts. */
+ XGpioPs_WriteReg(InstancePtr->GpioConfig.BaseAddr,
+ ((u32)(Bank) * XGPIOPS_REG_MASK_OFFSET) +
+ XGPIOPS_INTSTS_OFFSET, Mask);
+}
+
+/****************************************************************************/
+/**
+*
+* This function clears the specified pending interrupt. This function should be
+* called after the software has serviced the interrupts that are pending.
+*
+* @param InstancePtr is a pointer to the XGpioPs instance.
+* @param Pin is the pin number for which the interrupt status is to be
+* cleared. Valid values are 0-117 in Zynq and 0-173 in Zynq Ultrascale+ MP.
+*
+* @note None.
+*
+*****************************************************************************/
+void XGpioPs_IntrClearPin(const XGpioPs *InstancePtr, u32 Pin)
+{
+ u8 Bank;
+ u8 PinNumber;
+ u32 IntrReg;
+
+ Xil_AssertVoid(InstancePtr != NULL);
+ Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+ Xil_AssertVoid(Pin < InstancePtr->MaxPinNum);
+
+ /* Get the Bank number and Pin number within the bank. */
+#ifdef versal
+ XGpioPs_GetBankPin(InstancePtr,(u8)Pin, &Bank, &PinNumber);
+#else
+ XGpioPs_GetBankPin((u8)Pin, &Bank, &PinNumber);
+#endif
+
+ /* Clear the specified pending interrupts. */
+ IntrReg = XGpioPs_ReadReg(InstancePtr->GpioConfig.BaseAddr,
+ ((u32)(Bank) * XGPIOPS_REG_MASK_OFFSET) +
+ XGPIOPS_INTSTS_OFFSET);
+
+ IntrReg &= ((u32)1 << PinNumber);
+ XGpioPs_WriteReg(InstancePtr->GpioConfig.BaseAddr,
+ ((u32)(Bank) * XGPIOPS_REG_MASK_OFFSET) +
+ XGPIOPS_INTSTS_OFFSET, IntrReg);
+}
+
+/****************************************************************************/
+/**
+*
+* This function is used for setting the Interrupt Type, Interrupt Polarity and
+* Interrupt On Any for the specified GPIO Bank pins.
+*
+* @param InstancePtr is a pointer to an XGpioPs instance.
+* @param Bank is the bank number of the GPIO to operate on.
+* Valid values are 0-3 in Zynq and 0-5 in Zynq Ultrascale+ MP.
+* @param IntrType is the 32 bit mask of the interrupt type.
+* 0 means Level Sensitive and 1 means Edge Sensitive.
+* @param IntrPolarity is the 32 bit mask of the interrupt polarity.
+* 0 means Active Low or Falling Edge and 1 means Active High or
+* Rising Edge.
+* @param IntrOnAny is the 32 bit mask of the interrupt trigger for
+* edge triggered interrupts. 0 means trigger on single edge using
+* the configured interrupt polarity and 1 means trigger on both
+* edges.
+*
+* @return None.
+*
+* @note This function is used for setting the interrupt related
+* properties of all the pins in the specified bank. The previous
+* state of the pins is not maintained.
+* To change the Interrupt properties of a single GPIO pin, use the
+* function XGpioPs_SetPinIntrType().
+*
+*****************************************************************************/
+void XGpioPs_SetIntrType(const XGpioPs *InstancePtr, u8 Bank, u32 IntrType,
+ u32 IntrPolarity, u32 IntrOnAny)
+{
+ Xil_AssertVoid(InstancePtr != NULL);
+ Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+ Xil_AssertVoid(Bank < InstancePtr->MaxBanks);
+#ifdef versal
+ if(InstancePtr->PmcGpio == TRUE) {
+ Xil_AssertVoid(Bank != XGPIOPS_TWO);
+ } else {
+ Xil_AssertVoid((Bank !=XGPIOPS_ONE) && (Bank !=XGPIOPS_TWO));
+ }
+#endif
+
+ XGpioPs_WriteReg(InstancePtr->GpioConfig.BaseAddr,
+ ((u32)(Bank) * XGPIOPS_REG_MASK_OFFSET) +
+ XGPIOPS_INTTYPE_OFFSET, IntrType);
+
+ XGpioPs_WriteReg(InstancePtr->GpioConfig.BaseAddr,
+ ((u32)(Bank) * XGPIOPS_REG_MASK_OFFSET) +
+ XGPIOPS_INTPOL_OFFSET, IntrPolarity);
+
+ XGpioPs_WriteReg(InstancePtr->GpioConfig.BaseAddr,
+ ((u32)(Bank) * XGPIOPS_REG_MASK_OFFSET) +
+ XGPIOPS_INTANY_OFFSET, IntrOnAny);
+}
+
+/****************************************************************************/
+/**
+*
+* This function is used for getting the Interrupt Type, Interrupt Polarity and
+* Interrupt On Any for the specified GPIO Bank pins.
+*
+* @param InstancePtr is a pointer to an XGpioPs instance.
+* @param Bank is the bank number of the GPIO to operate on.
+* Valid values are 0-3 in Zynq and 0-5 in Zynq Ultrascale+ MP.
+* @param IntrType returns the 32 bit mask of the interrupt type.
+* 0 means Level Sensitive and 1 means Edge Sensitive.
+* @param IntrPolarity returns the 32 bit mask of the interrupt
+* polarity. 0 means Active Low or Falling Edge and 1 means
+* Active High or Rising Edge.
+* @param IntrOnAny returns the 32 bit mask of the interrupt trigger for
+* edge triggered interrupts. 0 means trigger on single edge using
+* the configured interrupt polarity and 1 means trigger on both
+* edges.
+*
+* @return None.
+*
+* @note None.
+*
+*****************************************************************************/
+void XGpioPs_GetIntrType(const XGpioPs *InstancePtr, u8 Bank, u32 *IntrType,
+ u32 *IntrPolarity, u32 *IntrOnAny)
+
+{
+ Xil_AssertVoid(InstancePtr != NULL);
+ Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+ Xil_AssertVoid(Bank < InstancePtr->MaxBanks);
+#ifdef versal
+ if(InstancePtr->PmcGpio == TRUE) {
+ Xil_AssertVoid(Bank != XGPIOPS_TWO);
+ } else {
+ Xil_AssertVoid((Bank !=XGPIOPS_ONE) && (Bank !=XGPIOPS_TWO));
+ }
+#endif
+
+ *IntrType = XGpioPs_ReadReg(InstancePtr->GpioConfig.BaseAddr,
+ ((u32)(Bank) * XGPIOPS_REG_MASK_OFFSET) +
+ XGPIOPS_INTTYPE_OFFSET);
+
+ *IntrPolarity = XGpioPs_ReadReg(InstancePtr->GpioConfig.BaseAddr,
+ ((u32)(Bank) * XGPIOPS_REG_MASK_OFFSET) +
+ XGPIOPS_INTPOL_OFFSET);
+
+ *IntrOnAny = XGpioPs_ReadReg(InstancePtr->GpioConfig.BaseAddr,
+ ((u32)(Bank) * XGPIOPS_REG_MASK_OFFSET) +
+ XGPIOPS_INTANY_OFFSET);
+}
+
+/****************************************************************************/
+/**
+*
+* This function is used for setting the IRQ Type of a single GPIO pin.
+*
+* @param InstancePtr is a pointer to an XGpioPs instance.
+* @param Pin is the pin number whose IRQ type is to be set.
+* Valid values are 0-117 in Zynq and 0-173 in Zynq Ultrascale+ MP.
+* @param IrqType is the IRQ type for GPIO Pin. Use XGPIOPS_IRQ_TYPE_*
+* defined in xgpiops.h to specify the IRQ type.
+*
+* @return None.
+*
+* @note None.
+*
+*****************************************************************************/
+void XGpioPs_SetIntrTypePin(const XGpioPs *InstancePtr, u32 Pin, u8 IrqType)
+{
+ u32 IntrTypeReg;
+ u32 IntrPolReg;
+ u32 IntrOnAnyReg;
+ u8 Bank;
+ u8 PinNumber;
+
+ Xil_AssertVoid(InstancePtr != NULL);
+ Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+ Xil_AssertVoid(Pin < InstancePtr->MaxPinNum);
+ Xil_AssertVoid(IrqType <= XGPIOPS_IRQ_TYPE_LEVEL_LOW);
+
+ /* Get the Bank number and Pin number within the bank. */
+#ifdef versal
+ XGpioPs_GetBankPin(InstancePtr,(u8)Pin, &Bank, &PinNumber);
+#else
+ XGpioPs_GetBankPin((u8)Pin, &Bank, &PinNumber);
+#endif
+
+ IntrTypeReg = XGpioPs_ReadReg(InstancePtr->GpioConfig.BaseAddr,
+ ((u32)(Bank) * XGPIOPS_REG_MASK_OFFSET) +
+ XGPIOPS_INTTYPE_OFFSET);
+
+ IntrPolReg = XGpioPs_ReadReg(InstancePtr->GpioConfig.BaseAddr,
+ ((u32)(Bank) * XGPIOPS_REG_MASK_OFFSET) +
+ XGPIOPS_INTPOL_OFFSET);
+
+ IntrOnAnyReg = XGpioPs_ReadReg(InstancePtr->GpioConfig.BaseAddr,
+ ((u32)(Bank) * XGPIOPS_REG_MASK_OFFSET) +
+ XGPIOPS_INTANY_OFFSET);
+
+ switch (IrqType) {
+ case XGPIOPS_IRQ_TYPE_EDGE_RISING:
+ IntrTypeReg |= ((u32)1 << (u32)PinNumber);
+ IntrPolReg |= ((u32)1 << (u32)PinNumber);
+ IntrOnAnyReg &= ~((u32)1 << (u32)PinNumber);
+ break;
+ case XGPIOPS_IRQ_TYPE_EDGE_FALLING:
+ IntrTypeReg |= ((u32)1 << (u32)PinNumber);
+ IntrPolReg &= ~((u32)1 << (u32)PinNumber);
+ IntrOnAnyReg &= ~((u32)1 << (u32)PinNumber);
+ break;
+ case XGPIOPS_IRQ_TYPE_EDGE_BOTH:
+ IntrTypeReg |= ((u32)1 << (u32)PinNumber);
+ IntrOnAnyReg |= ((u32)1 << (u32)PinNumber);
+ break;
+ case XGPIOPS_IRQ_TYPE_LEVEL_HIGH:
+ IntrTypeReg &= ~((u32)1 << (u32)PinNumber);
+ IntrPolReg |= ((u32)1 << (u32)PinNumber);
+ break;
+ case XGPIOPS_IRQ_TYPE_LEVEL_LOW:
+ IntrTypeReg &= ~((u32)1 << (u32)PinNumber);
+ IntrPolReg &= ~((u32)1 << (u32)PinNumber);
+ break;
+ default:
+ /**< Default statement is added for MISRA C compliance. */
+ break;
+ }
+
+ XGpioPs_WriteReg(InstancePtr->GpioConfig.BaseAddr,
+ ((u32)(Bank) * XGPIOPS_REG_MASK_OFFSET) +
+ XGPIOPS_INTTYPE_OFFSET, IntrTypeReg);
+
+ XGpioPs_WriteReg(InstancePtr->GpioConfig.BaseAddr,
+ ((u32)(Bank) * XGPIOPS_REG_MASK_OFFSET) +
+ XGPIOPS_INTPOL_OFFSET, IntrPolReg);
+
+ XGpioPs_WriteReg(InstancePtr->GpioConfig.BaseAddr,
+ ((u32)(Bank) * XGPIOPS_REG_MASK_OFFSET) +
+ XGPIOPS_INTANY_OFFSET, IntrOnAnyReg);
+}
+
+/****************************************************************************/
+/**
+*
+* This function returns the IRQ Type of a given GPIO pin.
+*
+* @param InstancePtr is a pointer to an XGpioPs instance.
+* @param Pin is the pin number whose IRQ type is to be obtained.
+* Valid values are 0-117 in Zynq and 0-173 in Zynq Ultrascale+ MP.
+*
+* @return None.
+*
+* @note Use XGPIOPS_IRQ_TYPE_* defined in xgpiops.h for the IRQ type
+* returned by this function.
+*
+*****************************************************************************/
+u8 XGpioPs_GetIntrTypePin(const XGpioPs *InstancePtr, u32 Pin)
+{
+ u32 IntrType;
+ u32 IntrPol;
+ u32 IntrOnAny;
+ u8 Bank;
+ u8 PinNumber;
+ u8 IrqType;
+
+ Xil_AssertNonvoid(InstancePtr != NULL);
+ Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+ Xil_AssertNonvoid(Pin < InstancePtr->MaxPinNum);
+
+ /* Get the Bank number and Pin number within the bank. */
+#ifdef versal
+ XGpioPs_GetBankPin(InstancePtr,(u8)Pin, &Bank, &PinNumber);
+#else
+ XGpioPs_GetBankPin((u8)Pin, &Bank, &PinNumber);
+#endif
+
+ IntrType = XGpioPs_ReadReg(InstancePtr->GpioConfig.BaseAddr,
+ ((u32)(Bank) * XGPIOPS_REG_MASK_OFFSET) +
+ XGPIOPS_INTTYPE_OFFSET) & ((u32)1 << PinNumber);
+
+ if (IntrType == ((u32)1 << PinNumber)) {
+
+ IntrOnAny = XGpioPs_ReadReg(InstancePtr->GpioConfig.BaseAddr,
+ ((u32)(Bank) * XGPIOPS_REG_MASK_OFFSET) +
+ XGPIOPS_INTANY_OFFSET) & ((u32)1 << PinNumber);
+
+ IntrPol = XGpioPs_ReadReg(InstancePtr->GpioConfig.BaseAddr,
+ ((u32)(Bank) * XGPIOPS_REG_MASK_OFFSET) +
+ XGPIOPS_INTPOL_OFFSET) & ((u32)1 << PinNumber);
+
+
+ if (IntrOnAny == ((u32)1 << PinNumber)) {
+ IrqType = XGPIOPS_IRQ_TYPE_EDGE_BOTH;
+ } else if (IntrPol == ((u32)1 << PinNumber)) {
+ IrqType = XGPIOPS_IRQ_TYPE_EDGE_RISING;
+ } else {
+ IrqType = XGPIOPS_IRQ_TYPE_EDGE_FALLING;
+ }
+ } else {
+
+ IntrPol = XGpioPs_ReadReg(InstancePtr->GpioConfig.BaseAddr,
+ ((u32)(Bank) * XGPIOPS_REG_MASK_OFFSET) +
+ XGPIOPS_INTPOL_OFFSET) & ((u32)1 << PinNumber);
+
+ if (IntrPol == ((u32)1 << PinNumber)) {
+ IrqType = XGPIOPS_IRQ_TYPE_LEVEL_HIGH;
+ } else {
+ IrqType = XGPIOPS_IRQ_TYPE_LEVEL_LOW;
+ }
+ }
+
+ return IrqType;
+}
+
+/*****************************************************************************/
+/**
+*
+* This function sets the status callback function. The callback function is
+* called by the XGpioPs_IntrHandler when an interrupt occurs.
+*
+* @param InstancePtr is a pointer to the XGpioPs instance.
+* @param CallBackRef is the upper layer callback reference passed back
+* when the callback function is invoked.
+* @param FuncPointer is the pointer to the callback function.
+*
+*
+* @return None.
+*
+* @note The handler is called within interrupt context, so it should do
+* its work quickly and queue potentially time-consuming work to a
+* task-level thread.
+*
+******************************************************************************/
+void XGpioPs_SetCallbackHandler(XGpioPs *InstancePtr, void *CallBackRef,
+ XGpioPs_Handler FuncPointer)
+{
+ Xil_AssertVoid(InstancePtr != NULL);
+ Xil_AssertVoid(FuncPointer != NULL);
+ Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+ InstancePtr->Handler = FuncPointer;
+ InstancePtr->CallBackRef = CallBackRef;
+}
+
+/*****************************************************************************/
+/**
+*
+* This function is the interrupt handler for GPIO interrupts.It checks the
+* interrupt status registers of all the banks to determine the actual bank in
+* which an interrupt has been triggered. It then calls the upper layer callback
+* handler set by the function XGpioPs_SetBankHandler(). The callback is called
+* when an interrupt
+*
+* @param InstancePtr is a pointer to the XGpioPs instance.
+*
+* @return None.
+*
+* @note This function does not save and restore the processor context
+* such that the user must provide this processing.
+*
+******************************************************************************/
+void XGpioPs_IntrHandler(const XGpioPs *InstancePtr)
+{
+ u8 Bank;
+ u32 IntrStatus;
+ u32 IntrEnabled;
+
+ Xil_AssertVoid(InstancePtr != NULL);
+ Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+ for (Bank = 0U; Bank < InstancePtr->MaxBanks; Bank++) {
+#ifdef versal
+ if(InstancePtr->PmcGpio == TRUE) {
+ if(Bank == XGPIOPS_TWO) {
+ continue;
+ }
+ } else {
+ if((Bank == XGPIOPS_ONE) || (Bank == XGPIOPS_TWO)) {
+ continue;
+ }
+ }
+#endif
+ IntrStatus = XGpioPs_IntrGetStatus(InstancePtr, Bank);
+ IntrEnabled = XGpioPs_IntrGetEnabled(InstancePtr,Bank);
+ if ((IntrStatus & IntrEnabled) != (u32)0) {
+ XGpioPs_IntrClear(InstancePtr, Bank,
+ (IntrStatus & IntrEnabled));
+ InstancePtr->Handler(InstancePtr->
+ CallBackRef, Bank,
+ (IntrStatus & IntrEnabled));
+ }
+ }
+}
+
+/*****************************************************************************/
+/**
+*
+* This is a stub for the status callback. The stub is here in case the upper
+* layers do not set the handler.
+*
+* @param CallBackRef is a pointer to the upper layer callback reference
+* @param Bank is the GPIO Bank in which an interrupt occurred.
+* @param Status is the Interrupt status of the GPIO bank.
+*
+* @return None.
+*
+* @note None.
+*
+******************************************************************************/
+void StubHandler(const void *CallBackRef, u32 Bank, u32 Status)
+{
+ (void) CallBackRef;
+ (void) Bank;
+ (void) Status;
+
+ Xil_AssertVoidAlways();
+}
+/** @} */
diff --git a/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/gpiops_v3_6/src/xgpiops_selftest.c b/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/gpiops_v3_6/src/xgpiops_selftest.c
new file mode 100644
index 0000000..4a002b5
--- /dev/null
+++ b/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/gpiops_v3_6/src/xgpiops_selftest.c
@@ -0,0 +1,132 @@
+/******************************************************************************
+*
+* Copyright (C) 2010 - 2019 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+* THE SOFTWARE.
+*
+*
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xgpiops_selftest.c
+* @addtogroup gpiops_v3_6
+* @{
+*
+* This file contains a diagnostic self-test function for the XGpioPs driver.
+*
+* Read xgpiops.h file for more information.
+*
+* <pre>
+* MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ----- ---- -------- -----------------------------------------------
+* 1.00a sv 01/18/10 First Release
+* 3.00 kvn 02/13/15 Modified code for MISRA-C:2012 compliance.
+* 3.5 sne 03/01/19 Fixes violations according to MISRAC-2012
+* in safety mode and modified the code such as
+* Use of mixed mode arithmetic,Declared the pointer param
+* as Pointer to const,Casting operation to a pointer,
+* Literal value requires a U suffix.
+* </pre>
+*
+*****************************************************************************/
+
+/***************************** Include Files ********************************/
+
+#include "xstatus.h"
+#include "xgpiops.h"
+
+/************************** Constant Definitions ****************************/
+
+
+/**************************** Type Definitions ******************************/
+
+/***************** Macros (Inline Functions) Definitions ********************/
+
+/************************** Variable Definitions ****************************/
+
+/************************** Function Prototypes *****************************/
+
+/*****************************************************************************/
+/**
+*
+* This function runs a self-test on the GPIO driver/device. This function
+* does a register read/write test on some of the Interrupt Registers.
+*
+* @param InstancePtr is a pointer to the XGpioPs instance.
+*
+* @return
+* - XST_SUCCESS if the self-test passed.
+* - XST_FAILURE otherwise.
+*
+*
+******************************************************************************/
+s32 XGpioPs_SelfTest(const XGpioPs *InstancePtr)
+{
+ s32 Status = XST_SUCCESS;
+ u32 IntrEnabled;
+ u32 CurrentIntrType = 0U;
+ u32 CurrentIntrPolarity = 0U;
+ u32 CurrentIntrOnAny = 0U;
+ u32 IntrType = 0U;
+ u32 IntrPolarity = 0U;
+ u32 IntrOnAny = 0U;
+ u32 IntrTestValue = 0x22U;
+
+ Xil_AssertNonvoid(InstancePtr != NULL);
+ Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+ /* Disable the Interrupts for Bank 0 . */
+ IntrEnabled = XGpioPs_IntrGetEnabled(InstancePtr, XGPIOPS_BANK0);
+ XGpioPs_IntrDisable(InstancePtr, XGPIOPS_BANK0, IntrEnabled);
+
+ /*
+ * Get the Current Interrupt properties for Bank 0.
+ * Set them to a known value, read it back and compare.
+ */
+ XGpioPs_GetIntrType(InstancePtr, XGPIOPS_BANK0, &CurrentIntrType,
+ &CurrentIntrPolarity, &CurrentIntrOnAny);
+
+ XGpioPs_SetIntrType(InstancePtr, XGPIOPS_BANK0, IntrTestValue,
+ IntrTestValue, IntrTestValue);
+
+ XGpioPs_GetIntrType(InstancePtr, XGPIOPS_BANK0, &IntrType,
+ &IntrPolarity, &IntrOnAny);
+
+ if ((IntrType != IntrTestValue) && (IntrPolarity != IntrTestValue) &&
+ (IntrOnAny != IntrTestValue)) {
+
+ Status = XST_FAILURE;
+ }
+
+ /*
+ * Restore the contents of all the interrupt registers modified in this
+ * test.
+ */
+ XGpioPs_SetIntrType(InstancePtr, XGPIOPS_BANK0, CurrentIntrType,
+ CurrentIntrPolarity, CurrentIntrOnAny);
+
+ XGpioPs_IntrEnable(InstancePtr, XGPIOPS_BANK0, IntrEnabled);
+
+ return Status;
+}
+/** @} */
diff --git a/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/gpiops_v3_6/src/xgpiops_sinit.c b/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/gpiops_v3_6/src/xgpiops_sinit.c
new file mode 100644
index 0000000..3b3b321
--- /dev/null
+++ b/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/gpiops_v3_6/src/xgpiops_sinit.c
@@ -0,0 +1,95 @@
+/******************************************************************************
+*
+* Copyright (C) 2010 - 2019 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+* THE SOFTWARE.
+*
+*
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xgpiops_sinit.c
+* @addtogroup gpiops_v3_6
+* @{
+*
+* This file contains the implementation of the XGpioPs driver's static
+* initialization functionality.
+*
+* @note None.
+*
+* <pre>
+*
+* MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ----- ---- -------- -----------------------------------------------
+* 1.00a sv 01/15/10 First Release
+* 3.00 kvn 02/13/15 Modified code for MISRA-C:2012 compliance.
+* </pre>
+*
+******************************************************************************/
+
+/***************************** Include Files *********************************/
+
+#include "xgpiops.h"
+#include "xparameters.h"
+
+/************************** Constant Definitions *****************************/
+
+/**************************** Type Definitions *******************************/
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/************************** Function Prototypes ******************************/
+
+/************************** Variable Definitions *****************************/
+extern XGpioPs_Config XGpioPs_ConfigTable[XPAR_XGPIOPS_NUM_INSTANCES];
+
+/*****************************************************************************/
+/**
+*
+* This function looks for the device configuration based on the unique device
+* ID. The table XGpioPs_ConfigTable[] contains the configuration information
+* for each device in the system.
+*
+* @param DeviceId is the unique device ID of the device being looked up.
+*
+* @return A pointer to the configuration table entry corresponding to the
+* given device ID, or NULL if no match is found.
+*
+* @note None.
+*
+******************************************************************************/
+XGpioPs_Config *XGpioPs_LookupConfig(u16 DeviceId)
+{
+ XGpioPs_Config *CfgPtr = NULL;
+ u32 Index;
+
+ for (Index = 0U; Index < (u32)XPAR_XGPIOPS_NUM_INSTANCES; Index++) {
+ if (XGpioPs_ConfigTable[Index].DeviceId == DeviceId) {
+ CfgPtr = &XGpioPs_ConfigTable[Index];
+ break;
+ }
+ }
+
+ return (XGpioPs_Config *)CfgPtr;
+}
+/** @} */
diff --git a/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/qspips_v3_6/src/Makefile b/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/qspips_v3_6/src/Makefile
new file mode 100644
index 0000000..3600928
--- /dev/null
+++ b/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/qspips_v3_6/src/Makefile
@@ -0,0 +1,40 @@
+COMPILER=
+ARCHIVER=
+CP=cp
+COMPILER_FLAGS=
+EXTRA_COMPILER_FLAGS=
+LIB=libxil.a
+
+CC_FLAGS = $(COMPILER_FLAGS)
+ECC_FLAGS = $(EXTRA_COMPILER_FLAGS)
+
+RELEASEDIR=../../../lib
+INCLUDEDIR=../../../include
+INCLUDES=-I./. -I${INCLUDEDIR}
+
+OUTS = *.o
+
+LIBSOURCES:=*.c
+INCLUDEFILES:=*.h
+
+OBJECTS = $(addsuffix .o, $(basename $(wildcard *.c)))
+
+libs: banner xqspips_libs clean
+
+%.o: %.c
+ ${COMPILER} $(CC_FLAGS) $(ECC_FLAGS) $(INCLUDES) -o $@ $<
+
+banner:
+ echo "Compiling qspips"
+
+xqspips_libs: ${OBJECTS}
+ $(ARCHIVER) -r ${RELEASEDIR}/${LIB} ${OBJECTS}
+
+.PHONY: include
+include: xqspips_includes
+
+xqspips_includes:
+ ${CP} ${INCLUDEFILES} ${INCLUDEDIR}
+
+clean:
+ rm -rf ${OBJECTS}
diff --git a/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/qspips_v3_6/src/xqspips.c b/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/qspips_v3_6/src/xqspips.c
new file mode 100644
index 0000000..0a20a6d
--- /dev/null
+++ b/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/qspips_v3_6/src/xqspips.c
@@ -0,0 +1,1609 @@
+/******************************************************************************
+*
+* Copyright (C) 2010 - 2019 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+* THE SOFTWARE.
+*
+*
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xqspips.c
+* @addtogroup qspips_v3_6
+* @{
+*
+* Contains implements the interface functions of the XQspiPs driver.
+* See xqspips.h for a detailed description of the device and driver.
+*
+* <pre>
+* MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ----- --- -------- -----------------------------------------------
+* 1.00 sdm 11/25/10 First release
+* 2.00a kka 07/25/12 Removed XQspiPs_GetWriteData API.
+* The XQspiPs_SetSlaveSelect has been modified to remove
+* the argument of the slave select as the QSPI controller
+* only supports one slave.
+* XQspiPs_GetSlaveSelect API has been removed
+* Added logic to XQspiPs_GetReadData to handle data
+* shift for normal data reads and instruction/status
+* reads differently based on the ShiftReadData flag.
+* Removed the selection for the following options:
+* Master mode (XQSPIPS_MASTER_OPTION) and
+* Flash interface mode (XQSPIPS_FLASH_MODE_OPTION) option
+* as the QSPI driver supports the Master mode
+* and Flash Interface mode and doesnot support
+* Slave mode or the legacy mode.
+* Modified the XQspiPs_PolledTransfer and XQspiPs_Transfer
+* APIs so that the last argument (IsInst) specifying whether
+* it is instruction or data has been removed. The first byte
+* in the SendBufPtr argument of these APIs specify the
+* instruction to be sent to the Flash Device.
+* The XQspiPs_PolledTransfer function has been updated
+* to fill the data to fifo depth.
+* This version of the driver fixes CRs 670197/663787.
+* 2.01a sg 02/03/13 Added flash opcodes for DUAL_IO_READ,QUAD_IO_READ.
+* Created macros XQspiPs_IsManualStart and
+* XQspiPs_IsManualChipSelect.
+* Changed QSPI transfer logic for polled and interrupt
+* modes to be based on filled tx fifo count and receive
+* based on it. RXNEMPTY interrupt is not used.
+* Added assertions to XQspiPs_LqspiRead function.
+*
+* 2.02a hk 05/14/13 Added enable and disable to the XQspiPs_LqspiRead()
+* function
+* Added instructions for bank selection, die erase and
+* flag status register to the flash instruction table
+* Handling for instructions not in flash instruction
+* table added. Checking for Tx FIFO empty when switching from
+* TXD1/2/3 to TXD0 added. If WRSR instruction is sent with
+* byte count 3 (spansion), instruction size and TXD register
+* changed accordingly. CR# 712502 and 703869.
+* Added (#ifdef linear base address) in the Linear read function.
+* Changed XPAR_XQSPIPS_0_LINEAR_BASEADDR to
+* XPAR_PS7_QSPI_LINEAR_0_S_AXI_BASEADDR in
+* XQspiPs_LqspiRead function. Fix for CR#718141
+*
+* 2.03a hk 09/05/13 Modified polled and interrupt transfers to make use of
+* thresholds. This is to improve performance.
+* Added RX and TX threshold reset to one in XQspiPs_Abort.
+* Added RX threshold reset(1) after transfer in polled and
+* interrupt transfers. Made changes to make sure threshold
+* change is done only when no transfer is in progress.
+* 3.1 hk 08/13/14 When writing to the configuration register, set/reset
+* required bits leaving reserved bits untouched. CR# 796813.
+* 3.2 sk 02/05/15 Add SLCR reset in abort function as a workaround because
+* controller does not update FIFO status flags as expected
+* when thresholds are used.
+* 3.3 sk 11/07/15 Modified the API prototypes according to MISRAC standards
+* to remove compilation warnings. CR# 868893.
+* 3.5 tjs 13/08/18 Fixed compilation warnings for ARMCC.
+* 3.6 akm 03/28/19 Fixed memory leak issue while reading from qspi.(CR#1016357)
+* 3.6 akm 04/15/19 Modified the mask in XQspiPs_GetReadData() API to retrieve
+* configuration register values of both the Flashes in dual
+* parellel connection.
+*
+* </pre>
+*
+******************************************************************************/
+
+/***************************** Include Files *********************************/
+
+#include "xqspips.h"
+
+/************************** Constant Definitions *****************************/
+
+
+/**************************** Type Definitions *******************************/
+
+/**
+ * This typedef defines qspi flash instruction format
+ */
+typedef struct {
+ u8 OpCode; /**< Operational code of the instruction */
+ u8 InstSize; /**< Size of the instruction including address bytes */
+ u8 TxOffset; /**< Register address where instruction has to be
+ written */
+} XQspiPsInstFormat;
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+#define ARRAY_SIZE(Array) (sizeof(Array) / sizeof((Array)[0]))
+
+/************************** Function Prototypes ******************************/
+static void XQspiPs_GetReadData(XQspiPs *InstancePtr, u32 Data, u8 Size);
+static void StubStatusHandler(void *CallBackRef, u32 StatusEvent,
+ unsigned ByteCount);
+
+/************************** Variable Definitions *****************************/
+
+/*
+ * List of all the QSPI instructions and its format
+ */
+static XQspiPsInstFormat FlashInst[] = {
+ { XQSPIPS_FLASH_OPCODE_WREN, 1, XQSPIPS_TXD_01_OFFSET },
+ { XQSPIPS_FLASH_OPCODE_WRDS, 1, XQSPIPS_TXD_01_OFFSET },
+ { XQSPIPS_FLASH_OPCODE_RDSR1, 2, XQSPIPS_TXD_10_OFFSET },
+ { XQSPIPS_FLASH_OPCODE_RDSR2, 2, XQSPIPS_TXD_10_OFFSET },
+ { XQSPIPS_FLASH_OPCODE_WRSR, 2, XQSPIPS_TXD_10_OFFSET },
+ { XQSPIPS_FLASH_OPCODE_PP, 4, XQSPIPS_TXD_00_OFFSET },
+ { XQSPIPS_FLASH_OPCODE_SE, 4, XQSPIPS_TXD_00_OFFSET },
+ { XQSPIPS_FLASH_OPCODE_BE_32K, 4, XQSPIPS_TXD_00_OFFSET },
+ { XQSPIPS_FLASH_OPCODE_BE_4K, 4, XQSPIPS_TXD_00_OFFSET },
+ { XQSPIPS_FLASH_OPCODE_BE, 1, XQSPIPS_TXD_01_OFFSET },
+ { XQSPIPS_FLASH_OPCODE_ERASE_SUS, 1, XQSPIPS_TXD_01_OFFSET },
+ { XQSPIPS_FLASH_OPCODE_ERASE_RES, 1, XQSPIPS_TXD_01_OFFSET },
+ { XQSPIPS_FLASH_OPCODE_RDID, 4, XQSPIPS_TXD_00_OFFSET },
+ { XQSPIPS_FLASH_OPCODE_NORM_READ, 4, XQSPIPS_TXD_00_OFFSET },
+ { XQSPIPS_FLASH_OPCODE_FAST_READ, 4, XQSPIPS_TXD_00_OFFSET },
+ { XQSPIPS_FLASH_OPCODE_DUAL_READ, 4, XQSPIPS_TXD_00_OFFSET },
+ { XQSPIPS_FLASH_OPCODE_QUAD_READ, 4, XQSPIPS_TXD_00_OFFSET },
+ { XQSPIPS_FLASH_OPCODE_DUAL_IO_READ, 4, XQSPIPS_TXD_00_OFFSET },
+ { XQSPIPS_FLASH_OPCODE_QUAD_IO_READ, 4, XQSPIPS_TXD_00_OFFSET },
+ { XQSPIPS_FLASH_OPCODE_BRWR, 2, XQSPIPS_TXD_10_OFFSET },
+ { XQSPIPS_FLASH_OPCODE_BRRD, 2, XQSPIPS_TXD_10_OFFSET },
+ { XQSPIPS_FLASH_OPCODE_EARWR, 2, XQSPIPS_TXD_10_OFFSET },
+ { XQSPIPS_FLASH_OPCODE_EARRD, 2, XQSPIPS_TXD_10_OFFSET },
+ { XQSPIPS_FLASH_OPCODE_DIE_ERASE, 4, XQSPIPS_TXD_00_OFFSET },
+ { XQSPIPS_FLASH_OPCODE_READ_FLAG_SR, 2, XQSPIPS_TXD_10_OFFSET },
+ { XQSPIPS_FLASH_OPCODE_CLEAR_FLAG_SR, 1, XQSPIPS_TXD_01_OFFSET },
+ /* Add all the instructions supported by the flash device */
+};
+
+/*****************************************************************************/
+/**
+*
+* Initializes a specific XQspiPs instance such that the driver is ready to use.
+*
+* The state of the device after initialization is:
+* - Master mode
+* - Active high clock polarity
+* - Clock phase 0
+* - Baud rate divisor 2
+* - Transfer width 32
+* - Master reference clock = pclk
+* - No chip select active
+* - Manual CS and Manual Start disabled
+*
+* @param InstancePtr is a pointer to the XQspiPs instance.
+* @param ConfigPtr is a reference to a structure containing information
+* about a specific QSPI device. This function initializes an
+* InstancePtr object for a specific device specified by the
+* contents of Config.
+* @param EffectiveAddr is the device base address in the virtual memory
+* address space. The caller is responsible for keeping the address
+* mapping from EffectiveAddr to the device physical base address
+* unchanged once this function is invoked. Unexpected errors may
+* occur if the address mapping changes after this function is
+* called. If address translation is not used, use
+* ConfigPtr->Config.BaseAddress for this device.
+*
+* @return
+* - XST_SUCCESS if successful.
+* - XST_DEVICE_IS_STARTED if the device is already started.
+* It must be stopped to re-initialize.
+*
+* @note None.
+*
+******************************************************************************/
+int XQspiPs_CfgInitialize(XQspiPs *InstancePtr, XQspiPs_Config *ConfigPtr,
+ u32 EffectiveAddr)
+{
+ Xil_AssertNonvoid(InstancePtr != NULL);
+ Xil_AssertNonvoid(ConfigPtr != NULL);
+
+ /*
+ * If the device is busy, disallow the initialize and return a status
+ * indicating it is already started. This allows the user to stop the
+ * device and re-initialize, but prevents a user from inadvertently
+ * initializing. This assumes the busy flag is cleared at startup.
+ */
+ if (InstancePtr->IsBusy == TRUE) {
+ return XST_DEVICE_IS_STARTED;
+ }
+
+ /*
+ * Set some default values.
+ */
+ InstancePtr->IsBusy = FALSE;
+
+ InstancePtr->Config.BaseAddress = EffectiveAddr;
+ InstancePtr->StatusHandler = StubStatusHandler;
+
+ InstancePtr->SendBufferPtr = NULL;
+ InstancePtr->RecvBufferPtr = NULL;
+ InstancePtr->RequestedBytes = 0;
+ InstancePtr->RemainingBytes = 0;
+ InstancePtr->IsReady = XIL_COMPONENT_IS_READY;
+
+ InstancePtr->Config.ConnectionMode = ConfigPtr->ConnectionMode;
+
+ /*
+ * Reset the QSPI device to get it into its initial state. It is
+ * expected that device configuration will take place after this
+ * initialization is done, but before the device is started.
+ */
+ XQspiPs_Reset(InstancePtr);
+
+ return XST_SUCCESS;
+}
+
+/*****************************************************************************/
+/**
+*
+* Resets the QSPI device. Reset must only be called after the driver has been
+* initialized. Any data transfer that is in progress is aborted.
+*
+* The upper layer software is responsible for re-configuring (if necessary)
+* and restarting the QSPI device after the reset.
+*
+* @param InstancePtr is a pointer to the XQspiPs instance.
+*
+* @return None.
+*
+* @note None.
+*
+******************************************************************************/
+void XQspiPs_Reset(XQspiPs *InstancePtr)
+{
+ u32 ConfigReg;
+
+ Xil_AssertVoid(InstancePtr != NULL);
+ Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+ /*
+ * Abort any transfer that is in progress
+ */
+ XQspiPs_Abort(InstancePtr);
+
+ /*
+ * Write default value to configuration register.
+ * Do not modify reserved bits.
+ */
+ ConfigReg = XQspiPs_ReadReg(InstancePtr->Config.BaseAddress,
+ XQSPIPS_CR_OFFSET);
+ ConfigReg |= XQSPIPS_CR_RESET_MASK_SET;
+ ConfigReg &= ~XQSPIPS_CR_RESET_MASK_CLR;
+ XQspiPs_WriteReg(InstancePtr->Config.BaseAddress, XQSPIPS_CR_OFFSET,
+ ConfigReg);
+}
+
+/*****************************************************************************/
+/**
+*
+* Aborts a transfer in progress by disabling the device and flush the RxFIFO.
+* The byte counts are cleared, the busy flag is cleared.
+*
+* @param InstancePtr is a pointer to the XQspiPs instance.
+*
+* @return None.
+*
+* @note
+*
+* This function does a read/modify/write of the config register. The user of
+* this function needs to take care of critical sections.
+*
+******************************************************************************/
+void XQspiPs_Abort(XQspiPs *InstancePtr)
+{
+ u32 ConfigReg;
+ u32 IsLock;
+
+ XQspiPs_Disable(InstancePtr);
+
+ /*
+ * De-assert slave select lines.
+ */
+ ConfigReg = XQspiPs_ReadReg(InstancePtr->Config.BaseAddress,
+ XQSPIPS_CR_OFFSET);
+ ConfigReg |= (XQSPIPS_CR_SSCTRL_MASK | XQSPIPS_CR_SSFORCE_MASK);
+ XQspiPs_WriteReg(InstancePtr->Config.BaseAddress,
+ XQSPIPS_CR_OFFSET, ConfigReg);
+
+ /*
+ * QSPI Software Reset
+ */
+ IsLock = XQspiPs_ReadReg(XPAR_XSLCR_0_BASEADDR, SLCR_LOCKSTA);
+ if (IsLock) {
+ XQspiPs_WriteReg(XPAR_XSLCR_0_BASEADDR, SLCR_UNLOCK,
+ SLCR_UNLOCK_MASK);
+ }
+ XQspiPs_WriteReg(XPAR_XSLCR_0_BASEADDR, LQSPI_RST_CTRL,
+ LQSPI_RST_CTRL_MASK);
+ XQspiPs_WriteReg(XPAR_XSLCR_0_BASEADDR, LQSPI_RST_CTRL, 0x0);
+ if (IsLock) {
+ XQspiPs_WriteReg(XPAR_XSLCR_0_BASEADDR, SLCR_LOCK,
+ SLCR_LOCK_MASK);
+ }
+
+ /*
+ * Set the RX and TX FIFO threshold to reset value (one)
+ */
+ XQspiPs_WriteReg(InstancePtr->Config.BaseAddress,
+ XQSPIPS_RXWR_OFFSET, XQSPIPS_RXWR_RESET_VALUE);
+
+ XQspiPs_WriteReg(InstancePtr->Config.BaseAddress,
+ XQSPIPS_TXWR_OFFSET, XQSPIPS_TXWR_RESET_VALUE);
+
+ InstancePtr->RemainingBytes = 0;
+ InstancePtr->RequestedBytes = 0;
+ InstancePtr->IsBusy = FALSE;
+}
+
+/*****************************************************************************/
+/**
+*
+* Transfers specified data on the QSPI bus. Initiates bus communication and
+* sends/receives data to/from the selected QSPI slave. For every byte sent,
+* a byte is received.
+*
+* The caller has the option of providing two different buffers for send and
+* receive, or one buffer for both send and receive, or no buffer for receive.
+* The receive buffer must be at least as big as the send buffer to prevent
+* unwanted memory writes. This implies that the byte count passed in as an
+* argument must be the smaller of the two buffers if they differ in size.
+* Here are some sample usages:
+* <pre>
+* XQspiPs_Transfer(InstancePtr, SendBuf, RecvBuf, ByteCount)
+* The caller wishes to send and receive, and provides two different
+* buffers for send and receive.
+*
+* XQspiPs_Transfer(InstancePtr, SendBuf, NULL, ByteCount)
+* The caller wishes only to send and does not care about the received
+* data. The driver ignores the received data in this case.
+*
+* XQspiPs_Transfer(InstancePtr, SendBuf, SendBuf, ByteCount)
+* The caller wishes to send and receive, but provides the same buffer
+* for doing both. The driver sends the data and overwrites the send
+* buffer with received data as it transfers the data.
+*
+* XQspiPs_Transfer(InstancePtr, RecvBuf, RecvBuf, ByteCount)
+* The caller wishes to only receive and does not care about sending
+* data. In this case, the caller must still provide a send buffer, but
+* it can be the same as the receive buffer if the caller does not care
+* what it sends. The device must send N bytes of data if it wishes to
+* receive N bytes of data.
+* </pre>
+* Although this function takes entire buffers as arguments, the driver can only
+* transfer a limited number of bytes at a time, limited by the size of the
+* FIFO. A call to this function only starts the transfer, then subsequent
+* transfers of the data is performed by the interrupt service routine until
+* the entire buffer has been transferred. The status callback function is
+* called when the entire buffer has been sent/received.
+*
+* This function is non-blocking. The SetSlaveSelect function must be called
+* prior to this function.
+*
+* @param InstancePtr is a pointer to the XQspiPs instance.
+* @param SendBufPtr is a pointer to a data buffer that needs to be
+* transmitted. This buffer must not be NULL.
+* @param RecvBufPtr is a pointer to a buffer for received data.
+* This argument can be NULL if do not care about receiving.
+* @param ByteCount contains the number of bytes to send/receive.
+* The number of bytes received always equals the number of bytes
+* sent.
+*
+* @return
+* - XST_SUCCESS if the buffers are successfully handed off to the
+* device for transfer.
+* - XST_DEVICE_BUSY indicates that a data transfer is already in
+* progress. This is determined by the driver.
+*
+* @note
+*
+* This function is not thread-safe. The higher layer software must ensure that
+* no two threads are transferring data on the QSPI bus at the same time.
+*
+******************************************************************************/
+s32 XQspiPs_Transfer(XQspiPs *InstancePtr, u8 *SendBufPtr, u8 *RecvBufPtr,
+ u32 ByteCount)
+{
+ u32 StatusReg;
+ u32 ConfigReg;
+ u8 Instruction;
+ u32 Data;
+ unsigned int Index;
+ u8 TransCount = 0;
+ XQspiPsInstFormat *CurrInst;
+ XQspiPsInstFormat NewInst[2];
+ u8 SwitchFlag = 0;
+
+ CurrInst = &NewInst[0];
+
+ /*
+ * The RecvBufPtr argument can be null
+ */
+ Xil_AssertNonvoid(InstancePtr != NULL);
+ Xil_AssertNonvoid(SendBufPtr != NULL);
+ Xil_AssertNonvoid(ByteCount > 0);
+ Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+ /*
+ * Check whether there is another transfer in progress. Not thread-safe.
+ */
+ if (InstancePtr->IsBusy) {
+ return XST_DEVICE_BUSY;
+ }
+
+ /*
+ * Set the busy flag, which will be cleared in the ISR when the
+ * transfer is entirely done.
+ */
+ InstancePtr->IsBusy = TRUE;
+
+ /*
+ * Set up buffer pointers.
+ */
+ InstancePtr->SendBufferPtr = SendBufPtr;
+ InstancePtr->RecvBufferPtr = RecvBufPtr;
+
+ InstancePtr->RequestedBytes = ByteCount;
+ InstancePtr->RemainingBytes = ByteCount;
+
+ /*
+ * The first byte with every chip-select assertion is always
+ * expected to be an instruction for flash interface mode
+ */
+ Instruction = *InstancePtr->SendBufferPtr;
+
+ for (Index = 0 ; Index < ARRAY_SIZE(FlashInst); Index++) {
+ if (Instruction == FlashInst[Index].OpCode) {
+ break;
+ }
+ }
+
+ /*
+ * Set the RX FIFO threshold
+ */
+ XQspiPs_WriteReg(InstancePtr->Config.BaseAddress,
+ XQSPIPS_RXWR_OFFSET, XQSPIPS_RXFIFO_THRESHOLD_OPT);
+
+ /*
+ * If the slave select is "Forced" or under manual control,
+ * set the slave select now, before beginning the transfer.
+ */
+ if (XQspiPs_IsManualChipSelect(InstancePtr)) {
+ ConfigReg = XQspiPs_ReadReg(InstancePtr->Config.BaseAddress,
+ XQSPIPS_CR_OFFSET);
+ ConfigReg &= ~XQSPIPS_CR_SSCTRL_MASK;
+ XQspiPs_WriteReg(InstancePtr->Config.BaseAddress,
+ XQSPIPS_CR_OFFSET,
+ ConfigReg);
+ }
+
+ /*
+ * Enable the device.
+ */
+ XQspiPs_Enable(InstancePtr);
+
+ /*
+ * Clear all the interrupts.
+ */
+ XQspiPs_WriteReg(InstancePtr->Config.BaseAddress, XQSPIPS_SR_OFFSET,
+ XQSPIPS_IXR_WR_TO_CLR_MASK);
+
+ if (Index < ARRAY_SIZE(FlashInst)) {
+ CurrInst = &FlashInst[Index];
+ /*
+ * Check for WRSR instruction which has different size for
+ * Spansion (3 bytes) and Micron (2 bytes)
+ */
+ if ((CurrInst->OpCode == XQSPIPS_FLASH_OPCODE_WRSR) &&
+ (ByteCount == 3)) {
+ CurrInst->InstSize = 3;
+ CurrInst->TxOffset = XQSPIPS_TXD_11_OFFSET;
+ }
+ }
+
+ /*
+ * If instruction not present in table
+ */
+ if (Index == ARRAY_SIZE(FlashInst)) {
+ /*
+ * Assign current instruction, size and TXD register to be used
+ * The InstSize mentioned in case of instructions greater than
+ * 4 bytes is not the actual size, but is indicative of
+ * the TXD register used.
+ * The remaining bytes of the instruction will be transmitted
+ * through TXD0 below.
+ */
+ switch (ByteCount%4) {
+ case XQSPIPS_SIZE_ONE:
+ CurrInst->OpCode = Instruction;
+ CurrInst->InstSize = XQSPIPS_SIZE_ONE;
+ CurrInst->TxOffset = XQSPIPS_TXD_01_OFFSET;
+ if (ByteCount > 4) {
+ SwitchFlag = 1;
+ }
+ break;
+ case XQSPIPS_SIZE_TWO:
+ CurrInst->OpCode = Instruction;
+ CurrInst->InstSize = XQSPIPS_SIZE_TWO;
+ CurrInst->TxOffset = XQSPIPS_TXD_10_OFFSET;
+ if (ByteCount > 4) {
+ SwitchFlag = 1;
+ }
+ break;
+ case XQSPIPS_SIZE_THREE:
+ CurrInst->OpCode = Instruction;
+ CurrInst->InstSize = XQSPIPS_SIZE_THREE;
+ CurrInst->TxOffset = XQSPIPS_TXD_11_OFFSET;
+ if (ByteCount > 4) {
+ SwitchFlag = 1;
+ }
+ break;
+ default:
+ CurrInst->OpCode = Instruction;
+ CurrInst->InstSize = XQSPIPS_SIZE_FOUR;
+ CurrInst->TxOffset = XQSPIPS_TXD_00_OFFSET;
+ break;
+ }
+ }
+
+ /*
+ * If the instruction size in not 4 bytes then the data received needs
+ * to be shifted
+ */
+ if (CurrInst->InstSize != 4) {
+ InstancePtr->ShiftReadData = 1;
+ } else {
+ InstancePtr->ShiftReadData = 0;
+ }
+
+ /* Get the complete command (flash inst + address/data) */
+ Data = *((u32 *)InstancePtr->SendBufferPtr);
+ InstancePtr->SendBufferPtr += CurrInst->InstSize;
+ InstancePtr->RemainingBytes -= CurrInst->InstSize;
+ if (InstancePtr->RemainingBytes < 0) {
+ InstancePtr->RemainingBytes = 0;
+ }
+
+ /* Write the command to the FIFO */
+ XQspiPs_WriteReg(InstancePtr->Config.BaseAddress,
+ CurrInst->TxOffset, Data);
+ TransCount++;
+
+ /*
+ * If switching from TXD1/2/3 to TXD0, then start transfer and
+ * check for FIFO empty
+ */
+ if (SwitchFlag == 1) {
+ SwitchFlag = 0;
+ /*
+ * If, in Manual Start mode, start the transfer.
+ */
+ if (XQspiPs_IsManualStart(InstancePtr)) {
+ ConfigReg = XQspiPs_ReadReg(
+ InstancePtr->Config.BaseAddress,
+ XQSPIPS_CR_OFFSET);
+ ConfigReg |= XQSPIPS_CR_MANSTRT_MASK;
+ XQspiPs_WriteReg(InstancePtr->Config.BaseAddress,
+ XQSPIPS_CR_OFFSET, ConfigReg);
+ }
+ /*
+ * Wait for the transfer to finish by polling Tx fifo status.
+ */
+ do {
+ StatusReg = XQspiPs_ReadReg(
+ InstancePtr->Config.BaseAddress,
+ XQSPIPS_SR_OFFSET);
+ } while ((StatusReg & XQSPIPS_IXR_TXOW_MASK) == 0);
+
+ }
+
+ /*
+ * Fill the Tx FIFO with as many bytes as it takes (or as many as
+ * we have to send).
+ */
+ while ((InstancePtr->RemainingBytes > 0) &&
+ (TransCount < XQSPIPS_FIFO_DEPTH)) {
+ /*
+ * In case of Write fill the Tx FIFO with data to be transmitted.
+ * In case of Read fill the Tx FIFO with DUMMY bytes.
+ */
+ if (!InstancePtr->RecvBufferPtr) {
+ XQspiPs_WriteReg(InstancePtr->Config.BaseAddress,
+ XQSPIPS_TXD_00_OFFSET,
+ *((u32 *)InstancePtr->SendBufferPtr));
+ InstancePtr->SendBufferPtr += 4;
+ } else {
+ XQspiPs_WriteReg(InstancePtr->Config.BaseAddress,
+ XQSPIPS_TXD_00_OFFSET,
+ XQSPIPS_DUMMY_TX_DATA);
+ }
+ InstancePtr->RemainingBytes -= 4;
+ if (InstancePtr->RemainingBytes < 0) {
+ InstancePtr->RemainingBytes = 0;
+ }
+ TransCount++;
+ }
+
+ /*
+ * Enable QSPI interrupts (connecting to the interrupt controller and
+ * enabling interrupts should have been done by the caller).
+ */
+ XQspiPs_WriteReg(InstancePtr->Config.BaseAddress,
+ XQSPIPS_IER_OFFSET, XQSPIPS_IXR_RXNEMPTY_MASK |
+ XQSPIPS_IXR_TXOW_MASK | XQSPIPS_IXR_RXOVR_MASK |
+ XQSPIPS_IXR_TXUF_MASK);
+
+ /*
+ * If, in Manual Start mode, Start the transfer.
+ */
+ if (XQspiPs_IsManualStart(InstancePtr)) {
+ ConfigReg = XQspiPs_ReadReg(InstancePtr->Config.BaseAddress,
+ XQSPIPS_CR_OFFSET);
+ ConfigReg |= XQSPIPS_CR_MANSTRT_MASK;
+ XQspiPs_WriteReg(InstancePtr->Config.BaseAddress,
+ XQSPIPS_CR_OFFSET, ConfigReg);
+ }
+
+ return XST_SUCCESS;
+}
+
+/*****************************************************************************/
+/**
+* Transfers specified data on the QSPI bus in polled mode.
+*
+* The caller has the option of providing two different buffers for send and
+* receive, or one buffer for both send and receive, or no buffer for receive.
+* The receive buffer must be at least as big as the send buffer to prevent
+* unwanted memory writes. This implies that the byte count passed in as an
+* argument must be the smaller of the two buffers if they differ in size.
+* Here are some sample usages:
+* <pre>
+* XQspiPs_PolledTransfer(InstancePtr, SendBuf, RecvBuf, ByteCount)
+* The caller wishes to send and receive, and provides two different
+* buffers for send and receive.
+*
+* XQspiPs_PolledTransfer(InstancePtr, SendBuf, NULL, ByteCount)
+* The caller wishes only to send and does not care about the received
+* data. The driver ignores the received data in this case.
+*
+* XQspiPs_PolledTransfer(InstancePtr, SendBuf, SendBuf, ByteCount)
+* The caller wishes to send and receive, but provides the same buffer
+* for doing both. The driver sends the data and overwrites the send
+* buffer with received data as it transfers the data.
+*
+* XQspiPs_PolledTransfer(InstancePtr, RecvBuf, RecvBuf, ByteCount)
+* The caller wishes to only receive and does not care about sending
+* data. In this case, the caller must still provide a send buffer, but
+* it can be the same as the receive buffer if the caller does not care
+* what it sends. The device must send N bytes of data if it wishes to
+* receive N bytes of data.
+*
+* </pre>
+*
+* @param InstancePtr is a pointer to the XQspiPs instance.
+* @param SendBufPtr is a pointer to a data buffer that needs to be
+* transmitted. This buffer must not be NULL.
+* @param RecvBufPtr is a pointer to a buffer for received data.
+* This argument can be NULL if do not care about receiving.
+* @param ByteCount contains the number of bytes to send/receive.
+* The number of bytes received always equals the number of bytes
+* sent.
+* @return
+* - XST_SUCCESS if the buffers are successfully handed off to the
+* device for transfer.
+* - XST_DEVICE_BUSY indicates that a data transfer is already in
+* progress. This is determined by the driver.
+*
+* @note
+*
+* This function is not thread-safe. The higher layer software must ensure that
+* no two threads are transferring data on the QSPI bus at the same time.
+*
+******************************************************************************/
+s32 XQspiPs_PolledTransfer(XQspiPs *InstancePtr, u8 *SendBufPtr,
+ u8 *RecvBufPtr, u32 ByteCount)
+{
+ u32 StatusReg;
+ u32 ConfigReg;
+ u8 Instruction;
+ u32 Data;
+ u8 TransCount;
+ unsigned int Index;
+ XQspiPsInstFormat *CurrInst;
+ XQspiPsInstFormat NewInst[2];
+ u8 SwitchFlag = 0;
+ u8 IsManualStart = FALSE;
+ u32 RxCount = 0;
+
+ CurrInst = &NewInst[0];
+ /*
+ * The RecvBufPtr argument can be NULL.
+ */
+ Xil_AssertNonvoid(InstancePtr != NULL);
+ Xil_AssertNonvoid(SendBufPtr != NULL);
+ Xil_AssertNonvoid(ByteCount > 0);
+ Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+ /*
+ * Check whether there is another transfer in progress. Not thread-safe.
+ */
+ if (InstancePtr->IsBusy) {
+ return XST_DEVICE_BUSY;
+ }
+
+ /*
+ * Set the busy flag, which will be cleared when the transfer is
+ * entirely done.
+ */
+ InstancePtr->IsBusy = TRUE;
+
+ /*
+ * Set up buffer pointers.
+ */
+ InstancePtr->SendBufferPtr = SendBufPtr;
+ InstancePtr->RecvBufferPtr = RecvBufPtr;
+
+ InstancePtr->RequestedBytes = ByteCount;
+ InstancePtr->RemainingBytes = ByteCount;
+
+ /*
+ * The first byte with every chip-select assertion is always
+ * expected to be an instruction for flash interface mode
+ */
+ Instruction = *InstancePtr->SendBufferPtr;
+
+ for (Index = 0 ; Index < ARRAY_SIZE(FlashInst); Index++) {
+ if (Instruction == FlashInst[Index].OpCode) {
+ break;
+ }
+ }
+
+ /*
+ * Set the RX FIFO threshold
+ */
+ XQspiPs_WriteReg(InstancePtr->Config.BaseAddress,
+ XQSPIPS_RXWR_OFFSET, XQSPIPS_RXFIFO_THRESHOLD_OPT);
+
+ /*
+ * If the slave select is "Forced" or under manual control,
+ * set the slave select now, before beginning the transfer.
+ */
+ if (XQspiPs_IsManualChipSelect(InstancePtr)) {
+ ConfigReg = XQspiPs_ReadReg(InstancePtr->Config.BaseAddress,
+ XQSPIPS_CR_OFFSET);
+ ConfigReg &= ~XQSPIPS_CR_SSCTRL_MASK;
+ XQspiPs_WriteReg(InstancePtr->Config.BaseAddress,
+ XQSPIPS_CR_OFFSET,
+ ConfigReg);
+ }
+
+ /*
+ * Enable the device.
+ */
+ XQspiPs_Enable(InstancePtr);
+
+ if (Index < ARRAY_SIZE(FlashInst)) {
+
+ CurrInst = &FlashInst[Index];
+ /*
+ * Check for WRSR instruction which has different size for
+ * Spansion (3 bytes) and Micron (2 bytes)
+ */
+ if ((CurrInst->OpCode == XQSPIPS_FLASH_OPCODE_WRSR) &&
+ (ByteCount == 3)) {
+ CurrInst->InstSize = 3;
+ CurrInst->TxOffset = XQSPIPS_TXD_11_OFFSET;
+ }
+ }
+
+ /*
+ * If instruction not present in table
+ */
+ if (Index == ARRAY_SIZE(FlashInst)) {
+ /*
+ * Assign current instruction, size and TXD register to be used.
+ * The InstSize mentioned in case of instructions greater than 4 bytes
+ * is not the actual size, but is indicative of the TXD register used.
+ * The remaining bytes of the instruction will be transmitted
+ * through TXD0 below.
+ */
+ switch (ByteCount % 4) {
+ case XQSPIPS_SIZE_ONE:
+ CurrInst->OpCode = Instruction;
+ CurrInst->InstSize = XQSPIPS_SIZE_ONE;
+ CurrInst->TxOffset = XQSPIPS_TXD_01_OFFSET;
+ if (ByteCount > 4) {
+ SwitchFlag = 1;
+ }
+ break;
+ case XQSPIPS_SIZE_TWO:
+ CurrInst->OpCode = Instruction;
+ CurrInst->InstSize = XQSPIPS_SIZE_TWO;
+ CurrInst->TxOffset = XQSPIPS_TXD_10_OFFSET;
+ if (ByteCount > 4) {
+ SwitchFlag = 1;
+ }
+ break;
+ case XQSPIPS_SIZE_THREE:
+ CurrInst->OpCode = Instruction;
+ CurrInst->InstSize = XQSPIPS_SIZE_THREE;
+ CurrInst->TxOffset = XQSPIPS_TXD_11_OFFSET;
+ if (ByteCount > 4) {
+ SwitchFlag = 1;
+ }
+ break;
+ default:
+ CurrInst->OpCode = Instruction;
+ CurrInst->InstSize = XQSPIPS_SIZE_FOUR;
+ CurrInst->TxOffset = XQSPIPS_TXD_00_OFFSET;
+ break;
+ }
+ }
+
+ /*
+ * If the instruction size in not 4 bytes then the data received needs
+ * to be shifted
+ */
+ if (CurrInst->InstSize != 4) {
+ InstancePtr->ShiftReadData = 1;
+ } else {
+ InstancePtr->ShiftReadData = 0;
+ }
+ TransCount = 0;
+ /* Get the complete command (flash inst + address/data) */
+ Data = *((u32 *)InstancePtr->SendBufferPtr);
+ InstancePtr->SendBufferPtr += CurrInst->InstSize;
+ InstancePtr->RemainingBytes -= CurrInst->InstSize;
+ if (InstancePtr->RemainingBytes < 0) {
+ InstancePtr->RemainingBytes = 0;
+ }
+
+ /* Write the command to the FIFO */
+ XQspiPs_WriteReg(InstancePtr->Config.BaseAddress,
+ CurrInst->TxOffset, Data);
+ ++TransCount;
+
+ /*
+ * If switching from TXD1/2/3 to TXD0, then start transfer and
+ * check for FIFO empty
+ */
+ if (SwitchFlag == 1) {
+ SwitchFlag = 0;
+ /*
+ * If, in Manual Start mode, start the transfer.
+ */
+ if (XQspiPs_IsManualStart(InstancePtr)) {
+ ConfigReg = XQspiPs_ReadReg(
+ InstancePtr->Config.BaseAddress,
+ XQSPIPS_CR_OFFSET);
+ ConfigReg |= XQSPIPS_CR_MANSTRT_MASK;
+ XQspiPs_WriteReg(InstancePtr->Config.BaseAddress,
+ XQSPIPS_CR_OFFSET, ConfigReg);
+ }
+ /*
+ * Wait for the transfer to finish by polling Tx fifo status.
+ */
+ do {
+ StatusReg = XQspiPs_ReadReg(
+ InstancePtr->Config.BaseAddress,
+ XQSPIPS_SR_OFFSET);
+ } while ((StatusReg & XQSPIPS_IXR_TXOW_MASK) == 0);
+
+ }
+
+ /*
+ * Check if manual start is selected and store it in a
+ * local variable for reference. This is to avoid reading
+ * the config register every time.
+ */
+ IsManualStart = XQspiPs_IsManualStart(InstancePtr);
+
+ /*
+ * Fill the DTR/FIFO with as many bytes as it will take (or as
+ * many as we have to send).
+ */
+ while ((InstancePtr->RemainingBytes > 0) &&
+ (TransCount < XQSPIPS_FIFO_DEPTH)) {
+ /*
+ * In case of Write fill the Tx FIFO with data to be transmitted.
+ * In case of Read fill the Tx FIFO with DUMMY bytes.
+ */
+ if (!InstancePtr->RecvBufferPtr) {
+ XQspiPs_WriteReg(InstancePtr->Config.BaseAddress,
+ XQSPIPS_TXD_00_OFFSET,
+ *((u32 *)InstancePtr->SendBufferPtr));
+ InstancePtr->SendBufferPtr += 4;
+ } else {
+ XQspiPs_WriteReg(InstancePtr->Config.BaseAddress,
+ XQSPIPS_TXD_00_OFFSET,
+ XQSPIPS_DUMMY_TX_DATA);
+ }
+ InstancePtr->RemainingBytes -= 4;
+ if (InstancePtr->RemainingBytes < 0) {
+ InstancePtr->RemainingBytes = 0;
+ }
+ ++TransCount;
+ }
+
+ while ((InstancePtr->RemainingBytes > 0) ||
+ (InstancePtr->RequestedBytes > 0)) {
+
+ /*
+ * Fill the TX FIFO with RX threshold no. of entries (or as
+ * many as we have to send, in case that's less).
+ */
+ while ((InstancePtr->RemainingBytes > 0) &&
+ (TransCount < XQSPIPS_RXFIFO_THRESHOLD_OPT)) {
+ /*
+ * In case of Write fill the Tx FIFO with data to be transmitted.
+ * In case of Read fill the Tx FIFO with DUMMY bytes.
+ */
+ if (!InstancePtr->RecvBufferPtr) {
+ XQspiPs_WriteReg(InstancePtr->Config.BaseAddress,
+ XQSPIPS_TXD_00_OFFSET,
+ *((u32 *)InstancePtr->SendBufferPtr));
+ InstancePtr->SendBufferPtr += 4;
+ } else {
+ XQspiPs_WriteReg(InstancePtr->Config.BaseAddress,
+ XQSPIPS_TXD_00_OFFSET,
+ XQSPIPS_DUMMY_TX_DATA);
+ }
+ InstancePtr->RemainingBytes -= 4;
+ if (InstancePtr->RemainingBytes < 0) {
+ InstancePtr->RemainingBytes = 0;
+ }
+ ++TransCount;
+ }
+
+ /*
+ * If, in Manual Start mode, start the transfer.
+ */
+ if (IsManualStart == TRUE) {
+ ConfigReg = XQspiPs_ReadReg(
+ InstancePtr->Config.BaseAddress,
+ XQSPIPS_CR_OFFSET);
+ ConfigReg |= XQSPIPS_CR_MANSTRT_MASK;
+ XQspiPs_WriteReg(InstancePtr->Config.BaseAddress,
+ XQSPIPS_CR_OFFSET, ConfigReg);
+ }
+
+ /*
+ * Reset TransCount - this is only used to fill TX FIFO
+ * in the above loop;
+ * RxCount is used to keep track of data received
+ */
+ TransCount = 0;
+
+ /*
+ * Wait for RX FIFO to reach threshold (or)
+ * TX FIFO to become empty.
+ * The latter check is required for
+ * small transfers (<32 words) and
+ * when the last chunk in a large data transfer is < 32 words.
+ */
+
+ do {
+ StatusReg = XQspiPs_ReadReg(
+ InstancePtr->Config.BaseAddress,
+ XQSPIPS_SR_OFFSET);
+ } while (((StatusReg & XQSPIPS_IXR_TXOW_MASK) == 0) &&
+ ((StatusReg & XQSPIPS_IXR_RXNEMPTY_MASK) == 0));
+
+ /*
+ * A transmit has just completed. Process received data
+ * and check for more data to transmit.
+ * First get the data received as a result of the
+ * transmit that just completed. Receive data based on the
+ * count obtained while filling tx fifo. Always get
+ * the received data, but only fill the receive
+ * buffer if it points to something (the upper layer
+ * software may not care to receive data).
+ */
+ while ((InstancePtr->RequestedBytes > 0) &&
+ (RxCount < XQSPIPS_RXFIFO_THRESHOLD_OPT)) {
+ u32 Data;
+
+ RxCount++;
+
+ if (InstancePtr->RecvBufferPtr != NULL) {
+ if (InstancePtr->RequestedBytes < 4) {
+ Data = XQspiPs_ReadReg(InstancePtr->Config.BaseAddress,
+ XQSPIPS_RXD_OFFSET);
+ XQspiPs_GetReadData(InstancePtr, Data,
+ InstancePtr->RequestedBytes);
+ } else {
+ (*(u32 *)InstancePtr->RecvBufferPtr) =
+ XQspiPs_ReadReg(InstancePtr->Config.BaseAddress,
+ XQSPIPS_RXD_OFFSET);
+ InstancePtr->RecvBufferPtr += 4;
+ InstancePtr->RequestedBytes -= 4;
+ if (InstancePtr->RequestedBytes < 0) {
+ InstancePtr->RequestedBytes = 0;
+ }
+ }
+ } else {
+ Data = XQspiPs_ReadReg(InstancePtr->Config.BaseAddress,
+ XQSPIPS_RXD_OFFSET);
+ InstancePtr->RequestedBytes -= 4;
+ }
+ }
+ RxCount = 0;
+ }
+
+ /*
+ * If the Slave select lines are being manually controlled, disable
+ * them because the transfer is complete.
+ */
+ if (XQspiPs_IsManualChipSelect(InstancePtr)) {
+ ConfigReg = XQspiPs_ReadReg(InstancePtr->Config.BaseAddress,
+ XQSPIPS_CR_OFFSET);
+ ConfigReg |= XQSPIPS_CR_SSCTRL_MASK;
+ XQspiPs_WriteReg(InstancePtr->Config.BaseAddress,
+ XQSPIPS_CR_OFFSET, ConfigReg);
+ }
+
+ /*
+ * Clear the busy flag.
+ */
+ InstancePtr->IsBusy = FALSE;
+
+ /*
+ * Disable the device.
+ */
+ XQspiPs_Disable(InstancePtr);
+
+ /*
+ * Reset the RX FIFO threshold to one
+ */
+ XQspiPs_WriteReg(InstancePtr->Config.BaseAddress,
+ XQSPIPS_RXWR_OFFSET, XQSPIPS_RXWR_RESET_VALUE);
+
+ return XST_SUCCESS;
+}
+
+/*****************************************************************************/
+/**
+*
+* Read the flash in Linear QSPI mode.
+*
+* @param InstancePtr is a pointer to the XQspiPs instance.
+* @param RecvBufPtr is a pointer to a buffer for received data.
+* @param Address is the starting address within the flash from
+* from where data needs to be read.
+* @param ByteCount contains the number of bytes to receive.
+*
+* @return
+* - XST_SUCCESS if read is performed
+* - XST_FAILURE if Linear mode is not set
+*
+* @note None.
+*
+*
+******************************************************************************/
+int XQspiPs_LqspiRead(XQspiPs *InstancePtr, u8 *RecvBufPtr,
+ u32 Address, unsigned ByteCount)
+{
+ int Status = (int)XST_SUCCESS;
+ Xil_AssertNonvoid(InstancePtr != NULL);
+ Xil_AssertNonvoid(RecvBufPtr != NULL);
+ Xil_AssertNonvoid(ByteCount > 0);
+ Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+#ifndef XPAR_PS7_QSPI_LINEAR_0_S_AXI_BASEADDR
+#define XPAR_PS7_QSPI_LINEAR_0_S_AXI_BASEADDR 0xFC000000
+#endif
+ /*
+ * Enable the controller
+ */
+ XQspiPs_Enable(InstancePtr);
+
+ if (XQspiPs_GetLqspiConfigReg(InstancePtr) &
+ XQSPIPS_LQSPI_CR_LINEAR_MASK) {
+ memcpy((void *)RecvBufPtr,
+ (const void *)(XPAR_PS7_QSPI_LINEAR_0_S_AXI_BASEADDR +
+ Address),
+ (size_t)ByteCount);
+ Status = (int)XST_SUCCESS;
+ } else {
+ Status = (int)XST_FAILURE;
+ }
+
+ /*
+ * Disable the controller
+ */
+ XQspiPs_Disable(InstancePtr);
+
+ return Status;
+}
+
+/*****************************************************************************/
+/**
+*
+* Selects the slave with which the master communicates.
+*
+* The user is not allowed to select the slave while a transfer is in progress.
+*
+* @param InstancePtr is a pointer to the XQspiPs instance.
+*
+* @return
+* - XST_SUCCESS if the slave is selected or deselected
+* successfully.
+* - XST_DEVICE_BUSY if a transfer is in progress, slave cannot be
+* changed.
+*
+* @note
+*
+* This function only sets the slave which will be selected when a transfer
+* occurs. The slave is not selected when the QSPI is idle.
+*
+******************************************************************************/
+int XQspiPs_SetSlaveSelect(XQspiPs *InstancePtr)
+{
+ u32 ConfigReg;
+
+ Xil_AssertNonvoid(InstancePtr != NULL);
+ Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+ /*
+ * Do not allow the slave select to change while a transfer is in
+ * progress. Not thread-safe.
+ */
+ if (InstancePtr->IsBusy) {
+ return XST_DEVICE_BUSY;
+ }
+
+ /*
+ * Select the slave
+ */
+ ConfigReg = XQspiPs_ReadReg(InstancePtr->Config.BaseAddress,
+ XQSPIPS_CR_OFFSET);
+ ConfigReg &= ~XQSPIPS_CR_SSCTRL_MASK;
+ XQspiPs_WriteReg(InstancePtr->Config.BaseAddress,
+ XQSPIPS_CR_OFFSET, ConfigReg);
+
+ return XST_SUCCESS;
+}
+
+/*****************************************************************************/
+/**
+*
+* Sets the status callback function, the status handler, which the driver
+* calls when it encounters conditions that should be reported to upper
+* layer software. The handler executes in an interrupt context, so it must
+* minimize the amount of processing performed. One of the following status
+* events is passed to the status handler.
+*
+* <pre>
+*
+* XST_SPI_TRANSFER_DONE The requested data transfer is done
+*
+* XST_SPI_TRANSMIT_UNDERRUN As a slave device, the master clocked data
+* but there were none available in the transmit
+* register/FIFO. This typically means the slave
+* application did not issue a transfer request
+* fast enough, or the processor/driver could not
+* fill the transmit register/FIFO fast enough.
+*
+* XST_SPI_RECEIVE_OVERRUN The QSPI device lost data. Data was received
+* but the receive data register/FIFO was full.
+*
+* </pre>
+* @param InstancePtr is a pointer to the XQspiPs instance.
+* @param CallBackRef is the upper layer callback reference passed back
+* when the callback function is invoked.
+* @param FuncPtr is the pointer to the callback function.
+*
+* @return None.
+*
+* @note
+*
+* The handler is called within interrupt context, so it should do its work
+* quickly and queue potentially time-consuming work to a task-level thread.
+*
+******************************************************************************/
+void XQspiPs_SetStatusHandler(XQspiPs *InstancePtr, void *CallBackRef,
+ XQspiPs_StatusHandler FuncPtr)
+{
+ Xil_AssertVoid(InstancePtr != NULL);
+ Xil_AssertVoid(FuncPtr != NULL);
+ Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+ InstancePtr->StatusHandler = FuncPtr;
+ InstancePtr->StatusRef = CallBackRef;
+}
+
+/*****************************************************************************/
+/**
+*
+* This is a stub for the status callback. The stub is here in case the upper
+* layers forget to set the handler.
+*
+* @param CallBackRef is a pointer to the upper layer callback reference
+* @param StatusEvent is the event that just occurred.
+* @param ByteCount is the number of bytes transferred up until the event
+* occurred.
+*
+* @return None.
+*
+* @note None.
+*
+******************************************************************************/
+static void StubStatusHandler(void *CallBackRef, u32 StatusEvent,
+ unsigned ByteCount)
+{
+ (void) CallBackRef;
+ (void) StatusEvent;
+ (void) ByteCount;
+
+ Xil_AssertVoidAlways();
+}
+
+/*****************************************************************************/
+/**
+*
+* The interrupt handler for QSPI interrupts. This function must be connected
+* by the user to an interrupt controller.
+*
+* The interrupts that are handled are:
+*
+*
+* - Data Transmit Register (FIFO) Empty. This interrupt is generated when the
+* transmit register or FIFO is empty. The driver uses this interrupt during a
+* transmission to continually send/receive data until the transfer is done.
+*
+* - Data Transmit Register (FIFO) Underflow. This interrupt is generated when
+* the QSPI device, when configured as a slave, attempts to read an empty
+* DTR/FIFO. An empty DTR/FIFO usually means that software is not giving the
+* device data in a timely manner. No action is taken by the driver other than
+* to inform the upper layer software of the error.
+*
+* - Data Receive Register (FIFO) Overflow. This interrupt is generated when the
+* QSPI device attempts to write a received byte to an already full DRR/FIFO.
+* A full DRR/FIFO usually means software is not emptying the data in a timely
+* manner. No action is taken by the driver other than to inform the upper
+* layer software of the error.
+*
+* @param InstancePtr is a pointer to the XQspiPs instance.
+*
+* @return None.
+*
+* @note
+*
+* The slave select register is being set to deselect the slave when a transfer
+* is complete.
+*
+******************************************************************************/
+void XQspiPs_InterruptHandler(void *InstancePtr)
+{
+ XQspiPs *QspiPtr = (XQspiPs *)InstancePtr;
+ u32 IntrStatus;
+ u32 ConfigReg;
+ u32 Data;
+ u32 TransCount;
+ u32 Count = 0;
+ unsigned BytesDone; /* Number of bytes done so far. */
+
+ Xil_AssertVoid(InstancePtr != NULL);
+ Xil_AssertVoid(QspiPtr->IsReady == XIL_COMPONENT_IS_READY);
+
+ /*
+ * Immediately clear the interrupts in case the ISR causes another
+ * interrupt to be generated. If we clear at the end of the ISR,
+ * we may miss newly generated interrupts. This occurs because we
+ * transmit from within the ISR, which could potentially cause another
+ * TX_EMPTY interrupt.
+ */
+ IntrStatus = XQspiPs_ReadReg(QspiPtr->Config.BaseAddress,
+ XQSPIPS_SR_OFFSET);
+ XQspiPs_WriteReg(QspiPtr->Config.BaseAddress, XQSPIPS_SR_OFFSET,
+ (IntrStatus & XQSPIPS_IXR_WR_TO_CLR_MASK));
+ XQspiPs_WriteReg(QspiPtr->Config.BaseAddress, XQSPIPS_IDR_OFFSET,
+ XQSPIPS_IXR_TXOW_MASK | XQSPIPS_IXR_RXNEMPTY_MASK |
+ XQSPIPS_IXR_RXOVR_MASK | XQSPIPS_IXR_TXUF_MASK);
+
+ if ((IntrStatus & XQSPIPS_IXR_TXOW_MASK) ||
+ (IntrStatus & XQSPIPS_IXR_RXNEMPTY_MASK)) {
+
+ /*
+ * Rx FIFO has just reached threshold no. of entries.
+ * Read threshold no. of entries from RX FIFO
+ * Another possibility of entering this loop is when
+ * the last byte has been transmitted and TX FIFO is empty,
+ * in which case, read all the data from RX FIFO.
+ * Always get the received data, but only fill the
+ * receive buffer if it is not null (it can be null when
+ * the device does not care to receive data).
+ */
+ TransCount = QspiPtr->RequestedBytes - QspiPtr->RemainingBytes;
+ if (TransCount % 4) {
+ TransCount = TransCount/4 + 1;
+ } else {
+ TransCount = TransCount/4;
+ }
+
+ while ((Count < TransCount) &&
+ (Count < XQSPIPS_RXFIFO_THRESHOLD_OPT)) {
+
+ if (QspiPtr->RecvBufferPtr != NULL) {
+ if (QspiPtr->RequestedBytes < 4) {
+ Data = XQspiPs_ReadReg(QspiPtr->Config.BaseAddress,
+ XQSPIPS_RXD_OFFSET);
+ XQspiPs_GetReadData(QspiPtr, Data,
+ QspiPtr->RequestedBytes);
+ } else {
+ (*(u32 *)QspiPtr->RecvBufferPtr) =
+ XQspiPs_ReadReg(QspiPtr->Config.BaseAddress,
+ XQSPIPS_RXD_OFFSET);
+ QspiPtr->RecvBufferPtr += 4;
+ QspiPtr->RequestedBytes -= 4;
+ if (QspiPtr->RequestedBytes < 0) {
+ QspiPtr->RequestedBytes = 0;
+ }
+ }
+ } else {
+ XQspiPs_ReadReg(QspiPtr->Config.BaseAddress,
+ XQSPIPS_RXD_OFFSET);
+ QspiPtr->RequestedBytes -= 4;
+ if (QspiPtr->RequestedBytes < 0) {
+ QspiPtr->RequestedBytes = 0;
+ }
+
+ }
+ Count++;
+ }
+ Count = 0;
+ /*
+ * Interrupt asserted as TX_OW got asserted
+ * See if there is more data to send.
+ * Fill TX FIFO with RX threshold no. of entries or
+ * remaining entries (in case that is less than threshold)
+ */
+ while ((QspiPtr->RemainingBytes > 0) &&
+ (Count < XQSPIPS_RXFIFO_THRESHOLD_OPT)) {
+ /*
+ * Send more data.
+ * In case of Write fill the Tx FIFO with data to be transmitted.
+ * In case of Read fill the Tx FIFO with DUMMY bytes.
+ */
+ if (!QspiPtr->RecvBufferPtr) {
+ XQspiPs_WriteReg(QspiPtr->Config.BaseAddress,
+ XQSPIPS_TXD_00_OFFSET,
+ *((u32 *)QspiPtr->SendBufferPtr));
+ QspiPtr->SendBufferPtr += 4;
+ } else {
+ XQspiPs_WriteReg(QspiPtr->Config.BaseAddress,
+ XQSPIPS_TXD_00_OFFSET,
+ XQSPIPS_DUMMY_TX_DATA);
+ }
+ QspiPtr->RemainingBytes -= 4;
+ if (QspiPtr->RemainingBytes < 0) {
+ QspiPtr->RemainingBytes = 0;
+ }
+
+ Count++;
+ }
+
+ if ((QspiPtr->RemainingBytes == 0) &&
+ (QspiPtr->RequestedBytes == 0)) {
+ /*
+ * No more data to send. Disable the interrupt
+ * and inform the upper layer software that the
+ * transfer is done. The interrupt will be re-enabled
+ * when another transfer is initiated.
+ */
+ XQspiPs_WriteReg(QspiPtr->Config.BaseAddress,
+ XQSPIPS_IDR_OFFSET,
+ XQSPIPS_IXR_RXNEMPTY_MASK |
+ XQSPIPS_IXR_TXOW_MASK |
+ XQSPIPS_IXR_RXOVR_MASK |
+ XQSPIPS_IXR_TXUF_MASK);
+
+ /*
+ * If the Slave select is being manually controlled,
+ * disable it because the transfer is complete.
+ */
+ if (XQspiPs_IsManualChipSelect(InstancePtr)) {
+ ConfigReg = XQspiPs_ReadReg(
+ QspiPtr->Config.BaseAddress,
+ XQSPIPS_CR_OFFSET);
+ ConfigReg |= XQSPIPS_CR_SSCTRL_MASK;
+ XQspiPs_WriteReg(QspiPtr->Config.BaseAddress,
+ XQSPIPS_CR_OFFSET,
+ ConfigReg);
+ }
+
+ /*
+ * Clear the busy flag.
+ */
+ QspiPtr->IsBusy = FALSE;
+
+ /*
+ * Disable the device.
+ */
+ XQspiPs_Disable(QspiPtr);
+
+ /*
+ * Reset the RX FIFO threshold to one
+ */
+ XQspiPs_WriteReg(QspiPtr->Config.BaseAddress,
+ XQSPIPS_RXWR_OFFSET, XQSPIPS_RXWR_RESET_VALUE);
+
+ QspiPtr->StatusHandler(QspiPtr->StatusRef,
+ XST_SPI_TRANSFER_DONE,
+ QspiPtr->RequestedBytes);
+ } else {
+ /*
+ * Enable the TXOW interrupt.
+ */
+ XQspiPs_WriteReg(QspiPtr->Config.BaseAddress,
+ XQSPIPS_IER_OFFSET,
+ XQSPIPS_IXR_RXNEMPTY_MASK |
+ XQSPIPS_IXR_TXOW_MASK |
+ XQSPIPS_IXR_RXOVR_MASK |
+ XQSPIPS_IXR_TXUF_MASK);
+ /*
+ * If, in Manual Start mode, start the transfer.
+ */
+ if (XQspiPs_IsManualStart(QspiPtr)) {
+ ConfigReg = XQspiPs_ReadReg(
+ QspiPtr->Config.BaseAddress,
+ XQSPIPS_CR_OFFSET);
+ ConfigReg |= XQSPIPS_CR_MANSTRT_MASK;
+ XQspiPs_WriteReg(
+ QspiPtr->Config.BaseAddress,
+ XQSPIPS_CR_OFFSET, ConfigReg);
+ }
+ }
+ }
+
+ /*
+ * Check for overflow and underflow errors.
+ */
+ if (IntrStatus & XQSPIPS_IXR_RXOVR_MASK) {
+ BytesDone = QspiPtr->RequestedBytes - QspiPtr->RemainingBytes;
+ QspiPtr->IsBusy = FALSE;
+
+ /*
+ * If the Slave select lines is being manually controlled,
+ * disable it because the transfer is complete.
+ */
+ if (XQspiPs_IsManualChipSelect(InstancePtr)) {
+ ConfigReg = XQspiPs_ReadReg(
+ QspiPtr->Config.BaseAddress,
+ XQSPIPS_CR_OFFSET);
+ ConfigReg |= XQSPIPS_CR_SSCTRL_MASK;
+ XQspiPs_WriteReg(QspiPtr->Config.BaseAddress,
+ XQSPIPS_CR_OFFSET, ConfigReg);
+ }
+
+ /*
+ * Disable the device.
+ */
+ XQspiPs_Disable(QspiPtr);
+
+ /*
+ * Reset the RX FIFO threshold to one
+ */
+ XQspiPs_WriteReg(QspiPtr->Config.BaseAddress,
+ XQSPIPS_RXWR_OFFSET, XQSPIPS_RXWR_RESET_VALUE);
+
+ QspiPtr->StatusHandler(QspiPtr->StatusRef,
+ XST_SPI_RECEIVE_OVERRUN, BytesDone);
+ }
+
+ if (IntrStatus & XQSPIPS_IXR_TXUF_MASK) {
+ BytesDone = QspiPtr->RequestedBytes - QspiPtr->RemainingBytes;
+
+ QspiPtr->IsBusy = FALSE;
+ /*
+ * If the Slave select lines is being manually controlled,
+ * disable it because the transfer is complete.
+ */
+ if (XQspiPs_IsManualChipSelect(InstancePtr)) {
+ ConfigReg = XQspiPs_ReadReg(
+ QspiPtr->Config.BaseAddress,
+ XQSPIPS_CR_OFFSET);
+ ConfigReg |= XQSPIPS_CR_SSCTRL_MASK;
+ XQspiPs_WriteReg(QspiPtr->Config.BaseAddress,
+ XQSPIPS_CR_OFFSET, ConfigReg);
+ }
+
+ /*
+ * Disable the device.
+ */
+ XQspiPs_Disable(QspiPtr);
+
+ /*
+ * Reset the RX FIFO threshold to one
+ */
+ XQspiPs_WriteReg(QspiPtr->Config.BaseAddress,
+ XQSPIPS_RXWR_OFFSET, XQSPIPS_RXWR_RESET_VALUE);
+
+ QspiPtr->StatusHandler(QspiPtr->StatusRef,
+ XST_SPI_TRANSMIT_UNDERRUN, BytesDone);
+ }
+}
+
+
+/*****************************************************************************/
+/**
+*
+* Copies data from Data to the Receive buffer.
+*
+* @param InstancePtr is a pointer to the XQspiPs instance.
+* @param Data is the data which needs to be copied to the Rx buffer.
+* @param Size is the number of bytes to be copied to the Receive buffer.
+*
+* @return None.
+*
+* @note None.
+*
+******************************************************************************/
+static void XQspiPs_GetReadData(XQspiPs *InstancePtr, u32 Data, u8 Size)
+{
+ u8 DataByte3;
+
+ if (InstancePtr->RecvBufferPtr) {
+ switch (Size) {
+ case 1:
+ if (InstancePtr->ShiftReadData == 1) {
+ *((u8 *)InstancePtr->RecvBufferPtr) =
+ ((Data & 0xFF000000) >> 24);
+ } else {
+ *((u8 *)InstancePtr->RecvBufferPtr) =
+ (Data & 0xFF);
+ }
+ InstancePtr->RecvBufferPtr += 1;
+ break;
+ case 2:
+ if (InstancePtr->ShiftReadData == 1) {
+ *((u16 *)InstancePtr->RecvBufferPtr) =
+ ((Data >> 16) & 0xFF00) |
+ ((Data >> 8) & 0xFF);
+ } else {
+ *((u16 *)InstancePtr->RecvBufferPtr) =
+ (Data & 0xFFFF);
+ }
+ InstancePtr->RecvBufferPtr += 2;
+ break;
+ case 3:
+ if (InstancePtr->ShiftReadData == 1) {
+ *((u16 *)InstancePtr->RecvBufferPtr) =
+ ((Data & 0x00FFFF00) >> 8);
+ InstancePtr->RecvBufferPtr += 2;
+ DataByte3 = ((Data & 0xFF000000) >> 24);
+ *((u8 *)InstancePtr->RecvBufferPtr) = DataByte3;
+ } else {
+ *((u16 *)InstancePtr->RecvBufferPtr) =
+ (Data & 0xFFFF);
+ InstancePtr->RecvBufferPtr += 2;
+ DataByte3 = ((Data & 0x00FF0000) >> 16);
+ *((u8 *)InstancePtr->RecvBufferPtr) = DataByte3;
+ }
+ InstancePtr->RecvBufferPtr += 1;
+ break;
+ default:
+ /* This will never execute */
+ break;
+ }
+ }
+ InstancePtr->ShiftReadData = 0;
+ InstancePtr->RequestedBytes -= Size;
+ if (InstancePtr->RequestedBytes < 0) {
+ InstancePtr->RequestedBytes = 0;
+ }
+}
+/** @} */
diff --git a/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/qspips_v3_6/src/xqspips.h b/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/qspips_v3_6/src/xqspips.h
new file mode 100644
index 0000000..43b6ffe
--- /dev/null
+++ b/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/qspips_v3_6/src/xqspips.h
@@ -0,0 +1,802 @@
+/******************************************************************************
+*
+* Copyright (C) 2010 - 2019 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+* THE SOFTWARE.
+*
+*
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xqspips.h
+* @addtogroup qspips_v3_6
+* @{
+* @details
+*
+* This file contains the implementation of the XQspiPs driver. It supports only
+* master mode. User documentation for the driver functions is contained in this
+* file in the form of comment blocks at the front of each function.
+*
+* A QSPI device connects to an QSPI bus through a 4-wire serial interface.
+* The QSPI bus is a full-duplex, synchronous bus that facilitates communication
+* between one master and one slave. The device is always full-duplex,
+* which means that for every byte sent, one is received, and vice-versa.
+* The master controls the clock, so it can regulate when it wants to
+* send or receive data. The slave is under control of the master, it must
+* respond quickly since it has no control of the clock and must send/receive
+* data as fast or as slow as the master does.
+*
+* <b> Linear Mode </b>
+* The Linear Quad-SPI Controller extends the existing Quad-SPI Controller�s
+* functionality by adding a linear addressing scheme that allows the SPI flash
+* memory subsystem to behave like a typical ROM device. The new feature hides
+* the normal SPI protocol from a master reading from the SPI flash memory. The
+* feature improves both the user friendliness and the overall read memory
+* throughput over that of the current Quad-SPI Controller by lessening the
+* amount of software overheads required and by the use of the faster AXI
+* interface.
+*
+* <b>Initialization & Configuration</b>
+*
+* The XQspiPs_Config structure is used by the driver to configure itself. This
+* configuration structure is typically created by the tool-chain based on HW
+* build properties.
+*
+* To support multiple runtime loading and initialization strategies employed by
+* various operating systems, the driver instance can be initialized in the
+* following way:
+* - XQspiPs_LookupConfig(DeviceId) - Use the device identifier to find
+* static configuration structure defined in xqspips_g.c. This is setup
+* by the tools. For some operating systems the config structure will be
+* initialized by the software and this call is not needed.
+* - XQspiPs_CfgInitialize(InstancePtr, CfgPtr, EffectiveAddr) - Uses a
+* configuration structure provided by the caller. If running in a system
+* with address translation, the provided virtual memory base address
+* replaces the physical address present in the configuration structure.
+*
+* <b>Multiple Masters</b>
+*
+* More than one master can exist, but arbitration is the responsibility of
+* the higher layer software. The device driver does not perform any type of
+* arbitration.
+*
+* <b>Modes of Operation</b>
+*
+* There are four modes to perform a data transfer and the selection of a mode
+* is based on Chip Select(CS) and Start. These two options individually, can
+* be controlled either by software(Manual) or hardware(Auto).
+* - Auto CS: Chip select is automatically asserted as soon as the first word
+* is written into the TXFIFO and de asserted when the TXFIFO becomes
+* empty
+* - Manual CS: Software must assert and de assert CS.
+* - Auto Start: Data transmission starts as soon as there is data in the
+* TXFIFO and stalls when the TXFIFO is empty
+* - Manual Start: Software must start data transmission at the beginning of
+* the transaction or whenever the TXFIFO has become empty
+*
+* The preferred combination is Manual CS and Auto Start.
+* In this combination, the software asserts CS before loading any data into
+* TXFIFO. In Auto Start mode, whenever data is in TXFIFO, controller sends it
+* out until TXFIFO becomes empty. The software reads the RXFIFO whenever the
+* data is available. If no further data, software disables CS.
+*
+* Risks/challenges of other combinations:
+* - Manual CS and Manual Start: Manual Start bit should be set after each
+* TXFIFO write otherwise there could be a race condition where the TXFIFO
+* becomes empty before the new word is written. In that case the
+* transmission stops.
+* - Auto CS with Manual or Auto Start: It is very difficult for software to
+* keep the TXFIFO filled. Whenever the TXFIFO runs empty, CS is de asserted.
+* This results in a single transaction to be split into multiple pieces each
+* with its own chip select. This will result in garbage data to be sent.
+*
+* <b>Interrupts</b>
+*
+* The user must connect the interrupt handler of the driver,
+* XQspiPs_InterruptHandler, to an interrupt system such that it will be
+* called when an interrupt occurs. This function does not save and restore
+* the processor context such that the user must provide this processing.
+*
+* The driver handles the following interrupts:
+* - Data Transmit Register/FIFO Underflow
+* - Data Receive Register/FIFO Not Empty
+* - Data Transmit Register/FIFO Overwater
+* - Data Receive Register/FIFO Overrun
+*
+* The Data Transmit Register/FIFO Overwater interrupt -- indicates that the
+* QSPI device has transmitted the data available to transmit, and now its data
+* register and FIFO is ready to accept more data. The driver uses this
+* interrupt to indicate progress while sending data. The driver may have
+* more data to send, in which case the data transmit register and FIFO is
+* filled for subsequent transmission. When this interrupt arrives and all
+* the data has been sent, the driver invokes the status callback with a
+* value of XST_SPI_TRANSFER_DONE to inform the upper layer software that
+* all data has been sent.
+*
+* The Data Transmit Register/FIFO Underflow interrupt -- indicates that,
+* as slave, the QSPI device was required to transmit but there was no data
+* available to transmit in the transmit register (or FIFO). This may not
+* be an error if the master is not expecting data. But in the case where
+* the master is expecting data, this serves as a notification of such a
+* condition. The driver reports this condition to the upper layer
+* software through the status handler.
+*
+* The Data Receive Register/FIFO Overrun interrupt -- indicates that the QSPI
+* device received data and subsequently dropped the data because the data
+* receive register and FIFO was full. The driver reports this condition to the
+* upper layer software through the status handler. This likely indicates a
+* problem with the higher layer protocol, or a problem with the slave
+* performance.
+*
+*
+* <b>Polled Operation</b>
+*
+* Transfer in polled mode is supported through a separate interface function
+* XQspiPs_PolledTransfer(). Unlike the transfer function in the interrupt mode,
+* this function blocks until all data has been sent/received.
+*
+* <b>Device Busy</b>
+*
+* Some operations are disallowed when the device is busy. The driver tracks
+* whether a device is busy. The device is considered busy when a data transfer
+* request is outstanding, and is considered not busy only when that transfer
+* completes (or is aborted with a mode fault error).
+*
+* <b>Device Configuration</b>
+*
+* The device can be configured in various ways during the FPGA implementation
+* process. Configuration parameters are stored in the xqspips_g.c file or
+* passed in via XQspiPs_CfgInitialize(). A table is defined where each entry
+* contains configuration information for an QSPI device, including the base
+* address for the device.
+*
+* <b>RTOS Independence</b>
+*
+* This driver is intended to be RTOS and processor independent. It works with
+* physical addresses only. Any needs for dynamic memory management, threads or
+* thread mutual exclusion, virtual memory, or cache control must be satisfied
+* by the layer above this driver.
+*
+* NOTE: This driver was always tested with endianness set to little-endian.
+*
+* <pre>
+* MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ----- --- -------- -----------------------------------------------
+* 1.00a sdm 11/25/10 First release, based on the PS SPI driver...
+* 1.01a sdm 11/22/11 Added TCL file for generating QSPI parameters
+* in xparameters.h
+* 2.00a kka 07/25/12 Added a few register defines for CR 670297
+* Removed code related to mode fault for CR 671468
+* The XQspiPs_SetSlaveSelect has been modified to remove
+* the argument of the slave select as the QSPI controller
+* only supports one slave.
+* XQspiPs_GetSlaveSelect API has been removed
+* Added a flag ShiftReadData to the instance structure
+*. and is used in the XQspiPs_GetReadData API.
+* The ShiftReadData Flag indicates whether the data
+* read from the Rx FIFO needs to be shifted
+* in cases where the data is less than 4 bytes
+* Removed the selection for the following options:
+* Master mode (XQSPIPS_MASTER_OPTION) and
+* Flash interface mode (XQSPIPS_FLASH_MODE_OPTION) option
+* as the QSPI driver supports the Master mode
+* and Flash Interface mode and doesnot support
+* Slave mode or the legacy mode.
+* Modified the XQspiPs_PolledTransfer and XQspiPs_Transfer
+* APIs so that the last argument (IsInst) specifying whether
+* it is instruction or data has been removed. The first byte
+* in the SendBufPtr argument of these APIs specify the
+* instruction to be sent to the Flash Device.
+* This version of the driver fixes CRs 670197/663787/
+* 670297/671468.
+* Added the option for setting the Holdb_dr bit in the
+* configuration options, XQSPIPS_HOLD_B_DRIVE_OPTION
+* is the option to be used for setting this bit in the
+* configuration register.
+* The XQspiPs_PolledTransfer function has been updated
+* to fill the data to fifo depth.
+* 2.01a sg 02/03/13 Added flash opcodes for DUAL_IO_READ,QUAD_IO_READ.
+* Added macros for Set/Get Rx Watermark. Changed QSPI
+* Enable/Disable macro argument from BaseAddress to
+* Instance Pointer. Added DelayNss argument to SetDelays
+* and GetDelays API's.
+* Created macros XQspiPs_IsManualStart and
+* XQspiPs_IsManualChipSelect.
+* Changed QSPI transfer logic for polled and interrupt
+* modes to be based on filled tx fifo count and receive
+* based on it. RXNEMPTY interrupt is not used.
+* Added assertions to XQspiPs_LqspiRead function.
+* SetDelays and GetDelays API's include DelayNss parameter.
+* Added defines for DelayNss,Rx Watermark,Interrupts
+* which need write to clear. Removed Read zeros mask from
+* LQSPI Config register. Renamed Fixed burst error to
+* data FSM error in LQSPI Status register.
+*
+* 2.02a hk 05/07/13 Added ConnectionMode to config structure.
+* Corresponds to C_QSPI_MODE - 0:Single, 1:Stacked, 2:Parallel
+* Added enable and disable to the XQspiPs_LqspiRead() function
+* Removed XQspi_Reset() in Set_Options() function when
+* LQSPI_MODE_OPTION is set.
+* Added instructions for bank selection, die erase and
+* flag status register to the flash instruction table
+* Handling for instructions not in flash instruction
+* table added. Checking for Tx FIFO empty when switching from
+* TXD1/2/3 to TXD0 added. If WRSR instruction is sent with
+* byte count 3 (spansion), instruction size and TXD register
+* changed accordingly. CR# 712502 and 703869.
+* Added prefix to constant definitions for ConnectionMode
+* Added (#ifdef linear base address) in the Linear read function.
+* Changed XPAR_XQSPIPS_0_LINEAR_BASEADDR to
+* XPAR_PS7_QSPI_LINEAR_0_S_AXI_BASEADDR in
+* XQspiPs_LqspiRead function. Fix for CR#718141.
+*
+* 2.03a hk 09/17/13 Modified polled and interrupt transfers to make use of
+* thresholds. This is to improve performance.
+* Added API's for QSPI reset and
+* linear mode initialization for boot.
+* Added RX and TX threshold reset to one in XQspiPs_Abort.
+* Added RX threshold reset(1) after transfer in polled and
+* interrupt transfers. Made changes to make sure threshold
+* change is done only when no transfer is in progress.
+* Updated linear init API for parallel and stacked modes.
+* CR#737760.
+* 3.1 hk 08/13/14 When writing to the configuration register, set/reset
+* required bits leaving reserved bits untouched. CR# 796813.
+* 3.2 sk 02/05/15 Add SLCR reset in abort function as a workaround because
+* controller does not update FIFO status flags as expected
+* when thresholds are used.
+* 3.3 sk 11/07/15 Modified the API prototypes according to MISRAC standards
+* to remove compilation warnings. CR# 868893.
+* ms 03/17/17 Added readme.txt file in examples folder for doxygen
+* generation.
+* ms 04/05/17 Modified Comment lines in functions of qspips
+* examples to recognize it as documentation block
+* and modified filename tag in
+* xqspips_dual_flash_stack_lqspi_example.c to include it in
+* doxygen examples.
+* 3.4 nsk 31/07/17 Added QSPI_BUS_WIDTH parameter in xparameters.h file
+* 3.5 tjs 08/21/18 Fixed compilation warnings for the ARMCC.
+* 3.5 tjs 07/16/18 Added support for low density ISSI flash parts.
+* 3.6 akm 03/28/19 Fixed memory leak issue while reading from qspi.(CR#1016357)
+* 3.6 akm 04/15/19 Modified FlashQuadEnable, FlashWrie and FlashErase APIs,
+* to wait for the on going operation to complete before
+* performing the next operation.
+* 3.6 akm 04/15/19 Modified the mask in XQspiPs_GetReadData() API to retrieve
+* configuration register values of both the Flashes in dual
+* parellel connection.
+*
+* </pre>
+*
+******************************************************************************/
+#ifndef XQSPIPS_H /* prevent circular inclusions */
+#define XQSPIPS_H /* by using protection macros */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/***************************** Include Files *********************************/
+
+#include "xstatus.h"
+#include "xqspips_hw.h"
+#include <string.h>
+
+/************************** Constant Definitions *****************************/
+
+/** @name Configuration options
+ *
+ * The following options are supported to enable/disable certain features of
+ * an QSPI device. Each of the options is a bit mask, so more than one may be
+ * specified.
+ *
+ *
+ * The <b>Active Low Clock option</b> configures the device's clock polarity.
+ * Setting this option means the clock is active low and the SCK signal idles
+ * high. By default, the clock is active high and SCK idles low.
+ *
+ * The <b>Clock Phase option</b> configures the QSPI device for one of two
+ * transfer formats. A clock phase of 0, the default, means data is valid on
+ * the first SCK edge (rising or falling) after the slave select (SS) signal
+ * has been asserted. A clock phase of 1 means data is valid on the second SCK
+ * edge (rising or falling) after SS has been asserted.
+ *
+ *
+ * The <b>QSPI Force Slave Select option</b> is used to enable manual control of
+ * the slave select signal.
+ * 0: The SPI_SS signal is controlled by the QSPI controller during
+ * transfers. (Default)
+ * 1: The SPI_SS signal is forced active (driven low) regardless of any
+ * transfers in progress.
+ *
+ * NOTE: The driver will handle setting and clearing the Slave Select when
+ * the user sets the "FORCE_SSELECT_OPTION". Using this option will allow the
+ * QSPI clock to be set to a faster speed. If the QSPI clock is too fast, the
+ * processor cannot empty and refill the FIFOs before the TX FIFO is empty
+ * When the QSPI hardware is controlling the Slave Select signals, this
+ * will cause slave to be de-selected and terminate the transfer.
+ *
+ * The <b>Manual Start option</b> is used to enable manual control of
+ * the Start command to perform data transfer.
+ * 0: The Start command is controlled by the QSPI controller during
+ * transfers(Default). Data transmission starts as soon as there is data in
+ * the TXFIFO and stalls when the TXFIFO is empty
+ * 1: The Start command must be issued by software to perform data transfer.
+ * Bit 15 of Configuration register is used to issue Start command. This bit
+ * must be set whenever TXFIFO is filled with new data.
+ *
+ * NOTE: The driver will set the Manual Start Enable bit in Configuration
+ * Register, if Manual Start option is selected. Software will issue
+ * Manual Start command whenever TXFIFO is filled with data. When there is
+ * no further data, driver will clear the Manual Start Enable bit.
+ *
+ * @{
+ */
+#define XQSPIPS_CLK_ACTIVE_LOW_OPTION 0x2 /**< Active Low Clock option */
+#define XQSPIPS_CLK_PHASE_1_OPTION 0x4 /**< Clock Phase one option */
+#define XQSPIPS_FORCE_SSELECT_OPTION 0x10 /**< Force Slave Select */
+#define XQSPIPS_MANUAL_START_OPTION 0x20 /**< Manual Start enable */
+#define XQSPIPS_LQSPI_MODE_OPTION 0x80 /**< Linear QPSI mode */
+#define XQSPIPS_HOLD_B_DRIVE_OPTION 0x100 /**< Drive HOLD_B Pin */
+/*@}*/
+
+
+/** @name QSPI Clock Prescaler options
+ * The QSPI Clock Prescaler Configuration bits are used to program master mode
+ * bit rate. The bit rate can be programmed in divide-by-two decrements from
+ * pclk/2 to pclk/256.
+ *
+ * @{
+ */
+#define XQSPIPS_CLK_PRESCALE_2 0x00 /**< PCLK/2 Prescaler */
+#define XQSPIPS_CLK_PRESCALE_4 0x01 /**< PCLK/4 Prescaler */
+#define XQSPIPS_CLK_PRESCALE_8 0x02 /**< PCLK/8 Prescaler */
+#define XQSPIPS_CLK_PRESCALE_16 0x03 /**< PCLK/16 Prescaler */
+#define XQSPIPS_CLK_PRESCALE_32 0x04 /**< PCLK/32 Prescaler */
+#define XQSPIPS_CLK_PRESCALE_64 0x05 /**< PCLK/64 Prescaler */
+#define XQSPIPS_CLK_PRESCALE_128 0x06 /**< PCLK/128 Prescaler */
+#define XQSPIPS_CLK_PRESCALE_256 0x07 /**< PCLK/256 Prescaler */
+
+/*@}*/
+
+
+/** @name Callback events
+ *
+ * These constants specify the handler events that are passed to
+ * a handler from the driver. These constants are not bit masks such that
+ * only one will be passed at a time to the handler.
+ *
+ * @{
+ */
+#define XQSPIPS_EVENT_TRANSFER_DONE 2 /**< Transfer done */
+#define XQSPIPS_EVENT_TRANSMIT_UNDERRUN 3 /**< TX FIFO empty */
+#define XQSPIPS_EVENT_RECEIVE_OVERRUN 4 /**< Receive data loss because
+ * RX FIFO full
+ */
+/*@}*/
+
+/** @name Flash commands
+ *
+ * The following constants define most of the commands supported by flash
+ * devices. Users can add more commands supported by the flash devices
+ *
+ * @{
+ */
+#define XQSPIPS_FLASH_OPCODE_WRSR 0x01 /* Write status register */
+#define XQSPIPS_FLASH_OPCODE_PP 0x02 /* Page program */
+#define XQSPIPS_FLASH_OPCODE_NORM_READ 0x03 /* Normal read data bytes */
+#define XQSPIPS_FLASH_OPCODE_WRDS 0x04 /* Write disable */
+#define XQSPIPS_FLASH_OPCODE_RDSR1 0x05 /* Read status register 1 */
+#define XQSPIPS_FLASH_OPCODE_WREN 0x06 /* Write enable */
+#define XQSPIPS_FLASH_OPCODE_FAST_READ 0x0B /* Fast read data bytes */
+#define XQSPIPS_FLASH_OPCODE_BE_4K 0x20 /* Erase 4KiB block */
+#define XQSPIPS_FLASH_OPCODE_RDSR2 0x35 /* Read status register 2 */
+#define XQSPIPS_FLASH_OPCODE_DUAL_READ 0x3B /* Dual read data bytes */
+#define XQSPIPS_FLASH_OPCODE_BE_32K 0x52 /* Erase 32KiB block */
+#define XQSPIPS_FLASH_OPCODE_QUAD_READ 0x6B /* Quad read data bytes */
+#define XQSPIPS_FLASH_OPCODE_ERASE_SUS 0x75 /* Erase suspend */
+#define XQSPIPS_FLASH_OPCODE_ERASE_RES 0x7A /* Erase resume */
+#define XQSPIPS_FLASH_OPCODE_RDID 0x9F /* Read JEDEC ID */
+#define XQSPIPS_FLASH_OPCODE_BE 0xC7 /* Erase whole flash block */
+#define XQSPIPS_FLASH_OPCODE_SE 0xD8 /* Sector erase (usually 64KB)*/
+#define XQSPIPS_FLASH_OPCODE_DUAL_IO_READ 0xBB /* Read data using Dual I/O */
+#define XQSPIPS_FLASH_OPCODE_QUAD_IO_READ 0xEB /* Read data using Quad I/O */
+#define XQSPIPS_FLASH_OPCODE_BRWR 0x17 /* Bank Register Write */
+#define XQSPIPS_FLASH_OPCODE_BRRD 0x16 /* Bank Register Read */
+/* Extende Address Register Write - Micron's equivalent of Bank Register */
+#define XQSPIPS_FLASH_OPCODE_EARWR 0xC5
+/* Extende Address Register Read - Micron's equivalent of Bank Register */
+#define XQSPIPS_FLASH_OPCODE_EARRD 0xC8
+#define XQSPIPS_FLASH_OPCODE_DIE_ERASE 0xC4
+#define XQSPIPS_FLASH_OPCODE_READ_FLAG_SR 0x70
+#define XQSPIPS_FLASH_OPCODE_CLEAR_FLAG_SR 0x50
+#define XQSPIPS_FLASH_OPCODE_READ_LOCK_REG 0xE8 /* Lock Reg Read */
+#define XQSPIPS_FLASH_OPCODE_WRITE_LOCK_REG 0xE5 /* Lock Reg Write */
+
+/*@}*/
+
+/** @name Instruction size
+ *
+ * The following constants define numbers 1 to 4.
+ * Used to identify whether TXD0,1,2 or 3 is to be used.
+ *
+ * @{
+ */
+#define XQSPIPS_SIZE_ONE 1
+#define XQSPIPS_SIZE_TWO 2
+#define XQSPIPS_SIZE_THREE 3
+#define XQSPIPS_SIZE_FOUR 4
+
+/*@}*/
+
+/** @name ConnectionMode
+ *
+ * The following constants are the possible values of ConnectionMode in
+ * Config structure.
+ *
+ * @{
+ */
+#define XQSPIPS_CONNECTION_MODE_SINGLE 0
+#define XQSPIPS_CONNECTION_MODE_STACKED 1
+#define XQSPIPS_CONNECTION_MODE_PARALLEL 2
+
+/*@}*/
+
+/** @name FIFO threshold value
+ *
+ * This is the Rx FIFO threshold (in words) that was found to be most
+ * optimal in terms of performance
+ *
+ * @{
+ */
+#define XQSPIPS_RXFIFO_THRESHOLD_OPT 32
+
+/*@}*/
+
+/**************************** Type Definitions *******************************/
+/**
+ * The handler data type allows the user to define a callback function to
+ * handle the asynchronous processing for the QSPI device. The application
+ * using this driver is expected to define a handler of this type to support
+ * interrupt driven mode. The handler executes in an interrupt context, so
+ * only minimal processing should be performed.
+ *
+ * @param CallBackRef is the callback reference passed in by the upper
+ * layer when setting the callback functions, and passed back to
+ * the upper layer when the callback is invoked. Its type is
+ * not important to the driver, so it is a void pointer.
+ * @param StatusEvent holds one or more status events that have occurred.
+ * See the XQspiPs_SetStatusHandler() for details on the status
+ * events that can be passed in the callback.
+ * @param ByteCount indicates how many bytes of data were successfully
+ * transferred. This may be less than the number of bytes
+ * requested if the status event indicates an error.
+ */
+typedef void (*XQspiPs_StatusHandler) (void *CallBackRef, u32 StatusEvent,
+ unsigned ByteCount);
+
+/**
+ * This typedef contains configuration information for the device.
+ */
+typedef struct {
+ u16 DeviceId; /**< Unique ID of device */
+ u32 BaseAddress; /**< Base address of the device */
+ u32 InputClockHz; /**< Input clock frequency */
+ u8 ConnectionMode; /**< Single, Stacked and Parallel mode */
+} XQspiPs_Config;
+
+/**
+ * The XQspiPs driver instance data. The user is required to allocate a
+ * variable of this type for every QSPI device in the system. A pointer
+ * to a variable of this type is then passed to the driver API functions.
+ */
+typedef struct {
+ XQspiPs_Config Config; /**< Configuration structure */
+ u32 IsReady; /**< Device is initialized and ready */
+
+ u8 *SendBufferPtr; /**< Buffer to send (state) */
+ u8 *RecvBufferPtr; /**< Buffer to receive (state) */
+ int RequestedBytes; /**< Number of bytes to transfer (state) */
+ int RemainingBytes; /**< Number of bytes left to transfer(state) */
+ u32 IsBusy; /**< A transfer is in progress (state) */
+ XQspiPs_StatusHandler StatusHandler;
+ void *StatusRef; /**< Callback reference for status handler */
+ u32 ShiftReadData; /**< Flag to indicate whether the data
+ * read from the Rx FIFO needs to be shifted
+ * in cases where the data is less than 4
+ * bytes
+ */
+} XQspiPs;
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/****************************************************************************/
+/*
+*
+* Check in OptionsTable if Manual Start Option is enabled or disabled.
+*
+* @param InstancePtr is a pointer to the XQspiPs instance.
+*
+* @return
+* - TRUE if option is set
+* - FALSE if option is not set
+*
+* @note C-Style signature:
+* u8 XQspiPs_IsManualStart(XQspiPs *InstancePtr);
+*
+*****************************************************************************/
+#define XQspiPs_IsManualStart(InstancePtr) \
+ ((XQspiPs_GetOptions(InstancePtr) & \
+ XQSPIPS_MANUAL_START_OPTION) ? TRUE : FALSE)
+
+/****************************************************************************/
+/*
+*
+* Check in OptionsTable if Manual Chip Select Option is enabled or disabled.
+*
+* @param InstancePtr is a pointer to the XSpiPs instance.
+*
+* @return
+* - TRUE if option is set
+* - FALSE if option is not set
+*
+* @note C-Style signature:
+* u8 XQspiPs_IsManualChipSelect(XQspiPs *InstancePtr);
+*
+*****************************************************************************/
+#define XQspiPs_IsManualChipSelect(InstancePtr) \
+ ((XQspiPs_GetOptions(InstancePtr) & \
+ XQSPIPS_FORCE_SSELECT_OPTION) ? TRUE : FALSE)
+
+/****************************************************************************/
+/**
+*
+* Set the contents of the slave idle count register.
+*
+* @param InstancePtr is a pointer to the XQspiPs instance.
+* @param RegisterValue is the value to be written, valid values are
+* 0-255.
+*
+* @return None
+*
+* @note C-Style signature:
+* void XQspiPs_SetSlaveIdle(XQspiPs *InstancePtr,
+* u32 RegisterValue)
+*
+*****************************************************************************/
+#define XQspiPs_SetSlaveIdle(InstancePtr, RegisterValue) \
+ XQspiPs_Out32(((InstancePtr)->Config.BaseAddress) + \
+ XQSPIPS_SICR_OFFSET, (RegisterValue))
+
+/****************************************************************************/
+/**
+*
+* Get the contents of the slave idle count register. Use the XQSPIPS_SICR_*
+* constants defined in xqspips_hw.h to interpret the bit-mask returned.
+*
+* @param InstancePtr is a pointer to the XQspiPs instance.
+*
+* @return An 8-bit value representing Slave Idle Count.
+*
+* @note C-Style signature:
+* u32 XQspiPs_GetSlaveIdle(XQspiPs *InstancePtr)
+*
+*****************************************************************************/
+#define XQspiPs_GetSlaveIdle(InstancePtr) \
+ XQspiPs_In32(((InstancePtr)->Config.BaseAddress) + \
+ XQSPIPS_SICR_OFFSET)
+
+/****************************************************************************/
+/**
+*
+* Set the contents of the transmit FIFO watermark register.
+*
+* @param InstancePtr is a pointer to the XQspiPs instance.
+* @param RegisterValue is the value to be written, valid values are 1-63.
+*
+* @return None.
+*
+* @note C-Style signature:
+* void XQspiPs_SetTXWatermark(XQspiPs *InstancePtr,
+* u32 RegisterValue)
+*
+*****************************************************************************/
+#define XQspiPs_SetTXWatermark(InstancePtr, RegisterValue) \
+ XQspiPs_Out32(((InstancePtr)->Config.BaseAddress) + \
+ XQSPIPS_TXWR_OFFSET, (RegisterValue))
+
+/****************************************************************************/
+/**
+*
+* Get the contents of the transmit FIFO watermark register.
+* Valid values are in the range 1-63.
+*
+* @param InstancePtr is a pointer to the XQspiPs instance.
+*
+* @return A 6-bit value representing Tx Watermark level.
+*
+* @note C-Style signature:
+* u32 XQspiPs_GetTXWatermark(XQspiPs *InstancePtr)
+*
+*****************************************************************************/
+#define XQspiPs_GetTXWatermark(InstancePtr) \
+ XQspiPs_In32((InstancePtr->Config.BaseAddress) + XQSPIPS_TXWR_OFFSET)
+
+/****************************************************************************/
+/**
+*
+* Set the contents of the receive FIFO watermark register.
+*
+* @param InstancePtr is a pointer to the XQspiPs instance.
+* @param RegisterValue is the value to be written, valid values are 1-63.
+*
+* @return None.
+*
+* @note C-Style signature:
+* void XQspiPs_SetRXWatermark(XQspiPs *InstancePtr,
+* u32 RegisterValue)
+*
+*****************************************************************************/
+#define XQspiPs_SetRXWatermark(InstancePtr, RegisterValue) \
+ XQspiPs_Out32(((InstancePtr)->Config.BaseAddress) + \
+ XQSPIPS_RXWR_OFFSET, (RegisterValue))
+
+/****************************************************************************/
+/**
+*
+* Get the contents of the receive FIFO watermark register.
+* Valid values are in the range 1-63.
+*
+* @param InstancePtr is a pointer to the XQspiPs instance.
+*
+* @return A 6-bit value representing Rx Watermark level.
+*
+* @note C-Style signature:
+* u32 XQspiPs_GetRXWatermark(XQspiPs *InstancePtr)
+*
+*****************************************************************************/
+#define XQspiPs_GetRXWatermark(InstancePtr) \
+ XQspiPs_In32((InstancePtr->Config.BaseAddress) + XQSPIPS_RXWR_OFFSET)
+
+/****************************************************************************/
+/**
+*
+* Enable the device and uninhibit master transactions.
+*
+* @param InstancePtr is a pointer to the XQspiPs instance.
+*
+* @return None.
+*
+* @note C-Style signature:
+* void XQspiPs_Enable(XQspiPs *InstancePtr)
+*
+*****************************************************************************/
+#define XQspiPs_Enable(InstancePtr) \
+ XQspiPs_Out32((InstancePtr->Config.BaseAddress) + XQSPIPS_ER_OFFSET, \
+ XQSPIPS_ER_ENABLE_MASK)
+
+/****************************************************************************/
+/**
+*
+* Disable the device.
+*
+* @param InstancePtr is a pointer to the XQspiPs instance.
+*
+* @return None.
+*
+* @note C-Style signature:
+* void XQspiPs_Disable(XQspiPs *InstancePtr)
+*
+*****************************************************************************/
+#define XQspiPs_Disable(InstancePtr) \
+ XQspiPs_Out32((InstancePtr->Config.BaseAddress) + XQSPIPS_ER_OFFSET, 0)
+
+/****************************************************************************/
+/**
+*
+* Set the contents of the Linear QSPI Configuration register.
+*
+* @param InstancePtr is a pointer to the XQspiPs instance.
+* @param RegisterValue is the value to be written to the Linear QSPI
+* configuration register.
+*
+* @return None.
+*
+* @note C-Style signature:
+* void XQspiPs_SetLqspiConfigReg(XQspiPs *InstancePtr,
+* u32 RegisterValue)
+*
+*****************************************************************************/
+#define XQspiPs_SetLqspiConfigReg(InstancePtr, RegisterValue) \
+ XQspiPs_Out32(((InstancePtr)->Config.BaseAddress) + \
+ XQSPIPS_LQSPI_CR_OFFSET, (RegisterValue))
+
+/****************************************************************************/
+/**
+*
+* Get the contents of the Linear QSPI Configuration register.
+*
+* @param InstancePtr is a pointer to the XQspiPs instance.
+*
+* @return A 32-bit value representing the contents of the LQSPI Config
+* register.
+*
+* @note C-Style signature:
+* u32 XQspiPs_GetLqspiConfigReg(u32 *InstancePtr)
+*
+*****************************************************************************/
+#define XQspiPs_GetLqspiConfigReg(InstancePtr) \
+ XQspiPs_In32((InstancePtr->Config.BaseAddress) + \
+ XQSPIPS_LQSPI_CR_OFFSET)
+
+/************************** Function Prototypes ******************************/
+
+/*
+ * Initialization function, implemented in xqspips_sinit.c
+ */
+XQspiPs_Config *XQspiPs_LookupConfig(u16 DeviceId);
+
+/*
+ * Functions implemented in xqspips.c
+ */
+int XQspiPs_CfgInitialize(XQspiPs *InstancePtr, XQspiPs_Config *Config,
+ u32 EffectiveAddr);
+void XQspiPs_Reset(XQspiPs *InstancePtr);
+void XQspiPs_Abort(XQspiPs *InstancePtr);
+
+s32 XQspiPs_Transfer(XQspiPs *InstancePtr, u8 *SendBufPtr, u8 *RecvBufPtr,
+ u32 ByteCount);
+s32 XQspiPs_PolledTransfer(XQspiPs *InstancePtr, u8 *SendBufPtr,
+ u8 *RecvBufPtr, u32 ByteCount);
+int XQspiPs_LqspiRead(XQspiPs *InstancePtr, u8 *RecvBufPtr,
+ u32 Address, unsigned ByteCount);
+
+int XQspiPs_SetSlaveSelect(XQspiPs *InstancePtr);
+
+void XQspiPs_SetStatusHandler(XQspiPs *InstancePtr, void *CallBackRef,
+ XQspiPs_StatusHandler FuncPtr);
+void XQspiPs_InterruptHandler(void *InstancePtr);
+
+/*
+ * Functions for selftest, in xqspips_selftest.c
+ */
+int XQspiPs_SelfTest(XQspiPs *InstancePtr);
+
+/*
+ * Functions for options, in xqspips_options.c
+ */
+s32 XQspiPs_SetOptions(XQspiPs *InstancePtr, u32 Options);
+u32 XQspiPs_GetOptions(XQspiPs *InstancePtr);
+
+s32 XQspiPs_SetClkPrescaler(XQspiPs *InstancePtr, u8 Prescaler);
+u8 XQspiPs_GetClkPrescaler(XQspiPs *InstancePtr);
+
+int XQspiPs_SetDelays(XQspiPs *InstancePtr, u8 DelayNss, u8 DelayBtwn,
+ u8 DelayAfter, u8 DelayInit);
+void XQspiPs_GetDelays(XQspiPs *InstancePtr, u8 *DelayNss, u8 *DelayBtwn,
+ u8 *DelayAfter, u8 *DelayInit);
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* end of protection macro */
+/** @} */
diff --git a/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/qspips_v3_6/src/xqspips_g.c b/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/qspips_v3_6/src/xqspips_g.c
new file mode 100644
index 0000000..b8728ef
--- /dev/null
+++ b/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/qspips_v3_6/src/xqspips_g.c
@@ -0,0 +1,49 @@
+
+/*******************************************************************
+*
+* CAUTION: This file is automatically generated by HSI.
+* Version: 2019.2
+* DO NOT EDIT.
+*
+* Copyright (C) 2010-2021 Xilinx, Inc. All Rights Reserved.*
+*Permission is hereby granted, free of charge, to any person obtaining a copy
+*of this software and associated documentation files (the Software), to deal
+*in the Software without restriction, including without limitation the rights
+*to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+*copies of the Software, and to permit persons to whom the Software is
+*furnished to do so, subject to the following conditions:
+*
+*The above copyright notice and this permission notice shall be included in
+*all copies or substantial portions of the Software.
+*
+*THE SOFTWARE IS PROVIDED AS IS, WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+*IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+*FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+*THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+*WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT
+*OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+*
+
+*
+* Description: Driver configuration
+*
+*******************************************************************/
+
+#include "xparameters.h"
+#include "xqspips.h"
+
+/*
+* The configuration table for devices
+*/
+
+XQspiPs_Config XQspiPs_ConfigTable[XPAR_XQSPIPS_NUM_INSTANCES] =
+{
+ {
+ XPAR_PS7_QSPI_0_DEVICE_ID,
+ XPAR_PS7_QSPI_0_BASEADDR,
+ XPAR_PS7_QSPI_0_QSPI_CLK_FREQ_HZ,
+ XPAR_PS7_QSPI_0_QSPI_MODE
+ }
+};
+
+
diff --git a/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/qspips_v3_6/src/xqspips_hw.c b/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/qspips_v3_6/src/xqspips_hw.c
new file mode 100644
index 0000000..ac144dc
--- /dev/null
+++ b/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/qspips_v3_6/src/xqspips_hw.c
@@ -0,0 +1,218 @@
+/******************************************************************************
+*
+* Copyright (C) 2013 - 2019 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+* THE SOFTWARE.
+*
+*
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xqspips_hw.c
+* @addtogroup qspips_v3_6
+* @{
+*
+* Contains low level functions, primarily reset related.
+*
+* <pre>
+* MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ----- --- -------- -----------------------------------------------
+* 2.03a hk 09/17/13 First release
+* 3.1 hk 06/19/14 When writing to the configuration register, set/reset
+* required bits leaving reserved bits untouched. CR# 796813.
+*
+* </pre>
+*
+******************************************************************************/
+
+/***************************** Include Files *********************************/
+
+#include "xqspips_hw.h"
+#include "xqspips.h"
+
+/************************** Constant Definitions *****************************/
+
+/** @name Pre-scaler value for divided by 4
+ *
+ * Pre-scaler value for divided by 4
+ *
+ * @{
+ */
+#define XQSPIPS_CR_PRESC_DIV_BY_4 0x01
+/* @} */
+
+/**************************** Type Definitions *******************************/
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/************************** Function Prototypes ******************************/
+
+/************************** Variable Definitions *****************************/
+
+
+/*****************************************************************************/
+/**
+*
+* Resets QSPI by disabling the device and bringing it to reset state through
+* register writes.
+*
+* @param None
+*
+* @return None.
+*
+* @note None.
+*
+******************************************************************************/
+void XQspiPs_ResetHw(u32 BaseAddress)
+{
+ u32 ConfigReg;
+
+ /*
+ * Disable interrupts
+ */
+ XQspiPs_WriteReg(BaseAddress, XQSPIPS_IDR_OFFSET,
+ XQSPIPS_IXR_DISABLE_ALL);
+
+ /*
+ * Disable device
+ */
+ XQspiPs_WriteReg(BaseAddress, XQSPIPS_ER_OFFSET,
+ 0);
+
+ /*
+ * De-assert slave select lines.
+ */
+ ConfigReg = XQspiPs_ReadReg(BaseAddress, XQSPIPS_CR_OFFSET);
+ ConfigReg |= (XQSPIPS_CR_SSCTRL_MASK | XQSPIPS_CR_SSFORCE_MASK);
+ XQspiPs_WriteReg(BaseAddress, XQSPIPS_CR_OFFSET, ConfigReg);
+
+ /*
+ * Write default value to RX and TX threshold registers
+ * RX threshold should be set to 1 here because the corresponding
+ * status bit is used next to clear the RXFIFO
+ */
+ XQspiPs_WriteReg(BaseAddress, XQSPIPS_TXWR_OFFSET,
+ (XQSPIPS_TXWR_RESET_VALUE & XQSPIPS_TXWR_MASK));
+ XQspiPs_WriteReg(BaseAddress, XQSPIPS_RXWR_OFFSET,
+ (XQSPIPS_RXWR_RESET_VALUE & XQSPIPS_RXWR_MASK));
+
+ /*
+ * Clear RXFIFO
+ */
+ while ((XQspiPs_ReadReg(BaseAddress,XQSPIPS_SR_OFFSET) &
+ XQSPIPS_IXR_RXNEMPTY_MASK) != 0) {
+ XQspiPs_ReadReg(BaseAddress, XQSPIPS_RXD_OFFSET);
+ }
+
+ /*
+ * Clear status register by reading register and
+ * writing 1 to clear the write to clear bits
+ */
+ XQspiPs_ReadReg(BaseAddress, XQSPIPS_SR_OFFSET);
+ XQspiPs_WriteReg(BaseAddress, XQSPIPS_SR_OFFSET,
+ XQSPIPS_IXR_WR_TO_CLR_MASK);
+
+ /*
+ * Write default value to configuration register
+ */
+ ConfigReg = XQspiPs_ReadReg(BaseAddress, XQSPIPS_CR_OFFSET);
+ ConfigReg |= XQSPIPS_CR_RESET_MASK_SET;
+ ConfigReg &= ~XQSPIPS_CR_RESET_MASK_CLR;
+ XQspiPs_WriteReg(BaseAddress, XQSPIPS_CR_OFFSET, ConfigReg);
+
+ /*
+ * De-select linear mode
+ */
+ XQspiPs_WriteReg(BaseAddress, XQSPIPS_LQSPI_CR_OFFSET,
+ 0x0);
+
+}
+
+/*****************************************************************************/
+/**
+*
+* Initializes QSPI to Linear mode with default QSPI boot settings.
+*
+* @param None
+*
+* @return None.
+*
+* @note None.
+*
+******************************************************************************/
+void XQspiPs_LinearInit(u32 BaseAddress)
+{
+ u32 BaudRateDiv;
+ u32 LinearCfg;
+ u32 ConfigReg;
+
+ /*
+ * Baud rate divisor for dividing by 4. Value of CR bits [5:3]
+ * should be set to 0x001; hence shift the value and use the mask.
+ */
+ BaudRateDiv = ( (XQSPIPS_CR_PRESC_DIV_BY_4) <<
+ XQSPIPS_CR_PRESC_SHIFT) & XQSPIPS_CR_PRESC_MASK;
+ /*
+ * Write configuration register with default values, slave selected &
+ * pre-scaler value for divide by 4
+ */
+ ConfigReg = XQspiPs_ReadReg(BaseAddress, XQSPIPS_CR_OFFSET);
+ ConfigReg |= (XQSPIPS_CR_RESET_MASK_SET | BaudRateDiv);
+ ConfigReg &= ~(XQSPIPS_CR_RESET_MASK_CLR | XQSPIPS_CR_SSCTRL_MASK);
+ XQspiPs_WriteReg(BaseAddress, XQSPIPS_CR_OFFSET, ConfigReg);
+
+ /*
+ * Write linear configuration register with default value -
+ * enable linear mode and use fast read.
+ */
+
+ if(XPAR_XQSPIPS_0_QSPI_MODE == XQSPIPS_CONNECTION_MODE_SINGLE){
+
+ LinearCfg = XQSPIPS_LQSPI_CR_RST_STATE;
+
+ }else if(XPAR_XQSPIPS_0_QSPI_MODE ==
+ XQSPIPS_CONNECTION_MODE_STACKED){
+
+ LinearCfg = XQSPIPS_LQSPI_CR_RST_STATE |
+ XQSPIPS_LQSPI_CR_TWO_MEM_MASK;
+
+ }else if(XPAR_XQSPIPS_0_QSPI_MODE ==
+ XQSPIPS_CONNECTION_MODE_PARALLEL){
+
+ LinearCfg = XQSPIPS_LQSPI_CR_RST_STATE |
+ XQSPIPS_LQSPI_CR_TWO_MEM_MASK |
+ XQSPIPS_LQSPI_CR_SEP_BUS_MASK;
+
+ }
+
+ XQspiPs_WriteReg(BaseAddress, XQSPIPS_LQSPI_CR_OFFSET,
+ LinearCfg);
+
+ /*
+ * Enable device
+ */
+ XQspiPs_WriteReg(BaseAddress, XQSPIPS_ER_OFFSET,
+ XQSPIPS_ER_ENABLE_MASK);
+
+}
+/** @} */
diff --git a/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/qspips_v3_6/src/xqspips_hw.h b/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/qspips_v3_6/src/xqspips_hw.h
new file mode 100644
index 0000000..33d17d9
--- /dev/null
+++ b/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/qspips_v3_6/src/xqspips_hw.h
@@ -0,0 +1,419 @@
+/******************************************************************************
+*
+* Copyright (C) 2010 - 2019 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+* THE SOFTWARE.
+*
+*
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xqspips_hw.h
+* @addtogroup qspips_v3_6
+* @{
+*
+* This header file contains the identifiers and basic HW access driver
+* functions (or macros) that can be used to access the device. Other driver
+* functions are defined in xqspips.h.
+*
+* <pre>
+* MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ----- --- -------- -----------------------------------------------
+* 1.00 sdm 11/25/10 First release
+* 2.00a ka 07/25/12 Added a few register defines for CR 670297
+* and removed some defines of reserved fields for
+* CR 671468
+* Added define XQSPIPS_CR_HOLD_B_MASK for Holdb_dr
+* bit in Configuration register.
+* 2.01a sg 02/03/13 Added defines for DelayNss,Rx Watermark,Interrupts
+* which need write to clear. Removed Read zeros mask from
+* LQSPI Config register.
+* 2.03a hk 08/22/13 Added prototypes of API's for QSPI reset and
+* linear mode initialization for boot. Added related
+* constant definitions.
+* 3.1 hk 08/13/14 Changed definition of CR reset value masks to set/reset
+* required bits leaving reserved bits untouched. CR# 796813.
+* 3.2 sk 02/05/15 Add SLCR reset in abort function as a workaround because
+* controller does not update FIFO status flags as expected
+* when thresholds are used.
+* 3.6 akm 03/28/19 Fixed memory leak issue while reading from qspi.(CR#1016357)
+*
+* </pre>
+*
+******************************************************************************/
+#ifndef XQSPIPS_HW_H /* prevent circular inclusions */
+#define XQSPIPS_HW_H /* by using protection macros */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/***************************** Include Files *********************************/
+
+#include "xil_types.h"
+#include "xil_assert.h"
+#include "xil_io.h"
+#include "xparameters.h"
+
+/************************** Constant Definitions *****************************/
+
+/** @name Register Map
+ *
+ * Register offsets from the base address of an QSPI device.
+ * @{
+ */
+#define XQSPIPS_CR_OFFSET 0x00 /**< Configuration Register */
+#define XQSPIPS_SR_OFFSET 0x04 /**< Interrupt Status */
+#define XQSPIPS_IER_OFFSET 0x08 /**< Interrupt Enable */
+#define XQSPIPS_IDR_OFFSET 0x0c /**< Interrupt Disable */
+#define XQSPIPS_IMR_OFFSET 0x10 /**< Interrupt Enabled Mask */
+#define XQSPIPS_ER_OFFSET 0x14 /**< Enable/Disable Register */
+#define XQSPIPS_DR_OFFSET 0x18 /**< Delay Register */
+#define XQSPIPS_TXD_00_OFFSET 0x1C /**< Transmit 4-byte inst/data */
+#define XQSPIPS_RXD_OFFSET 0x20 /**< Data Receive Register */
+#define XQSPIPS_SICR_OFFSET 0x24 /**< Slave Idle Count */
+#define XQSPIPS_TXWR_OFFSET 0x28 /**< Transmit FIFO Watermark */
+#define XQSPIPS_RXWR_OFFSET 0x2C /**< Receive FIFO Watermark */
+#define XQSPIPS_GPIO_OFFSET 0x30 /**< GPIO Register */
+#define XQSPIPS_LPBK_DLY_ADJ_OFFSET 0x38 /**< Loopback Delay Adjust Reg */
+#define XQSPIPS_TXD_01_OFFSET 0x80 /**< Transmit 1-byte inst */
+#define XQSPIPS_TXD_10_OFFSET 0x84 /**< Transmit 2-byte inst */
+#define XQSPIPS_TXD_11_OFFSET 0x88 /**< Transmit 3-byte inst */
+#define XQSPIPS_LQSPI_CR_OFFSET 0xA0 /**< Linear QSPI config register */
+#define XQSPIPS_LQSPI_SR_OFFSET 0xA4 /**< Linear QSPI status register */
+#define XQSPIPS_MOD_ID_OFFSET 0xFC /**< Module ID register */
+
+/* @} */
+
+/** @name Configuration Register
+ *
+ * This register contains various control bits that
+ * affect the operation of the QSPI device. Read/Write.
+ * @{
+ */
+
+#define XQSPIPS_CR_IFMODE_MASK 0x80000000 /**< Flash mem interface mode */
+#define XQSPIPS_CR_ENDIAN_MASK 0x04000000 /**< Tx/Rx FIFO endianness */
+#define XQSPIPS_CR_MANSTRT_MASK 0x00010000 /**< Manual Transmission Start */
+#define XQSPIPS_CR_MANSTRTEN_MASK 0x00008000 /**< Manual Transmission Start
+ Enable */
+#define XQSPIPS_CR_SSFORCE_MASK 0x00004000 /**< Force Slave Select */
+#define XQSPIPS_CR_SSCTRL_MASK 0x00000400 /**< Slave Select Decode */
+#define XQSPIPS_CR_SSCTRL_SHIFT 10 /**< Slave Select Decode shift */
+#define XQSPIPS_CR_DATA_SZ_MASK 0x000000C0 /**< Size of word to be
+ transferred */
+#define XQSPIPS_CR_PRESC_MASK 0x00000038 /**< Prescaler Setting */
+#define XQSPIPS_CR_PRESC_SHIFT 3 /**< Prescaler shift */
+#define XQSPIPS_CR_PRESC_MAXIMUM 0x07 /**< Prescaler maximum value */
+
+#define XQSPIPS_CR_CPHA_MASK 0x00000004 /**< Phase Configuration */
+#define XQSPIPS_CR_CPOL_MASK 0x00000002 /**< Polarity Configuration */
+
+#define XQSPIPS_CR_MSTREN_MASK 0x00000001 /**< Master Mode Enable */
+
+#define XQSPIPS_CR_HOLD_B_MASK 0x00080000 /**< HOLD_B Pin Drive Enable */
+
+#define XQSPIPS_CR_REF_CLK_MASK 0x00000100 /**< Ref clk bit - should be 0 */
+
+/* Deselect the Slave select line and set the transfer size to 32 at reset */
+#define XQSPIPS_CR_RESET_MASK_SET XQSPIPS_CR_IFMODE_MASK | \
+ XQSPIPS_CR_SSCTRL_MASK | \
+ XQSPIPS_CR_DATA_SZ_MASK | \
+ XQSPIPS_CR_MSTREN_MASK | \
+ XQSPIPS_CR_SSFORCE_MASK | \
+ XQSPIPS_CR_HOLD_B_MASK
+#define XQSPIPS_CR_RESET_MASK_CLR XQSPIPS_CR_CPOL_MASK | \
+ XQSPIPS_CR_CPHA_MASK | \
+ XQSPIPS_CR_PRESC_MASK | \
+ XQSPIPS_CR_MANSTRTEN_MASK | \
+ XQSPIPS_CR_MANSTRT_MASK | \
+ XQSPIPS_CR_ENDIAN_MASK | \
+ XQSPIPS_CR_REF_CLK_MASK
+/* @} */
+
+
+/** @name QSPI Interrupt Registers
+ *
+ * <b>QSPI Status Register</b>
+ *
+ * This register holds the interrupt status flags for an QSPI device. Some
+ * of the flags are level triggered, which means that they are set as long
+ * as the interrupt condition exists. Other flags are edge triggered,
+ * which means they are set once the interrupt condition occurs and remain
+ * set until they are cleared by software. The interrupts are cleared by
+ * writing a '1' to the interrupt bit position in the Status Register.
+ * Read/Write.
+ *
+ * <b>QSPI Interrupt Enable Register</b>
+ *
+ * This register is used to enable chosen interrupts for an QSPI device.
+ * Writing a '1' to a bit in this register sets the corresponding bit in the
+ * QSPI Interrupt Mask register. Write only.
+ *
+ * <b>QSPI Interrupt Disable Register </b>
+ *
+ * This register is used to disable chosen interrupts for an QSPI device.
+ * Writing a '1' to a bit in this register clears the corresponding bit in the
+ * QSPI Interrupt Mask register. Write only.
+ *
+ * <b>QSPI Interrupt Mask Register</b>
+ *
+ * This register shows the enabled/disabled interrupts of an QSPI device.
+ * Read only.
+ *
+ * All four registers have the same bit definitions. They are only defined once
+ * for each of the Interrupt Enable Register, Interrupt Disable Register,
+ * Interrupt Mask Register, and Channel Interrupt Status Register
+ * @{
+ */
+
+#define XQSPIPS_IXR_TXUF_MASK 0x00000040 /**< QSPI Tx FIFO Underflow */
+#define XQSPIPS_IXR_RXFULL_MASK 0x00000020 /**< QSPI Rx FIFO Full */
+#define XQSPIPS_IXR_RXNEMPTY_MASK 0x00000010 /**< QSPI Rx FIFO Not Empty */
+#define XQSPIPS_IXR_TXFULL_MASK 0x00000008 /**< QSPI Tx FIFO Full */
+#define XQSPIPS_IXR_TXOW_MASK 0x00000004 /**< QSPI Tx FIFO Overwater */
+#define XQSPIPS_IXR_RXOVR_MASK 0x00000001 /**< QSPI Rx FIFO Overrun */
+#define XQSPIPS_IXR_DFLT_MASK 0x00000025 /**< QSPI default interrupts
+ mask */
+#define XQSPIPS_IXR_WR_TO_CLR_MASK 0x00000041 /**< Interrupts which
+ need write to clear */
+#define XQSPIPS_ISR_RESET_STATE 0x00000004 /**< Default to tx/rx empty */
+#define XQSPIPS_IXR_DISABLE_ALL 0x0000007D /**< Disable all interrupts */
+/* @} */
+
+
+/** @name Enable Register
+ *
+ * This register is used to enable or disable an QSPI device.
+ * Read/Write
+ * @{
+ */
+#define XQSPIPS_ER_ENABLE_MASK 0x00000001 /**< QSPI Enable Bit Mask */
+/* @} */
+
+
+/** @name Delay Register
+ *
+ * This register is used to program timing delays in
+ * slave mode. Read/Write
+ * @{
+ */
+#define XQSPIPS_DR_NSS_MASK 0xFF000000 /**< Delay to de-assert slave select
+ between two words mask */
+#define XQSPIPS_DR_NSS_SHIFT 24 /**< Delay to de-assert slave select
+ between two words shift */
+#define XQSPIPS_DR_BTWN_MASK 0x00FF0000 /**< Delay Between Transfers
+ mask */
+#define XQSPIPS_DR_BTWN_SHIFT 16 /**< Delay Between Transfers shift */
+#define XQSPIPS_DR_AFTER_MASK 0x0000FF00 /**< Delay After Transfers mask */
+#define XQSPIPS_DR_AFTER_SHIFT 8 /**< Delay After Transfers shift */
+#define XQSPIPS_DR_INIT_MASK 0x000000FF /**< Delay Initially mask */
+/* @} */
+
+/** @name Slave Idle Count Registers
+ *
+ * This register defines the number of pclk cycles the slave waits for a the
+ * QSPI clock to become stable in quiescent state before it can detect the start
+ * of the next transfer in CPHA = 1 mode.
+ * Read/Write
+ *
+ * @{
+ */
+#define XQSPIPS_SICR_MASK 0x000000FF /**< Slave Idle Count Mask */
+/* @} */
+
+
+/** @name Transmit FIFO Watermark Register
+ *
+ * This register defines the watermark setting for the Transmit FIFO.
+ *
+ * @{
+ */
+#define XQSPIPS_TXWR_MASK 0x0000003F /**< Transmit Watermark Mask */
+#define XQSPIPS_TXWR_RESET_VALUE 0x00000001 /**< Transmit Watermark
+ * register reset value */
+
+/* @} */
+
+/** @name Receive FIFO Watermark Register
+ *
+ * This register defines the watermark setting for the Receive FIFO.
+ *
+ * @{
+ */
+#define XQSPIPS_RXWR_MASK 0x0000003F /**< Receive Watermark Mask */
+#define XQSPIPS_RXWR_RESET_VALUE 0x00000001 /**< Receive Watermark
+ * register reset value */
+
+/* @} */
+
+/** @name FIFO Depth
+ *
+ * This macro provides the depth of transmit FIFO and receive FIFO.
+ *
+ * @{
+ */
+#define XQSPIPS_FIFO_DEPTH 63 /**< FIFO depth (words) */
+/* @} */
+
+
+/** @name Linear QSPI Configuration Register
+ *
+ * This register contains various control bits that
+ * affect the operation of the Linear QSPI controller. Read/Write.
+ *
+ * @{
+ */
+#define XQSPIPS_LQSPI_CR_LINEAR_MASK 0x80000000 /**< LQSPI mode enable */
+#define XQSPIPS_LQSPI_CR_TWO_MEM_MASK 0x40000000 /**< Both memories or one */
+#define XQSPIPS_LQSPI_CR_SEP_BUS_MASK 0x20000000 /**< Separate memory bus */
+#define XQSPIPS_LQSPI_CR_U_PAGE_MASK 0x10000000 /**< Upper memory page */
+#define XQSPIPS_LQSPI_CR_MODE_EN_MASK 0x02000000 /**< Enable mode bits */
+#define XQSPIPS_LQSPI_CR_MODE_ON_MASK 0x01000000 /**< Mode on */
+#define XQSPIPS_LQSPI_CR_MODE_BITS_MASK 0x00FF0000 /**< Mode value for dual I/O
+ or quad I/O */
+#define XQSPIPS_LQSPI_CR_DUMMY_MASK 0x00000700 /**< Number of dummy bytes
+ between addr and return
+ read data */
+#define XQSPIPS_LQSPI_CR_INST_MASK 0x000000FF /**< Read instr code */
+#define XQSPIPS_LQSPI_CR_RST_STATE 0x8000016B /**< Default CR value */
+/* @} */
+
+/** @name Linear QSPI Status Register
+ *
+ * This register contains various status bits of the Linear QSPI controller.
+ * Read/Write.
+ *
+ * @{
+ */
+#define XQSPIPS_LQSPI_SR_D_FSM_ERR_MASK 0x00000004 /**< AXI Data FSM Error
+ received */
+#define XQSPIPS_LQSPI_SR_WR_RECVD_MASK 0x00000002 /**< AXI write command
+ received */
+/* @} */
+
+
+/** @name Loopback Delay Adjust Register
+ *
+ * This register contains various bit masks of Loopback Delay Adjust Register.
+ *
+ * @{
+ */
+
+#define XQSPIPS_LPBK_DLY_ADJ_USE_LPBK_MASK 0x00000020 /**< Loopback Bit */
+
+/* @} */
+
+
+/** @name SLCR Register
+ *
+ * Register offsets from SLCR base address.
+ *
+ * @{
+ */
+
+#define SLCR_LOCK 0x00000004 /**< SLCR Write Protection Lock */
+#define SLCR_UNLOCK 0x00000008 /**< SLCR Write Protection Unlock */
+#define LQSPI_RST_CTRL 0x00000230 /**< Quad SPI Software Reset Control */
+#define SLCR_LOCKSTA 0x0000000C /**< SLCR Write Protection status */
+
+/* @} */
+
+
+/** @name SLCR Register
+ *
+ * Bit Masks of above SLCR Registers .
+ *
+ * @{
+ */
+
+#ifndef XPAR_XSLCR_0_BASEADDR
+#define XPAR_XSLCR_0_BASEADDR 0xF8000000
+#endif
+#define SLCR_LOCK_MASK 0x767B /**< Write Protection Lock mask*/
+#define SLCR_UNLOCK_MASK 0xDF0D /**< SLCR Write Protection Unlock */
+#define LQSPI_RST_CTRL_MASK 0x3 /**< Quad SPI Software Reset Control */
+
+/* @} */
+
+
+/**************************** Type Definitions *******************************/
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+#define XQspiPs_In32 Xil_In32
+#define XQspiPs_Out32 Xil_Out32
+#define XQSPIPS_DUMMY_TX_DATA 0xFFFFFFFF
+
+/****************************************************************************/
+/**
+* Read a register.
+*
+* @param BaseAddress contains the base address of the device.
+* @param RegOffset contains the offset from the 1st register of the
+* device to the target register.
+*
+* @return The value read from the register.
+*
+* @note C-Style signature:
+* u32 XQspiPs_ReadReg(u32 BaseAddress. int RegOffset)
+*
+******************************************************************************/
+#define XQspiPs_ReadReg(BaseAddress, RegOffset) \
+ XQspiPs_In32((BaseAddress) + (RegOffset))
+
+/***************************************************************************/
+/**
+* Write to a register.
+*
+* @param BaseAddress contains the base address of the device.
+* @param RegOffset contains the offset from the 1st register of the
+* device to target register.
+* @param RegisterValue is the value to be written to the register.
+*
+* @return None.
+*
+* @note C-Style signature:
+* void XQspiPs_WriteReg(u32 BaseAddress, int RegOffset,
+* u32 RegisterValue)
+*
+******************************************************************************/
+#define XQspiPs_WriteReg(BaseAddress, RegOffset, RegisterValue) \
+ XQspiPs_Out32((BaseAddress) + (RegOffset), (RegisterValue))
+
+/************************** Function Prototypes ******************************/
+
+/*
+ * Functions implemented in xqspips_hw.c
+ */
+void XQspiPs_ResetHw(u32 BaseAddress);
+void XQspiPs_LinearInit(u32 BaseAddress);
+
+/************************** Variable Definitions *****************************/
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* end of protection macro */
+/** @} */
diff --git a/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/qspips_v3_6/src/xqspips_options.c b/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/qspips_v3_6/src/xqspips_options.c
new file mode 100644
index 0000000..9fd6ca2
--- /dev/null
+++ b/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/qspips_v3_6/src/xqspips_options.c
@@ -0,0 +1,424 @@
+/******************************************************************************
+*
+* Copyright (C) 2010 - 2019 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+* THE SOFTWARE.
+*
+*
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xqspips_options.c
+* @addtogroup qspips_v3_6
+* @{
+*
+* Contains functions for the configuration of the XQspiPs driver component.
+*
+* <pre>
+* MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ----- --- -------- -----------------------------------------------
+* 1.00 sdm 11/25/10 First release
+* 2.00a kka 07/25/12 Removed the selection for the following options:
+* Master mode (XQSPIPS_MASTER_OPTION) and
+* Flash interface mode (XQSPIPS_FLASH_MODE_OPTION) option
+* as the QSPI driver supports the Master mode
+* and Flash Interface mode. The driver doesnot support
+* Slave mode or the legacy mode.
+* Added the option for setting the Holdb_dr bit in the
+* configuration options, XQSPIPS_HOLD_B_DRIVE_OPTION
+* is the option to be used for setting this bit in the
+* configuration register.
+* 2.01a sg 02/03/13 SetDelays and GetDelays API's include DelayNss parameter.
+*
+* 2.02a hk 26/03/13 Removed XQspi_Reset() in Set_Options() function when
+* LQSPI_MODE_OPTION is set. Moved Enable() to XQpsiPs_LqspiRead().
+* 3.3 sk 11/07/15 Modified the API prototypes according to MISRAC standards
+* to remove compilation warnings. CR# 868893.
+*</pre>
+*
+******************************************************************************/
+
+/***************************** Include Files *********************************/
+
+#include "xqspips.h"
+
+/************************** Constant Definitions *****************************/
+
+/**************************** Type Definitions *******************************/
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/************************** Function Prototypes ******************************/
+
+/************************** Variable Definitions *****************************/
+
+/*
+ * Create the table of options which are processed to get/set the device
+ * options. These options are table driven to allow easy maintenance and
+ * expansion of the options.
+ */
+typedef struct {
+ u32 Option;
+ u32 Mask;
+} OptionsMap;
+
+static OptionsMap OptionsTable[] = {
+ {XQSPIPS_CLK_ACTIVE_LOW_OPTION, XQSPIPS_CR_CPOL_MASK},
+ {XQSPIPS_CLK_PHASE_1_OPTION, XQSPIPS_CR_CPHA_MASK},
+ {XQSPIPS_FORCE_SSELECT_OPTION, XQSPIPS_CR_SSFORCE_MASK},
+ {XQSPIPS_MANUAL_START_OPTION, XQSPIPS_CR_MANSTRTEN_MASK},
+ {XQSPIPS_HOLD_B_DRIVE_OPTION, XQSPIPS_CR_HOLD_B_MASK},
+};
+
+#define XQSPIPS_NUM_OPTIONS (sizeof(OptionsTable) / sizeof(OptionsMap))
+
+/*****************************************************************************/
+/**
+*
+* This function sets the options for the QSPI device driver. The options control
+* how the device behaves relative to the QSPI bus. The device must be idle
+* rather than busy transferring data before setting these device options.
+*
+* @param InstancePtr is a pointer to the XQspiPs instance.
+* @param Options contains the specified options to be set. This is a bit
+* mask where a 1 means to turn the option on, and a 0 means to
+* turn the option off. One or more bit values may be contained in
+* the mask. See the bit definitions named XQSPIPS_*_OPTIONS in
+* the file xqspips.h.
+*
+* @return
+* - XST_SUCCESS if options are successfully set.
+* - XST_DEVICE_BUSY if the device is currently transferring data.
+* The transfer must complete or be aborted before setting options.
+*
+* @note
+* This function is not thread-safe.
+*
+******************************************************************************/
+s32 XQspiPs_SetOptions(XQspiPs *InstancePtr, u32 Options)
+{
+ u32 ConfigReg;
+ unsigned int Index;
+ u32 QspiOptions;
+
+ Xil_AssertNonvoid(InstancePtr != NULL);
+ Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+ /*
+ * Do not allow to modify the Control Register while a transfer is in
+ * progress. Not thread-safe.
+ */
+ if (InstancePtr->IsBusy) {
+ return XST_DEVICE_BUSY;
+ }
+
+ QspiOptions = Options & XQSPIPS_LQSPI_MODE_OPTION;
+ Options &= ~XQSPIPS_LQSPI_MODE_OPTION;
+
+ ConfigReg = XQspiPs_ReadReg(InstancePtr->Config.BaseAddress,
+ XQSPIPS_CR_OFFSET);
+
+ /*
+ * Loop through the options table, turning the option on or off
+ * depending on whether the bit is set in the incoming options flag.
+ */
+ for (Index = 0; Index < XQSPIPS_NUM_OPTIONS; Index++) {
+ if (Options & OptionsTable[Index].Option) {
+ /* Turn it on */
+ ConfigReg |= OptionsTable[Index].Mask;
+ } else {
+ /* Turn it off */
+ ConfigReg &= ~(OptionsTable[Index].Mask);
+ }
+ }
+
+ /*
+ * Now write the control register. Leave it to the upper layers
+ * to restart the device.
+ */
+ XQspiPs_WriteReg(InstancePtr->Config.BaseAddress, XQSPIPS_CR_OFFSET,
+ ConfigReg);
+
+ /*
+ * Check for the LQSPI configuration options.
+ */
+ ConfigReg = XQspiPs_ReadReg(InstancePtr->Config.BaseAddress,
+ XQSPIPS_LQSPI_CR_OFFSET);
+
+
+ if (QspiOptions & XQSPIPS_LQSPI_MODE_OPTION) {
+ XQspiPs_WriteReg(InstancePtr->Config.BaseAddress,
+ XQSPIPS_LQSPI_CR_OFFSET,
+ XQSPIPS_LQSPI_CR_RST_STATE);
+ XQspiPs_SetSlaveSelect(InstancePtr);
+ } else {
+ ConfigReg &= ~XQSPIPS_LQSPI_CR_LINEAR_MASK;
+ XQspiPs_WriteReg(InstancePtr->Config.BaseAddress,
+ XQSPIPS_LQSPI_CR_OFFSET, ConfigReg);
+ }
+
+ return XST_SUCCESS;
+}
+
+/*****************************************************************************/
+/**
+*
+* This function gets the options for the QSPI device. The options control how
+* the device behaves relative to the QSPI bus.
+*
+* @param InstancePtr is a pointer to the XQspiPs instance.
+*
+* @return
+*
+* Options contains the specified options currently set. This is a bit value
+* where a 1 means the option is on, and a 0 means the option is off.
+* See the bit definitions named XQSPIPS_*_OPTIONS in file xqspips.h.
+*
+* @note None.
+*
+******************************************************************************/
+u32 XQspiPs_GetOptions(XQspiPs *InstancePtr)
+{
+ u32 OptionsFlag = 0;
+ u32 ConfigReg;
+ unsigned int Index;
+
+ Xil_AssertNonvoid(InstancePtr != NULL);
+ Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+ /*
+ * Get the current options from QSPI configuration register.
+ */
+ ConfigReg = XQspiPs_ReadReg(InstancePtr->Config.BaseAddress,
+ XQSPIPS_CR_OFFSET);
+
+ /*
+ * Loop through the options table to grab options
+ */
+ for (Index = 0; Index < XQSPIPS_NUM_OPTIONS; Index++) {
+ if (ConfigReg & OptionsTable[Index].Mask) {
+ OptionsFlag |= OptionsTable[Index].Option;
+ }
+ }
+
+ /*
+ * Check for the LQSPI configuration options.
+ */
+ ConfigReg = XQspiPs_ReadReg(InstancePtr->Config.BaseAddress,
+ XQSPIPS_LQSPI_CR_OFFSET);
+
+ if ((ConfigReg & XQSPIPS_LQSPI_CR_LINEAR_MASK) != 0) {
+ OptionsFlag |= XQSPIPS_LQSPI_MODE_OPTION;
+ }
+
+ return OptionsFlag;
+}
+
+/*****************************************************************************/
+/**
+*
+* This function sets the clock prescaler for an QSPI device. The device
+* must be idle rather than busy transferring data before setting these device
+* options.
+*
+* @param InstancePtr is a pointer to the XQspiPs instance.
+* @param Prescaler is the value that determine how much the clock should
+* be divided by. Use the XQSPIPS_CLK_PRESCALE_* constants defined
+* in xqspips.h for this setting.
+*
+* @return
+* - XST_SUCCESS if options are successfully set.
+* - XST_DEVICE_BUSY if the device is currently transferring data.
+* The transfer must complete or be aborted before setting options.
+*
+* @note
+* This function is not thread-safe.
+*
+******************************************************************************/
+s32 XQspiPs_SetClkPrescaler(XQspiPs *InstancePtr, u8 Prescaler)
+{
+ u32 ConfigReg;
+
+ Xil_AssertNonvoid(InstancePtr != NULL);
+ Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+ Xil_AssertNonvoid(Prescaler <= XQSPIPS_CR_PRESC_MAXIMUM);
+
+ /*
+ * Do not allow the slave select to change while a transfer is in
+ * progress. Not thread-safe.
+ */
+ if (InstancePtr->IsBusy) {
+ return XST_DEVICE_BUSY;
+ }
+
+ /*
+ * Read the configuration register, mask out the interesting bits, and set
+ * them with the shifted value passed into the function. Write the
+ * results back to the configuration register.
+ */
+ ConfigReg = XQspiPs_ReadReg(InstancePtr->Config.BaseAddress,
+ XQSPIPS_CR_OFFSET);
+
+ ConfigReg &= ~XQSPIPS_CR_PRESC_MASK;
+ ConfigReg |= (u32) (Prescaler & XQSPIPS_CR_PRESC_MAXIMUM) <<
+ XQSPIPS_CR_PRESC_SHIFT;
+
+ XQspiPs_WriteReg(InstancePtr->Config.BaseAddress,
+ XQSPIPS_CR_OFFSET,
+ ConfigReg);
+
+ return XST_SUCCESS;
+}
+
+/*****************************************************************************/
+/**
+*
+* This function gets the clock prescaler of an QSPI device.
+*
+* @param InstancePtr is a pointer to the XQspiPs instance.
+*
+* @return The prescaler value.
+*
+* @note None.
+*
+*
+******************************************************************************/
+u8 XQspiPs_GetClkPrescaler(XQspiPs *InstancePtr)
+{
+ u32 ConfigReg;
+
+ Xil_AssertNonvoid(InstancePtr != NULL);
+ Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+ ConfigReg = XQspiPs_ReadReg(InstancePtr->Config.BaseAddress,
+ XQSPIPS_CR_OFFSET);
+
+ ConfigReg &= XQSPIPS_CR_PRESC_MASK;
+
+ return (u8)(ConfigReg >> XQSPIPS_CR_PRESC_SHIFT);
+}
+
+/*****************************************************************************/
+/**
+*
+* This function sets the delay register for the QSPI device driver.
+* The delay register controls the Delay Between Transfers, Delay After
+* Transfers, and the Delay Initially. The default value is 0x0. The range of
+* each delay value is 0-255.
+*
+* @param InstancePtr is a pointer to the XQspiPs instance.
+* @param DelayNss is the delay to de-assert slave select between
+* two word transfers.
+* @param DelayBtwn is the delay between one Slave Select being
+* de-activated and the activation of another slave. The delay is
+* the number of master clock periods given by DelayBtwn + 2.
+* @param DelayAfter define the delay between the last bit of the current
+* byte transfer and the first bit of the next byte transfer.
+* The delay in number of master clock periods is given as:
+* CHPA=0:DelayInit+DelayAfter+3
+* CHPA=1:DelayAfter+1
+* @param DelayInit is the delay between asserting the slave select signal
+* and the first bit transfer. The delay int number of master clock
+* periods is DelayInit+1.
+*
+* @return
+* - XST_SUCCESS if delays are successfully set.
+* - XST_DEVICE_BUSY if the device is currently transferring data.
+* The transfer must complete or be aborted before setting options.
+*
+* @note None.
+*
+******************************************************************************/
+int XQspiPs_SetDelays(XQspiPs *InstancePtr, u8 DelayNss, u8 DelayBtwn,
+ u8 DelayAfter, u8 DelayInit)
+{
+ u32 DelayRegister;
+
+ Xil_AssertNonvoid(InstancePtr != NULL);
+ Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+ /*
+ * Do not allow the delays to change while a transfer is in
+ * progress. Not thread-safe.
+ */
+ if (InstancePtr->IsBusy) {
+ return XST_DEVICE_BUSY;
+ }
+
+ /* Shift, Mask and OR the values to build the register settings */
+ DelayRegister = (u32) DelayNss << XQSPIPS_DR_NSS_SHIFT;
+ DelayRegister |= (u32) DelayBtwn << XQSPIPS_DR_BTWN_SHIFT;
+ DelayRegister |= (u32) DelayAfter << XQSPIPS_DR_AFTER_SHIFT;
+ DelayRegister |= (u32) DelayInit;
+
+ XQspiPs_WriteReg(InstancePtr->Config.BaseAddress,
+ XQSPIPS_DR_OFFSET, DelayRegister);
+
+ return XST_SUCCESS;
+}
+
+/*****************************************************************************/
+/**
+*
+* This function gets the delay settings for an QSPI device.
+* The delay register controls the Delay Between Transfers, Delay After
+* Transfers, and the Delay Initially. The default value is 0x0.
+*
+* @param InstancePtr is a pointer to the XQspiPs instance.
+* @param DelayNss is a pointer to the Delay to de-assert slave select
+* between two word transfers.
+* @param DelayBtwn is a pointer to the Delay Between transfers value.
+* This is a return parameter.
+* @param DelayAfter is a pointer to the Delay After transfer value.
+* This is a return parameter.
+* @param DelayInit is a pointer to the Delay Initially value. This is
+* a return parameter.
+*
+* @return None.
+*
+* @note None.
+*
+******************************************************************************/
+void XQspiPs_GetDelays(XQspiPs *InstancePtr, u8 *DelayNss, u8 *DelayBtwn,
+ u8 *DelayAfter, u8 *DelayInit)
+{
+ u32 DelayRegister;
+
+ Xil_AssertVoid(InstancePtr != NULL);
+ Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+ DelayRegister = XQspiPs_ReadReg(InstancePtr->Config.BaseAddress,
+ XQSPIPS_DR_OFFSET);
+
+ *DelayInit = (u8)(DelayRegister & XQSPIPS_DR_INIT_MASK);
+
+ *DelayAfter = (u8)((DelayRegister & XQSPIPS_DR_AFTER_MASK) >>
+ XQSPIPS_DR_AFTER_SHIFT);
+
+ *DelayBtwn = (u8)((DelayRegister & XQSPIPS_DR_BTWN_MASK) >>
+ XQSPIPS_DR_BTWN_SHIFT);
+
+ *DelayNss = (u8)((DelayRegister & XQSPIPS_DR_NSS_MASK) >>
+ XQSPIPS_DR_NSS_SHIFT);
+}
+/** @} */
diff --git a/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/qspips_v3_6/src/xqspips_selftest.c b/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/qspips_v3_6/src/xqspips_selftest.c
new file mode 100644
index 0000000..f1afd7f
--- /dev/null
+++ b/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/qspips_v3_6/src/xqspips_selftest.c
@@ -0,0 +1,133 @@
+/******************************************************************************
+*
+* Copyright (C) 2010 - 2019 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+* THE SOFTWARE.
+*
+*
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xqspips_selftest.c
+* @addtogroup qspips_v3_6
+* @{
+*
+* This file contains the implementation of selftest function for the QSPI
+* device.
+*
+* <pre>
+* MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ----- --- -------- -----------------------------------------------
+* 1.00 sdm 11/25/10 First release
+* 2.01a sg 02/03/13 Delay Register test is added with DelayNss parameter.
+* 3.1 hk 06/19/14 Remove checks for CR and ISR register values as they are
+* reset in the previous step.
+*
+* </pre>
+*
+******************************************************************************/
+
+/***************************** Include Files *********************************/
+
+#include "xqspips.h"
+
+/************************** Constant Definitions *****************************/
+
+/**************************** Type Definitions *******************************/
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/************************** Function Prototypes ******************************/
+
+/************************** Variable Definitions *****************************/
+
+/*****************************************************************************/
+/**
+*
+* Runs a self-test on the driver/device. The self-test is destructive in that
+* a reset of the device is performed in order to check the reset values of
+* the registers and to get the device into a known state.
+*
+* Upon successful return from the self-test, the device is reset.
+*
+* @param InstancePtr is a pointer to the XQspiPs instance.
+*
+* @return
+* - XST_SUCCESS if successful
+* - XST_REGISTER_ERROR indicates a register did not read or write
+* correctly.
+*
+* @note None.
+*
+******************************************************************************/
+int XQspiPs_SelfTest(XQspiPs *InstancePtr)
+{
+ int Status;
+ u8 DelayTestNss;
+ u8 DelayTestBtwn;
+ u8 DelayTestAfter;
+ u8 DelayTestInit;
+
+ Xil_AssertNonvoid(InstancePtr != NULL);
+ Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+ /*
+ * Reset the QSPI device to leave it in a known good state
+ */
+ XQspiPs_Reset(InstancePtr);
+
+ DelayTestNss = 0x5A;
+ DelayTestBtwn = 0xA5;
+ DelayTestAfter = 0xAA;
+ DelayTestInit = 0x55;
+
+ /*
+ * Write and read the delay register, just to be sure there is some
+ * hardware out there.
+ */
+ Status = XQspiPs_SetDelays(InstancePtr, DelayTestNss, DelayTestBtwn,
+ DelayTestAfter, DelayTestInit);
+ if (Status != XST_SUCCESS) {
+ return Status;
+ }
+
+ XQspiPs_GetDelays(InstancePtr, &DelayTestNss, &DelayTestBtwn,
+ &DelayTestAfter, &DelayTestInit);
+ if ((0x5A != DelayTestNss) || (0xA5 != DelayTestBtwn) ||
+ (0xAA != DelayTestAfter) || (0x55 != DelayTestInit)) {
+ return XST_REGISTER_ERROR;
+ }
+
+ Status = XQspiPs_SetDelays(InstancePtr, 0, 0, 0, 0);
+ if (Status != XST_SUCCESS) {
+ return Status;
+ }
+
+ /*
+ * Reset the QSPI device to leave it in a known good state
+ */
+ XQspiPs_Reset(InstancePtr);
+
+ return XST_SUCCESS;
+}
+/** @} */
diff --git a/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/qspips_v3_6/src/xqspips_sinit.c b/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/qspips_v3_6/src/xqspips_sinit.c
new file mode 100644
index 0000000..f6c2b70
--- /dev/null
+++ b/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/qspips_v3_6/src/xqspips_sinit.c
@@ -0,0 +1,94 @@
+/******************************************************************************
+*
+* Copyright (C) 2010 - 2019 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+* THE SOFTWARE.
+*
+*
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xqspips_sinit.c
+* @addtogroup qspips_v3_6
+* @{
+*
+* The implementation of the XQspiPs component's static initialization
+* functionality.
+*
+* <pre>
+* MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ----- --- -------- -----------------------------------------------
+* 1.00 sdm 11/25/10 First release
+* </pre>
+*
+******************************************************************************/
+
+/***************************** Include Files *********************************/
+
+#include "xstatus.h"
+#include "xqspips.h"
+#include "xparameters.h"
+
+/************************** Constant Definitions *****************************/
+
+/**************************** Type Definitions *******************************/
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/************************** Function Prototypes ******************************/
+
+/************************** Variable Definitions *****************************/
+
+extern XQspiPs_Config XQspiPs_ConfigTable[];
+
+/*****************************************************************************/
+/**
+*
+* Looks up the device configuration based on the unique device ID. A table
+* contains the configuration info for each device in the system.
+*
+* @param DeviceId contains the ID of the device to look up the
+* configuration for.
+*
+* @return
+*
+* A pointer to the configuration found or NULL if the specified device ID was
+* not found. See xqspips.h for the definition of XQspiPs_Config.
+*
+* @note None.
+*
+******************************************************************************/
+XQspiPs_Config *XQspiPs_LookupConfig(u16 DeviceId)
+{
+ XQspiPs_Config *CfgPtr = NULL;
+ int Index;
+
+ for (Index = 0; Index < XPAR_XQSPIPS_NUM_INSTANCES; Index++) {
+ if (XQspiPs_ConfigTable[Index].DeviceId == DeviceId) {
+ CfgPtr = &XQspiPs_ConfigTable[Index];
+ break;
+ }
+ }
+ return CfgPtr;
+}
+/** @} */
diff --git a/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/scugic_v4_1/src/Makefile b/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/scugic_v4_1/src/Makefile
new file mode 100644
index 0000000..04867a4
--- /dev/null
+++ b/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/scugic_v4_1/src/Makefile
@@ -0,0 +1,40 @@
+COMPILER=
+ARCHIVER=
+CP=cp
+COMPILER_FLAGS=
+EXTRA_COMPILER_FLAGS=
+LIB=libxil.a
+
+CC_FLAGS = $(COMPILER_FLAGS)
+ECC_FLAGS = $(EXTRA_COMPILER_FLAGS)
+
+RELEASEDIR=../../../lib
+INCLUDEDIR=../../../include
+INCLUDES=-I./. -I${INCLUDEDIR}
+
+OUTS = *.o
+
+LIBSOURCES:=*.c
+INCLUDEFILES:=*.h
+
+OBJECTS = $(addsuffix .o, $(basename $(wildcard *.c)))
+
+libs: banner scugic_libs clean
+
+%.o: %.c
+ ${COMPILER} $(CC_FLAGS) $(ECC_FLAGS) $(INCLUDES) -o $@ $<
+
+banner:
+ echo "Compiling scugic"
+
+scugic_libs: ${OBJECTS}
+ $(ARCHIVER) -r ${RELEASEDIR}/${LIB} ${OBJECTS}
+
+.PHONY: include
+include: scugic_includes
+
+scugic_includes:
+ ${CP} ${INCLUDEFILES} ${INCLUDEDIR}
+
+clean:
+ rm -rf ${OBJECTS}
diff --git a/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/scugic_v4_1/src/xscugic.c b/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/scugic_v4_1/src/xscugic.c
new file mode 100644
index 0000000..36e74d1
--- /dev/null
+++ b/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/scugic_v4_1/src/xscugic.c
@@ -0,0 +1,1180 @@
+/******************************************************************************
+*
+* Copyright (C) 2010 - 2019 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+* THE SOFTWARE.
+*
+*
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xscugic.c
+* @addtogroup scugic_v4_0
+* @{
+*
+* Contains required functions for the XScuGic driver for the Interrupt
+* Controller. See xscugic.h for a detailed description of the driver.
+*
+* <pre>
+* MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ----- ---- -------- --------------------------------------------------------
+* 1.00a drg 01/19/10 First release
+* 1.01a sdm 11/09/11 Changes are made in function XScuGic_CfgInitialize
+* Since entry is now made as pointer in the XScuGic
+* structure, necessary changes are made.
+* The HandlerTable can now be populated through the low
+* level routine XScuGic_RegisterHandler added in this
+* release. Hence necessary checks are added not to
+* overwrite the HandlerTable entriesin function
+* XScuGic_CfgInitialize.
+* 1.03a srt 02/27/13 Added APIs
+* -XScuGic_SetPriTrigTypeByDistAddr()
+* -XScuGic_GetPriTrigTypeByDistAddr()
+* Removed Offset calculation macros, defined in _hw.h
+* (CR 702687)
+* added support to direct interrupts to the appropriate
+* CPU Earlier interrupts were directed to CPU1
+* (hard coded).Now depending upon the CPU selected by the
+* user(xparameters.h), interrupts will be directed to
+* the relevant CPU. This fixes CR 699688.
+*
+* 1.04a hk 05/04/13 Assigned EffectiveAddr to CpuBaseAddress in
+* XScuGic_CfgInitialize. Fix for CR#704400 to remove
+* warnings.
+* Moved functions XScuGic_SetPriTrigTypeByDistAddr and
+* XScuGic_GetPriTrigTypeByDistAddr to xscugic_hw.c.
+* This is fix for CR#705621.
+* 1.06a asa 16/11/13 Fix for CR#749178. Assignment for EffectiveAddr
+* in function XScuGic_CfgInitialize is removed as it was
+* a bug.
+* 3.00 kvn 02/13/14 Modified code for MISRA-C:2012 compliance.
+* 3.01 pkp 06/19/15 Added XScuGic_InterruptMaptoCpu API for an interrupt
+* target CPU mapping
+* 3.02 pkp 11/09/15 Modified DistributorInit function for AMP case to add
+* the current cpu to interrupt processor targets registers
+* 3.2 asa 02/29/16 Modified DistributorInit function for Zynq AMP case. The
+* distributor is left uninitialized for Zynq AMP. It is
+* assumed that the distributor will be initialized by
+* Linux master. However for CortexR5 case, the earlier code
+* is left unchanged where the the interrupt processor target
+* registers in the distributor is initialized with the
+* corresponding CPU ID on which the application built over
+* the scugic driver runs. These changes fix CR#937243.
+* 3.3 pkp 05/12/16 Modified XScuGic_InterruptMaptoCpu to write proper value
+* to interrupt target register to fix CR#951848
+*
+* 3.4 asa 04/07/16 Created a new static function DoDistributorInit to
+* simplify the flow and avoid code duplication. Changes are
+* made for USE_AMP use case for R5. In a scenario
+* (in R5 split mode) when one R5 is operating with A53 in
+* open amp config and other R5 running baremetal app, the
+* existing code had the potential to stop the whole AMP
+* solution to work(if for some reason the R5 running the
+* baremetal app tasked to initialize the Distributor hangs
+* or crashes before initializing).Changes are made so that
+* the R5 under AMP first checks if the distributor is
+* enabled or not and if not, it does the standard
+* Distributor initialization.This fixes the CR#952962.
+* 3.4 mus 09/08/16 Added assert to avoid invalid access of GIC from CPUID 1
+* for single core zynq-7000s
+* 3.5 mus 10/05/16 Modified DistributorInit function to avoid
+* re-initialization of distributor, If it is already
+* initialized by other CPU.
+* 3.5 pkp 10/17/16 Modified XScuGic_InterruptMaptoCpu to correct the CPU Id
+* value and properly mask interrupt target processor value
+* to modify interrupt target processor register for a given
+* interrupt ID and cpu ID
+* 3.6 pkp 20/01/17 Added new API XScuGic_Stop to Disable distributor and
+* interrupts in case they are being used only by current
+* cpu. It also removes current cpu from interrupt target
+* registers for all interrupts.
+* kvn 02/17/17 Add support for changing GIC CPU master at run time.
+* kvn 02/28/17 Make the CpuId as static variable and Added new
+* XScugiC_GetCpuId to access CpuId.
+* 3.9 mus 02/21/18 Added new API's XScuGic_UnmapAllInterruptsFromCpu and
+* XScuGic_InterruptUnmapFromCpu, These API's can be used
+* by applications to unmap specific/all interrupts from
+* target CPU. It fixes CR#992490.
+* 3.10 mus 07/17/18 Updated file to fix the various coding style issues
+* reported by checkpatch. It fixes CR#1006344.
+* 3.10 aru 08/23/18 Resolved MISRA-C:2012 compliance mandatory violations
+* It fixes CR#1007753.
+* 3.10 mus 09/19/18 Fix cppcheck warnings
+* 4.0 mus 11/22/18 Fixed bugs in software interrupt generation through
+* XScuGic_SoftwareIntr API
+* 4.1 asa 03/30/19 Made changes not to direct each interrupt to all
+* available CPUs by default. This was breaking AMP
+* behavior. Instead every time an interrupt enable
+* request is received, the interrupt was mapped to
+* the respective CPU. There were several other changes
+* made to implement this. This set of changes was to
+* fix CR-1024716.
+* 4.1 mus 06/19/19 Added API's XScuGic_MarkCoreAsleep and
+* XScuGic_MarkCoreAwake to mark processor core as
+* asleep or awake. Fix for CR#1027220.
+* </pre>
+*
+******************************************************************************/
+
+/***************************** Include Files *********************************/
+#include "xil_types.h"
+#include "xil_assert.h"
+#include "xscugic.h"
+
+/************************** Constant Definitions *****************************/
+
+
+/**************************** Type Definitions *******************************/
+
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/************************** Variable Definitions *****************************/
+static u32 CpuId = XPAR_CPU_ID; /**< CPU Core identifier */
+
+/************************** Function Prototypes ******************************/
+
+static void StubHandler(void *CallBackRef);
+
+/*****************************************************************************/
+/**
+*
+* DoDistributorInit initializes the distributor of the GIC. The
+* initialization entails:
+*
+* - Write the trigger mode, priority
+* - All interrupt sources are disabled
+* - Enable the distributor
+*
+* @param InstancePtr is a pointer to the XScuGic instance.
+*
+* @return None
+*
+* @note None.
+*
+******************************************************************************/
+static void DoDistributorInit(XScuGic *InstancePtr)
+{
+ u32 Int_Id;
+
+#if defined (GICv3)
+ u32 Temp;
+
+ Temp = XScuGic_DistReadReg(InstancePtr, XSCUGIC_DIST_EN_OFFSET);
+ Temp = (XSCUGIC500_DCTLR_ARE_NS_ENABLE | XSCUGIC500_DCTLR_ARE_S_ENABLE);
+ Temp &= ~(XSCUGIC_EN_INT_MASK);
+ XScuGic_DistWriteReg(InstancePtr, XSCUGIC_DIST_EN_OFFSET, Temp);
+#else
+ XScuGic_DistWriteReg(InstancePtr, XSCUGIC_DIST_EN_OFFSET, 0U);
+#endif
+
+ /*
+ * Set the security domains in the int_security registers for
+ * non-secure interrupts
+ * All are secure, so leave at the default. Set to 1 for non-secure
+ * interrupts.
+ */
+
+ /*
+ * For the Shared Peripheral Interrupts INT_ID[MAX..32], set:
+ */
+
+ /*
+ * 1. The trigger mode in the int_config register
+ * Only write to the SPI interrupts, so start at 32
+ */
+ for (Int_Id = 32U; Int_Id < XSCUGIC_MAX_NUM_INTR_INPUTS;
+ Int_Id = Int_Id+16U) {
+ /*
+ * Each INT_ID uses two bits, or 16 INT_ID per register
+ * Set them all to be level sensitive, active HIGH.
+ */
+ XScuGic_DistWriteReg(InstancePtr,
+ XSCUGIC_INT_CFG_OFFSET_CALC(Int_Id),
+ 0U);
+ }
+
+
+#define DEFAULT_PRIORITY 0xa0a0a0a0U
+ for (Int_Id = 0U; Int_Id < XSCUGIC_MAX_NUM_INTR_INPUTS;
+ Int_Id = Int_Id+4U) {
+ /*
+ * 2. The priority using int the priority_level register
+ * The priority_level and spi_target registers use one byte per
+ * INT_ID.
+ * Write a default value that can be changed elsewhere.
+ */
+ XScuGic_DistWriteReg(InstancePtr,
+ XSCUGIC_PRIORITY_OFFSET_CALC(Int_Id),
+ DEFAULT_PRIORITY);
+ }
+
+#if defined (GICv3)
+ for (Int_Id = 0U; Int_Id<XSCUGIC_MAX_NUM_INTR_INPUTS;Int_Id=Int_Id+32U) {
+
+ XScuGic_DistWriteReg(InstancePtr,
+ XSCUGIC_SECURITY_TARGET_OFFSET_CALC(Int_Id),
+ XSCUGIC_DEFAULT_SECURITY);
+ }
+ /*
+ * Set security for SGI/PPI
+ *
+ */
+ XScuGic_ReDistSGIPPIWriteReg(InstancePtr,XSCUGIC_RDIST_IGROUPR_OFFSET,
+ XSCUGIC_DEFAULT_SECURITY);
+#endif
+ for (Int_Id = 0U; Int_Id<XSCUGIC_MAX_NUM_INTR_INPUTS;Int_Id=Int_Id+32U) {
+ /*
+ * 4. Enable the SPI using the enable_set register. Leave all
+ * disabled for now.
+ */
+ XScuGic_DistWriteReg(InstancePtr,
+ XSCUGIC_EN_DIS_OFFSET_CALC(XSCUGIC_DISABLE_OFFSET, Int_Id),
+ 0xFFFFFFFFU);
+
+ }
+#if defined (GICv3)
+ Temp = XScuGic_DistReadReg(InstancePtr, XSCUGIC_DIST_EN_OFFSET);
+ Temp |= XSCUGIC_EN_INT_MASK;
+ XScuGic_DistWriteReg(InstancePtr, XSCUGIC_DIST_EN_OFFSET, Temp);
+ XScuGic_Enable_Group1_Interrupts();
+ XScuGic_Enable_Group0_Interrupts();
+#else
+ XScuGic_DistWriteReg(InstancePtr, XSCUGIC_DIST_EN_OFFSET,
+ XSCUGIC_EN_INT_MASK);
+#endif
+}
+
+/*****************************************************************************/
+/**
+*
+* DistributorInit initializes the distributor of the GIC. It calls
+* DoDistributorInit to finish the initialization.
+*
+* @param InstancePtr is a pointer to the XScuGic instance.
+*
+* @return None
+*
+* @note None.
+*
+******************************************************************************/
+static void DistributorInit(XScuGic *InstancePtr)
+{
+ u32 RegValue;
+
+#if USE_AMP==1 && (defined (ARMA9) || defined(__aarch64__))
+#warning "Building GIC for AMP"
+ /*
+ * GIC initialization is taken care by master CPU in
+ * openamp configuration, so do nothing and return.
+ */
+ return;
+#endif
+
+ Xil_AssertVoid(InstancePtr != NULL);
+ RegValue = XScuGic_DistReadReg(InstancePtr, XSCUGIC_DIST_EN_OFFSET);
+ if ((RegValue & XSCUGIC_EN_INT_MASK) == 0U) {
+ DoDistributorInit(InstancePtr);
+ return;
+ }
+}
+
+#if !defined (GICv3)
+/*****************************************************************************/
+/**
+*
+* CPUInitialize initializes the CPU Interface of the GIC. The initialization
+* entails:
+*
+* - Set the priority of the CPU
+* - Enable the CPU interface
+*
+* @param InstancePtr is a pointer to the XScuGic instance.
+*
+* @return None
+*
+* @note None.
+*
+******************************************************************************/
+static void CPUInitialize(XScuGic *InstancePtr)
+{
+ /*
+ * Program the priority mask of the CPU using the Priority mask register
+ */
+ XScuGic_CPUWriteReg(InstancePtr, XSCUGIC_CPU_PRIOR_OFFSET, 0xF0U);
+
+
+ /*
+ * If the CPU operates in both security domains, set parameters in the
+ * control_s register.
+ * 1. Set FIQen=1 to use FIQ for secure interrupts,
+ * 2. Program the AckCtl bit
+ * 3. Program the SBPR bit to select the binary pointer behavior
+ * 4. Set EnableS = 1 to enable secure interrupts
+ * 5. Set EnbleNS = 1 to enable non secure interrupts
+ */
+
+ /*
+ * If the CPU operates only in the secure domain, setup the
+ * control_s register.
+ * 1. Set FIQen=1,
+ * 2. Set EnableS=1, to enable the CPU interface to signal secure
+ * interrupts. Only enable the IRQ output unless secure interrupts
+ * are needed.
+ */
+ XScuGic_CPUWriteReg(InstancePtr, XSCUGIC_CONTROL_OFFSET, 0x07U);
+
+}
+#endif
+
+/*****************************************************************************/
+/**
+*
+* CfgInitialize a specific interrupt controller instance/driver. The
+* initialization entails:
+*
+* - Initialize fields of the XScuGic structure
+* - Initial vector table with stub function calls
+* - All interrupt sources are disabled
+*
+* @param InstancePtr is a pointer to the XScuGic instance.
+* @param ConfigPtr is a pointer to a config table for the particular
+* device this driver is associated with.
+* @param EffectiveAddr is the device base address in the virtual memory
+* address space. The caller is responsible for keeping the address
+* mapping from EffectiveAddr to the device physical base address
+* unchanged once this function is invoked. Unexpected errors may
+* occur if the address mapping changes after this function is
+* called. If address translation is not used, use
+* Config->BaseAddress for this parameters, passing the physical
+* address instead.
+*
+* @return
+* - XST_SUCCESS if initialization was successful
+*
+* @note None.
+*
+******************************************************************************/
+s32 XScuGic_CfgInitialize(XScuGic *InstancePtr,
+ XScuGic_Config *ConfigPtr,
+ u32 EffectiveAddr)
+{
+ u32 Int_Id;
+ (void) EffectiveAddr;
+
+ Xil_AssertNonvoid(InstancePtr != NULL);
+ Xil_AssertNonvoid(ConfigPtr != NULL);
+ /*
+ * Detect Zynq-7000 base silicon configuration,Dual or Single CPU.
+ * If it is single CPU cnfiguration then invoke assert for CPU ID=1
+ */
+#ifdef ARMA9
+ if (XPAR_CPU_ID == 0x01) {
+ Xil_AssertNonvoid((Xil_In32(XPS_EFUSE_BASEADDR
+ + EFUSE_STATUS_OFFSET) & EFUSE_STATUS_CPU_MASK) == 0);
+ }
+#endif
+
+ if(InstancePtr->IsReady != XIL_COMPONENT_IS_READY) {
+
+ InstancePtr->IsReady = 0U;
+ InstancePtr->Config = ConfigPtr;
+
+
+ for (Int_Id = 0U; Int_Id < XSCUGIC_MAX_NUM_INTR_INPUTS;
+ Int_Id++) {
+ /*
+ * Initialize the handler to point to a stub to handle an
+ * interrupt which has not been connected to a handler
+ * Only initialize it if the handler is 0 which means it
+ * was not initialized statically by the tools/user. Set
+ * the callback reference to this instance so that
+ * unhandled interrupts can be tracked.
+ */
+ if ((InstancePtr->Config->HandlerTable[Int_Id].Handler
+ == (Xil_InterruptHandler)NULL)) {
+ InstancePtr->Config->HandlerTable[Int_Id].Handler
+ = (Xil_InterruptHandler)StubHandler;
+ }
+ InstancePtr->Config->HandlerTable[Int_Id].CallBackRef =
+ InstancePtr;
+ }
+#if defined (GICv3)
+ u32 Waker_State;
+ Waker_State = XScuGic_ReDistReadReg(InstancePtr,XSCUGIC_RDIST_WAKER_OFFSET);
+ XScuGic_ReDistWriteReg(InstancePtr,XSCUGIC_RDIST_WAKER_OFFSET,
+ Waker_State & (~ XSCUGIC_RDIST_WAKER_LOW_POWER_STATE_MASK));
+ /* Enable system reg interface through ICC_SRE_EL1 */
+ #if EL3
+ XScuGic_Enable_SystemReg_CPU_Interface_EL3();
+ #endif
+ XScuGic_Enable_SystemReg_CPU_Interface_EL1();
+ isb();
+#endif
+ XScuGic_Stop(InstancePtr);
+ DistributorInit(InstancePtr);
+#if defined (GICv3)
+ XScuGic_set_priority_filter(0xff);
+#else
+ CPUInitialize(InstancePtr);
+#endif
+ InstancePtr->IsReady = XIL_COMPONENT_IS_READY;
+ }
+
+ return XST_SUCCESS;
+}
+
+/*****************************************************************************/
+/**
+*
+* Makes the connection between the Int_Id of the interrupt source and the
+* associated handler that is to run when the interrupt is recognized. The
+* argument provided in this call as the Callbackref is used as the argument
+* for the handler when it is called.
+*
+* @param InstancePtr is a pointer to the XScuGic instance.
+* @param Int_Id contains the ID of the interrupt source and should be
+* in the range of 0 to XSCUGIC_MAX_NUM_INTR_INPUTS - 1
+* @param Handler to the handler for that interrupt.
+* @param CallBackRef is the callback reference, usually the instance
+* pointer of the connecting driver.
+*
+* @return
+*
+* - XST_SUCCESS if the handler was connected correctly.
+*
+* @note
+*
+* WARNING: The handler provided as an argument will overwrite any handler
+* that was previously connected.
+*
+****************************************************************************/
+s32 XScuGic_Connect(XScuGic *InstancePtr, u32 Int_Id,
+ Xil_InterruptHandler Handler, void *CallBackRef)
+{
+ /*
+ * Assert the arguments
+ */
+ Xil_AssertNonvoid(InstancePtr != NULL);
+ Xil_AssertNonvoid(Int_Id < XSCUGIC_MAX_NUM_INTR_INPUTS);
+ Xil_AssertNonvoid(Handler != NULL);
+ Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+ /*
+ * The Int_Id is used as an index into the table to select the proper
+ * handler
+ */
+ InstancePtr->Config->HandlerTable[Int_Id].Handler = (Xil_InterruptHandler)Handler;
+ InstancePtr->Config->HandlerTable[Int_Id].CallBackRef = CallBackRef;
+
+ return XST_SUCCESS;
+}
+
+/*****************************************************************************/
+/**
+*
+* Updates the interrupt table with the Null Handler and NULL arguments at the
+* location pointed at by the Int_Id. This effectively disconnects that interrupt
+* source from any handler. The interrupt is disabled also.
+*
+* @param InstancePtr is a pointer to the XScuGic instance to be worked on.
+* @param Int_Id contains the ID of the interrupt source and should
+* be in the range of 0 to XSCUGIC_MAX_NUM_INTR_INPUTS - 1
+*
+* @return None.
+*
+* @note None.
+*
+****************************************************************************/
+void XScuGic_Disconnect(XScuGic *InstancePtr, u32 Int_Id)
+{
+ u32 Mask;
+
+ /*
+ * Assert the arguments
+ */
+ Xil_AssertVoid(InstancePtr != NULL);
+ Xil_AssertVoid(Int_Id < XSCUGIC_MAX_NUM_INTR_INPUTS);
+ Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+ /*
+ * The Int_Id is used to create the appropriate mask for the
+ * desired bit position. Int_Id currently limited to 0 - 31
+ */
+ Mask = 0x00000001U << (Int_Id % 32U);
+
+ /*
+ * Disable the interrupt such that it won't occur while disconnecting
+ * the handler, only disable the specified interrupt id without
+ * modifying the other interrupt ids
+ */
+ XScuGic_DistWriteReg(InstancePtr, (u32)XSCUGIC_DISABLE_OFFSET +
+ ((Int_Id / 32U) * 4U), Mask);
+
+ /*
+ * Disconnect the handler and connect a stub, the callback reference
+ * must be set to this instance to allow unhandled interrupts to be
+ * tracked
+ */
+ InstancePtr->Config->HandlerTable[Int_Id].Handler = (Xil_InterruptHandler)StubHandler;
+ InstancePtr->Config->HandlerTable[Int_Id].CallBackRef = InstancePtr;
+}
+
+/*****************************************************************************/
+/**
+*
+* Enables the interrupt source provided as the argument Int_Id. Any pending
+* interrupt condition for the specified Int_Id will occur after this function is
+* called.
+* This API also maps the interrupt to the requesting CPU.
+*
+* @param InstancePtr is a pointer to the XScuGic instance.
+* @param Int_Id contains the ID of the interrupt source and should be
+* in the range of 0 to XSCUGIC_MAX_NUM_INTR_INPUTS - 1
+*
+* @return None.
+*
+* @note None.
+*
+****************************************************************************/
+void XScuGic_Enable(XScuGic *InstancePtr, u32 Int_Id)
+{
+ u32 Mask;
+ u8 Cpu_Id = (u8)CpuId;
+
+#if defined (GICv3)
+ u32 Temp;
+#endif
+ /*
+ * Assert the arguments
+ */
+ Xil_AssertVoid(InstancePtr != NULL);
+ Xil_AssertVoid(Int_Id < XSCUGIC_MAX_NUM_INTR_INPUTS);
+ Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+#if defined (GICv3)
+ if (Int_Id < XSCUGIC_SPI_INT_ID_START) {
+ XScuGic_InterruptMaptoCpu(InstancePtr, Cpu_Id, Int_Id);
+
+ Int_Id &= 0x1f;
+ Int_Id = 1 << Int_Id;
+
+ Temp = XScuGic_ReDistSGIPPIReadReg(InstancePtr,XSCUGIC_RDIST_ISENABLE_OFFSET);
+ Temp |= Int_Id;
+ XScuGic_ReDistSGIPPIWriteReg(InstancePtr,XSCUGIC_RDIST_ISENABLE_OFFSET,Temp);
+ }
+#endif
+ XScuGic_InterruptMaptoCpu(InstancePtr, Cpu_Id, Int_Id);
+ /*
+ * The Int_Id is used to create the appropriate mask for the
+ * desired bit position.
+ */
+ Mask = 0x00000001U << (Int_Id % 32U);
+ /*
+ * Enable the selected interrupt source by setting the
+ * corresponding bit in the Enable Set register.
+ */
+ XScuGic_DistWriteReg(InstancePtr, (u32)XSCUGIC_ENABLE_SET_OFFSET +
+ ((Int_Id / 32U) * 4U), Mask);
+}
+
+/*****************************************************************************/
+/**
+*
+* Disables the interrupt source provided as the argument Int_Id such that the
+* interrupt controller will not cause interrupts for the specified Int_Id. The
+* interrupt controller will continue to hold an interrupt condition for the
+* Int_Id, but will not cause an interrupt.
+* This API also unmaps the interrupt for the requesting CPU.
+*
+* @param InstancePtr is a pointer to the XScuGic instance.
+* @param Int_Id contains the ID of the interrupt source and should be
+* in the range of 0 to XSCUGIC_MAX_NUM_INTR_INPUTS - 1
+*
+* @return None.
+*
+* @note None.
+*
+****************************************************************************/
+void XScuGic_Disable(XScuGic *InstancePtr, u32 Int_Id)
+{
+ u32 Mask;
+ u8 Cpu_Id = (u8)CpuId;
+#if defined (GICv3)
+ u32 Temp;
+#endif
+
+ /*
+ * Assert the arguments
+ */
+ Xil_AssertVoid(InstancePtr != NULL);
+ Xil_AssertVoid(Int_Id < XSCUGIC_MAX_NUM_INTR_INPUTS);
+ Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+#if defined (GICv3)
+ if (Int_Id < XSCUGIC_SPI_INT_ID_START) {
+
+ XScuGic_InterruptUnmapFromCpu(InstancePtr, Cpu_Id, Int_Id);
+
+ Int_Id &= 0x1f;
+ Int_Id = 1 << Int_Id;
+
+ Temp = XScuGic_ReDistSGIPPIReadReg(InstancePtr,XSCUGIC_RDIST_ISENABLE_OFFSET);
+ Temp &= ~Int_Id;
+ XScuGic_ReDistSGIPPIWriteReg(InstancePtr,XSCUGIC_RDIST_ISENABLE_OFFSET,Temp);
+ }
+#endif
+ XScuGic_InterruptUnmapFromCpu(InstancePtr, Cpu_Id, Int_Id);
+ /*
+ * The Int_Id is used to create the appropriate mask for the
+ * desired bit position. Int_Id currently limited to 0 - 31
+ */
+ Mask = 0x00000001U << (Int_Id % 32U);
+
+ /*
+ * Disable the selected interrupt source by setting the
+ * corresponding bit in the IDR.
+ */
+ XScuGic_DistWriteReg(InstancePtr, (u32)XSCUGIC_DISABLE_OFFSET +
+ ((Int_Id / 32U) * 4U), Mask);
+}
+
+/*****************************************************************************/
+/**
+*
+* Allows software to simulate an interrupt in the interrupt controller. This
+* function will only be successful when the interrupt controller has been
+* started in simulation mode. A simulated interrupt allows the interrupt
+* controller to be tested without any device to drive an interrupt input
+* signal into it.
+*
+* @param InstancePtr is a pointer to the XScuGic instance.
+* @param Int_Id is the software interrupt ID to simulate an interrupt.
+* @param Cpu_Id is the list of CPUs to send the interrupt.
+*
+* @return
+*
+* XST_SUCCESS if successful, or XST_FAILURE if the interrupt could not be
+* simulated
+*
+* @note None.
+*
+******************************************************************************/
+s32 XScuGic_SoftwareIntr(XScuGic *InstancePtr, u32 Int_Id, u32 Cpu_Id)
+{
+ u32 Mask;
+
+ /*
+ * Assert the arguments
+ */
+ Xil_AssertNonvoid(InstancePtr != NULL);
+ Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+ Xil_AssertNonvoid(Int_Id <= 15U);
+ Xil_AssertNonvoid(Cpu_Id <= 255U);
+
+#if defined (GICv3)
+ Mask = (Cpu_Id | (Int_Id << XSCUGIC_SGIR_EL1_INITID_SHIFT));
+#if EL3
+ XScuGic_WriteICC_SGI0R_EL1(Mask);
+#else
+ XScuGic_WriteICC_SGI1R_EL1(Mask);
+#endif
+#else
+
+ /*
+ * The Int_Id is used to create the appropriate mask for the
+ * desired interrupt. Int_Id currently limited to 0 - 15
+ * Use the target list for the Cpu ID.
+ */
+ Mask = ((Cpu_Id << 16U) | Int_Id) &
+ (XSCUGIC_SFI_TRIG_CPU_MASK | XSCUGIC_SFI_TRIG_INTID_MASK);
+
+ /*
+ * Write to the Software interrupt trigger register. Use the appropriate
+ * CPU Int_Id.
+ */
+ XScuGic_DistWriteReg(InstancePtr, XSCUGIC_SFI_TRIG_OFFSET, Mask);
+
+ /* Indicate the interrupt was successfully simulated */
+#endif
+ return XST_SUCCESS;
+}
+
+/*****************************************************************************/
+/**
+*
+* A stub for the asynchronous callback. The stub is here in case the upper
+* layers forget to set the handler.
+*
+* @param CallBackRef is a pointer to the upper layer callback reference
+*
+* @return None.
+*
+* @note None.
+*
+******************************************************************************/
+static void StubHandler(void *CallBackRef)
+{
+ /*
+ * verify that the inputs are valid
+ */
+ Xil_AssertVoid(CallBackRef != NULL);
+
+ /*
+ * Indicate another unhandled interrupt for stats
+ */
+ ((XScuGic *)((void *)CallBackRef))->UnhandledInterrupts++;
+}
+
+/****************************************************************************/
+/**
+* Sets the interrupt priority and trigger type for the specificd IRQ source.
+*
+* @param InstancePtr is a pointer to the instance to be worked on.
+* @param Int_Id is the IRQ source number to modify
+* @param Priority is the new priority for the IRQ source. 0 is highest
+* priority, 0xF8(248) is lowest. There are 32 priority levels
+* supported with a step of 8. Hence the supported priorities are
+* 0, 8, 16, 32, 40 ..., 248.
+* @param Trigger is the new trigger type for the IRQ source.
+* Each bit pair describes the configuration for an INT_ID.
+* SFI Read Only b10 always
+* PPI Read Only depending on how the PPIs are configured.
+* b01 Active HIGH level sensitive
+* b11 Rising edge sensitive
+* SPI LSB is read only.
+* b01 Active HIGH level sensitive
+* b11 Rising edge sensitive/
+*
+* @return None.
+*
+* @note None.
+*
+*****************************************************************************/
+void XScuGic_SetPriorityTriggerType(XScuGic *InstancePtr, u32 Int_Id,
+ u8 Priority, u8 Trigger)
+{
+ u32 RegValue;
+#if defined (GICv3)
+ u32 Temp;
+ u32 Index;
+#endif
+ u8 LocalPriority;
+ LocalPriority = Priority;
+
+ Xil_AssertVoid(InstancePtr != NULL);
+ Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+ Xil_AssertVoid(Int_Id < XSCUGIC_MAX_NUM_INTR_INPUTS);
+ Xil_AssertVoid(Trigger <= (u8)XSCUGIC_INT_CFG_MASK);
+ Xil_AssertVoid(LocalPriority <= (u8)XSCUGIC_MAX_INTR_PRIO_VAL);
+#if defined (GICv3)
+ if (Int_Id < XSCUGIC_SPI_INT_ID_START )
+ {
+ XScuGic_ReDistSGIPPIWriteReg(InstancePtr,XSCUGIC_RDIST_INT_PRIORITY_OFFSET_CALC(Int_Id),Priority);
+ Temp = XScuGic_ReDistSGIPPIReadReg(InstancePtr,XSCUGIC_RDIST_INT_CONFIG_OFFSET_CALC(Int_Id));
+ Index = XScuGic_Get_Rdist_Int_Trigger_Index(Int_Id);
+ Temp |= (Trigger << Index);
+ XScuGic_ReDistSGIPPIWriteReg(InstancePtr,XSCUGIC_RDIST_INT_CONFIG_OFFSET_CALC(Int_Id),Temp);
+ return;
+ }
+#endif
+
+ /*
+ * Determine the register to write to using the Int_Id.
+ */
+ RegValue = XScuGic_DistReadReg(InstancePtr,
+ XSCUGIC_PRIORITY_OFFSET_CALC(Int_Id));
+
+ /*
+ * The priority bits are Bits 7 to 3 in GIC Priority Register. This
+ * means the number of priority levels supported are 32 and they are
+ * in steps of 8. The priorities can be 0, 8, 16, 32, 48, ... etc.
+ * The lower order 3 bits are masked before putting it in the register.
+ */
+ LocalPriority = LocalPriority & (u8)XSCUGIC_INTR_PRIO_MASK;
+ /*
+ * Shift and Mask the correct bits for the priority and trigger in the
+ * register
+ */
+ RegValue &= ~(XSCUGIC_PRIORITY_MASK << ((Int_Id%4U)*8U));
+ RegValue |= (u32)LocalPriority << ((Int_Id%4U)*8U);
+
+ /*
+ * Write the value back to the register.
+ */
+ XScuGic_DistWriteReg(InstancePtr, XSCUGIC_PRIORITY_OFFSET_CALC(Int_Id),
+ RegValue);
+
+ /*
+ * Determine the register to write to using the Int_Id.
+ */
+ RegValue = XScuGic_DistReadReg(InstancePtr,
+ XSCUGIC_INT_CFG_OFFSET_CALC(Int_Id));
+
+ /*
+ * Shift and Mask the correct bits for the priority and trigger in the
+ * register
+ */
+ RegValue &= ~(XSCUGIC_INT_CFG_MASK << ((Int_Id%16U)*2U));
+ RegValue |= (u32)Trigger << ((Int_Id%16U)*2U);
+
+ /*
+ * Write the value back to the register.
+ */
+ XScuGic_DistWriteReg(InstancePtr, XSCUGIC_INT_CFG_OFFSET_CALC(Int_Id),
+ RegValue);
+
+}
+
+/****************************************************************************/
+/**
+* Gets the interrupt priority and trigger type for the specificd IRQ source.
+*
+* @param InstancePtr is a pointer to the instance to be worked on.
+* @param Int_Id is the IRQ source number to modify
+* @param Priority is a pointer to the value of the priority of the IRQ
+* source. This is a return value.
+* @param Trigger is pointer to the value of the trigger of the IRQ
+* source. This is a return value.
+*
+* @return None.
+*
+* @note None
+*
+*****************************************************************************/
+void XScuGic_GetPriorityTriggerType(XScuGic *InstancePtr, u32 Int_Id,
+ u8 *Priority, u8 *Trigger)
+{
+ u32 RegValue;
+
+ Xil_AssertVoid(InstancePtr != NULL);
+ Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+ Xil_AssertVoid(Int_Id < XSCUGIC_MAX_NUM_INTR_INPUTS);
+ Xil_AssertVoid(Priority != NULL);
+ Xil_AssertVoid(Trigger != NULL);
+
+ /*
+ * Determine the register to read to using the Int_Id.
+ */
+ RegValue = XScuGic_DistReadReg(InstancePtr,
+ XSCUGIC_PRIORITY_OFFSET_CALC(Int_Id));
+
+ /*
+ * Shift and Mask the correct bits for the priority and trigger in the
+ * register
+ */
+ RegValue = RegValue >> ((Int_Id%4U)*8U);
+ *Priority = (u8)(RegValue & XSCUGIC_PRIORITY_MASK);
+
+ /*
+ * Determine the register to read to using the Int_Id.
+ */
+ RegValue = XScuGic_DistReadReg(InstancePtr,
+ XSCUGIC_INT_CFG_OFFSET_CALC(Int_Id));
+
+ /*
+ * Shift and Mask the correct bits for the priority and trigger in the
+ * register
+ */
+ RegValue = RegValue >> ((Int_Id%16U)*2U);
+
+ *Trigger = (u8)(RegValue & XSCUGIC_INT_CFG_MASK);
+}
+/****************************************************************************/
+/**
+* Sets the target CPU for the interrupt of a peripheral
+*
+* @param InstancePtr is a pointer to the instance to be worked on.
+* @param Cpu_Id is a CPU number for which the interrupt has to be targeted
+* @param Int_Id is the IRQ source number to modify
+*
+* @return None.
+*
+* @note None
+*
+*****************************************************************************/
+void XScuGic_InterruptMaptoCpu(XScuGic *InstancePtr, u8 Cpu_Id, u32 Int_Id)
+{
+ u32 RegValue;
+
+#if defined (GICv3)
+ u32 Temp;
+ Xil_AssertVoid(InstancePtr != NULL);
+ if (Int_Id >= 32) {
+ Temp = Int_Id - 32;
+ RegValue = XScuGic_DistReadReg(InstancePtr,
+ XSCUGIC_IROUTER_OFFSET_CALC(Temp));
+ RegValue |= Cpu_Id;
+ XScuGic_DistWriteReg(InstancePtr, XSCUGIC_IROUTER_OFFSET_CALC(Temp),
+ (Cpu_Id-1));
+ }
+#else
+ u32 Offset;
+ Xil_AssertVoid(InstancePtr != NULL);
+ RegValue = XScuGic_DistReadReg(InstancePtr,
+ XSCUGIC_SPI_TARGET_OFFSET_CALC(Int_Id));
+
+ Offset = (Int_Id & 0x3U);
+ Cpu_Id = (0x1U << Cpu_Id);
+
+ RegValue |= (Cpu_Id) << (Offset*8U);
+ XScuGic_DistWriteReg(InstancePtr,
+ XSCUGIC_SPI_TARGET_OFFSET_CALC(Int_Id),
+ RegValue);
+#endif
+}
+/****************************************************************************/
+/**
+* Unmaps specific SPI interrupt from the target CPU
+*
+* @param InstancePtr is a pointer to the instance to be worked on.
+* @param Cpu_Id is a CPU number from which the interrupt has to be
+* unmapped
+* @param Int_Id is the IRQ source number to modify
+*
+* @return None.
+*
+* @note None
+*
+*****************************************************************************/
+void XScuGic_InterruptUnmapFromCpu(XScuGic *InstancePtr, u8 Cpu_Id, u32 Int_Id)
+{
+ u32 RegValue;
+
+#if defined (GICv3)
+ u32 Temp;
+ Xil_AssertVoid(InstancePtr != NULL);
+ if (Int_Id >= 32) {
+ Temp = Int_Id - 32;
+ RegValue = XScuGic_DistReadReg(InstancePtr,
+ XSCUGIC_IROUTER_OFFSET_CALC(Temp));
+ RegValue &= ~Cpu_Id;
+ XScuGic_DistWriteReg(InstancePtr, XSCUGIC_IROUTER_OFFSET_CALC(Temp),
+ (Cpu_Id-1));
+ }
+#else
+ u32 Offset;
+ Xil_AssertVoid(InstancePtr != NULL);
+ RegValue = XScuGic_DistReadReg(InstancePtr,
+ XSCUGIC_SPI_TARGET_OFFSET_CALC(Int_Id));
+
+ Offset = (Int_Id & 0x3U);
+ Cpu_Id = (0x1U << Cpu_Id);
+
+ RegValue &= ~(Cpu_Id << (Offset*8U));
+ XScuGic_DistWriteReg(InstancePtr,
+ XSCUGIC_SPI_TARGET_OFFSET_CALC(Int_Id),
+ RegValue);
+#endif
+}
+/****************************************************************************/
+/**
+* Unmaps all SPI interrupts from the target CPU
+*
+* @param InstancePtr is a pointer to the instance to be worked on.
+* @param Cpu_Id is a CPU number from which the interrupts has to be
+* unmapped
+*
+* @return None.
+*
+* @note None
+*
+*****************************************************************************/
+void XScuGic_UnmapAllInterruptsFromCpu(XScuGic *InstancePtr, u8 Cpu_Id)
+{
+ u32 Int_Id;
+ u32 Target_Cpu;
+ u32 LocalCpuID = (1U << Cpu_Id);
+
+ Xil_AssertVoid(InstancePtr != NULL);
+
+ LocalCpuID |= LocalCpuID << 8U;
+ LocalCpuID |= LocalCpuID << 16U;
+
+ for (Int_Id = 32U; Int_Id < XSCUGIC_MAX_NUM_INTR_INPUTS;
+ Int_Id = Int_Id+4U) {
+
+ Target_Cpu = XScuGic_DistReadReg(InstancePtr,
+ XSCUGIC_SPI_TARGET_OFFSET_CALC(Int_Id));
+ /* Remove LocalCpuID from interrupt target register */
+ Target_Cpu &= (~LocalCpuID);
+ XScuGic_DistWriteReg(InstancePtr,
+ XSCUGIC_SPI_TARGET_OFFSET_CALC(Int_Id), Target_Cpu);
+
+ }
+}
+/****************************************************************************/
+/**
+* It checks if the interrupt target register contains all interrupts to be
+* targeted for current CPU. If they are programmed to be forwarded to current
+* cpu, this API disable all interrupts and disable GIC distributor.
+* This API also removes current CPU from interrupt target registers for all
+* interrupt.
+*
+* @param InstancePtr is a pointer to the instance to be worked on.
+*
+* @return None.
+*
+* @note None
+*
+*****************************************************************************/
+void XScuGic_Stop(XScuGic *InstancePtr)
+{
+ u32 Int_Id;
+ u32 RegValue;
+ u32 Target_Cpu;
+ u32 DistDisable = 1; /* Track distributor status*/
+ u32 LocalCpuID = ((u32)0x1 << CpuId);
+
+ Xil_AssertVoid(InstancePtr != NULL);
+
+ /* If distributor is already disabled, no need to do anything */
+ RegValue = XScuGic_DistReadReg(InstancePtr, XSCUGIC_DIST_EN_OFFSET);
+ if ((RegValue & XSCUGIC_EN_INT_MASK) == 0U) {
+ return;
+ }
+
+ LocalCpuID |= LocalCpuID << 8U;
+ LocalCpuID |= LocalCpuID << 16U;
+
+ /*
+ * Check if the interrupt are targeted to current cpu only or not.
+ * Also remove current cpu from interrupt target register for all
+ * interrupts.
+ */
+ for (Int_Id = 32U; Int_Id < XSCUGIC_MAX_NUM_INTR_INPUTS;
+ Int_Id = Int_Id+4U) {
+
+ Target_Cpu = XScuGic_DistReadReg(InstancePtr,
+ XSCUGIC_SPI_TARGET_OFFSET_CALC(Int_Id));
+ if ((Target_Cpu != LocalCpuID) && (Target_Cpu != 0)) {
+ /*
+ * If any other CPU is also programmed to target
+ * register, GIC distributor can not be disabled.
+ */
+ DistDisable = 0;
+ }
+
+ /* Remove current CPU from interrupt target register */
+ Target_Cpu &= (~LocalCpuID);
+ XScuGic_DistWriteReg(InstancePtr,
+ XSCUGIC_SPI_TARGET_OFFSET_CALC(Int_Id), Target_Cpu);
+
+ }
+
+ /*
+ * If GIC distributor is safe to be disabled, disable all the interrupt
+ * and then disable distributor.
+ */
+ if (DistDisable == 1) {
+ for (Int_Id = 0U; Int_Id < XSCUGIC_MAX_NUM_INTR_INPUTS;
+ Int_Id = Int_Id+32U) {
+ /*
+ * Disable all the interrupts
+ */
+ XScuGic_DistWriteReg(InstancePtr,
+ XSCUGIC_EN_DIS_OFFSET_CALC(XSCUGIC_DISABLE_OFFSET,
+ Int_Id),
+ 0xFFFFFFFFU);
+ }
+ XScuGic_DistWriteReg(InstancePtr, XSCUGIC_DIST_EN_OFFSET, 0U);
+ }
+}
+
+/****************************************************************************/
+/**
+* This updates the CpuId global variable.
+*
+* @param CpuCoreId is the CPU core number.
+*
+* @return None.
+*
+* @note None
+*
+*****************************************************************************/
+void XScuGic_SetCpuID(u32 CpuCoreId)
+{
+ Xil_AssertVoid(CpuCoreId <= 1U);
+
+ CpuId = CpuCoreId;
+}
+
+/****************************************************************************/
+/**
+* This function returns the CpuId variable.
+*
+* @return The CPU core number.
+*
+* @note None.
+*
+*****************************************************************************/
+u32 XScuGic_GetCpuID(void)
+{
+ return CpuId;
+}
+
+#if defined (GICv3)
+/****************************************************************************/
+/**
+* It marks processor core which calls this API as asleep
+*
+* @return None.
+*
+* @note It should be called before suspending processor core. Once this
+* API is invoked, pending interrupts for processor core asserts
+* WakeRequest, to indicate that the PE is to have its power
+* restored Incase of Versal SoC, WakeRequest will be consumed by
+* psv_psm processor and psmfw will wake up APU processor core.
+*
+*****************************************************************************/
+void XScuGic_MarkCoreAsleep(XScuGic *InstancePtr)
+{
+ u32 Waker_State;
+
+ Waker_State = XScuGic_ReDistReadReg(InstancePtr,XSCUGIC_RDIST_WAKER_OFFSET);
+ XScuGic_ReDistWriteReg(InstancePtr,XSCUGIC_RDIST_WAKER_OFFSET,
+ Waker_State |
+ XSCUGIC_RDIST_WAKER_LOW_POWER_STATE_MASK);
+}
+
+/****************************************************************************/
+/**
+* It marks processor core which calls this API as awake
+*
+* @return None.
+*
+* @note None
+*
+*****************************************************************************/
+void XScuGic_MarkCoreAwake(XScuGic *InstancePtr)
+{
+ u32 Waker_State;
+
+ Waker_State = XScuGic_ReDistReadReg(InstancePtr,
+ XSCUGIC_RDIST_WAKER_OFFSET);
+ XScuGic_ReDistWriteReg(InstancePtr,XSCUGIC_RDIST_WAKER_OFFSET,
+ Waker_State &
+ (~ XSCUGIC_RDIST_WAKER_LOW_POWER_STATE_MASK));
+}
+#endif
+/** @} */
diff --git a/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/scugic_v4_1/src/xscugic.h b/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/scugic_v4_1/src/xscugic.h
new file mode 100644
index 0000000..10dc3dc
--- /dev/null
+++ b/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/scugic_v4_1/src/xscugic.h
@@ -0,0 +1,610 @@
+/******************************************************************************
+*
+* Copyright (C) 2010 - 2019 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+* THE SOFTWARE.
+*
+*
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xscugic.h
+* @addtogroup scugic_v4_0
+* @{
+* @details
+*
+* The generic interrupt controller driver component.
+*
+* The interrupt controller driver uses the idea of priority for the various
+* handlers. Priority is an integer within the range of 1 and 31 inclusive with
+* default of 1 being the highest priority interrupt source. The priorities
+* of the various sources can be dynamically altered as needed through
+* hardware configuration.
+*
+* The generic interrupt controller supports the following
+* features:
+*
+* - specific individual interrupt enabling/disabling
+* - specific individual interrupt acknowledging
+* - attaching specific callback function to handle interrupt source
+* - assigning desired priority to interrupt source if default is not
+* acceptable.
+*
+* Details about connecting the interrupt handler of the driver are contained
+* in the source file specific to interrupt processing, xscugic_intr.c.
+*
+* This driver is intended to be RTOS and processor independent. It works with
+* physical addresses only. Any needs for dynamic memory management, threads
+* or thread mutual exclusion, virtual memory, or cache control must be
+* satisfied by the layer above this driver.
+*
+* <b>Interrupt Vector Tables</b>
+*
+* The device ID of the interrupt controller device is used by the driver as a
+* direct index into the configuration data table. The user should populate the
+* vector table with handlers and callbacks at run-time using the
+* XScuGic_Connect() and XScuGic_Disconnect() functions.
+*
+* Each vector table entry corresponds to a device that can generate an
+* interrupt. Each entry contains an interrupt handler function and an
+* argument to be passed to the handler when an interrupt occurs. The
+* user must use XScuGic_Connect() when the interrupt handler takes an
+* argument other than the base address.
+*
+* <b>Nested Interrupts Processing</b>
+*
+* Nested interrupts are not supported by this driver.
+*
+* NOTE:
+* The generic interrupt controller is not a part of the snoop control unit
+* as indicated by the prefix "scu" in the name of the driver.
+* It is an independent module in APU.
+*
+* <pre>
+* MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ----- ---- -------- ---------------------------------------------------------
+* 1.00a drg 01/19/00 First release
+* 1.01a sdm 11/09/11 The XScuGic and XScuGic_Config structures have changed.
+* The HandlerTable (of type XScuGic_VectorTableEntry) is
+* moved to XScuGic_Config structure from XScuGic structure.
+*
+* The "Config" entry in XScuGic structure is made as
+* pointer for better efficiency.
+*
+* A new file named as xscugic_hw.c is now added. It is
+* to implement low level driver routines without using
+* any xscugic instance pointer. They are useful when the
+* user wants to use xscugic through device id or
+* base address. The driver routines provided are explained
+* below.
+* XScuGic_DeviceInitialize that takes device id as
+* argument and initializes the device (without calling
+* XScuGic_CfgInitialize).
+* XScuGic_DeviceInterruptHandler that takes device id
+* as argument and calls appropriate handlers from the
+* HandlerTable.
+* XScuGic_RegisterHandler that registers a new handler
+* by taking xscugic hardware base address as argument.
+* LookupConfigByBaseAddress is used to return the
+* corresponding config structure from XScuGic_ConfigTable
+* based on the scugic base address passed.
+* 1.02a sdm 12/20/11 Removed AckBeforeService from the XScuGic_Config
+* structure.
+* 1.03a srt 02/27/13 Moved Offset calculation macros from *.c and *_hw.c to
+* *_hw.h
+* Added APIs
+* - XScuGic_SetPriTrigTypeByDistAddr()
+* - XScuGic_GetPriTrigTypeByDistAddr()
+* (CR 702687)
+* Added support to direct interrupts to the appropriate CPU. Earlier
+* interrupts were directed to CPU1 (hard coded). Now depending
+* upon the CPU selected by the user (xparameters.h), interrupts
+* will be directed to the relevant CPU. This fixes CR 699688.
+* 1.04a hk 05/04/13 Assigned EffectiveAddr to CpuBaseAddress in
+* XScuGic_CfgInitialize. Fix for CR#704400 to remove warnings.
+* Moved functions XScuGic_SetPriTrigTypeByDistAddr and
+* XScuGic_GetPriTrigTypeByDistAddr to xscugic_hw.c.
+* This is fix for CR#705621.
+* 1.05a hk 06/26/13 Modified tcl to export external interrupts correctly to
+* xparameters.h. Fix for CR's 690505, 708928 & 719359.
+* 2.0 adk 12/10/13 Updated as per the New Tcl API's
+* 2.1 adk 25/04/14 Fixed the CR:789373 changes are made in the driver tcl file.
+* 3.00 kvn 02/13/15 Modified code for MISRA-C:2012 compliance.
+* 3.2 asa 02/29/16 Modified DistributorInit function for Zynq AMP case. The
+* distributor is left uninitialized for Zynq AMP. It is assumed
+* that the distributor will be initialized by Linux master. However
+* for CortexR5 case, the earlier code is left unchanged where the
+* the interrupt processor target registers in the distributor is
+* initialized with the corresponding CPU ID on which the application
+* built over the scugic driver runs.
+* These changes fix CR#937243.
+*
+* 3.4 asa 04/07/16 Created a new static function DoDistributorInit to simplify
+* the flow and avoid code duplication. Changes are made for
+* USE_AMP use case for R5. In a scenario (in R5 split mode) when
+* one R5 is operating with A53 in open amp config and other
+* R5 running baremetal app, the existing code
+* had the potential to stop the whole AMP solution to work (if
+* for some reason the R5 running the baremetal app tasked to
+* initialize the Distributor hangs or crashes before initializing).
+* Changes are made so that the R5 under AMP first checks if
+* the distributor is enabled or not and if not, it does the
+* standard Distributor initialization.
+* This fixes the CR#952962.
+* 3.6 ms 01/23/17 Modified xil_printf statement in main function for all
+* examples to ensure that "Successfully ran" and "Failed"
+* strings are available in all examples. This is a fix
+* for CR-965028.
+* kvn 02/17/17 Add support for changing GIC CPU master at run time.
+* kvn 02/28/17 Make the CpuId as static variable and Added new
+* XScugiC_GetCpuId to access CpuId.
+* ms 03/17/17 Added readme.txt file in examples folder for doxygen
+* generation.
+* 3.7 ms 04/11/17 Modified tcl file to add suffix U for all macro
+* definitions of scugic in xparameters.h
+* 3.8 mus 07/05/17 Updated scugic.tcl to add support for interrupts connected
+* through util_reduced_vector IP(OR gate)
+* mus 07/05/17 Updated xdefine_zynq_canonical_xpars proc to initialize
+* the HandlerTable in XScuGic_ConfigTable to 0, it removes
+* the compilation warning in xscugic_g.c. Fix for CR#978736.
+* mus 07/25/17 Updated xdefine_gic_params proc to export correct canonical
+* definitions for pl to ps interrupts.Fix for CR#980534
+* 3.9 mus 02/21/18 Added new API's XScuGic_UnmapAllInterruptsFromCpu and
+* XScuGic_InterruptUnmapFromCpu, These API's can be used
+* by applications to unmap specific/all interrupts from
+* target CPU.
+* 3.10 aru 08/23/18 Resolved MISRA-C:2012 compliance mandatory violations
+* 4.0 mus 11/22/18 Fixed bugs in software interrupt generation through
+* XScuGic_SoftwareIntr API
+* 4.1 asa 03/30/19 Made changes not to direct each interrupt to all
+* available CPUs by default. This was breaking AMP
+* behavior. Instead every time an interrupt enable
+* request is received, the interrupt was mapped to
+* the respective CPU. There were several other changes
+* made to implement this. This set of changes was to
+* fix CR-1024716.
+* 4.1 mus 06/19/19 Added API's XScuGic_MarkCoreAsleep and
+* XScuGic_MarkCoreAwake to mark processor core as
+* asleep or awake. Fix for CR#1027220.
+*
+* </pre>
+*
+******************************************************************************/
+
+#ifndef XSCUGIC_H /* prevent circular inclusions */
+#define XSCUGIC_H /* by using protection macros */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+
+/***************************** Include Files *********************************/
+
+#include "xstatus.h"
+#include "xil_io.h"
+#include "xscugic_hw.h"
+#include "xil_exception.h"
+
+/************************** Constant Definitions *****************************/
+
+#define EFUSE_STATUS_OFFSET 0x10
+#define EFUSE_STATUS_CPU_MASK 0x80
+
+#if !defined (ARMR5) && !defined (__aarch64__) && !defined (ARMA53_32)
+#define ARMA9
+#endif
+
+#define XSCUGIC500_DCTLR_ARE_NS_ENABLE 0x20
+#define XSCUGIC500_DCTLR_ARE_S_ENABLE 0x10
+/**************************** Type Definitions *******************************/
+
+/* The following data type defines each entry in an interrupt vector table.
+ * The callback reference is the base address of the interrupting device
+ * for the low level driver and an instance pointer for the high level driver.
+ */
+typedef struct
+{
+ Xil_InterruptHandler Handler;
+ void *CallBackRef;
+} XScuGic_VectorTableEntry;
+
+/**
+ * This typedef contains configuration information for the device.
+ */
+typedef struct
+{
+ u16 DeviceId; /**< Unique ID of device */
+ u32 CpuBaseAddress; /**< CPU Interface Register base address */
+ u32 DistBaseAddress; /**< Distributor Register base address */
+ XScuGic_VectorTableEntry HandlerTable[XSCUGIC_MAX_NUM_INTR_INPUTS];/**<
+ Vector table of interrupt handlers */
+} XScuGic_Config;
+
+/**
+ * The XScuGic driver instance data. The user is required to allocate a
+ * variable of this type for every intc device in the system. A pointer
+ * to a variable of this type is then passed to the driver API functions.
+ */
+typedef struct
+{
+ XScuGic_Config *Config; /**< Configuration table entry */
+ u32 IsReady; /**< Device is initialized and ready */
+ u32 UnhandledInterrupts; /**< Intc Statistics */
+} XScuGic;
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/****************************************************************************/
+/**
+*
+* Write the given CPU Interface register
+*
+* @param InstancePtr is a pointer to the instance to be worked on.
+* @param RegOffset is the register offset to be written
+* @param Data is the 32-bit value to write to the register
+*
+* @return None.
+*
+* @note
+* C-style signature:
+* void XScuGic_CPUWriteReg(XScuGic *InstancePtr, u32 RegOffset, u32 Data)
+*
+*****************************************************************************/
+#define XScuGic_CPUWriteReg(InstancePtr, RegOffset, Data) \
+(XScuGic_WriteReg(((InstancePtr)->Config->CpuBaseAddress), (RegOffset), \
+ ((u32)(Data))))
+
+/****************************************************************************/
+/**
+*
+* Read the given CPU Interface register
+*
+* @param InstancePtr is a pointer to the instance to be worked on.
+* @param RegOffset is the register offset to be read
+*
+* @return The 32-bit value of the register
+*
+* @note
+* C-style signature:
+* u32 XScuGic_CPUReadReg(XScuGic *InstancePtr, u32 RegOffset)
+*
+*****************************************************************************/
+#define XScuGic_CPUReadReg(InstancePtr, RegOffset) \
+ (XScuGic_ReadReg(((InstancePtr)->Config->CpuBaseAddress), (RegOffset)))
+
+/****************************************************************************/
+/**
+*
+* Write the given Distributor Interface register
+*
+* @param InstancePtr is a pointer to the instance to be worked on.
+* @param RegOffset is the register offset to be written
+* @param Data is the 32-bit value to write to the register
+*
+* @return None.
+*
+* @note
+* C-style signature:
+* void XScuGic_DistWriteReg(XScuGic *InstancePtr, u32 RegOffset, u32 Data)
+*
+*****************************************************************************/
+#define XScuGic_DistWriteReg(InstancePtr, RegOffset, Data) \
+(XScuGic_WriteReg(((InstancePtr)->Config->DistBaseAddress), (RegOffset), \
+ ((u32)(Data))))
+
+/****************************************************************************/
+/**
+*
+* Read the given Distributor Interface register
+*
+* @param InstancePtr is a pointer to the instance to be worked on.
+* @param RegOffset is the register offset to be read
+*
+* @return The 32-bit value of the register
+*
+* @note
+* C-style signature:
+* u32 XScuGic_DistReadReg(XScuGic *InstancePtr, u32 RegOffset)
+*
+*****************************************************************************/
+#define XScuGic_DistReadReg(InstancePtr, RegOffset) \
+(XScuGic_ReadReg(((InstancePtr)->Config->DistBaseAddress), (RegOffset)))
+
+/****************************************************************************/
+/**
+*
+* Write the given ReDistributor Interface register
+*
+* @param InstancePtr is a pointer to the instance to be worked on.
+* @param RegOffset is the register offset to be written
+* @param Data is the 32-bit value to write to the register
+*
+* @return None.
+*
+* @note
+* C-style signature:
+* void XScuGic_DistWriteReg(XScuGic *InstancePtr, u32 RegOffset, u32 Data)
+*
+*****************************************************************************/
+#define XScuGic_ReDistWriteReg(InstancePtr, RegOffset, Data) \
+(XScuGic_WriteReg(((InstancePtr)->Config->DistBaseAddress)+ \
+ XSCUGIC_RDIST_OFFSET, (RegOffset), ((u32)(Data))))
+
+/****************************************************************************/
+/**
+*
+* Read the given ReDistributor Interface register
+*
+* @param InstancePtr is a pointer to the instance to be worked on.
+* @param RegOffset is the register offset to be read
+*
+* @return The 32-bit value of the register
+*
+* @note
+* C-style signature:
+* u32 XScuGic_DistReadReg(XScuGic *InstancePtr, u32 RegOffset)
+*
+*****************************************************************************/
+#define XScuGic_ReDistReadReg(InstancePtr, RegOffset) \
+(XScuGic_ReadReg((((InstancePtr)->Config->DistBaseAddress)+ \
+XSCUGIC_RDIST_OFFSET), (RegOffset)))
+
+/****************************************************************************/
+/**
+*
+* Write the given ReDistributor SGI PPI Interface register
+*
+* @param InstancePtr is a pointer to the instance to be worked on.
+* @param RegOffset is the register offset to be written
+* @param Data is the 32-bit value to write to the register
+*
+* @return None.
+*
+* @note
+* C-style signature:
+* void XScuGic_DistWriteReg(XScuGic *InstancePtr, u32 RegOffset, u32 Data)
+*
+*****************************************************************************/
+#define XScuGic_ReDistSGIPPIWriteReg(InstancePtr, RegOffset, Data) \
+(XScuGic_WriteReg(((InstancePtr)->Config->DistBaseAddress)+ \
+ XSCUGIC_RDIST_SGI_PPI_OFFSET, (RegOffset), ((u32)(Data))))
+
+/****************************************************************************/
+/**
+*
+* Read the given ReDistributor SGI PPI Interface register
+*
+* @param InstancePtr is a pointer to the instance to be worked on.
+* @param RegOffset is the register offset to be read
+*
+* @return The 32-bit value of the register
+*
+* @note
+* C-style signature:
+* u32 XScuGic_DistReadReg(XScuGic *InstancePtr, u32 RegOffset)
+*
+*****************************************************************************/
+#define XScuGic_ReDistSGIPPIReadReg(InstancePtr, RegOffset) \
+(XScuGic_ReadReg((((InstancePtr)->Config->DistBaseAddress)+ \
+ XSCUGIC_RDIST_SGI_PPI_OFFSET), (RegOffset)))
+
+/****************************************************************************/
+/**
+* This function enables system register interface for GIC CPU Interface
+*
+* @param value to be written
+*
+* @return None.
+*
+* @note None.
+*
+*****************************************************************************/
+#define XScuGic_Enable_SystemReg_CPU_Interface_EL3() mtcp(S3_6_C12_C12_5, 0xF);
+#define XScuGic_Enable_SystemReg_CPU_Interface_EL1() mtcp(S3_0_C12_C12_5, 0xF);
+/****************************************************************************/
+/**
+* This function enables Grou0 interrupts
+*
+* @param None.
+*
+* @return None.
+*
+* @note None.
+*
+*****************************************************************************/
+#define XScuGic_Enable_Group0_Interrupts() mtcp(S3_0_C12_C12_6,0x1);
+/****************************************************************************/
+/**
+* This function enables Group1 interrupts
+*
+* @param None.
+*
+* @return None.
+*
+* @note None.
+*
+*****************************************************************************/
+#if defined (__aarch64__)
+#if EL1_NONSECURE
+#define XScuGic_Enable_Group1_Interrupts() \
+ mtcp (S3_0_C12_C12_7, 0x1 | mfcp(S3_0_C12_C12_7) );
+#else
+#define XScuGic_Enable_Group1_Interrupts() \
+ mtcp (S3_6_C12_C12_7, 0x1 | mfcp(S3_6_C12_C12_7) );
+#endif
+#endif
+/****************************************************************************/
+/**
+* This function writes to ICC_SGI0R_EL1
+*
+* @param value to be written
+*
+* @return None.
+*
+* @note None.
+*
+*****************************************************************************/
+#define XScuGic_WriteICC_SGI0R_EL1(val) mtcp(S3_0_C12_C11_7,val)
+
+/****************************************************************************/
+/**
+* This function writes to ICC_SGI1R_EL1
+*
+* @param value to be written
+*
+* @return None.
+*
+* @note None.
+*
+*****************************************************************************/
+#define XScuGic_WriteICC_SGI1R_EL1(val) mtcp(S3_0_C12_C11_5,val)
+
+/****************************************************************************/
+/**
+* This function reads ICC_SGI1R_EL1 register
+*
+* @param None
+*
+* @return Value of ICC_SGI1R_EL1 register
+*
+* @note None.
+*
+*****************************************************************************/
+#define XScuGic_ReadICC_SGI1R_EL1() mfcp(S3_0_C12_C11_5)
+/****************************************************************************/
+/**
+* This function sets interrupt priority filter
+*
+* @param None.
+*
+* @return None.
+*
+* @note None.
+*
+*****************************************************************************/
+#define XScuGic_set_priority_filter(val) __asm__ __volatile__("msr S3_0_C4_C6_0,%0" : : "r" (val))
+/****************************************************************************/
+/**
+* This function returns interrupt id of highest priority pending interrupt
+*
+* @param None.
+*
+* @return None.
+*
+* @note None.
+*
+*****************************************************************************/
+#if defined (__aarch64__)
+#if EL3
+#define XScuGic_get_IntID() mfcp(S3_0_C12_C8_0)
+#else
+#define XScuGic_get_IntID() mfcp(S3_0_C12_C12_0)
+#endif
+#endif
+/****************************************************************************/
+/**
+* This function acks the interrupt
+*
+* @param None.
+*
+* @return None.
+*
+* @note None.
+*
+*****************************************************************************/
+#if defined (__aarch64__)
+#if EL3
+#define XScuGic_ack_Int(val) mtcp(S3_0_C12_C8_1,val)
+#else
+#define XScuGic_ack_Int(val) mtcp(S3_0_C12_C12_1,val)
+#endif
+#endif
+/****************************************************************************/
+/**
+* This macro returns bit position for the specific interrupt's trigger type
+* configuration within GICR_ICFGR0/GICR_ICFGR1 register
+*
+* @param None.
+*
+* @return None.
+*
+* @note None.
+*
+*****************************************************************************/
+#define XScuGic_Get_Rdist_Int_Trigger_Index(IntrId) (((Int_Id%16) & 0x1f) << 2) +1
+/************************** Function Prototypes ******************************/
+
+/*
+ * Required functions in xscugic.c
+ */
+
+s32 XScuGic_Connect(XScuGic *InstancePtr, u32 Int_Id,
+ Xil_InterruptHandler Handler, void *CallBackRef);
+void XScuGic_Disconnect(XScuGic *InstancePtr, u32 Int_Id);
+
+void XScuGic_Enable(XScuGic *InstancePtr, u32 Int_Id);
+void XScuGic_Disable(XScuGic *InstancePtr, u32 Int_Id);
+
+s32 XScuGic_CfgInitialize(XScuGic *InstancePtr, XScuGic_Config *ConfigPtr,
+ u32 EffectiveAddr);
+
+s32 XScuGic_SoftwareIntr(XScuGic *InstancePtr, u32 Int_Id, u32 Cpu_Id);
+
+void XScuGic_GetPriorityTriggerType(XScuGic *InstancePtr, u32 Int_Id,
+ u8 *Priority, u8 *Trigger);
+void XScuGic_SetPriorityTriggerType(XScuGic *InstancePtr, u32 Int_Id,
+ u8 Priority, u8 Trigger);
+void XScuGic_InterruptMaptoCpu(XScuGic *InstancePtr, u8 Cpu_Id, u32 Int_Id);
+void XScuGic_InterruptUnmapFromCpu(XScuGic *InstancePtr, u8 Cpu_Id, u32 Int_Id);
+void XScuGic_UnmapAllInterruptsFromCpu(XScuGic *InstancePtr, u8 Cpu_Id);
+void XScuGic_Stop(XScuGic *InstancePtr);
+void XScuGic_SetCpuID(u32 CpuCoreId);
+u32 XScuGic_GetCpuID(void);
+/*
+ * Initialization functions in xscugic_sinit.c
+ */
+XScuGic_Config *XScuGic_LookupConfig(u16 DeviceId);
+
+/*
+ * Interrupt functions in xscugic_intr.c
+ */
+void XScuGic_InterruptHandler(XScuGic *InstancePtr);
+
+/*
+ * Self-test functions in xscugic_selftest.c
+ */
+s32 XScuGic_SelfTest(XScuGic *InstancePtr);
+
+void XScuGic_EnableSGI_PPI(XScuGic *InstancePtr,u32 ID);
+void XScuGic_SetPPI_SGI_Priority(XScuGic *InstancePtr,u32 ID, u32 priority);
+#if defined (GICv3)
+void XScuGic_MarkCoreAsleep(XScuGic *InstancePtr);
+void XScuGic_MarkCoreAwake(XScuGic *InstancePtr);
+#endif
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* end of protection macro */
+/** @} */
diff --git a/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/scugic_v4_1/src/xscugic_g.c b/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/scugic_v4_1/src/xscugic_g.c
new file mode 100644
index 0000000..0f69b16
--- /dev/null
+++ b/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/scugic_v4_1/src/xscugic_g.c
@@ -0,0 +1,49 @@
+
+/*******************************************************************
+*
+* CAUTION: This file is automatically generated by HSI.
+* Version: 2019.2
+* DO NOT EDIT.
+*
+* Copyright (C) 2010-2021 Xilinx, Inc. All Rights Reserved.*
+*Permission is hereby granted, free of charge, to any person obtaining a copy
+*of this software and associated documentation files (the Software), to deal
+*in the Software without restriction, including without limitation the rights
+*to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+*copies of the Software, and to permit persons to whom the Software is
+*furnished to do so, subject to the following conditions:
+*
+*The above copyright notice and this permission notice shall be included in
+*all copies or substantial portions of the Software.
+*
+*THE SOFTWARE IS PROVIDED AS IS, WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+*IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+*FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+*THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+*WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT
+*OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+*
+
+*
+* Description: Driver configuration
+*
+*******************************************************************/
+
+#include "xparameters.h"
+#include "xscugic.h"
+
+/*
+* The configuration table for devices
+*/
+
+XScuGic_Config XScuGic_ConfigTable[XPAR_XSCUGIC_NUM_INSTANCES] =
+{
+ {
+ XPAR_PS7_SCUGIC_0_DEVICE_ID,
+ XPAR_PS7_SCUGIC_0_BASEADDR,
+ XPAR_PS7_SCUGIC_0_DIST_BASEADDR,
+ {{0}} /**< Initialize the HandlerTable to 0 */
+ }
+};
+
+
diff --git a/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/scugic_v4_1/src/xscugic_hw.c b/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/scugic_v4_1/src/xscugic_hw.c
new file mode 100644
index 0000000..6483a78
--- /dev/null
+++ b/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/scugic_v4_1/src/xscugic_hw.c
@@ -0,0 +1,872 @@
+/******************************************************************************
+*
+* Copyright (C) 2010 - 2019 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+* THE SOFTWARE.
+*
+*
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xscugic_hw.c
+* @addtogroup scugic_v4_0
+* @{
+*
+* This file contains low-level driver functions that can be used to access the
+* device. The user should refer to the hardware device specification for more
+* details of the device operation.
+* These routines are used when the user does not want to create an instance of
+* XScuGic structure but still wants to use the ScuGic device. Hence the
+* routines provided here take device id or scugic base address as arguments.
+* Separate static versions of DistInit and CPUInit are provided to implement
+* the low level driver routines.
+*
+* <pre>
+* MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ----- ---- -------- -------------------------------------------------------
+* 1.01a sdm 07/18/11 First release
+* 1.03a srt 02/27/13 Moved Offset calculation macros from *_hw.c (CR
+* 702687).
+* Added support to direct interrupts to the appropriate
+* CPU. Earlier interrupts were directed to CPU1
+* (hard coded). Now depending upon the CPU selected by
+* the user (xparameters.h), interrupts will be directed
+* to the relevant CPU.This fixes CR 699688.
+* 1.04a hk 05/04/13 Fix for CR#705621. Moved functions
+* XScuGic_SetPriTrigTypeByDistAddr and
+* XScuGic_GetPriTrigTypeByDistAddr here from xscugic.c
+* 3.00 kvn 02/13/15 Modified code for MISRA-C:2012 compliance.
+* 3.6 kvn 02/17/17 Add support for changing GIC CPU master at run time.
+* kvn 02/28/17 Make the CpuId as static variable and Added new
+* XScugiC_GetCpuId to access CpuId.
+* 3.9 mus 02/21/18 Added new API's
+* XScuGic_InterruptUnmapFromCpuByDistAddr and
+* XScuGic_UnmapAllInterruptsFromCpuByDistAddr, These
+* API's can be used by applications to unmap
+* specific/all interrupts from target CPU. It fixes
+* CR#992490.
+* 3.10 mus 07/17/18 Updated XScuGic_DeviceInterruptHandler to fix array
+* overrun reported by coverity tool. It fixes
+* CR#1006344.
+* 3.10 mus 07/17/18 Updated file to fix the various coding style issues
+* reported by checkpatch. It fixes CR#1006344.
+* 3.10 aru 08/23/18 Resolved MISRA-C:2012 compliance mandatory violations
+* It fixes CR#1007753
+* 3.10 mus 09/19/18 Update documentation for XScuGic_RegisterHandler to
+* fix doxygen warnings.
+* 4.1 asa 03/30/19 Made changes not to direct each interrupt to all
+* available CPUs by default. This was breaking AMP
+* behavior. Instead every time an interrupt enable
+* request is received, the interrupt was mapped to
+* the respective CPU. There were several other changes
+* made to implement this including adding APIs:
+* XScuGic_InterruptMapFromCpuByDistAddr,
+* XScuGic_EnableIntr, and XScuGic_DisableIntr.
+* This set of changes was to fix CR-1024716.
+* 4.1 mus 06/12/19 Updated existing low level API's to support GIC500. It
+* fixes CR#1033401.
+* </pre>
+*
+******************************************************************************/
+
+
+/***************************** Include Files *********************************/
+
+#include "xil_types.h"
+#include "xil_assert.h"
+#include "xscugic.h"
+#include "xparameters.h"
+
+/************************** Constant Definitions *****************************/
+
+/**************************** Type Definitions *******************************/
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/************************** Function Prototypes ******************************/
+
+static void DistInit(XScuGic_Config *Config);
+#if !defined (GICv3)
+static void CPUInit(XScuGic_Config *Config);
+#endif
+static XScuGic_Config *LookupConfigByBaseAddress(u32 CpuBaseAddress);
+
+/************************** Variable Definitions *****************************/
+
+extern XScuGic_Config XScuGic_ConfigTable[XPAR_XSCUGIC_NUM_INSTANCES];
+
+/*****************************************************************************/
+/**
+*
+* DistInit initializes the distributor of the GIC. The
+* initialization entails:
+*
+* - Write the trigger mode, priority and target CPU
+* - All interrupt sources are disabled
+* - Enable the distributor
+*
+* @param InstancePtr is a pointer to the XScuGic instance.
+* @param CpuID is the Cpu ID to be initialized.
+*
+* @return None
+*
+* @note None.
+*
+******************************************************************************/
+static void DistInit(XScuGic_Config *Config)
+{
+ u32 Int_Id;
+
+#if USE_AMP == 1
+ #warning "Building GIC for AMP"
+
+ /*
+ * The distrubutor should not be initialized by FreeRTOS in the case of
+ * AMP -- it is assumed that Linux is the master of this device in that
+ * case.
+ */
+ return;
+#endif
+
+#if defined (GICv3)
+ u32 Temp;
+ u32 Waker_State;
+
+ Waker_State = XScuGic_ReadReg((Config->DistBaseAddress) +
+ XSCUGIC_RDIST_OFFSET,XSCUGIC_RDIST_WAKER_OFFSET);
+ XScuGic_WriteReg((Config->DistBaseAddress) +
+ XSCUGIC_RDIST_OFFSET,XSCUGIC_RDIST_WAKER_OFFSET,
+ Waker_State & (~ XSCUGIC_RDIST_WAKER_LOW_POWER_STATE_MASK));
+ /* Enable system reg interface through ICC_SRE_EL1 */
+#if EL3
+ XScuGic_Enable_SystemReg_CPU_Interface_EL3();
+#endif
+ XScuGic_Enable_SystemReg_CPU_Interface_EL1();
+ isb();
+
+ Temp = XScuGic_ReadReg(Config->DistBaseAddress, XSCUGIC_DIST_EN_OFFSET);
+ Temp |= (XSCUGIC500_DCTLR_ARE_NS_ENABLE | XSCUGIC500_DCTLR_ARE_S_ENABLE);
+ Temp &= ~(XSCUGIC_EN_INT_MASK);
+ XScuGic_WriteReg(Config->DistBaseAddress, XSCUGIC_DIST_EN_OFFSET, Temp);
+#else
+ XScuGic_WriteReg(Config->DistBaseAddress, XSCUGIC_DIST_EN_OFFSET, 0U);
+#endif
+
+ /*
+ * Set the security domains in the int_security registers for non-secure
+ * interrupts. All are secure, so leave at the default. Set to 1 for
+ * non-secure interrupts.
+ */
+
+
+ /*
+ * For the Shared Peripheral Interrupts INT_ID[MAX..32], set:
+ */
+
+ /*
+ * 1. The trigger mode in the int_config register
+ * Only write to the SPI interrupts, so start at 32
+ */
+ for (Int_Id = 32U; Int_Id < XSCUGIC_MAX_NUM_INTR_INPUTS;
+ Int_Id = Int_Id+16U) {
+ /*
+ * Each INT_ID uses two bits, or 16 INT_ID per register
+ * Set them all to be level sensitive, active HIGH.
+ */
+ XScuGic_WriteReg(Config->DistBaseAddress,
+ XSCUGIC_INT_CFG_OFFSET_CALC(Int_Id), 0U);
+ }
+
+
+#define DEFAULT_PRIORITY 0xa0a0a0a0U
+ for (Int_Id = 0U; Int_Id < XSCUGIC_MAX_NUM_INTR_INPUTS;
+ Int_Id = Int_Id+4U) {
+ /*
+ * 2. The priority using int the priority_level register
+ * The priority_level and spi_target registers use one byte per
+ * INT_ID.
+ * Write a default value that can be changed elsewhere.
+ */
+ XScuGic_WriteReg(Config->DistBaseAddress,
+ XSCUGIC_PRIORITY_OFFSET_CALC(Int_Id),
+ DEFAULT_PRIORITY);
+ }
+
+#if defined (GICv3)
+ for (Int_Id = 0U; Int_Id<XSCUGIC_MAX_NUM_INTR_INPUTS;Int_Id=Int_Id+32U) {
+ XScuGic_WriteReg(Config->DistBaseAddress,
+ XSCUGIC_SECURITY_TARGET_OFFSET_CALC(Int_Id),
+ XSCUGIC_DEFAULT_SECURITY);
+ }
+ /*
+ * Set security for SGI/PPI
+ *
+ */
+ XScuGic_WriteReg( Config->DistBaseAddress + XSCUGIC_RDIST_SGI_PPI_OFFSET,
+ XSCUGIC_RDIST_IGROUPR_OFFSET, XSCUGIC_DEFAULT_SECURITY);
+#endif
+
+ for (Int_Id = 0U; Int_Id < XSCUGIC_MAX_NUM_INTR_INPUTS;
+ Int_Id = Int_Id+32U) {
+ /*
+ * 4. Enable the SPI using the enable_set register.
+ * Leave all disabled for now.
+ */
+ XScuGic_WriteReg(Config->DistBaseAddress,
+ XSCUGIC_EN_DIS_OFFSET_CALC(XSCUGIC_DISABLE_OFFSET,
+ Int_Id),
+ 0xFFFFFFFFU);
+
+ }
+
+#if defined (GICv3)
+ Temp = XScuGic_ReadReg(Config->DistBaseAddress, XSCUGIC_DIST_EN_OFFSET);
+ Temp |= XSCUGIC_EN_INT_MASK;
+ XScuGic_WriteReg(Config->DistBaseAddress, XSCUGIC_DIST_EN_OFFSET, Temp);
+ XScuGic_Enable_Group1_Interrupts();
+ XScuGic_Enable_Group0_Interrupts();
+ XScuGic_set_priority_filter(0xff);
+#else
+
+ XScuGic_WriteReg(Config->DistBaseAddress, XSCUGIC_DIST_EN_OFFSET,
+ XSCUGIC_EN_INT_MASK);
+#endif
+
+}
+
+#if !defined (GICv3)
+/*****************************************************************************/
+/**
+*
+* CPUInit initializes the CPU Interface of the GIC. The initialization entails:
+*
+* - Set the priority of the CPU.
+* - Enable the CPU interface
+*
+* @param ConfigPtr is a pointer to a config table for the particular
+* device this driver is associated with.
+*
+* @return None
+*
+* @note None.
+*
+******************************************************************************/
+static void CPUInit(XScuGic_Config *Config)
+{
+ /*
+ * Program the priority mask of the CPU using the Priority mask
+ * register
+ */
+ XScuGic_WriteReg(Config->CpuBaseAddress, XSCUGIC_CPU_PRIOR_OFFSET,
+ 0xF0U);
+
+ /*
+ * If the CPU operates in both security domains, set parameters in the
+ * control_s register.
+ * 1. Set FIQen=1 to use FIQ for secure interrupts,
+ * 2. Program the AckCtl bit
+ * 3. Program the SBPR bit to select the binary pointer behavior
+ * 4. Set EnableS = 1 to enable secure interrupts
+ * 5. Set EnbleNS = 1 to enable non secure interrupts
+ */
+
+ /*
+ * If the CPU operates only in the secure domain, setup the
+ * control_s register.
+ * 1. Set FIQen=1,
+ * 2. Set EnableS=1, to enable the CPU interface to signal secure .
+ * interrupts Only enable the IRQ output unless secure interrupts
+ * are needed.
+ */
+ XScuGic_WriteReg(Config->CpuBaseAddress, XSCUGIC_CONTROL_OFFSET, 0x07U);
+
+}
+#endif
+
+/*****************************************************************************/
+/**
+*
+* Initialize the GIC based on the device id. The
+* initialization entails:
+*
+* - Initialize distributor interface
+* - Initialize cpu interface
+*
+* @param DeviceId is device id to be worked on.
+*
+* @return
+*
+* - XST_SUCCESS if initialization was successful
+*
+* @note
+*
+* None.
+*
+******************************************************************************/
+s32 XScuGic_DeviceInitialize(u32 DeviceId)
+{
+ XScuGic_Config *Config;
+
+ Config = &XScuGic_ConfigTable[(u32)DeviceId];
+ DistInit(Config);
+#if !defined (GICv3)
+ CPUInit(Config);
+#endif
+
+ return XST_SUCCESS;
+}
+
+/*****************************************************************************/
+/**
+* This function is the primary interrupt handler for the driver. It must be
+* connected to the interrupt source such that it is called when an interrupt of
+* the interrupt controller is active. It will resolve which interrupts are
+* active and enabled and call the appropriate interrupt handler. It uses
+* the Interrupt Type information to determine when to acknowledge the
+* interrupt.Highest priority interrupts are serviced first.
+*
+* This function assumes that an interrupt vector table has been previously
+* initialized. It does not verify that entries in the table are valid before
+* calling an interrupt handler.
+*
+* @param DeviceId is the unique identifier for the ScuGic device.
+*
+* @return None.
+*
+* @note None.
+*
+******************************************************************************/
+void XScuGic_DeviceInterruptHandler(void *DeviceId)
+{
+
+ u32 InterruptID;
+#if !defined (GICv3)
+ u32 IntIDFull;
+#endif
+ XScuGic_VectorTableEntry *TablePtr;
+ XScuGic_Config *CfgPtr;
+
+ CfgPtr = &XScuGic_ConfigTable[(INTPTR)DeviceId];
+
+#if defined (GICv3)
+ InterruptID = XScuGic_get_IntID();
+#else
+ /*
+ * Read the int_ack register to identify the highest priority
+ * interrupt ID and make sure it is valid. Reading Int_Ack will
+ * clear the interrupt in the GIC.
+ */
+ IntIDFull = XScuGic_ReadReg(CfgPtr->CpuBaseAddress,
+ XSCUGIC_INT_ACK_OFFSET);
+ InterruptID = IntIDFull & XSCUGIC_ACK_INTID_MASK;
+
+#endif
+ if (XSCUGIC_MAX_NUM_INTR_INPUTS <= InterruptID) {
+ goto IntrExit;
+ }
+
+ /*
+ * If the interrupt is shared, do some locking here if there are
+ * multiple processors.
+ */
+ /*
+ * If pre-eption is required:
+ * Re-enable pre-emption by setting the CPSR I bit for non-secure ,
+ * interrupts or the F bit for secure interrupts
+ */
+
+ /*
+ * If we need to change security domains, issue a SMC instruction here.
+ */
+
+ /*
+ * Execute the ISR. Jump into the Interrupt service routine based on
+ * the IRQSource. A software trigger is cleared by the ACK.
+ */
+ TablePtr = &(CfgPtr->HandlerTable[InterruptID]);
+ if (TablePtr != NULL) {
+ TablePtr->Handler(TablePtr->CallBackRef);
+ }
+
+IntrExit:
+ /*
+ * Write to the EOI register, we are all done here.
+ * Let this function return, the boot code will restore the stack.
+ */
+#if defined (GICv3)
+ XScuGic_ack_Int(InterruptID);
+#else
+ XScuGic_WriteReg(CfgPtr->CpuBaseAddress, XSCUGIC_EOI_OFFSET, IntIDFull);
+#endif
+
+ /*
+ * Return from the interrupt. Change security domains could happen
+ * here.
+ */
+}
+
+/*****************************************************************************/
+/**
+*
+* Register a handler function for a specific interrupt ID. The vector table
+* of the interrupt controller is updated, overwriting any previous handler.
+* The handler function will be called when an interrupt occurs for the given
+* interrupt ID.
+*
+* @param BaseAddress is the CPU Interface Register base address of the
+* interrupt controller whose vector table will be modified.
+* @param InterruptID is the interrupt ID to be associated with the input
+* handler.
+* @param IntrHandler is the function pointer that will be added to
+* the vector table for the given interrupt ID.
+* @param CallBackRef is the argument that will be passed to the new
+* handler function when it is called. This is user-specific.
+*
+* @return None.
+*
+* @note
+*
+* Note that this function has no effect if the input base address is invalid.
+*
+******************************************************************************/
+void XScuGic_RegisterHandler(u32 BaseAddress, s32 InterruptID,
+ Xil_InterruptHandler IntrHandler, void *CallBackRef)
+{
+ XScuGic_Config *CfgPtr;
+ CfgPtr = LookupConfigByBaseAddress(BaseAddress);
+
+ if (CfgPtr != NULL) {
+ if (IntrHandler != NULL) {
+ CfgPtr->HandlerTable[InterruptID].Handler =
+ (Xil_InterruptHandler)IntrHandler;
+ }
+ if (CallBackRef != NULL) {
+ CfgPtr->HandlerTable[InterruptID].CallBackRef =
+ CallBackRef;
+ }
+ }
+}
+
+/*****************************************************************************/
+/**
+*
+* Looks up the device configuration based on the CPU interface base address of
+* the device. A table contains the configuration info for each device in the
+* system.
+*
+* @param CpuBaseAddress is the CPU Interface Register base address.
+*
+* @return A pointer to the configuration structure for the specified
+* device, or NULL if the device was not found.
+*
+* @note None.
+*
+******************************************************************************/
+static XScuGic_Config *LookupConfigByBaseAddress(u32 CpuBaseAddress)
+{
+ XScuGic_Config *CfgPtr = NULL;
+ u32 Index;
+
+ for (Index = 0U; Index < XPAR_SCUGIC_NUM_INSTANCES; Index++) {
+ if (XScuGic_ConfigTable[Index].CpuBaseAddress ==
+ CpuBaseAddress) {
+ CfgPtr = &XScuGic_ConfigTable[Index];
+ break;
+ }
+ }
+
+ return (XScuGic_Config *)CfgPtr;
+}
+
+/****************************************************************************/
+/**
+* Sets the interrupt priority and trigger type for the specificd IRQ source.
+*
+* @param DistBaseAddress is the distributor base address
+* @param Int_Id is the IRQ source number to modify
+* @param Priority is the new priority for the IRQ source. 0 is highest
+* priority, 0xF8(248) is lowest. There are 32 priority
+* levels supported with a step of 8. Hence the supported
+* priorities are 0, 8, 16, 32, 40 ..., 248.
+* @param Trigger is the new trigger type for the IRQ source.
+* Each bit pair describes the configuration for an INT_ID.
+* SFI Read Only b10 always
+* PPI Read Only depending on how the PPIs are configured.
+* b01 Active HIGH level sensitive
+* b11 Rising edge sensitive
+* SPI LSB is read only.
+* b01 Active HIGH level sensitive
+* b11 Rising edge sensitive/
+*
+* @return None.
+*
+* @note This API has the similar functionality of XScuGic_SetPriority
+* TriggerType() and should be used when there is no InstancePtr.
+*
+*****************************************************************************/
+void XScuGic_SetPriTrigTypeByDistAddr(u32 DistBaseAddress, u32 Int_Id,
+ u8 Priority, u8 Trigger)
+{
+ u32 RegValue;
+#if defined (GICv3)
+ u32 Temp;
+ u32 Index;
+#endif
+ u8 LocalPriority = Priority;
+
+ Xil_AssertVoid(Int_Id < XSCUGIC_MAX_NUM_INTR_INPUTS);
+ Xil_AssertVoid(Trigger <= XSCUGIC_INT_CFG_MASK);
+ Xil_AssertVoid(LocalPriority <= XSCUGIC_MAX_INTR_PRIO_VAL);
+#if defined (GICv3)
+ if (Int_Id < XSCUGIC_SPI_INT_ID_START )
+ {
+ XScuGic_WriteReg(DistBaseAddress + XSCUGIC_RDIST_SGI_PPI_OFFSET,
+ XSCUGIC_RDIST_INT_PRIORITY_OFFSET_CALC(Int_Id),Priority);
+ Temp = XScuGic_ReadReg(DistBaseAddress + XSCUGIC_RDIST_SGI_PPI_OFFSET,
+ XSCUGIC_RDIST_INT_CONFIG_OFFSET_CALC(Int_Id));
+ Index = XScuGic_Get_Rdist_Int_Trigger_Index(Int_Id);
+ Temp |= (Trigger << Index);
+ XScuGic_WriteReg(DistBaseAddress + XSCUGIC_RDIST_SGI_PPI_OFFSET,
+ XSCUGIC_RDIST_INT_CONFIG_OFFSET_CALC(Int_Id),Temp);
+ return;
+ }
+#endif
+ /*
+ * Determine the register to write to using the Int_Id.
+ */
+ RegValue = XScuGic_ReadReg(DistBaseAddress,
+ XSCUGIC_PRIORITY_OFFSET_CALC(Int_Id));
+
+ /*
+ * The priority bits are Bits 7 to 3 in GIC Priority Register. This
+ * means the number of priority levels supported are 32 and they are
+ * in steps of 8. The priorities can be 0, 8, 16, 32, 48, ... etc.
+ * The lower order 3 bits are masked before putting it in the register.
+ */
+ LocalPriority = LocalPriority & XSCUGIC_INTR_PRIO_MASK;
+ /*
+ * Shift and Mask the correct bits for the priority and trigger in the
+ * register
+ */
+ RegValue &= ~(XSCUGIC_PRIORITY_MASK << ((Int_Id%4U)*8U));
+ RegValue |= (u32)LocalPriority << ((Int_Id%4U)*8U);
+
+ /*
+ * Write the value back to the register.
+ */
+ XScuGic_WriteReg(DistBaseAddress, XSCUGIC_PRIORITY_OFFSET_CALC(Int_Id),
+ RegValue);
+ /*
+ * Determine the register to write to using the Int_Id.
+ */
+ RegValue = XScuGic_ReadReg(DistBaseAddress,
+ XSCUGIC_INT_CFG_OFFSET_CALC(Int_Id));
+
+ /*
+ * Shift and Mask the correct bits for the priority and trigger in the
+ * register
+ */
+ RegValue &= ~(XSCUGIC_INT_CFG_MASK << ((Int_Id%16U)*2U));
+ RegValue |= (u32)Trigger << ((Int_Id%16U)*2U);
+
+ /*
+ * Write the value back to the register.
+ */
+ XScuGic_WriteReg(DistBaseAddress, XSCUGIC_INT_CFG_OFFSET_CALC(Int_Id),
+ RegValue);
+}
+
+/****************************************************************************/
+/**
+* Gets the interrupt priority and trigger type for the specificd IRQ source.
+*
+* @param DistBaseAddress is the distributor base address
+* @param Int_Id is the IRQ source number to modify
+* @param Priority is a pointer to the value of the priority of the IRQ
+* source. This is a return value.
+* @param Trigger is pointer to the value of the trigger of the IRQ
+* source. This is a return value.
+*
+* @return None.
+*
+* @note This API has the similar functionality of XScuGic_GetPriority
+* TriggerType() and should be used when there is no InstancePtr.
+*
+*****************************************************************************/
+void XScuGic_GetPriTrigTypeByDistAddr(u32 DistBaseAddress, u32 Int_Id,
+ u8 *Priority, u8 *Trigger)
+{
+ u32 RegValue;
+
+ Xil_AssertVoid(Int_Id < XSCUGIC_MAX_NUM_INTR_INPUTS);
+ Xil_AssertVoid(Priority != NULL);
+ Xil_AssertVoid(Trigger != NULL);
+
+ /*
+ * Determine the register to read to using the Int_Id.
+ */
+ RegValue = XScuGic_ReadReg(DistBaseAddress,
+ XSCUGIC_PRIORITY_OFFSET_CALC(Int_Id));
+
+ /*
+ * Shift and Mask the correct bits for the priority and trigger in the
+ * register
+ */
+ RegValue = RegValue >> ((Int_Id%4U)*8U);
+ *Priority = (u8)(RegValue & XSCUGIC_PRIORITY_MASK);
+
+ /*
+ * Determine the register to read to using the Int_Id.
+ */
+ RegValue = XScuGic_ReadReg(DistBaseAddress,
+ XSCUGIC_INT_CFG_OFFSET_CALC(Int_Id));
+
+ /*
+ * Shift and Mask the correct bits for the priority and trigger in the
+ * register
+ */
+ RegValue = RegValue >> ((Int_Id%16U)*2U);
+
+ *Trigger = (u8)(RegValue & XSCUGIC_INT_CFG_MASK);
+}
+
+/****************************************************************************/
+/**
+* Sets the target CPU for the interrupt of a peripheral
+*
+* @param DistBaseAddress is the device base address
+* @param Cpu_Id is a CPU number from which the interrupt has to be
+* unmapped
+* @param Int_Id is the IRQ source number to modify
+*
+* @return None.
+*
+* @note None
+*
+*****************************************************************************/
+void XScuGic_InterruptMapFromCpuByDistAddr(u32 DistBaseAddress,
+ u8 Cpu_Id, u32 Int_Id)
+{
+ u32 RegValue;
+#if !defined (GICv3)
+ u32 Offset;
+#endif
+
+ Xil_AssertVoid(Int_Id < XSCUGIC_MAX_NUM_INTR_INPUTS);
+#if defined (GICv3)
+ u32 Temp;
+ if (Int_Id >= 32) {
+ Temp = Int_Id - 32;
+ RegValue = XScuGic_ReadReg(DistBaseAddress,
+ XSCUGIC_IROUTER_OFFSET_CALC(Temp));
+ RegValue |= (Cpu_Id);
+ XScuGic_WriteReg(DistBaseAddress, XSCUGIC_IROUTER_OFFSET_CALC(Temp),
+ RegValue);
+ }
+#else
+ RegValue = XScuGic_ReadReg(DistBaseAddress,
+ XSCUGIC_SPI_TARGET_OFFSET_CALC(Int_Id));
+
+ Offset = (Int_Id & 0x3U);
+ Cpu_Id = (0x1U << Cpu_Id);
+
+ RegValue |= (Cpu_Id) << (Offset*8U);
+
+ XScuGic_WriteReg(DistBaseAddress,
+ XSCUGIC_SPI_TARGET_OFFSET_CALC(Int_Id),
+ RegValue);
+#endif
+}
+
+/****************************************************************************/
+/**
+* Unmaps specific SPI interrupt from the target CPU
+*
+* @param DistBaseAddress is the device base address
+* @param Cpu_Id is a CPU number from which the interrupt has to be
+* unmapped
+* @param Int_Id is the IRQ source number to modify
+*
+* @return None.
+*
+* @note None
+*
+*****************************************************************************/
+void XScuGic_InterruptUnmapFromCpuByDistAddr(u32 DistBaseAddress,
+ u8 Cpu_Id, u32 Int_Id)
+{
+ u32 RegValue;
+#if !defined (GICv3)
+ u32 Offset;
+#endif
+
+ Xil_AssertVoid(Int_Id < XSCUGIC_MAX_NUM_INTR_INPUTS);
+#if defined (GICv3)
+ u32 Temp;
+ if (Int_Id >= 32 && Cpu_Id != 0) {
+ Temp = Int_Id - 32;
+ RegValue = XScuGic_ReadReg(DistBaseAddress,
+ XSCUGIC_IROUTER_OFFSET_CALC(Temp));
+ RegValue &= ~(Cpu_Id);
+ XScuGic_WriteReg(DistBaseAddress, XSCUGIC_IROUTER_OFFSET_CALC(Temp),
+ RegValue);
+ } else if (Cpu_Id == 0) {
+ xil_printf("Error: Unable to unmap interrupt id %d from core %d",Int_Id,Cpu_Id);
+ }
+#else
+ RegValue = XScuGic_ReadReg(DistBaseAddress,
+ XSCUGIC_SPI_TARGET_OFFSET_CALC(Int_Id));
+
+ Offset = (Int_Id & 0x3U);
+ Cpu_Id = (0x1U << Cpu_Id);
+
+ RegValue &= ~(Cpu_Id << (Offset*8U));
+ XScuGic_WriteReg(DistBaseAddress,
+ XSCUGIC_SPI_TARGET_OFFSET_CALC(Int_Id), RegValue);
+#endif
+}
+
+/****************************************************************************/
+/**
+* Unmaps all SPI interrupts from the target CPU
+*
+* @param DistBaseAddress is the device base address
+* @param Cpu_Id is a CPU number from which the interrupts has to be
+* unmapped
+*
+* @return None.
+*
+* @note None
+*
+*****************************************************************************/
+void XScuGic_UnmapAllInterruptsFromCpuByDistAddr(u32 DistBaseAddress,
+ u8 Cpu_Id)
+{
+ u32 Int_Id;
+ u32 Target_Cpu;
+ u32 LocalCpuID = (1U << Cpu_Id);
+
+ LocalCpuID |= LocalCpuID << 8U;
+ LocalCpuID |= LocalCpuID << 16U;
+
+ for (Int_Id = 32U; Int_Id < XSCUGIC_MAX_NUM_INTR_INPUTS;
+ Int_Id = Int_Id+4U) {
+
+ Target_Cpu = XScuGic_ReadReg(DistBaseAddress,
+ XSCUGIC_SPI_TARGET_OFFSET_CALC(Int_Id));
+ /* Remove LocalCpuID from interrupt target register */
+ Target_Cpu &= (~LocalCpuID);
+ XScuGic_WriteReg(DistBaseAddress,
+ XSCUGIC_SPI_TARGET_OFFSET_CALC(Int_Id), Target_Cpu);
+
+ }
+}
+
+/*****************************************************************************/
+/**
+*
+* Enables the interrupt source provided as the argument Int_Id. Any pending
+* interrupt condition for the specified Int_Id will occur after this function is
+* called.
+*
+* @param InstancePtr is a pointer to the XScuGic instance.
+* @param Int_Id contains the ID of the interrupt source and should be
+* in the range of 0 to XSCUGIC_MAX_NUM_INTR_INPUTS - 1
+*
+* @return None.
+*
+* @note None.
+*
+****************************************************************************/
+void XScuGic_EnableIntr (u32 DistBaseAddress, u32 Int_Id)
+{
+ u8 Cpu_Id = (u8)XScuGic_GetCpuID();
+#if defined (GICv3)
+ u32 Temp;
+#endif
+
+#if defined (GICv3)
+ if (Int_Id < XSCUGIC_SPI_INT_ID_START) {
+ XScuGic_InterruptMapFromCpuByDistAddr(DistBaseAddress, Cpu_Id,
+ Int_Id);
+
+ Int_Id &= 0x1f;
+ Int_Id = 1 << Int_Id;
+
+ Temp = XScuGic_ReadReg(DistBaseAddress +
+ XSCUGIC_RDIST_SGI_PPI_OFFSET, XSCUGIC_RDIST_ISENABLE_OFFSET);
+ Temp |= Int_Id;
+ XScuGic_WriteReg(DistBaseAddress + XSCUGIC_RDIST_SGI_PPI_OFFSET,
+ XSCUGIC_RDIST_ISENABLE_OFFSET,Temp);
+ }
+#endif
+
+ XScuGic_InterruptMapFromCpuByDistAddr(DistBaseAddress, Cpu_Id, Int_Id);
+ XScuGic_WriteReg((DistBaseAddress), XSCUGIC_ENABLE_SET_OFFSET +
+ (((Int_Id) / 32U) * 4U), (0x00000001U << ((Int_Id) % 32U)));
+}
+
+/*****************************************************************************/
+/**
+*
+* Disables the interrupt source provided as the argument Int_Id such that the
+* interrupt controller will not cause interrupts for the specified Int_Id. The
+* interrupt controller will continue to hold an interrupt condition for the
+* Int_Id, but will not cause an interrupt.
+*
+* @param InstancePtr is a pointer to the XScuGic instance.
+* @param Int_Id contains the ID of the interrupt source and should be
+* in the range of 0 to XSCUGIC_MAX_NUM_INTR_INPUTS - 1
+*
+* @return None.
+*
+* @note None.
+*
+****************************************************************************/
+void XScuGic_DisableIntr (u32 DistBaseAddress, u32 Int_Id)
+{
+ u8 Cpu_Id = (u8)XScuGic_GetCpuID();
+#if defined (GICv3)
+ u32 Temp;
+
+ if (Int_Id < XSCUGIC_SPI_INT_ID_START) {
+
+ XScuGic_InterruptUnmapFromCpuByDistAddr(DistBaseAddress +
+ XSCUGIC_RDIST_SGI_PPI_OFFSET, Cpu_Id, Int_Id);
+
+ Int_Id &= 0x1f;
+ Int_Id = 1 << Int_Id;
+
+ Temp = XScuGic_ReadReg(DistBaseAddress + XSCUGIC_RDIST_SGI_PPI_OFFSET,
+ XSCUGIC_RDIST_ISENABLE_OFFSET);
+ Temp &= ~Int_Id;
+ XScuGic_WriteReg(DistBaseAddress + XSCUGIC_RDIST_SGI_PPI_OFFSET,
+ XSCUGIC_RDIST_ISENABLE_OFFSET,Temp);
+ }
+#endif
+ XScuGic_InterruptUnmapFromCpuByDistAddr(DistBaseAddress, Cpu_Id, Int_Id);
+ XScuGic_WriteReg((DistBaseAddress), XSCUGIC_DISABLE_OFFSET +
+ (((Int_Id) / 32U) * 4U), (0x00000001U << ((Int_Id) % 32U)));
+}
+
+/** @} */
diff --git a/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/scugic_v4_1/src/xscugic_hw.h b/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/scugic_v4_1/src/xscugic_hw.h
new file mode 100644
index 0000000..6254168
--- /dev/null
+++ b/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/scugic_v4_1/src/xscugic_hw.h
@@ -0,0 +1,718 @@
+/******************************************************************************
+*
+* Copyright (C) 2010 - 2019 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+* THE SOFTWARE.
+*
+*
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xscugic_hw.h
+* @addtogroup scugic_v4_0
+* @{
+*
+* This header file contains identifiers and HW access functions (or
+* macros) that can be used to access the device. The user should refer to the
+* hardware device specification for more details of the device operation.
+* The driver functions/APIs are defined in xscugic.h.
+*
+* This GIC device has two parts, a distributor and CPU interface(s). Each part
+* has separate register definition sections.
+*
+*
+* <pre>
+* MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ----- ---- -------- -----------------------------------------------------
+* 1.00a drg 01/19/10 First release
+* 1.01a sdm 11/09/11 "xil_exception.h" added as include.
+* Macros XScuGic_EnableIntr and XScuGic_DisableIntr are
+* added to enable or disable interrupts based on
+* Distributor Register base address. Normally users use
+* XScuGic instance and call XScuGic_Enable or
+* XScuGic_Disable to enable/disable interrupts. These
+* new macros are provided when user does not want to
+* use an instance pointer but still wants to enable or
+* disable interrupts.
+* Function prototypes for functions (present in newly
+* added file xscugic_hw.c) are added.
+* 1.03a srt 02/27/13 Moved Offset calculation macros from *_hw.c (CR
+* 702687).
+* 1.04a hk 05/04/13 Fix for CR#705621. Moved function prototypes
+* XScuGic_SetPriTrigTypeByDistAddr and
+* XScuGic_GetPriTrigTypeByDistAddr here from xscugic.h
+* 3.0 pkp 12/09/14 changed XSCUGIC_MAX_NUM_INTR_INPUTS for
+* Zynq Ultrascale Mp
+* 3.0 kvn 02/13/14 Modified code for MISRA-C:2012 compliance.
+* 3.2 pkp 11/09/15 Corrected the interrupt processsor target mask value
+* for CPU interface 2 i.e. XSCUGIC_SPI_CPU2_MASK
+* 3.9 mus 02/21/18 Added new API's XScuGic_InterruptUnmapFromCpuByDistAddr
+* and XScuGic_UnmapAllInterruptsFromCpuByDistAddr, These
+* API's can be used by applications to unmap specific/all
+* interrupts from target CPU. It fixes CR#992490.
+* 3.10 aru 08/23/18 Resolved MISRA-C:2012 compliance mandatory violations
+* 4.1 asa 03/30/19 Removed macros for XScuGic_EnableIntr, and
+* XScuGic_DisableIntr. These are now C functions. This
+* change was to fix CR-1024716.
+* 4.1 mus 06/12/19 Updated XSCUGIC_MAX_NUM_INTR_INPUTS for Versal.
+*
+* </pre>
+*
+******************************************************************************/
+
+#ifndef XSCUGIC_HW_H /* prevent circular inclusions */
+#define XSCUGIC_HW_H /* by using protection macros */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/***************************** Include Files *********************************/
+
+#include "xil_types.h"
+#include "xil_assert.h"
+#include "xil_io.h"
+#include "xil_exception.h"
+#include "bspconfig.h"
+
+/************************** Constant Definitions *****************************/
+#if defined (versal) && !defined(ARMR5)
+#define GICv3
+#endif
+
+/*
+ * The maximum number of interrupts supported by the hardware.
+ */
+#ifdef PLATFORM_ZYNQ
+#define XSCUGIC_MAX_NUM_INTR_INPUTS 95U /* Maximum number of interrupt defined by Zynq */
+#elif defined (versal)
+#define XSCUGIC_MAX_NUM_INTR_INPUTS 192U
+#else
+#define XSCUGIC_MAX_NUM_INTR_INPUTS 195U /* Maximum number of interrupt defined by Zynq Ultrascale Mp */
+#endif
+
+/*
+ * First Interrupt Id for SPI interrupts.
+ */
+#define XSCUGIC_SPI_INT_ID_START 0x20
+/*
+ * The maximum priority value that can be used in the GIC.
+ */
+#define XSCUGIC_MAX_INTR_PRIO_VAL 248U
+#define XSCUGIC_INTR_PRIO_MASK 0x000000F8U
+
+/** @name Distributor Interface Register Map
+ *
+ * Define the offsets from the base address for all Distributor registers of
+ * the interrupt controller, some registers may be reserved in the hardware
+ * device.
+ * @{
+ */
+#define XSCUGIC_DIST_EN_OFFSET 0x00000000U /**< Distributor Enable
+ Register */
+#define XSCUGIC_IC_TYPE_OFFSET 0x00000004U /**< Interrupt Controller
+ Type Register */
+#define XSCUGIC_DIST_IDENT_OFFSET 0x00000008U /**< Implementor ID
+ Register */
+#define XSCUGIC_SECURITY_OFFSET 0x00000080U /**< Interrupt Security
+ Register */
+#define XSCUGIC_ENABLE_SET_OFFSET 0x00000100U /**< Enable Set
+ Register */
+#define XSCUGIC_DISABLE_OFFSET 0x00000180U /**< Enable Clear Register */
+#define XSCUGIC_PENDING_SET_OFFSET 0x00000200U /**< Pending Set
+ Register */
+#define XSCUGIC_PENDING_CLR_OFFSET 0x00000280U /**< Pending Clear
+ Register */
+#define XSCUGIC_ACTIVE_OFFSET 0x00000300U /**< Active Status Register */
+#define XSCUGIC_PRIORITY_OFFSET 0x00000400U /**< Priority Level Register */
+#define XSCUGIC_SPI_TARGET_OFFSET 0x00000800U /**< SPI Target
+ Register 0x800-0x8FB */
+#define XSCUGIC_INT_CFG_OFFSET 0x00000C00U /**< Interrupt Configuration
+ Register 0xC00-0xCFC */
+#define XSCUGIC_PPI_STAT_OFFSET 0x00000D00U /**< PPI Status Register */
+#define XSCUGIC_SPI_STAT_OFFSET 0x00000D04U /**< SPI Status Register
+ 0xd04-0xd7C */
+#define XSCUGIC_AHB_CONFIG_OFFSET 0x00000D80U /**< AHB Configuration
+ Register */
+#define XSCUGIC_SFI_TRIG_OFFSET 0x00000F00U /**< Software Triggered
+ Interrupt Register */
+#define XSCUGIC_PERPHID_OFFSET 0x00000FD0U /**< Peripheral ID Reg */
+#if defined (GICv3)
+#define XSCUGIC_PCELLID_OFFSET 0x0000FFF0U /**< Pcell ID Register */
+#else
+#define XSCUGIC_PCELLID_OFFSET 0x00000FF0U /**< Pcell ID Register */
+#endif
+/* @} */
+
+/** @name Distributor Enable Register
+ * Controls if the distributor response to external interrupt inputs.
+ * @{
+ */
+#if defined (GICv3)
+#define XSCUGIC_EN_INT_MASK 0x00000003U /**< Interrupt In Enable */
+#else
+#define XSCUGIC_EN_INT_MASK 0x00000001U /**< Interrupt In Enable */
+#endif
+/* @} */
+
+/** @name Interrupt Controller Type Register
+ * @{
+ */
+#define XSCUGIC_LSPI_MASK 0x0000F800U /**< Number of Lockable
+ Shared Peripheral
+ Interrupts*/
+#define XSCUGIC_DOMAIN_MASK 0x00000400U /**< Number os Security domains*/
+#define XSCUGIC_CPU_NUM_MASK 0x000000E0U /**< Number of CPU Interfaces */
+#define XSCUGIC_NUM_INT_MASK 0x0000001FU /**< Number of Interrupt IDs */
+/* @} */
+
+/** @name Implementor ID Register
+ * Implementor and revision information.
+ * @{
+ */
+#define XSCUGIC_REV_MASK 0x00FFF000U /**< Revision Number */
+#define XSCUGIC_IMPL_MASK 0x00000FFFU /**< Implementor */
+/* @} */
+
+/** @name Interrupt Security Registers
+ * Each bit controls the security level of an interrupt, either secure or non
+ * secure. These registers can only be accessed using secure read and write.
+ * There are registers for each of the CPU interfaces at offset 0x080. A
+ * register set for the SPI interrupts is available to all CPU interfaces.
+ * There are up to 32 of these registers staring at location 0x084.
+ * @{
+ */
+#define XSCUGIC_INT_NS_MASK 0x00000001U /**< Each bit corresponds to an
+ INT_ID */
+/* @} */
+
+/** @name Enable Set Register
+ * Each bit controls the enabling of an interrupt, a 0 is disabled, a 1 is
+ * enabled. Writing a 0 has no effect. Use the ENABLE_CLR register to set a
+ * bit to 0.
+ * There are registers for each of the CPU interfaces at offset 0x100. With up
+ * to 8 registers aliased to the same address. A register set for the SPI
+ * interrupts is available to all CPU interfaces.
+ * There are up to 32 of these registers staring at location 0x104.
+ * @{
+ */
+#define XSCUGIC_INT_EN_MASK 0x00000001U /**< Each bit corresponds to an
+ INT_ID */
+/* @} */
+
+/** @name Enable Clear Register
+ * Each bit controls the disabling of an interrupt, a 0 is disabled, a 1 is
+ * enabled. Writing a 0 has no effect. Writing a 1 disables an interrupt and
+ * sets the corresponding bit to 0.
+ * There are registers for each of the CPU interfaces at offset 0x180. With up
+ * to 8 registers aliased to the same address.
+ * A register set for the SPI interrupts is available to all CPU interfaces.
+ * There are up to 32 of these registers staring at location 0x184.
+ * @{
+ */
+#define XSCUGIC_INT_CLR_MASK 0x00000001U /**< Each bit corresponds to an
+ INT_ID */
+/* @} */
+
+/** @name Pending Set Register
+ * Each bit controls the Pending or Active and Pending state of an interrupt, a
+ * 0 is not pending, a 1 is pending. Writing a 0 has no effect. Writing a 1 sets
+ * an interrupt to the pending state.
+ * There are registers for each of the CPU interfaces at offset 0x200. With up
+ * to 8 registers aliased to the same address.
+ * A register set for the SPI interrupts is available to all CPU interfaces.
+ * There are up to 32 of these registers staring at location 0x204.
+ * @{
+ */
+#define XSCUGIC_PEND_SET_MASK 0x00000001U /**< Each bit corresponds to an
+ INT_ID */
+/* @} */
+
+/** @name Pending Clear Register
+ * Each bit can clear the Pending or Active and Pending state of an interrupt, a
+ * 0 is not pending, a 1 is pending. Writing a 0 has no effect. Writing a 1
+ * clears the pending state of an interrupt.
+ * There are registers for each of the CPU interfaces at offset 0x280. With up
+ * to 8 registers aliased to the same address.
+ * A register set for the SPI interrupts is available to all CPU interfaces.
+ * There are up to 32 of these registers staring at location 0x284.
+ * @{
+ */
+#define XSCUGIC_PEND_CLR_MASK 0x00000001U /**< Each bit corresponds to an
+ INT_ID */
+/* @} */
+
+/** @name Active Status Register
+ * Each bit provides the Active status of an interrupt, a
+ * 0 is not Active, a 1 is Active. This is a read only register.
+ * There are registers for each of the CPU interfaces at offset 0x300. With up
+ * to 8 registers aliased to each address.
+ * A register set for the SPI interrupts is available to all CPU interfaces.
+ * There are up to 32 of these registers staring at location 0x380.
+ * @{
+ */
+#define XSCUGIC_ACTIVE_MASK 0x00000001U /**< Each bit corresponds to an
+ INT_ID */
+/* @} */
+
+/** @name Priority Level Register
+ * Each byte in a Priority Level Register sets the priority level of an
+ * interrupt. Reading the register provides the priority level of an interrupt.
+ * There are registers for each of the CPU interfaces at offset 0x400 through
+ * 0x41C. With up to 8 registers aliased to each address.
+ * 0 is highest priority, 0xFF is lowest.
+ * A register set for the SPI interrupts is available to all CPU interfaces.
+ * There are up to 255 of these registers staring at location 0x420.
+ * @{
+ */
+#define XSCUGIC_PRIORITY_MASK 0x000000FFU /**< Each Byte corresponds to an
+ INT_ID */
+#define XSCUGIC_PRIORITY_MAX 0x000000FFU /**< Highest value of a priority
+ actually the lowest priority*/
+/* @} */
+
+/** @name SPI Target Register 0x800-0x8FB
+ * Each byte references a separate SPI and programs which of the up to 8 CPU
+ * interfaces are sent a Pending interrupt.
+ * There are registers for each of the CPU interfaces at offset 0x800 through
+ * 0x81C. With up to 8 registers aliased to each address.
+ * A register set for the SPI interrupts is available to all CPU interfaces.
+ * There are up to 255 of these registers staring at location 0x820.
+ *
+ * This driver does not support multiple CPU interfaces. These are included
+ * for complete documentation.
+ * @{
+ */
+#define XSCUGIC_SPI_CPU7_MASK 0x00000080U /**< CPU 7 Mask*/
+#define XSCUGIC_SPI_CPU6_MASK 0x00000040U /**< CPU 6 Mask*/
+#define XSCUGIC_SPI_CPU5_MASK 0x00000020U /**< CPU 5 Mask*/
+#define XSCUGIC_SPI_CPU4_MASK 0x00000010U /**< CPU 4 Mask*/
+#define XSCUGIC_SPI_CPU3_MASK 0x00000008U /**< CPU 3 Mask*/
+#define XSCUGIC_SPI_CPU2_MASK 0x00000004U /**< CPU 2 Mask*/
+#define XSCUGIC_SPI_CPU1_MASK 0x00000002U /**< CPU 1 Mask*/
+#define XSCUGIC_SPI_CPU0_MASK 0x00000001U /**< CPU 0 Mask*/
+/* @} */
+
+/** @name Interrupt Configuration Register 0xC00-0xCFC
+ * The interrupt configuration registers program an SFI to be active HIGH level
+ * sensitive or rising edge sensitive.
+ * Each bit pair describes the configuration for an INT_ID.
+ * SFI Read Only b10 always
+ * PPI Read Only depending on how the PPIs are configured.
+ * b01 Active HIGH level sensitive
+ * b11 Rising edge sensitive
+ * SPI LSB is read only.
+ * b01 Active HIGH level sensitive
+ * b11 Rising edge sensitive/
+ * There are registers for each of the CPU interfaces at offset 0xC00 through
+ * 0xC04. With up to 8 registers aliased to each address.
+ * A register set for the SPI interrupts is available to all CPU interfaces.
+ * There are up to 255 of these registers staring at location 0xC08.
+ * @{
+ */
+#define XSCUGIC_INT_CFG_MASK 0x00000003U /**< */
+/* @} */
+
+/** @name PPI Status Register
+ * Enables an external AMBA master to access the status of the PPI inputs.
+ * A CPU can only read the status of its local PPI signals and cannot read the
+ * status for other CPUs.
+ * This register is aliased for each CPU interface.
+ * @{
+ */
+#define XSCUGIC_PPI_C15_MASK 0x00008000U /**< PPI Status */
+#define XSCUGIC_PPI_C14_MASK 0x00004000U /**< PPI Status */
+#define XSCUGIC_PPI_C13_MASK 0x00002000U /**< PPI Status */
+#define XSCUGIC_PPI_C12_MASK 0x00001000U /**< PPI Status */
+#define XSCUGIC_PPI_C11_MASK 0x00000800U /**< PPI Status */
+#define XSCUGIC_PPI_C10_MASK 0x00000400U /**< PPI Status */
+#define XSCUGIC_PPI_C09_MASK 0x00000200U /**< PPI Status */
+#define XSCUGIC_PPI_C08_MASK 0x00000100U /**< PPI Status */
+#define XSCUGIC_PPI_C07_MASK 0x00000080U /**< PPI Status */
+#define XSCUGIC_PPI_C06_MASK 0x00000040U /**< PPI Status */
+#define XSCUGIC_PPI_C05_MASK 0x00000020U /**< PPI Status */
+#define XSCUGIC_PPI_C04_MASK 0x00000010U /**< PPI Status */
+#define XSCUGIC_PPI_C03_MASK 0x00000008U /**< PPI Status */
+#define XSCUGIC_PPI_C02_MASK 0x00000004U /**< PPI Status */
+#define XSCUGIC_PPI_C01_MASK 0x00000002U /**< PPI Status */
+#define XSCUGIC_PPI_C00_MASK 0x00000001U /**< PPI Status */
+/* @} */
+
+/** @name SPI Status Register 0xd04-0xd7C
+ * Enables an external AMBA master to access the status of the SPI inputs.
+ * There are up to 63 registers if the maximum number of SPI inputs are
+ * configured.
+ * @{
+ */
+#define XSCUGIC_SPI_N_MASK 0x00000001U /**< Each bit corresponds to an SPI
+ input */
+/* @} */
+
+/** @name AHB Configuration Register
+ * Provides the status of the CFGBIGEND input signal and allows the endianness
+ * of the GIC to be set.
+ * @{
+ */
+#define XSCUGIC_AHB_END_MASK 0x00000004U /**< 0-GIC uses little Endian,
+ 1-GIC uses Big Endian */
+#define XSCUGIC_AHB_ENDOVR_MASK 0x00000002U /**< 0-Uses CFGBIGEND control,
+ 1-use the AHB_END bit */
+#define XSCUGIC_AHB_TIE_OFF_MASK 0x00000001U /**< State of CFGBIGEND */
+
+/* @} */
+
+/** @name Software Triggered Interrupt Register
+ * Controls issuing of software interrupts.
+ * @{
+ */
+#define XSCUGIC_SFI_SELFTRIG_MASK 0x02010000U
+#define XSCUGIC_SFI_TRIG_TRGFILT_MASK 0x03000000U /**< Target List filter
+ b00-Use the target List
+ b01-All CPUs except requester
+ b10-To Requester
+ b11-reserved */
+#define XSCUGIC_SFI_TRIG_CPU_MASK 0x00FF0000U /**< CPU Target list */
+#define XSCUGIC_SFI_TRIG_SATT_MASK 0x00008000U /**< 0= Use a secure interrupt */
+#define XSCUGIC_SFI_TRIG_INTID_MASK 0x0000000FU /**< Set to the INTID
+ signaled to the CPU*/
+/* @} */
+
+/** @name CPU Interface Register Map
+ *
+ * Define the offsets from the base address for all CPU registers of the
+ * interrupt controller, some registers may be reserved in the hardware device.
+ * @{
+ */
+#define XSCUGIC_CONTROL_OFFSET 0x00000000U /**< CPU Interface Control
+ Register */
+#define XSCUGIC_CPU_PRIOR_OFFSET 0x00000004U /**< Priority Mask Reg */
+#define XSCUGIC_BIN_PT_OFFSET 0x00000008U /**< Binary Point Register */
+#define XSCUGIC_INT_ACK_OFFSET 0x0000000CU /**< Interrupt ACK Reg */
+#define XSCUGIC_EOI_OFFSET 0x00000010U /**< End of Interrupt Reg */
+#define XSCUGIC_RUN_PRIOR_OFFSET 0x00000014U /**< Running Priority Reg */
+#define XSCUGIC_HI_PEND_OFFSET 0x00000018U /**< Highest Pending Interrupt
+ Register */
+#define XSCUGIC_ALIAS_BIN_PT_OFFSET 0x0000001CU /**< Aliased non-Secure
+ Binary Point Register */
+
+/**< 0x00000020 to 0x00000FBC are reserved and should not be read or written
+ * to. */
+/* @} */
+
+
+/** @name Control Register
+ * CPU Interface Control register definitions
+ * All bits are defined here although some are not available in the non-secure
+ * mode.
+ * @{
+ */
+#define XSCUGIC_CNTR_SBPR_MASK 0x00000010U /**< Secure Binary Pointer,
+ 0=separate registers,
+ 1=both use bin_pt_s */
+#define XSCUGIC_CNTR_FIQEN_MASK 0x00000008U /**< Use nFIQ_C for secure
+ interrupts,
+ 0= use IRQ for both,
+ 1=Use FIQ for secure, IRQ for non*/
+#define XSCUGIC_CNTR_ACKCTL_MASK 0x00000004U /**< Ack control for secure or non secure */
+#define XSCUGIC_CNTR_EN_NS_MASK 0x00000002U /**< Non Secure enable */
+#define XSCUGIC_CNTR_EN_S_MASK 0x00000001U /**< Secure enable, 0=Disabled, 1=Enabled */
+/* @} */
+
+/** @name Priority Mask Register
+ * Priority Mask register definitions
+ * The CPU interface does not send interrupt if the level of the interrupt is
+ * lower than the level of the register.
+ * @{
+ */
+/*#define XSCUGIC_PRIORITY_MASK 0x000000FFU*/ /**< All interrupts */
+/* @} */
+
+/** @name Binary Point Register
+ * Binary Point register definitions
+ * @{
+ */
+
+#define XSCUGIC_BIN_PT_MASK 0x00000007U /**< Binary point mask value
+ Value Secure Non-secure
+ b000 0xFE 0xFF
+ b001 0xFC 0xFE
+ b010 0xF8 0xFC
+ b011 0xF0 0xF8
+ b100 0xE0 0xF0
+ b101 0xC0 0xE0
+ b110 0x80 0xC0
+ b111 0x00 0x80
+ */
+/*@}*/
+
+/** @name Interrupt Acknowledge Register
+ * Interrupt Acknowledge register definitions
+ * Identifies the current Pending interrupt, and the CPU ID for software
+ * interrupts.
+ */
+#define XSCUGIC_ACK_INTID_MASK 0x000003FFU /**< Interrupt ID */
+#define XSCUGIC_CPUID_MASK 0x00000C00U /**< CPU ID */
+/* @} */
+
+/** @name End of Interrupt Register
+ * End of Interrupt register definitions
+ * Allows the CPU to signal the GIC when it completes an interrupt service
+ * routine.
+ */
+#define XSCUGIC_EOI_INTID_MASK 0x000003FFU /**< Interrupt ID */
+
+/* @} */
+
+/** @name Running Priority Register
+ * Running Priority register definitions
+ * Identifies the interrupt priority level of the highest priority active
+ * interrupt.
+ */
+#define XSCUGIC_RUN_PRIORITY_MASK 0x000000FFU /**< Interrupt Priority */
+/* @} */
+
+#if defined (GICv3)
+#define XSCUGIC_IROUTER_BASE_OFFSET 0x6000U
+#endif
+/*
+ * Highest Pending Interrupt register definitions
+ * Identifies the interrupt priority of the highest priority pending interrupt
+ */
+#define XSCUGIC_PEND_INTID_MASK 0x000003FFU /**< Pending Interrupt ID */
+/*#define XSCUGIC_CPUID_MASK 0x00000C00U */ /**< CPU ID */
+/* @} */
+#if defined (GICv3)
+/** @name ReDistributor Interface Register Map
+ *
+ * @{
+ */
+#define XSCUGIC_RDIST_OFFSET 0x80000U
+#define XSCUGIC_RDIST_BASE_ADDRESS (XPAR_SCUGIC_0_DIST_BASEADDR + XSCUGIC_RDIST_OFFSET)
+#define XSCUGIC_RDIST_SGI_PPI_OFFSET 0x90000U
+#define XSCUGIC_RDIST_SGI_PPI_BASE_ADDRESS (XPAR_SCUGIC_0_DIST_BASEADDR + XSCUGIC_RDIST_SGI_PPI_OFFSET)
+#define XSCUGIC_RDIST_ISENABLE_OFFSET 0x100U
+#define XSCUGIC_RDIST_IPRIORITYR_OFFSET 0x400U
+#define XSCUGIC_RDIST_IGROUPR_OFFSET 0x80U
+#define XSCUGIC_RDIST_GRPMODR_OFFSET 0xD00U
+#define XSCUGIC_RDIST_INT_CONFIG_OFFSET 0xC00U
+#define XSCUGIC_RDIST_WAKER_OFFSET 0x14U
+#define XSCUGIC_SGIR_EL1_INITID_SHIFT 24U
+
+/*
+ * GICR_IGROUPR register definitions
+ */
+#if EL3
+#define XSCUGIC_DEFAULT_SECURITY 0x0U
+#else
+#define XSCUGIC_DEFAULT_SECURITY 0xFFFFFFFFU
+#endif
+/*
+ * GICR_WAKER register definitions
+ */
+#define XSCUGIC_RDIST_WAKER_LOW_POWER_STATE_MASK 0x7
+#endif
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/****************************************************************************/
+/**
+*
+* Read the Interrupt Configuration Register offset for an interrupt id.
+*
+* @param InterruptID is the interrupt number.
+*
+* @return The 32-bit value of the offset
+*
+* @note
+*
+*****************************************************************************/
+#define XSCUGIC_INT_CFG_OFFSET_CALC(InterruptID) \
+ ((u32)XSCUGIC_INT_CFG_OFFSET + (((InterruptID)/16U) * 4U))
+
+/****************************************************************************/
+/**
+*
+* Read the Interrupt Priority Register offset for an interrupt id.
+*
+* @param InterruptID is the interrupt number.
+*
+* @return The 32-bit value of the offset
+*
+* @note
+*
+*****************************************************************************/
+#define XSCUGIC_PRIORITY_OFFSET_CALC(InterruptID) \
+ ((u32)XSCUGIC_PRIORITY_OFFSET + (((InterruptID)/4U) * 4U))
+
+/****************************************************************************/
+/**
+*
+* Read the Interrupt Routing Register offset for an interrupt id.
+*
+* @param InterruptID is the interrupt number.
+*
+* @return The 32-bit value of the offset
+*
+* @note
+*
+*****************************************************************************/
+#define XSCUGIC_IROUTER_OFFSET_CALC(InterruptID) \
+ ((u32)XSCUGIC_IROUTER_BASE_OFFSET + (InterruptID * 8))
+
+/****************************************************************************/
+/**
+*
+* Read the SPI Target Register offset for an interrupt id.
+*
+* @param InterruptID is the interrupt number.
+*
+* @return The 32-bit value of the offset
+*
+* @note
+*
+*****************************************************************************/
+#define XSCUGIC_SPI_TARGET_OFFSET_CALC(InterruptID) \
+ ((u32)XSCUGIC_SPI_TARGET_OFFSET + (((InterruptID)/4U) * 4U))
+/****************************************************************************/
+/**
+*
+* Read the SPI Target Register offset for an interrupt id.
+*
+* @param InterruptID is the interrupt number.
+*
+* @return The 32-bit value of the offset
+*
+* @note
+*
+*****************************************************************************/
+#define XSCUGIC_SECURITY_TARGET_OFFSET_CALC(InterruptID) \
+ ((u32)XSCUGIC_SECURITY_OFFSET + (((InterruptID)/32U)*4U))
+
+/****************************************************************************/
+/**
+*
+* Read the Re-distributor Interrupt configuration register offset
+*
+* @param InterruptID is the interrupt number.
+*
+* @return The 32-bit value of the offset
+*
+* @note
+*
+*****************************************************************************/
+#define XSCUGIC_RDIST_INT_CONFIG_OFFSET_CALC(InterruptID) \
+ ((u32)XSCUGIC_RDIST_INT_CONFIG_OFFSET + ((InterruptID /16)*4))
+
+/****************************************************************************/
+/**
+*
+* Read the Re-distributor Interrupt Priority register offset
+*
+* @param InterruptID is the interrupt number.
+*
+* @return The 32-bit value of the offset
+*
+* @note
+*
+*****************************************************************************/
+#define XSCUGIC_RDIST_INT_PRIORITY_OFFSET_CALC(InterruptID) \
+ ((u32)XSCUGIC_RDIST_IPRIORITYR_OFFSET + (InterruptID * 4))
+/****************************************************************************/
+/**
+*
+* Read the Interrupt Clear-Enable Register offset for an interrupt ID
+*
+* @param Register is the register offset for the clear/enable bank.
+* @param InterruptID is the interrupt number.
+*
+* @return The 32-bit value of the offset
+*
+* @note
+*
+*****************************************************************************/
+#define XSCUGIC_EN_DIS_OFFSET_CALC(Register, InterruptID) \
+ ((Register) + (((InterruptID)/32U) * 4U))
+
+/****************************************************************************/
+/**
+*
+* Read the given Intc register.
+*
+* @param BaseAddress is the base address of the device.
+* @param RegOffset is the register offset to be read
+*
+* @return The 32-bit value of the register
+*
+* @note
+* C-style signature:
+* u32 XScuGic_ReadReg(u32 BaseAddress, u32 RegOffset)
+*
+*****************************************************************************/
+#define XScuGic_ReadReg(BaseAddress, RegOffset) \
+ (Xil_In32((BaseAddress) + (RegOffset)))
+
+
+/****************************************************************************/
+/**
+*
+* Write the given Intc register.
+*
+* @param BaseAddress is the base address of the device.
+* @param RegOffset is the register offset to be written
+* @param Data is the 32-bit value to write to the register
+*
+* @return None.
+*
+* @note
+* C-style signature:
+* void XScuGic_WriteReg(u32 BaseAddress, u32 RegOffset, u32 Data)
+*
+*****************************************************************************/
+#define XScuGic_WriteReg(BaseAddress, RegOffset, Data) \
+ (Xil_Out32(((BaseAddress) + (RegOffset)), ((u32)(Data))))
+
+
+/************************** Function Prototypes ******************************/
+
+void XScuGic_DeviceInterruptHandler(void *DeviceId);
+s32 XScuGic_DeviceInitialize(u32 DeviceId);
+void XScuGic_RegisterHandler(u32 BaseAddress, s32 InterruptID,
+ Xil_InterruptHandler Handler, void *CallBackRef);
+void XScuGic_SetPriTrigTypeByDistAddr(u32 DistBaseAddress, u32 Int_Id,
+ u8 Priority, u8 Trigger);
+void XScuGic_GetPriTrigTypeByDistAddr(u32 DistBaseAddress, u32 Int_Id,
+ u8 *Priority, u8 *Trigger);
+void XScuGic_InterruptMapFromCpuByDistAddr(u32 DistBaseAddress,
+ u8 Cpu_Id, u32 Int_Id);
+void XScuGic_InterruptUnmapFromCpuByDistAddr(u32 DistBaseAddress,
+ u8 Cpu_Id, u32 Int_Id);
+void XScuGic_UnmapAllInterruptsFromCpuByDistAddr(u32 DistBaseAddress,
+ u8 Cpu_Id);
+void XScuGic_EnableIntr (u32 DistBaseAddress, u32 Int_Id);
+void XScuGic_DisableIntr (u32 DistBaseAddress, u32 Int_Id);
+/************************** Variable Definitions *****************************/
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* end of protection macro */
+/** @} */
diff --git a/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/scugic_v4_1/src/xscugic_intr.c b/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/scugic_v4_1/src/xscugic_intr.c
new file mode 100644
index 0000000..f15fb9c
--- /dev/null
+++ b/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/scugic_v4_1/src/xscugic_intr.c
@@ -0,0 +1,183 @@
+/******************************************************************************
+*
+* Copyright (C) 2010 - 2019 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+* THE SOFTWARE.
+*
+*
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xscugic_intr.c
+* @addtogroup scugic_v4_0
+* @{
+*
+* This file contains the interrupt processing for the driver for the Xilinx
+* Interrupt Controller. The interrupt processing is partitioned separately such
+* that users are not required to use the provided interrupt processing. This
+* file requires other files of the driver to be linked in also.
+*
+* The interrupt handler, XScuGic_InterruptHandler, uses an input argument which
+* is an instance pointer to an interrupt controller driver such that multiple
+* interrupt controllers can be supported. This handler requires the calling
+* function to pass it the appropriate argument, so another level of indirection
+* may be required.
+*
+* The interrupt processing may be used by connecting the interrupt handler to
+* the interrupt system. The handler does not save and restore the processor
+* context but only handles the processing of the Interrupt Controller. The user
+* is encouraged to supply their own interrupt handler when performance tuning is
+* deemed necessary.
+*
+* <pre>
+* MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ----- ---- -------- ---------------------------------------------------------
+* 1.00a drg 01/19/10 First release
+* 1.01a sdm 11/09/11 XScuGic_InterruptHandler has changed correspondingly
+* since the HandlerTable has now moved to XScuGic_Config.
+* 3.00 kvn 02/13/15 Modified code for MISRA-C:2012 compliance.
+* 3.10 mus 07/17/18 Updated XScuGic_InterruptHandler to fix array overrun
+* reported by coverity tool. It fixes CR#1006344.
+* 3.10 mus 07/17/18 Updated file to fix the various coding style issues
+* reported by checkpatch. It fixes CR#1006344.
+*
+* </pre>
+*
+* @internal
+*
+* This driver assumes that the context of the processor has been saved prior to
+* the calling of the Interrupt Controller interrupt handler and then restored
+* after the handler returns. This requires either the running RTOS to save the
+* state of the machine or that a wrapper be used as the destination of the
+* interrupt vector to save the state of the processor and restore the state
+* after the interrupt handler returns.
+*
+******************************************************************************/
+
+/***************************** Include Files *********************************/
+
+#include "xil_types.h"
+#include "xil_assert.h"
+#include "xscugic.h"
+
+/************************** Constant Definitions *****************************/
+
+/**************************** Type Definitions *******************************/
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/************************** Function Prototypes ******************************/
+
+/************************** Variable Definitions *****************************/
+
+/*****************************************************************************/
+/**
+* This function is the primary interrupt handler for the driver. It must be
+* connected to the interrupt source such that it is called when an interrupt of
+* the interrupt controller is active. It will resolve which interrupts are
+* active and enabled and call the appropriate interrupt handler. It uses
+* the Interrupt Type information to determine when to acknowledge the interrupt.
+* Highest priority interrupts are serviced first.
+*
+* This function assumes that an interrupt vector table has been previously
+* initialized. It does not verify that entries in the table are valid before
+* calling an interrupt handler.
+*
+*
+* @param InstancePtr is a pointer to the XScuGic instance.
+*
+* @return None.
+*
+* @note None.
+*
+******************************************************************************/
+void XScuGic_InterruptHandler(XScuGic *InstancePtr)
+{
+
+ u32 InterruptID;
+#if !defined (GICv3)
+ u32 IntIDFull;
+#endif
+ XScuGic_VectorTableEntry *TablePtr;
+
+ /* Assert that the pointer to the instance is valid
+ */
+ Xil_AssertVoid(InstancePtr != NULL);
+
+ /*
+ * Read the int_ack register to identify the highest priority
+ * interrupt ID and make sure it is valid. Reading Int_Ack will
+ * clear the interrupt in the GIC.
+ */
+#if defined (GICv3)
+ InterruptID = XScuGic_get_IntID();
+#else
+ IntIDFull = XScuGic_CPUReadReg(InstancePtr, XSCUGIC_INT_ACK_OFFSET);
+ InterruptID = IntIDFull & XSCUGIC_ACK_INTID_MASK;
+#endif
+ if (XSCUGIC_MAX_NUM_INTR_INPUTS <= InterruptID) {
+ goto IntrExit;
+ }
+
+ /*
+ * If the interrupt is shared, do some locking here if
+ * there are multiple processors.
+ */
+ /*
+ * If pre-eption is required:
+ * Re-enable pre-emption by setting the CPSR I bit for non-secure ,
+ * interrupts or the F bit for secure interrupts
+ */
+
+ /*
+ * If we need to change security domains, issue a SMC
+ * instruction here.
+ */
+
+ /*
+ * Execute the ISR. Jump into the Interrupt service routine
+ * based on the IRQSource. A software trigger is cleared by
+ *.the ACK.
+ */
+ TablePtr = &(InstancePtr->Config->HandlerTable[InterruptID]);
+ if (TablePtr != NULL) {
+ TablePtr->Handler(TablePtr->CallBackRef);
+ }
+
+IntrExit:
+ /*
+ * Write to the EOI register, we are all done here.
+ * Let this function return, the boot code will restore the stack.
+ */
+#if defined (GICv3)
+ XScuGic_ack_Int(InterruptID);
+
+#else
+ XScuGic_CPUWriteReg(InstancePtr, XSCUGIC_EOI_OFFSET, IntIDFull);
+#endif
+ /*
+ * Return from the interrupt. Change security domains
+ * could happen here.
+ */
+}
+/** @} */
diff --git a/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/scugic_v4_1/src/xscugic_selftest.c b/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/scugic_v4_1/src/xscugic_selftest.c
new file mode 100644
index 0000000..645b5dd
--- /dev/null
+++ b/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/scugic_v4_1/src/xscugic_selftest.c
@@ -0,0 +1,112 @@
+/******************************************************************************
+*
+* Copyright (C) 2010 - 2019 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+* THE SOFTWARE.
+*
+*
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xscugic_selftest.c
+* @addtogroup scugic_v4_0
+* @{
+*
+* Contains diagnostic self-test functions for the XScuGic driver.
+* <pre>
+* MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ----- ---- -------- -----------------------------------------------
+* 1.00a drg 01/19/10 First release
+* 3.00 kvn 02/13/15 Modified code for MISRA-C:2012 compliance.
+* 3.10 mus 07/17/18 Updated file to fix the various coding style issues
+* reported by checkpatch. It fixes CR#1006344.
+*
+* </pre>
+*
+******************************************************************************/
+
+/***************************** Include Files *********************************/
+
+#include "xil_types.h"
+#include "xil_assert.h"
+#include "xscugic.h"
+
+/************************** Constant Definitions *****************************/
+
+#define XSCUGIC_PCELL_ID 0xB105F00DU
+
+/**************************** Type Definitions *******************************/
+
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+
+/************************** Function Prototypes ******************************/
+
+/************************** Variable Definitions *****************************/
+
+/*****************************************************************************/
+/**
+*
+* Run a self-test on the driver/device. This test reads the ID registers and
+* compares them.
+*
+* @param InstancePtr is a pointer to the XScuGic instance.
+*
+* @return
+*
+* -XST_SUCCESS if self-test is successful.
+* -XST_FAILURE if the self-test is not successful.
+*
+* @note None.
+*
+******************************************************************************/
+s32 XScuGic_SelfTest(XScuGic *InstancePtr)
+{
+ u32 RegValue1 = 0U;
+ u32 Index;
+ s32 Status;
+
+ /*
+ * Assert the arguments
+ */
+ Xil_AssertNonvoid(InstancePtr != NULL);
+ Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+ /*
+ * Read the ID registers.
+ */
+ for (Index = 0U; Index <= 3U; Index++) {
+ RegValue1 |= XScuGic_DistReadReg(InstancePtr,
+ ((u32)XSCUGIC_PCELLID_OFFSET + (Index * 4U))) <<
+ (Index * 8U);
+ }
+
+ if (XSCUGIC_PCELL_ID != RegValue1) {
+ Status = XST_FAILURE;
+ } else {
+ Status = XST_SUCCESS;
+ }
+ return Status;
+}
+/** @} */
diff --git a/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/scugic_v4_1/src/xscugic_sinit.c b/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/scugic_v4_1/src/xscugic_sinit.c
new file mode 100644
index 0000000..41743f5
--- /dev/null
+++ b/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/scugic_v4_1/src/xscugic_sinit.c
@@ -0,0 +1,99 @@
+/******************************************************************************
+*
+* Copyright (C) 2010 - 2019 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+* THE SOFTWARE.
+*
+*
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xscugic_sinit.c
+* @addtogroup scugic_v4_0
+* @{
+*
+* Contains static init functions for the XScuGic driver for the Interrupt
+* Controller. See xscugic.h for a detailed description of the driver.
+*
+* <pre>
+* MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ----- ---- -------- --------------------------------------------------------
+* 1.00a drg 01/19/10 First release
+* 3.00 kvn 02/13/15 Modified code for MISRA-C:2012 compliance.
+* 3.10 mus 07/17/18 Updated file to fix the various coding style issues
+* reported by checkpatch. It fixes CR#1006344.
+*
+* </pre>
+*
+******************************************************************************/
+
+/***************************** Include Files *********************************/
+
+#include "xil_types.h"
+#include "xil_assert.h"
+#include "xparameters.h"
+#include "xscugic.h"
+
+/************************** Constant Definitions *****************************/
+
+
+/**************************** Type Definitions *******************************/
+
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/************************** Variable Definitions *****************************/
+
+extern XScuGic_Config XScuGic_ConfigTable[XPAR_SCUGIC_NUM_INSTANCES];
+
+/************************** Function Prototypes ******************************/
+
+/*****************************************************************************/
+/**
+*
+* Looks up the device configuration based on the unique device ID. A table
+* contains the configuration info for each device in the system.
+*
+* @param DeviceId is the unique identifier for a device.
+*
+* @return A pointer to the XScuGic configuration structure for the
+* specified device, or NULL if the device was not found.
+*
+* @note None.
+*
+******************************************************************************/
+XScuGic_Config *XScuGic_LookupConfig(u16 DeviceId)
+{
+ XScuGic_Config *CfgPtr = NULL;
+ u32 Index;
+
+ for (Index = 0U; Index < (u32)XPAR_SCUGIC_NUM_INSTANCES; Index++) {
+ if (XScuGic_ConfigTable[Index].DeviceId == DeviceId) {
+ CfgPtr = &XScuGic_ConfigTable[Index];
+ break;
+ }
+ }
+
+ return (XScuGic_Config *)CfgPtr;
+}
+/** @} */
diff --git a/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/scutimer_v2_1/src/Makefile b/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/scutimer_v2_1/src/Makefile
new file mode 100644
index 0000000..7c673d4
--- /dev/null
+++ b/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/scutimer_v2_1/src/Makefile
@@ -0,0 +1,40 @@
+COMPILER=
+ARCHIVER=
+CP=cp
+COMPILER_FLAGS=
+EXTRA_COMPILER_FLAGS=
+LIB=libxil.a
+
+CC_FLAGS = $(COMPILER_FLAGS)
+ECC_FLAGS = $(EXTRA_COMPILER_FLAGS)
+
+RELEASEDIR=../../../lib
+INCLUDEDIR=../../../include
+INCLUDES=-I./. -I${INCLUDEDIR}
+
+OUTS = *.o
+
+LIBSOURCES:=*.c
+INCLUDEFILES:=*.h
+
+OBJECTS = $(addsuffix .o, $(basename $(wildcard *.c)))
+
+libs: banner scutimer_libs clean
+
+%.o: %.c
+ ${COMPILER} $(CC_FLAGS) $(ECC_FLAGS) $(INCLUDES) -o $@ $<
+
+banner:
+ echo "Compiling scutimer"
+
+scutimer_libs: ${OBJECTS}
+ $(ARCHIVER) -r ${RELEASEDIR}/${LIB} ${OBJECTS}
+
+.PHONY: include
+include: scutimer_includes
+
+scutimer_includes:
+ ${CP} ${INCLUDEFILES} ${INCLUDEDIR}
+
+clean:
+ rm -rf ${OBJECTS}
diff --git a/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/scutimer_v2_1/src/xscutimer.c b/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/scutimer_v2_1/src/xscutimer.c
new file mode 100644
index 0000000..7c03a34
--- /dev/null
+++ b/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/scutimer_v2_1/src/xscutimer.c
@@ -0,0 +1,280 @@
+/******************************************************************************
+*
+* Copyright (C) 2010 - 2015 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+* THE SOFTWARE.
+*
+*
+*
+******************************************************************************/
+/****************************************************************************/
+/**
+*
+* @file xscutimer.c
+* @addtogroup scutimer_v2_1
+* @{
+*
+* Contains the implementation of interface functions of the SCU Timer driver.
+* See xscutimer.h for a description of the driver.
+*
+* <pre>
+* MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ----- --- -------- ---------------------------------------------
+* 1.00a nm 03/10/10 First release
+* 2.1 sk 02/26/15 Modified the code for MISRA-C:2012 compliance.
+* </pre>
+*
+******************************************************************************/
+
+/***************************** Include Files *********************************/
+
+#include "xscutimer.h"
+
+/************************** Constant Definitions *****************************/
+
+/**************************** Type Definitions *******************************/
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/************************** Function Prototypes ******************************/
+
+/************************** Variable Definitions *****************************/
+
+/****************************************************************************/
+/**
+*
+* Initialize a specific timer instance/driver. This function must be called
+* before other functions of the driver are called.
+*
+* @param InstancePtr is a pointer to the XScuTimer instance.
+* @param ConfigPtr points to the XScuTimer configuration structure.
+* @param EffectiveAddress is the base address for the device. It could be
+* a virtual address if address translation is supported in the
+* system, otherwise it is the physical address.
+*
+* @return
+* - XST_SUCCESS if initialization was successful.
+* - XST_DEVICE_IS_STARTED if the device has already been started.
+*
+* @note None.
+*
+******************************************************************************/
+s32 XScuTimer_CfgInitialize(XScuTimer *InstancePtr,
+ XScuTimer_Config *ConfigPtr, u32 EffectiveAddress)
+{
+ s32 Status;
+ Xil_AssertNonvoid(InstancePtr != NULL);
+ Xil_AssertNonvoid(ConfigPtr != NULL);
+
+ /*
+ * If the device is started, disallow the initialize and return a
+ * status indicating it is started. This allows the user to stop the
+ * device and reinitialize, but prevents a user from inadvertently
+ * initializing.
+ */
+ if (InstancePtr->IsStarted != XIL_COMPONENT_IS_STARTED) {
+ /*
+ * Copy configuration into the instance structure.
+ */
+ InstancePtr->Config.DeviceId = ConfigPtr->DeviceId;
+
+ /*
+ * Save the base address pointer such that the registers of the block
+ * can be accessed and indicate it has not been started yet.
+ */
+ InstancePtr->Config.BaseAddr = EffectiveAddress;
+
+ InstancePtr->IsStarted = (u32)0;
+
+ /*
+ * Indicate the instance is ready to use, successfully initialized.
+ */
+ InstancePtr->IsReady = XIL_COMPONENT_IS_READY;
+
+ Status =(s32)XST_SUCCESS;
+ }
+ else {
+ Status = (s32)XST_DEVICE_IS_STARTED;
+ }
+ return Status;
+}
+
+/****************************************************************************/
+/**
+*
+* Start the timer.
+*
+* @param InstancePtr is a pointer to the XScuTimer instance.
+*
+* @return None.
+*
+* @note None.
+*
+******************************************************************************/
+void XScuTimer_Start(XScuTimer *InstancePtr)
+{
+ u32 Register;
+
+ Xil_AssertVoid(InstancePtr != NULL);
+ Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+ /*
+ * Read the contents of the Control register.
+ */
+ Register = XScuTimer_ReadReg(InstancePtr->Config.BaseAddr,
+ XSCUTIMER_CONTROL_OFFSET);
+
+ /*
+ * Set the 'timer enable' bit in the register.
+ */
+ Register |= XSCUTIMER_CONTROL_ENABLE_MASK;
+
+ /*
+ * Update the Control register with the new value.
+ */
+ XScuTimer_WriteReg(InstancePtr->Config.BaseAddr,
+ XSCUTIMER_CONTROL_OFFSET, Register);
+
+ /*
+ * Indicate that the device is started.
+ */
+ InstancePtr->IsStarted = XIL_COMPONENT_IS_STARTED;
+}
+
+/****************************************************************************/
+/**
+*
+* Stop the timer.
+*
+* @param InstancePtr is a pointer to the XScuTimer instance.
+*
+* @return None.
+*
+* @note None.
+*
+******************************************************************************/
+void XScuTimer_Stop(XScuTimer *InstancePtr)
+{
+ u32 Register;
+
+ Xil_AssertVoid(InstancePtr != NULL);
+ Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+ /*
+ * Read the contents of the Control register.
+ */
+ Register = XScuTimer_ReadReg(InstancePtr->Config.BaseAddr,
+ XSCUTIMER_CONTROL_OFFSET);
+
+ /*
+ * Clear the 'timer enable' bit in the register.
+ */
+ Register &= (u32)(~XSCUTIMER_CONTROL_ENABLE_MASK);
+
+ /*
+ * Update the Control register with the new value.
+ */
+ XScuTimer_WriteReg(InstancePtr->Config.BaseAddr,
+ XSCUTIMER_CONTROL_OFFSET, Register);
+
+ /*
+ * Indicate that the device is stopped.
+ */
+ InstancePtr->IsStarted = (u32)0;
+}
+
+/*****************************************************************************/
+/**
+*
+* This function sets the prescaler bits in the timer control register.
+*
+* @param InstancePtr is a pointer to the XScuTimer instance.
+* @param PrescalerValue is a 8 bit value that sets the prescaler to use.
+*
+* @return None
+*
+* @note None
+*
+****************************************************************************/
+void XScuTimer_SetPrescaler(XScuTimer *InstancePtr, u8 PrescalerValue)
+{
+ u32 ControlReg;
+
+ /*
+ * Assert to validate input arguments.
+ */
+ Xil_AssertVoid(InstancePtr != NULL);
+ Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+ /*
+ * Read the Timer control register.
+ */
+ ControlReg = XScuTimer_ReadReg(InstancePtr->Config.BaseAddr,
+ XSCUTIMER_CONTROL_OFFSET);
+
+ /*
+ * Clear all of the prescaler control bits in the register.
+ */
+ ControlReg &= (u32)(~XSCUTIMER_CONTROL_PRESCALER_MASK);
+
+ /*
+ * Set the prescaler value.
+ */
+ ControlReg |= (((u32)PrescalerValue) << XSCUTIMER_CONTROL_PRESCALER_SHIFT);
+
+ /*
+ * Write the register with the new values.
+ */
+ XScuTimer_WriteReg(InstancePtr->Config.BaseAddr,
+ XSCUTIMER_CONTROL_OFFSET, ControlReg);
+}
+
+/*****************************************************************************/
+/**
+*
+* This function returns the current prescaler value.
+*
+* @param InstancePtr is a pointer to the XScuTimer instance.
+*
+* @return The prescaler value.
+*
+* @note None.
+*
+****************************************************************************/
+u8 XScuTimer_GetPrescaler(XScuTimer *InstancePtr)
+{
+ u32 ControlReg;
+
+ /*
+ * Assert to validate input arguments.
+ */
+ Xil_AssertNonvoid(InstancePtr != NULL);
+ Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+ /*
+ * Read the Timer control register.
+ */
+ ControlReg = XScuTimer_ReadReg(InstancePtr->Config.BaseAddr,
+ XSCUTIMER_CONTROL_OFFSET);
+ ControlReg &= XSCUTIMER_CONTROL_PRESCALER_MASK;
+
+ return (u8)(ControlReg >> XSCUTIMER_CONTROL_PRESCALER_SHIFT);
+}
+/** @} */
diff --git a/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/scutimer_v2_1/src/xscutimer.h b/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/scutimer_v2_1/src/xscutimer.h
new file mode 100644
index 0000000..a3c0be8
--- /dev/null
+++ b/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/scutimer_v2_1/src/xscutimer.h
@@ -0,0 +1,362 @@
+/******************************************************************************
+*
+* Copyright (C) 2010 - 2015 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+* THE SOFTWARE.
+*
+*
+*
+******************************************************************************/
+/****************************************************************************/
+/**
+*
+* @file xscutimer.h
+* @addtogroup scutimer_v2_1
+* @{
+* @details
+*
+* The timer driver supports the Cortex A9 private timer.
+*
+* The timer driver supports the following features:
+* - Normal mode and Auto reload mode
+* - Interrupts (Interrupt handler is not provided in this driver. Application
+* has to register it's own handler)
+*
+* <b> Initialization and Configuration </b>
+*
+* The device driver enables higher layer software (e.g., an application) to
+* communicate with the Timer.
+*
+* XScuTimer_CfgInitialize() API is used to initialize the Timer. The
+* user needs to first call the XScuTimer_LookupConfig() API which returns
+* the Configuration structure pointer which is passed as a parameter to
+* the XScuTimer_CfgInitialize() API.
+*
+* <b> Interrupts </b>
+*
+* The Timer hardware supports interrupts.
+*
+* This driver does not provide a Interrupt Service Routine (ISR) for the device.
+* It is the responsibility of the application to provide one if needed. Refer to
+* the interrupt example provided with this driver for details on using the
+* Timer in interrupt mode.
+*
+* <b> Virtual Memory </b>
+*
+* This driver supports Virtual Memory. The RTOS is responsible for calculating
+* the correct device base address in Virtual Memory space.
+*
+* <b> Threads </b>
+*
+* This driver is not thread safe. Any needs for threads or thread mutual
+* exclusion must be satisfied by the layer above this driver.
+*
+* <b> Asserts </b>
+*
+* Asserts are used within all Xilinx drivers to enforce constraints on argument
+* values. Asserts can be turned off on a system-wide basis by defining, at
+* compile time, the NDEBUG identifier. By default, asserts are turned on and it
+* is recommended that users leave asserts on during development.
+*
+* <b> Building the driver </b>
+*
+* The XScuTimer driver is composed of several source files. This allows the user
+* to build and link only those parts of the driver that are necessary.
+*
+* <br><br>
+*
+* NOTE:
+* The timer is not a part of the snoop control unit as indicated by the
+* prefix "scu" in the name of the driver.
+* It is an independent module in APU.
+*
+* <pre>
+* MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ----- --- -------- ---------------------------------------------
+* 1.00a nm 03/10/10 First release
+* 1.02a sg 07/17/12 Included xil_assert.h for CR 667947. This is an issue
+* when the xstatus.h in the common driver overwrites
+* the xstatus.h of the standalone BSP during the
+* libgen.
+* 2.1 sk 02/26/15 Modified the code for MISRA-C:2012 compliance.
+* ms 03/17/17 Added readme.txt file in examples folder for doxygen
+* generation.
+* </pre>
+*
+******************************************************************************/
+#ifndef XSCUTIMER_H /* prevent circular inclusions */
+#define XSCUTIMER_H /* by using protection macros */
+
+/***************************** Include Files *********************************/
+
+#include "xstatus.h"
+#include "xscutimer_hw.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/************************** Constant Definitions *****************************/
+
+/**************************** Type Definitions *******************************/
+
+/**
+ * This typedef contains configuration information for the device.
+ */
+typedef struct {
+ u16 DeviceId; /**< Unique ID of device */
+ u32 BaseAddr; /**< Base address of the device */
+} XScuTimer_Config;
+
+/**
+ * The XScuTimer driver instance data. The user is required to allocate a
+ * variable of this type for every timer device in the system.
+ * A pointer to a variable of this type is then passed to the driver API
+ * functions.
+ */
+typedef struct {
+ XScuTimer_Config Config; /**< Hardware Configuration */
+ u32 IsReady; /**< Device is initialized and ready */
+ u32 IsStarted; /**< Device timer is running */
+} XScuTimer;
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/****************************************************************************/
+/**
+*
+* Check if the timer has expired.
+*
+* @param InstancePtr is a pointer to the XScuTimer instance.
+*
+* @return
+* - TRUE if the timer has expired.
+* - FALSE if the timer has not expired.
+*
+* @note C-style signature:
+* int XScuTimer_IsExpired(XScuTimer *InstancePtr)
+*
+******************************************************************************/
+#define XScuTimer_IsExpired(InstancePtr) \
+ ((XScuTimer_ReadReg((InstancePtr)->Config.BaseAddr, \
+ XSCUTIMER_ISR_OFFSET) & \
+ XSCUTIMER_ISR_EVENT_FLAG_MASK) == \
+ XSCUTIMER_ISR_EVENT_FLAG_MASK)
+
+/****************************************************************************/
+/**
+*
+* Re-start the timer. This macro will read the timer load register
+* and writes the same value to load register to update the counter register.
+*
+* @param InstancePtr is a pointer to the XScuTimer instance.
+*
+* @return None.
+*
+* @note C-style signature:
+* void XScuTimer_RestartTimer(XScuTimer *InstancePtr)
+*
+******************************************************************************/
+#define XScuTimer_RestartTimer(InstancePtr) \
+ XScuTimer_LoadTimer((InstancePtr), \
+ XScuTimer_ReadReg((InstancePtr)->Config.BaseAddr, \
+ XSCUTIMER_LOAD_OFFSET))
+
+/****************************************************************************/
+/**
+*
+* Write to the timer load register. This will also update the
+* timer counter register with the new value. This macro can be used to
+* change the time-out value.
+*
+* @param InstancePtr is a pointer to the XScuTimer instance.
+* @param Value is the count to be loaded in to the load register.
+*
+* @return None.
+*
+* @note C-style signature:
+* void XScuTimer_LoadTimer(XScuTimer *InstancePtr, u32 Value)
+*
+******************************************************************************/
+#define XScuTimer_LoadTimer(InstancePtr, Value) \
+ XScuTimer_WriteReg((InstancePtr)->Config.BaseAddr, \
+ XSCUTIMER_LOAD_OFFSET, (Value))
+
+/****************************************************************************/
+/**
+*
+* Returns the current timer counter register value. It can be called at any
+* time.
+*
+* @param InstancePtr is a pointer to the XScuTimer instance.
+*
+* @return Contents of the timer counter register.
+*
+* @note C-style signature:
+ u32 XScuTimer_GetCounterValue(XScuTimer *InstancePtr)
+*
+******************************************************************************/
+#define XScuTimer_GetCounterValue(InstancePtr) \
+ XScuTimer_ReadReg((InstancePtr)->Config.BaseAddr, \
+ XSCUTIMER_COUNTER_OFFSET)
+
+/****************************************************************************/
+/**
+*
+* Enable auto-reload mode.
+*
+* @param InstancePtr is a pointer to the XScuTimer instance.
+*
+* @return None.
+*
+* @note C-style signature:
+* void XScuTimer_EnableAutoReload(XScuTimer *InstancePtr)
+*
+******************************************************************************/
+#define XScuTimer_EnableAutoReload(InstancePtr) \
+ XScuTimer_WriteReg((InstancePtr)->Config.BaseAddr, \
+ XSCUTIMER_CONTROL_OFFSET, \
+ (XScuTimer_ReadReg((InstancePtr)->Config.BaseAddr, \
+ XSCUTIMER_CONTROL_OFFSET) | \
+ XSCUTIMER_CONTROL_AUTO_RELOAD_MASK))
+
+/****************************************************************************/
+/**
+*
+* Disable auto-reload mode.
+*
+* @param InstancePtr is a pointer to the XScuTimer instance.
+*
+* @return None.
+*
+* @note C-style signature:
+* void XScuTimer_DisableAutoReload(XScuTimer *InstancePtr)
+*
+******************************************************************************/
+#define XScuTimer_DisableAutoReload(InstancePtr) \
+ XScuTimer_WriteReg((InstancePtr)->Config.BaseAddr, \
+ XSCUTIMER_CONTROL_OFFSET, \
+ (XScuTimer_ReadReg((InstancePtr)->Config.BaseAddr, \
+ XSCUTIMER_CONTROL_OFFSET) & \
+ ~(XSCUTIMER_CONTROL_AUTO_RELOAD_MASK)))
+
+/****************************************************************************/
+/**
+*
+* Enable the Timer interrupt.
+*
+* @param InstancePtr is a pointer to the XScuTimer instance.
+*
+* @return None.
+*
+* @note C-style signature:
+* void XScuTimer_EnableInterrupt(XScuTimer *InstancePtr)
+*
+******************************************************************************/
+#define XScuTimer_EnableInterrupt(InstancePtr) \
+ XScuTimer_WriteReg((InstancePtr)->Config.BaseAddr, \
+ XSCUTIMER_CONTROL_OFFSET, \
+ (XScuTimer_ReadReg((InstancePtr)->Config.BaseAddr, \
+ XSCUTIMER_CONTROL_OFFSET) | \
+ XSCUTIMER_CONTROL_IRQ_ENABLE_MASK))
+
+/****************************************************************************/
+/**
+*
+* Disable the Timer interrupt.
+*
+* @param InstancePtr is a pointer to the XScuTimer instance.
+*
+* @return None.
+*
+* @note C-style signature:
+* void XScuTimer_DisableInterrupt(XScuTimer *InstancePtr)
+*
+******************************************************************************/
+#define XScuTimer_DisableInterrupt(InstancePtr) \
+ XScuTimer_WriteReg((InstancePtr)->Config.BaseAddr, \
+ XSCUTIMER_CONTROL_OFFSET, \
+ (XScuTimer_ReadReg((InstancePtr)->Config.BaseAddr, \
+ XSCUTIMER_CONTROL_OFFSET) & \
+ ~(XSCUTIMER_CONTROL_IRQ_ENABLE_MASK)))
+
+/*****************************************************************************/
+/**
+*
+* This function reads the interrupt status.
+*
+* @param InstancePtr is a pointer to the XScuTimer instance.
+*
+* @return None.
+*
+* @note C-style signature:
+* void XScuTimer_GetInterruptStatus(XScuTimer *InstancePtr)
+*
+******************************************************************************/
+#define XScuTimer_GetInterruptStatus(InstancePtr) \
+ XScuTimer_ReadReg((InstancePtr)->Config.BaseAddr, \
+ XSCUTIMER_ISR_OFFSET)
+
+/*****************************************************************************/
+/**
+*
+* This function clears the interrupt status.
+*
+* @param InstancePtr is a pointer to the XScuTimer instance.
+*
+* @return None.
+*
+* @note C-style signature:
+* void XScuTimer_ClearInterruptStatus(XScuTimer *InstancePtr)
+*
+******************************************************************************/
+#define XScuTimer_ClearInterruptStatus(InstancePtr) \
+ XScuTimer_WriteReg((InstancePtr)->Config.BaseAddr, \
+ XSCUTIMER_ISR_OFFSET, XSCUTIMER_ISR_EVENT_FLAG_MASK)
+
+/************************** Function Prototypes ******************************/
+
+/*
+ * Lookup configuration in xscutimer_sinit.c
+ */
+XScuTimer_Config *XScuTimer_LookupConfig(u16 DeviceId);
+
+/*
+ * Selftest function in xscutimer_selftest.c
+ */
+s32 XScuTimer_SelfTest(XScuTimer *InstancePtr);
+
+/*
+ * Interface functions in xscutimer.c
+ */
+s32 XScuTimer_CfgInitialize(XScuTimer *InstancePtr,
+ XScuTimer_Config *ConfigPtr, u32 EffectiveAddress);
+void XScuTimer_Start(XScuTimer *InstancePtr);
+void XScuTimer_Stop(XScuTimer *InstancePtr);
+void XScuTimer_SetPrescaler(XScuTimer *InstancePtr, u8 PrescalerValue);
+u8 XScuTimer_GetPrescaler(XScuTimer *InstancePtr);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* end of protection macro */
+/** @} */
diff --git a/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/scutimer_v2_1/src/xscutimer_g.c b/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/scutimer_v2_1/src/xscutimer_g.c
new file mode 100644
index 0000000..d384477
--- /dev/null
+++ b/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/scutimer_v2_1/src/xscutimer_g.c
@@ -0,0 +1,47 @@
+
+/*******************************************************************
+*
+* CAUTION: This file is automatically generated by HSI.
+* Version: 2019.2
+* DO NOT EDIT.
+*
+* Copyright (C) 2010-2021 Xilinx, Inc. All Rights Reserved.*
+*Permission is hereby granted, free of charge, to any person obtaining a copy
+*of this software and associated documentation files (the Software), to deal
+*in the Software without restriction, including without limitation the rights
+*to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+*copies of the Software, and to permit persons to whom the Software is
+*furnished to do so, subject to the following conditions:
+*
+*The above copyright notice and this permission notice shall be included in
+*all copies or substantial portions of the Software.
+*
+*THE SOFTWARE IS PROVIDED AS IS, WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+*IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+*FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+*THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+*WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT
+*OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+*
+
+*
+* Description: Driver configuration
+*
+*******************************************************************/
+
+#include "xparameters.h"
+#include "xscutimer.h"
+
+/*
+* The configuration table for devices
+*/
+
+XScuTimer_Config XScuTimer_ConfigTable[XPAR_XSCUTIMER_NUM_INSTANCES] =
+{
+ {
+ XPAR_PS7_SCUTIMER_0_DEVICE_ID,
+ XPAR_PS7_SCUTIMER_0_BASEADDR
+ }
+};
+
+
diff --git a/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/scutimer_v2_1/src/xscutimer_hw.h b/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/scutimer_v2_1/src/xscutimer_hw.h
new file mode 100644
index 0000000..a8b2302
--- /dev/null
+++ b/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/scutimer_v2_1/src/xscutimer_hw.h
@@ -0,0 +1,281 @@
+/******************************************************************************
+*
+* Copyright (C) 2010 - 2015 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+* THE SOFTWARE.
+*
+*
+*
+******************************************************************************/
+/****************************************************************************/
+/**
+*
+* @file xscutimer_hw.h
+* @addtogroup scutimer_v2_1
+* @{
+*
+* This file contains the hardware interface to the Timer.
+*
+* <pre>
+* MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ----- --- -------- ---------------------------------------------
+* 1.00a nm 03/10/10 First release
+* 1.01a sdm 02/02/12 Added low level macros to read/write load, counter, control
+* and interrupt registers
+* 1.02a sg 07/17/12 Included xil_assert.h for CR 667947. This is an issue
+* when the xstatus.h in the common driver overwrites
+* the xstatus.h of the standalone BSP during the
+* libgen.
+* 2.1 sk 02/26/15 Modified the code for MISRA-C:2012 compliance.
+* </pre>
+*
+******************************************************************************/
+#ifndef XSCUTIMER_HW_H /* prevent circular inclusions */
+#define XSCUTIMER_HW_H /* by using protection macros */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/***************************** Include Files *********************************/
+#include "xil_types.h"
+#include "xil_io.h"
+#include "xil_assert.h"
+/************************** Constant Definitions *****************************/
+
+/** @name Register Map
+ * Offsets of registers from the start of the device
+ * @{
+ */
+
+#define XSCUTIMER_LOAD_OFFSET 0x00U /**< Timer Load Register */
+#define XSCUTIMER_COUNTER_OFFSET 0x04U /**< Timer Counter Register */
+#define XSCUTIMER_CONTROL_OFFSET 0x08U /**< Timer Control Register */
+#define XSCUTIMER_ISR_OFFSET 0x0CU /**< Timer Interrupt
+ Status Register */
+/* @} */
+
+/** @name Timer Control register
+ * This register bits control the prescaler, Intr enable,
+ * auto-reload and timer enable.
+ * @{
+ */
+
+#define XSCUTIMER_CONTROL_PRESCALER_MASK 0x0000FF00U /**< Prescaler */
+#define XSCUTIMER_CONTROL_PRESCALER_SHIFT 8U
+#define XSCUTIMER_CONTROL_IRQ_ENABLE_MASK 0x00000004U /**< Intr enable */
+#define XSCUTIMER_CONTROL_AUTO_RELOAD_MASK 0x00000002U /**< Auto-reload */
+#define XSCUTIMER_CONTROL_ENABLE_MASK 0x00000001U /**< Timer enable */
+/* @} */
+
+/** @name Interrupt Status register
+ * This register indicates the Timer counter register has reached zero.
+ * @{
+ */
+
+#define XSCUTIMER_ISR_EVENT_FLAG_MASK 0x00000001U /**< Event flag */
+/*@}*/
+
+/**************************** Type Definitions *******************************/
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/****************************************************************************/
+/**
+*
+* Write to the timer load register. This will also update the
+* timer counter register with the new value. This macro can be used to
+* change the time-out value.
+*
+* @param BaseAddr is the base address of the scu timer.
+* @param Value is the count to be loaded in to the load register.
+*
+* @return None.
+*
+* @note C-style signature:
+* void XScuTimer_SetLoadReg(u32 BaseAddr, u32 Value)
+*
+******************************************************************************/
+#define XScuTimer_SetLoadReg(BaseAddr, Value) \
+ XScuTimer_WriteReg(BaseAddr, XSCUTIMER_LOAD_OFFSET, (Value))
+
+/****************************************************************************/
+/**
+*
+* Returns the current timer load register value.
+*
+* @param BaseAddr is the base address of the scu timer.
+*
+* @return Contents of the timer load register.
+*
+* @note C-style signature:
+* u32 XScuTimer_GetLoadReg(u32 BaseAddr)
+*
+******************************************************************************/
+#define XScuTimer_GetLoadReg(BaseAddr) \
+ XScuTimer_ReadReg(BaseAddr, XSCUTIMER_LOAD_OFFSET)
+
+/****************************************************************************/
+/**
+*
+* Write to the timer counter register.
+*
+* @param BaseAddr is the base address of the scu timer.
+* @param Value is the count to be loaded in to the counter register.
+*
+* @return None.
+*
+* @note C-style signature:
+* void XScuTimer_SetCounterReg(u32 BaseAddr, u32 Value)
+*
+******************************************************************************/
+#define XScuTimer_SetCounterReg(BaseAddr, Value) \
+ XScuTimer_WriteReg(BaseAddr, XSCUTIMER_COUNTER_OFFSET, (Value))
+
+/****************************************************************************/
+/**
+*
+* Returns the current timer counter register value.
+*
+* @param BaseAddr is the base address of the scu timer.
+*
+* @return Contents of the timer counter register.
+*
+* @note C-style signature:
+ u32 XScuTimer_GetCounterReg(u32 BaseAddr)
+*
+******************************************************************************/
+#define XScuTimer_GetCounterReg(BaseAddr) \
+ XScuTimer_ReadReg(BaseAddr, XSCUTIMER_COUNTER_OFFSET)
+
+/****************************************************************************/
+/**
+*
+* Write to the timer load register. This will also update the
+* timer counter register with the new value. This macro can be used to
+* change the time-out value.
+*
+* @param BaseAddr is the base address of the scu timer.
+* @param Value is the count to be loaded in to the load register.
+*
+* @return None.
+*
+* @note C-style signature:
+* void XScuTimer_SetControlReg(u32 BaseAddr, u32 Value)
+*
+******************************************************************************/
+#define XScuTimer_SetControlReg(BaseAddr, Value) \
+ XScuTimer_WriteReg(BaseAddr, XSCUTIMER_CONTROL_OFFSET, (Value))
+
+/****************************************************************************/
+/**
+*
+* Returns the current timer load register value.
+*
+* @param BaseAddr is the base address of the scu timer.
+*
+* @return Contents of the timer load register.
+*
+* @note C-style signature:
+ u32 XScuTimer_GetControlReg(u32 BaseAddr)
+*
+******************************************************************************/
+#define XScuTimer_GetControlReg(BaseAddr) \
+ XScuTimer_ReadReg(BaseAddr, XSCUTIMER_CONTROL_OFFSET)
+
+/****************************************************************************/
+/**
+*
+* Write to the timer counter register.
+*
+* @param BaseAddr is the base address of the scu timer.
+* @param Value is the count to be loaded in to the counter register.
+*
+* @return None.
+*
+* @note C-style signature:
+* void XScuTimer_SetIntrReg(u32 BaseAddr, u32 Value)
+*
+******************************************************************************/
+#define XScuTimer_SetIntrReg(BaseAddr, Value) \
+ XScuTimer_WriteReg(BaseAddr, XSCUTIMER_ISR_OFFSET, (Value))
+
+/****************************************************************************/
+/**
+*
+* Returns the current timer counter register value.
+*
+* @param BaseAddr is the base address of the scu timer.
+*
+* @return Contents of the timer counter register.
+*
+* @note C-style signature:
+ u32 XScuTimer_GetIntrReg(u32 BaseAddr)
+*
+******************************************************************************/
+#define XScuTimer_GetIntrReg(BaseAddr) \
+ XScuTimer_ReadReg(BaseAddr, XSCUTIMER_ISR_OFFSET)
+
+/****************************************************************************/
+/**
+*
+* Read from the given Timer register.
+*
+* @param BaseAddr is the base address of the device
+* @param RegOffset is the register offset to be read
+*
+* @return The 32-bit value of the register
+*
+* @note C-style signature:
+* u32 XScuTimer_ReadReg(u32 BaseAddr, u32 RegOffset)
+*
+*****************************************************************************/
+#define XScuTimer_ReadReg(BaseAddr, RegOffset) \
+ Xil_In32((BaseAddr) + (RegOffset))
+
+/****************************************************************************/
+/**
+*
+* Write to the given Timer register.
+*
+* @param BaseAddr is the base address of the device
+* @param RegOffset is the register offset to be written
+* @param Data is the 32-bit value to write to the register
+*
+* @return None.
+*
+* @note C-style signature:
+* void XScuTimer_WriteReg(u32 BaseAddr, u32 RegOffset, u32 Data)
+*
+*****************************************************************************/
+#define XScuTimer_WriteReg(BaseAddr, RegOffset, Data) \
+ Xil_Out32((BaseAddr) + (RegOffset), (Data))
+
+/************************** Function Prototypes ******************************/
+
+/************************** Variable Definitions *****************************/
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* end of protection macro */
+/** @} */
diff --git a/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/scutimer_v2_1/src/xscutimer_selftest.c b/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/scutimer_v2_1/src/xscutimer_selftest.c
new file mode 100644
index 0000000..482849d
--- /dev/null
+++ b/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/scutimer_v2_1/src/xscutimer_selftest.c
@@ -0,0 +1,133 @@
+/******************************************************************************
+*
+* Copyright (C) 2010 - 2015 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+* THE SOFTWARE.
+*
+*
+*
+******************************************************************************/
+/****************************************************************************/
+/**
+*
+* @file xscutimer_selftest.c
+* @addtogroup scutimer_v2_1
+* @{
+*
+* Contains diagnostic self-test functions for the XScuTimer driver.
+*
+* <pre>
+* MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ----- --- -------- ---------------------------------------------
+* 1.00a nm 03/10/10 First release
+* 2.1 sk 02/26/15 Modified the code for MISRA-C:2012 compliance.
+* </pre>
+*
+******************************************************************************/
+
+/***************************** Include Files *********************************/
+
+#include "xscutimer.h"
+
+/************************** Constant Definitions *****************************/
+
+#define XSCUTIMER_SELFTEST_VALUE 0xA55AF00FU
+
+/**************************** Type Definitions *******************************/
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/************************** Function Prototypes ******************************/
+
+/************************** Variable Definitions *****************************/
+
+/****************************************************************************/
+/**
+*
+* Run a self-test on the timer. This test clears the timer enable bit in
+* the control register, writes to the timer load register and verifies the
+* value read back matches the value written and restores the control register
+* and the timer load register.
+*
+* @param InstancePtr is a pointer to the XScuTimer instance.
+*
+* @return
+* - XST_SUCCESS if self-test was successful.
+* - XST_FAILURE if self test was not successful.
+*
+* @note None.
+*
+******************************************************************************/
+s32 XScuTimer_SelfTest(XScuTimer *InstancePtr)
+{
+ u32 Register;
+ u32 CtrlOrig;
+ u32 LoadOrig;
+ s32 Status;
+
+ /*
+ * Assert to ensure the inputs are valid and the instance has been
+ * initialized.
+ */
+ Xil_AssertNonvoid(InstancePtr != NULL);
+ Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+ /*
+ * Save the contents of the Control Register and stop the timer.
+ */
+ CtrlOrig = XScuTimer_ReadReg(InstancePtr->Config.BaseAddr,
+ XSCUTIMER_CONTROL_OFFSET);
+ Register = CtrlOrig & (u32)(~XSCUTIMER_CONTROL_ENABLE_MASK);
+ XScuTimer_WriteReg(InstancePtr->Config.BaseAddr,
+ XSCUTIMER_CONTROL_OFFSET, Register);
+
+ /*
+ * Save the contents of the Load Register.
+ * Load a new test value in the Load Register, read it back and
+ * compare it with the written value.
+ */
+ LoadOrig = XScuTimer_ReadReg((InstancePtr)->Config.BaseAddr,
+ XSCUTIMER_LOAD_OFFSET);
+ XScuTimer_LoadTimer(InstancePtr, XSCUTIMER_SELFTEST_VALUE);
+ Register = XScuTimer_ReadReg((InstancePtr)->Config.BaseAddr,
+ XSCUTIMER_LOAD_OFFSET);
+
+ /*
+ * Restore the contents of the Load Register and Control Register.
+ */
+ XScuTimer_LoadTimer(InstancePtr, LoadOrig);
+ XScuTimer_WriteReg(InstancePtr->Config.BaseAddr,
+ XSCUTIMER_CONTROL_OFFSET, CtrlOrig);
+
+ /*
+ * Return a Failure if the contents of the Load Register do not
+ * match with the value written to it.
+ */
+ if (Register != XSCUTIMER_SELFTEST_VALUE) {
+ Status = (s32)XST_FAILURE;
+ }
+ else {
+ Status = (s32)XST_SUCCESS;
+ }
+
+ return Status;
+}
+/** @} */
diff --git a/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/scutimer_v2_1/src/xscutimer_sinit.c b/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/scutimer_v2_1/src/xscutimer_sinit.c
new file mode 100644
index 0000000..fca3ada
--- /dev/null
+++ b/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/scutimer_v2_1/src/xscutimer_sinit.c
@@ -0,0 +1,90 @@
+/******************************************************************************
+*
+* Copyright (C) 2010 - 2015 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+* THE SOFTWARE.
+*
+*
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xscutimer_sinit.c
+* @addtogroup scutimer_v2_1
+* @{
+*
+* This file contains method for static initialization (compile-time) of the
+* driver.
+*
+* <pre>
+* MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ----- --- -------- ---------------------------------------------
+* 1.00a nm 03/10/10 First release
+* 2.1 sk 02/26/15 Modified the code for MISRA-C:2012 compliance.
+* </pre>
+*
+******************************************************************************/
+
+/***************************** Include Files *********************************/
+
+#include "xscutimer.h"
+#include "xparameters.h"
+
+/************************** Constant Definitions *****************************/
+
+/**************************** Type Definitions *******************************/
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/************************** Variable Definitions ****************************/
+extern XScuTimer_Config XScuTimer_ConfigTable[XPAR_XSCUTIMER_NUM_INSTANCES];
+
+/************************** Function Prototypes ******************************/
+
+/*****************************************************************************/
+/**
+* Lookup the device configuration based on the unique device ID. The table
+* contains the configuration info for each device in the system.
+*
+* @param DeviceId is the unique device ID of the device being looked up.
+*
+* @return A pointer to the configuration table entry corresponding to the
+* given device ID, or NULL if no match is found.
+*
+* @note None.
+*
+******************************************************************************/
+XScuTimer_Config *XScuTimer_LookupConfig(u16 DeviceId)
+{
+ XScuTimer_Config *CfgPtr = NULL;
+ u32 Index;
+
+ for (Index = 0U; Index < XPAR_XSCUTIMER_NUM_INSTANCES; Index++) {
+ if (XScuTimer_ConfigTable[Index].DeviceId == DeviceId) {
+ CfgPtr = &XScuTimer_ConfigTable[Index];
+ break;
+ }
+ }
+
+ return (XScuTimer_Config *)CfgPtr;
+}
+/** @} */
diff --git a/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/scuwdt_v2_1/src/Makefile b/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/scuwdt_v2_1/src/Makefile
new file mode 100644
index 0000000..493ad9a
--- /dev/null
+++ b/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/scuwdt_v2_1/src/Makefile
@@ -0,0 +1,40 @@
+COMPILER=
+ARCHIVER=
+CP=cp
+COMPILER_FLAGS=
+EXTRA_COMPILER_FLAGS=
+LIB=libxil.a
+
+CC_FLAGS = $(COMPILER_FLAGS)
+ECC_FLAGS = $(EXTRA_COMPILER_FLAGS)
+
+RELEASEDIR=../../../lib
+INCLUDEDIR=../../../include
+INCLUDES=-I./. -I${INCLUDEDIR}
+
+OUTS = *.o
+
+LIBSOURCES:=*.c
+INCLUDEFILES:=*.h
+
+OBJECTS = $(addsuffix .o, $(basename $(wildcard *.c)))
+
+libs: banner scuwdt_libs clean
+
+%.o: %.c
+ ${COMPILER} $(CC_FLAGS) $(ECC_FLAGS) $(INCLUDES) -o $@ $<
+
+banner:
+ echo "Compiling scuwdt"
+
+scuwdt_libs: ${OBJECTS}
+ $(ARCHIVER) -r ${RELEASEDIR}/${LIB} ${OBJECTS}
+
+.PHONY: include
+include: scuwdt_includes
+
+scuwdt_includes:
+ ${CP} ${INCLUDEFILES} ${INCLUDEDIR}
+
+clean:
+ rm -rf ${OBJECTS}
diff --git a/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/scuwdt_v2_1/src/xscuwdt.c b/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/scuwdt_v2_1/src/xscuwdt.c
new file mode 100644
index 0000000..ca066f9
--- /dev/null
+++ b/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/scuwdt_v2_1/src/xscuwdt.c
@@ -0,0 +1,211 @@
+/******************************************************************************
+*
+* Copyright (C) 2010 - 2015 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+* THE SOFTWARE.
+*
+*
+*
+******************************************************************************/
+/****************************************************************************/
+/**
+*
+* @file xscuwdt.c
+* @addtogroup scuwdt_v2_1
+* @{
+*
+* Contains the implementation of interface functions of the XScuWdt driver.
+* See xscuwdt.h for a description of the driver.
+*
+* <pre>
+* MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ----- --- -------- ---------------------------------------------
+* 1.00a sdm 01/15/10 First release
+* 2.1 sk 02/26/15 Modified the code for MISRA-C:2012 compliance.
+* </pre>
+*
+******************************************************************************/
+
+/***************************** Include Files *********************************/
+
+#include "xscuwdt.h"
+
+/************************** Constant Definitions *****************************/
+
+/**************************** Type Definitions *******************************/
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/************************** Function Prototypes ******************************/
+
+/************************** Variable Definitions *****************************/
+
+/****************************************************************************/
+/**
+*
+* Initialize a specific watchdog timer instance/driver. This function
+* must be called before other functions of the driver are called.
+*
+* @param InstancePtr is a pointer to the XScuWdt instance.
+* @param ConfigPtr is the config structure.
+* @param EffectiveAddress is the base address for the device. It could be
+* a virtual address if address translation is supported in the
+* system, otherwise it is the physical address.
+*
+* @return
+* - XST_SUCCESS if initialization was successful.
+* - XST_DEVICE_IS_STARTED if the device has already been started.
+*
+* @note This function enables the watchdog mode.
+*
+******************************************************************************/
+s32 XScuWdt_CfgInitialize(XScuWdt *InstancePtr,
+ XScuWdt_Config *ConfigPtr, u32 EffectiveAddress)
+{
+ s32 CfgStatus;
+ Xil_AssertNonvoid(InstancePtr != NULL);
+ Xil_AssertNonvoid(ConfigPtr != NULL);
+ Xil_AssertNonvoid(EffectiveAddress != 0x00U);
+
+ /*
+ * If the device is started, disallow the initialize and return a
+ * status indicating it is started. This allows the user to stop the
+ * device and reinitialize, but prevents a user from inadvertently
+ * initializing.
+ */
+ if (InstancePtr->IsStarted == XIL_COMPONENT_IS_STARTED) {
+ CfgStatus = (s32)XST_DEVICE_IS_STARTED;
+ }
+ else {
+ /*
+ * Copy configuration into instance.
+ */
+ InstancePtr->Config.DeviceId = ConfigPtr->DeviceId;
+
+ /*
+ * Save the base address pointer such that the registers of the block
+ * can be accessed and indicate it has not been started yet.
+ */
+ InstancePtr->Config.BaseAddr = EffectiveAddress;
+ InstancePtr->IsStarted = 0U;
+
+ /*
+ * Put the watchdog timer in Watchdog mode.
+ */
+ XScuWdt_SetWdMode(InstancePtr);
+
+ /*
+ * Indicate the instance is ready to use, successfully initialized.
+ */
+ InstancePtr->IsReady = XIL_COMPONENT_IS_READY;
+
+ CfgStatus =(s32)XST_SUCCESS;
+ }
+ return CfgStatus;
+}
+
+/****************************************************************************/
+/**
+*
+* Start the watchdog counter of the device.
+*
+* @param InstancePtr is a pointer to the XScuWdt instance.
+*
+* @return None.
+*
+* @note User needs to select the appropriate mode (watchdog/timer)
+* before using this API.
+* See XScuWdt_SetWdMode/XScuWdt_SetTimerMode macros in
+* xscuwdt.h.
+*
+******************************************************************************/
+void XScuWdt_Start(XScuWdt *InstancePtr)
+{
+ u32 Register;
+
+ Xil_AssertVoid(InstancePtr != NULL);
+ Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+ /*
+ * Read the contents of the Control register.
+ */
+ Register = XScuWdt_ReadReg(InstancePtr->Config.BaseAddr,
+ XSCUWDT_CONTROL_OFFSET);
+
+ /*
+ * Set the 'watchdog enable' bit in the register.
+ */
+ Register |= XSCUWDT_CONTROL_WD_ENABLE_MASK;
+
+ /*
+ * Update the Control register with the new value.
+ */
+ XScuWdt_WriteReg(InstancePtr->Config.BaseAddr,
+ XSCUWDT_CONTROL_OFFSET, Register);
+
+ /*
+ * Indicate that the device is started.
+ */
+ InstancePtr->IsStarted = XIL_COMPONENT_IS_STARTED;
+}
+
+/****************************************************************************/
+/**
+*
+* Stop the watchdog timer.
+*
+* @param InstancePtr is a pointer to the XScuWdt instance.
+*
+* @return None.
+*
+* @note None.
+*
+******************************************************************************/
+void XScuWdt_Stop(XScuWdt *InstancePtr)
+{
+ u32 Register;
+
+ Xil_AssertVoid(InstancePtr != NULL);
+ Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+ /*
+ * Read the contents of the Control register.
+ */
+ Register = XScuWdt_ReadReg(InstancePtr->Config.BaseAddr,
+ XSCUWDT_CONTROL_OFFSET);
+
+ /*
+ * Clear the 'watchdog enable' bit in the register.
+ */
+ Register &= (u32)(~XSCUWDT_CONTROL_WD_ENABLE_MASK);
+
+ /*
+ * Update the Control register with the new value.
+ */
+ XScuWdt_WriteReg(InstancePtr->Config.BaseAddr,
+ XSCUWDT_CONTROL_OFFSET, Register);
+
+ /*
+ * Indicate that the device is stopped.
+ */
+ InstancePtr->IsStarted = 0U;
+}
+/** @} */
diff --git a/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/scuwdt_v2_1/src/xscuwdt.h b/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/scuwdt_v2_1/src/xscuwdt.h
new file mode 100644
index 0000000..61a73dd
--- /dev/null
+++ b/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/scuwdt_v2_1/src/xscuwdt.h
@@ -0,0 +1,377 @@
+/******************************************************************************
+*
+* Copyright (C) 2010 - 2015 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+* THE SOFTWARE.
+*
+*
+*
+******************************************************************************/
+/****************************************************************************/
+/**
+*
+* @file xscuwdt.h
+* @addtogroup scuwdt_v2_1
+* @{
+* @details
+*
+* The Xilinx SCU watchdog timer driver (XScuWdt) supports the Xilinx SCU private
+* watchdog timer hardware.
+*
+* The XScuWdt driver supports the following features:
+* - Watchdog mode
+* - Timer mode
+* - Auto reload (timer mode only)
+*
+* The watchdog counter register is a down counter and starts decrementing when
+* the watchdog is started.
+* In watchdog mode, when the counter reaches 0, the Reset flag is set in the
+* Reset status register and the WDRESETREQ pin is asserted, causing a system
+* reset. The Reset flag is not reset by normal processor reset and is cleared
+* when written with a value of 1. This enables the user to differentiate a
+* normal reset and a reset caused by watchdog time-out. The user needs to call
+* XScuWdt_RestartWdt() periodically, to avoid the watchdog from being timed-out.
+*
+* The IsWdtExpired function can be used to check if the watchdog was the cause
+* of the last reset. In this situation, call Initialize then call IsWdtExpired.
+* If the result is true, watchdog timeout caused the last system reset. The
+* application then needs to clear the Reset flag.
+*
+* In timer mode, when the counter reaches 0, the Event flag is set in the
+* Interrupt status register and if interrupts are enabled, interrupt ID 30 is
+* set as pending in the interrupt distributor. The IsTimerExpired function
+* is used to check if the watchdog counter has decremented to 0 in timer mode.
+* If auto-reload mode is enabled, the Counter register is automatically reloaded
+* from the Load register.
+*
+* <b> Initialization and Configuration </b>
+*
+* The device driver enables higher layer software (e.g., an application) to
+* communicate with the Watchdog Timer.
+*
+* XScuWdt_CfgInitialize() API is used to initialize the Watchdog Timer. The
+* user needs to first call the XScuWdt_LookupConfig() API which returns
+* the Configuration structure pointer which is passed as a parameter to
+* the XScuWdt_CfgInitialize() API.
+*
+* <b>Interrupts</b>
+*
+* The SCU Watchdog Timer supports interrupts in Timer mode.
+*
+* This driver does not provide a Interrupt Service Routine (ISR) for the device.
+* It is the responsibility of the application to provide one if needed. Refer to
+* the interrupt example provided with this driver for details on using the
+* Timer in interrupt mode.
+*
+* <b> Virtual Memory </b>
+*
+* This driver supports Virtual Memory. The RTOS is responsible for calculating
+* the correct device base address in Virtual Memory space.
+*
+* <b> Threads </b>
+*
+* This driver is not thread safe. Any needs for threads or thread mutual
+* exclusion must be satisfied by the layer above this driver.
+*
+* <b> Asserts </b>
+*
+* Asserts are used within all Xilinx drivers to enforce constraints on argument
+* values. Asserts can be turned off on a system-wide basis by defining, at
+* compile time, the NDEBUG identifier. By default, asserts are turned on and it
+* is recommended that users leave asserts on during development.
+*
+* <b> Building the driver </b>
+*
+* The XScuWdt driver is composed of several source files. This allows the user
+* to build and link only those parts of the driver that are necessary.
+*
+* <br><br>
+*
+* NOTE:
+* The watchdog timer is not a part of the snoop control unit as indicated
+* by the prefix "scu" in the name of the driver.
+* It is an independent module in APU.
+*
+* <pre>
+* MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ----- --- -------- ---------------------------------------------
+* 1.00a sdm 01/15/10 First release
+* 1.02a sg 07/17/12 Included xil_assert.h for CR 667947. This is an issue
+* when the xstatus.h in the common driver overwrites
+* the xstatus.h of the standalone BSP during the
+* libgen.
+* 2.1 sk 02/26/15 Modified the code for MISRA-C:2012 compliance.
+* ms 03/17/17 Added readme.txt file in examples folder for doxygen
+* generation.
+* </pre>
+*
+******************************************************************************/
+#ifndef XSCUWDT_H /* prevent circular inclusions */
+#define XSCUWDT_H /* by using protection macros */
+
+/***************************** Include Files *********************************/
+
+#include "xstatus.h"
+#include "xscuwdt_hw.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/************************** Constant Definitions *****************************/
+
+/**************************** Type Definitions *******************************/
+
+/**
+ * This typedef contains configuration information for the device.
+ */
+typedef struct {
+ u16 DeviceId; /**< Unique ID of device */
+ u32 BaseAddr; /**< Base address of the device */
+} XScuWdt_Config;
+
+/**
+ * The XScuWdt driver instance data. The user is required to allocate a
+ * variable of this type for every watchdog/timer device in the system.
+ * A pointer to a variable of this type is then passed to the driver API
+ * functions.
+ */
+typedef struct {
+ XScuWdt_Config Config;/**< Hardware Configuration */
+ u32 IsReady; /**< Device is initialized and ready */
+ u32 IsStarted; /**< Device watchdog timer is running */
+} XScuWdt;
+
+/***************** Macros (Inline Functions) Definitions *********************/
+/****************************************************************************/
+/**
+*
+* This function is used to check if the watchdog has timed-out and the last
+* reset was caused by the watchdog reset.
+*
+* @param InstancePtr is a pointer to the XScuWdt instance.
+*
+* @return
+* - TRUE if the watchdog has expired.
+* - FALSE if the watchdog has not expired.
+*
+* @note C-style signature:
+* int XScuWdt_IsWdtExpired(XScuWdt *InstancePtr)
+*
+******************************************************************************/
+#define XScuWdt_IsWdtExpired(InstancePtr) \
+ ((XScuWdt_ReadReg((InstancePtr)->Config.BaseAddr, \
+ XSCUWDT_RST_STS_OFFSET) & \
+ XSCUWDT_RST_STS_RESET_FLAG_MASK) == XSCUWDT_RST_STS_RESET_FLAG_MASK)
+
+/****************************************************************************/
+/**
+*
+* This function is used to check if the watchdog counter has reached 0 in timer
+* mode.
+*
+* @param InstancePtr is a pointer to the XScuWdt instance.
+*
+* @return
+* - TRUE if the watchdog has expired.
+* - FALSE if the watchdog has not expired.
+*
+* @note C-style signature:
+* int XScuWdt_IsTimerExpired(XScuWdt *InstancePtr)
+*
+******************************************************************************/
+#define XScuWdt_IsTimerExpired(InstancePtr) \
+ ((XScuWdt_ReadReg((InstancePtr)->Config.BaseAddr, \
+ XSCUWDT_ISR_OFFSET) & \
+ XSCUWDT_ISR_EVENT_FLAG_MASK) == XSCUWDT_ISR_EVENT_FLAG_MASK)
+
+/****************************************************************************/
+/**
+*
+* Re-start the watchdog timer. This macro will read the watchdog load register
+* and write the same value to load register to update the counter register.
+* An application needs to call this function periodically to keep the watchdog
+* from asserting the WDRESETREQ reset request output pin.
+*
+* @param InstancePtr is a pointer to the XScuWdt instance.
+*
+* @return None.
+*
+* @note C-style signature:
+* void XScuWdt_RestartWdt(XScuWdt *InstancePtr)
+*
+******************************************************************************/
+#define XScuWdt_RestartWdt(InstancePtr) \
+ XScuWdt_LoadWdt((InstancePtr), \
+ (XScuWdt_ReadReg((InstancePtr)->Config.BaseAddr, \
+ XSCUWDT_LOAD_OFFSET)))
+
+/****************************************************************************/
+/**
+*
+* Write to the watchdog timer load register. This will also update the
+* watchdog counter register with the new value. This macro can be used to
+* change the time-out value.
+*
+* @param InstancePtr is a pointer to the XScuWdt instance.
+* @param Value is the value to be written to the Watchdog Load register.
+*
+* @return None.
+*
+* @note C-style signature:
+* void XScuWdt_LoadWdt(XScuWdt *InstancePtr, u32 Value)
+*
+******************************************************************************/
+#define XScuWdt_LoadWdt(InstancePtr, Value) \
+ XScuWdt_WriteReg((InstancePtr)->Config.BaseAddr, \
+ XSCUWDT_LOAD_OFFSET, (Value))
+
+/****************************************************************************/
+/**
+*
+* Put the watchdog timer in Watchdog mode by setting the WD mode bit of the
+* Watchdog control register.
+*
+* @param InstancePtr is a pointer to the XScuWdt instance.
+*
+* @return None.
+*
+* @note C-style signature:
+* void XScuWdt_SetWdMode(XScuWdt *InstancePtr)
+*
+******************************************************************************/
+#define XScuWdt_SetWdMode(InstancePtr) \
+ XScuWdt_WriteReg((InstancePtr)->Config.BaseAddr, \
+ XSCUWDT_CONTROL_OFFSET, \
+ (XScuWdt_ReadReg((InstancePtr)->Config.BaseAddr, \
+ XSCUWDT_CONTROL_OFFSET) | \
+ (XSCUWDT_CONTROL_WD_MODE_MASK)))
+
+/****************************************************************************/
+/**
+*
+* Put the watchdog timer in Timer mode by writing 0x12345678 and 0x87654321
+* successively to the Watchdog Disable Register.
+* The software must write 0x12345678 and 0x87654321 successively to the
+* Watchdog Disable Register so that the watchdog mode bit in the Watchdog
+* Control Register is set to zero.
+*
+* @param InstancePtr is a pointer to the XScuWdt instance.
+*
+* @return None.
+*
+* @note C-style signature:
+* void XScuWdt_SetTimerMode(XScuWdt *InstancePtr)
+*
+******************************************************************************/
+#define XScuWdt_SetTimerMode(InstancePtr) \
+{ \
+ XScuWdt_WriteReg((InstancePtr)->Config.BaseAddr, \
+ XSCUWDT_DISABLE_OFFSET, \
+ XSCUWDT_DISABLE_VALUE1); \
+ XScuWdt_WriteReg((InstancePtr)->Config.BaseAddr, \
+ XSCUWDT_DISABLE_OFFSET, \
+ XSCUWDT_DISABLE_VALUE2); \
+}
+
+/****************************************************************************/
+/**
+*
+* Get the contents of the watchdog control register.
+*
+* @param InstancePtr is a pointer to the XScuWdt instance.
+*
+* @return Contents of the watchdog control register.
+*
+* @note C-style signature:
+ u32 XScuWdt_GetControlReg(XScuWdt *InstancePtr)
+*
+******************************************************************************/
+#define XScuWdt_GetControlReg(InstancePtr) \
+ XScuWdt_ReadReg((InstancePtr)->Config.BaseAddr, \
+ XSCUWDT_CONTROL_OFFSET)
+
+/****************************************************************************/
+/**
+*
+* Write to the watchdog control register.
+*
+* @param InstancePtr is a pointer to the XScuWdt instance.
+* @param ControlReg is the value to be written to the watchdog control
+* register.
+*
+* @return None.
+*
+* @note C-style signature:
+ void XScuWdt_SetControlReg(XScuWdt *InstancePtr, u32 ControlReg)
+*
+******************************************************************************/
+#define XScuWdt_SetControlReg(InstancePtr, ControlReg) \
+ XScuWdt_WriteReg((InstancePtr)->Config.BaseAddr, \
+ XSCUWDT_CONTROL_OFFSET, (ControlReg))
+
+/****************************************************************************/
+/**
+*
+* Enable auto-reload mode.
+*
+* @param InstancePtr is a pointer to the XScuWdt instance.
+*
+* @return None.
+*
+* @note C-style signature:
+* void XScuWdt_EnableAutoReload(XScuWdt *InstancePtr)
+*
+******************************************************************************/
+#define XScuWdt_EnableAutoReload(InstancePtr) \
+ XScuWdt_SetControlReg((InstancePtr), \
+ (XScuWdt_GetControlReg(InstancePtr) | \
+ XSCUWDT_CONTROL_AUTO_RELOAD_MASK))
+
+/************************** Function Prototypes ******************************/
+
+/*
+ * Lookup configuration in xscuwdt_sinit.c.
+ */
+XScuWdt_Config *XScuWdt_LookupConfig(u16 DeviceId);
+
+/*
+ * Selftest function in xscuwdt_selftest.c
+ */
+s32 XScuWdt_SelfTest(XScuWdt *InstancePtr);
+
+/*
+ * Interface functions in xscuwdt.c
+ */
+s32 XScuWdt_CfgInitialize(XScuWdt *InstancePtr,
+ XScuWdt_Config *ConfigPtr, u32 EffectiveAddress);
+
+void XScuWdt_Start(XScuWdt *InstancePtr);
+
+void XScuWdt_Stop(XScuWdt *InstancePtr);
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* end of protection macro */
+/** @} */
diff --git a/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/scuwdt_v2_1/src/xscuwdt_g.c b/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/scuwdt_v2_1/src/xscuwdt_g.c
new file mode 100644
index 0000000..3e4258f
--- /dev/null
+++ b/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/scuwdt_v2_1/src/xscuwdt_g.c
@@ -0,0 +1,47 @@
+
+/*******************************************************************
+*
+* CAUTION: This file is automatically generated by HSI.
+* Version: 2019.2
+* DO NOT EDIT.
+*
+* Copyright (C) 2010-2021 Xilinx, Inc. All Rights Reserved.*
+*Permission is hereby granted, free of charge, to any person obtaining a copy
+*of this software and associated documentation files (the Software), to deal
+*in the Software without restriction, including without limitation the rights
+*to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+*copies of the Software, and to permit persons to whom the Software is
+*furnished to do so, subject to the following conditions:
+*
+*The above copyright notice and this permission notice shall be included in
+*all copies or substantial portions of the Software.
+*
+*THE SOFTWARE IS PROVIDED AS IS, WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+*IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+*FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+*THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+*WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT
+*OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+*
+
+*
+* Description: Driver configuration
+*
+*******************************************************************/
+
+#include "xparameters.h"
+#include "xscuwdt.h"
+
+/*
+* The configuration table for devices
+*/
+
+XScuWdt_Config XScuWdt_ConfigTable[XPAR_XSCUWDT_NUM_INSTANCES] =
+{
+ {
+ XPAR_PS7_SCUWDT_0_DEVICE_ID,
+ XPAR_PS7_SCUWDT_0_BASEADDR
+ }
+};
+
+
diff --git a/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/scuwdt_v2_1/src/xscuwdt_hw.h b/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/scuwdt_v2_1/src/xscuwdt_hw.h
new file mode 100644
index 0000000..efe0a3a
--- /dev/null
+++ b/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/scuwdt_v2_1/src/xscuwdt_hw.h
@@ -0,0 +1,176 @@
+/******************************************************************************
+*
+* Copyright (C) 2010 - 2015 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+* THE SOFTWARE.
+*
+*
+*
+******************************************************************************/
+/****************************************************************************/
+/**
+*
+* @file xscuwdt_hw.h
+* @addtogroup scuwdt_v2_1
+* @{
+*
+* This file contains the hardware interface to the Xilinx SCU private Watch Dog
+* Timer (XSCUWDT).
+*
+* <pre>
+* MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ----- --- -------- ---------------------------------------------
+* 1.00a sdm 01/15/10 First release
+* 1.01a bss 02/27/12 Updated the register offsets to start at 0x0 instead
+* of 0x20 as the base address obtained from the tools
+* starts at 0x20.
+* 1.02a sg 07/17/12 Included xil_assert.h for CR 667947. This is an issue
+* when the xstatus.h in the common driver overwrites
+* the xstatus.h of the standalone BSP during the
+* libgen.
+* 2.1 sk 02/26/15 Modified the code for MISRA-C:2012 compliance.
+* </pre>
+*
+******************************************************************************/
+#ifndef XSCUWDT_HW_H /* prevent circular inclusions */
+#define XSCUWDT_HW_H /* by using protection macros */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/***************************** Include Files *********************************/
+
+#include "xil_types.h"
+#include "xil_io.h"
+#include "xil_assert.h"
+/************************** Constant Definitions *****************************/
+
+/** @name Register Map
+ * Offsets of registers from the start of the device. The WDT registers start at
+ * an offset 0x20
+ * @{
+ */
+
+#define XSCUWDT_LOAD_OFFSET 0x00U /**< Watchdog Load Register */
+#define XSCUWDT_COUNTER_OFFSET 0x04U /**< Watchdog Counter Register */
+#define XSCUWDT_CONTROL_OFFSET 0x08U /**< Watchdog Control Register */
+#define XSCUWDT_ISR_OFFSET 0x0CU /**< Watchdog Interrupt Status Register */
+#define XSCUWDT_RST_STS_OFFSET 0x10U /**< Watchdog Reset Status Register */
+#define XSCUWDT_DISABLE_OFFSET 0x14U /**< Watchdog Disable Register */
+/* @} */
+
+/** @name Watchdog Control register
+ * This register bits control the prescaler, WD/Timer mode, Intr enable,
+ * auto-reload, watchdog enable.
+ * @{
+ */
+
+#define XSCUWDT_CONTROL_PRESCALER_MASK 0x0000FF00U /**< Prescaler */
+#define XSCUWDT_CONTROL_PRESCALER_SHIFT 8U
+#define XSCUWDT_CONTROL_WD_MODE_MASK 0x00000008U /**< Watchdog/Timer mode */
+#define XSCUWDT_CONTROL_IT_ENABLE_MASK 0x00000004U /**< Intr enable (in
+ timer mode) */
+#define XSCUWDT_CONTROL_AUTO_RELOAD_MASK 0x00000002U /**< Auto-reload (in
+ timer mode) */
+#define XSCUWDT_CONTROL_WD_ENABLE_MASK 0x00000001U /**< Watchdog enable */
+/* @} */
+
+/** @name Interrupt Status register
+ * This register indicates the Counter register has reached zero in Counter
+ * mode.
+ * @{
+ */
+
+#define XSCUWDT_ISR_EVENT_FLAG_MASK 0x00000001U /**< Event flag */
+/*@}*/
+
+/** @name Reset Status register
+ * This register indicates the Counter register has reached zero in Watchdog
+ * mode and a reset request is sent.
+ * @{
+ */
+
+#define XSCUWDT_RST_STS_RESET_FLAG_MASK 0x00000001U /**< Time out occurred */
+/*@}*/
+
+/** @name Disable register
+ * This register is used to switch from watchdog mode to timer mode.
+ * The software must write 0x12345678 and 0x87654321 successively to the
+ * Watchdog Disable Register so that the watchdog mode bit in the Watchdog
+ * Control Register is set to zero.
+ * @{
+ */
+#define XSCUWDT_DISABLE_VALUE1 0x12345678U /**< Watchdog mode disable
+ value 1 */
+#define XSCUWDT_DISABLE_VALUE2 0x87654321U /**< Watchdog mode disable
+ value 2 */
+/*@}*/
+
+/**************************** Type Definitions *******************************/
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/****************************************************************************/
+/**
+*
+* Read the given register.
+*
+* @param BaseAddr is the base address of the device
+* @param RegOffset is the register offset to be read
+*
+* @return The 32-bit value of the register
+*
+* @note C-style signature:
+* u32 XScuWdt_ReadReg(u32 BaseAddr, u32 RegOffset)
+*
+*****************************************************************************/
+#define XScuWdt_ReadReg(BaseAddr, RegOffset) \
+ Xil_In32((BaseAddr) + ((u32)RegOffset))
+
+/****************************************************************************/
+/**
+*
+* Write the given register.
+*
+* @param BaseAddr is the base address of the device
+* @param RegOffset is the register offset to be written
+* @param Data is the 32-bit value to write to the register
+*
+* @return None.
+*
+* @note C-style signature:
+* void XScuWdt_WriteReg(u32 BaseAddr, u32 RegOffset, u32 Data)
+*
+*****************************************************************************/
+#define XScuWdt_WriteReg(BaseAddr, RegOffset, Data) \
+ Xil_Out32((BaseAddr) + ((u32)RegOffset), ((u32)Data))
+
+/************************** Function Prototypes ******************************/
+
+/************************** Variable Definitions *****************************/
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* end of protection macro */
+/** @} */
diff --git a/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/scuwdt_v2_1/src/xscuwdt_selftest.c b/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/scuwdt_v2_1/src/xscuwdt_selftest.c
new file mode 100644
index 0000000..b8c054e
--- /dev/null
+++ b/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/scuwdt_v2_1/src/xscuwdt_selftest.c
@@ -0,0 +1,125 @@
+/******************************************************************************
+*
+* Copyright (C) 2010 - 2015 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+* THE SOFTWARE.
+*
+*
+*
+******************************************************************************/
+/****************************************************************************/
+/**
+*
+* @file xscuwdt_selftest.c
+* @addtogroup scuwdt_v2_1
+* @{
+*
+* Contains diagnostic self-test functions for the XScuWdt driver.
+*
+* <pre>
+* MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ----- --- -------- ---------------------------------------------
+* 1.00a sdm 01/15/10 First release
+* 2.1 sk 02/26/15 Modified the code for MISRA-C:2012 compliance.
+* </pre>
+*
+******************************************************************************/
+
+/***************************** Include Files *********************************/
+
+#include "xscuwdt.h"
+
+/************************** Constant Definitions *****************************/
+
+/**************************** Type Definitions *******************************/
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/************************** Function Prototypes ******************************/
+
+/************************** Variable Definitions *****************************/
+
+/****************************************************************************/
+/**
+*
+* Run a self-test on the WDT. This test stops the watchdog, writes a value to
+* the watchdog load register, starts the watchdog and verifies that the value
+* read from the counter register is less that the value written to the load
+* register. It then restores the control register and the watchdog load
+* register.
+*
+* @param InstancePtr is a pointer to the XScuWdt instance.
+*
+* @return
+* - XST_SUCCESS if self-test was successful.
+* - XST_FAILURE if the WDT is not decrementing.
+*
+* @note None.
+*
+******************************************************************************/
+s32 XScuWdt_SelfTest(XScuWdt *InstancePtr)
+{
+ s32 SelfTestStatus;
+ u32 Register;
+ u32 CtrlOrig;
+ u32 LoadOrig;
+
+ /*
+ * Assert to ensure the inputs are valid and the instance has been
+ * initialized.
+ */
+ Xil_AssertNonvoid(InstancePtr != NULL);
+ Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+ /*
+ * Stop the watchdog timer.
+ */
+ CtrlOrig = XScuWdt_GetControlReg(InstancePtr);
+ XScuWdt_SetControlReg(InstancePtr,
+ CtrlOrig & (u32)(~XSCUWDT_CONTROL_WD_ENABLE_MASK));
+
+ LoadOrig = XScuWdt_ReadReg((InstancePtr)->Config.BaseAddr,
+ XSCUWDT_LOAD_OFFSET);
+ XScuWdt_LoadWdt(InstancePtr, 0xFFFFFFFFU);
+
+ /*
+ * Start the watchdog timer and check if the watchdog counter is
+ * decrementing.
+ */
+ XScuWdt_SetControlReg(InstancePtr,
+ CtrlOrig | (u32)XSCUWDT_CONTROL_WD_ENABLE_MASK);
+
+ Register = XScuWdt_ReadReg((InstancePtr)->Config.BaseAddr,
+ XSCUWDT_COUNTER_OFFSET);
+
+ XScuWdt_LoadWdt(InstancePtr, LoadOrig);
+ XScuWdt_SetControlReg(InstancePtr, CtrlOrig);
+
+ if (Register == 0xFFFFFFFFU) {
+ SelfTestStatus = (s32)XST_FAILURE;
+ }
+ else {
+ SelfTestStatus = (s32)XST_SUCCESS;
+ }
+
+ return SelfTestStatus;
+}
+/** @} */
diff --git a/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/scuwdt_v2_1/src/xscuwdt_sinit.c b/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/scuwdt_v2_1/src/xscuwdt_sinit.c
new file mode 100644
index 0000000..7e333fb
--- /dev/null
+++ b/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/scuwdt_v2_1/src/xscuwdt_sinit.c
@@ -0,0 +1,90 @@
+/******************************************************************************
+*
+* Copyright (C) 2010 - 2015 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+* THE SOFTWARE.
+*
+*
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xscuwdt_sinit.c
+* @addtogroup scuwdt_v2_1
+* @{
+*
+* This file contains method for static initialization (compile-time) of the
+* driver.
+*
+* <pre>
+* MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ----- --- -------- ---------------------------------------------
+* 1.00a sdm 01/15/10 First release
+* 2.1 sk 02/26/15 Modified the code for MISRA-C:2012 compliance.
+* </pre>
+*
+******************************************************************************/
+
+/***************************** Include Files *********************************/
+
+#include "xscuwdt.h"
+#include "xparameters.h"
+
+/************************** Constant Definitions *****************************/
+
+/**************************** Type Definitions *******************************/
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/************************** Function Prototypes ******************************/
+
+/************************** Variable Definitions *****************************/
+extern XScuWdt_Config XScuWdt_ConfigTable[XPAR_XSCUWDT_NUM_INSTANCES];
+
+/*****************************************************************************/
+/**
+* Lookup the device configuration based on the unique device ID. The table
+* contains the configuration info for each device in the system.
+*
+* @param DeviceId is the unique device ID of the device being looked up.
+*
+* @return A pointer to the configuration table entry corresponding to the
+* given device ID, or NULL if no match is found.
+*
+* @note None.
+*
+******************************************************************************/
+XScuWdt_Config *XScuWdt_LookupConfig(u16 DeviceId)
+{
+ XScuWdt_Config *CfgPtr = NULL;
+ u32 Index;
+
+ for (Index = 0U; Index < XPAR_XSCUWDT_NUM_INSTANCES; Index++) {
+ if (XScuWdt_ConfigTable[Index].DeviceId == DeviceId) {
+ CfgPtr = &XScuWdt_ConfigTable[Index];
+ break;
+ }
+ }
+
+ return (XScuWdt_Config *)CfgPtr;
+}
+/** @} */
diff --git a/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/sdps_v3_8/src/Makefile b/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/sdps_v3_8/src/Makefile
new file mode 100644
index 0000000..f57081a
--- /dev/null
+++ b/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/sdps_v3_8/src/Makefile
@@ -0,0 +1,40 @@
+COMPILER=
+ARCHIVER=
+CP=cp
+COMPILER_FLAGS=
+EXTRA_COMPILER_FLAGS=
+LIB=libxil.a
+
+CC_FLAGS = $(COMPILER_FLAGS)
+ECC_FLAGS = $(EXTRA_COMPILER_FLAGS)
+
+RELEASEDIR=../../../lib
+INCLUDEDIR=../../../include
+INCLUDES=-I./. -I${INCLUDEDIR}
+
+OUTS = *.o
+
+LIBSOURCES:=*.c
+INCLUDEFILES:=*.h
+
+OBJECTS = $(addsuffix .o, $(basename $(wildcard *.c)))
+
+libs: banner xsdps_libs clean
+
+%.o: %.c
+ ${COMPILER} $(CC_FLAGS) $(ECC_FLAGS) $(INCLUDES) -o $@ $<
+
+banner:
+ echo "Compiling sdps"
+
+xsdps_libs: ${OBJECTS}
+ $(ARCHIVER) -r ${RELEASEDIR}/${LIB} ${OBJECTS}
+
+.PHONY: include
+include: xsdps_includes
+
+xsdps_includes:
+ ${CP} ${INCLUDEFILES} ${INCLUDEDIR}
+
+clean:
+ rm -rf ${OBJECTS}
diff --git a/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/sdps_v3_8/src/xsdps.c b/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/sdps_v3_8/src/xsdps.c
new file mode 100644
index 0000000..bd811a5
--- /dev/null
+++ b/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/sdps_v3_8/src/xsdps.c
@@ -0,0 +1,2040 @@
+/******************************************************************************
+*
+* Copyright (C) 2013 - 2019 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+* THE SOFTWARE.
+*
+*
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xsdps.c
+* @addtogroup sdps_v3_8
+* @{
+*
+* Contains the interface functions of the XSdPs driver.
+* See xsdps.h for a detailed description of the device and driver.
+*
+* <pre>
+* MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ----- --- -------- -----------------------------------------------
+* 1.00a hk/sg 10/17/13 Initial release
+* 2.0 hk 12/13/13 Added check for arm to use sleep.h and its API's
+* 2.1 hk 04/18/14 Add sleep for microblaze designs. CR# 781117.
+* 2.2 hk 07/28/14 Make changes to enable use of data cache.
+* 2.3 sk 09/23/14 Send command for relative card address
+* when re-initialization is done.CR# 819614.
+* Use XSdPs_Change_ClkFreq API whenever changing
+* clock.CR# 816586.
+* 2.4 sk 12/04/14 Added support for micro SD without
+* WP/CD. CR# 810655.
+* Checked for DAT Inhibit mask instead of CMD
+* Inhibit mask in Cmd Transfer API.
+* Added Support for SD Card v1.0
+* 2.5 sg 07/09/15 Added SD 3.0 features
+* kvn 07/15/15 Modified the code according to MISRAC-2012.
+* 2.6 sk 10/12/15 Added support for SD card v1.0 CR# 840601.
+* 2.7 sk 11/24/15 Considered the slot type befoe checking CD/WP pins.
+* sk 12/10/15 Added support for MMC cards.
+* sk 02/16/16 Corrected the Tuning logic.
+* sk 03/01/16 Removed Bus Width check for eMMC. CR# 938311.
+* 2.8 sk 05/03/16 Standard Speed for SD to 19MHz in ZynqMPSoC. CR#951024
+* 3.0 sk 06/09/16 Added support for mkfs to calculate sector count.
+* sk 07/16/16 Added support for UHS modes.
+* sk 07/07/16 Used usleep API for both arm and microblaze.
+* sk 07/16/16 Added Tap delays accordingly to different SD/eMMC
+* operating modes.
+* 3.1 mi 09/07/16 Removed compilation warnings with extra compiler flags.
+* sk 10/13/16 Reduced the delay during power cycle to 1ms as per spec
+* sk 10/19/16 Used emmc_hwreset pin to reset eMMC.
+* sk 11/07/16 Enable Rst_n bit in ext_csd reg if not enabled.
+* 3.2 sk 11/30/16 Modified the voltage switching sequence as per spec.
+* sk 02/01/17 Added HSD and DDR mode support for eMMC.
+* vns 02/09/17 Added ARMA53_32 support for ZynqMP CR#968397
+* sk 03/20/17 Add support for EL1 non-secure mode.
+* 3.3 mn 05/17/17 Add support for 64bit DMA addressing
+* mn 07/17/17 Add support for running SD at 200MHz
+* mn 07/26/17 Fixed compilation warnings
+* mn 08/07/17 Modify driver to support 64-bit DMA in arm64 only
+* mn 08/17/17 Added CCI support for A53 and disabled data cache
+* operations when it is enabled.
+* mn 08/22/17 Updated for Word Access System support
+* mn 09/06/17 Resolved compilation errors with IAR toolchain
+* mn 09/26/17 Added UHS_MODE_ENABLE macro to enable UHS mode
+* 3.4 mn 10/17/17 Use different commands for single and multi block
+* transfers
+* mn 03/02/18 Move UHS macro check to SD card initialization routine
+* 3.5 mn 04/18/18 Resolve compilation warnings for sdps driver
+* 3.6 mn 07/06/18 Fix Cppcheck and Doxygen warnings for sdps driver
+* mn 08/01/18 Add support for using 64Bit DMA with 32-Bit Processor
+* mn 08/01/18 Add cache invalidation call before returning from
+* ReadPolled API
+* mn 08/14/18 Resolve compilation warnings for ARMCC toolchain
+* mn 10/01/18 Change Expected Response for CMD3 to R1 for MMC
+* mus 11/05/18 Support 64 bit DMA addresses for Microblaze-X platform.
+* 3.7 mn 02/01/19 Add support for idling of SDIO
+* aru 03/12/19 Modified the code according to MISRAC-2012.
+* 3.8 mn 04/12/19 Modified TapDelay code for supporting ZynqMP and Versal
+* mn 09/17/19 Modified ADMA handling API for 32bit and 64bit addresses
+* </pre>
+*
+******************************************************************************/
+
+/***************************** Include Files *********************************/
+#include "xsdps.h"
+#include "sleep.h"
+
+/************************** Constant Definitions *****************************/
+#define XSDPS_CMD8_VOL_PATTERN 0x1AAU
+#define XSDPS_RESPOCR_READY 0x80000000U
+#define XSDPS_ACMD41_HCS 0x40000000U
+#define XSDPS_ACMD41_3V3 0x00300000U
+#define XSDPS_CMD1_HIGH_VOL 0x00FF8000U
+#define XSDPS_CMD1_DUAL_VOL 0x00FF8010U
+#define HIGH_SPEED_SUPPORT 0x2U
+#define UHS_SDR50_SUPPORT 0x4U
+#define WIDTH_4_BIT_SUPPORT 0x4U
+#define SD_CLK_25_MHZ 25000000U
+#define SD_CLK_19_MHZ 19000000U
+#define SD_CLK_26_MHZ 26000000U
+#define EXT_CSD_DEVICE_TYPE_BYTE 196U
+#define EXT_CSD_SEC_COUNT_BYTE1 212U
+#define EXT_CSD_SEC_COUNT_BYTE2 213U
+#define EXT_CSD_SEC_COUNT_BYTE3 214U
+#define EXT_CSD_SEC_COUNT_BYTE4 215U
+#define EXT_CSD_DEVICE_TYPE_HIGH_SPEED 0x2U
+#define EXT_CSD_DEVICE_TYPE_DDR_1V8_HIGH_SPEED 0x4U
+#define EXT_CSD_DEVICE_TYPE_DDR_1V2_HIGH_SPEED 0x8U
+#define EXT_CSD_DEVICE_TYPE_SDR_1V8_HS200 0x10U
+#define EXT_CSD_DEVICE_TYPE_SDR_1V2_HS200 0x20U
+#define CSD_SPEC_VER_3 0x3U
+#define SCR_SPEC_VER_3 0x80U
+#define ADDRESS_BEYOND_32BIT 0x100000000U
+
+/**************************** Type Definitions *******************************/
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/************************** Function Prototypes ******************************/
+u32 XSdPs_FrameCmd(XSdPs *InstancePtr, u32 Cmd);
+s32 XSdPs_CmdTransfer(XSdPs *InstancePtr, u32 Cmd, u32 Arg, u32 BlkCnt);
+void XSdPs_SetupADMA2DescTbl(XSdPs *InstancePtr, u32 BlkCnt, const u8 *Buff);
+void XSdPs_SetupADMA2DescTbl64Bit(XSdPs *InstancePtr, u32 BlkCnt);
+extern s32 XSdPs_Uhs_ModeInit(XSdPs *InstancePtr, u8 Mode);
+static s32 XSdPs_IdentifyCard(XSdPs *InstancePtr);
+static s32 XSdPs_Switch_Voltage(XSdPs *InstancePtr);
+
+u16 TransferMode;
+/*****************************************************************************/
+/**
+*
+* Initializes a specific XSdPs instance such that the driver is ready to use.
+*
+*
+* @param InstancePtr is a pointer to the XSdPs instance.
+* @param ConfigPtr is a reference to a structure containing information
+* about a specific SD device. This function initializes an
+* InstancePtr object for a specific device specified by the
+* contents of Config.
+* @param EffectiveAddr is the device base address in the virtual memory
+* address space. The caller is responsible for keeping the address
+* mapping from EffectiveAddr to the device physical base address
+* unchanged once this function is invoked. Unexpected errors may
+* occur if the address mapping changes after this function is
+* called. If address translation is not used, use
+* ConfigPtr->Config.BaseAddress for this device.
+*
+* @return
+* - XST_SUCCESS if successful.
+* - XST_DEVICE_IS_STARTED if the device is already started.
+* It must be stopped to re-initialize.
+*
+* @note This function initializes the host controller.
+* Initial clock of 400KHz is set.
+* Voltage of 3.3V is selected as that is supported by host.
+* Interrupts status is enabled and signal disabled by default.
+* Default data direction is card to host and
+* 32 bit ADMA2 is selected. Default Block size is 512 bytes.
+*
+******************************************************************************/
+s32 XSdPs_CfgInitialize(XSdPs *InstancePtr, XSdPs_Config *ConfigPtr,
+ u32 EffectiveAddr)
+{
+ s32 Status;
+ u8 PowerLevel;
+ u8 ReadReg;
+
+ Xil_AssertNonvoid(InstancePtr != NULL);
+ Xil_AssertNonvoid(ConfigPtr != NULL);
+
+ /* Set some default values. */
+ InstancePtr->Config.DeviceId = ConfigPtr->DeviceId;
+ InstancePtr->Config.BaseAddress = EffectiveAddr;
+ InstancePtr->Config.InputClockHz = ConfigPtr->InputClockHz;
+ InstancePtr->IsReady = XIL_COMPONENT_IS_READY;
+ InstancePtr->Config.CardDetect = ConfigPtr->CardDetect;
+ InstancePtr->Config.WriteProtect = ConfigPtr->WriteProtect;
+ InstancePtr->Config.BusWidth = ConfigPtr->BusWidth;
+ InstancePtr->Config.BankNumber = ConfigPtr->BankNumber;
+ InstancePtr->Config.HasEMIO = ConfigPtr->HasEMIO;
+ InstancePtr->Config.IsCacheCoherent = ConfigPtr->IsCacheCoherent;
+ InstancePtr->SectorCount = 0U;
+ InstancePtr->Mode = XSDPS_DEFAULT_SPEED_MODE;
+ InstancePtr->OTapDelay = 0U;
+ InstancePtr->ITapDelay = 0U;
+ InstancePtr->Dma64BitAddr = 0U;
+
+ /* Disable bus power and issue emmc hw reset */
+ if ((XSdPs_ReadReg16(InstancePtr->Config.BaseAddress,
+ XSDPS_HOST_CTRL_VER_OFFSET) & XSDPS_HC_SPEC_VER_MASK) ==
+ XSDPS_HC_SPEC_V3) {
+ XSdPs_WriteReg8(InstancePtr->Config.BaseAddress,
+ XSDPS_POWER_CTRL_OFFSET, XSDPS_PC_EMMC_HW_RST_MASK);
+ } else {
+ XSdPs_WriteReg8(InstancePtr->Config.BaseAddress,
+ XSDPS_POWER_CTRL_OFFSET, 0x0);
+ }
+
+ /* Delay to poweroff card */
+ (void)usleep(1000U);
+
+ /* "Software reset for all" is initiated */
+ XSdPs_WriteReg8(InstancePtr->Config.BaseAddress, XSDPS_SW_RST_OFFSET,
+ XSDPS_SWRST_ALL_MASK);
+
+ /* Proceed with initialization only after reset is complete */
+ ReadReg = XSdPs_ReadReg8(InstancePtr->Config.BaseAddress,
+ XSDPS_SW_RST_OFFSET);
+ while ((ReadReg & XSDPS_SWRST_ALL_MASK) != 0U) {
+ ReadReg = XSdPs_ReadReg8(InstancePtr->Config.BaseAddress,
+ XSDPS_SW_RST_OFFSET);
+ }
+ /* Host Controller version is read. */
+ InstancePtr->HC_Version =
+ (u8)(XSdPs_ReadReg16(InstancePtr->Config.BaseAddress,
+ XSDPS_HOST_CTRL_VER_OFFSET) & XSDPS_HC_SPEC_VER_MASK);
+
+ /*
+ * Read capabilities register and update it in Instance pointer.
+ * It is sufficient to read this once on power on.
+ */
+ InstancePtr->Host_Caps = XSdPs_ReadReg(InstancePtr->Config.BaseAddress,
+ XSDPS_CAPS_OFFSET);
+
+ /* Select voltage and enable bus power. */
+ if (InstancePtr->HC_Version == XSDPS_HC_SPEC_V3) {
+ XSdPs_WriteReg8(InstancePtr->Config.BaseAddress,
+ XSDPS_POWER_CTRL_OFFSET,
+ (XSDPS_PC_BUS_VSEL_3V3_MASK | XSDPS_PC_BUS_PWR_MASK) &
+ ~XSDPS_PC_EMMC_HW_RST_MASK);
+ } else {
+ XSdPs_WriteReg8(InstancePtr->Config.BaseAddress,
+ XSDPS_POWER_CTRL_OFFSET,
+ XSDPS_PC_BUS_VSEL_3V3_MASK | XSDPS_PC_BUS_PWR_MASK);
+ }
+
+ /* Delay before issuing the command after emmc reset */
+ if (InstancePtr->HC_Version == XSDPS_HC_SPEC_V3) {
+ if ((InstancePtr->Host_Caps & XSDPS_CAPS_SLOT_TYPE_MASK) ==
+ XSDPS_CAPS_EMB_SLOT) {
+ usleep(200);
+ }
+ }
+
+ /* Change the clock frequency to 400 KHz */
+ Status = XSdPs_Change_ClkFreq(InstancePtr, XSDPS_CLK_400_KHZ);
+ if (Status != XST_SUCCESS) {
+ Status = XST_FAILURE;
+ goto RETURN_PATH ;
+ }
+
+ if ((InstancePtr->Host_Caps & XSDPS_CAP_VOLT_3V3_MASK) != 0U) {
+ PowerLevel = XSDPS_PC_BUS_VSEL_3V3_MASK;
+ } else if ((InstancePtr->Host_Caps & XSDPS_CAP_VOLT_3V0_MASK) != 0U) {
+ PowerLevel = XSDPS_PC_BUS_VSEL_3V0_MASK;
+ } else if ((InstancePtr->Host_Caps & XSDPS_CAP_VOLT_1V8_MASK) != 0U) {
+ PowerLevel = XSDPS_PC_BUS_VSEL_1V8_MASK;
+ } else {
+ PowerLevel = 0U;
+ }
+
+ /* Select voltage based on capability and enable bus power. */
+ XSdPs_WriteReg8(InstancePtr->Config.BaseAddress,
+ XSDPS_POWER_CTRL_OFFSET,
+ PowerLevel | XSDPS_PC_BUS_PWR_MASK);
+
+ if (InstancePtr->HC_Version == XSDPS_HC_SPEC_V3) {
+ /* Enable ADMA2 in 64bit mode. */
+ XSdPs_WriteReg8(InstancePtr->Config.BaseAddress,
+ XSDPS_HOST_CTRL1_OFFSET,
+ XSDPS_HC_DMA_ADMA2_64_MASK);
+ } else {
+ /* Enable ADMA2 in 32bit mode. */
+ XSdPs_WriteReg8(InstancePtr->Config.BaseAddress,
+ XSDPS_HOST_CTRL1_OFFSET,
+ XSDPS_HC_DMA_ADMA2_32_MASK);
+ }
+
+ /* Enable all interrupt status except card interrupt initially */
+ XSdPs_WriteReg16(InstancePtr->Config.BaseAddress,
+ XSDPS_NORM_INTR_STS_EN_OFFSET,
+ XSDPS_NORM_INTR_ALL_MASK & (~XSDPS_INTR_CARD_MASK));
+
+ XSdPs_WriteReg16(InstancePtr->Config.BaseAddress,
+ XSDPS_ERR_INTR_STS_EN_OFFSET,
+ XSDPS_ERROR_INTR_ALL_MASK);
+
+ /* Disable all interrupt signals by default. */
+ XSdPs_WriteReg16(InstancePtr->Config.BaseAddress,
+ XSDPS_NORM_INTR_SIG_EN_OFFSET, 0x0U);
+ XSdPs_WriteReg16(InstancePtr->Config.BaseAddress,
+ XSDPS_ERR_INTR_SIG_EN_OFFSET, 0x0U);
+
+ /*
+ * Transfer mode register - default value
+ * DMA enabled, block count enabled, data direction card to host(read)
+ */
+ TransferMode = XSDPS_TM_DMA_EN_MASK | XSDPS_TM_BLK_CNT_EN_MASK |
+ XSDPS_TM_DAT_DIR_SEL_MASK;
+
+ /* Set block size to 512 by default */
+ XSdPs_WriteReg16(InstancePtr->Config.BaseAddress,
+ XSDPS_BLK_SIZE_OFFSET, XSDPS_BLK_SIZE_512_MASK);
+
+ Status = XST_SUCCESS;
+
+RETURN_PATH:
+ return Status;
+
+}
+
+/*****************************************************************************/
+/**
+* SD initialization is done in this function
+*
+*
+* @param InstancePtr is a pointer to the instance to be worked on.
+*
+* @return
+* - XST_SUCCESS if initialization was successful
+* - XST_FAILURE if failure - could be because
+* a) SD is already initialized
+* b) There is no card inserted
+* c) One of the steps (commands) in the
+ initialization cycle failed
+*
+* @note This function initializes the SD card by following its
+* initialization and identification state diagram.
+* CMD0 is sent to reset card.
+* CMD8 and ACDM41 are sent to identify voltage and
+* high capacity support
+* CMD2 and CMD3 are sent to obtain Card ID and
+* Relative card address respectively.
+* CMD9 is sent to read the card specific data.
+*
+******************************************************************************/
+s32 XSdPs_SdCardInitialize(XSdPs *InstancePtr)
+{
+ u32 PresentStateReg;
+ s32 Status;
+ u32 RespOCR;
+ u32 CSD[4];
+ u32 Arg;
+ u8 ReadReg;
+ u32 BlkLen, DeviceSize, Mult;
+
+ Xil_AssertNonvoid(InstancePtr != NULL);
+ Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+#ifndef UHS_MODE_ENABLE
+ InstancePtr->Config.BusWidth = XSDPS_WIDTH_4;
+#endif
+
+ if ((InstancePtr->HC_Version != XSDPS_HC_SPEC_V3) ||
+ ((InstancePtr->Host_Caps & XSDPS_CAPS_SLOT_TYPE_MASK)
+ != XSDPS_CAPS_EMB_SLOT)) {
+ if(InstancePtr->Config.CardDetect != 0U) {
+ /*
+ * Check the present state register to make sure
+ * card is inserted and detected by host controller
+ */
+ PresentStateReg = XSdPs_ReadReg(InstancePtr->Config.BaseAddress,
+ XSDPS_PRES_STATE_OFFSET);
+ if ((PresentStateReg & XSDPS_PSR_CARD_INSRT_MASK) == 0U) {
+ Status = XST_FAILURE;
+ goto RETURN_PATH;
+ }
+ }
+ }
+
+ /* CMD0 no response expected */
+ Status = XSdPs_CmdTransfer(InstancePtr, (u32)CMD0, 0U, 0U);
+ if (Status != XST_SUCCESS) {
+ Status = XST_FAILURE;
+ goto RETURN_PATH;
+ }
+
+ /*
+ * CMD8; response expected
+ * 0x1AA - Supply Voltage 2.7 - 3.6V and AA is pattern
+ */
+ Status = XSdPs_CmdTransfer(InstancePtr, CMD8,
+ XSDPS_CMD8_VOL_PATTERN, 0U);
+ if ((Status != XST_SUCCESS) && (Status != XSDPS_CT_ERROR)) {
+ Status = XST_FAILURE;
+ goto RETURN_PATH;
+ }
+
+ if (Status == XSDPS_CT_ERROR) {
+ /* "Software reset for all" is initiated */
+ XSdPs_WriteReg8(InstancePtr->Config.BaseAddress, XSDPS_SW_RST_OFFSET,
+ XSDPS_SWRST_CMD_LINE_MASK);
+
+ /* Proceed with initialization only after reset is complete */
+ ReadReg = XSdPs_ReadReg8(InstancePtr->Config.BaseAddress,
+ XSDPS_SW_RST_OFFSET);
+ while ((ReadReg & XSDPS_SWRST_CMD_LINE_MASK) != 0U) {
+ ReadReg = XSdPs_ReadReg8(InstancePtr->Config.BaseAddress,
+ XSDPS_SW_RST_OFFSET);
+ }
+ }
+
+ RespOCR = XSdPs_ReadReg(InstancePtr->Config.BaseAddress,
+ XSDPS_RESP0_OFFSET);
+ if (RespOCR != XSDPS_CMD8_VOL_PATTERN) {
+ InstancePtr->Card_Version = XSDPS_SD_VER_1_0;
+ }
+ else {
+ InstancePtr->Card_Version = XSDPS_SD_VER_2_0;
+ }
+
+ RespOCR = 0U;
+ /* Send ACMD41 while card is still busy with power up */
+ while ((RespOCR & XSDPS_RESPOCR_READY) == 0U) {
+ Status = XSdPs_CmdTransfer(InstancePtr, CMD55, 0U, 0U);
+ if (Status != XST_SUCCESS) {
+ Status = XST_FAILURE;
+ goto RETURN_PATH;
+ }
+
+ Arg = XSDPS_ACMD41_HCS | XSDPS_ACMD41_3V3 | (0x1FFU << 15U);
+ /*
+ * There is no support to switch to 1.8V and use UHS mode on
+ * 1.0 silicon
+ */
+ if ((InstancePtr->HC_Version == XSDPS_HC_SPEC_V3) &&
+#if defined (ARMR5) || (__aarch64__) || (ARMA53_32) || (PSU_PMU)
+ (XGetPSVersion_Info() > (u32)XPS_VERSION_1) &&
+#endif
+ (InstancePtr->Config.BusWidth == XSDPS_WIDTH_8)) {
+ Arg |= XSDPS_OCR_S18;
+ }
+
+ /* 0x40300000 - Host High Capacity support & 3.3V window */
+ Status = XSdPs_CmdTransfer(InstancePtr, ACMD41,
+ Arg, 0U);
+ if (Status != XST_SUCCESS) {
+ Status = XST_FAILURE;
+ goto RETURN_PATH;
+ }
+
+ /* Response with card capacity */
+ RespOCR = XSdPs_ReadReg(InstancePtr->Config.BaseAddress,
+ XSDPS_RESP0_OFFSET);
+
+ }
+
+ /* Update HCS support flag based on card capacity response */
+ if ((RespOCR & XSDPS_ACMD41_HCS) != 0U) {
+ InstancePtr->HCS = 1U;
+ }
+
+ if ((RespOCR & XSDPS_OCR_S18) != 0U) {
+ InstancePtr->Switch1v8 = 1U;
+ Status = XSdPs_Switch_Voltage(InstancePtr);
+ if (Status != XST_SUCCESS) {
+ Status = XST_FAILURE;
+ goto RETURN_PATH;
+ }
+ }
+
+ /* CMD2 for Card ID */
+ Status = XSdPs_CmdTransfer(InstancePtr, CMD2, 0U, 0U);
+ if (Status != XST_SUCCESS) {
+ Status = XST_FAILURE;
+ goto RETURN_PATH;
+ }
+
+ InstancePtr->CardID[0] =
+ XSdPs_ReadReg16(InstancePtr->Config.BaseAddress,
+ XSDPS_RESP0_OFFSET);
+ InstancePtr->CardID[1] =
+ XSdPs_ReadReg16(InstancePtr->Config.BaseAddress,
+ XSDPS_RESP1_OFFSET);
+ InstancePtr->CardID[2] =
+ XSdPs_ReadReg16(InstancePtr->Config.BaseAddress,
+ XSDPS_RESP2_OFFSET);
+ InstancePtr->CardID[3] =
+ XSdPs_ReadReg16(InstancePtr->Config.BaseAddress,
+ XSDPS_RESP3_OFFSET);
+ do {
+ Status = XSdPs_CmdTransfer(InstancePtr, CMD3, 0U, 0U);
+ if (Status != XST_SUCCESS) {
+ Status = XST_FAILURE;
+ goto RETURN_PATH;
+ }
+
+ /*
+ * Relative card address is stored as the upper 16 bits
+ * This is to avoid shifting when sending commands
+ */
+ InstancePtr->RelCardAddr =
+ XSdPs_ReadReg(InstancePtr->Config.BaseAddress,
+ XSDPS_RESP0_OFFSET) & 0xFFFF0000U;
+ } while (InstancePtr->RelCardAddr == 0U);
+
+ Status = XSdPs_CmdTransfer(InstancePtr, CMD9, (InstancePtr->RelCardAddr), 0U);
+ if (Status != XST_SUCCESS) {
+ Status = XST_FAILURE;
+ goto RETURN_PATH;
+ }
+
+ /*
+ * Card specific data is read.
+ * Currently not used for any operation.
+ */
+ CSD[0] = XSdPs_ReadReg(InstancePtr->Config.BaseAddress,
+ XSDPS_RESP0_OFFSET);
+ CSD[1] = XSdPs_ReadReg(InstancePtr->Config.BaseAddress,
+ XSDPS_RESP1_OFFSET);
+ CSD[2] = XSdPs_ReadReg(InstancePtr->Config.BaseAddress,
+ XSDPS_RESP2_OFFSET);
+ CSD[3] = XSdPs_ReadReg(InstancePtr->Config.BaseAddress,
+ XSDPS_RESP3_OFFSET);
+
+ if (((CSD[3] & CSD_STRUCT_MASK) >> 22U) == 0U) {
+ BlkLen = 1U << ((u32)(CSD[2] & READ_BLK_LEN_MASK) >> 8U);
+ Mult = 1U << ((u32)((CSD[1] & C_SIZE_MULT_MASK) >> 7U) + 2U);
+ DeviceSize = (CSD[1] & C_SIZE_LOWER_MASK) >> 22U;
+ DeviceSize |= (CSD[2] & C_SIZE_UPPER_MASK) << 10U;
+ DeviceSize = (DeviceSize + 1U) * Mult;
+ DeviceSize = DeviceSize * BlkLen;
+ InstancePtr->SectorCount = (DeviceSize/XSDPS_BLK_SIZE_512_MASK);
+ } else if (((CSD[3] & CSD_STRUCT_MASK) >> 22U) == 1U) {
+ InstancePtr->SectorCount = (((CSD[1] & CSD_V2_C_SIZE_MASK) >> 8U) +
+ 1U) * 1024U;
+ } else {
+ Status = XST_FAILURE;
+ goto RETURN_PATH;
+ }
+
+ Status = XST_SUCCESS;
+
+RETURN_PATH:
+ return Status;
+
+}
+
+/*****************************************************************************/
+/**
+*
+* Initialize Card with Identification mode sequence
+*
+*
+* @param InstancePtr is a pointer to the instance to be worked on.
+*
+* @return
+* - XST_SUCCESS if initialization was successful
+* - XST_FAILURE if failure - could be because
+* a) SD is already initialized
+* b) There is no card inserted
+* c) One of the steps (commands) in the
+* initialization cycle failed
+*
+*
+******************************************************************************/
+s32 XSdPs_CardInitialize(XSdPs *InstancePtr)
+{
+#ifdef __ICCARM__
+#pragma data_alignment = 32
+ static u8 ExtCsd[512];
+#pragma data_alignment = 32
+ static u8 SCR[8] = { 0U };
+#else
+ static u8 ExtCsd[512] __attribute__ ((aligned(32)));
+ static u8 SCR[8] __attribute__ ((aligned(32))) = { 0U };
+#endif
+ u8 ReadBuff[64] = { 0U };
+ s32 Status;
+ u32 Arg;
+
+ Xil_AssertNonvoid(InstancePtr != NULL);
+ Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+ /* Default settings */
+ InstancePtr->BusWidth = XSDPS_1_BIT_WIDTH;
+ InstancePtr->CardType = XSDPS_CARD_SD;
+ InstancePtr->Switch1v8 = 0U;
+ InstancePtr->BusSpeed = XSDPS_CLK_400_KHZ;
+
+ if ((InstancePtr->HC_Version == XSDPS_HC_SPEC_V3) &&
+ ((InstancePtr->Host_Caps & XSDPS_CAPS_SLOT_TYPE_MASK)
+ == XSDPS_CAPS_EMB_SLOT)) {
+ InstancePtr->CardType = XSDPS_CHIP_EMMC;
+ } else {
+ Status = XSdPs_IdentifyCard(InstancePtr);
+ if (Status == XST_FAILURE) {
+ goto RETURN_PATH;
+ }
+ }
+
+ if ((InstancePtr->CardType != XSDPS_CARD_SD) &&
+ (InstancePtr->CardType != XSDPS_CARD_MMC) &&
+ (InstancePtr->CardType != XSDPS_CHIP_EMMC)) {
+ Status = XST_FAILURE;
+ goto RETURN_PATH;
+ }
+
+ if (InstancePtr->CardType == XSDPS_CARD_SD) {
+ Status = XSdPs_SdCardInitialize(InstancePtr);
+ if (Status != XST_SUCCESS) {
+ Status = XST_FAILURE;
+ goto RETURN_PATH;
+ }
+
+ /* Change clock to default clock 25MHz */
+ /*
+ * SD default speed mode timing should be closed at 19 MHz.
+ * The reason for this is SD requires a voltage level shifter.
+ * This limitation applies to ZynqMPSoC.
+ */
+ if (InstancePtr->HC_Version == XSDPS_HC_SPEC_V3) {
+ InstancePtr->BusSpeed = SD_CLK_19_MHZ;
+ } else {
+ InstancePtr->BusSpeed = SD_CLK_25_MHZ;
+ }
+ Status = XSdPs_Change_ClkFreq(InstancePtr, InstancePtr->BusSpeed);
+ if (Status != XST_SUCCESS) {
+ Status = XST_FAILURE;
+ goto RETURN_PATH;
+ }
+
+ } else if ((InstancePtr->CardType == XSDPS_CARD_MMC)
+ || (InstancePtr->CardType == XSDPS_CHIP_EMMC)) {
+ Status = XSdPs_MmcCardInitialize(InstancePtr);
+ if (Status != XST_SUCCESS) {
+ Status = XST_FAILURE;
+ goto RETURN_PATH;
+ }
+ /* Change clock to default clock 26MHz */
+ InstancePtr->BusSpeed = SD_CLK_26_MHZ;
+ Status = XSdPs_Change_ClkFreq(InstancePtr, InstancePtr->BusSpeed);
+ if (Status != XST_SUCCESS) {
+ Status = XST_FAILURE;
+ goto RETURN_PATH;
+ }
+ } else {
+ Status = XST_FAILURE;
+ goto RETURN_PATH;
+ }
+
+ Status = XSdPs_Select_Card(InstancePtr);
+ if (Status != XST_SUCCESS) {
+ Status = XST_FAILURE;
+ goto RETURN_PATH;
+ }
+
+ if (InstancePtr->CardType == XSDPS_CARD_SD) {
+ /* Pull-up disconnected during data transfer */
+ Status = XSdPs_Pullup(InstancePtr);
+ if (Status != XST_SUCCESS) {
+ Status = XST_FAILURE;
+ goto RETURN_PATH;
+ }
+
+ Status = XSdPs_Get_BusWidth(InstancePtr, SCR);
+ if (Status != XST_SUCCESS) {
+ Status = XST_FAILURE;
+ goto RETURN_PATH;
+ }
+
+ if ((SCR[1] & WIDTH_4_BIT_SUPPORT) != 0U) {
+ Status = XSdPs_Change_BusWidth(InstancePtr);
+ if (Status != XST_SUCCESS) {
+ Status = XST_FAILURE;
+ goto RETURN_PATH;
+ }
+ }
+
+ /* Get speed supported by device */
+ Status = XSdPs_Get_BusSpeed(InstancePtr, ReadBuff);
+ if (Status != XST_SUCCESS) {
+ goto RETURN_PATH;
+ }
+
+ if (((SCR[2] & SCR_SPEC_VER_3) != 0U) &&
+ (ReadBuff[13] >= UHS_SDR50_SUPPORT) &&
+ (InstancePtr->Config.BusWidth == XSDPS_WIDTH_8) &&
+#if defined (ARMR5) || (__aarch64__) || (ARMA53_32) || (PSU_PMU)
+ (XGetPSVersion_Info() > (u32)XPS_VERSION_1) &&
+#endif
+ (InstancePtr->Switch1v8 == 0U)) {
+ u16 CtrlReg, ClockReg;
+
+ /* Stop the clock */
+ CtrlReg = XSdPs_ReadReg16(InstancePtr->Config.BaseAddress,
+ XSDPS_CLK_CTRL_OFFSET);
+ CtrlReg &= ~(XSDPS_CC_SD_CLK_EN_MASK | XSDPS_CC_INT_CLK_EN_MASK);
+ XSdPs_WriteReg16(InstancePtr->Config.BaseAddress, XSDPS_CLK_CTRL_OFFSET,
+ CtrlReg);
+
+ /* Enabling 1.8V in controller */
+ CtrlReg = XSdPs_ReadReg16(InstancePtr->Config.BaseAddress,
+ XSDPS_HOST_CTRL2_OFFSET);
+ CtrlReg |= XSDPS_HC2_1V8_EN_MASK;
+ XSdPs_WriteReg16(InstancePtr->Config.BaseAddress, XSDPS_HOST_CTRL2_OFFSET,
+ CtrlReg);
+
+ /* Wait minimum 5mSec */
+ (void)usleep(5000U);
+
+ /* Check for 1.8V signal enable bit is cleared by Host */
+ CtrlReg = XSdPs_ReadReg16(InstancePtr->Config.BaseAddress,
+ XSDPS_HOST_CTRL2_OFFSET);
+ if ((CtrlReg & XSDPS_HC2_1V8_EN_MASK) == 0U) {
+ Status = XST_FAILURE;
+ goto RETURN_PATH;
+ }
+
+ /* Wait for internal clock to stabilize */
+ ClockReg = XSdPs_ReadReg16(InstancePtr->Config.BaseAddress,
+ XSDPS_CLK_CTRL_OFFSET);
+ XSdPs_WriteReg16(InstancePtr->Config.BaseAddress,
+ XSDPS_CLK_CTRL_OFFSET,
+ ClockReg | XSDPS_CC_INT_CLK_EN_MASK);
+ ClockReg = XSdPs_ReadReg16(InstancePtr->Config.BaseAddress,
+ XSDPS_CLK_CTRL_OFFSET);
+ while((ClockReg & XSDPS_CC_INT_CLK_STABLE_MASK) == 0U) {
+ ClockReg = XSdPs_ReadReg16(InstancePtr->Config.BaseAddress,
+ XSDPS_CLK_CTRL_OFFSET);
+ }
+
+ /* Enable SD clock */
+ ClockReg = XSdPs_ReadReg16(InstancePtr->Config.BaseAddress,
+ XSDPS_CLK_CTRL_OFFSET);
+ XSdPs_WriteReg16(InstancePtr->Config.BaseAddress,
+ XSDPS_CLK_CTRL_OFFSET,
+ ClockReg | XSDPS_CC_SD_CLK_EN_MASK);
+
+ /* Wait for 1mSec */
+ (void)usleep(1000U);
+
+ InstancePtr->Switch1v8 = 1U;
+ }
+
+#if defined (ARMR5) || defined (__aarch64__) || defined (ARMA53_32) || defined (__MICROBLAZE__)
+ if (InstancePtr->Switch1v8 != 0U) {
+
+ /* Identify the UHS mode supported by card */
+ XSdPs_Identify_UhsMode(InstancePtr, ReadBuff);
+
+ /* Set UHS-I SDR104 mode */
+ Status = XSdPs_Uhs_ModeInit(InstancePtr, (u8)InstancePtr->Mode);
+ if (Status != XST_SUCCESS) {
+ goto RETURN_PATH;
+ }
+
+ } else {
+#endif
+ /*
+ * card supports CMD6 when SD_SPEC field in SCR register
+ * indicates that the Physical Layer Specification Version
+ * is 1.10 or later. So for SD v1.0 cmd6 is not supported.
+ */
+ if (SCR[0] != 0U) {
+ /* Check for high speed support */
+ if (((ReadBuff[13] & HIGH_SPEED_SUPPORT) != 0U) &&
+ (InstancePtr->BusWidth >= XSDPS_4_BIT_WIDTH)) {
+ InstancePtr->Mode = XSDPS_HIGH_SPEED_MODE;
+#if defined (ARMR5) || defined (__aarch64__) || defined (ARMA53_32) || defined (__MICROBLAZE__)
+ InstancePtr->OTapDelay = SD_OTAPDLYSEL_SD_HSD;
+ InstancePtr->ITapDelay = SD_ITAPDLYSEL_HSD;
+#endif
+ Status = XSdPs_Change_BusSpeed(InstancePtr);
+ if (Status != XST_SUCCESS) {
+ Status = XST_FAILURE;
+ goto RETURN_PATH;
+ }
+ }
+ }
+#if defined (ARMR5) || defined (__aarch64__) || defined (ARMA53_32) || defined (__MICROBLAZE__)
+ }
+#endif
+
+ } else if (((InstancePtr->CardType == XSDPS_CARD_MMC) &&
+ (InstancePtr->Card_Version > CSD_SPEC_VER_3)) &&
+ (InstancePtr->HC_Version == XSDPS_HC_SPEC_V2)) {
+
+ Status = XSdPs_Change_BusWidth(InstancePtr);
+ if (Status != XST_SUCCESS) {
+ Status = XST_FAILURE;
+ goto RETURN_PATH;
+ }
+
+ Status = XSdPs_Get_Mmc_ExtCsd(InstancePtr, ExtCsd);
+ if (Status != XST_SUCCESS) {
+ Status = XST_FAILURE;
+ goto RETURN_PATH;
+ }
+
+ InstancePtr->SectorCount = ((u32)ExtCsd[EXT_CSD_SEC_COUNT_BYTE4]) << 24;
+ InstancePtr->SectorCount |= (u32)ExtCsd[EXT_CSD_SEC_COUNT_BYTE3] << 16;
+ InstancePtr->SectorCount |= (u32)ExtCsd[EXT_CSD_SEC_COUNT_BYTE2] << 8;
+ InstancePtr->SectorCount |= (u32)ExtCsd[EXT_CSD_SEC_COUNT_BYTE1];
+
+ if (((ExtCsd[EXT_CSD_DEVICE_TYPE_BYTE] &
+ EXT_CSD_DEVICE_TYPE_HIGH_SPEED) != 0U) &&
+ (InstancePtr->BusWidth >= XSDPS_4_BIT_WIDTH)) {
+ InstancePtr->Mode = XSDPS_HIGH_SPEED_MODE;
+ Status = XSdPs_Change_BusSpeed(InstancePtr);
+ if (Status != XST_SUCCESS) {
+ Status = XST_FAILURE;
+ goto RETURN_PATH;
+ }
+
+ Status = XSdPs_Get_Mmc_ExtCsd(InstancePtr, ExtCsd);
+ if (Status != XST_SUCCESS) {
+ Status = XST_FAILURE;
+ goto RETURN_PATH;
+ }
+
+ if (ExtCsd[EXT_CSD_HS_TIMING_BYTE] != EXT_CSD_HS_TIMING_HIGH) {
+ Status = XST_FAILURE;
+ goto RETURN_PATH;
+ }
+ }
+ } else if (InstancePtr->CardType == XSDPS_CHIP_EMMC){
+ /* Change bus width to 8-bit */
+ Status = XSdPs_Change_BusWidth(InstancePtr);
+ if (Status != XST_SUCCESS) {
+ Status = XST_FAILURE;
+ goto RETURN_PATH;
+ }
+
+ /* Get Extended CSD */
+ Status = XSdPs_Get_Mmc_ExtCsd(InstancePtr, ExtCsd);
+ if (Status != XST_SUCCESS) {
+ Status = XST_FAILURE;
+ goto RETURN_PATH;
+ }
+
+ InstancePtr->SectorCount = ((u32)ExtCsd[EXT_CSD_SEC_COUNT_BYTE4]) << 24;
+ InstancePtr->SectorCount |= (u32)ExtCsd[EXT_CSD_SEC_COUNT_BYTE3] << 16;
+ InstancePtr->SectorCount |= (u32)ExtCsd[EXT_CSD_SEC_COUNT_BYTE2] << 8;
+ InstancePtr->SectorCount |= (u32)ExtCsd[EXT_CSD_SEC_COUNT_BYTE1];
+
+ /* Check for card supported speed */
+ if (((ExtCsd[EXT_CSD_DEVICE_TYPE_BYTE] &
+ (EXT_CSD_DEVICE_TYPE_SDR_1V8_HS200 |
+ EXT_CSD_DEVICE_TYPE_SDR_1V2_HS200)) != 0U) &&
+ (InstancePtr->BusWidth >= XSDPS_4_BIT_WIDTH)) {
+ InstancePtr->Mode = XSDPS_HS200_MODE;
+#if defined (ARMR5) || defined (__aarch64__) || defined (ARMA53_32) || defined (__MICROBLAZE__)
+ if (InstancePtr->Config.BankNumber == 2U) {
+ InstancePtr->OTapDelay = SD_OTAPDLYSEL_HS200_B2;
+ } else {
+ InstancePtr->OTapDelay = SD_OTAPDLYSEL_HS200_B0;
+ }
+#endif
+ } else if (((ExtCsd[EXT_CSD_DEVICE_TYPE_BYTE] &
+ (EXT_CSD_DEVICE_TYPE_DDR_1V8_HIGH_SPEED |
+ EXT_CSD_DEVICE_TYPE_DDR_1V2_HIGH_SPEED)) != 0U) &&
+ (InstancePtr->BusWidth >= XSDPS_4_BIT_WIDTH)) {
+ InstancePtr->Mode = XSDPS_DDR52_MODE;
+#if defined (ARMR5) || defined (__aarch64__) || defined (ARMA53_32) || defined (__MICROBLAZE__)
+ InstancePtr->OTapDelay = SD_ITAPDLYSEL_EMMC_DDR50;
+ InstancePtr->ITapDelay = SD_ITAPDLYSEL_EMMC_DDR50;
+#endif
+ } else if (((ExtCsd[EXT_CSD_DEVICE_TYPE_BYTE] &
+ EXT_CSD_DEVICE_TYPE_HIGH_SPEED) != 0U) &&
+ (InstancePtr->BusWidth >= XSDPS_4_BIT_WIDTH)) {
+ InstancePtr->Mode = XSDPS_HIGH_SPEED_MODE;
+#if defined (ARMR5) || defined (__aarch64__) || defined (ARMA53_32) || defined (__MICROBLAZE__)
+ InstancePtr->OTapDelay = SD_OTAPDLYSEL_EMMC_HSD;
+ InstancePtr->ITapDelay = SD_ITAPDLYSEL_HSD;
+#endif
+ } else {
+ InstancePtr->Mode = XSDPS_DEFAULT_SPEED_MODE;
+ }
+
+ if (InstancePtr->Mode != XSDPS_DEFAULT_SPEED_MODE) {
+ Status = XSdPs_Change_BusSpeed(InstancePtr);
+ if (Status != XST_SUCCESS) {
+ Status = XST_FAILURE;
+ goto RETURN_PATH;
+ }
+
+ Status = XSdPs_Get_Mmc_ExtCsd(InstancePtr, ExtCsd);
+ if (Status != XST_SUCCESS) {
+ Status = XST_FAILURE;
+ goto RETURN_PATH;
+ }
+
+ if (InstancePtr->Mode == XSDPS_HS200_MODE) {
+ if (ExtCsd[EXT_CSD_HS_TIMING_BYTE] != EXT_CSD_HS_TIMING_HS200) {
+ Status = XST_FAILURE;
+ goto RETURN_PATH;
+ }
+ }
+
+ if ((InstancePtr->Mode == XSDPS_HIGH_SPEED_MODE) ||
+ (InstancePtr->Mode == XSDPS_DDR52_MODE)) {
+ if (ExtCsd[EXT_CSD_HS_TIMING_BYTE] != EXT_CSD_HS_TIMING_HIGH) {
+ Status = XST_FAILURE;
+ goto RETURN_PATH;
+ }
+
+ if (InstancePtr->Mode == XSDPS_DDR52_MODE) {
+ Status = XSdPs_Change_BusWidth(InstancePtr);
+ if (Status != XST_SUCCESS) {
+ Status = XST_FAILURE;
+ goto RETURN_PATH;
+ }
+ }
+ }
+ }
+
+ /* Enable Rst_n_Fun bit if it is disabled */
+ if(ExtCsd[EXT_CSD_RST_N_FUN_BYTE] == EXT_CSD_RST_N_FUN_TEMP_DIS) {
+ Arg = XSDPS_MMC_RST_FUN_EN_ARG;
+ Status = XSdPs_Set_Mmc_ExtCsd(InstancePtr, Arg);
+ if (Status != XST_SUCCESS) {
+ Status = XST_FAILURE;
+ goto RETURN_PATH;
+ }
+ }
+ } else {
+ Status = XST_FAILURE;
+ goto RETURN_PATH;
+ }
+ if ((InstancePtr->Mode != XSDPS_DDR52_MODE) ||
+ (InstancePtr->CardType == XSDPS_CARD_SD)) {
+ Status = XSdPs_SetBlkSize(InstancePtr, XSDPS_BLK_SIZE_512_MASK);
+ if (Status != XST_SUCCESS) {
+ Status = XST_FAILURE;
+ goto RETURN_PATH;
+ }
+ }
+
+RETURN_PATH:
+ return Status;
+}
+
+/*****************************************************************************/
+/**
+*
+* Identify type of card using CMD0 + CMD1 sequence
+*
+*
+* @param InstancePtr is a pointer to the XSdPs instance.
+*
+******************************************************************************/
+static s32 XSdPs_IdentifyCard(XSdPs *InstancePtr)
+{
+ s32 Status;
+ u8 ReadReg;
+
+ Xil_AssertNonvoid(InstancePtr != NULL);
+ Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+ /* 74 CLK delay after card is powered up, before the first command. */
+ usleep(XSDPS_INIT_DELAY);
+
+ /* CMD0 no response expected */
+ Status = XSdPs_CmdTransfer(InstancePtr, CMD0, 0U, 0U);
+ if (Status != XST_SUCCESS) {
+ Status = XST_FAILURE;
+ goto RETURN_PATH;
+ }
+
+ /* Host High Capacity support & High voltage window */
+ Status = XSdPs_CmdTransfer(InstancePtr, CMD1,
+ XSDPS_ACMD41_HCS | XSDPS_CMD1_HIGH_VOL, 0U);
+ if (Status != XST_SUCCESS) {
+ InstancePtr->CardType = XSDPS_CARD_SD;
+ } else {
+ InstancePtr->CardType = XSDPS_CARD_MMC;
+ }
+
+ XSdPs_WriteReg16(InstancePtr->Config.BaseAddress,
+ XSDPS_NORM_INTR_STS_OFFSET, XSDPS_NORM_INTR_ALL_MASK);
+ XSdPs_WriteReg16(InstancePtr->Config.BaseAddress,
+ XSDPS_ERR_INTR_STS_OFFSET, XSDPS_ERROR_INTR_ALL_MASK);
+
+ /* "Software reset for all" is initiated */
+ XSdPs_WriteReg8(InstancePtr->Config.BaseAddress, XSDPS_SW_RST_OFFSET,
+ XSDPS_SWRST_CMD_LINE_MASK);
+
+ /* Proceed with initialization only after reset is complete */
+ ReadReg = XSdPs_ReadReg8(InstancePtr->Config.BaseAddress,
+ XSDPS_SW_RST_OFFSET);
+ while ((ReadReg & XSDPS_SWRST_CMD_LINE_MASK) != 0U) {
+ ReadReg = XSdPs_ReadReg8(InstancePtr->Config.BaseAddress,
+ XSDPS_SW_RST_OFFSET);
+ }
+
+ Status = XST_SUCCESS;
+
+RETURN_PATH:
+ return Status;
+}
+
+/*****************************************************************************/
+/**
+*
+* Switches the SD card voltage from 3v3 to 1v8
+*
+*
+* @param InstancePtr is a pointer to the XSdPs instance.
+*
+******************************************************************************/
+static s32 XSdPs_Switch_Voltage(XSdPs *InstancePtr)
+{
+ s32 Status;
+ u16 CtrlReg;
+ u32 ReadReg, ClockReg;
+
+ /* Send switch voltage command */
+ Status = XSdPs_CmdTransfer(InstancePtr, CMD11, 0U, 0U);
+ if (Status != XST_SUCCESS) {
+ Status = XST_FAILURE;
+ }
+
+ /* Wait for CMD and DATA line to go low */
+ ReadReg = XSdPs_ReadReg(InstancePtr->Config.BaseAddress,
+ XSDPS_PRES_STATE_OFFSET);
+ while ((ReadReg & (XSDPS_PSR_CMD_SG_LVL_MASK |
+ XSDPS_PSR_DAT30_SG_LVL_MASK)) != 0U) {
+ ReadReg = XSdPs_ReadReg(InstancePtr->Config.BaseAddress,
+ XSDPS_PRES_STATE_OFFSET);
+ }
+
+ /* Stop the clock */
+ CtrlReg = XSdPs_ReadReg16(InstancePtr->Config.BaseAddress,
+ XSDPS_CLK_CTRL_OFFSET);
+ CtrlReg &= ~(XSDPS_CC_SD_CLK_EN_MASK | XSDPS_CC_INT_CLK_EN_MASK);
+ XSdPs_WriteReg16(InstancePtr->Config.BaseAddress, XSDPS_CLK_CTRL_OFFSET,
+ CtrlReg);
+
+ /* Enabling 1.8V in controller */
+ CtrlReg = XSdPs_ReadReg16(InstancePtr->Config.BaseAddress,
+ XSDPS_HOST_CTRL2_OFFSET);
+ CtrlReg |= XSDPS_HC2_1V8_EN_MASK;
+ XSdPs_WriteReg16(InstancePtr->Config.BaseAddress, XSDPS_HOST_CTRL2_OFFSET,
+ CtrlReg);
+
+ /* Wait minimum 5mSec */
+ (void)usleep(5000U);
+
+ /* Check for 1.8V signal enable bit is cleared by Host */
+ CtrlReg = XSdPs_ReadReg16(InstancePtr->Config.BaseAddress,
+ XSDPS_HOST_CTRL2_OFFSET);
+ if ((CtrlReg & XSDPS_HC2_1V8_EN_MASK) == 0U) {
+ Status = XST_FAILURE;
+ goto RETURN_PATH;
+ }
+
+ /* Wait for internal clock to stabilize */
+ ClockReg = XSdPs_ReadReg16(InstancePtr->Config.BaseAddress,
+ XSDPS_CLK_CTRL_OFFSET);
+ XSdPs_WriteReg16(InstancePtr->Config.BaseAddress,
+ XSDPS_CLK_CTRL_OFFSET,
+ ClockReg | XSDPS_CC_INT_CLK_EN_MASK);
+ ClockReg = XSdPs_ReadReg16(InstancePtr->Config.BaseAddress,
+ XSDPS_CLK_CTRL_OFFSET);
+ while((ClockReg & XSDPS_CC_INT_CLK_STABLE_MASK) == 0U) {
+ ClockReg = XSdPs_ReadReg16(InstancePtr->Config.BaseAddress,
+ XSDPS_CLK_CTRL_OFFSET);
+ }
+
+ /* Enable SD clock */
+ ClockReg = XSdPs_ReadReg16(InstancePtr->Config.BaseAddress,
+ XSDPS_CLK_CTRL_OFFSET);
+ XSdPs_WriteReg16(InstancePtr->Config.BaseAddress,
+ XSDPS_CLK_CTRL_OFFSET,
+ ClockReg | XSDPS_CC_SD_CLK_EN_MASK);
+
+ /* Wait for 1mSec */
+ (void)usleep(1000U);
+
+ /* Wait for CMD and DATA line to go high */
+ ReadReg = XSdPs_ReadReg(InstancePtr->Config.BaseAddress,
+ XSDPS_PRES_STATE_OFFSET);
+ while ((ReadReg & (XSDPS_PSR_CMD_SG_LVL_MASK | XSDPS_PSR_DAT30_SG_LVL_MASK))
+ != (XSDPS_PSR_CMD_SG_LVL_MASK | XSDPS_PSR_DAT30_SG_LVL_MASK)) {
+ ReadReg = XSdPs_ReadReg(InstancePtr->Config.BaseAddress,
+ XSDPS_PRES_STATE_OFFSET);
+ }
+
+RETURN_PATH:
+ return Status;
+}
+
+/*****************************************************************************/
+/**
+
+* This function does SD command generation.
+*
+* @param InstancePtr is a pointer to the instance to be worked on.
+* @param Cmd is the command to be sent.
+* @param Arg is the argument to be sent along with the command.
+* This could be address or any other information
+* @param BlkCnt - Block count passed by the user.
+*
+* @return
+* - XST_SUCCESS if initialization was successful
+* - XST_FAILURE if failure - could be because another transfer
+* is in progress or command or data inhibit is set
+*
+******************************************************************************/
+s32 XSdPs_CmdTransfer(XSdPs *InstancePtr, u32 Cmd, u32 Arg, u32 BlkCnt)
+{
+ u32 PresentStateReg;
+ u32 CommandReg;
+ u32 StatusReg;
+ s32 Status;
+
+ Xil_AssertNonvoid(InstancePtr != NULL);
+ Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+ /*
+ * Check the command inhibit to make sure no other
+ * command transfer is in progress
+ */
+ PresentStateReg = XSdPs_ReadReg(InstancePtr->Config.BaseAddress,
+ XSDPS_PRES_STATE_OFFSET);
+ if ((PresentStateReg & XSDPS_PSR_INHIBIT_CMD_MASK) != 0U) {
+ Status = XST_FAILURE;
+ goto RETURN_PATH;
+ }
+
+ /* Write block count register */
+ XSdPs_WriteReg16(InstancePtr->Config.BaseAddress,
+ XSDPS_BLK_CNT_OFFSET, (u16)BlkCnt);
+
+ XSdPs_WriteReg8(InstancePtr->Config.BaseAddress,
+ XSDPS_TIMEOUT_CTRL_OFFSET, 0xEU);
+
+ /* Write argument register */
+ XSdPs_WriteReg(InstancePtr->Config.BaseAddress,
+ XSDPS_ARGMT_OFFSET, Arg);
+
+ XSdPs_WriteReg16(InstancePtr->Config.BaseAddress,
+ XSDPS_NORM_INTR_STS_OFFSET, XSDPS_NORM_INTR_ALL_MASK);
+ XSdPs_WriteReg16(InstancePtr->Config.BaseAddress,
+ XSDPS_ERR_INTR_STS_OFFSET, XSDPS_ERROR_INTR_ALL_MASK);
+ /* Command register is set to trigger transfer of command */
+ CommandReg = XSdPs_FrameCmd(InstancePtr, Cmd);
+
+ /*
+ * Mask to avoid writing to reserved bits 31-30
+ * This is necessary because 0x80000000 is used by this software to
+ * distinguish between ACMD and CMD of same number
+ */
+ CommandReg = CommandReg & 0x3FFFU;
+
+ /*
+ * Check for data inhibit in case of command using DAT lines.
+ * For Tuning Commands DAT lines check can be ignored.
+ */
+ if ((Cmd != CMD21) && (Cmd != CMD19)) {
+ PresentStateReg = XSdPs_ReadReg(InstancePtr->Config.BaseAddress,
+ XSDPS_PRES_STATE_OFFSET);
+ if (((PresentStateReg & (XSDPS_PSR_INHIBIT_DAT_MASK |
+ XSDPS_PSR_INHIBIT_DAT_MASK)) != 0U) &&
+ ((CommandReg & XSDPS_DAT_PRESENT_SEL_MASK) != 0U)) {
+ Status = XST_FAILURE;
+ goto RETURN_PATH;
+ }
+ }
+
+ XSdPs_WriteReg(InstancePtr->Config.BaseAddress, XSDPS_XFER_MODE_OFFSET,
+ (CommandReg << 16) | TransferMode);
+
+ /* Polling for response for now */
+ do {
+ StatusReg = XSdPs_ReadReg16(InstancePtr->Config.BaseAddress,
+ XSDPS_NORM_INTR_STS_OFFSET);
+ if ((Cmd == CMD21) || (Cmd == CMD19)) {
+ if ((XSdPs_ReadReg16(InstancePtr->Config.BaseAddress,
+ XSDPS_NORM_INTR_STS_OFFSET) & XSDPS_INTR_BRR_MASK) != 0U){
+ XSdPs_WriteReg16(InstancePtr->Config.BaseAddress,
+ XSDPS_NORM_INTR_STS_OFFSET, XSDPS_INTR_BRR_MASK);
+ break;
+ }
+ }
+
+ if ((StatusReg & XSDPS_INTR_ERR_MASK) != 0U) {
+ Status = (s32)XSdPs_ReadReg16(InstancePtr->Config.BaseAddress,
+ XSDPS_ERR_INTR_STS_OFFSET);
+ if (((u32)Status & ~XSDPS_INTR_ERR_CT_MASK) == 0U) {
+ Status = XSDPS_CT_ERROR;
+ }
+ /* Write to clear error bits */
+ XSdPs_WriteReg16(InstancePtr->Config.BaseAddress,
+ XSDPS_ERR_INTR_STS_OFFSET,
+ XSDPS_ERROR_INTR_ALL_MASK);
+ goto RETURN_PATH;
+ }
+ } while((StatusReg & XSDPS_INTR_CC_MASK) == 0U);
+ /* Write to clear bit */
+ XSdPs_WriteReg16(InstancePtr->Config.BaseAddress,
+ XSDPS_NORM_INTR_STS_OFFSET,
+ XSDPS_INTR_CC_MASK);
+
+ Status = XST_SUCCESS;
+
+RETURN_PATH:
+ return Status;
+
+}
+
+/*****************************************************************************/
+/**
+* This function frames the Command register for a particular command.
+* Note that this generates only the command register value i.e.
+* the upper 16 bits of the transfer mode and command register.
+* This value is already shifted to be upper 16 bits and can be directly
+* OR'ed with transfer mode register value.
+*
+* @param InstancePtr is a pointer to the instance to be worked on.
+* @param Cmd is the Command to be sent.
+*
+* @return Command register value complete with response type and
+* data, CRC and index related flags.
+*
+******************************************************************************/
+u32 XSdPs_FrameCmd(XSdPs *InstancePtr, u32 Cmd)
+{
+ u32 RetVal;
+
+ RetVal = Cmd;
+
+ switch(Cmd) {
+ case CMD0:
+ RetVal |= RESP_NONE;
+ break;
+ case CMD1:
+ RetVal |= RESP_R3;
+ break;
+ case CMD2:
+ RetVal |= RESP_R2;
+ break;
+ case CMD3:
+ if (InstancePtr->CardType == XSDPS_CARD_SD) {
+ RetVal |= RESP_R6;
+ } else {
+ RetVal |= RESP_R1;
+ }
+ break;
+ case CMD4:
+ RetVal |= RESP_NONE;
+ break;
+ case CMD5:
+ RetVal |= RESP_R1B;
+ break;
+ case CMD6:
+ if (InstancePtr->CardType == XSDPS_CARD_SD) {
+ RetVal |= RESP_R1 | (u32)XSDPS_DAT_PRESENT_SEL_MASK;
+ } else {
+ RetVal |= RESP_R1B;
+ }
+ break;
+ case ACMD6:
+ RetVal |= RESP_R1;
+ break;
+ case CMD7:
+ RetVal |= RESP_R1;
+ break;
+ case CMD8:
+ if (InstancePtr->CardType == XSDPS_CARD_SD) {
+ RetVal |= RESP_R1;
+ } else {
+ RetVal |= RESP_R1 | (u32)XSDPS_DAT_PRESENT_SEL_MASK;
+ }
+ break;
+ case CMD9:
+ RetVal |= RESP_R2;
+ break;
+ case CMD11:
+ case CMD10:
+ case CMD12:
+ RetVal |= RESP_R1;
+ break;
+ case ACMD13:
+ RetVal |= RESP_R1 | (u32)XSDPS_DAT_PRESENT_SEL_MASK;
+ break;
+ case CMD16:
+ RetVal |= RESP_R1;
+ break;
+ case CMD17:
+ case CMD18:
+ case CMD19:
+ case CMD21:
+ RetVal |= RESP_R1 | (u32)XSDPS_DAT_PRESENT_SEL_MASK;
+ break;
+ case CMD23:
+ case ACMD23:
+ case CMD24:
+ case CMD25:
+ RetVal |= RESP_R1 | (u32)XSDPS_DAT_PRESENT_SEL_MASK;
+ break;
+ case ACMD41:
+ RetVal |= RESP_R3;
+ break;
+ case ACMD42:
+ RetVal |= RESP_R1;
+ break;
+ case ACMD51:
+ RetVal |= RESP_R1 | (u32)XSDPS_DAT_PRESENT_SEL_MASK;
+ break;
+ case CMD52:
+ case CMD55:
+ RetVal |= RESP_R1;
+ break;
+ case CMD58:
+ break;
+ default :
+ RetVal |= Cmd;
+ break;
+ }
+
+ return RetVal;
+}
+
+/*****************************************************************************/
+/**
+* This function performs SD read in polled mode.
+*
+* @param InstancePtr is a pointer to the instance to be worked on.
+* @param Arg is the address passed by the user that is to be sent as
+* argument along with the command.
+* @param BlkCnt - Block count passed by the user.
+* @param Buff - Pointer to the data buffer for a DMA transfer.
+*
+* @return
+* - XST_SUCCESS if initialization was successful
+* - XST_FAILURE if failure - could be because another transfer
+* is in progress or command or data inhibit is set
+*
+******************************************************************************/
+s32 XSdPs_ReadPolled(XSdPs *InstancePtr, u32 Arg, u32 BlkCnt, u8 *Buff)
+{
+ s32 Status;
+ u32 PresentStateReg;
+ u32 StatusReg;
+
+ if ((InstancePtr->HC_Version != XSDPS_HC_SPEC_V3) ||
+ ((InstancePtr->Host_Caps & XSDPS_CAPS_SLOT_TYPE_MASK)
+ != XSDPS_CAPS_EMB_SLOT)) {
+ if(InstancePtr->Config.CardDetect != 0U) {
+ /* Check status to ensure card is initialized */
+ PresentStateReg = XSdPs_ReadReg(InstancePtr->Config.BaseAddress,
+ XSDPS_PRES_STATE_OFFSET);
+ if ((PresentStateReg & XSDPS_PSR_CARD_INSRT_MASK) == 0x0U) {
+ Status = XST_FAILURE;
+ goto RETURN_PATH;
+ }
+ }
+ }
+
+ /* Set block size to 512 if not already set */
+ if( XSdPs_ReadReg(InstancePtr->Config.BaseAddress,
+ XSDPS_BLK_SIZE_OFFSET) != XSDPS_BLK_SIZE_512_MASK ) {
+ Status = XSdPs_SetBlkSize(InstancePtr,
+ XSDPS_BLK_SIZE_512_MASK);
+ if (Status != XST_SUCCESS) {
+ Status = XST_FAILURE;
+ goto RETURN_PATH;
+ }
+ }
+
+ if (InstancePtr->Dma64BitAddr >= ADDRESS_BEYOND_32BIT) {
+ XSdPs_SetupADMA2DescTbl64Bit(InstancePtr, BlkCnt);
+ } else {
+ XSdPs_SetupADMA2DescTbl(InstancePtr, BlkCnt, Buff);
+ if (InstancePtr->Config.IsCacheCoherent == 0U) {
+ Xil_DCacheInvalidateRange((INTPTR)Buff,
+ BlkCnt * XSDPS_BLK_SIZE_512_MASK);
+ }
+ }
+
+ if (BlkCnt == 1U) {
+ TransferMode = XSDPS_TM_BLK_CNT_EN_MASK |
+ XSDPS_TM_DAT_DIR_SEL_MASK | XSDPS_TM_DMA_EN_MASK;
+
+ /* Send single block read command */
+ Status = XSdPs_CmdTransfer(InstancePtr, CMD17, Arg, BlkCnt);
+ if (Status != XST_SUCCESS) {
+ Status = XST_FAILURE;
+ goto RETURN_PATH;
+ }
+ } else {
+ TransferMode = XSDPS_TM_AUTO_CMD12_EN_MASK |
+ XSDPS_TM_BLK_CNT_EN_MASK | XSDPS_TM_DAT_DIR_SEL_MASK |
+ XSDPS_TM_DMA_EN_MASK | XSDPS_TM_MUL_SIN_BLK_SEL_MASK;
+
+ /* Send multiple blocks read command */
+ Status = XSdPs_CmdTransfer(InstancePtr, CMD18, Arg, BlkCnt);
+ if (Status != XST_SUCCESS) {
+ Status = XST_FAILURE;
+ goto RETURN_PATH;
+ }
+ }
+
+ /* Check for transfer complete */
+ do {
+ StatusReg = XSdPs_ReadReg16(InstancePtr->Config.BaseAddress,
+ XSDPS_NORM_INTR_STS_OFFSET);
+ if ((StatusReg & XSDPS_INTR_ERR_MASK) != 0U) {
+ /* Write to clear error bits */
+ XSdPs_WriteReg16(InstancePtr->Config.BaseAddress,
+ XSDPS_ERR_INTR_STS_OFFSET,
+ XSDPS_ERROR_INTR_ALL_MASK);
+ Status = XST_FAILURE;
+ goto RETURN_PATH;
+ }
+ } while((StatusReg & XSDPS_INTR_TC_MASK) == 0U);
+
+ /* Write to clear bit */
+ XSdPs_WriteReg16(InstancePtr->Config.BaseAddress,
+ XSDPS_NORM_INTR_STS_OFFSET, XSDPS_INTR_TC_MASK);
+
+ if (InstancePtr->Config.IsCacheCoherent == 0U) {
+ Xil_DCacheInvalidateRange((INTPTR)Buff,
+ BlkCnt * XSDPS_BLK_SIZE_512_MASK);
+ }
+
+ Status = XST_SUCCESS;
+
+RETURN_PATH:
+ return Status;
+}
+
+/*****************************************************************************/
+/**
+* This function performs SD write in polled mode.
+*
+* @param InstancePtr is a pointer to the instance to be worked on.
+* @param Arg is the address passed by the user that is to be sent as
+* argument along with the command.
+* @param BlkCnt - Block count passed by the user.
+* @param Buff - Pointer to the data buffer for a DMA transfer.
+*
+* @return
+* - XST_SUCCESS if initialization was successful
+* - XST_FAILURE if failure - could be because another transfer
+* is in progress or command or data inhibit is set
+*
+******************************************************************************/
+s32 XSdPs_WritePolled(XSdPs *InstancePtr, u32 Arg, u32 BlkCnt, const u8 *Buff)
+{
+ s32 Status;
+ u32 PresentStateReg;
+ u32 StatusReg;
+
+ if ((InstancePtr->HC_Version != XSDPS_HC_SPEC_V3) ||
+ ((InstancePtr->Host_Caps & XSDPS_CAPS_SLOT_TYPE_MASK)
+ != XSDPS_CAPS_EMB_SLOT)) {
+ if(InstancePtr->Config.CardDetect != 0U) {
+ /* Check status to ensure card is initialized */
+ PresentStateReg = XSdPs_ReadReg(InstancePtr->Config.BaseAddress,
+ XSDPS_PRES_STATE_OFFSET);
+ if ((PresentStateReg & XSDPS_PSR_CARD_INSRT_MASK) == 0x0U) {
+ Status = XST_FAILURE;
+ goto RETURN_PATH;
+ }
+ }
+ }
+
+ /* Set block size to 512 if not already set */
+ if( XSdPs_ReadReg(InstancePtr->Config.BaseAddress,
+ XSDPS_BLK_SIZE_OFFSET) != XSDPS_BLK_SIZE_512_MASK ) {
+ Status = XSdPs_SetBlkSize(InstancePtr,
+ XSDPS_BLK_SIZE_512_MASK);
+ if (Status != XST_SUCCESS) {
+ Status = XST_FAILURE;
+ goto RETURN_PATH;
+ }
+
+ }
+
+ if (InstancePtr->Dma64BitAddr >= ADDRESS_BEYOND_32BIT) {
+ XSdPs_SetupADMA2DescTbl64Bit(InstancePtr, BlkCnt);
+ } else {
+ XSdPs_SetupADMA2DescTbl(InstancePtr, BlkCnt, Buff);
+ if (InstancePtr->Config.IsCacheCoherent == 0U) {
+ Xil_DCacheFlushRange((INTPTR)Buff,
+ BlkCnt * XSDPS_BLK_SIZE_512_MASK);
+ }
+ }
+
+ if (BlkCnt == 1U) {
+ TransferMode = XSDPS_TM_BLK_CNT_EN_MASK | XSDPS_TM_DMA_EN_MASK;
+
+ /* Send single block write command */
+ Status = XSdPs_CmdTransfer(InstancePtr, CMD24, Arg, BlkCnt);
+ if (Status != XST_SUCCESS) {
+ Status = XST_FAILURE;
+ goto RETURN_PATH;
+ }
+ } else {
+ TransferMode = XSDPS_TM_AUTO_CMD12_EN_MASK |
+ XSDPS_TM_BLK_CNT_EN_MASK |
+ XSDPS_TM_MUL_SIN_BLK_SEL_MASK | XSDPS_TM_DMA_EN_MASK;
+
+ /* Send multiple blocks write command */
+ Status = XSdPs_CmdTransfer(InstancePtr, CMD25, Arg, BlkCnt);
+ if (Status != XST_SUCCESS) {
+ Status = XST_FAILURE;
+ goto RETURN_PATH;
+ }
+ }
+
+ /*
+ * Check for transfer complete
+ * Polling for response for now
+ */
+ do {
+ StatusReg = XSdPs_ReadReg16(InstancePtr->Config.BaseAddress,
+ XSDPS_NORM_INTR_STS_OFFSET);
+ if ((StatusReg & XSDPS_INTR_ERR_MASK) != 0U) {
+ /* Write to clear error bits */
+ XSdPs_WriteReg16(InstancePtr->Config.BaseAddress,
+ XSDPS_ERR_INTR_STS_OFFSET,
+ XSDPS_ERROR_INTR_ALL_MASK);
+ Status = XST_FAILURE;
+ goto RETURN_PATH;
+ }
+ } while((StatusReg & XSDPS_INTR_TC_MASK) == 0U);
+
+ /* Write to clear bit */
+ XSdPs_WriteReg16(InstancePtr->Config.BaseAddress,
+ XSDPS_NORM_INTR_STS_OFFSET, XSDPS_INTR_TC_MASK);
+
+ Status = XST_SUCCESS;
+
+ RETURN_PATH:
+ return Status;
+}
+
+/*****************************************************************************/
+/**
+*
+* Selects card and sets default block size
+*
+*
+* @param InstancePtr is a pointer to the XSdPs instance.
+*
+* @return
+* - XST_SUCCESS if successful.
+* - XST_FAILURE if fail.
+*
+* @note None.
+*
+******************************************************************************/
+s32 XSdPs_Select_Card (XSdPs *InstancePtr)
+{
+ s32 Status;
+
+ /* Send CMD7 - Select card */
+ Status = XSdPs_CmdTransfer(InstancePtr, CMD7,
+ InstancePtr->RelCardAddr, 0U);
+ if (Status != XST_SUCCESS) {
+ Status = XST_FAILURE;
+ goto RETURN_PATH;
+ }
+
+RETURN_PATH:
+ return Status;
+
+}
+
+/*****************************************************************************/
+/**
+*
+* API to setup ADMA2 descriptor table for 64 Bit DMA
+*
+*
+* @param InstancePtr is a pointer to the XSdPs instance.
+* @param BlkCnt - block count.
+*
+* @return None
+*
+* @note None.
+*
+******************************************************************************/
+void XSdPs_SetupADMA2DescTbl64Bit(XSdPs *InstancePtr, u32 BlkCnt)
+{
+#ifdef __ICCARM__
+#pragma data_alignment = 32
+ static XSdPs_Adma2Descriptor64 Adma2_DescrTbl[32];
+#else
+ static XSdPs_Adma2Descriptor64 Adma2_DescrTbl[32] __attribute__ ((aligned(32)));
+#endif
+ u32 TotalDescLines;
+ u64 DescNum;
+ u32 BlkSize;
+
+ /* Setup ADMA2 - Write descriptor table and point ADMA SAR to it */
+ BlkSize = (u32)XSdPs_ReadReg16(InstancePtr->Config.BaseAddress,
+ XSDPS_BLK_SIZE_OFFSET) &
+ XSDPS_BLK_SIZE_MASK;
+
+ if((BlkCnt*BlkSize) < XSDPS_DESC_MAX_LENGTH) {
+
+ TotalDescLines = 1U;
+
+ } else {
+
+ TotalDescLines = ((BlkCnt*BlkSize) / XSDPS_DESC_MAX_LENGTH);
+ if (((BlkCnt * BlkSize) % XSDPS_DESC_MAX_LENGTH) != 0U) {
+ TotalDescLines += 1U;
+ }
+
+ }
+
+ for (DescNum = 0U; DescNum < (TotalDescLines-1); DescNum++) {
+ Adma2_DescrTbl[DescNum].Address =
+ InstancePtr->Dma64BitAddr +
+ (DescNum*XSDPS_DESC_MAX_LENGTH);
+ Adma2_DescrTbl[DescNum].Attribute =
+ XSDPS_DESC_TRAN | XSDPS_DESC_VALID;
+ Adma2_DescrTbl[DescNum].Length = 0U;
+ }
+
+ Adma2_DescrTbl[TotalDescLines-1].Address =
+ InstancePtr->Dma64BitAddr +
+ (DescNum*XSDPS_DESC_MAX_LENGTH);
+
+ Adma2_DescrTbl[TotalDescLines-1].Attribute =
+ XSDPS_DESC_TRAN | XSDPS_DESC_END | XSDPS_DESC_VALID;
+
+ Adma2_DescrTbl[TotalDescLines-1].Length =
+ (u16)((BlkCnt*BlkSize) - (u32)(DescNum*XSDPS_DESC_MAX_LENGTH));
+
+ XSdPs_WriteReg(InstancePtr->Config.BaseAddress, XSDPS_ADMA_SAR_OFFSET,
+ (u32)(UINTPTR)&(Adma2_DescrTbl[0]));
+
+ if (InstancePtr->Config.IsCacheCoherent == 0U) {
+ Xil_DCacheFlushRange((INTPTR)&(Adma2_DescrTbl[0]),
+ sizeof(XSdPs_Adma2Descriptor64) * 32U);
+ }
+
+ /* Clear the 64-Bit Address variable */
+ InstancePtr->Dma64BitAddr = 0U;
+
+}
+
+/*****************************************************************************/
+/**
+*
+* API to setup ADMA2 descriptor table for 32-bit DMA
+*
+*
+* @param InstancePtr is a pointer to the XSdPs instance.
+* @param BlkCnt - block count.
+* @param Buff pointer to data buffer.
+*
+* @return None
+*
+* @note None.
+*
+******************************************************************************/
+static void XSdPs_Setup32ADMA2DescTbl(XSdPs *InstancePtr, u32 BlkCnt, const u8 *Buff)
+{
+#ifdef __ICCARM__
+#pragma data_alignment = 32
+ static XSdPs_Adma2Descriptor32 Adma2_DescrTbl[32];
+#else
+ static XSdPs_Adma2Descriptor32 Adma2_DescrTbl[32] __attribute__ ((aligned(32)));
+#endif
+ u32 TotalDescLines;
+ u64 DescNum;
+ u32 BlkSize;
+
+ /* Setup ADMA2 - Write descriptor table and point ADMA SAR to it */
+ BlkSize = (u32)XSdPs_ReadReg16(InstancePtr->Config.BaseAddress,
+ XSDPS_BLK_SIZE_OFFSET) &
+ XSDPS_BLK_SIZE_MASK;
+
+ if((BlkCnt*BlkSize) < XSDPS_DESC_MAX_LENGTH) {
+ TotalDescLines = 1U;
+ } else {
+ TotalDescLines = ((BlkCnt*BlkSize) / XSDPS_DESC_MAX_LENGTH);
+ if (((BlkCnt * BlkSize) % XSDPS_DESC_MAX_LENGTH) != 0U) {
+ TotalDescLines += 1U;
+ }
+ }
+
+ for (DescNum = 0U; DescNum < (TotalDescLines-1); DescNum++) {
+ Adma2_DescrTbl[DescNum].Address =
+ (u32)((UINTPTR)Buff + (DescNum*XSDPS_DESC_MAX_LENGTH));
+ Adma2_DescrTbl[DescNum].Attribute =
+ XSDPS_DESC_TRAN | XSDPS_DESC_VALID;
+ Adma2_DescrTbl[DescNum].Length = 0U;
+ }
+
+ Adma2_DescrTbl[TotalDescLines-1].Address =
+ (u32)((UINTPTR)Buff + (DescNum*XSDPS_DESC_MAX_LENGTH));
+
+ Adma2_DescrTbl[TotalDescLines-1].Attribute =
+ XSDPS_DESC_TRAN | XSDPS_DESC_END | XSDPS_DESC_VALID;
+
+ Adma2_DescrTbl[TotalDescLines-1].Length =
+ (u16)((BlkCnt*BlkSize) - (u32)(DescNum*XSDPS_DESC_MAX_LENGTH));
+
+ XSdPs_WriteReg(InstancePtr->Config.BaseAddress, XSDPS_ADMA_SAR_OFFSET,
+ (u32)(UINTPTR)&(Adma2_DescrTbl[0]));
+
+ if (InstancePtr->Config.IsCacheCoherent == 0U) {
+ Xil_DCacheFlushRange((INTPTR)&(Adma2_DescrTbl[0]),
+ sizeof(XSdPs_Adma2Descriptor32) * 32U);
+ }
+}
+
+/*****************************************************************************/
+/**
+*
+* API to setup ADMA2 descriptor table for 64-bit DMA
+*
+*
+* @param InstancePtr is a pointer to the XSdPs instance.
+* @param BlkCnt - block count.
+* @param Buff pointer to data buffer.
+*
+* @return None
+*
+* @note None.
+*
+******************************************************************************/
+static void XSdPs_Setup64ADMA2DescTbl(XSdPs *InstancePtr, u32 BlkCnt, const u8 *Buff)
+{
+#ifdef __ICCARM__
+#pragma data_alignment = 32
+ static XSdPs_Adma2Descriptor64 Adma2_DescrTbl[32];
+#else
+ static XSdPs_Adma2Descriptor64 Adma2_DescrTbl[32] __attribute__ ((aligned(32)));
+#endif
+ u32 TotalDescLines;
+ u64 DescNum;
+ u32 BlkSize;
+
+ /* Setup ADMA2 - Write descriptor table and point ADMA SAR to it */
+ BlkSize = (u32)XSdPs_ReadReg16(InstancePtr->Config.BaseAddress,
+ XSDPS_BLK_SIZE_OFFSET) &
+ XSDPS_BLK_SIZE_MASK;
+
+ if((BlkCnt*BlkSize) < XSDPS_DESC_MAX_LENGTH) {
+ TotalDescLines = 1U;
+ } else {
+ TotalDescLines = ((BlkCnt*BlkSize) / XSDPS_DESC_MAX_LENGTH);
+ if (((BlkCnt * BlkSize) % XSDPS_DESC_MAX_LENGTH) != 0U) {
+ TotalDescLines += 1U;
+ }
+ }
+
+ for (DescNum = 0U; DescNum < (TotalDescLines-1); DescNum++) {
+ Adma2_DescrTbl[DescNum].Address =
+ ((UINTPTR)Buff + (DescNum*XSDPS_DESC_MAX_LENGTH));
+ Adma2_DescrTbl[DescNum].Attribute =
+ XSDPS_DESC_TRAN | XSDPS_DESC_VALID;
+ Adma2_DescrTbl[DescNum].Length = 0U;
+ }
+
+ Adma2_DescrTbl[TotalDescLines-1].Address =
+ (u64)((UINTPTR)Buff + (DescNum*XSDPS_DESC_MAX_LENGTH));
+
+ Adma2_DescrTbl[TotalDescLines-1].Attribute =
+ XSDPS_DESC_TRAN | XSDPS_DESC_END | XSDPS_DESC_VALID;
+
+ Adma2_DescrTbl[TotalDescLines-1].Length =
+ (u16)((BlkCnt*BlkSize) - (u32)(DescNum*XSDPS_DESC_MAX_LENGTH));
+
+#if defined(__aarch64__) || defined(__arch64__)
+ XSdPs_WriteReg(InstancePtr->Config.BaseAddress, XSDPS_ADMA_SAR_EXT_OFFSET,
+ (u32)((UINTPTR)(Adma2_DescrTbl)>>32U));
+#endif
+
+ XSdPs_WriteReg(InstancePtr->Config.BaseAddress, XSDPS_ADMA_SAR_OFFSET,
+ (u32)(UINTPTR)&(Adma2_DescrTbl[0]));
+
+ if (InstancePtr->Config.IsCacheCoherent == 0U) {
+ Xil_DCacheFlushRange((INTPTR)&(Adma2_DescrTbl[0]),
+ sizeof(XSdPs_Adma2Descriptor64) * 32U);
+ }
+}
+
+/*****************************************************************************/
+/**
+*
+* API to setup ADMA2 descriptor table
+*
+*
+* @param InstancePtr is a pointer to the XSdPs instance.
+* @param BlkCnt - block count.
+* @param Buff pointer to data buffer.
+*
+* @return None
+*
+* @note None.
+*
+******************************************************************************/
+void XSdPs_SetupADMA2DescTbl(XSdPs *InstancePtr, u32 BlkCnt, const u8 *Buff)
+{
+ if (InstancePtr->HC_Version == XSDPS_HC_SPEC_V3) {
+ XSdPs_Setup64ADMA2DescTbl(InstancePtr, BlkCnt, Buff);
+ } else {
+ XSdPs_Setup32ADMA2DescTbl(InstancePtr, BlkCnt, Buff);
+ }
+}
+
+/*****************************************************************************/
+/**
+* Mmc initialization is done in this function
+*
+*
+* @param InstancePtr is a pointer to the instance to be worked on.
+*
+* @return
+* - XST_SUCCESS if initialization was successful
+* - XST_FAILURE if failure - could be because
+* a) MMC is already initialized
+* b) There is no card inserted
+* c) One of the steps (commands) in the initialization
+* cycle failed
+* @note This function initializes the SD card by following its
+* initialization and identification state diagram.
+* CMD0 is sent to reset card.
+* CMD1 sent to identify voltage and high capacity support
+* CMD2 and CMD3 are sent to obtain Card ID and
+* Relative card address respectively.
+* CMD9 is sent to read the card specific data.
+*
+******************************************************************************/
+s32 XSdPs_MmcCardInitialize(XSdPs *InstancePtr)
+{
+ u32 PresentStateReg;
+ s32 Status;
+ u32 RespOCR;
+ u32 CSD[4];
+ u32 BlkLen, DeviceSize, Mult;
+
+ Xil_AssertNonvoid(InstancePtr != NULL);
+ Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+ if ((InstancePtr->HC_Version != XSDPS_HC_SPEC_V3) ||
+ ((InstancePtr->Host_Caps & XSDPS_CAPS_SLOT_TYPE_MASK)
+ != XSDPS_CAPS_EMB_SLOT)) {
+ if(InstancePtr->Config.CardDetect != 0U) {
+ /*
+ * Check the present state register to make sure
+ * card is inserted and detected by host controller
+ */
+ PresentStateReg = XSdPs_ReadReg(InstancePtr->Config.BaseAddress,
+ XSDPS_PRES_STATE_OFFSET);
+ if ((PresentStateReg & XSDPS_PSR_CARD_INSRT_MASK) == 0U) {
+ Status = XST_FAILURE;
+ goto RETURN_PATH;
+ }
+ }
+ }
+
+ /* CMD0 no response expected */
+ Status = XSdPs_CmdTransfer(InstancePtr, CMD0, 0U, 0U);
+ if (Status != XST_SUCCESS) {
+ Status = XST_FAILURE;
+ goto RETURN_PATH;
+ }
+
+ RespOCR = 0U;
+ /* Send CMD1 while card is still busy with power up */
+ while ((RespOCR & XSDPS_RESPOCR_READY) == 0U) {
+
+ /* Host High Capacity support & High volage window */
+ Status = XSdPs_CmdTransfer(InstancePtr, CMD1,
+ XSDPS_ACMD41_HCS | XSDPS_CMD1_HIGH_VOL, 0U);
+ if (Status != XST_SUCCESS) {
+ Status = XST_FAILURE;
+ goto RETURN_PATH;
+ }
+
+ /* Response with card capacity */
+ RespOCR = XSdPs_ReadReg(InstancePtr->Config.BaseAddress,
+ XSDPS_RESP0_OFFSET);
+
+ }
+
+ /* Update HCS support flag based on card capacity response */
+ if ((RespOCR & XSDPS_ACMD41_HCS) != 0U) {
+ InstancePtr->HCS = 1U;
+ }
+
+ /* CMD2 for Card ID */
+ Status = XSdPs_CmdTransfer(InstancePtr, CMD2, 0U, 0U);
+ if (Status != XST_SUCCESS) {
+ Status = XST_FAILURE;
+ goto RETURN_PATH;
+ }
+
+ InstancePtr->CardID[0] =
+ XSdPs_ReadReg16(InstancePtr->Config.BaseAddress,
+ XSDPS_RESP0_OFFSET);
+ InstancePtr->CardID[1] =
+ XSdPs_ReadReg16(InstancePtr->Config.BaseAddress,
+ XSDPS_RESP1_OFFSET);
+ InstancePtr->CardID[2] =
+ XSdPs_ReadReg16(InstancePtr->Config.BaseAddress,
+ XSDPS_RESP2_OFFSET);
+ InstancePtr->CardID[3] =
+ XSdPs_ReadReg16(InstancePtr->Config.BaseAddress,
+ XSDPS_RESP3_OFFSET);
+
+ /* Set relative card address */
+ InstancePtr->RelCardAddr = 0x12340000U;
+ Status = XSdPs_CmdTransfer(InstancePtr, CMD3, (InstancePtr->RelCardAddr), 0U);
+ if (Status != XST_SUCCESS) {
+ Status = XST_FAILURE;
+ goto RETURN_PATH;
+ }
+
+ Status = XSdPs_CmdTransfer(InstancePtr, CMD9, (InstancePtr->RelCardAddr), 0U);
+ if (Status != XST_SUCCESS) {
+ Status = XST_FAILURE;
+ goto RETURN_PATH;
+ }
+
+ /*
+ * Card specific data is read.
+ * Currently not used for any operation.
+ */
+ CSD[0] = XSdPs_ReadReg(InstancePtr->Config.BaseAddress,
+ XSDPS_RESP0_OFFSET);
+ CSD[1] = XSdPs_ReadReg(InstancePtr->Config.BaseAddress,
+ XSDPS_RESP1_OFFSET);
+ CSD[2] = XSdPs_ReadReg(InstancePtr->Config.BaseAddress,
+ XSDPS_RESP2_OFFSET);
+ CSD[3] = XSdPs_ReadReg(InstancePtr->Config.BaseAddress,
+ XSDPS_RESP3_OFFSET);
+
+ InstancePtr->Card_Version = (u8)((u32)(CSD[3] & CSD_SPEC_VER_MASK) >>18U);
+
+ /* Calculating the memory capacity */
+ BlkLen = 1U << ((u32)(CSD[2] & READ_BLK_LEN_MASK) >> 8U);
+ Mult = 1U << ((u32)((CSD[1] & C_SIZE_MULT_MASK) >> 7U) + 2U);
+ DeviceSize = (CSD[1] & C_SIZE_LOWER_MASK) >> 22U;
+ DeviceSize |= (CSD[2] & C_SIZE_UPPER_MASK) << 10U;
+ DeviceSize = (DeviceSize + 1U) * Mult;
+ DeviceSize = DeviceSize * BlkLen;
+
+ InstancePtr->SectorCount = (DeviceSize/XSDPS_BLK_SIZE_512_MASK);
+
+ Status = XST_SUCCESS;
+
+RETURN_PATH:
+ return Status;
+
+}
+
+/*****************************************************************************/
+/**
+*
+* API to idle the SDIO Interface
+*
+*
+* @param InstancePtr is a pointer to the XSdPs instance.
+*
+* @return None
+*
+* @note None.
+*
+******************************************************************************/
+void XSdPs_Idle(XSdPs *InstancePtr)
+{
+ u32 Timeout = MAX_TIMEOUT;
+ u32 PresentStateReg;
+ u32 StatusReg;
+ u8 RegVal;
+
+ PresentStateReg = XSdPs_ReadReg8(InstancePtr->Config.BaseAddress,
+ XSDPS_PRES_STATE_OFFSET);
+ /* Check for Card Present */
+ if ((PresentStateReg & XSDPS_PSR_CARD_INSRT_MASK) != 0U) {
+ /* Check for SD idle */
+ do {
+ StatusReg = XSdPs_ReadReg8(InstancePtr->Config.BaseAddress,
+ XSDPS_PRES_STATE_OFFSET);
+ Timeout = Timeout - 1;
+ } while (((StatusReg & (XSDPS_PSR_INHIBIT_CMD_MASK
+ | XSDPS_PSR_INHIBIT_DAT_MASK
+ | XSDPS_PSR_DAT_ACTIVE_MASK)) != 0U)
+ && (Timeout != 0U));
+ }
+ /* Reset the eMMC card */
+ if (InstancePtr->CardType == XSDPS_CHIP_EMMC) {
+ RegVal = XSdPs_ReadReg8(InstancePtr->Config.BaseAddress,
+ XSDPS_POWER_CTRL_OFFSET);
+ XSdPs_WriteReg8(InstancePtr->Config.BaseAddress,
+ XSDPS_POWER_CTRL_OFFSET,
+ RegVal | XSDPS_PC_EMMC_HW_RST_MASK);
+ usleep(1000);
+ RegVal = XSdPs_ReadReg8(InstancePtr->Config.BaseAddress,
+ XSDPS_POWER_CTRL_OFFSET);
+ XSdPs_WriteReg8(InstancePtr->Config.BaseAddress,
+ XSDPS_POWER_CTRL_OFFSET,
+ RegVal & ~XSDPS_PC_EMMC_HW_RST_MASK);
+ }
+
+ /* Disable bus power */
+ XSdPs_WriteReg8(InstancePtr->Config.BaseAddress,
+ XSDPS_POWER_CTRL_OFFSET, 0);
+
+ /* Delay to disable bus power to card */
+ (void)usleep(1000U);
+
+ /* "Software reset for all" is initiated */
+ XSdPs_WriteReg8(InstancePtr->Config.BaseAddress,
+ XSDPS_SW_RST_OFFSET, XSDPS_SWRST_ALL_MASK);
+
+ Timeout = MAX_TIMEOUT;
+ /* Proceed with initialization only after reset is complete */
+ RegVal = XSdPs_ReadReg8(InstancePtr->Config.BaseAddress,
+ XSDPS_SW_RST_OFFSET);
+ Timeout = Timeout - 1;
+ while (((RegVal & XSDPS_SWRST_ALL_MASK) != 0U) && (Timeout != 0U)) {
+ RegVal = XSdPs_ReadReg8(InstancePtr->Config.BaseAddress,
+ XSDPS_SW_RST_OFFSET);
+ Timeout = Timeout - 1;
+ }
+}
+/** @} */
diff --git a/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/sdps_v3_8/src/xsdps.h b/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/sdps_v3_8/src/xsdps.h
new file mode 100644
index 0000000..24cc271
--- /dev/null
+++ b/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/sdps_v3_8/src/xsdps.h
@@ -0,0 +1,282 @@
+/******************************************************************************
+*
+* Copyright (C) 2013 - 2019 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+* THE SOFTWARE.
+*
+*
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xsdps.h
+* @addtogroup sdps_v3_8
+* @{
+* @details
+*
+* This file contains the implementation of XSdPs driver.
+* This driver is used initialize read from and write to the SD card.
+* Features such as switching bus width to 4-bit and switching to high speed,
+* changing clock frequency, block size etc. are supported.
+* SD 2.0 uses 1/4 bus width and speeds of 25/50KHz. Initialization, however
+* is done using 1-bit bus width and 400KHz clock frequency.
+* SD commands are classified as broadcast and addressed. Commands can be
+* those with response only (using only command line) or
+* response + data (using command and data lines).
+* Only one command can be sent at a time. During a data transfer however,
+* when dsta lines are in use, certain commands (which use only the command
+* line) can be sent, most often to obtain status.
+* This driver does not support multi card slots at present.
+*
+* Initialization:
+* This includes initialization on the host controller side to select
+* clock frequency, bus power and default transfer related parameters.
+* The default voltage is 3.3V.
+* On the SD card side, the initialization and identification state diagram is
+* implemented. This resets the card, gives it a unique address/ID and
+* identifies key card related specifications.
+*
+* Data transfer:
+* The SD card is put in transfer state to read from or write to it.
+* The default block size is 512 bytes and if supported,
+* default bus width is 4-bit and bus speed is High speed.
+* The read and write functions are implemented in polled mode using ADMA2.
+*
+* At any point, when key parameters such as block size or
+* clock/speed or bus width are modified, this driver takes care of
+* maintaining the same selection on host and card.
+* All error bits in host controller are monitored by the driver and in the
+* event one of them is set, driver will clear the interrupt status and
+* communicate failure to the upper layer.
+*
+* File system use:
+* This driver can be used with xilffs library to read and write files to SD.
+* (Please refer to procedure in diskio.c). The file system read/write example
+* in polled mode can used for reference.
+*
+* There is no example for using SD driver without file system at present.
+* However, the driver can be used without the file system. The glue layer
+* in filesystem can be used as reference for the same. The block count
+* passed to the read/write function in one call is limited by the ADMA2
+* descriptor table and hence care will have to be taken to call read/write
+* API's in a loop for large file sizes.
+*
+* Interrupt mode is not supported because it offers no improvement when used
+* with file system.
+*
+* eMMC support:
+* SD driver supports SD and eMMC based on the "enable MMC" parameter in SDK.
+* The features of eMMC supported by the driver will depend on those supported
+* by the host controller. The current driver supports read/write on eMMC card
+* using 4-bit and high speed mode currently.
+*
+* Features not supported include - card write protect, password setting,
+* lock/unlock, interrupts, SDMA mode, programmed I/O mode and
+* 64-bit addressed ADMA2, erase/pre-erase commands.
+*
+* <pre>
+* MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ----- --- -------- -----------------------------------------------
+* 1.00a hk/sg 10/17/13 Initial release
+* 2.0 hk 03/07/14 Version number revised.
+* 2.1 hk 04/18/14 Increase sleep for eMMC switch command.
+* Add sleep for microblaze designs. CR# 781117.
+* 2.2 hk 07/28/14 Make changes to enable use of data cache.
+* 2.3 sk 09/23/14 Send command for relative card address
+* when re-initialization is done.CR# 819614.
+* Use XSdPs_Change_ClkFreq API whenever changing
+* clock.CR# 816586.
+* 2.4 sk 12/04/14 Added support for micro SD without
+* WP/CD. CR# 810655.
+* Checked for DAT Inhibit mask instead of CMD
+* Inhibit mask in Cmd Transfer API.
+* Added Support for SD Card v1.0
+* 2.5 sg 07/09/15 Added SD 3.0 features
+* kvn 07/15/15 Modified the code according to MISRAC-2012.
+* 2.6 sk 10/12/15 Added support for SD card v1.0 CR# 840601.
+* 2.7 sk 11/24/15 Considered the slot type befoe checking CD/WP pins.
+* sk 12/10/15 Added support for MMC cards.
+* 01/08/16 Added workaround for issue in auto tuning mode
+* of SDR50, SDR104 and HS200.
+* sk 02/16/16 Corrected the Tuning logic.
+* sk 03/01/16 Removed Bus Width check for eMMC. CR# 938311.
+* 2.8 sk 04/20/16 Added new workaround for auto tuning.
+* 05/03/16 Standard Speed for SD to 19MHz in ZynqMPSoC. CR#951024
+* 3.0 sk 06/09/16 Added support for mkfs to calculate sector count.
+* sk 07/16/16 Added support for UHS modes.
+* sk 07/07/16 Used usleep API for both arm and microblaze.
+* sk 07/16/16 Added Tap delays accordingly to different SD/eMMC
+* operating modes.
+* sk 08/13/16 Removed sleep.h from xsdps.h as a temporary fix for
+* CR#956899.
+* 3.1 mi 09/07/16 Removed compilation warnings with extra compiler flags.
+* sk 10/13/16 Reduced the delay during power cycle to 1ms as per spec
+* sk 10/19/16 Used emmc_hwreset pin to reset eMMC.
+* sk 11/07/16 Enable Rst_n bit in ext_csd reg if not enabled.
+* sk 11/16/16 Issue DLL reset at 31 iteration to load new zero value.
+* 3.2 sk 11/30/16 Modified the voltage switching sequence as per spec.
+* sk 02/01/17 Added HSD and DDR mode support for eMMC.
+* sk 02/01/17 Consider bus width parameter from design for switching
+* vns 02/09/17 Added ARMA53_32 support for ZynqMP CR#968397
+* sk 03/20/17 Add support for EL1 non-secure mode.
+* 3.3 mn 05/17/17 Add support for 64bit DMA addressing
+* mn 08/07/17 Modify driver to support 64-bit DMA in arm64 only
+* mn 08/17/17 Enabled CCI support for A53 by adding cache coherency
+* information.
+* mn 09/06/17 Resolved compilation errors with IAR toolchain
+* 3.6 mn 08/01/18 Add support for using 64Bit DMA with 32-Bit Processor
+* 3.7 mn 02/01/19 Add support for idling of SDIO
+* 3.8 mn 04/12/19 Modified TapDelay code for supporting ZynqMP and Versal
+* mn 09/17/19 Modified ADMA handling API for 32bit and 64bit addresses
+*
+* </pre>
+*
+******************************************************************************/
+
+
+#ifndef SDPS_H_
+#define SDPS_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include "xil_printf.h"
+#include "xil_cache.h"
+#include "xstatus.h"
+#include "xsdps_hw.h"
+#include "xplatform_info.h"
+#include <string.h>
+
+/************************** Constant Definitions *****************************/
+
+#define XSDPS_CT_ERROR 0x2L /**< Command timeout flag */
+#define MAX_TUNING_COUNT 40U /**< Maximum Tuning count */
+#define MAX_TIMEOUT 0x1FFFFFFFU /**< Maximum Timeout */
+
+/**************************** Type Definitions *******************************/
+
+typedef void (*XSdPs_ConfigTap) (u32 Bank, u32 DeviceId, u32 CardType);
+
+/**
+ * This typedef contains configuration information for the device.
+ */
+typedef struct {
+ u16 DeviceId; /**< Unique ID of device */
+ u32 BaseAddress; /**< Base address of the device */
+ u32 InputClockHz; /**< Input clock frequency */
+ u32 CardDetect; /**< Card Detect */
+ u32 WriteProtect; /**< Write Protect */
+ u32 BusWidth; /**< Bus Width */
+ u32 BankNumber; /**< MIO Bank selection for SD */
+ u32 HasEMIO; /**< If SD is connected to EMIO */
+ u8 IsCacheCoherent; /**< If SD is Cache Coherent or not */
+} XSdPs_Config;
+
+/* ADMA2 32-Bit descriptor table */
+typedef struct {
+ u16 Attribute; /**< Attributes of descriptor */
+ u16 Length; /**< Length of current dma transfer */
+ u32 Address; /**< Address of current dma transfer */
+#ifdef __ICCARM__
+#pragma data_alignment = 32
+} XSdPs_Adma2Descriptor32;
+#else
+} __attribute__((__packed__))XSdPs_Adma2Descriptor32;
+#endif
+
+/* ADMA2 64-Bit descriptor table */
+typedef struct {
+ u16 Attribute; /**< Attributes of descriptor */
+ u16 Length; /**< Length of current dma transfer */
+ u64 Address; /**< Address of current dma transfer */
+#ifdef __ICCARM__
+#pragma data_alignment = 32
+} XSdPs_Adma2Descriptor64;
+#else
+} __attribute__((__packed__))XSdPs_Adma2Descriptor64;
+#endif
+
+/**
+ * The XSdPs driver instance data. The user is required to allocate a
+ * variable of this type for every SD device in the system. A pointer
+ * to a variable of this type is then passed to the driver API functions.
+ */
+typedef struct {
+ XSdPs_Config Config; /**< Configuration structure */
+ u32 IsReady; /**< Device is initialized and ready */
+ u32 Host_Caps; /**< Capabilities of host controller */
+ u32 Host_CapsExt; /**< Extended Capabilities */
+ u32 HCS; /**< High capacity support in card */
+ u8 CardType; /**< Type of card - SD/MMC/eMMC */
+ u8 Card_Version; /**< Card version */
+ u8 HC_Version; /**< Host controller version */
+ u8 BusWidth; /**< Current operating bus width */
+ u32 BusSpeed; /**< Current operating bus speed */
+ u8 Switch1v8; /**< 1.8V Switch support */
+ u32 CardID[4]; /**< Card ID Register */
+ u32 RelCardAddr; /**< Relative Card Address */
+ u32 CardSpecData[4]; /**< Card Specific Data Register */
+ u32 SectorCount; /**< Sector Count */
+ u32 SdCardConfig; /**< Sd Card Configuration Register */
+ u32 Mode; /**< Bus Speed Mode */
+ u32 OTapDelay; /**< Output Tap Delay */
+ u32 ITapDelay; /**< Input Tap Delay */
+ u64 Dma64BitAddr; /**< 64 Bit DMA Address */
+} XSdPs;
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/************************** Function Prototypes ******************************/
+XSdPs_Config *XSdPs_LookupConfig(u16 DeviceId);
+s32 XSdPs_CfgInitialize(XSdPs *InstancePtr, XSdPs_Config *ConfigPtr,
+ u32 EffectiveAddr);
+s32 XSdPs_SdCardInitialize(XSdPs *InstancePtr);
+s32 XSdPs_ReadPolled(XSdPs *InstancePtr, u32 Arg, u32 BlkCnt, u8 *Buff);
+s32 XSdPs_WritePolled(XSdPs *InstancePtr, u32 Arg, u32 BlkCnt, const u8 *Buff);
+s32 XSdPs_SetBlkSize(XSdPs *InstancePtr, u16 BlkSize);
+s32 XSdPs_Select_Card (XSdPs *InstancePtr);
+s32 XSdPs_Change_ClkFreq(XSdPs *InstancePtr, u32 SelFreq);
+s32 XSdPs_Change_BusWidth(XSdPs *InstancePtr);
+s32 XSdPs_Change_BusSpeed(XSdPs *InstancePtr);
+s32 XSdPs_Get_BusWidth(XSdPs *InstancePtr, u8 *ReadBuff);
+s32 XSdPs_Get_BusSpeed(XSdPs *InstancePtr, u8 *ReadBuff);
+s32 XSdPs_Get_Status(XSdPs *InstancePtr, u8 *SdStatReg);
+s32 XSdPs_Pullup(XSdPs *InstancePtr);
+s32 XSdPs_MmcCardInitialize(XSdPs *InstancePtr);
+s32 XSdPs_CardInitialize(XSdPs *InstancePtr);
+s32 XSdPs_Get_Mmc_ExtCsd(XSdPs *InstancePtr, u8 *ReadBuff);
+s32 XSdPs_Set_Mmc_ExtCsd(XSdPs *InstancePtr, u32 Arg);
+void XSdPs_Idle(XSdPs *InstancePtr);
+#if defined (ARMR5) || defined (__aarch64__) || defined (ARMA53_32) || defined (__MICROBLAZE__)
+void XSdPs_Identify_UhsMode(XSdPs *InstancePtr, u8 *ReadBuff);
+void XSdPs_ddr50_tapdelay(u32 Bank, u32 DeviceId, u32 CardType);
+void XSdPs_hsd_sdr25_tapdelay(u32 Bank, u32 DeviceId, u32 CardType);
+void XSdPs_sdr104_hs200_tapdelay(u32 Bank, u32 DeviceId, u32 CardType);
+#endif
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* SD_H_ */
+/** @} */
diff --git a/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/sdps_v3_8/src/xsdps_g.c b/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/sdps_v3_8/src/xsdps_g.c
new file mode 100644
index 0000000..366b9d7
--- /dev/null
+++ b/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/sdps_v3_8/src/xsdps_g.c
@@ -0,0 +1,54 @@
+
+/*******************************************************************
+*
+* CAUTION: This file is automatically generated by HSI.
+* Version: 2019.2
+* DO NOT EDIT.
+*
+* Copyright (C) 2010-2021 Xilinx, Inc. All Rights Reserved.*
+*Permission is hereby granted, free of charge, to any person obtaining a copy
+*of this software and associated documentation files (the Software), to deal
+*in the Software without restriction, including without limitation the rights
+*to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+*copies of the Software, and to permit persons to whom the Software is
+*furnished to do so, subject to the following conditions:
+*
+*The above copyright notice and this permission notice shall be included in
+*all copies or substantial portions of the Software.
+*
+*THE SOFTWARE IS PROVIDED AS IS, WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+*IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+*FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+*THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+*WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT
+*OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+*
+
+*
+* Description: Driver configuration
+*
+*******************************************************************/
+
+#include "xparameters.h"
+#include "xsdps.h"
+
+/*
+* The configuration table for devices
+*/
+
+XSdPs_Config XSdPs_ConfigTable[XPAR_XSDPS_NUM_INSTANCES] =
+{
+ {
+ XPAR_PS7_SD_0_DEVICE_ID,
+ XPAR_PS7_SD_0_BASEADDR,
+ XPAR_PS7_SD_0_SDIO_CLK_FREQ_HZ,
+ XPAR_PS7_SD_0_HAS_CD,
+ XPAR_PS7_SD_0_HAS_WP,
+ XPAR_PS7_SD_0_BUS_WIDTH,
+ XPAR_PS7_SD_0_MIO_BANK,
+ XPAR_PS7_SD_0_HAS_EMIO,
+ XPAR_PS7_SD_0_IS_CACHE_COHERENT
+ }
+};
+
+
diff --git a/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/sdps_v3_8/src/xsdps_hw.h b/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/sdps_v3_8/src/xsdps_hw.h
new file mode 100644
index 0000000..8097d04
--- /dev/null
+++ b/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/sdps_v3_8/src/xsdps_hw.h
@@ -0,0 +1,1317 @@
+/******************************************************************************
+*
+* Copyright (C) 2013 - 2019 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+* THE SOFTWARE.
+*
+*
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xsdps_hw.h
+* @addtogroup sdps_v3_8
+* @{
+*
+* This header file contains the identifiers and basic HW access driver
+* functions (or macros) that can be used to access the device. Other driver
+* functions are defined in xsdps.h.
+*
+* <pre>
+* MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ----- --- -------- -----------------------------------------------
+* 1.00a hk/sg 10/17/13 Initial release
+* 2.5 sg 07/09/15 Added SD 3.0 features
+* kvn 07/15/15 Modified the code according to MISRAC-2012.
+* 2.7 sk 12/10/15 Added support for MMC cards.
+* sk 03/02/16 Configured the Tap Delay values for eMMC HS200 mode.
+* 2.8 sk 04/20/16 Added new workaround for auto tuning.
+* 3.0 sk 06/09/16 Added support for mkfs to calculate sector count.
+* sk 07/16/16 Added support for UHS modes.
+* sk 07/16/16 Added Tap delays accordingly to different SD/eMMC
+* operating modes.
+* 3.1 sk 11/07/16 Enable Rst_n bit in ext_csd reg if not enabled.
+* 3.2 sk 03/20/17 Add support for EL1 non-secure mode.
+* 3.3 mn 08/22/17 Updated for Word Access System support
+* mn 09/06/17 Added support for ARMCC toolchain
+* 3.4 mn 01/22/18 Separated out SDR104 and HS200 clock defines
+* 3.6 mn 07/06/18 Fix Doxygen warnings for sdps driver
+* 3.8 mn 04/12/19 Modified TapDelay code for supporting ZynqMP and Versal
+* mn 05/21/19 Set correct tap delays for Versal
+* mn 05/21/19 Disable DLL Reset code for Versal
+* mn 05/21/19 Enable SD UHS Mode support by default for Versal
+* mn 07/03/19 Update Input Tap Delays for Versal
+*
+* </pre>
+*
+******************************************************************************/
+
+#ifndef SD_HW_H_
+#define SD_HW_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/***************************** Include Files *********************************/
+
+#include "xil_types.h"
+#include "xil_assert.h"
+#include "xil_io.h"
+#include "xparameters.h"
+
+/************************** Constant Definitions *****************************/
+
+/* Enable UHS Mode support by default for Versal */
+#ifdef versal
+#define UHS_MODE_ENABLE
+#endif
+/** @name Register Map
+ *
+ * Register offsets from the base address of an SD device.
+ * @{
+ */
+
+#define XSDPS_SDMA_SYS_ADDR_OFFSET 0x00U /**< SDMA System Address
+ Register */
+#define XSDPS_SDMA_SYS_ADDR_LO_OFFSET XSDPS_SDMA_SYS_ADDR_OFFSET
+ /**< SDMA System Address
+ Low Register */
+#define XSDPS_ARGMT2_LO_OFFSET 0x00U /**< Argument2 Low Register */
+#define XSDPS_SDMA_SYS_ADDR_HI_OFFSET 0x02U /**< SDMA System Address
+ High Register */
+#define XSDPS_ARGMT2_HI_OFFSET 0x02U /**< Argument2 High Register */
+
+#define XSDPS_BLK_SIZE_OFFSET 0x04U /**< Block Size Register */
+#define XSDPS_BLK_CNT_OFFSET 0x06U /**< Block Count Register */
+#define XSDPS_ARGMT_OFFSET 0x08U /**< Argument Register */
+#define XSDPS_ARGMT1_LO_OFFSET XSDPS_ARGMT_OFFSET
+ /**< Argument1 Register */
+#define XSDPS_ARGMT1_HI_OFFSET 0x0AU /**< Argument1 Register */
+
+#define XSDPS_XFER_MODE_OFFSET 0x0CU /**< Transfer Mode Register */
+#define XSDPS_CMD_OFFSET 0x0EU /**< Command Register */
+#define XSDPS_RESP0_OFFSET 0x10U /**< Response0 Register */
+#define XSDPS_RESP1_OFFSET 0x14U /**< Response1 Register */
+#define XSDPS_RESP2_OFFSET 0x18U /**< Response2 Register */
+#define XSDPS_RESP3_OFFSET 0x1CU /**< Response3 Register */
+#define XSDPS_BUF_DAT_PORT_OFFSET 0x20U /**< Buffer Data Port */
+#define XSDPS_PRES_STATE_OFFSET 0x24U /**< Present State */
+#define XSDPS_HOST_CTRL1_OFFSET 0x28U /**< Host Control 1 */
+#define XSDPS_POWER_CTRL_OFFSET 0x29U /**< Power Control */
+#define XSDPS_BLK_GAP_CTRL_OFFSET 0x2AU /**< Block Gap Control */
+#define XSDPS_WAKE_UP_CTRL_OFFSET 0x2BU /**< Wake Up Control */
+#define XSDPS_CLK_CTRL_OFFSET 0x2CU /**< Clock Control */
+#define XSDPS_TIMEOUT_CTRL_OFFSET 0x2EU /**< Timeout Control */
+#define XSDPS_SW_RST_OFFSET 0x2FU /**< Software Reset */
+#define XSDPS_NORM_INTR_STS_OFFSET 0x30U /**< Normal Interrupt
+ Status Register */
+#define XSDPS_ERR_INTR_STS_OFFSET 0x32U /**< Error Interrupt
+ Status Register */
+#define XSDPS_NORM_INTR_STS_EN_OFFSET 0x34U /**< Normal Interrupt
+ Status Enable Register */
+#define XSDPS_ERR_INTR_STS_EN_OFFSET 0x36U /**< Error Interrupt
+ Status Enable Register */
+#define XSDPS_NORM_INTR_SIG_EN_OFFSET 0x38U /**< Normal Interrupt
+ Signal Enable Register */
+#define XSDPS_ERR_INTR_SIG_EN_OFFSET 0x3AU /**< Error Interrupt
+ Signal Enable Register */
+
+#define XSDPS_AUTO_CMD12_ERR_STS_OFFSET 0x3CU /**< Auto CMD12 Error Status
+ Register */
+#define XSDPS_HOST_CTRL2_OFFSET 0x3EU /**< Host Control2 Register */
+#define XSDPS_CAPS_OFFSET 0x40U /**< Capabilities Register */
+#define XSDPS_CAPS_EXT_OFFSET 0x44U /**< Capabilities Extended */
+#define XSDPS_MAX_CURR_CAPS_OFFSET 0x48U /**< Maximum Current
+ Capabilities Register */
+#define XSDPS_MAX_CURR_CAPS_EXT_OFFSET 0x4CU /**< Maximum Current
+ Capabilities Ext Register */
+#define XSDPS_FE_ERR_INT_STS_OFFSET 0x52U /**< Force Event for
+ Error Interrupt Status */
+#define XSDPS_FE_AUTO_CMD12_EIS_OFFSET 0x50U /**< Auto CM12 Error Interrupt
+ Status Register */
+#define XSDPS_ADMA_ERR_STS_OFFSET 0x54U /**< ADMA Error Status
+ Register */
+#define XSDPS_ADMA_SAR_OFFSET 0x58U /**< ADMA System Address
+ Register */
+#define XSDPS_ADMA_SAR_EXT_OFFSET 0x5CU /**< ADMA System Address
+ Extended Register */
+#define XSDPS_PRE_VAL_1_OFFSET 0x60U /**< Preset Value Register */
+#define XSDPS_PRE_VAL_2_OFFSET 0x64U /**< Preset Value Register */
+#define XSDPS_PRE_VAL_3_OFFSET 0x68U /**< Preset Value Register */
+#define XSDPS_PRE_VAL_4_OFFSET 0x6CU /**< Preset Value Register */
+#define XSDPS_BOOT_TOUT_CTRL_OFFSET 0x70U /**< Boot timeout control
+ register */
+
+#define XSDPS_SHARED_BUS_CTRL_OFFSET 0xE0U /**< Shared Bus Control
+ Register */
+#define XSDPS_SLOT_INTR_STS_OFFSET 0xFCU /**< Slot Interrupt Status
+ Register */
+#define XSDPS_HOST_CTRL_VER_OFFSET 0xFEU /**< Host Controller Version
+ Register */
+
+/* @} */
+
+/** @name Control Register - Host control, Power control,
+ * Block Gap control and Wakeup control
+ *
+ * This register contains bits for various configuration options of
+ * the SD host controller. Read/Write apart from the reserved bits.
+ * @{
+ */
+
+#define XSDPS_HC_LED_MASK 0x00000001U /**< LED Control */
+#define XSDPS_HC_WIDTH_MASK 0x00000002U /**< Bus width */
+#define XSDPS_HC_BUS_WIDTH_4 0x00000002U
+#define XSDPS_HC_SPEED_MASK 0x00000004U /**< High Speed */
+#define XSDPS_HC_DMA_MASK 0x00000018U /**< DMA Mode Select */
+#define XSDPS_HC_DMA_SDMA_MASK 0x00000000U /**< SDMA Mode */
+#define XSDPS_HC_DMA_ADMA1_MASK 0x00000008U /**< ADMA1 Mode */
+#define XSDPS_HC_DMA_ADMA2_32_MASK 0x00000010U /**< ADMA2 Mode - 32 bit */
+#define XSDPS_HC_DMA_ADMA2_64_MASK 0x00000018U /**< ADMA2 Mode - 64 bit */
+#define XSDPS_HC_EXT_BUS_WIDTH 0x00000020U /**< Bus width - 8 bit */
+#define XSDPS_HC_CARD_DET_TL_MASK 0x00000040U /**< Card Detect Tst Lvl */
+#define XSDPS_HC_CARD_DET_SD_MASK 0x00000080U /**< Card Detect Sig Det */
+
+#define XSDPS_PC_BUS_PWR_MASK 0x00000001U /**< Bus Power Control */
+#define XSDPS_PC_BUS_VSEL_MASK 0x0000000EU /**< Bus Voltage Select */
+#define XSDPS_PC_BUS_VSEL_3V3_MASK 0x0000000EU /**< Bus Voltage 3.3V */
+#define XSDPS_PC_BUS_VSEL_3V0_MASK 0x0000000CU /**< Bus Voltage 3.0V */
+#define XSDPS_PC_BUS_VSEL_1V8_MASK 0x0000000AU /**< Bus Voltage 1.8V */
+#define XSDPS_PC_EMMC_HW_RST_MASK 0x00000010U /**< HW reset for eMMC */
+
+#define XSDPS_BGC_STP_REQ_MASK 0x00000001U /**< Block Gap Stop Req */
+#define XSDPS_BGC_CNT_REQ_MASK 0x00000002U /**< Block Gap Cont Req */
+#define XSDPS_BGC_RWC_MASK 0x00000004U /**< Block Gap Rd Wait */
+#define XSDPS_BGC_INTR_MASK 0x00000008U /**< Block Gap Intr */
+#define XSDPS_BGC_SPI_MODE_MASK 0x00000010U /**< Block Gap SPI Mode */
+#define XSDPS_BGC_BOOT_EN_MASK 0x00000020U /**< Block Gap Boot Enb */
+#define XSDPS_BGC_ALT_BOOT_EN_MASK 0x00000040U /**< Block Gap Alt BootEn */
+#define XSDPS_BGC_BOOT_ACK_MASK 0x00000080U /**< Block Gap Boot Ack */
+
+#define XSDPS_WC_WUP_ON_INTR_MASK 0x00000001U /**< Wakeup Card Intr */
+#define XSDPS_WC_WUP_ON_INSRT_MASK 0x00000002U /**< Wakeup Card Insert */
+#define XSDPS_WC_WUP_ON_REM_MASK 0x00000004U /**< Wakeup Card Removal */
+
+/* @} */
+
+/** @name Control Register - Clock control, Timeout control & Software reset
+ *
+ * This register contains bits for configuration options of clock, timeout and
+ * software reset.
+ * Read/Write except for Inter_Clock_Stable bit (read only) and reserved bits.
+ * @{
+ */
+
+#define XSDPS_CC_INT_CLK_EN_MASK 0x00000001U
+#define XSDPS_CC_INT_CLK_STABLE_MASK 0x00000002U
+#define XSDPS_CC_SD_CLK_EN_MASK 0x00000004U
+#define XSDPS_CC_SD_CLK_GEN_SEL_MASK 0x00000020U
+#define XSDPS_CC_SDCLK_FREQ_SEL_EXT_MASK 0x000000C0U
+#define XSDPS_CC_SDCLK_FREQ_SEL_MASK 0x0000FF00U
+#define XSDPS_CC_SDCLK_FREQ_D256_MASK 0x00008000U
+#define XSDPS_CC_SDCLK_FREQ_D128_MASK 0x00004000U
+#define XSDPS_CC_SDCLK_FREQ_D64_MASK 0x00002000U
+#define XSDPS_CC_SDCLK_FREQ_D32_MASK 0x00001000U
+#define XSDPS_CC_SDCLK_FREQ_D16_MASK 0x00000800U
+#define XSDPS_CC_SDCLK_FREQ_D8_MASK 0x00000400U
+#define XSDPS_CC_SDCLK_FREQ_D4_MASK 0x00000200U
+#define XSDPS_CC_SDCLK_FREQ_D2_MASK 0x00000100U
+#define XSDPS_CC_SDCLK_FREQ_BASE_MASK 0x00000000U
+#define XSDPS_CC_MAX_DIV_CNT 256U
+#define XSDPS_CC_EXT_MAX_DIV_CNT 2046U
+#define XSDPS_CC_EXT_DIV_SHIFT 6U
+
+#define XSDPS_TC_CNTR_VAL_MASK 0x0000000FU
+
+#define XSDPS_SWRST_ALL_MASK 0x00000001U
+#define XSDPS_SWRST_CMD_LINE_MASK 0x00000002U
+#define XSDPS_SWRST_DAT_LINE_MASK 0x00000004U
+
+#define XSDPS_CC_MAX_NUM_OF_DIV 9U
+#define XSDPS_CC_DIV_SHIFT 8U
+
+/* @} */
+
+/** @name SD Interrupt Registers
+ *
+ * <b> Normal and Error Interrupt Status Register </b>
+ * This register shows the normal and error interrupt status.
+ * Status enable register affects reads of this register.
+ * If Signal enable register is set and the corresponding status bit is set,
+ * interrupt is generated.
+ * Write to clear except
+ * Error_interrupt and Card_Interrupt bits - Read only
+ *
+ * <b> Normal and Error Interrupt Status Enable Register </b>
+ * Setting this register bits enables Interrupt status.
+ * Read/Write except Fixed_to_0 bit (Read only)
+ *
+ * <b> Normal and Error Interrupt Signal Enable Register </b>
+ * This register is used to select which interrupt status is
+ * indicated to the Host System as the interrupt.
+ * Read/Write except Fixed_to_0 bit (Read only)
+ *
+ * All three registers have same bit definitions
+ * @{
+ */
+
+#define XSDPS_INTR_CC_MASK 0x00000001U /**< Command Complete */
+#define XSDPS_INTR_TC_MASK 0x00000002U /**< Transfer Complete */
+#define XSDPS_INTR_BGE_MASK 0x00000004U /**< Block Gap Event */
+#define XSDPS_INTR_DMA_MASK 0x00000008U /**< DMA Interrupt */
+#define XSDPS_INTR_BWR_MASK 0x00000010U /**< Buffer Write Ready */
+#define XSDPS_INTR_BRR_MASK 0x00000020U /**< Buffer Read Ready */
+#define XSDPS_INTR_CARD_INSRT_MASK 0x00000040U /**< Card Insert */
+#define XSDPS_INTR_CARD_REM_MASK 0x00000080U /**< Card Remove */
+#define XSDPS_INTR_CARD_MASK 0x00000100U /**< Card Interrupt */
+#define XSDPS_INTR_INT_A_MASK 0x00000200U /**< INT A Interrupt */
+#define XSDPS_INTR_INT_B_MASK 0x00000400U /**< INT B Interrupt */
+#define XSDPS_INTR_INT_C_MASK 0x00000800U /**< INT C Interrupt */
+#define XSDPS_INTR_RE_TUNING_MASK 0x00001000U /**< Re-Tuning Interrupt */
+#define XSDPS_INTR_BOOT_ACK_RECV_MASK 0x00002000U /**< Boot Ack Recv
+ Interrupt */
+#define XSDPS_INTR_BOOT_TERM_MASK 0x00004000U /**< Boot Terminate
+ Interrupt */
+#define XSDPS_INTR_ERR_MASK 0x00008000U /**< Error Interrupt */
+#define XSDPS_NORM_INTR_ALL_MASK 0x0000FFFFU
+
+#define XSDPS_INTR_ERR_CT_MASK 0x00000001U /**< Command Timeout
+ Error */
+#define XSDPS_INTR_ERR_CCRC_MASK 0x00000002U /**< Command CRC Error */
+#define XSDPS_INTR_ERR_CEB_MASK 0x00000004U /**< Command End Bit
+ Error */
+#define XSDPS_INTR_ERR_CI_MASK 0x00000008U /**< Command Index Error */
+#define XSDPS_INTR_ERR_DT_MASK 0x00000010U /**< Data Timeout Error */
+#define XSDPS_INTR_ERR_DCRC_MASK 0x00000020U /**< Data CRC Error */
+#define XSDPS_INTR_ERR_DEB_MASK 0x00000040U /**< Data End Bit Error */
+#define XSDPS_INTR_ERR_CUR_LMT_MASK 0x00000080U /**< Current Limit Error */
+#define XSDPS_INTR_ERR_AUTO_CMD12_MASK 0x00000100U /**< Auto CMD12 Error */
+#define XSDPS_INTR_ERR_ADMA_MASK 0x00000200U /**< ADMA Error */
+#define XSDPS_INTR_ERR_TR_MASK 0x00001000U /**< Tuning Error */
+#define XSDPS_INTR_VEND_SPF_ERR_MASK 0x0000E000U /**< Vendor Specific
+ Error */
+#define XSDPS_ERROR_INTR_ALL_MASK 0x0000F3FFU /**< Mask for error bits */
+/* @} */
+
+/** @name Block Size and Block Count Register
+ *
+ * This register contains the block count for current transfer,
+ * block size and SDMA buffer size.
+ * Read/Write except for reserved bits.
+ * @{
+ */
+
+#define XSDPS_BLK_SIZE_MASK 0x00000FFFU /**< Transfer Block Size */
+#define XSDPS_SDMA_BUFF_SIZE_MASK 0x00007000U /**< Host SDMA Buffer Size */
+#define XSDPS_BLK_SIZE_1024 0x400U
+#define XSDPS_BLK_SIZE_2048 0x800U
+#define XSDPS_BLK_CNT_MASK 0x0000FFFFU /**< Block Count for
+ Current Transfer */
+
+/* @} */
+
+/** @name Transfer Mode and Command Register
+ *
+ * The Transfer Mode register is used to control the data transfers and
+ * Command register is used for command generation
+ * Read/Write except for reserved bits.
+ * @{
+ */
+
+#define XSDPS_TM_DMA_EN_MASK 0x00000001U /**< DMA Enable */
+#define XSDPS_TM_BLK_CNT_EN_MASK 0x00000002U /**< Block Count Enable */
+#define XSDPS_TM_AUTO_CMD12_EN_MASK 0x00000004U /**< Auto CMD12 Enable */
+#define XSDPS_TM_DAT_DIR_SEL_MASK 0x00000010U /**< Data Transfer
+ Direction Select */
+#define XSDPS_TM_MUL_SIN_BLK_SEL_MASK 0x00000020U /**< Multi/Single
+ Block Select */
+
+#define XSDPS_CMD_RESP_SEL_MASK 0x00000003U /**< Response Type
+ Select */
+#define XSDPS_CMD_RESP_NONE_MASK 0x00000000U /**< No Response */
+#define XSDPS_CMD_RESP_L136_MASK 0x00000001U /**< Response length 138 */
+#define XSDPS_CMD_RESP_L48_MASK 0x00000002U /**< Response length 48 */
+#define XSDPS_CMD_RESP_L48_BSY_CHK_MASK 0x00000003U /**< Response length 48 &
+ check busy after
+ response */
+#define XSDPS_CMD_CRC_CHK_EN_MASK 0x00000008U /**< Command CRC Check
+ Enable */
+#define XSDPS_CMD_INX_CHK_EN_MASK 0x00000010U /**< Command Index Check
+ Enable */
+#define XSDPS_DAT_PRESENT_SEL_MASK 0x00000020U /**< Data Present Select */
+#define XSDPS_CMD_TYPE_MASK 0x000000C0U /**< Command Type */
+#define XSDPS_CMD_TYPE_NORM_MASK 0x00000000U /**< CMD Type - Normal */
+#define XSDPS_CMD_TYPE_SUSPEND_MASK 0x00000040U /**< CMD Type - Suspend */
+#define XSDPS_CMD_TYPE_RESUME_MASK 0x00000080U /**< CMD Type - Resume */
+#define XSDPS_CMD_TYPE_ABORT_MASK 0x000000C0U /**< CMD Type - Abort */
+#define XSDPS_CMD_MASK 0x00003F00U /**< Command Index Mask -
+ Set to CMD0-63,
+ AMCD0-63 */
+
+/* @} */
+
+/** @name Auto CMD Error Status Register
+ *
+ * This register is read only register which contains
+ * information about the error status of Auto CMD 12 and 23.
+ * Read Only
+ * @{
+ */
+#define XSDPS_AUTO_CMD12_NT_EX_MASK 0x0001U /**< Auto CMD12 Not
+ executed */
+#define XSDPS_AUTO_CMD_TOUT_MASK 0x0002U /**< Auto CMD Timeout
+ Error */
+#define XSDPS_AUTO_CMD_CRC_MASK 0x0004U /**< Auto CMD CRC Error */
+#define XSDPS_AUTO_CMD_EB_MASK 0x0008U /**< Auto CMD End Bit
+ Error */
+#define XSDPS_AUTO_CMD_IND_MASK 0x0010U /**< Auto CMD Index Error */
+#define XSDPS_AUTO_CMD_CNI_ERR_MASK 0x0080U /**< Command not issued by
+ Auto CMD12 Error */
+/* @} */
+
+/** @name Host Control2 Register
+ *
+ * This register contains extended configuration bits.
+ * Read Write
+ * @{
+ */
+#define XSDPS_HC2_UHS_MODE_MASK 0x0007U /**< UHS Mode select bits */
+#define XSDPS_HC2_UHS_MODE_SDR12_MASK 0x0000U /**< SDR12 UHS Mode */
+#define XSDPS_HC2_UHS_MODE_SDR25_MASK 0x0001U /**< SDR25 UHS Mode */
+#define XSDPS_HC2_UHS_MODE_SDR50_MASK 0x0002U /**< SDR50 UHS Mode */
+#define XSDPS_HC2_UHS_MODE_SDR104_MASK 0x0003U /**< SDR104 UHS Mode */
+#define XSDPS_HC2_UHS_MODE_DDR50_MASK 0x0004U /**< DDR50 UHS Mode */
+#define XSDPS_HC2_1V8_EN_MASK 0x0008U /**< 1.8V Signal Enable */
+#define XSDPS_HC2_DRV_STR_SEL_MASK 0x0030U /**< Driver Strength
+ Selection */
+#define XSDPS_HC2_DRV_STR_B_MASK 0x0000U /**< Driver Strength B */
+#define XSDPS_HC2_DRV_STR_A_MASK 0x0010U /**< Driver Strength A */
+#define XSDPS_HC2_DRV_STR_C_MASK 0x0020U /**< Driver Strength C */
+#define XSDPS_HC2_DRV_STR_D_MASK 0x0030U /**< Driver Strength D */
+#define XSDPS_HC2_EXEC_TNG_MASK 0x0040U /**< Execute Tuning */
+#define XSDPS_HC2_SAMP_CLK_SEL_MASK 0x0080U /**< Sampling Clock
+ Selection */
+#define XSDPS_HC2_ASYNC_INTR_EN_MASK 0x4000U /**< Asynchronous Interrupt
+ Enable */
+#define XSDPS_HC2_PRE_VAL_EN_MASK 0x8000U /**< Preset Value Enable */
+
+/* @} */
+
+/** @name Capabilities Register
+ *
+ * Capabilities register is a read only register which contains
+ * information about the host controller.
+ * Sufficient if read once after power on.
+ * Read Only
+ * @{
+ */
+#define XSDPS_CAP_TOUT_CLK_FREQ_MASK 0x0000003FU /**< Timeout clock freq
+ select */
+#define XSDPS_CAP_TOUT_CLK_UNIT_MASK 0x00000080U /**< Timeout clock unit -
+ MHz/KHz */
+#define XSDPS_CAP_MAX_BLK_LEN_MASK 0x00030000U /**< Max block length */
+#define XSDPS_CAP_MAX_BLK_LEN_512B_MASK 0x00000000U /**< Max block 512 bytes */
+#define XSDPS_CAP_MAX_BL_LN_1024_MASK 0x00010000U /**< Max block 1024 bytes */
+#define XSDPS_CAP_MAX_BL_LN_2048_MASK 0x00020000U /**< Max block 2048 bytes */
+#define XSDPS_CAP_MAX_BL_LN_4096_MASK 0x00030000U /**< Max block 4096 bytes */
+
+#define XSDPS_CAP_EXT_MEDIA_BUS_MASK 0x00040000U /**< Extended media bus */
+#define XSDPS_CAP_ADMA2_MASK 0x00080000U /**< ADMA2 support */
+#define XSDPS_CAP_HIGH_SPEED_MASK 0x00200000U /**< High speed support */
+#define XSDPS_CAP_SDMA_MASK 0x00400000U /**< SDMA support */
+#define XSDPS_CAP_SUSP_RESUME_MASK 0x00800000U /**< Suspend/Resume
+ support */
+#define XSDPS_CAP_VOLT_3V3_MASK 0x01000000U /**< 3.3V support */
+#define XSDPS_CAP_VOLT_3V0_MASK 0x02000000U /**< 3.0V support */
+#define XSDPS_CAP_VOLT_1V8_MASK 0x04000000U /**< 1.8V support */
+
+#define XSDPS_CAP_SYS_BUS_64_MASK 0x10000000U /**< 64 bit system bus
+ support */
+/* Spec 2.0 */
+#define XSDPS_CAP_INTR_MODE_MASK 0x08000000U /**< Interrupt mode
+ support */
+#define XSDPS_CAP_SPI_MODE_MASK 0x20000000U /**< SPI mode */
+#define XSDPS_CAP_SPI_BLOCK_MODE_MASK 0x40000000U /**< SPI block mode */
+
+
+/* Spec 3.0 */
+#define XSDPS_CAPS_ASYNC_INTR_MASK 0x20000000U /**< Async Interrupt
+ support */
+#define XSDPS_CAPS_SLOT_TYPE_MASK 0xC0000000U /**< Slot Type */
+#define XSDPS_CAPS_REM_CARD 0x00000000U /**< Removable Slot */
+#define XSDPS_CAPS_EMB_SLOT 0x40000000U /**< Embedded Slot */
+#define XSDPS_CAPS_SHR_BUS 0x80000000U /**< Shared Bus Slot */
+
+#define XSDPS_ECAPS_SDR50_MASK 0x00000001U /**< SDR50 Mode support */
+#define XSDPS_ECAPS_SDR104_MASK 0x00000002U /**< SDR104 Mode support */
+#define XSDPS_ECAPS_DDR50_MASK 0x00000004U /**< DDR50 Mode support */
+#define XSDPS_ECAPS_DRV_TYPE_A_MASK 0x00000010U /**< DriverType A support */
+#define XSDPS_ECAPS_DRV_TYPE_C_MASK 0x00000020U /**< DriverType C support */
+#define XSDPS_ECAPS_DRV_TYPE_D_MASK 0x00000040U /**< DriverType D support */
+#define XSDPS_ECAPS_TMR_CNT_MASK 0x00000F00U /**< Timer Count for
+ Re-tuning */
+#define XSDPS_ECAPS_USE_TNG_SDR50_MASK 0x00002000U /**< SDR50 Mode needs
+ tuning */
+#define XSDPS_ECAPS_RE_TNG_MODES_MASK 0x0000C000U /**< Re-tuning modes
+ support */
+#define XSDPS_ECAPS_RE_TNG_MODE1_MASK 0x00000000U /**< Re-tuning mode 1 */
+#define XSDPS_ECAPS_RE_TNG_MODE2_MASK 0x00004000U /**< Re-tuning mode 2 */
+#define XSDPS_ECAPS_RE_TNG_MODE3_MASK 0x00008000U /**< Re-tuning mode 3 */
+#define XSDPS_ECAPS_CLK_MULT_MASK 0x00FF0000U /**< Clock Multiplier value
+ for Programmable clock
+ mode */
+#define XSDPS_ECAPS_SPI_MODE_MASK 0x01000000U /**< SPI mode */
+#define XSDPS_ECAPS_SPI_BLK_MODE_MASK 0x02000000U /**< SPI block mode */
+
+/* @} */
+
+/** @name Present State Register
+ *
+ * Gives the current status of the host controller
+ * Read Only
+ * @{
+ */
+
+#define XSDPS_PSR_INHIBIT_CMD_MASK 0x00000001U /**< Command inhibit - CMD */
+#define XSDPS_PSR_INHIBIT_DAT_MASK 0x00000002U /**< Command Inhibit - DAT */
+#define XSDPS_PSR_DAT_ACTIVE_MASK 0x00000004U /**< DAT line active */
+#define XSDPS_PSR_RE_TUNING_REQ_MASK 0x00000008U /**< Re-tuning request */
+#define XSDPS_PSR_WR_ACTIVE_MASK 0x00000100U /**< Write transfer active */
+#define XSDPS_PSR_RD_ACTIVE_MASK 0x00000200U /**< Read transfer active */
+#define XSDPS_PSR_BUFF_WR_EN_MASK 0x00000400U /**< Buffer write enable */
+#define XSDPS_PSR_BUFF_RD_EN_MASK 0x00000800U /**< Buffer read enable */
+#define XSDPS_PSR_CARD_INSRT_MASK 0x00010000U /**< Card inserted */
+#define XSDPS_PSR_CARD_STABLE_MASK 0x00020000U /**< Card state stable */
+#define XSDPS_PSR_CARD_DPL_MASK 0x00040000U /**< Card detect pin level */
+#define XSDPS_PSR_WPS_PL_MASK 0x00080000U /**< Write protect switch
+ pin level */
+#define XSDPS_PSR_DAT30_SG_LVL_MASK 0x00F00000U /**< Data 3:0 signal lvl */
+#define XSDPS_PSR_CMD_SG_LVL_MASK 0x01000000U /**< Cmd Line signal lvl */
+#define XSDPS_PSR_DAT74_SG_LVL_MASK 0x1E000000U /**< Data 7:4 signal lvl */
+
+/* @} */
+
+/** @name Maximum Current Capabilities Register
+ *
+ * This register is read only register which contains
+ * information about current capabilities at each voltage levels.
+ * Read Only
+ * @{
+ */
+#define XSDPS_MAX_CUR_CAPS_1V8_MASK 0x00000F00U /**< Maximum Current
+ Capability at 1.8V */
+#define XSDPS_MAX_CUR_CAPS_3V0_MASK 0x000000F0U /**< Maximum Current
+ Capability at 3.0V */
+#define XSDPS_MAX_CUR_CAPS_3V3_MASK 0x0000000FU /**< Maximum Current
+ Capability at 3.3V */
+/* @} */
+
+
+/** @name Force Event for Auto CMD Error Status Register
+ *
+ * This register is write only register which contains
+ * control bits to generate events for Auto CMD error status.
+ * Write Only
+ * @{
+ */
+#define XSDPS_FE_AUTO_CMD12_NT_EX_MASK 0x0001U /**< Auto CMD12 Not
+ executed */
+#define XSDPS_FE_AUTO_CMD_TOUT_MASK 0x0002U /**< Auto CMD Timeout
+ Error */
+#define XSDPS_FE_AUTO_CMD_CRC_MASK 0x0004U /**< Auto CMD CRC Error */
+#define XSDPS_FE_AUTO_CMD_EB_MASK 0x0008U /**< Auto CMD End Bit
+ Error */
+#define XSDPS_FE_AUTO_CMD_IND_MASK 0x0010U /**< Auto CMD Index Error */
+#define XSDPS_FE_AUTO_CMD_CNI_ERR_MASK 0x0080U /**< Command not issued by
+ Auto CMD12 Error */
+/* @} */
+
+
+
+/** @name Force Event for Error Interrupt Status Register
+ *
+ * This register is write only register which contains
+ * control bits to generate events of error interrupt status register.
+ * Write Only
+ * @{
+ */
+#define XSDPS_FE_INTR_ERR_CT_MASK 0x0001U /**< Command Timeout
+ Error */
+#define XSDPS_FE_INTR_ERR_CCRC_MASK 0x0002U /**< Command CRC Error */
+#define XSDPS_FE_INTR_ERR_CEB_MASK 0x0004U /**< Command End Bit
+ Error */
+#define XSDPS_FE_INTR_ERR_CI_MASK 0x0008U /**< Command Index Error */
+#define XSDPS_FE_INTR_ERR_DT_MASK 0x0010U /**< Data Timeout Error */
+#define XSDPS_FE_INTR_ERR_DCRC_MASK 0x0020U /**< Data CRC Error */
+#define XSDPS_FE_INTR_ERR_DEB_MASK 0x0040U /**< Data End Bit Error */
+#define XSDPS_FE_INTR_ERR_CUR_LMT_MASK 0x0080U /**< Current Limit Error */
+#define XSDPS_FE_INTR_ERR_AUTO_CMD_MASK 0x0100U /**< Auto CMD Error */
+#define XSDPS_FE_INTR_ERR_ADMA_MASK 0x0200U /**< ADMA Error */
+#define XSDPS_FE_INTR_ERR_TR_MASK 0x1000U /**< Target Response */
+#define XSDPS_FE_INTR_VEND_SPF_ERR_MASK 0xE000U /**< Vendor Specific
+ Error */
+
+/* @} */
+
+/** @name ADMA Error Status Register
+ *
+ * This register is read only register which contains
+ * status information about ADMA errors.
+ * Read Only
+ * @{
+ */
+#define XSDPS_ADMA_ERR_MM_LEN_MASK 0x04U /**< ADMA Length Mismatch
+ Error */
+#define XSDPS_ADMA_ERR_STATE_MASK 0x03U /**< ADMA Error State */
+#define XSDPS_ADMA_ERR_STATE_STOP_MASK 0x00U /**< ADMA Error State
+ STOP */
+#define XSDPS_ADMA_ERR_STATE_FDS_MASK 0x01U /**< ADMA Error State
+ FDS */
+#define XSDPS_ADMA_ERR_STATE_TFR_MASK 0x03U /**< ADMA Error State
+ TFR */
+/* @} */
+
+/** @name Preset Values Register
+ *
+ * This register is read only register which contains
+ * preset values for each of speed modes.
+ * Read Only
+ * @{
+ */
+#define XSDPS_PRE_VAL_SDCLK_FSEL_MASK 0x03FFU /**< SDCLK Frequency
+ Select Value */
+#define XSDPS_PRE_VAL_CLK_GEN_SEL_MASK 0x0400U /**< Clock Generator
+ Mode Select */
+#define XSDPS_PRE_VAL_DRV_STR_SEL_MASK 0xC000U /**< Driver Strength
+ Select Value */
+
+/* @} */
+
+/** @name Slot Interrupt Status Register
+ *
+ * This register is read only register which contains
+ * interrupt slot signal for each slot.
+ * Read Only
+ * @{
+ */
+#define XSDPS_SLOT_INTR_STS_INT_MASK 0x0007U /**< Interrupt Signal
+ mask */
+
+/* @} */
+
+/** @name Host Controller Version Register
+ *
+ * This register is read only register which contains
+ * Host Controller and Vendor Specific version.
+ * Read Only
+ * @{
+ */
+#define XSDPS_HC_VENDOR_VER 0xFF00U /**< Vendor
+ Specification
+ version mask */
+#define XSDPS_HC_SPEC_VER_MASK 0x00FFU /**< Host
+ Specification
+ version mask */
+#define XSDPS_HC_SPEC_V3 0x0002U
+#define XSDPS_HC_SPEC_V2 0x0001U
+#define XSDPS_HC_SPEC_V1 0x0000U
+
+/** @name Block size mask for 512 bytes
+ *
+ * Block size mask for 512 bytes - This is the default block size.
+ * @{
+ */
+
+#define XSDPS_BLK_SIZE_512_MASK 0x200U
+
+/* @} */
+
+/** @name Commands
+ *
+ * Constant definitions for commands and response related to SD
+ * @{
+ */
+
+#define XSDPS_APP_CMD_PREFIX 0x8000U
+#define CMD0 0x0000U
+#define CMD1 0x0100U
+#define CMD2 0x0200U
+#define CMD3 0x0300U
+#define CMD4 0x0400U
+#define CMD5 0x0500U
+#define CMD6 0x0600U
+#define ACMD6 (XSDPS_APP_CMD_PREFIX + 0x0600U)
+#define CMD7 0x0700U
+#define CMD8 0x0800U
+#define CMD9 0x0900U
+#define CMD10 0x0A00U
+#define CMD11 0x0B00U
+#define CMD12 0x0C00U
+#define ACMD13 (XSDPS_APP_CMD_PREFIX + 0x0D00U)
+#define CMD16 0x1000U
+#define CMD17 0x1100U
+#define CMD18 0x1200U
+#define CMD19 0x1300U
+#define CMD21 0x1500U
+#define CMD23 0x1700U
+#define ACMD23 (XSDPS_APP_CMD_PREFIX + 0x1700U)
+#define CMD24 0x1800U
+#define CMD25 0x1900U
+#define CMD41 0x2900U
+#define ACMD41 (XSDPS_APP_CMD_PREFIX + 0x2900U)
+#define ACMD42 (XSDPS_APP_CMD_PREFIX + 0x2A00U)
+#define ACMD51 (XSDPS_APP_CMD_PREFIX + 0x3300U)
+#define CMD52 0x3400U
+#define CMD55 0x3700U
+#define CMD58 0x3A00U
+
+#define RESP_NONE (u32)XSDPS_CMD_RESP_NONE_MASK
+#define RESP_R1 (u32)XSDPS_CMD_RESP_L48_MASK | (u32)XSDPS_CMD_CRC_CHK_EN_MASK | \
+ (u32)XSDPS_CMD_INX_CHK_EN_MASK
+
+#define RESP_R1B (u32)XSDPS_CMD_RESP_L48_BSY_CHK_MASK | \
+ (u32)XSDPS_CMD_CRC_CHK_EN_MASK | (u32)XSDPS_CMD_INX_CHK_EN_MASK
+
+#define RESP_R2 (u32)XSDPS_CMD_RESP_L136_MASK | (u32)XSDPS_CMD_CRC_CHK_EN_MASK
+#define RESP_R3 (u32)XSDPS_CMD_RESP_L48_MASK
+
+#define RESP_R6 (u32)XSDPS_CMD_RESP_L48_BSY_CHK_MASK | \
+ (u32)XSDPS_CMD_CRC_CHK_EN_MASK | (u32)XSDPS_CMD_INX_CHK_EN_MASK
+
+/* @} */
+
+/* Card Interface Conditions Definitions */
+#define XSDPS_CIC_CHK_PATTERN 0xAAU
+#define XSDPS_CIC_VOLT_MASK (0xFU<<8)
+#define XSDPS_CIC_VOLT_2V7_3V6 (1U<<8)
+#define XSDPS_CIC_VOLT_LOW (1U<<9)
+
+/* Operation Conditions Register Definitions */
+#define XSDPS_OCR_PWRUP_STS (1U<<31)
+#define XSDPS_OCR_CC_STS (1U<<30)
+#define XSDPS_OCR_S18 (1U<<24)
+#define XSDPS_OCR_3V5_3V6 (1U<<23)
+#define XSDPS_OCR_3V4_3V5 (1U<<22)
+#define XSDPS_OCR_3V3_3V4 (1U<<21)
+#define XSDPS_OCR_3V2_3V3 (1U<<20)
+#define XSDPS_OCR_3V1_3V2 (1U<<19)
+#define XSDPS_OCR_3V0_3V1 (1U<<18)
+#define XSDPS_OCR_2V9_3V0 (1U<<17)
+#define XSDPS_OCR_2V8_2V9 (1U<<16)
+#define XSDPS_OCR_2V7_2V8 (1U<<15)
+#define XSDPS_OCR_1V7_1V95 (1U<<7)
+#define XSDPS_OCR_HIGH_VOL 0x00FF8000U
+#define XSDPS_OCR_LOW_VOL 0x00000080U
+
+/* SD Card Configuration Register Definitions */
+#define XSDPS_SCR_REG_LEN 8U
+#define XSDPS_SCR_STRUCT_MASK (0xFU<<28)
+#define XSDPS_SCR_SPEC_MASK (0xFU<<24)
+#define XSDPS_SCR_SPEC_1V0 0U
+#define XSDPS_SCR_SPEC_1V1 (1U<<24)
+#define XSDPS_SCR_SPEC_2V0_3V0 (2U<<24)
+#define XSDPS_SCR_MEM_VAL_AF_ERASE (1U<<23)
+#define XSDPS_SCR_SEC_SUPP_MASK (7U<<20)
+#define XSDPS_SCR_SEC_SUPP_NONE 0U
+#define XSDPS_SCR_SEC_SUPP_1V1 (2U<<20)
+#define XSDPS_SCR_SEC_SUPP_2V0 (3U<<20)
+#define XSDPS_SCR_SEC_SUPP_3V0 (4U<<20)
+#define XSDPS_SCR_BUS_WIDTH_MASK (0xFU<<16)
+#define XSDPS_SCR_BUS_WIDTH_1 (1U<<16)
+#define XSDPS_SCR_BUS_WIDTH_4 (4U<<16)
+#define XSDPS_SCR_SPEC3_MASK (1U<<12)
+#define XSDPS_SCR_SPEC3_2V0 0U
+#define XSDPS_SCR_SPEC3_3V0 (1U<<12)
+#define XSDPS_SCR_CMD_SUPP_MASK 0x3U
+#define XSDPS_SCR_CMD23_SUPP (1U<<1)
+#define XSDPS_SCR_CMD20_SUPP (1U<<0)
+
+/* Card Status Register Definitions */
+#define XSDPS_CD_STS_OUT_OF_RANGE (1U<<31)
+#define XSDPS_CD_STS_ADDR_ERR (1U<<30)
+#define XSDPS_CD_STS_BLK_LEN_ERR (1U<<29)
+#define XSDPS_CD_STS_ER_SEQ_ERR (1U<<28)
+#define XSDPS_CD_STS_ER_PRM_ERR (1U<<27)
+#define XSDPS_CD_STS_WP_VIO (1U<<26)
+#define XSDPS_CD_STS_IS_LOCKED (1U<<25)
+#define XSDPS_CD_STS_LOCK_UNLOCK_FAIL (1U<<24)
+#define XSDPS_CD_STS_CMD_CRC_ERR (1U<<23)
+#define XSDPS_CD_STS_ILGL_CMD (1U<<22)
+#define XSDPS_CD_STS_CARD_ECC_FAIL (1U<<21)
+#define XSDPS_CD_STS_CC_ERR (1U<<20)
+#define XSDPS_CD_STS_ERR (1U<<19)
+#define XSDPS_CD_STS_CSD_OVRWR (1U<<16)
+#define XSDPS_CD_STS_WP_ER_SKIP (1U<<15)
+#define XSDPS_CD_STS_CARD_ECC_DIS (1U<<14)
+#define XSDPS_CD_STS_ER_RST (1U<<13)
+#define XSDPS_CD_STS_CUR_STATE (0xFU<<9)
+#define XSDPS_CD_STS_RDY_FOR_DATA (1U<<8)
+#define XSDPS_CD_STS_APP_CMD (1U<<5)
+#define XSDPS_CD_STS_AKE_SEQ_ERR (1U<<2)
+
+/* Switch Function Definitions CMD6 */
+#define XSDPS_SWITCH_SD_RESP_LEN 64U
+
+#define XSDPS_SWITCH_FUNC_SWITCH (1U<<31)
+#define XSDPS_SWITCH_FUNC_CHECK 0U
+
+#define XSDPS_MODE_FUNC_GRP1 1U
+#define XSDPS_MODE_FUNC_GRP2 2U
+#define XSDPS_MODE_FUNC_GRP3 3U
+#define XSDPS_MODE_FUNC_GRP4 4U
+#define XSDPS_MODE_FUNC_GRP5 5U
+#define XSDPS_MODE_FUNC_GRP6 6U
+
+#define XSDPS_FUNC_GRP_DEF_VAL 0xFU
+#define XSDPS_FUNC_ALL_GRP_DEF_VAL 0xFFFFFFU
+
+#define XSDPS_ACC_MODE_DEF_SDR12 0U
+#define XSDPS_ACC_MODE_HS_SDR25 1U
+#define XSDPS_ACC_MODE_SDR50 2U
+#define XSDPS_ACC_MODE_SDR104 3U
+#define XSDPS_ACC_MODE_DDR50 4U
+
+#define XSDPS_CMD_SYS_ARG_SHIFT 4U
+#define XSDPS_CMD_SYS_DEF 0U
+#define XSDPS_CMD_SYS_eC 1U
+#define XSDPS_CMD_SYS_OTP 3U
+#define XSDPS_CMD_SYS_ASSD 4U
+#define XSDPS_CMD_SYS_VEND 5U
+
+#define XSDPS_DRV_TYPE_ARG_SHIFT 8U
+#define XSDPS_DRV_TYPE_B 0U
+#define XSDPS_DRV_TYPE_A 1U
+#define XSDPS_DRV_TYPE_C 2U
+#define XSDPS_DRV_TYPE_D 3U
+
+#define XSDPS_CUR_LIM_ARG_SHIFT 12U
+#define XSDPS_CUR_LIM_200 0U
+#define XSDPS_CUR_LIM_400 1U
+#define XSDPS_CUR_LIM_600 2U
+#define XSDPS_CUR_LIM_800 3U
+
+#define CSD_SPEC_VER_MASK 0x3C0000U
+#define READ_BLK_LEN_MASK 0x00000F00U
+#define C_SIZE_MULT_MASK 0x00000380U
+#define C_SIZE_LOWER_MASK 0xFFC00000U
+#define C_SIZE_UPPER_MASK 0x00000003U
+#define CSD_STRUCT_MASK 0x00C00000U
+#define CSD_V2_C_SIZE_MASK 0x3FFFFF00U
+
+/* EXT_CSD field definitions */
+#define XSDPS_EXT_CSD_SIZE 512U
+
+#define EXT_CSD_WR_REL_PARAM_EN (1U<<2)
+
+#define EXT_CSD_BOOT_WP_B_PWR_WP_DIS (0x40U)
+#define EXT_CSD_BOOT_WP_B_PERM_WP_DIS (0x10U)
+#define EXT_CSD_BOOT_WP_B_PERM_WP_EN (0x04U)
+#define EXT_CSD_BOOT_WP_B_PWR_WP_EN (0x01U)
+
+#define EXT_CSD_PART_CONFIG_ACC_MASK (0x7U)
+#define EXT_CSD_PART_CONFIG_ACC_BOOT0 (0x1U)
+#define EXT_CSD_PART_CONFIG_ACC_RPMB (0x3U)
+#define EXT_CSD_PART_CONFIG_ACC_GP0 (0x4U)
+
+#define EXT_CSD_PART_SUPPORT_PART_EN (0x1U)
+
+#define EXT_CSD_CMD_SET_NORMAL (1U<<0)
+#define EXT_CSD_CMD_SET_SECURE (1U<<1)
+#define EXT_CSD_CMD_SET_CPSECURE (1U<<2)
+
+#define EXT_CSD_CARD_TYPE_26 (1U<<0) /* Card can run at 26MHz */
+#define EXT_CSD_CARD_TYPE_52 (1U<<1) /* Card can run at 52MHz */
+#define EXT_CSD_CARD_TYPE_MASK 0x3FU /* Mask out reserved bits */
+#define EXT_CSD_CARD_TYPE_DDR_1_8V (1U<<2) /* Card can run at 52MHz */
+ /* DDR mode @1.8V or 3V I/O */
+#define EXT_CSD_CARD_TYPE_DDR_1_2V (1U<<3) /* Card can run at 52MHz */
+ /* DDR mode @1.2V I/O */
+#define EXT_CSD_CARD_TYPE_DDR_52 (EXT_CSD_CARD_TYPE_DDR_1_8V \
+ | EXT_CSD_CARD_TYPE_DDR_1_2V)
+#define EXT_CSD_CARD_TYPE_SDR_1_8V (1U<<4) /* Card can run at 200MHz */
+#define EXT_CSD_CARD_TYPE_SDR_1_2V (1U<<5) /* Card can run at 200MHz */
+ /* SDR mode @1.2V I/O */
+#define EXT_CSD_BUS_WIDTH_BYTE 183U
+#define EXT_CSD_BUS_WIDTH_1_BIT 0U /* Card is in 1 bit mode */
+#define EXT_CSD_BUS_WIDTH_4_BIT 1U /* Card is in 4 bit mode */
+#define EXT_CSD_BUS_WIDTH_8_BIT 2U /* Card is in 8 bit mode */
+#define EXT_CSD_BUS_WIDTH_DDR_4_BIT 5U /* Card is in 4 bit DDR mode */
+#define EXT_CSD_BUS_WIDTH_DDR_8_BIT 6U /* Card is in 8 bit DDR mode */
+
+#define EXT_CSD_HS_TIMING_BYTE 185U
+#define EXT_CSD_HS_TIMING_DEF 0U
+#define EXT_CSD_HS_TIMING_HIGH 1U /* Card is in high speed mode */
+#define EXT_CSD_HS_TIMING_HS200 2U /* Card is in HS200 mode */
+
+#define EXT_CSD_RST_N_FUN_BYTE 162U
+#define EXT_CSD_RST_N_FUN_TEMP_DIS 0U /* RST_n signal is temporarily disabled */
+#define EXT_CSD_RST_N_FUN_PERM_EN 1U /* RST_n signal is permanently enabled */
+#define EXT_CSD_RST_N_FUN_PERM_DIS 2U /* RST_n signal is permanently disabled */
+
+#define XSDPS_EXT_CSD_CMD_SET 0U
+#define XSDPS_EXT_CSD_SET_BITS 1U
+#define XSDPS_EXT_CSD_CLR_BITS 2U
+#define XSDPS_EXT_CSD_WRITE_BYTE 3U
+
+#define XSDPS_MMC_DEF_SPEED_ARG (((u32)XSDPS_EXT_CSD_WRITE_BYTE << 24) \
+ | ((u32)EXT_CSD_HS_TIMING_BYTE << 16) \
+ | ((u32)EXT_CSD_HS_TIMING_DEF << 8))
+
+#define XSDPS_MMC_HIGH_SPEED_ARG (((u32)XSDPS_EXT_CSD_WRITE_BYTE << 24) \
+ | ((u32)EXT_CSD_HS_TIMING_BYTE << 16) \
+ | ((u32)EXT_CSD_HS_TIMING_HIGH << 8))
+
+#define XSDPS_MMC_HS200_ARG (((u32)XSDPS_EXT_CSD_WRITE_BYTE << 24) \
+ | ((u32)EXT_CSD_HS_TIMING_BYTE << 16) \
+ | ((u32)EXT_CSD_HS_TIMING_HS200 << 8))
+
+#define XSDPS_MMC_1_BIT_BUS_ARG (((u32)XSDPS_EXT_CSD_WRITE_BYTE << 24) \
+ | ((u32)EXT_CSD_BUS_WIDTH_BYTE << 16) \
+ | ((u32)EXT_CSD_BUS_WITH_1_BIT << 8))
+
+#define XSDPS_MMC_4_BIT_BUS_ARG (((u32)XSDPS_EXT_CSD_WRITE_BYTE << 24) \
+ | ((u32)EXT_CSD_BUS_WIDTH_BYTE << 16) \
+ | ((u32)EXT_CSD_BUS_WIDTH_4_BIT << 8))
+
+#define XSDPS_MMC_8_BIT_BUS_ARG (((u32)XSDPS_EXT_CSD_WRITE_BYTE << 24) \
+ | ((u32)EXT_CSD_BUS_WIDTH_BYTE << 16) \
+ | ((u32)EXT_CSD_BUS_WIDTH_8_BIT << 8))
+
+#define XSDPS_MMC_DDR_4_BIT_BUS_ARG (((u32)XSDPS_EXT_CSD_WRITE_BYTE << 24) \
+ | ((u32)EXT_CSD_BUS_WIDTH_BYTE << 16) \
+ | ((u32)EXT_CSD_BUS_WIDTH_DDR_4_BIT << 8))
+
+#define XSDPS_MMC_DDR_8_BIT_BUS_ARG (((u32)XSDPS_EXT_CSD_WRITE_BYTE << 24) \
+ | ((u32)EXT_CSD_BUS_WIDTH_BYTE << 16) \
+ | ((u32)EXT_CSD_BUS_WIDTH_DDR_8_BIT << 8))
+
+#define XSDPS_MMC_RST_FUN_EN_ARG (((u32)XSDPS_EXT_CSD_WRITE_BYTE << 24) \
+ | ((u32)EXT_CSD_RST_N_FUN_BYTE << 16) \
+ | ((u32)EXT_CSD_RST_N_FUN_PERM_EN << 8))
+
+#define XSDPS_MMC_DELAY_FOR_SWITCH 1000U
+
+/* @} */
+
+/* @400KHz, in usec */
+#define XSDPS_74CLK_DELAY 2960U
+#define XSDPS_100CLK_DELAY 4000U
+#define XSDPS_INIT_DELAY 10000U
+
+#define XSDPS_DEF_VOLT_LVL XSDPS_PC_BUS_VSEL_3V0_MASK
+#define XSDPS_CARD_DEF_ADDR 0x1234U
+
+#define XSDPS_CARD_SD 1U
+#define XSDPS_CARD_MMC 2U
+#define XSDPS_CARD_SDIO 3U
+#define XSDPS_CARD_SDCOMBO 4U
+#define XSDPS_CHIP_EMMC 5U
+
+
+/** @name ADMA2 Descriptor related definitions
+ *
+ * ADMA2 Descriptor related definitions
+ * @{
+ */
+
+#define XSDPS_DESC_MAX_LENGTH 65536U
+
+#define XSDPS_DESC_VALID (0x1U << 0)
+#define XSDPS_DESC_END (0x1U << 1)
+#define XSDPS_DESC_INT (0x1U << 2)
+#define XSDPS_DESC_TRAN (0x2U << 4)
+
+/* @} */
+
+/* For changing clock frequencies */
+#define XSDPS_CLK_400_KHZ 400000U /**< 400 KHZ */
+#define XSDPS_CLK_50_MHZ 50000000U /**< 50 MHZ */
+#define XSDPS_CLK_52_MHZ 52000000U /**< 52 MHZ */
+#define XSDPS_SD_VER_1_0 0x1U /**< SD ver 1 */
+#define XSDPS_SD_VER_2_0 0x2U /**< SD ver 2 */
+#define XSDPS_SCR_BLKCNT 1U
+#define XSDPS_SCR_BLKSIZE 8U
+#define XSDPS_1_BIT_WIDTH 0x1U
+#define XSDPS_4_BIT_WIDTH 0x2U
+#define XSDPS_8_BIT_WIDTH 0x3U
+#define XSDPS_UHS_SPEED_MODE_SDR12 0x0U
+#define XSDPS_UHS_SPEED_MODE_SDR25 0x1U
+#define XSDPS_UHS_SPEED_MODE_SDR50 0x2U
+#define XSDPS_UHS_SPEED_MODE_SDR104 0x3U
+#define XSDPS_UHS_SPEED_MODE_DDR50 0x4U
+#define XSDPS_HIGH_SPEED_MODE 0x5U
+#define XSDPS_DEFAULT_SPEED_MODE 0x6U
+#define XSDPS_HS200_MODE 0x7U
+#define XSDPS_DDR52_MODE 0x4U
+#define XSDPS_SWITCH_CMD_BLKCNT 1U
+#define XSDPS_SWITCH_CMD_BLKSIZE 64U
+#define XSDPS_SWITCH_CMD_HS_GET 0x00FFFFF0U
+#define XSDPS_SWITCH_CMD_HS_SET 0x80FFFFF1U
+#define XSDPS_SWITCH_CMD_SDR12_SET 0x80FFFFF0U
+#define XSDPS_SWITCH_CMD_SDR25_SET 0x80FFFFF1U
+#define XSDPS_SWITCH_CMD_SDR50_SET 0x80FFFFF2U
+#define XSDPS_SWITCH_CMD_SDR104_SET 0x80FFFFF3U
+#define XSDPS_SWITCH_CMD_DDR50_SET 0x80FFFFF4U
+#define XSDPS_EXT_CSD_CMD_BLKCNT 1U
+#define XSDPS_EXT_CSD_CMD_BLKSIZE 512U
+#define XSDPS_TUNING_CMD_BLKCNT 1U
+#define XSDPS_TUNING_CMD_BLKSIZE 64U
+
+#define XSDPS_HIGH_SPEED_MAX_CLK 50000000U
+#define XSDPS_UHS_SDR104_MAX_CLK 208000000U
+#define XSDPS_UHS_SDR50_MAX_CLK 100000000U
+#define XSDPS_UHS_DDR50_MAX_CLK 50000000U
+#define XSDPS_UHS_SDR25_MAX_CLK 50000000U
+#define XSDPS_UHS_SDR12_MAX_CLK 25000000U
+
+#define SD_DRIVER_TYPE_B 0x01U
+#define SD_DRIVER_TYPE_A 0x02U
+#define SD_DRIVER_TYPE_C 0x04U
+#define SD_DRIVER_TYPE_D 0x08U
+#define SD_SET_CURRENT_LIMIT_200 0U
+#define SD_SET_CURRENT_LIMIT_400 1U
+#define SD_SET_CURRENT_LIMIT_600 2U
+#define SD_SET_CURRENT_LIMIT_800 3U
+
+#define SD_MAX_CURRENT_200 (1U << SD_SET_CURRENT_LIMIT_200)
+#define SD_MAX_CURRENT_400 (1U << SD_SET_CURRENT_LIMIT_400)
+#define SD_MAX_CURRENT_600 (1U << SD_SET_CURRENT_LIMIT_600)
+#define SD_MAX_CURRENT_800 (1U << SD_SET_CURRENT_LIMIT_800)
+
+#define XSDPS_SD_SDR12_MAX_CLK 25000000U
+#define XSDPS_SD_SDR25_MAX_CLK 50000000U
+#define XSDPS_SD_SDR50_MAX_CLK 100000000U
+#define XSDPS_SD_DDR50_MAX_CLK 50000000U
+#define XSDPS_SD_SDR104_MAX_CLK 208000000U
+/*
+ * XSDPS_SD_INPUT_MAX_CLK is set to 175000000 in order to keep it smaller
+ * than the clock value coming from the core. This value is kept to safely
+ * switch to SDR104 mode if the SD card supports it.
+ */
+#define XSDPS_SD_INPUT_MAX_CLK 175000000U
+
+#define XSDPS_MMC_HS200_MAX_CLK 200000000U
+#define XSDPS_MMC_HSD_MAX_CLK 52000000U
+#define XSDPS_MMC_DDR_MAX_CLK 52000000U
+
+#define XSDPS_CARD_STATE_IDLE 0U
+#define XSDPS_CARD_STATE_RDY 1U
+#define XSDPS_CARD_STATE_IDEN 2U
+#define XSDPS_CARD_STATE_STBY 3U
+#define XSDPS_CARD_STATE_TRAN 4U
+#define XSDPS_CARD_STATE_DATA 5U
+#define XSDPS_CARD_STATE_RCV 6U
+#define XSDPS_CARD_STATE_PROG 7U
+#define XSDPS_CARD_STATE_DIS 8U
+#define XSDPS_CARD_STATE_BTST 9U
+#define XSDPS_CARD_STATE_SLP 10U
+
+#define XSDPS_SLOT_REM 0U
+#define XSDPS_SLOT_EMB 1U
+
+#define XSDPS_WIDTH_8 8U
+#define XSDPS_WIDTH_4 4U
+
+
+#if defined (ARMR5) || defined (__aarch64__) || defined (ARMA53_32) || defined (__MICROBLAZE__)
+#ifdef versal
+#define SD_ITAPDLY_SEL_MASK 0x000000FFU
+#define SD_OTAPDLY_SEL_MASK 0x0000003FU
+#define SD_ITAPDLY 0x0000F0F8U
+#define SD_OTAPDLY 0x0000F0FCU
+#define SD_ITAPCHGWIN 0x00000200U
+#define SD_ITAPDLYENA 0x00000100U
+#define SD_OTAPDLYENA 0x00000040U
+#define SD_OTAPDLYSEL_HS200_B0 0x00000002U
+#define SD_OTAPDLYSEL_HS200_B2 0x00000002U
+#define SD_ITAPDLYSEL_SD50 0x0000000EU
+#define SD_OTAPDLYSEL_SD50 0x00000003U
+#define SD_ITAPDLYSEL_SD_DDR50 0x00000036U
+#define SD_ITAPDLYSEL_EMMC_DDR50 0x0000001EU
+#define SD_OTAPDLYSEL_SD_DDR50 0x00000003U
+#define SD_OTAPDLYSEL_EMMC_DDR50 0x00000005U
+#define SD_ITAPDLYSEL_HSD 0x0000002CU
+#define SD_OTAPDLYSEL_SD_HSD 0x00000004U
+#define SD_OTAPDLYSEL_EMMC_HSD 0x00000005U
+#else
+#define SD0_ITAPDLY_SEL_MASK 0x000000FFU
+#define SD0_OTAPDLY_SEL_MASK 0x0000003FU
+#define SD1_ITAPDLY_SEL_MASK 0x00FF0000U
+#define SD1_OTAPDLY_SEL_MASK 0x003F0000U
+#define SD_DLL_CTRL 0x00000358U
+#define SD_ITAPDLY 0x00000314U
+#define SD_OTAPDLY 0x00000318U
+#define SD0_DLL_RST 0x00000004U
+#define SD1_DLL_RST 0x00040000U
+#define SD0_ITAPCHGWIN 0x00000200U
+#define SD0_ITAPDLYENA 0x00000100U
+#define SD0_OTAPDLYENA 0x00000040U
+#define SD1_ITAPCHGWIN 0x02000000U
+#define SD1_ITAPDLYENA 0x01000000U
+#define SD1_OTAPDLYENA 0x00400000U
+#define SD_OTAPDLYSEL_HS200_B0 0x00000003U
+#define SD_OTAPDLYSEL_HS200_B2 0x00000002U
+#define SD_ITAPDLYSEL_SD50 0x00000014U
+#define SD_OTAPDLYSEL_SD50 0x00000003U
+#define SD_ITAPDLYSEL_SD_DDR50 0x0000003DU
+#define SD_ITAPDLYSEL_EMMC_DDR50 0x00000012U
+#define SD_OTAPDLYSEL_SD_DDR50 0x00000004U
+#define SD_OTAPDLYSEL_EMMC_DDR50 0x00000006U
+#define SD_ITAPDLYSEL_HSD 0x00000015U
+#define SD_OTAPDLYSEL_SD_HSD 0x00000005U
+#define SD_OTAPDLYSEL_EMMC_HSD 0x00000006U
+#endif
+
+#endif
+
+#ifdef __MICROBLAZE__
+#define XPS_SYS_CTRL_BASEADDR 0xFF180000U
+#endif
+
+/**************************** Type Definitions *******************************/
+
+/***************** Macros (Inline Functions) Definitions *********************/
+#define XSdPs_In64 Xil_In64
+#define XSdPs_Out64 Xil_Out64
+
+#define XSdPs_In32 Xil_In32
+#define XSdPs_Out32 Xil_Out32
+
+#define XSdPs_In16 Xil_In16
+#define XSdPs_Out16 Xil_Out16
+
+#define XSdPs_In8 Xil_In8
+#define XSdPs_Out8 Xil_Out8
+
+/****************************************************************************/
+/**
+* Read a register.
+*
+* @param InstancePtr is the pointer to the sdps instance.
+* @param RegOffset contains the offset from the 1st register of the
+* device to the target register.
+*
+* @return The value read from the register.
+*
+* @note C-Style signature:
+* u32 XSdPs_ReadReg(XSdPs *InstancePtr. s32 RegOffset)
+*
+******************************************************************************/
+#define XSdPs_ReadReg64(InstancePtr, RegOffset) \
+ XSdPs_In64((InstancePtr->Config.BaseAddress) + RegOffset)
+
+/***************************************************************************/
+/**
+* Write to a register.
+*
+* @param InstancePtr is the pointer to the sdps instance.
+* @param RegOffset contains the offset from the 1st register of the
+* device to target register.
+* @param RegisterValue is the value to be written to the register.
+*
+* @return None.
+*
+* @note C-Style signature:
+* void XSdPs_WriteReg(XSdPs *InstancePtr, s32 RegOffset,
+* u64 RegisterValue)
+*
+******************************************************************************/
+#define XSdPs_WriteReg64(InstancePtr, RegOffset, RegisterValue) \
+ XSdPs_Out64((InstancePtr->Config.BaseAddress) + (RegOffset), \
+ (RegisterValue))
+
+/****************************************************************************/
+/**
+* Read a register.
+*
+* @param BaseAddress contains the base address of the device.
+* @param RegOffset contains the offset from the 1st register of the
+* device to the target register.
+*
+* @return The value read from the register.
+*
+* @note C-Style signature:
+* u32 XSdPs_ReadReg(u32 BaseAddress. int RegOffset)
+*
+******************************************************************************/
+#define XSdPs_ReadReg(BaseAddress, RegOffset) \
+ XSdPs_In32((BaseAddress) + (RegOffset))
+
+/***************************************************************************/
+/**
+* Write to a register.
+*
+* @param BaseAddress contains the base address of the device.
+* @param RegOffset contains the offset from the 1st register of the
+* device to target register.
+* @param RegisterValue is the value to be written to the register.
+*
+* @return None.
+*
+* @note C-Style signature:
+* void XSdPs_WriteReg(u32 BaseAddress, int RegOffset,
+* u32 RegisterValue)
+*
+******************************************************************************/
+#define XSdPs_WriteReg(BaseAddress, RegOffset, RegisterValue) \
+ XSdPs_Out32((BaseAddress) + (RegOffset), (RegisterValue))
+
+/****************************************************************************/
+/**
+* Read a register.
+*
+* @param BaseAddress contains the base address of the device.
+* @param RegOffset contains the offset from the 1st register of the
+* device to the target register.
+*
+* @return The value read from the register.
+*
+* @note C-Style signature:
+* u16 XSdPs_ReadReg(u32 BaseAddress. int RegOffset)
+*
+******************************************************************************/
+static INLINE u16 XSdPs_ReadReg16(u32 BaseAddress, u8 RegOffset)
+{
+#if defined (__MICROBLAZE__)
+ u32 Reg;
+ BaseAddress += RegOffset & 0xFC;
+ Reg = XSdPs_In32(BaseAddress);
+ Reg >>= ((RegOffset & 0x3)*8);
+ return (u16)Reg;
+#else
+ return XSdPs_In16((BaseAddress) + (RegOffset));
+#endif
+}
+
+/***************************************************************************/
+/**
+* Write to a register.
+*
+* @param BaseAddress contains the base address of the device.
+* @param RegOffset contains the offset from the 1st register of the
+* device to target register.
+* @param RegisterValue is the value to be written to the register.
+*
+* @return None.
+*
+* @note C-Style signature:
+* void XSdPs_WriteReg(u32 BaseAddress, int RegOffset,
+* u16 RegisterValue)
+*
+******************************************************************************/
+
+static INLINE void XSdPs_WriteReg16(u32 BaseAddress, u8 RegOffset, u16 RegisterValue)
+{
+#if defined (__MICROBLAZE__)
+ u32 Reg;
+ BaseAddress += RegOffset & 0xFC;
+ Reg = XSdPs_In32(BaseAddress);
+ Reg &= ~(0xFFFF<<((RegOffset & 0x3)*8));
+ Reg |= RegisterValue <<((RegOffset & 0x3)*8);
+ XSdPs_Out32(BaseAddress, Reg);
+#else
+ XSdPs_Out16((BaseAddress) + (RegOffset), (RegisterValue));
+#endif
+}
+
+/****************************************************************************/
+/**
+* Read a register.
+*
+* @param BaseAddress contains the base address of the device.
+* @param RegOffset contains the offset from the 1st register of the
+* device to the target register.
+*
+* @return The value read from the register.
+*
+* @note C-Style signature:
+* u8 XSdPs_ReadReg(u32 BaseAddress. int RegOffset)
+*
+******************************************************************************/
+static INLINE u8 XSdPs_ReadReg8(u32 BaseAddress, u8 RegOffset)
+{
+#if defined (__MICROBLAZE__)
+ u32 Reg;
+ BaseAddress += RegOffset & 0xFC;
+ Reg = XSdPs_In32(BaseAddress);
+ Reg >>= ((RegOffset & 0x3)*8);
+ return (u8)Reg;
+#else
+ return XSdPs_In8((BaseAddress) + (RegOffset));
+#endif
+}
+/***************************************************************************/
+/**
+* Write to a register.
+*
+* @param BaseAddress contains the base address of the device.
+* @param RegOffset contains the offset from the 1st register of the
+* device to target register.
+* @param RegisterValue is the value to be written to the register.
+*
+* @return None.
+*
+* @note C-Style signature:
+* void XSdPs_WriteReg(u32 BaseAddress, int RegOffset,
+* u8 RegisterValue)
+*
+******************************************************************************/
+static INLINE void XSdPs_WriteReg8(u32 BaseAddress, u8 RegOffset, u8 RegisterValue)
+{
+#if defined (__MICROBLAZE__)
+ u32 Reg;
+ BaseAddress += RegOffset & 0xFC;
+ Reg = XSdPs_In32(BaseAddress);
+ Reg &= ~(0xFF<<((RegOffset & 0x3)*8));
+ Reg |= RegisterValue <<((RegOffset & 0x3)*8);
+ XSdPs_Out32(BaseAddress, Reg);
+#else
+ XSdPs_Out8((BaseAddress) + (RegOffset), (RegisterValue));
+#endif
+}
+/***************************************************************************/
+/**
+* Macro to get present status register
+*
+* @param BaseAddress contains the base address of the device.
+*
+* @return None.
+*
+* @note C-Style signature:
+* void XSdPs_WriteReg(u32 BaseAddress, int RegOffset,
+* u8 RegisterValue)
+*
+******************************************************************************/
+#define XSdPs_GetPresentStatusReg(BaseAddress) \
+ XSdPs_In32((BaseAddress) + (XSDPS_PRES_STATE_OFFSET))
+
+/************************** Function Prototypes ******************************/
+
+/************************** Variable Definitions *****************************/
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* SD_HW_H_ */
+/** @} */
diff --git a/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/sdps_v3_8/src/xsdps_options.c b/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/sdps_v3_8/src/xsdps_options.c
new file mode 100644
index 0000000..d59864f
--- /dev/null
+++ b/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/sdps_v3_8/src/xsdps_options.c
@@ -0,0 +1,1600 @@
+/******************************************************************************
+*
+* Copyright (C) 2013 - 2019 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+* THE SOFTWARE.
+*
+*
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xsdps_options.c
+* @addtogroup sdps_v3_8
+* @{
+*
+* Contains API's for changing the various options in host and card.
+* See xsdps.h for a detailed description of the device and driver.
+*
+* <pre>
+* MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ----- --- -------- -----------------------------------------------
+* 1.00a hk/sg 10/17/13 Initial release
+* 2.1 hk 04/18/14 Increase sleep for eMMC switch command.
+* Add sleep for microblaze designs. CR# 781117.
+* 2.3 sk 09/23/14 Use XSdPs_Change_ClkFreq API whenever changing
+* clock.CR# 816586.
+* 2.5 sg 07/09/15 Added SD 3.0 features
+* kvn 07/15/15 Modified the code according to MISRAC-2012.
+* 2.7 sk 01/08/16 Added workaround for issue in auto tuning mode
+* of SDR50, SDR104 and HS200.
+* sk 02/16/16 Corrected the Tuning logic.
+* sk 03/02/16 Configured the Tap Delay values for eMMC HS200 mode.
+* 2.8 sk 04/20/16 Added new workaround for auto tuning.
+* 3.0 sk 07/07/16 Used usleep API for both arm and microblaze.
+* sk 07/16/16 Added support for UHS modes.
+* sk 07/16/16 Added Tap delays accordingly to different SD/eMMC
+* operating modes.
+* 3.1 mi 09/07/16 Removed compilation warnings with extra compiler flags.
+* sk 11/07/16 Enable Rst_n bit in ext_csd reg if not enabled.
+* sk 11/16/16 Issue DLL reset at 31 iteration to load new zero value.
+* 3.2 sk 02/01/17 Added HSD and DDR mode support for eMMC.
+* sk 02/01/17 Consider bus width parameter from design for switching
+* vns 02/09/17 Added ARMA53_32 support for ZynqMP CR#968397
+* vns 03/13/17 Fixed MISRAC mandatory violation
+* sk 03/20/17 Add support for EL1 non-secure mode.
+* 3.3 mn 07/25/17 Removed SD0_OTAPDLYENA and SD1_OTAPDLYENA bits
+* mn 08/07/17 Properly set OTAPDLY value by clearing previous bit
+* settings
+* mn 08/17/17 Added CCI support for A53 and disabled data cache
+* operations when it is enabled.
+* mn 08/22/17 Updated for Word Access System support
+* 3.4 mn 01/22/18 Separated out SDR104 and HS200 clock defines
+* 3.6 mn 07/06/18 Fix Cppcheck warnings for sdps driver
+* 3.7 aru 03/12/19 Modified the code according to MISRAC-2012.
+* mn 03/27/19 Disable calls to dll_reset API for versal SPP Platforms
+* 3.8 mn 04/12/19 Modified TapDelay code for supporting ZynqMP and Versal
+* mn 05/21/19 Set correct tap delays for Versal
+* mn 05/21/19 Disable DLL Reset code for Versal
+* mn 08/29/19 Add call to Cache Invalidation API in XSdPs_Get_BusWidth
+*
+* </pre>
+*
+******************************************************************************/
+
+/***************************** Include Files *********************************/
+#include "xsdps.h"
+#include "sleep.h"
+#if defined (__aarch64__)
+#include "xil_smc.h"
+#endif
+/************************** Constant Definitions *****************************/
+#define UHS_SDR12_SUPPORT 0x1U
+#define UHS_SDR25_SUPPORT 0x2U
+#define UHS_SDR50_SUPPORT 0x4U
+#define UHS_SDR104_SUPPORT 0x8U
+#define UHS_DDR50_SUPPORT 0x10U
+/**************************** Type Definitions *******************************/
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/************************** Function Prototypes ******************************/
+s32 XSdPs_CmdTransfer(XSdPs *InstancePtr, u32 Cmd, u32 Arg, u32 BlkCnt);
+void XSdPs_SetupADMA2DescTbl(XSdPs *InstancePtr, u32 BlkCnt, const u8 *Buff);
+static s32 XSdPs_Execute_Tuning(XSdPs *InstancePtr);
+#if defined (ARMR5) || defined (__aarch64__) || defined (ARMA53_32) || defined (__MICROBLAZE__)
+s32 XSdPs_Uhs_ModeInit(XSdPs *InstancePtr, u8 Mode);
+void XSdPs_SetTapDelay(XSdPs *InstancePtr);
+#ifndef versal
+static void XSdPs_DllReset(XSdPs *InstancePtr);
+#endif
+#endif
+
+extern u16 TransferMode;
+/*****************************************************************************/
+/**
+* Update Block size for read/write operations.
+*
+* @param InstancePtr is a pointer to the instance to be worked on.
+* @param BlkSize - Block size passed by the user.
+*
+* @return None
+*
+******************************************************************************/
+s32 XSdPs_SetBlkSize(XSdPs *InstancePtr, u16 BlkSize)
+{
+ s32 Status;
+ u32 PresentStateReg;
+
+ Xil_AssertNonvoid(InstancePtr != NULL);
+ Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+ PresentStateReg = XSdPs_ReadReg(InstancePtr->Config.BaseAddress,
+ XSDPS_PRES_STATE_OFFSET);
+
+ if ((PresentStateReg & ((u32)XSDPS_PSR_INHIBIT_CMD_MASK |
+ (u32)XSDPS_PSR_INHIBIT_DAT_MASK |
+ (u32)XSDPS_PSR_WR_ACTIVE_MASK | (u32)XSDPS_PSR_RD_ACTIVE_MASK)) != 0U) {
+ Status = XST_FAILURE;
+ goto RETURN_PATH;
+ }
+
+
+ /* Send block write command */
+ Status = XSdPs_CmdTransfer(InstancePtr, CMD16, BlkSize, 0U);
+ if (Status != XST_SUCCESS) {
+ Status = XST_FAILURE;
+ goto RETURN_PATH;
+ }
+
+ /* Set block size to the value passed */
+ XSdPs_WriteReg16(InstancePtr->Config.BaseAddress, XSDPS_BLK_SIZE_OFFSET,
+ BlkSize & XSDPS_BLK_SIZE_MASK);
+
+ Status = XST_SUCCESS;
+
+ RETURN_PATH:
+ return Status;
+
+}
+
+/*****************************************************************************/
+/**
+*
+* API to get bus width support by card.
+*
+*
+* @param InstancePtr is a pointer to the XSdPs instance.
+* @param SCR - buffer to store SCR register returned by card.
+*
+* @return
+* - XST_SUCCESS if successful.
+* - XST_FAILURE if fail.
+*
+* @note None.
+*
+******************************************************************************/
+s32 XSdPs_Get_BusWidth(XSdPs *InstancePtr, u8 *ReadBuff)
+{
+ s32 Status;
+ u32 StatusReg;
+ u16 BlkCnt;
+ u16 BlkSize;
+ s32 LoopCnt;
+
+ Xil_AssertNonvoid(InstancePtr != NULL);
+ Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+ for (LoopCnt = 0; LoopCnt < 8; LoopCnt++) {
+ ReadBuff[LoopCnt] = 0U;
+ }
+
+ /* Send block write command */
+ Status = XSdPs_CmdTransfer(InstancePtr, CMD55,
+ InstancePtr->RelCardAddr, 0U);
+ if (Status != XST_SUCCESS) {
+ Status = XST_FAILURE;
+ goto RETURN_PATH;
+ }
+
+ BlkCnt = XSDPS_SCR_BLKCNT;
+ BlkSize = XSDPS_SCR_BLKSIZE;
+
+ /* Set block size to the value passed */
+ BlkSize &= XSDPS_BLK_SIZE_MASK;
+ XSdPs_WriteReg16(InstancePtr->Config.BaseAddress,
+ XSDPS_BLK_SIZE_OFFSET, BlkSize);
+
+ XSdPs_SetupADMA2DescTbl(InstancePtr, BlkCnt, ReadBuff);
+
+ TransferMode = XSDPS_TM_DAT_DIR_SEL_MASK | XSDPS_TM_DMA_EN_MASK;
+
+ if (InstancePtr->Config.IsCacheCoherent == 0U) {
+ Xil_DCacheInvalidateRange((INTPTR)ReadBuff, 8);
+ }
+
+ Status = XSdPs_CmdTransfer(InstancePtr, ACMD51, 0U, BlkCnt);
+ if (Status != XST_SUCCESS) {
+ Status = XST_FAILURE;
+ goto RETURN_PATH;
+ }
+
+ /*
+ * Check for transfer complete
+ * Polling for response for now
+ */
+ do {
+ StatusReg = XSdPs_ReadReg16(InstancePtr->Config.BaseAddress,
+ XSDPS_NORM_INTR_STS_OFFSET);
+ if ((StatusReg & XSDPS_INTR_ERR_MASK) != 0U) {
+ /* Write to clear error bits */
+ XSdPs_WriteReg16(InstancePtr->Config.BaseAddress,
+ XSDPS_ERR_INTR_STS_OFFSET,
+ XSDPS_ERROR_INTR_ALL_MASK);
+ Status = XST_FAILURE;
+ goto RETURN_PATH;
+ }
+ } while ((StatusReg & XSDPS_INTR_TC_MASK) == 0U);
+
+ /* Write to clear bit */
+ XSdPs_WriteReg16(InstancePtr->Config.BaseAddress,
+ XSDPS_NORM_INTR_STS_OFFSET, XSDPS_INTR_TC_MASK);
+
+ if (InstancePtr->Config.IsCacheCoherent == 0U) {
+ Xil_DCacheInvalidateRange((INTPTR)ReadBuff, 8);
+ }
+
+ Status = XST_SUCCESS;
+
+ RETURN_PATH:
+ return Status;
+
+}
+
+/*****************************************************************************/
+/**
+*
+* API to set bus width to 4-bit in card and host
+*
+*
+* @param InstancePtr is a pointer to the XSdPs instance.
+*
+* @return
+* - XST_SUCCESS if successful.
+* - XST_FAILURE if fail.
+*
+* @note None.
+*
+******************************************************************************/
+s32 XSdPs_Change_BusWidth(XSdPs *InstancePtr)
+{
+ s32 Status;
+ u32 StatusReg;
+ u32 Arg;
+
+ Xil_AssertNonvoid(InstancePtr != NULL);
+ Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+
+ /*
+ * check for bus width for 3.0 controller and return if
+ * bus width is <4
+ */
+ if ((InstancePtr->HC_Version == XSDPS_HC_SPEC_V3) &&
+ (InstancePtr->Config.BusWidth < XSDPS_WIDTH_4)) {
+ Status = XST_SUCCESS;
+ goto RETURN_PATH;
+ }
+
+ if (InstancePtr->CardType == XSDPS_CARD_SD) {
+
+ Status = XSdPs_CmdTransfer(InstancePtr, CMD55, InstancePtr->RelCardAddr,
+ 0U);
+ if (Status != XST_SUCCESS) {
+ Status = XST_FAILURE;
+ goto RETURN_PATH;
+ }
+
+ InstancePtr->BusWidth = XSDPS_4_BIT_WIDTH;
+
+ Arg = ((u32)InstancePtr->BusWidth);
+
+ Status = XSdPs_CmdTransfer(InstancePtr, ACMD6, Arg, 0U);
+ if (Status != XST_SUCCESS) {
+ Status = XST_FAILURE;
+ goto RETURN_PATH;
+ }
+ } else {
+
+ if ((InstancePtr->HC_Version == XSDPS_HC_SPEC_V3)
+ && (InstancePtr->CardType == XSDPS_CHIP_EMMC) &&
+ (InstancePtr->Config.BusWidth == XSDPS_WIDTH_8)) {
+ /* in case of eMMC data width 8-bit */
+ InstancePtr->BusWidth = XSDPS_8_BIT_WIDTH;
+ } else {
+ InstancePtr->BusWidth = XSDPS_4_BIT_WIDTH;
+ }
+
+ if (InstancePtr->BusWidth == XSDPS_8_BIT_WIDTH) {
+ if (InstancePtr->Mode == XSDPS_DDR52_MODE) {
+ Arg = XSDPS_MMC_DDR_8_BIT_BUS_ARG;
+ } else {
+ Arg = XSDPS_MMC_8_BIT_BUS_ARG;
+ }
+ } else {
+ if (InstancePtr->Mode == XSDPS_DDR52_MODE) {
+ Arg = XSDPS_MMC_DDR_4_BIT_BUS_ARG;
+ } else {
+ Arg = XSDPS_MMC_4_BIT_BUS_ARG;
+ }
+ }
+
+ Status = XSdPs_CmdTransfer(InstancePtr, CMD6, Arg, 0U);
+ if (Status != XST_SUCCESS) {
+ Status = XST_FAILURE;
+ goto RETURN_PATH;
+ }
+
+ /* Check for transfer complete */
+ do {
+ StatusReg = XSdPs_ReadReg16(InstancePtr->Config.BaseAddress,
+ XSDPS_NORM_INTR_STS_OFFSET);
+ if ((StatusReg & XSDPS_INTR_ERR_MASK) != 0U) {
+ /* Write to clear error bits */
+ XSdPs_WriteReg16(InstancePtr->Config.BaseAddress,
+ XSDPS_ERR_INTR_STS_OFFSET,
+ XSDPS_ERROR_INTR_ALL_MASK);
+ Status = XST_FAILURE;
+ goto RETURN_PATH;
+ }
+ } while((StatusReg & XSDPS_INTR_TC_MASK) == 0U);
+
+ /* Write to clear bit */
+ XSdPs_WriteReg16(InstancePtr->Config.BaseAddress,
+ XSDPS_NORM_INTR_STS_OFFSET, XSDPS_INTR_TC_MASK);
+ }
+
+ usleep(XSDPS_MMC_DELAY_FOR_SWITCH);
+
+ StatusReg = XSdPs_ReadReg8(InstancePtr->Config.BaseAddress,
+ XSDPS_HOST_CTRL1_OFFSET);
+
+ /* Width setting in controller */
+ if (InstancePtr->BusWidth == XSDPS_8_BIT_WIDTH) {
+ StatusReg |= XSDPS_HC_EXT_BUS_WIDTH;
+ } else {
+ StatusReg |= XSDPS_HC_WIDTH_MASK;
+ }
+
+ XSdPs_WriteReg8(InstancePtr->Config.BaseAddress,
+ XSDPS_HOST_CTRL1_OFFSET,
+ (u8)StatusReg);
+
+ if (InstancePtr->Mode == XSDPS_DDR52_MODE) {
+ StatusReg = XSdPs_ReadReg16(InstancePtr->Config.BaseAddress,
+ XSDPS_HOST_CTRL2_OFFSET);
+ StatusReg &= (u32)(~XSDPS_HC2_UHS_MODE_MASK);
+ StatusReg |= InstancePtr->Mode;
+ XSdPs_WriteReg16(InstancePtr->Config.BaseAddress,
+ XSDPS_HOST_CTRL2_OFFSET, (u16)StatusReg);
+ }
+
+ Status = XST_SUCCESS;
+
+ RETURN_PATH:
+ return Status;
+
+}
+
+/*****************************************************************************/
+/**
+*
+* API to get bus speed supported by card.
+*
+*
+* @param InstancePtr is a pointer to the XSdPs instance.
+* @param ReadBuff - buffer to store function group support data
+* returned by card.
+*
+* @return
+* - XST_SUCCESS if successful.
+* - XST_FAILURE if fail.
+*
+* @note None.
+*
+******************************************************************************/
+s32 XSdPs_Get_BusSpeed(XSdPs *InstancePtr, u8 *ReadBuff)
+{
+ s32 Status;
+ u32 StatusReg;
+ u32 Arg;
+ u16 BlkCnt;
+ u16 BlkSize;
+ s32 LoopCnt;
+
+ Xil_AssertNonvoid(InstancePtr != NULL);
+ Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+ for (LoopCnt = 0; LoopCnt < 64; LoopCnt++) {
+ ReadBuff[LoopCnt] = 0U;
+ }
+
+ BlkCnt = XSDPS_SWITCH_CMD_BLKCNT;
+ BlkSize = XSDPS_SWITCH_CMD_BLKSIZE;
+ BlkSize &= XSDPS_BLK_SIZE_MASK;
+ XSdPs_WriteReg16(InstancePtr->Config.BaseAddress,
+ XSDPS_BLK_SIZE_OFFSET, BlkSize);
+
+ XSdPs_SetupADMA2DescTbl(InstancePtr, BlkCnt, ReadBuff);
+
+ TransferMode = XSDPS_TM_DAT_DIR_SEL_MASK | XSDPS_TM_DMA_EN_MASK;
+
+ Arg = XSDPS_SWITCH_CMD_HS_GET;
+
+ if (InstancePtr->Config.IsCacheCoherent == 0U) {
+ Xil_DCacheInvalidateRange((INTPTR)ReadBuff, 64);
+ }
+
+ Status = XSdPs_CmdTransfer(InstancePtr, CMD6, Arg, 1U);
+ if (Status != XST_SUCCESS) {
+ Status = XST_FAILURE;
+ goto RETURN_PATH;
+ }
+
+ /*
+ * Check for transfer complete
+ * Polling for response for now
+ */
+ do {
+ StatusReg = XSdPs_ReadReg16(InstancePtr->Config.BaseAddress,
+ XSDPS_NORM_INTR_STS_OFFSET);
+ if ((StatusReg & XSDPS_INTR_ERR_MASK) != 0U) {
+ /* Write to clear error bits */
+ XSdPs_WriteReg16(InstancePtr->Config.BaseAddress,
+ XSDPS_ERR_INTR_STS_OFFSET,
+ XSDPS_ERROR_INTR_ALL_MASK);
+ Status = XST_FAILURE;
+ goto RETURN_PATH;
+ }
+ } while ((StatusReg & XSDPS_INTR_TC_MASK) == 0U);
+
+ /* Write to clear bit */
+ XSdPs_WriteReg16(InstancePtr->Config.BaseAddress,
+ XSDPS_NORM_INTR_STS_OFFSET, XSDPS_INTR_TC_MASK);
+
+ if (InstancePtr->Config.IsCacheCoherent == 0U) {
+ Xil_DCacheInvalidateRange((INTPTR)ReadBuff, 64U);
+ }
+
+ Status = XST_SUCCESS;
+
+ RETURN_PATH:
+ return Status;
+
+}
+
+/*****************************************************************************/
+/**
+*
+* API to get SD card status information.
+*
+*
+* @param InstancePtr is a pointer to the XSdPs instance.
+* @param SdStatReg - buffer to store status data returned by card.
+*
+* @return
+* - XST_SUCCESS if successful.
+* - XST_FAILURE if fail.
+*
+* @note None.
+*
+******************************************************************************/
+s32 XSdPs_Get_Status(XSdPs *InstancePtr, u8 *SdStatReg)
+{
+ s32 Status;
+ u32 StatusReg;
+ u16 BlkCnt;
+ u16 BlkSize;
+
+ Xil_AssertNonvoid(InstancePtr != NULL);
+ Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+ /* Send block write command */
+ Status = XSdPs_CmdTransfer(InstancePtr, CMD55,
+ InstancePtr->RelCardAddr, 0U);
+ if (Status != XST_SUCCESS) {
+ Status = XST_FAILURE;
+ goto RETURN_PATH;
+ }
+
+ BlkCnt = 1;
+ BlkSize = 64;
+
+ /* Set block size to the value passed */
+ BlkSize &= XSDPS_BLK_SIZE_MASK;
+ XSdPs_WriteReg16(InstancePtr->Config.BaseAddress,
+ XSDPS_BLK_SIZE_OFFSET, BlkSize);
+
+ XSdPs_SetupADMA2DescTbl(InstancePtr, BlkCnt, SdStatReg);
+
+ TransferMode = XSDPS_TM_DAT_DIR_SEL_MASK | XSDPS_TM_DMA_EN_MASK;
+
+ if (InstancePtr->Config.IsCacheCoherent == 0U) {
+ Xil_DCacheInvalidateRange((INTPTR)SdStatReg, 64);
+ }
+
+ Status = XSdPs_CmdTransfer(InstancePtr, ACMD13, 0U, BlkCnt);
+ if (Status != XST_SUCCESS) {
+ Status = XST_FAILURE;
+ goto RETURN_PATH;
+ }
+
+ /*
+ * Check for transfer complete
+ * Polling for response for now
+ */
+ do {
+ StatusReg = XSdPs_ReadReg16(InstancePtr->Config.BaseAddress,
+ XSDPS_NORM_INTR_STS_OFFSET);
+ if ((StatusReg & XSDPS_INTR_ERR_MASK) != 0U) {
+ /* Write to clear error bits */
+ XSdPs_WriteReg16(InstancePtr->Config.BaseAddress,
+ XSDPS_ERR_INTR_STS_OFFSET,
+ XSDPS_ERROR_INTR_ALL_MASK);
+ Status = XST_FAILURE;
+ goto RETURN_PATH;
+ }
+ } while ((StatusReg & XSDPS_INTR_TC_MASK) == 0U);
+
+ /* Write to clear bit */
+ XSdPs_WriteReg16(InstancePtr->Config.BaseAddress,
+ XSDPS_NORM_INTR_STS_OFFSET, XSDPS_INTR_TC_MASK);
+
+ if (InstancePtr->Config.IsCacheCoherent == 0U) {
+ Xil_DCacheInvalidateRange((INTPTR)SdStatReg, 64U);
+ }
+
+ Status = XST_SUCCESS;
+
+ RETURN_PATH:
+ return Status;
+}
+
+/*****************************************************************************/
+/**
+*
+* API to set high speed in card and host. Changes clock in host accordingly.
+*
+*
+* @param InstancePtr is a pointer to the XSdPs instance.
+*
+* @return
+* - XST_SUCCESS if successful.
+* - XST_FAILURE if fail.
+*
+* @note None.
+*
+******************************************************************************/
+s32 XSdPs_Change_BusSpeed(XSdPs *InstancePtr)
+{
+ s32 Status;
+ u32 StatusReg;
+ u32 Arg;
+ u16 BlkCnt;
+ u16 BlkSize;
+ u8 ReadBuff[64] = {0U};
+
+ Xil_AssertNonvoid(InstancePtr != NULL);
+ Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+ if (InstancePtr->CardType == XSDPS_CARD_SD) {
+
+ BlkCnt = XSDPS_SWITCH_CMD_BLKCNT;
+ BlkSize = XSDPS_SWITCH_CMD_BLKSIZE;
+ BlkSize &= XSDPS_BLK_SIZE_MASK;
+ XSdPs_WriteReg16(InstancePtr->Config.BaseAddress,
+ XSDPS_BLK_SIZE_OFFSET, BlkSize);
+
+ XSdPs_SetupADMA2DescTbl(InstancePtr, BlkCnt, ReadBuff);
+
+ if (InstancePtr->Config.IsCacheCoherent == 0U) {
+ Xil_DCacheFlushRange((INTPTR)ReadBuff, 64);
+ }
+
+ TransferMode = XSDPS_TM_DAT_DIR_SEL_MASK | XSDPS_TM_DMA_EN_MASK;
+
+ Arg = XSDPS_SWITCH_CMD_HS_SET;
+
+ Status = XSdPs_CmdTransfer(InstancePtr, CMD6, Arg, 1U);
+ if (Status != XST_SUCCESS) {
+ Status = XST_FAILURE;
+ goto RETURN_PATH;
+ }
+
+ /*
+ * Check for transfer complete
+ * Polling for response for now
+ */
+ do {
+ StatusReg = XSdPs_ReadReg16(InstancePtr->Config.BaseAddress,
+ XSDPS_NORM_INTR_STS_OFFSET);
+ if ((StatusReg & XSDPS_INTR_ERR_MASK) != 0U) {
+ /* Write to clear error bits */
+ XSdPs_WriteReg16(InstancePtr->Config.BaseAddress,
+ XSDPS_ERR_INTR_STS_OFFSET,
+ XSDPS_ERROR_INTR_ALL_MASK);
+ Status = XST_FAILURE;
+ goto RETURN_PATH;
+ }
+ } while ((StatusReg & XSDPS_INTR_TC_MASK) == 0U);
+
+ /* Write to clear bit */
+ XSdPs_WriteReg16(InstancePtr->Config.BaseAddress,
+ XSDPS_NORM_INTR_STS_OFFSET, XSDPS_INTR_TC_MASK);
+
+ /* Change the clock frequency to 50 MHz */
+ InstancePtr->BusSpeed = XSDPS_CLK_50_MHZ;
+ Status = XSdPs_Change_ClkFreq(InstancePtr, InstancePtr->BusSpeed);
+ if (Status != XST_SUCCESS) {
+ Status = XST_FAILURE;
+ goto RETURN_PATH;
+ }
+
+ } else if (InstancePtr->CardType == XSDPS_CARD_MMC) {
+ Arg = XSDPS_MMC_HIGH_SPEED_ARG;
+
+ Status = XSdPs_CmdTransfer(InstancePtr, CMD6, Arg, 0U);
+ if (Status != XST_SUCCESS) {
+ Status = XST_FAILURE;
+ goto RETURN_PATH;
+ }
+
+ /*
+ * Check for transfer complete
+ */
+ do {
+ StatusReg = XSdPs_ReadReg16(InstancePtr->Config.BaseAddress,
+ XSDPS_NORM_INTR_STS_OFFSET);
+ if ((StatusReg & XSDPS_INTR_ERR_MASK) != 0U) {
+ /*
+ * Write to clear error bits
+ */
+ XSdPs_WriteReg16(InstancePtr->Config.BaseAddress,
+ XSDPS_ERR_INTR_STS_OFFSET,
+ XSDPS_ERROR_INTR_ALL_MASK);
+ Status = XST_FAILURE;
+ goto RETURN_PATH;
+ }
+ } while ((StatusReg & XSDPS_INTR_TC_MASK) == 0U);
+
+ /*
+ * Write to clear bit
+ */
+ XSdPs_WriteReg16(InstancePtr->Config.BaseAddress,
+ XSDPS_NORM_INTR_STS_OFFSET, XSDPS_INTR_TC_MASK);
+
+ /* Change the clock frequency to 52 MHz */
+ InstancePtr->BusSpeed = XSDPS_CLK_52_MHZ;
+ Status = XSdPs_Change_ClkFreq(InstancePtr, XSDPS_CLK_52_MHZ);
+ if (Status != XST_SUCCESS) {
+ Status = XST_FAILURE;
+ goto RETURN_PATH;
+ }
+ } else {
+ if (InstancePtr->Mode == XSDPS_HS200_MODE) {
+ Arg = XSDPS_MMC_HS200_ARG;
+ InstancePtr->BusSpeed = XSDPS_MMC_HS200_MAX_CLK;
+ } else if (InstancePtr->Mode == XSDPS_DDR52_MODE) {
+ Arg = XSDPS_MMC_HIGH_SPEED_ARG;
+ InstancePtr->BusSpeed = XSDPS_MMC_DDR_MAX_CLK;
+ } else {
+ Arg = XSDPS_MMC_HIGH_SPEED_ARG;
+ InstancePtr->BusSpeed = XSDPS_MMC_HSD_MAX_CLK;
+ }
+
+ Status = XSdPs_CmdTransfer(InstancePtr, CMD6, Arg, 0U);
+ if (Status != XST_SUCCESS) {
+ Status = XST_FAILURE;
+ goto RETURN_PATH;
+ }
+
+ /*
+ * Check for transfer complete
+ */
+ do {
+ StatusReg = XSdPs_ReadReg16(InstancePtr->Config.BaseAddress,
+ XSDPS_NORM_INTR_STS_OFFSET);
+ if ((StatusReg & XSDPS_INTR_ERR_MASK) != 0U) {
+ /*
+ * Write to clear error bits
+ */
+ XSdPs_WriteReg16(InstancePtr->Config.BaseAddress,
+ XSDPS_ERR_INTR_STS_OFFSET,
+ XSDPS_ERROR_INTR_ALL_MASK);
+ Status = XST_FAILURE;
+ goto RETURN_PATH;
+ }
+ } while ((StatusReg & XSDPS_INTR_TC_MASK) == 0U);
+
+ /*
+ * Write to clear bit
+ */
+ XSdPs_WriteReg16(InstancePtr->Config.BaseAddress,
+ XSDPS_NORM_INTR_STS_OFFSET, XSDPS_INTR_TC_MASK);
+
+ Status = XSdPs_Change_ClkFreq(InstancePtr, InstancePtr->BusSpeed);
+ if (Status != XST_SUCCESS) {
+ Status = XST_FAILURE;
+ goto RETURN_PATH;
+ }
+
+ if (InstancePtr->Mode == XSDPS_HS200_MODE) {
+ Status = XSdPs_Execute_Tuning(InstancePtr);
+ if (Status != XST_SUCCESS) {
+ Status = XST_FAILURE;
+ goto RETURN_PATH;
+ }
+ }
+ }
+
+ usleep(XSDPS_MMC_DELAY_FOR_SWITCH);
+
+ StatusReg = (u32)XSdPs_ReadReg8(InstancePtr->Config.BaseAddress,
+ XSDPS_HOST_CTRL1_OFFSET);
+ StatusReg |= XSDPS_HC_SPEED_MASK;
+ XSdPs_WriteReg8(InstancePtr->Config.BaseAddress,
+ XSDPS_HOST_CTRL1_OFFSET, (u8)StatusReg);
+
+ Status = XST_SUCCESS;
+
+ RETURN_PATH:
+ return Status;
+
+}
+
+/*****************************************************************************/
+/**
+*
+* API to change clock freq to given value.
+*
+*
+* @param InstancePtr is a pointer to the XSdPs instance.
+* @param SelFreq - Clock frequency in Hz.
+*
+* @return None
+*
+* @note This API will change clock frequency to the value less than
+* or equal to the given value using the permissible dividors.
+*
+******************************************************************************/
+s32 XSdPs_Change_ClkFreq(XSdPs *InstancePtr, u32 SelFreq)
+{
+ u16 ClockReg;
+ u16 DivCnt;
+ u16 Divisor = 0U;
+ u16 ExtDivisor;
+ s32 Status;
+ u16 ReadReg;
+
+ Xil_AssertNonvoid(InstancePtr != NULL);
+ Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+ /* Disable clock */
+ ClockReg = XSdPs_ReadReg16(InstancePtr->Config.BaseAddress,
+ XSDPS_CLK_CTRL_OFFSET);
+ ClockReg &= ~(XSDPS_CC_SD_CLK_EN_MASK | XSDPS_CC_INT_CLK_EN_MASK);
+ XSdPs_WriteReg16(InstancePtr->Config.BaseAddress,
+ XSDPS_CLK_CTRL_OFFSET, ClockReg);
+
+ if (InstancePtr->HC_Version == XSDPS_HC_SPEC_V3) {
+#if defined (ARMR5) || defined (__aarch64__) || defined (ARMA53_32) || defined (__MICROBLAZE__)
+ if ((InstancePtr->Mode != XSDPS_DEFAULT_SPEED_MODE) &&
+ (InstancePtr->Mode != XSDPS_UHS_SPEED_MODE_SDR12)) {
+ /* Program the Tap delays */
+ XSdPs_SetTapDelay(InstancePtr);
+ }
+#endif
+ /* Calculate divisor */
+ for (DivCnt = 0x1U; DivCnt <= XSDPS_CC_EXT_MAX_DIV_CNT;DivCnt++) {
+ if (((InstancePtr->Config.InputClockHz) / DivCnt) <= SelFreq) {
+ Divisor = DivCnt >> 1;
+ break;
+ }
+ }
+
+ if (DivCnt > XSDPS_CC_EXT_MAX_DIV_CNT) {
+ /* No valid divisor found for given frequency */
+ Status = XST_FAILURE;
+ goto RETURN_PATH;
+ }
+ } else {
+ /* Calculate divisor */
+ DivCnt = 0x1U;
+ while (DivCnt <= XSDPS_CC_MAX_DIV_CNT) {
+ if (((InstancePtr->Config.InputClockHz) / DivCnt) <= SelFreq) {
+ Divisor = DivCnt / 2U;
+ break;
+ }
+ DivCnt = DivCnt << 1U;
+ }
+
+ if (DivCnt > XSDPS_CC_MAX_DIV_CNT) {
+ /* No valid divisor found for given frequency */
+ Status = XST_FAILURE;
+ goto RETURN_PATH;
+ }
+ }
+
+ /* Set clock divisor */
+ if (InstancePtr->HC_Version == XSDPS_HC_SPEC_V3) {
+ ClockReg = XSdPs_ReadReg16(InstancePtr->Config.BaseAddress,
+ XSDPS_CLK_CTRL_OFFSET);
+ ClockReg &= ~(XSDPS_CC_SDCLK_FREQ_SEL_MASK |
+ XSDPS_CC_SDCLK_FREQ_SEL_EXT_MASK);
+
+ ExtDivisor = Divisor >> 8;
+ ExtDivisor <<= XSDPS_CC_EXT_DIV_SHIFT;
+ ExtDivisor &= XSDPS_CC_SDCLK_FREQ_SEL_EXT_MASK;
+
+ Divisor <<= XSDPS_CC_DIV_SHIFT;
+ Divisor &= XSDPS_CC_SDCLK_FREQ_SEL_MASK;
+ ClockReg |= Divisor | ExtDivisor | (u16)XSDPS_CC_INT_CLK_EN_MASK;
+ XSdPs_WriteReg16(InstancePtr->Config.BaseAddress, XSDPS_CLK_CTRL_OFFSET,
+ ClockReg);
+ } else {
+ ClockReg = XSdPs_ReadReg16(InstancePtr->Config.BaseAddress,
+ XSDPS_CLK_CTRL_OFFSET);
+ ClockReg &= (~XSDPS_CC_SDCLK_FREQ_SEL_MASK);
+
+ Divisor <<= XSDPS_CC_DIV_SHIFT;
+ Divisor &= XSDPS_CC_SDCLK_FREQ_SEL_MASK;
+ ClockReg |= Divisor | (u16)XSDPS_CC_INT_CLK_EN_MASK;
+ XSdPs_WriteReg16(InstancePtr->Config.BaseAddress, XSDPS_CLK_CTRL_OFFSET,
+ ClockReg);
+ }
+
+ /* Wait for internal clock to stabilize */
+ ReadReg = XSdPs_ReadReg16(InstancePtr->Config.BaseAddress,
+ XSDPS_CLK_CTRL_OFFSET);
+ while((ReadReg & XSDPS_CC_INT_CLK_STABLE_MASK) == 0U) {
+ ReadReg = XSdPs_ReadReg16(InstancePtr->Config.BaseAddress,
+ XSDPS_CLK_CTRL_OFFSET);;
+ }
+
+ /* Enable SD clock */
+ ClockReg = XSdPs_ReadReg16(InstancePtr->Config.BaseAddress,
+ XSDPS_CLK_CTRL_OFFSET);
+ XSdPs_WriteReg16(InstancePtr->Config.BaseAddress,
+ XSDPS_CLK_CTRL_OFFSET,
+ ClockReg | XSDPS_CC_SD_CLK_EN_MASK);
+
+ Status = XST_SUCCESS;
+
+RETURN_PATH:
+ return Status;
+
+}
+
+/*****************************************************************************/
+/**
+*
+* API to send pullup command to card before using DAT line 3(using 4-bit bus)
+*
+*
+* @param InstancePtr is a pointer to the XSdPs instance.
+*
+* @return
+* - XST_SUCCESS if successful.
+* - XST_FAILURE if fail.
+*
+* @note None.
+*
+******************************************************************************/
+s32 XSdPs_Pullup(XSdPs *InstancePtr)
+{
+ s32 Status;
+
+ Xil_AssertNonvoid(InstancePtr != NULL);
+ Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+ Status = XSdPs_CmdTransfer(InstancePtr, CMD55,
+ InstancePtr->RelCardAddr, 0U);
+ if (Status != XST_SUCCESS) {
+ Status = XST_FAILURE;
+ goto RETURN_PATH;
+ }
+
+ Status = XSdPs_CmdTransfer(InstancePtr, ACMD42, 0U, 0U);
+ if (Status != XST_SUCCESS) {
+ Status = XST_FAILURE;
+ goto RETURN_PATH;
+ }
+
+ Status = XST_SUCCESS;
+
+ RETURN_PATH:
+ return Status;
+
+}
+
+/*****************************************************************************/
+/**
+*
+* API to get EXT_CSD register of eMMC.
+*
+*
+* @param InstancePtr is a pointer to the XSdPs instance.
+* @param ReadBuff - buffer to store EXT_CSD
+*
+* @return
+* - XST_SUCCESS if successful.
+* - XST_FAILURE if fail.
+*
+* @note None.
+*
+******************************************************************************/
+s32 XSdPs_Get_Mmc_ExtCsd(XSdPs *InstancePtr, u8 *ReadBuff)
+{
+ s32 Status;
+ u32 StatusReg;
+ u32 Arg = 0U;
+ u16 BlkCnt;
+ u16 BlkSize;
+ s32 LoopCnt;
+
+ Xil_AssertNonvoid(InstancePtr != NULL);
+ Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+ for (LoopCnt = 0; LoopCnt < 512; LoopCnt++) {
+ ReadBuff[LoopCnt] = 0U;
+ }
+
+ BlkCnt = XSDPS_EXT_CSD_CMD_BLKCNT;
+ BlkSize = XSDPS_EXT_CSD_CMD_BLKSIZE;
+ BlkSize &= XSDPS_BLK_SIZE_MASK;
+ XSdPs_WriteReg16(InstancePtr->Config.BaseAddress,
+ XSDPS_BLK_SIZE_OFFSET, BlkSize);
+
+ XSdPs_SetupADMA2DescTbl(InstancePtr, BlkCnt, ReadBuff);
+
+ if (InstancePtr->Config.IsCacheCoherent == 0U) {
+ Xil_DCacheInvalidateRange((INTPTR)ReadBuff, 512U);
+ }
+
+ TransferMode = XSDPS_TM_DAT_DIR_SEL_MASK | XSDPS_TM_DMA_EN_MASK;
+
+ /* Send SEND_EXT_CSD command */
+ Status = XSdPs_CmdTransfer(InstancePtr, CMD8, Arg, 1U);
+ if (Status != XST_SUCCESS) {
+ Status = XST_FAILURE;
+ goto RETURN_PATH;
+ }
+
+ /*
+ * Check for transfer complete
+ * Polling for response for now
+ */
+ do {
+ StatusReg = XSdPs_ReadReg16(InstancePtr->Config.BaseAddress,
+ XSDPS_NORM_INTR_STS_OFFSET);
+ if ((StatusReg & XSDPS_INTR_ERR_MASK) != 0U) {
+ /* Write to clear error bits */
+ XSdPs_WriteReg16(InstancePtr->Config.BaseAddress,
+ XSDPS_ERR_INTR_STS_OFFSET,
+ XSDPS_ERROR_INTR_ALL_MASK);
+ Status = XST_FAILURE;
+ goto RETURN_PATH;
+ }
+ } while ((StatusReg & XSDPS_INTR_TC_MASK) == 0U);
+
+ /* Write to clear bit */
+ XSdPs_WriteReg16(InstancePtr->Config.BaseAddress,
+ XSDPS_NORM_INTR_STS_OFFSET, XSDPS_INTR_TC_MASK);
+
+ if (InstancePtr->Config.IsCacheCoherent == 0U) {
+ Xil_DCacheInvalidateRange((INTPTR)ReadBuff, 512U);
+ }
+
+ Status = XST_SUCCESS;
+
+ RETURN_PATH:
+ return Status;
+
+}
+
+/*****************************************************************************/
+/**
+*
+* API to write EXT_CSD register of eMMC.
+*
+*
+* @param InstancePtr is a pointer to the XSdPs instance.
+* @param Arg is the argument to be sent along with the command
+*
+* @return
+* - XST_SUCCESS if successful.
+* - XST_FAILURE if fail.
+*
+* @note None.
+*
+******************************************************************************/
+s32 XSdPs_Set_Mmc_ExtCsd(XSdPs *InstancePtr, u32 Arg)
+{
+ s32 Status;
+ u32 StatusReg;
+
+ Status = XSdPs_CmdTransfer(InstancePtr, CMD6, Arg, 0U);
+ if (Status != XST_SUCCESS) {
+ Status = XST_FAILURE;
+ goto RETURN_PATH;
+ }
+
+ /*
+ * Check for transfer complete
+ */
+ do {
+ StatusReg = XSdPs_ReadReg16(InstancePtr->Config.BaseAddress,
+ XSDPS_NORM_INTR_STS_OFFSET);
+ if ((StatusReg & XSDPS_INTR_ERR_MASK) != 0U) {
+ /*
+ * Write to clear error bits
+ */
+ XSdPs_WriteReg16(InstancePtr->Config.BaseAddress,
+ XSDPS_ERR_INTR_STS_OFFSET,
+ XSDPS_ERROR_INTR_ALL_MASK);
+ Status = XST_FAILURE;
+ goto RETURN_PATH;
+ }
+ } while ((StatusReg & XSDPS_INTR_TC_MASK) == 0U);
+
+ /* Write to clear bit */
+ XSdPs_WriteReg16(InstancePtr->Config.BaseAddress,
+ XSDPS_NORM_INTR_STS_OFFSET, XSDPS_INTR_TC_MASK);
+
+ Status = XST_SUCCESS;
+
+ RETURN_PATH:
+ return Status;
+
+}
+
+#if defined (ARMR5) || defined (__aarch64__) || defined (ARMA53_32) || defined (__MICROBLAZE__)
+/*****************************************************************************/
+/**
+*
+* API to Identify the supported UHS mode. This API will assign the
+* corresponding tap delay API to the Config_TapDelay pointer based on the
+* supported bus speed.
+*
+*
+* @param InstancePtr is a pointer to the XSdPs instance.
+* @param ReadBuff contains the response for CMD6
+*
+* @return None.
+*
+* @note None.
+*
+******************************************************************************/
+void XSdPs_Identify_UhsMode(XSdPs *InstancePtr, u8 *ReadBuff)
+{
+
+ Xil_AssertVoid(InstancePtr != NULL);
+
+ if (((ReadBuff[13] & UHS_SDR104_SUPPORT) != 0U) &&
+ (InstancePtr->Config.InputClockHz >= XSDPS_SD_INPUT_MAX_CLK)) {
+ InstancePtr->Mode = XSDPS_UHS_SPEED_MODE_SDR104;
+ if (InstancePtr->Config.BankNumber == 2U) {
+ InstancePtr->OTapDelay = SD_OTAPDLYSEL_HS200_B2;
+ } else {
+ InstancePtr->OTapDelay = SD_OTAPDLYSEL_HS200_B0;
+ }
+ } else if (((ReadBuff[13] & UHS_SDR50_SUPPORT) != 0U) &&
+ (InstancePtr->Config.InputClockHz >= XSDPS_SD_SDR50_MAX_CLK)) {
+ InstancePtr->Mode = XSDPS_UHS_SPEED_MODE_SDR50;
+ InstancePtr->OTapDelay = SD_OTAPDLYSEL_SD50;
+ } else if (((ReadBuff[13] & UHS_DDR50_SUPPORT) != 0U) &&
+ (InstancePtr->Config.InputClockHz >= XSDPS_SD_DDR50_MAX_CLK)) {
+ InstancePtr->Mode = XSDPS_UHS_SPEED_MODE_DDR50;
+ InstancePtr->OTapDelay = SD_OTAPDLYSEL_SD_DDR50;
+ InstancePtr->ITapDelay = SD_ITAPDLYSEL_SD_DDR50;
+ } else if (((ReadBuff[13] & UHS_SDR25_SUPPORT) != 0U) &&
+ (InstancePtr->Config.InputClockHz >= XSDPS_SD_SDR25_MAX_CLK)) {
+ InstancePtr->Mode = XSDPS_UHS_SPEED_MODE_SDR25;
+ InstancePtr->OTapDelay = SD_OTAPDLYSEL_SD_HSD;
+ InstancePtr->ITapDelay = SD_ITAPDLYSEL_HSD;
+ } else {
+ InstancePtr->Mode = XSDPS_UHS_SPEED_MODE_SDR12;
+ }
+}
+
+/*****************************************************************************/
+/**
+*
+* API to UHS-I mode initialization
+*
+*
+* @param InstancePtr is a pointer to the XSdPs instance.
+* @param Mode UHS-I mode
+*
+* @return
+* - XST_SUCCESS if successful.
+* - XST_FAILURE if fail.
+*
+* @note None.
+*
+******************************************************************************/
+s32 XSdPs_Uhs_ModeInit(XSdPs *InstancePtr, u8 Mode)
+{
+ s32 Status = XST_SUCCESS;
+ u16 StatusReg;
+ u16 CtrlReg;
+ u32 Arg = 0U;
+ u16 BlkCnt;
+ u16 BlkSize;
+ u8 ReadBuff[64] = {0U};
+
+ Xil_AssertNonvoid(InstancePtr != NULL);
+ Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+ /* Drive strength */
+
+ /* Bus speed mode selection */
+ BlkCnt = XSDPS_SWITCH_CMD_BLKCNT;
+ BlkSize = XSDPS_SWITCH_CMD_BLKSIZE;
+ BlkSize &= XSDPS_BLK_SIZE_MASK;
+ XSdPs_WriteReg16(InstancePtr->Config.BaseAddress, XSDPS_BLK_SIZE_OFFSET,
+ BlkSize);
+
+ XSdPs_SetupADMA2DescTbl(InstancePtr, BlkCnt, ReadBuff);
+
+ if (InstancePtr->Config.IsCacheCoherent == 0U) {
+ Xil_DCacheFlushRange((INTPTR)ReadBuff, 64);
+ }
+
+ TransferMode = XSDPS_TM_DAT_DIR_SEL_MASK | XSDPS_TM_DMA_EN_MASK;
+
+ switch (Mode) {
+ case 0U:
+ Arg = XSDPS_SWITCH_CMD_SDR12_SET;
+ InstancePtr->BusSpeed = XSDPS_SD_SDR12_MAX_CLK;
+ break;
+ case 1U:
+ Arg = XSDPS_SWITCH_CMD_SDR25_SET;
+ InstancePtr->BusSpeed = XSDPS_SD_SDR25_MAX_CLK;
+ break;
+ case 2U:
+ Arg = XSDPS_SWITCH_CMD_SDR50_SET;
+ InstancePtr->BusSpeed = XSDPS_SD_SDR50_MAX_CLK;
+ break;
+ case 3U:
+ Arg = XSDPS_SWITCH_CMD_SDR104_SET;
+ InstancePtr->BusSpeed = XSDPS_SD_SDR104_MAX_CLK;
+ break;
+ case 4U:
+ Arg = XSDPS_SWITCH_CMD_DDR50_SET;
+ InstancePtr->BusSpeed = XSDPS_SD_DDR50_MAX_CLK;
+ break;
+ default:
+ Status = XST_FAILURE;
+ break;
+ }
+
+ if (Status == XST_FAILURE) {
+ goto RETURN_PATH;
+ }
+
+ Status = XSdPs_CmdTransfer(InstancePtr, CMD6, Arg, 1U);
+ if (Status != XST_SUCCESS) {
+ Status = XST_FAILURE;
+ goto RETURN_PATH;
+ }
+
+ /*
+ * Check for transfer complete
+ * Polling for response for now
+ */
+ do {
+ StatusReg = XSdPs_ReadReg16(InstancePtr->Config.BaseAddress,
+ XSDPS_NORM_INTR_STS_OFFSET);
+ if ((StatusReg & XSDPS_INTR_ERR_MASK) != 0U) {
+ /* Write to clear error bits */
+ XSdPs_WriteReg16(InstancePtr->Config.BaseAddress,
+ XSDPS_ERR_INTR_STS_OFFSET, XSDPS_ERROR_INTR_ALL_MASK);
+ Status = XST_FAILURE;
+ goto RETURN_PATH;
+ }
+ } while ((StatusReg & XSDPS_INTR_TC_MASK) == 0U);
+
+ /* Write to clear bit */
+ XSdPs_WriteReg16(InstancePtr->Config.BaseAddress,
+ XSDPS_NORM_INTR_STS_OFFSET, XSDPS_INTR_TC_MASK);
+
+
+ /* Current limit */
+
+ /* Set UHS mode in controller */
+ CtrlReg = XSdPs_ReadReg16(InstancePtr->Config.BaseAddress,
+ XSDPS_HOST_CTRL2_OFFSET);
+ CtrlReg &= (u16)(~XSDPS_HC2_UHS_MODE_MASK);
+ CtrlReg |= Mode;
+ XSdPs_WriteReg16(InstancePtr->Config.BaseAddress,
+ XSDPS_HOST_CTRL2_OFFSET, CtrlReg);
+
+ /* Change the clock frequency */
+ Status = XSdPs_Change_ClkFreq(InstancePtr, InstancePtr->BusSpeed);
+ if (Status != XST_SUCCESS) {
+ Status = XST_FAILURE;
+ goto RETURN_PATH;
+ }
+
+ if((Mode == XSDPS_UHS_SPEED_MODE_SDR104) ||
+ (Mode == XSDPS_UHS_SPEED_MODE_SDR50)) {
+ /* Send tuning pattern */
+ Status = XSdPs_Execute_Tuning(InstancePtr);
+ if (Status != XST_SUCCESS) {
+ Status = XST_FAILURE;
+ goto RETURN_PATH;
+ }
+ }
+
+ Status = XST_SUCCESS;
+
+ RETURN_PATH:
+ return Status;
+}
+#endif
+
+static s32 XSdPs_Execute_Tuning(XSdPs *InstancePtr)
+{
+ s32 Status;
+ u16 BlkSize;
+ u16 CtrlReg;
+ u8 TuningCount;
+
+ Xil_AssertNonvoid(InstancePtr != NULL);
+ Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+ BlkSize = XSDPS_TUNING_CMD_BLKSIZE;
+ if(InstancePtr->BusWidth == XSDPS_8_BIT_WIDTH)
+ {
+ BlkSize = BlkSize*2U;
+ }
+ BlkSize &= XSDPS_BLK_SIZE_MASK;
+ XSdPs_WriteReg16(InstancePtr->Config.BaseAddress, XSDPS_BLK_SIZE_OFFSET,
+ BlkSize);
+
+ TransferMode = XSDPS_TM_DAT_DIR_SEL_MASK;
+
+ CtrlReg = XSdPs_ReadReg16(InstancePtr->Config.BaseAddress,
+ XSDPS_HOST_CTRL2_OFFSET);
+ CtrlReg |= XSDPS_HC2_EXEC_TNG_MASK;
+ XSdPs_WriteReg16(InstancePtr->Config.BaseAddress,
+ XSDPS_HOST_CTRL2_OFFSET, CtrlReg);
+
+ /*
+ * workaround which can work for 1.0/2.0 silicon for auto tuning.
+ * This can be revisited for 3.0 silicon if necessary.
+ */
+ /* Wait for ~60 clock cycles to reset the tap values */
+ (void)usleep(1U);
+
+#ifndef versal
+#if defined (ARMR5) || defined (__aarch64__) || defined (ARMA53_32) || defined (__MICROBLAZE__)
+ /* Issue DLL Reset to load new SDHC tuned tap values */
+ XSdPs_DllReset(InstancePtr);
+#endif
+#endif
+
+ for (TuningCount = 0U; TuningCount < MAX_TUNING_COUNT; TuningCount++) {
+
+ if (InstancePtr->CardType == XSDPS_CARD_SD) {
+ Status = XSdPs_CmdTransfer(InstancePtr, CMD19, 0U, 1U);
+ } else {
+ Status = XSdPs_CmdTransfer(InstancePtr, CMD21, 0U, 1U);
+ }
+
+ if (Status != XST_SUCCESS) {
+ Status = XST_FAILURE;
+ goto RETURN_PATH;
+ }
+
+ if ((XSdPs_ReadReg16(InstancePtr->Config.BaseAddress,
+ XSDPS_HOST_CTRL2_OFFSET) & XSDPS_HC2_EXEC_TNG_MASK) == 0U) {
+ break;
+ }
+
+#ifndef versal
+ if (TuningCount == 31U) {
+#if defined (ARMR5) || defined (__aarch64__) || defined (ARMA53_32) || defined (__MICROBLAZE__)
+ /* Issue DLL Reset to load new SDHC tuned tap values */
+ XSdPs_DllReset(InstancePtr);
+#endif
+ }
+#endif
+ }
+
+ if ((XSdPs_ReadReg16(InstancePtr->Config.BaseAddress,
+ XSDPS_HOST_CTRL2_OFFSET) & XSDPS_HC2_SAMP_CLK_SEL_MASK) == 0U) {
+ Status = XST_FAILURE;
+ goto RETURN_PATH;
+ }
+
+ /* Wait for ~12 clock cycles to synchronize the new tap values */
+ (void)usleep(1U);
+
+#ifndef versal
+#if defined (ARMR5) || defined (__aarch64__) || defined (ARMA53_32) || defined (__MICROBLAZE__)
+ /* Issue DLL Reset to load new SDHC tuned tap values */
+ XSdPs_DllReset(InstancePtr);
+#endif
+#endif
+
+ Status = XST_SUCCESS;
+
+ RETURN_PATH: return Status;
+
+}
+
+#if defined (ARMR5) || defined (__aarch64__) || defined (ARMA53_32) || defined (__MICROBLAZE__)
+
+#ifndef versal
+#if EL1_NONSECURE && defined (__aarch64__)
+static inline void XSdps_Smc(u32 RegOffset, u32 Mask, u32 Val)
+{
+ (void)Xil_Smc(MMIO_WRITE_SMC_FID, (u64)(XPS_SYS_CTRL_BASEADDR +
+ RegOffset) | ((u64)Mask << 32),
+ (u64)Val, 0, 0, 0, 0, 0);
+}
+#endif
+
+/*****************************************************************************/
+/**
+*
+* API to Set or Reset the DLL
+*
+*
+* @param InstancePtr is a pointer to the XSdPs instance.
+* @param EnRst is a flag indicating whether to Assert or De-assert Reset.
+*
+* @return None
+*
+* @note None.
+*
+******************************************************************************/
+static void XSdPs_DllRstCtrl(XSdPs *InstancePtr, u8 EnRst)
+{
+ u32 DeviceId = InstancePtr->Config.DeviceId;
+ u32 DllCtrl;
+
+#ifdef XPAR_PSU_SD_0_DEVICE_ID
+ if (DeviceId == 0U) {
+#if EL1_NONSECURE && defined (__aarch64__)
+ (void)DllCtrl;
+
+ XSdps_Smc(SD_DLL_CTRL, SD0_DLL_RST, (EnRst == 1U) ? SD0_DLL_RST : 0U);
+#else
+ DllCtrl = XSdPs_ReadReg(XPS_SYS_CTRL_BASEADDR, SD_DLL_CTRL);
+ if (EnRst == 1U) {
+ DllCtrl |= SD0_DLL_RST;
+ } else {
+ DllCtrl &= ~SD0_DLL_RST;
+ }
+ XSdPs_WriteReg(XPS_SYS_CTRL_BASEADDR, SD_DLL_CTRL, DllCtrl);
+#endif
+ } else {
+#endif /* XPAR_PSU_SD_0_DEVICE_ID */
+ (void) DeviceId;
+#if EL1_NONSECURE && defined (__aarch64__)
+ (void)DllCtrl;
+
+ XSdps_Smc(SD_DLL_CTRL, SD1_DLL_RST, (EnRst == 1U) ? SD1_DLL_RST : 0U);
+#else
+ DllCtrl = XSdPs_ReadReg(XPS_SYS_CTRL_BASEADDR, SD_DLL_CTRL);
+ if (EnRst == 1U) {
+ DllCtrl |= SD1_DLL_RST;
+ } else {
+ DllCtrl &= ~SD1_DLL_RST;
+ }
+ XSdPs_WriteReg(XPS_SYS_CTRL_BASEADDR, SD_DLL_CTRL, DllCtrl);
+#endif
+#ifdef XPAR_PSU_SD_0_DEVICE_ID
+ }
+#endif
+}
+
+/*****************************************************************************/
+/**
+*
+* API to reset the DLL
+*
+*
+* @param InstancePtr is a pointer to the XSdPs instance.
+*
+* @return None
+*
+* @note None.
+*
+******************************************************************************/
+static void XSdPs_DllReset(XSdPs *InstancePtr)
+{
+ u32 ClockReg;
+
+ /* Disable clock */
+ ClockReg = XSdPs_ReadReg16(InstancePtr->Config.BaseAddress,
+ XSDPS_CLK_CTRL_OFFSET);
+ ClockReg &= ~XSDPS_CC_SD_CLK_EN_MASK;
+ XSdPs_WriteReg16(InstancePtr->Config.BaseAddress,
+ XSDPS_CLK_CTRL_OFFSET, (u16)ClockReg);
+
+ /* Issue DLL Reset to load zero tap values */
+ XSdPs_DllRstCtrl(InstancePtr, 1U);
+
+ /* Wait for 2 micro seconds */
+ (void)usleep(2U);
+
+ XSdPs_DllRstCtrl(InstancePtr, 0U);
+
+ /* Wait for internal clock to stabilize */
+ ClockReg = XSdPs_ReadReg16(InstancePtr->Config.BaseAddress,
+ XSDPS_CLK_CTRL_OFFSET);
+ while((ClockReg & XSDPS_CC_INT_CLK_STABLE_MASK) == 0U) {
+ ClockReg = XSdPs_ReadReg16(InstancePtr->Config.BaseAddress,
+ XSDPS_CLK_CTRL_OFFSET);
+ }
+
+ /* Enable SD clock */
+ ClockReg = XSdPs_ReadReg16(InstancePtr->Config.BaseAddress,
+ XSDPS_CLK_CTRL_OFFSET);
+ XSdPs_WriteReg16(InstancePtr->Config.BaseAddress,
+ XSDPS_CLK_CTRL_OFFSET,
+ ClockReg | XSDPS_CC_SD_CLK_EN_MASK);
+}
+#endif
+
+/*****************************************************************************/
+/**
+*
+* Function to configure the Tap Delays.
+*
+*
+* @param InstancePtr is a pointer to the XSdPs instance.
+*
+* @return None
+*
+* @note None.
+*
+******************************************************************************/
+static void XSdPs_ConfigTapDelay(XSdPs *InstancePtr)
+{
+ u32 DeviceId = InstancePtr->Config.DeviceId ;
+ u32 TapDelay = 0U;
+ u32 ITapDelay = InstancePtr->ITapDelay;
+ u32 OTapDelay = InstancePtr->OTapDelay;
+
+#ifdef versal
+ (void) DeviceId;
+ if (ITapDelay) {
+ TapDelay = SD_ITAPCHGWIN;
+ XSdPs_WriteReg(InstancePtr->Config.BaseAddress, SD_ITAPDLY, TapDelay);
+ /* Program the ITAPDLY */
+ TapDelay |= SD_ITAPDLYENA;
+ XSdPs_WriteReg(InstancePtr->Config.BaseAddress, SD_ITAPDLY, TapDelay);
+ TapDelay |= ITapDelay;
+ XSdPs_WriteReg(InstancePtr->Config.BaseAddress, SD_ITAPDLY, TapDelay);
+ TapDelay &= ~SD_ITAPCHGWIN;
+ XSdPs_WriteReg(InstancePtr->Config.BaseAddress, SD_ITAPDLY, TapDelay);
+ }
+ if (OTapDelay) {
+ /* Program the OTAPDLY */
+ TapDelay = SD_OTAPDLYENA;
+ XSdPs_WriteReg(InstancePtr->Config.BaseAddress, SD_OTAPDLY, TapDelay);
+ TapDelay |= OTapDelay;
+ XSdPs_WriteReg(InstancePtr->Config.BaseAddress, SD_OTAPDLY, TapDelay);
+ }
+#else
+#ifdef XPAR_PSU_SD_0_DEVICE_ID
+ if (DeviceId == 0U) {
+#if EL1_NONSECURE && defined (__aarch64__)
+ (void)TapDelay;
+ if (ITapDelay) {
+ XSdps_Smc(SD_ITAPDLY, SD0_ITAPCHGWIN, SD0_ITAPCHGWIN);
+ XSdps_Smc(SD_ITAPDLY, SD0_ITAPDLYENA, SD0_ITAPDLYENA);
+ XSdps_Smc(SD_ITAPDLY, SD0_ITAPDLY_SEL_MASK, ITapDelay);
+ XSdps_Smc(SD_ITAPDLY, SD0_ITAPCHGWIN, 0U);
+ }
+ if (OTapDelay) {
+ XSdps_Smc(SD_OTAPDLY, SD0_OTAPDLY_SEL_MASK, OTapDelay);
+ }
+#else
+ if (ITapDelay) {
+ TapDelay = XSdPs_ReadReg(XPS_SYS_CTRL_BASEADDR, SD_ITAPDLY);
+ TapDelay |= SD0_ITAPCHGWIN;
+ XSdPs_WriteReg(XPS_SYS_CTRL_BASEADDR, SD_ITAPDLY, TapDelay);
+ /* Program the ITAPDLY */
+ TapDelay |= SD0_ITAPDLYENA;
+ XSdPs_WriteReg(XPS_SYS_CTRL_BASEADDR, SD_ITAPDLY, TapDelay);
+ TapDelay |= ITapDelay;
+ XSdPs_WriteReg(XPS_SYS_CTRL_BASEADDR, SD_ITAPDLY, TapDelay);
+ TapDelay &= ~SD0_ITAPCHGWIN;
+ XSdPs_WriteReg(XPS_SYS_CTRL_BASEADDR, SD_ITAPDLY, TapDelay);
+ }
+ if (OTapDelay) {
+ /* Program the OTAPDLY */
+ TapDelay = XSdPs_ReadReg(XPS_SYS_CTRL_BASEADDR, SD_OTAPDLY);
+ TapDelay &= ~SD0_OTAPDLY_SEL_MASK;
+ TapDelay |= OTapDelay;
+ XSdPs_WriteReg(XPS_SYS_CTRL_BASEADDR, SD_OTAPDLY, TapDelay);
+ }
+#endif
+ } else {
+#endif
+ (void) DeviceId;
+ ITapDelay = ITapDelay << 16U;
+ OTapDelay = OTapDelay << 16U;
+#if EL1_NONSECURE && defined (__aarch64__)
+ (void)TapDelay;
+ if (ITapDelay) {
+ XSdps_Smc(SD_ITAPDLY, SD1_ITAPCHGWIN, SD1_ITAPCHGWIN);
+ XSdps_Smc(SD_ITAPDLY, SD1_ITAPDLYENA, SD1_ITAPDLYENA);
+ XSdps_Smc(SD_ITAPDLY, SD1_ITAPDLY_SEL_MASK, ITapDelay);
+ XSdps_Smc(SD_ITAPDLY, SD1_ITAPCHGWIN, 0U);
+ }
+ if (OTapDelay) {
+ XSdps_Smc(SD_OTAPDLY, SD1_OTAPDLY_SEL_MASK, OTapDelay);
+ }
+#else
+ if (ITapDelay) {
+ TapDelay = XSdPs_ReadReg(XPS_SYS_CTRL_BASEADDR, SD_ITAPDLY);
+ TapDelay |= SD1_ITAPCHGWIN;
+ XSdPs_WriteReg(XPS_SYS_CTRL_BASEADDR, SD_ITAPDLY, TapDelay);
+ /* Program the ITAPDLY */
+ TapDelay |= SD1_ITAPDLYENA;
+ XSdPs_WriteReg(XPS_SYS_CTRL_BASEADDR, SD_ITAPDLY, TapDelay);
+ TapDelay |= ITapDelay;
+ XSdPs_WriteReg(XPS_SYS_CTRL_BASEADDR, SD_ITAPDLY, TapDelay);
+ TapDelay &= ~SD1_ITAPCHGWIN;
+ XSdPs_WriteReg(XPS_SYS_CTRL_BASEADDR, SD_ITAPDLY, TapDelay);
+ }
+ if (OTapDelay) {
+ /* Program the OTAPDLY */
+ TapDelay = XSdPs_ReadReg(XPS_SYS_CTRL_BASEADDR, SD_OTAPDLY);
+ TapDelay &= ~SD1_OTAPDLY_SEL_MASK;
+ TapDelay |= OTapDelay;
+ XSdPs_WriteReg(XPS_SYS_CTRL_BASEADDR, SD_OTAPDLY, TapDelay);
+ }
+#endif
+#ifdef XPAR_PSU_SD_0_DEVICE_ID
+ }
+#endif
+#endif /* versal */
+}
+
+/*****************************************************************************/
+/**
+*
+* API to set Tap Delay w.r.t speed modes
+*
+*
+* @param InstancePtr is a pointer to the XSdPs instance.
+*
+* @return None
+*
+* @note None.
+*
+******************************************************************************/
+void XSdPs_SetTapDelay(XSdPs *InstancePtr)
+{
+#ifndef versal
+ /* Issue DLL Reset */
+ XSdPs_DllRstCtrl(InstancePtr, 1U);
+#endif
+
+ /* Configure the Tap Delay Registers */
+ XSdPs_ConfigTapDelay(InstancePtr);
+
+#ifndef versal
+ /* Release the DLL out of reset */
+ XSdPs_DllRstCtrl(InstancePtr, 0U);
+#endif
+}
+#endif
+/** @} */
diff --git a/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/sdps_v3_8/src/xsdps_sinit.c b/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/sdps_v3_8/src/xsdps_sinit.c
new file mode 100644
index 0000000..5519b95
--- /dev/null
+++ b/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/sdps_v3_8/src/xsdps_sinit.c
@@ -0,0 +1,94 @@
+/******************************************************************************
+*
+* Copyright (C) 2013 - 2019 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+* THE SOFTWARE.
+*
+*
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xsdps_sinit.c
+* @addtogroup sdps_v3_8
+* @{
+*
+* The implementation of the XSdPs component's static initialization
+* functionality.
+*
+* <pre>
+* MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ----- --- -------- -----------------------------------------------
+* 1.00a hk/sg 10/17/13 Initial release
+* kvn 07/15/15 Modified the code according to MISRAC-2012.
+* 3.7 aru 03/12/19 Modified the code according to MISRAC-2012.
+*
+* </pre>
+*
+******************************************************************************/
+
+/***************************** Include Files *********************************/
+#include "xstatus.h"
+#include "xsdps.h"
+#include "xparameters.h"
+/************************** Constant Definitions *****************************/
+
+/**************************** Type Definitions *******************************/
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/************************** Function Prototypes ******************************/
+
+/************************** Variable Definitions *****************************/
+extern XSdPs_Config XSdPs_ConfigTable[XPAR_XSDPS_NUM_INSTANCES];
+
+/*****************************************************************************/
+/**
+*
+* Looks up the device configuration based on the unique device ID. A table
+* contains the configuration info for each device in the system.
+*
+* @param DeviceId contains the ID of the device to look up the
+* configuration for.
+*
+* @return
+*
+* A pointer to the configuration found or NULL if the specified device ID was
+* not found. See xsdps.h for the definition of XSdPs_Config.
+*
+* @note None.
+*
+******************************************************************************/
+XSdPs_Config *XSdPs_LookupConfig(u16 DeviceId)
+{
+ XSdPs_Config *CfgPtr = NULL;
+ u32 Index;
+
+ for (Index = 0U; Index < (u32)XPAR_XSDPS_NUM_INSTANCES; Index++) {
+ if (XSdPs_ConfigTable[Index].DeviceId == DeviceId) {
+ CfgPtr = &XSdPs_ConfigTable[Index];
+ break;
+ }
+ }
+ return (XSdPs_Config *)CfgPtr;
+}
+/** @} */
diff --git a/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v7_1/src/Makefile b/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v7_1/src/Makefile
new file mode 100644
index 0000000..0ebde4e
--- /dev/null
+++ b/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v7_1/src/Makefile
@@ -0,0 +1,81 @@
+###############################################################################
+#
+# Copyright (C) 2011 - 2015 Xilinx, Inc. All rights reserved.
+#
+# Permission is hereby granted, free of charge, to any person obtaining a copy
+# of this software and associated documentation files (the "Software"), to deal
+# in the Software without restriction, including without limitation the rights
+# to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+# copies of the Software, and to permit persons to whom the Software is
+# furnished to do so, subject to the following conditions:
+#
+# The above copyright notice and this permission notice shall be included in
+# all copies or substantial portions of the Software.
+#
+# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+# THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+# LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+# OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+# THE SOFTWARE.
+#
+#
+#
+###############################################################################
+
+include config.make
+
+CC=$(COMPILER)
+AR=$(ARCHIVER)
+CP=cp
+COMPILER_FLAGS=
+EXTRA_COMPILER_FLAGS=
+LIB=libxil.a
+
+CC_FLAGS = $(subst -pg, -DPROFILING, $(COMPILER_FLAGS))
+ECC_FLAGS = $(subst -pg, -DPROFILING, $(EXTRA_COMPILER_FLAGS))
+
+ifeq (($(notdir $(CC))) , arm-xilinx-eabi-gcc)
+ECC_FLAGS += -nostartfiles\
+ -march=armv7-a \
+ -mfloat-abi=soft \
+ -mfpu=neon
+endif
+
+ifeq (($(notdir $(CC))) , arm-none-eabi-gcc)
+ECC_FLAGS += -nostartfiles
+endif
+
+RELEASEDIR=../../../lib
+INCLUDEDIR=../../../include
+INCLUDES=-I./. -I${INCLUDEDIR}
+
+OUTS = *.o
+OBJECTS = $(addsuffix .o, $(basename $(wildcard *.c)))
+ASSEMBLY_OBJECTS = $(addsuffix .o, $(basename $(wildcard *.S)))
+INCLUDEFILES=*.h
+
+libs: $(LIBS)
+
+standalone_libs: $(LIBSOURCES)
+ echo "Compiling standalone"
+ $(CC) $(CC_FLAGS) $(ECC_FLAGS) $(INCLUDES) $^
+ $(AR) -r ${RELEASEDIR}/${LIB} ${OBJECTS} ${ASSEMBLY_OBJECTS}
+
+profile_libs:
+ $(MAKE) -C profile COMPILER_FLAGS="$(COMPILER_FLAGS)" EXTRA_COMPILER_FLAGS="$(EXTRA_COMPILER_FLAGS)" COMPILER="$(CC)" ARCHIVER="$(AR)" libs
+
+.PHONY: include
+include: standalone_includes profile_includes
+
+standalone_includes:
+ ${CP} ${INCLUDEFILES} ${INCLUDEDIR}
+
+profile_includes:
+ $(MAKE) -C profile COMPILER_FLAGS="$(COMPILER_FLAGS)" EXTRA_COMPILER_FLAGS="$(EXTRA_COMPILER_FLAGS)" COMPILER="$(CC)" ARCHIVER="$(AR)" include
+
+clean:
+ rm -rf ${OBJECTS}
+ rm -rf ${ASSEMBLY_OBJECTS}
+ $(MAKE) -C profile COMPILER_FLAGS="$(COMPILER_FLAGS)" EXTRA_COMPILER_FLAGS="$(EXTRA_COMPILER_FLAGS)" COMPILER="$(CC)" ARCHIVER="$(AR)" clean
diff --git a/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v7_1/src/_exit.c b/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v7_1/src/_exit.c
new file mode 100644
index 0000000..17ccc54
--- /dev/null
+++ b/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v7_1/src/_exit.c
@@ -0,0 +1,38 @@
+/******************************************************************************
+*
+* Copyright (C) 2009 - 2015 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+* THE SOFTWARE.
+*
+*
+*
+******************************************************************************/
+
+#include <unistd.h>
+#include "xil_types.h"
+
+/* _exit - Simple implementation. Does not return.
+*/
+__attribute__((weak)) void _exit (sint32 status)
+{
+ (void)status;
+ while (1) {
+ ;
+ }
+}
diff --git a/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v7_1/src/_open.c b/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v7_1/src/_open.c
new file mode 100644
index 0000000..eea0ad1
--- /dev/null
+++ b/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v7_1/src/_open.c
@@ -0,0 +1,48 @@
+/******************************************************************************
+*
+* Copyright (C) 2009 - 2015 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+* THE SOFTWARE.
+*
+*
+*
+******************************************************************************/
+#ifndef UNDEFINE_FILE_OPS
+#include <errno.h>
+#include "xil_types.h"
+
+#ifdef __cplusplus
+extern "C" {
+ __attribute__((weak)) s32 _open(const char8 *buf, s32 flags, s32 mode);
+}
+#endif
+
+/*
+ * _open -- open a file descriptor. We don't have a filesystem, so
+ * we return an error.
+ */
+__attribute__((weak)) s32 _open(const char8 *buf, s32 flags, s32 mode)
+{
+ (void)buf;
+ (void)flags;
+ (void)mode;
+ errno = EIO;
+ return (-1);
+}
+#endif
diff --git a/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v7_1/src/_sbrk.c b/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v7_1/src/_sbrk.c
new file mode 100644
index 0000000..a3cba0a
--- /dev/null
+++ b/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v7_1/src/_sbrk.c
@@ -0,0 +1,59 @@
+/******************************************************************************
+*
+* Copyright (C) 2009 - 2015 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+* THE SOFTWARE.
+*
+*
+*
+******************************************************************************/
+
+#include <sys/types.h>
+#include "xil_types.h"
+
+extern u8 _heap_start[];
+extern u8 _heap_end[];
+
+#ifdef __cplusplus
+extern "C" {
+ __attribute__((weak)) caddr_t _sbrk ( s32 incr );
+}
+#endif
+
+__attribute__((weak)) caddr_t _sbrk ( s32 incr )
+{
+ static u8 *heap = NULL;
+ u8 *prev_heap;
+ static u8 *HeapEndPtr = (u8 *)&_heap_end;
+ caddr_t Status;
+
+ if (heap == NULL) {
+ heap = (u8 *)&_heap_start;
+ }
+ prev_heap = heap;
+
+ if (((heap + incr) <= HeapEndPtr) && (prev_heap != NULL)) {
+ heap += incr;
+ Status = (caddr_t) ((void *)prev_heap);
+ } else {
+ Status = (caddr_t) -1;
+ }
+
+ return Status;
+}
diff --git a/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v7_1/src/abort.c b/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v7_1/src/abort.c
new file mode 100644
index 0000000..997747e
--- /dev/null
+++ b/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v7_1/src/abort.c
@@ -0,0 +1,36 @@
+/******************************************************************************
+*
+* Copyright (C) 2009 - 2015 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+* THE SOFTWARE.
+*
+*
+*
+******************************************************************************/
+
+#include <stdlib.h>
+#include <unistd.h>
+
+/*
+ * abort -- go out via exit...
+ */
+__attribute__((weak)) void abort(void)
+{
+ _exit(1);
+}
diff --git a/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v7_1/src/asm_vectors.S b/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v7_1/src/asm_vectors.S
new file mode 100644
index 0000000..7861714
--- /dev/null
+++ b/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v7_1/src/asm_vectors.S
@@ -0,0 +1,197 @@
+/******************************************************************************
+*
+* Copyright (C) 2009 - 2018 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+* THE SOFTWARE.
+*
+*
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+* @file asm_vectors.s
+*
+* This file contains the initial vector table for the Cortex A9 processor
+*
+* <pre>
+* MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ----- ------- -------- ---------------------------------------------------
+* 1.00a ecm/sdm 10/20/09 Initial version
+* 3.05a sdm 02/02/12 Save lr when profiling is enabled
+* 3.10a srt 04/18/13 Implemented ARM Erratas. Please refer to file
+* 'xil_errata.h' for errata description
+* 4.00a pkp 22/01/14 Modified return addresses for interrupt
+* handlers (DataAbortHandler and SVCHandler)
+* to fix CR#767251
+* 5.1 pkp 05/13/15 Saved the addresses of instruction causing data
+* abort and prefetch abort into DataAbortAddr and
+* PrefetchAbortAddr for further use to fix CR#854523
+* 5.4 pkp 12/03/15 Added handler for undefined exception
+* 6.8 mus 04/27/18 Removed __ARM_NEON__ flag definition. Now,
+* saving/restoring of of HW floating point register
+* would be done through newly introduced flag
+* FPU_HARD_FLOAT_ABI_ENABLED. This new flag will be
+* configured based on the -mfpu-abi option in extra
+* compiler flags.
+* </pre>
+*
+* @note
+*
+* None.
+*
+******************************************************************************/
+#include "xil_errata.h"
+#include "bspconfig.h"
+
+.org 0
+.text
+
+.globl _vector_table
+
+.section .vectors
+_vector_table:
+ B _boot
+ B Undefined
+ B SVCHandler
+ B PrefetchAbortHandler
+ B DataAbortHandler
+ NOP /* Placeholder for address exception vector*/
+ B IRQHandler
+ B FIQHandler
+
+
+IRQHandler: /* IRQ vector handler */
+
+ stmdb sp!,{r0-r3,r12,lr} /* state save from compiled code*/
+#if FPU_HARD_FLOAT_ABI_ENABLED
+ vpush {d0-d7}
+ vpush {d16-d31}
+ vmrs r1, FPSCR
+ push {r1}
+ vmrs r1, FPEXC
+ push {r1}
+#endif
+
+#ifdef PROFILING
+ ldr r2, =prof_pc
+ subs r3, lr, #0
+ str r3, [r2]
+#endif
+
+ bl IRQInterrupt /* IRQ vector */
+
+#if FPU_HARD_FLOAT_ABI_ENABLED
+ pop {r1}
+ vmsr FPEXC, r1
+ pop {r1}
+ vmsr FPSCR, r1
+ vpop {d16-d31}
+ vpop {d0-d7}
+#endif
+ ldmia sp!,{r0-r3,r12,lr} /* state restore from compiled code */
+
+
+ subs pc, lr, #4 /* adjust return */
+
+
+FIQHandler: /* FIQ vector handler */
+ stmdb sp!,{r0-r3,r12,lr} /* state save from compiled code */
+#if FPU_HARD_FLOAT_ABI_ENABLED
+ vpush {d0-d7}
+ vpush {d16-d31}
+ vmrs r1, FPSCR
+ push {r1}
+ vmrs r1, FPEXC
+ push {r1}
+#endif
+
+FIQLoop:
+ bl FIQInterrupt /* FIQ vector */
+
+#if FPU_HARD_FLOAT_ABI_ENABLED
+ pop {r1}
+ vmsr FPEXC, r1
+ pop {r1}
+ vmsr FPSCR, r1
+ vpop {d16-d31}
+ vpop {d0-d7}
+#endif
+ ldmia sp!,{r0-r3,r12,lr} /* state restore from compiled code */
+ subs pc, lr, #4 /* adjust return */
+
+
+Undefined: /* Undefined handler */
+ stmdb sp!,{r0-r3,r12,lr} /* state save from compiled code */
+ ldr r0, =UndefinedExceptionAddr
+ sub r1, lr, #4
+ str r1, [r0] /* Store address of instruction causing undefined exception */
+
+ bl UndefinedException /* UndefinedException: call C function here */
+ ldmia sp!,{r0-r3,r12,lr} /* state restore from compiled code */
+ movs pc, lr
+
+SVCHandler: /* SWI handler */
+ stmdb sp!,{r0-r3,r12,lr} /* state save from compiled code */
+
+ tst r0, #0x20 /* check the T bit */
+ ldrneh r0, [lr,#-2] /* Thumb mode */
+ bicne r0, r0, #0xff00 /* Thumb mode */
+ ldreq r0, [lr,#-4] /* ARM mode */
+ biceq r0, r0, #0xff000000 /* ARM mode */
+
+ bl SWInterrupt /* SWInterrupt: call C function here */
+
+ ldmia sp!,{r0-r3,r12,lr} /* state restore from compiled code */
+
+ movs pc, lr /*return to the next instruction after the SWI instruction */
+
+
+DataAbortHandler: /* Data Abort handler */
+#ifdef CONFIG_ARM_ERRATA_775420
+ dsb
+#endif
+ stmdb sp!,{r0-r3,r12,lr} /* state save from compiled code */
+ ldr r0, =DataAbortAddr
+ sub r1, lr, #8
+ str r1, [r0] /* Stores instruction causing data abort */
+
+ bl DataAbortInterrupt /*DataAbortInterrupt :call C function here */
+
+ ldmia sp!,{r0-r3,r12,lr} /* state restore from compiled code */
+
+ subs pc, lr, #8 /* points to the instruction that caused the Data Abort exception */
+
+PrefetchAbortHandler: /* Prefetch Abort handler */
+#ifdef CONFIG_ARM_ERRATA_775420
+ dsb
+#endif
+ stmdb sp!,{r0-r3,r12,lr} /* state save from compiled code */
+ ldr r0, =PrefetchAbortAddr
+ sub r1, lr, #4
+ str r1, [r0] /* Stores instruction causing prefetch abort */
+
+ bl PrefetchAbortInterrupt /* PrefetchAbortInterrupt: call C function here */
+
+ ldmia sp!,{r0-r3,r12,lr} /* state restore from compiled code */
+
+ subs pc, lr, #4 /* points to the instruction that caused the Prefetch Abort exception */
+
+.end
diff --git a/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v7_1/src/boot.S b/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v7_1/src/boot.S
new file mode 100644
index 0000000..af693c0
--- /dev/null
+++ b/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v7_1/src/boot.S
@@ -0,0 +1,490 @@
+/******************************************************************************
+*
+* Copyright (C) 2010 - 2016 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+* THE SOFTWARE.
+*
+*
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+* @file boot.S
+*
+* @addtogroup a9_boot_code Cortex A9 Processor Boot Code
+* @{
+* <h2> boot.S </h2>
+* The boot code performs minimum configuration which is required for an
+* application to run starting from processor's reset state. Below is a
+* sequence illustrating what all configuration is performed before control
+* reaches to main function.
+*
+* 1. Program vector table base for exception handling
+* 2. Invalidate instruction cache, data cache and TLBs
+* 3. Program stack pointer for various modes (IRQ, FIQ, supervisor, undefine,
+* abort, system)
+* 4. Configure MMU with short descriptor translation table format and program
+* base address of translation table
+* 5. Enable data cache, instruction cache and MMU
+* 6. Enable Floating point unit
+* 7. Transfer control to _start which clears BSS sections, initializes
+* global timer and runs global constructor before jumping to main
+* application
+*
+* <pre>
+* MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ----- ------- -------- ---------------------------------------------------
+* 1.00a ecm/sdm 10/20/09 Initial version
+* 3.06a sgd 05/15/12 Updated L2CC Auxiliary and Tag RAM Latency control
+* register settings.
+* 3.06a asa 06/17/12 Modified the TTBR settings and L2 Cache auxiliary
+* register settings.
+* 3.07a asa 07/16/12 Modified the L2 Cache controller settings to improve
+* performance. Changed the property of the ".boot"
+* section.
+* 3.07a sgd 08/21/12 Modified the L2 Cache controller and cp15 Aux Control
+* Register settings
+* 3.09a sgd 02/06/13 Updated SLCR l2c Ram Control register to a
+* value of 0x00020202. Fix for CR 697094 (SI#687034).
+* 3.10a srt 04/18/13 Implemented ARM Erratas. Please refer to file
+* 'xil_errata.h' for errata description
+* 4.2 pkp 06/19/14 Enabled asynchronous abort exception
+* 5.0 pkp 16/15/14 Modified initialization code to enable scu after
+* MMU is enabled
+* 5.1 pkp 05/13/15 Changed the initialization order so to first invalidate
+* caches and TLB, enable MMU and caches, then enable SMP
+* bit in ACTLR. L2Cache invalidation and enabling of L2Cache
+* is done later.
+* 5.4 asa 12/6/15 Added code to initialize SPSR for all relevant modes.
+* 6.0 mus 08/04/16 Added code to detect zynq-7000 base silicon configuration and
+* attempt to enable dual core behavior on single cpu zynq-7000s
+* devices is prevented from corrupting system behavior.
+* 6.0 mus 08/24/16 Check CPU core before putting cpu1 to reset for single core
+* zynq-7000s devices
+*
+* </pre>
+*
+* @note
+*
+* None.
+*
+******************************************************************************/
+
+#include "xparameters.h"
+#include "xil_errata.h"
+
+.globl MMUTable
+.global _prestart
+.global _boot
+.global __stack
+.global __irq_stack
+.global __supervisor_stack
+.global __abort_stack
+.global __fiq_stack
+.global __undef_stack
+.global _vector_table
+
+.set PSS_L2CC_BASE_ADDR, 0xF8F02000
+.set PSS_SLCR_BASE_ADDR, 0xF8000000
+
+.set RESERVED, 0x0fffff00
+.set TblBase , MMUTable
+.set LRemap, 0xFE00000F /* set the base address of the peripheral block as not shared */
+.set L2CCWay, (PSS_L2CC_BASE_ADDR + 0x077C) /*(PSS_L2CC_BASE_ADDR + PSS_L2CC_CACHE_INVLD_WAY_OFFSET)*/
+.set L2CCSync, (PSS_L2CC_BASE_ADDR + 0x0730) /*(PSS_L2CC_BASE_ADDR + PSS_L2CC_CACHE_SYNC_OFFSET)*/
+.set L2CCCrtl, (PSS_L2CC_BASE_ADDR + 0x0100) /*(PSS_L2CC_BASE_ADDR + PSS_L2CC_CNTRL_OFFSET)*/
+.set L2CCAuxCrtl, (PSS_L2CC_BASE_ADDR + 0x0104) /*(PSS_L2CC_BASE_ADDR + XPSS_L2CC_AUX_CNTRL_OFFSET)*/
+.set L2CCTAGLatReg, (PSS_L2CC_BASE_ADDR + 0x0108) /*(PSS_L2CC_BASE_ADDR + XPSS_L2CC_TAG_RAM_CNTRL_OFFSET)*/
+.set L2CCDataLatReg, (PSS_L2CC_BASE_ADDR + 0x010C) /*(PSS_L2CC_BASE_ADDR + XPSS_L2CC_DATA_RAM_CNTRL_OFFSET)*/
+.set L2CCIntClear, (PSS_L2CC_BASE_ADDR + 0x0220) /*(PSS_L2CC_BASE_ADDR + XPSS_L2CC_IAR_OFFSET)*/
+.set L2CCIntRaw, (PSS_L2CC_BASE_ADDR + 0x021C) /*(PSS_L2CC_BASE_ADDR + XPSS_L2CC_ISR_OFFSET)*/
+
+.set SLCRlockReg, (PSS_SLCR_BASE_ADDR + 0x04) /*(PSS_SLCR_BASE_ADDR + XPSS_SLCR_LOCK_OFFSET)*/
+.set SLCRUnlockReg, (PSS_SLCR_BASE_ADDR + 0x08) /*(PSS_SLCR_BASE_ADDR + XPSS_SLCR_UNLOCK_OFFSET)*/
+.set SLCRL2cRamReg, (PSS_SLCR_BASE_ADDR + 0xA1C) /*(PSS_SLCR_BASE_ADDR + XPSS_SLCR_L2C_RAM_OFFSET)*/
+.set SLCRCPURSTReg, (0xF8000000 + 0x244) /*(XPS_SYS_CTRL_BASEADDR + A9_CPU_RST_CTRL_OFFSET)*/
+.set EFUSEStaus, (0xF800D000 + 0x10) /*(XPS_EFUSE_BASEADDR + EFUSE_STATUS_OFFSET)*/
+
+/* workaround for simulation not working when L1 D and I caches,MMU and L2 cache enabled - DT568997 */
+.if SIM_MODE == 1
+.set CRValMmuCac, 0b00000000000000 /* Disable IDC, and MMU */
+.else
+.set CRValMmuCac, 0b01000000000101 /* Enable IDC, and MMU */
+.endif
+
+.set CRValHiVectorAddr, 0b10000000000000 /* Set the Vector address to high, 0xFFFF0000 */
+
+.set L2CCAuxControl, 0x72360000 /* Enable all prefetching, Cache replacement policy, Parity enable,
+ Event monitor bus enable and Way Size (64 KB) */
+.set L2CCControl, 0x01 /* Enable L2CC */
+.set L2CCTAGLatency, 0x0111 /* latency for TAG RAM */
+.set L2CCDataLatency, 0x0121 /* latency for DATA RAM */
+
+.set SLCRlockKey, 0x767B /* SLCR lock key */
+.set SLCRUnlockKey, 0xDF0D /* SLCR unlock key */
+.set SLCRL2cRamConfig, 0x00020202 /* SLCR L2C ram configuration */
+
+/* Stack Pointer locations for boot code */
+.set Undef_stack, __undef_stack
+.set FIQ_stack, __fiq_stack
+.set Abort_stack, __abort_stack
+.set SPV_stack, __supervisor_stack
+.set IRQ_stack, __irq_stack
+.set SYS_stack, __stack
+
+.set vector_base, _vector_table
+
+.set FPEXC_EN, 0x40000000 /* FPU enable bit, (1 << 30) */
+
+.section .boot,"ax"
+
+
+/* this initializes the various processor modes */
+
+_prestart:
+_boot:
+
+#if XPAR_CPU_ID==0
+ /* only allow cpu0 through */
+ mrc p15,0,r1,c0,c0,5
+ and r1, r1, #0xf
+ cmp r1, #0
+ beq CheckEFUSE
+ EndlessLoop0:
+ wfe
+ b EndlessLoop0
+
+CheckEFUSE:
+ ldr r0,=EFUSEStaus
+ ldr r1,[r0] /* Read eFuse setting */
+ ands r1,r1,#0x80 /* Check whether device is having single core */
+ beq OKToRun
+
+ /* single core device, reset cpu1 */
+ ldr r0,=SLCRUnlockReg /* Load SLCR base address base + unlock register */
+ ldr r1,=SLCRUnlockKey /* set unlock key */
+ str r1, [r0] /* Unlock SLCR */
+
+ ldr r0,=SLCRCPURSTReg
+ ldr r1,[r0] /* Read CPU Software Reset Control register */
+ orr r1,r1,#0x22
+ str r1,[r0] /* Reset CPU1 */
+
+ ldr r0,=SLCRlockReg /* Load SLCR base address base + lock register */
+ ldr r1,=SLCRlockKey /* set lock key */
+ str r1, [r0] /* lock SLCR */
+
+#elif XPAR_CPU_ID==1
+ /* only allow cpu1 through */
+ mrc p15,0,r1,c0,c0,5
+ and r1, r1, #0xf
+ cmp r1, #1
+ beq CheckEFUSE1
+ b EndlessLoop1
+
+CheckEFUSE1:
+ ldr r0,=EFUSEStaus
+ ldr r1,[r0] /* Read eFuse setting */
+ ands r1,r1,#0x80 /* Check whether device is having single core */
+ beq OKToRun
+ EndlessLoop1:
+ wfe
+ b EndlessLoop1
+#endif
+
+OKToRun:
+ mrc p15, 0, r0, c0, c0, 0 /* Get the revision */
+ and r5, r0, #0x00f00000
+ and r6, r0, #0x0000000f
+ orr r6, r6, r5, lsr #20-4
+
+#ifdef CONFIG_ARM_ERRATA_742230
+ cmp r6, #0x22 /* only present up to r2p2 */
+ mrcle p15, 0, r10, c15, c0, 1 /* read diagnostic register */
+ orrle r10, r10, #1 << 4 /* set bit #4 */
+ mcrle p15, 0, r10, c15, c0, 1 /* write diagnostic register */
+#endif
+
+#ifdef CONFIG_ARM_ERRATA_743622
+ teq r5, #0x00200000 /* only present in r2p* */
+ mrceq p15, 0, r10, c15, c0, 1 /* read diagnostic register */
+ orreq r10, r10, #1 << 6 /* set bit #6 */
+ mcreq p15, 0, r10, c15, c0, 1 /* write diagnostic register */
+#endif
+
+ /* set VBAR to the _vector_table address in linker script */
+ ldr r0, =vector_base
+ mcr p15, 0, r0, c12, c0, 0
+
+ /*invalidate scu*/
+ ldr r7, =0xf8f0000c
+ ldr r6, =0xffff
+ str r6, [r7]
+
+ /* Invalidate caches and TLBs */
+ mov r0,#0 /* r0 = 0 */
+ mcr p15, 0, r0, c8, c7, 0 /* invalidate TLBs */
+ mcr p15, 0, r0, c7, c5, 0 /* invalidate icache */
+ mcr p15, 0, r0, c7, c5, 6 /* Invalidate branch predictor array */
+ bl invalidate_dcache /* invalidate dcache */
+
+ /* Disable MMU, if enabled */
+ mrc p15, 0, r0, c1, c0, 0 /* read CP15 register 1 */
+ bic r0, r0, #0x1 /* clear bit 0 */
+ mcr p15, 0, r0, c1, c0, 0 /* write value back */
+
+#ifdef SHAREABLE_DDR
+ /* Mark the entire DDR memory as shareable */
+ ldr r3, =0x3ff /* 1024 entries to cover 1G DDR */
+ ldr r0, =TblBase /* MMU Table address in memory */
+ ldr r2, =0x15de6 /* S=b1 TEX=b101 AP=b11, Domain=b1111, C=b0, B=b1 */
+shareable_loop:
+ str r2, [r0] /* write the entry to MMU table */
+ add r0, r0, #0x4 /* next entry in the table */
+ add r2, r2, #0x100000 /* next section */
+ subs r3, r3, #1
+ bge shareable_loop /* loop till 1G is covered */
+#endif
+
+ mrs r0, cpsr /* get the current PSR */
+ mvn r1, #0x1f /* set up the irq stack pointer */
+ and r2, r1, r0
+ orr r2, r2, #0x12 /* IRQ mode */
+ msr cpsr, r2
+ ldr r13,=IRQ_stack /* IRQ stack pointer */
+ bic r2, r2, #(0x1 << 9) /* Set EE bit to little-endian */
+ msr spsr_fsxc,r2
+
+ mrs r0, cpsr /* get the current PSR */
+ mvn r1, #0x1f /* set up the supervisor stack pointer */
+ and r2, r1, r0
+ orr r2, r2, #0x13 /* supervisor mode */
+ msr cpsr, r2
+ ldr r13,=SPV_stack /* Supervisor stack pointer */
+ bic r2, r2, #(0x1 << 9) /* Set EE bit to little-endian */
+ msr spsr_fsxc,r2
+
+ mrs r0, cpsr /* get the current PSR */
+ mvn r1, #0x1f /* set up the Abort stack pointer */
+ and r2, r1, r0
+ orr r2, r2, #0x17 /* Abort mode */
+ msr cpsr, r2
+ ldr r13,=Abort_stack /* Abort stack pointer */
+ bic r2, r2, #(0x1 << 9) /* Set EE bit to little-endian */
+ msr spsr_fsxc,r2
+
+ mrs r0, cpsr /* get the current PSR */
+ mvn r1, #0x1f /* set up the FIQ stack pointer */
+ and r2, r1, r0
+ orr r2, r2, #0x11 /* FIQ mode */
+ msr cpsr, r2
+ ldr r13,=FIQ_stack /* FIQ stack pointer */
+ bic r2, r2, #(0x1 << 9) /* Set EE bit to little-endian */
+ msr spsr_fsxc,r2
+
+ mrs r0, cpsr /* get the current PSR */
+ mvn r1, #0x1f /* set up the Undefine stack pointer */
+ and r2, r1, r0
+ orr r2, r2, #0x1b /* Undefine mode */
+ msr cpsr, r2
+ ldr r13,=Undef_stack /* Undefine stack pointer */
+ bic r2, r2, #(0x1 << 9) /* Set EE bit to little-endian */
+ msr spsr_fsxc,r2
+
+ mrs r0, cpsr /* get the current PSR */
+ mvn r1, #0x1f /* set up the system stack pointer */
+ and r2, r1, r0
+ orr r2, r2, #0x1F /* SYS mode */
+ msr cpsr, r2
+ ldr r13,=SYS_stack /* SYS stack pointer */
+
+ /*set scu enable bit in scu*/
+ ldr r7, =0xf8f00000
+ ldr r0, [r7]
+ orr r0, r0, #0x1
+ str r0, [r7]
+
+ /* enable MMU and cache */
+
+ ldr r0,=TblBase /* Load MMU translation table base */
+ orr r0, r0, #0x5B /* Outer-cacheable, WB */
+ mcr 15, 0, r0, c2, c0, 0 /* TTB0 */
+
+ mvn r0,#0 /* Load MMU domains -- all ones=manager */
+ mcr p15,0,r0,c3,c0,0
+
+ /* Enable mmu, icahce and dcache */
+ ldr r0,=CRValMmuCac
+ mcr p15,0,r0,c1,c0,0 /* Enable cache and MMU */
+ dsb /* dsb allow the MMU to start up */
+ isb /* isb flush prefetch buffer */
+
+ /* Write to ACTLR */
+ mrc p15, 0, r0, c1, c0, 1 /* Read ACTLR*/
+ orr r0, r0, #(0x01 << 6) /* set SMP bit */
+ orr r0, r0, #(0x01 ) /* Cache/TLB maintenance broadcast */
+ mcr p15, 0, r0, c1, c0, 1 /* Write ACTLR*/
+
+/* Invalidate L2 Cache and enable L2 Cache*/
+/* For AMP, assume running on CPU1. Don't initialize L2 Cache (up to Linux) */
+#if USE_AMP!=1
+ ldr r0,=L2CCCrtl /* Load L2CC base address base + control register */
+ mov r1, #0 /* force the disable bit */
+ str r1, [r0] /* disable the L2 Caches */
+
+ ldr r0,=L2CCAuxCrtl /* Load L2CC base address base + Aux control register */
+ ldr r1,[r0] /* read the register */
+ ldr r2,=L2CCAuxControl /* set the default bits */
+ orr r1,r1,r2
+ str r1, [r0] /* store the Aux Control Register */
+
+ ldr r0,=L2CCTAGLatReg /* Load L2CC base address base + TAG Latency address */
+ ldr r1,=L2CCTAGLatency /* set the latencies for the TAG*/
+ str r1, [r0] /* store the TAG Latency register Register */
+
+ ldr r0,=L2CCDataLatReg /* Load L2CC base address base + Data Latency address */
+ ldr r1,=L2CCDataLatency /* set the latencies for the Data*/
+ str r1, [r0] /* store the Data Latency register Register */
+
+ ldr r0,=L2CCWay /* Load L2CC base address base + way register*/
+ ldr r2, =0xFFFF
+ str r2, [r0] /* force invalidate */
+
+ ldr r0,=L2CCSync /* need to poll 0x730, PSS_L2CC_CACHE_SYNC_OFFSET */
+ /* Load L2CC base address base + sync register*/
+ /* poll for completion */
+Sync: ldr r1, [r0]
+ cmp r1, #0
+ bne Sync
+
+ ldr r0,=L2CCIntRaw /* clear pending interrupts */
+ ldr r1,[r0]
+ ldr r0,=L2CCIntClear
+ str r1,[r0]
+
+ ldr r0,=SLCRUnlockReg /* Load SLCR base address base + unlock register */
+ ldr r1,=SLCRUnlockKey /* set unlock key */
+ str r1, [r0] /* Unlock SLCR */
+
+ ldr r0,=SLCRL2cRamReg /* Load SLCR base address base + l2c Ram Control register */
+ ldr r1,=SLCRL2cRamConfig /* set the configuration value */
+ str r1, [r0] /* store the L2c Ram Control Register */
+
+ ldr r0,=SLCRlockReg /* Load SLCR base address base + lock register */
+ ldr r1,=SLCRlockKey /* set lock key */
+ str r1, [r0] /* lock SLCR */
+
+ ldr r0,=L2CCCrtl /* Load L2CC base address base + control register */
+ ldr r1,[r0] /* read the register */
+ mov r2, #L2CCControl /* set the enable bit */
+ orr r1,r1,r2
+ str r1, [r0] /* enable the L2 Caches */
+#endif
+
+ mov r0, r0
+ mrc p15, 0, r1, c1, c0, 2 /* read cp access control register (CACR) into r1 */
+ orr r1, r1, #(0xf << 20) /* enable full access for p10 & p11 */
+ mcr p15, 0, r1, c1, c0, 2 /* write back into CACR */
+
+ /* enable vfp */
+ fmrx r1, FPEXC /* read the exception register */
+ orr r1,r1, #FPEXC_EN /* set VFP enable bit, leave the others in orig state */
+ fmxr FPEXC, r1 /* write back the exception register */
+
+ mrc p15,0,r0,c1,c0,0 /* flow prediction enable */
+ orr r0, r0, #(0x01 << 11) /* #0x8000 */
+ mcr p15,0,r0,c1,c0,0
+
+ mrc p15,0,r0,c1,c0,1 /* read Auxiliary Control Register */
+ orr r0, r0, #(0x1 << 2) /* enable Dside prefetch */
+ orr r0, r0, #(0x1 << 1) /* enable L2 Prefetch hint */
+ mcr p15,0,r0,c1,c0,1 /* write Auxiliary Control Register */
+
+ mrs r0, cpsr /* get the current PSR */
+ bic r0, r0, #0x100 /* enable asynchronous abort exception */
+ msr cpsr_xsf, r0
+
+
+ b _start /* jump to C startup code */
+ and r0, r0, r0 /* no op */
+
+.Ldone: b .Ldone /* Paranoia: we should never get here */
+
+
+/*
+ *************************************************************************
+ *
+ * invalidate_dcache - invalidate the entire d-cache by set/way
+ *
+ * Note: for Cortex-A9, there is no cp instruction for invalidating
+ * the whole D-cache. Need to invalidate each line.
+ *
+ *************************************************************************
+ */
+invalidate_dcache:
+ mrc p15, 1, r0, c0, c0, 1 /* read CLIDR */
+ ands r3, r0, #0x7000000
+ mov r3, r3, lsr #23 /* cache level value (naturally aligned) */
+ beq finished
+ mov r10, #0 /* start with level 0 */
+loop1:
+ add r2, r10, r10, lsr #1 /* work out 3xcachelevel */
+ mov r1, r0, lsr r2 /* bottom 3 bits are the Cache type for this level */
+ and r1, r1, #7 /* get those 3 bits alone */
+ cmp r1, #2
+ blt skip /* no cache or only instruction cache at this level */
+ mcr p15, 2, r10, c0, c0, 0 /* write the Cache Size selection register */
+ isb /* isb to sync the change to the CacheSizeID reg */
+ mrc p15, 1, r1, c0, c0, 0 /* reads current Cache Size ID register */
+ and r2, r1, #7 /* extract the line length field */
+ add r2, r2, #4 /* add 4 for the line length offset (log2 16 bytes) */
+ ldr r4, =0x3ff
+ ands r4, r4, r1, lsr #3 /* r4 is the max number on the way size (right aligned) */
+ clz r5, r4 /* r5 is the bit position of the way size increment */
+ ldr r7, =0x7fff
+ ands r7, r7, r1, lsr #13 /* r7 is the max number of the index size (right aligned) */
+loop2:
+ mov r9, r4 /* r9 working copy of the max way size (right aligned) */
+loop3:
+ orr r11, r10, r9, lsl r5 /* factor in the way number and cache number into r11 */
+ orr r11, r11, r7, lsl r2 /* factor in the index number */
+ mcr p15, 0, r11, c7, c6, 2 /* invalidate by set/way */
+ subs r9, r9, #1 /* decrement the way number */
+ bge loop3
+ subs r7, r7, #1 /* decrement the index */
+ bge loop2
+skip:
+ add r10, r10, #2 /* increment the cache number */
+ cmp r3, r10
+ bgt loop1
+
+finished:
+ mov r10, #0 /* switch back to cache level 0 */
+ mcr p15, 2, r10, c0, c0, 0 /* select current cache level in cssr */
+ dsb
+ isb
+
+ bx lr
+
+.end
+/**
+* @} End of "addtogroup a9_boot_code".
+*/
\ No newline at end of file
diff --git a/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v7_1/src/bspconfig.h b/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v7_1/src/bspconfig.h
new file mode 100644
index 0000000..5387688
--- /dev/null
+++ b/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v7_1/src/bspconfig.h
@@ -0,0 +1,40 @@
+
+/*******************************************************************
+*
+* CAUTION: This file is automatically generated by HSI.
+* Version: 2019.2
+* DO NOT EDIT.
+*
+* Copyright (C) 2010-2021 Xilinx, Inc. All Rights Reserved.*
+*Permission is hereby granted, free of charge, to any person obtaining a copy
+*of this software and associated documentation files (the Software), to deal
+*in the Software without restriction, including without limitation the rights
+*to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+*copies of the Software, and to permit persons to whom the Software is
+*furnished to do so, subject to the following conditions:
+*
+*The above copyright notice and this permission notice shall be included in
+*all copies or substantial portions of the Software.
+*
+*THE SOFTWARE IS PROVIDED AS IS, WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+*IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+*FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+*THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+*WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT
+*OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+*
+
+*
+* Description: Configurations for Standalone BSP
+*
+*******************************************************************/
+
+#ifndef BSPCONFIG_H /* prevent circular inclusions */
+#define BSPCONFIG_H /* by using protection macros */
+
+#define MICROBLAZE_PVR_NONE
+
+/* Definition for hard-float ABI */
+#define FPU_HARD_FLOAT_ABI_ENABLED 1
+
+#endif /*end of __BSPCONFIG_H_*/
diff --git a/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v7_1/src/changelog.txt b/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v7_1/src/changelog.txt
new file mode 100644
index 0000000..648f443
--- /dev/null
+++ b/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v7_1/src/changelog.txt
@@ -0,0 +1,618 @@
+/*****************************************************************************
+ * MODIFICATION HISTORY:
+ *
+ * Ver Who Date Changes
+ * ----- ---- -------- ---------------------------------------------------
+ * 3.02a sdm 05/30/11 Added Xuint64 typedef and XUINT64_MSW/XUINT64_LSW macros
+ * 3.02a sdm 06/27/11 Added INST_SYNC and DATA_SYNC macros for all the CPUs
+ * 3.02a sdm 07/07/11 Updated ppc440 boot.S to set guarded bit for all but
+ * cacheable regions
+ * Update ppc440/xil_cache.c to use CACHEABLE_REGION_MASK
+ * generated by the cpu driver, for enabling caches
+ * 3.02a sdm 07/08/11 Updated microblaze cache flush APIs based on write-back/
+ * write-thru caches
+ * 3.03a sdm 08/20/11 Updated the tag/data RAM latency values for L2CC
+ * Updated the MMU table to mark OCM in high address space
+ * as inner cacheable and reserved space as Invalid
+ * 3.03a sdm 08/20/11 Changes to support FreeRTOS
+ * Updated the MMU table to mark upper half of the DDR as
+ * non-cacheable
+ * Setup supervisor and abort mode stacks
+ * Do not initialize/enable L2CC in case of AMP
+ * Initialize UART1 for 9600bps in case of AMP
+ * 3.03a sdm 08/27/11 Setup abort and supervisor mode stacks and don't init SMC
+ * in case of AMP
+ * 3.03a sdm 09/14/11 Added code for performance monitor and L2CC event
+ * counters
+ * 3.03a sdm 11/08/11 Updated microblaze xil_cache.h file to include
+ * xparameters.h file for CR630532 - Xil_DCacheFlush()/
+ * Xil_DCacheFlushRange() functions in standalone BSP v3_02a
+ * for MicroBlaze will invalidate data in the cache instead
+ * of flushing it for writeback caches
+ * 3.04a sdm 11/21/11 Updated to initialize stdio device for 115200bps, for PS7
+ * 3.04a sdm 01/02/12 Updated to clear cp15 regs with unknown reset values
+ * Remove redundant dsb/dmb instructions in cache maintenance
+ * APIs
+ * Remove redundant dsb in mcr instruction
+ * 3.04a sdm 01/13/12 Updated MMU table to mark DDR memory as Shareable
+ * 3.05a sdm 02/02/12 Removed some of the defines as they are being generated through
+ * driver tcl in xparameters.h. Update the gcc/translationtable.s
+ * for the QSPI complete address range - DT644567
+ * Removed profile directory for armcc compiler and changed
+ * profiling setting to false in standalone_v2_1_0.tcl file
+ * Deleting boot.S file after preprocessing for armcc compiler
+ * 3.05a asa 03/11/12 Updated the function Xil_EnableMMU in file xil_mmu.c to
+ * invalidate the caches before enabling back the MMU and
+ * D cache.
+ * 3.05a asa 04/15/12 Updated the function Xil_SetTlbAttributes in file
+ * xil_mmu.c. Now we invalidate UTLB, Branch predictor
+ * array, flush the D-cache before changing the attributes
+ * in translation table. The user need not call Xil_DisableMMU
+ * before calling Xil_SetTlbAttributes.
+ * 3.06a asa/ 06/17/12 Removed the UART initialization for Zynq. For PEEP, the UART
+ * sgd initialization is present. Changes for this were done in
+ * uart.c and xil-crt0.s.
+ * Made changes in xil_io.c to use volatile pointers.
+ * Made changes in xil_mmu.c to correct the function
+ * Xil_SetTlbAttributes.
+ * Changes are made xil-crt0.s to initialize the static
+ * C++ constructors.
+ * Changes are made in boot.s, to fix the TTBR settings,
+ * correct the L2 Cache Auxiliary register settings, L2 cache
+ * latency settings.
+ * 3.07a asa/ 07/16/12 Made changes in cortexa9/xtime_l.c, xtime_l.h, sleep.c
+ * sgd usleep.c to use global timer instead of CP15.
+ * Made changes in cortexa9/gcc/translation_table.s to map
+ * the peripheral devices as shareable device memory.
+ * Made changes in cortexa9/gcc/xil-crt0.s to initialize
+ * the global timer.
+ * Made changes in cortexa9/armcc/boot.S to initialize
+ * the global timer.
+ * Made changes in cortexa9/armcc/translation_table.s to
+ * map the peripheral devices as shareable device memory.
+ * Made changes in cortexa9/gcc/boot.S to optimize the
+ * L2 cache settings. Changes the section properties for
+ * ".mmu_tbl" and ".boot" sections in cortexa9/gcc/boot.S
+ * and cortexa9/gcc/translation_table.S.
+ * Made changes in cortexa9/xil_cache.c to change the
+ * cache invalidation order.
+ * 3.07a asa 08/17/12 Made changes across files for Cortexa9 to remove
+ * compilation/linking issues for C++ compiler.
+ * Made changes in mb_interface.h to remove compilation/
+ * linking issues for C++ compiler.
+ * Added macros for swapb and swaph microblaze instructions
+ * mb_interface.h
+ * Remove barrier usage (SYNCHRONIZE_IO) from xil_io.c
+ * for CortexA9.
+ * 3.07a asa 08/30/12 Updated for CR 675636 to provide the L2 Base Address
+ * 3.07a asa 08/31/12 Added xil_printf.h include
+ * 3.07a sgd 09/18/12 Corrected the L2 cache enable settings
+ * Corrected L2 cache sequence disable sequence
+ * 3.07a sgd 10/19/12 SMC NOR and SRAM initialization with compiler option
+ * 3.09a asa 01/25/13 Updated to push and pop neon registers into stack for
+ * irq/fiq handling.
+ * Relocated COUNTS_PER_SECOND from sleep.c to xtime_l.h. This
+ * fixes the CR #692094.
+ * 3.09a sgd 02/14/13 Fix for CRs 697094 (SI#687034) and 675552.
+ * 3.10a srt 04/18/13 Implemented ARM Erratas.
+ * Cortex A9 Errata - 742230, 743622, 775420, 794073
+ * L2Cache PL310 Errata - 588369, 727915, 759370
+ * Please refer to file 'xil_errata.h' for errata
+ * description.
+ * 3.10a asa 05/04/13 Added support for L2 cache in MicroBlaze BSP. The older
+ * cache APIs were corresponding to only Layer 1 cache
+ * memories. New APIs were now added and the existing cache
+ * related APIs were changed to provide a uniform interface
+ * to flush/invalidate/enable/disable the complete cache
+ * system which includes both L1 and L2 caches. The changes
+ * for these were done in:
+ * src/microblaze/xil_cache.c and src/microblaze/xil_cache.h
+ * files.
+ * Four new files were added for supporting L2 cache. They are:
+ * microblaze_flush_cache_ext.S-> Flushes L2 cache
+ * microblaze_flush_cache_ext_range.S -> Flushes a range of
+ * memory in L2 cache.
+ * microblaze_invalidate_cache_ext.S-> Invalidates L2 cache
+ * microblaze_invalidate_cache_ext_range -> Invalidates a
+ * range of memory in L2 cache.
+ * These changes are done to implement PR #697214.
+ * 3.10a asa 05/13/13 Modified cache disable APIs at src/cortexa9/xil_cache.c to
+ * fix the CR #706464. L2 cache disabling happens independent
+ * of L1 data cache disable operation. Changes are done in the
+ * same file in cache handling APIs to do a L2 cache sync
+ * (poll reg7_?cache_?sync). This fixes CR #700542.
+ * 3.10a asa 05/20/13 Added API/Macros for enabling and disabling nested
+ * interrupts for ARM. These are done to fix the CR#699680.
+ * 3.10a srt 05/20/13 Made changes in cache maintenance APIs to do a proper cach
+ * sync operation. This fixes the CR# 716781.
+ * 3.11a asa 09/07/13 Updated armcc specific BSP files to have proper support
+ * for armcc toolchain.
+ * Modified asm_vectors.S (gcc) and asm_vectors.s (armcc) to
+ * fix issues related to NEON context saving. The assembly
+ * routines for IRQ and FIQ handling are modified.
+ * Deprecated the older BSP (3.10a).
+ * 3.11a asa 09/22/13 Fix for CR#732704. Cache APIs are modified to avoid
+ * various potential issues. Made changes in the function
+ * Xil_SetAttributes in file xil_mmu.c.
+ * 3.11a asa 09/23/13 Added files xil_misc_psreset_api.c and xil_misc_psreset_api.h
+ * in src\cortexa9 and src\microblaze folders.
+ * 3.11a asa 09/28/13 Modified the cache APIs (src\cortexa9) to fix handling of
+ * L2 cache sync operation and to fix issues around complete
+ * L2 cache flush/invalidation by ways.
+ * 3.12a asa 10/22/13 Modified the files xpseudo_asm_rvct.c and xpseudo_asm_rvct.h
+ * to fix linking issues with armcc/DS-5. Modified the armcc
+ * makefile to fix issues.
+ * 3.12a asa 11/15/13 Fix for CR#754800. It fixes issues around profiling for MB.
+ * 4.0 hk 12/13/13 Added check for STDOUT_BASEADDRESS where outbyte is used.
+ * 4.0 pkp 22/01/14 Modified return addresses for interrupt handlers (DataAbortHandler
+ * and SWIHandler) in asm_vector.S (src\cortexa9\gcc\ and
+ * src\cortexa9\armcc\) to fix CR#767251
+ * 4.0 pkp 24/01/14 Modified cache APIs (Xil_DCacheInvalidateRange and
+ * Xil_L1DCacheInvalidate) in xil_cache.c (src\cortexa9) to fix the bugs.
+ * Few cache lines were missed to invalidate when unaligned address
+ * invalidation was accommodated in Xil_DCacheInvalidateRange.
+ * In Xil_L1DCacheInvalidate, while invalidating all L1D cache
+ * stack memory (which contains return address) was invalidated. So
+ * stack memory is flushed first and then L1D cache is invalidated.
+ * This is done to fix CR #763829
+ * 4.0 adk 22/02/2014 Fixed the CR:775379 removed unnecessay _t(unit32_t etc) from
+ * mblaze_nt_types.h file and replace uint32_t with u32 in the
+ * profile_hist.c to fix the above CR.
+ * 4.1 bss 04/14/14 Updated driver tcl to remove _interrupt_handler.o from libgloss.a
+ * instead of libxil.a and added prototypes for
+ * microblaze_invalidate_cache_ext and microblaze_flush_cache_ext in
+ * mb_interface.h
+ * 4.1 hk 04/18/14 Add sleep function.
+ * 4.1 asa 04/21/14 Fix for CR#764881. Added support for msrset and msrclr. Renamed
+ * some of the *.s files inMB BSP source to *.S.
+ * 4.1 asa 04/28/14 Fix for CR#772280. Made changes in file cortexa9/gcc/read.c.
+ * 4.1 bss 04/29/14 Modified driver tcl to use libxil.a if libgloss.a does not exist
+ * CR#794205
+ * 4.1 asa 05/09/14 Fix for CR#798230. Made changes in cortexa9/xil_cache.c and
+ * common/xil_testcache.c
+ * Fix for CR#764881.
+ * 4.1 srt 06/27/14 Remove '#undef DEBUG' from src/common/xdebug.h, which allows to
+ * output the DEBUG logs when -DDEBUG flag is enabled in BSP.
+ * 4.2 pkp 06/27/14 Added support for IAR compiler in src/cortexa9/iccarm.
+ * Also added explanatory notes in cortexa9/xil_cache.c for CR#785243.
+ * 4.2 pkp 06/19/14 Asynchronous abort has been enabled into cortexa9/gcc/boot.s and
+ * cortexa9/armcc/boot.s. Added default exception handlers for data
+ * abort and prefetch abort using handlers called
+ * DataAbortHandler and PrefetchAbortHandler respectively in
+ * cortexa9/xil_exception.c to fix CR#802862.
+ * 4.2 pkp 06/30/14 MakeFile for cortexa9/armcc has been changed to fixes the
+ * issue of improper linking of translation_table.s
+ * 4.2 pkp 07/04/14 added weak attribute for the function in BSP which are also present
+ * in tool chain to avoid conflicts into some special cases
+ * 4.2 pkp 07/21/14 Corrected reset value of event counter in function
+ * Xpm_ResetEventCounters in src/cortexa9/xpm_counter.c to fix CR#796275
+ * 4.2 pkp 07/21/14 Included xil_types.h file in xil_mmu.h which had contained a function
+ * containing type def u32 defined in xil_types.g to resolve issue of
+ * CR#805869
+ * 4.2 pkp 08/04/14 Removed unimplemented nanosleep routine from cortexa9/usleep.c as
+ * it is not possible to generate timer in nanosecond due to limited
+ * cpu frequency
+ * 4.2 pkp 08/04/14 Removed PEEP board related code which contained initialization of
+ * uart, smc nor and sram from cortexa9/gcc/xil-crt0.s and armcc/boot.s
+ * and iccarm/boot.s. Also uart.c and smc.c have been removed. Also
+ * removed function definition of XSmc_NorInit and XSmc_NorInit from
+ * cortexa9/smc.h
+ * 4.2 bss 08/11/14 Added microblaze_flush_cache_ext_range and microblaze_invalidate_
+ * cache_ext_range declarations in mb_interface.h CR#783821.
+ * Modified profile_mcount_mb.S to fix CR#808412.
+ * 4.2 pkp 08/21/14 modified makefile of iccarm for proper linking of objectfiles in
+ * cortexa9/iccarm to fix CR#816701
+ * 4.2 pkp 09/02/14 modified translation table entries in cortexa9/gcc/translation_table.s,
+ * armcc/translation_table.s and iccarm/translation_table.s
+ * to properly defined reserved entries according to address map for
+ * fixing CR#820146
+ * 4.2 pkp 09/11/14 modified translation table entries in cortexa9/iccarm/translation_table.s
+ * and cortexa9/armcc/translation_table.s to resolve compilation
+ * error for solving CR#822897
+ * 5.0 kvn 12/9/14 Support for Zync Ultrascale Mp.Also modified code for
+ * MISRA-C:2012 compliance.
+ * 5.0 pkp 12/15/14 Added APIs to get information about the platforms running the code by
+ * adding src/common/xplatform_info.*s
+ * 5.0 pkp 16/12/14 Modified boot code to enable scu after MMU is enabled and
+ * removed incorrect initialization of TLB lockdown register to fix
+ * CR#830580 in cortexa9/gcc/boot.S & cpu_init.S, armcc/boot.S
+ * and iccarm/boot.s
+ * 5.0 pkp 25/02/15 Modified floating point flag to vfpv3 from vfpv3_d16 in BSP MakeFile
+ * for iccarm and armcc compiler of cortexA9
+ * 5.1 pkp 05/13/15 Changed the initialization order in cortexa9/gcc/boot.S, iccarm/boot.s
+ * and armcc/boot.s so to first invalidate caches and TLB, enable MMU and
+ * caches, then enable SMP bit in ACTLR. L2Cache invalidation and enabling
+ * of L2Cache is done later.
+ * 5.1 pkp 12/05/15 Modified cortexa9/xil_cache.c to modify Xil_DCacheInvalidateRange and
+ * Xil_DCacheFlushRange to remove unnecessary dsb which is unnecessarily
+ * taking long time to fix CR#853097. L2CacheSync is added into
+ * Xil_L2CacheInvalidateRange API. Xil_L1DCacheInvalidate and
+ * Xil_L2CacheInvalidate APIs are modified to flush the complete stack
+ * instead of just System Stack
+ * 5.1 pkp 14/05/15 Modified cortexa9/gcc/Makefile to keep a correct check of a compiler
+ * to update ECC_FLAGS and also take the compiler and archiver as specified
+ * in settings instead of hardcoding it.
+ * 5.2 pkp 06/08/15 Modified cortexa9/gcc/translation_table.S to put a check for
+ * XPAR_PS7_DDR_0_S_AXI_BASEADDR to confirm if DDR is present or not and
+ * accordingly generate the translation table
+ * 5.2 pkp 23/07/15 Modified cortexa9/gcc/Makefile to keep a correct check of a compiler
+ * to update ECC_FLAGS to fix a bug introduced during new version creation
+ * of BSP.
+ * 5.3 pkp 10/07/15 Modified cortexa9/xil_cache.c file to change cache API so that L2 Cache
+ * functionalities are avoided for the OpenAMP slave application(when
+ * USE_AMP flag is defined for BSP) as master CPU would be utilizing L2
+ * cache for its operation. Also file operations such as read, write,
+ * close, open are also avoided for OpenAMP support(when USE_AMP flag is
+ * defined for BSP) because XilOpenAMP library contains own file operation.
+ * The xil-crt0.S file is modified for not initializing global timer for
+ * OpenAMP application as it might be already in use by master CPU
+ * 5.3 pkp 10/09/15 Modified cortexa9/iccarm/xpseudo_asm_iccarm.h file to change function
+ * definition for dsb, isb and dmb to fix the compilation error when used
+ * kvn 16/10/15 Encapsulated assembly code into macros for R5 xil_cache file.
+ * 5.4 pkp 09/11/15 Modified cortexr5/gcc/boot.S to disable ACTLR.DBWR bit to avoid potential
+ * R5 deadlock for errata 780125
+ * 5.4 pkp 09/11/15 Modified cortexa53/32bit/gcc/boot.S to enable I-Cache and D-Cache for a53
+ * 32 bit BSP in the initialization
+ * 5.4 pkp 09/11/15 Modified cortexa9/xil_misc_psreset_api.c file to change the description
+ * for XOcm_Remap function
+ * 5.4 pkp 16/11/15 Modified microblaze/xil_misc_psreset_api.c file to change the description
+ * for XOcm_Remap function
+ * kvn 21/11/15 Added volatile keyword for ADDR variables in Xil_Out API
+ * kvn 21/11/15 Changed ADDR variable type from u32 to UINTPTR. This is
+ * required for MISRA-C:2012 Compliance.
+ * 5.4 pkp 23/11/15 Added attribute definitions for Xil_SetTlbAttributes API of Cortex-A9
+ * in cortexa9/xil_mmu.h
+ * 5.4 pkp 23/11/15 Added default undefined exception handler for Cortex-A9
+ * 5.4 pkp 11/12/15 Modified common/xplatform_info.h to add #defines for silicon for
+ * checking the current executing platform
+ * 5.4 pkp 18/12/15 Modified cortexa53/32bit/gcc/xil-crt0.S and 64bit/gcc/xil-crt0.S
+ * to initialize global constructor for C++ applications
+ * 5.4 pkp 18/12/15 Modified cortexr5/gcc/xil-crt0.S to initialize global constructor for
+ * C++ applications
+ * 5.4 pkp 18/12/15 Modified cortexa53/32bit/gcc/translation_table.S and 64bit/gcc/
+ * translation_table.S to update the translation table according to proper
+ * address map
+ * 5.4 pkp 18/12/15 Modified cortexar5/mpu.c to initialize the MPU according to proper
+ * address map
+ * 5.4 pkp 05/01/16 Modified cortexa53/64bit/boot.S to set the reset vector register RVBAR
+ * equivalent to vector table base address
+ * 5.4 pkp 08/01/16 Modified cortexa9/gcc/Makefile to update the extra compiler flag
+ * as per the toolchain update
+ * 5.4 pkp 12/01/16 Changed common/xplatform_info.* to add platform information support
+ * for Cortex-A53 32bit mode
+ * 5.4 pkp 28/01/16 Modified cortexa53/32bit/sleep.c and usleep.c & cortexa53/64bit/sleep.c
+ * and usleep.c to correct routines to avoid hardcoding the timer frequency,
+ * instead take it from xparameters.h to properly configure the timestamp
+ * clock frequency
+ * 5.4 asa 29/01/16 Modified microblaze/mb_interface.h to add macros that support the
+ * new instructions for MB address extension feature
+ * 5.4 kvn 30/01/16 Modified xparameters_ps.h file to add interrupt ID number for
+ * system monitor.
+ * 5.4 pkp 04/02/16 Modified cortexr5/gcc/boot.S to enable fault log for lock-step mode
+ * 5.4 pkp 19/02/16 Modified cortexr5/xtime_l.c to add an API XTime_StartTimer and updated
+ * cortexr5/xil-crt0.S to configure the TTC3 timer when present. Modified
+ * cortexr5/sleep.c, cortexr5/usleep.c to use TTC3 when present otherwise
+ * use set of assembly instructions to provide required delay to fix
+ * CR#913249.
+ * 5.4 asa 25/02/16 Made changes in xil-crt0.S for R5, A53 64 and 32 bit BSPs, to replace
+ * _exit with exit. We should not be directly calling _exit and should
+ * always use the library exit. This fixes the CR#937036.
+ * 5.4 pkp 25/02/16 Made change to cortexr5/gcc/boot.S to initialize the floating point
+ * registers, banked registers for various modes and enabled
+ * the cache ECC check before enabling the fault log for lock step mode
+ * Also modified the cortexr5/gcc/Makefile to support floating point
+ * registers initialization in boot code.
+ * 5.4 pkp 03/01/16 Updated the exit function in cortexr5/gcc/_exit.c to enable the debug
+ * logic in case of lock-step mode when fault log is enabled to fix
+ * CR#938281
+ * 5.4 pkp 03/02/16 Modified cortexa9/iccarm/xpseudo_asm_iccarm.h file to include
+ * header file instrinsics.h which contains assembly instructions
+ * definitions which can be used by C
+ * 5.4 asa 03/02/16 Added print.c in MB BSP. Made other cosmetic changes to have uniform
+ * proto for all print.c across the BSPs. This patch fixes CR#938738.
+ * 5.4 pkp 03/09/16 Modified cortexr5/sleep.c and usleep.c to avoid disabling the
+ * interrupts when sleep/usleep is being executed using assembly
+ * instructions to fix CR#913249.
+ * 5.4 pkp 03/11/16 Modified cortexr5/xtime_l.c to avoid enabling overflow interrupt,
+ * instead modified cortexr5/sleep.c and usleep.c to poll the counter
+ * value and compare it with previous value to detect the overflow
+ * to fix CR#940209.
+ * 5.4 pkp 03/24/16 Modified cortexr5/boot.S to reset the dbg_lpd_reset before enabling
+ * the fault log to avoid intervention for lock-step mode and cortexr5/
+ * _exit.c to enable the dbg_lpd_reset once the fault log is disabled
+ * to fix CR#947335
+ * 5.5 pkp 04/11/16 Modified cortexr5/boot.S to enable comparators for non-JTAG bootmode
+ * in lock-step to avoid resetting the debug logic which restricts the
+ * access for debugger and removed enabling back of debug modules in
+ * cortexr5/_exit.c
+ * 5.5 pkp 04/13/16 Modified cortexa9/gcc/read.c to return correct number of bytes when
+ * read buffer is filled and removed the redundant NULL checking for
+ * buffer to simplify the code
+ * 5.5 pkp 04/13/16 Modified cortexa53/64bit/gcc/read.c and cortexa53/32bit/gcc/read.c
+ * to return correct number of bytes when read buffer is filled and
+ * removed the redundant NULL checking for buffer to simplify the code
+ * 5.5 pkp 04/13/16 Modified cortexr5/gcc/read.c to return correct number of bytes when
+ * read buffer is filled and removed the redundant NULL checking for
+ * buffer to simplify the code
+ * 5.5 pkp 04/13/16 Modified cortexa53/64bit/xpseudo_asm_gcc.h to add volatile to asm
+ * instruction macros to disable certain optimizations which may move
+ * code out of loops if optimizers believe that the code will always
+ * return the same result or discard asm statements if optimizers
+ * determine there is no need for the output variables
+ * 5.5 pkp 04/13/16 Modified cortexa53/64bit/xtime_l.c to add XTime_StartTimer which
+ * starts the timer if it is disabled and modified XTime_GetTime to
+ * enable the timer if it is not enabled. Also modified cortexa53/64bit/
+ * sleep.c and cortexa53/64bit/usleep.c to enable the timer if it is
+ * disabled and read the counter value directly from register instead
+ * of using XTime_GetTime for optimization
+ * 5.5 pkp 04/13/16 Modified cortexa53/32bit/xtime_l.c to add XTime_StartTimer which
+ * starts the timer if it is disabled and modified XTime_GetTime to
+ * enable the timer if it is not enabled. Also modified cortexa53/32bit/
+ * sleep.c and cortexa53/32bit/usleep.c to enable the timer if it is
+ * disabled and read the counter value directly from register instead
+ * of using XTime_GetTime for optimization
+ * 5.5 pkp 04/13/16 Modified cortexa53/32bit/xil_cache.c and cortexa53/64bit/xil_cache.c
+ * to update the Xil_DCacheInvalidate, Xil_DCacheInvalidateLine and
+ * Xil_DCacheInvalidateRange functions description for proper
+ * explanation to fix CR#949801
+ * 5.5 asa 04/20/16 Added missing macros for hibernate and suspend in Microblaze BSP
+ * file mb_interface.h. This fixes the CR#949503.
+ * 5.5 asa 04/29/16 Fix for CR#951080. Updated cache APIs for HW designs where cache
+ * memory is not included for MicroBlaze.
+ * 5.5 pkp 05/06/16 Modified the cortexa9/xil_exception.h to update the macros
+ * Xil_EnableNestedInterrupts and Xil_DisableNestedInterrupts for fixing
+ * the issue of lr being corrupted to resolve CR#950468
+ * 5.5 pkp 05/06/16 Modified the cortexr5/xil_exception.h to update the macros
+ * Xil_EnableNestedInterrupts and Xil_DisableNestedInterrupts for fixing
+ * the issue of lr being corrupted to resolve CR#950468
+ * 6.0 kvn 05/31/16 Make Xil_AsserWait a global variable
+ * 6.0 pkp 06/27/16 Updated cortexr5/mpu.c to move the code related to Init_MPU to .boot
+ * section since it is part of boot process to fix CR#949555
+ * hk 07/12/16 Correct masks for IOU SLCR GEM registers
+ * 6.0 pkp 07/25/16 Program the counter frequency in boot code for CortexA53
+ * 6.0 asa 08/03/16 Updated sleep_common function in microblaze_sleep.c to improve the
+ * the accuracy of MB sleep functionality. This fixes the CR#954191.
+ * 6.0 mus 08/03/16 Restructured the BSP to avoid code duplication across all BSPs.
+ * Source code directories specific to ARM processor's are moved to src/arm
+ * directory(i.e. src/cortexa53,src/cortexa9 and src/cortexr5 moved to src/arm/cortexa53,
+ * src/arm/cortexa9 and src/arm/cortexr5 respectively).Files xil_printf.c,xil_printf.h,
+ * print.c,xil_io.c and xil_io.h are consolidated across all BSPs into common file each and
+ * consolidated files are kept at src/common directory.Files putnum.c,vectors.c,vectors.h,
+ * xil_exception.c and xil_exception.h are consolidated across all ARM BSPs
+ * into common file each and consolidated files are kept at src/arm/common directory.
+ * GCC source files related to file operations are consolidated and kept
+ * at src/arm/common/gcc directory.
+ * All io interfacing functions (i.e. All variants of xil_out, xil_in )
+ * are made as static inline and implementation is kept in consolidated common/xil_io.h,
+ * xil_io.h must be included as a header file to access io interfacing functions.
+ * Added undefined exception handler for A53 32 bit and R5 processor
+ * 6.0 mus 08/11/16 Updated xtime_l.c in R5 BSP to remove implementation of XTime_SetTime API, since
+ * TTC counter value register is read only.
+ * 6.0 asa 08/15/16 Modified the signatures for functions sleep and usleep. This fixes
+ * the CR#956899.
+ * 6.0 mus 08/18/16 Defined ARMA53_32 flag in cortexa53/32bit/xparameters_ps.h and ARMR5 flag
+ * in cortexr5/xparameters_ps.h
+ * 6.0 mus 08/18/16 Added support for the the Zynq 7000s devices
+ * 6.0 mus 08/18/16 Removed unused variables from xil_printf.c and xplatform_info.c
+ * 6.0 mus 08/19/16 Modified xil_io.h to remove __LITTLE_ENDIAN__ flag check for all ARM processors
+ * 6.1 mus 11/03/16 Added APIs handle_stdin_parameter and handle_stdout_parameter in standalone tcl.
+ * ::hsi::utils::handle_stdin and ::hsi::utils::handle_stdout are taken as a base for
+ * these APIs and modifications are done on top of it to handle stdout/stdin
+ * parameters for design which doesnt have UART.It fixes CR#953681
+ * 6.1 nsk 11/07/16 Added two new files xil_mem.c and xil_mem.h for xil_memcpy
+ * 6.2 pkp 12/14/16 Updated cortexa53/64bit/translation_table.S for upper ps DDR. The 0x800000000 -
+ * 0xFFFFFFFFF range is marked normal memory for the DDR size defined in hdf
+ * and rest of the memory in that 32GB region is marked as reserved to avoid
+ * any speculative access
+ * 6.2 pkp 12/23/16 Added support for floating point operation to Cortex-A53 64bit mode. It modified
+ * asm_vectors.S to implement lazy floating point context saving i.e. floating point
+ * access is enabled if there is any floating point operation, it is disabled by
+ * default. Also FPU is initially disabled for IRQ and none of the floating point
+ * registers are saved during normal context saving. If IRQ handler does not require
+ * floating point operation, the floating point registers are untouched and no need
+ * for saving/restoring. If IRQ handler uses any floating point operation, then floating
+ * point registers are saved and FPU is enabled for IRQ handler. Then floating point
+ * registers are restored back after servicing IRQ during normal context restoring.
+ * 6.2 mus 01/01/17 Updated makefiles of R5 and a53 64 bit/32 bit processors to fix error in clean
+ * target.It fixes the CR#966900
+ * 6.2 pkp 01/22/17 Added support for EL1 non-secure execution and Hypervisor Baremetal for Cortex-A53
+ * 64bit Mode. If Hypervisor_guest is selected as true in BSP settings, BSP will be built
+ * for EL1 Non-secure, else BSP will be built for EL3. By default hypervisor_guest is
+ * as false i.e. default bsp is EL3.
+ * 6.2 pkp 01/24/17 Updated cortexa53/64bit/boot.S to clear FPUStatus variable to make sure that it
+ * contains initial status of FPU i.e. disabled. In case of a warm restart execution
+ * when bss sections are not cleared, it may contain previously updated value which
+ * does not hold true once processor resumes. This fixes CR#966826.
+ * 6.2 asa 01/31/17 The existing Xil_DCacheDisable API first flushes the
+ * D caches and then disables it. The problem with that is,
+ * potentially there will be a small window after the cache
+ * flush operation and before the we disable D caches where
+ * we might have valid data in cache lines. In such a
+ * scenario disabling the D cache can lead to unknown behavior.
+ * The ideal solution to this is to use assembly code for
+ * the complete API and avoid any memory accesses. But with
+ * that we will end up having a huge amount on assembly code
+ * which is not maintainable. Changes are done to use a mix
+ * of assembly and C code. All local variables are put in
+ * registers. Also function calls are avoided in the API to
+ * avoid using stack memory.
+ * 6.2 mus 02/13/17 A53 CPU cache system can pre-fetch catch lines.So there are
+ * scenarios when an invalidated cache line can get pre fetched to cache.
+ * If that happens, the coherency between cache and memory is lost
+ * resulting in lost data. To avoid this kind of issue either
+ * user has to use dsb() or disable pre-fetching for L1 cache
+ * or else reduce maximum number of outstanding data prefetches allowed.
+ * Using dsb() while comparing data costing more performance compared to
+ * disabling pre-fetching/reducing maximum number of outstanding data
+ * prefetches for L1 Cache.The new api Xil_ConfigureL1Prefetch is added
+ * to disable pre-fetching/configure maximum number of outstanding data
+ * prefetches allowed in L1 cache system.This fixes CR#967864.
+ * 6.2 pkp 02/16/17 Added xil_smc.c file to provide a C wrapper for smc calling which can be
+ * used by cortex-A53 64bit EL1 Non-secure application.
+ * 6.2 kvn 03/03/17 Added support thumb mode
+ * 6.2 mus 03/13/17 Fixed MISRA C mandatory standard violations in ARM cortexr5 and cortexa53 BSP.
+ * It fixes CR#970543
+ * 6.2 asa 03/16/17 Fix for CR#970859. For Mcroblaze BSP, when we enable intrusive
+ * profiling we see a crash. That is because the the tcl uses invalid
+ * HSI command. This change fixes it.
+ * 6.2 mus 03/22/17 Updated standalone tcl to generate xparameter XPAR_FPD_IS_CACHE_COHERENT, if
+ * any FPD peripheral is configured to use CCI.It fixes CR#972638
+ * 6.3 mus 03/20/17 Updated cortex-r5 BSP, to add hard floating point support.
+ * 6.3 mus 04/17/17 Updated Cortex-a53 32 bit BSP boot code to fix bug in
+ * the HW coherency enablement. It fixes the CR#973287
+ * 6.3 mus 04/20/17 Updated Cortex-A53 64 bit BSP boot code, to remove redundant write to the
+ * L2CTLR_EL1 register. It fixes the CR#974698
+ * 6.4 mus 06/08/17 Updated arm/common/xil_exception.c to fix warnings in C level exception handlers
+ * of ARM 32 bit processor's.
+ * 6.4 mus 06/14/17 Updated cortexa53/64bit/gcc/asm_vectors.S to fix bug in IRQInterruptHandler code
+ * snippet, which checks for the FPEN bit of CPACR_EL1 register.
+ * 6.4 ms 05/23/17 Added PSU_PMU macro in xplatform_info.c, xparameters.h to support
+ * XGetPSVersion_Info function for PMUFW.
+ * ms 06/13/17 Added PSU_PMU macro in xplatform_info.c to support XGetPlatform_Info
+ * function for PMUFW.
+ * 6.4 mus 07/05/17 Updated Xil_In32BE function in xil_io.h to fix bug.It fixes CR#979740.
+ * 6.4 mus 07/25/17 Updated a53 32 bit boot code and vectors to support hard floating point
+ * operations.Now,VFP is being enabled in FPEXC register, through boot code
+ * and FPU registers are being saved/restored when irq/fiq vector is invoked.
+ * 6.4 adk 08/01/17 Updated standalone tcl to generate xparameter XPAR_PL_IS_CACHE_COHERENT,
+ * if h/w design configured with HPC port.
+ * 6.4 mus 08/10/17 Updated a53 64 bit translation table to mark memory as a outer shareable for
+ * EL1 NS execution. This change has been done to support CCI enabled IP's.
+ * 6.4 mus 08/11/17 Updated a53 64 bit boot code to implement ARM erratum 855873.This fixes
+ * CR#982209.
+ * 6.4 asa 08/16/17 Made several changes in the R5 MPU handling logic. Added new APIs to
+ * make RPU MPU handling user-friendly. This also fixes the CR-981028.
+ * 6.4 mus 08/17/17 Updated XGet_Zynq_UltraMp_Platform_info and XGetPSVersion_Info APIs to read
+ * version register through SMC call, over EL1 NS mode. This change has been done to
+ * support these APIs over EL1 NS mode.
+ * 6.5 mus 10/20/17 Updated standalone.tcl to fix bug in mb_can_handle_exceptions_in_delay_slots proc,
+ * it fixes CR#987464.
+ * 6.6 mus 12/07/17 Updated cortexa9/xil_errata.h and cortexa9/xil_cache.c to remove Errata 753970.
+ * It fixes CR#989132.
+ * srm 10/18/17 Updated all the sleep routines in a9,a53,R5,microblaze. Now the sleep routines
+ * will use the timer specified by the user to provide delay. A9 and A53 can use
+ * Global timer or TTC. R5 can use TTC or the machine cycles. Microblaze can use
+ * machine cycles or Axi timer. Updated standalone.tcl and standalone.mld files
+ * to support the sleep configuration Added new API's for the Axi timer in
+ * microblaze and TTC in ARM. Added two new files, xil_sleeptimer.c and
+ * xil_sleeptimer.h in ARM for the common sleep routines and 1 new file,
+ * xil_sleepcommon.c in Standalone-common for sleep/usleep API's.
+ * 6.6 hk 12/15/17 Export platform macros to bspconfig.h based on the processor.
+ * 6.6 asa 1/16/18 Ensure C stack information for A9 are flushed out from L1 D cache
+ * or L2 cache only when the respective caches are enabled. This fixes CR-922023.
+ * 6.6 mus 01/19/18 Updated asm_vectors.S and boot.S in Cortexa53 64 bit BSP, to add isb
+ * after writing to cpacr_el1/cptr_el3 registers. It would ensure
+ * disabling/enabling of floating-point unit, before any subsequent
+ * instruction.
+ * 6.6 hk 12/15/17 Export platform macros to xparameters.h based on the processor.
+ * 6.6 asa 1/16/18 Ensure C stack information for A9 are flushed out from L1 D cache
+ * or L2 cache only when the respective caches are enabled.This fixes CR-922023.
+ *
+ * 6.6 mus 01/19/18 Updated asm_vectors.S and boot.S in Cortexa53 64 bit BSP, to add isb
+ * after writing to cpacr_el1/cptr_el3 registers. It would ensure
+ * disabling/enabling of floating-point unit, before any subsequent
+ * instruction.
+ * 6.6 mus 01/30/18 Updated hypervisor enabled Cortexa53 64 bit BSP, to add xen PV console
+ * support. Now, xil_printf would use PV console instead of UART in case of
+ * hypervisor enabled BSP.
+ * 6.6 mus 02/02/18 Updated get_connected_if proc in standalone tcl to detect the HPC port
+ * configured with smart interconnect.It fixes CR#990318.
+ * 6.6 srm 02/10/18 Updated csu_wdt interrupt to the correct value. Fixes CR#992229
+ * 6.6 asa 02/12/18 Fix for heap handling for ARM platforms. CR#993932.
+ * 6.6 mus 02/19/18 Updated standalone.tcl to fix bug in handle_profile_opbtimer proc,
+ * CR#995014.
+ * 6.6 mus 02/23/18 Presently Cortex R5 BSP boot code is disabling the debug logic in
+ * non-JTAG boot mode, when processor is in lockstep configuration.
+ * This behavior is restricting application debugging in non-JTAG boot
+ * mode. To get rid of this restriction, added new mld parameter
+ * "lockstep_mode_debug", to enable/disable debug logic from BSP
+ * settings. Now, debug logic can be enabled through BSP settings,
+ * by modifying value of parameter "lockstep_mode_debug" as "true".
+ * It fixes CR#993896.
+ * 6.6.mus 02/27/18 Updated Xil_DCacheInvalidateRange and
+ * Xil_ICacheInvalidateRange APIs in Cortexa53 64 bit BSP, to fix bug
+ * in handling upper DDR addresses.It fixes CR#995581.
+ * 6.6 mus 03/12/18 Updated makefile of Cortexa53 32bit BSP to add includes_ps directory
+ * in the list of include paths. This change allows applications/BSP
+ * files to include .h files in include_ps directory.
+ * 6.6 mus 03/16/18 By default CPUACTLR_EL1 is accessible only from EL3, it
+ * results into abort if accessed from EL1 non secure privilege
+ * level. Updated Xil_ConfigureL1Prefetch function in Cortexa53 64 bit BSP
+ * to avoid CPUACTLR_EL1 access from privile levels other than EL3.
+ * 6.6 mus 03/16/18 Updated hypervisor enabled BSP to use PV console, based on the
+ * XEN_USE_PV_CONSOLE flag. By default hypervisor enabled BSP would
+ * use UART console, PV console can be enabled by appending
+ * "-DXEN_USE_PV_CONSOLE" to the BSP extra compiler flags.
+ * 6.7 asa 04/26/18 Added API Xil_GetExceptionRegisterHandler for obtaining information
+ * on an already registered exception vector.
+ * 6.7 asa 05/18/18 Fixed bugss in the API Xil_GetExceptionRegisterHandler.
+ * 6.8 mus 04/27/18 Removed __ARM_NEON__ flag definition. Now, saving/restoring of of HW
+ * floating point register would be done through newly introduced flag
+ * FPU_HARD_FLOAT_ABI_ENABLED. This new flag will be configured based on
+ * the -mfpu-abi option in extra compiler flags.. This change has
+ * been done to avoid saving/restoring of HW floating point registers,
+ * when BSP is not compiled with HW floating point configuration.
+ * 6.8 aru 06/15/18 Removed unused variable in xil_cache.c for A53-32. It
+ * fixes CR1005118.
+ * 6.8 aru 07/02/18 Returned the pointer instead of address of that pointer in xil_mpu.c
+ * for R5 processor.It Fixes CR#1005119.
+ * 6.8 mus 07/12/18 Updated Cortexa9 translation table to mark DDR memory as inner cacheable,
+ * if BSP is built with the USE_AMP flag. It fixes CR#1006745.
+ *
+ * 6.8 aru 07/04/18 Optimized the code to use a loop and to remove redundant code
+ * in Xil_DCacheFlush() and Xil_DCacheInvalidate()
+ * of xil_cache.c for A53-32.
+ * 6.8 aru 07/26/18 added support in xil_printf.c to print u64 variabbles
+ * correctly in 32 bit processor.It fixes CR#1007207.
+ * 6.8 aru 09/03/18 Optimized the code to use a single function and removed
+ * code redundancy in xil_printf.c . It Fixes CR#1009654.
+ * 6.8 aru 09/06/18 Removed the compiler warnings for ARMCC toolchain.
+ * It fixes CR#1008309.
+ * 6.8 mus 09/20/18 Updated CortexR5 boot code to initialize CortexR5 core with LOVEC
+ * on reset. It fixes CR#1010656.
+ * 6.8 mus 10/04/18 Updated microblaze sleep functinality to execute default method of
+ * sleep implementation, in case of FreeRTOS BSP.
+ * 6.8 mus 10/25/18 Updated assembly code for cache APIs and inline assemby macros to
+ * to support 64 bit addresses.
+ * 6.8 asa 10/11/18 Updated the A53 32 bit cache APIs for Xil_DCacheFlush and
+ * Xil_DCacheInvalidate to fix various issues. These issues were not
+ * present in the previous releases but got introduced as part of
+ * optimization patches that got applied for 6.8 BSP version. These
+ * changes fix the CR#1016012.
+ * 7.0 rp 10/25/18 Added XST_NO_ACCESS status macros for generic access error.
+ * 7.0 mus 02/01/19 Added support for Versal. Cortea53 BSP will be re-used by Cortexa72,
+ * re-named cortexa53 directory as ARMv8, since files are generic for
+ * ARMv8 based processors. Created "platform" directory to place
+ * SoC based files.
+ * 7.0 mus 02/05/19 Updated Xil_MemCpy API to copy two bytes at a time from source to
+ * destination if byte count is <= 2.
+ * 7.0 mus 02/28/19 Added armclang compiler support to the Cortexa53 64 bit BSP.
+ * 7.0 mus 04/08/19 Fix microblaze_disable_dcache for 64 bit microblaze
+ * 7.0 mus 04/26/19 Added frequently used functions in common area in xil_utils.c,
+ * so that other modules can make use of it.
+ * 7.1 mus 03/29/19 Updated standalone tcl to export trustzone information of
+ * Cortexr5 processor and different SLCR register space being
+ * accessed in Cortexr5 BSP. Files src/arm/cortexr5/gcc/xil-crt0.S,
+ * arm/cortexr5/gcc/boot.S and arm/common/xil_sleeptimer.c have been
+ * updated to skip access to the secure address space if processor is
+ * marked as non secure in trustzone setting. It fixes CR#1015725.
+ * 7.1 aru 04/16/19 Updated arm/cortexr5/xpm_counter.c and arm/cortexr5/xpm_counter.h
+ * to fix Cortexr5 events.
+ * 7.1 sk 07/26/19 Updated src/arm/cortexr5/xil_mpu.c to fix infinite loop in
+ * Xil_MemMap API. It fixes CR#1032910
+ * 7.1 mus 07/30/19 Updated arm/ARMv8/32bit/xil_mmu.h to add #defines related to memory
+ * attributes.
+ * 7.1 mus 06/08/19 Updated arm/ARMv8/64bit/xil_smc.h with SMC ID's of Versal.
+ * 7.1 mus 29/08/19 Updated arm/ARMv8/64bit/platform/versal/translation_table.S to mark
+ * DDR_CH_1, DDR_CH_2 and DDR_CH_3 region as memory based on their
+ * respective sizes in HW design.
+ * 7.1 scs 09/09/19 Updated inline assembly macros in microblaze/mb_interface.h to fix
+ * MISRA-C mandatory violations.
+ * 7.1 mus 09/09/19 In case, if DDR size is not in power of 2, Cortexr5 BSP maps range
+ * of memory as "normal memory", where "real" memory is not present in that
+ * memory region. This behavior is due to Cortexr5 MPU restriction,
+ * which allows MPU size only in power of 2. Updated Init_MPU funcion
+ * in Cortexr5 BSP, to print warning, if DDR size is not in
+ * power of 2. This has been done to warn users about incorrect mapping
+ * for specific memory region. It fixes CR#1038577.
+ *****************************************************************************************/
diff --git a/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v7_1/src/close.c b/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v7_1/src/close.c
new file mode 100644
index 0000000..67c30ec
--- /dev/null
+++ b/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v7_1/src/close.c
@@ -0,0 +1,43 @@
+/******************************************************************************
+*
+* Copyright (C) 2009 - 2015 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+* THE SOFTWARE.
+*
+*
+*
+******************************************************************************/
+#ifndef UNDEFINE_FILE_OPS
+#include "xil_types.h"
+#ifdef __cplusplus
+extern "C" {
+ __attribute__((weak)) s32 _close(s32 fd);
+}
+#endif
+
+/*
+ * close -- We don't need to do anything, but pretend we did.
+ */
+
+__attribute__((weak)) s32 _close(s32 fd)
+{
+ (void)fd;
+ return (0);
+}
+#endif
diff --git a/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v7_1/src/config.make b/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v7_1/src/config.make
new file mode 100644
index 0000000..2668199
--- /dev/null
+++ b/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v7_1/src/config.make
@@ -0,0 +1,3 @@
+LIBSOURCES = *.c *.S
+PROFILE_ARCH_OBJS = profile_mcount_arm.o
+LIBS = standalone_libs
diff --git a/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v7_1/src/cpputest_time.c b/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v7_1/src/cpputest_time.c
new file mode 100644
index 0000000..781da2f
--- /dev/null
+++ b/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v7_1/src/cpputest_time.c
@@ -0,0 +1,47 @@
+/******************************************************************************
+*
+* Copyright (C) 2019 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+* THE SOFTWARE.
+*
+*
+*
+******************************************************************************/
+
+#ifndef UNDEFINE_FILE_OPS
+#include <errno.h>
+#include "xil_types.h"
+#include <time.h>
+struct tms* tms;
+#ifdef __cplusplus
+extern "C" {
+ __attribute__((weak)) clock_t _times(struct tms* tms);
+}
+#endif
+
+__attribute__((weak)) clock_t _times(struct tms* tms)
+{
+ (void)tms;
+
+ errno = EIO;
+ return (-1);
+}
+
+
+#endif
diff --git a/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v7_1/src/cpu_init.S b/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v7_1/src/cpu_init.S
new file mode 100644
index 0000000..5cde6c3
--- /dev/null
+++ b/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v7_1/src/cpu_init.S
@@ -0,0 +1,74 @@
+/******************************************************************************
+*
+* Copyright (C) 2009 - 2015 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+* THE SOFTWARE.
+*
+*
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+* @file cpu_init.s
+*
+* This file contains CPU specific initialization. Invoked from main CRT
+*
+* <pre>
+* MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ----- ------- -------- ---------------------------------------------------
+* 1.00a ecm/sdm 10/20/09 Initial version
+* 3.04a sdm 01/02/12 Updated to clear cp15 regs with unknown reset values
+* 5.0 pkp 12/16/14 removed incorrect initialization of TLB lockdown
+* register to fix CR#830580
+* </pre>
+*
+* @note
+*
+* None.
+*
+******************************************************************************/
+
+ .text
+ .global __cpu_init
+ .align 2
+__cpu_init:
+
+/* Clear cp15 regs with unknown reset values */
+ mov r0, #0x0
+ mcr p15, 0, r0, c5, c0, 0 /* DFSR */
+ mcr p15, 0, r0, c5, c0, 1 /* IFSR */
+ mcr p15, 0, r0, c6, c0, 0 /* DFAR */
+ mcr p15, 0, r0, c6, c0, 2 /* IFAR */
+ mcr p15, 0, r0, c9, c13, 2 /* PMXEVCNTR */
+ mcr p15, 0, r0, c13, c0, 2 /* TPIDRURW */
+ mcr p15, 0, r0, c13, c0, 3 /* TPIDRURO */
+
+/* Reset and start Cycle Counter */
+ mov r2, #0x80000000 /* clear overflow */
+ mcr p15, 0, r2, c9, c12, 3
+ mov r2, #0xd /* D, C, E */
+ mcr p15, 0, r2, c9, c12, 0
+ mov r2, #0x80000000 /* enable cycle counter */
+ mcr p15, 0, r2, c9, c12, 1
+
+ bx lr
+
+.end
diff --git a/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v7_1/src/errno.c b/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v7_1/src/errno.c
new file mode 100644
index 0000000..56ee4e1
--- /dev/null
+++ b/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v7_1/src/errno.c
@@ -0,0 +1,45 @@
+/******************************************************************************
+*
+* Copyright (C) 2009 - 2015 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+* THE SOFTWARE.
+*
+*
+*
+******************************************************************************/
+
+/* The errno variable is stored in the reentrancy structure. This
+ function returns its address for use by the macro errno defined in
+ errno.h. */
+
+#include <errno.h>
+#include <reent.h>
+#include "xil_types.h"
+
+#ifdef __cplusplus
+extern "C" {
+ __attribute__((weak)) sint32 * __errno (void);
+}
+#endif
+
+__attribute__((weak)) sint32 *
+__errno (void)
+{
+ return &_REENT->_errno;
+}
diff --git a/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v7_1/src/fcntl.c b/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v7_1/src/fcntl.c
new file mode 100644
index 0000000..5f0d02b
--- /dev/null
+++ b/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v7_1/src/fcntl.c
@@ -0,0 +1,40 @@
+/******************************************************************************
+*
+* Copyright (C) 2009 - 2015 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+* THE SOFTWARE.
+*
+*
+*
+******************************************************************************/
+
+#include <stdio.h>
+#include "xil_types.h"
+
+/*
+ * fcntl -- Manipulate a file descriptor.
+ * We don't have a filesystem, so we do nothing.
+ */
+__attribute__((weak)) sint32 fcntl (sint32 fd, sint32 cmd, long arg)
+{
+ (void)fd;
+ (void)cmd;
+ (void)arg;
+ return 0;
+}
diff --git a/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v7_1/src/fstat.c b/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v7_1/src/fstat.c
new file mode 100644
index 0000000..98cfcd8
--- /dev/null
+++ b/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v7_1/src/fstat.c
@@ -0,0 +1,44 @@
+/******************************************************************************
+*
+* Copyright (C) 2009 - 2015 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+* THE SOFTWARE.
+*
+*
+*
+******************************************************************************/
+
+#include <sys/stat.h>
+#include "xil_types.h"
+
+#ifdef __cplusplus
+extern "C" {
+ __attribute__((weak)) s32 _fstat(s32 fd, struct stat *buf);
+}
+#endif
+/*
+ * fstat -- Since we have no file system, we just return an error.
+ */
+__attribute__((weak)) s32 _fstat(s32 fd, struct stat *buf)
+{
+ (void)fd;
+ buf->st_mode = S_IFCHR; /* Always pretend to be a tty */
+
+ return (0);
+}
diff --git a/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v7_1/src/getpid.c b/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v7_1/src/getpid.c
new file mode 100644
index 0000000..f7b8acc
--- /dev/null
+++ b/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v7_1/src/getpid.c
@@ -0,0 +1,45 @@
+/******************************************************************************
+*
+* Copyright (C) 2009 - 2015 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+* THE SOFTWARE.
+*
+*
+*
+******************************************************************************/
+
+#include "xil_types.h"
+/*
+ * getpid -- only one process, so just return 1.
+ */
+#ifdef __cplusplus
+extern "C" {
+ __attribute__((weak)) s32 _getpid(void);
+}
+#endif
+
+__attribute__((weak)) s32 getpid(void)
+{
+ return 1;
+}
+
+__attribute__((weak)) s32 _getpid(void)
+{
+ return 1;
+}
diff --git a/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v7_1/src/inbyte.c b/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v7_1/src/inbyte.c
new file mode 100644
index 0000000..0036459
--- /dev/null
+++ b/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v7_1/src/inbyte.c
@@ -0,0 +1,14 @@
+#include "xparameters.h"
+#include "xuartps_hw.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+char inbyte(void);
+#ifdef __cplusplus
+}
+#endif
+
+char inbyte(void) {
+ return XUartPs_RecvByte(STDIN_BASEADDRESS);
+}
diff --git a/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v7_1/src/isatty.c b/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v7_1/src/isatty.c
new file mode 100644
index 0000000..844172c
--- /dev/null
+++ b/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v7_1/src/isatty.c
@@ -0,0 +1,50 @@
+/******************************************************************************
+*
+* Copyright (C) 2009 - 2015 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+* THE SOFTWARE.
+*
+*
+*
+******************************************************************************/
+#include <unistd.h>
+#include "xil_types.h"
+
+#ifdef __cplusplus
+extern "C" {
+ __attribute__((weak)) sint32 _isatty(sint32 fd);
+}
+#endif
+
+/*
+ * isatty -- returns 1 if connected to a terminal device,
+ * returns 0 if not. Since we're hooked up to a
+ * serial port, we'll say yes _AND return a 1.
+ */
+__attribute__((weak)) sint32 isatty(sint32 fd)
+{
+ (void)fd;
+ return (1);
+}
+
+__attribute__((weak)) sint32 _isatty(sint32 fd)
+{
+ (void)fd;
+ return (1);
+}
diff --git a/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v7_1/src/kill.c b/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v7_1/src/kill.c
new file mode 100644
index 0000000..318766c
--- /dev/null
+++ b/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v7_1/src/kill.c
@@ -0,0 +1,54 @@
+/******************************************************************************
+*
+* Copyright (C) 2014 - 2016 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+* THE SOFTWARE.
+*
+*
+*
+******************************************************************************/
+#include <signal.h>
+#include <unistd.h>
+#include "xil_types.h"
+
+#ifdef __cplusplus
+extern "C" {
+ __attribute__((weak)) int _kill(pid_t pid, int sig);
+}
+#endif
+
+/*
+ * kill -- go out via exit...
+ */
+
+__attribute__((weak)) int kill(pid_t pid, int sig)
+{
+ if(pid == 1) {
+ _exit(sig);
+ }
+ return 0;
+}
+
+__attribute__((weak)) int _kill(pid_t pid, int sig)
+{
+ if(pid == 1) {
+ _exit(sig);
+ }
+ return 0;
+}
diff --git a/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v7_1/src/lseek.c b/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v7_1/src/lseek.c
new file mode 100644
index 0000000..110a6ac
--- /dev/null
+++ b/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v7_1/src/lseek.c
@@ -0,0 +1,55 @@
+/******************************************************************************
+*
+* Copyright (C) 2009 - 2015 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+* THE SOFTWARE.
+*
+*
+*
+******************************************************************************/
+
+#include <sys/types.h>
+#include <errno.h>
+#include "xil_types.h"
+
+#ifdef __cplusplus
+extern "C" {
+ __attribute__((weak)) off_t _lseek(s32 fd, off_t offset, s32 whence);
+}
+#endif
+/*
+ * lseek -- Since a serial port is non-seekable, we return an error.
+ */
+__attribute__((weak)) off_t lseek(s32 fd, off_t offset, s32 whence)
+{
+ (void)fd;
+ (void)offset;
+ (void)whence;
+ errno = ESPIPE;
+ return ((off_t)-1);
+}
+
+__attribute__((weak)) off_t _lseek(s32 fd, off_t offset, s32 whence)
+{
+ (void)fd;
+ (void)offset;
+ (void)whence;
+ errno = ESPIPE;
+ return ((off_t)-1);
+}
diff --git a/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v7_1/src/open.c b/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v7_1/src/open.c
new file mode 100644
index 0000000..d8d57c5
--- /dev/null
+++ b/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v7_1/src/open.c
@@ -0,0 +1,47 @@
+/******************************************************************************
+*
+* Copyright (C) 2009 - 2015 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+* THE SOFTWARE.
+*
+*
+*
+******************************************************************************/
+#ifndef UNDEFINE_FILE_OPS
+#include <errno.h>
+#include "xil_types.h"
+
+#ifdef __cplusplus
+extern "C" {
+ __attribute__((weak)) s32 open(char8 *buf, s32 flags, s32 mode);
+}
+#endif
+/*
+ * open -- open a file descriptor. We don't have a filesystem, so
+ * we return an error.
+ */
+__attribute__((weak)) s32 open(char8 *buf, s32 flags, s32 mode)
+{
+ (void)buf;
+ (void)flags;
+ (void)mode;
+ errno = EIO;
+ return (-1);
+}
+#endif
diff --git a/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v7_1/src/outbyte.c b/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v7_1/src/outbyte.c
new file mode 100644
index 0000000..8b56036
--- /dev/null
+++ b/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v7_1/src/outbyte.c
@@ -0,0 +1,15 @@
+#include "xparameters.h"
+#include "xuartps_hw.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+void outbyte(char c);
+
+#ifdef __cplusplus
+}
+#endif
+
+void outbyte(char c) {
+ XUartPs_SendByte(STDOUT_BASEADDRESS, c);
+}
diff --git a/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v7_1/src/print.c b/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v7_1/src/print.c
new file mode 100644
index 0000000..da7e768
--- /dev/null
+++ b/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v7_1/src/print.c
@@ -0,0 +1,36 @@
+/* print.c -- print a string on the output device.
+ *
+ * Copyright (c) 1995 Cygnus Support
+ *
+ * The authors hereby grant permission to use, copy, modify, distribute,
+ * and license this software and its documentation for any purpose, provided
+ * that existing copyright notices are retained in all copies and that this
+ * notice is included verbatim in any distributions. No written agreement,
+ * license, or royalty fee is required for any of the authorized uses.
+ * Modifications to this software may be copyrighted by their authors
+ * and need not follow the licensing terms described here, provided that
+ * the new terms are clearly indicated on the first page of each file where
+ * they apply.
+ *
+ */
+
+/*
+ * print -- do a raw print of a string
+ */
+#include "xil_printf.h"
+
+void print(const char8 *ptr)
+{
+#if HYP_GUEST && EL1_NONSECURE && XEN_USE_PV_CONSOLE
+ XPVXenConsole_Write(ptr);
+#else
+#ifdef STDOUT_BASEADDRESS
+ while (*ptr != (char8)0) {
+ outbyte (*ptr);
+ ptr++;
+ }
+#else
+(void)ptr;
+#endif
+#endif
+}
diff --git a/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v7_1/src/profile/Makefile b/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v7_1/src/profile/Makefile
new file mode 100644
index 0000000..0ca93b9
--- /dev/null
+++ b/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v7_1/src/profile/Makefile
@@ -0,0 +1,72 @@
+###############################################################################
+#
+# Copyright (C) 2002 - 2014 Xilinx, Inc. All rights reserved.
+#
+# Permission is hereby granted, free of charge, to any person obtaining a copy
+# of this software and associated documentation files (the "Software"), to deal
+# in the Software without restriction, including without limitation the rights
+# to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+# copies of the Software, and to permit persons to whom the Software is
+# furnished to do so, subject to the following conditions:
+#
+# The above copyright notice and this permission notice shall be included in
+# all copies or substantial portions of the Software.
+#
+# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+# THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+# LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+# OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+# THE SOFTWARE.
+#
+#
+#
+###############################################################################
+#
+# Makefile for profiler
+#
+#######################################################################
+
+# PROFILE_ARCH_OBJS - Processor Architecture Dependent files defined here
+include ../config.make
+
+AS=mb-as
+COMPILER = mb-gcc
+ARCHIVER = mb-ar
+CP = cp
+COMPILER_FLAGS=-O2
+EXTRA_COMPILER_FLAGS=
+LIB = libxil.a
+DUMMYLIB = libxilprofile.a
+
+CC_FLAGS = $(subst -pg, , $(COMPILER_FLAGS))
+ECC_FLAGS = $(subst -pg, , $(EXTRA_COMPILER_FLAGS))
+
+RELEASEDIR = ../../../../lib
+INCLUDEDIR = ../../../../include
+INCLUDES = -I./. -I${INCLUDEDIR}
+
+OBJS = _profile_init.o _profile_clean.o _profile_timer_hw.o profile_hist.o profile_cg.o
+DUMMYOBJ = dummy.o
+INCLUDEFILES = profile.h mblaze_nt_types.h _profile_timer_hw.h
+
+libs : reallibs dummylibs
+
+reallibs : $(OBJS) $(PROFILE_ARCH_OBJS)
+ $(ARCHIVER) -r $(RELEASEDIR)/$(LIB) $(OBJS) $(PROFILE_ARCH_OBJS)
+
+dummylibs : $(DUMMYOBJ)
+ $(ARCHIVER) -r $(RELEASEDIR)/$(DUMMYLIB) $(DUMMYOBJ)
+
+%.o:%.c
+ $(COMPILER) $(CC_FLAGS) $(ECC_FLAGS) -c $< -o $@ $(INCLUDES)
+
+%.o:%.S
+ $(COMPILER) $(CC_FLAGS) $(ECC_FLAGS) -c $< -o $@ $(INCLUDES)
+
+include:
+ $(CP) -rf $(INCLUDEFILES) $(INCLUDEDIR)
+
+clean:
+ rm -f $(OBJS) $(PROFILE_ARCH_OBJS) $(LIB)
diff --git a/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v7_1/src/profile/_profile_clean.c b/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v7_1/src/profile/_profile_clean.c
new file mode 100644
index 0000000..bd8f7ab
--- /dev/null
+++ b/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v7_1/src/profile/_profile_clean.c
@@ -0,0 +1,41 @@
+/******************************************************************************
+*
+* Copyright (C) 2002 - 2014 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+* THE SOFTWARE.
+*
+*
+*
+******************************************************************************/
+
+#include "profile.h"
+#include "_profile_timer_hw.h"
+#include "xil_exception.h"
+
+void _profile_clean( void );
+
+/*
+ * This function is the exit routine and is called by the crtinit, when the
+ * program terminates. The name needs to be changed later..
+ */
+void _profile_clean( void )
+{
+ Xil_ExceptionDisable();
+ disable_timer();
+}
diff --git a/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v7_1/src/profile/_profile_init.c b/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v7_1/src/profile/_profile_init.c
new file mode 100644
index 0000000..dba9ccf
--- /dev/null
+++ b/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v7_1/src/profile/_profile_init.c
@@ -0,0 +1,84 @@
+/******************************************************************************
+*
+* Copyright (C) 2002 - 2014 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+* THE SOFTWARE.
+*
+*
+*
+******************************************************************************
+*
+* _program_init.c:
+* Initialize the Profiling Structures.
+*
+******************************************************************************/
+
+#include "profile.h"
+
+/* XMD Initializes the following Global Variables Value during Program
+ * Download with appropriate values. */
+
+#ifdef PROC_MICROBLAZE
+
+extern s32 microblaze_init(void);
+
+#elif defined PROC_PPC
+
+extern s32 powerpc405_init(void);
+
+#else
+
+extern s32 cortexa9_init(void);
+
+#endif
+
+s32 profile_version = 1; /* Version of S/W Intrusive Profiling library */
+
+u32 binsize = (u32)BINSIZE; /* Histogram Bin Size */
+u32 cpu_clk_freq = (u32)CPU_FREQ_HZ ; /* CPU Clock Frequency */
+u32 sample_freq_hz = (u32)SAMPLE_FREQ_HZ ; /* Histogram Sampling Frequency */
+u32 timer_clk_ticks = (u32)TIMER_CLK_TICKS ;/* Timer Clock Ticks for the Timer */
+
+/* Structure for Storing the Profiling Data */
+struct gmonparam *_gmonparam = (struct gmonparam *)(0xffffffffU);
+s32 n_gmon_sections = 1;
+
+/* This is the initialization code, which is called from the crtinit. */
+
+void _profile_init( void )
+{
+/* print("Gmon Init called....\r\n") */
+/* putnum(n_gmon_sections) , print("\r\n") */
+/* if( _gmonparam == 0xffffffff ) */
+/* printf("Gmonparam is NULL !!\r\n") */
+/* for( i = 0, i < n_gmon_sections, i++ )[ */
+/* putnum( _gmonparam[i].lowpc) , print("\t") */
+/* putnum( _gmonparam[i].highpc) , print("\r\n") */
+/* putnum( _gmonparam[i].textsize ), print("\r\n") */
+/* putnum( _gmonparam[i].kcountsize * sizeof(unsigned short)), print("\r\n") */
+/* ] */
+
+#ifdef PROC_MICROBLAZE
+ (void)microblaze_init();
+#elif defined PROC_PPC
+ powerpc405_init();
+#else
+ (void)cortexa9_init();
+#endif
+}
diff --git a/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v7_1/src/profile/_profile_timer_hw.c b/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v7_1/src/profile/_profile_timer_hw.c
new file mode 100644
index 0000000..70417f2
--- /dev/null
+++ b/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v7_1/src/profile/_profile_timer_hw.c
@@ -0,0 +1,381 @@
+/******************************************************************************
+*
+* Copyright (C) 2004 - 2014 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+* THE SOFTWARE.
+*
+*
+*
+******************************************************************************
+*
+* _program_timer_hw.c:
+* Timer related functions
+*
+******************************************************************************/
+
+#include "profile.h"
+#include "_profile_timer_hw.h"
+
+#include "xil_exception.h"
+
+#ifdef PROC_PPC
+#include "xtime_l.h"
+#include "xpseudo_asm.h"
+#endif
+
+#ifdef TIMER_CONNECT_INTC
+#include "xintc_l.h"
+#include "xintc.h"
+#endif /* TIMER_CONNECT_INTC */
+
+/* #ifndef PPC_PIT_INTERRUPT */
+#if (!defined PPC_PIT_INTERRUPT && !defined PROC_CORTEXA9)
+#include "xtmrctr_l.h"
+#endif
+
+/* extern u32 timer_clk_ticks, */
+
+#ifdef PROC_PPC405
+#ifdef PPC_PIT_INTERRUPT
+s32 ppc_pit_init( void );
+#endif
+s32 powerpc405_init()
+#endif /* PROC_CORTEXA9 */
+
+#ifdef PROC_PPC440
+#ifdef PPC_PIT_INTERRUPT
+s32 ppc_dec_init( void );
+#endif
+s32 powerpc405_init(void);
+#endif /* PROC_PPC440 */
+
+#if (!defined PPC_PIT_INTERRUPT && !defined PROC_CORTEXA9)
+s32 opb_timer_init( void );
+#endif
+
+#ifdef PROC_MICROBLAZE
+s32 microblaze_init(void);
+#endif /* PROC_MICROBLAZE */
+
+#ifdef PROC_CORTEXA9
+s32 scu_timer_init( void );
+s32 cortexa9_init(void);
+#endif /* PROC_CORTEXA9 */
+
+
+/*--------------------------------------------------------------------
+ * PowerPC Target - Timer related functions
+ *-------------------------------------------------------------------- */
+#ifdef PROC_PPC405
+
+
+/*--------------------------------------------------------------------
+* PowerPC PIT Timer Init.
+* Defined only if PIT Timer is used for Profiling
+*
+*-------------------------------------------------------------------- */
+#ifdef PPC_PIT_INTERRUPT
+int ppc_pit_init( void )
+{
+ /* 1. Register Profile_intr_handler as Interrupt handler */
+ /* 2. Set PIT Timer Interrupt and Enable it. */
+ Xil_ExceptionRegisterHandler( XIL_EXCEPTION_ID_PIT_INT,
+ (Xil_ExceptionHandler)profile_intr_handler,NULL);
+ XTime_PITSetInterval( timer_clk_ticks ) ;
+ XTime_PITEnableAutoReload() ;
+ return 0;
+}
+#endif
+
+
+/* --------------------------------------------------------------------
+* PowerPC Timer Initialization functions.
+* For PowerPC, PIT and opb_timer can be used for Profiling. This
+* is selected by the user in standalone BSP
+*
+*-------------------------------------------------------------------- */
+s32 powerpc405_init()
+{
+ Xil_ExceptionInit() ;
+ Xil_ExceptionDisableMask( XIL_EXCEPTION_NON_CRITICAL ) ;
+
+ /* Initialize the Timer.
+ * 1. If PowerPC PIT Timer has to be used, initialize PIT timer.
+ * 2. Else use opb_timer. It can be directly connected or through intc to PowerPC */
+#ifdef PPC_PIT_INTERRUPT
+ ppc_pit_init();
+#else
+#ifdef TIMER_CONNECT_INTC
+ Xil_ExceptionRegisterHandler( XIL_EXCEPTION_ID_NON_CRITICAL_INT,
+ (Xil_ExceptionHandler)XIntc_DeviceInterruptHandler,NULL);
+ XIntc_RegisterHandler( INTC_BASEADDR, PROFILE_TIMER_INTR_ID,
+ (XInterruptHandler)profile_intr_handler,NULL);
+#else
+ Xil_ExceptionRegisterHandler( XIL_EXCEPTION_ID_NON_CRITICAL_INT,
+ (Xil_ExceptionHandler)profile_intr_handler,NULL);
+#endif
+ /* Initialize the timer with Timer Ticks */
+ opb_timer_init() ;
+#endif
+
+ /* Enable Interrupts in the System, if Profile Timer is the only Interrupt
+ * in the System. */
+#ifdef ENABLE_SYS_INTR
+#ifdef PPC_PIT_INTERRUPT
+ XTime_PITEnableInterrupt() ;
+#elif TIMER_CONNECT_INTC
+ XIntc_MasterEnable( INTC_BASEADDR );
+ XIntc_SetIntrSvcOption( INTC_BASEADDR, XIN_SVC_ALL_ISRS_OPTION);
+ XIntc_EnableIntr( INTC_BASEADDR, PROFILE_TIMER_INTR_MASK );
+#endif
+ Xil_ExceptionEnableMask( XIL_EXCEPTION_NON_CRITICAL ) ;
+#endif
+ return 0;
+}
+
+#endif /* PROC_PPC */
+
+
+
+/*--------------------------------------------------------------------
+ * PowerPC440 Target - Timer related functions
+ * -------------------------------------------------------------------- */
+#ifdef PROC_PPC440
+
+
+/*--------------------------------------------------------------------
+ * PowerPC DEC Timer Init.
+ * Defined only if DEC Timer is used for Profiling
+ *
+ *-------------------------------------------------------------------- */
+#ifdef PPC_PIT_INTERRUPT
+s32 ppc_dec_init( void )
+{
+ /* 1. Register Profile_intr_handler as Interrupt handler */
+ /* 2. Set DEC Timer Interrupt and Enable it. */
+ Xil_ExceptionRegisterHandler( XIL_EXCEPTION_ID_DEC_INT,
+ (Xil_ExceptionHandler)profile_intr_handler,NULL);
+ XTime_DECSetInterval( timer_clk_ticks ) ;
+ XTime_DECEnableAutoReload() ;
+ return 0;
+}
+#endif
+
+
+/*--------------------------------------------------------------------
+ * PowerPC Timer Initialization functions.
+ * For PowerPC, DEC and opb_timer can be used for Profiling. This
+ * is selected by the user in standalone BSP
+ *
+ *-------------------------------------------------------------------- */
+s32 powerpc405_init(void)
+{
+ Xil_ExceptionInit();
+ Xil_ExceptionDisableMask( XIL_EXCEPTION_NON_CRITICAL ) ;
+
+ /* Initialize the Timer.
+ * 1. If PowerPC DEC Timer has to be used, initialize DEC timer.
+ * 2. Else use opb_timer. It can be directly connected or through intc to PowerPC */
+#ifdef PPC_PIT_INTERRUPT
+ ppc_dec_init();
+#else
+#ifdef TIMER_CONNECT_INTC
+ Xil_ExceptionRegisterHandler(XIL_EXCEPTION_ID_NON_CRITICAL_INT,
+ (Xil_ExceptionHandler)XIntc_DeviceInterruptHandler,NULL);
+
+ XIntc_RegisterHandler( INTC_BASEADDR, PROFILE_TIMER_INTR_ID,
+ (XInterruptHandler)profile_intr_handler,NULL);
+#else
+ Xil_ExceptionRegisterHandler( XIL_EXCEPTION_ID_NON_CRITICAL_INT,
+ (Xil_ExceptionHandler)profile_intr_handler,NULL);
+ Xil_ExceptionRegisterHandler( XIL_EXCEPTION_ID_NON_CRITICAL_INT,
+ (Xil_ExceptionHandler)profile_intr_handler,NULL);
+#endif
+ /* Initialize the timer with Timer Ticks */
+ opb_timer_init() ;
+#endif
+
+ /* Enable Interrupts in the System, if Profile Timer is the only Interrupt
+ * in the System. */
+#ifdef ENABLE_SYS_INTR
+#ifdef PPC_PIT_INTERRUPT
+ XTime_DECEnableInterrupt() ;
+#elif TIMER_CONNECT_INTC
+ XIntc_MasterEnable( INTC_BASEADDR );
+ XIntc_SetIntrSvcOption( INTC_BASEADDR, XIN_SVC_ALL_ISRS_OPTION);
+ XIntc_EnableIntr( INTC_BASEADDR, PROFILE_TIMER_INTR_MASK );
+#endif
+ Xil_ExceptionEnableMask( XEXC_NON_CRITICAL ) ;
+#endif
+ return 0;
+}
+
+#endif /* PROC_PPC440 */
+
+/* --------------------------------------------------------------------
+ * opb_timer Initialization for PowerPC and MicroBlaze. This function
+ * is not needed if DEC timer is used in PowerPC
+ *
+ *-------------------------------------------------------------------- */
+/* #ifndef PPC_PIT_INTERRUPT */
+#if (!defined PPC_PIT_INTERRUPT && !defined PROC_CORTEXA9)
+s32 opb_timer_init( void )
+{
+ /* set the number of cycles the timer counts before interrupting */
+ XTmrCtr_SetLoadReg((u32)PROFILE_TIMER_BASEADDR, (u16)0, (u32)timer_clk_ticks);
+
+ /* reset the timers, and clear interrupts */
+ XTmrCtr_SetControlStatusReg((u32)PROFILE_TIMER_BASEADDR, (u16)0,
+ (u32)XTC_CSR_INT_OCCURED_MASK | (u32)XTC_CSR_LOAD_MASK );
+
+ /* start the timers */
+ XTmrCtr_SetControlStatusReg((u32)PROFILE_TIMER_BASEADDR, (u16)0, (u32)XTC_CSR_ENABLE_TMR_MASK
+ | (u32)XTC_CSR_ENABLE_INT_MASK | (u32)XTC_CSR_AUTO_RELOAD_MASK | (u32)XTC_CSR_DOWN_COUNT_MASK);
+ return 0;
+}
+#endif
+
+
+/*--------------------------------------------------------------------
+ * MicroBlaze Target - Timer related functions
+ *-------------------------------------------------------------------- */
+#ifdef PROC_MICROBLAZE
+
+/* --------------------------------------------------------------------
+ * Initialize the Profile Timer for MicroBlaze Target.
+ * For MicroBlaze, opb_timer is used. The opb_timer can be directly
+ * connected to MicroBlaze or connected through Interrupt Controller.
+ *
+ *-------------------------------------------------------------------- */
+s32 microblaze_init(void)
+{
+ /* Register profile_intr_handler
+ * 1. If timer is connected to Interrupt Controller, register the handler
+ * to Interrupt Controllers vector table.
+ * 2. If timer is directly connected to MicroBlaze, register the handler
+ * as Interrupt handler */
+ Xil_ExceptionInit();
+
+#ifdef TIMER_CONNECT_INTC
+ XIntc_RegisterHandler( INTC_BASEADDR, PROFILE_TIMER_INTR_ID,
+ (XInterruptHandler)profile_intr_handler,NULL);
+#else
+ Xil_ExceptionRegisterHandler(XIL_EXCEPTION_ID_INT,
+ (Xil_ExceptionHandler)profile_intr_handler,
+ NULL) ;
+#endif
+
+ /* Initialize the timer with Timer Ticks */
+ (void)opb_timer_init() ;
+
+ /* Enable Interrupts in the System, if Profile Timer is the only Interrupt
+ * in the System. */
+#ifdef ENABLE_SYS_INTR
+#ifdef TIMER_CONNECT_INTC
+ XIntc_MasterEnable((u32)INTC_BASEADDR );
+ XIntc_SetIntrSvcOption( INTC_BASEADDR, XIN_SVC_ALL_ISRS_OPTION);
+ XIntc_EnableIntr( (u32)INTC_BASEADDR, PROFILE_TIMER_INTR_MASK );
+ Xil_ExceptionRegisterHandler(XIL_EXCEPTION_ID_INT,
+ (Xil_ExceptionHandler)XIntc_DeviceInterruptHandler,NULL);
+#endif
+
+#endif
+
+ Xil_ExceptionEnable();
+
+ return 0;
+
+}
+
+#endif /* PROC_MICROBLAZE */
+
+
+
+/* --------------------------------------------------------------------
+ * Cortex A9 Target - Timer related functions
+ *-------------------------------------------------------------------- */
+#ifdef PROC_CORTEXA9
+
+/* --------------------------------------------------------------------
+ * Initialize the Profile Timer for Cortex A9 Target.
+ * The scu private timer is connected to the Scu GIC controller.
+ *
+ *-------------------------------------------------------------------- */
+s32 scu_timer_init( void )
+{
+ /* set the number of cycles the timer counts before interrupting
+ * scu timer runs at half the cpu clock */
+ XScuTimer_SetLoadReg(PROFILE_TIMER_BASEADDR, timer_clk_ticks/2U);
+
+ /* clear any pending interrupts */
+ XScuTimer_SetIntrReg(PROFILE_TIMER_BASEADDR, 1U);
+
+ /* enable interrupts, auto-reload mode and start the timer */
+ XScuTimer_SetControlReg(PROFILE_TIMER_BASEADDR, XSCUTIMER_CONTROL_IRQ_ENABLE_MASK |
+ XSCUTIMER_CONTROL_AUTO_RELOAD_MASK | XSCUTIMER_CONTROL_ENABLE_MASK);
+
+ return 0;
+}
+
+s32 cortexa9_init(void)
+{
+
+ Xil_ExceptionInit();
+
+ XScuGic_DeviceInitialize(0);
+
+ /*
+ * Connect the interrupt controller interrupt handler to the hardware
+ * interrupt handling logic in the processor.
+ */
+ Xil_ExceptionRegisterHandler(XIL_EXCEPTION_ID_IRQ_INT,
+ (Xil_ExceptionHandler)XScuGic_DeviceInterruptHandler,
+ NULL);
+
+ /*
+ * Connect the device driver handler that will be called when an
+ * interrupt for the device occurs, the handler defined above performs
+ * the specific interrupt processing for the device.
+ */
+ XScuGic_RegisterHandler(SCUGIC_CPU_BASEADDR,
+ PROFILE_TIMER_INTR_ID,
+ (Xil_ExceptionHandler)profile_intr_handler,
+ NULL);
+
+ /*
+ * Enable the interrupt for scu timer.
+ */
+ XScuGic_EnableIntr(SCUGIC_DIST_BASEADDR, PROFILE_TIMER_INTR_ID);
+
+ /*
+ * Enable interrupts in the Processor.
+ */
+ Xil_ExceptionEnableMask(XIL_EXCEPTION_IRQ);
+
+ /*
+ * Initialize the timer with Timer Ticks
+ */
+ (void)scu_timer_init() ;
+
+ Xil_ExceptionEnable();
+
+ return 0;
+}
+
+#endif /* PROC_CORTEXA9 */
diff --git a/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v7_1/src/profile/_profile_timer_hw.h b/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v7_1/src/profile/_profile_timer_hw.h
new file mode 100644
index 0000000..01e2b50
--- /dev/null
+++ b/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v7_1/src/profile/_profile_timer_hw.h
@@ -0,0 +1,306 @@
+/******************************************************************************
+*
+* Copyright (C) 2004 - 2014 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+* THE SOFTWARE.
+*
+*
+*
+******************************************************************************
+*
+* _program_timer_hw.h:
+* Timer related functions
+*
+******************************************************************************/
+
+#ifndef PROFILE_TIMER_HW_H
+#define PROFILE_TIMER_HW_H
+
+#include "profile.h"
+
+#ifdef PROC_PPC
+#if defined __GNUC__
+# define SYNCHRONIZE_IO __asm__ volatile ("eieio")
+#elif defined __DCC__
+# define SYNCHRONIZE_IO __asm volatile(" eieio")
+#else
+# define SYNCHRONIZE_IO
+#endif
+#endif
+
+#ifdef PROC_PPC
+#define ProfIo_In32(InputPtr) { (*(volatile u32 *)(InputPtr)); SYNCHRONIZE_IO; }
+#define ProfIo_Out32(OutputPtr, Value) { (*(volatile u32 *)(OutputPtr) = Value); SYNCHRONIZE_IO; }
+#else
+#define ProfIo_In32(InputPtr) (*(volatile u32 *)(InputPtr));
+#define ProfIo_Out32(OutputPtr, Value) { (*(volatile u32 *)(OutputPtr) = (Value)); }
+#endif
+
+#define ProfTmrCtr_mWriteReg(BaseAddress, TmrCtrNumber, RegOffset, ValueToWrite)\
+ ProfIo_Out32(((u32)(BaseAddress) + (u32)XTmrCtr_Offsets[(TmrCtrNumber)] + \
+ (u32)(RegOffset)), (u32)(ValueToWrite))
+
+#define ProfTimerCtr_mReadReg(BaseAddress, TmrCtrNumber, RegOffset) \
+ ProfIo_In32((u32)(BaseAddress) + (u32)XTmrCtr_Offsets[(TmrCtrNumber)] + (u32)(RegOffset))
+
+#define ProfTmrCtr_mSetControlStatusReg(BaseAddress, TmrCtrNumber, RegisterValue)\
+ ProfTmrCtr_mWriteReg((BaseAddress), (TmrCtrNumber), XTC_TCSR_OFFSET, \
+ (RegisterValue))
+
+#define ProfTmrCtr_mGetControlStatusReg(BaseAddress, TmrCtrNumber) \
+ ProfTimerCtr_mReadReg((u32)(BaseAddress), (TmrCtrNumber), XTC_TCSR_OFFSET)
+
+
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#ifdef PROC_PPC
+#include "xexception_l.h"
+#include "xtime_l.h"
+#include "xpseudo_asm.h"
+#endif
+
+#ifdef TIMER_CONNECT_INTC
+#include "xintc_l.h"
+#include "xintc.h"
+#endif /* TIMER_CONNECT_INTC */
+
+#if (!defined PPC_PIT_INTERRUPT && !defined PROC_CORTEXA9)
+#include "xtmrctr_l.h"
+#endif
+
+#ifdef PROC_CORTEXA9
+#include "xscutimer_hw.h"
+#include "xscugic.h"
+#endif
+
+extern u32 timer_clk_ticks ;
+
+/*--------------------------------------------------------------------
+ * PowerPC Target - Timer related functions
+ *-------------------------------------------------------------------- */
+#ifdef PROC_PPC
+
+#ifdef PPC_PIT_INTERRUPT
+u32 timer_lo_clk_ticks ; /* Clk ticks when Timer is disabled in CG */
+#endif
+
+#ifdef PROC_PPC440
+#define XREG_TCR_PIT_INTERRUPT_ENABLE XREG_TCR_DEC_INTERRUPT_ENABLE
+#define XREG_TSR_PIT_INTERRUPT_STATUS XREG_TSR_DEC_INTERRUPT_STATUS
+#define XREG_SPR_PIT XREG_SPR_DEC
+#define XEXC_ID_PIT_INT XEXC_ID_DEC_INT
+#endif
+
+/* --------------------------------------------------------------------
+ * Disable the Timer - During Profiling
+ *
+ * For PIT Timer -
+ * 1. XTime_PITDisableInterrupt() ;
+ * 2. Store the remaining timer clk tick
+ * 3. Stop the PIT Timer
+ *-------------------------------------------------------------------- */
+
+#ifdef PPC_PIT_INTERRUPT
+#define disable_timer() \
+ { \
+ u32 val; \
+ val=mfspr(XREG_SPR_TCR); \
+ mtspr(XREG_SPR_TCR, val & (~XREG_TCR_PIT_INTERRUPT_ENABLE)); \
+ timer_lo_clk_ticks = mfspr(XREG_SPR_PIT); \
+ mtspr(XREG_SPR_PIT, 0); \
+ }
+#else
+#define disable_timer() \
+ { \
+ u32 addr = (PROFILE_TIMER_BASEADDR) + XTmrCtr_Offsets[(0)] + XTC_TCSR_OFFSET; \
+ u32 tmp_v = ProfIo_In32(addr); \
+ tmp_v = tmp_v & (~XTC_CSR_ENABLE_TMR_MASK); \
+ ProfIo_Out32((PROFILE_TIMER_BASEADDR) + XTmrCtr_Offsets[(0)] + XTC_TCSR_OFFSET, tmp_v); \
+ }
+#endif
+
+
+
+/* --------------------------------------------------------------------
+ * Enable the Timer
+ *
+ * For PIT Timer -
+ * 1. Load the remaining timer clk ticks
+ * 2. XTime_PITEnableInterrupt() ;
+ *-------------------------------------------------------------------- */
+#ifdef PPC_PIT_INTERRUPT
+#define enable_timer() \
+ { \
+ u32 val; \
+ val=mfspr(XREG_SPR_TCR); \
+ mtspr(XREG_SPR_PIT, timer_lo_clk_ticks); \
+ mtspr(XREG_SPR_TCR, val | XREG_TCR_PIT_INTERRUPT_ENABLE); \
+ }
+#else
+#define enable_timer() \
+ { \
+ u32 addr = (PROFILE_TIMER_BASEADDR) + XTmrCtr_Offsets[(0)] + XTC_TCSR_OFFSET; \
+ u32 tmp_v = ProfIo_In32(addr); \
+ tmp_v = tmp_v | XTC_CSR_ENABLE_TMR_MASK; \
+ ProfIo_Out32((PROFILE_TIMER_BASEADDR) + XTmrCtr_Offsets[(0)] + XTC_TCSR_OFFSET, tmp_v); \
+ }
+#endif
+
+
+
+/* --------------------------------------------------------------------
+ * Send Ack to Timer Interrupt
+ *
+ * For PIT Timer -
+ * 1. Load the timer clk ticks
+ * 2. Enable AutoReload and Interrupt
+ * 3. Clear PIT Timer Status bits
+ *-------------------------------------------------------------------- */
+#ifdef PPC_PIT_INTERRUPT
+#define timer_ack() \
+ { \
+ u32 val; \
+ mtspr(XREG_SPR_PIT, timer_clk_ticks); \
+ mtspr(XREG_SPR_TSR, XREG_TSR_PIT_INTERRUPT_STATUS); \
+ val=mfspr(XREG_SPR_TCR); \
+ mtspr(XREG_SPR_TCR, val| XREG_TCR_PIT_INTERRUPT_ENABLE| XREG_TCR_AUTORELOAD_ENABLE); \
+ }
+#else
+#define timer_ack() \
+ { \
+ u32 csr; \
+ csr = ProfTmrCtr_mGetControlStatusReg(PROFILE_TIMER_BASEADDR, 0); \
+ ProfTmrCtr_mSetControlStatusReg(PROFILE_TIMER_BASEADDR, 0, csr); \
+ }
+#endif
+
+/*-------------------------------------------------------------------- */
+#endif /* PROC_PPC */
+/* -------------------------------------------------------------------- */
+
+
+
+
+/* --------------------------------------------------------------------
+ * MicroBlaze Target - Timer related functions
+ *-------------------------------------------------------------------- */
+#ifdef PROC_MICROBLAZE
+
+/* --------------------------------------------------------------------
+ * Disable the Timer during Call-Graph Data collection
+ *
+ *-------------------------------------------------------------------- */
+#define disable_timer() \
+ { \
+ u32 Addr = ((u32)PROFILE_TIMER_BASEADDR); \
+ Addr += (u32)XTmrCtr_Offsets[(u16)(0)]; \
+ Addr += (u32)XTC_TCSR_OFFSET; \
+ u32 tmp_v = ProfIo_In32(Addr); \
+ tmp_v = tmp_v & (u32)(~XTC_CSR_ENABLE_TMR_MASK); \
+ u32 OutAddr = (u32)PROFILE_TIMER_BASEADDR; \
+ OutAddr += (u32)XTmrCtr_Offsets[(u16)(0)]; \
+ OutAddr += (u32)XTC_TCSR_OFFSET; \
+ ProfIo_Out32(OutAddr, (u32)tmp_v); \
+ }
+
+
+/* --------------------------------------------------------------------
+ * Enable the Timer after Call-Graph Data collection
+ *
+ *-------------------------------------------------------------------- */
+#define enable_timer() \
+ { \
+ u32 Addr = ((u32)PROFILE_TIMER_BASEADDR); \
+ Addr += (u32)XTmrCtr_Offsets[(u16)(0)]; \
+ Addr += (u32)XTC_TCSR_OFFSET; \
+ u32 tmp_v = (u32)ProfIo_In32(Addr); \
+ tmp_v = tmp_v | (u32)XTC_CSR_ENABLE_TMR_MASK; \
+ ProfIo_Out32((u32)(PROFILE_TIMER_BASEADDR) + (u32)XTmrCtr_Offsets[(u16)(0)] + (u32)XTC_TCSR_OFFSET, (u32)tmp_v); \
+ }
+
+
+/* --------------------------------------------------------------------
+ * Send Ack to Timer Interrupt
+ *
+ *-------------------------------------------------------------------- */
+#define timer_ack() \
+ { \
+ u32 csr; \
+ csr = ProfTmrCtr_mGetControlStatusReg((u32)PROFILE_TIMER_BASEADDR, (u16)0); \
+ ProfTmrCtr_mSetControlStatusReg((u32)PROFILE_TIMER_BASEADDR, (u16)0, (u32)csr); \
+ }
+
+/*-------------------------------------------------------------------- */
+#endif /* PROC_MICROBLAZE */
+/*-------------------------------------------------------------------- */
+
+/* --------------------------------------------------------------------
+ * Cortex A9 Target - Timer related functions
+ *-------------------------------------------------------------------- */
+#ifdef PROC_CORTEXA9
+
+/* --------------------------------------------------------------------
+ * Disable the Timer during Call-Graph Data collection
+ *
+ *-------------------------------------------------------------------- */
+#define disable_timer() \
+{ \
+ u32 Reg; \
+ Reg = Xil_In32(PROFILE_TIMER_BASEADDR + XSCUTIMER_CONTROL_OFFSET); \
+ Reg &= (~XSCUTIMER_CONTROL_ENABLE_MASK);\
+ Xil_Out32(PROFILE_TIMER_BASEADDR + XSCUTIMER_CONTROL_OFFSET, Reg);\
+}
+
+
+/* --------------------------------------------------------------------
+ * Enable the Timer after Call-Graph Data collection
+ *
+ *-------------------------------------------------------------------- */
+#define enable_timer() \
+{ \
+ u32 Reg; \
+ Reg = Xil_In32(PROFILE_TIMER_BASEADDR + XSCUTIMER_CONTROL_OFFSET); \
+ Reg |= XSCUTIMER_CONTROL_ENABLE_MASK; \
+ Xil_Out32(PROFILE_TIMER_BASEADDR + XSCUTIMER_CONTROL_OFFSET, Reg);\
+}
+
+
+/* --------------------------------------------------------------------
+ * Send Ack to Timer Interrupt
+ *
+ *-------------------------------------------------------------------- */
+#define timer_ack() \
+{ \
+ Xil_Out32((u32)PROFILE_TIMER_BASEADDR + (u32)XSCUTIMER_ISR_OFFSET, \
+ (u32)XSCUTIMER_ISR_EVENT_FLAG_MASK);\
+}
+
+/*-------------------------------------------------------------------- */
+#endif /* PROC_CORTEXA9 */
+/*-------------------------------------------------------------------- */
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff --git a/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v7_1/src/profile/dummy.S b/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v7_1/src/profile/dummy.S
new file mode 100644
index 0000000..1a0432c
--- /dev/null
+++ b/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v7_1/src/profile/dummy.S
@@ -0,0 +1,58 @@
+/******************************************************************************
+*
+* Copyright (C) 2002 - 2014 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+* THE SOFTWARE.
+*
+*
+*
+******************************************************************************/
+
+ .globl dummy_f
+
+#ifdef PROC_MICROBLAZE
+ .text
+ .align 2
+ .ent dummy_f
+
+dummy_f:
+ nop
+
+ .end dummy_f
+#endif
+
+#ifdef PROC_PPC
+ .section .text
+ .align 2
+ .type dummy_f@function
+
+dummy_f:
+ b dummy_f
+
+#endif
+
+#ifdef PROC_CORTEXA9
+ .section .text
+ .align 2
+ .type dummy_f, %function
+
+dummy_f:
+ b dummy_f
+
+#endif
diff --git a/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v7_1/src/profile/mblaze_nt_types.h b/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v7_1/src/profile/mblaze_nt_types.h
new file mode 100644
index 0000000..b6cfb84
--- /dev/null
+++ b/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v7_1/src/profile/mblaze_nt_types.h
@@ -0,0 +1,48 @@
+/******************************************************************************
+*
+* Copyright (C) 2002 - 2014 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+* THE SOFTWARE.
+*
+*
+*
+******************************************************************************/
+
+
+#ifndef _MBLAZE_NT_TYPES_H
+#define _MBLAZE_NT_TYPES_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+typedef char byte;
+typedef short half;
+typedef int word;
+typedef unsigned char ubyte;
+typedef unsigned short uhalf;
+typedef unsigned int uword;
+typedef ubyte boolean;
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff --git a/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v7_1/src/profile/profile.h b/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v7_1/src/profile/profile.h
new file mode 100644
index 0000000..8b105c1
--- /dev/null
+++ b/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v7_1/src/profile/profile.h
@@ -0,0 +1,125 @@
+/******************************************************************************
+*
+* Copyright (C) 2002 - 2014 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+* THE SOFTWARE.
+*
+*
+*
+******************************************************************************/
+
+#ifndef PROFILE_H
+#define PROFILE_H 1
+
+#include <stdio.h>
+#include "xil_types.h"
+#include "profile_config.h"
+
+#ifdef PROC_MICROBLAZE
+#include "mblaze_nt_types.h"
+#endif
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+void _system_init( void ) ;
+void _system_clean( void ) ;
+void mcount(u32 frompc, u32 selfpc);
+void profile_intr_handler( void ) ;
+void _profile_init( void );
+
+
+
+/****************************************************************************
+ * Profiling on hardware - Hash table maintained on hardware and data sent
+ * to xmd for gmon.out generation.
+ ****************************************************************************/
+/*
+ * histogram counters are unsigned shorts (according to the kernel).
+ */
+#define HISTCOUNTER u16
+
+struct tostruct {
+ u32 selfpc;
+ s32 count;
+ s16 link;
+ u16 pad;
+};
+
+struct fromstruct {
+ u32 frompc ;
+ s16 link ;
+ u16 pad ;
+} ;
+
+/*
+ * general rounding functions.
+ */
+#define ROUNDDOWN(x,y) (((x)/(y))*(y))
+#define ROUNDUP(x,y) ((((x)+(y)-1)/(y))*(y))
+
+/*
+ * The profiling data structures are housed in this structure.
+ */
+struct gmonparam {
+ s32 state;
+
+ /* Histogram Information */
+ u16 *kcount; /* No. of bins in histogram */
+ u32 kcountsize; /* Histogram samples */
+
+ /* Call-graph Information */
+ struct fromstruct *froms;
+ u32 fromssize;
+ struct tostruct *tos;
+ u32 tossize;
+
+ /* Initialization I/Ps */
+ u32 lowpc;
+ u32 highpc;
+ u32 textsize;
+ /* u32 cg_froms, */
+ /* u32 cg_tos, */
+};
+extern struct gmonparam *_gmonparam;
+extern s32 n_gmon_sections;
+
+/*
+ * Possible states of profiling.
+ */
+#define GMON_PROF_ON 0
+#define GMON_PROF_BUSY 1
+#define GMON_PROF_ERROR 2
+#define GMON_PROF_OFF 3
+
+/*
+ * Sysctl definitions for extracting profiling information from the kernel.
+ */
+#define GPROF_STATE 0 /* int: profiling enabling variable */
+#define GPROF_COUNT 1 /* struct: profile tick count buffer */
+#define GPROF_FROMS 2 /* struct: from location hash bucket */
+#define GPROF_TOS 3 /* struct: destination/count structure */
+#define GPROF_GMONPARAM 4 /* struct: profiling parameters (see above) */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* PROFILE_H */
diff --git a/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v7_1/src/profile/profile_cg.c b/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v7_1/src/profile/profile_cg.c
new file mode 100644
index 0000000..e1442ca
--- /dev/null
+++ b/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v7_1/src/profile/profile_cg.c
@@ -0,0 +1,165 @@
+/******************************************************************************
+*
+* Copyright (C) 2002 - 2014 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+* THE SOFTWARE.
+*
+*
+*
+******************************************************************************/
+
+#include "profile.h"
+#include "_profile_timer_hw.h"
+#ifdef PROC_MICROBLAZE
+#include "mblaze_nt_types.h"
+#endif
+
+/*
+ * The mcount function is excluded from the library, if the user defines
+ * PROFILE_NO_GRAPH.
+ */
+#ifndef PROFILE_NO_GRAPH
+
+#include <stdio.h>
+#include <stdlib.h>
+#include <string.h>
+
+#ifdef PROFILE_NO_FUNCPTR
+s32 searchpc(const struct fromto_struct *cgtable, s32 cgtable_size, u32 frompc );
+#else
+s32 searchpc(const struct fromstruct *froms, s32 fromssize, u32 frompc );
+#endif
+
+/*extern struct gmonparam *_gmonparam, */
+
+#ifdef PROFILE_NO_FUNCPTR
+s32 searchpc(const struct fromto_struct *cgtable, s32 cgtable_size, u32 frompc )
+{
+ s32 index = 0 ;
+
+ while( (index < cgtable_size) && (cgtable[index].frompc != frompc) ){
+ index++ ;
+ }
+ if( index == cgtable_size ) {
+ return -1 ;
+ } else {
+ return index ;
+ }
+}
+#else
+s32 searchpc(const struct fromstruct *froms, s32 fromssize, u32 frompc )
+{
+ s32 index = 0 ;
+ s32 Status;
+
+ while( (index < fromssize) && (froms[index].frompc != frompc) ){
+ index++ ;
+ }
+ if( index == fromssize ) {
+ Status = -1 ;
+ } else {
+ Status = index ;
+ }
+ return Status;
+}
+#endif /* PROFILE_NO_FUNCPTR */
+
+
+void mcount( u32 frompc, u32 selfpc )
+{
+ register struct gmonparam *p = NULL;
+ register s32 toindex, fromindex;
+ s32 j;
+
+ disable_timer();
+
+ /*print("CG: "), putnum(frompc), print("->"), putnum(selfpc), print("\r\n") ,
+ * check that frompcindex is a reasonable pc value.
+ * for example: signal catchers get called from the stack,
+ * not from text space. too bad.
+ */
+ for(j = 0; j < n_gmon_sections; j++ ){
+ if((frompc >= _gmonparam[j].lowpc) && (frompc < _gmonparam[j].highpc)) {
+ p = &_gmonparam[j];
+ break;
+ }
+ }
+ if( j == n_gmon_sections ) {
+ goto done;
+ }
+
+#ifdef PROFILE_NO_FUNCPTR
+ fromindex = searchpc( p->cgtable, p->cgtable_size, frompc ) ;
+ if( fromindex == -1 ) {
+ fromindex = p->cgtable_size ;
+ p->cgtable_size++ ;
+ p->cgtable[fromindex].frompc = frompc ;
+ p->cgtable[fromindex].selfpc = selfpc ;
+ p->cgtable[fromindex].count = 1 ;
+ goto done ;
+ }
+ p->cgtable[fromindex].count++ ;
+#else
+ fromindex = (s32)searchpc( p->froms, ((s32)p->fromssize), frompc ) ;
+ if( fromindex == -1 ) {
+ fromindex = (s32)p->fromssize ;
+ p->fromssize++ ;
+ /*if( fromindex >= N_FROMS ) {
+ * print("Error : From PC table overflow\r\n")
+ * goto overflow
+ *}*/
+ p->froms[fromindex].frompc = frompc ;
+ p->froms[fromindex].link = -1 ;
+ }else {
+ toindex = ((s32)(p->froms[fromindex].link));
+ while(toindex != -1) {
+ toindex = (((s32)p->tossize) - toindex)-1 ;
+ if( p->tos[toindex].selfpc == selfpc ) {
+ p->tos[toindex].count++ ;
+ goto done ;
+ }
+ toindex = ((s32)(p->tos[toindex].link)) ;
+ }
+ }
+
+ /*if( toindex == -1 ) { */
+ p->tos-- ;
+ p->tossize++ ;
+ /* if( toindex >= N_TOS ) {
+ * print("Error : To PC table overflow\r\n")
+ * goto overflow
+ *} */
+ p->tos[0].selfpc = selfpc ;
+ p->tos[0].count = 1 ;
+ p->tos[0].link = p->froms[fromindex].link ;
+ p->froms[fromindex].link = ((s32)(p->tossize))-((s32)1);
+#endif
+
+ done:
+ p->state = GMON_PROF_ON;
+ goto enable_timer_label ;
+ /* overflow: */
+ /*p->state = GMON_PROF_ERROR */
+ enable_timer_label:
+ enable_timer();
+ return ;
+}
+
+
+#endif /* PROFILE_NO_GRAPH */
diff --git a/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v7_1/src/profile/profile_config.h b/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v7_1/src/profile/profile_config.h
new file mode 100644
index 0000000..0ef80c7
--- /dev/null
+++ b/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v7_1/src/profile/profile_config.h
@@ -0,0 +1,50 @@
+/******************************************************************************
+*
+* Copyright (C) 2002 - 2014 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+* THE SOFTWARE.
+*
+*
+*
+******************************************************************************/
+
+
+#ifndef _PROFILE_CONFIG_H
+#define _PROFILE_CONFIG_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#define BINSIZE 4U
+#define SAMPLE_FREQ_HZ 100000U
+#define TIMER_CLK_TICKS 1000U
+
+#define PROFILE_NO_FUNCPTR_FLAG 0
+
+#define PROFILE_TIMER_BASEADDR 0x00608000U
+#define PROFILE_TIMER_INTR_ID 0U
+
+#define TIMER_CONNECT_INTC
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff --git a/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v7_1/src/profile/profile_hist.c b/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v7_1/src/profile/profile_hist.c
new file mode 100644
index 0000000..73085e8
--- /dev/null
+++ b/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v7_1/src/profile/profile_hist.c
@@ -0,0 +1,65 @@
+/******************************************************************************
+*
+* Copyright (C) 2002 - 2014 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+* THE SOFTWARE.
+*
+*
+*
+******************************************************************************/
+
+#include "profile.h"
+#include "_profile_timer_hw.h"
+
+#ifdef PROC_MICROBLAZE
+#include "mblaze_nt_types.h"
+#endif
+
+#ifdef PROC_PPC
+#include "xpseudo_asm.h"
+#define SPR_SRR0 0x01A
+#endif
+
+#include "xil_types.h"
+
+extern u32 binsize ;
+u32 prof_pc ;
+
+void profile_intr_handler( void )
+{
+
+ s32 j;
+
+#ifdef PROC_MICROBLAZE
+ asm( "swi r14, r0, prof_pc" ) ;
+#elif defined PROC_PPC
+ prof_pc = mfspr(SPR_SRR0);
+#else
+ /* for cortexa9, lr is saved in asm interrupt handler */
+#endif
+ /* print("PC: "), putnum(prof_pc), print("\r\n"), */
+ for(j = 0; j < n_gmon_sections; j++ ){
+ if((prof_pc >= ((u32)_gmonparam[j].lowpc)) && (prof_pc < ((u32)_gmonparam[j].highpc))) {
+ _gmonparam[j].kcount[(prof_pc-_gmonparam[j].lowpc)/((u32)4 * binsize)]++;
+ break;
+ }
+ }
+ /* Ack the Timer Interrupt */
+ timer_ack();
+}
diff --git a/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v7_1/src/profile/profile_mcount_arm.S b/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v7_1/src/profile/profile_mcount_arm.S
new file mode 100644
index 0000000..660cd6c
--- /dev/null
+++ b/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v7_1/src/profile/profile_mcount_arm.S
@@ -0,0 +1,39 @@
+/******************************************************************************
+*
+* Copyright (C) 2002 - 2014 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+* THE SOFTWARE.
+*
+*
+*
+******************************************************************************/
+// based on "ARM Profiling Implementation" from Sourcery G++ Lite for ARM EABI
+
+.globl __gnu_mcount_nc
+.type __gnu_mcount_nc, %function
+
+__gnu_mcount_nc:
+ push {r0, r1, r2, r3, lr}
+ subs r1, lr, #0 /* callee - current lr */
+ ldr r0, [sp, #20] /* caller - at the top of the stack */
+ bl mcount /* when __gnu_mcount_nc is called */
+ pop {r0, r1, r2, r3, ip, lr}
+ bx ip
+
+ .end __gnu_mcount_nc
diff --git a/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v7_1/src/profile/profile_mcount_mb.S b/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v7_1/src/profile/profile_mcount_mb.S
new file mode 100644
index 0000000..7ca7e6b
--- /dev/null
+++ b/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v7_1/src/profile/profile_mcount_mb.S
@@ -0,0 +1,63 @@
+/******************************************************************************
+*
+* Copyright (C) 2002 - 2014 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+* THE SOFTWARE.
+*
+*
+*
+******************************************************************************/
+
+ .globl _mcount
+ .text
+ .align 2
+ .ent _mcount
+
+ #ifndef PROFILE_NO_GRAPH
+
+_mcount:
+ addi r1, r1, -48
+ swi r11, r1, 44
+ swi r12, r1, 40
+ swi r5, r1, 36
+ swi r6, r1, 32
+ swi r7, r1, 28
+ swi r8, r1, 24
+ swi r9, r1, 20
+ swi r10, r1, 16
+ swi r15, r1, 12
+ add r5, r0, r15
+ brlid r15, mcount
+ add r6, r0, r16
+
+ lwi r11, r1, 44
+ lwi r12, r1, 40
+ lwi r5, r1, 36
+ lwi r6, r1, 32
+ lwi r7, r1, 28
+ lwi r8, r1, 24
+ lwi r9, r1, 20
+ lwi r10, r1, 16
+ lwi r15, r1, 12
+ rtsd r15, 4
+ addi r1, r1, 48
+
+ #endif /* PROFILE_NO_GRAPH */
+
+ .end _mcount
diff --git a/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v7_1/src/profile/profile_mcount_ppc.S b/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v7_1/src/profile/profile_mcount_ppc.S
new file mode 100644
index 0000000..f522a0c
--- /dev/null
+++ b/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v7_1/src/profile/profile_mcount_ppc.S
@@ -0,0 +1,65 @@
+/******************************************************************************
+*
+* Copyright (C) 2002 - 2014 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+* THE SOFTWARE.
+*
+*
+*
+******************************************************************************/
+
+ .globl _mcount
+
+ #define _MCOUNT_STACK_FRAME 48
+ .section .text
+ .align 2
+ .type _mcount@function
+
+
+_mcount:
+ stwu 1, -_MCOUNT_STACK_FRAME(1)
+ stw 3, 8(1)
+ stw 4, 12(1)
+ stw 5, 16(1)
+ stw 6, 20(1)
+ stw 7, 24(1)
+ stw 8, 28(1)
+ stw 9, 32(1)
+ stw 10, 36(1)
+ stw 11, 40(1)
+ stw 12, 44(1)
+ mflr 4
+ stw 4, (_MCOUNT_STACK_FRAME+4)(1)
+ lwz 3, (_MCOUNT_STACK_FRAME)(1)
+ lwz 3, 4(3)
+ bl mcount
+ lwz 4, (_MCOUNT_STACK_FRAME+4)(1)
+ mtlr 4
+ lwz 12, 44(1)
+ lwz 11, 40(1)
+ lwz 10, 36(1)
+ lwz 9, 32(1)
+ lwz 8, 28(1)
+ lwz 7, 24(1)
+ lwz 6, 20(1)
+ lwz 5, 16(1)
+ lwz 4, 12(1)
+ lwz 3, 8(1)
+ addi 1,1, _MCOUNT_STACK_FRAME
+ blr
diff --git a/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v7_1/src/putnum.c b/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v7_1/src/putnum.c
new file mode 100644
index 0000000..aaf9ede
--- /dev/null
+++ b/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v7_1/src/putnum.c
@@ -0,0 +1,59 @@
+/* putnum.c -- put a hex number on the output device.
+ *
+ * Copyright (c) 1995 Cygnus Support
+ *
+ * The authors hereby grant permission to use, copy, modify, distribute,
+ * and license this software and its documentation for any purpose, provided
+ * that existing copyright notices are retained in all copies and that this
+ * notice is included verbatim in any distributions. No written agreement,
+ * license, or royalty fee is required for any of the authorized uses.
+ * Modifications to this software may be copyrighted by their authors
+ * and need not follow the licensing terms described here, provided that
+ * the new terms are clearly indicated on the first page of each file where
+ * they apply.
+ */
+
+/*
+ * putnum -- print a 32 bit number in hex
+ */
+
+/***************************** Include Files *********************************/
+#include "xil_types.h"
+
+/************************** Function Prototypes ******************************/
+extern void print (const char8 *ptr);
+void putnum(u32 num);
+
+void putnum(u32 num)
+{
+ char8 buf[9];
+ s32 cnt;
+ s32 i;
+ char8 *ptr;
+ u32 digit;
+ for(i = 0; i<9; i++) {
+ buf[i] = '0';
+ }
+
+ ptr = buf;
+ for (cnt = 7 ; cnt >= 0 ; cnt--) {
+ digit = (num >> (cnt * 4U)) & 0x0000000fU;
+
+ if ((digit <= 9U) && (ptr != NULL)) {
+ digit += (u32)'0';
+ *ptr = ((char8) digit);
+ ptr += 1;
+ } else if (ptr != NULL) {
+ digit += ((u32)'a' - (u32)10);
+ *ptr = ((char8)digit);
+ ptr += 1;
+ } else {
+ /*Made for MisraC Compliance*/;
+ }
+ }
+
+ if(ptr != NULL) {
+ *ptr = (char8) 0;
+ }
+ print (buf);
+}
diff --git a/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v7_1/src/read.c b/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v7_1/src/read.c
new file mode 100644
index 0000000..90a49f2
--- /dev/null
+++ b/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v7_1/src/read.c
@@ -0,0 +1,98 @@
+/******************************************************************************
+*
+* Copyright (C) 2009 - 2015 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+* THE SOFTWARE.
+*
+*
+*
+******************************************************************************/
+
+/* read.c -- read bytes from a input device.
+ */
+#ifndef UNDEFINE_FILE_OPS
+#include "xil_printf.h"
+#include "xparameters.h"
+
+#ifdef __cplusplus
+extern "C" {
+ __attribute__((weak)) s32 _read (s32 fd, char8* buf, s32 nbytes);
+}
+#endif
+
+/*
+ * read -- read bytes from the serial port. Ignore fd, since
+ * we only have stdin.
+ */
+__attribute__((weak)) s32
+read (s32 fd, char8* buf, s32 nbytes)
+{
+#ifdef STDIN_BASEADDRESS
+ s32 i;
+ s32 numbytes = 0;
+ char8* LocalBuf = buf;
+
+ (void)fd;
+ if(LocalBuf != NULL) {
+ for (i = 0; i < nbytes; i++) {
+ numbytes++;
+ *(LocalBuf + i) = inbyte();
+ if ((*(LocalBuf + i) == '\n' )|| (*(LocalBuf + i) == '\r')) {
+ break;
+ }
+ }
+ }
+
+ return numbytes;
+#else
+ (void)fd;
+ (void)buf;
+ (void)nbytes;
+ return 0;
+#endif
+}
+
+__attribute__((weak)) s32
+_read (s32 fd, char8* buf, s32 nbytes)
+{
+#ifdef STDIN_BASEADDRESS
+ s32 i;
+ s32 numbytes = 0;
+ char8* LocalBuf = buf;
+
+ (void)fd;
+ if(LocalBuf != NULL) {
+ for (i = 0; i < nbytes; i++) {
+ numbytes++;
+ *(LocalBuf + i) = inbyte();
+ if ((*(LocalBuf + i) == '\n' )|| (*(LocalBuf + i) == '\r')) {
+ break;
+ }
+ }
+ }
+
+ return numbytes;
+#else
+ (void)fd;
+ (void)buf;
+ (void)nbytes;
+ return 0;
+#endif
+}
+#endif
diff --git a/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v7_1/src/sbrk.c b/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v7_1/src/sbrk.c
new file mode 100644
index 0000000..9abfd35
--- /dev/null
+++ b/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v7_1/src/sbrk.c
@@ -0,0 +1,55 @@
+/******************************************************************************
+*
+* Copyright (C) 2009 - 2015 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+* THE SOFTWARE.
+*
+*
+*
+******************************************************************************/
+
+#include <errno.h>
+#include "xil_types.h"
+#ifdef __cplusplus
+extern "C" {
+ __attribute__((weak)) char8 *sbrk (s32 nbytes);
+}
+#endif
+
+extern u8 _heap_start[];
+extern u8 _heap_end[];
+extern char8 HeapBase[];
+extern char8 HeapLimit[];
+
+
+
+__attribute__((weak)) char8 *sbrk (s32 nbytes)
+{
+ char8 *base;
+ static char8 *heap_ptr = HeapBase;
+
+ base = heap_ptr;
+ if((heap_ptr != NULL) && (heap_ptr + nbytes <= (char8 *)&HeapLimit + 1)) {
+ heap_ptr += nbytes;
+ return base;
+ } else {
+ errno = ENOMEM;
+ return ((char8 *)-1);
+ }
+}
diff --git a/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v7_1/src/sleep.c b/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v7_1/src/sleep.c
new file mode 100644
index 0000000..79bf1f6
--- /dev/null
+++ b/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v7_1/src/sleep.c
@@ -0,0 +1,86 @@
+/******************************************************************************
+*
+* Copyright (C) 2009 - 2017 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+* THE SOFTWARE.
+*
+*
+*
+******************************************************************************/
+/*****************************************************************************
+*
+* @file sleep.c
+*
+* This function provides a second delay using the Global Timer register in
+* the ARM Cortex A9 MP core.
+*
+* <pre>
+* MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ----- -------- -------- -----------------------------------------------
+* 1.00a ecm/sdm 11/11/09 First release
+* 3.07a sgd 07/05/12 Updated sleep function to make use Global
+* 6.0 asa 08/15/16 Updated the sleep signature. Fix for CR#956899.
+* 6.6 srm 10/18/17 Updated sleep routines to support user configurable
+* implementation. Now sleep routines will use Timer
+* specified by the user (i.e. Global timer/TTC timer)
+*
+* </pre>
+*
+******************************************************************************/
+/***************************** Include Files *********************************/
+
+#include "sleep.h"
+#include "xtime_l.h"
+#include "xparameters.h"
+
+#if defined (SLEEP_TIMER_BASEADDR)
+#include "xil_sleeptimer.h"
+#endif
+
+/*****************************************************************************/
+/*
+*
+* This API is used to provide delays in seconds
+*
+* @param seconds requested
+*
+* @return 0 always
+*
+* @note None.
+*
+****************************************************************************/
+unsigned sleep_A9(unsigned int seconds)
+{
+#if defined (SLEEP_TIMER_BASEADDR)
+ Xil_SleepTTCCommon(seconds, COUNTS_PER_SECOND);
+#else
+ XTime tEnd, tCur;
+
+ XTime_GetTime(&tCur);
+ tEnd = tCur + (((XTime) seconds) * COUNTS_PER_SECOND);
+ do
+ {
+ XTime_GetTime(&tCur);
+ } while (tCur < tEnd);
+#endif
+
+ return 0;
+}
diff --git a/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v7_1/src/sleep.h b/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v7_1/src/sleep.h
new file mode 100644
index 0000000..9245419
--- /dev/null
+++ b/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v7_1/src/sleep.h
@@ -0,0 +1,113 @@
+/******************************************************************************
+*
+* Copyright (C) 2014 - 2017 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+* THE SOFTWARE.
+*
+*
+*
+******************************************************************************/
+
+/*****************************************************************************/
+/**
+* @file sleep.h
+*
+* This header file contains ARM Cortex A53,A9,R5,Microblaze specific sleep
+* related APIs.
+*
+* <pre>
+* MODIFICATION HISTORY :
+*
+* Ver Who Date Changes
+* ----- ---- -------- -------------------------------------------------------
+* 6.6 srm 11/02/17 Added processor specific sleep routines
+* function prototypes.
+*
+* </pre>
+*
+******************************************************************************/
+
+#ifndef SLEEP_H
+#define SLEEP_H
+
+#include "xil_types.h"
+#include "xil_io.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*****************************************************************************/
+/**
+*
+* This macro polls an address periodically until a condition is met or till the
+* timeout occurs.
+* The minimum timeout for calling this macro is 100us. If the timeout is less
+* than 100us, it still waits for 100us. Also the unit for the timeout is 100us.
+* If the timeout is not a multiple of 100us, it waits for a timeout of
+* the next usec value which is a multiple of 100us.
+*
+* @param IO_func - accessor function to read the register contents.
+* Depends on the register width.
+* @param ADDR - Address to be polled
+* @param VALUE - variable to read the value
+* @param COND - Condition to checked (usually involves VALUE)
+* @param TIMEOUT_US - timeout in micro seconds
+*
+* @return 0 - when the condition is met
+* -1 - when the condition is not met till the timeout period
+*
+* @note none
+*
+*****************************************************************************/
+#define Xil_poll_timeout(IO_func, ADDR, VALUE, COND, TIMEOUT_US) \
+ ( { \
+ u64 timeout = TIMEOUT_US/100; \
+ if(TIMEOUT_US%100!=0) \
+ timeout++; \
+ for(;;) { \
+ VALUE = IO_func(ADDR); \
+ if(COND) \
+ break; \
+ else { \
+ usleep(100); \
+ timeout--; \
+ if(timeout==0) \
+ break; \
+ } \
+ } \
+ (timeout>0) ? 0 : -1; \
+ } )
+
+void usleep(unsigned long useconds);
+void sleep(unsigned int seconds);
+int usleep_R5(unsigned long useconds);
+unsigned sleep_R5(unsigned int seconds);
+int usleep_MB(unsigned long useconds);
+unsigned sleep_MB(unsigned int seconds);
+int usleep_A53(unsigned long useconds);
+unsigned sleep_A53(unsigned int seconds);
+int usleep_A9(unsigned long useconds);
+unsigned sleep_A9(unsigned int seconds);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff --git a/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v7_1/src/smc.h b/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v7_1/src/smc.h
new file mode 100644
index 0000000..94d4c0e
--- /dev/null
+++ b/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v7_1/src/smc.h
@@ -0,0 +1,108 @@
+/******************************************************************************
+*
+* Copyright (C) 2010 - 2015 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+* THE SOFTWARE.
+*
+*
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+* @file smc.h
+*
+* <pre>
+* MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ----- ---- -------- ---------------------------------------------------
+* 1.00a sdm 11/03/09 Initial release.
+* 4.2 pkp 08/04/14 Removed function definition of XSmc_NorInit and XSmc_NorInit
+* as smc.c is removed
+* </pre>
+*
+* @note None.
+*
+******************************************************************************/
+
+#ifndef SMC_H /* prevent circular inclusions */
+#define SMC_H /* by using protection macros */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/***************************** Include Files *********************************/
+
+#include "xparameters.h"
+#include "xil_io.h"
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/**************************** Type Definitions *******************************/
+
+/************************** Constant Definitions *****************************/
+
+/* Memory controller configuration register offset */
+#define XSMCPSS_MC_STATUS 0x000U /* Controller status reg, RO */
+#define XSMCPSS_MC_INTERFACE_CONFIG 0x004U /* Interface config reg, RO */
+#define XSMCPSS_MC_SET_CONFIG 0x008U /* Set configuration reg, WO */
+#define XSMCPSS_MC_CLR_CONFIG 0x00CU /* Clear config reg, WO */
+#define XSMCPSS_MC_DIRECT_CMD 0x010U /* Direct command reg, WO */
+#define XSMCPSS_MC_SET_CYCLES 0x014U /* Set cycles register, WO */
+#define XSMCPSS_MC_SET_OPMODE 0x018U /* Set opmode register, WO */
+#define XSMCPSS_MC_REFRESH_PERIOD_0 0x020U /* Refresh period_0 reg, RW */
+#define XSMCPSS_MC_REFRESH_PERIOD_1 0x024U /* Refresh period_1 reg, RW */
+
+/* Chip select configuration register offset */
+#define XSMCPSS_CS_IF0_CHIP_0_OFFSET 0x100U /* Interface 0 chip 0 config */
+#define XSMCPSS_CS_IF0_CHIP_1_OFFSET 0x120U /* Interface 0 chip 1 config */
+#define XSMCPSS_CS_IF0_CHIP_2_OFFSET 0x140U /* Interface 0 chip 2 config */
+#define XSMCPSS_CS_IF0_CHIP_3_OFFSET 0x160U /* Interface 0 chip 3 config */
+#define XSMCPSS_CS_IF1_CHIP_0_OFFSET 0x180U /* Interface 1 chip 0 config */
+#define XSMCPSS_CS_IF1_CHIP_1_OFFSET 0x1A0U /* Interface 1 chip 1 config */
+#define XSMCPSS_CS_IF1_CHIP_2_OFFSET 0x1C0U /* Interface 1 chip 2 config */
+#define XSMCPSS_CS_IF1_CHIP_3_OFFSET 0x1E0U /* Interface 1 chip 3 config */
+
+/* User configuration register offset */
+#define XSMCPSS_UC_STATUS_OFFSET 0x200U /* User status reg, RO */
+#define XSMCPSS_UC_CONFIG_OFFSET 0x204U /* User config reg, WO */
+
+/* Integration test register offset */
+#define XSMCPSS_IT_OFFSET 0xE00U
+
+/* ID configuration register offset */
+#define XSMCPSS_ID_PERIP_0_OFFSET 0xFE0U
+#define XSMCPSS_ID_PERIP_1_OFFSET 0xFE4U
+#define XSMCPSS_ID_PERIP_2_OFFSET 0xFE8U
+#define XSMCPSS_ID_PERIP_3_OFFSET 0xFECU
+#define XSMCPSS_ID_PCELL_0_OFFSET 0xFF0U
+#define XSMCPSS_ID_PCELL_1_OFFSET 0xFF4U
+#define XSMCPSS_ID_PCELL_2_OFFSET 0xFF8U
+#define XSMCPSS_ID_PCELL_3_OFFSET 0xFFCU
+
+/************************** Variable Definitions *****************************/
+
+/************************** Function Prototypes ******************************/
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+
+#endif /* SMC_H */
diff --git a/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v7_1/src/translation_table.S b/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v7_1/src/translation_table.S
new file mode 100644
index 0000000..24285a0
--- /dev/null
+++ b/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v7_1/src/translation_table.S
@@ -0,0 +1,224 @@
+/******************************************************************************
+*
+* Copyright (C) 2009 - 2015 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+* THE SOFTWARE.
+*
+*
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+* @file translation_table.s
+*
+* @addtogroup a9_boot_code
+* @{
+* <h2> translation_table.S </h2>
+* translation_table.S contains a static page table required by MMU for
+* cortex-A9. This translation table is flat mapped (input address = output
+* address) with default memory attributes defined for zynq architecture. It
+* utilizes short descriptor translation table format with each section defining
+* 1MB of memory.
+*
+* The overview of translation table memory attributes is described below.
+*
+*| | Memory Range | Definition in Translation Table |
+*|-----------------------|-------------------------|-----------------------------------|
+*| DDR | 0x00000000 - 0x3FFFFFFF | Normal write-back Cacheable |
+*| PL | 0x40000000 - 0xBFFFFFFF | Strongly Ordered |
+*| Reserved | 0xC0000000 - 0xDFFFFFFF | Unassigned |
+*| Memory mapped devices | 0xE0000000 - 0xE02FFFFF | Device Memory |
+*| Reserved | 0xE0300000 - 0xE0FFFFFF | Unassigned |
+*| NAND, NOR | 0xE1000000 - 0xE3FFFFFF | Device memory |
+*| SRAM | 0xE4000000 - 0xE5FFFFFF | Normal write-back Cacheable |
+*| Reserved | 0xE6000000 - 0xF7FFFFFF | Unassigned |
+*| AMBA APB Peripherals | 0xF8000000 - 0xF8FFFFFF | Device Memory |
+*| Reserved | 0xF9000000 - 0xFBFFFFFF | Unassigned |
+*| Linear QSPI - XIP | 0xFC000000 - 0xFDFFFFFF | Normal write-through cacheable |
+*| Reserved | 0xFE000000 - 0xFFEFFFFF | Unassigned |
+*| OCM | 0xFFF00000 - 0xFFFFFFFF | Normal inner write-back cacheable |
+*
+* @note
+*
+* For region 0x00000000 - 0x3FFFFFFF, a system where DDR is less than 1GB,
+* region after DDR and before PL is marked as undefined/reserved in translation
+* table. In 0xF8000000 - 0xF8FFFFFF, 0xF8000C00 - 0xF8000FFF, 0xF8010000 -
+* 0xF88FFFFF and 0xF8F03000 to 0xF8FFFFFF are reserved but due to granual size
+* of 1MB, it is not possible to define separate regions for them. For region
+* 0xFFF00000 - 0xFFFFFFFF, 0xFFF00000 to 0xFFFB0000 is reserved but due to 1MB
+* granual size, it is not possible to define separate region for it
+*
+* <pre>
+* MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ----- ---- -------- ---------------------------------------------------
+* 1.00a ecm 10/20/09 Initial version
+* 3.04a sdm 01/13/12 Updated MMU table to mark DDR memory as Shareable
+* 3.07a sgd 07/05/2012 Configuring device address spaces as shareable device
+* instead of strongly-ordered.
+* 3.07a asa 07/17/2012 Changed the property of the ".mmu_tbl" section.
+* 4.2 pkp 09/02/2014 added entries for 0xfe000000 to 0xffefffff as reserved
+* and 0xe0000000 - 0xe1ffffff is broken down into
+* 0xe0000000 - 0xe02fffff (memory mapped divides)
+* 0xe0300000 - 0xe0ffffff (reserved) and
+* 0xe1000000 - 0xe1ffffff (NAND)
+* 5.2 pkp 06/08/2015 put a check for XPAR_PS7_DDR_0_S_AXI_BASEADDR to confirm
+* if DDR is present or not and accordingly generate the
+* translation table
+* 6.1 pkp 07/11/2016 Corrected comments for memory attributes
+* 6.8 mus 07/12/2018 Mark DDR memory as inner cacheable, if BSP is built
+* with the USE_AMP flag.
+* </pre>
+*
+*
+******************************************************************************/
+#include "xparameters.h"
+ .globl MMUTable
+
+ .section .mmu_tbl,"a"
+
+MMUTable:
+ /* Each table entry occupies one 32-bit word and there are
+ * 4096 entries, so the entire table takes up 16KB.
+ * Each entry covers a 1MB section.
+ */
+.set SECT, 0
+
+#ifdef XPAR_PS7_DDR_0_S_AXI_BASEADDR
+.set DDR_START, XPAR_PS7_DDR_0_S_AXI_BASEADDR
+.set DDR_END, XPAR_PS7_DDR_0_S_AXI_HIGHADDR
+.set DDR_SIZE, (DDR_END - DDR_START)+1
+.set DDR_REG, DDR_SIZE/0x100000
+#else
+.set DDR_REG, 0
+#endif
+
+.set UNDEF_REG, 0x3FF - DDR_REG
+
+#ifndef USE_AMP
+ /*0x00000000 - 0x00100000 (inner and outer cacheable )*/
+.word SECT + 0x15de6 /* S=b1 TEX=b101 AP=b11, Domain=b1111, C=b0, B=b1 */
+#else
+ /*0x00000000 - 0x00100000 (inner cacheable )*/
+.word SECT + 0x14de6 /* S=b1 TEX=b100 AP=b11, Domain=b1111, C=b0, B=b1 */
+#endif
+.set SECT, SECT+0x100000
+
+.rept DDR_REG /* (DDR Cacheable) */
+.word SECT + 0x15de6 /* S=b1 TEX=b101 AP=b11, Domain=b1111, C=b0, B=b1 */
+.set SECT, SECT+0x100000
+.endr
+
+.rept UNDEF_REG /* (unassigned/reserved).
+ * Generates a translation fault if accessed */
+.word SECT + 0x0 /* S=b0 TEX=b000 AP=b00, Domain=b0, C=b0, B=b0 */
+.set SECT, SECT+0x100000
+.endr
+
+
+.rept 0x0400 /* 0x40000000 - 0x7fffffff (FPGA slave0) */
+.word SECT + 0xc02 /* S=b0 TEX=b000 AP=b11, Domain=b0, C=b0, B=b0 */
+.set SECT, SECT+0x100000
+.endr
+
+.rept 0x0400 /* 0x80000000 - 0xbfffffff (FPGA slave1) */
+.word SECT + 0xc02 /* S=b0 TEX=b000 AP=b11, Domain=b0, C=b0, B=b0 */
+.set SECT, SECT+0x100000
+.endr
+
+.rept 0x0200 /* 0xc0000000 - 0xdfffffff (unassigned/reserved).
+ * Generates a translation fault if accessed */
+.word SECT + 0x0 /* S=b0 TEX=b000 AP=b00, Domain=b0, C=b0, B=b0 */
+.set SECT, SECT+0x100000
+.endr
+
+.rept 0x003 /* 0xe0000000 - 0xe02fffff (Memory mapped devices)
+ * UART/USB/IIC/SPI/CAN/GEM/GPIO/QSPI/SD/NAND */
+.word SECT + 0xc06 /* S=b0 TEX=b000 AP=b11, Domain=b0, C=b0, B=b1 */
+.set SECT, SECT+0x100000
+.endr
+
+.rept 0x0D /* 0xe0300000 - 0xe0ffffff (unassigned/reserved).
+ * Generates a translation fault if accessed */
+.word SECT + 0x0 /* S=b0 TEX=b000 AP=b00, Domain=b0, C=b0, B=b0 */
+.set SECT, SECT+0x100000
+.endr
+
+.rept 0x0010 /* 0xe1000000 - 0xe1ffffff (NAND) */
+.word SECT + 0xc06 /* S=b0 TEX=b000 AP=b11, Domain=b0, C=b0, B=b1 */
+.set SECT, SECT+0x100000
+.endr
+
+.rept 0x0020 /* 0xe2000000 - 0xe3ffffff (NOR) */
+.word SECT + 0xc06 /* S=b0 TEX=b000 AP=b11, Domain=b0, C=b0, B=b1 */
+.set SECT, SECT+0x100000
+.endr
+
+.rept 0x0020 /* 0xe4000000 - 0xe5ffffff (SRAM) */
+.word SECT + 0xc0e /* S=b0 TEX=b000 AP=b11, Domain=b0, C=b1, B=b1 */
+.set SECT, SECT+0x100000
+.endr
+
+.rept 0x0120 /* 0xe6000000 - 0xf7ffffff (unassigned/reserved).
+ * Generates a translation fault if accessed */
+.word SECT + 0x0 /* S=b0 TEX=b000 AP=b00, Domain=b0, C=b0, B=b0 */
+.set SECT, SECT+0x100000
+.endr
+
+/* 0xf8000c00 to 0xf8000fff, 0xf8010000 to 0xf88fffff and
+ 0xf8f03000 to 0xf8ffffff are reserved but due to granual size of
+ 1MB, it is not possible to define separate regions for them */
+
+.rept 0x0010 /* 0xf8000000 - 0xf8ffffff (AMBA APB Peripherals) */
+
+.word SECT + 0xc06 /* S=b0 TEX=b000 AP=b11, Domain=b0, C=b0, B=b1 */
+.set SECT, SECT+0x100000
+.endr
+
+.rept 0x0030 /* 0xf9000000 - 0xfbffffff (unassigned/reserved).
+ * Generates a translation fault if accessed */
+.word SECT + 0x0 /* S=b0 TEX=b000 AP=b00, Domain=b0, C=b0, B=b0 */
+.set SECT, SECT+0x100000
+.endr
+
+.rept 0x0020 /* 0xfc000000 - 0xfdffffff (Linear QSPI - XIP) */
+.word SECT + 0xc0a /* S=b0 TEX=b000 AP=b11, Domain=b0, C=b1, B=b0 */
+.set SECT, SECT+0x100000
+.endr
+
+.rept 0x001F /* 0xfe000000 - 0xffefffff (unassigned/reserved).
+ * Generates a translation fault if accessed */
+.word SECT + 0x0 /* S=b0 TEX=b000 AP=b00, Domain=b0, C=b0, B=b0 */
+.set SECT, SECT+0x100000
+.endr
+
+/* 0xfff00000 to 0xfffb0000 is reserved but due to granual size of
+ 1MB, it is not possible to define separate region for it
+
+ 0xfff00000 - 0xffffffff
+ 256K OCM when mapped to high address space
+ inner-cacheable */
+.word SECT + 0x4c0e /* S=b0 TEX=b100 AP=b11, Domain=b0, C=b1, B=b1 */
+.set SECT, SECT+0x100000
+
+.end
+/**
+* @} End of "addtogroup a9_boot_code".
+*/
\ No newline at end of file
diff --git a/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v7_1/src/unlink.c b/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v7_1/src/unlink.c
new file mode 100644
index 0000000..562bd7e
--- /dev/null
+++ b/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v7_1/src/unlink.c
@@ -0,0 +1,44 @@
+/******************************************************************************
+*
+* Copyright (C) 2009 - 2015 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+* THE SOFTWARE.
+*
+*
+*
+******************************************************************************/
+
+#include <errno.h>
+#include "xil_types.h"
+
+#ifdef __cplusplus
+extern "C" {
+ __attribute__((weak)) sint32 unlink(char8 *path);
+}
+#endif
+/*
+ * unlink -- since we have no file system,
+ * we just return an error.
+ */
+__attribute__((weak)) sint32 unlink(char8 *path)
+{
+ (void) path;
+ errno = EIO;
+ return (-1);
+}
diff --git a/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v7_1/src/usleep.c b/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v7_1/src/usleep.c
new file mode 100644
index 0000000..6f14102
--- /dev/null
+++ b/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v7_1/src/usleep.c
@@ -0,0 +1,101 @@
+/******************************************************************************
+*
+* Copyright (C) 2009 - 2017 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+* THE SOFTWARE.
+*
+*
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file usleep.c
+*
+* This function provides a microsecond delay using the Global Timer register in
+* the ARM Cortex A9 MP core.
+*
+* <pre>
+* MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ----- -------- -------- -----------------------------------------------
+* 1.00a ecm/sdm 11/11/09 First release
+* 3.07a sgd 07/05/12 Updated micro sleep function to make use Global Timer
+* 4.2 pkp 08/04/14 Removed unimplemented nanosleep routine as it is not
+* possible to generate timer in nanosecond due to
+* limited cpu frequency
+* 6.0 asa 08/15/16 Updated the usleep signature. Fix for CR#956899.
+* 6.6 srm 10/18/17 Updated sleep routines to support user configurable
+* implementation. Now sleep routines will use Timer
+* specified by the user (i.e. Global timer/TTC timer)
+* </pre>
+*
+******************************************************************************/
+/***************************** Include Files *********************************/
+
+#include "sleep.h"
+#include "xtime_l.h"
+#include "xparameters.h"
+#include "xil_types.h"
+#include "xpseudo_asm.h"
+#include "xreg_cortexa9.h"
+
+#if defined (SLEEP_TIMER_BASEADDR)
+#include "xil_sleeptimer.h"
+#endif
+
+/**************************** Constant Definitions ************************/
+#if defined (SLEEP_TIMER_BASEADDR)
+#define COUNTS_PER_USECOND (SLEEP_TIMER_FREQUENCY / 1000000)
+#else
+/* Global Timer is always clocked at half of the CPU frequency */
+#define COUNTS_PER_USECOND (XPAR_CPU_CORTEXA9_CORE_CLOCK_FREQ_HZ / (2U*1000000U))
+#endif
+
+/*****************************************************************************/
+/**
+*
+* This API gives a delay in microseconds
+*
+* @param useconds requested
+*
+* @return 0 if the delay can be achieved, -1 if the requested delay
+* is out of range
+*
+* @note None.
+*
+****************************************************************************/
+int usleep_A9(unsigned long useconds)
+{
+#if defined (SLEEP_TIMER_BASEADDR)
+ Xil_SleepTTCCommon(useconds, COUNTS_PER_USECOND);
+#else
+ XTime tEnd, tCur;
+
+ XTime_GetTime(&tCur);
+ tEnd = tCur + (((XTime) useconds) * COUNTS_PER_USECOND);
+ do
+ {
+ XTime_GetTime(&tCur);
+ } while (tCur < tEnd);
+#endif
+
+ return 0;
+}
diff --git a/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v7_1/src/vectors.c b/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v7_1/src/vectors.c
new file mode 100644
index 0000000..0702dc8
--- /dev/null
+++ b/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v7_1/src/vectors.c
@@ -0,0 +1,225 @@
+/******************************************************************************
+*
+* Copyright (C) 2009 - 2016 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+* THE SOFTWARE.
+*
+*
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+* @file vectors.c
+*
+* This file contains the C level vectors for the ARM Cortex A9 core.
+*
+* <pre>
+* MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ----- ---- -------- ---------------------------------------------------
+* 1.00a ecm 10/20/09 Initial version, moved over from bsp area
+* 6.0 mus 27/07/16 Consolidated vectors for a53,a9 and r5 processor
+* and added UndefinedException for a53 32 bit and r5
+* processor
+* </pre>
+*
+* @note
+*
+* None.
+*
+******************************************************************************/
+/***************************** Include Files *********************************/
+
+#include "xil_exception.h"
+#include "vectors.h"
+
+/************************** Constant Definitions *****************************/
+
+/**************************** Type Definitions *******************************/
+
+typedef struct {
+ Xil_ExceptionHandler Handler;
+ void *Data;
+} XExc_VectorTableEntry;
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/************************** Variable Definitions *****************************/
+
+extern XExc_VectorTableEntry XExc_VectorTable[];
+
+/************************** Function Prototypes ******************************/
+
+
+/*****************************************************************************/
+/**
+*
+* This is the C level wrapper for the FIQ interrupt called from the vectors.s
+* file.
+*
+* @param None.
+*
+* @return None.
+*
+* @note None.
+*
+******************************************************************************/
+void FIQInterrupt(void)
+{
+ XExc_VectorTable[XIL_EXCEPTION_ID_FIQ_INT].Handler(XExc_VectorTable[
+ XIL_EXCEPTION_ID_FIQ_INT].Data);
+}
+
+/*****************************************************************************/
+/**
+*
+* This is the C level wrapper for the IRQ interrupt called from the vectors.s
+* file.
+*
+* @param None.
+*
+* @return None.
+*
+* @note None.
+*
+******************************************************************************/
+void IRQInterrupt(void)
+{
+ XExc_VectorTable[XIL_EXCEPTION_ID_IRQ_INT].Handler(XExc_VectorTable[
+ XIL_EXCEPTION_ID_IRQ_INT].Data);
+}
+
+#if !defined (__aarch64__)
+/*****************************************************************************/
+/**
+*
+* This is the C level wrapper for the Undefined exception called from the
+* vectors.s file.
+*
+* @param None.
+*
+* @return None.
+*
+* @note None.
+*
+******************************************************************************/
+void UndefinedException(void)
+{
+ XExc_VectorTable[XIL_EXCEPTION_ID_UNDEFINED_INT].Handler(XExc_VectorTable[
+ XIL_EXCEPTION_ID_UNDEFINED_INT].Data);
+}
+
+/*****************************************************************************/
+/**
+*
+* This is the C level wrapper for the SW Interrupt called from the vectors.s
+* file.
+*
+* @param None.
+*
+* @return None.
+*
+* @note None.
+*
+******************************************************************************/
+void SWInterrupt(void)
+{
+ XExc_VectorTable[XIL_EXCEPTION_ID_SWI_INT].Handler(XExc_VectorTable[
+ XIL_EXCEPTION_ID_SWI_INT].Data);
+}
+
+/*****************************************************************************/
+/**
+*
+* This is the C level wrapper for the DataAbort Interrupt called from the
+* vectors.s file.
+*
+* @param None.
+*
+* @return None.
+*
+* @note None.
+*
+******************************************************************************/
+void DataAbortInterrupt(void)
+{
+ XExc_VectorTable[XIL_EXCEPTION_ID_DATA_ABORT_INT].Handler(
+ XExc_VectorTable[XIL_EXCEPTION_ID_DATA_ABORT_INT].Data);
+}
+
+/*****************************************************************************/
+/**
+*
+* This is the C level wrapper for the PrefetchAbort Interrupt called from the
+* vectors.s file.
+*
+* @param None.
+*
+* @return None.
+*
+* @note None.
+*
+******************************************************************************/
+void PrefetchAbortInterrupt(void)
+{
+ XExc_VectorTable[XIL_EXCEPTION_ID_PREFETCH_ABORT_INT].Handler(
+ XExc_VectorTable[XIL_EXCEPTION_ID_PREFETCH_ABORT_INT].Data);
+}
+#else
+
+/*****************************************************************************/
+/**
+*
+* This is the C level wrapper for the Synchronous Interrupt called from the vectors.s
+* file.
+*
+* @param None.
+*
+* @return None.
+*
+* @note None.
+*
+******************************************************************************/
+void SynchronousInterrupt(void)
+{
+ XExc_VectorTable[XIL_EXCEPTION_ID_SYNC_INT].Handler(XExc_VectorTable[
+ XIL_EXCEPTION_ID_SYNC_INT].Data);
+}
+
+/*****************************************************************************/
+/**
+*
+* This is the C level wrapper for the SError Interrupt called from the
+* vectors.s file.
+*
+* @param None.
+*
+* @return None.
+*
+* @note None.
+*
+******************************************************************************/
+void SErrorInterrupt(void)
+{
+ XExc_VectorTable[XIL_EXCEPTION_ID_SERROR_ABORT_INT].Handler(
+ XExc_VectorTable[XIL_EXCEPTION_ID_SERROR_ABORT_INT].Data);
+}
+
+#endif
diff --git a/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v7_1/src/vectors.h b/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v7_1/src/vectors.h
new file mode 100644
index 0000000..2647862
--- /dev/null
+++ b/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v7_1/src/vectors.h
@@ -0,0 +1,82 @@
+/******************************************************************************
+*
+* Copyright (C) 2009 - 2016 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+* THE SOFTWARE.
+*
+*
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+* @file vectors.h
+*
+* This file contains the C level vector prototypes for the ARM Cortex A9 core.
+*
+* <pre>
+* MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ----- ---- -------- ---------------------------------------------------
+* 1.00a ecm 10/20/10 Initial version, moved over from bsp area
+* 6.0 mus 07/27/16 Consolidated vectors for a9,a53 and r5 processors
+* </pre>
+*
+* @note
+*
+* None.
+*
+******************************************************************************/
+
+#ifndef _VECTORS_H_
+#define _VECTORS_H_
+
+/***************************** Include Files *********************************/
+
+#include "xil_types.h"
+#include "xil_assert.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/**************************** Type Definitions *******************************/
+
+/************************** Constant Definitions *****************************/
+
+/************************** Function Prototypes ******************************/
+
+void FIQInterrupt(void);
+void IRQInterrupt(void);
+#if !defined (__aarch64__)
+void SWInterrupt(void);
+void DataAbortInterrupt(void);
+void PrefetchAbortInterrupt(void);
+void UndefinedException(void);
+#else
+void SynchronousInterrupt(void);
+void SErrorInterrupt(void);
+#endif
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* protection macro */
diff --git a/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v7_1/src/write.c b/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v7_1/src/write.c
new file mode 100644
index 0000000..beb6a12
--- /dev/null
+++ b/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v7_1/src/write.c
@@ -0,0 +1,115 @@
+/******************************************************************************
+*
+* Copyright (C) 2009 - 2018 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+* THE SOFTWARE.
+*
+*
+*
+******************************************************************************/
+
+/* write.c -- write bytes to an output device.
+ */
+#ifndef UNDEFINE_FILE_OPS
+#include "xil_printf.h"
+#include "xparameters.h"
+
+#ifdef __cplusplus
+extern "C" {
+ __attribute__((weak)) sint32 _write (sint32 fd, char8* buf, sint32 nbytes);
+}
+#endif
+
+/*
+ * write -- write bytes to the serial port. Ignore fd, since
+ * stdout and stderr are the same. Since we have no filesystem,
+ * open will only return an error.
+ */
+__attribute__((weak)) sint32
+write (sint32 fd, char8* buf, sint32 nbytes)
+
+{
+#ifdef STDOUT_BASEADDRESS
+ s32 i;
+ char8* LocalBuf = buf;
+
+ (void)fd;
+ for (i = 0; i < nbytes; i++) {
+ if(LocalBuf != NULL) {
+ LocalBuf += i;
+ }
+ if(LocalBuf != NULL) {
+ if (*LocalBuf == '\n') {
+ outbyte ('\r');
+ }
+ outbyte (*LocalBuf);
+ }
+ if(LocalBuf != NULL) {
+ LocalBuf -= i;
+ }
+ }
+ return (nbytes);
+#else
+ (void)fd;
+ (void)buf;
+ (void)nbytes;
+ return 0;
+#endif
+}
+
+__attribute__((weak)) sint32
+_write (sint32 fd, char8* buf, sint32 nbytes)
+{
+#if HYP_GUEST && EL1_NONSECURE && XEN_USE_PV_CONSOLE
+ sint32 length;
+
+ (void)fd;
+ (void)nbytes;
+ length = XPVXenConsole_Write(buf);
+ return length;
+#else
+#ifdef STDOUT_BASEADDRESS
+ s32 i;
+ char8* LocalBuf = buf;
+
+ (void)fd;
+ for (i = 0; i < nbytes; i++) {
+ if(LocalBuf != NULL) {
+ LocalBuf += i;
+ }
+ if(LocalBuf != NULL) {
+ if (*LocalBuf == '\n') {
+ outbyte ('\r');
+ }
+ outbyte (*LocalBuf);
+ }
+ if(LocalBuf != NULL) {
+ LocalBuf -= i;
+ }
+ }
+ return (nbytes);
+#else
+ (void)fd;
+ (void)buf;
+ (void)nbytes;
+ return 0;
+#endif
+#endif
+}
+#endif
diff --git a/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v7_1/src/xbasic_types.h b/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v7_1/src/xbasic_types.h
new file mode 100644
index 0000000..e9a0256
--- /dev/null
+++ b/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v7_1/src/xbasic_types.h
@@ -0,0 +1,125 @@
+/******************************************************************************
+*
+* Copyright (C) 2010 - 2019 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+* THE SOFTWARE.
+*
+*
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xbasic_types.h
+*
+*
+* @note Dummy File for backwards compatibility
+*
+
+*
+* <pre>
+* MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ----- ---- -------- -------------------------------------------------------
+* 1.00a adk 1/31/14 Added in bsp common folder for backward compatibility
+* 7.0 aru 01/21/19 Modified the typedef of u32,u16,u8
+* 7.0 aru 02/06/19 Included stdint.h and stddef.h
+* </pre>
+*
+******************************************************************************/
+
+#ifndef XBASIC_TYPES_H /* prevent circular inclusions */
+#define XBASIC_TYPES_H /* by using protection macros */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <stdint.h>
+#include <stddef.h>
+
+/** @name Legacy types
+ * Deprecated legacy types.
+ * @{
+ */
+typedef uint8_t Xuint8; /**< unsigned 8-bit */
+typedef char Xint8; /**< signed 8-bit */
+typedef uint16_t Xuint16; /**< unsigned 16-bit */
+typedef short Xint16; /**< signed 16-bit */
+typedef uint32_t Xuint32; /**< unsigned 32-bit */
+typedef long Xint32; /**< signed 32-bit */
+typedef float Xfloat32; /**< 32-bit floating point */
+typedef double Xfloat64; /**< 64-bit double precision FP */
+typedef unsigned long Xboolean; /**< boolean (XTRUE or XFALSE) */
+
+#if !defined __XUINT64__
+typedef struct
+{
+ Xuint32 Upper;
+ Xuint32 Lower;
+} Xuint64;
+#endif
+
+/** @name New types
+ * New simple types.
+ * @{
+ */
+#ifndef __KERNEL__
+#ifndef XIL_TYPES_H
+typedef Xuint32 u32;
+typedef Xuint16 u16;
+typedef Xuint8 u8;
+#endif
+#else
+#include <linux/types.h>
+#endif
+
+#ifndef TRUE
+# define TRUE 1U
+#endif
+
+#ifndef FALSE
+# define FALSE 0U
+#endif
+
+#ifndef NULL
+#define NULL 0U
+#endif
+
+/*
+ * Xilinx NULL, TRUE and FALSE legacy support. Deprecated.
+ * Please use NULL, TRUE and FALSE
+ */
+#define XNULL NULL
+#define XTRUE TRUE
+#define XFALSE FALSE
+
+/*
+ * This file is deprecated and users
+ * should use xil_types.h and xil_assert.h\n\r
+ */
+#warning The xbasics_type.h file is deprecated and users should use xil_types.h and xil_assert.
+#warning Please refer the Standalone BSP UG647 for further details
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* end of protection macro */
diff --git a/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v7_1/src/xdebug.h b/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v7_1/src/xdebug.h
new file mode 100644
index 0000000..b09c02d
--- /dev/null
+++ b/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v7_1/src/xdebug.h
@@ -0,0 +1,40 @@
+#ifndef XDEBUG /* prevent circular inclusions */
+#define XDEBUG /* by using protection macros */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#if defined(DEBUG) && !defined(NDEBUG)
+
+#ifndef XDEBUG_WARNING
+#define XDEBUG_WARNING
+#warning DEBUG is enabled
+#endif
+
+int printf(const char *format, ...);
+
+#define XDBG_DEBUG_ERROR 0x00000001U /* error condition messages */
+#define XDBG_DEBUG_GENERAL 0x00000002U /* general debug messages */
+#define XDBG_DEBUG_ALL 0xFFFFFFFFU /* all debugging data */
+
+#define xdbg_current_types (XDBG_DEBUG_GENERAL)
+
+#define xdbg_stmnt(x) x
+
+#define xdbg_printf(type, ...) (((type) & xdbg_current_types) ? printf (__VA_ARGS__) : 0)
+
+
+#else /* defined(DEBUG) && !defined(NDEBUG) */
+
+#define xdbg_stmnt(x)
+
+#define xdbg_printf(...)
+
+#endif /* defined(DEBUG) && !defined(NDEBUG) */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* XDEBUG */
diff --git a/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v7_1/src/xenv.h b/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v7_1/src/xenv.h
new file mode 100644
index 0000000..a52b909
--- /dev/null
+++ b/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v7_1/src/xenv.h
@@ -0,0 +1,181 @@
+/******************************************************************************
+*
+* Copyright (C) 2002 - 2015 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+* THE SOFTWARE.
+*
+*
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xenv.h
+*
+* Defines common services that are typically found in a host operating.
+* environment. This include file simply includes an OS specific file based
+* on the compile-time constant BUILD_ENV_*, where * is the name of the target
+* environment.
+*
+* All services are defined as macros.
+*
+* <pre>
+* MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ----- ---- -------- -----------------------------------------------
+* 1.00b ch 10/24/02 Added XENV_LINUX
+* 1.00a rmm 04/17/02 First release
+* </pre>
+*
+******************************************************************************/
+
+#ifndef XENV_H /* prevent circular inclusions */
+#define XENV_H /* by using protection macros */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+ * Select which target environment we are operating under
+ */
+
+/* VxWorks target environment */
+#if defined XENV_VXWORKS
+#include "xenv_vxworks.h"
+
+/* Linux target environment */
+#elif defined XENV_LINUX
+#include "xenv_linux.h"
+
+/* Unit test environment */
+#elif defined XENV_UNITTEST
+#include "ut_xenv.h"
+
+/* Integration test environment */
+#elif defined XENV_INTTEST
+#include "int_xenv.h"
+
+/* Standalone environment selected */
+#else
+#include "xenv_standalone.h"
+#endif
+
+
+/*
+ * The following comments specify the types and macro wrappers that are
+ * expected to be defined by the target specific header files
+ */
+
+/**************************** Type Definitions *******************************/
+
+/*****************************************************************************/
+/**
+ *
+ * XENV_TIME_STAMP
+ *
+ * A structure that contains a time stamp used by other time stamp macros
+ * defined below. This structure is processor dependent.
+ */
+
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/*****************************************************************************/
+/**
+ *
+ * XENV_MEM_COPY(void *DestPtr, void *SrcPtr, unsigned Bytes)
+ *
+ * Copies a non-overlapping block of memory.
+ *
+ * @param DestPtr is the destination address to copy data to.
+ * @param SrcPtr is the source address to copy data from.
+ * @param Bytes is the number of bytes to copy.
+ *
+ * @return None
+ */
+
+/*****************************************************************************/
+/**
+ *
+ * XENV_MEM_FILL(void *DestPtr, char Data, unsigned Bytes)
+ *
+ * Fills an area of memory with constant data.
+ *
+ * @param DestPtr is the destination address to set.
+ * @param Data contains the value to set.
+ * @param Bytes is the number of bytes to set.
+ *
+ * @return None
+ */
+/*****************************************************************************/
+/**
+ *
+ * XENV_TIME_STAMP_GET(XTIME_STAMP *StampPtr)
+ *
+ * Samples the processor's or external timer's time base counter.
+ *
+ * @param StampPtr is the storage for the retrieved time stamp.
+ *
+ * @return None
+ */
+
+/*****************************************************************************/
+/**
+ *
+ * XENV_TIME_STAMP_DELTA_US(XTIME_STAMP *Stamp1Ptr, XTIME_STAMP* Stamp2Ptr)
+ *
+ * Computes the delta between the two time stamps.
+ *
+ * @param Stamp1Ptr - First sampled time stamp.
+ * @param Stamp1Ptr - Sedond sampled time stamp.
+ *
+ * @return An unsigned int value with units of microseconds.
+ */
+
+/*****************************************************************************/
+/**
+ *
+ * XENV_TIME_STAMP_DELTA_MS(XTIME_STAMP *Stamp1Ptr, XTIME_STAMP* Stamp2Ptr)
+ *
+ * Computes the delta between the two time stamps.
+ *
+ * @param Stamp1Ptr - First sampled time stamp.
+ * @param Stamp1Ptr - Sedond sampled time stamp.
+ *
+ * @return An unsigned int value with units of milliseconds.
+ */
+
+/*****************************************************************************//**
+ *
+ * XENV_USLEEP(unsigned delay)
+ *
+ * Delay the specified number of microseconds.
+ *
+ * @param delay is the number of microseconds to delay.
+ *
+ * @return None
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* end of protection macro */
diff --git a/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v7_1/src/xenv_standalone.h b/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v7_1/src/xenv_standalone.h
new file mode 100644
index 0000000..4468abb
--- /dev/null
+++ b/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v7_1/src/xenv_standalone.h
@@ -0,0 +1,362 @@
+/******************************************************************************
+*
+* Copyright (C) 2002 - 2015 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+* THE SOFTWARE.
+*
+*
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xenv_standalone.h
+*
+* Defines common services specified by xenv.h.
+*
+* @note
+* This file is not intended to be included directly by driver code.
+* Instead, the generic xenv.h file is intended to be included by driver
+* code.
+*
+* <pre>
+* MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ----- ---- -------- -----------------------------------------------
+* 1.00a wgr 02/28/07 Added cache handling macros.
+* 1.00a wgr 02/27/07 Simplified code. Deprecated old-style macro names.
+* 1.00a rmm 01/24/06 Implemented XENV_USLEEP. Assume implementation is being
+* used under Xilinx standalone BSP.
+* 1.00a xd 11/03/04 Improved support for doxygen.
+* 1.00a rmm 03/21/02 First release
+* 1.00a wgr 03/22/07 Converted to new coding style.
+* 1.00a rpm 06/29/07 Added udelay macro for standalone
+* 1.00a xd 07/19/07 Included xparameters.h as XPAR_ constants are referred
+* to in MICROBLAZE section
+* 1.00a ecm 09/19/08 updated for v7.20 of Microblaze, new functionality
+*
+* </pre>
+*
+*
+******************************************************************************/
+
+#ifndef XENV_STANDALONE_H
+#define XENV_STANDALONE_H
+
+#include "xil_types.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/***************************** Include Files *********************************/
+/******************************************************************************
+ *
+ * Get the processor dependent includes
+ *
+ ******************************************************************************/
+
+#include <string.h>
+
+#if defined __MICROBLAZE__
+# include "mb_interface.h"
+# include "xparameters.h" /* XPAR constants used below in MB section */
+
+#elif defined __PPC__
+# include "sleep.h"
+# include "xcache_l.h" /* also include xcache_l.h for caching macros */
+#endif
+
+/******************************************************************************
+ *
+ * MEMCPY / MEMSET related macros.
+ *
+ * The following are straight forward implementations of memset and memcpy.
+ *
+ * NOTE: memcpy may not work if source and target memory area are overlapping.
+ *
+ ******************************************************************************/
+/*****************************************************************************/
+/**
+ *
+ * Copies a non-overlapping block of memory.
+ *
+ * @param DestPtr
+ * Destination address to copy data to.
+ *
+ * @param SrcPtr
+ * Source address to copy data from.
+ *
+ * @param Bytes
+ * Number of bytes to copy.
+ *
+ * @return None.
+ *
+ * @note
+ * The use of XENV_MEM_COPY is deprecated. Use memcpy() instead.
+ *
+ * @note
+ * This implementation MAY BREAK work if source and target memory
+ * area are overlapping.
+ *
+ *****************************************************************************/
+
+#define XENV_MEM_COPY(DestPtr, SrcPtr, Bytes) \
+ memcpy((void *) DestPtr, (const void *) SrcPtr, (size_t) Bytes)
+
+
+
+/*****************************************************************************/
+/**
+ *
+ * Fills an area of memory with constant data.
+ *
+ * @param DestPtr
+ * Destination address to copy data to.
+ *
+ * @param Data
+ * Value to set.
+ *
+ * @param Bytes
+ * Number of bytes to copy.
+ *
+ * @return None.
+ *
+ * @note
+ * The use of XENV_MEM_FILL is deprecated. Use memset() instead.
+ *
+ *****************************************************************************/
+
+#define XENV_MEM_FILL(DestPtr, Data, Bytes) \
+ memset((void *) DestPtr, (s32) Data, (size_t) Bytes)
+
+
+
+/******************************************************************************
+ *
+ * TIME related macros
+ *
+ ******************************************************************************/
+
+/**
+ * A structure that contains a time stamp used by other time stamp macros
+ * defined below. This structure is processor dependent.
+ */
+typedef s32 XENV_TIME_STAMP;
+
+/*****************************************************************************/
+/**
+ *
+ * Time is derived from the 64 bit PPC timebase register
+ *
+ * @param StampPtr is the storage for the retrieved time stamp.
+ *
+ * @return None.
+ *
+ * @note
+ *
+ * Signature: void XENV_TIME_STAMP_GET(XTIME_STAMP *StampPtr)
+ * <br><br>
+ * This macro must be implemented by the user.
+ *
+ *****************************************************************************/
+#define XENV_TIME_STAMP_GET(StampPtr)
+
+/*****************************************************************************/
+/**
+ *
+ * This macro is not yet implemented and always returns 0.
+ *
+ * @param Stamp1Ptr is the first sampled time stamp.
+ * @param Stamp2Ptr is the second sampled time stamp.
+ *
+ * @return 0
+ *
+ * @note
+ *
+ * This macro must be implemented by the user.
+ *
+ *****************************************************************************/
+#define XENV_TIME_STAMP_DELTA_US(Stamp1Ptr, Stamp2Ptr) (0)
+
+/*****************************************************************************/
+/**
+ *
+ * This macro is not yet implemented and always returns 0.
+ *
+ * @param Stamp1Ptr is the first sampled time stamp.
+ * @param Stamp2Ptr is the second sampled time stamp.
+ *
+ * @return 0
+ *
+ * @note
+ *
+ * This macro must be implemented by the user.
+ *
+ *****************************************************************************/
+#define XENV_TIME_STAMP_DELTA_MS(Stamp1Ptr, Stamp2Ptr) (0)
+
+/*****************************************************************************/
+/**
+ * XENV_USLEEP(unsigned delay)
+ *
+ * Delay the specified number of microseconds. Not implemented without OS
+ * support.
+ *
+ * @param delay
+ * Number of microseconds to delay.
+ *
+ * @return None.
+ *
+ *****************************************************************************/
+
+#ifdef __PPC__
+#define XENV_USLEEP(delay) usleep(delay)
+#define udelay(delay) usleep(delay)
+#else
+#define XENV_USLEEP(delay)
+#define udelay(delay)
+#endif
+
+
+/******************************************************************************
+ *
+ * CACHE handling macros / mappings
+ *
+ ******************************************************************************/
+/******************************************************************************
+ *
+ * Processor independent macros
+ *
+ ******************************************************************************/
+
+#define XCACHE_ENABLE_CACHE() \
+ { XCACHE_ENABLE_DCACHE(); XCACHE_ENABLE_ICACHE(); }
+
+#define XCACHE_DISABLE_CACHE() \
+ { XCACHE_DISABLE_DCACHE(); XCACHE_DISABLE_ICACHE(); }
+
+
+/******************************************************************************
+ *
+ * MicroBlaze case
+ *
+ * NOTE: Currently the following macros will only work on systems that contain
+ * only ONE MicroBlaze processor. Also, the macros will only be enabled if the
+ * system is built using a xparameters.h file.
+ *
+ ******************************************************************************/
+
+#if defined __MICROBLAZE__
+
+/* Check if MicroBlaze data cache was built into the core.
+ */
+#if (XPAR_MICROBLAZE_USE_DCACHE == 1)
+# define XCACHE_ENABLE_DCACHE() microblaze_enable_dcache()
+# define XCACHE_DISABLE_DCACHE() microblaze_disable_dcache()
+# define XCACHE_INVALIDATE_DCACHE() microblaze_invalidate_dcache()
+
+# define XCACHE_INVALIDATE_DCACHE_RANGE(Addr, Len) \
+ microblaze_invalidate_dcache_range((s32)(Addr), (s32)(Len))
+
+#if (XPAR_MICROBLAZE_DCACHE_USE_WRITEBACK == 1)
+# define XCACHE_FLUSH_DCACHE() microblaze_flush_dcache()
+# define XCACHE_FLUSH_DCACHE_RANGE(Addr, Len) \
+ microblaze_flush_dcache_range((s32)(Addr), (s32)(Len))
+#else
+# define XCACHE_FLUSH_DCACHE() microblaze_invalidate_dcache()
+# define XCACHE_FLUSH_DCACHE_RANGE(Addr, Len) \
+ microblaze_invalidate_dcache_range((s32)(Addr), (s32)(Len))
+#endif /*XPAR_MICROBLAZE_DCACHE_USE_WRITEBACK*/
+
+#else
+# define XCACHE_ENABLE_DCACHE()
+# define XCACHE_DISABLE_DCACHE()
+# define XCACHE_INVALIDATE_DCACHE_RANGE(Addr, Len)
+# define XCACHE_FLUSH_DCACHE_RANGE(Addr, Len)
+#endif /*XPAR_MICROBLAZE_USE_DCACHE*/
+
+
+/* Check if MicroBlaze instruction cache was built into the core.
+ */
+#if (XPAR_MICROBLAZE_USE_ICACHE == 1)
+# define XCACHE_ENABLE_ICACHE() microblaze_enable_icache()
+# define XCACHE_DISABLE_ICACHE() microblaze_disable_icache()
+
+# define XCACHE_INVALIDATE_ICACHE() microblaze_invalidate_icache()
+
+# define XCACHE_INVALIDATE_ICACHE_RANGE(Addr, Len) \
+ microblaze_invalidate_icache_range((s32)(Addr), (s32)(Len))
+
+#else
+# define XCACHE_ENABLE_ICACHE()
+# define XCACHE_DISABLE_ICACHE()
+#endif /*XPAR_MICROBLAZE_USE_ICACHE*/
+
+
+/******************************************************************************
+ *
+ * PowerPC case
+ *
+ * Note that the XCACHE_ENABLE_xxx functions are hardcoded to enable a
+ * specific memory region (0x80000001). Each bit (0-30) in the regions
+ * bitmask stands for 128MB of memory. Bit 31 stands for the upper 2GB
+ * range.
+ *
+ * regions --> cached address range
+ * ------------|--------------------------------------------------
+ * 0x80000000 | [0, 0x7FFFFFF]
+ * 0x00000001 | [0xF8000000, 0xFFFFFFFF]
+ * 0x80000001 | [0, 0x7FFFFFF],[0xF8000000, 0xFFFFFFFF]
+ *
+ ******************************************************************************/
+
+#elif defined __PPC__
+
+#define XCACHE_ENABLE_DCACHE() XCache_EnableDCache(0x80000001)
+#define XCACHE_DISABLE_DCACHE() XCache_DisableDCache()
+#define XCACHE_ENABLE_ICACHE() XCache_EnableICache(0x80000001)
+#define XCACHE_DISABLE_ICACHE() XCache_DisableICache()
+
+#define XCACHE_INVALIDATE_DCACHE_RANGE(Addr, Len) \
+ XCache_InvalidateDCacheRange((u32)(Addr), (u32)(Len))
+
+#define XCACHE_FLUSH_DCACHE_RANGE(Addr, Len) \
+ XCache_FlushDCacheRange((u32)(Addr), (u32)(Len))
+
+#define XCACHE_INVALIDATE_ICACHE() XCache_InvalidateICache()
+
+
+/******************************************************************************
+ *
+ * Unknown processor / architecture
+ *
+ ******************************************************************************/
+
+#else
+/* #error "Unknown processor / architecture. Must be MicroBlaze or PowerPC." */
+#endif
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* #ifndef XENV_STANDALONE_H */
diff --git a/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v7_1/src/xil-crt0.S b/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v7_1/src/xil-crt0.S
new file mode 100644
index 0000000..1eb3913
--- /dev/null
+++ b/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v7_1/src/xil-crt0.S
@@ -0,0 +1,153 @@
+/******************************************************************************
+*
+* Copyright (C) 2009 - 2017 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+* THE SOFTWARE.
+*
+*
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+* @file xil-crt0.S
+*
+* <pre>
+* MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ----- ---- -------- ---------------------------------------------------
+* 1.00a ecm 10/20/09 Initial version
+* 3.05a sdm 02/02/12 Added code for profiling
+* 3.06a sgd 05/16/12 Added global constructors and cleanup code
+* Uart initialization based on compiler flag
+* 3.07a sgd 07/05/12 Updated with reset and start Global Timer
+* 3.07a sgd 10/19/12 SMC NOR and SRAM initialization with build option
+* 4.2 pkp 08/04/14 Removed PEEP board related code which contained
+* initialization of uart smc nor and sram
+* 5.3 pkp 10/07/15 Added support for OpenAMP by not initializing global
+* timer when USE_AMP flag is defined
+* 6.6 srm 10/18/17 Added timer configuration using XTime_StartTTCTimer API.
+* Now the TTC instance as specified by the user will be
+* started.
+* </pre>
+*
+* @note
+*
+* None.
+*
+******************************************************************************/
+#include "bspconfig.h"
+
+ .file "xil-crt0.S"
+ .section ".got2","aw"
+ .align 2
+
+ .text
+.Lsbss_start:
+ .long __sbss_start
+
+.Lsbss_end:
+ .long __sbss_end
+
+.Lbss_start:
+ .long __bss_start
+
+.Lbss_end:
+ .long __bss_end
+
+.Lstack:
+ .long __stack
+
+
+ .globl _start
+_start:
+ bl __cpu_init /* Initialize the CPU first (BSP provides this) */
+
+ mov r0, #0
+
+ /* clear sbss */
+ ldr r1,.Lsbss_start /* calculate beginning of the SBSS */
+ ldr r2,.Lsbss_end /* calculate end of the SBSS */
+
+.Lloop_sbss:
+ cmp r1,r2
+ bge .Lenclsbss /* If no SBSS, no clearing required */
+ str r0, [r1], #4
+ b .Lloop_sbss
+
+.Lenclsbss:
+ /* clear bss */
+ ldr r1,.Lbss_start /* calculate beginning of the BSS */
+ ldr r2,.Lbss_end /* calculate end of the BSS */
+
+.Lloop_bss:
+ cmp r1,r2
+ bge .Lenclbss /* If no BSS, no clearing required */
+ str r0, [r1], #4
+ b .Lloop_bss
+
+.Lenclbss:
+
+ /* set stack pointer */
+ ldr r13,.Lstack /* stack address */
+
+ /* Reset and start Global Timer */
+ mov r0, #0x0
+ mov r1, #0x0
+
+ /* Reset and start Triple Timer Counter */
+ #if defined SLEEP_TIMER_BASEADDR
+ bl XTime_StartTTCTimer
+ #endif
+
+#if USE_AMP != 1
+ bl XTime_SetTime
+#endif
+
+#ifdef PROFILING /* defined in Makefile */
+ /* Setup profiling stuff */
+ bl _profile_init
+#endif /* PROFILING */
+
+ /* run global constructors */
+ bl __libc_init_array
+
+ /* make sure argc and argv are valid */
+ mov r0, #0
+ mov r1, #0
+
+ /* Let her rip */
+ bl main
+
+ /* Cleanup global constructors */
+ bl __libc_fini_array
+
+#ifdef PROFILING
+ /* Cleanup profiling stuff */
+ bl _profile_clean
+#endif /* PROFILING */
+
+ /* All done */
+ bl exit
+
+.Lexit: /* should never get here */
+ b .Lexit
+
+.Lstart:
+ .size _start,.Lstart-_start
diff --git a/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v7_1/src/xil_assert.c b/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v7_1/src/xil_assert.c
new file mode 100644
index 0000000..8018420
--- /dev/null
+++ b/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v7_1/src/xil_assert.c
@@ -0,0 +1,141 @@
+/******************************************************************************
+*
+* Copyright (C) 2009 - 2016 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+* THE SOFTWARE.
+*
+*
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xil_assert.c
+*
+* This file contains basic assert related functions for Xilinx software IP.
+*
+* <pre>
+* MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ----- ---- -------- -------------------------------------------------------
+* 1.00a hbm 07/14/09 Initial release
+* 6.0 kvn 05/31/16 Make Xil_AsserWait a global variable
+* </pre>
+*
+******************************************************************************/
+
+/***************************** Include Files *********************************/
+
+#include "xil_types.h"
+#include "xil_assert.h"
+
+/************************** Constant Definitions *****************************/
+
+/**************************** Type Definitions *******************************/
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/************************** Variable Definitions *****************************/
+
+/**
+ * This variable allows testing to be done easier with asserts. An assert
+ * sets this variable such that a driver can evaluate this variable
+ * to determine if an assert occurred.
+ */
+u32 Xil_AssertStatus;
+
+/**
+ * This variable allows the assert functionality to be changed for testing
+ * such that it does not wait infinitely. Use the debugger to disable the
+ * waiting during testing of asserts.
+ */
+s32 Xil_AssertWait = 1;
+
+/* The callback function to be invoked when an assert is taken */
+static Xil_AssertCallback Xil_AssertCallbackRoutine = NULL;
+
+/************************** Function Prototypes ******************************/
+
+/*****************************************************************************/
+/**
+*
+* @brief Implement assert. Currently, it calls a user-defined callback
+* function if one has been set. Then, it potentially enters an
+* infinite loop depending on the value of the Xil_AssertWait
+* variable.
+*
+* @param file: filename of the source
+* @param line: linenumber within File
+*
+* @return None.
+*
+* @note None.
+*
+******************************************************************************/
+void Xil_Assert(const char8 *File, s32 Line)
+{
+ /* if the callback has been set then invoke it */
+ if (Xil_AssertCallbackRoutine != 0) {
+ (*Xil_AssertCallbackRoutine)(File, Line);
+ }
+
+ /* if specified, wait indefinitely such that the assert will show up
+ * in testing
+ */
+ while (Xil_AssertWait != 0) {
+ }
+}
+
+/*****************************************************************************/
+/**
+*
+* @brief Set up a callback function to be invoked when an assert occurs.
+* If a callback is already installed, then it will be replaced.
+*
+* @param routine: callback to be invoked when an assert is taken
+*
+* @return None.
+*
+* @note This function has no effect if NDEBUG is set
+*
+******************************************************************************/
+void Xil_AssertSetCallback(Xil_AssertCallback Routine)
+{
+ Xil_AssertCallbackRoutine = Routine;
+}
+
+/*****************************************************************************/
+/**
+*
+* @brief Null handler function. This follows the XInterruptHandler
+* signature for interrupt handlers. It can be used to assign a null
+* handler (a stub) to an interrupt controller vector table.
+*
+* @param NullParameter: arbitrary void pointer and not used.
+*
+* @return None.
+*
+* @note None.
+*
+******************************************************************************/
+void XNullHandler(void *NullParameter)
+{
+ (void) NullParameter;
+}
diff --git a/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v7_1/src/xil_assert.h b/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v7_1/src/xil_assert.h
new file mode 100644
index 0000000..489c62c
--- /dev/null
+++ b/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v7_1/src/xil_assert.h
@@ -0,0 +1,189 @@
+/******************************************************************************
+*
+* Copyright (C) 2009 - 2018 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+* THE SOFTWARE.
+*
+*
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xil_assert.h
+*
+* @addtogroup common_assert_apis Assert APIs and Macros
+*
+* The xil_assert.h file contains assert related functions and macros.
+* Assert APIs/Macros specifies that a application program satisfies certain
+* conditions at particular points in its execution. These function can be
+* used by application programs to ensure that, application code is satisfying
+* certain conditions.
+*
+* @{
+* <pre>
+* MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ----- ---- -------- -------------------------------------------------------
+* 1.00a hbm 07/14/09 First release
+* 6.0 kvn 05/31/16 Make Xil_AsserWait a global variable
+* </pre>
+*
+******************************************************************************/
+
+#ifndef XIL_ASSERT_H /* prevent circular inclusions */
+#define XIL_ASSERT_H /* by using protection macros */
+
+#include "xil_types.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+
+/***************************** Include Files *********************************/
+
+
+/************************** Constant Definitions *****************************/
+
+#define XIL_ASSERT_NONE 0U
+#define XIL_ASSERT_OCCURRED 1U
+#define XNULL NULL
+
+extern u32 Xil_AssertStatus;
+extern s32 Xil_AssertWait;
+extern void Xil_Assert(const char8 *File, s32 Line);
+void XNullHandler(void *NullParameter);
+
+/**
+ * This data type defines a callback to be invoked when an
+ * assert occurs. The callback is invoked only when asserts are enabled
+ */
+typedef void (*Xil_AssertCallback) (const char8 *File, s32 Line);
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+#ifndef NDEBUG
+
+/*****************************************************************************/
+/**
+* @brief This assert macro is to be used for void functions. This in
+* conjunction with the Xil_AssertWait boolean can be used to
+* accommodate tests so that asserts which fail allow execution to
+* continue.
+*
+* @param Expression: expression to be evaluated. If it evaluates to
+* false, the assert occurs.
+*
+* @return Returns void unless the Xil_AssertWait variable is true, in which
+* case no return is made and an infinite loop is entered.
+*
+******************************************************************************/
+#define Xil_AssertVoid(Expression) \
+{ \
+ if (Expression) { \
+ Xil_AssertStatus = XIL_ASSERT_NONE; \
+ } else { \
+ Xil_Assert(__FILE__, __LINE__); \
+ Xil_AssertStatus = XIL_ASSERT_OCCURRED; \
+ return; \
+ } \
+}
+
+/*****************************************************************************/
+/**
+* @brief This assert macro is to be used for functions that do return a
+* value. This in conjunction with the Xil_AssertWait boolean can be
+* used to accommodate tests so that asserts which fail allow execution
+* to continue.
+*
+* @param Expression: expression to be evaluated. If it evaluates to false,
+* the assert occurs.
+*
+* @return Returns 0 unless the Xil_AssertWait variable is true, in which
+* case no return is made and an infinite loop is entered.
+*
+******************************************************************************/
+#define Xil_AssertNonvoid(Expression) \
+{ \
+ if (Expression) { \
+ Xil_AssertStatus = XIL_ASSERT_NONE; \
+ } else { \
+ Xil_Assert(__FILE__, __LINE__); \
+ Xil_AssertStatus = XIL_ASSERT_OCCURRED; \
+ return 0; \
+ } \
+}
+
+/*****************************************************************************/
+/**
+* @brief Always assert. This assert macro is to be used for void functions.
+* Use for instances where an assert should always occur.
+*
+* @return Returns void unless the Xil_AssertWait variable is true, in which
+* case no return is made and an infinite loop is entered.
+*
+******************************************************************************/
+#define Xil_AssertVoidAlways() \
+{ \
+ Xil_Assert(__FILE__, __LINE__); \
+ Xil_AssertStatus = XIL_ASSERT_OCCURRED; \
+ return; \
+}
+
+/*****************************************************************************/
+/**
+* @brief Always assert. This assert macro is to be used for functions that
+* do return a value. Use for instances where an assert should always
+* occur.
+*
+* @return Returns void unless the Xil_AssertWait variable is true, in which
+* case no return is made and an infinite loop is entered.
+*
+******************************************************************************/
+#define Xil_AssertNonvoidAlways() \
+{ \
+ Xil_Assert(__FILE__, __LINE__); \
+ Xil_AssertStatus = XIL_ASSERT_OCCURRED; \
+ return 0; \
+}
+
+
+#else
+
+#define Xil_AssertVoid(Expression)
+#define Xil_AssertVoidAlways()
+#define Xil_AssertNonvoid(Expression)
+#define Xil_AssertNonvoidAlways()
+
+#endif
+
+/************************** Function Prototypes ******************************/
+
+void Xil_AssertSetCallback(Xil_AssertCallback Routine);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* end of protection macro */
+/**
+* @} End of "addtogroup common_assert_apis".
+*/
diff --git a/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v7_1/src/xil_cache.c b/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v7_1/src/xil_cache.c
new file mode 100644
index 0000000..6905db3
--- /dev/null
+++ b/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v7_1/src/xil_cache.c
@@ -0,0 +1,1635 @@
+/******************************************************************************
+*
+* Copyright (C) 2010 - 2015 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+* THE SOFTWARE.
+*
+*
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xil_cache.c
+*
+* Contains required functions for the ARM cache functionality.
+*
+* <pre>
+* MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ----- ---- -------- -----------------------------------------------
+* 1.00a ecm 01/29/10 First release
+* 1.00a ecm 06/24/10 Moved the L1 and L2 specific function prototypes
+* to xil_cache_mach.h to give access to sophisticated users
+* 3.02a sdm 04/07/11 Updated Flush/InvalidateRange APIs to flush/invalidate
+* L1 and L2 caches in a single loop and used dsb, L2 sync
+* at the end of the loop.
+* 3.04a sdm 01/02/12 Remove redundant dsb/dmb instructions in cache maintenance
+* APIs.
+* 3.07a asa 07/16/12 Corrected the L1 and L2 cache invalidation order.
+* 3.07a sgd 09/18/12 Corrected the L2 cache enable and disable sequence.
+* 3.10a srt 04/18/13 Implemented ARM Erratas. Please refer to file
+* 'xil_errata.h' for errata description
+* 3.10a asa 05/13/13 Modified cache disable APIs. The L2 cache disable
+* operation was being done with L1 Data cache disabled. This is
+* fixed so that L2 cache disable operation happens independent of
+* L1 cache disable operation. This fixes CR #706464.
+* Changes are done to do a L2 cache sync (poll reg7_?cache_?sync).
+* This is done to fix the CR #700542.
+* 3.11a asa 09/23/13 Modified the Xil_DCacheFlushRange and
+* Xil_DCacheInvalidateRange to fix potential issues. Fixed other
+* relevant cache APIs to disable and enable back the interrupts.
+* This fixes CR #663885.
+* 3.11a asa 09/28/13 Made changes for L2 cache sync operation. It is found
+* out that for L2 cache flush/clean/invalidation by cache lines
+* does not need a cache sync as these are atomic nature. Similarly
+* figured out that for complete L2 cache flush/invalidation by way
+* we need to wait for some more time in a loop till the status
+* shows that the cache operation is completed.
+* 4.00 pkp 24/01/14 Modified Xil_DCacheInvalidateRange to fix the bug. Few
+* cache lines were missed to invalidate when unaligned address
+* invalidation was accommodated. That fixes CR #766768.
+* Also in Xil_L1DCacheInvalidate, while invalidating all L1D cache
+* stack memory which contains return address was invalidated. So
+* stack memory was flushed first and then L1D cache is invalidated.
+* This is done to fix CR #763829
+* 4.01 asa 05/09/14 Made changes in cortexa9/xil_cache.c to fix CR# 798230.
+* 4.02 pkp 06/27/14 Added notes to Xil_L1DCacheInvalidateRange function for
+* explanation of CR#785243
+* 5.00 kvn 12/15/14 Xil_L2CacheInvalidate was modified to fix CR# 838835. L2 Cache
+* has stack memory which has return address. Before invalidating
+* cache, stack memory was flushed first and L2 Cache is invalidated.
+* 5.01 pkp 05/12/15 Xil_DCacheInvalidateRange and Xil_DCacheFlushRange is modified
+* to remove unnecessary dsb in the APIs. Instead of using dsb
+* for L2 Cache, L2CacheSync has been used for each L2 cache line
+* and single dsb has been used for L1 cache. Also L2CacheSync is
+* added into Xil_L2CacheInvalidateRange API. Xil_L1DCacheInvalidate
+* and Xil_L2CacheInvalidate APIs are modified to flush the complete
+* stack instead of just System Stack
+* 5.03 pkp 10/07/15 L2 Cache functionalities are avoided for the OpenAMP slave
+* application(when USE_AMP flag is defined for BSP) as master CPU
+* would be utilizing L2 cache for its operation
+* 6.6 mus 12/07/17 Errata 753970 is not applicable for the PL130 cache controller
+* version r0p2, which is present in zynq. So,removed the handling
+* related to same.It fixes CR#989132.
+* 6.6 asa 16/01/18 Changes made in Xil_L1DCacheInvalidate and Xil_L2CacheInvalidate
+* routines to ensure the stack data flushed only when the respective
+* caches are enabled. This fixes CR-992023.
+*
+* </pre>
+*
+******************************************************************************/
+
+/***************************** Include Files *********************************/
+
+#include "xil_cache.h"
+#include "xil_cache_l.h"
+#include "xil_io.h"
+#include "xpseudo_asm.h"
+#include "xparameters.h"
+#include "xreg_cortexa9.h"
+#include "xl2cc.h"
+#include "xil_errata.h"
+#include "xil_exception.h"
+
+/************************** Function Prototypes ******************************/
+
+/************************** Variable Definitions *****************************/
+
+#define IRQ_FIQ_MASK 0xC0U /* Mask IRQ and FIQ interrupts in cpsr */
+
+#ifdef __GNUC__
+ extern s32 _stack_end;
+ extern s32 __undef_stack;
+#endif
+
+#ifndef USE_AMP
+/****************************************************************************
+*
+* Access L2 Debug Control Register.
+*
+* @param Value, value to be written to Debug Control Register.
+*
+* @return None.
+*
+* @note None.
+*
+****************************************************************************/
+#ifdef __GNUC__
+static inline void Xil_L2WriteDebugCtrl(u32 Value)
+#else
+static void Xil_L2WriteDebugCtrl(u32 Value)
+#endif
+{
+#if defined(CONFIG_PL310_ERRATA_588369) || defined(CONFIG_PL310_ERRATA_727915)
+ Xil_Out32(XPS_L2CC_BASEADDR + XPS_L2CC_DEBUG_CTRL_OFFSET, Value);
+#else
+ (void)(Value);
+#endif
+}
+
+/****************************************************************************
+*
+* Perform L2 Cache Sync Operation.
+*
+* @param None.
+*
+* @return None.
+*
+* @note None.
+*
+****************************************************************************/
+#ifdef __GNUC__
+static inline void Xil_L2CacheSync(void)
+#else
+static void Xil_L2CacheSync(void)
+#endif
+{
+ Xil_Out32(XPS_L2CC_BASEADDR + XPS_L2CC_CACHE_SYNC_OFFSET, 0x0U);
+}
+#endif
+/****************************************************************************/
+/**
+* @brief Enable the Data cache.
+*
+* @param None.
+*
+* @return None.
+*
+* @note None.
+*
+****************************************************************************/
+void Xil_DCacheEnable(void)
+{
+ Xil_L1DCacheEnable();
+#ifndef USE_AMP
+ Xil_L2CacheEnable();
+#endif
+}
+
+/****************************************************************************/
+/**
+* @brief Disable the Data cache.
+*
+* @param None.
+*
+* @return None.
+*
+* @note None.
+*
+****************************************************************************/
+void Xil_DCacheDisable(void)
+{
+#ifndef USE_AMP
+ Xil_L2CacheDisable();
+#endif
+ Xil_L1DCacheDisable();
+}
+
+/****************************************************************************/
+/**
+* @brief Invalidate the entire Data cache.
+*
+* @param None.
+*
+* @return None.
+*
+* @note None.
+*
+****************************************************************************/
+void Xil_DCacheInvalidate(void)
+{
+ u32 currmask;
+
+ currmask = mfcpsr();
+ mtcpsr(currmask | IRQ_FIQ_MASK);
+#ifndef USE_AMP
+ Xil_L2CacheInvalidate();
+#endif
+ Xil_L1DCacheInvalidate();
+
+ mtcpsr(currmask);
+}
+
+/*****************************************************************************/
+/**
+* @brief Invalidate a Data cache line. If the byte specified by the address
+* (adr) is cached by the Data cache, the cacheline containing that
+* byte is invalidated. If the cacheline is modified (dirty), the
+* modified contents are lost and are NOT written to the system memory
+* before the line is invalidated.
+*
+* @param adr: 32bit address of the data to be flushed.
+*
+* @return None.
+*
+* @note The bottom 4 bits are set to 0, forced by architecture.
+*
+****************************************************************************/
+void Xil_DCacheInvalidateLine(u32 adr)
+{
+ u32 currmask;
+
+ currmask = mfcpsr();
+ mtcpsr(currmask | IRQ_FIQ_MASK);
+#ifndef USE_AMP
+ Xil_L2CacheInvalidateLine(adr);
+#endif
+ Xil_L1DCacheInvalidateLine(adr);
+
+ mtcpsr(currmask);
+}
+
+
+/*****************************************************************************/
+/**
+* @brief Invalidate the Data cache for the given address range.
+* If the bytes specified by the address range are cached by the Data
+* cache, the cachelines containing those bytes are invalidated. If
+* the cachelines are modified (dirty), the modified contents are lost
+* and NOT written to the system memory before the lines are
+* invalidated.
+*
+* In this function, if start address or end address is not aligned to
+* cache-line, particular cache-line containing unaligned start or end
+* address is flush first and then invalidated the others as
+* invalidating the same unaligned cache line may result into loss of
+* data. This issue raises few possibilities.
+*
+* If the address to be invalidated is not cache-line aligned, the
+* following choices are available:
+* 1. Invalidate the cache line when required and do not bother much
+* for the side effects. Though it sounds good, it can result in
+* hard-to-debug issues. The problem is, if some other variable are
+* allocated in the same cache line and had been recently updated
+* (in cache), the invalidation would result in loss of data.
+* 2. Flush the cache line first. This will ensure that if any other
+* variable present in the same cache line and updated recently are
+* flushed out to memory. Then it can safely be invalidated. Again it
+* sounds good, but this can result in issues. For example, when the
+* invalidation happens in a typical ISR (after a DMA transfer has
+* updated the memory), then flushing the cache line means, losing
+* data that were updated recently before the ISR got invoked.
+*
+* Linux prefers the second one. To have uniform implementation
+* (across standalone and Linux), the second option is implemented.
+* This being the case, following needs to be taken care of:
+* 1. Whenever possible, the addresses must be cache line aligned.
+* Please nore that, not just start address, even the end address must
+* be cache line aligned. If that is taken care of, this will always
+* work.
+* 2. Avoid situations where invalidation has to be done after the
+* data is updated by peripheral/DMA directly into the memory. It is
+* not tough to achieve (may be a bit risky). The common use case to
+* do invalidation is when a DMA happens. Generally for such use
+* cases, buffers can be allocated first and then start the DMA. The
+* practice that needs to be followed here is, immediately after
+* buffer allocation and before starting the DMA, do the invalidation.
+* With this approach, invalidation need not to be done after the DMA
+* transfer is over.
+*
+* This is going to always work if done carefully.
+* However, the concern is, there is no guarantee that invalidate has
+* not needed to be done after DMA is complete. For example, because
+* of some reasons if the first cache line or last cache line
+* (assuming the buffer in question comprises of multiple cache lines)
+* are brought into cache (between the time it is invalidated and DMA
+* completes) because of some speculative prefetching or reading data
+* for a variable present in the same cache line, then we will have to
+* invalidate the cache after DMA is complete.
+*
+*
+* @param adr: 32bit start address of the range to be invalidated.
+* @param len: Length of the range to be invalidated in bytes.
+*
+* @return None.
+*
+* @note None.
+*
+****************************************************************************/
+void Xil_DCacheInvalidateRange(INTPTR adr, u32 len)
+{
+ const u32 cacheline = 32U;
+ u32 end;
+ u32 tempadr = adr;
+ u32 tempend;
+ u32 currmask;
+ volatile u32 *L2CCOffset = (volatile u32 *)(XPS_L2CC_BASEADDR +
+ XPS_L2CC_CACHE_INVLD_PA_OFFSET);
+
+ currmask = mfcpsr();
+ mtcpsr(currmask | IRQ_FIQ_MASK);
+
+ if (len != 0U) {
+ end = tempadr + len;
+ tempend = end;
+ /* Select L1 Data cache in CSSR */
+ mtcp(XREG_CP15_CACHE_SIZE_SEL, 0U);
+
+ if ((tempadr & (cacheline-1U)) != 0U) {
+ tempadr &= (~(cacheline - 1U));
+
+ Xil_L1DCacheFlushLine(tempadr);
+#ifndef USE_AMP
+ /* Disable Write-back and line fills */
+ Xil_L2WriteDebugCtrl(0x3U);
+ Xil_L2CacheFlushLine(tempadr);
+ /* Enable Write-back and line fills */
+ Xil_L2WriteDebugCtrl(0x0U);
+ Xil_L2CacheSync();
+#endif
+ tempadr += cacheline;
+ }
+ if ((tempend & (cacheline-1U)) != 0U) {
+ tempend &= (~(cacheline - 1U));
+
+ Xil_L1DCacheFlushLine(tempend);
+#ifndef USE_AMP
+ /* Disable Write-back and line fills */
+ Xil_L2WriteDebugCtrl(0x3U);
+ Xil_L2CacheFlushLine(tempend);
+ /* Enable Write-back and line fills */
+ Xil_L2WriteDebugCtrl(0x0U);
+ Xil_L2CacheSync();
+#endif
+ }
+
+ while (tempadr < tempend) {
+#ifndef USE_AMP
+ /* Invalidate L2 cache line */
+ *L2CCOffset = tempadr;
+ Xil_L2CacheSync();
+#endif
+
+ /* Invalidate L1 Data cache line */
+#if defined (__GNUC__) || defined (__ICCARM__)
+ asm_cp15_inval_dc_line_mva_poc(tempadr);
+#else
+ { volatile register u32 Reg
+ __asm(XREG_CP15_INVAL_DC_LINE_MVA_POC);
+ Reg = tempadr; }
+#endif
+ tempadr += cacheline;
+ }
+ }
+
+ dsb();
+ mtcpsr(currmask);
+}
+
+/****************************************************************************/
+/**
+* @brief Flush the entire Data cache.
+*
+* @param None.
+*
+* @return None.
+*
+* @note None.
+*
+****************************************************************************/
+void Xil_DCacheFlush(void)
+{
+ u32 currmask;
+
+ currmask = mfcpsr();
+ mtcpsr(currmask | IRQ_FIQ_MASK);
+ Xil_L1DCacheFlush();
+#ifndef USE_AMP
+ Xil_L2CacheFlush();
+#endif
+ mtcpsr(currmask);
+}
+
+
+/****************************************************************************/
+/**
+* @brief Flush a Data cache line. If the byte specified by the address (adr)
+* is cached by the Data cache, the cacheline containing that byte is
+* invalidated. If the cacheline is modified (dirty), the entire
+* contents of the cacheline are written to system memory before the
+* line is invalidated.
+*
+* @param adr: 32bit address of the data to be flushed.
+*
+* @return None.
+*
+* @note The bottom 4 bits are set to 0, forced by architecture.
+*
+****************************************************************************/
+void Xil_DCacheFlushLine(u32 adr)
+{
+ u32 currmask;
+
+ currmask = mfcpsr();
+ mtcpsr(currmask | IRQ_FIQ_MASK);
+ Xil_L1DCacheFlushLine(adr);
+#ifndef USE_AMP
+ /* Disable Write-back and line fills */
+ Xil_L2WriteDebugCtrl(0x3U);
+
+ Xil_L2CacheFlushLine(adr);
+
+ /* Enable Write-back and line fills */
+ Xil_L2WriteDebugCtrl(0x0U);
+ Xil_L2CacheSync();
+#endif
+ mtcpsr(currmask);
+}
+
+/****************************************************************************/
+/**
+* @brief Flush the Data cache for the given address range.
+* If the bytes specified by the address range are cached by the
+* data cache, the cachelines containing those bytes are invalidated.
+* If the cachelines are modified (dirty), they are written to the
+* system memory before the lines are invalidated.
+*
+* @param adr: 32bit start address of the range to be flushed.
+* @param len: Length of the range to be flushed in bytes.
+*
+* @return None.
+*
+* @note None.
+*
+****************************************************************************/
+void Xil_DCacheFlushRange(INTPTR adr, u32 len)
+{
+ u32 LocalAddr = adr;
+ const u32 cacheline = 32U;
+ u32 end;
+ u32 currmask;
+ volatile u32 *L2CCOffset = (volatile u32 *)(XPS_L2CC_BASEADDR +
+ XPS_L2CC_CACHE_INV_CLN_PA_OFFSET);
+
+ currmask = mfcpsr();
+ mtcpsr(currmask | IRQ_FIQ_MASK);
+
+ if (len != 0U) {
+ /* Back the starting address up to the start of a cache line
+ * perform cache operations until adr+len
+ */
+ end = LocalAddr + len;
+ LocalAddr &= ~(cacheline - 1U);
+
+ while (LocalAddr < end) {
+
+ /* Flush L1 Data cache line */
+#if defined (__GNUC__) || defined (__ICCARM__)
+ asm_cp15_clean_inval_dc_line_mva_poc(LocalAddr);
+#else
+ { volatile register u32 Reg
+ __asm(XREG_CP15_CLEAN_INVAL_DC_LINE_MVA_POC);
+ Reg = LocalAddr; }
+#endif
+#ifndef USE_AMP
+ /* Flush L2 cache line */
+ *L2CCOffset = LocalAddr;
+ Xil_L2CacheSync();
+#endif
+ LocalAddr += cacheline;
+ }
+ }
+ dsb();
+ mtcpsr(currmask);
+}
+/****************************************************************************/
+/**
+* @brief Store a Data cache line. If the byte specified by the address (adr)
+* is cached by the Data cache and the cacheline is modified (dirty),
+* the entire contents of the cacheline are written to system memory.
+* After the store completes, the cacheline is marked as unmodified
+* (not dirty).
+*
+* @param adr: 32bit address of the data to be stored.
+*
+* @return None.
+*
+* @note The bottom 4 bits are set to 0, forced by architecture.
+*
+****************************************************************************/
+void Xil_DCacheStoreLine(u32 adr)
+{
+ u32 currmask;
+
+ currmask = mfcpsr();
+ mtcpsr(currmask | IRQ_FIQ_MASK);
+
+ Xil_L1DCacheStoreLine(adr);
+#ifndef USE_AMP
+ Xil_L2CacheStoreLine(adr);
+#endif
+ mtcpsr(currmask);
+}
+
+/***************************************************************************/
+/**
+* @brief Enable the instruction cache.
+*
+* @param None.
+*
+* @return None.
+*
+* @note None.
+*
+****************************************************************************/
+void Xil_ICacheEnable(void)
+{
+ Xil_L1ICacheEnable();
+#ifndef USE_AMP
+ Xil_L2CacheEnable();
+#endif
+}
+
+/***************************************************************************/
+/**
+* @brief Disable the instruction cache.
+*
+* @param None.
+*
+* @return None.
+*
+* @note None.
+*
+****************************************************************************/
+void Xil_ICacheDisable(void)
+{
+#ifndef USE_AMP
+ Xil_L2CacheDisable();
+#endif
+ Xil_L1ICacheDisable();
+}
+
+
+/****************************************************************************/
+/**
+* @brief Invalidate the entire instruction cache.
+*
+* @param None.
+*
+* @return None.
+*
+* @note None.
+*
+****************************************************************************/
+void Xil_ICacheInvalidate(void)
+{
+ u32 currmask;
+
+ currmask = mfcpsr();
+ mtcpsr(currmask | IRQ_FIQ_MASK);
+#ifndef USE_AMP
+ Xil_L2CacheInvalidate();
+#endif
+ Xil_L1ICacheInvalidate();
+
+ mtcpsr(currmask);
+}
+
+/****************************************************************************/
+/**
+* @brief Invalidate an instruction cache line. If the instruction specified
+* by the address is cached by the instruction cache, the cacheline
+* containing that instruction is invalidated.
+*
+* @param adr: 32bit address of the instruction to be invalidated.
+*
+* @return None.
+*
+* @note The bottom 4 bits are set to 0, forced by architecture.
+*
+****************************************************************************/
+void Xil_ICacheInvalidateLine(u32 adr)
+{
+ u32 currmask;
+
+ currmask = mfcpsr();
+ mtcpsr(currmask | IRQ_FIQ_MASK);
+#ifndef USE_AMP
+ Xil_L2CacheInvalidateLine(adr);
+#endif
+ Xil_L1ICacheInvalidateLine(adr);
+ mtcpsr(currmask);
+}
+
+/****************************************************************************/
+/**
+* @brief Invalidate the instruction cache for the given address range.
+* If the instructions specified by the address range are cached by
+* the instrunction cache, the cachelines containing those
+* instructions are invalidated.
+*
+* @param adr: 32bit start address of the range to be invalidated.
+* @param len: Length of the range to be invalidated in bytes.
+*
+* @return None.
+*
+* @note None.
+*
+****************************************************************************/
+void Xil_ICacheInvalidateRange(INTPTR adr, u32 len)
+{
+ u32 LocalAddr = adr;
+ const u32 cacheline = 32U;
+ u32 end;
+ volatile u32 *L2CCOffset = (volatile u32 *)(XPS_L2CC_BASEADDR +
+ XPS_L2CC_CACHE_INVLD_PA_OFFSET);
+
+ u32 currmask;
+
+ currmask = mfcpsr();
+ mtcpsr(currmask | IRQ_FIQ_MASK);
+ if (len != 0U) {
+ /* Back the starting address up to the start of a cache line
+ * perform cache operations until adr+len
+ */
+ end = LocalAddr + len;
+ LocalAddr = LocalAddr & ~(cacheline - 1U);
+
+ /* Select cache L0 I-cache in CSSR */
+ mtcp(XREG_CP15_CACHE_SIZE_SEL, 1U);
+
+ while (LocalAddr < end) {
+#ifndef USE_AMP
+ /* Invalidate L2 cache line */
+ *L2CCOffset = LocalAddr;
+ dsb();
+#endif
+
+ /* Invalidate L1 I-cache line */
+#if defined (__GNUC__) || defined (__ICCARM__)
+ asm_cp15_inval_ic_line_mva_pou(LocalAddr);
+#else
+ { volatile register u32 Reg
+ __asm(XREG_CP15_INVAL_IC_LINE_MVA_POU);
+ Reg = LocalAddr; }
+#endif
+
+ LocalAddr += cacheline;
+ }
+ }
+
+ /* Wait for L1 and L2 invalidate to complete */
+ dsb();
+ mtcpsr(currmask);
+}
+
+/****************************************************************************/
+/**
+* @brief Enable the level 1 Data cache.
+*
+* @param None.
+*
+* @return None.
+*
+* @note None.
+*
+****************************************************************************/
+void Xil_L1DCacheEnable(void)
+{
+ register u32 CtrlReg;
+
+ /* enable caches only if they are disabled */
+#ifdef __GNUC__
+ CtrlReg = mfcp(XREG_CP15_SYS_CONTROL);
+#elif defined (__ICCARM__)
+ mfcp(XREG_CP15_SYS_CONTROL, CtrlReg);
+#else
+ { volatile register u32 Reg __asm(XREG_CP15_SYS_CONTROL);
+ CtrlReg = Reg; }
+#endif
+ if ((CtrlReg & (XREG_CP15_CONTROL_C_BIT)) != 0U) {
+ return;
+ }
+
+ /* clean and invalidate the Data cache */
+ Xil_L1DCacheInvalidate();
+
+ /* enable the Data cache */
+ CtrlReg |= (XREG_CP15_CONTROL_C_BIT);
+
+ mtcp(XREG_CP15_SYS_CONTROL, CtrlReg);
+}
+
+/***************************************************************************/
+/**
+* @brief Disable the level 1 Data cache.
+*
+* @param None.
+*
+* @return None.
+*
+* @note None.
+*
+****************************************************************************/
+void Xil_L1DCacheDisable(void)
+{
+ register u32 CtrlReg;
+
+ /* clean and invalidate the Data cache */
+ Xil_L1DCacheFlush();
+
+#ifdef __GNUC__
+ /* disable the Data cache */
+ CtrlReg = mfcp(XREG_CP15_SYS_CONTROL);
+#elif defined (__ICCARM__)
+ mfcp(XREG_CP15_SYS_CONTROL, CtrlReg);
+#else
+ { volatile register u32 Reg __asm(XREG_CP15_SYS_CONTROL);
+ CtrlReg = Reg; }
+#endif
+
+ CtrlReg &= ~(XREG_CP15_CONTROL_C_BIT);
+
+ mtcp(XREG_CP15_SYS_CONTROL, CtrlReg);
+}
+
+/****************************************************************************/
+/**
+* @brief Invalidate the level 1 Data cache.
+*
+* @param None.
+*
+* @return None.
+*
+* @note In Cortex A9, there is no cp instruction for invalidating
+* the whole D-cache. This function invalidates each line by
+* set/way.
+*
+****************************************************************************/
+void Xil_L1DCacheInvalidate(void)
+{
+ register u32 CsidReg, C7Reg;
+ u32 CacheSize, LineSize, NumWays;
+ u32 Way, WayIndex, Set, SetIndex, NumSet;
+ u32 currmask;
+
+#ifdef __GNUC__
+ u32 stack_start,stack_end,stack_size;
+ register u32 CtrlReg;
+#endif
+
+ currmask = mfcpsr();
+ mtcpsr(currmask | IRQ_FIQ_MASK);
+
+#ifdef __GNUC__
+ stack_end = (u32)&_stack_end;
+ stack_start = (u32)&__undef_stack;
+ stack_size=stack_start-stack_end;
+
+ /* Check for the cache status. If cache is enabled, then only
+ * flush stack memory to save return address. If cache is disabled,
+ * don't flush anything as it might result in flushing stale date into
+ * memory which is undesirable.
+ * */
+ CtrlReg = mfcp(XREG_CP15_SYS_CONTROL);
+ if ((CtrlReg & (XREG_CP15_CONTROL_C_BIT)) != 0U) {
+ Xil_DCacheFlushRange(stack_end, stack_size);
+ }
+#endif
+
+ /* Select cache level 0 and D cache in CSSR */
+ mtcp(XREG_CP15_CACHE_SIZE_SEL, 0U);
+
+#ifdef __GNUC__
+ CsidReg = mfcp(XREG_CP15_CACHE_SIZE_ID);
+#elif defined (__ICCARM__)
+ mfcp(XREG_CP15_CACHE_SIZE_ID, CsidReg);
+#else
+ { volatile register u32 Reg __asm(XREG_CP15_CACHE_SIZE_ID);
+ CsidReg = Reg; }
+#endif
+ /* Determine Cache Size */
+ CacheSize = (CsidReg >> 13U) & 0x1FFU;
+ CacheSize +=1U;
+ CacheSize *=128U; /* to get number of bytes */
+
+ /* Number of Ways */
+ NumWays = (CsidReg & 0x3ffU) >> 3U;
+ NumWays += 1U;
+
+ /* Get the cacheline size, way size, index size from csidr */
+ LineSize = (CsidReg & 0x07U) + 4U;
+
+ NumSet = CacheSize/NumWays;
+ NumSet /= (0x00000001U << LineSize);
+
+ Way = 0U;
+ Set = 0U;
+
+ /* Invalidate all the cachelines */
+ for (WayIndex =0U; WayIndex < NumWays; WayIndex++) {
+ for (SetIndex =0U; SetIndex < NumSet; SetIndex++) {
+ C7Reg = Way | Set;
+
+ /* Invalidate by Set/Way */
+#if defined (__GNUC__) || defined (__ICCARM__)
+ asm_cp15_inval_dc_line_sw(C7Reg);
+#else
+ /*mtcp(XREG_CP15_INVAL_DC_LINE_SW, C7Reg), */
+ { volatile register u32 Reg
+ __asm(XREG_CP15_INVAL_DC_LINE_SW);
+ Reg = C7Reg; }
+#endif
+ Set += (0x00000001U << LineSize);
+ }
+ Set=0U;
+ Way += 0x40000000U;
+ }
+
+ /* Wait for L1 invalidate to complete */
+ dsb();
+ mtcpsr(currmask);
+}
+
+/****************************************************************************/
+/**
+* @brief Invalidate a level 1 Data cache line. If the byte specified by the
+* address (Addr) is cached by the Data cache, the cacheline
+* containing that byte is invalidated. If the cacheline is modified
+* (dirty), the modified contents are lost and are NOT written to
+* system memory before the line is invalidated.
+*
+* @param adr: 32bit address of the data to be invalidated.
+*
+* @return None.
+*
+* @note The bottom 5 bits are set to 0, forced by architecture.
+*
+****************************************************************************/
+void Xil_L1DCacheInvalidateLine(u32 adr)
+{
+ mtcp(XREG_CP15_CACHE_SIZE_SEL, 0U);
+ mtcp(XREG_CP15_INVAL_DC_LINE_MVA_POC, (adr & (~0x1FU)));
+
+ /* Wait for L1 invalidate to complete */
+ dsb();
+}
+
+/****************************************************************************/
+/**
+* @brief Invalidate the level 1 Data cache for the given address range.
+* If the bytes specified by the address range are cached by the Data
+* cache, the cachelines containing those bytes are invalidated. If the
+* cachelines are modified (dirty), the modified contents are lost and
+* NOT written to the system memory before the lines are invalidated.
+*
+* @param adr: 32bit start address of the range to be invalidated.
+* @param len: Length of the range to be invalidated in bytes.
+*
+* @return None.
+*
+* @note None.
+*
+****************************************************************************/
+void Xil_L1DCacheInvalidateRange(u32 adr, u32 len)
+{
+ u32 LocalAddr = adr;
+ const u32 cacheline = 32U;
+ u32 end;
+ u32 currmask;
+
+ currmask = mfcpsr();
+ mtcpsr(currmask | IRQ_FIQ_MASK);
+
+ if (len != 0U) {
+ /* Back the starting address up to the start of a cache line
+ * perform cache operations until adr+len
+ */
+ end = LocalAddr + len;
+ LocalAddr = LocalAddr & ~(cacheline - 1U);
+
+ /* Select cache L0 D-cache in CSSR */
+ mtcp(XREG_CP15_CACHE_SIZE_SEL, 0);
+
+ while (LocalAddr < end) {
+
+#if defined (__GNUC__) || defined (__ICCARM__)
+ asm_cp15_inval_dc_line_mva_poc(LocalAddr);
+#else
+ { volatile register u32 Reg
+ __asm(XREG_CP15_INVAL_DC_LINE_MVA_POC);
+ Reg = LocalAddr; }
+#endif
+ LocalAddr += cacheline;
+ }
+ }
+
+ /* Wait for L1 invalidate to complete */
+ dsb();
+ mtcpsr(currmask);
+}
+
+/****************************************************************************/
+/**
+* @brief Flush the level 1 Data cache.
+*
+* @param None.
+*
+* @return None.
+*
+* @note In Cortex A9, there is no cp instruction for flushing
+* the whole D-cache. Need to flush each line.
+*
+****************************************************************************/
+void Xil_L1DCacheFlush(void)
+{
+ register u32 CsidReg, C7Reg;
+ u32 CacheSize, LineSize, NumWays;
+ u32 Way;
+ u32 WayIndex, Set, SetIndex, NumSet;
+ u32 currmask;
+
+ currmask = mfcpsr();
+ mtcpsr(currmask | IRQ_FIQ_MASK);
+
+ /* Select cache level 0 and D cache in CSSR */
+ mtcp(XREG_CP15_CACHE_SIZE_SEL, 0);
+
+#ifdef __GNUC__
+ CsidReg = mfcp(XREG_CP15_CACHE_SIZE_ID);
+#elif defined (__ICCARM__)
+ mfcp(XREG_CP15_CACHE_SIZE_ID, CsidReg);
+#else
+ { volatile register u32 Reg __asm(XREG_CP15_CACHE_SIZE_ID);
+ CsidReg = Reg; }
+#endif
+
+ /* Determine Cache Size */
+
+ CacheSize = (CsidReg >> 13U) & 0x1FFU;
+ CacheSize +=1U;
+ CacheSize *=128U; /* to get number of bytes */
+
+ /* Number of Ways */
+ NumWays = (CsidReg & 0x3ffU) >> 3U;
+ NumWays += 1U;
+
+ /* Get the cacheline size, way size, index size from csidr */
+ LineSize = (CsidReg & 0x07U) + 4U;
+
+ NumSet = CacheSize/NumWays;
+ NumSet /= (0x00000001U << LineSize);
+
+ Way = 0U;
+ Set = 0U;
+
+ /* Invalidate all the cachelines */
+ for (WayIndex =0U; WayIndex < NumWays; WayIndex++) {
+ for (SetIndex =0U; SetIndex < NumSet; SetIndex++) {
+ C7Reg = Way | Set;
+ /* Flush by Set/Way */
+
+#if defined (__GNUC__) || defined (__ICCARM__)
+ asm_cp15_clean_inval_dc_line_sw(C7Reg);
+#else
+ { volatile register u32 Reg
+ __asm(XREG_CP15_CLEAN_INVAL_DC_LINE_SW);
+ Reg = C7Reg; }
+#endif
+ Set += (0x00000001U << LineSize);
+ }
+ Set = 0U;
+ Way += 0x40000000U;
+ }
+
+ /* Wait for L1 flush to complete */
+ dsb();
+ mtcpsr(currmask);
+}
+
+/****************************************************************************/
+/**
+* @brief Flush a level 1 Data cache line. If the byte specified by the
+* address (adr) is cached by the Data cache, the cacheline containing
+* that byte is invalidated. If the cacheline is modified (dirty), the
+* entire contents of the cacheline are written to system memory
+* before the line is invalidated.
+*
+* @param adr: 32bit address of the data to be flushed.
+*
+* @return None.
+*
+* @note The bottom 5 bits are set to 0, forced by architecture.
+*
+****************************************************************************/
+void Xil_L1DCacheFlushLine(u32 adr)
+{
+ mtcp(XREG_CP15_CACHE_SIZE_SEL, 0U);
+ mtcp(XREG_CP15_CLEAN_INVAL_DC_LINE_MVA_POC, (adr & (~0x1FU)));
+
+ /* Wait for L1 flush to complete */
+ dsb();
+}
+
+/****************************************************************************/
+/**
+* @brief Flush the level 1 Data cache for the given address range.
+* If the bytes specified by the address range are cached by the Data
+* cache, the cacheline containing those bytes are invalidated. If the
+* cachelines are modified (dirty), they are written to system memory
+* before the lines are invalidated.
+*
+* @param adr: 32bit start address of the range to be flushed.
+* @param len: Length of the range to be flushed in bytes.
+*
+* @return None.
+*
+* @note None.
+*
+****************************************************************************/
+void Xil_L1DCacheFlushRange(u32 adr, u32 len)
+{
+ u32 LocalAddr = adr;
+ const u32 cacheline = 32U;
+ u32 end;
+ u32 currmask;
+
+ currmask = mfcpsr();
+ mtcpsr(currmask | IRQ_FIQ_MASK);
+
+ if (len != 0U) {
+ /* Back the starting address up to the start of a cache line
+ * perform cache operations until adr+len
+ */
+ end = LocalAddr + len;
+ LocalAddr = LocalAddr & ~(cacheline - 1U);
+
+ /* Select cache L0 D-cache in CSSR */
+ mtcp(XREG_CP15_CACHE_SIZE_SEL, 0U);
+
+ while (LocalAddr < end) {
+
+#if defined (__GNUC__) || defined (__ICCARM__)
+ asm_cp15_clean_inval_dc_line_mva_poc(LocalAddr);
+#else
+ { volatile register u32 Reg
+ __asm(XREG_CP15_CLEAN_INVAL_DC_LINE_MVA_POC);
+ Reg = LocalAddr; }
+#endif
+ LocalAddr += cacheline;
+ }
+ }
+
+ /* Wait for L1 flush to complete */
+ dsb();
+ mtcpsr(currmask);
+}
+
+/****************************************************************************/
+/**
+* @brief Store a level 1 Data cache line. If the byte specified by the
+* address (adr) is cached by the Data cache and the cacheline is
+* modified (dirty), the entire contents of the cacheline are written
+* to system memory. After the store completes, the cacheline is
+* marked as unmodified (not dirty).
+*
+* @param Address to be stored.
+*
+* @return None.
+*
+* @note The bottom 5 bits are set to 0, forced by architecture.
+*
+****************************************************************************/
+void Xil_L1DCacheStoreLine(u32 adr)
+{
+ mtcp(XREG_CP15_CACHE_SIZE_SEL, 0U);
+ mtcp(XREG_CP15_CLEAN_DC_LINE_MVA_POC, (adr & (~0x1FU)));
+
+ /* Wait for L1 store to complete */
+ dsb();
+}
+
+
+/****************************************************************************/
+/**
+* @brief Enable the level 1 instruction cache.
+*
+* @param None.
+*
+* @return None.
+*
+* @note None.
+*
+****************************************************************************/
+void Xil_L1ICacheEnable(void)
+{
+ register u32 CtrlReg;
+
+ /* enable caches only if they are disabled */
+#ifdef __GNUC__
+ CtrlReg = mfcp(XREG_CP15_SYS_CONTROL);
+#elif defined (__ICCARM__)
+ mfcp(XREG_CP15_SYS_CONTROL, CtrlReg);
+#else
+ { volatile register u32 Reg __asm(XREG_CP15_SYS_CONTROL);
+ CtrlReg = Reg; }
+#endif
+ if ((CtrlReg & (XREG_CP15_CONTROL_I_BIT)) != 0U) {
+ return;
+ }
+
+ /* invalidate the instruction cache */
+ mtcp(XREG_CP15_INVAL_IC_POU, 0U);
+
+ /* enable the instruction cache */
+ CtrlReg |= (XREG_CP15_CONTROL_I_BIT);
+
+ mtcp(XREG_CP15_SYS_CONTROL, CtrlReg);
+}
+
+/****************************************************************************/
+/**
+* @brief Disable level 1 the instruction cache.
+*
+* @param None.
+*
+* @return None.
+*
+* @note None.
+*
+****************************************************************************/
+void Xil_L1ICacheDisable(void)
+{
+ register u32 CtrlReg;
+
+ dsb();
+
+ /* invalidate the instruction cache */
+ mtcp(XREG_CP15_INVAL_IC_POU, 0U);
+
+ /* disable the instruction cache */
+#ifdef __GNUC__
+ CtrlReg = mfcp(XREG_CP15_SYS_CONTROL);
+#elif defined (__ICCARM__)
+ mfcp(XREG_CP15_SYS_CONTROL, CtrlReg);
+#else
+ { volatile register u32 Reg __asm(XREG_CP15_SYS_CONTROL);
+ CtrlReg = Reg; }
+#endif
+ CtrlReg &= ~(XREG_CP15_CONTROL_I_BIT);
+
+ mtcp(XREG_CP15_SYS_CONTROL, CtrlReg);
+}
+
+/****************************************************************************/
+/**
+* @brief Invalidate the entire level 1 instruction cache.
+*
+* @param None.
+*
+* @return None.
+*
+* @note None.
+*
+****************************************************************************/
+void Xil_L1ICacheInvalidate(void)
+{
+ mtcp(XREG_CP15_CACHE_SIZE_SEL, 1U);
+ /* invalidate the instruction cache */
+ mtcp(XREG_CP15_INVAL_IC_POU, 0U);
+
+ /* Wait for L1 invalidate to complete */
+ dsb();
+}
+
+/****************************************************************************/
+/**
+* @brief Invalidate a level 1 instruction cache line. If the instruction
+* specified by the address is cached by the instruction cache, the
+* cacheline containing that instruction is invalidated.
+*
+* @param adr: 32bit address of the instruction to be invalidated.
+*
+* @return None.
+*
+* @note The bottom 5 bits are set to 0, forced by architecture.
+*
+****************************************************************************/
+void Xil_L1ICacheInvalidateLine(u32 adr)
+{
+ mtcp(XREG_CP15_CACHE_SIZE_SEL, 1U);
+ mtcp(XREG_CP15_INVAL_IC_LINE_MVA_POU, (adr & (~0x1FU)));
+
+ /* Wait for L1 invalidate to complete */
+ dsb();
+}
+
+/****************************************************************************/
+/**
+* @brief Invalidate the level 1 instruction cache for the given address
+* range. If the instrucions specified by the address range are cached
+* by the instruction cache, the cacheline containing those bytes are
+* invalidated.
+*
+* @param adr: 32bit start address of the range to be invalidated.
+* @param len: Length of the range to be invalidated in bytes.
+*
+* @return None.
+*
+* @note None.
+*
+****************************************************************************/
+void Xil_L1ICacheInvalidateRange(u32 adr, u32 len)
+{
+ u32 LocalAddr = adr;
+ const u32 cacheline = 32U;
+ u32 end;
+ u32 currmask;
+
+ currmask = mfcpsr();
+ mtcpsr(currmask | IRQ_FIQ_MASK);
+
+ if (len != 0U) {
+ /* Back the starting address up to the start of a cache line
+ * perform cache operations until adr+len
+ */
+ end = LocalAddr + len;
+ LocalAddr = LocalAddr & ~(cacheline - 1U);
+
+ /* Select cache L0 I-cache in CSSR */
+ mtcp(XREG_CP15_CACHE_SIZE_SEL, 1U);
+
+ while (LocalAddr < end) {
+
+#if defined (__GNUC__) || defined (__ICCARM__)
+ asm_cp15_inval_ic_line_mva_pou(LocalAddr);
+#else
+ { volatile register u32 Reg
+ __asm(XREG_CP15_INVAL_IC_LINE_MVA_POU);
+ Reg = LocalAddr; }
+#endif
+ LocalAddr += cacheline;
+ }
+ }
+
+ /* Wait for L1 invalidate to complete */
+ dsb();
+ mtcpsr(currmask);
+}
+
+#ifndef USE_AMP
+/****************************************************************************/
+/**
+* @brief Enable the L2 cache.
+*
+* @param None.
+*
+* @return None.
+*
+* @note None.
+*
+****************************************************************************/
+void Xil_L2CacheEnable(void)
+{
+ register u32 L2CCReg;
+
+ L2CCReg = Xil_In32(XPS_L2CC_BASEADDR + XPS_L2CC_CNTRL_OFFSET);
+
+ /* only enable if L2CC is currently disabled */
+ if ((L2CCReg & 0x01U) == 0U) {
+ /* set up the way size and latencies */
+ L2CCReg = Xil_In32(XPS_L2CC_BASEADDR +
+ XPS_L2CC_AUX_CNTRL_OFFSET);
+ L2CCReg &= XPS_L2CC_AUX_REG_ZERO_MASK;
+ L2CCReg |= XPS_L2CC_AUX_REG_DEFAULT_MASK;
+ Xil_Out32(XPS_L2CC_BASEADDR + XPS_L2CC_AUX_CNTRL_OFFSET,
+ L2CCReg);
+ Xil_Out32(XPS_L2CC_BASEADDR + XPS_L2CC_TAG_RAM_CNTRL_OFFSET,
+ XPS_L2CC_TAG_RAM_DEFAULT_MASK);
+ Xil_Out32(XPS_L2CC_BASEADDR + XPS_L2CC_DATA_RAM_CNTRL_OFFSET,
+ XPS_L2CC_DATA_RAM_DEFAULT_MASK);
+
+ /* Clear the pending interrupts */
+ L2CCReg = Xil_In32(XPS_L2CC_BASEADDR +
+ XPS_L2CC_ISR_OFFSET);
+ Xil_Out32(XPS_L2CC_BASEADDR + XPS_L2CC_IAR_OFFSET, L2CCReg);
+
+ Xil_L2CacheInvalidate();
+ /* Enable the L2CC */
+ L2CCReg = Xil_In32(XPS_L2CC_BASEADDR +
+ XPS_L2CC_CNTRL_OFFSET);
+ Xil_Out32(XPS_L2CC_BASEADDR + XPS_L2CC_CNTRL_OFFSET,
+ (L2CCReg | (0x01U)));
+
+ Xil_L2CacheSync();
+ /* synchronize the processor */
+ dsb();
+
+ }
+}
+
+/****************************************************************************/
+/**
+* @brief Disable the L2 cache.
+*
+* @param None.
+*
+* @return None.
+*
+* @note None.
+*
+****************************************************************************/
+void Xil_L2CacheDisable(void)
+{
+ register u32 L2CCReg;
+
+ L2CCReg = Xil_In32(XPS_L2CC_BASEADDR + XPS_L2CC_CNTRL_OFFSET);
+
+ if((L2CCReg & 0x1U) != 0U) {
+
+ /* Clean and Invalidate L2 Cache */
+ Xil_L2CacheFlush();
+
+ /* Disable the L2CC */
+ L2CCReg = Xil_In32(XPS_L2CC_BASEADDR + XPS_L2CC_CNTRL_OFFSET);
+ Xil_Out32(XPS_L2CC_BASEADDR + XPS_L2CC_CNTRL_OFFSET,
+ (L2CCReg & (~0x01U)));
+ /* Wait for the cache operations to complete */
+
+ dsb();
+ }
+}
+
+/*****************************************************************************/
+/**
+* @brief Invalidate the entire level 2 cache.
+*
+* @param None.
+*
+* @return None.
+*
+* @note None.
+*
+****************************************************************************/
+void Xil_L2CacheInvalidate(void)
+{
+ #ifdef __GNUC__
+ u32 stack_start,stack_end,stack_size;
+ register u32 L2CCReg;
+ stack_end = (u32)&_stack_end;
+ stack_start = (u32)&__undef_stack;
+ stack_size=stack_start-stack_end;
+
+ /* Check for the cache status. If cache is enabled, then only
+ * flush stack memory to save return address. If cache is disabled,
+ * don't flush anything as it might result in flushing stale date into
+ * memory which is undesirable.
+ */
+ L2CCReg = Xil_In32(XPS_L2CC_BASEADDR + XPS_L2CC_CNTRL_OFFSET);
+ if ((L2CCReg & 0x01U) != 0U) {
+ /*Flush stack memory to save return address*/
+ Xil_DCacheFlushRange(stack_end, stack_size);
+ }
+
+ #endif
+ u32 ResultDCache;
+ /* Invalidate the caches */
+ Xil_Out32(XPS_L2CC_BASEADDR + XPS_L2CC_CACHE_INVLD_WAY_OFFSET,
+ 0x0000FFFFU);
+ ResultDCache = Xil_In32(XPS_L2CC_BASEADDR + XPS_L2CC_CACHE_INVLD_WAY_OFFSET)
+ & 0x0000FFFFU;
+ while(ResultDCache != (u32)0U) {
+ ResultDCache = Xil_In32(XPS_L2CC_BASEADDR + XPS_L2CC_CACHE_INVLD_WAY_OFFSET)
+ & 0x0000FFFFU;
+ }
+
+ /* Wait for the invalidate to complete */
+ Xil_L2CacheSync();
+
+ /* synchronize the processor */
+ dsb();
+}
+
+/*****************************************************************************/
+/**
+* @brief Invalidate a level 2 cache line. If the byte specified by the
+* address (adr) is cached by the Data cache, the cacheline containing
+* that byte is invalidated. If the cacheline is modified (dirty),
+* the modified contents are lost and are NOT written to system memory
+* before the line is invalidated.
+*
+* @param adr: 32bit address of the data/instruction to be invalidated.
+*
+* @return None.
+*
+* @note The bottom 4 bits are set to 0, forced by architecture.
+*
+****************************************************************************/
+void Xil_L2CacheInvalidateLine(u32 adr)
+{
+ Xil_Out32(XPS_L2CC_BASEADDR + XPS_L2CC_CACHE_INVLD_PA_OFFSET, (u32)adr);
+ /* synchronize the processor */
+ dsb();
+}
+
+/****************************************************************************/
+/**
+* @brief Invalidate the level 2 cache for the given address range.
+* If the bytes specified by the address range are cached by the L2
+* cache, the cacheline containing those bytes are invalidated. If the
+* cachelines are modified (dirty), the modified contents are lost and
+* are NOT written to system memory before the lines are invalidated.
+*
+* @param adr: 32bit start address of the range to be invalidated.
+* @param len: Length of the range to be invalidated in bytes.
+*
+* @return None.
+*
+* @note None.
+*
+****************************************************************************/
+void Xil_L2CacheInvalidateRange(u32 adr, u32 len)
+{
+ u32 LocalAddr = adr;
+ const u32 cacheline = 32U;
+ u32 end;
+ volatile u32 *L2CCOffset = (volatile u32 *)(XPS_L2CC_BASEADDR +
+ XPS_L2CC_CACHE_INVLD_PA_OFFSET);
+
+ u32 currmask;
+
+ currmask = mfcpsr();
+ mtcpsr(currmask | IRQ_FIQ_MASK);
+
+ if (len != 0U) {
+ /* Back the starting address up to the start of a cache line
+ * perform cache operations until adr+len
+ */
+ end = LocalAddr + len;
+ LocalAddr = LocalAddr & ~(cacheline - 1U);
+
+ /* Disable Write-back and line fills */
+ Xil_L2WriteDebugCtrl(0x3U);
+
+ while (LocalAddr < end) {
+ *L2CCOffset = LocalAddr;
+ Xil_L2CacheSync();
+ LocalAddr += cacheline;
+ }
+
+ /* Enable Write-back and line fills */
+ Xil_L2WriteDebugCtrl(0x0U);
+ }
+
+ /* synchronize the processor */
+ dsb();
+ mtcpsr(currmask);
+}
+
+/****************************************************************************/
+/**
+* @brief Flush the entire level 2 cache.
+*
+* @param None.
+*
+* @return None.
+*
+* @note None.
+*
+****************************************************************************/
+void Xil_L2CacheFlush(void)
+{
+ u32 ResultL2Cache;
+
+ /* Flush the caches */
+
+ /* Disable Write-back and line fills */
+ Xil_L2WriteDebugCtrl(0x3U);
+
+ Xil_Out32(XPS_L2CC_BASEADDR + XPS_L2CC_CACHE_INV_CLN_WAY_OFFSET,
+ 0x0000FFFFU);
+ ResultL2Cache = Xil_In32(XPS_L2CC_BASEADDR + XPS_L2CC_CACHE_INV_CLN_WAY_OFFSET)
+ & 0x0000FFFFU;
+
+ while(ResultL2Cache != (u32)0U) {
+ ResultL2Cache = Xil_In32(XPS_L2CC_BASEADDR + XPS_L2CC_CACHE_INV_CLN_WAY_OFFSET)
+ & 0x0000FFFFU;
+ }
+
+ Xil_L2CacheSync();
+ /* Enable Write-back and line fills */
+ Xil_L2WriteDebugCtrl(0x0U);
+
+ /* synchronize the processor */
+ dsb();
+}
+
+/****************************************************************************/
+/**
+* @brief Flush a level 2 cache line. If the byte specified by the address
+* (adr) is cached by the L2 cache, the cacheline containing that
+* byte is invalidated. If the cacheline is modified (dirty), the
+* entire contents of the cacheline are written to system memory
+* before the line is invalidated.
+*
+* @param adr: 32bit address of the data/instruction to be flushed.
+*
+* @return None.
+*
+* @note The bottom 4 bits are set to 0, forced by architecture.
+*
+****************************************************************************/
+void Xil_L2CacheFlushLine(u32 adr)
+{
+#ifdef CONFIG_PL310_ERRATA_588369
+ Xil_Out32(XPS_L2CC_BASEADDR + XPS_L2CC_CACHE_CLEAN_PA_OFFSET, adr);
+ Xil_Out32(XPS_L2CC_BASEADDR + XPS_L2CC_CACHE_INVLD_PA_OFFSET, adr);
+#else
+ Xil_Out32(XPS_L2CC_BASEADDR + XPS_L2CC_CACHE_INV_CLN_PA_OFFSET, adr);
+#endif
+ /* synchronize the processor */
+ dsb();
+}
+
+/****************************************************************************/
+/**
+* @brief Flush the level 2 cache for the given address range.
+* If the bytes specified by the address range are cached by the L2
+* cache, the cacheline containing those bytes are invalidated. If the
+* cachelines are modified (dirty), they are written to the system
+* memory before the lines are invalidated.
+*
+* @param adr: 32bit start address of the range to be flushed.
+* @param len: Length of the range to be flushed in bytes.
+*
+* @return None.
+*
+* @note None.
+*
+****************************************************************************/
+void Xil_L2CacheFlushRange(u32 adr, u32 len)
+{
+ u32 LocalAddr = adr;
+ const u32 cacheline = 32U;
+ u32 end;
+ volatile u32 *L2CCOffset = (volatile u32 *)(XPS_L2CC_BASEADDR +
+ XPS_L2CC_CACHE_INV_CLN_PA_OFFSET);
+
+ u32 currmask;
+
+ currmask = mfcpsr();
+ mtcpsr(currmask | IRQ_FIQ_MASK);
+ if (len != 0U) {
+ /* Back the starting address up to the start of a cache line
+ * perform cache operations until adr+len
+ */
+ end = LocalAddr + len;
+ LocalAddr = LocalAddr & ~(cacheline - 1U);
+
+ /* Disable Write-back and line fills */
+ Xil_L2WriteDebugCtrl(0x3U);
+
+ while (LocalAddr < end) {
+ *L2CCOffset = LocalAddr;
+ Xil_L2CacheSync();
+ LocalAddr += cacheline;
+ }
+
+ /* Enable Write-back and line fills */
+ Xil_L2WriteDebugCtrl(0x0U);
+ }
+ /* synchronize the processor */
+ dsb();
+ mtcpsr(currmask);
+}
+
+/****************************************************************************/
+/**
+* @brief Store a level 2 cache line. If the byte specified by the address
+* (adr) is cached by the L2 cache and the cacheline is modified
+* (dirty), the entire contents of the cacheline are written to
+* system memory. After the store completes, the cacheline is marked
+* as unmodified (not dirty).
+*
+* @param adr: 32bit address of the data/instruction to be stored.
+*
+* @return None.
+*
+* @note The bottom 4 bits are set to 0, forced by architecture.
+*
+****************************************************************************/
+void Xil_L2CacheStoreLine(u32 adr)
+{
+ Xil_Out32(XPS_L2CC_BASEADDR + XPS_L2CC_CACHE_CLEAN_PA_OFFSET, adr);
+ /* synchronize the processor */
+ dsb();
+}
+#endif
diff --git a/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v7_1/src/xil_cache.h b/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v7_1/src/xil_cache.h
new file mode 100644
index 0000000..6304a00
--- /dev/null
+++ b/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v7_1/src/xil_cache.h
@@ -0,0 +1,116 @@
+/******************************************************************************
+*
+* Copyright (C) 2010 - 2018 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+* THE SOFTWARE.
+*
+*
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xil_cache.h
+*
+* @addtogroup a9_cache_apis Cortex A9 Processor Cache Functions
+*
+* Cache functions provide access to cache related operations such as flush
+* and invalidate for instruction and data caches. It gives option to perform
+* the cache operations on a single cacheline, a range of memory and an entire
+* cache.
+*
+* @{
+*
+* <pre>
+* MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ----- ---- -------- -----------------------------------------------
+* 1.00a ecm 01/29/10 First release
+* 3.04a sdm 01/02/12 Remove redundant dsb/dmb instructions in cache maintenance
+* APIs.
+* 6.8 aru 09/06/18 Removed compilation warnings for ARMCC toolchain.
+* </pre>
+*
+******************************************************************************/
+#ifndef XIL_CACHE_H
+#define XIL_CACHE_H
+
+#include "xil_types.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#ifdef __GNUC__
+
+#define asm_cp15_inval_dc_line_mva_poc(param) __asm__ __volatile__("mcr " \
+ XREG_CP15_INVAL_DC_LINE_MVA_POC :: "r" (param));
+
+#define asm_cp15_clean_inval_dc_line_mva_poc(param) __asm__ __volatile__("mcr " \
+ XREG_CP15_CLEAN_INVAL_DC_LINE_MVA_POC :: "r" (param));
+
+#define asm_cp15_inval_ic_line_mva_pou(param) __asm__ __volatile__("mcr " \
+ XREG_CP15_INVAL_IC_LINE_MVA_POU :: "r" (param));
+
+#define asm_cp15_inval_dc_line_sw(param) __asm__ __volatile__("mcr " \
+ XREG_CP15_INVAL_DC_LINE_SW :: "r" (param));
+
+#define asm_cp15_clean_inval_dc_line_sw(param) __asm__ __volatile__("mcr " \
+ XREG_CP15_CLEAN_INVAL_DC_LINE_SW :: "r" (param));
+
+#elif defined (__ICCARM__)
+
+#define asm_cp15_inval_dc_line_mva_poc(param) __asm volatile ("mcr " \
+ XREG_CP15_INVAL_DC_LINE_MVA_POC :: "r" (param));
+
+#define asm_cp15_clean_inval_dc_line_mva_poc(param) __asm volatile ("mcr " \
+ XREG_CP15_CLEAN_INVAL_DC_LINE_MVA_POC :: "r" (param));
+
+#define asm_cp15_inval_ic_line_mva_pou(param) __asm volatile ("mcr " \
+ XREG_CP15_INVAL_IC_LINE_MVA_POU :: "r" (param));
+
+#define asm_cp15_inval_dc_line_sw(param) __asm volatile ("mcr " \
+ XREG_CP15_INVAL_DC_LINE_SW :: "r" (param));
+
+#define asm_cp15_clean_inval_dc_line_sw(param) __asm volatile ("mcr " \
+ XREG_CP15_CLEAN_INVAL_DC_LINE_SW :: "r" (param));
+
+#endif
+
+void Xil_DCacheEnable(void);
+void Xil_DCacheDisable(void);
+void Xil_DCacheInvalidate(void);
+void Xil_DCacheInvalidateRange(INTPTR adr, u32 len);
+void Xil_DCacheFlush(void);
+void Xil_DCacheFlushRange(INTPTR adr, u32 len);
+
+void Xil_ICacheEnable(void);
+void Xil_ICacheDisable(void);
+void Xil_ICacheInvalidate(void);
+void Xil_ICacheInvalidateRange(INTPTR adr, u32 len);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
+/**
+* @} End of "addtogroup a9_cache_apis".
+*/
diff --git a/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v7_1/src/xil_cache_l.h b/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v7_1/src/xil_cache_l.h
new file mode 100644
index 0000000..60601b2
--- /dev/null
+++ b/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v7_1/src/xil_cache_l.h
@@ -0,0 +1,95 @@
+/******************************************************************************
+*
+* Copyright (C) 2010 - 2018 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+* THE SOFTWARE.
+*
+*
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xil_cache_l.h
+*
+* Contains L1 and L2 specific functions for the ARM cache functionality
+* used by xcache.c. This functionality is being made available here for
+* more sophisticated users.
+*
+* @addtogroup a9_cache_apis
+* @{
+* <pre>
+* MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ----- ---- -------- -----------------------------------------------
+* 1.00a ecm 01/24/10 First release
+* 6.8 aru 09/06/18 Removed compilation warnings for ARMCC toolchain.
+* </pre>
+*
+******************************************************************************/
+#ifndef XIL_CACHE_MACH_H
+#define XIL_CACHE_MACH_H
+
+#include "xil_types.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/************************** Function Prototypes ******************************/
+
+void Xil_DCacheInvalidateLine(u32 adr);
+void Xil_DCacheFlushLine(u32 adr);
+void Xil_DCacheStoreLine(u32 adr);
+void Xil_ICacheInvalidateLine(u32 adr);
+
+void Xil_L1DCacheEnable(void);
+void Xil_L1DCacheDisable(void);
+void Xil_L1DCacheInvalidate(void);
+void Xil_L1DCacheInvalidateLine(u32 adr);
+void Xil_L1DCacheInvalidateRange(u32 adr, u32 len);
+void Xil_L1DCacheFlush(void);
+void Xil_L1DCacheFlushLine(u32 adr);
+void Xil_L1DCacheFlushRange(u32 adr, u32 len);
+void Xil_L1DCacheStoreLine(u32 adr);
+
+void Xil_L1ICacheEnable(void);
+void Xil_L1ICacheDisable(void);
+void Xil_L1ICacheInvalidate(void);
+void Xil_L1ICacheInvalidateLine(u32 adr);
+void Xil_L1ICacheInvalidateRange(u32 adr, u32 len);
+
+void Xil_L2CacheEnable(void);
+void Xil_L2CacheDisable(void);
+void Xil_L2CacheInvalidate(void);
+void Xil_L2CacheInvalidateLine(u32 adr);
+void Xil_L2CacheInvalidateRange(u32 adr, u32 len);
+void Xil_L2CacheFlush(void);
+void Xil_L2CacheFlushLine(u32 adr);
+void Xil_L2CacheFlushRange(u32 adr, u32 len);
+void Xil_L2CacheStoreLine(u32 adr);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
+/**
+* @} End of "addtogroup a9_cache_apis".
+*/
diff --git a/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v7_1/src/xil_cache_vxworks.h b/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v7_1/src/xil_cache_vxworks.h
new file mode 100644
index 0000000..730d526
--- /dev/null
+++ b/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v7_1/src/xil_cache_vxworks.h
@@ -0,0 +1,87 @@
+/******************************************************************************
+*
+* Copyright (C) 2009 - 2015 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+* THE SOFTWARE.
+*
+*
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xil_cache_vxworks.h
+*
+* Contains the cache related functions for VxWorks that is wrapped by
+* xil_cache.
+*
+* <pre>
+* MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ----- ---- -------- -------------------------------------------------------
+* 1.00a hbm 12/11/09 Initial release
+*
+* </pre>
+*
+* @note
+*
+******************************************************************************/
+
+#ifndef XIL_CACHE_VXWORKS_H
+#define XIL_CACHE_VXWORKS_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include "vxWorks.h"
+#include "vxLib.h"
+#include "sysLibExtra.h"
+#include "cacheLib.h"
+
+#if (CPU_FAMILY==PPC)
+
+#define Xil_DCacheEnable() cacheEnable(DATA_CACHE)
+
+#define Xil_DCacheDisable() cacheDisable(DATA_CACHE)
+
+#define Xil_DCacheInvalidateRange(Addr, Len) \
+ cacheInvalidate(DATA_CACHE, (void *)(Addr), (Len))
+
+#define Xil_DCacheFlushRange(Addr, Len) \
+ cacheFlush(DATA_CACHE, (void *)(Addr), (Len))
+
+#define Xil_ICacheEnable() cacheEnable(INSTRUCTION_CACHE)
+
+#define Xil_ICacheDisable() cacheDisable(INSTRUCTION_CACHE)
+
+#define Xil_ICacheInvalidateRange(Addr, Len) \
+ cacheInvalidate(INSTRUCTION_CACHE, (void *)(Addr), (Len))
+
+
+#else
+#error "Unknown processor / architecture. Must be PPC for VxWorks."
+#endif
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff --git a/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v7_1/src/xil_errata.h b/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v7_1/src/xil_errata.h
new file mode 100644
index 0000000..1ce2d64
--- /dev/null
+++ b/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v7_1/src/xil_errata.h
@@ -0,0 +1,125 @@
+/******************************************************************************
+*
+* Copyright (C) 2013 - 2015 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+* THE SOFTWARE.
+*
+*
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xil_errata.h
+*
+* @addtogroup a9_errata Cortex A9 Processor and pl310 Errata Support
+* @{
+* Various ARM errata are handled in the standalone BSP. The implementation for
+* errata handling follows ARM guidelines and is based on the open source Linux
+* support for these errata.
+*
+* @note
+* The errata handling is enabled by default. To disable handling of all the
+* errata globally, un-define the macro ENABLE_ARM_ERRATA in xil_errata.h. To
+* disable errata on a per-erratum basis, un-define relevant macros in
+* xil_errata.h.
+*
+* <pre>
+* MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ----- ---- -------- -----------------------------------------------
+* 1.00a srt 04/18/13 First release
+* 6.6 mus 12/07/17 Removed errata 753970, It fixes CR#989132.
+* </pre>
+*
+******************************************************************************/
+#ifndef XIL_ERRATA_H
+#define XIL_ERRATA_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * @name errata_definitions
+ *
+ * The errata conditions handled in the standalone BSP are listed below
+ * @{
+ */
+
+#define ENABLE_ARM_ERRATA 1
+
+#ifdef ENABLE_ARM_ERRATA
+
+/**
+ * Errata No: 742230
+ * Description: DMB operation may be faulty
+ */
+#define CONFIG_ARM_ERRATA_742230 1
+
+/**
+ * Errata No: 743622
+ * Description: Faulty hazard checking in the Store Buffer may lead
+ * to data corruption.
+ */
+#define CONFIG_ARM_ERRATA_743622 1
+
+/**
+ * Errata No: 775420
+ * Description: A data cache maintenance operation which aborts,
+ * might lead to deadlock
+ */
+#define CONFIG_ARM_ERRATA_775420 1
+
+/**
+ * Errata No: 794073
+ * Description: Speculative instruction fetches with MMU disabled
+ * might not comply with architectural requirements
+ */
+#define CONFIG_ARM_ERRATA_794073 1
+
+
+/** PL310 L2 Cache Errata */
+
+/**
+ * Errata No: 588369
+ * Description: Clean & Invalidate maintenance operations do not
+ * invalidate clean lines
+ */
+#define CONFIG_PL310_ERRATA_588369 1
+
+/**
+ * Errata No: 727915
+ * Description: Background Clean and Invalidate by Way operation
+ * can cause data corruption
+ */
+#define CONFIG_PL310_ERRATA_727915 1
+
+/*@}*/
+#endif /* ENABLE_ARM_ERRATA */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* XIL_ERRATA_H */
+/**
+* @} End of "addtogroup a9_errata".
+*/
diff --git a/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v7_1/src/xil_exception.c b/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v7_1/src/xil_exception.c
new file mode 100644
index 0000000..1229989
--- /dev/null
+++ b/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v7_1/src/xil_exception.c
@@ -0,0 +1,377 @@
+/******************************************************************************
+*
+* Copyright (C) 2015 - 2019 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+* THE SOFTWARE.
+*
+*
+*
+******************************************************************************/
+/****************************************************************************/
+/**
+*
+* @file xil_exception.c
+*
+* This file contains low-level driver functions for the Cortex A53,A9,R5 exception
+* Handler.
+*
+* <pre>
+* MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ----- -------- -------- -----------------------------------------------
+* 5.2 pkp 28/05/15 First release
+* 6.0 mus 27/07/16 Consolidated exceptions for a53,a9 and r5
+* processors and added Xil_UndefinedExceptionHandler
+* for a53 32 bit and r5 as well.
+* 6.4 mus 08/06/17 Updated debug prints to replace %x with the %lx, to
+* fix the warnings.
+* 6.7 mna 26/04/18 Add an API to obtain a corresponding
+* Xil_ExceptionHandler entry from XExc_VectorTable.
+* 6.7 asa 18/05/18 Fix bugs in the API Xil_GetExceptionRegisterHandler.
+* 7.0 mus 07/03/19 Tweak Xil_ExceptionRegisterHandler and
+* Xil_GetExceptionRegisterHandler to support legacy
+* examples for Cortexa72 EL3 exception level.
+*
+* </pre>
+*
+*****************************************************************************/
+
+/***************************** Include Files ********************************/
+
+#include "xil_types.h"
+#include "xil_assert.h"
+#include "xil_exception.h"
+#include "xpseudo_asm.h"
+#include "xdebug.h"
+/************************** Constant Definitions ****************************/
+
+/**************************** Type Definitions ******************************/
+
+typedef struct {
+ Xil_ExceptionHandler Handler;
+ void *Data;
+} XExc_VectorTableEntry;
+
+/***************** Macros (Inline Functions) Definitions ********************/
+
+/************************** Function Prototypes *****************************/
+static void Xil_ExceptionNullHandler(void *Data);
+/************************** Variable Definitions *****************************/
+/*
+ * Exception vector table to store handlers for each exception vector.
+ */
+#if defined (__aarch64__)
+XExc_VectorTableEntry XExc_VectorTable[XIL_EXCEPTION_ID_LAST + 1] =
+{
+ {Xil_ExceptionNullHandler, NULL},
+ {Xil_SyncAbortHandler, NULL},
+ {Xil_ExceptionNullHandler, NULL},
+ {Xil_ExceptionNullHandler, NULL},
+ {Xil_SErrorAbortHandler, NULL},
+
+};
+#else
+XExc_VectorTableEntry XExc_VectorTable[XIL_EXCEPTION_ID_LAST + 1] =
+{
+ {Xil_ExceptionNullHandler, NULL},
+ {Xil_UndefinedExceptionHandler, NULL},
+ {Xil_ExceptionNullHandler, NULL},
+ {Xil_PrefetchAbortHandler, NULL},
+ {Xil_DataAbortHandler, NULL},
+ {Xil_ExceptionNullHandler, NULL},
+ {Xil_ExceptionNullHandler, NULL},
+};
+#endif
+#if !defined (__aarch64__)
+u32 DataAbortAddr; /* Address of instruction causing data abort */
+u32 PrefetchAbortAddr; /* Address of instruction causing prefetch abort */
+u32 UndefinedExceptionAddr; /* Address of instruction causing Undefined
+ exception */
+#endif
+
+/*****************************************************************************/
+
+/****************************************************************************/
+/**
+*
+* This function is a stub Handler that is the default Handler that gets called
+* if the application has not setup a Handler for a specific exception. The
+* function interface has to match the interface specified for a Handler even
+* though none of the arguments are used.
+*
+* @param Data is unused by this function.
+*
+* @return None.
+*
+* @note None.
+*
+*****************************************************************************/
+static void Xil_ExceptionNullHandler(void *Data)
+{
+ (void) Data;
+DieLoop: goto DieLoop;
+}
+
+/****************************************************************************/
+/**
+* @brief The function is a common API used to initialize exception handlers
+* across all supported arm processors. For ARM Cortex-A53, Cortex-R5,
+* and Cortex-A9, the exception handlers are being initialized
+* statically and this function does not do anything.
+* However, it is still present to take care of backward compatibility
+* issues (in earlier versions of BSPs, this API was being used to
+* initialize exception handlers).
+*
+* @param None.
+*
+* @return None.
+*
+* @note None.
+*
+*****************************************************************************/
+void Xil_ExceptionInit(void)
+{
+ return;
+}
+
+/*****************************************************************************/
+/**
+* @brief Register a handler for a specific exception. This handler is being
+* called when the processor encounters the specified exception.
+*
+* @param exception_id contains the ID of the exception source and should
+* be in the range of 0 to XIL_EXCEPTION_ID_LAST.
+* See xil_exception.h for further information.
+* @param Handler to the Handler for that exception.
+* @param Data is a reference to Data that will be passed to the
+* Handler when it gets called.
+*
+* @return None.
+*
+* @note None.
+*
+****************************************************************************/
+void Xil_ExceptionRegisterHandler(u32 Exception_id,
+ Xil_ExceptionHandler Handler,
+ void *Data)
+{
+#if defined (versal) && !defined(ARMR5) && EL3
+/*
+ * Cortexa72 processor in versal is coupled with GIC-500, and GIC-500 supports
+ * only FIQ at EL3. Hence, tweaking this API to always act on FIQ,
+ * ignoring argument passed by user.
+ */
+ Exception_id = XIL_EXCEPTION_ID_FIQ_INT;
+#endif
+ XExc_VectorTable[Exception_id].Handler = Handler;
+ XExc_VectorTable[Exception_id].Data = Data;
+}
+
+/*****************************************************************************/
+/**
+* @brief Get a handler for a specific exception. This handler is being
+* called when the processor encounters the specified exception.
+*
+* @param exception_id contains the ID of the exception source and should
+* be in the range of 0 to XIL_EXCEPTION_ID_LAST.
+* See xil_exception.h for further information.
+* @param Handler to the Handler for that exception.
+* @param Data is a reference to Data that will be passed to the
+* Handler when it gets called.
+*
+* @return None.
+*
+* @note None.
+*
+****************************************************************************/
+void Xil_GetExceptionRegisterHandler(u32 Exception_id,
+ Xil_ExceptionHandler *Handler,
+ void **Data)
+{
+#if defined (versal) && !defined(ARMR5) && EL3
+/*
+ * Cortexa72 processor in versal is coupled with GIC-500, and GIC-500 supports
+ * only FIQ at EL3. Hence, tweaking this API to always act on FIQ,
+ * ignoring argument passed by user.
+ */
+ Exception_id = XIL_EXCEPTION_ID_FIQ_INT;
+#endif
+
+ *Handler = XExc_VectorTable[Exception_id].Handler;
+ *Data = XExc_VectorTable[Exception_id].Data;
+}
+
+/*****************************************************************************/
+/**
+*
+* @brief Removes the Handler for a specific exception Id. The stub Handler
+* is then registered for this exception Id.
+*
+* @param exception_id contains the ID of the exception source and should
+* be in the range of 0 to XIL_EXCEPTION_ID_LAST.
+* See xil_exception.h for further information.
+*
+* @return None.
+*
+* @note None.
+*
+****************************************************************************/
+void Xil_ExceptionRemoveHandler(u32 Exception_id)
+{
+ Xil_ExceptionRegisterHandler(Exception_id,
+ Xil_ExceptionNullHandler,
+ NULL);
+}
+
+#if defined (__aarch64__)
+/*****************************************************************************/
+/**
+*
+* Default Synchronous abort handler which prints a debug message on console if
+* Debug flag is enabled
+*
+* @param None
+*
+* @return None.
+*
+* @note None.
+*
+****************************************************************************/
+
+void Xil_SyncAbortHandler(void *CallBackRef){
+ (void) CallBackRef;
+ xdbg_printf(XDBG_DEBUG_ERROR, "Synchronous abort \n");
+ while(1) {
+ ;
+ }
+}
+
+/*****************************************************************************/
+/**
+*
+* Default SError abort handler which prints a debug message on console if
+* Debug flag is enabled
+*
+* @param None
+*
+* @return None.
+*
+* @note None.
+*
+****************************************************************************/
+void Xil_SErrorAbortHandler(void *CallBackRef){
+ (void) CallBackRef;
+ xdbg_printf(XDBG_DEBUG_ERROR, "Synchronous abort \n");
+ while(1) {
+ ;
+ }
+}
+#else
+/*****************************************************************************/
+/*
+*
+* Default Data abort handler which prints data fault status register through
+* which information about data fault can be acquired
+*
+* @param None
+*
+* @return None.
+*
+* @note None.
+*
+****************************************************************************/
+
+void Xil_DataAbortHandler(void *CallBackRef){
+ (void) CallBackRef;
+#ifdef DEBUG
+ u32 FaultStatus;
+
+ xdbg_printf(XDBG_DEBUG_ERROR, "Data abort \n");
+ #ifdef __GNUC__
+ FaultStatus = mfcp(XREG_CP15_DATA_FAULT_STATUS);
+ #elif defined (__ICCARM__)
+ mfcp(XREG_CP15_DATA_FAULT_STATUS,FaultStatus);
+ #else
+ { volatile register u32 Reg __asm(XREG_CP15_DATA_FAULT_STATUS);
+ FaultStatus = Reg; }
+ #endif
+ xdbg_printf(XDBG_DEBUG_GENERAL, "Data abort with Data Fault Status Register %lx\n",FaultStatus);
+ xdbg_printf(XDBG_DEBUG_GENERAL, "Address of Instruction causing Data abort %lx\n",DataAbortAddr);
+#endif
+ while(1) {
+ ;
+ }
+}
+
+/*****************************************************************************/
+/*
+*
+* Default Prefetch abort handler which prints prefetch fault status register through
+* which information about instruction prefetch fault can be acquired
+*
+* @param None
+*
+* @return None.
+*
+* @note None.
+*
+****************************************************************************/
+void Xil_PrefetchAbortHandler(void *CallBackRef){
+ (void) CallBackRef;
+#ifdef DEBUG
+ u32 FaultStatus;
+
+ xdbg_printf(XDBG_DEBUG_ERROR, "Prefetch abort \n");
+ #ifdef __GNUC__
+ FaultStatus = mfcp(XREG_CP15_INST_FAULT_STATUS);
+ #elif defined (__ICCARM__)
+ mfcp(XREG_CP15_INST_FAULT_STATUS,FaultStatus);
+ #else
+ { volatile register u32 Reg __asm(XREG_CP15_INST_FAULT_STATUS);
+ FaultStatus = Reg; }
+ #endif
+ xdbg_printf(XDBG_DEBUG_GENERAL, "Prefetch abort with Instruction Fault Status Register %lx\n",FaultStatus);
+ xdbg_printf(XDBG_DEBUG_GENERAL, "Address of Instruction causing Prefetch abort %lx\n",PrefetchAbortAddr);
+#endif
+ while(1) {
+ ;
+ }
+}
+/*****************************************************************************/
+/*
+*
+* Default undefined exception handler which prints address of the undefined
+* instruction if debug prints are enabled
+*
+* @param None
+*
+* @return None.
+*
+* @note None.
+*
+****************************************************************************/
+void Xil_UndefinedExceptionHandler(void *CallBackRef){
+ (void) CallBackRef;
+ xdbg_printf(XDBG_DEBUG_GENERAL, "Address of the undefined instruction %lx\n",UndefinedExceptionAddr);
+ while(1) {
+ ;
+ }
+}
+#endif
diff --git a/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v7_1/src/xil_exception.h b/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v7_1/src/xil_exception.h
new file mode 100644
index 0000000..0f03e0a
--- /dev/null
+++ b/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v7_1/src/xil_exception.h
@@ -0,0 +1,283 @@
+/******************************************************************************
+*
+* Copyright (C) 2015 - 2016 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+* THE SOFTWARE.
+*
+*
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xil_exception.h
+*
+* This header file contains ARM Cortex A53,A9,R5 specific exception related APIs.
+* For exception related functions that can be used across all Xilinx supported
+* processors, please use xil_exception.h.
+*
+* @addtogroup arm_exception_apis ARM Processor Exception Handling
+* @{
+* ARM processors specific exception related APIs for cortex A53,A9 and R5 can
+* utilized for enabling/disabling IRQ, registering/removing handler for
+* exceptions or initializing exception vector table with null handler.
+*
+* <pre>
+* MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ----- -------- -------- -----------------------------------------------
+* 5.2 pkp 28/05/15 First release
+* 6.0 mus 27/07/16 Consolidated file for a53,a9 and r5 processors
+* 6.7 mna 26/04/18 Add API Xil_GetExceptionRegisterHandler.
+* 6.7 asa 18/05/18 Update signature of API Xil_GetExceptionRegisterHandler.
+* 7.0 mus 01/03/19 Tweak Xil_ExceptionEnableMask and
+* Xil_ExceptionDisableMask macros to support legacy
+* examples for Cortexa72 EL3 exception level.
+* </pre>
+*
+******************************************************************************/
+
+#ifndef XIL_EXCEPTION_H /* prevent circular inclusions */
+#define XIL_EXCEPTION_H /* by using protection macros */
+
+/***************************** Include Files ********************************/
+
+#include "xil_types.h"
+#include "xpseudo_asm.h"
+#include "bspconfig.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/************************** Constant Definitions ****************************/
+
+#define XIL_EXCEPTION_FIQ XREG_CPSR_FIQ_ENABLE
+#define XIL_EXCEPTION_IRQ XREG_CPSR_IRQ_ENABLE
+#define XIL_EXCEPTION_ALL (XREG_CPSR_FIQ_ENABLE | XREG_CPSR_IRQ_ENABLE)
+
+#define XIL_EXCEPTION_ID_FIRST 0U
+#if defined (__aarch64__)
+#define XIL_EXCEPTION_ID_SYNC_INT 1U
+#define XIL_EXCEPTION_ID_IRQ_INT 2U
+#define XIL_EXCEPTION_ID_FIQ_INT 3U
+#define XIL_EXCEPTION_ID_SERROR_ABORT_INT 4U
+#define XIL_EXCEPTION_ID_LAST 5U
+#else
+#define XIL_EXCEPTION_ID_RESET 0U
+#define XIL_EXCEPTION_ID_UNDEFINED_INT 1U
+#define XIL_EXCEPTION_ID_SWI_INT 2U
+#define XIL_EXCEPTION_ID_PREFETCH_ABORT_INT 3U
+#define XIL_EXCEPTION_ID_DATA_ABORT_INT 4U
+#define XIL_EXCEPTION_ID_IRQ_INT 5U
+#define XIL_EXCEPTION_ID_FIQ_INT 6U
+#define XIL_EXCEPTION_ID_LAST 6U
+#endif
+
+/*
+ * XIL_EXCEPTION_ID_INT is defined for all Xilinx processors.
+ */
+#if defined (versal) && !defined(ARMR5) && EL3
+#define XIL_EXCEPTION_ID_INT XIL_EXCEPTION_ID_FIQ_INT
+#else
+#define XIL_EXCEPTION_ID_INT XIL_EXCEPTION_ID_IRQ_INT
+#endif
+
+/**************************** Type Definitions ******************************/
+
+/**
+ * This typedef is the exception handler function.
+ */
+typedef void (*Xil_ExceptionHandler)(void *data);
+typedef void (*Xil_InterruptHandler)(void *data);
+
+/***************** Macros (Inline Functions) Definitions ********************/
+
+/****************************************************************************/
+/**
+* @brief Enable Exceptions.
+*
+* @param Mask: Value for enabling the exceptions.
+*
+* @return None.
+*
+* @note If bit is 0, exception is enabled.
+* C-Style signature: void Xil_ExceptionEnableMask(Mask)
+*
+******************************************************************************/
+#if defined (versal) && !defined(ARMR5) && EL3
+/*
+ * Cortexa72 processor in versal is coupled with GIC-500, and GIC-500 supports
+ * only FIQ at EL3. Hence, tweaking this macro to always enable FIQ
+ * ignoring argument passed by user.
+ */
+#define Xil_ExceptionEnableMask(Mask) \
+ mtcpsr(mfcpsr() & ~ ((XIL_EXCEPTION_FIQ) & XIL_EXCEPTION_ALL))
+#elif defined (__GNUC__) || defined (__ICCARM__)
+#define Xil_ExceptionEnableMask(Mask) \
+ mtcpsr(mfcpsr() & ~ ((Mask) & XIL_EXCEPTION_ALL))
+#else
+#define Xil_ExceptionEnableMask(Mask) \
+ { \
+ register u32 Reg __asm("cpsr"); \
+ mtcpsr((Reg) & (~((Mask) & XIL_EXCEPTION_ALL))); \
+ }
+#endif
+/****************************************************************************/
+/**
+* @brief Enable the IRQ exception.
+*
+* @return None.
+*
+* @note None.
+*
+******************************************************************************/
+#if defined (versal) && !defined(ARMR5) && EL3
+#define Xil_ExceptionEnable() \
+ Xil_ExceptionEnableMask(XIL_EXCEPTION_FIQ)
+#else
+#define Xil_ExceptionEnable() \
+ Xil_ExceptionEnableMask(XIL_EXCEPTION_IRQ)
+#endif
+
+/****************************************************************************/
+/**
+* @brief Disable Exceptions.
+*
+* @param Mask: Value for disabling the exceptions.
+*
+* @return None.
+*
+* @note If bit is 1, exception is disabled.
+* C-Style signature: Xil_ExceptionDisableMask(Mask)
+*
+******************************************************************************/
+#if defined (versal) && !defined(ARMR5) && EL3
+/*
+ * Cortexa72 processor in versal is coupled with GIC-500, and GIC-500 supports
+ * only FIQ at EL3. Hence, tweaking this macro to always disable FIQ
+ * ignoring argument passed by user.
+ */
+#define Xil_ExceptionDisableMask(Mask) \
+ mtcpsr(mfcpsr() | ((XIL_EXCEPTION_FIQ) & XIL_EXCEPTION_ALL))
+#elif defined (__GNUC__) || defined (__ICCARM__)
+#define Xil_ExceptionDisableMask(Mask) \
+ mtcpsr(mfcpsr() | ((Mask) & XIL_EXCEPTION_ALL))
+#else
+#define Xil_ExceptionDisableMask(Mask) \
+ { \
+ register u32 Reg __asm("cpsr"); \
+ mtcpsr((Reg) | ((Mask) & XIL_EXCEPTION_ALL)); \
+ }
+#endif
+/****************************************************************************/
+/**
+* Disable the IRQ exception.
+*
+* @return None.
+*
+* @note None.
+*
+******************************************************************************/
+#define Xil_ExceptionDisable() \
+ Xil_ExceptionDisableMask(XIL_EXCEPTION_IRQ)
+
+#if !defined (__aarch64__) && !defined (ARMA53_32)
+/****************************************************************************/
+/**
+* @brief Enable nested interrupts by clearing the I and F bits in CPSR. This
+* API is defined for cortex-a9 and cortex-r5.
+*
+* @return None.
+*
+* @note This macro is supposed to be used from interrupt handlers. In the
+* interrupt handler the interrupts are disabled by default (I and F
+* are 1). To allow nesting of interrupts, this macro should be
+* used. It clears the I and F bits by changing the ARM mode to
+* system mode. Once these bits are cleared and provided the
+* preemption of interrupt conditions are met in the GIC, nesting of
+* interrupts will start happening.
+* Caution: This macro must be used with caution. Before calling this
+* macro, the user must ensure that the source of the current IRQ
+* is appropriately cleared. Otherwise, as soon as we clear the I and
+* F bits, there can be an infinite loop of interrupts with an
+* eventual crash (all the stack space getting consumed).
+******************************************************************************/
+#define Xil_EnableNestedInterrupts() \
+ __asm__ __volatile__ ("stmfd sp!, {lr}"); \
+ __asm__ __volatile__ ("mrs lr, spsr"); \
+ __asm__ __volatile__ ("stmfd sp!, {lr}"); \
+ __asm__ __volatile__ ("msr cpsr_c, #0x1F"); \
+ __asm__ __volatile__ ("stmfd sp!, {lr}");
+
+/****************************************************************************/
+/**
+* @brief Disable the nested interrupts by setting the I and F bits. This API
+* is defined for cortex-a9 and cortex-r5.
+*
+* @return None.
+*
+* @note This macro is meant to be called in the interrupt service routines.
+* This macro cannot be used independently. It can only be used when
+* nesting of interrupts have been enabled by using the macro
+* Xil_EnableNestedInterrupts(). In a typical flow, the user first
+* calls the Xil_EnableNestedInterrupts in the ISR at the appropriate
+* point. The user then must call this macro before exiting the interrupt
+* service routine. This macro puts the ARM back in IRQ/FIQ mode and
+* hence sets back the I and F bits.
+******************************************************************************/
+#define Xil_DisableNestedInterrupts() \
+ __asm__ __volatile__ ("ldmfd sp!, {lr}"); \
+ __asm__ __volatile__ ("msr cpsr_c, #0x92"); \
+ __asm__ __volatile__ ("ldmfd sp!, {lr}"); \
+ __asm__ __volatile__ ("msr spsr_cxsf, lr"); \
+ __asm__ __volatile__ ("ldmfd sp!, {lr}"); \
+
+#endif
+/************************** Variable Definitions ****************************/
+
+/************************** Function Prototypes *****************************/
+
+extern void Xil_ExceptionRegisterHandler(u32 Exception_id,
+ Xil_ExceptionHandler Handler,
+ void *Data);
+
+extern void Xil_ExceptionRemoveHandler(u32 Exception_id);
+extern void Xil_GetExceptionRegisterHandler(u32 Exception_id,
+ Xil_ExceptionHandler *Handler, void **Data);
+
+extern void Xil_ExceptionInit(void);
+#if defined (__aarch64__)
+void Xil_SyncAbortHandler(void *CallBackRef);
+void Xil_SErrorAbortHandler(void *CallBackRef);
+#else
+extern void Xil_DataAbortHandler(void *CallBackRef);
+extern void Xil_PrefetchAbortHandler(void *CallBackRef);
+extern void Xil_UndefinedExceptionHandler(void *CallBackRef);
+#endif
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+
+#endif /* XIL_EXCEPTION_H */
+/**
+* @} End of "addtogroup arm_exception_apis".
+*/
diff --git a/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v7_1/src/xil_hal.h b/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v7_1/src/xil_hal.h
new file mode 100644
index 0000000..be56e0e
--- /dev/null
+++ b/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v7_1/src/xil_hal.h
@@ -0,0 +1,63 @@
+/******************************************************************************
+*
+* Copyright (C) 2009 - 2015 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+* THE SOFTWARE.
+*
+*
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xil_hal.h
+*
+* Contains all the HAL header files.
+*
+* <pre>
+* MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ----- ---- -------- -------------------------------------------------------
+* 1.00a hbm 07/28/09 Initial release
+*
+* </pre>
+*
+* @note
+*
+******************************************************************************/
+
+#ifndef XIL_HAL_H
+#define XIL_HAL_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include "xil_cache.h"
+#include "xil_io.h"
+#include "xil_assert.h"
+#include "xil_exception.h"
+#include "xil_types.h"
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff --git a/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v7_1/src/xil_io.c b/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v7_1/src/xil_io.c
new file mode 100644
index 0000000..7556ad6
--- /dev/null
+++ b/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v7_1/src/xil_io.c
@@ -0,0 +1,96 @@
+/******************************************************************************
+*
+* Copyright (C) 2014 - 2016 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+* THE SOFTWARE.
+*
+*
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xil_io.c
+*
+* Contains I/O functions for memory-mapped or non-memory-mapped I/O
+* architectures.
+*
+* @note
+*
+* This file contains architecture-dependent code.
+*
+* <pre>
+* MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ----- -------- -------- -----------------------------------------------
+* 5.00 pkp 05/29/14 First release
+* </pre>
+******************************************************************************/
+
+
+/***************************** Include Files *********************************/
+#include "xil_io.h"
+#include "xil_types.h"
+#include "xil_assert.h"
+
+/*****************************************************************************/
+/**
+*
+* @brief Perform a 16-bit endian conversion.
+*
+* @param Data: 16 bit value to be converted
+*
+* @return 16 bit Data with converted endianness
+*
+******************************************************************************/
+u16 Xil_EndianSwap16(u16 Data)
+{
+ return (u16) (((Data & 0xFF00U) >> 8U) | ((Data & 0x00FFU) << 8U));
+}
+
+/*****************************************************************************/
+/**
+*
+* @brief Perform a 32-bit endian conversion.
+*
+* @param Data: 32 bit value to be converted
+*
+* @return 32 bit data with converted endianness
+*
+******************************************************************************/
+u32 Xil_EndianSwap32(u32 Data)
+{
+ u16 LoWord;
+ u16 HiWord;
+
+ /* get each of the half words from the 32 bit word */
+
+ LoWord = (u16) (Data & 0x0000FFFFU);
+ HiWord = (u16) ((Data & 0xFFFF0000U) >> 16U);
+
+ /* byte swap each of the 16 bit half words */
+
+ LoWord = (((LoWord & 0xFF00U) >> 8U) | ((LoWord & 0x00FFU) << 8U));
+ HiWord = (((HiWord & 0xFF00U) >> 8U) | ((HiWord & 0x00FFU) << 8U));
+
+ /* swap the half words before returning the value */
+
+ return ((((u32)LoWord) << (u32)16U) | (u32)HiWord);
+}
diff --git a/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v7_1/src/xil_io.h b/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v7_1/src/xil_io.h
new file mode 100644
index 0000000..a475227
--- /dev/null
+++ b/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v7_1/src/xil_io.h
@@ -0,0 +1,339 @@
+/******************************************************************************
+*
+* Copyright (C) 2014 - 2016 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+* THE SOFTWARE.
+*
+*
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xil_io.h
+*
+* @addtogroup common_io_interfacing_apis Register IO interfacing APIs
+*
+* The xil_io.h file contains the interface for the general I/O component, which
+* encapsulates the Input/Output functions for the processors that do not
+* require any special I/O handling.
+*
+* @{
+* <pre>
+* MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ----- -------- -------- -----------------------------------------------
+* 5.00 pkp 05/29/14 First release
+* 6.00 mus 08/19/16 Remove checking of __LITTLE_ENDIAN__ flag for
+* ARM processors
+* </pre>
+******************************************************************************/
+
+#ifndef XIL_IO_H /* prevent circular inclusions */
+#define XIL_IO_H /* by using protection macros */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/***************************** Include Files *********************************/
+
+#include "xil_types.h"
+#include "xil_printf.h"
+
+#if defined (__MICROBLAZE__)
+#include "mb_interface.h"
+#else
+#include "xpseudo_asm.h"
+#endif
+
+/************************** Function Prototypes ******************************/
+u16 Xil_EndianSwap16(u16 Data);
+u32 Xil_EndianSwap32(u32 Data);
+#ifdef ENABLE_SAFETY
+extern u32 XStl_RegUpdate(u32 RegAddr, u32 RegVal);
+#endif
+
+/***************** Macros (Inline Functions) Definitions *********************/
+#if defined __GNUC__
+#if defined (__MICROBLAZE__)
+# define INST_SYNC mbar(0)
+# define DATA_SYNC mbar(1)
+# else
+# define SYNCHRONIZE_IO dmb()
+# define INST_SYNC isb()
+# define DATA_SYNC dsb()
+# endif
+#else
+# define SYNCHRONIZE_IO
+# define INST_SYNC
+# define DATA_SYNC
+# define INST_SYNC
+# define DATA_SYNC
+#endif
+
+#if defined (__GNUC__) || defined (__ICCARM__) || defined (__MICROBLAZE__)
+#define INLINE inline
+#else
+#define INLINE __inline
+#endif
+
+/*****************************************************************************/
+/**
+*
+* @brief Performs an input operation for a memory location by reading
+* from the specified address and returning the 8 bit Value read from
+* that address.
+*
+* @param Addr: contains the address to perform the input operation
+*
+* @return The 8 bit Value read from the specified input address.
+
+*
+******************************************************************************/
+static INLINE u8 Xil_In8(UINTPTR Addr)
+{
+ return *(volatile u8 *) Addr;
+}
+
+/*****************************************************************************/
+/**
+*
+* @brief Performs an input operation for a memory location by reading from
+* the specified address and returning the 16 bit Value read from that
+* address.
+*
+* @param Addr: contains the address to perform the input operation
+*
+* @return The 16 bit Value read from the specified input address.
+*
+******************************************************************************/
+static INLINE u16 Xil_In16(UINTPTR Addr)
+{
+ return *(volatile u16 *) Addr;
+}
+
+/*****************************************************************************/
+/**
+*
+* @brief Performs an input operation for a memory location by
+* reading from the specified address and returning the 32 bit Value
+* read from that address.
+*
+* @param Addr: contains the address to perform the input operation
+*
+* @return The 32 bit Value read from the specified input address.
+*
+******************************************************************************/
+static INLINE u32 Xil_In32(UINTPTR Addr)
+{
+ return *(volatile u32 *) Addr;
+}
+
+/*****************************************************************************/
+/**
+*
+* @brief Performs an input operation for a memory location by reading the
+* 64 bit Value read from that address.
+*
+*
+* @param Addr: contains the address to perform the input operation
+*
+* @return The 64 bit Value read from the specified input address.
+*
+******************************************************************************/
+static INLINE u64 Xil_In64(UINTPTR Addr)
+{
+ return *(volatile u64 *) Addr;
+}
+
+/*****************************************************************************/
+/**
+*
+* @brief Performs an output operation for an memory location by
+* writing the 8 bit Value to the the specified address.
+*
+* @param Addr: contains the address to perform the output operation
+* @param Value: contains the 8 bit Value to be written at the specified
+* address.
+*
+* @return None.
+*
+******************************************************************************/
+static INLINE void Xil_Out8(UINTPTR Addr, u8 Value)
+{
+ volatile u8 *LocalAddr = (volatile u8 *)Addr;
+ *LocalAddr = Value;
+}
+
+/*****************************************************************************/
+/**
+*
+* @brief Performs an output operation for a memory location by writing the
+* 16 bit Value to the the specified address.
+*
+* @param Addr contains the address to perform the output operation
+* @param Value contains the Value to be written at the specified address.
+*
+* @return None.
+*
+******************************************************************************/
+static INLINE void Xil_Out16(UINTPTR Addr, u16 Value)
+{
+ volatile u16 *LocalAddr = (volatile u16 *)Addr;
+ *LocalAddr = Value;
+}
+
+/*****************************************************************************/
+/**
+*
+* @brief Performs an output operation for a memory location by writing the
+* 32 bit Value to the the specified address.
+*
+* @param Addr contains the address to perform the output operation
+* @param Value contains the 32 bit Value to be written at the specified
+* address.
+*
+* @return None.
+*
+******************************************************************************/
+static INLINE void Xil_Out32(UINTPTR Addr, u32 Value)
+{
+#ifndef ENABLE_SAFETY
+ volatile u32 *LocalAddr = (volatile u32 *)Addr;
+ *LocalAddr = Value;
+#else
+ XStl_RegUpdate(Addr, Value);
+#endif
+}
+
+/*****************************************************************************/
+/**
+*
+* @brief Performs an output operation for a memory location by writing the
+* 64 bit Value to the the specified address.
+*
+* @param Addr contains the address to perform the output operation
+* @param Value contains 64 bit Value to be written at the specified address.
+*
+* @return None.
+*
+******************************************************************************/
+static INLINE void Xil_Out64(UINTPTR Addr, u64 Value)
+{
+ volatile u64 *LocalAddr = (volatile u64 *)Addr;
+ *LocalAddr = Value;
+}
+
+#if defined (__MICROBLAZE__)
+#ifdef __LITTLE_ENDIAN__
+# define Xil_In16LE Xil_In16
+# define Xil_In32LE Xil_In32
+# define Xil_Out16LE Xil_Out16
+# define Xil_Out32LE Xil_Out32
+# define Xil_Htons Xil_EndianSwap16
+# define Xil_Htonl Xil_EndianSwap32
+# define Xil_Ntohs Xil_EndianSwap16
+# define Xil_Ntohl Xil_EndianSwap32
+# else
+# define Xil_In16BE Xil_In16
+# define Xil_In32BE Xil_In32
+# define Xil_Out16BE Xil_Out16
+# define Xil_Out32BE Xil_Out32
+# define Xil_Htons(Data) (Data)
+# define Xil_Htonl(Data) (Data)
+# define Xil_Ntohs(Data) (Data)
+# define Xil_Ntohl(Data) (Data)
+#endif
+#else
+# define Xil_In16LE Xil_In16
+# define Xil_In32LE Xil_In32
+# define Xil_Out16LE Xil_Out16
+# define Xil_Out32LE Xil_Out32
+# define Xil_Htons Xil_EndianSwap16
+# define Xil_Htonl Xil_EndianSwap32
+# define Xil_Ntohs Xil_EndianSwap16
+# define Xil_Ntohl Xil_EndianSwap32
+#endif
+
+#if defined (__MICROBLAZE__)
+#ifdef __LITTLE_ENDIAN__
+static INLINE u16 Xil_In16BE(UINTPTR Addr)
+#else
+static INLINE u16 Xil_In16LE(UINTPTR Addr)
+#endif
+#else
+static INLINE u16 Xil_In16BE(UINTPTR Addr)
+#endif
+{
+ u16 value = Xil_In16(Addr);
+ return Xil_EndianSwap16(value);
+}
+
+#if defined (__MICROBLAZE__)
+#ifdef __LITTLE_ENDIAN__
+static INLINE u32 Xil_In32BE(UINTPTR Addr)
+#else
+static INLINE u32 Xil_In32LE(UINTPTR Addr)
+#endif
+#else
+static INLINE u32 Xil_In32BE(UINTPTR Addr)
+#endif
+{
+ u32 value = Xil_In32(Addr);
+ return Xil_EndianSwap32(value);
+}
+
+#if defined (__MICROBLAZE__)
+#ifdef __LITTLE_ENDIAN__
+static INLINE void Xil_Out16BE(UINTPTR Addr, u16 Value)
+#else
+static INLINE void Xil_Out16LE(UINTPTR Addr, u16 Value)
+#endif
+#else
+static INLINE void Xil_Out16BE(UINTPTR Addr, u16 Value)
+#endif
+{
+ Value = Xil_EndianSwap16(Value);
+ Xil_Out16(Addr, Value);
+}
+
+#if defined (__MICROBLAZE__)
+#ifdef __LITTLE_ENDIAN__
+static INLINE void Xil_Out32BE(UINTPTR Addr, u32 Value)
+#else
+static INLINE void Xil_Out32LE(UINTPTR Addr, u32 Value)
+#endif
+#else
+static INLINE void Xil_Out32BE(UINTPTR Addr, u32 Value)
+#endif
+{
+ Value = Xil_EndianSwap32(Value);
+ Xil_Out32(Addr, Value);
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* end of protection macro */
+/**
+* @} End of "addtogroup common_io_interfacing_apis".
+*/
diff --git a/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v7_1/src/xil_macroback.h b/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v7_1/src/xil_macroback.h
new file mode 100644
index 0000000..414970e
--- /dev/null
+++ b/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v7_1/src/xil_macroback.h
@@ -0,0 +1,1054 @@
+/******************************************************************************
+*
+* Copyright (C) 2010 - 2015 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+* THE SOFTWARE.
+*
+*
+*
+******************************************************************************/
+
+/*********************************************************************/
+/**
+ * @file xil_macroback.h
+ *
+ * This header file is meant to bring back the removed _m macros.
+ * This header file must be included last.
+ * The following macros are not defined here due to the driver change:
+ * XGpio_mSetDataDirection
+ * XGpio_mGetDataReg
+ * XGpio_mSetDataReg
+ * XIIC_RESET
+ * XIIC_CLEAR_STATS
+ * XSpi_mReset
+ * XSysAce_mSetCfgAddr
+ * XSysAce_mIsCfgDone
+ * XTft_mSetPixel
+ * XTft_mGetPixel
+ * XWdtTb_mEnableWdt
+ * XWdtTb_mDisbleWdt
+ * XWdtTb_mRestartWdt
+ * XWdtTb_mGetTimebaseReg
+ * XWdtTb_mHasReset
+ *
+ * Please refer the corresponding driver document for replacement.
+ *
+ *********************************************************************/
+
+#ifndef XIL_MACROBACK_H
+#define XIL_MACROBACK_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*********************************************************************/
+/**
+ * Macros for Driver XCan
+ *
+ *********************************************************************/
+#ifndef XCan_mReadReg
+#define XCan_mReadReg XCan_ReadReg
+#endif
+
+#ifndef XCan_mWriteReg
+#define XCan_mWriteReg XCan_WriteReg
+#endif
+
+#ifndef XCan_mIsTxDone
+#define XCan_mIsTxDone XCan_IsTxDone
+#endif
+
+#ifndef XCan_mIsTxFifoFull
+#define XCan_mIsTxFifoFull XCan_IsTxFifoFull
+#endif
+
+#ifndef XCan_mIsHighPriorityBufFull
+#define XCan_mIsHighPriorityBufFull XCan_IsHighPriorityBufFull
+#endif
+
+#ifndef XCan_mIsRxEmpty
+#define XCan_mIsRxEmpty XCan_IsRxEmpty
+#endif
+
+#ifndef XCan_mIsAcceptFilterBusy
+#define XCan_mIsAcceptFilterBusy XCan_IsAcceptFilterBusy
+#endif
+
+#ifndef XCan_mCreateIdValue
+#define XCan_mCreateIdValue XCan_CreateIdValue
+#endif
+
+#ifndef XCan_mCreateDlcValue
+#define XCan_mCreateDlcValue XCan_CreateDlcValue
+#endif
+
+/*********************************************************************/
+/**
+ * Macros for Driver XDmaCentral
+ *
+ *********************************************************************/
+#ifndef XDmaCentral_mWriteReg
+#define XDmaCentral_mWriteReg XDmaCentral_WriteReg
+#endif
+
+#ifndef XDmaCentral_mReadReg
+#define XDmaCentral_mReadReg XDmaCentral_ReadReg
+#endif
+
+/*********************************************************************/
+/**
+ * Macros for Driver XDsAdc
+ *
+ *********************************************************************/
+#ifndef XDsAdc_mWriteReg
+#define XDsAdc_mWriteReg XDsAdc_WriteReg
+#endif
+
+#ifndef XDsAdc_mReadReg
+#define XDsAdc_mReadReg XDsAdc_ReadReg
+#endif
+
+#ifndef XDsAdc_mIsEmpty
+#define XDsAdc_mIsEmpty XDsAdc_IsEmpty
+#endif
+
+#ifndef XDsAdc_mSetFstmReg
+#define XDsAdc_mSetFstmReg XDsAdc_SetFstmReg
+#endif
+
+#ifndef XDsAdc_mGetFstmReg
+#define XDsAdc_mGetFstmReg XDsAdc_GetFstmReg
+#endif
+
+#ifndef XDsAdc_mEnableConversion
+#define XDsAdc_mEnableConversion XDsAdc_EnableConversion
+#endif
+
+#ifndef XDsAdc_mDisableConversion
+#define XDsAdc_mDisableConversion XDsAdc_DisableConversion
+#endif
+
+#ifndef XDsAdc_mGetFifoOccyReg
+#define XDsAdc_mGetFifoOccyReg XDsAdc_GetFifoOccyReg
+#endif
+
+/*********************************************************************/
+/**
+ * Macros for Driver XDsDac
+ *
+ *********************************************************************/
+#ifndef XDsDac_mWriteReg
+#define XDsDac_mWriteReg XDsDac_WriteReg
+#endif
+
+#ifndef XDsDac_mReadReg
+#define XDsDac_mReadReg XDsDac_ReadReg
+#endif
+
+#ifndef XDsDac_mIsEmpty
+#define XDsDac_mIsEmpty XDsDac_IsEmpty
+#endif
+
+#ifndef XDsDac_mFifoIsFull
+#define XDsDac_mFifoIsFull XDsDac_FifoIsFull
+#endif
+
+#ifndef XDsDac_mGetVacancy
+#define XDsDac_mGetVacancy XDsDac_GetVacancy
+#endif
+
+/*********************************************************************/
+/**
+ * Macros for Driver XEmacLite
+ *
+ *********************************************************************/
+#ifndef XEmacLite_mReadReg
+#define XEmacLite_mReadReg XEmacLite_ReadReg
+#endif
+
+#ifndef XEmacLite_mWriteReg
+#define XEmacLite_mWriteReg XEmacLite_WriteReg
+#endif
+
+#ifndef XEmacLite_mGetTxStatus
+#define XEmacLite_mGetTxStatus XEmacLite_GetTxStatus
+#endif
+
+#ifndef XEmacLite_mSetTxStatus
+#define XEmacLite_mSetTxStatus XEmacLite_SetTxStatus
+#endif
+
+#ifndef XEmacLite_mGetRxStatus
+#define XEmacLite_mGetRxStatus XEmacLite_GetRxStatus
+#endif
+
+#ifndef XEmacLite_mSetRxStatus
+#define XEmacLite_mSetRxStatus XEmacLite_SetRxStatus
+#endif
+
+#ifndef XEmacLite_mIsTxDone
+#define XEmacLite_mIsTxDone XEmacLite_IsTxDone
+#endif
+
+#ifndef XEmacLite_mIsRxEmpty
+#define XEmacLite_mIsRxEmpty XEmacLite_IsRxEmpty
+#endif
+
+#ifndef XEmacLite_mNextTransmitAddr
+#define XEmacLite_mNextTransmitAddr XEmacLite_NextTransmitAddr
+#endif
+
+#ifndef XEmacLite_mNextReceiveAddr
+#define XEmacLite_mNextReceiveAddr XEmacLite_NextReceiveAddr
+#endif
+
+#ifndef XEmacLite_mIsMdioConfigured
+#define XEmacLite_mIsMdioConfigured XEmacLite_IsMdioConfigured
+#endif
+
+#ifndef XEmacLite_mIsLoopbackConfigured
+#define XEmacLite_mIsLoopbackConfigured XEmacLite_IsLoopbackConfigured
+#endif
+
+#ifndef XEmacLite_mGetReceiveDataLength
+#define XEmacLite_mGetReceiveDataLength XEmacLite_GetReceiveDataLength
+#endif
+
+#ifndef XEmacLite_mGetTxActive
+#define XEmacLite_mGetTxActive XEmacLite_GetTxActive
+#endif
+
+#ifndef XEmacLite_mSetTxActive
+#define XEmacLite_mSetTxActive XEmacLite_SetTxActive
+#endif
+
+/*********************************************************************/
+/**
+ * Macros for Driver XGpio
+ *
+ *********************************************************************/
+#ifndef XGpio_mWriteReg
+#define XGpio_mWriteReg XGpio_WriteReg
+#endif
+
+#ifndef XGpio_mReadReg
+#define XGpio_mReadReg XGpio_ReadReg
+#endif
+
+/*********************************************************************/
+/**
+ * Macros for Driver XHwIcap
+ *
+ *********************************************************************/
+#ifndef XHwIcap_mFifoWrite
+#define XHwIcap_mFifoWrite XHwIcap_FifoWrite
+#endif
+
+#ifndef XHwIcap_mFifoRead
+#define XHwIcap_mFifoRead XHwIcap_FifoRead
+#endif
+
+#ifndef XHwIcap_mSetSizeReg
+#define XHwIcap_mSetSizeReg XHwIcap_SetSizeReg
+#endif
+
+#ifndef XHwIcap_mGetControlReg
+#define XHwIcap_mGetControlReg XHwIcap_GetControlReg
+#endif
+
+#ifndef XHwIcap_mStartConfig
+#define XHwIcap_mStartConfig XHwIcap_StartConfig
+#endif
+
+#ifndef XHwIcap_mStartReadBack
+#define XHwIcap_mStartReadBack XHwIcap_StartReadBack
+#endif
+
+#ifndef XHwIcap_mGetStatusReg
+#define XHwIcap_mGetStatusReg XHwIcap_GetStatusReg
+#endif
+
+#ifndef XHwIcap_mIsTransferDone
+#define XHwIcap_mIsTransferDone XHwIcap_IsTransferDone
+#endif
+
+#ifndef XHwIcap_mIsDeviceBusy
+#define XHwIcap_mIsDeviceBusy XHwIcap_IsDeviceBusy
+#endif
+
+#ifndef XHwIcap_mIntrGlobalEnable
+#define XHwIcap_mIntrGlobalEnable XHwIcap_IntrGlobalEnable
+#endif
+
+#ifndef XHwIcap_mIntrGlobalDisable
+#define XHwIcap_mIntrGlobalDisable XHwIcap_IntrGlobalDisable
+#endif
+
+#ifndef XHwIcap_mIntrGetStatus
+#define XHwIcap_mIntrGetStatus XHwIcap_IntrGetStatus
+#endif
+
+#ifndef XHwIcap_mIntrDisable
+#define XHwIcap_mIntrDisable XHwIcap_IntrDisable
+#endif
+
+#ifndef XHwIcap_mIntrEnable
+#define XHwIcap_mIntrEnable XHwIcap_IntrEnable
+#endif
+
+#ifndef XHwIcap_mIntrGetEnabled
+#define XHwIcap_mIntrGetEnabled XHwIcap_IntrGetEnabled
+#endif
+
+#ifndef XHwIcap_mIntrClear
+#define XHwIcap_mIntrClear XHwIcap_IntrClear
+#endif
+
+#ifndef XHwIcap_mGetWrFifoVacancy
+#define XHwIcap_mGetWrFifoVacancy XHwIcap_GetWrFifoVacancy
+#endif
+
+#ifndef XHwIcap_mGetRdFifoOccupancy
+#define XHwIcap_mGetRdFifoOccupancy XHwIcap_GetRdFifoOccupancy
+#endif
+
+#ifndef XHwIcap_mSliceX2Col
+#define XHwIcap_mSliceX2Col XHwIcap_SliceX2Col
+#endif
+
+#ifndef XHwIcap_mSliceY2Row
+#define XHwIcap_mSliceY2Row XHwIcap_SliceY2Row
+#endif
+
+#ifndef XHwIcap_mSliceXY2Slice
+#define XHwIcap_mSliceXY2Slice XHwIcap_SliceXY2Slice
+#endif
+
+#ifndef XHwIcap_mReadReg
+#define XHwIcap_mReadReg XHwIcap_ReadReg
+#endif
+
+#ifndef XHwIcap_mWriteReg
+#define XHwIcap_mWriteReg XHwIcap_WriteReg
+#endif
+
+/*********************************************************************/
+/**
+ * Macros for Driver XIic
+ *
+ *********************************************************************/
+#ifndef XIic_mReadReg
+#define XIic_mReadReg XIic_ReadReg
+#endif
+
+#ifndef XIic_mWriteReg
+#define XIic_mWriteReg XIic_WriteReg
+#endif
+
+#ifndef XIic_mEnterCriticalRegion
+#define XIic_mEnterCriticalRegion XIic_IntrGlobalDisable
+#endif
+
+#ifndef XIic_mExitCriticalRegion
+#define XIic_mExitCriticalRegion XIic_IntrGlobalEnable
+#endif
+
+#ifndef XIIC_GINTR_DISABLE
+#define XIIC_GINTR_DISABLE XIic_IntrGlobalDisable
+#endif
+
+#ifndef XIIC_GINTR_ENABLE
+#define XIIC_GINTR_ENABLE XIic_IntrGlobalEnable
+#endif
+
+#ifndef XIIC_IS_GINTR_ENABLED
+#define XIIC_IS_GINTR_ENABLED XIic_IsIntrGlobalEnabled
+#endif
+
+#ifndef XIIC_WRITE_IISR
+#define XIIC_WRITE_IISR XIic_WriteIisr
+#endif
+
+#ifndef XIIC_READ_IISR
+#define XIIC_READ_IISR XIic_ReadIisr
+#endif
+
+#ifndef XIIC_WRITE_IIER
+#define XIIC_WRITE_IIER XIic_WriteIier
+#endif
+
+#ifndef XIic_mClearIisr
+#define XIic_mClearIisr XIic_ClearIisr
+#endif
+
+#ifndef XIic_mSend7BitAddress
+#define XIic_mSend7BitAddress XIic_Send7BitAddress
+#endif
+
+#ifndef XIic_mDynSend7BitAddress
+#define XIic_mDynSend7BitAddress XIic_DynSend7BitAddress
+#endif
+
+#ifndef XIic_mDynSendStartStopAddress
+#define XIic_mDynSendStartStopAddress XIic_DynSendStartStopAddress
+#endif
+
+#ifndef XIic_mDynSendStop
+#define XIic_mDynSendStop XIic_DynSendStop
+#endif
+
+#ifndef XIic_mSend10BitAddrByte1
+#define XIic_mSend10BitAddrByte1 XIic_Send10BitAddrByte1
+#endif
+
+#ifndef XIic_mSend10BitAddrByte2
+#define XIic_mSend10BitAddrByte2 XIic_Send10BitAddrByte2
+#endif
+
+#ifndef XIic_mSend7BitAddr
+#define XIic_mSend7BitAddr XIic_Send7BitAddr
+#endif
+
+#ifndef XIic_mDisableIntr
+#define XIic_mDisableIntr XIic_DisableIntr
+#endif
+
+#ifndef XIic_mEnableIntr
+#define XIic_mEnableIntr XIic_EnableIntr
+#endif
+
+#ifndef XIic_mClearIntr
+#define XIic_mClearIntr XIic_ClearIntr
+#endif
+
+#ifndef XIic_mClearEnableIntr
+#define XIic_mClearEnableIntr XIic_ClearEnableIntr
+#endif
+
+#ifndef XIic_mFlushRxFifo
+#define XIic_mFlushRxFifo XIic_FlushRxFifo
+#endif
+
+#ifndef XIic_mFlushTxFifo
+#define XIic_mFlushTxFifo XIic_FlushTxFifo
+#endif
+
+#ifndef XIic_mReadRecvByte
+#define XIic_mReadRecvByte XIic_ReadRecvByte
+#endif
+
+#ifndef XIic_mWriteSendByte
+#define XIic_mWriteSendByte XIic_WriteSendByte
+#endif
+
+#ifndef XIic_mSetControlRegister
+#define XIic_mSetControlRegister XIic_SetControlRegister
+#endif
+
+/*********************************************************************/
+/**
+ * Macros for Driver XIntc
+ *
+ *********************************************************************/
+#ifndef XIntc_mMasterEnable
+#define XIntc_mMasterEnable XIntc_MasterEnable
+#endif
+
+#ifndef XIntc_mMasterDisable
+#define XIntc_mMasterDisable XIntc_MasterDisable
+#endif
+
+#ifndef XIntc_mEnableIntr
+#define XIntc_mEnableIntr XIntc_EnableIntr
+#endif
+
+#ifndef XIntc_mDisableIntr
+#define XIntc_mDisableIntr XIntc_DisableIntr
+#endif
+
+#ifndef XIntc_mAckIntr
+#define XIntc_mAckIntr XIntc_AckIntr
+#endif
+
+#ifndef XIntc_mGetIntrStatus
+#define XIntc_mGetIntrStatus XIntc_GetIntrStatus
+#endif
+
+/*********************************************************************/
+/**
+ * Macros for Driver XLlDma
+ *
+ *********************************************************************/
+#ifndef XLlDma_mBdRead
+#define XLlDma_mBdRead XLlDma_BdRead
+#endif
+
+#ifndef XLlDma_mBdWrite
+#define XLlDma_mBdWrite XLlDma_BdWrite
+#endif
+
+#ifndef XLlDma_mWriteReg
+#define XLlDma_mWriteReg XLlDma_WriteReg
+#endif
+
+#ifndef XLlDma_mReadReg
+#define XLlDma_mReadReg XLlDma_ReadReg
+#endif
+
+#ifndef XLlDma_mBdClear
+#define XLlDma_mBdClear XLlDma_BdClear
+#endif
+
+#ifndef XLlDma_mBdSetStsCtrl
+#define XLlDma_mBdSetStsCtrl XLlDma_BdSetStsCtrl
+#endif
+
+#ifndef XLlDma_mBdGetStsCtrl
+#define XLlDma_mBdGetStsCtrl XLlDma_BdGetStsCtrl
+#endif
+
+#ifndef XLlDma_mBdSetLength
+#define XLlDma_mBdSetLength XLlDma_BdSetLength
+#endif
+
+#ifndef XLlDma_mBdGetLength
+#define XLlDma_mBdGetLength XLlDma_BdGetLength
+#endif
+
+#ifndef XLlDma_mBdSetId
+#define XLlDma_mBdSetId XLlDma_BdSetId
+#endif
+
+#ifndef XLlDma_mBdGetId
+#define XLlDma_mBdGetId XLlDma_BdGetId
+#endif
+
+#ifndef XLlDma_mBdSetBufAddr
+#define XLlDma_mBdSetBufAddr XLlDma_BdSetBufAddr
+#endif
+
+#ifndef XLlDma_mBdGetBufAddr
+#define XLlDma_mBdGetBufAddr XLlDma_BdGetBufAddr
+#endif
+
+#ifndef XLlDma_mBdGetLength
+#define XLlDma_mBdGetLength XLlDma_BdGetLength
+#endif
+
+#ifndef XLlDma_mGetTxRing
+#define XLlDma_mGetTxRing XLlDma_GetTxRing
+#endif
+
+#ifndef XLlDma_mGetRxRing
+#define XLlDma_mGetRxRing XLlDma_GetRxRing
+#endif
+
+#ifndef XLlDma_mGetCr
+#define XLlDma_mGetCr XLlDma_GetCr
+#endif
+
+#ifndef XLlDma_mSetCr
+#define XLlDma_mSetCr XLlDma_SetCr
+#endif
+
+#ifndef XLlDma_mBdRingCntCalc
+#define XLlDma_mBdRingCntCalc XLlDma_BdRingCntCalc
+#endif
+
+#ifndef XLlDma_mBdRingMemCalc
+#define XLlDma_mBdRingMemCalc XLlDma_BdRingMemCalc
+#endif
+
+#ifndef XLlDma_mBdRingGetCnt
+#define XLlDma_mBdRingGetCnt XLlDma_BdRingGetCnt
+#endif
+
+#ifndef XLlDma_mBdRingGetFreeCnt
+#define XLlDma_mBdRingGetFreeCnt XLlDma_BdRingGetFreeCnt
+#endif
+
+#ifndef XLlDma_mBdRingSnapShotCurrBd
+#define XLlDma_mBdRingSnapShotCurrBd XLlDma_BdRingSnapShotCurrBd
+#endif
+
+#ifndef XLlDma_mBdRingNext
+#define XLlDma_mBdRingNext XLlDma_BdRingNext
+#endif
+
+#ifndef XLlDma_mBdRingPrev
+#define XLlDma_mBdRingPrev XLlDma_BdRingPrev
+#endif
+
+#ifndef XLlDma_mBdRingGetSr
+#define XLlDma_mBdRingGetSr XLlDma_BdRingGetSr
+#endif
+
+#ifndef XLlDma_mBdRingSetSr
+#define XLlDma_mBdRingSetSr XLlDma_BdRingSetSr
+#endif
+
+#ifndef XLlDma_mBdRingGetCr
+#define XLlDma_mBdRingGetCr XLlDma_BdRingGetCr
+#endif
+
+#ifndef XLlDma_mBdRingSetCr
+#define XLlDma_mBdRingSetCr XLlDma_BdRingSetCr
+#endif
+
+#ifndef XLlDma_mBdRingBusy
+#define XLlDma_mBdRingBusy XLlDma_BdRingBusy
+#endif
+
+#ifndef XLlDma_mBdRingIntEnable
+#define XLlDma_mBdRingIntEnable XLlDma_BdRingIntEnable
+#endif
+
+#ifndef XLlDma_mBdRingIntDisable
+#define XLlDma_mBdRingIntDisable XLlDma_BdRingIntDisable
+#endif
+
+#ifndef XLlDma_mBdRingIntGetEnabled
+#define XLlDma_mBdRingIntGetEnabled XLlDma_BdRingIntGetEnabled
+#endif
+
+#ifndef XLlDma_mBdRingGetIrq
+#define XLlDma_mBdRingGetIrq XLlDma_BdRingGetIrq
+#endif
+
+#ifndef XLlDma_mBdRingAckIrq
+#define XLlDma_mBdRingAckIrq XLlDma_BdRingAckIrq
+#endif
+
+/*********************************************************************/
+/**
+ * Macros for Driver XMbox
+ *
+ *********************************************************************/
+#ifndef XMbox_mWriteReg
+#define XMbox_mWriteReg XMbox_WriteReg
+#endif
+
+#ifndef XMbox_mReadReg
+#define XMbox_mReadReg XMbox_ReadReg
+#endif
+
+#ifndef XMbox_mWriteMBox
+#define XMbox_mWriteMBox XMbox_WriteMBox
+#endif
+
+#ifndef XMbox_mReadMBox
+#define XMbox_mReadMBox XMbox_ReadMBox
+#endif
+
+#ifndef XMbox_mFSLReadMBox
+#define XMbox_mFSLReadMBox XMbox_FSLReadMBox
+#endif
+
+#ifndef XMbox_mFSLWriteMBox
+#define XMbox_mFSLWriteMBox XMbox_FSLWriteMBox
+#endif
+
+#ifndef XMbox_mFSLIsEmpty
+#define XMbox_mFSLIsEmpty XMbox_FSLIsEmpty
+#endif
+
+#ifndef XMbox_mFSLIsFull
+#define XMbox_mFSLIsFull XMbox_FSLIsFull
+#endif
+
+#ifndef XMbox_mIsEmpty
+#define XMbox_mIsEmpty XMbox_IsEmptyHw
+#endif
+
+#ifndef XMbox_mIsFull
+#define XMbox_mIsFull XMbox_IsFullHw
+#endif
+
+/*********************************************************************/
+/**
+ * Macros for Driver XMpmc
+ *
+ *********************************************************************/
+#ifndef XMpmc_mReadReg
+#define XMpmc_mReadReg XMpmc_ReadReg
+#endif
+
+#ifndef XMpmc_mWriteReg
+#define XMpmc_mWriteReg XMpmc_WriteReg
+#endif
+
+/*********************************************************************/
+/**
+ * Macros for Driver XMutex
+ *
+ *********************************************************************/
+#ifndef XMutex_mWriteReg
+#define XMutex_mWriteReg XMutex_WriteReg
+#endif
+
+#ifndef XMutex_mReadReg
+#define XMutex_mReadReg XMutex_ReadReg
+#endif
+
+/*********************************************************************/
+/**
+ * Macros for Driver XPcie
+ *
+ *********************************************************************/
+#ifndef XPcie_mReadReg
+#define XPcie_mReadReg XPcie_ReadReg
+#endif
+
+#ifndef XPcie_mWriteReg
+#define XPcie_mWriteReg XPcie_WriteReg
+#endif
+
+/*********************************************************************/
+/**
+ * Macros for Driver XSpi
+ *
+ *********************************************************************/
+#ifndef XSpi_mIntrGlobalEnable
+#define XSpi_mIntrGlobalEnable XSpi_IntrGlobalEnable
+#endif
+
+#ifndef XSpi_mIntrGlobalDisable
+#define XSpi_mIntrGlobalDisable XSpi_IntrGlobalDisable
+#endif
+
+#ifndef XSpi_mIsIntrGlobalEnabled
+#define XSpi_mIsIntrGlobalEnabled XSpi_IsIntrGlobalEnabled
+#endif
+
+#ifndef XSpi_mIntrGetStatus
+#define XSpi_mIntrGetStatus XSpi_IntrGetStatus
+#endif
+
+#ifndef XSpi_mIntrClear
+#define XSpi_mIntrClear XSpi_IntrClear
+#endif
+
+#ifndef XSpi_mIntrEnable
+#define XSpi_mIntrEnable XSpi_IntrEnable
+#endif
+
+#ifndef XSpi_mIntrDisable
+#define XSpi_mIntrDisable XSpi_IntrDisable
+#endif
+
+#ifndef XSpi_mIntrGetEnabled
+#define XSpi_mIntrGetEnabled XSpi_IntrGetEnabled
+#endif
+
+#ifndef XSpi_mSetControlReg
+#define XSpi_mSetControlReg XSpi_SetControlReg
+#endif
+
+#ifndef XSpi_mGetControlReg
+#define XSpi_mGetControlReg XSpi_GetControlReg
+#endif
+
+#ifndef XSpi_mGetStatusReg
+#define XSpi_mGetStatusReg XSpi_GetStatusReg
+#endif
+
+#ifndef XSpi_mSetSlaveSelectReg
+#define XSpi_mSetSlaveSelectReg XSpi_SetSlaveSelectReg
+#endif
+
+#ifndef XSpi_mGetSlaveSelectReg
+#define XSpi_mGetSlaveSelectReg XSpi_GetSlaveSelectReg
+#endif
+
+#ifndef XSpi_mEnable
+#define XSpi_mEnable XSpi_Enable
+#endif
+
+#ifndef XSpi_mDisable
+#define XSpi_mDisable XSpi_Disable
+#endif
+
+/*********************************************************************/
+/**
+ * Macros for Driver XSysAce
+ *
+ *********************************************************************/
+#ifndef XSysAce_mGetControlReg
+#define XSysAce_mGetControlReg XSysAce_GetControlReg
+#endif
+
+#ifndef XSysAce_mSetControlReg
+#define XSysAce_mSetControlReg XSysAce_SetControlReg
+#endif
+
+#ifndef XSysAce_mOrControlReg
+#define XSysAce_mOrControlReg XSysAce_OrControlReg
+#endif
+
+#ifndef XSysAce_mAndControlReg
+#define XSysAce_mAndControlReg XSysAce_AndControlReg
+#endif
+
+#ifndef XSysAce_mGetErrorReg
+#define XSysAce_mGetErrorReg XSysAce_GetErrorReg
+#endif
+
+#ifndef XSysAce_mGetStatusReg
+#define XSysAce_mGetStatusReg XSysAce_GetStatusReg
+#endif
+
+#ifndef XSysAce_mWaitForLock
+#define XSysAce_mWaitForLock XSysAce_WaitForLock
+#endif
+
+#ifndef XSysAce_mEnableIntr
+#define XSysAce_mEnableIntr XSysAce_EnableIntr
+#endif
+
+#ifndef XSysAce_mDisableIntr
+#define XSysAce_mDisableIntr XSysAce_DisableIntr
+#endif
+
+#ifndef XSysAce_mIsReadyForCmd
+#define XSysAce_mIsReadyForCmd XSysAce_IsReadyForCmd
+#endif
+
+#ifndef XSysAce_mIsMpuLocked
+#define XSysAce_mIsMpuLocked XSysAce_IsMpuLocked
+#endif
+
+#ifndef XSysAce_mIsIntrEnabled
+#define XSysAce_mIsIntrEnabled XSysAce_IsIntrEnabled
+#endif
+
+/*********************************************************************/
+/**
+ * Macros for Driver XSysMon
+ *
+ *********************************************************************/
+#ifndef XSysMon_mIsEventSamplingModeSet
+#define XSysMon_mIsEventSamplingModeSet XSysMon_IsEventSamplingModeSet
+#endif
+
+#ifndef XSysMon_mIsDrpBusy
+#define XSysMon_mIsDrpBusy XSysMon_IsDrpBusy
+#endif
+
+#ifndef XSysMon_mIsDrpLocked
+#define XSysMon_mIsDrpLocked XSysMon_IsDrpLocked
+#endif
+
+#ifndef XSysMon_mRawToTemperature
+#define XSysMon_mRawToTemperature XSysMon_RawToTemperature
+#endif
+
+#ifndef XSysMon_mRawToVoltage
+#define XSysMon_mRawToVoltage XSysMon_RawToVoltage
+#endif
+
+#ifndef XSysMon_mTemperatureToRaw
+#define XSysMon_mTemperatureToRaw XSysMon_TemperatureToRaw
+#endif
+
+#ifndef XSysMon_mVoltageToRaw
+#define XSysMon_mVoltageToRaw XSysMon_VoltageToRaw
+#endif
+
+#ifndef XSysMon_mReadReg
+#define XSysMon_mReadReg XSysMon_ReadReg
+#endif
+
+#ifndef XSysMon_mWriteReg
+#define XSysMon_mWriteReg XSysMon_WriteReg
+#endif
+
+/*********************************************************************/
+/**
+ * Macros for Driver XTmrCtr
+ *
+ *********************************************************************/
+#ifndef XTimerCtr_mReadReg
+#define XTimerCtr_mReadReg XTimerCtr_ReadReg
+#endif
+
+#ifndef XTmrCtr_mWriteReg
+#define XTmrCtr_mWriteReg XTmrCtr_WriteReg
+#endif
+
+#ifndef XTmrCtr_mSetControlStatusReg
+#define XTmrCtr_mSetControlStatusReg XTmrCtr_SetControlStatusReg
+#endif
+
+#ifndef XTmrCtr_mGetControlStatusReg
+#define XTmrCtr_mGetControlStatusReg XTmrCtr_GetControlStatusReg
+#endif
+
+#ifndef XTmrCtr_mGetTimerCounterReg
+#define XTmrCtr_mGetTimerCounterReg XTmrCtr_GetTimerCounterReg
+#endif
+
+#ifndef XTmrCtr_mSetLoadReg
+#define XTmrCtr_mSetLoadReg XTmrCtr_SetLoadReg
+#endif
+
+#ifndef XTmrCtr_mGetLoadReg
+#define XTmrCtr_mGetLoadReg XTmrCtr_GetLoadReg
+#endif
+
+#ifndef XTmrCtr_mEnable
+#define XTmrCtr_mEnable XTmrCtr_Enable
+#endif
+
+#ifndef XTmrCtr_mDisable
+#define XTmrCtr_mDisable XTmrCtr_Disable
+#endif
+
+#ifndef XTmrCtr_mEnableIntr
+#define XTmrCtr_mEnableIntr XTmrCtr_EnableIntr
+#endif
+
+#ifndef XTmrCtr_mDisableIntr
+#define XTmrCtr_mDisableIntr XTmrCtr_DisableIntr
+#endif
+
+#ifndef XTmrCtr_mLoadTimerCounterReg
+#define XTmrCtr_mLoadTimerCounterReg XTmrCtr_LoadTimerCounterReg
+#endif
+
+#ifndef XTmrCtr_mHasEventOccurred
+#define XTmrCtr_mHasEventOccurred XTmrCtr_HasEventOccurred
+#endif
+
+/*********************************************************************/
+/**
+ * Macros for Driver XUartLite
+ *
+ *********************************************************************/
+#ifndef XUartLite_mUpdateStats
+#define XUartLite_mUpdateStats XUartLite_UpdateStats
+#endif
+
+#ifndef XUartLite_mWriteReg
+#define XUartLite_mWriteReg XUartLite_WriteReg
+#endif
+
+#ifndef XUartLite_mReadReg
+#define XUartLite_mReadReg XUartLite_ReadReg
+#endif
+
+#ifndef XUartLite_mClearStats
+#define XUartLite_mClearStats XUartLite_ClearStats
+#endif
+
+#ifndef XUartLite_mSetControlReg
+#define XUartLite_mSetControlReg XUartLite_SetControlReg
+#endif
+
+#ifndef XUartLite_mGetStatusReg
+#define XUartLite_mGetStatusReg XUartLite_GetStatusReg
+#endif
+
+#ifndef XUartLite_mIsReceiveEmpty
+#define XUartLite_mIsReceiveEmpty XUartLite_IsReceiveEmpty
+#endif
+
+#ifndef XUartLite_mIsTransmitFull
+#define XUartLite_mIsTransmitFull XUartLite_IsTransmitFull
+#endif
+
+#ifndef XUartLite_mIsIntrEnabled
+#define XUartLite_mIsIntrEnabled XUartLite_IsIntrEnabled
+#endif
+
+#ifndef XUartLite_mEnableIntr
+#define XUartLite_mEnableIntr XUartLite_EnableIntr
+#endif
+
+#ifndef XUartLite_mDisableIntr
+#define XUartLite_mDisableIntr XUartLite_DisableIntr
+#endif
+
+/*********************************************************************/
+/**
+ * Macros for Driver XUartNs550
+ *
+ *********************************************************************/
+#ifndef XUartNs550_mUpdateStats
+#define XUartNs550_mUpdateStats XUartNs550_UpdateStats
+#endif
+
+#ifndef XUartNs550_mReadReg
+#define XUartNs550_mReadReg XUartNs550_ReadReg
+#endif
+
+#ifndef XUartNs550_mWriteReg
+#define XUartNs550_mWriteReg XUartNs550_WriteReg
+#endif
+
+#ifndef XUartNs550_mClearStats
+#define XUartNs550_mClearStats XUartNs550_ClearStats
+#endif
+
+#ifndef XUartNs550_mGetLineStatusReg
+#define XUartNs550_mGetLineStatusReg XUartNs550_GetLineStatusReg
+#endif
+
+#ifndef XUartNs550_mGetLineControlReg
+#define XUartNs550_mGetLineControlReg XUartNs550_GetLineControlReg
+#endif
+
+#ifndef XUartNs550_mSetLineControlReg
+#define XUartNs550_mSetLineControlReg XUartNs550_SetLineControlReg
+#endif
+
+#ifndef XUartNs550_mEnableIntr
+#define XUartNs550_mEnableIntr XUartNs550_EnableIntr
+#endif
+
+#ifndef XUartNs550_mDisableIntr
+#define XUartNs550_mDisableIntr XUartNs550_DisableIntr
+#endif
+
+#ifndef XUartNs550_mIsReceiveData
+#define XUartNs550_mIsReceiveData XUartNs550_IsReceiveData
+#endif
+
+#ifndef XUartNs550_mIsTransmitEmpty
+#define XUartNs550_mIsTransmitEmpty XUartNs550_IsTransmitEmpty
+#endif
+
+/*********************************************************************/
+/**
+ * Macros for Driver XUsb
+ *
+ *********************************************************************/
+#ifndef XUsb_mReadReg
+#define XUsb_mReadReg XUsb_ReadReg
+#endif
+
+#ifndef XUsb_mWriteReg
+#define XUsb_mWriteReg XUsb_WriteReg
+#endif
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff --git a/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v7_1/src/xil_mem.c b/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v7_1/src/xil_mem.c
new file mode 100644
index 0000000..4db526c
--- /dev/null
+++ b/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v7_1/src/xil_mem.c
@@ -0,0 +1,83 @@
+/******************************************************************************/
+/**
+* Copyright (C) 2015 - 2016 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+* THE SOFTWARE.
+*
+*
+*
+******************************************************************************/
+/****************************************************************************/
+/**
+* @file xil_mem.c
+*
+* This file contains xil mem copy function to use in case of word aligned
+* data copies.
+*
+* <pre>
+* MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ----- -------- -------- -----------------------------------------------
+* 6.1 nsk 11/07/16 First release.
+*
+* </pre>
+*
+*****************************************************************************/
+
+/***************************** Include Files ********************************/
+
+#include "xil_types.h"
+
+/***************** Inline Functions Definitions ********************/
+/*****************************************************************************/
+/**
+* @brief This function copies memory from once location to other.
+*
+* @param dst: pointer pointing to destination memory
+*
+* @param src: pointer pointing to source memory
+*
+* @param cnt: 32 bit length of bytes to be copied
+*
+*****************************************************************************/
+void Xil_MemCpy(void* dst, const void* src, u32 cnt)
+{
+ char *d = (char*)(void *)dst;
+ const char *s = src;
+
+ while (cnt >= sizeof (int)) {
+ *(int*)d = *(int*)s;
+ d += sizeof (int);
+ s += sizeof (int);
+ cnt -= sizeof (int);
+ }
+ while (cnt >= sizeof (u16)) {
+ *(u16*)d = *(u16*)s;
+ d += sizeof (u16);
+ s += sizeof (u16);
+ cnt -= sizeof (u16);
+ }
+ while ((cnt) > 0U){
+ *d = *s;
+ d += 1U;
+ s += 1U;
+ cnt -= 1U;
+ }
+}
diff --git a/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v7_1/src/xil_mem.h b/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v7_1/src/xil_mem.h
new file mode 100644
index 0000000..4327b96
--- /dev/null
+++ b/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v7_1/src/xil_mem.h
@@ -0,0 +1,66 @@
+/******************************************************************************/
+/**
+* Copyright (C) 2015 - 2019 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+* THE SOFTWARE.
+*
+*
+*
+******************************************************************************/
+/****************************************************************************/
+/**
+* @file xil_mem.h
+*
+* @addtogroup common_mem_operation_api Customized APIs for Memory Operations
+*
+* The xil_mem.h file contains prototype for functions related
+* to memory operations. These APIs are applicable for all processors supported
+* by Xilinx.
+*
+* @{
+* <pre>
+* MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ----- -------- -------- -----------------------------------------------
+* 6.1 nsk 11/07/16 First release.
+* 7.0 mus 01/07/19 Add cpp extern macro
+*
+* </pre>
+*
+*****************************************************************************/
+#ifndef XIL_MEM_H /* prevent circular inclusions */
+#define XIL_MEM_H /* by using protection macros */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/************************** Function Prototypes *****************************/
+
+void Xil_MemCpy(void* dst, const void* src, u32 cnt);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* XIL_MEM_H */
+/**
+* @} End of "addtogroup common_mem_operation_api".
+*/
\ No newline at end of file
diff --git a/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v7_1/src/xil_misc_psreset_api.c b/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v7_1/src/xil_misc_psreset_api.c
new file mode 100644
index 0000000..1802e8c
--- /dev/null
+++ b/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v7_1/src/xil_misc_psreset_api.c
@@ -0,0 +1,518 @@
+/******************************************************************************
+*
+* Copyright (C) 2013 - 2015 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+* THE SOFTWARE.
+*
+*
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xil_misc_reset.c
+*
+* This file contains the implementation of the reset sequence for various
+* zynq ps devices like DDR,OCM,Slcr,Ethernet,Usb.. controllers. The reset
+* sequence provided to the interfaces is based on the provision in
+* slcr reset functional block.
+*
+* <pre>
+* MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ----- ---- -------- -------------------------------------------------------
+* 1.00b kpc 03/07/13 First release
+* 5.4 pkp 09/11/15 Change the description for XOcm_Remap function
+* </pre>
+*
+******************************************************************************/
+
+
+/***************************** Include Files *********************************/
+#include "xil_misc_psreset_api.h"
+
+/************************** Constant Definitions *****************************/
+
+
+/**************************** Type Definitions *******************************/
+
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+
+/************************** Function Prototypes ******************************/
+
+
+/*****************************************************************************/
+/**
+* This function contains the implementation for ddr reset.
+*
+* @param N/A.
+*
+* @return N/A.
+*
+* @note None.
+*
+******************************************************************************/
+void XDdr_ResetHw(void)
+{
+ u32 RegVal;
+
+ /* Unlock the slcr register access lock */
+ Xil_Out32(XSLCR_UNLOCK_ADDR, XSLCR_UNLOCK_CODE);
+ /* Assert and deassert the ddr softreset bit */
+ RegVal = Xil_In32(XDDRC_CTRL_BASEADDR);
+ RegVal &= (u32)(~XDDRPS_CTRL_RESET_MASK);
+ Xil_Out32(XDDRC_CTRL_BASEADDR,RegVal);
+ RegVal |= ((u32)XDDRPS_CTRL_RESET_MASK);
+ Xil_Out32(XDDRC_CTRL_BASEADDR,RegVal);
+
+}
+
+/*****************************************************************************/
+/**
+* This function contains the implementation for remapping the ocm memory region
+* to postbootrom state.
+*
+* @param N/A.
+*
+* @return N/A.
+*
+* @note None.
+*
+******************************************************************************/
+void XOcm_Remap(void)
+{
+ u32 RegVal;
+
+ /* Unlock the slcr register access lock */
+ Xil_Out32(XSLCR_UNLOCK_ADDR, XSLCR_UNLOCK_CODE);
+ /* Map the ocm region to postbootrom state */
+ RegVal = Xil_In32(XSLCR_OCM_CFG_ADDR);
+ RegVal = (RegVal & (u32)(~XSLCR_OCM_CFG_HIADDR_MASK)) | (u32)XSLCR_OCM_CFG_RESETVAL;
+ Xil_Out32(XSLCR_OCM_CFG_ADDR, RegVal);
+}
+
+/*****************************************************************************/
+/**
+* This function contains the implementation for SMC reset sequence
+*
+* @param BaseAddress of the interface
+*
+* @return N/A.
+*
+* @note None.
+*
+******************************************************************************/
+void XSmc_ResetHw(u32 BaseAddress)
+{
+ u32 RegVal;
+
+ /* Clear the interuupts */
+ RegVal = Xil_In32(BaseAddress + XSMC_MEMC_CLR_CONFIG_OFFSET);
+ RegVal = RegVal | (u32)XSMC_MEMC_CLR_CONFIG_MASK;
+ Xil_Out32(BaseAddress + XSMC_MEMC_CLR_CONFIG_OFFSET, RegVal);
+ /* Clear the idle counter registers */
+ Xil_Out32(BaseAddress + XSMC_REFRESH_PERIOD_0_OFFSET, 0x0U);
+ Xil_Out32(BaseAddress + XSMC_REFRESH_PERIOD_1_OFFSET, 0x0U);
+ /* Update the ecc registers with reset values */
+ Xil_Out32(BaseAddress + XSMC_ECC_MEMCFG1_OFFSET,
+ XSMC_ECC_MEMCFG1_RESET_VAL);
+ Xil_Out32(BaseAddress + XSMC_ECC_MEMCMD1_OFFSET,
+ XSMC_ECC_MEMCMD1_RESET_VAL);
+ Xil_Out32(BaseAddress + XSMC_ECC_MEMCMD2_OFFSET,
+ XSMC_ECC_MEMCMD2_RESET_VAL);
+
+}
+
+/*****************************************************************************/
+/**
+* This function contains the implementation for updating the slcr mio registers
+* with reset values
+* @param N/A.
+*
+* @return N/A.
+*
+* @note None.
+*
+******************************************************************************/
+void XSlcr_MioWriteResetValues(void)
+{
+ u32 i;
+
+ /* Unlock the slcr register access lock */
+ Xil_Out32(XSLCR_UNLOCK_ADDR, XSLCR_UNLOCK_CODE);
+ /* Update all the MIO registers with reset values */
+ for (i=0U; i<=1U;i++)
+ {
+ Xil_Out32((XSLCR_MIO_PIN_00_ADDR + (i * 4U)),
+ XSLCR_MIO_PIN_00_RESET_VAL);
+ }
+ for (; i<=8U;i++)
+ {
+ Xil_Out32((XSLCR_MIO_PIN_00_ADDR + (i * 4U)),
+ XSLCR_MIO_PIN_02_RESET_VAL);
+ }
+ for (; i<=53U ;i++)
+ {
+ Xil_Out32((XSLCR_MIO_PIN_00_ADDR + (i * 4U)),
+ XSLCR_MIO_PIN_00_RESET_VAL);
+ }
+
+
+}
+
+/*****************************************************************************/
+/**
+* This function contains the implementation for updating the slcr pll registers
+* with reset values
+* @param N/A.
+*
+* @return N/A.
+*
+* @note None.
+*
+******************************************************************************/
+void XSlcr_PllWriteResetValues(void)
+{
+
+ /* Unlock the slcr register access lock */
+ Xil_Out32(XSLCR_UNLOCK_ADDR, XSLCR_UNLOCK_CODE);
+
+ /* update the pll control registers with reset values */
+ Xil_Out32(XSLCR_IO_PLL_CTRL_ADDR, XSLCR_IO_PLL_CTRL_RESET_VAL);
+ Xil_Out32(XSLCR_ARM_PLL_CTRL_ADDR, XSLCR_ARM_PLL_CTRL_RESET_VAL);
+ Xil_Out32(XSLCR_DDR_PLL_CTRL_ADDR, XSLCR_DDR_PLL_CTRL_RESET_VAL);
+ /* update the pll config registers with reset values */
+ Xil_Out32(XSLCR_IO_PLL_CFG_ADDR, XSLCR_IO_PLL_CFG_RESET_VAL);
+ Xil_Out32(XSLCR_ARM_PLL_CFG_ADDR, XSLCR_ARM_PLL_CFG_RESET_VAL);
+ Xil_Out32(XSLCR_DDR_PLL_CFG_ADDR, XSLCR_DDR_PLL_CFG_RESET_VAL);
+ /* update the clock control registers with reset values */
+ Xil_Out32(XSLCR_ARM_CLK_CTRL_ADDR, XSLCR_ARM_CLK_CTRL_RESET_VAL);
+ Xil_Out32(XSLCR_DDR_CLK_CTRL_ADDR, XSLCR_DDR_CLK_CTRL_RESET_VAL);
+}
+
+/*****************************************************************************/
+/**
+* This function contains the implementation for disabling the level shifters
+*
+* @param N/A.
+*
+* @return N/A.
+*
+* @note None.
+*
+******************************************************************************/
+void XSlcr_DisableLevelShifters(void)
+{
+ u32 RegVal;
+ /* Unlock the slcr register access lock */
+ Xil_Out32(XSLCR_UNLOCK_ADDR, XSLCR_UNLOCK_CODE);
+ /* Disable the level shifters */
+ RegVal = Xil_In32(XSLCR_LVL_SHFTR_EN_ADDR);
+ RegVal = RegVal & (u32)(~XSLCR_LVL_SHFTR_EN_MASK);
+ Xil_Out32(XSLCR_LVL_SHFTR_EN_ADDR, RegVal);
+
+}
+/*****************************************************************************/
+/**
+* This function contains the implementation for OCM software reset from the
+* slcr
+*
+* @param N/A.
+*
+* @return N/A.
+*
+* @note None.
+*
+******************************************************************************/
+void XSlcr_OcmReset(void)
+{
+ u32 RegVal;
+ /* Unlock the slcr register access lock */
+ Xil_Out32(XSLCR_UNLOCK_ADDR, XSLCR_UNLOCK_CODE);
+ /* Assert the reset */
+ RegVal = Xil_In32(XSLCR_OCM_RST_CTRL_ADDR);
+ RegVal = RegVal | ((u32)XSLCR_OCM_RST_CTRL_VAL);
+ Xil_Out32(XSLCR_OCM_RST_CTRL_ADDR, RegVal);
+ /* Release the reset */
+ RegVal = Xil_In32(XSLCR_OCM_RST_CTRL_ADDR);
+ RegVal = RegVal & (u32)(~XSLCR_OCM_RST_CTRL_VAL);
+ Xil_Out32(XSLCR_OCM_RST_CTRL_ADDR, RegVal);
+}
+
+/*****************************************************************************/
+/**
+* This function contains the implementation for Ethernet software reset from
+* the slcr
+* @param N/A.
+*
+* @return N/A.
+*
+* @note None.
+*
+******************************************************************************/
+void XSlcr_EmacPsReset(void)
+{
+ u32 RegVal;
+ /* Unlock the slcr register access lock */
+ Xil_Out32(XSLCR_UNLOCK_ADDR, XSLCR_UNLOCK_CODE);
+ /* Assert the reset */
+ RegVal = Xil_In32(XSLCR_GEM_RST_CTRL_ADDR);
+ RegVal = RegVal | ((u32)XSLCR_GEM_RST_CTRL_VAL);
+ Xil_Out32(XSLCR_GEM_RST_CTRL_ADDR, RegVal);
+ /* Release the reset */
+ RegVal = Xil_In32(XSLCR_GEM_RST_CTRL_ADDR);
+ RegVal = RegVal & (u32)(~XSLCR_GEM_RST_CTRL_VAL);
+ Xil_Out32(XSLCR_GEM_RST_CTRL_ADDR, RegVal);
+}
+
+/*****************************************************************************/
+/**
+* This function contains the implementation for USB software reset from the
+* slcr
+*
+* @param N/A.
+*
+* @return N/A.
+*
+* @note None.
+*
+******************************************************************************/
+void XSlcr_UsbPsReset(void)
+{
+ u32 RegVal;
+ /* Unlock the slcr register access lock */
+ Xil_Out32(XSLCR_UNLOCK_ADDR, XSLCR_UNLOCK_CODE);
+ /* Assert the reset */
+ RegVal = Xil_In32(XSLCR_USB_RST_CTRL_ADDR);
+ RegVal = RegVal | ((u32)XSLCR_USB_RST_CTRL_VAL);
+ Xil_Out32(XSLCR_USB_RST_CTRL_ADDR, RegVal);
+ /* Release the reset */
+ RegVal = Xil_In32(XSLCR_USB_RST_CTRL_ADDR);
+ RegVal = RegVal & (u32)(~XSLCR_USB_RST_CTRL_VAL);
+ Xil_Out32(XSLCR_USB_RST_CTRL_ADDR, RegVal);
+}
+/*****************************************************************************/
+/**
+* This function contains the implementation for QSPI software reset from the
+* slcr
+*
+* @param N/A.
+*
+* @return N/A.
+*
+* @note None.
+*
+******************************************************************************/
+void XSlcr_QspiPsReset(void)
+{
+ u32 RegVal;
+ /* Unlock the slcr register access lock */
+ Xil_Out32(XSLCR_UNLOCK_ADDR, XSLCR_UNLOCK_CODE);
+ /* Assert the reset */
+ RegVal = Xil_In32(XSLCR_LQSPI_RST_CTRL_ADDR);
+ RegVal = RegVal | ((u32)XSLCR_QSPI_RST_CTRL_VAL);
+ Xil_Out32(XSLCR_LQSPI_RST_CTRL_ADDR, RegVal);
+ /* Release the reset */
+ RegVal = Xil_In32(XSLCR_LQSPI_RST_CTRL_ADDR);
+ RegVal = RegVal & (u32)(~XSLCR_QSPI_RST_CTRL_VAL);
+ Xil_Out32(XSLCR_LQSPI_RST_CTRL_ADDR, RegVal);
+}
+/*****************************************************************************/
+/**
+* This function contains the implementation for SPI software reset from the
+* slcr
+*
+* @param N/A.
+*
+* @return N/A.
+*
+* @note None.
+*
+******************************************************************************/
+void XSlcr_SpiPsReset(void)
+{
+ u32 RegVal;
+ /* Unlock the slcr register access lock */
+ Xil_Out32(XSLCR_UNLOCK_ADDR, XSLCR_UNLOCK_CODE);
+ /* Assert the reset */
+ RegVal = Xil_In32(XSLCR_SPI_RST_CTRL_ADDR);
+ RegVal = RegVal | ((u32)XSLCR_SPI_RST_CTRL_VAL);
+ Xil_Out32(XSLCR_SPI_RST_CTRL_ADDR, RegVal);
+ /* Release the reset */
+ RegVal = Xil_In32(XSLCR_SPI_RST_CTRL_ADDR);
+ RegVal = RegVal & (u32)(~XSLCR_SPI_RST_CTRL_VAL);
+ Xil_Out32(XSLCR_SPI_RST_CTRL_ADDR, RegVal);
+}
+/*****************************************************************************/
+/**
+* This function contains the implementation for i2c software reset from the slcr
+*
+* @param N/A.
+*
+* @return N/A.
+*
+* @note None.
+*
+******************************************************************************/
+void XSlcr_I2cPsReset(void)
+{
+ u32 RegVal;
+ /* Unlock the slcr register access lock */
+ Xil_Out32(XSLCR_UNLOCK_ADDR, XSLCR_UNLOCK_CODE);
+ /* Assert the reset */
+ RegVal = Xil_In32(XSLCR_I2C_RST_CTRL_ADDR);
+ RegVal = RegVal | ((u32)XSLCR_I2C_RST_CTRL_VAL);
+ Xil_Out32(XSLCR_I2C_RST_CTRL_ADDR, RegVal);
+ /* Release the reset */
+ RegVal = Xil_In32(XSLCR_I2C_RST_CTRL_ADDR);
+ RegVal = RegVal & (u32)(~XSLCR_I2C_RST_CTRL_VAL);
+ Xil_Out32(XSLCR_I2C_RST_CTRL_ADDR, RegVal);
+}
+/*****************************************************************************/
+/**
+* This function contains the implementation for UART software reset from the
+* slcr
+*
+* @param N/A.
+*
+* @return N/A.
+*
+* @note None.
+*
+******************************************************************************/
+void XSlcr_UartPsReset(void)
+{
+ u32 RegVal;
+ /* Unlock the slcr register access lock */
+ Xil_Out32(XSLCR_UNLOCK_ADDR, XSLCR_UNLOCK_CODE);
+ /* Assert the reset */
+ RegVal = Xil_In32(XSLCR_UART_RST_CTRL_ADDR);
+ RegVal = RegVal | ((u32)XSLCR_UART_RST_CTRL_VAL);
+ Xil_Out32(XSLCR_UART_RST_CTRL_ADDR, RegVal);
+ /* Release the reset */
+ RegVal = Xil_In32(XSLCR_UART_RST_CTRL_ADDR);
+ RegVal = RegVal & (u32)(~XSLCR_UART_RST_CTRL_VAL);
+ Xil_Out32(XSLCR_UART_RST_CTRL_ADDR, RegVal);
+}
+/*****************************************************************************/
+/**
+* This function contains the implementation for CAN software reset from slcr
+* registers
+*
+* @param N/A.
+*
+* @return N/A.
+*
+* @note None.
+*
+******************************************************************************/
+void XSlcr_CanPsReset(void)
+{
+ u32 RegVal;
+ /* Unlock the slcr register access lock */
+ Xil_Out32(XSLCR_UNLOCK_ADDR, XSLCR_UNLOCK_CODE);
+ /* Assert the reset */
+ RegVal = Xil_In32(XSLCR_CAN_RST_CTRL_ADDR);
+ RegVal = RegVal | ((u32)XSLCR_CAN_RST_CTRL_VAL);
+ Xil_Out32(XSLCR_CAN_RST_CTRL_ADDR, RegVal);
+ /* Release the reset */
+ RegVal = Xil_In32(XSLCR_CAN_RST_CTRL_ADDR);
+ RegVal = RegVal & (u32)(~XSLCR_CAN_RST_CTRL_VAL);
+ Xil_Out32(XSLCR_CAN_RST_CTRL_ADDR, RegVal);
+}
+/*****************************************************************************/
+/**
+* This function contains the implementation for SMC software reset from the slcr
+*
+* @param N/A.
+*
+* @return N/A.
+*
+* @note None.
+*
+******************************************************************************/
+void XSlcr_SmcPsReset(void)
+{
+ u32 RegVal;
+ /* Unlock the slcr register access lock */
+ Xil_Out32(XSLCR_UNLOCK_ADDR, XSLCR_UNLOCK_CODE);
+ /* Assert the reset */
+ RegVal = Xil_In32(XSLCR_SMC_RST_CTRL_ADDR);
+ RegVal = RegVal | ((u32)XSLCR_SMC_RST_CTRL_VAL);
+ Xil_Out32(XSLCR_SMC_RST_CTRL_ADDR, RegVal);
+ /* Release the reset */
+ RegVal = Xil_In32(XSLCR_SMC_RST_CTRL_ADDR);
+ RegVal = RegVal & (u32)(~XSLCR_SMC_RST_CTRL_VAL);
+ Xil_Out32(XSLCR_SMC_RST_CTRL_ADDR, RegVal);
+}
+/*****************************************************************************/
+/**
+* This function contains the implementation for DMA controller software reset
+* from the slcr
+*
+* @param N/A.
+*
+* @return N/A.
+*
+* @note None.
+*
+******************************************************************************/
+void XSlcr_DmaPsReset(void)
+{
+ u32 RegVal;
+ /* Unlock the slcr register access lock */
+ Xil_Out32(XSLCR_UNLOCK_ADDR, XSLCR_UNLOCK_CODE);
+ /* Assert the reset */
+ RegVal = Xil_In32(XSLCR_DMAC_RST_CTRL_ADDR);
+ RegVal = RegVal | ((u32)XSLCR_DMAC_RST_CTRL_VAL);
+ Xil_Out32(XSLCR_DMAC_RST_CTRL_ADDR, RegVal);
+ /* Release the reset */
+ RegVal = Xil_In32(XSLCR_DMAC_RST_CTRL_ADDR);
+ RegVal = RegVal & (u32)(~XSLCR_DMAC_RST_CTRL_VAL);
+ Xil_Out32(XSLCR_DMAC_RST_CTRL_ADDR, RegVal);
+}
+/*****************************************************************************/
+/**
+* This function contains the implementation for Gpio AMBA software reset from
+* the slcr
+*
+* @param N/A.
+*
+* @return N/A.
+*
+* @note None.
+*
+******************************************************************************/
+void XSlcr_GpioPsReset(void)
+{
+ u32 RegVal;
+ /* Unlock the slcr register access lock */
+ Xil_Out32(XSLCR_UNLOCK_ADDR, XSLCR_UNLOCK_CODE);
+ /* Assert the reset */
+ RegVal = Xil_In32(XSLCR_GPIO_RST_CTRL_ADDR);
+ RegVal = RegVal | ((u32)XSLCR_GPIO_RST_CTRL_VAL);
+ Xil_Out32(XSLCR_GPIO_RST_CTRL_ADDR, RegVal);
+ /* Release the reset */
+ RegVal = Xil_In32(XSLCR_GPIO_RST_CTRL_ADDR);
+ RegVal = RegVal & (u32)(~XSLCR_GPIO_RST_CTRL_VAL);
+ Xil_Out32(XSLCR_GPIO_RST_CTRL_ADDR, RegVal);
+}
diff --git a/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v7_1/src/xil_misc_psreset_api.h b/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v7_1/src/xil_misc_psreset_api.h
new file mode 100644
index 0000000..76e2c1b
--- /dev/null
+++ b/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v7_1/src/xil_misc_psreset_api.h
@@ -0,0 +1,271 @@
+/******************************************************************************
+*
+* Copyright (C) 2013 - 2015 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+* THE SOFTWARE.
+*
+*
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+* @file xil_misc_psreset_api.h
+*
+* This file contains the various register definitions and function prototypes for
+* implementing the reset functionality of zynq ps devices
+*
+* MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ----- ---- -------- -------------------------------------------------------
+* 1.00b kpc 03/07/13 First release.
+* </pre>
+*
+******************************************************************************/
+
+#ifndef XIL_MISC_RESET_H /* prevent circular inclusions */
+#define XIL_MISC_RESET_H /* by using protection macros */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+
+/***************************** Include Files *********************************/
+#include "xil_types.h"
+#include "xil_io.h"
+
+/************************** Constant Definitions *****************************/
+#define XDDRC_CTRL_BASEADDR 0xF8006000U
+#define XSLCR_BASEADDR 0xF8000000U
+/**< OCM configuration register */
+#define XSLCR_OCM_CFG_ADDR (XSLCR_BASEADDR + 0x00000910U)
+/**< SLCR unlock register */
+#define XSLCR_UNLOCK_ADDR (XSLCR_BASEADDR + 0x00000008U)
+/**< SLCR GEM0 rx clock control register */
+#define XSLCR_GEM0_RCLK_CTRL_ADDR (XSLCR_BASEADDR + 0x00000138U)
+/**< SLCR GEM1 rx clock control register */
+#define XSLCR_GEM1_RCLK_CTRL_ADDR (XSLCR_BASEADDR + 0x0000013CU)
+/**< SLCR GEM0 clock control register */
+#define XSLCR_GEM0_CLK_CTRL_ADDR (XSLCR_BASEADDR + 0x00000140U)
+/**< SLCR GEM1 clock control register */
+#define XSLCR_GEM1_CLK_CTRL_ADDR (XSLCR_BASEADDR + 0x00000144U)
+/**< SLCR SMC clock control register */
+#define XSLCR_SMC_CLK_CTRL_ADDR (XSLCR_BASEADDR + 0x00000148U)
+/**< SLCR GEM reset control register */
+#define XSLCR_GEM_RST_CTRL_ADDR (XSLCR_BASEADDR + 0x00000214U)
+/**< SLCR USB0 clock control register */
+#define XSLCR_USB0_CLK_CTRL_ADDR (XSLCR_BASEADDR + 0x00000130U)
+/**< SLCR USB1 clock control register */
+#define XSLCR_USB1_CLK_CTRL_ADDR (XSLCR_BASEADDR + 0x00000134U)
+/**< SLCR USB1 reset control register */
+#define XSLCR_USB_RST_CTRL_ADDR (XSLCR_BASEADDR + 0x00000210U)
+/**< SLCR SMC reset control register */
+#define XSLCR_SMC_RST_CTRL_ADDR (XSLCR_BASEADDR + 0x00000234U)
+/**< SLCR Level shifter enable register */
+#define XSLCR_LVL_SHFTR_EN_ADDR (XSLCR_BASEADDR + 0x00000900U)
+/**< SLCR ARM pll control register */
+#define XSLCR_ARM_PLL_CTRL_ADDR (XSLCR_BASEADDR + 0x00000100U)
+/**< SLCR DDR pll control register */
+#define XSLCR_DDR_PLL_CTRL_ADDR (XSLCR_BASEADDR + 0x00000104U)
+/**< SLCR IO pll control register */
+#define XSLCR_IO_PLL_CTRL_ADDR (XSLCR_BASEADDR + 0x00000108U)
+/**< SLCR ARM pll configuration register */
+#define XSLCR_ARM_PLL_CFG_ADDR (XSLCR_BASEADDR + 0x00000110U)
+/**< SLCR DDR pll configuration register */
+#define XSLCR_DDR_PLL_CFG_ADDR (XSLCR_BASEADDR + 0x00000114U)
+/**< SLCR IO pll configuration register */
+#define XSLCR_IO_PLL_CFG_ADDR (XSLCR_BASEADDR + 0x00000118U)
+/**< SLCR ARM clock control register */
+#define XSLCR_ARM_CLK_CTRL_ADDR (XSLCR_BASEADDR + 0x00000120U)
+/**< SLCR DDR clock control register */
+#define XSLCR_DDR_CLK_CTRL_ADDR (XSLCR_BASEADDR + 0x00000124U)
+/**< SLCR MIO pin address register */
+#define XSLCR_MIO_PIN_00_ADDR (XSLCR_BASEADDR + 0x00000700U)
+/**< SLCR DMAC reset control address register */
+#define XSLCR_DMAC_RST_CTRL_ADDR (XSLCR_BASEADDR + 0x0000020CU)
+/**< SLCR USB reset control address register */
+/*#define XSLCR_USB_RST_CTRL_ADDR (XSLCR_BASEADDR + 0x00000210U)*/
+/**< SLCR GEM reset control address register */
+/*#define XSLCR_GEM_RST_CTRL_ADDR (XSLCR_BASEADDR + 0x00000214U)*/
+/**< SLCR SDIO reset control address register */
+#define XSLCR_SDIO_RST_CTRL_ADDR (XSLCR_BASEADDR + 0x00000218U)
+/**< SLCR SPI reset control address register */
+#define XSLCR_SPI_RST_CTRL_ADDR (XSLCR_BASEADDR + 0x0000021CU)
+/**< SLCR CAN reset control address register */
+#define XSLCR_CAN_RST_CTRL_ADDR (XSLCR_BASEADDR + 0x00000220U)
+/**< SLCR I2C reset control address register */
+#define XSLCR_I2C_RST_CTRL_ADDR (XSLCR_BASEADDR + 0x00000224U)
+/**< SLCR UART reset control address register */
+#define XSLCR_UART_RST_CTRL_ADDR (XSLCR_BASEADDR + 0x00000228U)
+/**< SLCR GPIO reset control address register */
+#define XSLCR_GPIO_RST_CTRL_ADDR (XSLCR_BASEADDR + 0x0000022CU)
+/**< SLCR LQSPI reset control address register */
+#define XSLCR_LQSPI_RST_CTRL_ADDR (XSLCR_BASEADDR + 0x00000230U)
+/**< SLCR SMC reset control address register */
+/*#define XSLCR_SMC_RST_CTRL_ADDR (XSLCR_BASEADDR + 0x00000234U)*/
+/**< SLCR OCM reset control address register */
+#define XSLCR_OCM_RST_CTRL_ADDR (XSLCR_BASEADDR + 0x00000238U)
+
+/**< SMC mem controller clear config register */
+#define XSMC_MEMC_CLR_CONFIG_OFFSET 0x0000000CU
+/**< SMC idlecount configuration register */
+#define XSMC_REFRESH_PERIOD_0_OFFSET 0x00000020U
+#define XSMC_REFRESH_PERIOD_1_OFFSET 0x00000024U
+/**< SMC ECC configuration register */
+#define XSMC_ECC_MEMCFG1_OFFSET 0x00000404U
+/**< SMC ECC command 1 register */
+#define XSMC_ECC_MEMCMD1_OFFSET 0x00000404U
+/**< SMC ECC command 2 register */
+#define XSMC_ECC_MEMCMD2_OFFSET 0x00000404U
+
+/**< SLCR unlock code */
+#define XSLCR_UNLOCK_CODE 0x0000DF0DU
+
+/**< SMC mem clear configuration mask */
+#define XSMC_MEMC_CLR_CONFIG_MASK 0x000005FU
+/**< SMC ECC memconfig 1 reset value */
+#define XSMC_ECC_MEMCFG1_RESET_VAL 0x0000043U
+/**< SMC ECC memcommand 1 reset value */
+#define XSMC_ECC_MEMCMD1_RESET_VAL 0x01300080U
+/**< SMC ECC memcommand 2 reset value */
+#define XSMC_ECC_MEMCMD2_RESET_VAL 0x01E00585U
+
+/**< DDR controller reset bit mask */
+#define XDDRPS_CTRL_RESET_MASK 0x00000001U
+/**< SLCR OCM configuration reset value*/
+#define XSLCR_OCM_CFG_RESETVAL 0x00000008U
+/**< SLCR OCM bank selection mask*/
+#define XSLCR_OCM_CFG_HIADDR_MASK 0x0000000FU
+/**< SLCR level shifter enable mask*/
+#define XSLCR_LVL_SHFTR_EN_MASK 0x0000000FU
+
+/**< SLCR PLL register reset values */
+#define XSLCR_ARM_PLL_CTRL_RESET_VAL 0x0001A008U
+#define XSLCR_DDR_PLL_CTRL_RESET_VAL 0x0001A008U
+#define XSLCR_IO_PLL_CTRL_RESET_VAL 0x0001A008U
+#define XSLCR_ARM_PLL_CFG_RESET_VAL 0x00177EA0U
+#define XSLCR_DDR_PLL_CFG_RESET_VAL 0x00177EA0U
+#define XSLCR_IO_PLL_CFG_RESET_VAL 0x00177EA0U
+#define XSLCR_ARM_CLK_CTRL_RESET_VAL 0x1F000400U
+#define XSLCR_DDR_CLK_CTRL_RESET_VAL 0x18400003U
+
+/**< SLCR MIO register default values */
+#define XSLCR_MIO_PIN_00_RESET_VAL 0x00001601U
+#define XSLCR_MIO_PIN_02_RESET_VAL 0x00000601U
+
+/**< SLCR Reset control registers default values */
+#define XSLCR_DMAC_RST_CTRL_VAL 0x00000001U
+#define XSLCR_GEM_RST_CTRL_VAL 0x000000F3U
+#define XSLCR_USB_RST_CTRL_VAL 0x00000003U
+#define XSLCR_I2C_RST_CTRL_VAL 0x00000003U
+#define XSLCR_SPI_RST_CTRL_VAL 0x0000000FU
+#define XSLCR_UART_RST_CTRL_VAL 0x0000000FU
+#define XSLCR_QSPI_RST_CTRL_VAL 0x00000003U
+#define XSLCR_GPIO_RST_CTRL_VAL 0x00000001U
+#define XSLCR_SMC_RST_CTRL_VAL 0x00000003U
+#define XSLCR_OCM_RST_CTRL_VAL 0x00000001U
+#define XSLCR_SDIO_RST_CTRL_VAL 0x00000033U
+#define XSLCR_CAN_RST_CTRL_VAL 0x00000003U
+/**************************** Type Definitions *******************************/
+
+/* the following data type is used to hold a null terminated version string
+ * consisting of the following format, "X.YYX"
+ */
+
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+
+/************************** Function Prototypes ******************************/
+/*
+ * Performs reset operation to the ddr interface
+ */
+void XDdr_ResetHw(void);
+/*
+ * Map the ocm region to post bootrom state
+ */
+void XOcm_Remap(void);
+/*
+ * Performs the smc interface reset
+ */
+void XSmc_ResetHw(u32 BaseAddress);
+/*
+ * updates the MIO registers with reset values
+ */
+void XSlcr_MioWriteResetValues(void);
+/*
+ * updates the PLL and clock registers with reset values
+ */
+void XSlcr_PllWriteResetValues(void);
+/*
+ * Disables the level shifters
+ */
+void XSlcr_DisableLevelShifters(void);
+/*
+ * provides softreset to the GPIO interface
+ */
+void XSlcr_GpioPsReset(void);
+/*
+ * provides softreset to the DMA interface
+ */
+void XSlcr_DmaPsReset(void);
+/*
+ * provides softreset to the SMC interface
+ */
+void XSlcr_SmcPsReset(void);
+/*
+ * provides softreset to the CAN interface
+ */
+void XSlcr_CanPsReset(void);
+/*
+ * provides softreset to the Uart interface
+ */
+void XSlcr_UartPsReset(void);
+/*
+ * provides softreset to the I2C interface
+ */
+void XSlcr_I2cPsReset(void);
+/*
+ * provides softreset to the SPI interface
+ */
+void XSlcr_SpiPsReset(void);
+/*
+ * provides softreset to the QSPI interface
+ */
+void XSlcr_QspiPsReset(void);
+/*
+ * provides softreset to the USB interface
+ */
+void XSlcr_UsbPsReset(void);
+/*
+ * provides softreset to the GEM interface
+ */
+void XSlcr_EmacPsReset(void);
+/*
+ * provides softreset to the OCM interface
+ */
+void XSlcr_OcmReset(void);
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* XIL_MISC_RESET_H */
diff --git a/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v7_1/src/xil_mmu.c b/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v7_1/src/xil_mmu.c
new file mode 100644
index 0000000..d237eac
--- /dev/null
+++ b/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v7_1/src/xil_mmu.c
@@ -0,0 +1,225 @@
+/******************************************************************************
+*
+* Copyright (C) 2012 - 2018 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+* THE SOFTWARE.
+*
+*
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+* @file xil_mmu.c
+*
+* This file provides APIs for enabling/disabling MMU and setting the memory
+* attributes for sections, in the MMU translation table.
+*
+* <pre>
+* MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ----- ---- -------- ---------------------------------------------------
+* 1.00a sdm 01/12/12 Initial version
+* 3.05a asa 03/10/12 Modified the Xil_EnableMMU to invalidate the caches
+* before enabling back.
+* 3.05a asa 04/15/12 Modified the Xil_SetTlbAttributes routine so that
+* translation table and branch predictor arrays are
+* invalidated, D-cache flushed before the attribute
+* change is applied. This is done so that the user
+* need not call Xil_DisableMMU before calling
+* Xil_SetTlbAttributes.
+* 3.10a srt 04/18/13 Implemented ARM Erratas. Please refer to file
+* 'xil_errata.h' for errata description
+* 3.11a asa 09/23/13 Modified Xil_SetTlbAttributes to flush the complete
+* D cache after the translation table update. Removed the
+* redundant TLB invalidation in the same API at the beginning.
+* 6.8 aru 09/06/18 Removed compilation warnings for ARMCC toolchain.
+* It fixes CR#1008309.
+* </pre>
+*
+* @note
+*
+* None.
+*
+******************************************************************************/
+
+/***************************** Include Files *********************************/
+
+#include "xil_cache.h"
+#include "xpseudo_asm.h"
+#include "xil_types.h"
+#include "xil_mmu.h"
+#include "xil_errata.h"
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/**************************** Type Definitions *******************************/
+
+/************************** Constant Definitions *****************************/
+#define ARM_AR_MEM_TTB_SECT_SIZE 1024*1024
+#define ARM_AR_MEM_TTB_SECT_SIZE_MASK (~(ARM_AR_MEM_TTB_SECT_SIZE-1UL))
+/************************** Variable Definitions *****************************/
+
+extern u32 MMUTable;
+
+/************************** Function Prototypes ******************************/
+
+/*****************************************************************************/
+/**
+* @brief This function sets the memory attributes for a section covering 1MB
+* of memory in the translation table.
+*
+* @param Addr: 32-bit address for which memory attributes need to be set.
+* @param attrib: Attribute for the given memory region. xil_mmu.h contains
+* definitions of commonly used memory attributes which can be
+* utilized for this function.
+*
+*
+* @return None.
+*
+* @note The MMU or D-cache does not need to be disabled before changing a
+* translation table entry.
+*
+******************************************************************************/
+void Xil_SetTlbAttributes(INTPTR Addr, u32 attrib)
+{
+ u32 *ptr;
+ u32 section;
+
+ section = Addr / 0x100000U;
+ ptr = &MMUTable;
+ ptr += section;
+ if(ptr != NULL) {
+ *ptr = (Addr & 0xFFF00000U) | attrib;
+ }
+
+ Xil_DCacheFlush();
+
+ mtcp(XREG_CP15_INVAL_UTLB_UNLOCKED, 0U);
+ /* Invalidate all branch predictors */
+ mtcp(XREG_CP15_INVAL_BRANCH_ARRAY, 0U);
+
+ dsb(); /* ensure completion of the BP and TLB invalidation */
+ isb(); /* synchronize context on this processor */
+}
+
+/*****************************************************************************/
+/**
+* @brief Enable MMU for cortex A9 processor. This function invalidates the
+* instruction and data caches, and then enables MMU.
+*
+* @param None.
+* @return None.
+*
+******************************************************************************/
+void Xil_EnableMMU(void)
+{
+ u32 Reg;
+ Xil_DCacheInvalidate();
+ Xil_ICacheInvalidate();
+
+#ifdef __GNUC__
+ Reg = mfcp(XREG_CP15_SYS_CONTROL);
+#elif defined (__ICCARM__)
+ mfcp(XREG_CP15_SYS_CONTROL, Reg);
+#else
+ { volatile register u32 Cp15Reg __asm(XREG_CP15_SYS_CONTROL);
+ Reg = Cp15Reg; }
+#endif
+ Reg |= (u32)0x05U;
+ mtcp(XREG_CP15_SYS_CONTROL, Reg);
+
+ dsb();
+ isb();
+}
+
+/*****************************************************************************/
+/**
+* @brief Disable MMU for Cortex A9 processors. This function invalidates
+* the TLBs, Branch Predictor Array and flushed the D Caches before
+* disabling the MMU.
+*
+* @param None.
+*
+* @return None.
+*
+* @note When the MMU is disabled, all the memory accesses are treated as
+* strongly ordered.
+******************************************************************************/
+void Xil_DisableMMU(void)
+{
+ u32 Reg;
+
+ mtcp(XREG_CP15_INVAL_UTLB_UNLOCKED, 0U);
+ mtcp(XREG_CP15_INVAL_BRANCH_ARRAY, 0U);
+ Xil_DCacheFlush();
+
+#ifdef __GNUC__
+ Reg = mfcp(XREG_CP15_SYS_CONTROL);
+#elif defined (__ICCARM__)
+ mfcp(XREG_CP15_SYS_CONTROL, Reg);
+#else
+ { volatile register u32 Cp15Reg __asm(XREG_CP15_SYS_CONTROL);
+ Reg = Cp15Reg; }
+#endif
+ Reg &= (u32)(~0x05U);
+#ifdef CONFIG_ARM_ERRATA_794073
+ /* Disable Branch Prediction */
+ Reg &= (u32)(~0x800U);
+#endif
+ mtcp(XREG_CP15_SYS_CONTROL, Reg);
+}
+
+/*****************************************************************************/
+/**
+* @brief Memory mapping for Cortex A9 processor.
+*
+* @param PhysAddr is physical address.
+* @param size is size of region.
+* @param flags is flags used to set translation table.
+*
+* @return Pointer to virtual address.
+*
+* @note: Previously this was implemented in libmetal. Move to embeddedsw as this
+* functionality is specific to A9 processor.
+*
+******************************************************************************/
+void* Xil_MemMap(UINTPTR PhysAddr, size_t size, u32 flags)
+{
+ u32 Sectionoffset;
+ u32 Ttbaddr;
+
+ if (!flags)
+ return (void*)PhysAddr;
+
+ /* Ensure alignment on a section boundary */
+ PhysAddr &= ARM_AR_MEM_TTB_SECT_SIZE_MASK;
+
+ /* Loop through entire region of memory (one MMU section at a time).
+ Each section requires a TTB entry. */
+ for (Sectionoffset = 0; Sectionoffset < size;
+ Sectionoffset += ARM_AR_MEM_TTB_SECT_SIZE) {
+ /* Calculate translation table entry for this memory section */
+ Ttbaddr = (PhysAddr + Sectionoffset);
+
+ /* Write translation table entry value to entry address */
+ Xil_SetTlbAttributes(Ttbaddr, flags);
+ }
+ return (void*)PhysAddr;
+}
diff --git a/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v7_1/src/xil_mmu.h b/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v7_1/src/xil_mmu.h
new file mode 100644
index 0000000..749bcdf
--- /dev/null
+++ b/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v7_1/src/xil_mmu.h
@@ -0,0 +1,104 @@
+/******************************************************************************
+*
+* Copyright (C) 2012 - 2018 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+* THE SOFTWARE.
+*
+*
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+* @file xil_mmu.h
+*
+* @addtogroup a9_mmu_apis Cortex A9 Processor MMU Functions
+*
+* MMU functions equip users to enable MMU, disable MMU and modify default
+* memory attributes of MMU table as per the need.
+*
+* @{
+*
+* <pre>
+* MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ----- ---- -------- ---------------------------------------------------
+* 1.00a sdm 01/12/12 Initial version
+* 4.2 pkp 07/21/14 Included xil_types.h file which contains definition for
+* u32 which resolves issue of CR#805869
+* 5.4 pkp 23/11/15 Added attribute definitions for Xil_SetTlbAttributes API
+* 6.8 aru 09/06/18 Removed compilation warnings for ARMCC toolchain.
+* </pre>
+*
+*
+******************************************************************************/
+
+#ifndef XIL_MMU_H
+#define XIL_MMU_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif /* __cplusplus */
+
+/***************************** Include Files *********************************/
+
+#include "xil_types.h"
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/**************************** Type Definitions *******************************/
+
+/************************** Constant Definitions *****************************/
+
+/* Memory type */
+#define NORM_NONCACHE 0x11DE2 /* Normal Non-cacheable */
+#define STRONG_ORDERED 0xC02 /* Strongly ordered */
+#define DEVICE_MEMORY 0xC06 /* Device memory */
+#define RESERVED 0x0 /* reserved memory */
+
+/* Normal write-through cacheable shareable */
+#define NORM_WT_CACHE 0x16DEA
+
+/* Normal write back cacheable shareable */
+#define NORM_WB_CACHE 0x15DE6
+
+/* shareability attribute */
+#define SHAREABLE (0x1 << 16)
+#define NON_SHAREABLE (~(0x1 << 16))
+
+/* Execution type */
+#define EXECUTE_NEVER ((0x1 << 4) | (0x1 << 0))
+
+/************************** Variable Definitions *****************************/
+
+/************************** Function Prototypes ******************************/
+
+void Xil_SetTlbAttributes(INTPTR Addr, u32 attrib);
+void Xil_EnableMMU(void);
+void Xil_DisableMMU(void);
+void* Xil_MemMap(UINTPTR PhysAddr, size_t size, u32 flags);
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+
+#endif /* XIL_MMU_H */
+/**
+* @} End of "addtogroup a9_mmu_apis".
+*/
diff --git a/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v7_1/src/xil_printf.c b/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v7_1/src/xil_printf.c
new file mode 100644
index 0000000..c265ccf
--- /dev/null
+++ b/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v7_1/src/xil_printf.c
@@ -0,0 +1,442 @@
+/*---------------------------------------------------*/
+/* Modified from : */
+/* Public Domain version of printf */
+/* Rud Merriam, Compsult, Inc. Houston, Tx. */
+/* For Embedded Systems Programming, 1991 */
+/* */
+/*---------------------------------------------------*/
+#include "xil_printf.h"
+#include "xil_types.h"
+#include "xil_assert.h"
+#include <ctype.h>
+#include <string.h>
+#include <stdarg.h>
+
+static void padding( const s32 l_flag,const struct params_s *par);
+static void outs(const charptr lp, struct params_s *par);
+static s32 getnum( charptr* linep);
+
+typedef struct params_s {
+ s32 len;
+ s32 num1;
+ s32 num2;
+ char8 pad_character;
+ s32 do_padding;
+ s32 left_flag;
+ s32 unsigned_flag;
+} params_t;
+
+
+/*---------------------------------------------------*/
+/* The purpose of this routine is to output data the */
+/* same as the standard printf function without the */
+/* overhead most run-time libraries involve. Usually */
+/* the printf brings in many kilobytes of code and */
+/* that is unacceptable in most embedded systems. */
+/*---------------------------------------------------*/
+
+
+/*---------------------------------------------------*/
+/* */
+/* This routine puts pad characters into the output */
+/* buffer. */
+/* */
+static void padding( const s32 l_flag, const struct params_s *par)
+{
+ s32 i;
+
+ if ((par->do_padding != 0) && (l_flag != 0) && (par->len < par->num1)) {
+ i=(par->len);
+ for (; i<(par->num1); i++) {
+#ifdef STDOUT_BASEADDRESS
+ outbyte( par->pad_character);
+#endif
+ }
+ }
+}
+
+/*---------------------------------------------------*/
+/* */
+/* This routine moves a string to the output buffer */
+/* as directed by the padding and positioning flags. */
+/* */
+static void outs(const charptr lp, struct params_s *par)
+{
+ charptr LocalPtr;
+ LocalPtr = lp;
+ /* pad on left if needed */
+ if(LocalPtr != NULL) {
+ par->len = (s32)strlen( LocalPtr);
+ }
+ padding( !(par->left_flag), par);
+
+ /* Move string to the buffer */
+ while (((*LocalPtr) != (char8)0) && ((par->num2) != 0)) {
+ (par->num2)--;
+#ifdef STDOUT_BASEADDRESS
+ outbyte(*LocalPtr);
+#endif
+ LocalPtr += 1;
+}
+
+ /* Pad on right if needed */
+ /* CR 439175 - elided next stmt. Seemed bogus. */
+ /* par->len = strlen( lp) */
+ padding( par->left_flag, par);
+}
+
+/*---------------------------------------------------*/
+/* */
+/* This routine moves a number to the output buffer */
+/* as directed by the padding and positioning flags. */
+/* */
+
+static void outnum( const s32 n, const s32 base, struct params_s *par)
+{
+ s32 negative;
+ s32 i;
+ char8 outbuf[32];
+ const char8 digits[] = "0123456789ABCDEF";
+ u32 num;
+ for(i = 0; i<32; i++) {
+ outbuf[i] = '0';
+ }
+
+ /* Check if number is negative */
+ if ((par->unsigned_flag == 0) && (base == 10) && (n < 0L)) {
+ negative = 1;
+ num =(-(n));
+ }
+ else{
+ num = n;
+ negative = 0;
+ }
+
+ /* Build number (backwards) in outbuf */
+ i = 0;
+ do {
+ outbuf[i] = digits[(num % base)];
+ i++;
+ num /= base;
+ } while (num > 0);
+
+ if (negative != 0) {
+ outbuf[i] = '-';
+ i++;
+ }
+
+ outbuf[i] = '\0';
+ i--;
+
+ /* Move the converted number to the buffer and */
+ /* add in the padding where needed. */
+ par->len = (s32)strlen(outbuf);
+ padding( !(par->left_flag), par);
+ while (&outbuf[i] >= outbuf) {
+#ifdef STDOUT_BASEADDRESS
+ outbyte( outbuf[i] );
+#endif
+ i--;
+}
+ padding( par->left_flag, par);
+}
+/*---------------------------------------------------*/
+/* */
+/* This routine moves a 64-bit number to the output */
+/* buffer as directed by the padding and positioning */
+/* flags. */
+/* */
+#if defined (__aarch64__) || defined (__arch64__)
+static void outnum1( const s64 n, const s32 base, params_t *par)
+{
+ s32 negative;
+ s32 i;
+ char8 outbuf[64];
+ const char8 digits[] = "0123456789ABCDEF";
+ u64 num;
+ for(i = 0; i<64; i++) {
+ outbuf[i] = '0';
+ }
+
+ /* Check if number is negative */
+ if ((par->unsigned_flag == 0) && (base == 10) && (n < 0L)) {
+ negative = 1;
+ num =(-(n));
+ }
+ else{
+ num = (n);
+ negative = 0;
+ }
+
+ /* Build number (backwards) in outbuf */
+ i = 0;
+ do {
+ outbuf[i] = digits[(num % base)];
+ i++;
+ num /= base;
+ } while (num > 0);
+
+ if (negative != 0) {
+ outbuf[i] = '-';
+ i++;
+ }
+
+ outbuf[i] = '\0';
+ i--;
+
+ /* Move the converted number to the buffer and */
+ /* add in the padding where needed. */
+ par->len = (s32)strlen(outbuf);
+ padding( !(par->left_flag), par);
+ while (&outbuf[i] >= outbuf) {
+ outbyte( outbuf[i] );
+ i--;
+}
+ padding( par->left_flag, par);
+}
+#endif
+/*---------------------------------------------------*/
+/* */
+/* This routine gets a number from the format */
+/* string. */
+/* */
+static s32 getnum( charptr* linep)
+{
+ s32 n;
+ s32 ResultIsDigit = 0;
+ charptr cptr;
+ n = 0;
+ cptr = *linep;
+ if(cptr != NULL){
+ ResultIsDigit = isdigit(((s32)*cptr));
+ }
+ while (ResultIsDigit != 0) {
+ if(cptr != NULL){
+ n = ((n*10) + (((s32)*cptr) - (s32)'0'));
+ cptr += 1;
+ if(cptr != NULL){
+ ResultIsDigit = isdigit(((s32)*cptr));
+ }
+ }
+ ResultIsDigit = isdigit(((s32)*cptr));
+ }
+ *linep = ((charptr )(cptr));
+ return(n);
+}
+
+/*---------------------------------------------------*/
+/* */
+/* This routine operates just like a printf/sprintf */
+/* routine. It outputs a set of data under the */
+/* control of a formatting string. Not all of the */
+/* standard C format control are supported. The ones */
+/* provided are primarily those needed for embedded */
+/* systems work. Primarily the floating point */
+/* routines are omitted. Other formats could be */
+/* added easily by following the examples shown for */
+/* the supported formats. */
+/* */
+
+/* void esp_printf( const func_ptr f_ptr,
+ const charptr ctrl1, ...) */
+#if defined (__aarch64__) && HYP_GUEST && EL1_NONSECURE && XEN_USE_PV_CONSOLE
+void xil_printf( const char8 *ctrl1, ...){
+ XPVXenConsole_Printf(ctrl1);
+}
+#else
+void xil_printf( const char8 *ctrl1, ...)
+{
+ s32 Check;
+#if defined (__aarch64__) || defined (__arch64__)
+ s32 long_flag;
+#endif
+ s32 dot_flag;
+
+ params_t par;
+
+ char8 ch;
+ va_list argp;
+ char8 *ctrl = (char8 *)ctrl1;
+
+ va_start( argp, ctrl1);
+
+ while ((ctrl != NULL) && (*ctrl != (char8)0)) {
+
+ /* move format string chars to buffer until a */
+ /* format control is found. */
+ if (*ctrl != '%') {
+#ifdef STDOUT_BASEADDRESS
+ outbyte(*ctrl);
+#endif
+ ctrl += 1;
+ continue;
+ }
+
+ /* initialize all the flags for this format. */
+ dot_flag = 0;
+#if defined (__aarch64__) || defined (__arch64__)
+ long_flag = 0;
+#endif
+ par.unsigned_flag = 0;
+ par.left_flag = 0;
+ par.do_padding = 0;
+ par.pad_character = ' ';
+ par.num2=32767;
+ par.num1=0;
+ par.len=0;
+
+ try_next:
+ if(ctrl != NULL) {
+ ctrl += 1;
+ }
+ if(ctrl != NULL) {
+ ch = *ctrl;
+ } else {
+ break;
+ }
+
+ if (isdigit((s32)ch) != 0) {
+ if (dot_flag != 0) {
+ par.num2 = getnum(&ctrl);
+ }
+ else {
+ if (ch == '0') {
+ par.pad_character = '0';
+ }
+ if(ctrl != NULL) {
+ par.num1 = getnum(&ctrl);
+ }
+ par.do_padding = 1;
+ }
+ if(ctrl != NULL) {
+ ctrl -= 1;
+ }
+ goto try_next;
+ }
+
+ switch (tolower((s32)ch)) {
+ case '%':
+#ifdef STDOUT_BASEADDRESS
+ outbyte( '%');
+#endif
+ Check = 1;
+ break;
+
+ case '-':
+ par.left_flag = 1;
+ Check = 0;
+ break;
+
+ case '.':
+ dot_flag = 1;
+ Check = 0;
+ break;
+
+ case 'l':
+ #if defined (__aarch64__) || defined (__arch64__)
+ long_flag = 1;
+ #endif
+ Check = 0;
+ break;
+
+ case 'u':
+ par.unsigned_flag = 1;
+ /* fall through */
+ case 'i':
+ case 'd':
+ #if defined (__aarch64__) || defined (__arch64__)
+ if (long_flag != 0){
+ outnum1((s64)va_arg(argp, s64), 10L, &par);
+ }
+ else {
+ outnum( va_arg(argp, s32), 10L, &par);
+ }
+ #else
+ outnum( va_arg(argp, s32), 10L, &par);
+ #endif
+ Check = 1;
+ break;
+ case 'p':
+ #if defined (__aarch64__) || defined (__arch64__)
+ par.unsigned_flag = 1;
+ outnum1((s64)va_arg(argp, s64), 16L, &par);
+ Check = 1;
+ break;
+ #endif
+ case 'X':
+ case 'x':
+ par.unsigned_flag = 1;
+ #if defined (__aarch64__) || defined (__arch64__)
+ if (long_flag != 0) {
+ outnum1((s64)va_arg(argp, s64), 16L, &par);
+ }
+ else {
+ outnum((s32)va_arg(argp, s32), 16L, &par);
+ }
+ #else
+ outnum((s32)va_arg(argp, s32), 16L, &par);
+ #endif
+ Check = 1;
+ break;
+
+ case 's':
+ outs( va_arg( argp, char *), &par);
+ Check = 1;
+ break;
+
+ case 'c':
+#ifdef STDOUT_BASEADDRESS
+ outbyte( va_arg( argp, s32));
+#endif
+ Check = 1;
+ break;
+
+ case '\\':
+ switch (*ctrl) {
+ case 'a':
+#ifdef STDOUT_BASEADDRESS
+ outbyte( ((char8)0x07));
+#endif
+ break;
+ case 'h':
+#ifdef STDOUT_BASEADDRESS
+ outbyte( ((char8)0x08));
+#endif
+ break;
+ case 'r':
+#ifdef STDOUT_BASEADDRESS
+ outbyte( ((char8)0x0D));
+#endif
+ break;
+ case 'n':
+#ifdef STDOUT_BASEADDRESS
+ outbyte( ((char8)0x0D));
+ outbyte( ((char8)0x0A));
+#endif
+ break;
+ default:
+#ifdef STDOUT_BASEADDRESS
+ outbyte( *ctrl);
+#endif
+ break;
+ }
+ ctrl += 1;
+ Check = 0;
+ break;
+
+ default:
+ Check = 1;
+ break;
+ }
+ if(Check == 1) {
+ if(ctrl != NULL) {
+ ctrl += 1;
+ }
+ continue;
+ }
+ goto try_next;
+ }
+ va_end( argp);
+}
+#endif
+/*---------------------------------------------------*/
diff --git a/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v7_1/src/xil_printf.h b/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v7_1/src/xil_printf.h
new file mode 100644
index 0000000..a0177fc
--- /dev/null
+++ b/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v7_1/src/xil_printf.h
@@ -0,0 +1,48 @@
+ #ifndef XIL_PRINTF_H
+ #define XIL_PRINTF_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <ctype.h>
+#include <string.h>
+#include <stdarg.h>
+#include "xil_types.h"
+#include "xparameters.h"
+#include "bspconfig.h"
+#if defined (__aarch64__) && HYP_GUEST && EL1_NONSECURE && XEN_USE_PV_CONSOLE
+#include "xen_console.h"
+#endif
+
+/*----------------------------------------------------*/
+/* Use the following parameter passing structure to */
+/* make xil_printf re-entrant. */
+/*----------------------------------------------------*/
+
+struct params_s;
+
+
+/*---------------------------------------------------*/
+/* The purpose of this routine is to output data the */
+/* same as the standard printf function without the */
+/* overhead most run-time libraries involve. Usually */
+/* the printf brings in many kilobytes of code and */
+/* that is unacceptable in most embedded systems. */
+/*---------------------------------------------------*/
+
+typedef char8* charptr;
+typedef s32 (*func_ptr)(int c);
+
+/* */
+
+void xil_printf( const char8 *ctrl1, ...);
+void print( const char8 *ptr);
+extern void outbyte (char8 c);
+extern char8 inbyte(void);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* end of protection macro */
diff --git a/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v7_1/src/xil_sleepcommon.c b/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v7_1/src/xil_sleepcommon.c
new file mode 100644
index 0000000..2a07825
--- /dev/null
+++ b/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v7_1/src/xil_sleepcommon.c
@@ -0,0 +1,100 @@
+/******************************************************************************
+*
+* Copyright (C) 2017 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+* THE SOFTWARE.
+*
+*
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+*@file xil_sleepcommon.c
+*
+* This file contains the sleep API's
+*
+* <pre>
+* MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ----- -------- -------- -----------------------------------------------
+* 6.6 srm 11/02/17 First release
+* </pre>
+******************************************************************************/
+
+
+/***************************** Include Files *********************************/
+#include "xil_io.h"
+#include "sleep.h"
+
+/**************************** Constant Definitions *************************/
+
+
+/*****************************************************************************/
+/**
+*
+* This API gives delay in sec
+*
+* @param seconds - delay time in seconds
+*
+* @return none
+*
+* @note none
+*
+*****************************************************************************/
+ void sleep(unsigned int seconds)
+ {
+#if defined (ARMR5)
+ sleep_R5(seconds);
+#elif defined (__aarch64__) || defined (ARMA53_32)
+ sleep_A53(seconds);
+#elif defined (__MICROBLAZE__)
+ sleep_MB(seconds);
+#else
+ sleep_A9(seconds);
+#endif
+
+ }
+
+/****************************************************************************/
+/**
+*
+* This API gives delay in usec
+*
+* @param useconds - delay time in useconds
+*
+* @return none
+*
+* @note none
+*
+*****************************************************************************/
+ void usleep(unsigned long useconds)
+ {
+#if defined (ARMR5)
+ usleep_R5(useconds);
+#elif defined (__aarch64__) || defined (ARMA53_32)
+ usleep_A53(useconds);
+#elif defined (__MICROBLAZE__)
+ usleep_MB(useconds);
+#else
+ usleep_A9(useconds);
+#endif
+
+ }
diff --git a/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v7_1/src/xil_sleeptimer.c b/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v7_1/src/xil_sleeptimer.c
new file mode 100644
index 0000000..7fa6b35
--- /dev/null
+++ b/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v7_1/src/xil_sleeptimer.c
@@ -0,0 +1,163 @@
+/******************************************************************************
+*
+* Copyright (C) 2017 - 2019 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+* THE SOFTWARE.
+*
+*
+*
+******************************************************************************/
+
+/*****************************************************************************/
+/**
+*
+* @file xil_sleeptimer.c
+*
+* This file provides the common helper routines for the sleep API's
+*
+* <pre>
+* MODIFICATION HISTORY :
+*
+* Ver Who Date Changes
+* ----- ---- -------- -------------------------------------------------------
+* 6.6 srm 10/18/17 First Release.
+* 6.6 srm 04/20/18 Fixed compilation warning in Xil_SleepTTCCommon API
+* 7.0 mus 03/27/19 Updated XTime_StartTTCTimer to skip IOU slcr address
+* space access, if processor is nonsecure and IOU slcr
+* address space is secure. CR#1015725.
+*
+* </pre>
+*****************************************************************************/
+
+/**************************** Include Files ********************************/
+
+#include "xil_io.h"
+#include "xil_sleeptimer.h"
+#include "xtime_l.h"
+
+/**************************** Constant Definitions *************************/
+
+
+/* Function definitions are applicable only when TTC3 is present*/
+#if defined (SLEEP_TIMER_BASEADDR)
+/****************************************************************************/
+/**
+*
+* This is a helper function used by sleep/usleep APIs to
+* have delay in sec/usec
+*
+* @param delay - delay time in seconds/micro seconds
+*
+* @param frequency - Number of counts per second/micro second
+*
+* @return none
+*
+* @note none
+*
+*****************************************************************************/
+void Xil_SleepTTCCommon(u32 delay, u64 frequency)
+{
+ u64 tEnd = 0U;
+ u64 tCur = 0U;
+ XCntrVal TimeHighVal = 0U;
+ XCntrVal TimeLowVal1 = 0U;
+ XCntrVal TimeLowVal2 = 0U;
+
+ TimeLowVal1 = XSleep_ReadCounterVal(SLEEP_TIMER_BASEADDR +
+ XSLEEP_TIMER_TTC_COUNT_VALUE_OFFSET);
+ tEnd = (u64)TimeLowVal1 + ((u64)(delay) * frequency);
+ do
+ {
+ TimeLowVal2 = XSleep_ReadCounterVal(SLEEP_TIMER_BASEADDR +
+ XSLEEP_TIMER_TTC_COUNT_VALUE_OFFSET);
+ if (TimeLowVal2 < TimeLowVal1) {
+ TimeHighVal++;
+ }
+ TimeLowVal1 = TimeLowVal2;
+ tCur = (((u64) TimeHighVal) << XSLEEP_TIMER_REG_SHIFT) |
+ (u64)TimeLowVal2;
+ }while (tCur < tEnd);
+}
+
+
+/*****************************************************************************/
+/**
+*
+* This API starts the Triple Timer Counter
+*
+* @param none
+*
+* @return none
+*
+* @note none
+*
+*****************************************************************************/
+void XTime_StartTTCTimer()
+{
+ u32 TimerPrescalar;
+ u32 TimerCntrl;
+
+#if (defined (__aarch64__) && EL3==1) || (defined (ARMR5) && (PROCESSOR_ACCESS_VALUE & IOU_SLCR_TZ_MASK)) || defined (ARMA53_32)
+ u32 LpdRst;
+
+#if defined (versal)
+ u32 RstAddr = CRL_TTC_RST;
+ u32 RstMask = CRL_TTC_BASE_RST_MASK << XSLEEP_TTC_INSTANCE;
+#else
+ u32 RstAddr = RST_LPD_IOU2;
+ u32 RstMask = RST_LPD_IOU2_TTC_BASE_RESET_MASK << XSLEEP_TTC_INSTANCE;
+#endif
+ /* check if the timer is reset */
+ LpdRst = XSleep_ReadCounterVal(RstAddr);
+ if ((LpdRst & RstMask) != 0 ) {
+ LpdRst = LpdRst & (~RstMask);
+ Xil_Out32(RstAddr, LpdRst);
+ } else {
+#endif
+ TimerCntrl = XSleep_ReadCounterVal(SLEEP_TIMER_BASEADDR +
+ XSLEEP_TIMER_TTC_CNT_CNTRL_OFFSET);
+ /* check if Timer is disabled */
+ if ((TimerCntrl & XSLEEP_TIMER_TTC_CNT_CNTRL_DIS_MASK) == 0) {
+ TimerPrescalar = XSleep_ReadCounterVal(SLEEP_TIMER_BASEADDR +
+ XSLEEP_TIMER_TTC_CLK_CNTRL_OFFSET);
+ /* check if Timer is configured with proper functionalty for sleep */
+ if ((TimerPrescalar & XSLEEP_TIMER_TTC_CLK_CNTRL_PS_EN_MASK) == 0)
+ return;
+ }
+#if (defined (__aarch64__) && EL3==1) || (defined (ARMR5) && (PROCESSOR_ACCESS_VALUE & IOU_SLCR_TZ_MASK)) || defined (ARMA53_32)
+ }
+#endif
+ /* Disable the timer to configure */
+ TimerCntrl = XSleep_ReadCounterVal(SLEEP_TIMER_BASEADDR +
+ XSLEEP_TIMER_TTC_CNT_CNTRL_OFFSET);
+ TimerCntrl = TimerCntrl | XSLEEP_TIMER_TTC_CNT_CNTRL_DIS_MASK;
+ Xil_Out32(SLEEP_TIMER_BASEADDR + XSLEEP_TIMER_TTC_CNT_CNTRL_OFFSET,
+ TimerCntrl);
+ /* Disable the prescalar */
+ TimerPrescalar = XSleep_ReadCounterVal(SLEEP_TIMER_BASEADDR +
+ XSLEEP_TIMER_TTC_CLK_CNTRL_OFFSET);
+ TimerPrescalar = TimerPrescalar & (~XSLEEP_TIMER_TTC_CLK_CNTRL_PS_EN_MASK);
+ Xil_Out32(SLEEP_TIMER_BASEADDR + XSLEEP_TIMER_TTC_CLK_CNTRL_OFFSET,
+ TimerPrescalar);
+ /* Enable the Timer */
+ TimerCntrl = TimerCntrl & (~XSLEEP_TIMER_TTC_CNT_CNTRL_DIS_MASK);
+ Xil_Out32(SLEEP_TIMER_BASEADDR + XSLEEP_TIMER_TTC_CNT_CNTRL_OFFSET,
+ TimerCntrl);
+}
+#endif
diff --git a/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v7_1/src/xil_sleeptimer.h b/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v7_1/src/xil_sleeptimer.h
new file mode 100644
index 0000000..4c28d6d
--- /dev/null
+++ b/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v7_1/src/xil_sleeptimer.h
@@ -0,0 +1,126 @@
+/******************************************************************************
+*
+* Copyright (C) 2017 - 2019 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+* THE SOFTWARE.
+*
+*
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xil_sleeptimer.h
+*
+* This header file contains ARM Cortex A53,A9,R5 specific sleep related APIs.
+* For sleep related functions that can be used across all Xilinx supported
+* processors, please use xil_sleeptimer.h.
+*
+*
+* <pre>
+* MODIFICATION HISTORY :
+*
+* Ver Who Date Changes
+* ----- ---- -------- -------------------------------------------------------
+* 6.6 srm 10/18/17 First Release.
+* 7.0 mus 01/07/19 Add cpp extern macro
+*
+* </pre>
+*****************************************************************************/
+
+#ifndef XIL_SLEEPTIMER_H /* prevent circular inclusions */
+#define XIL_SLEEPTIMER_H /* by using protection macros */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**************************** Include Files ********************************/
+
+#include "xil_io.h"
+#include "xparameters.h"
+#include "bspconfig.h"
+
+/************************** Constant Definitions *****************************/
+
+#if defined (ARMR5) || (__aarch64__) || (ARMA53_32)
+#define XSLEEP_TIMER_REG_SHIFT 32U
+#define XSleep_ReadCounterVal Xil_In32
+#define XCntrVal u32
+#else
+#define XSLEEP_TIMER_REG_SHIFT 16U
+#define XSleep_ReadCounterVal Xil_In16
+#define XCntrVal u16
+#endif
+
+#if defined(ARMR5) || (defined (__aarch64__) && EL3==1) || defined (ARMA53_32)
+#if defined (versal)
+#define CRL_TTC_RST 0xFF5E0344U
+#define CRL_TTC_BASE_RST_MASK 0x1U
+#else
+#define RST_LPD_IOU2 0xFF5E0238U
+#define RST_LPD_IOU2_TTC_BASE_RESET_MASK 0x00000800U
+#endif
+#endif
+
+#if defined (SLEEP_TIMER_BASEADDR)
+/** @name Register Map
+*
+* Register offsets from the base address of the TTC device
+*
+* @{
+*/
+ #define XSLEEP_TIMER_TTC_CLK_CNTRL_OFFSET 0x00000000U
+ /**< Clock Control Register */
+ #define XSLEEP_TIMER_TTC_CNT_CNTRL_OFFSET 0x0000000CU
+ /**< Counter Control Register*/
+ #define XSLEEP_TIMER_TTC_COUNT_VALUE_OFFSET 0x00000018U
+ /**< Current Counter Value */
+/* @} */
+/** @name Clock Control Register
+* Clock Control Register definitions of TTC
+* @{
+*/
+ #define XSLEEP_TIMER_TTC_CLK_CNTRL_PS_EN_MASK 0x00000001U
+ /**< Prescale enable */
+/* @} */
+/** @name Counter Control Register
+* Counter Control Register definitions of TTC
+* @{
+*/
+#define XSLEEP_TIMER_TTC_CNT_CNTRL_DIS_MASK 0x00000001U
+ /**< Disable the counter */
+#define XSLEEP_TIMER_TTC_CNT_CNTRL_RST_MASK 0x00000010U
+ /**< Reset counter */
+/* @} */
+
+/**************************** Type Definitions *******************************/
+
+/************************** Function Prototypes ******************************/
+
+void Xil_SleepTTCCommon(u32 delay, u64 frequency);
+void XTime_StartTTCTimer();
+
+#endif
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* XIL_SLEEPTIMER_H */
diff --git a/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v7_1/src/xil_testcache.c b/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v7_1/src/xil_testcache.c
new file mode 100644
index 0000000..eea69ef
--- /dev/null
+++ b/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v7_1/src/xil_testcache.c
@@ -0,0 +1,365 @@
+/******************************************************************************
+*
+* Copyright (C) 2009 - 2015 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+* THE SOFTWARE.
+*
+*
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xil_testcache.c
+*
+* Contains utility functions to test cache.
+*
+* <pre>
+* MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ----- ---- -------- -------------------------------------------------------
+* 1.00a hbm 07/28/09 Initial release
+* 4.1 asa 05/09/14 Ensured that the address uses for cache test is aligned
+* cache line.
+* </pre>
+*
+* @note
+* This file contain functions that all operate on HAL.
+*
+******************************************************************************/
+#ifdef __ARM__
+#include "xil_cache.h"
+#include "xil_testcache.h"
+#include "xil_types.h"
+#include "xpseudo_asm.h"
+#ifdef __aarch64__
+#include "xreg_cortexa53.h"
+#else
+#include "xreg_cortexr5.h"
+#endif
+
+#include "xil_types.h"
+
+extern void xil_printf(const char8 *ctrl1, ...);
+
+#define DATA_LENGTH 128
+
+#ifdef __aarch64__
+static INTPTR Data[DATA_LENGTH] __attribute__ ((aligned(64)));
+#else
+static INTPTR Data[DATA_LENGTH] __attribute__ ((aligned(32)));
+#endif
+
+
+/*****************************************************************************/
+/**
+*
+* @brief Perform DCache range related API test such as Xil_DCacheFlushRange
+* and Xil_DCacheInvalidateRange. This test function writes a constant
+* value to the Data array, flushes the range, writes a new value, then
+* invalidates the corresponding range.
+* @param None
+*
+* @return
+* - -1 is returned for a failure
+* - 0 is returned for a pass
+*
+*****************************************************************************/
+s32 Xil_TestDCacheRange(void)
+{
+ s32 Index;
+ s32 Status = 0;
+ u32 CtrlReg;
+ INTPTR Value;
+
+ xil_printf("-- Cache Range Test --\n\r");
+
+ for (Index = 0; Index < DATA_LENGTH; Index++)
+ Data[Index] = 0xA0A00505;
+
+ xil_printf(" initialize Data done:\r\n");
+
+ Xil_DCacheFlushRange((INTPTR)Data, DATA_LENGTH * sizeof(INTPTR));
+
+ xil_printf(" flush range done\r\n");
+
+ dsb();
+ #ifdef __aarch64__
+ CtrlReg = mfcp(SCTLR_EL3);
+ CtrlReg &= ~(XREG_CONTROL_DCACHE_BIT);
+ mtcp(SCTLR_EL3,CtrlReg);
+ #else
+ CtrlReg = mfcp(XREG_CP15_SYS_CONTROL);
+ CtrlReg &= ~(XREG_CP15_CONTROL_C_BIT);
+ mtcp(XREG_CP15_SYS_CONTROL, CtrlReg);
+ #endif
+ dsb();
+
+ Status = 0;
+
+ for (Index = 0; Index < DATA_LENGTH; Index++) {
+ Value = Data[Index];
+ if (Value != 0xA0A00505) {
+ Status = -1;
+ xil_printf("Data[%d] = %x\r\n", Index, Value);
+ break;
+ }
+ }
+
+ if (!Status) {
+ xil_printf(" Flush worked\r\n");
+ }
+ else {
+ xil_printf("Error: flush dcache range not working\r\n");
+ }
+ dsb();
+ #ifdef __aarch64__
+ CtrlReg = mfcp(SCTLR_EL3);
+ CtrlReg |= (XREG_CONTROL_DCACHE_BIT);
+ mtcp(SCTLR_EL3,CtrlReg);
+ #else
+ CtrlReg = mfcp(XREG_CP15_SYS_CONTROL);
+ CtrlReg |= (XREG_CP15_CONTROL_C_BIT);
+ mtcp(XREG_CP15_SYS_CONTROL, CtrlReg);
+ #endif
+ dsb();
+ for (Index = 0; Index < DATA_LENGTH; Index++)
+ Data[Index] = 0xA0A0C505;
+
+
+
+ Xil_DCacheFlushRange((INTPTR)Data, DATA_LENGTH * sizeof(INTPTR));
+
+ for (Index = 0; Index < DATA_LENGTH; Index++)
+ Data[Index] = Index + 3;
+
+ Xil_DCacheInvalidateRange((INTPTR)Data, DATA_LENGTH * sizeof(INTPTR));
+
+ xil_printf(" invalidate dcache range done\r\n");
+ dsb();
+ #ifdef __aarch64__
+ CtrlReg = mfcp(SCTLR_EL3);
+ CtrlReg &= ~(XREG_CONTROL_DCACHE_BIT);
+ mtcp(SCTLR_EL3,CtrlReg);
+ #else
+ CtrlReg = mfcp(XREG_CP15_SYS_CONTROL);
+ CtrlReg &= ~(XREG_CP15_CONTROL_C_BIT);
+ mtcp(XREG_CP15_SYS_CONTROL, CtrlReg);
+ #endif
+ dsb();
+ for (Index = 0; Index < DATA_LENGTH; Index++)
+ Data[Index] = 0xA0A0A05;
+ dsb();
+ #ifdef __aarch64__
+ CtrlReg = mfcp(SCTLR_EL3);
+ CtrlReg |= (XREG_CONTROL_DCACHE_BIT);
+ mtcp(SCTLR_EL3,CtrlReg);
+ #else
+ CtrlReg = mfcp(XREG_CP15_SYS_CONTROL);
+ CtrlReg |= (XREG_CP15_CONTROL_C_BIT);
+ mtcp(XREG_CP15_SYS_CONTROL, CtrlReg);
+ #endif
+ dsb();
+
+ Status = 0;
+
+ for (Index = 0; Index < DATA_LENGTH; Index++) {
+ Value = Data[Index];
+ if (Value != 0xA0A0A05) {
+ Status = -1;
+ xil_printf("Data[%d] = %x\r\n", Index, Value);
+ break;
+ }
+ }
+
+
+ if (!Status) {
+ xil_printf(" Invalidate worked\r\n");
+ }
+ else {
+ xil_printf("Error: Invalidate dcache range not working\r\n");
+ }
+ xil_printf("-- Cache Range Test Complete --\r\n");
+ return Status;
+
+}
+
+/*****************************************************************************/
+/**
+* @brief Perform DCache all related API test such as Xil_DCacheFlush and
+* Xil_DCacheInvalidate. This test function writes a constant value
+* to the Data array, flushes the DCache, writes a new value,
+* then invalidates the DCache.
+*
+* @return
+* - 0 is returned for a pass
+* - -1 is returned for a failure
+*****************************************************************************/
+s32 Xil_TestDCacheAll(void)
+{
+ s32 Index;
+ s32 Status;
+ INTPTR Value;
+ u32 CtrlReg;
+
+ xil_printf("-- Cache All Test --\n\r");
+
+ for (Index = 0; Index < DATA_LENGTH; Index++)
+ Data[Index] = 0x50500A0A;
+ xil_printf(" initialize Data done:\r\n");
+
+ Xil_DCacheFlush();
+ xil_printf(" flush all done\r\n");
+ dsb();
+ #ifdef __aarch64__
+ CtrlReg = mfcp(SCTLR_EL3);
+ CtrlReg &= ~(XREG_CONTROL_DCACHE_BIT);
+ mtcp(SCTLR_EL3,CtrlReg);
+ #else
+ CtrlReg = mfcp(XREG_CP15_SYS_CONTROL);
+ CtrlReg &= ~(XREG_CP15_CONTROL_C_BIT);
+ mtcp(XREG_CP15_SYS_CONTROL, CtrlReg);
+ #endif
+ dsb();
+ Status = 0;
+
+ for (Index = 0; Index < DATA_LENGTH; Index++) {
+ Value = Data[Index];
+
+ if (Value != 0x50500A0A) {
+ Status = -1;
+ xil_printf("Data[%d] = %x\r\n", Index, Value);
+ break;
+ }
+ }
+
+ if (!Status) {
+ xil_printf(" Flush all worked\r\n");
+ }
+ else {
+ xil_printf("Error: Flush dcache all not working\r\n");
+ }
+ dsb();
+ #ifdef __aarch64__
+ CtrlReg = mfcp(SCTLR_EL3);
+ CtrlReg |= (XREG_CONTROL_DCACHE_BIT);
+ mtcp(SCTLR_EL3,CtrlReg);
+ #else
+ CtrlReg = mfcp(XREG_CP15_SYS_CONTROL);
+ CtrlReg |= (XREG_CP15_CONTROL_C_BIT);
+ mtcp(XREG_CP15_SYS_CONTROL, CtrlReg);
+ #endif
+ dsb();
+ for (Index = 0; Index < DATA_LENGTH; Index++)
+ Data[Index] = 0x505FFA0A;
+
+ Xil_DCacheFlush();
+
+
+ for (Index = 0; Index < DATA_LENGTH; Index++)
+ Data[Index] = Index + 3;
+
+ Xil_DCacheInvalidate();
+
+ xil_printf(" invalidate all done\r\n");
+ dsb();
+ #ifdef __aarch64__
+ CtrlReg = mfcp(SCTLR_EL3);
+ CtrlReg &= ~(XREG_CONTROL_DCACHE_BIT);
+ mtcp(SCTLR_EL3,CtrlReg);
+ #else
+ CtrlReg = mfcp(XREG_CP15_SYS_CONTROL);
+ CtrlReg &= ~(XREG_CP15_CONTROL_C_BIT);
+ mtcp(XREG_CP15_SYS_CONTROL, CtrlReg);
+ #endif
+ dsb();
+ for (Index = 0; Index < DATA_LENGTH; Index++)
+ Data[Index] = 0x50CFA0A;
+ dsb();
+ #ifdef __aarch64__
+ CtrlReg = mfcp(SCTLR_EL3);
+ CtrlReg |= (XREG_CONTROL_DCACHE_BIT);
+ mtcp(SCTLR_EL3,CtrlReg);
+ #else
+ CtrlReg = mfcp(XREG_CP15_SYS_CONTROL);
+ CtrlReg |= (XREG_CP15_CONTROL_C_BIT);
+ mtcp(XREG_CP15_SYS_CONTROL, CtrlReg);
+ #endif
+ dsb();
+ Status = 0;
+
+ for (Index = 0; Index < DATA_LENGTH; Index++) {
+ Value = Data[Index];
+ if (Value != 0x50CFA0A) {
+ Status = -1;
+ xil_printf("Data[%d] = %x\r\n", Index, Value);
+ break;
+ }
+ }
+
+ if (!Status) {
+ xil_printf(" Invalidate all worked\r\n");
+ }
+ else {
+ xil_printf("Error: Invalidate dcache all not working\r\n");
+ }
+
+ xil_printf("-- DCache all Test Complete --\n\r");
+
+ return Status;
+}
+
+/*****************************************************************************/
+/**
+* @brief Perform Xil_ICacheInvalidateRange() on a few function pointers.
+*
+* @return
+* - 0 is returned for a pass
+* @note
+* The function will hang if it fails.
+*****************************************************************************/
+s32 Xil_TestICacheRange(void)
+{
+
+ Xil_ICacheInvalidateRange((INTPTR)Xil_TestICacheRange, 1024);
+ Xil_ICacheInvalidateRange((INTPTR)Xil_TestDCacheRange, 1024);
+ Xil_ICacheInvalidateRange((INTPTR)Xil_TestDCacheAll, 1024);
+
+ xil_printf("-- Invalidate icache range done --\r\n");
+
+ return 0;
+}
+
+/*****************************************************************************/
+/**
+* @brief Perform Xil_ICacheInvalidate() on a few function pointers.
+*
+* @return
+* - 0 is returned for a pass
+* @note
+* The function will hang if it fails.
+*****************************************************************************/
+s32 Xil_TestICacheAll(void)
+{
+ Xil_ICacheInvalidate();
+ xil_printf("-- Invalidate icache all done --\r\n");
+ return 0;
+}
+#endif
diff --git a/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v7_1/src/xil_testcache.h b/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v7_1/src/xil_testcache.h
new file mode 100644
index 0000000..f9d7f19
--- /dev/null
+++ b/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v7_1/src/xil_testcache.h
@@ -0,0 +1,65 @@
+/******************************************************************************
+*
+* Copyright (C) 2009 - 2015 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+* THE SOFTWARE.
+*
+*
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xil_testcache.h
+*
+* @addtogroup common_test_utils
+* <h2>Cache test </h2>
+* The xil_testcache.h file contains utility functions to test cache.
+*
+* @{
+* <pre>
+* Ver Who Date Changes
+* ----- ---- -------- -----------------------------------------------
+* 1.00a hbm 07/29/09 First release
+* </pre>
+*
+******************************************************************************/
+
+#ifndef XIL_TESTCACHE_H /* prevent circular inclusions */
+#define XIL_TESTCACHE_H /* by using protection macros */
+
+#include "xil_types.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+extern s32 Xil_TestDCacheRange(void);
+extern s32 Xil_TestDCacheAll(void);
+extern s32 Xil_TestICacheRange(void);
+extern s32 Xil_TestICacheAll(void);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* end of protection macro */
+/**
+* @} End of "addtogroup common_test_utils".
+*/
\ No newline at end of file
diff --git a/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v7_1/src/xil_testio.c b/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v7_1/src/xil_testio.c
new file mode 100644
index 0000000..f8cc46b
--- /dev/null
+++ b/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v7_1/src/xil_testio.c
@@ -0,0 +1,293 @@
+/******************************************************************************
+*
+* Copyright (C) 2009 - 2015 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+* THE SOFTWARE.
+*
+*
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xil_testio.c
+*
+* Contains the memory test utility functions.
+*
+* <pre>
+* MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ----- ---- -------- -----------------------------------------------
+* 1.00a hbm 08/25/09 First release
+* </pre>
+*
+*****************************************************************************/
+
+/***************************** Include Files ********************************/
+#include "xil_testio.h"
+#include "xil_assert.h"
+#include "xil_io.h"
+
+/************************** Constant Definitions ****************************/
+/************************** Function Prototypes *****************************/
+
+
+
+/**
+ *
+ * Endian swap a 16-bit word.
+ * @param Data is the 16-bit word to be swapped.
+ * @return The endian swapped value.
+ *
+ */
+static u16 Swap16(u16 Data)
+{
+ return ((Data >> 8U) & 0x00FFU) | ((Data << 8U) & 0xFF00U);
+}
+
+/**
+ *
+ * Endian swap a 32-bit word.
+ * @param Data is the 32-bit word to be swapped.
+ * @return The endian swapped value.
+ *
+ */
+static u32 Swap32(u32 Data)
+{
+ u16 Lo16;
+ u16 Hi16;
+
+ u16 Swap16Lo;
+ u16 Swap16Hi;
+
+ Hi16 = (u16)((Data >> 16U) & 0x0000FFFFU);
+ Lo16 = (u16)(Data & 0x0000FFFFU);
+
+ Swap16Lo = Swap16(Lo16);
+ Swap16Hi = Swap16(Hi16);
+
+ return (((u32)(Swap16Lo)) << 16U) | ((u32)Swap16Hi);
+}
+
+/*****************************************************************************/
+/**
+*
+* @brief Perform a destructive 8-bit wide register IO test where the
+* register is accessed using Xil_Out8 and Xil_In8, and comparing
+* the written values by reading them back.
+*
+* @param Addr: a pointer to the region of memory to be tested.
+* @param Length: Length of the block.
+* @param Value: constant used for writing the memory.
+*
+* @return
+* - -1 is returned for a failure
+* - 0 is returned for a pass
+*
+*****************************************************************************/
+
+s32 Xil_TestIO8(u8 *Addr, s32 Length, u8 Value)
+{
+ u8 ValueIn;
+ s32 Index;
+ s32 Status = 0;
+
+ for (Index = 0; Index < Length; Index++) {
+ Xil_Out8((INTPTR)Addr, Value);
+
+ ValueIn = Xil_In8((INTPTR)Addr);
+
+ if ((Value != ValueIn) && (Status == 0)) {
+ Status = -1;
+ break;
+ }
+ }
+ return Status;
+
+}
+
+/*****************************************************************************/
+/**
+*
+* @brief Perform a destructive 16-bit wide register IO test. Each location
+* is tested by sequentially writing a 16-bit wide register, reading
+* the register, and comparing value. This function tests three kinds
+* of register IO functions, normal register IO, little-endian register
+* IO, and big-endian register IO. When testing little/big-endian IO,
+* the function performs the following sequence, Xil_Out16LE/Xil_Out16BE,
+* Xil_In16, Compare In-Out values, Xil_Out16, Xil_In16LE/Xil_In16BE,
+* Compare In-Out values. Whether to swap the read-in value before
+* comparing is controlled by the 5th argument.
+*
+* @param Addr: a pointer to the region of memory to be tested.
+* @param Length: Length of the block.
+* @param Value: constant used for writing the memory.
+* @param Kind: Type of test. Acceptable values are:
+* XIL_TESTIO_DEFAULT, XIL_TESTIO_LE, XIL_TESTIO_BE.
+* @param Swap: indicates whether to byte swap the read-in value.
+*
+* @return
+* - -1 is returned for a failure
+* - 0 is returned for a pass
+*
+*****************************************************************************/
+
+s32 Xil_TestIO16(u16 *Addr, s32 Length, u16 Value, s32 Kind, s32 Swap)
+{
+ u16 *TempAddr16;
+ u16 ValueIn = 0U;
+ s32 Index;
+ TempAddr16 = Addr;
+ Xil_AssertNonvoid(TempAddr16 != NULL);
+
+ for (Index = 0; Index < Length; Index++) {
+ switch (Kind) {
+ case XIL_TESTIO_LE:
+ Xil_Out16LE((INTPTR)TempAddr16, Value);
+ break;
+ case XIL_TESTIO_BE:
+ Xil_Out16BE((INTPTR)TempAddr16, Value);
+ break;
+ default:
+ Xil_Out16((INTPTR)TempAddr16, Value);
+ break;
+ }
+
+ ValueIn = Xil_In16((INTPTR)TempAddr16);
+
+ if ((Kind != 0) && (Swap != 0)) {
+ ValueIn = Swap16(ValueIn);
+ }
+
+ if (Value != ValueIn) {
+ return -1;
+ }
+
+ /* second round */
+ Xil_Out16((INTPTR)TempAddr16, Value);
+
+ switch (Kind) {
+ case XIL_TESTIO_LE:
+ ValueIn = Xil_In16LE((INTPTR)TempAddr16);
+ break;
+ case XIL_TESTIO_BE:
+ ValueIn = Xil_In16BE((INTPTR)TempAddr16);
+ break;
+ default:
+ ValueIn = Xil_In16((INTPTR)TempAddr16);
+ break;
+ }
+
+
+ if ((Kind != 0) && (Swap != 0)) {
+ ValueIn = Swap16(ValueIn);
+ }
+
+ if (Value != ValueIn) {
+ return -1;
+ }
+ TempAddr16 += sizeof(u16);
+ }
+ return 0;
+}
+
+
+/*****************************************************************************/
+/**
+*
+* @brief Perform a destructive 32-bit wide register IO test. Each location
+* is tested by sequentially writing a 32-bit wide register, reading
+* the register, and comparing value. This function tests three kinds
+* of register IO functions, normal register IO, little-endian register IO,
+* and big-endian register IO. When testing little/big-endian IO,
+* the function perform the following sequence, Xil_Out32LE/
+* Xil_Out32BE, Xil_In32, Compare, Xil_Out32, Xil_In32LE/Xil_In32BE, Compare.
+* Whether to swap the read-in value *before comparing is controlled
+* by the 5th argument.
+* @param Addr: a pointer to the region of memory to be tested.
+* @param Length: Length of the block.
+* @param Value: constant used for writing the memory.
+* @param Kind: type of test. Acceptable values are:
+* XIL_TESTIO_DEFAULT, XIL_TESTIO_LE, XIL_TESTIO_BE.
+* @param Swap: indicates whether to byte swap the read-in value.
+*
+* @return
+* - -1 is returned for a failure
+* - 0 is returned for a pass
+*
+*****************************************************************************/
+s32 Xil_TestIO32(u32 *Addr, s32 Length, u32 Value, s32 Kind, s32 Swap)
+{
+ u32 *TempAddr;
+ u32 ValueIn = 0U;
+ s32 Index;
+ TempAddr = Addr;
+ Xil_AssertNonvoid(TempAddr != NULL);
+
+ for (Index = 0; Index < Length; Index++) {
+ switch (Kind) {
+ case XIL_TESTIO_LE:
+ Xil_Out32LE((INTPTR)TempAddr, Value);
+ break;
+ case XIL_TESTIO_BE:
+ Xil_Out32BE((INTPTR)TempAddr, Value);
+ break;
+ default:
+ Xil_Out32((INTPTR)TempAddr, Value);
+ break;
+ }
+
+ ValueIn = Xil_In32((INTPTR)TempAddr);
+
+ if ((Kind != 0) && (Swap != 0)) {
+ ValueIn = Swap32(ValueIn);
+ }
+
+ if (Value != ValueIn) {
+ return -1;
+ }
+
+ /* second round */
+ Xil_Out32((INTPTR)TempAddr, Value);
+
+
+ switch (Kind) {
+ case XIL_TESTIO_LE:
+ ValueIn = Xil_In32LE((INTPTR)TempAddr);
+ break;
+ case XIL_TESTIO_BE:
+ ValueIn = Xil_In32BE((INTPTR)TempAddr);
+ break;
+ default:
+ ValueIn = Xil_In32((INTPTR)TempAddr);
+ break;
+ }
+
+ if ((Kind != 0) && (Swap != 0)) {
+ ValueIn = Swap32(ValueIn);
+ }
+
+ if (Value != ValueIn) {
+ return -1;
+ }
+ TempAddr += sizeof(u32);
+ }
+ return 0;
+}
diff --git a/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v7_1/src/xil_testio.h b/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v7_1/src/xil_testio.h
new file mode 100644
index 0000000..747c49a
--- /dev/null
+++ b/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v7_1/src/xil_testio.h
@@ -0,0 +1,88 @@
+/******************************************************************************
+*
+* Copyright (C) 2009 - 2015 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+* THE SOFTWARE.
+*
+*
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xil_testio.h
+*
+* @addtogroup common_test_utils Test Utilities
+* <h2>I/O test </h2>
+* The xil_testio.h file contains utility functions to test endian related memory
+* IO functions.
+*
+* A subset of the memory tests can be selected or all of the tests can be run
+* in order. If there is an error detected by a subtest, the test stops and the
+* failure code is returned. Further tests are not run even if all of the tests
+* are selected.
+*
+* @{
+* <pre>
+* MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ----- ---- -------- -----------------------------------------------
+* 1.00 hbm 08/05/09 First release
+* </pre>
+*
+******************************************************************************/
+
+#ifndef XIL_TESTIO_H /* prevent circular inclusions */
+#define XIL_TESTIO_H /* by using protection macros */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/***************************** Include Files *********************************/
+#include "xil_types.h"
+
+/************************** Constant Definitions *****************************/
+
+
+#define XIL_TESTIO_DEFAULT 0
+#define XIL_TESTIO_LE 1
+#define XIL_TESTIO_BE 2
+
+/**************************** Type Definitions *******************************/
+
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+
+/************************** Function Prototypes ******************************/
+
+extern s32 Xil_TestIO8(u8 *Addr, s32 Length, u8 Value);
+extern s32 Xil_TestIO16(u16 *Addr, s32 Length, u16 Value, s32 Kind, s32 Swap);
+extern s32 Xil_TestIO32(u32 *Addr, s32 Length, u32 Value, s32 Kind, s32 Swap);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* end of protection macro */
+/**
+* @} End of "addtogroup common_test_utils".
+*/
diff --git a/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v7_1/src/xil_testmem.c b/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v7_1/src/xil_testmem.c
new file mode 100644
index 0000000..dd36b5b
--- /dev/null
+++ b/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v7_1/src/xil_testmem.c
@@ -0,0 +1,862 @@
+/******************************************************************************
+*
+* Copyright (C) 2009 - 2015 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+* THE SOFTWARE.
+*
+*
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xil_testmem.c
+*
+* Contains the memory test utility functions.
+*
+* <pre>
+* MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ----- ---- -------- -----------------------------------------------
+* 1.00a hbm 08/25/09 First release
+* </pre>
+*
+*****************************************************************************/
+
+/***************************** Include Files ********************************/
+#include "xil_testmem.h"
+#include "xil_io.h"
+#include "xil_assert.h"
+
+/************************** Constant Definitions ****************************/
+/************************** Function Prototypes *****************************/
+
+static u32 RotateLeft(u32 Input, u8 Width);
+
+/* define ROTATE_RIGHT to give access to this functionality */
+/* #define ROTATE_RIGHT */
+#ifdef ROTATE_RIGHT
+static u32 RotateRight(u32 Input, u8 Width);
+#endif /* ROTATE_RIGHT */
+
+
+/*****************************************************************************/
+/**
+*
+* @brief Perform a destructive 32-bit wide memory test.
+*
+* @param Addr: pointer to the region of memory to be tested.
+* @param Words: length of the block.
+* @param Pattern: constant used for the constant pattern test, if 0,
+* 0xDEADBEEF is used.
+* @param Subtest: test type selected. See xil_testmem.h for possible
+* values.
+*
+* @return
+* - 0 is returned for a pass
+* - 1 is returned for a failure
+*
+* @note
+* Used for spaces where the address range of the region is smaller than
+* the data width. If the memory range is greater than 2 ** Width,
+* the patterns used in XIL_TESTMEM_WALKONES and XIL_TESTMEM_WALKZEROS will
+* repeat on a boundary of a power of two making it more difficult to detect
+* addressing errors. The XIL_TESTMEM_INCREMENT and XIL_TESTMEM_INVERSEADDR
+* tests suffer the same problem. Ideally, if large blocks of memory are to be
+* tested, break them up into smaller regions of memory to allow the test
+* patterns used not to repeat over the region tested.
+*
+*****************************************************************************/
+s32 Xil_TestMem32(u32 *Addr, u32 Words, u32 Pattern, u8 Subtest)
+{
+ u32 I;
+ u32 j;
+ u32 Val;
+ u32 FirtVal;
+ u32 WordMem32;
+ s32 Status = 0;
+
+ Xil_AssertNonvoid(Words != (u32)0);
+ Xil_AssertNonvoid(Subtest <= (u8)XIL_TESTMEM_MAXTEST);
+ Xil_AssertNonvoid(Addr != NULL);
+
+ /*
+ * variable initialization
+ */
+ Val = XIL_TESTMEM_INIT_VALUE;
+ FirtVal = XIL_TESTMEM_INIT_VALUE;
+
+
+ if((Subtest == XIL_TESTMEM_ALLMEMTESTS) || (Subtest == XIL_TESTMEM_INCREMENT)) {
+ /*
+ * Fill the memory with incrementing
+ * values starting from 'FirtVal'
+ */
+ for (I = 0U; I < Words; I++) {
+ *(Addr+I) = Val;
+ Val++;
+ }
+
+ /*
+ * Restore the reference 'Val' to the
+ * initial value
+ */
+ Val = FirtVal;
+
+ /*
+ * Check every word within the words
+ * of tested memory and compare it
+ * with the incrementing reference
+ * Val
+ */
+
+ for (I = 0U; I < Words; I++) {
+ WordMem32 = *(Addr+I);
+
+ if (WordMem32 != Val) {
+ Status = -1;
+ goto End_Label;
+ }
+
+ Val++;
+ }
+ }
+
+ if((Subtest == XIL_TESTMEM_ALLMEMTESTS) || (Subtest == XIL_TESTMEM_WALKONES)) {
+ /*
+ * set up to cycle through all possible initial
+ * test Patterns for walking ones test
+ */
+
+ for (j = 0U; j < (u32)32; j++) {
+ /*
+ * Generate an initial value for walking ones test
+ * to test for bad data bits
+ */
+
+ Val = (1U << j);
+
+ /*
+ * START walking ones test
+ * Write a one to each data bit indifferent locations
+ */
+
+ for (I = 0U; I < (u32)32; I++) {
+ /* write memory location */
+ *(Addr+I) = Val;
+ Val = (u32) RotateLeft(Val, 32U);
+ }
+
+ /*
+ * Restore the reference 'val' to the
+ * initial value
+ */
+ Val = 1U << j;
+
+ /* Read the values from each location that was
+ * written */
+ for (I = 0U; I < (u32)32; I++) {
+ /* read memory location */
+
+ WordMem32 = *(Addr+I);
+
+ if (WordMem32 != Val) {
+ Status = -1;
+ goto End_Label;
+ }
+
+ Val = (u32)RotateLeft(Val, 32U);
+ }
+ }
+ }
+
+ if((Subtest == XIL_TESTMEM_ALLMEMTESTS) || (Subtest == XIL_TESTMEM_WALKZEROS)) {
+ /*
+ * set up to cycle through all possible
+ * initial test Patterns for walking zeros test
+ */
+
+ for (j = 0U; j < (u32)32; j++) {
+
+ /*
+ * Generate an initial value for walking ones test
+ * to test for bad data bits
+ */
+
+ Val = ~(1U << j);
+
+ /*
+ * START walking zeros test
+ * Write a one to each data bit indifferent locations
+ */
+
+ for (I = 0U; I < (u32)32; I++) {
+ /* write memory location */
+ *(Addr+I) = Val;
+ Val = ~((u32)RotateLeft(~Val, 32U));
+ }
+
+ /*
+ * Restore the reference 'Val' to the
+ * initial value
+ */
+
+ Val = ~(1U << j);
+
+ /* Read the values from each location that was
+ * written */
+ for (I = 0U; I < (u32)32; I++) {
+ /* read memory location */
+ WordMem32 = *(Addr+I);
+ if (WordMem32 != Val) {
+ Status = -1;
+ goto End_Label;
+ }
+ Val = ~((u32)RotateLeft(~Val, 32U));
+ }
+
+ }
+ }
+
+ if((Subtest == XIL_TESTMEM_ALLMEMTESTS) || (Subtest == XIL_TESTMEM_INVERSEADDR)) {
+ /* Fill the memory with inverse of address */
+ for (I = 0U; I < Words; I++) {
+ /* write memory location */
+ Val = (u32) (~((INTPTR) (&Addr[I])));
+ *(Addr+I) = Val;
+ }
+
+ /*
+ * Check every word within the words
+ * of tested memory
+ */
+
+ for (I = 0U; I < Words; I++) {
+ /* Read the location */
+ WordMem32 = *(Addr+I);
+ Val = (u32) (~((INTPTR) (&Addr[I])));
+
+ if ((WordMem32 ^ Val) != 0x00000000U) {
+ Status = -1;
+ goto End_Label;
+ }
+ }
+ }
+
+ if((Subtest == XIL_TESTMEM_ALLMEMTESTS) || (Subtest == XIL_TESTMEM_FIXEDPATTERN)) {
+ /*
+ * Generate an initial value for
+ * memory testing
+ */
+
+ if (Pattern == (u32)0) {
+ Val = 0xDEADBEEFU;
+ }
+ else {
+ Val = Pattern;
+ }
+
+ /*
+ * Fill the memory with fixed Pattern
+ */
+
+ for (I = 0U; I < Words; I++) {
+ /* write memory location */
+ *(Addr+I) = Val;
+ }
+
+ /*
+ * Check every word within the words
+ * of tested memory and compare it
+ * with the fixed Pattern
+ */
+
+ for (I = 0U; I < Words; I++) {
+
+ /* read memory location */
+
+ WordMem32 = *(Addr+I);
+ if (WordMem32 != Val) {
+ Status = -1;
+ goto End_Label;
+ }
+ }
+ }
+
+End_Label:
+ return Status;
+}
+
+/*****************************************************************************/
+/**
+*
+* @brief Perform a destructive 16-bit wide memory test.
+*
+* @param Addr: pointer to the region of memory to be tested.
+* @param Words: length of the block.
+* @param Pattern: constant used for the constant Pattern test, if 0,
+* 0xDEADBEEF is used.
+* @param Subtest: type of test selected. See xil_testmem.h for possible
+* values.
+*
+* @return
+*
+* - -1 is returned for a failure
+* - 0 is returned for a pass
+*
+* @note
+* Used for spaces where the address range of the region is smaller than
+* the data width. If the memory range is greater than 2 ** Width,
+* the patterns used in XIL_TESTMEM_WALKONES and XIL_TESTMEM_WALKZEROS will
+* repeat on a boundary of a power of two making it more difficult to detect
+* addressing errors. The XIL_TESTMEM_INCREMENT and XIL_TESTMEM_INVERSEADDR
+* tests suffer the same problem. Ideally, if large blocks of memory are to be
+* tested, break them up into smaller regions of memory to allow the test
+* patterns used not to repeat over the region tested.
+*
+*****************************************************************************/
+s32 Xil_TestMem16(u16 *Addr, u32 Words, u16 Pattern, u8 Subtest)
+{
+ u32 I;
+ u32 j;
+ u16 Val;
+ u16 FirtVal;
+ u16 WordMem16;
+ s32 Status = 0;
+
+ Xil_AssertNonvoid(Words != (u32)0);
+ Xil_AssertNonvoid(Subtest <= XIL_TESTMEM_MAXTEST);
+ Xil_AssertNonvoid(Addr != NULL);
+
+ /*
+ * variable initialization
+ */
+ Val = XIL_TESTMEM_INIT_VALUE;
+ FirtVal = XIL_TESTMEM_INIT_VALUE;
+
+ /*
+ * selectthe proper Subtest(s)
+ */
+
+ if((Subtest == XIL_TESTMEM_ALLMEMTESTS) || (Subtest == XIL_TESTMEM_INCREMENT)) {
+ /*
+ * Fill the memory with incrementing
+ * values starting from 'FirtVal'
+ */
+ for (I = 0U; I < Words; I++) {
+ /* write memory location */
+ *(Addr+I) = Val;
+ Val++;
+ }
+ /*
+ * Restore the reference 'Val' to the
+ * initial value
+ */
+ Val = FirtVal;
+
+ /*
+ * Check every word within the words
+ * of tested memory and compare it
+ * with the incrementing reference val
+ */
+
+ for (I = 0U; I < Words; I++) {
+ /* read memory location */
+ WordMem16 = *(Addr+I);
+ if (WordMem16 != Val) {
+ Status = -1;
+ goto End_Label;
+ }
+ Val++;
+ }
+ }
+
+ if((Subtest == XIL_TESTMEM_ALLMEMTESTS) || (Subtest == XIL_TESTMEM_WALKONES)) {
+ /*
+ * set up to cycle through all possible initial test
+ * Patterns for walking ones test
+ */
+
+ for (j = 0U; j < (u32)16; j++) {
+ /*
+ * Generate an initial value for walking ones test
+ * to test for bad data bits
+ */
+
+ Val = (u16)((u32)1 << j);
+ /*
+ * START walking ones test
+ * Write a one to each data bit indifferent locations
+ */
+
+ for (I = 0U; I < (u32)16; I++) {
+ /* write memory location */
+ *(Addr+I) = Val;
+ Val = (u16)RotateLeft(Val, 16U);
+ }
+ /*
+ * Restore the reference 'Val' to the
+ * initial value
+ */
+ Val = (u16)((u32)1 << j);
+ /* Read the values from each location that was written */
+ for (I = 0U; I < (u32)16; I++) {
+ /* read memory location */
+ WordMem16 = *(Addr+I);
+ if (WordMem16 != Val) {
+ Status = -1;
+ goto End_Label;
+ }
+ Val = (u16)RotateLeft(Val, 16U);
+ }
+ }
+ }
+
+ if((Subtest == XIL_TESTMEM_ALLMEMTESTS) || (Subtest == XIL_TESTMEM_WALKZEROS)) {
+ /*
+ * set up to cycle through all possible initial
+ * test Patterns for walking zeros test
+ */
+
+ for (j = 0U; j < (u32)16; j++) {
+ /*
+ * Generate an initial value for walking ones
+ * test to test for bad
+ * data bits
+ */
+
+ Val = ~(1U << j);
+ /*
+ * START walking zeros test
+ * Write a one to each data bit indifferent locations
+ */
+
+ for (I = 0U; I < (u32)16; I++) {
+ /* write memory location */
+ *(Addr+I) = Val;
+ Val = ~((u16)RotateLeft(~Val, 16U));
+ }
+ /*
+ * Restore the reference 'Val' to the
+ * initial value
+ */
+ Val = ~(1U << j);
+ /* Read the values from each location that was written */
+ for (I = 0U; I < (u32)16; I++) {
+ /* read memory location */
+ WordMem16 = *(Addr+I);
+ if (WordMem16 != Val) {
+ Status = -1;
+ goto End_Label;
+ }
+ Val = ~((u16)RotateLeft(~Val, 16U));
+ }
+
+ }
+ }
+
+ if((Subtest == XIL_TESTMEM_ALLMEMTESTS) || (Subtest == XIL_TESTMEM_INVERSEADDR)) {
+ /* Fill the memory with inverse of address */
+ for (I = 0U; I < Words; I++) {
+ /* write memory location */
+ Val = (u16) (~((INTPTR)(&Addr[I])));
+ *(Addr+I) = Val;
+ }
+ /*
+ * Check every word within the words
+ * of tested memory
+ */
+
+ for (I = 0U; I < Words; I++) {
+ /* read memory location */
+ WordMem16 = *(Addr+I);
+ Val = (u16) (~((INTPTR) (&Addr[I])));
+ if ((WordMem16 ^ Val) != 0x0000U) {
+ Status = -1;
+ goto End_Label;
+ }
+ }
+ }
+
+ if((Subtest == XIL_TESTMEM_ALLMEMTESTS) || (Subtest == XIL_TESTMEM_FIXEDPATTERN)) {
+ /*
+ * Generate an initial value for
+ * memory testing
+ */
+ if (Pattern == (u16)0) {
+ Val = 0xDEADU;
+ }
+ else {
+ Val = Pattern;
+ }
+
+ /*
+ * Fill the memory with fixed pattern
+ */
+
+ for (I = 0U; I < Words; I++) {
+ /* write memory location */
+ *(Addr+I) = Val;
+ }
+
+ /*
+ * Check every word within the words
+ * of tested memory and compare it
+ * with the fixed pattern
+ */
+
+ for (I = 0U; I < Words; I++) {
+ /* read memory location */
+ WordMem16 = *(Addr+I);
+ if (WordMem16 != Val) {
+ Status = -1;
+ goto End_Label;
+ }
+ }
+ }
+
+End_Label:
+ return Status;
+}
+
+
+/*****************************************************************************/
+/**
+*
+* @brief Perform a destructive 8-bit wide memory test.
+*
+* @param Addr: pointer to the region of memory to be tested.
+* @param Words: length of the block.
+* @param Pattern: constant used for the constant pattern test, if 0,
+* 0xDEADBEEF is used.
+* @param Subtest: type of test selected. See xil_testmem.h for possible
+* values.
+*
+* @return
+* - -1 is returned for a failure
+* - 0 is returned for a pass
+*
+* @note
+* Used for spaces where the address range of the region is smaller than
+* the data width. If the memory range is greater than 2 ** Width,
+* the patterns used in XIL_TESTMEM_WALKONES and XIL_TESTMEM_WALKZEROS will
+* repeat on a boundary of a power of two making it more difficult to detect
+* addressing errors. The XIL_TESTMEM_INCREMENT and XIL_TESTMEM_INVERSEADDR
+* tests suffer the same problem. Ideally, if large blocks of memory are to be
+* tested, break them up into smaller regions of memory to allow the test
+* patterns used not to repeat over the region tested.
+*
+*****************************************************************************/
+s32 Xil_TestMem8(u8 *Addr, u32 Words, u8 Pattern, u8 Subtest)
+{
+ u32 I;
+ u32 j;
+ u8 Val;
+ u8 FirtVal;
+ u8 WordMem8;
+ s32 Status = 0;
+
+ Xil_AssertNonvoid(Words != (u32)0);
+ Xil_AssertNonvoid(Subtest <= XIL_TESTMEM_MAXTEST);
+ Xil_AssertNonvoid(Addr != NULL);
+
+ /*
+ * variable initialization
+ */
+ Val = XIL_TESTMEM_INIT_VALUE;
+ FirtVal = XIL_TESTMEM_INIT_VALUE;
+
+ /*
+ * select the proper Subtest(s)
+ */
+
+ if((Subtest == XIL_TESTMEM_ALLMEMTESTS) || (Subtest == XIL_TESTMEM_INCREMENT)) {
+ /*
+ * Fill the memory with incrementing
+ * values starting from 'FirtVal'
+ */
+ for (I = 0U; I < Words; I++) {
+ /* write memory location */
+ *(Addr+I) = Val;
+ Val++;
+ }
+ /*
+ * Restore the reference 'Val' to the
+ * initial value
+ */
+ Val = FirtVal;
+ /*
+ * Check every word within the words
+ * of tested memory and compare it
+ * with the incrementing reference
+ * Val
+ */
+
+ for (I = 0U; I < Words; I++) {
+ /* read memory location */
+ WordMem8 = *(Addr+I);
+ if (WordMem8 != Val) {
+ Status = -1;
+ goto End_Label;
+ }
+ Val++;
+ }
+ }
+
+ if((Subtest == XIL_TESTMEM_ALLMEMTESTS) || (Subtest == XIL_TESTMEM_WALKONES)) {
+ /*
+ * set up to cycle through all possible initial
+ * test Patterns for walking ones test
+ */
+
+ for (j = 0U; j < (u32)8; j++) {
+ /*
+ * Generate an initial value for walking ones test
+ * to test for bad data bits
+ */
+ Val = (u8)((u32)1 << j);
+ /*
+ * START walking ones test
+ * Write a one to each data bit indifferent locations
+ */
+ for (I = 0U; I < (u32)8; I++) {
+ /* write memory location */
+ *(Addr+I) = Val;
+ Val = (u8)RotateLeft(Val, 8U);
+ }
+ /*
+ * Restore the reference 'Val' to the
+ * initial value
+ */
+ Val = (u8)((u32)1 << j);
+ /* Read the values from each location that was written */
+ for (I = 0U; I < (u32)8; I++) {
+ /* read memory location */
+ WordMem8 = *(Addr+I);
+ if (WordMem8 != Val) {
+ Status = -1;
+ goto End_Label;
+ }
+ Val = (u8)RotateLeft(Val, 8U);
+ }
+ }
+ }
+
+ if((Subtest == XIL_TESTMEM_ALLMEMTESTS) || (Subtest == XIL_TESTMEM_WALKZEROS)) {
+ /*
+ * set up to cycle through all possible initial test
+ * Patterns for walking zeros test
+ */
+
+ for (j = 0U; j < (u32)8; j++) {
+ /*
+ * Generate an initial value for walking ones test to test
+ * for bad data bits
+ */
+ Val = ~(1U << j);
+ /*
+ * START walking zeros test
+ * Write a one to each data bit indifferent locations
+ */
+ for (I = 0U; I < (u32)8; I++) {
+ /* write memory location */
+ *(Addr+I) = Val;
+ Val = ~((u8)RotateLeft(~Val, 8U));
+ }
+ /*
+ * Restore the reference 'Val' to the
+ * initial value
+ */
+ Val = ~(1U << j);
+ /* Read the values from each location that was written */
+ for (I = 0U; I < (u32)8; I++) {
+ /* read memory location */
+ WordMem8 = *(Addr+I);
+ if (WordMem8 != Val) {
+ Status = -1;
+ goto End_Label;
+ }
+
+ Val = ~((u8)RotateLeft(~Val, 8U));
+ }
+ }
+ }
+
+ if((Subtest == XIL_TESTMEM_ALLMEMTESTS) || (Subtest == XIL_TESTMEM_INVERSEADDR)) {
+ /* Fill the memory with inverse of address */
+ for (I = 0U; I < Words; I++) {
+ /* write memory location */
+ Val = (u8) (~((INTPTR) (&Addr[I])));
+ *(Addr+I) = Val;
+ }
+
+ /*
+ * Check every word within the words
+ * of tested memory
+ */
+
+ for (I = 0U; I < Words; I++) {
+ /* read memory location */
+ WordMem8 = *(Addr+I);
+ Val = (u8) (~((INTPTR) (&Addr[I])));
+ if ((WordMem8 ^ Val) != 0x00U) {
+ Status = -1;
+ goto End_Label;
+ }
+ }
+ }
+
+ if((Subtest == XIL_TESTMEM_ALLMEMTESTS) || (Subtest == XIL_TESTMEM_FIXEDPATTERN)) {
+ /*
+ * Generate an initial value for
+ * memory testing
+ */
+
+ if (Pattern == (u8)0) {
+ Val = 0xA5U;
+ }
+ else {
+ Val = Pattern;
+ }
+ /*
+ * Fill the memory with fixed Pattern
+ */
+ for (I = 0U; I < Words; I++) {
+ /* write memory location */
+ *(Addr+I) = Val;
+ }
+ /*
+ * Check every word within the words
+ * of tested memory and compare it
+ * with the fixed Pattern
+ */
+
+ for (I = 0U; I < Words; I++) {
+ /* read memory location */
+ WordMem8 = *(Addr+I);
+ if (WordMem8 != Val) {
+ Status = -1;
+ goto End_Label;
+ }
+ }
+ }
+
+End_Label:
+ return Status;
+}
+
+
+/*****************************************************************************/
+/**
+*
+* @brief Rotates the provided value to the left one bit position
+*
+* @param Input is value to be rotated to the left
+* @param Width is the number of bits in the input data
+*
+* @return
+* The resulting unsigned long value of the rotate left
+*
+*
+*****************************************************************************/
+static u32 RotateLeft(u32 Input, u8 Width)
+{
+ u32 Msb;
+ u32 ReturnVal;
+ u32 WidthMask;
+ u32 MsbMask;
+ u32 LocalInput = Input;
+
+ /*
+ * set up the WidthMask and the MsbMask
+ */
+
+ MsbMask = 1U << (Width - 1U);
+
+ WidthMask = (MsbMask << (u32)1) - (u32)1;
+
+ /*
+ * set the Width of the Input to the correct width
+ */
+
+ LocalInput = LocalInput & WidthMask;
+
+ Msb = LocalInput & MsbMask;
+
+ ReturnVal = LocalInput << 1U;
+
+ if (Msb != 0x00000000U) {
+ ReturnVal = ReturnVal | (u32)0x00000001;
+ }
+
+ ReturnVal = ReturnVal & WidthMask;
+
+ return ReturnVal;
+
+}
+
+#ifdef ROTATE_RIGHT
+/*****************************************************************************/
+/**
+*
+* @brief Rotates the provided value to the right one bit position
+*
+* @param Input: value to be rotated to the right
+* @param Width: number of bits in the input data
+*
+* @return
+* The resulting u32 value of the rotate right
+*
+*****************************************************************************/
+static u32 RotateRight(u32 Input, u8 Width)
+{
+ u32 Lsb;
+ u32 ReturnVal;
+ u32 WidthMask;
+ u32 MsbMask;
+ u32 LocalInput = Input;
+ /*
+ * set up the WidthMask and the MsbMask
+ */
+
+ MsbMask = 1U << (Width - 1U);
+
+ WidthMask = (MsbMask << 1U) - 1U;
+
+ /*
+ * set the width of the input to the correct width
+ */
+
+ LocalInput = LocalInput & WidthMask;
+
+ ReturnVal = LocalInput >> 1U;
+
+ Lsb = LocalInput & 0x00000001U;
+
+ if (Lsb != 0x00000000U) {
+ ReturnVal = ReturnVal | MsbMask;
+ }
+
+ ReturnVal = ReturnVal & WidthMask;
+
+ return ReturnVal;
+
+}
+#endif /* ROTATE_RIGHT */
diff --git a/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v7_1/src/xil_testmem.h b/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v7_1/src/xil_testmem.h
new file mode 100644
index 0000000..6d9c597
--- /dev/null
+++ b/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v7_1/src/xil_testmem.h
@@ -0,0 +1,152 @@
+/******************************************************************************
+*
+* Copyright (C) 2009 - 2015 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+* THE SOFTWARE.
+*
+*
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xil_testmem.h
+* @addtogroup common_test_utils
+*
+* <h2>Memory test</h2>
+*
+* The xil_testmem.h file contains utility functions to test memory.
+* A subset of the memory tests can be selected or all of the tests can be run
+* in order. If there is an error detected by a subtest, the test stops and the
+* failure code is returned. Further tests are not run even if all of the tests
+* are selected.
+* Following list describes the supported memory tests:
+*
+* - XIL_TESTMEM_ALLMEMTESTS: This test runs all of the subtests.
+*
+* - XIL_TESTMEM_INCREMENT: This test
+* starts at 'XIL_TESTMEM_INIT_VALUE' and uses the incrementing value as the
+* test value for memory.
+*
+* - XIL_TESTMEM_WALKONES: Also known as the Walking ones test. This test
+* uses a walking '1' as the test value for memory.
+* @code
+* location 1 = 0x00000001
+* location 2 = 0x00000002
+* ...
+* @endcode
+*
+* - XIL_TESTMEM_WALKZEROS: Also known as the Walking zero's test.
+* This test uses the inverse value of the walking ones test
+* as the test value for memory.
+* @code
+* location 1 = 0xFFFFFFFE
+* location 2 = 0xFFFFFFFD
+* ...
+*@endcode
+*
+* - XIL_TESTMEM_INVERSEADDR: Also known as the inverse address test.
+* This test uses the inverse of the address of the location under test
+* as the test value for memory.
+*
+* - XIL_TESTMEM_FIXEDPATTERN: Also known as the fixed pattern test.
+* This test uses the provided patters as the test value for memory.
+* If zero is provided as the pattern the test uses '0xDEADBEEF".
+*
+* @warning
+* The tests are <b>DESTRUCTIVE</b>. Run before any initialized memory spaces
+* have been set up.
+* The address provided to the memory tests is not checked for
+* validity except for the NULL case. It is possible to provide a code-space
+* pointer for this test to start with and ultimately destroy executable code
+* causing random failures.
+*
+* @note
+* Used for spaces where the address range of the region is smaller than
+* the data width. If the memory range is greater than 2 ** width,
+* the patterns used in XIL_TESTMEM_WALKONES and XIL_TESTMEM_WALKZEROS will
+* repeat on a boundary of a power of two making it more difficult to detect
+* addressing errors. The XIL_TESTMEM_INCREMENT and XIL_TESTMEM_INVERSEADDR
+* tests suffer the same problem. Ideally, if large blocks of memory are to be
+* tested, break them up into smaller regions of memory to allow the test
+* patterns used not to repeat over the region tested.
+*
+* <pre>
+* MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ----- ---- -------- -----------------------------------------------
+* 1.00a hbm 08/25/09 First release
+* </pre>
+*
+******************************************************************************/
+
+#ifndef XIL_TESTMEM_H /* prevent circular inclusions */
+#define XIL_TESTMEM_H /* by using protection macros */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/***************************** Include Files *********************************/
+#include "xil_types.h"
+
+/************************** Constant Definitions *****************************/
+
+
+/**************************** Type Definitions *******************************/
+
+/* xutil_memtest defines */
+
+#define XIL_TESTMEM_INIT_VALUE 1U
+
+/** @name Memory subtests
+ * @{
+ */
+/**
+ * See the detailed description of the subtests in the file description.
+ */
+#define XIL_TESTMEM_ALLMEMTESTS 0x00U
+#define XIL_TESTMEM_INCREMENT 0x01U
+#define XIL_TESTMEM_WALKONES 0x02U
+#define XIL_TESTMEM_WALKZEROS 0x03U
+#define XIL_TESTMEM_INVERSEADDR 0x04U
+#define XIL_TESTMEM_FIXEDPATTERN 0x05U
+#define XIL_TESTMEM_MAXTEST XIL_TESTMEM_FIXEDPATTERN
+/* @} */
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+
+/************************** Function Prototypes ******************************/
+
+/* xutil_testmem prototypes */
+
+extern s32 Xil_TestMem32(u32 *Addr, u32 Words, u32 Pattern, u8 Subtest);
+extern s32 Xil_TestMem16(u16 *Addr, u32 Words, u16 Pattern, u8 Subtest);
+extern s32 Xil_TestMem8(u8 *Addr, u32 Words, u8 Pattern, u8 Subtest);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* end of protection macro */
+/**
+* @} End of "addtogroup common_test_utils".
+*/
diff --git a/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v7_1/src/xil_types.h b/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v7_1/src/xil_types.h
new file mode 100644
index 0000000..f88edf2
--- /dev/null
+++ b/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v7_1/src/xil_types.h
@@ -0,0 +1,217 @@
+/******************************************************************************
+*
+* Copyright (C) 2010 - 2019 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+* THE SOFTWARE.
+*
+*
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xil_types.h
+*
+* @addtogroup common_types Basic Data types for Xilinx® Software IP
+*
+* The xil_types.h file contains basic types for Xilinx software IP. These data types
+* are applicable for all processors supported by Xilinx.
+* @{
+* <pre>
+* MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ----- ---- -------- -------------------------------------------------------
+* 1.00a hbm 07/14/09 First release
+* 3.03a sdm 05/30/11 Added Xuint64 typedef and XUINT64_MSW/XUINT64_LSW macros
+* 5.00 pkp 05/29/14 Made changes for 64 bit architecture
+* srt 07/14/14 Use standard definitions from stdint.h and stddef.h
+* Define LONG and ULONG datatypes and mask values
+* 7.00 mus 01/07/19 Add cpp extern macro
+* 7.1 aru 08/19/19 Shift the value in UPPER_32_BITS only if it
+* is 64-bit processor
+* </pre>
+*
+******************************************************************************/
+
+#ifndef XIL_TYPES_H /* prevent circular inclusions */
+#define XIL_TYPES_H /* by using protection macros */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <stdint.h>
+#include <stddef.h>
+
+/************************** Constant Definitions *****************************/
+
+#ifndef TRUE
+# define TRUE 1U
+#endif
+
+#ifndef FALSE
+# define FALSE 0U
+#endif
+
+#ifndef NULL
+#define NULL 0U
+#endif
+
+#define XIL_COMPONENT_IS_READY 0x11111111U /**< In device drivers, This macro will be
+ assigend to "IsReady" member of driver
+ instance to indicate that driver
+ instance is initialized and ready to use. */
+#define XIL_COMPONENT_IS_STARTED 0x22222222U /**< In device drivers, This macro will be assigend to
+ "IsStarted" member of driver instance
+ to indicate that driver instance is
+ started and it can be enabled. */
+
+/* @name New types
+ * New simple types.
+ * @{
+ */
+#ifndef __KERNEL__
+#ifndef XBASIC_TYPES_H
+/*
+ * guarded against xbasic_types.h.
+ */
+typedef uint8_t u8;
+typedef uint16_t u16;
+typedef uint32_t u32;
+/** @}*/
+#define __XUINT64__
+typedef struct
+{
+ u32 Upper;
+ u32 Lower;
+} Xuint64;
+
+
+/*****************************************************************************/
+/**
+* @brief Return the most significant half of the 64 bit data type.
+*
+* @param x is the 64 bit word.
+*
+* @return The upper 32 bits of the 64 bit word.
+*
+******************************************************************************/
+#define XUINT64_MSW(x) ((x).Upper)
+
+/*****************************************************************************/
+/**
+* @brief Return the least significant half of the 64 bit data type.
+*
+* @param x is the 64 bit word.
+*
+* @return The lower 32 bits of the 64 bit word.
+*
+******************************************************************************/
+#define XUINT64_LSW(x) ((x).Lower)
+
+#endif /* XBASIC_TYPES_H */
+
+/*
+ * xbasic_types.h does not typedef s* or u64
+ */
+/** @{ */
+typedef char char8;
+typedef int8_t s8;
+typedef int16_t s16;
+typedef int32_t s32;
+typedef int64_t s64;
+typedef uint64_t u64;
+typedef int sint32;
+
+typedef intptr_t INTPTR;
+typedef uintptr_t UINTPTR;
+typedef ptrdiff_t PTRDIFF;
+/** @}*/
+#if !defined(LONG) || !defined(ULONG)
+typedef long LONG;
+typedef unsigned long ULONG;
+#endif
+
+#define ULONG64_HI_MASK 0xFFFFFFFF00000000U
+#define ULONG64_LO_MASK ~ULONG64_HI_MASK
+
+#else
+#include <linux/types.h>
+#endif
+
+/** @{ */
+/**
+ * This data type defines an interrupt handler for a device.
+ * The argument points to the instance of the component
+ */
+typedef void (*XInterruptHandler) (void *InstancePtr);
+
+/**
+ * This data type defines an exception handler for a processor.
+ * The argument points to the instance of the component
+ */
+typedef void (*XExceptionHandler) (void *InstancePtr);
+
+/**
+ * @brief Returns 32-63 bits of a number.
+ * @param n : Number being accessed.
+ * @return Bits 32-63 of number.
+ *
+ * @note A basic shift-right of a 64- or 32-bit quantity.
+ * Use this to suppress the "right shift count >= width of type"
+ * warning when that quantity is 32-bits.
+ */
+#if defined (__aarch64__) || defined (__arch64__)
+#define UPPER_32_BITS(n) ((u32)(((n) >> 16) >> 16))
+#else
+#define UPPER_32_BITS(n) 0U
+#endif
+/**
+ * @brief Returns 0-31 bits of a number
+ * @param n : Number being accessed.
+ * @return Bits 0-31 of number
+ */
+#define LOWER_32_BITS(n) ((u32)(n))
+
+
+
+
+/************************** Constant Definitions *****************************/
+
+#ifndef TRUE
+#define TRUE 1U
+#endif
+
+#ifndef FALSE
+#define FALSE 0U
+#endif
+
+#ifndef NULL
+#define NULL 0U
+#endif
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* end of protection macro */
+/**
+* @} End of "addtogroup common_types".
+*/
diff --git a/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v7_1/src/xil_util.c b/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v7_1/src/xil_util.c
new file mode 100644
index 0000000..07118a4
--- /dev/null
+++ b/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v7_1/src/xil_util.c
@@ -0,0 +1,389 @@
+/******************************************************************************/
+/**
+* Copyright (C) 2019 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+* THE SOFTWARE.
+*
+*
+*
+******************************************************************************/
+/****************************************************************************/
+/**
+* @file xil_util.c
+*
+* This file contains xil utility functions
+*
+* <pre>
+* MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ----- -------- -------- -----------------------------------------------
+* 6.4 mmd 04/21/19 First release.
+*
+* </pre>
+*
+*****************************************************************************/
+
+/****************************** Include Files *********************************/
+#include "xil_util.h"
+
+/************************** Constant Definitions ****************************/
+#define MAX_NIBBLES 8U
+
+/************************** Function Prototypes *****************************/
+/****************************************************************************/
+/**
+ * Converts the char into the equivalent nibble.
+ * Ex: 'a' -> 0xa, 'A' -> 0xa, '9'->0x9
+ *
+ * @param InChar - Input character to be converted to nibble.
+ * Valid characters are between 0-9, a-f, A-F
+ * @param Num - Memory location where nibble is to be stored
+ *
+ * @return
+ * XST_SUCCESS - Character converted to nibble
+ * XST_FAILURE - Invalid input character
+ *
+ * @note None.
+ *
+ *****************************************************************************/
+
+u32 Xil_ConvertCharToNibble(u8 InChar, u8 *Num)
+{
+ u32 Status;
+
+ /* Convert the char to nibble */
+ if ((InChar >= (u8)'0') && (InChar <= (u8)'9')) {
+ *Num = InChar - (u8)'0';
+ Status = XST_SUCCESS;
+ }
+ else if ((InChar >= (u8)'a') && (InChar <= (u8)'f')) {
+ *Num = InChar - (u8)'a' + 10U;
+ Status = XST_SUCCESS;
+ }
+ else if ((InChar >= (u8)'A') && (InChar <= (u8)'F')) {
+ *Num = InChar - (u8)'A' + 10U;
+ Status = XST_SUCCESS;
+ }
+ else {
+ Status = XST_FAILURE;
+ }
+
+ return Status;
+}
+
+/****************************************************************************/
+/*
+ * Converts the string into the equivalent Hex buffer.
+ * Ex: "abc123" -> {0xab, 0xc1, 0x23}
+ *
+ * @param Str - Pointer to string to be converted to Hex.
+ * Accepted characters in string are between 0-9, a-f and A-F
+ * @param Buf - Pointer to memory location where converted hex values are to
+ * be stored.
+ * @param Len - Length of input string
+ *
+ * @return
+ * XST_SUCCESS - Input string is converted to hex
+ * XST_FAILURE - Invalid character in inpit string
+ *
+ * @note None.
+ *
+ *****************************************************************************/
+u32 Xil_ConvertStringToHex(const char *Str, u32 *buf, u8 Len)
+{
+ u32 Status = XST_FAILURE;
+ u8 ConvertedLen = 0U, index = 0U;
+ u8 Nibble[MAX_NIBBLES] = {0U};
+ u8 i;
+
+ while (ConvertedLen < Len) {
+ for (i = 0U; i < MAX_NIBBLES; i++) {
+ Status = Xil_ConvertCharToNibble(Str[ConvertedLen],
+ &Nibble[i]);
+ ConvertedLen = ConvertedLen +1U;
+ if (Status != XST_SUCCESS) {
+ /* Error converting char to nibble */
+ goto END;
+ }
+ }
+
+ buf[index] = ((Nibble[0] << (u8)28U) | (Nibble[1] << (u8)24U) |
+ (Nibble[2] << (u8)20U) | (Nibble[3] << (u8)16U) |
+ (Nibble[4] << (u8)12U) | (Nibble[5] << (u8)8U) |
+ (Nibble[6] << (u8)4U) | (u32)Nibble[7]);
+ index++;
+ }
+END:
+ return Status;
+}
+
+/****************************************************************************/
+/*
+ * Waits for the event
+ *
+ * @param RegAddr - Address of register to be checked for event(s) occurance
+ * @param EventMask - Mask indicating event(s) to be checked
+ * @param Event - Specific event(s) value to be checked
+ * @param Timeout - Free counter decremented on each event(s) check and
+ * declared timeout when reaches 0
+ *
+ * @return
+ * XST_SUCCESS - On occurance of the event(s).
+ * XST_FAILURE - Event did not occur before counter reaches 0
+ *
+ * @note None.
+ *
+ *****************************************************************************/
+u32 Xil_WaitForEvent(u32 RegAddr, u32 EventMask, u32 Event, u32 Timeout)
+{
+ u32 EventStatus;
+ u32 PollCount = Timeout;
+ u32 Status = XST_FAILURE;
+
+ while(PollCount > 0) {
+ EventStatus = Xil_In32(RegAddr) & EventMask;
+ if (EventStatus == Event) {
+ Status = XST_SUCCESS;
+ break;
+ }
+ PollCount--;
+ }
+
+ return Status;
+}
+
+
+/******************************************************************************/
+/**
+ * Waits for the events. Returns on occurrence of first event / timeout.
+ *
+ * @param RegAddr - Address of register to be checked for event(s)
+ * occurrence
+ * @param EventMask - Mask indicating event(s) to be checked
+ * @param WaitEvents - Specific event(s) to be checked
+ * @param Timeout - Free counter decremented on each event(s) check and
+ * declared timeout when reaches 0
+ * @param Events - Mask of Events occured returned in memory pointed by
+ * this variable
+ *
+ * @return
+ * XST_SUCCESS - On occurrence of the event(s).
+ * XST_FAILURE - Event did not occur before counter reaches 0
+ *
+ * @note None.
+ *
+ ******************************************************************************/
+u32 Xil_WaitForEvents(u32 EventsRegAddr, u32 EventsMask, u32 WaitEvents,
+ u32 Timeout, u32* Events)
+{
+ u32 EventStatus;
+ u32 PollCount = Timeout;
+ u32 Status = XST_TIMEOUT;
+
+ *Events = 0x00;
+ do {
+ EventStatus = Xil_In32(EventsRegAddr);
+ EventStatus &= EventsMask;
+ if(EventStatus & WaitEvents) {
+ Status = XST_SUCCESS;
+ *Events = EventStatus;
+ break;
+ }
+ PollCount--;
+ }
+ while(PollCount > 0);
+
+ return Status;
+}
+
+/******************************************************************************/
+/**
+ * Checks whether the passed character is a valid hex digit
+ *
+ * @param Ch - Input Character
+ *
+ * @return
+ * XST_SUCCESS - on valid hex digit
+ * XST_FAILURE - on invalid hex digit
+ *
+ * @note None.
+ *
+ ******************************************************************************/
+u32 Xil_IsValidHexChar(const char Ch)
+{
+ char ValidChars[] = "0123456789abcdefABCDEF";
+ char *RetVal;
+ u32 Status = XST_FAILURE;
+
+ RetVal = strchr(ValidChars, (int)Ch);
+ if (RetVal != NULL) {
+ Status = XST_SUCCESS;
+ }
+
+ return Status;
+}
+
+/******************************************************************************/
+/**
+ * Validate the input string contains only hexadecimal characters
+ *
+ * @param HexStr - Pointer to string to be validated
+ *
+ * @return
+ * XST_SUCCESS - On valid input hex string
+ * XST_INVALID_PARAM - On invalid length of the input string
+ * XST_FAILURE - On non hexadecimal character in string
+ *
+ * @note None
+ *
+ ******************************************************************************/
+u32 Xil_ValidateHexStr(const char *HexStr)
+{
+ u32 Idx;
+ u32 Len;
+ u32 Status = XST_INVALID_PARAM;
+
+ if(NULL == HexStr) {
+ goto END;
+ }
+
+ Len = Xil_Strnlen(HexStr, XIL_MAX_HEX_STR_LEN + 1U);
+ if (Len > XIL_MAX_HEX_STR_LEN) {
+ goto END;
+ }
+
+ for (Idx = 0U; Idx < Len; Idx++) {
+ Status = Xil_IsValidHexChar(HexStr[Idx]);
+ if (Status != XST_SUCCESS) {
+ break;
+ }
+ }
+
+END:
+ return Status;
+}
+
+/******************************************************************************/
+/**
+ * Converts the string into the equivalent Hex buffer.
+ * Ex: "abc123" -> {0x23, 0xc1, 0xab}
+ *
+ * @param Str - Input String to be converted to hex number in little
+ * endian format. Valid characters of input strin are between
+ * 0-9, a-f and A-F
+ * @param Buf - Pointer to memory location where converted hex numbers are to
+ * be stored.
+ * @param Len - Expected number of output bits
+ *
+ * @return
+ * XST_SUCCESS - Input string is converted to hex number(s)
+ * XST_FAILURE - Invalid input character detected in input string
+ *
+ * @note
+ *
+ ******************************************************************************/
+u32 Xil_ConvertStringToHexLE(const char *Str, u8 *Buf, u32 Len)
+{
+ u32 ConvertedLen;
+ u8 LowerNibble = 0U;
+ u8 UpperNibble = 0U;
+ u32 StrIndex;
+ u32 Status = XST_FAILURE;
+
+ if ((NULL == Str) || (NULL == Buf)) {
+ Status = XST_INVALID_PARAM;
+ goto END;
+ }
+
+ if ((Len == 0U) || ((Len % XIL_SIZE_OF_BYTE_IN_BITS) != 0U)) {
+ Status = XST_INVALID_PARAM;
+ goto END;
+ }
+
+ if(Len != (strlen(Str) * XIL_SIZE_OF_NIBBLE_IN_BITS)) {
+ Status = XST_INVALID_PARAM;
+ goto END;
+ }
+
+ StrIndex = (Len / XIL_SIZE_OF_BYTE_IN_BITS) - 1U;
+ ConvertedLen = 0U;
+ while (ConvertedLen < (Len / XIL_SIZE_OF_NIBBLE_IN_BITS)) {
+ Status = Xil_ConvertCharToNibble(Str[ConvertedLen],
+ &UpperNibble);
+ if (XST_SUCCESS == Status) {
+ Status = Xil_ConvertCharToNibble(Str[ConvertedLen + 1],
+ &LowerNibble);
+ if (XST_SUCCESS == Status) {
+ Buf[StrIndex] =
+ (UpperNibble << XIL_SIZE_OF_NIBBLE_IN_BITS) |
+ LowerNibble;
+ StrIndex = StrIndex - 1U;
+ }
+ else {
+ Status = XST_INVALID_PARAM;
+ goto END;
+ }
+ }
+ else {
+ Status = XST_INVALID_PARAM;
+ goto END;
+ }
+ ConvertedLen += 2U;
+ }
+
+ Status = XST_SUCCESS;
+END:
+ return Status;
+}
+
+/******************************************************************************/
+/**
+ * Returns the length of input string.
+ *
+ * @param Str - Input string
+ * @param MaxLen - Maximum expected length of the input string
+ *
+ * @return
+ * Returns length of the input string if length is less than MaxLen.
+ * Returns MaxLen if the length of the input string is >= MaxLen.
+ *
+ * @note
+ *
+ ******************************************************************************/
+u32 Xil_Strnlen(const char *Str, u32 MaxLen)
+{
+ const char *InStr = Str;
+ u32 StrLen = 0U;
+
+ if (NULL == Str) {
+ goto END;
+ }
+
+ while(StrLen < MaxLen) {
+ if ('\0' == *InStr) {
+ break;
+ }
+ StrLen++;
+ InStr++;
+ }
+
+END:
+ return StrLen;
+}
diff --git a/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v7_1/src/xil_util.h b/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v7_1/src/xil_util.h
new file mode 100644
index 0000000..41eae4b
--- /dev/null
+++ b/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v7_1/src/xil_util.h
@@ -0,0 +1,112 @@
+/******************************************************************************/
+/**
+* Copyright (C) 2019 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+* THE SOFTWARE.
+*
+*
+*
+******************************************************************************/
+/****************************************************************************/
+/**
+* @file xil_util.h
+*
+* This file contains xil utility functions declaration
+*
+* <pre>
+* MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ----- -------- -------- -----------------------------------------------
+* 6.4 mmd 04/21/19 First release.
+*
+* </pre>
+*
+*****************************************************************************/
+
+#ifndef XIL_UTIL_H_
+#define XIL_UTIL_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include "xil_types.h"
+#include "xil_io.h"
+#include "xstatus.h"
+
+/*************************** Constant Definitions *****************************/
+#define XIL_SIZE_OF_NIBBLE_IN_BITS 4U
+#define XIL_SIZE_OF_BYTE_IN_BITS 8U
+
+/* Maximum string length handled by Xil_ValidateHexStr function */
+#define XIL_MAX_HEX_STR_LEN 512U
+
+
+/****************** Macros (Inline Functions) Definitions *********************/
+
+/******************************************************************************/
+/**
+* This API ceils the provided float value.
+*
+* @param Value is a float variable which has to ceiled to nearest
+* integer.
+*
+* @return Returns ceiled value.
+*
+* @note one.
+*
+*******************************************************************************/
+#define Xil_Ceil(Value) \
+ (((Value > (u32)Value) || ((u32)Value == 0U)) ? \
+ (u32)((u32)Value + 1U) : (u32)Value)
+
+
+/*************************** Function Prototypes ******************************/
+
+/* Converts input character to nibble */
+u32 Xil_ConvertCharToNibble(u8 InChar, u8 *Num);
+
+/* Convert input hex string to array of 32-bits integers */
+u32 Xil_ConvertStringToHex(const char *Str, u32 *buf, u8 Len);
+
+/* Waits for specified event */
+u32 Xil_WaitForEvent(u32 RegAddr, u32 EventMask, u32 Event, u32 Timeout);
+
+/* Waits for specified events */
+u32 Xil_WaitForEvents(u32 EventsRegAddr, u32 EventsMask, u32 WaitEvents,
+ u32 Timeout, u32* Events);
+
+/* Validate input hex character */
+u32 Xil_IsValidHexChar(const char Ch);
+
+/* Validate the input string contains only hexadecimal characters */
+u32 Xil_ValidateHexStr(const char *HexStr);
+
+/* Convert string to hex numbers in little enidian format */
+u32 Xil_ConvertStringToHexLE(const char *Str, u8 *Buf, u32 Len);
+
+/* Returns length of the input string */
+u32 Xil_Strnlen(const char *Str, u32 MaxLen);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* XIL_UTIL_H_ */
diff --git a/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v7_1/src/xl2cc.h b/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v7_1/src/xl2cc.h
new file mode 100644
index 0000000..c8c46c9
--- /dev/null
+++ b/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v7_1/src/xl2cc.h
@@ -0,0 +1,166 @@
+/******************************************************************************
+*
+* Copyright (C) 2011 - 2015 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+* THE SOFTWARE.
+*
+*
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+* @file xl2cc.h
+*
+* This file contains the address definitions for the PL310 Level-2 Cache
+* Controller.
+*
+* <pre>
+* MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ----- ---- -------- ---------------------------------------------------
+* 1.00a sdm 02/01/10 Initial version
+* 3.10a srt 04/18/13 Implemented ARM Erratas. Please refer to file
+* 'xil_errata.h' for errata description
+* </pre>
+*
+* @note
+*
+* None.
+*
+******************************************************************************/
+
+#ifndef _XL2CC_H_
+#define _XL2CC_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/************************** Constant Definitions *****************************/
+/* L2CC Register Offsets */
+#define XPS_L2CC_ID_OFFSET 0x0000U
+#define XPS_L2CC_TYPE_OFFSET 0x0004U
+#define XPS_L2CC_CNTRL_OFFSET 0x0100U
+#define XPS_L2CC_AUX_CNTRL_OFFSET 0x0104U
+#define XPS_L2CC_TAG_RAM_CNTRL_OFFSET 0x0108U
+#define XPS_L2CC_DATA_RAM_CNTRL_OFFSET 0x010CU
+
+#define XPS_L2CC_EVNT_CNTRL_OFFSET 0x0200U
+#define XPS_L2CC_EVNT_CNT1_CTRL_OFFSET 0x0204U
+#define XPS_L2CC_EVNT_CNT0_CTRL_OFFSET 0x0208U
+#define XPS_L2CC_EVNT_CNT1_VAL_OFFSET 0x020CU
+#define XPS_L2CC_EVNT_CNT0_VAL_OFFSET 0x0210U
+
+#define XPS_L2CC_IER_OFFSET 0x0214U /* Interrupt Mask */
+#define XPS_L2CC_IPR_OFFSET 0x0218U /* Masked interrupt status */
+#define XPS_L2CC_ISR_OFFSET 0x021CU /* Raw Interrupt Status */
+#define XPS_L2CC_IAR_OFFSET 0x0220U /* Interrupt Clear */
+
+#define XPS_L2CC_CACHE_SYNC_OFFSET 0x0730U /* Cache Sync */
+#define XPS_L2CC_DUMMY_CACHE_SYNC_OFFSET 0x0740U /* Dummy Register for Cache Sync */
+#define XPS_L2CC_CACHE_INVLD_PA_OFFSET 0x0770U /* Cache Invalid by PA */
+#define XPS_L2CC_CACHE_INVLD_WAY_OFFSET 0x077CU /* Cache Invalid by Way */
+#define XPS_L2CC_CACHE_CLEAN_PA_OFFSET 0x07B0U /* Cache Clean by PA */
+#define XPS_L2CC_CACHE_CLEAN_INDX_OFFSET 0x07B8U /* Cache Clean by Index */
+#define XPS_L2CC_CACHE_CLEAN_WAY_OFFSET 0x07BCU /* Cache Clean by Way */
+#define XPS_L2CC_CACHE_INV_CLN_PA_OFFSET 0x07F0U /* Cache Invalidate and Clean by PA */
+#define XPS_L2CC_CACHE_INV_CLN_INDX_OFFSET 0x07F8U /* Cache Invalidate and Clean by Index */
+#define XPS_L2CC_CACHE_INV_CLN_WAY_OFFSET 0x07FCU /* Cache Invalidate and Clean by Way */
+
+#define XPS_L2CC_CACHE_DLCKDWN_0_WAY_OFFSET 0x0900U /* Cache Data Lockdown 0 by Way */
+#define XPS_L2CC_CACHE_ILCKDWN_0_WAY_OFFSET 0x0904U /* Cache Instruction Lockdown 0 by Way */
+#define XPS_L2CC_CACHE_DLCKDWN_1_WAY_OFFSET 0x0908U /* Cache Data Lockdown 1 by Way */
+#define XPS_L2CC_CACHE_ILCKDWN_1_WAY_OFFSET 0x090CU /* Cache Instruction Lockdown 1 by Way */
+#define XPS_L2CC_CACHE_DLCKDWN_2_WAY_OFFSET 0x0910U /* Cache Data Lockdown 2 by Way */
+#define XPS_L2CC_CACHE_ILCKDWN_2_WAY_OFFSET 0x0914U /* Cache Instruction Lockdown 2 by Way */
+#define XPS_L2CC_CACHE_DLCKDWN_3_WAY_OFFSET 0x0918U /* Cache Data Lockdown 3 by Way */
+#define XPS_L2CC_CACHE_ILCKDWN_3_WAY_OFFSET 0x091CU /* Cache Instruction Lockdown 3 by Way */
+#define XPS_L2CC_CACHE_DLCKDWN_4_WAY_OFFSET 0x0920U /* Cache Data Lockdown 4 by Way */
+#define XPS_L2CC_CACHE_ILCKDWN_4_WAY_OFFSET 0x0924U /* Cache Instruction Lockdown 4 by Way */
+#define XPS_L2CC_CACHE_DLCKDWN_5_WAY_OFFSET 0x0928U /* Cache Data Lockdown 5 by Way */
+#define XPS_L2CC_CACHE_ILCKDWN_5_WAY_OFFSET 0x092CU /* Cache Instruction Lockdown 5 by Way */
+#define XPS_L2CC_CACHE_DLCKDWN_6_WAY_OFFSET 0x0930U /* Cache Data Lockdown 6 by Way */
+#define XPS_L2CC_CACHE_ILCKDWN_6_WAY_OFFSET 0x0934U /* Cache Instruction Lockdown 6 by Way */
+#define XPS_L2CC_CACHE_DLCKDWN_7_WAY_OFFSET 0x0938U /* Cache Data Lockdown 7 by Way */
+#define XPS_L2CC_CACHE_ILCKDWN_7_WAY_OFFSET 0x093CU /* Cache Instruction Lockdown 7 by Way */
+
+#define XPS_L2CC_CACHE_LCKDWN_LINE_ENABLE_OFFSET 0x0950U /* Cache Lockdown Line Enable */
+#define XPS_L2CC_CACHE_UUNLOCK_ALL_WAY_OFFSET 0x0954U /* Cache Unlock All Lines by Way */
+
+#define XPS_L2CC_ADDR_FILTER_START_OFFSET 0x0C00U /* Start of address filtering */
+#define XPS_L2CC_ADDR_FILTER_END_OFFSET 0x0C04U /* Start of address filtering */
+
+#define XPS_L2CC_DEBUG_CTRL_OFFSET 0x0F40U /* Debug Control Register */
+
+/* XPS_L2CC_CNTRL_OFFSET bit masks */
+#define XPS_L2CC_ENABLE_MASK 0x00000001U /* enables the L2CC */
+
+/* XPS_L2CC_AUX_CNTRL_OFFSET bit masks */
+#define XPS_L2CC_AUX_EBRESPE_MASK 0x40000000U /* Early BRESP Enable */
+#define XPS_L2CC_AUX_IPFE_MASK 0x20000000U /* Instruction Prefetch Enable */
+#define XPS_L2CC_AUX_DPFE_MASK 0x10000000U /* Data Prefetch Enable */
+#define XPS_L2CC_AUX_NSIC_MASK 0x08000000U /* Non-secure interrupt access control */
+#define XPS_L2CC_AUX_NSLE_MASK 0x04000000U /* Non-secure lockdown enable */
+#define XPS_L2CC_AUX_CRP_MASK 0x02000000U /* Cache replacement policy */
+#define XPS_L2CC_AUX_FWE_MASK 0x01800000U /* Force write allocate */
+#define XPS_L2CC_AUX_SAOE_MASK 0x00400000U /* Shared attribute override enable */
+#define XPS_L2CC_AUX_PE_MASK 0x00200000U /* Parity enable */
+#define XPS_L2CC_AUX_EMBE_MASK 0x00100000U /* Event monitor bus enable */
+#define XPS_L2CC_AUX_WAY_SIZE_MASK 0x000E0000U /* Way-size */
+#define XPS_L2CC_AUX_ASSOC_MASK 0x00010000U /* Associativity */
+#define XPS_L2CC_AUX_SAIE_MASK 0x00002000U /* Shared attribute invalidate enable */
+#define XPS_L2CC_AUX_EXCL_CACHE_MASK 0x00001000U /* Exclusive cache configuration */
+#define XPS_L2CC_AUX_SBDLE_MASK 0x00000800U /* Store buffer device limitation Enable */
+#define XPS_L2CC_AUX_HPSODRE_MASK 0x00000400U /* High Priority for SO and Dev Reads Enable */
+#define XPS_L2CC_AUX_FLZE_MASK 0x00000001U /* Full line of zero enable */
+
+#define XPS_L2CC_AUX_REG_DEFAULT_MASK 0x72360000U /* Enable all prefetching, */
+ /* Cache replacement policy, Parity enable, */
+ /* Event monitor bus enable and Way Size (64 KB) */
+#define XPS_L2CC_AUX_REG_ZERO_MASK 0xFFF1FFFFU /* */
+
+#define XPS_L2CC_TAG_RAM_DEFAULT_MASK 0x00000111U /* latency for TAG RAM */
+#define XPS_L2CC_DATA_RAM_DEFAULT_MASK 0x00000121U /* latency for DATA RAM */
+
+/* Interrupt bit masks */
+#define XPS_L2CC_IXR_DECERR_MASK 0x00000100U /* DECERR from L3 */
+#define XPS_L2CC_IXR_SLVERR_MASK 0x00000080U /* SLVERR from L3 */
+#define XPS_L2CC_IXR_ERRRD_MASK 0x00000040U /* Error on L2 data RAM (Read) */
+#define XPS_L2CC_IXR_ERRRT_MASK 0x00000020U /* Error on L2 tag RAM (Read) */
+#define XPS_L2CC_IXR_ERRWD_MASK 0x00000010U /* Error on L2 data RAM (Write) */
+#define XPS_L2CC_IXR_ERRWT_MASK 0x00000008U /* Error on L2 tag RAM (Write) */
+#define XPS_L2CC_IXR_PARRD_MASK 0x00000004U /* Parity Error on L2 data RAM (Read) */
+#define XPS_L2CC_IXR_PARRT_MASK 0x00000002U /* Parity Error on L2 tag RAM (Read) */
+#define XPS_L2CC_IXR_ECNTR_MASK 0x00000001U /* Event Counter1/0 Overflow Increment */
+
+/* Address filtering mask and enable bit */
+#define XPS_L2CC_ADDR_FILTER_VALID_MASK 0xFFF00000U /* Address filtering valid bits*/
+#define XPS_L2CC_ADDR_FILTER_ENABLE_MASK 0x00000001U /* Address filtering enable bit*/
+
+/* Debug control bits */
+#define XPS_L2CC_DEBUG_SPIDEN_MASK 0x00000004U /* Debug SPIDEN bit */
+#define XPS_L2CC_DEBUG_DWB_MASK 0x00000002U /* Debug DWB bit, forces write through */
+#define XPS_L2CC_DEBUG_DCL_MASK 0x00000002U /* Debug DCL bit, disables cache line fill */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* protection macro */
diff --git a/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v7_1/src/xl2cc_counter.c b/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v7_1/src/xl2cc_counter.c
new file mode 100644
index 0000000..99bff66
--- /dev/null
+++ b/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v7_1/src/xl2cc_counter.c
@@ -0,0 +1,163 @@
+/******************************************************************************
+*
+* Copyright (C) 2011 - 2015 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+* THE SOFTWARE.
+*
+*
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xl2cc_counter.c
+*
+* This file contains APIs for configuring and controlling the event counters
+* in PL310 L2 cache controller. For more information about the event counters,
+* see xl2cc_counter.h.
+*
+* <pre>
+* MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ----- ---- -------- -----------------------------------------------
+* 1.00a sdm 07/11/11 First release
+* 3.07a asa 08/30/12 Updated for CR 675636 to provide the L2 Base Address
+* inside the APIs
+* </pre>
+*
+******************************************************************************/
+
+/***************************** Include Files *********************************/
+
+#include <stdint.h>
+#include "xparameters_ps.h"
+#include "xl2cc_counter.h"
+#include "xl2cc.h"
+
+/************************** Constant Definitions ****************************/
+
+/**************************** Type Definitions ******************************/
+
+/***************** Macros (Inline Functions) Definitions ********************/
+
+/************************** Variable Definitions *****************************/
+
+/************************** Function Prototypes ******************************/
+
+void XL2cc_EventCtrReset(void);
+
+/******************************************************************************/
+
+/****************************************************************************/
+/**
+*
+* @brief This function initializes the event counters in L2 Cache controller
+* with a set of event codes specified by the user.
+*
+* @param Event0: Event code for counter 0.
+* @param Event1: Event code for counter 1.
+*
+* @return None.
+*
+* @note The definitions for event codes XL2CC_* can be found in
+* xl2cc_counter.h.
+*
+*****************************************************************************/
+void XL2cc_EventCtrInit(s32 Event0, s32 Event1)
+{
+
+ /* Write event code into cnt1 cfg reg */
+ *((volatile u32*)(XPS_L2CC_BASEADDR + XPS_L2CC_EVNT_CNT1_CTRL_OFFSET)) = (((u32)Event1) << 2);
+
+ /* Write event code into cnt0 cfg reg */
+ *((volatile u32*)(XPS_L2CC_BASEADDR + XPS_L2CC_EVNT_CNT0_CTRL_OFFSET)) = (((u32)Event0) << 2);
+
+ /* Reset counters */
+ XL2cc_EventCtrReset();
+}
+
+
+/****************************************************************************/
+/**
+*
+* @brief This function starts the event counters in L2 Cache controller.
+*
+* @param None.
+*
+* @return None.
+*
+* @note None.
+*
+*****************************************************************************/
+void XL2cc_EventCtrStart(void)
+{
+ u32 *LocalPtr;
+ LocalPtr = (u32 *)(XPS_L2CC_BASEADDR + XPS_L2CC_EVNT_CNTRL_OFFSET);
+ XL2cc_EventCtrReset();
+
+ /* Enable counter */
+ /* *((volatile u32*)((void *)(XPS_L2CC_BASEADDR + XPS_L2CC_EVNT_CNTRL_OFFSET))) = 1 */
+ *LocalPtr = (u32)1;
+}
+
+/****************************************************************************/
+/**
+*
+* @brief This function disables the event counters in L2 Cache controller,
+* saves the counter values and resets the counters.
+*
+* @param EveCtr0: Output parameter which is used to return the value
+* in event counter 0.
+* EveCtr1: Output parameter which is used to return the value
+* in event counter 1.
+*
+* @return None.
+*
+* @note None.
+*
+*****************************************************************************/
+void XL2cc_EventCtrStop(u32 *EveCtr0, u32 *EveCtr1)
+{
+ /* Disable counter */
+ *((volatile u32*) (XPS_L2CC_BASEADDR + XPS_L2CC_EVNT_CNTRL_OFFSET)) = 0U;
+
+ /* Save counter values */
+ *EveCtr1 = *((volatile u32*)(XPS_L2CC_BASEADDR + XPS_L2CC_EVNT_CNT1_VAL_OFFSET));
+ *EveCtr0 = *((volatile u32*)(XPS_L2CC_BASEADDR + XPS_L2CC_EVNT_CNT0_VAL_OFFSET));
+
+ XL2cc_EventCtrReset();
+}
+
+/****************************************************************************/
+/**
+*
+* @brief This function resets the event counters in L2 Cache controller.
+*
+* @param None.
+*
+* @return None.
+*
+* @note None.
+*
+*****************************************************************************/
+void XL2cc_EventCtrReset(void)
+{
+ *((volatile u32*)(XPS_L2CC_BASEADDR + XPS_L2CC_EVNT_CNTRL_OFFSET)) = 0x6U;
+}
diff --git a/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v7_1/src/xl2cc_counter.h b/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v7_1/src/xl2cc_counter.h
new file mode 100644
index 0000000..0810d31
--- /dev/null
+++ b/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v7_1/src/xl2cc_counter.h
@@ -0,0 +1,108 @@
+/******************************************************************************
+*
+* Copyright (C) 2011 - 2018 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+* THE SOFTWARE.
+*
+*
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xl2cc_counter.h
+*
+* @addtogroup l2_event_counter_apis PL310 L2 Event Counters Functions
+*
+* xl2cc_counter.h contains APIs for configuring and controlling the event
+* counters in PL310 L2 cache controller.
+* PL310 has two event counters which can be used to count variety of events
+* like DRHIT, DRREQ, DWHIT, DWREQ, etc. xl2cc_counter.h contains definitions
+* for different configurations which can be used for the event counters to
+* count a set of events.
+*
+*
+* @{
+*
+* <pre>
+* MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ----- ---- -------- -----------------------------------------------
+* 1.00a sdm 07/11/11 First release
+* 3.07a asa 08/30/12 Updated for CR 675636 to provide the L2 Base Address
+* inside the APIs
+* 6.8 aru 09/06/18 Removed compilation warnings for ARMCC toolchain.
+* </pre>
+*
+******************************************************************************/
+
+#ifndef L2CCCOUNTER_H /* prevent circular inclusions */
+#define L2CCCOUNTER_H /* by using protection macros */
+
+/***************************** Include Files ********************************/
+
+#include "xpseudo_asm.h"
+#include "xil_types.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif /* __cplusplus */
+
+/************************** Constant Definitions ****************************/
+
+/*
+ * The following constants define the event codes for the event counters.
+ */
+#define XL2CC_CO 0x1
+#define XL2CC_DRHIT 0x2
+#define XL2CC_DRREQ 0x3
+#define XL2CC_DWHIT 0x4
+#define XL2CC_DWREQ 0x5
+#define XL2CC_DWTREQ 0x6
+#define XL2CC_IRHIT 0x7
+#define XL2CC_IRREQ 0x8
+#define XL2CC_WA 0x9
+#define XL2CC_IPFALLOC 0xa
+#define XL2CC_EPFHIT 0xb
+#define XL2CC_EPFALLOC 0xc
+#define XL2CC_SRRCVD 0xd
+#define XL2CC_SRCONF 0xe
+#define XL2CC_EPFRCVD 0xf
+
+/**************************** Type Definitions ******************************/
+
+/***************** Macros (Inline Functions) Definitions ********************/
+
+/************************** Variable Definitions ****************************/
+
+/************************** Function Prototypes *****************************/
+
+void XL2cc_EventCtrInit(s32 Event0, s32 Event1);
+void XL2cc_EventCtrStart(void);
+void XL2cc_EventCtrStop(u32 *EveCtr0, u32 *EveCtr1);
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+
+#endif /* L2CCCOUNTER_H */
+/**
+* @} End of "addtogroup l2_event_counter_apis".
+*/
diff --git a/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v7_1/src/xparameters_ps.h b/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v7_1/src/xparameters_ps.h
new file mode 100644
index 0000000..4d35859
--- /dev/null
+++ b/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v7_1/src/xparameters_ps.h
@@ -0,0 +1,332 @@
+/******************************************************************************
+*
+* Copyright (C) 2010 - 2017 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+* THE SOFTWARE.
+*
+*
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+* @file xparameters_ps.h
+*
+* This file contains the address definitions for the hard peripherals
+* attached to the ARM Cortex A9 core.
+*
+* <pre>
+* MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ----- ------- -------- ---------------------------------------------------
+* 1.00a ecm/sdm 02/01/10 Initial version
+* 3.04a sdm 02/02/12 Removed some of the defines as they are being generated through
+* driver tcl
+* 5.0 pkp 01/16/15 Added interrupt ID definition of ttc for TEST APP
+* 6.6 srm 10/18/17 Added ARMA9 macro to identify CortexA9
+*
+* </pre>
+*
+* @note
+*
+* None.
+*
+******************************************************************************/
+
+#ifndef _XPARAMETERS_PS_H_
+#define _XPARAMETERS_PS_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**************************** Include Files *******************************/
+
+
+/************************** Constant Definitions *****************************/
+
+/*
+ * This block contains constant declarations for the peripherals
+ * within the hardblock
+ */
+
+/* Canonical definitions for DDR MEMORY */
+#define XPAR_DDR_MEM_BASEADDR 0x00000000U
+#define XPAR_DDR_MEM_HIGHADDR 0x3FFFFFFFU
+
+/* Canonical definitions for Interrupts */
+#define XPAR_XUARTPS_0_INTR XPS_UART0_INT_ID
+#define XPAR_XUARTPS_1_INTR XPS_UART1_INT_ID
+#define XPAR_XUSBPS_0_INTR XPS_USB0_INT_ID
+#define XPAR_XUSBPS_1_INTR XPS_USB1_INT_ID
+#define XPAR_XIICPS_0_INTR XPS_I2C0_INT_ID
+#define XPAR_XIICPS_1_INTR XPS_I2C1_INT_ID
+#define XPAR_XSPIPS_0_INTR XPS_SPI0_INT_ID
+#define XPAR_XSPIPS_1_INTR XPS_SPI1_INT_ID
+#define XPAR_XCANPS_0_INTR XPS_CAN0_INT_ID
+#define XPAR_XCANPS_1_INTR XPS_CAN1_INT_ID
+#define XPAR_XGPIOPS_0_INTR XPS_GPIO_INT_ID
+#define XPAR_XEMACPS_0_INTR XPS_GEM0_INT_ID
+#define XPAR_XEMACPS_0_WAKE_INTR XPS_GEM0_WAKE_INT_ID
+#define XPAR_XEMACPS_1_INTR XPS_GEM1_INT_ID
+#define XPAR_XEMACPS_1_WAKE_INTR XPS_GEM1_WAKE_INT_ID
+#define XPAR_XSDIOPS_0_INTR XPS_SDIO0_INT_ID
+#define XPAR_XQSPIPS_0_INTR XPS_QSPI_INT_ID
+#define XPAR_XSDIOPS_1_INTR XPS_SDIO1_INT_ID
+#define XPAR_XWDTPS_0_INTR XPS_WDT_INT_ID
+#define XPAR_XDCFG_0_INTR XPS_DVC_INT_ID
+#define XPAR_SCUTIMER_INTR XPS_SCU_TMR_INT_ID
+#define XPAR_SCUWDT_INTR XPS_SCU_WDT_INT_ID
+#define XPAR_XTTCPS_0_INTR XPS_TTC0_0_INT_ID
+#define XPAR_XTTCPS_1_INTR XPS_TTC0_1_INT_ID
+#define XPAR_XTTCPS_2_INTR XPS_TTC0_2_INT_ID
+#define XPAR_XTTCPS_3_INTR XPS_TTC1_0_INT_ID
+#define XPAR_XTTCPS_4_INTR XPS_TTC1_1_INT_ID
+#define XPAR_XTTCPS_5_INTR XPS_TTC1_2_INT_ID
+#define XPAR_XDMAPS_0_FAULT_INTR XPS_DMA0_ABORT_INT_ID
+#define XPAR_XDMAPS_0_DONE_INTR_0 XPS_DMA0_INT_ID
+#define XPAR_XDMAPS_0_DONE_INTR_1 XPS_DMA1_INT_ID
+#define XPAR_XDMAPS_0_DONE_INTR_2 XPS_DMA2_INT_ID
+#define XPAR_XDMAPS_0_DONE_INTR_3 XPS_DMA3_INT_ID
+#define XPAR_XDMAPS_0_DONE_INTR_4 XPS_DMA4_INT_ID
+#define XPAR_XDMAPS_0_DONE_INTR_5 XPS_DMA5_INT_ID
+#define XPAR_XDMAPS_0_DONE_INTR_6 XPS_DMA6_INT_ID
+#define XPAR_XDMAPS_0_DONE_INTR_7 XPS_DMA7_INT_ID
+
+
+#define XPAR_XQSPIPS_0_LINEAR_BASEADDR XPS_QSPI_LINEAR_BASEADDR
+#define XPAR_XPARPORTPS_CTRL_BASEADDR XPS_PARPORT_CRTL_BASEADDR
+
+
+
+/* Canonical definitions for DMAC */
+
+
+/* Canonical definitions for WDT */
+
+/* Canonical definitions for SLCR */
+#define XPAR_XSLCR_NUM_INSTANCES 1U
+#define XPAR_XSLCR_0_DEVICE_ID 0U
+#define XPAR_XSLCR_0_BASEADDR XPS_SYS_CTRL_BASEADDR
+
+/* Canonical definitions for SCU GIC */
+#define XPAR_SCUGIC_NUM_INSTANCES 1U
+#define XPAR_SCUGIC_SINGLE_DEVICE_ID 0U
+#define XPAR_SCUGIC_CPU_BASEADDR (XPS_SCU_PERIPH_BASE + 0x00000100U)
+#define XPAR_SCUGIC_DIST_BASEADDR (XPS_SCU_PERIPH_BASE + 0x00001000U)
+#define XPAR_SCUGIC_ACK_BEFORE 0U
+
+/* Canonical definitions for Global Timer */
+#define XPAR_GLOBAL_TMR_NUM_INSTANCES 1U
+#define XPAR_GLOBAL_TMR_DEVICE_ID 0U
+#define XPAR_GLOBAL_TMR_BASEADDR (XPS_SCU_PERIPH_BASE + 0x00000200U)
+#define XPAR_GLOBAL_TMR_INTR XPS_GLOBAL_TMR_INT_ID
+
+
+/* Xilinx Parallel Flash Library (XilFlash) User Settings */
+#define XPAR_AXI_EMC
+
+
+#define XPAR_CPU_CORTEXA9_CORE_CLOCK_FREQ_HZ XPAR_CPU_CORTEXA9_0_CPU_CLK_FREQ_HZ
+
+
+/*
+ * This block contains constant declarations for the peripherals
+ * within the hardblock. These have been put for bacwards compatibility
+ */
+
+#define XPS_PERIPHERAL_BASEADDR 0xE0000000U
+#define XPS_UART0_BASEADDR 0xE0000000U
+#define XPS_UART1_BASEADDR 0xE0001000U
+#define XPS_USB0_BASEADDR 0xE0002000U
+#define XPS_USB1_BASEADDR 0xE0003000U
+#define XPS_I2C0_BASEADDR 0xE0004000U
+#define XPS_I2C1_BASEADDR 0xE0005000U
+#define XPS_SPI0_BASEADDR 0xE0006000U
+#define XPS_SPI1_BASEADDR 0xE0007000U
+#define XPS_CAN0_BASEADDR 0xE0008000U
+#define XPS_CAN1_BASEADDR 0xE0009000U
+#define XPS_GPIO_BASEADDR 0xE000A000U
+#define XPS_GEM0_BASEADDR 0xE000B000U
+#define XPS_GEM1_BASEADDR 0xE000C000U
+#define XPS_QSPI_BASEADDR 0xE000D000U
+#define XPS_PARPORT_CRTL_BASEADDR 0xE000E000U
+#define XPS_SDIO0_BASEADDR 0xE0100000U
+#define XPS_SDIO1_BASEADDR 0xE0101000U
+#define XPS_IOU_BUS_CFG_BASEADDR 0xE0200000U
+#define XPS_NAND_BASEADDR 0xE1000000U
+#define XPS_PARPORT0_BASEADDR 0xE2000000U
+#define XPS_PARPORT1_BASEADDR 0xE4000000U
+#define XPS_QSPI_LINEAR_BASEADDR 0xFC000000U
+#define XPS_SYS_CTRL_BASEADDR 0xF8000000U /* AKA SLCR */
+#define XPS_TTC0_BASEADDR 0xF8001000U
+#define XPS_TTC1_BASEADDR 0xF8002000U
+#define XPS_DMAC0_SEC_BASEADDR 0xF8003000U
+#define XPS_DMAC0_NON_SEC_BASEADDR 0xF8004000U
+#define XPS_WDT_BASEADDR 0xF8005000U
+#define XPS_DDR_CTRL_BASEADDR 0xF8006000U
+#define XPS_DEV_CFG_APB_BASEADDR 0xF8007000U
+#define XPS_AFI0_BASEADDR 0xF8008000U
+#define XPS_AFI1_BASEADDR 0xF8009000U
+#define XPS_AFI2_BASEADDR 0xF800A000U
+#define XPS_AFI3_BASEADDR 0xF800B000U
+#define XPS_OCM_BASEADDR 0xF800C000U
+#define XPS_EFUSE_BASEADDR 0xF800D000U
+#define XPS_CORESIGHT_BASEADDR 0xF8800000U
+#define XPS_TOP_BUS_CFG_BASEADDR 0xF8900000U
+#define XPS_SCU_PERIPH_BASE 0xF8F00000U
+#define XPS_L2CC_BASEADDR 0xF8F02000U
+#define XPS_SAM_RAM_BASEADDR 0xFFFC0000U
+#define XPS_FPGA_AXI_S0_BASEADDR 0x40000000U
+#define XPS_FPGA_AXI_S1_BASEADDR 0x80000000U
+#define XPS_IOU_S_SWITCH_BASEADDR 0xE0000000U
+#define XPS_PERIPH_APB_BASEADDR 0xF8000000U
+
+/* Shared Peripheral Interrupts (SPI) */
+#define XPS_CORE_PARITY0_INT_ID 32U
+#define XPS_CORE_PARITY1_INT_ID 33U
+#define XPS_L2CC_INT_ID 34U
+#define XPS_OCMINTR_INT_ID 35U
+#define XPS_ECC_INT_ID 36U
+#define XPS_PMU0_INT_ID 37U
+#define XPS_PMU1_INT_ID 38U
+#define XPS_SYSMON_INT_ID 39U
+#define XPS_DVC_INT_ID 40U
+#define XPS_WDT_INT_ID 41U
+#define XPS_TTC0_0_INT_ID 42U
+#define XPS_TTC0_1_INT_ID 43U
+#define XPS_TTC0_2_INT_ID 44U
+#define XPS_DMA0_ABORT_INT_ID 45U
+#define XPS_DMA0_INT_ID 46U
+#define XPS_DMA1_INT_ID 47U
+#define XPS_DMA2_INT_ID 48U
+#define XPS_DMA3_INT_ID 49U
+#define XPS_SMC_INT_ID 50U
+#define XPS_QSPI_INT_ID 51U
+#define XPS_GPIO_INT_ID 52U
+#define XPS_USB0_INT_ID 53U
+#define XPS_GEM0_INT_ID 54U
+#define XPS_GEM0_WAKE_INT_ID 55U
+#define XPS_SDIO0_INT_ID 56U
+#define XPS_I2C0_INT_ID 57U
+#define XPS_SPI0_INT_ID 58U
+#define XPS_UART0_INT_ID 59U
+#define XPS_CAN0_INT_ID 60U
+#define XPS_FPGA0_INT_ID 61U
+#define XPS_FPGA1_INT_ID 62U
+#define XPS_FPGA2_INT_ID 63U
+#define XPS_FPGA3_INT_ID 64U
+#define XPS_FPGA4_INT_ID 65U
+#define XPS_FPGA5_INT_ID 66U
+#define XPS_FPGA6_INT_ID 67U
+#define XPS_FPGA7_INT_ID 68U
+#define XPS_TTC1_0_INT_ID 69U
+#define XPS_TTC1_1_INT_ID 70U
+#define XPS_TTC1_2_INT_ID 71U
+#define XPS_DMA4_INT_ID 72U
+#define XPS_DMA5_INT_ID 73U
+#define XPS_DMA6_INT_ID 74U
+#define XPS_DMA7_INT_ID 75U
+#define XPS_USB1_INT_ID 76U
+#define XPS_GEM1_INT_ID 77U
+#define XPS_GEM1_WAKE_INT_ID 78U
+#define XPS_SDIO1_INT_ID 79U
+#define XPS_I2C1_INT_ID 80U
+#define XPS_SPI1_INT_ID 81U
+#define XPS_UART1_INT_ID 82U
+#define XPS_CAN1_INT_ID 83U
+#define XPS_FPGA8_INT_ID 84U
+#define XPS_FPGA9_INT_ID 85U
+#define XPS_FPGA10_INT_ID 86U
+#define XPS_FPGA11_INT_ID 87U
+#define XPS_FPGA12_INT_ID 88U
+#define XPS_FPGA13_INT_ID 89U
+#define XPS_FPGA14_INT_ID 90U
+#define XPS_FPGA15_INT_ID 91U
+
+/* Private Peripheral Interrupts (PPI) */
+#define XPS_GLOBAL_TMR_INT_ID 27U /* SCU Global Timer interrupt */
+#define XPS_FIQ_INT_ID 28U /* FIQ from FPGA fabric */
+#define XPS_SCU_TMR_INT_ID 29U /* SCU Private Timer interrupt */
+#define XPS_SCU_WDT_INT_ID 30U /* SCU Private WDT interrupt */
+#define XPS_IRQ_INT_ID 31U /* IRQ from FPGA fabric */
+
+
+/* REDEFINES for TEST APP */
+/* Definitions for UART */
+#define XPAR_PS7_UART_0_INTR XPS_UART0_INT_ID
+#define XPAR_PS7_UART_1_INTR XPS_UART1_INT_ID
+#define XPAR_PS7_USB_0_INTR XPS_USB0_INT_ID
+#define XPAR_PS7_USB_1_INTR XPS_USB1_INT_ID
+#define XPAR_PS7_I2C_0_INTR XPS_I2C0_INT_ID
+#define XPAR_PS7_I2C_1_INTR XPS_I2C1_INT_ID
+#define XPAR_PS7_SPI_0_INTR XPS_SPI0_INT_ID
+#define XPAR_PS7_SPI_1_INTR XPS_SPI1_INT_ID
+#define XPAR_PS7_CAN_0_INTR XPS_CAN0_INT_ID
+#define XPAR_PS7_CAN_1_INTR XPS_CAN1_INT_ID
+#define XPAR_PS7_GPIO_0_INTR XPS_GPIO_INT_ID
+#define XPAR_PS7_ETHERNET_0_INTR XPS_GEM0_INT_ID
+#define XPAR_PS7_ETHERNET_0_WAKE_INTR XPS_GEM0_WAKE_INT_ID
+#define XPAR_PS7_ETHERNET_1_INTR XPS_GEM1_INT_ID
+#define XPAR_PS7_ETHERNET_1_WAKE_INTR XPS_GEM1_WAKE_INT_ID
+#define XPAR_PS7_QSPI_0_INTR XPS_QSPI_INT_ID
+#define XPAR_PS7_WDT_0_INTR XPS_WDT_INT_ID
+#define XPAR_PS7_SCUWDT_0_INTR XPS_SCU_WDT_INT_ID
+#define XPAR_PS7_SCUTIMER_0_INTR XPS_SCU_TMR_INT_ID
+#define XPAR_PS7_XADC_0_INTR XPS_SYSMON_INT_ID
+#define XPAR_PS7_TTC_0_INTR XPS_TTC0_0_INT_ID
+#define XPAR_PS7_TTC_1_INTR XPS_TTC0_1_INT_ID
+#define XPAR_PS7_TTC_2_INTR XPS_TTC0_2_INT_ID
+#define XPAR_PS7_TTC_3_INTR XPS_TTC1_0_INT_ID
+#define XPAR_PS7_TTC_4_INTR XPS_TTC1_1_INT_ID
+#define XPAR_PS7_TTC_5_INTR XPS_TTC1_2_INT_ID
+
+#define XPAR_XADCPS_INT_ID XPS_SYSMON_INT_ID
+
+/* For backwards compatibility */
+#define XPAR_XUARTPS_0_CLOCK_HZ XPAR_XUARTPS_0_UART_CLK_FREQ_HZ
+#define XPAR_XUARTPS_1_CLOCK_HZ XPAR_XUARTPS_1_UART_CLK_FREQ_HZ
+#define XPAR_XTTCPS_0_CLOCK_HZ XPAR_XTTCPS_0_TTC_CLK_FREQ_HZ
+#define XPAR_XTTCPS_1_CLOCK_HZ XPAR_XTTCPS_1_TTC_CLK_FREQ_HZ
+#define XPAR_XTTCPS_2_CLOCK_HZ XPAR_XTTCPS_2_TTC_CLK_FREQ_HZ
+#define XPAR_XTTCPS_3_CLOCK_HZ XPAR_XTTCPS_3_TTC_CLK_FREQ_HZ
+#define XPAR_XTTCPS_4_CLOCK_HZ XPAR_XTTCPS_4_TTC_CLK_FREQ_HZ
+#define XPAR_XTTCPS_5_CLOCK_HZ XPAR_XTTCPS_5_TTC_CLK_FREQ_HZ
+#define XPAR_XIICPS_0_CLOCK_HZ XPAR_XIICPS_0_I2C_CLK_FREQ_HZ
+#define XPAR_XIICPS_1_CLOCK_HZ XPAR_XIICPS_1_I2C_CLK_FREQ_HZ
+
+#define XPAR_XQSPIPS_0_CLOCK_HZ XPAR_XQSPIPS_0_QSPI_CLK_FREQ_HZ
+
+#ifdef XPAR_CPU_CORTEXA9_0_CPU_CLK_FREQ_HZ
+#define XPAR_CPU_CORTEXA9_CORE_CLOCK_FREQ_HZ XPAR_CPU_CORTEXA9_0_CPU_CLK_FREQ_HZ
+#endif
+
+#ifdef XPAR_CPU_CORTEXA9_1_CPU_CLK_FREQ_HZ
+#define XPAR_CPU_CORTEXA9_CORE_CLOCK_FREQ_HZ XPAR_CPU_CORTEXA9_1_CPU_CLK_FREQ_HZ
+#endif
+
+#define XPAR_SCUTIMER_DEVICE_ID 0U
+#define XPAR_SCUWDT_DEVICE_ID 0U
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* protection macro */
diff --git a/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v7_1/src/xplatform_info.c b/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v7_1/src/xplatform_info.c
new file mode 100644
index 0000000..37dc8f4
--- /dev/null
+++ b/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v7_1/src/xplatform_info.c
@@ -0,0 +1,160 @@
+/******************************************************************************
+*
+* Copyright (C) 2014 - 2015 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+* THE SOFTWARE.
+*
+*
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xplatform_info.c
+*
+* This file contains information about hardware for which the code is built
+*
+* <pre>
+* MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ----- ---- -------- -------------------------------------------------------
+* 5.00 pkp 12/15/14 Initial release
+* 5.04 pkp 01/12/16 Added platform information support for Cortex-A53 32bit
+* mode
+* 6.00 mus 17/08/16 Removed unused variable from XGetPlatform_Info
+* 6.4 ms 05/23/17 Added PSU_PMU macro to support XGetPSVersion_Info
+* function for PMUFW.
+* ms 06/13/17 Added PSU_PMU macro to provide support of
+* XGetPlatform_Info function for PMUFW.
+* mus 08/17/17 Add EL1 NS mode support for
+* XGet_Zynq_UltraMp_Platform_info and XGetPSVersion_Info
+* APIs.
+* 7.0 aru 03/15/19 Check for versal before aarch64 and armr5
+* in XGetPlatform_Info()
+* </pre>
+*
+******************************************************************************/
+
+/***************************** Include Files *********************************/
+
+#include "xil_types.h"
+#include "xil_io.h"
+#include "xplatform_info.h"
+#if defined (__aarch64__)
+#include "bspconfig.h"
+#include "xil_smc.h"
+#endif
+/************************** Constant Definitions *****************************/
+
+/**************************** Type Definitions *******************************/
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/************************** Variable Definitions *****************************/
+
+
+/************************** Function Prototypes ******************************/
+
+/*****************************************************************************/
+/**
+*
+* @brief This API is used to provide information about platform
+*
+* @param None.
+*
+* @return The information about platform defined in xplatform_info.h
+*
+******************************************************************************/
+u32 XGetPlatform_Info()
+{
+#if defined (versal)
+ return XPLAT_VERSAL;
+#elif defined (ARMR5) || (__aarch64__) || (ARMA53_32) || (PSU_PMU)
+ return XPLAT_ZYNQ_ULTRA_MP;
+#elif (__microblaze__)
+ return XPLAT_MICROBLAZE;
+#else
+ return XPLAT_ZYNQ;
+#endif
+}
+
+/*****************************************************************************/
+/**
+*
+* @brief This API is used to provide information about zynq ultrascale MP platform
+*
+* @param None.
+*
+* @return The information about zynq ultrascale MP platform defined in
+* xplatform_info.h
+*
+******************************************************************************/
+#if defined (ARMR5) || (__aarch64__) || (ARMA53_32)
+u32 XGet_Zynq_UltraMp_Platform_info()
+{
+#if EL1_NONSECURE
+ XSmc_OutVar reg;
+ /*
+ * This SMC call will return,
+ * idcode - upper 32 bits of reg.Arg0
+ * version - lower 32 bits of reg.Arg1
+ */
+ reg = Xil_Smc(GET_CHIPID_SMC_FID,0,0, 0, 0, 0, 0, 0);
+ return (u32)((reg.Arg1 >> XPLAT_INFO_SHIFT) & XPLAT_INFO_MASK);
+#else
+ u32 reg;
+ reg = ((Xil_In32(XPLAT_PS_VERSION_ADDRESS) >> XPLAT_INFO_SHIFT )
+ & XPLAT_INFO_MASK);
+ return reg;
+#endif
+}
+#endif
+
+/*****************************************************************************/
+/**
+*
+* @brief This API is used to provide information about PS Silicon version
+*
+* @param None.
+*
+* @return The information about PS Silicon version.
+*
+******************************************************************************/
+#if defined (ARMR5) || (__aarch64__) || (ARMA53_32) || (PSU_PMU)
+u32 XGetPSVersion_Info()
+{
+#if EL1_NONSECURE
+ /*
+ * This SMC call will return,
+ * idcode - upper 32 bits of reg.Arg0
+ * version - lower 32 bits of reg.Arg1
+ */
+ XSmc_OutVar reg;
+ reg = Xil_Smc(GET_CHIPID_SMC_FID,0,0, 0, 0, 0, 0, 0);
+ return (u32)((reg.Arg1 & XPS_VERSION_INFO_MASK) >>
+ XPS_VERSION_INFO_SHIFT);
+#else
+ u32 reg;
+ reg = (Xil_In32(XPLAT_PS_VERSION_ADDRESS)
+ & XPS_VERSION_INFO_MASK);
+ return (reg >> XPS_VERSION_INFO_SHIFT);
+#endif
+}
+#endif
diff --git a/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v7_1/src/xplatform_info.h b/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v7_1/src/xplatform_info.h
new file mode 100644
index 0000000..a917354
--- /dev/null
+++ b/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v7_1/src/xplatform_info.h
@@ -0,0 +1,118 @@
+/******************************************************************************
+*
+* Copyright (C) 2014 - 2017 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+* THE SOFTWARE.
+*
+*
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xplatform_info.h
+*
+* @addtogroup common_platform_info APIs to Get Platform Information
+*
+* The xplatform_info.h file contains definitions for various available Xilinx®
+* platforms. Also, it contains prototype of APIs, which can be used to get the
+* platform information.
+*
+* @{
+* <pre>
+* MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ----- ---- --------- -------------------------------------------------------
+* 6.4 ms 05/23/17 Added PSU_PMU macro to support XGetPSVersion_Info
+* function for PMUFW.
+* </pre>
+*
+******************************************************************************/
+
+#ifndef XPLATFORM_INFO_H /* prevent circular inclusions */
+#define XPLATFORM_INFO_H /* by using protection macros */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/***************************** Include Files *********************************/
+
+#include "xil_types.h"
+
+/************************** Constant Definitions *****************************/
+#if defined (versal)
+#define XPAR_PMC_TAP_BASEADDR 0xF11A0000U
+#define XPAR_PMC_TAP_VERSION_OFFSET 0x00000004U
+#define XPLAT_PS_VERSION_ADDRESS (XPAR_PMC_TAP_BASEADDR + \
+ XPAR_PMC_TAP_VERSION_OFFSET)
+#else
+#define XPAR_CSU_BASEADDR 0xFFCA0000U
+#define XPAR_CSU_VER_OFFSET 0x00000044U
+#define XPLAT_PS_VERSION_ADDRESS (XPAR_CSU_BASEADDR + \
+ XPAR_CSU_VER_OFFSET)
+#endif
+#define XPLAT_ZYNQ_ULTRA_MP_SILICON 0x0
+#define XPLAT_ZYNQ_ULTRA_MP 0x1
+#define XPLAT_ZYNQ_ULTRA_MPVEL 0x2
+#define XPLAT_ZYNQ_ULTRA_MPQEMU 0x3
+#define XPLAT_ZYNQ 0x4
+#define XPLAT_MICROBLAZE 0x5
+#define XPLAT_VERSAL 0x6U
+
+#define XPS_VERSION_1 0x0
+#define XPS_VERSION_2 0x1
+#define XPLAT_INFO_MASK (0xF)
+
+#if defined (versal)
+#define XPS_VERSION_INFO_MASK 0xFF00U
+#define XPS_VERSION_INFO_SHIFT 0x8U
+#define XPLAT_INFO_SHIFT 0x18U
+#else
+#define XPS_VERSION_INFO_MASK (0xF)
+#define XPS_VERSION_INFO_SHIFT 0x0U
+#define XPLAT_INFO_SHIFT 0xCU
+#endif
+
+/**************************** Type Definitions *******************************/
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+
+u32 XGetPlatform_Info(void);
+
+#if defined (ARMR5) || (__aarch64__) || (ARMA53_32) || (PSU_PMU)
+u32 XGetPSVersion_Info();
+#endif
+
+#if defined (ARMR5) || (__aarch64__) || (ARMA53_32)
+u32 XGet_Zynq_UltraMp_Platform_info();
+#endif
+/************************** Function Prototypes ******************************/
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* end of protection macro */
+/**
+* @} End of "addtogroup common_platform_info".
+*/
diff --git a/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v7_1/src/xpm_counter.c b/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v7_1/src/xpm_counter.c
new file mode 100644
index 0000000..e26a35f
--- /dev/null
+++ b/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v7_1/src/xpm_counter.c
@@ -0,0 +1,291 @@
+/******************************************************************************
+*
+* Copyright (C) 2011 - 2015 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+* THE SOFTWARE.
+*
+*
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xpm_counter.c
+*
+* This file contains APIs for configuring and controlling the Cortex-A9
+* Performance Monitor Events. For more information about the event counters,
+* see xpm_counter.h.
+*
+* <pre>
+* MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ----- ---- -------- -----------------------------------------------
+* 1.00a sdm 07/11/11 First release
+* 4.2 pkp 07/21/14 Corrected reset value of event counter in function
+* Xpm_ResetEventCounters to fix CR#796275
+* </pre>
+*
+******************************************************************************/
+
+/***************************** Include Files *********************************/
+
+#include "xpm_counter.h"
+
+/************************** Constant Definitions ****************************/
+
+/**************************** Type Definitions ******************************/
+
+typedef const u32 PmcrEventCfg32[XPM_CTRCOUNT];
+
+/***************** Macros (Inline Functions) Definitions ********************/
+
+/************************** Variable Definitions *****************************/
+
+/************************** Function Prototypes ******************************/
+
+void Xpm_DisableEventCounters(void);
+void Xpm_EnableEventCounters (void);
+void Xpm_ResetEventCounters (void);
+
+/******************************************************************************/
+
+/****************************************************************************/
+/**
+*
+* @brief This function disables the Cortex A9 event counters.
+*
+* @param None.
+*
+* @return None.
+*
+* @note None.
+*
+*****************************************************************************/
+void Xpm_DisableEventCounters(void)
+{
+ /* Disable the event counters */
+ mtcp(XREG_CP15_COUNT_ENABLE_CLR, 0x3f);
+}
+
+/****************************************************************************/
+/**
+*
+* @brief This function enables the Cortex A9 event counters.
+*
+* @param None.
+*
+* @return None.
+*
+* @note None.
+*
+*****************************************************************************/
+void Xpm_EnableEventCounters(void)
+{
+ /* Enable the event counters */
+ mtcp(XREG_CP15_COUNT_ENABLE_SET, 0x3f);
+}
+
+/****************************************************************************/
+/**
+*
+* @brief This function resets the Cortex A9 event counters.
+*
+* @param None.
+*
+* @return None.
+*
+* @note None.
+*
+*****************************************************************************/
+void Xpm_ResetEventCounters(void)
+{
+ u32 Reg;
+#ifdef __GNUC__
+ Reg = mfcp(XREG_CP15_PERF_MONITOR_CTRL);
+#elif defined (__ICCARM__)
+ mfcp(XREG_CP15_PERF_MONITOR_CTRL, Reg);
+#else
+ { register u32 C15Reg __asm(XREG_CP15_PERF_MONITOR_CTRL);
+ Reg = C15Reg; }
+#endif
+ Reg |= (1U << 1U); /* reset event counters */
+ mtcp(XREG_CP15_PERF_MONITOR_CTRL, Reg);
+
+}
+
+/****************************************************************************/
+/**
+* @brief This function configures the Cortex A9 event counters controller,
+* with the event codes, in a configuration selected by the user and
+* enables the counters.
+*
+* @param PmcrCfg: Configuration value based on which the event counters
+* are configured. XPM_CNTRCFG* values defined in xpm_counter.h can
+* be utilized for setting configuration.
+*
+* @return None.
+*
+* @note None.
+*
+*****************************************************************************/
+void Xpm_SetEvents(s32 PmcrCfg)
+{
+ u32 Counter;
+ static PmcrEventCfg32 PmcrEvents[] = {
+ {
+ XPM_EVENT_SOFTINCR,
+ XPM_EVENT_INSRFETCH_CACHEREFILL,
+ XPM_EVENT_INSTRFECT_TLBREFILL,
+ XPM_EVENT_DATA_CACHEREFILL,
+ XPM_EVENT_DATA_CACHEACCESS,
+ XPM_EVENT_DATA_TLBREFILL
+ },
+ {
+ XPM_EVENT_DATA_READS,
+ XPM_EVENT_DATA_WRITE,
+ XPM_EVENT_EXCEPTION,
+ XPM_EVENT_EXCEPRETURN,
+ XPM_EVENT_CHANGECONTEXT,
+ XPM_EVENT_SW_CHANGEPC
+ },
+ {
+ XPM_EVENT_IMMEDBRANCH,
+ XPM_EVENT_UNALIGNEDACCESS,
+ XPM_EVENT_BRANCHMISS,
+ XPM_EVENT_CLOCKCYCLES,
+ XPM_EVENT_BRANCHPREDICT,
+ XPM_EVENT_JAVABYTECODE
+ },
+ {
+ XPM_EVENT_SWJAVABYTECODE,
+ XPM_EVENT_JAVABACKBRANCH,
+ XPM_EVENT_COHERLINEMISS,
+ XPM_EVENT_COHERLINEHIT,
+ XPM_EVENT_INSTRSTALL,
+ XPM_EVENT_DATASTALL
+ },
+ {
+ XPM_EVENT_MAINTLBSTALL,
+ XPM_EVENT_STREXPASS,
+ XPM_EVENT_STREXFAIL,
+ XPM_EVENT_DATAEVICT,
+ XPM_EVENT_NODISPATCH,
+ XPM_EVENT_ISSUEEMPTY
+ },
+ {
+ XPM_EVENT_INSTRRENAME,
+ XPM_EVENT_PREDICTFUNCRET,
+ XPM_EVENT_MAINEXEC,
+ XPM_EVENT_SECEXEC,
+ XPM_EVENT_LDRSTR,
+ XPM_EVENT_FLOATRENAME
+ },
+ {
+ XPM_EVENT_NEONRENAME,
+ XPM_EVENT_PLDSTALL,
+ XPM_EVENT_WRITESTALL,
+ XPM_EVENT_INSTRTLBSTALL,
+ XPM_EVENT_DATATLBSTALL,
+ XPM_EVENT_INSTR_uTLBSTALL
+ },
+ {
+ XPM_EVENT_DATA_uTLBSTALL,
+ XPM_EVENT_DMB_STALL,
+ XPM_EVENT_INT_CLKEN,
+ XPM_EVENT_DE_CLKEN,
+ XPM_EVENT_INSTRISB,
+ XPM_EVENT_INSTRDSB
+ },
+ {
+ XPM_EVENT_INSTRDMB,
+ XPM_EVENT_EXTINT,
+ XPM_EVENT_PLE_LRC,
+ XPM_EVENT_PLE_LRS,
+ XPM_EVENT_PLE_FLUSH,
+ XPM_EVENT_PLE_CMPL
+ },
+ {
+ XPM_EVENT_PLE_OVFL,
+ XPM_EVENT_PLE_PROG,
+ XPM_EVENT_PLE_LRC,
+ XPM_EVENT_PLE_LRS,
+ XPM_EVENT_PLE_FLUSH,
+ XPM_EVENT_PLE_CMPL
+ },
+ {
+ XPM_EVENT_DATASTALL,
+ XPM_EVENT_INSRFETCH_CACHEREFILL,
+ XPM_EVENT_INSTRFECT_TLBREFILL,
+ XPM_EVENT_DATA_CACHEREFILL,
+ XPM_EVENT_DATA_CACHEACCESS,
+ XPM_EVENT_DATA_TLBREFILL
+ },
+ };
+ const u32 *ptr = PmcrEvents[PmcrCfg];
+
+ Xpm_DisableEventCounters();
+
+ for(Counter = 0U; Counter < XPM_CTRCOUNT; Counter++) {
+
+ /* Selecet event counter */
+ mtcp(XREG_CP15_EVENT_CNTR_SEL, Counter);
+
+ /* Set the event */
+ mtcp(XREG_CP15_EVENT_TYPE_SEL, ptr[Counter]);
+ }
+
+ Xpm_ResetEventCounters();
+ Xpm_EnableEventCounters();
+}
+
+/****************************************************************************/
+/**
+*
+* @brief This function disables the event counters and returns the counter
+* values.
+*
+* @param PmCtrValue: Pointer to an array of type u32 PmCtrValue[6].
+* It is an output parameter which is used to return the PM
+* counter values.
+*
+* @return None.
+*
+* @note None.
+*
+*****************************************************************************/
+void Xpm_GetEventCounters(u32 *PmCtrValue)
+{
+ u32 Counter;
+
+ Xpm_DisableEventCounters();
+
+ for(Counter = 0U; Counter < XPM_CTRCOUNT; Counter++) {
+
+ mtcp(XREG_CP15_EVENT_CNTR_SEL, Counter);
+#ifdef __GNUC__
+ PmCtrValue[Counter] = mfcp(XREG_CP15_PERF_MONITOR_COUNT);
+#elif defined (__ICCARM__)
+ mfcp(XREG_CP15_PERF_MONITOR_COUNT, PmCtrValue[Counter]);
+#else
+ { register u32 Cp15Reg __asm(XREG_CP15_PERF_MONITOR_COUNT);
+ PmCtrValue[Counter] = Cp15Reg; }
+#endif
+ }
+}
diff --git a/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v7_1/src/xpm_counter.h b/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v7_1/src/xpm_counter.h
new file mode 100644
index 0000000..1288952
--- /dev/null
+++ b/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v7_1/src/xpm_counter.h
@@ -0,0 +1,570 @@
+/******************************************************************************
+*
+* Copyright (C) 2011 - 2018 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+* THE SOFTWARE.
+*
+*
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xpm_counter.h
+*
+* @addtogroup a9_event_counter_apis Cortex A9 Event Counters Functions
+*
+* Cortex A9 event counter functions can be utilized to configure and control
+* the Cortex-A9 performance monitor events.
+*
+* Cortex-A9 performance monitor has six event counters which can be used to
+* count a variety of events described in Coretx-A9 TRM. xpm_counter.h defines
+* configurations XPM_CNTRCFGx which can be used to program the event counters
+* to count a set of events.
+*
+* @note
+* It doesn't handle the Cortex-A9 cycle counter, as the cycle counter is
+* being used for time keeping.
+*
+* @{
+*
+* <pre>
+* MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ----- ---- -------- -----------------------------------------------
+* 1.00a sdm 07/11/11 First release
+* 6.8 aru 09/06/18 Removed compilation warnings for ARMCC toolchain.
+* </pre>
+*
+******************************************************************************/
+
+#ifndef XPMCOUNTER_H /* prevent circular inclusions */
+#define XPMCOUNTER_H /* by using protection macros */
+
+/***************************** Include Files ********************************/
+
+#include <stdint.h>
+#include "xpseudo_asm.h"
+#include "xil_types.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif /* __cplusplus */
+
+/************************** Constant Definitions ****************************/
+
+/* Number of performance counters */
+#define XPM_CTRCOUNT 6U
+
+/* The following constants define the Cortex-A9 Performance Monitor Events */
+
+/*
+ * Software increment. The register is incremented only on writes to the
+ * Software Increment Register
+ */
+#define XPM_EVENT_SOFTINCR 0x00U
+
+/*
+ * Instruction fetch that causes a refill at (at least) the lowest level(s) of
+ * instruction or unified cache. Includes the speculative linefills in the
+ * count
+ */
+#define XPM_EVENT_INSRFETCH_CACHEREFILL 0x01U
+
+/*
+ * Instruction fetch that causes a TLB refill at (at least) the lowest level of
+ * TLB. Includes the speculative requests in the count
+ */
+#define XPM_EVENT_INSTRFECT_TLBREFILL 0x02U
+
+/*
+ * Data read or write operation that causes a refill at (at least) the lowest
+ * level(s)of data or unified cache. Counts the number of allocations performed
+ * in the Data Cache due to a read or a write
+ */
+#define XPM_EVENT_DATA_CACHEREFILL 0x03U
+
+/*
+ * Data read or write operation that causes a cache access at (at least) the
+ * lowest level(s) of data or unified cache. This includes speculative reads
+ */
+#define XPM_EVENT_DATA_CACHEACCESS 0x04U
+
+/*
+ * Data read or write operation that causes a TLB refill at (at least) the
+ * lowest level of TLB. This does not include micro TLB misses due to PLD, PLI,
+ * CP15 Cache operation by MVA and CP15 VA to PA operations
+ */
+#define XPM_EVENT_DATA_TLBREFILL 0x05U
+
+/*
+ * Data read architecturally executed. Counts the number of data read
+ * instructions accepted by the Load Store Unit. This includes counting the
+ * speculative and aborted LDR/LDM, as well as the reads due to the SWP
+ * instructions
+ */
+#define XPM_EVENT_DATA_READS 0x06U
+
+/*
+ * Data write architecturally executed. Counts the number of data write
+ * instructions accepted by the Load Store Unit. This includes counting the
+ * speculative and aborted STR/STM, as well as the writes due to the SWP
+ * instructions
+ */
+#define XPM_EVENT_DATA_WRITE 0x07U
+
+/* Exception taken. Counts the number of exceptions architecturally taken.*/
+#define XPM_EVENT_EXCEPTION 0x09U
+
+/* Exception return architecturally executed.*/
+#define XPM_EVENT_EXCEPRETURN 0x0AU
+
+/*
+ * Change to ContextID retired. Counts the number of instructions
+ * architecturally executed writing into the ContextID Register
+ */
+#define XPM_EVENT_CHANGECONTEXT 0x0BU
+
+/*
+ * Software change of PC, except by an exception, architecturally executed.
+ * Count the number of PC changes architecturally executed, excluding the PC
+ * changes due to taken exceptions
+ */
+#define XPM_EVENT_SW_CHANGEPC 0x0CU
+
+/*
+ * Immediate branch architecturally executed (taken or not taken). This includes
+ * the branches which are flushed due to a previous load/store which aborts
+ * late
+ */
+#define XPM_EVENT_IMMEDBRANCH 0x0DU
+
+/*
+ * Unaligned access architecturally executed. Counts the number of aborted
+ * unaligned accessed architecturally executed, and the number of not-aborted
+ * unaligned accesses, including the speculative ones
+ */
+#define XPM_EVENT_UNALIGNEDACCESS 0x0FU
+
+/*
+ * Branch mispredicted/not predicted. Counts the number of mispredicted or
+ * not-predicted branches executed. This includes the branches which are flushed
+ * due to a previous load/store which aborts late
+ */
+#define XPM_EVENT_BRANCHMISS 0x10U
+
+/*
+ * Counts clock cycles when the Cortex-A9 processor is not in WFE/WFI. This
+ * event is not exported on the PMUEVENT bus
+ */
+#define XPM_EVENT_CLOCKCYCLES 0x11U
+
+/*
+ * Branches or other change in program flow that could have been predicted by
+ * the branch prediction resources of the processor. This includes the branches
+ * which are flushed due to a previous load/store which aborts late
+ */
+#define XPM_EVENT_BRANCHPREDICT 0x12U
+
+/*
+ * Java bytecode execute. Counts the number of Java bytecodes being decoded,
+ * including speculative ones
+ */
+#define XPM_EVENT_JAVABYTECODE 0x40U
+
+/*
+ * Software Java bytecode executed. Counts the number of software java bytecodes
+ * being decoded, including speculative ones
+ */
+#define XPM_EVENT_SWJAVABYTECODE 0x41U
+
+/*
+ * Jazelle backward branches executed. Counts the number of Jazelle taken
+ * branches being executed. This includes the branches which are flushed due
+ * to a previous load/store which aborts late
+ */
+#define XPM_EVENT_JAVABACKBRANCH 0x42U
+
+/*
+ * Coherent linefill miss Counts the number of coherent linefill requests
+ * performed by the Cortex-A9 processor which also miss in all the other
+ * Cortex-A9 processors, meaning that the request is sent to the external
+ * memory
+ */
+#define XPM_EVENT_COHERLINEMISS 0x50U
+
+/*
+ * Coherent linefill hit. Counts the number of coherent linefill requests
+ * performed by the Cortex-A9 processor which hit in another Cortex-A9
+ * processor, meaning that the linefill data is fetched directly from the
+ * relevant Cortex-A9 cache
+ */
+#define XPM_EVENT_COHERLINEHIT 0x51U
+
+/*
+ * Instruction cache dependent stall cycles. Counts the number of cycles where
+ * the processor is ready to accept new instructions, but does not receive any
+ * due to the instruction side not being able to provide any and the
+ * instruction cache is currently performing at least one linefill
+ */
+#define XPM_EVENT_INSTRSTALL 0x60U
+
+/*
+ * Data cache dependent stall cycles. Counts the number of cycles where the core
+ * has some instructions that it cannot issue to any pipeline, and the Load
+ * Store unit has at least one pending linefill request, and no pending
+ */
+#define XPM_EVENT_DATASTALL 0x61U
+
+/*
+ * Main TLB miss stall cycles. Counts the number of cycles where the processor
+ * is stalled waiting for the completion of translation table walks from the
+ * main TLB. The processor stalls can be due to the instruction side not being
+ * able to provide the instructions, or to the data side not being able to
+ * provide the necessary data, due to them waiting for the main TLB translation
+ * table walk to complete
+ */
+#define XPM_EVENT_MAINTLBSTALL 0x62U
+
+/*
+ * Counts the number of STREX instructions architecturally executed and
+ * passed
+ */
+#define XPM_EVENT_STREXPASS 0x63U
+
+/*
+ * Counts the number of STREX instructions architecturally executed and
+ * failed
+ */
+#define XPM_EVENT_STREXFAIL 0x64U
+
+/*
+ * Data eviction. Counts the number of eviction requests due to a linefill in
+ * the data cache
+ */
+#define XPM_EVENT_DATAEVICT 0x65U
+
+/*
+ * Counts the number of cycles where the issue stage does not dispatch any
+ * instruction because it is empty or cannot dispatch any instructions
+ */
+#define XPM_EVENT_NODISPATCH 0x66U
+
+/*
+ * Counts the number of cycles where the issue stage is empty
+ */
+#define XPM_EVENT_ISSUEEMPTY 0x67U
+
+/*
+ * Counts the number of instructions going through the Register Renaming stage.
+ * This number is an approximate number of the total number of instructions
+ * speculatively executed, and even more approximate of the total number of
+ * instructions architecturally executed. The approximation depends mainly on
+ * the branch misprediction rate.
+ * The renaming stage can handle two instructions in the same cycle so the event
+ * is two bits long:
+ * - b00 no instructions renamed
+ * - b01 one instruction renamed
+ * - b10 two instructions renamed
+ */
+#define XPM_EVENT_INSTRRENAME 0x68U
+
+/*
+ * Counts the number of procedure returns whose condition codes do not fail,
+ * excluding all returns from exception. This count includes procedure returns
+ * which are flushed due to a previous load/store which aborts late.
+ * Only the following instructions are reported:
+ * - BX R14
+ * - MOV PC LR
+ * - POP {..,pc}
+ * - LDR pc,[sp],#offset
+ * The following instructions are not reported:
+ * - LDMIA R9!,{..,PC} (ThumbEE state only)
+ * - LDR PC,[R9],#offset (ThumbEE state only)
+ * - BX R0 (Rm != R14)
+ * - MOV PC,R0 (Rm != R14)
+ * - LDM SP,{...,PC} (writeback not specified)
+ * - LDR PC,[SP,#offset] (wrong addressing mode)
+ */
+#define XPM_EVENT_PREDICTFUNCRET 0x6EU
+
+/*
+ * Counts the number of instructions being executed in the main execution
+ * pipeline of the processor, the multiply pipeline and arithmetic logic unit
+ * pipeline. The counted instructions are still speculative
+ */
+#define XPM_EVENT_MAINEXEC 0x70U
+
+/*
+ * Counts the number of instructions being executed in the processor second
+ * execution pipeline (ALU). The counted instructions are still speculative
+ */
+#define XPM_EVENT_SECEXEC 0x71U
+
+/*
+ * Counts the number of instructions being executed in the Load/Store unit. The
+ * counted instructions are still speculative
+ */
+#define XPM_EVENT_LDRSTR 0x72U
+
+/*
+ * Counts the number of Floating-point instructions going through the Register
+ * Rename stage. Instructions are still speculative in this stage.
+ *Two floating-point instructions can be renamed in the same cycle so the event
+ * is two bitslong:
+ *0b00 no floating-point instruction renamed
+ *0b01 one floating-point instruction renamed
+ *0b10 two floating-point instructions renamed
+ */
+#define XPM_EVENT_FLOATRENAME 0x73U
+
+/*
+ * Counts the number of Neon instructions going through the Register Rename
+ * stage.Instructions are still speculative in this stage.
+ * Two NEON instructions can be renamed in the same cycle so the event is two
+ * bits long:
+ *0b00 no NEON instruction renamed
+ *0b01 one NEON instruction renamed
+ *0b10 two NEON instructions renamed
+ */
+#define XPM_EVENT_NEONRENAME 0x74U
+
+/*
+ * Counts the number of cycles where the processor is stalled because PLD slots
+ * are all full
+ */
+#define XPM_EVENT_PLDSTALL 0x80U
+
+/*
+ * Counts the number of cycles when the processor is stalled and the data side
+ * is stalled too because it is full and executing writes to the external
+ * memory
+ */
+#define XPM_EVENT_WRITESTALL 0x81U
+
+/*
+ * Counts the number of stall cycles due to main TLB misses on requests issued
+ * by the instruction side
+ */
+#define XPM_EVENT_INSTRTLBSTALL 0x82U
+
+/*
+ * Counts the number of stall cycles due to main TLB misses on requests issued
+ * by the data side
+ */
+#define XPM_EVENT_DATATLBSTALL 0x83U
+
+/*
+ * Counts the number of stall cycles due to micro TLB misses on the instruction
+ * side. This event does not include main TLB miss stall cycles that are already
+ * counted in the corresponding main TLB event
+ */
+#define XPM_EVENT_INSTR_uTLBSTALL 0x84U
+
+/*
+ * Counts the number of stall cycles due to micro TLB misses on the data side.
+ * This event does not include main TLB miss stall cycles that are already
+ * counted in the corresponding main TLB event
+ */
+#define XPM_EVENT_DATA_uTLBSTALL 0x85U
+
+/*
+ * Counts the number of stall cycles because of the execution of a DMB memory
+ * barrier. This includes all DMB instructions being executed, even
+ * speculatively
+ */
+#define XPM_EVENT_DMB_STALL 0x86U
+
+/*
+ * Counts the number of cycles during which the integer core clock is enabled
+ */
+#define XPM_EVENT_INT_CLKEN 0x8AU
+
+/*
+ * Counts the number of cycles during which the Data Engine clock is enabled
+ */
+#define XPM_EVENT_DE_CLKEN 0x8BU
+
+/*
+ * Counts the number of ISB instructions architecturally executed
+ */
+#define XPM_EVENT_INSTRISB 0x90U
+
+/*
+ * Counts the number of DSB instructions architecturally executed
+ */
+#define XPM_EVENT_INSTRDSB 0x91U
+
+/*
+ * Counts the number of DMB instructions speculatively executed
+ */
+#define XPM_EVENT_INSTRDMB 0x92U
+
+/*
+ * Counts the number of external interrupts executed by the processor
+ */
+#define XPM_EVENT_EXTINT 0x93U
+
+/*
+ * PLE cache line request completed
+ */
+#define XPM_EVENT_PLE_LRC 0xA0U
+
+/*
+ * PLE cache line request skipped
+ */
+#define XPM_EVENT_PLE_LRS 0xA1U
+
+/*
+ * PLE FIFO flush
+ */
+#define XPM_EVENT_PLE_FLUSH 0xA2U
+
+/*
+ * PLE request complete
+ */
+#define XPM_EVENT_PLE_CMPL 0xA3U
+
+/*
+ * PLE FIFO overflow
+ */
+#define XPM_EVENT_PLE_OVFL 0xA4U
+
+/*
+ * PLE request programmed
+ */
+#define XPM_EVENT_PLE_PROG 0xA5U
+
+/*
+ * The following constants define the configurations for Cortex-A9 Performance
+ * Monitor Events. Each configuration configures the event counters for a set
+ * of events.
+ * -----------------------------------------------
+ * Config PmCtr0... PmCtr5
+ * -----------------------------------------------
+ * XPM_CNTRCFG1 { XPM_EVENT_SOFTINCR,
+ * XPM_EVENT_INSRFETCH_CACHEREFILL,
+ * XPM_EVENT_INSTRFECT_TLBREFILL,
+ * XPM_EVENT_DATA_CACHEREFILL,
+ * XPM_EVENT_DATA_CACHEACCESS,
+ * XPM_EVENT_DATA_TLBREFILL }
+ *
+ * XPM_CNTRCFG2 { XPM_EVENT_DATA_READS,
+ * XPM_EVENT_DATA_WRITE,
+ * XPM_EVENT_EXCEPTION,
+ * XPM_EVENT_EXCEPRETURN,
+ * XPM_EVENT_CHANGECONTEXT,
+ * XPM_EVENT_SW_CHANGEPC }
+ *
+ * XPM_CNTRCFG3 { XPM_EVENT_IMMEDBRANCH,
+ * XPM_EVENT_UNALIGNEDACCESS,
+ * XPM_EVENT_BRANCHMISS,
+ * XPM_EVENT_CLOCKCYCLES,
+ * XPM_EVENT_BRANCHPREDICT,
+ * XPM_EVENT_JAVABYTECODE }
+ *
+ * XPM_CNTRCFG4 { XPM_EVENT_SWJAVABYTECODE,
+ * XPM_EVENT_JAVABACKBRANCH,
+ * XPM_EVENT_COHERLINEMISS,
+ * XPM_EVENT_COHERLINEHIT,
+ * XPM_EVENT_INSTRSTALL,
+ * XPM_EVENT_DATASTALL }
+ *
+ * XPM_CNTRCFG5 { XPM_EVENT_MAINTLBSTALL,
+ * XPM_EVENT_STREXPASS,
+ * XPM_EVENT_STREXFAIL,
+ * XPM_EVENT_DATAEVICT,
+ * XPM_EVENT_NODISPATCH,
+ * XPM_EVENT_ISSUEEMPTY }
+ *
+ * XPM_CNTRCFG6 { XPM_EVENT_INSTRRENAME,
+ * XPM_EVENT_PREDICTFUNCRET,
+ * XPM_EVENT_MAINEXEC,
+ * XPM_EVENT_SECEXEC,
+ * XPM_EVENT_LDRSTR,
+ * XPM_EVENT_FLOATRENAME }
+ *
+ * XPM_CNTRCFG7 { XPM_EVENT_NEONRENAME,
+ * XPM_EVENT_PLDSTALL,
+ * XPM_EVENT_WRITESTALL,
+ * XPM_EVENT_INSTRTLBSTALL,
+ * XPM_EVENT_DATATLBSTALL,
+ * XPM_EVENT_INSTR_uTLBSTALL }
+ *
+ * XPM_CNTRCFG8 { XPM_EVENT_DATA_uTLBSTALL,
+ * XPM_EVENT_DMB_STALL,
+ * XPM_EVENT_INT_CLKEN,
+ * XPM_EVENT_DE_CLKEN,
+ * XPM_EVENT_INSTRISB,
+ * XPM_EVENT_INSTRDSB }
+ *
+ * XPM_CNTRCFG9 { XPM_EVENT_INSTRDMB,
+ * XPM_EVENT_EXTINT,
+ * XPM_EVENT_PLE_LRC,
+ * XPM_EVENT_PLE_LRS,
+ * XPM_EVENT_PLE_FLUSH,
+ * XPM_EVENT_PLE_CMPL }
+ *
+ * XPM_CNTRCFG10 { XPM_EVENT_PLE_OVFL,
+ * XPM_EVENT_PLE_PROG,
+ * XPM_EVENT_PLE_LRC,
+ * XPM_EVENT_PLE_LRS,
+ * XPM_EVENT_PLE_FLUSH,
+ * XPM_EVENT_PLE_CMPL }
+ *
+ * XPM_CNTRCFG11 { XPM_EVENT_DATASTALL,
+ * XPM_EVENT_INSRFETCH_CACHEREFILL,
+ * XPM_EVENT_INSTRFECT_TLBREFILL,
+ * XPM_EVENT_DATA_CACHEREFILL,
+ * XPM_EVENT_DATA_CACHEACCESS,
+ * XPM_EVENT_DATA_TLBREFILL }
+ */
+#define XPM_CNTRCFG1 0
+#define XPM_CNTRCFG2 1
+#define XPM_CNTRCFG3 2
+#define XPM_CNTRCFG4 3
+#define XPM_CNTRCFG5 4
+#define XPM_CNTRCFG6 5
+#define XPM_CNTRCFG7 6
+#define XPM_CNTRCFG8 7
+#define XPM_CNTRCFG9 8
+#define XPM_CNTRCFG10 9
+#define XPM_CNTRCFG11 10
+
+/**************************** Type Definitions ******************************/
+
+/***************** Macros (Inline Functions) Definitions ********************/
+
+/************************** Variable Definitions ****************************/
+
+/************************** Function Prototypes *****************************/
+
+/* Interface functions to access performance counters from abstraction layer */
+void Xpm_SetEvents(s32 PmcrCfg);
+void Xpm_GetEventCounters(u32 *PmCtrValue);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
+/**
+* @} End of "addtogroup a9_event_counter_apis".
+*/
diff --git a/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v7_1/src/xpseudo_asm.h b/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v7_1/src/xpseudo_asm.h
new file mode 100644
index 0000000..9cc27a3
--- /dev/null
+++ b/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v7_1/src/xpseudo_asm.h
@@ -0,0 +1,80 @@
+/******************************************************************************
+*
+* Copyright (C) 2009 - 2018 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+* THE SOFTWARE.
+*
+*
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xpseudo_asm.h
+*
+* @addtogroup a9_specific Cortex A9 Processor Specific Include Files
+*
+* The xpseudo_asm.h includes xreg_cortexa9.h and xpseudo_asm_gcc.h.
+*
+* The xreg_cortexa9.h file contains definitions for inline assembler code.
+* It provides inline definitions for Cortex A9 GPRs, SPRs, MPE registers,
+* co-processor registers and Debug registers.
+*
+* The xpseudo_asm_gcc.h contains the definitions for the most often used inline
+* assembler instructions, available as macros. These can be very useful for
+* tasks such as setting or getting special purpose registers, synchronization,
+* or cache manipulation etc. These inline assembler instructions can be used
+* from drivers and user applications written in C.
+*
+* @{
+* <pre>
+* MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ----- ---- -------- -----------------------------------------------
+* 1.00a ecm 10/18/09 First release
+* 3.04a sdm 01/02/12 Remove redundant dsb in mcr instruction.
+* 6.8 aru 09/06/18 Removed compilation warnings for ARMCC toolchain.
+* </pre>
+*
+******************************************************************************/
+#ifndef XPSEUDO_ASM_H
+#define XPSEUDO_ASM_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include "xreg_cortexa9.h"
+#ifdef __GNUC__
+ #include "xpseudo_asm_gcc.h"
+#elif defined (__ICCARM__)
+ #include "xpseudo_asm_iccarm.h"
+#else
+ #include "xpseudo_asm_rvct.h"
+#endif
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* XPSEUDO_ASM_H */
+/**
+* @} End of "addtogroup a9_specific".
+*/
diff --git a/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v7_1/src/xpseudo_asm_gcc.h b/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v7_1/src/xpseudo_asm_gcc.h
new file mode 100644
index 0000000..ed3b8ff
--- /dev/null
+++ b/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v7_1/src/xpseudo_asm_gcc.h
@@ -0,0 +1,250 @@
+/******************************************************************************
+*
+* Copyright (C) 2014 - 2016 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+* THE SOFTWARE.
+*
+*
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xpseudo_asm_gcc.h
+*
+* This header file contains macros for using inline assembler code. It is
+* written specifically for the GNU compiler.
+*
+* <pre>
+* MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ----- -------- -------- -----------------------------------------------
+* 5.00 pkp 05/21/14 First release
+* 6.0 mus 07/27/16 Consolidated file for a53,a9 and r5 processors
+* </pre>
+*
+******************************************************************************/
+
+#ifndef XPSEUDO_ASM_GCC_H /* prevent circular inclusions */
+#define XPSEUDO_ASM_GCC_H /* by using protection macros */
+
+/***************************** Include Files ********************************/
+
+#include "xil_types.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif /* __cplusplus */
+
+/************************** Constant Definitions ****************************/
+
+/**************************** Type Definitions ******************************/
+
+/***************** Macros (Inline Functions) Definitions ********************/
+
+/* necessary for pre-processor */
+#define stringify(s) tostring(s)
+#define tostring(s) #s
+
+#if defined (__aarch64__)
+/* pseudo assembler instructions */
+#define mfcpsr() ({u32 rval = 0U; \
+ asm volatile("mrs %0, DAIF" : "=r" (rval));\
+ rval;\
+ })
+
+#define mtcpsr(v) __asm__ __volatile__ ("msr DAIF, %0" : : "r" (v))
+
+#define cpsiei() //__asm__ __volatile__("cpsie i\n")
+#define cpsidi() //__asm__ __volatile__("cpsid i\n")
+
+#define cpsief() //__asm__ __volatile__("cpsie f\n")
+#define cpsidf() //__asm__ __volatile__("cpsid f\n")
+
+
+
+#define mtgpr(rn, v) /*__asm__ __volatile__(\
+ "mov r" stringify(rn) ", %0 \n"\
+ : : "r" (v)\
+ )*/
+
+#define mfgpr(rn) /*({u32 rval; \
+ __asm__ __volatile__(\
+ "mov %0,r" stringify(rn) "\n"\
+ : "=r" (rval)\
+ );\
+ rval;\
+ })*/
+
+/* memory synchronization operations */
+
+/* Instruction Synchronization Barrier */
+#define isb() __asm__ __volatile__ ("isb sy")
+
+/* Data Synchronization Barrier */
+#define dsb() __asm__ __volatile__("dsb sy")
+
+/* Data Memory Barrier */
+#define dmb() __asm__ __volatile__("dmb sy")
+
+
+/* Memory Operations */
+#define ldr(adr) ({u64 rval; \
+ __asm__ __volatile__(\
+ "ldr %0,[%1]"\
+ : "=r" (rval) : "r" (adr)\
+ );\
+ rval;\
+ })
+
+#define mfelrel3() ({u64 rval = 0U; \
+ asm volatile("mrs %0, ELR_EL3" : "=r" (rval));\
+ rval;\
+ })
+
+#define mtelrel3(v) __asm__ __volatile__ ("msr ELR_EL3, %0" : : "r" (v))
+
+#else
+
+/* pseudo assembler instructions */
+#define mfcpsr() ({u32 rval = 0U; \
+ __asm__ __volatile__(\
+ "mrs %0, cpsr\n"\
+ : "=r" (rval)\
+ );\
+ rval;\
+ })
+
+#define mtcpsr(v) __asm__ __volatile__(\
+ "msr cpsr,%0\n"\
+ : : "r" (v)\
+ )
+
+#define cpsiei() __asm__ __volatile__("cpsie i\n")
+#define cpsidi() __asm__ __volatile__("cpsid i\n")
+
+#define cpsief() __asm__ __volatile__("cpsie f\n")
+#define cpsidf() __asm__ __volatile__("cpsid f\n")
+
+
+
+#define mtgpr(rn, v) __asm__ __volatile__(\
+ "mov r" stringify(rn) ", %0 \n"\
+ : : "r" (v)\
+ )
+
+#define mfgpr(rn) ({u32 rval; \
+ __asm__ __volatile__(\
+ "mov %0,r" stringify(rn) "\n"\
+ : "=r" (rval)\
+ );\
+ rval;\
+ })
+
+/* memory synchronization operations */
+
+/* Instruction Synchronization Barrier */
+#define isb() __asm__ __volatile__ ("isb" : : : "memory")
+
+/* Data Synchronization Barrier */
+#define dsb() __asm__ __volatile__ ("dsb" : : : "memory")
+
+/* Data Memory Barrier */
+#define dmb() __asm__ __volatile__ ("dmb" : : : "memory")
+
+
+/* Memory Operations */
+#define ldr(adr) ({u32 rval; \
+ __asm__ __volatile__(\
+ "ldr %0,[%1]"\
+ : "=r" (rval) : "r" (adr)\
+ );\
+ rval;\
+ })
+
+#endif
+
+#define ldrb(adr) ({u8 rval; \
+ __asm__ __volatile__(\
+ "ldrb %0,[%1]"\
+ : "=r" (rval) : "r" (adr)\
+ );\
+ rval;\
+ })
+
+#define str(adr, val) __asm__ __volatile__(\
+ "str %0,[%1]\n"\
+ : : "r" (val), "r" (adr)\
+ )
+
+#define strb(adr, val) __asm__ __volatile__(\
+ "strb %0,[%1]\n"\
+ : : "r" (val), "r" (adr)\
+ )
+
+/* Count leading zeroes (clz) */
+#define clz(arg) ({u8 rval; \
+ __asm__ __volatile__(\
+ "clz %0,%1"\
+ : "=r" (rval) : "r" (arg)\
+ );\
+ rval;\
+ })
+
+#if defined (__aarch64__)
+#define mtcpdc(reg,val) __asm__ __volatile__("dc " #reg ",%0" : : "r" (val))
+#define mtcpic(reg,val) __asm__ __volatile__("ic " #reg ",%0" : : "r" (val))
+
+#define mtcpicall(reg) __asm__ __volatile__("ic " #reg)
+#define mtcptlbi(reg) __asm__ __volatile__("tlbi " #reg)
+#define mtcpat(reg,val) __asm__ __volatile__("at " #reg ",%0" : : "r" (val))
+/* CP15 operations */
+#define mfcp(reg) ({u64 rval = 0U;\
+ __asm__ __volatile__("mrs %0, " #reg : "=r" (rval));\
+ rval;\
+ })
+
+#define mtcp(reg,val) __asm__ __volatile__("msr " #reg ",%0" : : "r" (val))
+
+#else
+/* CP15 operations */
+#define mtcp(rn, v) __asm__ __volatile__(\
+ "mcr " rn "\n"\
+ : : "r" (v)\
+ );
+
+#define mfcp(rn) ({u32 rval = 0U; \
+ __asm__ __volatile__(\
+ "mrc " rn "\n"\
+ : "=r" (rval)\
+ );\
+ rval;\
+ })
+#endif
+
+/************************** Variable Definitions ****************************/
+
+/************************** Function Prototypes *****************************/
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+
+#endif /* XPSEUDO_ASM_GCC_H */
diff --git a/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v7_1/src/xreg_cortexa9.h b/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v7_1/src/xreg_cortexa9.h
new file mode 100644
index 0000000..7638ca1
--- /dev/null
+++ b/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v7_1/src/xreg_cortexa9.h
@@ -0,0 +1,585 @@
+/******************************************************************************
+*
+* Copyright (C) 2009 - 2015 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+* THE SOFTWARE.
+*
+*
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xreg_cortexa9.h
+*
+* This header file contains definitions for using inline assembler code. It is
+* written specifically for the GNU, ARMCC compiler.
+*
+* All of the ARM Cortex A9 GPRs, SPRs, and Debug Registers are defined along
+* with the positions of the bits within the registers.
+*
+* <pre>
+* MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ----- -------- -------- -----------------------------------------------
+* 1.00a ecm/sdm 10/20/09 First release
+* </pre>
+*
+******************************************************************************/
+#ifndef XREG_CORTEXA9_H
+#define XREG_CORTEXA9_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif /* __cplusplus */
+
+/* GPRs */
+#define XREG_GPR0 r0
+#define XREG_GPR1 r1
+#define XREG_GPR2 r2
+#define XREG_GPR3 r3
+#define XREG_GPR4 r4
+#define XREG_GPR5 r5
+#define XREG_GPR6 r6
+#define XREG_GPR7 r7
+#define XREG_GPR8 r8
+#define XREG_GPR9 r9
+#define XREG_GPR10 r10
+#define XREG_GPR11 r11
+#define XREG_GPR12 r12
+#define XREG_GPR13 r13
+#define XREG_GPR14 r14
+#define XREG_GPR15 r15
+#define XREG_CPSR cpsr
+
+/* Coprocessor number defines */
+#define XREG_CP0 0
+#define XREG_CP1 1
+#define XREG_CP2 2
+#define XREG_CP3 3
+#define XREG_CP4 4
+#define XREG_CP5 5
+#define XREG_CP6 6
+#define XREG_CP7 7
+#define XREG_CP8 8
+#define XREG_CP9 9
+#define XREG_CP10 10
+#define XREG_CP11 11
+#define XREG_CP12 12
+#define XREG_CP13 13
+#define XREG_CP14 14
+#define XREG_CP15 15
+
+/* Coprocessor control register defines */
+#define XREG_CR0 cr0
+#define XREG_CR1 cr1
+#define XREG_CR2 cr2
+#define XREG_CR3 cr3
+#define XREG_CR4 cr4
+#define XREG_CR5 cr5
+#define XREG_CR6 cr6
+#define XREG_CR7 cr7
+#define XREG_CR8 cr8
+#define XREG_CR9 cr9
+#define XREG_CR10 cr10
+#define XREG_CR11 cr11
+#define XREG_CR12 cr12
+#define XREG_CR13 cr13
+#define XREG_CR14 cr14
+#define XREG_CR15 cr15
+
+/* Current Processor Status Register (CPSR) Bits */
+#define XREG_CPSR_THUMB_MODE 0x20
+#define XREG_CPSR_MODE_BITS 0x1F
+#define XREG_CPSR_SYSTEM_MODE 0x1F
+#define XREG_CPSR_UNDEFINED_MODE 0x1B
+#define XREG_CPSR_DATA_ABORT_MODE 0x17
+#define XREG_CPSR_SVC_MODE 0x13
+#define XREG_CPSR_IRQ_MODE 0x12
+#define XREG_CPSR_FIQ_MODE 0x11
+#define XREG_CPSR_USER_MODE 0x10
+
+#define XREG_CPSR_IRQ_ENABLE 0x80
+#define XREG_CPSR_FIQ_ENABLE 0x40
+
+#define XREG_CPSR_N_BIT 0x80000000
+#define XREG_CPSR_Z_BIT 0x40000000
+#define XREG_CPSR_C_BIT 0x20000000
+#define XREG_CPSR_V_BIT 0x10000000
+
+
+/* CP15 defines */
+#if defined (__GNUC__) || defined (__ICCARM__)
+/* C0 Register defines */
+#define XREG_CP15_MAIN_ID "p15, 0, %0, c0, c0, 0"
+#define XREG_CP15_CACHE_TYPE "p15, 0, %0, c0, c0, 1"
+#define XREG_CP15_TCM_TYPE "p15, 0, %0, c0, c0, 2"
+#define XREG_CP15_TLB_TYPE "p15, 0, %0, c0, c0, 3"
+#define XREG_CP15_MULTI_PROC_AFFINITY "p15, 0, %0, c0, c0, 5"
+
+#define XREG_CP15_PROC_FEATURE_0 "p15, 0, %0, c0, c1, 0"
+#define XREG_CP15_PROC_FEATURE_1 "p15, 0, %0, c0, c1, 1"
+#define XREG_CP15_DEBUG_FEATURE_0 "p15, 0, %0, c0, c1, 2"
+#define XREG_CP15_MEMORY_FEATURE_0 "p15, 0, %0, c0, c1, 4"
+#define XREG_CP15_MEMORY_FEATURE_1 "p15, 0, %0, c0, c1, 5"
+#define XREG_CP15_MEMORY_FEATURE_2 "p15, 0, %0, c0, c1, 6"
+#define XREG_CP15_MEMORY_FEATURE_3 "p15, 0, %0, c0, c1, 7"
+
+#define XREG_CP15_INST_FEATURE_0 "p15, 0, %0, c0, c2, 0"
+#define XREG_CP15_INST_FEATURE_1 "p15, 0, %0, c0, c2, 1"
+#define XREG_CP15_INST_FEATURE_2 "p15, 0, %0, c0, c2, 2"
+#define XREG_CP15_INST_FEATURE_3 "p15, 0, %0, c0, c2, 3"
+#define XREG_CP15_INST_FEATURE_4 "p15, 0, %0, c0, c2, 4"
+
+#define XREG_CP15_CACHE_SIZE_ID "p15, 1, %0, c0, c0, 0"
+#define XREG_CP15_CACHE_LEVEL_ID "p15, 1, %0, c0, c0, 1"
+#define XREG_CP15_AUXILARY_ID "p15, 1, %0, c0, c0, 7"
+
+#define XREG_CP15_CACHE_SIZE_SEL "p15, 2, %0, c0, c0, 0"
+
+/* C1 Register Defines */
+#define XREG_CP15_SYS_CONTROL "p15, 0, %0, c1, c0, 0"
+#define XREG_CP15_AUX_CONTROL "p15, 0, %0, c1, c0, 1"
+#define XREG_CP15_CP_ACCESS_CONTROL "p15, 0, %0, c1, c0, 2"
+
+#define XREG_CP15_SECURE_CONFIG "p15, 0, %0, c1, c1, 0"
+#define XREG_CP15_SECURE_DEBUG_ENABLE "p15, 0, %0, c1, c1, 1"
+#define XREG_CP15_NS_ACCESS_CONTROL "p15, 0, %0, c1, c1, 2"
+#define XREG_CP15_VIRTUAL_CONTROL "p15, 0, %0, c1, c1, 3"
+
+#else /* RVCT */
+/* C0 Register defines */
+#define XREG_CP15_MAIN_ID "cp15:0:c0:c0:0"
+#define XREG_CP15_CACHE_TYPE "cp15:0:c0:c0:1"
+#define XREG_CP15_TCM_TYPE "cp15:0:c0:c0:2"
+#define XREG_CP15_TLB_TYPE "cp15:0:c0:c0:3"
+#define XREG_CP15_MULTI_PROC_AFFINITY "cp15:0:c0:c0:5"
+
+#define XREG_CP15_PROC_FEATURE_0 "cp15:0:c0:c1:0"
+#define XREG_CP15_PROC_FEATURE_1 "cp15:0:c0:c1:1"
+#define XREG_CP15_DEBUG_FEATURE_0 "cp15:0:c0:c1:2"
+#define XREG_CP15_MEMORY_FEATURE_0 "cp15:0:c0:c1:4"
+#define XREG_CP15_MEMORY_FEATURE_1 "cp15:0:c0:c1:5"
+#define XREG_CP15_MEMORY_FEATURE_2 "cp15:0:c0:c1:6"
+#define XREG_CP15_MEMORY_FEATURE_3 "cp15:0:c0:c1:7"
+
+#define XREG_CP15_INST_FEATURE_0 "cp15:0:c0:c2:0"
+#define XREG_CP15_INST_FEATURE_1 "cp15:0:c0:c2:1"
+#define XREG_CP15_INST_FEATURE_2 "cp15:0:c0:c2:2"
+#define XREG_CP15_INST_FEATURE_3 "cp15:0:c0:c2:3"
+#define XREG_CP15_INST_FEATURE_4 "cp15:0:c0:c2:4"
+
+#define XREG_CP15_CACHE_SIZE_ID "cp15:1:c0:c0:0"
+#define XREG_CP15_CACHE_LEVEL_ID "cp15:1:c0:c0:1"
+#define XREG_CP15_AUXILARY_ID "cp15:1:c0:c0:7"
+
+#define XREG_CP15_CACHE_SIZE_SEL "cp15:2:c0:c0:0"
+
+/* C1 Register Defines */
+#define XREG_CP15_SYS_CONTROL "cp15:0:c1:c0:0"
+#define XREG_CP15_AUX_CONTROL "cp15:0:c1:c0:1"
+#define XREG_CP15_CP_ACCESS_CONTROL "cp15:0:c1:c0:2"
+
+#define XREG_CP15_SECURE_CONFIG "cp15:0:c1:c1:0"
+#define XREG_CP15_SECURE_DEBUG_ENABLE "cp15:0:c1:c1:1"
+#define XREG_CP15_NS_ACCESS_CONTROL "cp15:0:c1:c1:2"
+#define XREG_CP15_VIRTUAL_CONTROL "cp15:0:c1:c1:3"
+#endif
+
+/* XREG_CP15_CONTROL bit defines */
+#define XREG_CP15_CONTROL_TE_BIT 0x40000000U
+#define XREG_CP15_CONTROL_AFE_BIT 0x20000000U
+#define XREG_CP15_CONTROL_TRE_BIT 0x10000000U
+#define XREG_CP15_CONTROL_NMFI_BIT 0x08000000U
+#define XREG_CP15_CONTROL_EE_BIT 0x02000000U
+#define XREG_CP15_CONTROL_HA_BIT 0x00020000U
+#define XREG_CP15_CONTROL_RR_BIT 0x00004000U
+#define XREG_CP15_CONTROL_V_BIT 0x00002000U
+#define XREG_CP15_CONTROL_I_BIT 0x00001000U
+#define XREG_CP15_CONTROL_Z_BIT 0x00000800U
+#define XREG_CP15_CONTROL_SW_BIT 0x00000400U
+#define XREG_CP15_CONTROL_B_BIT 0x00000080U
+#define XREG_CP15_CONTROL_C_BIT 0x00000004U
+#define XREG_CP15_CONTROL_A_BIT 0x00000002U
+#define XREG_CP15_CONTROL_M_BIT 0x00000001U
+
+#if defined (__GNUC__) || defined (__ICCARM__)
+/* C2 Register Defines */
+#define XREG_CP15_TTBR0 "p15, 0, %0, c2, c0, 0"
+#define XREG_CP15_TTBR1 "p15, 0, %0, c2, c0, 1"
+#define XREG_CP15_TTB_CONTROL "p15, 0, %0, c2, c0, 2"
+
+/* C3 Register Defines */
+#define XREG_CP15_DOMAIN_ACCESS_CTRL "p15, 0, %0, c3, c0, 0"
+
+/* C4 Register Defines */
+/* Not Used */
+
+/* C5 Register Defines */
+#define XREG_CP15_DATA_FAULT_STATUS "p15, 0, %0, c5, c0, 0"
+#define XREG_CP15_INST_FAULT_STATUS "p15, 0, %0, c5, c0, 1"
+
+#define XREG_CP15_AUX_DATA_FAULT_STATUS "p15, 0, %0, c5, c1, 0"
+#define XREG_CP15_AUX_INST_FAULT_STATUS "p15, 0, %0, c5, c1, 1"
+
+/* C6 Register Defines */
+#define XREG_CP15_DATA_FAULT_ADDRESS "p15, 0, %0, c6, c0, 0"
+#define XREG_CP15_INST_FAULT_ADDRESS "p15, 0, %0, c6, c0, 2"
+
+/* C7 Register Defines */
+#define XREG_CP15_NOP "p15, 0, %0, c7, c0, 4"
+
+#define XREG_CP15_INVAL_IC_POU_IS "p15, 0, %0, c7, c1, 0"
+#define XREG_CP15_INVAL_BRANCH_ARRAY_IS "p15, 0, %0, c7, c1, 6"
+
+#define XREG_CP15_PHYS_ADDR "p15, 0, %0, c7, c4, 0"
+
+#define XREG_CP15_INVAL_IC_POU "p15, 0, %0, c7, c5, 0"
+#define XREG_CP15_INVAL_IC_LINE_MVA_POU "p15, 0, %0, c7, c5, 1"
+
+/* The CP15 register access below has been deprecated in favor of the new
+ * isb instruction in Cortex A9.
+ */
+#define XREG_CP15_INST_SYNC_BARRIER "p15, 0, %0, c7, c5, 4"
+#define XREG_CP15_INVAL_BRANCH_ARRAY "p15, 0, %0, c7, c5, 6"
+
+#define XREG_CP15_INVAL_DC_LINE_MVA_POC "p15, 0, %0, c7, c6, 1"
+#define XREG_CP15_INVAL_DC_LINE_SW "p15, 0, %0, c7, c6, 2"
+
+#define XREG_CP15_VA_TO_PA_CURRENT_0 "p15, 0, %0, c7, c8, 0"
+#define XREG_CP15_VA_TO_PA_CURRENT_1 "p15, 0, %0, c7, c8, 1"
+#define XREG_CP15_VA_TO_PA_CURRENT_2 "p15, 0, %0, c7, c8, 2"
+#define XREG_CP15_VA_TO_PA_CURRENT_3 "p15, 0, %0, c7, c8, 3"
+
+#define XREG_CP15_VA_TO_PA_OTHER_0 "p15, 0, %0, c7, c8, 4"
+#define XREG_CP15_VA_TO_PA_OTHER_1 "p15, 0, %0, c7, c8, 5"
+#define XREG_CP15_VA_TO_PA_OTHER_2 "p15, 0, %0, c7, c8, 6"
+#define XREG_CP15_VA_TO_PA_OTHER_3 "p15, 0, %0, c7, c8, 7"
+
+#define XREG_CP15_CLEAN_DC_LINE_MVA_POC "p15, 0, %0, c7, c10, 1"
+#define XREG_CP15_CLEAN_DC_LINE_SW "p15, 0, %0, c7, c10, 2"
+
+/* The next two CP15 register accesses below have been deprecated in favor
+ * of the new dsb and dmb instructions in Cortex A9.
+ */
+#define XREG_CP15_DATA_SYNC_BARRIER "p15, 0, %0, c7, c10, 4"
+#define XREG_CP15_DATA_MEMORY_BARRIER "p15, 0, %0, c7, c10, 5"
+
+#define XREG_CP15_CLEAN_DC_LINE_MVA_POU "p15, 0, %0, c7, c11, 1"
+
+#define XREG_CP15_NOP2 "p15, 0, %0, c7, c13, 1"
+
+#define XREG_CP15_CLEAN_INVAL_DC_LINE_MVA_POC "p15, 0, %0, c7, c14, 1"
+#define XREG_CP15_CLEAN_INVAL_DC_LINE_SW "p15, 0, %0, c7, c14, 2"
+
+/* C8 Register Defines */
+#define XREG_CP15_INVAL_TLB_IS "p15, 0, %0, c8, c3, 0"
+#define XREG_CP15_INVAL_TLB_MVA_IS "p15, 0, %0, c8, c3, 1"
+#define XREG_CP15_INVAL_TLB_ASID_IS "p15, 0, %0, c8, c3, 2"
+#define XREG_CP15_INVAL_TLB_MVA_ASID_IS "p15, 0, %0, c8, c3, 3"
+
+#define XREG_CP15_INVAL_ITLB_UNLOCKED "p15, 0, %0, c8, c5, 0"
+#define XREG_CP15_INVAL_ITLB_MVA "p15, 0, %0, c8, c5, 1"
+#define XREG_CP15_INVAL_ITLB_ASID "p15, 0, %0, c8, c5, 2"
+
+#define XREG_CP15_INVAL_DTLB_UNLOCKED "p15, 0, %0, c8, c6, 0"
+#define XREG_CP15_INVAL_DTLB_MVA "p15, 0, %0, c8, c6, 1"
+#define XREG_CP15_INVAL_DTLB_ASID "p15, 0, %0, c8, c6, 2"
+
+#define XREG_CP15_INVAL_UTLB_UNLOCKED "p15, 0, %0, c8, c7, 0"
+#define XREG_CP15_INVAL_UTLB_MVA "p15, 0, %0, c8, c7, 1"
+#define XREG_CP15_INVAL_UTLB_ASID "p15, 0, %0, c8, c7, 2"
+#define XREG_CP15_INVAL_UTLB_MVA_ASID "p15, 0, %0, c8, c7, 3"
+
+/* C9 Register Defines */
+#define XREG_CP15_PERF_MONITOR_CTRL "p15, 0, %0, c9, c12, 0"
+#define XREG_CP15_COUNT_ENABLE_SET "p15, 0, %0, c9, c12, 1"
+#define XREG_CP15_COUNT_ENABLE_CLR "p15, 0, %0, c9, c12, 2"
+#define XREG_CP15_V_FLAG_STATUS "p15, 0, %0, c9, c12, 3"
+#define XREG_CP15_SW_INC "p15, 0, %0, c9, c12, 4"
+#define XREG_CP15_EVENT_CNTR_SEL "p15, 0, %0, c9, c12, 5"
+
+#define XREG_CP15_PERF_CYCLE_COUNTER "p15, 0, %0, c9, c13, 0"
+#define XREG_CP15_EVENT_TYPE_SEL "p15, 0, %0, c9, c13, 1"
+#define XREG_CP15_PERF_MONITOR_COUNT "p15, 0, %0, c9, c13, 2"
+
+#define XREG_CP15_USER_ENABLE "p15, 0, %0, c9, c14, 0"
+#define XREG_CP15_INTR_ENABLE_SET "p15, 0, %0, c9, c14, 1"
+#define XREG_CP15_INTR_ENABLE_CLR "p15, 0, %0, c9, c14, 2"
+
+/* C10 Register Defines */
+#define XREG_CP15_TLB_LOCKDWN "p15, 0, %0, c10, c0, 0"
+
+#define XREG_CP15_PRI_MEM_REMAP "p15, 0, %0, c10, c2, 0"
+#define XREG_CP15_NORM_MEM_REMAP "p15, 0, %0, c10, c2, 1"
+
+/* C11 Register Defines */
+/* Not used */
+
+/* C12 Register Defines */
+#define XREG_CP15_VEC_BASE_ADDR "p15, 0, %0, c12, c0, 0"
+#define XREG_CP15_MONITOR_VEC_BASE_ADDR "p15, 0, %0, c12, c0, 1"
+
+#define XREG_CP15_INTERRUPT_STATUS "p15, 0, %0, c12, c1, 0"
+#define XREG_CP15_VIRTUALIZATION_INTR "p15, 0, %0, c12, c1, 1"
+
+/* C13 Register Defines */
+#define XREG_CP15_CONTEXT_ID "p15, 0, %0, c13, c0, 1"
+#define USER_RW_THREAD_PID "p15, 0, %0, c13, c0, 2"
+#define USER_RO_THREAD_PID "p15, 0, %0, c13, c0, 3"
+#define USER_PRIV_THREAD_PID "p15, 0, %0, c13, c0, 4"
+
+/* C14 Register Defines */
+/* not used */
+
+/* C15 Register Defines */
+#define XREG_CP15_POWER_CTRL "p15, 0, %0, c15, c0, 0"
+#define XREG_CP15_CONFIG_BASE_ADDR "p15, 4, %0, c15, c0, 0"
+
+#define XREG_CP15_READ_TLB_ENTRY "p15, 5, %0, c15, c4, 2"
+#define XREG_CP15_WRITE_TLB_ENTRY "p15, 5, %0, c15, c4, 4"
+
+#define XREG_CP15_MAIN_TLB_VA "p15, 5, %0, c15, c5, 2"
+
+#define XREG_CP15_MAIN_TLB_PA "p15, 5, %0, c15, c6, 2"
+
+#define XREG_CP15_MAIN_TLB_ATTR "p15, 5, %0, c15, c7, 2"
+
+#else
+/* C2 Register Defines */
+#define XREG_CP15_TTBR0 "cp15:0:c2:c0:0"
+#define XREG_CP15_TTBR1 "cp15:0:c2:c0:1"
+#define XREG_CP15_TTB_CONTROL "cp15:0:c2:c0:2"
+
+/* C3 Register Defines */
+#define XREG_CP15_DOMAIN_ACCESS_CTRL "cp15:0:c3:c0:0"
+
+/* C4 Register Defines */
+/* Not Used */
+
+/* C5 Register Defines */
+#define XREG_CP15_DATA_FAULT_STATUS "cp15:0:c5:c0:0"
+#define XREG_CP15_INST_FAULT_STATUS "cp15:0:c5:c0:1"
+
+#define XREG_CP15_AUX_DATA_FAULT_STATUS "cp15:0:c5:c1:0"
+#define XREG_CP15_AUX_INST_FAULT_STATUS "cp15:0:c5:c1:1"
+
+/* C6 Register Defines */
+#define XREG_CP15_DATA_FAULT_ADDRESS "cp15:0:c6:c0:0"
+#define XREG_CP15_INST_FAULT_ADDRESS "cp15:0:c6:c0:2"
+
+/* C7 Register Defines */
+#define XREG_CP15_NOP "cp15:0:c7:c0:4"
+
+#define XREG_CP15_INVAL_IC_POU_IS "cp15:0:c7:c1:0"
+#define XREG_CP15_INVAL_BRANCH_ARRAY_IS "cp15:0:c7:c1:6"
+
+#define XREG_CP15_PHYS_ADDR "cp15:0:c7:c4:0"
+
+#define XREG_CP15_INVAL_IC_POU "cp15:0:c7:c5:0"
+#define XREG_CP15_INVAL_IC_LINE_MVA_POU "cp15:0:c7:c5:1"
+
+/* The CP15 register access below has been deprecated in favor of the new
+ * isb instruction in Cortex A9.
+ */
+#define XREG_CP15_INST_SYNC_BARRIER "cp15:0:c7:c5:4"
+#define XREG_CP15_INVAL_BRANCH_ARRAY "cp15:0:c7:c5:6"
+
+#define XREG_CP15_INVAL_DC_LINE_MVA_POC "cp15:0:c7:c6:1"
+#define XREG_CP15_INVAL_DC_LINE_SW "cp15:0:c7:c6:2"
+
+#define XREG_CP15_VA_TO_PA_CURRENT_0 "cp15:0:c7:c8:0"
+#define XREG_CP15_VA_TO_PA_CURRENT_1 "cp15:0:c7:c8:1"
+#define XREG_CP15_VA_TO_PA_CURRENT_2 "cp15:0:c7:c8:2"
+#define XREG_CP15_VA_TO_PA_CURRENT_3 "cp15:0:c7:c8:3"
+
+#define XREG_CP15_VA_TO_PA_OTHER_0 "cp15:0:c7:c8:4"
+#define XREG_CP15_VA_TO_PA_OTHER_1 "cp15:0:c7:c8:5"
+#define XREG_CP15_VA_TO_PA_OTHER_2 "cp15:0:c7:c8:6"
+#define XREG_CP15_VA_TO_PA_OTHER_3 "cp15:0:c7:c8:7"
+
+#define XREG_CP15_CLEAN_DC_LINE_MVA_POC "cp15:0:c7:c10:1"
+#define XREG_CP15_CLEAN_DC_LINE_SW "cp15:0:c7:c10:2"
+
+/* The next two CP15 register accesses below have been deprecated in favor
+ * of the new dsb and dmb instructions in Cortex A9.
+ */
+#define XREG_CP15_DATA_SYNC_BARRIER "cp15:0:c7:c10:4"
+#define XREG_CP15_DATA_MEMORY_BARRIER "cp15:0:c7:c10:5"
+
+#define XREG_CP15_CLEAN_DC_LINE_MVA_POU "cp15:0:c7:c11:1"
+
+#define XREG_CP15_NOP2 "cp15:0:c7:c13:1"
+
+#define XREG_CP15_CLEAN_INVAL_DC_LINE_MVA_POC "cp15:0:c7:c14:1"
+#define XREG_CP15_CLEAN_INVAL_DC_LINE_SW "cp15:0:c7:c14:2"
+
+/* C8 Register Defines */
+#define XREG_CP15_INVAL_TLB_IS "cp15:0:c8:c3:0"
+#define XREG_CP15_INVAL_TLB_MVA_IS "cp15:0:c8:c3:1"
+#define XREG_CP15_INVAL_TLB_ASID_IS "cp15:0:c8:c3:2"
+#define XREG_CP15_INVAL_TLB_MVA_ASID_IS "cp15:0:c8:c3:3"
+
+#define XREG_CP15_INVAL_ITLB_UNLOCKED "cp15:0:c8:c5:0"
+#define XREG_CP15_INVAL_ITLB_MVA "cp15:0:c8:c5:1"
+#define XREG_CP15_INVAL_ITLB_ASID "cp15:0:c8:c5:2"
+
+#define XREG_CP15_INVAL_DTLB_UNLOCKED "cp15:0:c8:c6:0"
+#define XREG_CP15_INVAL_DTLB_MVA "cp15:0:c8:c6:1"
+#define XREG_CP15_INVAL_DTLB_ASID "cp15:0:c8:c6:2"
+
+#define XREG_CP15_INVAL_UTLB_UNLOCKED "cp15:0:c8:c7:0"
+#define XREG_CP15_INVAL_UTLB_MVA "cp15:0:c8:c7:1"
+#define XREG_CP15_INVAL_UTLB_ASID "cp15:0:c8:c7:2"
+#define XREG_CP15_INVAL_UTLB_MVA_ASID "cp15:0:c8:c7:3"
+
+/* C9 Register Defines */
+#define XREG_CP15_PERF_MONITOR_CTRL "cp15:0:c9:c12:0"
+#define XREG_CP15_COUNT_ENABLE_SET "cp15:0:c9:c12:1"
+#define XREG_CP15_COUNT_ENABLE_CLR "cp15:0:c9:c12:2"
+#define XREG_CP15_V_FLAG_STATUS "cp15:0:c9:c12:3"
+#define XREG_CP15_SW_INC "cp15:0:c9:c12:4"
+#define XREG_CP15_EVENT_CNTR_SEL "cp15:0:c9:c12:5"
+
+#define XREG_CP15_PERF_CYCLE_COUNTER "cp15:0:c9:c13:0"
+#define XREG_CP15_EVENT_TYPE_SEL "cp15:0:c9:c13:1"
+#define XREG_CP15_PERF_MONITOR_COUNT "cp15:0:c9:c13:2"
+
+#define XREG_CP15_USER_ENABLE "cp15:0:c9:c14:0"
+#define XREG_CP15_INTR_ENABLE_SET "cp15:0:c9:c14:1"
+#define XREG_CP15_INTR_ENABLE_CLR "cp15:0:c9:c14:2"
+
+/* C10 Register Defines */
+#define XREG_CP15_TLB_LOCKDWN "cp15:0:c10:c0:0"
+
+#define XREG_CP15_PRI_MEM_REMAP "cp15:0:c10:c2:0"
+#define XREG_CP15_NORM_MEM_REMAP "cp15:0:c10:c2:1"
+
+/* C11 Register Defines */
+/* Not used */
+
+/* C12 Register Defines */
+#define XREG_CP15_VEC_BASE_ADDR "cp15:0:c12:c0:0"
+#define XREG_CP15_MONITOR_VEC_BASE_ADDR "cp15:0:c12:c0:1"
+
+#define XREG_CP15_INTERRUPT_STATUS "cp15:0:c12:c1:0"
+#define XREG_CP15_VIRTUALIZATION_INTR "cp15:0:c12:c1:1"
+
+/* C13 Register Defines */
+#define XREG_CP15_CONTEXT_ID "cp15:0:c13:c0:1"
+#define USER_RW_THREAD_PID "cp15:0:c13:c0:2"
+#define USER_RO_THREAD_PID "cp15:0:c13:c0:3"
+#define USER_PRIV_THREAD_PID "cp15:0:c13:c0:4"
+
+/* C14 Register Defines */
+/* not used */
+
+/* C15 Register Defines */
+#define XREG_CP15_POWER_CTRL "cp15:0:c15:c0:0"
+#define XREG_CP15_CONFIG_BASE_ADDR "cp15:4:c15:c0:0"
+
+#define XREG_CP15_READ_TLB_ENTRY "cp15:5:c15:c4:2"
+#define XREG_CP15_WRITE_TLB_ENTRY "cp15:5:c15:c4:4"
+
+#define XREG_CP15_MAIN_TLB_VA "cp15:5:c15:c5:2"
+
+#define XREG_CP15_MAIN_TLB_PA "cp15:5:c15:c6:2"
+
+#define XREG_CP15_MAIN_TLB_ATTR "cp15:5:c15:c7:2"
+#endif
+
+
+/* MPE register definitions */
+#define XREG_FPSID c0
+#define XREG_FPSCR c1
+#define XREG_MVFR1 c6
+#define XREG_MVFR0 c7
+#define XREG_FPEXC c8
+#define XREG_FPINST c9
+#define XREG_FPINST2 c10
+
+/* FPSID bits */
+#define XREG_FPSID_IMPLEMENTER_BIT (24)
+#define XREG_FPSID_IMPLEMENTER_MASK (0xFF << FPSID_IMPLEMENTER_BIT)
+#define XREG_FPSID_SOFTWARE (1<<23)
+#define XREG_FPSID_ARCH_BIT (16)
+#define XREG_FPSID_ARCH_MASK (0xF << FPSID_ARCH_BIT)
+#define XREG_FPSID_PART_BIT (8)
+#define XREG_FPSID_PART_MASK (0xFF << FPSID_PART_BIT)
+#define XREG_FPSID_VARIANT_BIT (4)
+#define XREG_FPSID_VARIANT_MASK (0xF << FPSID_VARIANT_BIT)
+#define XREG_FPSID_REV_BIT (0)
+#define XREG_FPSID_REV_MASK (0xF << FPSID_REV_BIT)
+
+/* FPSCR bits */
+#define XREG_FPSCR_N_BIT (1 << 31)
+#define XREG_FPSCR_Z_BIT (1 << 30)
+#define XREG_FPSCR_C_BIT (1 << 29)
+#define XREG_FPSCR_V_BIT (1 << 28)
+#define XREG_FPSCR_QC (1 << 27)
+#define XREG_FPSCR_AHP (1 << 26)
+#define XREG_FPSCR_DEFAULT_NAN (1 << 25)
+#define XREG_FPSCR_FLUSHTOZERO (1 << 24)
+#define XREG_FPSCR_ROUND_NEAREST (0 << 22)
+#define XREG_FPSCR_ROUND_PLUSINF (1 << 22)
+#define XREG_FPSCR_ROUND_MINUSINF (2 << 22)
+#define XREG_FPSCR_ROUND_TOZERO (3 << 22)
+#define XREG_FPSCR_RMODE_BIT (22)
+#define XREG_FPSCR_RMODE_MASK (3 << FPSCR_RMODE_BIT)
+#define XREG_FPSCR_STRIDE_BIT (20)
+#define XREG_FPSCR_STRIDE_MASK (3 << FPSCR_STRIDE_BIT)
+#define XREG_FPSCR_LENGTH_BIT (16)
+#define XREG_FPSCR_LENGTH_MASK (7 << FPSCR_LENGTH_BIT)
+#define XREG_FPSCR_IDC (1 << 7)
+#define XREG_FPSCR_IXC (1 << 4)
+#define XREG_FPSCR_UFC (1 << 3)
+#define XREG_FPSCR_OFC (1 << 2)
+#define XREG_FPSCR_DZC (1 << 1)
+#define XREG_FPSCR_IOC (1 << 0)
+
+/* MVFR0 bits */
+#define XREG_MVFR0_RMODE_BIT (28)
+#define XREG_MVFR0_RMODE_MASK (0xF << XREG_MVFR0_RMODE_BIT)
+#define XREG_MVFR0_SHORT_VEC_BIT (24)
+#define XREG_MVFR0_SHORT_VEC_MASK (0xF << XREG_MVFR0_SHORT_VEC_BIT)
+#define XREG_MVFR0_SQRT_BIT (20)
+#define XREG_MVFR0_SQRT_MASK (0xF << XREG_MVFR0_SQRT_BIT)
+#define XREG_MVFR0_DIVIDE_BIT (16)
+#define XREG_MVFR0_DIVIDE_MASK (0xF << XREG_MVFR0_DIVIDE_BIT)
+#define XREG_MVFR0_EXEC_TRAP_BIT (12)
+#define XREG_MVFR0_EXEC_TRAP_MASK (0xF << XREG_MVFR0_EXEC_TRAP_BIT)
+#define XREG_MVFR0_DP_BIT (8)
+#define XREG_MVFR0_DP_MASK (0xF << XREG_MVFR0_DP_BIT)
+#define XREG_MVFR0_SP_BIT (4)
+#define XREG_MVFR0_SP_MASK (0xF << XREG_MVFR0_SP_BIT)
+#define XREG_MVFR0_A_SIMD_BIT (0)
+#define XREG_MVFR0_A_SIMD_MASK (0xF << MVFR0_A_SIMD_BIT)
+
+/* FPEXC bits */
+#define XREG_FPEXC_EX (1 << 31)
+#define XREG_FPEXC_EN (1 << 30)
+#define XREG_FPEXC_DEX (1 << 29)
+
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+
+#endif /* XREG_CORTEXA9_H */
diff --git a/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v7_1/src/xstatus.h b/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v7_1/src/xstatus.h
new file mode 100644
index 0000000..9a6ed89
--- /dev/null
+++ b/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v7_1/src/xstatus.h
@@ -0,0 +1,533 @@
+/******************************************************************************
+*
+* Copyright (C) 2002 - 2019 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+* THE SOFTWARE.
+*
+*
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xstatus.h
+*
+* @addtogroup common_status_codes Xilinx® software status codes
+*
+* The xstatus.h file contains the Xilinx® software status codes.These codes are
+* used throughout the Xilinx device drivers.
+*
+* @{
+******************************************************************************/
+
+#ifndef XSTATUS_H /* prevent circular inclusions */
+#define XSTATUS_H /* by using protection macros */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/***************************** Include Files *********************************/
+
+#include "xil_types.h"
+#include "xil_assert.h"
+
+/************************** Constant Definitions *****************************/
+
+/*********************** Common statuses 0 - 500 *****************************/
+/**
+@name Common Status Codes for All Device Drivers
+@{
+*/
+#define XST_SUCCESS 0L
+#define XST_FAILURE 1L
+#define XST_DEVICE_NOT_FOUND 2L
+#define XST_DEVICE_BLOCK_NOT_FOUND 3L
+#define XST_INVALID_VERSION 4L
+#define XST_DEVICE_IS_STARTED 5L
+#define XST_DEVICE_IS_STOPPED 6L
+#define XST_FIFO_ERROR 7L /*!< An error occurred during an
+ operation with a FIFO such as
+ an underrun or overrun, this
+ error requires the device to
+ be reset */
+#define XST_RESET_ERROR 8L /*!< An error occurred which requires
+ the device to be reset */
+#define XST_DMA_ERROR 9L /*!< A DMA error occurred, this error
+ typically requires the device
+ using the DMA to be reset */
+#define XST_NOT_POLLED 10L /*!< The device is not configured for
+ polled mode operation */
+#define XST_FIFO_NO_ROOM 11L /*!< A FIFO did not have room to put
+ the specified data into */
+#define XST_BUFFER_TOO_SMALL 12L /*!< The buffer is not large enough
+ to hold the expected data */
+#define XST_NO_DATA 13L /*!< There was no data available */
+#define XST_REGISTER_ERROR 14L /*!< A register did not contain the
+ expected value */
+#define XST_INVALID_PARAM 15L /*!< An invalid parameter was passed
+ into the function */
+#define XST_NOT_SGDMA 16L /*!< The device is not configured for
+ scatter-gather DMA operation */
+#define XST_LOOPBACK_ERROR 17L /*!< A loopback test failed */
+#define XST_NO_CALLBACK 18L /*!< A callback has not yet been
+ registered */
+#define XST_NO_FEATURE 19L /*!< Device is not configured with
+ the requested feature */
+#define XST_NOT_INTERRUPT 20L /*!< Device is not configured for
+ interrupt mode operation */
+#define XST_DEVICE_BUSY 21L /*!< Device is busy */
+#define XST_ERROR_COUNT_MAX 22L /*!< The error counters of a device
+ have maxed out */
+#define XST_IS_STARTED 23L /*!< Used when part of device is
+ already started i.e.
+ sub channel */
+#define XST_IS_STOPPED 24L /*!< Used when part of device is
+ already stopped i.e.
+ sub channel */
+#define XST_DATA_LOST 26L /*!< Driver defined error */
+#define XST_RECV_ERROR 27L /*!< Generic receive error */
+#define XST_SEND_ERROR 28L /*!< Generic transmit error */
+#define XST_NOT_ENABLED 29L /*!< A requested service is not
+ available because it has not
+ been enabled */
+#define XST_NO_ACCESS 30L /* Generic access error */
+#define XST_TIMEOUT 31L /*!< Event timeout occurred */
+
+/** @} */
+/***************** Utility Component statuses 401 - 500 *********************/
+/**
+@name Utility Component Status Codes 401 - 500
+@{
+*/
+#define XST_MEMTEST_FAILED 401L /*!< Memory test failed */
+
+/** @} */
+/***************** Common Components statuses 501 - 1000 *********************/
+/**
+@name Packet Fifo Status Codes 501 - 510
+@{
+*/
+/********************* Packet Fifo statuses 501 - 510 ************************/
+
+#define XST_PFIFO_LACK_OF_DATA 501L /*!< Not enough data in FIFO */
+#define XST_PFIFO_NO_ROOM 502L /*!< Not enough room in FIFO */
+#define XST_PFIFO_BAD_REG_VALUE 503L /*!< Self test, a register value
+ was invalid after reset */
+#define XST_PFIFO_ERROR 504L /*!< Generic packet FIFO error */
+#define XST_PFIFO_DEADLOCK 505L /*!< Packet FIFO is reporting
+ * empty and full simultaneously
+ */
+/** @} */
+/**
+@name DMA Status Codes 511 - 530
+@{
+*/
+/************************** DMA statuses 511 - 530 ***************************/
+
+#define XST_DMA_TRANSFER_ERROR 511L /*!< Self test, DMA transfer
+ failed */
+#define XST_DMA_RESET_REGISTER_ERROR 512L /*!< Self test, a register value
+ was invalid after reset */
+#define XST_DMA_SG_LIST_EMPTY 513L /*!< Scatter gather list contains
+ no buffer descriptors ready
+ to be processed */
+#define XST_DMA_SG_IS_STARTED 514L /*!< Scatter gather not stopped */
+#define XST_DMA_SG_IS_STOPPED 515L /*!< Scatter gather not running */
+#define XST_DMA_SG_LIST_FULL 517L /*!< All the buffer descriptors of
+ the scatter gather list are
+ being used */
+#define XST_DMA_SG_BD_LOCKED 518L /*!< The scatter gather buffer
+ descriptor which is to be
+ copied over in the scatter
+ list is locked */
+#define XST_DMA_SG_NOTHING_TO_COMMIT 519L /*!< No buffer descriptors have been
+ put into the scatter gather
+ list to be committed */
+#define XST_DMA_SG_COUNT_EXCEEDED 521L /*!< The packet count threshold
+ specified was larger than the
+ total # of buffer descriptors
+ in the scatter gather list */
+#define XST_DMA_SG_LIST_EXISTS 522L /*!< The scatter gather list has
+ already been created */
+#define XST_DMA_SG_NO_LIST 523L /*!< No scatter gather list has
+ been created */
+#define XST_DMA_SG_BD_NOT_COMMITTED 524L /*!< The buffer descriptor which was
+ being started was not committed
+ to the list */
+#define XST_DMA_SG_NO_DATA 525L /*!< The buffer descriptor to start
+ has already been used by the
+ hardware so it can't be reused
+ */
+#define XST_DMA_SG_LIST_ERROR 526L /*!< General purpose list access
+ error */
+#define XST_DMA_BD_ERROR 527L /*!< General buffer descriptor
+ error */
+/** @} */
+/**
+@name IPIF Status Codes Codes 531 - 550
+@{
+*/
+/************************** IPIF statuses 531 - 550 ***************************/
+
+#define XST_IPIF_REG_WIDTH_ERROR 531L /*!< An invalid register width
+ was passed into the function */
+#define XST_IPIF_RESET_REGISTER_ERROR 532L /*!< The value of a register at
+ reset was not valid */
+#define XST_IPIF_DEVICE_STATUS_ERROR 533L /*!< A write to the device interrupt
+ status register did not read
+ back correctly */
+#define XST_IPIF_DEVICE_ACK_ERROR 534L /*!< The device interrupt status
+ register did not reset when
+ acked */
+#define XST_IPIF_DEVICE_ENABLE_ERROR 535L /*!< The device interrupt enable
+ register was not updated when
+ other registers changed */
+#define XST_IPIF_IP_STATUS_ERROR 536L /*!< A write to the IP interrupt
+ status register did not read
+ back correctly */
+#define XST_IPIF_IP_ACK_ERROR 537L /*!< The IP interrupt status register
+ did not reset when acked */
+#define XST_IPIF_IP_ENABLE_ERROR 538L /*!< IP interrupt enable register was
+ not updated correctly when other
+ registers changed */
+#define XST_IPIF_DEVICE_PENDING_ERROR 539L /*!< The device interrupt pending
+ register did not indicate the
+ expected value */
+#define XST_IPIF_DEVICE_ID_ERROR 540L /*!< The device interrupt ID register
+ did not indicate the expected
+ value */
+#define XST_IPIF_ERROR 541L /*!< Generic ipif error */
+/** @} */
+
+/****************** Device specific statuses 1001 - 4095 *********************/
+/**
+@name Ethernet Status Codes 1001 - 1050
+@{
+*/
+/********************* Ethernet statuses 1001 - 1050 *************************/
+
+#define XST_EMAC_MEMORY_SIZE_ERROR 1001L /*!< Memory space is not big enough
+ * to hold the minimum number of
+ * buffers or descriptors */
+#define XST_EMAC_MEMORY_ALLOC_ERROR 1002L /*!< Memory allocation failed */
+#define XST_EMAC_MII_READ_ERROR 1003L /*!< MII read error */
+#define XST_EMAC_MII_BUSY 1004L /*!< An MII operation is in progress */
+#define XST_EMAC_OUT_OF_BUFFERS 1005L /*!< Driver is out of buffers */
+#define XST_EMAC_PARSE_ERROR 1006L /*!< Invalid driver init string */
+#define XST_EMAC_COLLISION_ERROR 1007L /*!< Excess deferral or late
+ * collision on polled send */
+/** @} */
+/**
+@name UART Status Codes 1051 - 1075
+@{
+*/
+/*********************** UART statuses 1051 - 1075 ***************************/
+#define XST_UART
+
+#define XST_UART_INIT_ERROR 1051L
+#define XST_UART_START_ERROR 1052L
+#define XST_UART_CONFIG_ERROR 1053L
+#define XST_UART_TEST_FAIL 1054L
+#define XST_UART_BAUD_ERROR 1055L
+#define XST_UART_BAUD_RANGE 1056L
+
+/** @} */
+/**
+@name IIC Status Codes 1076 - 1100
+@{
+*/
+/************************ IIC statuses 1076 - 1100 ***************************/
+
+#define XST_IIC_SELFTEST_FAILED 1076 /*!< self test failed */
+#define XST_IIC_BUS_BUSY 1077 /*!< bus found busy */
+#define XST_IIC_GENERAL_CALL_ADDRESS 1078 /*!< mastersend attempted with */
+ /* general call address */
+#define XST_IIC_STAND_REG_RESET_ERROR 1079 /*!< A non parameterizable reg */
+ /* value after reset not valid */
+#define XST_IIC_TX_FIFO_REG_RESET_ERROR 1080 /*!< Tx fifo included in design */
+ /* value after reset not valid */
+#define XST_IIC_RX_FIFO_REG_RESET_ERROR 1081 /*!< Rx fifo included in design */
+ /* value after reset not valid */
+#define XST_IIC_TBA_REG_RESET_ERROR 1082 /*!< 10 bit addr incl in design */
+ /* value after reset not valid */
+#define XST_IIC_CR_READBACK_ERROR 1083 /*!< Read of the control register */
+ /* didn't return value written */
+#define XST_IIC_DTR_READBACK_ERROR 1084 /*!< Read of the data Tx reg */
+ /* didn't return value written */
+#define XST_IIC_DRR_READBACK_ERROR 1085 /*!< Read of the data Receive reg */
+ /* didn't return value written */
+#define XST_IIC_ADR_READBACK_ERROR 1086 /*!< Read of the data Tx reg */
+ /* didn't return value written */
+#define XST_IIC_TBA_READBACK_ERROR 1087 /*!< Read of the 10 bit addr reg */
+ /* didn't return written value */
+#define XST_IIC_NOT_SLAVE 1088 /*!< The device isn't a slave */
+#define XST_IIC_ARB_LOST 1089 /*!< Arbitration lost for master */
+/** @} */
+/**
+@name ATMC Status Codes 1101 - 1125
+@{
+*/
+/*********************** ATMC statuses 1101 - 1125 ***************************/
+
+#define XST_ATMC_ERROR_COUNT_MAX 1101L /*!< the error counters in the ATM
+ controller hit the max value
+ which requires the statistics
+ to be cleared */
+/** @} */
+/**
+@name Flash Status Codes 1126 - 1150
+@{
+*/
+/*********************** Flash statuses 1126 - 1150 **************************/
+
+#define XST_FLASH_BUSY 1126L /*!< Flash is erasing or programming
+ */
+#define XST_FLASH_READY 1127L /*!< Flash is ready for commands */
+#define XST_FLASH_ERROR 1128L /*!< Flash had detected an internal
+ error. Use XFlash_DeviceControl
+ to retrieve device specific codes
+ */
+#define XST_FLASH_ERASE_SUSPENDED 1129L /*!< Flash is in suspended erase state
+ */
+#define XST_FLASH_WRITE_SUSPENDED 1130L /*!< Flash is in suspended write state
+ */
+#define XST_FLASH_PART_NOT_SUPPORTED 1131L /*!< Flash type not supported by
+ driver */
+#define XST_FLASH_NOT_SUPPORTED 1132L /*!< Operation not supported */
+#define XST_FLASH_TOO_MANY_REGIONS 1133L /*!< Too many erase regions */
+#define XST_FLASH_TIMEOUT_ERROR 1134L /*!< Programming or erase operation
+ aborted due to a timeout */
+#define XST_FLASH_ADDRESS_ERROR 1135L /*!< Accessed flash outside its
+ addressible range */
+#define XST_FLASH_ALIGNMENT_ERROR 1136L /*!< Write alignment error */
+#define XST_FLASH_BLOCKING_CALL_ERROR 1137L /*!< Couldn't return immediately from
+ write/erase function with
+ XFL_NON_BLOCKING_WRITE/ERASE
+ option cleared */
+#define XST_FLASH_CFI_QUERY_ERROR 1138L /*!< Failed to query the device */
+/** @} */
+/**
+@name SPI Status Codes 1151 - 1175
+@{
+*/
+/*********************** SPI statuses 1151 - 1175 ****************************/
+
+#define XST_SPI_MODE_FAULT 1151 /*!< master was selected as slave */
+#define XST_SPI_TRANSFER_DONE 1152 /*!< data transfer is complete */
+#define XST_SPI_TRANSMIT_UNDERRUN 1153 /*!< slave underruns transmit register */
+#define XST_SPI_RECEIVE_OVERRUN 1154 /*!< device overruns receive register */
+#define XST_SPI_NO_SLAVE 1155 /*!< no slave has been selected yet */
+#define XST_SPI_TOO_MANY_SLAVES 1156 /*!< more than one slave is being
+ * selected */
+#define XST_SPI_NOT_MASTER 1157 /*!< operation is valid only as master */
+#define XST_SPI_SLAVE_ONLY 1158 /*!< device is configured as slave-only
+ */
+#define XST_SPI_SLAVE_MODE_FAULT 1159 /*!< slave was selected while disabled */
+#define XST_SPI_SLAVE_MODE 1160 /*!< device has been addressed as slave */
+#define XST_SPI_RECEIVE_NOT_EMPTY 1161 /*!< device received data in slave mode */
+
+#define XST_SPI_COMMAND_ERROR 1162 /*!< unrecognised command - qspi only */
+#define XST_SPI_POLL_DONE 1163 /*!< controller completed polling the
+ device for status */
+/** @} */
+/**
+@name OPB Arbiter Status Codes 1176 - 1200
+@{
+*/
+/********************** OPB Arbiter statuses 1176 - 1200 *********************/
+
+#define XST_OPBARB_INVALID_PRIORITY 1176 /*!< the priority registers have either
+ * one master assigned to two or more
+ * priorities, or one master not
+ * assigned to any priority
+ */
+#define XST_OPBARB_NOT_SUSPENDED 1177 /*!< an attempt was made to modify the
+ * priority levels without first
+ * suspending the use of priority
+ * levels
+ */
+#define XST_OPBARB_PARK_NOT_ENABLED 1178 /*!< bus parking by id was enabled but
+ * bus parking was not enabled
+ */
+#define XST_OPBARB_NOT_FIXED_PRIORITY 1179 /*!< the arbiter must be in fixed
+ * priority mode to allow the
+ * priorities to be changed
+ */
+/** @} */
+/**
+@name INTC Status Codes 1201 - 1225
+@{
+*/
+/************************ Intc statuses 1201 - 1225 **************************/
+
+#define XST_INTC_FAIL_SELFTEST 1201 /*!< self test failed */
+#define XST_INTC_CONNECT_ERROR 1202 /*!< interrupt already in use */
+/** @} */
+/**
+@name TmrCtr Status Codes 1226 - 1250
+@{
+*/
+/********************** TmrCtr statuses 1226 - 1250 **************************/
+
+#define XST_TMRCTR_TIMER_FAILED 1226 /*!< self test failed */
+/** @} */
+/**
+@name WdtTb Status Codes 1251 - 1275
+@{
+*/
+/********************** WdtTb statuses 1251 - 1275 ***************************/
+
+#define XST_WDTTB_TIMER_FAILED 1251L
+/** @} */
+/**
+@name PlbArb status Codes 1276 - 1300
+@{
+*/
+/********************** PlbArb statuses 1276 - 1300 **************************/
+
+#define XST_PLBARB_FAIL_SELFTEST 1276L
+/** @} */
+/**
+@name Plb2Opb Status Codes 1301 - 1325
+@{
+*/
+/********************** Plb2Opb statuses 1301 - 1325 *************************/
+
+#define XST_PLB2OPB_FAIL_SELFTEST 1301L
+/** @} */
+/**
+@name Opb2Plb Status 1326 - 1350
+@{
+*/
+/********************** Opb2Plb statuses 1326 - 1350 *************************/
+
+#define XST_OPB2PLB_FAIL_SELFTEST 1326L
+/** @} */
+/**
+@name SysAce Status Codes 1351 - 1360
+@{
+*/
+/********************** SysAce statuses 1351 - 1360 **************************/
+
+#define XST_SYSACE_NO_LOCK 1351L /*!< No MPU lock has been granted */
+/** @} */
+/**
+@name PCI Bridge Status Codes 1361 - 1375
+@{
+*/
+/********************** PCI Bridge statuses 1361 - 1375 **********************/
+
+#define XST_PCI_INVALID_ADDRESS 1361L
+/** @} */
+/**
+@name FlexRay Constants 1400 - 1409
+@{
+*/
+/********************** FlexRay constants 1400 - 1409 *************************/
+
+#define XST_FR_TX_ERROR 1400
+#define XST_FR_TX_BUSY 1401
+#define XST_FR_BUF_LOCKED 1402
+#define XST_FR_NO_BUF 1403
+/** @} */
+/**
+@name USB constants 1410 - 1420
+@{
+*/
+/****************** USB constants 1410 - 1420 *******************************/
+
+#define XST_USB_ALREADY_CONFIGURED 1410
+#define XST_USB_BUF_ALIGN_ERROR 1411
+#define XST_USB_NO_DESC_AVAILABLE 1412
+#define XST_USB_BUF_TOO_BIG 1413
+#define XST_USB_NO_BUF 1414
+/** @} */
+/**
+@name HWICAP constants 1421 - 1429
+@{
+*/
+/****************** HWICAP constants 1421 - 1429 *****************************/
+
+#define XST_HWICAP_WRITE_DONE 1421
+
+/** @} */
+/**
+@name AXI VDMA constants 1430 - 1440
+@{
+*/
+/****************** AXI VDMA constants 1430 - 1440 *****************************/
+
+#define XST_VDMA_MISMATCH_ERROR 1430
+/** @} */
+/**
+@name NAND Flash Status Codes 1441 - 1459
+@{
+*/
+/*********************** NAND Flash statuses 1441 - 1459 *********************/
+
+#define XST_NAND_BUSY 1441L /*!< Flash is erasing or
+ * programming
+ */
+#define XST_NAND_READY 1442L /*!< Flash is ready for commands
+ */
+#define XST_NAND_ERROR 1443L /*!< Flash had detected an
+ * internal error.
+ */
+#define XST_NAND_PART_NOT_SUPPORTED 1444L /*!< Flash type not supported by
+ * driver
+ */
+#define XST_NAND_OPT_NOT_SUPPORTED 1445L /*!< Operation not supported
+ */
+#define XST_NAND_TIMEOUT_ERROR 1446L /*!< Programming or erase
+ * operation aborted due to a
+ * timeout
+ */
+#define XST_NAND_ADDRESS_ERROR 1447L /*!< Accessed flash outside its
+ * addressible range
+ */
+#define XST_NAND_ALIGNMENT_ERROR 1448L /*!< Write alignment error
+ */
+#define XST_NAND_PARAM_PAGE_ERROR 1449L /*!< Failed to read parameter
+ * page of the device
+ */
+#define XST_NAND_CACHE_ERROR 1450L /*!< Flash page buffer error
+ */
+
+#define XST_NAND_WRITE_PROTECTED 1451L /*!< Flash is write protected
+ */
+/** @} */
+
+/**************************** Type Definitions *******************************/
+
+typedef s32 XStatus;
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+
+/************************** Function Prototypes ******************************/
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* end of protection macro */
+/**
+* @} End of "addtogroup common_status_codes".
+*/
diff --git a/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v7_1/src/xtime_l.c b/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v7_1/src/xtime_l.c
new file mode 100644
index 0000000..936e4bb
--- /dev/null
+++ b/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v7_1/src/xtime_l.c
@@ -0,0 +1,116 @@
+/******************************************************************************
+*
+* Copyright (C) 2009 - 2015 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+* THE SOFTWARE.
+*
+*
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+* @file xtime_l.c
+*
+* This file contains low level functions to get/set time from the Global Timer
+* register in the ARM Cortex A9 MP core.
+*
+* <pre>
+* MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ----- ------ -------- ---------------------------------------------------
+* 1.00a rp/sdm 11/03/09 Initial release.
+* 3.07a sgd 07/05/12 Updated get/set time functions to make use Global Timer
+* </pre>
+*
+* @note None.
+*
+******************************************************************************/
+/***************************** Include Files *********************************/
+
+#include "xtime_l.h"
+#include "xpseudo_asm.h"
+#include "xil_types.h"
+#include "xil_assert.h"
+#include "xil_io.h"
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/**************************** Type Definitions *******************************/
+
+/************************** Constant Definitions *****************************/
+
+/************************** Variable Definitions *****************************/
+
+/************************** Function Prototypes ******************************/
+
+/****************************************************************************/
+/**
+* @brief Set the time in the Global Timer Counter Register.
+*
+* @param Xtime_Global: 64-bit Value to be written to the Global Timer
+* Counter Register.
+*
+* @return None.
+*
+* @note When this function is called by any one processor in a multi-
+* processor environment, reference time will reset/lost for all
+* processors.
+*
+****************************************************************************/
+void XTime_SetTime(XTime Xtime_Global)
+{
+ /* Disable Global Timer */
+ Xil_Out32((u32)GLOBAL_TMR_BASEADDR + (u32)GTIMER_CONTROL_OFFSET, (u32)0x0);
+
+ /* Updating Global Timer Counter Register */
+ Xil_Out32((u32)GLOBAL_TMR_BASEADDR + (u32)GTIMER_COUNTER_LOWER_OFFSET, (u32)Xtime_Global);
+ Xil_Out32((u32)GLOBAL_TMR_BASEADDR + (u32)GTIMER_COUNTER_UPPER_OFFSET,
+ (u32)((u32)(Xtime_Global>>32U)));
+
+ /* Enable Global Timer */
+ Xil_Out32((u32)GLOBAL_TMR_BASEADDR + (u32)GTIMER_CONTROL_OFFSET, (u32)0x1);
+}
+
+/****************************************************************************/
+/**
+* @brief Get the time from the Global Timer Counter Register.
+*
+* @param Xtime_Global: Pointer to the 64-bit location which will be
+* updated with the current timer value.
+*
+* @return None.
+*
+* @note None.
+*
+****************************************************************************/
+void XTime_GetTime(XTime *Xtime_Global)
+{
+ u32 low;
+ u32 high;
+
+ /* Reading Global Timer Counter Register */
+ do
+ {
+ high = Xil_In32(GLOBAL_TMR_BASEADDR + GTIMER_COUNTER_UPPER_OFFSET);
+ low = Xil_In32(GLOBAL_TMR_BASEADDR + GTIMER_COUNTER_LOWER_OFFSET);
+ } while(Xil_In32(GLOBAL_TMR_BASEADDR + GTIMER_COUNTER_UPPER_OFFSET) != high);
+
+ *Xtime_Global = (((XTime) high) << 32U) | (XTime) low;
+}
diff --git a/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v7_1/src/xtime_l.h b/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v7_1/src/xtime_l.h
new file mode 100644
index 0000000..8392419
--- /dev/null
+++ b/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v7_1/src/xtime_l.h
@@ -0,0 +1,102 @@
+/******************************************************************************
+*
+* Copyright (C) 2009 - 2018 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+* THE SOFTWARE.
+*
+*
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+* @file xtime_l.h
+* @addtogroup a9_time_apis Cortex A9 Time Functions
+*
+* xtime_l.h provides access to the 64-bit Global Counter in the PMU. This
+* counter increases by one at every two processor cycles. These functions can
+* be used to get/set time in the global timer.
+*
+* @{
+* <pre>
+* MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ----- ------ -------- ---------------------------------------------------
+* 1.00a rp/sdm 11/03/09 Initial release.
+* 3.06a sgd 05/15/12 Updated get/set time functions to make use Global Timer
+* 3.06a asa 06/17/12 Reverted back the changes to make use Global Timer.
+* 3.07a sgd 07/05/12 Updated get/set time functions to make use Global Timer
+* 6.6 srm 10/23/17 Updated the macros to support user configurable sleep
+* implementation
+* 6.8 aru 09/06/18 Removed compilation warnings for ARMCC toolchain.
+* </pre>
+*
+******************************************************************************/
+
+#ifndef XTIME_H /* prevent circular inclusions */
+#define XTIME_H /* by using protection macros */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/***************************** Include Files *********************************/
+
+#include "xil_types.h"
+#include "xparameters.h"
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/**************************** Type Definitions *******************************/
+
+typedef u64 XTime;
+
+/************************** Constant Definitions *****************************/
+#define GLOBAL_TMR_BASEADDR XPAR_GLOBAL_TMR_BASEADDR
+#define GTIMER_COUNTER_LOWER_OFFSET 0x00U
+#define GTIMER_COUNTER_UPPER_OFFSET 0x04U
+#define GTIMER_CONTROL_OFFSET 0x08U
+
+#if defined (SLEEP_TIMER_BASEADDR)
+#define COUNTS_PER_SECOND (SLEEP_TIMER_FREQUENCY)
+#else
+/* Global Timer is always clocked at half of the CPU frequency */
+#define COUNTS_PER_SECOND (XPAR_CPU_CORTEXA9_CORE_CLOCK_FREQ_HZ /2)
+#endif
+
+#if defined (XSLEEP_TIMER_IS_DEFAULT_TIMER)
+#ifdef __GNUC__
+#pragma message ("For the sleep routines, Global timer is being used")
+#endif
+#endif
+/************************** Variable Definitions *****************************/
+
+/************************** Function Prototypes ******************************/
+
+void XTime_SetTime(XTime Xtime_Global);
+void XTime_GetTime(XTime *Xtime_Global);
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+
+#endif /* XTIME_H */
+/**
+* @} End of "addtogroup a9_time_apis".
+*/
diff --git a/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/ttcps_v3_10/src/Makefile b/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/ttcps_v3_10/src/Makefile
new file mode 100644
index 0000000..35c277d
--- /dev/null
+++ b/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/ttcps_v3_10/src/Makefile
@@ -0,0 +1,40 @@
+COMPILER=
+ARCHIVER=
+CP=cp
+COMPILER_FLAGS=
+EXTRA_COMPILER_FLAGS=
+LIB=libxil.a
+
+CC_FLAGS = $(COMPILER_FLAGS)
+ECC_FLAGS = $(EXTRA_COMPILER_FLAGS)
+
+RELEASEDIR=../../../lib
+INCLUDEDIR=../../../include
+INCLUDES=-I./. -I${INCLUDEDIR}
+
+OUTS = *.o
+
+LIBSOURCES:=*.c
+INCLUDEFILES:=*.h
+
+OBJECTS = $(addsuffix .o, $(basename $(wildcard *.c)))
+
+libs: banner ttcps_libs clean
+
+%.o: %.c
+ ${COMPILER} $(CC_FLAGS) $(ECC_FLAGS) $(INCLUDES) -o $@ $<
+
+banner:
+ echo "Compiling ttcps"
+
+ttcps_libs: ${OBJECTS}
+ $(ARCHIVER) -r ${RELEASEDIR}/${LIB} ${OBJECTS}
+
+.PHONY: include
+include: ttcps_includes
+
+ttcps_includes:
+ ${CP} ${INCLUDEFILES} ${INCLUDEDIR}
+
+clean:
+ rm -rf ${OBJECTS}
diff --git a/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/ttcps_v3_10/src/xttcps.c b/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/ttcps_v3_10/src/xttcps.c
new file mode 100644
index 0000000..07758d9
--- /dev/null
+++ b/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/ttcps_v3_10/src/xttcps.c
@@ -0,0 +1,555 @@
+/******************************************************************************
+*
+* Copyright (C) 2010 - 2019 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+* THE SOFTWARE.
+*
+*
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xttcps.c
+* @addtogroup ttcps_v3_10
+* @{
+*
+* This file contains the implementation of the XTtcPs driver. This driver
+* controls the operation of one timer counter in the Triple Timer Counter (TTC)
+* module in the Ps block. Refer to xttcps.h for more detailed description
+* of the driver.
+*
+* <pre>
+* MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ----- ------ -------- -------------------------------------------------
+* 1.00a drg/jz 01/21/10 First release
+* 3.00 kvn 02/13/15 Modified code for MISRA-C:2012 compliance.
+* 3.01 pkp 01/30/16 Modified XTtcPs_CfgInitialize to add XTtcps_Stop
+* to stop the timer before configuring
+* 3.2 mus 10/28/16 Modified XTtcPs_CalcIntervalFromFreq to calculate
+* 32 bit interval count for zynq ultrascale+mpsoc
+* 3.5 srm 10/06/17 Updated XTtcPs_GetMatchValue and XTtcPs_SetMatchValue
+* APIs to use correct match register width for zynq
+* (i.e. 16 bit) and zynq ultrascale+mpsoc (i.e. 32 bit).
+* It fixes CR# 986617
+* 3.6 srm 04/25/18 Corrected the Match register initialization in
+ XTtcPs_CfgInitialize API.
+* 3.7 mus 09/20/18 Modified XTtcPs_CalcIntervalFromFreq API to use
+* XTTCPS_MAX_INTERVAL_COUNT instead of hardcoding
+* MAX interval count to 16 bit value(i.e.65532),
+* which is incorrect for zynq ultrascale+mpsoc
+* (i.e. max interval count is 32 bit).
+* 3.10 aru 05/06/19 Added assert check for driver instance and freq
+* parameter in XTtcPs_CalcIntervalFromFreq().
+* 3.10 aru 05/30/19 Added interrupt handler to clear ISR
+* </pre>
+*
+******************************************************************************/
+
+/***************************** Include Files *********************************/
+
+#include "xttcps.h"
+
+/************************** Constant Definitions *****************************/
+
+/**************************** Type Definitions *******************************/
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/************************** Function Prototypes ******************************/
+static void StubStatusHandler(const void *CallBackRef, u32 StatusEvent);
+/************************** Variable Definitions *****************************/
+
+
+/*****************************************************************************/
+/**
+*
+* Initializes a specific XTtcPs instance such that the driver is ready to use.
+* This function initializes a single timer counter in the triple timer counter
+* function block.
+*
+* The state of the device after initialization is:
+* - Overflow Mode
+* - Internal (pclk) selected
+* - Counter disabled
+* - All Interrupts disabled
+* - Output waveforms disabled
+*
+* @param InstancePtr is a pointer to the XTtcPs instance.
+* @param ConfigPtr is a reference to a structure containing information
+* about a specific TTC device.
+* @param EffectiveAddr is the device base address in the virtual memory
+* address space. The caller is responsible for keeping the address
+* mapping from EffectiveAddr to the device physical base address
+* unchanged once this function is invoked. Unexpected errors may
+* occur if the address mapping changes after this function is
+* called. If address translation is not used, then use
+* ConfigPtr->BaseAddress for this parameter, passing the physical
+* address instead.
+*
+* @return
+*
+* - XST_SUCCESS if the initialization is successful.
+* - XST_DEVICE_IS_STARTED if the device is started. It must be
+* stopped to re-initialize.
+*
+* @note Device has to be stopped first to call this function to
+* initialize it.
+*
+******************************************************************************/
+s32 XTtcPs_CfgInitialize(XTtcPs *InstancePtr, XTtcPs_Config *ConfigPtr,
+ u32 EffectiveAddr)
+{
+ s32 Status;
+ u32 IsStartResult;
+ /*
+ * Assert to validate input arguments.
+ */
+ Xil_AssertNonvoid(InstancePtr != NULL);
+ Xil_AssertNonvoid(ConfigPtr != NULL);
+
+ /*
+ * Set some default values
+ */
+ InstancePtr->Config.DeviceId = ConfigPtr->DeviceId;
+ InstancePtr->Config.BaseAddress = EffectiveAddr;
+ InstancePtr->Config.InputClockHz = ConfigPtr->InputClockHz;
+ InstancePtr->StatusHandler = StubStatusHandler;
+
+ IsStartResult = XTtcPs_IsStarted(InstancePtr);
+ /*
+ * If the timer counter has already started, return an error
+ * Device should be stopped first.
+ */
+ if(IsStartResult == (u32)TRUE) {
+ Status = XST_DEVICE_IS_STARTED;
+ } else {
+
+ /*
+ * stop the timer before configuring
+ */
+ XTtcPs_Stop(InstancePtr);
+ /*
+ * Reset the count control register to it's default value.
+ */
+ XTtcPs_WriteReg(InstancePtr->Config.BaseAddress,
+ XTTCPS_CNT_CNTRL_OFFSET,
+ XTTCPS_CNT_CNTRL_RESET_VALUE);
+
+ /*
+ * Reset the rest of the registers to the default values.
+ */
+ XTtcPs_WriteReg(InstancePtr->Config.BaseAddress,
+ XTTCPS_CLK_CNTRL_OFFSET, 0x00U);
+ XTtcPs_WriteReg(InstancePtr->Config.BaseAddress,
+ XTTCPS_INTERVAL_VAL_OFFSET, 0x00U);
+ XTtcPs_WriteReg(InstancePtr->Config.BaseAddress,
+ XTTCPS_MATCH_0_OFFSET, 0x00U);
+ XTtcPs_WriteReg(InstancePtr->Config.BaseAddress,
+ XTTCPS_MATCH_1_OFFSET, 0x00U);
+ XTtcPs_WriteReg(InstancePtr->Config.BaseAddress,
+ XTTCPS_MATCH_2_OFFSET, 0x00U);
+ XTtcPs_WriteReg(InstancePtr->Config.BaseAddress,
+ XTTCPS_IER_OFFSET, 0x00U);
+ XTtcPs_WriteReg(InstancePtr->Config.BaseAddress,
+ XTTCPS_ISR_OFFSET, XTTCPS_IXR_ALL_MASK);
+
+ InstancePtr->IsReady = XIL_COMPONENT_IS_READY;
+
+ /*
+ * Reset the counter value
+ */
+ XTtcPs_ResetCounterValue(InstancePtr);
+ Status = XST_SUCCESS;
+ }
+ return Status;
+}
+
+/*****************************************************************************/
+/**
+*
+* This function is used to set the match registers. There are three match
+* registers.
+*
+* The match 0 register is special. If the waveform output mode is enabled, the
+* waveform will change polarity when the count matches the value in the match 0
+* register. The polarity of the waveform output can also be set using the
+* XTtcPs_SetOptions() function.
+*
+* @param InstancePtr is a pointer to the XTtcPs instance.
+* @param MatchIndex is the index to the match register to be set.
+* Valid values are: 0 - 2.
+* @param Value is the 16-bit value to be set in the match register.
+* Valid Values are: (For Zynq):
+* 0 - ((2^16)-1)
+* (For Zynq UltraScale + MpSoc) and Versal:
+* 0 - ((2^32) - 1)
+*
+* @return None
+*
+* @note None
+*
+****************************************************************************/
+void XTtcPs_SetMatchValue(XTtcPs *InstancePtr, u8 MatchIndex, XMatchRegValue Value)
+{
+ /*
+ * Assert to validate input arguments.
+ */
+ Xil_AssertVoid(InstancePtr != NULL);
+ Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+ Xil_AssertVoid(MatchIndex < (u8)XTTCPS_NUM_MATCH_REG);
+
+ /*
+ * Write the value to the correct match register with MatchIndex
+ */
+ XTtcPs_WriteReg(InstancePtr->Config.BaseAddress,
+ XTtcPs_Match_N_Offset(MatchIndex), Value);
+}
+
+/*****************************************************************************/
+/**
+*
+* This function is used to get the value of the match registers. There are
+* three match registers.
+*
+* @param InstancePtr is a pointer to the XTtcPs instance.
+* @param MatchIndex is the index to the match register to be set.
+* There are three match registers are there.
+* Valid values are: 0 - 2.
+*
+* @return The match register value
+*
+* @note None
+*
+****************************************************************************/
+XMatchRegValue XTtcPs_GetMatchValue(XTtcPs *InstancePtr, u8 MatchIndex)
+{
+ u32 MatchReg;
+
+ /*
+ * Assert to validate input arguments.
+ */
+ Xil_AssertNonvoid(InstancePtr != NULL);
+ Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+ Xil_AssertNonvoid(MatchIndex < XTTCPS_NUM_MATCH_REG);
+
+ MatchReg = XTtcPs_ReadReg(InstancePtr->Config.BaseAddress,
+ XTtcPs_Match_N_Offset(MatchIndex));
+
+ return (XMatchRegValue) MatchReg;
+}
+
+/*****************************************************************************/
+/**
+*
+* This function sets the prescaler enable bit and if needed sets the prescaler
+* bits in the control register.
+*
+* @param InstancePtr is a pointer to the XTtcPs instance.
+* @param PrescalerValue is a number from 0-16 that sets the prescaler
+* to use.
+* If the parameter is 0 - 15, use a prescaler on the clock of
+* 2^(PrescalerValue+1), or 2-65536.
+* If the parameter is XTTCPS_CLK_CNTRL_PS_DISABLE, do not use a
+* prescaler.
+*
+* Valid values are: 0 - 15
+*
+* @return None
+*
+* @note None
+*
+****************************************************************************/
+void XTtcPs_SetPrescaler(XTtcPs *InstancePtr, u8 PrescalerValue)
+{
+ u32 ClockReg;
+
+ /*
+ * Assert to validate input arguments.
+ */
+ Xil_AssertVoid(InstancePtr != NULL);
+ Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+ Xil_AssertVoid(PrescalerValue <= XTTCPS_CLK_CNTRL_PS_DISABLE);
+
+ /*
+ * Read the clock control register
+ */
+ ClockReg = XTtcPs_ReadReg(InstancePtr->Config.BaseAddress,
+ XTTCPS_CLK_CNTRL_OFFSET);
+
+ /*
+ * Clear all of the prescaler control bits in the register
+ */
+ ClockReg &=
+ ~(XTTCPS_CLK_CNTRL_PS_VAL_MASK | XTTCPS_CLK_CNTRL_PS_EN_MASK);
+
+ if (PrescalerValue < XTTCPS_CLK_CNTRL_PS_DISABLE) {
+ /*
+ * Set the prescaler value and enable prescaler
+ */
+ ClockReg |= (u32)(((u32)PrescalerValue << (u32)XTTCPS_CLK_CNTRL_PS_VAL_SHIFT) &
+ (u32)XTTCPS_CLK_CNTRL_PS_VAL_MASK);
+ ClockReg |= (u32)XTTCPS_CLK_CNTRL_PS_EN_MASK;
+ }
+
+ /*
+ * Write the register with the new values.
+ */
+ XTtcPs_WriteReg(InstancePtr->Config.BaseAddress,
+ XTTCPS_CLK_CNTRL_OFFSET, ClockReg);
+}
+
+/*****************************************************************************/
+/**
+*
+* This function gets the input clock prescaler
+*
+* @param InstancePtr is a pointer to the XTtcPs instance.
+*
+* <pre>
+* @return The value(n) from which the prescalar value is calculated
+* as 2^(n+1). Some example values are given below :
+*
+* Value Prescaler
+* 0 2
+* 1 4
+* N 2^(n+1)
+* 15 65536
+* 16 1
+*
+* Valid values are: 0 - 16
+* </pre>
+*
+* @note None.
+*
+****************************************************************************/
+u8 XTtcPs_GetPrescaler(XTtcPs *InstancePtr)
+{
+ u8 Status;
+ u32 ClockReg;
+
+ /*
+ * Assert to validate input arguments.
+ */
+ Xil_AssertNonvoid(InstancePtr != NULL);
+ Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+ /*
+ * Read the clock control register
+ */
+ ClockReg = XTtcPs_ReadReg(InstancePtr->Config.BaseAddress,
+ XTTCPS_CLK_CNTRL_OFFSET);
+
+ if (0 == (ClockReg & XTTCPS_CLK_CNTRL_PS_EN_MASK)) {
+ /*
+ * Prescaler is disabled. Return the correct flag value
+ */
+ Status = (u8)XTTCPS_CLK_CNTRL_PS_DISABLE;
+ }
+ else {
+
+ Status = (u8)((ClockReg & (u32)XTTCPS_CLK_CNTRL_PS_VAL_MASK) >>
+ (u32)XTTCPS_CLK_CNTRL_PS_VAL_SHIFT);
+ }
+ return Status;
+}
+
+/*****************************************************************************/
+/**
+*
+* This function calculates the interval value as well as the prescaler value
+* for a given frequency.
+*
+* @param InstancePtr is a pointer to the XTtcPs instance.
+* @param Freq is the requested output frequency for the device.
+* valid values are: 1 - (2^32)-1
+* @param Interval is the interval value for the given frequency,
+* it is the output value for this function.
+* @param Prescaler is the prescaler value for the given frequency,
+* it is the output value for this function.
+*
+* @return None.
+*
+* @note
+* Upon successful calculation for the given frequency, Interval and Prescaler
+* carry the settings for the timer counter; Upon unsuccessful calculation,
+* Interval and Prescaler are set to 0xFF(FF) for their maximum values to
+* signal the caller of failure. Therefore, caller needs to check the return
+* interval or prescaler values for whether the function has succeeded.
+*
+****************************************************************************/
+void XTtcPs_CalcIntervalFromFreq(XTtcPs *InstancePtr, u32 Freq,
+ XInterval *Interval, u8 *Prescaler)
+{
+ u8 TmpPrescaler;
+ UINTPTR TempValue;
+ u32 InputClock;
+
+ /*
+ * Assert to validate input arguments.
+ */
+ Xil_AssertVoid(InstancePtr != NULL);
+ Xil_AssertVoid(Freq > 0U);
+
+ InputClock = InstancePtr->Config.InputClockHz;
+ /*
+ * Find the smallest prescaler that will work for a given frequency. The
+ * smaller the prescaler, the larger the count and the more accurate the
+ * PWM setting.
+ */
+ TempValue = InputClock/ Freq;
+
+ if (TempValue < 4U) {
+ /*
+ * The frequency is too high, it is too close to the input
+ * clock value. Use maximum values to signal caller.
+ */
+ *Interval = XTTCPS_MAX_INTERVAL_COUNT;
+ *Prescaler = 0xFFU;
+ return;
+ }
+
+ /*
+ * First, do we need a prescaler or not?
+ */
+ if (((UINTPTR)XTTCPS_MAX_INTERVAL_COUNT) > TempValue) {
+ /*
+ * We do not need a prescaler, so set the values appropriately
+ */
+ *Interval = (XInterval)TempValue;
+ *Prescaler = XTTCPS_CLK_CNTRL_PS_DISABLE;
+ return;
+ }
+
+
+ for (TmpPrescaler = 0U; TmpPrescaler < XTTCPS_CLK_CNTRL_PS_DISABLE;
+ TmpPrescaler++) {
+ TempValue = InputClock/ (Freq * (1U << (TmpPrescaler + 1U)));
+
+ /*
+ * The first value less than 2^16 is the best bet
+ */
+ if (((UINTPTR)XTTCPS_MAX_INTERVAL_COUNT) > TempValue) {
+ /*
+ * Set the values appropriately
+ */
+ *Interval = (XInterval)TempValue;
+ *Prescaler = TmpPrescaler;
+ return;
+ }
+ }
+
+ /* Can not find interval values that work for the given frequency.
+ * Return maximum values to signal caller.
+ */
+ *Interval = XTTCPS_MAX_INTERVAL_COUNT;
+ *Prescaler = 0XFFU;
+ return;
+}
+
+/*****************************************************************************/
+/**
+ *
+ * Handles interrupts by resetting the counter value
+ * and clearing the status register
+ *
+ * @param InstancePtr is a pointer to the XTtcPs instance.
+ *
+ * @return
+ * - XST_SUCCESS if successful.
+ *
+ * @note None.
+ *
+ ******************************************************************************/
+
+u32 XTtcPs_InterruptHandler(XTtcPs *InstancePtr)
+{
+ u32 XTtcPsStatusReg;
+
+ Xil_AssertNonvoid(InstancePtr != NULL);
+
+ XTtcPsStatusReg = XTtcPs_GetInterruptStatus(InstancePtr);
+ XTtcPs_ClearInterruptStatus(InstancePtr, XTtcPsStatusReg);
+ InstancePtr->StatusHandler(InstancePtr->StatusRef,
+ XTtcPsStatusReg);
+ return XST_SUCCESS;
+
+
+
+}
+
+/*****************************************************************************/
+/**
+ *
+ * Sets the status callback function, the status handler, which the driver
+ * calls when it encounters conditions that should be reported to upper
+ * layer software. The handler executes in an interrupt context, so it must
+ * minimize the amount of processing performed. One of the following status
+ * events is passed to the status handler.
+ *
+ * </pre>
+ * @param InstancePtr is a pointer to the XTtcPs instance.
+ * @param CallBackRef is the upper layer callback reference passed back
+ * when the callback function is invoked.
+ * @param FuncPointer is the pointer to the callback function.
+ *
+ * @return None.
+ *
+ * @note
+ *
+ * The handler is called within interrupt context, so it should do its work
+ * quickly and queue potentially time-consuming work to a task-level thread.
+ *
+ ******************************************************************************/
+void XTtcPs_SetStatusHandler(XTtcPs *InstancePtr, void *CallBackRef,
+ XTtcPs_StatusHandler FuncPointer)
+{
+ Xil_AssertVoid(InstancePtr != NULL);
+ Xil_AssertVoid(FuncPointer != NULL);
+ Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+ InstancePtr->StatusHandler = FuncPointer;
+ InstancePtr->StatusRef = CallBackRef;
+}
+
+
+/*****************************************************************************/
+/**
+ *
+ * This is a stub for the status callback. The stub is here in case the upper
+ * layers forget to set the handler.
+ *
+ * @param CallBackRef is a pointer to the upper layer callback reference
+ * @param StatusEvent is the event that just occurred.
+ *
+ * @return None.
+ *
+ * @note None.
+ *
+ ******************************************************************************/
+static void StubStatusHandler(const void *CallBackRef, u32 StatusEvent)
+{
+ (const void) CallBackRef;
+ (void) StatusEvent;
+
+ Xil_AssertVoidAlways();
+}
+/** @} */
diff --git a/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/ttcps_v3_10/src/xttcps.h b/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/ttcps_v3_10/src/xttcps.h
new file mode 100644
index 0000000..67969ba
--- /dev/null
+++ b/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/ttcps_v3_10/src/xttcps.h
@@ -0,0 +1,536 @@
+/******************************************************************************
+*
+* Copyright (C) 2010 - 2019 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+* THE SOFTWARE.
+*
+*
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xttcps.h
+* @addtogroup ttcps_v3_10
+* @{
+* @details
+*
+* This is the driver for one 16-bit timer counter in the Triple Timer Counter
+* (TTC) module in the Ps block.
+*
+* The TTC module provides three independent timer/counter modules that can each
+* be clocked using either the system clock (pclk) or an externally driven
+* clock (ext_clk). In addition, each counter can independently prescale its
+* selected clock input (divided by 2 to 65536). Counters can be set to
+* decrement or increment.
+*
+* Each of the counters can be programmed to generate interrupt pulses:
+* . At a regular, predefined period, that is on a timed interval
+* . When the counter registers overflow
+* . When the count matches any one of the three 'match' registers
+*
+* Therefore, up to six different events can trigger a timer interrupt: three
+* match interrupts, an overflow interrupt, an interval interrupt and an event
+* timer interrupt. Note that the overflow interrupt and the interval interrupt
+* are mutually exclusive.
+*
+* <b>Initialization & Configuration</b>
+*
+* An XTtcPs_Config structure is used to configure a driver instance.
+* Information in the XTtcPs_Config structure is the hardware properties
+* about the device.
+*
+* A driver instance is initialized through
+* XTtcPs_CfgInitialize(InstancePtr, CfgPtr, EffectiveAddr). Where CfgPtr
+* is a pointer to the XTtcPs_Config structure, it can be looked up statically
+* through XTtcPs_LookupConfig(DeviceID), or passed in by the caller. The
+* EffectiveAddr can be the static base address of the device or virtual
+* mapped address if address translation is supported.
+*
+* <b>Interrupts</b>
+*
+* Interrupt handler is not provided by the driver, as handling of interrupt
+* is application specific.
+*
+* <b>stack usage(in bytes)</b>
+*
+* XTtcPs_LookupConfig : 32
+* XTtcPs_CfgInitialize : 80
+* XTtcPs_SetMatchValue : 32
+* XTtcPs_GetMatchValue : 48
+* XTtcPs_SetPrescaler : 48
+* XTtcPs_GetPrescaler : 48
+* XTtcPs_CalcIntervalFromFreq : 48
+* XTtcPs_SetOptions : 48
+* XTtcPs_GetOptions : 48
+* XTtcPs_SelfTest : 48
+* XTtcPs_InterruptHandler : 48
+* XTtcPs_SetStatusHandler : 48
+*
+* <b>Memory foot-print(in bytes)</b>
+*
+* XTtcPs_LookupConfig : 72
+* XTtcPs_CfgInitialize : 304
+* XTtcPs_SetMatchValue : 168
+* XTtcPs_GetMatchValue : 176
+* XTtcPs_SetPrescaler : 172
+* XTtcPs_GetPrescaler : 152
+* XTtcPs_CalcIntervalFromFreq : 228
+* XTtcPs_SetOptions : 424
+* XTtcPs_GetOptions : 200
+* XTtcPs_SelfTest : 148
+* XTtcPs_InterruptHandler : 88
+* XTtcPs_SetStatusHandler : 140
+*
+* <b>Execution Time(in usec)</b>
+*
+* XTtcPs_LookupConfig : 8.31
+* TtcPs_CfgInitialize : 1.30
+* XTtcPs_SetMatchValue : 1.10
+* XTtcPs_GetMatchValue : 1.00
+* XTtcPs_SetPrescaler : 1.09
+* XTtcPs_GetPrescaler : 1.00
+* XTtcPs_CalcIntervalFromFreq : 1.29
+* XTtcPs_SetOptions: 1.91
+* XTtcPs_GetOptions: 2.55
+* XTtcPs_SelfTest: .85
+*
+* <b>Assumptions of Use</b>
+
+* 1.The default setting for a timer/counter is:
+* - Overflow Mode
+* - Internal clock (pclk) selected
+* - Counter disabled
+* - All Interrupts disabled
+* - Output waveforms disabled
+*
+* <b>Compiler Name</b>
+*
+* gcc
+*
+* <b>Compiler version</b>
+*
+* 8.2.0
+*
+* <b>Compiler options</b>
+*
+* -DARMR5 -Wall -O0 -g3 -c -fmessage-length=0 -MT"$@" -mcpu=cortex-r5 -mfloat-abi=hard -mfpu=vfpv3-d16 -I<include_path>
+* -Wall -O0 -g3 -c -fmessage-length=0 -MT"$@" -mcpu=cortex-a72 -I<include_path>
+* -Wall -O0 -g3 -c -fmessage-length=0 -MT"$@" -I<include_path>
+*
+* <b>User Defined data types</b>
+*
+* u8 1 byte
+* u16 2 bytes
+* u32 4 bytes / 1 word
+* u64 8 bytes / double word
+*
+*
+* <pre>
+* MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ----- ------ -------- -----------------------------------------------------
+* 1.00a drg/jz 01/20/10 First release..
+* 2.0 adk 12/10/13 Updated as per the New Tcl API's
+* 3.0 pkp 12/09/14 Added support for Zynq Ultrascale Mp.Also code
+* modified for MISRA-C:2012 compliance.
+* 3.2 mus 10/28/16 Modified XTtcPs_GetCounterValue and XTtcPs_SetInterval
+* macros to return 32 bit values for zynq ultrascale+mpsoc
+* ms 01/23/17 Modified xil_printf statement in main function for all
+* examples to ensure that "Successfully ran" and "Failed"
+* strings are available in all examples. This is a fix
+* for CR-965028.
+* ms 03/17/17 Added readme.txt file in examples folder for doxygen
+* generation.
+* 3.4 ms 04/18/17 Modified tcl file to add suffix U for all macros
+* definitions of ttcps in xparameters.h
+* 3.5 srm 10/06/17 Added new typedef XMatchRegValue for match register width
+* 3.8 aru 12/19/18 Modified in XTtcPs_ClearInterruptStatus function to clear
+* Interrupt status register by reading instead of writing it.
+* </pre>
+*
+******************************************************************************/
+
+#ifndef XTTCPS_H /* prevent circular inclusions */
+#define XTTCPS_H /* by using protection macros */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/***************************** Include Files *********************************/
+
+#include "xttcps_hw.h"
+#include "xstatus.h"
+
+/*****************************************************************************/
+typedef void (*XTtcPs_StatusHandler) (const void *CallBackRef, u32 StatusEvent);
+
+
+/************************** Constant Definitions *****************************/
+
+
+/*
+ * Maximum Value for interval counter
+ */
+ #if defined(ARMA9)
+ #define XTTCPS_MAX_INTERVAL_COUNT 0xFFFFU
+ #else
+ #define XTTCPS_MAX_INTERVAL_COUNT 0xFFFFFFFFU
+ #endif
+
+/** @name Configuration options
+ *
+ * Options for the device. Each of the options is bit field, so more than one
+ * options can be specified.
+ *
+ * @{
+ */
+#define XTTCPS_OPTION_EXTERNAL_CLK 0x00000001U /**< External clock source */
+#define XTTCPS_OPTION_CLK_EDGE_NEG 0x00000002U /**< Clock on trailing edge for
+ external clock*/
+#define XTTCPS_OPTION_INTERVAL_MODE 0x00000004U /**< Interval mode */
+#define XTTCPS_OPTION_DECREMENT 0x00000008U /**< Decrement the counter */
+#define XTTCPS_OPTION_MATCH_MODE 0x00000010U /**< Match mode */
+#define XTTCPS_OPTION_WAVE_DISABLE 0x00000020U /**< No waveform output */
+#define XTTCPS_OPTION_WAVE_POLARITY 0x00000040U /**< Waveform polarity */
+/*@}*/
+/**************************** Type Definitions *******************************/
+
+/**
+ * This typedef contains configuration information for the device.
+ */
+typedef struct {
+ u16 DeviceId; /**< Unique ID for device */
+ u32 BaseAddress; /**< Base address for device */
+ u32 InputClockHz; /**< Input clock frequency */
+} XTtcPs_Config;
+
+/**
+ * The XTtcPs driver instance data. The user is required to allocate a
+ * variable of this type for each PS timer/counter device in the system. A
+ * pointer to a variable of this type is then passed to various driver API
+ * functions.
+ */
+typedef struct {
+ XTtcPs_Config Config; /**< Configuration structure */
+ u32 IsReady; /**< Device is initialized and ready */
+ XTtcPs_StatusHandler StatusHandler;
+ void *StatusRef; /**< Callback reference for status handler */
+} XTtcPs;
+
+/**
+ * This typedef contains interval count and Match register value
+ */
+#if defined(ARMA9)
+typedef u16 XInterval;
+typedef u16 XMatchRegValue;
+#else
+typedef u32 XInterval;
+typedef u32 XMatchRegValue;
+#endif
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/*
+ * Internal helper macros
+ */
+#define InstReadReg(InstancePtr, RegOffset) \
+ (Xil_In32(((InstancePtr)->Config.BaseAddress) + (u32)(RegOffset)))
+
+#define InstWriteReg(InstancePtr, RegOffset, Data) \
+ (Xil_Out32(((InstancePtr)->Config.BaseAddress) + (u32)(RegOffset), (u32)(Data)))
+
+/*****************************************************************************/
+/**
+*
+* This function starts the counter/timer without resetting the counter value.
+*
+* @param InstancePtr is a pointer to the XTtcPs instance.
+*
+* @return None
+*
+* @note C-style signature:
+* void XTtcPs_Start(XTtcPs *InstancePtr)
+*
+****************************************************************************/
+#define XTtcPs_Start(InstancePtr) \
+ InstWriteReg((InstancePtr), XTTCPS_CNT_CNTRL_OFFSET, \
+ (InstReadReg((InstancePtr), XTTCPS_CNT_CNTRL_OFFSET) & \
+ ~XTTCPS_CNT_CNTRL_DIS_MASK))
+
+/*****************************************************************************/
+/**
+*
+* This function stops the counter/timer. This macro may be called at any time
+* to stop the counter. The counter holds the last value until it is reset,
+* restarted or enabled.
+*
+* @param InstancePtr is a pointer to the XTtcPs instance.
+*
+* @return None
+*
+* @note C-style signature:
+* void XTtcPs_Stop(XTtcPs *InstancePtr)
+*
+****************************************************************************/
+#define XTtcPs_Stop(InstancePtr) \
+ InstWriteReg((InstancePtr), XTTCPS_CNT_CNTRL_OFFSET, \
+ (InstReadReg((InstancePtr), XTTCPS_CNT_CNTRL_OFFSET) | \
+ XTTCPS_CNT_CNTRL_DIS_MASK))
+
+/*****************************************************************************/
+/**
+*
+* This function checks whether the timer counter has already started.
+*
+* @param InstancePtr is a pointer to the XTtcPs instance
+*
+* @return Non-zero if the device has started, '0' otherwise.
+*
+* @note C-style signature:
+* int XTtcPs_IsStarted(XTtcPs *InstancePtr)
+*
+****************************************************************************/
+#define XTtcPs_IsStarted(InstancePtr) \
+ ((InstReadReg((InstancePtr), XTTCPS_CNT_CNTRL_OFFSET) & \
+ XTTCPS_CNT_CNTRL_DIS_MASK) == 0U)
+
+/*****************************************************************************/
+/**
+*
+* This function returns the current 16-bit counter value. It may be called at
+* any time.
+*
+* @param InstancePtr is a pointer to the XTtcPs instance.
+*
+* @return zynq:16 bit counter value.
+* zynq ultrascale+mpsoc:32 bit counter value.
+*
+* @note C-style signature:
+* zynq: u16 XTtcPs_GetCounterValue(XTtcPs *InstancePtr)
+* zynq ultrascale+mpsoc: u32 XTtcPs_GetCounterValue(XTtcPs *InstancePtr)
+*
+****************************************************************************/
+#if defined(ARMA9)
+/*
+ * ttc supports 16 bit counter for zynq
+ */
+#define XTtcPs_GetCounterValue(InstancePtr) \
+ (u16)InstReadReg((InstancePtr), XTTCPS_COUNT_VALUE_OFFSET)
+#else
+/*
+ * ttc supports 32 bit counter for zynq ultrascale+mpsoc
+ */
+#define XTtcPs_GetCounterValue(InstancePtr) \
+ InstReadReg((InstancePtr), XTTCPS_COUNT_VALUE_OFFSET)
+#endif
+
+/*****************************************************************************/
+/**
+*
+* This function sets the interval value to be used in interval mode.
+*
+* @param InstancePtr is a pointer to the XTtcPs instance.
+* @param Value is the 16-bit value to be set in the interval register.
+*
+* @return None
+*
+* @note C-style signature:
+* void XTtcPs_SetInterval(XTtcPs *InstancePtr, XInterval Value)
+*
+****************************************************************************/
+#define XTtcPs_SetInterval(InstancePtr, Value) \
+ InstWriteReg((InstancePtr), XTTCPS_INTERVAL_VAL_OFFSET, (Value))
+
+/*****************************************************************************/
+/**
+*
+* This function gets the interval value from the interval register.
+*
+* @param InstancePtr is a pointer to the XTtcPs instance.
+*
+* @return zynq:16 bit interval value.
+* zynq ultrascale+mpsoc:32 bit interval value.
+*
+* @note C-style signature:
+* zynq: u16 XTtcPs_GetInterval(XTtcPs *InstancePtr)
+* zynq ultrascale+mpsoc: u32 XTtcPs_GetInterval(XTtcPs *InstancePtr)
+*
+****************************************************************************/
+#if defined(ARMA9)
+/*
+ * ttc supports 16 bit interval counter for zynq
+ */
+#define XTtcPs_GetInterval(InstancePtr) \
+ (u16)InstReadReg((InstancePtr), XTTCPS_INTERVAL_VAL_OFFSET)
+#else
+/*
+ * ttc supports 32 bit interval counter for zynq ultrascale+mpsoc
+ */
+#define XTtcPs_GetInterval(InstancePtr) \
+ InstReadReg((InstancePtr), XTTCPS_INTERVAL_VAL_OFFSET)
+#endif
+/*****************************************************************************/
+/**
+*
+* This macro resets the count register. It may be called at any time. The
+* counter is reset to either 0 or 0xFFFF, or the interval value, depending on
+* the increment/decrement mode. The state of the counter, as started or
+* stopped, is not affected by calling reset.
+*
+* @param InstancePtr is a pointer to the XTtcPs instance.
+*
+* @return None
+*
+* @note C-style signature:
+* void XTtcPs_ResetCounterValue(XTtcPs *InstancePtr)
+*
+****************************************************************************/
+#define XTtcPs_ResetCounterValue(InstancePtr) \
+ InstWriteReg((InstancePtr), XTTCPS_CNT_CNTRL_OFFSET, \
+ (InstReadReg((InstancePtr), XTTCPS_CNT_CNTRL_OFFSET) | \
+ (u32)XTTCPS_CNT_CNTRL_RST_MASK))
+
+/*****************************************************************************/
+/**
+*
+* This function enables the interrupts.
+*
+* @param InstancePtr is a pointer to the XTtcPs instance.
+* @param InterruptMask defines which interrupt should be enabled.
+* Constants are defined in xttcps_hw.h as XTTCPS_IXR_*.
+* This is a bit mask, all set bits will be enabled, cleared bits
+* will not be disabled.
+*
+* @return None.
+*
+* @note
+* C-style signature:
+* void XTtcPs_EnableInterrupts(XTtcPs *InstancePtr, u32 InterruptMask)
+*
+******************************************************************************/
+#define XTtcPs_EnableInterrupts(InstancePtr, InterruptMask) \
+ InstWriteReg((InstancePtr), XTTCPS_IER_OFFSET, \
+ (InstReadReg((InstancePtr), XTTCPS_IER_OFFSET) | \
+ (InterruptMask)))
+
+/*****************************************************************************/
+/**
+*
+* This function disables the interrupts.
+*
+* @param InstancePtr is a pointer to the XTtcPs instance.
+* @param InterruptMask defines which interrupt should be disabled.
+* Constants are defined in xttcps_hw.h as XTTCPS_IXR_*.
+* This is a bit mask, all set bits will be disabled, cleared bits
+* will not be disabled.
+*
+* @return None.
+*
+* @note
+* C-style signature:
+* void XTtcPs_DisableInterrupts(XTtcPs *InstancePtr, u32 InterruptMask)
+*
+******************************************************************************/
+#define XTtcPs_DisableInterrupts(InstancePtr, InterruptMask) \
+ InstWriteReg((InstancePtr), XTTCPS_IER_OFFSET, \
+ (InstReadReg((InstancePtr), XTTCPS_IER_OFFSET) & \
+ ~(InterruptMask)))
+
+/*****************************************************************************/
+/**
+*
+* This function reads the interrupt status.
+*
+* @param InstancePtr is a pointer to the XTtcPs instance.
+*
+* @return None.
+*
+* @note C-style signature:
+* u32 XTtcPs_GetInterruptStatus(XTtcPs *InstancePtr)
+*
+******************************************************************************/
+#define XTtcPs_GetInterruptStatus(InstancePtr) \
+ InstReadReg((InstancePtr), XTTCPS_ISR_OFFSET)
+
+/*****************************************************************************/
+/**
+*
+* This function clears the interrupt status.
+*
+* @param InstancePtr is a pointer to the XTtcPs instance.
+* @param InterruptMask defines which interrupt should be cleared.
+* Constants are defined in xttcps_hw.h as XTTCPS_IXR_*.
+* This is a bit mask, all set bits will be cleared, cleared bits
+* will not be cleared.
+*
+* @return None.
+*
+* @note
+* C-style signature:
+* void XTtcPs_ClearInterruptStatus(XTtcPs *InstancePtr, u32 InterruptMask)
+*
+******************************************************************************/
+#define XTtcPs_ClearInterruptStatus(InstancePtr, InterruptMask) \
+ InstReadReg((InstancePtr), XTTCPS_ISR_OFFSET)
+
+
+/************************** Function Prototypes ******************************/
+
+/*
+ * Initialization functions in xttcps_sinit.c
+ */
+XTtcPs_Config *XTtcPs_LookupConfig(u16 DeviceId);
+
+/*
+ * Required functions, in xttcps.c
+ */
+s32 XTtcPs_CfgInitialize(XTtcPs *InstancePtr,
+ XTtcPs_Config * ConfigPtr, u32 EffectiveAddr);
+
+void XTtcPs_SetMatchValue(XTtcPs *InstancePtr, u8 MatchIndex, XMatchRegValue Value);
+XMatchRegValue XTtcPs_GetMatchValue(XTtcPs *InstancePtr, u8 MatchIndex);
+
+void XTtcPs_SetPrescaler(XTtcPs *InstancePtr, u8 PrescalerValue);
+u8 XTtcPs_GetPrescaler(XTtcPs *InstancePtr);
+
+void XTtcPs_CalcIntervalFromFreq(XTtcPs *InstancePtr, u32 Freq,
+ XInterval *Interval, u8 *Prescaler);
+
+/*
+ * Functions for options, in file xttcps_options.c
+ */
+s32 XTtcPs_SetOptions(XTtcPs *InstancePtr, u32 Options);
+u32 XTtcPs_GetOptions(XTtcPs *InstancePtr);
+
+/*
+ * Function for self-test, in file xttcps_selftest.c
+ */
+s32 XTtcPs_SelfTest(XTtcPs *InstancePtr);
+u32 XTtcPs_InterruptHandler(XTtcPs *InstancePtr);
+void XTtcPs_SetStatusHandler(XTtcPs *InstancePtr, void *CallBackRef,
+ XTtcPs_StatusHandler FuncPointer);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* end of protection macro */
+/** @} */
diff --git a/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/ttcps_v3_10/src/xttcps_g.c b/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/ttcps_v3_10/src/xttcps_g.c
new file mode 100644
index 0000000..ae2a0a0
--- /dev/null
+++ b/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/ttcps_v3_10/src/xttcps_g.c
@@ -0,0 +1,58 @@
+
+/*******************************************************************
+*
+* CAUTION: This file is automatically generated by HSI.
+* Version: 2019.2
+* DO NOT EDIT.
+*
+* Copyright (C) 2010-2021 Xilinx, Inc. All Rights Reserved.*
+*Permission is hereby granted, free of charge, to any person obtaining a copy
+*of this software and associated documentation files (the Software), to deal
+*in the Software without restriction, including without limitation the rights
+*to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+*copies of the Software, and to permit persons to whom the Software is
+*furnished to do so, subject to the following conditions:
+*
+*The above copyright notice and this permission notice shall be included in
+*all copies or substantial portions of the Software.
+*
+*THE SOFTWARE IS PROVIDED AS IS, WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+*IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+*FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+*THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+*WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT
+*OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+*
+
+*
+* Description: Driver configuration
+*
+*******************************************************************/
+
+#include "xparameters.h"
+#include "xttcps.h"
+
+/*
+* The configuration table for devices
+*/
+
+XTtcPs_Config XTtcPs_ConfigTable[] =
+{
+ {
+ XPAR_PS7_TTC_0_DEVICE_ID,
+ XPAR_PS7_TTC_0_BASEADDR,
+ XPAR_PS7_TTC_0_TTC_CLK_FREQ_HZ
+ },
+ {
+ XPAR_PS7_TTC_1_DEVICE_ID,
+ XPAR_PS7_TTC_1_BASEADDR,
+ XPAR_PS7_TTC_1_TTC_CLK_FREQ_HZ
+ },
+ {
+ XPAR_PS7_TTC_2_DEVICE_ID,
+ XPAR_PS7_TTC_2_BASEADDR,
+ XPAR_PS7_TTC_2_TTC_CLK_FREQ_HZ
+ }
+};
+
+
diff --git a/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/ttcps_v3_10/src/xttcps_hw.h b/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/ttcps_v3_10/src/xttcps_hw.h
new file mode 100644
index 0000000..f07527d
--- /dev/null
+++ b/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/ttcps_v3_10/src/xttcps_hw.h
@@ -0,0 +1,227 @@
+/******************************************************************************
+*
+* Copyright (C) 2010 - 2019 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+* THE SOFTWARE.
+*
+*
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xttcps_hw.h
+* @addtogroup ttcps_v3_10
+* @{
+*
+* This file defines the hardware interface to one of the three timer counters
+* in the Ps block.
+*
+*
+* <pre>
+* MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ----- ------ -------- -------------------------------------------------
+* 1.00a drg/jz 01/21/10 First release
+* 3.00 kvn 02/13/15 Modified code for MISRA-C:2012 compliance.
+* 3.5 srm 10/06/17 Updated XTTCPS_COUNT_VALUE_MASK,
+* XTTCPS_INTERVAL_VAL_MASK, XTTCPS_MATCH_MASK macros to
+* mask 16 bit values for zynq and 32 bit values for
+* zynq ultrascale+mpsoc "
+* </pre>
+*
+******************************************************************************/
+
+#ifndef XTTCPS_HW_H /* prevent circular inclusions */
+#define XTTCPS_HW_H /* by using protection macros */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/***************************** Include Files *********************************/
+
+#include "xil_types.h"
+#include "xil_assert.h"
+#include "xil_io.h"
+
+/************************** Constant Definitions *****************************/
+/*
+ * Flag for a9 processor
+ */
+ #if !defined (ARMR5) && !defined (__aarch64__) && !defined (ARMA53_32)
+ #define ARMA9
+ #endif
+
+/** @name Register Map
+ *
+ * Register offsets from the base address of the device.
+ *
+ * @{
+ */
+#define XTTCPS_CLK_CNTRL_OFFSET 0x00000000U /**< Clock Control Register */
+#define XTTCPS_CNT_CNTRL_OFFSET 0x0000000CU /**< Counter Control Register*/
+#define XTTCPS_COUNT_VALUE_OFFSET 0x00000018U /**< Current Counter Value */
+#define XTTCPS_INTERVAL_VAL_OFFSET 0x00000024U /**< Interval Count Value */
+#define XTTCPS_MATCH_0_OFFSET 0x00000030U /**< Match 1 value */
+#define XTTCPS_MATCH_1_OFFSET 0x0000003CU /**< Match 2 value */
+#define XTTCPS_MATCH_2_OFFSET 0x00000048U /**< Match 3 value */
+#define XTTCPS_ISR_OFFSET 0x00000054U /**< Interrupt Status Register */
+#define XTTCPS_IER_OFFSET 0x00000060U /**< Interrupt Enable Register */
+/* @} */
+
+/** @name Clock Control Register
+ * Clock Control Register definitions
+ * @{
+ */
+#define XTTCPS_CLK_CNTRL_PS_EN_MASK 0x00000001U /**< Prescale enable */
+#define XTTCPS_CLK_CNTRL_PS_VAL_MASK 0x0000001EU /**< Prescale value */
+#define XTTCPS_CLK_CNTRL_PS_VAL_SHIFT 1U /**< Prescale shift */
+#define XTTCPS_CLK_CNTRL_PS_DISABLE 16U /**< Prescale disable */
+#define XTTCPS_CLK_CNTRL_SRC_MASK 0x00000020U /**< Clock source */
+#define XTTCPS_CLK_CNTRL_EXT_EDGE_MASK 0x00000040U /**< External Clock edge */
+/* @} */
+
+/** @name Counter Control Register
+ * Counter Control Register definitions
+ * @{
+ */
+#define XTTCPS_CNT_CNTRL_DIS_MASK 0x00000001U /**< Disable the counter */
+#define XTTCPS_CNT_CNTRL_INT_MASK 0x00000002U /**< Interval mode */
+#define XTTCPS_CNT_CNTRL_DECR_MASK 0x00000004U /**< Decrement mode */
+#define XTTCPS_CNT_CNTRL_MATCH_MASK 0x00000008U /**< Match mode */
+#define XTTCPS_CNT_CNTRL_RST_MASK 0x00000010U /**< Reset counter */
+#define XTTCPS_CNT_CNTRL_EN_WAVE_MASK 0x00000020U /**< Enable waveform */
+#define XTTCPS_CNT_CNTRL_POL_WAVE_MASK 0x00000040U /**< Waveform polarity */
+#define XTTCPS_CNT_CNTRL_RESET_VALUE 0x00000021U /**< Reset value */
+/* @} */
+
+/** @name Current Counter Value Register
+ * Current Counter Value Register definitions
+ * @{
+ */
+#if defined(ARMA9)
+#define XTTCPS_COUNT_VALUE_MASK 0x0000FFFFU /**< 16-bit counter value */
+#else
+#define XTTCPS_COUNT_VALUE_MASK 0xFFFFFFFFU /**< 32-bit counter value */
+#endif
+/* @} */
+
+/** @name Interval Value Register
+ * Interval Value Register is the maximum value the counter will count up or
+ * down to.
+ * @{
+ */
+#if defined(ARMA9)
+#define XTTCPS_INTERVAL_VAL_MASK 0x0000FFFFU /**< 16-bit Interval value*/
+#else
+#define XTTCPS_INTERVAL_VAL_MASK 0xFFFFFFFFU /**< 32-bit Interval value*/
+#endif
+/* @} */
+
+/** @name Match Registers
+ * Definitions for Match registers, each timer counter has three match
+ * registers.
+ * @{
+ */
+#if defined(ARMA9)
+#define XTTCPS_MATCH_MASK 0x0000FFFFU /**< 16-bit Match value */
+#else
+#define XTTCPS_MATCH_MASK 0xFFFFFFFFU /**< 32-bit Match value */
+#endif
+#define XTTCPS_NUM_MATCH_REG 3U /**< Num of Match reg */
+/* @} */
+
+/** @name Interrupt Registers
+ * Following register bit mask is for all interrupt registers.
+ *
+ * @{
+ */
+#define XTTCPS_IXR_INTERVAL_MASK 0x00000001U /**< Interval Interrupt */
+#define XTTCPS_IXR_MATCH_0_MASK 0x00000002U /**< Match 1 Interrupt */
+#define XTTCPS_IXR_MATCH_1_MASK 0x00000004U /**< Match 2 Interrupt */
+#define XTTCPS_IXR_MATCH_2_MASK 0x00000008U /**< Match 3 Interrupt */
+#define XTTCPS_IXR_CNT_OVR_MASK 0x00000010U /**< Counter Overflow */
+#define XTTCPS_IXR_ALL_MASK 0x0000001FU /**< All valid Interrupts */
+/* @} */
+
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/****************************************************************************/
+/**
+*
+* Read the given Timer Counter register.
+*
+* @param BaseAddress is the base address of the timer counter device.
+* @param RegOffset is the register offset to be read
+*
+* @return The 32-bit value of the register
+*
+* @note C-style signature:
+* u32 XTtcPs_ReadReg(u32 BaseAddress, u32 RegOffset)
+*
+*****************************************************************************/
+#define XTtcPs_ReadReg(BaseAddress, RegOffset) \
+ (Xil_In32((BaseAddress) + (u32)(RegOffset)))
+
+/****************************************************************************/
+/**
+*
+* Write the given Timer Counter register.
+*
+* @param BaseAddress is the base address of the timer counter device.
+* @param RegOffset is the register offset to be written
+* @param Data is the 32-bit value to write to the register
+*
+* @return None.
+*
+* @note C-style signature:
+* void XTtcPs_WriteReg(XTtcPs BaseAddress, u32 RegOffset,
+* u32 Data)
+*
+*****************************************************************************/
+#define XTtcPs_WriteReg(BaseAddress, RegOffset, Data) \
+ (Xil_Out32((BaseAddress) + (u32)(RegOffset), (u32)(Data)))
+
+/****************************************************************************/
+/**
+*
+* Calculate a match register offset using the Match Register index.
+*
+* @param MatchIndex is the 0-2 value of the match register
+*
+* @return MATCH_N_OFFSET.
+*
+* @note C-style signature:
+* u32 XTtcPs_Match_N_Offset(u8 MatchIndex)
+*
+*****************************************************************************/
+#define XTtcPs_Match_N_Offset(MatchIndex) \
+ ((u32)XTTCPS_MATCH_0_OFFSET + ((u32)(12U) * (u32)(MatchIndex)))
+
+/************************** Function Prototypes ******************************/
+
+/************************** Variable Definitions *****************************/
+#ifdef __cplusplus
+}
+#endif
+#endif /* end of protection macro */
+/** @} */
diff --git a/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/ttcps_v3_10/src/xttcps_options.c b/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/ttcps_v3_10/src/xttcps_options.c
new file mode 100644
index 0000000..2dbf11b
--- /dev/null
+++ b/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/ttcps_v3_10/src/xttcps_options.c
@@ -0,0 +1,212 @@
+/******************************************************************************
+*
+* Copyright (C) 2010 - 2019 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+* THE SOFTWARE.
+*
+*
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xttcps_options.c
+* @addtogroup ttcps_v3_10
+* @{
+*
+* This file contains functions to get or set option features for the device.
+*
+* <pre>
+* MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ----- ------ -------- ---------------------------------------------
+* 1.00a drg/jz 01/21/10 First release
+* 1.01a nm 03/05/2012 Removed break statement after return to remove
+* compilation warnings.
+* 3.00 kvn 02/13/15 Modified code for MISRA-C:2012 compliance.
+* 3.10 aru 05/16/19 Removed the redudant code from XTtcPs_SetOptions().
+* </pre>
+*
+******************************************************************************/
+
+/***************************** Include Files *********************************/
+
+#include "xttcps.h"
+
+/************************** Constant Definitions *****************************/
+
+
+/**************************** Type Definitions *******************************/
+
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+
+/************************** Function Prototypes ******************************/
+
+
+/************************** Variable Definitions *****************************/
+
+/*
+ * Create the table of options which are processed to get/set the device
+ * options. These options are table driven to allow easy maintenance and
+ * expansion of the options.
+ */
+typedef struct {
+ u32 Option;
+ u32 Mask;
+ u32 Register;
+} OptionsMap;
+
+static OptionsMap TmrCtrOptionsTable[] = {
+ {XTTCPS_OPTION_EXTERNAL_CLK, XTTCPS_CLK_CNTRL_SRC_MASK,
+ XTTCPS_CLK_CNTRL_OFFSET},
+ {XTTCPS_OPTION_CLK_EDGE_NEG, XTTCPS_CLK_CNTRL_EXT_EDGE_MASK,
+ XTTCPS_CLK_CNTRL_OFFSET},
+ {XTTCPS_OPTION_INTERVAL_MODE, XTTCPS_CNT_CNTRL_INT_MASK,
+ XTTCPS_CNT_CNTRL_OFFSET},
+ {XTTCPS_OPTION_DECREMENT, XTTCPS_CNT_CNTRL_DECR_MASK,
+ XTTCPS_CNT_CNTRL_OFFSET},
+ {XTTCPS_OPTION_MATCH_MODE, XTTCPS_CNT_CNTRL_MATCH_MASK,
+ XTTCPS_CNT_CNTRL_OFFSET},
+ {XTTCPS_OPTION_WAVE_DISABLE, XTTCPS_CNT_CNTRL_EN_WAVE_MASK,
+ XTTCPS_CNT_CNTRL_OFFSET},
+ {XTTCPS_OPTION_WAVE_POLARITY, XTTCPS_CNT_CNTRL_POL_WAVE_MASK,
+ XTTCPS_CNT_CNTRL_OFFSET},
+};
+
+#define XTTCPS_NUM_TMRCTR_OPTIONS (sizeof(TmrCtrOptionsTable) / \
+ sizeof(OptionsMap))
+
+/*****************************************************************************/
+/**
+*
+* This function sets the options for the TTC device.
+*
+* @param InstancePtr is a pointer to the XTtcPs instance.
+* @param Options contains the specified options to be set. This is a bit
+* mask where a 1 means to turn the option on, and a 0 means to
+* turn the option off. One or more bit values may be contained
+* in the mask. See the bit definitions named XTTCPS_*_OPTION in
+* the file xttcps.h.
+*
+* @return
+* - XST_SUCCESS if options are successfully set.
+* - XST_FAILURE if any of the options are unknown.
+*
+* @note None
+*
+******************************************************************************/
+s32 XTtcPs_SetOptions(XTtcPs *InstancePtr, u32 Options)
+{
+ u32 CountReg;
+ u32 ClockReg;
+ u32 Index;
+ s32 Status = XST_SUCCESS;
+
+ Xil_AssertNonvoid(InstancePtr != NULL);
+ Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+ ClockReg = XTtcPs_ReadReg(InstancePtr->Config.BaseAddress,
+ XTTCPS_CLK_CNTRL_OFFSET);
+ CountReg = XTtcPs_ReadReg(InstancePtr->Config.BaseAddress,
+ XTTCPS_CNT_CNTRL_OFFSET);
+
+ /*
+ * Loop through the options table, turning the option on or off
+ * depending on whether the bit is set in the incoming options flag.
+ */
+ for (Index = 0U; Index < XTTCPS_NUM_TMRCTR_OPTIONS; Index++) {
+ if ((Options & TmrCtrOptionsTable[Index].Option) != (u32)0) {
+ if(TmrCtrOptionsTable[Index].Register == XTTCPS_CLK_CNTRL_OFFSET) {
+ ClockReg |= TmrCtrOptionsTable[Index].Mask;
+ } else {
+ CountReg |= TmrCtrOptionsTable[Index].Mask;
+ }
+ } else {
+ if(TmrCtrOptionsTable[Index].Register == XTTCPS_CLK_CNTRL_OFFSET) {
+ ClockReg &= ~TmrCtrOptionsTable[Index].Mask;
+ } else {
+ CountReg &= ~TmrCtrOptionsTable[Index].Mask;
+ }
+ }
+ }
+
+ /*
+ * Now write the registers. Leave it to the upper layers to restart the
+ * device.
+ */
+ if (Status != (s32)XST_FAILURE ) {
+ XTtcPs_WriteReg(InstancePtr->Config.BaseAddress,
+ XTTCPS_CLK_CNTRL_OFFSET, ClockReg);
+ XTtcPs_WriteReg(InstancePtr->Config.BaseAddress,
+ XTTCPS_CNT_CNTRL_OFFSET, CountReg);
+ }
+
+ return Status;
+}
+
+/*****************************************************************************/
+/**
+*
+* This function gets the settings for the options for the TTC device.
+*
+* @param InstancePtr is a pointer to the XTtcPs instance.
+*
+* @return
+*
+* The return u32 contains the specified options that are set. This is a bit
+* mask where a '1' means the option is on, and a'0' means the option is off.
+* One or more bit values may be contained in the mask. See the bit definitions
+* named XTTCPS_*_OPTION in the file xttcps.h.
+*
+* @note None.
+*
+******************************************************************************/
+u32 XTtcPs_GetOptions(XTtcPs *InstancePtr)
+{
+ u32 OptionsFlag = 0U;
+ u32 Register;
+ u32 Index;
+
+ Xil_AssertNonvoid(InstancePtr != NULL);
+ Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+
+ /*
+ * Loop through the options table to determine which options are set
+ */
+ for (Index = 0U; Index < XTTCPS_NUM_TMRCTR_OPTIONS; Index++) {
+ /*
+ * Get the control register to determine which options are
+ * currently set.
+ */
+ Register = XTtcPs_ReadReg(InstancePtr->Config.BaseAddress,
+ TmrCtrOptionsTable[Index].
+ Register);
+
+ if ((Register & TmrCtrOptionsTable[Index].Mask) != (u32)0) {
+ OptionsFlag |= TmrCtrOptionsTable[Index].Option;
+ }
+ }
+
+ return OptionsFlag;
+}
+/** @} */
diff --git a/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/ttcps_v3_10/src/xttcps_selftest.c b/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/ttcps_v3_10/src/xttcps_selftest.c
new file mode 100644
index 0000000..ce124f2
--- /dev/null
+++ b/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/ttcps_v3_10/src/xttcps_selftest.c
@@ -0,0 +1,103 @@
+/******************************************************************************
+*
+* Copyright (C) 2010 - 2019 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+* THE SOFTWARE.
+*
+*
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xttcps_selftest.c
+* @addtogroup ttcps_v3_10
+* @{
+*
+* This file contains the implementation of self test function for the
+* XTtcPs driver.
+*
+* <pre>
+* MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ----- ------ -------- ---------------------------------------------
+* 1.00a drg/jz 01/21/10 First release
+* 3.00 kvn 02/13/15 Modified code for MISRA-C:2012 compliance.
+* </pre>
+*
+******************************************************************************/
+
+/***************************** Include Files *********************************/
+
+#include "xttcps.h"
+
+/************************** Constant Definitions *****************************/
+
+
+/**************************** Type Definitions *******************************/
+
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+
+/************************** Function Prototypes ******************************/
+
+
+/************************** Variable Definitions *****************************/
+
+
+/*****************************************************************************/
+/**
+*
+* Runs a self-test on the driver/device.
+*
+*
+* @param InstancePtr is a pointer to the XTtcPs instance.
+*
+* @return
+*
+* - XST_SUCCESS if successful
+* - XST_FAILURE indicates a register did not read or write correctly
+*
+* @note This test fails if it is not called right after initialization.
+*
+******************************************************************************/
+s32 XTtcPs_SelfTest(XTtcPs *InstancePtr)
+{
+ s32 Status;
+ u32 TempReg;
+
+ Xil_AssertNonvoid(InstancePtr != NULL);
+ Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+ /*
+ * All the TTC registers should be in their default state right now.
+ */
+ TempReg = XTtcPs_ReadReg(InstancePtr->Config.BaseAddress,
+ XTTCPS_CNT_CNTRL_OFFSET);
+ if (XTTCPS_CNT_CNTRL_RESET_VALUE != (u32)TempReg) {
+ Status = XST_FAILURE;
+ }
+ else {
+ Status = XST_SUCCESS;
+ }
+ return Status;
+}
+/** @} */
diff --git a/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/ttcps_v3_10/src/xttcps_sinit.c b/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/ttcps_v3_10/src/xttcps_sinit.c
new file mode 100644
index 0000000..4939061
--- /dev/null
+++ b/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/ttcps_v3_10/src/xttcps_sinit.c
@@ -0,0 +1,92 @@
+/******************************************************************************
+*
+* Copyright (C) 2010 - 2019 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+* THE SOFTWARE.
+*
+*
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xttcps_sinit.c
+* @addtogroup ttcps_v3_10
+* @{
+*
+* The implementation of the XTtcPs driver's static initialization functionality.
+*
+* <pre>
+* MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ----- ------ -------- ---------------------------------------------
+* 1.00a drg/jz 01/21/10 First release
+* 3.00 kvn 02/13/15 Modified code for MISRA-C:2012 compliance.
+* </pre>
+*
+******************************************************************************/
+
+/***************************** Include Files *********************************/
+
+#include "xttcps.h"
+#include "xparameters.h"
+
+/************************** Constant Definitions *****************************/
+
+/**************************** Type Definitions *******************************/
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/************************** Function Prototypes ******************************/
+
+/************************** Variable Definitions *****************************/
+extern XTtcPs_Config XTtcPs_ConfigTable[XPAR_XTTCPS_NUM_INSTANCES];
+
+/*****************************************************************************/
+/**
+*
+* Looks up the device configuration based on the unique device ID. A table
+* contains the configuration info for each device in the system.
+*
+* @param DeviceId contains the unique ID of the device
+*
+* @return
+*
+* A pointer to the configuration found or NULL if the specified device ID was
+* not found. See xttcps.h for the definition of XTtcPs_Config.
+*
+* @note None.
+*
+******************************************************************************/
+XTtcPs_Config *XTtcPs_LookupConfig(u16 DeviceId)
+{
+ XTtcPs_Config *CfgPtr = NULL;
+ u32 Index;
+
+ for (Index = 0U; Index < (u32)XPAR_XTTCPS_NUM_INSTANCES; Index++) {
+ if (XTtcPs_ConfigTable[Index].DeviceId == DeviceId) {
+ CfgPtr = &XTtcPs_ConfigTable[Index];
+ break;
+ }
+ }
+
+ return (XTtcPs_Config *)CfgPtr;
+}
+/** @} */
diff --git a/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/uartps_v3_8/src/Makefile b/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/uartps_v3_8/src/Makefile
new file mode 100644
index 0000000..88b1e62
--- /dev/null
+++ b/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/uartps_v3_8/src/Makefile
@@ -0,0 +1,40 @@
+COMPILER=
+ARCHIVER=
+CP=cp
+COMPILER_FLAGS=
+EXTRA_COMPILER_FLAGS=
+LIB=libxil.a
+
+CC_FLAGS = $(COMPILER_FLAGS)
+ECC_FLAGS = $(EXTRA_COMPILER_FLAGS)
+
+RELEASEDIR=../../../lib
+INCLUDEDIR=../../../include
+INCLUDES=-I./. -I${INCLUDEDIR}
+
+OUTS = *.o
+
+LIBSOURCES:=*.c
+INCLUDEFILES:=*.h
+
+OBJECTS = $(addsuffix .o, $(basename $(wildcard *.c)))
+
+libs: banner xuartps_libs clean
+
+%.o: %.c
+ ${COMPILER} $(CC_FLAGS) $(ECC_FLAGS) $(INCLUDES) -o $@ $<
+
+banner:
+ echo "Compiling uartps"
+
+xuartps_libs: ${OBJECTS}
+ $(ARCHIVER) -r ${RELEASEDIR}/${LIB} ${OBJECTS}
+
+.PHONY: include
+include: xuartps_includes
+
+xuartps_includes:
+ ${CP} ${INCLUDEFILES} ${INCLUDEDIR}
+
+clean:
+ rm -rf ${OBJECTS}
diff --git a/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/uartps_v3_8/src/xuartps.c b/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/uartps_v3_8/src/xuartps.c
new file mode 100644
index 0000000..a6b58bc
--- /dev/null
+++ b/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/uartps_v3_8/src/xuartps.c
@@ -0,0 +1,640 @@
+/******************************************************************************
+*
+* Copyright (C) 2010 - 2018 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+* THE SOFTWARE.
+*
+*
+*
+******************************************************************************/
+/****************************************************************************/
+/**
+*
+* @file xuartps.c
+* @addtogroup uartps_v3_8
+* @{
+*
+* This file contains the implementation of the interface functions for XUartPs
+* driver. Refer to the header file xuartps.h for more detailed information.
+*
+* <pre>
+* MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ----- ------ -------- ----------------------------------------------
+* 1.00 drg/jz 01/13/10 First Release
+* 2.2 hk 06/23/14 SW reset of RX and TX should be done when changing
+* baud rate. CR# 804281.
+* 3.00 kvn 02/13/15 Modified code for MISRA-C:2012 compliance.
+* 3.1 kvn 04/10/15 Modified code for latest RTL changes.
+* 3.5 NK 09/26/17 Fix the RX Buffer Overflow issue.
+* 3.7 aru 08/17/18 Resolved MISRA-C mandatory violations.(CR#1007755)
+* </pre>
+*
+*****************************************************************************/
+
+/***************************** Include Files ********************************/
+
+#include "xstatus.h"
+#include "xuartps.h"
+#include "xil_io.h"
+
+/************************** Constant Definitions ****************************/
+
+/* The following constant defines the amount of error that is allowed for
+ * a specified baud rate. This error is the difference between the actual
+ * baud rate that will be generated using the specified clock and the
+ * desired baud rate.
+ */
+#define XUARTPS_MAX_BAUD_ERROR_RATE 3U /* max % error allowed */
+
+/**************************** Type Definitions ******************************/
+
+
+/***************** Macros (Inline Functions) Definitions ********************/
+
+
+/************************** Function Prototypes *****************************/
+
+static void XUartPs_StubHandler(void *CallBackRef, u32 Event,
+ u32 ByteCount);
+
+u32 XUartPs_SendBuffer(XUartPs *InstancePtr);
+
+u32 XUartPs_ReceiveBuffer(XUartPs *InstancePtr);
+
+/************************** Variable Definitions ****************************/
+
+/****************************************************************************/
+/**
+*
+* Initializes a specific XUartPs instance such that it is ready to be used.
+* The data format of the device is setup for 8 data bits, 1 stop bit, and no
+* parity by default. The baud rate is set to a default value specified by
+* Config->DefaultBaudRate if set, otherwise it is set to 19.2K baud. The
+* receive FIFO threshold is set for 8 bytes. The default operating mode of the
+* driver is polled mode.
+*
+* @param InstancePtr is a pointer to the XUartPs instance.
+* @param Config is a reference to a structure containing information
+* about a specific XUartPs driver.
+* @param EffectiveAddr is the device base address in the virtual memory
+* address space. The caller is responsible for keeping the address
+* mapping from EffectiveAddr to the device physical base address
+* unchanged once this function is invoked. Unexpected errors may
+* occur if the address mapping changes after this function is
+* called. If address translation is not used, pass in the physical
+* address instead.
+*
+* @return
+*
+* - XST_SUCCESS if initialization was successful
+* - XST_UART_BAUD_ERROR if the baud rate is not possible because
+* the inputclock frequency is not divisible with an acceptable
+* amount of error
+*
+* @note
+*
+* The default configuration for the UART after initialization is:
+*
+* - 19,200 bps or XPAR_DFT_BAUDRATE if defined
+* - 8 data bits
+* - 1 stop bit
+* - no parity
+* - FIFO's are enabled with a receive threshold of 8 bytes
+* - The RX timeout is enabled with a timeout of 1 (4 char times)
+*
+* All interrupts are disabled.
+*
+*****************************************************************************/
+s32 XUartPs_CfgInitialize(XUartPs *InstancePtr,
+ XUartPs_Config * Config, u32 EffectiveAddr)
+{
+ s32 Status;
+ u32 ModeRegister;
+ u32 BaudRate;
+
+ /* Assert validates the input arguments */
+ Xil_AssertNonvoid(InstancePtr != NULL);
+ Xil_AssertNonvoid(Config != NULL);
+
+ /* Setup the driver instance using passed in parameters */
+ InstancePtr->Config.BaseAddress = EffectiveAddr;
+ InstancePtr->Config.InputClockHz = Config->InputClockHz;
+ InstancePtr->Config.ModemPinsConnected = Config->ModemPinsConnected;
+
+ /* Initialize other instance data to default values */
+ InstancePtr->Handler = (XUartPs_Handler)XUartPs_StubHandler;
+
+ InstancePtr->SendBuffer.NextBytePtr = NULL;
+ InstancePtr->SendBuffer.RemainingBytes = 0U;
+ InstancePtr->SendBuffer.RequestedBytes = 0U;
+
+ InstancePtr->ReceiveBuffer.NextBytePtr = NULL;
+ InstancePtr->ReceiveBuffer.RemainingBytes = 0U;
+ InstancePtr->ReceiveBuffer.RequestedBytes = 0U;
+
+ /* Initialize the platform data */
+ InstancePtr->Platform = XGetPlatform_Info();
+
+ InstancePtr->is_rxbs_error = 0U;
+
+ /* Flag that the driver instance is ready to use */
+ InstancePtr->IsReady = XIL_COMPONENT_IS_READY;
+
+ /*
+ * Set the default baud rate here, can be changed prior to
+ * starting the device
+ */
+ BaudRate = (u32)XUARTPS_DFT_BAUDRATE;
+ Status = XUartPs_SetBaudRate(InstancePtr, BaudRate);
+ if (Status != (s32)XST_SUCCESS) {
+ InstancePtr->IsReady = 0U;
+ } else {
+
+ /*
+ * Set up the default data format: 8 bit data, 1 stop bit, no
+ * parity
+ */
+ ModeRegister = XUartPs_ReadReg(InstancePtr->Config.BaseAddress,
+ XUARTPS_MR_OFFSET);
+
+ /* Mask off what's already there */
+ ModeRegister &= (~((u32)XUARTPS_MR_CHARLEN_MASK |
+ (u32)XUARTPS_MR_STOPMODE_MASK |
+ (u32)XUARTPS_MR_PARITY_MASK));
+
+ /* Set the register value to the desired data format */
+ ModeRegister |= ((u32)XUARTPS_MR_CHARLEN_8_BIT |
+ (u32)XUARTPS_MR_STOPMODE_1_BIT |
+ (u32)XUARTPS_MR_PARITY_NONE);
+
+ /* Write the mode register out */
+ XUartPs_WriteReg(InstancePtr->Config.BaseAddress, XUARTPS_MR_OFFSET,
+ ModeRegister);
+
+ /* Set the RX FIFO trigger at 8 data bytes. */
+ XUartPs_WriteReg(InstancePtr->Config.BaseAddress,
+ XUARTPS_RXWM_OFFSET, 0x08U);
+
+ /* Set the RX timeout to 1, which will be 4 character time */
+ XUartPs_WriteReg(InstancePtr->Config.BaseAddress,
+ XUARTPS_RXTOUT_OFFSET, 0x01U);
+
+ /* Disable all interrupts, polled mode is the default */
+ XUartPs_WriteReg(InstancePtr->Config.BaseAddress, XUARTPS_IDR_OFFSET,
+ XUARTPS_IXR_MASK);
+
+ Status = XST_SUCCESS;
+ }
+ return Status;
+}
+
+/****************************************************************************/
+/**
+*
+* This functions sends the specified buffer using the device in either
+* polled or interrupt driven mode. This function is non-blocking, if the device
+* is busy sending data, it will return and indicate zero bytes were sent.
+* Otherwise, it fills the TX FIFO as much as it can, and return the number of
+* bytes sent.
+*
+* In a polled mode, this function will only send as much data as TX FIFO can
+* buffer. The application may need to call it repeatedly to send the entire
+* buffer.
+*
+* In interrupt mode, this function will start sending the specified buffer,
+* then the interrupt handler will continue sending data until the entire
+* buffer has been sent. A callback function, as specified by the application,
+* will be called to indicate the completion of sending.
+*
+* @param InstancePtr is a pointer to the XUartPs instance.
+* @param BufferPtr is pointer to a buffer of data to be sent.
+* @param NumBytes contains the number of bytes to be sent. A value of
+* zero will stop a previous send operation that is in progress
+* in interrupt mode. Any data that was already put into the
+* transmit FIFO will be sent.
+*
+* @return The number of bytes actually sent.
+*
+* @note
+*
+* The number of bytes is not asserted so that this function may be called with
+* a value of zero to stop an operation that is already in progress.
+* <br><br>
+*
+*****************************************************************************/
+u32 XUartPs_Send(XUartPs *InstancePtr, u8 *BufferPtr,
+ u32 NumBytes)
+{
+ u32 BytesSent;
+
+ /* Asserts validate the input arguments */
+ Xil_AssertNonvoid(InstancePtr != NULL);
+ Xil_AssertNonvoid(BufferPtr != NULL);
+ Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+ /*
+ * Disable the UART transmit interrupts to allow this call to stop a
+ * previous operation that may be interrupt driven.
+ */
+ XUartPs_WriteReg(InstancePtr->Config.BaseAddress, XUARTPS_IDR_OFFSET,
+ (XUARTPS_IXR_TXEMPTY | XUARTPS_IXR_TXFULL));
+
+ /* Setup the buffer parameters */
+ InstancePtr->SendBuffer.RequestedBytes = NumBytes;
+ InstancePtr->SendBuffer.RemainingBytes = NumBytes;
+ InstancePtr->SendBuffer.NextBytePtr = BufferPtr;
+
+ /*
+ * Transmit interrupts will be enabled in XUartPs_SendBuffer(), after
+ * filling the TX FIFO.
+ */
+ BytesSent = XUartPs_SendBuffer(InstancePtr);
+
+ return BytesSent;
+}
+
+/****************************************************************************/
+/**
+*
+* This function attempts to receive a specified number of bytes of data
+* from the device and store it into the specified buffer. This function works
+* for both polled or interrupt driven modes. It is non-blocking.
+*
+* In a polled mode, this function will only receive the data already in the
+* RX FIFO. The application may need to call it repeatedly to receive the
+* entire buffer. Polled mode is the default mode of operation for the device.
+*
+* In interrupt mode, this function will start the receiving, if not the entire
+* buffer has been received, the interrupt handler will continue receiving data
+* until the entire buffer has been received. A callback function, as specified
+* by the application, will be called to indicate the completion of the
+* receiving or error conditions.
+*
+* @param InstancePtr is a pointer to the XUartPs instance
+* @param BufferPtr is pointer to buffer for data to be received into
+* @param NumBytes is the number of bytes to be received. A value of zero
+* will stop a previous receive operation that is in progress in
+* interrupt mode.
+*
+* @return The number of bytes received.
+*
+* @note
+*
+* The number of bytes is not asserted so that this function may be called
+* with a value of zero to stop an operation that is already in progress.
+*
+*****************************************************************************/
+u32 XUartPs_Recv(XUartPs *InstancePtr,
+ u8 *BufferPtr, u32 NumBytes)
+{
+ u32 ReceivedCount;
+ u32 ImrRegister;
+
+ /* Assert validates the input arguments */
+ Xil_AssertNonvoid(InstancePtr != NULL);
+ Xil_AssertNonvoid(BufferPtr != NULL);
+ Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+ /*
+ * Disable all the interrupts.
+ * This stops a previous operation that may be interrupt driven
+ */
+ ImrRegister = XUartPs_ReadReg(InstancePtr->Config.BaseAddress,
+ XUARTPS_IMR_OFFSET);
+ XUartPs_WriteReg(InstancePtr->Config.BaseAddress, XUARTPS_IDR_OFFSET,
+ XUARTPS_IXR_MASK);
+
+ /* Setup the buffer parameters */
+ InstancePtr->ReceiveBuffer.RequestedBytes = NumBytes;
+ InstancePtr->ReceiveBuffer.RemainingBytes = NumBytes;
+ InstancePtr->ReceiveBuffer.NextBytePtr = BufferPtr;
+
+ /* Receive the data from the device */
+ ReceivedCount = XUartPs_ReceiveBuffer(InstancePtr);
+
+ /* Restore the interrupt state */
+ XUartPs_WriteReg(InstancePtr->Config.BaseAddress, XUARTPS_IER_OFFSET,
+ ImrRegister);
+
+ return ReceivedCount;
+}
+
+/****************************************************************************/
+/*
+*
+* This function sends a buffer that has been previously specified by setting
+* up the instance variables of the instance. This function is an internal
+* function for the XUartPs driver such that it may be called from a shell
+* function that sets up the buffer or from an interrupt handler.
+*
+* This function sends the specified buffer in either polled or interrupt
+* driven modes. This function is non-blocking.
+*
+* In a polled mode, this function only sends as much data as the TX FIFO
+* can buffer. The application may need to call it repeatedly to send the
+* entire buffer.
+*
+* In interrupt mode, this function starts the sending of the buffer, if not
+* the entire buffer has been sent, then the interrupt handler continues the
+* sending until the entire buffer has been sent. A callback function, as
+* specified by the application, will be called to indicate the completion of
+* sending.
+*
+* @param InstancePtr is a pointer to the XUartPs instance
+*
+* @return The number of bytes actually sent
+*
+* @note None.
+*
+*****************************************************************************/
+u32 XUartPs_SendBuffer(XUartPs *InstancePtr)
+{
+ u32 SentCount = 0U;
+ u32 ImrRegister;
+
+ /*
+ * If the TX FIFO is full, send nothing.
+ * Otherwise put bytes into the TX FIFO unil it is full, or all of the
+ * data has been put into the FIFO.
+ */
+ while ((!XUartPs_IsTransmitFull(InstancePtr->Config.BaseAddress)) &&
+ (InstancePtr->SendBuffer.RemainingBytes > SentCount)) {
+
+ /* Fill the FIFO from the buffer */
+ XUartPs_WriteReg(InstancePtr->Config.BaseAddress,
+ XUARTPS_FIFO_OFFSET,
+ ((u32)InstancePtr->SendBuffer.
+ NextBytePtr[SentCount]));
+
+ /* Increment the send count. */
+ SentCount++;
+ }
+
+ /* Update the buffer to reflect the bytes that were sent from it */
+ InstancePtr->SendBuffer.NextBytePtr += SentCount;
+ InstancePtr->SendBuffer.RemainingBytes -= SentCount;
+
+ /*
+ * If interrupts are enabled as indicated by the receive interrupt, then
+ * enable the TX FIFO empty interrupt, so further action can be taken
+ * for this sending.
+ */
+ ImrRegister =
+ XUartPs_ReadReg(InstancePtr->Config.BaseAddress,
+ XUARTPS_IMR_OFFSET);
+ if (((ImrRegister & XUARTPS_IXR_RXFULL) != (u32)0) ||
+ ((ImrRegister & XUARTPS_IXR_RXEMPTY) != (u32)0)||
+ ((ImrRegister & XUARTPS_IXR_RXOVR) != (u32)0)) {
+
+ XUartPs_WriteReg(InstancePtr->Config.BaseAddress,
+ XUARTPS_IER_OFFSET,
+ ImrRegister | (u32)XUARTPS_IXR_TXEMPTY);
+ }
+
+ return SentCount;
+}
+
+/****************************************************************************/
+/*
+*
+* This function receives a buffer that has been previously specified by setting
+* up the instance variables of the instance. This function is an internal
+* function, and it may be called from a shell function that sets up the buffer
+* or from an interrupt handler.
+*
+* This function attempts to receive a specified number of bytes from the
+* device and store it into the specified buffer. This function works for
+* either polled or interrupt driven modes. It is non-blocking.
+*
+* In polled mode, this function only receives as much data as in the RX FIFO.
+* The application may need to call it repeatedly to receive the entire buffer.
+* Polled mode is the default mode for the driver.
+*
+* In interrupt mode, this function starts the receiving, if not the entire
+* buffer has been received, the interrupt handler will continue until the
+* entire buffer has been received. A callback function, as specified by the
+* application, will be called to indicate the completion of the receiving or
+* error conditions.
+*
+* @param InstancePtr is a pointer to the XUartPs instance
+*
+* @return The number of bytes received.
+*
+* @note None.
+*
+*****************************************************************************/
+u32 XUartPs_ReceiveBuffer(XUartPs *InstancePtr)
+{
+ u32 CsrRegister;
+ u32 ReceivedCount = 0U;
+ u32 ByteStatusValue, EventData;
+ u32 Event;
+
+ /*
+ * Read the Channel Status Register to determine if there is any data in
+ * the RX FIFO
+ */
+ CsrRegister = XUartPs_ReadReg(InstancePtr->Config.BaseAddress,
+ XUARTPS_SR_OFFSET);
+
+ /*
+ * Loop until there is no more data in RX FIFO or the specified
+ * number of bytes has been received
+ */
+ while((ReceivedCount < InstancePtr->ReceiveBuffer.RemainingBytes)&&
+ (((CsrRegister & XUARTPS_SR_RXEMPTY) == (u32)0))){
+
+ if (InstancePtr->is_rxbs_error) {
+ ByteStatusValue = XUartPs_ReadReg(
+ InstancePtr->Config.BaseAddress,
+ XUARTPS_RXBS_OFFSET);
+ if((ByteStatusValue & XUARTPS_RXBS_MASK)!= (u32)0) {
+ EventData = ByteStatusValue;
+ Event = XUARTPS_EVENT_PARE_FRAME_BRKE;
+ /*
+ * Call the application handler to indicate that there is a receive
+ * error or a break interrupt, if the application cares about the
+ * error it call a function to get the last errors.
+ */
+ InstancePtr->Handler(InstancePtr->CallBackRef,
+ Event, EventData);
+ }
+ }
+
+ InstancePtr->ReceiveBuffer.NextBytePtr[ReceivedCount] =
+ XUartPs_ReadReg(InstancePtr->Config.
+ BaseAddress,
+ XUARTPS_FIFO_OFFSET);
+
+ ReceivedCount++;
+
+ CsrRegister = XUartPs_ReadReg(InstancePtr->Config.BaseAddress,
+ XUARTPS_SR_OFFSET);
+ }
+ InstancePtr->is_rxbs_error = 0;
+ /*
+ * Update the receive buffer to reflect the number of bytes just
+ * received
+ */
+ if(InstancePtr->ReceiveBuffer.NextBytePtr != NULL){
+ InstancePtr->ReceiveBuffer.NextBytePtr += ReceivedCount;
+ }
+ InstancePtr->ReceiveBuffer.RemainingBytes -= ReceivedCount;
+
+ return ReceivedCount;
+}
+
+/*****************************************************************************/
+/**
+*
+* Sets the baud rate for the device. Checks the input value for
+* validity and also verifies that the requested rate can be configured to
+* within the maximum error range specified by XUARTPS_MAX_BAUD_ERROR_RATE.
+* If the provided rate is not possible, the current setting is unchanged.
+*
+* @param InstancePtr is a pointer to the XUartPs instance
+* @param BaudRate to be set
+*
+* @return
+* - XST_SUCCESS if everything configured as expected
+* - XST_UART_BAUD_ERROR if the requested rate is not available
+* because there was too much error
+*
+* @note None.
+*
+*****************************************************************************/
+s32 XUartPs_SetBaudRate(XUartPs *InstancePtr, u32 BaudRate)
+{
+ u32 IterBAUDDIV; /* Iterator for available baud divisor values */
+ u32 BRGR_Value; /* Calculated value for baud rate generator */
+ u32 CalcBaudRate; /* Calculated baud rate */
+ u32 BaudError; /* Diff between calculated and requested baud rate */
+ u32 Best_BRGR = 0U; /* Best value for baud rate generator */
+ u8 Best_BAUDDIV = 0U; /* Best value for baud divisor */
+ u32 Best_Error = 0xFFFFFFFFU;
+ u32 PercentError;
+ u32 ModeReg;
+ u32 InputClk;
+
+ /* Asserts validate the input arguments */
+ Xil_AssertNonvoid(InstancePtr != NULL);
+ Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+ Xil_AssertNonvoid(BaudRate <= (u32)XUARTPS_MAX_RATE);
+ Xil_AssertNonvoid(BaudRate >= (u32)XUARTPS_MIN_RATE);
+
+ /*
+ * Make sure the baud rate is not impossilby large.
+ * Fastest possible baud rate is Input Clock / 2.
+ */
+ if ((BaudRate * 2) > InstancePtr->Config.InputClockHz) {
+ return XST_UART_BAUD_ERROR;
+ }
+ /* Check whether the input clock is divided by 8 */
+ ModeReg = XUartPs_ReadReg( InstancePtr->Config.BaseAddress,
+ XUARTPS_MR_OFFSET);
+
+ InputClk = InstancePtr->Config.InputClockHz;
+ if(ModeReg & XUARTPS_MR_CLKSEL) {
+ InputClk = InstancePtr->Config.InputClockHz / 8;
+ }
+
+ /*
+ * Determine the Baud divider. It can be 4to 254.
+ * Loop through all possible combinations
+ */
+ for (IterBAUDDIV = 4; IterBAUDDIV < 255; IterBAUDDIV++) {
+
+ /* Calculate the value for BRGR register */
+ BRGR_Value = InputClk / (BaudRate * (IterBAUDDIV + 1));
+
+ /* Calculate the baud rate from the BRGR value */
+ CalcBaudRate = InputClk/ (BRGR_Value * (IterBAUDDIV + 1));
+
+ /* Avoid unsigned integer underflow */
+ if (BaudRate > CalcBaudRate) {
+ BaudError = BaudRate - CalcBaudRate;
+ }
+ else {
+ BaudError = CalcBaudRate - BaudRate;
+ }
+
+ /* Find the calculated baud rate closest to requested baud rate. */
+ if (Best_Error > BaudError) {
+
+ Best_BRGR = BRGR_Value;
+ Best_BAUDDIV = IterBAUDDIV;
+ Best_Error = BaudError;
+ }
+ }
+
+ /* Make sure the best error is not too large. */
+ PercentError = (Best_Error * 100) / BaudRate;
+ if (XUARTPS_MAX_BAUD_ERROR_RATE < PercentError) {
+ return XST_UART_BAUD_ERROR;
+ }
+
+ /* Disable TX and RX to avoid glitches when setting the baud rate. */
+ XUartPs_DisableUart(InstancePtr);
+
+ XUartPs_WriteReg(InstancePtr->Config.BaseAddress,
+ XUARTPS_BAUDGEN_OFFSET, Best_BRGR);
+ XUartPs_WriteReg(InstancePtr->Config.BaseAddress,
+ XUARTPS_BAUDDIV_OFFSET, Best_BAUDDIV);
+
+ /* RX and TX SW reset */
+ XUartPs_WriteReg(InstancePtr->Config.BaseAddress, XUARTPS_CR_OFFSET,
+ XUARTPS_CR_TXRST | XUARTPS_CR_RXRST);
+
+ /* Enable device */
+ XUartPs_EnableUart(InstancePtr);
+
+ InstancePtr->BaudRate = BaudRate;
+
+ return XST_SUCCESS;
+
+}
+
+/****************************************************************************/
+/**
+*
+* This function is a stub handler that is the default handler such that if the
+* application has not set the handler when interrupts are enabled, this
+* function will be called.
+*
+* @param CallBackRef is unused by this function.
+* @param Event is unused by this function.
+* @param ByteCount is unused by this function.
+*
+* @return None.
+*
+* @note None.
+*
+*****************************************************************************/
+static void XUartPs_StubHandler(void *CallBackRef, u32 Event,
+ u32 ByteCount)
+{
+ (void) CallBackRef;
+ (void) Event;
+ (void) ByteCount;
+ /* Assert occurs always since this is a stub and should never be called */
+ Xil_AssertVoidAlways();
+}
+/** @} */
diff --git a/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/uartps_v3_8/src/xuartps.h b/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/uartps_v3_8/src/xuartps.h
new file mode 100644
index 0000000..45618b1
--- /dev/null
+++ b/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/uartps_v3_8/src/xuartps.h
@@ -0,0 +1,515 @@
+/******************************************************************************
+*
+* Copyright (C) 2010 - 2018 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+* THE SOFTWARE.
+*
+*
+*
+******************************************************************************/
+/****************************************************************************/
+/**
+*
+* @file xuartps.h
+* @addtogroup uartps_v3_8
+* @{
+* @details
+*
+* This driver supports the following features:
+*
+* - Dynamic data format (baud rate, data bits, stop bits, parity)
+* - Polled mode
+* - Interrupt driven mode
+* - Transmit and receive FIFOs (32 byte FIFO depth)
+* - Access to the external modem control lines
+*
+* <b>Initialization & Configuration</b>
+*
+* The XUartPs_Config structure is used by the driver to configure itself.
+* Fields inside this structure are properties of XUartPs based on its hardware
+* build.
+*
+* To support multiple runtime loading and initialization strategies employed
+* by various operating systems, the driver instance can be initialized in the
+* following way:
+*
+* - XUartPs_CfgInitialize(InstancePtr, CfgPtr, EffectiveAddr) - Uses a
+* configuration structure provided by the caller. If running in a system
+* with address translation, the parameter EffectiveAddr should be the
+* virtual address.
+*
+* <b>Baud Rate</b>
+*
+* The UART has an internal baud rate generator, which furnishes the baud rate
+* clock for both the receiver and the transmitter. Ther input clock frequency
+* can be either the master clock or the master clock divided by 8, configured
+* through the mode register.
+*
+* Accompanied with the baud rate divider register, the baud rate is determined
+* by:
+* <pre>
+* baud_rate = input_clock / (bgen * (bdiv + 1)
+* </pre>
+* where bgen is the value of the baud rate generator, and bdiv is the value of
+* baud rate divider.
+*
+* <b>Interrupts</b>
+*
+* The FIFOs are not flushed when the driver is initialized, but a function is
+* provided to allow the user to reset the FIFOs if desired.
+*
+* The driver defaults to no interrupts at initialization such that interrupts
+* must be enabled if desired. An interrupt is generated for one of the
+* following conditions.
+*
+* - A change in the modem signals
+* - Data in the receive FIFO for a configuable time without receiver activity
+* - A parity error
+* - A framing error
+* - An overrun error
+* - Transmit FIFO is full
+* - Transmit FIFO is empty
+* - Receive FIFO is full
+* - Receive FIFO is empty
+* - Data in the receive FIFO equal to the receive threshold
+*
+* The application can control which interrupts are enabled using the
+* XUartPs_SetInterruptMask() function.
+*
+* In order to use interrupts, it is necessary for the user to connect the
+* driver interrupt handler, XUartPs_InterruptHandler(), to the interrupt
+* system of the application. A separate handler should be provided by the
+* application to communicate with the interrupt system, and conduct
+* application specific interrupt handling. An application registers its own
+* handler through the XUartPs_SetHandler() function.
+*
+* <b>Data Transfer</b>
+*
+* The functions, XUartPs_Send() and XUartPs_Recv(), are provided in the
+* driver to allow data to be sent and received. They can be used in either
+* polled or interrupt mode.
+*
+* @note
+*
+* The default configuration for the UART after initialization is:
+*
+* - 9,600 bps or XPAR_DFT_BAUDRATE if defined
+* - 8 data bits
+* - 1 stop bit
+* - no parity
+* - FIFO's are enabled with a receive threshold of 8 bytes
+* - The RX timeout is enabled with a timeout of 1 (4 char times)
+*
+* <pre>
+* MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ----- ------ -------- ----------------------------------------------
+* 1.00a drg/jz 01/12/10 First Release
+* 1.00a sdm 09/27/11 Fixed compiler warnings and also a bug
+* in XUartPs_SetFlowDelay where the value was not
+* being written to the register.
+* 1.01a sdm 12/20/11 Removed the InputClockHz parameter from the XUartPs
+* instance structure and the driver is updated to use
+* InputClockHz parameter from the XUartPs_Config config
+* structure.
+* Added a parameter to XUartPs_Config structure which
+* specifies whether the user has selected Modem pins
+* to be connected to MIO or FMIO.
+* Added the tcl file to generate the xparameters.h
+* 1.02a sg 05/16/12 Changed XUARTPS_RXWM_MASK to 0x3F for CR 652540 fix.
+* 1.03a sg 07/16/12 Updated XUARTPS_FORMAT_7_BITS and XUARTPS_FORMAT_6_BITS
+* with the correct values for CR 666724
+* Added defines for XUARTPS_IXR_TOVR, XUARTPS_IXR_TNFUL
+* and XUARTPS_IXR_TTRIG.
+* Modified the name of these defines
+* XUARTPS_MEDEMSR_DCDX to XUARTPS_MODEMSR_DDCD
+* XUARTPS_MEDEMSR_RIX to XUARTPS_MODEMSR_TERI
+* XUARTPS_MEDEMSR_DSRX to XUARTPS_MODEMSR_DDSR
+* XUARTPS_MEDEMSR_CTSX to XUARTPS_MODEMSR_DCTS
+* 1.05a hk 08/22/13 Added API for uart reset and related
+* constant definitions.
+* 2.0 hk 03/07/14 Version number revised.
+* 2.1 hk 04/16/14 Change XUARTPS_MAX_RATE to 921600. CR# 780625.
+* 2.2 hk 06/23/14 SW reset of RX and TX should be done when changing
+* baud rate. CR# 804281.
+* 3.0 vm 12/09/14 Modified source code according to misrac guideline.
+* Support for Zynq Ultrascale Mp added.
+* 3.1 kvn 04/10/15 Modified code for latest RTL changes. Also added
+* platform variable in driver instance structure.
+* 3.1 adk 14/03/16 Include interrupt examples in the peripheral test when
+* uart is connected to a valid interrupt controller CR#946803.
+* 3.2 rk 07/20/16 Modified the logic for transmission break bit set
+* 3.4 ms 01/23/17 Added xil_printf statement in main function for all
+* examples to ensure that "Successfully ran" and "Failed"
+* strings are available in all examples. This is a fix
+* for CR-965028.
+* ms 03/17/17 Added readme.txt file in examples folder for doxygen
+* generation.
+* 3.6 ms 02/16/18 Updates the flow control mode offset value in modem
+* control register.
+* 3.7 aru 08/17/18 Resolved MISRA-C:2012 compliance mandatory violations.
+*
+* </pre>
+*
+*****************************************************************************/
+
+#ifndef XUARTPS_H /* prevent circular inclusions */
+#define XUARTPS_H /* by using protection macros */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/***************************** Include Files ********************************/
+
+#include "xil_types.h"
+#include "xil_assert.h"
+#include "xstatus.h"
+#include "xuartps_hw.h"
+#include "xplatform_info.h"
+
+/************************** Constant Definitions ****************************/
+
+/*
+ * The following constants indicate the max and min baud rates and these
+ * numbers are based only on the testing that has been done. The hardware
+ * is capable of other baud rates.
+ */
+#define XUARTPS_MAX_RATE 921600U
+#define XUARTPS_MIN_RATE 110U
+
+#define XUARTPS_DFT_BAUDRATE 115200U /* Default baud rate */
+
+/** @name Configuration options
+ * @{
+ */
+/**
+ * These constants specify the options that may be set or retrieved
+ * with the driver, each is a unique bit mask such that multiple options
+ * may be specified. These constants indicate the available options
+ * in active state.
+ *
+ */
+
+#define XUARTPS_OPTION_SET_BREAK 0x0080U /**< Starts break transmission */
+#define XUARTPS_OPTION_STOP_BREAK 0x0040U /**< Stops break transmission */
+#define XUARTPS_OPTION_RESET_TMOUT 0x0020U /**< Reset the receive timeout */
+#define XUARTPS_OPTION_RESET_TX 0x0010U /**< Reset the transmitter */
+#define XUARTPS_OPTION_RESET_RX 0x0008U /**< Reset the receiver */
+#define XUARTPS_OPTION_ASSERT_RTS 0x0004U /**< Assert the RTS bit */
+#define XUARTPS_OPTION_ASSERT_DTR 0x0002U /**< Assert the DTR bit */
+#define XUARTPS_OPTION_SET_FCM 0x0001U /**< Turn on flow control mode */
+/*@}*/
+
+
+/** @name Channel Operational Mode
+ *
+ * The UART can operate in one of four modes: Normal, Local Loopback, Remote
+ * Loopback, or automatic echo.
+ *
+ * @{
+ */
+
+#define XUARTPS_OPER_MODE_NORMAL (u8)0x00U /**< Normal Mode */
+#define XUARTPS_OPER_MODE_AUTO_ECHO (u8)0x01U /**< Auto Echo Mode */
+#define XUARTPS_OPER_MODE_LOCAL_LOOP (u8)0x02U /**< Local Loopback Mode */
+#define XUARTPS_OPER_MODE_REMOTE_LOOP (u8)0x03U /**< Remote Loopback Mode */
+
+/* @} */
+
+/** @name Data format values
+ *
+ * These constants specify the data format that the driver supports.
+ * The data format includes the number of data bits, the number of stop
+ * bits and parity.
+ *
+ * @{
+ */
+#define XUARTPS_FORMAT_8_BITS 0U /**< 8 data bits */
+#define XUARTPS_FORMAT_7_BITS 2U /**< 7 data bits */
+#define XUARTPS_FORMAT_6_BITS 3U /**< 6 data bits */
+
+#define XUARTPS_FORMAT_NO_PARITY 4U /**< No parity */
+#define XUARTPS_FORMAT_MARK_PARITY 3U /**< Mark parity */
+#define XUARTPS_FORMAT_SPACE_PARITY 2U /**< parity */
+#define XUARTPS_FORMAT_ODD_PARITY 1U /**< Odd parity */
+#define XUARTPS_FORMAT_EVEN_PARITY 0U /**< Even parity */
+
+#define XUARTPS_FORMAT_2_STOP_BIT 2U /**< 2 stop bits */
+#define XUARTPS_FORMAT_1_5_STOP_BIT 1U /**< 1.5 stop bits */
+#define XUARTPS_FORMAT_1_STOP_BIT 0U /**< 1 stop bit */
+/*@}*/
+
+/** @name Callback events
+ *
+ * These constants specify the handler events that an application can handle
+ * using its specific handler function. Note that these constants are not bit
+ * mask, so only one event can be passed to an application at a time.
+ *
+ * @{
+ */
+#define XUARTPS_EVENT_RECV_DATA 1U /**< Data receiving done */
+#define XUARTPS_EVENT_RECV_TOUT 2U /**< A receive timeout occurred */
+#define XUARTPS_EVENT_SENT_DATA 3U /**< Data transmission done */
+#define XUARTPS_EVENT_RECV_ERROR 4U /**< A receive error detected */
+#define XUARTPS_EVENT_MODEM 5U /**< Modem status changed */
+#define XUARTPS_EVENT_PARE_FRAME_BRKE 6U /**< A receive parity, frame, break
+ * error detected */
+#define XUARTPS_EVENT_RECV_ORERR 7U /**< A receive overrun error detected */
+/*@}*/
+
+
+/**************************** Type Definitions ******************************/
+
+/**
+ * This typedef contains configuration information for the device.
+ */
+typedef struct {
+ u16 DeviceId; /**< Unique ID of device */
+ u32 BaseAddress; /**< Base address of device (IPIF) */
+ u32 InputClockHz;/**< Input clock frequency */
+ s32 ModemPinsConnected; /** Specifies whether modem pins are connected
+ * to MIO or FMIO */
+} XUartPs_Config;
+
+/* Keep track of state information about a data buffer in the interrupt mode. */
+typedef struct {
+ u8 *NextBytePtr;
+ u32 RequestedBytes;
+ u32 RemainingBytes;
+} XUartPsBuffer;
+
+/**
+ * Keep track of data format setting of a device.
+ */
+typedef struct {
+ u32 BaudRate; /**< In bps, ie 1200 */
+ u32 DataBits; /**< Number of data bits */
+ u32 Parity; /**< Parity */
+ u8 StopBits; /**< Number of stop bits */
+} XUartPsFormat;
+
+/******************************************************************************/
+/**
+ * This data type defines a handler that an application defines to communicate
+ * with interrupt system to retrieve state information about an application.
+ *
+ * @param CallBackRef is a callback reference passed in by the upper layer
+ * when setting the handler, and is passed back to the upper layer
+ * when the handler is called. It is used to find the device driver
+ * instance.
+ * @param Event contains one of the event constants indicating events that
+ * have occurred.
+ * @param EventData contains the number of bytes sent or received at the
+ * time of the call for send and receive events and contains the
+ * modem status for modem events.
+ *
+ ******************************************************************************/
+typedef void (*XUartPs_Handler) (void *CallBackRef, u32 Event,
+ u32 EventData);
+
+/**
+ * The XUartPs driver instance data structure. A pointer to an instance data
+ * structure is passed around by functions to refer to a specific driver
+ * instance.
+ */
+typedef struct {
+ XUartPs_Config Config; /* Configuration data structure */
+ u32 InputClockHz; /* Input clock frequency */
+ u32 IsReady; /* Device is initialized and ready */
+ u32 BaudRate; /* Current baud rate */
+
+ XUartPsBuffer SendBuffer;
+ XUartPsBuffer ReceiveBuffer;
+
+ XUartPs_Handler Handler;
+ void *CallBackRef; /* Callback reference for event handler */
+ u32 Platform;
+ u8 is_rxbs_error;
+} XUartPs;
+
+
+/***************** Macros (Inline Functions) Definitions ********************/
+
+/****************************************************************************/
+/**
+* Get the UART Channel Status Register.
+*
+* @param InstancePtr is a pointer to the XUartPs instance.
+*
+* @return The value read from the register.
+*
+* @note C-Style signature:
+* u16 XUartPs_GetChannelStatus(XUartPs *InstancePtr)
+*
+******************************************************************************/
+#define XUartPs_GetChannelStatus(InstancePtr) \
+ Xil_In32(((InstancePtr)->Config.BaseAddress) + (u32)XUARTPS_SR_OFFSET)
+
+/****************************************************************************/
+/**
+* Get the UART Mode Control Register.
+*
+* @param InstancePtr is a pointer to the XUartPs instance.
+*
+* @return The value read from the register.
+*
+* @note C-Style signature:
+* u32 XUartPs_GetControl(XUartPs *InstancePtr)
+*
+******************************************************************************/
+#define XUartPs_GetModeControl(InstancePtr) \
+ Xil_In32(((InstancePtr)->Config.BaseAddress) + (u32)XUARTPS_CR_OFFSET)
+
+/****************************************************************************/
+/**
+* Set the UART Mode Control Register.
+*
+* @param InstancePtr is a pointer to the XUartPs instance.
+* @param RegisterValue is the value to be written to the register.
+*
+* @return None.
+*
+* @note C-Style signature:
+* void XUartPs_SetModeControl(XUartPs *InstancePtr, u16 RegisterValue)
+*
+******************************************************************************/
+#define XUartPs_SetModeControl(InstancePtr, RegisterValue) \
+ Xil_Out32(((InstancePtr)->Config.BaseAddress) + (u32)XUARTPS_CR_OFFSET, \
+ (u32)(RegisterValue))
+
+/****************************************************************************/
+/**
+* Enable the transmitter and receiver of the UART.
+*
+* @param InstancePtr is a pointer to the XUartPs instance.
+*
+* @return None.
+*
+* @note C-Style signature:
+* void XUartPs_EnableUart(XUartPs *InstancePtr)
+*
+******************************************************************************/
+#define XUartPs_EnableUart(InstancePtr) \
+ Xil_Out32(((InstancePtr)->Config.BaseAddress + (u32)XUARTPS_CR_OFFSET), \
+ ((Xil_In32((InstancePtr)->Config.BaseAddress + (u32)XUARTPS_CR_OFFSET) & \
+ (u32)(~XUARTPS_CR_EN_DIS_MASK)) | ((u32)XUARTPS_CR_RX_EN | (u32)XUARTPS_CR_TX_EN)))
+
+/****************************************************************************/
+/**
+* Disable the transmitter and receiver of the UART.
+*
+* @param InstancePtr is a pointer to the XUartPs instance.
+*
+* @return None.
+*
+* @note C-Style signature:
+* void XUartPs_DisableUart(XUartPs *InstancePtr)
+*
+******************************************************************************/
+#define XUartPs_DisableUart(InstancePtr) \
+ Xil_Out32(((InstancePtr)->Config.BaseAddress + (u32)XUARTPS_CR_OFFSET), \
+ (((Xil_In32((InstancePtr)->Config.BaseAddress + (u32)XUARTPS_CR_OFFSET)) & \
+ (u32)(~XUARTPS_CR_EN_DIS_MASK)) | ((u32)XUARTPS_CR_RX_DIS | (u32)XUARTPS_CR_TX_DIS)))
+
+/****************************************************************************/
+/**
+* Determine if the transmitter FIFO is empty.
+*
+* @param InstancePtr is a pointer to the XUartPs instance.
+*
+* @return
+* - TRUE if a byte can be sent
+* - FALSE if the Transmitter Fifo is not empty
+*
+* @note C-Style signature:
+* u32 XUartPs_IsTransmitEmpty(XUartPs InstancePtr)
+*
+******************************************************************************/
+#define XUartPs_IsTransmitEmpty(InstancePtr) \
+ ((Xil_In32(((InstancePtr)->Config.BaseAddress) + (u32)XUARTPS_SR_OFFSET) & \
+ (u32)XUARTPS_SR_TXEMPTY) == (u32)XUARTPS_SR_TXEMPTY)
+
+
+/************************** Function Prototypes *****************************/
+
+/* Static lookup function implemented in xuartps_sinit.c */
+XUartPs_Config *XUartPs_LookupConfig(u16 DeviceId);
+
+/* Interface functions implemented in xuartps.c */
+s32 XUartPs_CfgInitialize(XUartPs *InstancePtr,
+ XUartPs_Config * Config, u32 EffectiveAddr);
+
+u32 XUartPs_Send(XUartPs *InstancePtr,u8 *BufferPtr,
+ u32 NumBytes);
+
+u32 XUartPs_Recv(XUartPs *InstancePtr,u8 *BufferPtr,
+ u32 NumBytes);
+
+s32 XUartPs_SetBaudRate(XUartPs *InstancePtr, u32 BaudRate);
+
+/* Options functions in xuartps_options.c */
+void XUartPs_SetOptions(XUartPs *InstancePtr, u16 Options);
+
+u16 XUartPs_GetOptions(XUartPs *InstancePtr);
+
+void XUartPs_SetFifoThreshold(XUartPs *InstancePtr, u8 TriggerLevel);
+
+u8 XUartPs_GetFifoThreshold(XUartPs *InstancePtr);
+
+u16 XUartPs_GetModemStatus(XUartPs *InstancePtr);
+
+u32 XUartPs_IsSending(XUartPs *InstancePtr);
+
+u8 XUartPs_GetOperMode(XUartPs *InstancePtr);
+
+void XUartPs_SetOperMode(XUartPs *InstancePtr, u8 OperationMode);
+
+u8 XUartPs_GetFlowDelay(XUartPs *InstancePtr);
+
+void XUartPs_SetFlowDelay(XUartPs *InstancePtr, u8 FlowDelayValue);
+
+u8 XUartPs_GetRecvTimeout(XUartPs *InstancePtr);
+
+void XUartPs_SetRecvTimeout(XUartPs *InstancePtr, u8 RecvTimeout);
+
+s32 XUartPs_SetDataFormat(XUartPs *InstancePtr, XUartPsFormat * FormatPtr);
+
+void XUartPs_GetDataFormat(XUartPs *InstancePtr, XUartPsFormat * FormatPtr);
+
+/* interrupt functions in xuartps_intr.c */
+u32 XUartPs_GetInterruptMask(XUartPs *InstancePtr);
+
+void XUartPs_SetInterruptMask(XUartPs *InstancePtr, u32 Mask);
+
+void XUartPs_InterruptHandler(XUartPs *InstancePtr);
+
+void XUartPs_SetHandler(XUartPs *InstancePtr, XUartPs_Handler FuncPtr,
+ void *CallBackRef);
+
+/* self-test functions in xuartps_selftest.c */
+s32 XUartPs_SelfTest(XUartPs *InstancePtr);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* end of protection macro */
+/** @} */
diff --git a/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/uartps_v3_8/src/xuartps_g.c b/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/uartps_v3_8/src/xuartps_g.c
new file mode 100644
index 0000000..0da7900
--- /dev/null
+++ b/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/uartps_v3_8/src/xuartps_g.c
@@ -0,0 +1,49 @@
+
+/*******************************************************************
+*
+* CAUTION: This file is automatically generated by HSI.
+* Version: 2019.2
+* DO NOT EDIT.
+*
+* Copyright (C) 2010-2021 Xilinx, Inc. All Rights Reserved.*
+*Permission is hereby granted, free of charge, to any person obtaining a copy
+*of this software and associated documentation files (the Software), to deal
+*in the Software without restriction, including without limitation the rights
+*to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+*copies of the Software, and to permit persons to whom the Software is
+*furnished to do so, subject to the following conditions:
+*
+*The above copyright notice and this permission notice shall be included in
+*all copies or substantial portions of the Software.
+*
+*THE SOFTWARE IS PROVIDED AS IS, WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+*IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+*FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+*THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+*WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT
+*OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+*
+
+*
+* Description: Driver configuration
+*
+*******************************************************************/
+
+#include "xparameters.h"
+#include "xuartps.h"
+
+/*
+* The configuration table for devices
+*/
+
+XUartPs_Config XUartPs_ConfigTable[XPAR_XUARTPS_NUM_INSTANCES] =
+{
+ {
+ XPAR_PS7_UART_1_DEVICE_ID,
+ XPAR_PS7_UART_1_BASEADDR,
+ XPAR_PS7_UART_1_UART_CLK_FREQ_HZ,
+ XPAR_PS7_UART_1_HAS_MODEM
+ }
+};
+
+
diff --git a/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/uartps_v3_8/src/xuartps_hw.c b/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/uartps_v3_8/src/xuartps_hw.c
new file mode 100644
index 0000000..83c238e
--- /dev/null
+++ b/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/uartps_v3_8/src/xuartps_hw.c
@@ -0,0 +1,174 @@
+/******************************************************************************
+*
+* Copyright (C) 2010 - 2015 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+* THE SOFTWARE.
+*
+*
+*
+******************************************************************************/
+/****************************************************************************/
+/**
+*
+* @file xuartps_hw.c
+* @addtogroup uartps_v3_8
+* @{
+*
+*
+* <pre>
+* MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ----- ------ -------- ----------------------------------------------
+* 1.00 drg/jz 01/12/10 First Release
+* 1.05a hk 08/22/13 Added reset function
+* 3.00 kvn 02/13/15 Modified code for MISRA-C:2012 compliance.
+* </pre>
+*
+*****************************************************************************/
+
+/***************************** Include Files ********************************/
+#include "xuartps_hw.h"
+
+/************************** Constant Definitions ****************************/
+
+
+/***************** Macros (Inline Functions) Definitions ********************/
+
+
+/************************** Function Prototypes ******************************/
+
+
+/************************** Variable Definitions *****************************/
+
+/****************************************************************************/
+/**
+*
+* This function sends one byte using the device. This function operates in
+* polled mode and blocks until the data has been put into the TX FIFO register.
+*
+* @param BaseAddress contains the base address of the device.
+* @param Data contains the byte to be sent.
+*
+* @return None.
+*
+* @note None.
+*
+*****************************************************************************/
+void XUartPs_SendByte(u32 BaseAddress, u8 Data)
+{
+ /* Wait until there is space in TX FIFO */
+ while (XUartPs_IsTransmitFull(BaseAddress)) {
+ ;
+ }
+
+ /* Write the byte into the TX FIFO */
+ XUartPs_WriteReg(BaseAddress, XUARTPS_FIFO_OFFSET, (u32)Data);
+}
+
+/****************************************************************************/
+/**
+*
+* This function receives a byte from the device. It operates in polled mode
+* and blocks until a byte has received.
+*
+* @param BaseAddress contains the base address of the device.
+*
+* @return The data byte received.
+*
+* @note None.
+*
+*****************************************************************************/
+u8 XUartPs_RecvByte(u32 BaseAddress)
+{
+ u32 RecievedByte;
+ /* Wait until there is data */
+ while (!XUartPs_IsReceiveData(BaseAddress)) {
+ ;
+ }
+ RecievedByte = XUartPs_ReadReg(BaseAddress, XUARTPS_FIFO_OFFSET);
+ /* Return the byte received */
+ return (u8)RecievedByte;
+}
+
+/****************************************************************************/
+/**
+*
+* This function resets UART
+*
+* @param BaseAddress contains the base address of the device.
+*
+* @return None
+*
+* @note None.
+*
+*****************************************************************************/
+void XUartPs_ResetHw(u32 BaseAddress)
+{
+
+ /* Disable interrupts */
+ XUartPs_WriteReg(BaseAddress, XUARTPS_IDR_OFFSET, XUARTPS_IXR_MASK);
+
+ /* Disable receive and transmit */
+ XUartPs_WriteReg(BaseAddress, XUARTPS_CR_OFFSET,
+ ((u32)XUARTPS_CR_RX_DIS | (u32)XUARTPS_CR_TX_DIS));
+
+ /*
+ * Software reset of receive and transmit
+ * This clears the FIFO.
+ */
+ XUartPs_WriteReg(BaseAddress, XUARTPS_CR_OFFSET,
+ ((u32)XUARTPS_CR_TXRST | (u32)XUARTPS_CR_RXRST));
+
+ /* Clear status flags - SW reset wont clear sticky flags. */
+ XUartPs_WriteReg(BaseAddress, XUARTPS_ISR_OFFSET, XUARTPS_IXR_MASK);
+
+ /*
+ * Mode register reset value : All zeroes
+ * Normal mode, even parity, 1 stop bit
+ */
+ XUartPs_WriteReg(BaseAddress, XUARTPS_MR_OFFSET,
+ XUARTPS_MR_CHMODE_NORM);
+
+ /* Rx and TX trigger register reset values */
+ XUartPs_WriteReg(BaseAddress, XUARTPS_RXWM_OFFSET,
+ XUARTPS_RXWM_RESET_VAL);
+ XUartPs_WriteReg(BaseAddress, XUARTPS_TXWM_OFFSET,
+ XUARTPS_TXWM_RESET_VAL);
+
+ /* Rx timeout disabled by default */
+ XUartPs_WriteReg(BaseAddress, XUARTPS_RXTOUT_OFFSET,
+ XUARTPS_RXTOUT_DISABLE);
+
+ /* Baud rate generator and dividor reset values */
+ XUartPs_WriteReg(BaseAddress, XUARTPS_BAUDGEN_OFFSET,
+ XUARTPS_BAUDGEN_RESET_VAL);
+ XUartPs_WriteReg(BaseAddress, XUARTPS_BAUDDIV_OFFSET,
+ XUARTPS_BAUDDIV_RESET_VAL);
+
+ /*
+ * Control register reset value -
+ * RX and TX are disable by default
+ */
+ XUartPs_WriteReg(BaseAddress, XUARTPS_CR_OFFSET,
+ ((u32)XUARTPS_CR_RX_DIS | (u32)XUARTPS_CR_TX_DIS |
+ (u32)XUARTPS_CR_STOPBRK));
+
+}
+/** @} */
diff --git a/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/uartps_v3_8/src/xuartps_hw.h b/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/uartps_v3_8/src/xuartps_hw.h
new file mode 100644
index 0000000..f627472
--- /dev/null
+++ b/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/uartps_v3_8/src/xuartps_hw.h
@@ -0,0 +1,445 @@
+/******************************************************************************
+*
+* Copyright (C) 2010 - 2017 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+* THE SOFTWARE.
+*
+*
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xuartps_hw.h
+* @addtogroup uartps_v3_8
+* @{
+*
+* This header file contains the hardware interface of an XUartPs device.
+*
+* <pre>
+* MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ----- ------ -------- ----------------------------------------------
+* 1.00 drg/jz 01/12/10 First Release
+* 1.03a sg 09/04/12 Added defines for XUARTPS_IXR_TOVR, XUARTPS_IXR_TNFUL
+* and XUARTPS_IXR_TTRIG.
+* Modified the names of these defines
+* XUARTPS_MEDEMSR_DCDX to XUARTPS_MODEMSR_DDCD
+* XUARTPS_MEDEMSR_RIX to XUARTPS_MODEMSR_TERI
+* XUARTPS_MEDEMSR_DSRX to XUARTPS_MODEMSR_DDSR
+* XUARTPS_MEDEMSR_CTSX to XUARTPS_MODEMSR_DCTS
+* 1.05a hk 08/22/13 Added prototype for uart reset and related
+* constant definitions.
+* 3.00 kvn 02/13/15 Modified code for MISRA-C:2012 compliance.
+* 3.1 kvn 04/10/15 Modified code for latest RTL changes.
+* 3.6 ms 02/16/18 Updates flow control mode offset value in
+* modem control register.
+*
+* </pre>
+*
+******************************************************************************/
+#ifndef XUARTPS_HW_H /* prevent circular inclusions */
+#define XUARTPS_HW_H /* by using protection macros */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/***************************** Include Files *********************************/
+
+#include "xil_types.h"
+#include "xil_assert.h"
+#include "xil_io.h"
+
+/************************** Constant Definitions *****************************/
+
+/** @name Register Map
+ *
+ * Register offsets for the UART.
+ * @{
+ */
+#define XUARTPS_CR_OFFSET 0x0000U /**< Control Register [8:0] */
+#define XUARTPS_MR_OFFSET 0x0004U /**< Mode Register [9:0] */
+#define XUARTPS_IER_OFFSET 0x0008U /**< Interrupt Enable [12:0] */
+#define XUARTPS_IDR_OFFSET 0x000CU /**< Interrupt Disable [12:0] */
+#define XUARTPS_IMR_OFFSET 0x0010U /**< Interrupt Mask [12:0] */
+#define XUARTPS_ISR_OFFSET 0x0014U /**< Interrupt Status [12:0]*/
+#define XUARTPS_BAUDGEN_OFFSET 0x0018U /**< Baud Rate Generator [15:0] */
+#define XUARTPS_RXTOUT_OFFSET 0x001CU /**< RX Timeout [7:0] */
+#define XUARTPS_RXWM_OFFSET 0x0020U /**< RX FIFO Trigger Level [5:0] */
+#define XUARTPS_MODEMCR_OFFSET 0x0024U /**< Modem Control [5:0] */
+#define XUARTPS_MODEMSR_OFFSET 0x0028U /**< Modem Status [8:0] */
+#define XUARTPS_SR_OFFSET 0x002CU /**< Channel Status [14:0] */
+#define XUARTPS_FIFO_OFFSET 0x0030U /**< FIFO [7:0] */
+#define XUARTPS_BAUDDIV_OFFSET 0x0034U /**< Baud Rate Divider [7:0] */
+#define XUARTPS_FLOWDEL_OFFSET 0x0038U /**< Flow Delay [5:0] */
+#define XUARTPS_TXWM_OFFSET 0x0044U /**< TX FIFO Trigger Level [5:0] */
+#define XUARTPS_RXBS_OFFSET 0x0048U /**< RX FIFO Byte Status [11:0] */
+/* @} */
+
+/** @name Control Register
+ *
+ * The Control register (CR) controls the major functions of the device.
+ *
+ * Control Register Bit Definition
+ */
+
+#define XUARTPS_CR_STOPBRK 0x00000100U /**< Stop transmission of break */
+#define XUARTPS_CR_STARTBRK 0x00000080U /**< Set break */
+#define XUARTPS_CR_TORST 0x00000040U /**< RX timeout counter restart */
+#define XUARTPS_CR_TX_DIS 0x00000020U /**< TX disabled. */
+#define XUARTPS_CR_TX_EN 0x00000010U /**< TX enabled */
+#define XUARTPS_CR_RX_DIS 0x00000008U /**< RX disabled. */
+#define XUARTPS_CR_RX_EN 0x00000004U /**< RX enabled */
+#define XUARTPS_CR_EN_DIS_MASK 0x0000003CU /**< Enable/disable Mask */
+#define XUARTPS_CR_TXRST 0x00000002U /**< TX logic reset */
+#define XUARTPS_CR_RXRST 0x00000001U /**< RX logic reset */
+/* @}*/
+
+
+/** @name Mode Register
+ *
+ * The mode register (MR) defines the mode of transfer as well as the data
+ * format. If this register is modified during transmission or reception,
+ * data validity cannot be guaranteed.
+ *
+ * Mode Register Bit Definition
+ * @{
+ */
+#define XUARTPS_MR_CCLK 0x00000400U /**< Input clock selection */
+#define XUARTPS_MR_CHMODE_R_LOOP 0x00000300U /**< Remote loopback mode */
+#define XUARTPS_MR_CHMODE_L_LOOP 0x00000200U /**< Local loopback mode */
+#define XUARTPS_MR_CHMODE_ECHO 0x00000100U /**< Auto echo mode */
+#define XUARTPS_MR_CHMODE_NORM 0x00000000U /**< Normal mode */
+#define XUARTPS_MR_CHMODE_SHIFT 8U /**< Mode shift */
+#define XUARTPS_MR_CHMODE_MASK 0x00000300U /**< Mode mask */
+#define XUARTPS_MR_STOPMODE_2_BIT 0x00000080U /**< 2 stop bits */
+#define XUARTPS_MR_STOPMODE_1_5_BIT 0x00000040U /**< 1.5 stop bits */
+#define XUARTPS_MR_STOPMODE_1_BIT 0x00000000U /**< 1 stop bit */
+#define XUARTPS_MR_STOPMODE_SHIFT 6U /**< Stop bits shift */
+#define XUARTPS_MR_STOPMODE_MASK 0x000000A0U /**< Stop bits mask */
+#define XUARTPS_MR_PARITY_NONE 0x00000020U /**< No parity mode */
+#define XUARTPS_MR_PARITY_MARK 0x00000018U /**< Mark parity mode */
+#define XUARTPS_MR_PARITY_SPACE 0x00000010U /**< Space parity mode */
+#define XUARTPS_MR_PARITY_ODD 0x00000008U /**< Odd parity mode */
+#define XUARTPS_MR_PARITY_EVEN 0x00000000U /**< Even parity mode */
+#define XUARTPS_MR_PARITY_SHIFT 3U /**< Parity setting shift */
+#define XUARTPS_MR_PARITY_MASK 0x00000038U /**< Parity mask */
+#define XUARTPS_MR_CHARLEN_6_BIT 0x00000006U /**< 6 bits data */
+#define XUARTPS_MR_CHARLEN_7_BIT 0x00000004U /**< 7 bits data */
+#define XUARTPS_MR_CHARLEN_8_BIT 0x00000000U /**< 8 bits data */
+#define XUARTPS_MR_CHARLEN_SHIFT 1U /**< Data Length shift */
+#define XUARTPS_MR_CHARLEN_MASK 0x00000006U /**< Data length mask */
+#define XUARTPS_MR_CLKSEL 0x00000001U /**< Input clock selection */
+/* @} */
+
+
+/** @name Interrupt Registers
+ *
+ * Interrupt control logic uses the interrupt enable register (IER) and the
+ * interrupt disable register (IDR) to set the value of the bits in the
+ * interrupt mask register (IMR). The IMR determines whether to pass an
+ * interrupt to the interrupt status register (ISR).
+ * Writing a 1 to IER Enbables an interrupt, writing a 1 to IDR disables an
+ * interrupt. IMR and ISR are read only, and IER and IDR are write only.
+ * Reading either IER or IDR returns 0x00.
+ *
+ * All four registers have the same bit definitions.
+ *
+ * @{
+ */
+#define XUARTPS_IXR_RBRK 0x00002000U /**< Rx FIFO break detect interrupt */
+#define XUARTPS_IXR_TOVR 0x00001000U /**< Tx FIFO Overflow interrupt */
+#define XUARTPS_IXR_TNFUL 0x00000800U /**< Tx FIFO Nearly Full interrupt */
+#define XUARTPS_IXR_TTRIG 0x00000400U /**< Tx Trig interrupt */
+#define XUARTPS_IXR_DMS 0x00000200U /**< Modem status change interrupt */
+#define XUARTPS_IXR_TOUT 0x00000100U /**< Timeout error interrupt */
+#define XUARTPS_IXR_PARITY 0x00000080U /**< Parity error interrupt */
+#define XUARTPS_IXR_FRAMING 0x00000040U /**< Framing error interrupt */
+#define XUARTPS_IXR_OVER 0x00000020U /**< Overrun error interrupt */
+#define XUARTPS_IXR_TXFULL 0x00000010U /**< TX FIFO full interrupt. */
+#define XUARTPS_IXR_TXEMPTY 0x00000008U /**< TX FIFO empty interrupt. */
+#define XUARTPS_IXR_RXFULL 0x00000004U /**< RX FIFO full interrupt. */
+#define XUARTPS_IXR_RXEMPTY 0x00000002U /**< RX FIFO empty interrupt. */
+#define XUARTPS_IXR_RXOVR 0x00000001U /**< RX FIFO trigger interrupt. */
+#define XUARTPS_IXR_MASK 0x00003FFFU /**< Valid bit mask */
+/* @} */
+
+
+/** @name Baud Rate Generator Register
+ *
+ * The baud rate generator control register (BRGR) is a 16 bit register that
+ * controls the receiver bit sample clock and baud rate.
+ * Valid values are 1 - 65535.
+ *
+ * Bit Sample Rate = CCLK / BRGR, where the CCLK is selected by the MR_CCLK bit
+ * in the MR register.
+ * @{
+ */
+#define XUARTPS_BAUDGEN_DISABLE 0x00000000U /**< Disable clock */
+#define XUARTPS_BAUDGEN_MASK 0x0000FFFFU /**< Valid bits mask */
+#define XUARTPS_BAUDGEN_RESET_VAL 0x0000028BU /**< Reset value */
+
+/** @name Baud Divisor Rate register
+ *
+ * The baud rate divider register (BDIV) controls how much the bit sample
+ * rate is divided by. It sets the baud rate.
+ * Valid values are 0x04 to 0xFF. Writing a value less than 4 will be ignored.
+ *
+ * Baud rate = CCLK / ((BAUDDIV + 1) x BRGR), where the CCLK is selected by
+ * the MR_CCLK bit in the MR register.
+ * @{
+ */
+#define XUARTPS_BAUDDIV_MASK 0x000000FFU /**< 8 bit baud divider mask */
+#define XUARTPS_BAUDDIV_RESET_VAL 0x0000000FU /**< Reset value */
+/* @} */
+
+
+/** @name Receiver Timeout Register
+ *
+ * Use the receiver timeout register (RTR) to detect an idle condition on
+ * the receiver data line.
+ *
+ * @{
+ */
+#define XUARTPS_RXTOUT_DISABLE 0x00000000U /**< Disable time out */
+#define XUARTPS_RXTOUT_MASK 0x000000FFU /**< Valid bits mask */
+
+/** @name Receiver FIFO Trigger Level Register
+ *
+ * Use the Receiver FIFO Trigger Level Register (RTRIG) to set the value at
+ * which the RX FIFO triggers an interrupt event.
+ * @{
+ */
+
+#define XUARTPS_RXWM_DISABLE 0x00000000U /**< Disable RX trigger interrupt */
+#define XUARTPS_RXWM_MASK 0x0000003FU /**< Valid bits mask */
+#define XUARTPS_RXWM_RESET_VAL 0x00000020U /**< Reset value */
+/* @} */
+
+/** @name Transmit FIFO Trigger Level Register
+ *
+ * Use the Transmit FIFO Trigger Level Register (TTRIG) to set the value at
+ * which the TX FIFO triggers an interrupt event.
+ * @{
+ */
+
+#define XUARTPS_TXWM_MASK 0x0000003FU /**< Valid bits mask */
+#define XUARTPS_TXWM_RESET_VAL 0x00000020U /**< Reset value */
+/* @} */
+
+/** @name Modem Control Register
+ *
+ * This register (MODEMCR) controls the interface with the modem or data set,
+ * or a peripheral device emulating a modem.
+ *
+ * @{
+ */
+#define XUARTPS_MODEMCR_FCM 0x00000020U /**< Flow control mode */
+#define XUARTPS_MODEMCR_RTS 0x00000002U /**< Request to send */
+#define XUARTPS_MODEMCR_DTR 0x00000001U /**< Data terminal ready */
+/* @} */
+
+/** @name Modem Status Register
+ *
+ * This register (MODEMSR) indicates the current state of the control lines
+ * from a modem, or another peripheral device, to the CPU. In addition, four
+ * bits of the modem status register provide change information. These bits
+ * are set to a logic 1 whenever a control input from the modem changes state.
+ *
+ * Note: Whenever the DCTS, DDSR, TERI, or DDCD bit is set to logic 1, a modem
+ * status interrupt is generated and this is reflected in the modem status
+ * register.
+ *
+ * @{
+ */
+#define XUARTPS_MODEMSR_FCMS 0x00000100U /**< Flow control mode (FCMS) */
+#define XUARTPS_MODEMSR_DCD 0x00000080U /**< Complement of DCD input */
+#define XUARTPS_MODEMSR_RI 0x00000040U /**< Complement of RI input */
+#define XUARTPS_MODEMSR_DSR 0x00000020U /**< Complement of DSR input */
+#define XUARTPS_MODEMSR_CTS 0x00000010U /**< Complement of CTS input */
+#define XUARTPS_MODEMSR_DDCD 0x00000008U /**< Delta DCD indicator */
+#define XUARTPS_MODEMSR_TERI 0x00000004U /**< Trailing Edge Ring Indicator */
+#define XUARTPS_MODEMSR_DDSR 0x00000002U /**< Change of DSR */
+#define XUARTPS_MODEMSR_DCTS 0x00000001U /**< Change of CTS */
+/* @} */
+
+/** @name Channel Status Register
+ *
+ * The channel status register (CSR) is provided to enable the control logic
+ * to monitor the status of bits in the channel interrupt status register,
+ * even if these are masked out by the interrupt mask register.
+ *
+ * @{
+ */
+#define XUARTPS_SR_TNFUL 0x00004000U /**< TX FIFO Nearly Full Status */
+#define XUARTPS_SR_TTRIG 0x00002000U /**< TX FIFO Trigger Status */
+#define XUARTPS_SR_FLOWDEL 0x00001000U /**< RX FIFO fill over flow delay */
+#define XUARTPS_SR_TACTIVE 0x00000800U /**< TX active */
+#define XUARTPS_SR_RACTIVE 0x00000400U /**< RX active */
+#define XUARTPS_SR_TXFULL 0x00000010U /**< TX FIFO full */
+#define XUARTPS_SR_TXEMPTY 0x00000008U /**< TX FIFO empty */
+#define XUARTPS_SR_RXFULL 0x00000004U /**< RX FIFO full */
+#define XUARTPS_SR_RXEMPTY 0x00000002U /**< RX FIFO empty */
+#define XUARTPS_SR_RXOVR 0x00000001U /**< RX FIFO fill over trigger */
+/* @} */
+
+/** @name Flow Delay Register
+ *
+ * Operation of the flow delay register (FLOWDEL) is very similar to the
+ * receive FIFO trigger register. An internal trigger signal activates when the
+ * FIFO is filled to the level set by this register. This trigger will not
+ * cause an interrupt, although it can be read through the channel status
+ * register. In hardware flow control mode, RTS is deactivated when the trigger
+ * becomes active. RTS only resets when the FIFO level is four less than the
+ * level of the flow delay trigger and the flow delay trigger is not activated.
+ * A value less than 4 disables the flow delay.
+ * @{
+ */
+#define XUARTPS_FLOWDEL_MASK XUARTPS_RXWM_MASK /**< Valid bit mask */
+/* @} */
+
+/** @name Receiver FIFO Byte Status Register
+ *
+ * The Receiver FIFO Status register is used to have a continuous
+ * monitoring of the raw unmasked byte status information. The register
+ * contains frame, parity and break status information for the top
+ * four bytes in the RX FIFO.
+ *
+ * Receiver FIFO Byte Status Register Bit Definition
+ * @{
+ */
+#define XUARTPS_RXBS_BYTE3_BRKE 0x00000800U /**< Byte3 Break Error */
+#define XUARTPS_RXBS_BYTE3_FRME 0x00000400U /**< Byte3 Frame Error */
+#define XUARTPS_RXBS_BYTE3_PARE 0x00000200U /**< Byte3 Parity Error */
+#define XUARTPS_RXBS_BYTE2_BRKE 0x00000100U /**< Byte2 Break Error */
+#define XUARTPS_RXBS_BYTE2_FRME 0x00000080U /**< Byte2 Frame Error */
+#define XUARTPS_RXBS_BYTE2_PARE 0x00000040U /**< Byte2 Parity Error */
+#define XUARTPS_RXBS_BYTE1_BRKE 0x00000020U /**< Byte1 Break Error */
+#define XUARTPS_RXBS_BYTE1_FRME 0x00000010U /**< Byte1 Frame Error */
+#define XUARTPS_RXBS_BYTE1_PARE 0x00000008U /**< Byte1 Parity Error */
+#define XUARTPS_RXBS_BYTE0_BRKE 0x00000004U /**< Byte0 Break Error */
+#define XUARTPS_RXBS_BYTE0_FRME 0x00000002U /**< Byte0 Frame Error */
+#define XUARTPS_RXBS_BYTE0_PARE 0x00000001U /**< Byte0 Parity Error */
+#define XUARTPS_RXBS_MASK 0x00000007U /**< 3 bit RX byte status mask */
+/* @} */
+
+
+/*
+ * Defines for backwards compatibility, will be removed
+ * in the next version of the driver
+ */
+#define XUARTPS_MEDEMSR_DCDX XUARTPS_MODEMSR_DDCD
+#define XUARTPS_MEDEMSR_RIX XUARTPS_MODEMSR_TERI
+#define XUARTPS_MEDEMSR_DSRX XUARTPS_MODEMSR_DDSR
+#define XUARTPS_MEDEMSR_CTSX XUARTPS_MODEMSR_DCTS
+
+
+
+/**************************** Type Definitions *******************************/
+
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/****************************************************************************/
+/**
+* Read a UART register.
+*
+* @param BaseAddress contains the base address of the device.
+* @param RegOffset contains the offset from the base address of the
+* device.
+*
+* @return The value read from the register.
+*
+* @note C-Style signature:
+* u32 XUartPs_ReadReg(u32 BaseAddress, int RegOffset)
+*
+******************************************************************************/
+#define XUartPs_ReadReg(BaseAddress, RegOffset) \
+ Xil_In32((BaseAddress) + (u32)(RegOffset))
+
+/***************************************************************************/
+/**
+* Write a UART register.
+*
+* @param BaseAddress contains the base address of the device.
+* @param RegOffset contains the offset from the base address of the
+* device.
+* @param RegisterValue is the value to be written to the register.
+*
+* @return None.
+*
+* @note C-Style signature:
+* void XUartPs_WriteReg(u32 BaseAddress, int RegOffset,
+* u16 RegisterValue)
+*
+******************************************************************************/
+#define XUartPs_WriteReg(BaseAddress, RegOffset, RegisterValue) \
+ Xil_Out32((BaseAddress) + (u32)(RegOffset), (u32)(RegisterValue))
+
+/****************************************************************************/
+/**
+* Determine if there is receive data in the receiver and/or FIFO.
+*
+* @param BaseAddress contains the base address of the device.
+*
+* @return TRUE if there is receive data, FALSE otherwise.
+*
+* @note C-Style signature:
+* u32 XUartPs_IsReceiveData(u32 BaseAddress)
+*
+******************************************************************************/
+#define XUartPs_IsReceiveData(BaseAddress) \
+ !((Xil_In32((BaseAddress) + XUARTPS_SR_OFFSET) & \
+ (u32)XUARTPS_SR_RXEMPTY) == (u32)XUARTPS_SR_RXEMPTY)
+
+/****************************************************************************/
+/**
+* Determine if a byte of data can be sent with the transmitter.
+*
+* @param BaseAddress contains the base address of the device.
+*
+* @return TRUE if the TX FIFO is full, FALSE if a byte can be put in the
+* FIFO.
+*
+* @note C-Style signature:
+* u32 XUartPs_IsTransmitFull(u32 BaseAddress)
+*
+******************************************************************************/
+#define XUartPs_IsTransmitFull(BaseAddress) \
+ ((Xil_In32((BaseAddress) + XUARTPS_SR_OFFSET) & \
+ (u32)XUARTPS_SR_TXFULL) == (u32)XUARTPS_SR_TXFULL)
+
+/************************** Function Prototypes ******************************/
+
+void XUartPs_SendByte(u32 BaseAddress, u8 Data);
+
+u8 XUartPs_RecvByte(u32 BaseAddress);
+
+void XUartPs_ResetHw(u32 BaseAddress);
+
+/************************** Variable Definitions *****************************/
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* end of protection macro */
+/** @} */
diff --git a/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/uartps_v3_8/src/xuartps_intr.c b/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/uartps_v3_8/src/xuartps_intr.c
new file mode 100644
index 0000000..45b06a6
--- /dev/null
+++ b/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/uartps_v3_8/src/xuartps_intr.c
@@ -0,0 +1,445 @@
+/******************************************************************************
+*
+* Copyright (C) 2010 - 2018 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+* THE SOFTWARE.
+*
+*
+*
+******************************************************************************/
+/****************************************************************************/
+/**
+*
+* @file xuartps_intr.c
+* @addtogroup uartps_v3_8
+* @{
+*
+* This file contains the functions for interrupt handling
+*
+* <pre>
+* MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ----- ------ -------- -----------------------------------------------
+* 1.00 drg/jz 01/13/10 First Release
+* 3.00 kvn 02/13/15 Modified code for MISRA-C:2012 compliance.
+* 3.1 kvn 04/10/15 Modified code for latest RTL changes.
+* 3.7 aru 08/17/18 Resolved MISRA-C mandatory violations.(CR#1007755)
+* </pre>
+*
+*****************************************************************************/
+
+/***************************** Include Files ********************************/
+
+#include "xuartps.h"
+
+/************************** Constant Definitions ****************************/
+
+/**************************** Type Definitions ******************************/
+
+/***************** Macros (Inline Functions) Definitions ********************/
+
+/************************** Function Prototypes *****************************/
+
+static void ReceiveDataHandler(XUartPs *InstancePtr);
+static void SendDataHandler(XUartPs *InstancePtr, u32 IsrStatus);
+static void ReceiveErrorHandler(XUartPs *InstancePtr, u32 IsrStatus);
+static void ReceiveTimeoutHandler(XUartPs *InstancePtr);
+static void ModemHandler(XUartPs *InstancePtr);
+
+
+/* Internal function prototypes implemented in xuartps.c */
+extern u32 XUartPs_ReceiveBuffer(XUartPs *InstancePtr);
+extern u32 XUartPs_SendBuffer(XUartPs *InstancePtr);
+
+/************************** Variable Definitions ****************************/
+
+typedef void (*Handler)(XUartPs *InstancePtr);
+
+/****************************************************************************/
+/**
+*
+* This function gets the interrupt mask
+*
+* @param InstancePtr is a pointer to the XUartPs instance.
+*
+* @return
+* The current interrupt mask. The mask indicates which interrupts
+* are enabled.
+*
+* @note None.
+*
+*****************************************************************************/
+u32 XUartPs_GetInterruptMask(XUartPs *InstancePtr)
+{
+ /* Assert validates the input argument */
+ Xil_AssertNonvoid(InstancePtr != NULL);
+
+ /* Read the Interrupt Mask register */
+ return (XUartPs_ReadReg(InstancePtr->Config.BaseAddress,
+ XUARTPS_IMR_OFFSET));
+}
+
+/****************************************************************************/
+/**
+*
+* This function sets the interrupt mask.
+*
+* @param InstancePtr is a pointer to the XUartPs instance
+* @param Mask contains the interrupts to be enabled or disabled.
+* A '1' enables an interrupt, and a '0' disables.
+*
+* @return None.
+*
+* @note None.
+*
+*****************************************************************************/
+void XUartPs_SetInterruptMask(XUartPs *InstancePtr, u32 Mask)
+{
+ u32 TempMask = Mask;
+ /* Assert validates the input arguments */
+ Xil_AssertVoid(InstancePtr != NULL);
+
+ TempMask &= (u32)XUARTPS_IXR_MASK;
+
+ /* Write the mask to the IER Register */
+ XUartPs_WriteReg(InstancePtr->Config.BaseAddress,
+ XUARTPS_IER_OFFSET, TempMask);
+
+ /* Write the inverse of the Mask to the IDR register */
+ XUartPs_WriteReg(InstancePtr->Config.BaseAddress,
+ XUARTPS_IDR_OFFSET, (~TempMask));
+
+}
+
+/****************************************************************************/
+/**
+*
+* This function sets the handler that will be called when an event (interrupt)
+* occurs that needs application's attention.
+*
+* @param InstancePtr is a pointer to the XUartPs instance
+* @param FuncPtr is the pointer to the callback function.
+* @param CallBackRef is the upper layer callback reference passed back
+* when the callback function is invoked.
+*
+* @return None.
+*
+* @note
+*
+* There is no assert on the CallBackRef since the driver doesn't know what it
+* is (nor should it)
+*
+*****************************************************************************/
+void XUartPs_SetHandler(XUartPs *InstancePtr, XUartPs_Handler FuncPtr,
+ void *CallBackRef)
+{
+ /*
+ * Asserts validate the input arguments
+ * CallBackRef not checked, no way to know what is valid
+ */
+ Xil_AssertVoid(InstancePtr != NULL);
+ Xil_AssertVoid(FuncPtr != NULL);
+ Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+ InstancePtr->Handler = (XUartPs_Handler)FuncPtr;
+ InstancePtr->CallBackRef = CallBackRef;
+}
+
+/****************************************************************************/
+/**
+*
+* This function is the interrupt handler for the driver.
+* It must be connected to an interrupt system by the application such that it
+* can be called when an interrupt occurs.
+*
+* @param InstancePtr contains a pointer to the driver instance
+*
+* @return None.
+*
+* @note None.
+*
+******************************************************************************/
+void XUartPs_InterruptHandler(XUartPs *InstancePtr)
+{
+ u32 IsrStatus;
+
+ Xil_AssertVoid(InstancePtr != NULL);
+ Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+ /*
+ * Read the interrupt ID register to determine which
+ * interrupt is active
+ */
+ IsrStatus = XUartPs_ReadReg(InstancePtr->Config.BaseAddress,
+ XUARTPS_IMR_OFFSET);
+
+ IsrStatus &= XUartPs_ReadReg(InstancePtr->Config.BaseAddress,
+ XUARTPS_ISR_OFFSET);
+
+ /* Dispatch an appropriate handler. */
+ if((IsrStatus & ((u32)XUARTPS_IXR_RXOVR | (u32)XUARTPS_IXR_RXEMPTY |
+ (u32)XUARTPS_IXR_RXFULL)) != (u32)0) {
+ /* Received data interrupt */
+ ReceiveDataHandler(InstancePtr);
+ }
+
+ if((IsrStatus & ((u32)XUARTPS_IXR_TXEMPTY | (u32)XUARTPS_IXR_TXFULL))
+ != (u32)0) {
+ /* Transmit data interrupt */
+ SendDataHandler(InstancePtr, IsrStatus);
+ }
+
+ /* XUARTPS_IXR_RBRK is applicable only for Zynq Ultrascale+ MP */
+ if ((IsrStatus & ((u32)XUARTPS_IXR_OVER | (u32)XUARTPS_IXR_FRAMING |
+ (u32)XUARTPS_IXR_PARITY | (u32)XUARTPS_IXR_RBRK)) != (u32)0) {
+ /* Received Error Status interrupt */
+ ReceiveErrorHandler(InstancePtr, IsrStatus);
+ }
+
+ if((IsrStatus & ((u32)XUARTPS_IXR_TOUT)) != (u32)0) {
+ /* Received Timeout interrupt */
+ ReceiveTimeoutHandler(InstancePtr);
+ }
+
+ if((IsrStatus & ((u32)XUARTPS_IXR_DMS)) != (u32)0) {
+ /* Modem status interrupt */
+ ModemHandler(InstancePtr);
+ }
+
+ /* Clear the interrupt status. */
+ XUartPs_WriteReg(InstancePtr->Config.BaseAddress, XUARTPS_ISR_OFFSET,
+ IsrStatus);
+
+}
+
+/****************************************************************************/
+/*
+*
+* This function handles interrupts for receive errors which include
+* overrun errors, framing errors, parity errors, and the break interrupt.
+*
+* @param InstancePtr is a pointer to the XUartPs instance.
+*
+* @return None.
+*
+* @note None.
+*
+*****************************************************************************/
+static void ReceiveErrorHandler(XUartPs *InstancePtr, u32 IsrStatus)
+{
+ u32 EventData;
+ u32 Event;
+
+ InstancePtr->is_rxbs_error = 0;
+
+ if ((InstancePtr->Platform == XPLAT_ZYNQ_ULTRA_MP) &&
+ (IsrStatus & ((u32)XUARTPS_IXR_PARITY | (u32)XUARTPS_IXR_RBRK
+ | (u32)XUARTPS_IXR_FRAMING))) {
+ InstancePtr->is_rxbs_error = 1;
+ }
+ /*
+ * If there are bytes still to be received in the specified buffer
+ * go ahead and receive them. Removing bytes from the RX FIFO will
+ * clear the interrupt.
+ */
+
+ (void)XUartPs_ReceiveBuffer(InstancePtr);
+
+ if (!(InstancePtr->is_rxbs_error)) {
+ Event = XUARTPS_EVENT_RECV_ERROR;
+ EventData = InstancePtr->ReceiveBuffer.RequestedBytes -
+ InstancePtr->ReceiveBuffer.RemainingBytes;
+
+ /*
+ * Call the application handler to indicate that there is a receive
+ * error or a break interrupt, if the application cares about the
+ * error it call a function to get the last errors.
+ */
+ InstancePtr->Handler(InstancePtr->CallBackRef,
+ Event,
+ EventData);
+ }
+}
+
+/****************************************************************************/
+/**
+*
+* This function handles the receive timeout interrupt. This interrupt occurs
+* whenever a number of bytes have been present in the RX FIFO and the receive
+* data line has been idle for at lease 4 or more character times, (the timeout
+* is set using XUartPs_SetrecvTimeout() function).
+*
+* @param InstancePtr is a pointer to the XUartPs instance
+*
+* @return None.
+*
+* @note None.
+*
+*****************************************************************************/
+static void ReceiveTimeoutHandler(XUartPs *InstancePtr)
+{
+ u32 Event;
+
+ /*
+ * If there are bytes still to be received in the specified buffer
+ * go ahead and receive them. Removing bytes from the RX FIFO will
+ * clear the interrupt.
+ */
+ if (InstancePtr->ReceiveBuffer.RemainingBytes != (u32)0) {
+ (void)XUartPs_ReceiveBuffer(InstancePtr);
+ }
+
+ /*
+ * If there are no more bytes to receive then indicate that this is
+ * not a receive timeout but the end of the buffer reached, a timeout
+ * normally occurs if # of bytes is not divisible by FIFO threshold,
+ * don't rely on previous test of remaining bytes since receive
+ * function updates it
+ */
+ if (InstancePtr->ReceiveBuffer.RemainingBytes != (u32)0) {
+ Event = XUARTPS_EVENT_RECV_TOUT;
+ } else {
+ Event = XUARTPS_EVENT_RECV_DATA;
+ }
+
+ /*
+ * Call the application handler to indicate that there is a receive
+ * timeout or data event
+ */
+ InstancePtr->Handler(InstancePtr->CallBackRef, Event,
+ InstancePtr->ReceiveBuffer.RequestedBytes -
+ InstancePtr->ReceiveBuffer.RemainingBytes);
+
+}
+/****************************************************************************/
+/**
+*
+* This function handles the interrupt when data is in RX FIFO.
+*
+* @param InstancePtr is a pointer to the XUartPs instance
+*
+* @return None.
+*
+* @note None.
+*
+*****************************************************************************/
+static void ReceiveDataHandler(XUartPs *InstancePtr)
+{
+ /*
+ * If there are bytes still to be received in the specified buffer
+ * go ahead and receive them. Removing bytes from the RX FIFO will
+ * clear the interrupt.
+ */
+ if (InstancePtr->ReceiveBuffer.RemainingBytes != (u32)0) {
+ (void)XUartPs_ReceiveBuffer(InstancePtr);
+ }
+
+ /* If the last byte of a message was received then call the application
+ * handler, this code should not use an else from the previous check of
+ * the number of bytes to receive because the call to receive the buffer
+ * updates the bytes ramained
+ */
+ if (InstancePtr->ReceiveBuffer.RemainingBytes == (u32)0) {
+ InstancePtr->Handler(InstancePtr->CallBackRef,
+ XUARTPS_EVENT_RECV_DATA,
+ (InstancePtr->ReceiveBuffer.RequestedBytes -
+ InstancePtr->ReceiveBuffer.RemainingBytes));
+ }
+
+}
+
+/****************************************************************************/
+/**
+*
+* This function handles the interrupt when data has been sent, the transmit
+* FIFO is empty (transmitter holding register).
+*
+* @param InstancePtr is a pointer to the XUartPs instance
+* @param IsrStatus is the register value for channel status register
+*
+* @return None.
+*
+* @note None.
+*
+*****************************************************************************/
+static void SendDataHandler(XUartPs *InstancePtr, u32 IsrStatus)
+{
+
+ /*
+ * If there are not bytes to be sent from the specified buffer then disable
+ * the transmit interrupt so it will stop interrupting as it interrupts
+ * any time the FIFO is empty
+ */
+ if (InstancePtr->SendBuffer.RemainingBytes == (u32)0) {
+ XUartPs_WriteReg(InstancePtr->Config.BaseAddress,
+ XUARTPS_IDR_OFFSET,
+ ((u32)XUARTPS_IXR_TXEMPTY | (u32)XUARTPS_IXR_TXFULL));
+
+ /* Call the application handler to indicate the sending is done */
+ InstancePtr->Handler(InstancePtr->CallBackRef,
+ XUARTPS_EVENT_SENT_DATA,
+ InstancePtr->SendBuffer.RequestedBytes -
+ InstancePtr->SendBuffer.RemainingBytes);
+ }
+
+ /* If TX FIFO is empty, send more. */
+ else if((IsrStatus & ((u32)XUARTPS_IXR_TXEMPTY)) != (u32)0) {
+ (void)XUartPs_SendBuffer(InstancePtr);
+ }
+ else {
+ /* Else with dummy entry for MISRA-C Compliance.*/
+ ;
+ }
+}
+
+/****************************************************************************/
+/**
+*
+* This function handles modem interrupts. It does not do any processing
+* except to call the application handler to indicate a modem event.
+*
+* @param InstancePtr is a pointer to the XUartPs instance
+*
+* @return None.
+*
+* @note None.
+*
+*****************************************************************************/
+static void ModemHandler(XUartPs *InstancePtr)
+{
+ u32 MsrRegister;
+
+ /*
+ * Read the modem status register so that the interrupt is acknowledged
+ * and it can be passed to the callback handler with the event
+ */
+ MsrRegister = XUartPs_ReadReg(InstancePtr->Config.BaseAddress,
+ XUARTPS_MODEMSR_OFFSET);
+
+ /*
+ * Call the application handler to indicate the modem status changed,
+ * passing the modem status and the event data in the call
+ */
+ InstancePtr->Handler(InstancePtr->CallBackRef,
+ XUARTPS_EVENT_MODEM,
+ MsrRegister);
+
+}
+/** @} */
diff --git a/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/uartps_v3_8/src/xuartps_options.c b/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/uartps_v3_8/src/xuartps_options.c
new file mode 100644
index 0000000..4f232d0
--- /dev/null
+++ b/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/uartps_v3_8/src/xuartps_options.c
@@ -0,0 +1,758 @@
+/******************************************************************************
+*
+* Copyright (C) 2010 - 2015 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+* THE SOFTWARE.
+*
+*
+*
+******************************************************************************/
+/****************************************************************************/
+/**
+*
+* @file xuartps_options.c
+* @addtogroup uartps_v3_8
+* @{
+*
+* The implementation of the options functions for the XUartPs driver.
+*
+* <pre>
+* MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ----- ------ -------- -----------------------------------------------
+* 1.00 drg/jz 01/13/10 First Release
+* 1.00 sdm 09/27/11 Fixed a bug in XUartPs_SetFlowDelay where the input
+* value was not being written to the register.
+* 3.00 kvn 02/13/15 Modified code for MISRA-C:2012 compliance.
+* 3.2 rk 07/20/16 Modified the logic for transmission break bit set
+*
+* </pre>
+*
+*****************************************************************************/
+
+/***************************** Include Files ********************************/
+
+#include "xuartps.h"
+
+/************************** Constant Definitions ****************************/
+
+/**************************** Type Definitions ******************************/
+
+/***************** Macros (Inline Functions) Definitions ********************/
+
+/************************** Variable Definitions ****************************/
+/*
+ * The following data type is a map from an option to the offset in the
+ * register to which it belongs as well as its bit mask in that register.
+ */
+typedef struct {
+ u16 Option;
+ u16 RegisterOffset;
+ u32 Mask;
+} Mapping;
+
+/*
+ * Create the table which contains options which are to be processed to get/set
+ * the options. These options are table driven to allow easy maintenance and
+ * expansion of the options.
+ */
+
+static Mapping OptionsTable[] = {
+ {XUARTPS_OPTION_SET_BREAK, XUARTPS_CR_OFFSET, XUARTPS_CR_STARTBRK},
+ {XUARTPS_OPTION_STOP_BREAK, XUARTPS_CR_OFFSET, XUARTPS_CR_STOPBRK},
+ {XUARTPS_OPTION_RESET_TMOUT, XUARTPS_CR_OFFSET, XUARTPS_CR_TORST},
+ {XUARTPS_OPTION_RESET_TX, XUARTPS_CR_OFFSET, XUARTPS_CR_TXRST},
+ {XUARTPS_OPTION_RESET_RX, XUARTPS_CR_OFFSET, XUARTPS_CR_RXRST},
+ {XUARTPS_OPTION_ASSERT_RTS, XUARTPS_MODEMCR_OFFSET,
+ XUARTPS_MODEMCR_RTS},
+ {XUARTPS_OPTION_ASSERT_DTR, XUARTPS_MODEMCR_OFFSET,
+ XUARTPS_MODEMCR_DTR},
+ {XUARTPS_OPTION_SET_FCM, XUARTPS_MODEMCR_OFFSET, XUARTPS_MODEMCR_FCM}
+};
+
+/* Create a constant for the number of entries in the table */
+
+#define XUARTPS_NUM_OPTIONS (sizeof(OptionsTable) / sizeof(Mapping))
+
+/************************** Function Prototypes *****************************/
+
+/****************************************************************************/
+/**
+*
+* Gets the options for the specified driver instance. The options are
+* implemented as bit masks such that multiple options may be enabled or
+* disabled simultaneously.
+*
+* @param InstancePtr is a pointer to the XUartPs instance.
+*
+* @return
+*
+* The current options for the UART. The options are bit masks that are
+* contained in the file xuartps.h and named XUARTPS_OPTION_*.
+*
+* @note None.
+*
+*****************************************************************************/
+u16 XUartPs_GetOptions(XUartPs *InstancePtr)
+{
+ u16 Options = 0U;
+ u32 Register;
+ u32 Index;
+
+ /* Assert validates the input arguments */
+ Xil_AssertNonvoid(InstancePtr != NULL);
+ Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+ /*
+ * Loop through the options table to map the physical options in the
+ * registers of the UART to the logical options to be returned
+ */
+ for (Index = 0U; Index < XUARTPS_NUM_OPTIONS; Index++) {
+ Register = XUartPs_ReadReg(InstancePtr->Config.BaseAddress,
+ OptionsTable[Index].
+ RegisterOffset);
+
+ /*
+ * If the bit in the register which correlates to the option
+ * is set, then set the corresponding bit in the options,
+ * ignoring any bits which are zero since the options variable
+ * is initialized to zero
+ */
+ if ((Register & OptionsTable[Index].Mask) != (u32)0) {
+ Options |= OptionsTable[Index].Option;
+ }
+ }
+
+ return Options;
+}
+
+/****************************************************************************/
+/**
+*
+* Sets the options for the specified driver instance. The options are
+* implemented as bit masks such that multiple options may be enabled or
+* disabled simultaneously.
+*
+* The GetOptions function may be called to retrieve the currently enabled
+* options. The result is ORed in the desired new settings to be enabled and
+* ANDed with the inverse to clear the settings to be disabled. The resulting
+* value is then used as the options for the SetOption function call.
+*
+* @param InstancePtr is a pointer to the XUartPs instance.
+* @param Options contains the options to be set which are bit masks
+* contained in the file xuartps.h and named XUARTPS_OPTION_*.
+*
+* @return None.
+*
+* @note None.
+*
+*****************************************************************************/
+void XUartPs_SetOptions(XUartPs *InstancePtr, u16 Options)
+{
+ u32 Index;
+ u32 Register;
+
+ /* Assert validates the input arguments */
+ Xil_AssertVoid(InstancePtr != NULL);
+ Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+ /*
+ * Loop through the options table to map the logical options to the
+ * physical options in the registers of the UART.
+ */
+ for (Index = 0U; Index < XUARTPS_NUM_OPTIONS; Index++) {
+
+ /*
+ * Read the register which contains option so that the register
+ * can be changed without destoying any other bits of the
+ * register.
+ */
+ Register = XUartPs_ReadReg(InstancePtr->Config.BaseAddress,
+ OptionsTable[Index].
+ RegisterOffset);
+
+ /*
+ * If the option is set in the input, then set the corresponding
+ * bit in the specified register, otherwise clear the bit in
+ * the register.
+ */
+ if ((Options & OptionsTable[Index].Option) != (u16)0) {
+ if(OptionsTable[Index].Option == XUARTPS_OPTION_SET_BREAK)
+ Register &= ~XUARTPS_CR_STOPBRK;
+ Register |= OptionsTable[Index].Mask;
+ }
+ else {
+ Register &= ~OptionsTable[Index].Mask;
+ }
+
+ /* Write the new value to the register to set the option */
+ XUartPs_WriteReg(InstancePtr->Config.BaseAddress,
+ OptionsTable[Index].RegisterOffset,
+ Register);
+ }
+
+}
+
+/****************************************************************************/
+/**
+*
+* This function gets the receive FIFO trigger level. The receive trigger
+* level indicates the number of bytes in the receive FIFO that cause a receive
+* data event (interrupt) to be generated.
+*
+* @param InstancePtr is a pointer to the XUartPs instance.
+*
+* @return The current receive FIFO trigger level. This is a value
+* from 0-31.
+*
+* @note None.
+*
+*****************************************************************************/
+u8 XUartPs_GetFifoThreshold(XUartPs *InstancePtr)
+{
+ u8 RtrigRegister;
+
+ /* Assert validates the input arguments */
+ Xil_AssertNonvoid(InstancePtr != NULL);
+ Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+ /*
+ * Read the value of the FIFO control register so that the threshold
+ * can be retrieved, this read takes special register processing
+ */
+ RtrigRegister = (u8) XUartPs_ReadReg(InstancePtr->Config.BaseAddress,
+ XUARTPS_RXWM_OFFSET);
+
+ /* Return only the trigger level from the register value */
+
+ RtrigRegister &= (u8)XUARTPS_RXWM_MASK;
+ return RtrigRegister;
+}
+
+/****************************************************************************/
+/**
+*
+* This functions sets the receive FIFO trigger level. The receive trigger
+* level specifies the number of bytes in the receive FIFO that cause a receive
+* data event (interrupt) to be generated.
+*
+* @param InstancePtr is a pointer to the XUartPs instance.
+* @param TriggerLevel contains the trigger level to set.
+*
+* @return None
+*
+* @note None.
+*
+*****************************************************************************/
+void XUartPs_SetFifoThreshold(XUartPs *InstancePtr, u8 TriggerLevel)
+{
+ u32 RtrigRegister;
+
+ /* Assert validates the input arguments */
+ Xil_AssertVoid(InstancePtr != NULL);
+ Xil_AssertVoid(TriggerLevel <= (u8)XUARTPS_RXWM_MASK);
+ Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+ RtrigRegister = ((u32)TriggerLevel) & (u32)XUARTPS_RXWM_MASK;
+
+ /*
+ * Write the new value for the FIFO control register to it such that the
+ * threshold is changed
+ */
+ XUartPs_WriteReg(InstancePtr->Config.BaseAddress,
+ XUARTPS_RXWM_OFFSET, RtrigRegister);
+
+}
+
+/****************************************************************************/
+/**
+*
+* This function gets the modem status from the specified UART. The modem
+* status indicates any changes of the modem signals. This function allows
+* the modem status to be read in a polled mode. The modem status is updated
+* whenever it is read such that reading it twice may not yield the same
+* results.
+*
+* @param InstancePtr is a pointer to the XUartPs instance.
+*
+* @return
+*
+* The modem status which are bit masks that are contained in the file
+* xuartps.h and named XUARTPS_MODEM_*.
+*
+* @note
+*
+* The bit masks used for the modem status are the exact bits of the modem
+* status register with no abstraction.
+*
+*****************************************************************************/
+u16 XUartPs_GetModemStatus(XUartPs *InstancePtr)
+{
+ u32 ModemStatusRegister;
+ u16 TmpRegister;
+ /* Assert validates the input arguments */
+ Xil_AssertNonvoid(InstancePtr != NULL);
+ Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+ /* Read the modem status register to return
+ */
+ ModemStatusRegister = XUartPs_ReadReg(InstancePtr->Config.BaseAddress,
+ XUARTPS_MODEMSR_OFFSET);
+ TmpRegister = (u16)ModemStatusRegister;
+ return TmpRegister;
+}
+
+/****************************************************************************/
+/**
+*
+* This function determines if the specified UART is sending data.
+*
+* @param InstancePtr is a pointer to the XUartPs instance.
+*
+* @return
+* - TRUE if the UART is sending data
+* - FALSE if UART is not sending data
+*
+* @note None.
+*
+*****************************************************************************/
+u32 XUartPs_IsSending(XUartPs *InstancePtr)
+{
+ u32 ChanStatRegister;
+ u32 ChanTmpSRegister;
+ u32 ActiveResult;
+ u32 EmptyResult;
+
+ /* Assert validates the input arguments */
+ Xil_AssertNonvoid(InstancePtr != NULL);
+ Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+ /*
+ * Read the channel status register to determine if the transmitter is
+ * active
+ */
+ ChanStatRegister = XUartPs_ReadReg(InstancePtr->Config.BaseAddress,
+ XUARTPS_SR_OFFSET);
+
+ /*
+ * If the transmitter is active, or the TX FIFO is not empty, then indicate
+ * that the UART is still sending some data
+ */
+ ActiveResult = ChanStatRegister & ((u32)XUARTPS_SR_TACTIVE);
+ EmptyResult = ChanStatRegister & ((u32)XUARTPS_SR_TXEMPTY);
+ ChanTmpSRegister = (((u32)XUARTPS_SR_TACTIVE) == ActiveResult) ||
+ (((u32)XUARTPS_SR_TXEMPTY) != EmptyResult);
+
+ return ChanTmpSRegister;
+}
+
+/****************************************************************************/
+/**
+*
+* This function gets the operational mode of the UART. The UART can operate
+* in one of four modes: Normal, Local Loopback, Remote Loopback, or automatic
+* echo.
+*
+* @param InstancePtr is a pointer to the XUartPs instance.
+*
+* @return
+*
+* The operational mode is specified by constants defined in xuartps.h. The
+* constants are named XUARTPS_OPER_MODE_*
+*
+* @note None.
+*
+*****************************************************************************/
+u8 XUartPs_GetOperMode(XUartPs *InstancePtr)
+{
+ u32 ModeRegister;
+ u8 OperMode;
+
+ /* Assert validates the input arguments */
+ Xil_AssertNonvoid(InstancePtr != NULL);
+ Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+ /* Read the Mode register. */
+ ModeRegister =
+ XUartPs_ReadReg(InstancePtr->Config.BaseAddress,
+ XUARTPS_MR_OFFSET);
+
+ ModeRegister &= (u32)XUARTPS_MR_CHMODE_MASK;
+ /* Return the constant */
+ switch (ModeRegister) {
+ case XUARTPS_MR_CHMODE_NORM:
+ OperMode = XUARTPS_OPER_MODE_NORMAL;
+ break;
+ case XUARTPS_MR_CHMODE_ECHO:
+ OperMode = XUARTPS_OPER_MODE_AUTO_ECHO;
+ break;
+ case XUARTPS_MR_CHMODE_L_LOOP:
+ OperMode = XUARTPS_OPER_MODE_LOCAL_LOOP;
+ break;
+ case XUARTPS_MR_CHMODE_R_LOOP:
+ OperMode = XUARTPS_OPER_MODE_REMOTE_LOOP;
+ break;
+ default:
+ OperMode = (u8) ((ModeRegister & (u32)XUARTPS_MR_CHMODE_MASK) >>
+ XUARTPS_MR_CHMODE_SHIFT);
+ break;
+ }
+
+ return OperMode;
+}
+
+/****************************************************************************/
+/**
+*
+* This function sets the operational mode of the UART. The UART can operate
+* in one of four modes: Normal, Local Loopback, Remote Loopback, or automatic
+* echo.
+*
+* @param InstancePtr is a pointer to the XUartPs instance.
+* @param OperationMode is the mode of the UART.
+*
+* @return None.
+*
+* @note None.
+*
+*****************************************************************************/
+void XUartPs_SetOperMode(XUartPs *InstancePtr, u8 OperationMode)
+{
+ u32 ModeRegister;
+
+ /* Assert validates the input arguments. */
+ Xil_AssertVoid(InstancePtr != NULL);
+ Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+ Xil_AssertVoid(OperationMode <= XUARTPS_OPER_MODE_REMOTE_LOOP);
+
+ /* Read the Mode register. */
+ ModeRegister =
+ XUartPs_ReadReg(InstancePtr->Config.BaseAddress,
+ XUARTPS_MR_OFFSET);
+
+ /* Set the correct value by masking the bits, then ORing the const. */
+ ModeRegister &= (u32)(~XUARTPS_MR_CHMODE_MASK);
+
+ switch (OperationMode) {
+ case XUARTPS_OPER_MODE_NORMAL:
+ ModeRegister |= (u32)XUARTPS_MR_CHMODE_NORM;
+ break;
+ case XUARTPS_OPER_MODE_AUTO_ECHO:
+ ModeRegister |= (u32)XUARTPS_MR_CHMODE_ECHO;
+ break;
+ case XUARTPS_OPER_MODE_LOCAL_LOOP:
+ ModeRegister |= (u32)XUARTPS_MR_CHMODE_L_LOOP;
+ break;
+ case XUARTPS_OPER_MODE_REMOTE_LOOP:
+ ModeRegister |= (u32)XUARTPS_MR_CHMODE_R_LOOP;
+ break;
+ default:
+ /* Default case made for MISRA-C Compliance. */
+ break;
+ }
+
+ XUartPs_WriteReg(InstancePtr->Config.BaseAddress, XUARTPS_MR_OFFSET,
+ ModeRegister);
+
+}
+
+/****************************************************************************/
+/**
+*
+* This function sets the Flow Delay.
+* 0 - 3: Flow delay inactive
+* 4 - 32: If Flow Control mode is enabled, UART_rtsN is deactivated when the
+* receive FIFO fills to this level.
+*
+* @param InstancePtr is a pointer to the XUartPs instance.
+*
+* @return
+*
+* The Flow Delay is specified by constants defined in xuartps_hw.h. The
+* constants are named XUARTPS_FLOWDEL*
+*
+* @note None.
+*
+*****************************************************************************/
+u8 XUartPs_GetFlowDelay(XUartPs *InstancePtr)
+{
+ u32 FdelTmpRegister;
+
+ /* Assert validates the input arguments */
+ Xil_AssertNonvoid(InstancePtr != NULL);
+ Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+ /* Read the Mode register. */
+ FdelTmpRegister = XUartPs_ReadReg(InstancePtr->Config.BaseAddress,
+ XUARTPS_FLOWDEL_OFFSET);
+
+ /* Return the contents of the flow delay register */
+ FdelTmpRegister = (u8)(FdelTmpRegister & (u32)XUARTPS_FLOWDEL_MASK);
+ return FdelTmpRegister;
+}
+
+/****************************************************************************/
+/**
+*
+* This function sets the Flow Delay.
+* 0 - 3: Flow delay inactive
+* 4 - 63: If Flow Control mode is enabled, UART_rtsN is deactivated when the
+* receive FIFO fills to this level.
+*
+* @param InstancePtr is a pointer to the XUartPs instance.
+* @param FlowDelayValue is the Setting for the flow delay.
+*
+* @return None.
+*
+* @note None.
+*
+*****************************************************************************/
+void XUartPs_SetFlowDelay(XUartPs *InstancePtr, u8 FlowDelayValue)
+{
+ u32 FdelRegister;
+
+ /* Assert validates the input arguments */
+ Xil_AssertVoid(InstancePtr != NULL);
+ Xil_AssertVoid(FlowDelayValue > (u8)XUARTPS_FLOWDEL_MASK);
+ Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+ /*
+ * Set the correct value by shifting the input constant, then masking
+ * the bits
+ */
+ FdelRegister = ((u32)FlowDelayValue) & (u32)XUARTPS_FLOWDEL_MASK;
+
+ XUartPs_WriteReg(InstancePtr->Config.BaseAddress,
+ XUARTPS_FLOWDEL_OFFSET, FdelRegister);
+
+}
+
+/****************************************************************************/
+/**
+*
+* This function gets the Receive Timeout of the UART.
+*
+* @param InstancePtr is a pointer to the XUartPs instance.
+*
+* @return The current setting for receive time out.
+*
+* @note None.
+*
+*****************************************************************************/
+u8 XUartPs_GetRecvTimeout(XUartPs *InstancePtr)
+{
+ u32 RtoRegister;
+ u8 RtoRTmpRegister;
+
+ /* Assert validates the input arguments */
+ Xil_AssertNonvoid(InstancePtr != NULL);
+ Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+ /* Read the Receive Timeout register. */
+ RtoRegister = XUartPs_ReadReg(InstancePtr->Config.BaseAddress,
+ XUARTPS_RXTOUT_OFFSET);
+
+ /* Return the contents of the mode register shifted appropriately */
+ RtoRTmpRegister = (u8)(RtoRegister & (u32)XUARTPS_RXTOUT_MASK);
+ return RtoRTmpRegister;
+}
+
+/****************************************************************************/
+/**
+*
+* This function sets the Receive Timeout of the UART.
+*
+* @param InstancePtr is a pointer to the XUartPs instance.
+* @param RecvTimeout setting allows the UART to detect an idle connection
+* on the receiver data line.
+* Timeout duration = RecvTimeout x 4 x Bit Period. 0 disables the
+* timeout function.
+*
+* @return None.
+*
+* @note None.
+*
+*****************************************************************************/
+void XUartPs_SetRecvTimeout(XUartPs *InstancePtr, u8 RecvTimeout)
+{
+ u32 RtoRegister;
+
+ /* Assert validates the input arguments */
+ Xil_AssertVoid(InstancePtr != NULL);
+ Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+ /* Set the correct value by masking the bits */
+ RtoRegister = ((u32)RecvTimeout & (u32)XUARTPS_RXTOUT_MASK);
+
+ XUartPs_WriteReg(InstancePtr->Config.BaseAddress,
+ XUARTPS_RXTOUT_OFFSET, RtoRegister);
+
+ /* Configure CR to restart the receiver timeout counter */
+ RtoRegister =
+ XUartPs_ReadReg(InstancePtr->Config.BaseAddress,
+ XUARTPS_CR_OFFSET);
+ XUartPs_WriteReg(InstancePtr->Config.BaseAddress, XUARTPS_CR_OFFSET,
+ (RtoRegister | XUARTPS_CR_TORST));
+
+}
+/****************************************************************************/
+/**
+*
+* Sets the data format for the device. The data format includes the
+* baud rate, number of data bits, number of stop bits, and parity. It is the
+* caller's responsibility to ensure that the UART is not sending or receiving
+* data when this function is called.
+*
+* @param InstancePtr is a pointer to the XUartPs instance.
+* @param FormatPtr is a pointer to a format structure containing the data
+* format to be set.
+*
+* @return
+* - XST_SUCCESS if the data format was successfully set.
+* - XST_UART_BAUD_ERROR indicates the baud rate could not be
+* set because of the amount of error with the baud rate and
+* the input clock frequency.
+* - XST_INVALID_PARAM if one of the parameters was not valid.
+*
+* @note
+*
+* The data types in the format type, data bits and parity, are 32 bit fields
+* to prevent a compiler warning.
+* The asserts in this function will cause a warning if these fields are
+* bytes.
+* <br><br>
+*
+*****************************************************************************/
+s32 XUartPs_SetDataFormat(XUartPs *InstancePtr,
+ XUartPsFormat * FormatPtr)
+{
+ s32 Status;
+ u32 ModeRegister;
+
+ Xil_AssertNonvoid(InstancePtr != NULL);
+ Xil_AssertNonvoid(FormatPtr != NULL);
+ Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+ /* Verify the inputs specified are valid */
+ if ((FormatPtr->DataBits > ((u32)XUARTPS_FORMAT_6_BITS)) ||
+ (FormatPtr->StopBits > ((u8)XUARTPS_FORMAT_2_STOP_BIT)) ||
+ (FormatPtr->Parity > ((u32)XUARTPS_FORMAT_NO_PARITY))) {
+ Status = XST_INVALID_PARAM;
+ } else {
+
+ /*
+ * Try to set the baud rate and if it's not successful then don't
+ * continue altering the data format, this is done first to avoid the
+ * format from being altered when an error occurs
+ */
+ Status = XUartPs_SetBaudRate(InstancePtr, FormatPtr->BaudRate);
+ if (Status != (s32)XST_SUCCESS) {
+ ;
+ } else {
+
+ ModeRegister =
+ XUartPs_ReadReg(InstancePtr->Config.BaseAddress,
+ XUARTPS_MR_OFFSET);
+
+ /*
+ * Set the length of data (8,7,6) by first clearing out the bits
+ * that control it in the register, then set the length in the register
+ */
+ ModeRegister &= (u32)(~XUARTPS_MR_CHARLEN_MASK);
+ ModeRegister |= (FormatPtr->DataBits << XUARTPS_MR_CHARLEN_SHIFT);
+
+ /*
+ * Set the number of stop bits in the mode register by first clearing
+ * out the bits that control it in the register, then set the number
+ * of stop bits in the register.
+ */
+ ModeRegister &= (u32)(~XUARTPS_MR_STOPMODE_MASK);
+ ModeRegister |= (((u32)FormatPtr->StopBits) << XUARTPS_MR_STOPMODE_SHIFT);
+
+ /*
+ * Set the parity by first clearing out the bits that control it in the
+ * register, then set the bits in the register, the default is no parity
+ * after clearing the register bits
+ */
+ ModeRegister &= (u32)(~XUARTPS_MR_PARITY_MASK);
+ ModeRegister |= (FormatPtr->Parity << XUARTPS_MR_PARITY_SHIFT);
+
+ /* Update the mode register */
+ XUartPs_WriteReg(InstancePtr->Config.BaseAddress, XUARTPS_MR_OFFSET,
+ ModeRegister);
+
+ Status = XST_SUCCESS;
+ }
+ }
+ return Status;
+}
+
+/****************************************************************************/
+/**
+*
+* Gets the data format for the specified UART. The data format includes the
+* baud rate, number of data bits, number of stop bits, and parity.
+*
+* @param InstancePtr is a pointer to the XUartPs instance.
+* @param FormatPtr is a pointer to a format structure that will contain
+* the data format after this call completes.
+*
+* @return None.
+*
+* @note None.
+*
+*
+*****************************************************************************/
+void XUartPs_GetDataFormat(XUartPs *InstancePtr, XUartPsFormat * FormatPtr)
+{
+ u32 ModeRegister;
+
+
+ /* Assert validates the input arguments */
+ Xil_AssertVoid(InstancePtr != NULL);
+ Xil_AssertVoid(FormatPtr != NULL);
+ Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+ /*
+ * Get the baud rate from the instance, this is not retrieved from the
+ * hardware because it is only kept as a divisor such that it is more
+ * difficult to get back to the baud rate
+ */
+ FormatPtr->BaudRate = InstancePtr->BaudRate;
+
+ ModeRegister = XUartPs_ReadReg(InstancePtr->Config.BaseAddress,
+ XUARTPS_MR_OFFSET);
+
+ /* Get the length of data (8,7,6,5) */
+ FormatPtr->DataBits =
+ ((ModeRegister & (u32)XUARTPS_MR_CHARLEN_MASK) >>
+ XUARTPS_MR_CHARLEN_SHIFT);
+
+ /* Get the number of stop bits */
+ FormatPtr->StopBits =
+ (u8)((ModeRegister & (u32)XUARTPS_MR_STOPMODE_MASK) >>
+ XUARTPS_MR_STOPMODE_SHIFT);
+
+ /* Determine what parity is */
+ FormatPtr->Parity =
+ (u32)((ModeRegister & (u32)XUARTPS_MR_PARITY_MASK) >>
+ XUARTPS_MR_PARITY_SHIFT);
+}
+/** @} */
diff --git a/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/uartps_v3_8/src/xuartps_selftest.c b/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/uartps_v3_8/src/xuartps_selftest.c
new file mode 100644
index 0000000..0c230ce
--- /dev/null
+++ b/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/uartps_v3_8/src/xuartps_selftest.c
@@ -0,0 +1,160 @@
+/******************************************************************************
+*
+* Copyright (C) 2010 - 2015 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+* THE SOFTWARE.
+*
+*
+*
+******************************************************************************/
+/****************************************************************************/
+/**
+*
+* @file xuartps_selftest.c
+* @addtogroup uartps_v3_8
+* @{
+*
+* This file contains the self-test functions for the XUartPs driver.
+*
+* <pre>
+* MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ----- ------ -------- -----------------------------------------------
+* 1.00 drg/jz 01/13/10 First Release
+* 3.00 kvn 02/13/15 Modified code for MISRA-C:2012 compliance.
+* </pre>
+*
+******************************************************************************/
+
+/***************************** Include Files *********************************/
+
+#include "xstatus.h"
+#include "xuartps.h"
+
+/************************** Constant Definitions *****************************/
+
+
+/**************************** Type Definitions *******************************/
+
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+#define XUARTPS_TOTAL_BYTES (u8)32
+
+/************************** Variable Definitions *****************************/
+
+static u8 TestString[XUARTPS_TOTAL_BYTES]="abcdefghABCDEFGH012345677654321";
+static u8 ReturnString[XUARTPS_TOTAL_BYTES];
+
+/************************** Function Prototypes ******************************/
+
+
+/****************************************************************************/
+/**
+*
+* This function runs a self-test on the driver and hardware device. This self
+* test performs a local loopback and verifies data can be sent and received.
+*
+* The time for this test is proportional to the baud rate that has been set
+* prior to calling this function.
+*
+* The mode and control registers are restored before return.
+*
+* @param InstancePtr is a pointer to the XUartPs instance
+*
+* @return
+* - XST_SUCCESS if the test was successful
+* - XST_UART_TEST_FAIL if the test failed looping back the data
+*
+* @note
+*
+* This function can hang if the hardware is not functioning properly.
+*
+******************************************************************************/
+s32 XUartPs_SelfTest(XUartPs *InstancePtr)
+{
+ s32 Status = XST_SUCCESS;
+ u32 IntrRegister;
+ u32 ModeRegister;
+ u8 Index;
+ u32 ReceiveDataResult;
+
+ /* Assert validates the input arguments */
+ Xil_AssertNonvoid(InstancePtr != NULL);
+ Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+ /* Disable all interrupts in the interrupt disable register */
+ IntrRegister = XUartPs_ReadReg(InstancePtr->Config.BaseAddress,
+ XUARTPS_IMR_OFFSET);
+ XUartPs_WriteReg(InstancePtr->Config.BaseAddress, XUARTPS_IDR_OFFSET,
+ XUARTPS_IXR_MASK);
+
+ /* Setup for local loopback */
+ ModeRegister = XUartPs_ReadReg(InstancePtr->Config.BaseAddress,
+ XUARTPS_MR_OFFSET);
+ XUartPs_WriteReg(InstancePtr->Config.BaseAddress, XUARTPS_MR_OFFSET,
+ ((ModeRegister & (u32)(~XUARTPS_MR_CHMODE_MASK)) |
+ (u32)XUARTPS_MR_CHMODE_L_LOOP));
+
+ /* Send a number of bytes and receive them, one at a time. */
+ for (Index = 0U; Index < XUARTPS_TOTAL_BYTES; Index++) {
+ /*
+ * Send out the byte and if it was not sent then the failure
+ * will be caught in the comparison at the end
+ */
+ (void)XUartPs_Send(InstancePtr, &TestString[Index], 1U);
+
+ /*
+ * Wait until the byte is received. This can hang if the HW
+ * is broken. Watch for the FIFO empty flag to be false.
+ */
+ ReceiveDataResult = Xil_In32((InstancePtr->Config.BaseAddress) + XUARTPS_SR_OFFSET) &
+ XUARTPS_SR_RXEMPTY;
+ while (ReceiveDataResult == XUARTPS_SR_RXEMPTY ) {
+ ReceiveDataResult = Xil_In32((InstancePtr->Config.BaseAddress) + XUARTPS_SR_OFFSET) &
+ XUARTPS_SR_RXEMPTY;
+ }
+
+ /* Receive the byte */
+ (void)XUartPs_Recv(InstancePtr, &ReturnString[Index], 1U);
+ }
+
+ /*
+ * Compare the bytes received to the bytes sent to verify the exact data
+ * was received
+ */
+ for (Index = 0U; Index < XUARTPS_TOTAL_BYTES; Index++) {
+ if (TestString[Index] != ReturnString[Index]) {
+ Status = XST_UART_TEST_FAIL;
+ }
+ }
+
+ /*
+ * Restore the registers which were altered to put into polling and
+ * loopback modes so that this test is not destructive
+ */
+ XUartPs_WriteReg(InstancePtr->Config.BaseAddress, XUARTPS_IER_OFFSET,
+ IntrRegister);
+ XUartPs_WriteReg(InstancePtr->Config.BaseAddress, XUARTPS_MR_OFFSET,
+ ModeRegister);
+
+ return Status;
+}
+/** @} */
diff --git a/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/uartps_v3_8/src/xuartps_sinit.c b/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/uartps_v3_8/src/xuartps_sinit.c
new file mode 100644
index 0000000..6d9b3b8
--- /dev/null
+++ b/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/uartps_v3_8/src/xuartps_sinit.c
@@ -0,0 +1,93 @@
+/******************************************************************************
+*
+* Copyright (C) 2010 - 2015 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+* THE SOFTWARE.
+*
+*
+*
+******************************************************************************/
+/****************************************************************************/
+/**
+*
+* @file xuartps_sinit.c
+* @addtogroup uartps_v3_8
+* @{
+*
+* The implementation of the XUartPs driver's static initialization
+* functionality.
+*
+* <pre>
+* MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ----- ------ -------- -----------------------------------------------
+* 1.00 drg/jz 01/13/10 First Release
+* 3.00 kvn 02/13/15 Modified code for MISRA-C:2012 compliance.
+* </pre>
+*
+*****************************************************************************/
+
+/***************************** Include Files ********************************/
+
+#include "xstatus.h"
+#include "xparameters.h"
+#include "xuartps.h"
+
+/************************** Constant Definitions ****************************/
+
+/**************************** Type Definitions ******************************/
+
+/***************** Macros (Inline Functions) Definitions ********************/
+
+/************************** Variable Definitions ****************************/
+extern XUartPs_Config XUartPs_ConfigTable[XPAR_XUARTPS_NUM_INSTANCES];
+
+/************************** Function Prototypes *****************************/
+
+/****************************************************************************/
+/**
+*
+* Looks up the device configuration based on the unique device ID. The table
+* contains the configuration info for each device in the system.
+*
+* @param DeviceId contains the ID of the device
+*
+* @return A pointer to the configuration structure or NULL if the
+* specified device is not in the system.
+*
+* @note None.
+*
+******************************************************************************/
+XUartPs_Config *XUartPs_LookupConfig(u16 DeviceId)
+{
+ XUartPs_Config *CfgPtr = NULL;
+
+ u32 Index;
+
+ for (Index = 0U; Index < (u32)XPAR_XUARTPS_NUM_INSTANCES; Index++) {
+ if (XUartPs_ConfigTable[Index].DeviceId == DeviceId) {
+ CfgPtr = &XUartPs_ConfigTable[Index];
+ break;
+ }
+ }
+
+ return (XUartPs_Config *)CfgPtr;
+}
+/** @} */
diff --git a/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/usbps_v2_4/src/Makefile b/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/usbps_v2_4/src/Makefile
new file mode 100644
index 0000000..7cf97e2
--- /dev/null
+++ b/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/usbps_v2_4/src/Makefile
@@ -0,0 +1,41 @@
+COMPILER=
+ARCHIVER=
+CP=cp
+COMPILER_FLAGS=
+EXTRA_COMPILER_FLAGS=
+LIB=libxil.a
+
+CC_FLAGS = $(COMPILER_FLAGS)
+ECC_FLAGS = $(EXTRA_COMPILER_FLAGS)
+
+RELEASEDIR=../../../lib
+INCLUDEDIR=../../../include
+INCLUDES=-I./. -I${INCLUDEDIR}
+
+OUTS = *.o
+
+LIBSOURCES:=*.c
+INCLUDEFILES:=*.h
+
+OBJECTS = $(addsuffix .o, $(basename $(wildcard *.c)))
+
+libs: banner xusbps_libs clean
+
+%.o: %.c
+ ${COMPILER} $(CC_FLAGS) $(ECC_FLAGS) $(INCLUDES) -o $@ $<
+
+banner:
+ echo "Compiling usbps"
+
+xusbps_libs: ${OBJECTS}
+ $(ARCHIVER) -r ${RELEASEDIR}/${LIB} ${OBJECTS}
+
+.PHONY: include
+include: xusbps_includes
+
+xusbps_includes:
+ ${CP} ${INCLUDEFILES} ${INCLUDEDIR}
+
+clean:
+ rm -rf ${OBJECTS}
+
diff --git a/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/usbps_v2_4/src/xusbps.c b/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/usbps_v2_4/src/xusbps.c
new file mode 100644
index 0000000..55976d3
--- /dev/null
+++ b/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/usbps_v2_4/src/xusbps.c
@@ -0,0 +1,358 @@
+/******************************************************************************
+*
+* Copyright (C) 2010 - 2015 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+* THE SOFTWARE.
+*
+*
+*
+******************************************************************************/
+/******************************************************************************/
+/**
+ * @file xusbps.c
+* @addtogroup usbps_v2_4
+* @{
+ *
+ * The XUsbPs driver. Functions in this file are the minimum required
+ * functions for this driver. See xusbps.h for a detailed description of the
+ * driver.
+ *
+ * @note None.
+ *
+ * <pre>
+ * MODIFICATION HISTORY:
+ *
+ * Ver Who Date Changes
+ * ----- ---- -------- --------------------------------------------------------
+ * 1.00a jz 10/10/10 First release
+ * 2.1 kpc 04/28/14 Removed unused functions
+ * </pre>
+ ******************************************************************************/
+
+/***************************** Include Files **********************************/
+#include <stdio.h>
+#include "xusbps.h"
+
+/************************** Constant Definitions ******************************/
+
+/**************************** Type Definitions ********************************/
+
+/***************** Macros (Inline Functions) Definitions **********************/
+
+/************************** Variable Definitions ******************************/
+
+/************************** Function Prototypes *******************************/
+
+/*****************************************************************************/
+/**
+*
+* This function initializes a XUsbPs instance/driver.
+*
+* The initialization entails:
+* - Initialize all members of the XUsbPs structure.
+*
+* @param InstancePtr is a pointer to XUsbPs instance of the controller.
+* @param ConfigPtr is a pointer to a XUsbPs_Config configuration
+* structure. This structure will contain the requested
+* configuration for the device. Typically, this is a local
+* structure and the content of which will be copied into the
+* configuration structure within XUsbPs.
+* @param VirtBaseAddress is the base address of the device. For systems
+* with virtual memory, this address must be the virtual address
+* of the device.
+* For systems that do not support virtual memory this address
+* should be the physical address of the device. For backwards
+* compatibility NULL may be passed in systems that do not support
+* virtual memory (deprecated).
+*
+* @return
+* - XST_SUCCESS no errors occurred.
+* - XST_FAILURE an error occurred during initialization.
+*
+* @note
+* After calling XUsbPs_CfgInitialize() the controller
+* IS NOT READY for use. Before the controller can be used its
+* DEVICE parameters must be configured. See xusbps.h
+* for details.
+*
+******************************************************************************/
+int XUsbPs_CfgInitialize(XUsbPs *InstancePtr,
+ const XUsbPs_Config *ConfigPtr, u32 VirtBaseAddress)
+{
+ Xil_AssertNonvoid(InstancePtr != NULL);
+ Xil_AssertNonvoid(ConfigPtr != NULL);
+
+ /* Copy the config structure. */
+ InstancePtr->Config = *ConfigPtr;
+
+ /* Check if the user provided a non-NULL base address. If so, we have
+ * to overwrite the base address in the configuration structure.
+ */
+ if (0 != VirtBaseAddress) {
+ InstancePtr->Config.BaseAddress = VirtBaseAddress;
+ }
+
+ /* Initialize the XUsbPs structure to default values. */
+ InstancePtr->CurrentAltSetting = XUSBPS_DEFAULT_ALT_SETTING;
+
+ InstancePtr->HandlerFunc = NULL;
+
+ return XST_SUCCESS;
+}
+
+/*****************************************************************************/
+/**
+*
+* This function performs device reset, device is stopped at the end.
+*
+* @param InstancePtr is a pointer to XUsbPs instance of the controller.
+*
+* @return None.
+*
+* @note None.
+*
+******************************************************************************/
+void XUsbPs_DeviceReset(XUsbPs *InstancePtr)
+{
+ int Timeout;
+
+ /* Clear all setup token semaphores by reading the
+ * XUSBPS_EPSTAT_OFFSET register and writing its value back to
+ * itself.
+ */
+ XUsbPs_WriteReg(InstancePtr->Config.BaseAddress, XUSBPS_EPSTAT_OFFSET,
+ XUsbPs_ReadReg(InstancePtr->Config.BaseAddress,
+ XUSBPS_EPSTAT_OFFSET));
+
+ /* Clear all the endpoint complete status bits by reading the
+ * XUSBPS_EPCOMPL_OFFSET register and writings its value back
+ * to itself.
+ */
+ XUsbPs_WriteReg(InstancePtr->Config.BaseAddress, XUSBPS_EPCOMPL_OFFSET,
+ XUsbPs_ReadReg(InstancePtr->Config.BaseAddress,
+ XUSBPS_EPCOMPL_OFFSET));
+
+ /* Cancel all endpoint prime status by waiting until all bits
+ * in XUSBPS_EPPRIME_OFFSET are 0 and then writing 0xFFFFFFFF
+ * to XUSBPS_EPFLUSH_OFFSET.
+ *
+ * Avoid hanging here by using a Timeout counter...
+ */
+ Timeout = XUSBPS_TIMEOUT_COUNTER;
+ while ((XUsbPs_ReadReg(InstancePtr->Config.BaseAddress,
+ XUSBPS_EPPRIME_OFFSET) &
+ XUSBPS_EP_ALL_MASK) && --Timeout) {
+ /* NOP */
+ }
+ XUsbPs_WriteReg(InstancePtr->Config.BaseAddress,
+ XUSBPS_EPFLUSH_OFFSET, 0xFFFFFFFF);
+
+ XUsbPs_Stop(InstancePtr);
+
+ /* Write to CR register for controller reset */
+ XUsbPs_WriteReg(InstancePtr->Config.BaseAddress, XUSBPS_CMD_OFFSET,
+ XUsbPs_ReadReg(InstancePtr->Config.BaseAddress,
+ XUSBPS_CMD_OFFSET) | XUSBPS_CMD_RST_MASK);
+
+ /* Wait for reset to finish, hardware clears the reset bit once done */
+ Timeout = 1000000;
+ while((XUsbPs_ReadReg(InstancePtr->Config.BaseAddress,
+ XUSBPS_CMD_OFFSET) &
+ XUSBPS_CMD_RST_MASK) && --Timeout) {
+ /* NOP */
+ }
+}
+/*****************************************************************************/
+/**
+*
+* This function resets the USB device. All the configuration registers are
+* reset to their default values. The function waits until the reset operation
+* is complete or for a certain duration within which the reset operation is
+* expected to be completed.
+*
+* @param InstancePtr is a pointer to XUsbPs instance of the controller.
+*
+* @return
+* - XST_SUCCESS Reset operation completed successfully.
+* - XST_FAILURE Reset operation timed out.
+*
+* @note None.
+*
+******************************************************************************/
+int XUsbPs_Reset(XUsbPs *InstancePtr)
+{
+ int Timeout;
+
+ Xil_AssertNonvoid(InstancePtr != NULL);
+
+ /* Write a 1 to the RESET bit. The RESET bit is cleared by HW once the
+ * RESET is complete.
+ *
+ * We are going to wait for the RESET bit to clear before we return
+ * from this function. Unfortunately we do not have timers available at
+ * this point to determine when we should report a Timeout.
+ *
+ * However, by using a large number for the poll loop we can assume
+ * that the polling operation will take longer than the expected time
+ * the HW needs to RESET. If the poll loop expires we can assume a
+ * Timeout. The drawback is that on a slow system (and even on a fast
+ * system) this can lead to _very_ long Timeout periods.
+ */
+ XUsbPs_WriteReg(InstancePtr->Config.BaseAddress,
+ XUSBPS_CMD_OFFSET, XUSBPS_CMD_RST_MASK);
+
+
+ /* Wait for the RESET bit to be cleared by HW. */
+ Timeout = XUSBPS_TIMEOUT_COUNTER;
+ while ((XUsbPs_ReadReg(InstancePtr->Config.BaseAddress,
+ XUSBPS_CMD_OFFSET) &
+ XUSBPS_CMD_RST_MASK) && --Timeout) {
+ /* NOP */
+ }
+
+ if (0 == Timeout) {
+ return XST_FAILURE;
+ }
+
+ return XST_SUCCESS;
+}
+
+/*****************************************************************************/
+/**
+ * USB Suspend
+ *
+ * In order to conserve power, USB devices automatically enter the suspended
+ * state when the device has observed no bus traffic for a specified period.
+ * When suspended, the USB device maintains any internal status, including its
+ * address and configuration. Attached devices must be prepared to suspend at
+ * any time they are powered, regardless of if they have been assigned a
+ * non-default address, are configured, or neither. Bus activity may cease due
+ * to the host entering a suspend mode of its own. In addition, a USB device
+ * shall also enter the suspended state when the hub port it is attached to is
+ * disabled.
+ *
+ * A USB device exits suspend mode when there is bus activity. A USB device may
+ * also request the host to exit suspend mode or selective suspend by using
+ * electrical signaling to indicate remote wakeup. The ability of a device to
+ * signal remote wakeup is optional. If the USB device is capable of remote
+ * wakeup signaling, the device must support the ability of the host to enable
+ * and disable this capability. When the device is reset, remote wakeup
+ * signaling must be disabled.
+ *
+ * @param InstancePtr is a pointer to XUsbPs instance of the controller.
+ *
+ * @return
+ * - XST_SUCCESS if the USB device has entered Suspend mode
+ * successfully
+ * - XST_FAILURE on any error
+ *
+ * @note None.
+ *
+ ******************************************************************************/
+int XUsbPs_Suspend(const XUsbPs *InstancePtr)
+{
+ (void) InstancePtr;
+
+ return XST_SUCCESS;
+}
+
+
+/*****************************************************************************/
+/**
+* USB Resume
+*
+ If the USB controller is suspended, its operation is resumed when any
+* non-idle signaling is received on its upstream facing port.
+*
+* @param InstancePtr is a pointer to XUsbPs instance of the controller.
+*
+* @return
+* - XST_SUCCESS if the USB device has Resumed successfully
+* - XST_FAILURE on any error
+*
+* @note None.
+*
+******************************************************************************/
+int XUsbPs_Resume(const XUsbPs *InstancePtr)
+{
+ (void) InstancePtr;
+ return XST_SUCCESS;
+}
+
+
+/*****************************************************************************/
+/**
+* USB Assert Resume
+*
+* @param InstancePtr is a pointer to XUsbPs instance of the controller.
+*
+* @return
+* - XST_SUCCESS if the USB device has Resumed successfully
+* - XST_FAILURE on any error
+*
+* @note None.
+*
+******************************************************************************/
+
+int XUsbPs_RequestHostResume(const XUsbPs *InstancePtr)
+{
+ (void) InstancePtr;
+ return XST_SUCCESS;
+}
+
+/****************************************************************************/
+/**
+* This functions sets the controller's DEVICE address. It also sets the
+* advance bit so the controller will wait for the next IN-ACK before the new
+* address takes effect.
+*
+* @param InstancePtr is a pointer to XUsbPs instance of the controller.
+* @param Address is the Address of the device.
+*
+* @return
+* - XST_SUCCESS: Address set successfully.
+* - XST_FAILURE: An error occurred.
+* - XST_INVALID_PARAM: Invalid parameter passed, e.g. address
+* value too big.
+*
+* @note None.
+*
+*****************************************************************************/
+int XUsbPs_SetDeviceAddress(XUsbPs *InstancePtr, u8 Address)
+{
+ Xil_AssertNonvoid(InstancePtr != NULL);
+
+ /* Check address range validity. */
+ if (Address > XUSBPS_DEVICEADDR_MAX) {
+ return XST_INVALID_PARAM;
+ }
+
+ /* Set the address register with the Address value provided. Also set
+ * the Address Advance Bit. This will cause the address to be set only
+ * after an IN occurred and has been ACKed on the endpoint.
+ */
+ XUsbPs_WriteReg(InstancePtr->Config.BaseAddress,
+ XUSBPS_DEVICEADDR_OFFSET,
+ (Address << XUSBPS_DEVICEADDR_ADDR_SHIFT) |
+ XUSBPS_DEVICEADDR_DEVICEAADV_MASK);
+
+ return XST_SUCCESS;
+}
+
+/** @} */
diff --git a/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/usbps_v2_4/src/xusbps.h b/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/usbps_v2_4/src/xusbps.h
new file mode 100644
index 0000000..250cb95
--- /dev/null
+++ b/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/usbps_v2_4/src/xusbps.h
@@ -0,0 +1,1092 @@
+/******************************************************************************
+*
+* Copyright (C) 2010 - 2015 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+* THE SOFTWARE.
+*
+*
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+ *
+ * @file xusbps.h
+* @addtogroup usbps_v2_4
+* @{
+* @details
+ *
+ * This file contains the implementation of the XUsbPs driver. It is the
+ * driver for an USB controller in DEVICE or HOST mode.
+ *
+ * <h2>Introduction</h2>
+ *
+ * The Spartan-3AF Embedded Peripheral Block contains a USB controller for
+ * communication with serial peripherals or hosts. The USB controller supports
+ * Host, Device and On the Go (OTG) applications.
+ *
+ * <h2>USB Controller Features</h2>
+ *
+ * - Supports Low Speed USB 1.1 (1.5Mbps), Full Speed USB 1.1 (12Mbps), and
+ * High Speed USB 2.0 (480Mbps) data speeds
+ * - Supports Device, Host and OTG operational modes
+ * - ULPI transceiver interface for USB 2.0 operation
+ * - Integrated USB Full and Low speed serial transceiver interfaces for lowest
+ * cost connections
+ *
+ * <h2>Initialization & Configuration</h2>
+ *
+ * The configuration of the USB driver happens in multiple stages:
+ *
+ * - (a) Configuration of the basic parameters:
+ * In this stage the basic parameters for the driver are configured,
+ * including the base address and the controller ID.
+ *
+ * - (b) Configuration of the DEVICE endpoints (if applicable):
+ * If DEVICE mode is desired, the endpoints of the controller need to be
+ * configured using the XUsbPs_DeviceConfig data structure. Once the
+ * endpoint configuration is set up in the data structure, The user then
+ * needs to allocate the required amount of DMAable memory and
+ * finalize the configuration of the XUsbPs_DeviceConfig data structure,
+ * e.g. setting the DMAMemVirt and DMAMemPhys members.
+ *
+ * - (c) Configuration of the DEVICE modes:
+ * In the second stage the parameters for DEVICE are configured.
+ * The caller only needs to configure the modes that are
+ * actually used. Configuration is done with the:
+ * XUsbPs_ConfigureDevice()
+ * Configuration parameters are defined and passed
+ * into these functions using the:
+ * XUsbPs_DeviceConfig data structures.
+ *
+ *
+ * <h2>USB Device Endpoints</h2>
+ *
+ * The USB core supports up to 4 endpoints. Each endpoint has two directions,
+ * an OUT (RX) and an IN (TX) direction. Note that the direction is viewed from
+ * the host's perspective. Endpoint 0 defaults to be the control endpoint and
+ * does not need to be set up. Other endpoints need to be configured and set up
+ * depending on the application. Only endpoints that are actuelly used by the
+ * application need to be initialized.
+ * See the example code (xusbps_intr_example.c) for more information.
+ *
+ *
+ * <h2>Interrupt Handling</h2>
+ *
+ * The USB core uses one interrupt line to report interrupts to the CPU.
+ * Interrupts are handled by the driver's interrupt handler function
+ * XUsbPs_IntrHandler().
+ * It has to be registered with the OS's interrupt subsystem. The driver's
+ * interrupt handler divides incoming interrupts into two categories:
+ *
+ * - General device interrupts
+ * - Endopint related interrupts
+ *
+ * The user (typically the adapter layer) can register general interrupt
+ * handler functions and endpoint specific interrupt handler functions with the
+ * driver to receive those interrupts by calling the
+ * XUsbPs_IntrSetHandler()
+ * and
+ * XUsbPs_EpSetHandler()
+ * functions respectively. Calling these functions with a NULL pointer as the
+ * argument for the function pointer will "clear" the handler function.
+ *
+ * The user can register one handler function for the generic interrupts and
+ * two handler functions for each endpoint, one for the RX (OUT) and one for
+ * the TX (IN) direction. For some applications it may be useful to register a
+ * single endpoint handler function for muliple endpoints/directions.
+ *
+ * When a callback function is called by the driver, parameters identifying the
+ * type of the interrupt will be passed into the handler functions. For general
+ * interrupts the interrupt mask will be passed into the handler function. For
+ * endpoint interrupts the parameters include the number of the endpoint, the
+ * direction (OUT/IN) and the type of the interrupt.
+ *
+ *
+ * <h2>Data buffer handling</h2>
+ *
+ * Data buffers are sent to and received from endpoint using the
+ * XUsbPs_EpBufferSend(), XUsbPs_EpBufferSendWithZLT()
+ * and
+ * XUsbPs_EpBufferReceive()
+ * functions.
+ *
+ * User data buffer size is limited to 16 Kbytes. If the user wants to send a
+ * data buffer that is bigger than this limit it needs to break down the data
+ * buffer into multiple fragments and send the fragments individually.
+ *
+ * From the controller perspective Data buffers can be aligned at any boundary.
+ * if the buffers are from cache region then the buffer and buffer size should
+ * be aligned to cache line aligned
+ *
+ *
+ * <h3>Zero copy</h3>
+ *
+ * The driver uses a zero copy mechanism which imposes certain restrictions to
+ * the way the user can handle the data buffers.
+ *
+ * One restriction is that the user needs to release a buffer after it is done
+ * processing the data in the buffer.
+ *
+ * Similarly, when the user sends a data buffer it MUST not re-use the buffer
+ * until it is notified by the driver that the buffer has been transmitted. The
+ * driver will notify the user via the registered endpoint interrupt handling
+ * function by sending a XUSBPS_EP_EVENT_DATA_TX event.
+ *
+ *
+ * <h2>DMA</h2>
+ *
+ * The driver uses DMA internally to move data from/to memory. This behaviour
+ * is transparent to the user. Keeping the DMA handling hidden from the user
+ * has the advantage that the same API can be used with USB cores that do not
+ * support DMA.
+ *
+ *
+ * <pre>
+ * MODIFICATION HISTORY:
+ *
+ * Ver Who Date Changes
+ * ----- ---- -------- ----------------------------------------------------------
+ * 1.00a wgr 10/10/10 First release
+ * 1.02a wgr 05/16/12 Removed comments as they are showing up in SDK
+ * Tabs for CR 657898
+ * 1.03a nm 09/21/12 Fixed CR#678977. Added proper sequence for setup packet
+ * handling.
+ * 1.04a nm 10/23/12 Fixed CR# 679106.
+ * 11/02/12 Fixed CR# 683931. Mult bits are set properly in dQH.
+ * 2.00a kpc 04/03/14 Fixed CR#777763. Corrected the setup tripwire macro val.
+ * 2.1 kpc 04/28/14 Removed unused function prototypes
+ * 2.2 kpc 08/23/14 Exported XUsbPs_DeviceReset API as global for calling in
+ * code coverage tests.
+ * 2.3 kpc 02/19/14 Fixed CR#873972, CR#873974. Corrected the logic for proper
+ * moving of dTD Head/Tail Pointers. Invalidate the cache
+ * after buffer receive in Endpoint Buffer Handler.
+ * 2.4 sg 04/26/16 Fixed CR#949693, Corrected the logic for EP flush
+ * ms 03/17/17 Added readme.txt file in examples folder for doxygen
+ * generation.
+ * ms 04/10/17 Modified filename tag to include the file in doxygen
+ * examples.
+ * </pre>
+ *
+ ******************************************************************************/
+
+#ifndef XUSBPS_H
+#define XUSBPS_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/***************************** Include Files *********************************/
+
+#include "xusbps_hw.h"
+#include "xil_types.h"
+#include "xstatus.h"
+
+/************************** Constant Definitions *****************************/
+
+/**
+ * @name System hang prevention Timeout counter value.
+ *
+ * This value is used throughout the code to initialize a Timeout counter that
+ * is used when hard polling a register. The ides is to initialize the Timeout
+ * counter to a value that is longer than any expected Timeout but short enough
+ * so the system will continue to work and report an error while the user is
+ * still paying attention. A reasonable Timeout time would be about 10 seconds.
+ * The XUSBPS_TIMEOUT_COUNTER value should be chosen so a polling loop would
+ * run about 10 seconds before a Timeout is detected. For example:
+ *
+ * int Timeout = XUSBPS_TIMEOUT_COUNTER;
+ * while ((XUsbPs_ReadReg(InstancePtr->Config.BaseAddress,
+ * XUSBPS_CMD_OFFSET) &
+ * XUSBPS_CMD_RST_MASK) && --Timeout) {
+ * ;
+ * }
+ * if (0 == Timeout) {
+ * return XST_FAILURE;
+ * }
+ *
+ */
+#define XUSBPS_TIMEOUT_COUNTER 1000000
+
+
+/**
+ * @name Endpoint Direction (bitmask)
+ * Definitions to be used with Endpoint related function that require a
+ * 'Direction' parameter.
+ *
+ * NOTE:
+ * The direction is always defined from the perspective of the HOST! This
+ * means that an IN endpoint on the controller is used for sending data while
+ * the OUT endpoint on the controller is used for receiving data.
+ * @{
+ */
+#define XUSBPS_EP_DIRECTION_IN 0x01 /**< Endpoint direction IN. */
+#define XUSBPS_EP_DIRECTION_OUT 0x02 /**< Endpoint direction OUT. */
+/* @} */
+
+
+/**
+ * @name Endpoint Type
+ * Definitions to be used with Endpoint related functions that require a 'Type'
+ * parameter.
+ * @{
+ */
+#define XUSBPS_EP_TYPE_NONE 0 /**< Endpoint is not used. */
+#define XUSBPS_EP_TYPE_CONTROL 1 /**< Endpoint for Control Transfers */
+#define XUSBPS_EP_TYPE_ISOCHRONOUS 2 /**< Endpoint for isochronous data */
+#define XUSBPS_EP_TYPE_BULK 3 /**< Endpoint for BULK Transfers. */
+#define XUSBPS_EP_TYPE_INTERRUPT 4 /**< Endpoint for interrupt Transfers */
+/* @} */
+
+/**
+ * Endpoint Max Packet Length in DeviceConfig is a coded value, ch9.6.6.
+ *
+ * @{
+ */
+#define ENDPOINT_MAXP_LENGTH 0x400
+#define ENDPOINT_MAXP_MULT_MASK 0xC00
+#define ENDPOINT_MAXP_MULT_SHIFT 10
+/* @} */
+
+/**
+ * @name Field names for status retrieval
+ * Definitions for the XUsbPs_GetStatus() function call 'StatusType'
+ * parameter.
+ * @{
+ */
+#define XUSBPS_EP_STS_ADDRESS 1 /**< Address of controller. */
+#define XUSBPS_EP_STS_CONTROLLER_STATE 2 /**< Current controller state. */
+/* @} */
+
+
+
+/**
+ * @name USB Default alternate setting
+ *
+ * @{
+ */
+#define XUSBPS_DEFAULT_ALT_SETTING 0 /**< The default alternate setting is 0 */
+/* @} */
+
+/**
+ * @name Endpoint event types
+ * Definitions that are used to identify events that occur on endpoints. Passed
+ * to the endpoint event handler functions registered with
+ * XUsbPs_EpSetHandler().
+ * @{
+ */
+#define XUSBPS_EP_EVENT_SETUP_DATA_RECEIVED 0x01
+ /**< Setup data has been received on the endpoint. */
+#define XUSBPS_EP_EVENT_DATA_RX 0x02
+ /**< Data frame has been received on the endpoint. */
+#define XUSBPS_EP_EVENT_DATA_TX 0x03
+ /**< Data frame has been sent on the endpoint. */
+/* @} */
+
+
+/*
+ * Maximum packet size for endpoint, 1024
+ * @{
+ */
+#define XUSBPS_MAX_PACKET_SIZE 1024
+ /**< Maximum value can be put into the queue head */
+/* @} */
+/**************************** Type Definitions *******************************/
+
+/******************************************************************************
+ * This data type defines the callback function to be used for Endpoint
+ * handlers.
+ *
+ * @param CallBackRef is the Callback reference passed in by the upper
+ * layer when setting the handler, and is passed back to the upper
+ * layer when the handler is called.
+ * @param EpNum is the Number of the endpoint that caused the event.
+ * @param EventType is the type of the event that occurred on the endpoint.
+ * @param Data is a pointer to user data pointer specified when callback
+ * was registered.
+ */
+typedef void (*XUsbPs_EpHandlerFunc)(void *CallBackRef,
+ u8 EpNum, u8 EventType, void *Data);
+
+
+/******************************************************************************
+ * This data type defines the callback function to be used for the general
+ * interrupt handler.
+ *
+ * @param CallBackRef is the Callback reference passed in by the upper
+ * layer when setting the handler, and is passed back to the upper
+ * layer when the handler is called.
+ * @param IrqMask is the Content of the interrupt status register. This
+ * value can be used by the callback function to distinguish the
+ * individual interrupt types.
+ */
+typedef void (*XUsbPs_IntrHandlerFunc)(void *CallBackRef, u32 IrqMask);
+
+
+/******************************************************************************/
+
+/* The following type definitions are used for referencing Queue Heads and
+ * Transfer Descriptors. The structures themselves are not used, however, the
+ * types are used in the API to avoid using (void *) pointers.
+ */
+typedef u8 XUsbPs_dQH[XUSBPS_dQH_ALIGN];
+typedef u8 XUsbPs_dTD[XUSBPS_dTD_ALIGN];
+
+
+/**
+ * The following data structures are used internally by the L0/L1 driver.
+ * Their contents MUST NOT be changed by the upper layers.
+ */
+
+/**
+ * The following data structure represents OUT endpoint.
+ */
+typedef struct {
+ XUsbPs_dQH *dQH;
+ /**< Pointer to the Queue Head structure of the endpoint. */
+
+ XUsbPs_dTD *dTDs;
+ /**< Pointer to the first dTD of the dTD list for this
+ * endpoint. */
+
+ XUsbPs_dTD *dTDCurr;
+ /**< Buffer to the currently processed descriptor. */
+
+ u8 *dTDBufs;
+ /**< Pointer to the first buffer of the buffer list for this
+ * endpoint. */
+
+ XUsbPs_EpHandlerFunc HandlerFunc;
+ /**< Handler function for this endpoint. */
+ void *HandlerRef;
+ /**< User data reference for the handler. */
+} XUsbPs_EpOut;
+
+
+/**
+ * The following data structure represents IN endpoint.
+ */
+typedef struct {
+ XUsbPs_dQH *dQH;
+ /**< Pointer to the Queue Head structure of the endpoint. */
+
+ XUsbPs_dTD *dTDs;
+ /**< List of pointers to the Transfer Descriptors of the
+ * endpoint. */
+
+ XUsbPs_dTD *dTDHead;
+ /**< Buffer to the next available descriptor in the list. */
+
+ XUsbPs_dTD *dTDTail;
+ /**< Buffer to the last unsent descriptor in the list*/
+
+ XUsbPs_EpHandlerFunc HandlerFunc;
+ /**< Handler function for this endpoint. */
+ void *HandlerRef;
+ /**< User data reference for the handler. */
+} XUsbPs_EpIn;
+
+
+/**
+ * The following data structure represents an endpoint used internally
+ * by the L0/L1 driver.
+ */
+typedef struct {
+ /* Each endpoint has an OUT and an IN component.
+ */
+ XUsbPs_EpOut Out; /**< OUT endpoint structure */
+ XUsbPs_EpIn In; /**< IN endpoint structure */
+} XUsbPs_Endpoint;
+
+
+
+/**
+ * The following structure is used by the user to receive Setup Data from an
+ * endpoint. Using this structure simplifies the process of interpreting the
+ * setup data in the core's data fields.
+ *
+ * The naming scheme for the members of this structure is different from the
+ * naming scheme found elsewhere in the code. The members of this structure are
+ * defined in the Chapter 9 USB reference guide. Using this naming scheme makes
+ * it easier for people familiar with the standard to read the code.
+ */
+typedef struct {
+ u8 bmRequestType; /**< bmRequestType in setup data */
+ u8 bRequest; /**< bRequest in setup data */
+ u16 wValue; /**< wValue in setup data */
+ u16 wIndex; /**< wIndex in setup data */
+ u16 wLength; /**< wLength in setup data */
+}
+XUsbPs_SetupData;
+
+
+/**
+ * Data structures used to configure endpoints.
+ */
+typedef struct {
+ u32 Type;
+ /**< Endpoint type:
+ - XUSBPS_EP_TYPE_CONTROL
+ - XUSBPS_EP_TYPE_ISOCHRONOUS
+ - XUSBPS_EP_TYPE_BULK
+ - XUSBPS_EP_TYPE_INTERRUPT */
+
+ u32 NumBufs;
+ /**< Number of buffers to be handled by this endpoint. */
+ u32 BufSize;
+ /**< Buffer size. Only relevant for OUT (receive) Endpoints. */
+
+ u16 MaxPacketSize;
+ /**< Maximum packet size for this endpoint. This number will
+ * define the maximum number of bytes sent on the wire per
+ * transaction. Range: 0..1024 */
+} XUsbPs_EpSetup;
+
+
+/**
+ * Endpoint configuration structure.
+ */
+typedef struct {
+ XUsbPs_EpSetup Out; /**< OUT component of endpoint. */
+ XUsbPs_EpSetup In; /**< IN component of endpoint. */
+} XUsbPs_EpConfig;
+
+
+/**
+ * The XUsbPs_DeviceConfig structure contains the configuration information to
+ * configure the USB controller for DEVICE mode. This data structure is used
+ * with the XUsbPs_ConfigureDevice() function call.
+ */
+typedef struct {
+ u8 NumEndpoints; /**< Number of Endpoints for the controller.
+ This number depends on the runtime
+ configuration of driver. The driver may
+ configure fewer endpoints than are available
+ in the core. */
+
+ XUsbPs_EpConfig EpCfg[XUSBPS_MAX_ENDPOINTS];
+ /**< List of endpoint configurations. */
+
+
+ u32 DMAMemPhys; /**< Physical base address of DMAable memory
+ allocated for the driver. */
+
+ /* The following members are used internally by the L0/L1 driver. They
+ * MUST NOT be accesses and/or modified in any way by the upper layers.
+ *
+ * The reason for having these members is that we generally try to
+ * avoid allocating memory in the L0/L1 driver as we want to be OS
+ * independent. In order to avoid allocating memory for this data
+ * structure wihin L0/L1 we put it into the XUsbPs_DeviceConfig
+ * structure which is allocated by the caller.
+ */
+ XUsbPs_Endpoint Ep[XUSBPS_MAX_ENDPOINTS];
+ /**< List of endpoint metadata structures. */
+
+ u32 PhysAligned; /**< 64 byte aligned base address of the DMA
+ memory block. Will be computed and set by
+ the L0/L1 driver. */
+} XUsbPs_DeviceConfig;
+
+
+/**
+ * The XUsbPs_Config structure contains configuration information for the USB
+ * controller.
+ *
+ * This structure only contains the basic configuration for the controller. The
+ * caller also needs to initialize the controller for the DEVICE mode
+ * using the XUsbPs_DeviceConfig data structures with the
+ * XUsbPs_ConfigureDevice() function call
+ */
+typedef struct {
+ u16 DeviceID; /**< Unique ID of controller. */
+ u32 BaseAddress; /**< Core register base address. */
+} XUsbPs_Config;
+
+
+/**
+ * The XUsbPs driver instance data. The user is required to allocate a
+ * variable of this type for every USB controller in the system. A pointer to a
+ * variable of this type is then passed to the driver API functions.
+ */
+typedef struct {
+ XUsbPs_Config Config; /**< Configuration structure */
+
+ int CurrentAltSetting; /**< Current alternative setting of interface */
+
+ void *UserDataPtr; /**< Data pointer to be used by upper layers to
+ store application dependent data structures.
+ The upper layers are responsible to allocated
+ and free the memory. The driver will not
+ mofidy this data pointer. */
+
+ /**
+ * The following structures hold the configuration for DEVICE mode
+ * of the controller. They are initialized using the
+ * XUsbPs_ConfigureDevice() function call.
+ */
+ XUsbPs_DeviceConfig DeviceConfig;
+ /**< Configuration for the DEVICE mode. */
+
+ XUsbPs_IntrHandlerFunc HandlerFunc;
+ /**< Handler function for the controller. */
+ void *HandlerRef;
+ /**< User data reference for the handler. */
+ u32 HandlerMask;
+ /**< User interrupt mask. Defines which interrupts will cause
+ * the callback to be called. */
+} XUsbPs;
+
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/******************************************************************************
+ *
+ * USB CONTROLLER RELATED MACROS
+ *
+ ******************************************************************************/
+/*****************************************************************************/
+/**
+ * This macro returns the current frame number.
+ *
+ * @param InstancePtr is a pointer to the XUsbPs instance of the
+ * controller.
+ *
+ * @return The current frame number.
+ *
+ * @note C-style signature:
+ * u32 XUsbPs_GetFrameNum(const XUsbPs *InstancePtr)
+ *
+ ******************************************************************************/
+#define XUsbPs_GetFrameNum(InstancePtr) \
+ XUsbPs_ReadReg((InstancePtr)->Config.BaseAddress, XUSBPS_FRAME_OFFSET)
+
+
+/*****************************************************************************/
+/**
+ * This macro starts the USB engine.
+ *
+ * @param InstancePtr is a pointer to the XUsbPs instance of the
+ * controller.
+ *
+ * @note C-style signature:
+ * void XUsbPs_Start(XUsbPs *InstancePtr)
+ *
+ ******************************************************************************/
+#define XUsbPs_Start(InstancePtr) \
+ XUsbPs_SetBits(InstancePtr, XUSBPS_CMD_OFFSET, XUSBPS_CMD_RS_MASK)
+
+
+/*****************************************************************************/
+/**
+ * This macro stops the USB engine.
+ *
+ * @param InstancePtr is a pointer to the XUsbPs instance of the
+ * controller.
+ *
+ * @note C-style signature:
+ * void XUsbPs_Stop(XUsbPs *InstancePtr)
+ *
+ ******************************************************************************/
+#define XUsbPs_Stop(InstancePtr) \
+ XUsbPs_ClrBits(InstancePtr, XUSBPS_CMD_OFFSET, XUSBPS_CMD_RS_MASK)
+
+
+/*****************************************************************************/
+/**
+ * This macro forces the USB engine to be in Full Speed (FS) mode.
+ *
+ * @param InstancePtr is a pointer to the XUsbPs instance of the
+ * controller.
+ *
+ * @note C-style signature:
+ * void XUsbPs_ForceFS(XUsbPs *InstancePtr)
+ *
+ ******************************************************************************/
+#define XUsbPs_ForceFS(InstancePtr) \
+ XUsbPs_SetBits(InstancePtr, XUSBPS_PORTSCR1_OFFSET, \
+ XUSBPS_PORTSCR_PFSC_MASK)
+
+
+/*****************************************************************************/
+/**
+ * This macro starts the USB Timer 0, with repeat option for period of
+ * one second.
+ *
+ * @param InstancePtr is a pointer to XUsbPs instance of the controller.
+ * @param Interval is the interval for Timer0 to generate an interrupt
+ *
+ * @note C-style signature:
+ * void XUsbPs_StartTimer0(XUsbPs *InstancePtr, u32 Interval)
+ *
+ ******************************************************************************/
+#define XUsbPs_StartTimer0(InstancePtr, Interval) \
+{ \
+ XUsbPs_WriteReg((InstancePtr)->Config.BaseAddress, \
+ XUSBPS_TIMER0_LD_OFFSET, (Interval)); \
+ XUsbPs_SetBits(InstancePtr, XUSBPS_TIMER0_CTL_OFFSET, \
+ XUSBPS_TIMER_RUN_MASK | \
+ XUSBPS_TIMER_RESET_MASK | \
+ XUSBPS_TIMER_REPEAT_MASK); \
+} \
+
+
+/*****************************************************************************/
+/**
+* This macro stops Timer 0.
+*
+* @param InstancePtr is a pointer to XUsbPs instance of the controller.
+*
+* @note C-style signature:
+* void XUsbPs_StopTimer0(XUsbPs *InstancePtr)
+*
+******************************************************************************/
+#define XUsbPs_StopTimer0(InstancePtr) \
+ XUsbPs_ClrBits(InstancePtr, XUSBPS_TIMER0_CTL_OFFSET, \
+ XUSBPS_TIMER_RUN_MASK)
+
+
+/*****************************************************************************/
+/**
+* This macro reads Timer 0.
+*
+* @param InstancePtr is a pointer to XUsbPs instance of the controller.
+*
+* @note C-style signature:
+* void XUsbPs_ReadTimer0(XUsbPs *InstancePtr)
+*
+******************************************************************************/
+#define XUsbPs_ReadTimer0(InstancePtr) \
+ XUsbPs_ReadReg((InstancePtr)->Config.BaseAddress, \
+ XUSBPS_TIMER0_CTL_OFFSET) & \
+ XUSBPS_TIMER_COUNTER_MASK
+
+
+/*****************************************************************************/
+/**
+* This macro force remote wakeup on host
+*
+* @param InstancePtr is a pointer to XUsbPs instance of the controller.
+*
+* @note C-style signature:
+* void XUsbPs_RemoteWakeup(XUsbPs *InstancePtr)
+*
+******************************************************************************/
+#define XUsbPs_RemoteWakeup(InstancePtr) \
+ XUsbPs_SetBits(InstancePtr, XUSBPS_PORTSCR1_OFFSET, \
+ XUSBPS_PORTSCR_FPR_MASK)
+
+
+/******************************************************************************
+ *
+ * ENDPOINT RELATED MACROS
+ *
+ ******************************************************************************/
+/*****************************************************************************/
+/**
+* This macro enables the given endpoint for the given direction.
+*
+* @param InstancePtr is a pointer to the XUsbPs instance of the
+* controller.
+* @param EpNum is number of the endpoint to enable.
+* @param Dir is direction of the endpoint (bitfield):
+* - XUSBPS_EP_DIRECTION_OUT
+* - XUSBPS_EP_DIRECTION_IN
+*
+* @note C-style signature:
+* void XUsbPs_EpEnable(XUsbPs *InstancePtr, u8 EpNum, u8 Dir)
+*
+******************************************************************************/
+#define XUsbPs_EpEnable(InstancePtr, EpNum, Dir) \
+ XUsbPs_SetBits(InstancePtr, XUSBPS_EPCRn_OFFSET(EpNum), \
+ ((Dir) & XUSBPS_EP_DIRECTION_OUT ? XUSBPS_EPCR_RXE_MASK : 0) | \
+ ((Dir) & XUSBPS_EP_DIRECTION_IN ? XUSBPS_EPCR_TXE_MASK : 0))
+
+
+/*****************************************************************************/
+/**
+* This macro disables the given endpoint for the given direction.
+*
+* @param InstancePtr is a pointer to the XUsbPs instance of the
+* controller.
+* @param EpNum is the number of the endpoint to disable.
+* @param Dir is the direction of the endpoint (bitfield):
+* - XUSBPS_EP_DIRECTION_OUT
+* - XUSBPS_EP_DIRECTION_IN
+*
+* @note C-style signature:
+* void XUsbPs_EpDisable(XUsbPs *InstancePtr, u8 EpNum, u8 Dir)
+*
+******************************************************************************/
+#define XUsbPs_EpDisable(InstancePtr, EpNum, Dir) \
+ XUsbPs_ClrBits(InstancePtr, XUSBPS_EPCRn_OFFSET(EpNum), \
+ ((Dir) & XUSBPS_EP_DIRECTION_OUT ? XUSBPS_EPCR_RXE_MASK : 0) | \
+ ((Dir) & XUSBPS_EP_DIRECTION_IN ? XUSBPS_EPCR_TXE_MASK : 0))
+
+
+/*****************************************************************************/
+/**
+* This macro stalls the given endpoint for the given direction, and flush
+* the buffers.
+*
+* @param InstancePtr is a pointer to the XUsbPs instance of the
+* controller.
+* @param EpNum is number of the endpoint to stall.
+* @param Dir is the direction of the endpoint (bitfield):
+* - XUSBPS_EP_DIRECTION_OUT
+* - XUSBPS_EP_DIRECTION_IN
+*
+* @note C-style signature:
+* void XUsbPs_EpStall(XUsbPs *InstancePtr, u8 EpNum, u8 Dir)
+*
+******************************************************************************/
+#define XUsbPs_EpStall(InstancePtr, EpNum, Dir) \
+ XUsbPs_SetBits(InstancePtr, XUSBPS_EPCRn_OFFSET(EpNum), \
+ ((Dir) & XUSBPS_EP_DIRECTION_OUT ? XUSBPS_EPCR_RXS_MASK : 0) | \
+ ((Dir) & XUSBPS_EP_DIRECTION_IN ? XUSBPS_EPCR_TXS_MASK : 0))
+
+
+/*****************************************************************************/
+/**
+* This macro unstalls the given endpoint for the given direction.
+*
+* @param InstancePtr is a pointer to the XUsbPs instance of the
+* controller.
+* @param EpNum is the Number of the endpoint to unstall.
+* @param Dir is the Direction of the endpoint (bitfield):
+* - XUSBPS_EP_DIRECTION_OUT
+* - XUSBPS_EP_DIRECTION_IN
+*
+* @note C-style signature:
+* void XUsbPs_EpUnStall(XUsbPs *InstancePtr, u8 EpNum, u8 Dir)
+*
+******************************************************************************/
+#define XUsbPs_EpUnStall(InstancePtr, EpNum, Dir) \
+ XUsbPs_ClrBits(InstancePtr, XUSBPS_EPCRn_OFFSET(EpNum), \
+ ((Dir) & XUSBPS_EP_DIRECTION_OUT ? XUSBPS_EPCR_RXS_MASK : 0) | \
+ ((Dir) & XUSBPS_EP_DIRECTION_IN ? XUSBPS_EPCR_TXS_MASK : 0))
+
+
+/*****************************************************************************/
+/**
+* This macro flush an endpoint upon interface disable
+*
+* @param InstancePtr is a pointer to the XUsbPs instance of the
+* controller.
+* @param EpNum is the number of the endpoint to flush.
+* @param Dir is the direction of the endpoint (bitfield):
+* - XUSBPS_EP_DIRECTION_OUT
+* - XUSBPS_EP_DIRECTION_IN
+*
+* @note C-style signature:
+* void XUsbPs_EpFlush(XUsbPs *InstancePtr, u8 EpNum, u8 Dir)
+*
+******************************************************************************/
+#define XUsbPs_EpFlush(InstancePtr, EpNum, Dir) \
+ XUsbPs_SetBits(InstancePtr, XUSBPS_EPFLUSH_OFFSET, \
+ 1 << (EpNum + ((Dir) & XUSBPS_EP_DIRECTION_OUT ? \
+ XUSBPS_EPFLUSH_RX_SHIFT:XUSBPS_EPFLUSH_TX_SHIFT))) \
+
+/*****************************************************************************/
+/**
+* This macro enables the interrupts defined by the bit mask.
+*
+* @param InstancePtr is a pointer to XUsbPs instance of the controller.
+* @param IntrMask is the Bit mask of interrupts to be enabled.
+*
+* @note C-style signature:
+* void XUsbPs_IntrEnable(XUsbPs *InstancePtr, u32 IntrMask)
+*
+******************************************************************************/
+#define XUsbPs_IntrEnable(InstancePtr, IntrMask) \
+ XUsbPs_SetBits(InstancePtr, XUSBPS_IER_OFFSET, IntrMask)
+
+
+/*****************************************************************************/
+/**
+* This function disables the interrupts defined by the bit mask.
+*
+*
+* @param InstancePtr is a pointer to XUsbPs instance of the controller.
+* @param IntrMask is a Bit mask of interrupts to be disabled.
+*
+* @note C-style signature:
+* void XUsbPs_IntrDisable(XUsbPs *InstancePtr, u32 IntrMask)
+*
+******************************************************************************/
+#define XUsbPs_IntrDisable(InstancePtr, IntrMask) \
+ XUsbPs_ClrBits(InstancePtr, XUSBPS_IER_OFFSET, IntrMask)
+
+
+/*****************************************************************************/
+/**
+* This macro enables the endpoint NAK interrupts defined by the bit mask.
+*
+* @param InstancePtr is a pointer to XUsbPs instance of the controller.
+* @param NakIntrMask is the Bit mask of endpoint NAK interrupts to be
+* enabled.
+* @note C-style signature:
+* void XUsbPs_NakIntrEnable(XUsbPs *InstancePtr, u32 NakIntrMask)
+*
+******************************************************************************/
+#define XUsbPs_NakIntrEnable(InstancePtr, NakIntrMask) \
+ XUsbPs_SetBits(InstancePtr, XUSBPS_EPNAKIER_OFFSET, NakIntrMask)
+
+
+/*****************************************************************************/
+/**
+* This macro disables the endpoint NAK interrupts defined by the bit mask.
+*
+* @param InstancePtr is a pointer to XUsbPs instance of the controller.
+* @param NakIntrMask is a Bit mask of endpoint NAK interrupts to be
+* disabled.
+*
+* @note
+* C-style signature:
+* void XUsbPs_NakIntrDisable(XUsbPs *InstancePtr, u32 NakIntrMask)
+*
+******************************************************************************/
+#define XUsbPs_NakIntrDisable(InstancePtr, NakIntrMask) \
+ XUsbPs_ClrBits(InstancePtr, XUSBPS_EPNAKIER_OFFSET, NakIntrMask)
+
+
+/*****************************************************************************/
+/**
+* This function clears the endpoint NAK interrupts status defined by the
+* bit mask.
+*
+* @param InstancePtr is a pointer to XUsbPs instance of the controller.
+* @param NakIntrMask is the Bit mask of endpoint NAK interrupts to be cleared.
+*
+* @note C-style signature:
+* void XUsbPs_NakIntrClear(XUsbPs *InstancePtr, u32 NakIntrMask)
+*
+******************************************************************************/
+#define XUsbPs_NakIntrClear(InstancePtr, NakIntrMask) \
+ XUsbPs_WriteReg((InstancePtr)->Config.BaseAddress, \
+ XUSBPS_EPNAKISR_OFFSET, NakIntrMask)
+
+
+
+/*****************************************************************************/
+/**
+* This macro sets the Interrupt Threshold value in the control register
+*
+* @param InstancePtr is a pointer to XUsbPs instance of the controller.
+* @param Threshold is the Interrupt threshold to be set.
+* Allowed values:
+* - XUSBPS_CMD_ITHRESHOLD_0 - Immediate interrupt
+* - XUSBPS_CMD_ITHRESHOLD_1 - 1 Frame
+* - XUSBPS_CMD_ITHRESHOLD_2 - 2 Frames
+* - XUSBPS_CMD_ITHRESHOLD_4 - 4 Frames
+* - XUSBPS_CMD_ITHRESHOLD_8 - 8 Frames
+* - XUSBPS_CMD_ITHRESHOLD_16 - 16 Frames
+* - XUSBPS_CMD_ITHRESHOLD_32 - 32 Frames
+* - XUSBPS_CMD_ITHRESHOLD_64 - 64 Frames
+*
+* @note
+* C-style signature:
+* void XUsbPs_SetIntrThreshold(XUsbPs *InstancePtr, u8 Threshold)
+*
+******************************************************************************/
+#define XUsbPs_SetIntrThreshold(InstancePtr, Threshold) \
+ XUsbPs_WriteReg((InstancePtr)->Config.BaseAddress, \
+ XUSBPS_CMD_OFFSET, (Threshold))\
+
+
+/*****************************************************************************/
+/**
+* This macro sets the Tripwire bit in the USB command register.
+*
+* @param InstancePtr is a pointer to XUsbPs instance of the controller.
+*
+* @note C-style signature:
+* void XUsbPs_SetTripwire(XUsbPs *InstancePtr)
+*
+******************************************************************************/
+#define XUsbPs_SetSetupTripwire(InstancePtr) \
+ XUsbPs_SetBits(InstancePtr, XUSBPS_CMD_OFFSET, \
+ XUSBPS_CMD_SUTW_MASK)
+
+
+/*****************************************************************************/
+/**
+* This macro clears the Tripwire bit in the USB command register.
+*
+* @param InstancePtr is a pointer to XUsbPs instance of the controller.
+*
+* @note C-style signature:
+* void XUsbPs_ClrTripwire(XUsbPs *InstancePtr)
+*
+******************************************************************************/
+#define XUsbPs_ClrSetupTripwire(InstancePtr) \
+ XUsbPs_ClrBits(InstancePtr, XUSBPS_CMD_OFFSET, \
+ XUSBPS_CMD_SUTW_MASK)
+
+
+/*****************************************************************************/
+/**
+* This macro checks if the Tripwire bit in the USB command register is set.
+*
+* @param InstancePtr is a pointer to XUsbPs instance of the controller.
+*
+* @return
+* - TRUE: The tripwire bit is still set.
+* - FALSE: The tripwire bit has been cleared.
+*
+* @note C-style signature:
+* int XUsbPs_TripwireIsSet(XUsbPs *InstancePtr)
+*
+******************************************************************************/
+#define XUsbPs_SetupTripwireIsSet(InstancePtr) \
+ (XUsbPs_ReadReg((InstancePtr)->Config.BaseAddress, \
+ XUSBPS_CMD_OFFSET) & \
+ XUSBPS_CMD_SUTW_MASK ? TRUE : FALSE)
+
+
+/******************************************************************************
+*
+* GENERAL REGISTER / BIT MANIPULATION MACROS
+*
+******************************************************************************/
+/****************************************************************************/
+/**
+* This macro sets the given bit mask in the register.
+*
+* @param InstancePtr is a pointer to XUsbPs instance of the controller.
+* @param RegOffset is the register offset to be written.
+* @param Bits is the Bits to be set in the register
+*
+* @return None.
+*
+* @note C-style signature:
+* void XUsbPs_SetBits(u32 BaseAddress, u32 RegOffset, u32 Bits)
+*
+*****************************************************************************/
+#define XUsbPs_SetBits(InstancePtr, RegOffset, Bits) \
+ XUsbPs_WriteReg((InstancePtr)->Config.BaseAddress, RegOffset, \
+ XUsbPs_ReadReg((InstancePtr)->Config.BaseAddress, \
+ RegOffset) | (Bits));
+
+
+/****************************************************************************/
+/**
+*
+* This macro clears the given bits in the register.
+*
+* @param InstancePtr is a pointer to XUsbPs instance of the controller.
+* @param RegOffset is the register offset to be written.
+* @param Bits are the bits to be cleared in the register
+*
+* @return None.
+*
+* @note
+* C-style signature:
+* void XUsbPs_ClrBits(u32 BaseAddress, u32 RegOffset, u32 Bits)
+*
+*****************************************************************************/
+#define XUsbPs_ClrBits(InstancePtr, RegOffset, Bits) \
+ XUsbPs_WriteReg((InstancePtr)->Config.BaseAddress, RegOffset, \
+ XUsbPs_ReadReg((InstancePtr)->Config.BaseAddress, \
+ RegOffset) & ~(Bits));
+
+
+/************************** Function Prototypes ******************************/
+
+/**
+ * Setup / Initialize functions.
+ *
+ * Implemented in file xusbps.c
+ */
+int XUsbPs_CfgInitialize(XUsbPs *InstancePtr,
+ const XUsbPs_Config *ConfigPtr, u32 BaseAddress);
+
+int XUsbPs_ConfigureDevice(XUsbPs *InstancePtr,
+ const XUsbPs_DeviceConfig *CfgPtr);
+
+/**
+ * Common functions used for DEVICE/HOST mode.
+ */
+int XUsbPs_Reset(XUsbPs *InstancePtr);
+
+void XUsbPs_DeviceReset(XUsbPs *InstancePtr);
+
+/**
+ * DEVICE mode specific functions.
+ */
+int XUsbPs_BusReset(XUsbPs *InstancePtr);
+int XUsbPs_SetDeviceAddress(XUsbPs *InstancePtr, u8 Address);
+
+
+/**
+ * Handling Suspend and Resume.
+ *
+ * Implemented in xusbps.c
+ */
+int XUsbPs_Suspend(const XUsbPs *InstancePtr);
+int XUsbPs_Resume(const XUsbPs *InstancePtr);
+int XUsbPs_RequestHostResume(const XUsbPs *InstancePtr);
+
+
+/*
+ * Functions for managing Endpoints / Transfers
+ *
+ * Implemented in file xusbps_endpoint.c
+ */
+int XUsbPs_EpBufferSend(XUsbPs *InstancePtr, u8 EpNum,
+ const u8 *BufferPtr, u32 BufferLen);
+int XUsbPs_EpBufferSendWithZLT(XUsbPs *InstancePtr, u8 EpNum,
+ const u8 *BufferPtr, u32 BufferLen);
+int XUsbPs_EpBufferReceive(XUsbPs *InstancePtr, u8 EpNum,
+ u8 **BufferPtr, u32 *BufferLenPtr, u32 *Handle);
+void XUsbPs_EpBufferRelease(u32 Handle);
+
+int XUsbPs_EpSetHandler(XUsbPs *InstancePtr, u8 EpNum, u8 Direction,
+ XUsbPs_EpHandlerFunc CallBackFunc,
+ void *CallBackRef);
+int XUsbPs_EpGetSetupData(XUsbPs *InstancePtr, int EpNum,
+ XUsbPs_SetupData *SetupDataPtr);
+
+int XUsbPs_EpPrime(XUsbPs *InstancePtr, u8 EpNum, u8 Direction);
+
+int XUsbPs_ReconfigureEp(XUsbPs *InstancePtr, XUsbPs_DeviceConfig *CfgPtr,
+ int EpNum, unsigned short NewDirection, int DirectionChanged);
+
+/*
+ * Interrupt handling functions
+ *
+ * Implemented in file xusbps_intr.c
+ */
+void XUsbPs_IntrHandler(void *InstancePtr);
+
+int XUsbPs_IntrSetHandler(XUsbPs *InstancePtr,
+ XUsbPs_IntrHandlerFunc CallBackFunc,
+ void *CallBackRef, u32 Mask);
+/*
+ * Helper functions for static configuration.
+ * Implemented in xusbps_sinit.c
+ */
+XUsbPs_Config *XUsbPs_LookupConfig(u16 DeviceId);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* XUSBPS_H */
+/** @} */
diff --git a/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/usbps_v2_4/src/xusbps_endpoint.c b/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/usbps_v2_4/src/xusbps_endpoint.c
new file mode 100644
index 0000000..937ef2e
--- /dev/null
+++ b/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/usbps_v2_4/src/xusbps_endpoint.c
@@ -0,0 +1,1448 @@
+/******************************************************************************
+*
+* Copyright (C) 2010 - 2015 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+* THE SOFTWARE.
+*
+*
+*
+******************************************************************************/
+/******************************************************************************/
+/**
+ * @file xusbps_endpoint.c
+* @addtogroup usbps_v2_4
+* @{
+ *
+ * Endpoint specific function implementations.
+ *
+ * @note None.
+ *
+ * <pre>
+ * MODIFICATION HISTORY:
+ *
+ * Ver Who Date Changes
+ * ----- ---- -------- --------------------------------------------------------
+ * 1.00a jz 10/10/10 First release
+ * 1.03a nm 09/21/12 Fixed CR#678977. Added proper sequence for setup packet
+ * handling.
+ * 1.04a nm 11/02/12 Fixed CR#683931. Mult bits are set properly in dQH.
+ * 2.00a kpc 04/03/14 Fixed CR#777763. Updated the macro names
+ * 2.1 kpc 04/28/14 Added XUsbPs_EpBufferSendWithZLT api and merged common
+ * code to XUsbPs_EpQueueRequest.
+ * 2.3 bss 01/19/16 Modified XUsbPs_EpQueueRequest function to fix CR#873972
+ * (moving of dTD Head/Tail Pointers)and CR#873974(invalidate
+ * Caches After Buffer Receive in Endpoint Buffer Handler...)
+ * </pre>
+ ******************************************************************************/
+
+/***************************** Include Files **********************************/
+
+#include <string.h> /* for bzero() */
+#include <stdio.h>
+
+#include "xusbps.h"
+#include "xusbps_endpoint.h"
+
+/************************** Constant Definitions ******************************/
+
+/**************************** Type Definitions ********************************/
+
+/************************** Variable Definitions ******************************/
+
+/************************** Function Prototypes ******************************/
+
+static void XUsbPs_EpListInit(XUsbPs_DeviceConfig *DevCfgPtr);
+static void XUsbPs_dQHInit(XUsbPs_DeviceConfig *DevCfgPtr);
+static int XUsbPs_dTDInit(XUsbPs_DeviceConfig *DevCfgPtr);
+static int XUsbPs_dTDAttachBuffer(XUsbPs_dTD *dTDPtr,
+ const u8 *BufferPtr, u32 BufferLen);
+
+static void XUsbPs_dQHSetMaxPacketLenISO(XUsbPs_dQH *dQHPtr, u32 Len);
+
+/* Functions to reconfigure endpoint upon host's set alternate interface
+ * request.
+ */
+static void XUsbPs_dQHReinitEp(XUsbPs_DeviceConfig *DevCfgPtr,
+ int EpNum, unsigned short NewDirection);
+static int XUsbPs_dTDReinitEp(XUsbPs_DeviceConfig *DevCfgPtr,
+ int EpNum, unsigned short NewDirection);
+static int XUsbPs_EpQueueRequest(XUsbPs *InstancePtr, u8 EpNum,
+ const u8 *BufferPtr, u32 BufferLen, u8 ReqZero);
+
+/******************************* Functions ************************************/
+
+/*****************************************************************************/
+/**
+ *
+ * This function configures the DEVICE side of the controller. The caller needs
+ * to pass in the desired configuration (e.g. number of endpoints) and a
+ * DMAable buffer that will hold the Queue Head List and the Transfer
+ * Descriptors. The required size for this buffer can be obtained by the caller
+ * using the: XUsbPs_DeviceMemRequired() macro.
+ *
+ * @param InstancePtr is a pointer to the XUsbPs instance of the
+ * controller.
+ * @param CfgPtr is a pointer to the configuration structure that contains
+ * the desired DEVICE side configuration.
+ *
+ * @return
+ * - XST_SUCCESS: The operation completed successfully.
+ * - XST_FAILURE: An error occurred.
+ *
+ * @note
+ * The caller may configure the controller for both, DEVICE and
+ * HOST side.
+ *
+ ******************************************************************************/
+int XUsbPs_ConfigureDevice(XUsbPs *InstancePtr,
+ const XUsbPs_DeviceConfig *CfgPtr)
+{
+ int Status;
+ u32 ModeValue = 0x0;
+
+ Xil_AssertNonvoid(InstancePtr != NULL);
+ Xil_AssertNonvoid(CfgPtr != NULL);
+
+ /* Copy the configuration data over into the local instance structure */
+ InstancePtr->DeviceConfig = *CfgPtr;
+
+
+ /* Align the buffer to a 2048 byte (XUSBPS_dQH_BASE_ALIGN) boundary.*/
+ InstancePtr->DeviceConfig.PhysAligned =
+ (InstancePtr->DeviceConfig.DMAMemPhys +
+ XUSBPS_dQH_BASE_ALIGN) &
+ ~(XUSBPS_dQH_BASE_ALIGN -1);
+
+ /* Initialize the endpoint pointer list data structure. */
+ XUsbPs_EpListInit(&InstancePtr->DeviceConfig);
+
+
+ /* Initialize the Queue Head structures in DMA memory. */
+ XUsbPs_dQHInit(&InstancePtr->DeviceConfig);
+
+
+ /* Initialize the Transfer Descriptors in DMA memory.*/
+ Status = XUsbPs_dTDInit(&InstancePtr->DeviceConfig);
+ if (XST_SUCCESS != Status) {
+ return XST_FAILURE;
+ }
+
+ /* Changing the DEVICE mode requires a controller RESET. */
+ if (XST_SUCCESS != XUsbPs_Reset(InstancePtr)) {
+ return XST_FAILURE;
+ }
+
+ /* Set the Queue Head List address. */
+ XUsbPs_WriteReg(InstancePtr->Config.BaseAddress,
+ XUSBPS_EPLISTADDR_OFFSET,
+ InstancePtr->DeviceConfig.PhysAligned);
+
+ /* Set the USB mode register to configure DEVICE mode.
+ *
+ * XUSBPS_MODE_SLOM_MASK note:
+ * Disable Setup Lockout. Setup Lockout is not required as we
+ * will be using the tripwire mechanism when handling setup
+ * packets.
+ */
+ ModeValue = XUSBPS_MODE_CM_DEVICE_MASK | XUSBPS_MODE_SLOM_MASK;
+
+ XUsbPs_WriteReg(InstancePtr->Config.BaseAddress,
+ XUSBPS_MODE_OFFSET, ModeValue);
+
+ XUsbPs_SetBits(InstancePtr, XUSBPS_OTGCSR_OFFSET,
+ XUSBPS_OTGSC_OT_MASK);
+
+ return XST_SUCCESS;
+}
+
+/*****************************************************************************/
+/**
+* This function sends a given data buffer.
+*
+* @param InstancePtr is a pointer to XUsbPs instance of the controller.
+* @param EpNum is the number of the endpoint to receive data from.
+* @param BufferPtr is a pointer to the buffer to send.
+* @param BufferLen is the Buffer length.
+*
+* @return
+* - XST_SUCCESS: The operation completed successfully.
+* - XST_FAILURE: An error occurred.
+* - XST_USB_BUF_TOO_BIG: Provided buffer is too big (>16kB).
+* - XST_USB_NO_DESC_AVAILABLE: No TX descriptor is available.
+*
+******************************************************************************/
+int XUsbPs_EpBufferSend(XUsbPs *InstancePtr, u8 EpNum,
+ const u8 *BufferPtr, u32 BufferLen)
+{
+ Xil_AssertNonvoid(InstancePtr != NULL);
+ Xil_AssertNonvoid(EpNum < InstancePtr->DeviceConfig.NumEndpoints);
+
+ return XUsbPs_EpQueueRequest(InstancePtr, EpNum, BufferPtr,
+ BufferLen, FALSE);
+}
+
+/*****************************************************************************/
+/**
+* This function sends a given data buffer and also zero length packet if the
+* Bufferlen is in multiples of endpoint max packet size.
+*
+* @param InstancePtr is a pointer to XUsbPs instance of the controller.
+* @param EpNum is the number of the endpoint to receive data from.
+* @param BufferPtr is a pointer to the buffer to send.
+* @param BufferLen is the Buffer length.
+*
+* @return
+* - XST_SUCCESS: The operation completed successfully.
+* - XST_FAILURE: An error occurred.
+* - XST_USB_BUF_TOO_BIG: Provided buffer is too big (>16kB).
+* - XST_USB_NO_DESC_AVAILABLE: No TX descriptor is available.
+*
+******************************************************************************/
+int XUsbPs_EpBufferSendWithZLT(XUsbPs *InstancePtr, u8 EpNum,
+ const u8 *BufferPtr, u32 BufferLen)
+{
+ u8 ReqZero = FALSE;
+ XUsbPs_EpSetup *Ep;
+
+ Xil_AssertNonvoid(InstancePtr != NULL);
+ Xil_AssertNonvoid(EpNum < InstancePtr->DeviceConfig.NumEndpoints);
+
+ Ep = &InstancePtr->DeviceConfig.EpCfg[EpNum].In;
+
+ if ((BufferLen >= Ep->MaxPacketSize) &&
+ (BufferLen % Ep->MaxPacketSize == 0)) {
+ ReqZero = TRUE;
+ }
+
+ return XUsbPs_EpQueueRequest(InstancePtr, EpNum, BufferPtr,
+ BufferLen, ReqZero);
+}
+
+/*****************************************************************************/
+/**
+* This function sends a given data buffer and also sends ZLT packet if it is
+* requested.
+*
+* @param InstancePtr is a pointer to XUsbPs instance of the controller.
+* @param EpNum is the number of the endpoint to receive data from.
+* @param BufferPtr is a pointer to the buffer to send.
+* @param BufferLen is the Buffer length.
+* @param ReqZero is the
+*
+* @return
+* - XST_SUCCESS: The operation completed successfully.
+* - XST_FAILURE: An error occurred.
+* - XST_USB_BUF_TOO_BIG: Provided buffer is too big (>16kB).
+* - XST_USB_NO_DESC_AVAILABLE: No TX descriptor is available.
+*
+******************************************************************************/
+static int XUsbPs_EpQueueRequest(XUsbPs *InstancePtr, u8 EpNum,
+ const u8 *BufferPtr, u32 BufferLen, u8 ReqZero)
+{
+ int Status;
+ u32 Token;
+ XUsbPs_EpIn *Ep;
+ XUsbPs_dTD *DescPtr;
+ u32 Length;
+ u32 PipeEmpty = 1;
+ u32 Mask = 0x00010000;
+ u32 BitMask = Mask << EpNum;
+ u32 RegValue;
+ u32 Temp;
+ u32 exit = 1;
+
+
+ /* Locate the next available buffer in the ring. A buffer is available
+ * if its descriptor is not active.
+ */
+ Ep = &InstancePtr->DeviceConfig.Ep[EpNum].In;
+
+ Xil_DCacheFlushRange((unsigned int)BufferPtr, BufferLen);
+
+ if(Ep->dTDTail != Ep->dTDHead) {
+ PipeEmpty = 0;
+ }
+ XUsbPs_dTDInvalidateCache(Ep->dTDHead);
+
+ /* Tell the caller if we do not have any descriptors available. */
+ if (XUsbPs_dTDIsActive(Ep->dTDHead)) {
+ return XST_USB_NO_DESC_AVAILABLE;
+ }
+
+ /* Remember the current head. */
+ DescPtr = Ep->dTDHead;
+
+ do {
+
+ /* Tell the caller if we do not have any descriptors available. */
+ if (XUsbPs_dTDIsActive(Ep->dTDHead)) {
+ return XST_USB_NO_DESC_AVAILABLE;
+ }
+
+ Length = (BufferLen > XUSBPS_dTD_BUF_MAX_SIZE) ? XUSBPS_dTD_BUF_MAX_SIZE : BufferLen;
+ /* Attach the provided buffer to the current descriptor.*/
+ Status = XUsbPs_dTDAttachBuffer(Ep->dTDHead, BufferPtr, Length);
+ if (XST_SUCCESS != Status) {
+ return XST_FAILURE;
+ }
+ BufferLen -= Length;
+ BufferPtr += Length;
+
+ XUsbPs_dTDSetActive(Ep->dTDHead);
+ if (BufferLen == 0 && (ReqZero == FALSE)) {
+ XUsbPs_dTDSetIOC(Ep->dTDHead);
+ exit = 0;
+ }
+ XUsbPs_dTDClrTerminate(Ep->dTDHead);
+ XUsbPs_dTDFlushCache(Ep->dTDHead);
+
+ /* Advance the head descriptor pointer to the next descriptor. */
+ Ep->dTDHead = XUsbPs_dTDGetNLP(Ep->dTDHead);
+ /* Terminate the next descriptor and flush the cache.*/
+ XUsbPs_dTDInvalidateCache(Ep->dTDHead);
+
+ if (ReqZero && BufferLen == 0) {
+ ReqZero = FALSE;
+ }
+
+ } while(BufferLen || exit);
+
+ XUsbPs_dTDSetTerminate(Ep->dTDHead);
+ XUsbPs_dTDFlushCache(Ep->dTDHead);
+
+ if(!PipeEmpty) {
+ /* Read the endpoint prime register. */
+ RegValue = XUsbPs_ReadReg(InstancePtr->Config.BaseAddress, XUSBPS_EPPRIME_OFFSET);
+ if(RegValue & BitMask) {
+ return XST_SUCCESS;
+ }
+
+ do {
+ RegValue = XUsbPs_ReadReg(InstancePtr->Config.BaseAddress, XUSBPS_CMD_OFFSET);
+ XUsbPs_WriteReg(InstancePtr->Config.BaseAddress, XUSBPS_CMD_OFFSET,
+ RegValue | XUSBPS_CMD_ATDTW_MASK);
+ Temp = XUsbPs_ReadReg(InstancePtr->Config.BaseAddress, XUSBPS_EPRDY_OFFSET)
+ & BitMask;
+ } while(!(XUsbPs_ReadReg(InstancePtr->Config.BaseAddress, XUSBPS_CMD_OFFSET) &
+ XUSBPS_CMD_ATDTW_MASK));
+
+ RegValue = XUsbPs_ReadReg(InstancePtr->Config.BaseAddress, XUSBPS_CMD_OFFSET);
+ XUsbPs_WriteReg(InstancePtr->Config.BaseAddress, XUSBPS_CMD_OFFSET,
+ RegValue & ~XUSBPS_CMD_ATDTW_MASK);
+
+ if(Temp) {
+ return XST_SUCCESS;
+ }
+ }
+
+ /* Check, if the DMA engine is still running. If it is running, we do
+ * not clear Queue Head fields.
+ *
+ * Same cache rule as for the Transfer Descriptor applies for the Queue
+ * Head.
+ */
+ XUsbPs_dQHInvalidateCache(Ep->dQH);
+ /* Add the dTD to the dQH */
+ XUsbPs_WritedQH(Ep->dQH, XUSBPS_dQHdTDNLP, DescPtr);
+ Token = XUsbPs_ReaddQH(Ep->dQH, XUSBPS_dQHdTDTOKEN);
+ Token &= ~(XUSBPS_dTDTOKEN_ACTIVE_MASK | XUSBPS_dTDTOKEN_HALT_MASK);
+ XUsbPs_WritedQH(Ep->dQH, XUSBPS_dQHdTDTOKEN, Token);
+
+ XUsbPs_dQHFlushCache(Ep->dQH);
+
+ Status = XUsbPs_EpPrime(InstancePtr, EpNum, XUSBPS_EP_DIRECTION_IN);
+
+ return Status;
+}
+
+/*****************************************************************************/
+/**
+ * This function receives a data buffer from the endpoint of the given endpoint
+ * number.
+ *
+ * @param InstancePtr is a pointer to the XUsbPs instance of the
+ * controller.
+ * @param EpNum is the number of the endpoint to receive data from.
+ * @param BufferPtr (OUT param) is a pointer to the buffer pointer to hold
+ * the reference of the data buffer.
+ * @param BufferLenPtr (OUT param) is a pointer to the integer that will
+ * hold the buffer length.
+ * @param Handle is the opaque handle to be used when the buffer is
+ * released.
+ *
+ * @return
+ * - XST_SUCCESS: The operation completed successfully.
+ * - XST_FAILURE: An error occurred.
+ * - XST_USB_NO_BUF: No buffer available.
+ *
+ * @note
+ * After handling the data in the buffer, the user MUST release
+ * the buffer using the Handle by calling the
+ * XUsbPs_EpBufferRelease() function.
+ *
+ ******************************************************************************/
+int XUsbPs_EpBufferReceive(XUsbPs *InstancePtr, u8 EpNum,
+ u8 **BufferPtr, u32 *BufferLenPtr, u32 *Handle)
+{
+ XUsbPs_EpOut *Ep;
+ XUsbPs_EpSetup *EpSetup;
+ u32 length = 0;
+
+ Xil_AssertNonvoid(InstancePtr != NULL);
+ Xil_AssertNonvoid(BufferPtr != NULL);
+ Xil_AssertNonvoid(BufferLenPtr != NULL);
+ Xil_AssertNonvoid(Handle != NULL);
+ Xil_AssertNonvoid(EpNum < InstancePtr->DeviceConfig.NumEndpoints);
+
+ /* Locate the next available buffer in the ring. A buffer is available
+ * if its descriptor is not active.
+ */
+ Ep = &InstancePtr->DeviceConfig.Ep[EpNum].Out;
+
+ XUsbPs_dTDInvalidateCache(Ep->dTDCurr);
+
+ if (XUsbPs_dTDIsActive(Ep->dTDCurr)) {
+ return XST_USB_NO_BUF;
+ }
+
+ /* The buffer is not active which means that it has been processed by
+ * the DMA engine and contains valid data.
+ */
+ EpSetup = &InstancePtr->DeviceConfig.EpCfg[EpNum].Out;
+
+
+ /* Use the buffer pointer stored in the "user data" field of the
+ * Transfer Descriptor.
+ */
+ *BufferPtr = (u8 *) XUsbPs_ReaddTD(Ep->dTDCurr,
+ XUSBPS_dTDUSERDATA);
+
+ length = EpSetup->BufSize -
+ XUsbPs_dTDGetTransferLen(Ep->dTDCurr);
+
+ if(length > 0) {
+ *BufferLenPtr = length;
+ }else {
+ *BufferLenPtr = 0;
+ }
+
+ *Handle = (u32) Ep->dTDCurr;
+
+
+ /* Reset the descriptor's BufferPointer0 and Transfer Length fields to
+ * their original value. Note that we can not yet re-activate the
+ * descriptor as the caller will be using the attached buffer. Once the
+ * caller releases the buffer by calling XUsbPs_EpBufferRelease(), we
+ * can re-activate the descriptor.
+ */
+ XUsbPs_WritedTD(Ep->dTDCurr, XUSBPS_dTDBPTR0, *BufferPtr);
+ XUsbPs_dTDSetTransferLen(Ep->dTDCurr, EpSetup->BufSize);
+
+ XUsbPs_dTDFlushCache(Ep->dTDCurr);
+
+ return XST_SUCCESS;
+}
+
+
+/*****************************************************************************/
+/**
+* This function returns a previously received data buffer to the driver.
+*
+* @param Handle is a pointer to the buffer that is returned.
+*
+* @return None.
+*
+******************************************************************************/
+void XUsbPs_EpBufferRelease(u32 Handle)
+{
+ XUsbPs_dTD *dTDPtr;
+
+ /* Perform sanity check on Handle.*/
+ Xil_AssertVoid((0 != Handle) && (0 == (Handle % XUSBPS_dTD_ALIGN)));
+
+ /* Activate the descriptor and clear the Terminate bit. Make sure to do
+ * the proper cache handling.
+ */
+ dTDPtr = (XUsbPs_dTD *) Handle;
+
+ XUsbPs_dTDInvalidateCache(dTDPtr);
+
+ XUsbPs_dTDClrTerminate(dTDPtr);
+ XUsbPs_dTDSetActive(dTDPtr);
+ XUsbPs_dTDSetIOC(dTDPtr);
+
+ XUsbPs_dTDFlushCache(dTDPtr);
+
+}
+
+
+/*****************************************************************************/
+/**
+ * This function sets the handler for endpoint events.
+ *
+ * @param InstancePtr is a pointer to the XUsbPs instance of the
+ * controller.
+ * @param EpNum is the number of the endpoint to receive data from.
+ * @param Direction is the direction of the endpoint (bitfield):
+ * - XUSBPS_EP_DIRECTION_OUT
+ * - XUSBPS_EP_DIRECTION_IN
+ * @param CallBackFunc is the Handler callback function.
+ * Can be NULL if the user wants to disable the handler entry.
+ * @param CallBackRef is the user definable data pointer that will be
+ * passed back if the handler is called. May be NULL.
+ *
+ * @return
+ * - XST_SUCCESS: The operation completed successfully.
+ * - XST_FAILURE: An error occurred.
+ * - XST_INVALID_PARAM: Invalid parameter passed.
+ *
+ * @note
+ * The user can disable a handler by setting the callback function
+ * pointer to NULL.
+ *
+ ******************************************************************************/
+int XUsbPs_EpSetHandler(XUsbPs *InstancePtr, u8 EpNum, u8 Direction,
+ XUsbPs_EpHandlerFunc CallBackFunc,
+ void *CallBackRef)
+{
+ XUsbPs_Endpoint *Ep;
+
+ Xil_AssertNonvoid(InstancePtr != NULL);
+ Xil_AssertNonvoid(CallBackFunc != NULL);
+ Xil_AssertNonvoid(EpNum < InstancePtr->DeviceConfig.NumEndpoints);
+
+ Ep = &InstancePtr->DeviceConfig.Ep[EpNum];
+
+ if(Direction & XUSBPS_EP_DIRECTION_OUT) {
+ Ep->Out.HandlerFunc = CallBackFunc;
+ Ep->Out.HandlerRef = CallBackRef;
+ }
+
+ if(Direction & XUSBPS_EP_DIRECTION_IN) {
+ Ep->In.HandlerFunc = CallBackFunc;
+ Ep->In.HandlerRef = CallBackRef;
+ }
+
+ return XST_SUCCESS;
+}
+
+
+/*****************************************************************************/
+/**
+* This function primes an endpoint.
+*
+* @param InstancePtr is pointer to the XUsbPs instance.
+* @param EpNum is the number of the endpoint to receive data from.
+* @param Direction is the direction of the endpoint (bitfield):
+* - XUSBPS_EP_DIRECTION_OUT
+* - XUSBPS_EP_DIRECTION_IN
+*
+* @return
+* - XST_SUCCESS: The operation completed successfully.
+* - XST_FAILURE: An error occurred.
+* - XST_INVALID_PARAM: Invalid parameter passed.
+*
+* @note None.
+*
+******************************************************************************/
+int XUsbPs_EpPrime(XUsbPs *InstancePtr, u8 EpNum, u8 Direction)
+{
+ u32 Mask;
+
+ Xil_AssertNonvoid(InstancePtr != NULL);
+ Xil_AssertNonvoid(EpNum < InstancePtr->DeviceConfig.NumEndpoints);
+
+ /* Get the right bit mask for the endpoint direction. */
+ switch (Direction) {
+
+ case XUSBPS_EP_DIRECTION_OUT:
+ Mask = 0x00000001;
+ break;
+
+ case XUSBPS_EP_DIRECTION_IN:
+ Mask = 0x00010000;
+ break;
+
+ default:
+ return XST_INVALID_PARAM;
+ }
+
+ /* Write the endpoint prime register. */
+ XUsbPs_WriteReg(InstancePtr->Config.BaseAddress,
+ XUSBPS_EPPRIME_OFFSET, Mask << EpNum);
+
+ return XST_SUCCESS;
+}
+
+
+/*****************************************************************************/
+/**
+* This function extracts the Setup Data from a given endpoint.
+*
+* @param InstancePtr is a pointer to the XUsbPs instance of the
+* controller.
+* @param EpNum is the number of the endpoint to receive data from.
+* @param SetupDataPtr is a pointer to the setup data structure to be
+* filled.
+*
+* @return
+* - XST_SUCCESS: The operation completed successfully.
+* - XST_FAILURE: An error occurred.
+*
+* @note None.
+******************************************************************************/
+int XUsbPs_EpGetSetupData(XUsbPs *InstancePtr, int EpNum,
+ XUsbPs_SetupData *SetupDataPtr)
+{
+ XUsbPs_EpOut *Ep;
+
+ u32 Data[2];
+ u8 *p;
+
+ int Timeout;
+
+ Xil_AssertNonvoid(InstancePtr != NULL);
+ Xil_AssertNonvoid(SetupDataPtr != NULL);
+ Xil_AssertNonvoid(EpNum < InstancePtr->DeviceConfig.NumEndpoints);
+
+ Ep = &InstancePtr->DeviceConfig.Ep[EpNum].Out;
+
+
+ /* Get the data from the Queue Heads Setup buffer into local variables
+ * so we can extract the setup data values.
+ */
+ do {
+ /* Arm the tripwire. The tripwire will tell us if a new setup
+ * packet arrived (in which case the tripwire bit will be
+ * cleared) while we were reading the buffer. If a new setup
+ * packet arrived the buffer is corrupted and we continue
+ * reading.
+ */
+ XUsbPs_SetSetupTripwire(InstancePtr);
+
+ XUsbPs_dQHInvalidateCache(Ep->dQH);
+
+ Data[0] = XUsbPs_ReaddQH(Ep->dQH, XUSBPS_dQHSUB0);
+ Data[1] = XUsbPs_ReaddQH(Ep->dQH, XUSBPS_dQHSUB1);
+ } while (FALSE == XUsbPs_SetupTripwireIsSet(InstancePtr));
+
+ /* Clear the pending endpoint setup stat bit.
+ */
+ XUsbPs_WriteReg(InstancePtr->Config.BaseAddress,
+ XUSBPS_EPSTAT_OFFSET, 1 << EpNum);
+
+ /* Clear the Tripwire bit and continue.
+ */
+ XUsbPs_ClrSetupTripwire(InstancePtr);
+
+
+ /* Data in the setup buffer is being converted by the core to big
+ * endian format. We have to take care of proper byte swapping when
+ * reading the setup data values.
+ *
+ * Need to check if there is a smarter way to do this and take the
+ * processor/memory-controller endianness into account?
+ */
+ p = (u8 *) Data;
+
+ SetupDataPtr->bmRequestType = p[0];
+ SetupDataPtr->bRequest = p[1];
+ SetupDataPtr->wValue = (p[3] << 8) | p[2];
+ SetupDataPtr->wIndex = (p[5] << 8) | p[4];
+ SetupDataPtr->wLength = (p[7] << 8) | p[6];
+
+ /* Before we leave we need to make sure that the endpoint setup bit has
+ * cleared. It needs to be 0 before the endpoint can be re-primed.
+ *
+ * Note: According to the documentation this endpoint setup bit should
+ * clear within 1-2us after it has been written above. This means that
+ * we should never catch it being 1 here. However, we still need to
+ * poll it to make sure. Just in case, we use a counter 'Timeout' so we
+ * won't hang here if the bit is stuck for some reason.
+ */
+ Timeout = XUSBPS_TIMEOUT_COUNTER;
+ while ((XUsbPs_ReadReg(InstancePtr->Config.BaseAddress,
+ XUSBPS_EPSTAT_OFFSET) &
+ (1 << EpNum)) && --Timeout) {
+ /* NOP */
+ }
+ if (0 == Timeout) {
+ return XST_FAILURE;
+ }
+
+ return XST_SUCCESS;
+}
+
+
+/*****************************************************************************/
+/**
+*
+* This function initializes the endpoint pointer data structure.
+*
+* The function sets up the local data structure with the aligned addresses for
+* the Queue Head and Transfer Descriptors.
+*
+* @param DevCfgPtr is pointer to the XUsbPs DEVICE configuration
+* structure.
+*
+* @return none
+*
+* @note
+* Endpoints of type XUSBPS_EP_TYPE_NONE are not used in the
+* system. Therefore no memory is reserved for them.
+*
+******************************************************************************/
+static void XUsbPs_EpListInit(XUsbPs_DeviceConfig *DevCfgPtr)
+{
+ int EpNum;
+ u8 *p;
+
+ XUsbPs_Endpoint *Ep;
+ XUsbPs_EpConfig *EpCfg;
+
+ /* Set up the XUsbPs_Endpoint array. This array is used to define the
+ * location of the Queue Head list and the Transfer Descriptors in the
+ * block of DMA memory that has been passed into the driver.
+ *
+ * 'p' is used to set the pointers in the local data structure.
+ * Initially 'p' is pointed to the beginning of the DMAable memory
+ * block. As pointers are assigned, 'p' is incremented by the size of
+ * the respective object.
+ */
+ Ep = DevCfgPtr->Ep;
+ EpCfg = DevCfgPtr->EpCfg;
+
+ /* Start off with 'p' pointing to the (aligned) beginning of the DMA
+ * buffer.
+ */
+ p = (u8 *) DevCfgPtr->PhysAligned;
+
+
+ /* Initialize the Queue Head pointer list.
+ *
+ * Each endpoint has two Queue Heads. One for the OUT direction and one
+ * for the IN direction. An OUT Queue Head is always followed by an IN
+ * Queue Head.
+ *
+ * Queue Head alignment is XUSBPS_dQH_ALIGN.
+ *
+ * Note that we have to reserve space here for unused endpoints.
+ */
+ for (EpNum = 0; EpNum < DevCfgPtr->NumEndpoints; ++EpNum) {
+ /* OUT Queue Head */
+ Ep[EpNum].Out.dQH = (XUsbPs_dQH *) p;
+ p += XUSBPS_dQH_ALIGN;
+
+ /* IN Queue Head */
+ Ep[EpNum].In.dQH = (XUsbPs_dQH *) p;
+ p += XUSBPS_dQH_ALIGN;
+ }
+
+
+ /* 'p' now points to the first address after the Queue Head list. The
+ * Transfer Descriptors start here.
+ *
+ * Each endpoint has a variable number of Transfer Descriptors
+ * depending on user configuration.
+ *
+ * Transfer Descriptor alignment is XUSBPS_dTD_ALIGN.
+ */
+ for (EpNum = 0; EpNum < DevCfgPtr->NumEndpoints; ++EpNum) {
+ /* OUT Descriptors.
+ */
+ if (XUSBPS_EP_TYPE_NONE != EpCfg[EpNum].Out.Type) {
+ Ep[EpNum].Out.dTDs = (XUsbPs_dTD *) p;
+ Ep[EpNum].Out.dTDCurr = (XUsbPs_dTD *) p;
+ p += XUSBPS_dTD_ALIGN * EpCfg[EpNum].Out.NumBufs;
+ }
+
+ /* IN Descriptors.
+ */
+ if (XUSBPS_EP_TYPE_NONE != EpCfg[EpNum].In.Type) {
+ Ep[EpNum].In.dTDs = (XUsbPs_dTD *) p;
+ Ep[EpNum].In.dTDHead = (XUsbPs_dTD *) p;
+ Ep[EpNum].In.dTDTail = (XUsbPs_dTD *) p;
+ p += XUSBPS_dTD_ALIGN * EpCfg[EpNum].In.NumBufs;
+ }
+ }
+
+
+ /* 'p' now points to the first address after the Transfer Descriptors.
+ * The data buffers for the OUT Transfer Descriptors start here.
+ *
+ * Note that IN (TX) Transfer Descriptors are not assigned buffers at
+ * this point. Buffers will be assigned when the user calls the send()
+ * function.
+ */
+ for (EpNum = 0; EpNum < DevCfgPtr->NumEndpoints; ++EpNum) {
+
+ if (XUSBPS_EP_TYPE_NONE != EpCfg[EpNum].Out.Type) {
+ /* If BufSize for this endpoint is set to 0 it means
+ * that we do not need to attach a buffer to this
+ * descriptor. We also initialize it's buffer pointer
+ * to NULL.
+ */
+ if (0 == EpCfg[EpNum].Out.BufSize) {
+ Ep[EpNum].Out.dTDBufs = NULL;
+ continue;
+ }
+
+ Ep[EpNum].Out.dTDBufs = p;
+ p += EpCfg[EpNum].Out.BufSize * EpCfg[EpNum].Out.NumBufs;
+ }
+ }
+
+
+ /* Initialize the endpoint event handlers to NULL.
+ */
+ for (EpNum = 0; EpNum < DevCfgPtr->NumEndpoints; ++EpNum) {
+ Ep[EpNum].Out.HandlerFunc = NULL;
+ Ep[EpNum].In.HandlerFunc = NULL;
+ }
+}
+
+
+/*****************************************************************************/
+/**
+*
+* This function initializes the Queue Head List in memory.
+*
+* @param DevCfgPtr is a pointer to the XUsbPs DEVICE configuration
+* structure.
+*
+* @return None
+*
+* @note None.
+*
+******************************************************************************/
+static void XUsbPs_dQHInit(XUsbPs_DeviceConfig *DevCfgPtr)
+{
+ int EpNum;
+
+ XUsbPs_Endpoint *Ep;
+ XUsbPs_EpConfig *EpCfg;
+
+ /* Setup pointers for simpler access. */
+ Ep = DevCfgPtr->Ep;
+ EpCfg = DevCfgPtr->EpCfg;
+
+
+ /* Go through the list of Queue Head entries and:
+ *
+ * - Set Transfer Descriptor addresses
+ * - Set Maximum Packet Size
+ * - Disable Zero Length Termination (ZLT) for non-isochronous transfers
+ * - Enable Interrupt On Setup (IOS)
+ *
+ */
+ for (EpNum = 0; EpNum < DevCfgPtr->NumEndpoints; ++EpNum) {
+
+ /* OUT Queue Heads.*/
+ if (XUSBPS_EP_TYPE_NONE != EpCfg[EpNum].Out.Type) {
+ XUsbPs_WritedQH(Ep[EpNum].Out.dQH,
+ XUSBPS_dQHCPTR, Ep[EpNum].Out.dTDs);
+
+ /* For isochronous, ep max packet size translates to different
+ * values in queue head than other types.
+ * Also enable ZLT for isochronous.
+ */
+ if(XUSBPS_EP_TYPE_ISOCHRONOUS == EpCfg[EpNum].Out.Type) {
+ XUsbPs_dQHSetMaxPacketLenISO(Ep[EpNum].Out.dQH,
+ EpCfg[EpNum].Out.MaxPacketSize);
+ XUsbPs_dQHEnableZLT(Ep[EpNum].Out.dQH);
+ }else {
+ XUsbPs_dQHSetMaxPacketLen(Ep[EpNum].Out.dQH,
+ EpCfg[EpNum].Out.MaxPacketSize);
+ XUsbPs_dQHDisableZLT(Ep[EpNum].Out.dQH);
+ }
+
+ /* Only control OUT needs this */
+ if(XUSBPS_EP_TYPE_CONTROL == EpCfg[EpNum].Out.Type) {
+ XUsbPs_dQHSetIOS(Ep[EpNum].Out.dQH);
+ }
+
+ /* Set up the overlay next dTD pointer. */
+ XUsbPs_WritedQH(Ep[EpNum].Out.dQH,
+ XUSBPS_dQHdTDNLP, Ep[EpNum].Out.dTDs);
+
+ XUsbPs_dQHFlushCache(Ep[EpNum].Out.dQH);
+ }
+
+
+ /* IN Queue Heads. */
+ if (XUSBPS_EP_TYPE_NONE != EpCfg[EpNum].In.Type) {
+ XUsbPs_WritedQH(Ep[EpNum].In.dQH,
+ XUSBPS_dQHCPTR, Ep[EpNum].In.dTDs);
+
+
+ /* Isochronous ep packet size can be larger than 1024.*/
+ if(XUSBPS_EP_TYPE_ISOCHRONOUS == EpCfg[EpNum].In.Type) {
+ XUsbPs_dQHSetMaxPacketLenISO(Ep[EpNum].In.dQH,
+ EpCfg[EpNum].In.MaxPacketSize);
+ XUsbPs_dQHEnableZLT(Ep[EpNum].In.dQH);
+ }else {
+ XUsbPs_dQHSetMaxPacketLen(Ep[EpNum].In.dQH,
+ EpCfg[EpNum].In.MaxPacketSize);
+ XUsbPs_dQHDisableZLT(Ep[EpNum].In.dQH);
+ }
+
+ XUsbPs_dQHFlushCache(Ep[EpNum].In.dQH);
+ }
+ }
+}
+
+
+/*****************************************************************************/
+/**
+ *
+ * This function initializes the Transfer Descriptors lists in memory.
+ *
+ * @param DevCfgPtr is a pointer to the XUsbPs DEVICE configuration
+ * structure.
+ *
+ * @return
+ * - XST_SUCCESS: The operation completed successfully.
+ * - XST_FAILURE: An error occurred.
+ *
+ ******************************************************************************/
+static int XUsbPs_dTDInit(XUsbPs_DeviceConfig *DevCfgPtr)
+{
+ int EpNum;
+
+ XUsbPs_Endpoint *Ep;
+ XUsbPs_EpConfig *EpCfg;
+
+ /* Setup pointers for simpler access. */
+ Ep = DevCfgPtr->Ep;
+ EpCfg = DevCfgPtr->EpCfg;
+
+
+ /* Walk through the list of endpoints and initialize their Transfer
+ * Descriptors.
+ */
+ for (EpNum = 0; EpNum < DevCfgPtr->NumEndpoints; ++EpNum) {
+ int Td;
+ int NumdTD;
+
+ XUsbPs_EpOut *Out = &Ep[EpNum].Out;
+ XUsbPs_EpIn *In = &Ep[EpNum].In;
+
+
+ /* OUT Descriptors
+ * ===============
+ *
+ * + Set the next link pointer
+ * + Set the interrupt complete and the active bit
+ * + Attach the buffer to the dTD
+ */
+ if (XUSBPS_EP_TYPE_NONE != EpCfg[EpNum].Out.Type) {
+ NumdTD = EpCfg[EpNum].Out.NumBufs;
+ }
+ else {
+ NumdTD = 0;
+ }
+
+ for (Td = 0; Td < NumdTD; ++Td) {
+ int Status;
+
+ int NextTd = (Td + 1) % NumdTD;
+
+ XUsbPs_dTDInvalidateCache(&Out->dTDs[Td]);
+
+ /* Set NEXT link pointer. */
+ XUsbPs_WritedTD(&Out->dTDs[Td], XUSBPS_dTDNLP,
+ &Out->dTDs[NextTd]);
+
+ /* Set the OUT descriptor ACTIVE and enable the
+ * interrupt on complete.
+ */
+ XUsbPs_dTDSetActive(&Out->dTDs[Td]);
+ XUsbPs_dTDSetIOC(&Out->dTDs[Td]);
+
+
+ /* Set up the data buffer with the descriptor. If the
+ * buffer pointer is NULL it means that we do not need
+ * to attach a buffer to this descriptor.
+ */
+ if (NULL == Out->dTDBufs) {
+ XUsbPs_dTDFlushCache(&Out->dTDs[Td]);
+ continue;
+ }
+
+ Status = XUsbPs_dTDAttachBuffer(
+ &Out->dTDs[Td],
+ Out->dTDBufs +
+ (Td * EpCfg[EpNum].Out.BufSize),
+ EpCfg[EpNum].Out.BufSize);
+ if (XST_SUCCESS != Status) {
+ return XST_FAILURE;
+ }
+
+ XUsbPs_dTDFlushCache(&Out->dTDs[Td]);
+ }
+
+
+ /* IN Descriptors
+ * ==============
+ *
+ * + Set the next link pointer
+ * + Set the Terminate bit to mark it available
+ */
+ if (XUSBPS_EP_TYPE_NONE != EpCfg[EpNum].In.Type) {
+ NumdTD = EpCfg[EpNum].In.NumBufs;
+ }
+ else {
+ NumdTD = 0;
+ }
+
+ for (Td = 0; Td < NumdTD; ++Td) {
+ int NextTd = (Td + 1) % NumdTD;
+
+ XUsbPs_dTDInvalidateCache(&In->dTDs[Td]);
+
+ /* Set NEXT link pointer. */
+ XUsbPs_WritedTD(In->dTDs[Td], XUSBPS_dTDNLP,
+ In->dTDs[NextTd]);
+
+ /* Set the IN descriptor's TERMINATE bits. */
+ XUsbPs_dTDSetTerminate(In->dTDs[Td]);
+
+ XUsbPs_dTDFlushCache(&In->dTDs[Td]);
+ }
+ }
+
+ return XST_SUCCESS;
+}
+
+
+/*****************************************************************************/
+/**
+ *
+ * This function associates a buffer with a Transfer Descriptor. The function
+ * will take care of splitting the buffer into multiple 4kB aligned segments if
+ * the buffer happens to span one or more 4kB pages.
+ *
+ * @param dTDIndex is a pointer to the Transfer Descriptor
+ * @param BufferPtr is pointer to the buffer to link to the descriptor.
+ * @param BufferLen is the length of the buffer.
+ *
+ * @return
+ * - XST_SUCCESS: The operation completed successfully.
+ * - XST_FAILURE: An error occurred.
+ * - XST_USB_BUF_TOO_BIG: The provided buffer is bigger than tha
+ * maximum allowed buffer size (16k).
+ *
+ * @note
+ * Cache invalidation and flushing needs to be handler by the
+ * caller of this function.
+ *
+ ******************************************************************************/
+static int XUsbPs_dTDAttachBuffer(XUsbPs_dTD *dTDPtr,
+ const u8 *BufferPtr, u32 BufferLen)
+{
+ u32 BufAddr;
+ u32 BufEnd;
+ u32 PtrNum;
+
+ Xil_AssertNonvoid(dTDPtr != NULL);
+
+ /* Check if the buffer is smaller than 16kB. */
+ if (BufferLen > XUSBPS_dTD_BUF_MAX_SIZE) {
+ return XST_USB_BUF_TOO_BIG;
+ }
+
+ /* Get a u32 of the buffer pointer to avoid casting in the following
+ * logic operations.
+ */
+ BufAddr = (u32) BufferPtr;
+
+
+ /* Set the buffer pointer 0. Buffer pointer 0 can point to any location
+ * in memory. It does not need to be 4kB aligned. However, if the
+ * provided buffer spans one or more 4kB boundaries, we need to set up
+ * the subsequent buffer pointers which must be 4kB aligned.
+ */
+ XUsbPs_WritedTD(dTDPtr, XUSBPS_dTDBPTR(0), BufAddr);
+
+ /* Check if the buffer spans a 4kB boundary.
+ *
+ * Only do this check, if we are not sending a 0-length buffer.
+ */
+ if (BufferLen > 0) {
+ BufEnd = BufAddr + BufferLen -1;
+ PtrNum = 1;
+
+ while ((BufAddr & 0xFFFFF000) != (BufEnd & 0xFFFFF000)) {
+ /* The buffer spans at least one boundary, let's set
+ * the next buffer pointer and repeat the procedure
+ * until the end of the buffer and the pointer written
+ * are in the same 4kB page.
+ */
+ BufAddr = (BufAddr + 0x1000) & 0xFFFFF000;
+ XUsbPs_WritedTD(dTDPtr, XUSBPS_dTDBPTR(PtrNum),
+ BufAddr);
+ PtrNum++;
+ }
+ }
+
+ /* Set the length of the buffer. */
+ XUsbPs_dTDSetTransferLen(dTDPtr, BufferLen);
+
+
+ /* We remember the buffer pointer in the user data field (reserved
+ * field in the dTD). This makes it easier to reset the buffer pointer
+ * after a buffer has been received on the endpoint. The buffer pointer
+ * needs to be reset because the DMA engine modifies the buffer pointer
+ * while receiving.
+ */
+ XUsbPs_WritedTD(dTDPtr, XUSBPS_dTDUSERDATA, BufferPtr);
+
+ return XST_SUCCESS;
+}
+
+
+/*****************************************************************************/
+/**
+ * This function set the Max PacketLen for the queue head for isochronous EP.
+ *
+ * If the max packet length is greater than XUSBPS_MAX_PACKET_SIZE, then
+ * Mult bits are set to reflect that.
+ *
+ * @param dQHPtr is a pointer to the dQH element.
+ * @param Len is the Length to be set.
+ *
+ ******************************************************************************/
+static void XUsbPs_dQHSetMaxPacketLenISO(XUsbPs_dQH *dQHPtr, u32 Len)
+{
+ u32 Mult = (Len & ENDPOINT_MAXP_MULT_MASK) >> ENDPOINT_MAXP_MULT_SHIFT;
+ u32 MaxPktSize = (Mult > 1) ? ENDPOINT_MAXP_LENGTH : Len;
+
+ if (MaxPktSize > XUSBPS_MAX_PACKET_SIZE) {
+ return;
+ }
+
+ if (Mult > 3) {
+ return;
+ }
+
+ /* Set Max packet size */
+ XUsbPs_WritedQH(dQHPtr, XUSBPS_dQHCFG,
+ (XUsbPs_ReaddQH(dQHPtr, XUSBPS_dQHCFG) &
+ ~XUSBPS_dQHCFG_MPL_MASK) |
+ (MaxPktSize << XUSBPS_dQHCFG_MPL_SHIFT));
+
+ /* Set Mult to tell hardware how many transactions in each microframe */
+ XUsbPs_WritedQH(dQHPtr, XUSBPS_dQHCFG,
+ (XUsbPs_ReaddQH(dQHPtr, XUSBPS_dQHCFG) &
+ ~XUSBPS_dQHCFG_MULT_MASK) |
+ (Mult << XUSBPS_dQHCFG_MULT_SHIFT));
+
+}
+
+/*****************************************************************************/
+/**
+* This function reconfigures one Ep corresponding to host's request of setting
+* alternate interface. The endpoint has been disabled before this call.
+*
+* Both QH and dTDs are updated for the new configuration.
+*
+* @param InstancePtr is a pointer to the XUsbPs instance of the
+* controller.
+* @param CfgPtr
+* Pointer to the updated XUsbPs DEVICE configuration structure.
+*
+* @param EpNum
+* The endpoint to be reconfigured.
+*
+* @param NewDirection
+* The new transfer direction the endpoint.
+*
+* @param DirectionChanged
+* A boolean value indicate whether the transfer direction has changed.
+*
+* @return
+* XST_SUCCESS upon success, XST_FAILURE otherwise.
+*
+******************************************************************************/
+int XUsbPs_ReconfigureEp(XUsbPs *InstancePtr, XUsbPs_DeviceConfig *CfgPtr,
+ int EpNum, unsigned short NewDirection,
+ int DirectionChanged) {
+
+ int Status = XST_SUCCESS;
+ XUsbPs_Endpoint *Ep;
+ XUsbPs_EpConfig *EpCfg;
+
+ Xil_AssertNonvoid(InstancePtr != NULL);
+ Xil_AssertNonvoid(CfgPtr != NULL);
+
+ Ep = CfgPtr->Ep;
+ EpCfg = CfgPtr->EpCfg;
+
+ /* If transfer direction changes, dTDs has to be reset
+ * Number of buffers are preset and should not to be changed.
+ */
+ if(DirectionChanged) {
+ if(NewDirection == XUSBPS_EP_DIRECTION_OUT) {
+ u8 *p;
+
+ /* Swap the pointer to the dTDs.
+ */
+ Ep[EpNum].Out.dTDs = Ep[EpNum].In.dTDs;
+ p = (u8 *)(Ep[EpNum].Out.dTDs + XUSBPS_dTD_ALIGN * EpCfg[EpNum].Out.NumBufs);
+
+ /* Set the OUT buffer if buffer size is not zero
+ */
+ if(EpCfg[EpNum].Out.BufSize > 0) {
+ Ep[EpNum].Out.dTDBufs = p;
+ }
+ } else if(NewDirection == XUSBPS_EP_DIRECTION_IN) {
+ Ep[EpNum].In.dTDs = Ep[EpNum].Out.dTDs;
+ }
+ }
+
+ /* Reset dTD progress tracking pointers
+ */
+ if(NewDirection == XUSBPS_EP_DIRECTION_IN) {
+ Ep[EpNum].In.dTDHead = Ep[EpNum].In.dTDTail = Ep[EpNum].In.dTDs;
+ } else if(NewDirection == XUSBPS_EP_DIRECTION_OUT) {
+ Ep[EpNum].Out.dTDCurr = Ep[EpNum].Out.dTDs;
+ }
+
+ /* Reinitialize information in QH
+ */
+ XUsbPs_dQHReinitEp(CfgPtr, EpNum, NewDirection);
+
+ /* Reinitialize the dTD linked list, and flush the cache
+ */
+ Status = XUsbPs_dTDReinitEp(CfgPtr, EpNum, NewDirection);
+ if(Status != XST_SUCCESS) {
+ return Status;
+ }
+
+ return XST_SUCCESS;
+}
+
+
+/*****************************************************************************/
+/**
+ * This function re-initializes the Queue Head List in memory.
+ * The endpoint 1 has been disabled before this call.
+ *
+ * @param DevCfgPtr
+ * Pointer to the updated XUsbPs DEVICE configuration structure.
+ *
+ * @param EpNum
+ * The endpoint to be reconfigured.
+ *
+ * @param NewDirection
+ * The new transfer direction of endpoint 1
+ *
+ * @return none
+ *
+ ******************************************************************************/
+static void XUsbPs_dQHReinitEp(XUsbPs_DeviceConfig *DevCfgPtr,
+int EpNum, unsigned short NewDirection)
+{
+ XUsbPs_Endpoint *Ep;
+ XUsbPs_EpConfig *EpCfg;
+
+ /* Setup pointers for simpler access.
+ */
+ Ep = DevCfgPtr->Ep;
+ EpCfg = DevCfgPtr->EpCfg;
+
+
+ /* Go through the list of Queue Head entries and:
+ *
+ * - Set Transfer Descriptor addresses
+ * - Set Maximum Packet Size
+ * - Disable Zero Length Termination (ZLT) for non-isochronous transfers
+ * - Enable Interrupt On Setup (IOS)
+ *
+ */
+ if(NewDirection == XUSBPS_EP_DIRECTION_OUT) {
+ /* OUT Queue Heads.
+ */
+ XUsbPs_WritedQH(Ep[EpNum].Out.dQH,
+ XUSBPS_dQHCPTR, Ep[EpNum].Out.dTDs);
+
+ /* For isochronous, ep max packet size translates to different
+ * values in queue head than other types.
+ * Also enable ZLT for isochronous.
+ */
+ if(XUSBPS_EP_TYPE_ISOCHRONOUS == EpCfg[EpNum].Out.Type) {
+ XUsbPs_dQHSetMaxPacketLenISO(Ep[EpNum].Out.dQH,
+ EpCfg[EpNum].Out.MaxPacketSize);
+ XUsbPs_dQHEnableZLT(Ep[EpNum].Out.dQH);
+ }else {
+ XUsbPs_dQHSetMaxPacketLen(Ep[EpNum].Out.dQH,
+ EpCfg[EpNum].Out.MaxPacketSize);
+ XUsbPs_dQHDisableZLT(Ep[EpNum].Out.dQH);
+ }
+
+ XUsbPs_dQHSetIOS(Ep[EpNum].Out.dQH);
+
+ /* Set up the overlay next dTD pointer.
+ */
+ XUsbPs_WritedQH(Ep[EpNum].Out.dQH,
+ XUSBPS_dQHdTDNLP, Ep[EpNum].Out.dTDs);
+
+ XUsbPs_dQHFlushCache(Ep[EpNum].Out.dQH);
+
+ } else if(NewDirection == XUSBPS_EP_DIRECTION_IN) {
+
+ /* IN Queue Heads.
+ */
+ XUsbPs_WritedQH(Ep[EpNum].In.dQH,
+ XUSBPS_dQHCPTR, Ep[EpNum].In.dTDs);
+
+ /* Isochronous ep packet size can be larger than 1024. */
+ if(XUSBPS_EP_TYPE_ISOCHRONOUS == EpCfg[EpNum].In.Type) {
+ XUsbPs_dQHSetMaxPacketLenISO(Ep[EpNum].In.dQH,
+ EpCfg[EpNum].In.MaxPacketSize);
+ XUsbPs_dQHEnableZLT(Ep[EpNum].In.dQH);
+ }else {
+ XUsbPs_dQHSetMaxPacketLen(Ep[EpNum].In.dQH,
+ EpCfg[EpNum].In.MaxPacketSize);
+ XUsbPs_dQHDisableZLT(Ep[EpNum].In.dQH);
+ }
+
+ XUsbPs_dQHSetIOS(Ep[EpNum].In.dQH);
+
+ XUsbPs_dQHFlushCache(Ep[EpNum].In.dQH);
+ }
+
+}
+
+/*****************************************************************************/
+/**
+ *
+ * This function re-initializes the Transfer Descriptors lists in memory.
+ * The endpoint has been disabled before the call. The transfer descriptors
+ * list pointer has been initialized too.
+ *
+ * @param DevCfgPtr
+ * Pointer to the XUsbPs DEVICE configuration structure.
+ *
+ * @param EpNum
+ * The endpoint to be reconfigured.
+ *
+ * @param NewDirection
+ * The new transfer direction of endpoint 1
+ *
+ * @return
+ * - XST_SUCCESS: The operation completed successfully.
+ * - XST_FAILURE: An error occurred.
+ *
+ ******************************************************************************/
+static int XUsbPs_dTDReinitEp(XUsbPs_DeviceConfig *DevCfgPtr,
+int EpNum, unsigned short NewDirection)
+{
+ XUsbPs_Endpoint *Ep;
+ XUsbPs_EpConfig *EpCfg;
+ int Td;
+ int NumdTD;
+
+
+ /* Setup pointers for simpler access.
+ */
+ Ep = DevCfgPtr->Ep;
+ EpCfg = DevCfgPtr->EpCfg;
+
+
+ if(NewDirection == XUSBPS_EP_DIRECTION_OUT) {
+ XUsbPs_EpOut *Out = &Ep[EpNum].Out;
+
+ /* OUT Descriptors
+ * ===============
+ *
+ * + Set the next link pointer
+ * + Set the interrupt complete and the active bit
+ * + Attach the buffer to the dTD
+ */
+ NumdTD = EpCfg[EpNum].Out.NumBufs;
+
+ for (Td = 0; Td < NumdTD; ++Td) {
+ int Status;
+
+ int NextTd = (Td + 1) % NumdTD;
+
+ XUsbPs_dTDInvalidateCache(&Out->dTDs[Td]);
+
+ /* Set NEXT link pointer.
+ */
+ XUsbPs_WritedTD(&Out->dTDs[Td], XUSBPS_dTDNLP,
+ &Out->dTDs[NextTd]);
+
+ /* Set the OUT descriptor ACTIVE and enable the
+ * interrupt on complete.
+ */
+ XUsbPs_dTDSetActive(&Out->dTDs[Td]);
+ XUsbPs_dTDSetIOC(&Out->dTDs[Td]);
+
+ /* Set up the data buffer with the descriptor. If the
+ * buffer pointer is NULL it means that we do not need
+ * to attach a buffer to this descriptor.
+ */
+ if (Out->dTDBufs != NULL) {
+
+ Status = XUsbPs_dTDAttachBuffer(
+ &Out->dTDs[Td],
+ Out->dTDBufs +
+ (Td * EpCfg[EpNum].Out.BufSize),
+ EpCfg[EpNum].Out.BufSize);
+ if (Status != XST_SUCCESS) {
+ return XST_FAILURE;
+ }
+ }
+ XUsbPs_dTDFlushCache(&Out->dTDs[Td]);
+ }
+ } else if(NewDirection == XUSBPS_EP_DIRECTION_IN) {
+ XUsbPs_EpIn *In = &Ep[EpNum].In;
+
+ /* IN Descriptors
+ * ==============
+ *
+ * + Set the next link pointer
+ * + Set the Terminate bit to mark it available
+ */
+ NumdTD = EpCfg[EpNum].In.NumBufs;
+
+ for (Td = 0; Td < NumdTD; ++Td) {
+ int NextTd = (Td + 1) % NumdTD;
+
+ XUsbPs_dTDInvalidateCache(&In->dTDs[Td]);
+
+ /* Set NEXT link pointer.
+ */
+ XUsbPs_WritedTD(&In->dTDs[Td], XUSBPS_dTDNLP,
+ &In->dTDs[NextTd]);
+
+ /* Set the IN descriptor's TERMINATE bits.
+ */
+ XUsbPs_dTDSetTerminate(&In->dTDs[Td]);
+
+ XUsbPs_dTDFlushCache(&In->dTDs[Td]);
+ }
+ }
+
+ return XST_SUCCESS;
+}
+
+/** @} */
diff --git a/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/usbps_v2_4/src/xusbps_endpoint.h b/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/usbps_v2_4/src/xusbps_endpoint.h
new file mode 100644
index 0000000..0455b70
--- /dev/null
+++ b/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/usbps_v2_4/src/xusbps_endpoint.h
@@ -0,0 +1,509 @@
+/******************************************************************************
+*
+* Copyright (C) 2010 - 2015 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+* THE SOFTWARE.
+*
+*
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+ *
+ * @file xusbps_endpoint.h
+* @addtogroup usbps_v2_4
+* @{
+ *
+ * This is an internal file containung the definitions for endpoints. It is
+ * included by the xusbps_endpoint.c which is implementing the endpoint
+ * functions and by xusbps_intr.c.
+ *
+ * <pre>
+ * MODIFICATION HISTORY:
+ *
+ * Ver Who Date Changes
+ * ----- ---- -------- --------------------------------------------------------
+ * 1.00a wgr 10/10/10 First release
+ * </pre>
+ *
+ ******************************************************************************/
+#ifndef XUSBPS_ENDPOINT_H
+#define XUSBPS_ENDPOINT_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/***************************** Include Files *********************************/
+
+#include "xil_cache.h"
+#include "xusbps.h"
+#include "xil_types.h"
+
+/**************************** Type Definitions *******************************/
+
+/************************** Constant Definitions *****************************/
+
+
+/**
+ * Endpoint Device Transfer Descriptor
+ *
+ * The dTD describes to the device controller the location and quantity of data
+ * to be sent/received for given transfer. The driver does not attempt to
+ * modify any field in an active dTD except the Next Link Pointer.
+ */
+#define XUSBPS_dTDNLP 0x00 /**< Pointer to the next descriptor */
+#define XUSBPS_dTDTOKEN 0x04 /**< Descriptor Token */
+#define XUSBPS_dTDBPTR0 0x08 /**< Buffer Pointer 0 */
+#define XUSBPS_dTDBPTR1 0x0C /**< Buffer Pointer 1 */
+#define XUSBPS_dTDBPTR2 0x10 /**< Buffer Pointer 2 */
+#define XUSBPS_dTDBPTR3 0x14 /**< Buffer Pointer 3 */
+#define XUSBPS_dTDBPTR4 0x18 /**< Buffer Pointer 4 */
+#define XUSBPS_dTDBPTR(n) (XUSBPS_dTDBPTR0 + (n) * 0x04)
+#define XUSBPS_dTDRSRVD 0x1C /**< Reserved field */
+
+/* We use the reserved field in the dTD to store user data. */
+#define XUSBPS_dTDUSERDATA XUSBPS_dTDRSRVD /**< Reserved field */
+
+
+/** @name dTD Next Link Pointer (dTDNLP) bit positions.
+ * @{
+ */
+#define XUSBPS_dTDNLP_T_MASK 0x00000001
+ /**< USB dTD Next Link Pointer Terminate Bit */
+#define XUSBPS_dTDNLP_ADDR_MASK 0xFFFFFFE0
+ /**< USB dTD Next Link Pointer Address [31:5] */
+/* @} */
+
+
+/** @name dTD Token (dTDTOKEN) bit positions.
+ * @{
+ */
+#define XUSBPS_dTDTOKEN_XERR_MASK 0x00000008 /**< dTD Transaction Error */
+#define XUSBPS_dTDTOKEN_BUFERR_MASK 0x00000020 /**< dTD Data Buffer Error */
+#define XUSBPS_dTDTOKEN_HALT_MASK 0x00000040 /**< dTD Halted Flag */
+#define XUSBPS_dTDTOKEN_ACTIVE_MASK 0x00000080 /**< dTD Active Bit */
+#define XUSBPS_dTDTOKEN_MULTO_MASK 0x00000C00 /**< Multiplier Override Field [1:0] */
+#define XUSBPS_dTDTOKEN_IOC_MASK 0x00008000 /**< Interrupt on Complete Bit */
+#define XUSBPS_dTDTOKEN_LEN_MASK 0x7FFF0000 /**< Transfer Length Field */
+/* @} */
+
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/*****************************************************************************/
+/**
+ *
+ * IMPORTANT NOTE:
+ * ===============
+ *
+ * Many of the following macros modify Device Queue Head (dQH) data structures
+ * and Device Transfer Descriptor (dTD) data structures. Those structures can
+ * potentially reside in CACHED memory. Therefore, it's the callers
+ * responsibility to ensure cache coherency by using provided
+ *
+ * XUsbPs_dQHInvalidateCache()
+ * XUsbPs_dQHFlushCache()
+ * XUsbPs_dTDInvalidateCache()
+ * XUsbPs_dTDFlushCache()
+ *
+ * function calls.
+ *
+ ******************************************************************************/
+#define XUsbPs_dTDInvalidateCache(dTDPtr) \
+ Xil_DCacheInvalidateRange((unsigned int)dTDPtr, sizeof(XUsbPs_dTD))
+
+#define XUsbPs_dTDFlushCache(dTDPtr) \
+ Xil_DCacheFlushRange((unsigned int)dTDPtr, sizeof(XUsbPs_dTD))
+
+#define XUsbPs_dQHInvalidateCache(dQHPtr) \
+ Xil_DCacheInvalidateRange((unsigned int)dQHPtr, sizeof(XUsbPs_dQH))
+
+#define XUsbPs_dQHFlushCache(dQHPtr) \
+ Xil_DCacheFlushRange((unsigned int)dQHPtr, sizeof(XUsbPs_dQH))
+
+/*****************************************************************************/
+/**
+ *
+ * This macro sets the Transfer Length for the given Transfer Descriptor.
+ *
+ * @param dTDPtr is pointer to the dTD element.
+ * @param Len is the length to be set. Range: 0..16384
+ *
+ * @note C-style signature:
+ * void XUsbPs_dTDSetTransferLen(u32 dTDPtr, u32 Len)
+ *
+ ******************************************************************************/
+#define XUsbPs_dTDSetTransferLen(dTDPtr, Len) \
+ XUsbPs_WritedTD(dTDPtr, XUSBPS_dTDTOKEN, \
+ (XUsbPs_ReaddTD(dTDPtr, XUSBPS_dTDTOKEN) & \
+ ~XUSBPS_dTDTOKEN_LEN_MASK) | ((Len) << 16))
+
+
+/*****************************************************************************/
+/**
+ *
+ * This macro gets the Next Link pointer of the given Transfer Descriptor.
+ *
+ * @param dTDPtr is pointer to the dTD element.
+ *
+ * @return TransferLength field of the descriptor.
+ *
+ * @note C-style signature:
+ * u32 XUsbPs_dTDGetTransferLen(u32 dTDPtr)
+ *
+ ******************************************************************************/
+#define XUsbPs_dTDGetNLP(dTDPtr) \
+ (XUsbPs_dTD *) ((XUsbPs_ReaddTD(dTDPtr, XUSBPS_dTDNLP)\
+ & XUSBPS_dTDNLP_ADDR_MASK))
+
+
+/*****************************************************************************/
+/**
+ *
+ * This macro sets the Next Link pointer of the given Transfer Descriptor.
+ *
+ * @param dTDPtr is a pointer to the dTD element.
+ * @param NLP is the Next Link Pointer
+ *
+ * @note C-style signature:
+ * void XUsbPs_dTDSetTransferLen(u32 dTDPtr, u32 Len)
+ *
+ ******************************************************************************/
+#define XUsbPs_dTDSetNLP(dTDPtr, NLP) \
+ XUsbPs_WritedTD(dTDPtr, XUSBPS_dTDNLP, \
+ (XUsbPs_ReaddTD(dTDPtr, XUSBPS_dTDNLP) & \
+ ~XUSBPS_dTDNLP_ADDR_MASK) | \
+ ((NLP) & XUSBPS_dTDNLP_ADDR_MASK))
+
+
+/*****************************************************************************/
+/**
+ *
+ * This macro gets the Transfer Length for the given Transfer Descriptor.
+ *
+ * @param dTDPtr is a pointer to the dTD element.
+ *
+ * @return TransferLength field of the descriptor.
+ *
+ * @note C-style signature:
+ * u32 XUsbPs_dTDGetTransferLen(u32 dTDPtr)
+ *
+ ******************************************************************************/
+#define XUsbPs_dTDGetTransferLen(dTDPtr) \
+ (u32) ((XUsbPs_ReaddTD(dTDPtr, XUSBPS_dTDTOKEN) \
+ & XUSBPS_dTDTOKEN_LEN_MASK) >> 16)
+
+
+/*****************************************************************************/
+/**
+ *
+ * This macro sets the Interrupt On Complete (IOC) bit for the given Transfer
+ * Descriptor.
+ *
+ * @param dTDPtr is a pointer to the dTD element.
+ *
+ * @note C-style signature:
+ * void XUsbPs_dTDSetIOC(u32 dTDPtr)
+ *
+ ******************************************************************************/
+#define XUsbPs_dTDSetIOC(dTDPtr) \
+ XUsbPs_WritedTD(dTDPtr, XUSBPS_dTDTOKEN, \
+ XUsbPs_ReaddTD(dTDPtr, XUSBPS_dTDTOKEN) | \
+ XUSBPS_dTDTOKEN_IOC_MASK)
+
+
+/*****************************************************************************/
+/**
+ *
+ * This macro sets the Terminate bit for the given Transfer Descriptor.
+ *
+ * @param dTDPtr is a pointer to the dTD element.
+ *
+ * @note C-style signature:
+ * void XUsbPs_dTDSetTerminate(u32 dTDPtr)
+ *
+ ******************************************************************************/
+#define XUsbPs_dTDSetTerminate(dTDPtr) \
+ XUsbPs_WritedTD(dTDPtr, XUSBPS_dTDNLP, \
+ XUsbPs_ReaddTD(dTDPtr, XUSBPS_dTDNLP) | \
+ XUSBPS_dTDNLP_T_MASK)
+
+
+/*****************************************************************************/
+/**
+ *
+ * This macro clears the Terminate bit for the given Transfer Descriptor.
+ *
+ * @param dTDPtr is a pointer to the dTD element.
+ *
+ * @note C-style signature:
+ * void XUsbPs_dTDClrTerminate(u32 dTDPtr)
+ *
+ ******************************************************************************/
+#define XUsbPs_dTDClrTerminate(dTDPtr) \
+ XUsbPs_WritedTD(dTDPtr, XUSBPS_dTDNLP, \
+ XUsbPs_ReaddTD(dTDPtr, XUSBPS_dTDNLP) & \
+ ~XUSBPS_dTDNLP_T_MASK)
+
+
+/*****************************************************************************/
+/**
+ *
+ * This macro checks if the given descriptor is active.
+ *
+ * @param dTDPtr is a pointer to the dTD element.
+ *
+ * @return
+ * - TRUE: The buffer is active.
+ * - FALSE: The buffer is not active.
+ *
+ * @note C-style signature:
+ * int XUsbPs_dTDIsActive(u32 dTDPtr)
+ *
+ ******************************************************************************/
+#define XUsbPs_dTDIsActive(dTDPtr) \
+ ((XUsbPs_ReaddTD(dTDPtr, XUSBPS_dTDTOKEN) & \
+ XUSBPS_dTDTOKEN_ACTIVE_MASK) ? TRUE : FALSE)
+
+
+/*****************************************************************************/
+/**
+ *
+ * This macro sets the Active bit for the given Transfer Descriptor.
+ *
+ * @param dTDPtr is a pointer to the dTD element.
+ *
+ * @note C-style signature:
+ * void XUsbPs_dTDSetActive(u32 dTDPtr)
+ *
+ ******************************************************************************/
+#define XUsbPs_dTDSetActive(dTDPtr) \
+ XUsbPs_WritedTD(dTDPtr, XUSBPS_dTDTOKEN, \
+ XUsbPs_ReaddTD(dTDPtr, XUSBPS_dTDTOKEN) | \
+ XUSBPS_dTDTOKEN_ACTIVE_MASK)
+
+
+/*****************************************************************************/
+/**
+ *
+ * This macro reads the content of a field in a Transfer Descriptor.
+ *
+ * @param dTDPtr is a pointer to the dTD element.
+ * @param Id is the field ID inside the dTD element to read.
+ *
+ * @note C-style signature:
+ * u32 XUsbPs_ReaddTD(u32 dTDPtr, u32 Id)
+ *
+ ******************************************************************************/
+#define XUsbPs_ReaddTD(dTDPtr, Id) (*(u32 *)((u32)(dTDPtr) + (u32)(Id)))
+
+/*****************************************************************************/
+/**
+ *
+ * This macro writes a value to a field in a Transfer Descriptor.
+ *
+ * @param dTDPtr is pointer to the dTD element.
+ * @param Id is the field ID inside the dTD element to read.
+ * @param Val is the value to write to the field.
+ *
+ * @note C-style signature:
+ * u32 XUsbPs_WritedTD(u32 dTDPtr, u32 Id, u32 Val)
+ *
+ ******************************************************************************/
+#define XUsbPs_WritedTD(dTDPtr, Id, Val) \
+ (*(u32 *) ((u32)(dTDPtr) + (u32)(Id)) = (u32)(Val))
+
+
+/******************************************************************************/
+/**
+ * Endpoint Device Queue Head
+ *
+ * Device queue heads are arranged in an array in a continuous area of memory
+ * pointed to by the ENDPOINTLISTADDR pointer. The device controller will index
+ * into this array based upon the endpoint number received from the USB bus.
+ * All information necessary to respond to transactions for all primed
+ * transfers is contained in this list so the Device Controller can readily
+ * respond to incoming requests without having to traverse a linked list.
+ *
+ * The device Endpoint Queue Head (dQH) is where all transfers are managed. The
+ * dQH is a 48-byte data structure, but must be aligned on a 64-byte boundary.
+ * During priming of an endpoint, the dTD (device transfer descriptor) is
+ * copied into the overlay area of the dQH, which starts at the nextTD pointer
+ * DWord and continues through the end of the buffer pointers DWords. After a
+ * transfer is complete, the dTD status DWord is updated in the dTD pointed to
+ * by the currentTD pointer. While a packet is in progress, the overlay area of
+ * the dQH is used as a staging area for the dTD so that the Device Controller
+ * can access needed information with little minimal latency.
+ *
+ * @note
+ * Software must ensure that no interface data structure reachable by the
+ * Device Controller spans a 4K-page boundary. The first element of the
+ * Endpoint Queue Head List must be aligned on a 4K boundary.
+ */
+#define XUSBPS_dQHCFG 0x00 /**< dQH Configuration */
+#define XUSBPS_dQHCPTR 0x04 /**< dQH Current dTD Pointer */
+#define XUSBPS_dQHdTDNLP 0x08 /**< dTD Next Link Ptr in dQH
+ overlay */
+#define XUSBPS_dQHdTDTOKEN 0x0C /**< dTD Token in dQH overlay */
+#define XUSBPS_dQHSUB0 0x28 /**< USB dQH Setup Buffer 0 */
+#define XUSBPS_dQHSUB1 0x2C /**< USB dQH Setup Buffer 1 */
+
+
+/** @name dQH Configuration (dQHCFG) bit positions.
+ * @{
+ */
+#define XUSBPS_dQHCFG_IOS_MASK 0x00008000
+ /**< USB dQH Interrupt on Setup Bit */
+#define XUSBPS_dQHCFG_MPL_MASK 0x07FF0000
+ /**< USB dQH Maximum Packet Length
+ * Field [10:0] */
+#define XUSBPS_dQHCFG_MPL_SHIFT 16
+#define XUSBPS_dQHCFG_ZLT_MASK 0x20000000
+ /**< USB dQH Zero Length Termination
+ * Select Bit */
+#define XUSBPS_dQHCFG_MULT_MASK 0xC0000000
+ /* USB dQH Number of Transactions Field
+ * [1:0] */
+#define XUSBPS_dQHCFG_MULT_SHIFT 30
+/* @} */
+
+
+/*****************************************************************************/
+/**
+ *
+ * This macro sets the Maximum Packet Length field of the give Queue Head.
+ *
+ * @param dQHPtr is a pointer to the dQH element.
+ * @param Len is the length to be set.
+ *
+ * @note C-style signature:
+ * void XUsbPs_dQHSetMaxPacketLen(u32 dQHPtr, u32 Len)
+ *
+ ******************************************************************************/
+#define XUsbPs_dQHSetMaxPacketLen(dQHPtr, Len) \
+ XUsbPs_WritedQH(dQHPtr, XUSBPS_dQHCFG, \
+ (XUsbPs_ReaddQH(dQHPtr, XUSBPS_dQHCFG) & \
+ ~XUSBPS_dQHCFG_MPL_MASK) | ((Len) << 16))
+
+/*****************************************************************************/
+/**
+ *
+ * This macro sets the Interrupt On Setup (IOS) bit for an endpoint.
+ *
+ * @param dQHPtr is a pointer to the dQH element.
+ *
+ * @note C-style signature:
+ * void XUsbPs_dQHSetIOS(u32 dQHPtr)
+ *
+ ******************************************************************************/
+#define XUsbPs_dQHSetIOS(dQHPtr) \
+ XUsbPs_WritedQH(dQHPtr, XUSBPS_dQHCFG, \
+ XUsbPs_ReaddQH(dQHPtr, XUSBPS_dQHCFG) | \
+ XUSBPS_dQHCFG_IOS_MASK)
+
+/*****************************************************************************/
+/**
+ *
+ * This macro clears the Interrupt On Setup (IOS) bit for an endpoint.
+ *
+ * @param dQHPtr is a pointer to the dQH element.
+ *
+ * @note C-style signature:
+ * void XUsbPs_dQHClrIOS(u32 dQHPtr)
+ *
+ ******************************************************************************/
+#define XUsbPs_dQHClrIOS(dQHPtr) \
+ XUsbPs_WritedQH(dQHPtr, XUSBPS_dQHCFG, \
+ XUsbPs_ReaddQH(dQHPtr, XUSBPS_dQHCFG) & \
+ ~XUSBPS_dQHCFG_IOS_MASK)
+
+/*****************************************************************************/
+/**
+ *
+ * This macro enables Zero Length Termination for the endpoint.
+ *
+ * @param dQHPtr is a pointer to the dQH element.
+ *
+ * @note C-style signature:
+ * void XUsbPs_dQHEnableZLT(u32 dQHPtr)
+ *
+ *
+ ******************************************************************************/
+#define XUsbPs_dQHEnableZLT(dQHPtr) \
+ XUsbPs_WritedQH(dQHPtr, XUSBPS_dQHCFG, \
+ XUsbPs_ReaddQH(dQHPtr, XUSBPS_dQHCFG) & \
+ ~XUSBPS_dQHCFG_ZLT_MASK)
+
+
+/*****************************************************************************/
+/**
+ *
+ * This macro disables Zero Length Termination for the endpoint.
+ *
+ * @param dQHPtr is a pointer to the dQH element.
+ *
+ * @note C-style signature:
+ * void XUsbPs_dQHDisableZLT(u32 dQHPtr)
+ *
+ *
+ ******************************************************************************/
+#define XUsbPs_dQHDisableZLT(dQHPtr) \
+ XUsbPs_WritedQH(dQHPtr, XUSBPS_dQHCFG, \
+ XUsbPs_ReaddQH(dQHPtr, XUSBPS_dQHCFG) | \
+ XUSBPS_dQHCFG_ZLT_MASK)
+
+/*****************************************************************************/
+/**
+ *
+ * This macro reads the content of a field in a Queue Head.
+ *
+ * @param dQHPtr is a pointer to the dQH element.
+ * @param Id is the Field ID inside the dQH element to read.
+ *
+ * @note C-style signature:
+ * u32 XUsbPs_ReaddQH(u32 dQHPtr, u32 Id)
+ *
+ ******************************************************************************/
+#define XUsbPs_ReaddQH(dQHPtr, Id) (*(u32 *)((u32)(dQHPtr) + (u32) (Id)))
+
+/*****************************************************************************/
+/**
+ *
+ * This macro writes a value to a field in a Queue Head.
+ *
+ * @param dQHPtr is a pointer to the dQH element.
+ * @param Id is the Field ID inside the dQH element to read.
+ * @param Val is the Value to write to the field.
+ *
+ * @note C-style signature:
+ * u32 XUsbPs_WritedQH(u32 dQHPtr, u32 Id, u32 Val)
+ *
+ ******************************************************************************/
+#define XUsbPs_WritedQH(dQHPtr, Id, Val) \
+ (*(u32 *) ((u32)(dQHPtr) + (u32)(Id)) = (u32)(Val))
+
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* XUSBPS_ENDPOINT_H */
+/** @} */
diff --git a/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/usbps_v2_4/src/xusbps_g.c b/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/usbps_v2_4/src/xusbps_g.c
new file mode 100644
index 0000000..7e1c40d
--- /dev/null
+++ b/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/usbps_v2_4/src/xusbps_g.c
@@ -0,0 +1,47 @@
+
+/*******************************************************************
+*
+* CAUTION: This file is automatically generated by HSI.
+* Version: 2019.2
+* DO NOT EDIT.
+*
+* Copyright (C) 2010-2021 Xilinx, Inc. All Rights Reserved.*
+*Permission is hereby granted, free of charge, to any person obtaining a copy
+*of this software and associated documentation files (the Software), to deal
+*in the Software without restriction, including without limitation the rights
+*to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+*copies of the Software, and to permit persons to whom the Software is
+*furnished to do so, subject to the following conditions:
+*
+*The above copyright notice and this permission notice shall be included in
+*all copies or substantial portions of the Software.
+*
+*THE SOFTWARE IS PROVIDED AS IS, WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+*IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+*FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+*THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+*WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT
+*OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+*
+
+*
+* Description: Driver configuration
+*
+*******************************************************************/
+
+#include "xparameters.h"
+#include "xusbps.h"
+
+/*
+* The configuration table for devices
+*/
+
+XUsbPs_Config XUsbPs_ConfigTable[XPAR_XUSBPS_NUM_INSTANCES] =
+{
+ {
+ XPAR_PS7_USB_0_DEVICE_ID,
+ XPAR_PS7_USB_0_BASEADDR
+ }
+};
+
+
diff --git a/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/usbps_v2_4/src/xusbps_hw.c b/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/usbps_v2_4/src/xusbps_hw.c
new file mode 100644
index 0000000..7639e3e
--- /dev/null
+++ b/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/usbps_v2_4/src/xusbps_hw.c
@@ -0,0 +1,116 @@
+/******************************************************************************
+*
+* Copyright (C) 2010 - 2015 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+* THE SOFTWARE.
+*
+*
+*
+******************************************************************************/
+/****************************************************************************/
+/**
+ *
+ * @file xusbps_hw.c
+* @addtogroup usbps_v2_4
+* @{
+ *
+ * The implementation of the XUsbPs interface reset functionality
+ *
+ * <pre>
+ * MODIFICATION HISTORY:
+ *
+ * Ver Who Date Changes
+ * ----- ---- -------- -----------------------------------------------
+ * 1.05a kpc 10/10/10 first version
+ * </pre>
+ *
+ *****************************************************************************/
+
+/***************************** Include Files ********************************/
+
+#include "xstatus.h"
+#include "xusbps.h"
+#include "xparameters.h"
+
+
+/************************** Constant Definitions ****************************/
+#define XUSBPS_RESET_TIMEOUT 0xFFFFF
+/**************************** Type Definitions ******************************/
+
+/***************** Macros (Inline Functions) Definitions ********************/
+
+/************************** Variable Definitions ****************************/
+
+
+/************************** Function Prototypes *****************************/
+
+
+/*****************************************************************************/
+/**
+* This function perform the reset sequence to the given usbps interface by
+* configuring the appropriate control bits in the usbps specific registers.
+* the usbps reset sequence involves the below steps
+* Disable the interrupts
+* Clear the status registers
+* Apply the reset command and wait for reset complete status
+* Update the relevant control registers with reset values
+* @param BaseAddress of the interface
+*
+* @return N/A.
+*
+* @note None.
+*
+******************************************************************************/
+void XUsbPs_ResetHw(u32 BaseAddress)
+{
+ u32 RegVal;
+ u32 Timeout = 0;
+
+ /* Host and device mode */
+ /* Disable the interrupts */
+ XUsbPs_WriteReg(BaseAddress,XUSBPS_IER_OFFSET,0x0);
+ /* Clear the interuupt status */
+ RegVal = XUsbPs_ReadReg(BaseAddress,XUSBPS_ISR_OFFSET);
+ XUsbPs_WriteReg(BaseAddress,XUSBPS_ISR_OFFSET,RegVal);
+
+ /* Perform the reset operation using USB CMD register */
+ RegVal = XUsbPs_ReadReg(BaseAddress,XUSBPS_CMD_OFFSET);
+ RegVal = RegVal | XUSBPS_CMD_RST_MASK;
+ XUsbPs_WriteReg(BaseAddress,XUSBPS_CMD_OFFSET,RegVal);
+ RegVal = XUsbPs_ReadReg(BaseAddress,XUSBPS_CMD_OFFSET);
+ /* Wait till the reset operation returns success */
+ /*
+ * FIX ME: right now no indication to the caller or user about
+ * timeout overflow
+ */
+ while ((RegVal & XUSBPS_CMD_RST_MASK) && (Timeout < XUSBPS_RESET_TIMEOUT))
+ {
+ RegVal = XUsbPs_ReadReg(BaseAddress,XUSBPS_CMD_OFFSET);
+ Timeout++;
+ }
+ /* Update periodic list base address register with reset value */
+ XUsbPs_WriteReg(BaseAddress,XUSBPS_LISTBASE_OFFSET,0x0);
+ /* Update async/endpoint list base address register with reset value */
+ XUsbPs_WriteReg(BaseAddress,XUSBPS_ASYNCLISTADDR_OFFSET,0x0);
+
+}
+
+
+
+/** @} */
diff --git a/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/usbps_v2_4/src/xusbps_hw.h b/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/usbps_v2_4/src/xusbps_hw.h
new file mode 100644
index 0000000..751a8d1
--- /dev/null
+++ b/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/usbps_v2_4/src/xusbps_hw.h
@@ -0,0 +1,520 @@
+/******************************************************************************
+*
+* Copyright (C) 2010 - 2015 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+* THE SOFTWARE.
+*
+*
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+ *
+ * @file xusbps_hw.h
+* @addtogroup usbps_v2_4
+* @{
+ *
+ * This header file contains identifiers and low-level driver functions (or
+ * macros) that can be used to access the device. High-level driver functions
+ * are defined in xusbps.h.
+ *
+ * <pre>
+ * MODIFICATION HISTORY:
+ *
+ * Ver Who Date Changes
+ * ----- ---- -------- -----------------------------------------------
+ * 1.00a wgr 10/10/10 First release
+ * 1.04a nm 10/23/12 Fixed CR# 679106.
+ * 1.05a kpc 07/03/13 Added XUsbPs_ResetHw function prototype
+ * 2.00a kpc 04/03/14 Fixed CR#777764. Corrected max endpoint vale and masks
+ * </pre>
+ *
+ ******************************************************************************/
+#ifndef XUSBPS_HW_H
+#define XUSBPS_HW_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/***************************** Include Files *********************************/
+
+#include "xil_types.h"
+#include "xil_assert.h"
+#include "xil_io.h"
+
+/************************** Constant Definitions *****************************/
+
+
+#define XUSBPS_REG_SPACING 4
+
+/** @name Timer 0 Register offsets
+ *
+ * @{
+ */
+#define XUSBPS_TIMER0_LD_OFFSET 0x00000080
+#define XUSBPS_TIMER0_CTL_OFFSET 0x00000084
+/* @} */
+
+/** @name Timer Control Register bit mask
+ *
+ * @{
+ */
+#define XUSBPS_TIMER_RUN_MASK 0x80000000
+#define XUSBPS_TIMER_STOP_MASK 0x80000000
+#define XUSBPS_TIMER_RESET_MASK 0x40000000
+#define XUSBPS_TIMER_REPEAT_MASK 0x01000000
+/* @} */
+
+/** @name Timer Control Register bit mask
+ *
+ * @{
+ */
+#define XUSBPS_TIMER_COUNTER_MASK 0x00FFFFFF
+/* @} */
+
+/** @name Device Hardware Parameters
+ *
+ * @{
+ */
+#define XUSBPS_HWDEVICE_OFFSET 0x0000000C
+
+#define XUSBPS_EP_NUM_MASK 0x3E
+#define XUSBPS_EP_NUM_SHIFT 1
+/* @} */
+
+/** @name Capability Register offsets
+ */
+#define XUSBPS_HCSPARAMS_OFFSET 0x00000104
+
+/** @name Operational Register offsets.
+ * Register comments are tagged with "H:" and "D:" for Host and Device modes,
+ * respectively.
+ * Tags are only present for registers that have a different meaning DEVICE and
+ * HOST modes. Most registers are only valid for either DEVICE or HOST mode.
+ * Those registers don't have tags.
+ * @{
+ */
+#define XUSBPS_CMD_OFFSET 0x00000140 /**< Configuration */
+#define XUSBPS_ISR_OFFSET 0x00000144 /**< Interrupt Status */
+#define XUSBPS_IER_OFFSET 0x00000148 /**< Interrupt Enable */
+#define XUSBPS_FRAME_OFFSET 0x0000014C /**< USB Frame Index */
+#define XUSBPS_LISTBASE_OFFSET 0x00000154 /**< H: Periodic List Base Address */
+#define XUSBPS_DEVICEADDR_OFFSET 0x00000154 /**< D: Device Address */
+#define XUSBPS_ASYNCLISTADDR_OFFSET 0x00000158 /**< H: Async List Address */
+#define XUSBPS_EPLISTADDR_OFFSET 0x00000158 /**< D: Endpoint List Addr */
+#define XUSBPS_TTCTRL_OFFSET 0x0000015C /**< TT Control */
+#define XUSBPS_BURSTSIZE_OFFSET 0x00000160 /**< Burst Size */
+#define XUSBPS_TXFILL_OFFSET 0x00000164 /**< Tx Fill Tuning */
+#define XUSBPS_ULPIVIEW_OFFSET 0x00000170 /**< ULPI Viewport */
+#define XUSBPS_EPNAKISR_OFFSET 0x00000178 /**< Endpoint NAK IRQ Status */
+#define XUSBPS_EPNAKIER_OFFSET 0x0000017C /**< Endpoint NAK IRQ Enable */
+#define XUSBPS_PORTSCR1_OFFSET 0x00000184 /**< Port Control/Status 1 */
+
+/* NOTE: The Port Control / Status Register index is 1-based. */
+#define XUSBPS_PORTSCRn_OFFSET(n) \
+ (XUSBPS_PORTSCR1_OFFSET + (((n)-1) * XUSBPS_REG_SPACING))
+
+
+#define XUSBPS_OTGCSR_OFFSET 0x000001A4 /**< OTG Status and Control */
+#define XUSBPS_MODE_OFFSET 0x000001A8 /**< USB Mode */
+#define XUSBPS_EPSTAT_OFFSET 0x000001AC /**< Endpoint Setup Status */
+#define XUSBPS_EPPRIME_OFFSET 0x000001B0 /**< Endpoint Prime */
+#define XUSBPS_EPFLUSH_OFFSET 0x000001B4 /**< Endpoint Flush */
+#define XUSBPS_EPRDY_OFFSET 0x000001B8 /**< Endpoint Ready */
+#define XUSBPS_EPCOMPL_OFFSET 0x000001BC /**< Endpoint Complete */
+#define XUSBPS_EPCR0_OFFSET 0x000001C0 /**< Endpoint Control 0 */
+#define XUSBPS_EPCR1_OFFSET 0x000001C4 /**< Endpoint Control 1 */
+#define XUSBPS_EPCR2_OFFSET 0x000001C8 /**< Endpoint Control 2 */
+#define XUSBPS_EPCR3_OFFSET 0x000001CC /**< Endpoint Control 3 */
+#define XUSBPS_EPCR4_OFFSET 0x000001D0 /**< Endpoint Control 4 */
+
+#define XUSBPS_MAX_ENDPOINTS 12 /**< Number of supported Endpoints in
+ * this core. */
+#define XUSBPS_EP_OUT_MASK 0x00000FFF /**< OUR (RX) endpoint mask */
+#define XUSBPS_EP_IN_MASK 0x0FFF0000 /**< IN (TX) endpoint mask */
+#define XUSBPS_EP_ALL_MASK 0x0FFF0FFF /**< Mask used for endpoint control
+ * registers */
+#define XUSBPS_EPCRn_OFFSET(n) \
+ (XUSBPS_EPCR0_OFFSET + ((n) * XUSBPS_REG_SPACING))
+
+#define XUSBPS_EPFLUSH_RX_SHIFT 0
+#define XUSBPS_EPFLUSH_TX_SHIFT 16
+
+/* @} */
+
+
+
+/** @name Endpoint Control Register (EPCR) bit positions.
+ * @{
+ */
+
+/* Definitions for TX Endpoint bits */
+#define XUSBPS_EPCR_TXT_CONTROL_MASK 0x00000000 /**< Control Endpoint - TX */
+#define XUSBPS_EPCR_TXT_ISO_MASK 0x00040000 /**< Isochronous. Endpoint */
+#define XUSBPS_EPCR_TXT_BULK_MASK 0x00080000 /**< Bulk Endpoint - TX */
+#define XUSBPS_EPCR_TXT_INTR_MASK 0x000C0000 /**< Interrupt Endpoint */
+#define XUSBPS_EPCR_TXS_MASK 0x00010000 /**< Stall TX endpoint */
+#define XUSBPS_EPCR_TXE_MASK 0x00800000 /**< Transmit enable - TX */
+#define XUSBPS_EPCR_TXR_MASK 0x00400000 /**< Data Toggle Reset Bit */
+
+
+/* Definitions for RX Endpoint bits */
+#define XUSBPS_EPCR_RXT_CONTROL_MASK 0x00000000 /**< Control Endpoint - RX */
+#define XUSBPS_EPCR_RXT_ISO_MASK 0x00000004 /**< Isochronous Endpoint */
+#define XUSBPS_EPCR_RXT_BULK_MASK 0x00000008 /**< Bulk Endpoint - RX */
+#define XUSBPS_EPCR_RXT_INTR_MASK 0x0000000C /**< Interrupt Endpoint */
+#define XUSBPS_EPCR_RXS_MASK 0x00000001 /**< Stall RX endpoint. */
+#define XUSBPS_EPCR_RXE_MASK 0x00000080 /**< Transmit enable. - RX */
+#define XUSBPS_EPCR_RXR_MASK 0x00000040 /**< Data Toggle Reset Bit */
+/* @} */
+
+
+/** @name USB Command Register (CR) bit positions.
+ * @{
+ */
+#define XUSBPS_CMD_RS_MASK 0x00000001 /**< Run/Stop */
+#define XUSBPS_CMD_RST_MASK 0x00000002 /**< Controller RESET */
+#define XUSBPS_CMD_FS01_MASK 0x0000000C /**< Frame List Size bit 0,1 */
+#define XUSBPS_CMD_PSE_MASK 0x00000010 /**< Periodic Sched Enable */
+#define XUSBPS_CMD_ASE_MASK 0x00000020 /**< Async Sched Enable */
+#define XUSBPS_CMD_IAA_MASK 0x00000040 /**< IRQ Async Advance Doorbell */
+#define XUSBPS_CMD_ASP_MASK 0x00000300 /**< Async Sched Park Mode Cnt */
+#define XUSBPS_CMD_ASPE_MASK 0x00000800 /**< Async Sched Park Mode Enbl */
+#define XUSBPS_CMD_SUTW_MASK 0x00002000 /**< Setup TripWire */
+#define XUSBPS_CMD_ATDTW_MASK 0x00004000 /**< Add dTD TripWire */
+#define XUSBPS_CMD_FS2_MASK 0x00008000 /**< Frame List Size bit 2 */
+#define XUSBPS_CMD_ITC_MASK 0x00FF0000 /**< IRQ Threshold Control */
+/* @} */
+
+
+/**
+ * @name Interrupt Threshold
+ * These definitions are used by software to set the maximum rate at which the
+ * USB controller will generate interrupt requests. The interrupt interval is
+ * given in number of micro-frames.
+ *
+ * USB defines a full-speed 1 ms frame time indicated by a Start Of Frame (SOF)
+ * packet each and every 1ms. USB also defines a high-speed micro-frame with a
+ * 125us frame time. For each micro-frame a SOF (Start Of Frame) packet is
+ * generated. Data is sent in between the SOF packets. The interrupt threshold
+ * defines how many micro-frames the controller waits before issuing an
+ * interrupt after data has been received.
+ *
+ * For a threshold of 0 the controller will issue an interrupt immediately
+ * after the last byte of the data has been received. For a threshold n>0 the
+ * controller will wait for n micro-frames before issuing an interrupt.
+ *
+ * Therefore, a setting of 8 micro-frames (default) means that the controller
+ * will issue at most 1 interrupt per millisecond.
+ *
+ * @{
+ */
+#define XUSBPS_CMD_ITHRESHOLD_0 0x00 /**< Immediate interrupt. */
+#define XUSBPS_CMD_ITHRESHOLD_1 0x01 /**< 1 micro-frame */
+#define XUSBPS_CMD_ITHRESHOLD_2 0x02 /**< 2 micro-frames */
+#define XUSBPS_CMD_ITHRESHOLD_4 0x04 /**< 4 micro-frames */
+#define XUSBPS_CMD_ITHRESHOLD_8 0x08 /**< 8 micro-frames */
+#define XUSBPS_CMD_ITHRESHOLD_16 0x10 /**< 16 micro-frames */
+#define XUSBPS_CMD_ITHRESHOLD_32 0x20 /**< 32 micro-frames */
+#define XUSBPS_CMD_ITHRESHOLD_64 0x40 /**< 64 micro-frames */
+#define XUSBPS_CMD_ITHRESHOLD_MAX XUSBPS_CMD_ITHRESHOLD_64
+#define XUSBPS_CMD_ITHRESHOLD_DEFAULT XUSBPS_CMD_ITHRESHOLD_8
+/* @} */
+
+
+
+/** @name USB Interrupt Status Register (ISR) / Interrupt Enable Register (IER)
+ * bit positions.
+ * @{
+ */
+#define XUSBPS_IXR_UI_MASK 0x00000001 /**< USB Transaction Complete */
+#define XUSBPS_IXR_UE_MASK 0x00000002 /**< Transaction Error */
+#define XUSBPS_IXR_PC_MASK 0x00000004 /**< Port Change Detect */
+#define XUSBPS_IXR_FRE_MASK 0x00000008 /**< Frame List Rollover */
+#define XUSBPS_IXR_AA_MASK 0x00000020 /**< Async Advance */
+#define XUSBPS_IXR_UR_MASK 0x00000040 /**< RESET Received */
+#define XUSBPS_IXR_SR_MASK 0x00000080 /**< Start of Frame */
+#define XUSBPS_IXR_SLE_MASK 0x00000100 /**< Device Controller Suspend */
+#define XUSBPS_IXR_ULPI_MASK 0x00000400 /**< ULPI IRQ */
+#define XUSBPS_IXR_HCH_MASK 0x00001000 /**< Host Controller Halted
+ * Read Only */
+#define XUSBPS_IXR_RCL_MASK 0x00002000 /**< USB Reclamation Read Only */
+#define XUSBPS_IXR_PS_MASK 0x00004000 /**< Periodic Sched Status
+ * Read Only */
+#define XUSBPS_IXR_AS_MASK 0x00008000 /**< Async Sched Status Read only */
+#define XUSBPS_IXR_NAK_MASK 0x00010000 /**< NAK IRQ */
+#define XUSBPS_IXR_UA_MASK 0x00040000 /**< USB Host Async IRQ */
+#define XUSBPS_IXR_UP_MASK 0x00080000 /**< USB Host Periodic IRQ */
+#define XUSBPS_IXR_TI0_MASK 0x01000000 /**< Timer 0 Interrupt */
+#define XUSBPS_IXR_TI1_MASK 0x02000000 /**< Timer 1 Interrupt */
+
+#define XUSBPS_IXR_ALL (XUSBPS_IXR_UI_MASK | \
+ XUSBPS_IXR_UE_MASK | \
+ XUSBPS_IXR_PC_MASK | \
+ XUSBPS_IXR_FRE_MASK | \
+ XUSBPS_IXR_AA_MASK | \
+ XUSBPS_IXR_UR_MASK | \
+ XUSBPS_IXR_SR_MASK | \
+ XUSBPS_IXR_SLE_MASK | \
+ XUSBPS_IXR_ULPI_MASK | \
+ XUSBPS_IXR_HCH_MASK | \
+ XUSBPS_IXR_RCL_MASK | \
+ XUSBPS_IXR_PS_MASK | \
+ XUSBPS_IXR_AS_MASK | \
+ XUSBPS_IXR_NAK_MASK | \
+ XUSBPS_IXR_UA_MASK | \
+ XUSBPS_IXR_UP_MASK | \
+ XUSBPS_IXR_TI0_MASK | \
+ XUSBPS_IXR_TI1_MASK)
+ /**< Mask for ALL IRQ types */
+/* @} */
+
+
+/** @name USB Mode Register (MODE) bit positions.
+ * @{
+ */
+#define XUSBPS_MODE_CM_MASK 0x00000003 /**< Controller Mode Select */
+#define XUSBPS_MODE_CM_IDLE_MASK 0x00000000
+#define XUSBPS_MODE_CM_DEVICE_MASK 0x00000002
+#define XUSBPS_MODE_CM_HOST_MASK 0x00000003
+#define XUSBPS_MODE_ES_MASK 0x00000004 /**< USB Endian Select */
+#define XUSBPS_MODE_SLOM_MASK 0x00000008 /**< USB Setup Lockout Mode Disable */
+#define XUSBPS_MODE_SDIS_MASK 0x00000010
+#define XUSBPS_MODE_VALID_MASK 0x0000001F
+
+/* @} */
+
+
+/** @name USB Device Address Register (DEVICEADDR) bit positions.
+ * @{
+ */
+#define XUSBPS_DEVICEADDR_DEVICEAADV_MASK 0x01000000
+ /**< Device Addr Auto Advance */
+#define XUSBPS_DEVICEADDR_ADDR_MASK 0xFE000000
+ /**< Device Address */
+#define XUSBPS_DEVICEADDR_ADDR_SHIFT 25
+ /**< Address shift */
+#define XUSBPS_DEVICEADDR_MAX 127
+ /**< Biggest allowed address */
+/* @} */
+
+/** @name USB TT Control Register (TTCTRL) bit positions.
+ * @{
+ */
+#define XUSBPS_TTCTRL_HUBADDR_MASK 0x7F000000 /**< TT Hub Address */
+/* @} */
+
+
+/** @name USB Burst Size Register (BURSTSIZE) bit posisions.
+ * @{
+ */
+#define XUSBPS_BURSTSIZE_RX_MASK 0x000000FF /**< RX Burst Length */
+#define XUSBPS_BURSTSIZE_TX_MASK 0x0000FF00 /**< TX Burst Length */
+/* @} */
+
+
+/** @name USB Tx Fill Tuning Register (TXFILL) bit positions.
+ * @{
+ */
+#define XUSBPS_TXFILL_OVERHEAD_MASK 0x000000FF
+ /**< Scheduler Overhead */
+#define XUSBPS_TXFILL_HEALTH_MASK 0x00001F00
+ /**< Scheduler Health Cntr */
+#define XUSBPS_TXFILL_BURST_MASK 0x003F0000
+ /**< FIFO Burst Threshold */
+/* @} */
+
+
+/** @name USB ULPI Viewport Register (ULPIVIEW) bit positions.
+ * @{
+ */
+#define XUSBPS_ULPIVIEW_DATWR_MASK 0x000000FF /**< ULPI Data Write */
+#define XUSBPS_ULPIVIEW_DATRD_MASK 0x0000FF00 /**< ULPI Data Read */
+#define XUSBPS_ULPIVIEW_ADDR_MASK 0x00FF0000 /**< ULPI Data Address */
+#define XUSBPS_ULPIVIEW_PORT_MASK 0x07000000 /**< ULPI Port Number */
+#define XUSBPS_ULPIVIEW_SS_MASK 0x08000000 /**< ULPI Synchronous State */
+#define XUSBPS_ULPIVIEW_RW_MASK 0x20000000 /**< ULPI Read/Write Control */
+#define XUSBPS_ULPIVIEW_RUN_MASK 0x40000000 /**< ULPI Run */
+#define XUSBPS_ULPIVIEW_WU_MASK 0x80000000 /**< ULPI Wakeup */
+/* @} */
+
+
+/** @name Port Status Control Register bit positions.
+ * @{
+ */
+#define XUSBPS_PORTSCR_CCS_MASK 0x00000001 /**< Current Connect Status */
+#define XUSBPS_PORTSCR_CSC_MASK 0x00000002 /**< Connect Status Change */
+#define XUSBPS_PORTSCR_PE_MASK 0x00000004 /**< Port Enable/Disable */
+#define XUSBPS_PORTSCR_PEC_MASK 0x00000008 /**< Port Enable/Disable Change */
+#define XUSBPS_PORTSCR_OCA_MASK 0x00000010 /**< Over-current Active */
+#define XUSBPS_PORTSCR_OCC_MASK 0x00000020 /**< Over-current Change */
+#define XUSBPS_PORTSCR_FPR_MASK 0x00000040 /**< Force Port Resume */
+#define XUSBPS_PORTSCR_SUSP_MASK 0x00000080 /**< Suspend */
+#define XUSBPS_PORTSCR_PR_MASK 0x00000100 /**< Port Reset */
+#define XUSBPS_PORTSCR_HSP_MASK 0x00000200 /**< High Speed Port */
+#define XUSBPS_PORTSCR_LS_MASK 0x00000C00 /**< Line Status */
+#define XUSBPS_PORTSCR_PP_MASK 0x00001000 /**< Port Power */
+#define XUSBPS_PORTSCR_PO_MASK 0x00002000 /**< Port Owner */
+#define XUSBPS_PORTSCR_PIC_MASK 0x0000C000 /**< Port Indicator Control */
+#define XUSBPS_PORTSCR_PTC_MASK 0x000F0000 /**< Port Test Control */
+#define XUSBPS_PORTSCR_WKCN_MASK 0x00100000 /**< Wake on Connect Enable */
+#define XUSBPS_PORTSCR_WKDS_MASK 0x00200000 /**< Wake on Disconnect Enable */
+#define XUSBPS_PORTSCR_WKOC_MASK 0x00400000 /**< Wake on Over-current Enable */
+#define XUSBPS_PORTSCR_PHCD_MASK 0x00800000 /**< PHY Low Power Suspend -
+ * Clock Disable */
+#define XUSBPS_PORTSCR_PFSC_MASK 0x01000000 /**< Port Force Full Speed
+ * Connect */
+#define XUSBPS_PORTSCR_PSPD_MASK 0x0C000000 /**< Port Speed */
+/* @} */
+
+
+/** @name On-The-Go Status Control Register (OTGCSR) bit positions.
+ * @{
+ */
+#define XUSBPS_OTGSC_VD_MASK 0x00000001 /**< VBus Discharge Bit */
+#define XUSBPS_OTGSC_VC_MASK 0x00000002 /**< VBus Charge Bit */
+#define XUSBPS_OTGSC_HAAR_MASK 0x00000004 /**< HW Assist Auto Reset
+ * Enable Bit */
+#define XUSBPS_OTGSC_OT_MASK 0x00000008 /**< OTG Termination Bit */
+#define XUSBPS_OTGSC_DP_MASK 0x00000010 /**< Data Pulsing Pull-up
+ * Enable Bit */
+#define XUSBPS_OTGSC_IDPU_MASK 0x00000020 /**< ID Pull-up Enable Bit */
+#define XUSBPS_OTGSC_HADP_MASK 0x00000040 /**< HW Assist Data Pulse
+ * Enable Bit */
+#define XUSBPS_OTGSC_HABA_MASK 0x00000080 /**< USB Hardware Assist
+ * B Disconnect to A
+ * Connect Enable Bit */
+#define XUSBPS_OTGSC_ID_MASK 0x00000100 /**< ID Status Flag */
+#define XUSBPS_OTGSC_AVV_MASK 0x00000200 /**< USB A VBus Valid Interrupt Status Flag */
+#define XUSBPS_OTGSC_ASV_MASK 0x00000400 /**< USB A Session Valid Interrupt Status Flag */
+#define XUSBPS_OTGSC_BSV_MASK 0x00000800 /**< USB B Session Valid Status Flag */
+#define XUSBPS_OTGSC_BSE_MASK 0x00001000 /**< USB B Session End Status Flag */
+#define XUSBPS_OTGSC_1MST_MASK 0x00002000 /**< USB 1 Millisecond Timer Status Flag */
+#define XUSBPS_OTGSC_DPS_MASK 0x00004000 /**< Data Pulse Status Flag */
+#define XUSBPS_OTGSC_IDIS_MASK 0x00010000 /**< USB ID Interrupt Status Flag */
+#define XUSBPS_OTGSC_AVVIS_MASK 0x00020000 /**< USB A VBus Valid Interrupt Status Flag */
+#define XUSBPS_OTGSC_ASVIS_MASK 0x00040000 /**< USB A Session Valid Interrupt Status Flag */
+#define XUSBPS_OTGSC_BSVIS_MASK 0x00080000 /**< USB B Session Valid Interrupt Status Flag */
+#define XUSBPS_OTGSC_BSEIS_MASK 0x00100000 /**< USB B Session End Interrupt Status Flag */
+#define XUSBPS_OTGSC_1MSS_MASK 0x00200000 /**< 1 Millisecond Timer Interrupt Status Flag */
+#define XUSBPS_OTGSC_DPIS_MASK 0x00400000 /**< Data Pulse Interrupt Status Flag */
+#define XUSBPS_OTGSC_IDIE_MASK 0x01000000 /**< ID Interrupt Enable Bit */
+#define XUSBPS_OTGSC_AVVIE_MASK 0x02000000 /**< USB A VBus Valid Interrupt Enable Bit */
+#define XUSBPS_OTGSC_ASVIE_MASK 0x04000000 /**< USB A Session Valid Interrupt Enable Bit */
+#define XUSBPS_OTGSC_BSVIE_MASK 0x08000000 /**< USB B Session Valid Interrupt Enable Bit */
+#define XUSBPS_OTGSC_BSEE_MASK 0x10000000 /**< USB B Session End Interrupt Enable Bit */
+#define XUSBPS_OTGSC_1MSE_MASK 0x20000000 /**< 1 Millisecond Timer
+ * Interrupt Enable Bit */
+#define XUSBPS_OTGSC_DPIE_MASK 0x40000000 /**< Data Pulse Interrupt
+ * Enable Bit */
+
+#define XUSBPS_OTG_ISB_ALL (XUSBPS_OTGSC_IDIS_MASK |\
+ XUSBPS_OTGSC_AVVIS_MASK | \
+ XUSBPS_OTGSC_ASVIS_MASK | \
+ XUSBPS_OTGSC_BSVIS_MASK | \
+ XUSBPS_OTGSC_BSEIS_MASK | \
+ XUSBPS_OTGSC_1MSS_MASK | \
+ XUSBPS_OTGSC_DPIS_MASK)
+ /** Mask for All IRQ status masks */
+
+#define XUSBPS_OTG_IEB_ALL (XUSBPS_OTGSC_IDIE_MASK |\
+ XUSBPS_OTGSC_AVVIE_MASK | \
+ XUSBPS_OTGSC_ASVIE_MASK | \
+ XUSBPS_OTGSC_BSVIE_MASK | \
+ XUSBPS_OTGSC_BSEE_IEB_MASK | \
+ XUSBPS_OTGSC_1MSE_MASK | \
+ XUSBPS_OTGSC_DPIE_MASK)
+ /** Mask for All IRQ Enable masks */
+/* @} */
+
+
+/**< Alignment of the Device Queue Head List BASE. */
+#define XUSBPS_dQH_BASE_ALIGN 2048
+
+/**< Alignment of a Device Queue Head structure. */
+#define XUSBPS_dQH_ALIGN 64
+
+/**< Alignment of a Device Transfer Descriptor structure. */
+#define XUSBPS_dTD_ALIGN 32
+
+/**< Size of one RX buffer for a OUT Transfer Descriptor. */
+#define XUSBPS_dTD_BUF_SIZE 4096
+
+/**< Maximum size of one RX/TX buffer. */
+#define XUSBPS_dTD_BUF_MAX_SIZE 16*1024
+
+/**< Alignment requirement for Transfer Descriptor buffers. */
+#define XUSBPS_dTD_BUF_ALIGN 4096
+
+
+/**************************** Type Definitions *******************************/
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/****************************************************************************/
+/**
+*
+* This macro reads the given register.
+*
+* @param BaseAddress is the base address for the USB registers.
+* @param RegOffset is the register offset to be read.
+*
+* @return The 32-bit value of the register.
+*
+* @note C-style signature:
+* u32 XUsbPs_ReadReg(u32 BaseAddress, u32 RegOffset)
+*
+*****************************************************************************/
+#define XUsbPs_ReadReg(BaseAddress, RegOffset) \
+ Xil_In32(BaseAddress + (RegOffset))
+
+
+/****************************************************************************/
+/**
+*
+* This macro writes the given register.
+*
+* @param BaseAddress is the the base address for the USB registers.
+* @param RegOffset is the register offset to be written.
+* @param Data is the the 32-bit value to write to the register.
+*
+* @return None.
+*
+* @note C-style signature:
+* void XUsbPs_WriteReg(u32 BaseAddress, u32 RegOffset, u32 Data)
+*
+ *****************************************************************************/
+#define XUsbPs_WriteReg(BaseAddress, RegOffset, Data) \
+ Xil_Out32(BaseAddress + (RegOffset), (Data))
+
+
+/************************** Function Prototypes ******************************/
+/*
+ * Perform reset operation to the USB PS interface
+ */
+void XUsbPs_ResetHw(u32 BaseAddress);
+/************************** Variable Definitions ******************************/
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* XUSBPS_L_H */
+/** @} */
diff --git a/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/usbps_v2_4/src/xusbps_intr.c b/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/usbps_v2_4/src/xusbps_intr.c
new file mode 100644
index 0000000..3b03f0b
--- /dev/null
+++ b/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/usbps_v2_4/src/xusbps_intr.c
@@ -0,0 +1,466 @@
+/******************************************************************************
+*
+* Copyright (C) 2010 - 2015 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+* THE SOFTWARE.
+*
+*
+*
+******************************************************************************/
+/******************************************************************************/
+/**
+ * @file xusbps_intr.c
+* @addtogroup usbps_v2_4
+* @{
+ *
+ * This file contains the functions that are related to interrupt processing
+ * for the EPB USB driver.
+ *
+ * <pre>
+ * MODIFICATION HISTORY:
+ *
+ * Ver Who Date Changes
+ * ----- ---- -------- ----------------------------------------------------------
+ * 1.00a jz 10/10/10 First release
+ * 1.03a nm 09/21/12 Fixed CR#678977. Added proper sequence for setup packet
+ * handling.
+ * 2.3 bss 01/19/16 Modified XUsbPs_EpQueueRequest function to fix CR#873972
+ * (moving of dTD Head/Tail Pointers properly).
+ * </pre>
+ ******************************************************************************/
+
+/***************************** Include Files **********************************/
+
+#include "xusbps.h"
+#include "xusbps_endpoint.h"
+
+/************************** Constant Definitions ******************************/
+
+/**************************** Type Definitions ********************************/
+
+/***************** Macros (Inline Functions) Definitions **********************/
+
+/************************** Variable Definitions ******************************/
+
+/************************** Function Prototypes *******************************/
+
+static void XUsbPs_IntrHandleTX(XUsbPs *InstancePtr, u32 EpCompl);
+static void XUsbPs_IntrHandleRX(XUsbPs *InstancePtr, u32 EpCompl);
+static void XUsbPs_IntrHandleReset(XUsbPs *InstancePtr, u32 IrqSts);
+static void XUsbPs_IntrHandleEp0Setup(XUsbPs *InstancePtr);
+
+/*****************************************************************************/
+/**
+* This function is the first-level interrupt handler for the USB core. All USB
+* interrupts will be handled here. Depending on the type of the interrupt,
+* second level interrupt handler may be called. Second level interrupt
+* handlers will be registered by the user using the:
+* XUsbPs_IntrSetHandler()
+* and/or
+* XUsbPs_EpSetHandler()
+* functions.
+*
+*
+* @param HandlerRef is a Reference passed to the interrupt register
+* function. In our case this will be a pointer to the XUsbPs
+* instance.
+*
+* @return None
+*
+* @note None
+*
+******************************************************************************/
+void XUsbPs_IntrHandler(void *HandlerRef)
+{
+ XUsbPs *InstancePtr;
+
+ u32 IrqSts;
+
+ Xil_AssertVoid(HandlerRef != NULL);
+
+ InstancePtr = (XUsbPs *) HandlerRef;
+
+ /* Handle controller (non-endpoint) related interrupts. */
+ IrqSts = XUsbPs_ReadReg(InstancePtr->Config.BaseAddress,
+ XUSBPS_ISR_OFFSET);
+
+ /* Clear the interrupt status register. */
+ XUsbPs_WriteReg(InstancePtr->Config.BaseAddress,
+ XUSBPS_ISR_OFFSET, IrqSts);
+
+ /* Nak interrupt, used to respond to host's IN request */
+ if(IrqSts & XUSBPS_IXR_NAK_MASK) {
+ /* Ack the hardware */
+ XUsbPs_WriteReg(InstancePtr->Config.BaseAddress,
+ XUSBPS_EPNAKISR_OFFSET,
+ XUsbPs_ReadReg(InstancePtr->Config.BaseAddress,
+ XUSBPS_EPNAKISR_OFFSET));
+ }
+
+
+ /***************************************************************
+ *
+ * Handle general interrupts. Endpoint interrupts will be handler
+ * later.
+ *
+ */
+
+ /* RESET interrupt.*/
+ if (IrqSts & XUSBPS_IXR_UR_MASK) {
+ XUsbPs_IntrHandleReset(InstancePtr, IrqSts);
+ return;
+ }
+
+ /* Check if we have a user handler that needs to be called. Note that
+ * this is the handler for general interrupts. Endpoint interrupts will
+ * be handled below.
+ */
+ if ((IrqSts & InstancePtr->HandlerMask) && InstancePtr->HandlerFunc) {
+ (InstancePtr->HandlerFunc)(InstancePtr->HandlerRef, IrqSts);
+ }
+
+
+ /***************************************************************
+ *
+ * Handle Endpoint interrupts.
+ *
+ */
+ if (IrqSts & XUSBPS_IXR_UI_MASK) {
+ u32 EpStat;
+ u32 EpCompl;
+
+ /* ENDPOINT 0 SETUP PACKET HANDLING
+ *
+ * Check if we got a setup packet on endpoint 0. Currently we
+ * only check for setup packets on endpoint 0 as we would not
+ * expect setup packets on any other endpoint (even though it
+ * is possible to send setup packets on other endpoints).
+ */
+ EpStat = XUsbPs_ReadReg(InstancePtr->Config.BaseAddress,
+ XUSBPS_EPSTAT_OFFSET);
+ if (EpStat & 0x0001) {
+ /* Handle the setup packet */
+ XUsbPs_IntrHandleEp0Setup(InstancePtr);
+
+ /* Re-Prime the endpoint.
+ * Endpoint is de-primed if a setup packet comes in.
+ */
+ XUsbPs_EpPrime(InstancePtr, 0, XUSBPS_EP_DIRECTION_OUT);
+ }
+
+ /* Check for RX and TX complete interrupts. */
+ EpCompl = XUsbPs_ReadReg(InstancePtr->Config.BaseAddress,
+ XUSBPS_EPCOMPL_OFFSET);
+
+
+ /* ACK the complete interrupts. */
+ XUsbPs_WriteReg(InstancePtr->Config.BaseAddress,
+ XUSBPS_EPCOMPL_OFFSET, EpCompl);
+
+ /* Check OUT (RX) endpoints. */
+ if (EpCompl & XUSBPS_EP_OUT_MASK) {
+ XUsbPs_IntrHandleRX(InstancePtr, EpCompl);
+ }
+
+ /* Check IN (TX) endpoints. */
+ if (EpCompl & XUSBPS_EP_IN_MASK) {
+ XUsbPs_IntrHandleTX(InstancePtr, EpCompl);
+ }
+ }
+}
+
+
+/*****************************************************************************/
+/**
+* This function registers the user callback handler for controller
+* (non-endpoint) interrupts.
+*
+* @param InstancePtr is a pointer to the XUsbPs instance of the
+* controller.
+* @param CallBackFunc is the Callback function to register.
+* CallBackFunc may be NULL to clear the entry.
+* @param CallBackRef is the user data reference passed to the
+* callback function. CallBackRef may be NULL.
+* @param Mask is the User interrupt mask. Defines which interrupts
+* will cause the callback to be called.
+*
+* @return
+* - XST_SUCCESS: Callback registered successfully.
+* - XST_FAILURE: Callback could not be registered.
+*
+* @note None.
+*
+******************************************************************************/
+int XUsbPs_IntrSetHandler(XUsbPs *InstancePtr,
+ XUsbPs_IntrHandlerFunc CallBackFunc,
+ void *CallBackRef, u32 Mask)
+{
+ Xil_AssertNonvoid(InstancePtr != NULL);
+
+ InstancePtr->HandlerFunc = CallBackFunc;
+ InstancePtr->HandlerRef = CallBackRef;
+ InstancePtr->HandlerMask = Mask;
+
+ return XST_SUCCESS;
+}
+
+
+/*****************************************************************************/
+/**
+* This function handles TX buffer interrupts. It is called by the interrupt
+* when a transmit complete interrupt occurs. It returns buffers of completed
+* descriptors to the caller.
+*
+* @param InstancePtr is a pointer to the XUsbPs instance of the
+* controller.
+* @param EpCompl is the Bit mask of endpoints that caused a transmit
+* complete interrupt.
+*
+* @return None
+*
+* @note None.
+*
+******************************************************************************/
+static void XUsbPs_IntrHandleTX(XUsbPs *InstancePtr, u32 EpCompl)
+{
+ int Index;
+ u32 Mask;
+ int NumEp;
+
+ /* Check all endpoints for TX complete bits.
+ */
+ Mask = 0x00010000;
+ NumEp = InstancePtr->DeviceConfig.NumEndpoints;
+
+ /* Check for every endpoint if its TX complete bit is
+ * set.
+ */
+ for (Index = 0; Index < NumEp; Index++, Mask <<= 1) {
+ XUsbPs_EpIn *Ep;
+
+ if (!(EpCompl & Mask)) {
+ continue;
+ }
+ /* The TX complete bit for this endpoint is
+ * set. Walk the list of descriptors to see
+ * which ones are completed.
+ */
+ Ep = &InstancePtr->DeviceConfig.Ep[Index].In;
+ do {
+
+ XUsbPs_dTDInvalidateCache(Ep->dTDTail);
+
+ /* If the descriptor is not active then the buffer has
+ * not been sent yet.
+ */
+ if (XUsbPs_dTDIsActive(Ep->dTDTail)) {
+ break;
+ }
+
+ if (Ep->HandlerFunc) {
+ void *BufPtr;
+
+ BufPtr = (void *) XUsbPs_ReaddTD(Ep->dTDTail,
+ XUSBPS_dTDUSERDATA);
+
+ Ep->HandlerFunc(Ep->HandlerRef, Index,
+ XUSBPS_EP_EVENT_DATA_TX,
+ BufPtr);
+ }
+
+ Ep->dTDTail = XUsbPs_dTDGetNLP(Ep->dTDTail);
+ } while(Ep->dTDTail != Ep->dTDHead);
+ }
+}
+
+
+/*****************************************************************************/
+/**
+ * This function handles RX buffer interrupts. It is called by the interrupt
+ * when a receive complete interrupt occurs. It notifies the callback functions
+ * that have been registered with the individual endpoints that data has been
+ * received.
+ *
+ * @param InstancePtr
+ * Pointer to the XUsbPs instance of the controller.
+ *
+ * @param EpCompl
+ * Bit mask of endpoints that caused a receive complete interrupt.
+ * @return
+ * none
+ *
+ ******************************************************************************/
+static void XUsbPs_IntrHandleRX(XUsbPs *InstancePtr, u32 EpCompl)
+{
+ XUsbPs_EpOut *Ep;
+ int Index;
+ u32 Mask;
+ int NumEp;
+
+ /* Check all endpoints for RX complete bits. */
+ Mask = 0x00000001;
+ NumEp = InstancePtr->DeviceConfig.NumEndpoints;
+
+
+ /* Check for every endpoint if its RX complete bit is set.*/
+ for (Index = 0; Index < NumEp; Index++, Mask <<= 1) {
+ int numP = 0;
+
+ if (!(EpCompl & Mask)) {
+ continue;
+ }
+ Ep = &InstancePtr->DeviceConfig.Ep[Index].Out;
+
+ XUsbPs_dTDInvalidateCache(Ep->dTDCurr);
+
+ /* Handle all finished dTDs */
+ while (!XUsbPs_dTDIsActive(Ep->dTDCurr)) {
+ numP += 1;
+ if (Ep->HandlerFunc) {
+ Ep->HandlerFunc(Ep->HandlerRef, Index,
+ XUSBPS_EP_EVENT_DATA_RX, NULL);
+ }
+
+ Ep->dTDCurr = XUsbPs_dTDGetNLP(Ep->dTDCurr);
+ XUsbPs_dTDInvalidateCache(Ep->dTDCurr);
+ }
+ /* Re-Prime the endpoint.*/
+ XUsbPs_EpPrime(InstancePtr, Index, XUSBPS_EP_DIRECTION_OUT);
+ }
+}
+
+
+/*****************************************************************************/
+/**
+* This function handles a RESET interrupt. It will notify the interrupt
+* handler callback of the RESET condition.
+*
+* @param InstancePtr is pointer to the XUsbPs instance of the controller
+* @param IrqSts is the Interrupt status register content.
+* To be passed on to the user.
+*
+* @return None
+*
+* @Note None.
+*
+******************************************************************************/
+static void XUsbPs_IntrHandleReset(XUsbPs *InstancePtr, u32 IrqSts)
+{
+ int Timeout;
+
+ /* Clear all setup token semaphores by reading the
+ * XUSBPS_EPSTAT_OFFSET register and writing its value back to
+ * itself.
+ */
+ XUsbPs_WriteReg(InstancePtr->Config.BaseAddress, XUSBPS_EPSTAT_OFFSET,
+ XUsbPs_ReadReg(InstancePtr->Config.BaseAddress,
+ XUSBPS_EPSTAT_OFFSET));
+
+ /* Clear all the endpoint complete status bits by reading the
+ * XUSBPS_EPCOMPL_OFFSET register and writings its value back
+ * to itself.
+ */
+ XUsbPs_WriteReg(InstancePtr->Config.BaseAddress,
+ XUSBPS_EPCOMPL_OFFSET,
+ XUsbPs_ReadReg(InstancePtr->Config.BaseAddress,
+ XUSBPS_EPCOMPL_OFFSET));
+
+ /* Cancel all endpoint prime status by waiting until all bits
+ * in XUSBPS_EPPRIME_OFFSET are 0 and then writing 0xFFFFFFFF
+ * to XUSBPS_EPFLUSH_OFFSET.
+ *
+ * Avoid hanging here by using a Timeout counter...
+ */
+ Timeout = XUSBPS_TIMEOUT_COUNTER;
+ while ((XUsbPs_ReadReg(InstancePtr->Config.BaseAddress,
+ XUSBPS_EPPRIME_OFFSET) &
+ XUSBPS_EP_ALL_MASK) && --Timeout) {
+ /* NOP */
+ }
+ XUsbPs_WriteReg(InstancePtr->Config.BaseAddress,
+ XUSBPS_EPFLUSH_OFFSET, 0xFFFFFFFF);
+
+ /* Make sure that the reset bit in XUSBPS_PORTSCR1_OFFSET is
+ * still set at this point. If the code gets to this point and
+ * the reset bit has already been cleared we are in trouble and
+ * hardware reset is necessary.
+ */
+ if (!(XUsbPs_ReadReg(InstancePtr->Config.BaseAddress,
+ XUSBPS_PORTSCR1_OFFSET) &
+ XUSBPS_PORTSCR_PR_MASK)) {
+ /* Send a notification to the user that a hardware
+ * RESET is required. At this point we can only hope
+ * that the user registered an interrupt handler and
+ * will issue a hardware RESET.
+ */
+ if (InstancePtr->HandlerFunc) {
+ (InstancePtr->HandlerFunc)(InstancePtr->HandlerRef,
+ IrqSts);
+ }
+ else {
+ for (;;);
+ }
+
+ /* If we get here there is nothing more to do. The user
+ * should have reset the core.
+ */
+ return;
+ }
+
+ /* Check if we have a user handler that needs to be called.
+ */
+ if (InstancePtr->HandlerFunc) {
+ (InstancePtr->HandlerFunc)(InstancePtr->HandlerRef, IrqSts);
+ }
+
+ /* We are done. After RESET we don't proceed in the interrupt
+ * handler.
+ */
+}
+
+
+/*****************************************************************************/
+/**
+* This function handles a Setup Packet interrupt. It will notify the interrupt
+* handler callback of the RESET condition.
+*
+* @param InstancePtr is a pointer to the XUsbPs instance of the
+* controller.
+*
+* @return None
+*
+* @Note None
+*
+******************************************************************************/
+static void XUsbPs_IntrHandleEp0Setup(XUsbPs *InstancePtr)
+{
+
+ XUsbPs_EpOut *Ep;
+
+ /* Notify the user. */
+ Ep = &InstancePtr->DeviceConfig.Ep[0].Out;
+
+ if (Ep->HandlerFunc) {
+ Ep->HandlerFunc(Ep->HandlerRef, 0,
+ XUSBPS_EP_EVENT_SETUP_DATA_RECEIVED, NULL);
+ }
+}
+
+
+/** @} */
diff --git a/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/usbps_v2_4/src/xusbps_sinit.c b/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/usbps_v2_4/src/xusbps_sinit.c
new file mode 100644
index 0000000..e84d62b
--- /dev/null
+++ b/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/usbps_v2_4/src/xusbps_sinit.c
@@ -0,0 +1,93 @@
+/******************************************************************************
+*
+* Copyright (C) 2010 - 2015 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+* THE SOFTWARE.
+*
+*
+*
+******************************************************************************/
+/****************************************************************************/
+/**
+ *
+ * @file xusbps_sinit.c
+* @addtogroup usbps_v2_4
+* @{
+ *
+ * The implementation of the XUsbPs driver's static initialization
+ * functionality.
+ *
+ * <pre>
+ * MODIFICATION HISTORY:
+ *
+ * Ver Who Date Changes
+ * ----- ---- -------- -----------------------------------------------
+ * 1.00a wgr 10/10/10 First release
+ * </pre>
+ *
+ *****************************************************************************/
+
+/***************************** Include Files ********************************/
+
+#include "xstatus.h"
+#include "xusbps.h"
+#include "xparameters.h"
+
+/************************** Constant Definitions ****************************/
+
+/**************************** Type Definitions ******************************/
+
+/***************** Macros (Inline Functions) Definitions ********************/
+
+/************************** Variable Definitions ****************************/
+
+extern XUsbPs_Config XUsbPs_ConfigTable[];
+
+/************************** Function Prototypes *****************************/
+
+/****************************************************************************/
+/**
+*
+* Looks up the controller configuration based on the unique controller ID. A
+* table contains the configuration info for each controller in the system.
+*
+* @param DeviceID is the ID of the controller to look up the
+* configuration for.
+*
+* @return
+* A pointer to the configuration found or NULL if the specified
+* controller ID was not found.
+*
+******************************************************************************/
+XUsbPs_Config *XUsbPs_LookupConfig(u16 DeviceID)
+{
+ XUsbPs_Config *CfgPtr = NULL;
+
+ int Index;
+
+ for (Index = 0; Index < XPAR_XUSBPS_NUM_INSTANCES; Index++) {
+ if (XUsbPs_ConfigTable[Index].DeviceID == DeviceID) {
+ CfgPtr = &XUsbPs_ConfigTable[Index];
+ break;
+ }
+ }
+
+ return CfgPtr;
+}
+/** @} */
diff --git a/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/xadcps_v2_3/src/Makefile b/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/xadcps_v2_3/src/Makefile
new file mode 100644
index 0000000..837ca13
--- /dev/null
+++ b/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/xadcps_v2_3/src/Makefile
@@ -0,0 +1,40 @@
+COMPILER=
+ARCHIVER=
+CP=cp
+COMPILER_FLAGS=
+EXTRA_COMPILER_FLAGS=
+LIB=libxil.a
+
+CC_FLAGS = $(COMPILER_FLAGS)
+ECC_FLAGS = $(EXTRA_COMPILER_FLAGS)
+
+RELEASEDIR=../../../lib
+INCLUDEDIR=../../../include
+INCLUDES=-I./. -I${INCLUDEDIR}
+
+OUTS = *.o
+
+LIBSOURCES:=*.c
+INCLUDEFILES:=*.h
+
+OBJECTS = $(addsuffix .o, $(basename $(wildcard *.c)))
+
+libs: banner xadcps_libs clean
+
+%.o: %.c
+ ${COMPILER} $(CC_FLAGS) $(ECC_FLAGS) $(INCLUDES) -o $@ $<
+
+banner:
+ echo "Compiling xadcps"
+
+xadcps_libs: ${OBJECTS}
+ $(ARCHIVER) -r ${RELEASEDIR}/${LIB} ${OBJECTS}
+
+.PHONY: include
+include: xadcps_includes
+
+xadcps_includes:
+ ${CP} ${INCLUDEFILES} ${INCLUDEDIR}
+
+clean:
+ rm -rf ${OBJECTS}
diff --git a/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/xadcps_v2_3/src/xadcps.c b/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/xadcps_v2_3/src/xadcps.c
new file mode 100644
index 0000000..797c8d5
--- /dev/null
+++ b/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/xadcps_v2_3/src/xadcps.c
@@ -0,0 +1,1828 @@
+/******************************************************************************
+*
+* Copyright (C) 2011 - 2014 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+* THE SOFTWARE.
+*
+*
+*
+******************************************************************************/
+/****************************************************************************/
+/**
+*
+* @file xadcps.c
+* @addtogroup xadcps_v2_3
+* @{
+*
+* This file contains the driver API functions that can be used to access
+* the XADC device.
+*
+* Refer to the xadcps.h header file for more information about this driver.
+*
+* @note None.
+*
+* <pre>
+*
+* MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ----- ----- -------- -----------------------------------------------------
+* 1.00a ssb 12/22/11 First release based on the XPS/AXI xadc driver
+* 1.01a bss 02/18/13 Modified XAdcPs_SetSeqChEnables,XAdcPs_SetSeqAvgEnables
+* XAdcPs_SetSeqInputMode and XAdcPs_SetSeqAcqTime APIs
+* to fix CR #693371
+* 2.1 bss 08/05/14 Modified Assert for XAdcPs_SetSingleChParams to fix
+* CR #807563.
+* 2.2 bss 04/27/14 Modified to use correct Device Config base address
+* (CR#854437).
+* 2.3 mn 07/09/18 Fix Doxygen warning
+* </pre>
+*
+*****************************************************************************/
+
+/***************************** Include Files ********************************/
+
+#include "xadcps.h"
+
+/************************** Constant Definitions ****************************/
+
+/**************************** Type Definitions ******************************/
+
+/***************** Macros (Inline Functions) Definitions ********************/
+
+/************************** Function Prototypes *****************************/
+
+void XAdcPs_WriteInternalReg(XAdcPs *InstancePtr, u32 RegOffset, u32 Data);
+u32 XAdcPs_ReadInternalReg(XAdcPs *InstancePtr, u32 RegOffset);
+
+
+/************************** Variable Definitions ****************************/
+
+
+/*****************************************************************************/
+/**
+*
+* This function initializes a specific XAdcPs device/instance. This function
+* must be called prior to using the XADC device.
+*
+* @param InstancePtr is a pointer to the XAdcPs instance.
+* @param ConfigPtr points to the XAdcPs device configuration structure.
+* @param EffectiveAddr is the device base address in the virtual memory
+* address space. If the address translation is not used then the
+* physical address is passed.
+* Unexpected errors may occur if the address mapping is changed
+* after this function is invoked.
+*
+* @return
+* - XST_SUCCESS if successful.
+*
+* @note The user needs to first call the XAdcPs_LookupConfig() API
+* which returns the Configuration structure pointer which is
+* passed as a parameter to the XAdcPs_CfgInitialize() API.
+*
+******************************************************************************/
+int XAdcPs_CfgInitialize(XAdcPs *InstancePtr, XAdcPs_Config *ConfigPtr,
+ u32 EffectiveAddr)
+{
+
+ u32 RegValue;
+ /*
+ * Assert the input arguments.
+ */
+ Xil_AssertNonvoid(InstancePtr != NULL);
+ Xil_AssertNonvoid(ConfigPtr != NULL);
+
+
+ /*
+ * Set the values read from the device config and the base address.
+ */
+ InstancePtr->Config.DeviceId = ConfigPtr->DeviceId;
+ InstancePtr->Config.BaseAddress = EffectiveAddr;
+
+ /* Write Unlock value to Device Config Unlock register */
+ XAdcPs_WriteReg(XPAR_XDCFG_0_BASEADDR,
+ XADCPS_UNLK_OFFSET, XADCPS_UNLK_VALUE);
+
+ /* Enable the PS access of xadc and set FIFO thresholds */
+
+ RegValue = XAdcPs_ReadReg((InstancePtr)->Config.BaseAddress,
+ XADCPS_CFG_OFFSET);
+
+ RegValue = RegValue | XADCPS_CFG_ENABLE_MASK |
+ XADCPS_CFG_CFIFOTH_MASK | XADCPS_CFG_DFIFOTH_MASK;
+
+ XAdcPs_WriteReg((InstancePtr)->Config.BaseAddress,
+ XADCPS_CFG_OFFSET, RegValue);
+
+ /* Release xadc from reset */
+
+ XAdcPs_WriteReg((InstancePtr)->Config.BaseAddress,
+ XADCPS_MCTL_OFFSET, 0x00);
+
+ /*
+ * Indicate the instance is now ready to use and
+ * initialized without error.
+ */
+ InstancePtr->IsReady = XIL_COMPONENT_IS_READY;
+
+ return XST_SUCCESS;
+}
+
+
+/****************************************************************************/
+/**
+*
+* The functions sets the contents of the Config Register.
+*
+* @param InstancePtr is a pointer to the XAdcPs instance.
+* @param Data is the 32 bit data to be written to the Register.
+*
+* @return None.
+*
+* @note None.
+*
+*****************************************************************************/
+void XAdcPs_SetConfigRegister(XAdcPs *InstancePtr, u32 Data)
+{
+ /*
+ * Assert the arguments.
+ */
+ Xil_AssertVoid(InstancePtr != NULL);
+ Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+ XAdcPs_WriteReg((InstancePtr)->Config.BaseAddress,
+ XADCPS_CFG_OFFSET, Data);
+
+}
+
+
+/****************************************************************************/
+/**
+*
+* The functions reads the contents of the Config Register.
+*
+* @param InstancePtr is a pointer to the XAdcPs instance.
+*
+* @return A 32-bit value representing the contents of the Config Register.
+* Use the XADCPS_SR_*_MASK constants defined in xadcps_hw.h to
+* interpret the returned value.
+*
+* @note None.
+*
+*****************************************************************************/
+u32 XAdcPs_GetConfigRegister(XAdcPs *InstancePtr)
+{
+ /*
+ * Assert the arguments.
+ */
+ Xil_AssertNonvoid(InstancePtr != NULL);
+ Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+ /*
+ * Read the Config Register and return the value.
+ */
+ return XAdcPs_ReadReg((InstancePtr)->Config.BaseAddress,
+ XADCPS_CFG_OFFSET);
+}
+
+
+/****************************************************************************/
+/**
+*
+* The functions reads the contents of the Miscellaneous Status Register.
+*
+* @param InstancePtr is a pointer to the XAdcPs instance.
+*
+* @return A 32-bit value representing the contents of the Miscellaneous
+* Status Register. Use the XADCPS_MSTS_*_MASK constants defined
+* in xadcps_hw.h to interpret the returned value.
+*
+* @note None.
+*
+*****************************************************************************/
+u32 XAdcPs_GetMiscStatus(XAdcPs *InstancePtr)
+{
+ /*
+ * Assert the arguments.
+ */
+ Xil_AssertNonvoid(InstancePtr != NULL);
+ Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+ /*
+ * Read the Miscellaneous Status Register and return the value.
+ */
+ return XAdcPs_ReadReg((InstancePtr)->Config.BaseAddress,
+ XADCPS_MSTS_OFFSET);
+}
+
+
+/****************************************************************************/
+/**
+*
+* The functions sets the contents of the Miscellaneous Control register.
+*
+* @param InstancePtr is a pointer to the XAdcPs instance.
+* @param Data is the 32 bit data to be written to the Register.
+*
+* @return None.
+*
+* @note None.
+*
+*****************************************************************************/
+void XAdcPs_SetMiscCtrlRegister(XAdcPs *InstancePtr, u32 Data)
+{
+ /*
+ * Assert the arguments.
+ */
+ Xil_AssertVoid(InstancePtr != NULL);
+ Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+ /*
+ * Write to the Miscellaneous control register Register.
+ */
+ XAdcPs_WriteReg((InstancePtr)->Config.BaseAddress,
+ XADCPS_MCTL_OFFSET, Data);
+}
+
+
+/****************************************************************************/
+/**
+*
+* The functions reads the contents of the Miscellaneous control register.
+*
+* @param InstancePtr is a pointer to the XAdcPs instance.
+*
+* @return A 32-bit value representing the contents of the Config Register.
+* Use the XADCPS_SR_*_MASK constants defined in xadcps_hw.h to
+* interpret the returned value.
+*
+* @note None.
+*
+*****************************************************************************/
+u32 XAdcPs_GetMiscCtrlRegister(XAdcPs *InstancePtr)
+{
+ /*
+ * Assert the arguments.
+ */
+ Xil_AssertNonvoid(InstancePtr != NULL);
+ Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+ /*
+ * Read the Miscellaneous control register and return the value.
+ */
+ return XAdcPs_ReadReg((InstancePtr)->Config.BaseAddress,
+ XADCPS_MCTL_OFFSET);
+}
+
+
+/*****************************************************************************/
+/**
+*
+* This function resets the XADC Hard Macro in the device.
+*
+* @param InstancePtr is a pointer to the Xxadc instance.
+*
+* @return None.
+*
+* @note None.
+*
+******************************************************************************/
+void XAdcPs_Reset(XAdcPs *InstancePtr)
+{
+ /*
+ * Assert the arguments.
+ */
+ Xil_AssertVoid(InstancePtr != NULL);
+ Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+ /*
+ * Generate the reset by Control
+ * register and release from reset
+ */
+ XAdcPs_WriteReg((InstancePtr)->Config.BaseAddress,
+ XADCPS_MCTL_OFFSET, 0x10);
+ XAdcPs_WriteReg((InstancePtr)->Config.BaseAddress,
+ XADCPS_MCTL_OFFSET, 0x00);
+}
+
+
+/****************************************************************************/
+/**
+*
+* Get the ADC converted data for the specified channel.
+*
+* @param InstancePtr is a pointer to the XAdcPs instance.
+* @param Channel is the channel number. Use the XADCPS_CH_* defined in
+* the file xadcps.h.
+* The valid channels are
+* - 0 to 6
+* - 13 to 31
+*
+* @return A 16-bit value representing the ADC converted data for the
+* specified channel. The XADC Monitor/ADC device guarantees
+* a 10 bit resolution for the ADC converted data and data is the
+* 10 MSB bits of the 16 data read from the device.
+*
+* @note The channels 7,8,9 are used for calibration of the device and
+* hence there is no associated data with this channel.
+*
+*****************************************************************************/
+u16 XAdcPs_GetAdcData(XAdcPs *InstancePtr, u8 Channel)
+{
+
+ u32 RegData;
+
+ /*
+ * Assert the arguments.
+ */
+ Xil_AssertNonvoid(InstancePtr != NULL);
+ Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+ Xil_AssertNonvoid((Channel <= XADCPS_CH_VBRAM) ||
+ ((Channel >= XADCPS_CH_VCCPINT) &&
+ (Channel <= XADCPS_CH_AUX_MAX)));
+
+ RegData = XAdcPs_ReadInternalReg(InstancePtr,
+ (XADCPS_TEMP_OFFSET +
+ Channel));
+ return (u16) RegData;
+}
+
+/****************************************************************************/
+/**
+*
+* This function gets the calibration coefficient data for the specified
+* parameter.
+*
+* @param InstancePtr is a pointer to the XAdcPs instance.
+* @param CoeffType specifies the calibration coefficient
+* to be read. Use XADCPS_CALIB_* constants defined in xadcps.h to
+* specify the calibration coefficient to be read.
+*
+* @return A 16-bit value representing the calibration coefficient.
+* The XADC device guarantees a 10 bit resolution for
+* the ADC converted data and data is the 10 MSB bits of the 16
+* data read from the device.
+*
+* @note None.
+*
+*****************************************************************************/
+u16 XAdcPs_GetCalibCoefficient(XAdcPs *InstancePtr, u8 CoeffType)
+{
+ u32 RegData;
+
+ /*
+ * Assert the arguments.
+ */
+ Xil_AssertNonvoid(InstancePtr != NULL);
+ Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+ Xil_AssertNonvoid(CoeffType <= XADCPS_CALIB_GAIN_ERROR_COEFF);
+
+ /*
+ * Read the selected calibration coefficient.
+ */
+ RegData = XAdcPs_ReadInternalReg(InstancePtr,
+ (XADCPS_ADC_A_SUPPLY_CALIB_OFFSET +
+ CoeffType));
+ return (u16) RegData;
+}
+
+/****************************************************************************/
+/**
+*
+* This function reads the Minimum/Maximum measurement for one of the
+* specified parameters. Use XADCPS_MAX_* and XADCPS_MIN_* constants defined in
+* xadcps.h to specify the parameters (Temperature, VccInt, VccAux, VBram,
+* VccPInt, VccPAux and VccPDro).
+*
+* @param InstancePtr is a pointer to the XAdcPs instance.
+* @param MeasurementType specifies the parameter for which the
+* Minimum/Maximum measurement has to be read.
+* Use XADCPS_MAX_* and XADCPS_MIN_* constants defined in xadcps.h to
+* specify the data to be read.
+*
+* @return A 16-bit value representing the maximum/minimum measurement for
+* specified parameter.
+* The XADC device guarantees a 10 bit resolution for
+* the ADC converted data and data is the 10 MSB bits of the 16
+* data read from the device.
+*
+* @note None.
+*
+*****************************************************************************/
+u16 XAdcPs_GetMinMaxMeasurement(XAdcPs *InstancePtr, u8 MeasurementType)
+{
+ u32 RegData;
+ /*
+ * Assert the arguments.
+ */
+ Xil_AssertNonvoid(InstancePtr != NULL);
+ Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+ Xil_AssertNonvoid((MeasurementType <= XADCPS_MAX_VCCPDRO) ||
+ ((MeasurementType >= XADCPS_MIN_VCCPINT) &&
+ (MeasurementType <= XADCPS_MIN_VCCPDRO)))
+
+ /*
+ * Read and return the specified Minimum/Maximum measurement.
+ */
+ RegData = XAdcPs_ReadInternalReg(InstancePtr,
+ (XADCPS_MAX_TEMP_OFFSET +
+ MeasurementType));
+ return (u16) RegData;
+}
+
+/****************************************************************************/
+/**
+*
+* This function sets the number of samples of averaging that is to be done for
+* all the channels in both the single channel mode and sequence mode of
+* operations.
+*
+* @param InstancePtr is a pointer to the XAdcPs instance.
+* @param Average is the number of samples of averaging programmed to the
+* Configuration Register 0. Use the XADCPS_AVG_* definitions defined
+* in xadcps.h file :
+* - XADCPS_AVG_0_SAMPLES for no averaging
+* - XADCPS_AVG_16_SAMPLES for 16 samples of averaging
+* - XADCPS_AVG_64_SAMPLES for 64 samples of averaging
+* - XADCPS_AVG_256_SAMPLES for 256 samples of averaging
+*
+* @return None.
+*
+* @note None.
+*
+*****************************************************************************/
+void XAdcPs_SetAvg(XAdcPs *InstancePtr, u8 Average)
+{
+ u32 RegData;
+
+ /*
+ * Assert the arguments.
+ */
+ Xil_AssertVoid(InstancePtr != NULL);
+ Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+ Xil_AssertVoid(Average <= XADCPS_AVG_256_SAMPLES);
+
+ /*
+ * Write the averaging value into the Configuration Register 0.
+ */
+ RegData = XAdcPs_ReadInternalReg(InstancePtr,
+ XADCPS_CFR0_OFFSET) &
+ (~XADCPS_CFR0_AVG_VALID_MASK);
+
+ RegData |= (((u32) Average << XADCPS_CFR0_AVG_SHIFT));
+ XAdcPs_WriteInternalReg(InstancePtr, XADCPS_CFR0_OFFSET,
+ RegData);
+
+}
+
+/****************************************************************************/
+/**
+*
+* This function returns the number of samples of averaging configured for all
+* the channels in the Configuration Register 0.
+*
+* @param InstancePtr is a pointer to the XAdcPs instance.
+*
+* @return The averaging read from the Configuration Register 0 is
+* returned. Use the XADCPS_AVG_* bit definitions defined in
+* xadcps.h file to interpret the returned value :
+* - XADCPS_AVG_0_SAMPLES means no averaging
+* - XADCPS_AVG_16_SAMPLES means 16 samples of averaging
+* - XADCPS_AVG_64_SAMPLES means 64 samples of averaging
+* - XADCPS_AVG_256_SAMPLES means 256 samples of averaging
+*
+* @note None.
+*
+*****************************************************************************/
+u8 XAdcPs_GetAvg(XAdcPs *InstancePtr)
+{
+ u32 Average;
+
+ /*
+ * Assert the arguments.
+ */
+ Xil_AssertNonvoid(InstancePtr != NULL);
+ Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+ /*
+ * Read the averaging value from the Configuration Register 0.
+ */
+ Average = XAdcPs_ReadInternalReg(InstancePtr,
+ XADCPS_CFR0_OFFSET) & XADCPS_CFR0_AVG_VALID_MASK;
+
+
+ return ((u8) (Average >> XADCPS_CFR0_AVG_SHIFT));
+}
+
+/****************************************************************************/
+/**
+*
+* The function sets the given parameters in the Configuration Register 0 in
+* the single channel mode.
+*
+* @param InstancePtr is a pointer to the XAdcPs instance.
+* @param Channel is the channel number for the singel channel mode.
+* The valid channels are 0 to 6, 8, and 13 to 31.
+* If the external Mux is used then this specifies the channel
+* oonnected to the external Mux. Please read the Device Spec
+* to know which channels are valid.
+* @param IncreaseAcqCycles is a boolean parameter which specifies whether
+* the Acquisition time for the external channels has to be
+* increased to 10 ADCCLK cycles (specify TRUE) or remain at the
+* default 4 ADCCLK cycles (specify FALSE). This parameter is
+* only valid for the external channels.
+* @param IsEventMode specifies whether the operation of the ADC is Event
+* driven or Continuous mode.
+* @param IsDifferentialMode is a boolean parameter which specifies
+* unipolar(specify FALSE) or differential mode (specify TRUE) for
+* the analog inputs. The input mode is only valid for the
+* external channels.
+*
+* @return
+* - XST_SUCCESS if the given values were written successfully to
+* the Configuration Register 0.
+* - XST_FAILURE if the channel sequencer is enabled or the input
+* parameters are not valid for the selected channel.
+*
+* @note
+* - The number of samples for the averaging for all the channels
+* is set by using the function XAdcPs_SetAvg.
+* - The calibration of the device is done by doing a ADC
+* conversion on the calibration channel(channel 8). The input
+* parameters IncreaseAcqCycles, IsDifferentialMode and
+* IsEventMode are not valid for this channel
+*
+*
+*****************************************************************************/
+int XAdcPs_SetSingleChParams(XAdcPs *InstancePtr,
+ u8 Channel,
+ int IncreaseAcqCycles,
+ int IsEventMode,
+ int IsDifferentialMode)
+{
+ u32 RegValue;
+
+ /*
+ * Assert the arguments.
+ */
+ Xil_AssertNonvoid(InstancePtr != NULL);
+ Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+ Xil_AssertNonvoid((Channel <= XADCPS_CH_VBRAM) ||
+ (Channel == XADCPS_CH_ADC_CALIB) ||
+ ((Channel >= XADCPS_CH_VCCPINT) &&
+ (Channel <= XADCPS_CH_AUX_MAX)));
+ Xil_AssertNonvoid((IncreaseAcqCycles == TRUE) ||
+ (IncreaseAcqCycles == FALSE));
+ Xil_AssertNonvoid((IsEventMode == TRUE) || (IsEventMode == FALSE));
+ Xil_AssertNonvoid((IsDifferentialMode == TRUE) ||
+ (IsDifferentialMode == FALSE));
+
+ /*
+ * Check if the device is in single channel mode else return failure
+ */
+ if ((XAdcPs_GetSequencerMode(InstancePtr) !=
+ XADCPS_SEQ_MODE_SINGCHAN)) {
+ return XST_FAILURE;
+ }
+
+ /*
+ * Read the Configuration Register 0.
+ */
+ RegValue = XAdcPs_ReadInternalReg(InstancePtr,
+ XADCPS_CFR0_OFFSET) &
+ XADCPS_CFR0_AVG_VALID_MASK;
+
+ /*
+ * Select the number of acquisition cycles. The acquisition cycles is
+ * only valid for the external channels.
+ */
+ if (IncreaseAcqCycles == TRUE) {
+ if (((Channel >= XADCPS_CH_AUX_MIN) &&
+ (Channel <= XADCPS_CH_AUX_MAX)) ||
+ (Channel == XADCPS_CH_VPVN)){
+ RegValue |= XADCPS_CFR0_ACQ_MASK;
+ } else {
+ return XST_FAILURE;
+ }
+
+ }
+
+ /*
+ * Select the input mode. The input mode is only valid for the
+ * external channels.
+ */
+ if (IsDifferentialMode == TRUE) {
+
+ if (((Channel >= XADCPS_CH_AUX_MIN) &&
+ (Channel <= XADCPS_CH_AUX_MAX)) ||
+ (Channel == XADCPS_CH_VPVN)){
+ RegValue |= XADCPS_CFR0_DU_MASK;
+ } else {
+ return XST_FAILURE;
+ }
+ }
+
+ /*
+ * Select the ADC mode.
+ */
+ if (IsEventMode == TRUE) {
+ RegValue |= XADCPS_CFR0_EC_MASK;
+ }
+
+ /*
+ * Write the given values into the Configuration Register 0.
+ */
+ RegValue |= (Channel & XADCPS_CFR0_CHANNEL_MASK);
+ XAdcPs_WriteInternalReg(InstancePtr, XADCPS_CFR0_OFFSET,
+ RegValue);
+
+ return XST_SUCCESS;
+}
+
+/****************************************************************************/
+/**
+*
+* This function enables the alarm outputs for the specified alarms in the
+* Configuration Register 1.
+*
+* @param InstancePtr is a pointer to the XAdcPs instance.
+* @param AlmEnableMask is the bit-mask of the alarm outputs to be enabled
+* in the Configuration Register 1.
+* Bit positions of 1 will be enabled. Bit positions of 0 will be
+* disabled. This mask is formed by OR'ing XADCPS_CFR1_ALM_*_MASK and
+* XADCPS_CFR1_OT_MASK masks defined in xadcps_hw.h.
+*
+* @return None.
+*
+* @note The implementation of the alarm enables in the Configuration
+* register 1 is such that the alarms for bit positions of 1 will
+* be disabled and alarms for bit positions of 0 will be enabled.
+* The alarm outputs specified by the AlmEnableMask are negated
+* before writing to the Configuration Register 1.
+*
+*
+*****************************************************************************/
+void XAdcPs_SetAlarmEnables(XAdcPs *InstancePtr, u16 AlmEnableMask)
+{
+ u32 RegValue;
+
+ /*
+ * Assert the arguments.
+ */
+ Xil_AssertVoid(InstancePtr != NULL);
+ Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+
+ RegValue = XAdcPs_ReadInternalReg(InstancePtr, XADCPS_CFR1_OFFSET);
+
+ RegValue &= (u32)~XADCPS_CFR1_ALM_ALL_MASK;
+ RegValue |= (~AlmEnableMask & XADCPS_CFR1_ALM_ALL_MASK);
+
+ /*
+ * Enable/disables the alarm enables for the specified alarm bits in the
+ * Configuration Register 1.
+ */
+ XAdcPs_WriteInternalReg(InstancePtr, XADCPS_CFR1_OFFSET,
+ RegValue);
+}
+
+/****************************************************************************/
+/**
+*
+* This function gets the status of the alarm output enables in the
+* Configuration Register 1.
+*
+* @param InstancePtr is a pointer to the XAdcPs instance.
+*
+* @return This is the bit-mask of the enabled alarm outputs in the
+* Configuration Register 1. Use the masks XADCPS_CFR1_ALM*_* and
+* XADCPS_CFR1_OT_MASK defined in xadcps_hw.h to interpret the
+* returned value.
+* Bit positions of 1 indicate that the alarm output is enabled.
+* Bit positions of 0 indicate that the alarm output is disabled.
+*
+*
+* @note The implementation of the alarm enables in the Configuration
+* register 1 is such that alarms for the bit positions of 1 will
+* be disabled and alarms for bit positions of 0 will be enabled.
+* The enabled alarm outputs returned by this function is the
+* negated value of the the data read from the Configuration
+* Register 1.
+*
+*****************************************************************************/
+u16 XAdcPs_GetAlarmEnables(XAdcPs *InstancePtr)
+{
+ u32 RegValue;
+
+ /*
+ * Assert the arguments
+ */
+ Xil_AssertNonvoid(InstancePtr != NULL);
+ Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+ /*
+ * Read the status of alarm output enables from the Configuration
+ * Register 1.
+ */
+ RegValue = XAdcPs_ReadInternalReg(InstancePtr,
+ XADCPS_CFR1_OFFSET) & XADCPS_CFR1_ALM_ALL_MASK;
+ return (u16) (~RegValue & XADCPS_CFR1_ALM_ALL_MASK);
+}
+
+/****************************************************************************/
+/**
+*
+* This function enables the specified calibration in the Configuration
+* Register 1 :
+*
+* - XADCPS_CFR1_CAL_ADC_OFFSET_MASK : Calibration 0 -ADC offset correction
+* - XADCPS_CFR1_CAL_ADC_GAIN_OFFSET_MASK : Calibration 1 -ADC gain and offset
+* correction
+* - XADCPS_CFR1_CAL_PS_OFFSET_MASK : Calibration 2 -Power Supply sensor
+* offset correction
+* - XADCPS_CFR1_CAL_PS_GAIN_OFFSET_MASK : Calibration 3 -Power Supply sensor
+* gain and offset correction
+* - XADCPS_CFR1_CAL_DISABLE_MASK : No Calibration
+*
+* @param InstancePtr is a pointer to the XAdcPs instance.
+* @param Calibration is the Calibration to be applied.
+* Use XADCPS_CFR1_CAL*_* bits defined in xadcps_hw.h.
+* Multiple calibrations can be enabled at a time by oring the
+* XADCPS_CFR1_CAL_ADC_* and XADCPS_CFR1_CAL_PS_* bits.
+* Calibration can be disabled by specifying
+ XADCPS_CFR1_CAL_DISABLE_MASK;
+*
+* @return None.
+*
+* @note None.
+*
+*****************************************************************************/
+void XAdcPs_SetCalibEnables(XAdcPs *InstancePtr, u16 Calibration)
+{
+ u32 RegValue;
+
+ /*
+ * Assert the arguments.
+ */
+ Xil_AssertVoid(InstancePtr != NULL);
+ Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+ Xil_AssertVoid(((Calibration >= XADCPS_CFR1_CAL_ADC_OFFSET_MASK) &&
+ (Calibration <= XADCPS_CFR1_CAL_VALID_MASK)) ||
+ (Calibration == XADCPS_CFR1_CAL_DISABLE_MASK));
+
+ /*
+ * Set the specified calibration in the Configuration Register 1.
+ */
+ RegValue = XAdcPs_ReadInternalReg(InstancePtr,
+ XADCPS_CFR1_OFFSET);
+
+ RegValue &= (~ XADCPS_CFR1_CAL_VALID_MASK);
+ RegValue |= (Calibration & XADCPS_CFR1_CAL_VALID_MASK);
+ XAdcPs_WriteInternalReg(InstancePtr, XADCPS_CFR1_OFFSET,
+ RegValue);
+
+}
+
+/****************************************************************************/
+/**
+*
+* This function reads the value of the calibration enables from the
+* Configuration Register 1.
+*
+* @param InstancePtr is a pointer to the XAdcPs instance.
+*
+* @return The value of the calibration enables in the Configuration
+* Register 1 :
+* - XADCPS_CFR1_CAL_ADC_OFFSET_MASK : ADC offset correction
+* - XADCPS_CFR1_CAL_ADC_GAIN_OFFSET_MASK : ADC gain and offset
+* correction
+* - XADCPS_CFR1_CAL_PS_OFFSET_MASK : Power Supply sensor offset
+* correction
+* - XADCPS_CFR1_CAL_PS_GAIN_OFFSET_MASK : Power Supply sensor
+* gain and offset correction
+* - XADCPS_CFR1_CAL_DISABLE_MASK : No Calibration
+*
+* @note None.
+*
+*****************************************************************************/
+u16 XAdcPs_GetCalibEnables(XAdcPs *InstancePtr)
+{
+ /*
+ * Assert the arguments.
+ */
+ Xil_AssertNonvoid(InstancePtr != NULL);
+ Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+ /*
+ * Read the calibration enables from the Configuration Register 1.
+ */
+ return (u16) XAdcPs_ReadInternalReg(InstancePtr,
+ XADCPS_CFR1_OFFSET) & XADCPS_CFR1_CAL_VALID_MASK;
+
+}
+
+/****************************************************************************/
+/**
+*
+* This function sets the specified Channel Sequencer Mode in the Configuration
+* Register 1 :
+* - Default safe mode (XADCPS_SEQ_MODE_SAFE)
+* - One pass through sequence (XADCPS_SEQ_MODE_ONEPASS)
+* - Continuous channel sequencing (XADCPS_SEQ_MODE_CONTINPASS)
+* - Single Channel/Sequencer off (XADCPS_SEQ_MODE_SINGCHAN)
+* - Simulataneous sampling mode (XADCPS_SEQ_MODE_SIMUL_SAMPLING)
+* - Independent mode (XADCPS_SEQ_MODE_INDEPENDENT)
+*
+* @param InstancePtr is a pointer to the XAdcPs instance.
+* @param SequencerMode is the sequencer mode to be set.
+* Use XADCPS_SEQ_MODE_* bits defined in xadcps.h.
+* @return None.
+*
+* @note Only one of the modes can be enabled at a time. Please
+* read the Spec of the XADC for further information about the
+* sequencer modes.
+*
+*
+*****************************************************************************/
+void XAdcPs_SetSequencerMode(XAdcPs *InstancePtr, u8 SequencerMode)
+{
+ u32 RegValue;
+
+ /*
+ * Assert the arguments.
+ */
+ Xil_AssertVoid(InstancePtr != NULL);
+ Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+ Xil_AssertVoid((SequencerMode <= XADCPS_SEQ_MODE_SIMUL_SAMPLING) ||
+ (SequencerMode == XADCPS_SEQ_MODE_INDEPENDENT));
+
+ /*
+ * Set the specified sequencer mode in the Configuration Register 1.
+ */
+ RegValue = XAdcPs_ReadInternalReg(InstancePtr,
+ XADCPS_CFR1_OFFSET);
+ RegValue &= (~ XADCPS_CFR1_SEQ_VALID_MASK);
+ RegValue |= ((SequencerMode << XADCPS_CFR1_SEQ_SHIFT) &
+ XADCPS_CFR1_SEQ_VALID_MASK);
+ XAdcPs_WriteInternalReg(InstancePtr, XADCPS_CFR1_OFFSET,
+ RegValue);
+
+}
+
+/****************************************************************************/
+/**
+*
+* This function gets the channel sequencer mode from the Configuration
+* Register 1.
+*
+* @param InstancePtr is a pointer to the XAdcPs instance.
+*
+* @return The channel sequencer mode :
+* - XADCPS_SEQ_MODE_SAFE : Default safe mode
+* - XADCPS_SEQ_MODE_ONEPASS : One pass through sequence
+* - XADCPS_SEQ_MODE_CONTINPASS : Continuous channel sequencing
+* - XADCPS_SEQ_MODE_SINGCHAN : Single channel/Sequencer off
+* - XADCPS_SEQ_MODE_SIMUL_SAMPLING : Simulataneous sampling mode
+* - XADCPS_SEQ_MODE_INDEPENDENT : Independent mode
+*
+*
+* @note None.
+*
+*****************************************************************************/
+u8 XAdcPs_GetSequencerMode(XAdcPs *InstancePtr)
+{
+ /*
+ * Assert the arguments.
+ */
+ Xil_AssertNonvoid(InstancePtr != NULL);
+ Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+ /*
+ * Read the channel sequencer mode from the Configuration Register 1.
+ */
+ return ((u8) ((XAdcPs_ReadInternalReg(InstancePtr,
+ XADCPS_CFR1_OFFSET) & XADCPS_CFR1_SEQ_VALID_MASK) >>
+ XADCPS_CFR1_SEQ_SHIFT));
+
+}
+
+/****************************************************************************/
+/**
+*
+* The function sets the frequency of the ADCCLK by configuring the DCLK to
+* ADCCLK ratio in the Configuration Register #2
+*
+* @param InstancePtr is a pointer to the XAdcPs instance.
+* @param Divisor is clock divisor used to derive ADCCLK from DCLK.
+* Valid values of the divisor are
+* - 0 to 255. Values 0, 1, 2 are all mapped to 2.
+* Refer to the device specification for more details
+*
+* @return None.
+*
+* @note - The ADCCLK is an internal clock used by the ADC and is
+* synchronized to the DCLK clock. The ADCCLK is equal to DCLK
+* divided by the user selection in the Configuration Register 2.
+* - There is no Assert on the minimum value of the Divisor.
+*
+*****************************************************************************/
+void XAdcPs_SetAdcClkDivisor(XAdcPs *InstancePtr, u8 Divisor)
+{
+ /*
+ * Assert the arguments.
+ */
+ Xil_AssertVoid(InstancePtr != NULL);
+ Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+ /*
+ * Write the divisor value into the Configuration Register #2.
+ */
+ XAdcPs_WriteInternalReg(InstancePtr, XADCPS_CFR2_OFFSET,
+ Divisor << XADCPS_CFR2_CD_SHIFT);
+
+}
+
+/****************************************************************************/
+/**
+*
+* The function gets the ADCCLK divisor from the Configuration Register 2.
+*
+* @param InstancePtr is a pointer to the XAdcPs instance.
+*
+* @return The divisor read from the Configuration Register 2.
+*
+* @note The ADCCLK is an internal clock used by the ADC and is
+* synchronized to the DCLK clock. The ADCCLK is equal to DCLK
+* divided by the user selection in the Configuration Register 2.
+*
+*****************************************************************************/
+u8 XAdcPs_GetAdcClkDivisor(XAdcPs *InstancePtr)
+{
+ u16 Divisor;
+
+ /*
+ * Assert the arguments.
+ */
+ Xil_AssertNonvoid(InstancePtr != NULL);
+ Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+ /*
+ * Read the divisor value from the Configuration Register 2.
+ */
+ Divisor = (u16) XAdcPs_ReadInternalReg(InstancePtr,
+ XADCPS_CFR2_OFFSET);
+
+ return (u8) (Divisor >> XADCPS_CFR2_CD_SHIFT);
+}
+
+/****************************************************************************/
+/**
+*
+* This function enables the specified channels in the ADC Channel Selection
+* Sequencer Registers. The sequencer must be disabled before writing to these
+* regsiters.
+*
+* @param InstancePtr is a pointer to the XAdcPs instance.
+* @param ChEnableMask is the bit mask of all the channels to be enabled.
+* Use XADCPS_SEQ_CH__* defined in xadcps_hw.h to specify the Channel
+* numbers. Bit masks of 1 will be enabled and bit mask of 0 will
+* be disabled.
+* The ChEnableMask is a 32 bit mask that is written to the two
+* 16 bit ADC Channel Selection Sequencer Registers.
+*
+* @return
+* - XST_SUCCESS if the given values were written successfully to
+* the ADC Channel Selection Sequencer Registers.
+* - XST_FAILURE if the channel sequencer is enabled.
+*
+* @note None
+*
+*****************************************************************************/
+int XAdcPs_SetSeqChEnables(XAdcPs *InstancePtr, u32 ChEnableMask)
+{
+ /*
+ * Assert the arguments.
+ */
+ Xil_AssertNonvoid(InstancePtr != NULL);
+ Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+ /*
+ * The sequencer must be disabled for writing any of these registers
+ * Return XST_FAILURE if the channel sequencer is enabled.
+ */
+ if ((XAdcPs_GetSequencerMode(InstancePtr) != XADCPS_SEQ_MODE_SAFE)) {
+ return XST_FAILURE;
+ }
+
+ /*
+ * Enable the specified channels in the ADC Channel Selection Sequencer
+ * Registers.
+ */
+ XAdcPs_WriteInternalReg(InstancePtr,
+ XADCPS_SEQ00_OFFSET,
+ (ChEnableMask & XADCPS_SEQ00_CH_VALID_MASK));
+
+ XAdcPs_WriteInternalReg(InstancePtr,
+ XADCPS_SEQ01_OFFSET,
+ (ChEnableMask >> XADCPS_SEQ_CH_AUX_SHIFT) &
+ XADCPS_SEQ01_CH_VALID_MASK);
+
+ return XST_SUCCESS;
+}
+
+/****************************************************************************/
+/**
+*
+* This function gets the channel enable bits status from the ADC Channel
+* Selection Sequencer Registers.
+*
+* @param InstancePtr is a pointer to the XAdcPs instance.
+*
+* @return Gets the channel enable bits. Use XADCPS_SEQ_CH__* defined in
+* xadcps_hw.h to interpret the Channel numbers. Bit masks of 1
+* are the channels that are enabled and bit mask of 0 are
+* the channels that are disabled.
+*
+* @return None
+*
+* @note None
+*
+*****************************************************************************/
+u32 XAdcPs_GetSeqChEnables(XAdcPs *InstancePtr)
+{
+ u32 RegValEnable;
+
+ /*
+ * Assert the arguments.
+ */
+ Xil_AssertNonvoid(InstancePtr != NULL);
+ Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+ /*
+ * Read the channel enable bits for all the channels from the ADC
+ * Channel Selection Register.
+ */
+ RegValEnable = XAdcPs_ReadInternalReg(InstancePtr,
+ XADCPS_SEQ00_OFFSET) &
+ XADCPS_SEQ00_CH_VALID_MASK;
+ RegValEnable |= (XAdcPs_ReadInternalReg(InstancePtr,
+ XADCPS_SEQ01_OFFSET) &
+ XADCPS_SEQ01_CH_VALID_MASK) <<
+ XADCPS_SEQ_CH_AUX_SHIFT;
+
+
+ return RegValEnable;
+}
+
+/****************************************************************************/
+/**
+*
+* This function enables the averaging for the specified channels in the ADC
+* Channel Averaging Enable Sequencer Registers. The sequencer must be disabled
+* before writing to these regsiters.
+*
+* @param InstancePtr is a pointer to the XAdcPs instance.
+* @param AvgEnableChMask is the bit mask of all the channels for which
+* averaging is to be enabled. Use XADCPS_SEQ_CH__* defined in
+* xadcps_hw.h to specify the Channel numbers. Averaging will be
+* enabled for bit masks of 1 and disabled for bit mask of 0.
+* The AvgEnableChMask is a 32 bit mask that is written to the two
+* 16 bit ADC Channel Averaging Enable Sequencer Registers.
+*
+* @return
+* - XST_SUCCESS if the given values were written successfully to
+* the ADC Channel Averaging Enables Sequencer Registers.
+* - XST_FAILURE if the channel sequencer is enabled.
+*
+* @note None
+*
+*****************************************************************************/
+int XAdcPs_SetSeqAvgEnables(XAdcPs *InstancePtr, u32 AvgEnableChMask)
+{
+ /*
+ * Assert the arguments.
+ */
+ Xil_AssertNonvoid(InstancePtr != NULL);
+ Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+ /*
+ * The sequencer must be disabled for writing any of these registers
+ * Return XST_FAILURE if the channel sequencer is enabled.
+ */
+ if ((XAdcPs_GetSequencerMode(InstancePtr) != XADCPS_SEQ_MODE_SAFE)) {
+ return XST_FAILURE;
+ }
+
+ /*
+ * Enable/disable the averaging for the specified channels in the
+ * ADC Channel Averaging Enables Sequencer Registers.
+ */
+ XAdcPs_WriteInternalReg(InstancePtr,
+ XADCPS_SEQ02_OFFSET,
+ (AvgEnableChMask & XADCPS_SEQ02_CH_VALID_MASK));
+
+ XAdcPs_WriteInternalReg(InstancePtr,
+ XADCPS_SEQ03_OFFSET,
+ (AvgEnableChMask >> XADCPS_SEQ_CH_AUX_SHIFT) &
+ XADCPS_SEQ03_CH_VALID_MASK);
+
+ return XST_SUCCESS;
+}
+
+/****************************************************************************/
+/**
+*
+* This function returns the channels for which the averaging has been enabled
+* in the ADC Channel Averaging Enables Sequencer Registers.
+*
+* @param InstancePtr is a pointer to the XAdcPs instance.
+*
+* @returns The status of averaging (enabled/disabled) for all the channels.
+* Use XADCPS_SEQ_CH__* defined in xadcps_hw.h to interpret the
+* Channel numbers. Bit masks of 1 are the channels for which
+* averaging is enabled and bit mask of 0 are the channels for
+* averaging is disabled
+*
+* @note None
+*
+*****************************************************************************/
+u32 XAdcPs_GetSeqAvgEnables(XAdcPs *InstancePtr)
+{
+ u32 RegValAvg;
+
+ /*
+ * Assert the arguments.
+ */
+ Xil_AssertNonvoid(InstancePtr != NULL);
+ Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+ /*
+ * Read the averaging enable status for all the channels from the
+ * ADC Channel Averaging Enables Sequencer Registers.
+ */
+ RegValAvg = XAdcPs_ReadInternalReg(InstancePtr,
+ XADCPS_SEQ02_OFFSET) & XADCPS_SEQ02_CH_VALID_MASK;
+ RegValAvg |= (XAdcPs_ReadInternalReg(InstancePtr,
+ XADCPS_SEQ03_OFFSET) & XADCPS_SEQ03_CH_VALID_MASK) <<
+ XADCPS_SEQ_CH_AUX_SHIFT;
+
+ return RegValAvg;
+}
+
+/****************************************************************************/
+/**
+*
+* This function sets the Analog input mode for the specified channels in the ADC
+* Channel Analog-Input Mode Sequencer Registers. The sequencer must be disabled
+* before writing to these regsiters.
+*
+* @param InstancePtr is a pointer to the XAdcPs instance.
+* @param InputModeChMask is the bit mask of all the channels for which
+* the input mode is differential mode. Use XADCPS_SEQ_CH__* defined
+* in xadcps_hw.h to specify the channel numbers. Differential
+* input mode will be set for bit masks of 1 and unipolar input
+* mode for bit masks of 0.
+* The InputModeChMask is a 32 bit mask that is written to the two
+* 16 bit ADC Channel Analog-Input Mode Sequencer Registers.
+*
+* @return
+* - XST_SUCCESS if the given values were written successfully to
+* the ADC Channel Analog-Input Mode Sequencer Registers.
+* - XST_FAILURE if the channel sequencer is enabled.
+*
+* @note None
+*
+*****************************************************************************/
+int XAdcPs_SetSeqInputMode(XAdcPs *InstancePtr, u32 InputModeChMask)
+{
+ /*
+ * Assert the arguments.
+ */
+ Xil_AssertNonvoid(InstancePtr != NULL);
+ Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+ /*
+ * The sequencer must be disabled for writing any of these registers
+ * Return XST_FAILURE if the channel sequencer is enabled.
+ */
+ if ((XAdcPs_GetSequencerMode(InstancePtr) != XADCPS_SEQ_MODE_SAFE)) {
+ return XST_FAILURE;
+ }
+
+ /*
+ * Set the input mode for the specified channels in the ADC Channel
+ * Analog-Input Mode Sequencer Registers.
+ */
+ XAdcPs_WriteInternalReg(InstancePtr,
+ XADCPS_SEQ04_OFFSET,
+ (InputModeChMask & XADCPS_SEQ04_CH_VALID_MASK));
+
+ XAdcPs_WriteInternalReg(InstancePtr,
+ XADCPS_SEQ05_OFFSET,
+ (InputModeChMask >> XADCPS_SEQ_CH_AUX_SHIFT) &
+ XADCPS_SEQ05_CH_VALID_MASK);
+
+ return XST_SUCCESS;
+}
+
+/****************************************************************************/
+/**
+*
+* This function gets the Analog input mode for all the channels from
+* the ADC Channel Analog-Input Mode Sequencer Registers.
+*
+* @param InstancePtr is a pointer to the XAdcPs instance.
+*
+* @returns The input mode for all the channels.
+* Use XADCPS_SEQ_CH_* defined in xadcps_hw.h to interpret the
+* Channel numbers. Bit masks of 1 are the channels for which
+* input mode is differential and bit mask of 0 are the channels
+* for which input mode is unipolar.
+*
+* @note None.
+*
+*****************************************************************************/
+u32 XAdcPs_GetSeqInputMode(XAdcPs *InstancePtr)
+{
+ u32 InputMode;
+
+ /*
+ * Assert the arguments.
+ */
+ Xil_AssertNonvoid(InstancePtr != NULL);
+ Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+ /*
+ * Get the input mode for all the channels from the ADC Channel
+ * Analog-Input Mode Sequencer Registers.
+ */
+ InputMode = XAdcPs_ReadInternalReg(InstancePtr,
+ XADCPS_SEQ04_OFFSET) &
+ XADCPS_SEQ04_CH_VALID_MASK;
+ InputMode |= (XAdcPs_ReadInternalReg(InstancePtr,
+ XADCPS_SEQ05_OFFSET) &
+ XADCPS_SEQ05_CH_VALID_MASK) <<
+ XADCPS_SEQ_CH_AUX_SHIFT;
+
+ return InputMode;
+}
+
+/****************************************************************************/
+/**
+*
+* This function sets the number of Acquisition cycles in the ADC Channel
+* Acquisition Time Sequencer Registers. The sequencer must be disabled
+* before writing to these regsiters.
+*
+* @param InstancePtr is a pointer to the XAdcPs instance.
+* @param AcqCyclesChMask is the bit mask of all the channels for which
+* the number of acquisition cycles is to be extended.
+* Use XADCPS_SEQ_CH__* defined in xadcps_hw.h to specify the Channel
+* numbers. Acquisition cycles will be extended to 10 ADCCLK cycles
+* for bit masks of 1 and will be the default 4 ADCCLK cycles for
+* bit masks of 0.
+* The AcqCyclesChMask is a 32 bit mask that is written to the two
+* 16 bit ADC Channel Acquisition Time Sequencer Registers.
+*
+* @return
+* - XST_SUCCESS if the given values were written successfully to
+* the Channel Sequencer Registers.
+* - XST_FAILURE if the channel sequencer is enabled.
+*
+* @note None.
+*
+*****************************************************************************/
+int XAdcPs_SetSeqAcqTime(XAdcPs *InstancePtr, u32 AcqCyclesChMask)
+{
+ /*
+ * Assert the arguments.
+ */
+ Xil_AssertNonvoid(InstancePtr != NULL);
+ Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+ /*
+ * The sequencer must be disabled for writing any of these registers
+ * Return XST_FAILURE if the channel sequencer is enabled.
+ */
+ if ((XAdcPs_GetSequencerMode(InstancePtr) !=
+ XADCPS_SEQ_MODE_SAFE)) {
+ return XST_FAILURE;
+ }
+
+ /*
+ * Set the Acquisition time for the specified channels in the
+ * ADC Channel Acquisition Time Sequencer Registers.
+ */
+ XAdcPs_WriteInternalReg(InstancePtr,
+ XADCPS_SEQ06_OFFSET,
+ (AcqCyclesChMask & XADCPS_SEQ06_CH_VALID_MASK));
+
+ XAdcPs_WriteInternalReg(InstancePtr,
+ XADCPS_SEQ07_OFFSET,
+ (AcqCyclesChMask >> XADCPS_SEQ_CH_AUX_SHIFT) &
+ XADCPS_SEQ07_CH_VALID_MASK);
+
+ return XST_SUCCESS;
+}
+
+/****************************************************************************/
+/**
+*
+* This function gets the status of acquisition from the ADC Channel Acquisition
+* Time Sequencer Registers.
+*
+* @param InstancePtr is a pointer to the XAdcPs instance.
+*
+* @returns The acquisition time for all the channels.
+* Use XADCPS_SEQ_CH__* defined in xadcps_hw.h to interpret the
+* Channel numbers. Bit masks of 1 are the channels for which
+* acquisition cycles are extended and bit mask of 0 are the
+* channels for which acquisition cycles are not extended.
+*
+* @note None
+*
+*****************************************************************************/
+u32 XAdcPs_GetSeqAcqTime(XAdcPs *InstancePtr)
+{
+ u32 RegValAcq;
+
+ /*
+ * Assert the arguments.
+ */
+ Xil_AssertNonvoid(InstancePtr != NULL);
+ Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+ /*
+ * Get the Acquisition cycles for the specified channels from the ADC
+ * Channel Acquisition Time Sequencer Registers.
+ */
+ RegValAcq = XAdcPs_ReadInternalReg(InstancePtr,
+ XADCPS_SEQ06_OFFSET) &
+ XADCPS_SEQ06_CH_VALID_MASK;
+ RegValAcq |= (XAdcPs_ReadInternalReg(InstancePtr,
+ XADCPS_SEQ07_OFFSET) &
+ XADCPS_SEQ07_CH_VALID_MASK) <<
+ XADCPS_SEQ_CH_AUX_SHIFT;
+
+ return RegValAcq;
+}
+
+/****************************************************************************/
+/**
+*
+* This functions sets the contents of the given Alarm Threshold Register.
+*
+* @param InstancePtr is a pointer to the XAdcPs instance.
+* @param AlarmThrReg is the index of an Alarm Threshold Register to
+* be set. Use XADCPS_ATR_* constants defined in xadcps.h to
+* specify the index.
+* @param Value is the 16-bit threshold value to write into the register.
+*
+* @return None.
+*
+* @note Use XAdcPs_SetOverTemp() to set the Over Temperature upper
+* threshold value.
+*
+*****************************************************************************/
+void XAdcPs_SetAlarmThreshold(XAdcPs *InstancePtr, u8 AlarmThrReg, u16 Value)
+{
+
+ /*
+ * Assert the arguments.
+ */
+ Xil_AssertVoid(InstancePtr != NULL);
+ Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+ Xil_AssertVoid(AlarmThrReg <= XADCPS_ATR_VCCPDRO_LOWER);
+
+ /*
+ * Write the value into the specified Alarm Threshold Register.
+ */
+ XAdcPs_WriteInternalReg(InstancePtr, XADCPS_ATR_TEMP_UPPER_OFFSET +
+ AlarmThrReg,Value);
+
+}
+
+/****************************************************************************/
+/**
+*
+* This function returns the contents of the specified Alarm Threshold Register.
+*
+* @param InstancePtr is a pointer to the XAdcPs instance.
+* @param AlarmThrReg is the index of an Alarm Threshold Register
+* to be read. Use XADCPS_ATR_* constants defined in xadcps_hw.h
+* to specify the index.
+*
+* @return A 16-bit value representing the contents of the selected Alarm
+* Threshold Register.
+*
+* @note None.
+*
+*****************************************************************************/
+u16 XAdcPs_GetAlarmThreshold(XAdcPs *InstancePtr, u8 AlarmThrReg)
+{
+ u32 RegData;
+ /*
+ * Assert the arguments.
+ */
+ Xil_AssertNonvoid(InstancePtr != NULL);
+ Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+ Xil_AssertNonvoid(AlarmThrReg <= XADCPS_ATR_VCCPDRO_LOWER);
+
+ /*
+ * Read the specified Alarm Threshold Register and return
+ * the value
+ */
+ RegData = XAdcPs_ReadInternalReg(InstancePtr,
+ (XADCPS_ATR_TEMP_UPPER_OFFSET + AlarmThrReg));
+
+ return (u16) RegData;
+}
+
+
+/****************************************************************************/
+/**
+*
+* This function enables programming of the powerdown temperature for the
+* OverTemp signal in the OT Powerdown register.
+*
+* @param InstancePtr is a pointer to the XAdcPs instance.
+*
+* @return None.
+*
+* @note None.
+*
+*****************************************************************************/
+void XAdcPs_EnableUserOverTemp(XAdcPs *InstancePtr)
+{
+ u16 OtUpper;
+
+ /*
+ * Assert the arguments.
+ */
+ Xil_AssertVoid(InstancePtr != NULL);
+ Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+ /*
+ * Read the OT upper Alarm Threshold Register.
+ */
+ OtUpper = XAdcPs_ReadInternalReg(InstancePtr,
+ XADCPS_ATR_OT_UPPER_OFFSET);
+ OtUpper &= ~(XADCPS_ATR_OT_UPPER_ENB_MASK);
+
+ /*
+ * Preserve the powerdown value and write OT enable value the into the
+ * OT Upper Alarm Threshold Register.
+ */
+ OtUpper |= XADCPS_ATR_OT_UPPER_ENB_VAL;
+ XAdcPs_WriteInternalReg(InstancePtr,
+ XADCPS_ATR_OT_UPPER_OFFSET, OtUpper);
+}
+
+/****************************************************************************/
+/**
+*
+* This function disables programming of the powerdown temperature for the
+* OverTemp signal in the OT Powerdown register.
+*
+* @param InstancePtr is a pointer to the XAdcPs instance.
+*
+* @return None.
+*
+* @note None.
+*
+*
+*****************************************************************************/
+void XAdcPs_DisableUserOverTemp(XAdcPs *InstancePtr)
+{
+ u16 OtUpper;
+
+ /*
+ * Assert the arguments.
+ */
+ Xil_AssertVoid(InstancePtr != NULL);
+ Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+ /*
+ * Read the OT Upper Alarm Threshold Register.
+ */
+ OtUpper = XAdcPs_ReadInternalReg(InstancePtr,
+ XADCPS_ATR_OT_UPPER_OFFSET);
+ OtUpper &= ~(XADCPS_ATR_OT_UPPER_ENB_MASK);
+
+ XAdcPs_WriteInternalReg(InstancePtr,
+ XADCPS_ATR_OT_UPPER_OFFSET, OtUpper);
+}
+
+
+/****************************************************************************/
+/**
+*
+* The function enables the Event mode or Continuous mode in the sequencer mode.
+*
+* @param InstancePtr is a pointer to the XAdcPs instance.
+* @param IsEventMode is a boolean parameter that specifies continuous
+* sampling (specify FALSE) or event driven sampling mode (specify
+* TRUE) for the given channel.
+*
+* @return None.
+*
+* @note None.
+*
+*****************************************************************************/
+void XAdcPs_SetSequencerEvent(XAdcPs *InstancePtr, int IsEventMode)
+{
+ u32 RegValue;
+
+ /*
+ * Assert the arguments.
+ */
+ Xil_AssertVoid(InstancePtr != NULL);
+ Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+ Xil_AssertVoid((IsEventMode == TRUE) || (IsEventMode == FALSE));
+
+ /*
+ * Read the Configuration Register 0.
+ */
+ RegValue = XAdcPs_ReadInternalReg(InstancePtr,
+ XADCPS_CFR0_OFFSET) &
+ (~XADCPS_CFR0_EC_MASK);
+
+ /*
+ * Set the ADC mode.
+ */
+ if (IsEventMode == TRUE) {
+ RegValue |= XADCPS_CFR0_EC_MASK;
+ } else {
+ RegValue &= ~XADCPS_CFR0_EC_MASK;
+ }
+
+ XAdcPs_WriteInternalReg(InstancePtr, XADCPS_CFR0_OFFSET,
+ RegValue);
+}
+
+
+/****************************************************************************/
+/**
+*
+* This function returns the sampling mode.
+*
+* @param InstancePtr is a pointer to the XAdcPs instance.
+*
+* @return The sampling mode
+* - 0 specifies continuous sampling
+* - 1 specifies event driven sampling mode
+*
+* @note None.
+*
+*****************************************************************************/
+int XAdcPs_GetSamplingMode(XAdcPs *InstancePtr)
+{
+ u32 Mode;
+
+ /*
+ * Assert the arguments.
+ */
+ Xil_AssertNonvoid(InstancePtr != NULL);
+ Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+ /*
+ * Read the sampling mode from the Configuration Register 0.
+ */
+ Mode = XAdcPs_ReadInternalReg(InstancePtr,
+ XADCPS_CFR0_OFFSET) &
+ XADCPS_CFR0_EC_MASK;
+ if (Mode) {
+
+ return 1;
+ }
+
+ return (0);
+}
+
+
+/****************************************************************************/
+/**
+*
+* This function sets the External Mux mode.
+*
+* @param InstancePtr is a pointer to the XAdcPs instance.
+* @param MuxMode specifies whether External Mux is used
+* - FALSE specifies NO external MUX
+* - TRUE specifies External Mux is used
+* @param Channel specifies the channel to be used for the
+* external Mux. Please read the Device Spec for which
+* channels are valid for which mode.
+*
+* @return None.
+*
+* @note There is no Assert in this function for checking the channel
+* number if the external Mux is used. The user should provide a
+* valid channel number.
+*
+*****************************************************************************/
+void XAdcPs_SetMuxMode(XAdcPs *InstancePtr, int MuxMode, u8 Channel)
+{
+ u32 RegValue;
+
+ /*
+ * Assert the arguments.
+ */
+ Xil_AssertVoid(InstancePtr != NULL);
+ Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+ Xil_AssertVoid((MuxMode == TRUE) || (MuxMode == FALSE));
+
+ /*
+ * Read the Configuration Register 0.
+ */
+ RegValue = XAdcPs_ReadInternalReg(InstancePtr,
+ XADCPS_CFR0_OFFSET) &
+ (~XADCPS_CFR0_MUX_MASK);
+ /*
+ * Select the Mux mode and the channel to be used.
+ */
+ if (MuxMode == TRUE) {
+ RegValue |= XADCPS_CFR0_MUX_MASK;
+ RegValue |= (Channel & XADCPS_CFR0_CHANNEL_MASK);
+
+ }
+
+ /*
+ * Write the mux mode into the Configuration Register 0.
+ */
+ XAdcPs_WriteInternalReg(InstancePtr, XADCPS_CFR0_OFFSET,
+ RegValue);
+}
+
+
+/****************************************************************************/
+/**
+*
+* This function sets the Power Down mode.
+*
+* @param InstancePtr is a pointer to the XAdcPs instance.
+* @param Mode specifies the Power Down Mode
+* - XADCPS_PD_MODE_NONE specifies NO Power Down (Both ADC A and
+* ADC B are enabled)
+* - XADCPS_PD_MODE_ADCB specfies the Power Down of ADC B
+* - XADCPS_PD_MODE_XADC specifies the Power Down of
+* both ADC A and ADC B.
+*
+* @return None.
+*
+* @note None.
+*
+*****************************************************************************/
+void XAdcPs_SetPowerdownMode(XAdcPs *InstancePtr, u32 Mode)
+{
+ u32 RegValue;
+
+ /*
+ * Assert the arguments.
+ */
+ Xil_AssertVoid(InstancePtr != NULL);
+ Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+ Xil_AssertVoid(Mode < XADCPS_PD_MODE_XADC);
+
+
+ /*
+ * Read the Configuration Register 2.
+ */
+ RegValue = XAdcPs_ReadInternalReg(InstancePtr,
+ XADCPS_CFR2_OFFSET) &
+ (~XADCPS_CFR2_PD_MASK);
+ /*
+ * Select the Power Down mode.
+ */
+ RegValue |= (Mode << XADCPS_CFR2_PD_SHIFT);
+
+ XAdcPs_WriteInternalReg(InstancePtr, XADCPS_CFR2_OFFSET,
+ RegValue);
+}
+
+/****************************************************************************/
+/**
+*
+* This function gets the Power Down mode.
+*
+* @param InstancePtr is a pointer to the XAdcPs instance.
+*
+* @return Mode specifies the Power Down Mode
+* - XADCPS_PD_MODE_NONE specifies NO Power Down (Both ADC A and
+* ADC B are enabled)
+* - XADCPS_PD_MODE_ADCB specfies the Power Down of ADC B
+* - XADCPS_PD_MODE_XADC specifies the Power Down of
+* both ADC A and ADC B.
+*
+* @note None.
+*
+*****************************************************************************/
+u32 XAdcPs_GetPowerdownMode(XAdcPs *InstancePtr)
+{
+ u32 RegValue;
+
+ /*
+ * Assert the arguments.
+ */
+ Xil_AssertNonvoid(InstancePtr != NULL);
+ Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+ /*
+ * Read the Power Down Mode.
+ */
+ RegValue = XAdcPs_ReadInternalReg(InstancePtr,
+ XADCPS_CFR2_OFFSET) &
+ (~XADCPS_CFR2_PD_MASK);
+ /*
+ * Return the Power Down mode.
+ */
+ return (RegValue >> XADCPS_CFR2_PD_SHIFT);
+
+}
+
+/****************************************************************************/
+/**
+*
+* This function is used for writing to XADC Registers using the command FIFO.
+*
+* @param InstancePtr is a pointer to the XAdcPs instance.
+* @param RegOffset is the offset of the XADC register to be written.
+* @param Data is the data to be written.
+*
+* @return None.
+*
+* @note None.
+*
+*
+*****************************************************************************/
+void XAdcPs_WriteInternalReg(XAdcPs *InstancePtr, u32 RegOffset, u32 Data)
+{
+ u32 RegData;
+
+ /*
+ * Write the Data into the FIFO Register.
+ */
+ RegData = XAdcPs_FormatWriteData(RegOffset, Data, TRUE);
+
+ XAdcPs_WriteFifo(InstancePtr, RegData);
+
+ /* Read the Read FIFO after any write since for each write
+ * one location of Read FIFO gets updated
+ */
+ XAdcPs_ReadFifo(InstancePtr);
+
+}
+
+
+/****************************************************************************/
+/**
+*
+* This function is used for reading from the XADC Registers using the Data FIFO.
+*
+* @param InstancePtr is a pointer to the XAdcPs instance.
+* @param RegOffset is the offset of the XADC register to be read.
+*
+* @return Data read from the FIFO
+*
+* @note None.
+*
+*
+*****************************************************************************/
+u32 XAdcPs_ReadInternalReg(XAdcPs *InstancePtr, u32 RegOffset)
+{
+
+ u32 RegData;
+
+ RegData = XAdcPs_FormatWriteData(RegOffset, 0x0, FALSE);
+
+ /* Read cmd to FIFO*/
+ XAdcPs_WriteFifo(InstancePtr, RegData);
+
+ /* Do a Dummy read */
+ RegData = XAdcPs_ReadFifo(InstancePtr);
+
+ /* Do a Dummy write to get the actual read */
+ XAdcPs_WriteFifo(InstancePtr, RegData);
+
+ /* Do the Actual read */
+ RegData = XAdcPs_ReadFifo(InstancePtr);
+
+ return RegData;
+
+}
+/** @} */
diff --git a/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/xadcps_v2_3/src/xadcps.h b/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/xadcps_v2_3/src/xadcps.h
new file mode 100644
index 0000000..ef4fde4
--- /dev/null
+++ b/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/xadcps_v2_3/src/xadcps.h
@@ -0,0 +1,587 @@
+/******************************************************************************
+*
+* Copyright (C) 2011 - 2014 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+* THE SOFTWARE.
+*
+*
+*
+******************************************************************************/
+/****************************************************************************/
+/**
+*
+* @file xadcps.h
+* @addtogroup xadcps_v2_3
+* @{
+* @details
+*
+* The XAdcPs driver supports the Xilinx XADC/ADC device.
+*
+* The XADC/ADC device has the following features:
+* - 10-bit, 200-KSPS (kilo samples per second)
+* Analog-to-Digital Converter (ADC)
+* - Monitoring of on-chip supply voltages and temperature
+* - 1 dedicated differential analog-input pair and
+* 16 auxiliary differential analog-input pairs
+* - Automatic alarms based on user defined limits for the on-chip
+* supply voltages and temperature
+* - Automatic Channel Sequencer, programmable averaging, programmable
+* acquisition time for the external inputs, unipolar or differential
+* input selection for the external inputs
+* - Inbuilt Calibration
+* - Optional interrupt request generation
+*
+*
+* The user should refer to the hardware device specification for detailed
+* information about the device.
+*
+* This header file contains the prototypes of driver functions that can
+* be used to access the XADC/ADC device.
+*
+*
+* <b> XADC Channel Sequencer Modes </b>
+*
+* The XADC Channel Sequencer supports the following operating modes:
+*
+* - <b> Default </b>: This is the default mode after power up.
+* In this mode of operation the XADC operates in
+* a sequence mode, monitoring the on chip sensors:
+* Temperature, VCCINT, and VCCAUX.
+* - <b> One pass through sequence </b>: In this mode the XADC
+* converts the channels enabled in the Sequencer Channel Enable
+* registers for a single pass and then stops.
+* - <b> Continuous cycling of sequence </b>: In this mode the XADC
+* converts the channels enabled in the Sequencer Channel Enable
+* registers continuously.
+* - <b> Single channel mode</b>: In this mode the XADC Channel
+* Sequencer is disabled and the XADC operates in a
+* Single Channel Mode.
+* The XADC can operate either in a Continuous or Event
+* driven sampling mode in the single channel mode.
+* - <b> Simultaneous Sampling Mode</b>: In this mode the XADC Channel
+* Sequencer will automatically sequence through eight fixed pairs
+* of auxiliary analog input channels for simulataneous conversion.
+* - <b> Independent ADC mode</b>: In this mode the first ADC (A) is used to
+* is used to implement a fixed monitoring mode similar to the
+* default mode but the alarm fucntions ar eenabled.
+* The second ADC (B) is available to be used with external analog
+* input channels only.
+*
+* Read the XADC spec for more information about the sequencer modes.
+*
+* <b> Initialization and Configuration </b>
+*
+* The device driver enables higher layer software (e.g., an application) to
+* communicate to the XADC/ADC device.
+*
+* XAdcPs_CfgInitialize() API is used to initialize the XADC/ADC
+* device. The user needs to first call the XAdcPs_LookupConfig() API which
+* returns the Configuration structure pointer which is passed as a parameter to
+* the XAdcPs_CfgInitialize() API.
+*
+*
+* <b>Interrupts</b>
+*
+* The XADC/ADC device supports interrupt driven mode and the default
+* operation mode is polling mode.
+*
+* The interrupt mode is available only if hardware is configured to support
+* interrupts.
+*
+* This driver does not provide a Interrupt Service Routine (ISR) for the device.
+* It is the responsibility of the application to provide one if needed. Refer to
+* the interrupt example provided with this driver for details on using the
+* device in interrupt mode.
+*
+*
+* <b> Virtual Memory </b>
+*
+* This driver supports Virtual Memory. The RTOS is responsible for calculating
+* the correct device base address in Virtual Memory space.
+*
+*
+* <b> Threads </b>
+*
+* This driver is not thread safe. Any needs for threads or thread mutual
+* exclusion must be satisfied by the layer above this driver.
+*
+*
+* <b> Asserts </b>
+*
+* Asserts are used within all Xilinx drivers to enforce constraints on argument
+* values. Asserts can be turned off on a system-wide basis by defining, at
+* compile time, the NDEBUG identifier. By default, asserts are turned on and it
+* is recommended that users leave asserts on during development.
+*
+*
+* <b> Building the driver </b>
+*
+* The XAdcPs driver is composed of several source files. This allows the user
+* to build and link only those parts of the driver that are necessary.
+*
+* <b> Limitations of the driver </b>
+*
+* XADC/ADC device can be accessed through the JTAG port and the PLB
+* interface. The driver implementation does not support the simultaneous access
+* of the device by both these interfaces. The user has to care of this situation
+* in the user application code.
+*
+* <br><br>
+*
+* <pre>
+*
+* MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ----- ----- -------- -----------------------------------------------------
+* 1.00a ssb 12/22/11 First release based on the XPS/AXI xadc driver
+* 1.01a bss 02/18/13 Modified XAdcPs_SetSeqChEnables,XAdcPs_SetSeqAvgEnables
+* XAdcPs_SetSeqInputMode and XAdcPs_SetSeqAcqTime APIs
+* in xadcps.c to fix CR #693371
+* 1.03a bss 11/01/13 Modified xadcps_hw.h to use correct Register offsets
+* CR#749687
+* 2.1 bss 08/05/14 Added declarations for XAdcPs_SetSequencerEvent,
+* XAdcPs_GetSamplingMode, XAdcPs_SetMuxMode,
+* XAdcPs_SetPowerdownMode and XAdcPs_GetPowerdownMode
+* functions.
+* Modified Assert for XAdcPs_SetSingleChParams in
+* xadcps.c to fix CR #807563.
+* 2.2 bss 04/27/14 Modified to use correct Device Config base address in
+* xadcps.c (CR#854437).
+* ms 01/23/17 Added xil_printf statement in main function for all
+* examples to ensure that "Successfully ran" and "Failed"
+* strings are available in all examples. This is a fix
+* for CR-965028.
+* ms 03/17/17 Added readme.txt file in examples folder for doxygen
+* generation.
+* ms 04/05/17 Modified Comment lines in functions of xadcps
+* examples to recognize it as documentation block
+* for doxygen generation.
+* 2.3 mn 07/09/18 Fix Doxygen warning
+*
+* </pre>
+*
+*****************************************************************************/
+#ifndef XADCPS_H /* Prevent circular inclusions */
+#define XADCPS_H /* by using protection macros */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/***************************** Include Files ********************************/
+
+#include "xil_types.h"
+#include "xil_assert.h"
+#include "xstatus.h"
+#include "xadcps_hw.h"
+
+/************************** Constant Definitions ****************************/
+
+
+/**
+ * @name Indexes for the different channels.
+ * @{
+ */
+#define XADCPS_CH_TEMP 0x0 /**< On Chip Temperature */
+#define XADCPS_CH_VCCINT 0x1 /**< VCCINT */
+#define XADCPS_CH_VCCAUX 0x2 /**< VCCAUX */
+#define XADCPS_CH_VPVN 0x3 /**< VP/VN Dedicated analog inputs */
+#define XADCPS_CH_VREFP 0x4 /**< VREFP */
+#define XADCPS_CH_VREFN 0x5 /**< VREFN */
+#define XADCPS_CH_VBRAM 0x6 /**< On-chip VBRAM Data Reg, 7 series */
+#define XADCPS_CH_SUPPLY_CALIB 0x07 /**< Supply Calib Data Reg */
+#define XADCPS_CH_ADC_CALIB 0x08 /**< ADC Offset Channel Reg */
+#define XADCPS_CH_GAINERR_CALIB 0x09 /**< Gain Error Channel Reg */
+#define XADCPS_CH_VCCPINT 0x0D /**< On-chip PS VCCPINT Channel , Zynq */
+#define XADCPS_CH_VCCPAUX 0x0E /**< On-chip PS VCCPAUX Channel , Zynq */
+#define XADCPS_CH_VCCPDRO 0x0F /**< On-chip PS VCCPDRO Channel , Zynq */
+#define XADCPS_CH_AUX_MIN 16 /**< Channel number for 1st Aux Channel */
+#define XADCPS_CH_AUX_MAX 31 /**< Channel number for Last Aux channel */
+
+/*@}*/
+
+
+/**
+ * @name Indexes for reading the Calibration Coefficient Data.
+ * @{
+ */
+#define XADCPS_CALIB_SUPPLY_COEFF 0 /**< Supply Offset Calib Coefficient */
+#define XADCPS_CALIB_ADC_COEFF 1 /**< ADC Offset Calib Coefficient */
+#define XADCPS_CALIB_GAIN_ERROR_COEFF 2 /**< Gain Error Calib Coefficient*/
+/*@}*/
+
+
+/**
+ * @name Indexes for reading the Minimum/Maximum Measurement Data.
+ * @{
+ */
+#define XADCPS_MAX_TEMP 0 /**< Maximum Temperature Data */
+#define XADCPS_MAX_VCCINT 1 /**< Maximum VCCINT Data */
+#define XADCPS_MAX_VCCAUX 2 /**< Maximum VCCAUX Data */
+#define XADCPS_MAX_VBRAM 3 /**< Maximum VBRAM Data */
+#define XADCPS_MIN_TEMP 4 /**< Minimum Temperature Data */
+#define XADCPS_MIN_VCCINT 5 /**< Minimum VCCINT Data */
+#define XADCPS_MIN_VCCAUX 6 /**< Minimum VCCAUX Data */
+#define XADCPS_MIN_VBRAM 7 /**< Minimum VBRAM Data */
+#define XADCPS_MAX_VCCPINT 8 /**< Maximum VCCPINT Register , Zynq */
+#define XADCPS_MAX_VCCPAUX 9 /**< Maximum VCCPAUX Register , Zynq */
+#define XADCPS_MAX_VCCPDRO 0xA /**< Maximum VCCPDRO Register , Zynq */
+#define XADCPS_MIN_VCCPINT 0xC /**< Minimum VCCPINT Register , Zynq */
+#define XADCPS_MIN_VCCPAUX 0xD /**< Minimum VCCPAUX Register , Zynq */
+#define XADCPS_MIN_VCCPDRO 0xE /**< Minimum VCCPDRO Register , Zynq */
+
+/*@}*/
+
+
+/**
+ * @name Alarm Threshold(Limit) Register (ATR) indexes.
+ * @{
+ */
+#define XADCPS_ATR_TEMP_UPPER 0 /**< High user Temperature */
+#define XADCPS_ATR_VCCINT_UPPER 1 /**< VCCINT high voltage limit register */
+#define XADCPS_ATR_VCCAUX_UPPER 2 /**< VCCAUX high voltage limit register */
+#define XADCPS_ATR_OT_UPPER 3 /**< VCCAUX high voltage limit register */
+#define XADCPS_ATR_TEMP_LOWER 4 /**< Upper Over Temperature limit Reg */
+#define XADCPS_ATR_VCCINT_LOWER 5 /**< VCCINT high voltage limit register */
+#define XADCPS_ATR_VCCAUX_LOWER 6 /**< VCCAUX low voltage limit register */
+#define XADCPS_ATR_OT_LOWER 7 /**< Lower Over Temperature limit */
+#define XADCPS_ATR_VBRAM_UPPER_ 8 /**< VRBAM Upper Alarm Reg, 7 Series */
+#define XADCPS_ATR_VCCPINT_UPPER 9 /**< VCCPINT Upper Alarm Reg, Zynq */
+#define XADCPS_ATR_VCCPAUX_UPPER 0xA /**< VCCPAUX Upper Alarm Reg, Zynq */
+#define XADCPS_ATR_VCCPDRO_UPPER 0xB /**< VCCPDRO Upper Alarm Reg, Zynq */
+#define XADCPS_ATR_VBRAM_LOWER 0xC /**< VRBAM Lower Alarm Reg, 7 Series */
+#define XADCPS_ATR_VCCPINT_LOWER 0xD /**< VCCPINT Lower Alarm Reg , Zynq */
+#define XADCPS_ATR_VCCPAUX_LOWER 0xE /**< VCCPAUX Lower Alarm Reg , Zynq */
+#define XADCPS_ATR_VCCPDRO_LOWER 0xF /**< VCCPDRO Lower Alarm Reg , Zynq */
+
+/*@}*/
+
+
+/**
+ * @name Averaging to be done for the channels.
+ * @{
+ */
+#define XADCPS_AVG_0_SAMPLES 0 /**< No Averaging */
+#define XADCPS_AVG_16_SAMPLES 1 /**< Average 16 samples */
+#define XADCPS_AVG_64_SAMPLES 2 /**< Average 64 samples */
+#define XADCPS_AVG_256_SAMPLES 3 /**< Average 256 samples */
+
+/*@}*/
+
+
+/**
+ * @name Channel Sequencer Modes of operation
+ * @{
+ */
+#define XADCPS_SEQ_MODE_SAFE 0 /**< Default Safe Mode */
+#define XADCPS_SEQ_MODE_ONEPASS 1 /**< Onepass through Sequencer */
+#define XADCPS_SEQ_MODE_CONTINPASS 2 /**< Continuous Cycling Sequencer */
+#define XADCPS_SEQ_MODE_SINGCHAN 3 /**< Single channel -No Sequencing */
+#define XADCPS_SEQ_MODE_SIMUL_SAMPLING 4 /**< Simultaneous sampling */
+#define XADCPS_SEQ_MODE_INDEPENDENT 8 /**< Independent mode */
+
+/*@}*/
+
+
+
+/**
+ * @name Power Down Modes
+ * @{
+ */
+#define XADCPS_PD_MODE_NONE 0 /**< No Power Down */
+#define XADCPS_PD_MODE_ADCB 1 /**< Power Down ADC B */
+#define XADCPS_PD_MODE_XADC 2 /**< Power Down ADC A and ADC B */
+/*@}*/
+
+/**************************** Type Definitions ******************************/
+
+/**
+ * This typedef contains configuration information for the XADC/ADC
+ * device.
+ */
+typedef struct {
+ u16 DeviceId; /**< Unique ID of device */
+ u32 BaseAddress; /**< Device base address */
+} XAdcPs_Config;
+
+
+/**
+ * The driver's instance data. The user is required to allocate a variable
+ * of this type for every XADC/ADC device in the system. A pointer to
+ * a variable of this type is then passed to the driver API functions.
+ */
+typedef struct {
+ XAdcPs_Config Config; /**< XAdcPs_Config of current device */
+ u32 IsReady; /**< Device is initialized and ready */
+
+} XAdcPs;
+
+/***************** Macros (Inline Functions) Definitions ********************/
+
+/****************************************************************************/
+/**
+*
+* This macro checks if the XADC device is in Event Sampling mode.
+*
+* @param InstancePtr is a pointer to the XAdcPs instance.
+*
+* @return
+* - TRUE if the device is in Event Sampling Mode.
+* - FALSE if the device is in Continuous Sampling Mode.
+*
+* @note C-Style signature:
+* int XAdcPs_IsEventSamplingMode(XAdcPs *InstancePtr);
+*
+*****************************************************************************/
+#define XAdcPs_IsEventSamplingModeSet(InstancePtr) \
+ (((XAdcPs_ReadInternalReg(InstancePtr, \
+ XADCPS_CFR0_OFFSET) & XADCPS_CFR0_EC_MASK) ? \
+ TRUE : FALSE))
+
+
+/****************************************************************************/
+/**
+*
+* This macro checks if the XADC device is in External Mux mode.
+*
+* @param InstancePtr is a pointer to the XAdcPs instance.
+*
+* @return
+* - TRUE if the device is in External Mux Mode.
+* - FALSE if the device is NOT in External Mux Mode.
+*
+* @note C-Style signature:
+* int XAdcPs_IsExternalMuxMode(XAdcPs *InstancePtr);
+*
+*****************************************************************************/
+#define XAdcPs_IsExternalMuxModeSet(InstancePtr) \
+ (((XAdcPs_ReadInternalReg(InstancePtr, \
+ XADCPS_CFR0_OFFSET) & XADCPS_CFR0_MUX_MASK) ? \
+ TRUE : FALSE))
+
+/****************************************************************************/
+/**
+*
+* This macro converts XADC Raw Data to Temperature(centigrades).
+*
+* @param AdcData is the Raw ADC Data from XADC.
+*
+* @return The Temperature in centigrades.
+*
+* @note C-Style signature:
+* float XAdcPs_RawToTemperature(u32 AdcData);
+*
+*****************************************************************************/
+#define XAdcPs_RawToTemperature(AdcData) \
+ ((((float)(AdcData)/65536.0f)/0.00198421639f ) - 273.15f)
+
+/****************************************************************************/
+/**
+*
+* This macro converts XADC/ADC Raw Data to Voltage(volts).
+*
+* @param AdcData is the XADC/ADC Raw Data.
+*
+* @return The Voltage in volts.
+*
+* @note C-Style signature:
+* float XAdcPs_RawToVoltage(u32 AdcData);
+*
+*****************************************************************************/
+#define XAdcPs_RawToVoltage(AdcData) \
+ ((((float)(AdcData))* (3.0f))/65536.0f)
+
+/****************************************************************************/
+/**
+*
+* This macro converts Temperature in centigrades to XADC/ADC Raw Data.
+*
+* @param Temperature is the Temperature in centigrades to be
+* converted to XADC/ADC Raw Data.
+*
+* @return The XADC/ADC Raw Data.
+*
+* @note C-Style signature:
+* int XAdcPs_TemperatureToRaw(float Temperature);
+*
+*****************************************************************************/
+#define XAdcPs_TemperatureToRaw(Temperature) \
+ ((int)(((Temperature) + 273.15f)*65536.0f*0.00198421639f))
+
+/****************************************************************************/
+/**
+*
+* This macro converts Voltage in Volts to XADC/ADC Raw Data.
+*
+* @param Voltage is the Voltage in volts to be converted to
+* XADC/ADC Raw Data.
+*
+* @return The XADC/ADC Raw Data.
+*
+* @note C-Style signature:
+* int XAdcPs_VoltageToRaw(float Voltage);
+*
+*****************************************************************************/
+#define XAdcPs_VoltageToRaw(Voltage) \
+ ((int)((Voltage)*65536.0f/3.0f))
+
+
+/****************************************************************************/
+/**
+*
+* This macro is used for writing to the XADC Registers using the
+* command FIFO.
+*
+* @param InstancePtr is a pointer to the XAdcPs instance.
+* @param Data is the value to be written to XADC register.
+*
+* @return None.
+*
+* @note C-Style signature:
+* void XAdcPs_WriteFifo(XAdcPs *InstancePtr, u32 Data);
+*
+*****************************************************************************/
+#define XAdcPs_WriteFifo(InstancePtr, Data) \
+ XAdcPs_WriteReg((InstancePtr)->Config.BaseAddress, \
+ XADCPS_CMDFIFO_OFFSET, Data);
+
+
+/****************************************************************************/
+/**
+*
+* This macro is used for reading from the XADC Registers using the
+* data FIFO.
+*
+* @param InstancePtr is a pointer to the XAdcPs instance.
+*
+* @return Data read from the FIFO
+*
+* @note C-Style signature:
+* u32 XAdcPs_ReadFifo(XAdcPs *InstancePtr);
+*
+*****************************************************************************/
+#define XAdcPs_ReadFifo(InstancePtr) \
+ XAdcPs_ReadReg((InstancePtr)->Config.BaseAddress, \
+ XADCPS_RDFIFO_OFFSET);
+
+
+/************************** Function Prototypes *****************************/
+
+
+
+/**
+ * Functions in xadcps_sinit.c
+ */
+XAdcPs_Config *XAdcPs_LookupConfig(u16 DeviceId);
+
+/**
+ * Functions in xadcps.c
+ */
+int XAdcPs_CfgInitialize(XAdcPs *InstancePtr,
+ XAdcPs_Config *ConfigPtr,
+ u32 EffectiveAddr);
+
+
+u32 XAdcPs_GetStatus(XAdcPs *InstancePtr);
+
+u32 XAdcPs_GetAlarmOutputStatus(XAdcPs *InstancePtr);
+
+void XAdcPs_StartAdcConversion(XAdcPs *InstancePtr);
+
+void XAdcPs_Reset(XAdcPs *InstancePtr);
+
+u16 XAdcPs_GetAdcData(XAdcPs *InstancePtr, u8 Channel);
+
+u16 XAdcPs_GetCalibCoefficient(XAdcPs *InstancePtr, u8 CoeffType);
+
+u16 XAdcPs_GetMinMaxMeasurement(XAdcPs *InstancePtr, u8 MeasurementType);
+
+void XAdcPs_SetAvg(XAdcPs *InstancePtr, u8 Average);
+u8 XAdcPs_GetAvg(XAdcPs *InstancePtr);
+
+int XAdcPs_SetSingleChParams(XAdcPs *InstancePtr,
+ u8 Channel,
+ int IncreaseAcqCycles,
+ int IsEventMode,
+ int IsDifferentialMode);
+
+
+void XAdcPs_SetAlarmEnables(XAdcPs *InstancePtr, u16 AlmEnableMask);
+u16 XAdcPs_GetAlarmEnables(XAdcPs *InstancePtr);
+
+void XAdcPs_SetCalibEnables(XAdcPs *InstancePtr, u16 Calibration);
+u16 XAdcPs_GetCalibEnables(XAdcPs *InstancePtr);
+
+void XAdcPs_SetSequencerMode(XAdcPs *InstancePtr, u8 SequencerMode);
+u8 XAdcPs_GetSequencerMode(XAdcPs *InstancePtr);
+
+void XAdcPs_SetAdcClkDivisor(XAdcPs *InstancePtr, u8 Divisor);
+u8 XAdcPs_GetAdcClkDivisor(XAdcPs *InstancePtr);
+
+int XAdcPs_SetSeqChEnables(XAdcPs *InstancePtr, u32 ChEnableMask);
+u32 XAdcPs_GetSeqChEnables(XAdcPs *InstancePtr);
+
+int XAdcPs_SetSeqAvgEnables(XAdcPs *InstancePtr, u32 AvgEnableChMask);
+u32 XAdcPs_GetSeqAvgEnables(XAdcPs *InstancePtr);
+
+int XAdcPs_SetSeqInputMode(XAdcPs *InstancePtr, u32 InputModeChMask);
+u32 XAdcPs_GetSeqInputMode(XAdcPs *InstancePtr);
+
+int XAdcPs_SetSeqAcqTime(XAdcPs *InstancePtr, u32 AcqCyclesChMask);
+u32 XAdcPs_GetSeqAcqTime(XAdcPs *InstancePtr);
+
+void XAdcPs_SetAlarmThreshold(XAdcPs *InstancePtr, u8 AlarmThrReg, u16 Value);
+u16 XAdcPs_GetAlarmThreshold(XAdcPs *InstancePtr, u8 AlarmThrReg);
+
+void XAdcPs_EnableUserOverTemp(XAdcPs *InstancePtr);
+void XAdcPs_DisableUserOverTemp(XAdcPs *InstancePtr);
+
+void XAdcPs_SetSequencerEvent(XAdcPs *InstancePtr, int IsEventMode);
+
+int XAdcPs_GetSamplingMode(XAdcPs *InstancePtr);
+
+void XAdcPs_SetMuxMode(XAdcPs *InstancePtr, int MuxMode, u8 Channel);
+
+void XAdcPs_SetPowerdownMode(XAdcPs *InstancePtr, u32 Mode);
+
+u32 XAdcPs_GetPowerdownMode(XAdcPs *InstancePtr);
+
+/**
+ * Functions in xadcps_selftest.c
+ */
+int XAdcPs_SelfTest(XAdcPs *InstancePtr);
+
+/**
+ * Functions in xadcps_intr.c
+ */
+void XAdcPs_IntrEnable(XAdcPs *InstancePtr, u32 Mask);
+void XAdcPs_IntrDisable(XAdcPs *InstancePtr, u32 Mask);
+u32 XAdcPs_IntrGetEnabled(XAdcPs *InstancePtr);
+
+u32 XAdcPs_IntrGetStatus(XAdcPs *InstancePtr);
+void XAdcPs_IntrClear(XAdcPs *InstancePtr, u32 Mask);
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* End of protection macro. */
+/** @} */
diff --git a/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/xadcps_v2_3/src/xadcps_g.c b/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/xadcps_v2_3/src/xadcps_g.c
new file mode 100644
index 0000000..ee60423
--- /dev/null
+++ b/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/xadcps_v2_3/src/xadcps_g.c
@@ -0,0 +1,47 @@
+
+/*******************************************************************
+*
+* CAUTION: This file is automatically generated by HSI.
+* Version: 2019.2
+* DO NOT EDIT.
+*
+* Copyright (C) 2010-2021 Xilinx, Inc. All Rights Reserved.*
+*Permission is hereby granted, free of charge, to any person obtaining a copy
+*of this software and associated documentation files (the Software), to deal
+*in the Software without restriction, including without limitation the rights
+*to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+*copies of the Software, and to permit persons to whom the Software is
+*furnished to do so, subject to the following conditions:
+*
+*The above copyright notice and this permission notice shall be included in
+*all copies or substantial portions of the Software.
+*
+*THE SOFTWARE IS PROVIDED AS IS, WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+*IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+*FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+*THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+*WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT
+*OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+*
+
+*
+* Description: Driver configuration
+*
+*******************************************************************/
+
+#include "xparameters.h"
+#include "xadcps.h"
+
+/*
+* The configuration table for devices
+*/
+
+XAdcPs_Config XAdcPs_ConfigTable[XPAR_XADCPS_NUM_INSTANCES] =
+{
+ {
+ XPAR_PS7_XADC_0_DEVICE_ID,
+ XPAR_PS7_XADC_0_BASEADDR
+ }
+};
+
+
diff --git a/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/xadcps_v2_3/src/xadcps_hw.h b/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/xadcps_v2_3/src/xadcps_hw.h
new file mode 100644
index 0000000..717fc90
--- /dev/null
+++ b/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/xadcps_v2_3/src/xadcps_hw.h
@@ -0,0 +1,496 @@
+/******************************************************************************
+*
+* Copyright (C) 2011 - 2014 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+* THE SOFTWARE.
+*
+*
+*
+******************************************************************************/
+/****************************************************************************/
+/**
+*
+* @file xadcps_hw.h
+* @addtogroup xadcps_v2_3
+* @{
+*
+* This header file contains identifiers and basic driver functions (or
+* macros) that can be used to access the XADC device through the Device
+* Config Interface of the Zynq.
+*
+*
+* Refer to the device specification for more information about this driver.
+*
+* @note None.
+*
+*
+* <pre>
+*
+* MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ----- ----- -------- -----------------------------------------------------
+* 1.00a bss 12/22/11 First release based on the XPS/AXI xadc driver
+* 1.03a bss 11/01/13 Modified macros to use correct Register offsets
+* CR#749687
+*
+* </pre>
+*
+*****************************************************************************/
+#ifndef XADCPS_HW_H /* Prevent circular inclusions */
+#define XADCPS_HW_H /* by using protection macros */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/***************************** Include Files ********************************/
+
+#include "xil_types.h"
+#include "xil_assert.h"
+#include "xil_io.h"
+
+/************************** Constant Definitions ****************************/
+
+
+/**@name Register offsets of XADC in the Device Config
+ *
+ * The following constants provide access to each of the registers of the
+ * XADC device.
+ * @{
+ */
+
+#define XADCPS_CFG_OFFSET 0x00 /**< Configuration Register */
+#define XADCPS_INT_STS_OFFSET 0x04 /**< Interrupt Status Register */
+#define XADCPS_INT_MASK_OFFSET 0x08 /**< Interrupt Mask Register */
+#define XADCPS_MSTS_OFFSET 0x0C /**< Misc status register */
+#define XADCPS_CMDFIFO_OFFSET 0x10 /**< Command FIFO Register */
+#define XADCPS_RDFIFO_OFFSET 0x14 /**< Read FIFO Register */
+#define XADCPS_MCTL_OFFSET 0x18 /**< Misc control register */
+
+/* @} */
+
+
+
+
+
+/** @name XADC Config Register Bit definitions
+ * @{
+ */
+#define XADCPS_CFG_ENABLE_MASK 0x80000000 /**< Enable access from PS mask */
+#define XADCPS_CFG_CFIFOTH_MASK 0x00F00000 /**< Command FIFO Threshold mask */
+#define XADCPS_CFG_DFIFOTH_MASK 0x000F0000 /**< Data FIFO Threshold mask */
+#define XADCPS_CFG_WEDGE_MASK 0x00002000 /**< Write Edge Mask */
+#define XADCPS_CFG_REDGE_MASK 0x00001000 /**< Read Edge Mask */
+#define XADCPS_CFG_TCKRATE_MASK 0x00000300 /**< Clock freq control */
+#define XADCPS_CFG_IGAP_MASK 0x0000001F /**< Idle Gap between
+ * successive commands */
+/* @} */
+
+
+/** @name XADC Interrupt Status/Mask Register Bit definitions
+ *
+ * The definitions are same for the Interrupt Status Register and
+ * Interrupt Mask Register. They are defined only once.
+ * @{
+ */
+#define XADCPS_INTX_ALL_MASK 0x000003FF /**< Alarm Signals Mask */
+#define XADCPS_INTX_CFIFO_LTH_MASK 0x00000200 /**< CMD FIFO less than threshold */
+#define XADCPS_INTX_DFIFO_GTH_MASK 0x00000100 /**< Data FIFO greater than threshold */
+#define XADCPS_INTX_OT_MASK 0x00000080 /**< Over temperature Alarm Status */
+#define XADCPS_INTX_ALM_ALL_MASK 0x0000007F /**< Alarm Signals Mask */
+#define XADCPS_INTX_ALM6_MASK 0x00000040 /**< Alarm 6 Mask */
+#define XADCPS_INTX_ALM5_MASK 0x00000020 /**< Alarm 5 Mask */
+#define XADCPS_INTX_ALM4_MASK 0x00000010 /**< Alarm 4 Mask */
+#define XADCPS_INTX_ALM3_MASK 0x00000008 /**< Alarm 3 Mask */
+#define XADCPS_INTX_ALM2_MASK 0x00000004 /**< Alarm 2 Mask */
+#define XADCPS_INTX_ALM1_MASK 0x00000002 /**< Alarm 1 Mask */
+#define XADCPS_INTX_ALM0_MASK 0x00000001 /**< Alarm 0 Mask */
+
+/* @} */
+
+
+/** @name XADC Miscellaneous Register Bit definitions
+ * @{
+ */
+#define XADCPS_MSTS_CFIFO_LVL_MASK 0x000F0000 /**< Command FIFO Level mask */
+#define XADCPS_MSTS_DFIFO_LVL_MASK 0x0000F000 /**< Data FIFO Level Mask */
+#define XADCPS_MSTS_CFIFOF_MASK 0x00000800 /**< Command FIFO Full Mask */
+#define XADCPS_MSTS_CFIFOE_MASK 0x00000400 /**< Command FIFO Empty Mask */
+#define XADCPS_MSTS_DFIFOF_MASK 0x00000200 /**< Data FIFO Full Mask */
+#define XADCPS_MSTS_DFIFOE_MASK 0x00000100 /**< Data FIFO Empty Mask */
+#define XADCPS_MSTS_OT_MASK 0x00000080 /**< Over Temperature Mask */
+#define XADCPS_MSTS_ALM_MASK 0x0000007F /**< Alarms Mask */
+/* @} */
+
+
+/** @name XADC Miscellaneous Control Register Bit definitions
+ * @{
+ */
+#define XADCPS_MCTL_RESET_MASK 0x00000010 /**< Reset XADC */
+#define XADCPS_MCTL_FLUSH_MASK 0x00000001 /**< Flush the FIFOs */
+/* @} */
+
+
+/**@name Internal Register offsets of the XADC
+ *
+ * The following constants provide access to each of the internal registers of
+ * the XADC device.
+ * @{
+ */
+
+/*
+ * XADC Internal Channel Registers
+ */
+#define XADCPS_TEMP_OFFSET 0x00 /**< On-chip Temperature Reg */
+#define XADCPS_VCCINT_OFFSET 0x01 /**< On-chip VCCINT Data Reg */
+#define XADCPS_VCCAUX_OFFSET 0x02 /**< On-chip VCCAUX Data Reg */
+#define XADCPS_VPVN_OFFSET 0x03 /**< ADC out of VP/VN */
+#define XADCPS_VREFP_OFFSET 0x04 /**< On-chip VREFP Data Reg */
+#define XADCPS_VREFN_OFFSET 0x05 /**< On-chip VREFN Data Reg */
+#define XADCPS_VBRAM_OFFSET 0x06 /**< On-chip VBRAM , 7 Series */
+#define XADCPS_ADC_A_SUPPLY_CALIB_OFFSET 0x08 /**< ADC A Supply Offset Reg */
+#define XADCPS_ADC_A_OFFSET_CALIB_OFFSET 0x09 /**< ADC A Offset Data Reg */
+#define XADCPS_ADC_A_GAINERR_CALIB_OFFSET 0x0A /**< ADC A Gain Error Reg */
+#define XADCPS_VCCPINT_OFFSET 0x0D /**< On-chip VCCPINT Reg, Zynq */
+#define XADCPS_VCCPAUX_OFFSET 0x0E /**< On-chip VCCPAUX Reg, Zynq */
+#define XADCPS_VCCPDRO_OFFSET 0x0F /**< On-chip VCCPDRO Reg, Zynq */
+
+/*
+ * XADC External Channel Registers
+ */
+#define XADCPS_AUX00_OFFSET 0x10 /**< ADC out of VAUXP0/VAUXN0 */
+#define XADCPS_AUX01_OFFSET 0x11 /**< ADC out of VAUXP1/VAUXN1 */
+#define XADCPS_AUX02_OFFSET 0x12 /**< ADC out of VAUXP2/VAUXN2 */
+#define XADCPS_AUX03_OFFSET 0x13 /**< ADC out of VAUXP3/VAUXN3 */
+#define XADCPS_AUX04_OFFSET 0x14 /**< ADC out of VAUXP4/VAUXN4 */
+#define XADCPS_AUX05_OFFSET 0x15 /**< ADC out of VAUXP5/VAUXN5 */
+#define XADCPS_AUX06_OFFSET 0x16 /**< ADC out of VAUXP6/VAUXN6 */
+#define XADCPS_AUX07_OFFSET 0x17 /**< ADC out of VAUXP7/VAUXN7 */
+#define XADCPS_AUX08_OFFSET 0x18 /**< ADC out of VAUXP8/VAUXN8 */
+#define XADCPS_AUX09_OFFSET 0x19 /**< ADC out of VAUXP9/VAUXN9 */
+#define XADCPS_AUX10_OFFSET 0x1A /**< ADC out of VAUXP10/VAUXN10 */
+#define XADCPS_AUX11_OFFSET 0x1B /**< ADC out of VAUXP11/VAUXN11 */
+#define XADCPS_AUX12_OFFSET 0x1C /**< ADC out of VAUXP12/VAUXN12 */
+#define XADCPS_AUX13_OFFSET 0x1D /**< ADC out of VAUXP13/VAUXN13 */
+#define XADCPS_AUX14_OFFSET 0x1E /**< ADC out of VAUXP14/VAUXN14 */
+#define XADCPS_AUX15_OFFSET 0x1F /**< ADC out of VAUXP15/VAUXN15 */
+
+/*
+ * XADC Registers for Maximum/Minimum data captured for the
+ * on chip Temperature/VCCINT/VCCAUX data.
+ */
+#define XADCPS_MAX_TEMP_OFFSET 0x20 /**< Max Temperature Reg */
+#define XADCPS_MAX_VCCINT_OFFSET 0x21 /**< Max VCCINT Register */
+#define XADCPS_MAX_VCCAUX_OFFSET 0x22 /**< Max VCCAUX Register */
+#define XADCPS_MAX_VCCBRAM_OFFSET 0x23 /**< Max BRAM Register, 7 series */
+#define XADCPS_MIN_TEMP_OFFSET 0x24 /**< Min Temperature Reg */
+#define XADCPS_MIN_VCCINT_OFFSET 0x25 /**< Min VCCINT Register */
+#define XADCPS_MIN_VCCAUX_OFFSET 0x26 /**< Min VCCAUX Register */
+#define XADCPS_MIN_VCCBRAM_OFFSET 0x27 /**< Min BRAM Register, 7 series */
+#define XADCPS_MAX_VCCPINT_OFFSET 0x28 /**< Max VCCPINT Register, Zynq */
+#define XADCPS_MAX_VCCPAUX_OFFSET 0x29 /**< Max VCCPAUX Register, Zynq */
+#define XADCPS_MAX_VCCPDRO_OFFSET 0x2A /**< Max VCCPDRO Register, Zynq */
+#define XADCPS_MIN_VCCPINT_OFFSET 0x2C /**< Min VCCPINT Register, Zynq */
+#define XADCPS_MIN_VCCPAUX_OFFSET 0x2D /**< Min VCCPAUX Register, Zynq */
+#define XADCPS_MIN_VCCPDRO_OFFSET 0x2E /**< Min VCCPDRO Register,Zynq */
+ /* Undefined 0x2F to 0x3E */
+#define XADCPS_FLAG_OFFSET 0x3F /**< Flag Register */
+
+/*
+ * XADC Configuration Registers
+ */
+#define XADCPS_CFR0_OFFSET 0x40 /**< Configuration Register 0 */
+#define XADCPS_CFR1_OFFSET 0x41 /**< Configuration Register 1 */
+#define XADCPS_CFR2_OFFSET 0x42 /**< Configuration Register 2 */
+
+/* Test Registers 0x43 to 0x47 */
+
+/*
+ * XADC Sequence Registers
+ */
+#define XADCPS_SEQ00_OFFSET 0x48 /**< Seq Reg 00 Adc Channel Selection */
+#define XADCPS_SEQ01_OFFSET 0x49 /**< Seq Reg 01 Adc Channel Selection */
+#define XADCPS_SEQ02_OFFSET 0x4A /**< Seq Reg 02 Adc Average Enable */
+#define XADCPS_SEQ03_OFFSET 0x4B /**< Seq Reg 03 Adc Average Enable */
+#define XADCPS_SEQ04_OFFSET 0x4C /**< Seq Reg 04 Adc Input Mode Select */
+#define XADCPS_SEQ05_OFFSET 0x4D /**< Seq Reg 05 Adc Input Mode Select */
+#define XADCPS_SEQ06_OFFSET 0x4E /**< Seq Reg 06 Adc Acquisition Select */
+#define XADCPS_SEQ07_OFFSET 0x4F /**< Seq Reg 07 Adc Acquisition Select */
+
+/*
+ * XADC Alarm Threshold/Limit Registers (ATR)
+ */
+#define XADCPS_ATR_TEMP_UPPER_OFFSET 0x50 /**< Temp Upper Alarm Register */
+#define XADCPS_ATR_VCCINT_UPPER_OFFSET 0x51 /**< VCCINT Upper Alarm Reg */
+#define XADCPS_ATR_VCCAUX_UPPER_OFFSET 0x52 /**< VCCAUX Upper Alarm Reg */
+#define XADCPS_ATR_OT_UPPER_OFFSET 0x53 /**< Over Temp Upper Alarm Reg */
+#define XADCPS_ATR_TEMP_LOWER_OFFSET 0x54 /**< Temp Lower Alarm Register */
+#define XADCPS_ATR_VCCINT_LOWER_OFFSET 0x55 /**< VCCINT Lower Alarm Reg */
+#define XADCPS_ATR_VCCAUX_LOWER_OFFSET 0x56 /**< VCCAUX Lower Alarm Reg */
+#define XADCPS_ATR_OT_LOWER_OFFSET 0x57 /**< Over Temp Lower Alarm Reg */
+#define XADCPS_ATR_VBRAM_UPPER_OFFSET 0x58 /**< VBRAM Upper Alarm, 7 series */
+#define XADCPS_ATR_VCCPINT_UPPER_OFFSET 0x59 /**< VCCPINT Upper Alarm, Zynq */
+#define XADCPS_ATR_VCCPAUX_UPPER_OFFSET 0x5A /**< VCCPAUX Upper Alarm, Zynq */
+#define XADCPS_ATR_VCCPDRO_UPPER_OFFSET 0x5B /**< VCCPDRO Upper Alarm, Zynq */
+#define XADCPS_ATR_VBRAM_LOWER_OFFSET 0x5C /**< VRBAM Lower Alarm, 7 Series */
+#define XADCPS_ATR_VCCPINT_LOWER_OFFSET 0x5D /**< VCCPINT Lower Alarm, Zynq */
+#define XADCPS_ATR_VCCPAUX_LOWER_OFFSET 0x5E /**< VCCPAUX Lower Alarm, Zynq */
+#define XADCPS_ATR_VCCPDRO_LOWER_OFFSET 0x5F /**< VCCPDRO Lower Alarm, Zynq */
+
+/* Undefined 0x60 to 0x7F */
+
+/*@}*/
+
+
+
+/**
+ * @name Configuration Register 0 (CFR0) mask(s)
+ * @{
+ */
+#define XADCPS_CFR0_CAL_AVG_MASK 0x8000 /**< Averaging enable Mask */
+#define XADCPS_CFR0_AVG_VALID_MASK 0x3000 /**< Averaging bit Mask */
+#define XADCPS_CFR0_AVG1_MASK 0x0000 /**< No Averaging */
+#define XADCPS_CFR0_AVG16_MASK 0x1000 /**< Average 16 samples */
+#define XADCPS_CFR0_AVG64_MASK 0x2000 /**< Average 64 samples */
+#define XADCPS_CFR0_AVG256_MASK 0x3000 /**< Average 256 samples */
+#define XADCPS_CFR0_AVG_SHIFT 12 /**< Averaging bits shift */
+#define XADCPS_CFR0_MUX_MASK 0x0800 /**< External Mask Enable */
+#define XADCPS_CFR0_DU_MASK 0x0400 /**< Bipolar/Unipolar mode */
+#define XADCPS_CFR0_EC_MASK 0x0200 /**< Event driven/
+ * Continuous mode selection
+ */
+#define XADCPS_CFR0_ACQ_MASK 0x0100 /**< Add acquisition by 6 ADCCLK */
+#define XADCPS_CFR0_CHANNEL_MASK 0x001F /**< Channel number bit Mask */
+
+/*@}*/
+
+/**
+ * @name Configuration Register 1 (CFR1) mask(s)
+ * @{
+ */
+#define XADCPS_CFR1_SEQ_VALID_MASK 0xF000 /**< Sequence bit Mask */
+#define XADCPS_CFR1_SEQ_SAFEMODE_MASK 0x0000 /**< Default Safe Mode */
+#define XADCPS_CFR1_SEQ_ONEPASS_MASK 0x1000 /**< Onepass through Seq */
+#define XADCPS_CFR1_SEQ_CONTINPASS_MASK 0x2000 /**< Continuous Cycling Seq */
+#define XADCPS_CFR1_SEQ_SINGCHAN_MASK 0x3000 /**< Single channel - No Seq */
+#define XADCPS_CFR1_SEQ_SIMUL_SAMPLING_MASK 0x4000 /**< Simulataneous Sampling Mask */
+#define XADCPS_CFR1_SEQ_INDEPENDENT_MASK 0x8000 /**< Independent Mode */
+#define XADCPS_CFR1_SEQ_SHIFT 12 /**< Sequence bit shift */
+#define XADCPS_CFR1_ALM_VCCPDRO_MASK 0x0800 /**< Alm 6 - VCCPDRO, Zynq */
+#define XADCPS_CFR1_ALM_VCCPAUX_MASK 0x0400 /**< Alm 5 - VCCPAUX, Zynq */
+#define XADCPS_CFR1_ALM_VCCPINT_MASK 0x0200 /**< Alm 4 - VCCPINT, Zynq */
+#define XADCPS_CFR1_ALM_VBRAM_MASK 0x0100 /**< Alm 3 - VBRAM, 7 series */
+#define XADCPS_CFR1_CAL_VALID_MASK 0x00F0 /**< Valid Calibration Mask */
+#define XADCPS_CFR1_CAL_PS_GAIN_OFFSET_MASK 0x0080 /**< Calibration 3 -Power
+ Supply Gain/Offset
+ Enable */
+#define XADCPS_CFR1_CAL_PS_OFFSET_MASK 0x0040 /**< Calibration 2 -Power
+ Supply Offset Enable */
+#define XADCPS_CFR1_CAL_ADC_GAIN_OFFSET_MASK 0x0020 /**< Calibration 1 -ADC Gain
+ Offset Enable */
+#define XADCPS_CFR1_CAL_ADC_OFFSET_MASK 0x0010 /**< Calibration 0 -ADC Offset
+ Enable */
+#define XADCPS_CFR1_CAL_DISABLE_MASK 0x0000 /**< No Calibration */
+#define XADCPS_CFR1_ALM_ALL_MASK 0x0F0F /**< Mask for all alarms */
+#define XADCPS_CFR1_ALM_VCCAUX_MASK 0x0008 /**< Alarm 2 - VCCAUX Enable */
+#define XADCPS_CFR1_ALM_VCCINT_MASK 0x0004 /**< Alarm 1 - VCCINT Enable */
+#define XADCPS_CFR1_ALM_TEMP_MASK 0x0002 /**< Alarm 0 - Temperature */
+#define XADCPS_CFR1_OT_MASK 0x0001 /**< Over Temperature Enable */
+
+/*@}*/
+
+/**
+ * @name Configuration Register 2 (CFR2) mask(s)
+ * @{
+ */
+#define XADCPS_CFR2_CD_VALID_MASK 0xFF00 /**<Clock Divisor bit Mask */
+#define XADCPS_CFR2_CD_SHIFT 8 /**<Num of shift on division */
+#define XADCPS_CFR2_CD_MIN 8 /**<Minimum value of divisor */
+#define XADCPS_CFR2_CD_MAX 255 /**<Maximum value of divisor */
+
+#define XADCPS_CFR2_CD_MIN 8 /**<Minimum value of divisor */
+#define XADCPS_CFR2_PD_MASK 0x0030 /**<Power Down Mask */
+#define XADCPS_CFR2_PD_XADC_MASK 0x0030 /**<Power Down XADC Mask */
+#define XADCPS_CFR2_PD_ADC1_MASK 0x0020 /**<Power Down ADC1 Mask */
+#define XADCPS_CFR2_PD_SHIFT 4 /**<Power Down Shift */
+/*@}*/
+
+/**
+ * @name Sequence Register (SEQ) Bit Definitions
+ * @{
+ */
+#define XADCPS_SEQ_CH_CALIB 0x00000001 /**< ADC Calibration Channel */
+#define XADCPS_SEQ_CH_VCCPINT 0x00000020 /**< VCCPINT, Zynq Only */
+#define XADCPS_SEQ_CH_VCCPAUX 0x00000040 /**< VCCPAUX, Zynq Only */
+#define XADCPS_SEQ_CH_VCCPDRO 0x00000080 /**< VCCPDRO, Zynq Only */
+#define XADCPS_SEQ_CH_TEMP 0x00000100 /**< On Chip Temperature Channel */
+#define XADCPS_SEQ_CH_VCCINT 0x00000200 /**< VCCINT Channel */
+#define XADCPS_SEQ_CH_VCCAUX 0x00000400 /**< VCCAUX Channel */
+#define XADCPS_SEQ_CH_VPVN 0x00000800 /**< VP/VN analog inputs Channel */
+#define XADCPS_SEQ_CH_VREFP 0x00001000 /**< VREFP Channel */
+#define XADCPS_SEQ_CH_VREFN 0x00002000 /**< VREFN Channel */
+#define XADCPS_SEQ_CH_VBRAM 0x00004000 /**< VBRAM Channel, 7 series */
+#define XADCPS_SEQ_CH_AUX00 0x00010000 /**< 1st Aux Channel */
+#define XADCPS_SEQ_CH_AUX01 0x00020000 /**< 2nd Aux Channel */
+#define XADCPS_SEQ_CH_AUX02 0x00040000 /**< 3rd Aux Channel */
+#define XADCPS_SEQ_CH_AUX03 0x00080000 /**< 4th Aux Channel */
+#define XADCPS_SEQ_CH_AUX04 0x00100000 /**< 5th Aux Channel */
+#define XADCPS_SEQ_CH_AUX05 0x00200000 /**< 6th Aux Channel */
+#define XADCPS_SEQ_CH_AUX06 0x00400000 /**< 7th Aux Channel */
+#define XADCPS_SEQ_CH_AUX07 0x00800000 /**< 8th Aux Channel */
+#define XADCPS_SEQ_CH_AUX08 0x01000000 /**< 9th Aux Channel */
+#define XADCPS_SEQ_CH_AUX09 0x02000000 /**< 10th Aux Channel */
+#define XADCPS_SEQ_CH_AUX10 0x04000000 /**< 11th Aux Channel */
+#define XADCPS_SEQ_CH_AUX11 0x08000000 /**< 12th Aux Channel */
+#define XADCPS_SEQ_CH_AUX12 0x10000000 /**< 13th Aux Channel */
+#define XADCPS_SEQ_CH_AUX13 0x20000000 /**< 14th Aux Channel */
+#define XADCPS_SEQ_CH_AUX14 0x40000000 /**< 15th Aux Channel */
+#define XADCPS_SEQ_CH_AUX15 0x80000000 /**< 16th Aux Channel */
+
+#define XADCPS_SEQ00_CH_VALID_MASK 0x7FE1 /**< Mask for the valid channels */
+#define XADCPS_SEQ01_CH_VALID_MASK 0xFFFF /**< Mask for the valid channels */
+
+#define XADCPS_SEQ02_CH_VALID_MASK 0x7FE0 /**< Mask for the valid channels */
+#define XADCPS_SEQ03_CH_VALID_MASK 0xFFFF /**< Mask for the valid channels */
+
+#define XADCPS_SEQ04_CH_VALID_MASK 0x0800 /**< Mask for the valid channels */
+#define XADCPS_SEQ05_CH_VALID_MASK 0xFFFF /**< Mask for the valid channels */
+
+#define XADCPS_SEQ06_CH_VALID_MASK 0x0800 /**< Mask for the valid channels */
+#define XADCPS_SEQ07_CH_VALID_MASK 0xFFFF /**< Mask for the valid channels */
+
+
+#define XADCPS_SEQ_CH_AUX_SHIFT 16 /**< Shift for the Aux Channel */
+
+/*@}*/
+
+/**
+ * @name OT Upper Alarm Threshold Register Bit Definitions
+ * @{
+ */
+
+#define XADCPS_ATR_OT_UPPER_ENB_MASK 0x000F /**< Mask for OT enable */
+#define XADCPS_ATR_OT_UPPER_VAL_MASK 0xFFF0 /**< Mask for OT value */
+#define XADCPS_ATR_OT_UPPER_VAL_SHIFT 4 /**< Shift for OT value */
+#define XADCPS_ATR_OT_UPPER_ENB_VAL 0x0003 /**< Value for OT enable */
+#define XADCPS_ATR_OT_UPPER_VAL_MAX 0x0FFF /**< Max OT value */
+
+/*@}*/
+
+
+/**
+ * @name JTAG DRP Bit Definitions
+ * @{
+ */
+#define XADCPS_JTAG_DATA_MASK 0x0000FFFF /**< Mask for the Data */
+#define XADCPS_JTAG_ADDR_MASK 0x03FF0000 /**< Mask for the Addr */
+#define XADCPS_JTAG_ADDR_SHIFT 16 /**< Shift for the Addr */
+#define XADCPS_JTAG_CMD_MASK 0x3C000000 /**< Mask for the Cmd */
+#define XADCPS_JTAG_CMD_WRITE_MASK 0x08000000 /**< Mask for CMD Write */
+#define XADCPS_JTAG_CMD_READ_MASK 0x04000000 /**< Mask for CMD Read */
+#define XADCPS_JTAG_CMD_SHIFT 26 /**< Shift for the Cmd */
+
+/*@}*/
+
+/** @name Unlock Register Definitions
+ * @{
+ */
+ #define XADCPS_UNLK_OFFSET 0x034 /**< Unlock Register */
+ #define XADCPS_UNLK_VALUE 0x757BDF0D /**< Unlock Value */
+
+ /* @} */
+
+
+/**************************** Type Definitions *******************************/
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/*****************************************************************************/
+/**
+*
+* Read a register of the XADC device. This macro provides register
+* access to all registers using the register offsets defined above.
+*
+* @param BaseAddress contains the base address of the device.
+* @param RegOffset is the offset of the register to read.
+*
+* @return The contents of the register.
+*
+* @note C-style Signature:
+* u32 XAdcPs_ReadReg(u32 BaseAddress, u32 RegOffset);
+*
+******************************************************************************/
+#define XAdcPs_ReadReg(BaseAddress, RegOffset) \
+ (Xil_In32((BaseAddress) + (RegOffset)))
+
+/*****************************************************************************/
+/**
+*
+* Write a register of the XADC device. This macro provides
+* register access to all registers using the register offsets defined above.
+*
+* @param BaseAddress contains the base address of the device.
+* @param RegOffset is the offset of the register to write.
+* @param Data is the value to write to the register.
+*
+* @return None.
+*
+* @note C-style Signature:
+* void XAdcPs_WriteReg(u32 BaseAddress,
+* u32 RegOffset,u32 Data)
+*
+******************************************************************************/
+#define XAdcPs_WriteReg(BaseAddress, RegOffset, Data) \
+ (Xil_Out32((BaseAddress) + (RegOffset), (Data)))
+
+/************************** Function Prototypes ******************************/
+
+
+/*****************************************************************************/
+/**
+*
+* Formats the data to be written to the the XADC registers.
+*
+* @param RegOffset is the offset of the Register
+* @param Data is the data to be written to the Register if it is
+* a write.
+* @param ReadWrite specifies whether it is a Read or a Write.
+* Use 0 for Read, 1 for Write.
+*
+* @return None.
+*
+* @note C-style Signature:
+* void XAdcPs_FormatWriteData(u32 RegOffset,
+* u16 Data, int ReadWrite)
+*
+******************************************************************************/
+#define XAdcPs_FormatWriteData(RegOffset, Data, ReadWrite) \
+ ((ReadWrite ? XADCPS_JTAG_CMD_WRITE_MASK : XADCPS_JTAG_CMD_READ_MASK ) | \
+ ((RegOffset << XADCPS_JTAG_ADDR_SHIFT) & XADCPS_JTAG_ADDR_MASK) | \
+ (Data & XADCPS_JTAG_DATA_MASK))
+
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* End of protection macro. */
+/** @} */
diff --git a/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/xadcps_v2_3/src/xadcps_intr.c b/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/xadcps_v2_3/src/xadcps_intr.c
new file mode 100644
index 0000000..065bb68
--- /dev/null
+++ b/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/xadcps_v2_3/src/xadcps_intr.c
@@ -0,0 +1,244 @@
+/******************************************************************************
+*
+* Copyright (C) 2011 - 2014 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+* THE SOFTWARE.
+*
+*
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xadcps_intr.c
+* @addtogroup xadcps_v2_3
+* @{
+*
+* This file contains interrupt handling API functions of the XADC
+* device.
+*
+* The device must be configured at hardware build time to support interrupt
+* for all the functions in this file to work.
+*
+* Refer to xadcps.h header file and device specification for more information.
+*
+* @note
+*
+* Calling the interrupt functions without including the interrupt component will
+* result in asserts if asserts are enabled, and will result in a unpredictable
+* behavior if the asserts are not enabled.
+*
+* <pre>
+*
+* MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ----- ----- -------- -----------------------------------------------------
+* 1.00a ssb 12/22/11 First release based on the XPS/AXI xadc driver
+*
+* </pre>
+*
+******************************************************************************/
+
+/***************************** Include Files *********************************/
+
+#include "xadcps.h"
+
+/************************** Constant Definitions *****************************/
+
+/**************************** Type Definitions *******************************/
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/************************** Function Prototypes ******************************/
+
+/************************** Variable Definitions *****************************/
+
+
+/****************************************************************************/
+/**
+*
+* This function enables the specified interrupts in the device.
+*
+* @param InstancePtr is a pointer to the XAdcPs instance.
+* @param Mask is the bit-mask of the interrupts to be enabled.
+* Bit positions of 1 will be enabled. Bit positions of 0 will
+* keep the previous setting. This mask is formed by OR'ing
+* XADCPS_INTX_* bits defined in xadcps_hw.h.
+*
+* @return None.
+*
+* @note None.
+*
+*****************************************************************************/
+void XAdcPs_IntrEnable(XAdcPs *InstancePtr, u32 Mask)
+{
+ u32 RegValue;
+
+ /*
+ * Assert the arguments.
+ */
+ Xil_AssertVoid(InstancePtr != NULL);
+ Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+ /*
+ * Disable the specified interrupts in the IPIER.
+ */
+ RegValue = XAdcPs_ReadReg(InstancePtr->Config.BaseAddress,
+ XADCPS_INT_MASK_OFFSET);
+ RegValue &= ~(Mask & XADCPS_INTX_ALL_MASK);
+ XAdcPs_WriteReg(InstancePtr->Config.BaseAddress,
+ XADCPS_INT_MASK_OFFSET,
+ RegValue);
+}
+
+
+/****************************************************************************/
+/**
+*
+* This function disables the specified interrupts in the device.
+*
+* @param InstancePtr is a pointer to the XAdcPs instance.
+* @param Mask is the bit-mask of the interrupts to be disabled.
+* Bit positions of 1 will be disabled. Bit positions of 0 will
+* keep the previous setting. This mask is formed by OR'ing
+* XADCPS_INTX_* bits defined in xadcps_hw.h.
+*
+* @return None.
+*
+* @note None
+*
+*****************************************************************************/
+void XAdcPs_IntrDisable(XAdcPs *InstancePtr, u32 Mask)
+{
+ u32 RegValue;
+
+ /*
+ * Assert the arguments.
+ */
+ Xil_AssertVoid(InstancePtr != NULL);
+ Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+ /*
+ * Enable the specified interrupts in the IPIER.
+ */
+ RegValue = XAdcPs_ReadReg(InstancePtr->Config.BaseAddress,
+ XADCPS_INT_MASK_OFFSET);
+ RegValue |= (Mask & XADCPS_INTX_ALL_MASK);
+ XAdcPs_WriteReg(InstancePtr->Config.BaseAddress,
+ XADCPS_INT_MASK_OFFSET,
+ RegValue);
+}
+/****************************************************************************/
+/**
+*
+* This function returns the enabled interrupts read from the Interrupt Mask
+* Register (IPIER). Use the XADCPS_IPIXR_* constants defined in xadcps_hw.h to
+* interpret the returned value.
+*
+* @param InstancePtr is a pointer to the XAdcPs instance.
+*
+* @return A 32-bit value representing the contents of the I.
+*
+* @note None.
+*
+*****************************************************************************/
+u32 XAdcPs_IntrGetEnabled(XAdcPs *InstancePtr)
+{
+ /*
+ * Assert the arguments.
+ */
+ Xil_AssertNonvoid(InstancePtr != NULL);
+ Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+ /*
+ * Return the value read from the Interrupt Enable Register.
+ */
+ return (~ XAdcPs_ReadReg(InstancePtr->Config.BaseAddress,
+ XADCPS_INT_MASK_OFFSET) & XADCPS_INTX_ALL_MASK);
+}
+
+/****************************************************************************/
+/**
+*
+* This function returns the interrupt status read from Interrupt Status
+* Register(IPISR). Use the XADCPS_IPIXR_* constants defined in xadcps_hw.h
+* to interpret the returned value.
+*
+* @param InstancePtr is a pointer to the XAdcPs instance.
+*
+* @return A 32-bit value representing the contents of the IPISR.
+*
+* @note The device must be configured at hardware build time to include
+* interrupt component for this function to work.
+*
+*****************************************************************************/
+u32 XAdcPs_IntrGetStatus(XAdcPs *InstancePtr)
+{
+ /*
+ * Assert the arguments.
+ */
+ Xil_AssertNonvoid(InstancePtr != NULL);
+ Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+ /*
+ * Return the value read from the Interrupt Status register.
+ */
+ return XAdcPs_ReadReg(InstancePtr->Config.BaseAddress,
+ XADCPS_INT_STS_OFFSET) & XADCPS_INTX_ALL_MASK;
+}
+
+/****************************************************************************/
+/**
+*
+* This function clears the specified interrupts in the Interrupt Status
+* Register (IPISR).
+*
+* @param InstancePtr is a pointer to the XAdcPs instance.
+* @param Mask is the bit-mask of the interrupts to be cleared.
+* Bit positions of 1 will be cleared. Bit positions of 0 will not
+* change the previous interrupt status. This mask is formed by
+* OR'ing XADCPS_IPIXR_* bits which are defined in xadcps_hw.h.
+*
+* @return None.
+*
+* @note None.
+*
+*****************************************************************************/
+void XAdcPs_IntrClear(XAdcPs *InstancePtr, u32 Mask)
+{
+ u32 RegValue;
+
+ /*
+ * Assert the arguments.
+ */
+ Xil_AssertVoid(InstancePtr != NULL);
+ Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+ /*
+ * Clear the specified interrupts in the Interrupt Status register.
+ */
+ RegValue = XAdcPs_ReadReg(InstancePtr->Config.BaseAddress,
+ XADCPS_INT_STS_OFFSET);
+ RegValue &= (Mask & XADCPS_INTX_ALL_MASK);
+ XAdcPs_WriteReg(InstancePtr->Config.BaseAddress, XADCPS_INT_STS_OFFSET,
+ RegValue);
+
+}
+/** @} */
diff --git a/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/xadcps_v2_3/src/xadcps_selftest.c b/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/xadcps_v2_3/src/xadcps_selftest.c
new file mode 100644
index 0000000..a8a5065
--- /dev/null
+++ b/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/xadcps_v2_3/src/xadcps_selftest.c
@@ -0,0 +1,135 @@
+/******************************************************************************
+*
+* Copyright (C) 2011 - 2014 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+* THE SOFTWARE.
+*
+*
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xadcps_selftest.c
+* @addtogroup xadcps_v2_3
+* @{
+*
+* This file contains a diagnostic self test function for the XAdcPs driver.
+* The self test function does a simple read/write test of the Alarm Threshold
+* Register.
+*
+* See xadcps.h for more information.
+*
+* @note None.
+*
+* <pre>
+*
+* MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ----- ----- -------- -----------------------------------------------------
+* 1.00a ssb 12/22/11 First release based on the XPS/AXI xadc driver
+*
+* </pre>
+*
+*****************************************************************************/
+
+/***************************** Include Files ********************************/
+
+#include "xadcps.h"
+
+/************************** Constant Definitions ****************************/
+
+/*
+ * The following constant defines the test value to be written
+ * to the Alarm Threshold Register
+ */
+#define XADCPS_ATR_TEST_VALUE 0x55
+
+/**************************** Type Definitions ******************************/
+
+/***************** Macros (Inline Functions) Definitions ********************/
+
+/************************** Variable Definitions ****************************/
+
+/************************** Function Prototypes *****************************/
+
+/*****************************************************************************/
+/**
+*
+* Run a self-test on the driver/device. The test
+* - Resets the device,
+* - Writes a value into the Alarm Threshold register and reads it back
+* for comparison.
+* - Resets the device again.
+*
+*
+* @param InstancePtr is a pointer to the XAdcPs instance.
+*
+* @return
+* - XST_SUCCESS if the value read from the Alarm Threshold
+* register is the same as the value written.
+* - XST_FAILURE Otherwise
+*
+* @note This is a destructive test in that resets of the device are
+* performed. Refer to the device specification for the
+* device status after the reset operation.
+*
+******************************************************************************/
+int XAdcPs_SelfTest(XAdcPs *InstancePtr)
+{
+ int Status;
+ u32 RegValue;
+
+ /*
+ * Assert the argument
+ */
+ Xil_AssertNonvoid(InstancePtr != NULL);
+ Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+
+ /*
+ * Reset the device to get it back to its default state
+ */
+ XAdcPs_Reset(InstancePtr);
+
+ /*
+ * Write a value into the Alarm Threshold registers, read it back, and
+ * do the comparison
+ */
+ XAdcPs_SetAlarmThreshold(InstancePtr, XADCPS_ATR_VCCINT_UPPER,
+ XADCPS_ATR_TEST_VALUE);
+ RegValue = XAdcPs_GetAlarmThreshold(InstancePtr, XADCPS_ATR_VCCINT_UPPER);
+
+ if (RegValue == XADCPS_ATR_TEST_VALUE) {
+ Status = XST_SUCCESS;
+ } else {
+ Status = XST_FAILURE;
+ }
+
+ /*
+ * Reset the device again to its default state.
+ */
+ XAdcPs_Reset(InstancePtr);
+ /*
+ * Return the test result.
+ */
+ return Status;
+}
+/** @} */
diff --git a/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/xadcps_v2_3/src/xadcps_sinit.c b/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/xadcps_v2_3/src/xadcps_sinit.c
new file mode 100644
index 0000000..4277027
--- /dev/null
+++ b/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/xadcps_v2_3/src/xadcps_sinit.c
@@ -0,0 +1,97 @@
+/******************************************************************************
+*
+* Copyright (C) 2011 - 2014 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+* THE SOFTWARE.
+*
+*
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xadcps_sinit.c
+* @addtogroup xadcps_v2_3
+* @{
+*
+* This file contains the implementation of the XAdcPs driver's static
+* initialization functionality.
+*
+* @note None.
+*
+* <pre>
+*
+* MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ----- ----- -------- -----------------------------------------------------
+* 1.00a ssb 12/22/11 First release based on the XPS/AXI XADC driver
+*
+* </pre>
+*
+******************************************************************************/
+
+/***************************** Include Files *********************************/
+
+#include "xparameters.h"
+#include "xadcps.h"
+
+/************************** Constant Definitions *****************************/
+
+/**************************** Type Definitions *******************************/
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/************************** Function Prototypes ******************************/
+
+/************************** Variable Definitions *****************************/
+extern XAdcPs_Config XAdcPs_ConfigTable[];
+
+/*****************************************************************************/
+/**
+*
+* This function looks up the device configuration based on the unique device ID.
+* The table XAdcPs_ConfigTable contains the configuration info for each device
+* in the system.
+*
+* @param DeviceId contains the ID of the device for which the
+* device configuration pointer is to be returned.
+*
+* @return
+* - A pointer to the configuration found.
+* - NULL if the specified device ID was not found.
+*
+* @note None.
+*
+******************************************************************************/
+XAdcPs_Config *XAdcPs_LookupConfig(u16 DeviceId)
+{
+ XAdcPs_Config *CfgPtr = NULL;
+ u32 Index;
+
+ for (Index=0; Index < 1; Index++) {
+ if (XAdcPs_ConfigTable[Index].DeviceId == DeviceId) {
+ CfgPtr = &XAdcPs_ConfigTable[Index];
+ break;
+ }
+ }
+
+ return CfgPtr;
+}
+/** @} */
diff --git a/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/xilffs_v4_2/src/Makefile b/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/xilffs_v4_2/src/Makefile
new file mode 100644
index 0000000..fae42d0
--- /dev/null
+++ b/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/xilffs_v4_2/src/Makefile
@@ -0,0 +1,81 @@
+###############################################################################
+#
+# Copyright (C) 2013 - 2015 Xilinx, Inc. All rights reserved.
+#
+# Permission is hereby granted, free of charge, to any person obtaining a copy
+# of this software and associated documentation files (the "Software"), to deal
+# in the Software without restriction, including without limitation the rights
+# to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+# copies of the Software, and to permit persons to whom the Software is
+# furnished to do so, subject to the following conditions:
+#
+# The above copyright notice and this permission notice shall be included in
+# all copies or substantial portions of the Software.
+#
+# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+# THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+# LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+# OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+# THE SOFTWARE.
+#
+#
+#
+###############################################################################
+
+COMPILER=
+ARCHIVER=
+CP=cp
+COMPILER_FLAGS =
+LIB=libxilffs.a
+
+ifeq ($(notdir $(COMPILER)) , iccarm)
+ EXTRA_ARCHIVE_FLAGS=--create
+else
+ifeq ($(notdir $(COMPILER)) , armcc)
+ EXTRA_ARCHIVE_FLAGS=--create
+else
+ifeq ($(notdir $(COMPILER)) , armclang)
+ EXTRA_ARCHIVE_FLAGS=-rc
+else
+ EXTRA_ARCHIVE_FLAGS=rc
+endif
+endif
+endif
+
+RELEASEDIR=../../../lib
+INCLUDEDIR=../../../include
+INCLUDES=-I./. -I${INCLUDEDIR}
+
+FATFS_DIR = .
+OUTS = *.o
+OBJECTS = $(addsuffix .o, $(basename $(wildcard *.c)))
+FATFS_SRCS := $(wildcard *.c)
+FATFS_OBJS = $(addprefix $(FATFS_DIR)/, $(FATFS_SRCS:%.c=%.o))
+
+INCLUDEFILES=$(FATFS_DIR)/include/ff.h \
+ $(FATFS_DIR)/include/ffconf.h \
+ $(FATFS_DIR)/include/diskio.h \
+ $(FATFS_DIR)/include/integer.h
+
+libs: libxilffs.a
+
+libxilffs.a: print_msg_fatfs $(FATFS_OBJS)
+ $(ARCHIVER) $(EXTRA_ARCHIVE_FLAGS) ${RELEASEDIR}/${LIB} ${FATFS_OBJS}
+
+print_msg_fatfs:
+ @echo "Compiling XilFFs Library"
+
+.PHONY: include
+include: libxilffs_includes
+
+libxilffs_includes:
+ ${CP} ${INCLUDEFILES} ${INCLUDEDIR}
+
+clean:
+ rm -rf $(FATFS_DIR)/${OBJECTS}
+ rm -rf ${RELEASEDIR}/${LIB}
+
+$(FATFS_DIR)/%.o: $(FATFS_DIR)/%.c $(INCLUDEFILES)
+ $(COMPILER) $(COMPILER_FLAGS) $(EXTRA_COMPILER_FLAGS) $(INCLUDES) -c $< -o $@
diff --git a/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/xilffs_v4_2/src/diskio.c b/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/xilffs_v4_2/src/diskio.c
new file mode 100644
index 0000000..1b53c8d
--- /dev/null
+++ b/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/xilffs_v4_2/src/diskio.c
@@ -0,0 +1,523 @@
+/*-----------------------------------------------------------------------*/
+/* Low level disk I/O module skeleton for FatFs (C)ChaN, 2016 */
+/*-----------------------------------------------------------------------*/
+
+/*****************************************************************************/
+/**
+*
+* @file diskio.c
+* This file is the glue layer between file system and
+* driver.
+* Description related to SD driver:
+* Process to use file system with SD
+* Select xilffs in SDK when creating a BSP
+* In SDK, set "fs_interface" to 1 to select SD interface.
+* This glue layer can currently be used only with one
+* SD controller enabled.
+* In order to use eMMC, in SDK set "Enable MMC" to 1. If not,
+* SD support is enabled by default.
+*
+* Description:
+* This glue layer initializes the host controller and SD card
+* in disk_initialize. If SD card supports it, 4-bit mode and
+* high speed mode will be enabled.
+* The default block size is 512 bytes.
+* disk_read and disk_write functions are used to read and
+* write files using ADMA2 in polled mode.
+* The file system can be used to read from and write to an
+* SD card that is already formatted as FATFS.
+*
+* <pre>
+* MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ----- ---- -------- -------------------------------------------------------
+* 1.00a hk 10/17/13 First release
+* 2.0 hk 02/12/14 Corrected status check in disk initialize. CR# 772072.
+* 2.1 hk 04/16/14 Move check for ExtCSD high speed bit set inside if
+* condition for high speed support.
+* Include xil_types.h irrespective of xsdps.h. CR# 797086.
+* 2.2 hk 07/28/14 Make changes to enable use of data cache.
+* 3.0 sk 12/04/14 Added support for micro SD without
+* WP/CD. CR# 810655.
+* Make changes for prototypes of disk_read and
+* disk_write according to latest version.
+* 12/15/14 Modified the code according to MISRAC 2012 Compliant.
+* Updated the FatFs to R0.10b
+* Removed alignment for local buffers as CacheInvalidate
+* will take care of it.
+* sg 03/03/15 Added card detection check logic
+* 04/28/15 Card detection only in case of card detection signal
+* 3.1 sk 06/04/15 Added support for SD1.
+* 3.2 sk 11/24/15 Considered the slot type before checking the CD/WP pins.
+* 3.3 sk 04/01/15 Added one second delay for checking CD pin.
+* 3.4 sk 06/09/16 Added support for mkfs.
+* 3.8 mj 07/31/17 Added support for RAM based FATfs.
+* mn 12/04/17 Resolve errors in XilFFS for ARMCC compiler
+* 3.9 mn 04/18/18 Resolve build warnings for xilffs library
+* mn 07/06/18 Fix Cppcheck and Doxygen warnings
+* 4.2 mn 08/16/19 Initialize Status variables with failure values
+* mn 09/25/19 Check if the SD is powered on or not in disk_status()
+*
+* </pre>
+*
+* @note
+*
+******************************************************************************/
+#include "diskio.h"
+#include "ff.h"
+#include "xil_types.h"
+
+#ifdef FILE_SYSTEM_INTERFACE_SD
+#include "xsdps.h" /* SD device driver */
+#endif
+#include "sleep.h"
+#include "xil_printf.h"
+
+#define HIGH_SPEED_SUPPORT 0x01U
+#define WIDTH_4_BIT_SUPPORT 0x4U
+#define SD_CLK_25_MHZ 25000000U
+#define SD_CLK_26_MHZ 26000000U
+#define SD_CLK_52_MHZ 52000000U
+#define EXT_CSD_DEVICE_TYPE_BYTE 196
+#define EXT_CSD_4_BIT_WIDTH_BYTE 183
+#define EXT_CSD_HIGH_SPEED_BYTE 185
+#define EXT_CSD_DEVICE_TYPE_HIGH_SPEED 0x3
+#define SD_CD_DELAY 10000U
+
+#ifdef FILE_SYSTEM_INTERFACE_RAM
+#include "xparameters.h"
+
+static char *dataramfs = NULL;
+
+#define BLOCKSIZE 1U
+#define SECTORSIZE 512U
+#define SECTORCNT (RAMFS_SIZE / SECTORSIZE)
+#endif
+
+/*--------------------------------------------------------------------------
+
+ Public Functions
+
+---------------------------------------------------------------------------*/
+
+/*
+ * Global variables
+ */
+static DSTATUS Stat[2] = {STA_NOINIT, STA_NOINIT}; /* Disk status */
+
+#ifdef FILE_SYSTEM_INTERFACE_SD
+static XSdPs SdInstance[2];
+static u32 BaseAddress;
+static u32 CardDetect;
+static u32 WriteProtect;
+static u32 SlotType[2];
+static u8 HostCntrlrVer[2];
+#endif
+
+/*-----------------------------------------------------------------------*/
+/* Get Disk Status */
+/*-----------------------------------------------------------------------*/
+
+/*****************************************************************************/
+/**
+*
+* Gets the status of the disk.
+* In case of SD, it checks whether card is present or not.
+*
+* @param pdrv - Drive number
+*
+* @return
+* 0 Status ok
+* STA_NOINIT Drive not initialized
+* STA_NODISK No medium in the drive
+* STA_PROTECT Write protected
+*
+* @note In case Card detect signal is not connected,
+* this function will not be able to check if card is present.
+*
+******************************************************************************/
+DSTATUS disk_status (
+ BYTE pdrv /* Drive number (0) */
+)
+{
+ DSTATUS s = Stat[pdrv];
+#ifdef FILE_SYSTEM_INTERFACE_SD
+ u32 StatusReg;
+ u32 DelayCount = 0;
+
+ if (SdInstance[pdrv].Config.BaseAddress == (u32)0) {
+#ifdef XPAR_XSDPS_1_DEVICE_ID
+ if(pdrv == 1) {
+ BaseAddress = XPAR_XSDPS_1_BASEADDR;
+ CardDetect = XPAR_XSDPS_1_HAS_CD;
+ WriteProtect = XPAR_XSDPS_1_HAS_WP;
+ } else {
+#endif
+ BaseAddress = XPAR_XSDPS_0_BASEADDR;
+ CardDetect = XPAR_XSDPS_0_HAS_CD;
+ WriteProtect = XPAR_XSDPS_0_HAS_WP;
+#ifdef XPAR_XSDPS_1_DEVICE_ID
+ }
+#endif
+ HostCntrlrVer[pdrv] = (u8)(XSdPs_ReadReg16(BaseAddress,
+ XSDPS_HOST_CTRL_VER_OFFSET) & XSDPS_HC_SPEC_VER_MASK);
+ if (HostCntrlrVer[pdrv] == XSDPS_HC_SPEC_V3) {
+ SlotType[pdrv] = XSdPs_ReadReg(BaseAddress,
+ XSDPS_CAPS_OFFSET) & XSDPS_CAPS_SLOT_TYPE_MASK;
+ } else {
+ SlotType[pdrv] = 0;
+ }
+ }
+
+ /* If SD is not powered up then mark it as not initialized */
+ if ((XSdPs_ReadReg8((u32)BaseAddress, XSDPS_POWER_CTRL_OFFSET) &
+ XSDPS_PC_BUS_PWR_MASK) == 0U) {
+ s |= STA_NOINIT;
+ }
+
+ StatusReg = XSdPs_GetPresentStatusReg((u32)BaseAddress);
+ if (SlotType[pdrv] != XSDPS_CAPS_EMB_SLOT) {
+ if (CardDetect) {
+ while ((StatusReg & XSDPS_PSR_CARD_INSRT_MASK) == 0U) {
+ if (DelayCount == 500U) {
+ s = STA_NODISK | STA_NOINIT;
+ goto Label;
+ } else {
+ /* Wait for 10 msec */
+ usleep(SD_CD_DELAY);
+ DelayCount++;
+ StatusReg = XSdPs_GetPresentStatusReg((u32)BaseAddress);
+ }
+ }
+ }
+ s &= ~STA_NODISK;
+ if (WriteProtect) {
+ if ((StatusReg & XSDPS_PSR_WPS_PL_MASK) == 0U){
+ s |= STA_PROTECT;
+ goto Label;
+ }
+ }
+ s &= ~STA_PROTECT;
+ } else {
+ s &= ~STA_NODISK & ~STA_PROTECT;
+ }
+
+
+Label:
+ Stat[pdrv] = s;
+#endif
+
+ return s;
+}
+
+/*-----------------------------------------------------------------------*/
+/* Initialize Disk Drive */
+/*-----------------------------------------------------------------------*/
+/*****************************************************************************/
+/**
+*
+* Initializes the drive.
+* In case of SD, it initializes the host controller and the card.
+* This function also selects additional settings such as bus width,
+* speed and block size.
+*
+* @param pdrv - Drive number
+*
+* @return s - which contains an OR of the following information
+* STA_NODISK Disk is not present
+* STA_NOINIT Drive not initialized
+* STA_PROTECT Drive is write protected
+* 0 or only STA_PROTECT both indicate successful initialization.
+*
+* @note
+*
+******************************************************************************/
+DSTATUS disk_initialize (
+ BYTE pdrv /* Physical drive number (0) */
+)
+{
+ DSTATUS s;
+#ifdef FILE_SYSTEM_INTERFACE_SD
+ s32 Status = XST_FAILURE;
+ XSdPs_Config *SdConfig;
+#endif
+
+ s = disk_status(pdrv);
+ if ((s & STA_NODISK) != 0U) {
+ return s;
+ }
+
+ /* If disk is already initialized */
+ if ((s & STA_NOINIT) == 0U) {
+ return s;
+ }
+
+#ifdef FILE_SYSTEM_INTERFACE_SD
+ if (CardDetect) {
+ /*
+ * Card detection check
+ * If the HC detects the No Card State, power will be cleared
+ */
+ while(!((XSDPS_PSR_CARD_DPL_MASK |
+ XSDPS_PSR_CARD_STABLE_MASK |
+ XSDPS_PSR_CARD_INSRT_MASK) ==
+ ( XSdPs_GetPresentStatusReg((u32)BaseAddress) &
+ (XSDPS_PSR_CARD_DPL_MASK |
+ XSDPS_PSR_CARD_STABLE_MASK |
+ XSDPS_PSR_CARD_INSRT_MASK))));
+ }
+
+ /*
+ * Initialize the host controller
+ */
+ SdConfig = XSdPs_LookupConfig((u16)pdrv);
+ if (NULL == SdConfig) {
+ s |= STA_NOINIT;
+ return s;
+ }
+
+ Status = XSdPs_CfgInitialize(&SdInstance[pdrv], SdConfig,
+ SdConfig->BaseAddress);
+ if (Status != XST_SUCCESS) {
+ s |= STA_NOINIT;
+ return s;
+ }
+
+ Status = XSdPs_CardInitialize(&SdInstance[pdrv]);
+ if (Status != XST_SUCCESS) {
+ s |= STA_NOINIT;
+ return s;
+ }
+
+
+ /*
+ * Disk is initialized.
+ * Store the same in Stat.
+ */
+ s &= (~STA_NOINIT);
+
+ Stat[pdrv] = s;
+#endif
+
+#ifdef FILE_SYSTEM_INTERFACE_RAM
+ /* Assign RAMFS address value from xparameters.h */
+ dataramfs = (char *)RAMFS_START_ADDR;
+
+ /* Clearing No init Status for RAM */
+ s &= (~STA_NOINIT);
+ Stat[pdrv] = s;
+#endif
+
+ return s;
+}
+
+
+/*-----------------------------------------------------------------------*/
+/* Read Sector(s) */
+/*-----------------------------------------------------------------------*/
+/*****************************************************************************/
+/**
+*
+* Reads the drive
+* In case of SD, it reads the SD card using ADMA2 in polled mode.
+*
+* @param pdrv - Drive number
+* @param *buff - Pointer to the data buffer to store read data
+* @param sector - Start sector number
+* @param count - Sector count
+*
+* @return
+* RES_OK Read successful
+* STA_NOINIT Drive not initialized
+* RES_ERROR Read not successful
+*
+* @note
+*
+******************************************************************************/
+DRESULT disk_read (
+ BYTE pdrv, /* Physical drive number (0) */
+ BYTE *buff, /* Pointer to the data buffer to store read data */
+ DWORD sector, /* Start sector number (LBA) */
+ UINT count /* Sector count (1..128) */
+)
+{
+ DSTATUS s;
+#ifdef FILE_SYSTEM_INTERFACE_SD
+ s32 Status = XST_FAILURE;
+ DWORD LocSector = sector;
+#endif
+
+ s = disk_status(pdrv);
+
+ if ((s & STA_NOINIT) != 0U) {
+ return RES_NOTRDY;
+ }
+ if (count == 0U) {
+ return RES_PARERR;
+ }
+
+#ifdef FILE_SYSTEM_INTERFACE_SD
+ /* Convert LBA to byte address if needed */
+ if ((SdInstance[pdrv].HCS) == 0U) {
+ LocSector *= (DWORD)XSDPS_BLK_SIZE_512_MASK;
+ }
+
+ Status = XSdPs_ReadPolled(&SdInstance[pdrv], (u32)LocSector, count, buff);
+ if (Status != XST_SUCCESS) {
+ return RES_ERROR;
+ }
+#endif
+
+#ifdef FILE_SYSTEM_INTERFACE_RAM
+ memcpy(buff, dataramfs + (sector * SECTORSIZE), count * SECTORSIZE);
+#endif
+
+ return RES_OK;
+}
+
+/*-----------------------------------------------------------------------*/
+/* Miscellaneous Functions */
+/*-----------------------------------------------------------------------*/
+
+DRESULT disk_ioctl (
+ BYTE pdrv, /* Physical drive number (0) */
+ BYTE cmd, /* Control code */
+ void *buff /* Buffer to send/receive control data */
+)
+{
+ DRESULT res = RES_ERROR;
+
+#ifdef FILE_SYSTEM_INTERFACE_SD
+ void *LocBuff = buff;
+ if ((disk_status(pdrv) & STA_NOINIT) != 0U) { /* Check if card is in the socket */
+ return RES_NOTRDY;
+ }
+
+ switch (cmd) {
+ case (BYTE)CTRL_SYNC : /* Make sure that no pending write process */
+ res = RES_OK;
+ break;
+
+ case (BYTE)GET_SECTOR_COUNT : /* Get number of sectors on the disk (DWORD) */
+ (*((DWORD *)(void *)LocBuff)) = (DWORD)SdInstance[pdrv].SectorCount;
+ res = RES_OK;
+ break;
+
+ case (BYTE)GET_BLOCK_SIZE : /* Get erase block size in unit of sector (DWORD) */
+ (*((DWORD *)((void *)LocBuff))) = ((DWORD)128);
+ res = RES_OK;
+ break;
+
+ default:
+ res = RES_PARERR;
+ break;
+ }
+#endif
+
+#ifdef FILE_SYSTEM_INTERFACE_RAM
+ switch (cmd) {
+ case (BYTE)CTRL_SYNC:
+ res = RES_OK;
+ break;
+ case (BYTE)GET_BLOCK_SIZE:
+ *(WORD *)buff = BLOCKSIZE;
+ res = RES_OK;
+ break;
+ case (BYTE)GET_SECTOR_SIZE:
+ *(WORD *)buff = SECTORSIZE;
+ res = RES_OK;
+ break;
+ case (BYTE)GET_SECTOR_COUNT:
+ *(DWORD *)buff = SECTORCNT;
+ res = RES_OK;
+ break;
+ default:
+ res = RES_PARERR;
+ break;
+ }
+#endif
+
+ return res;
+}
+
+/******************************************************************************/
+/**
+*
+* This function is User Provided Timer Function for FatFs module
+*
+* @return DWORD
+*
+* @note None
+*
+****************************************************************************/
+
+DWORD get_fattime (void)
+{
+ return ((DWORD)(2010U - 1980U) << 25U) /* Fixed to Jan. 1, 2010 */
+ | ((DWORD)1 << 21)
+ | ((DWORD)1 << 16)
+ | ((DWORD)0 << 11)
+ | ((DWORD)0 << 5)
+ | ((DWORD)0 >> 1);
+}
+
+/*****************************************************************************/
+/**
+*
+* Reads the drive
+* In case of SD, it reads the SD card using ADMA2 in polled mode.
+*
+* @param pdrv - Drive number
+* @param *buff - Pointer to the data to be written
+* @param sector - Sector address
+* @param count - Sector count
+*
+* @return
+* RES_OK Read successful
+* STA_NOINIT Drive not initialized
+* RES_ERROR Read not successful
+*
+* @note
+*
+******************************************************************************/
+DRESULT disk_write (
+ BYTE pdrv, /* Physical drive nmuber (0..) */
+ const BYTE *buff, /* Data to be written */
+ DWORD sector, /* Sector address (LBA) */
+ UINT count /* Number of sectors to write (1..128) */
+)
+{
+ DSTATUS s;
+#ifdef FILE_SYSTEM_INTERFACE_SD
+ s32 Status = XST_FAILURE;
+ DWORD LocSector = sector;
+#endif
+
+ s = disk_status(pdrv);
+ if ((s & STA_NOINIT) != 0U) {
+ return RES_NOTRDY;
+ }
+ if (count == 0U) {
+ return RES_PARERR;
+ }
+
+#ifdef FILE_SYSTEM_INTERFACE_SD
+ /* Convert LBA to byte address if needed */
+ if ((SdInstance[pdrv].HCS) == 0U) {
+ LocSector *= (DWORD)XSDPS_BLK_SIZE_512_MASK;
+ }
+
+ Status = XSdPs_WritePolled(&SdInstance[pdrv], (u32)LocSector, count, buff);
+ if (Status != XST_SUCCESS) {
+ return RES_ERROR;
+ }
+
+#endif
+
+#ifdef FILE_SYSTEM_INTERFACE_RAM
+ memcpy(dataramfs + (sector * SECTORSIZE), buff, count * SECTORSIZE);
+#endif
+
+ return RES_OK;
+}
diff --git a/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/xilffs_v4_2/src/ff.c b/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/xilffs_v4_2/src/ff.c
new file mode 100644
index 0000000..55dd919
--- /dev/null
+++ b/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/xilffs_v4_2/src/ff.c
@@ -0,0 +1,6564 @@
+/*----------------------------------------------------------------------------/
+/ FatFs - Generic FAT Filesystem Module R0.13b /
+/-----------------------------------------------------------------------------/
+/
+/ Copyright (C) 2018, ChaN, all right reserved.
+/
+/ FatFs module is an open source software. Redistribution and use of FatFs in
+/ source and binary forms, with or without modification, are permitted provided
+/ that the following condition is met:
+/
+/ 1. Redistributions of source code must retain the above copyright notice,
+/ this condition and the following disclaimer.
+/
+/ This software is provided by the copyright holder and contributors "AS IS"
+/ and any warranties related to this software are DISCLAIMED.
+/ The copyright owner or contributors be NOT LIABLE for any damages caused
+/ by use of this software.
+/
+/----------------------------------------------------------------------------*/
+
+/**
+*
+* MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ----- ---- -------- -------------------------------------------------------
+* 3.9 mn 04/18/18 Resolve build warnings for xilffs library
+* 4.2 aru 07/10/19 Fix Coverity warnings
+* mn 08/16/19 Initialize Status variables with failure values
+******************************************************************************/
+#include "xparameters.h"
+#if (defined FILE_SYSTEM_INTERFACE_SD) || (defined FILE_SYSTEM_INTERFACE_RAM)
+#include "ff.h" /* Declarations of FatFs API */
+#include "diskio.h" /* Declarations of device I/O functions */
+#include "xil_printf.h"
+
+
+/*--------------------------------------------------------------------------
+
+ Module Private Definitions
+
+---------------------------------------------------------------------------*/
+
+#if FF_DEFINED != 63463 /* Revision ID */
+#error Wrong include file (ff.h).
+#endif
+
+
+/* Character code support macros */
+#define IsUpper(c) ((c) >= 'A' && (c) <= 'Z')
+#define IsLower(c) ((c) >= 'a' && (c) <= 'z')
+#define IsDigit(c) ((c) >= '0' && (c) <= '9')
+#define IsSurrogate(c) ((c) >= 0xD800 && (c) <= 0xDFFF)
+#define IsSurrogateH(c) ((c) >= 0xD800 && (c) <= 0xDBFF)
+#define IsSurrogateL(c) ((c) >= 0xDC00 && (c) <= 0xDFFF)
+
+
+/* Additional file attribute bits for internal use */
+#define AM_VOL 0x08 /* Volume label */
+#define AM_LFN 0x0F /* LFN entry */
+#define AM_MASK 0x3F /* Mask of defined bits */
+
+
+/* Additional file access control and file status flags for internal use */
+#define FA_SEEKEND 0x20 /* Seek to end of the file on file open */
+#define FA_MODIFIED 0x40 /* File has been modified */
+#define FA_DIRTY 0x80 /* FIL.buf[] needs to be written-back */
+
+
+/* Name status flags in fn[11] */
+#define NSFLAG 11 /* Index of the name status byte */
+#define NS_LOSS 0x01 /* Out of 8.3 format */
+#define NS_LFN 0x02 /* Force to create LFN entry */
+#define NS_LAST 0x04 /* Last segment */
+#define NS_BODY 0x08 /* Lower case flag (body) */
+#define NS_EXT 0x10 /* Lower case flag (ext) */
+#define NS_DOT 0x20 /* Dot entry */
+#define NS_NOLFN 0x40 /* Do not find LFN */
+#define NS_NONAME 0x80 /* Not followed */
+
+
+/* Limits and boundaries */
+#define MAX_DIR 0x200000 /* Max size of FAT directory */
+#define MAX_DIR_EX 0x10000000 /* Max size of exFAT directory */
+#define MAX_FAT12 0xFF5 /* Max FAT12 clusters (differs from specs, but right for real DOS/Windows behavior) */
+#define MAX_FAT16 0xFFF5 /* Max FAT16 clusters (differs from specs, but right for real DOS/Windows behavior) */
+#define MAX_FAT32 0x0FFFFFF5 /* Max FAT32 clusters (not specified, practical limit) */
+#define MAX_EXFAT 0x7FFFFFFD /* Max exFAT clusters (differs from specs, implementation limit) */
+
+
+/* FatFs refers the FAT structure as simple byte array instead of structure member
+/ because the C structure is not binary compatible between different platforms */
+
+#define BS_JmpBoot 0 /* x86 jump instruction (3-byte) */
+#define BS_OEMName 3 /* OEM name (8-byte) */
+#define BPB_BytsPerSec 11 /* Sector size [byte] (WORD) */
+#define BPB_SecPerClus 13 /* Cluster size [sector] (BYTE) */
+#define BPB_RsvdSecCnt 14 /* Size of reserved area [sector] (WORD) */
+#define BPB_NumFATs 16 /* Number of FATs (BYTE) */
+#define BPB_RootEntCnt 17 /* Size of root directory area for FAT [entry] (WORD) */
+#define BPB_TotSec16 19 /* Volume size (16-bit) [sector] (WORD) */
+#define BPB_Media 21 /* Media descriptor byte (BYTE) */
+#define BPB_FATSz16 22 /* FAT size (16-bit) [sector] (WORD) */
+#define BPB_SecPerTrk 24 /* Number of sectors per track for int13h [sector] (WORD) */
+#define BPB_NumHeads 26 /* Number of heads for int13h (WORD) */
+#define BPB_HiddSec 28 /* Volume offset from top of the drive (DWORD) */
+#define BPB_TotSec32 32 /* Volume size (32-bit) [sector] (DWORD) */
+#define BS_DrvNum 36 /* Physical drive number for int13h (BYTE) */
+#define BS_NTres 37 /* WindowsNT error flag (BYTE) */
+#define BS_BootSig 38 /* Extended boot signature (BYTE) */
+#define BS_VolID 39 /* Volume serial number (DWORD) */
+#define BS_VolLab 43 /* Volume label string (8-byte) */
+#define BS_FilSysType 54 /* Filesystem type string (8-byte) */
+#define BS_BootCode 62 /* Boot code (448-byte) */
+#define BS_55AA 510 /* Signature word (WORD) */
+
+#define BPB_FATSz32 36 /* FAT32: FAT size [sector] (DWORD) */
+#define BPB_ExtFlags32 40 /* FAT32: Extended flags (WORD) */
+#define BPB_FSVer32 42 /* FAT32: Filesystem version (WORD) */
+#define BPB_RootClus32 44 /* FAT32: Root directory cluster (DWORD) */
+#define BPB_FSInfo32 48 /* FAT32: Offset of FSINFO sector (WORD) */
+#define BPB_BkBootSec32 50 /* FAT32: Offset of backup boot sector (WORD) */
+#define BS_DrvNum32 64 /* FAT32: Physical drive number for int13h (BYTE) */
+#define BS_NTres32 65 /* FAT32: Error flag (BYTE) */
+#define BS_BootSig32 66 /* FAT32: Extended boot signature (BYTE) */
+#define BS_VolID32 67 /* FAT32: Volume serial number (DWORD) */
+#define BS_VolLab32 71 /* FAT32: Volume label string (8-byte) */
+#define BS_FilSysType32 82 /* FAT32: Filesystem type string (8-byte) */
+#define BS_BootCode32 90 /* FAT32: Boot code (420-byte) */
+
+#define BPB_ZeroedEx 11 /* exFAT: MBZ field (53-byte) */
+#define BPB_VolOfsEx 64 /* exFAT: Volume offset from top of the drive [sector] (QWORD) */
+#define BPB_TotSecEx 72 /* exFAT: Volume size [sector] (QWORD) */
+#define BPB_FatOfsEx 80 /* exFAT: FAT offset from top of the volume [sector] (DWORD) */
+#define BPB_FatSzEx 84 /* exFAT: FAT size [sector] (DWORD) */
+#define BPB_DataOfsEx 88 /* exFAT: Data offset from top of the volume [sector] (DWORD) */
+#define BPB_NumClusEx 92 /* exFAT: Number of clusters (DWORD) */
+#define BPB_RootClusEx 96 /* exFAT: Root directory start cluster (DWORD) */
+#define BPB_VolIDEx 100 /* exFAT: Volume serial number (DWORD) */
+#define BPB_FSVerEx 104 /* exFAT: Filesystem version (WORD) */
+#define BPB_VolFlagEx 106 /* exFAT: Volume flags (WORD) */
+#define BPB_BytsPerSecEx 108 /* exFAT: Log2 of sector size in unit of byte (BYTE) */
+#define BPB_SecPerClusEx 109 /* exFAT: Log2 of cluster size in unit of sector (BYTE) */
+#define BPB_NumFATsEx 110 /* exFAT: Number of FATs (BYTE) */
+#define BPB_DrvNumEx 111 /* exFAT: Physical drive number for int13h (BYTE) */
+#define BPB_PercInUseEx 112 /* exFAT: Percent in use (BYTE) */
+#define BPB_RsvdEx 113 /* exFAT: Reserved (7-byte) */
+#define BS_BootCodeEx 120 /* exFAT: Boot code (390-byte) */
+
+#define DIR_Name 0 /* Short file name (11-byte) */
+#define DIR_Attr 11 /* Attribute (BYTE) */
+#define DIR_NTres 12 /* Lower case flag (BYTE) */
+#define DIR_CrtTime10 13 /* Created time sub-second (BYTE) */
+#define DIR_CrtTime 14 /* Created time (DWORD) */
+#define DIR_LstAccDate 18 /* Last accessed date (WORD) */
+#define DIR_FstClusHI 20 /* Higher 16-bit of first cluster (WORD) */
+#define DIR_ModTime 22 /* Modified time (DWORD) */
+#define DIR_FstClusLO 26 /* Lower 16-bit of first cluster (WORD) */
+#define DIR_FileSize 28 /* File size (DWORD) */
+#define LDIR_Ord 0 /* LFN: LFN order and LLE flag (BYTE) */
+#define LDIR_Attr 11 /* LFN: LFN attribute (BYTE) */
+#define LDIR_Type 12 /* LFN: Entry type (BYTE) */
+#define LDIR_Chksum 13 /* LFN: Checksum of the SFN (BYTE) */
+#define LDIR_FstClusLO 26 /* LFN: MBZ field (WORD) */
+#define XDIR_Type 0 /* exFAT: Type of exFAT directory entry (BYTE) */
+#define XDIR_NumLabel 1 /* exFAT: Number of volume label characters (BYTE) */
+#define XDIR_Label 2 /* exFAT: Volume label (11-WORD) */
+#define XDIR_CaseSum 4 /* exFAT: Sum of case conversion table (DWORD) */
+#define XDIR_NumSec 1 /* exFAT: Number of secondary entries (BYTE) */
+#define XDIR_SetSum 2 /* exFAT: Sum of the set of directory entries (WORD) */
+#define XDIR_Attr 4 /* exFAT: File attribute (WORD) */
+#define XDIR_CrtTime 8 /* exFAT: Created time (DWORD) */
+#define XDIR_ModTime 12 /* exFAT: Modified time (DWORD) */
+#define XDIR_AccTime 16 /* exFAT: Last accessed time (DWORD) */
+#define XDIR_CrtTime10 20 /* exFAT: Created time subsecond (BYTE) */
+#define XDIR_ModTime10 21 /* exFAT: Modified time subsecond (BYTE) */
+#define XDIR_CrtTZ 22 /* exFAT: Created timezone (BYTE) */
+#define XDIR_ModTZ 23 /* exFAT: Modified timezone (BYTE) */
+#define XDIR_AccTZ 24 /* exFAT: Last accessed timezone (BYTE) */
+#define XDIR_GenFlags 33 /* exFAT: General secondary flags (BYTE) */
+#define XDIR_NumName 35 /* exFAT: Number of file name characters (BYTE) */
+#define XDIR_NameHash 36 /* exFAT: Hash of file name (WORD) */
+#define XDIR_ValidFileSize 40 /* exFAT: Valid file size (QWORD) */
+#define XDIR_FstClus 52 /* exFAT: First cluster of the file data (DWORD) */
+#define XDIR_FileSize 56 /* exFAT: File/Directory size (QWORD) */
+
+#define SZDIRE 32 /* Size of a directory entry */
+#define DDEM 0xE5 /* Deleted directory entry mark set to DIR_Name[0] */
+#define RDDEM 0x05 /* Replacement of the character collides with DDEM */
+#define LLEF 0x40 /* Last long entry flag in LDIR_Ord */
+
+#define FSI_LeadSig 0 /* FAT32 FSI: Leading signature (DWORD) */
+#define FSI_StrucSig 484 /* FAT32 FSI: Structure signature (DWORD) */
+#define FSI_Free_Count 488 /* FAT32 FSI: Number of free clusters (DWORD) */
+#define FSI_Nxt_Free 492 /* FAT32 FSI: Last allocated cluster (DWORD) */
+
+#define MBR_Table 446 /* MBR: Offset of partition table in the MBR */
+#define SZ_PTE 16 /* MBR: Size of a partition table entry */
+#define PTE_Boot 0 /* MBR PTE: Boot indicator */
+#define PTE_StHead 1 /* MBR PTE: Start head */
+#define PTE_StSec 2 /* MBR PTE: Start sector */
+#define PTE_StCyl 3 /* MBR PTE: Start cylinder */
+#define PTE_System 4 /* MBR PTE: System ID */
+#define PTE_EdHead 5 /* MBR PTE: End head */
+#define PTE_EdSec 6 /* MBR PTE: End sector */
+#define PTE_EdCyl 7 /* MBR PTE: End cylinder */
+#define PTE_StLba 8 /* MBR PTE: Start in LBA */
+#define PTE_SizLba 12 /* MBR PTE: Size in LBA */
+
+
+/* Post process on fatal error in the file operations */
+#define ABORT(fs, res) { fp->err = (BYTE)(res); LEAVE_FF(fs, res); }
+
+
+/* Re-entrancy related */
+#if FF_FS_REENTRANT
+#if FF_USE_LFN == 1
+#error Static LFN work area cannot be used at thread-safe configuration
+#endif
+#define LEAVE_FF(fs, res) { unlock_fs(fs, res); return res; }
+#else
+#define LEAVE_FF(fs, res) return res
+#endif
+
+
+/* Definitions of volume - physical location conversion */
+#if FF_MULTI_PARTITION
+#define LD2PD(vol) VolToPart[vol].pd /* Get physical drive number */
+#define LD2PT(vol) VolToPart[vol].pt /* Get partition index */
+#else
+#define LD2PD(vol) (BYTE)(vol) /* Each logical drive is bound to the same physical drive number */
+#define LD2PT(vol) 0 /* Find first valid partition or in SFD */
+#endif
+
+
+/* Definitions of sector size */
+#if (FF_MAX_SS < FF_MIN_SS) || (FF_MAX_SS != 512 && FF_MAX_SS != 1024 && FF_MAX_SS != 2048 && FF_MAX_SS != 4096) || (FF_MIN_SS != 512 && FF_MIN_SS != 1024 && FF_MIN_SS != 2048 && FF_MIN_SS != 4096)
+#error Wrong sector size configuration
+#endif
+#if FF_MAX_SS == FF_MIN_SS
+#define SS(fs) ((UINT)FF_MAX_SS) /* Fixed sector size */
+#else
+#define SS(fs) ((fs)->ssize) /* Variable sector size */
+#endif
+
+
+/* Timestamp */
+#if FF_FS_NORTC == 1
+#if FF_NORTC_YEAR < 1980 || FF_NORTC_YEAR > 2107 || FF_NORTC_MON < 1 || FF_NORTC_MON > 12 || FF_NORTC_MDAY < 1 || FF_NORTC_MDAY > 31
+#error Invalid FF_FS_NORTC settings
+#endif
+#define GET_FATTIME() ((DWORD)(FF_NORTC_YEAR - 1980) << 25 | (DWORD)FF_NORTC_MON << 21 | (DWORD)FF_NORTC_MDAY << 16)
+#else
+#define GET_FATTIME() get_fattime()
+#endif
+
+
+/* File lock controls */
+#if FF_FS_LOCK != 0
+#if FF_FS_READONLY
+#error FF_FS_LOCK must be 0 at read-only configuration
+#endif
+typedef struct {
+ FATFS *fs; /* Object ID 1, volume (NULL:blank entry) */
+ DWORD clu; /* Object ID 2, containing directory (0:root) */
+ DWORD ofs; /* Object ID 3, offset in the directory */
+ WORD ctr; /* Object open counter, 0:none, 0x01..0xFF:read mode open count, 0x100:write mode */
+} FILESEM;
+#endif
+
+
+/* SBCS up-case tables (\x80-\xFF) */
+#define TBL_CT437 {0x80,0x9A,0x45,0x41,0x8E,0x41,0x8F,0x80,0x45,0x45,0x45,0x49,0x49,0x49,0x8E,0x8F, \
+ 0x90,0x92,0x92,0x4F,0x99,0x4F,0x55,0x55,0x59,0x99,0x9A,0x9B,0x9C,0x9D,0x9E,0x9F, \
+ 0x41,0x49,0x4F,0x55,0xA5,0xA5,0xA6,0xA7,0xA8,0xA9,0xAA,0xAB,0xAC,0xAD,0xAE,0xAF, \
+ 0xB0,0xB1,0xB2,0xB3,0xB4,0xB5,0xB6,0xB7,0xB8,0xB9,0xBA,0xBB,0xBC,0xBD,0xBE,0xBF, \
+ 0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF, \
+ 0xD0,0xD1,0xD2,0xD3,0xD4,0xD5,0xD6,0xD7,0xD8,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0xDF, \
+ 0xE0,0xE1,0xE2,0xE3,0xE4,0xE5,0xE6,0xE7,0xE8,0xE9,0xEA,0xEB,0xEC,0xED,0xEE,0xEF, \
+ 0xF0,0xF1,0xF2,0xF3,0xF4,0xF5,0xF6,0xF7,0xF8,0xF9,0xFA,0xFB,0xFC,0xFD,0xFE,0xFF}
+#define TBL_CT720 {0x80,0x81,0x82,0x83,0x84,0x85,0x86,0x87,0x88,0x89,0x8A,0x8B,0x8C,0x8D,0x8E,0x8F, \
+ 0x90,0x91,0x92,0x93,0x94,0x95,0x96,0x97,0x98,0x99,0x9A,0x9B,0x9C,0x9D,0x9E,0x9F, \
+ 0xA0,0xA1,0xA2,0xA3,0xA4,0xA5,0xA6,0xA7,0xA8,0xA9,0xAA,0xAB,0xAC,0xAD,0xAE,0xAF, \
+ 0xB0,0xB1,0xB2,0xB3,0xB4,0xB5,0xB6,0xB7,0xB8,0xB9,0xBA,0xBB,0xBC,0xBD,0xBE,0xBF, \
+ 0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF, \
+ 0xD0,0xD1,0xD2,0xD3,0xD4,0xD5,0xD6,0xD7,0xD8,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0xDF, \
+ 0xE0,0xE1,0xE2,0xE3,0xE4,0xE5,0xE6,0xE7,0xE8,0xE9,0xEA,0xEB,0xEC,0xED,0xEE,0xEF, \
+ 0xF0,0xF1,0xF2,0xF3,0xF4,0xF5,0xF6,0xF7,0xF8,0xF9,0xFA,0xFB,0xFC,0xFD,0xFE,0xFF}
+#define TBL_CT737 {0x80,0x81,0x82,0x83,0x84,0x85,0x86,0x87,0x88,0x89,0x8A,0x8B,0x8C,0x8D,0x8E,0x8F, \
+ 0x90,0x92,0x92,0x93,0x94,0x95,0x96,0x97,0x80,0x81,0x82,0x83,0x84,0x85,0x86,0x87, \
+ 0x88,0x89,0x8A,0x8B,0x8C,0x8D,0x8E,0x8F,0x90,0x91,0xAA,0x92,0x93,0x94,0x95,0x96, \
+ 0xB0,0xB1,0xB2,0xB3,0xB4,0xB5,0xB6,0xB7,0xB8,0xB9,0xBA,0xBB,0xBC,0xBD,0xBE,0xBF, \
+ 0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF, \
+ 0xD0,0xD1,0xD2,0xD3,0xD4,0xD5,0xD6,0xD7,0xD8,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0xDF, \
+ 0x97,0xEA,0xEB,0xEC,0xE4,0xED,0xEE,0xEF,0xF5,0xF0,0xEA,0xEB,0xEC,0xED,0xEE,0xEF, \
+ 0xF0,0xF1,0xF2,0xF3,0xF4,0xF5,0xF6,0xF7,0xF8,0xF9,0xFA,0xFB,0xFC,0xFD,0xFE,0xFF}
+#define TBL_CT771 {0x80,0x81,0x82,0x83,0x84,0x85,0x86,0x87,0x88,0x89,0x8A,0x8B,0x8C,0x8D,0x8E,0x8F, \
+ 0x90,0x91,0x92,0x93,0x94,0x95,0x96,0x97,0x98,0x99,0x9A,0x9B,0x9C,0x9D,0x9E,0x9F, \
+ 0x80,0x81,0x82,0x83,0x84,0x85,0x86,0x87,0x88,0x89,0x8A,0x8B,0x8C,0x8D,0x8E,0x8F, \
+ 0xB0,0xB1,0xB2,0xB3,0xB4,0xB5,0xB6,0xB7,0xB8,0xB9,0xBA,0xBB,0xBC,0xBD,0xBE,0xBF, \
+ 0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF, \
+ 0xD0,0xD1,0xD2,0xD3,0xD4,0xD5,0xD6,0xD7,0xD8,0xD9,0xDA,0xDB,0xDC,0xDC,0xDE,0xDE, \
+ 0x90,0x91,0x92,0x93,0x94,0x95,0x96,0x97,0x98,0x99,0x9A,0x9B,0x9C,0x9D,0x9E,0x9F, \
+ 0xF0,0xF0,0xF2,0xF2,0xF4,0xF4,0xF6,0xF6,0xF8,0xF8,0xFA,0xFA,0xFC,0xFC,0xFE,0xFF}
+#define TBL_CT775 {0x80,0x9A,0x91,0xA0,0x8E,0x95,0x8F,0x80,0xAD,0xED,0x8A,0x8A,0xA1,0x8D,0x8E,0x8F, \
+ 0x90,0x92,0x92,0xE2,0x99,0x95,0x96,0x97,0x97,0x99,0x9A,0x9D,0x9C,0x9D,0x9E,0x9F, \
+ 0xA0,0xA1,0xE0,0xA3,0xA3,0xA5,0xA6,0xA7,0xA8,0xA9,0xAA,0xAB,0xAC,0xAD,0xAE,0xAF, \
+ 0xB0,0xB1,0xB2,0xB3,0xB4,0xB5,0xB6,0xB7,0xB8,0xB9,0xBA,0xBB,0xBC,0xBD,0xBE,0xBF, \
+ 0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF, \
+ 0xB5,0xB6,0xB7,0xB8,0xBD,0xBE,0xC6,0xC7,0xA5,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0xDF, \
+ 0xE0,0xE1,0xE2,0xE3,0xE5,0xE5,0xE6,0xE3,0xE8,0xE8,0xEA,0xEA,0xEE,0xED,0xEE,0xEF, \
+ 0xF0,0xF1,0xF2,0xF3,0xF4,0xF5,0xF6,0xF7,0xF8,0xF9,0xFA,0xFB,0xFC,0xFD,0xFE,0xFF}
+#define TBL_CT850 {0x43,0x55,0x45,0x41,0x41,0x41,0x41,0x43,0x45,0x45,0x45,0x49,0x49,0x49,0x41,0x41, \
+ 0x45,0x92,0x92,0x4F,0x4F,0x4F,0x55,0x55,0x59,0x4F,0x55,0x4F,0x9C,0x4F,0x9E,0x9F, \
+ 0x41,0x49,0x4F,0x55,0xA5,0xA5,0xA6,0xA7,0xA8,0xA9,0xAA,0xAB,0xAC,0xAD,0xAE,0xAF, \
+ 0xB0,0xB1,0xB2,0xB3,0xB4,0x41,0x41,0x41,0xB8,0xB9,0xBA,0xBB,0xBC,0xBD,0xBE,0xBF, \
+ 0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0x41,0x41,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF, \
+ 0xD1,0xD1,0x45,0x45,0x45,0x49,0x49,0x49,0x49,0xD9,0xDA,0xDB,0xDC,0xDD,0x49,0xDF, \
+ 0x4F,0xE1,0x4F,0x4F,0x4F,0x4F,0xE6,0xE8,0xE8,0x55,0x55,0x55,0x59,0x59,0xEE,0xEF, \
+ 0xF0,0xF1,0xF2,0xF3,0xF4,0xF5,0xF6,0xF7,0xF8,0xF9,0xFA,0xFB,0xFC,0xFD,0xFE,0xFF}
+#define TBL_CT852 {0x80,0x9A,0x90,0xB6,0x8E,0xDE,0x8F,0x80,0x9D,0xD3,0x8A,0x8A,0xD7,0x8D,0x8E,0x8F, \
+ 0x90,0x91,0x91,0xE2,0x99,0x95,0x95,0x97,0x97,0x99,0x9A,0x9B,0x9B,0x9D,0x9E,0xAC, \
+ 0xB5,0xD6,0xE0,0xE9,0xA4,0xA4,0xA6,0xA6,0xA8,0xA8,0xAA,0x8D,0xAC,0xB8,0xAE,0xAF, \
+ 0xB0,0xB1,0xB2,0xB3,0xB4,0xB5,0xB6,0xB7,0xB8,0xB9,0xBA,0xBB,0xBC,0xBD,0xBD,0xBF, \
+ 0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC6,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF, \
+ 0xD1,0xD1,0xD2,0xD3,0xD2,0xD5,0xD6,0xD7,0xB7,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0xDF, \
+ 0xE0,0xE1,0xE2,0xE3,0xE3,0xD5,0xE6,0xE6,0xE8,0xE9,0xE8,0xEB,0xED,0xED,0xDD,0xEF, \
+ 0xF0,0xF1,0xF2,0xF3,0xF4,0xF5,0xF6,0xF7,0xF8,0xF9,0xFA,0xEB,0xFC,0xFC,0xFE,0xFF}
+#define TBL_CT855 {0x81,0x81,0x83,0x83,0x85,0x85,0x87,0x87,0x89,0x89,0x8B,0x8B,0x8D,0x8D,0x8F,0x8F, \
+ 0x91,0x91,0x93,0x93,0x95,0x95,0x97,0x97,0x99,0x99,0x9B,0x9B,0x9D,0x9D,0x9F,0x9F, \
+ 0xA1,0xA1,0xA3,0xA3,0xA5,0xA5,0xA7,0xA7,0xA9,0xA9,0xAB,0xAB,0xAD,0xAD,0xAE,0xAF, \
+ 0xB0,0xB1,0xB2,0xB3,0xB4,0xB6,0xB6,0xB8,0xB8,0xB9,0xBA,0xBB,0xBC,0xBE,0xBE,0xBF, \
+ 0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC7,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF, \
+ 0xD1,0xD1,0xD3,0xD3,0xD5,0xD5,0xD7,0xD7,0xDD,0xD9,0xDA,0xDB,0xDC,0xDD,0xE0,0xDF, \
+ 0xE0,0xE2,0xE2,0xE4,0xE4,0xE6,0xE6,0xE8,0xE8,0xEA,0xEA,0xEC,0xEC,0xEE,0xEE,0xEF, \
+ 0xF0,0xF2,0xF2,0xF4,0xF4,0xF6,0xF6,0xF8,0xF8,0xFA,0xFA,0xFC,0xFC,0xFD,0xFE,0xFF}
+#define TBL_CT857 {0x80,0x9A,0x90,0xB6,0x8E,0xB7,0x8F,0x80,0xD2,0xD3,0xD4,0xD8,0xD7,0x49,0x8E,0x8F, \
+ 0x90,0x92,0x92,0xE2,0x99,0xE3,0xEA,0xEB,0x98,0x99,0x9A,0x9D,0x9C,0x9D,0x9E,0x9E, \
+ 0xB5,0xD6,0xE0,0xE9,0xA5,0xA5,0xA6,0xA6,0xA8,0xA9,0xAA,0xAB,0xAC,0xAD,0xAE,0xAF, \
+ 0xB0,0xB1,0xB2,0xB3,0xB4,0xB5,0xB6,0xB7,0xB8,0xB9,0xBA,0xBB,0xBC,0xBD,0xBE,0xBF, \
+ 0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC7,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF, \
+ 0xD0,0xD1,0xD2,0xD3,0xD4,0x49,0xD6,0xD7,0xD8,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0xDF, \
+ 0xE0,0xE1,0xE2,0xE3,0xE5,0xE5,0xE6,0xE7,0xE8,0xE9,0xEA,0xEB,0xDE,0xED,0xEE,0xEF, \
+ 0xF0,0xF1,0xF2,0xF3,0xF4,0xF5,0xF6,0xF7,0xF8,0xF9,0xFA,0xFB,0xFC,0xFD,0xFE,0xFF}
+#define TBL_CT860 {0x80,0x9A,0x90,0x8F,0x8E,0x91,0x86,0x80,0x89,0x89,0x92,0x8B,0x8C,0x98,0x8E,0x8F, \
+ 0x90,0x91,0x92,0x8C,0x99,0xA9,0x96,0x9D,0x98,0x99,0x9A,0x9B,0x9C,0x9D,0x9E,0x9F, \
+ 0x86,0x8B,0x9F,0x96,0xA5,0xA5,0xA6,0xA7,0xA8,0xA9,0xAA,0xAB,0xAC,0xAD,0xAE,0xAF, \
+ 0xB0,0xB1,0xB2,0xB3,0xB4,0xB5,0xB6,0xB7,0xB8,0xB9,0xBA,0xBB,0xBC,0xBD,0xBE,0xBF, \
+ 0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF, \
+ 0xD0,0xD1,0xD2,0xD3,0xD4,0xD5,0xD6,0xD7,0xD8,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0xDF, \
+ 0xE0,0xE1,0xE2,0xE3,0xE4,0xE5,0xE6,0xE7,0xE8,0xE9,0xEA,0xEB,0xEC,0xED,0xEE,0xEF, \
+ 0xF0,0xF1,0xF2,0xF3,0xF4,0xF5,0xF6,0xF7,0xF8,0xF9,0xFA,0xFB,0xFC,0xFD,0xFE,0xFF}
+#define TBL_CT861 {0x80,0x9A,0x90,0x41,0x8E,0x41,0x8F,0x80,0x45,0x45,0x45,0x8B,0x8B,0x8D,0x8E,0x8F, \
+ 0x90,0x92,0x92,0x4F,0x99,0x8D,0x55,0x97,0x97,0x99,0x9A,0x9D,0x9C,0x9D,0x9E,0x9F, \
+ 0xA4,0xA5,0xA6,0xA7,0xA4,0xA5,0xA6,0xA7,0xA8,0xA9,0xAA,0xAB,0xAC,0xAD,0xAE,0xAF, \
+ 0xB0,0xB1,0xB2,0xB3,0xB4,0xB5,0xB6,0xB7,0xB8,0xB9,0xBA,0xBB,0xBC,0xBD,0xBE,0xBF, \
+ 0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF, \
+ 0xD0,0xD1,0xD2,0xD3,0xD4,0xD5,0xD6,0xD7,0xD8,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0xDF, \
+ 0xE0,0xE1,0xE2,0xE3,0xE4,0xE5,0xE6,0xE7,0xE8,0xE9,0xEA,0xEB,0xEC,0xED,0xEE,0xEF, \
+ 0xF0,0xF1,0xF2,0xF3,0xF4,0xF5,0xF6,0xF7,0xF8,0xF9,0xFA,0xFB,0xFC,0xFD,0xFE,0xFF}
+#define TBL_CT862 {0x80,0x81,0x82,0x83,0x84,0x85,0x86,0x87,0x88,0x89,0x8A,0x8B,0x8C,0x8D,0x8E,0x8F, \
+ 0x90,0x91,0x92,0x93,0x94,0x95,0x96,0x97,0x98,0x99,0x9A,0x9B,0x9C,0x9D,0x9E,0x9F, \
+ 0x41,0x49,0x4F,0x55,0xA5,0xA5,0xA6,0xA7,0xA8,0xA9,0xAA,0xAB,0xAC,0xAD,0xAE,0xAF, \
+ 0xB0,0xB1,0xB2,0xB3,0xB4,0xB5,0xB6,0xB7,0xB8,0xB9,0xBA,0xBB,0xBC,0xBD,0xBE,0xBF, \
+ 0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF, \
+ 0xD0,0xD1,0xD2,0xD3,0xD4,0xD5,0xD6,0xD7,0xD8,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0xDF, \
+ 0xE0,0xE1,0xE2,0xE3,0xE4,0xE5,0xE6,0xE7,0xE8,0xE9,0xEA,0xEB,0xEC,0xED,0xEE,0xEF, \
+ 0xF0,0xF1,0xF2,0xF3,0xF4,0xF5,0xF6,0xF7,0xF8,0xF9,0xFA,0xFB,0xFC,0xFD,0xFE,0xFF}
+#define TBL_CT863 {0x43,0x55,0x45,0x41,0x41,0x41,0x86,0x43,0x45,0x45,0x45,0x49,0x49,0x8D,0x41,0x8F, \
+ 0x45,0x45,0x45,0x4F,0x45,0x49,0x55,0x55,0x98,0x4F,0x55,0x9B,0x9C,0x55,0x55,0x9F, \
+ 0xA0,0xA1,0x4F,0x55,0xA4,0xA5,0xA6,0xA7,0x49,0xA9,0xAA,0xAB,0xAC,0xAD,0xAE,0xAF, \
+ 0xB0,0xB1,0xB2,0xB3,0xB4,0xB5,0xB6,0xB7,0xB8,0xB9,0xBA,0xBB,0xBC,0xBD,0xBE,0xBF, \
+ 0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF, \
+ 0xD0,0xD1,0xD2,0xD3,0xD4,0xD5,0xD6,0xD7,0xD8,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0xDF, \
+ 0xE0,0xE1,0xE2,0xE3,0xE4,0xE5,0xE6,0xE7,0xE8,0xE9,0xEA,0xEB,0xEC,0xED,0xEE,0xEF, \
+ 0xF0,0xF1,0xF2,0xF3,0xF4,0xF5,0xF6,0xF7,0xF8,0xF9,0xFA,0xFB,0xFC,0xFD,0xFE,0xFF}
+#define TBL_CT864 {0x80,0x9A,0x45,0x41,0x8E,0x41,0x8F,0x80,0x45,0x45,0x45,0x49,0x49,0x49,0x8E,0x8F, \
+ 0x90,0x92,0x92,0x4F,0x99,0x4F,0x55,0x55,0x59,0x99,0x9A,0x9B,0x9C,0x9D,0x9E,0x9F, \
+ 0x41,0x49,0x4F,0x55,0xA5,0xA5,0xA6,0xA7,0xA8,0xA9,0xAA,0xAB,0xAC,0xAD,0xAE,0xAF, \
+ 0xB0,0xB1,0xB2,0xB3,0xB4,0xB5,0xB6,0xB7,0xB8,0xB9,0xBA,0xBB,0xBC,0xBD,0xBE,0xBF, \
+ 0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF, \
+ 0xD0,0xD1,0xD2,0xD3,0xD4,0xD5,0xD6,0xD7,0xD8,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0xDF, \
+ 0xE0,0xE1,0xE2,0xE3,0xE4,0xE5,0xE6,0xE7,0xE8,0xE9,0xEA,0xEB,0xEC,0xED,0xEE,0xEF, \
+ 0xF0,0xF1,0xF2,0xF3,0xF4,0xF5,0xF6,0xF7,0xF8,0xF9,0xFA,0xFB,0xFC,0xFD,0xFE,0xFF}
+#define TBL_CT865 {0x80,0x9A,0x90,0x41,0x8E,0x41,0x8F,0x80,0x45,0x45,0x45,0x49,0x49,0x49,0x8E,0x8F, \
+ 0x90,0x92,0x92,0x4F,0x99,0x4F,0x55,0x55,0x59,0x99,0x9A,0x9B,0x9C,0x9D,0x9E,0x9F, \
+ 0x41,0x49,0x4F,0x55,0xA5,0xA5,0xA6,0xA7,0xA8,0xA9,0xAA,0xAB,0xAC,0xAD,0xAE,0xAF, \
+ 0xB0,0xB1,0xB2,0xB3,0xB4,0xB5,0xB6,0xB7,0xB8,0xB9,0xBA,0xBB,0xBC,0xBD,0xBE,0xBF, \
+ 0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF, \
+ 0xD0,0xD1,0xD2,0xD3,0xD4,0xD5,0xD6,0xD7,0xD8,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0xDF, \
+ 0xE0,0xE1,0xE2,0xE3,0xE4,0xE5,0xE6,0xE7,0xE8,0xE9,0xEA,0xEB,0xEC,0xED,0xEE,0xEF, \
+ 0xF0,0xF1,0xF2,0xF3,0xF4,0xF5,0xF6,0xF7,0xF8,0xF9,0xFA,0xFB,0xFC,0xFD,0xFE,0xFF}
+#define TBL_CT866 {0x80,0x81,0x82,0x83,0x84,0x85,0x86,0x87,0x88,0x89,0x8A,0x8B,0x8C,0x8D,0x8E,0x8F, \
+ 0x90,0x91,0x92,0x93,0x94,0x95,0x96,0x97,0x98,0x99,0x9A,0x9B,0x9C,0x9D,0x9E,0x9F, \
+ 0x80,0x81,0x82,0x83,0x84,0x85,0x86,0x87,0x88,0x89,0x8A,0x8B,0x8C,0x8D,0x8E,0x8F, \
+ 0xB0,0xB1,0xB2,0xB3,0xB4,0xB5,0xB6,0xB7,0xB8,0xB9,0xBA,0xBB,0xBC,0xBD,0xBE,0xBF, \
+ 0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF, \
+ 0xD0,0xD1,0xD2,0xD3,0xD4,0xD5,0xD6,0xD7,0xD8,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0xDF, \
+ 0x90,0x91,0x92,0x93,0x94,0x95,0x96,0x97,0x98,0x99,0x9A,0x9B,0x9C,0x9D,0x9E,0x9F, \
+ 0xF0,0xF0,0xF2,0xF2,0xF4,0xF4,0xF6,0xF6,0xF8,0xF9,0xFA,0xFB,0xFC,0xFD,0xFE,0xFF}
+#define TBL_CT869 {0x80,0x81,0x82,0x83,0x84,0x85,0x86,0x87,0x88,0x89,0x8A,0x8B,0x8C,0x8D,0x8E,0x8F, \
+ 0x90,0x91,0x92,0x93,0x94,0x95,0x96,0x97,0x98,0x99,0x9A,0x86,0x9C,0x8D,0x8F,0x90, \
+ 0x91,0x90,0x92,0x95,0xA4,0xA5,0xA6,0xA7,0xA8,0xA9,0xAA,0xAB,0xAC,0xAD,0xAE,0xAF, \
+ 0xB0,0xB1,0xB2,0xB3,0xB4,0xB5,0xB6,0xB7,0xB8,0xB9,0xBA,0xBB,0xBC,0xBD,0xBE,0xBF, \
+ 0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF, \
+ 0xD0,0xD1,0xD2,0xD3,0xD4,0xD5,0xA4,0xA5,0xA6,0xD9,0xDA,0xDB,0xDC,0xA7,0xA8,0xDF, \
+ 0xA9,0xAA,0xAC,0xAD,0xB5,0xB6,0xB7,0xB8,0xBD,0xBE,0xC6,0xC7,0xCF,0xCF,0xD0,0xEF, \
+ 0xF0,0xF1,0xD1,0xD2,0xD3,0xF5,0xD4,0xF7,0xF8,0xF9,0xD5,0x96,0x95,0x98,0xFE,0xFF}
+
+
+/* DBCS code range |----- 1st byte -----| |----------- 2nd byte -----------| */
+#define TBL_DC932 {0x81, 0x9F, 0xE0, 0xFC, 0x40, 0x7E, 0x80, 0xFC, 0x00, 0x00}
+#define TBL_DC936 {0x81, 0xFE, 0x00, 0x00, 0x40, 0x7E, 0x80, 0xFE, 0x00, 0x00}
+#define TBL_DC949 {0x81, 0xFE, 0x00, 0x00, 0x41, 0x5A, 0x61, 0x7A, 0x81, 0xFE}
+#define TBL_DC950 {0x81, 0xFE, 0x00, 0x00, 0x40, 0x7E, 0xA1, 0xFE, 0x00, 0x00}
+
+
+/* Macros for table definitions */
+#define MERGE_2STR(a, b) a ## b
+#define MKCVTBL(hd, cp) MERGE_2STR(hd, cp)
+
+
+
+
+/*--------------------------------------------------------------------------
+
+ Module Private Work Area
+
+---------------------------------------------------------------------------*/
+/* Remark: Variables defined here without initial value shall be guaranteed
+/ zero/null at start-up. If not, the linker option or start-up routine is
+/ not compliance with C standard. */
+
+/*--------------------------------*/
+/* File/Volume controls */
+/*--------------------------------*/
+
+#if FF_VOLUMES < 1 || FF_VOLUMES > 10
+#error Wrong FF_VOLUMES setting
+#endif
+static FATFS* FatFs[FF_VOLUMES]; /* Pointer to the filesystem objects (logical drives) */
+static WORD Fsid; /* Filesystem mount ID */
+
+#if FF_FS_RPATH != 0
+static BYTE CurrVol; /* Current drive */
+#endif
+
+#if FF_FS_LOCK != 0
+static FILESEM Files[FF_FS_LOCK]; /* Open object lock semaphores */
+#endif
+
+#if FF_STR_VOLUME_ID
+#ifdef FF_VOLUME_STRS
+static const char* const VolumeStr[FF_VOLUMES] = {FF_VOLUME_STRS}; /* Pre-defined volume ID */
+#endif
+#endif
+
+
+/*--------------------------------*/
+/* LFN/Directory working buffer */
+/*--------------------------------*/
+
+#if FF_USE_LFN == 0 /* Non-LFN configuration */
+#if FF_FS_EXFAT
+#error LFN must be enabled when enable exFAT
+#endif
+#define DEF_NAMBUF
+#define INIT_NAMBUF(fs)
+#define FREE_NAMBUF()
+#define LEAVE_MKFS(res) return res
+
+#else /* LFN configurations */
+#if FF_MAX_LFN < 12 || FF_MAX_LFN > 255
+#error Wrong setting of FF_MAX_LFN
+#endif
+#if FF_LFN_BUF < FF_SFN_BUF || FF_SFN_BUF < 12
+#error Wrong setting of FF_LFN_BUF or FF_SFN_BUF
+#endif
+#if FF_LFN_UNICODE < 0 || FF_LFN_UNICODE > 3
+#error Wrong setting of FF_LFN_UNICODE
+#endif
+static const BYTE LfnOfs[] = {1,3,5,7,9,14,16,18,20,22,24,28,30}; /* FAT: Offset of LFN characters in the directory entry */
+#define MAXDIRB(nc) ((nc + 44U) / 15 * SZDIRE) /* exFAT: Size of directory entry block scratchpad buffer needed for the name length */
+
+#if FF_USE_LFN == 1 /* LFN enabled with static working buffer */
+#if FF_FS_EXFAT
+static BYTE DirBuf[MAXDIRB(FF_MAX_LFN)]; /* Directory entry block scratchpad buffer */
+#endif
+static WCHAR LfnBuf[FF_MAX_LFN + 1]; /* LFN working buffer */
+#define DEF_NAMBUF
+#define INIT_NAMBUF(fs)
+#define FREE_NAMBUF()
+#define LEAVE_MKFS(res) return res
+
+#elif FF_USE_LFN == 2 /* LFN enabled with dynamic working buffer on the stack */
+#if FF_FS_EXFAT
+#define DEF_NAMBUF WCHAR lbuf[FF_MAX_LFN+1]; BYTE dbuf[MAXDIRB(FF_MAX_LFN)]; /* LFN working buffer and directory entry block scratchpad buffer */
+#define INIT_NAMBUF(fs) { (fs)->lfnbuf = lbuf; (fs)->dirbuf = dbuf; }
+#define FREE_NAMBUF()
+#else
+#define DEF_NAMBUF WCHAR lbuf[FF_MAX_LFN+1]; /* LFN working buffer */
+#define INIT_NAMBUF(fs) { (fs)->lfnbuf = lbuf; }
+#define FREE_NAMBUF()
+#endif
+#define LEAVE_MKFS(res) return res
+
+#elif FF_USE_LFN == 3 /* LFN enabled with dynamic working buffer on the heap */
+#if FF_FS_EXFAT
+#define DEF_NAMBUF WCHAR *lfn; /* Pointer to LFN working buffer and directory entry block scratchpad buffer */
+#define INIT_NAMBUF(fs) { lfn = ff_memalloc((FF_MAX_LFN+1)*2 + MAXDIRB(FF_MAX_LFN)); if (!lfn) LEAVE_FF(fs, FR_NOT_ENOUGH_CORE); (fs)->lfnbuf = lfn; (fs)->dirbuf = (BYTE*)(lfn+FF_MAX_LFN+1); }
+#define FREE_NAMBUF() ff_memfree(lfn)
+#else
+#define DEF_NAMBUF WCHAR *lfn; /* Pointer to LFN working buffer */
+#define INIT_NAMBUF(fs) { lfn = ff_memalloc((FF_MAX_LFN+1)*2); if (!lfn) LEAVE_FF(fs, FR_NOT_ENOUGH_CORE); (fs)->lfnbuf = lfn; }
+#define FREE_NAMBUF() ff_memfree(lfn)
+#endif
+#define LEAVE_MKFS(res) { if (!work) ff_memfree(buf); return res; }
+#define MAX_MALLOC 0x8000 /* Must be >=FF_MAX_SS */
+
+#else
+#error Wrong setting of FF_USE_LFN
+
+#endif /* FF_USE_LFN == 1 */
+#endif /* FF_USE_LFN == 0 */
+
+
+
+/*--------------------------------*/
+/* Code conversion tables */
+/*--------------------------------*/
+
+#if FF_CODE_PAGE == 0 /* Run-time code page configuration */
+#define CODEPAGE CodePage
+static WORD CodePage; /* Current code page */
+static const BYTE *ExCvt, *DbcTbl; /* Pointer to current SBCS up-case table and DBCS code range table below */
+static const BYTE Ct437[] = TBL_CT437;
+static const BYTE Ct720[] = TBL_CT720;
+static const BYTE Ct737[] = TBL_CT737;
+static const BYTE Ct771[] = TBL_CT771;
+static const BYTE Ct775[] = TBL_CT775;
+static const BYTE Ct850[] = TBL_CT850;
+static const BYTE Ct852[] = TBL_CT852;
+static const BYTE Ct855[] = TBL_CT855;
+static const BYTE Ct857[] = TBL_CT857;
+static const BYTE Ct860[] = TBL_CT860;
+static const BYTE Ct861[] = TBL_CT861;
+static const BYTE Ct862[] = TBL_CT862;
+static const BYTE Ct863[] = TBL_CT863;
+static const BYTE Ct864[] = TBL_CT864;
+static const BYTE Ct865[] = TBL_CT865;
+static const BYTE Ct866[] = TBL_CT866;
+static const BYTE Ct869[] = TBL_CT869;
+static const BYTE Dc932[] = TBL_DC932;
+static const BYTE Dc936[] = TBL_DC936;
+static const BYTE Dc949[] = TBL_DC949;
+static const BYTE Dc950[] = TBL_DC950;
+
+#elif FF_CODE_PAGE < 900 /* Static code page configuration (SBCS) */
+#define CODEPAGE FF_CODE_PAGE
+static const BYTE ExCvt[] = MKCVTBL(TBL_CT, FF_CODE_PAGE);
+
+#else /* Static code page configuration (DBCS) */
+#define CODEPAGE FF_CODE_PAGE
+static const BYTE DbcTbl[] = MKCVTBL(TBL_DC, FF_CODE_PAGE);
+
+#endif
+
+
+
+
+/*--------------------------------------------------------------------------
+
+ Module Private Functions
+
+---------------------------------------------------------------------------*/
+
+
+/*-----------------------------------------------------------------------*/
+/* Load/Store multi-byte word in the FAT structure */
+/*-----------------------------------------------------------------------*/
+
+static WORD ld_word (const BYTE* ptr) /* Load a 2-byte little-endian word */
+{
+ WORD rv;
+
+ rv = ptr[1];
+ rv = rv << 8 | ptr[0];
+ return rv;
+}
+
+static DWORD ld_dword (const BYTE* ptr) /* Load a 4-byte little-endian word */
+{
+ DWORD rv;
+
+ rv = ptr[3];
+ rv = rv << 8 | ptr[2];
+ rv = rv << 8 | ptr[1];
+ rv = rv << 8 | ptr[0];
+ return rv;
+}
+
+#if FF_FS_EXFAT
+static QWORD ld_qword (const BYTE* ptr) /* Load an 8-byte little-endian word */
+{
+ QWORD rv;
+
+ rv = ptr[7];
+ rv = rv << 8 | ptr[6];
+ rv = rv << 8 | ptr[5];
+ rv = rv << 8 | ptr[4];
+ rv = rv << 8 | ptr[3];
+ rv = rv << 8 | ptr[2];
+ rv = rv << 8 | ptr[1];
+ rv = rv << 8 | ptr[0];
+ return rv;
+}
+#endif
+
+#if !FF_FS_READONLY
+static void st_word (BYTE* ptr, WORD val) /* Store a 2-byte word in little-endian */
+{
+ *ptr++ = (BYTE)val; val >>= 8;
+ *ptr++ = (BYTE)val;
+}
+
+static void st_dword (BYTE* ptr, DWORD val) /* Store a 4-byte word in little-endian */
+{
+ *ptr++ = (BYTE)val; val >>= 8;
+ *ptr++ = (BYTE)val; val >>= 8;
+ *ptr++ = (BYTE)val; val >>= 8;
+ *ptr++ = (BYTE)val;
+}
+
+#if FF_FS_EXFAT
+static void st_qword (BYTE* ptr, QWORD val) /* Store an 8-byte word in little-endian */
+{
+ *ptr++ = (BYTE)val; val >>= 8;
+ *ptr++ = (BYTE)val; val >>= 8;
+ *ptr++ = (BYTE)val; val >>= 8;
+ *ptr++ = (BYTE)val; val >>= 8;
+ *ptr++ = (BYTE)val; val >>= 8;
+ *ptr++ = (BYTE)val; val >>= 8;
+ *ptr++ = (BYTE)val; val >>= 8;
+ *ptr++ = (BYTE)val;
+}
+#endif
+#endif /* !FF_FS_READONLY */
+
+
+
+/*-----------------------------------------------------------------------*/
+/* String functions */
+/*-----------------------------------------------------------------------*/
+
+/* Copy memory to memory */
+static void mem_cpy (void* dst, const void* src, UINT cnt)
+{
+ BYTE *d = (BYTE*)dst;
+ const BYTE *s = (const BYTE*)src;
+
+#if FF_WORD_ACCESS == 1
+ while (cnt >= sizeof (int)) {
+ *(int*)d = *(int*)s;
+ d += sizeof (int); s += sizeof (int);
+ cnt -= sizeof (int);
+ }
+#endif
+ if (cnt != 0) {
+ do {
+ *d++ = *s++;
+ } while (--cnt);
+ }
+}
+
+
+/* Fill memory block */
+static void mem_set (void* dst, int val, UINT cnt)
+{
+ BYTE *d = (BYTE*)dst;
+
+ do {
+ *d++ = (BYTE)val;
+ } while (--cnt);
+}
+
+
+/* Compare memory block */
+static int mem_cmp (const void* dst, const void* src, UINT cnt) /* ZR:same, NZ:different */
+{
+ const BYTE *d = (const BYTE *)dst, *s = (const BYTE *)src;
+ int r = 0;
+
+ do {
+ r = *d++ - *s++;
+ } while (--cnt && r == 0);
+
+ return r;
+}
+
+
+/* Check if chr is contained in the string */
+static int chk_chr (const char* str, int chr) /* NZ:contained, ZR:not contained */
+{
+ while (*str && *str != chr) str++;
+ return *str;
+}
+
+
+/* Test if the character is DBC 1st byte */
+static int dbc_1st (BYTE c)
+{
+#if FF_CODE_PAGE == 0 /* Variable code page */
+ if (DbcTbl && c >= DbcTbl[0]) {
+ if (c <= DbcTbl[1]) return 1; /* 1st byte range 1 */
+ if (c >= DbcTbl[2] && c <= DbcTbl[3]) return 1; /* 1st byte range 2 */
+ }
+#elif FF_CODE_PAGE >= 900 /* DBCS fixed code page */
+ if (c >= DbcTbl[0]) {
+ if (c <= DbcTbl[1]) return 1;
+ if (c >= DbcTbl[2] && c <= DbcTbl[3]) return 1;
+ }
+#else /* SBCS fixed code page */
+ if (c != 0) return 0; /* Always false */
+#endif
+ return 0;
+}
+
+
+/* Test if the character is DBC 2nd byte */
+static int dbc_2nd (BYTE c)
+{
+#if FF_CODE_PAGE == 0 /* Variable code page */
+ if (DbcTbl && c >= DbcTbl[4]) {
+ if (c <= DbcTbl[5]) return 1; /* 2nd byte range 1 */
+ if (c >= DbcTbl[6] && c <= DbcTbl[7]) return 1; /* 2nd byte range 2 */
+ if (c >= DbcTbl[8] && c <= DbcTbl[9]) return 1; /* 2nd byte range 3 */
+ }
+#elif FF_CODE_PAGE >= 900 /* DBCS fixed code page */
+ if (c >= DbcTbl[4]) {
+ if (c <= DbcTbl[5]) return 1;
+ if (c >= DbcTbl[6] && c <= DbcTbl[7]) return 1;
+ if (c >= DbcTbl[8] && c <= DbcTbl[9]) return 1;
+ }
+#else /* SBCS fixed code page */
+ if (c != 0) return 0; /* Always false */
+#endif
+ return 0;
+}
+
+
+#if FF_USE_LFN
+
+/* Get a character from TCHAR string in defined API encodeing */
+static DWORD tchar2uni ( /* Returns character in UTF-16 encoding (>=0x10000 on double encoding unit, 0xFFFFFFFF on decode error) */
+ const TCHAR** str /* Pointer to pointer to TCHAR string in configured encoding */
+)
+{
+ DWORD uc;
+ const TCHAR *p = *str;
+
+#if FF_LFN_UNICODE == 1 /* UTF-16 input */
+ WCHAR wc;
+
+ uc = *p++; /* Get a unit */
+ if (IsSurrogate(uc)) { /* Surrogate? */
+ wc = *p++; /* Get low surrogate */
+ if (!IsSurrogateH(uc) || !IsSurrogateL(wc)) return 0xFFFFFFFF; /* Wrong surrogate? */
+ uc = uc << 16 | wc;
+ }
+
+#elif FF_LFN_UNICODE == 2 /* UTF-8 input */
+ BYTE b;
+ int nf;
+
+ uc = (BYTE)*p++; /* Get a unit */
+ if (uc & 0x80) { /* Multiple byte code? */
+ if ((uc & 0xE0) == 0xC0) { /* 2-byte sequence? */
+ uc &= 0x1F; nf = 1;
+ } else {
+ if ((uc & 0xF0) == 0xE0) { /* 3-byte sequence? */
+ uc &= 0x0F; nf = 2;
+ } else {
+ if ((uc & 0xF8) == 0xF0) { /* 4-byte sequence? */
+ uc &= 0x07; nf = 3;
+ } else { /* Wrong sequence */
+ return 0xFFFFFFFF;
+ }
+ }
+ }
+ do { /* Get trailing bytes */
+ b = (BYTE)*p++;
+ if ((b & 0xC0) != 0x80) return 0xFFFFFFFF; /* Wrong sequence? */
+ uc = uc << 6 | (b & 0x3F);
+ } while (--nf != 0);
+ if (uc < 0x80 || IsSurrogate(uc) || uc >= 0x110000) return 0xFFFFFFFF; /* Wrong code? */
+ if (uc >= 0x010000) uc = 0xD800DC00 | ((uc - 0x10000) << 6 & 0x3FF0000) | (uc & 0x3FF); /* Make a surrogate pair if needed */
+ }
+
+#elif FF_LFN_UNICODE == 3 /* UTF-32 input */
+ uc = (TCHAR)*p++; /* Get a unit */
+ if (uc >= 0x110000) return 0xFFFFFFFF; /* Wrong code? */
+ if (uc >= 0x010000) uc = 0xD800DC00 | ((uc - 0x10000) << 6 & 0x3FF0000) | (uc & 0x3FF); /* Make a surrogate pair if needed */
+
+#else /* ANSI/OEM input */
+ BYTE b;
+ WCHAR wc;
+
+ wc = (BYTE)*p++; /* Get a byte */
+ if (dbc_1st((BYTE)wc)) { /* Is it a DBC 1st byte? */
+ b = (BYTE)*p++; /* Get 2nd byte */
+ if (!dbc_2nd(b)) return 0xFFFFFFFF; /* Invalid code? */
+ wc = (wc << 8) + b; /* Make a DBC */
+ }
+ if (wc != 0) {
+ wc = ff_oem2uni(wc, CODEPAGE); /* ANSI/OEM ==> Unicode */
+ if (wc == 0) return 0xFFFFFFFF; /* Invalid code? */
+ }
+ uc = wc;
+
+#endif
+ *str = p; /* Next read pointer */
+ return uc;
+}
+
+
+/* Output a TCHAR string in defined API encoding */
+static BYTE put_utf ( /* Returns number of encoding units written (0:buffer overflow or wrong encoding) */
+ DWORD chr, /* UTF-16 encoded character (Double encoding unit char if >=0x10000) */
+ TCHAR* buf, /* Output buffer */
+ UINT szb /* Size of the buffer */
+)
+{
+#if FF_LFN_UNICODE == 1 /* UTF-16 output */
+ WCHAR hs, wc;
+
+ hs = (WCHAR)(chr >> 16);
+ wc = (WCHAR)chr;
+ if (hs == 0) { /* Single encoding unit? */
+ if (szb < 1 || IsSurrogate(wc)) return 0; /* Buffer overflow or wrong code? */
+ *buf = wc;
+ return 1;
+ }
+ if (szb < 2 || !IsSurrogateH(hs) || !IsSurrogateL(wc)) return 0; /* Buffer overflow or wrong surrogate? */
+ *buf++ = hs;
+ *buf++ = wc;
+ return 2;
+
+#elif FF_LFN_UNICODE == 2 /* UTF-8 output */
+ DWORD hc;
+
+ if (chr < 0x80) { /* Single byte code? */
+ if (szb < 1) return 0; /* Buffer overflow? */
+ *buf = (TCHAR)chr;
+ return 1;
+ }
+ if (chr < 0x800) { /* 2-byte sequence? */
+ if (szb < 2) return 0; /* Buffer overflow? */
+ *buf++ = (TCHAR)(0xC0 | (chr >> 6 & 0x1F));
+ *buf++ = (TCHAR)(0x80 | (chr >> 0 & 0x3F));
+ return 2;
+ }
+ if (chr < 0x10000) { /* 3-byte sequence? */
+ if (szb < 3 || IsSurrogate(chr)) return 0; /* Buffer overflow or wrong code? */
+ *buf++ = (TCHAR)(0xE0 | (chr >> 12 & 0x0F));
+ *buf++ = (TCHAR)(0x80 | (chr >> 6 & 0x3F));
+ *buf++ = (TCHAR)(0x80 | (chr >> 0 & 0x3F));
+ return 3;
+ }
+ /* 4-byte sequence */
+ if (szb < 4) return 0; /* Buffer overflow? */
+ hc = ((chr & 0xFFFF0000) - 0xD8000000) >> 6; /* Get high 10 bits */
+ chr = (chr & 0xFFFF) - 0xDC00; /* Get low 10 bits */
+ if (hc >= 0x100000 || chr >= 0x400) return 0; /* Wrong surrogate? */
+ chr = (hc | chr) + 0x10000;
+ *buf++ = (TCHAR)(0xF0 | (chr >> 18 & 0x07));
+ *buf++ = (TCHAR)(0x80 | (chr >> 12 & 0x3F));
+ *buf++ = (TCHAR)(0x80 | (chr >> 6 & 0x3F));
+ *buf++ = (TCHAR)(0x80 | (chr >> 0 & 0x3F));
+ return 4;
+
+#elif FF_LFN_UNICODE == 3 /* UTF-32 output */
+ DWORD hc;
+
+ if (szb < 1) return 0; /* Buffer overflow? */
+ if (chr >= 0x10000) { /* Out of BMP? */
+ hc = ((chr & 0xFFFF0000) - 0xD8000000) >> 6; /* Get high 10 bits */
+ chr = (chr & 0xFFFF) - 0xDC00; /* Get low 10 bits */
+ if (hc >= 0x100000 || chr >= 0x400) return 0; /* Wrong surrogate? */
+ chr = (hc | chr) + 0x10000;
+ }
+ *buf++ = (TCHAR)chr;
+ return 1;
+
+#else /* ANSI/OEM output */
+ WCHAR wc;
+
+ wc = ff_uni2oem(chr, CODEPAGE);
+ if (wc >= 0x100) { /* Is this a DBC? */
+ if (szb < 2) return 0;
+ *buf++ = (char)(wc >> 8); /* Store DBC 1st byte */
+ *buf++ = (TCHAR)wc; /* Store DBC 2nd byte */
+ return 2;
+ }
+ if (wc == 0 || szb < 1) return 0; /* Invalid char or buffer overflow? */
+ *buf++ = (TCHAR)wc; /* Store the character */
+ return 1;
+#endif
+}
+#endif /* FF_USE_LFN */
+
+
+#if FF_FS_REENTRANT
+/*-----------------------------------------------------------------------*/
+/* Request/Release grant to access the volume */
+/*-----------------------------------------------------------------------*/
+static int lock_fs ( /* 1:Ok, 0:timeout */
+ FATFS* fs /* Filesystem object */
+)
+{
+ return ff_req_grant(fs->sobj);
+}
+
+
+static void unlock_fs (
+ FATFS* fs, /* Filesystem object */
+ FRESULT res /* Result code to be returned */
+)
+{
+ if (fs && res != FR_NOT_ENABLED && res != FR_INVALID_DRIVE && res != FR_TIMEOUT) {
+ ff_rel_grant(fs->sobj);
+ }
+}
+
+#endif
+
+
+
+#if FF_FS_LOCK != 0
+/*-----------------------------------------------------------------------*/
+/* File lock control functions */
+/*-----------------------------------------------------------------------*/
+
+static FRESULT chk_lock ( /* Check if the file can be accessed */
+ DIR* dp, /* Directory object pointing the file to be checked */
+ int acc /* Desired access type (0:Read mode open, 1:Write mode open, 2:Delete or rename) */
+)
+{
+ UINT i, be;
+
+ /* Search open object table for the object */
+ be = 0;
+ for (i = 0; i < FF_FS_LOCK; i++) {
+ if (Files[i].fs) { /* Existing entry */
+ if (Files[i].fs == dp->obj.fs && /* Check if the object matches with an open object */
+ Files[i].clu == dp->obj.sclust &&
+ Files[i].ofs == dp->dptr) break;
+ } else { /* Blank entry */
+ be = 1;
+ }
+ }
+ if (i == FF_FS_LOCK) { /* The object has not been opened */
+ return (!be && acc != 2) ? FR_TOO_MANY_OPEN_FILES : FR_OK; /* Is there a blank entry for new object? */
+ }
+
+ /* The object was opened. Reject any open against writing file and all write mode open */
+ return (acc != 0 || Files[i].ctr == 0x100) ? FR_LOCKED : FR_OK;
+}
+
+
+static int enq_lock (void) /* Check if an entry is available for a new object */
+{
+ UINT i;
+
+ for (i = 0; i < FF_FS_LOCK && Files[i].fs; i++) ;
+ return (i == FF_FS_LOCK) ? 0 : 1;
+}
+
+
+static UINT inc_lock ( /* Increment object open counter and returns its index (0:Internal error) */
+ DIR* dp, /* Directory object pointing the file to register or increment */
+ int acc /* Desired access (0:Read, 1:Write, 2:Delete/Rename) */
+)
+{
+ UINT i;
+
+
+ for (i = 0; i < FF_FS_LOCK; i++) { /* Find the object */
+ if (Files[i].fs == dp->obj.fs &&
+ Files[i].clu == dp->obj.sclust &&
+ Files[i].ofs == dp->dptr) break;
+ }
+
+ if (i == FF_FS_LOCK) { /* Not opened. Register it as new. */
+ for (i = 0; i < FF_FS_LOCK && Files[i].fs; i++) ;
+ if (i == FF_FS_LOCK) return 0; /* No free entry to register (int err) */
+ Files[i].fs = dp->obj.fs;
+ Files[i].clu = dp->obj.sclust;
+ Files[i].ofs = dp->dptr;
+ Files[i].ctr = 0;
+ }
+
+ if (acc >= 1 && Files[i].ctr) return 0; /* Access violation (int err) */
+
+ Files[i].ctr = acc ? 0x100 : Files[i].ctr + 1; /* Set semaphore value */
+
+ return i + 1; /* Index number origin from 1 */
+}
+
+
+static FRESULT dec_lock ( /* Decrement object open counter */
+ UINT i /* Semaphore index (1..) */
+)
+{
+ WORD n;
+ FRESULT res = FR_DISK_ERR;
+
+
+ if (--i < FF_FS_LOCK) { /* Index number origin from 0 */
+ n = Files[i].ctr;
+ if (n == 0x100) n = 0; /* If write mode open, delete the entry */
+ if (n > 0) n--; /* Decrement read mode open count */
+ Files[i].ctr = n;
+ if (n == 0) Files[i].fs = 0; /* Delete the entry if open count gets zero */
+ res = FR_OK;
+ } else {
+ res = FR_INT_ERR; /* Invalid index number */
+ }
+ return res;
+}
+
+
+static void clear_lock ( /* Clear lock entries of the volume */
+ FATFS *fs
+)
+{
+ UINT i;
+
+ for (i = 0; i < FF_FS_LOCK; i++) {
+ if (Files[i].fs == fs) Files[i].fs = 0;
+ }
+}
+
+#endif /* FF_FS_LOCK != 0 */
+
+
+
+/*-----------------------------------------------------------------------*/
+/* Move/Flush disk access window in the filesystem object */
+/*-----------------------------------------------------------------------*/
+#if !FF_FS_READONLY
+static FRESULT sync_window ( /* Returns FR_OK or FR_DISK_ERR */
+ FATFS* fs /* Filesystem object */
+)
+{
+ FRESULT res = FR_DISK_ERR;
+
+ if (fs->wflag) { /* Is the disk access window dirty */
+ if (disk_write(fs->pdrv, fs->win, fs->winsect, 1) == RES_OK) { /* Write back the window */
+ fs->wflag = 0; /* Clear window dirty flag */
+ if (fs->winsect - fs->fatbase < fs->fsize) { /* Is it in the 1st FAT? */
+ if (fs->n_fats == 2) disk_write(fs->pdrv, fs->win, fs->winsect + fs->fsize, 1); /* Reflect it to 2nd FAT if needed */
+ }
+ res = FR_OK;
+ }
+ } else {
+ res = FR_OK;
+ }
+
+ return res;
+}
+#endif
+
+
+static FRESULT move_window ( /* Returns FR_OK or FR_DISK_ERR */
+ FATFS* fs, /* Filesystem object */
+ DWORD sector /* Sector number to make appearance in the fs->win[] */
+)
+{
+ FRESULT res = FR_DISK_ERR;
+
+ if (sector != fs->winsect) { /* Window offset changed? */
+#if !FF_FS_READONLY
+ res = sync_window(fs); /* Write-back changes */
+ if (res == FR_OK) { /* Fill sector window with new data */
+#endif
+ if (disk_read(fs->pdrv, fs->win, sector, 1) != RES_OK) {
+ sector = 0xFFFFFFFF; /* Invalidate window if read data is not valid */
+ res = FR_DISK_ERR;
+ } else {
+ res = FR_OK;
+ }
+ fs->winsect = sector;
+#if !FF_FS_READONLY
+ }
+#endif
+ } else {
+ res = FR_OK;
+ }
+ return res;
+}
+
+
+
+
+#if !FF_FS_READONLY
+/*-----------------------------------------------------------------------*/
+/* Synchronize filesystem and data on the storage */
+/*-----------------------------------------------------------------------*/
+
+static FRESULT sync_fs ( /* Returns FR_OK or FR_DISK_ERR */
+ FATFS* fs /* Filesystem object */
+)
+{
+ FRESULT res = FR_DISK_ERR;
+
+
+ res = sync_window(fs);
+ if (res == FR_OK) {
+ if (fs->fs_type == FS_FAT32 && fs->fsi_flag == 1) { /* FAT32: Update FSInfo sector if needed */
+ /* Create FSInfo structure */
+ mem_set(fs->win, 0, SS(fs));
+ st_word(fs->win + BS_55AA, 0xAA55);
+ st_dword(fs->win + FSI_LeadSig, 0x41615252);
+ st_dword(fs->win + FSI_StrucSig, 0x61417272);
+ st_dword(fs->win + FSI_Free_Count, fs->free_clst);
+ st_dword(fs->win + FSI_Nxt_Free, fs->last_clst);
+ /* Write it into the FSInfo sector */
+ fs->winsect = fs->volbase + 1;
+ disk_write(fs->pdrv, fs->win, fs->winsect, 1);
+ fs->fsi_flag = 0;
+ }
+ /* Make sure that no pending write process in the lower layer */
+ if (disk_ioctl(fs->pdrv, CTRL_SYNC, 0) != RES_OK) res = FR_DISK_ERR;
+ }
+
+ return res;
+}
+
+#endif
+
+
+
+/*-----------------------------------------------------------------------*/
+/* Get physical sector number from cluster number */
+/*-----------------------------------------------------------------------*/
+
+static DWORD clst2sect ( /* !=0:Sector number, 0:Failed (invalid cluster#) */
+ FATFS* fs, /* Filesystem object */
+ DWORD clst /* Cluster# to be converted */
+)
+{
+ clst -= 2; /* Cluster number is origin from 2 */
+ if (clst >= fs->n_fatent - 2) return 0; /* Is it invalid cluster number? */
+ return fs->database + fs->csize * clst; /* Start sector number of the cluster */
+}
+
+
+
+
+/*-----------------------------------------------------------------------*/
+/* FAT access - Read value of a FAT entry */
+/*-----------------------------------------------------------------------*/
+
+static DWORD get_fat ( /* 0xFFFFFFFF:Disk error, 1:Internal error, 2..0x7FFFFFFF:Cluster status */
+ FFOBJID* obj, /* Corresponding object */
+ DWORD clst /* Cluster number to get the value */
+)
+{
+ UINT wc, bc;
+ DWORD val;
+ FATFS *fs = obj->fs;
+
+
+ if (clst < 2 || clst >= fs->n_fatent) { /* Check if in valid range */
+ val = 1; /* Internal error */
+
+ } else {
+ val = 0xFFFFFFFF; /* Default value falls on disk error */
+
+ switch (fs->fs_type) {
+ case FS_FAT12 :
+ bc = (UINT)clst; bc += bc / 2;
+ if (move_window(fs, fs->fatbase + (bc / SS(fs))) != FR_OK) break;
+ wc = fs->win[bc++ % SS(fs)]; /* Get 1st byte of the entry */
+ if (move_window(fs, fs->fatbase + (bc / SS(fs))) != FR_OK) break;
+ wc |= fs->win[bc % SS(fs)] << 8; /* Merge 2nd byte of the entry */
+ val = (clst & 1) ? (wc >> 4) : (wc & 0xFFF); /* Adjust bit position */
+ break;
+
+ case FS_FAT16 :
+ if (move_window(fs, fs->fatbase + (clst / (SS(fs) / 2))) != FR_OK) break;
+ val = ld_word(fs->win + clst * 2 % SS(fs)); /* Simple WORD array */
+ break;
+
+ case FS_FAT32 :
+ if (move_window(fs, fs->fatbase + (clst / (SS(fs) / 4))) != FR_OK) break;
+ val = ld_dword(fs->win + clst * 4 % SS(fs)) & 0x0FFFFFFF; /* Simple DWORD array but mask out upper 4 bits */
+ break;
+#if FF_FS_EXFAT
+ case FS_EXFAT :
+ if ((obj->objsize != 0 && obj->sclust != 0) || obj->stat == 0) { /* Object except root dir must have valid data length */
+ DWORD cofs = clst - obj->sclust; /* Offset from start cluster */
+ DWORD clen = (DWORD)((obj->objsize - 1) / SS(fs)) / fs->csize; /* Number of clusters - 1 */
+
+ if (obj->stat == 2 && cofs <= clen) { /* Is it a contiguous chain? */
+ val = (cofs == clen) ? 0x7FFFFFFF : clst + 1; /* No data on the FAT, generate the value */
+ break;
+ }
+ if (obj->stat == 3 && cofs < obj->n_cont) { /* Is it in the 1st fragment? */
+ val = clst + 1; /* Generate the value */
+ break;
+ }
+ if (obj->stat != 2) { /* Get value from FAT if FAT chain is valid */
+ if (obj->n_frag != 0) { /* Is it on the growing edge? */
+ val = 0x7FFFFFFF; /* Generate EOC */
+ } else {
+ if (move_window(fs, fs->fatbase + (clst / (SS(fs) / 4))) != FR_OK) break;
+ val = ld_dword(fs->win + clst * 4 % SS(fs)) & 0x7FFFFFFF;
+ }
+ break;
+ }
+ }
+ val = 1; /* Internal error */
+ break;
+#endif
+ default:
+ val = 1; /* Internal error */
+ }
+ }
+
+ return val;
+}
+
+
+
+
+#if !FF_FS_READONLY
+/*-----------------------------------------------------------------------*/
+/* FAT access - Change value of a FAT entry */
+/*-----------------------------------------------------------------------*/
+
+static FRESULT put_fat ( /* FR_OK(0):succeeded, !=0:error */
+ FATFS* fs, /* Corresponding filesystem object */
+ DWORD clst, /* FAT index number (cluster number) to be changed */
+ DWORD val /* New value to be set to the entry */
+)
+{
+ UINT bc;
+ BYTE *p;
+ FRESULT res = FR_INT_ERR;
+
+
+ if (clst >= 2 && clst < fs->n_fatent) { /* Check if in valid range */
+ switch (fs->fs_type) {
+ case FS_FAT12 :
+ bc = (UINT)clst; bc += bc / 2; /* bc: byte offset of the entry */
+ res = move_window(fs, fs->fatbase + (bc / SS(fs)));
+ if (res != FR_OK) break;
+ p = fs->win + bc++ % SS(fs);
+ *p = (clst & 1) ? ((*p & 0x0F) | ((BYTE)val << 4)) : (BYTE)val; /* Put 1st byte */
+ fs->wflag = 1;
+ res = move_window(fs, fs->fatbase + (bc / SS(fs)));
+ if (res != FR_OK) break;
+ p = fs->win + bc % SS(fs);
+ *p = (clst & 1) ? (BYTE)(val >> 4) : ((*p & 0xF0) | ((BYTE)(val >> 8) & 0x0F)); /* Put 2nd byte */
+ fs->wflag = 1;
+ break;
+
+ case FS_FAT16 :
+ res = move_window(fs, fs->fatbase + (clst / (SS(fs) / 2)));
+ if (res != FR_OK) break;
+ st_word(fs->win + clst * 2 % SS(fs), (WORD)val); /* Simple WORD array */
+ fs->wflag = 1;
+ break;
+
+ case FS_FAT32 :
+#if FF_FS_EXFAT
+ case FS_EXFAT :
+#endif
+ res = move_window(fs, fs->fatbase + (clst / (SS(fs) / 4)));
+ if (res != FR_OK) break;
+ if (!FF_FS_EXFAT || fs->fs_type != FS_EXFAT) {
+ val = (val & 0x0FFFFFFF) | (ld_dword(fs->win + clst * 4 % SS(fs)) & 0xF0000000);
+ }
+ st_dword(fs->win + clst * 4 % SS(fs), val);
+ fs->wflag = 1;
+ break;
+ }
+ }
+ return res;
+}
+
+#endif /* !FF_FS_READONLY */
+
+
+
+
+#if FF_FS_EXFAT && !FF_FS_READONLY
+/*-----------------------------------------------------------------------*/
+/* exFAT: Accessing FAT and Allocation Bitmap */
+/*-----------------------------------------------------------------------*/
+
+/*--------------------------------------*/
+/* Find a contiguous free cluster block */
+/*--------------------------------------*/
+
+static DWORD find_bitmap ( /* 0:Not found, 2..:Cluster block found, 0xFFFFFFFF:Disk error */
+ FATFS* fs, /* Filesystem object */
+ DWORD clst, /* Cluster number to scan from */
+ DWORD ncl /* Number of contiguous clusters to find (1..) */
+)
+{
+ BYTE bm, bv;
+ UINT i;
+ DWORD val, scl, ctr;
+
+
+ clst -= 2; /* The first bit in the bitmap corresponds to cluster #2 */
+ if (clst >= fs->n_fatent - 2) clst = 0;
+ scl = val = clst; ctr = 0;
+ for (;;) {
+ if (move_window(fs, fs->database + val / 8 / SS(fs)) != FR_OK) return 0xFFFFFFFF; /* (assuming bitmap is located top of the cluster heap) */
+ i = val / 8 % SS(fs); bm = 1 << (val % 8);
+ do {
+ do {
+ bv = fs->win[i] & bm; bm <<= 1; /* Get bit value */
+ if (++val >= fs->n_fatent - 2) { /* Next cluster (with wrap-around) */
+ val = 0; bm = 0; i = SS(fs);
+ }
+ if (bv == 0) { /* Is it a free cluster? */
+ if (++ctr == ncl) return scl + 2; /* Check if run length is sufficient for required */
+ } else {
+ scl = val; ctr = 0; /* Encountered a cluster in-use, restart to scan */
+ }
+ if (val == clst) return 0; /* All cluster scanned? */
+ } while (bm != 0);
+ bm = 1;
+ } while (++i < SS(fs));
+ }
+}
+
+
+/*----------------------------------------*/
+/* Set/Clear a block of allocation bitmap */
+/*----------------------------------------*/
+
+static FRESULT change_bitmap (
+ FATFS* fs, /* Filesystem object */
+ DWORD clst, /* Cluster number to change from */
+ DWORD ncl, /* Number of clusters to be changed */
+ int bv /* bit value to be set (0 or 1) */
+)
+{
+ BYTE bm;
+ UINT i;
+ DWORD sect;
+
+
+ clst -= 2; /* The first bit corresponds to cluster #2 */
+ sect = fs->database + clst / 8 / SS(fs); /* Sector address (assuming bitmap is located top of the cluster heap) */
+ i = clst / 8 % SS(fs); /* Byte offset in the sector */
+ bm = 1 << (clst % 8); /* Bit mask in the byte */
+ for (;;) {
+ if (move_window(fs, sect++) != FR_OK) return FR_DISK_ERR;
+ do {
+ do {
+ if (bv == (int)((fs->win[i] & bm) != 0)) return FR_INT_ERR; /* Is the bit expected value? */
+ fs->win[i] ^= bm; /* Flip the bit */
+ fs->wflag = 1;
+ if (--ncl == 0) return FR_OK; /* All bits processed? */
+ } while (bm <<= 1); /* Next bit */
+ bm = 1;
+ } while (++i < SS(fs)); /* Next byte */
+ i = 0;
+ }
+}
+
+
+/*---------------------------------------------*/
+/* Fill the first fragment of the FAT chain */
+/*---------------------------------------------*/
+
+static FRESULT fill_first_frag (
+ FFOBJID* obj /* Pointer to the corresponding object */
+)
+{
+ FRESULT res = FR_DISK_ERR;
+ DWORD cl, n;
+
+
+ if (obj->stat == 3) { /* Has the object been changed 'fragmented' in this session? */
+ for (cl = obj->sclust, n = obj->n_cont; n; cl++, n--) { /* Create cluster chain on the FAT */
+ res = put_fat(obj->fs, cl, cl + 1);
+ if (res != FR_OK) return res;
+ }
+ obj->stat = 0; /* Change status 'FAT chain is valid' */
+ }
+ return FR_OK;
+}
+
+
+/*---------------------------------------------*/
+/* Fill the last fragment of the FAT chain */
+/*---------------------------------------------*/
+
+static FRESULT fill_last_frag (
+ FFOBJID* obj, /* Pointer to the corresponding object */
+ DWORD lcl, /* Last cluster of the fragment */
+ DWORD term /* Value to set the last FAT entry */
+)
+{
+ FRESULT res = FR_DISK_ERR;
+
+
+ while (obj->n_frag > 0) { /* Create the chain of last fragment */
+ res = put_fat(obj->fs, lcl - obj->n_frag + 1, (obj->n_frag > 1) ? lcl - obj->n_frag + 2 : term);
+ if (res != FR_OK) return res;
+ obj->n_frag--;
+ }
+ return FR_OK;
+}
+
+#endif /* FF_FS_EXFAT && !FF_FS_READONLY */
+
+
+
+#if !FF_FS_READONLY
+/*-----------------------------------------------------------------------*/
+/* FAT handling - Remove a cluster chain */
+/*-----------------------------------------------------------------------*/
+
+static FRESULT remove_chain ( /* FR_OK(0):succeeded, !=0:error */
+ FFOBJID* obj, /* Corresponding object */
+ DWORD clst, /* Cluster to remove a chain from */
+ DWORD pclst /* Previous cluster of clst (0:entire chain) */
+)
+{
+ FRESULT res = FR_DISK_ERR;
+ DWORD nxt;
+ FATFS *fs = obj->fs;
+#if FF_FS_EXFAT || FF_USE_TRIM
+ DWORD scl = clst, ecl = clst;
+#endif
+#if FF_USE_TRIM
+ DWORD rt[2];
+#endif
+
+ if (clst < 2 || clst >= fs->n_fatent) return FR_INT_ERR; /* Check if in valid range */
+
+ /* Mark the previous cluster 'EOC' on the FAT if it exists */
+ if (pclst != 0 && (!FF_FS_EXFAT || fs->fs_type != FS_EXFAT || obj->stat != 2)) {
+ res = put_fat(fs, pclst, 0xFFFFFFFF);
+ if (res != FR_OK) return res;
+ }
+
+ /* Remove the chain */
+ do {
+ nxt = get_fat(obj, clst); /* Get cluster status */
+ if (nxt == 0) break; /* Empty cluster? */
+ if (nxt == 1) return FR_INT_ERR; /* Internal error? */
+ if (nxt == 0xFFFFFFFF) return FR_DISK_ERR; /* Disk error? */
+ if (!FF_FS_EXFAT || fs->fs_type != FS_EXFAT) {
+ res = put_fat(fs, clst, 0); /* Mark the cluster 'free' on the FAT */
+ if (res != FR_OK) return res;
+ }
+ if (fs->free_clst < fs->n_fatent - 2) { /* Update FSINFO */
+ fs->free_clst++;
+ fs->fsi_flag |= 1;
+ }
+#if FF_FS_EXFAT || FF_USE_TRIM
+ if (ecl + 1 == nxt) { /* Is next cluster contiguous? */
+ ecl = nxt;
+ } else { /* End of contiguous cluster block */
+#if FF_FS_EXFAT
+ if (fs->fs_type == FS_EXFAT) {
+ res = change_bitmap(fs, scl, ecl - scl + 1, 0); /* Mark the cluster block 'free' on the bitmap */
+ if (res != FR_OK) return res;
+ }
+#endif
+#if FF_USE_TRIM
+ rt[0] = clst2sect(fs, scl); /* Start of data area freed */
+ rt[1] = clst2sect(fs, ecl) + fs->csize - 1; /* End of data area freed */
+ disk_ioctl(fs->pdrv, CTRL_TRIM, rt); /* Inform device the data in the block is no longer needed */
+#endif
+ scl = ecl = nxt;
+ }
+#endif
+ clst = nxt; /* Next cluster */
+ } while (clst < fs->n_fatent); /* Repeat while not the last link */
+
+#if FF_FS_EXFAT
+ /* Some post processes for chain status */
+ if (fs->fs_type == FS_EXFAT) {
+ if (pclst == 0) { /* Has the entire chain been removed? */
+ obj->stat = 0; /* Change the chain status 'initial' */
+ } else {
+ if (obj->stat == 0) { /* Is it a fragmented chain from the beginning of this session? */
+ clst = obj->sclust; /* Follow the chain to check if it gets contiguous */
+ while (clst != pclst) {
+ nxt = get_fat(obj, clst);
+ if (nxt < 2) return FR_INT_ERR;
+ if (nxt == 0xFFFFFFFF) return FR_DISK_ERR;
+ if (nxt != clst + 1) break; /* Not contiguous? */
+ clst++;
+ }
+ if (clst == pclst) { /* Has the chain got contiguous again? */
+ obj->stat = 2; /* Change the chain status 'contiguous' */
+ }
+ } else {
+ if (obj->stat == 3 && pclst >= obj->sclust && pclst <= obj->sclust + obj->n_cont) { /* Was the chain fragmented in this session and got contiguous again? */
+ obj->stat = 2; /* Change the chain status 'contiguous' */
+ }
+ }
+ }
+ }
+#endif
+ return FR_OK;
+}
+
+
+
+
+/*-----------------------------------------------------------------------*/
+/* FAT handling - Stretch a chain or Create a new chain */
+/*-----------------------------------------------------------------------*/
+
+static DWORD create_chain ( /* 0:No free cluster, 1:Internal error, 0xFFFFFFFF:Disk error, >=2:New cluster# */
+ FFOBJID* obj, /* Corresponding object */
+ DWORD clst /* Cluster# to stretch, 0:Create a new chain */
+)
+{
+ DWORD cs, ncl, scl;
+ FRESULT res = FR_DISK_ERR;
+ FATFS *fs = obj->fs;
+
+
+ if (clst == 0) { /* Create a new chain */
+ scl = fs->last_clst; /* Suggested cluster to start to find */
+ if (scl == 0 || scl >= fs->n_fatent) scl = 1;
+ }
+ else { /* Stretch a chain */
+ cs = get_fat(obj, clst); /* Check the cluster status */
+ if (cs < 2) return 1; /* Test for insanity */
+ if (cs == 0xFFFFFFFF) return cs; /* Test for disk error */
+ if (cs < fs->n_fatent) return cs; /* It is already followed by next cluster */
+ scl = clst; /* Cluster to start to find */
+ }
+ if (fs->free_clst == 0) return 0; /* No free cluster */
+
+#if FF_FS_EXFAT
+ if (fs->fs_type == FS_EXFAT) { /* On the exFAT volume */
+ ncl = find_bitmap(fs, scl, 1); /* Find a free cluster */
+ if (ncl == 0 || ncl == 0xFFFFFFFF) return ncl; /* No free cluster or hard error? */
+ res = change_bitmap(fs, ncl, 1, 1); /* Mark the cluster 'in use' */
+ if (res == FR_INT_ERR) return 1;
+ if (res == FR_DISK_ERR) return 0xFFFFFFFF;
+ if (clst == 0) { /* Is it a new chain? */
+ obj->stat = 2; /* Set status 'contiguous' */
+ } else { /* It is a stretched chain */
+ if (obj->stat == 2 && ncl != scl + 1) { /* Is the chain got fragmented? */
+ obj->n_cont = scl - obj->sclust; /* Set size of the contiguous part */
+ obj->stat = 3; /* Change status 'just fragmented' */
+ }
+ }
+ if (obj->stat != 2) { /* Is the file non-contiguous? */
+ if (ncl == clst + 1) { /* Is the cluster next to previous one? */
+ obj->n_frag = obj->n_frag ? obj->n_frag + 1 : 2; /* Increment size of last framgent */
+ } else { /* New fragment */
+ if (obj->n_frag == 0) obj->n_frag = 1;
+ res = fill_last_frag(obj, clst, ncl); /* Fill last fragment on the FAT and link it to new one */
+ if (res == FR_OK) obj->n_frag = 1;
+ }
+ }
+ } else
+#endif
+ { /* On the FAT/FAT32 volume */
+ ncl = 0;
+ if (scl == clst) { /* Stretching an existing chain? */
+ ncl = scl + 1; /* Test if next cluster is free */
+ if (ncl >= fs->n_fatent) ncl = 2;
+ cs = get_fat(obj, ncl); /* Get next cluster status */
+ if (cs == 1 || cs == 0xFFFFFFFF) return cs; /* Test for error */
+ if (cs != 0) { /* Not free? */
+ cs = fs->last_clst; /* Start at suggested cluster if it is valid */
+ if (cs >= 2 && cs < fs->n_fatent) scl = cs;
+ ncl = 0;
+ }
+ }
+ if (ncl == 0) { /* The new cluster cannot be contiguous and find another fragment */
+ ncl = scl; /* Start cluster */
+ for (;;) {
+ ncl++; /* Next cluster */
+ if (ncl >= fs->n_fatent) { /* Check wrap-around */
+ ncl = 2;
+ if (ncl > scl) return 0; /* No free cluster found? */
+ }
+ cs = get_fat(obj, ncl); /* Get the cluster status */
+ if (cs == 0) break; /* Found a free cluster? */
+ if (cs == 1 || cs == 0xFFFFFFFF) return cs; /* Test for error */
+ if (ncl == scl) return 0; /* No free cluster found? */
+ }
+ }
+ res = put_fat(fs, ncl, 0xFFFFFFFF); /* Mark the new cluster 'EOC' */
+ if (res == FR_OK && clst != 0) {
+ res = put_fat(fs, clst, ncl); /* Link it from the previous one if needed */
+ }
+ }
+
+ if (res == FR_OK) { /* Update FSINFO if function succeeded. */
+ fs->last_clst = ncl;
+ if (fs->free_clst <= fs->n_fatent - 2) fs->free_clst--;
+ fs->fsi_flag |= 1;
+ } else {
+ ncl = (res == FR_DISK_ERR) ? 0xFFFFFFFF : 1; /* Failed. Generate error status */
+ }
+
+ return ncl; /* Return new cluster number or error status */
+}
+
+#endif /* !FF_FS_READONLY */
+
+
+
+
+#if FF_USE_FASTSEEK
+/*-----------------------------------------------------------------------*/
+/* FAT handling - Convert offset into cluster with link map table */
+/*-----------------------------------------------------------------------*/
+
+static DWORD clmt_clust ( /* <2:Error, >=2:Cluster number */
+ FIL* fp, /* Pointer to the file object */
+ FSIZE_t ofs /* File offset to be converted to cluster# */
+)
+{
+ DWORD cl, ncl, *tbl;
+ FATFS *fs = fp->obj.fs;
+
+
+ tbl = fp->cltbl + 1; /* Top of CLMT */
+ cl = (DWORD)(ofs / SS(fs) / fs->csize); /* Cluster order from top of the file */
+ for (;;) {
+ ncl = *tbl++; /* Number of cluters in the fragment */
+ if (ncl == 0) return 0; /* End of table? (error) */
+ if (cl < ncl) break; /* In this fragment? */
+ cl -= ncl; tbl++; /* Next fragment */
+ }
+ return cl + *tbl; /* Return the cluster number */
+}
+
+#endif /* FF_USE_FASTSEEK */
+
+
+
+
+/*-----------------------------------------------------------------------*/
+/* Directory handling - Fill a cluster with zeros */
+/*-----------------------------------------------------------------------*/
+
+#if !FF_FS_READONLY
+static FRESULT dir_clear ( /* Returns FR_OK or FR_DISK_ERR */
+ FATFS *fs, /* Filesystem object */
+ DWORD clst /* Directory table to clear */
+)
+{
+ DWORD sect;
+ UINT n, szb;
+ BYTE *ibuf;
+
+
+ if (sync_window(fs) != FR_OK) return FR_DISK_ERR; /* Flush disk access window */
+ sect = clst2sect(fs, clst); /* Top of the cluster */
+ fs->winsect = sect; /* Set window to top of the cluster */
+ mem_set(fs->win, 0, SS(fs)); /* Clear window buffer */
+#if FF_USE_LFN == 3 /* Quick table clear by using multi-secter write */
+ /* Allocate a temporary buffer */
+ for (szb = ((DWORD)fs->csize * SS(fs) >= MAX_MALLOC) ? MAX_MALLOC : fs->csize * SS(fs), ibuf = 0; szb > SS(fs) && (ibuf = ff_memalloc(szb)) == 0; szb /= 2) ;
+ if (szb > SS(fs)) { /* Buffer allocated? */
+ mem_set(ibuf, 0, szb);
+ szb /= SS(fs); /* Bytes -> Sectors */
+ for (n = 0; n < fs->csize && disk_write(fs->pdrv, ibuf, sect + n, szb) == RES_OK; n += szb) ; /* Fill the cluster with 0 */
+ ff_memfree(ibuf);
+ } else
+#endif
+ {
+ ibuf = fs->win; szb = 1; /* Use window buffer (many single-sector writes may take a time) */
+ for (n = 0; n < fs->csize && disk_write(fs->pdrv, ibuf, sect + n, szb) == RES_OK; n += szb) ; /* Fill the cluster with 0 */
+ }
+ return (n == fs->csize) ? FR_OK : FR_DISK_ERR;
+}
+#endif /* !FF_FS_READONLY */
+
+
+
+
+/*-----------------------------------------------------------------------*/
+/* Directory handling - Set directory index */
+/*-----------------------------------------------------------------------*/
+
+static FRESULT dir_sdi ( /* FR_OK(0):succeeded, !=0:error */
+ DIR* dp, /* Pointer to directory object */
+ DWORD ofs /* Offset of directory table */
+)
+{
+ DWORD csz, clst;
+ FATFS *fs = dp->obj.fs;
+
+
+ if (ofs >= (DWORD)((FF_FS_EXFAT && fs->fs_type == FS_EXFAT) ? MAX_DIR_EX : MAX_DIR) || ofs % SZDIRE) { /* Check range of offset and alignment */
+ return FR_INT_ERR;
+ }
+ dp->dptr = ofs; /* Set current offset */
+ clst = dp->obj.sclust; /* Table start cluster (0:root) */
+ if (clst == 0 && fs->fs_type >= FS_FAT32) { /* Replace cluster# 0 with root cluster# */
+ clst = fs->dirbase;
+ if (FF_FS_EXFAT) dp->obj.stat = 0; /* exFAT: Root dir has an FAT chain */
+ }
+
+ if (clst == 0) { /* Static table (root-directory on the FAT volume) */
+ if (ofs / SZDIRE >= fs->n_rootdir) return FR_INT_ERR; /* Is index out of range? */
+ dp->sect = fs->dirbase;
+
+ } else { /* Dynamic table (sub-directory or root-directory on the FAT32/exFAT volume) */
+ csz = (DWORD)fs->csize * SS(fs); /* Bytes per cluster */
+ while (ofs >= csz) { /* Follow cluster chain */
+ clst = get_fat(&dp->obj, clst); /* Get next cluster */
+ if (clst == 0xFFFFFFFF) return FR_DISK_ERR; /* Disk error */
+ if (clst < 2 || clst >= fs->n_fatent) return FR_INT_ERR; /* Reached to end of table or internal error */
+ ofs -= csz;
+ }
+ dp->sect = clst2sect(fs, clst);
+ }
+ dp->clust = clst; /* Current cluster# */
+ if (dp->sect == 0) return FR_INT_ERR;
+ dp->sect += ofs / SS(fs); /* Sector# of the directory entry */
+ dp->dir = fs->win + (ofs % SS(fs)); /* Pointer to the entry in the win[] */
+
+ return FR_OK;
+}
+
+
+
+
+/*-----------------------------------------------------------------------*/
+/* Directory handling - Move directory table index next */
+/*-----------------------------------------------------------------------*/
+
+static FRESULT dir_next ( /* FR_OK(0):succeeded, FR_NO_FILE:End of table, FR_DENIED:Could not stretch */
+ DIR* dp, /* Pointer to the directory object */
+ int stretch /* 0: Do not stretch table, 1: Stretch table if needed */
+)
+{
+ DWORD ofs, clst;
+ FATFS *fs = dp->obj.fs;
+
+
+ ofs = dp->dptr + SZDIRE; /* Next entry */
+ if (ofs >= (DWORD)((FF_FS_EXFAT && fs->fs_type == FS_EXFAT) ? MAX_DIR_EX : MAX_DIR)) dp->sect = 0; /* Disable it if the offset reached the max value */
+ if (dp->sect == 0) return FR_NO_FILE; /* Report EOT if it has been disabled */
+
+ if (ofs % SS(fs) == 0) { /* Sector changed? */
+ dp->sect++; /* Next sector */
+
+ if (dp->clust == 0) { /* Static table */
+ if (ofs / SZDIRE >= fs->n_rootdir) { /* Report EOT if it reached end of static table */
+ dp->sect = 0; return FR_NO_FILE;
+ }
+ }
+ else { /* Dynamic table */
+ if ((ofs / SS(fs) & (fs->csize - 1)) == 0) { /* Cluster changed? */
+ clst = get_fat(&dp->obj, dp->clust); /* Get next cluster */
+ if (clst <= 1) return FR_INT_ERR; /* Internal error */
+ if (clst == 0xFFFFFFFF) return FR_DISK_ERR; /* Disk error */
+ if (clst >= fs->n_fatent) { /* It reached end of dynamic table */
+#if !FF_FS_READONLY
+ if (!stretch) { /* If no stretch, report EOT */
+ dp->sect = 0; return FR_NO_FILE;
+ }
+ clst = create_chain(&dp->obj, dp->clust); /* Allocate a cluster */
+ if (clst == 0) return FR_DENIED; /* No free cluster */
+ if (clst == 1) return FR_INT_ERR; /* Internal error */
+ if (clst == 0xFFFFFFFF) return FR_DISK_ERR; /* Disk error */
+ if (dir_clear(fs, clst) != FR_OK) return FR_DISK_ERR; /* Clean up the stretched table */
+ if (FF_FS_EXFAT) dp->obj.stat |= 4; /* exFAT: The directory has been stretched */
+#else
+ if (!stretch) dp->sect = 0; /* (this line is to suppress compiler warning) */
+ dp->sect = 0; return FR_NO_FILE; /* Report EOT */
+#endif
+ }
+ dp->clust = clst; /* Initialize data for new cluster */
+ dp->sect = clst2sect(fs, clst);
+ }
+ }
+ }
+ dp->dptr = ofs; /* Current entry */
+ dp->dir = fs->win + ofs % SS(fs); /* Pointer to the entry in the win[] */
+
+ return FR_OK;
+}
+
+
+
+
+#if !FF_FS_READONLY
+/*-----------------------------------------------------------------------*/
+/* Directory handling - Reserve a block of directory entries */
+/*-----------------------------------------------------------------------*/
+
+static FRESULT dir_alloc ( /* FR_OK(0):succeeded, !=0:error */
+ DIR* dp, /* Pointer to the directory object */
+ UINT nent /* Number of contiguous entries to allocate */
+)
+{
+ FRESULT res = FR_DISK_ERR;
+ UINT n;
+ FATFS *fs = dp->obj.fs;
+
+
+ res = dir_sdi(dp, 0);
+ if (res == FR_OK) {
+ n = 0;
+ do {
+ res = move_window(fs, dp->sect);
+ if (res != FR_OK) break;
+#if FF_FS_EXFAT
+ if ((fs->fs_type == FS_EXFAT) ? (int)((dp->dir[XDIR_Type] & 0x80) == 0) : (int)(dp->dir[DIR_Name] == DDEM || dp->dir[DIR_Name] == 0)) {
+#else
+ if (dp->dir[DIR_Name] == DDEM || dp->dir[DIR_Name] == 0) {
+#endif
+ if (++n == nent) break; /* A block of contiguous free entries is found */
+ } else {
+ n = 0; /* Not a blank entry. Restart to search */
+ }
+ res = dir_next(dp, 1);
+ } while (res == FR_OK); /* Next entry with table stretch enabled */
+ }
+
+ if (res == FR_NO_FILE) res = FR_DENIED; /* No directory entry to allocate */
+ return res;
+}
+
+#endif /* !FF_FS_READONLY */
+
+
+
+
+/*-----------------------------------------------------------------------*/
+/* FAT: Directory handling - Load/Store start cluster number */
+/*-----------------------------------------------------------------------*/
+
+static DWORD ld_clust ( /* Returns the top cluster value of the SFN entry */
+ FATFS* fs, /* Pointer to the fs object */
+ const BYTE* dir /* Pointer to the key entry */
+)
+{
+ DWORD cl;
+
+ cl = ld_word(dir + DIR_FstClusLO);
+ if (fs->fs_type == FS_FAT32) {
+ cl |= (DWORD)ld_word(dir + DIR_FstClusHI) << 16;
+ }
+
+ return cl;
+}
+
+
+#if !FF_FS_READONLY
+static void st_clust (
+ FATFS* fs, /* Pointer to the fs object */
+ BYTE* dir, /* Pointer to the key entry */
+ DWORD cl /* Value to be set */
+)
+{
+ st_word(dir + DIR_FstClusLO, (WORD)cl);
+ if (fs->fs_type == FS_FAT32) {
+ st_word(dir + DIR_FstClusHI, (WORD)(cl >> 16));
+ }
+}
+#endif
+
+
+
+#if FF_USE_LFN
+/*--------------------------------------------------------*/
+/* FAT-LFN: Compare a part of file name with an LFN entry */
+/*--------------------------------------------------------*/
+
+static int cmp_lfn ( /* 1:matched, 0:not matched */
+ const WCHAR* lfnbuf, /* Pointer to the LFN working buffer to be compared */
+ BYTE* dir /* Pointer to the directory entry containing the part of LFN */
+)
+{
+ UINT i, s;
+ WCHAR wc, uc;
+
+
+ if (ld_word(dir + LDIR_FstClusLO) != 0) return 0; /* Check LDIR_FstClusLO */
+
+ i = ((dir[LDIR_Ord] & 0x3F) - 1) * 13; /* Offset in the LFN buffer */
+
+ for (wc = 1, s = 0; s < 13; s++) { /* Process all characters in the entry */
+ uc = ld_word(dir + LfnOfs[s]); /* Pick an LFN character */
+ if (wc != 0) {
+ if (i >= FF_MAX_LFN || ff_wtoupper(uc) != ff_wtoupper(lfnbuf[i++])) { /* Compare it */
+ return 0; /* Not matched */
+ }
+ wc = uc;
+ } else {
+ if (uc != 0xFFFF) return 0; /* Check filler */
+ }
+ }
+
+ if ((dir[LDIR_Ord] & LLEF) && wc && lfnbuf[i]) return 0; /* Last segment matched but different length */
+
+ return 1; /* The part of LFN matched */
+}
+
+
+#if FF_FS_MINIMIZE <= 1 || FF_FS_RPATH >= 2 || FF_USE_LABEL || FF_FS_EXFAT
+/*-----------------------------------------------------*/
+/* FAT-LFN: Pick a part of file name from an LFN entry */
+/*-----------------------------------------------------*/
+
+static int pick_lfn ( /* 1:succeeded, 0:buffer overflow or invalid LFN entry */
+ WCHAR* lfnbuf, /* Pointer to the LFN working buffer */
+ BYTE* dir /* Pointer to the LFN entry */
+)
+{
+ UINT i, s;
+ WCHAR wc, uc;
+
+
+ if (ld_word(dir + LDIR_FstClusLO) != 0) return 0; /* Check LDIR_FstClusLO is 0 */
+
+ i = ((dir[LDIR_Ord] & ~LLEF) - 1) * 13; /* Offset in the LFN buffer */
+
+ for (wc = 1, s = 0; s < 13; s++) { /* Process all characters in the entry */
+ uc = ld_word(dir + LfnOfs[s]); /* Pick an LFN character */
+ if (wc != 0) {
+ if (i >= FF_MAX_LFN) return 0; /* Buffer overflow? */
+ lfnbuf[i++] = wc = uc; /* Store it */
+ } else {
+ if (uc != 0xFFFF) return 0; /* Check filler */
+ }
+ }
+
+ if (dir[LDIR_Ord] & LLEF) { /* Put terminator if it is the last LFN part */
+ if (i >= FF_MAX_LFN) return 0; /* Buffer overflow? */
+ lfnbuf[i] = 0;
+ }
+
+ return 1; /* The part of LFN is valid */
+}
+#endif
+
+
+#if !FF_FS_READONLY
+/*-----------------------------------------*/
+/* FAT-LFN: Create an entry of LFN entries */
+/*-----------------------------------------*/
+
+static void put_lfn (
+ const WCHAR* lfn, /* Pointer to the LFN */
+ BYTE* dir, /* Pointer to the LFN entry to be created */
+ BYTE ord, /* LFN order (1-20) */
+ BYTE sum /* Checksum of the corresponding SFN */
+)
+{
+ UINT i, s;
+ WCHAR wc;
+
+
+ dir[LDIR_Chksum] = sum; /* Set checksum */
+ dir[LDIR_Attr] = AM_LFN; /* Set attribute. LFN entry */
+ dir[LDIR_Type] = 0;
+ st_word(dir + LDIR_FstClusLO, 0);
+
+ i = (ord - 1) * 13; /* Get offset in the LFN working buffer */
+ s = wc = 0;
+ do {
+ if (wc != 0xFFFF) wc = lfn[i++]; /* Get an effective character */
+ st_word(dir + LfnOfs[s], wc); /* Put it */
+ if (wc == 0) wc = 0xFFFF; /* Padding characters for left locations */
+ } while (++s < 13);
+ if (wc == 0xFFFF || !lfn[i]) ord |= LLEF; /* Last LFN part is the start of LFN sequence */
+ dir[LDIR_Ord] = ord; /* Set the LFN order */
+}
+
+#endif /* !FF_FS_READONLY */
+#endif /* FF_USE_LFN */
+
+
+
+#if FF_USE_LFN && !FF_FS_READONLY
+/*-----------------------------------------------------------------------*/
+/* FAT-LFN: Create a Numbered SFN */
+/*-----------------------------------------------------------------------*/
+
+static void gen_numname (
+ BYTE* dst, /* Pointer to the buffer to store numbered SFN */
+ const BYTE* src, /* Pointer to SFN */
+ const WCHAR* lfn, /* Pointer to LFN */
+ UINT seq /* Sequence number */
+)
+{
+ BYTE ns[8], c;
+ UINT i, j;
+ WCHAR wc;
+ DWORD sr;
+
+
+ mem_cpy(dst, src, 11);
+
+ if (seq > 5) { /* In case of many collisions, generate a hash number instead of sequential number */
+ sr = seq;
+ while (*lfn) { /* Create a CRC as hash value */
+ wc = *lfn++;
+ for (i = 0; i < 16; i++) {
+ sr = (sr << 1) + (wc & 1);
+ wc >>= 1;
+ if (sr & 0x10000) sr ^= 0x11021;
+ }
+ }
+ seq = (UINT)sr;
+ }
+
+ /* itoa (hexdecimal) */
+ i = 7;
+ do {
+ c = (BYTE)((seq % 16) + '0');
+ if (c > '9') c += 7;
+ ns[i--] = c;
+ seq /= 16;
+ } while (seq);
+ ns[i] = '~';
+
+ /* Append the number to the SFN body */
+ for (j = 0; j < i && dst[j] != ' '; j++) {
+ if (dbc_1st(dst[j])) {
+ if (j == i - 1) break;
+ j++;
+ }
+ }
+ do {
+ dst[j++] = (i < 8) ? ns[i++] : ' ';
+ } while (j < 8);
+}
+#endif /* FF_USE_LFN && !FF_FS_READONLY */
+
+
+
+#if FF_USE_LFN
+/*-----------------------------------------------------------------------*/
+/* FAT-LFN: Calculate checksum of an SFN entry */
+/*-----------------------------------------------------------------------*/
+
+static BYTE sum_sfn (
+ const BYTE* dir /* Pointer to the SFN entry */
+)
+{
+ BYTE sum = 0;
+ UINT n = 11;
+
+ do {
+ sum = (sum >> 1) + (sum << 7) + *dir++;
+ } while (--n);
+ return sum;
+}
+
+#endif /* FF_USE_LFN */
+
+
+
+#if FF_FS_EXFAT
+/*-----------------------------------------------------------------------*/
+/* exFAT: Checksum */
+/*-----------------------------------------------------------------------*/
+
+static WORD xdir_sum ( /* Get checksum of the directoly entry block */
+ const BYTE* dir /* Directory entry block to be calculated */
+)
+{
+ UINT i, szblk;
+ WORD sum;
+
+
+ szblk = (dir[XDIR_NumSec] + 1) * SZDIRE; /* Number of bytes of the entry block */
+ for (i = sum = 0; i < szblk; i++) {
+ if (i == XDIR_SetSum) { /* Skip 2-byte sum field */
+ i++;
+ } else {
+ sum = ((sum & 1) ? 0x8000 : 0) + (sum >> 1) + dir[i];
+ }
+ }
+ return sum;
+}
+
+
+
+static WORD xname_sum ( /* Get check sum (to be used as hash) of the file name */
+ const WCHAR* name /* File name to be calculated */
+)
+{
+ WCHAR chr;
+ WORD sum = 0;
+
+
+ while ((chr = *name++) != 0) {
+ chr = (WCHAR)ff_wtoupper(chr); /* File name needs to be up-case converted */
+ sum = ((sum & 1) ? 0x8000 : 0) + (sum >> 1) + (chr & 0xFF);
+ sum = ((sum & 1) ? 0x8000 : 0) + (sum >> 1) + (chr >> 8);
+ }
+ return sum;
+}
+
+
+#if !FF_FS_READONLY && FF_USE_MKFS
+static DWORD xsum32 ( /* Returns 32-bit checksum */
+ BYTE dat, /* Byte to be calculated (byte-by-byte processing) */
+ DWORD sum /* Previous sum value */
+)
+{
+ sum = ((sum & 1) ? 0x80000000 : 0) + (sum >> 1) + dat;
+ return sum;
+}
+#endif
+
+
+#if FF_FS_MINIMIZE <= 1 || FF_FS_RPATH >= 2
+/*------------------------------------------------------*/
+/* exFAT: Get object information from a directory block */
+/*------------------------------------------------------*/
+
+static void get_xfileinfo (
+ BYTE* dirb, /* Pointer to the directory entry block 85+C0+C1s */
+ FILINFO* fno /* Buffer to store the extracted file information */
+)
+{
+ WCHAR wc, hs;
+ UINT di, si, nc;
+
+ /* Get file name from the entry block */
+ si = SZDIRE * 2; /* 1st C1 entry */
+ nc = 0; hs = 0; di = 0;
+ while (nc < dirb[XDIR_NumName]) {
+ if (si >= MAXDIRB(FF_MAX_LFN)) { di = 0; break; } /* Truncated directory block? */
+ if ((si % SZDIRE) == 0) si += 2; /* Skip entry type field */
+ wc = ld_word(dirb + si); si += 2; nc++; /* Get a character */
+ if (hs == 0 && IsSurrogate(wc)) { /* Is it a surrogate? */
+ hs = wc; continue; /* Get low surrogate */
+ }
+ wc = put_utf((DWORD)hs << 16 | wc, &fno->fname[di], FF_LFN_BUF - di); /* Store it in API encoding */
+ if (wc == 0) { di = 0; break; } /* Buffer overflow or wrong encoding? */
+ di += wc;
+ hs = 0;
+ }
+ if (hs != 0) di = 0; /* Broken surrogate pair? */
+ if (di == 0) fno->fname[di++] = '?'; /* Inaccessible object name? */
+ fno->fname[di] = 0; /* Terminate the name */
+ fno->altname[0] = 0; /* exFAT does not support SFN */
+
+ fno->fattrib = dirb[XDIR_Attr]; /* Attribute */
+ fno->fsize = (fno->fattrib & AM_DIR) ? 0 : ld_qword(dirb + XDIR_FileSize); /* Size */
+ fno->ftime = ld_word(dirb + XDIR_ModTime + 0); /* Time */
+ fno->fdate = ld_word(dirb + XDIR_ModTime + 2); /* Date */
+}
+
+#endif /* FF_FS_MINIMIZE <= 1 || FF_FS_RPATH >= 2 */
+
+
+/*-----------------------------------*/
+/* exFAT: Get a directory entry block */
+/*-----------------------------------*/
+
+static FRESULT load_xdir ( /* FR_INT_ERR: invalid entry block */
+ DIR* dp /* Reading directory object pointing top of the entry block to load */
+)
+{
+ FRESULT res = FR_DISK_ERR;
+ UINT i, sz_ent;
+ BYTE* dirb = dp->obj.fs->dirbuf; /* Pointer to the on-memory directory entry block 85+C0+C1s */
+
+
+ /* Load 85 entry */
+ res = move_window(dp->obj.fs, dp->sect);
+ if (res != FR_OK) return res;
+ if (dp->dir[XDIR_Type] != 0x85) return FR_INT_ERR; /* Invalid order */
+ mem_cpy(dirb + 0 * SZDIRE, dp->dir, SZDIRE);
+ sz_ent = (dirb[XDIR_NumSec] + 1) * SZDIRE;
+ if (sz_ent < 3 * SZDIRE || sz_ent > 19 * SZDIRE) return FR_INT_ERR;
+
+ /* Load C0 entry */
+ res = dir_next(dp, 0);
+ if (res == FR_NO_FILE) res = FR_INT_ERR; /* It cannot be */
+ if (res != FR_OK) return res;
+ res = move_window(dp->obj.fs, dp->sect);
+ if (res != FR_OK) return res;
+ if (dp->dir[XDIR_Type] != 0xC0) return FR_INT_ERR; /* Invalid order */
+ mem_cpy(dirb + 1 * SZDIRE, dp->dir, SZDIRE);
+ if (MAXDIRB(dirb[XDIR_NumName]) > sz_ent) return FR_INT_ERR;
+
+ /* Load C1 entries */
+ i = 2 * SZDIRE; /* C1 offset to load */
+ do {
+ res = dir_next(dp, 0);
+ if (res == FR_NO_FILE) res = FR_INT_ERR; /* It cannot be */
+ if (res != FR_OK) return res;
+ res = move_window(dp->obj.fs, dp->sect);
+ if (res != FR_OK) return res;
+ if (dp->dir[XDIR_Type] != 0xC1) return FR_INT_ERR; /* Invalid order */
+ if (i < MAXDIRB(FF_MAX_LFN)) mem_cpy(dirb + i, dp->dir, SZDIRE);
+ } while ((i += SZDIRE) < sz_ent);
+
+ /* Sanity check (do it for only accessible object) */
+ if (i <= MAXDIRB(FF_MAX_LFN)) {
+ if (xdir_sum(dirb) != ld_word(dirb + XDIR_SetSum)) return FR_INT_ERR;
+ }
+ return FR_OK;
+}
+
+
+/*------------------------------------------------------------------*/
+/* exFAT: Initialize object allocation info with loaded entry block */
+/*------------------------------------------------------------------*/
+
+static void init_alloc_info (
+ FATFS* fs, /* Filesystem object */
+ FFOBJID* obj /* Object allocation information to be initialized */
+)
+{
+ obj->sclust = ld_dword(fs->dirbuf + XDIR_FstClus); /* Start cluster */
+ obj->objsize = ld_qword(fs->dirbuf + XDIR_FileSize); /* Size */
+ obj->stat = fs->dirbuf[XDIR_GenFlags] & 2; /* Allocation status */
+ obj->n_frag = 0; /* No last fragment info */
+}
+
+
+
+#if !FF_FS_READONLY || FF_FS_RPATH != 0
+/*------------------------------------------------*/
+/* exFAT: Load the object's directory entry block */
+/*------------------------------------------------*/
+
+static FRESULT load_obj_xdir (
+ DIR* dp, /* Blank directory object to be used to access containing directory */
+ const FFOBJID* obj /* Object with its containing directory information */
+)
+{
+ FRESULT res = FR_DISK_ERR;
+
+ /* Open object containing directory */
+ dp->obj.fs = obj->fs;
+ dp->obj.sclust = obj->c_scl;
+ dp->obj.stat = (BYTE)obj->c_size;
+ dp->obj.objsize = obj->c_size & 0xFFFFFF00;
+ dp->obj.n_frag = 0;
+ dp->blk_ofs = obj->c_ofs;
+
+ res = dir_sdi(dp, dp->blk_ofs); /* Goto object's entry block */
+ if (res == FR_OK) {
+ res = load_xdir(dp); /* Load the object's entry block */
+ }
+ return res;
+}
+#endif
+
+
+#if !FF_FS_READONLY
+/*----------------------------------------*/
+/* exFAT: Store the directory entry block */
+/*----------------------------------------*/
+
+static FRESULT store_xdir (
+ DIR* dp /* Pointer to the directory object */
+)
+{
+ FRESULT res = FR_DISK_ERR;
+ UINT nent;
+ BYTE* dirb = dp->obj.fs->dirbuf; /* Pointer to the directory entry block 85+C0+C1s */
+
+ /* Create set sum */
+ st_word(dirb + XDIR_SetSum, xdir_sum(dirb));
+ nent = dirb[XDIR_NumSec] + 1;
+
+ /* Store the directory entry block to the directory */
+ res = dir_sdi(dp, dp->blk_ofs);
+ while (res == FR_OK) {
+ res = move_window(dp->obj.fs, dp->sect);
+ if (res != FR_OK) break;
+ mem_cpy(dp->dir, dirb, SZDIRE);
+ dp->obj.fs->wflag = 1;
+ if (--nent == 0) break;
+ dirb += SZDIRE;
+ res = dir_next(dp, 0);
+ }
+ return (res == FR_OK || res == FR_DISK_ERR) ? res : FR_INT_ERR;
+}
+
+
+
+/*-------------------------------------------*/
+/* exFAT: Create a new directory entry block */
+/*-------------------------------------------*/
+
+static void create_xdir (
+ BYTE* dirb, /* Pointer to the directory entry block buffer */
+ const WCHAR* lfn /* Pointer to the object name */
+)
+{
+ UINT i;
+ BYTE nc1, nlen;
+ WCHAR wc;
+
+
+ /* Create 85,C0 entry */
+ mem_set(dirb, 0, 2 * SZDIRE);
+ dirb[0 * SZDIRE + XDIR_Type] = 0x85; /* 85 entry */
+ dirb[1 * SZDIRE + XDIR_Type] = 0xC0; /* C0 entry */
+
+ /* Create C1 entries */
+ i = SZDIRE * 2; /* Top of C1 entries */
+ nlen = nc1 = 0; wc = 1;
+ do {
+ dirb[i++] = 0xC1; dirb[i++] = 0; /* Entry type C1 */
+ do { /* Fill name field */
+ if (wc != 0 && (wc = lfn[nlen]) != 0) nlen++; /* Get a character if exist */
+ st_word(dirb + i, wc); /* Store it */
+ i += 2;
+ } while (i % SZDIRE != 0);
+ nc1++;
+ } while (lfn[nlen]); /* Fill next entry if any char follows */
+
+ dirb[XDIR_NumName] = nlen; /* Set name length */
+ dirb[XDIR_NumSec] = 1 + nc1; /* Set secondary count (C0 + C1s) */
+ st_word(dirb + XDIR_NameHash, xname_sum(lfn)); /* Set name hash */
+}
+
+#endif /* !FF_FS_READONLY */
+#endif /* FF_FS_EXFAT */
+
+
+
+#if FF_FS_MINIMIZE <= 1 || FF_FS_RPATH >= 2 || FF_USE_LABEL || FF_FS_EXFAT
+/*-----------------------------------------------------------------------*/
+/* Read an object from the directory */
+/*-----------------------------------------------------------------------*/
+
+#define dir_read_file(dp) dir_read(dp, 0)
+#define dir_read_label(dp) dir_read(dp, 1)
+
+static FRESULT dir_read (
+ DIR* dp, /* Pointer to the directory object */
+ int vol /* Filtered by 0:file/directory or 1:volume label */
+)
+{
+ FRESULT res = FR_NO_FILE;
+ FATFS *fs = dp->obj.fs;
+ BYTE a, c;
+#if FF_USE_LFN
+ BYTE ord = 0xFF, sum = 0xFF;
+#endif
+
+ while (dp->sect) {
+ res = move_window(fs, dp->sect);
+ if (res != FR_OK) break;
+ c = dp->dir[DIR_Name]; /* Test for the entry type */
+ if (c == 0) {
+ res = FR_NO_FILE; break; /* Reached to end of the directory */
+ }
+#if FF_FS_EXFAT
+ if (fs->fs_type == FS_EXFAT) { /* On the exFAT volume */
+ if (FF_USE_LABEL && vol) {
+ if (c == 0x83) break; /* Volume label entry? */
+ } else {
+ if (c == 0x85) { /* Start of the file entry block? */
+ dp->blk_ofs = dp->dptr; /* Get location of the block */
+ res = load_xdir(dp); /* Load the entry block */
+ if (res == FR_OK) {
+ dp->obj.attr = fs->dirbuf[XDIR_Attr] & AM_MASK; /* Get attribute */
+ }
+ break;
+ }
+ }
+ } else
+#endif
+ { /* On the FAT/FAT32 volume */
+ dp->obj.attr = a = dp->dir[DIR_Attr] & AM_MASK; /* Get attribute */
+#if FF_USE_LFN /* LFN configuration */
+ if (c == DDEM || c == '.' || (int)((a & ~AM_ARC) == AM_VOL) != vol) { /* An entry without valid data */
+ ord = 0xFF;
+ } else {
+ if (a == AM_LFN) { /* An LFN entry is found */
+ if (c & LLEF) { /* Is it start of an LFN sequence? */
+ sum = dp->dir[LDIR_Chksum];
+ c &= (BYTE)~LLEF; ord = c;
+ dp->blk_ofs = dp->dptr;
+ }
+ /* Check LFN validity and capture it */
+ ord = (c == ord && sum == dp->dir[LDIR_Chksum] && pick_lfn(fs->lfnbuf, dp->dir)) ? ord - 1 : 0xFF;
+ } else { /* An SFN entry is found */
+ if (ord != 0 || sum != sum_sfn(dp->dir)) { /* Is there a valid LFN? */
+ dp->blk_ofs = 0xFFFFFFFF; /* It has no LFN. */
+ }
+ break;
+ }
+ }
+#else /* Non LFN configuration */
+ if (c != DDEM && c != '.' && a != AM_LFN && (int)((a & ~AM_ARC) == AM_VOL) == vol) { /* Is it a valid entry? */
+ break;
+ }
+#endif
+ }
+ res = dir_next(dp, 0); /* Next entry */
+ if (res != FR_OK) break;
+ }
+
+ if (res != FR_OK) dp->sect = 0; /* Terminate the read operation on error or EOT */
+ return res;
+}
+
+#endif /* FF_FS_MINIMIZE <= 1 || FF_USE_LABEL || FF_FS_RPATH >= 2 */
+
+
+
+/*-----------------------------------------------------------------------*/
+/* Directory handling - Find an object in the directory */
+/*-----------------------------------------------------------------------*/
+
+static FRESULT dir_find ( /* FR_OK(0):succeeded, !=0:error */
+ DIR* dp /* Pointer to the directory object with the file name */
+)
+{
+ FRESULT res = FR_DISK_ERR;
+ FATFS *fs = dp->obj.fs;
+ BYTE c;
+#if FF_USE_LFN
+ BYTE a, ord, sum;
+#endif
+
+ res = dir_sdi(dp, 0); /* Rewind directory object */
+ if (res != FR_OK) return res;
+#if FF_FS_EXFAT
+ if (fs->fs_type == FS_EXFAT) { /* On the exFAT volume */
+ BYTE nc;
+ UINT di, ni;
+ WORD hash = xname_sum(fs->lfnbuf); /* Hash value of the name to find */
+
+ while ((res = dir_read_file(dp)) == FR_OK) { /* Read an item */
+#if FF_MAX_LFN < 255
+ if (fs->dirbuf[XDIR_NumName] > FF_MAX_LFN) continue; /* Skip comparison if inaccessible object name */
+#endif
+ if (ld_word(fs->dirbuf + XDIR_NameHash) != hash) continue; /* Skip comparison if hash mismatched */
+ for (nc = fs->dirbuf[XDIR_NumName], di = SZDIRE * 2, ni = 0; nc; nc--, di += 2, ni++) { /* Compare the name */
+ if ((di % SZDIRE) == 0) di += 2;
+ if (ff_wtoupper(ld_word(fs->dirbuf + di)) != ff_wtoupper(fs->lfnbuf[ni])) break;
+ }
+ if (nc == 0 && !fs->lfnbuf[ni]) break; /* Name matched? */
+ }
+ return res;
+ }
+#endif
+ /* On the FAT/FAT32 volume */
+#if FF_USE_LFN
+ ord = sum = 0xFF; dp->blk_ofs = 0xFFFFFFFF; /* Reset LFN sequence */
+#endif
+ do {
+ res = move_window(fs, dp->sect);
+ if (res != FR_OK) break;
+ c = dp->dir[DIR_Name];
+ if (c == 0) { res = FR_NO_FILE; break; } /* Reached to end of table */
+#if FF_USE_LFN /* LFN configuration */
+ dp->obj.attr = a = dp->dir[DIR_Attr] & AM_MASK;
+ if (c == DDEM || ((a & AM_VOL) && a != AM_LFN)) { /* An entry without valid data */
+ ord = 0xFF; dp->blk_ofs = 0xFFFFFFFF; /* Reset LFN sequence */
+ } else {
+ if (a == AM_LFN) { /* An LFN entry is found */
+ if (!(dp->fn[NSFLAG] & NS_NOLFN)) {
+ if (c & LLEF) { /* Is it start of LFN sequence? */
+ sum = dp->dir[LDIR_Chksum];
+ c &= (BYTE)~LLEF; ord = c; /* LFN start order */
+ dp->blk_ofs = dp->dptr; /* Start offset of LFN */
+ }
+ /* Check validity of the LFN entry and compare it with given name */
+ ord = (c == ord && sum == dp->dir[LDIR_Chksum] && cmp_lfn(fs->lfnbuf, dp->dir)) ? ord - 1 : 0xFF;
+ }
+ } else { /* An SFN entry is found */
+ if (ord == 0 && sum == sum_sfn(dp->dir)) break; /* LFN matched? */
+ if (!(dp->fn[NSFLAG] & NS_LOSS) && !mem_cmp(dp->dir, dp->fn, 11)) break; /* SFN matched? */
+ ord = 0xFF; dp->blk_ofs = 0xFFFFFFFF; /* Reset LFN sequence */
+ }
+ }
+#else /* Non LFN configuration */
+ dp->obj.attr = dp->dir[DIR_Attr] & AM_MASK;
+ if (!(dp->dir[DIR_Attr] & AM_VOL) && !mem_cmp(dp->dir, dp->fn, 11)) break; /* Is it a valid entry? */
+#endif
+ res = dir_next(dp, 0); /* Next entry */
+ } while (res == FR_OK);
+
+ return res;
+}
+
+
+
+
+#if !FF_FS_READONLY
+/*-----------------------------------------------------------------------*/
+/* Register an object to the directory */
+/*-----------------------------------------------------------------------*/
+
+static FRESULT dir_register ( /* FR_OK:succeeded, FR_DENIED:no free entry or too many SFN collision, FR_DISK_ERR:disk error */
+ DIR* dp /* Target directory with object name to be created */
+)
+{
+ FRESULT res = FR_DISK_ERR;
+ FATFS *fs = dp->obj.fs;
+#if FF_USE_LFN /* LFN configuration */
+ UINT n, nlen, nent;
+ BYTE sn[12], sum;
+
+
+ if (dp->fn[NSFLAG] & (NS_DOT | NS_NONAME)) return FR_INVALID_NAME; /* Check name validity */
+ for (nlen = 0; fs->lfnbuf[nlen]; nlen++) ; /* Get lfn length */
+
+#if FF_FS_EXFAT
+ if (fs->fs_type == FS_EXFAT) { /* On the exFAT volume */
+ nent = (nlen + 14) / 15 + 2; /* Number of entries to allocate (85+C0+C1s) */
+ res = dir_alloc(dp, nent); /* Allocate entries */
+ if (res != FR_OK) return res;
+ dp->blk_ofs = dp->dptr - SZDIRE * (nent - 1); /* Set the allocated entry block offset */
+
+ if (dp->obj.stat & 4) { /* Has the directory been stretched? */
+ dp->obj.stat &= ~4;
+ res = fill_first_frag(&dp->obj); /* Fill the first fragment on the FAT if needed */
+ if (res != FR_OK) return res;
+ res = fill_last_frag(&dp->obj, dp->clust, 0xFFFFFFFF); /* Fill the last fragment on the FAT if needed */
+ if (res != FR_OK) return res;
+ if (dp->obj.sclust != 0) { /* Is it a sub directory? */
+ DIR dj;
+
+ res = load_obj_xdir(&dj, &dp->obj); /* Load the object status */
+ if (res != FR_OK) return res;
+ dp->obj.objsize += (DWORD)fs->csize * SS(fs); /* Increase the directory size by cluster size */
+ st_qword(fs->dirbuf + XDIR_FileSize, dp->obj.objsize); /* Update the allocation status */
+ st_qword(fs->dirbuf + XDIR_ValidFileSize, dp->obj.objsize);
+ fs->dirbuf[XDIR_GenFlags] = dp->obj.stat | 1;
+ res = store_xdir(&dj); /* Store the object status */
+ if (res != FR_OK) return res;
+ }
+ }
+
+ create_xdir(fs->dirbuf, fs->lfnbuf); /* Create on-memory directory block to be written later */
+ return FR_OK;
+ }
+#endif
+ /* On the FAT/FAT32 volume */
+ mem_cpy(sn, dp->fn, 12);
+ if (sn[NSFLAG] & NS_LOSS) { /* When LFN is out of 8.3 format, generate a numbered name */
+ dp->fn[NSFLAG] = NS_NOLFN; /* Find only SFN */
+ for (n = 1; n < 100; n++) {
+ gen_numname(dp->fn, sn, fs->lfnbuf, n); /* Generate a numbered name */
+ res = dir_find(dp); /* Check if the name collides with existing SFN */
+ if (res != FR_OK) break;
+ }
+ if (n == 100) return FR_DENIED; /* Abort if too many collisions */
+ if (res != FR_NO_FILE) return res; /* Abort if the result is other than 'not collided' */
+ dp->fn[NSFLAG] = sn[NSFLAG];
+ }
+
+ /* Create an SFN with/without LFNs. */
+ nent = (sn[NSFLAG] & NS_LFN) ? (nlen + 12) / 13 + 1 : 1; /* Number of entries to allocate */
+ res = dir_alloc(dp, nent); /* Allocate entries */
+ if (res == FR_OK && --nent) { /* Set LFN entry if needed */
+ res = dir_sdi(dp, dp->dptr - nent * SZDIRE);
+ if (res == FR_OK) {
+ sum = sum_sfn(dp->fn); /* Checksum value of the SFN tied to the LFN */
+ do { /* Store LFN entries in bottom first */
+ res = move_window(fs, dp->sect);
+ if (res != FR_OK) break;
+ put_lfn(fs->lfnbuf, dp->dir, (BYTE)nent, sum);
+ fs->wflag = 1;
+ res = dir_next(dp, 0); /* Next entry */
+ } while (res == FR_OK && --nent);
+ }
+ }
+
+#else /* Non LFN configuration */
+ res = dir_alloc(dp, 1); /* Allocate an entry for SFN */
+
+#endif
+
+ /* Set SFN entry */
+ if (res == FR_OK) {
+ res = move_window(fs, dp->sect);
+ if (res == FR_OK) {
+ mem_set(dp->dir, 0, SZDIRE); /* Clean the entry */
+ mem_cpy(dp->dir + DIR_Name, dp->fn, 11); /* Put SFN */
+#if FF_USE_LFN
+ dp->dir[DIR_NTres] = dp->fn[NSFLAG] & (NS_BODY | NS_EXT); /* Put NT flag */
+#endif
+ fs->wflag = 1;
+ }
+ }
+
+ return res;
+}
+
+#endif /* !FF_FS_READONLY */
+
+
+
+#if !FF_FS_READONLY && FF_FS_MINIMIZE == 0
+/*-----------------------------------------------------------------------*/
+/* Remove an object from the directory */
+/*-----------------------------------------------------------------------*/
+
+static FRESULT dir_remove ( /* FR_OK:Succeeded, FR_DISK_ERR:A disk error */
+ DIR* dp /* Directory object pointing the entry to be removed */
+)
+{
+ FRESULT res = FR_DISK_ERR;
+ FATFS *fs = dp->obj.fs;
+#if FF_USE_LFN /* LFN configuration */
+ DWORD last = dp->dptr;
+
+ res = (dp->blk_ofs == 0xFFFFFFFF) ? FR_OK : dir_sdi(dp, dp->blk_ofs); /* Goto top of the entry block if LFN is exist */
+ if (res == FR_OK) {
+ do {
+ res = move_window(fs, dp->sect);
+ if (res != FR_OK) break;
+ if (FF_FS_EXFAT && fs->fs_type == FS_EXFAT) { /* On the exFAT volume */
+ dp->dir[XDIR_Type] &= 0x7F; /* Clear the entry InUse flag. */
+ } else { /* On the FAT/FAT32 volume */
+ dp->dir[DIR_Name] = DDEM; /* Mark the entry 'deleted'. */
+ }
+ fs->wflag = 1;
+ if (dp->dptr >= last) break; /* If reached last entry then all entries of the object has been deleted. */
+ res = dir_next(dp, 0); /* Next entry */
+ } while (res == FR_OK);
+ if (res == FR_NO_FILE) res = FR_INT_ERR;
+ }
+#else /* Non LFN configuration */
+
+ res = move_window(fs, dp->sect);
+ if (res == FR_OK) {
+ dp->dir[DIR_Name] = DDEM; /* Mark the entry 'deleted'.*/
+ fs->wflag = 1;
+ }
+#endif
+
+ return res;
+}
+
+#endif /* !FF_FS_READONLY && FF_FS_MINIMIZE == 0 */
+
+
+
+#if FF_FS_MINIMIZE <= 1 || FF_FS_RPATH >= 2
+/*-----------------------------------------------------------------------*/
+/* Get file information from directory entry */
+/*-----------------------------------------------------------------------*/
+
+static void get_fileinfo (
+ DIR* dp, /* Pointer to the directory object */
+ FILINFO* fno /* Pointer to the file information to be filled */
+)
+{
+ UINT si, di;
+#if FF_USE_LFN
+ WCHAR wc, hs;
+ FATFS *fs = dp->obj.fs;
+#else
+ TCHAR c;
+#endif
+
+
+ fno->fname[0] = 0; /* Invaidate file info */
+ if (dp->sect == 0) return; /* Exit if read pointer has reached end of directory */
+
+#if FF_USE_LFN /* LFN configuration */
+#if FF_FS_EXFAT
+ if (fs->fs_type == FS_EXFAT) { /* On the exFAT volume */
+ get_xfileinfo(fs->dirbuf, fno);
+ return;
+ } else
+#endif
+ { /* On the FAT/FAT32 volume */
+ if (dp->blk_ofs != 0xFFFFFFFF) { /* Get LFN if available */
+ si = di = hs = 0;
+ while (fs->lfnbuf[si] != 0) {
+ wc = fs->lfnbuf[si++]; /* Get an LFN character (UTF-16) */
+ if (hs == 0 && IsSurrogate(wc)) { /* Is it a surrogate? */
+ hs = wc; continue; /* Get low surrogate */
+ }
+ wc = put_utf((DWORD)hs << 16 | wc, &fno->fname[di], FF_LFN_BUF - di); /* Store it in UTF-16 or UTF-8 encoding */
+ if (wc == 0) { di = 0; break; } /* Invalid char or buffer overflow? */
+ di += wc;
+ hs = 0;
+ }
+ if (hs != 0) di = 0; /* Broken surrogate pair? */
+ fno->fname[di] = 0; /* Terminate the LFN (null string means LFN is invalid) */
+ }
+ }
+
+ si = di = 0;
+ while (si < 11) { /* Get SFN from SFN entry */
+ wc = dp->dir[si++]; /* Get a char */
+ if (wc == ' ') continue; /* Skip padding spaces */
+ if (wc == RDDEM) wc = DDEM; /* Restore replaced DDEM character */
+ if (si == 9 && di < FF_SFN_BUF) fno->altname[di++] = '.'; /* Insert a . if extension is exist */
+#if FF_LFN_UNICODE >= 1 /* Unicode output */
+ if (dbc_1st((BYTE)wc) && si != 8 && si != 11 && dbc_2nd(dp->dir[si])) { /* Make a DBC if needed */
+ wc = wc << 8 | dp->dir[si++];
+ }
+ wc = ff_oem2uni(wc, CODEPAGE); /* ANSI/OEM -> Unicode */
+ if (wc == 0) { di = 0; break; } /* Wrong char in the current code page? */
+ wc = put_utf(wc, &fno->altname[di], FF_SFN_BUF - di); /* Store it in Unicode */
+ if (wc == 0) { di = 0; break; } /* Buffer overflow? */
+ di += wc;
+#else /* ANSI/OEM output */
+ fno->altname[di++] = (TCHAR)wc; /* Store it without any conversion */
+#endif
+ }
+ fno->altname[di] = 0; /* Terminate the SFN (null string means SFN is invalid) */
+
+ if (fno->fname[0] == 0) { /* If LFN is invalid, altname[] needs to be copied to fname[] */
+ if (di == 0) { /* If LFN and SFN both are invalid, this object is inaccessible */
+ fno->fname[di++] = '?';
+ } else {
+ for (si = di = 0; fno->altname[si]; si++, di++) { /* Copy altname[] to fname[] with case information */
+ wc = (WCHAR)fno->altname[si];
+ if (IsUpper(wc) && (dp->dir[DIR_NTres] & ((si >= 9) ? NS_EXT : NS_BODY))) wc += 0x20;
+ fno->fname[di] = (TCHAR)wc;
+ }
+ }
+ fno->fname[di] = 0; /* Terminate the LFN */
+ if (!dp->dir[DIR_NTres]) fno->altname[0] = 0; /* Altname is not needed if neither LFN nor case info is exist. */
+ }
+
+#else /* Non-LFN configuration */
+ si = di = 0;
+ while (si < 11) { /* Copy name body and extension */
+ c = (TCHAR)dp->dir[si++];
+ if (c == ' ') continue; /* Skip padding spaces */
+ if (c == RDDEM) c = DDEM; /* Restore replaced DDEM character */
+ if (si == 9) fno->fname[di++] = '.';/* Insert a . if extension is exist */
+ fno->fname[di++] = c;
+ }
+ fno->fname[di] = 0;
+#endif
+
+ fno->fattrib = dp->dir[DIR_Attr]; /* Attribute */
+ fno->fsize = ld_dword(dp->dir + DIR_FileSize); /* Size */
+ fno->ftime = ld_word(dp->dir + DIR_ModTime + 0); /* Time */
+ fno->fdate = ld_word(dp->dir + DIR_ModTime + 2); /* Date */
+}
+
+#endif /* FF_FS_MINIMIZE <= 1 || FF_FS_RPATH >= 2 */
+
+
+
+#if FF_USE_FIND && FF_FS_MINIMIZE <= 1
+/*-----------------------------------------------------------------------*/
+/* Pattern matching */
+/*-----------------------------------------------------------------------*/
+
+static DWORD get_achar ( /* Get a character and advances ptr */
+ const TCHAR** ptr /* Pointer to pointer to the ANSI/OEM or Unicode string */
+)
+{
+ DWORD chr;
+
+
+#if FF_USE_LFN && FF_LFN_UNICODE >= 1 /* Unicode input */
+ chr = tchar2uni(ptr);
+ if (chr == 0xFFFFFFFF) chr = 0; /* Wrong UTF encoding is recognized as end of the string */
+ chr = ff_wtoupper(chr);
+
+#else /* ANSI/OEM input */
+ chr = (BYTE)*(*ptr)++; /* Get a byte */
+ if (IsLower(chr)) chr -= 0x20; /* To upper ASCII char */
+#if FF_CODE_PAGE == 0
+ if (ExCvt && chr >= 0x80) chr = ExCvt[chr - 0x80]; /* To upper SBCS extended char */
+#elif FF_CODE_PAGE < 900
+ if (chr >= 0x80) chr = ExCvt[chr - 0x80]; /* To upper SBCS extended char */
+#endif
+#if FF_CODE_PAGE == 0 || FF_CODE_PAGE >= 900
+ if (dbc_1st((BYTE)chr)) { /* Get DBC 2nd byte if needed */
+ chr = dbc_2nd((BYTE)**ptr) ? chr << 8 | (BYTE)*(*ptr)++ : 0;
+ }
+#endif
+
+#endif
+ return chr;
+}
+
+
+static int pattern_matching ( /* 0:not matched, 1:matched */
+ const TCHAR* pat, /* Matching pattern */
+ const TCHAR* nam, /* String to be tested */
+ int skip, /* Number of pre-skip chars (number of ?s) */
+ int inf /* Infinite search (* specified) */
+)
+{
+ const TCHAR *pp, *np;
+ DWORD pc, nc;
+ int nm, nx;
+
+
+ while (skip--) { /* Pre-skip name chars */
+ if (!get_achar(&nam)) return 0; /* Branch mismatched if less name chars */
+ }
+ if (*pat == 0 && inf) return 1; /* (short circuit) */
+
+ do {
+ pp = pat; np = nam; /* Top of pattern and name to match */
+ for (;;) {
+ if (*pp == '?' || *pp == '*') { /* Wildcard? */
+ nm = nx = 0;
+ do { /* Analyze the wildcard block */
+ if (*pp++ == '?') nm++; else nx = 1;
+ } while (*pp == '?' || *pp == '*');
+ if (pattern_matching(pp, np, nm, nx)) return 1; /* Test new branch (recurs up to number of wildcard blocks in the pattern) */
+ nc = *np; break; /* Branch mismatched */
+ }
+ pc = get_achar(&pp); /* Get a pattern char */
+ nc = get_achar(&np); /* Get a name char */
+ if (pc != nc) break; /* Branch mismatched? */
+ if (pc == 0) return 1; /* Branch matched? (matched at end of both strings) */
+ }
+ get_achar(&nam); /* nam++ */
+ } while (inf && nc); /* Retry until end of name if infinite search is specified */
+
+ return 0;
+}
+
+#endif /* FF_USE_FIND && FF_FS_MINIMIZE <= 1 */
+
+
+
+/*-----------------------------------------------------------------------*/
+/* Pick a top segment and create the object name in directory form */
+/*-----------------------------------------------------------------------*/
+
+static FRESULT create_name ( /* FR_OK: successful, FR_INVALID_NAME: could not create */
+ DIR* dp, /* Pointer to the directory object */
+ const TCHAR** path /* Pointer to pointer to the segment in the path string */
+)
+{
+#if FF_USE_LFN /* LFN configuration */
+ BYTE b, cf;
+ WCHAR wc, *lfn;
+ DWORD uc;
+ UINT i, ni, si, di;
+ const TCHAR *p;
+
+
+ /* Create LFN into LFN working buffer */
+ p = *path; lfn = dp->obj.fs->lfnbuf; di = 0;
+ for (;;) {
+ uc = tchar2uni(&p); /* Get a character */
+ if (uc == 0xFFFFFFFF) return FR_INVALID_NAME; /* Invalid code or UTF decode error */
+ if (uc >= 0x10000) lfn[di++] = (WCHAR)(uc >> 16); /* Store high surrogate if needed */
+ wc = (WCHAR)uc;
+ if (wc < ' ' || wc == '/' || wc == '\\') break; /* Break if end of the path or a separator is found */
+ if (wc < 0x80 && chk_chr("\"*:<>\?|\x7F", wc)) return FR_INVALID_NAME; /* Reject illegal characters for LFN */
+ if (di >= FF_MAX_LFN) return FR_INVALID_NAME; /* Reject too long name */
+ lfn[di++] = wc; /* Store the Unicode character */
+ }
+ while (*p == '/' || *p == '\\') p++; /* Skip duplicated separators if exist */
+ *path = p; /* Return pointer to the next segment */
+ cf = (wc < ' ') ? NS_LAST : 0; /* Set last segment flag if end of the path */
+
+#if FF_FS_RPATH != 0
+ if ((di == 1 && lfn[di - 1] == '.') ||
+ (di == 2 && lfn[di - 1] == '.' && lfn[di - 2] == '.')) { /* Is this segment a dot name? */
+ lfn[di] = 0;
+ for (i = 0; i < 11; i++) { /* Create dot name for SFN entry */
+ dp->fn[i] = (i < di) ? '.' : ' ';
+ }
+ dp->fn[i] = cf | NS_DOT; /* This is a dot entry */
+ return FR_OK;
+ }
+#endif
+ while (di) { /* Snip off trailing spaces and dots if exist */
+ wc = lfn[di - 1];
+ if (wc != ' ' && wc != '.') break;
+ di--;
+ }
+ lfn[di] = 0; /* LFN is created into the working buffer */
+ if (di == 0) return FR_INVALID_NAME; /* Reject null name */
+
+ /* Create SFN in directory form */
+ for (si = 0; lfn[si] == ' '; si++) ; /* Remove leading spaces */
+ if (si > 0 || lfn[si] == '.') cf |= NS_LOSS | NS_LFN; /* Is there any leading space or dot? */
+ while (di > 0 && lfn[di - 1] != '.') di--; /* Find last dot (di<=si: no extension) */
+
+ mem_set(dp->fn, ' ', 11);
+ i = b = 0; ni = 8;
+ for (;;) {
+ wc = lfn[si++]; /* Get an LFN character */
+ if (wc == 0) break; /* Break on end of the LFN */
+ if (wc == ' ' || (wc == '.' && si != di)) { /* Remove embedded spaces and dots */
+ cf |= NS_LOSS | NS_LFN;
+ continue;
+ }
+
+ if (i >= ni || si == di) { /* End of field? */
+ if (ni == 11) { /* Name extension overflow? */
+ cf |= NS_LOSS | NS_LFN;
+ break;
+ }
+ if (si != di) cf |= NS_LOSS | NS_LFN; /* Name body overflow? */
+ if (si > di) break; /* No name extension? */
+ si = di; i = 8; ni = 11; b <<= 2; /* Enter name extension */
+ continue;
+ }
+
+ if (wc >= 0x80) { /* Is this a non-ASCII character? */
+ cf |= NS_LFN; /* LFN entry needs to be created */
+#if FF_CODE_PAGE == 0
+ if (ExCvt) { /* At SBCS */
+ wc = ff_uni2oem(wc, CODEPAGE); /* Unicode ==> ANSI/OEM code */
+ if (wc & 0x80) wc = ExCvt[wc & 0x7F]; /* Convert extended character to upper (SBCS) */
+ } else { /* At DBCS */
+ wc = ff_uni2oem(ff_wtoupper(wc), CODEPAGE); /* Unicode ==> Upper convert ==> ANSI/OEM code */
+ }
+#elif FF_CODE_PAGE < 900 /* SBCS cfg */
+ wc = ff_uni2oem(wc, CODEPAGE); /* Unicode ==> ANSI/OEM code */
+ if (wc & 0x80) wc = ExCvt[wc & 0x7F]; /* Convert extended character to upper (SBCS) */
+#else /* DBCS cfg */
+ wc = ff_uni2oem(ff_wtoupper(wc), CODEPAGE); /* Unicode ==> Upper convert ==> ANSI/OEM code */
+#endif
+ }
+
+ if (wc >= 0x100) { /* Is this a DBC? */
+ if (i >= ni - 1) { /* Field overflow? */
+ cf |= NS_LOSS | NS_LFN;
+ i = ni; continue; /* Next field */
+ }
+ dp->fn[i++] = (BYTE)(wc >> 8); /* Put 1st byte */
+ } else { /* SBC */
+ if (wc == 0 || chk_chr("+,;=[]", wc)) { /* Replace illegal characters for SFN if needed */
+ wc = '_'; cf |= NS_LOSS | NS_LFN;/* Lossy conversion */
+ } else {
+ if (IsUpper(wc)) { /* ASCII upper case? */
+ b |= 2;
+ }
+ if (IsLower(wc)) { /* ASCII lower case? */
+ b |= 1; wc -= 0x20;
+ }
+ }
+ }
+ dp->fn[i++] = (BYTE)wc;
+ }
+
+ if (dp->fn[0] == DDEM) dp->fn[0] = RDDEM; /* If the first character collides with DDEM, replace it with RDDEM */
+
+ if (ni == 8) b <<= 2; /* Shift capital flags if no extension */
+ if ((b & 0x0C) == 0x0C || (b & 0x03) == 0x03) cf |= NS_LFN; /* LFN entry needs to be created if composite capitals */
+ if (!(cf & NS_LFN)) { /* When LFN is in 8.3 format without extended character, NT flags are created */
+ if (b & 0x01) cf |= NS_EXT; /* NT flag (Extension has small capital letters only) */
+ if (b & 0x04) cf |= NS_BODY; /* NT flag (Body has small capital letters only) */
+ }
+
+ dp->fn[NSFLAG] = cf; /* SFN is created into dp->fn[] */
+
+ return FR_OK;
+
+
+#else /* FF_USE_LFN : Non-LFN configuration */
+ BYTE c, d, *sfn;
+ UINT ni, si, i;
+ const char *p;
+
+ /* Create file name in directory form */
+ p = *path; sfn = dp->fn;
+ mem_set(sfn, ' ', 11);
+ si = i = 0; ni = 8;
+#if FF_FS_RPATH != 0
+ if (p[si] == '.') { /* Is this a dot entry? */
+ for (;;) {
+ c = (BYTE)p[si++];
+ if (c != '.' || si >= 3) break;
+ sfn[i++] = c;
+ }
+ if (c != '/' && c != '\\' && c > ' ') return FR_INVALID_NAME;
+ *path = p + si; /* Return pointer to the next segment */
+ sfn[NSFLAG] = (c <= ' ') ? NS_LAST | NS_DOT : NS_DOT; /* Set last segment flag if end of the path */
+ return FR_OK;
+ }
+#endif
+ for (;;) {
+ c = (BYTE)p[si++]; /* Get a byte */
+ if (c <= ' ') break; /* Break if end of the path name */
+ if (c == '/' || c == '\\') { /* Break if a separator is found */
+ while (p[si] == '/' || p[si] == '\\') si++; /* Skip duplicated separator if exist */
+ break;
+ }
+ if (c == '.' || i >= ni) { /* End of body or field overflow? */
+ if (ni == 11 || c != '.') return FR_INVALID_NAME; /* Field overflow or invalid dot? */
+ i = 8; ni = 11; /* Enter file extension field */
+ continue;
+ }
+#if FF_CODE_PAGE == 0
+ if (ExCvt && c >= 0x80) { /* Is SBC extended character? */
+ c = ExCvt[c & 0x7F]; /* To upper SBC extended character */
+ }
+#elif FF_CODE_PAGE < 900
+ if (c >= 0x80) { /* Is SBC extended character? */
+ c = ExCvt[c & 0x7F]; /* To upper SBC extended character */
+ }
+#endif
+ if (dbc_1st(c)) { /* Check if it is a DBC 1st byte */
+ d = (BYTE)p[si++]; /* Get 2nd byte */
+ if (!dbc_2nd(d) || i >= ni - 1) return FR_INVALID_NAME; /* Reject invalid DBC */
+ sfn[i++] = c;
+ sfn[i++] = d;
+ } else { /* SBC */
+ if (chk_chr("\"*+,:;<=>\?[]|\x7F", c)) return FR_INVALID_NAME; /* Reject illegal chrs for SFN */
+ if (IsLower(c)) c -= 0x20; /* To upper */
+ sfn[i++] = c;
+ }
+ }
+ *path = p + si; /* Return pointer to the next segment */
+ if (i == 0) return FR_INVALID_NAME; /* Reject nul string */
+
+ if (sfn[0] == DDEM) sfn[0] = RDDEM; /* If the first character collides with DDEM, replace it with RDDEM */
+ sfn[NSFLAG] = (c <= ' ') ? NS_LAST : 0; /* Set last segment flag if end of the path */
+
+ return FR_OK;
+#endif /* FF_USE_LFN */
+}
+
+
+
+
+/*-----------------------------------------------------------------------*/
+/* Follow a file path */
+/*-----------------------------------------------------------------------*/
+
+static FRESULT follow_path ( /* FR_OK(0): successful, !=0: error code */
+ DIR* dp, /* Directory object to return last directory and found object */
+ const TCHAR* path /* Full-path string to find a file or directory */
+)
+{
+ FRESULT res = FR_DISK_ERR;
+ BYTE ns;
+ FATFS *fs = dp->obj.fs;
+
+
+#if FF_FS_RPATH != 0
+ if (*path != '/' && *path != '\\') { /* Without heading separator */
+ dp->obj.sclust = fs->cdir; /* Start from current directory */
+ } else
+#endif
+ { /* With heading separator */
+ while (*path == '/' || *path == '\\') path++; /* Strip heading separator */
+ dp->obj.sclust = 0; /* Start from root directory */
+ }
+#if FF_FS_EXFAT
+ dp->obj.n_frag = 0; /* Invalidate last fragment counter of the object */
+#if FF_FS_RPATH != 0
+ if (fs->fs_type == FS_EXFAT && dp->obj.sclust) { /* exFAT: Retrieve the sub-directory's status */
+ DIR dj;
+
+ dp->obj.c_scl = fs->cdc_scl;
+ dp->obj.c_size = fs->cdc_size;
+ dp->obj.c_ofs = fs->cdc_ofs;
+ res = load_obj_xdir(&dj, &dp->obj);
+ if (res != FR_OK) return res;
+ dp->obj.objsize = ld_dword(fs->dirbuf + XDIR_FileSize);
+ dp->obj.stat = fs->dirbuf[XDIR_GenFlags] & 2;
+ }
+#endif
+#endif
+
+ if ((UINT)*path < ' ') { /* Null path name is the origin directory itself */
+ dp->fn[NSFLAG] = NS_NONAME;
+ res = dir_sdi(dp, 0);
+
+ } else { /* Follow path */
+ for (;;) {
+ res = create_name(dp, &path); /* Get a segment name of the path */
+ if (res != FR_OK) break;
+ res = dir_find(dp); /* Find an object with the segment name */
+ ns = dp->fn[NSFLAG];
+ if (res != FR_OK) { /* Failed to find the object */
+ if (res == FR_NO_FILE) { /* Object is not found */
+ if (FF_FS_RPATH && (ns & NS_DOT)) { /* If dot entry is not exist, stay there */
+ if (!(ns & NS_LAST)) continue; /* Continue to follow if not last segment */
+ dp->fn[NSFLAG] = NS_NONAME;
+ res = FR_OK;
+ } else { /* Could not find the object */
+ if (!(ns & NS_LAST)) res = FR_NO_PATH; /* Adjust error code if not last segment */
+ }
+ }
+ break;
+ }
+ if (ns & NS_LAST) break; /* Last segment matched. Function completed. */
+ /* Get into the sub-directory */
+ if (!(dp->obj.attr & AM_DIR)) { /* It is not a sub-directory and cannot follow */
+ res = FR_NO_PATH; break;
+ }
+#if FF_FS_EXFAT
+ if (fs->fs_type == FS_EXFAT) { /* Save containing directory information for next dir */
+ dp->obj.c_scl = dp->obj.sclust;
+ dp->obj.c_size = ((DWORD)dp->obj.objsize & 0xFFFFFF00) | dp->obj.stat;
+ dp->obj.c_ofs = dp->blk_ofs;
+ init_alloc_info(fs, &dp->obj); /* Open next directory */
+ } else
+#endif
+ {
+ dp->obj.sclust = ld_clust(fs, fs->win + dp->dptr % SS(fs)); /* Open next directory */
+ }
+ }
+ }
+
+ return res;
+}
+
+
+
+
+/*-----------------------------------------------------------------------*/
+/* Get logical drive number from path name */
+/*-----------------------------------------------------------------------*/
+
+static int get_ldnumber ( /* Returns logical drive number (-1:invalid drive number or null pointer) */
+ const TCHAR** path /* Pointer to pointer to the path name */
+)
+{
+ const TCHAR *tp, *tt;
+ TCHAR tc;
+ int i, vol = -1;
+#if FF_STR_VOLUME_ID /* Find string volume ID */
+ const char *sp;
+ char c;
+#endif
+
+ tt = tp = *path;
+ if (!tp) return vol; /* Invalid path name? */
+ do tc = *tt++; while ((UINT)tc >= (FF_USE_LFN ? ' ' : '!') && tc != ':'); /* Find a colon in the path */
+
+ if (tc == ':') { /* DOS/Windows style volume ID? */
+ i = FF_VOLUMES;
+ if (IsDigit(*tp) && tp + 2 == tt) { /* Is there a numeric volume ID + colon? */
+ i = (int)*tp - '0'; /* Get the LD number */
+ }
+#if FF_STR_VOLUME_ID == 1 /* Arbitrary string is enabled */
+ else {
+ i = 0;
+ do {
+ sp = VolumeStr[i]; tp = *path; /* This string volume ID and path name */
+ do { /* Compare the volume ID with path name */
+ c = *sp++; tc = *tp++;
+ if (IsLower(c)) c -= 0x20;
+ if (IsLower(tc)) tc -= 0x20;
+ } while (c && (TCHAR)c == tc);
+ } while ((c || tp != tt) && ++i < FF_VOLUMES); /* Repeat for each id until pattern match */
+ }
+#endif
+ if ((UINT)i < FF_VOLUMES) { /* If a volume ID is found, get the drive number and strip it */
+ vol = i; /* Drive number */
+ *path = tt; /* Snip the drive prefix off */
+ }
+ return vol;
+ }
+#if FF_STR_VOLUME_ID == 2 /* Unix style volume ID is enabled */
+ if (*tp == '/') {
+ i = 0;
+ do {
+ sp = VolumeStr[i]; tp = *path; /* This string volume ID and path name */
+ do { /* Compare the volume ID with path name */
+ c = *sp++; tc = *(++tp);
+ if (IsLower(c)) c -= 0x20;
+ if (IsLower(tc)) tc -= 0x20;
+ } while (c && (TCHAR)c == tc);
+ } while ((c || (tc != '/' && (UINT)tc >= (FF_USE_LFN ? ' ' : '!'))) && ++i < FF_VOLUMES); /* Repeat for each ID until pattern match */
+ if (i < FF_VOLUMES) { /* If a volume ID is found, get the drive number and strip it */
+ vol = i; /* Drive number */
+ *path = tp; /* Snip the drive prefix off */
+ return vol;
+ }
+ }
+#endif
+ /* No drive prefix is found */
+#if FF_FS_RPATH != 0
+ vol = CurrVol; /* Default drive is current drive */
+#else
+ vol = 0; /* Default drive is 0 */
+#endif
+ return vol; /* Return the default drive */
+}
+
+
+
+
+/*-----------------------------------------------------------------------*/
+/* Load a sector and check if it is an FAT VBR */
+/*-----------------------------------------------------------------------*/
+
+static BYTE check_fs ( /* 0:FAT, 1:exFAT, 2:Valid BS but not FAT, 3:Not a BS, 4:Disk error */
+ FATFS* fs, /* Filesystem object */
+ DWORD sect /* Sector# (lba) to load and check if it is an FAT-VBR or not */
+)
+{
+ fs->wflag = 0; fs->winsect = 0xFFFFFFFF; /* Invaidate window */
+ if (move_window(fs, sect) != FR_OK) return 4; /* Load boot record */
+
+ if (ld_word(fs->win + BS_55AA) != 0xAA55) return 3; /* Check boot record signature (always here regardless of the sector size) */
+
+#if FF_FS_EXFAT
+ if (!mem_cmp(fs->win + BS_JmpBoot, "\xEB\x76\x90" "EXFAT ", 11)) return 1; /* Check if exFAT VBR */
+#endif
+ if (fs->win[BS_JmpBoot] == 0xE9 || fs->win[BS_JmpBoot] == 0xEB || fs->win[BS_JmpBoot] == 0xE8) { /* Valid JumpBoot code? */
+ if (!mem_cmp(fs->win + BS_FilSysType, "FAT", 3)) return 0; /* Is it an FAT VBR? */
+ if (!mem_cmp(fs->win + BS_FilSysType32, "FAT32", 5)) return 0; /* Is it an FAT32 VBR? */
+ }
+ return 2; /* Valid BS but not FAT */
+}
+
+
+
+
+/*-----------------------------------------------------------------------*/
+/* Determine logical drive number and mount the volume if needed */
+/*-----------------------------------------------------------------------*/
+
+static FRESULT find_volume ( /* FR_OK(0): successful, !=0: an error occurred */
+ const TCHAR** path, /* Pointer to pointer to the path name (drive number) */
+ FATFS** rfs, /* Pointer to pointer to the found filesystem object */
+ BYTE mode /* !=0: Check write protection for write access */
+)
+{
+ BYTE fmt, *pt;
+ int vol;
+ DSTATUS stat;
+ DWORD bsect, fasize, tsect, sysect, nclst, szbfat, br[4];
+ WORD nrsv;
+ FATFS *fs;
+ UINT i;
+
+
+ /* Get logical drive number */
+ *rfs = 0;
+ vol = get_ldnumber(path);
+ if (vol < 0) return FR_INVALID_DRIVE;
+
+ /* Check if the filesystem object is valid or not */
+ fs = FatFs[vol]; /* Get pointer to the filesystem object */
+ if (!fs) return FR_NOT_ENABLED; /* Is the filesystem object available? */
+#if FF_FS_REENTRANT
+ if (!lock_fs(fs)) return FR_TIMEOUT; /* Lock the volume */
+#endif
+ *rfs = fs; /* Return pointer to the filesystem object */
+
+ mode &= (BYTE)~FA_READ; /* Desired access mode, write access or not */
+ if (fs->fs_type != 0) { /* If the volume has been mounted */
+ stat = disk_status(fs->pdrv);
+ if (!(stat & STA_NOINIT)) { /* and the physical drive is kept initialized */
+ if (!FF_FS_READONLY && mode && (stat & STA_PROTECT)) { /* Check write protection if needed */
+ return FR_WRITE_PROTECTED;
+ }
+ return FR_OK; /* The filesystem object is valid */
+ }
+ }
+
+ /* The filesystem object is not valid. */
+ /* Following code attempts to mount the volume. (analyze BPB and initialize the filesystem object) */
+
+ fs->fs_type = 0; /* Clear the filesystem object */
+ fs->pdrv = LD2PD(vol); /* Bind the logical drive and a physical drive */
+ stat = disk_initialize(fs->pdrv); /* Initialize the physical drive */
+ if (stat & STA_NOINIT) { /* Check if the initialization succeeded */
+ return FR_NOT_READY; /* Failed to initialize due to no medium or hard error */
+ }
+ if (!FF_FS_READONLY && mode && (stat & STA_PROTECT)) { /* Check disk write protection if needed */
+ return FR_WRITE_PROTECTED;
+ }
+#if FF_MAX_SS != FF_MIN_SS /* Get sector size (multiple sector size cfg only) */
+ if (disk_ioctl(fs->pdrv, GET_SECTOR_SIZE, &SS(fs)) != RES_OK) return FR_DISK_ERR;
+ if (SS(fs) > FF_MAX_SS || SS(fs) < FF_MIN_SS || (SS(fs) & (SS(fs) - 1))) return FR_DISK_ERR;
+#endif
+
+ /* Find an FAT partition on the drive. Supports only generic partitioning rules, FDISK and SFD. */
+ bsect = 0;
+ fmt = check_fs(fs, bsect); /* Load sector 0 and check if it is an FAT-VBR as SFD */
+ if (fmt == 2 || (fmt < 2 && LD2PT(vol) != 0)) { /* Not an FAT-VBR or forced partition number */
+ for (i = 0; i < 4; i++) { /* Get partition offset */
+ pt = fs->win + (MBR_Table + i * SZ_PTE);
+ br[i] = pt[PTE_System] ? ld_dword(pt + PTE_StLba) : 0;
+ }
+ i = LD2PT(vol); /* Partition number: 0:auto, 1-4:forced */
+ if (i != 0) i--;
+ do { /* Find an FAT volume */
+ bsect = br[i];
+ fmt = bsect ? check_fs(fs, bsect) : 3; /* Check the partition */
+ } while (LD2PT(vol) == 0 && fmt >= 2 && ++i < 4);
+ }
+ if (fmt == 4) return FR_DISK_ERR; /* An error occurred in the disk I/O layer */
+ if (fmt >= 2) return FR_NO_FILESYSTEM; /* No FAT volume is found */
+
+ /* An FAT volume is found (bsect). Following code initializes the filesystem object */
+
+#if FF_FS_EXFAT
+ if (fmt == 1) {
+ QWORD maxlba;
+
+ for (i = BPB_ZeroedEx; i < BPB_ZeroedEx + 53 && fs->win[i] == 0; i++) ; /* Check zero filler */
+ if (i < BPB_ZeroedEx + 53) return FR_NO_FILESYSTEM;
+
+ if (ld_word(fs->win + BPB_FSVerEx) != 0x100) return FR_NO_FILESYSTEM; /* Check exFAT version (must be version 1.0) */
+
+ if (1 << fs->win[BPB_BytsPerSecEx] != SS(fs)) { /* (BPB_BytsPerSecEx must be equal to the physical sector size) */
+ return FR_NO_FILESYSTEM;
+ }
+
+ maxlba = ld_qword(fs->win + BPB_TotSecEx) + bsect; /* Last LBA + 1 of the volume */
+ if (maxlba >= 0x100000000) return FR_NO_FILESYSTEM; /* (It cannot be handled in 32-bit LBA) */
+
+ fs->fsize = ld_dword(fs->win + BPB_FatSzEx); /* Number of sectors per FAT */
+
+ fs->n_fats = fs->win[BPB_NumFATsEx]; /* Number of FATs */
+ if (fs->n_fats != 1) return FR_NO_FILESYSTEM; /* (Supports only 1 FAT) */
+
+ fs->csize = 1 << fs->win[BPB_SecPerClusEx]; /* Cluster size */
+ if (fs->csize == 0) return FR_NO_FILESYSTEM; /* (Must be 1..32768) */
+
+ nclst = ld_dword(fs->win + BPB_NumClusEx); /* Number of clusters */
+ if (nclst > MAX_EXFAT) return FR_NO_FILESYSTEM; /* (Too many clusters) */
+ fs->n_fatent = nclst + 2;
+
+ /* Boundaries and Limits */
+ fs->volbase = bsect;
+ fs->database = bsect + ld_dword(fs->win + BPB_DataOfsEx);
+ fs->fatbase = bsect + ld_dword(fs->win + BPB_FatOfsEx);
+ if (maxlba < (QWORD)fs->database + nclst * fs->csize) return FR_NO_FILESYSTEM; /* (Volume size must not be smaller than the size required) */
+ fs->dirbase = ld_dword(fs->win + BPB_RootClusEx);
+
+ /* Check if bitmap location is in assumption (at the first cluster) */
+ if (move_window(fs, clst2sect(fs, fs->dirbase)) != FR_OK) return FR_DISK_ERR;
+ for (i = 0; i < SS(fs); i += SZDIRE) {
+ if (fs->win[i] == 0x81 && ld_dword(fs->win + i + 20) == 2) break; /* 81 entry with cluster #2? */
+ }
+ if (i == SS(fs)) return FR_NO_FILESYSTEM;
+#if !FF_FS_READONLY
+ fs->last_clst = fs->free_clst = 0xFFFFFFFF; /* Initialize cluster allocation information */
+#endif
+ fmt = FS_EXFAT; /* FAT sub-type */
+ } else
+#endif /* FF_FS_EXFAT */
+ {
+ if (ld_word(fs->win + BPB_BytsPerSec) != SS(fs)) return FR_NO_FILESYSTEM; /* (BPB_BytsPerSec must be equal to the physical sector size) */
+
+ fasize = ld_word(fs->win + BPB_FATSz16); /* Number of sectors per FAT */
+ if (fasize == 0) fasize = ld_dword(fs->win + BPB_FATSz32);
+ fs->fsize = fasize;
+
+ fs->n_fats = fs->win[BPB_NumFATs]; /* Number of FATs */
+ if (fs->n_fats != 1 && fs->n_fats != 2) return FR_NO_FILESYSTEM; /* (Must be 1 or 2) */
+ fasize *= fs->n_fats; /* Number of sectors for FAT area */
+
+ fs->csize = fs->win[BPB_SecPerClus]; /* Cluster size */
+ if (fs->csize == 0 || (fs->csize & (fs->csize - 1))) return FR_NO_FILESYSTEM; /* (Must be power of 2) */
+
+ fs->n_rootdir = ld_word(fs->win + BPB_RootEntCnt); /* Number of root directory entries */
+ if (fs->n_rootdir % (SS(fs) / SZDIRE)) return FR_NO_FILESYSTEM; /* (Must be sector aligned) */
+
+ tsect = ld_word(fs->win + BPB_TotSec16); /* Number of sectors on the volume */
+ if (tsect == 0) tsect = ld_dword(fs->win + BPB_TotSec32);
+
+ nrsv = ld_word(fs->win + BPB_RsvdSecCnt); /* Number of reserved sectors */
+ if (nrsv == 0) return FR_NO_FILESYSTEM; /* (Must not be 0) */
+
+ /* Determine the FAT sub type */
+ sysect = nrsv + fasize + fs->n_rootdir / (SS(fs) / SZDIRE); /* RSV + FAT + DIR */
+ if (tsect < sysect) return FR_NO_FILESYSTEM; /* (Invalid volume size) */
+ nclst = (tsect - sysect) / fs->csize; /* Number of clusters */
+ if (nclst == 0) return FR_NO_FILESYSTEM; /* (Invalid volume size) */
+ fmt = 0;
+ if (nclst <= MAX_FAT32) fmt = FS_FAT32;
+ if (nclst <= MAX_FAT16) fmt = FS_FAT16;
+ if (nclst <= MAX_FAT12) fmt = FS_FAT12;
+ if (fmt == 0) return FR_NO_FILESYSTEM;
+
+ /* Boundaries and Limits */
+ fs->n_fatent = nclst + 2; /* Number of FAT entries */
+ fs->volbase = bsect; /* Volume start sector */
+ fs->fatbase = bsect + nrsv; /* FAT start sector */
+ fs->database = bsect + sysect; /* Data start sector */
+ if (fmt == FS_FAT32) {
+ if (ld_word(fs->win + BPB_FSVer32) != 0) return FR_NO_FILESYSTEM; /* (Must be FAT32 revision 0.0) */
+ if (fs->n_rootdir != 0) return FR_NO_FILESYSTEM; /* (BPB_RootEntCnt must be 0) */
+ fs->dirbase = ld_dword(fs->win + BPB_RootClus32); /* Root directory start cluster */
+ szbfat = fs->n_fatent * 4; /* (Needed FAT size) */
+ } else {
+ if (fs->n_rootdir == 0) return FR_NO_FILESYSTEM; /* (BPB_RootEntCnt must not be 0) */
+ fs->dirbase = fs->fatbase + fasize; /* Root directory start sector */
+ szbfat = (fmt == FS_FAT16) ? /* (Needed FAT size) */
+ fs->n_fatent * 2 : fs->n_fatent * 3 / 2 + (fs->n_fatent & 1);
+ }
+ if (fs->fsize < (szbfat + (SS(fs) - 1)) / SS(fs)) return FR_NO_FILESYSTEM; /* (BPB_FATSz must not be less than the size needed) */
+
+#if !FF_FS_READONLY
+ /* Get FSInfo if available */
+ fs->last_clst = fs->free_clst = 0xFFFFFFFF; /* Initialize cluster allocation information */
+ fs->fsi_flag = 0x80;
+#if (FF_FS_NOFSINFO & 3) != 3
+ if (fmt == FS_FAT32 /* Allow to update FSInfo only if BPB_FSInfo32 == 1 */
+ && ld_word(fs->win + BPB_FSInfo32) == 1
+ && move_window(fs, bsect + 1) == FR_OK)
+ {
+ fs->fsi_flag = 0;
+ if (ld_word(fs->win + BS_55AA) == 0xAA55 /* Load FSInfo data if available */
+ && ld_dword(fs->win + FSI_LeadSig) == 0x41615252
+ && ld_dword(fs->win + FSI_StrucSig) == 0x61417272)
+ {
+#if (FF_FS_NOFSINFO & 1) == 0
+ fs->free_clst = ld_dword(fs->win + FSI_Free_Count);
+#endif
+#if (FF_FS_NOFSINFO & 2) == 0
+ fs->last_clst = ld_dword(fs->win + FSI_Nxt_Free);
+#endif
+ }
+ }
+#endif /* (FF_FS_NOFSINFO & 3) != 3 */
+#endif /* !FF_FS_READONLY */
+ }
+
+ fs->fs_type = fmt; /* FAT sub-type */
+ fs->id = ++Fsid; /* Volume mount ID */
+#if FF_USE_LFN == 1
+ fs->lfnbuf = LfnBuf; /* Static LFN working buffer */
+#if FF_FS_EXFAT
+ fs->dirbuf = DirBuf; /* Static directory block scratchpad buuffer */
+#endif
+#endif
+#if FF_FS_RPATH != 0
+ fs->cdir = 0; /* Initialize current directory */
+#endif
+#if FF_FS_LOCK != 0 /* Clear file lock semaphores */
+ clear_lock(fs);
+#endif
+ return FR_OK;
+}
+
+
+
+
+/*-----------------------------------------------------------------------*/
+/* Check if the file/directory object is valid or not */
+/*-----------------------------------------------------------------------*/
+
+static FRESULT validate ( /* Returns FR_OK or FR_INVALID_OBJECT */
+ FFOBJID* obj, /* Pointer to the FFOBJID, the 1st member in the FIL/DIR object, to check validity */
+ FATFS** rfs /* Pointer to pointer to the owner filesystem object to return */
+)
+{
+ FRESULT res = FR_INVALID_OBJECT;
+
+
+ if (obj && obj->fs && obj->fs->fs_type && obj->id == obj->fs->id) { /* Test if the object is valid */
+#if FF_FS_REENTRANT
+ if (lock_fs(obj->fs)) { /* Obtain the filesystem object */
+ if (!(disk_status(obj->fs->pdrv) & STA_NOINIT)) { /* Test if the phsical drive is kept initialized */
+ res = FR_OK;
+ } else {
+ unlock_fs(obj->fs, FR_OK);
+ }
+ } else {
+ res = FR_TIMEOUT;
+ }
+#else
+ if (!(disk_status(obj->fs->pdrv) & STA_NOINIT)) { /* Test if the phsical drive is kept initialized */
+ res = FR_OK;
+ }
+#endif
+ }
+ *rfs = (res == FR_OK) ? obj->fs : 0; /* Corresponding filesystem object */
+ return res;
+}
+
+
+
+
+/*---------------------------------------------------------------------------
+
+ Public Functions (FatFs API)
+
+----------------------------------------------------------------------------*/
+
+
+
+/*-----------------------------------------------------------------------*/
+/* Mount/Unmount a Logical Drive */
+/*-----------------------------------------------------------------------*/
+
+FRESULT f_mount (
+ FATFS* fs, /* Pointer to the filesystem object (NULL:unmount)*/
+ const TCHAR* path, /* Logical drive number to be mounted/unmounted */
+ BYTE opt /* Mode option 0:Do not mount (delayed mount), 1:Mount immediately */
+)
+{
+ FATFS *cfs;
+ int vol;
+ FRESULT res = FR_DISK_ERR;
+ const TCHAR *rp = path;
+
+
+ /* Get logical drive number */
+ vol = get_ldnumber(&rp);
+ if (vol < 0) return FR_INVALID_DRIVE;
+ cfs = FatFs[vol]; /* Pointer to fs object */
+
+ if (cfs) {
+#if FF_FS_LOCK != 0
+ clear_lock(cfs);
+#endif
+#if FF_FS_REENTRANT /* Discard sync object of the current volume */
+ if (!ff_del_syncobj(cfs->sobj)) return FR_INT_ERR;
+#endif
+ cfs->fs_type = 0; /* Clear old fs object */
+ }
+
+ if (fs) {
+ fs->fs_type = 0; /* Clear new fs object */
+#if FF_FS_REENTRANT /* Create sync object for the new volume */
+ if (!ff_cre_syncobj((BYTE)vol, &fs->sobj)) return FR_INT_ERR;
+#endif
+ }
+ FatFs[vol] = fs; /* Register new fs object */
+
+ if (opt == 0) return FR_OK; /* Do not mount now, it will be mounted later */
+
+ res = find_volume(&path, &fs, 0); /* Force mounted the volume */
+ LEAVE_FF(fs, res);
+}
+
+
+
+
+/*-----------------------------------------------------------------------*/
+/* Open or Create a File */
+/*-----------------------------------------------------------------------*/
+
+FRESULT f_open (
+ FIL* fp, /* Pointer to the blank file object */
+ const TCHAR* path, /* Pointer to the file name */
+ BYTE mode /* Access mode and file open mode flags */
+)
+{
+ FRESULT res = FR_DISK_ERR;
+ DIR dj = {0};
+ FATFS *fs;
+#if !FF_FS_READONLY
+ DWORD dw, cl, bcs, clst, sc;
+ FSIZE_t ofs;
+#endif
+ DEF_NAMBUF
+
+
+ if (!fp) return FR_INVALID_OBJECT;
+
+ /* Get logical drive number */
+ mode &= FF_FS_READONLY ? FA_READ : FA_READ | FA_WRITE | FA_CREATE_ALWAYS | FA_CREATE_NEW | FA_OPEN_ALWAYS | FA_OPEN_APPEND;
+ res = find_volume(&path, &fs, mode);
+ if (res == FR_OK) {
+ dj.obj.fs = fs;
+ INIT_NAMBUF(fs);
+ res = follow_path(&dj, path); /* Follow the file path */
+#if !FF_FS_READONLY /* Read/Write configuration */
+ if (res == FR_OK) {
+ if (dj.fn[NSFLAG] & NS_NONAME) { /* Origin directory itself? */
+ res = FR_INVALID_NAME;
+ }
+#if FF_FS_LOCK != 0
+ else {
+ res = chk_lock(&dj, (mode & ~FA_READ) ? 1 : 0); /* Check if the file can be used */
+ }
+#endif
+ }
+ /* Create or Open a file */
+ if (mode & (FA_CREATE_ALWAYS | FA_OPEN_ALWAYS | FA_CREATE_NEW)) {
+ if (res != FR_OK) { /* No file, create new */
+ if (res == FR_NO_FILE) { /* There is no file to open, create a new entry */
+#if FF_FS_LOCK != 0
+ res = enq_lock() ? dir_register(&dj) : FR_TOO_MANY_OPEN_FILES;
+#else
+ res = dir_register(&dj);
+#endif
+ }
+ mode |= FA_CREATE_ALWAYS; /* File is created */
+ }
+ else { /* Any object with the same name is already existing */
+ if (dj.obj.attr & (AM_RDO | AM_DIR)) { /* Cannot overwrite it (R/O or DIR) */
+ res = FR_DENIED;
+ } else {
+ if (mode & FA_CREATE_NEW) res = FR_EXIST; /* Cannot create as new file */
+ }
+ }
+ if (res == FR_OK && (mode & FA_CREATE_ALWAYS)) { /* Truncate the file if overwrite mode */
+#if FF_FS_EXFAT
+ if (fs->fs_type == FS_EXFAT) {
+ /* Get current allocation info */
+ fp->obj.fs = fs;
+ init_alloc_info(fs, &fp->obj);
+ /* Set directory entry block initial state */
+ mem_set(fs->dirbuf + 2, 0, 30); /* Clear 85 entry except for NumSec */
+ mem_set(fs->dirbuf + 38, 0, 26); /* Clear C0 entry except for NumName and NameHash */
+ fs->dirbuf[XDIR_Attr] = AM_ARC;
+ st_dword(fs->dirbuf + XDIR_CrtTime, GET_FATTIME());
+ fs->dirbuf[XDIR_GenFlags] = 1;
+ res = store_xdir(&dj);
+ if (res == FR_OK && fp->obj.sclust != 0) { /* Remove the cluster chain if exist */
+ res = remove_chain(&fp->obj, fp->obj.sclust, 0);
+ fs->last_clst = fp->obj.sclust - 1; /* Reuse the cluster hole */
+ }
+ } else
+#endif
+ {
+ /* Set directory entry initial state */
+ cl = ld_clust(fs, dj.dir); /* Get current cluster chain */
+ st_dword(dj.dir + DIR_CrtTime, GET_FATTIME()); /* Set created time */
+ dj.dir[DIR_Attr] = AM_ARC; /* Reset attribute */
+ st_clust(fs, dj.dir, 0); /* Reset file allocation info */
+ st_dword(dj.dir + DIR_FileSize, 0);
+ fs->wflag = 1;
+ if (cl != 0) { /* Remove the cluster chain if exist */
+ dw = fs->winsect;
+ res = remove_chain(&dj.obj, cl, 0);
+ if (res == FR_OK) {
+ res = move_window(fs, dw);
+ fs->last_clst = cl - 1; /* Reuse the cluster hole */
+ }
+ }
+ }
+ }
+ }
+ else { /* Open an existing file */
+ if (res == FR_OK) { /* Is the object existing? */
+ if (dj.obj.attr & AM_DIR) { /* File open against a directory */
+ res = FR_NO_FILE;
+ } else {
+ if ((mode & FA_WRITE) && (dj.obj.attr & AM_RDO)) { /* Write mode open against R/O file */
+ res = FR_DENIED;
+ }
+ }
+ }
+ }
+ if (res == FR_OK) {
+ if (mode & FA_CREATE_ALWAYS) mode |= FA_MODIFIED; /* Set file change flag if created or overwritten */
+ fp->dir_sect = fs->winsect; /* Pointer to the directory entry */
+ fp->dir_ptr = dj.dir;
+#if FF_FS_LOCK != 0
+ fp->obj.lockid = inc_lock(&dj, (mode & ~FA_READ) ? 1 : 0); /* Lock the file for this session */
+ if (fp->obj.lockid == 0) res = FR_INT_ERR;
+#endif
+ }
+#else /* R/O configuration */
+ if (res == FR_OK) {
+ if (dj.fn[NSFLAG] & NS_NONAME) { /* Is it origin directory itself? */
+ res = FR_INVALID_NAME;
+ } else {
+ if (dj.obj.attr & AM_DIR) { /* Is it a directory? */
+ res = FR_NO_FILE;
+ }
+ }
+ }
+#endif
+
+ if (res == FR_OK) {
+#if FF_FS_EXFAT
+ if (fs->fs_type == FS_EXFAT) {
+ fp->obj.c_scl = dj.obj.sclust; /* Get containing directory info */
+ fp->obj.c_size = ((DWORD)dj.obj.objsize & 0xFFFFFF00) | dj.obj.stat;
+ fp->obj.c_ofs = dj.blk_ofs;
+ init_alloc_info(fs, &fp->obj);
+ } else
+#endif
+ {
+ fp->obj.sclust = ld_clust(fs, dj.dir); /* Get object allocation info */
+ fp->obj.objsize = ld_dword(dj.dir + DIR_FileSize);
+ }
+#if FF_USE_FASTSEEK
+ fp->cltbl = 0; /* Disable fast seek mode */
+#endif
+ fp->obj.fs = fs; /* Validate the file object */
+ fp->obj.id = fs->id;
+ fp->flag = mode; /* Set file access mode */
+ fp->err = 0; /* Clear error flag */
+ fp->sect = 0; /* Invalidate current data sector */
+ fp->fptr = 0; /* Set file pointer top of the file */
+#if !FF_FS_READONLY
+#if !FF_FS_TINY
+ mem_set(fp->buf, 0, FF_MAX_SS); /* Clear sector buffer */
+#endif
+ if ((mode & FA_SEEKEND) && fp->obj.objsize > 0) { /* Seek to end of file if FA_OPEN_APPEND is specified */
+ fp->fptr = fp->obj.objsize; /* Offset to seek */
+ bcs = (DWORD)fs->csize * SS(fs); /* Cluster size in byte */
+ clst = fp->obj.sclust; /* Follow the cluster chain */
+ for (ofs = fp->obj.objsize; res == FR_OK && ofs > bcs; ofs -= bcs) {
+ clst = get_fat(&fp->obj, clst);
+ if (clst <= 1) res = FR_INT_ERR;
+ if (clst == 0xFFFFFFFF) res = FR_DISK_ERR;
+ }
+ fp->clust = clst;
+ if (res == FR_OK && ofs % SS(fs)) { /* Fill sector buffer if not on the sector boundary */
+ if ((sc = clst2sect(fs, clst)) == 0) {
+ res = FR_INT_ERR;
+ } else {
+ fp->sect = sc + (DWORD)(ofs / SS(fs));
+#if !FF_FS_TINY
+ if (disk_read(fs->pdrv, fp->buf, fp->sect, 1) != RES_OK) res = FR_DISK_ERR;
+#endif
+ }
+ }
+ }
+#endif
+ }
+
+ FREE_NAMBUF();
+ }
+
+ if (res != FR_OK) fp->obj.fs = 0; /* Invalidate file object on error */
+
+ LEAVE_FF(fs, res);
+}
+
+
+
+
+/*-----------------------------------------------------------------------*/
+/* Read File */
+/*-----------------------------------------------------------------------*/
+
+FRESULT f_read (
+ FIL* fp, /* Pointer to the file object */
+ void* buff, /* Pointer to data buffer */
+ UINT btr, /* Number of bytes to read */
+ UINT* br /* Pointer to number of bytes read */
+)
+{
+ FRESULT res = FR_DISK_ERR;
+ FATFS *fs;
+ DWORD clst, sect;
+ FSIZE_t remain;
+ UINT rcnt, cc, csect;
+ BYTE *rbuff = (BYTE*)buff;
+
+
+ *br = 0; /* Clear read byte counter */
+ res = validate(&fp->obj, &fs); /* Check validity of the file object */
+ if (res != FR_OK || (res = (FRESULT)fp->err) != FR_OK) LEAVE_FF(fs, res); /* Check validity */
+ if (!(fp->flag & FA_READ)) LEAVE_FF(fs, FR_DENIED); /* Check access mode */
+ remain = fp->obj.objsize - fp->fptr;
+ if (btr > remain) btr = (UINT)remain; /* Truncate btr by remaining bytes */
+
+ for ( ; btr; /* Repeat until btr bytes read */
+ btr -= rcnt, *br += rcnt, rbuff += rcnt, fp->fptr += rcnt) {
+ if (fp->fptr % SS(fs) == 0) { /* On the sector boundary? */
+ csect = (UINT)(fp->fptr / SS(fs) & (fs->csize - 1)); /* Sector offset in the cluster */
+ if (csect == 0) { /* On the cluster boundary? */
+ if (fp->fptr == 0) { /* On the top of the file? */
+ clst = fp->obj.sclust; /* Follow cluster chain from the origin */
+ } else { /* Middle or end of the file */
+#if FF_USE_FASTSEEK
+ if (fp->cltbl) {
+ clst = clmt_clust(fp, fp->fptr); /* Get cluster# from the CLMT */
+ } else
+#endif
+ {
+ clst = get_fat(&fp->obj, fp->clust); /* Follow cluster chain on the FAT */
+ }
+ }
+ if (clst < 2) ABORT(fs, FR_INT_ERR);
+ if (clst == 0xFFFFFFFF) ABORT(fs, FR_DISK_ERR);
+ fp->clust = clst; /* Update current cluster */
+ }
+ sect = clst2sect(fs, fp->clust); /* Get current sector */
+ if (sect == 0) ABORT(fs, FR_INT_ERR);
+ sect += csect;
+ cc = btr / SS(fs); /* When remaining bytes >= sector size, */
+ if (cc > 0) { /* Read maximum contiguous sectors directly */
+ if (csect + cc > fs->csize) { /* Clip at cluster boundary */
+ cc = fs->csize - csect;
+ }
+ if (disk_read(fs->pdrv, rbuff, sect, cc) != RES_OK) ABORT(fs, FR_DISK_ERR);
+#if !FF_FS_READONLY && FF_FS_MINIMIZE <= 2 /* Replace one of the read sectors with cached data if it contains a dirty sector */
+#if FF_FS_TINY
+ if (fs->wflag && fs->winsect - sect < cc) {
+ mem_cpy(rbuff + ((fs->winsect - sect) * SS(fs)), fs->win, SS(fs));
+ }
+#else
+ if ((fp->flag & FA_DIRTY) && fp->sect - sect < cc) {
+ mem_cpy(rbuff + ((fp->sect - sect) * SS(fs)), fp->buf, SS(fs));
+ }
+#endif
+#endif
+ rcnt = SS(fs) * cc; /* Number of bytes transferred */
+ continue;
+ }
+#if !FF_FS_TINY
+ if (fp->sect != sect) { /* Load data sector if not in cache */
+#if !FF_FS_READONLY
+ if (fp->flag & FA_DIRTY) { /* Write-back dirty sector cache */
+ if (disk_write(fs->pdrv, fp->buf, fp->sect, 1) != RES_OK) ABORT(fs, FR_DISK_ERR);
+ fp->flag &= (BYTE)~FA_DIRTY;
+ }
+#endif
+ if (disk_read(fs->pdrv, fp->buf, sect, 1) != RES_OK) ABORT(fs, FR_DISK_ERR); /* Fill sector cache */
+ }
+#endif
+ fp->sect = sect;
+ }
+ rcnt = SS(fs) - (UINT)fp->fptr % SS(fs); /* Number of bytes left in the sector */
+ if (rcnt > btr) rcnt = btr; /* Clip it by btr if needed */
+#if FF_FS_TINY
+ if (move_window(fs, fp->sect) != FR_OK) ABORT(fs, FR_DISK_ERR); /* Move sector window */
+ mem_cpy(rbuff, fs->win + fp->fptr % SS(fs), rcnt); /* Extract partial sector */
+#else
+ mem_cpy(rbuff, fp->buf + fp->fptr % SS(fs), rcnt); /* Extract partial sector */
+#endif
+ }
+
+ LEAVE_FF(fs, FR_OK);
+}
+
+
+
+
+#if !FF_FS_READONLY
+/*-----------------------------------------------------------------------*/
+/* Write File */
+/*-----------------------------------------------------------------------*/
+
+FRESULT f_write (
+ FIL* fp, /* Pointer to the file object */
+ const void* buff, /* Pointer to the data to be written */
+ UINT btw, /* Number of bytes to write */
+ UINT* bw /* Pointer to number of bytes written */
+)
+{
+ FRESULT res = FR_DISK_ERR;
+ FATFS *fs;
+ DWORD clst, sect;
+ UINT wcnt, cc, csect;
+ const BYTE *wbuff = (const BYTE*)buff;
+
+
+ *bw = 0; /* Clear write byte counter */
+ res = validate(&fp->obj, &fs); /* Check validity of the file object */
+ if (res != FR_OK || (res = (FRESULT)fp->err) != FR_OK) LEAVE_FF(fs, res); /* Check validity */
+ if (!(fp->flag & FA_WRITE)) LEAVE_FF(fs, FR_DENIED); /* Check access mode */
+
+ /* Check fptr wrap-around (file size cannot reach 4 GiB at FAT volume) */
+ if ((!FF_FS_EXFAT || fs->fs_type != FS_EXFAT) && (DWORD)(fp->fptr + btw) < (DWORD)fp->fptr) {
+ btw = (UINT)(0xFFFFFFFF - (DWORD)fp->fptr);
+ }
+
+ for ( ; btw; /* Repeat until all data written */
+ btw -= wcnt, *bw += wcnt, wbuff += wcnt, fp->fptr += wcnt, fp->obj.objsize = (fp->fptr > fp->obj.objsize) ? fp->fptr : fp->obj.objsize) {
+ if (fp->fptr % SS(fs) == 0) { /* On the sector boundary? */
+ csect = (UINT)(fp->fptr / SS(fs)) & (fs->csize - 1); /* Sector offset in the cluster */
+ if (csect == 0) { /* On the cluster boundary? */
+ if (fp->fptr == 0) { /* On the top of the file? */
+ clst = fp->obj.sclust; /* Follow from the origin */
+ if (clst == 0) { /* If no cluster is allocated, */
+ clst = create_chain(&fp->obj, 0); /* create a new cluster chain */
+ }
+ } else { /* On the middle or end of the file */
+#if FF_USE_FASTSEEK
+ if (fp->cltbl) {
+ clst = clmt_clust(fp, fp->fptr); /* Get cluster# from the CLMT */
+ } else
+#endif
+ {
+ clst = create_chain(&fp->obj, fp->clust); /* Follow or stretch cluster chain on the FAT */
+ }
+ }
+ if (clst == 0) break; /* Could not allocate a new cluster (disk full) */
+ if (clst == 1) ABORT(fs, FR_INT_ERR);
+ if (clst == 0xFFFFFFFF) ABORT(fs, FR_DISK_ERR);
+ fp->clust = clst; /* Update current cluster */
+ if (fp->obj.sclust == 0) fp->obj.sclust = clst; /* Set start cluster if the first write */
+ }
+#if FF_FS_TINY
+ if (fs->winsect == fp->sect && sync_window(fs) != FR_OK) ABORT(fs, FR_DISK_ERR); /* Write-back sector cache */
+#else
+ if (fp->flag & FA_DIRTY) { /* Write-back sector cache */
+ if (disk_write(fs->pdrv, fp->buf, fp->sect, 1) != RES_OK) ABORT(fs, FR_DISK_ERR);
+ fp->flag &= (BYTE)~FA_DIRTY;
+ }
+#endif
+ sect = clst2sect(fs, fp->clust); /* Get current sector */
+ if (sect == 0) ABORT(fs, FR_INT_ERR);
+ sect += csect;
+ cc = btw / SS(fs); /* When remaining bytes >= sector size, */
+ if (cc > 0) { /* Write maximum contiguous sectors directly */
+ if (csect + cc > fs->csize) { /* Clip at cluster boundary */
+ cc = fs->csize - csect;
+ }
+ if (disk_write(fs->pdrv, wbuff, sect, cc) != RES_OK) ABORT(fs, FR_DISK_ERR);
+#if FF_FS_MINIMIZE <= 2
+#if FF_FS_TINY
+ if (fs->winsect - sect < cc) { /* Refill sector cache if it gets invalidated by the direct write */
+ mem_cpy(fs->win, wbuff + ((fs->winsect - sect) * SS(fs)), SS(fs));
+ fs->wflag = 0;
+ }
+#else
+ if (fp->sect - sect < cc) { /* Refill sector cache if it gets invalidated by the direct write */
+ mem_cpy(fp->buf, wbuff + ((fp->sect - sect) * SS(fs)), SS(fs));
+ fp->flag &= (BYTE)~FA_DIRTY;
+ }
+#endif
+#endif
+ wcnt = SS(fs) * cc; /* Number of bytes transferred */
+ continue;
+ }
+#if FF_FS_TINY
+ if (fp->fptr >= fp->obj.objsize) { /* Avoid silly cache filling on the growing edge */
+ if (sync_window(fs) != FR_OK) ABORT(fs, FR_DISK_ERR);
+ fs->winsect = sect;
+ }
+#else
+ if (fp->sect != sect && /* Fill sector cache with file data */
+ fp->fptr < fp->obj.objsize &&
+ disk_read(fs->pdrv, fp->buf, sect, 1) != RES_OK) {
+ ABORT(fs, FR_DISK_ERR);
+ }
+#endif
+ fp->sect = sect;
+ }
+ wcnt = SS(fs) - (UINT)fp->fptr % SS(fs); /* Number of bytes left in the sector */
+ if (wcnt > btw) wcnt = btw; /* Clip it by btw if needed */
+#if FF_FS_TINY
+ if (move_window(fs, fp->sect) != FR_OK) ABORT(fs, FR_DISK_ERR); /* Move sector window */
+ mem_cpy(fs->win + fp->fptr % SS(fs), wbuff, wcnt); /* Fit data to the sector */
+ fs->wflag = 1;
+#else
+ mem_cpy(fp->buf + fp->fptr % SS(fs), wbuff, wcnt); /* Fit data to the sector */
+ fp->flag |= FA_DIRTY;
+#endif
+ }
+
+ fp->flag |= FA_MODIFIED; /* Set file change flag */
+
+ LEAVE_FF(fs, FR_OK);
+}
+
+
+
+
+/*-----------------------------------------------------------------------*/
+/* Synchronize the File */
+/*-----------------------------------------------------------------------*/
+
+FRESULT f_sync (
+ FIL* fp /* Pointer to the file object */
+)
+{
+ FRESULT res = FR_DISK_ERR;
+ FATFS *fs;
+ DWORD tm;
+ BYTE *dir;
+
+
+ res = validate(&fp->obj, &fs); /* Check validity of the file object */
+ if (res == FR_OK) {
+ if (fp->flag & FA_MODIFIED) { /* Is there any change to the file? */
+#if !FF_FS_TINY
+ if (fp->flag & FA_DIRTY) { /* Write-back cached data if needed */
+ if (disk_write(fs->pdrv, fp->buf, fp->sect, 1) != RES_OK) LEAVE_FF(fs, FR_DISK_ERR);
+ fp->flag &= (BYTE)~FA_DIRTY;
+ }
+#endif
+ /* Update the directory entry */
+ tm = GET_FATTIME(); /* Modified time */
+#if FF_FS_EXFAT
+ if (fs->fs_type == FS_EXFAT) {
+ res = fill_first_frag(&fp->obj); /* Fill first fragment on the FAT if needed */
+ if (res == FR_OK) {
+ res = fill_last_frag(&fp->obj, fp->clust, 0xFFFFFFFF); /* Fill last fragment on the FAT if needed */
+ }
+ if (res == FR_OK) {
+ DIR dj;
+ DEF_NAMBUF
+
+ INIT_NAMBUF(fs);
+ res = load_obj_xdir(&dj, &fp->obj); /* Load directory entry block */
+ if (res == FR_OK) {
+ fs->dirbuf[XDIR_Attr] |= AM_ARC; /* Set archive attribute to indicate that the file has been changed */
+ fs->dirbuf[XDIR_GenFlags] = fp->obj.stat | 1; /* Update file allocation information */
+ st_dword(fs->dirbuf + XDIR_FstClus, fp->obj.sclust);
+ st_qword(fs->dirbuf + XDIR_FileSize, fp->obj.objsize);
+ st_qword(fs->dirbuf + XDIR_ValidFileSize, fp->obj.objsize);
+ st_dword(fs->dirbuf + XDIR_ModTime, tm); /* Update modified time */
+ fs->dirbuf[XDIR_ModTime10] = 0;
+ st_dword(fs->dirbuf + XDIR_AccTime, 0);
+ res = store_xdir(&dj); /* Restore it to the directory */
+ if (res == FR_OK) {
+ res = sync_fs(fs);
+ fp->flag &= (BYTE)~FA_MODIFIED;
+ }
+ }
+ FREE_NAMBUF();
+ }
+ } else
+#endif
+ {
+ res = move_window(fs, fp->dir_sect);
+ if (res == FR_OK) {
+ dir = fp->dir_ptr;
+ dir[DIR_Attr] |= AM_ARC; /* Set archive attribute to indicate that the file has been changed */
+ st_clust(fp->obj.fs, dir, fp->obj.sclust); /* Update file allocation information */
+ st_dword(dir + DIR_FileSize, (DWORD)fp->obj.objsize); /* Update file size */
+ st_dword(dir + DIR_ModTime, tm); /* Update modified time */
+ st_word(dir + DIR_LstAccDate, 0);
+ fs->wflag = 1;
+ res = sync_fs(fs); /* Restore it to the directory */
+ fp->flag &= (BYTE)~FA_MODIFIED;
+ }
+ }
+ }
+ }
+
+ LEAVE_FF(fs, res);
+}
+
+#endif /* !FF_FS_READONLY */
+
+
+
+
+/*-----------------------------------------------------------------------*/
+/* Close File */
+/*-----------------------------------------------------------------------*/
+
+FRESULT f_close (
+ FIL* fp /* Pointer to the file object to be closed */
+)
+{
+ FRESULT res = FR_DISK_ERR;
+ FATFS *fs;
+
+#if !FF_FS_READONLY
+ res = f_sync(fp); /* Flush cached data */
+ if (res == FR_OK)
+#endif
+ {
+ res = validate(&fp->obj, &fs); /* Lock volume */
+ if (res == FR_OK) {
+#if FF_FS_LOCK != 0
+ res = dec_lock(fp->obj.lockid); /* Decrement file open counter */
+ if (res == FR_OK) fp->obj.fs = 0; /* Invalidate file object */
+#else
+ fp->obj.fs = 0; /* Invalidate file object */
+#endif
+#if FF_FS_REENTRANT
+ unlock_fs(fs, FR_OK); /* Unlock volume */
+#endif
+ }
+ }
+ return res;
+}
+
+
+
+
+#if FF_FS_RPATH >= 1
+/*-----------------------------------------------------------------------*/
+/* Change Current Directory or Current Drive, Get Current Directory */
+/*-----------------------------------------------------------------------*/
+
+FRESULT f_chdrive (
+ const TCHAR* path /* Drive number to set */
+)
+{
+ int vol;
+
+
+ /* Get logical drive number */
+ vol = get_ldnumber(&path);
+ if (vol < 0) return FR_INVALID_DRIVE;
+ CurrVol = (BYTE)vol; /* Set it as current volume */
+
+ return FR_OK;
+}
+
+
+
+FRESULT f_chdir (
+ const TCHAR* path /* Pointer to the directory path */
+)
+{
+#if FF_STR_VOLUME_ID == 2
+ UINT i;
+#endif
+ FRESULT res = FR_DISK_ERR;
+ DIR dj;
+ FATFS *fs;
+ DEF_NAMBUF
+
+
+ /* Get logical drive */
+ res = find_volume(&path, &fs, 0);
+ if (res == FR_OK) {
+ dj.obj.fs = fs;
+ INIT_NAMBUF(fs);
+ res = follow_path(&dj, path); /* Follow the path */
+ if (res == FR_OK) { /* Follow completed */
+ if (dj.fn[NSFLAG] & NS_NONAME) { /* Is it the start directory itself? */
+ fs->cdir = dj.obj.sclust;
+#if FF_FS_EXFAT
+ if (fs->fs_type == FS_EXFAT) {
+ fs->cdc_scl = dj.obj.c_scl;
+ fs->cdc_size = dj.obj.c_size;
+ fs->cdc_ofs = dj.obj.c_ofs;
+ }
+#endif
+ } else {
+ if (dj.obj.attr & AM_DIR) { /* It is a sub-directory */
+#if FF_FS_EXFAT
+ if (fs->fs_type == FS_EXFAT) {
+ fs->cdir = ld_dword(fs->dirbuf + XDIR_FstClus); /* Sub-directory cluster */
+ fs->cdc_scl = dj.obj.sclust; /* Save containing directory information */
+ fs->cdc_size = ((DWORD)dj.obj.objsize & 0xFFFFFF00) | dj.obj.stat;
+ fs->cdc_ofs = dj.blk_ofs;
+ } else
+#endif
+ {
+ fs->cdir = ld_clust(fs, dj.dir); /* Sub-directory cluster */
+ }
+ } else {
+ res = FR_NO_PATH; /* Reached but a file */
+ }
+ }
+ }
+ FREE_NAMBUF();
+ if (res == FR_NO_FILE) res = FR_NO_PATH;
+#if FF_STR_VOLUME_ID == 2 /* Also current drive is changed at Unix style volume ID */
+ if (res == FR_OK) {
+ for (i = FF_VOLUMES - 1; i && fs != FatFs[i]; i--) ; /* Set current drive */
+ CurrVol = (BYTE)i;
+ }
+#endif
+ }
+
+ LEAVE_FF(fs, res);
+}
+
+
+#if FF_FS_RPATH >= 2
+FRESULT f_getcwd (
+ TCHAR* buff, /* Pointer to the directory path */
+ UINT len /* Size of buff in unit of TCHAR */
+)
+{
+ FRESULT res = FR_DISK_ERR;
+ DIR dj;
+ FATFS *fs;
+ UINT i, n;
+ DWORD ccl;
+ TCHAR *tp = buff;
+#if FF_VOLUMES >= 2
+ UINT vl;
+#endif
+#if FF_STR_VOLUME_ID
+ const char *vp;
+#endif
+ FILINFO fno;
+ DEF_NAMBUF
+
+
+ /* Get logical drive */
+ buff[0] = 0; /* Set null string to get current volume */
+ res = find_volume((const TCHAR**)&buff, &fs, 0); /* Get current volume */
+ if (res == FR_OK) {
+ dj.obj.fs = fs;
+ INIT_NAMBUF(fs);
+
+ /* Follow parent directories and create the path */
+ i = len; /* Bottom of buffer (directory stack base) */
+ if (!FF_FS_EXFAT || fs->fs_type != FS_EXFAT) { /* (Cannot do getcwd on exFAT and returns root path) */
+ dj.obj.sclust = fs->cdir; /* Start to follow upper directory from current directory */
+ while ((ccl = dj.obj.sclust) != 0) { /* Repeat while current directory is a sub-directory */
+ res = dir_sdi(&dj, 1 * SZDIRE); /* Get parent directory */
+ if (res != FR_OK) break;
+ res = move_window(fs, dj.sect);
+ if (res != FR_OK) break;
+ dj.obj.sclust = ld_clust(fs, dj.dir); /* Goto parent directory */
+ res = dir_sdi(&dj, 0);
+ if (res != FR_OK) break;
+ do { /* Find the entry links to the child directory */
+ res = dir_read_file(&dj);
+ if (res != FR_OK) break;
+ if (ccl == ld_clust(fs, dj.dir)) break; /* Found the entry */
+ res = dir_next(&dj, 0);
+ } while (res == FR_OK);
+ if (res == FR_NO_FILE) res = FR_INT_ERR;/* It cannot be 'not found'. */
+ if (res != FR_OK) break;
+ get_fileinfo(&dj, &fno); /* Get the directory name and push it to the buffer */
+ for (n = 0; fno.fname[n]; n++) ; /* Name length */
+ if (i < n + 1) { /* Insufficient space to store the path name? */
+ res = FR_NOT_ENOUGH_CORE; break;
+ }
+ while (n) buff[--i] = fno.fname[--n]; /* Stack the name */
+ buff[--i] = '/';
+ }
+ }
+ if (res == FR_OK) {
+ if (i == len) buff[--i] = '/'; /* Is it the root-directory? */
+#if FF_VOLUMES >= 2 /* Put drive prefix */
+ vl = 0;
+#if FF_STR_VOLUME_ID >= 1 /* String volume ID */
+ for (n = 0, vp = (const char*)VolumeStr[CurrVol]; vp[n]; n++) ;
+ if (i >= n + 2) {
+ if (FF_STR_VOLUME_ID == 2) *tp++ = (TCHAR)'/';
+ for (vl = 0; vl < n; *tp++ = (TCHAR)vp[vl], vl++) ;
+ if (FF_STR_VOLUME_ID == 1) *tp++ = (TCHAR)':';
+ vl++;
+ }
+#else /* Numeric volume ID */
+ if (i >= 3) {
+ *tp++ = (TCHAR)'0' + CurrVol;
+ *tp++ = (TCHAR)':';
+ vl = 2;
+ }
+#endif
+ if (vl == 0) res = FR_NOT_ENOUGH_CORE;
+#endif
+ /* Add current directory path */
+ if (res == FR_OK) {
+ do *tp++ = buff[i++]; while (i < len); /* Copy stacked path string */
+ }
+ }
+ FREE_NAMBUF();
+ }
+
+ *tp = 0;
+ LEAVE_FF(fs, res);
+}
+
+#endif /* FF_FS_RPATH >= 2 */
+#endif /* FF_FS_RPATH >= 1 */
+
+
+
+#if FF_FS_MINIMIZE <= 2
+/*-----------------------------------------------------------------------*/
+/* Seek File Read/Write Pointer */
+/*-----------------------------------------------------------------------*/
+
+FRESULT f_lseek (
+ FIL* fp, /* Pointer to the file object */
+ FSIZE_t ofs /* File pointer from top of file */
+)
+{
+ FRESULT res = FR_DISK_ERR;
+ FATFS *fs;
+ DWORD clst, bcs, nsect;
+ FSIZE_t ifptr;
+#if FF_USE_FASTSEEK
+ DWORD cl, pcl, ncl, tcl, dsc, tlen, ulen, *tbl;
+#endif
+
+ res = validate(&fp->obj, &fs); /* Check validity of the file object */
+ if (res == FR_OK) res = (FRESULT)fp->err;
+#if FF_FS_EXFAT && !FF_FS_READONLY
+ if (res == FR_OK && fs->fs_type == FS_EXFAT) {
+ res = fill_last_frag(&fp->obj, fp->clust, 0xFFFFFFFF); /* Fill last fragment on the FAT if needed */
+ }
+#endif
+ if (res != FR_OK) LEAVE_FF(fs, res);
+
+#if FF_USE_FASTSEEK
+ if (fp->cltbl) { /* Fast seek */
+ if (ofs == CREATE_LINKMAP) { /* Create CLMT */
+ tbl = fp->cltbl;
+ tlen = *tbl++; ulen = 2; /* Given table size and required table size */
+ cl = fp->obj.sclust; /* Origin of the chain */
+ if (cl != 0) {
+ do {
+ /* Get a fragment */
+ tcl = cl; ncl = 0; ulen += 2; /* Top, length and used items */
+ do {
+ pcl = cl; ncl++;
+ cl = get_fat(&fp->obj, cl);
+ if (cl <= 1) ABORT(fs, FR_INT_ERR);
+ if (cl == 0xFFFFFFFF) ABORT(fs, FR_DISK_ERR);
+ } while (cl == pcl + 1);
+ if (ulen <= tlen) { /* Store the length and top of the fragment */
+ *tbl++ = ncl; *tbl++ = tcl;
+ }
+ } while (cl < fs->n_fatent); /* Repeat until end of chain */
+ }
+ *fp->cltbl = ulen; /* Number of items used */
+ if (ulen <= tlen) {
+ *tbl = 0; /* Terminate table */
+ } else {
+ res = FR_NOT_ENOUGH_CORE; /* Given table size is smaller than required */
+ }
+ } else { /* Fast seek */
+ if (ofs > fp->obj.objsize) ofs = fp->obj.objsize; /* Clip offset at the file size */
+ fp->fptr = ofs; /* Set file pointer */
+ if (ofs > 0) {
+ fp->clust = clmt_clust(fp, ofs - 1);
+ dsc = clst2sect(fs, fp->clust);
+ if (dsc == 0) ABORT(fs, FR_INT_ERR);
+ dsc += (DWORD)((ofs - 1) / SS(fs)) & (fs->csize - 1);
+ if (fp->fptr % SS(fs) && dsc != fp->sect) { /* Refill sector cache if needed */
+#if !FF_FS_TINY
+#if !FF_FS_READONLY
+ if (fp->flag & FA_DIRTY) { /* Write-back dirty sector cache */
+ if (disk_write(fs->pdrv, fp->buf, fp->sect, 1) != RES_OK) ABORT(fs, FR_DISK_ERR);
+ fp->flag &= (BYTE)~FA_DIRTY;
+ }
+#endif
+ if (disk_read(fs->pdrv, fp->buf, dsc, 1) != RES_OK) ABORT(fs, FR_DISK_ERR); /* Load current sector */
+#endif
+ fp->sect = dsc;
+ }
+ }
+ }
+ } else
+#endif
+
+ /* Normal Seek */
+ {
+#if FF_FS_EXFAT
+ if (fs->fs_type != FS_EXFAT && ofs >= 0x100000000) ofs = 0xFFFFFFFF; /* Clip at 4 GiB - 1 if at FATxx */
+#endif
+ if (ofs > fp->obj.objsize && (FF_FS_READONLY || !(fp->flag & FA_WRITE))) { /* In read-only mode, clip offset with the file size */
+ ofs = fp->obj.objsize;
+ }
+ ifptr = fp->fptr;
+ fp->fptr = nsect = 0;
+ if (ofs > 0) {
+ bcs = (DWORD)fs->csize * SS(fs); /* Cluster size (byte) */
+ if (ifptr > 0 &&
+ (ofs - 1) / bcs >= (ifptr - 1) / bcs) { /* When seek to same or following cluster, */
+ fp->fptr = (ifptr - 1) & ~(FSIZE_t)(bcs - 1); /* start from the current cluster */
+ ofs -= fp->fptr;
+ clst = fp->clust;
+ } else { /* When seek to back cluster, */
+ clst = fp->obj.sclust; /* start from the first cluster */
+#if !FF_FS_READONLY
+ if (clst == 0) { /* If no cluster chain, create a new chain */
+ clst = create_chain(&fp->obj, 0);
+ if (clst == 1) ABORT(fs, FR_INT_ERR);
+ if (clst == 0xFFFFFFFF) ABORT(fs, FR_DISK_ERR);
+ fp->obj.sclust = clst;
+ }
+#endif
+ fp->clust = clst;
+ }
+ if (clst != 0) {
+ while (ofs > bcs) { /* Cluster following loop */
+ ofs -= bcs; fp->fptr += bcs;
+#if !FF_FS_READONLY
+ if (fp->flag & FA_WRITE) { /* Check if in write mode or not */
+ if (FF_FS_EXFAT && fp->fptr > fp->obj.objsize) { /* No FAT chain object needs correct objsize to generate FAT value */
+ fp->obj.objsize = fp->fptr;
+ fp->flag |= FA_MODIFIED;
+ }
+ clst = create_chain(&fp->obj, clst); /* Follow chain with forceed stretch */
+ if (clst == 0) { /* Clip file size in case of disk full */
+ ofs = 0; break;
+ }
+ } else
+#endif
+ {
+ clst = get_fat(&fp->obj, clst); /* Follow cluster chain if not in write mode */
+ }
+ if (clst == 0xFFFFFFFF) ABORT(fs, FR_DISK_ERR);
+ if (clst <= 1 || clst >= fs->n_fatent) ABORT(fs, FR_INT_ERR);
+ fp->clust = clst;
+ }
+ fp->fptr += ofs;
+ if (ofs % SS(fs)) {
+ nsect = clst2sect(fs, clst); /* Current sector */
+ if (nsect == 0) ABORT(fs, FR_INT_ERR);
+ nsect += (DWORD)(ofs / SS(fs));
+ }
+ }
+ }
+ if (!FF_FS_READONLY && fp->fptr > fp->obj.objsize) { /* Set file change flag if the file size is extended */
+ fp->obj.objsize = fp->fptr;
+ fp->flag |= FA_MODIFIED;
+ }
+ if (fp->fptr % SS(fs) && nsect != fp->sect) { /* Fill sector cache if needed */
+#if !FF_FS_TINY
+#if !FF_FS_READONLY
+ if (fp->flag & FA_DIRTY) { /* Write-back dirty sector cache */
+ if (disk_write(fs->pdrv, fp->buf, fp->sect, 1) != RES_OK) ABORT(fs, FR_DISK_ERR);
+ fp->flag &= (BYTE)~FA_DIRTY;
+ }
+#endif
+ if (disk_read(fs->pdrv, fp->buf, nsect, 1) != RES_OK) ABORT(fs, FR_DISK_ERR); /* Fill sector cache */
+#endif
+ fp->sect = nsect;
+ }
+ }
+
+ LEAVE_FF(fs, res);
+}
+
+
+
+#if FF_FS_MINIMIZE <= 1
+/*-----------------------------------------------------------------------*/
+/* Create a Directory Object */
+/*-----------------------------------------------------------------------*/
+
+FRESULT f_opendir (
+ DIR* dp, /* Pointer to directory object to create */
+ const TCHAR* path /* Pointer to the directory path */
+)
+{
+ FRESULT res = FR_DISK_ERR;
+ FATFS *fs;
+ DEF_NAMBUF
+
+
+ if (!dp) return FR_INVALID_OBJECT;
+
+ /* Get logical drive */
+ res = find_volume(&path, &fs, 0);
+ if (res == FR_OK) {
+ dp->obj.fs = fs;
+ INIT_NAMBUF(fs);
+ res = follow_path(dp, path); /* Follow the path to the directory */
+ if (res == FR_OK) { /* Follow completed */
+ if (!(dp->fn[NSFLAG] & NS_NONAME)) { /* It is not the origin directory itself */
+ if (dp->obj.attr & AM_DIR) { /* This object is a sub-directory */
+#if FF_FS_EXFAT
+ if (fs->fs_type == FS_EXFAT) {
+ dp->obj.c_scl = dp->obj.sclust; /* Get containing directory inforamation */
+ dp->obj.c_size = ((DWORD)dp->obj.objsize & 0xFFFFFF00) | dp->obj.stat;
+ dp->obj.c_ofs = dp->blk_ofs;
+ init_alloc_info(fs, &dp->obj); /* Get object allocation info */
+ } else
+#endif
+ {
+ dp->obj.sclust = ld_clust(fs, dp->dir); /* Get object allocation info */
+ }
+ } else { /* This object is a file */
+ res = FR_NO_PATH;
+ }
+ }
+ if (res == FR_OK) {
+ dp->obj.id = fs->id;
+ res = dir_sdi(dp, 0); /* Rewind directory */
+#if FF_FS_LOCK != 0
+ if (res == FR_OK) {
+ if (dp->obj.sclust != 0) {
+ dp->obj.lockid = inc_lock(dp, 0); /* Lock the sub directory */
+ if (!dp->obj.lockid) res = FR_TOO_MANY_OPEN_FILES;
+ } else {
+ dp->obj.lockid = 0; /* Root directory need not to be locked */
+ }
+ }
+#endif
+ }
+ }
+ FREE_NAMBUF();
+ if (res == FR_NO_FILE) res = FR_NO_PATH;
+ }
+ if (res != FR_OK) dp->obj.fs = 0; /* Invalidate the directory object if function failed */
+
+ LEAVE_FF(fs, res);
+}
+
+
+
+
+/*-----------------------------------------------------------------------*/
+/* Close Directory */
+/*-----------------------------------------------------------------------*/
+
+FRESULT f_closedir (
+ DIR *dp /* Pointer to the directory object to be closed */
+)
+{
+ FRESULT res = FR_DISK_ERR;
+ FATFS *fs;
+
+
+ res = validate(&dp->obj, &fs); /* Check validity of the file object */
+ if (res == FR_OK) {
+#if FF_FS_LOCK != 0
+ if (dp->obj.lockid) res = dec_lock(dp->obj.lockid); /* Decrement sub-directory open counter */
+ if (res == FR_OK) dp->obj.fs = 0; /* Invalidate directory object */
+#else
+ dp->obj.fs = 0; /* Invalidate directory object */
+#endif
+#if FF_FS_REENTRANT
+ unlock_fs(fs, FR_OK); /* Unlock volume */
+#endif
+ }
+ return res;
+}
+
+
+
+
+/*-----------------------------------------------------------------------*/
+/* Read Directory Entries in Sequence */
+/*-----------------------------------------------------------------------*/
+
+FRESULT f_readdir (
+ DIR* dp, /* Pointer to the open directory object */
+ FILINFO* fno /* Pointer to file information to return */
+)
+{
+ FRESULT res = FR_DISK_ERR;
+ FATFS *fs;
+ DEF_NAMBUF
+
+
+ res = validate(&dp->obj, &fs); /* Check validity of the directory object */
+ if (res == FR_OK) {
+ if (!fno) {
+ res = dir_sdi(dp, 0); /* Rewind the directory object */
+ } else {
+ INIT_NAMBUF(fs);
+ res = dir_read_file(dp); /* Read an item */
+ if (res == FR_NO_FILE) res = FR_OK; /* Ignore end of directory */
+ if (res == FR_OK) { /* A valid entry is found */
+ get_fileinfo(dp, fno); /* Get the object information */
+ res = dir_next(dp, 0); /* Increment index for next */
+ if (res == FR_NO_FILE) res = FR_OK; /* Ignore end of directory now */
+ }
+ FREE_NAMBUF();
+ }
+ }
+ LEAVE_FF(fs, res);
+}
+
+
+
+#if FF_USE_FIND
+/*-----------------------------------------------------------------------*/
+/* Find Next File */
+/*-----------------------------------------------------------------------*/
+
+FRESULT f_findnext (
+ DIR* dp, /* Pointer to the open directory object */
+ FILINFO* fno /* Pointer to the file information structure */
+)
+{
+ FRESULT res = FR_DISK_ERR;
+
+
+ for (;;) {
+ res = f_readdir(dp, fno); /* Get a directory item */
+ if (res != FR_OK || !fno || !fno->fname[0]) break; /* Terminate if any error or end of directory */
+ if (pattern_matching(dp->pat, fno->fname, 0, 0)) break; /* Test for the file name */
+#if FF_USE_LFN && FF_USE_FIND == 2
+ if (pattern_matching(dp->pat, fno->altname, 0, 0)) break; /* Test for alternative name if exist */
+#endif
+ }
+ return res;
+}
+
+
+
+/*-----------------------------------------------------------------------*/
+/* Find First File */
+/*-----------------------------------------------------------------------*/
+
+FRESULT f_findfirst (
+ DIR* dp, /* Pointer to the blank directory object */
+ FILINFO* fno, /* Pointer to the file information structure */
+ const TCHAR* path, /* Pointer to the directory to open */
+ const TCHAR* pattern /* Pointer to the matching pattern */
+)
+{
+ FRESULT res = FR_DISK_ERR;
+
+
+ dp->pat = pattern; /* Save pointer to pattern string */
+ res = f_opendir(dp, path); /* Open the target directory */
+ if (res == FR_OK) {
+ res = f_findnext(dp, fno); /* Find the first item */
+ }
+ return res;
+}
+
+#endif /* FF_USE_FIND */
+
+
+
+#if FF_FS_MINIMIZE == 0
+/*-----------------------------------------------------------------------*/
+/* Get File Status */
+/*-----------------------------------------------------------------------*/
+
+FRESULT f_stat (
+ const TCHAR* path, /* Pointer to the file path */
+ FILINFO* fno /* Pointer to file information to return */
+)
+{
+ FRESULT res = FR_DISK_ERR;
+ DIR dj = {0};
+ DEF_NAMBUF
+
+
+ /* Get logical drive */
+ res = find_volume(&path, &dj.obj.fs, 0);
+ if (res == FR_OK) {
+ INIT_NAMBUF(dj.obj.fs);
+ res = follow_path(&dj, path); /* Follow the file path */
+ if (res == FR_OK) { /* Follow completed */
+ if (dj.fn[NSFLAG] & NS_NONAME) { /* It is origin directory */
+ res = FR_INVALID_NAME;
+ } else { /* Found an object */
+ if (fno) get_fileinfo(&dj, fno);
+ }
+ }
+ FREE_NAMBUF();
+ }
+
+ LEAVE_FF(dj.obj.fs, res);
+}
+
+
+
+#if !FF_FS_READONLY
+/*-----------------------------------------------------------------------*/
+/* Get Number of Free Clusters */
+/*-----------------------------------------------------------------------*/
+
+FRESULT f_getfree (
+ const TCHAR* path, /* Logical drive number */
+ DWORD* nclst, /* Pointer to a variable to return number of free clusters */
+ FATFS** fatfs /* Pointer to return pointer to corresponding filesystem object */
+)
+{
+ FRESULT res = FR_DISK_ERR;
+ FATFS *fs;
+ DWORD nfree, clst, sect, stat;
+ UINT i;
+ FFOBJID obj;
+
+
+ /* Get logical drive */
+ res = find_volume(&path, &fs, 0);
+ if (res == FR_OK) {
+ *fatfs = fs; /* Return ptr to the fs object */
+ /* If free_clst is valid, return it without full FAT scan */
+ if (fs->free_clst <= fs->n_fatent - 2) {
+ *nclst = fs->free_clst;
+ } else {
+ /* Scan FAT to obtain number of free clusters */
+ nfree = 0;
+ if (fs->fs_type == FS_FAT12) { /* FAT12: Scan bit field FAT entries */
+ clst = 2; obj.fs = fs;
+ do {
+ stat = get_fat(&obj, clst);
+ if (stat == 0xFFFFFFFF) { res = FR_DISK_ERR; break; }
+ if (stat == 1) { res = FR_INT_ERR; break; }
+ if (stat == 0) nfree++;
+ } while (++clst < fs->n_fatent);
+ } else {
+#if FF_FS_EXFAT
+ if (fs->fs_type == FS_EXFAT) { /* exFAT: Scan allocation bitmap */
+ BYTE bm;
+ UINT b;
+
+ clst = fs->n_fatent - 2; /* Number of clusters */
+ sect = fs->database; /* Assuming bitmap starts at cluster 2 */
+ i = 0; /* Offset in the sector */
+ do { /* Counts numbuer of bits with zero in the bitmap */
+ if (i == 0) {
+ res = move_window(fs, sect++);
+ if (res != FR_OK) break;
+ }
+ for (b = 8, bm = fs->win[i]; b && clst; b--, clst--) {
+ if (!(bm & 1)) nfree++;
+ bm >>= 1;
+ }
+ i = (i + 1) % SS(fs);
+ } while (clst);
+ } else
+#endif
+ { /* FAT16/32: Scan WORD/DWORD FAT entries */
+ clst = fs->n_fatent; /* Number of entries */
+ sect = fs->fatbase; /* Top of the FAT */
+ i = 0; /* Offset in the sector */
+ do { /* Counts numbuer of entries with zero in the FAT */
+ if (i == 0) {
+ res = move_window(fs, sect++);
+ if (res != FR_OK) break;
+ }
+ if (fs->fs_type == FS_FAT16) {
+ if (ld_word(fs->win + i) == 0) nfree++;
+ i += 2;
+ } else {
+ if ((ld_dword(fs->win + i) & 0x0FFFFFFF) == 0) nfree++;
+ i += 4;
+ }
+ i %= SS(fs);
+ } while (--clst);
+ }
+ }
+ *nclst = nfree; /* Return the free clusters */
+ fs->free_clst = nfree; /* Now free_clst is valid */
+ fs->fsi_flag |= 1; /* FAT32: FSInfo is to be updated */
+ }
+ }
+
+ LEAVE_FF(fs, res);
+}
+
+
+
+
+/*-----------------------------------------------------------------------*/
+/* Truncate File */
+/*-----------------------------------------------------------------------*/
+
+FRESULT f_truncate (
+ FIL* fp /* Pointer to the file object */
+)
+{
+ FRESULT res = FR_DISK_ERR;
+ FATFS *fs;
+ DWORD ncl;
+
+
+ res = validate(&fp->obj, &fs); /* Check validity of the file object */
+ if (res != FR_OK || (res = (FRESULT)fp->err) != FR_OK) LEAVE_FF(fs, res);
+ if (!(fp->flag & FA_WRITE)) LEAVE_FF(fs, FR_DENIED); /* Check access mode */
+
+ if (fp->fptr < fp->obj.objsize) { /* Process when fptr is not on the eof */
+ if (fp->fptr == 0) { /* When set file size to zero, remove entire cluster chain */
+ res = remove_chain(&fp->obj, fp->obj.sclust, 0);
+ fp->obj.sclust = 0;
+ } else { /* When truncate a part of the file, remove remaining clusters */
+ ncl = get_fat(&fp->obj, fp->clust);
+ res = FR_OK;
+ if (ncl == 0xFFFFFFFF) res = FR_DISK_ERR;
+ if (ncl == 1) res = FR_INT_ERR;
+ if (res == FR_OK && ncl < fs->n_fatent) {
+ res = remove_chain(&fp->obj, ncl, fp->clust);
+ }
+ }
+ fp->obj.objsize = fp->fptr; /* Set file size to current read/write point */
+ fp->flag |= FA_MODIFIED;
+#if !FF_FS_TINY
+ if (res == FR_OK && (fp->flag & FA_DIRTY)) {
+ if (disk_write(fs->pdrv, fp->buf, fp->sect, 1) != RES_OK) {
+ res = FR_DISK_ERR;
+ } else {
+ fp->flag &= (BYTE)~FA_DIRTY;
+ }
+ }
+#endif
+ if (res != FR_OK) ABORT(fs, res);
+ }
+
+ LEAVE_FF(fs, res);
+}
+
+
+
+
+/*-----------------------------------------------------------------------*/
+/* Delete a File/Directory */
+/*-----------------------------------------------------------------------*/
+
+FRESULT f_unlink (
+ const TCHAR* path /* Pointer to the file or directory path */
+)
+{
+ FRESULT res = FR_DISK_ERR;
+ DIR dj, sdj;
+ DWORD dclst = 0;
+ FATFS *fs;
+#if FF_FS_EXFAT
+ FFOBJID obj;
+#endif
+ DEF_NAMBUF
+
+
+ /* Get logical drive */
+ res = find_volume(&path, &fs, FA_WRITE);
+ if (res == FR_OK) {
+ dj.obj.fs = fs;
+ INIT_NAMBUF(fs);
+ res = follow_path(&dj, path); /* Follow the file path */
+ if (FF_FS_RPATH && res == FR_OK && (dj.fn[NSFLAG] & NS_DOT)) {
+ res = FR_INVALID_NAME; /* Cannot remove dot entry */
+ }
+#if FF_FS_LOCK != 0
+ if (res == FR_OK) res = chk_lock(&dj, 2); /* Check if it is an open object */
+#endif
+ if (res == FR_OK) { /* The object is accessible */
+ if (dj.fn[NSFLAG] & NS_NONAME) {
+ res = FR_INVALID_NAME; /* Cannot remove the origin directory */
+ } else {
+ if (dj.obj.attr & AM_RDO) {
+ res = FR_DENIED; /* Cannot remove R/O object */
+ }
+ }
+ if (res == FR_OK) {
+#if FF_FS_EXFAT
+ obj.fs = fs;
+ if (fs->fs_type == FS_EXFAT) {
+ init_alloc_info(fs, &obj);
+ dclst = obj.sclust;
+ } else
+#endif
+ {
+ dclst = ld_clust(fs, dj.dir);
+ }
+ if (dj.obj.attr & AM_DIR) { /* Is it a sub-directory? */
+#if FF_FS_RPATH != 0
+ if (dclst == fs->cdir) { /* Is it the current directory? */
+ res = FR_DENIED;
+ } else
+#endif
+ {
+ sdj.obj.fs = fs; /* Open the sub-directory */
+ sdj.obj.sclust = dclst;
+#if FF_FS_EXFAT
+ if (fs->fs_type == FS_EXFAT) {
+ sdj.obj.objsize = obj.objsize;
+ sdj.obj.stat = obj.stat;
+ }
+#endif
+ res = dir_sdi(&sdj, 0);
+ if (res == FR_OK) {
+ res = dir_read_file(&sdj); /* Test if the directory is empty */
+ if (res == FR_OK) res = FR_DENIED; /* Not empty? */
+ if (res == FR_NO_FILE) res = FR_OK; /* Empty? */
+ }
+ }
+ }
+ }
+ if (res == FR_OK) {
+ res = dir_remove(&dj); /* Remove the directory entry */
+ if (res == FR_OK && dclst != 0) { /* Remove the cluster chain if exist */
+#if FF_FS_EXFAT
+ res = remove_chain(&obj, dclst, 0);
+#else
+ res = remove_chain(&dj.obj, dclst, 0);
+#endif
+ }
+ if (res == FR_OK) res = sync_fs(fs);
+ }
+ }
+ FREE_NAMBUF();
+ }
+
+ LEAVE_FF(fs, res);
+}
+
+
+
+
+/*-----------------------------------------------------------------------*/
+/* Create a Directory */
+/*-----------------------------------------------------------------------*/
+
+FRESULT f_mkdir (
+ const TCHAR* path /* Pointer to the directory path */
+)
+{
+ FRESULT res = FR_DISK_ERR;
+ DIR dj;
+ FFOBJID sobj;
+ FATFS *fs;
+ BYTE *dir;
+ DWORD dcl, pcl, tm;
+ DEF_NAMBUF
+
+
+ /* Get logical drive */
+ res = find_volume(&path, &fs, FA_WRITE);
+ if (res == FR_OK) {
+ dj.obj.fs = fs;
+ INIT_NAMBUF(fs);
+ res = follow_path(&dj, path); /* Follow the file path */
+ if (res == FR_OK) res = FR_EXIST; /* Any object with same name is already existing */
+ if (FF_FS_RPATH && res == FR_NO_FILE && (dj.fn[NSFLAG] & NS_DOT)) {
+ res = FR_INVALID_NAME;
+ }
+ if (res == FR_NO_FILE) { /* Can create a new directory */
+ sobj.fs = fs; /* New object id to create a new chain */
+ dcl = create_chain(&sobj, 0); /* Allocate a cluster for the new directory */
+ res = FR_OK;
+ if (dcl == 0) res = FR_DENIED; /* No space to allocate a new cluster */
+ if (dcl == 1) res = FR_INT_ERR;
+ if (dcl == 0xFFFFFFFF) res = FR_DISK_ERR;
+ tm = GET_FATTIME();
+ if (res == FR_OK) { /* Initialize the new directory table */
+ res = dir_clear(fs, dcl); /* Clean up the new table */
+ if (res == FR_OK && (!FF_FS_EXFAT || fs->fs_type != FS_EXFAT)) { /* Create dot entries (FAT only) */
+ dir = fs->win;
+ mem_set(dir + DIR_Name, ' ', 11); /* Create "." entry */
+ dir[DIR_Name] = '.';
+ dir[DIR_Attr] = AM_DIR;
+ st_dword(dir + DIR_ModTime, tm);
+ st_clust(fs, dir, dcl);
+ mem_cpy(dir + SZDIRE, dir, SZDIRE); /* Create ".." entry */
+ dir[SZDIRE + 1] = '.'; pcl = dj.obj.sclust;
+ st_clust(fs, dir + SZDIRE, pcl);
+ fs->wflag = 1;
+ }
+ }
+ if (res == FR_OK) {
+ res = dir_register(&dj); /* Register the object to the directory */
+ }
+ if (res == FR_OK) {
+#if FF_FS_EXFAT
+ if (fs->fs_type == FS_EXFAT) { /* Initialize directory entry block */
+ st_dword(fs->dirbuf + XDIR_ModTime, tm); /* Created time */
+ st_dword(fs->dirbuf + XDIR_FstClus, dcl); /* Table start cluster */
+ st_dword(fs->dirbuf + XDIR_FileSize, (DWORD)fs->csize * SS(fs)); /* File size needs to be valid */
+ st_dword(fs->dirbuf + XDIR_ValidFileSize, (DWORD)fs->csize * SS(fs));
+ fs->dirbuf[XDIR_GenFlags] = 3; /* Initialize the object flag */
+ fs->dirbuf[XDIR_Attr] = AM_DIR; /* Attribute */
+ res = store_xdir(&dj);
+ } else
+#endif
+ {
+ dir = dj.dir;
+ st_dword(dir + DIR_ModTime, tm); /* Created time */
+ st_clust(fs, dir, dcl); /* Table start cluster */
+ dir[DIR_Attr] = AM_DIR; /* Attribute */
+ fs->wflag = 1;
+ }
+ if (res == FR_OK) {
+ res = sync_fs(fs);
+ }
+ } else {
+ (void)remove_chain(&dj.obj, dcl, 0); /* Could not register, remove cluster chain */
+ }
+ }
+ FREE_NAMBUF();
+ }
+
+ LEAVE_FF(fs, res);
+}
+
+
+
+
+/*-----------------------------------------------------------------------*/
+/* Rename a File/Directory */
+/*-----------------------------------------------------------------------*/
+
+FRESULT f_rename (
+ const TCHAR* path_old, /* Pointer to the object name to be renamed */
+ const TCHAR* path_new /* Pointer to the new name */
+)
+{
+ FRESULT res = FR_DISK_ERR;
+ DIR djo, djn;
+ FATFS *fs;
+ BYTE buf[FF_FS_EXFAT ? SZDIRE * 2 : SZDIRE], *dir;
+ DWORD dw;
+ DEF_NAMBUF
+
+
+ get_ldnumber(&path_new); /* Snip the drive number of new name off */
+ res = find_volume(&path_old, &fs, FA_WRITE); /* Get logical drive of the old object */
+ if (res == FR_OK) {
+ djo.obj.fs = fs;
+ INIT_NAMBUF(fs);
+ res = follow_path(&djo, path_old); /* Check old object */
+ if (res == FR_OK && (djo.fn[NSFLAG] & (NS_DOT | NS_NONAME))) res = FR_INVALID_NAME; /* Check validity of name */
+#if FF_FS_LOCK != 0
+ if (res == FR_OK) {
+ res = chk_lock(&djo, 2);
+ }
+#endif
+ if (res == FR_OK) { /* Object to be renamed is found */
+#if FF_FS_EXFAT
+ if (fs->fs_type == FS_EXFAT) { /* At exFAT volume */
+ BYTE nf, nn;
+ WORD nh;
+
+ mem_cpy(buf, fs->dirbuf, SZDIRE * 2); /* Save 85+C0 entry of old object */
+ mem_cpy(&djn, &djo, sizeof djo);
+ res = follow_path(&djn, path_new); /* Make sure if new object name is not in use */
+ if (res == FR_OK) { /* Is new name already in use by any other object? */
+ res = (djn.obj.sclust == djo.obj.sclust && djn.dptr == djo.dptr) ? FR_NO_FILE : FR_EXIST;
+ }
+ if (res == FR_NO_FILE) { /* It is a valid path and no name collision */
+ res = dir_register(&djn); /* Register the new entry */
+ if (res == FR_OK) {
+ nf = fs->dirbuf[XDIR_NumSec]; nn = fs->dirbuf[XDIR_NumName];
+ nh = ld_word(fs->dirbuf + XDIR_NameHash);
+ mem_cpy(fs->dirbuf, buf, SZDIRE * 2); /* Restore 85+C0 entry */
+ fs->dirbuf[XDIR_NumSec] = nf; fs->dirbuf[XDIR_NumName] = nn;
+ st_word(fs->dirbuf + XDIR_NameHash, nh);
+ if (!(fs->dirbuf[XDIR_Attr] & AM_DIR)) fs->dirbuf[XDIR_Attr] |= AM_ARC; /* Set archive attribute if it is a file */
+/* Start of critical section where an interruption can cause a cross-link */
+ res = store_xdir(&djn);
+ }
+ }
+ } else
+#endif
+ { /* At FAT/FAT32 volume */
+ mem_cpy(buf, djo.dir, SZDIRE); /* Save directory entry of the object */
+ mem_cpy(&djn, &djo, sizeof (DIR)); /* Duplicate the directory object */
+ res = follow_path(&djn, path_new); /* Make sure if new object name is not in use */
+ if (res == FR_OK) { /* Is new name already in use by any other object? */
+ res = (djn.obj.sclust == djo.obj.sclust && djn.dptr == djo.dptr) ? FR_NO_FILE : FR_EXIST;
+ }
+ if (res == FR_NO_FILE) { /* It is a valid path and no name collision */
+ res = dir_register(&djn); /* Register the new entry */
+ if (res == FR_OK) {
+ dir = djn.dir; /* Copy directory entry of the object except name */
+ mem_cpy(dir + 13, buf + 13, SZDIRE - 13);
+ dir[DIR_Attr] = buf[DIR_Attr];
+ if (!(dir[DIR_Attr] & AM_DIR)) dir[DIR_Attr] |= AM_ARC; /* Set archive attribute if it is a file */
+ fs->wflag = 1;
+ if ((dir[DIR_Attr] & AM_DIR) && djo.obj.sclust != djn.obj.sclust) { /* Update .. entry in the sub-directory if needed */
+ dw = clst2sect(fs, ld_clust(fs, dir));
+ if (dw == 0) {
+ res = FR_INT_ERR;
+ } else {
+/* Start of critical section where an interruption can cause a cross-link */
+ res = move_window(fs, dw);
+ dir = fs->win + SZDIRE * 1; /* Ptr to .. entry */
+ if (res == FR_OK && dir[1] == '.') {
+ st_clust(fs, dir, djn.obj.sclust);
+ fs->wflag = 1;
+ }
+ }
+ }
+ }
+ }
+ }
+ if (res == FR_OK) {
+ res = dir_remove(&djo); /* Remove old entry */
+ if (res == FR_OK) {
+ res = sync_fs(fs);
+ }
+ }
+/* End of the critical section */
+ }
+ FREE_NAMBUF();
+ }
+
+ LEAVE_FF(fs, res);
+}
+
+#endif /* !FF_FS_READONLY */
+#endif /* FF_FS_MINIMIZE == 0 */
+#endif /* FF_FS_MINIMIZE <= 1 */
+#endif /* FF_FS_MINIMIZE <= 2 */
+
+
+
+#if FF_USE_CHMOD && !FF_FS_READONLY
+/*-----------------------------------------------------------------------*/
+/* Change Attribute */
+/*-----------------------------------------------------------------------*/
+
+FRESULT f_chmod (
+ const TCHAR* path, /* Pointer to the file path */
+ BYTE attr, /* Attribute bits */
+ BYTE mask /* Attribute mask to change */
+)
+{
+ FRESULT res = FR_DISK_ERR;
+ DIR dj;
+ FATFS *fs;
+ DEF_NAMBUF
+
+
+ res = find_volume(&path, &fs, FA_WRITE); /* Get logical drive */
+ if (res == FR_OK) {
+ dj.obj.fs = fs;
+ INIT_NAMBUF(fs);
+ res = follow_path(&dj, path); /* Follow the file path */
+ if (res == FR_OK && (dj.fn[NSFLAG] & (NS_DOT | NS_NONAME))) res = FR_INVALID_NAME; /* Check object validity */
+ if (res == FR_OK) {
+ mask &= AM_RDO|AM_HID|AM_SYS|AM_ARC; /* Valid attribute mask */
+#if FF_FS_EXFAT
+ if (fs->fs_type == FS_EXFAT) {
+ fs->dirbuf[XDIR_Attr] = (attr & mask) | (fs->dirbuf[XDIR_Attr] & (BYTE)~mask); /* Apply attribute change */
+ res = store_xdir(&dj);
+ } else
+#endif
+ {
+ dj.dir[DIR_Attr] = (attr & mask) | (dj.dir[DIR_Attr] & (BYTE)~mask); /* Apply attribute change */
+ fs->wflag = 1;
+ }
+ if (res == FR_OK) {
+ res = sync_fs(fs);
+ }
+ }
+ FREE_NAMBUF();
+ }
+
+ LEAVE_FF(fs, res);
+}
+
+
+
+
+/*-----------------------------------------------------------------------*/
+/* Change Timestamp */
+/*-----------------------------------------------------------------------*/
+
+FRESULT f_utime (
+ const TCHAR* path, /* Pointer to the file/directory name */
+ const FILINFO* fno /* Pointer to the timestamp to be set */
+)
+{
+ FRESULT res = FR_DISK_ERR;
+ DIR dj;
+ FATFS *fs;
+ DEF_NAMBUF
+
+
+ res = find_volume(&path, &fs, FA_WRITE); /* Get logical drive */
+ if (res == FR_OK) {
+ dj.obj.fs = fs;
+ INIT_NAMBUF(fs);
+ res = follow_path(&dj, path); /* Follow the file path */
+ if (res == FR_OK && (dj.fn[NSFLAG] & (NS_DOT | NS_NONAME))) res = FR_INVALID_NAME; /* Check object validity */
+ if (res == FR_OK) {
+#if FF_FS_EXFAT
+ if (fs->fs_type == FS_EXFAT) {
+ st_dword(fs->dirbuf + XDIR_ModTime, (DWORD)fno->fdate << 16 | fno->ftime);
+ res = store_xdir(&dj);
+ } else
+#endif
+ {
+ st_dword(dj.dir + DIR_ModTime, (DWORD)fno->fdate << 16 | fno->ftime);
+ fs->wflag = 1;
+ }
+ if (res == FR_OK) {
+ res = sync_fs(fs);
+ }
+ }
+ FREE_NAMBUF();
+ }
+
+ LEAVE_FF(fs, res);
+}
+
+#endif /* FF_USE_CHMOD && !FF_FS_READONLY */
+
+
+
+#if FF_USE_LABEL
+/*-----------------------------------------------------------------------*/
+/* Get Volume Label */
+/*-----------------------------------------------------------------------*/
+
+FRESULT f_getlabel (
+ const TCHAR* path, /* Logical drive number */
+ TCHAR* label, /* Buffer to store the volume label */
+ DWORD* vsn /* Variable to store the volume serial number */
+)
+{
+ FRESULT res = FR_DISK_ERR;
+ DIR dj;
+ FATFS *fs;
+ UINT si, di;
+ WCHAR wc;
+
+ /* Get logical drive */
+ res = find_volume(&path, &fs, 0);
+
+ /* Get volume label */
+ if (res == FR_OK && label) {
+ dj.obj.fs = fs; dj.obj.sclust = 0; /* Open root directory */
+ res = dir_sdi(&dj, 0);
+ if (res == FR_OK) {
+ res = dir_read_label(&dj); /* Find a volume label entry */
+ if (res == FR_OK) {
+#if FF_FS_EXFAT
+ if (fs->fs_type == FS_EXFAT) {
+ WCHAR hs;
+
+ for (si = di = hs = 0; si < dj.dir[XDIR_NumLabel]; si++) { /* Extract volume label from 83 entry */
+ wc = ld_word(dj.dir + XDIR_Label + si * 2);
+ if (hs == 0 && IsSurrogate(wc)) { /* Is the code a surrogate? */
+ hs = wc; continue;
+ }
+ wc = put_utf((DWORD)hs << 16 | wc, &label[di], 4);
+ if (wc == 0) { di = 0; break; }
+ di += wc;
+ hs = 0;
+ }
+ if (hs != 0) di = 0; /* Broken surrogate pair? */
+ label[di] = 0;
+ } else
+#endif
+ {
+ si = di = 0; /* Extract volume label from AM_VOL entry */
+ while (si < 11) {
+ wc = dj.dir[si++];
+#if FF_USE_LFN && FF_LFN_UNICODE >= 1 /* Unicode output */
+ if (dbc_1st((BYTE)wc) && si < 11) wc = wc << 8 | dj.dir[si++]; /* Is it a DBC? */
+ wc = ff_oem2uni(wc, CODEPAGE); /* Convert it into Unicode */
+ if (wc != 0) wc = put_utf(wc, &label[di], 4); /* Put it in Unicode */
+ if (wc == 0) { di = 0; break; }
+ di += wc;
+#else /* ANSI/OEM output */
+ label[di++] = (TCHAR)wc;
+#endif
+ }
+ do { /* Truncate trailing spaces */
+ label[di] = 0;
+ if (di == 0) break;
+ } while (label[--di] == ' ');
+ }
+ }
+ }
+ if (res == FR_NO_FILE) { /* No label entry and return nul string */
+ label[0] = 0;
+ res = FR_OK;
+ }
+ }
+
+ /* Get volume serial number */
+ if (res == FR_OK && vsn) {
+ res = move_window(fs, fs->volbase);
+ if (res == FR_OK) {
+ switch (fs->fs_type) {
+ case FS_EXFAT:
+ di = BPB_VolIDEx; break;
+
+ case FS_FAT32:
+ di = BS_VolID32; break;
+
+ default:
+ di = BS_VolID;
+ }
+ *vsn = ld_dword(fs->win + di);
+ }
+ }
+
+ LEAVE_FF(fs, res);
+}
+
+
+
+#if !FF_FS_READONLY
+/*-----------------------------------------------------------------------*/
+/* Set Volume Label */
+/*-----------------------------------------------------------------------*/
+
+FRESULT f_setlabel (
+ const TCHAR* label /* Volume label to set with heading logical drive number */
+)
+{
+ FRESULT res = FR_DISK_ERR;
+ DIR dj;
+ FATFS *fs;
+ BYTE dirvn[22];
+ UINT di;
+ WCHAR wc;
+ static const char badchr[] = "+.,;=[]/\\\"*:<>\?|\x7F"; /* [0..] for FAT, [7..] for exFAT */
+#if FF_USE_LFN
+ DWORD dc;
+#endif
+
+ /* Get logical drive */
+ res = find_volume(&label, &fs, FA_WRITE);
+ if (res != FR_OK) LEAVE_FF(fs, res);
+
+#if FF_FS_EXFAT
+ if (fs->fs_type == FS_EXFAT) { /* On the exFAT volume */
+ mem_set(dirvn, 0, 22);
+ di = 0;
+ while ((UINT)*label >= ' ') { /* Create volume label */
+ dc = tchar2uni(&label); /* Get a Unicode character */
+ if (dc >= 0x10000) {
+ if (dc == 0xFFFFFFFF || di >= 10) { /* Wrong surrogate or buffer overflow */
+ dc = 0;
+ } else {
+ st_word(dirvn + di * 2, (WCHAR)(dc >> 16)); di++;
+ }
+ }
+ if (dc == 0 || chk_chr(badchr + 7, (int)dc) || di >= 11) { /* Check validity of the volume label */
+ LEAVE_FF(fs, FR_INVALID_NAME);
+ }
+ st_word(dirvn + di * 2, (WCHAR)dc); di++;
+ }
+ } else
+#endif
+ { /* On the FAT/FAT32 volume */
+ mem_set(dirvn, ' ', 11);
+ di = 0;
+ while ((UINT)*label >= ' ') { /* Create volume label */
+#if FF_USE_LFN
+ dc = tchar2uni(&label);
+ wc = (dc < 0x10000) ? ff_uni2oem(ff_wtoupper(dc), CODEPAGE) : 0;
+#else /* ANSI/OEM input */
+ wc = (BYTE)*label++;
+ if (dbc_1st((BYTE)wc)) wc = dbc_2nd((BYTE)*label) ? wc << 8 | (BYTE)*label++ : 0;
+ if (IsLower(wc)) wc -= 0x20; /* To upper ASCII characters */
+#if FF_CODE_PAGE == 0
+ if (ExCvt && wc >= 0x80) wc = ExCvt[wc - 0x80]; /* To upper extended characters (SBCS cfg) */
+#elif FF_CODE_PAGE < 900
+ if (wc >= 0x80) wc = ExCvt[wc - 0x80]; /* To upper extended characters (SBCS cfg) */
+#endif
+#endif
+ if (wc == 0 || chk_chr(badchr + 0, (int)wc) || di >= (UINT)((wc >= 0x100) ? 10 : 11)) { /* Reject invalid characters for volume label */
+ LEAVE_FF(fs, FR_INVALID_NAME);
+ }
+ if (wc >= 0x100) dirvn[di++] = (BYTE)(wc >> 8);
+ dirvn[di++] = (BYTE)wc;
+ }
+ if (dirvn[0] == DDEM) LEAVE_FF(fs, FR_INVALID_NAME); /* Reject illegal name (heading DDEM) */
+ while (di && dirvn[di - 1] == ' ') di--; /* Snip trailing spaces */
+ }
+
+ /* Set volume label */
+ dj.obj.fs = fs; dj.obj.sclust = 0; /* Open root directory */
+ res = dir_sdi(&dj, 0);
+ if (res == FR_OK) {
+ res = dir_read_label(&dj); /* Get volume label entry */
+ if (res == FR_OK) {
+ if (FF_FS_EXFAT && fs->fs_type == FS_EXFAT) {
+ dj.dir[XDIR_NumLabel] = (BYTE)di; /* Change the volume label */
+ mem_cpy(dj.dir + XDIR_Label, dirvn, 22);
+ } else {
+ if (di != 0) {
+ mem_cpy(dj.dir, dirvn, 11); /* Change the volume label */
+ } else {
+ dj.dir[DIR_Name] = DDEM; /* Remove the volume label */
+ }
+ }
+ fs->wflag = 1;
+ res = sync_fs(fs);
+ } else { /* No volume label entry or an error */
+ if (res == FR_NO_FILE) {
+ res = FR_OK;
+ if (di != 0) { /* Create a volume label entry */
+ res = dir_alloc(&dj, 1); /* Allocate an entry */
+ if (res == FR_OK) {
+ mem_set(dj.dir, 0, SZDIRE); /* Clean the entry */
+ if (FF_FS_EXFAT && fs->fs_type == FS_EXFAT) {
+ dj.dir[XDIR_Type] = 0x83; /* Create 83 entry */
+ dj.dir[XDIR_NumLabel] = (BYTE)di;
+ mem_cpy(dj.dir + XDIR_Label, dirvn, 22);
+ } else {
+ dj.dir[DIR_Attr] = AM_VOL; /* Create volume label entry */
+ mem_cpy(dj.dir, dirvn, 11);
+ }
+ fs->wflag = 1;
+ res = sync_fs(fs);
+ }
+ }
+ }
+ }
+ }
+
+ LEAVE_FF(fs, res);
+}
+
+#endif /* !FF_FS_READONLY */
+#endif /* FF_USE_LABEL */
+
+
+
+#if FF_USE_EXPAND && !FF_FS_READONLY
+/*-----------------------------------------------------------------------*/
+/* Allocate a Contiguous Blocks to the File */
+/*-----------------------------------------------------------------------*/
+
+FRESULT f_expand (
+ FIL* fp, /* Pointer to the file object */
+ FSIZE_t fsz, /* File size to be expanded to */
+ BYTE opt /* Operation mode 0:Find and prepare or 1:Find and allocate */
+)
+{
+ FRESULT res = FR_DISK_ERR;
+ FATFS *fs;
+ DWORD n, clst, stcl, scl, ncl, tcl, lclst;
+
+
+ res = validate(&fp->obj, &fs); /* Check validity of the file object */
+ if (res != FR_OK || (res = (FRESULT)fp->err) != FR_OK) LEAVE_FF(fs, res);
+ if (fsz == 0 || fp->obj.objsize != 0 || !(fp->flag & FA_WRITE)) LEAVE_FF(fs, FR_DENIED);
+#if FF_FS_EXFAT
+ if (fs->fs_type != FS_EXFAT && fsz >= 0x100000000) LEAVE_FF(fs, FR_DENIED); /* Check if in size limit */
+#endif
+ n = (DWORD)fs->csize * SS(fs); /* Cluster size */
+ tcl = (DWORD)(fsz / n) + ((fsz & (n - 1)) ? 1 : 0); /* Number of clusters required */
+ stcl = fs->last_clst; lclst = 0;
+ if (stcl < 2 || stcl >= fs->n_fatent) stcl = 2;
+
+#if FF_FS_EXFAT
+ if (fs->fs_type == FS_EXFAT) {
+ scl = find_bitmap(fs, stcl, tcl); /* Find a contiguous cluster block */
+ if (scl == 0) res = FR_DENIED; /* No contiguous cluster block was found */
+ if (scl == 0xFFFFFFFF) res = FR_DISK_ERR;
+ if (res == FR_OK) { /* A contiguous free area is found */
+ if (opt) { /* Allocate it now */
+ res = change_bitmap(fs, scl, tcl, 1); /* Mark the cluster block 'in use' */
+ lclst = scl + tcl - 1;
+ } else { /* Set it as suggested point for next allocation */
+ lclst = scl - 1;
+ }
+ }
+ } else
+#endif
+ {
+ scl = clst = stcl; ncl = 0;
+ for (;;) { /* Find a contiguous cluster block */
+ n = get_fat(&fp->obj, clst);
+ if (++clst >= fs->n_fatent) clst = 2;
+ if (n == 1) { res = FR_INT_ERR; break; }
+ if (n == 0xFFFFFFFF) { res = FR_DISK_ERR; break; }
+ if (n == 0) { /* Is it a free cluster? */
+ if (++ncl == tcl) break; /* Break if a contiguous cluster block is found */
+ } else {
+ scl = clst; ncl = 0; /* Not a free cluster */
+ }
+ if (clst == stcl) { res = FR_DENIED; break; } /* No contiguous cluster? */
+ }
+ if (res == FR_OK) { /* A contiguous free area is found */
+ if (opt) { /* Allocate it now */
+ for (clst = scl, n = tcl; n; clst++, n--) { /* Create a cluster chain on the FAT */
+ res = put_fat(fs, clst, (n == 1) ? 0xFFFFFFFF : clst + 1);
+ if (res != FR_OK) break;
+ lclst = clst;
+ }
+ } else { /* Set it as suggested point for next allocation */
+ lclst = scl - 1;
+ }
+ }
+ }
+
+ if (res == FR_OK) {
+ fs->last_clst = lclst; /* Set suggested start cluster to start next */
+ if (opt) { /* Is it allocated now? */
+ fp->obj.sclust = scl; /* Update object allocation information */
+ fp->obj.objsize = fsz;
+ if (FF_FS_EXFAT) fp->obj.stat = 2; /* Set status 'contiguous chain' */
+ fp->flag |= FA_MODIFIED;
+ if (fs->free_clst <= fs->n_fatent - 2) { /* Update FSINFO */
+ fs->free_clst -= tcl;
+ fs->fsi_flag |= 1;
+ }
+ }
+ }
+
+ LEAVE_FF(fs, res);
+}
+
+#endif /* FF_USE_EXPAND && !FF_FS_READONLY */
+
+
+
+#if FF_USE_FORWARD
+/*-----------------------------------------------------------------------*/
+/* Forward Data to the Stream Directly */
+/*-----------------------------------------------------------------------*/
+
+FRESULT f_forward (
+ FIL* fp, /* Pointer to the file object */
+ UINT (*func)(const BYTE*,UINT), /* Pointer to the streaming function */
+ UINT btf, /* Number of bytes to forward */
+ UINT* bf /* Pointer to number of bytes forwarded */
+)
+{
+ FRESULT res = FR_DISK_ERR;
+ FATFS *fs;
+ DWORD clst, sect;
+ FSIZE_t remain;
+ UINT rcnt, csect;
+ BYTE *dbuf;
+
+
+ *bf = 0; /* Clear transfer byte counter */
+ res = validate(&fp->obj, &fs); /* Check validity of the file object */
+ if (res != FR_OK || (res = (FRESULT)fp->err) != FR_OK) LEAVE_FF(fs, res);
+ if (!(fp->flag & FA_READ)) LEAVE_FF(fs, FR_DENIED); /* Check access mode */
+
+ remain = fp->obj.objsize - fp->fptr;
+ if (btf > remain) btf = (UINT)remain; /* Truncate btf by remaining bytes */
+
+ for ( ; btf && (*func)(0, 0); /* Repeat until all data transferred or stream goes busy */
+ fp->fptr += rcnt, *bf += rcnt, btf -= rcnt) {
+ csect = (UINT)(fp->fptr / SS(fs) & (fs->csize - 1)); /* Sector offset in the cluster */
+ if (fp->fptr % SS(fs) == 0) { /* On the sector boundary? */
+ if (csect == 0) { /* On the cluster boundary? */
+ clst = (fp->fptr == 0) ? /* On the top of the file? */
+ fp->obj.sclust : get_fat(&fp->obj, fp->clust);
+ if (clst <= 1) ABORT(fs, FR_INT_ERR);
+ if (clst == 0xFFFFFFFF) ABORT(fs, FR_DISK_ERR);
+ fp->clust = clst; /* Update current cluster */
+ }
+ }
+ sect = clst2sect(fs, fp->clust); /* Get current data sector */
+ if (sect == 0) ABORT(fs, FR_INT_ERR);
+ sect += csect;
+#if FF_FS_TINY
+ if (move_window(fs, sect) != FR_OK) ABORT(fs, FR_DISK_ERR); /* Move sector window to the file data */
+ dbuf = fs->win;
+#else
+ if (fp->sect != sect) { /* Fill sector cache with file data */
+#if !FF_FS_READONLY
+ if (fp->flag & FA_DIRTY) { /* Write-back dirty sector cache */
+ if (disk_write(fs->pdrv, fp->buf, fp->sect, 1) != RES_OK) ABORT(fs, FR_DISK_ERR);
+ fp->flag &= (BYTE)~FA_DIRTY;
+ }
+#endif
+ if (disk_read(fs->pdrv, fp->buf, sect, 1) != RES_OK) ABORT(fs, FR_DISK_ERR);
+ }
+ dbuf = fp->buf;
+#endif
+ fp->sect = sect;
+ rcnt = SS(fs) - (UINT)fp->fptr % SS(fs); /* Number of bytes left in the sector */
+ if (rcnt > btf) rcnt = btf; /* Clip it by btr if needed */
+ rcnt = (*func)(dbuf + ((UINT)fp->fptr % SS(fs)), rcnt); /* Forward the file data */
+ if (rcnt == 0) ABORT(fs, FR_INT_ERR);
+ }
+
+ LEAVE_FF(fs, FR_OK);
+}
+#endif /* FF_USE_FORWARD */
+
+
+
+#if FF_USE_MKFS && !FF_FS_READONLY
+/*-----------------------------------------------------------------------*/
+/* Create an FAT/exFAT volume */
+/*-----------------------------------------------------------------------*/
+
+FRESULT f_mkfs (
+ const TCHAR* path, /* Logical drive number */
+ BYTE opt, /* Format option */
+ DWORD au, /* Size of allocation unit (cluster) [byte] */
+ void* work, /* Pointer to working buffer (null: use heap memory) */
+ UINT len /* Size of working buffer [byte] */
+)
+{
+ const UINT n_fats = 1; /* Number of FATs for FAT/FAT32 volume (1 or 2) */
+ const UINT n_rootdir = 512; /* Number of root directory entries for FAT volume */
+ static const WORD cst[] = {1, 4, 16, 64, 256, 512, 0}; /* Cluster size boundary for FAT volume (4Ks unit) */
+ static const WORD cst32[] = {1, 2, 4, 8, 16, 32, 0}; /* Cluster size boundary for FAT32 volume (128Ks unit) */
+ BYTE fmt, sys, *buf, *pte, pdrv, part;
+ WORD ss; /* Sector size */
+ DWORD szb_buf, sz_buf, sz_blk, n_clst, pau, sect, nsect, n;
+ DWORD b_vol, b_fat, b_data; /* Base LBA for volume, fat, data */
+ DWORD sz_vol, sz_rsv, sz_fat, sz_dir; /* Size for volume, fat, dir, data */
+ UINT i;
+ int vol;
+ DSTATUS stat;
+#if FF_USE_TRIM || FF_FS_EXFAT
+ DWORD tbl[3];
+#endif
+
+
+ /* Check mounted drive and clear work area */
+ vol = get_ldnumber(&path); /* Get target logical drive */
+ if (vol < 0) return FR_INVALID_DRIVE;
+ if (FatFs[vol]) FatFs[vol]->fs_type = 0; /* Clear the volume if mounted */
+ pdrv = LD2PD(vol); /* Physical drive */
+ part = LD2PT(vol); /* Partition (0:create as new, 1-4:get from partition table) */
+
+ /* Check physical drive status */
+ stat = disk_initialize(pdrv);
+ if (stat & STA_NOINIT) return FR_NOT_READY;
+ if (stat & STA_PROTECT) return FR_WRITE_PROTECTED;
+ if (disk_ioctl(pdrv, GET_BLOCK_SIZE, &sz_blk) != RES_OK || !sz_blk || sz_blk > 32768 || (sz_blk & (sz_blk - 1))) sz_blk = 1; /* Erase block to align data area */
+#if FF_MAX_SS != FF_MIN_SS /* Get sector size of the medium if variable sector size cfg. */
+ if (disk_ioctl(pdrv, GET_SECTOR_SIZE, &ss) != RES_OK) return FR_DISK_ERR;
+ if (ss > FF_MAX_SS || ss < FF_MIN_SS || (ss & (ss - 1))) return FR_DISK_ERR;
+#else
+ ss = FF_MAX_SS;
+#endif
+ if ((au != 0 && au < ss) || au > 0x1000000 || (au & (au - 1))) return FR_INVALID_PARAMETER; /* Check if au is valid */
+ au /= ss; /* Cluster size in unit of sector */
+
+ /* Get working buffer */
+#if FF_USE_LFN == 3
+ if (!work) { /* Use heap memory for working buffer */
+ for (szb_buf = MAX_MALLOC, buf = 0; szb_buf >= ss && (buf = ff_memalloc(szb_buf)) == 0; szb_buf /= 2) ;
+ sz_buf = szb_buf / ss; /* Size of working buffer (sector) */
+ } else
+#endif
+ {
+ buf = (BYTE*)work; /* Working buffer */
+ sz_buf = len / ss; /* Size of working buffer (sector) */
+ szb_buf = sz_buf * ss; /* Size of working buffer (byte) */
+ }
+ if (!buf || sz_buf == 0) return FR_NOT_ENOUGH_CORE;
+
+ /* Determine where the volume to be located (b_vol, sz_vol) */
+ if (FF_MULTI_PARTITION && part != 0) {
+ /* Get partition information from partition table in the MBR */
+ if (disk_read(pdrv, buf, 0, 1) != RES_OK) LEAVE_MKFS(FR_DISK_ERR); /* Load MBR */
+ if (ld_word(buf + BS_55AA) != 0xAA55) LEAVE_MKFS(FR_MKFS_ABORTED); /* Check if MBR is valid */
+ pte = buf + (MBR_Table + (part - 1) * SZ_PTE);
+ if (pte[PTE_System] == 0) LEAVE_MKFS(FR_MKFS_ABORTED); /* No partition? */
+ b_vol = ld_dword(pte + PTE_StLba); /* Get volume start sector */
+ sz_vol = ld_dword(pte + PTE_SizLba); /* Get volume size */
+ } else {
+ /* Create a single-partition in this function */
+ if (disk_ioctl(pdrv, GET_SECTOR_COUNT, &sz_vol) != RES_OK) LEAVE_MKFS(FR_DISK_ERR);
+ b_vol = (opt & FM_SFD) ? 0 : 63; /* Volume start sector */
+ if (sz_vol < b_vol) LEAVE_MKFS(FR_MKFS_ABORTED);
+ sz_vol -= b_vol; /* Volume size */
+ }
+ if (sz_vol < 128) LEAVE_MKFS(FR_MKFS_ABORTED); /* Check if volume size is >=128s */
+
+ /* Pre-determine the FAT type */
+ do {
+ if (FF_FS_EXFAT && (opt & FM_EXFAT)) { /* exFAT possible? */
+ if ((opt & FM_ANY) == FM_EXFAT || sz_vol >= 0x4000000 || au > 128) { /* exFAT only, vol >= 64Ms or au > 128s ? */
+ fmt = FS_EXFAT; break;
+ }
+ }
+ if (au > 128) LEAVE_MKFS(FR_INVALID_PARAMETER); /* Too large au for FAT/FAT32 */
+ if (opt & FM_FAT32) { /* FAT32 possible? */
+ if ((opt & FM_ANY) == FM_FAT32 || !(opt & FM_FAT)) { /* FAT32 only or no-FAT? */
+ fmt = FS_FAT32; break;
+ }
+ }
+ if (!(opt & FM_FAT)) LEAVE_MKFS(FR_INVALID_PARAMETER); /* no-FAT? */
+ fmt = FS_FAT16;
+ } while (0);
+
+#if FF_FS_EXFAT
+ if (fmt == FS_EXFAT) { /* Create an exFAT volume */
+ DWORD szb_bit, szb_case, sum, nb, cl;
+ WCHAR ch, si;
+ UINT j, st;
+ BYTE b;
+
+ if (sz_vol < 0x1000) LEAVE_MKFS(FR_MKFS_ABORTED); /* Too small volume? */
+#if FF_USE_TRIM
+ tbl[0] = b_vol; tbl[1] = b_vol + sz_vol - 1; /* Inform the device the volume area may be erased */
+ disk_ioctl(pdrv, CTRL_TRIM, tbl);
+#endif
+ /* Determine FAT location, data location and number of clusters */
+ if (au == 0) { /* au auto-selection */
+ au = 8;
+ if (sz_vol >= 0x80000) au = 64; /* >= 512Ks */
+ if (sz_vol >= 0x4000000) au = 256; /* >= 64Ms */
+ }
+ b_fat = b_vol + 32; /* FAT start at offset 32 */
+ sz_fat = ((sz_vol / au + 2) * 4 + ss - 1) / ss; /* Number of FAT sectors */
+ b_data = (b_fat + sz_fat + sz_blk - 1) & ~(sz_blk - 1); /* Align data area to the erase block boundary */
+ if (b_data >= sz_vol / 2) LEAVE_MKFS(FR_MKFS_ABORTED); /* Too small volume? */
+ n_clst = (sz_vol - (b_data - b_vol)) / au; /* Number of clusters */
+ if (n_clst <16) LEAVE_MKFS(FR_MKFS_ABORTED); /* Too few clusters? */
+ if (n_clst > MAX_EXFAT) LEAVE_MKFS(FR_MKFS_ABORTED); /* Too many clusters? */
+
+ szb_bit = (n_clst + 7) / 8; /* Size of allocation bitmap */
+ tbl[0] = (szb_bit + au * ss - 1) / (au * ss); /* Number of allocation bitmap clusters */
+
+ /* Create a compressed up-case table */
+ sect = b_data + au * tbl[0]; /* Table start sector */
+ sum = 0; /* Table checksum to be stored in the 82 entry */
+ st = 0; si = 0; i = 0; j = 0; szb_case = 0;
+ do {
+ switch (st) {
+ case 0:
+ ch = (WCHAR)ff_wtoupper(si); /* Get an up-case char */
+ if (ch != si) {
+ si++; break; /* Store the up-case char if exist */
+ }
+ for (j = 1; (WCHAR)(si + j) && (WCHAR)(si + j) == ff_wtoupper((WCHAR)(si + j)); j++) ; /* Get run length of no-case block */
+ if (j >= 128) {
+ ch = 0xFFFF; st = 2; break; /* Compress the no-case block if run is >= 128 */
+ }
+ st = 1; /* Do not compress short run */
+ ch = si++; /* Fill the short run */
+ if (--j == 0) st = 0;
+ break;
+ case 1:
+ ch = si++; /* Fill the short run */
+ if (--j == 0) st = 0;
+ break;
+
+ default:
+ ch = (WCHAR)j; si += (WCHAR)j; /* Number of chars to skip */
+ st = 0;
+ }
+ sum = xsum32(buf[i + 0] = (BYTE)ch, sum); /* Put it into the write buffer */
+ sum = xsum32(buf[i + 1] = (BYTE)(ch >> 8), sum);
+ i += 2; szb_case += 2;
+ if (si == 0 || i == szb_buf) { /* Write buffered data when buffer full or end of process */
+ n = (i + ss - 1) / ss;
+ if (disk_write(pdrv, buf, sect, n) != RES_OK) LEAVE_MKFS(FR_DISK_ERR);
+ sect += n; i = 0;
+ }
+ } while (si);
+ tbl[1] = (szb_case + au * ss - 1) / (au * ss); /* Number of up-case table clusters */
+ tbl[2] = 1; /* Number of root dir clusters */
+
+ /* Initialize the allocation bitmap */
+ sect = b_data; nsect = (szb_bit + ss - 1) / ss; /* Start of bitmap and number of sectors */
+ nb = tbl[0] + tbl[1] + tbl[2]; /* Number of clusters in-use by system */
+ do {
+ mem_set(buf, 0, szb_buf);
+ for (i = 0; nb >= 8 && i < szb_buf; buf[i++] = 0xFF, nb -= 8) ;
+ for (b = 1; nb != 0 && i < szb_buf; buf[i] |= b, b <<= 1, nb--) ;
+ n = (nsect > sz_buf) ? sz_buf : nsect; /* Write the buffered data */
+ if (disk_write(pdrv, buf, sect, n) != RES_OK) LEAVE_MKFS(FR_DISK_ERR);
+ sect += n; nsect -= n;
+ } while (nsect);
+
+ /* Initialize the FAT */
+ sect = b_fat; nsect = sz_fat; /* Start of FAT and number of FAT sectors */
+ j = nb = cl = 0;
+ do {
+ mem_set(buf, 0, szb_buf); i = 0; /* Clear work area and reset write index */
+ if (cl == 0) { /* Set entry 0 and 1 */
+ st_dword(buf + i, 0xFFFFFFF8); i += 4; cl++;
+ st_dword(buf + i, 0xFFFFFFFF); i += 4; cl++;
+ }
+ do { /* Create chains of bitmap, up-case and root dir */
+ while (nb != 0 && i < szb_buf) { /* Create a chain */
+ st_dword(buf + i, (nb > 1) ? cl + 1 : 0xFFFFFFFF);
+ i += 4; cl++; nb--;
+ }
+ if (nb == 0 && j < 3) nb = tbl[j++]; /* Next chain */
+ } while (nb != 0 && i < szb_buf);
+ n = (nsect > sz_buf) ? sz_buf : nsect; /* Write the buffered data */
+ if (disk_write(pdrv, buf, sect, n) != RES_OK) LEAVE_MKFS(FR_DISK_ERR);
+ sect += n; nsect -= n;
+ } while (nsect);
+
+ /* Initialize the root directory */
+ mem_set(buf, 0, szb_buf);
+ buf[SZDIRE * 0 + 0] = 0x83; /* 83 entry (volume label) */
+ buf[SZDIRE * 1 + 0] = 0x81; /* 81 entry (allocation bitmap) */
+ st_dword(buf + SZDIRE * 1 + 20, 2); /* cluster */
+ st_dword(buf + SZDIRE * 1 + 24, szb_bit); /* size */
+ buf[SZDIRE * 2 + 0] = 0x82; /* 82 entry (up-case table) */
+ st_dword(buf + SZDIRE * 2 + 4, sum); /* sum */
+ st_dword(buf + SZDIRE * 2 + 20, 2 + tbl[0]); /* cluster */
+ st_dword(buf + SZDIRE * 2 + 24, szb_case); /* size */
+ sect = b_data + au * (tbl[0] + tbl[1]); nsect = au; /* Start of the root directory and number of sectors */
+ do { /* Fill root directory sectors */
+ n = (nsect > sz_buf) ? sz_buf : nsect;
+ if (disk_write(pdrv, buf, sect, n) != RES_OK) LEAVE_MKFS(FR_DISK_ERR);
+ mem_set(buf, 0, ss);
+ sect += n; nsect -= n;
+ } while (nsect);
+
+ /* Create two set of the exFAT VBR blocks */
+ sect = b_vol;
+ for (n = 0; n < 2; n++) {
+ /* Main record (+0) */
+ mem_set(buf, 0, ss);
+ mem_cpy(buf + BS_JmpBoot, "\xEB\x76\x90" "EXFAT ", 11); /* Boot jump code (x86), OEM name */
+ st_dword(buf + BPB_VolOfsEx, b_vol); /* Volume offset in the physical drive [sector] */
+ st_dword(buf + BPB_TotSecEx, sz_vol); /* Volume size [sector] */
+ st_dword(buf + BPB_FatOfsEx, b_fat - b_vol); /* FAT offset [sector] */
+ st_dword(buf + BPB_FatSzEx, sz_fat); /* FAT size [sector] */
+ st_dword(buf + BPB_DataOfsEx, b_data - b_vol); /* Data offset [sector] */
+ st_dword(buf + BPB_NumClusEx, n_clst); /* Number of clusters */
+ st_dword(buf + BPB_RootClusEx, 2 + tbl[0] + tbl[1]); /* Root dir cluster # */
+ st_dword(buf + BPB_VolIDEx, GET_FATTIME()); /* VSN */
+ st_word(buf + BPB_FSVerEx, 0x100); /* Filesystem version (1.00) */
+ for (buf[BPB_BytsPerSecEx] = 0, i = ss; i >>= 1; buf[BPB_BytsPerSecEx]++) ; /* Log2 of sector size [byte] */
+ for (buf[BPB_SecPerClusEx] = 0, i = au; i >>= 1; buf[BPB_SecPerClusEx]++) ; /* Log2 of cluster size [sector] */
+ buf[BPB_NumFATsEx] = 1; /* Number of FATs */
+ buf[BPB_DrvNumEx] = 0x80; /* Drive number (for int13) */
+ st_word(buf + BS_BootCodeEx, 0xFEEB); /* Boot code (x86) */
+ st_word(buf + BS_55AA, 0xAA55); /* Signature (placed here regardless of sector size) */
+ for (i = sum = 0; i < ss; i++) { /* VBR checksum */
+ if (i != BPB_VolFlagEx && i != BPB_VolFlagEx + 1 && i != BPB_PercInUseEx) sum = xsum32(buf[i], sum);
+ }
+ if (disk_write(pdrv, buf, sect++, 1) != RES_OK) LEAVE_MKFS(FR_DISK_ERR);
+ /* Extended bootstrap record (+1..+8) */
+ mem_set(buf, 0, ss);
+ st_word(buf + ss - 2, 0xAA55); /* Signature (placed at end of sector) */
+ for (j = 1; j < 9; j++) {
+ for (i = 0; i < ss; sum = xsum32(buf[i++], sum)) ; /* VBR checksum */
+ if (disk_write(pdrv, buf, sect++, 1) != RES_OK) LEAVE_MKFS(FR_DISK_ERR);
+ }
+ /* OEM/Reserved record (+9..+10) */
+ mem_set(buf, 0, ss);
+ for ( ; j < 11; j++) {
+ for (i = 0; i < ss; sum = xsum32(buf[i++], sum)) ; /* VBR checksum */
+ if (disk_write(pdrv, buf, sect++, 1) != RES_OK) LEAVE_MKFS(FR_DISK_ERR);
+ }
+ /* Sum record (+11) */
+ for (i = 0; i < ss; i += 4) st_dword(buf + i, sum); /* Fill with checksum value */
+ if (disk_write(pdrv, buf, sect++, 1) != RES_OK) LEAVE_MKFS(FR_DISK_ERR);
+ }
+
+ } else
+#endif /* FF_FS_EXFAT */
+ { /* Create an FAT/FAT32 volume */
+ do {
+ pau = au;
+ /* Pre-determine number of clusters and FAT sub-type */
+ if (fmt == FS_FAT32) { /* FAT32 volume */
+ if (pau == 0) { /* au auto-selection */
+ n = sz_vol / 0x20000; /* Volume size in unit of 128KS */
+ for (i = 0, pau = 1; cst32[i] && cst32[i] <= n; i++, pau <<= 1) ; /* Get from table */
+ }
+ n_clst = sz_vol / pau; /* Number of clusters */
+ sz_fat = (n_clst * 4 + 8 + ss - 1) / ss; /* FAT size [sector] */
+ sz_rsv = 32; /* Number of reserved sectors */
+ sz_dir = 0; /* No static directory */
+ if (n_clst <= MAX_FAT16 || n_clst > MAX_FAT32) LEAVE_MKFS(FR_MKFS_ABORTED);
+ } else { /* FAT volume */
+ if (pau == 0) { /* au auto-selection */
+ n = sz_vol / 0x1000; /* Volume size in unit of 4KS */
+ for (i = 0, pau = 1; cst[i] && cst[i] <= n; i++, pau <<= 1) ; /* Get from table */
+ }
+ n_clst = sz_vol / pau;
+ if (n_clst > MAX_FAT12) {
+ n = n_clst * 2 + 4; /* FAT size [byte] */
+ } else {
+ fmt = FS_FAT12;
+ n = (n_clst * 3 + 1) / 2 + 3; /* FAT size [byte] */
+ }
+ sz_fat = (n + ss - 1) / ss; /* FAT size [sector] */
+ sz_rsv = 1; /* Number of reserved sectors */
+ sz_dir = (DWORD)n_rootdir * SZDIRE / ss; /* Rootdir size [sector] */
+ }
+ b_fat = b_vol + sz_rsv; /* FAT base */
+ b_data = b_fat + sz_fat * n_fats + sz_dir; /* Data base */
+
+ /* Align data base to erase block boundary (for flash memory media) */
+ n = ((b_data + sz_blk - 1) & ~(sz_blk - 1)) - b_data; /* Next nearest erase block from current data base */
+ if (fmt == FS_FAT32) { /* FAT32: Move FAT base */
+ sz_rsv += n; b_fat += n;
+ } else { /* FAT: Expand FAT size */
+ sz_fat += n / n_fats;
+ }
+
+ /* Determine number of clusters and final check of validity of the FAT sub-type */
+ if (sz_vol < b_data + pau * 16 - b_vol) LEAVE_MKFS(FR_MKFS_ABORTED); /* Too small volume */
+ n_clst = (sz_vol - sz_rsv - sz_fat * n_fats - sz_dir) / pau;
+ if (fmt == FS_FAT32) {
+ if (n_clst <= MAX_FAT16) { /* Too few clusters for FAT32 */
+ if (au == 0 && (au = pau / 2) != 0) continue; /* Adjust cluster size and retry */
+ LEAVE_MKFS(FR_MKFS_ABORTED);
+ }
+ }
+ if (fmt == FS_FAT16) {
+ if (n_clst > MAX_FAT16) { /* Too many clusters for FAT16 */
+ if (au == 0 && (pau * 2) <= 64) {
+ au = pau * 2; continue; /* Adjust cluster size and retry */
+ }
+ if ((opt & FM_FAT32)) {
+ fmt = FS_FAT32; continue; /* Switch type to FAT32 and retry */
+ }
+ if (au == 0 && (au = pau * 2) <= 128) continue; /* Adjust cluster size and retry */
+ LEAVE_MKFS(FR_MKFS_ABORTED);
+ }
+ if (n_clst <= MAX_FAT12) { /* Too few clusters for FAT16 */
+ if (au == 0 && (au = pau * 2) <= 128) continue; /* Adjust cluster size and retry */
+ LEAVE_MKFS(FR_MKFS_ABORTED);
+ }
+ }
+ if (fmt == FS_FAT12 && n_clst > MAX_FAT12) LEAVE_MKFS(FR_MKFS_ABORTED); /* Too many clusters for FAT12 */
+
+ /* Ok, it is the valid cluster configuration */
+ break;
+ } while (1);
+
+#if FF_USE_TRIM
+ tbl[0] = b_vol; tbl[1] = b_vol + sz_vol - 1; /* Inform the device the volume area can be erased */
+ disk_ioctl(pdrv, CTRL_TRIM, tbl);
+#endif
+ /* Create FAT VBR */
+ mem_set(buf, 0, ss);
+ mem_cpy(buf + BS_JmpBoot, "\xEB\xFE\x90" "MSDOS5.0", 11);/* Boot jump code (x86), OEM name */
+ st_word(buf + BPB_BytsPerSec, ss); /* Sector size [byte] */
+ buf[BPB_SecPerClus] = (BYTE)pau; /* Cluster size [sector] */
+ st_word(buf + BPB_RsvdSecCnt, (WORD)sz_rsv); /* Size of reserved area */
+ buf[BPB_NumFATs] = (BYTE)n_fats; /* Number of FATs */
+ st_word(buf + BPB_RootEntCnt, (WORD)((fmt == FS_FAT32) ? 0 : n_rootdir)); /* Number of root directory entries */
+ if (sz_vol < 0x10000) {
+ st_word(buf + BPB_TotSec16, (WORD)sz_vol); /* Volume size in 16-bit LBA */
+ } else {
+ st_dword(buf + BPB_TotSec32, sz_vol); /* Volume size in 32-bit LBA */
+ }
+ buf[BPB_Media] = 0xF8; /* Media descriptor byte */
+ st_word(buf + BPB_SecPerTrk, 63); /* Number of sectors per track (for int13) */
+ st_word(buf + BPB_NumHeads, 255); /* Number of heads (for int13) */
+ st_dword(buf + BPB_HiddSec, b_vol); /* Volume offset in the physical drive [sector] */
+ if (fmt == FS_FAT32) {
+ st_dword(buf + BS_VolID32, GET_FATTIME()); /* VSN */
+ st_dword(buf + BPB_FATSz32, sz_fat); /* FAT size [sector] */
+ st_dword(buf + BPB_RootClus32, 2); /* Root directory cluster # (2) */
+ st_word(buf + BPB_FSInfo32, 1); /* Offset of FSINFO sector (VBR + 1) */
+ st_word(buf + BPB_BkBootSec32, 6); /* Offset of backup VBR (VBR + 6) */
+ buf[BS_DrvNum32] = 0x80; /* Drive number (for int13) */
+ buf[BS_BootSig32] = 0x29; /* Extended boot signature */
+ mem_cpy(buf + BS_VolLab32, "NO NAME " "FAT32 ", 19); /* Volume label, FAT signature */
+ } else {
+ st_dword(buf + BS_VolID, GET_FATTIME()); /* VSN */
+ st_word(buf + BPB_FATSz16, (WORD)sz_fat); /* FAT size [sector] */
+ buf[BS_DrvNum] = 0x80; /* Drive number (for int13) */
+ buf[BS_BootSig] = 0x29; /* Extended boot signature */
+ mem_cpy(buf + BS_VolLab, "NO NAME " "FAT ", 19); /* Volume label, FAT signature */
+ }
+ st_word(buf + BS_55AA, 0xAA55); /* Signature (offset is fixed here regardless of sector size) */
+ if (disk_write(pdrv, buf, b_vol, 1) != RES_OK) LEAVE_MKFS(FR_DISK_ERR); /* Write it to the VBR sector */
+
+ /* Create FSINFO record if needed */
+ if (fmt == FS_FAT32) {
+ (void)disk_write(pdrv, buf, b_vol + 6, 1); /* Write backup VBR (VBR + 6) */
+ mem_set(buf, 0, ss);
+ st_dword(buf + FSI_LeadSig, 0x41615252);
+ st_dword(buf + FSI_StrucSig, 0x61417272);
+ st_dword(buf + FSI_Free_Count, n_clst - 1); /* Number of free clusters */
+ st_dword(buf + FSI_Nxt_Free, 2); /* Last allocated cluster# */
+ st_word(buf + BS_55AA, 0xAA55);
+ (void)disk_write(pdrv, buf, b_vol + 7, 1); /* Write backup FSINFO (VBR + 7) */
+ (void)disk_write(pdrv, buf, b_vol + 1, 1); /* Write original FSINFO (VBR + 1) */
+ }
+
+ /* Initialize FAT area */
+ mem_set(buf, 0, (UINT)szb_buf);
+ sect = b_fat; /* FAT start sector */
+ for (i = 0; i < n_fats; i++) { /* Initialize FATs each */
+ if (fmt == FS_FAT32) {
+ st_dword(buf + 0, 0xFFFFFFF8); /* Entry 0 */
+ st_dword(buf + 4, 0xFFFFFFFF); /* Entry 1 */
+ st_dword(buf + 8, 0x0FFFFFFF); /* Entry 2 (root directory) */
+ } else {
+ st_dword(buf + 0, (fmt == FS_FAT12) ? 0xFFFFF8 : 0xFFFFFFF8); /* Entry 0 and 1 */
+ }
+ nsect = sz_fat; /* Number of FAT sectors */
+ do { /* Fill FAT sectors */
+ n = (nsect > sz_buf) ? sz_buf : nsect;
+ if (disk_write(pdrv, buf, sect, (UINT)n) != RES_OK) LEAVE_MKFS(FR_DISK_ERR);
+ mem_set(buf, 0, ss);
+ sect += n; nsect -= n;
+ } while (nsect);
+ }
+
+ /* Initialize root directory (fill with zero) */
+ nsect = (fmt == FS_FAT32) ? pau : sz_dir; /* Number of root directory sectors */
+ do {
+ n = (nsect > sz_buf) ? sz_buf : nsect;
+ if (disk_write(pdrv, buf, sect, (UINT)n) != RES_OK) LEAVE_MKFS(FR_DISK_ERR);
+ sect += n; nsect -= n;
+ } while (nsect);
+ }
+
+ /* Determine system ID in the partition table */
+ if (FF_FS_EXFAT && fmt == FS_EXFAT) {
+ sys = 0x07; /* HPFS/NTFS/exFAT */
+ } else {
+ if (fmt == FS_FAT32) {
+ sys = 0x0C; /* FAT32X */
+ } else {
+ if (sz_vol >= 0x10000) {
+ sys = 0x06; /* FAT12/16 (large) */
+ } else {
+ sys = (fmt == FS_FAT16) ? 0x04 : 0x01; /* FAT16 : FAT12 */
+ }
+ }
+ }
+
+ /* Update partition information */
+ if (FF_MULTI_PARTITION && part != 0) { /* Created in the existing partition */
+ /* Update system ID in the partition table */
+ if (disk_read(pdrv, buf, 0, 1) != RES_OK) LEAVE_MKFS(FR_DISK_ERR); /* Read the MBR */
+ buf[MBR_Table + (part - 1) * SZ_PTE + PTE_System] = sys; /* Set system ID */
+ if (disk_write(pdrv, buf, 0, 1) != RES_OK) LEAVE_MKFS(FR_DISK_ERR); /* Write it back to the MBR */
+ } else { /* Created as a new single partition */
+ if (!(opt & FM_SFD)) { /* Create partition table if in FDISK format */
+ mem_set(buf, 0, ss);
+ st_word(buf + BS_55AA, 0xAA55); /* MBR signature */
+ pte = buf + MBR_Table; /* Create partition table for single partition in the drive */
+ pte[PTE_Boot] = 0; /* Boot indicator */
+ pte[PTE_StHead] = 1; /* Start head */
+ pte[PTE_StSec] = 1; /* Start sector */
+ pte[PTE_StCyl] = 0; /* Start cylinder */
+ pte[PTE_System] = sys; /* System type */
+ n = (b_vol + sz_vol) / (63 * 255); /* (End CHS may be invalid) */
+ pte[PTE_EdHead] = 254; /* End head */
+ pte[PTE_EdSec] = (BYTE)(((n >> 2) & 0xC0) | 63); /* End sector */
+ pte[PTE_EdCyl] = (BYTE)n; /* End cylinder */
+ st_dword(pte + PTE_StLba, b_vol); /* Start offset in LBA */
+ st_dword(pte + PTE_SizLba, sz_vol); /* Size in sectors */
+ if (disk_write(pdrv, buf, 0, 1) != RES_OK) LEAVE_MKFS(FR_DISK_ERR); /* Write it to the MBR */
+ }
+ }
+
+ if (disk_ioctl(pdrv, CTRL_SYNC, 0) != RES_OK) LEAVE_MKFS(FR_DISK_ERR);
+
+ LEAVE_MKFS(FR_OK);
+}
+
+
+
+#if FF_MULTI_PARTITION
+/*-----------------------------------------------------------------------*/
+/* Create Partition Table on the Physical Drive */
+/*-----------------------------------------------------------------------*/
+
+FRESULT f_fdisk (
+ BYTE pdrv, /* Physical drive number */
+ const DWORD* szt, /* Pointer to the size table for each partitions */
+ void* work /* Pointer to the working buffer (null: use heap memory) */
+)
+{
+ UINT i, n, sz_cyl, tot_cyl, b_cyl, e_cyl, p_cyl;
+ BYTE s_hd, e_hd, *p, *buf = (BYTE*)work;
+ DSTATUS stat;
+ DWORD sz_disk, sz_part, s_part;
+ FRESULT res = FR_DISK_ERR;
+
+
+ stat = disk_initialize(pdrv);
+ if (stat & STA_NOINIT) return FR_NOT_READY;
+ if (stat & STA_PROTECT) return FR_WRITE_PROTECTED;
+ if (disk_ioctl(pdrv, GET_SECTOR_COUNT, &sz_disk)) return FR_DISK_ERR;
+
+ buf = (BYTE*)work;
+#if FF_USE_LFN == 3
+ if (!buf) buf = ff_memalloc(FF_MAX_SS); /* Use heap memory for working buffer */
+#endif
+ if (!buf) return FR_NOT_ENOUGH_CORE;
+
+ /* Determine the CHS without any consideration of the drive geometry */
+ for (n = 16; n < 256 && sz_disk / n / 63 > 1024; n *= 2) ;
+ if (n == 256) n--;
+ e_hd = (BYTE)(n - 1);
+ sz_cyl = 63 * n;
+ tot_cyl = sz_disk / sz_cyl;
+
+ /* Create partition table */
+ mem_set(buf, 0, FF_MAX_SS);
+ p = buf + MBR_Table; b_cyl = 0;
+ for (i = 0; i < 4; i++, p += SZ_PTE) {
+ p_cyl = (szt[i] <= 100U) ? (DWORD)tot_cyl * szt[i] / 100 : szt[i] / sz_cyl; /* Number of cylinders */
+ if (p_cyl == 0) continue;
+ s_part = (DWORD)sz_cyl * b_cyl;
+ sz_part = (DWORD)sz_cyl * p_cyl;
+ if (i == 0) { /* Exclude first track of cylinder 0 */
+ s_hd = 1;
+ s_part += 63; sz_part -= 63;
+ } else {
+ s_hd = 0;
+ }
+ e_cyl = b_cyl + p_cyl - 1; /* End cylinder */
+ if (e_cyl >= tot_cyl) LEAVE_MKFS(FR_INVALID_PARAMETER);
+
+ /* Set partition table */
+ p[1] = s_hd; /* Start head */
+ p[2] = (BYTE)(((b_cyl >> 2) & 0xC0) | 1); /* Start sector */
+ p[3] = (BYTE)b_cyl; /* Start cylinder */
+ p[4] = 0x07; /* System type (temporary setting) */
+ p[5] = e_hd; /* End head */
+ p[6] = (BYTE)(((e_cyl >> 2) & 0xC0) | 63); /* End sector */
+ p[7] = (BYTE)e_cyl; /* End cylinder */
+ st_dword(p + 8, s_part); /* Start sector in LBA */
+ st_dword(p + 12, sz_part); /* Number of sectors */
+
+ /* Next partition */
+ b_cyl += p_cyl;
+ }
+ st_word(p, 0xAA55); /* MBR signature (always at offset 510) */
+
+ /* Write it to the MBR */
+ res = (disk_write(pdrv, buf, 0, 1) == RES_OK && disk_ioctl(pdrv, CTRL_SYNC, 0) == RES_OK) ? FR_OK : FR_DISK_ERR;
+ LEAVE_MKFS(res);
+}
+
+#endif /* FF_MULTI_PARTITION */
+#endif /* FF_USE_MKFS && !FF_FS_READONLY */
+
+
+
+
+#if FF_USE_STRFUNC
+#if FF_USE_LFN && FF_LFN_UNICODE && (FF_STRF_ENCODE < 0 || FF_STRF_ENCODE > 3)
+#error Wrong FF_STRF_ENCODE setting
+#endif
+/*-----------------------------------------------------------------------*/
+/* Get a String from the File */
+/*-----------------------------------------------------------------------*/
+
+TCHAR* f_gets (
+ TCHAR* buff, /* Pointer to the string buffer to read */
+ int len, /* Size of string buffer (items) */
+ FIL* fp /* Pointer to the file object */
+)
+{
+ int nc = 0;
+ TCHAR *p = buff;
+ BYTE s[4];
+ UINT rc;
+ DWORD dc;
+#if FF_USE_LFN && FF_LFN_UNICODE && FF_STRF_ENCODE <= 2
+ WCHAR wc;
+#endif
+#if FF_USE_LFN && FF_LFN_UNICODE && FF_STRF_ENCODE == 3
+ UINT ct;
+#endif
+
+#if FF_USE_LFN && FF_LFN_UNICODE /* With code conversion (Unicode API) */
+ /* Make a room for the character and terminator */
+ if (FF_LFN_UNICODE == 1) len -= (FF_STRF_ENCODE == 0) ? 1 : 2;
+ if (FF_LFN_UNICODE == 2) len -= (FF_STRF_ENCODE == 0) ? 3 : 4;
+ if (FF_LFN_UNICODE == 3) len -= 1;
+ while (nc < len) {
+#if FF_STRF_ENCODE == 0 /* Read a character in ANSI/OEM */
+ f_read(fp, s, 1, &rc);
+ if (rc != 1) break;
+ wc = s[0];
+ if (dbc_1st((BYTE)wc)) {
+ f_read(fp, s, 1, &rc);
+ if (rc != 1 || !dbc_2nd(s[0])) continue;
+ wc = wc << 8 | s[0];
+ }
+ dc = ff_oem2uni(wc, CODEPAGE);
+ if (dc == 0) continue;
+#elif FF_STRF_ENCODE == 1 || FF_STRF_ENCODE == 2 /* Read a character in UTF-16LE/BE */
+ f_read(fp, s, 2, &rc);
+ if (rc != 2) break;
+ dc = (FF_STRF_ENCODE == 1) ? ld_word(s) : s[0] << 8 | s[1];
+ if (IsSurrogateL(dc)) continue;
+ if (IsSurrogateH(dc)) {
+ f_read(fp, s, 2, &rc);
+ if (rc != 2) break;
+ wc = (FF_STRF_ENCODE == 1) ? ld_word(s) : s[0] << 8 | s[1];
+ if (!IsSurrogateL(wc)) continue;
+ dc = ((dc & 0x3FF) + 0x40) << 10 | (wc & 0x3FF);
+ }
+#else /* Read a character in UTF-8 */
+ f_read(fp, s, 1, &rc);
+ if (rc != 1) break;
+ dc = s[0];
+ if (dc >= 0x80) { /* Multi-byte character? */
+ ct = 0;
+ if ((dc & 0xE0) == 0xC0) { dc &= 0x1F; ct = 1; } /* 2-byte? */
+ if ((dc & 0xF0) == 0xE0) { dc &= 0x0F; ct = 2; } /* 3-byte? */
+ if ((dc & 0xF8) == 0xF0) { dc &= 0x07; ct = 3; } /* 4-byte? */
+ if (ct == 0) continue;
+ f_read(fp, s, ct, &rc); /* Get trailing bytes */
+ if (rc != ct) break;
+ rc = 0;
+ do { /* Merge trailing bytes */
+ if ((s[rc] & 0xC0) != 0x80) break;
+ dc = dc << 6 | (s[rc] & 0x3F);
+ } while (++rc < ct);
+ if (rc != ct || dc < 0x80 || IsSurrogate(dc) || dc >= 0x110000) continue; /* Wrong encoding? */
+ }
+#endif
+ if (FF_USE_STRFUNC == 2 && dc == '\r') continue; /* Strip \r off if needed */
+#if FF_LFN_UNICODE == 1 || FF_LFN_UNICODE == 3 /* Output it in UTF-16/32 encoding */
+ if (FF_LFN_UNICODE == 1 && dc >= 0x10000) { /* Out of BMP at UTF-16? */
+ *p++ = (TCHAR)(0xD800 | ((dc >> 10) - 0x40)); nc++; /* Make and output high surrogate */
+ dc = 0xDC00 | (dc & 0x3FF); /* Make low surrogate */
+ }
+ *p++ = (TCHAR)dc; nc++;
+ if (dc == '\n') break; /* End of line? */
+#elif FF_LFN_UNICODE == 2 /* Output it in UTF-8 encoding */
+ if (dc < 0x80) { /* 1-byte */
+ *p++ = (TCHAR)dc;
+ nc++;
+ if (dc == '\n') break; /* End of line? */
+ } else {
+ if (dc < 0x800) { /* 2-byte */
+ *p++ = (TCHAR)(0xC0 | (dc >> 6 & 0x1F));
+ *p++ = (TCHAR)(0x80 | (dc >> 0 & 0x3F));
+ nc += 2;
+ } else {
+ if (dc < 0x10000) { /* 3-byte */
+ *p++ = (TCHAR)(0xE0 | (dc >> 12 & 0x0F));
+ *p++ = (TCHAR)(0x80 | (dc >> 6 & 0x3F));
+ *p++ = (TCHAR)(0x80 | (dc >> 0 & 0x3F));
+ nc += 3;
+ } else { /* 4-byte */
+ *p++ = (TCHAR)(0xF0 | (dc >> 18 & 0x07));
+ *p++ = (TCHAR)(0x80 | (dc >> 12 & 0x3F));
+ *p++ = (TCHAR)(0x80 | (dc >> 6 & 0x3F));
+ *p++ = (TCHAR)(0x80 | (dc >> 0 & 0x3F));
+ nc += 4;
+ }
+ }
+ }
+#endif
+ }
+
+#else /* Byte-by-byte without any conversion (ANSI/OEM API) */
+ len -= 1; /* Make a room for the terminator */
+ while (nc < len) {
+ f_read(fp, s, 1, &rc);
+ if (rc != 1) break;
+ dc = s[0];
+ if (FF_USE_STRFUNC == 2 && dc == '\r') continue;
+ *p++ = (TCHAR)dc; nc++;
+ if (dc == '\n') break;
+ }
+#endif
+
+ *p = 0; /* Terminate the string */
+ return nc ? buff : 0; /* When no data read due to EOF or error, return with error. */
+}
+
+
+
+
+#if !FF_FS_READONLY
+#include <stdarg.h>
+/*-----------------------------------------------------------------------*/
+/* Put a Character to the File */
+/*-----------------------------------------------------------------------*/
+
+typedef struct { /* Putchar output buffer and work area */
+ FIL *fp; /* Ptr to the writing file */
+ int idx, nchr; /* Write index of buf[] (-1:error), number of encoding units written */
+#if FF_USE_LFN && FF_LFN_UNICODE == 1
+ WCHAR hs;
+#elif FF_USE_LFN && FF_LFN_UNICODE == 2
+ BYTE bs[4];
+ UINT wi, ct;
+#endif
+ BYTE buf[64]; /* Write buffer */
+} putbuff;
+
+
+static
+void putc_bfd ( /* Buffered write with code conversion */
+ putbuff* pb,
+ TCHAR c
+)
+{
+ UINT n;
+ int i, nc;
+#if FF_USE_LFN && FF_LFN_UNICODE
+ WCHAR hs, wc;
+#if FF_LFN_UNICODE == 2
+ DWORD dc;
+ TCHAR *tp;
+#endif
+#endif
+
+ if (FF_USE_STRFUNC == 2 && c == '\n') { /* LF -> CRLF conversion */
+ putc_bfd(pb, '\r');
+ }
+
+ i = pb->idx; /* Write index of pb->buf[] */
+ if (i < 0) return;
+ nc = pb->nchr; /* Write unit counter */
+
+#if FF_USE_LFN && FF_LFN_UNICODE
+#if FF_LFN_UNICODE == 1 /* UTF-16 input */
+ if (IsSurrogateH(c)) {
+ pb->hs = c; return;
+ }
+ hs = pb->hs; pb->hs = 0;
+ if (hs != 0) {
+ if (!IsSurrogateL(c)) hs = 0;
+ } else {
+ if (IsSurrogateL(c)) return;
+ }
+ wc = c;
+#elif FF_LFN_UNICODE == 2 /* UTF-8 input */
+ for (;;) {
+ if (pb->ct == 0) { /* Out of multi-byte sequence? */
+ pb->bs[pb->wi = 0] = (BYTE)c; /* Save 1st byte */
+ if ((BYTE)c < 0x80) break; /* 1-byte? */
+ if (((BYTE)c & 0xE0) == 0xC0) pb->ct = 1; /* 2-byte? */
+ if (((BYTE)c & 0xF0) == 0xE0) pb->ct = 2; /* 3-byte? */
+ if (((BYTE)c & 0xF1) == 0xF0) pb->ct = 3; /* 4-byte? */
+ return;
+ } else { /* In the multi-byte sequence */
+ if (((BYTE)c & 0xC0) != 0x80) { /* Broken sequence? */
+ pb->ct = 0; continue;
+ }
+ pb->bs[++pb->wi] = (BYTE)c; /* Save the trailing byte */
+ if (--pb->ct == 0) break; /* End of multi-byte sequence? */
+ return;
+ }
+ }
+ tp = (TCHAR*)pb->bs;
+ dc = tchar2uni(&tp); /* UTF-8 ==> UTF-16 */
+ if (dc == 0xFFFFFFFF) return;
+ wc = (WCHAR)dc;
+ hs = (WCHAR)(dc >> 16);
+#elif FF_LFN_UNICODE == 3 /* UTF-32 input */
+ if (IsSurrogate(c) || c >= 0x110000) return;
+ if (c >= 0x10000) {
+ hs = (WCHAR)(0xD800 | ((c >> 10) - 0x40)); /* Make high surrogate */
+ wc = 0xDC00 | (c & 0x3FF); /* Make low surrogate */
+ } else {
+ hs = 0;
+ wc = (WCHAR)c;
+ }
+#endif
+
+#if FF_STRF_ENCODE == 1 /* Write a character in UTF-16LE */
+ if (hs != 0) {
+ st_word(&pb->buf[i], hs);
+ i += 2;
+ nc++;
+ }
+ st_word(&pb->buf[i], wc);
+ i += 2;
+#elif FF_STRF_ENCODE == 2 /* Write a character in UTF-16BE */
+ if (hs != 0) {
+ pb->buf[i++] = (BYTE)(hs >> 8);
+ pb->buf[i++] = (BYTE)hs;
+ nc++;
+ }
+ pb->buf[i++] = (BYTE)(wc >> 8);
+ pb->buf[i++] = (BYTE)wc;
+#elif FF_STRF_ENCODE == 3 /* Write it in UTF-8 */
+ if (hs != 0) { /* 4-byte */
+ nc += 3;
+ hs = (hs & 0x3FF) + 0x40;
+ pb->buf[i++] = (BYTE)(0xF0 | hs >> 8);
+ pb->buf[i++] = (BYTE)(0x80 | (hs >> 2 & 0x3F));
+ pb->buf[i++] = (BYTE)(0x80 | (hs & 3) << 4 | (wc >> 6 & 0x0F));
+ pb->buf[i++] = (BYTE)(0x80 | (wc & 0x3F));
+ } else {
+ if (wc < 0x80) { /* 1-byte */
+ pb->buf[i++] = (BYTE)wc;
+ } else {
+ if (wc < 0x800) { /* 2-byte */
+ nc += 1;
+ pb->buf[i++] = (BYTE)(0xC0 | wc >> 6);
+ } else { /* 3-byte */
+ nc += 2;
+ pb->buf[i++] = (BYTE)(0xE0 | wc >> 12);
+ pb->buf[i++] = (BYTE)(0x80 | (wc >> 6 & 0x3F));
+ }
+ pb->buf[i++] = (BYTE)(0x80 | (wc & 0x3F));
+ }
+ }
+#else /* Write it in ANSI/OEM */
+ if (hs != 0) return;
+ wc = ff_uni2oem(wc, CODEPAGE); /* UTF-16 ==> ANSI/OEM */
+ if (wc == 0) return;;
+ if (wc >= 0x100) {
+ pb->buf[i++] = (BYTE)(wc >> 8); nc++;
+ }
+ pb->buf[i++] = (BYTE)wc;
+#endif
+
+#else /* ANSI/OEM input (without re-encode) */
+ pb->buf[i++] = (BYTE)c;
+#endif
+
+ if (i >= (int)(sizeof pb->buf) - 4) { /* Write buffered characters to the file */
+ f_write(pb->fp, pb->buf, (UINT)i, &n);
+ i = (n == (UINT)i) ? 0 : -1;
+ }
+ pb->idx = i;
+ pb->nchr = nc + 1;
+}
+
+
+static
+int putc_flush ( /* Flush left characters in the buffer */
+ putbuff* pb
+)
+{
+ UINT nw;
+
+ if ( pb->idx >= 0 /* Flush buffered characters to the file */
+ && f_write(pb->fp, pb->buf, (UINT)pb->idx, &nw) == FR_OK
+ && (UINT)pb->idx == nw) return pb->nchr;
+ return EOF;
+}
+
+
+static
+void putc_init ( /* Initialize write buffer */
+ putbuff* pb,
+ FIL* fp
+)
+{
+ mem_set(pb, 0, sizeof (putbuff));
+ pb->fp = fp;
+}
+
+
+
+int f_putc (
+ TCHAR c, /* A character to be output */
+ FIL* fp /* Pointer to the file object */
+)
+{
+ putbuff pb;
+
+
+ putc_init(&pb, fp);
+ putc_bfd(&pb, c); /* Put the character */
+ return putc_flush(&pb);
+}
+
+
+
+
+/*-----------------------------------------------------------------------*/
+/* Put a String to the File */
+/*-----------------------------------------------------------------------*/
+
+int f_puts (
+ const TCHAR* str, /* Pointer to the string to be output */
+ FIL* fp /* Pointer to the file object */
+)
+{
+ putbuff pb;
+
+
+ putc_init(&pb, fp);
+ while (*str) putc_bfd(&pb, *str++); /* Put the string */
+ return putc_flush(&pb);
+}
+
+
+
+
+/*-----------------------------------------------------------------------*/
+/* Put a Formatted String to the File */
+/*-----------------------------------------------------------------------*/
+
+int f_printf (
+ FIL* fp, /* Pointer to the file object */
+ const TCHAR* fmt, /* Pointer to the format string */
+ ... /* Optional arguments... */
+)
+{
+ va_list arp;
+ putbuff pb;
+ BYTE f, r;
+ UINT i, j, w;
+ DWORD v;
+ TCHAR c, d, str[32], *p;
+
+
+ putc_init(&pb, fp);
+
+ va_start(arp, fmt);
+
+ for (;;) {
+ c = *fmt++;
+ if (c == 0) break; /* End of string */
+ if (c != '%') { /* Non escape character */
+ putc_bfd(&pb, c);
+ continue;
+ }
+ w = f = 0;
+ c = *fmt++;
+ if (c == '0') { /* Flag: '0' padding */
+ f = 1; c = *fmt++;
+ } else {
+ if (c == '-') { /* Flag: left justified */
+ f = 2; c = *fmt++;
+ }
+ }
+ if (c == '*') { /* Minimum width by argument */
+ w = va_arg(arp, int);
+ c = *fmt++;
+ } else {
+ while (IsDigit(c)) { /* Minimum width */
+ w = w * 10 + c - '0';
+ c = *fmt++;
+ }
+ }
+ if (c == 'l' || c == 'L') { /* Type prefix: Size is long int */
+ f |= 4; c = *fmt++;
+ }
+ if (c == 0) break;
+ d = c;
+ if (IsLower(d)) d -= 0x20;
+ switch (d) { /* Atgument type is... */
+ case 'S' : /* String */
+ p = va_arg(arp, TCHAR*);
+ for (j = 0; p[j]; j++) ;
+ if (!(f & 2)) { /* Right padded */
+ while (j++ < w) putc_bfd(&pb, ' ') ;
+ }
+ while (*p) putc_bfd(&pb, *p++) ; /* String body */
+ while (j++ < w) putc_bfd(&pb, ' ') ; /* Left padded */
+ continue;
+
+ case 'C' : /* Character */
+ putc_bfd(&pb, (TCHAR)va_arg(arp, int)); continue;
+
+ case 'B' : /* Unsigned binary */
+ r = 2; break;
+
+ case 'O' : /* Unsigned octal */
+ r = 8; break;
+
+ case 'D' : /* Signed decimal */
+ case 'U' : /* Unsigned decimal */
+ r = 10; break;
+
+ case 'X' : /* Unsigned hexdecimal */
+ r = 16; break;
+
+ default: /* Unknown type (pass-through) */
+ putc_bfd(&pb, c); continue;
+ }
+
+ /* Get an argument and put it in numeral */
+ v = (f & 4) ? (DWORD)va_arg(arp, long) : ((d == 'D') ? (DWORD)(long)va_arg(arp, int) : (DWORD)va_arg(arp, unsigned int));
+ if (d == 'D' && (v & 0x80000000)) {
+ v = 0 - v;
+ f |= 8;
+ }
+ i = 0;
+ do {
+ d = (TCHAR)(v % r); v /= r;
+ if (d > 9) d += (c == 'x') ? 0x27 : 0x07;
+ str[i++] = d + '0';
+ } while (v && i < sizeof str / sizeof *str);
+ if (f & 8) str[i++] = '-';
+ j = i; d = (f & 1) ? '0' : ' ';
+ if (!(f & 2)) {
+ while (j++ < w) putc_bfd(&pb, d); /* Right pad */
+ }
+ do {
+ putc_bfd(&pb, str[--i]); /* Number body */
+ } while (i);
+ while (j++ < w) putc_bfd(&pb, d); /* Left pad */
+ }
+
+ va_end(arp);
+
+ return putc_flush(&pb);
+}
+
+#endif /* !FF_FS_READONLY */
+#endif /* FF_USE_STRFUNC */
+
+
+
+#if FF_CODE_PAGE == 0
+/*-----------------------------------------------------------------------*/
+/* Set Active Codepage for the Path Name */
+/*-----------------------------------------------------------------------*/
+
+FRESULT f_setcp (
+ WORD cp /* Value to be set as active code page */
+)
+{
+ static const WORD validcp[] = { 437, 720, 737, 771, 775, 850, 852, 857, 860, 861, 862, 863, 864, 865, 866, 869, 932, 936, 949, 950, 0};
+ static const BYTE* const tables[] = {Ct437, Ct720, Ct737, Ct771, Ct775, Ct850, Ct852, Ct857, Ct860, Ct861, Ct862, Ct863, Ct864, Ct865, Ct866, Ct869, Dc932, Dc936, Dc949, Dc950, 0};
+ UINT i;
+
+
+ for (i = 0; validcp[i] != 0 && validcp[i] != cp; i++) ; /* Find the code page */
+ if (validcp[i] != cp) return FR_INVALID_PARAMETER; /* Not found? */
+
+ CodePage = cp;
+ if (cp >= 900) { /* DBCS */
+ ExCvt = 0;
+ DbcTbl = tables[i];
+ } else { /* SBCS */
+ ExCvt = tables[i];
+ DbcTbl = 0;
+ }
+ return FR_OK;
+}
+#endif /* FF_CODE_PAGE == 0 */
+
+#endif /* (defined FILE_SYSTEM_INTERFACE_SD) || (defined FILE_SYSTEM_INTERFACE_RAM) */
diff --git a/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/xilffs_v4_2/src/ffsystem.c b/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/xilffs_v4_2/src/ffsystem.c
new file mode 100644
index 0000000..9df330f
--- /dev/null
+++ b/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/xilffs_v4_2/src/ffsystem.c
@@ -0,0 +1,171 @@
+/*------------------------------------------------------------------------*/
+/* Sample Code of OS Dependent Functions for FatFs */
+/* (C)ChaN, 2017 */
+/*------------------------------------------------------------------------*/
+
+
+#include "ff.h"
+
+
+
+#if FF_USE_LFN == 3 /* Dynamic memory allocation */
+
+/*------------------------------------------------------------------------*/
+/* Allocate a memory block */
+/*------------------------------------------------------------------------*/
+
+void* ff_memalloc ( /* Returns pointer to the allocated memory block (null on not enough core) */
+ UINT msize /* Number of bytes to allocate */
+)
+{
+ return malloc(msize); /* Allocate a new memory block with POSIX API */
+}
+
+
+/*------------------------------------------------------------------------*/
+/* Free a memory block */
+/*------------------------------------------------------------------------*/
+
+void ff_memfree (
+ void* mblock /* Pointer to the memory block to free (nothing to do for null) */
+)
+{
+ free(mblock); /* Free the memory block with POSIX API */
+}
+
+#endif
+
+
+
+#if FF_FS_REENTRANT /* Mutal exclusion */
+
+/*------------------------------------------------------------------------*/
+/* Create a Synchronization Object */
+/*------------------------------------------------------------------------*/
+/* This function is called in f_mount() function to create a new
+/ synchronization object for the volume, such as semaphore and mutex.
+/ When a 0 is returned, the f_mount() function fails with FR_INT_ERR.
+*/
+
+//const osMutexDef_t Mutex[FF_VOLUMES]; /* CMSIS-RTOS */
+
+
+int ff_cre_syncobj ( /* 1:Function succeeded, 0:Could not create the sync object */
+ BYTE vol, /* Corresponding volume (logical drive number) */
+ FF_SYNC_t* sobj /* Pointer to return the created sync object */
+)
+{
+ /* Win32 */
+ *sobj = CreateMutex(NULL, FALSE, NULL);
+ return (int)(*sobj != INVALID_HANDLE_VALUE);
+
+ /* uITRON */
+// T_CSEM csem = {TA_TPRI,1,1};
+// *sobj = acre_sem(&csem);
+// return (int)(*sobj > 0);
+
+ /* uC/OS-II */
+// OS_ERR err;
+// *sobj = OSMutexCreate(0, &err);
+// return (int)(err == OS_NO_ERR);
+
+ /* FreeRTOS */
+// *sobj = xSemaphoreCreateMutex();
+// return (int)(*sobj != NULL);
+
+ /* CMSIS-RTOS */
+// *sobj = osMutexCreate(Mutex + vol);
+// return (int)(*sobj != NULL);
+}
+
+
+/*------------------------------------------------------------------------*/
+/* Delete a Synchronization Object */
+/*------------------------------------------------------------------------*/
+/* This function is called in f_mount() function to delete a synchronization
+/ object that created with ff_cre_syncobj() function. When a 0 is returned,
+/ the f_mount() function fails with FR_INT_ERR.
+*/
+
+int ff_del_syncobj ( /* 1:Function succeeded, 0:Could not delete due to an error */
+ FF_SYNC_t sobj /* Sync object tied to the logical drive to be deleted */
+)
+{
+ /* Win32 */
+ return (int)CloseHandle(sobj);
+
+ /* uITRON */
+// return (int)(del_sem(sobj) == E_OK);
+
+ /* uC/OS-II */
+// OS_ERR err;
+// OSMutexDel(sobj, OS_DEL_ALWAYS, &err);
+// return (int)(err == OS_NO_ERR);
+
+ /* FreeRTOS */
+// vSemaphoreDelete(sobj);
+// return 1;
+
+ /* CMSIS-RTOS */
+// return (int)(osMutexDelete(sobj) == osOK);
+}
+
+
+/*------------------------------------------------------------------------*/
+/* Request Grant to Access the Volume */
+/*------------------------------------------------------------------------*/
+/* This function is called on entering file functions to lock the volume.
+/ When a 0 is returned, the file function fails with FR_TIMEOUT.
+*/
+
+int ff_req_grant ( /* 1:Got a grant to access the volume, 0:Could not get a grant */
+ FF_SYNC_t sobj /* Sync object to wait */
+)
+{
+ /* Win32 */
+ return (int)(WaitForSingleObject(sobj, FF_FS_TIMEOUT) == WAIT_OBJECT_0);
+
+ /* uITRON */
+// return (int)(wai_sem(sobj) == E_OK);
+
+ /* uC/OS-II */
+// OS_ERR err;
+// OSMutexPend(sobj, FF_FS_TIMEOUT, &err));
+// return (int)(err == OS_NO_ERR);
+
+ /* FreeRTOS */
+// return (int)(xSemaphoreTake(sobj, FF_FS_TIMEOUT) == pdTRUE);
+
+ /* CMSIS-RTOS */
+// return (int)(osMutexWait(sobj, FF_FS_TIMEOUT) == osOK);
+}
+
+
+/*------------------------------------------------------------------------*/
+/* Release Grant to Access the Volume */
+/*------------------------------------------------------------------------*/
+/* This function is called on leaving file functions to unlock the volume.
+*/
+
+void ff_rel_grant (
+ FF_SYNC_t sobj /* Sync object to be signaled */
+)
+{
+ /* Win32 */
+ ReleaseMutex(sobj);
+
+ /* uITRON */
+// sig_sem(sobj);
+
+ /* uC/OS-II */
+// OSMutexPost(sobj);
+
+ /* FreeRTOS */
+// xSemaphoreGive(sobj);
+
+ /* CMSIS-RTOS */
+// osMutexRelease(sobj);
+}
+
+#endif
+
diff --git a/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/xilffs_v4_2/src/ffunicode.c b/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/xilffs_v4_2/src/ffunicode.c
new file mode 100644
index 0000000..9a5d37e
--- /dev/null
+++ b/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/xilffs_v4_2/src/ffunicode.c
@@ -0,0 +1,15597 @@
+/*------------------------------------------------------------------------*/
+/* Unicode handling functions for FatFs R0.13b */
+/*------------------------------------------------------------------------*/
+/* This module will occupy a huge memory in the .const section when the /
+/ FatFs is configured for LFN with DBCS. If the system has any Unicode /
+/ utilitiy for the code conversion, this module should be modified to use /
+/ that function to avoid silly memory consumption. /
+/-------------------------------------------------------------------------*/
+/*
+/ Copyright (C) 2018, ChaN, all right reserved.
+/
+/ FatFs module is an open source software. Redistribution and use of FatFs in
+/ source and binary forms, with or without modification, are permitted provided
+/ that the following condition is met:
+/
+/ 1. Redistributions of source code must retain the above copyright notice,
+/ this condition and the following disclaimer.
+/
+/ This software is provided by the copyright holder and contributors "AS IS"
+/ and any warranties related to this software are DISCLAIMED.
+/ The copyright owner or contributors be NOT LIABLE for any damages caused
+/ by use of this software.
+*/
+
+
+#include "ff.h"
+
+#if FF_USE_LFN /* This module is blanked when non-LFN configuration */
+
+#if FF_DEFINED != 63463 /* Revision ID */
+#error Wrong include file (ff.h).
+#endif
+
+#define MERGE2(a, b) a ## b
+#define CVTBL(tbl, cp) MERGE2(tbl, cp)
+
+
+/*------------------------------------------------------------------------*/
+/* Code Conversion Tables */
+/*------------------------------------------------------------------------*/
+
+#if FF_CODE_PAGE == 932 || FF_CODE_PAGE == 0 /* Japanese */
+static const WCHAR uni2oem932[] = { /* Unicode --> Shift_JIS pairs */
+ 0x00A7, 0x8198, 0x00A8, 0x814E, 0x00B0, 0x818B, 0x00B1, 0x817D, 0x00B4, 0x814C, 0x00B6, 0x81F7, 0x00D7, 0x817E, 0x00F7, 0x8180,
+ 0x0391, 0x839F, 0x0392, 0x83A0, 0x0393, 0x83A1, 0x0394, 0x83A2, 0x0395, 0x83A3, 0x0396, 0x83A4, 0x0397, 0x83A5, 0x0398, 0x83A6,
+ 0x0399, 0x83A7, 0x039A, 0x83A8, 0x039B, 0x83A9, 0x039C, 0x83AA, 0x039D, 0x83AB, 0x039E, 0x83AC, 0x039F, 0x83AD, 0x03A0, 0x83AE,
+ 0x03A1, 0x83AF, 0x03A3, 0x83B0, 0x03A4, 0x83B1, 0x03A5, 0x83B2, 0x03A6, 0x83B3, 0x03A7, 0x83B4, 0x03A8, 0x83B5, 0x03A9, 0x83B6,
+ 0x03B1, 0x83BF, 0x03B2, 0x83C0, 0x03B3, 0x83C1, 0x03B4, 0x83C2, 0x03B5, 0x83C3, 0x03B6, 0x83C4, 0x03B7, 0x83C5, 0x03B8, 0x83C6,
+ 0x03B9, 0x83C7, 0x03BA, 0x83C8, 0x03BB, 0x83C9, 0x03BC, 0x83CA, 0x03BD, 0x83CB, 0x03BE, 0x83CC, 0x03BF, 0x83CD, 0x03C0, 0x83CE,
+ 0x03C1, 0x83CF, 0x03C3, 0x83D0, 0x03C4, 0x83D1, 0x03C5, 0x83D2, 0x03C6, 0x83D3, 0x03C7, 0x83D4, 0x03C8, 0x83D5, 0x03C9, 0x83D6,
+ 0x0401, 0x8446, 0x0410, 0x8440, 0x0411, 0x8441, 0x0412, 0x8442, 0x0413, 0x8443, 0x0414, 0x8444, 0x0415, 0x8445, 0x0416, 0x8447,
+ 0x0417, 0x8448, 0x0418, 0x8449, 0x0419, 0x844A, 0x041A, 0x844B, 0x041B, 0x844C, 0x041C, 0x844D, 0x041D, 0x844E, 0x041E, 0x844F,
+ 0x041F, 0x8450, 0x0420, 0x8451, 0x0421, 0x8452, 0x0422, 0x8453, 0x0423, 0x8454, 0x0424, 0x8455, 0x0425, 0x8456, 0x0426, 0x8457,
+ 0x0427, 0x8458, 0x0428, 0x8459, 0x0429, 0x845A, 0x042A, 0x845B, 0x042B, 0x845C, 0x042C, 0x845D, 0x042D, 0x845E, 0x042E, 0x845F,
+ 0x042F, 0x8460, 0x0430, 0x8470, 0x0431, 0x8471, 0x0432, 0x8472, 0x0433, 0x8473, 0x0434, 0x8474, 0x0435, 0x8475, 0x0436, 0x8477,
+ 0x0437, 0x8478, 0x0438, 0x8479, 0x0439, 0x847A, 0x043A, 0x847B, 0x043B, 0x847C, 0x043C, 0x847D, 0x043D, 0x847E, 0x043E, 0x8480,
+ 0x043F, 0x8481, 0x0440, 0x8482, 0x0441, 0x8483, 0x0442, 0x8484, 0x0443, 0x8485, 0x0444, 0x8486, 0x0445, 0x8487, 0x0446, 0x8488,
+ 0x0447, 0x8489, 0x0448, 0x848A, 0x0449, 0x848B, 0x044A, 0x848C, 0x044B, 0x848D, 0x044C, 0x848E, 0x044D, 0x848F, 0x044E, 0x8490,
+ 0x044F, 0x8491, 0x0451, 0x8476, 0x2010, 0x815D, 0x2015, 0x815C, 0x2018, 0x8165, 0x2019, 0x8166, 0x201C, 0x8167, 0x201D, 0x8168,
+ 0x2020, 0x81F5, 0x2021, 0x81F6, 0x2025, 0x8164, 0x2026, 0x8163, 0x2030, 0x81F1, 0x2032, 0x818C, 0x2033, 0x818D, 0x203B, 0x81A6,
+ 0x2103, 0x818E, 0x2116, 0x8782, 0x2121, 0x8784, 0x212B, 0x81F0, 0x2160, 0x8754, 0x2161, 0x8755, 0x2162, 0x8756, 0x2163, 0x8757,
+ 0x2164, 0x8758, 0x2165, 0x8759, 0x2166, 0x875A, 0x2167, 0x875B, 0x2168, 0x875C, 0x2169, 0x875D, 0x2170, 0xFA40, 0x2171, 0xFA41,
+ 0x2172, 0xFA42, 0x2173, 0xFA43, 0x2174, 0xFA44, 0x2175, 0xFA45, 0x2176, 0xFA46, 0x2177, 0xFA47, 0x2178, 0xFA48, 0x2179, 0xFA49,
+ 0x2190, 0x81A9, 0x2191, 0x81AA, 0x2192, 0x81A8, 0x2193, 0x81AB, 0x21D2, 0x81CB, 0x21D4, 0x81CC, 0x2200, 0x81CD, 0x2202, 0x81DD,
+ 0x2203, 0x81CE, 0x2207, 0x81DE, 0x2208, 0x81B8, 0x220B, 0x81B9, 0x2211, 0x8794, 0x221A, 0x81E3, 0x221D, 0x81E5, 0x221E, 0x8187,
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+ 0x9D60, 0x8D94, 0x9D61, 0x96B7, 0x9D64, 0xEA42, 0x9D6B, 0xFC48, 0x9D6C, 0x9651, 0x9D6F, 0xEA4A, 0x9D70, 0xFC47, 0x9D72, 0xEA46,
+ 0x9D7A, 0xEA4B, 0x9D87, 0xEA48, 0x9D89, 0xEA47, 0x9D8F, 0x8C7B, 0x9D9A, 0xEA4C, 0x9DA4, 0xEA4D, 0x9DA9, 0xEA4E, 0x9DAB, 0xEA49,
+ 0x9DAF, 0xE9F2, 0x9DB2, 0xEA4F, 0x9DB4, 0x92DF, 0x9DB8, 0xEA53, 0x9DBA, 0xEA54, 0x9DBB, 0xEA52, 0x9DC1, 0xEA51, 0x9DC2, 0xEA57,
+ 0x9DC4, 0xEA50, 0x9DC6, 0xEA55, 0x9DCF, 0xEA56, 0x9DD3, 0xEA59, 0x9DD9, 0xEA58, 0x9DE6, 0xEA5B, 0x9DED, 0xEA5C, 0x9DEF, 0xEA5D,
+ 0x9DF2, 0x9868, 0x9DF8, 0xEA5A, 0x9DF9, 0x91E9, 0x9DFA, 0x8DEB, 0x9DFD, 0xEA5E, 0x9E19, 0xFC4A, 0x9E1A, 0xEA5F, 0x9E1B, 0xEA60,
+ 0x9E1E, 0xEA61, 0x9E75, 0xEA62, 0x9E78, 0x8CB2, 0x9E79, 0xEA63, 0x9E7D, 0xEA64, 0x9E7F, 0x8EAD, 0x9E81, 0xEA65, 0x9E88, 0xEA66,
+ 0x9E8B, 0xEA67, 0x9E8C, 0xEA68, 0x9E91, 0xEA6B, 0x9E92, 0xEA69, 0x9E93, 0x985B, 0x9E95, 0xEA6A, 0x9E97, 0x97ED, 0x9E9D, 0xEA6C,
+ 0x9E9F, 0x97D9, 0x9EA5, 0xEA6D, 0x9EA6, 0x949E, 0x9EA9, 0xEA6E, 0x9EAA, 0xEA70, 0x9EAD, 0xEA71, 0x9EB8, 0xEA6F, 0x9EB9, 0x8D8D,
+ 0x9EBA, 0x96CB, 0x9EBB, 0x9683, 0x9EBC, 0x9BF5, 0x9EBE, 0x9F80, 0x9EBF, 0x969B, 0x9EC4, 0x89A9, 0x9ECC, 0xEA73, 0x9ECD, 0x8B6F,
+ 0x9ECE, 0xEA74, 0x9ECF, 0xEA75, 0x9ED0, 0xEA76, 0x9ED1, 0xFC4B, 0x9ED2, 0x8D95, 0x9ED4, 0xEA77, 0x9ED8, 0xE0D2, 0x9ED9, 0x96D9,
+ 0x9EDB, 0x91E1, 0x9EDC, 0xEA78, 0x9EDD, 0xEA7A, 0x9EDE, 0xEA79, 0x9EE0, 0xEA7B, 0x9EE5, 0xEA7C, 0x9EE8, 0xEA7D, 0x9EEF, 0xEA7E,
+ 0x9EF4, 0xEA80, 0x9EF6, 0xEA81, 0x9EF7, 0xEA82, 0x9EF9, 0xEA83, 0x9EFB, 0xEA84, 0x9EFC, 0xEA85, 0x9EFD, 0xEA86, 0x9F07, 0xEA87,
+ 0x9F08, 0xEA88, 0x9F0E, 0x9343, 0x9F13, 0x8CDB, 0x9F15, 0xEA8A, 0x9F20, 0x916C, 0x9F21, 0xEA8B, 0x9F2C, 0xEA8C, 0x9F3B, 0x9540,
+ 0x9F3E, 0xEA8D, 0x9F4A, 0xEA8E, 0x9F4B, 0xE256, 0x9F4E, 0xE6D8, 0x9F4F, 0xE8EB, 0x9F52, 0xEA8F, 0x9F54, 0xEA90, 0x9F5F, 0xEA92,
+ 0x9F60, 0xEA93, 0x9F61, 0xEA94, 0x9F62, 0x97EE, 0x9F63, 0xEA91, 0x9F66, 0xEA95, 0x9F67, 0xEA96, 0x9F6A, 0xEA98, 0x9F6C, 0xEA97,
+ 0x9F72, 0xEA9A, 0x9F76, 0xEA9B, 0x9F77, 0xEA99, 0x9F8D, 0x97B4, 0x9F95, 0xEA9C, 0x9F9C, 0xEA9D, 0x9F9D, 0xE273, 0x9FA0, 0xEA9E,
+ 0xF929, 0xFAE0, 0xF9DC, 0xFBE9, 0xFA0E, 0xFA90, 0xFA0F, 0xFA9B, 0xFA10, 0xFA9C, 0xFA11, 0xFAB1, 0xFA12, 0xFAD8, 0xFA13, 0xFAE8,
+ 0xFA14, 0xFAEA, 0xFA15, 0xFB58, 0xFA16, 0xFB5E, 0xFA17, 0xFB75, 0xFA18, 0xFB7D, 0xFA19, 0xFB7E, 0xFA1A, 0xFB80, 0xFA1B, 0xFB82,
+ 0xFA1C, 0xFB86, 0xFA1D, 0xFB89, 0xFA1E, 0xFB92, 0xFA1F, 0xFB9D, 0xFA20, 0xFB9F, 0xFA21, 0xFBA0, 0xFA22, 0xFBA9, 0xFA23, 0xFBB1,
+ 0xFA24, 0xFBB3, 0xFA25, 0xFBB4, 0xFA26, 0xFBB7, 0xFA27, 0xFBD3, 0xFA28, 0xFBDA, 0xFA29, 0xFBEA, 0xFA2A, 0xFBF6, 0xFA2B, 0xFBF7,
+ 0xFA2C, 0xFBF9, 0xFA2D, 0xFC49, 0xFF01, 0x8149, 0xFF02, 0xFA57, 0xFF03, 0x8194, 0xFF04, 0x8190, 0xFF05, 0x8193, 0xFF06, 0x8195,
+ 0xFF07, 0xFA56, 0xFF08, 0x8169, 0xFF09, 0x816A, 0xFF0A, 0x8196, 0xFF0B, 0x817B, 0xFF0C, 0x8143, 0xFF0D, 0x817C, 0xFF0E, 0x8144,
+ 0xFF0F, 0x815E, 0xFF10, 0x824F, 0xFF11, 0x8250, 0xFF12, 0x8251, 0xFF13, 0x8252, 0xFF14, 0x8253, 0xFF15, 0x8254, 0xFF16, 0x8255,
+ 0xFF17, 0x8256, 0xFF18, 0x8257, 0xFF19, 0x8258, 0xFF1A, 0x8146, 0xFF1B, 0x8147, 0xFF1C, 0x8183, 0xFF1D, 0x8181, 0xFF1E, 0x8184,
+ 0xFF1F, 0x8148, 0xFF20, 0x8197, 0xFF21, 0x8260, 0xFF22, 0x8261, 0xFF23, 0x8262, 0xFF24, 0x8263, 0xFF25, 0x8264, 0xFF26, 0x8265,
+ 0xFF27, 0x8266, 0xFF28, 0x8267, 0xFF29, 0x8268, 0xFF2A, 0x8269, 0xFF2B, 0x826A, 0xFF2C, 0x826B, 0xFF2D, 0x826C, 0xFF2E, 0x826D,
+ 0xFF2F, 0x826E, 0xFF30, 0x826F, 0xFF31, 0x8270, 0xFF32, 0x8271, 0xFF33, 0x8272, 0xFF34, 0x8273, 0xFF35, 0x8274, 0xFF36, 0x8275,
+ 0xFF37, 0x8276, 0xFF38, 0x8277, 0xFF39, 0x8278, 0xFF3A, 0x8279, 0xFF3B, 0x816D, 0xFF3C, 0x815F, 0xFF3D, 0x816E, 0xFF3E, 0x814F,
+ 0xFF3F, 0x8151, 0xFF40, 0x814D, 0xFF41, 0x8281, 0xFF42, 0x8282, 0xFF43, 0x8283, 0xFF44, 0x8284, 0xFF45, 0x8285, 0xFF46, 0x8286,
+ 0xFF47, 0x8287, 0xFF48, 0x8288, 0xFF49, 0x8289, 0xFF4A, 0x828A, 0xFF4B, 0x828B, 0xFF4C, 0x828C, 0xFF4D, 0x828D, 0xFF4E, 0x828E,
+ 0xFF4F, 0x828F, 0xFF50, 0x8290, 0xFF51, 0x8291, 0xFF52, 0x8292, 0xFF53, 0x8293, 0xFF54, 0x8294, 0xFF55, 0x8295, 0xFF56, 0x8296,
+ 0xFF57, 0x8297, 0xFF58, 0x8298, 0xFF59, 0x8299, 0xFF5A, 0x829A, 0xFF5B, 0x816F, 0xFF5C, 0x8162, 0xFF5D, 0x8170, 0xFF5E, 0x8160,
+ 0xFF61, 0x00A1, 0xFF62, 0x00A2, 0xFF63, 0x00A3, 0xFF64, 0x00A4, 0xFF65, 0x00A5, 0xFF66, 0x00A6, 0xFF67, 0x00A7, 0xFF68, 0x00A8,
+ 0xFF69, 0x00A9, 0xFF6A, 0x00AA, 0xFF6B, 0x00AB, 0xFF6C, 0x00AC, 0xFF6D, 0x00AD, 0xFF6E, 0x00AE, 0xFF6F, 0x00AF, 0xFF70, 0x00B0,
+ 0xFF71, 0x00B1, 0xFF72, 0x00B2, 0xFF73, 0x00B3, 0xFF74, 0x00B4, 0xFF75, 0x00B5, 0xFF76, 0x00B6, 0xFF77, 0x00B7, 0xFF78, 0x00B8,
+ 0xFF79, 0x00B9, 0xFF7A, 0x00BA, 0xFF7B, 0x00BB, 0xFF7C, 0x00BC, 0xFF7D, 0x00BD, 0xFF7E, 0x00BE, 0xFF7F, 0x00BF, 0xFF80, 0x00C0,
+ 0xFF81, 0x00C1, 0xFF82, 0x00C2, 0xFF83, 0x00C3, 0xFF84, 0x00C4, 0xFF85, 0x00C5, 0xFF86, 0x00C6, 0xFF87, 0x00C7, 0xFF88, 0x00C8,
+ 0xFF89, 0x00C9, 0xFF8A, 0x00CA, 0xFF8B, 0x00CB, 0xFF8C, 0x00CC, 0xFF8D, 0x00CD, 0xFF8E, 0x00CE, 0xFF8F, 0x00CF, 0xFF90, 0x00D0,
+ 0xFF91, 0x00D1, 0xFF92, 0x00D2, 0xFF93, 0x00D3, 0xFF94, 0x00D4, 0xFF95, 0x00D5, 0xFF96, 0x00D6, 0xFF97, 0x00D7, 0xFF98, 0x00D8,
+ 0xFF99, 0x00D9, 0xFF9A, 0x00DA, 0xFF9B, 0x00DB, 0xFF9C, 0x00DC, 0xFF9D, 0x00DD, 0xFF9E, 0x00DE, 0xFF9F, 0x00DF, 0xFFE0, 0x8191,
+ 0xFFE1, 0x8192, 0xFFE2, 0x81CA, 0xFFE3, 0x8150, 0xFFE4, 0xFA55, 0xFFE5, 0x818F, 0, 0
+};
+
+static const WCHAR oem2uni932[] = { /* Shift_JIS --> Unicode pairs */
+ 0x00A1, 0xFF61, 0x00A2, 0xFF62, 0x00A3, 0xFF63, 0x00A4, 0xFF64, 0x00A5, 0xFF65, 0x00A6, 0xFF66, 0x00A7, 0xFF67, 0x00A8, 0xFF68,
+ 0x00A9, 0xFF69, 0x00AA, 0xFF6A, 0x00AB, 0xFF6B, 0x00AC, 0xFF6C, 0x00AD, 0xFF6D, 0x00AE, 0xFF6E, 0x00AF, 0xFF6F, 0x00B0, 0xFF70,
+ 0x00B1, 0xFF71, 0x00B2, 0xFF72, 0x00B3, 0xFF73, 0x00B4, 0xFF74, 0x00B5, 0xFF75, 0x00B6, 0xFF76, 0x00B7, 0xFF77, 0x00B8, 0xFF78,
+ 0x00B9, 0xFF79, 0x00BA, 0xFF7A, 0x00BB, 0xFF7B, 0x00BC, 0xFF7C, 0x00BD, 0xFF7D, 0x00BE, 0xFF7E, 0x00BF, 0xFF7F, 0x00C0, 0xFF80,
+ 0x00C1, 0xFF81, 0x00C2, 0xFF82, 0x00C3, 0xFF83, 0x00C4, 0xFF84, 0x00C5, 0xFF85, 0x00C6, 0xFF86, 0x00C7, 0xFF87, 0x00C8, 0xFF88,
+ 0x00C9, 0xFF89, 0x00CA, 0xFF8A, 0x00CB, 0xFF8B, 0x00CC, 0xFF8C, 0x00CD, 0xFF8D, 0x00CE, 0xFF8E, 0x00CF, 0xFF8F, 0x00D0, 0xFF90,
+ 0x00D1, 0xFF91, 0x00D2, 0xFF92, 0x00D3, 0xFF93, 0x00D4, 0xFF94, 0x00D5, 0xFF95, 0x00D6, 0xFF96, 0x00D7, 0xFF97, 0x00D8, 0xFF98,
+ 0x00D9, 0xFF99, 0x00DA, 0xFF9A, 0x00DB, 0xFF9B, 0x00DC, 0xFF9C, 0x00DD, 0xFF9D, 0x00DE, 0xFF9E, 0x00DF, 0xFF9F, 0x8140, 0x3000,
+ 0x8141, 0x3001, 0x8142, 0x3002, 0x8143, 0xFF0C, 0x8144, 0xFF0E, 0x8145, 0x30FB, 0x8146, 0xFF1A, 0x8147, 0xFF1B, 0x8148, 0xFF1F,
+ 0x8149, 0xFF01, 0x814A, 0x309B, 0x814B, 0x309C, 0x814C, 0x00B4, 0x814D, 0xFF40, 0x814E, 0x00A8, 0x814F, 0xFF3E, 0x8150, 0xFFE3,
+ 0x8151, 0xFF3F, 0x8152, 0x30FD, 0x8153, 0x30FE, 0x8154, 0x309D, 0x8155, 0x309E, 0x8156, 0x3003, 0x8157, 0x4EDD, 0x8158, 0x3005,
+ 0x8159, 0x3006, 0x815A, 0x3007, 0x815B, 0x30FC, 0x815C, 0x2015, 0x815D, 0x2010, 0x815E, 0xFF0F, 0x815F, 0xFF3C, 0x8160, 0xFF5E,
+ 0x8161, 0x2225, 0x8162, 0xFF5C, 0x8163, 0x2026, 0x8164, 0x2025, 0x8165, 0x2018, 0x8166, 0x2019, 0x8167, 0x201C, 0x8168, 0x201D,
+ 0x8169, 0xFF08, 0x816A, 0xFF09, 0x816B, 0x3014, 0x816C, 0x3015, 0x816D, 0xFF3B, 0x816E, 0xFF3D, 0x816F, 0xFF5B, 0x8170, 0xFF5D,
+ 0x8171, 0x3008, 0x8172, 0x3009, 0x8173, 0x300A, 0x8174, 0x300B, 0x8175, 0x300C, 0x8176, 0x300D, 0x8177, 0x300E, 0x8178, 0x300F,
+ 0x8179, 0x3010, 0x817A, 0x3011, 0x817B, 0xFF0B, 0x817C, 0xFF0D, 0x817D, 0x00B1, 0x817E, 0x00D7, 0x8180, 0x00F7, 0x8181, 0xFF1D,
+ 0x8182, 0x2260, 0x8183, 0xFF1C, 0x8184, 0xFF1E, 0x8185, 0x2266, 0x8186, 0x2267, 0x8187, 0x221E, 0x8188, 0x2234, 0x8189, 0x2642,
+ 0x818A, 0x2640, 0x818B, 0x00B0, 0x818C, 0x2032, 0x818D, 0x2033, 0x818E, 0x2103, 0x818F, 0xFFE5, 0x8190, 0xFF04, 0x8191, 0xFFE0,
+ 0x8192, 0xFFE1, 0x8193, 0xFF05, 0x8194, 0xFF03, 0x8195, 0xFF06, 0x8196, 0xFF0A, 0x8197, 0xFF20, 0x8198, 0x00A7, 0x8199, 0x2606,
+ 0x819A, 0x2605, 0x819B, 0x25CB, 0x819C, 0x25CF, 0x819D, 0x25CE, 0x819E, 0x25C7, 0x819F, 0x25C6, 0x81A0, 0x25A1, 0x81A1, 0x25A0,
+ 0x81A2, 0x25B3, 0x81A3, 0x25B2, 0x81A4, 0x25BD, 0x81A5, 0x25BC, 0x81A6, 0x203B, 0x81A7, 0x3012, 0x81A8, 0x2192, 0x81A9, 0x2190,
+ 0x81AA, 0x2191, 0x81AB, 0x2193, 0x81AC, 0x3013, 0x81B8, 0x2208, 0x81B9, 0x220B, 0x81BA, 0x2286, 0x81BB, 0x2287, 0x81BC, 0x2282,
+ 0x81BD, 0x2283, 0x81BE, 0x222A, 0x81BF, 0x2229, 0x81C8, 0x2227, 0x81C9, 0x2228, 0x81CA, 0xFFE2, 0x81CB, 0x21D2, 0x81CC, 0x21D4,
+ 0x81CD, 0x2200, 0x81CE, 0x2203, 0x81DA, 0x2220, 0x81DB, 0x22A5, 0x81DC, 0x2312, 0x81DD, 0x2202, 0x81DE, 0x2207, 0x81DF, 0x2261,
+ 0x81E0, 0x2252, 0x81E1, 0x226A, 0x81E2, 0x226B, 0x81E3, 0x221A, 0x81E4, 0x223D, 0x81E5, 0x221D, 0x81E6, 0x2235, 0x81E7, 0x222B,
+ 0x81E8, 0x222C, 0x81F0, 0x212B, 0x81F1, 0x2030, 0x81F2, 0x266F, 0x81F3, 0x266D, 0x81F4, 0x266A, 0x81F5, 0x2020, 0x81F6, 0x2021,
+ 0x81F7, 0x00B6, 0x81FC, 0x25EF, 0x824F, 0xFF10, 0x8250, 0xFF11, 0x8251, 0xFF12, 0x8252, 0xFF13, 0x8253, 0xFF14, 0x8254, 0xFF15,
+ 0x8255, 0xFF16, 0x8256, 0xFF17, 0x8257, 0xFF18, 0x8258, 0xFF19, 0x8260, 0xFF21, 0x8261, 0xFF22, 0x8262, 0xFF23, 0x8263, 0xFF24,
+ 0x8264, 0xFF25, 0x8265, 0xFF26, 0x8266, 0xFF27, 0x8267, 0xFF28, 0x8268, 0xFF29, 0x8269, 0xFF2A, 0x826A, 0xFF2B, 0x826B, 0xFF2C,
+ 0x826C, 0xFF2D, 0x826D, 0xFF2E, 0x826E, 0xFF2F, 0x826F, 0xFF30, 0x8270, 0xFF31, 0x8271, 0xFF32, 0x8272, 0xFF33, 0x8273, 0xFF34,
+ 0x8274, 0xFF35, 0x8275, 0xFF36, 0x8276, 0xFF37, 0x8277, 0xFF38, 0x8278, 0xFF39, 0x8279, 0xFF3A, 0x8281, 0xFF41, 0x8282, 0xFF42,
+ 0x8283, 0xFF43, 0x8284, 0xFF44, 0x8285, 0xFF45, 0x8286, 0xFF46, 0x8287, 0xFF47, 0x8288, 0xFF48, 0x8289, 0xFF49, 0x828A, 0xFF4A,
+ 0x828B, 0xFF4B, 0x828C, 0xFF4C, 0x828D, 0xFF4D, 0x828E, 0xFF4E, 0x828F, 0xFF4F, 0x8290, 0xFF50, 0x8291, 0xFF51, 0x8292, 0xFF52,
+ 0x8293, 0xFF53, 0x8294, 0xFF54, 0x8295, 0xFF55, 0x8296, 0xFF56, 0x8297, 0xFF57, 0x8298, 0xFF58, 0x8299, 0xFF59, 0x829A, 0xFF5A,
+ 0x829F, 0x3041, 0x82A0, 0x3042, 0x82A1, 0x3043, 0x82A2, 0x3044, 0x82A3, 0x3045, 0x82A4, 0x3046, 0x82A5, 0x3047, 0x82A6, 0x3048,
+ 0x82A7, 0x3049, 0x82A8, 0x304A, 0x82A9, 0x304B, 0x82AA, 0x304C, 0x82AB, 0x304D, 0x82AC, 0x304E, 0x82AD, 0x304F, 0x82AE, 0x3050,
+ 0x82AF, 0x3051, 0x82B0, 0x3052, 0x82B1, 0x3053, 0x82B2, 0x3054, 0x82B3, 0x3055, 0x82B4, 0x3056, 0x82B5, 0x3057, 0x82B6, 0x3058,
+ 0x82B7, 0x3059, 0x82B8, 0x305A, 0x82B9, 0x305B, 0x82BA, 0x305C, 0x82BB, 0x305D, 0x82BC, 0x305E, 0x82BD, 0x305F, 0x82BE, 0x3060,
+ 0x82BF, 0x3061, 0x82C0, 0x3062, 0x82C1, 0x3063, 0x82C2, 0x3064, 0x82C3, 0x3065, 0x82C4, 0x3066, 0x82C5, 0x3067, 0x82C6, 0x3068,
+ 0x82C7, 0x3069, 0x82C8, 0x306A, 0x82C9, 0x306B, 0x82CA, 0x306C, 0x82CB, 0x306D, 0x82CC, 0x306E, 0x82CD, 0x306F, 0x82CE, 0x3070,
+ 0x82CF, 0x3071, 0x82D0, 0x3072, 0x82D1, 0x3073, 0x82D2, 0x3074, 0x82D3, 0x3075, 0x82D4, 0x3076, 0x82D5, 0x3077, 0x82D6, 0x3078,
+ 0x82D7, 0x3079, 0x82D8, 0x307A, 0x82D9, 0x307B, 0x82DA, 0x307C, 0x82DB, 0x307D, 0x82DC, 0x307E, 0x82DD, 0x307F, 0x82DE, 0x3080,
+ 0x82DF, 0x3081, 0x82E0, 0x3082, 0x82E1, 0x3083, 0x82E2, 0x3084, 0x82E3, 0x3085, 0x82E4, 0x3086, 0x82E5, 0x3087, 0x82E6, 0x3088,
+ 0x82E7, 0x3089, 0x82E8, 0x308A, 0x82E9, 0x308B, 0x82EA, 0x308C, 0x82EB, 0x308D, 0x82EC, 0x308E, 0x82ED, 0x308F, 0x82EE, 0x3090,
+ 0x82EF, 0x3091, 0x82F0, 0x3092, 0x82F1, 0x3093, 0x8340, 0x30A1, 0x8341, 0x30A2, 0x8342, 0x30A3, 0x8343, 0x30A4, 0x8344, 0x30A5,
+ 0x8345, 0x30A6, 0x8346, 0x30A7, 0x8347, 0x30A8, 0x8348, 0x30A9, 0x8349, 0x30AA, 0x834A, 0x30AB, 0x834B, 0x30AC, 0x834C, 0x30AD,
+ 0x834D, 0x30AE, 0x834E, 0x30AF, 0x834F, 0x30B0, 0x8350, 0x30B1, 0x8351, 0x30B2, 0x8352, 0x30B3, 0x8353, 0x30B4, 0x8354, 0x30B5,
+ 0x8355, 0x30B6, 0x8356, 0x30B7, 0x8357, 0x30B8, 0x8358, 0x30B9, 0x8359, 0x30BA, 0x835A, 0x30BB, 0x835B, 0x30BC, 0x835C, 0x30BD,
+ 0x835D, 0x30BE, 0x835E, 0x30BF, 0x835F, 0x30C0, 0x8360, 0x30C1, 0x8361, 0x30C2, 0x8362, 0x30C3, 0x8363, 0x30C4, 0x8364, 0x30C5,
+ 0x8365, 0x30C6, 0x8366, 0x30C7, 0x8367, 0x30C8, 0x8368, 0x30C9, 0x8369, 0x30CA, 0x836A, 0x30CB, 0x836B, 0x30CC, 0x836C, 0x30CD,
+ 0x836D, 0x30CE, 0x836E, 0x30CF, 0x836F, 0x30D0, 0x8370, 0x30D1, 0x8371, 0x30D2, 0x8372, 0x30D3, 0x8373, 0x30D4, 0x8374, 0x30D5,
+ 0x8375, 0x30D6, 0x8376, 0x30D7, 0x8377, 0x30D8, 0x8378, 0x30D9, 0x8379, 0x30DA, 0x837A, 0x30DB, 0x837B, 0x30DC, 0x837C, 0x30DD,
+ 0x837D, 0x30DE, 0x837E, 0x30DF, 0x8380, 0x30E0, 0x8381, 0x30E1, 0x8382, 0x30E2, 0x8383, 0x30E3, 0x8384, 0x30E4, 0x8385, 0x30E5,
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+ 0xFBAC, 0x8B7F, 0xFBAD, 0x8CF0, 0xFBAE, 0x8CF4, 0xFBAF, 0x8D12, 0xFBB0, 0x8D76, 0xFBB1, 0xFA23, 0xFBB2, 0x8ECF, 0xFBB3, 0xFA24,
+ 0xFBB4, 0xFA25, 0xFBB5, 0x9067, 0xFBB6, 0x90DE, 0xFBB7, 0xFA26, 0xFBB8, 0x9115, 0xFBB9, 0x9127, 0xFBBA, 0x91DA, 0xFBBB, 0x91D7,
+ 0xFBBC, 0x91DE, 0xFBBD, 0x91ED, 0xFBBE, 0x91EE, 0xFBBF, 0x91E4, 0xFBC0, 0x91E5, 0xFBC1, 0x9206, 0xFBC2, 0x9210, 0xFBC3, 0x920A,
+ 0xFBC4, 0x923A, 0xFBC5, 0x9240, 0xFBC6, 0x923C, 0xFBC7, 0x924E, 0xFBC8, 0x9259, 0xFBC9, 0x9251, 0xFBCA, 0x9239, 0xFBCB, 0x9267,
+ 0xFBCC, 0x92A7, 0xFBCD, 0x9277, 0xFBCE, 0x9278, 0xFBCF, 0x92E7, 0xFBD0, 0x92D7, 0xFBD1, 0x92D9, 0xFBD2, 0x92D0, 0xFBD3, 0xFA27,
+ 0xFBD4, 0x92D5, 0xFBD5, 0x92E0, 0xFBD6, 0x92D3, 0xFBD7, 0x9325, 0xFBD8, 0x9321, 0xFBD9, 0x92FB, 0xFBDA, 0xFA28, 0xFBDB, 0x931E,
+ 0xFBDC, 0x92FF, 0xFBDD, 0x931D, 0xFBDE, 0x9302, 0xFBDF, 0x9370, 0xFBE0, 0x9357, 0xFBE1, 0x93A4, 0xFBE2, 0x93C6, 0xFBE3, 0x93DE,
+ 0xFBE4, 0x93F8, 0xFBE5, 0x9431, 0xFBE6, 0x9445, 0xFBE7, 0x9448, 0xFBE8, 0x9592, 0xFBE9, 0xF9DC, 0xFBEA, 0xFA29, 0xFBEB, 0x969D,
+ 0xFBEC, 0x96AF, 0xFBED, 0x9733, 0xFBEE, 0x973B, 0xFBEF, 0x9743, 0xFBF0, 0x974D, 0xFBF1, 0x974F, 0xFBF2, 0x9751, 0xFBF3, 0x9755,
+ 0xFBF4, 0x9857, 0xFBF5, 0x9865, 0xFBF6, 0xFA2A, 0xFBF7, 0xFA2B, 0xFBF8, 0x9927, 0xFBF9, 0xFA2C, 0xFBFA, 0x999E, 0xFBFB, 0x9A4E,
+ 0xFBFC, 0x9AD9, 0xFC40, 0x9ADC, 0xFC41, 0x9B75, 0xFC42, 0x9B72, 0xFC43, 0x9B8F, 0xFC44, 0x9BB1, 0xFC45, 0x9BBB, 0xFC46, 0x9C00,
+ 0xFC47, 0x9D70, 0xFC48, 0x9D6B, 0xFC49, 0xFA2D, 0xFC4A, 0x9E19, 0xFC4B, 0x9ED1, 0, 0
+};
+#endif
+
+#if FF_CODE_PAGE == 936 || FF_CODE_PAGE == 0 /* Simplified Chinese */
+static const WCHAR uni2oem936[] = { /* Unicode --> GBK pairs */
+ 0x00A4, 0xA1E8, 0x00A7, 0xA1EC, 0x00A8, 0xA1A7, 0x00B0, 0xA1E3, 0x00B1, 0xA1C0, 0x00B7, 0xA1A4, 0x00D7, 0xA1C1, 0x00E0, 0xA8A4,
+ 0x00E1, 0xA8A2, 0x00E8, 0xA8A8, 0x00E9, 0xA8A6, 0x00EA, 0xA8BA, 0x00EC, 0xA8AC, 0x00ED, 0xA8AA, 0x00F2, 0xA8B0, 0x00F3, 0xA8AE,
+ 0x00F7, 0xA1C2, 0x00F9, 0xA8B4, 0x00FA, 0xA8B2, 0x00FC, 0xA8B9, 0x0101, 0xA8A1, 0x0113, 0xA8A5, 0x011B, 0xA8A7, 0x012B, 0xA8A9,
+ 0x0144, 0xA8BD, 0x0148, 0xA8BE, 0x014D, 0xA8AD, 0x016B, 0xA8B1, 0x01CE, 0xA8A3, 0x01D0, 0xA8AB, 0x01D2, 0xA8AF, 0x01D4, 0xA8B3,
+ 0x01D6, 0xA8B5, 0x01D8, 0xA8B6, 0x01DA, 0xA8B7, 0x01DC, 0xA8B8, 0x0251, 0xA8BB, 0x0261, 0xA8C0, 0x02C7, 0xA1A6, 0x02C9, 0xA1A5,
+ 0x02CA, 0xA840, 0x02CB, 0xA841, 0x02D9, 0xA842, 0x0391, 0xA6A1, 0x0392, 0xA6A2, 0x0393, 0xA6A3, 0x0394, 0xA6A4, 0x0395, 0xA6A5,
+ 0x0396, 0xA6A6, 0x0397, 0xA6A7, 0x0398, 0xA6A8, 0x0399, 0xA6A9, 0x039A, 0xA6AA, 0x039B, 0xA6AB, 0x039C, 0xA6AC, 0x039D, 0xA6AD,
+ 0x039E, 0xA6AE, 0x039F, 0xA6AF, 0x03A0, 0xA6B0, 0x03A1, 0xA6B1, 0x03A3, 0xA6B2, 0x03A4, 0xA6B3, 0x03A5, 0xA6B4, 0x03A6, 0xA6B5,
+ 0x03A7, 0xA6B6, 0x03A8, 0xA6B7, 0x03A9, 0xA6B8, 0x03B1, 0xA6C1, 0x03B2, 0xA6C2, 0x03B3, 0xA6C3, 0x03B4, 0xA6C4, 0x03B5, 0xA6C5,
+ 0x03B6, 0xA6C6, 0x03B7, 0xA6C7, 0x03B8, 0xA6C8, 0x03B9, 0xA6C9, 0x03BA, 0xA6CA, 0x03BB, 0xA6CB, 0x03BC, 0xA6CC, 0x03BD, 0xA6CD,
+ 0x03BE, 0xA6CE, 0x03BF, 0xA6CF, 0x03C0, 0xA6D0, 0x03C1, 0xA6D1, 0x03C3, 0xA6D2, 0x03C4, 0xA6D3, 0x03C5, 0xA6D4, 0x03C6, 0xA6D5,
+ 0x03C7, 0xA6D6, 0x03C8, 0xA6D7, 0x03C9, 0xA6D8, 0x0401, 0xA7A7, 0x0410, 0xA7A1, 0x0411, 0xA7A2, 0x0412, 0xA7A3, 0x0413, 0xA7A4,
+ 0x0414, 0xA7A5, 0x0415, 0xA7A6, 0x0416, 0xA7A8, 0x0417, 0xA7A9, 0x0418, 0xA7AA, 0x0419, 0xA7AB, 0x041A, 0xA7AC, 0x041B, 0xA7AD,
+ 0x041C, 0xA7AE, 0x041D, 0xA7AF, 0x041E, 0xA7B0, 0x041F, 0xA7B1, 0x0420, 0xA7B2, 0x0421, 0xA7B3, 0x0422, 0xA7B4, 0x0423, 0xA7B5,
+ 0x0424, 0xA7B6, 0x0425, 0xA7B7, 0x0426, 0xA7B8, 0x0427, 0xA7B9, 0x0428, 0xA7BA, 0x0429, 0xA7BB, 0x042A, 0xA7BC, 0x042B, 0xA7BD,
+ 0x042C, 0xA7BE, 0x042D, 0xA7BF, 0x042E, 0xA7C0, 0x042F, 0xA7C1, 0x0430, 0xA7D1, 0x0431, 0xA7D2, 0x0432, 0xA7D3, 0x0433, 0xA7D4,
+ 0x0434, 0xA7D5, 0x0435, 0xA7D6, 0x0436, 0xA7D8, 0x0437, 0xA7D9, 0x0438, 0xA7DA, 0x0439, 0xA7DB, 0x043A, 0xA7DC, 0x043B, 0xA7DD,
+ 0x043C, 0xA7DE, 0x043D, 0xA7DF, 0x043E, 0xA7E0, 0x043F, 0xA7E1, 0x0440, 0xA7E2, 0x0441, 0xA7E3, 0x0442, 0xA7E4, 0x0443, 0xA7E5,
+ 0x0444, 0xA7E6, 0x0445, 0xA7E7, 0x0446, 0xA7E8, 0x0447, 0xA7E9, 0x0448, 0xA7EA, 0x0449, 0xA7EB, 0x044A, 0xA7EC, 0x044B, 0xA7ED,
+ 0x044C, 0xA7EE, 0x044D, 0xA7EF, 0x044E, 0xA7F0, 0x044F, 0xA7F1, 0x0451, 0xA7D7, 0x2010, 0xA95C, 0x2013, 0xA843, 0x2014, 0xA1AA,
+ 0x2015, 0xA844, 0x2016, 0xA1AC, 0x2018, 0xA1AE, 0x2019, 0xA1AF, 0x201C, 0xA1B0, 0x201D, 0xA1B1, 0x2025, 0xA845, 0x2026, 0xA1AD,
+ 0x2030, 0xA1EB, 0x2032, 0xA1E4, 0x2033, 0xA1E5, 0x2035, 0xA846, 0x203B, 0xA1F9, 0x20AC, 0x0080, 0x2103, 0xA1E6, 0x2105, 0xA847,
+ 0x2109, 0xA848, 0x2116, 0xA1ED, 0x2121, 0xA959, 0x2160, 0xA2F1, 0x2161, 0xA2F2, 0x2162, 0xA2F3, 0x2163, 0xA2F4, 0x2164, 0xA2F5,
+ 0x2165, 0xA2F6, 0x2166, 0xA2F7, 0x2167, 0xA2F8, 0x2168, 0xA2F9, 0x2169, 0xA2FA, 0x216A, 0xA2FB, 0x216B, 0xA2FC, 0x2170, 0xA2A1,
+ 0x2171, 0xA2A2, 0x2172, 0xA2A3, 0x2173, 0xA2A4, 0x2174, 0xA2A5, 0x2175, 0xA2A6, 0x2176, 0xA2A7, 0x2177, 0xA2A8, 0x2178, 0xA2A9,
+ 0x2179, 0xA2AA, 0x2190, 0xA1FB, 0x2191, 0xA1FC, 0x2192, 0xA1FA, 0x2193, 0xA1FD, 0x2196, 0xA849, 0x2197, 0xA84A, 0x2198, 0xA84B,
+ 0x2199, 0xA84C, 0x2208, 0xA1CA, 0x220F, 0xA1C7, 0x2211, 0xA1C6, 0x2215, 0xA84D, 0x221A, 0xA1CC, 0x221D, 0xA1D8, 0x221E, 0xA1DE,
+ 0x221F, 0xA84E, 0x2220, 0xA1CF, 0x2223, 0xA84F, 0x2225, 0xA1CE, 0x2227, 0xA1C4, 0x2228, 0xA1C5, 0x2229, 0xA1C9, 0x222A, 0xA1C8,
+ 0x222B, 0xA1D2, 0x222E, 0xA1D3, 0x2234, 0xA1E0, 0x2235, 0xA1DF, 0x2236, 0xA1C3, 0x2237, 0xA1CB, 0x223D, 0xA1D7, 0x2248, 0xA1D6,
+ 0x224C, 0xA1D5, 0x2252, 0xA850, 0x2260, 0xA1D9, 0x2261, 0xA1D4, 0x2264, 0xA1DC, 0x2265, 0xA1DD, 0x2266, 0xA851, 0x2267, 0xA852,
+ 0x226E, 0xA1DA, 0x226F, 0xA1DB, 0x2295, 0xA892, 0x2299, 0xA1D1, 0x22A5, 0xA1CD, 0x22BF, 0xA853, 0x2312, 0xA1D0, 0x2460, 0xA2D9,
+ 0x2461, 0xA2DA, 0x2462, 0xA2DB, 0x2463, 0xA2DC, 0x2464, 0xA2DD, 0x2465, 0xA2DE, 0x2466, 0xA2DF, 0x2467, 0xA2E0, 0x2468, 0xA2E1,
+ 0x2469, 0xA2E2, 0x2474, 0xA2C5, 0x2475, 0xA2C6, 0x2476, 0xA2C7, 0x2477, 0xA2C8, 0x2478, 0xA2C9, 0x2479, 0xA2CA, 0x247A, 0xA2CB,
+ 0x247B, 0xA2CC, 0x247C, 0xA2CD, 0x247D, 0xA2CE, 0x247E, 0xA2CF, 0x247F, 0xA2D0, 0x2480, 0xA2D1, 0x2481, 0xA2D2, 0x2482, 0xA2D3,
+ 0x2483, 0xA2D4, 0x2484, 0xA2D5, 0x2485, 0xA2D6, 0x2486, 0xA2D7, 0x2487, 0xA2D8, 0x2488, 0xA2B1, 0x2489, 0xA2B2, 0x248A, 0xA2B3,
+ 0x248B, 0xA2B4, 0x248C, 0xA2B5, 0x248D, 0xA2B6, 0x248E, 0xA2B7, 0x248F, 0xA2B8, 0x2490, 0xA2B9, 0x2491, 0xA2BA, 0x2492, 0xA2BB,
+ 0x2493, 0xA2BC, 0x2494, 0xA2BD, 0x2495, 0xA2BE, 0x2496, 0xA2BF, 0x2497, 0xA2C0, 0x2498, 0xA2C1, 0x2499, 0xA2C2, 0x249A, 0xA2C3,
+ 0x249B, 0xA2C4, 0x2500, 0xA9A4, 0x2501, 0xA9A5, 0x2502, 0xA9A6, 0x2503, 0xA9A7, 0x2504, 0xA9A8, 0x2505, 0xA9A9, 0x2506, 0xA9AA,
+ 0x2507, 0xA9AB, 0x2508, 0xA9AC, 0x2509, 0xA9AD, 0x250A, 0xA9AE, 0x250B, 0xA9AF, 0x250C, 0xA9B0, 0x250D, 0xA9B1, 0x250E, 0xA9B2,
+ 0x250F, 0xA9B3, 0x2510, 0xA9B4, 0x2511, 0xA9B5, 0x2512, 0xA9B6, 0x2513, 0xA9B7, 0x2514, 0xA9B8, 0x2515, 0xA9B9, 0x2516, 0xA9BA,
+ 0x2517, 0xA9BB, 0x2518, 0xA9BC, 0x2519, 0xA9BD, 0x251A, 0xA9BE, 0x251B, 0xA9BF, 0x251C, 0xA9C0, 0x251D, 0xA9C1, 0x251E, 0xA9C2,
+ 0x251F, 0xA9C3, 0x2520, 0xA9C4, 0x2521, 0xA9C5, 0x2522, 0xA9C6, 0x2523, 0xA9C7, 0x2524, 0xA9C8, 0x2525, 0xA9C9, 0x2526, 0xA9CA,
+ 0x2527, 0xA9CB, 0x2528, 0xA9CC, 0x2529, 0xA9CD, 0x252A, 0xA9CE, 0x252B, 0xA9CF, 0x252C, 0xA9D0, 0x252D, 0xA9D1, 0x252E, 0xA9D2,
+ 0x252F, 0xA9D3, 0x2530, 0xA9D4, 0x2531, 0xA9D5, 0x2532, 0xA9D6, 0x2533, 0xA9D7, 0x2534, 0xA9D8, 0x2535, 0xA9D9, 0x2536, 0xA9DA,
+ 0x2537, 0xA9DB, 0x2538, 0xA9DC, 0x2539, 0xA9DD, 0x253A, 0xA9DE, 0x253B, 0xA9DF, 0x253C, 0xA9E0, 0x253D, 0xA9E1, 0x253E, 0xA9E2,
+ 0x253F, 0xA9E3, 0x2540, 0xA9E4, 0x2541, 0xA9E5, 0x2542, 0xA9E6, 0x2543, 0xA9E7, 0x2544, 0xA9E8, 0x2545, 0xA9E9, 0x2546, 0xA9EA,
+ 0x2547, 0xA9EB, 0x2548, 0xA9EC, 0x2549, 0xA9ED, 0x254A, 0xA9EE, 0x254B, 0xA9EF, 0x2550, 0xA854, 0x2551, 0xA855, 0x2552, 0xA856,
+ 0x2553, 0xA857, 0x2554, 0xA858, 0x2555, 0xA859, 0x2556, 0xA85A, 0x2557, 0xA85B, 0x2558, 0xA85C, 0x2559, 0xA85D, 0x255A, 0xA85E,
+ 0x255B, 0xA85F, 0x255C, 0xA860, 0x255D, 0xA861, 0x255E, 0xA862, 0x255F, 0xA863, 0x2560, 0xA864, 0x2561, 0xA865, 0x2562, 0xA866,
+ 0x2563, 0xA867, 0x2564, 0xA868, 0x2565, 0xA869, 0x2566, 0xA86A, 0x2567, 0xA86B, 0x2568, 0xA86C, 0x2569, 0xA86D, 0x256A, 0xA86E,
+ 0x256B, 0xA86F, 0x256C, 0xA870, 0x256D, 0xA871, 0x256E, 0xA872, 0x256F, 0xA873, 0x2570, 0xA874, 0x2571, 0xA875, 0x2572, 0xA876,
+ 0x2573, 0xA877, 0x2581, 0xA878, 0x2582, 0xA879, 0x2583, 0xA87A, 0x2584, 0xA87B, 0x2585, 0xA87C, 0x2586, 0xA87D, 0x2587, 0xA87E,
+ 0x2588, 0xA880, 0x2589, 0xA881, 0x258A, 0xA882, 0x258B, 0xA883, 0x258C, 0xA884, 0x258D, 0xA885, 0x258E, 0xA886, 0x258F, 0xA887,
+ 0x2593, 0xA888, 0x2594, 0xA889, 0x2595, 0xA88A, 0x25A0, 0xA1F6, 0x25A1, 0xA1F5, 0x25B2, 0xA1F8, 0x25B3, 0xA1F7, 0x25BC, 0xA88B,
+ 0x25BD, 0xA88C, 0x25C6, 0xA1F4, 0x25C7, 0xA1F3, 0x25CB, 0xA1F0, 0x25CE, 0xA1F2, 0x25CF, 0xA1F1, 0x25E2, 0xA88D, 0x25E3, 0xA88E,
+ 0x25E4, 0xA88F, 0x25E5, 0xA890, 0x2605, 0xA1EF, 0x2606, 0xA1EE, 0x2609, 0xA891, 0x2640, 0xA1E2, 0x2642, 0xA1E1, 0x3000, 0xA1A1,
+ 0x3001, 0xA1A2, 0x3002, 0xA1A3, 0x3003, 0xA1A8, 0x3005, 0xA1A9, 0x3006, 0xA965, 0x3007, 0xA996, 0x3008, 0xA1B4, 0x3009, 0xA1B5,
+ 0x300A, 0xA1B6, 0x300B, 0xA1B7, 0x300C, 0xA1B8, 0x300D, 0xA1B9, 0x300E, 0xA1BA, 0x300F, 0xA1BB, 0x3010, 0xA1BE, 0x3011, 0xA1BF,
+ 0x3012, 0xA893, 0x3013, 0xA1FE, 0x3014, 0xA1B2, 0x3015, 0xA1B3, 0x3016, 0xA1BC, 0x3017, 0xA1BD, 0x301D, 0xA894, 0x301E, 0xA895,
+ 0x3021, 0xA940, 0x3022, 0xA941, 0x3023, 0xA942, 0x3024, 0xA943, 0x3025, 0xA944, 0x3026, 0xA945, 0x3027, 0xA946, 0x3028, 0xA947,
+ 0x3029, 0xA948, 0x3041, 0xA4A1, 0x3042, 0xA4A2, 0x3043, 0xA4A3, 0x3044, 0xA4A4, 0x3045, 0xA4A5, 0x3046, 0xA4A6, 0x3047, 0xA4A7,
+ 0x3048, 0xA4A8, 0x3049, 0xA4A9, 0x304A, 0xA4AA, 0x304B, 0xA4AB, 0x304C, 0xA4AC, 0x304D, 0xA4AD, 0x304E, 0xA4AE, 0x304F, 0xA4AF,
+ 0x3050, 0xA4B0, 0x3051, 0xA4B1, 0x3052, 0xA4B2, 0x3053, 0xA4B3, 0x3054, 0xA4B4, 0x3055, 0xA4B5, 0x3056, 0xA4B6, 0x3057, 0xA4B7,
+ 0x3058, 0xA4B8, 0x3059, 0xA4B9, 0x305A, 0xA4BA, 0x305B, 0xA4BB, 0x305C, 0xA4BC, 0x305D, 0xA4BD, 0x305E, 0xA4BE, 0x305F, 0xA4BF,
+ 0x3060, 0xA4C0, 0x3061, 0xA4C1, 0x3062, 0xA4C2, 0x3063, 0xA4C3, 0x3064, 0xA4C4, 0x3065, 0xA4C5, 0x3066, 0xA4C6, 0x3067, 0xA4C7,
+ 0x3068, 0xA4C8, 0x3069, 0xA4C9, 0x306A, 0xA4CA, 0x306B, 0xA4CB, 0x306C, 0xA4CC, 0x306D, 0xA4CD, 0x306E, 0xA4CE, 0x306F, 0xA4CF,
+ 0x3070, 0xA4D0, 0x3071, 0xA4D1, 0x3072, 0xA4D2, 0x3073, 0xA4D3, 0x3074, 0xA4D4, 0x3075, 0xA4D5, 0x3076, 0xA4D6, 0x3077, 0xA4D7,
+ 0x3078, 0xA4D8, 0x3079, 0xA4D9, 0x307A, 0xA4DA, 0x307B, 0xA4DB, 0x307C, 0xA4DC, 0x307D, 0xA4DD, 0x307E, 0xA4DE, 0x307F, 0xA4DF,
+ 0x3080, 0xA4E0, 0x3081, 0xA4E1, 0x3082, 0xA4E2, 0x3083, 0xA4E3, 0x3084, 0xA4E4, 0x3085, 0xA4E5, 0x3086, 0xA4E6, 0x3087, 0xA4E7,
+ 0x3088, 0xA4E8, 0x3089, 0xA4E9, 0x308A, 0xA4EA, 0x308B, 0xA4EB, 0x308C, 0xA4EC, 0x308D, 0xA4ED, 0x308E, 0xA4EE, 0x308F, 0xA4EF,
+ 0x3090, 0xA4F0, 0x3091, 0xA4F1, 0x3092, 0xA4F2, 0x3093, 0xA4F3, 0x309B, 0xA961, 0x309C, 0xA962, 0x309D, 0xA966, 0x309E, 0xA967,
+ 0x30A1, 0xA5A1, 0x30A2, 0xA5A2, 0x30A3, 0xA5A3, 0x30A4, 0xA5A4, 0x30A5, 0xA5A5, 0x30A6, 0xA5A6, 0x30A7, 0xA5A7, 0x30A8, 0xA5A8,
+ 0x30A9, 0xA5A9, 0x30AA, 0xA5AA, 0x30AB, 0xA5AB, 0x30AC, 0xA5AC, 0x30AD, 0xA5AD, 0x30AE, 0xA5AE, 0x30AF, 0xA5AF, 0x30B0, 0xA5B0,
+ 0x30B1, 0xA5B1, 0x30B2, 0xA5B2, 0x30B3, 0xA5B3, 0x30B4, 0xA5B4, 0x30B5, 0xA5B5, 0x30B6, 0xA5B6, 0x30B7, 0xA5B7, 0x30B8, 0xA5B8,
+ 0x30B9, 0xA5B9, 0x30BA, 0xA5BA, 0x30BB, 0xA5BB, 0x30BC, 0xA5BC, 0x30BD, 0xA5BD, 0x30BE, 0xA5BE, 0x30BF, 0xA5BF, 0x30C0, 0xA5C0,
+ 0x30C1, 0xA5C1, 0x30C2, 0xA5C2, 0x30C3, 0xA5C3, 0x30C4, 0xA5C4, 0x30C5, 0xA5C5, 0x30C6, 0xA5C6, 0x30C7, 0xA5C7, 0x30C8, 0xA5C8,
+ 0x30C9, 0xA5C9, 0x30CA, 0xA5CA, 0x30CB, 0xA5CB, 0x30CC, 0xA5CC, 0x30CD, 0xA5CD, 0x30CE, 0xA5CE, 0x30CF, 0xA5CF, 0x30D0, 0xA5D0,
+ 0x30D1, 0xA5D1, 0x30D2, 0xA5D2, 0x30D3, 0xA5D3, 0x30D4, 0xA5D4, 0x30D5, 0xA5D5, 0x30D6, 0xA5D6, 0x30D7, 0xA5D7, 0x30D8, 0xA5D8,
+ 0x30D9, 0xA5D9, 0x30DA, 0xA5DA, 0x30DB, 0xA5DB, 0x30DC, 0xA5DC, 0x30DD, 0xA5DD, 0x30DE, 0xA5DE, 0x30DF, 0xA5DF, 0x30E0, 0xA5E0,
+ 0x30E1, 0xA5E1, 0x30E2, 0xA5E2, 0x30E3, 0xA5E3, 0x30E4, 0xA5E4, 0x30E5, 0xA5E5, 0x30E6, 0xA5E6, 0x30E7, 0xA5E7, 0x30E8, 0xA5E8,
+ 0x30E9, 0xA5E9, 0x30EA, 0xA5EA, 0x30EB, 0xA5EB, 0x30EC, 0xA5EC, 0x30ED, 0xA5ED, 0x30EE, 0xA5EE, 0x30EF, 0xA5EF, 0x30F0, 0xA5F0,
+ 0x30F1, 0xA5F1, 0x30F2, 0xA5F2, 0x30F3, 0xA5F3, 0x30F4, 0xA5F4, 0x30F5, 0xA5F5, 0x30F6, 0xA5F6, 0x30FC, 0xA960, 0x30FD, 0xA963,
+ 0x30FE, 0xA964, 0x3105, 0xA8C5, 0x3106, 0xA8C6, 0x3107, 0xA8C7, 0x3108, 0xA8C8, 0x3109, 0xA8C9, 0x310A, 0xA8CA, 0x310B, 0xA8CB,
+ 0x310C, 0xA8CC, 0x310D, 0xA8CD, 0x310E, 0xA8CE, 0x310F, 0xA8CF, 0x3110, 0xA8D0, 0x3111, 0xA8D1, 0x3112, 0xA8D2, 0x3113, 0xA8D3,
+ 0x3114, 0xA8D4, 0x3115, 0xA8D5, 0x3116, 0xA8D6, 0x3117, 0xA8D7, 0x3118, 0xA8D8, 0x3119, 0xA8D9, 0x311A, 0xA8DA, 0x311B, 0xA8DB,
+ 0x311C, 0xA8DC, 0x311D, 0xA8DD, 0x311E, 0xA8DE, 0x311F, 0xA8DF, 0x3120, 0xA8E0, 0x3121, 0xA8E1, 0x3122, 0xA8E2, 0x3123, 0xA8E3,
+ 0x3124, 0xA8E4, 0x3125, 0xA8E5, 0x3126, 0xA8E6, 0x3127, 0xA8E7, 0x3128, 0xA8E8, 0x3129, 0xA8E9, 0x3220, 0xA2E5, 0x3221, 0xA2E6,
+ 0x3222, 0xA2E7, 0x3223, 0xA2E8, 0x3224, 0xA2E9, 0x3225, 0xA2EA, 0x3226, 0xA2EB, 0x3227, 0xA2EC, 0x3228, 0xA2ED, 0x3229, 0xA2EE,
+ 0x3231, 0xA95A, 0x32A3, 0xA949, 0x338E, 0xA94A, 0x338F, 0xA94B, 0x339C, 0xA94C, 0x339D, 0xA94D, 0x339E, 0xA94E, 0x33A1, 0xA94F,
+ 0x33C4, 0xA950, 0x33CE, 0xA951, 0x33D1, 0xA952, 0x33D2, 0xA953, 0x33D5, 0xA954, 0x4E00, 0xD2BB, 0x4E01, 0xB6A1, 0x4E02, 0x8140,
+ 0x4E03, 0xC6DF, 0x4E04, 0x8141, 0x4E05, 0x8142, 0x4E06, 0x8143, 0x4E07, 0xCDF2, 0x4E08, 0xD5C9, 0x4E09, 0xC8FD, 0x4E0A, 0xC9CF,
+ 0x4E0B, 0xCFC2, 0x4E0C, 0xD8A2, 0x4E0D, 0xB2BB, 0x4E0E, 0xD3EB, 0x4E0F, 0x8144, 0x4E10, 0xD8A4, 0x4E11, 0xB3F3, 0x4E12, 0x8145,
+ 0x4E13, 0xD7A8, 0x4E14, 0xC7D2, 0x4E15, 0xD8A7, 0x4E16, 0xCAC0, 0x4E17, 0x8146, 0x4E18, 0xC7F0, 0x4E19, 0xB1FB, 0x4E1A, 0xD2B5,
+ 0x4E1B, 0xB4D4, 0x4E1C, 0xB6AB, 0x4E1D, 0xCBBF, 0x4E1E, 0xD8A9, 0x4E1F, 0x8147, 0x4E20, 0x8148, 0x4E21, 0x8149, 0x4E22, 0xB6AA,
+ 0x4E23, 0x814A, 0x4E24, 0xC1BD, 0x4E25, 0xD1CF, 0x4E26, 0x814B, 0x4E27, 0xC9A5, 0x4E28, 0xD8AD, 0x4E29, 0x814C, 0x4E2A, 0xB8F6,
+ 0x4E2B, 0xD1BE, 0x4E2C, 0xE3DC, 0x4E2D, 0xD6D0, 0x4E2E, 0x814D, 0x4E2F, 0x814E, 0x4E30, 0xB7E1, 0x4E31, 0x814F, 0x4E32, 0xB4AE,
+ 0x4E33, 0x8150, 0x4E34, 0xC1D9, 0x4E35, 0x8151, 0x4E36, 0xD8BC, 0x4E37, 0x8152, 0x4E38, 0xCDE8, 0x4E39, 0xB5A4, 0x4E3A, 0xCEAA,
+ 0x4E3B, 0xD6F7, 0x4E3C, 0x8153, 0x4E3D, 0xC0F6, 0x4E3E, 0xBED9, 0x4E3F, 0xD8AF, 0x4E40, 0x8154, 0x4E41, 0x8155, 0x4E42, 0x8156,
+ 0x4E43, 0xC4CB, 0x4E44, 0x8157, 0x4E45, 0xBEC3, 0x4E46, 0x8158, 0x4E47, 0xD8B1, 0x4E48, 0xC3B4, 0x4E49, 0xD2E5, 0x4E4A, 0x8159,
+ 0x4E4B, 0xD6AE, 0x4E4C, 0xCEDA, 0x4E4D, 0xD5A7, 0x4E4E, 0xBAF5, 0x4E4F, 0xB7A6, 0x4E50, 0xC0D6, 0x4E51, 0x815A, 0x4E52, 0xC6B9,
+ 0x4E53, 0xC5D2, 0x4E54, 0xC7C7, 0x4E55, 0x815B, 0x4E56, 0xB9D4, 0x4E57, 0x815C, 0x4E58, 0xB3CB, 0x4E59, 0xD2D2, 0x4E5A, 0x815D,
+ 0x4E5B, 0x815E, 0x4E5C, 0xD8BF, 0x4E5D, 0xBEC5, 0x4E5E, 0xC6F2, 0x4E5F, 0xD2B2, 0x4E60, 0xCFB0, 0x4E61, 0xCFE7, 0x4E62, 0x815F,
+ 0x4E63, 0x8160, 0x4E64, 0x8161, 0x4E65, 0x8162, 0x4E66, 0xCAE9, 0x4E67, 0x8163, 0x4E68, 0x8164, 0x4E69, 0xD8C0, 0x4E6A, 0x8165,
+ 0x4E6B, 0x8166, 0x4E6C, 0x8167, 0x4E6D, 0x8168, 0x4E6E, 0x8169, 0x4E6F, 0x816A, 0x4E70, 0xC2F2, 0x4E71, 0xC2D2, 0x4E72, 0x816B,
+ 0x4E73, 0xC8E9, 0x4E74, 0x816C, 0x4E75, 0x816D, 0x4E76, 0x816E, 0x4E77, 0x816F, 0x4E78, 0x8170, 0x4E79, 0x8171, 0x4E7A, 0x8172,
+ 0x4E7B, 0x8173, 0x4E7C, 0x8174, 0x4E7D, 0x8175, 0x4E7E, 0xC7AC, 0x4E7F, 0x8176, 0x4E80, 0x8177, 0x4E81, 0x8178, 0x4E82, 0x8179,
+ 0x4E83, 0x817A, 0x4E84, 0x817B, 0x4E85, 0x817C, 0x4E86, 0xC1CB, 0x4E87, 0x817D, 0x4E88, 0xD3E8, 0x4E89, 0xD5F9, 0x4E8A, 0x817E,
+ 0x4E8B, 0xCAC2, 0x4E8C, 0xB6FE, 0x4E8D, 0xD8A1, 0x4E8E, 0xD3DA, 0x4E8F, 0xBFF7, 0x4E90, 0x8180, 0x4E91, 0xD4C6, 0x4E92, 0xBBA5,
+ 0x4E93, 0xD8C1, 0x4E94, 0xCEE5, 0x4E95, 0xBEAE, 0x4E96, 0x8181, 0x4E97, 0x8182, 0x4E98, 0xD8A8, 0x4E99, 0x8183, 0x4E9A, 0xD1C7,
+ 0x4E9B, 0xD0A9, 0x4E9C, 0x8184, 0x4E9D, 0x8185, 0x4E9E, 0x8186, 0x4E9F, 0xD8BD, 0x4EA0, 0xD9EF, 0x4EA1, 0xCDF6, 0x4EA2, 0xBFBA,
+ 0x4EA3, 0x8187, 0x4EA4, 0xBDBB, 0x4EA5, 0xBAA5, 0x4EA6, 0xD2E0, 0x4EA7, 0xB2FA, 0x4EA8, 0xBAE0, 0x4EA9, 0xC4B6, 0x4EAA, 0x8188,
+ 0x4EAB, 0xCFED, 0x4EAC, 0xBEA9, 0x4EAD, 0xCDA4, 0x4EAE, 0xC1C1, 0x4EAF, 0x8189, 0x4EB0, 0x818A, 0x4EB1, 0x818B, 0x4EB2, 0xC7D7,
+ 0x4EB3, 0xD9F1, 0x4EB4, 0x818C, 0x4EB5, 0xD9F4, 0x4EB6, 0x818D, 0x4EB7, 0x818E, 0x4EB8, 0x818F, 0x4EB9, 0x8190, 0x4EBA, 0xC8CB,
+ 0x4EBB, 0xD8E9, 0x4EBC, 0x8191, 0x4EBD, 0x8192, 0x4EBE, 0x8193, 0x4EBF, 0xD2DA, 0x4EC0, 0xCAB2, 0x4EC1, 0xC8CA, 0x4EC2, 0xD8EC,
+ 0x4EC3, 0xD8EA, 0x4EC4, 0xD8C6, 0x4EC5, 0xBDF6, 0x4EC6, 0xC6CD, 0x4EC7, 0xB3F0, 0x4EC8, 0x8194, 0x4EC9, 0xD8EB, 0x4ECA, 0xBDF1,
+ 0x4ECB, 0xBDE9, 0x4ECC, 0x8195, 0x4ECD, 0xC8D4, 0x4ECE, 0xB4D3, 0x4ECF, 0x8196, 0x4ED0, 0x8197, 0x4ED1, 0xC2D8, 0x4ED2, 0x8198,
+ 0x4ED3, 0xB2D6, 0x4ED4, 0xD7D0, 0x4ED5, 0xCACB, 0x4ED6, 0xCBFB, 0x4ED7, 0xD5CC, 0x4ED8, 0xB8B6, 0x4ED9, 0xCFC9, 0x4EDA, 0x8199,
+ 0x4EDB, 0x819A, 0x4EDC, 0x819B, 0x4EDD, 0xD9DA, 0x4EDE, 0xD8F0, 0x4EDF, 0xC7AA, 0x4EE0, 0x819C, 0x4EE1, 0xD8EE, 0x4EE2, 0x819D,
+ 0x4EE3, 0xB4FA, 0x4EE4, 0xC1EE, 0x4EE5, 0xD2D4, 0x4EE6, 0x819E, 0x4EE7, 0x819F, 0x4EE8, 0xD8ED, 0x4EE9, 0x81A0, 0x4EEA, 0xD2C7,
+ 0x4EEB, 0xD8EF, 0x4EEC, 0xC3C7, 0x4EED, 0x81A1, 0x4EEE, 0x81A2, 0x4EEF, 0x81A3, 0x4EF0, 0xD1F6, 0x4EF1, 0x81A4, 0x4EF2, 0xD6D9,
+ 0x4EF3, 0xD8F2, 0x4EF4, 0x81A5, 0x4EF5, 0xD8F5, 0x4EF6, 0xBCFE, 0x4EF7, 0xBCDB, 0x4EF8, 0x81A6, 0x4EF9, 0x81A7, 0x4EFA, 0x81A8,
+ 0x4EFB, 0xC8CE, 0x4EFC, 0x81A9, 0x4EFD, 0xB7DD, 0x4EFE, 0x81AA, 0x4EFF, 0xB7C2, 0x4F00, 0x81AB, 0x4F01, 0xC6F3, 0x4F02, 0x81AC,
+ 0x4F03, 0x81AD, 0x4F04, 0x81AE, 0x4F05, 0x81AF, 0x4F06, 0x81B0, 0x4F07, 0x81B1, 0x4F08, 0x81B2, 0x4F09, 0xD8F8, 0x4F0A, 0xD2C1,
+ 0x4F0B, 0x81B3, 0x4F0C, 0x81B4, 0x4F0D, 0xCEE9, 0x4F0E, 0xBCBF, 0x4F0F, 0xB7FC, 0x4F10, 0xB7A5, 0x4F11, 0xD0DD, 0x4F12, 0x81B5,
+ 0x4F13, 0x81B6, 0x4F14, 0x81B7, 0x4F15, 0x81B8, 0x4F16, 0x81B9, 0x4F17, 0xD6DA, 0x4F18, 0xD3C5, 0x4F19, 0xBBEF, 0x4F1A, 0xBBE1,
+ 0x4F1B, 0xD8F1, 0x4F1C, 0x81BA, 0x4F1D, 0x81BB, 0x4F1E, 0xC9A1, 0x4F1F, 0xCEB0, 0x4F20, 0xB4AB, 0x4F21, 0x81BC, 0x4F22, 0xD8F3,
+ 0x4F23, 0x81BD, 0x4F24, 0xC9CB, 0x4F25, 0xD8F6, 0x4F26, 0xC2D7, 0x4F27, 0xD8F7, 0x4F28, 0x81BE, 0x4F29, 0x81BF, 0x4F2A, 0xCEB1,
+ 0x4F2B, 0xD8F9, 0x4F2C, 0x81C0, 0x4F2D, 0x81C1, 0x4F2E, 0x81C2, 0x4F2F, 0xB2AE, 0x4F30, 0xB9C0, 0x4F31, 0x81C3, 0x4F32, 0xD9A3,
+ 0x4F33, 0x81C4, 0x4F34, 0xB0E9, 0x4F35, 0x81C5, 0x4F36, 0xC1E6, 0x4F37, 0x81C6, 0x4F38, 0xC9EC, 0x4F39, 0x81C7, 0x4F3A, 0xCBC5,
+ 0x4F3B, 0x81C8, 0x4F3C, 0xCBC6, 0x4F3D, 0xD9A4, 0x4F3E, 0x81C9, 0x4F3F, 0x81CA, 0x4F40, 0x81CB, 0x4F41, 0x81CC, 0x4F42, 0x81CD,
+ 0x4F43, 0xB5E8, 0x4F44, 0x81CE, 0x4F45, 0x81CF, 0x4F46, 0xB5AB, 0x4F47, 0x81D0, 0x4F48, 0x81D1, 0x4F49, 0x81D2, 0x4F4A, 0x81D3,
+ 0x4F4B, 0x81D4, 0x4F4C, 0x81D5, 0x4F4D, 0xCEBB, 0x4F4E, 0xB5CD, 0x4F4F, 0xD7A1, 0x4F50, 0xD7F4, 0x4F51, 0xD3D3, 0x4F52, 0x81D6,
+ 0x4F53, 0xCCE5, 0x4F54, 0x81D7, 0x4F55, 0xBACE, 0x4F56, 0x81D8, 0x4F57, 0xD9A2, 0x4F58, 0xD9DC, 0x4F59, 0xD3E0, 0x4F5A, 0xD8FD,
+ 0x4F5B, 0xB7F0, 0x4F5C, 0xD7F7, 0x4F5D, 0xD8FE, 0x4F5E, 0xD8FA, 0x4F5F, 0xD9A1, 0x4F60, 0xC4E3, 0x4F61, 0x81D9, 0x4F62, 0x81DA,
+ 0x4F63, 0xD3B6, 0x4F64, 0xD8F4, 0x4F65, 0xD9DD, 0x4F66, 0x81DB, 0x4F67, 0xD8FB, 0x4F68, 0x81DC, 0x4F69, 0xC5E5, 0x4F6A, 0x81DD,
+ 0x4F6B, 0x81DE, 0x4F6C, 0xC0D0, 0x4F6D, 0x81DF, 0x4F6E, 0x81E0, 0x4F6F, 0xD1F0, 0x4F70, 0xB0DB, 0x4F71, 0x81E1, 0x4F72, 0x81E2,
+ 0x4F73, 0xBCD1, 0x4F74, 0xD9A6, 0x4F75, 0x81E3, 0x4F76, 0xD9A5, 0x4F77, 0x81E4, 0x4F78, 0x81E5, 0x4F79, 0x81E6, 0x4F7A, 0x81E7,
+ 0x4F7B, 0xD9AC, 0x4F7C, 0xD9AE, 0x4F7D, 0x81E8, 0x4F7E, 0xD9AB, 0x4F7F, 0xCAB9, 0x4F80, 0x81E9, 0x4F81, 0x81EA, 0x4F82, 0x81EB,
+ 0x4F83, 0xD9A9, 0x4F84, 0xD6B6, 0x4F85, 0x81EC, 0x4F86, 0x81ED, 0x4F87, 0x81EE, 0x4F88, 0xB3DE, 0x4F89, 0xD9A8, 0x4F8A, 0x81EF,
+ 0x4F8B, 0xC0FD, 0x4F8C, 0x81F0, 0x4F8D, 0xCACC, 0x4F8E, 0x81F1, 0x4F8F, 0xD9AA, 0x4F90, 0x81F2, 0x4F91, 0xD9A7, 0x4F92, 0x81F3,
+ 0x4F93, 0x81F4, 0x4F94, 0xD9B0, 0x4F95, 0x81F5, 0x4F96, 0x81F6, 0x4F97, 0xB6B1, 0x4F98, 0x81F7, 0x4F99, 0x81F8, 0x4F9A, 0x81F9,
+ 0x4F9B, 0xB9A9, 0x4F9C, 0x81FA, 0x4F9D, 0xD2C0, 0x4F9E, 0x81FB, 0x4F9F, 0x81FC, 0x4FA0, 0xCFC0, 0x4FA1, 0x81FD, 0x4FA2, 0x81FE,
+ 0x4FA3, 0xC2C2, 0x4FA4, 0x8240, 0x4FA5, 0xBDC4, 0x4FA6, 0xD5EC, 0x4FA7, 0xB2E0, 0x4FA8, 0xC7C8, 0x4FA9, 0xBFEB, 0x4FAA, 0xD9AD,
+ 0x4FAB, 0x8241, 0x4FAC, 0xD9AF, 0x4FAD, 0x8242, 0x4FAE, 0xCEEA, 0x4FAF, 0xBAEE, 0x4FB0, 0x8243, 0x4FB1, 0x8244, 0x4FB2, 0x8245,
+ 0x4FB3, 0x8246, 0x4FB4, 0x8247, 0x4FB5, 0xC7D6, 0x4FB6, 0x8248, 0x4FB7, 0x8249, 0x4FB8, 0x824A, 0x4FB9, 0x824B, 0x4FBA, 0x824C,
+ 0x4FBB, 0x824D, 0x4FBC, 0x824E, 0x4FBD, 0x824F, 0x4FBE, 0x8250, 0x4FBF, 0xB1E3, 0x4FC0, 0x8251, 0x4FC1, 0x8252, 0x4FC2, 0x8253,
+ 0x4FC3, 0xB4D9, 0x4FC4, 0xB6ED, 0x4FC5, 0xD9B4, 0x4FC6, 0x8254, 0x4FC7, 0x8255, 0x4FC8, 0x8256, 0x4FC9, 0x8257, 0x4FCA, 0xBFA1,
+ 0x4FCB, 0x8258, 0x4FCC, 0x8259, 0x4FCD, 0x825A, 0x4FCE, 0xD9DE, 0x4FCF, 0xC7CE, 0x4FD0, 0xC0FE, 0x4FD1, 0xD9B8, 0x4FD2, 0x825B,
+ 0x4FD3, 0x825C, 0x4FD4, 0x825D, 0x4FD5, 0x825E, 0x4FD6, 0x825F, 0x4FD7, 0xCBD7, 0x4FD8, 0xB7FD, 0x4FD9, 0x8260, 0x4FDA, 0xD9B5,
+ 0x4FDB, 0x8261, 0x4FDC, 0xD9B7, 0x4FDD, 0xB1A3, 0x4FDE, 0xD3E1, 0x4FDF, 0xD9B9, 0x4FE0, 0x8262, 0x4FE1, 0xD0C5, 0x4FE2, 0x8263,
+ 0x4FE3, 0xD9B6, 0x4FE4, 0x8264, 0x4FE5, 0x8265, 0x4FE6, 0xD9B1, 0x4FE7, 0x8266, 0x4FE8, 0xD9B2, 0x4FE9, 0xC1A9, 0x4FEA, 0xD9B3,
+ 0x4FEB, 0x8267, 0x4FEC, 0x8268, 0x4FED, 0xBCF3, 0x4FEE, 0xD0DE, 0x4FEF, 0xB8A9, 0x4FF0, 0x8269, 0x4FF1, 0xBEE3, 0x4FF2, 0x826A,
+ 0x4FF3, 0xD9BD, 0x4FF4, 0x826B, 0x4FF5, 0x826C, 0x4FF6, 0x826D, 0x4FF7, 0x826E, 0x4FF8, 0xD9BA, 0x4FF9, 0x826F, 0x4FFA, 0xB0B3,
+ 0x4FFB, 0x8270, 0x4FFC, 0x8271, 0x4FFD, 0x8272, 0x4FFE, 0xD9C2, 0x4FFF, 0x8273, 0x5000, 0x8274, 0x5001, 0x8275, 0x5002, 0x8276,
+ 0x5003, 0x8277, 0x5004, 0x8278, 0x5005, 0x8279, 0x5006, 0x827A, 0x5007, 0x827B, 0x5008, 0x827C, 0x5009, 0x827D, 0x500A, 0x827E,
+ 0x500B, 0x8280, 0x500C, 0xD9C4, 0x500D, 0xB1B6, 0x500E, 0x8281, 0x500F, 0xD9BF, 0x5010, 0x8282, 0x5011, 0x8283, 0x5012, 0xB5B9,
+ 0x5013, 0x8284, 0x5014, 0xBEF3, 0x5015, 0x8285, 0x5016, 0x8286, 0x5017, 0x8287, 0x5018, 0xCCC8, 0x5019, 0xBAF2, 0x501A, 0xD2D0,
+ 0x501B, 0x8288, 0x501C, 0xD9C3, 0x501D, 0x8289, 0x501E, 0x828A, 0x501F, 0xBDE8, 0x5020, 0x828B, 0x5021, 0xB3AB, 0x5022, 0x828C,
+ 0x5023, 0x828D, 0x5024, 0x828E, 0x5025, 0xD9C5, 0x5026, 0xBEEB, 0x5027, 0x828F, 0x5028, 0xD9C6, 0x5029, 0xD9BB, 0x502A, 0xC4DF,
+ 0x502B, 0x8290, 0x502C, 0xD9BE, 0x502D, 0xD9C1, 0x502E, 0xD9C0, 0x502F, 0x8291, 0x5030, 0x8292, 0x5031, 0x8293, 0x5032, 0x8294,
+ 0x5033, 0x8295, 0x5034, 0x8296, 0x5035, 0x8297, 0x5036, 0x8298, 0x5037, 0x8299, 0x5038, 0x829A, 0x5039, 0x829B, 0x503A, 0xD5AE,
+ 0x503B, 0x829C, 0x503C, 0xD6B5, 0x503D, 0x829D, 0x503E, 0xC7E3, 0x503F, 0x829E, 0x5040, 0x829F, 0x5041, 0x82A0, 0x5042, 0x82A1,
+ 0x5043, 0xD9C8, 0x5044, 0x82A2, 0x5045, 0x82A3, 0x5046, 0x82A4, 0x5047, 0xBCD9, 0x5048, 0xD9CA, 0x5049, 0x82A5, 0x504A, 0x82A6,
+ 0x504B, 0x82A7, 0x504C, 0xD9BC, 0x504D, 0x82A8, 0x504E, 0xD9CB, 0x504F, 0xC6AB, 0x5050, 0x82A9, 0x5051, 0x82AA, 0x5052, 0x82AB,
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+ 0x592B, 0xB7F2, 0x592C, 0x89F8, 0x592D, 0xD8B2, 0x592E, 0xD1EB, 0x592F, 0xBABB, 0x5930, 0x89F9, 0x5931, 0xCAA7, 0x5932, 0x89FA,
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+ 0x593B, 0x89FE, 0x593C, 0xDEC5, 0x593D, 0x8A40, 0x593E, 0x8A41, 0x593F, 0x8A42, 0x5940, 0x8A43, 0x5941, 0xDEC6, 0x5942, 0xDBBC,
+ 0x5943, 0x8A44, 0x5944, 0xD1D9, 0x5945, 0x8A45, 0x5946, 0x8A46, 0x5947, 0xC6E6, 0x5948, 0xC4CE, 0x5949, 0xB7EE, 0x594A, 0x8A47,
+ 0x594B, 0xB7DC, 0x594C, 0x8A48, 0x594D, 0x8A49, 0x594E, 0xBFFC, 0x594F, 0xD7E0, 0x5950, 0x8A4A, 0x5951, 0xC6F5, 0x5952, 0x8A4B,
+ 0x5953, 0x8A4C, 0x5954, 0xB1BC, 0x5955, 0xDEC8, 0x5956, 0xBDB1, 0x5957, 0xCCD7, 0x5958, 0xDECA, 0x5959, 0x8A4D, 0x595A, 0xDEC9,
+ 0x595B, 0x8A4E, 0x595C, 0x8A4F, 0x595D, 0x8A50, 0x595E, 0x8A51, 0x595F, 0x8A52, 0x5960, 0xB5EC, 0x5961, 0x8A53, 0x5962, 0xC9DD,
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+ 0x596B, 0x8A5B, 0x596C, 0x8A5C, 0x596D, 0x8A5D, 0x596E, 0x8A5E, 0x596F, 0x8A5F, 0x5970, 0x8A60, 0x5971, 0x8A61, 0x5972, 0x8A62,
+ 0x5973, 0xC5AE, 0x5974, 0xC5AB, 0x5975, 0x8A63, 0x5976, 0xC4CC, 0x5977, 0x8A64, 0x5978, 0xBCE9, 0x5979, 0xCBFD, 0x597A, 0x8A65,
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+ 0x5983, 0xE5FA, 0x5984, 0xCDFD, 0x5985, 0x8A6B, 0x5986, 0xD7B1, 0x5987, 0xB8BE, 0x5988, 0xC2E8, 0x5989, 0x8A6C, 0x598A, 0xC8D1,
+ 0x598B, 0x8A6D, 0x598C, 0x8A6E, 0x598D, 0xE5FB, 0x598E, 0x8A6F, 0x598F, 0x8A70, 0x5990, 0x8A71, 0x5991, 0x8A72, 0x5992, 0xB6CA,
+ 0x5993, 0xBCCB, 0x5994, 0x8A73, 0x5995, 0x8A74, 0x5996, 0xD1FD, 0x5997, 0xE6A1, 0x5998, 0x8A75, 0x5999, 0xC3EE, 0x599A, 0x8A76,
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+ 0x59A3, 0xE5FE, 0x59A4, 0xE6A5, 0x59A5, 0xCDD7, 0x59A6, 0x8A7E, 0x59A7, 0x8A80, 0x59A8, 0xB7C1, 0x59A9, 0xE5FC, 0x59AA, 0xE5FD,
+ 0x59AB, 0xE6A3, 0x59AC, 0x8A81, 0x59AD, 0x8A82, 0x59AE, 0xC4DD, 0x59AF, 0xE6A8, 0x59B0, 0x8A83, 0x59B1, 0x8A84, 0x59B2, 0xE6A7,
+ 0x59B3, 0x8A85, 0x59B4, 0x8A86, 0x59B5, 0x8A87, 0x59B6, 0x8A88, 0x59B7, 0x8A89, 0x59B8, 0x8A8A, 0x59B9, 0xC3C3, 0x59BA, 0x8A8B,
+ 0x59BB, 0xC6DE, 0x59BC, 0x8A8C, 0x59BD, 0x8A8D, 0x59BE, 0xE6AA, 0x59BF, 0x8A8E, 0x59C0, 0x8A8F, 0x59C1, 0x8A90, 0x59C2, 0x8A91,
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+ 0x59D3, 0xD0D5, 0x59D4, 0xCEAF, 0x59D5, 0x8A9C, 0x59D6, 0x8A9D, 0x59D7, 0xE6A9, 0x59D8, 0xE6B0, 0x59D9, 0x8A9E, 0x59DA, 0xD2A6,
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+ 0x59F3, 0x8AB1, 0x59F4, 0x8AB2, 0x59F5, 0x8AB3, 0x59F6, 0x8AB4, 0x59F7, 0x8AB5, 0x59F8, 0x8AB6, 0x59F9, 0xE6B1, 0x59FA, 0x8AB7,
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+ 0x5A0B, 0x8ABE, 0x5A0C, 0xE6B2, 0x5A0D, 0x8ABF, 0x5A0E, 0x8AC0, 0x5A0F, 0x8AC1, 0x5A10, 0x8AC2, 0x5A11, 0xE6B6, 0x5A12, 0x8AC3,
+ 0x5A13, 0xE6B8, 0x5A14, 0x8AC4, 0x5A15, 0x8AC5, 0x5A16, 0x8AC6, 0x5A17, 0x8AC7, 0x5A18, 0xC4EF, 0x5A19, 0x8AC8, 0x5A1A, 0x8AC9,
+ 0x5A1B, 0x8ACA, 0x5A1C, 0xC4C8, 0x5A1D, 0x8ACB, 0x5A1E, 0x8ACC, 0x5A1F, 0xBEEA, 0x5A20, 0xC9EF, 0x5A21, 0x8ACD, 0x5A22, 0x8ACE,
+ 0x5A23, 0xE6B7, 0x5A24, 0x8ACF, 0x5A25, 0xB6F0, 0x5A26, 0x8AD0, 0x5A27, 0x8AD1, 0x5A28, 0x8AD2, 0x5A29, 0xC3E4, 0x5A2A, 0x8AD3,
+ 0x5A2B, 0x8AD4, 0x5A2C, 0x8AD5, 0x5A2D, 0x8AD6, 0x5A2E, 0x8AD7, 0x5A2F, 0x8AD8, 0x5A30, 0x8AD9, 0x5A31, 0xD3E9, 0x5A32, 0xE6B4,
+ 0x5A33, 0x8ADA, 0x5A34, 0xE6B5, 0x5A35, 0x8ADB, 0x5A36, 0xC8A2, 0x5A37, 0x8ADC, 0x5A38, 0x8ADD, 0x5A39, 0x8ADE, 0x5A3A, 0x8ADF,
+ 0x5A3B, 0x8AE0, 0x5A3C, 0xE6BD, 0x5A3D, 0x8AE1, 0x5A3E, 0x8AE2, 0x5A3F, 0x8AE3, 0x5A40, 0xE6B9, 0x5A41, 0x8AE4, 0x5A42, 0x8AE5,
+ 0x5A43, 0x8AE6, 0x5A44, 0x8AE7, 0x5A45, 0x8AE8, 0x5A46, 0xC6C5, 0x5A47, 0x8AE9, 0x5A48, 0x8AEA, 0x5A49, 0xCDF1, 0x5A4A, 0xE6BB,
+ 0x5A4B, 0x8AEB, 0x5A4C, 0x8AEC, 0x5A4D, 0x8AED, 0x5A4E, 0x8AEE, 0x5A4F, 0x8AEF, 0x5A50, 0x8AF0, 0x5A51, 0x8AF1, 0x5A52, 0x8AF2,
+ 0x5A53, 0x8AF3, 0x5A54, 0x8AF4, 0x5A55, 0xE6BC, 0x5A56, 0x8AF5, 0x5A57, 0x8AF6, 0x5A58, 0x8AF7, 0x5A59, 0x8AF8, 0x5A5A, 0xBBE9,
+ 0x5A5B, 0x8AF9, 0x5A5C, 0x8AFA, 0x5A5D, 0x8AFB, 0x5A5E, 0x8AFC, 0x5A5F, 0x8AFD, 0x5A60, 0x8AFE, 0x5A61, 0x8B40, 0x5A62, 0xE6BE,
+ 0x5A63, 0x8B41, 0x5A64, 0x8B42, 0x5A65, 0x8B43, 0x5A66, 0x8B44, 0x5A67, 0xE6BA, 0x5A68, 0x8B45, 0x5A69, 0x8B46, 0x5A6A, 0xC0B7,
+ 0x5A6B, 0x8B47, 0x5A6C, 0x8B48, 0x5A6D, 0x8B49, 0x5A6E, 0x8B4A, 0x5A6F, 0x8B4B, 0x5A70, 0x8B4C, 0x5A71, 0x8B4D, 0x5A72, 0x8B4E,
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+ 0x5A7B, 0x8B52, 0x5A7C, 0x8B53, 0x5A7D, 0x8B54, 0x5A7E, 0x8B55, 0x5A7F, 0xD0F6, 0x5A80, 0x8B56, 0x5A81, 0x8B57, 0x5A82, 0x8B58,
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+ 0x5A9B, 0xE6C2, 0x5A9C, 0x8B6F, 0x5A9D, 0x8B70, 0x5A9E, 0x8B71, 0x5A9F, 0x8B72, 0x5AA0, 0x8B73, 0x5AA1, 0x8B74, 0x5AA2, 0x8B75,
+ 0x5AA3, 0x8B76, 0x5AA4, 0x8B77, 0x5AA5, 0x8B78, 0x5AA6, 0x8B79, 0x5AA7, 0x8B7A, 0x5AA8, 0x8B7B, 0x5AA9, 0x8B7C, 0x5AAA, 0xE6C1,
+ 0x5AAB, 0x8B7D, 0x5AAC, 0x8B7E, 0x5AAD, 0x8B80, 0x5AAE, 0x8B81, 0x5AAF, 0x8B82, 0x5AB0, 0x8B83, 0x5AB1, 0x8B84, 0x5AB2, 0xE6C7,
+ 0x5AB3, 0xCFB1, 0x5AB4, 0x8B85, 0x5AB5, 0xEBF4, 0x5AB6, 0x8B86, 0x5AB7, 0x8B87, 0x5AB8, 0xE6CA, 0x5AB9, 0x8B88, 0x5ABA, 0x8B89,
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+ 0x5ACB, 0x8B96, 0x5ACC, 0xCFD3, 0x5ACD, 0x8B97, 0x5ACE, 0x8B98, 0x5ACF, 0x8B99, 0x5AD0, 0x8B9A, 0x5AD1, 0x8B9B, 0x5AD2, 0xE6C8,
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+ 0x5ADB, 0x8BA1, 0x5ADC, 0xE6D1, 0x5ADD, 0x8BA2, 0x5ADE, 0x8BA3, 0x5ADF, 0x8BA4, 0x5AE0, 0xE6CB, 0x5AE1, 0xB5D5, 0x5AE2, 0x8BA5,
+ 0x5AE3, 0xE6CC, 0x5AE4, 0x8BA6, 0x5AE5, 0x8BA7, 0x5AE6, 0xE6CF, 0x5AE7, 0x8BA8, 0x5AE8, 0x8BA9, 0x5AE9, 0xC4DB, 0x5AEA, 0x8BAA,
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+ 0x5AF3, 0x8BB1, 0x5AF4, 0x8BB2, 0x5AF5, 0x8BB3, 0x5AF6, 0x8BB4, 0x5AF7, 0x8BB5, 0x5AF8, 0x8BB6, 0x5AF9, 0x8BB7, 0x5AFA, 0x8BB8,
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+ 0x5B03, 0x8BC1, 0x5B04, 0x8BC2, 0x5B05, 0x8BC3, 0x5B06, 0x8BC4, 0x5B07, 0x8BC5, 0x5B08, 0x8BC6, 0x5B09, 0xE6D2, 0x5B0A, 0x8BC7,
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+ 0x5B13, 0x8BD0, 0x5B14, 0x8BD1, 0x5B15, 0x8BD2, 0x5B16, 0xE6D4, 0x5B17, 0xE6D3, 0x5B18, 0x8BD3, 0x5B19, 0x8BD4, 0x5B1A, 0x8BD5,
+ 0x5B1B, 0x8BD6, 0x5B1C, 0x8BD7, 0x5B1D, 0x8BD8, 0x5B1E, 0x8BD9, 0x5B1F, 0x8BDA, 0x5B20, 0x8BDB, 0x5B21, 0x8BDC, 0x5B22, 0x8BDD,
+ 0x5B23, 0x8BDE, 0x5B24, 0x8BDF, 0x5B25, 0x8BE0, 0x5B26, 0x8BE1, 0x5B27, 0x8BE2, 0x5B28, 0x8BE3, 0x5B29, 0x8BE4, 0x5B2A, 0x8BE5,
+ 0x5B2B, 0x8BE6, 0x5B2C, 0x8BE7, 0x5B2D, 0x8BE8, 0x5B2E, 0x8BE9, 0x5B2F, 0x8BEA, 0x5B30, 0x8BEB, 0x5B31, 0x8BEC, 0x5B32, 0xE6D5,
+ 0x5B33, 0x8BED, 0x5B34, 0xD9F8, 0x5B35, 0x8BEE, 0x5B36, 0x8BEF, 0x5B37, 0xE6D6, 0x5B38, 0x8BF0, 0x5B39, 0x8BF1, 0x5B3A, 0x8BF2,
+ 0x5B3B, 0x8BF3, 0x5B3C, 0x8BF4, 0x5B3D, 0x8BF5, 0x5B3E, 0x8BF6, 0x5B3F, 0x8BF7, 0x5B40, 0xE6D7, 0x5B41, 0x8BF8, 0x5B42, 0x8BF9,
+ 0x5B43, 0x8BFA, 0x5B44, 0x8BFB, 0x5B45, 0x8BFC, 0x5B46, 0x8BFD, 0x5B47, 0x8BFE, 0x5B48, 0x8C40, 0x5B49, 0x8C41, 0x5B4A, 0x8C42,
+ 0x5B4B, 0x8C43, 0x5B4C, 0x8C44, 0x5B4D, 0x8C45, 0x5B4E, 0x8C46, 0x5B4F, 0x8C47, 0x5B50, 0xD7D3, 0x5B51, 0xE6DD, 0x5B52, 0x8C48,
+ 0x5B53, 0xE6DE, 0x5B54, 0xBFD7, 0x5B55, 0xD4D0, 0x5B56, 0x8C49, 0x5B57, 0xD7D6, 0x5B58, 0xB4E6, 0x5B59, 0xCBEF, 0x5B5A, 0xE6DA,
+ 0x5B5B, 0xD8C3, 0x5B5C, 0xD7CE, 0x5B5D, 0xD0A2, 0x5B5E, 0x8C4A, 0x5B5F, 0xC3CF, 0x5B60, 0x8C4B, 0x5B61, 0x8C4C, 0x5B62, 0xE6DF,
+ 0x5B63, 0xBCBE, 0x5B64, 0xB9C2, 0x5B65, 0xE6DB, 0x5B66, 0xD1A7, 0x5B67, 0x8C4D, 0x5B68, 0x8C4E, 0x5B69, 0xBAA2, 0x5B6A, 0xC2CF,
+ 0x5B6B, 0x8C4F, 0x5B6C, 0xD8AB, 0x5B6D, 0x8C50, 0x5B6E, 0x8C51, 0x5B6F, 0x8C52, 0x5B70, 0xCAEB, 0x5B71, 0xE5EE, 0x5B72, 0x8C53,
+ 0x5B73, 0xE6DC, 0x5B74, 0x8C54, 0x5B75, 0xB7F5, 0x5B76, 0x8C55, 0x5B77, 0x8C56, 0x5B78, 0x8C57, 0x5B79, 0x8C58, 0x5B7A, 0xC8E6,
+ 0x5B7B, 0x8C59, 0x5B7C, 0x8C5A, 0x5B7D, 0xC4F5, 0x5B7E, 0x8C5B, 0x5B7F, 0x8C5C, 0x5B80, 0xE5B2, 0x5B81, 0xC4FE, 0x5B82, 0x8C5D,
+ 0x5B83, 0xCBFC, 0x5B84, 0xE5B3, 0x5B85, 0xD5AC, 0x5B86, 0x8C5E, 0x5B87, 0xD3EE, 0x5B88, 0xCAD8, 0x5B89, 0xB0B2, 0x5B8A, 0x8C5F,
+ 0x5B8B, 0xCBCE, 0x5B8C, 0xCDEA, 0x5B8D, 0x8C60, 0x5B8E, 0x8C61, 0x5B8F, 0xBAEA, 0x5B90, 0x8C62, 0x5B91, 0x8C63, 0x5B92, 0x8C64,
+ 0x5B93, 0xE5B5, 0x5B94, 0x8C65, 0x5B95, 0xE5B4, 0x5B96, 0x8C66, 0x5B97, 0xD7DA, 0x5B98, 0xB9D9, 0x5B99, 0xD6E6, 0x5B9A, 0xB6A8,
+ 0x5B9B, 0xCDF0, 0x5B9C, 0xD2CB, 0x5B9D, 0xB1A6, 0x5B9E, 0xCAB5, 0x5B9F, 0x8C67, 0x5BA0, 0xB3E8, 0x5BA1, 0xC9F3, 0x5BA2, 0xBFCD,
+ 0x5BA3, 0xD0FB, 0x5BA4, 0xCAD2, 0x5BA5, 0xE5B6, 0x5BA6, 0xBBC2, 0x5BA7, 0x8C68, 0x5BA8, 0x8C69, 0x5BA9, 0x8C6A, 0x5BAA, 0xCFDC,
+ 0x5BAB, 0xB9AC, 0x5BAC, 0x8C6B, 0x5BAD, 0x8C6C, 0x5BAE, 0x8C6D, 0x5BAF, 0x8C6E, 0x5BB0, 0xD4D7, 0x5BB1, 0x8C6F, 0x5BB2, 0x8C70,
+ 0x5BB3, 0xBAA6, 0x5BB4, 0xD1E7, 0x5BB5, 0xCFFC, 0x5BB6, 0xBCD2, 0x5BB7, 0x8C71, 0x5BB8, 0xE5B7, 0x5BB9, 0xC8DD, 0x5BBA, 0x8C72,
+ 0x5BBB, 0x8C73, 0x5BBC, 0x8C74, 0x5BBD, 0xBFED, 0x5BBE, 0xB1F6, 0x5BBF, 0xCBDE, 0x5BC0, 0x8C75, 0x5BC1, 0x8C76, 0x5BC2, 0xBCC5,
+ 0x5BC3, 0x8C77, 0x5BC4, 0xBCC4, 0x5BC5, 0xD2FA, 0x5BC6, 0xC3DC, 0x5BC7, 0xBFDC, 0x5BC8, 0x8C78, 0x5BC9, 0x8C79, 0x5BCA, 0x8C7A,
+ 0x5BCB, 0x8C7B, 0x5BCC, 0xB8BB, 0x5BCD, 0x8C7C, 0x5BCE, 0x8C7D, 0x5BCF, 0x8C7E, 0x5BD0, 0xC3C2, 0x5BD1, 0x8C80, 0x5BD2, 0xBAAE,
+ 0x5BD3, 0xD4A2, 0x5BD4, 0x8C81, 0x5BD5, 0x8C82, 0x5BD6, 0x8C83, 0x5BD7, 0x8C84, 0x5BD8, 0x8C85, 0x5BD9, 0x8C86, 0x5BDA, 0x8C87,
+ 0x5BDB, 0x8C88, 0x5BDC, 0x8C89, 0x5BDD, 0xC7DE, 0x5BDE, 0xC4AF, 0x5BDF, 0xB2EC, 0x5BE0, 0x8C8A, 0x5BE1, 0xB9D1, 0x5BE2, 0x8C8B,
+ 0x5BE3, 0x8C8C, 0x5BE4, 0xE5BB, 0x5BE5, 0xC1C8, 0x5BE6, 0x8C8D, 0x5BE7, 0x8C8E, 0x5BE8, 0xD5AF, 0x5BE9, 0x8C8F, 0x5BEA, 0x8C90,
+ 0x5BEB, 0x8C91, 0x5BEC, 0x8C92, 0x5BED, 0x8C93, 0x5BEE, 0xE5BC, 0x5BEF, 0x8C94, 0x5BF0, 0xE5BE, 0x5BF1, 0x8C95, 0x5BF2, 0x8C96,
+ 0x5BF3, 0x8C97, 0x5BF4, 0x8C98, 0x5BF5, 0x8C99, 0x5BF6, 0x8C9A, 0x5BF7, 0x8C9B, 0x5BF8, 0xB4E7, 0x5BF9, 0xB6D4, 0x5BFA, 0xCBC2,
+ 0x5BFB, 0xD1B0, 0x5BFC, 0xB5BC, 0x5BFD, 0x8C9C, 0x5BFE, 0x8C9D, 0x5BFF, 0xCAD9, 0x5C00, 0x8C9E, 0x5C01, 0xB7E2, 0x5C02, 0x8C9F,
+ 0x5C03, 0x8CA0, 0x5C04, 0xC9E4, 0x5C05, 0x8CA1, 0x5C06, 0xBDAB, 0x5C07, 0x8CA2, 0x5C08, 0x8CA3, 0x5C09, 0xCEBE, 0x5C0A, 0xD7F0,
+ 0x5C0B, 0x8CA4, 0x5C0C, 0x8CA5, 0x5C0D, 0x8CA6, 0x5C0E, 0x8CA7, 0x5C0F, 0xD0A1, 0x5C10, 0x8CA8, 0x5C11, 0xC9D9, 0x5C12, 0x8CA9,
+ 0x5C13, 0x8CAA, 0x5C14, 0xB6FB, 0x5C15, 0xE6D8, 0x5C16, 0xBCE2, 0x5C17, 0x8CAB, 0x5C18, 0xB3BE, 0x5C19, 0x8CAC, 0x5C1A, 0xC9D0,
+ 0x5C1B, 0x8CAD, 0x5C1C, 0xE6D9, 0x5C1D, 0xB3A2, 0x5C1E, 0x8CAE, 0x5C1F, 0x8CAF, 0x5C20, 0x8CB0, 0x5C21, 0x8CB1, 0x5C22, 0xDECC,
+ 0x5C23, 0x8CB2, 0x5C24, 0xD3C8, 0x5C25, 0xDECD, 0x5C26, 0x8CB3, 0x5C27, 0xD2A2, 0x5C28, 0x8CB4, 0x5C29, 0x8CB5, 0x5C2A, 0x8CB6,
+ 0x5C2B, 0x8CB7, 0x5C2C, 0xDECE, 0x5C2D, 0x8CB8, 0x5C2E, 0x8CB9, 0x5C2F, 0x8CBA, 0x5C30, 0x8CBB, 0x5C31, 0xBECD, 0x5C32, 0x8CBC,
+ 0x5C33, 0x8CBD, 0x5C34, 0xDECF, 0x5C35, 0x8CBE, 0x5C36, 0x8CBF, 0x5C37, 0x8CC0, 0x5C38, 0xCAAC, 0x5C39, 0xD2FC, 0x5C3A, 0xB3DF,
+ 0x5C3B, 0xE5EA, 0x5C3C, 0xC4E1, 0x5C3D, 0xBEA1, 0x5C3E, 0xCEB2, 0x5C3F, 0xC4F2, 0x5C40, 0xBED6, 0x5C41, 0xC6A8, 0x5C42, 0xB2E3,
+ 0x5C43, 0x8CC1, 0x5C44, 0x8CC2, 0x5C45, 0xBED3, 0x5C46, 0x8CC3, 0x5C47, 0x8CC4, 0x5C48, 0xC7FC, 0x5C49, 0xCCEB, 0x5C4A, 0xBDEC,
+ 0x5C4B, 0xCEDD, 0x5C4C, 0x8CC5, 0x5C4D, 0x8CC6, 0x5C4E, 0xCABA, 0x5C4F, 0xC6C1, 0x5C50, 0xE5EC, 0x5C51, 0xD0BC, 0x5C52, 0x8CC7,
+ 0x5C53, 0x8CC8, 0x5C54, 0x8CC9, 0x5C55, 0xD5B9, 0x5C56, 0x8CCA, 0x5C57, 0x8CCB, 0x5C58, 0x8CCC, 0x5C59, 0xE5ED, 0x5C5A, 0x8CCD,
+ 0x5C5B, 0x8CCE, 0x5C5C, 0x8CCF, 0x5C5D, 0x8CD0, 0x5C5E, 0xCAF4, 0x5C5F, 0x8CD1, 0x5C60, 0xCDC0, 0x5C61, 0xC2C5, 0x5C62, 0x8CD2,
+ 0x5C63, 0xE5EF, 0x5C64, 0x8CD3, 0x5C65, 0xC2C4, 0x5C66, 0xE5F0, 0x5C67, 0x8CD4, 0x5C68, 0x8CD5, 0x5C69, 0x8CD6, 0x5C6A, 0x8CD7,
+ 0x5C6B, 0x8CD8, 0x5C6C, 0x8CD9, 0x5C6D, 0x8CDA, 0x5C6E, 0xE5F8, 0x5C6F, 0xCDCD, 0x5C70, 0x8CDB, 0x5C71, 0xC9BD, 0x5C72, 0x8CDC,
+ 0x5C73, 0x8CDD, 0x5C74, 0x8CDE, 0x5C75, 0x8CDF, 0x5C76, 0x8CE0, 0x5C77, 0x8CE1, 0x5C78, 0x8CE2, 0x5C79, 0xD2D9, 0x5C7A, 0xE1A8,
+ 0x5C7B, 0x8CE3, 0x5C7C, 0x8CE4, 0x5C7D, 0x8CE5, 0x5C7E, 0x8CE6, 0x5C7F, 0xD3EC, 0x5C80, 0x8CE7, 0x5C81, 0xCBEA, 0x5C82, 0xC6F1,
+ 0x5C83, 0x8CE8, 0x5C84, 0x8CE9, 0x5C85, 0x8CEA, 0x5C86, 0x8CEB, 0x5C87, 0x8CEC, 0x5C88, 0xE1AC, 0x5C89, 0x8CED, 0x5C8A, 0x8CEE,
+ 0x5C8B, 0x8CEF, 0x5C8C, 0xE1A7, 0x5C8D, 0xE1A9, 0x5C8E, 0x8CF0, 0x5C8F, 0x8CF1, 0x5C90, 0xE1AA, 0x5C91, 0xE1AF, 0x5C92, 0x8CF2,
+ 0x5C93, 0x8CF3, 0x5C94, 0xB2ED, 0x5C95, 0x8CF4, 0x5C96, 0xE1AB, 0x5C97, 0xB8DA, 0x5C98, 0xE1AD, 0x5C99, 0xE1AE, 0x5C9A, 0xE1B0,
+ 0x5C9B, 0xB5BA, 0x5C9C, 0xE1B1, 0x5C9D, 0x8CF5, 0x5C9E, 0x8CF6, 0x5C9F, 0x8CF7, 0x5CA0, 0x8CF8, 0x5CA1, 0x8CF9, 0x5CA2, 0xE1B3,
+ 0x5CA3, 0xE1B8, 0x5CA4, 0x8CFA, 0x5CA5, 0x8CFB, 0x5CA6, 0x8CFC, 0x5CA7, 0x8CFD, 0x5CA8, 0x8CFE, 0x5CA9, 0xD1D2, 0x5CAA, 0x8D40,
+ 0x5CAB, 0xE1B6, 0x5CAC, 0xE1B5, 0x5CAD, 0xC1EB, 0x5CAE, 0x8D41, 0x5CAF, 0x8D42, 0x5CB0, 0x8D43, 0x5CB1, 0xE1B7, 0x5CB2, 0x8D44,
+ 0x5CB3, 0xD4C0, 0x5CB4, 0x8D45, 0x5CB5, 0xE1B2, 0x5CB6, 0x8D46, 0x5CB7, 0xE1BA, 0x5CB8, 0xB0B6, 0x5CB9, 0x8D47, 0x5CBA, 0x8D48,
+ 0x5CBB, 0x8D49, 0x5CBC, 0x8D4A, 0x5CBD, 0xE1B4, 0x5CBE, 0x8D4B, 0x5CBF, 0xBFF9, 0x5CC0, 0x8D4C, 0x5CC1, 0xE1B9, 0x5CC2, 0x8D4D,
+ 0x5CC3, 0x8D4E, 0x5CC4, 0xE1BB, 0x5CC5, 0x8D4F, 0x5CC6, 0x8D50, 0x5CC7, 0x8D51, 0x5CC8, 0x8D52, 0x5CC9, 0x8D53, 0x5CCA, 0x8D54,
+ 0x5CCB, 0xE1BE, 0x5CCC, 0x8D55, 0x5CCD, 0x8D56, 0x5CCE, 0x8D57, 0x5CCF, 0x8D58, 0x5CD0, 0x8D59, 0x5CD1, 0x8D5A, 0x5CD2, 0xE1BC,
+ 0x5CD3, 0x8D5B, 0x5CD4, 0x8D5C, 0x5CD5, 0x8D5D, 0x5CD6, 0x8D5E, 0x5CD7, 0x8D5F, 0x5CD8, 0x8D60, 0x5CD9, 0xD6C5, 0x5CDA, 0x8D61,
+ 0x5CDB, 0x8D62, 0x5CDC, 0x8D63, 0x5CDD, 0x8D64, 0x5CDE, 0x8D65, 0x5CDF, 0x8D66, 0x5CE0, 0x8D67, 0x5CE1, 0xCFBF, 0x5CE2, 0x8D68,
+ 0x5CE3, 0x8D69, 0x5CE4, 0xE1BD, 0x5CE5, 0xE1BF, 0x5CE6, 0xC2CD, 0x5CE7, 0x8D6A, 0x5CE8, 0xB6EB, 0x5CE9, 0x8D6B, 0x5CEA, 0xD3F8,
+ 0x5CEB, 0x8D6C, 0x5CEC, 0x8D6D, 0x5CED, 0xC7CD, 0x5CEE, 0x8D6E, 0x5CEF, 0x8D6F, 0x5CF0, 0xB7E5, 0x5CF1, 0x8D70, 0x5CF2, 0x8D71,
+ 0x5CF3, 0x8D72, 0x5CF4, 0x8D73, 0x5CF5, 0x8D74, 0x5CF6, 0x8D75, 0x5CF7, 0x8D76, 0x5CF8, 0x8D77, 0x5CF9, 0x8D78, 0x5CFA, 0x8D79,
+ 0x5CFB, 0xBEFE, 0x5CFC, 0x8D7A, 0x5CFD, 0x8D7B, 0x5CFE, 0x8D7C, 0x5CFF, 0x8D7D, 0x5D00, 0x8D7E, 0x5D01, 0x8D80, 0x5D02, 0xE1C0,
+ 0x5D03, 0xE1C1, 0x5D04, 0x8D81, 0x5D05, 0x8D82, 0x5D06, 0xE1C7, 0x5D07, 0xB3E7, 0x5D08, 0x8D83, 0x5D09, 0x8D84, 0x5D0A, 0x8D85,
+ 0x5D0B, 0x8D86, 0x5D0C, 0x8D87, 0x5D0D, 0x8D88, 0x5D0E, 0xC6E9, 0x5D0F, 0x8D89, 0x5D10, 0x8D8A, 0x5D11, 0x8D8B, 0x5D12, 0x8D8C,
+ 0x5D13, 0x8D8D, 0x5D14, 0xB4DE, 0x5D15, 0x8D8E, 0x5D16, 0xD1C2, 0x5D17, 0x8D8F, 0x5D18, 0x8D90, 0x5D19, 0x8D91, 0x5D1A, 0x8D92,
+ 0x5D1B, 0xE1C8, 0x5D1C, 0x8D93, 0x5D1D, 0x8D94, 0x5D1E, 0xE1C6, 0x5D1F, 0x8D95, 0x5D20, 0x8D96, 0x5D21, 0x8D97, 0x5D22, 0x8D98,
+ 0x5D23, 0x8D99, 0x5D24, 0xE1C5, 0x5D25, 0x8D9A, 0x5D26, 0xE1C3, 0x5D27, 0xE1C2, 0x5D28, 0x8D9B, 0x5D29, 0xB1C0, 0x5D2A, 0x8D9C,
+ 0x5D2B, 0x8D9D, 0x5D2C, 0x8D9E, 0x5D2D, 0xD5B8, 0x5D2E, 0xE1C4, 0x5D2F, 0x8D9F, 0x5D30, 0x8DA0, 0x5D31, 0x8DA1, 0x5D32, 0x8DA2,
+ 0x5D33, 0x8DA3, 0x5D34, 0xE1CB, 0x5D35, 0x8DA4, 0x5D36, 0x8DA5, 0x5D37, 0x8DA6, 0x5D38, 0x8DA7, 0x5D39, 0x8DA8, 0x5D3A, 0x8DA9,
+ 0x5D3B, 0x8DAA, 0x5D3C, 0x8DAB, 0x5D3D, 0xE1CC, 0x5D3E, 0xE1CA, 0x5D3F, 0x8DAC, 0x5D40, 0x8DAD, 0x5D41, 0x8DAE, 0x5D42, 0x8DAF,
+ 0x5D43, 0x8DB0, 0x5D44, 0x8DB1, 0x5D45, 0x8DB2, 0x5D46, 0x8DB3, 0x5D47, 0xEFFA, 0x5D48, 0x8DB4, 0x5D49, 0x8DB5, 0x5D4A, 0xE1D3,
+ 0x5D4B, 0xE1D2, 0x5D4C, 0xC7B6, 0x5D4D, 0x8DB6, 0x5D4E, 0x8DB7, 0x5D4F, 0x8DB8, 0x5D50, 0x8DB9, 0x5D51, 0x8DBA, 0x5D52, 0x8DBB,
+ 0x5D53, 0x8DBC, 0x5D54, 0x8DBD, 0x5D55, 0x8DBE, 0x5D56, 0x8DBF, 0x5D57, 0x8DC0, 0x5D58, 0xE1C9, 0x5D59, 0x8DC1, 0x5D5A, 0x8DC2,
+ 0x5D5B, 0xE1CE, 0x5D5C, 0x8DC3, 0x5D5D, 0xE1D0, 0x5D5E, 0x8DC4, 0x5D5F, 0x8DC5, 0x5D60, 0x8DC6, 0x5D61, 0x8DC7, 0x5D62, 0x8DC8,
+ 0x5D63, 0x8DC9, 0x5D64, 0x8DCA, 0x5D65, 0x8DCB, 0x5D66, 0x8DCC, 0x5D67, 0x8DCD, 0x5D68, 0x8DCE, 0x5D69, 0xE1D4, 0x5D6A, 0x8DCF,
+ 0x5D6B, 0xE1D1, 0x5D6C, 0xE1CD, 0x5D6D, 0x8DD0, 0x5D6E, 0x8DD1, 0x5D6F, 0xE1CF, 0x5D70, 0x8DD2, 0x5D71, 0x8DD3, 0x5D72, 0x8DD4,
+ 0x5D73, 0x8DD5, 0x5D74, 0xE1D5, 0x5D75, 0x8DD6, 0x5D76, 0x8DD7, 0x5D77, 0x8DD8, 0x5D78, 0x8DD9, 0x5D79, 0x8DDA, 0x5D7A, 0x8DDB,
+ 0x5D7B, 0x8DDC, 0x5D7C, 0x8DDD, 0x5D7D, 0x8DDE, 0x5D7E, 0x8DDF, 0x5D7F, 0x8DE0, 0x5D80, 0x8DE1, 0x5D81, 0x8DE2, 0x5D82, 0xE1D6,
+ 0x5D83, 0x8DE3, 0x5D84, 0x8DE4, 0x5D85, 0x8DE5, 0x5D86, 0x8DE6, 0x5D87, 0x8DE7, 0x5D88, 0x8DE8, 0x5D89, 0x8DE9, 0x5D8A, 0x8DEA,
+ 0x5D8B, 0x8DEB, 0x5D8C, 0x8DEC, 0x5D8D, 0x8DED, 0x5D8E, 0x8DEE, 0x5D8F, 0x8DEF, 0x5D90, 0x8DF0, 0x5D91, 0x8DF1, 0x5D92, 0x8DF2,
+ 0x5D93, 0x8DF3, 0x5D94, 0x8DF4, 0x5D95, 0x8DF5, 0x5D96, 0x8DF6, 0x5D97, 0x8DF7, 0x5D98, 0x8DF8, 0x5D99, 0xE1D7, 0x5D9A, 0x8DF9,
+ 0x5D9B, 0x8DFA, 0x5D9C, 0x8DFB, 0x5D9D, 0xE1D8, 0x5D9E, 0x8DFC, 0x5D9F, 0x8DFD, 0x5DA0, 0x8DFE, 0x5DA1, 0x8E40, 0x5DA2, 0x8E41,
+ 0x5DA3, 0x8E42, 0x5DA4, 0x8E43, 0x5DA5, 0x8E44, 0x5DA6, 0x8E45, 0x5DA7, 0x8E46, 0x5DA8, 0x8E47, 0x5DA9, 0x8E48, 0x5DAA, 0x8E49,
+ 0x5DAB, 0x8E4A, 0x5DAC, 0x8E4B, 0x5DAD, 0x8E4C, 0x5DAE, 0x8E4D, 0x5DAF, 0x8E4E, 0x5DB0, 0x8E4F, 0x5DB1, 0x8E50, 0x5DB2, 0x8E51,
+ 0x5DB3, 0x8E52, 0x5DB4, 0x8E53, 0x5DB5, 0x8E54, 0x5DB6, 0x8E55, 0x5DB7, 0xE1DA, 0x5DB8, 0x8E56, 0x5DB9, 0x8E57, 0x5DBA, 0x8E58,
+ 0x5DBB, 0x8E59, 0x5DBC, 0x8E5A, 0x5DBD, 0x8E5B, 0x5DBE, 0x8E5C, 0x5DBF, 0x8E5D, 0x5DC0, 0x8E5E, 0x5DC1, 0x8E5F, 0x5DC2, 0x8E60,
+ 0x5DC3, 0x8E61, 0x5DC4, 0x8E62, 0x5DC5, 0xE1DB, 0x5DC6, 0x8E63, 0x5DC7, 0x8E64, 0x5DC8, 0x8E65, 0x5DC9, 0x8E66, 0x5DCA, 0x8E67,
+ 0x5DCB, 0x8E68, 0x5DCC, 0x8E69, 0x5DCD, 0xCEA1, 0x5DCE, 0x8E6A, 0x5DCF, 0x8E6B, 0x5DD0, 0x8E6C, 0x5DD1, 0x8E6D, 0x5DD2, 0x8E6E,
+ 0x5DD3, 0x8E6F, 0x5DD4, 0x8E70, 0x5DD5, 0x8E71, 0x5DD6, 0x8E72, 0x5DD7, 0x8E73, 0x5DD8, 0x8E74, 0x5DD9, 0x8E75, 0x5DDA, 0x8E76,
+ 0x5DDB, 0xE7DD, 0x5DDC, 0x8E77, 0x5DDD, 0xB4A8, 0x5DDE, 0xD6DD, 0x5DDF, 0x8E78, 0x5DE0, 0x8E79, 0x5DE1, 0xD1B2, 0x5DE2, 0xB3B2,
+ 0x5DE3, 0x8E7A, 0x5DE4, 0x8E7B, 0x5DE5, 0xB9A4, 0x5DE6, 0xD7F3, 0x5DE7, 0xC7C9, 0x5DE8, 0xBEDE, 0x5DE9, 0xB9AE, 0x5DEA, 0x8E7C,
+ 0x5DEB, 0xCED7, 0x5DEC, 0x8E7D, 0x5DED, 0x8E7E, 0x5DEE, 0xB2EE, 0x5DEF, 0xDBCF, 0x5DF0, 0x8E80, 0x5DF1, 0xBCBA, 0x5DF2, 0xD2D1,
+ 0x5DF3, 0xCBC8, 0x5DF4, 0xB0CD, 0x5DF5, 0x8E81, 0x5DF6, 0x8E82, 0x5DF7, 0xCFEF, 0x5DF8, 0x8E83, 0x5DF9, 0x8E84, 0x5DFA, 0x8E85,
+ 0x5DFB, 0x8E86, 0x5DFC, 0x8E87, 0x5DFD, 0xD9E3, 0x5DFE, 0xBDED, 0x5DFF, 0x8E88, 0x5E00, 0x8E89, 0x5E01, 0xB1D2, 0x5E02, 0xCAD0,
+ 0x5E03, 0xB2BC, 0x5E04, 0x8E8A, 0x5E05, 0xCBA7, 0x5E06, 0xB7AB, 0x5E07, 0x8E8B, 0x5E08, 0xCAA6, 0x5E09, 0x8E8C, 0x5E0A, 0x8E8D,
+ 0x5E0B, 0x8E8E, 0x5E0C, 0xCFA3, 0x5E0D, 0x8E8F, 0x5E0E, 0x8E90, 0x5E0F, 0xE0F8, 0x5E10, 0xD5CA, 0x5E11, 0xE0FB, 0x5E12, 0x8E91,
+ 0x5E13, 0x8E92, 0x5E14, 0xE0FA, 0x5E15, 0xC5C1, 0x5E16, 0xCCFB, 0x5E17, 0x8E93, 0x5E18, 0xC1B1, 0x5E19, 0xE0F9, 0x5E1A, 0xD6E3,
+ 0x5E1B, 0xB2AF, 0x5E1C, 0xD6C4, 0x5E1D, 0xB5DB, 0x5E1E, 0x8E94, 0x5E1F, 0x8E95, 0x5E20, 0x8E96, 0x5E21, 0x8E97, 0x5E22, 0x8E98,
+ 0x5E23, 0x8E99, 0x5E24, 0x8E9A, 0x5E25, 0x8E9B, 0x5E26, 0xB4F8, 0x5E27, 0xD6A1, 0x5E28, 0x8E9C, 0x5E29, 0x8E9D, 0x5E2A, 0x8E9E,
+ 0x5E2B, 0x8E9F, 0x5E2C, 0x8EA0, 0x5E2D, 0xCFAF, 0x5E2E, 0xB0EF, 0x5E2F, 0x8EA1, 0x5E30, 0x8EA2, 0x5E31, 0xE0FC, 0x5E32, 0x8EA3,
+ 0x5E33, 0x8EA4, 0x5E34, 0x8EA5, 0x5E35, 0x8EA6, 0x5E36, 0x8EA7, 0x5E37, 0xE1A1, 0x5E38, 0xB3A3, 0x5E39, 0x8EA8, 0x5E3A, 0x8EA9,
+ 0x5E3B, 0xE0FD, 0x5E3C, 0xE0FE, 0x5E3D, 0xC3B1, 0x5E3E, 0x8EAA, 0x5E3F, 0x8EAB, 0x5E40, 0x8EAC, 0x5E41, 0x8EAD, 0x5E42, 0xC3DD,
+ 0x5E43, 0x8EAE, 0x5E44, 0xE1A2, 0x5E45, 0xB7F9, 0x5E46, 0x8EAF, 0x5E47, 0x8EB0, 0x5E48, 0x8EB1, 0x5E49, 0x8EB2, 0x5E4A, 0x8EB3,
+ 0x5E4B, 0x8EB4, 0x5E4C, 0xBBCF, 0x5E4D, 0x8EB5, 0x5E4E, 0x8EB6, 0x5E4F, 0x8EB7, 0x5E50, 0x8EB8, 0x5E51, 0x8EB9, 0x5E52, 0x8EBA,
+ 0x5E53, 0x8EBB, 0x5E54, 0xE1A3, 0x5E55, 0xC4BB, 0x5E56, 0x8EBC, 0x5E57, 0x8EBD, 0x5E58, 0x8EBE, 0x5E59, 0x8EBF, 0x5E5A, 0x8EC0,
+ 0x5E5B, 0xE1A4, 0x5E5C, 0x8EC1, 0x5E5D, 0x8EC2, 0x5E5E, 0xE1A5, 0x5E5F, 0x8EC3, 0x5E60, 0x8EC4, 0x5E61, 0xE1A6, 0x5E62, 0xB4B1,
+ 0x5E63, 0x8EC5, 0x5E64, 0x8EC6, 0x5E65, 0x8EC7, 0x5E66, 0x8EC8, 0x5E67, 0x8EC9, 0x5E68, 0x8ECA, 0x5E69, 0x8ECB, 0x5E6A, 0x8ECC,
+ 0x5E6B, 0x8ECD, 0x5E6C, 0x8ECE, 0x5E6D, 0x8ECF, 0x5E6E, 0x8ED0, 0x5E6F, 0x8ED1, 0x5E70, 0x8ED2, 0x5E71, 0x8ED3, 0x5E72, 0xB8C9,
+ 0x5E73, 0xC6BD, 0x5E74, 0xC4EA, 0x5E75, 0x8ED4, 0x5E76, 0xB2A2, 0x5E77, 0x8ED5, 0x5E78, 0xD0D2, 0x5E79, 0x8ED6, 0x5E7A, 0xE7DB,
+ 0x5E7B, 0xBBC3, 0x5E7C, 0xD3D7, 0x5E7D, 0xD3C4, 0x5E7E, 0x8ED7, 0x5E7F, 0xB9E3, 0x5E80, 0xE2CF, 0x5E81, 0x8ED8, 0x5E82, 0x8ED9,
+ 0x5E83, 0x8EDA, 0x5E84, 0xD7AF, 0x5E85, 0x8EDB, 0x5E86, 0xC7EC, 0x5E87, 0xB1D3, 0x5E88, 0x8EDC, 0x5E89, 0x8EDD, 0x5E8A, 0xB4B2,
+ 0x5E8B, 0xE2D1, 0x5E8C, 0x8EDE, 0x5E8D, 0x8EDF, 0x5E8E, 0x8EE0, 0x5E8F, 0xD0F2, 0x5E90, 0xC2AE, 0x5E91, 0xE2D0, 0x5E92, 0x8EE1,
+ 0x5E93, 0xBFE2, 0x5E94, 0xD3A6, 0x5E95, 0xB5D7, 0x5E96, 0xE2D2, 0x5E97, 0xB5EA, 0x5E98, 0x8EE2, 0x5E99, 0xC3ED, 0x5E9A, 0xB8FD,
+ 0x5E9B, 0x8EE3, 0x5E9C, 0xB8AE, 0x5E9D, 0x8EE4, 0x5E9E, 0xC5D3, 0x5E9F, 0xB7CF, 0x5EA0, 0xE2D4, 0x5EA1, 0x8EE5, 0x5EA2, 0x8EE6,
+ 0x5EA3, 0x8EE7, 0x5EA4, 0x8EE8, 0x5EA5, 0xE2D3, 0x5EA6, 0xB6C8, 0x5EA7, 0xD7F9, 0x5EA8, 0x8EE9, 0x5EA9, 0x8EEA, 0x5EAA, 0x8EEB,
+ 0x5EAB, 0x8EEC, 0x5EAC, 0x8EED, 0x5EAD, 0xCDA5, 0x5EAE, 0x8EEE, 0x5EAF, 0x8EEF, 0x5EB0, 0x8EF0, 0x5EB1, 0x8EF1, 0x5EB2, 0x8EF2,
+ 0x5EB3, 0xE2D8, 0x5EB4, 0x8EF3, 0x5EB5, 0xE2D6, 0x5EB6, 0xCAFC, 0x5EB7, 0xBFB5, 0x5EB8, 0xD3B9, 0x5EB9, 0xE2D5, 0x5EBA, 0x8EF4,
+ 0x5EBB, 0x8EF5, 0x5EBC, 0x8EF6, 0x5EBD, 0x8EF7, 0x5EBE, 0xE2D7, 0x5EBF, 0x8EF8, 0x5EC0, 0x8EF9, 0x5EC1, 0x8EFA, 0x5EC2, 0x8EFB,
+ 0x5EC3, 0x8EFC, 0x5EC4, 0x8EFD, 0x5EC5, 0x8EFE, 0x5EC6, 0x8F40, 0x5EC7, 0x8F41, 0x5EC8, 0x8F42, 0x5EC9, 0xC1AE, 0x5ECA, 0xC0C8,
+ 0x5ECB, 0x8F43, 0x5ECC, 0x8F44, 0x5ECD, 0x8F45, 0x5ECE, 0x8F46, 0x5ECF, 0x8F47, 0x5ED0, 0x8F48, 0x5ED1, 0xE2DB, 0x5ED2, 0xE2DA,
+ 0x5ED3, 0xC0AA, 0x5ED4, 0x8F49, 0x5ED5, 0x8F4A, 0x5ED6, 0xC1CE, 0x5ED7, 0x8F4B, 0x5ED8, 0x8F4C, 0x5ED9, 0x8F4D, 0x5EDA, 0x8F4E,
+ 0x5EDB, 0xE2DC, 0x5EDC, 0x8F4F, 0x5EDD, 0x8F50, 0x5EDE, 0x8F51, 0x5EDF, 0x8F52, 0x5EE0, 0x8F53, 0x5EE1, 0x8F54, 0x5EE2, 0x8F55,
+ 0x5EE3, 0x8F56, 0x5EE4, 0x8F57, 0x5EE5, 0x8F58, 0x5EE6, 0x8F59, 0x5EE7, 0x8F5A, 0x5EE8, 0xE2DD, 0x5EE9, 0x8F5B, 0x5EEA, 0xE2DE,
+ 0x5EEB, 0x8F5C, 0x5EEC, 0x8F5D, 0x5EED, 0x8F5E, 0x5EEE, 0x8F5F, 0x5EEF, 0x8F60, 0x5EF0, 0x8F61, 0x5EF1, 0x8F62, 0x5EF2, 0x8F63,
+ 0x5EF3, 0x8F64, 0x5EF4, 0xDBC8, 0x5EF5, 0x8F65, 0x5EF6, 0xD1D3, 0x5EF7, 0xCDA2, 0x5EF8, 0x8F66, 0x5EF9, 0x8F67, 0x5EFA, 0xBDA8,
+ 0x5EFB, 0x8F68, 0x5EFC, 0x8F69, 0x5EFD, 0x8F6A, 0x5EFE, 0xDEC3, 0x5EFF, 0xD8A5, 0x5F00, 0xBFAA, 0x5F01, 0xDBCD, 0x5F02, 0xD2EC,
+ 0x5F03, 0xC6FA, 0x5F04, 0xC5AA, 0x5F05, 0x8F6B, 0x5F06, 0x8F6C, 0x5F07, 0x8F6D, 0x5F08, 0xDEC4, 0x5F09, 0x8F6E, 0x5F0A, 0xB1D7,
+ 0x5F0B, 0xDFAE, 0x5F0C, 0x8F6F, 0x5F0D, 0x8F70, 0x5F0E, 0x8F71, 0x5F0F, 0xCABD, 0x5F10, 0x8F72, 0x5F11, 0xDFB1, 0x5F12, 0x8F73,
+ 0x5F13, 0xB9AD, 0x5F14, 0x8F74, 0x5F15, 0xD2FD, 0x5F16, 0x8F75, 0x5F17, 0xB8A5, 0x5F18, 0xBAEB, 0x5F19, 0x8F76, 0x5F1A, 0x8F77,
+ 0x5F1B, 0xB3DA, 0x5F1C, 0x8F78, 0x5F1D, 0x8F79, 0x5F1E, 0x8F7A, 0x5F1F, 0xB5DC, 0x5F20, 0xD5C5, 0x5F21, 0x8F7B, 0x5F22, 0x8F7C,
+ 0x5F23, 0x8F7D, 0x5F24, 0x8F7E, 0x5F25, 0xC3D6, 0x5F26, 0xCFD2, 0x5F27, 0xBBA1, 0x5F28, 0x8F80, 0x5F29, 0xE5F3, 0x5F2A, 0xE5F2,
+ 0x5F2B, 0x8F81, 0x5F2C, 0x8F82, 0x5F2D, 0xE5F4, 0x5F2E, 0x8F83, 0x5F2F, 0xCDE4, 0x5F30, 0x8F84, 0x5F31, 0xC8F5, 0x5F32, 0x8F85,
+ 0x5F33, 0x8F86, 0x5F34, 0x8F87, 0x5F35, 0x8F88, 0x5F36, 0x8F89, 0x5F37, 0x8F8A, 0x5F38, 0x8F8B, 0x5F39, 0xB5AF, 0x5F3A, 0xC7BF,
+ 0x5F3B, 0x8F8C, 0x5F3C, 0xE5F6, 0x5F3D, 0x8F8D, 0x5F3E, 0x8F8E, 0x5F3F, 0x8F8F, 0x5F40, 0xECB0, 0x5F41, 0x8F90, 0x5F42, 0x8F91,
+ 0x5F43, 0x8F92, 0x5F44, 0x8F93, 0x5F45, 0x8F94, 0x5F46, 0x8F95, 0x5F47, 0x8F96, 0x5F48, 0x8F97, 0x5F49, 0x8F98, 0x5F4A, 0x8F99,
+ 0x5F4B, 0x8F9A, 0x5F4C, 0x8F9B, 0x5F4D, 0x8F9C, 0x5F4E, 0x8F9D, 0x5F4F, 0x8F9E, 0x5F50, 0xE5E6, 0x5F51, 0x8F9F, 0x5F52, 0xB9E9,
+ 0x5F53, 0xB5B1, 0x5F54, 0x8FA0, 0x5F55, 0xC2BC, 0x5F56, 0xE5E8, 0x5F57, 0xE5E7, 0x5F58, 0xE5E9, 0x5F59, 0x8FA1, 0x5F5A, 0x8FA2,
+ 0x5F5B, 0x8FA3, 0x5F5C, 0x8FA4, 0x5F5D, 0xD2CD, 0x5F5E, 0x8FA5, 0x5F5F, 0x8FA6, 0x5F60, 0x8FA7, 0x5F61, 0xE1EA, 0x5F62, 0xD0CE,
+ 0x5F63, 0x8FA8, 0x5F64, 0xCDAE, 0x5F65, 0x8FA9, 0x5F66, 0xD1E5, 0x5F67, 0x8FAA, 0x5F68, 0x8FAB, 0x5F69, 0xB2CA, 0x5F6A, 0xB1EB,
+ 0x5F6B, 0x8FAC, 0x5F6C, 0xB1F2, 0x5F6D, 0xC5ED, 0x5F6E, 0x8FAD, 0x5F6F, 0x8FAE, 0x5F70, 0xD5C3, 0x5F71, 0xD3B0, 0x5F72, 0x8FAF,
+ 0x5F73, 0xE1DC, 0x5F74, 0x8FB0, 0x5F75, 0x8FB1, 0x5F76, 0x8FB2, 0x5F77, 0xE1DD, 0x5F78, 0x8FB3, 0x5F79, 0xD2DB, 0x5F7A, 0x8FB4,
+ 0x5F7B, 0xB3B9, 0x5F7C, 0xB1CB, 0x5F7D, 0x8FB5, 0x5F7E, 0x8FB6, 0x5F7F, 0x8FB7, 0x5F80, 0xCDF9, 0x5F81, 0xD5F7, 0x5F82, 0xE1DE,
+ 0x5F83, 0x8FB8, 0x5F84, 0xBEB6, 0x5F85, 0xB4FD, 0x5F86, 0x8FB9, 0x5F87, 0xE1DF, 0x5F88, 0xBADC, 0x5F89, 0xE1E0, 0x5F8A, 0xBBB2,
+ 0x5F8B, 0xC2C9, 0x5F8C, 0xE1E1, 0x5F8D, 0x8FBA, 0x5F8E, 0x8FBB, 0x5F8F, 0x8FBC, 0x5F90, 0xD0EC, 0x5F91, 0x8FBD, 0x5F92, 0xCDBD,
+ 0x5F93, 0x8FBE, 0x5F94, 0x8FBF, 0x5F95, 0xE1E2, 0x5F96, 0x8FC0, 0x5F97, 0xB5C3, 0x5F98, 0xC5C7, 0x5F99, 0xE1E3, 0x5F9A, 0x8FC1,
+ 0x5F9B, 0x8FC2, 0x5F9C, 0xE1E4, 0x5F9D, 0x8FC3, 0x5F9E, 0x8FC4, 0x5F9F, 0x8FC5, 0x5FA0, 0x8FC6, 0x5FA1, 0xD3F9, 0x5FA2, 0x8FC7,
+ 0x5FA3, 0x8FC8, 0x5FA4, 0x8FC9, 0x5FA5, 0x8FCA, 0x5FA6, 0x8FCB, 0x5FA7, 0x8FCC, 0x5FA8, 0xE1E5, 0x5FA9, 0x8FCD, 0x5FAA, 0xD1AD,
+ 0x5FAB, 0x8FCE, 0x5FAC, 0x8FCF, 0x5FAD, 0xE1E6, 0x5FAE, 0xCEA2, 0x5FAF, 0x8FD0, 0x5FB0, 0x8FD1, 0x5FB1, 0x8FD2, 0x5FB2, 0x8FD3,
+ 0x5FB3, 0x8FD4, 0x5FB4, 0x8FD5, 0x5FB5, 0xE1E7, 0x5FB6, 0x8FD6, 0x5FB7, 0xB5C2, 0x5FB8, 0x8FD7, 0x5FB9, 0x8FD8, 0x5FBA, 0x8FD9,
+ 0x5FBB, 0x8FDA, 0x5FBC, 0xE1E8, 0x5FBD, 0xBBD5, 0x5FBE, 0x8FDB, 0x5FBF, 0x8FDC, 0x5FC0, 0x8FDD, 0x5FC1, 0x8FDE, 0x5FC2, 0x8FDF,
+ 0x5FC3, 0xD0C4, 0x5FC4, 0xE2E0, 0x5FC5, 0xB1D8, 0x5FC6, 0xD2E4, 0x5FC7, 0x8FE0, 0x5FC8, 0x8FE1, 0x5FC9, 0xE2E1, 0x5FCA, 0x8FE2,
+ 0x5FCB, 0x8FE3, 0x5FCC, 0xBCC9, 0x5FCD, 0xC8CC, 0x5FCE, 0x8FE4, 0x5FCF, 0xE2E3, 0x5FD0, 0xECFE, 0x5FD1, 0xECFD, 0x5FD2, 0xDFAF,
+ 0x5FD3, 0x8FE5, 0x5FD4, 0x8FE6, 0x5FD5, 0x8FE7, 0x5FD6, 0xE2E2, 0x5FD7, 0xD6BE, 0x5FD8, 0xCDFC, 0x5FD9, 0xC3A6, 0x5FDA, 0x8FE8,
+ 0x5FDB, 0x8FE9, 0x5FDC, 0x8FEA, 0x5FDD, 0xE3C3, 0x5FDE, 0x8FEB, 0x5FDF, 0x8FEC, 0x5FE0, 0xD6D2, 0x5FE1, 0xE2E7, 0x5FE2, 0x8FED,
+ 0x5FE3, 0x8FEE, 0x5FE4, 0xE2E8, 0x5FE5, 0x8FEF, 0x5FE6, 0x8FF0, 0x5FE7, 0xD3C7, 0x5FE8, 0x8FF1, 0x5FE9, 0x8FF2, 0x5FEA, 0xE2EC,
+ 0x5FEB, 0xBFEC, 0x5FEC, 0x8FF3, 0x5FED, 0xE2ED, 0x5FEE, 0xE2E5, 0x5FEF, 0x8FF4, 0x5FF0, 0x8FF5, 0x5FF1, 0xB3C0, 0x5FF2, 0x8FF6,
+ 0x5FF3, 0x8FF7, 0x5FF4, 0x8FF8, 0x5FF5, 0xC4EE, 0x5FF6, 0x8FF9, 0x5FF7, 0x8FFA, 0x5FF8, 0xE2EE, 0x5FF9, 0x8FFB, 0x5FFA, 0x8FFC,
+ 0x5FFB, 0xD0C3, 0x5FFC, 0x8FFD, 0x5FFD, 0xBAF6, 0x5FFE, 0xE2E9, 0x5FFF, 0xB7DE, 0x6000, 0xBBB3, 0x6001, 0xCCAC, 0x6002, 0xCBCB,
+ 0x6003, 0xE2E4, 0x6004, 0xE2E6, 0x6005, 0xE2EA, 0x6006, 0xE2EB, 0x6007, 0x8FFE, 0x6008, 0x9040, 0x6009, 0x9041, 0x600A, 0xE2F7,
+ 0x600B, 0x9042, 0x600C, 0x9043, 0x600D, 0xE2F4, 0x600E, 0xD4F5, 0x600F, 0xE2F3, 0x6010, 0x9044, 0x6011, 0x9045, 0x6012, 0xC5AD,
+ 0x6013, 0x9046, 0x6014, 0xD5FA, 0x6015, 0xC5C2, 0x6016, 0xB2C0, 0x6017, 0x9047, 0x6018, 0x9048, 0x6019, 0xE2EF, 0x601A, 0x9049,
+ 0x601B, 0xE2F2, 0x601C, 0xC1AF, 0x601D, 0xCBBC, 0x601E, 0x904A, 0x601F, 0x904B, 0x6020, 0xB5A1, 0x6021, 0xE2F9, 0x6022, 0x904C,
+ 0x6023, 0x904D, 0x6024, 0x904E, 0x6025, 0xBCB1, 0x6026, 0xE2F1, 0x6027, 0xD0D4, 0x6028, 0xD4B9, 0x6029, 0xE2F5, 0x602A, 0xB9D6,
+ 0x602B, 0xE2F6, 0x602C, 0x904F, 0x602D, 0x9050, 0x602E, 0x9051, 0x602F, 0xC7D3, 0x6030, 0x9052, 0x6031, 0x9053, 0x6032, 0x9054,
+ 0x6033, 0x9055, 0x6034, 0x9056, 0x6035, 0xE2F0, 0x6036, 0x9057, 0x6037, 0x9058, 0x6038, 0x9059, 0x6039, 0x905A, 0x603A, 0x905B,
+ 0x603B, 0xD7DC, 0x603C, 0xEDA1, 0x603D, 0x905C, 0x603E, 0x905D, 0x603F, 0xE2F8, 0x6040, 0x905E, 0x6041, 0xEDA5, 0x6042, 0xE2FE,
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+ 0x62CB, 0x9281, 0x62CC, 0xB0E8, 0x62CD, 0xC5C4, 0x62CE, 0xC1E0, 0x62CF, 0x9282, 0x62D0, 0xB9D5, 0x62D1, 0x9283, 0x62D2, 0xBEDC,
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+ 0x75FB, 0xAF78, 0x75FC, 0xF0F3, 0x75FD, 0xAF79, 0x75FE, 0xAF7A, 0x75FF, 0xF0F4, 0x7600, 0xF0F6, 0x7601, 0xB4E1, 0x7602, 0xAF7B,
+ 0x7603, 0xF0F1, 0x7604, 0xAF7C, 0x7605, 0xF0F7, 0x7606, 0xAF7D, 0x7607, 0xAF7E, 0x7608, 0xAF80, 0x7609, 0xAF81, 0x760A, 0xF0FA,
+ 0x760B, 0xAF82, 0x760C, 0xF0F8, 0x760D, 0xAF83, 0x760E, 0xAF84, 0x760F, 0xAF85, 0x7610, 0xF0F5, 0x7611, 0xAF86, 0x7612, 0xAF87,
+ 0x7613, 0xAF88, 0x7614, 0xAF89, 0x7615, 0xF0FD, 0x7616, 0xAF8A, 0x7617, 0xF0F9, 0x7618, 0xF0FC, 0x7619, 0xF0FE, 0x761A, 0xAF8B,
+ 0x761B, 0xF1A1, 0x761C, 0xAF8C, 0x761D, 0xAF8D, 0x761E, 0xAF8E, 0x761F, 0xCEC1, 0x7620, 0xF1A4, 0x7621, 0xAF8F, 0x7622, 0xF1A3,
+ 0x7623, 0xAF90, 0x7624, 0xC1F6, 0x7625, 0xF0FB, 0x7626, 0xCADD, 0x7627, 0xAF91, 0x7628, 0xAF92, 0x7629, 0xB4F1, 0x762A, 0xB1F1,
+ 0x762B, 0xCCB1, 0x762C, 0xAF93, 0x762D, 0xF1A6, 0x762E, 0xAF94, 0x762F, 0xAF95, 0x7630, 0xF1A7, 0x7631, 0xAF96, 0x7632, 0xAF97,
+ 0x7633, 0xF1AC, 0x7634, 0xD5CE, 0x7635, 0xF1A9, 0x7636, 0xAF98, 0x7637, 0xAF99, 0x7638, 0xC8B3, 0x7639, 0xAF9A, 0x763A, 0xAF9B,
+ 0x763B, 0xAF9C, 0x763C, 0xF1A2, 0x763D, 0xAF9D, 0x763E, 0xF1AB, 0x763F, 0xF1A8, 0x7640, 0xF1A5, 0x7641, 0xAF9E, 0x7642, 0xAF9F,
+ 0x7643, 0xF1AA, 0x7644, 0xAFA0, 0x7645, 0xB040, 0x7646, 0xB041, 0x7647, 0xB042, 0x7648, 0xB043, 0x7649, 0xB044, 0x764A, 0xB045,
+ 0x764B, 0xB046, 0x764C, 0xB0A9, 0x764D, 0xF1AD, 0x764E, 0xB047, 0x764F, 0xB048, 0x7650, 0xB049, 0x7651, 0xB04A, 0x7652, 0xB04B,
+ 0x7653, 0xB04C, 0x7654, 0xF1AF, 0x7655, 0xB04D, 0x7656, 0xF1B1, 0x7657, 0xB04E, 0x7658, 0xB04F, 0x7659, 0xB050, 0x765A, 0xB051,
+ 0x765B, 0xB052, 0x765C, 0xF1B0, 0x765D, 0xB053, 0x765E, 0xF1AE, 0x765F, 0xB054, 0x7660, 0xB055, 0x7661, 0xB056, 0x7662, 0xB057,
+ 0x7663, 0xD1A2, 0x7664, 0xB058, 0x7665, 0xB059, 0x7666, 0xB05A, 0x7667, 0xB05B, 0x7668, 0xB05C, 0x7669, 0xB05D, 0x766A, 0xB05E,
+ 0x766B, 0xF1B2, 0x766C, 0xB05F, 0x766D, 0xB060, 0x766E, 0xB061, 0x766F, 0xF1B3, 0x7670, 0xB062, 0x7671, 0xB063, 0x7672, 0xB064,
+ 0x7673, 0xB065, 0x7674, 0xB066, 0x7675, 0xB067, 0x7676, 0xB068, 0x7677, 0xB069, 0x7678, 0xB9EF, 0x7679, 0xB06A, 0x767A, 0xB06B,
+ 0x767B, 0xB5C7, 0x767C, 0xB06C, 0x767D, 0xB0D7, 0x767E, 0xB0D9, 0x767F, 0xB06D, 0x7680, 0xB06E, 0x7681, 0xB06F, 0x7682, 0xD4ED,
+ 0x7683, 0xB070, 0x7684, 0xB5C4, 0x7685, 0xB071, 0x7686, 0xBDD4, 0x7687, 0xBBCA, 0x7688, 0xF0A7, 0x7689, 0xB072, 0x768A, 0xB073,
+ 0x768B, 0xB8DE, 0x768C, 0xB074, 0x768D, 0xB075, 0x768E, 0xF0A8, 0x768F, 0xB076, 0x7690, 0xB077, 0x7691, 0xB0A8, 0x7692, 0xB078,
+ 0x7693, 0xF0A9, 0x7694, 0xB079, 0x7695, 0xB07A, 0x7696, 0xCDEE, 0x7697, 0xB07B, 0x7698, 0xB07C, 0x7699, 0xF0AA, 0x769A, 0xB07D,
+ 0x769B, 0xB07E, 0x769C, 0xB080, 0x769D, 0xB081, 0x769E, 0xB082, 0x769F, 0xB083, 0x76A0, 0xB084, 0x76A1, 0xB085, 0x76A2, 0xB086,
+ 0x76A3, 0xB087, 0x76A4, 0xF0AB, 0x76A5, 0xB088, 0x76A6, 0xB089, 0x76A7, 0xB08A, 0x76A8, 0xB08B, 0x76A9, 0xB08C, 0x76AA, 0xB08D,
+ 0x76AB, 0xB08E, 0x76AC, 0xB08F, 0x76AD, 0xB090, 0x76AE, 0xC6A4, 0x76AF, 0xB091, 0x76B0, 0xB092, 0x76B1, 0xD6E5, 0x76B2, 0xF1E4,
+ 0x76B3, 0xB093, 0x76B4, 0xF1E5, 0x76B5, 0xB094, 0x76B6, 0xB095, 0x76B7, 0xB096, 0x76B8, 0xB097, 0x76B9, 0xB098, 0x76BA, 0xB099,
+ 0x76BB, 0xB09A, 0x76BC, 0xB09B, 0x76BD, 0xB09C, 0x76BE, 0xB09D, 0x76BF, 0xC3F3, 0x76C0, 0xB09E, 0x76C1, 0xB09F, 0x76C2, 0xD3DB,
+ 0x76C3, 0xB0A0, 0x76C4, 0xB140, 0x76C5, 0xD6D1, 0x76C6, 0xC5E8, 0x76C7, 0xB141, 0x76C8, 0xD3AF, 0x76C9, 0xB142, 0x76CA, 0xD2E6,
+ 0x76CB, 0xB143, 0x76CC, 0xB144, 0x76CD, 0xEEC1, 0x76CE, 0xB0BB, 0x76CF, 0xD5B5, 0x76D0, 0xD1CE, 0x76D1, 0xBCE0, 0x76D2, 0xBAD0,
+ 0x76D3, 0xB145, 0x76D4, 0xBFF8, 0x76D5, 0xB146, 0x76D6, 0xB8C7, 0x76D7, 0xB5C1, 0x76D8, 0xC5CC, 0x76D9, 0xB147, 0x76DA, 0xB148,
+ 0x76DB, 0xCAA2, 0x76DC, 0xB149, 0x76DD, 0xB14A, 0x76DE, 0xB14B, 0x76DF, 0xC3CB, 0x76E0, 0xB14C, 0x76E1, 0xB14D, 0x76E2, 0xB14E,
+ 0x76E3, 0xB14F, 0x76E4, 0xB150, 0x76E5, 0xEEC2, 0x76E6, 0xB151, 0x76E7, 0xB152, 0x76E8, 0xB153, 0x76E9, 0xB154, 0x76EA, 0xB155,
+ 0x76EB, 0xB156, 0x76EC, 0xB157, 0x76ED, 0xB158, 0x76EE, 0xC4BF, 0x76EF, 0xB6A2, 0x76F0, 0xB159, 0x76F1, 0xEDEC, 0x76F2, 0xC3A4,
+ 0x76F3, 0xB15A, 0x76F4, 0xD6B1, 0x76F5, 0xB15B, 0x76F6, 0xB15C, 0x76F7, 0xB15D, 0x76F8, 0xCFE0, 0x76F9, 0xEDEF, 0x76FA, 0xB15E,
+ 0x76FB, 0xB15F, 0x76FC, 0xC5CE, 0x76FD, 0xB160, 0x76FE, 0xB6DC, 0x76FF, 0xB161, 0x7700, 0xB162, 0x7701, 0xCAA1, 0x7702, 0xB163,
+ 0x7703, 0xB164, 0x7704, 0xEDED, 0x7705, 0xB165, 0x7706, 0xB166, 0x7707, 0xEDF0, 0x7708, 0xEDF1, 0x7709, 0xC3BC, 0x770A, 0xB167,
+ 0x770B, 0xBFB4, 0x770C, 0xB168, 0x770D, 0xEDEE, 0x770E, 0xB169, 0x770F, 0xB16A, 0x7710, 0xB16B, 0x7711, 0xB16C, 0x7712, 0xB16D,
+ 0x7713, 0xB16E, 0x7714, 0xB16F, 0x7715, 0xB170, 0x7716, 0xB171, 0x7717, 0xB172, 0x7718, 0xB173, 0x7719, 0xEDF4, 0x771A, 0xEDF2,
+ 0x771B, 0xB174, 0x771C, 0xB175, 0x771D, 0xB176, 0x771E, 0xB177, 0x771F, 0xD5E6, 0x7720, 0xC3DF, 0x7721, 0xB178, 0x7722, 0xEDF3,
+ 0x7723, 0xB179, 0x7724, 0xB17A, 0x7725, 0xB17B, 0x7726, 0xEDF6, 0x7727, 0xB17C, 0x7728, 0xD5A3, 0x7729, 0xD1A3, 0x772A, 0xB17D,
+ 0x772B, 0xB17E, 0x772C, 0xB180, 0x772D, 0xEDF5, 0x772E, 0xB181, 0x772F, 0xC3D0, 0x7730, 0xB182, 0x7731, 0xB183, 0x7732, 0xB184,
+ 0x7733, 0xB185, 0x7734, 0xB186, 0x7735, 0xEDF7, 0x7736, 0xBFF4, 0x7737, 0xBEEC, 0x7738, 0xEDF8, 0x7739, 0xB187, 0x773A, 0xCCF7,
+ 0x773B, 0xB188, 0x773C, 0xD1DB, 0x773D, 0xB189, 0x773E, 0xB18A, 0x773F, 0xB18B, 0x7740, 0xD7C5, 0x7741, 0xD5F6, 0x7742, 0xB18C,
+ 0x7743, 0xEDFC, 0x7744, 0xB18D, 0x7745, 0xB18E, 0x7746, 0xB18F, 0x7747, 0xEDFB, 0x7748, 0xB190, 0x7749, 0xB191, 0x774A, 0xB192,
+ 0x774B, 0xB193, 0x774C, 0xB194, 0x774D, 0xB195, 0x774E, 0xB196, 0x774F, 0xB197, 0x7750, 0xEDF9, 0x7751, 0xEDFA, 0x7752, 0xB198,
+ 0x7753, 0xB199, 0x7754, 0xB19A, 0x7755, 0xB19B, 0x7756, 0xB19C, 0x7757, 0xB19D, 0x7758, 0xB19E, 0x7759, 0xB19F, 0x775A, 0xEDFD,
+ 0x775B, 0xBEA6, 0x775C, 0xB1A0, 0x775D, 0xB240, 0x775E, 0xB241, 0x775F, 0xB242, 0x7760, 0xB243, 0x7761, 0xCBAF, 0x7762, 0xEEA1,
+ 0x7763, 0xB6BD, 0x7764, 0xB244, 0x7765, 0xEEA2, 0x7766, 0xC4C0, 0x7767, 0xB245, 0x7768, 0xEDFE, 0x7769, 0xB246, 0x776A, 0xB247,
+ 0x776B, 0xBDDE, 0x776C, 0xB2C7, 0x776D, 0xB248, 0x776E, 0xB249, 0x776F, 0xB24A, 0x7770, 0xB24B, 0x7771, 0xB24C, 0x7772, 0xB24D,
+ 0x7773, 0xB24E, 0x7774, 0xB24F, 0x7775, 0xB250, 0x7776, 0xB251, 0x7777, 0xB252, 0x7778, 0xB253, 0x7779, 0xB6C3, 0x777A, 0xB254,
+ 0x777B, 0xB255, 0x777C, 0xB256, 0x777D, 0xEEA5, 0x777E, 0xD8BA, 0x777F, 0xEEA3, 0x7780, 0xEEA6, 0x7781, 0xB257, 0x7782, 0xB258,
+ 0x7783, 0xB259, 0x7784, 0xC3E9, 0x7785, 0xB3F2, 0x7786, 0xB25A, 0x7787, 0xB25B, 0x7788, 0xB25C, 0x7789, 0xB25D, 0x778A, 0xB25E,
+ 0x778B, 0xB25F, 0x778C, 0xEEA7, 0x778D, 0xEEA4, 0x778E, 0xCFB9, 0x778F, 0xB260, 0x7790, 0xB261, 0x7791, 0xEEA8, 0x7792, 0xC2F7,
+ 0x7793, 0xB262, 0x7794, 0xB263, 0x7795, 0xB264, 0x7796, 0xB265, 0x7797, 0xB266, 0x7798, 0xB267, 0x7799, 0xB268, 0x779A, 0xB269,
+ 0x779B, 0xB26A, 0x779C, 0xB26B, 0x779D, 0xB26C, 0x779E, 0xB26D, 0x779F, 0xEEA9, 0x77A0, 0xEEAA, 0x77A1, 0xB26E, 0x77A2, 0xDEAB,
+ 0x77A3, 0xB26F, 0x77A4, 0xB270, 0x77A5, 0xC6B3, 0x77A6, 0xB271, 0x77A7, 0xC7C6, 0x77A8, 0xB272, 0x77A9, 0xD6F5, 0x77AA, 0xB5C9,
+ 0x77AB, 0xB273, 0x77AC, 0xCBB2, 0x77AD, 0xB274, 0x77AE, 0xB275, 0x77AF, 0xB276, 0x77B0, 0xEEAB, 0x77B1, 0xB277, 0x77B2, 0xB278,
+ 0x77B3, 0xCDAB, 0x77B4, 0xB279, 0x77B5, 0xEEAC, 0x77B6, 0xB27A, 0x77B7, 0xB27B, 0x77B8, 0xB27C, 0x77B9, 0xB27D, 0x77BA, 0xB27E,
+ 0x77BB, 0xD5B0, 0x77BC, 0xB280, 0x77BD, 0xEEAD, 0x77BE, 0xB281, 0x77BF, 0xF6C4, 0x77C0, 0xB282, 0x77C1, 0xB283, 0x77C2, 0xB284,
+ 0x77C3, 0xB285, 0x77C4, 0xB286, 0x77C5, 0xB287, 0x77C6, 0xB288, 0x77C7, 0xB289, 0x77C8, 0xB28A, 0x77C9, 0xB28B, 0x77CA, 0xB28C,
+ 0x77CB, 0xB28D, 0x77CC, 0xB28E, 0x77CD, 0xDBC7, 0x77CE, 0xB28F, 0x77CF, 0xB290, 0x77D0, 0xB291, 0x77D1, 0xB292, 0x77D2, 0xB293,
+ 0x77D3, 0xB294, 0x77D4, 0xB295, 0x77D5, 0xB296, 0x77D6, 0xB297, 0x77D7, 0xB4A3, 0x77D8, 0xB298, 0x77D9, 0xB299, 0x77DA, 0xB29A,
+ 0x77DB, 0xC3AC, 0x77DC, 0xF1E6, 0x77DD, 0xB29B, 0x77DE, 0xB29C, 0x77DF, 0xB29D, 0x77E0, 0xB29E, 0x77E1, 0xB29F, 0x77E2, 0xCAB8,
+ 0x77E3, 0xD2D3, 0x77E4, 0xB2A0, 0x77E5, 0xD6AA, 0x77E6, 0xB340, 0x77E7, 0xEFF2, 0x77E8, 0xB341, 0x77E9, 0xBED8, 0x77EA, 0xB342,
+ 0x77EB, 0xBDC3, 0x77EC, 0xEFF3, 0x77ED, 0xB6CC, 0x77EE, 0xB0AB, 0x77EF, 0xB343, 0x77F0, 0xB344, 0x77F1, 0xB345, 0x77F2, 0xB346,
+ 0x77F3, 0xCAAF, 0x77F4, 0xB347, 0x77F5, 0xB348, 0x77F6, 0xEDB6, 0x77F7, 0xB349, 0x77F8, 0xEDB7, 0x77F9, 0xB34A, 0x77FA, 0xB34B,
+ 0x77FB, 0xB34C, 0x77FC, 0xB34D, 0x77FD, 0xCEF9, 0x77FE, 0xB7AF, 0x77FF, 0xBFF3, 0x7800, 0xEDB8, 0x7801, 0xC2EB, 0x7802, 0xC9B0,
+ 0x7803, 0xB34E, 0x7804, 0xB34F, 0x7805, 0xB350, 0x7806, 0xB351, 0x7807, 0xB352, 0x7808, 0xB353, 0x7809, 0xEDB9, 0x780A, 0xB354,
+ 0x780B, 0xB355, 0x780C, 0xC6F6, 0x780D, 0xBFB3, 0x780E, 0xB356, 0x780F, 0xB357, 0x7810, 0xB358, 0x7811, 0xEDBC, 0x7812, 0xC5F8,
+ 0x7813, 0xB359, 0x7814, 0xD1D0, 0x7815, 0xB35A, 0x7816, 0xD7A9, 0x7817, 0xEDBA, 0x7818, 0xEDBB, 0x7819, 0xB35B, 0x781A, 0xD1E2,
+ 0x781B, 0xB35C, 0x781C, 0xEDBF, 0x781D, 0xEDC0, 0x781E, 0xB35D, 0x781F, 0xEDC4, 0x7820, 0xB35E, 0x7821, 0xB35F, 0x7822, 0xB360,
+ 0x7823, 0xEDC8, 0x7824, 0xB361, 0x7825, 0xEDC6, 0x7826, 0xEDCE, 0x7827, 0xD5E8, 0x7828, 0xB362, 0x7829, 0xEDC9, 0x782A, 0xB363,
+ 0x782B, 0xB364, 0x782C, 0xEDC7, 0x782D, 0xEDBE, 0x782E, 0xB365, 0x782F, 0xB366, 0x7830, 0xC5E9, 0x7831, 0xB367, 0x7832, 0xB368,
+ 0x7833, 0xB369, 0x7834, 0xC6C6, 0x7835, 0xB36A, 0x7836, 0xB36B, 0x7837, 0xC9E9, 0x7838, 0xD4D2, 0x7839, 0xEDC1, 0x783A, 0xEDC2,
+ 0x783B, 0xEDC3, 0x783C, 0xEDC5, 0x783D, 0xB36C, 0x783E, 0xC0F9, 0x783F, 0xB36D, 0x7840, 0xB4A1, 0x7841, 0xB36E, 0x7842, 0xB36F,
+ 0x7843, 0xB370, 0x7844, 0xB371, 0x7845, 0xB9E8, 0x7846, 0xB372, 0x7847, 0xEDD0, 0x7848, 0xB373, 0x7849, 0xB374, 0x784A, 0xB375,
+ 0x784B, 0xB376, 0x784C, 0xEDD1, 0x784D, 0xB377, 0x784E, 0xEDCA, 0x784F, 0xB378, 0x7850, 0xEDCF, 0x7851, 0xB379, 0x7852, 0xCEF8,
+ 0x7853, 0xB37A, 0x7854, 0xB37B, 0x7855, 0xCBB6, 0x7856, 0xEDCC, 0x7857, 0xEDCD, 0x7858, 0xB37C, 0x7859, 0xB37D, 0x785A, 0xB37E,
+ 0x785B, 0xB380, 0x785C, 0xB381, 0x785D, 0xCFF5, 0x785E, 0xB382, 0x785F, 0xB383, 0x7860, 0xB384, 0x7861, 0xB385, 0x7862, 0xB386,
+ 0x7863, 0xB387, 0x7864, 0xB388, 0x7865, 0xB389, 0x7866, 0xB38A, 0x7867, 0xB38B, 0x7868, 0xB38C, 0x7869, 0xB38D, 0x786A, 0xEDD2,
+ 0x786B, 0xC1F2, 0x786C, 0xD3B2, 0x786D, 0xEDCB, 0x786E, 0xC8B7, 0x786F, 0xB38E, 0x7870, 0xB38F, 0x7871, 0xB390, 0x7872, 0xB391,
+ 0x7873, 0xB392, 0x7874, 0xB393, 0x7875, 0xB394, 0x7876, 0xB395, 0x7877, 0xBCEF, 0x7878, 0xB396, 0x7879, 0xB397, 0x787A, 0xB398,
+ 0x787B, 0xB399, 0x787C, 0xC5F0, 0x787D, 0xB39A, 0x787E, 0xB39B, 0x787F, 0xB39C, 0x7880, 0xB39D, 0x7881, 0xB39E, 0x7882, 0xB39F,
+ 0x7883, 0xB3A0, 0x7884, 0xB440, 0x7885, 0xB441, 0x7886, 0xB442, 0x7887, 0xEDD6, 0x7888, 0xB443, 0x7889, 0xB5EF, 0x788A, 0xB444,
+ 0x788B, 0xB445, 0x788C, 0xC2B5, 0x788D, 0xB0AD, 0x788E, 0xCBE9, 0x788F, 0xB446, 0x7890, 0xB447, 0x7891, 0xB1AE, 0x7892, 0xB448,
+ 0x7893, 0xEDD4, 0x7894, 0xB449, 0x7895, 0xB44A, 0x7896, 0xB44B, 0x7897, 0xCDEB, 0x7898, 0xB5E2, 0x7899, 0xB44C, 0x789A, 0xEDD5,
+ 0x789B, 0xEDD3, 0x789C, 0xEDD7, 0x789D, 0xB44D, 0x789E, 0xB44E, 0x789F, 0xB5FA, 0x78A0, 0xB44F, 0x78A1, 0xEDD8, 0x78A2, 0xB450,
+ 0x78A3, 0xEDD9, 0x78A4, 0xB451, 0x78A5, 0xEDDC, 0x78A6, 0xB452, 0x78A7, 0xB1CC, 0x78A8, 0xB453, 0x78A9, 0xB454, 0x78AA, 0xB455,
+ 0x78AB, 0xB456, 0x78AC, 0xB457, 0x78AD, 0xB458, 0x78AE, 0xB459, 0x78AF, 0xB45A, 0x78B0, 0xC5F6, 0x78B1, 0xBCEE, 0x78B2, 0xEDDA,
+ 0x78B3, 0xCCBC, 0x78B4, 0xB2EA, 0x78B5, 0xB45B, 0x78B6, 0xB45C, 0x78B7, 0xB45D, 0x78B8, 0xB45E, 0x78B9, 0xEDDB, 0x78BA, 0xB45F,
+ 0x78BB, 0xB460, 0x78BC, 0xB461, 0x78BD, 0xB462, 0x78BE, 0xC4EB, 0x78BF, 0xB463, 0x78C0, 0xB464, 0x78C1, 0xB4C5, 0x78C2, 0xB465,
+ 0x78C3, 0xB466, 0x78C4, 0xB467, 0x78C5, 0xB0F5, 0x78C6, 0xB468, 0x78C7, 0xB469, 0x78C8, 0xB46A, 0x78C9, 0xEDDF, 0x78CA, 0xC0DA,
+ 0x78CB, 0xB4E8, 0x78CC, 0xB46B, 0x78CD, 0xB46C, 0x78CE, 0xB46D, 0x78CF, 0xB46E, 0x78D0, 0xC5CD, 0x78D1, 0xB46F, 0x78D2, 0xB470,
+ 0x78D3, 0xB471, 0x78D4, 0xEDDD, 0x78D5, 0xBFC4, 0x78D6, 0xB472, 0x78D7, 0xB473, 0x78D8, 0xB474, 0x78D9, 0xEDDE, 0x78DA, 0xB475,
+ 0x78DB, 0xB476, 0x78DC, 0xB477, 0x78DD, 0xB478, 0x78DE, 0xB479, 0x78DF, 0xB47A, 0x78E0, 0xB47B, 0x78E1, 0xB47C, 0x78E2, 0xB47D,
+ 0x78E3, 0xB47E, 0x78E4, 0xB480, 0x78E5, 0xB481, 0x78E6, 0xB482, 0x78E7, 0xB483, 0x78E8, 0xC4A5, 0x78E9, 0xB484, 0x78EA, 0xB485,
+ 0x78EB, 0xB486, 0x78EC, 0xEDE0, 0x78ED, 0xB487, 0x78EE, 0xB488, 0x78EF, 0xB489, 0x78F0, 0xB48A, 0x78F1, 0xB48B, 0x78F2, 0xEDE1,
+ 0x78F3, 0xB48C, 0x78F4, 0xEDE3, 0x78F5, 0xB48D, 0x78F6, 0xB48E, 0x78F7, 0xC1D7, 0x78F8, 0xB48F, 0x78F9, 0xB490, 0x78FA, 0xBBC7,
+ 0x78FB, 0xB491, 0x78FC, 0xB492, 0x78FD, 0xB493, 0x78FE, 0xB494, 0x78FF, 0xB495, 0x7900, 0xB496, 0x7901, 0xBDB8, 0x7902, 0xB497,
+ 0x7903, 0xB498, 0x7904, 0xB499, 0x7905, 0xEDE2, 0x7906, 0xB49A, 0x7907, 0xB49B, 0x7908, 0xB49C, 0x7909, 0xB49D, 0x790A, 0xB49E,
+ 0x790B, 0xB49F, 0x790C, 0xB4A0, 0x790D, 0xB540, 0x790E, 0xB541, 0x790F, 0xB542, 0x7910, 0xB543, 0x7911, 0xB544, 0x7912, 0xB545,
+ 0x7913, 0xEDE4, 0x7914, 0xB546, 0x7915, 0xB547, 0x7916, 0xB548, 0x7917, 0xB549, 0x7918, 0xB54A, 0x7919, 0xB54B, 0x791A, 0xB54C,
+ 0x791B, 0xB54D, 0x791C, 0xB54E, 0x791D, 0xB54F, 0x791E, 0xEDE6, 0x791F, 0xB550, 0x7920, 0xB551, 0x7921, 0xB552, 0x7922, 0xB553,
+ 0x7923, 0xB554, 0x7924, 0xEDE5, 0x7925, 0xB555, 0x7926, 0xB556, 0x7927, 0xB557, 0x7928, 0xB558, 0x7929, 0xB559, 0x792A, 0xB55A,
+ 0x792B, 0xB55B, 0x792C, 0xB55C, 0x792D, 0xB55D, 0x792E, 0xB55E, 0x792F, 0xB55F, 0x7930, 0xB560, 0x7931, 0xB561, 0x7932, 0xB562,
+ 0x7933, 0xB563, 0x7934, 0xEDE7, 0x7935, 0xB564, 0x7936, 0xB565, 0x7937, 0xB566, 0x7938, 0xB567, 0x7939, 0xB568, 0x793A, 0xCABE,
+ 0x793B, 0xECEA, 0x793C, 0xC0F1, 0x793D, 0xB569, 0x793E, 0xC9E7, 0x793F, 0xB56A, 0x7940, 0xECEB, 0x7941, 0xC6EE, 0x7942, 0xB56B,
+ 0x7943, 0xB56C, 0x7944, 0xB56D, 0x7945, 0xB56E, 0x7946, 0xECEC, 0x7947, 0xB56F, 0x7948, 0xC6ED, 0x7949, 0xECED, 0x794A, 0xB570,
+ 0x794B, 0xB571, 0x794C, 0xB572, 0x794D, 0xB573, 0x794E, 0xB574, 0x794F, 0xB575, 0x7950, 0xB576, 0x7951, 0xB577, 0x7952, 0xB578,
+ 0x7953, 0xECF0, 0x7954, 0xB579, 0x7955, 0xB57A, 0x7956, 0xD7E6, 0x7957, 0xECF3, 0x7958, 0xB57B, 0x7959, 0xB57C, 0x795A, 0xECF1,
+ 0x795B, 0xECEE, 0x795C, 0xECEF, 0x795D, 0xD7A3, 0x795E, 0xC9F1, 0x795F, 0xCBEE, 0x7960, 0xECF4, 0x7961, 0xB57D, 0x7962, 0xECF2,
+ 0x7963, 0xB57E, 0x7964, 0xB580, 0x7965, 0xCFE9, 0x7966, 0xB581, 0x7967, 0xECF6, 0x7968, 0xC6B1, 0x7969, 0xB582, 0x796A, 0xB583,
+ 0x796B, 0xB584, 0x796C, 0xB585, 0x796D, 0xBCC0, 0x796E, 0xB586, 0x796F, 0xECF5, 0x7970, 0xB587, 0x7971, 0xB588, 0x7972, 0xB589,
+ 0x7973, 0xB58A, 0x7974, 0xB58B, 0x7975, 0xB58C, 0x7976, 0xB58D, 0x7977, 0xB5BB, 0x7978, 0xBBF6, 0x7979, 0xB58E, 0x797A, 0xECF7,
+ 0x797B, 0xB58F, 0x797C, 0xB590, 0x797D, 0xB591, 0x797E, 0xB592, 0x797F, 0xB593, 0x7980, 0xD9F7, 0x7981, 0xBDFB, 0x7982, 0xB594,
+ 0x7983, 0xB595, 0x7984, 0xC2BB, 0x7985, 0xECF8, 0x7986, 0xB596, 0x7987, 0xB597, 0x7988, 0xB598, 0x7989, 0xB599, 0x798A, 0xECF9,
+ 0x798B, 0xB59A, 0x798C, 0xB59B, 0x798D, 0xB59C, 0x798E, 0xB59D, 0x798F, 0xB8A3, 0x7990, 0xB59E, 0x7991, 0xB59F, 0x7992, 0xB5A0,
+ 0x7993, 0xB640, 0x7994, 0xB641, 0x7995, 0xB642, 0x7996, 0xB643, 0x7997, 0xB644, 0x7998, 0xB645, 0x7999, 0xB646, 0x799A, 0xECFA,
+ 0x799B, 0xB647, 0x799C, 0xB648, 0x799D, 0xB649, 0x799E, 0xB64A, 0x799F, 0xB64B, 0x79A0, 0xB64C, 0x79A1, 0xB64D, 0x79A2, 0xB64E,
+ 0x79A3, 0xB64F, 0x79A4, 0xB650, 0x79A5, 0xB651, 0x79A6, 0xB652, 0x79A7, 0xECFB, 0x79A8, 0xB653, 0x79A9, 0xB654, 0x79AA, 0xB655,
+ 0x79AB, 0xB656, 0x79AC, 0xB657, 0x79AD, 0xB658, 0x79AE, 0xB659, 0x79AF, 0xB65A, 0x79B0, 0xB65B, 0x79B1, 0xB65C, 0x79B2, 0xB65D,
+ 0x79B3, 0xECFC, 0x79B4, 0xB65E, 0x79B5, 0xB65F, 0x79B6, 0xB660, 0x79B7, 0xB661, 0x79B8, 0xB662, 0x79B9, 0xD3ED, 0x79BA, 0xD8AE,
+ 0x79BB, 0xC0EB, 0x79BC, 0xB663, 0x79BD, 0xC7DD, 0x79BE, 0xBACC, 0x79BF, 0xB664, 0x79C0, 0xD0E3, 0x79C1, 0xCBBD, 0x79C2, 0xB665,
+ 0x79C3, 0xCDBA, 0x79C4, 0xB666, 0x79C5, 0xB667, 0x79C6, 0xB8D1, 0x79C7, 0xB668, 0x79C8, 0xB669, 0x79C9, 0xB1FC, 0x79CA, 0xB66A,
+ 0x79CB, 0xC7EF, 0x79CC, 0xB66B, 0x79CD, 0xD6D6, 0x79CE, 0xB66C, 0x79CF, 0xB66D, 0x79D0, 0xB66E, 0x79D1, 0xBFC6, 0x79D2, 0xC3EB,
+ 0x79D3, 0xB66F, 0x79D4, 0xB670, 0x79D5, 0xEFF5, 0x79D6, 0xB671, 0x79D7, 0xB672, 0x79D8, 0xC3D8, 0x79D9, 0xB673, 0x79DA, 0xB674,
+ 0x79DB, 0xB675, 0x79DC, 0xB676, 0x79DD, 0xB677, 0x79DE, 0xB678, 0x79DF, 0xD7E2, 0x79E0, 0xB679, 0x79E1, 0xB67A, 0x79E2, 0xB67B,
+ 0x79E3, 0xEFF7, 0x79E4, 0xB3D3, 0x79E5, 0xB67C, 0x79E6, 0xC7D8, 0x79E7, 0xD1ED, 0x79E8, 0xB67D, 0x79E9, 0xD6C8, 0x79EA, 0xB67E,
+ 0x79EB, 0xEFF8, 0x79EC, 0xB680, 0x79ED, 0xEFF6, 0x79EE, 0xB681, 0x79EF, 0xBBFD, 0x79F0, 0xB3C6, 0x79F1, 0xB682, 0x79F2, 0xB683,
+ 0x79F3, 0xB684, 0x79F4, 0xB685, 0x79F5, 0xB686, 0x79F6, 0xB687, 0x79F7, 0xB688, 0x79F8, 0xBDD5, 0x79F9, 0xB689, 0x79FA, 0xB68A,
+ 0x79FB, 0xD2C6, 0x79FC, 0xB68B, 0x79FD, 0xBBE0, 0x79FE, 0xB68C, 0x79FF, 0xB68D, 0x7A00, 0xCFA1, 0x7A01, 0xB68E, 0x7A02, 0xEFFC,
+ 0x7A03, 0xEFFB, 0x7A04, 0xB68F, 0x7A05, 0xB690, 0x7A06, 0xEFF9, 0x7A07, 0xB691, 0x7A08, 0xB692, 0x7A09, 0xB693, 0x7A0A, 0xB694,
+ 0x7A0B, 0xB3CC, 0x7A0C, 0xB695, 0x7A0D, 0xC9D4, 0x7A0E, 0xCBB0, 0x7A0F, 0xB696, 0x7A10, 0xB697, 0x7A11, 0xB698, 0x7A12, 0xB699,
+ 0x7A13, 0xB69A, 0x7A14, 0xEFFE, 0x7A15, 0xB69B, 0x7A16, 0xB69C, 0x7A17, 0xB0DE, 0x7A18, 0xB69D, 0x7A19, 0xB69E, 0x7A1A, 0xD6C9,
+ 0x7A1B, 0xB69F, 0x7A1C, 0xB6A0, 0x7A1D, 0xB740, 0x7A1E, 0xEFFD, 0x7A1F, 0xB741, 0x7A20, 0xB3ED, 0x7A21, 0xB742, 0x7A22, 0xB743,
+ 0x7A23, 0xF6D5, 0x7A24, 0xB744, 0x7A25, 0xB745, 0x7A26, 0xB746, 0x7A27, 0xB747, 0x7A28, 0xB748, 0x7A29, 0xB749, 0x7A2A, 0xB74A,
+ 0x7A2B, 0xB74B, 0x7A2C, 0xB74C, 0x7A2D, 0xB74D, 0x7A2E, 0xB74E, 0x7A2F, 0xB74F, 0x7A30, 0xB750, 0x7A31, 0xB751, 0x7A32, 0xB752,
+ 0x7A33, 0xCEC8, 0x7A34, 0xB753, 0x7A35, 0xB754, 0x7A36, 0xB755, 0x7A37, 0xF0A2, 0x7A38, 0xB756, 0x7A39, 0xF0A1, 0x7A3A, 0xB757,
+ 0x7A3B, 0xB5BE, 0x7A3C, 0xBCDA, 0x7A3D, 0xBBFC, 0x7A3E, 0xB758, 0x7A3F, 0xB8E5, 0x7A40, 0xB759, 0x7A41, 0xB75A, 0x7A42, 0xB75B,
+ 0x7A43, 0xB75C, 0x7A44, 0xB75D, 0x7A45, 0xB75E, 0x7A46, 0xC4C2, 0x7A47, 0xB75F, 0x7A48, 0xB760, 0x7A49, 0xB761, 0x7A4A, 0xB762,
+ 0x7A4B, 0xB763, 0x7A4C, 0xB764, 0x7A4D, 0xB765, 0x7A4E, 0xB766, 0x7A4F, 0xB767, 0x7A50, 0xB768, 0x7A51, 0xF0A3, 0x7A52, 0xB769,
+ 0x7A53, 0xB76A, 0x7A54, 0xB76B, 0x7A55, 0xB76C, 0x7A56, 0xB76D, 0x7A57, 0xCBEB, 0x7A58, 0xB76E, 0x7A59, 0xB76F, 0x7A5A, 0xB770,
+ 0x7A5B, 0xB771, 0x7A5C, 0xB772, 0x7A5D, 0xB773, 0x7A5E, 0xB774, 0x7A5F, 0xB775, 0x7A60, 0xB776, 0x7A61, 0xB777, 0x7A62, 0xB778,
+ 0x7A63, 0xB779, 0x7A64, 0xB77A, 0x7A65, 0xB77B, 0x7A66, 0xB77C, 0x7A67, 0xB77D, 0x7A68, 0xB77E, 0x7A69, 0xB780, 0x7A6A, 0xB781,
+ 0x7A6B, 0xB782, 0x7A6C, 0xB783, 0x7A6D, 0xB784, 0x7A6E, 0xB785, 0x7A6F, 0xB786, 0x7A70, 0xF0A6, 0x7A71, 0xB787, 0x7A72, 0xB788,
+ 0x7A73, 0xB789, 0x7A74, 0xD1A8, 0x7A75, 0xB78A, 0x7A76, 0xBEBF, 0x7A77, 0xC7EE, 0x7A78, 0xF1B6, 0x7A79, 0xF1B7, 0x7A7A, 0xBFD5,
+ 0x7A7B, 0xB78B, 0x7A7C, 0xB78C, 0x7A7D, 0xB78D, 0x7A7E, 0xB78E, 0x7A7F, 0xB4A9, 0x7A80, 0xF1B8, 0x7A81, 0xCDBB, 0x7A82, 0xB78F,
+ 0x7A83, 0xC7D4, 0x7A84, 0xD5AD, 0x7A85, 0xB790, 0x7A86, 0xF1B9, 0x7A87, 0xB791, 0x7A88, 0xF1BA, 0x7A89, 0xB792, 0x7A8A, 0xB793,
+ 0x7A8B, 0xB794, 0x7A8C, 0xB795, 0x7A8D, 0xC7CF, 0x7A8E, 0xB796, 0x7A8F, 0xB797, 0x7A90, 0xB798, 0x7A91, 0xD2A4, 0x7A92, 0xD6CF,
+ 0x7A93, 0xB799, 0x7A94, 0xB79A, 0x7A95, 0xF1BB, 0x7A96, 0xBDD1, 0x7A97, 0xB4B0, 0x7A98, 0xBEBD, 0x7A99, 0xB79B, 0x7A9A, 0xB79C,
+ 0x7A9B, 0xB79D, 0x7A9C, 0xB4DC, 0x7A9D, 0xCED1, 0x7A9E, 0xB79E, 0x7A9F, 0xBFDF, 0x7AA0, 0xF1BD, 0x7AA1, 0xB79F, 0x7AA2, 0xB7A0,
+ 0x7AA3, 0xB840, 0x7AA4, 0xB841, 0x7AA5, 0xBFFA, 0x7AA6, 0xF1BC, 0x7AA7, 0xB842, 0x7AA8, 0xF1BF, 0x7AA9, 0xB843, 0x7AAA, 0xB844,
+ 0x7AAB, 0xB845, 0x7AAC, 0xF1BE, 0x7AAD, 0xF1C0, 0x7AAE, 0xB846, 0x7AAF, 0xB847, 0x7AB0, 0xB848, 0x7AB1, 0xB849, 0x7AB2, 0xB84A,
+ 0x7AB3, 0xF1C1, 0x7AB4, 0xB84B, 0x7AB5, 0xB84C, 0x7AB6, 0xB84D, 0x7AB7, 0xB84E, 0x7AB8, 0xB84F, 0x7AB9, 0xB850, 0x7ABA, 0xB851,
+ 0x7ABB, 0xB852, 0x7ABC, 0xB853, 0x7ABD, 0xB854, 0x7ABE, 0xB855, 0x7ABF, 0xC1FE, 0x7AC0, 0xB856, 0x7AC1, 0xB857, 0x7AC2, 0xB858,
+ 0x7AC3, 0xB859, 0x7AC4, 0xB85A, 0x7AC5, 0xB85B, 0x7AC6, 0xB85C, 0x7AC7, 0xB85D, 0x7AC8, 0xB85E, 0x7AC9, 0xB85F, 0x7ACA, 0xB860,
+ 0x7ACB, 0xC1A2, 0x7ACC, 0xB861, 0x7ACD, 0xB862, 0x7ACE, 0xB863, 0x7ACF, 0xB864, 0x7AD0, 0xB865, 0x7AD1, 0xB866, 0x7AD2, 0xB867,
+ 0x7AD3, 0xB868, 0x7AD4, 0xB869, 0x7AD5, 0xB86A, 0x7AD6, 0xCAFA, 0x7AD7, 0xB86B, 0x7AD8, 0xB86C, 0x7AD9, 0xD5BE, 0x7ADA, 0xB86D,
+ 0x7ADB, 0xB86E, 0x7ADC, 0xB86F, 0x7ADD, 0xB870, 0x7ADE, 0xBEBA, 0x7ADF, 0xBEB9, 0x7AE0, 0xD5C2, 0x7AE1, 0xB871, 0x7AE2, 0xB872,
+ 0x7AE3, 0xBFA2, 0x7AE4, 0xB873, 0x7AE5, 0xCDAF, 0x7AE6, 0xF1B5, 0x7AE7, 0xB874, 0x7AE8, 0xB875, 0x7AE9, 0xB876, 0x7AEA, 0xB877,
+ 0x7AEB, 0xB878, 0x7AEC, 0xB879, 0x7AED, 0xBDDF, 0x7AEE, 0xB87A, 0x7AEF, 0xB6CB, 0x7AF0, 0xB87B, 0x7AF1, 0xB87C, 0x7AF2, 0xB87D,
+ 0x7AF3, 0xB87E, 0x7AF4, 0xB880, 0x7AF5, 0xB881, 0x7AF6, 0xB882, 0x7AF7, 0xB883, 0x7AF8, 0xB884, 0x7AF9, 0xD6F1, 0x7AFA, 0xF3C3,
+ 0x7AFB, 0xB885, 0x7AFC, 0xB886, 0x7AFD, 0xF3C4, 0x7AFE, 0xB887, 0x7AFF, 0xB8CD, 0x7B00, 0xB888, 0x7B01, 0xB889, 0x7B02, 0xB88A,
+ 0x7B03, 0xF3C6, 0x7B04, 0xF3C7, 0x7B05, 0xB88B, 0x7B06, 0xB0CA, 0x7B07, 0xB88C, 0x7B08, 0xF3C5, 0x7B09, 0xB88D, 0x7B0A, 0xF3C9,
+ 0x7B0B, 0xCBF1, 0x7B0C, 0xB88E, 0x7B0D, 0xB88F, 0x7B0E, 0xB890, 0x7B0F, 0xF3CB, 0x7B10, 0xB891, 0x7B11, 0xD0A6, 0x7B12, 0xB892,
+ 0x7B13, 0xB893, 0x7B14, 0xB1CA, 0x7B15, 0xF3C8, 0x7B16, 0xB894, 0x7B17, 0xB895, 0x7B18, 0xB896, 0x7B19, 0xF3CF, 0x7B1A, 0xB897,
+ 0x7B1B, 0xB5D1, 0x7B1C, 0xB898, 0x7B1D, 0xB899, 0x7B1E, 0xF3D7, 0x7B1F, 0xB89A, 0x7B20, 0xF3D2, 0x7B21, 0xB89B, 0x7B22, 0xB89C,
+ 0x7B23, 0xB89D, 0x7B24, 0xF3D4, 0x7B25, 0xF3D3, 0x7B26, 0xB7FB, 0x7B27, 0xB89E, 0x7B28, 0xB1BF, 0x7B29, 0xB89F, 0x7B2A, 0xF3CE,
+ 0x7B2B, 0xF3CA, 0x7B2C, 0xB5DA, 0x7B2D, 0xB8A0, 0x7B2E, 0xF3D0, 0x7B2F, 0xB940, 0x7B30, 0xB941, 0x7B31, 0xF3D1, 0x7B32, 0xB942,
+ 0x7B33, 0xF3D5, 0x7B34, 0xB943, 0x7B35, 0xB944, 0x7B36, 0xB945, 0x7B37, 0xB946, 0x7B38, 0xF3CD, 0x7B39, 0xB947, 0x7B3A, 0xBCE3,
+ 0x7B3B, 0xB948, 0x7B3C, 0xC1FD, 0x7B3D, 0xB949, 0x7B3E, 0xF3D6, 0x7B3F, 0xB94A, 0x7B40, 0xB94B, 0x7B41, 0xB94C, 0x7B42, 0xB94D,
+ 0x7B43, 0xB94E, 0x7B44, 0xB94F, 0x7B45, 0xF3DA, 0x7B46, 0xB950, 0x7B47, 0xF3CC, 0x7B48, 0xB951, 0x7B49, 0xB5C8, 0x7B4A, 0xB952,
+ 0x7B4B, 0xBDEE, 0x7B4C, 0xF3DC, 0x7B4D, 0xB953, 0x7B4E, 0xB954, 0x7B4F, 0xB7A4, 0x7B50, 0xBFF0, 0x7B51, 0xD6FE, 0x7B52, 0xCDB2,
+ 0x7B53, 0xB955, 0x7B54, 0xB4F0, 0x7B55, 0xB956, 0x7B56, 0xB2DF, 0x7B57, 0xB957, 0x7B58, 0xF3D8, 0x7B59, 0xB958, 0x7B5A, 0xF3D9,
+ 0x7B5B, 0xC9B8, 0x7B5C, 0xB959, 0x7B5D, 0xF3DD, 0x7B5E, 0xB95A, 0x7B5F, 0xB95B, 0x7B60, 0xF3DE, 0x7B61, 0xB95C, 0x7B62, 0xF3E1,
+ 0x7B63, 0xB95D, 0x7B64, 0xB95E, 0x7B65, 0xB95F, 0x7B66, 0xB960, 0x7B67, 0xB961, 0x7B68, 0xB962, 0x7B69, 0xB963, 0x7B6A, 0xB964,
+ 0x7B6B, 0xB965, 0x7B6C, 0xB966, 0x7B6D, 0xB967, 0x7B6E, 0xF3DF, 0x7B6F, 0xB968, 0x7B70, 0xB969, 0x7B71, 0xF3E3, 0x7B72, 0xF3E2,
+ 0x7B73, 0xB96A, 0x7B74, 0xB96B, 0x7B75, 0xF3DB, 0x7B76, 0xB96C, 0x7B77, 0xBFEA, 0x7B78, 0xB96D, 0x7B79, 0xB3EF, 0x7B7A, 0xB96E,
+ 0x7B7B, 0xF3E0, 0x7B7C, 0xB96F, 0x7B7D, 0xB970, 0x7B7E, 0xC7A9, 0x7B7F, 0xB971, 0x7B80, 0xBCF2, 0x7B81, 0xB972, 0x7B82, 0xB973,
+ 0x7B83, 0xB974, 0x7B84, 0xB975, 0x7B85, 0xF3EB, 0x7B86, 0xB976, 0x7B87, 0xB977, 0x7B88, 0xB978, 0x7B89, 0xB979, 0x7B8A, 0xB97A,
+ 0x7B8B, 0xB97B, 0x7B8C, 0xB97C, 0x7B8D, 0xB9BF, 0x7B8E, 0xB97D, 0x7B8F, 0xB97E, 0x7B90, 0xF3E4, 0x7B91, 0xB980, 0x7B92, 0xB981,
+ 0x7B93, 0xB982, 0x7B94, 0xB2AD, 0x7B95, 0xBBFE, 0x7B96, 0xB983, 0x7B97, 0xCBE3, 0x7B98, 0xB984, 0x7B99, 0xB985, 0x7B9A, 0xB986,
+ 0x7B9B, 0xB987, 0x7B9C, 0xF3ED, 0x7B9D, 0xF3E9, 0x7B9E, 0xB988, 0x7B9F, 0xB989, 0x7BA0, 0xB98A, 0x7BA1, 0xB9DC, 0x7BA2, 0xF3EE,
+ 0x7BA3, 0xB98B, 0x7BA4, 0xB98C, 0x7BA5, 0xB98D, 0x7BA6, 0xF3E5, 0x7BA7, 0xF3E6, 0x7BA8, 0xF3EA, 0x7BA9, 0xC2E1, 0x7BAA, 0xF3EC,
+ 0x7BAB, 0xF3EF, 0x7BAC, 0xF3E8, 0x7BAD, 0xBCFD, 0x7BAE, 0xB98E, 0x7BAF, 0xB98F, 0x7BB0, 0xB990, 0x7BB1, 0xCFE4, 0x7BB2, 0xB991,
+ 0x7BB3, 0xB992, 0x7BB4, 0xF3F0, 0x7BB5, 0xB993, 0x7BB6, 0xB994, 0x7BB7, 0xB995, 0x7BB8, 0xF3E7, 0x7BB9, 0xB996, 0x7BBA, 0xB997,
+ 0x7BBB, 0xB998, 0x7BBC, 0xB999, 0x7BBD, 0xB99A, 0x7BBE, 0xB99B, 0x7BBF, 0xB99C, 0x7BC0, 0xB99D, 0x7BC1, 0xF3F2, 0x7BC2, 0xB99E,
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+ 0x7E5B, 0xBF9E, 0x7E5C, 0xBF9F, 0x7E5D, 0xBFA0, 0x7E5E, 0xC040, 0x7E5F, 0xC041, 0x7E60, 0xC042, 0x7E61, 0xC043, 0x7E62, 0xC044,
+ 0x7E63, 0xC045, 0x7E64, 0xC046, 0x7E65, 0xC047, 0x7E66, 0xC048, 0x7E67, 0xC049, 0x7E68, 0xC04A, 0x7E69, 0xC04B, 0x7E6A, 0xC04C,
+ 0x7E6B, 0xC04D, 0x7E6C, 0xC04E, 0x7E6D, 0xC04F, 0x7E6E, 0xC050, 0x7E6F, 0xC051, 0x7E70, 0xC052, 0x7E71, 0xC053, 0x7E72, 0xC054,
+ 0x7E73, 0xC055, 0x7E74, 0xC056, 0x7E75, 0xC057, 0x7E76, 0xC058, 0x7E77, 0xC059, 0x7E78, 0xC05A, 0x7E79, 0xC05B, 0x7E7A, 0xC05C,
+ 0x7E7B, 0xC05D, 0x7E7C, 0xC05E, 0x7E7D, 0xC05F, 0x7E7E, 0xC060, 0x7E7F, 0xC061, 0x7E80, 0xC062, 0x7E81, 0xC063, 0x7E82, 0xD7EB,
+ 0x7E83, 0xC064, 0x7E84, 0xC065, 0x7E85, 0xC066, 0x7E86, 0xC067, 0x7E87, 0xC068, 0x7E88, 0xC069, 0x7E89, 0xC06A, 0x7E8A, 0xC06B,
+ 0x7E8B, 0xC06C, 0x7E8C, 0xC06D, 0x7E8D, 0xC06E, 0x7E8E, 0xC06F, 0x7E8F, 0xC070, 0x7E90, 0xC071, 0x7E91, 0xC072, 0x7E92, 0xC073,
+ 0x7E93, 0xC074, 0x7E94, 0xC075, 0x7E95, 0xC076, 0x7E96, 0xC077, 0x7E97, 0xC078, 0x7E98, 0xC079, 0x7E99, 0xC07A, 0x7E9A, 0xC07B,
+ 0x7E9B, 0xF4EE, 0x7E9C, 0xC07C, 0x7E9D, 0xC07D, 0x7E9E, 0xC07E, 0x7E9F, 0xE6F9, 0x7EA0, 0xBEC0, 0x7EA1, 0xE6FA, 0x7EA2, 0xBAEC,
+ 0x7EA3, 0xE6FB, 0x7EA4, 0xCFCB, 0x7EA5, 0xE6FC, 0x7EA6, 0xD4BC, 0x7EA7, 0xBCB6, 0x7EA8, 0xE6FD, 0x7EA9, 0xE6FE, 0x7EAA, 0xBCCD,
+ 0x7EAB, 0xC8D2, 0x7EAC, 0xCEB3, 0x7EAD, 0xE7A1, 0x7EAE, 0xC080, 0x7EAF, 0xB4BF, 0x7EB0, 0xE7A2, 0x7EB1, 0xC9B4, 0x7EB2, 0xB8D9,
+ 0x7EB3, 0xC4C9, 0x7EB4, 0xC081, 0x7EB5, 0xD7DD, 0x7EB6, 0xC2DA, 0x7EB7, 0xB7D7, 0x7EB8, 0xD6BD, 0x7EB9, 0xCEC6, 0x7EBA, 0xB7C4,
+ 0x7EBB, 0xC082, 0x7EBC, 0xC083, 0x7EBD, 0xC5A6, 0x7EBE, 0xE7A3, 0x7EBF, 0xCFDF, 0x7EC0, 0xE7A4, 0x7EC1, 0xE7A5, 0x7EC2, 0xE7A6,
+ 0x7EC3, 0xC1B7, 0x7EC4, 0xD7E9, 0x7EC5, 0xC9F0, 0x7EC6, 0xCFB8, 0x7EC7, 0xD6AF, 0x7EC8, 0xD6D5, 0x7EC9, 0xE7A7, 0x7ECA, 0xB0ED,
+ 0x7ECB, 0xE7A8, 0x7ECC, 0xE7A9, 0x7ECD, 0xC9DC, 0x7ECE, 0xD2EF, 0x7ECF, 0xBEAD, 0x7ED0, 0xE7AA, 0x7ED1, 0xB0F3, 0x7ED2, 0xC8DE,
+ 0x7ED3, 0xBDE1, 0x7ED4, 0xE7AB, 0x7ED5, 0xC8C6, 0x7ED6, 0xC084, 0x7ED7, 0xE7AC, 0x7ED8, 0xBBE6, 0x7ED9, 0xB8F8, 0x7EDA, 0xD1A4,
+ 0x7EDB, 0xE7AD, 0x7EDC, 0xC2E7, 0x7EDD, 0xBEF8, 0x7EDE, 0xBDCA, 0x7EDF, 0xCDB3, 0x7EE0, 0xE7AE, 0x7EE1, 0xE7AF, 0x7EE2, 0xBEEE,
+ 0x7EE3, 0xD0E5, 0x7EE4, 0xC085, 0x7EE5, 0xCBE7, 0x7EE6, 0xCCD0, 0x7EE7, 0xBCCC, 0x7EE8, 0xE7B0, 0x7EE9, 0xBCA8, 0x7EEA, 0xD0F7,
+ 0x7EEB, 0xE7B1, 0x7EEC, 0xC086, 0x7EED, 0xD0F8, 0x7EEE, 0xE7B2, 0x7EEF, 0xE7B3, 0x7EF0, 0xB4C2, 0x7EF1, 0xE7B4, 0x7EF2, 0xE7B5,
+ 0x7EF3, 0xC9FE, 0x7EF4, 0xCEAC, 0x7EF5, 0xC3E0, 0x7EF6, 0xE7B7, 0x7EF7, 0xB1C1, 0x7EF8, 0xB3F1, 0x7EF9, 0xC087, 0x7EFA, 0xE7B8,
+ 0x7EFB, 0xE7B9, 0x7EFC, 0xD7DB, 0x7EFD, 0xD5C0, 0x7EFE, 0xE7BA, 0x7EFF, 0xC2CC, 0x7F00, 0xD7BA, 0x7F01, 0xE7BB, 0x7F02, 0xE7BC,
+ 0x7F03, 0xE7BD, 0x7F04, 0xBCEA, 0x7F05, 0xC3E5, 0x7F06, 0xC0C2, 0x7F07, 0xE7BE, 0x7F08, 0xE7BF, 0x7F09, 0xBCA9, 0x7F0A, 0xC088,
+ 0x7F0B, 0xE7C0, 0x7F0C, 0xE7C1, 0x7F0D, 0xE7B6, 0x7F0E, 0xB6D0, 0x7F0F, 0xE7C2, 0x7F10, 0xC089, 0x7F11, 0xE7C3, 0x7F12, 0xE7C4,
+ 0x7F13, 0xBBBA, 0x7F14, 0xB5DE, 0x7F15, 0xC2C6, 0x7F16, 0xB1E0, 0x7F17, 0xE7C5, 0x7F18, 0xD4B5, 0x7F19, 0xE7C6, 0x7F1A, 0xB8BF,
+ 0x7F1B, 0xE7C8, 0x7F1C, 0xE7C7, 0x7F1D, 0xB7EC, 0x7F1E, 0xC08A, 0x7F1F, 0xE7C9, 0x7F20, 0xB2F8, 0x7F21, 0xE7CA, 0x7F22, 0xE7CB,
+ 0x7F23, 0xE7CC, 0x7F24, 0xE7CD, 0x7F25, 0xE7CE, 0x7F26, 0xE7CF, 0x7F27, 0xE7D0, 0x7F28, 0xD3A7, 0x7F29, 0xCBF5, 0x7F2A, 0xE7D1,
+ 0x7F2B, 0xE7D2, 0x7F2C, 0xE7D3, 0x7F2D, 0xE7D4, 0x7F2E, 0xC9C9, 0x7F2F, 0xE7D5, 0x7F30, 0xE7D6, 0x7F31, 0xE7D7, 0x7F32, 0xE7D8,
+ 0x7F33, 0xE7D9, 0x7F34, 0xBDC9, 0x7F35, 0xE7DA, 0x7F36, 0xF3BE, 0x7F37, 0xC08B, 0x7F38, 0xB8D7, 0x7F39, 0xC08C, 0x7F3A, 0xC8B1,
+ 0x7F3B, 0xC08D, 0x7F3C, 0xC08E, 0x7F3D, 0xC08F, 0x7F3E, 0xC090, 0x7F3F, 0xC091, 0x7F40, 0xC092, 0x7F41, 0xC093, 0x7F42, 0xF3BF,
+ 0x7F43, 0xC094, 0x7F44, 0xF3C0, 0x7F45, 0xF3C1, 0x7F46, 0xC095, 0x7F47, 0xC096, 0x7F48, 0xC097, 0x7F49, 0xC098, 0x7F4A, 0xC099,
+ 0x7F4B, 0xC09A, 0x7F4C, 0xC09B, 0x7F4D, 0xC09C, 0x7F4E, 0xC09D, 0x7F4F, 0xC09E, 0x7F50, 0xB9DE, 0x7F51, 0xCDF8, 0x7F52, 0xC09F,
+ 0x7F53, 0xC0A0, 0x7F54, 0xD8E8, 0x7F55, 0xBAB1, 0x7F56, 0xC140, 0x7F57, 0xC2DE, 0x7F58, 0xEEB7, 0x7F59, 0xC141, 0x7F5A, 0xB7A3,
+ 0x7F5B, 0xC142, 0x7F5C, 0xC143, 0x7F5D, 0xC144, 0x7F5E, 0xC145, 0x7F5F, 0xEEB9, 0x7F60, 0xC146, 0x7F61, 0xEEB8, 0x7F62, 0xB0D5,
+ 0x7F63, 0xC147, 0x7F64, 0xC148, 0x7F65, 0xC149, 0x7F66, 0xC14A, 0x7F67, 0xC14B, 0x7F68, 0xEEBB, 0x7F69, 0xD5D6, 0x7F6A, 0xD7EF,
+ 0x7F6B, 0xC14C, 0x7F6C, 0xC14D, 0x7F6D, 0xC14E, 0x7F6E, 0xD6C3, 0x7F6F, 0xC14F, 0x7F70, 0xC150, 0x7F71, 0xEEBD, 0x7F72, 0xCAF0,
+ 0x7F73, 0xC151, 0x7F74, 0xEEBC, 0x7F75, 0xC152, 0x7F76, 0xC153, 0x7F77, 0xC154, 0x7F78, 0xC155, 0x7F79, 0xEEBE, 0x7F7A, 0xC156,
+ 0x7F7B, 0xC157, 0x7F7C, 0xC158, 0x7F7D, 0xC159, 0x7F7E, 0xEEC0, 0x7F7F, 0xC15A, 0x7F80, 0xC15B, 0x7F81, 0xEEBF, 0x7F82, 0xC15C,
+ 0x7F83, 0xC15D, 0x7F84, 0xC15E, 0x7F85, 0xC15F, 0x7F86, 0xC160, 0x7F87, 0xC161, 0x7F88, 0xC162, 0x7F89, 0xC163, 0x7F8A, 0xD1F2,
+ 0x7F8B, 0xC164, 0x7F8C, 0xC7BC, 0x7F8D, 0xC165, 0x7F8E, 0xC3C0, 0x7F8F, 0xC166, 0x7F90, 0xC167, 0x7F91, 0xC168, 0x7F92, 0xC169,
+ 0x7F93, 0xC16A, 0x7F94, 0xB8E1, 0x7F95, 0xC16B, 0x7F96, 0xC16C, 0x7F97, 0xC16D, 0x7F98, 0xC16E, 0x7F99, 0xC16F, 0x7F9A, 0xC1E7,
+ 0x7F9B, 0xC170, 0x7F9C, 0xC171, 0x7F9D, 0xF4C6, 0x7F9E, 0xD0DF, 0x7F9F, 0xF4C7, 0x7FA0, 0xC172, 0x7FA1, 0xCFDB, 0x7FA2, 0xC173,
+ 0x7FA3, 0xC174, 0x7FA4, 0xC8BA, 0x7FA5, 0xC175, 0x7FA6, 0xC176, 0x7FA7, 0xF4C8, 0x7FA8, 0xC177, 0x7FA9, 0xC178, 0x7FAA, 0xC179,
+ 0x7FAB, 0xC17A, 0x7FAC, 0xC17B, 0x7FAD, 0xC17C, 0x7FAE, 0xC17D, 0x7FAF, 0xF4C9, 0x7FB0, 0xF4CA, 0x7FB1, 0xC17E, 0x7FB2, 0xF4CB,
+ 0x7FB3, 0xC180, 0x7FB4, 0xC181, 0x7FB5, 0xC182, 0x7FB6, 0xC183, 0x7FB7, 0xC184, 0x7FB8, 0xD9FA, 0x7FB9, 0xB8FE, 0x7FBA, 0xC185,
+ 0x7FBB, 0xC186, 0x7FBC, 0xE5F1, 0x7FBD, 0xD3F0, 0x7FBE, 0xC187, 0x7FBF, 0xF4E0, 0x7FC0, 0xC188, 0x7FC1, 0xCECC, 0x7FC2, 0xC189,
+ 0x7FC3, 0xC18A, 0x7FC4, 0xC18B, 0x7FC5, 0xB3E1, 0x7FC6, 0xC18C, 0x7FC7, 0xC18D, 0x7FC8, 0xC18E, 0x7FC9, 0xC18F, 0x7FCA, 0xF1B4,
+ 0x7FCB, 0xC190, 0x7FCC, 0xD2EE, 0x7FCD, 0xC191, 0x7FCE, 0xF4E1, 0x7FCF, 0xC192, 0x7FD0, 0xC193, 0x7FD1, 0xC194, 0x7FD2, 0xC195,
+ 0x7FD3, 0xC196, 0x7FD4, 0xCFE8, 0x7FD5, 0xF4E2, 0x7FD6, 0xC197, 0x7FD7, 0xC198, 0x7FD8, 0xC7CC, 0x7FD9, 0xC199, 0x7FDA, 0xC19A,
+ 0x7FDB, 0xC19B, 0x7FDC, 0xC19C, 0x7FDD, 0xC19D, 0x7FDE, 0xC19E, 0x7FDF, 0xB5D4, 0x7FE0, 0xB4E4, 0x7FE1, 0xF4E4, 0x7FE2, 0xC19F,
+ 0x7FE3, 0xC1A0, 0x7FE4, 0xC240, 0x7FE5, 0xF4E3, 0x7FE6, 0xF4E5, 0x7FE7, 0xC241, 0x7FE8, 0xC242, 0x7FE9, 0xF4E6, 0x7FEA, 0xC243,
+ 0x7FEB, 0xC244, 0x7FEC, 0xC245, 0x7FED, 0xC246, 0x7FEE, 0xF4E7, 0x7FEF, 0xC247, 0x7FF0, 0xBAB2, 0x7FF1, 0xB0BF, 0x7FF2, 0xC248,
+ 0x7FF3, 0xF4E8, 0x7FF4, 0xC249, 0x7FF5, 0xC24A, 0x7FF6, 0xC24B, 0x7FF7, 0xC24C, 0x7FF8, 0xC24D, 0x7FF9, 0xC24E, 0x7FFA, 0xC24F,
+ 0x7FFB, 0xB7AD, 0x7FFC, 0xD2ED, 0x7FFD, 0xC250, 0x7FFE, 0xC251, 0x7FFF, 0xC252, 0x8000, 0xD2AB, 0x8001, 0xC0CF, 0x8002, 0xC253,
+ 0x8003, 0xBFBC, 0x8004, 0xEBA3, 0x8005, 0xD5DF, 0x8006, 0xEAC8, 0x8007, 0xC254, 0x8008, 0xC255, 0x8009, 0xC256, 0x800A, 0xC257,
+ 0x800B, 0xF1F3, 0x800C, 0xB6F8, 0x800D, 0xCBA3, 0x800E, 0xC258, 0x800F, 0xC259, 0x8010, 0xC4CD, 0x8011, 0xC25A, 0x8012, 0xF1E7,
+ 0x8013, 0xC25B, 0x8014, 0xF1E8, 0x8015, 0xB8FB, 0x8016, 0xF1E9, 0x8017, 0xBAC4, 0x8018, 0xD4C5, 0x8019, 0xB0D2, 0x801A, 0xC25C,
+ 0x801B, 0xC25D, 0x801C, 0xF1EA, 0x801D, 0xC25E, 0x801E, 0xC25F, 0x801F, 0xC260, 0x8020, 0xF1EB, 0x8021, 0xC261, 0x8022, 0xF1EC,
+ 0x8023, 0xC262, 0x8024, 0xC263, 0x8025, 0xF1ED, 0x8026, 0xF1EE, 0x8027, 0xF1EF, 0x8028, 0xF1F1, 0x8029, 0xF1F0, 0x802A, 0xC5D5,
+ 0x802B, 0xC264, 0x802C, 0xC265, 0x802D, 0xC266, 0x802E, 0xC267, 0x802F, 0xC268, 0x8030, 0xC269, 0x8031, 0xF1F2, 0x8032, 0xC26A,
+ 0x8033, 0xB6FA, 0x8034, 0xC26B, 0x8035, 0xF1F4, 0x8036, 0xD2AE, 0x8037, 0xDEC7, 0x8038, 0xCBCA, 0x8039, 0xC26C, 0x803A, 0xC26D,
+ 0x803B, 0xB3DC, 0x803C, 0xC26E, 0x803D, 0xB5A2, 0x803E, 0xC26F, 0x803F, 0xB9A2, 0x8040, 0xC270, 0x8041, 0xC271, 0x8042, 0xC4F4,
+ 0x8043, 0xF1F5, 0x8044, 0xC272, 0x8045, 0xC273, 0x8046, 0xF1F6, 0x8047, 0xC274, 0x8048, 0xC275, 0x8049, 0xC276, 0x804A, 0xC1C4,
+ 0x804B, 0xC1FB, 0x804C, 0xD6B0, 0x804D, 0xF1F7, 0x804E, 0xC277, 0x804F, 0xC278, 0x8050, 0xC279, 0x8051, 0xC27A, 0x8052, 0xF1F8,
+ 0x8053, 0xC27B, 0x8054, 0xC1AA, 0x8055, 0xC27C, 0x8056, 0xC27D, 0x8057, 0xC27E, 0x8058, 0xC6B8, 0x8059, 0xC280, 0x805A, 0xBEDB,
+ 0x805B, 0xC281, 0x805C, 0xC282, 0x805D, 0xC283, 0x805E, 0xC284, 0x805F, 0xC285, 0x8060, 0xC286, 0x8061, 0xC287, 0x8062, 0xC288,
+ 0x8063, 0xC289, 0x8064, 0xC28A, 0x8065, 0xC28B, 0x8066, 0xC28C, 0x8067, 0xC28D, 0x8068, 0xC28E, 0x8069, 0xF1F9, 0x806A, 0xB4CF,
+ 0x806B, 0xC28F, 0x806C, 0xC290, 0x806D, 0xC291, 0x806E, 0xC292, 0x806F, 0xC293, 0x8070, 0xC294, 0x8071, 0xF1FA, 0x8072, 0xC295,
+ 0x8073, 0xC296, 0x8074, 0xC297, 0x8075, 0xC298, 0x8076, 0xC299, 0x8077, 0xC29A, 0x8078, 0xC29B, 0x8079, 0xC29C, 0x807A, 0xC29D,
+ 0x807B, 0xC29E, 0x807C, 0xC29F, 0x807D, 0xC2A0, 0x807E, 0xC340, 0x807F, 0xEDB2, 0x8080, 0xEDB1, 0x8081, 0xC341, 0x8082, 0xC342,
+ 0x8083, 0xCBE0, 0x8084, 0xD2DE, 0x8085, 0xC343, 0x8086, 0xCBC1, 0x8087, 0xD5D8, 0x8088, 0xC344, 0x8089, 0xC8E2, 0x808A, 0xC345,
+ 0x808B, 0xC0DF, 0x808C, 0xBCA1, 0x808D, 0xC346, 0x808E, 0xC347, 0x808F, 0xC348, 0x8090, 0xC349, 0x8091, 0xC34A, 0x8092, 0xC34B,
+ 0x8093, 0xEBC1, 0x8094, 0xC34C, 0x8095, 0xC34D, 0x8096, 0xD0A4, 0x8097, 0xC34E, 0x8098, 0xD6E2, 0x8099, 0xC34F, 0x809A, 0xB6C7,
+ 0x809B, 0xB8D8, 0x809C, 0xEBC0, 0x809D, 0xB8CE, 0x809E, 0xC350, 0x809F, 0xEBBF, 0x80A0, 0xB3A6, 0x80A1, 0xB9C9, 0x80A2, 0xD6AB,
+ 0x80A3, 0xC351, 0x80A4, 0xB7F4, 0x80A5, 0xB7CA, 0x80A6, 0xC352, 0x80A7, 0xC353, 0x80A8, 0xC354, 0x80A9, 0xBCE7, 0x80AA, 0xB7BE,
+ 0x80AB, 0xEBC6, 0x80AC, 0xC355, 0x80AD, 0xEBC7, 0x80AE, 0xB0B9, 0x80AF, 0xBFCF, 0x80B0, 0xC356, 0x80B1, 0xEBC5, 0x80B2, 0xD3FD,
+ 0x80B3, 0xC357, 0x80B4, 0xEBC8, 0x80B5, 0xC358, 0x80B6, 0xC359, 0x80B7, 0xEBC9, 0x80B8, 0xC35A, 0x80B9, 0xC35B, 0x80BA, 0xB7CE,
+ 0x80BB, 0xC35C, 0x80BC, 0xEBC2, 0x80BD, 0xEBC4, 0x80BE, 0xC9F6, 0x80BF, 0xD6D7, 0x80C0, 0xD5CD, 0x80C1, 0xD0B2, 0x80C2, 0xEBCF,
+ 0x80C3, 0xCEB8, 0x80C4, 0xEBD0, 0x80C5, 0xC35D, 0x80C6, 0xB5A8, 0x80C7, 0xC35E, 0x80C8, 0xC35F, 0x80C9, 0xC360, 0x80CA, 0xC361,
+ 0x80CB, 0xC362, 0x80CC, 0xB1B3, 0x80CD, 0xEBD2, 0x80CE, 0xCCA5, 0x80CF, 0xC363, 0x80D0, 0xC364, 0x80D1, 0xC365, 0x80D2, 0xC366,
+ 0x80D3, 0xC367, 0x80D4, 0xC368, 0x80D5, 0xC369, 0x80D6, 0xC5D6, 0x80D7, 0xEBD3, 0x80D8, 0xC36A, 0x80D9, 0xEBD1, 0x80DA, 0xC5DF,
+ 0x80DB, 0xEBCE, 0x80DC, 0xCAA4, 0x80DD, 0xEBD5, 0x80DE, 0xB0FB, 0x80DF, 0xC36B, 0x80E0, 0xC36C, 0x80E1, 0xBAFA, 0x80E2, 0xC36D,
+ 0x80E3, 0xC36E, 0x80E4, 0xD8B7, 0x80E5, 0xF1E3, 0x80E6, 0xC36F, 0x80E7, 0xEBCA, 0x80E8, 0xEBCB, 0x80E9, 0xEBCC, 0x80EA, 0xEBCD,
+ 0x80EB, 0xEBD6, 0x80EC, 0xE6C0, 0x80ED, 0xEBD9, 0x80EE, 0xC370, 0x80EF, 0xBFE8, 0x80F0, 0xD2C8, 0x80F1, 0xEBD7, 0x80F2, 0xEBDC,
+ 0x80F3, 0xB8EC, 0x80F4, 0xEBD8, 0x80F5, 0xC371, 0x80F6, 0xBDBA, 0x80F7, 0xC372, 0x80F8, 0xD0D8, 0x80F9, 0xC373, 0x80FA, 0xB0B7,
+ 0x80FB, 0xC374, 0x80FC, 0xEBDD, 0x80FD, 0xC4DC, 0x80FE, 0xC375, 0x80FF, 0xC376, 0x8100, 0xC377, 0x8101, 0xC378, 0x8102, 0xD6AC,
+ 0x8103, 0xC379, 0x8104, 0xC37A, 0x8105, 0xC37B, 0x8106, 0xB4E0, 0x8107, 0xC37C, 0x8108, 0xC37D, 0x8109, 0xC2F6, 0x810A, 0xBCB9,
+ 0x810B, 0xC37E, 0x810C, 0xC380, 0x810D, 0xEBDA, 0x810E, 0xEBDB, 0x810F, 0xD4E0, 0x8110, 0xC6EA, 0x8111, 0xC4D4, 0x8112, 0xEBDF,
+ 0x8113, 0xC5A7, 0x8114, 0xD9F5, 0x8115, 0xC381, 0x8116, 0xB2B1, 0x8117, 0xC382, 0x8118, 0xEBE4, 0x8119, 0xC383, 0x811A, 0xBDC5,
+ 0x811B, 0xC384, 0x811C, 0xC385, 0x811D, 0xC386, 0x811E, 0xEBE2, 0x811F, 0xC387, 0x8120, 0xC388, 0x8121, 0xC389, 0x8122, 0xC38A,
+ 0x8123, 0xC38B, 0x8124, 0xC38C, 0x8125, 0xC38D, 0x8126, 0xC38E, 0x8127, 0xC38F, 0x8128, 0xC390, 0x8129, 0xC391, 0x812A, 0xC392,
+ 0x812B, 0xC393, 0x812C, 0xEBE3, 0x812D, 0xC394, 0x812E, 0xC395, 0x812F, 0xB8AC, 0x8130, 0xC396, 0x8131, 0xCDD1, 0x8132, 0xEBE5,
+ 0x8133, 0xC397, 0x8134, 0xC398, 0x8135, 0xC399, 0x8136, 0xEBE1, 0x8137, 0xC39A, 0x8138, 0xC1B3, 0x8139, 0xC39B, 0x813A, 0xC39C,
+ 0x813B, 0xC39D, 0x813C, 0xC39E, 0x813D, 0xC39F, 0x813E, 0xC6A2, 0x813F, 0xC3A0, 0x8140, 0xC440, 0x8141, 0xC441, 0x8142, 0xC442,
+ 0x8143, 0xC443, 0x8144, 0xC444, 0x8145, 0xC445, 0x8146, 0xCCF3, 0x8147, 0xC446, 0x8148, 0xEBE6, 0x8149, 0xC447, 0x814A, 0xC0B0,
+ 0x814B, 0xD2B8, 0x814C, 0xEBE7, 0x814D, 0xC448, 0x814E, 0xC449, 0x814F, 0xC44A, 0x8150, 0xB8AF, 0x8151, 0xB8AD, 0x8152, 0xC44B,
+ 0x8153, 0xEBE8, 0x8154, 0xC7BB, 0x8155, 0xCDF3, 0x8156, 0xC44C, 0x8157, 0xC44D, 0x8158, 0xC44E, 0x8159, 0xEBEA, 0x815A, 0xEBEB,
+ 0x815B, 0xC44F, 0x815C, 0xC450, 0x815D, 0xC451, 0x815E, 0xC452, 0x815F, 0xC453, 0x8160, 0xEBED, 0x8161, 0xC454, 0x8162, 0xC455,
+ 0x8163, 0xC456, 0x8164, 0xC457, 0x8165, 0xD0C8, 0x8166, 0xC458, 0x8167, 0xEBF2, 0x8168, 0xC459, 0x8169, 0xEBEE, 0x816A, 0xC45A,
+ 0x816B, 0xC45B, 0x816C, 0xC45C, 0x816D, 0xEBF1, 0x816E, 0xC8F9, 0x816F, 0xC45D, 0x8170, 0xD1FC, 0x8171, 0xEBEC, 0x8172, 0xC45E,
+ 0x8173, 0xC45F, 0x8174, 0xEBE9, 0x8175, 0xC460, 0x8176, 0xC461, 0x8177, 0xC462, 0x8178, 0xC463, 0x8179, 0xB8B9, 0x817A, 0xCFD9,
+ 0x817B, 0xC4E5, 0x817C, 0xEBEF, 0x817D, 0xEBF0, 0x817E, 0xCCDA, 0x817F, 0xCDC8, 0x8180, 0xB0F2, 0x8181, 0xC464, 0x8182, 0xEBF6,
+ 0x8183, 0xC465, 0x8184, 0xC466, 0x8185, 0xC467, 0x8186, 0xC468, 0x8187, 0xC469, 0x8188, 0xEBF5, 0x8189, 0xC46A, 0x818A, 0xB2B2,
+ 0x818B, 0xC46B, 0x818C, 0xC46C, 0x818D, 0xC46D, 0x818E, 0xC46E, 0x818F, 0xB8E0, 0x8190, 0xC46F, 0x8191, 0xEBF7, 0x8192, 0xC470,
+ 0x8193, 0xC471, 0x8194, 0xC472, 0x8195, 0xC473, 0x8196, 0xC474, 0x8197, 0xC475, 0x8198, 0xB1EC, 0x8199, 0xC476, 0x819A, 0xC477,
+ 0x819B, 0xCCC5, 0x819C, 0xC4A4, 0x819D, 0xCFA5, 0x819E, 0xC478, 0x819F, 0xC479, 0x81A0, 0xC47A, 0x81A1, 0xC47B, 0x81A2, 0xC47C,
+ 0x81A3, 0xEBF9, 0x81A4, 0xC47D, 0x81A5, 0xC47E, 0x81A6, 0xECA2, 0x81A7, 0xC480, 0x81A8, 0xC5F2, 0x81A9, 0xC481, 0x81AA, 0xEBFA,
+ 0x81AB, 0xC482, 0x81AC, 0xC483, 0x81AD, 0xC484, 0x81AE, 0xC485, 0x81AF, 0xC486, 0x81B0, 0xC487, 0x81B1, 0xC488, 0x81B2, 0xC489,
+ 0x81B3, 0xC9C5, 0x81B4, 0xC48A, 0x81B5, 0xC48B, 0x81B6, 0xC48C, 0x81B7, 0xC48D, 0x81B8, 0xC48E, 0x81B9, 0xC48F, 0x81BA, 0xE2DF,
+ 0x81BB, 0xEBFE, 0x81BC, 0xC490, 0x81BD, 0xC491, 0x81BE, 0xC492, 0x81BF, 0xC493, 0x81C0, 0xCDCE, 0x81C1, 0xECA1, 0x81C2, 0xB1DB,
+ 0x81C3, 0xD3B7, 0x81C4, 0xC494, 0x81C5, 0xC495, 0x81C6, 0xD2DC, 0x81C7, 0xC496, 0x81C8, 0xC497, 0x81C9, 0xC498, 0x81CA, 0xEBFD,
+ 0x81CB, 0xC499, 0x81CC, 0xEBFB, 0x81CD, 0xC49A, 0x81CE, 0xC49B, 0x81CF, 0xC49C, 0x81D0, 0xC49D, 0x81D1, 0xC49E, 0x81D2, 0xC49F,
+ 0x81D3, 0xC4A0, 0x81D4, 0xC540, 0x81D5, 0xC541, 0x81D6, 0xC542, 0x81D7, 0xC543, 0x81D8, 0xC544, 0x81D9, 0xC545, 0x81DA, 0xC546,
+ 0x81DB, 0xC547, 0x81DC, 0xC548, 0x81DD, 0xC549, 0x81DE, 0xC54A, 0x81DF, 0xC54B, 0x81E0, 0xC54C, 0x81E1, 0xC54D, 0x81E2, 0xC54E,
+ 0x81E3, 0xB3BC, 0x81E4, 0xC54F, 0x81E5, 0xC550, 0x81E6, 0xC551, 0x81E7, 0xEAB0, 0x81E8, 0xC552, 0x81E9, 0xC553, 0x81EA, 0xD7D4,
+ 0x81EB, 0xC554, 0x81EC, 0xF4AB, 0x81ED, 0xB3F4, 0x81EE, 0xC555, 0x81EF, 0xC556, 0x81F0, 0xC557, 0x81F1, 0xC558, 0x81F2, 0xC559,
+ 0x81F3, 0xD6C1, 0x81F4, 0xD6C2, 0x81F5, 0xC55A, 0x81F6, 0xC55B, 0x81F7, 0xC55C, 0x81F8, 0xC55D, 0x81F9, 0xC55E, 0x81FA, 0xC55F,
+ 0x81FB, 0xD5E9, 0x81FC, 0xBECA, 0x81FD, 0xC560, 0x81FE, 0xF4A7, 0x81FF, 0xC561, 0x8200, 0xD2A8, 0x8201, 0xF4A8, 0x8202, 0xF4A9,
+ 0x8203, 0xC562, 0x8204, 0xF4AA, 0x8205, 0xBECB, 0x8206, 0xD3DF, 0x8207, 0xC563, 0x8208, 0xC564, 0x8209, 0xC565, 0x820A, 0xC566,
+ 0x820B, 0xC567, 0x820C, 0xC9E0, 0x820D, 0xC9E1, 0x820E, 0xC568, 0x820F, 0xC569, 0x8210, 0xF3C2, 0x8211, 0xC56A, 0x8212, 0xCAE6,
+ 0x8213, 0xC56B, 0x8214, 0xCCF2, 0x8215, 0xC56C, 0x8216, 0xC56D, 0x8217, 0xC56E, 0x8218, 0xC56F, 0x8219, 0xC570, 0x821A, 0xC571,
+ 0x821B, 0xE2B6, 0x821C, 0xCBB4, 0x821D, 0xC572, 0x821E, 0xCEE8, 0x821F, 0xD6DB, 0x8220, 0xC573, 0x8221, 0xF4AD, 0x8222, 0xF4AE,
+ 0x8223, 0xF4AF, 0x8224, 0xC574, 0x8225, 0xC575, 0x8226, 0xC576, 0x8227, 0xC577, 0x8228, 0xF4B2, 0x8229, 0xC578, 0x822A, 0xBABD,
+ 0x822B, 0xF4B3, 0x822C, 0xB0E3, 0x822D, 0xF4B0, 0x822E, 0xC579, 0x822F, 0xF4B1, 0x8230, 0xBDA2, 0x8231, 0xB2D5, 0x8232, 0xC57A,
+ 0x8233, 0xF4B6, 0x8234, 0xF4B7, 0x8235, 0xB6E6, 0x8236, 0xB2B0, 0x8237, 0xCFCF, 0x8238, 0xF4B4, 0x8239, 0xB4AC, 0x823A, 0xC57B,
+ 0x823B, 0xF4B5, 0x823C, 0xC57C, 0x823D, 0xC57D, 0x823E, 0xF4B8, 0x823F, 0xC57E, 0x8240, 0xC580, 0x8241, 0xC581, 0x8242, 0xC582,
+ 0x8243, 0xC583, 0x8244, 0xF4B9, 0x8245, 0xC584, 0x8246, 0xC585, 0x8247, 0xCDA7, 0x8248, 0xC586, 0x8249, 0xF4BA, 0x824A, 0xC587,
+ 0x824B, 0xF4BB, 0x824C, 0xC588, 0x824D, 0xC589, 0x824E, 0xC58A, 0x824F, 0xF4BC, 0x8250, 0xC58B, 0x8251, 0xC58C, 0x8252, 0xC58D,
+ 0x8253, 0xC58E, 0x8254, 0xC58F, 0x8255, 0xC590, 0x8256, 0xC591, 0x8257, 0xC592, 0x8258, 0xCBD2, 0x8259, 0xC593, 0x825A, 0xF4BD,
+ 0x825B, 0xC594, 0x825C, 0xC595, 0x825D, 0xC596, 0x825E, 0xC597, 0x825F, 0xF4BE, 0x8260, 0xC598, 0x8261, 0xC599, 0x8262, 0xC59A,
+ 0x8263, 0xC59B, 0x8264, 0xC59C, 0x8265, 0xC59D, 0x8266, 0xC59E, 0x8267, 0xC59F, 0x8268, 0xF4BF, 0x8269, 0xC5A0, 0x826A, 0xC640,
+ 0x826B, 0xC641, 0x826C, 0xC642, 0x826D, 0xC643, 0x826E, 0xF4DE, 0x826F, 0xC1BC, 0x8270, 0xBCE8, 0x8271, 0xC644, 0x8272, 0xC9AB,
+ 0x8273, 0xD1DE, 0x8274, 0xE5F5, 0x8275, 0xC645, 0x8276, 0xC646, 0x8277, 0xC647, 0x8278, 0xC648, 0x8279, 0xDCB3, 0x827A, 0xD2D5,
+ 0x827B, 0xC649, 0x827C, 0xC64A, 0x827D, 0xDCB4, 0x827E, 0xB0AC, 0x827F, 0xDCB5, 0x8280, 0xC64B, 0x8281, 0xC64C, 0x8282, 0xBDDA,
+ 0x8283, 0xC64D, 0x8284, 0xDCB9, 0x8285, 0xC64E, 0x8286, 0xC64F, 0x8287, 0xC650, 0x8288, 0xD8C2, 0x8289, 0xC651, 0x828A, 0xDCB7,
+ 0x828B, 0xD3F3, 0x828C, 0xC652, 0x828D, 0xC9D6, 0x828E, 0xDCBA, 0x828F, 0xDCB6, 0x8290, 0xC653, 0x8291, 0xDCBB, 0x8292, 0xC3A2,
+ 0x8293, 0xC654, 0x8294, 0xC655, 0x8295, 0xC656, 0x8296, 0xC657, 0x8297, 0xDCBC, 0x8298, 0xDCC5, 0x8299, 0xDCBD, 0x829A, 0xC658,
+ 0x829B, 0xC659, 0x829C, 0xCEDF, 0x829D, 0xD6A5, 0x829E, 0xC65A, 0x829F, 0xDCCF, 0x82A0, 0xC65B, 0x82A1, 0xDCCD, 0x82A2, 0xC65C,
+ 0x82A3, 0xC65D, 0x82A4, 0xDCD2, 0x82A5, 0xBDE6, 0x82A6, 0xC2AB, 0x82A7, 0xC65E, 0x82A8, 0xDCB8, 0x82A9, 0xDCCB, 0x82AA, 0xDCCE,
+ 0x82AB, 0xDCBE, 0x82AC, 0xB7D2, 0x82AD, 0xB0C5, 0x82AE, 0xDCC7, 0x82AF, 0xD0BE, 0x82B0, 0xDCC1, 0x82B1, 0xBBA8, 0x82B2, 0xC65F,
+ 0x82B3, 0xB7BC, 0x82B4, 0xDCCC, 0x82B5, 0xC660, 0x82B6, 0xC661, 0x82B7, 0xDCC6, 0x82B8, 0xDCBF, 0x82B9, 0xC7DB, 0x82BA, 0xC662,
+ 0x82BB, 0xC663, 0x82BC, 0xC664, 0x82BD, 0xD1BF, 0x82BE, 0xDCC0, 0x82BF, 0xC665, 0x82C0, 0xC666, 0x82C1, 0xDCCA, 0x82C2, 0xC667,
+ 0x82C3, 0xC668, 0x82C4, 0xDCD0, 0x82C5, 0xC669, 0x82C6, 0xC66A, 0x82C7, 0xCEAD, 0x82C8, 0xDCC2, 0x82C9, 0xC66B, 0x82CA, 0xDCC3,
+ 0x82CB, 0xDCC8, 0x82CC, 0xDCC9, 0x82CD, 0xB2D4, 0x82CE, 0xDCD1, 0x82CF, 0xCBD5, 0x82D0, 0xC66C, 0x82D1, 0xD4B7, 0x82D2, 0xDCDB,
+ 0x82D3, 0xDCDF, 0x82D4, 0xCCA6, 0x82D5, 0xDCE6, 0x82D6, 0xC66D, 0x82D7, 0xC3E7, 0x82D8, 0xDCDC, 0x82D9, 0xC66E, 0x82DA, 0xC66F,
+ 0x82DB, 0xBFC1, 0x82DC, 0xDCD9, 0x82DD, 0xC670, 0x82DE, 0xB0FA, 0x82DF, 0xB9B6, 0x82E0, 0xDCE5, 0x82E1, 0xDCD3, 0x82E2, 0xC671,
+ 0x82E3, 0xDCC4, 0x82E4, 0xDCD6, 0x82E5, 0xC8F4, 0x82E6, 0xBFE0, 0x82E7, 0xC672, 0x82E8, 0xC673, 0x82E9, 0xC674, 0x82EA, 0xC675,
+ 0x82EB, 0xC9BB, 0x82EC, 0xC676, 0x82ED, 0xC677, 0x82EE, 0xC678, 0x82EF, 0xB1BD, 0x82F0, 0xC679, 0x82F1, 0xD3A2, 0x82F2, 0xC67A,
+ 0x82F3, 0xC67B, 0x82F4, 0xDCDA, 0x82F5, 0xC67C, 0x82F6, 0xC67D, 0x82F7, 0xDCD5, 0x82F8, 0xC67E, 0x82F9, 0xC6BB, 0x82FA, 0xC680,
+ 0x82FB, 0xDCDE, 0x82FC, 0xC681, 0x82FD, 0xC682, 0x82FE, 0xC683, 0x82FF, 0xC684, 0x8300, 0xC685, 0x8301, 0xD7C2, 0x8302, 0xC3AF,
+ 0x8303, 0xB7B6, 0x8304, 0xC7D1, 0x8305, 0xC3A9, 0x8306, 0xDCE2, 0x8307, 0xDCD8, 0x8308, 0xDCEB, 0x8309, 0xDCD4, 0x830A, 0xC686,
+ 0x830B, 0xC687, 0x830C, 0xDCDD, 0x830D, 0xC688, 0x830E, 0xBEA5, 0x830F, 0xDCD7, 0x8310, 0xC689, 0x8311, 0xDCE0, 0x8312, 0xC68A,
+ 0x8313, 0xC68B, 0x8314, 0xDCE3, 0x8315, 0xDCE4, 0x8316, 0xC68C, 0x8317, 0xDCF8, 0x8318, 0xC68D, 0x8319, 0xC68E, 0x831A, 0xDCE1,
+ 0x831B, 0xDDA2, 0x831C, 0xDCE7, 0x831D, 0xC68F, 0x831E, 0xC690, 0x831F, 0xC691, 0x8320, 0xC692, 0x8321, 0xC693, 0x8322, 0xC694,
+ 0x8323, 0xC695, 0x8324, 0xC696, 0x8325, 0xC697, 0x8326, 0xC698, 0x8327, 0xBCEB, 0x8328, 0xB4C4, 0x8329, 0xC699, 0x832A, 0xC69A,
+ 0x832B, 0xC3A3, 0x832C, 0xB2E7, 0x832D, 0xDCFA, 0x832E, 0xC69B, 0x832F, 0xDCF2, 0x8330, 0xC69C, 0x8331, 0xDCEF, 0x8332, 0xC69D,
+ 0x8333, 0xDCFC, 0x8334, 0xDCEE, 0x8335, 0xD2F0, 0x8336, 0xB2E8, 0x8337, 0xC69E, 0x8338, 0xC8D7, 0x8339, 0xC8E3, 0x833A, 0xDCFB,
+ 0x833B, 0xC69F, 0x833C, 0xDCED, 0x833D, 0xC6A0, 0x833E, 0xC740, 0x833F, 0xC741, 0x8340, 0xDCF7, 0x8341, 0xC742, 0x8342, 0xC743,
+ 0x8343, 0xDCF5, 0x8344, 0xC744, 0x8345, 0xC745, 0x8346, 0xBEA3, 0x8347, 0xDCF4, 0x8348, 0xC746, 0x8349, 0xB2DD, 0x834A, 0xC747,
+ 0x834B, 0xC748, 0x834C, 0xC749, 0x834D, 0xC74A, 0x834E, 0xC74B, 0x834F, 0xDCF3, 0x8350, 0xBCF6, 0x8351, 0xDCE8, 0x8352, 0xBBC4,
+ 0x8353, 0xC74C, 0x8354, 0xC0F3, 0x8355, 0xC74D, 0x8356, 0xC74E, 0x8357, 0xC74F, 0x8358, 0xC750, 0x8359, 0xC751, 0x835A, 0xBCD4,
+ 0x835B, 0xDCE9, 0x835C, 0xDCEA, 0x835D, 0xC752, 0x835E, 0xDCF1, 0x835F, 0xDCF6, 0x8360, 0xDCF9, 0x8361, 0xB5B4, 0x8362, 0xC753,
+ 0x8363, 0xC8D9, 0x8364, 0xBBE7, 0x8365, 0xDCFE, 0x8366, 0xDCFD, 0x8367, 0xD3AB, 0x8368, 0xDDA1, 0x8369, 0xDDA3, 0x836A, 0xDDA5,
+ 0x836B, 0xD2F1, 0x836C, 0xDDA4, 0x836D, 0xDDA6, 0x836E, 0xDDA7, 0x836F, 0xD2A9, 0x8370, 0xC754, 0x8371, 0xC755, 0x8372, 0xC756,
+ 0x8373, 0xC757, 0x8374, 0xC758, 0x8375, 0xC759, 0x8376, 0xC75A, 0x8377, 0xBAC9, 0x8378, 0xDDA9, 0x8379, 0xC75B, 0x837A, 0xC75C,
+ 0x837B, 0xDDB6, 0x837C, 0xDDB1, 0x837D, 0xDDB4, 0x837E, 0xC75D, 0x837F, 0xC75E, 0x8380, 0xC75F, 0x8381, 0xC760, 0x8382, 0xC761,
+ 0x8383, 0xC762, 0x8384, 0xC763, 0x8385, 0xDDB0, 0x8386, 0xC6CE, 0x8387, 0xC764, 0x8388, 0xC765, 0x8389, 0xC0F2, 0x838A, 0xC766,
+ 0x838B, 0xC767, 0x838C, 0xC768, 0x838D, 0xC769, 0x838E, 0xC9AF, 0x838F, 0xC76A, 0x8390, 0xC76B, 0x8391, 0xC76C, 0x8392, 0xDCEC,
+ 0x8393, 0xDDAE, 0x8394, 0xC76D, 0x8395, 0xC76E, 0x8396, 0xC76F, 0x8397, 0xC770, 0x8398, 0xDDB7, 0x8399, 0xC771, 0x839A, 0xC772,
+ 0x839B, 0xDCF0, 0x839C, 0xDDAF, 0x839D, 0xC773, 0x839E, 0xDDB8, 0x839F, 0xC774, 0x83A0, 0xDDAC, 0x83A1, 0xC775, 0x83A2, 0xC776,
+ 0x83A3, 0xC777, 0x83A4, 0xC778, 0x83A5, 0xC779, 0x83A6, 0xC77A, 0x83A7, 0xC77B, 0x83A8, 0xDDB9, 0x83A9, 0xDDB3, 0x83AA, 0xDDAD,
+ 0x83AB, 0xC4AA, 0x83AC, 0xC77C, 0x83AD, 0xC77D, 0x83AE, 0xC77E, 0x83AF, 0xC780, 0x83B0, 0xDDA8, 0x83B1, 0xC0B3, 0x83B2, 0xC1AB,
+ 0x83B3, 0xDDAA, 0x83B4, 0xDDAB, 0x83B5, 0xC781, 0x83B6, 0xDDB2, 0x83B7, 0xBBF1, 0x83B8, 0xDDB5, 0x83B9, 0xD3A8, 0x83BA, 0xDDBA,
+ 0x83BB, 0xC782, 0x83BC, 0xDDBB, 0x83BD, 0xC3A7, 0x83BE, 0xC783, 0x83BF, 0xC784, 0x83C0, 0xDDD2, 0x83C1, 0xDDBC, 0x83C2, 0xC785,
+ 0x83C3, 0xC786, 0x83C4, 0xC787, 0x83C5, 0xDDD1, 0x83C6, 0xC788, 0x83C7, 0xB9BD, 0x83C8, 0xC789, 0x83C9, 0xC78A, 0x83CA, 0xBED5,
+ 0x83CB, 0xC78B, 0x83CC, 0xBEFA, 0x83CD, 0xC78C, 0x83CE, 0xC78D, 0x83CF, 0xBACA, 0x83D0, 0xC78E, 0x83D1, 0xC78F, 0x83D2, 0xC790,
+ 0x83D3, 0xC791, 0x83D4, 0xDDCA, 0x83D5, 0xC792, 0x83D6, 0xDDC5, 0x83D7, 0xC793, 0x83D8, 0xDDBF, 0x83D9, 0xC794, 0x83DA, 0xC795,
+ 0x83DB, 0xC796, 0x83DC, 0xB2CB, 0x83DD, 0xDDC3, 0x83DE, 0xC797, 0x83DF, 0xDDCB, 0x83E0, 0xB2A4, 0x83E1, 0xDDD5, 0x83E2, 0xC798,
+ 0x83E3, 0xC799, 0x83E4, 0xC79A, 0x83E5, 0xDDBE, 0x83E6, 0xC79B, 0x83E7, 0xC79C, 0x83E8, 0xC79D, 0x83E9, 0xC6D0, 0x83EA, 0xDDD0,
+ 0x83EB, 0xC79E, 0x83EC, 0xC79F, 0x83ED, 0xC7A0, 0x83EE, 0xC840, 0x83EF, 0xC841, 0x83F0, 0xDDD4, 0x83F1, 0xC1E2, 0x83F2, 0xB7C6,
+ 0x83F3, 0xC842, 0x83F4, 0xC843, 0x83F5, 0xC844, 0x83F6, 0xC845, 0x83F7, 0xC846, 0x83F8, 0xDDCE, 0x83F9, 0xDDCF, 0x83FA, 0xC847,
+ 0x83FB, 0xC848, 0x83FC, 0xC849, 0x83FD, 0xDDC4, 0x83FE, 0xC84A, 0x83FF, 0xC84B, 0x8400, 0xC84C, 0x8401, 0xDDBD, 0x8402, 0xC84D,
+ 0x8403, 0xDDCD, 0x8404, 0xCCD1, 0x8405, 0xC84E, 0x8406, 0xDDC9, 0x8407, 0xC84F, 0x8408, 0xC850, 0x8409, 0xC851, 0x840A, 0xC852,
+ 0x840B, 0xDDC2, 0x840C, 0xC3C8, 0x840D, 0xC6BC, 0x840E, 0xCEAE, 0x840F, 0xDDCC, 0x8410, 0xC853, 0x8411, 0xDDC8, 0x8412, 0xC854,
+ 0x8413, 0xC855, 0x8414, 0xC856, 0x8415, 0xC857, 0x8416, 0xC858, 0x8417, 0xC859, 0x8418, 0xDDC1, 0x8419, 0xC85A, 0x841A, 0xC85B,
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+ 0x86E3, 0xCD84, 0x86E4, 0xB8F2, 0x86E5, 0xCD85, 0x86E6, 0xCD86, 0x86E7, 0xCD87, 0x86E8, 0xCD88, 0x86E9, 0xF2CB, 0x86EA, 0xCD89,
+ 0x86EB, 0xCD8A, 0x86EC, 0xCD8B, 0x86ED, 0xF2CE, 0x86EE, 0xC2F9, 0x86EF, 0xCD8C, 0x86F0, 0xD5DD, 0x86F1, 0xF2CC, 0x86F2, 0xF2CD,
+ 0x86F3, 0xF2CF, 0x86F4, 0xF2D3, 0x86F5, 0xCD8D, 0x86F6, 0xCD8E, 0x86F7, 0xCD8F, 0x86F8, 0xF2D9, 0x86F9, 0xD3BC, 0x86FA, 0xCD90,
+ 0x86FB, 0xCD91, 0x86FC, 0xCD92, 0x86FD, 0xCD93, 0x86FE, 0xB6EA, 0x86FF, 0xCD94, 0x8700, 0xCAF1, 0x8701, 0xCD95, 0x8702, 0xB7E4,
+ 0x8703, 0xF2D7, 0x8704, 0xCD96, 0x8705, 0xCD97, 0x8706, 0xCD98, 0x8707, 0xF2D8, 0x8708, 0xF2DA, 0x8709, 0xF2DD, 0x870A, 0xF2DB,
+ 0x870B, 0xCD99, 0x870C, 0xCD9A, 0x870D, 0xF2DC, 0x870E, 0xCD9B, 0x870F, 0xCD9C, 0x8710, 0xCD9D, 0x8711, 0xCD9E, 0x8712, 0xD1D1,
+ 0x8713, 0xF2D1, 0x8714, 0xCD9F, 0x8715, 0xCDC9, 0x8716, 0xCDA0, 0x8717, 0xCECF, 0x8718, 0xD6A9, 0x8719, 0xCE40, 0x871A, 0xF2E3,
+ 0x871B, 0xCE41, 0x871C, 0xC3DB, 0x871D, 0xCE42, 0x871E, 0xF2E0, 0x871F, 0xCE43, 0x8720, 0xCE44, 0x8721, 0xC0AF, 0x8722, 0xF2EC,
+ 0x8723, 0xF2DE, 0x8724, 0xCE45, 0x8725, 0xF2E1, 0x8726, 0xCE46, 0x8727, 0xCE47, 0x8728, 0xCE48, 0x8729, 0xF2E8, 0x872A, 0xCE49,
+ 0x872B, 0xCE4A, 0x872C, 0xCE4B, 0x872D, 0xCE4C, 0x872E, 0xF2E2, 0x872F, 0xCE4D, 0x8730, 0xCE4E, 0x8731, 0xF2E7, 0x8732, 0xCE4F,
+ 0x8733, 0xCE50, 0x8734, 0xF2E6, 0x8735, 0xCE51, 0x8736, 0xCE52, 0x8737, 0xF2E9, 0x8738, 0xCE53, 0x8739, 0xCE54, 0x873A, 0xCE55,
+ 0x873B, 0xF2DF, 0x873C, 0xCE56, 0x873D, 0xCE57, 0x873E, 0xF2E4, 0x873F, 0xF2EA, 0x8740, 0xCE58, 0x8741, 0xCE59, 0x8742, 0xCE5A,
+ 0x8743, 0xCE5B, 0x8744, 0xCE5C, 0x8745, 0xCE5D, 0x8746, 0xCE5E, 0x8747, 0xD3AC, 0x8748, 0xF2E5, 0x8749, 0xB2F5, 0x874A, 0xCE5F,
+ 0x874B, 0xCE60, 0x874C, 0xF2F2, 0x874D, 0xCE61, 0x874E, 0xD0AB, 0x874F, 0xCE62, 0x8750, 0xCE63, 0x8751, 0xCE64, 0x8752, 0xCE65,
+ 0x8753, 0xF2F5, 0x8754, 0xCE66, 0x8755, 0xCE67, 0x8756, 0xCE68, 0x8757, 0xBBC8, 0x8758, 0xCE69, 0x8759, 0xF2F9, 0x875A, 0xCE6A,
+ 0x875B, 0xCE6B, 0x875C, 0xCE6C, 0x875D, 0xCE6D, 0x875E, 0xCE6E, 0x875F, 0xCE6F, 0x8760, 0xF2F0, 0x8761, 0xCE70, 0x8762, 0xCE71,
+ 0x8763, 0xF2F6, 0x8764, 0xF2F8, 0x8765, 0xF2FA, 0x8766, 0xCE72, 0x8767, 0xCE73, 0x8768, 0xCE74, 0x8769, 0xCE75, 0x876A, 0xCE76,
+ 0x876B, 0xCE77, 0x876C, 0xCE78, 0x876D, 0xCE79, 0x876E, 0xF2F3, 0x876F, 0xCE7A, 0x8770, 0xF2F1, 0x8771, 0xCE7B, 0x8772, 0xCE7C,
+ 0x8773, 0xCE7D, 0x8774, 0xBAFB, 0x8775, 0xCE7E, 0x8776, 0xB5FB, 0x8777, 0xCE80, 0x8778, 0xCE81, 0x8779, 0xCE82, 0x877A, 0xCE83,
+ 0x877B, 0xF2EF, 0x877C, 0xF2F7, 0x877D, 0xF2ED, 0x877E, 0xF2EE, 0x877F, 0xCE84, 0x8780, 0xCE85, 0x8781, 0xCE86, 0x8782, 0xF2EB,
+ 0x8783, 0xF3A6, 0x8784, 0xCE87, 0x8785, 0xF3A3, 0x8786, 0xCE88, 0x8787, 0xCE89, 0x8788, 0xF3A2, 0x8789, 0xCE8A, 0x878A, 0xCE8B,
+ 0x878B, 0xF2F4, 0x878C, 0xCE8C, 0x878D, 0xC8DA, 0x878E, 0xCE8D, 0x878F, 0xCE8E, 0x8790, 0xCE8F, 0x8791, 0xCE90, 0x8792, 0xCE91,
+ 0x8793, 0xF2FB, 0x8794, 0xCE92, 0x8795, 0xCE93, 0x8796, 0xCE94, 0x8797, 0xF3A5, 0x8798, 0xCE95, 0x8799, 0xCE96, 0x879A, 0xCE97,
+ 0x879B, 0xCE98, 0x879C, 0xCE99, 0x879D, 0xCE9A, 0x879E, 0xCE9B, 0x879F, 0xC3F8, 0x87A0, 0xCE9C, 0x87A1, 0xCE9D, 0x87A2, 0xCE9E,
+ 0x87A3, 0xCE9F, 0x87A4, 0xCEA0, 0x87A5, 0xCF40, 0x87A6, 0xCF41, 0x87A7, 0xCF42, 0x87A8, 0xF2FD, 0x87A9, 0xCF43, 0x87AA, 0xCF44,
+ 0x87AB, 0xF3A7, 0x87AC, 0xF3A9, 0x87AD, 0xF3A4, 0x87AE, 0xCF45, 0x87AF, 0xF2FC, 0x87B0, 0xCF46, 0x87B1, 0xCF47, 0x87B2, 0xCF48,
+ 0x87B3, 0xF3AB, 0x87B4, 0xCF49, 0x87B5, 0xF3AA, 0x87B6, 0xCF4A, 0x87B7, 0xCF4B, 0x87B8, 0xCF4C, 0x87B9, 0xCF4D, 0x87BA, 0xC2DD,
+ 0x87BB, 0xCF4E, 0x87BC, 0xCF4F, 0x87BD, 0xF3AE, 0x87BE, 0xCF50, 0x87BF, 0xCF51, 0x87C0, 0xF3B0, 0x87C1, 0xCF52, 0x87C2, 0xCF53,
+ 0x87C3, 0xCF54, 0x87C4, 0xCF55, 0x87C5, 0xCF56, 0x87C6, 0xF3A1, 0x87C7, 0xCF57, 0x87C8, 0xCF58, 0x87C9, 0xCF59, 0x87CA, 0xF3B1,
+ 0x87CB, 0xF3AC, 0x87CC, 0xCF5A, 0x87CD, 0xCF5B, 0x87CE, 0xCF5C, 0x87CF, 0xCF5D, 0x87D0, 0xCF5E, 0x87D1, 0xF3AF, 0x87D2, 0xF2FE,
+ 0x87D3, 0xF3AD, 0x87D4, 0xCF5F, 0x87D5, 0xCF60, 0x87D6, 0xCF61, 0x87D7, 0xCF62, 0x87D8, 0xCF63, 0x87D9, 0xCF64, 0x87DA, 0xCF65,
+ 0x87DB, 0xF3B2, 0x87DC, 0xCF66, 0x87DD, 0xCF67, 0x87DE, 0xCF68, 0x87DF, 0xCF69, 0x87E0, 0xF3B4, 0x87E1, 0xCF6A, 0x87E2, 0xCF6B,
+ 0x87E3, 0xCF6C, 0x87E4, 0xCF6D, 0x87E5, 0xF3A8, 0x87E6, 0xCF6E, 0x87E7, 0xCF6F, 0x87E8, 0xCF70, 0x87E9, 0xCF71, 0x87EA, 0xF3B3,
+ 0x87EB, 0xCF72, 0x87EC, 0xCF73, 0x87ED, 0xCF74, 0x87EE, 0xF3B5, 0x87EF, 0xCF75, 0x87F0, 0xCF76, 0x87F1, 0xCF77, 0x87F2, 0xCF78,
+ 0x87F3, 0xCF79, 0x87F4, 0xCF7A, 0x87F5, 0xCF7B, 0x87F6, 0xCF7C, 0x87F7, 0xCF7D, 0x87F8, 0xCF7E, 0x87F9, 0xD0B7, 0x87FA, 0xCF80,
+ 0x87FB, 0xCF81, 0x87FC, 0xCF82, 0x87FD, 0xCF83, 0x87FE, 0xF3B8, 0x87FF, 0xCF84, 0x8800, 0xCF85, 0x8801, 0xCF86, 0x8802, 0xCF87,
+ 0x8803, 0xD9F9, 0x8804, 0xCF88, 0x8805, 0xCF89, 0x8806, 0xCF8A, 0x8807, 0xCF8B, 0x8808, 0xCF8C, 0x8809, 0xCF8D, 0x880A, 0xF3B9,
+ 0x880B, 0xCF8E, 0x880C, 0xCF8F, 0x880D, 0xCF90, 0x880E, 0xCF91, 0x880F, 0xCF92, 0x8810, 0xCF93, 0x8811, 0xCF94, 0x8812, 0xCF95,
+ 0x8813, 0xF3B7, 0x8814, 0xCF96, 0x8815, 0xC8E4, 0x8816, 0xF3B6, 0x8817, 0xCF97, 0x8818, 0xCF98, 0x8819, 0xCF99, 0x881A, 0xCF9A,
+ 0x881B, 0xF3BA, 0x881C, 0xCF9B, 0x881D, 0xCF9C, 0x881E, 0xCF9D, 0x881F, 0xCF9E, 0x8820, 0xCF9F, 0x8821, 0xF3BB, 0x8822, 0xB4C0,
+ 0x8823, 0xCFA0, 0x8824, 0xD040, 0x8825, 0xD041, 0x8826, 0xD042, 0x8827, 0xD043, 0x8828, 0xD044, 0x8829, 0xD045, 0x882A, 0xD046,
+ 0x882B, 0xD047, 0x882C, 0xD048, 0x882D, 0xD049, 0x882E, 0xD04A, 0x882F, 0xD04B, 0x8830, 0xD04C, 0x8831, 0xD04D, 0x8832, 0xEEC3,
+ 0x8833, 0xD04E, 0x8834, 0xD04F, 0x8835, 0xD050, 0x8836, 0xD051, 0x8837, 0xD052, 0x8838, 0xD053, 0x8839, 0xF3BC, 0x883A, 0xD054,
+ 0x883B, 0xD055, 0x883C, 0xF3BD, 0x883D, 0xD056, 0x883E, 0xD057, 0x883F, 0xD058, 0x8840, 0xD1AA, 0x8841, 0xD059, 0x8842, 0xD05A,
+ 0x8843, 0xD05B, 0x8844, 0xF4AC, 0x8845, 0xD0C6, 0x8846, 0xD05C, 0x8847, 0xD05D, 0x8848, 0xD05E, 0x8849, 0xD05F, 0x884A, 0xD060,
+ 0x884B, 0xD061, 0x884C, 0xD0D0, 0x884D, 0xD1DC, 0x884E, 0xD062, 0x884F, 0xD063, 0x8850, 0xD064, 0x8851, 0xD065, 0x8852, 0xD066,
+ 0x8853, 0xD067, 0x8854, 0xCFCE, 0x8855, 0xD068, 0x8856, 0xD069, 0x8857, 0xBDD6, 0x8858, 0xD06A, 0x8859, 0xD1C3, 0x885A, 0xD06B,
+ 0x885B, 0xD06C, 0x885C, 0xD06D, 0x885D, 0xD06E, 0x885E, 0xD06F, 0x885F, 0xD070, 0x8860, 0xD071, 0x8861, 0xBAE2, 0x8862, 0xE1E9,
+ 0x8863, 0xD2C2, 0x8864, 0xF1C2, 0x8865, 0xB2B9, 0x8866, 0xD072, 0x8867, 0xD073, 0x8868, 0xB1ED, 0x8869, 0xF1C3, 0x886A, 0xD074,
+ 0x886B, 0xC9C0, 0x886C, 0xB3C4, 0x886D, 0xD075, 0x886E, 0xD9F2, 0x886F, 0xD076, 0x8870, 0xCBA5, 0x8871, 0xD077, 0x8872, 0xF1C4,
+ 0x8873, 0xD078, 0x8874, 0xD079, 0x8875, 0xD07A, 0x8876, 0xD07B, 0x8877, 0xD6D4, 0x8878, 0xD07C, 0x8879, 0xD07D, 0x887A, 0xD07E,
+ 0x887B, 0xD080, 0x887C, 0xD081, 0x887D, 0xF1C5, 0x887E, 0xF4C0, 0x887F, 0xF1C6, 0x8880, 0xD082, 0x8881, 0xD4AC, 0x8882, 0xF1C7,
+ 0x8883, 0xD083, 0x8884, 0xB0C0, 0x8885, 0xF4C1, 0x8886, 0xD084, 0x8887, 0xD085, 0x8888, 0xF4C2, 0x8889, 0xD086, 0x888A, 0xD087,
+ 0x888B, 0xB4FC, 0x888C, 0xD088, 0x888D, 0xC5DB, 0x888E, 0xD089, 0x888F, 0xD08A, 0x8890, 0xD08B, 0x8891, 0xD08C, 0x8892, 0xCCBB,
+ 0x8893, 0xD08D, 0x8894, 0xD08E, 0x8895, 0xD08F, 0x8896, 0xD0E4, 0x8897, 0xD090, 0x8898, 0xD091, 0x8899, 0xD092, 0x889A, 0xD093,
+ 0x889B, 0xD094, 0x889C, 0xCDE0, 0x889D, 0xD095, 0x889E, 0xD096, 0x889F, 0xD097, 0x88A0, 0xD098, 0x88A1, 0xD099, 0x88A2, 0xF1C8,
+ 0x88A3, 0xD09A, 0x88A4, 0xD9F3, 0x88A5, 0xD09B, 0x88A6, 0xD09C, 0x88A7, 0xD09D, 0x88A8, 0xD09E, 0x88A9, 0xD09F, 0x88AA, 0xD0A0,
+ 0x88AB, 0xB1BB, 0x88AC, 0xD140, 0x88AD, 0xCFAE, 0x88AE, 0xD141, 0x88AF, 0xD142, 0x88B0, 0xD143, 0x88B1, 0xB8A4, 0x88B2, 0xD144,
+ 0x88B3, 0xD145, 0x88B4, 0xD146, 0x88B5, 0xD147, 0x88B6, 0xD148, 0x88B7, 0xF1CA, 0x88B8, 0xD149, 0x88B9, 0xD14A, 0x88BA, 0xD14B,
+ 0x88BB, 0xD14C, 0x88BC, 0xF1CB, 0x88BD, 0xD14D, 0x88BE, 0xD14E, 0x88BF, 0xD14F, 0x88C0, 0xD150, 0x88C1, 0xB2C3, 0x88C2, 0xC1D1,
+ 0x88C3, 0xD151, 0x88C4, 0xD152, 0x88C5, 0xD7B0, 0x88C6, 0xF1C9, 0x88C7, 0xD153, 0x88C8, 0xD154, 0x88C9, 0xF1CC, 0x88CA, 0xD155,
+ 0x88CB, 0xD156, 0x88CC, 0xD157, 0x88CD, 0xD158, 0x88CE, 0xF1CE, 0x88CF, 0xD159, 0x88D0, 0xD15A, 0x88D1, 0xD15B, 0x88D2, 0xD9F6,
+ 0x88D3, 0xD15C, 0x88D4, 0xD2E1, 0x88D5, 0xD4A3, 0x88D6, 0xD15D, 0x88D7, 0xD15E, 0x88D8, 0xF4C3, 0x88D9, 0xC8B9, 0x88DA, 0xD15F,
+ 0x88DB, 0xD160, 0x88DC, 0xD161, 0x88DD, 0xD162, 0x88DE, 0xD163, 0x88DF, 0xF4C4, 0x88E0, 0xD164, 0x88E1, 0xD165, 0x88E2, 0xF1CD,
+ 0x88E3, 0xF1CF, 0x88E4, 0xBFE3, 0x88E5, 0xF1D0, 0x88E6, 0xD166, 0x88E7, 0xD167, 0x88E8, 0xF1D4, 0x88E9, 0xD168, 0x88EA, 0xD169,
+ 0x88EB, 0xD16A, 0x88EC, 0xD16B, 0x88ED, 0xD16C, 0x88EE, 0xD16D, 0x88EF, 0xD16E, 0x88F0, 0xF1D6, 0x88F1, 0xF1D1, 0x88F2, 0xD16F,
+ 0x88F3, 0xC9D1, 0x88F4, 0xC5E1, 0x88F5, 0xD170, 0x88F6, 0xD171, 0x88F7, 0xD172, 0x88F8, 0xC2E3, 0x88F9, 0xB9FC, 0x88FA, 0xD173,
+ 0x88FB, 0xD174, 0x88FC, 0xF1D3, 0x88FD, 0xD175, 0x88FE, 0xF1D5, 0x88FF, 0xD176, 0x8900, 0xD177, 0x8901, 0xD178, 0x8902, 0xB9D3,
+ 0x8903, 0xD179, 0x8904, 0xD17A, 0x8905, 0xD17B, 0x8906, 0xD17C, 0x8907, 0xD17D, 0x8908, 0xD17E, 0x8909, 0xD180, 0x890A, 0xF1DB,
+ 0x890B, 0xD181, 0x890C, 0xD182, 0x890D, 0xD183, 0x890E, 0xD184, 0x890F, 0xD185, 0x8910, 0xBAD6, 0x8911, 0xD186, 0x8912, 0xB0FD,
+ 0x8913, 0xF1D9, 0x8914, 0xD187, 0x8915, 0xD188, 0x8916, 0xD189, 0x8917, 0xD18A, 0x8918, 0xD18B, 0x8919, 0xF1D8, 0x891A, 0xF1D2,
+ 0x891B, 0xF1DA, 0x891C, 0xD18C, 0x891D, 0xD18D, 0x891E, 0xD18E, 0x891F, 0xD18F, 0x8920, 0xD190, 0x8921, 0xF1D7, 0x8922, 0xD191,
+ 0x8923, 0xD192, 0x8924, 0xD193, 0x8925, 0xC8EC, 0x8926, 0xD194, 0x8927, 0xD195, 0x8928, 0xD196, 0x8929, 0xD197, 0x892A, 0xCDCA,
+ 0x892B, 0xF1DD, 0x892C, 0xD198, 0x892D, 0xD199, 0x892E, 0xD19A, 0x892F, 0xD19B, 0x8930, 0xE5BD, 0x8931, 0xD19C, 0x8932, 0xD19D,
+ 0x8933, 0xD19E, 0x8934, 0xF1DC, 0x8935, 0xD19F, 0x8936, 0xF1DE, 0x8937, 0xD1A0, 0x8938, 0xD240, 0x8939, 0xD241, 0x893A, 0xD242,
+ 0x893B, 0xD243, 0x893C, 0xD244, 0x893D, 0xD245, 0x893E, 0xD246, 0x893F, 0xD247, 0x8940, 0xD248, 0x8941, 0xF1DF, 0x8942, 0xD249,
+ 0x8943, 0xD24A, 0x8944, 0xCFE5, 0x8945, 0xD24B, 0x8946, 0xD24C, 0x8947, 0xD24D, 0x8948, 0xD24E, 0x8949, 0xD24F, 0x894A, 0xD250,
+ 0x894B, 0xD251, 0x894C, 0xD252, 0x894D, 0xD253, 0x894E, 0xD254, 0x894F, 0xD255, 0x8950, 0xD256, 0x8951, 0xD257, 0x8952, 0xD258,
+ 0x8953, 0xD259, 0x8954, 0xD25A, 0x8955, 0xD25B, 0x8956, 0xD25C, 0x8957, 0xD25D, 0x8958, 0xD25E, 0x8959, 0xD25F, 0x895A, 0xD260,
+ 0x895B, 0xD261, 0x895C, 0xD262, 0x895D, 0xD263, 0x895E, 0xF4C5, 0x895F, 0xBDF3, 0x8960, 0xD264, 0x8961, 0xD265, 0x8962, 0xD266,
+ 0x8963, 0xD267, 0x8964, 0xD268, 0x8965, 0xD269, 0x8966, 0xF1E0, 0x8967, 0xD26A, 0x8968, 0xD26B, 0x8969, 0xD26C, 0x896A, 0xD26D,
+ 0x896B, 0xD26E, 0x896C, 0xD26F, 0x896D, 0xD270, 0x896E, 0xD271, 0x896F, 0xD272, 0x8970, 0xD273, 0x8971, 0xD274, 0x8972, 0xD275,
+ 0x8973, 0xD276, 0x8974, 0xD277, 0x8975, 0xD278, 0x8976, 0xD279, 0x8977, 0xD27A, 0x8978, 0xD27B, 0x8979, 0xD27C, 0x897A, 0xD27D,
+ 0x897B, 0xF1E1, 0x897C, 0xD27E, 0x897D, 0xD280, 0x897E, 0xD281, 0x897F, 0xCEF7, 0x8980, 0xD282, 0x8981, 0xD2AA, 0x8982, 0xD283,
+ 0x8983, 0xF1FB, 0x8984, 0xD284, 0x8985, 0xD285, 0x8986, 0xB8B2, 0x8987, 0xD286, 0x8988, 0xD287, 0x8989, 0xD288, 0x898A, 0xD289,
+ 0x898B, 0xD28A, 0x898C, 0xD28B, 0x898D, 0xD28C, 0x898E, 0xD28D, 0x898F, 0xD28E, 0x8990, 0xD28F, 0x8991, 0xD290, 0x8992, 0xD291,
+ 0x8993, 0xD292, 0x8994, 0xD293, 0x8995, 0xD294, 0x8996, 0xD295, 0x8997, 0xD296, 0x8998, 0xD297, 0x8999, 0xD298, 0x899A, 0xD299,
+ 0x899B, 0xD29A, 0x899C, 0xD29B, 0x899D, 0xD29C, 0x899E, 0xD29D, 0x899F, 0xD29E, 0x89A0, 0xD29F, 0x89A1, 0xD2A0, 0x89A2, 0xD340,
+ 0x89A3, 0xD341, 0x89A4, 0xD342, 0x89A5, 0xD343, 0x89A6, 0xD344, 0x89A7, 0xD345, 0x89A8, 0xD346, 0x89A9, 0xD347, 0x89AA, 0xD348,
+ 0x89AB, 0xD349, 0x89AC, 0xD34A, 0x89AD, 0xD34B, 0x89AE, 0xD34C, 0x89AF, 0xD34D, 0x89B0, 0xD34E, 0x89B1, 0xD34F, 0x89B2, 0xD350,
+ 0x89B3, 0xD351, 0x89B4, 0xD352, 0x89B5, 0xD353, 0x89B6, 0xD354, 0x89B7, 0xD355, 0x89B8, 0xD356, 0x89B9, 0xD357, 0x89BA, 0xD358,
+ 0x89BB, 0xD359, 0x89BC, 0xD35A, 0x89BD, 0xD35B, 0x89BE, 0xD35C, 0x89BF, 0xD35D, 0x89C0, 0xD35E, 0x89C1, 0xBCFB, 0x89C2, 0xB9DB,
+ 0x89C3, 0xD35F, 0x89C4, 0xB9E6, 0x89C5, 0xC3D9, 0x89C6, 0xCAD3, 0x89C7, 0xEAE8, 0x89C8, 0xC0C0, 0x89C9, 0xBEF5, 0x89CA, 0xEAE9,
+ 0x89CB, 0xEAEA, 0x89CC, 0xEAEB, 0x89CD, 0xD360, 0x89CE, 0xEAEC, 0x89CF, 0xEAED, 0x89D0, 0xEAEE, 0x89D1, 0xEAEF, 0x89D2, 0xBDC7,
+ 0x89D3, 0xD361, 0x89D4, 0xD362, 0x89D5, 0xD363, 0x89D6, 0xF5FB, 0x89D7, 0xD364, 0x89D8, 0xD365, 0x89D9, 0xD366, 0x89DA, 0xF5FD,
+ 0x89DB, 0xD367, 0x89DC, 0xF5FE, 0x89DD, 0xD368, 0x89DE, 0xF5FC, 0x89DF, 0xD369, 0x89E0, 0xD36A, 0x89E1, 0xD36B, 0x89E2, 0xD36C,
+ 0x89E3, 0xBDE2, 0x89E4, 0xD36D, 0x89E5, 0xF6A1, 0x89E6, 0xB4A5, 0x89E7, 0xD36E, 0x89E8, 0xD36F, 0x89E9, 0xD370, 0x89EA, 0xD371,
+ 0x89EB, 0xF6A2, 0x89EC, 0xD372, 0x89ED, 0xD373, 0x89EE, 0xD374, 0x89EF, 0xF6A3, 0x89F0, 0xD375, 0x89F1, 0xD376, 0x89F2, 0xD377,
+ 0x89F3, 0xECB2, 0x89F4, 0xD378, 0x89F5, 0xD379, 0x89F6, 0xD37A, 0x89F7, 0xD37B, 0x89F8, 0xD37C, 0x89F9, 0xD37D, 0x89FA, 0xD37E,
+ 0x89FB, 0xD380, 0x89FC, 0xD381, 0x89FD, 0xD382, 0x89FE, 0xD383, 0x89FF, 0xD384, 0x8A00, 0xD1D4, 0x8A01, 0xD385, 0x8A02, 0xD386,
+ 0x8A03, 0xD387, 0x8A04, 0xD388, 0x8A05, 0xD389, 0x8A06, 0xD38A, 0x8A07, 0xD9EA, 0x8A08, 0xD38B, 0x8A09, 0xD38C, 0x8A0A, 0xD38D,
+ 0x8A0B, 0xD38E, 0x8A0C, 0xD38F, 0x8A0D, 0xD390, 0x8A0E, 0xD391, 0x8A0F, 0xD392, 0x8A10, 0xD393, 0x8A11, 0xD394, 0x8A12, 0xD395,
+ 0x8A13, 0xD396, 0x8A14, 0xD397, 0x8A15, 0xD398, 0x8A16, 0xD399, 0x8A17, 0xD39A, 0x8A18, 0xD39B, 0x8A19, 0xD39C, 0x8A1A, 0xD39D,
+ 0x8A1B, 0xD39E, 0x8A1C, 0xD39F, 0x8A1D, 0xD3A0, 0x8A1E, 0xD440, 0x8A1F, 0xD441, 0x8A20, 0xD442, 0x8A21, 0xD443, 0x8A22, 0xD444,
+ 0x8A23, 0xD445, 0x8A24, 0xD446, 0x8A25, 0xD447, 0x8A26, 0xD448, 0x8A27, 0xD449, 0x8A28, 0xD44A, 0x8A29, 0xD44B, 0x8A2A, 0xD44C,
+ 0x8A2B, 0xD44D, 0x8A2C, 0xD44E, 0x8A2D, 0xD44F, 0x8A2E, 0xD450, 0x8A2F, 0xD451, 0x8A30, 0xD452, 0x8A31, 0xD453, 0x8A32, 0xD454,
+ 0x8A33, 0xD455, 0x8A34, 0xD456, 0x8A35, 0xD457, 0x8A36, 0xD458, 0x8A37, 0xD459, 0x8A38, 0xD45A, 0x8A39, 0xD45B, 0x8A3A, 0xD45C,
+ 0x8A3B, 0xD45D, 0x8A3C, 0xD45E, 0x8A3D, 0xD45F, 0x8A3E, 0xF6A4, 0x8A3F, 0xD460, 0x8A40, 0xD461, 0x8A41, 0xD462, 0x8A42, 0xD463,
+ 0x8A43, 0xD464, 0x8A44, 0xD465, 0x8A45, 0xD466, 0x8A46, 0xD467, 0x8A47, 0xD468, 0x8A48, 0xEEBA, 0x8A49, 0xD469, 0x8A4A, 0xD46A,
+ 0x8A4B, 0xD46B, 0x8A4C, 0xD46C, 0x8A4D, 0xD46D, 0x8A4E, 0xD46E, 0x8A4F, 0xD46F, 0x8A50, 0xD470, 0x8A51, 0xD471, 0x8A52, 0xD472,
+ 0x8A53, 0xD473, 0x8A54, 0xD474, 0x8A55, 0xD475, 0x8A56, 0xD476, 0x8A57, 0xD477, 0x8A58, 0xD478, 0x8A59, 0xD479, 0x8A5A, 0xD47A,
+ 0x8A5B, 0xD47B, 0x8A5C, 0xD47C, 0x8A5D, 0xD47D, 0x8A5E, 0xD47E, 0x8A5F, 0xD480, 0x8A60, 0xD481, 0x8A61, 0xD482, 0x8A62, 0xD483,
+ 0x8A63, 0xD484, 0x8A64, 0xD485, 0x8A65, 0xD486, 0x8A66, 0xD487, 0x8A67, 0xD488, 0x8A68, 0xD489, 0x8A69, 0xD48A, 0x8A6A, 0xD48B,
+ 0x8A6B, 0xD48C, 0x8A6C, 0xD48D, 0x8A6D, 0xD48E, 0x8A6E, 0xD48F, 0x8A6F, 0xD490, 0x8A70, 0xD491, 0x8A71, 0xD492, 0x8A72, 0xD493,
+ 0x8A73, 0xD494, 0x8A74, 0xD495, 0x8A75, 0xD496, 0x8A76, 0xD497, 0x8A77, 0xD498, 0x8A78, 0xD499, 0x8A79, 0xD5B2, 0x8A7A, 0xD49A,
+ 0x8A7B, 0xD49B, 0x8A7C, 0xD49C, 0x8A7D, 0xD49D, 0x8A7E, 0xD49E, 0x8A7F, 0xD49F, 0x8A80, 0xD4A0, 0x8A81, 0xD540, 0x8A82, 0xD541,
+ 0x8A83, 0xD542, 0x8A84, 0xD543, 0x8A85, 0xD544, 0x8A86, 0xD545, 0x8A87, 0xD546, 0x8A88, 0xD547, 0x8A89, 0xD3FE, 0x8A8A, 0xCCDC,
+ 0x8A8B, 0xD548, 0x8A8C, 0xD549, 0x8A8D, 0xD54A, 0x8A8E, 0xD54B, 0x8A8F, 0xD54C, 0x8A90, 0xD54D, 0x8A91, 0xD54E, 0x8A92, 0xD54F,
+ 0x8A93, 0xCAC4, 0x8A94, 0xD550, 0x8A95, 0xD551, 0x8A96, 0xD552, 0x8A97, 0xD553, 0x8A98, 0xD554, 0x8A99, 0xD555, 0x8A9A, 0xD556,
+ 0x8A9B, 0xD557, 0x8A9C, 0xD558, 0x8A9D, 0xD559, 0x8A9E, 0xD55A, 0x8A9F, 0xD55B, 0x8AA0, 0xD55C, 0x8AA1, 0xD55D, 0x8AA2, 0xD55E,
+ 0x8AA3, 0xD55F, 0x8AA4, 0xD560, 0x8AA5, 0xD561, 0x8AA6, 0xD562, 0x8AA7, 0xD563, 0x8AA8, 0xD564, 0x8AA9, 0xD565, 0x8AAA, 0xD566,
+ 0x8AAB, 0xD567, 0x8AAC, 0xD568, 0x8AAD, 0xD569, 0x8AAE, 0xD56A, 0x8AAF, 0xD56B, 0x8AB0, 0xD56C, 0x8AB1, 0xD56D, 0x8AB2, 0xD56E,
+ 0x8AB3, 0xD56F, 0x8AB4, 0xD570, 0x8AB5, 0xD571, 0x8AB6, 0xD572, 0x8AB7, 0xD573, 0x8AB8, 0xD574, 0x8AB9, 0xD575, 0x8ABA, 0xD576,
+ 0x8ABB, 0xD577, 0x8ABC, 0xD578, 0x8ABD, 0xD579, 0x8ABE, 0xD57A, 0x8ABF, 0xD57B, 0x8AC0, 0xD57C, 0x8AC1, 0xD57D, 0x8AC2, 0xD57E,
+ 0x8AC3, 0xD580, 0x8AC4, 0xD581, 0x8AC5, 0xD582, 0x8AC6, 0xD583, 0x8AC7, 0xD584, 0x8AC8, 0xD585, 0x8AC9, 0xD586, 0x8ACA, 0xD587,
+ 0x8ACB, 0xD588, 0x8ACC, 0xD589, 0x8ACD, 0xD58A, 0x8ACE, 0xD58B, 0x8ACF, 0xD58C, 0x8AD0, 0xD58D, 0x8AD1, 0xD58E, 0x8AD2, 0xD58F,
+ 0x8AD3, 0xD590, 0x8AD4, 0xD591, 0x8AD5, 0xD592, 0x8AD6, 0xD593, 0x8AD7, 0xD594, 0x8AD8, 0xD595, 0x8AD9, 0xD596, 0x8ADA, 0xD597,
+ 0x8ADB, 0xD598, 0x8ADC, 0xD599, 0x8ADD, 0xD59A, 0x8ADE, 0xD59B, 0x8ADF, 0xD59C, 0x8AE0, 0xD59D, 0x8AE1, 0xD59E, 0x8AE2, 0xD59F,
+ 0x8AE3, 0xD5A0, 0x8AE4, 0xD640, 0x8AE5, 0xD641, 0x8AE6, 0xD642, 0x8AE7, 0xD643, 0x8AE8, 0xD644, 0x8AE9, 0xD645, 0x8AEA, 0xD646,
+ 0x8AEB, 0xD647, 0x8AEC, 0xD648, 0x8AED, 0xD649, 0x8AEE, 0xD64A, 0x8AEF, 0xD64B, 0x8AF0, 0xD64C, 0x8AF1, 0xD64D, 0x8AF2, 0xD64E,
+ 0x8AF3, 0xD64F, 0x8AF4, 0xD650, 0x8AF5, 0xD651, 0x8AF6, 0xD652, 0x8AF7, 0xD653, 0x8AF8, 0xD654, 0x8AF9, 0xD655, 0x8AFA, 0xD656,
+ 0x8AFB, 0xD657, 0x8AFC, 0xD658, 0x8AFD, 0xD659, 0x8AFE, 0xD65A, 0x8AFF, 0xD65B, 0x8B00, 0xD65C, 0x8B01, 0xD65D, 0x8B02, 0xD65E,
+ 0x8B03, 0xD65F, 0x8B04, 0xD660, 0x8B05, 0xD661, 0x8B06, 0xD662, 0x8B07, 0xE5C0, 0x8B08, 0xD663, 0x8B09, 0xD664, 0x8B0A, 0xD665,
+ 0x8B0B, 0xD666, 0x8B0C, 0xD667, 0x8B0D, 0xD668, 0x8B0E, 0xD669, 0x8B0F, 0xD66A, 0x8B10, 0xD66B, 0x8B11, 0xD66C, 0x8B12, 0xD66D,
+ 0x8B13, 0xD66E, 0x8B14, 0xD66F, 0x8B15, 0xD670, 0x8B16, 0xD671, 0x8B17, 0xD672, 0x8B18, 0xD673, 0x8B19, 0xD674, 0x8B1A, 0xD675,
+ 0x8B1B, 0xD676, 0x8B1C, 0xD677, 0x8B1D, 0xD678, 0x8B1E, 0xD679, 0x8B1F, 0xD67A, 0x8B20, 0xD67B, 0x8B21, 0xD67C, 0x8B22, 0xD67D,
+ 0x8B23, 0xD67E, 0x8B24, 0xD680, 0x8B25, 0xD681, 0x8B26, 0xF6A5, 0x8B27, 0xD682, 0x8B28, 0xD683, 0x8B29, 0xD684, 0x8B2A, 0xD685,
+ 0x8B2B, 0xD686, 0x8B2C, 0xD687, 0x8B2D, 0xD688, 0x8B2E, 0xD689, 0x8B2F, 0xD68A, 0x8B30, 0xD68B, 0x8B31, 0xD68C, 0x8B32, 0xD68D,
+ 0x8B33, 0xD68E, 0x8B34, 0xD68F, 0x8B35, 0xD690, 0x8B36, 0xD691, 0x8B37, 0xD692, 0x8B38, 0xD693, 0x8B39, 0xD694, 0x8B3A, 0xD695,
+ 0x8B3B, 0xD696, 0x8B3C, 0xD697, 0x8B3D, 0xD698, 0x8B3E, 0xD699, 0x8B3F, 0xD69A, 0x8B40, 0xD69B, 0x8B41, 0xD69C, 0x8B42, 0xD69D,
+ 0x8B43, 0xD69E, 0x8B44, 0xD69F, 0x8B45, 0xD6A0, 0x8B46, 0xD740, 0x8B47, 0xD741, 0x8B48, 0xD742, 0x8B49, 0xD743, 0x8B4A, 0xD744,
+ 0x8B4B, 0xD745, 0x8B4C, 0xD746, 0x8B4D, 0xD747, 0x8B4E, 0xD748, 0x8B4F, 0xD749, 0x8B50, 0xD74A, 0x8B51, 0xD74B, 0x8B52, 0xD74C,
+ 0x8B53, 0xD74D, 0x8B54, 0xD74E, 0x8B55, 0xD74F, 0x8B56, 0xD750, 0x8B57, 0xD751, 0x8B58, 0xD752, 0x8B59, 0xD753, 0x8B5A, 0xD754,
+ 0x8B5B, 0xD755, 0x8B5C, 0xD756, 0x8B5D, 0xD757, 0x8B5E, 0xD758, 0x8B5F, 0xD759, 0x8B60, 0xD75A, 0x8B61, 0xD75B, 0x8B62, 0xD75C,
+ 0x8B63, 0xD75D, 0x8B64, 0xD75E, 0x8B65, 0xD75F, 0x8B66, 0xBEAF, 0x8B67, 0xD760, 0x8B68, 0xD761, 0x8B69, 0xD762, 0x8B6A, 0xD763,
+ 0x8B6B, 0xD764, 0x8B6C, 0xC6A9, 0x8B6D, 0xD765, 0x8B6E, 0xD766, 0x8B6F, 0xD767, 0x8B70, 0xD768, 0x8B71, 0xD769, 0x8B72, 0xD76A,
+ 0x8B73, 0xD76B, 0x8B74, 0xD76C, 0x8B75, 0xD76D, 0x8B76, 0xD76E, 0x8B77, 0xD76F, 0x8B78, 0xD770, 0x8B79, 0xD771, 0x8B7A, 0xD772,
+ 0x8B7B, 0xD773, 0x8B7C, 0xD774, 0x8B7D, 0xD775, 0x8B7E, 0xD776, 0x8B7F, 0xD777, 0x8B80, 0xD778, 0x8B81, 0xD779, 0x8B82, 0xD77A,
+ 0x8B83, 0xD77B, 0x8B84, 0xD77C, 0x8B85, 0xD77D, 0x8B86, 0xD77E, 0x8B87, 0xD780, 0x8B88, 0xD781, 0x8B89, 0xD782, 0x8B8A, 0xD783,
+ 0x8B8B, 0xD784, 0x8B8C, 0xD785, 0x8B8D, 0xD786, 0x8B8E, 0xD787, 0x8B8F, 0xD788, 0x8B90, 0xD789, 0x8B91, 0xD78A, 0x8B92, 0xD78B,
+ 0x8B93, 0xD78C, 0x8B94, 0xD78D, 0x8B95, 0xD78E, 0x8B96, 0xD78F, 0x8B97, 0xD790, 0x8B98, 0xD791, 0x8B99, 0xD792, 0x8B9A, 0xD793,
+ 0x8B9B, 0xD794, 0x8B9C, 0xD795, 0x8B9D, 0xD796, 0x8B9E, 0xD797, 0x8B9F, 0xD798, 0x8BA0, 0xDAA5, 0x8BA1, 0xBCC6, 0x8BA2, 0xB6A9,
+ 0x8BA3, 0xB8BC, 0x8BA4, 0xC8CF, 0x8BA5, 0xBCA5, 0x8BA6, 0xDAA6, 0x8BA7, 0xDAA7, 0x8BA8, 0xCCD6, 0x8BA9, 0xC8C3, 0x8BAA, 0xDAA8,
+ 0x8BAB, 0xC6FD, 0x8BAC, 0xD799, 0x8BAD, 0xD1B5, 0x8BAE, 0xD2E9, 0x8BAF, 0xD1B6, 0x8BB0, 0xBCC7, 0x8BB1, 0xD79A, 0x8BB2, 0xBDB2,
+ 0x8BB3, 0xBBE4, 0x8BB4, 0xDAA9, 0x8BB5, 0xDAAA, 0x8BB6, 0xD1C8, 0x8BB7, 0xDAAB, 0x8BB8, 0xD0ED, 0x8BB9, 0xB6EF, 0x8BBA, 0xC2DB,
+ 0x8BBB, 0xD79B, 0x8BBC, 0xCBCF, 0x8BBD, 0xB7ED, 0x8BBE, 0xC9E8, 0x8BBF, 0xB7C3, 0x8BC0, 0xBEF7, 0x8BC1, 0xD6A4, 0x8BC2, 0xDAAC,
+ 0x8BC3, 0xDAAD, 0x8BC4, 0xC6C0, 0x8BC5, 0xD7E7, 0x8BC6, 0xCAB6, 0x8BC7, 0xD79C, 0x8BC8, 0xD5A9, 0x8BC9, 0xCBDF, 0x8BCA, 0xD5EF,
+ 0x8BCB, 0xDAAE, 0x8BCC, 0xD6DF, 0x8BCD, 0xB4CA, 0x8BCE, 0xDAB0, 0x8BCF, 0xDAAF, 0x8BD0, 0xD79D, 0x8BD1, 0xD2EB, 0x8BD2, 0xDAB1,
+ 0x8BD3, 0xDAB2, 0x8BD4, 0xDAB3, 0x8BD5, 0xCAD4, 0x8BD6, 0xDAB4, 0x8BD7, 0xCAAB, 0x8BD8, 0xDAB5, 0x8BD9, 0xDAB6, 0x8BDA, 0xB3CF,
+ 0x8BDB, 0xD6EF, 0x8BDC, 0xDAB7, 0x8BDD, 0xBBB0, 0x8BDE, 0xB5AE, 0x8BDF, 0xDAB8, 0x8BE0, 0xDAB9, 0x8BE1, 0xB9EE, 0x8BE2, 0xD1AF,
+ 0x8BE3, 0xD2E8, 0x8BE4, 0xDABA, 0x8BE5, 0xB8C3, 0x8BE6, 0xCFEA, 0x8BE7, 0xB2EF, 0x8BE8, 0xDABB, 0x8BE9, 0xDABC, 0x8BEA, 0xD79E,
+ 0x8BEB, 0xBDEB, 0x8BEC, 0xCEDC, 0x8BED, 0xD3EF, 0x8BEE, 0xDABD, 0x8BEF, 0xCEF3, 0x8BF0, 0xDABE, 0x8BF1, 0xD3D5, 0x8BF2, 0xBBE5,
+ 0x8BF3, 0xDABF, 0x8BF4, 0xCBB5, 0x8BF5, 0xCBD0, 0x8BF6, 0xDAC0, 0x8BF7, 0xC7EB, 0x8BF8, 0xD6EE, 0x8BF9, 0xDAC1, 0x8BFA, 0xC5B5,
+ 0x8BFB, 0xB6C1, 0x8BFC, 0xDAC2, 0x8BFD, 0xB7CC, 0x8BFE, 0xBFCE, 0x8BFF, 0xDAC3, 0x8C00, 0xDAC4, 0x8C01, 0xCBAD, 0x8C02, 0xDAC5,
+ 0x8C03, 0xB5F7, 0x8C04, 0xDAC6, 0x8C05, 0xC1C2, 0x8C06, 0xD7BB, 0x8C07, 0xDAC7, 0x8C08, 0xCCB8, 0x8C09, 0xD79F, 0x8C0A, 0xD2EA,
+ 0x8C0B, 0xC4B1, 0x8C0C, 0xDAC8, 0x8C0D, 0xB5FD, 0x8C0E, 0xBBD1, 0x8C0F, 0xDAC9, 0x8C10, 0xD0B3, 0x8C11, 0xDACA, 0x8C12, 0xDACB,
+ 0x8C13, 0xCEBD, 0x8C14, 0xDACC, 0x8C15, 0xDACD, 0x8C16, 0xDACE, 0x8C17, 0xB2F7, 0x8C18, 0xDAD1, 0x8C19, 0xDACF, 0x8C1A, 0xD1E8,
+ 0x8C1B, 0xDAD0, 0x8C1C, 0xC3D5, 0x8C1D, 0xDAD2, 0x8C1E, 0xD7A0, 0x8C1F, 0xDAD3, 0x8C20, 0xDAD4, 0x8C21, 0xDAD5, 0x8C22, 0xD0BB,
+ 0x8C23, 0xD2A5, 0x8C24, 0xB0F9, 0x8C25, 0xDAD6, 0x8C26, 0xC7AB, 0x8C27, 0xDAD7, 0x8C28, 0xBDF7, 0x8C29, 0xC3A1, 0x8C2A, 0xDAD8,
+ 0x8C2B, 0xDAD9, 0x8C2C, 0xC3FD, 0x8C2D, 0xCCB7, 0x8C2E, 0xDADA, 0x8C2F, 0xDADB, 0x8C30, 0xC0BE, 0x8C31, 0xC6D7, 0x8C32, 0xDADC,
+ 0x8C33, 0xDADD, 0x8C34, 0xC7B4, 0x8C35, 0xDADE, 0x8C36, 0xDADF, 0x8C37, 0xB9C8, 0x8C38, 0xD840, 0x8C39, 0xD841, 0x8C3A, 0xD842,
+ 0x8C3B, 0xD843, 0x8C3C, 0xD844, 0x8C3D, 0xD845, 0x8C3E, 0xD846, 0x8C3F, 0xD847, 0x8C40, 0xD848, 0x8C41, 0xBBED, 0x8C42, 0xD849,
+ 0x8C43, 0xD84A, 0x8C44, 0xD84B, 0x8C45, 0xD84C, 0x8C46, 0xB6B9, 0x8C47, 0xF4F8, 0x8C48, 0xD84D, 0x8C49, 0xF4F9, 0x8C4A, 0xD84E,
+ 0x8C4B, 0xD84F, 0x8C4C, 0xCDE3, 0x8C4D, 0xD850, 0x8C4E, 0xD851, 0x8C4F, 0xD852, 0x8C50, 0xD853, 0x8C51, 0xD854, 0x8C52, 0xD855,
+ 0x8C53, 0xD856, 0x8C54, 0xD857, 0x8C55, 0xF5B9, 0x8C56, 0xD858, 0x8C57, 0xD859, 0x8C58, 0xD85A, 0x8C59, 0xD85B, 0x8C5A, 0xEBE0,
+ 0x8C5B, 0xD85C, 0x8C5C, 0xD85D, 0x8C5D, 0xD85E, 0x8C5E, 0xD85F, 0x8C5F, 0xD860, 0x8C60, 0xD861, 0x8C61, 0xCFF3, 0x8C62, 0xBBBF,
+ 0x8C63, 0xD862, 0x8C64, 0xD863, 0x8C65, 0xD864, 0x8C66, 0xD865, 0x8C67, 0xD866, 0x8C68, 0xD867, 0x8C69, 0xD868, 0x8C6A, 0xBAC0,
+ 0x8C6B, 0xD4A5, 0x8C6C, 0xD869, 0x8C6D, 0xD86A, 0x8C6E, 0xD86B, 0x8C6F, 0xD86C, 0x8C70, 0xD86D, 0x8C71, 0xD86E, 0x8C72, 0xD86F,
+ 0x8C73, 0xE1D9, 0x8C74, 0xD870, 0x8C75, 0xD871, 0x8C76, 0xD872, 0x8C77, 0xD873, 0x8C78, 0xF5F4, 0x8C79, 0xB1AA, 0x8C7A, 0xB2F2,
+ 0x8C7B, 0xD874, 0x8C7C, 0xD875, 0x8C7D, 0xD876, 0x8C7E, 0xD877, 0x8C7F, 0xD878, 0x8C80, 0xD879, 0x8C81, 0xD87A, 0x8C82, 0xF5F5,
+ 0x8C83, 0xD87B, 0x8C84, 0xD87C, 0x8C85, 0xF5F7, 0x8C86, 0xD87D, 0x8C87, 0xD87E, 0x8C88, 0xD880, 0x8C89, 0xBAD1, 0x8C8A, 0xF5F6,
+ 0x8C8B, 0xD881, 0x8C8C, 0xC3B2, 0x8C8D, 0xD882, 0x8C8E, 0xD883, 0x8C8F, 0xD884, 0x8C90, 0xD885, 0x8C91, 0xD886, 0x8C92, 0xD887,
+ 0x8C93, 0xD888, 0x8C94, 0xF5F9, 0x8C95, 0xD889, 0x8C96, 0xD88A, 0x8C97, 0xD88B, 0x8C98, 0xF5F8, 0x8C99, 0xD88C, 0x8C9A, 0xD88D,
+ 0x8C9B, 0xD88E, 0x8C9C, 0xD88F, 0x8C9D, 0xD890, 0x8C9E, 0xD891, 0x8C9F, 0xD892, 0x8CA0, 0xD893, 0x8CA1, 0xD894, 0x8CA2, 0xD895,
+ 0x8CA3, 0xD896, 0x8CA4, 0xD897, 0x8CA5, 0xD898, 0x8CA6, 0xD899, 0x8CA7, 0xD89A, 0x8CA8, 0xD89B, 0x8CA9, 0xD89C, 0x8CAA, 0xD89D,
+ 0x8CAB, 0xD89E, 0x8CAC, 0xD89F, 0x8CAD, 0xD8A0, 0x8CAE, 0xD940, 0x8CAF, 0xD941, 0x8CB0, 0xD942, 0x8CB1, 0xD943, 0x8CB2, 0xD944,
+ 0x8CB3, 0xD945, 0x8CB4, 0xD946, 0x8CB5, 0xD947, 0x8CB6, 0xD948, 0x8CB7, 0xD949, 0x8CB8, 0xD94A, 0x8CB9, 0xD94B, 0x8CBA, 0xD94C,
+ 0x8CBB, 0xD94D, 0x8CBC, 0xD94E, 0x8CBD, 0xD94F, 0x8CBE, 0xD950, 0x8CBF, 0xD951, 0x8CC0, 0xD952, 0x8CC1, 0xD953, 0x8CC2, 0xD954,
+ 0x8CC3, 0xD955, 0x8CC4, 0xD956, 0x8CC5, 0xD957, 0x8CC6, 0xD958, 0x8CC7, 0xD959, 0x8CC8, 0xD95A, 0x8CC9, 0xD95B, 0x8CCA, 0xD95C,
+ 0x8CCB, 0xD95D, 0x8CCC, 0xD95E, 0x8CCD, 0xD95F, 0x8CCE, 0xD960, 0x8CCF, 0xD961, 0x8CD0, 0xD962, 0x8CD1, 0xD963, 0x8CD2, 0xD964,
+ 0x8CD3, 0xD965, 0x8CD4, 0xD966, 0x8CD5, 0xD967, 0x8CD6, 0xD968, 0x8CD7, 0xD969, 0x8CD8, 0xD96A, 0x8CD9, 0xD96B, 0x8CDA, 0xD96C,
+ 0x8CDB, 0xD96D, 0x8CDC, 0xD96E, 0x8CDD, 0xD96F, 0x8CDE, 0xD970, 0x8CDF, 0xD971, 0x8CE0, 0xD972, 0x8CE1, 0xD973, 0x8CE2, 0xD974,
+ 0x8CE3, 0xD975, 0x8CE4, 0xD976, 0x8CE5, 0xD977, 0x8CE6, 0xD978, 0x8CE7, 0xD979, 0x8CE8, 0xD97A, 0x8CE9, 0xD97B, 0x8CEA, 0xD97C,
+ 0x8CEB, 0xD97D, 0x8CEC, 0xD97E, 0x8CED, 0xD980, 0x8CEE, 0xD981, 0x8CEF, 0xD982, 0x8CF0, 0xD983, 0x8CF1, 0xD984, 0x8CF2, 0xD985,
+ 0x8CF3, 0xD986, 0x8CF4, 0xD987, 0x8CF5, 0xD988, 0x8CF6, 0xD989, 0x8CF7, 0xD98A, 0x8CF8, 0xD98B, 0x8CF9, 0xD98C, 0x8CFA, 0xD98D,
+ 0x8CFB, 0xD98E, 0x8CFC, 0xD98F, 0x8CFD, 0xD990, 0x8CFE, 0xD991, 0x8CFF, 0xD992, 0x8D00, 0xD993, 0x8D01, 0xD994, 0x8D02, 0xD995,
+ 0x8D03, 0xD996, 0x8D04, 0xD997, 0x8D05, 0xD998, 0x8D06, 0xD999, 0x8D07, 0xD99A, 0x8D08, 0xD99B, 0x8D09, 0xD99C, 0x8D0A, 0xD99D,
+ 0x8D0B, 0xD99E, 0x8D0C, 0xD99F, 0x8D0D, 0xD9A0, 0x8D0E, 0xDA40, 0x8D0F, 0xDA41, 0x8D10, 0xDA42, 0x8D11, 0xDA43, 0x8D12, 0xDA44,
+ 0x8D13, 0xDA45, 0x8D14, 0xDA46, 0x8D15, 0xDA47, 0x8D16, 0xDA48, 0x8D17, 0xDA49, 0x8D18, 0xDA4A, 0x8D19, 0xDA4B, 0x8D1A, 0xDA4C,
+ 0x8D1B, 0xDA4D, 0x8D1C, 0xDA4E, 0x8D1D, 0xB1B4, 0x8D1E, 0xD5EA, 0x8D1F, 0xB8BA, 0x8D20, 0xDA4F, 0x8D21, 0xB9B1, 0x8D22, 0xB2C6,
+ 0x8D23, 0xD4F0, 0x8D24, 0xCFCD, 0x8D25, 0xB0DC, 0x8D26, 0xD5CB, 0x8D27, 0xBBF5, 0x8D28, 0xD6CA, 0x8D29, 0xB7B7, 0x8D2A, 0xCCB0,
+ 0x8D2B, 0xC6B6, 0x8D2C, 0xB1E1, 0x8D2D, 0xB9BA, 0x8D2E, 0xD6FC, 0x8D2F, 0xB9E1, 0x8D30, 0xB7A1, 0x8D31, 0xBCFA, 0x8D32, 0xEADA,
+ 0x8D33, 0xEADB, 0x8D34, 0xCCF9, 0x8D35, 0xB9F3, 0x8D36, 0xEADC, 0x8D37, 0xB4FB, 0x8D38, 0xC3B3, 0x8D39, 0xB7D1, 0x8D3A, 0xBAD8,
+ 0x8D3B, 0xEADD, 0x8D3C, 0xD4F4, 0x8D3D, 0xEADE, 0x8D3E, 0xBCD6, 0x8D3F, 0xBBDF, 0x8D40, 0xEADF, 0x8D41, 0xC1DE, 0x8D42, 0xC2B8,
+ 0x8D43, 0xD4DF, 0x8D44, 0xD7CA, 0x8D45, 0xEAE0, 0x8D46, 0xEAE1, 0x8D47, 0xEAE4, 0x8D48, 0xEAE2, 0x8D49, 0xEAE3, 0x8D4A, 0xC9DE,
+ 0x8D4B, 0xB8B3, 0x8D4C, 0xB6C4, 0x8D4D, 0xEAE5, 0x8D4E, 0xCAEA, 0x8D4F, 0xC9CD, 0x8D50, 0xB4CD, 0x8D51, 0xDA50, 0x8D52, 0xDA51,
+ 0x8D53, 0xE2D9, 0x8D54, 0xC5E2, 0x8D55, 0xEAE6, 0x8D56, 0xC0B5, 0x8D57, 0xDA52, 0x8D58, 0xD7B8, 0x8D59, 0xEAE7, 0x8D5A, 0xD7AC,
+ 0x8D5B, 0xC8FC, 0x8D5C, 0xD8D3, 0x8D5D, 0xD8CD, 0x8D5E, 0xD4DE, 0x8D5F, 0xDA53, 0x8D60, 0xD4F9, 0x8D61, 0xC9C4, 0x8D62, 0xD3AE,
+ 0x8D63, 0xB8D3, 0x8D64, 0xB3E0, 0x8D65, 0xDA54, 0x8D66, 0xC9E2, 0x8D67, 0xF4F6, 0x8D68, 0xDA55, 0x8D69, 0xDA56, 0x8D6A, 0xDA57,
+ 0x8D6B, 0xBAD5, 0x8D6C, 0xDA58, 0x8D6D, 0xF4F7, 0x8D6E, 0xDA59, 0x8D6F, 0xDA5A, 0x8D70, 0xD7DF, 0x8D71, 0xDA5B, 0x8D72, 0xDA5C,
+ 0x8D73, 0xF4F1, 0x8D74, 0xB8B0, 0x8D75, 0xD5D4, 0x8D76, 0xB8CF, 0x8D77, 0xC6F0, 0x8D78, 0xDA5D, 0x8D79, 0xDA5E, 0x8D7A, 0xDA5F,
+ 0x8D7B, 0xDA60, 0x8D7C, 0xDA61, 0x8D7D, 0xDA62, 0x8D7E, 0xDA63, 0x8D7F, 0xDA64, 0x8D80, 0xDA65, 0x8D81, 0xB3C3, 0x8D82, 0xDA66,
+ 0x8D83, 0xDA67, 0x8D84, 0xF4F2, 0x8D85, 0xB3AC, 0x8D86, 0xDA68, 0x8D87, 0xDA69, 0x8D88, 0xDA6A, 0x8D89, 0xDA6B, 0x8D8A, 0xD4BD,
+ 0x8D8B, 0xC7F7, 0x8D8C, 0xDA6C, 0x8D8D, 0xDA6D, 0x8D8E, 0xDA6E, 0x8D8F, 0xDA6F, 0x8D90, 0xDA70, 0x8D91, 0xF4F4, 0x8D92, 0xDA71,
+ 0x8D93, 0xDA72, 0x8D94, 0xF4F3, 0x8D95, 0xDA73, 0x8D96, 0xDA74, 0x8D97, 0xDA75, 0x8D98, 0xDA76, 0x8D99, 0xDA77, 0x8D9A, 0xDA78,
+ 0x8D9B, 0xDA79, 0x8D9C, 0xDA7A, 0x8D9D, 0xDA7B, 0x8D9E, 0xDA7C, 0x8D9F, 0xCCCB, 0x8DA0, 0xDA7D, 0x8DA1, 0xDA7E, 0x8DA2, 0xDA80,
+ 0x8DA3, 0xC8A4, 0x8DA4, 0xDA81, 0x8DA5, 0xDA82, 0x8DA6, 0xDA83, 0x8DA7, 0xDA84, 0x8DA8, 0xDA85, 0x8DA9, 0xDA86, 0x8DAA, 0xDA87,
+ 0x8DAB, 0xDA88, 0x8DAC, 0xDA89, 0x8DAD, 0xDA8A, 0x8DAE, 0xDA8B, 0x8DAF, 0xDA8C, 0x8DB0, 0xDA8D, 0x8DB1, 0xF4F5, 0x8DB2, 0xDA8E,
+ 0x8DB3, 0xD7E3, 0x8DB4, 0xC5BF, 0x8DB5, 0xF5C0, 0x8DB6, 0xDA8F, 0x8DB7, 0xDA90, 0x8DB8, 0xF5BB, 0x8DB9, 0xDA91, 0x8DBA, 0xF5C3,
+ 0x8DBB, 0xDA92, 0x8DBC, 0xF5C2, 0x8DBD, 0xDA93, 0x8DBE, 0xD6BA, 0x8DBF, 0xF5C1, 0x8DC0, 0xDA94, 0x8DC1, 0xDA95, 0x8DC2, 0xDA96,
+ 0x8DC3, 0xD4BE, 0x8DC4, 0xF5C4, 0x8DC5, 0xDA97, 0x8DC6, 0xF5CC, 0x8DC7, 0xDA98, 0x8DC8, 0xDA99, 0x8DC9, 0xDA9A, 0x8DCA, 0xDA9B,
+ 0x8DCB, 0xB0CF, 0x8DCC, 0xB5F8, 0x8DCD, 0xDA9C, 0x8DCE, 0xF5C9, 0x8DCF, 0xF5CA, 0x8DD0, 0xDA9D, 0x8DD1, 0xC5DC, 0x8DD2, 0xDA9E,
+ 0x8DD3, 0xDA9F, 0x8DD4, 0xDAA0, 0x8DD5, 0xDB40, 0x8DD6, 0xF5C5, 0x8DD7, 0xF5C6, 0x8DD8, 0xDB41, 0x8DD9, 0xDB42, 0x8DDA, 0xF5C7,
+ 0x8DDB, 0xF5CB, 0x8DDC, 0xDB43, 0x8DDD, 0xBEE0, 0x8DDE, 0xF5C8, 0x8DDF, 0xB8FA, 0x8DE0, 0xDB44, 0x8DE1, 0xDB45, 0x8DE2, 0xDB46,
+ 0x8DE3, 0xF5D0, 0x8DE4, 0xF5D3, 0x8DE5, 0xDB47, 0x8DE6, 0xDB48, 0x8DE7, 0xDB49, 0x8DE8, 0xBFE7, 0x8DE9, 0xDB4A, 0x8DEA, 0xB9F2,
+ 0x8DEB, 0xF5BC, 0x8DEC, 0xF5CD, 0x8DED, 0xDB4B, 0x8DEE, 0xDB4C, 0x8DEF, 0xC2B7, 0x8DF0, 0xDB4D, 0x8DF1, 0xDB4E, 0x8DF2, 0xDB4F,
+ 0x8DF3, 0xCCF8, 0x8DF4, 0xDB50, 0x8DF5, 0xBCF9, 0x8DF6, 0xDB51, 0x8DF7, 0xF5CE, 0x8DF8, 0xF5CF, 0x8DF9, 0xF5D1, 0x8DFA, 0xB6E5,
+ 0x8DFB, 0xF5D2, 0x8DFC, 0xDB52, 0x8DFD, 0xF5D5, 0x8DFE, 0xDB53, 0x8DFF, 0xDB54, 0x8E00, 0xDB55, 0x8E01, 0xDB56, 0x8E02, 0xDB57,
+ 0x8E03, 0xDB58, 0x8E04, 0xDB59, 0x8E05, 0xF5BD, 0x8E06, 0xDB5A, 0x8E07, 0xDB5B, 0x8E08, 0xDB5C, 0x8E09, 0xF5D4, 0x8E0A, 0xD3BB,
+ 0x8E0B, 0xDB5D, 0x8E0C, 0xB3EC, 0x8E0D, 0xDB5E, 0x8E0E, 0xDB5F, 0x8E0F, 0xCCA4, 0x8E10, 0xDB60, 0x8E11, 0xDB61, 0x8E12, 0xDB62,
+ 0x8E13, 0xDB63, 0x8E14, 0xF5D6, 0x8E15, 0xDB64, 0x8E16, 0xDB65, 0x8E17, 0xDB66, 0x8E18, 0xDB67, 0x8E19, 0xDB68, 0x8E1A, 0xDB69,
+ 0x8E1B, 0xDB6A, 0x8E1C, 0xDB6B, 0x8E1D, 0xF5D7, 0x8E1E, 0xBEE1, 0x8E1F, 0xF5D8, 0x8E20, 0xDB6C, 0x8E21, 0xDB6D, 0x8E22, 0xCCDF,
+ 0x8E23, 0xF5DB, 0x8E24, 0xDB6E, 0x8E25, 0xDB6F, 0x8E26, 0xDB70, 0x8E27, 0xDB71, 0x8E28, 0xDB72, 0x8E29, 0xB2C8, 0x8E2A, 0xD7D9,
+ 0x8E2B, 0xDB73, 0x8E2C, 0xF5D9, 0x8E2D, 0xDB74, 0x8E2E, 0xF5DA, 0x8E2F, 0xF5DC, 0x8E30, 0xDB75, 0x8E31, 0xF5E2, 0x8E32, 0xDB76,
+ 0x8E33, 0xDB77, 0x8E34, 0xDB78, 0x8E35, 0xF5E0, 0x8E36, 0xDB79, 0x8E37, 0xDB7A, 0x8E38, 0xDB7B, 0x8E39, 0xF5DF, 0x8E3A, 0xF5DD,
+ 0x8E3B, 0xDB7C, 0x8E3C, 0xDB7D, 0x8E3D, 0xF5E1, 0x8E3E, 0xDB7E, 0x8E3F, 0xDB80, 0x8E40, 0xF5DE, 0x8E41, 0xF5E4, 0x8E42, 0xF5E5,
+ 0x8E43, 0xDB81, 0x8E44, 0xCCE3, 0x8E45, 0xDB82, 0x8E46, 0xDB83, 0x8E47, 0xE5BF, 0x8E48, 0xB5B8, 0x8E49, 0xF5E3, 0x8E4A, 0xF5E8,
+ 0x8E4B, 0xCCA3, 0x8E4C, 0xDB84, 0x8E4D, 0xDB85, 0x8E4E, 0xDB86, 0x8E4F, 0xDB87, 0x8E50, 0xDB88, 0x8E51, 0xF5E6, 0x8E52, 0xF5E7,
+ 0x8E53, 0xDB89, 0x8E54, 0xDB8A, 0x8E55, 0xDB8B, 0x8E56, 0xDB8C, 0x8E57, 0xDB8D, 0x8E58, 0xDB8E, 0x8E59, 0xF5BE, 0x8E5A, 0xDB8F,
+ 0x8E5B, 0xDB90, 0x8E5C, 0xDB91, 0x8E5D, 0xDB92, 0x8E5E, 0xDB93, 0x8E5F, 0xDB94, 0x8E60, 0xDB95, 0x8E61, 0xDB96, 0x8E62, 0xDB97,
+ 0x8E63, 0xDB98, 0x8E64, 0xDB99, 0x8E65, 0xDB9A, 0x8E66, 0xB1C4, 0x8E67, 0xDB9B, 0x8E68, 0xDB9C, 0x8E69, 0xF5BF, 0x8E6A, 0xDB9D,
+ 0x8E6B, 0xDB9E, 0x8E6C, 0xB5C5, 0x8E6D, 0xB2E4, 0x8E6E, 0xDB9F, 0x8E6F, 0xF5EC, 0x8E70, 0xF5E9, 0x8E71, 0xDBA0, 0x8E72, 0xB6D7,
+ 0x8E73, 0xDC40, 0x8E74, 0xF5ED, 0x8E75, 0xDC41, 0x8E76, 0xF5EA, 0x8E77, 0xDC42, 0x8E78, 0xDC43, 0x8E79, 0xDC44, 0x8E7A, 0xDC45,
+ 0x8E7B, 0xDC46, 0x8E7C, 0xF5EB, 0x8E7D, 0xDC47, 0x8E7E, 0xDC48, 0x8E7F, 0xB4DA, 0x8E80, 0xDC49, 0x8E81, 0xD4EA, 0x8E82, 0xDC4A,
+ 0x8E83, 0xDC4B, 0x8E84, 0xDC4C, 0x8E85, 0xF5EE, 0x8E86, 0xDC4D, 0x8E87, 0xB3F9, 0x8E88, 0xDC4E, 0x8E89, 0xDC4F, 0x8E8A, 0xDC50,
+ 0x8E8B, 0xDC51, 0x8E8C, 0xDC52, 0x8E8D, 0xDC53, 0x8E8E, 0xDC54, 0x8E8F, 0xF5EF, 0x8E90, 0xF5F1, 0x8E91, 0xDC55, 0x8E92, 0xDC56,
+ 0x8E93, 0xDC57, 0x8E94, 0xF5F0, 0x8E95, 0xDC58, 0x8E96, 0xDC59, 0x8E97, 0xDC5A, 0x8E98, 0xDC5B, 0x8E99, 0xDC5C, 0x8E9A, 0xDC5D,
+ 0x8E9B, 0xDC5E, 0x8E9C, 0xF5F2, 0x8E9D, 0xDC5F, 0x8E9E, 0xF5F3, 0x8E9F, 0xDC60, 0x8EA0, 0xDC61, 0x8EA1, 0xDC62, 0x8EA2, 0xDC63,
+ 0x8EA3, 0xDC64, 0x8EA4, 0xDC65, 0x8EA5, 0xDC66, 0x8EA6, 0xDC67, 0x8EA7, 0xDC68, 0x8EA8, 0xDC69, 0x8EA9, 0xDC6A, 0x8EAA, 0xDC6B,
+ 0x8EAB, 0xC9ED, 0x8EAC, 0xB9AA, 0x8EAD, 0xDC6C, 0x8EAE, 0xDC6D, 0x8EAF, 0xC7FB, 0x8EB0, 0xDC6E, 0x8EB1, 0xDC6F, 0x8EB2, 0xB6E3,
+ 0x8EB3, 0xDC70, 0x8EB4, 0xDC71, 0x8EB5, 0xDC72, 0x8EB6, 0xDC73, 0x8EB7, 0xDC74, 0x8EB8, 0xDC75, 0x8EB9, 0xDC76, 0x8EBA, 0xCCC9,
+ 0x8EBB, 0xDC77, 0x8EBC, 0xDC78, 0x8EBD, 0xDC79, 0x8EBE, 0xDC7A, 0x8EBF, 0xDC7B, 0x8EC0, 0xDC7C, 0x8EC1, 0xDC7D, 0x8EC2, 0xDC7E,
+ 0x8EC3, 0xDC80, 0x8EC4, 0xDC81, 0x8EC5, 0xDC82, 0x8EC6, 0xDC83, 0x8EC7, 0xDC84, 0x8EC8, 0xDC85, 0x8EC9, 0xDC86, 0x8ECA, 0xDC87,
+ 0x8ECB, 0xDC88, 0x8ECC, 0xDC89, 0x8ECD, 0xDC8A, 0x8ECE, 0xEAA6, 0x8ECF, 0xDC8B, 0x8ED0, 0xDC8C, 0x8ED1, 0xDC8D, 0x8ED2, 0xDC8E,
+ 0x8ED3, 0xDC8F, 0x8ED4, 0xDC90, 0x8ED5, 0xDC91, 0x8ED6, 0xDC92, 0x8ED7, 0xDC93, 0x8ED8, 0xDC94, 0x8ED9, 0xDC95, 0x8EDA, 0xDC96,
+ 0x8EDB, 0xDC97, 0x8EDC, 0xDC98, 0x8EDD, 0xDC99, 0x8EDE, 0xDC9A, 0x8EDF, 0xDC9B, 0x8EE0, 0xDC9C, 0x8EE1, 0xDC9D, 0x8EE2, 0xDC9E,
+ 0x8EE3, 0xDC9F, 0x8EE4, 0xDCA0, 0x8EE5, 0xDD40, 0x8EE6, 0xDD41, 0x8EE7, 0xDD42, 0x8EE8, 0xDD43, 0x8EE9, 0xDD44, 0x8EEA, 0xDD45,
+ 0x8EEB, 0xDD46, 0x8EEC, 0xDD47, 0x8EED, 0xDD48, 0x8EEE, 0xDD49, 0x8EEF, 0xDD4A, 0x8EF0, 0xDD4B, 0x8EF1, 0xDD4C, 0x8EF2, 0xDD4D,
+ 0x8EF3, 0xDD4E, 0x8EF4, 0xDD4F, 0x8EF5, 0xDD50, 0x8EF6, 0xDD51, 0x8EF7, 0xDD52, 0x8EF8, 0xDD53, 0x8EF9, 0xDD54, 0x8EFA, 0xDD55,
+ 0x8EFB, 0xDD56, 0x8EFC, 0xDD57, 0x8EFD, 0xDD58, 0x8EFE, 0xDD59, 0x8EFF, 0xDD5A, 0x8F00, 0xDD5B, 0x8F01, 0xDD5C, 0x8F02, 0xDD5D,
+ 0x8F03, 0xDD5E, 0x8F04, 0xDD5F, 0x8F05, 0xDD60, 0x8F06, 0xDD61, 0x8F07, 0xDD62, 0x8F08, 0xDD63, 0x8F09, 0xDD64, 0x8F0A, 0xDD65,
+ 0x8F0B, 0xDD66, 0x8F0C, 0xDD67, 0x8F0D, 0xDD68, 0x8F0E, 0xDD69, 0x8F0F, 0xDD6A, 0x8F10, 0xDD6B, 0x8F11, 0xDD6C, 0x8F12, 0xDD6D,
+ 0x8F13, 0xDD6E, 0x8F14, 0xDD6F, 0x8F15, 0xDD70, 0x8F16, 0xDD71, 0x8F17, 0xDD72, 0x8F18, 0xDD73, 0x8F19, 0xDD74, 0x8F1A, 0xDD75,
+ 0x8F1B, 0xDD76, 0x8F1C, 0xDD77, 0x8F1D, 0xDD78, 0x8F1E, 0xDD79, 0x8F1F, 0xDD7A, 0x8F20, 0xDD7B, 0x8F21, 0xDD7C, 0x8F22, 0xDD7D,
+ 0x8F23, 0xDD7E, 0x8F24, 0xDD80, 0x8F25, 0xDD81, 0x8F26, 0xDD82, 0x8F27, 0xDD83, 0x8F28, 0xDD84, 0x8F29, 0xDD85, 0x8F2A, 0xDD86,
+ 0x8F2B, 0xDD87, 0x8F2C, 0xDD88, 0x8F2D, 0xDD89, 0x8F2E, 0xDD8A, 0x8F2F, 0xDD8B, 0x8F30, 0xDD8C, 0x8F31, 0xDD8D, 0x8F32, 0xDD8E,
+ 0x8F33, 0xDD8F, 0x8F34, 0xDD90, 0x8F35, 0xDD91, 0x8F36, 0xDD92, 0x8F37, 0xDD93, 0x8F38, 0xDD94, 0x8F39, 0xDD95, 0x8F3A, 0xDD96,
+ 0x8F3B, 0xDD97, 0x8F3C, 0xDD98, 0x8F3D, 0xDD99, 0x8F3E, 0xDD9A, 0x8F3F, 0xDD9B, 0x8F40, 0xDD9C, 0x8F41, 0xDD9D, 0x8F42, 0xDD9E,
+ 0x8F43, 0xDD9F, 0x8F44, 0xDDA0, 0x8F45, 0xDE40, 0x8F46, 0xDE41, 0x8F47, 0xDE42, 0x8F48, 0xDE43, 0x8F49, 0xDE44, 0x8F4A, 0xDE45,
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+ 0x987B, 0xD0EB, 0x987C, 0xE7EF, 0x987D, 0xCDE7, 0x987E, 0xB9CB, 0x987F, 0xB6D9, 0x9880, 0xF1FD, 0x9881, 0xB0E4, 0x9882, 0xCBCC,
+ 0x9883, 0xF1FE, 0x9884, 0xD4A4, 0x9885, 0xC2AD, 0x9886, 0xC1EC, 0x9887, 0xC6C4, 0x9888, 0xBEB1, 0x9889, 0xF2A1, 0x988A, 0xBCD5,
+ 0x988B, 0xEF46, 0x988C, 0xF2A2, 0x988D, 0xF2A3, 0x988E, 0xEF47, 0x988F, 0xF2A4, 0x9890, 0xD2C3, 0x9891, 0xC6B5, 0x9892, 0xEF48,
+ 0x9893, 0xCDC7, 0x9894, 0xF2A5, 0x9895, 0xEF49, 0x9896, 0xD3B1, 0x9897, 0xBFC5, 0x9898, 0xCCE2, 0x9899, 0xEF4A, 0x989A, 0xF2A6,
+ 0x989B, 0xF2A7, 0x989C, 0xD1D5, 0x989D, 0xB6EE, 0x989E, 0xF2A8, 0x989F, 0xF2A9, 0x98A0, 0xB5DF, 0x98A1, 0xF2AA, 0x98A2, 0xF2AB,
+ 0x98A3, 0xEF4B, 0x98A4, 0xB2FC, 0x98A5, 0xF2AC, 0x98A6, 0xF2AD, 0x98A7, 0xC8A7, 0x98A8, 0xEF4C, 0x98A9, 0xEF4D, 0x98AA, 0xEF4E,
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+ 0x996B, 0xE2C0, 0x996C, 0xE2C1, 0x996D, 0xB7B9, 0x996E, 0xD2FB, 0x996F, 0xBDA4, 0x9970, 0xCACE, 0x9971, 0xB1A5, 0x9972, 0xCBC7,
+ 0x9973, 0xF099, 0x9974, 0xE2C2, 0x9975, 0xB6FC, 0x9976, 0xC8C4, 0x9977, 0xE2C3, 0x9978, 0xF09A, 0x9979, 0xF09B, 0x997A, 0xBDC8,
+ 0x997B, 0xF09C, 0x997C, 0xB1FD, 0x997D, 0xE2C4, 0x997E, 0xF09D, 0x997F, 0xB6F6, 0x9980, 0xE2C5, 0x9981, 0xC4D9, 0x9982, 0xF09E,
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+ 0x99C3, 0xF169, 0x99C4, 0xF16A, 0x99C5, 0xF16B, 0x99C6, 0xF16C, 0x99C7, 0xF16D, 0x99C8, 0xF16E, 0x99C9, 0xF16F, 0x99CA, 0xF170,
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+ 0x9A03, 0xF249, 0x9A04, 0xF24A, 0x9A05, 0xF24B, 0x9A06, 0xF24C, 0x9A07, 0xF24D, 0x9A08, 0xF24E, 0x9A09, 0xF24F, 0x9A0A, 0xF250,
+ 0x9A0B, 0xF251, 0x9A0C, 0xF252, 0x9A0D, 0xF253, 0x9A0E, 0xF254, 0x9A0F, 0xF255, 0x9A10, 0xF256, 0x9A11, 0xF257, 0x9A12, 0xF258,
+ 0x9A13, 0xF259, 0x9A14, 0xF25A, 0x9A15, 0xF25B, 0x9A16, 0xF25C, 0x9A17, 0xF25D, 0x9A18, 0xF25E, 0x9A19, 0xF25F, 0x9A1A, 0xF260,
+ 0x9A1B, 0xF261, 0x9A1C, 0xF262, 0x9A1D, 0xF263, 0x9A1E, 0xF264, 0x9A1F, 0xF265, 0x9A20, 0xF266, 0x9A21, 0xF267, 0x9A22, 0xF268,
+ 0x9A23, 0xF269, 0x9A24, 0xF26A, 0x9A25, 0xF26B, 0x9A26, 0xF26C, 0x9A27, 0xF26D, 0x9A28, 0xF26E, 0x9A29, 0xF26F, 0x9A2A, 0xF270,
+ 0x9A2B, 0xF271, 0x9A2C, 0xF272, 0x9A2D, 0xF273, 0x9A2E, 0xF274, 0x9A2F, 0xF275, 0x9A30, 0xF276, 0x9A31, 0xF277, 0x9A32, 0xF278,
+ 0x9A33, 0xF279, 0x9A34, 0xF27A, 0x9A35, 0xF27B, 0x9A36, 0xF27C, 0x9A37, 0xF27D, 0x9A38, 0xF27E, 0x9A39, 0xF280, 0x9A3A, 0xF281,
+ 0x9A3B, 0xF282, 0x9A3C, 0xF283, 0x9A3D, 0xF284, 0x9A3E, 0xF285, 0x9A3F, 0xF286, 0x9A40, 0xF287, 0x9A41, 0xF288, 0x9A42, 0xF289,
+ 0x9A43, 0xF28A, 0x9A44, 0xF28B, 0x9A45, 0xF28C, 0x9A46, 0xF28D, 0x9A47, 0xF28E, 0x9A48, 0xF28F, 0x9A49, 0xF290, 0x9A4A, 0xF291,
+ 0x9A4B, 0xF292, 0x9A4C, 0xF293, 0x9A4D, 0xF294, 0x9A4E, 0xF295, 0x9A4F, 0xF296, 0x9A50, 0xF297, 0x9A51, 0xF298, 0x9A52, 0xF299,
+ 0x9A53, 0xF29A, 0x9A54, 0xF29B, 0x9A55, 0xF29C, 0x9A56, 0xF29D, 0x9A57, 0xF29E, 0x9A58, 0xF29F, 0x9A59, 0xF2A0, 0x9A5A, 0xF340,
+ 0x9A5B, 0xF341, 0x9A5C, 0xF342, 0x9A5D, 0xF343, 0x9A5E, 0xF344, 0x9A5F, 0xF345, 0x9A60, 0xF346, 0x9A61, 0xF347, 0x9A62, 0xF348,
+ 0x9A63, 0xF349, 0x9A64, 0xF34A, 0x9A65, 0xF34B, 0x9A66, 0xF34C, 0x9A67, 0xF34D, 0x9A68, 0xF34E, 0x9A69, 0xF34F, 0x9A6A, 0xF350,
+ 0x9A6B, 0xF351, 0x9A6C, 0xC2ED, 0x9A6D, 0xD4A6, 0x9A6E, 0xCDD4, 0x9A6F, 0xD1B1, 0x9A70, 0xB3DB, 0x9A71, 0xC7FD, 0x9A72, 0xF352,
+ 0x9A73, 0xB2B5, 0x9A74, 0xC2BF, 0x9A75, 0xE6E0, 0x9A76, 0xCABB, 0x9A77, 0xE6E1, 0x9A78, 0xE6E2, 0x9A79, 0xBED4, 0x9A7A, 0xE6E3,
+ 0x9A7B, 0xD7A4, 0x9A7C, 0xCDD5, 0x9A7D, 0xE6E5, 0x9A7E, 0xBCDD, 0x9A7F, 0xE6E4, 0x9A80, 0xE6E6, 0x9A81, 0xE6E7, 0x9A82, 0xC2EE,
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+ 0x9A8B, 0xB3D2, 0x9A8C, 0xD1E9, 0x9A8D, 0xF355, 0x9A8E, 0xF356, 0x9A8F, 0xBFA5, 0x9A90, 0xE6EB, 0x9A91, 0xC6EF, 0x9A92, 0xE6EC,
+ 0x9A93, 0xE6ED, 0x9A94, 0xF357, 0x9A95, 0xF358, 0x9A96, 0xE6EE, 0x9A97, 0xC6AD, 0x9A98, 0xE6EF, 0x9A99, 0xF359, 0x9A9A, 0xC9A7,
+ 0x9A9B, 0xE6F0, 0x9A9C, 0xE6F1, 0x9A9D, 0xE6F2, 0x9A9E, 0xE5B9, 0x9A9F, 0xE6F3, 0x9AA0, 0xE6F4, 0x9AA1, 0xC2E2, 0x9AA2, 0xE6F5,
+ 0x9AA3, 0xE6F6, 0x9AA4, 0xD6E8, 0x9AA5, 0xE6F7, 0x9AA6, 0xF35A, 0x9AA7, 0xE6F8, 0x9AA8, 0xB9C7, 0x9AA9, 0xF35B, 0x9AAA, 0xF35C,
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+ 0x9AB3, 0xF363, 0x9AB4, 0xF364, 0x9AB5, 0xF365, 0x9AB6, 0xF7BE, 0x9AB7, 0xF7BC, 0x9AB8, 0xBAA1, 0x9AB9, 0xF366, 0x9ABA, 0xF7BF,
+ 0x9ABB, 0xF367, 0x9ABC, 0xF7C0, 0x9ABD, 0xF368, 0x9ABE, 0xF369, 0x9ABF, 0xF36A, 0x9AC0, 0xF7C2, 0x9AC1, 0xF7C1, 0x9AC2, 0xF7C4,
+ 0x9AC3, 0xF36B, 0x9AC4, 0xF36C, 0x9AC5, 0xF7C3, 0x9AC6, 0xF36D, 0x9AC7, 0xF36E, 0x9AC8, 0xF36F, 0x9AC9, 0xF370, 0x9ACA, 0xF371,
+ 0x9ACB, 0xF7C5, 0x9ACC, 0xF7C6, 0x9ACD, 0xF372, 0x9ACE, 0xF373, 0x9ACF, 0xF374, 0x9AD0, 0xF375, 0x9AD1, 0xF7C7, 0x9AD2, 0xF376,
+ 0x9AD3, 0xCBE8, 0x9AD4, 0xF377, 0x9AD5, 0xF378, 0x9AD6, 0xF379, 0x9AD7, 0xF37A, 0x9AD8, 0xB8DF, 0x9AD9, 0xF37B, 0x9ADA, 0xF37C,
+ 0x9ADB, 0xF37D, 0x9ADC, 0xF37E, 0x9ADD, 0xF380, 0x9ADE, 0xF381, 0x9ADF, 0xF7D4, 0x9AE0, 0xF382, 0x9AE1, 0xF7D5, 0x9AE2, 0xF383,
+ 0x9AE3, 0xF384, 0x9AE4, 0xF385, 0x9AE5, 0xF386, 0x9AE6, 0xF7D6, 0x9AE7, 0xF387, 0x9AE8, 0xF388, 0x9AE9, 0xF389, 0x9AEA, 0xF38A,
+ 0x9AEB, 0xF7D8, 0x9AEC, 0xF38B, 0x9AED, 0xF7DA, 0x9AEE, 0xF38C, 0x9AEF, 0xF7D7, 0x9AF0, 0xF38D, 0x9AF1, 0xF38E, 0x9AF2, 0xF38F,
+ 0x9AF3, 0xF390, 0x9AF4, 0xF391, 0x9AF5, 0xF392, 0x9AF6, 0xF393, 0x9AF7, 0xF394, 0x9AF8, 0xF395, 0x9AF9, 0xF7DB, 0x9AFA, 0xF396,
+ 0x9AFB, 0xF7D9, 0x9AFC, 0xF397, 0x9AFD, 0xF398, 0x9AFE, 0xF399, 0x9AFF, 0xF39A, 0x9B00, 0xF39B, 0x9B01, 0xF39C, 0x9B02, 0xF39D,
+ 0x9B03, 0xD7D7, 0x9B04, 0xF39E, 0x9B05, 0xF39F, 0x9B06, 0xF3A0, 0x9B07, 0xF440, 0x9B08, 0xF7DC, 0x9B09, 0xF441, 0x9B0A, 0xF442,
+ 0x9B0B, 0xF443, 0x9B0C, 0xF444, 0x9B0D, 0xF445, 0x9B0E, 0xF446, 0x9B0F, 0xF7DD, 0x9B10, 0xF447, 0x9B11, 0xF448, 0x9B12, 0xF449,
+ 0x9B13, 0xF7DE, 0x9B14, 0xF44A, 0x9B15, 0xF44B, 0x9B16, 0xF44C, 0x9B17, 0xF44D, 0x9B18, 0xF44E, 0x9B19, 0xF44F, 0x9B1A, 0xF450,
+ 0x9B1B, 0xF451, 0x9B1C, 0xF452, 0x9B1D, 0xF453, 0x9B1E, 0xF454, 0x9B1F, 0xF7DF, 0x9B20, 0xF455, 0x9B21, 0xF456, 0x9B22, 0xF457,
+ 0x9B23, 0xF7E0, 0x9B24, 0xF458, 0x9B25, 0xF459, 0x9B26, 0xF45A, 0x9B27, 0xF45B, 0x9B28, 0xF45C, 0x9B29, 0xF45D, 0x9B2A, 0xF45E,
+ 0x9B2B, 0xF45F, 0x9B2C, 0xF460, 0x9B2D, 0xF461, 0x9B2E, 0xF462, 0x9B2F, 0xDBCB, 0x9B30, 0xF463, 0x9B31, 0xF464, 0x9B32, 0xD8AA,
+ 0x9B33, 0xF465, 0x9B34, 0xF466, 0x9B35, 0xF467, 0x9B36, 0xF468, 0x9B37, 0xF469, 0x9B38, 0xF46A, 0x9B39, 0xF46B, 0x9B3A, 0xF46C,
+ 0x9B3B, 0xE5F7, 0x9B3C, 0xB9ED, 0x9B3D, 0xF46D, 0x9B3E, 0xF46E, 0x9B3F, 0xF46F, 0x9B40, 0xF470, 0x9B41, 0xBFFD, 0x9B42, 0xBBEA,
+ 0x9B43, 0xF7C9, 0x9B44, 0xC6C7, 0x9B45, 0xF7C8, 0x9B46, 0xF471, 0x9B47, 0xF7CA, 0x9B48, 0xF7CC, 0x9B49, 0xF7CB, 0x9B4A, 0xF472,
+ 0x9B4B, 0xF473, 0x9B4C, 0xF474, 0x9B4D, 0xF7CD, 0x9B4E, 0xF475, 0x9B4F, 0xCEBA, 0x9B50, 0xF476, 0x9B51, 0xF7CE, 0x9B52, 0xF477,
+ 0x9B53, 0xF478, 0x9B54, 0xC4A7, 0x9B55, 0xF479, 0x9B56, 0xF47A, 0x9B57, 0xF47B, 0x9B58, 0xF47C, 0x9B59, 0xF47D, 0x9B5A, 0xF47E,
+ 0x9B5B, 0xF480, 0x9B5C, 0xF481, 0x9B5D, 0xF482, 0x9B5E, 0xF483, 0x9B5F, 0xF484, 0x9B60, 0xF485, 0x9B61, 0xF486, 0x9B62, 0xF487,
+ 0x9B63, 0xF488, 0x9B64, 0xF489, 0x9B65, 0xF48A, 0x9B66, 0xF48B, 0x9B67, 0xF48C, 0x9B68, 0xF48D, 0x9B69, 0xF48E, 0x9B6A, 0xF48F,
+ 0x9B6B, 0xF490, 0x9B6C, 0xF491, 0x9B6D, 0xF492, 0x9B6E, 0xF493, 0x9B6F, 0xF494, 0x9B70, 0xF495, 0x9B71, 0xF496, 0x9B72, 0xF497,
+ 0x9B73, 0xF498, 0x9B74, 0xF499, 0x9B75, 0xF49A, 0x9B76, 0xF49B, 0x9B77, 0xF49C, 0x9B78, 0xF49D, 0x9B79, 0xF49E, 0x9B7A, 0xF49F,
+ 0x9B7B, 0xF4A0, 0x9B7C, 0xF540, 0x9B7D, 0xF541, 0x9B7E, 0xF542, 0x9B7F, 0xF543, 0x9B80, 0xF544, 0x9B81, 0xF545, 0x9B82, 0xF546,
+ 0x9B83, 0xF547, 0x9B84, 0xF548, 0x9B85, 0xF549, 0x9B86, 0xF54A, 0x9B87, 0xF54B, 0x9B88, 0xF54C, 0x9B89, 0xF54D, 0x9B8A, 0xF54E,
+ 0x9B8B, 0xF54F, 0x9B8C, 0xF550, 0x9B8D, 0xF551, 0x9B8E, 0xF552, 0x9B8F, 0xF553, 0x9B90, 0xF554, 0x9B91, 0xF555, 0x9B92, 0xF556,
+ 0x9B93, 0xF557, 0x9B94, 0xF558, 0x9B95, 0xF559, 0x9B96, 0xF55A, 0x9B97, 0xF55B, 0x9B98, 0xF55C, 0x9B99, 0xF55D, 0x9B9A, 0xF55E,
+ 0x9B9B, 0xF55F, 0x9B9C, 0xF560, 0x9B9D, 0xF561, 0x9B9E, 0xF562, 0x9B9F, 0xF563, 0x9BA0, 0xF564, 0x9BA1, 0xF565, 0x9BA2, 0xF566,
+ 0x9BA3, 0xF567, 0x9BA4, 0xF568, 0x9BA5, 0xF569, 0x9BA6, 0xF56A, 0x9BA7, 0xF56B, 0x9BA8, 0xF56C, 0x9BA9, 0xF56D, 0x9BAA, 0xF56E,
+ 0x9BAB, 0xF56F, 0x9BAC, 0xF570, 0x9BAD, 0xF571, 0x9BAE, 0xF572, 0x9BAF, 0xF573, 0x9BB0, 0xF574, 0x9BB1, 0xF575, 0x9BB2, 0xF576,
+ 0x9BB3, 0xF577, 0x9BB4, 0xF578, 0x9BB5, 0xF579, 0x9BB6, 0xF57A, 0x9BB7, 0xF57B, 0x9BB8, 0xF57C, 0x9BB9, 0xF57D, 0x9BBA, 0xF57E,
+ 0x9BBB, 0xF580, 0x9BBC, 0xF581, 0x9BBD, 0xF582, 0x9BBE, 0xF583, 0x9BBF, 0xF584, 0x9BC0, 0xF585, 0x9BC1, 0xF586, 0x9BC2, 0xF587,
+ 0x9BC3, 0xF588, 0x9BC4, 0xF589, 0x9BC5, 0xF58A, 0x9BC6, 0xF58B, 0x9BC7, 0xF58C, 0x9BC8, 0xF58D, 0x9BC9, 0xF58E, 0x9BCA, 0xF58F,
+ 0x9BCB, 0xF590, 0x9BCC, 0xF591, 0x9BCD, 0xF592, 0x9BCE, 0xF593, 0x9BCF, 0xF594, 0x9BD0, 0xF595, 0x9BD1, 0xF596, 0x9BD2, 0xF597,
+ 0x9BD3, 0xF598, 0x9BD4, 0xF599, 0x9BD5, 0xF59A, 0x9BD6, 0xF59B, 0x9BD7, 0xF59C, 0x9BD8, 0xF59D, 0x9BD9, 0xF59E, 0x9BDA, 0xF59F,
+ 0x9BDB, 0xF5A0, 0x9BDC, 0xF640, 0x9BDD, 0xF641, 0x9BDE, 0xF642, 0x9BDF, 0xF643, 0x9BE0, 0xF644, 0x9BE1, 0xF645, 0x9BE2, 0xF646,
+ 0x9BE3, 0xF647, 0x9BE4, 0xF648, 0x9BE5, 0xF649, 0x9BE6, 0xF64A, 0x9BE7, 0xF64B, 0x9BE8, 0xF64C, 0x9BE9, 0xF64D, 0x9BEA, 0xF64E,
+ 0x9BEB, 0xF64F, 0x9BEC, 0xF650, 0x9BED, 0xF651, 0x9BEE, 0xF652, 0x9BEF, 0xF653, 0x9BF0, 0xF654, 0x9BF1, 0xF655, 0x9BF2, 0xF656,
+ 0x9BF3, 0xF657, 0x9BF4, 0xF658, 0x9BF5, 0xF659, 0x9BF6, 0xF65A, 0x9BF7, 0xF65B, 0x9BF8, 0xF65C, 0x9BF9, 0xF65D, 0x9BFA, 0xF65E,
+ 0x9BFB, 0xF65F, 0x9BFC, 0xF660, 0x9BFD, 0xF661, 0x9BFE, 0xF662, 0x9BFF, 0xF663, 0x9C00, 0xF664, 0x9C01, 0xF665, 0x9C02, 0xF666,
+ 0x9C03, 0xF667, 0x9C04, 0xF668, 0x9C05, 0xF669, 0x9C06, 0xF66A, 0x9C07, 0xF66B, 0x9C08, 0xF66C, 0x9C09, 0xF66D, 0x9C0A, 0xF66E,
+ 0x9C0B, 0xF66F, 0x9C0C, 0xF670, 0x9C0D, 0xF671, 0x9C0E, 0xF672, 0x9C0F, 0xF673, 0x9C10, 0xF674, 0x9C11, 0xF675, 0x9C12, 0xF676,
+ 0x9C13, 0xF677, 0x9C14, 0xF678, 0x9C15, 0xF679, 0x9C16, 0xF67A, 0x9C17, 0xF67B, 0x9C18, 0xF67C, 0x9C19, 0xF67D, 0x9C1A, 0xF67E,
+ 0x9C1B, 0xF680, 0x9C1C, 0xF681, 0x9C1D, 0xF682, 0x9C1E, 0xF683, 0x9C1F, 0xF684, 0x9C20, 0xF685, 0x9C21, 0xF686, 0x9C22, 0xF687,
+ 0x9C23, 0xF688, 0x9C24, 0xF689, 0x9C25, 0xF68A, 0x9C26, 0xF68B, 0x9C27, 0xF68C, 0x9C28, 0xF68D, 0x9C29, 0xF68E, 0x9C2A, 0xF68F,
+ 0x9C2B, 0xF690, 0x9C2C, 0xF691, 0x9C2D, 0xF692, 0x9C2E, 0xF693, 0x9C2F, 0xF694, 0x9C30, 0xF695, 0x9C31, 0xF696, 0x9C32, 0xF697,
+ 0x9C33, 0xF698, 0x9C34, 0xF699, 0x9C35, 0xF69A, 0x9C36, 0xF69B, 0x9C37, 0xF69C, 0x9C38, 0xF69D, 0x9C39, 0xF69E, 0x9C3A, 0xF69F,
+ 0x9C3B, 0xF6A0, 0x9C3C, 0xF740, 0x9C3D, 0xF741, 0x9C3E, 0xF742, 0x9C3F, 0xF743, 0x9C40, 0xF744, 0x9C41, 0xF745, 0x9C42, 0xF746,
+ 0x9C43, 0xF747, 0x9C44, 0xF748, 0x9C45, 0xF749, 0x9C46, 0xF74A, 0x9C47, 0xF74B, 0x9C48, 0xF74C, 0x9C49, 0xF74D, 0x9C4A, 0xF74E,
+ 0x9C4B, 0xF74F, 0x9C4C, 0xF750, 0x9C4D, 0xF751, 0x9C4E, 0xF752, 0x9C4F, 0xF753, 0x9C50, 0xF754, 0x9C51, 0xF755, 0x9C52, 0xF756,
+ 0x9C53, 0xF757, 0x9C54, 0xF758, 0x9C55, 0xF759, 0x9C56, 0xF75A, 0x9C57, 0xF75B, 0x9C58, 0xF75C, 0x9C59, 0xF75D, 0x9C5A, 0xF75E,
+ 0x9C5B, 0xF75F, 0x9C5C, 0xF760, 0x9C5D, 0xF761, 0x9C5E, 0xF762, 0x9C5F, 0xF763, 0x9C60, 0xF764, 0x9C61, 0xF765, 0x9C62, 0xF766,
+ 0x9C63, 0xF767, 0x9C64, 0xF768, 0x9C65, 0xF769, 0x9C66, 0xF76A, 0x9C67, 0xF76B, 0x9C68, 0xF76C, 0x9C69, 0xF76D, 0x9C6A, 0xF76E,
+ 0x9C6B, 0xF76F, 0x9C6C, 0xF770, 0x9C6D, 0xF771, 0x9C6E, 0xF772, 0x9C6F, 0xF773, 0x9C70, 0xF774, 0x9C71, 0xF775, 0x9C72, 0xF776,
+ 0x9C73, 0xF777, 0x9C74, 0xF778, 0x9C75, 0xF779, 0x9C76, 0xF77A, 0x9C77, 0xF77B, 0x9C78, 0xF77C, 0x9C79, 0xF77D, 0x9C7A, 0xF77E,
+ 0x9C7B, 0xF780, 0x9C7C, 0xD3E3, 0x9C7D, 0xF781, 0x9C7E, 0xF782, 0x9C7F, 0xF6CF, 0x9C80, 0xF783, 0x9C81, 0xC2B3, 0x9C82, 0xF6D0,
+ 0x9C83, 0xF784, 0x9C84, 0xF785, 0x9C85, 0xF6D1, 0x9C86, 0xF6D2, 0x9C87, 0xF6D3, 0x9C88, 0xF6D4, 0x9C89, 0xF786, 0x9C8A, 0xF787,
+ 0x9C8B, 0xF6D6, 0x9C8C, 0xF788, 0x9C8D, 0xB1AB, 0x9C8E, 0xF6D7, 0x9C8F, 0xF789, 0x9C90, 0xF6D8, 0x9C91, 0xF6D9, 0x9C92, 0xF6DA,
+ 0x9C93, 0xF78A, 0x9C94, 0xF6DB, 0x9C95, 0xF6DC, 0x9C96, 0xF78B, 0x9C97, 0xF78C, 0x9C98, 0xF78D, 0x9C99, 0xF78E, 0x9C9A, 0xF6DD,
+ 0x9C9B, 0xF6DE, 0x9C9C, 0xCFCA, 0x9C9D, 0xF78F, 0x9C9E, 0xF6DF, 0x9C9F, 0xF6E0, 0x9CA0, 0xF6E1, 0x9CA1, 0xF6E2, 0x9CA2, 0xF6E3,
+ 0x9CA3, 0xF6E4, 0x9CA4, 0xC0F0, 0x9CA5, 0xF6E5, 0x9CA6, 0xF6E6, 0x9CA7, 0xF6E7, 0x9CA8, 0xF6E8, 0x9CA9, 0xF6E9, 0x9CAA, 0xF790,
+ 0x9CAB, 0xF6EA, 0x9CAC, 0xF791, 0x9CAD, 0xF6EB, 0x9CAE, 0xF6EC, 0x9CAF, 0xF792, 0x9CB0, 0xF6ED, 0x9CB1, 0xF6EE, 0x9CB2, 0xF6EF,
+ 0x9CB3, 0xF6F0, 0x9CB4, 0xF6F1, 0x9CB5, 0xF6F2, 0x9CB6, 0xF6F3, 0x9CB7, 0xF6F4, 0x9CB8, 0xBEA8, 0x9CB9, 0xF793, 0x9CBA, 0xF6F5,
+ 0x9CBB, 0xF6F6, 0x9CBC, 0xF6F7, 0x9CBD, 0xF6F8, 0x9CBE, 0xF794, 0x9CBF, 0xF795, 0x9CC0, 0xF796, 0x9CC1, 0xF797, 0x9CC2, 0xF798,
+ 0x9CC3, 0xC8FA, 0x9CC4, 0xF6F9, 0x9CC5, 0xF6FA, 0x9CC6, 0xF6FB, 0x9CC7, 0xF6FC, 0x9CC8, 0xF799, 0x9CC9, 0xF79A, 0x9CCA, 0xF6FD,
+ 0x9CCB, 0xF6FE, 0x9CCC, 0xF7A1, 0x9CCD, 0xF7A2, 0x9CCE, 0xF7A3, 0x9CCF, 0xF7A4, 0x9CD0, 0xF7A5, 0x9CD1, 0xF79B, 0x9CD2, 0xF79C,
+ 0x9CD3, 0xF7A6, 0x9CD4, 0xF7A7, 0x9CD5, 0xF7A8, 0x9CD6, 0xB1EE, 0x9CD7, 0xF7A9, 0x9CD8, 0xF7AA, 0x9CD9, 0xF7AB, 0x9CDA, 0xF79D,
+ 0x9CDB, 0xF79E, 0x9CDC, 0xF7AC, 0x9CDD, 0xF7AD, 0x9CDE, 0xC1DB, 0x9CDF, 0xF7AE, 0x9CE0, 0xF79F, 0x9CE1, 0xF7A0, 0x9CE2, 0xF7AF,
+ 0x9CE3, 0xF840, 0x9CE4, 0xF841, 0x9CE5, 0xF842, 0x9CE6, 0xF843, 0x9CE7, 0xF844, 0x9CE8, 0xF845, 0x9CE9, 0xF846, 0x9CEA, 0xF847,
+ 0x9CEB, 0xF848, 0x9CEC, 0xF849, 0x9CED, 0xF84A, 0x9CEE, 0xF84B, 0x9CEF, 0xF84C, 0x9CF0, 0xF84D, 0x9CF1, 0xF84E, 0x9CF2, 0xF84F,
+ 0x9CF3, 0xF850, 0x9CF4, 0xF851, 0x9CF5, 0xF852, 0x9CF6, 0xF853, 0x9CF7, 0xF854, 0x9CF8, 0xF855, 0x9CF9, 0xF856, 0x9CFA, 0xF857,
+ 0x9CFB, 0xF858, 0x9CFC, 0xF859, 0x9CFD, 0xF85A, 0x9CFE, 0xF85B, 0x9CFF, 0xF85C, 0x9D00, 0xF85D, 0x9D01, 0xF85E, 0x9D02, 0xF85F,
+ 0x9D03, 0xF860, 0x9D04, 0xF861, 0x9D05, 0xF862, 0x9D06, 0xF863, 0x9D07, 0xF864, 0x9D08, 0xF865, 0x9D09, 0xF866, 0x9D0A, 0xF867,
+ 0x9D0B, 0xF868, 0x9D0C, 0xF869, 0x9D0D, 0xF86A, 0x9D0E, 0xF86B, 0x9D0F, 0xF86C, 0x9D10, 0xF86D, 0x9D11, 0xF86E, 0x9D12, 0xF86F,
+ 0x9D13, 0xF870, 0x9D14, 0xF871, 0x9D15, 0xF872, 0x9D16, 0xF873, 0x9D17, 0xF874, 0x9D18, 0xF875, 0x9D19, 0xF876, 0x9D1A, 0xF877,
+ 0x9D1B, 0xF878, 0x9D1C, 0xF879, 0x9D1D, 0xF87A, 0x9D1E, 0xF87B, 0x9D1F, 0xF87C, 0x9D20, 0xF87D, 0x9D21, 0xF87E, 0x9D22, 0xF880,
+ 0x9D23, 0xF881, 0x9D24, 0xF882, 0x9D25, 0xF883, 0x9D26, 0xF884, 0x9D27, 0xF885, 0x9D28, 0xF886, 0x9D29, 0xF887, 0x9D2A, 0xF888,
+ 0x9D2B, 0xF889, 0x9D2C, 0xF88A, 0x9D2D, 0xF88B, 0x9D2E, 0xF88C, 0x9D2F, 0xF88D, 0x9D30, 0xF88E, 0x9D31, 0xF88F, 0x9D32, 0xF890,
+ 0x9D33, 0xF891, 0x9D34, 0xF892, 0x9D35, 0xF893, 0x9D36, 0xF894, 0x9D37, 0xF895, 0x9D38, 0xF896, 0x9D39, 0xF897, 0x9D3A, 0xF898,
+ 0x9D3B, 0xF899, 0x9D3C, 0xF89A, 0x9D3D, 0xF89B, 0x9D3E, 0xF89C, 0x9D3F, 0xF89D, 0x9D40, 0xF89E, 0x9D41, 0xF89F, 0x9D42, 0xF8A0,
+ 0x9D43, 0xF940, 0x9D44, 0xF941, 0x9D45, 0xF942, 0x9D46, 0xF943, 0x9D47, 0xF944, 0x9D48, 0xF945, 0x9D49, 0xF946, 0x9D4A, 0xF947,
+ 0x9D4B, 0xF948, 0x9D4C, 0xF949, 0x9D4D, 0xF94A, 0x9D4E, 0xF94B, 0x9D4F, 0xF94C, 0x9D50, 0xF94D, 0x9D51, 0xF94E, 0x9D52, 0xF94F,
+ 0x9D53, 0xF950, 0x9D54, 0xF951, 0x9D55, 0xF952, 0x9D56, 0xF953, 0x9D57, 0xF954, 0x9D58, 0xF955, 0x9D59, 0xF956, 0x9D5A, 0xF957,
+ 0x9D5B, 0xF958, 0x9D5C, 0xF959, 0x9D5D, 0xF95A, 0x9D5E, 0xF95B, 0x9D5F, 0xF95C, 0x9D60, 0xF95D, 0x9D61, 0xF95E, 0x9D62, 0xF95F,
+ 0x9D63, 0xF960, 0x9D64, 0xF961, 0x9D65, 0xF962, 0x9D66, 0xF963, 0x9D67, 0xF964, 0x9D68, 0xF965, 0x9D69, 0xF966, 0x9D6A, 0xF967,
+ 0x9D6B, 0xF968, 0x9D6C, 0xF969, 0x9D6D, 0xF96A, 0x9D6E, 0xF96B, 0x9D6F, 0xF96C, 0x9D70, 0xF96D, 0x9D71, 0xF96E, 0x9D72, 0xF96F,
+ 0x9D73, 0xF970, 0x9D74, 0xF971, 0x9D75, 0xF972, 0x9D76, 0xF973, 0x9D77, 0xF974, 0x9D78, 0xF975, 0x9D79, 0xF976, 0x9D7A, 0xF977,
+ 0x9D7B, 0xF978, 0x9D7C, 0xF979, 0x9D7D, 0xF97A, 0x9D7E, 0xF97B, 0x9D7F, 0xF97C, 0x9D80, 0xF97D, 0x9D81, 0xF97E, 0x9D82, 0xF980,
+ 0x9D83, 0xF981, 0x9D84, 0xF982, 0x9D85, 0xF983, 0x9D86, 0xF984, 0x9D87, 0xF985, 0x9D88, 0xF986, 0x9D89, 0xF987, 0x9D8A, 0xF988,
+ 0x9D8B, 0xF989, 0x9D8C, 0xF98A, 0x9D8D, 0xF98B, 0x9D8E, 0xF98C, 0x9D8F, 0xF98D, 0x9D90, 0xF98E, 0x9D91, 0xF98F, 0x9D92, 0xF990,
+ 0x9D93, 0xF991, 0x9D94, 0xF992, 0x9D95, 0xF993, 0x9D96, 0xF994, 0x9D97, 0xF995, 0x9D98, 0xF996, 0x9D99, 0xF997, 0x9D9A, 0xF998,
+ 0x9D9B, 0xF999, 0x9D9C, 0xF99A, 0x9D9D, 0xF99B, 0x9D9E, 0xF99C, 0x9D9F, 0xF99D, 0x9DA0, 0xF99E, 0x9DA1, 0xF99F, 0x9DA2, 0xF9A0,
+ 0x9DA3, 0xFA40, 0x9DA4, 0xFA41, 0x9DA5, 0xFA42, 0x9DA6, 0xFA43, 0x9DA7, 0xFA44, 0x9DA8, 0xFA45, 0x9DA9, 0xFA46, 0x9DAA, 0xFA47,
+ 0x9DAB, 0xFA48, 0x9DAC, 0xFA49, 0x9DAD, 0xFA4A, 0x9DAE, 0xFA4B, 0x9DAF, 0xFA4C, 0x9DB0, 0xFA4D, 0x9DB1, 0xFA4E, 0x9DB2, 0xFA4F,
+ 0x9DB3, 0xFA50, 0x9DB4, 0xFA51, 0x9DB5, 0xFA52, 0x9DB6, 0xFA53, 0x9DB7, 0xFA54, 0x9DB8, 0xFA55, 0x9DB9, 0xFA56, 0x9DBA, 0xFA57,
+ 0x9DBB, 0xFA58, 0x9DBC, 0xFA59, 0x9DBD, 0xFA5A, 0x9DBE, 0xFA5B, 0x9DBF, 0xFA5C, 0x9DC0, 0xFA5D, 0x9DC1, 0xFA5E, 0x9DC2, 0xFA5F,
+ 0x9DC3, 0xFA60, 0x9DC4, 0xFA61, 0x9DC5, 0xFA62, 0x9DC6, 0xFA63, 0x9DC7, 0xFA64, 0x9DC8, 0xFA65, 0x9DC9, 0xFA66, 0x9DCA, 0xFA67,
+ 0x9DCB, 0xFA68, 0x9DCC, 0xFA69, 0x9DCD, 0xFA6A, 0x9DCE, 0xFA6B, 0x9DCF, 0xFA6C, 0x9DD0, 0xFA6D, 0x9DD1, 0xFA6E, 0x9DD2, 0xFA6F,
+ 0x9DD3, 0xFA70, 0x9DD4, 0xFA71, 0x9DD5, 0xFA72, 0x9DD6, 0xFA73, 0x9DD7, 0xFA74, 0x9DD8, 0xFA75, 0x9DD9, 0xFA76, 0x9DDA, 0xFA77,
+ 0x9DDB, 0xFA78, 0x9DDC, 0xFA79, 0x9DDD, 0xFA7A, 0x9DDE, 0xFA7B, 0x9DDF, 0xFA7C, 0x9DE0, 0xFA7D, 0x9DE1, 0xFA7E, 0x9DE2, 0xFA80,
+ 0x9DE3, 0xFA81, 0x9DE4, 0xFA82, 0x9DE5, 0xFA83, 0x9DE6, 0xFA84, 0x9DE7, 0xFA85, 0x9DE8, 0xFA86, 0x9DE9, 0xFA87, 0x9DEA, 0xFA88,
+ 0x9DEB, 0xFA89, 0x9DEC, 0xFA8A, 0x9DED, 0xFA8B, 0x9DEE, 0xFA8C, 0x9DEF, 0xFA8D, 0x9DF0, 0xFA8E, 0x9DF1, 0xFA8F, 0x9DF2, 0xFA90,
+ 0x9DF3, 0xFA91, 0x9DF4, 0xFA92, 0x9DF5, 0xFA93, 0x9DF6, 0xFA94, 0x9DF7, 0xFA95, 0x9DF8, 0xFA96, 0x9DF9, 0xFA97, 0x9DFA, 0xFA98,
+ 0x9DFB, 0xFA99, 0x9DFC, 0xFA9A, 0x9DFD, 0xFA9B, 0x9DFE, 0xFA9C, 0x9DFF, 0xFA9D, 0x9E00, 0xFA9E, 0x9E01, 0xFA9F, 0x9E02, 0xFAA0,
+ 0x9E03, 0xFB40, 0x9E04, 0xFB41, 0x9E05, 0xFB42, 0x9E06, 0xFB43, 0x9E07, 0xFB44, 0x9E08, 0xFB45, 0x9E09, 0xFB46, 0x9E0A, 0xFB47,
+ 0x9E0B, 0xFB48, 0x9E0C, 0xFB49, 0x9E0D, 0xFB4A, 0x9E0E, 0xFB4B, 0x9E0F, 0xFB4C, 0x9E10, 0xFB4D, 0x9E11, 0xFB4E, 0x9E12, 0xFB4F,
+ 0x9E13, 0xFB50, 0x9E14, 0xFB51, 0x9E15, 0xFB52, 0x9E16, 0xFB53, 0x9E17, 0xFB54, 0x9E18, 0xFB55, 0x9E19, 0xFB56, 0x9E1A, 0xFB57,
+ 0x9E1B, 0xFB58, 0x9E1C, 0xFB59, 0x9E1D, 0xFB5A, 0x9E1E, 0xFB5B, 0x9E1F, 0xC4F1, 0x9E20, 0xF0AF, 0x9E21, 0xBCA6, 0x9E22, 0xF0B0,
+ 0x9E23, 0xC3F9, 0x9E24, 0xFB5C, 0x9E25, 0xC5B8, 0x9E26, 0xD1BB, 0x9E27, 0xFB5D, 0x9E28, 0xF0B1, 0x9E29, 0xF0B2, 0x9E2A, 0xF0B3,
+ 0x9E2B, 0xF0B4, 0x9E2C, 0xF0B5, 0x9E2D, 0xD1BC, 0x9E2E, 0xFB5E, 0x9E2F, 0xD1EC, 0x9E30, 0xFB5F, 0x9E31, 0xF0B7, 0x9E32, 0xF0B6,
+ 0x9E33, 0xD4A7, 0x9E34, 0xFB60, 0x9E35, 0xCDD2, 0x9E36, 0xF0B8, 0x9E37, 0xF0BA, 0x9E38, 0xF0B9, 0x9E39, 0xF0BB, 0x9E3A, 0xF0BC,
+ 0x9E3B, 0xFB61, 0x9E3C, 0xFB62, 0x9E3D, 0xB8EB, 0x9E3E, 0xF0BD, 0x9E3F, 0xBAE8, 0x9E40, 0xFB63, 0x9E41, 0xF0BE, 0x9E42, 0xF0BF,
+ 0x9E43, 0xBEE9, 0x9E44, 0xF0C0, 0x9E45, 0xB6EC, 0x9E46, 0xF0C1, 0x9E47, 0xF0C2, 0x9E48, 0xF0C3, 0x9E49, 0xF0C4, 0x9E4A, 0xC8B5,
+ 0x9E4B, 0xF0C5, 0x9E4C, 0xF0C6, 0x9E4D, 0xFB64, 0x9E4E, 0xF0C7, 0x9E4F, 0xC5F4, 0x9E50, 0xFB65, 0x9E51, 0xF0C8, 0x9E52, 0xFB66,
+ 0x9E53, 0xFB67, 0x9E54, 0xFB68, 0x9E55, 0xF0C9, 0x9E56, 0xFB69, 0x9E57, 0xF0CA, 0x9E58, 0xF7BD, 0x9E59, 0xFB6A, 0x9E5A, 0xF0CB,
+ 0x9E5B, 0xF0CC, 0x9E5C, 0xF0CD, 0x9E5D, 0xFB6B, 0x9E5E, 0xF0CE, 0x9E5F, 0xFB6C, 0x9E60, 0xFB6D, 0x9E61, 0xFB6E, 0x9E62, 0xFB6F,
+ 0x9E63, 0xF0CF, 0x9E64, 0xBAD7, 0x9E65, 0xFB70, 0x9E66, 0xF0D0, 0x9E67, 0xF0D1, 0x9E68, 0xF0D2, 0x9E69, 0xF0D3, 0x9E6A, 0xF0D4,
+ 0x9E6B, 0xF0D5, 0x9E6C, 0xF0D6, 0x9E6D, 0xF0D8, 0x9E6E, 0xFB71, 0x9E6F, 0xFB72, 0x9E70, 0xD3A5, 0x9E71, 0xF0D7, 0x9E72, 0xFB73,
+ 0x9E73, 0xF0D9, 0x9E74, 0xFB74, 0x9E75, 0xFB75, 0x9E76, 0xFB76, 0x9E77, 0xFB77, 0x9E78, 0xFB78, 0x9E79, 0xFB79, 0x9E7A, 0xFB7A,
+ 0x9E7B, 0xFB7B, 0x9E7C, 0xFB7C, 0x9E7D, 0xFB7D, 0x9E7E, 0xF5BA, 0x9E7F, 0xC2B9, 0x9E80, 0xFB7E, 0x9E81, 0xFB80, 0x9E82, 0xF7E4,
+ 0x9E83, 0xFB81, 0x9E84, 0xFB82, 0x9E85, 0xFB83, 0x9E86, 0xFB84, 0x9E87, 0xF7E5, 0x9E88, 0xF7E6, 0x9E89, 0xFB85, 0x9E8A, 0xFB86,
+ 0x9E8B, 0xF7E7, 0x9E8C, 0xFB87, 0x9E8D, 0xFB88, 0x9E8E, 0xFB89, 0x9E8F, 0xFB8A, 0x9E90, 0xFB8B, 0x9E91, 0xFB8C, 0x9E92, 0xF7E8,
+ 0x9E93, 0xC2B4, 0x9E94, 0xFB8D, 0x9E95, 0xFB8E, 0x9E96, 0xFB8F, 0x9E97, 0xFB90, 0x9E98, 0xFB91, 0x9E99, 0xFB92, 0x9E9A, 0xFB93,
+ 0x9E9B, 0xFB94, 0x9E9C, 0xFB95, 0x9E9D, 0xF7EA, 0x9E9E, 0xFB96, 0x9E9F, 0xF7EB, 0x9EA0, 0xFB97, 0x9EA1, 0xFB98, 0x9EA2, 0xFB99,
+ 0x9EA3, 0xFB9A, 0x9EA4, 0xFB9B, 0x9EA5, 0xFB9C, 0x9EA6, 0xC2F3, 0x9EA7, 0xFB9D, 0x9EA8, 0xFB9E, 0x9EA9, 0xFB9F, 0x9EAA, 0xFBA0,
+ 0x9EAB, 0xFC40, 0x9EAC, 0xFC41, 0x9EAD, 0xFC42, 0x9EAE, 0xFC43, 0x9EAF, 0xFC44, 0x9EB0, 0xFC45, 0x9EB1, 0xFC46, 0x9EB2, 0xFC47,
+ 0x9EB3, 0xFC48, 0x9EB4, 0xF4F0, 0x9EB5, 0xFC49, 0x9EB6, 0xFC4A, 0x9EB7, 0xFC4B, 0x9EB8, 0xF4EF, 0x9EB9, 0xFC4C, 0x9EBA, 0xFC4D,
+ 0x9EBB, 0xC2E9, 0x9EBC, 0xFC4E, 0x9EBD, 0xF7E1, 0x9EBE, 0xF7E2, 0x9EBF, 0xFC4F, 0x9EC0, 0xFC50, 0x9EC1, 0xFC51, 0x9EC2, 0xFC52,
+ 0x9EC3, 0xFC53, 0x9EC4, 0xBBC6, 0x9EC5, 0xFC54, 0x9EC6, 0xFC55, 0x9EC7, 0xFC56, 0x9EC8, 0xFC57, 0x9EC9, 0xD9E4, 0x9ECA, 0xFC58,
+ 0x9ECB, 0xFC59, 0x9ECC, 0xFC5A, 0x9ECD, 0xCAF2, 0x9ECE, 0xC0E8, 0x9ECF, 0xF0A4, 0x9ED0, 0xFC5B, 0x9ED1, 0xBADA, 0x9ED2, 0xFC5C,
+ 0x9ED3, 0xFC5D, 0x9ED4, 0xC7AD, 0x9ED5, 0xFC5E, 0x9ED6, 0xFC5F, 0x9ED7, 0xFC60, 0x9ED8, 0xC4AC, 0x9ED9, 0xFC61, 0x9EDA, 0xFC62,
+ 0x9EDB, 0xF7EC, 0x9EDC, 0xF7ED, 0x9EDD, 0xF7EE, 0x9EDE, 0xFC63, 0x9EDF, 0xF7F0, 0x9EE0, 0xF7EF, 0x9EE1, 0xFC64, 0x9EE2, 0xF7F1,
+ 0x9EE3, 0xFC65, 0x9EE4, 0xFC66, 0x9EE5, 0xF7F4, 0x9EE6, 0xFC67, 0x9EE7, 0xF7F3, 0x9EE8, 0xFC68, 0x9EE9, 0xF7F2, 0x9EEA, 0xF7F5,
+ 0x9EEB, 0xFC69, 0x9EEC, 0xFC6A, 0x9EED, 0xFC6B, 0x9EEE, 0xFC6C, 0x9EEF, 0xF7F6, 0x9EF0, 0xFC6D, 0x9EF1, 0xFC6E, 0x9EF2, 0xFC6F,
+ 0x9EF3, 0xFC70, 0x9EF4, 0xFC71, 0x9EF5, 0xFC72, 0x9EF6, 0xFC73, 0x9EF7, 0xFC74, 0x9EF8, 0xFC75, 0x9EF9, 0xEDE9, 0x9EFA, 0xFC76,
+ 0x9EFB, 0xEDEA, 0x9EFC, 0xEDEB, 0x9EFD, 0xFC77, 0x9EFE, 0xF6BC, 0x9EFF, 0xFC78, 0x9F00, 0xFC79, 0x9F01, 0xFC7A, 0x9F02, 0xFC7B,
+ 0x9F03, 0xFC7C, 0x9F04, 0xFC7D, 0x9F05, 0xFC7E, 0x9F06, 0xFC80, 0x9F07, 0xFC81, 0x9F08, 0xFC82, 0x9F09, 0xFC83, 0x9F0A, 0xFC84,
+ 0x9F0B, 0xF6BD, 0x9F0C, 0xFC85, 0x9F0D, 0xF6BE, 0x9F0E, 0xB6A6, 0x9F0F, 0xFC86, 0x9F10, 0xD8BE, 0x9F11, 0xFC87, 0x9F12, 0xFC88,
+ 0x9F13, 0xB9C4, 0x9F14, 0xFC89, 0x9F15, 0xFC8A, 0x9F16, 0xFC8B, 0x9F17, 0xD8BB, 0x9F18, 0xFC8C, 0x9F19, 0xDCB1, 0x9F1A, 0xFC8D,
+ 0x9F1B, 0xFC8E, 0x9F1C, 0xFC8F, 0x9F1D, 0xFC90, 0x9F1E, 0xFC91, 0x9F1F, 0xFC92, 0x9F20, 0xCAF3, 0x9F21, 0xFC93, 0x9F22, 0xF7F7,
+ 0x9F23, 0xFC94, 0x9F24, 0xFC95, 0x9F25, 0xFC96, 0x9F26, 0xFC97, 0x9F27, 0xFC98, 0x9F28, 0xFC99, 0x9F29, 0xFC9A, 0x9F2A, 0xFC9B,
+ 0x9F2B, 0xFC9C, 0x9F2C, 0xF7F8, 0x9F2D, 0xFC9D, 0x9F2E, 0xFC9E, 0x9F2F, 0xF7F9, 0x9F30, 0xFC9F, 0x9F31, 0xFCA0, 0x9F32, 0xFD40,
+ 0x9F33, 0xFD41, 0x9F34, 0xFD42, 0x9F35, 0xFD43, 0x9F36, 0xFD44, 0x9F37, 0xF7FB, 0x9F38, 0xFD45, 0x9F39, 0xF7FA, 0x9F3A, 0xFD46,
+ 0x9F3B, 0xB1C7, 0x9F3C, 0xFD47, 0x9F3D, 0xF7FC, 0x9F3E, 0xF7FD, 0x9F3F, 0xFD48, 0x9F40, 0xFD49, 0x9F41, 0xFD4A, 0x9F42, 0xFD4B,
+ 0x9F43, 0xFD4C, 0x9F44, 0xF7FE, 0x9F45, 0xFD4D, 0x9F46, 0xFD4E, 0x9F47, 0xFD4F, 0x9F48, 0xFD50, 0x9F49, 0xFD51, 0x9F4A, 0xFD52,
+ 0x9F4B, 0xFD53, 0x9F4C, 0xFD54, 0x9F4D, 0xFD55, 0x9F4E, 0xFD56, 0x9F4F, 0xFD57, 0x9F50, 0xC6EB, 0x9F51, 0xECB4, 0x9F52, 0xFD58,
+ 0x9F53, 0xFD59, 0x9F54, 0xFD5A, 0x9F55, 0xFD5B, 0x9F56, 0xFD5C, 0x9F57, 0xFD5D, 0x9F58, 0xFD5E, 0x9F59, 0xFD5F, 0x9F5A, 0xFD60,
+ 0x9F5B, 0xFD61, 0x9F5C, 0xFD62, 0x9F5D, 0xFD63, 0x9F5E, 0xFD64, 0x9F5F, 0xFD65, 0x9F60, 0xFD66, 0x9F61, 0xFD67, 0x9F62, 0xFD68,
+ 0x9F63, 0xFD69, 0x9F64, 0xFD6A, 0x9F65, 0xFD6B, 0x9F66, 0xFD6C, 0x9F67, 0xFD6D, 0x9F68, 0xFD6E, 0x9F69, 0xFD6F, 0x9F6A, 0xFD70,
+ 0x9F6B, 0xFD71, 0x9F6C, 0xFD72, 0x9F6D, 0xFD73, 0x9F6E, 0xFD74, 0x9F6F, 0xFD75, 0x9F70, 0xFD76, 0x9F71, 0xFD77, 0x9F72, 0xFD78,
+ 0x9F73, 0xFD79, 0x9F74, 0xFD7A, 0x9F75, 0xFD7B, 0x9F76, 0xFD7C, 0x9F77, 0xFD7D, 0x9F78, 0xFD7E, 0x9F79, 0xFD80, 0x9F7A, 0xFD81,
+ 0x9F7B, 0xFD82, 0x9F7C, 0xFD83, 0x9F7D, 0xFD84, 0x9F7E, 0xFD85, 0x9F7F, 0xB3DD, 0x9F80, 0xF6B3, 0x9F81, 0xFD86, 0x9F82, 0xFD87,
+ 0x9F83, 0xF6B4, 0x9F84, 0xC1E4, 0x9F85, 0xF6B5, 0x9F86, 0xF6B6, 0x9F87, 0xF6B7, 0x9F88, 0xF6B8, 0x9F89, 0xF6B9, 0x9F8A, 0xF6BA,
+ 0x9F8B, 0xC8A3, 0x9F8C, 0xF6BB, 0x9F8D, 0xFD88, 0x9F8E, 0xFD89, 0x9F8F, 0xFD8A, 0x9F90, 0xFD8B, 0x9F91, 0xFD8C, 0x9F92, 0xFD8D,
+ 0x9F93, 0xFD8E, 0x9F94, 0xFD8F, 0x9F95, 0xFD90, 0x9F96, 0xFD91, 0x9F97, 0xFD92, 0x9F98, 0xFD93, 0x9F99, 0xC1FA, 0x9F9A, 0xB9A8,
+ 0x9F9B, 0xEDE8, 0x9F9C, 0xFD94, 0x9F9D, 0xFD95, 0x9F9E, 0xFD96, 0x9F9F, 0xB9EA, 0x9FA0, 0xD9DF, 0x9FA1, 0xFD97, 0x9FA2, 0xFD98,
+ 0x9FA3, 0xFD99, 0x9FA4, 0xFD9A, 0x9FA5, 0xFD9B, 0xF92C, 0xFD9C, 0xF979, 0xFD9D, 0xF995, 0xFD9E, 0xF9E7, 0xFD9F, 0xF9F1, 0xFDA0,
+ 0xFA0C, 0xFE40, 0xFA0D, 0xFE41, 0xFA0E, 0xFE42, 0xFA0F, 0xFE43, 0xFA11, 0xFE44, 0xFA13, 0xFE45, 0xFA14, 0xFE46, 0xFA18, 0xFE47,
+ 0xFA1F, 0xFE48, 0xFA20, 0xFE49, 0xFA21, 0xFE4A, 0xFA23, 0xFE4B, 0xFA24, 0xFE4C, 0xFA27, 0xFE4D, 0xFA28, 0xFE4E, 0xFA29, 0xFE4F,
+ 0xFE30, 0xA955, 0xFE31, 0xA6F2, 0xFE33, 0xA6F4, 0xFE34, 0xA6F5, 0xFE35, 0xA6E0, 0xFE36, 0xA6E1, 0xFE37, 0xA6F0, 0xFE38, 0xA6F1,
+ 0xFE39, 0xA6E2, 0xFE3A, 0xA6E3, 0xFE3B, 0xA6EE, 0xFE3C, 0xA6EF, 0xFE3D, 0xA6E6, 0xFE3E, 0xA6E7, 0xFE3F, 0xA6E4, 0xFE40, 0xA6E5,
+ 0xFE41, 0xA6E8, 0xFE42, 0xA6E9, 0xFE43, 0xA6EA, 0xFE44, 0xA6EB, 0xFE49, 0xA968, 0xFE4A, 0xA969, 0xFE4B, 0xA96A, 0xFE4C, 0xA96B,
+ 0xFE4D, 0xA96C, 0xFE4E, 0xA96D, 0xFE4F, 0xA96E, 0xFE50, 0xA96F, 0xFE51, 0xA970, 0xFE52, 0xA971, 0xFE54, 0xA972, 0xFE55, 0xA973,
+ 0xFE56, 0xA974, 0xFE57, 0xA975, 0xFE59, 0xA976, 0xFE5A, 0xA977, 0xFE5B, 0xA978, 0xFE5C, 0xA979, 0xFE5D, 0xA97A, 0xFE5E, 0xA97B,
+ 0xFE5F, 0xA97C, 0xFE60, 0xA97D, 0xFE61, 0xA97E, 0xFE62, 0xA980, 0xFE63, 0xA981, 0xFE64, 0xA982, 0xFE65, 0xA983, 0xFE66, 0xA984,
+ 0xFE68, 0xA985, 0xFE69, 0xA986, 0xFE6A, 0xA987, 0xFE6B, 0xA988, 0xFF01, 0xA3A1, 0xFF02, 0xA3A2, 0xFF03, 0xA3A3, 0xFF04, 0xA1E7,
+ 0xFF05, 0xA3A5, 0xFF06, 0xA3A6, 0xFF07, 0xA3A7, 0xFF08, 0xA3A8, 0xFF09, 0xA3A9, 0xFF0A, 0xA3AA, 0xFF0B, 0xA3AB, 0xFF0C, 0xA3AC,
+ 0xFF0D, 0xA3AD, 0xFF0E, 0xA3AE, 0xFF0F, 0xA3AF, 0xFF10, 0xA3B0, 0xFF11, 0xA3B1, 0xFF12, 0xA3B2, 0xFF13, 0xA3B3, 0xFF14, 0xA3B4,
+ 0xFF15, 0xA3B5, 0xFF16, 0xA3B6, 0xFF17, 0xA3B7, 0xFF18, 0xA3B8, 0xFF19, 0xA3B9, 0xFF1A, 0xA3BA, 0xFF1B, 0xA3BB, 0xFF1C, 0xA3BC,
+ 0xFF1D, 0xA3BD, 0xFF1E, 0xA3BE, 0xFF1F, 0xA3BF, 0xFF20, 0xA3C0, 0xFF21, 0xA3C1, 0xFF22, 0xA3C2, 0xFF23, 0xA3C3, 0xFF24, 0xA3C4,
+ 0xFF25, 0xA3C5, 0xFF26, 0xA3C6, 0xFF27, 0xA3C7, 0xFF28, 0xA3C8, 0xFF29, 0xA3C9, 0xFF2A, 0xA3CA, 0xFF2B, 0xA3CB, 0xFF2C, 0xA3CC,
+ 0xFF2D, 0xA3CD, 0xFF2E, 0xA3CE, 0xFF2F, 0xA3CF, 0xFF30, 0xA3D0, 0xFF31, 0xA3D1, 0xFF32, 0xA3D2, 0xFF33, 0xA3D3, 0xFF34, 0xA3D4,
+ 0xFF35, 0xA3D5, 0xFF36, 0xA3D6, 0xFF37, 0xA3D7, 0xFF38, 0xA3D8, 0xFF39, 0xA3D9, 0xFF3A, 0xA3DA, 0xFF3B, 0xA3DB, 0xFF3C, 0xA3DC,
+ 0xFF3D, 0xA3DD, 0xFF3E, 0xA3DE, 0xFF3F, 0xA3DF, 0xFF40, 0xA3E0, 0xFF41, 0xA3E1, 0xFF42, 0xA3E2, 0xFF43, 0xA3E3, 0xFF44, 0xA3E4,
+ 0xFF45, 0xA3E5, 0xFF46, 0xA3E6, 0xFF47, 0xA3E7, 0xFF48, 0xA3E8, 0xFF49, 0xA3E9, 0xFF4A, 0xA3EA, 0xFF4B, 0xA3EB, 0xFF4C, 0xA3EC,
+ 0xFF4D, 0xA3ED, 0xFF4E, 0xA3EE, 0xFF4F, 0xA3EF, 0xFF50, 0xA3F0, 0xFF51, 0xA3F1, 0xFF52, 0xA3F2, 0xFF53, 0xA3F3, 0xFF54, 0xA3F4,
+ 0xFF55, 0xA3F5, 0xFF56, 0xA3F6, 0xFF57, 0xA3F7, 0xFF58, 0xA3F8, 0xFF59, 0xA3F9, 0xFF5A, 0xA3FA, 0xFF5B, 0xA3FB, 0xFF5C, 0xA3FC,
+ 0xFF5D, 0xA3FD, 0xFF5E, 0xA1AB, 0xFFE0, 0xA1E9, 0xFFE1, 0xA1EA, 0xFFE2, 0xA956, 0xFFE3, 0xA3FE, 0xFFE4, 0xA957, 0xFFE5, 0xA3A4,
+ 0, 0
+};
+
+static const WCHAR oem2uni936[] = { /* GBK --> Unicode pairs */
+ 0x0080, 0x20AC, 0x8140, 0x4E02, 0x8141, 0x4E04, 0x8142, 0x4E05, 0x8143, 0x4E06, 0x8144, 0x4E0F, 0x8145, 0x4E12, 0x8146, 0x4E17,
+ 0x8147, 0x4E1F, 0x8148, 0x4E20, 0x8149, 0x4E21, 0x814A, 0x4E23, 0x814B, 0x4E26, 0x814C, 0x4E29, 0x814D, 0x4E2E, 0x814E, 0x4E2F,
+ 0x814F, 0x4E31, 0x8150, 0x4E33, 0x8151, 0x4E35, 0x8152, 0x4E37, 0x8153, 0x4E3C, 0x8154, 0x4E40, 0x8155, 0x4E41, 0x8156, 0x4E42,
+ 0x8157, 0x4E44, 0x8158, 0x4E46, 0x8159, 0x4E4A, 0x815A, 0x4E51, 0x815B, 0x4E55, 0x815C, 0x4E57, 0x815D, 0x4E5A, 0x815E, 0x4E5B,
+ 0x815F, 0x4E62, 0x8160, 0x4E63, 0x8161, 0x4E64, 0x8162, 0x4E65, 0x8163, 0x4E67, 0x8164, 0x4E68, 0x8165, 0x4E6A, 0x8166, 0x4E6B,
+ 0x8167, 0x4E6C, 0x8168, 0x4E6D, 0x8169, 0x4E6E, 0x816A, 0x4E6F, 0x816B, 0x4E72, 0x816C, 0x4E74, 0x816D, 0x4E75, 0x816E, 0x4E76,
+ 0x816F, 0x4E77, 0x8170, 0x4E78, 0x8171, 0x4E79, 0x8172, 0x4E7A, 0x8173, 0x4E7B, 0x8174, 0x4E7C, 0x8175, 0x4E7D, 0x8176, 0x4E7F,
+ 0x8177, 0x4E80, 0x8178, 0x4E81, 0x8179, 0x4E82, 0x817A, 0x4E83, 0x817B, 0x4E84, 0x817C, 0x4E85, 0x817D, 0x4E87, 0x817E, 0x4E8A,
+ 0x8180, 0x4E90, 0x8181, 0x4E96, 0x8182, 0x4E97, 0x8183, 0x4E99, 0x8184, 0x4E9C, 0x8185, 0x4E9D, 0x8186, 0x4E9E, 0x8187, 0x4EA3,
+ 0x8188, 0x4EAA, 0x8189, 0x4EAF, 0x818A, 0x4EB0, 0x818B, 0x4EB1, 0x818C, 0x4EB4, 0x818D, 0x4EB6, 0x818E, 0x4EB7, 0x818F, 0x4EB8,
+ 0x8190, 0x4EB9, 0x8191, 0x4EBC, 0x8192, 0x4EBD, 0x8193, 0x4EBE, 0x8194, 0x4EC8, 0x8195, 0x4ECC, 0x8196, 0x4ECF, 0x8197, 0x4ED0,
+ 0x8198, 0x4ED2, 0x8199, 0x4EDA, 0x819A, 0x4EDB, 0x819B, 0x4EDC, 0x819C, 0x4EE0, 0x819D, 0x4EE2, 0x819E, 0x4EE6, 0x819F, 0x4EE7,
+ 0x81A0, 0x4EE9, 0x81A1, 0x4EED, 0x81A2, 0x4EEE, 0x81A3, 0x4EEF, 0x81A4, 0x4EF1, 0x81A5, 0x4EF4, 0x81A6, 0x4EF8, 0x81A7, 0x4EF9,
+ 0x81A8, 0x4EFA, 0x81A9, 0x4EFC, 0x81AA, 0x4EFE, 0x81AB, 0x4F00, 0x81AC, 0x4F02, 0x81AD, 0x4F03, 0x81AE, 0x4F04, 0x81AF, 0x4F05,
+ 0x81B0, 0x4F06, 0x81B1, 0x4F07, 0x81B2, 0x4F08, 0x81B3, 0x4F0B, 0x81B4, 0x4F0C, 0x81B5, 0x4F12, 0x81B6, 0x4F13, 0x81B7, 0x4F14,
+ 0x81B8, 0x4F15, 0x81B9, 0x4F16, 0x81BA, 0x4F1C, 0x81BB, 0x4F1D, 0x81BC, 0x4F21, 0x81BD, 0x4F23, 0x81BE, 0x4F28, 0x81BF, 0x4F29,
+ 0x81C0, 0x4F2C, 0x81C1, 0x4F2D, 0x81C2, 0x4F2E, 0x81C3, 0x4F31, 0x81C4, 0x4F33, 0x81C5, 0x4F35, 0x81C6, 0x4F37, 0x81C7, 0x4F39,
+ 0x81C8, 0x4F3B, 0x81C9, 0x4F3E, 0x81CA, 0x4F3F, 0x81CB, 0x4F40, 0x81CC, 0x4F41, 0x81CD, 0x4F42, 0x81CE, 0x4F44, 0x81CF, 0x4F45,
+ 0x81D0, 0x4F47, 0x81D1, 0x4F48, 0x81D2, 0x4F49, 0x81D3, 0x4F4A, 0x81D4, 0x4F4B, 0x81D5, 0x4F4C, 0x81D6, 0x4F52, 0x81D7, 0x4F54,
+ 0x81D8, 0x4F56, 0x81D9, 0x4F61, 0x81DA, 0x4F62, 0x81DB, 0x4F66, 0x81DC, 0x4F68, 0x81DD, 0x4F6A, 0x81DE, 0x4F6B, 0x81DF, 0x4F6D,
+ 0x81E0, 0x4F6E, 0x81E1, 0x4F71, 0x81E2, 0x4F72, 0x81E3, 0x4F75, 0x81E4, 0x4F77, 0x81E5, 0x4F78, 0x81E6, 0x4F79, 0x81E7, 0x4F7A,
+ 0x81E8, 0x4F7D, 0x81E9, 0x4F80, 0x81EA, 0x4F81, 0x81EB, 0x4F82, 0x81EC, 0x4F85, 0x81ED, 0x4F86, 0x81EE, 0x4F87, 0x81EF, 0x4F8A,
+ 0x81F0, 0x4F8C, 0x81F1, 0x4F8E, 0x81F2, 0x4F90, 0x81F3, 0x4F92, 0x81F4, 0x4F93, 0x81F5, 0x4F95, 0x81F6, 0x4F96, 0x81F7, 0x4F98,
+ 0x81F8, 0x4F99, 0x81F9, 0x4F9A, 0x81FA, 0x4F9C, 0x81FB, 0x4F9E, 0x81FC, 0x4F9F, 0x81FD, 0x4FA1, 0x81FE, 0x4FA2, 0x8240, 0x4FA4,
+ 0x8241, 0x4FAB, 0x8242, 0x4FAD, 0x8243, 0x4FB0, 0x8244, 0x4FB1, 0x8245, 0x4FB2, 0x8246, 0x4FB3, 0x8247, 0x4FB4, 0x8248, 0x4FB6,
+ 0x8249, 0x4FB7, 0x824A, 0x4FB8, 0x824B, 0x4FB9, 0x824C, 0x4FBA, 0x824D, 0x4FBB, 0x824E, 0x4FBC, 0x824F, 0x4FBD, 0x8250, 0x4FBE,
+ 0x8251, 0x4FC0, 0x8252, 0x4FC1, 0x8253, 0x4FC2, 0x8254, 0x4FC6, 0x8255, 0x4FC7, 0x8256, 0x4FC8, 0x8257, 0x4FC9, 0x8258, 0x4FCB,
+ 0x8259, 0x4FCC, 0x825A, 0x4FCD, 0x825B, 0x4FD2, 0x825C, 0x4FD3, 0x825D, 0x4FD4, 0x825E, 0x4FD5, 0x825F, 0x4FD6, 0x8260, 0x4FD9,
+ 0x8261, 0x4FDB, 0x8262, 0x4FE0, 0x8263, 0x4FE2, 0x8264, 0x4FE4, 0x8265, 0x4FE5, 0x8266, 0x4FE7, 0x8267, 0x4FEB, 0x8268, 0x4FEC,
+ 0x8269, 0x4FF0, 0x826A, 0x4FF2, 0x826B, 0x4FF4, 0x826C, 0x4FF5, 0x826D, 0x4FF6, 0x826E, 0x4FF7, 0x826F, 0x4FF9, 0x8270, 0x4FFB,
+ 0x8271, 0x4FFC, 0x8272, 0x4FFD, 0x8273, 0x4FFF, 0x8274, 0x5000, 0x8275, 0x5001, 0x8276, 0x5002, 0x8277, 0x5003, 0x8278, 0x5004,
+ 0x8279, 0x5005, 0x827A, 0x5006, 0x827B, 0x5007, 0x827C, 0x5008, 0x827D, 0x5009, 0x827E, 0x500A, 0x8280, 0x500B, 0x8281, 0x500E,
+ 0x8282, 0x5010, 0x8283, 0x5011, 0x8284, 0x5013, 0x8285, 0x5015, 0x8286, 0x5016, 0x8287, 0x5017, 0x8288, 0x501B, 0x8289, 0x501D,
+ 0x828A, 0x501E, 0x828B, 0x5020, 0x828C, 0x5022, 0x828D, 0x5023, 0x828E, 0x5024, 0x828F, 0x5027, 0x8290, 0x502B, 0x8291, 0x502F,
+ 0x8292, 0x5030, 0x8293, 0x5031, 0x8294, 0x5032, 0x8295, 0x5033, 0x8296, 0x5034, 0x8297, 0x5035, 0x8298, 0x5036, 0x8299, 0x5037,
+ 0x829A, 0x5038, 0x829B, 0x5039, 0x829C, 0x503B, 0x829D, 0x503D, 0x829E, 0x503F, 0x829F, 0x5040, 0x82A0, 0x5041, 0x82A1, 0x5042,
+ 0x82A2, 0x5044, 0x82A3, 0x5045, 0x82A4, 0x5046, 0x82A5, 0x5049, 0x82A6, 0x504A, 0x82A7, 0x504B, 0x82A8, 0x504D, 0x82A9, 0x5050,
+ 0x82AA, 0x5051, 0x82AB, 0x5052, 0x82AC, 0x5053, 0x82AD, 0x5054, 0x82AE, 0x5056, 0x82AF, 0x5057, 0x82B0, 0x5058, 0x82B1, 0x5059,
+ 0x82B2, 0x505B, 0x82B3, 0x505D, 0x82B4, 0x505E, 0x82B5, 0x505F, 0x82B6, 0x5060, 0x82B7, 0x5061, 0x82B8, 0x5062, 0x82B9, 0x5063,
+ 0x82BA, 0x5064, 0x82BB, 0x5066, 0x82BC, 0x5067, 0x82BD, 0x5068, 0x82BE, 0x5069, 0x82BF, 0x506A, 0x82C0, 0x506B, 0x82C1, 0x506D,
+ 0x82C2, 0x506E, 0x82C3, 0x506F, 0x82C4, 0x5070, 0x82C5, 0x5071, 0x82C6, 0x5072, 0x82C7, 0x5073, 0x82C8, 0x5074, 0x82C9, 0x5075,
+ 0x82CA, 0x5078, 0x82CB, 0x5079, 0x82CC, 0x507A, 0x82CD, 0x507C, 0x82CE, 0x507D, 0x82CF, 0x5081, 0x82D0, 0x5082, 0x82D1, 0x5083,
+ 0x82D2, 0x5084, 0x82D3, 0x5086, 0x82D4, 0x5087, 0x82D5, 0x5089, 0x82D6, 0x508A, 0x82D7, 0x508B, 0x82D8, 0x508C, 0x82D9, 0x508E,
+ 0x82DA, 0x508F, 0x82DB, 0x5090, 0x82DC, 0x5091, 0x82DD, 0x5092, 0x82DE, 0x5093, 0x82DF, 0x5094, 0x82E0, 0x5095, 0x82E1, 0x5096,
+ 0x82E2, 0x5097, 0x82E3, 0x5098, 0x82E4, 0x5099, 0x82E5, 0x509A, 0x82E6, 0x509B, 0x82E7, 0x509C, 0x82E8, 0x509D, 0x82E9, 0x509E,
+ 0x82EA, 0x509F, 0x82EB, 0x50A0, 0x82EC, 0x50A1, 0x82ED, 0x50A2, 0x82EE, 0x50A4, 0x82EF, 0x50A6, 0x82F0, 0x50AA, 0x82F1, 0x50AB,
+ 0x82F2, 0x50AD, 0x82F3, 0x50AE, 0x82F4, 0x50AF, 0x82F5, 0x50B0, 0x82F6, 0x50B1, 0x82F7, 0x50B3, 0x82F8, 0x50B4, 0x82F9, 0x50B5,
+ 0x82FA, 0x50B6, 0x82FB, 0x50B7, 0x82FC, 0x50B8, 0x82FD, 0x50B9, 0x82FE, 0x50BC, 0x8340, 0x50BD, 0x8341, 0x50BE, 0x8342, 0x50BF,
+ 0x8343, 0x50C0, 0x8344, 0x50C1, 0x8345, 0x50C2, 0x8346, 0x50C3, 0x8347, 0x50C4, 0x8348, 0x50C5, 0x8349, 0x50C6, 0x834A, 0x50C7,
+ 0x834B, 0x50C8, 0x834C, 0x50C9, 0x834D, 0x50CA, 0x834E, 0x50CB, 0x834F, 0x50CC, 0x8350, 0x50CD, 0x8351, 0x50CE, 0x8352, 0x50D0,
+ 0x8353, 0x50D1, 0x8354, 0x50D2, 0x8355, 0x50D3, 0x8356, 0x50D4, 0x8357, 0x50D5, 0x8358, 0x50D7, 0x8359, 0x50D8, 0x835A, 0x50D9,
+ 0x835B, 0x50DB, 0x835C, 0x50DC, 0x835D, 0x50DD, 0x835E, 0x50DE, 0x835F, 0x50DF, 0x8360, 0x50E0, 0x8361, 0x50E1, 0x8362, 0x50E2,
+ 0x8363, 0x50E3, 0x8364, 0x50E4, 0x8365, 0x50E5, 0x8366, 0x50E8, 0x8367, 0x50E9, 0x8368, 0x50EA, 0x8369, 0x50EB, 0x836A, 0x50EF,
+ 0x836B, 0x50F0, 0x836C, 0x50F1, 0x836D, 0x50F2, 0x836E, 0x50F4, 0x836F, 0x50F6, 0x8370, 0x50F7, 0x8371, 0x50F8, 0x8372, 0x50F9,
+ 0x8373, 0x50FA, 0x8374, 0x50FC, 0x8375, 0x50FD, 0x8376, 0x50FE, 0x8377, 0x50FF, 0x8378, 0x5100, 0x8379, 0x5101, 0x837A, 0x5102,
+ 0x837B, 0x5103, 0x837C, 0x5104, 0x837D, 0x5105, 0x837E, 0x5108, 0x8380, 0x5109, 0x8381, 0x510A, 0x8382, 0x510C, 0x8383, 0x510D,
+ 0x8384, 0x510E, 0x8385, 0x510F, 0x8386, 0x5110, 0x8387, 0x5111, 0x8388, 0x5113, 0x8389, 0x5114, 0x838A, 0x5115, 0x838B, 0x5116,
+ 0x838C, 0x5117, 0x838D, 0x5118, 0x838E, 0x5119, 0x838F, 0x511A, 0x8390, 0x511B, 0x8391, 0x511C, 0x8392, 0x511D, 0x8393, 0x511E,
+ 0x8394, 0x511F, 0x8395, 0x5120, 0x8396, 0x5122, 0x8397, 0x5123, 0x8398, 0x5124, 0x8399, 0x5125, 0x839A, 0x5126, 0x839B, 0x5127,
+ 0x839C, 0x5128, 0x839D, 0x5129, 0x839E, 0x512A, 0x839F, 0x512B, 0x83A0, 0x512C, 0x83A1, 0x512D, 0x83A2, 0x512E, 0x83A3, 0x512F,
+ 0x83A4, 0x5130, 0x83A5, 0x5131, 0x83A6, 0x5132, 0x83A7, 0x5133, 0x83A8, 0x5134, 0x83A9, 0x5135, 0x83AA, 0x5136, 0x83AB, 0x5137,
+ 0x83AC, 0x5138, 0x83AD, 0x5139, 0x83AE, 0x513A, 0x83AF, 0x513B, 0x83B0, 0x513C, 0x83B1, 0x513D, 0x83B2, 0x513E, 0x83B3, 0x5142,
+ 0x83B4, 0x5147, 0x83B5, 0x514A, 0x83B6, 0x514C, 0x83B7, 0x514E, 0x83B8, 0x514F, 0x83B9, 0x5150, 0x83BA, 0x5152, 0x83BB, 0x5153,
+ 0x83BC, 0x5157, 0x83BD, 0x5158, 0x83BE, 0x5159, 0x83BF, 0x515B, 0x83C0, 0x515D, 0x83C1, 0x515E, 0x83C2, 0x515F, 0x83C3, 0x5160,
+ 0x83C4, 0x5161, 0x83C5, 0x5163, 0x83C6, 0x5164, 0x83C7, 0x5166, 0x83C8, 0x5167, 0x83C9, 0x5169, 0x83CA, 0x516A, 0x83CB, 0x516F,
+ 0x83CC, 0x5172, 0x83CD, 0x517A, 0x83CE, 0x517E, 0x83CF, 0x517F, 0x83D0, 0x5183, 0x83D1, 0x5184, 0x83D2, 0x5186, 0x83D3, 0x5187,
+ 0x83D4, 0x518A, 0x83D5, 0x518B, 0x83D6, 0x518E, 0x83D7, 0x518F, 0x83D8, 0x5190, 0x83D9, 0x5191, 0x83DA, 0x5193, 0x83DB, 0x5194,
+ 0x83DC, 0x5198, 0x83DD, 0x519A, 0x83DE, 0x519D, 0x83DF, 0x519E, 0x83E0, 0x519F, 0x83E1, 0x51A1, 0x83E2, 0x51A3, 0x83E3, 0x51A6,
+ 0x83E4, 0x51A7, 0x83E5, 0x51A8, 0x83E6, 0x51A9, 0x83E7, 0x51AA, 0x83E8, 0x51AD, 0x83E9, 0x51AE, 0x83EA, 0x51B4, 0x83EB, 0x51B8,
+ 0x83EC, 0x51B9, 0x83ED, 0x51BA, 0x83EE, 0x51BE, 0x83EF, 0x51BF, 0x83F0, 0x51C1, 0x83F1, 0x51C2, 0x83F2, 0x51C3, 0x83F3, 0x51C5,
+ 0x83F4, 0x51C8, 0x83F5, 0x51CA, 0x83F6, 0x51CD, 0x83F7, 0x51CE, 0x83F8, 0x51D0, 0x83F9, 0x51D2, 0x83FA, 0x51D3, 0x83FB, 0x51D4,
+ 0x83FC, 0x51D5, 0x83FD, 0x51D6, 0x83FE, 0x51D7, 0x8440, 0x51D8, 0x8441, 0x51D9, 0x8442, 0x51DA, 0x8443, 0x51DC, 0x8444, 0x51DE,
+ 0x8445, 0x51DF, 0x8446, 0x51E2, 0x8447, 0x51E3, 0x8448, 0x51E5, 0x8449, 0x51E6, 0x844A, 0x51E7, 0x844B, 0x51E8, 0x844C, 0x51E9,
+ 0x844D, 0x51EA, 0x844E, 0x51EC, 0x844F, 0x51EE, 0x8450, 0x51F1, 0x8451, 0x51F2, 0x8452, 0x51F4, 0x8453, 0x51F7, 0x8454, 0x51FE,
+ 0x8455, 0x5204, 0x8456, 0x5205, 0x8457, 0x5209, 0x8458, 0x520B, 0x8459, 0x520C, 0x845A, 0x520F, 0x845B, 0x5210, 0x845C, 0x5213,
+ 0x845D, 0x5214, 0x845E, 0x5215, 0x845F, 0x521C, 0x8460, 0x521E, 0x8461, 0x521F, 0x8462, 0x5221, 0x8463, 0x5222, 0x8464, 0x5223,
+ 0x8465, 0x5225, 0x8466, 0x5226, 0x8467, 0x5227, 0x8468, 0x522A, 0x8469, 0x522C, 0x846A, 0x522F, 0x846B, 0x5231, 0x846C, 0x5232,
+ 0x846D, 0x5234, 0x846E, 0x5235, 0x846F, 0x523C, 0x8470, 0x523E, 0x8471, 0x5244, 0x8472, 0x5245, 0x8473, 0x5246, 0x8474, 0x5247,
+ 0x8475, 0x5248, 0x8476, 0x5249, 0x8477, 0x524B, 0x8478, 0x524E, 0x8479, 0x524F, 0x847A, 0x5252, 0x847B, 0x5253, 0x847C, 0x5255,
+ 0x847D, 0x5257, 0x847E, 0x5258, 0x8480, 0x5259, 0x8481, 0x525A, 0x8482, 0x525B, 0x8483, 0x525D, 0x8484, 0x525F, 0x8485, 0x5260,
+ 0x8486, 0x5262, 0x8487, 0x5263, 0x8488, 0x5264, 0x8489, 0x5266, 0x848A, 0x5268, 0x848B, 0x526B, 0x848C, 0x526C, 0x848D, 0x526D,
+ 0x848E, 0x526E, 0x848F, 0x5270, 0x8490, 0x5271, 0x8491, 0x5273, 0x8492, 0x5274, 0x8493, 0x5275, 0x8494, 0x5276, 0x8495, 0x5277,
+ 0x8496, 0x5278, 0x8497, 0x5279, 0x8498, 0x527A, 0x8499, 0x527B, 0x849A, 0x527C, 0x849B, 0x527E, 0x849C, 0x5280, 0x849D, 0x5283,
+ 0x849E, 0x5284, 0x849F, 0x5285, 0x84A0, 0x5286, 0x84A1, 0x5287, 0x84A2, 0x5289, 0x84A3, 0x528A, 0x84A4, 0x528B, 0x84A5, 0x528C,
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+ 0xA1B0, 0x201C, 0xA1B1, 0x201D, 0xA1B2, 0x3014, 0xA1B3, 0x3015, 0xA1B4, 0x3008, 0xA1B5, 0x3009, 0xA1B6, 0x300A, 0xA1B7, 0x300B,
+ 0xA1B8, 0x300C, 0xA1B9, 0x300D, 0xA1BA, 0x300E, 0xA1BB, 0x300F, 0xA1BC, 0x3016, 0xA1BD, 0x3017, 0xA1BE, 0x3010, 0xA1BF, 0x3011,
+ 0xA1C0, 0x00B1, 0xA1C1, 0x00D7, 0xA1C2, 0x00F7, 0xA1C3, 0x2236, 0xA1C4, 0x2227, 0xA1C5, 0x2228, 0xA1C6, 0x2211, 0xA1C7, 0x220F,
+ 0xA1C8, 0x222A, 0xA1C9, 0x2229, 0xA1CA, 0x2208, 0xA1CB, 0x2237, 0xA1CC, 0x221A, 0xA1CD, 0x22A5, 0xA1CE, 0x2225, 0xA1CF, 0x2220,
+ 0xA1D0, 0x2312, 0xA1D1, 0x2299, 0xA1D2, 0x222B, 0xA1D3, 0x222E, 0xA1D4, 0x2261, 0xA1D5, 0x224C, 0xA1D6, 0x2248, 0xA1D7, 0x223D,
+ 0xA1D8, 0x221D, 0xA1D9, 0x2260, 0xA1DA, 0x226E, 0xA1DB, 0x226F, 0xA1DC, 0x2264, 0xA1DD, 0x2265, 0xA1DE, 0x221E, 0xA1DF, 0x2235,
+ 0xA1E0, 0x2234, 0xA1E1, 0x2642, 0xA1E2, 0x2640, 0xA1E3, 0x00B0, 0xA1E4, 0x2032, 0xA1E5, 0x2033, 0xA1E6, 0x2103, 0xA1E7, 0xFF04,
+ 0xA1E8, 0x00A4, 0xA1E9, 0xFFE0, 0xA1EA, 0xFFE1, 0xA1EB, 0x2030, 0xA1EC, 0x00A7, 0xA1ED, 0x2116, 0xA1EE, 0x2606, 0xA1EF, 0x2605,
+ 0xA1F0, 0x25CB, 0xA1F1, 0x25CF, 0xA1F2, 0x25CE, 0xA1F3, 0x25C7, 0xA1F4, 0x25C6, 0xA1F5, 0x25A1, 0xA1F6, 0x25A0, 0xA1F7, 0x25B3,
+ 0xA1F8, 0x25B2, 0xA1F9, 0x203B, 0xA1FA, 0x2192, 0xA1FB, 0x2190, 0xA1FC, 0x2191, 0xA1FD, 0x2193, 0xA1FE, 0x3013, 0xA2A1, 0x2170,
+ 0xA2A2, 0x2171, 0xA2A3, 0x2172, 0xA2A4, 0x2173, 0xA2A5, 0x2174, 0xA2A6, 0x2175, 0xA2A7, 0x2176, 0xA2A8, 0x2177, 0xA2A9, 0x2178,
+ 0xA2AA, 0x2179, 0xA2B1, 0x2488, 0xA2B2, 0x2489, 0xA2B3, 0x248A, 0xA2B4, 0x248B, 0xA2B5, 0x248C, 0xA2B6, 0x248D, 0xA2B7, 0x248E,
+ 0xA2B8, 0x248F, 0xA2B9, 0x2490, 0xA2BA, 0x2491, 0xA2BB, 0x2492, 0xA2BC, 0x2493, 0xA2BD, 0x2494, 0xA2BE, 0x2495, 0xA2BF, 0x2496,
+ 0xA2C0, 0x2497, 0xA2C1, 0x2498, 0xA2C2, 0x2499, 0xA2C3, 0x249A, 0xA2C4, 0x249B, 0xA2C5, 0x2474, 0xA2C6, 0x2475, 0xA2C7, 0x2476,
+ 0xA2C8, 0x2477, 0xA2C9, 0x2478, 0xA2CA, 0x2479, 0xA2CB, 0x247A, 0xA2CC, 0x247B, 0xA2CD, 0x247C, 0xA2CE, 0x247D, 0xA2CF, 0x247E,
+ 0xA2D0, 0x247F, 0xA2D1, 0x2480, 0xA2D2, 0x2481, 0xA2D3, 0x2482, 0xA2D4, 0x2483, 0xA2D5, 0x2484, 0xA2D6, 0x2485, 0xA2D7, 0x2486,
+ 0xA2D8, 0x2487, 0xA2D9, 0x2460, 0xA2DA, 0x2461, 0xA2DB, 0x2462, 0xA2DC, 0x2463, 0xA2DD, 0x2464, 0xA2DE, 0x2465, 0xA2DF, 0x2466,
+ 0xA2E0, 0x2467, 0xA2E1, 0x2468, 0xA2E2, 0x2469, 0xA2E5, 0x3220, 0xA2E6, 0x3221, 0xA2E7, 0x3222, 0xA2E8, 0x3223, 0xA2E9, 0x3224,
+ 0xA2EA, 0x3225, 0xA2EB, 0x3226, 0xA2EC, 0x3227, 0xA2ED, 0x3228, 0xA2EE, 0x3229, 0xA2F1, 0x2160, 0xA2F2, 0x2161, 0xA2F3, 0x2162,
+ 0xA2F4, 0x2163, 0xA2F5, 0x2164, 0xA2F6, 0x2165, 0xA2F7, 0x2166, 0xA2F8, 0x2167, 0xA2F9, 0x2168, 0xA2FA, 0x2169, 0xA2FB, 0x216A,
+ 0xA2FC, 0x216B, 0xA3A1, 0xFF01, 0xA3A2, 0xFF02, 0xA3A3, 0xFF03, 0xA3A4, 0xFFE5, 0xA3A5, 0xFF05, 0xA3A6, 0xFF06, 0xA3A7, 0xFF07,
+ 0xA3A8, 0xFF08, 0xA3A9, 0xFF09, 0xA3AA, 0xFF0A, 0xA3AB, 0xFF0B, 0xA3AC, 0xFF0C, 0xA3AD, 0xFF0D, 0xA3AE, 0xFF0E, 0xA3AF, 0xFF0F,
+ 0xA3B0, 0xFF10, 0xA3B1, 0xFF11, 0xA3B2, 0xFF12, 0xA3B3, 0xFF13, 0xA3B4, 0xFF14, 0xA3B5, 0xFF15, 0xA3B6, 0xFF16, 0xA3B7, 0xFF17,
+ 0xA3B8, 0xFF18, 0xA3B9, 0xFF19, 0xA3BA, 0xFF1A, 0xA3BB, 0xFF1B, 0xA3BC, 0xFF1C, 0xA3BD, 0xFF1D, 0xA3BE, 0xFF1E, 0xA3BF, 0xFF1F,
+ 0xA3C0, 0xFF20, 0xA3C1, 0xFF21, 0xA3C2, 0xFF22, 0xA3C3, 0xFF23, 0xA3C4, 0xFF24, 0xA3C5, 0xFF25, 0xA3C6, 0xFF26, 0xA3C7, 0xFF27,
+ 0xA3C8, 0xFF28, 0xA3C9, 0xFF29, 0xA3CA, 0xFF2A, 0xA3CB, 0xFF2B, 0xA3CC, 0xFF2C, 0xA3CD, 0xFF2D, 0xA3CE, 0xFF2E, 0xA3CF, 0xFF2F,
+ 0xA3D0, 0xFF30, 0xA3D1, 0xFF31, 0xA3D2, 0xFF32, 0xA3D3, 0xFF33, 0xA3D4, 0xFF34, 0xA3D5, 0xFF35, 0xA3D6, 0xFF36, 0xA3D7, 0xFF37,
+ 0xA3D8, 0xFF38, 0xA3D9, 0xFF39, 0xA3DA, 0xFF3A, 0xA3DB, 0xFF3B, 0xA3DC, 0xFF3C, 0xA3DD, 0xFF3D, 0xA3DE, 0xFF3E, 0xA3DF, 0xFF3F,
+ 0xA3E0, 0xFF40, 0xA3E1, 0xFF41, 0xA3E2, 0xFF42, 0xA3E3, 0xFF43, 0xA3E4, 0xFF44, 0xA3E5, 0xFF45, 0xA3E6, 0xFF46, 0xA3E7, 0xFF47,
+ 0xA3E8, 0xFF48, 0xA3E9, 0xFF49, 0xA3EA, 0xFF4A, 0xA3EB, 0xFF4B, 0xA3EC, 0xFF4C, 0xA3ED, 0xFF4D, 0xA3EE, 0xFF4E, 0xA3EF, 0xFF4F,
+ 0xA3F0, 0xFF50, 0xA3F1, 0xFF51, 0xA3F2, 0xFF52, 0xA3F3, 0xFF53, 0xA3F4, 0xFF54, 0xA3F5, 0xFF55, 0xA3F6, 0xFF56, 0xA3F7, 0xFF57,
+ 0xA3F8, 0xFF58, 0xA3F9, 0xFF59, 0xA3FA, 0xFF5A, 0xA3FB, 0xFF5B, 0xA3FC, 0xFF5C, 0xA3FD, 0xFF5D, 0xA3FE, 0xFFE3, 0xA4A1, 0x3041,
+ 0xA4A2, 0x3042, 0xA4A3, 0x3043, 0xA4A4, 0x3044, 0xA4A5, 0x3045, 0xA4A6, 0x3046, 0xA4A7, 0x3047, 0xA4A8, 0x3048, 0xA4A9, 0x3049,
+ 0xA4AA, 0x304A, 0xA4AB, 0x304B, 0xA4AC, 0x304C, 0xA4AD, 0x304D, 0xA4AE, 0x304E, 0xA4AF, 0x304F, 0xA4B0, 0x3050, 0xA4B1, 0x3051,
+ 0xA4B2, 0x3052, 0xA4B3, 0x3053, 0xA4B4, 0x3054, 0xA4B5, 0x3055, 0xA4B6, 0x3056, 0xA4B7, 0x3057, 0xA4B8, 0x3058, 0xA4B9, 0x3059,
+ 0xA4BA, 0x305A, 0xA4BB, 0x305B, 0xA4BC, 0x305C, 0xA4BD, 0x305D, 0xA4BE, 0x305E, 0xA4BF, 0x305F, 0xA4C0, 0x3060, 0xA4C1, 0x3061,
+ 0xA4C2, 0x3062, 0xA4C3, 0x3063, 0xA4C4, 0x3064, 0xA4C5, 0x3065, 0xA4C6, 0x3066, 0xA4C7, 0x3067, 0xA4C8, 0x3068, 0xA4C9, 0x3069,
+ 0xA4CA, 0x306A, 0xA4CB, 0x306B, 0xA4CC, 0x306C, 0xA4CD, 0x306D, 0xA4CE, 0x306E, 0xA4CF, 0x306F, 0xA4D0, 0x3070, 0xA4D1, 0x3071,
+ 0xA4D2, 0x3072, 0xA4D3, 0x3073, 0xA4D4, 0x3074, 0xA4D5, 0x3075, 0xA4D6, 0x3076, 0xA4D7, 0x3077, 0xA4D8, 0x3078, 0xA4D9, 0x3079,
+ 0xA4DA, 0x307A, 0xA4DB, 0x307B, 0xA4DC, 0x307C, 0xA4DD, 0x307D, 0xA4DE, 0x307E, 0xA4DF, 0x307F, 0xA4E0, 0x3080, 0xA4E1, 0x3081,
+ 0xA4E2, 0x3082, 0xA4E3, 0x3083, 0xA4E4, 0x3084, 0xA4E5, 0x3085, 0xA4E6, 0x3086, 0xA4E7, 0x3087, 0xA4E8, 0x3088, 0xA4E9, 0x3089,
+ 0xA4EA, 0x308A, 0xA4EB, 0x308B, 0xA4EC, 0x308C, 0xA4ED, 0x308D, 0xA4EE, 0x308E, 0xA4EF, 0x308F, 0xA4F0, 0x3090, 0xA4F1, 0x3091,
+ 0xA4F2, 0x3092, 0xA4F3, 0x3093, 0xA5A1, 0x30A1, 0xA5A2, 0x30A2, 0xA5A3, 0x30A3, 0xA5A4, 0x30A4, 0xA5A5, 0x30A5, 0xA5A6, 0x30A6,
+ 0xA5A7, 0x30A7, 0xA5A8, 0x30A8, 0xA5A9, 0x30A9, 0xA5AA, 0x30AA, 0xA5AB, 0x30AB, 0xA5AC, 0x30AC, 0xA5AD, 0x30AD, 0xA5AE, 0x30AE,
+ 0xA5AF, 0x30AF, 0xA5B0, 0x30B0, 0xA5B1, 0x30B1, 0xA5B2, 0x30B2, 0xA5B3, 0x30B3, 0xA5B4, 0x30B4, 0xA5B5, 0x30B5, 0xA5B6, 0x30B6,
+ 0xA5B7, 0x30B7, 0xA5B8, 0x30B8, 0xA5B9, 0x30B9, 0xA5BA, 0x30BA, 0xA5BB, 0x30BB, 0xA5BC, 0x30BC, 0xA5BD, 0x30BD, 0xA5BE, 0x30BE,
+ 0xA5BF, 0x30BF, 0xA5C0, 0x30C0, 0xA5C1, 0x30C1, 0xA5C2, 0x30C2, 0xA5C3, 0x30C3, 0xA5C4, 0x30C4, 0xA5C5, 0x30C5, 0xA5C6, 0x30C6,
+ 0xA5C7, 0x30C7, 0xA5C8, 0x30C8, 0xA5C9, 0x30C9, 0xA5CA, 0x30CA, 0xA5CB, 0x30CB, 0xA5CC, 0x30CC, 0xA5CD, 0x30CD, 0xA5CE, 0x30CE,
+ 0xA5CF, 0x30CF, 0xA5D0, 0x30D0, 0xA5D1, 0x30D1, 0xA5D2, 0x30D2, 0xA5D3, 0x30D3, 0xA5D4, 0x30D4, 0xA5D5, 0x30D5, 0xA5D6, 0x30D6,
+ 0xA5D7, 0x30D7, 0xA5D8, 0x30D8, 0xA5D9, 0x30D9, 0xA5DA, 0x30DA, 0xA5DB, 0x30DB, 0xA5DC, 0x30DC, 0xA5DD, 0x30DD, 0xA5DE, 0x30DE,
+ 0xA5DF, 0x30DF, 0xA5E0, 0x30E0, 0xA5E1, 0x30E1, 0xA5E2, 0x30E2, 0xA5E3, 0x30E3, 0xA5E4, 0x30E4, 0xA5E5, 0x30E5, 0xA5E6, 0x30E6,
+ 0xA5E7, 0x30E7, 0xA5E8, 0x30E8, 0xA5E9, 0x30E9, 0xA5EA, 0x30EA, 0xA5EB, 0x30EB, 0xA5EC, 0x30EC, 0xA5ED, 0x30ED, 0xA5EE, 0x30EE,
+ 0xA5EF, 0x30EF, 0xA5F0, 0x30F0, 0xA5F1, 0x30F1, 0xA5F2, 0x30F2, 0xA5F3, 0x30F3, 0xA5F4, 0x30F4, 0xA5F5, 0x30F5, 0xA5F6, 0x30F6,
+ 0xA6A1, 0x0391, 0xA6A2, 0x0392, 0xA6A3, 0x0393, 0xA6A4, 0x0394, 0xA6A5, 0x0395, 0xA6A6, 0x0396, 0xA6A7, 0x0397, 0xA6A8, 0x0398,
+ 0xA6A9, 0x0399, 0xA6AA, 0x039A, 0xA6AB, 0x039B, 0xA6AC, 0x039C, 0xA6AD, 0x039D, 0xA6AE, 0x039E, 0xA6AF, 0x039F, 0xA6B0, 0x03A0,
+ 0xA6B1, 0x03A1, 0xA6B2, 0x03A3, 0xA6B3, 0x03A4, 0xA6B4, 0x03A5, 0xA6B5, 0x03A6, 0xA6B6, 0x03A7, 0xA6B7, 0x03A8, 0xA6B8, 0x03A9,
+ 0xA6C1, 0x03B1, 0xA6C2, 0x03B2, 0xA6C3, 0x03B3, 0xA6C4, 0x03B4, 0xA6C5, 0x03B5, 0xA6C6, 0x03B6, 0xA6C7, 0x03B7, 0xA6C8, 0x03B8,
+ 0xA6C9, 0x03B9, 0xA6CA, 0x03BA, 0xA6CB, 0x03BB, 0xA6CC, 0x03BC, 0xA6CD, 0x03BD, 0xA6CE, 0x03BE, 0xA6CF, 0x03BF, 0xA6D0, 0x03C0,
+ 0xA6D1, 0x03C1, 0xA6D2, 0x03C3, 0xA6D3, 0x03C4, 0xA6D4, 0x03C5, 0xA6D5, 0x03C6, 0xA6D6, 0x03C7, 0xA6D7, 0x03C8, 0xA6D8, 0x03C9,
+ 0xA6E0, 0xFE35, 0xA6E1, 0xFE36, 0xA6E2, 0xFE39, 0xA6E3, 0xFE3A, 0xA6E4, 0xFE3F, 0xA6E5, 0xFE40, 0xA6E6, 0xFE3D, 0xA6E7, 0xFE3E,
+ 0xA6E8, 0xFE41, 0xA6E9, 0xFE42, 0xA6EA, 0xFE43, 0xA6EB, 0xFE44, 0xA6EE, 0xFE3B, 0xA6EF, 0xFE3C, 0xA6F0, 0xFE37, 0xA6F1, 0xFE38,
+ 0xA6F2, 0xFE31, 0xA6F4, 0xFE33, 0xA6F5, 0xFE34, 0xA7A1, 0x0410, 0xA7A2, 0x0411, 0xA7A3, 0x0412, 0xA7A4, 0x0413, 0xA7A5, 0x0414,
+ 0xA7A6, 0x0415, 0xA7A7, 0x0401, 0xA7A8, 0x0416, 0xA7A9, 0x0417, 0xA7AA, 0x0418, 0xA7AB, 0x0419, 0xA7AC, 0x041A, 0xA7AD, 0x041B,
+ 0xA7AE, 0x041C, 0xA7AF, 0x041D, 0xA7B0, 0x041E, 0xA7B1, 0x041F, 0xA7B2, 0x0420, 0xA7B3, 0x0421, 0xA7B4, 0x0422, 0xA7B5, 0x0423,
+ 0xA7B6, 0x0424, 0xA7B7, 0x0425, 0xA7B8, 0x0426, 0xA7B9, 0x0427, 0xA7BA, 0x0428, 0xA7BB, 0x0429, 0xA7BC, 0x042A, 0xA7BD, 0x042B,
+ 0xA7BE, 0x042C, 0xA7BF, 0x042D, 0xA7C0, 0x042E, 0xA7C1, 0x042F, 0xA7D1, 0x0430, 0xA7D2, 0x0431, 0xA7D3, 0x0432, 0xA7D4, 0x0433,
+ 0xA7D5, 0x0434, 0xA7D6, 0x0435, 0xA7D7, 0x0451, 0xA7D8, 0x0436, 0xA7D9, 0x0437, 0xA7DA, 0x0438, 0xA7DB, 0x0439, 0xA7DC, 0x043A,
+ 0xA7DD, 0x043B, 0xA7DE, 0x043C, 0xA7DF, 0x043D, 0xA7E0, 0x043E, 0xA7E1, 0x043F, 0xA7E2, 0x0440, 0xA7E3, 0x0441, 0xA7E4, 0x0442,
+ 0xA7E5, 0x0443, 0xA7E6, 0x0444, 0xA7E7, 0x0445, 0xA7E8, 0x0446, 0xA7E9, 0x0447, 0xA7EA, 0x0448, 0xA7EB, 0x0449, 0xA7EC, 0x044A,
+ 0xA7ED, 0x044B, 0xA7EE, 0x044C, 0xA7EF, 0x044D, 0xA7F0, 0x044E, 0xA7F1, 0x044F, 0xA840, 0x02CA, 0xA841, 0x02CB, 0xA842, 0x02D9,
+ 0xA843, 0x2013, 0xA844, 0x2015, 0xA845, 0x2025, 0xA846, 0x2035, 0xA847, 0x2105, 0xA848, 0x2109, 0xA849, 0x2196, 0xA84A, 0x2197,
+ 0xA84B, 0x2198, 0xA84C, 0x2199, 0xA84D, 0x2215, 0xA84E, 0x221F, 0xA84F, 0x2223, 0xA850, 0x2252, 0xA851, 0x2266, 0xA852, 0x2267,
+ 0xA853, 0x22BF, 0xA854, 0x2550, 0xA855, 0x2551, 0xA856, 0x2552, 0xA857, 0x2553, 0xA858, 0x2554, 0xA859, 0x2555, 0xA85A, 0x2556,
+ 0xA85B, 0x2557, 0xA85C, 0x2558, 0xA85D, 0x2559, 0xA85E, 0x255A, 0xA85F, 0x255B, 0xA860, 0x255C, 0xA861, 0x255D, 0xA862, 0x255E,
+ 0xA863, 0x255F, 0xA864, 0x2560, 0xA865, 0x2561, 0xA866, 0x2562, 0xA867, 0x2563, 0xA868, 0x2564, 0xA869, 0x2565, 0xA86A, 0x2566,
+ 0xA86B, 0x2567, 0xA86C, 0x2568, 0xA86D, 0x2569, 0xA86E, 0x256A, 0xA86F, 0x256B, 0xA870, 0x256C, 0xA871, 0x256D, 0xA872, 0x256E,
+ 0xA873, 0x256F, 0xA874, 0x2570, 0xA875, 0x2571, 0xA876, 0x2572, 0xA877, 0x2573, 0xA878, 0x2581, 0xA879, 0x2582, 0xA87A, 0x2583,
+ 0xA87B, 0x2584, 0xA87C, 0x2585, 0xA87D, 0x2586, 0xA87E, 0x2587, 0xA880, 0x2588, 0xA881, 0x2589, 0xA882, 0x258A, 0xA883, 0x258B,
+ 0xA884, 0x258C, 0xA885, 0x258D, 0xA886, 0x258E, 0xA887, 0x258F, 0xA888, 0x2593, 0xA889, 0x2594, 0xA88A, 0x2595, 0xA88B, 0x25BC,
+ 0xA88C, 0x25BD, 0xA88D, 0x25E2, 0xA88E, 0x25E3, 0xA88F, 0x25E4, 0xA890, 0x25E5, 0xA891, 0x2609, 0xA892, 0x2295, 0xA893, 0x3012,
+ 0xA894, 0x301D, 0xA895, 0x301E, 0xA8A1, 0x0101, 0xA8A2, 0x00E1, 0xA8A3, 0x01CE, 0xA8A4, 0x00E0, 0xA8A5, 0x0113, 0xA8A6, 0x00E9,
+ 0xA8A7, 0x011B, 0xA8A8, 0x00E8, 0xA8A9, 0x012B, 0xA8AA, 0x00ED, 0xA8AB, 0x01D0, 0xA8AC, 0x00EC, 0xA8AD, 0x014D, 0xA8AE, 0x00F3,
+ 0xA8AF, 0x01D2, 0xA8B0, 0x00F2, 0xA8B1, 0x016B, 0xA8B2, 0x00FA, 0xA8B3, 0x01D4, 0xA8B4, 0x00F9, 0xA8B5, 0x01D6, 0xA8B6, 0x01D8,
+ 0xA8B7, 0x01DA, 0xA8B8, 0x01DC, 0xA8B9, 0x00FC, 0xA8BA, 0x00EA, 0xA8BB, 0x0251, 0xA8BD, 0x0144, 0xA8BE, 0x0148, 0xA8C0, 0x0261,
+ 0xA8C5, 0x3105, 0xA8C6, 0x3106, 0xA8C7, 0x3107, 0xA8C8, 0x3108, 0xA8C9, 0x3109, 0xA8CA, 0x310A, 0xA8CB, 0x310B, 0xA8CC, 0x310C,
+ 0xA8CD, 0x310D, 0xA8CE, 0x310E, 0xA8CF, 0x310F, 0xA8D0, 0x3110, 0xA8D1, 0x3111, 0xA8D2, 0x3112, 0xA8D3, 0x3113, 0xA8D4, 0x3114,
+ 0xA8D5, 0x3115, 0xA8D6, 0x3116, 0xA8D7, 0x3117, 0xA8D8, 0x3118, 0xA8D9, 0x3119, 0xA8DA, 0x311A, 0xA8DB, 0x311B, 0xA8DC, 0x311C,
+ 0xA8DD, 0x311D, 0xA8DE, 0x311E, 0xA8DF, 0x311F, 0xA8E0, 0x3120, 0xA8E1, 0x3121, 0xA8E2, 0x3122, 0xA8E3, 0x3123, 0xA8E4, 0x3124,
+ 0xA8E5, 0x3125, 0xA8E6, 0x3126, 0xA8E7, 0x3127, 0xA8E8, 0x3128, 0xA8E9, 0x3129, 0xA940, 0x3021, 0xA941, 0x3022, 0xA942, 0x3023,
+ 0xA943, 0x3024, 0xA944, 0x3025, 0xA945, 0x3026, 0xA946, 0x3027, 0xA947, 0x3028, 0xA948, 0x3029, 0xA949, 0x32A3, 0xA94A, 0x338E,
+ 0xA94B, 0x338F, 0xA94C, 0x339C, 0xA94D, 0x339D, 0xA94E, 0x339E, 0xA94F, 0x33A1, 0xA950, 0x33C4, 0xA951, 0x33CE, 0xA952, 0x33D1,
+ 0xA953, 0x33D2, 0xA954, 0x33D5, 0xA955, 0xFE30, 0xA956, 0xFFE2, 0xA957, 0xFFE4, 0xA959, 0x2121, 0xA95A, 0x3231, 0xA95C, 0x2010,
+ 0xA960, 0x30FC, 0xA961, 0x309B, 0xA962, 0x309C, 0xA963, 0x30FD, 0xA964, 0x30FE, 0xA965, 0x3006, 0xA966, 0x309D, 0xA967, 0x309E,
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+ 0xB05B, 0x7667, 0xB05C, 0x7668, 0xB05D, 0x7669, 0xB05E, 0x766A, 0xB05F, 0x766C, 0xB060, 0x766D, 0xB061, 0x766E, 0xB062, 0x7670,
+ 0xB063, 0x7671, 0xB064, 0x7672, 0xB065, 0x7673, 0xB066, 0x7674, 0xB067, 0x7675, 0xB068, 0x7676, 0xB069, 0x7677, 0xB06A, 0x7679,
+ 0xB06B, 0x767A, 0xB06C, 0x767C, 0xB06D, 0x767F, 0xB06E, 0x7680, 0xB06F, 0x7681, 0xB070, 0x7683, 0xB071, 0x7685, 0xB072, 0x7689,
+ 0xB073, 0x768A, 0xB074, 0x768C, 0xB075, 0x768D, 0xB076, 0x768F, 0xB077, 0x7690, 0xB078, 0x7692, 0xB079, 0x7694, 0xB07A, 0x7695,
+ 0xB07B, 0x7697, 0xB07C, 0x7698, 0xB07D, 0x769A, 0xB07E, 0x769B, 0xB080, 0x769C, 0xB081, 0x769D, 0xB082, 0x769E, 0xB083, 0x769F,
+ 0xB084, 0x76A0, 0xB085, 0x76A1, 0xB086, 0x76A2, 0xB087, 0x76A3, 0xB088, 0x76A5, 0xB089, 0x76A6, 0xB08A, 0x76A7, 0xB08B, 0x76A8,
+ 0xB08C, 0x76A9, 0xB08D, 0x76AA, 0xB08E, 0x76AB, 0xB08F, 0x76AC, 0xB090, 0x76AD, 0xB091, 0x76AF, 0xB092, 0x76B0, 0xB093, 0x76B3,
+ 0xB094, 0x76B5, 0xB095, 0x76B6, 0xB096, 0x76B7, 0xB097, 0x76B8, 0xB098, 0x76B9, 0xB099, 0x76BA, 0xB09A, 0x76BB, 0xB09B, 0x76BC,
+ 0xB09C, 0x76BD, 0xB09D, 0x76BE, 0xB09E, 0x76C0, 0xB09F, 0x76C1, 0xB0A0, 0x76C3, 0xB0A1, 0x554A, 0xB0A2, 0x963F, 0xB0A3, 0x57C3,
+ 0xB0A4, 0x6328, 0xB0A5, 0x54CE, 0xB0A6, 0x5509, 0xB0A7, 0x54C0, 0xB0A8, 0x7691, 0xB0A9, 0x764C, 0xB0AA, 0x853C, 0xB0AB, 0x77EE,
+ 0xB0AC, 0x827E, 0xB0AD, 0x788D, 0xB0AE, 0x7231, 0xB0AF, 0x9698, 0xB0B0, 0x978D, 0xB0B1, 0x6C28, 0xB0B2, 0x5B89, 0xB0B3, 0x4FFA,
+ 0xB0B4, 0x6309, 0xB0B5, 0x6697, 0xB0B6, 0x5CB8, 0xB0B7, 0x80FA, 0xB0B8, 0x6848, 0xB0B9, 0x80AE, 0xB0BA, 0x6602, 0xB0BB, 0x76CE,
+ 0xB0BC, 0x51F9, 0xB0BD, 0x6556, 0xB0BE, 0x71AC, 0xB0BF, 0x7FF1, 0xB0C0, 0x8884, 0xB0C1, 0x50B2, 0xB0C2, 0x5965, 0xB0C3, 0x61CA,
+ 0xB0C4, 0x6FB3, 0xB0C5, 0x82AD, 0xB0C6, 0x634C, 0xB0C7, 0x6252, 0xB0C8, 0x53ED, 0xB0C9, 0x5427, 0xB0CA, 0x7B06, 0xB0CB, 0x516B,
+ 0xB0CC, 0x75A4, 0xB0CD, 0x5DF4, 0xB0CE, 0x62D4, 0xB0CF, 0x8DCB, 0xB0D0, 0x9776, 0xB0D1, 0x628A, 0xB0D2, 0x8019, 0xB0D3, 0x575D,
+ 0xB0D4, 0x9738, 0xB0D5, 0x7F62, 0xB0D6, 0x7238, 0xB0D7, 0x767D, 0xB0D8, 0x67CF, 0xB0D9, 0x767E, 0xB0DA, 0x6446, 0xB0DB, 0x4F70,
+ 0xB0DC, 0x8D25, 0xB0DD, 0x62DC, 0xB0DE, 0x7A17, 0xB0DF, 0x6591, 0xB0E0, 0x73ED, 0xB0E1, 0x642C, 0xB0E2, 0x6273, 0xB0E3, 0x822C,
+ 0xB0E4, 0x9881, 0xB0E5, 0x677F, 0xB0E6, 0x7248, 0xB0E7, 0x626E, 0xB0E8, 0x62CC, 0xB0E9, 0x4F34, 0xB0EA, 0x74E3, 0xB0EB, 0x534A,
+ 0xB0EC, 0x529E, 0xB0ED, 0x7ECA, 0xB0EE, 0x90A6, 0xB0EF, 0x5E2E, 0xB0F0, 0x6886, 0xB0F1, 0x699C, 0xB0F2, 0x8180, 0xB0F3, 0x7ED1,
+ 0xB0F4, 0x68D2, 0xB0F5, 0x78C5, 0xB0F6, 0x868C, 0xB0F7, 0x9551, 0xB0F8, 0x508D, 0xB0F9, 0x8C24, 0xB0FA, 0x82DE, 0xB0FB, 0x80DE,
+ 0xB0FC, 0x5305, 0xB0FD, 0x8912, 0xB0FE, 0x5265, 0xB140, 0x76C4, 0xB141, 0x76C7, 0xB142, 0x76C9, 0xB143, 0x76CB, 0xB144, 0x76CC,
+ 0xB145, 0x76D3, 0xB146, 0x76D5, 0xB147, 0x76D9, 0xB148, 0x76DA, 0xB149, 0x76DC, 0xB14A, 0x76DD, 0xB14B, 0x76DE, 0xB14C, 0x76E0,
+ 0xB14D, 0x76E1, 0xB14E, 0x76E2, 0xB14F, 0x76E3, 0xB150, 0x76E4, 0xB151, 0x76E6, 0xB152, 0x76E7, 0xB153, 0x76E8, 0xB154, 0x76E9,
+ 0xB155, 0x76EA, 0xB156, 0x76EB, 0xB157, 0x76EC, 0xB158, 0x76ED, 0xB159, 0x76F0, 0xB15A, 0x76F3, 0xB15B, 0x76F5, 0xB15C, 0x76F6,
+ 0xB15D, 0x76F7, 0xB15E, 0x76FA, 0xB15F, 0x76FB, 0xB160, 0x76FD, 0xB161, 0x76FF, 0xB162, 0x7700, 0xB163, 0x7702, 0xB164, 0x7703,
+ 0xB165, 0x7705, 0xB166, 0x7706, 0xB167, 0x770A, 0xB168, 0x770C, 0xB169, 0x770E, 0xB16A, 0x770F, 0xB16B, 0x7710, 0xB16C, 0x7711,
+ 0xB16D, 0x7712, 0xB16E, 0x7713, 0xB16F, 0x7714, 0xB170, 0x7715, 0xB171, 0x7716, 0xB172, 0x7717, 0xB173, 0x7718, 0xB174, 0x771B,
+ 0xB175, 0x771C, 0xB176, 0x771D, 0xB177, 0x771E, 0xB178, 0x7721, 0xB179, 0x7723, 0xB17A, 0x7724, 0xB17B, 0x7725, 0xB17C, 0x7727,
+ 0xB17D, 0x772A, 0xB17E, 0x772B, 0xB180, 0x772C, 0xB181, 0x772E, 0xB182, 0x7730, 0xB183, 0x7731, 0xB184, 0x7732, 0xB185, 0x7733,
+ 0xB186, 0x7734, 0xB187, 0x7739, 0xB188, 0x773B, 0xB189, 0x773D, 0xB18A, 0x773E, 0xB18B, 0x773F, 0xB18C, 0x7742, 0xB18D, 0x7744,
+ 0xB18E, 0x7745, 0xB18F, 0x7746, 0xB190, 0x7748, 0xB191, 0x7749, 0xB192, 0x774A, 0xB193, 0x774B, 0xB194, 0x774C, 0xB195, 0x774D,
+ 0xB196, 0x774E, 0xB197, 0x774F, 0xB198, 0x7752, 0xB199, 0x7753, 0xB19A, 0x7754, 0xB19B, 0x7755, 0xB19C, 0x7756, 0xB19D, 0x7757,
+ 0xB19E, 0x7758, 0xB19F, 0x7759, 0xB1A0, 0x775C, 0xB1A1, 0x8584, 0xB1A2, 0x96F9, 0xB1A3, 0x4FDD, 0xB1A4, 0x5821, 0xB1A5, 0x9971,
+ 0xB1A6, 0x5B9D, 0xB1A7, 0x62B1, 0xB1A8, 0x62A5, 0xB1A9, 0x66B4, 0xB1AA, 0x8C79, 0xB1AB, 0x9C8D, 0xB1AC, 0x7206, 0xB1AD, 0x676F,
+ 0xB1AE, 0x7891, 0xB1AF, 0x60B2, 0xB1B0, 0x5351, 0xB1B1, 0x5317, 0xB1B2, 0x8F88, 0xB1B3, 0x80CC, 0xB1B4, 0x8D1D, 0xB1B5, 0x94A1,
+ 0xB1B6, 0x500D, 0xB1B7, 0x72C8, 0xB1B8, 0x5907, 0xB1B9, 0x60EB, 0xB1BA, 0x7119, 0xB1BB, 0x88AB, 0xB1BC, 0x5954, 0xB1BD, 0x82EF,
+ 0xB1BE, 0x672C, 0xB1BF, 0x7B28, 0xB1C0, 0x5D29, 0xB1C1, 0x7EF7, 0xB1C2, 0x752D, 0xB1C3, 0x6CF5, 0xB1C4, 0x8E66, 0xB1C5, 0x8FF8,
+ 0xB1C6, 0x903C, 0xB1C7, 0x9F3B, 0xB1C8, 0x6BD4, 0xB1C9, 0x9119, 0xB1CA, 0x7B14, 0xB1CB, 0x5F7C, 0xB1CC, 0x78A7, 0xB1CD, 0x84D6,
+ 0xB1CE, 0x853D, 0xB1CF, 0x6BD5, 0xB1D0, 0x6BD9, 0xB1D1, 0x6BD6, 0xB1D2, 0x5E01, 0xB1D3, 0x5E87, 0xB1D4, 0x75F9, 0xB1D5, 0x95ED,
+ 0xB1D6, 0x655D, 0xB1D7, 0x5F0A, 0xB1D8, 0x5FC5, 0xB1D9, 0x8F9F, 0xB1DA, 0x58C1, 0xB1DB, 0x81C2, 0xB1DC, 0x907F, 0xB1DD, 0x965B,
+ 0xB1DE, 0x97AD, 0xB1DF, 0x8FB9, 0xB1E0, 0x7F16, 0xB1E1, 0x8D2C, 0xB1E2, 0x6241, 0xB1E3, 0x4FBF, 0xB1E4, 0x53D8, 0xB1E5, 0x535E,
+ 0xB1E6, 0x8FA8, 0xB1E7, 0x8FA9, 0xB1E8, 0x8FAB, 0xB1E9, 0x904D, 0xB1EA, 0x6807, 0xB1EB, 0x5F6A, 0xB1EC, 0x8198, 0xB1ED, 0x8868,
+ 0xB1EE, 0x9CD6, 0xB1EF, 0x618B, 0xB1F0, 0x522B, 0xB1F1, 0x762A, 0xB1F2, 0x5F6C, 0xB1F3, 0x658C, 0xB1F4, 0x6FD2, 0xB1F5, 0x6EE8,
+ 0xB1F6, 0x5BBE, 0xB1F7, 0x6448, 0xB1F8, 0x5175, 0xB1F9, 0x51B0, 0xB1FA, 0x67C4, 0xB1FB, 0x4E19, 0xB1FC, 0x79C9, 0xB1FD, 0x997C,
+ 0xB1FE, 0x70B3, 0xB240, 0x775D, 0xB241, 0x775E, 0xB242, 0x775F, 0xB243, 0x7760, 0xB244, 0x7764, 0xB245, 0x7767, 0xB246, 0x7769,
+ 0xB247, 0x776A, 0xB248, 0x776D, 0xB249, 0x776E, 0xB24A, 0x776F, 0xB24B, 0x7770, 0xB24C, 0x7771, 0xB24D, 0x7772, 0xB24E, 0x7773,
+ 0xB24F, 0x7774, 0xB250, 0x7775, 0xB251, 0x7776, 0xB252, 0x7777, 0xB253, 0x7778, 0xB254, 0x777A, 0xB255, 0x777B, 0xB256, 0x777C,
+ 0xB257, 0x7781, 0xB258, 0x7782, 0xB259, 0x7783, 0xB25A, 0x7786, 0xB25B, 0x7787, 0xB25C, 0x7788, 0xB25D, 0x7789, 0xB25E, 0x778A,
+ 0xB25F, 0x778B, 0xB260, 0x778F, 0xB261, 0x7790, 0xB262, 0x7793, 0xB263, 0x7794, 0xB264, 0x7795, 0xB265, 0x7796, 0xB266, 0x7797,
+ 0xB267, 0x7798, 0xB268, 0x7799, 0xB269, 0x779A, 0xB26A, 0x779B, 0xB26B, 0x779C, 0xB26C, 0x779D, 0xB26D, 0x779E, 0xB26E, 0x77A1,
+ 0xB26F, 0x77A3, 0xB270, 0x77A4, 0xB271, 0x77A6, 0xB272, 0x77A8, 0xB273, 0x77AB, 0xB274, 0x77AD, 0xB275, 0x77AE, 0xB276, 0x77AF,
+ 0xB277, 0x77B1, 0xB278, 0x77B2, 0xB279, 0x77B4, 0xB27A, 0x77B6, 0xB27B, 0x77B7, 0xB27C, 0x77B8, 0xB27D, 0x77B9, 0xB27E, 0x77BA,
+ 0xB280, 0x77BC, 0xB281, 0x77BE, 0xB282, 0x77C0, 0xB283, 0x77C1, 0xB284, 0x77C2, 0xB285, 0x77C3, 0xB286, 0x77C4, 0xB287, 0x77C5,
+ 0xB288, 0x77C6, 0xB289, 0x77C7, 0xB28A, 0x77C8, 0xB28B, 0x77C9, 0xB28C, 0x77CA, 0xB28D, 0x77CB, 0xB28E, 0x77CC, 0xB28F, 0x77CE,
+ 0xB290, 0x77CF, 0xB291, 0x77D0, 0xB292, 0x77D1, 0xB293, 0x77D2, 0xB294, 0x77D3, 0xB295, 0x77D4, 0xB296, 0x77D5, 0xB297, 0x77D6,
+ 0xB298, 0x77D8, 0xB299, 0x77D9, 0xB29A, 0x77DA, 0xB29B, 0x77DD, 0xB29C, 0x77DE, 0xB29D, 0x77DF, 0xB29E, 0x77E0, 0xB29F, 0x77E1,
+ 0xB2A0, 0x77E4, 0xB2A1, 0x75C5, 0xB2A2, 0x5E76, 0xB2A3, 0x73BB, 0xB2A4, 0x83E0, 0xB2A5, 0x64AD, 0xB2A6, 0x62E8, 0xB2A7, 0x94B5,
+ 0xB2A8, 0x6CE2, 0xB2A9, 0x535A, 0xB2AA, 0x52C3, 0xB2AB, 0x640F, 0xB2AC, 0x94C2, 0xB2AD, 0x7B94, 0xB2AE, 0x4F2F, 0xB2AF, 0x5E1B,
+ 0xB2B0, 0x8236, 0xB2B1, 0x8116, 0xB2B2, 0x818A, 0xB2B3, 0x6E24, 0xB2B4, 0x6CCA, 0xB2B5, 0x9A73, 0xB2B6, 0x6355, 0xB2B7, 0x535C,
+ 0xB2B8, 0x54FA, 0xB2B9, 0x8865, 0xB2BA, 0x57E0, 0xB2BB, 0x4E0D, 0xB2BC, 0x5E03, 0xB2BD, 0x6B65, 0xB2BE, 0x7C3F, 0xB2BF, 0x90E8,
+ 0xB2C0, 0x6016, 0xB2C1, 0x64E6, 0xB2C2, 0x731C, 0xB2C3, 0x88C1, 0xB2C4, 0x6750, 0xB2C5, 0x624D, 0xB2C6, 0x8D22, 0xB2C7, 0x776C,
+ 0xB2C8, 0x8E29, 0xB2C9, 0x91C7, 0xB2CA, 0x5F69, 0xB2CB, 0x83DC, 0xB2CC, 0x8521, 0xB2CD, 0x9910, 0xB2CE, 0x53C2, 0xB2CF, 0x8695,
+ 0xB2D0, 0x6B8B, 0xB2D1, 0x60ED, 0xB2D2, 0x60E8, 0xB2D3, 0x707F, 0xB2D4, 0x82CD, 0xB2D5, 0x8231, 0xB2D6, 0x4ED3, 0xB2D7, 0x6CA7,
+ 0xB2D8, 0x85CF, 0xB2D9, 0x64CD, 0xB2DA, 0x7CD9, 0xB2DB, 0x69FD, 0xB2DC, 0x66F9, 0xB2DD, 0x8349, 0xB2DE, 0x5395, 0xB2DF, 0x7B56,
+ 0xB2E0, 0x4FA7, 0xB2E1, 0x518C, 0xB2E2, 0x6D4B, 0xB2E3, 0x5C42, 0xB2E4, 0x8E6D, 0xB2E5, 0x63D2, 0xB2E6, 0x53C9, 0xB2E7, 0x832C,
+ 0xB2E8, 0x8336, 0xB2E9, 0x67E5, 0xB2EA, 0x78B4, 0xB2EB, 0x643D, 0xB2EC, 0x5BDF, 0xB2ED, 0x5C94, 0xB2EE, 0x5DEE, 0xB2EF, 0x8BE7,
+ 0xB2F0, 0x62C6, 0xB2F1, 0x67F4, 0xB2F2, 0x8C7A, 0xB2F3, 0x6400, 0xB2F4, 0x63BA, 0xB2F5, 0x8749, 0xB2F6, 0x998B, 0xB2F7, 0x8C17,
+ 0xB2F8, 0x7F20, 0xB2F9, 0x94F2, 0xB2FA, 0x4EA7, 0xB2FB, 0x9610, 0xB2FC, 0x98A4, 0xB2FD, 0x660C, 0xB2FE, 0x7316, 0xB340, 0x77E6,
+ 0xB341, 0x77E8, 0xB342, 0x77EA, 0xB343, 0x77EF, 0xB344, 0x77F0, 0xB345, 0x77F1, 0xB346, 0x77F2, 0xB347, 0x77F4, 0xB348, 0x77F5,
+ 0xB349, 0x77F7, 0xB34A, 0x77F9, 0xB34B, 0x77FA, 0xB34C, 0x77FB, 0xB34D, 0x77FC, 0xB34E, 0x7803, 0xB34F, 0x7804, 0xB350, 0x7805,
+ 0xB351, 0x7806, 0xB352, 0x7807, 0xB353, 0x7808, 0xB354, 0x780A, 0xB355, 0x780B, 0xB356, 0x780E, 0xB357, 0x780F, 0xB358, 0x7810,
+ 0xB359, 0x7813, 0xB35A, 0x7815, 0xB35B, 0x7819, 0xB35C, 0x781B, 0xB35D, 0x781E, 0xB35E, 0x7820, 0xB35F, 0x7821, 0xB360, 0x7822,
+ 0xB361, 0x7824, 0xB362, 0x7828, 0xB363, 0x782A, 0xB364, 0x782B, 0xB365, 0x782E, 0xB366, 0x782F, 0xB367, 0x7831, 0xB368, 0x7832,
+ 0xB369, 0x7833, 0xB36A, 0x7835, 0xB36B, 0x7836, 0xB36C, 0x783D, 0xB36D, 0x783F, 0xB36E, 0x7841, 0xB36F, 0x7842, 0xB370, 0x7843,
+ 0xB371, 0x7844, 0xB372, 0x7846, 0xB373, 0x7848, 0xB374, 0x7849, 0xB375, 0x784A, 0xB376, 0x784B, 0xB377, 0x784D, 0xB378, 0x784F,
+ 0xB379, 0x7851, 0xB37A, 0x7853, 0xB37B, 0x7854, 0xB37C, 0x7858, 0xB37D, 0x7859, 0xB37E, 0x785A, 0xB380, 0x785B, 0xB381, 0x785C,
+ 0xB382, 0x785E, 0xB383, 0x785F, 0xB384, 0x7860, 0xB385, 0x7861, 0xB386, 0x7862, 0xB387, 0x7863, 0xB388, 0x7864, 0xB389, 0x7865,
+ 0xB38A, 0x7866, 0xB38B, 0x7867, 0xB38C, 0x7868, 0xB38D, 0x7869, 0xB38E, 0x786F, 0xB38F, 0x7870, 0xB390, 0x7871, 0xB391, 0x7872,
+ 0xB392, 0x7873, 0xB393, 0x7874, 0xB394, 0x7875, 0xB395, 0x7876, 0xB396, 0x7878, 0xB397, 0x7879, 0xB398, 0x787A, 0xB399, 0x787B,
+ 0xB39A, 0x787D, 0xB39B, 0x787E, 0xB39C, 0x787F, 0xB39D, 0x7880, 0xB39E, 0x7881, 0xB39F, 0x7882, 0xB3A0, 0x7883, 0xB3A1, 0x573A,
+ 0xB3A2, 0x5C1D, 0xB3A3, 0x5E38, 0xB3A4, 0x957F, 0xB3A5, 0x507F, 0xB3A6, 0x80A0, 0xB3A7, 0x5382, 0xB3A8, 0x655E, 0xB3A9, 0x7545,
+ 0xB3AA, 0x5531, 0xB3AB, 0x5021, 0xB3AC, 0x8D85, 0xB3AD, 0x6284, 0xB3AE, 0x949E, 0xB3AF, 0x671D, 0xB3B0, 0x5632, 0xB3B1, 0x6F6E,
+ 0xB3B2, 0x5DE2, 0xB3B3, 0x5435, 0xB3B4, 0x7092, 0xB3B5, 0x8F66, 0xB3B6, 0x626F, 0xB3B7, 0x64A4, 0xB3B8, 0x63A3, 0xB3B9, 0x5F7B,
+ 0xB3BA, 0x6F88, 0xB3BB, 0x90F4, 0xB3BC, 0x81E3, 0xB3BD, 0x8FB0, 0xB3BE, 0x5C18, 0xB3BF, 0x6668, 0xB3C0, 0x5FF1, 0xB3C1, 0x6C89,
+ 0xB3C2, 0x9648, 0xB3C3, 0x8D81, 0xB3C4, 0x886C, 0xB3C5, 0x6491, 0xB3C6, 0x79F0, 0xB3C7, 0x57CE, 0xB3C8, 0x6A59, 0xB3C9, 0x6210,
+ 0xB3CA, 0x5448, 0xB3CB, 0x4E58, 0xB3CC, 0x7A0B, 0xB3CD, 0x60E9, 0xB3CE, 0x6F84, 0xB3CF, 0x8BDA, 0xB3D0, 0x627F, 0xB3D1, 0x901E,
+ 0xB3D2, 0x9A8B, 0xB3D3, 0x79E4, 0xB3D4, 0x5403, 0xB3D5, 0x75F4, 0xB3D6, 0x6301, 0xB3D7, 0x5319, 0xB3D8, 0x6C60, 0xB3D9, 0x8FDF,
+ 0xB3DA, 0x5F1B, 0xB3DB, 0x9A70, 0xB3DC, 0x803B, 0xB3DD, 0x9F7F, 0xB3DE, 0x4F88, 0xB3DF, 0x5C3A, 0xB3E0, 0x8D64, 0xB3E1, 0x7FC5,
+ 0xB3E2, 0x65A5, 0xB3E3, 0x70BD, 0xB3E4, 0x5145, 0xB3E5, 0x51B2, 0xB3E6, 0x866B, 0xB3E7, 0x5D07, 0xB3E8, 0x5BA0, 0xB3E9, 0x62BD,
+ 0xB3EA, 0x916C, 0xB3EB, 0x7574, 0xB3EC, 0x8E0C, 0xB3ED, 0x7A20, 0xB3EE, 0x6101, 0xB3EF, 0x7B79, 0xB3F0, 0x4EC7, 0xB3F1, 0x7EF8,
+ 0xB3F2, 0x7785, 0xB3F3, 0x4E11, 0xB3F4, 0x81ED, 0xB3F5, 0x521D, 0xB3F6, 0x51FA, 0xB3F7, 0x6A71, 0xB3F8, 0x53A8, 0xB3F9, 0x8E87,
+ 0xB3FA, 0x9504, 0xB3FB, 0x96CF, 0xB3FC, 0x6EC1, 0xB3FD, 0x9664, 0xB3FE, 0x695A, 0xB440, 0x7884, 0xB441, 0x7885, 0xB442, 0x7886,
+ 0xB443, 0x7888, 0xB444, 0x788A, 0xB445, 0x788B, 0xB446, 0x788F, 0xB447, 0x7890, 0xB448, 0x7892, 0xB449, 0x7894, 0xB44A, 0x7895,
+ 0xB44B, 0x7896, 0xB44C, 0x7899, 0xB44D, 0x789D, 0xB44E, 0x789E, 0xB44F, 0x78A0, 0xB450, 0x78A2, 0xB451, 0x78A4, 0xB452, 0x78A6,
+ 0xB453, 0x78A8, 0xB454, 0x78A9, 0xB455, 0x78AA, 0xB456, 0x78AB, 0xB457, 0x78AC, 0xB458, 0x78AD, 0xB459, 0x78AE, 0xB45A, 0x78AF,
+ 0xB45B, 0x78B5, 0xB45C, 0x78B6, 0xB45D, 0x78B7, 0xB45E, 0x78B8, 0xB45F, 0x78BA, 0xB460, 0x78BB, 0xB461, 0x78BC, 0xB462, 0x78BD,
+ 0xB463, 0x78BF, 0xB464, 0x78C0, 0xB465, 0x78C2, 0xB466, 0x78C3, 0xB467, 0x78C4, 0xB468, 0x78C6, 0xB469, 0x78C7, 0xB46A, 0x78C8,
+ 0xB46B, 0x78CC, 0xB46C, 0x78CD, 0xB46D, 0x78CE, 0xB46E, 0x78CF, 0xB46F, 0x78D1, 0xB470, 0x78D2, 0xB471, 0x78D3, 0xB472, 0x78D6,
+ 0xB473, 0x78D7, 0xB474, 0x78D8, 0xB475, 0x78DA, 0xB476, 0x78DB, 0xB477, 0x78DC, 0xB478, 0x78DD, 0xB479, 0x78DE, 0xB47A, 0x78DF,
+ 0xB47B, 0x78E0, 0xB47C, 0x78E1, 0xB47D, 0x78E2, 0xB47E, 0x78E3, 0xB480, 0x78E4, 0xB481, 0x78E5, 0xB482, 0x78E6, 0xB483, 0x78E7,
+ 0xB484, 0x78E9, 0xB485, 0x78EA, 0xB486, 0x78EB, 0xB487, 0x78ED, 0xB488, 0x78EE, 0xB489, 0x78EF, 0xB48A, 0x78F0, 0xB48B, 0x78F1,
+ 0xB48C, 0x78F3, 0xB48D, 0x78F5, 0xB48E, 0x78F6, 0xB48F, 0x78F8, 0xB490, 0x78F9, 0xB491, 0x78FB, 0xB492, 0x78FC, 0xB493, 0x78FD,
+ 0xB494, 0x78FE, 0xB495, 0x78FF, 0xB496, 0x7900, 0xB497, 0x7902, 0xB498, 0x7903, 0xB499, 0x7904, 0xB49A, 0x7906, 0xB49B, 0x7907,
+ 0xB49C, 0x7908, 0xB49D, 0x7909, 0xB49E, 0x790A, 0xB49F, 0x790B, 0xB4A0, 0x790C, 0xB4A1, 0x7840, 0xB4A2, 0x50A8, 0xB4A3, 0x77D7,
+ 0xB4A4, 0x6410, 0xB4A5, 0x89E6, 0xB4A6, 0x5904, 0xB4A7, 0x63E3, 0xB4A8, 0x5DDD, 0xB4A9, 0x7A7F, 0xB4AA, 0x693D, 0xB4AB, 0x4F20,
+ 0xB4AC, 0x8239, 0xB4AD, 0x5598, 0xB4AE, 0x4E32, 0xB4AF, 0x75AE, 0xB4B0, 0x7A97, 0xB4B1, 0x5E62, 0xB4B2, 0x5E8A, 0xB4B3, 0x95EF,
+ 0xB4B4, 0x521B, 0xB4B5, 0x5439, 0xB4B6, 0x708A, 0xB4B7, 0x6376, 0xB4B8, 0x9524, 0xB4B9, 0x5782, 0xB4BA, 0x6625, 0xB4BB, 0x693F,
+ 0xB4BC, 0x9187, 0xB4BD, 0x5507, 0xB4BE, 0x6DF3, 0xB4BF, 0x7EAF, 0xB4C0, 0x8822, 0xB4C1, 0x6233, 0xB4C2, 0x7EF0, 0xB4C3, 0x75B5,
+ 0xB4C4, 0x8328, 0xB4C5, 0x78C1, 0xB4C6, 0x96CC, 0xB4C7, 0x8F9E, 0xB4C8, 0x6148, 0xB4C9, 0x74F7, 0xB4CA, 0x8BCD, 0xB4CB, 0x6B64,
+ 0xB4CC, 0x523A, 0xB4CD, 0x8D50, 0xB4CE, 0x6B21, 0xB4CF, 0x806A, 0xB4D0, 0x8471, 0xB4D1, 0x56F1, 0xB4D2, 0x5306, 0xB4D3, 0x4ECE,
+ 0xB4D4, 0x4E1B, 0xB4D5, 0x51D1, 0xB4D6, 0x7C97, 0xB4D7, 0x918B, 0xB4D8, 0x7C07, 0xB4D9, 0x4FC3, 0xB4DA, 0x8E7F, 0xB4DB, 0x7BE1,
+ 0xB4DC, 0x7A9C, 0xB4DD, 0x6467, 0xB4DE, 0x5D14, 0xB4DF, 0x50AC, 0xB4E0, 0x8106, 0xB4E1, 0x7601, 0xB4E2, 0x7CB9, 0xB4E3, 0x6DEC,
+ 0xB4E4, 0x7FE0, 0xB4E5, 0x6751, 0xB4E6, 0x5B58, 0xB4E7, 0x5BF8, 0xB4E8, 0x78CB, 0xB4E9, 0x64AE, 0xB4EA, 0x6413, 0xB4EB, 0x63AA,
+ 0xB4EC, 0x632B, 0xB4ED, 0x9519, 0xB4EE, 0x642D, 0xB4EF, 0x8FBE, 0xB4F0, 0x7B54, 0xB4F1, 0x7629, 0xB4F2, 0x6253, 0xB4F3, 0x5927,
+ 0xB4F4, 0x5446, 0xB4F5, 0x6B79, 0xB4F6, 0x50A3, 0xB4F7, 0x6234, 0xB4F8, 0x5E26, 0xB4F9, 0x6B86, 0xB4FA, 0x4EE3, 0xB4FB, 0x8D37,
+ 0xB4FC, 0x888B, 0xB4FD, 0x5F85, 0xB4FE, 0x902E, 0xB540, 0x790D, 0xB541, 0x790E, 0xB542, 0x790F, 0xB543, 0x7910, 0xB544, 0x7911,
+ 0xB545, 0x7912, 0xB546, 0x7914, 0xB547, 0x7915, 0xB548, 0x7916, 0xB549, 0x7917, 0xB54A, 0x7918, 0xB54B, 0x7919, 0xB54C, 0x791A,
+ 0xB54D, 0x791B, 0xB54E, 0x791C, 0xB54F, 0x791D, 0xB550, 0x791F, 0xB551, 0x7920, 0xB552, 0x7921, 0xB553, 0x7922, 0xB554, 0x7923,
+ 0xB555, 0x7925, 0xB556, 0x7926, 0xB557, 0x7927, 0xB558, 0x7928, 0xB559, 0x7929, 0xB55A, 0x792A, 0xB55B, 0x792B, 0xB55C, 0x792C,
+ 0xB55D, 0x792D, 0xB55E, 0x792E, 0xB55F, 0x792F, 0xB560, 0x7930, 0xB561, 0x7931, 0xB562, 0x7932, 0xB563, 0x7933, 0xB564, 0x7935,
+ 0xB565, 0x7936, 0xB566, 0x7937, 0xB567, 0x7938, 0xB568, 0x7939, 0xB569, 0x793D, 0xB56A, 0x793F, 0xB56B, 0x7942, 0xB56C, 0x7943,
+ 0xB56D, 0x7944, 0xB56E, 0x7945, 0xB56F, 0x7947, 0xB570, 0x794A, 0xB571, 0x794B, 0xB572, 0x794C, 0xB573, 0x794D, 0xB574, 0x794E,
+ 0xB575, 0x794F, 0xB576, 0x7950, 0xB577, 0x7951, 0xB578, 0x7952, 0xB579, 0x7954, 0xB57A, 0x7955, 0xB57B, 0x7958, 0xB57C, 0x7959,
+ 0xB57D, 0x7961, 0xB57E, 0x7963, 0xB580, 0x7964, 0xB581, 0x7966, 0xB582, 0x7969, 0xB583, 0x796A, 0xB584, 0x796B, 0xB585, 0x796C,
+ 0xB586, 0x796E, 0xB587, 0x7970, 0xB588, 0x7971, 0xB589, 0x7972, 0xB58A, 0x7973, 0xB58B, 0x7974, 0xB58C, 0x7975, 0xB58D, 0x7976,
+ 0xB58E, 0x7979, 0xB58F, 0x797B, 0xB590, 0x797C, 0xB591, 0x797D, 0xB592, 0x797E, 0xB593, 0x797F, 0xB594, 0x7982, 0xB595, 0x7983,
+ 0xB596, 0x7986, 0xB597, 0x7987, 0xB598, 0x7988, 0xB599, 0x7989, 0xB59A, 0x798B, 0xB59B, 0x798C, 0xB59C, 0x798D, 0xB59D, 0x798E,
+ 0xB59E, 0x7990, 0xB59F, 0x7991, 0xB5A0, 0x7992, 0xB5A1, 0x6020, 0xB5A2, 0x803D, 0xB5A3, 0x62C5, 0xB5A4, 0x4E39, 0xB5A5, 0x5355,
+ 0xB5A6, 0x90F8, 0xB5A7, 0x63B8, 0xB5A8, 0x80C6, 0xB5A9, 0x65E6, 0xB5AA, 0x6C2E, 0xB5AB, 0x4F46, 0xB5AC, 0x60EE, 0xB5AD, 0x6DE1,
+ 0xB5AE, 0x8BDE, 0xB5AF, 0x5F39, 0xB5B0, 0x86CB, 0xB5B1, 0x5F53, 0xB5B2, 0x6321, 0xB5B3, 0x515A, 0xB5B4, 0x8361, 0xB5B5, 0x6863,
+ 0xB5B6, 0x5200, 0xB5B7, 0x6363, 0xB5B8, 0x8E48, 0xB5B9, 0x5012, 0xB5BA, 0x5C9B, 0xB5BB, 0x7977, 0xB5BC, 0x5BFC, 0xB5BD, 0x5230,
+ 0xB5BE, 0x7A3B, 0xB5BF, 0x60BC, 0xB5C0, 0x9053, 0xB5C1, 0x76D7, 0xB5C2, 0x5FB7, 0xB5C3, 0x5F97, 0xB5C4, 0x7684, 0xB5C5, 0x8E6C,
+ 0xB5C6, 0x706F, 0xB5C7, 0x767B, 0xB5C8, 0x7B49, 0xB5C9, 0x77AA, 0xB5CA, 0x51F3, 0xB5CB, 0x9093, 0xB5CC, 0x5824, 0xB5CD, 0x4F4E,
+ 0xB5CE, 0x6EF4, 0xB5CF, 0x8FEA, 0xB5D0, 0x654C, 0xB5D1, 0x7B1B, 0xB5D2, 0x72C4, 0xB5D3, 0x6DA4, 0xB5D4, 0x7FDF, 0xB5D5, 0x5AE1,
+ 0xB5D6, 0x62B5, 0xB5D7, 0x5E95, 0xB5D8, 0x5730, 0xB5D9, 0x8482, 0xB5DA, 0x7B2C, 0xB5DB, 0x5E1D, 0xB5DC, 0x5F1F, 0xB5DD, 0x9012,
+ 0xB5DE, 0x7F14, 0xB5DF, 0x98A0, 0xB5E0, 0x6382, 0xB5E1, 0x6EC7, 0xB5E2, 0x7898, 0xB5E3, 0x70B9, 0xB5E4, 0x5178, 0xB5E5, 0x975B,
+ 0xB5E6, 0x57AB, 0xB5E7, 0x7535, 0xB5E8, 0x4F43, 0xB5E9, 0x7538, 0xB5EA, 0x5E97, 0xB5EB, 0x60E6, 0xB5EC, 0x5960, 0xB5ED, 0x6DC0,
+ 0xB5EE, 0x6BBF, 0xB5EF, 0x7889, 0xB5F0, 0x53FC, 0xB5F1, 0x96D5, 0xB5F2, 0x51CB, 0xB5F3, 0x5201, 0xB5F4, 0x6389, 0xB5F5, 0x540A,
+ 0xB5F6, 0x9493, 0xB5F7, 0x8C03, 0xB5F8, 0x8DCC, 0xB5F9, 0x7239, 0xB5FA, 0x789F, 0xB5FB, 0x8776, 0xB5FC, 0x8FED, 0xB5FD, 0x8C0D,
+ 0xB5FE, 0x53E0, 0xB640, 0x7993, 0xB641, 0x7994, 0xB642, 0x7995, 0xB643, 0x7996, 0xB644, 0x7997, 0xB645, 0x7998, 0xB646, 0x7999,
+ 0xB647, 0x799B, 0xB648, 0x799C, 0xB649, 0x799D, 0xB64A, 0x799E, 0xB64B, 0x799F, 0xB64C, 0x79A0, 0xB64D, 0x79A1, 0xB64E, 0x79A2,
+ 0xB64F, 0x79A3, 0xB650, 0x79A4, 0xB651, 0x79A5, 0xB652, 0x79A6, 0xB653, 0x79A8, 0xB654, 0x79A9, 0xB655, 0x79AA, 0xB656, 0x79AB,
+ 0xB657, 0x79AC, 0xB658, 0x79AD, 0xB659, 0x79AE, 0xB65A, 0x79AF, 0xB65B, 0x79B0, 0xB65C, 0x79B1, 0xB65D, 0x79B2, 0xB65E, 0x79B4,
+ 0xB65F, 0x79B5, 0xB660, 0x79B6, 0xB661, 0x79B7, 0xB662, 0x79B8, 0xB663, 0x79BC, 0xB664, 0x79BF, 0xB665, 0x79C2, 0xB666, 0x79C4,
+ 0xB667, 0x79C5, 0xB668, 0x79C7, 0xB669, 0x79C8, 0xB66A, 0x79CA, 0xB66B, 0x79CC, 0xB66C, 0x79CE, 0xB66D, 0x79CF, 0xB66E, 0x79D0,
+ 0xB66F, 0x79D3, 0xB670, 0x79D4, 0xB671, 0x79D6, 0xB672, 0x79D7, 0xB673, 0x79D9, 0xB674, 0x79DA, 0xB675, 0x79DB, 0xB676, 0x79DC,
+ 0xB677, 0x79DD, 0xB678, 0x79DE, 0xB679, 0x79E0, 0xB67A, 0x79E1, 0xB67B, 0x79E2, 0xB67C, 0x79E5, 0xB67D, 0x79E8, 0xB67E, 0x79EA,
+ 0xB680, 0x79EC, 0xB681, 0x79EE, 0xB682, 0x79F1, 0xB683, 0x79F2, 0xB684, 0x79F3, 0xB685, 0x79F4, 0xB686, 0x79F5, 0xB687, 0x79F6,
+ 0xB688, 0x79F7, 0xB689, 0x79F9, 0xB68A, 0x79FA, 0xB68B, 0x79FC, 0xB68C, 0x79FE, 0xB68D, 0x79FF, 0xB68E, 0x7A01, 0xB68F, 0x7A04,
+ 0xB690, 0x7A05, 0xB691, 0x7A07, 0xB692, 0x7A08, 0xB693, 0x7A09, 0xB694, 0x7A0A, 0xB695, 0x7A0C, 0xB696, 0x7A0F, 0xB697, 0x7A10,
+ 0xB698, 0x7A11, 0xB699, 0x7A12, 0xB69A, 0x7A13, 0xB69B, 0x7A15, 0xB69C, 0x7A16, 0xB69D, 0x7A18, 0xB69E, 0x7A19, 0xB69F, 0x7A1B,
+ 0xB6A0, 0x7A1C, 0xB6A1, 0x4E01, 0xB6A2, 0x76EF, 0xB6A3, 0x53EE, 0xB6A4, 0x9489, 0xB6A5, 0x9876, 0xB6A6, 0x9F0E, 0xB6A7, 0x952D,
+ 0xB6A8, 0x5B9A, 0xB6A9, 0x8BA2, 0xB6AA, 0x4E22, 0xB6AB, 0x4E1C, 0xB6AC, 0x51AC, 0xB6AD, 0x8463, 0xB6AE, 0x61C2, 0xB6AF, 0x52A8,
+ 0xB6B0, 0x680B, 0xB6B1, 0x4F97, 0xB6B2, 0x606B, 0xB6B3, 0x51BB, 0xB6B4, 0x6D1E, 0xB6B5, 0x515C, 0xB6B6, 0x6296, 0xB6B7, 0x6597,
+ 0xB6B8, 0x9661, 0xB6B9, 0x8C46, 0xB6BA, 0x9017, 0xB6BB, 0x75D8, 0xB6BC, 0x90FD, 0xB6BD, 0x7763, 0xB6BE, 0x6BD2, 0xB6BF, 0x728A,
+ 0xB6C0, 0x72EC, 0xB6C1, 0x8BFB, 0xB6C2, 0x5835, 0xB6C3, 0x7779, 0xB6C4, 0x8D4C, 0xB6C5, 0x675C, 0xB6C6, 0x9540, 0xB6C7, 0x809A,
+ 0xB6C8, 0x5EA6, 0xB6C9, 0x6E21, 0xB6CA, 0x5992, 0xB6CB, 0x7AEF, 0xB6CC, 0x77ED, 0xB6CD, 0x953B, 0xB6CE, 0x6BB5, 0xB6CF, 0x65AD,
+ 0xB6D0, 0x7F0E, 0xB6D1, 0x5806, 0xB6D2, 0x5151, 0xB6D3, 0x961F, 0xB6D4, 0x5BF9, 0xB6D5, 0x58A9, 0xB6D6, 0x5428, 0xB6D7, 0x8E72,
+ 0xB6D8, 0x6566, 0xB6D9, 0x987F, 0xB6DA, 0x56E4, 0xB6DB, 0x949D, 0xB6DC, 0x76FE, 0xB6DD, 0x9041, 0xB6DE, 0x6387, 0xB6DF, 0x54C6,
+ 0xB6E0, 0x591A, 0xB6E1, 0x593A, 0xB6E2, 0x579B, 0xB6E3, 0x8EB2, 0xB6E4, 0x6735, 0xB6E5, 0x8DFA, 0xB6E6, 0x8235, 0xB6E7, 0x5241,
+ 0xB6E8, 0x60F0, 0xB6E9, 0x5815, 0xB6EA, 0x86FE, 0xB6EB, 0x5CE8, 0xB6EC, 0x9E45, 0xB6ED, 0x4FC4, 0xB6EE, 0x989D, 0xB6EF, 0x8BB9,
+ 0xB6F0, 0x5A25, 0xB6F1, 0x6076, 0xB6F2, 0x5384, 0xB6F3, 0x627C, 0xB6F4, 0x904F, 0xB6F5, 0x9102, 0xB6F6, 0x997F, 0xB6F7, 0x6069,
+ 0xB6F8, 0x800C, 0xB6F9, 0x513F, 0xB6FA, 0x8033, 0xB6FB, 0x5C14, 0xB6FC, 0x9975, 0xB6FD, 0x6D31, 0xB6FE, 0x4E8C, 0xB740, 0x7A1D,
+ 0xB741, 0x7A1F, 0xB742, 0x7A21, 0xB743, 0x7A22, 0xB744, 0x7A24, 0xB745, 0x7A25, 0xB746, 0x7A26, 0xB747, 0x7A27, 0xB748, 0x7A28,
+ 0xB749, 0x7A29, 0xB74A, 0x7A2A, 0xB74B, 0x7A2B, 0xB74C, 0x7A2C, 0xB74D, 0x7A2D, 0xB74E, 0x7A2E, 0xB74F, 0x7A2F, 0xB750, 0x7A30,
+ 0xB751, 0x7A31, 0xB752, 0x7A32, 0xB753, 0x7A34, 0xB754, 0x7A35, 0xB755, 0x7A36, 0xB756, 0x7A38, 0xB757, 0x7A3A, 0xB758, 0x7A3E,
+ 0xB759, 0x7A40, 0xB75A, 0x7A41, 0xB75B, 0x7A42, 0xB75C, 0x7A43, 0xB75D, 0x7A44, 0xB75E, 0x7A45, 0xB75F, 0x7A47, 0xB760, 0x7A48,
+ 0xB761, 0x7A49, 0xB762, 0x7A4A, 0xB763, 0x7A4B, 0xB764, 0x7A4C, 0xB765, 0x7A4D, 0xB766, 0x7A4E, 0xB767, 0x7A4F, 0xB768, 0x7A50,
+ 0xB769, 0x7A52, 0xB76A, 0x7A53, 0xB76B, 0x7A54, 0xB76C, 0x7A55, 0xB76D, 0x7A56, 0xB76E, 0x7A58, 0xB76F, 0x7A59, 0xB770, 0x7A5A,
+ 0xB771, 0x7A5B, 0xB772, 0x7A5C, 0xB773, 0x7A5D, 0xB774, 0x7A5E, 0xB775, 0x7A5F, 0xB776, 0x7A60, 0xB777, 0x7A61, 0xB778, 0x7A62,
+ 0xB779, 0x7A63, 0xB77A, 0x7A64, 0xB77B, 0x7A65, 0xB77C, 0x7A66, 0xB77D, 0x7A67, 0xB77E, 0x7A68, 0xB780, 0x7A69, 0xB781, 0x7A6A,
+ 0xB782, 0x7A6B, 0xB783, 0x7A6C, 0xB784, 0x7A6D, 0xB785, 0x7A6E, 0xB786, 0x7A6F, 0xB787, 0x7A71, 0xB788, 0x7A72, 0xB789, 0x7A73,
+ 0xB78A, 0x7A75, 0xB78B, 0x7A7B, 0xB78C, 0x7A7C, 0xB78D, 0x7A7D, 0xB78E, 0x7A7E, 0xB78F, 0x7A82, 0xB790, 0x7A85, 0xB791, 0x7A87,
+ 0xB792, 0x7A89, 0xB793, 0x7A8A, 0xB794, 0x7A8B, 0xB795, 0x7A8C, 0xB796, 0x7A8E, 0xB797, 0x7A8F, 0xB798, 0x7A90, 0xB799, 0x7A93,
+ 0xB79A, 0x7A94, 0xB79B, 0x7A99, 0xB79C, 0x7A9A, 0xB79D, 0x7A9B, 0xB79E, 0x7A9E, 0xB79F, 0x7AA1, 0xB7A0, 0x7AA2, 0xB7A1, 0x8D30,
+ 0xB7A2, 0x53D1, 0xB7A3, 0x7F5A, 0xB7A4, 0x7B4F, 0xB7A5, 0x4F10, 0xB7A6, 0x4E4F, 0xB7A7, 0x9600, 0xB7A8, 0x6CD5, 0xB7A9, 0x73D0,
+ 0xB7AA, 0x85E9, 0xB7AB, 0x5E06, 0xB7AC, 0x756A, 0xB7AD, 0x7FFB, 0xB7AE, 0x6A0A, 0xB7AF, 0x77FE, 0xB7B0, 0x9492, 0xB7B1, 0x7E41,
+ 0xB7B2, 0x51E1, 0xB7B3, 0x70E6, 0xB7B4, 0x53CD, 0xB7B5, 0x8FD4, 0xB7B6, 0x8303, 0xB7B7, 0x8D29, 0xB7B8, 0x72AF, 0xB7B9, 0x996D,
+ 0xB7BA, 0x6CDB, 0xB7BB, 0x574A, 0xB7BC, 0x82B3, 0xB7BD, 0x65B9, 0xB7BE, 0x80AA, 0xB7BF, 0x623F, 0xB7C0, 0x9632, 0xB7C1, 0x59A8,
+ 0xB7C2, 0x4EFF, 0xB7C3, 0x8BBF, 0xB7C4, 0x7EBA, 0xB7C5, 0x653E, 0xB7C6, 0x83F2, 0xB7C7, 0x975E, 0xB7C8, 0x5561, 0xB7C9, 0x98DE,
+ 0xB7CA, 0x80A5, 0xB7CB, 0x532A, 0xB7CC, 0x8BFD, 0xB7CD, 0x5420, 0xB7CE, 0x80BA, 0xB7CF, 0x5E9F, 0xB7D0, 0x6CB8, 0xB7D1, 0x8D39,
+ 0xB7D2, 0x82AC, 0xB7D3, 0x915A, 0xB7D4, 0x5429, 0xB7D5, 0x6C1B, 0xB7D6, 0x5206, 0xB7D7, 0x7EB7, 0xB7D8, 0x575F, 0xB7D9, 0x711A,
+ 0xB7DA, 0x6C7E, 0xB7DB, 0x7C89, 0xB7DC, 0x594B, 0xB7DD, 0x4EFD, 0xB7DE, 0x5FFF, 0xB7DF, 0x6124, 0xB7E0, 0x7CAA, 0xB7E1, 0x4E30,
+ 0xB7E2, 0x5C01, 0xB7E3, 0x67AB, 0xB7E4, 0x8702, 0xB7E5, 0x5CF0, 0xB7E6, 0x950B, 0xB7E7, 0x98CE, 0xB7E8, 0x75AF, 0xB7E9, 0x70FD,
+ 0xB7EA, 0x9022, 0xB7EB, 0x51AF, 0xB7EC, 0x7F1D, 0xB7ED, 0x8BBD, 0xB7EE, 0x5949, 0xB7EF, 0x51E4, 0xB7F0, 0x4F5B, 0xB7F1, 0x5426,
+ 0xB7F2, 0x592B, 0xB7F3, 0x6577, 0xB7F4, 0x80A4, 0xB7F5, 0x5B75, 0xB7F6, 0x6276, 0xB7F7, 0x62C2, 0xB7F8, 0x8F90, 0xB7F9, 0x5E45,
+ 0xB7FA, 0x6C1F, 0xB7FB, 0x7B26, 0xB7FC, 0x4F0F, 0xB7FD, 0x4FD8, 0xB7FE, 0x670D, 0xB840, 0x7AA3, 0xB841, 0x7AA4, 0xB842, 0x7AA7,
+ 0xB843, 0x7AA9, 0xB844, 0x7AAA, 0xB845, 0x7AAB, 0xB846, 0x7AAE, 0xB847, 0x7AAF, 0xB848, 0x7AB0, 0xB849, 0x7AB1, 0xB84A, 0x7AB2,
+ 0xB84B, 0x7AB4, 0xB84C, 0x7AB5, 0xB84D, 0x7AB6, 0xB84E, 0x7AB7, 0xB84F, 0x7AB8, 0xB850, 0x7AB9, 0xB851, 0x7ABA, 0xB852, 0x7ABB,
+ 0xB853, 0x7ABC, 0xB854, 0x7ABD, 0xB855, 0x7ABE, 0xB856, 0x7AC0, 0xB857, 0x7AC1, 0xB858, 0x7AC2, 0xB859, 0x7AC3, 0xB85A, 0x7AC4,
+ 0xB85B, 0x7AC5, 0xB85C, 0x7AC6, 0xB85D, 0x7AC7, 0xB85E, 0x7AC8, 0xB85F, 0x7AC9, 0xB860, 0x7ACA, 0xB861, 0x7ACC, 0xB862, 0x7ACD,
+ 0xB863, 0x7ACE, 0xB864, 0x7ACF, 0xB865, 0x7AD0, 0xB866, 0x7AD1, 0xB867, 0x7AD2, 0xB868, 0x7AD3, 0xB869, 0x7AD4, 0xB86A, 0x7AD5,
+ 0xB86B, 0x7AD7, 0xB86C, 0x7AD8, 0xB86D, 0x7ADA, 0xB86E, 0x7ADB, 0xB86F, 0x7ADC, 0xB870, 0x7ADD, 0xB871, 0x7AE1, 0xB872, 0x7AE2,
+ 0xB873, 0x7AE4, 0xB874, 0x7AE7, 0xB875, 0x7AE8, 0xB876, 0x7AE9, 0xB877, 0x7AEA, 0xB878, 0x7AEB, 0xB879, 0x7AEC, 0xB87A, 0x7AEE,
+ 0xB87B, 0x7AF0, 0xB87C, 0x7AF1, 0xB87D, 0x7AF2, 0xB87E, 0x7AF3, 0xB880, 0x7AF4, 0xB881, 0x7AF5, 0xB882, 0x7AF6, 0xB883, 0x7AF7,
+ 0xB884, 0x7AF8, 0xB885, 0x7AFB, 0xB886, 0x7AFC, 0xB887, 0x7AFE, 0xB888, 0x7B00, 0xB889, 0x7B01, 0xB88A, 0x7B02, 0xB88B, 0x7B05,
+ 0xB88C, 0x7B07, 0xB88D, 0x7B09, 0xB88E, 0x7B0C, 0xB88F, 0x7B0D, 0xB890, 0x7B0E, 0xB891, 0x7B10, 0xB892, 0x7B12, 0xB893, 0x7B13,
+ 0xB894, 0x7B16, 0xB895, 0x7B17, 0xB896, 0x7B18, 0xB897, 0x7B1A, 0xB898, 0x7B1C, 0xB899, 0x7B1D, 0xB89A, 0x7B1F, 0xB89B, 0x7B21,
+ 0xB89C, 0x7B22, 0xB89D, 0x7B23, 0xB89E, 0x7B27, 0xB89F, 0x7B29, 0xB8A0, 0x7B2D, 0xB8A1, 0x6D6E, 0xB8A2, 0x6DAA, 0xB8A3, 0x798F,
+ 0xB8A4, 0x88B1, 0xB8A5, 0x5F17, 0xB8A6, 0x752B, 0xB8A7, 0x629A, 0xB8A8, 0x8F85, 0xB8A9, 0x4FEF, 0xB8AA, 0x91DC, 0xB8AB, 0x65A7,
+ 0xB8AC, 0x812F, 0xB8AD, 0x8151, 0xB8AE, 0x5E9C, 0xB8AF, 0x8150, 0xB8B0, 0x8D74, 0xB8B1, 0x526F, 0xB8B2, 0x8986, 0xB8B3, 0x8D4B,
+ 0xB8B4, 0x590D, 0xB8B5, 0x5085, 0xB8B6, 0x4ED8, 0xB8B7, 0x961C, 0xB8B8, 0x7236, 0xB8B9, 0x8179, 0xB8BA, 0x8D1F, 0xB8BB, 0x5BCC,
+ 0xB8BC, 0x8BA3, 0xB8BD, 0x9644, 0xB8BE, 0x5987, 0xB8BF, 0x7F1A, 0xB8C0, 0x5490, 0xB8C1, 0x5676, 0xB8C2, 0x560E, 0xB8C3, 0x8BE5,
+ 0xB8C4, 0x6539, 0xB8C5, 0x6982, 0xB8C6, 0x9499, 0xB8C7, 0x76D6, 0xB8C8, 0x6E89, 0xB8C9, 0x5E72, 0xB8CA, 0x7518, 0xB8CB, 0x6746,
+ 0xB8CC, 0x67D1, 0xB8CD, 0x7AFF, 0xB8CE, 0x809D, 0xB8CF, 0x8D76, 0xB8D0, 0x611F, 0xB8D1, 0x79C6, 0xB8D2, 0x6562, 0xB8D3, 0x8D63,
+ 0xB8D4, 0x5188, 0xB8D5, 0x521A, 0xB8D6, 0x94A2, 0xB8D7, 0x7F38, 0xB8D8, 0x809B, 0xB8D9, 0x7EB2, 0xB8DA, 0x5C97, 0xB8DB, 0x6E2F,
+ 0xB8DC, 0x6760, 0xB8DD, 0x7BD9, 0xB8DE, 0x768B, 0xB8DF, 0x9AD8, 0xB8E0, 0x818F, 0xB8E1, 0x7F94, 0xB8E2, 0x7CD5, 0xB8E3, 0x641E,
+ 0xB8E4, 0x9550, 0xB8E5, 0x7A3F, 0xB8E6, 0x544A, 0xB8E7, 0x54E5, 0xB8E8, 0x6B4C, 0xB8E9, 0x6401, 0xB8EA, 0x6208, 0xB8EB, 0x9E3D,
+ 0xB8EC, 0x80F3, 0xB8ED, 0x7599, 0xB8EE, 0x5272, 0xB8EF, 0x9769, 0xB8F0, 0x845B, 0xB8F1, 0x683C, 0xB8F2, 0x86E4, 0xB8F3, 0x9601,
+ 0xB8F4, 0x9694, 0xB8F5, 0x94EC, 0xB8F6, 0x4E2A, 0xB8F7, 0x5404, 0xB8F8, 0x7ED9, 0xB8F9, 0x6839, 0xB8FA, 0x8DDF, 0xB8FB, 0x8015,
+ 0xB8FC, 0x66F4, 0xB8FD, 0x5E9A, 0xB8FE, 0x7FB9, 0xB940, 0x7B2F, 0xB941, 0x7B30, 0xB942, 0x7B32, 0xB943, 0x7B34, 0xB944, 0x7B35,
+ 0xB945, 0x7B36, 0xB946, 0x7B37, 0xB947, 0x7B39, 0xB948, 0x7B3B, 0xB949, 0x7B3D, 0xB94A, 0x7B3F, 0xB94B, 0x7B40, 0xB94C, 0x7B41,
+ 0xB94D, 0x7B42, 0xB94E, 0x7B43, 0xB94F, 0x7B44, 0xB950, 0x7B46, 0xB951, 0x7B48, 0xB952, 0x7B4A, 0xB953, 0x7B4D, 0xB954, 0x7B4E,
+ 0xB955, 0x7B53, 0xB956, 0x7B55, 0xB957, 0x7B57, 0xB958, 0x7B59, 0xB959, 0x7B5C, 0xB95A, 0x7B5E, 0xB95B, 0x7B5F, 0xB95C, 0x7B61,
+ 0xB95D, 0x7B63, 0xB95E, 0x7B64, 0xB95F, 0x7B65, 0xB960, 0x7B66, 0xB961, 0x7B67, 0xB962, 0x7B68, 0xB963, 0x7B69, 0xB964, 0x7B6A,
+ 0xB965, 0x7B6B, 0xB966, 0x7B6C, 0xB967, 0x7B6D, 0xB968, 0x7B6F, 0xB969, 0x7B70, 0xB96A, 0x7B73, 0xB96B, 0x7B74, 0xB96C, 0x7B76,
+ 0xB96D, 0x7B78, 0xB96E, 0x7B7A, 0xB96F, 0x7B7C, 0xB970, 0x7B7D, 0xB971, 0x7B7F, 0xB972, 0x7B81, 0xB973, 0x7B82, 0xB974, 0x7B83,
+ 0xB975, 0x7B84, 0xB976, 0x7B86, 0xB977, 0x7B87, 0xB978, 0x7B88, 0xB979, 0x7B89, 0xB97A, 0x7B8A, 0xB97B, 0x7B8B, 0xB97C, 0x7B8C,
+ 0xB97D, 0x7B8E, 0xB97E, 0x7B8F, 0xB980, 0x7B91, 0xB981, 0x7B92, 0xB982, 0x7B93, 0xB983, 0x7B96, 0xB984, 0x7B98, 0xB985, 0x7B99,
+ 0xB986, 0x7B9A, 0xB987, 0x7B9B, 0xB988, 0x7B9E, 0xB989, 0x7B9F, 0xB98A, 0x7BA0, 0xB98B, 0x7BA3, 0xB98C, 0x7BA4, 0xB98D, 0x7BA5,
+ 0xB98E, 0x7BAE, 0xB98F, 0x7BAF, 0xB990, 0x7BB0, 0xB991, 0x7BB2, 0xB992, 0x7BB3, 0xB993, 0x7BB5, 0xB994, 0x7BB6, 0xB995, 0x7BB7,
+ 0xB996, 0x7BB9, 0xB997, 0x7BBA, 0xB998, 0x7BBB, 0xB999, 0x7BBC, 0xB99A, 0x7BBD, 0xB99B, 0x7BBE, 0xB99C, 0x7BBF, 0xB99D, 0x7BC0,
+ 0xB99E, 0x7BC2, 0xB99F, 0x7BC3, 0xB9A0, 0x7BC4, 0xB9A1, 0x57C2, 0xB9A2, 0x803F, 0xB9A3, 0x6897, 0xB9A4, 0x5DE5, 0xB9A5, 0x653B,
+ 0xB9A6, 0x529F, 0xB9A7, 0x606D, 0xB9A8, 0x9F9A, 0xB9A9, 0x4F9B, 0xB9AA, 0x8EAC, 0xB9AB, 0x516C, 0xB9AC, 0x5BAB, 0xB9AD, 0x5F13,
+ 0xB9AE, 0x5DE9, 0xB9AF, 0x6C5E, 0xB9B0, 0x62F1, 0xB9B1, 0x8D21, 0xB9B2, 0x5171, 0xB9B3, 0x94A9, 0xB9B4, 0x52FE, 0xB9B5, 0x6C9F,
+ 0xB9B6, 0x82DF, 0xB9B7, 0x72D7, 0xB9B8, 0x57A2, 0xB9B9, 0x6784, 0xB9BA, 0x8D2D, 0xB9BB, 0x591F, 0xB9BC, 0x8F9C, 0xB9BD, 0x83C7,
+ 0xB9BE, 0x5495, 0xB9BF, 0x7B8D, 0xB9C0, 0x4F30, 0xB9C1, 0x6CBD, 0xB9C2, 0x5B64, 0xB9C3, 0x59D1, 0xB9C4, 0x9F13, 0xB9C5, 0x53E4,
+ 0xB9C6, 0x86CA, 0xB9C7, 0x9AA8, 0xB9C8, 0x8C37, 0xB9C9, 0x80A1, 0xB9CA, 0x6545, 0xB9CB, 0x987E, 0xB9CC, 0x56FA, 0xB9CD, 0x96C7,
+ 0xB9CE, 0x522E, 0xB9CF, 0x74DC, 0xB9D0, 0x5250, 0xB9D1, 0x5BE1, 0xB9D2, 0x6302, 0xB9D3, 0x8902, 0xB9D4, 0x4E56, 0xB9D5, 0x62D0,
+ 0xB9D6, 0x602A, 0xB9D7, 0x68FA, 0xB9D8, 0x5173, 0xB9D9, 0x5B98, 0xB9DA, 0x51A0, 0xB9DB, 0x89C2, 0xB9DC, 0x7BA1, 0xB9DD, 0x9986,
+ 0xB9DE, 0x7F50, 0xB9DF, 0x60EF, 0xB9E0, 0x704C, 0xB9E1, 0x8D2F, 0xB9E2, 0x5149, 0xB9E3, 0x5E7F, 0xB9E4, 0x901B, 0xB9E5, 0x7470,
+ 0xB9E6, 0x89C4, 0xB9E7, 0x572D, 0xB9E8, 0x7845, 0xB9E9, 0x5F52, 0xB9EA, 0x9F9F, 0xB9EB, 0x95FA, 0xB9EC, 0x8F68, 0xB9ED, 0x9B3C,
+ 0xB9EE, 0x8BE1, 0xB9EF, 0x7678, 0xB9F0, 0x6842, 0xB9F1, 0x67DC, 0xB9F2, 0x8DEA, 0xB9F3, 0x8D35, 0xB9F4, 0x523D, 0xB9F5, 0x8F8A,
+ 0xB9F6, 0x6EDA, 0xB9F7, 0x68CD, 0xB9F8, 0x9505, 0xB9F9, 0x90ED, 0xB9FA, 0x56FD, 0xB9FB, 0x679C, 0xB9FC, 0x88F9, 0xB9FD, 0x8FC7,
+ 0xB9FE, 0x54C8, 0xBA40, 0x7BC5, 0xBA41, 0x7BC8, 0xBA42, 0x7BC9, 0xBA43, 0x7BCA, 0xBA44, 0x7BCB, 0xBA45, 0x7BCD, 0xBA46, 0x7BCE,
+ 0xBA47, 0x7BCF, 0xBA48, 0x7BD0, 0xBA49, 0x7BD2, 0xBA4A, 0x7BD4, 0xBA4B, 0x7BD5, 0xBA4C, 0x7BD6, 0xBA4D, 0x7BD7, 0xBA4E, 0x7BD8,
+ 0xBA4F, 0x7BDB, 0xBA50, 0x7BDC, 0xBA51, 0x7BDE, 0xBA52, 0x7BDF, 0xBA53, 0x7BE0, 0xBA54, 0x7BE2, 0xBA55, 0x7BE3, 0xBA56, 0x7BE4,
+ 0xBA57, 0x7BE7, 0xBA58, 0x7BE8, 0xBA59, 0x7BE9, 0xBA5A, 0x7BEB, 0xBA5B, 0x7BEC, 0xBA5C, 0x7BED, 0xBA5D, 0x7BEF, 0xBA5E, 0x7BF0,
+ 0xBA5F, 0x7BF2, 0xBA60, 0x7BF3, 0xBA61, 0x7BF4, 0xBA62, 0x7BF5, 0xBA63, 0x7BF6, 0xBA64, 0x7BF8, 0xBA65, 0x7BF9, 0xBA66, 0x7BFA,
+ 0xBA67, 0x7BFB, 0xBA68, 0x7BFD, 0xBA69, 0x7BFF, 0xBA6A, 0x7C00, 0xBA6B, 0x7C01, 0xBA6C, 0x7C02, 0xBA6D, 0x7C03, 0xBA6E, 0x7C04,
+ 0xBA6F, 0x7C05, 0xBA70, 0x7C06, 0xBA71, 0x7C08, 0xBA72, 0x7C09, 0xBA73, 0x7C0A, 0xBA74, 0x7C0D, 0xBA75, 0x7C0E, 0xBA76, 0x7C10,
+ 0xBA77, 0x7C11, 0xBA78, 0x7C12, 0xBA79, 0x7C13, 0xBA7A, 0x7C14, 0xBA7B, 0x7C15, 0xBA7C, 0x7C17, 0xBA7D, 0x7C18, 0xBA7E, 0x7C19,
+ 0xBA80, 0x7C1A, 0xBA81, 0x7C1B, 0xBA82, 0x7C1C, 0xBA83, 0x7C1D, 0xBA84, 0x7C1E, 0xBA85, 0x7C20, 0xBA86, 0x7C21, 0xBA87, 0x7C22,
+ 0xBA88, 0x7C23, 0xBA89, 0x7C24, 0xBA8A, 0x7C25, 0xBA8B, 0x7C28, 0xBA8C, 0x7C29, 0xBA8D, 0x7C2B, 0xBA8E, 0x7C2C, 0xBA8F, 0x7C2D,
+ 0xBA90, 0x7C2E, 0xBA91, 0x7C2F, 0xBA92, 0x7C30, 0xBA93, 0x7C31, 0xBA94, 0x7C32, 0xBA95, 0x7C33, 0xBA96, 0x7C34, 0xBA97, 0x7C35,
+ 0xBA98, 0x7C36, 0xBA99, 0x7C37, 0xBA9A, 0x7C39, 0xBA9B, 0x7C3A, 0xBA9C, 0x7C3B, 0xBA9D, 0x7C3C, 0xBA9E, 0x7C3D, 0xBA9F, 0x7C3E,
+ 0xBAA0, 0x7C42, 0xBAA1, 0x9AB8, 0xBAA2, 0x5B69, 0xBAA3, 0x6D77, 0xBAA4, 0x6C26, 0xBAA5, 0x4EA5, 0xBAA6, 0x5BB3, 0xBAA7, 0x9A87,
+ 0xBAA8, 0x9163, 0xBAA9, 0x61A8, 0xBAAA, 0x90AF, 0xBAAB, 0x97E9, 0xBAAC, 0x542B, 0xBAAD, 0x6DB5, 0xBAAE, 0x5BD2, 0xBAAF, 0x51FD,
+ 0xBAB0, 0x558A, 0xBAB1, 0x7F55, 0xBAB2, 0x7FF0, 0xBAB3, 0x64BC, 0xBAB4, 0x634D, 0xBAB5, 0x65F1, 0xBAB6, 0x61BE, 0xBAB7, 0x608D,
+ 0xBAB8, 0x710A, 0xBAB9, 0x6C57, 0xBABA, 0x6C49, 0xBABB, 0x592F, 0xBABC, 0x676D, 0xBABD, 0x822A, 0xBABE, 0x58D5, 0xBABF, 0x568E,
+ 0xBAC0, 0x8C6A, 0xBAC1, 0x6BEB, 0xBAC2, 0x90DD, 0xBAC3, 0x597D, 0xBAC4, 0x8017, 0xBAC5, 0x53F7, 0xBAC6, 0x6D69, 0xBAC7, 0x5475,
+ 0xBAC8, 0x559D, 0xBAC9, 0x8377, 0xBACA, 0x83CF, 0xBACB, 0x6838, 0xBACC, 0x79BE, 0xBACD, 0x548C, 0xBACE, 0x4F55, 0xBACF, 0x5408,
+ 0xBAD0, 0x76D2, 0xBAD1, 0x8C89, 0xBAD2, 0x9602, 0xBAD3, 0x6CB3, 0xBAD4, 0x6DB8, 0xBAD5, 0x8D6B, 0xBAD6, 0x8910, 0xBAD7, 0x9E64,
+ 0xBAD8, 0x8D3A, 0xBAD9, 0x563F, 0xBADA, 0x9ED1, 0xBADB, 0x75D5, 0xBADC, 0x5F88, 0xBADD, 0x72E0, 0xBADE, 0x6068, 0xBADF, 0x54FC,
+ 0xBAE0, 0x4EA8, 0xBAE1, 0x6A2A, 0xBAE2, 0x8861, 0xBAE3, 0x6052, 0xBAE4, 0x8F70, 0xBAE5, 0x54C4, 0xBAE6, 0x70D8, 0xBAE7, 0x8679,
+ 0xBAE8, 0x9E3F, 0xBAE9, 0x6D2A, 0xBAEA, 0x5B8F, 0xBAEB, 0x5F18, 0xBAEC, 0x7EA2, 0xBAED, 0x5589, 0xBAEE, 0x4FAF, 0xBAEF, 0x7334,
+ 0xBAF0, 0x543C, 0xBAF1, 0x539A, 0xBAF2, 0x5019, 0xBAF3, 0x540E, 0xBAF4, 0x547C, 0xBAF5, 0x4E4E, 0xBAF6, 0x5FFD, 0xBAF7, 0x745A,
+ 0xBAF8, 0x58F6, 0xBAF9, 0x846B, 0xBAFA, 0x80E1, 0xBAFB, 0x8774, 0xBAFC, 0x72D0, 0xBAFD, 0x7CCA, 0xBAFE, 0x6E56, 0xBB40, 0x7C43,
+ 0xBB41, 0x7C44, 0xBB42, 0x7C45, 0xBB43, 0x7C46, 0xBB44, 0x7C47, 0xBB45, 0x7C48, 0xBB46, 0x7C49, 0xBB47, 0x7C4A, 0xBB48, 0x7C4B,
+ 0xBB49, 0x7C4C, 0xBB4A, 0x7C4E, 0xBB4B, 0x7C4F, 0xBB4C, 0x7C50, 0xBB4D, 0x7C51, 0xBB4E, 0x7C52, 0xBB4F, 0x7C53, 0xBB50, 0x7C54,
+ 0xBB51, 0x7C55, 0xBB52, 0x7C56, 0xBB53, 0x7C57, 0xBB54, 0x7C58, 0xBB55, 0x7C59, 0xBB56, 0x7C5A, 0xBB57, 0x7C5B, 0xBB58, 0x7C5C,
+ 0xBB59, 0x7C5D, 0xBB5A, 0x7C5E, 0xBB5B, 0x7C5F, 0xBB5C, 0x7C60, 0xBB5D, 0x7C61, 0xBB5E, 0x7C62, 0xBB5F, 0x7C63, 0xBB60, 0x7C64,
+ 0xBB61, 0x7C65, 0xBB62, 0x7C66, 0xBB63, 0x7C67, 0xBB64, 0x7C68, 0xBB65, 0x7C69, 0xBB66, 0x7C6A, 0xBB67, 0x7C6B, 0xBB68, 0x7C6C,
+ 0xBB69, 0x7C6D, 0xBB6A, 0x7C6E, 0xBB6B, 0x7C6F, 0xBB6C, 0x7C70, 0xBB6D, 0x7C71, 0xBB6E, 0x7C72, 0xBB6F, 0x7C75, 0xBB70, 0x7C76,
+ 0xBB71, 0x7C77, 0xBB72, 0x7C78, 0xBB73, 0x7C79, 0xBB74, 0x7C7A, 0xBB75, 0x7C7E, 0xBB76, 0x7C7F, 0xBB77, 0x7C80, 0xBB78, 0x7C81,
+ 0xBB79, 0x7C82, 0xBB7A, 0x7C83, 0xBB7B, 0x7C84, 0xBB7C, 0x7C85, 0xBB7D, 0x7C86, 0xBB7E, 0x7C87, 0xBB80, 0x7C88, 0xBB81, 0x7C8A,
+ 0xBB82, 0x7C8B, 0xBB83, 0x7C8C, 0xBB84, 0x7C8D, 0xBB85, 0x7C8E, 0xBB86, 0x7C8F, 0xBB87, 0x7C90, 0xBB88, 0x7C93, 0xBB89, 0x7C94,
+ 0xBB8A, 0x7C96, 0xBB8B, 0x7C99, 0xBB8C, 0x7C9A, 0xBB8D, 0x7C9B, 0xBB8E, 0x7CA0, 0xBB8F, 0x7CA1, 0xBB90, 0x7CA3, 0xBB91, 0x7CA6,
+ 0xBB92, 0x7CA7, 0xBB93, 0x7CA8, 0xBB94, 0x7CA9, 0xBB95, 0x7CAB, 0xBB96, 0x7CAC, 0xBB97, 0x7CAD, 0xBB98, 0x7CAF, 0xBB99, 0x7CB0,
+ 0xBB9A, 0x7CB4, 0xBB9B, 0x7CB5, 0xBB9C, 0x7CB6, 0xBB9D, 0x7CB7, 0xBB9E, 0x7CB8, 0xBB9F, 0x7CBA, 0xBBA0, 0x7CBB, 0xBBA1, 0x5F27,
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+ 0xBF59, 0x7E14, 0xBF5A, 0x7E15, 0xBF5B, 0x7E16, 0xBF5C, 0x7E17, 0xBF5D, 0x7E18, 0xBF5E, 0x7E19, 0xBF5F, 0x7E1A, 0xBF60, 0x7E1B,
+ 0xBF61, 0x7E1C, 0xBF62, 0x7E1D, 0xBF63, 0x7E1E, 0xBF64, 0x7E1F, 0xBF65, 0x7E20, 0xBF66, 0x7E21, 0xBF67, 0x7E22, 0xBF68, 0x7E23,
+ 0xBF69, 0x7E24, 0xBF6A, 0x7E25, 0xBF6B, 0x7E26, 0xBF6C, 0x7E27, 0xBF6D, 0x7E28, 0xBF6E, 0x7E29, 0xBF6F, 0x7E2A, 0xBF70, 0x7E2B,
+ 0xBF71, 0x7E2C, 0xBF72, 0x7E2D, 0xBF73, 0x7E2E, 0xBF74, 0x7E2F, 0xBF75, 0x7E30, 0xBF76, 0x7E31, 0xBF77, 0x7E32, 0xBF78, 0x7E33,
+ 0xBF79, 0x7E34, 0xBF7A, 0x7E35, 0xBF7B, 0x7E36, 0xBF7C, 0x7E37, 0xBF7D, 0x7E38, 0xBF7E, 0x7E39, 0xBF80, 0x7E3A, 0xBF81, 0x7E3C,
+ 0xBF82, 0x7E3D, 0xBF83, 0x7E3E, 0xBF84, 0x7E3F, 0xBF85, 0x7E40, 0xBF86, 0x7E42, 0xBF87, 0x7E43, 0xBF88, 0x7E44, 0xBF89, 0x7E45,
+ 0xBF8A, 0x7E46, 0xBF8B, 0x7E48, 0xBF8C, 0x7E49, 0xBF8D, 0x7E4A, 0xBF8E, 0x7E4B, 0xBF8F, 0x7E4C, 0xBF90, 0x7E4D, 0xBF91, 0x7E4E,
+ 0xBF92, 0x7E4F, 0xBF93, 0x7E50, 0xBF94, 0x7E51, 0xBF95, 0x7E52, 0xBF96, 0x7E53, 0xBF97, 0x7E54, 0xBF98, 0x7E55, 0xBF99, 0x7E56,
+ 0xBF9A, 0x7E57, 0xBF9B, 0x7E58, 0xBF9C, 0x7E59, 0xBF9D, 0x7E5A, 0xBF9E, 0x7E5B, 0xBF9F, 0x7E5C, 0xBFA0, 0x7E5D, 0xBFA1, 0x4FCA,
+ 0xBFA2, 0x7AE3, 0xBFA3, 0x6D5A, 0xBFA4, 0x90E1, 0xBFA5, 0x9A8F, 0xBFA6, 0x5580, 0xBFA7, 0x5496, 0xBFA8, 0x5361, 0xBFA9, 0x54AF,
+ 0xBFAA, 0x5F00, 0xBFAB, 0x63E9, 0xBFAC, 0x6977, 0xBFAD, 0x51EF, 0xBFAE, 0x6168, 0xBFAF, 0x520A, 0xBFB0, 0x582A, 0xBFB1, 0x52D8,
+ 0xBFB2, 0x574E, 0xBFB3, 0x780D, 0xBFB4, 0x770B, 0xBFB5, 0x5EB7, 0xBFB6, 0x6177, 0xBFB7, 0x7CE0, 0xBFB8, 0x625B, 0xBFB9, 0x6297,
+ 0xBFBA, 0x4EA2, 0xBFBB, 0x7095, 0xBFBC, 0x8003, 0xBFBD, 0x62F7, 0xBFBE, 0x70E4, 0xBFBF, 0x9760, 0xBFC0, 0x5777, 0xBFC1, 0x82DB,
+ 0xBFC2, 0x67EF, 0xBFC3, 0x68F5, 0xBFC4, 0x78D5, 0xBFC5, 0x9897, 0xBFC6, 0x79D1, 0xBFC7, 0x58F3, 0xBFC8, 0x54B3, 0xBFC9, 0x53EF,
+ 0xBFCA, 0x6E34, 0xBFCB, 0x514B, 0xBFCC, 0x523B, 0xBFCD, 0x5BA2, 0xBFCE, 0x8BFE, 0xBFCF, 0x80AF, 0xBFD0, 0x5543, 0xBFD1, 0x57A6,
+ 0xBFD2, 0x6073, 0xBFD3, 0x5751, 0xBFD4, 0x542D, 0xBFD5, 0x7A7A, 0xBFD6, 0x6050, 0xBFD7, 0x5B54, 0xBFD8, 0x63A7, 0xBFD9, 0x62A0,
+ 0xBFDA, 0x53E3, 0xBFDB, 0x6263, 0xBFDC, 0x5BC7, 0xBFDD, 0x67AF, 0xBFDE, 0x54ED, 0xBFDF, 0x7A9F, 0xBFE0, 0x82E6, 0xBFE1, 0x9177,
+ 0xBFE2, 0x5E93, 0xBFE3, 0x88E4, 0xBFE4, 0x5938, 0xBFE5, 0x57AE, 0xBFE6, 0x630E, 0xBFE7, 0x8DE8, 0xBFE8, 0x80EF, 0xBFE9, 0x5757,
+ 0xBFEA, 0x7B77, 0xBFEB, 0x4FA9, 0xBFEC, 0x5FEB, 0xBFED, 0x5BBD, 0xBFEE, 0x6B3E, 0xBFEF, 0x5321, 0xBFF0, 0x7B50, 0xBFF1, 0x72C2,
+ 0xBFF2, 0x6846, 0xBFF3, 0x77FF, 0xBFF4, 0x7736, 0xBFF5, 0x65F7, 0xBFF6, 0x51B5, 0xBFF7, 0x4E8F, 0xBFF8, 0x76D4, 0xBFF9, 0x5CBF,
+ 0xBFFA, 0x7AA5, 0xBFFB, 0x8475, 0xBFFC, 0x594E, 0xBFFD, 0x9B41, 0xBFFE, 0x5080, 0xC040, 0x7E5E, 0xC041, 0x7E5F, 0xC042, 0x7E60,
+ 0xC043, 0x7E61, 0xC044, 0x7E62, 0xC045, 0x7E63, 0xC046, 0x7E64, 0xC047, 0x7E65, 0xC048, 0x7E66, 0xC049, 0x7E67, 0xC04A, 0x7E68,
+ 0xC04B, 0x7E69, 0xC04C, 0x7E6A, 0xC04D, 0x7E6B, 0xC04E, 0x7E6C, 0xC04F, 0x7E6D, 0xC050, 0x7E6E, 0xC051, 0x7E6F, 0xC052, 0x7E70,
+ 0xC053, 0x7E71, 0xC054, 0x7E72, 0xC055, 0x7E73, 0xC056, 0x7E74, 0xC057, 0x7E75, 0xC058, 0x7E76, 0xC059, 0x7E77, 0xC05A, 0x7E78,
+ 0xC05B, 0x7E79, 0xC05C, 0x7E7A, 0xC05D, 0x7E7B, 0xC05E, 0x7E7C, 0xC05F, 0x7E7D, 0xC060, 0x7E7E, 0xC061, 0x7E7F, 0xC062, 0x7E80,
+ 0xC063, 0x7E81, 0xC064, 0x7E83, 0xC065, 0x7E84, 0xC066, 0x7E85, 0xC067, 0x7E86, 0xC068, 0x7E87, 0xC069, 0x7E88, 0xC06A, 0x7E89,
+ 0xC06B, 0x7E8A, 0xC06C, 0x7E8B, 0xC06D, 0x7E8C, 0xC06E, 0x7E8D, 0xC06F, 0x7E8E, 0xC070, 0x7E8F, 0xC071, 0x7E90, 0xC072, 0x7E91,
+ 0xC073, 0x7E92, 0xC074, 0x7E93, 0xC075, 0x7E94, 0xC076, 0x7E95, 0xC077, 0x7E96, 0xC078, 0x7E97, 0xC079, 0x7E98, 0xC07A, 0x7E99,
+ 0xC07B, 0x7E9A, 0xC07C, 0x7E9C, 0xC07D, 0x7E9D, 0xC07E, 0x7E9E, 0xC080, 0x7EAE, 0xC081, 0x7EB4, 0xC082, 0x7EBB, 0xC083, 0x7EBC,
+ 0xC084, 0x7ED6, 0xC085, 0x7EE4, 0xC086, 0x7EEC, 0xC087, 0x7EF9, 0xC088, 0x7F0A, 0xC089, 0x7F10, 0xC08A, 0x7F1E, 0xC08B, 0x7F37,
+ 0xC08C, 0x7F39, 0xC08D, 0x7F3B, 0xC08E, 0x7F3C, 0xC08F, 0x7F3D, 0xC090, 0x7F3E, 0xC091, 0x7F3F, 0xC092, 0x7F40, 0xC093, 0x7F41,
+ 0xC094, 0x7F43, 0xC095, 0x7F46, 0xC096, 0x7F47, 0xC097, 0x7F48, 0xC098, 0x7F49, 0xC099, 0x7F4A, 0xC09A, 0x7F4B, 0xC09B, 0x7F4C,
+ 0xC09C, 0x7F4D, 0xC09D, 0x7F4E, 0xC09E, 0x7F4F, 0xC09F, 0x7F52, 0xC0A0, 0x7F53, 0xC0A1, 0x9988, 0xC0A2, 0x6127, 0xC0A3, 0x6E83,
+ 0xC0A4, 0x5764, 0xC0A5, 0x6606, 0xC0A6, 0x6346, 0xC0A7, 0x56F0, 0xC0A8, 0x62EC, 0xC0A9, 0x6269, 0xC0AA, 0x5ED3, 0xC0AB, 0x9614,
+ 0xC0AC, 0x5783, 0xC0AD, 0x62C9, 0xC0AE, 0x5587, 0xC0AF, 0x8721, 0xC0B0, 0x814A, 0xC0B1, 0x8FA3, 0xC0B2, 0x5566, 0xC0B3, 0x83B1,
+ 0xC0B4, 0x6765, 0xC0B5, 0x8D56, 0xC0B6, 0x84DD, 0xC0B7, 0x5A6A, 0xC0B8, 0x680F, 0xC0B9, 0x62E6, 0xC0BA, 0x7BEE, 0xC0BB, 0x9611,
+ 0xC0BC, 0x5170, 0xC0BD, 0x6F9C, 0xC0BE, 0x8C30, 0xC0BF, 0x63FD, 0xC0C0, 0x89C8, 0xC0C1, 0x61D2, 0xC0C2, 0x7F06, 0xC0C3, 0x70C2,
+ 0xC0C4, 0x6EE5, 0xC0C5, 0x7405, 0xC0C6, 0x6994, 0xC0C7, 0x72FC, 0xC0C8, 0x5ECA, 0xC0C9, 0x90CE, 0xC0CA, 0x6717, 0xC0CB, 0x6D6A,
+ 0xC0CC, 0x635E, 0xC0CD, 0x52B3, 0xC0CE, 0x7262, 0xC0CF, 0x8001, 0xC0D0, 0x4F6C, 0xC0D1, 0x59E5, 0xC0D2, 0x916A, 0xC0D3, 0x70D9,
+ 0xC0D4, 0x6D9D, 0xC0D5, 0x52D2, 0xC0D6, 0x4E50, 0xC0D7, 0x96F7, 0xC0D8, 0x956D, 0xC0D9, 0x857E, 0xC0DA, 0x78CA, 0xC0DB, 0x7D2F,
+ 0xC0DC, 0x5121, 0xC0DD, 0x5792, 0xC0DE, 0x64C2, 0xC0DF, 0x808B, 0xC0E0, 0x7C7B, 0xC0E1, 0x6CEA, 0xC0E2, 0x68F1, 0xC0E3, 0x695E,
+ 0xC0E4, 0x51B7, 0xC0E5, 0x5398, 0xC0E6, 0x68A8, 0xC0E7, 0x7281, 0xC0E8, 0x9ECE, 0xC0E9, 0x7BF1, 0xC0EA, 0x72F8, 0xC0EB, 0x79BB,
+ 0xC0EC, 0x6F13, 0xC0ED, 0x7406, 0xC0EE, 0x674E, 0xC0EF, 0x91CC, 0xC0F0, 0x9CA4, 0xC0F1, 0x793C, 0xC0F2, 0x8389, 0xC0F3, 0x8354,
+ 0xC0F4, 0x540F, 0xC0F5, 0x6817, 0xC0F6, 0x4E3D, 0xC0F7, 0x5389, 0xC0F8, 0x52B1, 0xC0F9, 0x783E, 0xC0FA, 0x5386, 0xC0FB, 0x5229,
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+ 0xC145, 0x7F5E, 0xC146, 0x7F60, 0xC147, 0x7F63, 0xC148, 0x7F64, 0xC149, 0x7F65, 0xC14A, 0x7F66, 0xC14B, 0x7F67, 0xC14C, 0x7F6B,
+ 0xC14D, 0x7F6C, 0xC14E, 0x7F6D, 0xC14F, 0x7F6F, 0xC150, 0x7F70, 0xC151, 0x7F73, 0xC152, 0x7F75, 0xC153, 0x7F76, 0xC154, 0x7F77,
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+ 0xC15D, 0x7F83, 0xC15E, 0x7F84, 0xC15F, 0x7F85, 0xC160, 0x7F86, 0xC161, 0x7F87, 0xC162, 0x7F88, 0xC163, 0x7F89, 0xC164, 0x7F8B,
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+ 0xC175, 0x7FA5, 0xC176, 0x7FA6, 0xC177, 0x7FA8, 0xC178, 0x7FA9, 0xC179, 0x7FAA, 0xC17A, 0x7FAB, 0xC17B, 0x7FAC, 0xC17C, 0x7FAD,
+ 0xC17D, 0x7FAE, 0xC17E, 0x7FB1, 0xC180, 0x7FB3, 0xC181, 0x7FB4, 0xC182, 0x7FB5, 0xC183, 0x7FB6, 0xC184, 0x7FB7, 0xC185, 0x7FBA,
+ 0xC186, 0x7FBB, 0xC187, 0x7FBE, 0xC188, 0x7FC0, 0xC189, 0x7FC2, 0xC18A, 0x7FC3, 0xC18B, 0x7FC4, 0xC18C, 0x7FC6, 0xC18D, 0x7FC7,
+ 0xC18E, 0x7FC8, 0xC18F, 0x7FC9, 0xC190, 0x7FCB, 0xC191, 0x7FCD, 0xC192, 0x7FCF, 0xC193, 0x7FD0, 0xC194, 0x7FD1, 0xC195, 0x7FD2,
+ 0xC196, 0x7FD3, 0xC197, 0x7FD6, 0xC198, 0x7FD7, 0xC199, 0x7FD9, 0xC19A, 0x7FDA, 0xC19B, 0x7FDB, 0xC19C, 0x7FDC, 0xC19D, 0x7FDD,
+ 0xC19E, 0x7FDE, 0xC19F, 0x7FE2, 0xC1A0, 0x7FE3, 0xC1A1, 0x75E2, 0xC1A2, 0x7ACB, 0xC1A3, 0x7C92, 0xC1A4, 0x6CA5, 0xC1A5, 0x96B6,
+ 0xC1A6, 0x529B, 0xC1A7, 0x7483, 0xC1A8, 0x54E9, 0xC1A9, 0x4FE9, 0xC1AA, 0x8054, 0xC1AB, 0x83B2, 0xC1AC, 0x8FDE, 0xC1AD, 0x9570,
+ 0xC1AE, 0x5EC9, 0xC1AF, 0x601C, 0xC1B0, 0x6D9F, 0xC1B1, 0x5E18, 0xC1B2, 0x655B, 0xC1B3, 0x8138, 0xC1B4, 0x94FE, 0xC1B5, 0x604B,
+ 0xC1B6, 0x70BC, 0xC1B7, 0x7EC3, 0xC1B8, 0x7CAE, 0xC1B9, 0x51C9, 0xC1BA, 0x6881, 0xC1BB, 0x7CB1, 0xC1BC, 0x826F, 0xC1BD, 0x4E24,
+ 0xC1BE, 0x8F86, 0xC1BF, 0x91CF, 0xC1C0, 0x667E, 0xC1C1, 0x4EAE, 0xC1C2, 0x8C05, 0xC1C3, 0x64A9, 0xC1C4, 0x804A, 0xC1C5, 0x50DA,
+ 0xC1C6, 0x7597, 0xC1C7, 0x71CE, 0xC1C8, 0x5BE5, 0xC1C9, 0x8FBD, 0xC1CA, 0x6F66, 0xC1CB, 0x4E86, 0xC1CC, 0x6482, 0xC1CD, 0x9563,
+ 0xC1CE, 0x5ED6, 0xC1CF, 0x6599, 0xC1D0, 0x5217, 0xC1D1, 0x88C2, 0xC1D2, 0x70C8, 0xC1D3, 0x52A3, 0xC1D4, 0x730E, 0xC1D5, 0x7433,
+ 0xC1D6, 0x6797, 0xC1D7, 0x78F7, 0xC1D8, 0x9716, 0xC1D9, 0x4E34, 0xC1DA, 0x90BB, 0xC1DB, 0x9CDE, 0xC1DC, 0x6DCB, 0xC1DD, 0x51DB,
+ 0xC1DE, 0x8D41, 0xC1DF, 0x541D, 0xC1E0, 0x62CE, 0xC1E1, 0x73B2, 0xC1E2, 0x83F1, 0xC1E3, 0x96F6, 0xC1E4, 0x9F84, 0xC1E5, 0x94C3,
+ 0xC1E6, 0x4F36, 0xC1E7, 0x7F9A, 0xC1E8, 0x51CC, 0xC1E9, 0x7075, 0xC1EA, 0x9675, 0xC1EB, 0x5CAD, 0xC1EC, 0x9886, 0xC1ED, 0x53E6,
+ 0xC1EE, 0x4EE4, 0xC1EF, 0x6E9C, 0xC1F0, 0x7409, 0xC1F1, 0x69B4, 0xC1F2, 0x786B, 0xC1F3, 0x998F, 0xC1F4, 0x7559, 0xC1F5, 0x5218,
+ 0xC1F6, 0x7624, 0xC1F7, 0x6D41, 0xC1F8, 0x67F3, 0xC1F9, 0x516D, 0xC1FA, 0x9F99, 0xC1FB, 0x804B, 0xC1FC, 0x5499, 0xC1FD, 0x7B3C,
+ 0xC1FE, 0x7ABF, 0xC240, 0x7FE4, 0xC241, 0x7FE7, 0xC242, 0x7FE8, 0xC243, 0x7FEA, 0xC244, 0x7FEB, 0xC245, 0x7FEC, 0xC246, 0x7FED,
+ 0xC247, 0x7FEF, 0xC248, 0x7FF2, 0xC249, 0x7FF4, 0xC24A, 0x7FF5, 0xC24B, 0x7FF6, 0xC24C, 0x7FF7, 0xC24D, 0x7FF8, 0xC24E, 0x7FF9,
+ 0xC24F, 0x7FFA, 0xC250, 0x7FFD, 0xC251, 0x7FFE, 0xC252, 0x7FFF, 0xC253, 0x8002, 0xC254, 0x8007, 0xC255, 0x8008, 0xC256, 0x8009,
+ 0xC257, 0x800A, 0xC258, 0x800E, 0xC259, 0x800F, 0xC25A, 0x8011, 0xC25B, 0x8013, 0xC25C, 0x801A, 0xC25D, 0x801B, 0xC25E, 0x801D,
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+ 0xC267, 0x802E, 0xC268, 0x802F, 0xC269, 0x8030, 0xC26A, 0x8032, 0xC26B, 0x8034, 0xC26C, 0x8039, 0xC26D, 0x803A, 0xC26E, 0x803C,
+ 0xC26F, 0x803E, 0xC270, 0x8040, 0xC271, 0x8041, 0xC272, 0x8044, 0xC273, 0x8045, 0xC274, 0x8047, 0xC275, 0x8048, 0xC276, 0x8049,
+ 0xC277, 0x804E, 0xC278, 0x804F, 0xC279, 0x8050, 0xC27A, 0x8051, 0xC27B, 0x8053, 0xC27C, 0x8055, 0xC27D, 0x8056, 0xC27E, 0x8057,
+ 0xC280, 0x8059, 0xC281, 0x805B, 0xC282, 0x805C, 0xC283, 0x805D, 0xC284, 0x805E, 0xC285, 0x805F, 0xC286, 0x8060, 0xC287, 0x8061,
+ 0xC288, 0x8062, 0xC289, 0x8063, 0xC28A, 0x8064, 0xC28B, 0x8065, 0xC28C, 0x8066, 0xC28D, 0x8067, 0xC28E, 0x8068, 0xC28F, 0x806B,
+ 0xC290, 0x806C, 0xC291, 0x806D, 0xC292, 0x806E, 0xC293, 0x806F, 0xC294, 0x8070, 0xC295, 0x8072, 0xC296, 0x8073, 0xC297, 0x8074,
+ 0xC298, 0x8075, 0xC299, 0x8076, 0xC29A, 0x8077, 0xC29B, 0x8078, 0xC29C, 0x8079, 0xC29D, 0x807A, 0xC29E, 0x807B, 0xC29F, 0x807C,
+ 0xC2A0, 0x807D, 0xC2A1, 0x9686, 0xC2A2, 0x5784, 0xC2A3, 0x62E2, 0xC2A4, 0x9647, 0xC2A5, 0x697C, 0xC2A6, 0x5A04, 0xC2A7, 0x6402,
+ 0xC2A8, 0x7BD3, 0xC2A9, 0x6F0F, 0xC2AA, 0x964B, 0xC2AB, 0x82A6, 0xC2AC, 0x5362, 0xC2AD, 0x9885, 0xC2AE, 0x5E90, 0xC2AF, 0x7089,
+ 0xC2B0, 0x63B3, 0xC2B1, 0x5364, 0xC2B2, 0x864F, 0xC2B3, 0x9C81, 0xC2B4, 0x9E93, 0xC2B5, 0x788C, 0xC2B6, 0x9732, 0xC2B7, 0x8DEF,
+ 0xC2B8, 0x8D42, 0xC2B9, 0x9E7F, 0xC2BA, 0x6F5E, 0xC2BB, 0x7984, 0xC2BC, 0x5F55, 0xC2BD, 0x9646, 0xC2BE, 0x622E, 0xC2BF, 0x9A74,
+ 0xC2C0, 0x5415, 0xC2C1, 0x94DD, 0xC2C2, 0x4FA3, 0xC2C3, 0x65C5, 0xC2C4, 0x5C65, 0xC2C5, 0x5C61, 0xC2C6, 0x7F15, 0xC2C7, 0x8651,
+ 0xC2C8, 0x6C2F, 0xC2C9, 0x5F8B, 0xC2CA, 0x7387, 0xC2CB, 0x6EE4, 0xC2CC, 0x7EFF, 0xC2CD, 0x5CE6, 0xC2CE, 0x631B, 0xC2CF, 0x5B6A,
+ 0xC2D0, 0x6EE6, 0xC2D1, 0x5375, 0xC2D2, 0x4E71, 0xC2D3, 0x63A0, 0xC2D4, 0x7565, 0xC2D5, 0x62A1, 0xC2D6, 0x8F6E, 0xC2D7, 0x4F26,
+ 0xC2D8, 0x4ED1, 0xC2D9, 0x6CA6, 0xC2DA, 0x7EB6, 0xC2DB, 0x8BBA, 0xC2DC, 0x841D, 0xC2DD, 0x87BA, 0xC2DE, 0x7F57, 0xC2DF, 0x903B,
+ 0xC2E0, 0x9523, 0xC2E1, 0x7BA9, 0xC2E2, 0x9AA1, 0xC2E3, 0x88F8, 0xC2E4, 0x843D, 0xC2E5, 0x6D1B, 0xC2E6, 0x9A86, 0xC2E7, 0x7EDC,
+ 0xC2E8, 0x5988, 0xC2E9, 0x9EBB, 0xC2EA, 0x739B, 0xC2EB, 0x7801, 0xC2EC, 0x8682, 0xC2ED, 0x9A6C, 0xC2EE, 0x9A82, 0xC2EF, 0x561B,
+ 0xC2F0, 0x5417, 0xC2F1, 0x57CB, 0xC2F2, 0x4E70, 0xC2F3, 0x9EA6, 0xC2F4, 0x5356, 0xC2F5, 0x8FC8, 0xC2F6, 0x8109, 0xC2F7, 0x7792,
+ 0xC2F8, 0x9992, 0xC2F9, 0x86EE, 0xC2FA, 0x6EE1, 0xC2FB, 0x8513, 0xC2FC, 0x66FC, 0xC2FD, 0x6162, 0xC2FE, 0x6F2B, 0xC340, 0x807E,
+ 0xC341, 0x8081, 0xC342, 0x8082, 0xC343, 0x8085, 0xC344, 0x8088, 0xC345, 0x808A, 0xC346, 0x808D, 0xC347, 0x808E, 0xC348, 0x808F,
+ 0xC349, 0x8090, 0xC34A, 0x8091, 0xC34B, 0x8092, 0xC34C, 0x8094, 0xC34D, 0x8095, 0xC34E, 0x8097, 0xC34F, 0x8099, 0xC350, 0x809E,
+ 0xC351, 0x80A3, 0xC352, 0x80A6, 0xC353, 0x80A7, 0xC354, 0x80A8, 0xC355, 0x80AC, 0xC356, 0x80B0, 0xC357, 0x80B3, 0xC358, 0x80B5,
+ 0xC359, 0x80B6, 0xC35A, 0x80B8, 0xC35B, 0x80B9, 0xC35C, 0x80BB, 0xC35D, 0x80C5, 0xC35E, 0x80C7, 0xC35F, 0x80C8, 0xC360, 0x80C9,
+ 0xC361, 0x80CA, 0xC362, 0x80CB, 0xC363, 0x80CF, 0xC364, 0x80D0, 0xC365, 0x80D1, 0xC366, 0x80D2, 0xC367, 0x80D3, 0xC368, 0x80D4,
+ 0xC369, 0x80D5, 0xC36A, 0x80D8, 0xC36B, 0x80DF, 0xC36C, 0x80E0, 0xC36D, 0x80E2, 0xC36E, 0x80E3, 0xC36F, 0x80E6, 0xC370, 0x80EE,
+ 0xC371, 0x80F5, 0xC372, 0x80F7, 0xC373, 0x80F9, 0xC374, 0x80FB, 0xC375, 0x80FE, 0xC376, 0x80FF, 0xC377, 0x8100, 0xC378, 0x8101,
+ 0xC379, 0x8103, 0xC37A, 0x8104, 0xC37B, 0x8105, 0xC37C, 0x8107, 0xC37D, 0x8108, 0xC37E, 0x810B, 0xC380, 0x810C, 0xC381, 0x8115,
+ 0xC382, 0x8117, 0xC383, 0x8119, 0xC384, 0x811B, 0xC385, 0x811C, 0xC386, 0x811D, 0xC387, 0x811F, 0xC388, 0x8120, 0xC389, 0x8121,
+ 0xC38A, 0x8122, 0xC38B, 0x8123, 0xC38C, 0x8124, 0xC38D, 0x8125, 0xC38E, 0x8126, 0xC38F, 0x8127, 0xC390, 0x8128, 0xC391, 0x8129,
+ 0xC392, 0x812A, 0xC393, 0x812B, 0xC394, 0x812D, 0xC395, 0x812E, 0xC396, 0x8130, 0xC397, 0x8133, 0xC398, 0x8134, 0xC399, 0x8135,
+ 0xC39A, 0x8137, 0xC39B, 0x8139, 0xC39C, 0x813A, 0xC39D, 0x813B, 0xC39E, 0x813C, 0xC39F, 0x813D, 0xC3A0, 0x813F, 0xC3A1, 0x8C29,
+ 0xC3A2, 0x8292, 0xC3A3, 0x832B, 0xC3A4, 0x76F2, 0xC3A5, 0x6C13, 0xC3A6, 0x5FD9, 0xC3A7, 0x83BD, 0xC3A8, 0x732B, 0xC3A9, 0x8305,
+ 0xC3AA, 0x951A, 0xC3AB, 0x6BDB, 0xC3AC, 0x77DB, 0xC3AD, 0x94C6, 0xC3AE, 0x536F, 0xC3AF, 0x8302, 0xC3B0, 0x5192, 0xC3B1, 0x5E3D,
+ 0xC3B2, 0x8C8C, 0xC3B3, 0x8D38, 0xC3B4, 0x4E48, 0xC3B5, 0x73AB, 0xC3B6, 0x679A, 0xC3B7, 0x6885, 0xC3B8, 0x9176, 0xC3B9, 0x9709,
+ 0xC3BA, 0x7164, 0xC3BB, 0x6CA1, 0xC3BC, 0x7709, 0xC3BD, 0x5A92, 0xC3BE, 0x9541, 0xC3BF, 0x6BCF, 0xC3C0, 0x7F8E, 0xC3C1, 0x6627,
+ 0xC3C2, 0x5BD0, 0xC3C3, 0x59B9, 0xC3C4, 0x5A9A, 0xC3C5, 0x95E8, 0xC3C6, 0x95F7, 0xC3C7, 0x4EEC, 0xC3C8, 0x840C, 0xC3C9, 0x8499,
+ 0xC3CA, 0x6AAC, 0xC3CB, 0x76DF, 0xC3CC, 0x9530, 0xC3CD, 0x731B, 0xC3CE, 0x68A6, 0xC3CF, 0x5B5F, 0xC3D0, 0x772F, 0xC3D1, 0x919A,
+ 0xC3D2, 0x9761, 0xC3D3, 0x7CDC, 0xC3D4, 0x8FF7, 0xC3D5, 0x8C1C, 0xC3D6, 0x5F25, 0xC3D7, 0x7C73, 0xC3D8, 0x79D8, 0xC3D9, 0x89C5,
+ 0xC3DA, 0x6CCC, 0xC3DB, 0x871C, 0xC3DC, 0x5BC6, 0xC3DD, 0x5E42, 0xC3DE, 0x68C9, 0xC3DF, 0x7720, 0xC3E0, 0x7EF5, 0xC3E1, 0x5195,
+ 0xC3E2, 0x514D, 0xC3E3, 0x52C9, 0xC3E4, 0x5A29, 0xC3E5, 0x7F05, 0xC3E6, 0x9762, 0xC3E7, 0x82D7, 0xC3E8, 0x63CF, 0xC3E9, 0x7784,
+ 0xC3EA, 0x85D0, 0xC3EB, 0x79D2, 0xC3EC, 0x6E3A, 0xC3ED, 0x5E99, 0xC3EE, 0x5999, 0xC3EF, 0x8511, 0xC3F0, 0x706D, 0xC3F1, 0x6C11,
+ 0xC3F2, 0x62BF, 0xC3F3, 0x76BF, 0xC3F4, 0x654F, 0xC3F5, 0x60AF, 0xC3F6, 0x95FD, 0xC3F7, 0x660E, 0xC3F8, 0x879F, 0xC3F9, 0x9E23,
+ 0xC3FA, 0x94ED, 0xC3FB, 0x540D, 0xC3FC, 0x547D, 0xC3FD, 0x8C2C, 0xC3FE, 0x6478, 0xC440, 0x8140, 0xC441, 0x8141, 0xC442, 0x8142,
+ 0xC443, 0x8143, 0xC444, 0x8144, 0xC445, 0x8145, 0xC446, 0x8147, 0xC447, 0x8149, 0xC448, 0x814D, 0xC449, 0x814E, 0xC44A, 0x814F,
+ 0xC44B, 0x8152, 0xC44C, 0x8156, 0xC44D, 0x8157, 0xC44E, 0x8158, 0xC44F, 0x815B, 0xC450, 0x815C, 0xC451, 0x815D, 0xC452, 0x815E,
+ 0xC453, 0x815F, 0xC454, 0x8161, 0xC455, 0x8162, 0xC456, 0x8163, 0xC457, 0x8164, 0xC458, 0x8166, 0xC459, 0x8168, 0xC45A, 0x816A,
+ 0xC45B, 0x816B, 0xC45C, 0x816C, 0xC45D, 0x816F, 0xC45E, 0x8172, 0xC45F, 0x8173, 0xC460, 0x8175, 0xC461, 0x8176, 0xC462, 0x8177,
+ 0xC463, 0x8178, 0xC464, 0x8181, 0xC465, 0x8183, 0xC466, 0x8184, 0xC467, 0x8185, 0xC468, 0x8186, 0xC469, 0x8187, 0xC46A, 0x8189,
+ 0xC46B, 0x818B, 0xC46C, 0x818C, 0xC46D, 0x818D, 0xC46E, 0x818E, 0xC46F, 0x8190, 0xC470, 0x8192, 0xC471, 0x8193, 0xC472, 0x8194,
+ 0xC473, 0x8195, 0xC474, 0x8196, 0xC475, 0x8197, 0xC476, 0x8199, 0xC477, 0x819A, 0xC478, 0x819E, 0xC479, 0x819F, 0xC47A, 0x81A0,
+ 0xC47B, 0x81A1, 0xC47C, 0x81A2, 0xC47D, 0x81A4, 0xC47E, 0x81A5, 0xC480, 0x81A7, 0xC481, 0x81A9, 0xC482, 0x81AB, 0xC483, 0x81AC,
+ 0xC484, 0x81AD, 0xC485, 0x81AE, 0xC486, 0x81AF, 0xC487, 0x81B0, 0xC488, 0x81B1, 0xC489, 0x81B2, 0xC48A, 0x81B4, 0xC48B, 0x81B5,
+ 0xC48C, 0x81B6, 0xC48D, 0x81B7, 0xC48E, 0x81B8, 0xC48F, 0x81B9, 0xC490, 0x81BC, 0xC491, 0x81BD, 0xC492, 0x81BE, 0xC493, 0x81BF,
+ 0xC494, 0x81C4, 0xC495, 0x81C5, 0xC496, 0x81C7, 0xC497, 0x81C8, 0xC498, 0x81C9, 0xC499, 0x81CB, 0xC49A, 0x81CD, 0xC49B, 0x81CE,
+ 0xC49C, 0x81CF, 0xC49D, 0x81D0, 0xC49E, 0x81D1, 0xC49F, 0x81D2, 0xC4A0, 0x81D3, 0xC4A1, 0x6479, 0xC4A2, 0x8611, 0xC4A3, 0x6A21,
+ 0xC4A4, 0x819C, 0xC4A5, 0x78E8, 0xC4A6, 0x6469, 0xC4A7, 0x9B54, 0xC4A8, 0x62B9, 0xC4A9, 0x672B, 0xC4AA, 0x83AB, 0xC4AB, 0x58A8,
+ 0xC4AC, 0x9ED8, 0xC4AD, 0x6CAB, 0xC4AE, 0x6F20, 0xC4AF, 0x5BDE, 0xC4B0, 0x964C, 0xC4B1, 0x8C0B, 0xC4B2, 0x725F, 0xC4B3, 0x67D0,
+ 0xC4B4, 0x62C7, 0xC4B5, 0x7261, 0xC4B6, 0x4EA9, 0xC4B7, 0x59C6, 0xC4B8, 0x6BCD, 0xC4B9, 0x5893, 0xC4BA, 0x66AE, 0xC4BB, 0x5E55,
+ 0xC4BC, 0x52DF, 0xC4BD, 0x6155, 0xC4BE, 0x6728, 0xC4BF, 0x76EE, 0xC4C0, 0x7766, 0xC4C1, 0x7267, 0xC4C2, 0x7A46, 0xC4C3, 0x62FF,
+ 0xC4C4, 0x54EA, 0xC4C5, 0x5450, 0xC4C6, 0x94A0, 0xC4C7, 0x90A3, 0xC4C8, 0x5A1C, 0xC4C9, 0x7EB3, 0xC4CA, 0x6C16, 0xC4CB, 0x4E43,
+ 0xC4CC, 0x5976, 0xC4CD, 0x8010, 0xC4CE, 0x5948, 0xC4CF, 0x5357, 0xC4D0, 0x7537, 0xC4D1, 0x96BE, 0xC4D2, 0x56CA, 0xC4D3, 0x6320,
+ 0xC4D4, 0x8111, 0xC4D5, 0x607C, 0xC4D6, 0x95F9, 0xC4D7, 0x6DD6, 0xC4D8, 0x5462, 0xC4D9, 0x9981, 0xC4DA, 0x5185, 0xC4DB, 0x5AE9,
+ 0xC4DC, 0x80FD, 0xC4DD, 0x59AE, 0xC4DE, 0x9713, 0xC4DF, 0x502A, 0xC4E0, 0x6CE5, 0xC4E1, 0x5C3C, 0xC4E2, 0x62DF, 0xC4E3, 0x4F60,
+ 0xC4E4, 0x533F, 0xC4E5, 0x817B, 0xC4E6, 0x9006, 0xC4E7, 0x6EBA, 0xC4E8, 0x852B, 0xC4E9, 0x62C8, 0xC4EA, 0x5E74, 0xC4EB, 0x78BE,
+ 0xC4EC, 0x64B5, 0xC4ED, 0x637B, 0xC4EE, 0x5FF5, 0xC4EF, 0x5A18, 0xC4F0, 0x917F, 0xC4F1, 0x9E1F, 0xC4F2, 0x5C3F, 0xC4F3, 0x634F,
+ 0xC4F4, 0x8042, 0xC4F5, 0x5B7D, 0xC4F6, 0x556E, 0xC4F7, 0x954A, 0xC4F8, 0x954D, 0xC4F9, 0x6D85, 0xC4FA, 0x60A8, 0xC4FB, 0x67E0,
+ 0xC4FC, 0x72DE, 0xC4FD, 0x51DD, 0xC4FE, 0x5B81, 0xC540, 0x81D4, 0xC541, 0x81D5, 0xC542, 0x81D6, 0xC543, 0x81D7, 0xC544, 0x81D8,
+ 0xC545, 0x81D9, 0xC546, 0x81DA, 0xC547, 0x81DB, 0xC548, 0x81DC, 0xC549, 0x81DD, 0xC54A, 0x81DE, 0xC54B, 0x81DF, 0xC54C, 0x81E0,
+ 0xC54D, 0x81E1, 0xC54E, 0x81E2, 0xC54F, 0x81E4, 0xC550, 0x81E5, 0xC551, 0x81E6, 0xC552, 0x81E8, 0xC553, 0x81E9, 0xC554, 0x81EB,
+ 0xC555, 0x81EE, 0xC556, 0x81EF, 0xC557, 0x81F0, 0xC558, 0x81F1, 0xC559, 0x81F2, 0xC55A, 0x81F5, 0xC55B, 0x81F6, 0xC55C, 0x81F7,
+ 0xC55D, 0x81F8, 0xC55E, 0x81F9, 0xC55F, 0x81FA, 0xC560, 0x81FD, 0xC561, 0x81FF, 0xC562, 0x8203, 0xC563, 0x8207, 0xC564, 0x8208,
+ 0xC565, 0x8209, 0xC566, 0x820A, 0xC567, 0x820B, 0xC568, 0x820E, 0xC569, 0x820F, 0xC56A, 0x8211, 0xC56B, 0x8213, 0xC56C, 0x8215,
+ 0xC56D, 0x8216, 0xC56E, 0x8217, 0xC56F, 0x8218, 0xC570, 0x8219, 0xC571, 0x821A, 0xC572, 0x821D, 0xC573, 0x8220, 0xC574, 0x8224,
+ 0xC575, 0x8225, 0xC576, 0x8226, 0xC577, 0x8227, 0xC578, 0x8229, 0xC579, 0x822E, 0xC57A, 0x8232, 0xC57B, 0x823A, 0xC57C, 0x823C,
+ 0xC57D, 0x823D, 0xC57E, 0x823F, 0xC580, 0x8240, 0xC581, 0x8241, 0xC582, 0x8242, 0xC583, 0x8243, 0xC584, 0x8245, 0xC585, 0x8246,
+ 0xC586, 0x8248, 0xC587, 0x824A, 0xC588, 0x824C, 0xC589, 0x824D, 0xC58A, 0x824E, 0xC58B, 0x8250, 0xC58C, 0x8251, 0xC58D, 0x8252,
+ 0xC58E, 0x8253, 0xC58F, 0x8254, 0xC590, 0x8255, 0xC591, 0x8256, 0xC592, 0x8257, 0xC593, 0x8259, 0xC594, 0x825B, 0xC595, 0x825C,
+ 0xC596, 0x825D, 0xC597, 0x825E, 0xC598, 0x8260, 0xC599, 0x8261, 0xC59A, 0x8262, 0xC59B, 0x8263, 0xC59C, 0x8264, 0xC59D, 0x8265,
+ 0xC59E, 0x8266, 0xC59F, 0x8267, 0xC5A0, 0x8269, 0xC5A1, 0x62E7, 0xC5A2, 0x6CDE, 0xC5A3, 0x725B, 0xC5A4, 0x626D, 0xC5A5, 0x94AE,
+ 0xC5A6, 0x7EBD, 0xC5A7, 0x8113, 0xC5A8, 0x6D53, 0xC5A9, 0x519C, 0xC5AA, 0x5F04, 0xC5AB, 0x5974, 0xC5AC, 0x52AA, 0xC5AD, 0x6012,
+ 0xC5AE, 0x5973, 0xC5AF, 0x6696, 0xC5B0, 0x8650, 0xC5B1, 0x759F, 0xC5B2, 0x632A, 0xC5B3, 0x61E6, 0xC5B4, 0x7CEF, 0xC5B5, 0x8BFA,
+ 0xC5B6, 0x54E6, 0xC5B7, 0x6B27, 0xC5B8, 0x9E25, 0xC5B9, 0x6BB4, 0xC5BA, 0x85D5, 0xC5BB, 0x5455, 0xC5BC, 0x5076, 0xC5BD, 0x6CA4,
+ 0xC5BE, 0x556A, 0xC5BF, 0x8DB4, 0xC5C0, 0x722C, 0xC5C1, 0x5E15, 0xC5C2, 0x6015, 0xC5C3, 0x7436, 0xC5C4, 0x62CD, 0xC5C5, 0x6392,
+ 0xC5C6, 0x724C, 0xC5C7, 0x5F98, 0xC5C8, 0x6E43, 0xC5C9, 0x6D3E, 0xC5CA, 0x6500, 0xC5CB, 0x6F58, 0xC5CC, 0x76D8, 0xC5CD, 0x78D0,
+ 0xC5CE, 0x76FC, 0xC5CF, 0x7554, 0xC5D0, 0x5224, 0xC5D1, 0x53DB, 0xC5D2, 0x4E53, 0xC5D3, 0x5E9E, 0xC5D4, 0x65C1, 0xC5D5, 0x802A,
+ 0xC5D6, 0x80D6, 0xC5D7, 0x629B, 0xC5D8, 0x5486, 0xC5D9, 0x5228, 0xC5DA, 0x70AE, 0xC5DB, 0x888D, 0xC5DC, 0x8DD1, 0xC5DD, 0x6CE1,
+ 0xC5DE, 0x5478, 0xC5DF, 0x80DA, 0xC5E0, 0x57F9, 0xC5E1, 0x88F4, 0xC5E2, 0x8D54, 0xC5E3, 0x966A, 0xC5E4, 0x914D, 0xC5E5, 0x4F69,
+ 0xC5E6, 0x6C9B, 0xC5E7, 0x55B7, 0xC5E8, 0x76C6, 0xC5E9, 0x7830, 0xC5EA, 0x62A8, 0xC5EB, 0x70F9, 0xC5EC, 0x6F8E, 0xC5ED, 0x5F6D,
+ 0xC5EE, 0x84EC, 0xC5EF, 0x68DA, 0xC5F0, 0x787C, 0xC5F1, 0x7BF7, 0xC5F2, 0x81A8, 0xC5F3, 0x670B, 0xC5F4, 0x9E4F, 0xC5F5, 0x6367,
+ 0xC5F6, 0x78B0, 0xC5F7, 0x576F, 0xC5F8, 0x7812, 0xC5F9, 0x9739, 0xC5FA, 0x6279, 0xC5FB, 0x62AB, 0xC5FC, 0x5288, 0xC5FD, 0x7435,
+ 0xC5FE, 0x6BD7, 0xC640, 0x826A, 0xC641, 0x826B, 0xC642, 0x826C, 0xC643, 0x826D, 0xC644, 0x8271, 0xC645, 0x8275, 0xC646, 0x8276,
+ 0xC647, 0x8277, 0xC648, 0x8278, 0xC649, 0x827B, 0xC64A, 0x827C, 0xC64B, 0x8280, 0xC64C, 0x8281, 0xC64D, 0x8283, 0xC64E, 0x8285,
+ 0xC64F, 0x8286, 0xC650, 0x8287, 0xC651, 0x8289, 0xC652, 0x828C, 0xC653, 0x8290, 0xC654, 0x8293, 0xC655, 0x8294, 0xC656, 0x8295,
+ 0xC657, 0x8296, 0xC658, 0x829A, 0xC659, 0x829B, 0xC65A, 0x829E, 0xC65B, 0x82A0, 0xC65C, 0x82A2, 0xC65D, 0x82A3, 0xC65E, 0x82A7,
+ 0xC65F, 0x82B2, 0xC660, 0x82B5, 0xC661, 0x82B6, 0xC662, 0x82BA, 0xC663, 0x82BB, 0xC664, 0x82BC, 0xC665, 0x82BF, 0xC666, 0x82C0,
+ 0xC667, 0x82C2, 0xC668, 0x82C3, 0xC669, 0x82C5, 0xC66A, 0x82C6, 0xC66B, 0x82C9, 0xC66C, 0x82D0, 0xC66D, 0x82D6, 0xC66E, 0x82D9,
+ 0xC66F, 0x82DA, 0xC670, 0x82DD, 0xC671, 0x82E2, 0xC672, 0x82E7, 0xC673, 0x82E8, 0xC674, 0x82E9, 0xC675, 0x82EA, 0xC676, 0x82EC,
+ 0xC677, 0x82ED, 0xC678, 0x82EE, 0xC679, 0x82F0, 0xC67A, 0x82F2, 0xC67B, 0x82F3, 0xC67C, 0x82F5, 0xC67D, 0x82F6, 0xC67E, 0x82F8,
+ 0xC680, 0x82FA, 0xC681, 0x82FC, 0xC682, 0x82FD, 0xC683, 0x82FE, 0xC684, 0x82FF, 0xC685, 0x8300, 0xC686, 0x830A, 0xC687, 0x830B,
+ 0xC688, 0x830D, 0xC689, 0x8310, 0xC68A, 0x8312, 0xC68B, 0x8313, 0xC68C, 0x8316, 0xC68D, 0x8318, 0xC68E, 0x8319, 0xC68F, 0x831D,
+ 0xC690, 0x831E, 0xC691, 0x831F, 0xC692, 0x8320, 0xC693, 0x8321, 0xC694, 0x8322, 0xC695, 0x8323, 0xC696, 0x8324, 0xC697, 0x8325,
+ 0xC698, 0x8326, 0xC699, 0x8329, 0xC69A, 0x832A, 0xC69B, 0x832E, 0xC69C, 0x8330, 0xC69D, 0x8332, 0xC69E, 0x8337, 0xC69F, 0x833B,
+ 0xC6A0, 0x833D, 0xC6A1, 0x5564, 0xC6A2, 0x813E, 0xC6A3, 0x75B2, 0xC6A4, 0x76AE, 0xC6A5, 0x5339, 0xC6A6, 0x75DE, 0xC6A7, 0x50FB,
+ 0xC6A8, 0x5C41, 0xC6A9, 0x8B6C, 0xC6AA, 0x7BC7, 0xC6AB, 0x504F, 0xC6AC, 0x7247, 0xC6AD, 0x9A97, 0xC6AE, 0x98D8, 0xC6AF, 0x6F02,
+ 0xC6B0, 0x74E2, 0xC6B1, 0x7968, 0xC6B2, 0x6487, 0xC6B3, 0x77A5, 0xC6B4, 0x62FC, 0xC6B5, 0x9891, 0xC6B6, 0x8D2B, 0xC6B7, 0x54C1,
+ 0xC6B8, 0x8058, 0xC6B9, 0x4E52, 0xC6BA, 0x576A, 0xC6BB, 0x82F9, 0xC6BC, 0x840D, 0xC6BD, 0x5E73, 0xC6BE, 0x51ED, 0xC6BF, 0x74F6,
+ 0xC6C0, 0x8BC4, 0xC6C1, 0x5C4F, 0xC6C2, 0x5761, 0xC6C3, 0x6CFC, 0xC6C4, 0x9887, 0xC6C5, 0x5A46, 0xC6C6, 0x7834, 0xC6C7, 0x9B44,
+ 0xC6C8, 0x8FEB, 0xC6C9, 0x7C95, 0xC6CA, 0x5256, 0xC6CB, 0x6251, 0xC6CC, 0x94FA, 0xC6CD, 0x4EC6, 0xC6CE, 0x8386, 0xC6CF, 0x8461,
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+ 0xCE88, 0x8786, 0xCE89, 0x8787, 0xCE8A, 0x8789, 0xCE8B, 0x878A, 0xCE8C, 0x878C, 0xCE8D, 0x878E, 0xCE8E, 0x878F, 0xCE8F, 0x8790,
+ 0xCE90, 0x8791, 0xCE91, 0x8792, 0xCE92, 0x8794, 0xCE93, 0x8795, 0xCE94, 0x8796, 0xCE95, 0x8798, 0xCE96, 0x8799, 0xCE97, 0x879A,
+ 0xCE98, 0x879B, 0xCE99, 0x879C, 0xCE9A, 0x879D, 0xCE9B, 0x879E, 0xCE9C, 0x87A0, 0xCE9D, 0x87A1, 0xCE9E, 0x87A2, 0xCE9F, 0x87A3,
+ 0xCEA0, 0x87A4, 0xCEA1, 0x5DCD, 0xCEA2, 0x5FAE, 0xCEA3, 0x5371, 0xCEA4, 0x97E6, 0xCEA5, 0x8FDD, 0xCEA6, 0x6845, 0xCEA7, 0x56F4,
+ 0xCEA8, 0x552F, 0xCEA9, 0x60DF, 0xCEAA, 0x4E3A, 0xCEAB, 0x6F4D, 0xCEAC, 0x7EF4, 0xCEAD, 0x82C7, 0xCEAE, 0x840E, 0xCEAF, 0x59D4,
+ 0xCEB0, 0x4F1F, 0xCEB1, 0x4F2A, 0xCEB2, 0x5C3E, 0xCEB3, 0x7EAC, 0xCEB4, 0x672A, 0xCEB5, 0x851A, 0xCEB6, 0x5473, 0xCEB7, 0x754F,
+ 0xCEB8, 0x80C3, 0xCEB9, 0x5582, 0xCEBA, 0x9B4F, 0xCEBB, 0x4F4D, 0xCEBC, 0x6E2D, 0xCEBD, 0x8C13, 0xCEBE, 0x5C09, 0xCEBF, 0x6170,
+ 0xCEC0, 0x536B, 0xCEC1, 0x761F, 0xCEC2, 0x6E29, 0xCEC3, 0x868A, 0xCEC4, 0x6587, 0xCEC5, 0x95FB, 0xCEC6, 0x7EB9, 0xCEC7, 0x543B,
+ 0xCEC8, 0x7A33, 0xCEC9, 0x7D0A, 0xCECA, 0x95EE, 0xCECB, 0x55E1, 0xCECC, 0x7FC1, 0xCECD, 0x74EE, 0xCECE, 0x631D, 0xCECF, 0x8717,
+ 0xCED0, 0x6DA1, 0xCED1, 0x7A9D, 0xCED2, 0x6211, 0xCED3, 0x65A1, 0xCED4, 0x5367, 0xCED5, 0x63E1, 0xCED6, 0x6C83, 0xCED7, 0x5DEB,
+ 0xCED8, 0x545C, 0xCED9, 0x94A8, 0xCEDA, 0x4E4C, 0xCEDB, 0x6C61, 0xCEDC, 0x8BEC, 0xCEDD, 0x5C4B, 0xCEDE, 0x65E0, 0xCEDF, 0x829C,
+ 0xCEE0, 0x68A7, 0xCEE1, 0x543E, 0xCEE2, 0x5434, 0xCEE3, 0x6BCB, 0xCEE4, 0x6B66, 0xCEE5, 0x4E94, 0xCEE6, 0x6342, 0xCEE7, 0x5348,
+ 0xCEE8, 0x821E, 0xCEE9, 0x4F0D, 0xCEEA, 0x4FAE, 0xCEEB, 0x575E, 0xCEEC, 0x620A, 0xCEED, 0x96FE, 0xCEEE, 0x6664, 0xCEEF, 0x7269,
+ 0xCEF0, 0x52FF, 0xCEF1, 0x52A1, 0xCEF2, 0x609F, 0xCEF3, 0x8BEF, 0xCEF4, 0x6614, 0xCEF5, 0x7199, 0xCEF6, 0x6790, 0xCEF7, 0x897F,
+ 0xCEF8, 0x7852, 0xCEF9, 0x77FD, 0xCEFA, 0x6670, 0xCEFB, 0x563B, 0xCEFC, 0x5438, 0xCEFD, 0x9521, 0xCEFE, 0x727A, 0xCF40, 0x87A5,
+ 0xCF41, 0x87A6, 0xCF42, 0x87A7, 0xCF43, 0x87A9, 0xCF44, 0x87AA, 0xCF45, 0x87AE, 0xCF46, 0x87B0, 0xCF47, 0x87B1, 0xCF48, 0x87B2,
+ 0xCF49, 0x87B4, 0xCF4A, 0x87B6, 0xCF4B, 0x87B7, 0xCF4C, 0x87B8, 0xCF4D, 0x87B9, 0xCF4E, 0x87BB, 0xCF4F, 0x87BC, 0xCF50, 0x87BE,
+ 0xCF51, 0x87BF, 0xCF52, 0x87C1, 0xCF53, 0x87C2, 0xCF54, 0x87C3, 0xCF55, 0x87C4, 0xCF56, 0x87C5, 0xCF57, 0x87C7, 0xCF58, 0x87C8,
+ 0xCF59, 0x87C9, 0xCF5A, 0x87CC, 0xCF5B, 0x87CD, 0xCF5C, 0x87CE, 0xCF5D, 0x87CF, 0xCF5E, 0x87D0, 0xCF5F, 0x87D4, 0xCF60, 0x87D5,
+ 0xCF61, 0x87D6, 0xCF62, 0x87D7, 0xCF63, 0x87D8, 0xCF64, 0x87D9, 0xCF65, 0x87DA, 0xCF66, 0x87DC, 0xCF67, 0x87DD, 0xCF68, 0x87DE,
+ 0xCF69, 0x87DF, 0xCF6A, 0x87E1, 0xCF6B, 0x87E2, 0xCF6C, 0x87E3, 0xCF6D, 0x87E4, 0xCF6E, 0x87E6, 0xCF6F, 0x87E7, 0xCF70, 0x87E8,
+ 0xCF71, 0x87E9, 0xCF72, 0x87EB, 0xCF73, 0x87EC, 0xCF74, 0x87ED, 0xCF75, 0x87EF, 0xCF76, 0x87F0, 0xCF77, 0x87F1, 0xCF78, 0x87F2,
+ 0xCF79, 0x87F3, 0xCF7A, 0x87F4, 0xCF7B, 0x87F5, 0xCF7C, 0x87F6, 0xCF7D, 0x87F7, 0xCF7E, 0x87F8, 0xCF80, 0x87FA, 0xCF81, 0x87FB,
+ 0xCF82, 0x87FC, 0xCF83, 0x87FD, 0xCF84, 0x87FF, 0xCF85, 0x8800, 0xCF86, 0x8801, 0xCF87, 0x8802, 0xCF88, 0x8804, 0xCF89, 0x8805,
+ 0xCF8A, 0x8806, 0xCF8B, 0x8807, 0xCF8C, 0x8808, 0xCF8D, 0x8809, 0xCF8E, 0x880B, 0xCF8F, 0x880C, 0xCF90, 0x880D, 0xCF91, 0x880E,
+ 0xCF92, 0x880F, 0xCF93, 0x8810, 0xCF94, 0x8811, 0xCF95, 0x8812, 0xCF96, 0x8814, 0xCF97, 0x8817, 0xCF98, 0x8818, 0xCF99, 0x8819,
+ 0xCF9A, 0x881A, 0xCF9B, 0x881C, 0xCF9C, 0x881D, 0xCF9D, 0x881E, 0xCF9E, 0x881F, 0xCF9F, 0x8820, 0xCFA0, 0x8823, 0xCFA1, 0x7A00,
+ 0xCFA2, 0x606F, 0xCFA3, 0x5E0C, 0xCFA4, 0x6089, 0xCFA5, 0x819D, 0xCFA6, 0x5915, 0xCFA7, 0x60DC, 0xCFA8, 0x7184, 0xCFA9, 0x70EF,
+ 0xCFAA, 0x6EAA, 0xCFAB, 0x6C50, 0xCFAC, 0x7280, 0xCFAD, 0x6A84, 0xCFAE, 0x88AD, 0xCFAF, 0x5E2D, 0xCFB0, 0x4E60, 0xCFB1, 0x5AB3,
+ 0xCFB2, 0x559C, 0xCFB3, 0x94E3, 0xCFB4, 0x6D17, 0xCFB5, 0x7CFB, 0xCFB6, 0x9699, 0xCFB7, 0x620F, 0xCFB8, 0x7EC6, 0xCFB9, 0x778E,
+ 0xCFBA, 0x867E, 0xCFBB, 0x5323, 0xCFBC, 0x971E, 0xCFBD, 0x8F96, 0xCFBE, 0x6687, 0xCFBF, 0x5CE1, 0xCFC0, 0x4FA0, 0xCFC1, 0x72ED,
+ 0xCFC2, 0x4E0B, 0xCFC3, 0x53A6, 0xCFC4, 0x590F, 0xCFC5, 0x5413, 0xCFC6, 0x6380, 0xCFC7, 0x9528, 0xCFC8, 0x5148, 0xCFC9, 0x4ED9,
+ 0xCFCA, 0x9C9C, 0xCFCB, 0x7EA4, 0xCFCC, 0x54B8, 0xCFCD, 0x8D24, 0xCFCE, 0x8854, 0xCFCF, 0x8237, 0xCFD0, 0x95F2, 0xCFD1, 0x6D8E,
+ 0xCFD2, 0x5F26, 0xCFD3, 0x5ACC, 0xCFD4, 0x663E, 0xCFD5, 0x9669, 0xCFD6, 0x73B0, 0xCFD7, 0x732E, 0xCFD8, 0x53BF, 0xCFD9, 0x817A,
+ 0xCFDA, 0x9985, 0xCFDB, 0x7FA1, 0xCFDC, 0x5BAA, 0xCFDD, 0x9677, 0xCFDE, 0x9650, 0xCFDF, 0x7EBF, 0xCFE0, 0x76F8, 0xCFE1, 0x53A2,
+ 0xCFE2, 0x9576, 0xCFE3, 0x9999, 0xCFE4, 0x7BB1, 0xCFE5, 0x8944, 0xCFE6, 0x6E58, 0xCFE7, 0x4E61, 0xCFE8, 0x7FD4, 0xCFE9, 0x7965,
+ 0xCFEA, 0x8BE6, 0xCFEB, 0x60F3, 0xCFEC, 0x54CD, 0xCFED, 0x4EAB, 0xCFEE, 0x9879, 0xCFEF, 0x5DF7, 0xCFF0, 0x6A61, 0xCFF1, 0x50CF,
+ 0xCFF2, 0x5411, 0xCFF3, 0x8C61, 0xCFF4, 0x8427, 0xCFF5, 0x785D, 0xCFF6, 0x9704, 0xCFF7, 0x524A, 0xCFF8, 0x54EE, 0xCFF9, 0x56A3,
+ 0xCFFA, 0x9500, 0xCFFB, 0x6D88, 0xCFFC, 0x5BB5, 0xCFFD, 0x6DC6, 0xCFFE, 0x6653, 0xD040, 0x8824, 0xD041, 0x8825, 0xD042, 0x8826,
+ 0xD043, 0x8827, 0xD044, 0x8828, 0xD045, 0x8829, 0xD046, 0x882A, 0xD047, 0x882B, 0xD048, 0x882C, 0xD049, 0x882D, 0xD04A, 0x882E,
+ 0xD04B, 0x882F, 0xD04C, 0x8830, 0xD04D, 0x8831, 0xD04E, 0x8833, 0xD04F, 0x8834, 0xD050, 0x8835, 0xD051, 0x8836, 0xD052, 0x8837,
+ 0xD053, 0x8838, 0xD054, 0x883A, 0xD055, 0x883B, 0xD056, 0x883D, 0xD057, 0x883E, 0xD058, 0x883F, 0xD059, 0x8841, 0xD05A, 0x8842,
+ 0xD05B, 0x8843, 0xD05C, 0x8846, 0xD05D, 0x8847, 0xD05E, 0x8848, 0xD05F, 0x8849, 0xD060, 0x884A, 0xD061, 0x884B, 0xD062, 0x884E,
+ 0xD063, 0x884F, 0xD064, 0x8850, 0xD065, 0x8851, 0xD066, 0x8852, 0xD067, 0x8853, 0xD068, 0x8855, 0xD069, 0x8856, 0xD06A, 0x8858,
+ 0xD06B, 0x885A, 0xD06C, 0x885B, 0xD06D, 0x885C, 0xD06E, 0x885D, 0xD06F, 0x885E, 0xD070, 0x885F, 0xD071, 0x8860, 0xD072, 0x8866,
+ 0xD073, 0x8867, 0xD074, 0x886A, 0xD075, 0x886D, 0xD076, 0x886F, 0xD077, 0x8871, 0xD078, 0x8873, 0xD079, 0x8874, 0xD07A, 0x8875,
+ 0xD07B, 0x8876, 0xD07C, 0x8878, 0xD07D, 0x8879, 0xD07E, 0x887A, 0xD080, 0x887B, 0xD081, 0x887C, 0xD082, 0x8880, 0xD083, 0x8883,
+ 0xD084, 0x8886, 0xD085, 0x8887, 0xD086, 0x8889, 0xD087, 0x888A, 0xD088, 0x888C, 0xD089, 0x888E, 0xD08A, 0x888F, 0xD08B, 0x8890,
+ 0xD08C, 0x8891, 0xD08D, 0x8893, 0xD08E, 0x8894, 0xD08F, 0x8895, 0xD090, 0x8897, 0xD091, 0x8898, 0xD092, 0x8899, 0xD093, 0x889A,
+ 0xD094, 0x889B, 0xD095, 0x889D, 0xD096, 0x889E, 0xD097, 0x889F, 0xD098, 0x88A0, 0xD099, 0x88A1, 0xD09A, 0x88A3, 0xD09B, 0x88A5,
+ 0xD09C, 0x88A6, 0xD09D, 0x88A7, 0xD09E, 0x88A8, 0xD09F, 0x88A9, 0xD0A0, 0x88AA, 0xD0A1, 0x5C0F, 0xD0A2, 0x5B5D, 0xD0A3, 0x6821,
+ 0xD0A4, 0x8096, 0xD0A5, 0x5578, 0xD0A6, 0x7B11, 0xD0A7, 0x6548, 0xD0A8, 0x6954, 0xD0A9, 0x4E9B, 0xD0AA, 0x6B47, 0xD0AB, 0x874E,
+ 0xD0AC, 0x978B, 0xD0AD, 0x534F, 0xD0AE, 0x631F, 0xD0AF, 0x643A, 0xD0B0, 0x90AA, 0xD0B1, 0x659C, 0xD0B2, 0x80C1, 0xD0B3, 0x8C10,
+ 0xD0B4, 0x5199, 0xD0B5, 0x68B0, 0xD0B6, 0x5378, 0xD0B7, 0x87F9, 0xD0B8, 0x61C8, 0xD0B9, 0x6CC4, 0xD0BA, 0x6CFB, 0xD0BB, 0x8C22,
+ 0xD0BC, 0x5C51, 0xD0BD, 0x85AA, 0xD0BE, 0x82AF, 0xD0BF, 0x950C, 0xD0C0, 0x6B23, 0xD0C1, 0x8F9B, 0xD0C2, 0x65B0, 0xD0C3, 0x5FFB,
+ 0xD0C4, 0x5FC3, 0xD0C5, 0x4FE1, 0xD0C6, 0x8845, 0xD0C7, 0x661F, 0xD0C8, 0x8165, 0xD0C9, 0x7329, 0xD0CA, 0x60FA, 0xD0CB, 0x5174,
+ 0xD0CC, 0x5211, 0xD0CD, 0x578B, 0xD0CE, 0x5F62, 0xD0CF, 0x90A2, 0xD0D0, 0x884C, 0xD0D1, 0x9192, 0xD0D2, 0x5E78, 0xD0D3, 0x674F,
+ 0xD0D4, 0x6027, 0xD0D5, 0x59D3, 0xD0D6, 0x5144, 0xD0D7, 0x51F6, 0xD0D8, 0x80F8, 0xD0D9, 0x5308, 0xD0DA, 0x6C79, 0xD0DB, 0x96C4,
+ 0xD0DC, 0x718A, 0xD0DD, 0x4F11, 0xD0DE, 0x4FEE, 0xD0DF, 0x7F9E, 0xD0E0, 0x673D, 0xD0E1, 0x55C5, 0xD0E2, 0x9508, 0xD0E3, 0x79C0,
+ 0xD0E4, 0x8896, 0xD0E5, 0x7EE3, 0xD0E6, 0x589F, 0xD0E7, 0x620C, 0xD0E8, 0x9700, 0xD0E9, 0x865A, 0xD0EA, 0x5618, 0xD0EB, 0x987B,
+ 0xD0EC, 0x5F90, 0xD0ED, 0x8BB8, 0xD0EE, 0x84C4, 0xD0EF, 0x9157, 0xD0F0, 0x53D9, 0xD0F1, 0x65ED, 0xD0F2, 0x5E8F, 0xD0F3, 0x755C,
+ 0xD0F4, 0x6064, 0xD0F5, 0x7D6E, 0xD0F6, 0x5A7F, 0xD0F7, 0x7EEA, 0xD0F8, 0x7EED, 0xD0F9, 0x8F69, 0xD0FA, 0x55A7, 0xD0FB, 0x5BA3,
+ 0xD0FC, 0x60AC, 0xD0FD, 0x65CB, 0xD0FE, 0x7384, 0xD140, 0x88AC, 0xD141, 0x88AE, 0xD142, 0x88AF, 0xD143, 0x88B0, 0xD144, 0x88B2,
+ 0xD145, 0x88B3, 0xD146, 0x88B4, 0xD147, 0x88B5, 0xD148, 0x88B6, 0xD149, 0x88B8, 0xD14A, 0x88B9, 0xD14B, 0x88BA, 0xD14C, 0x88BB,
+ 0xD14D, 0x88BD, 0xD14E, 0x88BE, 0xD14F, 0x88BF, 0xD150, 0x88C0, 0xD151, 0x88C3, 0xD152, 0x88C4, 0xD153, 0x88C7, 0xD154, 0x88C8,
+ 0xD155, 0x88CA, 0xD156, 0x88CB, 0xD157, 0x88CC, 0xD158, 0x88CD, 0xD159, 0x88CF, 0xD15A, 0x88D0, 0xD15B, 0x88D1, 0xD15C, 0x88D3,
+ 0xD15D, 0x88D6, 0xD15E, 0x88D7, 0xD15F, 0x88DA, 0xD160, 0x88DB, 0xD161, 0x88DC, 0xD162, 0x88DD, 0xD163, 0x88DE, 0xD164, 0x88E0,
+ 0xD165, 0x88E1, 0xD166, 0x88E6, 0xD167, 0x88E7, 0xD168, 0x88E9, 0xD169, 0x88EA, 0xD16A, 0x88EB, 0xD16B, 0x88EC, 0xD16C, 0x88ED,
+ 0xD16D, 0x88EE, 0xD16E, 0x88EF, 0xD16F, 0x88F2, 0xD170, 0x88F5, 0xD171, 0x88F6, 0xD172, 0x88F7, 0xD173, 0x88FA, 0xD174, 0x88FB,
+ 0xD175, 0x88FD, 0xD176, 0x88FF, 0xD177, 0x8900, 0xD178, 0x8901, 0xD179, 0x8903, 0xD17A, 0x8904, 0xD17B, 0x8905, 0xD17C, 0x8906,
+ 0xD17D, 0x8907, 0xD17E, 0x8908, 0xD180, 0x8909, 0xD181, 0x890B, 0xD182, 0x890C, 0xD183, 0x890D, 0xD184, 0x890E, 0xD185, 0x890F,
+ 0xD186, 0x8911, 0xD187, 0x8914, 0xD188, 0x8915, 0xD189, 0x8916, 0xD18A, 0x8917, 0xD18B, 0x8918, 0xD18C, 0x891C, 0xD18D, 0x891D,
+ 0xD18E, 0x891E, 0xD18F, 0x891F, 0xD190, 0x8920, 0xD191, 0x8922, 0xD192, 0x8923, 0xD193, 0x8924, 0xD194, 0x8926, 0xD195, 0x8927,
+ 0xD196, 0x8928, 0xD197, 0x8929, 0xD198, 0x892C, 0xD199, 0x892D, 0xD19A, 0x892E, 0xD19B, 0x892F, 0xD19C, 0x8931, 0xD19D, 0x8932,
+ 0xD19E, 0x8933, 0xD19F, 0x8935, 0xD1A0, 0x8937, 0xD1A1, 0x9009, 0xD1A2, 0x7663, 0xD1A3, 0x7729, 0xD1A4, 0x7EDA, 0xD1A5, 0x9774,
+ 0xD1A6, 0x859B, 0xD1A7, 0x5B66, 0xD1A8, 0x7A74, 0xD1A9, 0x96EA, 0xD1AA, 0x8840, 0xD1AB, 0x52CB, 0xD1AC, 0x718F, 0xD1AD, 0x5FAA,
+ 0xD1AE, 0x65EC, 0xD1AF, 0x8BE2, 0xD1B0, 0x5BFB, 0xD1B1, 0x9A6F, 0xD1B2, 0x5DE1, 0xD1B3, 0x6B89, 0xD1B4, 0x6C5B, 0xD1B5, 0x8BAD,
+ 0xD1B6, 0x8BAF, 0xD1B7, 0x900A, 0xD1B8, 0x8FC5, 0xD1B9, 0x538B, 0xD1BA, 0x62BC, 0xD1BB, 0x9E26, 0xD1BC, 0x9E2D, 0xD1BD, 0x5440,
+ 0xD1BE, 0x4E2B, 0xD1BF, 0x82BD, 0xD1C0, 0x7259, 0xD1C1, 0x869C, 0xD1C2, 0x5D16, 0xD1C3, 0x8859, 0xD1C4, 0x6DAF, 0xD1C5, 0x96C5,
+ 0xD1C6, 0x54D1, 0xD1C7, 0x4E9A, 0xD1C8, 0x8BB6, 0xD1C9, 0x7109, 0xD1CA, 0x54BD, 0xD1CB, 0x9609, 0xD1CC, 0x70DF, 0xD1CD, 0x6DF9,
+ 0xD1CE, 0x76D0, 0xD1CF, 0x4E25, 0xD1D0, 0x7814, 0xD1D1, 0x8712, 0xD1D2, 0x5CA9, 0xD1D3, 0x5EF6, 0xD1D4, 0x8A00, 0xD1D5, 0x989C,
+ 0xD1D6, 0x960E, 0xD1D7, 0x708E, 0xD1D8, 0x6CBF, 0xD1D9, 0x5944, 0xD1DA, 0x63A9, 0xD1DB, 0x773C, 0xD1DC, 0x884D, 0xD1DD, 0x6F14,
+ 0xD1DE, 0x8273, 0xD1DF, 0x5830, 0xD1E0, 0x71D5, 0xD1E1, 0x538C, 0xD1E2, 0x781A, 0xD1E3, 0x96C1, 0xD1E4, 0x5501, 0xD1E5, 0x5F66,
+ 0xD1E6, 0x7130, 0xD1E7, 0x5BB4, 0xD1E8, 0x8C1A, 0xD1E9, 0x9A8C, 0xD1EA, 0x6B83, 0xD1EB, 0x592E, 0xD1EC, 0x9E2F, 0xD1ED, 0x79E7,
+ 0xD1EE, 0x6768, 0xD1EF, 0x626C, 0xD1F0, 0x4F6F, 0xD1F1, 0x75A1, 0xD1F2, 0x7F8A, 0xD1F3, 0x6D0B, 0xD1F4, 0x9633, 0xD1F5, 0x6C27,
+ 0xD1F6, 0x4EF0, 0xD1F7, 0x75D2, 0xD1F8, 0x517B, 0xD1F9, 0x6837, 0xD1FA, 0x6F3E, 0xD1FB, 0x9080, 0xD1FC, 0x8170, 0xD1FD, 0x5996,
+ 0xD1FE, 0x7476, 0xD240, 0x8938, 0xD241, 0x8939, 0xD242, 0x893A, 0xD243, 0x893B, 0xD244, 0x893C, 0xD245, 0x893D, 0xD246, 0x893E,
+ 0xD247, 0x893F, 0xD248, 0x8940, 0xD249, 0x8942, 0xD24A, 0x8943, 0xD24B, 0x8945, 0xD24C, 0x8946, 0xD24D, 0x8947, 0xD24E, 0x8948,
+ 0xD24F, 0x8949, 0xD250, 0x894A, 0xD251, 0x894B, 0xD252, 0x894C, 0xD253, 0x894D, 0xD254, 0x894E, 0xD255, 0x894F, 0xD256, 0x8950,
+ 0xD257, 0x8951, 0xD258, 0x8952, 0xD259, 0x8953, 0xD25A, 0x8954, 0xD25B, 0x8955, 0xD25C, 0x8956, 0xD25D, 0x8957, 0xD25E, 0x8958,
+ 0xD25F, 0x8959, 0xD260, 0x895A, 0xD261, 0x895B, 0xD262, 0x895C, 0xD263, 0x895D, 0xD264, 0x8960, 0xD265, 0x8961, 0xD266, 0x8962,
+ 0xD267, 0x8963, 0xD268, 0x8964, 0xD269, 0x8965, 0xD26A, 0x8967, 0xD26B, 0x8968, 0xD26C, 0x8969, 0xD26D, 0x896A, 0xD26E, 0x896B,
+ 0xD26F, 0x896C, 0xD270, 0x896D, 0xD271, 0x896E, 0xD272, 0x896F, 0xD273, 0x8970, 0xD274, 0x8971, 0xD275, 0x8972, 0xD276, 0x8973,
+ 0xD277, 0x8974, 0xD278, 0x8975, 0xD279, 0x8976, 0xD27A, 0x8977, 0xD27B, 0x8978, 0xD27C, 0x8979, 0xD27D, 0x897A, 0xD27E, 0x897C,
+ 0xD280, 0x897D, 0xD281, 0x897E, 0xD282, 0x8980, 0xD283, 0x8982, 0xD284, 0x8984, 0xD285, 0x8985, 0xD286, 0x8987, 0xD287, 0x8988,
+ 0xD288, 0x8989, 0xD289, 0x898A, 0xD28A, 0x898B, 0xD28B, 0x898C, 0xD28C, 0x898D, 0xD28D, 0x898E, 0xD28E, 0x898F, 0xD28F, 0x8990,
+ 0xD290, 0x8991, 0xD291, 0x8992, 0xD292, 0x8993, 0xD293, 0x8994, 0xD294, 0x8995, 0xD295, 0x8996, 0xD296, 0x8997, 0xD297, 0x8998,
+ 0xD298, 0x8999, 0xD299, 0x899A, 0xD29A, 0x899B, 0xD29B, 0x899C, 0xD29C, 0x899D, 0xD29D, 0x899E, 0xD29E, 0x899F, 0xD29F, 0x89A0,
+ 0xD2A0, 0x89A1, 0xD2A1, 0x6447, 0xD2A2, 0x5C27, 0xD2A3, 0x9065, 0xD2A4, 0x7A91, 0xD2A5, 0x8C23, 0xD2A6, 0x59DA, 0xD2A7, 0x54AC,
+ 0xD2A8, 0x8200, 0xD2A9, 0x836F, 0xD2AA, 0x8981, 0xD2AB, 0x8000, 0xD2AC, 0x6930, 0xD2AD, 0x564E, 0xD2AE, 0x8036, 0xD2AF, 0x7237,
+ 0xD2B0, 0x91CE, 0xD2B1, 0x51B6, 0xD2B2, 0x4E5F, 0xD2B3, 0x9875, 0xD2B4, 0x6396, 0xD2B5, 0x4E1A, 0xD2B6, 0x53F6, 0xD2B7, 0x66F3,
+ 0xD2B8, 0x814B, 0xD2B9, 0x591C, 0xD2BA, 0x6DB2, 0xD2BB, 0x4E00, 0xD2BC, 0x58F9, 0xD2BD, 0x533B, 0xD2BE, 0x63D6, 0xD2BF, 0x94F1,
+ 0xD2C0, 0x4F9D, 0xD2C1, 0x4F0A, 0xD2C2, 0x8863, 0xD2C3, 0x9890, 0xD2C4, 0x5937, 0xD2C5, 0x9057, 0xD2C6, 0x79FB, 0xD2C7, 0x4EEA,
+ 0xD2C8, 0x80F0, 0xD2C9, 0x7591, 0xD2CA, 0x6C82, 0xD2CB, 0x5B9C, 0xD2CC, 0x59E8, 0xD2CD, 0x5F5D, 0xD2CE, 0x6905, 0xD2CF, 0x8681,
+ 0xD2D0, 0x501A, 0xD2D1, 0x5DF2, 0xD2D2, 0x4E59, 0xD2D3, 0x77E3, 0xD2D4, 0x4EE5, 0xD2D5, 0x827A, 0xD2D6, 0x6291, 0xD2D7, 0x6613,
+ 0xD2D8, 0x9091, 0xD2D9, 0x5C79, 0xD2DA, 0x4EBF, 0xD2DB, 0x5F79, 0xD2DC, 0x81C6, 0xD2DD, 0x9038, 0xD2DE, 0x8084, 0xD2DF, 0x75AB,
+ 0xD2E0, 0x4EA6, 0xD2E1, 0x88D4, 0xD2E2, 0x610F, 0xD2E3, 0x6BC5, 0xD2E4, 0x5FC6, 0xD2E5, 0x4E49, 0xD2E6, 0x76CA, 0xD2E7, 0x6EA2,
+ 0xD2E8, 0x8BE3, 0xD2E9, 0x8BAE, 0xD2EA, 0x8C0A, 0xD2EB, 0x8BD1, 0xD2EC, 0x5F02, 0xD2ED, 0x7FFC, 0xD2EE, 0x7FCC, 0xD2EF, 0x7ECE,
+ 0xD2F0, 0x8335, 0xD2F1, 0x836B, 0xD2F2, 0x56E0, 0xD2F3, 0x6BB7, 0xD2F4, 0x97F3, 0xD2F5, 0x9634, 0xD2F6, 0x59FB, 0xD2F7, 0x541F,
+ 0xD2F8, 0x94F6, 0xD2F9, 0x6DEB, 0xD2FA, 0x5BC5, 0xD2FB, 0x996E, 0xD2FC, 0x5C39, 0xD2FD, 0x5F15, 0xD2FE, 0x9690, 0xD340, 0x89A2,
+ 0xD341, 0x89A3, 0xD342, 0x89A4, 0xD343, 0x89A5, 0xD344, 0x89A6, 0xD345, 0x89A7, 0xD346, 0x89A8, 0xD347, 0x89A9, 0xD348, 0x89AA,
+ 0xD349, 0x89AB, 0xD34A, 0x89AC, 0xD34B, 0x89AD, 0xD34C, 0x89AE, 0xD34D, 0x89AF, 0xD34E, 0x89B0, 0xD34F, 0x89B1, 0xD350, 0x89B2,
+ 0xD351, 0x89B3, 0xD352, 0x89B4, 0xD353, 0x89B5, 0xD354, 0x89B6, 0xD355, 0x89B7, 0xD356, 0x89B8, 0xD357, 0x89B9, 0xD358, 0x89BA,
+ 0xD359, 0x89BB, 0xD35A, 0x89BC, 0xD35B, 0x89BD, 0xD35C, 0x89BE, 0xD35D, 0x89BF, 0xD35E, 0x89C0, 0xD35F, 0x89C3, 0xD360, 0x89CD,
+ 0xD361, 0x89D3, 0xD362, 0x89D4, 0xD363, 0x89D5, 0xD364, 0x89D7, 0xD365, 0x89D8, 0xD366, 0x89D9, 0xD367, 0x89DB, 0xD368, 0x89DD,
+ 0xD369, 0x89DF, 0xD36A, 0x89E0, 0xD36B, 0x89E1, 0xD36C, 0x89E2, 0xD36D, 0x89E4, 0xD36E, 0x89E7, 0xD36F, 0x89E8, 0xD370, 0x89E9,
+ 0xD371, 0x89EA, 0xD372, 0x89EC, 0xD373, 0x89ED, 0xD374, 0x89EE, 0xD375, 0x89F0, 0xD376, 0x89F1, 0xD377, 0x89F2, 0xD378, 0x89F4,
+ 0xD379, 0x89F5, 0xD37A, 0x89F6, 0xD37B, 0x89F7, 0xD37C, 0x89F8, 0xD37D, 0x89F9, 0xD37E, 0x89FA, 0xD380, 0x89FB, 0xD381, 0x89FC,
+ 0xD382, 0x89FD, 0xD383, 0x89FE, 0xD384, 0x89FF, 0xD385, 0x8A01, 0xD386, 0x8A02, 0xD387, 0x8A03, 0xD388, 0x8A04, 0xD389, 0x8A05,
+ 0xD38A, 0x8A06, 0xD38B, 0x8A08, 0xD38C, 0x8A09, 0xD38D, 0x8A0A, 0xD38E, 0x8A0B, 0xD38F, 0x8A0C, 0xD390, 0x8A0D, 0xD391, 0x8A0E,
+ 0xD392, 0x8A0F, 0xD393, 0x8A10, 0xD394, 0x8A11, 0xD395, 0x8A12, 0xD396, 0x8A13, 0xD397, 0x8A14, 0xD398, 0x8A15, 0xD399, 0x8A16,
+ 0xD39A, 0x8A17, 0xD39B, 0x8A18, 0xD39C, 0x8A19, 0xD39D, 0x8A1A, 0xD39E, 0x8A1B, 0xD39F, 0x8A1C, 0xD3A0, 0x8A1D, 0xD3A1, 0x5370,
+ 0xD3A2, 0x82F1, 0xD3A3, 0x6A31, 0xD3A4, 0x5A74, 0xD3A5, 0x9E70, 0xD3A6, 0x5E94, 0xD3A7, 0x7F28, 0xD3A8, 0x83B9, 0xD3A9, 0x8424,
+ 0xD3AA, 0x8425, 0xD3AB, 0x8367, 0xD3AC, 0x8747, 0xD3AD, 0x8FCE, 0xD3AE, 0x8D62, 0xD3AF, 0x76C8, 0xD3B0, 0x5F71, 0xD3B1, 0x9896,
+ 0xD3B2, 0x786C, 0xD3B3, 0x6620, 0xD3B4, 0x54DF, 0xD3B5, 0x62E5, 0xD3B6, 0x4F63, 0xD3B7, 0x81C3, 0xD3B8, 0x75C8, 0xD3B9, 0x5EB8,
+ 0xD3BA, 0x96CD, 0xD3BB, 0x8E0A, 0xD3BC, 0x86F9, 0xD3BD, 0x548F, 0xD3BE, 0x6CF3, 0xD3BF, 0x6D8C, 0xD3C0, 0x6C38, 0xD3C1, 0x607F,
+ 0xD3C2, 0x52C7, 0xD3C3, 0x7528, 0xD3C4, 0x5E7D, 0xD3C5, 0x4F18, 0xD3C6, 0x60A0, 0xD3C7, 0x5FE7, 0xD3C8, 0x5C24, 0xD3C9, 0x7531,
+ 0xD3CA, 0x90AE, 0xD3CB, 0x94C0, 0xD3CC, 0x72B9, 0xD3CD, 0x6CB9, 0xD3CE, 0x6E38, 0xD3CF, 0x9149, 0xD3D0, 0x6709, 0xD3D1, 0x53CB,
+ 0xD3D2, 0x53F3, 0xD3D3, 0x4F51, 0xD3D4, 0x91C9, 0xD3D5, 0x8BF1, 0xD3D6, 0x53C8, 0xD3D7, 0x5E7C, 0xD3D8, 0x8FC2, 0xD3D9, 0x6DE4,
+ 0xD3DA, 0x4E8E, 0xD3DB, 0x76C2, 0xD3DC, 0x6986, 0xD3DD, 0x865E, 0xD3DE, 0x611A, 0xD3DF, 0x8206, 0xD3E0, 0x4F59, 0xD3E1, 0x4FDE,
+ 0xD3E2, 0x903E, 0xD3E3, 0x9C7C, 0xD3E4, 0x6109, 0xD3E5, 0x6E1D, 0xD3E6, 0x6E14, 0xD3E7, 0x9685, 0xD3E8, 0x4E88, 0xD3E9, 0x5A31,
+ 0xD3EA, 0x96E8, 0xD3EB, 0x4E0E, 0xD3EC, 0x5C7F, 0xD3ED, 0x79B9, 0xD3EE, 0x5B87, 0xD3EF, 0x8BED, 0xD3F0, 0x7FBD, 0xD3F1, 0x7389,
+ 0xD3F2, 0x57DF, 0xD3F3, 0x828B, 0xD3F4, 0x90C1, 0xD3F5, 0x5401, 0xD3F6, 0x9047, 0xD3F7, 0x55BB, 0xD3F8, 0x5CEA, 0xD3F9, 0x5FA1,
+ 0xD3FA, 0x6108, 0xD3FB, 0x6B32, 0xD3FC, 0x72F1, 0xD3FD, 0x80B2, 0xD3FE, 0x8A89, 0xD440, 0x8A1E, 0xD441, 0x8A1F, 0xD442, 0x8A20,
+ 0xD443, 0x8A21, 0xD444, 0x8A22, 0xD445, 0x8A23, 0xD446, 0x8A24, 0xD447, 0x8A25, 0xD448, 0x8A26, 0xD449, 0x8A27, 0xD44A, 0x8A28,
+ 0xD44B, 0x8A29, 0xD44C, 0x8A2A, 0xD44D, 0x8A2B, 0xD44E, 0x8A2C, 0xD44F, 0x8A2D, 0xD450, 0x8A2E, 0xD451, 0x8A2F, 0xD452, 0x8A30,
+ 0xD453, 0x8A31, 0xD454, 0x8A32, 0xD455, 0x8A33, 0xD456, 0x8A34, 0xD457, 0x8A35, 0xD458, 0x8A36, 0xD459, 0x8A37, 0xD45A, 0x8A38,
+ 0xD45B, 0x8A39, 0xD45C, 0x8A3A, 0xD45D, 0x8A3B, 0xD45E, 0x8A3C, 0xD45F, 0x8A3D, 0xD460, 0x8A3F, 0xD461, 0x8A40, 0xD462, 0x8A41,
+ 0xD463, 0x8A42, 0xD464, 0x8A43, 0xD465, 0x8A44, 0xD466, 0x8A45, 0xD467, 0x8A46, 0xD468, 0x8A47, 0xD469, 0x8A49, 0xD46A, 0x8A4A,
+ 0xD46B, 0x8A4B, 0xD46C, 0x8A4C, 0xD46D, 0x8A4D, 0xD46E, 0x8A4E, 0xD46F, 0x8A4F, 0xD470, 0x8A50, 0xD471, 0x8A51, 0xD472, 0x8A52,
+ 0xD473, 0x8A53, 0xD474, 0x8A54, 0xD475, 0x8A55, 0xD476, 0x8A56, 0xD477, 0x8A57, 0xD478, 0x8A58, 0xD479, 0x8A59, 0xD47A, 0x8A5A,
+ 0xD47B, 0x8A5B, 0xD47C, 0x8A5C, 0xD47D, 0x8A5D, 0xD47E, 0x8A5E, 0xD480, 0x8A5F, 0xD481, 0x8A60, 0xD482, 0x8A61, 0xD483, 0x8A62,
+ 0xD484, 0x8A63, 0xD485, 0x8A64, 0xD486, 0x8A65, 0xD487, 0x8A66, 0xD488, 0x8A67, 0xD489, 0x8A68, 0xD48A, 0x8A69, 0xD48B, 0x8A6A,
+ 0xD48C, 0x8A6B, 0xD48D, 0x8A6C, 0xD48E, 0x8A6D, 0xD48F, 0x8A6E, 0xD490, 0x8A6F, 0xD491, 0x8A70, 0xD492, 0x8A71, 0xD493, 0x8A72,
+ 0xD494, 0x8A73, 0xD495, 0x8A74, 0xD496, 0x8A75, 0xD497, 0x8A76, 0xD498, 0x8A77, 0xD499, 0x8A78, 0xD49A, 0x8A7A, 0xD49B, 0x8A7B,
+ 0xD49C, 0x8A7C, 0xD49D, 0x8A7D, 0xD49E, 0x8A7E, 0xD49F, 0x8A7F, 0xD4A0, 0x8A80, 0xD4A1, 0x6D74, 0xD4A2, 0x5BD3, 0xD4A3, 0x88D5,
+ 0xD4A4, 0x9884, 0xD4A5, 0x8C6B, 0xD4A6, 0x9A6D, 0xD4A7, 0x9E33, 0xD4A8, 0x6E0A, 0xD4A9, 0x51A4, 0xD4AA, 0x5143, 0xD4AB, 0x57A3,
+ 0xD4AC, 0x8881, 0xD4AD, 0x539F, 0xD4AE, 0x63F4, 0xD4AF, 0x8F95, 0xD4B0, 0x56ED, 0xD4B1, 0x5458, 0xD4B2, 0x5706, 0xD4B3, 0x733F,
+ 0xD4B4, 0x6E90, 0xD4B5, 0x7F18, 0xD4B6, 0x8FDC, 0xD4B7, 0x82D1, 0xD4B8, 0x613F, 0xD4B9, 0x6028, 0xD4BA, 0x9662, 0xD4BB, 0x66F0,
+ 0xD4BC, 0x7EA6, 0xD4BD, 0x8D8A, 0xD4BE, 0x8DC3, 0xD4BF, 0x94A5, 0xD4C0, 0x5CB3, 0xD4C1, 0x7CA4, 0xD4C2, 0x6708, 0xD4C3, 0x60A6,
+ 0xD4C4, 0x9605, 0xD4C5, 0x8018, 0xD4C6, 0x4E91, 0xD4C7, 0x90E7, 0xD4C8, 0x5300, 0xD4C9, 0x9668, 0xD4CA, 0x5141, 0xD4CB, 0x8FD0,
+ 0xD4CC, 0x8574, 0xD4CD, 0x915D, 0xD4CE, 0x6655, 0xD4CF, 0x97F5, 0xD4D0, 0x5B55, 0xD4D1, 0x531D, 0xD4D2, 0x7838, 0xD4D3, 0x6742,
+ 0xD4D4, 0x683D, 0xD4D5, 0x54C9, 0xD4D6, 0x707E, 0xD4D7, 0x5BB0, 0xD4D8, 0x8F7D, 0xD4D9, 0x518D, 0xD4DA, 0x5728, 0xD4DB, 0x54B1,
+ 0xD4DC, 0x6512, 0xD4DD, 0x6682, 0xD4DE, 0x8D5E, 0xD4DF, 0x8D43, 0xD4E0, 0x810F, 0xD4E1, 0x846C, 0xD4E2, 0x906D, 0xD4E3, 0x7CDF,
+ 0xD4E4, 0x51FF, 0xD4E5, 0x85FB, 0xD4E6, 0x67A3, 0xD4E7, 0x65E9, 0xD4E8, 0x6FA1, 0xD4E9, 0x86A4, 0xD4EA, 0x8E81, 0xD4EB, 0x566A,
+ 0xD4EC, 0x9020, 0xD4ED, 0x7682, 0xD4EE, 0x7076, 0xD4EF, 0x71E5, 0xD4F0, 0x8D23, 0xD4F1, 0x62E9, 0xD4F2, 0x5219, 0xD4F3, 0x6CFD,
+ 0xD4F4, 0x8D3C, 0xD4F5, 0x600E, 0xD4F6, 0x589E, 0xD4F7, 0x618E, 0xD4F8, 0x66FE, 0xD4F9, 0x8D60, 0xD4FA, 0x624E, 0xD4FB, 0x55B3,
+ 0xD4FC, 0x6E23, 0xD4FD, 0x672D, 0xD4FE, 0x8F67, 0xD540, 0x8A81, 0xD541, 0x8A82, 0xD542, 0x8A83, 0xD543, 0x8A84, 0xD544, 0x8A85,
+ 0xD545, 0x8A86, 0xD546, 0x8A87, 0xD547, 0x8A88, 0xD548, 0x8A8B, 0xD549, 0x8A8C, 0xD54A, 0x8A8D, 0xD54B, 0x8A8E, 0xD54C, 0x8A8F,
+ 0xD54D, 0x8A90, 0xD54E, 0x8A91, 0xD54F, 0x8A92, 0xD550, 0x8A94, 0xD551, 0x8A95, 0xD552, 0x8A96, 0xD553, 0x8A97, 0xD554, 0x8A98,
+ 0xD555, 0x8A99, 0xD556, 0x8A9A, 0xD557, 0x8A9B, 0xD558, 0x8A9C, 0xD559, 0x8A9D, 0xD55A, 0x8A9E, 0xD55B, 0x8A9F, 0xD55C, 0x8AA0,
+ 0xD55D, 0x8AA1, 0xD55E, 0x8AA2, 0xD55F, 0x8AA3, 0xD560, 0x8AA4, 0xD561, 0x8AA5, 0xD562, 0x8AA6, 0xD563, 0x8AA7, 0xD564, 0x8AA8,
+ 0xD565, 0x8AA9, 0xD566, 0x8AAA, 0xD567, 0x8AAB, 0xD568, 0x8AAC, 0xD569, 0x8AAD, 0xD56A, 0x8AAE, 0xD56B, 0x8AAF, 0xD56C, 0x8AB0,
+ 0xD56D, 0x8AB1, 0xD56E, 0x8AB2, 0xD56F, 0x8AB3, 0xD570, 0x8AB4, 0xD571, 0x8AB5, 0xD572, 0x8AB6, 0xD573, 0x8AB7, 0xD574, 0x8AB8,
+ 0xD575, 0x8AB9, 0xD576, 0x8ABA, 0xD577, 0x8ABB, 0xD578, 0x8ABC, 0xD579, 0x8ABD, 0xD57A, 0x8ABE, 0xD57B, 0x8ABF, 0xD57C, 0x8AC0,
+ 0xD57D, 0x8AC1, 0xD57E, 0x8AC2, 0xD580, 0x8AC3, 0xD581, 0x8AC4, 0xD582, 0x8AC5, 0xD583, 0x8AC6, 0xD584, 0x8AC7, 0xD585, 0x8AC8,
+ 0xD586, 0x8AC9, 0xD587, 0x8ACA, 0xD588, 0x8ACB, 0xD589, 0x8ACC, 0xD58A, 0x8ACD, 0xD58B, 0x8ACE, 0xD58C, 0x8ACF, 0xD58D, 0x8AD0,
+ 0xD58E, 0x8AD1, 0xD58F, 0x8AD2, 0xD590, 0x8AD3, 0xD591, 0x8AD4, 0xD592, 0x8AD5, 0xD593, 0x8AD6, 0xD594, 0x8AD7, 0xD595, 0x8AD8,
+ 0xD596, 0x8AD9, 0xD597, 0x8ADA, 0xD598, 0x8ADB, 0xD599, 0x8ADC, 0xD59A, 0x8ADD, 0xD59B, 0x8ADE, 0xD59C, 0x8ADF, 0xD59D, 0x8AE0,
+ 0xD59E, 0x8AE1, 0xD59F, 0x8AE2, 0xD5A0, 0x8AE3, 0xD5A1, 0x94E1, 0xD5A2, 0x95F8, 0xD5A3, 0x7728, 0xD5A4, 0x6805, 0xD5A5, 0x69A8,
+ 0xD5A6, 0x548B, 0xD5A7, 0x4E4D, 0xD5A8, 0x70B8, 0xD5A9, 0x8BC8, 0xD5AA, 0x6458, 0xD5AB, 0x658B, 0xD5AC, 0x5B85, 0xD5AD, 0x7A84,
+ 0xD5AE, 0x503A, 0xD5AF, 0x5BE8, 0xD5B0, 0x77BB, 0xD5B1, 0x6BE1, 0xD5B2, 0x8A79, 0xD5B3, 0x7C98, 0xD5B4, 0x6CBE, 0xD5B5, 0x76CF,
+ 0xD5B6, 0x65A9, 0xD5B7, 0x8F97, 0xD5B8, 0x5D2D, 0xD5B9, 0x5C55, 0xD5BA, 0x8638, 0xD5BB, 0x6808, 0xD5BC, 0x5360, 0xD5BD, 0x6218,
+ 0xD5BE, 0x7AD9, 0xD5BF, 0x6E5B, 0xD5C0, 0x7EFD, 0xD5C1, 0x6A1F, 0xD5C2, 0x7AE0, 0xD5C3, 0x5F70, 0xD5C4, 0x6F33, 0xD5C5, 0x5F20,
+ 0xD5C6, 0x638C, 0xD5C7, 0x6DA8, 0xD5C8, 0x6756, 0xD5C9, 0x4E08, 0xD5CA, 0x5E10, 0xD5CB, 0x8D26, 0xD5CC, 0x4ED7, 0xD5CD, 0x80C0,
+ 0xD5CE, 0x7634, 0xD5CF, 0x969C, 0xD5D0, 0x62DB, 0xD5D1, 0x662D, 0xD5D2, 0x627E, 0xD5D3, 0x6CBC, 0xD5D4, 0x8D75, 0xD5D5, 0x7167,
+ 0xD5D6, 0x7F69, 0xD5D7, 0x5146, 0xD5D8, 0x8087, 0xD5D9, 0x53EC, 0xD5DA, 0x906E, 0xD5DB, 0x6298, 0xD5DC, 0x54F2, 0xD5DD, 0x86F0,
+ 0xD5DE, 0x8F99, 0xD5DF, 0x8005, 0xD5E0, 0x9517, 0xD5E1, 0x8517, 0xD5E2, 0x8FD9, 0xD5E3, 0x6D59, 0xD5E4, 0x73CD, 0xD5E5, 0x659F,
+ 0xD5E6, 0x771F, 0xD5E7, 0x7504, 0xD5E8, 0x7827, 0xD5E9, 0x81FB, 0xD5EA, 0x8D1E, 0xD5EB, 0x9488, 0xD5EC, 0x4FA6, 0xD5ED, 0x6795,
+ 0xD5EE, 0x75B9, 0xD5EF, 0x8BCA, 0xD5F0, 0x9707, 0xD5F1, 0x632F, 0xD5F2, 0x9547, 0xD5F3, 0x9635, 0xD5F4, 0x84B8, 0xD5F5, 0x6323,
+ 0xD5F6, 0x7741, 0xD5F7, 0x5F81, 0xD5F8, 0x72F0, 0xD5F9, 0x4E89, 0xD5FA, 0x6014, 0xD5FB, 0x6574, 0xD5FC, 0x62EF, 0xD5FD, 0x6B63,
+ 0xD5FE, 0x653F, 0xD640, 0x8AE4, 0xD641, 0x8AE5, 0xD642, 0x8AE6, 0xD643, 0x8AE7, 0xD644, 0x8AE8, 0xD645, 0x8AE9, 0xD646, 0x8AEA,
+ 0xD647, 0x8AEB, 0xD648, 0x8AEC, 0xD649, 0x8AED, 0xD64A, 0x8AEE, 0xD64B, 0x8AEF, 0xD64C, 0x8AF0, 0xD64D, 0x8AF1, 0xD64E, 0x8AF2,
+ 0xD64F, 0x8AF3, 0xD650, 0x8AF4, 0xD651, 0x8AF5, 0xD652, 0x8AF6, 0xD653, 0x8AF7, 0xD654, 0x8AF8, 0xD655, 0x8AF9, 0xD656, 0x8AFA,
+ 0xD657, 0x8AFB, 0xD658, 0x8AFC, 0xD659, 0x8AFD, 0xD65A, 0x8AFE, 0xD65B, 0x8AFF, 0xD65C, 0x8B00, 0xD65D, 0x8B01, 0xD65E, 0x8B02,
+ 0xD65F, 0x8B03, 0xD660, 0x8B04, 0xD661, 0x8B05, 0xD662, 0x8B06, 0xD663, 0x8B08, 0xD664, 0x8B09, 0xD665, 0x8B0A, 0xD666, 0x8B0B,
+ 0xD667, 0x8B0C, 0xD668, 0x8B0D, 0xD669, 0x8B0E, 0xD66A, 0x8B0F, 0xD66B, 0x8B10, 0xD66C, 0x8B11, 0xD66D, 0x8B12, 0xD66E, 0x8B13,
+ 0xD66F, 0x8B14, 0xD670, 0x8B15, 0xD671, 0x8B16, 0xD672, 0x8B17, 0xD673, 0x8B18, 0xD674, 0x8B19, 0xD675, 0x8B1A, 0xD676, 0x8B1B,
+ 0xD677, 0x8B1C, 0xD678, 0x8B1D, 0xD679, 0x8B1E, 0xD67A, 0x8B1F, 0xD67B, 0x8B20, 0xD67C, 0x8B21, 0xD67D, 0x8B22, 0xD67E, 0x8B23,
+ 0xD680, 0x8B24, 0xD681, 0x8B25, 0xD682, 0x8B27, 0xD683, 0x8B28, 0xD684, 0x8B29, 0xD685, 0x8B2A, 0xD686, 0x8B2B, 0xD687, 0x8B2C,
+ 0xD688, 0x8B2D, 0xD689, 0x8B2E, 0xD68A, 0x8B2F, 0xD68B, 0x8B30, 0xD68C, 0x8B31, 0xD68D, 0x8B32, 0xD68E, 0x8B33, 0xD68F, 0x8B34,
+ 0xD690, 0x8B35, 0xD691, 0x8B36, 0xD692, 0x8B37, 0xD693, 0x8B38, 0xD694, 0x8B39, 0xD695, 0x8B3A, 0xD696, 0x8B3B, 0xD697, 0x8B3C,
+ 0xD698, 0x8B3D, 0xD699, 0x8B3E, 0xD69A, 0x8B3F, 0xD69B, 0x8B40, 0xD69C, 0x8B41, 0xD69D, 0x8B42, 0xD69E, 0x8B43, 0xD69F, 0x8B44,
+ 0xD6A0, 0x8B45, 0xD6A1, 0x5E27, 0xD6A2, 0x75C7, 0xD6A3, 0x90D1, 0xD6A4, 0x8BC1, 0xD6A5, 0x829D, 0xD6A6, 0x679D, 0xD6A7, 0x652F,
+ 0xD6A8, 0x5431, 0xD6A9, 0x8718, 0xD6AA, 0x77E5, 0xD6AB, 0x80A2, 0xD6AC, 0x8102, 0xD6AD, 0x6C41, 0xD6AE, 0x4E4B, 0xD6AF, 0x7EC7,
+ 0xD6B0, 0x804C, 0xD6B1, 0x76F4, 0xD6B2, 0x690D, 0xD6B3, 0x6B96, 0xD6B4, 0x6267, 0xD6B5, 0x503C, 0xD6B6, 0x4F84, 0xD6B7, 0x5740,
+ 0xD6B8, 0x6307, 0xD6B9, 0x6B62, 0xD6BA, 0x8DBE, 0xD6BB, 0x53EA, 0xD6BC, 0x65E8, 0xD6BD, 0x7EB8, 0xD6BE, 0x5FD7, 0xD6BF, 0x631A,
+ 0xD6C0, 0x63B7, 0xD6C1, 0x81F3, 0xD6C2, 0x81F4, 0xD6C3, 0x7F6E, 0xD6C4, 0x5E1C, 0xD6C5, 0x5CD9, 0xD6C6, 0x5236, 0xD6C7, 0x667A,
+ 0xD6C8, 0x79E9, 0xD6C9, 0x7A1A, 0xD6CA, 0x8D28, 0xD6CB, 0x7099, 0xD6CC, 0x75D4, 0xD6CD, 0x6EDE, 0xD6CE, 0x6CBB, 0xD6CF, 0x7A92,
+ 0xD6D0, 0x4E2D, 0xD6D1, 0x76C5, 0xD6D2, 0x5FE0, 0xD6D3, 0x949F, 0xD6D4, 0x8877, 0xD6D5, 0x7EC8, 0xD6D6, 0x79CD, 0xD6D7, 0x80BF,
+ 0xD6D8, 0x91CD, 0xD6D9, 0x4EF2, 0xD6DA, 0x4F17, 0xD6DB, 0x821F, 0xD6DC, 0x5468, 0xD6DD, 0x5DDE, 0xD6DE, 0x6D32, 0xD6DF, 0x8BCC,
+ 0xD6E0, 0x7CA5, 0xD6E1, 0x8F74, 0xD6E2, 0x8098, 0xD6E3, 0x5E1A, 0xD6E4, 0x5492, 0xD6E5, 0x76B1, 0xD6E6, 0x5B99, 0xD6E7, 0x663C,
+ 0xD6E8, 0x9AA4, 0xD6E9, 0x73E0, 0xD6EA, 0x682A, 0xD6EB, 0x86DB, 0xD6EC, 0x6731, 0xD6ED, 0x732A, 0xD6EE, 0x8BF8, 0xD6EF, 0x8BDB,
+ 0xD6F0, 0x9010, 0xD6F1, 0x7AF9, 0xD6F2, 0x70DB, 0xD6F3, 0x716E, 0xD6F4, 0x62C4, 0xD6F5, 0x77A9, 0xD6F6, 0x5631, 0xD6F7, 0x4E3B,
+ 0xD6F8, 0x8457, 0xD6F9, 0x67F1, 0xD6FA, 0x52A9, 0xD6FB, 0x86C0, 0xD6FC, 0x8D2E, 0xD6FD, 0x94F8, 0xD6FE, 0x7B51, 0xD740, 0x8B46,
+ 0xD741, 0x8B47, 0xD742, 0x8B48, 0xD743, 0x8B49, 0xD744, 0x8B4A, 0xD745, 0x8B4B, 0xD746, 0x8B4C, 0xD747, 0x8B4D, 0xD748, 0x8B4E,
+ 0xD749, 0x8B4F, 0xD74A, 0x8B50, 0xD74B, 0x8B51, 0xD74C, 0x8B52, 0xD74D, 0x8B53, 0xD74E, 0x8B54, 0xD74F, 0x8B55, 0xD750, 0x8B56,
+ 0xD751, 0x8B57, 0xD752, 0x8B58, 0xD753, 0x8B59, 0xD754, 0x8B5A, 0xD755, 0x8B5B, 0xD756, 0x8B5C, 0xD757, 0x8B5D, 0xD758, 0x8B5E,
+ 0xD759, 0x8B5F, 0xD75A, 0x8B60, 0xD75B, 0x8B61, 0xD75C, 0x8B62, 0xD75D, 0x8B63, 0xD75E, 0x8B64, 0xD75F, 0x8B65, 0xD760, 0x8B67,
+ 0xD761, 0x8B68, 0xD762, 0x8B69, 0xD763, 0x8B6A, 0xD764, 0x8B6B, 0xD765, 0x8B6D, 0xD766, 0x8B6E, 0xD767, 0x8B6F, 0xD768, 0x8B70,
+ 0xD769, 0x8B71, 0xD76A, 0x8B72, 0xD76B, 0x8B73, 0xD76C, 0x8B74, 0xD76D, 0x8B75, 0xD76E, 0x8B76, 0xD76F, 0x8B77, 0xD770, 0x8B78,
+ 0xD771, 0x8B79, 0xD772, 0x8B7A, 0xD773, 0x8B7B, 0xD774, 0x8B7C, 0xD775, 0x8B7D, 0xD776, 0x8B7E, 0xD777, 0x8B7F, 0xD778, 0x8B80,
+ 0xD779, 0x8B81, 0xD77A, 0x8B82, 0xD77B, 0x8B83, 0xD77C, 0x8B84, 0xD77D, 0x8B85, 0xD77E, 0x8B86, 0xD780, 0x8B87, 0xD781, 0x8B88,
+ 0xD782, 0x8B89, 0xD783, 0x8B8A, 0xD784, 0x8B8B, 0xD785, 0x8B8C, 0xD786, 0x8B8D, 0xD787, 0x8B8E, 0xD788, 0x8B8F, 0xD789, 0x8B90,
+ 0xD78A, 0x8B91, 0xD78B, 0x8B92, 0xD78C, 0x8B93, 0xD78D, 0x8B94, 0xD78E, 0x8B95, 0xD78F, 0x8B96, 0xD790, 0x8B97, 0xD791, 0x8B98,
+ 0xD792, 0x8B99, 0xD793, 0x8B9A, 0xD794, 0x8B9B, 0xD795, 0x8B9C, 0xD796, 0x8B9D, 0xD797, 0x8B9E, 0xD798, 0x8B9F, 0xD799, 0x8BAC,
+ 0xD79A, 0x8BB1, 0xD79B, 0x8BBB, 0xD79C, 0x8BC7, 0xD79D, 0x8BD0, 0xD79E, 0x8BEA, 0xD79F, 0x8C09, 0xD7A0, 0x8C1E, 0xD7A1, 0x4F4F,
+ 0xD7A2, 0x6CE8, 0xD7A3, 0x795D, 0xD7A4, 0x9A7B, 0xD7A5, 0x6293, 0xD7A6, 0x722A, 0xD7A7, 0x62FD, 0xD7A8, 0x4E13, 0xD7A9, 0x7816,
+ 0xD7AA, 0x8F6C, 0xD7AB, 0x64B0, 0xD7AC, 0x8D5A, 0xD7AD, 0x7BC6, 0xD7AE, 0x6869, 0xD7AF, 0x5E84, 0xD7B0, 0x88C5, 0xD7B1, 0x5986,
+ 0xD7B2, 0x649E, 0xD7B3, 0x58EE, 0xD7B4, 0x72B6, 0xD7B5, 0x690E, 0xD7B6, 0x9525, 0xD7B7, 0x8FFD, 0xD7B8, 0x8D58, 0xD7B9, 0x5760,
+ 0xD7BA, 0x7F00, 0xD7BB, 0x8C06, 0xD7BC, 0x51C6, 0xD7BD, 0x6349, 0xD7BE, 0x62D9, 0xD7BF, 0x5353, 0xD7C0, 0x684C, 0xD7C1, 0x7422,
+ 0xD7C2, 0x8301, 0xD7C3, 0x914C, 0xD7C4, 0x5544, 0xD7C5, 0x7740, 0xD7C6, 0x707C, 0xD7C7, 0x6D4A, 0xD7C8, 0x5179, 0xD7C9, 0x54A8,
+ 0xD7CA, 0x8D44, 0xD7CB, 0x59FF, 0xD7CC, 0x6ECB, 0xD7CD, 0x6DC4, 0xD7CE, 0x5B5C, 0xD7CF, 0x7D2B, 0xD7D0, 0x4ED4, 0xD7D1, 0x7C7D,
+ 0xD7D2, 0x6ED3, 0xD7D3, 0x5B50, 0xD7D4, 0x81EA, 0xD7D5, 0x6E0D, 0xD7D6, 0x5B57, 0xD7D7, 0x9B03, 0xD7D8, 0x68D5, 0xD7D9, 0x8E2A,
+ 0xD7DA, 0x5B97, 0xD7DB, 0x7EFC, 0xD7DC, 0x603B, 0xD7DD, 0x7EB5, 0xD7DE, 0x90B9, 0xD7DF, 0x8D70, 0xD7E0, 0x594F, 0xD7E1, 0x63CD,
+ 0xD7E2, 0x79DF, 0xD7E3, 0x8DB3, 0xD7E4, 0x5352, 0xD7E5, 0x65CF, 0xD7E6, 0x7956, 0xD7E7, 0x8BC5, 0xD7E8, 0x963B, 0xD7E9, 0x7EC4,
+ 0xD7EA, 0x94BB, 0xD7EB, 0x7E82, 0xD7EC, 0x5634, 0xD7ED, 0x9189, 0xD7EE, 0x6700, 0xD7EF, 0x7F6A, 0xD7F0, 0x5C0A, 0xD7F1, 0x9075,
+ 0xD7F2, 0x6628, 0xD7F3, 0x5DE6, 0xD7F4, 0x4F50, 0xD7F5, 0x67DE, 0xD7F6, 0x505A, 0xD7F7, 0x4F5C, 0xD7F8, 0x5750, 0xD7F9, 0x5EA7,
+ 0xD840, 0x8C38, 0xD841, 0x8C39, 0xD842, 0x8C3A, 0xD843, 0x8C3B, 0xD844, 0x8C3C, 0xD845, 0x8C3D, 0xD846, 0x8C3E, 0xD847, 0x8C3F,
+ 0xD848, 0x8C40, 0xD849, 0x8C42, 0xD84A, 0x8C43, 0xD84B, 0x8C44, 0xD84C, 0x8C45, 0xD84D, 0x8C48, 0xD84E, 0x8C4A, 0xD84F, 0x8C4B,
+ 0xD850, 0x8C4D, 0xD851, 0x8C4E, 0xD852, 0x8C4F, 0xD853, 0x8C50, 0xD854, 0x8C51, 0xD855, 0x8C52, 0xD856, 0x8C53, 0xD857, 0x8C54,
+ 0xD858, 0x8C56, 0xD859, 0x8C57, 0xD85A, 0x8C58, 0xD85B, 0x8C59, 0xD85C, 0x8C5B, 0xD85D, 0x8C5C, 0xD85E, 0x8C5D, 0xD85F, 0x8C5E,
+ 0xD860, 0x8C5F, 0xD861, 0x8C60, 0xD862, 0x8C63, 0xD863, 0x8C64, 0xD864, 0x8C65, 0xD865, 0x8C66, 0xD866, 0x8C67, 0xD867, 0x8C68,
+ 0xD868, 0x8C69, 0xD869, 0x8C6C, 0xD86A, 0x8C6D, 0xD86B, 0x8C6E, 0xD86C, 0x8C6F, 0xD86D, 0x8C70, 0xD86E, 0x8C71, 0xD86F, 0x8C72,
+ 0xD870, 0x8C74, 0xD871, 0x8C75, 0xD872, 0x8C76, 0xD873, 0x8C77, 0xD874, 0x8C7B, 0xD875, 0x8C7C, 0xD876, 0x8C7D, 0xD877, 0x8C7E,
+ 0xD878, 0x8C7F, 0xD879, 0x8C80, 0xD87A, 0x8C81, 0xD87B, 0x8C83, 0xD87C, 0x8C84, 0xD87D, 0x8C86, 0xD87E, 0x8C87, 0xD880, 0x8C88,
+ 0xD881, 0x8C8B, 0xD882, 0x8C8D, 0xD883, 0x8C8E, 0xD884, 0x8C8F, 0xD885, 0x8C90, 0xD886, 0x8C91, 0xD887, 0x8C92, 0xD888, 0x8C93,
+ 0xD889, 0x8C95, 0xD88A, 0x8C96, 0xD88B, 0x8C97, 0xD88C, 0x8C99, 0xD88D, 0x8C9A, 0xD88E, 0x8C9B, 0xD88F, 0x8C9C, 0xD890, 0x8C9D,
+ 0xD891, 0x8C9E, 0xD892, 0x8C9F, 0xD893, 0x8CA0, 0xD894, 0x8CA1, 0xD895, 0x8CA2, 0xD896, 0x8CA3, 0xD897, 0x8CA4, 0xD898, 0x8CA5,
+ 0xD899, 0x8CA6, 0xD89A, 0x8CA7, 0xD89B, 0x8CA8, 0xD89C, 0x8CA9, 0xD89D, 0x8CAA, 0xD89E, 0x8CAB, 0xD89F, 0x8CAC, 0xD8A0, 0x8CAD,
+ 0xD8A1, 0x4E8D, 0xD8A2, 0x4E0C, 0xD8A3, 0x5140, 0xD8A4, 0x4E10, 0xD8A5, 0x5EFF, 0xD8A6, 0x5345, 0xD8A7, 0x4E15, 0xD8A8, 0x4E98,
+ 0xD8A9, 0x4E1E, 0xD8AA, 0x9B32, 0xD8AB, 0x5B6C, 0xD8AC, 0x5669, 0xD8AD, 0x4E28, 0xD8AE, 0x79BA, 0xD8AF, 0x4E3F, 0xD8B0, 0x5315,
+ 0xD8B1, 0x4E47, 0xD8B2, 0x592D, 0xD8B3, 0x723B, 0xD8B4, 0x536E, 0xD8B5, 0x6C10, 0xD8B6, 0x56DF, 0xD8B7, 0x80E4, 0xD8B8, 0x9997,
+ 0xD8B9, 0x6BD3, 0xD8BA, 0x777E, 0xD8BB, 0x9F17, 0xD8BC, 0x4E36, 0xD8BD, 0x4E9F, 0xD8BE, 0x9F10, 0xD8BF, 0x4E5C, 0xD8C0, 0x4E69,
+ 0xD8C1, 0x4E93, 0xD8C2, 0x8288, 0xD8C3, 0x5B5B, 0xD8C4, 0x556C, 0xD8C5, 0x560F, 0xD8C6, 0x4EC4, 0xD8C7, 0x538D, 0xD8C8, 0x539D,
+ 0xD8C9, 0x53A3, 0xD8CA, 0x53A5, 0xD8CB, 0x53AE, 0xD8CC, 0x9765, 0xD8CD, 0x8D5D, 0xD8CE, 0x531A, 0xD8CF, 0x53F5, 0xD8D0, 0x5326,
+ 0xD8D1, 0x532E, 0xD8D2, 0x533E, 0xD8D3, 0x8D5C, 0xD8D4, 0x5366, 0xD8D5, 0x5363, 0xD8D6, 0x5202, 0xD8D7, 0x5208, 0xD8D8, 0x520E,
+ 0xD8D9, 0x522D, 0xD8DA, 0x5233, 0xD8DB, 0x523F, 0xD8DC, 0x5240, 0xD8DD, 0x524C, 0xD8DE, 0x525E, 0xD8DF, 0x5261, 0xD8E0, 0x525C,
+ 0xD8E1, 0x84AF, 0xD8E2, 0x527D, 0xD8E3, 0x5282, 0xD8E4, 0x5281, 0xD8E5, 0x5290, 0xD8E6, 0x5293, 0xD8E7, 0x5182, 0xD8E8, 0x7F54,
+ 0xD8E9, 0x4EBB, 0xD8EA, 0x4EC3, 0xD8EB, 0x4EC9, 0xD8EC, 0x4EC2, 0xD8ED, 0x4EE8, 0xD8EE, 0x4EE1, 0xD8EF, 0x4EEB, 0xD8F0, 0x4EDE,
+ 0xD8F1, 0x4F1B, 0xD8F2, 0x4EF3, 0xD8F3, 0x4F22, 0xD8F4, 0x4F64, 0xD8F5, 0x4EF5, 0xD8F6, 0x4F25, 0xD8F7, 0x4F27, 0xD8F8, 0x4F09,
+ 0xD8F9, 0x4F2B, 0xD8FA, 0x4F5E, 0xD8FB, 0x4F67, 0xD8FC, 0x6538, 0xD8FD, 0x4F5A, 0xD8FE, 0x4F5D, 0xD940, 0x8CAE, 0xD941, 0x8CAF,
+ 0xD942, 0x8CB0, 0xD943, 0x8CB1, 0xD944, 0x8CB2, 0xD945, 0x8CB3, 0xD946, 0x8CB4, 0xD947, 0x8CB5, 0xD948, 0x8CB6, 0xD949, 0x8CB7,
+ 0xD94A, 0x8CB8, 0xD94B, 0x8CB9, 0xD94C, 0x8CBA, 0xD94D, 0x8CBB, 0xD94E, 0x8CBC, 0xD94F, 0x8CBD, 0xD950, 0x8CBE, 0xD951, 0x8CBF,
+ 0xD952, 0x8CC0, 0xD953, 0x8CC1, 0xD954, 0x8CC2, 0xD955, 0x8CC3, 0xD956, 0x8CC4, 0xD957, 0x8CC5, 0xD958, 0x8CC6, 0xD959, 0x8CC7,
+ 0xD95A, 0x8CC8, 0xD95B, 0x8CC9, 0xD95C, 0x8CCA, 0xD95D, 0x8CCB, 0xD95E, 0x8CCC, 0xD95F, 0x8CCD, 0xD960, 0x8CCE, 0xD961, 0x8CCF,
+ 0xD962, 0x8CD0, 0xD963, 0x8CD1, 0xD964, 0x8CD2, 0xD965, 0x8CD3, 0xD966, 0x8CD4, 0xD967, 0x8CD5, 0xD968, 0x8CD6, 0xD969, 0x8CD7,
+ 0xD96A, 0x8CD8, 0xD96B, 0x8CD9, 0xD96C, 0x8CDA, 0xD96D, 0x8CDB, 0xD96E, 0x8CDC, 0xD96F, 0x8CDD, 0xD970, 0x8CDE, 0xD971, 0x8CDF,
+ 0xD972, 0x8CE0, 0xD973, 0x8CE1, 0xD974, 0x8CE2, 0xD975, 0x8CE3, 0xD976, 0x8CE4, 0xD977, 0x8CE5, 0xD978, 0x8CE6, 0xD979, 0x8CE7,
+ 0xD97A, 0x8CE8, 0xD97B, 0x8CE9, 0xD97C, 0x8CEA, 0xD97D, 0x8CEB, 0xD97E, 0x8CEC, 0xD980, 0x8CED, 0xD981, 0x8CEE, 0xD982, 0x8CEF,
+ 0xD983, 0x8CF0, 0xD984, 0x8CF1, 0xD985, 0x8CF2, 0xD986, 0x8CF3, 0xD987, 0x8CF4, 0xD988, 0x8CF5, 0xD989, 0x8CF6, 0xD98A, 0x8CF7,
+ 0xD98B, 0x8CF8, 0xD98C, 0x8CF9, 0xD98D, 0x8CFA, 0xD98E, 0x8CFB, 0xD98F, 0x8CFC, 0xD990, 0x8CFD, 0xD991, 0x8CFE, 0xD992, 0x8CFF,
+ 0xD993, 0x8D00, 0xD994, 0x8D01, 0xD995, 0x8D02, 0xD996, 0x8D03, 0xD997, 0x8D04, 0xD998, 0x8D05, 0xD999, 0x8D06, 0xD99A, 0x8D07,
+ 0xD99B, 0x8D08, 0xD99C, 0x8D09, 0xD99D, 0x8D0A, 0xD99E, 0x8D0B, 0xD99F, 0x8D0C, 0xD9A0, 0x8D0D, 0xD9A1, 0x4F5F, 0xD9A2, 0x4F57,
+ 0xD9A3, 0x4F32, 0xD9A4, 0x4F3D, 0xD9A5, 0x4F76, 0xD9A6, 0x4F74, 0xD9A7, 0x4F91, 0xD9A8, 0x4F89, 0xD9A9, 0x4F83, 0xD9AA, 0x4F8F,
+ 0xD9AB, 0x4F7E, 0xD9AC, 0x4F7B, 0xD9AD, 0x4FAA, 0xD9AE, 0x4F7C, 0xD9AF, 0x4FAC, 0xD9B0, 0x4F94, 0xD9B1, 0x4FE6, 0xD9B2, 0x4FE8,
+ 0xD9B3, 0x4FEA, 0xD9B4, 0x4FC5, 0xD9B5, 0x4FDA, 0xD9B6, 0x4FE3, 0xD9B7, 0x4FDC, 0xD9B8, 0x4FD1, 0xD9B9, 0x4FDF, 0xD9BA, 0x4FF8,
+ 0xD9BB, 0x5029, 0xD9BC, 0x504C, 0xD9BD, 0x4FF3, 0xD9BE, 0x502C, 0xD9BF, 0x500F, 0xD9C0, 0x502E, 0xD9C1, 0x502D, 0xD9C2, 0x4FFE,
+ 0xD9C3, 0x501C, 0xD9C4, 0x500C, 0xD9C5, 0x5025, 0xD9C6, 0x5028, 0xD9C7, 0x507E, 0xD9C8, 0x5043, 0xD9C9, 0x5055, 0xD9CA, 0x5048,
+ 0xD9CB, 0x504E, 0xD9CC, 0x506C, 0xD9CD, 0x507B, 0xD9CE, 0x50A5, 0xD9CF, 0x50A7, 0xD9D0, 0x50A9, 0xD9D1, 0x50BA, 0xD9D2, 0x50D6,
+ 0xD9D3, 0x5106, 0xD9D4, 0x50ED, 0xD9D5, 0x50EC, 0xD9D6, 0x50E6, 0xD9D7, 0x50EE, 0xD9D8, 0x5107, 0xD9D9, 0x510B, 0xD9DA, 0x4EDD,
+ 0xD9DB, 0x6C3D, 0xD9DC, 0x4F58, 0xD9DD, 0x4F65, 0xD9DE, 0x4FCE, 0xD9DF, 0x9FA0, 0xD9E0, 0x6C46, 0xD9E1, 0x7C74, 0xD9E2, 0x516E,
+ 0xD9E3, 0x5DFD, 0xD9E4, 0x9EC9, 0xD9E5, 0x9998, 0xD9E6, 0x5181, 0xD9E7, 0x5914, 0xD9E8, 0x52F9, 0xD9E9, 0x530D, 0xD9EA, 0x8A07,
+ 0xD9EB, 0x5310, 0xD9EC, 0x51EB, 0xD9ED, 0x5919, 0xD9EE, 0x5155, 0xD9EF, 0x4EA0, 0xD9F0, 0x5156, 0xD9F1, 0x4EB3, 0xD9F2, 0x886E,
+ 0xD9F3, 0x88A4, 0xD9F4, 0x4EB5, 0xD9F5, 0x8114, 0xD9F6, 0x88D2, 0xD9F7, 0x7980, 0xD9F8, 0x5B34, 0xD9F9, 0x8803, 0xD9FA, 0x7FB8,
+ 0xD9FB, 0x51AB, 0xD9FC, 0x51B1, 0xD9FD, 0x51BD, 0xD9FE, 0x51BC, 0xDA40, 0x8D0E, 0xDA41, 0x8D0F, 0xDA42, 0x8D10, 0xDA43, 0x8D11,
+ 0xDA44, 0x8D12, 0xDA45, 0x8D13, 0xDA46, 0x8D14, 0xDA47, 0x8D15, 0xDA48, 0x8D16, 0xDA49, 0x8D17, 0xDA4A, 0x8D18, 0xDA4B, 0x8D19,
+ 0xDA4C, 0x8D1A, 0xDA4D, 0x8D1B, 0xDA4E, 0x8D1C, 0xDA4F, 0x8D20, 0xDA50, 0x8D51, 0xDA51, 0x8D52, 0xDA52, 0x8D57, 0xDA53, 0x8D5F,
+ 0xDA54, 0x8D65, 0xDA55, 0x8D68, 0xDA56, 0x8D69, 0xDA57, 0x8D6A, 0xDA58, 0x8D6C, 0xDA59, 0x8D6E, 0xDA5A, 0x8D6F, 0xDA5B, 0x8D71,
+ 0xDA5C, 0x8D72, 0xDA5D, 0x8D78, 0xDA5E, 0x8D79, 0xDA5F, 0x8D7A, 0xDA60, 0x8D7B, 0xDA61, 0x8D7C, 0xDA62, 0x8D7D, 0xDA63, 0x8D7E,
+ 0xDA64, 0x8D7F, 0xDA65, 0x8D80, 0xDA66, 0x8D82, 0xDA67, 0x8D83, 0xDA68, 0x8D86, 0xDA69, 0x8D87, 0xDA6A, 0x8D88, 0xDA6B, 0x8D89,
+ 0xDA6C, 0x8D8C, 0xDA6D, 0x8D8D, 0xDA6E, 0x8D8E, 0xDA6F, 0x8D8F, 0xDA70, 0x8D90, 0xDA71, 0x8D92, 0xDA72, 0x8D93, 0xDA73, 0x8D95,
+ 0xDA74, 0x8D96, 0xDA75, 0x8D97, 0xDA76, 0x8D98, 0xDA77, 0x8D99, 0xDA78, 0x8D9A, 0xDA79, 0x8D9B, 0xDA7A, 0x8D9C, 0xDA7B, 0x8D9D,
+ 0xDA7C, 0x8D9E, 0xDA7D, 0x8DA0, 0xDA7E, 0x8DA1, 0xDA80, 0x8DA2, 0xDA81, 0x8DA4, 0xDA82, 0x8DA5, 0xDA83, 0x8DA6, 0xDA84, 0x8DA7,
+ 0xDA85, 0x8DA8, 0xDA86, 0x8DA9, 0xDA87, 0x8DAA, 0xDA88, 0x8DAB, 0xDA89, 0x8DAC, 0xDA8A, 0x8DAD, 0xDA8B, 0x8DAE, 0xDA8C, 0x8DAF,
+ 0xDA8D, 0x8DB0, 0xDA8E, 0x8DB2, 0xDA8F, 0x8DB6, 0xDA90, 0x8DB7, 0xDA91, 0x8DB9, 0xDA92, 0x8DBB, 0xDA93, 0x8DBD, 0xDA94, 0x8DC0,
+ 0xDA95, 0x8DC1, 0xDA96, 0x8DC2, 0xDA97, 0x8DC5, 0xDA98, 0x8DC7, 0xDA99, 0x8DC8, 0xDA9A, 0x8DC9, 0xDA9B, 0x8DCA, 0xDA9C, 0x8DCD,
+ 0xDA9D, 0x8DD0, 0xDA9E, 0x8DD2, 0xDA9F, 0x8DD3, 0xDAA0, 0x8DD4, 0xDAA1, 0x51C7, 0xDAA2, 0x5196, 0xDAA3, 0x51A2, 0xDAA4, 0x51A5,
+ 0xDAA5, 0x8BA0, 0xDAA6, 0x8BA6, 0xDAA7, 0x8BA7, 0xDAA8, 0x8BAA, 0xDAA9, 0x8BB4, 0xDAAA, 0x8BB5, 0xDAAB, 0x8BB7, 0xDAAC, 0x8BC2,
+ 0xDAAD, 0x8BC3, 0xDAAE, 0x8BCB, 0xDAAF, 0x8BCF, 0xDAB0, 0x8BCE, 0xDAB1, 0x8BD2, 0xDAB2, 0x8BD3, 0xDAB3, 0x8BD4, 0xDAB4, 0x8BD6,
+ 0xDAB5, 0x8BD8, 0xDAB6, 0x8BD9, 0xDAB7, 0x8BDC, 0xDAB8, 0x8BDF, 0xDAB9, 0x8BE0, 0xDABA, 0x8BE4, 0xDABB, 0x8BE8, 0xDABC, 0x8BE9,
+ 0xDABD, 0x8BEE, 0xDABE, 0x8BF0, 0xDABF, 0x8BF3, 0xDAC0, 0x8BF6, 0xDAC1, 0x8BF9, 0xDAC2, 0x8BFC, 0xDAC3, 0x8BFF, 0xDAC4, 0x8C00,
+ 0xDAC5, 0x8C02, 0xDAC6, 0x8C04, 0xDAC7, 0x8C07, 0xDAC8, 0x8C0C, 0xDAC9, 0x8C0F, 0xDACA, 0x8C11, 0xDACB, 0x8C12, 0xDACC, 0x8C14,
+ 0xDACD, 0x8C15, 0xDACE, 0x8C16, 0xDACF, 0x8C19, 0xDAD0, 0x8C1B, 0xDAD1, 0x8C18, 0xDAD2, 0x8C1D, 0xDAD3, 0x8C1F, 0xDAD4, 0x8C20,
+ 0xDAD5, 0x8C21, 0xDAD6, 0x8C25, 0xDAD7, 0x8C27, 0xDAD8, 0x8C2A, 0xDAD9, 0x8C2B, 0xDADA, 0x8C2E, 0xDADB, 0x8C2F, 0xDADC, 0x8C32,
+ 0xDADD, 0x8C33, 0xDADE, 0x8C35, 0xDADF, 0x8C36, 0xDAE0, 0x5369, 0xDAE1, 0x537A, 0xDAE2, 0x961D, 0xDAE3, 0x9622, 0xDAE4, 0x9621,
+ 0xDAE5, 0x9631, 0xDAE6, 0x962A, 0xDAE7, 0x963D, 0xDAE8, 0x963C, 0xDAE9, 0x9642, 0xDAEA, 0x9649, 0xDAEB, 0x9654, 0xDAEC, 0x965F,
+ 0xDAED, 0x9667, 0xDAEE, 0x966C, 0xDAEF, 0x9672, 0xDAF0, 0x9674, 0xDAF1, 0x9688, 0xDAF2, 0x968D, 0xDAF3, 0x9697, 0xDAF4, 0x96B0,
+ 0xDAF5, 0x9097, 0xDAF6, 0x909B, 0xDAF7, 0x909D, 0xDAF8, 0x9099, 0xDAF9, 0x90AC, 0xDAFA, 0x90A1, 0xDAFB, 0x90B4, 0xDAFC, 0x90B3,
+ 0xDAFD, 0x90B6, 0xDAFE, 0x90BA, 0xDB40, 0x8DD5, 0xDB41, 0x8DD8, 0xDB42, 0x8DD9, 0xDB43, 0x8DDC, 0xDB44, 0x8DE0, 0xDB45, 0x8DE1,
+ 0xDB46, 0x8DE2, 0xDB47, 0x8DE5, 0xDB48, 0x8DE6, 0xDB49, 0x8DE7, 0xDB4A, 0x8DE9, 0xDB4B, 0x8DED, 0xDB4C, 0x8DEE, 0xDB4D, 0x8DF0,
+ 0xDB4E, 0x8DF1, 0xDB4F, 0x8DF2, 0xDB50, 0x8DF4, 0xDB51, 0x8DF6, 0xDB52, 0x8DFC, 0xDB53, 0x8DFE, 0xDB54, 0x8DFF, 0xDB55, 0x8E00,
+ 0xDB56, 0x8E01, 0xDB57, 0x8E02, 0xDB58, 0x8E03, 0xDB59, 0x8E04, 0xDB5A, 0x8E06, 0xDB5B, 0x8E07, 0xDB5C, 0x8E08, 0xDB5D, 0x8E0B,
+ 0xDB5E, 0x8E0D, 0xDB5F, 0x8E0E, 0xDB60, 0x8E10, 0xDB61, 0x8E11, 0xDB62, 0x8E12, 0xDB63, 0x8E13, 0xDB64, 0x8E15, 0xDB65, 0x8E16,
+ 0xDB66, 0x8E17, 0xDB67, 0x8E18, 0xDB68, 0x8E19, 0xDB69, 0x8E1A, 0xDB6A, 0x8E1B, 0xDB6B, 0x8E1C, 0xDB6C, 0x8E20, 0xDB6D, 0x8E21,
+ 0xDB6E, 0x8E24, 0xDB6F, 0x8E25, 0xDB70, 0x8E26, 0xDB71, 0x8E27, 0xDB72, 0x8E28, 0xDB73, 0x8E2B, 0xDB74, 0x8E2D, 0xDB75, 0x8E30,
+ 0xDB76, 0x8E32, 0xDB77, 0x8E33, 0xDB78, 0x8E34, 0xDB79, 0x8E36, 0xDB7A, 0x8E37, 0xDB7B, 0x8E38, 0xDB7C, 0x8E3B, 0xDB7D, 0x8E3C,
+ 0xDB7E, 0x8E3E, 0xDB80, 0x8E3F, 0xDB81, 0x8E43, 0xDB82, 0x8E45, 0xDB83, 0x8E46, 0xDB84, 0x8E4C, 0xDB85, 0x8E4D, 0xDB86, 0x8E4E,
+ 0xDB87, 0x8E4F, 0xDB88, 0x8E50, 0xDB89, 0x8E53, 0xDB8A, 0x8E54, 0xDB8B, 0x8E55, 0xDB8C, 0x8E56, 0xDB8D, 0x8E57, 0xDB8E, 0x8E58,
+ 0xDB8F, 0x8E5A, 0xDB90, 0x8E5B, 0xDB91, 0x8E5C, 0xDB92, 0x8E5D, 0xDB93, 0x8E5E, 0xDB94, 0x8E5F, 0xDB95, 0x8E60, 0xDB96, 0x8E61,
+ 0xDB97, 0x8E62, 0xDB98, 0x8E63, 0xDB99, 0x8E64, 0xDB9A, 0x8E65, 0xDB9B, 0x8E67, 0xDB9C, 0x8E68, 0xDB9D, 0x8E6A, 0xDB9E, 0x8E6B,
+ 0xDB9F, 0x8E6E, 0xDBA0, 0x8E71, 0xDBA1, 0x90B8, 0xDBA2, 0x90B0, 0xDBA3, 0x90CF, 0xDBA4, 0x90C5, 0xDBA5, 0x90BE, 0xDBA6, 0x90D0,
+ 0xDBA7, 0x90C4, 0xDBA8, 0x90C7, 0xDBA9, 0x90D3, 0xDBAA, 0x90E6, 0xDBAB, 0x90E2, 0xDBAC, 0x90DC, 0xDBAD, 0x90D7, 0xDBAE, 0x90DB,
+ 0xDBAF, 0x90EB, 0xDBB0, 0x90EF, 0xDBB1, 0x90FE, 0xDBB2, 0x9104, 0xDBB3, 0x9122, 0xDBB4, 0x911E, 0xDBB5, 0x9123, 0xDBB6, 0x9131,
+ 0xDBB7, 0x912F, 0xDBB8, 0x9139, 0xDBB9, 0x9143, 0xDBBA, 0x9146, 0xDBBB, 0x520D, 0xDBBC, 0x5942, 0xDBBD, 0x52A2, 0xDBBE, 0x52AC,
+ 0xDBBF, 0x52AD, 0xDBC0, 0x52BE, 0xDBC1, 0x54FF, 0xDBC2, 0x52D0, 0xDBC3, 0x52D6, 0xDBC4, 0x52F0, 0xDBC5, 0x53DF, 0xDBC6, 0x71EE,
+ 0xDBC7, 0x77CD, 0xDBC8, 0x5EF4, 0xDBC9, 0x51F5, 0xDBCA, 0x51FC, 0xDBCB, 0x9B2F, 0xDBCC, 0x53B6, 0xDBCD, 0x5F01, 0xDBCE, 0x755A,
+ 0xDBCF, 0x5DEF, 0xDBD0, 0x574C, 0xDBD1, 0x57A9, 0xDBD2, 0x57A1, 0xDBD3, 0x587E, 0xDBD4, 0x58BC, 0xDBD5, 0x58C5, 0xDBD6, 0x58D1,
+ 0xDBD7, 0x5729, 0xDBD8, 0x572C, 0xDBD9, 0x572A, 0xDBDA, 0x5733, 0xDBDB, 0x5739, 0xDBDC, 0x572E, 0xDBDD, 0x572F, 0xDBDE, 0x575C,
+ 0xDBDF, 0x573B, 0xDBE0, 0x5742, 0xDBE1, 0x5769, 0xDBE2, 0x5785, 0xDBE3, 0x576B, 0xDBE4, 0x5786, 0xDBE5, 0x577C, 0xDBE6, 0x577B,
+ 0xDBE7, 0x5768, 0xDBE8, 0x576D, 0xDBE9, 0x5776, 0xDBEA, 0x5773, 0xDBEB, 0x57AD, 0xDBEC, 0x57A4, 0xDBED, 0x578C, 0xDBEE, 0x57B2,
+ 0xDBEF, 0x57CF, 0xDBF0, 0x57A7, 0xDBF1, 0x57B4, 0xDBF2, 0x5793, 0xDBF3, 0x57A0, 0xDBF4, 0x57D5, 0xDBF5, 0x57D8, 0xDBF6, 0x57DA,
+ 0xDBF7, 0x57D9, 0xDBF8, 0x57D2, 0xDBF9, 0x57B8, 0xDBFA, 0x57F4, 0xDBFB, 0x57EF, 0xDBFC, 0x57F8, 0xDBFD, 0x57E4, 0xDBFE, 0x57DD,
+ 0xDC40, 0x8E73, 0xDC41, 0x8E75, 0xDC42, 0x8E77, 0xDC43, 0x8E78, 0xDC44, 0x8E79, 0xDC45, 0x8E7A, 0xDC46, 0x8E7B, 0xDC47, 0x8E7D,
+ 0xDC48, 0x8E7E, 0xDC49, 0x8E80, 0xDC4A, 0x8E82, 0xDC4B, 0x8E83, 0xDC4C, 0x8E84, 0xDC4D, 0x8E86, 0xDC4E, 0x8E88, 0xDC4F, 0x8E89,
+ 0xDC50, 0x8E8A, 0xDC51, 0x8E8B, 0xDC52, 0x8E8C, 0xDC53, 0x8E8D, 0xDC54, 0x8E8E, 0xDC55, 0x8E91, 0xDC56, 0x8E92, 0xDC57, 0x8E93,
+ 0xDC58, 0x8E95, 0xDC59, 0x8E96, 0xDC5A, 0x8E97, 0xDC5B, 0x8E98, 0xDC5C, 0x8E99, 0xDC5D, 0x8E9A, 0xDC5E, 0x8E9B, 0xDC5F, 0x8E9D,
+ 0xDC60, 0x8E9F, 0xDC61, 0x8EA0, 0xDC62, 0x8EA1, 0xDC63, 0x8EA2, 0xDC64, 0x8EA3, 0xDC65, 0x8EA4, 0xDC66, 0x8EA5, 0xDC67, 0x8EA6,
+ 0xDC68, 0x8EA7, 0xDC69, 0x8EA8, 0xDC6A, 0x8EA9, 0xDC6B, 0x8EAA, 0xDC6C, 0x8EAD, 0xDC6D, 0x8EAE, 0xDC6E, 0x8EB0, 0xDC6F, 0x8EB1,
+ 0xDC70, 0x8EB3, 0xDC71, 0x8EB4, 0xDC72, 0x8EB5, 0xDC73, 0x8EB6, 0xDC74, 0x8EB7, 0xDC75, 0x8EB8, 0xDC76, 0x8EB9, 0xDC77, 0x8EBB,
+ 0xDC78, 0x8EBC, 0xDC79, 0x8EBD, 0xDC7A, 0x8EBE, 0xDC7B, 0x8EBF, 0xDC7C, 0x8EC0, 0xDC7D, 0x8EC1, 0xDC7E, 0x8EC2, 0xDC80, 0x8EC3,
+ 0xDC81, 0x8EC4, 0xDC82, 0x8EC5, 0xDC83, 0x8EC6, 0xDC84, 0x8EC7, 0xDC85, 0x8EC8, 0xDC86, 0x8EC9, 0xDC87, 0x8ECA, 0xDC88, 0x8ECB,
+ 0xDC89, 0x8ECC, 0xDC8A, 0x8ECD, 0xDC8B, 0x8ECF, 0xDC8C, 0x8ED0, 0xDC8D, 0x8ED1, 0xDC8E, 0x8ED2, 0xDC8F, 0x8ED3, 0xDC90, 0x8ED4,
+ 0xDC91, 0x8ED5, 0xDC92, 0x8ED6, 0xDC93, 0x8ED7, 0xDC94, 0x8ED8, 0xDC95, 0x8ED9, 0xDC96, 0x8EDA, 0xDC97, 0x8EDB, 0xDC98, 0x8EDC,
+ 0xDC99, 0x8EDD, 0xDC9A, 0x8EDE, 0xDC9B, 0x8EDF, 0xDC9C, 0x8EE0, 0xDC9D, 0x8EE1, 0xDC9E, 0x8EE2, 0xDC9F, 0x8EE3, 0xDCA0, 0x8EE4,
+ 0xDCA1, 0x580B, 0xDCA2, 0x580D, 0xDCA3, 0x57FD, 0xDCA4, 0x57ED, 0xDCA5, 0x5800, 0xDCA6, 0x581E, 0xDCA7, 0x5819, 0xDCA8, 0x5844,
+ 0xDCA9, 0x5820, 0xDCAA, 0x5865, 0xDCAB, 0x586C, 0xDCAC, 0x5881, 0xDCAD, 0x5889, 0xDCAE, 0x589A, 0xDCAF, 0x5880, 0xDCB0, 0x99A8,
+ 0xDCB1, 0x9F19, 0xDCB2, 0x61FF, 0xDCB3, 0x8279, 0xDCB4, 0x827D, 0xDCB5, 0x827F, 0xDCB6, 0x828F, 0xDCB7, 0x828A, 0xDCB8, 0x82A8,
+ 0xDCB9, 0x8284, 0xDCBA, 0x828E, 0xDCBB, 0x8291, 0xDCBC, 0x8297, 0xDCBD, 0x8299, 0xDCBE, 0x82AB, 0xDCBF, 0x82B8, 0xDCC0, 0x82BE,
+ 0xDCC1, 0x82B0, 0xDCC2, 0x82C8, 0xDCC3, 0x82CA, 0xDCC4, 0x82E3, 0xDCC5, 0x8298, 0xDCC6, 0x82B7, 0xDCC7, 0x82AE, 0xDCC8, 0x82CB,
+ 0xDCC9, 0x82CC, 0xDCCA, 0x82C1, 0xDCCB, 0x82A9, 0xDCCC, 0x82B4, 0xDCCD, 0x82A1, 0xDCCE, 0x82AA, 0xDCCF, 0x829F, 0xDCD0, 0x82C4,
+ 0xDCD1, 0x82CE, 0xDCD2, 0x82A4, 0xDCD3, 0x82E1, 0xDCD4, 0x8309, 0xDCD5, 0x82F7, 0xDCD6, 0x82E4, 0xDCD7, 0x830F, 0xDCD8, 0x8307,
+ 0xDCD9, 0x82DC, 0xDCDA, 0x82F4, 0xDCDB, 0x82D2, 0xDCDC, 0x82D8, 0xDCDD, 0x830C, 0xDCDE, 0x82FB, 0xDCDF, 0x82D3, 0xDCE0, 0x8311,
+ 0xDCE1, 0x831A, 0xDCE2, 0x8306, 0xDCE3, 0x8314, 0xDCE4, 0x8315, 0xDCE5, 0x82E0, 0xDCE6, 0x82D5, 0xDCE7, 0x831C, 0xDCE8, 0x8351,
+ 0xDCE9, 0x835B, 0xDCEA, 0x835C, 0xDCEB, 0x8308, 0xDCEC, 0x8392, 0xDCED, 0x833C, 0xDCEE, 0x8334, 0xDCEF, 0x8331, 0xDCF0, 0x839B,
+ 0xDCF1, 0x835E, 0xDCF2, 0x832F, 0xDCF3, 0x834F, 0xDCF4, 0x8347, 0xDCF5, 0x8343, 0xDCF6, 0x835F, 0xDCF7, 0x8340, 0xDCF8, 0x8317,
+ 0xDCF9, 0x8360, 0xDCFA, 0x832D, 0xDCFB, 0x833A, 0xDCFC, 0x8333, 0xDCFD, 0x8366, 0xDCFE, 0x8365, 0xDD40, 0x8EE5, 0xDD41, 0x8EE6,
+ 0xDD42, 0x8EE7, 0xDD43, 0x8EE8, 0xDD44, 0x8EE9, 0xDD45, 0x8EEA, 0xDD46, 0x8EEB, 0xDD47, 0x8EEC, 0xDD48, 0x8EED, 0xDD49, 0x8EEE,
+ 0xDD4A, 0x8EEF, 0xDD4B, 0x8EF0, 0xDD4C, 0x8EF1, 0xDD4D, 0x8EF2, 0xDD4E, 0x8EF3, 0xDD4F, 0x8EF4, 0xDD50, 0x8EF5, 0xDD51, 0x8EF6,
+ 0xDD52, 0x8EF7, 0xDD53, 0x8EF8, 0xDD54, 0x8EF9, 0xDD55, 0x8EFA, 0xDD56, 0x8EFB, 0xDD57, 0x8EFC, 0xDD58, 0x8EFD, 0xDD59, 0x8EFE,
+ 0xDD5A, 0x8EFF, 0xDD5B, 0x8F00, 0xDD5C, 0x8F01, 0xDD5D, 0x8F02, 0xDD5E, 0x8F03, 0xDD5F, 0x8F04, 0xDD60, 0x8F05, 0xDD61, 0x8F06,
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+ 0xE1A3, 0x5E54, 0xE1A4, 0x5E5B, 0xE1A5, 0x5E5E, 0xE1A6, 0x5E61, 0xE1A7, 0x5C8C, 0xE1A8, 0x5C7A, 0xE1A9, 0x5C8D, 0xE1AA, 0x5C90,
+ 0xE1AB, 0x5C96, 0xE1AC, 0x5C88, 0xE1AD, 0x5C98, 0xE1AE, 0x5C99, 0xE1AF, 0x5C91, 0xE1B0, 0x5C9A, 0xE1B1, 0x5C9C, 0xE1B2, 0x5CB5,
+ 0xE1B3, 0x5CA2, 0xE1B4, 0x5CBD, 0xE1B5, 0x5CAC, 0xE1B6, 0x5CAB, 0xE1B7, 0x5CB1, 0xE1B8, 0x5CA3, 0xE1B9, 0x5CC1, 0xE1BA, 0x5CB7,
+ 0xE1BB, 0x5CC4, 0xE1BC, 0x5CD2, 0xE1BD, 0x5CE4, 0xE1BE, 0x5CCB, 0xE1BF, 0x5CE5, 0xE1C0, 0x5D02, 0xE1C1, 0x5D03, 0xE1C2, 0x5D27,
+ 0xE1C3, 0x5D26, 0xE1C4, 0x5D2E, 0xE1C5, 0x5D24, 0xE1C6, 0x5D1E, 0xE1C7, 0x5D06, 0xE1C8, 0x5D1B, 0xE1C9, 0x5D58, 0xE1CA, 0x5D3E,
+ 0xE1CB, 0x5D34, 0xE1CC, 0x5D3D, 0xE1CD, 0x5D6C, 0xE1CE, 0x5D5B, 0xE1CF, 0x5D6F, 0xE1D0, 0x5D5D, 0xE1D1, 0x5D6B, 0xE1D2, 0x5D4B,
+ 0xE1D3, 0x5D4A, 0xE1D4, 0x5D69, 0xE1D5, 0x5D74, 0xE1D6, 0x5D82, 0xE1D7, 0x5D99, 0xE1D8, 0x5D9D, 0xE1D9, 0x8C73, 0xE1DA, 0x5DB7,
+ 0xE1DB, 0x5DC5, 0xE1DC, 0x5F73, 0xE1DD, 0x5F77, 0xE1DE, 0x5F82, 0xE1DF, 0x5F87, 0xE1E0, 0x5F89, 0xE1E1, 0x5F8C, 0xE1E2, 0x5F95,
+ 0xE1E3, 0x5F99, 0xE1E4, 0x5F9C, 0xE1E5, 0x5FA8, 0xE1E6, 0x5FAD, 0xE1E7, 0x5FB5, 0xE1E8, 0x5FBC, 0xE1E9, 0x8862, 0xE1EA, 0x5F61,
+ 0xE1EB, 0x72AD, 0xE1EC, 0x72B0, 0xE1ED, 0x72B4, 0xE1EE, 0x72B7, 0xE1EF, 0x72B8, 0xE1F0, 0x72C3, 0xE1F1, 0x72C1, 0xE1F2, 0x72CE,
+ 0xE1F3, 0x72CD, 0xE1F4, 0x72D2, 0xE1F5, 0x72E8, 0xE1F6, 0x72EF, 0xE1F7, 0x72E9, 0xE1F8, 0x72F2, 0xE1F9, 0x72F4, 0xE1FA, 0x72F7,
+ 0xE1FB, 0x7301, 0xE1FC, 0x72F3, 0xE1FD, 0x7303, 0xE1FE, 0x72FA, 0xE240, 0x91E6, 0xE241, 0x91E7, 0xE242, 0x91E8, 0xE243, 0x91E9,
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+ 0xE2A5, 0x730A, 0xE2A6, 0x731E, 0xE2A7, 0x731D, 0xE2A8, 0x7315, 0xE2A9, 0x7322, 0xE2AA, 0x7339, 0xE2AB, 0x7325, 0xE2AC, 0x732C,
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+ 0xE2B5, 0x737E, 0xE2B6, 0x821B, 0xE2B7, 0x5925, 0xE2B8, 0x98E7, 0xE2B9, 0x5924, 0xE2BA, 0x5902, 0xE2BB, 0x9963, 0xE2BC, 0x9967,
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+ 0xE2D5, 0x5EB9, 0xE2D6, 0x5EB5, 0xE2D7, 0x5EBE, 0xE2D8, 0x5EB3, 0xE2D9, 0x8D53, 0xE2DA, 0x5ED2, 0xE2DB, 0x5ED1, 0xE2DC, 0x5EDB,
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+ 0xE2E5, 0x5FEE, 0xE2E6, 0x6004, 0xE2E7, 0x5FE1, 0xE2E8, 0x5FE4, 0xE2E9, 0x5FFE, 0xE2EA, 0x6005, 0xE2EB, 0x6006, 0xE2EC, 0x5FEA,
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+ 0xE3A7, 0x6083, 0xE3A8, 0x6092, 0xE3A9, 0x608C, 0xE3AA, 0x609B, 0xE3AB, 0x60EC, 0xE3AC, 0x60BB, 0xE3AD, 0x60B1, 0xE3AE, 0x60DD,
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+ 0xE3F7, 0x6CD6, 0xE3F8, 0x6CFA, 0xE3F9, 0x6CEB, 0xE3FA, 0x6CEE, 0xE3FB, 0x6CB1, 0xE3FC, 0x6CD3, 0xE3FD, 0x6CEF, 0xE3FE, 0x6CFE,
+ 0xE440, 0x92A8, 0xE441, 0x92A9, 0xE442, 0x92AA, 0xE443, 0x92AB, 0xE444, 0x92AC, 0xE445, 0x92AD, 0xE446, 0x92AF, 0xE447, 0x92B0,
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+ 0xE4B1, 0x6D54, 0xE4B2, 0x6D33, 0xE4B3, 0x6D91, 0xE4B4, 0x6D6F, 0xE4B5, 0x6D9E, 0xE4B6, 0x6DA0, 0xE4B7, 0x6D5E, 0xE4B8, 0x6D93,
+ 0xE4B9, 0x6D94, 0xE4BA, 0x6D5C, 0xE4BB, 0x6D60, 0xE4BC, 0x6D7C, 0xE4BD, 0x6D63, 0xE4BE, 0x6E1A, 0xE4BF, 0x6DC7, 0xE4C0, 0x6DC5,
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+ 0xF060, 0x992A, 0xF061, 0x992B, 0xF062, 0x992C, 0xF063, 0x992D, 0xF064, 0x992F, 0xF065, 0x9930, 0xF066, 0x9931, 0xF067, 0x9932,
+ 0xF068, 0x9933, 0xF069, 0x9934, 0xF06A, 0x9935, 0xF06B, 0x9936, 0xF06C, 0x9937, 0xF06D, 0x9938, 0xF06E, 0x9939, 0xF06F, 0x993A,
+ 0xF070, 0x993B, 0xF071, 0x993C, 0xF072, 0x993D, 0xF073, 0x993E, 0xF074, 0x993F, 0xF075, 0x9940, 0xF076, 0x9941, 0xF077, 0x9942,
+ 0xF078, 0x9943, 0xF079, 0x9944, 0xF07A, 0x9945, 0xF07B, 0x9946, 0xF07C, 0x9947, 0xF07D, 0x9948, 0xF07E, 0x9949, 0xF080, 0x994A,
+ 0xF081, 0x994B, 0xF082, 0x994C, 0xF083, 0x994D, 0xF084, 0x994E, 0xF085, 0x994F, 0xF086, 0x9950, 0xF087, 0x9951, 0xF088, 0x9952,
+ 0xF089, 0x9953, 0xF08A, 0x9956, 0xF08B, 0x9957, 0xF08C, 0x9958, 0xF08D, 0x9959, 0xF08E, 0x995A, 0xF08F, 0x995B, 0xF090, 0x995C,
+ 0xF091, 0x995D, 0xF092, 0x995E, 0xF093, 0x995F, 0xF094, 0x9960, 0xF095, 0x9961, 0xF096, 0x9962, 0xF097, 0x9964, 0xF098, 0x9966,
+ 0xF099, 0x9973, 0xF09A, 0x9978, 0xF09B, 0x9979, 0xF09C, 0x997B, 0xF09D, 0x997E, 0xF09E, 0x9982, 0xF09F, 0x9983, 0xF0A0, 0x9989,
+ 0xF0A1, 0x7A39, 0xF0A2, 0x7A37, 0xF0A3, 0x7A51, 0xF0A4, 0x9ECF, 0xF0A5, 0x99A5, 0xF0A6, 0x7A70, 0xF0A7, 0x7688, 0xF0A8, 0x768E,
+ 0xF0A9, 0x7693, 0xF0AA, 0x7699, 0xF0AB, 0x76A4, 0xF0AC, 0x74DE, 0xF0AD, 0x74E0, 0xF0AE, 0x752C, 0xF0AF, 0x9E20, 0xF0B0, 0x9E22,
+ 0xF0B1, 0x9E28, 0xF0B2, 0x9E29, 0xF0B3, 0x9E2A, 0xF0B4, 0x9E2B, 0xF0B5, 0x9E2C, 0xF0B6, 0x9E32, 0xF0B7, 0x9E31, 0xF0B8, 0x9E36,
+ 0xF0B9, 0x9E38, 0xF0BA, 0x9E37, 0xF0BB, 0x9E39, 0xF0BC, 0x9E3A, 0xF0BD, 0x9E3E, 0xF0BE, 0x9E41, 0xF0BF, 0x9E42, 0xF0C0, 0x9E44,
+ 0xF0C1, 0x9E46, 0xF0C2, 0x9E47, 0xF0C3, 0x9E48, 0xF0C4, 0x9E49, 0xF0C5, 0x9E4B, 0xF0C6, 0x9E4C, 0xF0C7, 0x9E4E, 0xF0C8, 0x9E51,
+ 0xF0C9, 0x9E55, 0xF0CA, 0x9E57, 0xF0CB, 0x9E5A, 0xF0CC, 0x9E5B, 0xF0CD, 0x9E5C, 0xF0CE, 0x9E5E, 0xF0CF, 0x9E63, 0xF0D0, 0x9E66,
+ 0xF0D1, 0x9E67, 0xF0D2, 0x9E68, 0xF0D3, 0x9E69, 0xF0D4, 0x9E6A, 0xF0D5, 0x9E6B, 0xF0D6, 0x9E6C, 0xF0D7, 0x9E71, 0xF0D8, 0x9E6D,
+ 0xF0D9, 0x9E73, 0xF0DA, 0x7592, 0xF0DB, 0x7594, 0xF0DC, 0x7596, 0xF0DD, 0x75A0, 0xF0DE, 0x759D, 0xF0DF, 0x75AC, 0xF0E0, 0x75A3,
+ 0xF0E1, 0x75B3, 0xF0E2, 0x75B4, 0xF0E3, 0x75B8, 0xF0E4, 0x75C4, 0xF0E5, 0x75B1, 0xF0E6, 0x75B0, 0xF0E7, 0x75C3, 0xF0E8, 0x75C2,
+ 0xF0E9, 0x75D6, 0xF0EA, 0x75CD, 0xF0EB, 0x75E3, 0xF0EC, 0x75E8, 0xF0ED, 0x75E6, 0xF0EE, 0x75E4, 0xF0EF, 0x75EB, 0xF0F0, 0x75E7,
+ 0xF0F1, 0x7603, 0xF0F2, 0x75F1, 0xF0F3, 0x75FC, 0xF0F4, 0x75FF, 0xF0F5, 0x7610, 0xF0F6, 0x7600, 0xF0F7, 0x7605, 0xF0F8, 0x760C,
+ 0xF0F9, 0x7617, 0xF0FA, 0x760A, 0xF0FB, 0x7625, 0xF0FC, 0x7618, 0xF0FD, 0x7615, 0xF0FE, 0x7619, 0xF140, 0x998C, 0xF141, 0x998E,
+ 0xF142, 0x999A, 0xF143, 0x999B, 0xF144, 0x999C, 0xF145, 0x999D, 0xF146, 0x999E, 0xF147, 0x999F, 0xF148, 0x99A0, 0xF149, 0x99A1,
+ 0xF14A, 0x99A2, 0xF14B, 0x99A3, 0xF14C, 0x99A4, 0xF14D, 0x99A6, 0xF14E, 0x99A7, 0xF14F, 0x99A9, 0xF150, 0x99AA, 0xF151, 0x99AB,
+ 0xF152, 0x99AC, 0xF153, 0x99AD, 0xF154, 0x99AE, 0xF155, 0x99AF, 0xF156, 0x99B0, 0xF157, 0x99B1, 0xF158, 0x99B2, 0xF159, 0x99B3,
+ 0xF15A, 0x99B4, 0xF15B, 0x99B5, 0xF15C, 0x99B6, 0xF15D, 0x99B7, 0xF15E, 0x99B8, 0xF15F, 0x99B9, 0xF160, 0x99BA, 0xF161, 0x99BB,
+ 0xF162, 0x99BC, 0xF163, 0x99BD, 0xF164, 0x99BE, 0xF165, 0x99BF, 0xF166, 0x99C0, 0xF167, 0x99C1, 0xF168, 0x99C2, 0xF169, 0x99C3,
+ 0xF16A, 0x99C4, 0xF16B, 0x99C5, 0xF16C, 0x99C6, 0xF16D, 0x99C7, 0xF16E, 0x99C8, 0xF16F, 0x99C9, 0xF170, 0x99CA, 0xF171, 0x99CB,
+ 0xF172, 0x99CC, 0xF173, 0x99CD, 0xF174, 0x99CE, 0xF175, 0x99CF, 0xF176, 0x99D0, 0xF177, 0x99D1, 0xF178, 0x99D2, 0xF179, 0x99D3,
+ 0xF17A, 0x99D4, 0xF17B, 0x99D5, 0xF17C, 0x99D6, 0xF17D, 0x99D7, 0xF17E, 0x99D8, 0xF180, 0x99D9, 0xF181, 0x99DA, 0xF182, 0x99DB,
+ 0xF183, 0x99DC, 0xF184, 0x99DD, 0xF185, 0x99DE, 0xF186, 0x99DF, 0xF187, 0x99E0, 0xF188, 0x99E1, 0xF189, 0x99E2, 0xF18A, 0x99E3,
+ 0xF18B, 0x99E4, 0xF18C, 0x99E5, 0xF18D, 0x99E6, 0xF18E, 0x99E7, 0xF18F, 0x99E8, 0xF190, 0x99E9, 0xF191, 0x99EA, 0xF192, 0x99EB,
+ 0xF193, 0x99EC, 0xF194, 0x99ED, 0xF195, 0x99EE, 0xF196, 0x99EF, 0xF197, 0x99F0, 0xF198, 0x99F1, 0xF199, 0x99F2, 0xF19A, 0x99F3,
+ 0xF19B, 0x99F4, 0xF19C, 0x99F5, 0xF19D, 0x99F6, 0xF19E, 0x99F7, 0xF19F, 0x99F8, 0xF1A0, 0x99F9, 0xF1A1, 0x761B, 0xF1A2, 0x763C,
+ 0xF1A3, 0x7622, 0xF1A4, 0x7620, 0xF1A5, 0x7640, 0xF1A6, 0x762D, 0xF1A7, 0x7630, 0xF1A8, 0x763F, 0xF1A9, 0x7635, 0xF1AA, 0x7643,
+ 0xF1AB, 0x763E, 0xF1AC, 0x7633, 0xF1AD, 0x764D, 0xF1AE, 0x765E, 0xF1AF, 0x7654, 0xF1B0, 0x765C, 0xF1B1, 0x7656, 0xF1B2, 0x766B,
+ 0xF1B3, 0x766F, 0xF1B4, 0x7FCA, 0xF1B5, 0x7AE6, 0xF1B6, 0x7A78, 0xF1B7, 0x7A79, 0xF1B8, 0x7A80, 0xF1B9, 0x7A86, 0xF1BA, 0x7A88,
+ 0xF1BB, 0x7A95, 0xF1BC, 0x7AA6, 0xF1BD, 0x7AA0, 0xF1BE, 0x7AAC, 0xF1BF, 0x7AA8, 0xF1C0, 0x7AAD, 0xF1C1, 0x7AB3, 0xF1C2, 0x8864,
+ 0xF1C3, 0x8869, 0xF1C4, 0x8872, 0xF1C5, 0x887D, 0xF1C6, 0x887F, 0xF1C7, 0x8882, 0xF1C8, 0x88A2, 0xF1C9, 0x88C6, 0xF1CA, 0x88B7,
+ 0xF1CB, 0x88BC, 0xF1CC, 0x88C9, 0xF1CD, 0x88E2, 0xF1CE, 0x88CE, 0xF1CF, 0x88E3, 0xF1D0, 0x88E5, 0xF1D1, 0x88F1, 0xF1D2, 0x891A,
+ 0xF1D3, 0x88FC, 0xF1D4, 0x88E8, 0xF1D5, 0x88FE, 0xF1D6, 0x88F0, 0xF1D7, 0x8921, 0xF1D8, 0x8919, 0xF1D9, 0x8913, 0xF1DA, 0x891B,
+ 0xF1DB, 0x890A, 0xF1DC, 0x8934, 0xF1DD, 0x892B, 0xF1DE, 0x8936, 0xF1DF, 0x8941, 0xF1E0, 0x8966, 0xF1E1, 0x897B, 0xF1E2, 0x758B,
+ 0xF1E3, 0x80E5, 0xF1E4, 0x76B2, 0xF1E5, 0x76B4, 0xF1E6, 0x77DC, 0xF1E7, 0x8012, 0xF1E8, 0x8014, 0xF1E9, 0x8016, 0xF1EA, 0x801C,
+ 0xF1EB, 0x8020, 0xF1EC, 0x8022, 0xF1ED, 0x8025, 0xF1EE, 0x8026, 0xF1EF, 0x8027, 0xF1F0, 0x8029, 0xF1F1, 0x8028, 0xF1F2, 0x8031,
+ 0xF1F3, 0x800B, 0xF1F4, 0x8035, 0xF1F5, 0x8043, 0xF1F6, 0x8046, 0xF1F7, 0x804D, 0xF1F8, 0x8052, 0xF1F9, 0x8069, 0xF1FA, 0x8071,
+ 0xF1FB, 0x8983, 0xF1FC, 0x9878, 0xF1FD, 0x9880, 0xF1FE, 0x9883, 0xF240, 0x99FA, 0xF241, 0x99FB, 0xF242, 0x99FC, 0xF243, 0x99FD,
+ 0xF244, 0x99FE, 0xF245, 0x99FF, 0xF246, 0x9A00, 0xF247, 0x9A01, 0xF248, 0x9A02, 0xF249, 0x9A03, 0xF24A, 0x9A04, 0xF24B, 0x9A05,
+ 0xF24C, 0x9A06, 0xF24D, 0x9A07, 0xF24E, 0x9A08, 0xF24F, 0x9A09, 0xF250, 0x9A0A, 0xF251, 0x9A0B, 0xF252, 0x9A0C, 0xF253, 0x9A0D,
+ 0xF254, 0x9A0E, 0xF255, 0x9A0F, 0xF256, 0x9A10, 0xF257, 0x9A11, 0xF258, 0x9A12, 0xF259, 0x9A13, 0xF25A, 0x9A14, 0xF25B, 0x9A15,
+ 0xF25C, 0x9A16, 0xF25D, 0x9A17, 0xF25E, 0x9A18, 0xF25F, 0x9A19, 0xF260, 0x9A1A, 0xF261, 0x9A1B, 0xF262, 0x9A1C, 0xF263, 0x9A1D,
+ 0xF264, 0x9A1E, 0xF265, 0x9A1F, 0xF266, 0x9A20, 0xF267, 0x9A21, 0xF268, 0x9A22, 0xF269, 0x9A23, 0xF26A, 0x9A24, 0xF26B, 0x9A25,
+ 0xF26C, 0x9A26, 0xF26D, 0x9A27, 0xF26E, 0x9A28, 0xF26F, 0x9A29, 0xF270, 0x9A2A, 0xF271, 0x9A2B, 0xF272, 0x9A2C, 0xF273, 0x9A2D,
+ 0xF274, 0x9A2E, 0xF275, 0x9A2F, 0xF276, 0x9A30, 0xF277, 0x9A31, 0xF278, 0x9A32, 0xF279, 0x9A33, 0xF27A, 0x9A34, 0xF27B, 0x9A35,
+ 0xF27C, 0x9A36, 0xF27D, 0x9A37, 0xF27E, 0x9A38, 0xF280, 0x9A39, 0xF281, 0x9A3A, 0xF282, 0x9A3B, 0xF283, 0x9A3C, 0xF284, 0x9A3D,
+ 0xF285, 0x9A3E, 0xF286, 0x9A3F, 0xF287, 0x9A40, 0xF288, 0x9A41, 0xF289, 0x9A42, 0xF28A, 0x9A43, 0xF28B, 0x9A44, 0xF28C, 0x9A45,
+ 0xF28D, 0x9A46, 0xF28E, 0x9A47, 0xF28F, 0x9A48, 0xF290, 0x9A49, 0xF291, 0x9A4A, 0xF292, 0x9A4B, 0xF293, 0x9A4C, 0xF294, 0x9A4D,
+ 0xF295, 0x9A4E, 0xF296, 0x9A4F, 0xF297, 0x9A50, 0xF298, 0x9A51, 0xF299, 0x9A52, 0xF29A, 0x9A53, 0xF29B, 0x9A54, 0xF29C, 0x9A55,
+ 0xF29D, 0x9A56, 0xF29E, 0x9A57, 0xF29F, 0x9A58, 0xF2A0, 0x9A59, 0xF2A1, 0x9889, 0xF2A2, 0x988C, 0xF2A3, 0x988D, 0xF2A4, 0x988F,
+ 0xF2A5, 0x9894, 0xF2A6, 0x989A, 0xF2A7, 0x989B, 0xF2A8, 0x989E, 0xF2A9, 0x989F, 0xF2AA, 0x98A1, 0xF2AB, 0x98A2, 0xF2AC, 0x98A5,
+ 0xF2AD, 0x98A6, 0xF2AE, 0x864D, 0xF2AF, 0x8654, 0xF2B0, 0x866C, 0xF2B1, 0x866E, 0xF2B2, 0x867F, 0xF2B3, 0x867A, 0xF2B4, 0x867C,
+ 0xF2B5, 0x867B, 0xF2B6, 0x86A8, 0xF2B7, 0x868D, 0xF2B8, 0x868B, 0xF2B9, 0x86AC, 0xF2BA, 0x869D, 0xF2BB, 0x86A7, 0xF2BC, 0x86A3,
+ 0xF2BD, 0x86AA, 0xF2BE, 0x8693, 0xF2BF, 0x86A9, 0xF2C0, 0x86B6, 0xF2C1, 0x86C4, 0xF2C2, 0x86B5, 0xF2C3, 0x86CE, 0xF2C4, 0x86B0,
+ 0xF2C5, 0x86BA, 0xF2C6, 0x86B1, 0xF2C7, 0x86AF, 0xF2C8, 0x86C9, 0xF2C9, 0x86CF, 0xF2CA, 0x86B4, 0xF2CB, 0x86E9, 0xF2CC, 0x86F1,
+ 0xF2CD, 0x86F2, 0xF2CE, 0x86ED, 0xF2CF, 0x86F3, 0xF2D0, 0x86D0, 0xF2D1, 0x8713, 0xF2D2, 0x86DE, 0xF2D3, 0x86F4, 0xF2D4, 0x86DF,
+ 0xF2D5, 0x86D8, 0xF2D6, 0x86D1, 0xF2D7, 0x8703, 0xF2D8, 0x8707, 0xF2D9, 0x86F8, 0xF2DA, 0x8708, 0xF2DB, 0x870A, 0xF2DC, 0x870D,
+ 0xF2DD, 0x8709, 0xF2DE, 0x8723, 0xF2DF, 0x873B, 0xF2E0, 0x871E, 0xF2E1, 0x8725, 0xF2E2, 0x872E, 0xF2E3, 0x871A, 0xF2E4, 0x873E,
+ 0xF2E5, 0x8748, 0xF2E6, 0x8734, 0xF2E7, 0x8731, 0xF2E8, 0x8729, 0xF2E9, 0x8737, 0xF2EA, 0x873F, 0xF2EB, 0x8782, 0xF2EC, 0x8722,
+ 0xF2ED, 0x877D, 0xF2EE, 0x877E, 0xF2EF, 0x877B, 0xF2F0, 0x8760, 0xF2F1, 0x8770, 0xF2F2, 0x874C, 0xF2F3, 0x876E, 0xF2F4, 0x878B,
+ 0xF2F5, 0x8753, 0xF2F6, 0x8763, 0xF2F7, 0x877C, 0xF2F8, 0x8764, 0xF2F9, 0x8759, 0xF2FA, 0x8765, 0xF2FB, 0x8793, 0xF2FC, 0x87AF,
+ 0xF2FD, 0x87A8, 0xF2FE, 0x87D2, 0xF340, 0x9A5A, 0xF341, 0x9A5B, 0xF342, 0x9A5C, 0xF343, 0x9A5D, 0xF344, 0x9A5E, 0xF345, 0x9A5F,
+ 0xF346, 0x9A60, 0xF347, 0x9A61, 0xF348, 0x9A62, 0xF349, 0x9A63, 0xF34A, 0x9A64, 0xF34B, 0x9A65, 0xF34C, 0x9A66, 0xF34D, 0x9A67,
+ 0xF34E, 0x9A68, 0xF34F, 0x9A69, 0xF350, 0x9A6A, 0xF351, 0x9A6B, 0xF352, 0x9A72, 0xF353, 0x9A83, 0xF354, 0x9A89, 0xF355, 0x9A8D,
+ 0xF356, 0x9A8E, 0xF357, 0x9A94, 0xF358, 0x9A95, 0xF359, 0x9A99, 0xF35A, 0x9AA6, 0xF35B, 0x9AA9, 0xF35C, 0x9AAA, 0xF35D, 0x9AAB,
+ 0xF35E, 0x9AAC, 0xF35F, 0x9AAD, 0xF360, 0x9AAE, 0xF361, 0x9AAF, 0xF362, 0x9AB2, 0xF363, 0x9AB3, 0xF364, 0x9AB4, 0xF365, 0x9AB5,
+ 0xF366, 0x9AB9, 0xF367, 0x9ABB, 0xF368, 0x9ABD, 0xF369, 0x9ABE, 0xF36A, 0x9ABF, 0xF36B, 0x9AC3, 0xF36C, 0x9AC4, 0xF36D, 0x9AC6,
+ 0xF36E, 0x9AC7, 0xF36F, 0x9AC8, 0xF370, 0x9AC9, 0xF371, 0x9ACA, 0xF372, 0x9ACD, 0xF373, 0x9ACE, 0xF374, 0x9ACF, 0xF375, 0x9AD0,
+ 0xF376, 0x9AD2, 0xF377, 0x9AD4, 0xF378, 0x9AD5, 0xF379, 0x9AD6, 0xF37A, 0x9AD7, 0xF37B, 0x9AD9, 0xF37C, 0x9ADA, 0xF37D, 0x9ADB,
+ 0xF37E, 0x9ADC, 0xF380, 0x9ADD, 0xF381, 0x9ADE, 0xF382, 0x9AE0, 0xF383, 0x9AE2, 0xF384, 0x9AE3, 0xF385, 0x9AE4, 0xF386, 0x9AE5,
+ 0xF387, 0x9AE7, 0xF388, 0x9AE8, 0xF389, 0x9AE9, 0xF38A, 0x9AEA, 0xF38B, 0x9AEC, 0xF38C, 0x9AEE, 0xF38D, 0x9AF0, 0xF38E, 0x9AF1,
+ 0xF38F, 0x9AF2, 0xF390, 0x9AF3, 0xF391, 0x9AF4, 0xF392, 0x9AF5, 0xF393, 0x9AF6, 0xF394, 0x9AF7, 0xF395, 0x9AF8, 0xF396, 0x9AFA,
+ 0xF397, 0x9AFC, 0xF398, 0x9AFD, 0xF399, 0x9AFE, 0xF39A, 0x9AFF, 0xF39B, 0x9B00, 0xF39C, 0x9B01, 0xF39D, 0x9B02, 0xF39E, 0x9B04,
+ 0xF39F, 0x9B05, 0xF3A0, 0x9B06, 0xF3A1, 0x87C6, 0xF3A2, 0x8788, 0xF3A3, 0x8785, 0xF3A4, 0x87AD, 0xF3A5, 0x8797, 0xF3A6, 0x8783,
+ 0xF3A7, 0x87AB, 0xF3A8, 0x87E5, 0xF3A9, 0x87AC, 0xF3AA, 0x87B5, 0xF3AB, 0x87B3, 0xF3AC, 0x87CB, 0xF3AD, 0x87D3, 0xF3AE, 0x87BD,
+ 0xF3AF, 0x87D1, 0xF3B0, 0x87C0, 0xF3B1, 0x87CA, 0xF3B2, 0x87DB, 0xF3B3, 0x87EA, 0xF3B4, 0x87E0, 0xF3B5, 0x87EE, 0xF3B6, 0x8816,
+ 0xF3B7, 0x8813, 0xF3B8, 0x87FE, 0xF3B9, 0x880A, 0xF3BA, 0x881B, 0xF3BB, 0x8821, 0xF3BC, 0x8839, 0xF3BD, 0x883C, 0xF3BE, 0x7F36,
+ 0xF3BF, 0x7F42, 0xF3C0, 0x7F44, 0xF3C1, 0x7F45, 0xF3C2, 0x8210, 0xF3C3, 0x7AFA, 0xF3C4, 0x7AFD, 0xF3C5, 0x7B08, 0xF3C6, 0x7B03,
+ 0xF3C7, 0x7B04, 0xF3C8, 0x7B15, 0xF3C9, 0x7B0A, 0xF3CA, 0x7B2B, 0xF3CB, 0x7B0F, 0xF3CC, 0x7B47, 0xF3CD, 0x7B38, 0xF3CE, 0x7B2A,
+ 0xF3CF, 0x7B19, 0xF3D0, 0x7B2E, 0xF3D1, 0x7B31, 0xF3D2, 0x7B20, 0xF3D3, 0x7B25, 0xF3D4, 0x7B24, 0xF3D5, 0x7B33, 0xF3D6, 0x7B3E,
+ 0xF3D7, 0x7B1E, 0xF3D8, 0x7B58, 0xF3D9, 0x7B5A, 0xF3DA, 0x7B45, 0xF3DB, 0x7B75, 0xF3DC, 0x7B4C, 0xF3DD, 0x7B5D, 0xF3DE, 0x7B60,
+ 0xF3DF, 0x7B6E, 0xF3E0, 0x7B7B, 0xF3E1, 0x7B62, 0xF3E2, 0x7B72, 0xF3E3, 0x7B71, 0xF3E4, 0x7B90, 0xF3E5, 0x7BA6, 0xF3E6, 0x7BA7,
+ 0xF3E7, 0x7BB8, 0xF3E8, 0x7BAC, 0xF3E9, 0x7B9D, 0xF3EA, 0x7BA8, 0xF3EB, 0x7B85, 0xF3EC, 0x7BAA, 0xF3ED, 0x7B9C, 0xF3EE, 0x7BA2,
+ 0xF3EF, 0x7BAB, 0xF3F0, 0x7BB4, 0xF3F1, 0x7BD1, 0xF3F2, 0x7BC1, 0xF3F3, 0x7BCC, 0xF3F4, 0x7BDD, 0xF3F5, 0x7BDA, 0xF3F6, 0x7BE5,
+ 0xF3F7, 0x7BE6, 0xF3F8, 0x7BEA, 0xF3F9, 0x7C0C, 0xF3FA, 0x7BFE, 0xF3FB, 0x7BFC, 0xF3FC, 0x7C0F, 0xF3FD, 0x7C16, 0xF3FE, 0x7C0B,
+ 0xF440, 0x9B07, 0xF441, 0x9B09, 0xF442, 0x9B0A, 0xF443, 0x9B0B, 0xF444, 0x9B0C, 0xF445, 0x9B0D, 0xF446, 0x9B0E, 0xF447, 0x9B10,
+ 0xF448, 0x9B11, 0xF449, 0x9B12, 0xF44A, 0x9B14, 0xF44B, 0x9B15, 0xF44C, 0x9B16, 0xF44D, 0x9B17, 0xF44E, 0x9B18, 0xF44F, 0x9B19,
+ 0xF450, 0x9B1A, 0xF451, 0x9B1B, 0xF452, 0x9B1C, 0xF453, 0x9B1D, 0xF454, 0x9B1E, 0xF455, 0x9B20, 0xF456, 0x9B21, 0xF457, 0x9B22,
+ 0xF458, 0x9B24, 0xF459, 0x9B25, 0xF45A, 0x9B26, 0xF45B, 0x9B27, 0xF45C, 0x9B28, 0xF45D, 0x9B29, 0xF45E, 0x9B2A, 0xF45F, 0x9B2B,
+ 0xF460, 0x9B2C, 0xF461, 0x9B2D, 0xF462, 0x9B2E, 0xF463, 0x9B30, 0xF464, 0x9B31, 0xF465, 0x9B33, 0xF466, 0x9B34, 0xF467, 0x9B35,
+ 0xF468, 0x9B36, 0xF469, 0x9B37, 0xF46A, 0x9B38, 0xF46B, 0x9B39, 0xF46C, 0x9B3A, 0xF46D, 0x9B3D, 0xF46E, 0x9B3E, 0xF46F, 0x9B3F,
+ 0xF470, 0x9B40, 0xF471, 0x9B46, 0xF472, 0x9B4A, 0xF473, 0x9B4B, 0xF474, 0x9B4C, 0xF475, 0x9B4E, 0xF476, 0x9B50, 0xF477, 0x9B52,
+ 0xF478, 0x9B53, 0xF479, 0x9B55, 0xF47A, 0x9B56, 0xF47B, 0x9B57, 0xF47C, 0x9B58, 0xF47D, 0x9B59, 0xF47E, 0x9B5A, 0xF480, 0x9B5B,
+ 0xF481, 0x9B5C, 0xF482, 0x9B5D, 0xF483, 0x9B5E, 0xF484, 0x9B5F, 0xF485, 0x9B60, 0xF486, 0x9B61, 0xF487, 0x9B62, 0xF488, 0x9B63,
+ 0xF489, 0x9B64, 0xF48A, 0x9B65, 0xF48B, 0x9B66, 0xF48C, 0x9B67, 0xF48D, 0x9B68, 0xF48E, 0x9B69, 0xF48F, 0x9B6A, 0xF490, 0x9B6B,
+ 0xF491, 0x9B6C, 0xF492, 0x9B6D, 0xF493, 0x9B6E, 0xF494, 0x9B6F, 0xF495, 0x9B70, 0xF496, 0x9B71, 0xF497, 0x9B72, 0xF498, 0x9B73,
+ 0xF499, 0x9B74, 0xF49A, 0x9B75, 0xF49B, 0x9B76, 0xF49C, 0x9B77, 0xF49D, 0x9B78, 0xF49E, 0x9B79, 0xF49F, 0x9B7A, 0xF4A0, 0x9B7B,
+ 0xF4A1, 0x7C1F, 0xF4A2, 0x7C2A, 0xF4A3, 0x7C26, 0xF4A4, 0x7C38, 0xF4A5, 0x7C41, 0xF4A6, 0x7C40, 0xF4A7, 0x81FE, 0xF4A8, 0x8201,
+ 0xF4A9, 0x8202, 0xF4AA, 0x8204, 0xF4AB, 0x81EC, 0xF4AC, 0x8844, 0xF4AD, 0x8221, 0xF4AE, 0x8222, 0xF4AF, 0x8223, 0xF4B0, 0x822D,
+ 0xF4B1, 0x822F, 0xF4B2, 0x8228, 0xF4B3, 0x822B, 0xF4B4, 0x8238, 0xF4B5, 0x823B, 0xF4B6, 0x8233, 0xF4B7, 0x8234, 0xF4B8, 0x823E,
+ 0xF4B9, 0x8244, 0xF4BA, 0x8249, 0xF4BB, 0x824B, 0xF4BC, 0x824F, 0xF4BD, 0x825A, 0xF4BE, 0x825F, 0xF4BF, 0x8268, 0xF4C0, 0x887E,
+ 0xF4C1, 0x8885, 0xF4C2, 0x8888, 0xF4C3, 0x88D8, 0xF4C4, 0x88DF, 0xF4C5, 0x895E, 0xF4C6, 0x7F9D, 0xF4C7, 0x7F9F, 0xF4C8, 0x7FA7,
+ 0xF4C9, 0x7FAF, 0xF4CA, 0x7FB0, 0xF4CB, 0x7FB2, 0xF4CC, 0x7C7C, 0xF4CD, 0x6549, 0xF4CE, 0x7C91, 0xF4CF, 0x7C9D, 0xF4D0, 0x7C9C,
+ 0xF4D1, 0x7C9E, 0xF4D2, 0x7CA2, 0xF4D3, 0x7CB2, 0xF4D4, 0x7CBC, 0xF4D5, 0x7CBD, 0xF4D6, 0x7CC1, 0xF4D7, 0x7CC7, 0xF4D8, 0x7CCC,
+ 0xF4D9, 0x7CCD, 0xF4DA, 0x7CC8, 0xF4DB, 0x7CC5, 0xF4DC, 0x7CD7, 0xF4DD, 0x7CE8, 0xF4DE, 0x826E, 0xF4DF, 0x66A8, 0xF4E0, 0x7FBF,
+ 0xF4E1, 0x7FCE, 0xF4E2, 0x7FD5, 0xF4E3, 0x7FE5, 0xF4E4, 0x7FE1, 0xF4E5, 0x7FE6, 0xF4E6, 0x7FE9, 0xF4E7, 0x7FEE, 0xF4E8, 0x7FF3,
+ 0xF4E9, 0x7CF8, 0xF4EA, 0x7D77, 0xF4EB, 0x7DA6, 0xF4EC, 0x7DAE, 0xF4ED, 0x7E47, 0xF4EE, 0x7E9B, 0xF4EF, 0x9EB8, 0xF4F0, 0x9EB4,
+ 0xF4F1, 0x8D73, 0xF4F2, 0x8D84, 0xF4F3, 0x8D94, 0xF4F4, 0x8D91, 0xF4F5, 0x8DB1, 0xF4F6, 0x8D67, 0xF4F7, 0x8D6D, 0xF4F8, 0x8C47,
+ 0xF4F9, 0x8C49, 0xF4FA, 0x914A, 0xF4FB, 0x9150, 0xF4FC, 0x914E, 0xF4FD, 0x914F, 0xF4FE, 0x9164, 0xF540, 0x9B7C, 0xF541, 0x9B7D,
+ 0xF542, 0x9B7E, 0xF543, 0x9B7F, 0xF544, 0x9B80, 0xF545, 0x9B81, 0xF546, 0x9B82, 0xF547, 0x9B83, 0xF548, 0x9B84, 0xF549, 0x9B85,
+ 0xF54A, 0x9B86, 0xF54B, 0x9B87, 0xF54C, 0x9B88, 0xF54D, 0x9B89, 0xF54E, 0x9B8A, 0xF54F, 0x9B8B, 0xF550, 0x9B8C, 0xF551, 0x9B8D,
+ 0xF552, 0x9B8E, 0xF553, 0x9B8F, 0xF554, 0x9B90, 0xF555, 0x9B91, 0xF556, 0x9B92, 0xF557, 0x9B93, 0xF558, 0x9B94, 0xF559, 0x9B95,
+ 0xF55A, 0x9B96, 0xF55B, 0x9B97, 0xF55C, 0x9B98, 0xF55D, 0x9B99, 0xF55E, 0x9B9A, 0xF55F, 0x9B9B, 0xF560, 0x9B9C, 0xF561, 0x9B9D,
+ 0xF562, 0x9B9E, 0xF563, 0x9B9F, 0xF564, 0x9BA0, 0xF565, 0x9BA1, 0xF566, 0x9BA2, 0xF567, 0x9BA3, 0xF568, 0x9BA4, 0xF569, 0x9BA5,
+ 0xF56A, 0x9BA6, 0xF56B, 0x9BA7, 0xF56C, 0x9BA8, 0xF56D, 0x9BA9, 0xF56E, 0x9BAA, 0xF56F, 0x9BAB, 0xF570, 0x9BAC, 0xF571, 0x9BAD,
+ 0xF572, 0x9BAE, 0xF573, 0x9BAF, 0xF574, 0x9BB0, 0xF575, 0x9BB1, 0xF576, 0x9BB2, 0xF577, 0x9BB3, 0xF578, 0x9BB4, 0xF579, 0x9BB5,
+ 0xF57A, 0x9BB6, 0xF57B, 0x9BB7, 0xF57C, 0x9BB8, 0xF57D, 0x9BB9, 0xF57E, 0x9BBA, 0xF580, 0x9BBB, 0xF581, 0x9BBC, 0xF582, 0x9BBD,
+ 0xF583, 0x9BBE, 0xF584, 0x9BBF, 0xF585, 0x9BC0, 0xF586, 0x9BC1, 0xF587, 0x9BC2, 0xF588, 0x9BC3, 0xF589, 0x9BC4, 0xF58A, 0x9BC5,
+ 0xF58B, 0x9BC6, 0xF58C, 0x9BC7, 0xF58D, 0x9BC8, 0xF58E, 0x9BC9, 0xF58F, 0x9BCA, 0xF590, 0x9BCB, 0xF591, 0x9BCC, 0xF592, 0x9BCD,
+ 0xF593, 0x9BCE, 0xF594, 0x9BCF, 0xF595, 0x9BD0, 0xF596, 0x9BD1, 0xF597, 0x9BD2, 0xF598, 0x9BD3, 0xF599, 0x9BD4, 0xF59A, 0x9BD5,
+ 0xF59B, 0x9BD6, 0xF59C, 0x9BD7, 0xF59D, 0x9BD8, 0xF59E, 0x9BD9, 0xF59F, 0x9BDA, 0xF5A0, 0x9BDB, 0xF5A1, 0x9162, 0xF5A2, 0x9161,
+ 0xF5A3, 0x9170, 0xF5A4, 0x9169, 0xF5A5, 0x916F, 0xF5A6, 0x917D, 0xF5A7, 0x917E, 0xF5A8, 0x9172, 0xF5A9, 0x9174, 0xF5AA, 0x9179,
+ 0xF5AB, 0x918C, 0xF5AC, 0x9185, 0xF5AD, 0x9190, 0xF5AE, 0x918D, 0xF5AF, 0x9191, 0xF5B0, 0x91A2, 0xF5B1, 0x91A3, 0xF5B2, 0x91AA,
+ 0xF5B3, 0x91AD, 0xF5B4, 0x91AE, 0xF5B5, 0x91AF, 0xF5B6, 0x91B5, 0xF5B7, 0x91B4, 0xF5B8, 0x91BA, 0xF5B9, 0x8C55, 0xF5BA, 0x9E7E,
+ 0xF5BB, 0x8DB8, 0xF5BC, 0x8DEB, 0xF5BD, 0x8E05, 0xF5BE, 0x8E59, 0xF5BF, 0x8E69, 0xF5C0, 0x8DB5, 0xF5C1, 0x8DBF, 0xF5C2, 0x8DBC,
+ 0xF5C3, 0x8DBA, 0xF5C4, 0x8DC4, 0xF5C5, 0x8DD6, 0xF5C6, 0x8DD7, 0xF5C7, 0x8DDA, 0xF5C8, 0x8DDE, 0xF5C9, 0x8DCE, 0xF5CA, 0x8DCF,
+ 0xF5CB, 0x8DDB, 0xF5CC, 0x8DC6, 0xF5CD, 0x8DEC, 0xF5CE, 0x8DF7, 0xF5CF, 0x8DF8, 0xF5D0, 0x8DE3, 0xF5D1, 0x8DF9, 0xF5D2, 0x8DFB,
+ 0xF5D3, 0x8DE4, 0xF5D4, 0x8E09, 0xF5D5, 0x8DFD, 0xF5D6, 0x8E14, 0xF5D7, 0x8E1D, 0xF5D8, 0x8E1F, 0xF5D9, 0x8E2C, 0xF5DA, 0x8E2E,
+ 0xF5DB, 0x8E23, 0xF5DC, 0x8E2F, 0xF5DD, 0x8E3A, 0xF5DE, 0x8E40, 0xF5DF, 0x8E39, 0xF5E0, 0x8E35, 0xF5E1, 0x8E3D, 0xF5E2, 0x8E31,
+ 0xF5E3, 0x8E49, 0xF5E4, 0x8E41, 0xF5E5, 0x8E42, 0xF5E6, 0x8E51, 0xF5E7, 0x8E52, 0xF5E8, 0x8E4A, 0xF5E9, 0x8E70, 0xF5EA, 0x8E76,
+ 0xF5EB, 0x8E7C, 0xF5EC, 0x8E6F, 0xF5ED, 0x8E74, 0xF5EE, 0x8E85, 0xF5EF, 0x8E8F, 0xF5F0, 0x8E94, 0xF5F1, 0x8E90, 0xF5F2, 0x8E9C,
+ 0xF5F3, 0x8E9E, 0xF5F4, 0x8C78, 0xF5F5, 0x8C82, 0xF5F6, 0x8C8A, 0xF5F7, 0x8C85, 0xF5F8, 0x8C98, 0xF5F9, 0x8C94, 0xF5FA, 0x659B,
+ 0xF5FB, 0x89D6, 0xF5FC, 0x89DE, 0xF5FD, 0x89DA, 0xF5FE, 0x89DC, 0xF640, 0x9BDC, 0xF641, 0x9BDD, 0xF642, 0x9BDE, 0xF643, 0x9BDF,
+ 0xF644, 0x9BE0, 0xF645, 0x9BE1, 0xF646, 0x9BE2, 0xF647, 0x9BE3, 0xF648, 0x9BE4, 0xF649, 0x9BE5, 0xF64A, 0x9BE6, 0xF64B, 0x9BE7,
+ 0xF64C, 0x9BE8, 0xF64D, 0x9BE9, 0xF64E, 0x9BEA, 0xF64F, 0x9BEB, 0xF650, 0x9BEC, 0xF651, 0x9BED, 0xF652, 0x9BEE, 0xF653, 0x9BEF,
+ 0xF654, 0x9BF0, 0xF655, 0x9BF1, 0xF656, 0x9BF2, 0xF657, 0x9BF3, 0xF658, 0x9BF4, 0xF659, 0x9BF5, 0xF65A, 0x9BF6, 0xF65B, 0x9BF7,
+ 0xF65C, 0x9BF8, 0xF65D, 0x9BF9, 0xF65E, 0x9BFA, 0xF65F, 0x9BFB, 0xF660, 0x9BFC, 0xF661, 0x9BFD, 0xF662, 0x9BFE, 0xF663, 0x9BFF,
+ 0xF664, 0x9C00, 0xF665, 0x9C01, 0xF666, 0x9C02, 0xF667, 0x9C03, 0xF668, 0x9C04, 0xF669, 0x9C05, 0xF66A, 0x9C06, 0xF66B, 0x9C07,
+ 0xF66C, 0x9C08, 0xF66D, 0x9C09, 0xF66E, 0x9C0A, 0xF66F, 0x9C0B, 0xF670, 0x9C0C, 0xF671, 0x9C0D, 0xF672, 0x9C0E, 0xF673, 0x9C0F,
+ 0xF674, 0x9C10, 0xF675, 0x9C11, 0xF676, 0x9C12, 0xF677, 0x9C13, 0xF678, 0x9C14, 0xF679, 0x9C15, 0xF67A, 0x9C16, 0xF67B, 0x9C17,
+ 0xF67C, 0x9C18, 0xF67D, 0x9C19, 0xF67E, 0x9C1A, 0xF680, 0x9C1B, 0xF681, 0x9C1C, 0xF682, 0x9C1D, 0xF683, 0x9C1E, 0xF684, 0x9C1F,
+ 0xF685, 0x9C20, 0xF686, 0x9C21, 0xF687, 0x9C22, 0xF688, 0x9C23, 0xF689, 0x9C24, 0xF68A, 0x9C25, 0xF68B, 0x9C26, 0xF68C, 0x9C27,
+ 0xF68D, 0x9C28, 0xF68E, 0x9C29, 0xF68F, 0x9C2A, 0xF690, 0x9C2B, 0xF691, 0x9C2C, 0xF692, 0x9C2D, 0xF693, 0x9C2E, 0xF694, 0x9C2F,
+ 0xF695, 0x9C30, 0xF696, 0x9C31, 0xF697, 0x9C32, 0xF698, 0x9C33, 0xF699, 0x9C34, 0xF69A, 0x9C35, 0xF69B, 0x9C36, 0xF69C, 0x9C37,
+ 0xF69D, 0x9C38, 0xF69E, 0x9C39, 0xF69F, 0x9C3A, 0xF6A0, 0x9C3B, 0xF6A1, 0x89E5, 0xF6A2, 0x89EB, 0xF6A3, 0x89EF, 0xF6A4, 0x8A3E,
+ 0xF6A5, 0x8B26, 0xF6A6, 0x9753, 0xF6A7, 0x96E9, 0xF6A8, 0x96F3, 0xF6A9, 0x96EF, 0xF6AA, 0x9706, 0xF6AB, 0x9701, 0xF6AC, 0x9708,
+ 0xF6AD, 0x970F, 0xF6AE, 0x970E, 0xF6AF, 0x972A, 0xF6B0, 0x972D, 0xF6B1, 0x9730, 0xF6B2, 0x973E, 0xF6B3, 0x9F80, 0xF6B4, 0x9F83,
+ 0xF6B5, 0x9F85, 0xF6B6, 0x9F86, 0xF6B7, 0x9F87, 0xF6B8, 0x9F88, 0xF6B9, 0x9F89, 0xF6BA, 0x9F8A, 0xF6BB, 0x9F8C, 0xF6BC, 0x9EFE,
+ 0xF6BD, 0x9F0B, 0xF6BE, 0x9F0D, 0xF6BF, 0x96B9, 0xF6C0, 0x96BC, 0xF6C1, 0x96BD, 0xF6C2, 0x96CE, 0xF6C3, 0x96D2, 0xF6C4, 0x77BF,
+ 0xF6C5, 0x96E0, 0xF6C6, 0x928E, 0xF6C7, 0x92AE, 0xF6C8, 0x92C8, 0xF6C9, 0x933E, 0xF6CA, 0x936A, 0xF6CB, 0x93CA, 0xF6CC, 0x938F,
+ 0xF6CD, 0x943E, 0xF6CE, 0x946B, 0xF6CF, 0x9C7F, 0xF6D0, 0x9C82, 0xF6D1, 0x9C85, 0xF6D2, 0x9C86, 0xF6D3, 0x9C87, 0xF6D4, 0x9C88,
+ 0xF6D5, 0x7A23, 0xF6D6, 0x9C8B, 0xF6D7, 0x9C8E, 0xF6D8, 0x9C90, 0xF6D9, 0x9C91, 0xF6DA, 0x9C92, 0xF6DB, 0x9C94, 0xF6DC, 0x9C95,
+ 0xF6DD, 0x9C9A, 0xF6DE, 0x9C9B, 0xF6DF, 0x9C9E, 0xF6E0, 0x9C9F, 0xF6E1, 0x9CA0, 0xF6E2, 0x9CA1, 0xF6E3, 0x9CA2, 0xF6E4, 0x9CA3,
+ 0xF6E5, 0x9CA5, 0xF6E6, 0x9CA6, 0xF6E7, 0x9CA7, 0xF6E8, 0x9CA8, 0xF6E9, 0x9CA9, 0xF6EA, 0x9CAB, 0xF6EB, 0x9CAD, 0xF6EC, 0x9CAE,
+ 0xF6ED, 0x9CB0, 0xF6EE, 0x9CB1, 0xF6EF, 0x9CB2, 0xF6F0, 0x9CB3, 0xF6F1, 0x9CB4, 0xF6F2, 0x9CB5, 0xF6F3, 0x9CB6, 0xF6F4, 0x9CB7,
+ 0xF6F5, 0x9CBA, 0xF6F6, 0x9CBB, 0xF6F7, 0x9CBC, 0xF6F8, 0x9CBD, 0xF6F9, 0x9CC4, 0xF6FA, 0x9CC5, 0xF6FB, 0x9CC6, 0xF6FC, 0x9CC7,
+ 0xF6FD, 0x9CCA, 0xF6FE, 0x9CCB, 0xF740, 0x9C3C, 0xF741, 0x9C3D, 0xF742, 0x9C3E, 0xF743, 0x9C3F, 0xF744, 0x9C40, 0xF745, 0x9C41,
+ 0xF746, 0x9C42, 0xF747, 0x9C43, 0xF748, 0x9C44, 0xF749, 0x9C45, 0xF74A, 0x9C46, 0xF74B, 0x9C47, 0xF74C, 0x9C48, 0xF74D, 0x9C49,
+ 0xF74E, 0x9C4A, 0xF74F, 0x9C4B, 0xF750, 0x9C4C, 0xF751, 0x9C4D, 0xF752, 0x9C4E, 0xF753, 0x9C4F, 0xF754, 0x9C50, 0xF755, 0x9C51,
+ 0xF756, 0x9C52, 0xF757, 0x9C53, 0xF758, 0x9C54, 0xF759, 0x9C55, 0xF75A, 0x9C56, 0xF75B, 0x9C57, 0xF75C, 0x9C58, 0xF75D, 0x9C59,
+ 0xF75E, 0x9C5A, 0xF75F, 0x9C5B, 0xF760, 0x9C5C, 0xF761, 0x9C5D, 0xF762, 0x9C5E, 0xF763, 0x9C5F, 0xF764, 0x9C60, 0xF765, 0x9C61,
+ 0xF766, 0x9C62, 0xF767, 0x9C63, 0xF768, 0x9C64, 0xF769, 0x9C65, 0xF76A, 0x9C66, 0xF76B, 0x9C67, 0xF76C, 0x9C68, 0xF76D, 0x9C69,
+ 0xF76E, 0x9C6A, 0xF76F, 0x9C6B, 0xF770, 0x9C6C, 0xF771, 0x9C6D, 0xF772, 0x9C6E, 0xF773, 0x9C6F, 0xF774, 0x9C70, 0xF775, 0x9C71,
+ 0xF776, 0x9C72, 0xF777, 0x9C73, 0xF778, 0x9C74, 0xF779, 0x9C75, 0xF77A, 0x9C76, 0xF77B, 0x9C77, 0xF77C, 0x9C78, 0xF77D, 0x9C79,
+ 0xF77E, 0x9C7A, 0xF780, 0x9C7B, 0xF781, 0x9C7D, 0xF782, 0x9C7E, 0xF783, 0x9C80, 0xF784, 0x9C83, 0xF785, 0x9C84, 0xF786, 0x9C89,
+ 0xF787, 0x9C8A, 0xF788, 0x9C8C, 0xF789, 0x9C8F, 0xF78A, 0x9C93, 0xF78B, 0x9C96, 0xF78C, 0x9C97, 0xF78D, 0x9C98, 0xF78E, 0x9C99,
+ 0xF78F, 0x9C9D, 0xF790, 0x9CAA, 0xF791, 0x9CAC, 0xF792, 0x9CAF, 0xF793, 0x9CB9, 0xF794, 0x9CBE, 0xF795, 0x9CBF, 0xF796, 0x9CC0,
+ 0xF797, 0x9CC1, 0xF798, 0x9CC2, 0xF799, 0x9CC8, 0xF79A, 0x9CC9, 0xF79B, 0x9CD1, 0xF79C, 0x9CD2, 0xF79D, 0x9CDA, 0xF79E, 0x9CDB,
+ 0xF79F, 0x9CE0, 0xF7A0, 0x9CE1, 0xF7A1, 0x9CCC, 0xF7A2, 0x9CCD, 0xF7A3, 0x9CCE, 0xF7A4, 0x9CCF, 0xF7A5, 0x9CD0, 0xF7A6, 0x9CD3,
+ 0xF7A7, 0x9CD4, 0xF7A8, 0x9CD5, 0xF7A9, 0x9CD7, 0xF7AA, 0x9CD8, 0xF7AB, 0x9CD9, 0xF7AC, 0x9CDC, 0xF7AD, 0x9CDD, 0xF7AE, 0x9CDF,
+ 0xF7AF, 0x9CE2, 0xF7B0, 0x977C, 0xF7B1, 0x9785, 0xF7B2, 0x9791, 0xF7B3, 0x9792, 0xF7B4, 0x9794, 0xF7B5, 0x97AF, 0xF7B6, 0x97AB,
+ 0xF7B7, 0x97A3, 0xF7B8, 0x97B2, 0xF7B9, 0x97B4, 0xF7BA, 0x9AB1, 0xF7BB, 0x9AB0, 0xF7BC, 0x9AB7, 0xF7BD, 0x9E58, 0xF7BE, 0x9AB6,
+ 0xF7BF, 0x9ABA, 0xF7C0, 0x9ABC, 0xF7C1, 0x9AC1, 0xF7C2, 0x9AC0, 0xF7C3, 0x9AC5, 0xF7C4, 0x9AC2, 0xF7C5, 0x9ACB, 0xF7C6, 0x9ACC,
+ 0xF7C7, 0x9AD1, 0xF7C8, 0x9B45, 0xF7C9, 0x9B43, 0xF7CA, 0x9B47, 0xF7CB, 0x9B49, 0xF7CC, 0x9B48, 0xF7CD, 0x9B4D, 0xF7CE, 0x9B51,
+ 0xF7CF, 0x98E8, 0xF7D0, 0x990D, 0xF7D1, 0x992E, 0xF7D2, 0x9955, 0xF7D3, 0x9954, 0xF7D4, 0x9ADF, 0xF7D5, 0x9AE1, 0xF7D6, 0x9AE6,
+ 0xF7D7, 0x9AEF, 0xF7D8, 0x9AEB, 0xF7D9, 0x9AFB, 0xF7DA, 0x9AED, 0xF7DB, 0x9AF9, 0xF7DC, 0x9B08, 0xF7DD, 0x9B0F, 0xF7DE, 0x9B13,
+ 0xF7DF, 0x9B1F, 0xF7E0, 0x9B23, 0xF7E1, 0x9EBD, 0xF7E2, 0x9EBE, 0xF7E3, 0x7E3B, 0xF7E4, 0x9E82, 0xF7E5, 0x9E87, 0xF7E6, 0x9E88,
+ 0xF7E7, 0x9E8B, 0xF7E8, 0x9E92, 0xF7E9, 0x93D6, 0xF7EA, 0x9E9D, 0xF7EB, 0x9E9F, 0xF7EC, 0x9EDB, 0xF7ED, 0x9EDC, 0xF7EE, 0x9EDD,
+ 0xF7EF, 0x9EE0, 0xF7F0, 0x9EDF, 0xF7F1, 0x9EE2, 0xF7F2, 0x9EE9, 0xF7F3, 0x9EE7, 0xF7F4, 0x9EE5, 0xF7F5, 0x9EEA, 0xF7F6, 0x9EEF,
+ 0xF7F7, 0x9F22, 0xF7F8, 0x9F2C, 0xF7F9, 0x9F2F, 0xF7FA, 0x9F39, 0xF7FB, 0x9F37, 0xF7FC, 0x9F3D, 0xF7FD, 0x9F3E, 0xF7FE, 0x9F44,
+ 0xF840, 0x9CE3, 0xF841, 0x9CE4, 0xF842, 0x9CE5, 0xF843, 0x9CE6, 0xF844, 0x9CE7, 0xF845, 0x9CE8, 0xF846, 0x9CE9, 0xF847, 0x9CEA,
+ 0xF848, 0x9CEB, 0xF849, 0x9CEC, 0xF84A, 0x9CED, 0xF84B, 0x9CEE, 0xF84C, 0x9CEF, 0xF84D, 0x9CF0, 0xF84E, 0x9CF1, 0xF84F, 0x9CF2,
+ 0xF850, 0x9CF3, 0xF851, 0x9CF4, 0xF852, 0x9CF5, 0xF853, 0x9CF6, 0xF854, 0x9CF7, 0xF855, 0x9CF8, 0xF856, 0x9CF9, 0xF857, 0x9CFA,
+ 0xF858, 0x9CFB, 0xF859, 0x9CFC, 0xF85A, 0x9CFD, 0xF85B, 0x9CFE, 0xF85C, 0x9CFF, 0xF85D, 0x9D00, 0xF85E, 0x9D01, 0xF85F, 0x9D02,
+ 0xF860, 0x9D03, 0xF861, 0x9D04, 0xF862, 0x9D05, 0xF863, 0x9D06, 0xF864, 0x9D07, 0xF865, 0x9D08, 0xF866, 0x9D09, 0xF867, 0x9D0A,
+ 0xF868, 0x9D0B, 0xF869, 0x9D0C, 0xF86A, 0x9D0D, 0xF86B, 0x9D0E, 0xF86C, 0x9D0F, 0xF86D, 0x9D10, 0xF86E, 0x9D11, 0xF86F, 0x9D12,
+ 0xF870, 0x9D13, 0xF871, 0x9D14, 0xF872, 0x9D15, 0xF873, 0x9D16, 0xF874, 0x9D17, 0xF875, 0x9D18, 0xF876, 0x9D19, 0xF877, 0x9D1A,
+ 0xF878, 0x9D1B, 0xF879, 0x9D1C, 0xF87A, 0x9D1D, 0xF87B, 0x9D1E, 0xF87C, 0x9D1F, 0xF87D, 0x9D20, 0xF87E, 0x9D21, 0xF880, 0x9D22,
+ 0xF881, 0x9D23, 0xF882, 0x9D24, 0xF883, 0x9D25, 0xF884, 0x9D26, 0xF885, 0x9D27, 0xF886, 0x9D28, 0xF887, 0x9D29, 0xF888, 0x9D2A,
+ 0xF889, 0x9D2B, 0xF88A, 0x9D2C, 0xF88B, 0x9D2D, 0xF88C, 0x9D2E, 0xF88D, 0x9D2F, 0xF88E, 0x9D30, 0xF88F, 0x9D31, 0xF890, 0x9D32,
+ 0xF891, 0x9D33, 0xF892, 0x9D34, 0xF893, 0x9D35, 0xF894, 0x9D36, 0xF895, 0x9D37, 0xF896, 0x9D38, 0xF897, 0x9D39, 0xF898, 0x9D3A,
+ 0xF899, 0x9D3B, 0xF89A, 0x9D3C, 0xF89B, 0x9D3D, 0xF89C, 0x9D3E, 0xF89D, 0x9D3F, 0xF89E, 0x9D40, 0xF89F, 0x9D41, 0xF8A0, 0x9D42,
+ 0xF940, 0x9D43, 0xF941, 0x9D44, 0xF942, 0x9D45, 0xF943, 0x9D46, 0xF944, 0x9D47, 0xF945, 0x9D48, 0xF946, 0x9D49, 0xF947, 0x9D4A,
+ 0xF948, 0x9D4B, 0xF949, 0x9D4C, 0xF94A, 0x9D4D, 0xF94B, 0x9D4E, 0xF94C, 0x9D4F, 0xF94D, 0x9D50, 0xF94E, 0x9D51, 0xF94F, 0x9D52,
+ 0xF950, 0x9D53, 0xF951, 0x9D54, 0xF952, 0x9D55, 0xF953, 0x9D56, 0xF954, 0x9D57, 0xF955, 0x9D58, 0xF956, 0x9D59, 0xF957, 0x9D5A,
+ 0xF958, 0x9D5B, 0xF959, 0x9D5C, 0xF95A, 0x9D5D, 0xF95B, 0x9D5E, 0xF95C, 0x9D5F, 0xF95D, 0x9D60, 0xF95E, 0x9D61, 0xF95F, 0x9D62,
+ 0xF960, 0x9D63, 0xF961, 0x9D64, 0xF962, 0x9D65, 0xF963, 0x9D66, 0xF964, 0x9D67, 0xF965, 0x9D68, 0xF966, 0x9D69, 0xF967, 0x9D6A,
+ 0xF968, 0x9D6B, 0xF969, 0x9D6C, 0xF96A, 0x9D6D, 0xF96B, 0x9D6E, 0xF96C, 0x9D6F, 0xF96D, 0x9D70, 0xF96E, 0x9D71, 0xF96F, 0x9D72,
+ 0xF970, 0x9D73, 0xF971, 0x9D74, 0xF972, 0x9D75, 0xF973, 0x9D76, 0xF974, 0x9D77, 0xF975, 0x9D78, 0xF976, 0x9D79, 0xF977, 0x9D7A,
+ 0xF978, 0x9D7B, 0xF979, 0x9D7C, 0xF97A, 0x9D7D, 0xF97B, 0x9D7E, 0xF97C, 0x9D7F, 0xF97D, 0x9D80, 0xF97E, 0x9D81, 0xF980, 0x9D82,
+ 0xF981, 0x9D83, 0xF982, 0x9D84, 0xF983, 0x9D85, 0xF984, 0x9D86, 0xF985, 0x9D87, 0xF986, 0x9D88, 0xF987, 0x9D89, 0xF988, 0x9D8A,
+ 0xF989, 0x9D8B, 0xF98A, 0x9D8C, 0xF98B, 0x9D8D, 0xF98C, 0x9D8E, 0xF98D, 0x9D8F, 0xF98E, 0x9D90, 0xF98F, 0x9D91, 0xF990, 0x9D92,
+ 0xF991, 0x9D93, 0xF992, 0x9D94, 0xF993, 0x9D95, 0xF994, 0x9D96, 0xF995, 0x9D97, 0xF996, 0x9D98, 0xF997, 0x9D99, 0xF998, 0x9D9A,
+ 0xF999, 0x9D9B, 0xF99A, 0x9D9C, 0xF99B, 0x9D9D, 0xF99C, 0x9D9E, 0xF99D, 0x9D9F, 0xF99E, 0x9DA0, 0xF99F, 0x9DA1, 0xF9A0, 0x9DA2,
+ 0xFA40, 0x9DA3, 0xFA41, 0x9DA4, 0xFA42, 0x9DA5, 0xFA43, 0x9DA6, 0xFA44, 0x9DA7, 0xFA45, 0x9DA8, 0xFA46, 0x9DA9, 0xFA47, 0x9DAA,
+ 0xFA48, 0x9DAB, 0xFA49, 0x9DAC, 0xFA4A, 0x9DAD, 0xFA4B, 0x9DAE, 0xFA4C, 0x9DAF, 0xFA4D, 0x9DB0, 0xFA4E, 0x9DB1, 0xFA4F, 0x9DB2,
+ 0xFA50, 0x9DB3, 0xFA51, 0x9DB4, 0xFA52, 0x9DB5, 0xFA53, 0x9DB6, 0xFA54, 0x9DB7, 0xFA55, 0x9DB8, 0xFA56, 0x9DB9, 0xFA57, 0x9DBA,
+ 0xFA58, 0x9DBB, 0xFA59, 0x9DBC, 0xFA5A, 0x9DBD, 0xFA5B, 0x9DBE, 0xFA5C, 0x9DBF, 0xFA5D, 0x9DC0, 0xFA5E, 0x9DC1, 0xFA5F, 0x9DC2,
+ 0xFA60, 0x9DC3, 0xFA61, 0x9DC4, 0xFA62, 0x9DC5, 0xFA63, 0x9DC6, 0xFA64, 0x9DC7, 0xFA65, 0x9DC8, 0xFA66, 0x9DC9, 0xFA67, 0x9DCA,
+ 0xFA68, 0x9DCB, 0xFA69, 0x9DCC, 0xFA6A, 0x9DCD, 0xFA6B, 0x9DCE, 0xFA6C, 0x9DCF, 0xFA6D, 0x9DD0, 0xFA6E, 0x9DD1, 0xFA6F, 0x9DD2,
+ 0xFA70, 0x9DD3, 0xFA71, 0x9DD4, 0xFA72, 0x9DD5, 0xFA73, 0x9DD6, 0xFA74, 0x9DD7, 0xFA75, 0x9DD8, 0xFA76, 0x9DD9, 0xFA77, 0x9DDA,
+ 0xFA78, 0x9DDB, 0xFA79, 0x9DDC, 0xFA7A, 0x9DDD, 0xFA7B, 0x9DDE, 0xFA7C, 0x9DDF, 0xFA7D, 0x9DE0, 0xFA7E, 0x9DE1, 0xFA80, 0x9DE2,
+ 0xFA81, 0x9DE3, 0xFA82, 0x9DE4, 0xFA83, 0x9DE5, 0xFA84, 0x9DE6, 0xFA85, 0x9DE7, 0xFA86, 0x9DE8, 0xFA87, 0x9DE9, 0xFA88, 0x9DEA,
+ 0xFA89, 0x9DEB, 0xFA8A, 0x9DEC, 0xFA8B, 0x9DED, 0xFA8C, 0x9DEE, 0xFA8D, 0x9DEF, 0xFA8E, 0x9DF0, 0xFA8F, 0x9DF1, 0xFA90, 0x9DF2,
+ 0xFA91, 0x9DF3, 0xFA92, 0x9DF4, 0xFA93, 0x9DF5, 0xFA94, 0x9DF6, 0xFA95, 0x9DF7, 0xFA96, 0x9DF8, 0xFA97, 0x9DF9, 0xFA98, 0x9DFA,
+ 0xFA99, 0x9DFB, 0xFA9A, 0x9DFC, 0xFA9B, 0x9DFD, 0xFA9C, 0x9DFE, 0xFA9D, 0x9DFF, 0xFA9E, 0x9E00, 0xFA9F, 0x9E01, 0xFAA0, 0x9E02,
+ 0xFB40, 0x9E03, 0xFB41, 0x9E04, 0xFB42, 0x9E05, 0xFB43, 0x9E06, 0xFB44, 0x9E07, 0xFB45, 0x9E08, 0xFB46, 0x9E09, 0xFB47, 0x9E0A,
+ 0xFB48, 0x9E0B, 0xFB49, 0x9E0C, 0xFB4A, 0x9E0D, 0xFB4B, 0x9E0E, 0xFB4C, 0x9E0F, 0xFB4D, 0x9E10, 0xFB4E, 0x9E11, 0xFB4F, 0x9E12,
+ 0xFB50, 0x9E13, 0xFB51, 0x9E14, 0xFB52, 0x9E15, 0xFB53, 0x9E16, 0xFB54, 0x9E17, 0xFB55, 0x9E18, 0xFB56, 0x9E19, 0xFB57, 0x9E1A,
+ 0xFB58, 0x9E1B, 0xFB59, 0x9E1C, 0xFB5A, 0x9E1D, 0xFB5B, 0x9E1E, 0xFB5C, 0x9E24, 0xFB5D, 0x9E27, 0xFB5E, 0x9E2E, 0xFB5F, 0x9E30,
+ 0xFB60, 0x9E34, 0xFB61, 0x9E3B, 0xFB62, 0x9E3C, 0xFB63, 0x9E40, 0xFB64, 0x9E4D, 0xFB65, 0x9E50, 0xFB66, 0x9E52, 0xFB67, 0x9E53,
+ 0xFB68, 0x9E54, 0xFB69, 0x9E56, 0xFB6A, 0x9E59, 0xFB6B, 0x9E5D, 0xFB6C, 0x9E5F, 0xFB6D, 0x9E60, 0xFB6E, 0x9E61, 0xFB6F, 0x9E62,
+ 0xFB70, 0x9E65, 0xFB71, 0x9E6E, 0xFB72, 0x9E6F, 0xFB73, 0x9E72, 0xFB74, 0x9E74, 0xFB75, 0x9E75, 0xFB76, 0x9E76, 0xFB77, 0x9E77,
+ 0xFB78, 0x9E78, 0xFB79, 0x9E79, 0xFB7A, 0x9E7A, 0xFB7B, 0x9E7B, 0xFB7C, 0x9E7C, 0xFB7D, 0x9E7D, 0xFB7E, 0x9E80, 0xFB80, 0x9E81,
+ 0xFB81, 0x9E83, 0xFB82, 0x9E84, 0xFB83, 0x9E85, 0xFB84, 0x9E86, 0xFB85, 0x9E89, 0xFB86, 0x9E8A, 0xFB87, 0x9E8C, 0xFB88, 0x9E8D,
+ 0xFB89, 0x9E8E, 0xFB8A, 0x9E8F, 0xFB8B, 0x9E90, 0xFB8C, 0x9E91, 0xFB8D, 0x9E94, 0xFB8E, 0x9E95, 0xFB8F, 0x9E96, 0xFB90, 0x9E97,
+ 0xFB91, 0x9E98, 0xFB92, 0x9E99, 0xFB93, 0x9E9A, 0xFB94, 0x9E9B, 0xFB95, 0x9E9C, 0xFB96, 0x9E9E, 0xFB97, 0x9EA0, 0xFB98, 0x9EA1,
+ 0xFB99, 0x9EA2, 0xFB9A, 0x9EA3, 0xFB9B, 0x9EA4, 0xFB9C, 0x9EA5, 0xFB9D, 0x9EA7, 0xFB9E, 0x9EA8, 0xFB9F, 0x9EA9, 0xFBA0, 0x9EAA,
+ 0xFC40, 0x9EAB, 0xFC41, 0x9EAC, 0xFC42, 0x9EAD, 0xFC43, 0x9EAE, 0xFC44, 0x9EAF, 0xFC45, 0x9EB0, 0xFC46, 0x9EB1, 0xFC47, 0x9EB2,
+ 0xFC48, 0x9EB3, 0xFC49, 0x9EB5, 0xFC4A, 0x9EB6, 0xFC4B, 0x9EB7, 0xFC4C, 0x9EB9, 0xFC4D, 0x9EBA, 0xFC4E, 0x9EBC, 0xFC4F, 0x9EBF,
+ 0xFC50, 0x9EC0, 0xFC51, 0x9EC1, 0xFC52, 0x9EC2, 0xFC53, 0x9EC3, 0xFC54, 0x9EC5, 0xFC55, 0x9EC6, 0xFC56, 0x9EC7, 0xFC57, 0x9EC8,
+ 0xFC58, 0x9ECA, 0xFC59, 0x9ECB, 0xFC5A, 0x9ECC, 0xFC5B, 0x9ED0, 0xFC5C, 0x9ED2, 0xFC5D, 0x9ED3, 0xFC5E, 0x9ED5, 0xFC5F, 0x9ED6,
+ 0xFC60, 0x9ED7, 0xFC61, 0x9ED9, 0xFC62, 0x9EDA, 0xFC63, 0x9EDE, 0xFC64, 0x9EE1, 0xFC65, 0x9EE3, 0xFC66, 0x9EE4, 0xFC67, 0x9EE6,
+ 0xFC68, 0x9EE8, 0xFC69, 0x9EEB, 0xFC6A, 0x9EEC, 0xFC6B, 0x9EED, 0xFC6C, 0x9EEE, 0xFC6D, 0x9EF0, 0xFC6E, 0x9EF1, 0xFC6F, 0x9EF2,
+ 0xFC70, 0x9EF3, 0xFC71, 0x9EF4, 0xFC72, 0x9EF5, 0xFC73, 0x9EF6, 0xFC74, 0x9EF7, 0xFC75, 0x9EF8, 0xFC76, 0x9EFA, 0xFC77, 0x9EFD,
+ 0xFC78, 0x9EFF, 0xFC79, 0x9F00, 0xFC7A, 0x9F01, 0xFC7B, 0x9F02, 0xFC7C, 0x9F03, 0xFC7D, 0x9F04, 0xFC7E, 0x9F05, 0xFC80, 0x9F06,
+ 0xFC81, 0x9F07, 0xFC82, 0x9F08, 0xFC83, 0x9F09, 0xFC84, 0x9F0A, 0xFC85, 0x9F0C, 0xFC86, 0x9F0F, 0xFC87, 0x9F11, 0xFC88, 0x9F12,
+ 0xFC89, 0x9F14, 0xFC8A, 0x9F15, 0xFC8B, 0x9F16, 0xFC8C, 0x9F18, 0xFC8D, 0x9F1A, 0xFC8E, 0x9F1B, 0xFC8F, 0x9F1C, 0xFC90, 0x9F1D,
+ 0xFC91, 0x9F1E, 0xFC92, 0x9F1F, 0xFC93, 0x9F21, 0xFC94, 0x9F23, 0xFC95, 0x9F24, 0xFC96, 0x9F25, 0xFC97, 0x9F26, 0xFC98, 0x9F27,
+ 0xFC99, 0x9F28, 0xFC9A, 0x9F29, 0xFC9B, 0x9F2A, 0xFC9C, 0x9F2B, 0xFC9D, 0x9F2D, 0xFC9E, 0x9F2E, 0xFC9F, 0x9F30, 0xFCA0, 0x9F31,
+ 0xFD40, 0x9F32, 0xFD41, 0x9F33, 0xFD42, 0x9F34, 0xFD43, 0x9F35, 0xFD44, 0x9F36, 0xFD45, 0x9F38, 0xFD46, 0x9F3A, 0xFD47, 0x9F3C,
+ 0xFD48, 0x9F3F, 0xFD49, 0x9F40, 0xFD4A, 0x9F41, 0xFD4B, 0x9F42, 0xFD4C, 0x9F43, 0xFD4D, 0x9F45, 0xFD4E, 0x9F46, 0xFD4F, 0x9F47,
+ 0xFD50, 0x9F48, 0xFD51, 0x9F49, 0xFD52, 0x9F4A, 0xFD53, 0x9F4B, 0xFD54, 0x9F4C, 0xFD55, 0x9F4D, 0xFD56, 0x9F4E, 0xFD57, 0x9F4F,
+ 0xFD58, 0x9F52, 0xFD59, 0x9F53, 0xFD5A, 0x9F54, 0xFD5B, 0x9F55, 0xFD5C, 0x9F56, 0xFD5D, 0x9F57, 0xFD5E, 0x9F58, 0xFD5F, 0x9F59,
+ 0xFD60, 0x9F5A, 0xFD61, 0x9F5B, 0xFD62, 0x9F5C, 0xFD63, 0x9F5D, 0xFD64, 0x9F5E, 0xFD65, 0x9F5F, 0xFD66, 0x9F60, 0xFD67, 0x9F61,
+ 0xFD68, 0x9F62, 0xFD69, 0x9F63, 0xFD6A, 0x9F64, 0xFD6B, 0x9F65, 0xFD6C, 0x9F66, 0xFD6D, 0x9F67, 0xFD6E, 0x9F68, 0xFD6F, 0x9F69,
+ 0xFD70, 0x9F6A, 0xFD71, 0x9F6B, 0xFD72, 0x9F6C, 0xFD73, 0x9F6D, 0xFD74, 0x9F6E, 0xFD75, 0x9F6F, 0xFD76, 0x9F70, 0xFD77, 0x9F71,
+ 0xFD78, 0x9F72, 0xFD79, 0x9F73, 0xFD7A, 0x9F74, 0xFD7B, 0x9F75, 0xFD7C, 0x9F76, 0xFD7D, 0x9F77, 0xFD7E, 0x9F78, 0xFD80, 0x9F79,
+ 0xFD81, 0x9F7A, 0xFD82, 0x9F7B, 0xFD83, 0x9F7C, 0xFD84, 0x9F7D, 0xFD85, 0x9F7E, 0xFD86, 0x9F81, 0xFD87, 0x9F82, 0xFD88, 0x9F8D,
+ 0xFD89, 0x9F8E, 0xFD8A, 0x9F8F, 0xFD8B, 0x9F90, 0xFD8C, 0x9F91, 0xFD8D, 0x9F92, 0xFD8E, 0x9F93, 0xFD8F, 0x9F94, 0xFD90, 0x9F95,
+ 0xFD91, 0x9F96, 0xFD92, 0x9F97, 0xFD93, 0x9F98, 0xFD94, 0x9F9C, 0xFD95, 0x9F9D, 0xFD96, 0x9F9E, 0xFD97, 0x9FA1, 0xFD98, 0x9FA2,
+ 0xFD99, 0x9FA3, 0xFD9A, 0x9FA4, 0xFD9B, 0x9FA5, 0xFD9C, 0xF92C, 0xFD9D, 0xF979, 0xFD9E, 0xF995, 0xFD9F, 0xF9E7, 0xFDA0, 0xF9F1,
+ 0xFE40, 0xFA0C, 0xFE41, 0xFA0D, 0xFE42, 0xFA0E, 0xFE43, 0xFA0F, 0xFE44, 0xFA11, 0xFE45, 0xFA13, 0xFE46, 0xFA14, 0xFE47, 0xFA18,
+ 0xFE48, 0xFA1F, 0xFE49, 0xFA20, 0xFE4A, 0xFA21, 0xFE4B, 0xFA23, 0xFE4C, 0xFA24, 0xFE4D, 0xFA27, 0xFE4E, 0xFA28, 0xFE4F, 0xFA29,
+ 0, 0
+};
+#endif
+
+#if FF_CODE_PAGE == 949 || FF_CODE_PAGE == 0 /* Korean */
+static const WCHAR uni2oem949[] = { /* Unicode --> Korean pairs */
+ 0x00A1, 0xA2AE, 0x00A4, 0xA2B4, 0x00A7, 0xA1D7, 0x00A8, 0xA1A7, 0x00AA, 0xA8A3, 0x00AD, 0xA1A9, 0x00AE, 0xA2E7, 0x00B0, 0xA1C6,
+ 0x00B1, 0xA1BE, 0x00B2, 0xA9F7, 0x00B3, 0xA9F8, 0x00B4, 0xA2A5, 0x00B6, 0xA2D2, 0x00B7, 0xA1A4, 0x00B8, 0xA2AC, 0x00B9, 0xA9F6,
+ 0x00BA, 0xA8AC, 0x00BC, 0xA8F9, 0x00BD, 0xA8F6, 0x00BE, 0xA8FA, 0x00BF, 0xA2AF, 0x00C6, 0xA8A1, 0x00D0, 0xA8A2, 0x00D7, 0xA1BF,
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+ 0x02DD, 0xA2A9, 0x0391, 0xA5C1, 0x0392, 0xA5C2, 0x0393, 0xA5C3, 0x0394, 0xA5C4, 0x0395, 0xA5C5, 0x0396, 0xA5C6, 0x0397, 0xA5C7,
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+ 0x03A9, 0xA5D8, 0x03B1, 0xA5E1, 0x03B2, 0xA5E2, 0x03B3, 0xA5E3, 0x03B4, 0xA5E4, 0x03B5, 0xA5E5, 0x03B6, 0xA5E6, 0x03B7, 0xA5E7,
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+ 0x03C0, 0xA5F0, 0x03C1, 0xA5F1, 0x03C3, 0xA5F2, 0x03C4, 0xA5F3, 0x03C5, 0xA5F4, 0x03C6, 0xA5F5, 0x03C7, 0xA5F6, 0x03C8, 0xA5F7,
+ 0x03C9, 0xA5F8, 0x0401, 0xACA7, 0x0410, 0xACA1, 0x0411, 0xACA2, 0x0412, 0xACA3, 0x0413, 0xACA4, 0x0414, 0xACA5, 0x0415, 0xACA6,
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+ 0x0446, 0xACE8, 0x0447, 0xACE9, 0x0448, 0xACEA, 0x0449, 0xACEB, 0x044A, 0xACEC, 0x044B, 0xACED, 0x044C, 0xACEE, 0x044D, 0xACEF,
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+ 0x2020, 0xA2D3, 0x2021, 0xA2D4, 0x2025, 0xA1A5, 0x2026, 0xA1A6, 0x2030, 0xA2B6, 0x2032, 0xA1C7, 0x2033, 0xA1C8, 0x203B, 0xA1D8,
+ 0x2074, 0xA9F9, 0x207F, 0xA9FA, 0x2081, 0xA9FB, 0x2082, 0xA9FC, 0x2083, 0xA9FD, 0x2084, 0xA9FE, 0x20AC, 0xA2E6, 0x2103, 0xA1C9,
+ 0x2109, 0xA2B5, 0x2113, 0xA7A4, 0x2116, 0xA2E0, 0x2121, 0xA2E5, 0x2122, 0xA2E2, 0x2126, 0xA7D9, 0x212B, 0xA1CA, 0x2153, 0xA8F7,
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+ 0x30AF, 0xABAF, 0x30B0, 0xABB0, 0x30B1, 0xABB1, 0x30B2, 0xABB2, 0x30B3, 0xABB3, 0x30B4, 0xABB4, 0x30B5, 0xABB5, 0x30B6, 0xABB6,
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+ 0x30C7, 0xABC7, 0x30C8, 0xABC8, 0x30C9, 0xABC9, 0x30CA, 0xABCA, 0x30CB, 0xABCB, 0x30CC, 0xABCC, 0x30CD, 0xABCD, 0x30CE, 0xABCE,
+ 0x30CF, 0xABCF, 0x30D0, 0xABD0, 0x30D1, 0xABD1, 0x30D2, 0xABD2, 0x30D3, 0xABD3, 0x30D4, 0xABD4, 0x30D5, 0xABD5, 0x30D6, 0xABD6,
+ 0x30D7, 0xABD7, 0x30D8, 0xABD8, 0x30D9, 0xABD9, 0x30DA, 0xABDA, 0x30DB, 0xABDB, 0x30DC, 0xABDC, 0x30DD, 0xABDD, 0x30DE, 0xABDE,
+ 0x30DF, 0xABDF, 0x30E0, 0xABE0, 0x30E1, 0xABE1, 0x30E2, 0xABE2, 0x30E3, 0xABE3, 0x30E4, 0xABE4, 0x30E5, 0xABE5, 0x30E6, 0xABE6,
+ 0x30E7, 0xABE7, 0x30E8, 0xABE8, 0x30E9, 0xABE9, 0x30EA, 0xABEA, 0x30EB, 0xABEB, 0x30EC, 0xABEC, 0x30ED, 0xABED, 0x30EE, 0xABEE,
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+ 0x3131, 0xA4A1, 0x3132, 0xA4A2, 0x3133, 0xA4A3, 0x3134, 0xA4A4, 0x3135, 0xA4A5, 0x3136, 0xA4A6, 0x3137, 0xA4A7, 0x3138, 0xA4A8,
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+ 0x3151, 0xA4C1, 0x3152, 0xA4C2, 0x3153, 0xA4C3, 0x3154, 0xA4C4, 0x3155, 0xA4C5, 0x3156, 0xA4C6, 0x3157, 0xA4C7, 0x3158, 0xA4C8,
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+ 0x3171, 0xA4E1, 0x3172, 0xA4E2, 0x3173, 0xA4E3, 0x3174, 0xA4E4, 0x3175, 0xA4E5, 0x3176, 0xA4E6, 0x3177, 0xA4E7, 0x3178, 0xA4E8,
+ 0x3179, 0xA4E9, 0x317A, 0xA4EA, 0x317B, 0xA4EB, 0x317C, 0xA4EC, 0x317D, 0xA4ED, 0x317E, 0xA4EE, 0x317F, 0xA4EF, 0x3180, 0xA4F0,
+ 0x3181, 0xA4F1, 0x3182, 0xA4F2, 0x3183, 0xA4F3, 0x3184, 0xA4F4, 0x3185, 0xA4F5, 0x3186, 0xA4F6, 0x3187, 0xA4F7, 0x3188, 0xA4F8,
+ 0x3189, 0xA4F9, 0x318A, 0xA4FA, 0x318B, 0xA4FB, 0x318C, 0xA4FC, 0x318D, 0xA4FD, 0x318E, 0xA4FE, 0x3200, 0xA9B1, 0x3201, 0xA9B2,
+ 0x3202, 0xA9B3, 0x3203, 0xA9B4, 0x3204, 0xA9B5, 0x3205, 0xA9B6, 0x3206, 0xA9B7, 0x3207, 0xA9B8, 0x3208, 0xA9B9, 0x3209, 0xA9BA,
+ 0x320A, 0xA9BB, 0x320B, 0xA9BC, 0x320C, 0xA9BD, 0x320D, 0xA9BE, 0x320E, 0xA9BF, 0x320F, 0xA9C0, 0x3210, 0xA9C1, 0x3211, 0xA9C2,
+ 0x3212, 0xA9C3, 0x3213, 0xA9C4, 0x3214, 0xA9C5, 0x3215, 0xA9C6, 0x3216, 0xA9C7, 0x3217, 0xA9C8, 0x3218, 0xA9C9, 0x3219, 0xA9CA,
+ 0x321A, 0xA9CB, 0x321B, 0xA9CC, 0x321C, 0xA2DF, 0x3260, 0xA8B1, 0x3261, 0xA8B2, 0x3262, 0xA8B3, 0x3263, 0xA8B4, 0x3264, 0xA8B5,
+ 0x3265, 0xA8B6, 0x3266, 0xA8B7, 0x3267, 0xA8B8, 0x3268, 0xA8B9, 0x3269, 0xA8BA, 0x326A, 0xA8BB, 0x326B, 0xA8BC, 0x326C, 0xA8BD,
+ 0x326D, 0xA8BE, 0x326E, 0xA8BF, 0x326F, 0xA8C0, 0x3270, 0xA8C1, 0x3271, 0xA8C2, 0x3272, 0xA8C3, 0x3273, 0xA8C4, 0x3274, 0xA8C5,
+ 0x3275, 0xA8C6, 0x3276, 0xA8C7, 0x3277, 0xA8C8, 0x3278, 0xA8C9, 0x3279, 0xA8CA, 0x327A, 0xA8CB, 0x327B, 0xA8CC, 0x327F, 0xA2DE,
+ 0x3380, 0xA7C9, 0x3381, 0xA7CA, 0x3382, 0xA7CB, 0x3383, 0xA7CC, 0x3384, 0xA7CD, 0x3388, 0xA7BA, 0x3389, 0xA7BB, 0x338A, 0xA7DC,
+ 0x338B, 0xA7DD, 0x338C, 0xA7DE, 0x338D, 0xA7B6, 0x338E, 0xA7B7, 0x338F, 0xA7B8, 0x3390, 0xA7D4, 0x3391, 0xA7D5, 0x3392, 0xA7D6,
+ 0x3393, 0xA7D7, 0x3394, 0xA7D8, 0x3395, 0xA7A1, 0x3396, 0xA7A2, 0x3397, 0xA7A3, 0x3398, 0xA7A5, 0x3399, 0xA7AB, 0x339A, 0xA7AC,
+ 0x339B, 0xA7AD, 0x339C, 0xA7AE, 0x339D, 0xA7AF, 0x339E, 0xA7B0, 0x339F, 0xA7B1, 0x33A0, 0xA7B2, 0x33A1, 0xA7B3, 0x33A2, 0xA7B4,
+ 0x33A3, 0xA7A7, 0x33A4, 0xA7A8, 0x33A5, 0xA7A9, 0x33A6, 0xA7AA, 0x33A7, 0xA7BD, 0x33A8, 0xA7BE, 0x33A9, 0xA7E5, 0x33AA, 0xA7E6,
+ 0x33AB, 0xA7E7, 0x33AC, 0xA7E8, 0x33AD, 0xA7E1, 0x33AE, 0xA7E2, 0x33AF, 0xA7E3, 0x33B0, 0xA7BF, 0x33B1, 0xA7C0, 0x33B2, 0xA7C1,
+ 0x33B3, 0xA7C2, 0x33B4, 0xA7C3, 0x33B5, 0xA7C4, 0x33B6, 0xA7C5, 0x33B7, 0xA7C6, 0x33B8, 0xA7C7, 0x33B9, 0xA7C8, 0x33BA, 0xA7CE,
+ 0x33BB, 0xA7CF, 0x33BC, 0xA7D0, 0x33BD, 0xA7D1, 0x33BE, 0xA7D2, 0x33BF, 0xA7D3, 0x33C0, 0xA7DA, 0x33C1, 0xA7DB, 0x33C2, 0xA2E3,
+ 0x33C3, 0xA7EC, 0x33C4, 0xA7A6, 0x33C5, 0xA7E0, 0x33C6, 0xA7EF, 0x33C7, 0xA2E1, 0x33C8, 0xA7BC, 0x33C9, 0xA7ED, 0x33CA, 0xA7B5,
+ 0x33CF, 0xA7B9, 0x33D0, 0xA7EA, 0x33D3, 0xA7EB, 0x33D6, 0xA7DF, 0x33D8, 0xA2E4, 0x33DB, 0xA7E4, 0x33DC, 0xA7EE, 0x33DD, 0xA7E9,
+ 0x4E00, 0xECE9, 0x4E01, 0xEFCB, 0x4E03, 0xF6D2, 0x4E07, 0xD8B2, 0x4E08, 0xEDDB, 0x4E09, 0xDFB2, 0x4E0A, 0xDFBE, 0x4E0B, 0xF9BB,
+ 0x4E0D, 0xDCF4, 0x4E11, 0xF5E4, 0x4E14, 0xF3A6, 0x4E15, 0xDDE0, 0x4E16, 0xE1A6, 0x4E18, 0xCEF8, 0x4E19, 0xDCB0, 0x4E1E, 0xE3AA,
+ 0x4E2D, 0xF1E9, 0x4E32, 0xCDFA, 0x4E38, 0xFCAF, 0x4E39, 0xD3A1, 0x4E3B, 0xF1AB, 0x4E42, 0xE7D1, 0x4E43, 0xD2AC, 0x4E45, 0xCEF9,
+ 0x4E4B, 0xF1FD, 0x4E4D, 0xDEBF, 0x4E4E, 0xFBBA, 0x4E4F, 0xF9B9, 0x4E56, 0xCED2, 0x4E58, 0xE3AB, 0x4E59, 0xEBE0, 0x4E5D, 0xCEFA,
+ 0x4E5E, 0xCBF7, 0x4E5F, 0xE5A5, 0x4E6B, 0xCAE1, 0x4E6D, 0xD4CC, 0x4E73, 0xEAE1, 0x4E76, 0xDCE3, 0x4E77, 0xDFAD, 0x4E7E, 0xCBEB,
+ 0x4E82, 0xD5AF, 0x4E86, 0xD6F5, 0x4E88, 0xE5F8, 0x4E8B, 0xDEC0, 0x4E8C, 0xECA3, 0x4E8E, 0xE9CD, 0x4E90, 0xEAA7, 0x4E91, 0xE9F6,
+ 0x4E92, 0xFBBB, 0x4E94, 0xE7E9, 0x4E95, 0xEFCC, 0x4E98, 0xD0E6, 0x4E9B, 0xDEC1, 0x4E9E, 0xE4AC, 0x4EA1, 0xD8CC, 0x4EA2, 0xF9F1,
+ 0x4EA4, 0xCEDF, 0x4EA5, 0xFAA4, 0x4EA6, 0xE6B2, 0x4EA8, 0xFAFB, 0x4EAB, 0xFABD, 0x4EAC, 0xCCC8, 0x4EAD, 0xEFCD, 0x4EAE, 0xD5D5,
+ 0x4EB6, 0xD3A2, 0x4EBA, 0xECD1, 0x4EC0, 0xE4A7, 0x4EC1, 0xECD2, 0x4EC4, 0xF6B1, 0x4EC7, 0xCEFB, 0x4ECA, 0xD0D1, 0x4ECB, 0xCBBF,
+ 0x4ECD, 0xEDA4, 0x4ED4, 0xEDA8, 0x4ED5, 0xDEC2, 0x4ED6, 0xF6E2, 0x4ED7, 0xEDDC, 0x4ED8, 0xDCF5, 0x4ED9, 0xE0B9, 0x4EDD, 0xD4CE,
+ 0x4EDF, 0xF4B5, 0x4EE3, 0xD3DB, 0x4EE4, 0xD6B5, 0x4EE5, 0xECA4, 0x4EF0, 0xE4E6, 0x4EF2, 0xF1EA, 0x4EF6, 0xCBEC, 0x4EF7, 0xCBC0,
+ 0x4EFB, 0xECF2, 0x4F01, 0xD0EA, 0x4F09, 0xF9F2, 0x4F0A, 0xECA5, 0x4F0B, 0xD0DF, 0x4F0D, 0xE7EA, 0x4F0E, 0xD0EB, 0x4F0F, 0xDCD1,
+ 0x4F10, 0xDBE9, 0x4F11, 0xFDCC, 0x4F2F, 0xDBD7, 0x4F34, 0xDAE1, 0x4F36, 0xD6B6, 0x4F38, 0xE3DF, 0x4F3A, 0xDEC3, 0x4F3C, 0xDEC4,
+ 0x4F3D, 0xCAA1, 0x4F43, 0xEEEC, 0x4F46, 0xD3A3, 0x4F47, 0xEEB7, 0x4F48, 0xF8CF, 0x4F4D, 0xEAC8, 0x4F4E, 0xEEB8, 0x4F4F, 0xF1AC,
+ 0x4F50, 0xF1A5, 0x4F51, 0xE9CE, 0x4F55, 0xF9BC, 0x4F59, 0xE5F9, 0x4F5A, 0xECEA, 0x4F5B, 0xDDD6, 0x4F5C, 0xEDC2, 0x4F69, 0xF8A5,
+ 0x4F6F, 0xE5BA, 0x4F70, 0xDBD8, 0x4F73, 0xCAA2, 0x4F76, 0xD1CD, 0x4F7A, 0xEEED, 0x4F7E, 0xECEB, 0x4F7F, 0xDEC5, 0x4F81, 0xE3E0,
+ 0x4F83, 0xCAC9, 0x4F84, 0xF2E9, 0x4F86, 0xD5CE, 0x4F88, 0xF6B6, 0x4F8A, 0xCEC2, 0x4F8B, 0xD6C7, 0x4F8D, 0xE3B4, 0x4F8F, 0xF1AD,
+ 0x4F91, 0xEAE2, 0x4F96, 0xD7C2, 0x4F98, 0xF3A7, 0x4F9B, 0xCDEA, 0x4F9D, 0xEBEE, 0x4FAE, 0xD9B2, 0x4FAF, 0xFDA5, 0x4FB5, 0xF6D5,
+ 0x4FB6, 0xD5E2, 0x4FBF, 0xF8B5, 0x4FC2, 0xCCF5, 0x4FC3, 0xF5B5, 0x4FC4, 0xE4AD, 0x4FC9, 0xE7EB, 0x4FCA, 0xF1D5, 0x4FCE, 0xF0BB,
+ 0x4FD1, 0xE9B5, 0x4FD3, 0xCCC9, 0x4FD4, 0xFAD5, 0x4FD7, 0xE1D4, 0x4FDA, 0xD7D6, 0x4FDD, 0xDCC1, 0x4FDF, 0xDEC6, 0x4FE0, 0xFAEF,
+ 0x4FE1, 0xE3E1, 0x4FEE, 0xE1F3, 0x4FEF, 0xDCF6, 0x4FF1, 0xCEFC, 0x4FF3, 0xDBC4, 0x4FF5, 0xF8F1, 0x4FF8, 0xDCE4, 0x4FFA, 0xE5EF,
+ 0x5002, 0xDCB1, 0x5006, 0xD5D6, 0x5009, 0xF3DA, 0x500B, 0xCBC1, 0x500D, 0xDBC3, 0x5011, 0xD9FA, 0x5012, 0xD3EE, 0x5016, 0xFAB8,
+ 0x5019, 0xFDA6, 0x501A, 0xEBEF, 0x501C, 0xF4A6, 0x501E, 0xCCCA, 0x501F, 0xF3A8, 0x5021, 0xF3DB, 0x5023, 0xDBA7, 0x5024, 0xF6B7,
+ 0x5026, 0xCFE6, 0x5027, 0xF0F2, 0x5028, 0xCBDA, 0x502A, 0xE7D2, 0x502B, 0xD7C3, 0x502C, 0xF6F0, 0x502D, 0xE8DE, 0x503B, 0xE5A6,
+ 0x5043, 0xE5E7, 0x5047, 0xCAA3, 0x5048, 0xCCA7, 0x5049, 0xEAC9, 0x504F, 0xF8B6, 0x5055, 0xFAA5, 0x505A, 0xF1AE, 0x505C, 0xEFCE,
+ 0x5065, 0xCBED, 0x5074, 0xF6B0, 0x5075, 0xEFCF, 0x5076, 0xE9CF, 0x5078, 0xF7DE, 0x5080, 0xCED3, 0x5085, 0xDCF7, 0x508D, 0xDBA8,
+ 0x5091, 0xCBF8, 0x5098, 0xDFA1, 0x5099, 0xDDE1, 0x50AC, 0xF5CA, 0x50AD, 0xE9B6, 0x50B2, 0xE7EC, 0x50B3, 0xEEEE, 0x50B5, 0xF3F0,
+ 0x50B7, 0xDFBF, 0x50BE, 0xCCCB, 0x50C5, 0xD0C1, 0x50C9, 0xF4D2, 0x50CA, 0xE0BA, 0x50CF, 0xDFC0, 0x50D1, 0xCEE0, 0x50D5, 0xDCD2,
+ 0x50D6, 0xFDEA, 0x50DA, 0xD6F6, 0x50DE, 0xEACA, 0x50E5, 0xE8E9, 0x50E7, 0xE3AC, 0x50ED, 0xF3D0, 0x50F9, 0xCAA4, 0x50FB, 0xDBF8,
+ 0x50FF, 0xDEC7, 0x5100, 0xEBF0, 0x5101, 0xF1D6, 0x5104, 0xE5E2, 0x5106, 0xCCCC, 0x5109, 0xCBFB, 0x5112, 0xEAE3, 0x511F, 0xDFC1,
+ 0x5121, 0xD6ED, 0x512A, 0xE9D0, 0x5132, 0xEEB9, 0x5137, 0xD5E3, 0x513A, 0xD1D3, 0x513C, 0xE5F0, 0x5140, 0xE8B4, 0x5141, 0xEBC3,
+ 0x5143, 0xEAAA, 0x5144, 0xFAFC, 0x5145, 0xF5F6, 0x5146, 0xF0BC, 0x5147, 0xFDD4, 0x5148, 0xE0BB, 0x5149, 0xCEC3, 0x514B, 0xD0BA,
+ 0x514C, 0xF7BA, 0x514D, 0xD8F3, 0x514E, 0xF7CD, 0x5152, 0xE4AE, 0x515C, 0xD4DF, 0x5162, 0xD0E7, 0x5165, 0xECFD, 0x5167, 0xD2AE,
+ 0x5168, 0xEEEF, 0x5169, 0xD5D7, 0x516A, 0xEAE4, 0x516B, 0xF8A2, 0x516C, 0xCDEB, 0x516D, 0xD7BF, 0x516E, 0xFBB1, 0x5171, 0xCDEC,
+ 0x5175, 0xDCB2, 0x5176, 0xD0EC, 0x5177, 0xCEFD, 0x5178, 0xEEF0, 0x517C, 0xCCC2, 0x5180, 0xD0ED, 0x5186, 0xE5F7, 0x518A, 0xF3FC,
+ 0x518D, 0xEEA2, 0x5192, 0xD9B3, 0x5195, 0xD8F4, 0x5197, 0xE9B7, 0x51A0, 0xCEAE, 0x51A5, 0xD9A2, 0x51AA, 0xD8F1, 0x51AC, 0xD4CF,
+ 0x51B6, 0xE5A7, 0x51B7, 0xD5D2, 0x51BD, 0xD6A9, 0x51C4, 0xF4A2, 0x51C6, 0xF1D7, 0x51C9, 0xD5D8, 0x51CB, 0xF0BD, 0x51CC, 0xD7D0,
+ 0x51CD, 0xD4D0, 0x51DC, 0xD7CF, 0x51DD, 0xEBEA, 0x51DE, 0xFDEB, 0x51E1, 0xDBED, 0x51F0, 0xFCC5, 0x51F1, 0xCBC2, 0x51F6, 0xFDD5,
+ 0x51F8, 0xF4C8, 0x51F9, 0xE8EA, 0x51FA, 0xF5F3, 0x51FD, 0xF9DE, 0x5200, 0xD3EF, 0x5203, 0xECD3, 0x5206, 0xDDC2, 0x5207, 0xEFB7,
+ 0x5208, 0xE7D4, 0x520A, 0xCACA, 0x520E, 0xD9FB, 0x5211, 0xFAFD, 0x5217, 0xD6AA, 0x521D, 0xF4F8, 0x5224, 0xF7F7, 0x5225, 0xDCAC,
+ 0x5229, 0xD7D7, 0x522A, 0xDFA2, 0x522E, 0xCEBE, 0x5230, 0xD3F0, 0x5236, 0xF0A4, 0x5237, 0xE1EC, 0x5238, 0xCFE7, 0x5239, 0xF3CB,
+ 0x523A, 0xEDA9, 0x523B, 0xCABE, 0x5243, 0xF4EF, 0x5247, 0xF6CE, 0x524A, 0xDEFB, 0x524B, 0xD0BB, 0x524C, 0xD5B7, 0x524D, 0xEEF1,
+ 0x5254, 0xF4A8, 0x5256, 0xDCF8, 0x525B, 0xCBA7, 0x525D, 0xDACE, 0x5261, 0xE0E6, 0x5269, 0xEDA5, 0x526A, 0xEEF2, 0x526F, 0xDCF9,
+ 0x5272, 0xF9DC, 0x5275, 0xF3DC, 0x527D, 0xF8F2, 0x527F, 0xF4F9, 0x5283, 0xFCF1, 0x5287, 0xD0BC, 0x5288, 0xDBF9, 0x5289, 0xD7B1,
+ 0x528D, 0xCBFC, 0x5291, 0xF0A5, 0x5292, 0xCBFD, 0x529B, 0xD5F4, 0x529F, 0xCDED, 0x52A0, 0xCAA5, 0x52A3, 0xD6AB, 0x52A4, 0xD0C2,
+ 0x52A9, 0xF0BE, 0x52AA, 0xD2BD, 0x52AB, 0xCCA4, 0x52BE, 0xFAB6, 0x52C1, 0xCCCD, 0x52C3, 0xDAFA, 0x52C5, 0xF6CF, 0x52C7, 0xE9B8,
+ 0x52C9, 0xD8F5, 0x52CD, 0xCCCE, 0x52D2, 0xD7CD, 0x52D5, 0xD4D1, 0x52D6, 0xE9ED, 0x52D8, 0xCAEB, 0x52D9, 0xD9E2, 0x52DB, 0xFDB2,
+ 0x52DD, 0xE3AD, 0x52DE, 0xD6CC, 0x52DF, 0xD9B4, 0x52E2, 0xE1A7, 0x52E3, 0xEED3, 0x52E4, 0xD0C3, 0x52F3, 0xFDB3, 0x52F5, 0xD5E4,
+ 0x52F8, 0xCFE8, 0x52FA, 0xEDC3, 0x52FB, 0xD0B2, 0x52FE, 0xCEFE, 0x52FF, 0xDAA8, 0x5305, 0xF8D0, 0x5308, 0xFDD6, 0x530D, 0xF8D1,
+ 0x530F, 0xF8D2, 0x5310, 0xDCD3, 0x5315, 0xDDE2, 0x5316, 0xFBF9, 0x5317, 0xDDC1, 0x5319, 0xE3B5, 0x5320, 0xEDDD, 0x5321, 0xCEC4,
+ 0x5323, 0xCBA1, 0x532A, 0xDDE3, 0x532F, 0xFCDD, 0x5339, 0xF9AF, 0x533F, 0xD2FB, 0x5340, 0xCFA1, 0x5341, 0xE4A8, 0x5343, 0xF4B6,
+ 0x5344, 0xECFE, 0x5347, 0xE3AE, 0x5348, 0xE7ED, 0x5349, 0xFDC1, 0x534A, 0xDAE2, 0x534D, 0xD8B3, 0x5351, 0xDDE4, 0x5352, 0xF0EF,
+ 0x5353, 0xF6F1, 0x5354, 0xFAF0, 0x5357, 0xD1F5, 0x535A, 0xDACF, 0x535C, 0xDCD4, 0x535E, 0xDCA6, 0x5360, 0xEFBF, 0x5366, 0xCECF,
+ 0x5368, 0xE0D9, 0x536F, 0xD9D6, 0x5370, 0xECD4, 0x5371, 0xEACB, 0x5374, 0xCABF, 0x5375, 0xD5B0, 0x5377, 0xCFE9, 0x537D, 0xF1ED,
+ 0x537F, 0xCCCF, 0x5384, 0xE4F8, 0x5393, 0xE4ED, 0x5398, 0xD7D8, 0x539A, 0xFDA7, 0x539F, 0xEAAB, 0x53A0, 0xF6B2, 0x53A5, 0xCFF0,
+ 0x53A6, 0xF9BD, 0x53AD, 0xE6F4, 0x53BB, 0xCBDB, 0x53C3, 0xF3D1, 0x53C8, 0xE9D1, 0x53C9, 0xF3A9, 0x53CA, 0xD0E0, 0x53CB, 0xE9D2,
+ 0x53CD, 0xDAE3, 0x53D4, 0xE2D2, 0x53D6, 0xF6A2, 0x53D7, 0xE1F4, 0x53DB, 0xDAE4, 0x53E1, 0xE7D5, 0x53E2, 0xF5BF, 0x53E3, 0xCFA2,
+ 0x53E4, 0xCDAF, 0x53E5, 0xCFA3, 0x53E9, 0xCDB0, 0x53EA, 0xF1FE, 0x53EB, 0xD0A3, 0x53EC, 0xE1AF, 0x53ED, 0xF8A3, 0x53EF, 0xCAA6,
+ 0x53F0, 0xF7BB, 0x53F1, 0xF2EA, 0x53F2, 0xDEC8, 0x53F3, 0xE9D3, 0x53F8, 0xDEC9, 0x5403, 0xFDDE, 0x5404, 0xCAC0, 0x5408, 0xF9EA,
+ 0x5409, 0xD1CE, 0x540A, 0xEED4, 0x540C, 0xD4D2, 0x540D, 0xD9A3, 0x540E, 0xFDA8, 0x540F, 0xD7D9, 0x5410, 0xF7CE, 0x5411, 0xFABE,
+ 0x541B, 0xCFD6, 0x541D, 0xD7F0, 0x541F, 0xEBE1, 0x5420, 0xF8C5, 0x5426, 0xDCFA, 0x5429, 0xDDC3, 0x542B, 0xF9DF, 0x5433, 0xE7EF,
+ 0x5438, 0xFDE5, 0x5439, 0xF6A3, 0x543B, 0xD9FC, 0x543C, 0xFDA9, 0x543E, 0xE7EE, 0x5442, 0xD5E5, 0x5448, 0xEFD0, 0x544A, 0xCDB1,
+ 0x5451, 0xF7A2, 0x5468, 0xF1B2, 0x546A, 0xF1B1, 0x5471, 0xCDB2, 0x5473, 0xDAAB, 0x5475, 0xCAA7, 0x547B, 0xE3E2, 0x547C, 0xFBBC,
+ 0x547D, 0xD9A4, 0x5480, 0xEEBA, 0x5486, 0xF8D3, 0x548C, 0xFBFA, 0x548E, 0xCFA4, 0x5490, 0xDCFB, 0x54A4, 0xF6E3, 0x54A8, 0xEDAA,
+ 0x54AB, 0xF2A1, 0x54AC, 0xCEE1, 0x54B3, 0xFAA6, 0x54B8, 0xF9E0, 0x54BD, 0xECD6, 0x54C0, 0xE4EE, 0x54C1, 0xF9A1, 0x54C4, 0xFBEF,
+ 0x54C8, 0xF9EB, 0x54C9, 0xEEA3, 0x54E1, 0xEAAC, 0x54E5, 0xCAA8, 0x54E8, 0xF4FA, 0x54ED, 0xCDD6, 0x54EE, 0xFCF6, 0x54F2, 0xF4C9,
+ 0x54FA, 0xF8D4, 0x5504, 0xF8A6, 0x5506, 0xDECA, 0x5507, 0xF2C6, 0x550E, 0xD7DA, 0x5510, 0xD3D0, 0x551C, 0xD8C5, 0x552F, 0xEAE6,
+ 0x5531, 0xF3DD, 0x5535, 0xE4DA, 0x553E, 0xF6E4, 0x5544, 0xF6F2, 0x5546, 0xDFC2, 0x554F, 0xD9FD, 0x5553, 0xCCF6, 0x5556, 0xD3BA,
+ 0x555E, 0xE4AF, 0x5563, 0xF9E1, 0x557C, 0xF0A6, 0x5580, 0xCBD3, 0x5584, 0xE0BC, 0x5586, 0xF4CA, 0x5587, 0xD4FA, 0x5589, 0xFDAA,
+ 0x558A, 0xF9E2, 0x5598, 0xF4B7, 0x5599, 0xFDC2, 0x559A, 0xFCB0, 0x559C, 0xFDEC, 0x559D, 0xCAE2, 0x55A7, 0xFDBD, 0x55A9, 0xEAE7,
+ 0x55AA, 0xDFC3, 0x55AB, 0xD1D2, 0x55AC, 0xCEE2, 0x55AE, 0xD3A4, 0x55C5, 0xFDAB, 0x55C7, 0xDFE0, 0x55D4, 0xF2C7, 0x55DA, 0xE7F0,
+ 0x55DC, 0xD0EE, 0x55DF, 0xF3AA, 0x55E3, 0xDECB, 0x55E4, 0xF6B8, 0x55FD, 0xE1F5, 0x55FE, 0xF1B3, 0x5606, 0xF7A3, 0x5609, 0xCAA9,
+ 0x5614, 0xCFA5, 0x5617, 0xDFC4, 0x562F, 0xE1B0, 0x5632, 0xF0BF, 0x5634, 0xF6A4, 0x5636, 0xE3B6, 0x5653, 0xFAC6, 0x5668, 0xD0EF,
+ 0x566B, 0xFDED, 0x5674, 0xDDC4, 0x5686, 0xFCF7, 0x56A5, 0xE6BF, 0x56AC, 0xDEAD, 0x56AE, 0xFABF, 0x56B4, 0xE5F1, 0x56BC, 0xEDC4,
+ 0x56CA, 0xD2A5, 0x56CD, 0xFDEE, 0x56D1, 0xF5B6, 0x56DA, 0xE1F6, 0x56DB, 0xDECC, 0x56DE, 0xFCDE, 0x56E0, 0xECD7, 0x56F0, 0xCDDD,
+ 0x56F9, 0xD6B7, 0x56FA, 0xCDB3, 0x5703, 0xF8D5, 0x5704, 0xE5D8, 0x5708, 0xCFEA, 0x570B, 0xCFD0, 0x570D, 0xEACC, 0x5712, 0xEAAE,
+ 0x5713, 0xEAAD, 0x5716, 0xD3F1, 0x5718, 0xD3A5, 0x571F, 0xF7CF, 0x5728, 0xEEA4, 0x572D, 0xD0A4, 0x5730, 0xF2A2, 0x573B, 0xD0F0,
+ 0x5740, 0xF2A3, 0x5742, 0xF7F8, 0x5747, 0xD0B3, 0x574A, 0xDBA9, 0x574D, 0xD3BB, 0x574E, 0xCAEC, 0x5750, 0xF1A6, 0x5751, 0xCBD5,
+ 0x5761, 0xF7E7, 0x5764, 0xCDDE, 0x5766, 0xF7A4, 0x576A, 0xF8C0, 0x576E, 0xD3DD, 0x5770, 0xCCD0, 0x5775, 0xCFA6, 0x577C, 0xF6F3,
+ 0x5782, 0xE1F7, 0x5788, 0xD3DC, 0x578B, 0xFAFE, 0x5793, 0xFAA7, 0x57A0, 0xEBD9, 0x57A2, 0xCFA7, 0x57A3, 0xEAAF, 0x57C3, 0xE4EF,
+ 0x57C7, 0xE9B9, 0x57C8, 0xF1D8, 0x57CB, 0xD8D8, 0x57CE, 0xE0F2, 0x57DF, 0xE6B4, 0x57E0, 0xDCFC, 0x57F0, 0xF3F1, 0x57F4, 0xE3D0,
+ 0x57F7, 0xF2FB, 0x57F9, 0xDBC6, 0x57FA, 0xD0F1, 0x57FC, 0xD0F2, 0x5800, 0xCFDC, 0x5802, 0xD3D1, 0x5805, 0xCCB1, 0x5806, 0xF7D8,
+ 0x5808, 0xCBA8, 0x5809, 0xEBBC, 0x580A, 0xE4BE, 0x581E, 0xF4DC, 0x5821, 0xDCC2, 0x5824, 0xF0A7, 0x5827, 0xE6C0, 0x582A, 0xCAED,
+ 0x582F, 0xE8EB, 0x5830, 0xE5E8, 0x5831, 0xDCC3, 0x5834, 0xEDDE, 0x5835, 0xD3F2, 0x583A, 0xCCF7, 0x584A, 0xCED4, 0x584B, 0xE7AB,
+ 0x584F, 0xCBC3, 0x5851, 0xE1B1, 0x5854, 0xF7B2, 0x5857, 0xD3F3, 0x5858, 0xD3D2, 0x585A, 0xF5C0, 0x585E, 0xDFDD, 0x5861, 0xEEF3,
+ 0x5862, 0xE7F1, 0x5864, 0xFDB4, 0x5875, 0xF2C8, 0x5879, 0xF3D2, 0x587C, 0xEEF4, 0x587E, 0xE2D3, 0x5883, 0xCCD1, 0x5885, 0xDFEA,
+ 0x5889, 0xE9BA, 0x5893, 0xD9D7, 0x589C, 0xF5CD, 0x589E, 0xF1F2, 0x589F, 0xFAC7, 0x58A8, 0xD9F8, 0x58A9, 0xD4C2, 0x58AE, 0xF6E5,
+ 0x58B3, 0xDDC5, 0x58BA, 0xE7F2, 0x58BB, 0xEDDF, 0x58BE, 0xCACB, 0x58C1, 0xDBFA, 0x58C5, 0xE8B5, 0x58C7, 0xD3A6, 0x58CE, 0xFDB5,
+ 0x58D1, 0xF9C9, 0x58D3, 0xE4E2, 0x58D5, 0xFBBD, 0x58D8, 0xD7A4, 0x58D9, 0xCEC5, 0x58DE, 0xCED5, 0x58DF, 0xD6E6, 0x58E4, 0xE5BD,
+ 0x58EB, 0xDECD, 0x58EC, 0xECF3, 0x58EF, 0xEDE0, 0x58F9, 0xECEC, 0x58FA, 0xFBBE, 0x58FB, 0xDFEB, 0x58FD, 0xE1F8, 0x590F, 0xF9BE,
+ 0x5914, 0xD0F3, 0x5915, 0xE0AA, 0x5916, 0xE8E2, 0x5919, 0xE2D4, 0x591A, 0xD2FD, 0x591C, 0xE5A8, 0x5922, 0xD9D3, 0x5927, 0xD3DE,
+ 0x5929, 0xF4B8, 0x592A, 0xF7BC, 0x592B, 0xDCFD, 0x592D, 0xE8EC, 0x592E, 0xE4E7, 0x5931, 0xE3F7, 0x5937, 0xECA8, 0x593E, 0xFAF1,
+ 0x5944, 0xE5F2, 0x5947, 0xD0F4, 0x5948, 0xD2AF, 0x5949, 0xDCE5, 0x594E, 0xD0A5, 0x594F, 0xF1B4, 0x5950, 0xFCB1, 0x5951, 0xCCF8,
+ 0x5954, 0xDDC6, 0x5955, 0xFAD1, 0x5957, 0xF7DF, 0x595A, 0xFAA8, 0x5960, 0xEEF5, 0x5962, 0xDECE, 0x5967, 0xE7F3, 0x596A, 0xF7AC,
+ 0x596B, 0xEBC4, 0x596C, 0xEDE1, 0x596D, 0xE0AB, 0x596E, 0xDDC7, 0x5973, 0xD2B3, 0x5974, 0xD2BF, 0x5978, 0xCACC, 0x597D, 0xFBBF,
+ 0x5982, 0xE5FD, 0x5983, 0xDDE5, 0x5984, 0xD8CD, 0x598A, 0xECF4, 0x5993, 0xD0F5, 0x5996, 0xE8ED, 0x5997, 0xD0D2, 0x5999, 0xD9D8,
+ 0x59A5, 0xF6E6, 0x59A8, 0xDBAA, 0x59AC, 0xF7E0, 0x59B9, 0xD8D9, 0x59BB, 0xF4A3, 0x59BE, 0xF4DD, 0x59C3, 0xEFD1, 0x59C6, 0xD9B5,
+ 0x59C9, 0xEDAB, 0x59CB, 0xE3B7, 0x59D0, 0xEEBB, 0x59D1, 0xCDB4, 0x59D3, 0xE0F3, 0x59D4, 0xEACD, 0x59D9, 0xECF5, 0x59DA, 0xE8EE,
+ 0x59DC, 0xCBA9, 0x59DD, 0xF1AF, 0x59E6, 0xCACD, 0x59E8, 0xECA9, 0x59EA, 0xF2EB, 0x59EC, 0xFDEF, 0x59EE, 0xF9F3, 0x59F8, 0xE6C1,
+ 0x59FB, 0xECD8, 0x59FF, 0xEDAC, 0x5A01, 0xEACE, 0x5A03, 0xE8DF, 0x5A11, 0xDECF, 0x5A18, 0xD2A6, 0x5A1B, 0xE7F4, 0x5A1C, 0xD1D6,
+ 0x5A1F, 0xE6C2, 0x5A20, 0xE3E3, 0x5A25, 0xE4B0, 0x5A29, 0xD8B4, 0x5A36, 0xF6A5, 0x5A3C, 0xF3DE, 0x5A41, 0xD7A5, 0x5A46, 0xF7E8,
+ 0x5A49, 0xE8C6, 0x5A5A, 0xFBE6, 0x5A62, 0xDDE6, 0x5A66, 0xDCFE, 0x5A92, 0xD8DA, 0x5A9A, 0xDAAC, 0x5A9B, 0xEAB0, 0x5AA4, 0xE3B8,
+ 0x5AC1, 0xCAAA, 0x5AC2, 0xE1F9, 0x5AC4, 0xEAB1, 0x5AC9, 0xF2EC, 0x5ACC, 0xFAEE, 0x5AE1, 0xEED5, 0x5AE6, 0xF9F4, 0x5AE9, 0xD2EC,
+ 0x5B05, 0xFBFB, 0x5B09, 0xFDF0, 0x5B0B, 0xE0BD, 0x5B0C, 0xCEE3, 0x5B16, 0xF8C6, 0x5B2A, 0xDEAE, 0x5B40, 0xDFC5, 0x5B43, 0xE5BE,
+ 0x5B50, 0xEDAD, 0x5B51, 0xFAEA, 0x5B54, 0xCDEE, 0x5B55, 0xEDA6, 0x5B57, 0xEDAE, 0x5B58, 0xF0ED, 0x5B5A, 0xDDA1, 0x5B5C, 0xEDAF,
+ 0x5B5D, 0xFCF8, 0x5B5F, 0xD8EB, 0x5B63, 0xCCF9, 0x5B64, 0xCDB5, 0x5B69, 0xFAA9, 0x5B6B, 0xE1DD, 0x5B70, 0xE2D5, 0x5B71, 0xEDCF,
+ 0x5B75, 0xDDA2, 0x5B78, 0xF9CA, 0x5B7A, 0xEAE8, 0x5B7C, 0xE5ED, 0x5B85, 0xD3EB, 0x5B87, 0xE9D4, 0x5B88, 0xE1FA, 0x5B89, 0xE4CC,
+ 0x5B8B, 0xE1E4, 0x5B8C, 0xE8C7, 0x5B8F, 0xCEDB, 0x5B93, 0xDCD5, 0x5B95, 0xF7B5, 0x5B96, 0xFCF3, 0x5B97, 0xF0F3, 0x5B98, 0xCEAF,
+ 0x5B99, 0xF1B5, 0x5B9A, 0xEFD2, 0x5B9B, 0xE8C8, 0x5B9C, 0xEBF1, 0x5BA2, 0xCBD4, 0x5BA3, 0xE0BE, 0x5BA4, 0xE3F8, 0x5BA5, 0xEAE9,
+ 0x5BA6, 0xFCB2, 0x5BAC, 0xE0F4, 0x5BAE, 0xCFE0, 0x5BB0, 0xEEA5, 0x5BB3, 0xFAAA, 0x5BB4, 0xE6C3, 0x5BB5, 0xE1B2, 0x5BB6, 0xCAAB,
+ 0x5BB8, 0xE3E4, 0x5BB9, 0xE9BB, 0x5BBF, 0xE2D6, 0x5BC0, 0xF3F2, 0x5BC2, 0xEED6, 0x5BC3, 0xEAB2, 0x5BC4, 0xD0F6, 0x5BC5, 0xECD9,
+ 0x5BC6, 0xDACB, 0x5BC7, 0xCFA8, 0x5BCC, 0xDDA3, 0x5BD0, 0xD8DB, 0x5BD2, 0xF9CE, 0x5BD3, 0xE9D5, 0x5BD4, 0xE3D1, 0x5BD7, 0xD2BC,
+ 0x5BDE, 0xD8AC, 0x5BDF, 0xF3CC, 0x5BE1, 0xCDFB, 0x5BE2, 0xF6D6, 0x5BE4, 0xE7F5, 0x5BE5, 0xE8EF, 0x5BE6, 0xE3F9, 0x5BE7, 0xD2BB,
+ 0x5BE8, 0xF3F3, 0x5BE9, 0xE3FB, 0x5BEB, 0xDED0, 0x5BEC, 0xCEB0, 0x5BEE, 0xD6F7, 0x5BEF, 0xF1D9, 0x5BF5, 0xF5C1, 0x5BF6, 0xDCC4,
+ 0x5BF8, 0xF5BB, 0x5BFA, 0xDED1, 0x5C01, 0xDCE6, 0x5C04, 0xDED2, 0x5C07, 0xEDE2, 0x5C08, 0xEEF6, 0x5C09, 0xEACF, 0x5C0A, 0xF0EE,
+ 0x5C0B, 0xE3FC, 0x5C0D, 0xD3DF, 0x5C0E, 0xD3F4, 0x5C0F, 0xE1B3, 0x5C11, 0xE1B4, 0x5C16, 0xF4D3, 0x5C19, 0xDFC6, 0x5C24, 0xE9D6,
+ 0x5C28, 0xDBAB, 0x5C31, 0xF6A6, 0x5C38, 0xE3B9, 0x5C39, 0xEBC5, 0x5C3A, 0xF4A9, 0x5C3B, 0xCDB6, 0x5C3C, 0xD2F9, 0x5C3E, 0xDAAD,
+ 0x5C3F, 0xD2E3, 0x5C40, 0xCFD1, 0x5C45, 0xCBDC, 0x5C46, 0xCCFA, 0x5C48, 0xCFDD, 0x5C4B, 0xE8A9, 0x5C4D, 0xE3BB, 0x5C4E, 0xE3BA,
+ 0x5C51, 0xE0DA, 0x5C55, 0xEEF7, 0x5C5B, 0xDCB3, 0x5C60, 0xD3F5, 0x5C62, 0xD7A6, 0x5C64, 0xF6B5, 0x5C65, 0xD7DB, 0x5C6C, 0xE1D5,
+ 0x5C6F, 0xD4EA, 0x5C71, 0xDFA3, 0x5C79, 0xFDDF, 0x5C90, 0xD0F7, 0x5C91, 0xEDD4, 0x5CA1, 0xCBAA, 0x5CA9, 0xE4DB, 0x5CAB, 0xE1FB,
+ 0x5CAC, 0xCBA2, 0x5CB1, 0xD3E0, 0x5CB3, 0xE4BF, 0x5CB5, 0xFBC0, 0x5CB7, 0xDABE, 0x5CB8, 0xE4CD, 0x5CBA, 0xD6B9, 0x5CBE, 0xEFC0,
+ 0x5CC0, 0xE1FC, 0x5CD9, 0xF6B9, 0x5CE0, 0xDFC7, 0x5CE8, 0xE4B1, 0x5CEF, 0xDCE7, 0x5CF0, 0xDCE8, 0x5CF4, 0xFAD6, 0x5CF6, 0xD3F6,
+ 0x5CFB, 0xF1DA, 0x5CFD, 0xFAF2, 0x5D07, 0xE2FD, 0x5D0D, 0xD5CF, 0x5D0E, 0xD0F8, 0x5D11, 0xCDDF, 0x5D14, 0xF5CB, 0x5D16, 0xE4F0,
+ 0x5D17, 0xCBAB, 0x5D19, 0xD7C4, 0x5D27, 0xE2FE, 0x5D29, 0xDDDA, 0x5D4B, 0xDAAE, 0x5D4C, 0xCAEE, 0x5D50, 0xD5B9, 0x5D69, 0xE3A1,
+ 0x5D6C, 0xE8E3, 0x5D6F, 0xF3AB, 0x5D87, 0xCFA9, 0x5D8B, 0xD3F7, 0x5D9D, 0xD4F1, 0x5DA0, 0xCEE4, 0x5DA2, 0xE8F2, 0x5DAA, 0xE5F5,
+ 0x5DB8, 0xE7AE, 0x5DBA, 0xD6BA, 0x5DBC, 0xDFEC, 0x5DBD, 0xE4C0, 0x5DCD, 0xE8E4, 0x5DD2, 0xD8B5, 0x5DD6, 0xE4DC, 0x5DDD, 0xF4B9,
+ 0x5DDE, 0xF1B6, 0x5DE1, 0xE2DE, 0x5DE2, 0xE1B5, 0x5DE5, 0xCDEF, 0x5DE6, 0xF1A7, 0x5DE7, 0xCEE5, 0x5DE8, 0xCBDD, 0x5DEB, 0xD9E3,
+ 0x5DEE, 0xF3AC, 0x5DF1, 0xD0F9, 0x5DF2, 0xECAB, 0x5DF3, 0xDED3, 0x5DF4, 0xF7E9, 0x5DF7, 0xF9F5, 0x5DFD, 0xE1DE, 0x5DFE, 0xCBEE,
+ 0x5E02, 0xE3BC, 0x5E03, 0xF8D6, 0x5E06, 0xDBEE, 0x5E0C, 0xFDF1, 0x5E11, 0xF7B6, 0x5E16, 0xF4DE, 0x5E19, 0xF2ED, 0x5E1B, 0xDBD9,
+ 0x5E1D, 0xF0A8, 0x5E25, 0xE1FD, 0x5E2B, 0xDED4, 0x5E2D, 0xE0AC, 0x5E33, 0xEDE3, 0x5E36, 0xD3E1, 0x5E38, 0xDFC8, 0x5E3D, 0xD9B6,
+ 0x5E3F, 0xFDAC, 0x5E40, 0xEFD3, 0x5E44, 0xE4C1, 0x5E45, 0xF8EB, 0x5E47, 0xDBAC, 0x5E4C, 0xFCC6, 0x5E55, 0xD8AD, 0x5E5F, 0xF6BA,
+ 0x5E61, 0xDBDF, 0x5E62, 0xD3D3, 0x5E63, 0xF8C7, 0x5E72, 0xCACE, 0x5E73, 0xF8C1, 0x5E74, 0xD2B4, 0x5E77, 0xDCB4, 0x5E78, 0xFAB9,
+ 0x5E79, 0xCACF, 0x5E7B, 0xFCB3, 0x5E7C, 0xEAEA, 0x5E7D, 0xEAEB, 0x5E7E, 0xD0FA, 0x5E84, 0xEDE4, 0x5E87, 0xDDE7, 0x5E8A, 0xDFC9,
+ 0x5E8F, 0xDFED, 0x5E95, 0xEEBC, 0x5E97, 0xEFC1, 0x5E9A, 0xCCD2, 0x5E9C, 0xDDA4, 0x5EA0, 0xDFCA, 0x5EA6, 0xD3F8, 0x5EA7, 0xF1A8,
+ 0x5EAB, 0xCDB7, 0x5EAD, 0xEFD4, 0x5EB5, 0xE4DD, 0x5EB6, 0xDFEE, 0x5EB7, 0xCBAC, 0x5EB8, 0xE9BC, 0x5EBE, 0xEAEC, 0x5EC2, 0xDFCB,
+ 0x5EC8, 0xF9BF, 0x5EC9, 0xD6AF, 0x5ECA, 0xD5C6, 0x5ED0, 0xCFAA, 0x5ED3, 0xCEA9, 0x5ED6, 0xD6F8, 0x5EDA, 0xF1B7, 0x5EDB, 0xEEF8,
+ 0x5EDF, 0xD9D9, 0x5EE0, 0xF3DF, 0x5EE2, 0xF8C8, 0x5EE3, 0xCEC6, 0x5EEC, 0xD5E6, 0x5EF3, 0xF4E6, 0x5EF6, 0xE6C5, 0x5EF7, 0xEFD5,
+ 0x5EFA, 0xCBEF, 0x5EFB, 0xFCDF, 0x5F01, 0xDCA7, 0x5F04, 0xD6E7, 0x5F0A, 0xF8C9, 0x5F0F, 0xE3D2, 0x5F11, 0xE3BD, 0x5F13, 0xCFE1,
+ 0x5F14, 0xF0C0, 0x5F15, 0xECDA, 0x5F17, 0xDDD7, 0x5F18, 0xFBF0, 0x5F1B, 0xECAC, 0x5F1F, 0xF0A9, 0x5F26, 0xFAD7, 0x5F27, 0xFBC1,
+ 0x5F29, 0xD2C0, 0x5F31, 0xE5B0, 0x5F35, 0xEDE5, 0x5F3A, 0xCBAD, 0x5F3C, 0xF9B0, 0x5F48, 0xF7A5, 0x5F4A, 0xCBAE, 0x5F4C, 0xDAAF,
+ 0x5F4E, 0xD8B6, 0x5F56, 0xD3A7, 0x5F57, 0xFBB2, 0x5F59, 0xFDC4, 0x5F5B, 0xECAD, 0x5F62, 0xFBA1, 0x5F66, 0xE5E9, 0x5F67, 0xE9EE,
+ 0x5F69, 0xF3F4, 0x5F6A, 0xF8F3, 0x5F6B, 0xF0C1, 0x5F6C, 0xDEAF, 0x5F6D, 0xF8B0, 0x5F70, 0xF3E0, 0x5F71, 0xE7AF, 0x5F77, 0xDBAD,
+ 0x5F79, 0xE6B5, 0x5F7C, 0xF9A8, 0x5F7F, 0xDDD8, 0x5F80, 0xE8D9, 0x5F81, 0xEFD6, 0x5F85, 0xD3E2, 0x5F87, 0xE2DF, 0x5F8A, 0xFCE0,
+ 0x5F8B, 0xD7C8, 0x5F8C, 0xFDAD, 0x5F90, 0xDFEF, 0x5F91, 0xCCD3, 0x5F92, 0xD3F9, 0x5F97, 0xD4F0, 0x5F98, 0xDBC7, 0x5F99, 0xDED5,
+ 0x5F9E, 0xF0F4, 0x5FA0, 0xD5D0, 0x5FA1, 0xE5D9, 0x5FA8, 0xFCC7, 0x5FA9, 0xDCD6, 0x5FAA, 0xE2E0, 0x5FAE, 0xDAB0, 0x5FB5, 0xF3A3,
+ 0x5FB7, 0xD3EC, 0x5FB9, 0xF4CB, 0x5FBD, 0xFDC5, 0x5FC3, 0xE3FD, 0x5FC5, 0xF9B1, 0x5FCC, 0xD0FB, 0x5FCD, 0xECDB, 0x5FD6, 0xF5BC,
+ 0x5FD7, 0xF2A4, 0x5FD8, 0xD8CE, 0x5FD9, 0xD8CF, 0x5FE0, 0xF5F7, 0x5FEB, 0xF6E1, 0x5FF5, 0xD2B7, 0x5FFD, 0xFBEC, 0x5FFF, 0xDDC8,
+ 0x600F, 0xE4E8, 0x6012, 0xD2C1, 0x6016, 0xF8D7, 0x601C, 0xD6BB, 0x601D, 0xDED6, 0x6020, 0xF7BD, 0x6021, 0xECAE, 0x6025, 0xD0E1,
+ 0x6027, 0xE0F5, 0x6028, 0xEAB3, 0x602A, 0xCED6, 0x602F, 0xCCA5, 0x6041, 0xECF6, 0x6042, 0xE2E1, 0x6043, 0xE3BE, 0x604D, 0xFCC8,
+ 0x6050, 0xCDF0, 0x6052, 0xF9F6, 0x6055, 0xDFF0, 0x6059, 0xE5BF, 0x605D, 0xCEBF, 0x6062, 0xFCE1, 0x6063, 0xEDB0, 0x6064, 0xFDD1,
+ 0x6065, 0xF6BB, 0x6068, 0xF9CF, 0x6069, 0xEBDA, 0x606A, 0xCAC1, 0x606C, 0xD2B8, 0x606D, 0xCDF1, 0x606F, 0xE3D3, 0x6070, 0xFDE6,
+ 0x6085, 0xE6ED, 0x6089, 0xE3FA, 0x608C, 0xF0AA, 0x608D, 0xF9D0, 0x6094, 0xFCE2, 0x6096, 0xF8A7, 0x609A, 0xE1E5, 0x609B, 0xEEF9,
+ 0x609F, 0xE7F6, 0x60A0, 0xEAED, 0x60A3, 0xFCB4, 0x60A4, 0xF5C2, 0x60A7, 0xD7DC, 0x60B0, 0xF0F5, 0x60B2, 0xDDE8, 0x60B3, 0xD3ED,
+ 0x60B4, 0xF5FC, 0x60B6, 0xDABF, 0x60B8, 0xCCFB, 0x60BC, 0xD3FA, 0x60BD, 0xF4A4, 0x60C5, 0xEFD7, 0x60C7, 0xD4C3, 0x60D1, 0xFBE3,
+ 0x60DA, 0xFBED, 0x60DC, 0xE0AD, 0x60DF, 0xEAEE, 0x60E0, 0xFBB3, 0x60E1, 0xE4C2, 0x60F0, 0xF6E7, 0x60F1, 0xD2DD, 0x60F3, 0xDFCC,
+ 0x60F6, 0xFCC9, 0x60F9, 0xE5A9, 0x60FA, 0xE0F6, 0x60FB, 0xF6B3, 0x6101, 0xE1FE, 0x6106, 0xCBF0, 0x6108, 0xEAEF, 0x6109, 0xEAF0,
+ 0x610D, 0xDAC0, 0x610E, 0xF8B4, 0x610F, 0xEBF2, 0x6115, 0xE4C3, 0x611A, 0xE9D7, 0x611B, 0xE4F1, 0x611F, 0xCAEF, 0x6127, 0xCED7,
+ 0x6130, 0xFCCA, 0x6134, 0xF3E1, 0x6137, 0xCBC4, 0x613C, 0xE3E5, 0x613E, 0xCBC5, 0x613F, 0xEAB4, 0x6142, 0xE9BD, 0x6144, 0xD7C9,
+ 0x6147, 0xEBDB, 0x6148, 0xEDB1, 0x614A, 0xCCC3, 0x614B, 0xF7BE, 0x614C, 0xFCCB, 0x6153, 0xF8F4, 0x6155, 0xD9B7, 0x6158, 0xF3D3,
+ 0x6159, 0xF3D4, 0x615D, 0xF7E4, 0x615F, 0xF7D1, 0x6162, 0xD8B7, 0x6163, 0xCEB1, 0x6164, 0xCAC2, 0x6167, 0xFBB4, 0x6168, 0xCBC6,
+ 0x616B, 0xF0F6, 0x616E, 0xD5E7, 0x6170, 0xEAD0, 0x6176, 0xCCD4, 0x6177, 0xCBAF, 0x617D, 0xF4AA, 0x617E, 0xE9AF, 0x6181, 0xF5C3,
+ 0x6182, 0xE9D8, 0x618A, 0xDDE9, 0x618E, 0xF1F3, 0x6190, 0xD5FB, 0x6191, 0xDEBB, 0x6194, 0xF4FB, 0x6198, 0xFDF3, 0x6199, 0xFDF2,
+ 0x619A, 0xF7A6, 0x61A4, 0xDDC9, 0x61A7, 0xD4D3, 0x61A9, 0xCCA8, 0x61AB, 0xDAC1, 0x61AC, 0xCCD5, 0x61AE, 0xD9E4, 0x61B2, 0xFACA,
+ 0x61B6, 0xE5E3, 0x61BA, 0xD3BC, 0x61BE, 0xCAF0, 0x61C3, 0xD0C4, 0x61C7, 0xCAD0, 0x61C8, 0xFAAB, 0x61C9, 0xEBEB, 0x61CA, 0xE7F8,
+ 0x61CB, 0xD9E5, 0x61E6, 0xD1D7, 0x61F2, 0xF3A4, 0x61F6, 0xD4FB, 0x61F7, 0xFCE3, 0x61F8, 0xFAD8, 0x61FA, 0xF3D5, 0x61FC, 0xCFAB,
+ 0x61FF, 0xEBF3, 0x6200, 0xD5FC, 0x6207, 0xD3D4, 0x6208, 0xCDFC, 0x620A, 0xD9E6, 0x620C, 0xE2F9, 0x620D, 0xE2A1, 0x620E, 0xEBD4,
+ 0x6210, 0xE0F7, 0x6211, 0xE4B2, 0x6212, 0xCCFC, 0x6216, 0xFBE4, 0x621A, 0xF4AB, 0x621F, 0xD0BD, 0x6221, 0xCAF1, 0x622A, 0xEFB8,
+ 0x622E, 0xD7C0, 0x6230, 0xEEFA, 0x6231, 0xFDF4, 0x6234, 0xD3E3, 0x6236, 0xFBC2, 0x623E, 0xD5E8, 0x623F, 0xDBAE, 0x6240, 0xE1B6,
+ 0x6241, 0xF8B7, 0x6247, 0xE0BF, 0x6248, 0xFBC3, 0x6249, 0xDDEA, 0x624B, 0xE2A2, 0x624D, 0xEEA6, 0x6253, 0xF6E8, 0x6258, 0xF6F5,
+ 0x626E, 0xDDCA, 0x6271, 0xD0E2, 0x6276, 0xDDA6, 0x6279, 0xDDEB, 0x627C, 0xE4F9, 0x627F, 0xE3AF, 0x6280, 0xD0FC, 0x6284, 0xF4FC,
+ 0x6289, 0xCCBC, 0x628A, 0xF7EA, 0x6291, 0xE5E4, 0x6292, 0xDFF1, 0x6295, 0xF7E1, 0x6297, 0xF9F7, 0x6298, 0xEFB9, 0x629B, 0xF8D8,
+ 0x62AB, 0xF9A9, 0x62B1, 0xF8D9, 0x62B5, 0xEEBD, 0x62B9, 0xD8C6, 0x62BC, 0xE4E3, 0x62BD, 0xF5CE, 0x62C2, 0xDDD9, 0x62C7, 0xD9E7,
+ 0x62C8, 0xD2B9, 0x62C9, 0xD5C3, 0x62CC, 0xDAE5, 0x62CD, 0xDAD0, 0x62CF, 0xD1D9, 0x62D0, 0xCED8, 0x62D2, 0xCBDE, 0x62D3, 0xF4AC,
+ 0x62D4, 0xDAFB, 0x62D6, 0xF6E9, 0x62D7, 0xE8F3, 0x62D8, 0xCFAC, 0x62D9, 0xF0F0, 0x62DB, 0xF4FD, 0x62DC, 0xDBC8, 0x62EC, 0xCEC0,
+ 0x62ED, 0xE3D4, 0x62EE, 0xD1CF, 0x62EF, 0xF1F5, 0x62F1, 0xCDF2, 0x62F3, 0xCFEB, 0x62F7, 0xCDB8, 0x62FE, 0xE3A6, 0x62FF, 0xD1DA,
+ 0x6301, 0xF2A5, 0x6307, 0xF2A6, 0x6309, 0xE4CE, 0x6311, 0xD3FB, 0x632B, 0xF1A9, 0x632F, 0xF2C9, 0x633A, 0xEFD8, 0x633B, 0xE6C9,
+ 0x633D, 0xD8B8, 0x633E, 0xFAF3, 0x6349, 0xF3B5, 0x634C, 0xF8A4, 0x634F, 0xD1F3, 0x6350, 0xE6C8, 0x6355, 0xF8DA, 0x6367, 0xDCE9,
+ 0x6368, 0xDED7, 0x636E, 0xCBDF, 0x6372, 0xCFEC, 0x6377, 0xF4DF, 0x637A, 0xD1F4, 0x637B, 0xD2BA, 0x637F, 0xDFF2, 0x6383, 0xE1B7,
+ 0x6388, 0xE2A3, 0x6389, 0xD3FC, 0x638C, 0xEDE6, 0x6392, 0xDBC9, 0x6396, 0xE4FA, 0x6398, 0xCFDE, 0x639B, 0xCED0, 0x63A0, 0xD5D3,
+ 0x63A1, 0xF3F5, 0x63A2, 0xF7AE, 0x63A5, 0xEFC8, 0x63A7, 0xCDF3, 0x63A8, 0xF5CF, 0x63A9, 0xE5F3, 0x63AA, 0xF0C2, 0x63C0, 0xCAD1,
+ 0x63C4, 0xEAF1, 0x63C6, 0xD0A6, 0x63CF, 0xD9DA, 0x63D0, 0xF0AB, 0x63D6, 0xEBE7, 0x63DA, 0xE5C0, 0x63DB, 0xFCB5, 0x63E1, 0xE4C4,
+ 0x63ED, 0xCCA9, 0x63EE, 0xFDC6, 0x63F4, 0xEAB5, 0x63F6, 0xE5AA, 0x63F7, 0xDFBA, 0x640D, 0xE1DF, 0x640F, 0xDAD1, 0x6414, 0xE1B8,
+ 0x6416, 0xE8F4, 0x6417, 0xD3FD, 0x641C, 0xE2A4, 0x6422, 0xF2CA, 0x642C, 0xDAE6, 0x642D, 0xF7B3, 0x643A, 0xFDCD, 0x643E, 0xF3B6,
+ 0x6458, 0xEED7, 0x6460, 0xF5C4, 0x6469, 0xD8A4, 0x646F, 0xF2A7, 0x6478, 0xD9B8, 0x6479, 0xD9B9, 0x647A, 0xEFC9, 0x6488, 0xD6CE,
+ 0x6491, 0xF7CB, 0x6492, 0xDFAE, 0x6493, 0xE8F5, 0x649A, 0xD2B5, 0x649E, 0xD3D5, 0x64A4, 0xF4CC, 0x64A5, 0xDAFC, 0x64AB, 0xD9E8,
+ 0x64AD, 0xF7EB, 0x64AE, 0xF5C9, 0x64B0, 0xF3BC, 0x64B2, 0xDAD2, 0x64BB, 0xD3B5, 0x64C1, 0xE8B6, 0x64C4, 0xD6CF, 0x64C5, 0xF4BA,
+ 0x64C7, 0xF7C9, 0x64CA, 0xCCAA, 0x64CD, 0xF0C3, 0x64CE, 0xCCD6, 0x64D2, 0xD0D3, 0x64D4, 0xD3BD, 0x64D8, 0xDBFB, 0x64DA, 0xCBE0,
+ 0x64E1, 0xD3E4, 0x64E2, 0xF6F7, 0x64E5, 0xD5BA, 0x64E6, 0xF3CD, 0x64E7, 0xCBE1, 0x64EC, 0xEBF4, 0x64F2, 0xF4AD, 0x64F4, 0xFCAA,
+ 0x64FA, 0xF7EC, 0x64FE, 0xE8F6, 0x6500, 0xDAE7, 0x6504, 0xF7CC, 0x6518, 0xE5C1, 0x651D, 0xE0EE, 0x6523, 0xD5FD, 0x652A, 0xCEE6,
+ 0x652B, 0xFCAB, 0x652C, 0xD5BB, 0x652F, 0xF2A8, 0x6536, 0xE2A5, 0x6537, 0xCDB9, 0x6538, 0xEAF2, 0x6539, 0xCBC7, 0x653B, 0xCDF4,
+ 0x653E, 0xDBAF, 0x653F, 0xEFD9, 0x6545, 0xCDBA, 0x6548, 0xFCF9, 0x654D, 0xDFF3, 0x654E, 0xCEE7, 0x654F, 0xDAC2, 0x6551, 0xCFAD,
+ 0x6556, 0xE7F9, 0x6557, 0xF8A8, 0x655E, 0xF3E2, 0x6562, 0xCAF2, 0x6563, 0xDFA4, 0x6566, 0xD4C4, 0x656C, 0xCCD7, 0x656D, 0xE5C2,
+ 0x6572, 0xCDBB, 0x6574, 0xEFDA, 0x6575, 0xEED8, 0x6577, 0xDDA7, 0x6578, 0xE2A6, 0x657E, 0xE0C0, 0x6582, 0xD6B0, 0x6583, 0xF8CA,
+ 0x6585, 0xFCFA, 0x6587, 0xD9FE, 0x658C, 0xDEB0, 0x6590, 0xDDEC, 0x6591, 0xDAE8, 0x6597, 0xD4E0, 0x6599, 0xD6F9, 0x659B, 0xCDD7,
+ 0x659C, 0xDED8, 0x659F, 0xF2F8, 0x65A1, 0xE4D6, 0x65A4, 0xD0C5, 0x65A5, 0xF4AE, 0x65A7, 0xDDA8, 0x65AB, 0xEDC5, 0x65AC, 0xF3D6,
+ 0x65AF, 0xDED9, 0x65B0, 0xE3E6, 0x65B7, 0xD3A8, 0x65B9, 0xDBB0, 0x65BC, 0xE5DA, 0x65BD, 0xE3BF, 0x65C1, 0xDBB1, 0x65C5, 0xD5E9,
+ 0x65CB, 0xE0C1, 0x65CC, 0xEFDB, 0x65CF, 0xF0E9, 0x65D2, 0xD7B2, 0x65D7, 0xD0FD, 0x65E0, 0xD9E9, 0x65E3, 0xD0FE, 0x65E5, 0xECED,
+ 0x65E6, 0xD3A9, 0x65E8, 0xF2A9, 0x65E9, 0xF0C4, 0x65EC, 0xE2E2, 0x65ED, 0xE9EF, 0x65F1, 0xF9D1, 0x65F4, 0xE9D9, 0x65FA, 0xE8DA,
+ 0x65FB, 0xDAC3, 0x65FC, 0xDAC4, 0x65FD, 0xD4C5, 0x65FF, 0xE7FA, 0x6606, 0xCDE0, 0x6607, 0xE3B0, 0x6609, 0xDBB2, 0x660A, 0xFBC4,
+ 0x660C, 0xF3E3, 0x660E, 0xD9A5, 0x660F, 0xFBE7, 0x6610, 0xDDCB, 0x6611, 0xD0D4, 0x6613, 0xE6B6, 0x6614, 0xE0AE, 0x6615, 0xFDDA,
+ 0x661E, 0xDCB5, 0x661F, 0xE0F8, 0x6620, 0xE7B1, 0x6625, 0xF5F0, 0x6627, 0xD8DC, 0x6628, 0xEDC6, 0x662D, 0xE1B9, 0x662F, 0xE3C0,
+ 0x6630, 0xF9C0, 0x6631, 0xE9F0, 0x6634, 0xD9DB, 0x6636, 0xF3E4, 0x663A, 0xDCB6, 0x663B, 0xE4E9, 0x6641, 0xF0C5, 0x6642, 0xE3C1,
+ 0x6643, 0xFCCC, 0x6644, 0xFCCD, 0x6649, 0xF2CB, 0x664B, 0xF2CC, 0x664F, 0xE4CF, 0x6659, 0xF1DB, 0x665B, 0xFAD9, 0x665D, 0xF1B8,
+ 0x665E, 0xFDF5, 0x665F, 0xE0F9, 0x6664, 0xE7FB, 0x6665, 0xFCB7, 0x6666, 0xFCE4, 0x6667, 0xFBC5, 0x6668, 0xE3E7, 0x6669, 0xD8B9,
+ 0x666B, 0xF6F8, 0x666E, 0xDCC5, 0x666F, 0xCCD8, 0x6673, 0xE0AF, 0x6674, 0xF4E7, 0x6676, 0xEFDC, 0x6677, 0xCFFC, 0x6678, 0xEFDD,
+ 0x667A, 0xF2AA, 0x6684, 0xFDBE, 0x6687, 0xCAAC, 0x6688, 0xFDBB, 0x6689, 0xFDC7, 0x668E, 0xE7B2, 0x6690, 0xEAD1, 0x6691, 0xDFF4,
+ 0x6696, 0xD1EC, 0x6697, 0xE4DE, 0x6698, 0xE5C3, 0x669D, 0xD9A6, 0x66A0, 0xCDBC, 0x66A2, 0xF3E5, 0x66AB, 0xEDD5, 0x66AE, 0xD9BA,
+ 0x66B2, 0xEDE7, 0x66B3, 0xFBB5, 0x66B4, 0xF8EC, 0x66B9, 0xE0E7, 0x66BB, 0xCCD9, 0x66BE, 0xD4C6, 0x66C4, 0xE7A5, 0x66C6, 0xD5F5,
+ 0x66C7, 0xD3BE, 0x66C9, 0xFCFB, 0x66D6, 0xE4F2, 0x66D9, 0xDFF5, 0x66DC, 0xE8F8, 0x66DD, 0xF8ED, 0x66E0, 0xCEC7, 0x66E6, 0xFDF6,
+ 0x66F0, 0xE8D8, 0x66F2, 0xCDD8, 0x66F3, 0xE7D6, 0x66F4, 0xCCDA, 0x66F7, 0xCAE3, 0x66F8, 0xDFF6, 0x66F9, 0xF0C7, 0x66FA, 0xF0C6,
+ 0x66FC, 0xD8BA, 0x66FE, 0xF1F4, 0x66FF, 0xF4F0, 0x6700, 0xF5CC, 0x6703, 0xFCE5, 0x6708, 0xEAC5, 0x6709, 0xEAF3, 0x670B, 0xDDDB,
+ 0x670D, 0xDCD7, 0x6714, 0xDEFD, 0x6715, 0xF2F9, 0x6717, 0xD5C7, 0x671B, 0xD8D0, 0x671D, 0xF0C8, 0x671E, 0xD1A1, 0x671F, 0xD1A2,
+ 0x6726, 0xD9D4, 0x6727, 0xD6E8, 0x6728, 0xD9CA, 0x672A, 0xDAB1, 0x672B, 0xD8C7, 0x672C, 0xDCE2, 0x672D, 0xF3CE, 0x672E, 0xF5F4,
+ 0x6731, 0xF1B9, 0x6734, 0xDAD3, 0x6736, 0xF6EA, 0x673A, 0xCFF5, 0x673D, 0xFDAE, 0x6746, 0xCAD2, 0x6749, 0xDFB4, 0x674E, 0xD7DD,
+ 0x674F, 0xFABA, 0x6750, 0xEEA7, 0x6751, 0xF5BD, 0x6753, 0xF8F5, 0x6756, 0xEDE8, 0x675C, 0xD4E1, 0x675E, 0xD1A3, 0x675F, 0xE1D6,
+ 0x676D, 0xF9F8, 0x676F, 0xDBCA, 0x6770, 0xCBF9, 0x6771, 0xD4D4, 0x6773, 0xD9DC, 0x6775, 0xEEBE, 0x6777, 0xF7ED, 0x677B, 0xD2EE,
+ 0x677E, 0xE1E6, 0x677F, 0xF7F9, 0x6787, 0xDDED, 0x6789, 0xE8DB, 0x678B, 0xDBB3, 0x678F, 0xD1F7, 0x6790, 0xE0B0, 0x6793, 0xD4E2,
+ 0x6795, 0xF6D7, 0x6797, 0xD7F9, 0x679A, 0xD8DD, 0x679C, 0xCDFD, 0x679D, 0xF2AB, 0x67AF, 0xCDBD, 0x67B0, 0xF8C2, 0x67B3, 0xF2AC,
+ 0x67B6, 0xCAAD, 0x67B7, 0xCAAE, 0x67B8, 0xCFAE, 0x67BE, 0xE3C2, 0x67C4, 0xDCB7, 0x67CF, 0xDBDA, 0x67D0, 0xD9BB, 0x67D1, 0xCAF3,
+ 0x67D2, 0xF6D3, 0x67D3, 0xE6F8, 0x67D4, 0xEAF5, 0x67DA, 0xEAF6, 0x67DD, 0xF6F9, 0x67E9, 0xCFAF, 0x67EC, 0xCAD3, 0x67EF, 0xCAAF,
+ 0x67F0, 0xD2B0, 0x67F1, 0xF1BA, 0x67F3, 0xD7B3, 0x67F4, 0xE3C3, 0x67F5, 0xF3FD, 0x67F6, 0xDEDA, 0x67FB, 0xDEDB, 0x67FE, 0xEFDE,
+ 0x6812, 0xE2E3, 0x6813, 0xEEFB, 0x6816, 0xDFF7, 0x6817, 0xD7CA, 0x6821, 0xCEE8, 0x6822, 0xDBDB, 0x682A, 0xF1BB, 0x682F, 0xE9F1,
+ 0x6838, 0xFAB7, 0x6839, 0xD0C6, 0x683C, 0xCCAB, 0x683D, 0xEEA8, 0x6840, 0xCBFA, 0x6841, 0xF9F9, 0x6842, 0xCCFD, 0x6843, 0xD3FE,
+ 0x6848, 0xE4D0, 0x684E, 0xF2EE, 0x6850, 0xD4D5, 0x6851, 0xDFCD, 0x6853, 0xFCB8, 0x6854, 0xD1D0, 0x686D, 0xF2CD, 0x6876, 0xF7D2,
+ 0x687F, 0xCAD4, 0x6881, 0xD5D9, 0x6885, 0xD8DE, 0x688F, 0xCDD9, 0x6893, 0xEEA9, 0x6894, 0xF6BC, 0x6897, 0xCCDB, 0x689D, 0xF0C9,
+ 0x689F, 0xFCFC, 0x68A1, 0xE8C9, 0x68A2, 0xF4FE, 0x68A7, 0xE7FC, 0x68A8, 0xD7DE, 0x68AD, 0xDEDC, 0x68AF, 0xF0AC, 0x68B0, 0xCCFE,
+ 0x68B1, 0xCDE1, 0x68B3, 0xE1BA, 0x68B5, 0xDBEF, 0x68B6, 0xDAB2, 0x68C4, 0xD1A5, 0x68C5, 0xDCB8, 0x68C9, 0xD8F6, 0x68CB, 0xD1A4,
+ 0x68CD, 0xCDE2, 0x68D2, 0xDCEA, 0x68D5, 0xF0F7, 0x68D7, 0xF0CA, 0x68D8, 0xD0BE, 0x68DA, 0xDDDC, 0x68DF, 0xD4D6, 0x68E0, 0xD3D6,
+ 0x68E7, 0xEDD0, 0x68E8, 0xCDA1, 0x68EE, 0xDFB5, 0x68F2, 0xDFF8, 0x68F9, 0xD4A1, 0x68FA, 0xCEB2, 0x6900, 0xE8CA, 0x6905, 0xEBF5,
+ 0x690D, 0xE3D5, 0x690E, 0xF5D0, 0x6912, 0xF5A1, 0x6927, 0xD9A7, 0x6930, 0xE5AB, 0x693D, 0xE6CB, 0x693F, 0xF5F1, 0x694A, 0xE5C5,
+ 0x6953, 0xF9A3, 0x6954, 0xE0DB, 0x6955, 0xF6EB, 0x6957, 0xCBF1, 0x6959, 0xD9EA, 0x695A, 0xF5A2, 0x695E, 0xD7D1, 0x6960, 0xD1F8,
+ 0x6961, 0xEAF8, 0x6962, 0xEAF9, 0x6963, 0xDAB3, 0x6968, 0xEFDF, 0x696B, 0xF1EF, 0x696D, 0xE5F6, 0x696E, 0xEEBF, 0x696F, 0xE2E4,
+ 0x6975, 0xD0BF, 0x6977, 0xFAAC, 0x6978, 0xF5D1, 0x6979, 0xE7B3, 0x6995, 0xE9BE, 0x699B, 0xF2CE, 0x699C, 0xDBB4, 0x69A5, 0xFCCE,
+ 0x69A7, 0xDDEE, 0x69AE, 0xE7B4, 0x69B4, 0xD7B4, 0x69BB, 0xF7B4, 0x69C1, 0xCDBE, 0x69C3, 0xDAE9, 0x69CB, 0xCFB0, 0x69CC, 0xF7D9,
+ 0x69CD, 0xF3E6, 0x69D0, 0xCED9, 0x69E8, 0xCEAA, 0x69EA, 0xCBC8, 0x69FB, 0xD0A7, 0x69FD, 0xF0CB, 0x69FF, 0xD0C7, 0x6A02, 0xE4C5,
+ 0x6A0A, 0xDBE0, 0x6A11, 0xD5DA, 0x6A13, 0xD7A7, 0x6A17, 0xEEC0, 0x6A19, 0xF8F6, 0x6A1E, 0xF5D2, 0x6A1F, 0xEDE9, 0x6A21, 0xD9BC,
+ 0x6A23, 0xE5C6, 0x6A35, 0xF5A3, 0x6A38, 0xDAD4, 0x6A39, 0xE2A7, 0x6A3A, 0xFBFC, 0x6A3D, 0xF1DC, 0x6A44, 0xCAF4, 0x6A48, 0xE8FA,
+ 0x6A4B, 0xCEE9, 0x6A52, 0xE9F8, 0x6A53, 0xE2E5, 0x6A58, 0xD0B9, 0x6A59, 0xD4F2, 0x6A5F, 0xD1A6, 0x6A61, 0xDFCE, 0x6A6B, 0xFCF4,
+ 0x6A80, 0xD3AA, 0x6A84, 0xCCAC, 0x6A89, 0xEFE0, 0x6A8D, 0xE5E5, 0x6A8E, 0xD0D5, 0x6A97, 0xDBFC, 0x6A9C, 0xFCE6, 0x6AA2, 0xCBFE,
+ 0x6AA3, 0xEDEA, 0x6AB3, 0xDEB1, 0x6ABB, 0xF9E3, 0x6AC2, 0xD4A2, 0x6AC3, 0xCFF6, 0x6AD3, 0xD6D0, 0x6ADA, 0xD5EA, 0x6ADB, 0xF1EE,
+ 0x6AF6, 0xFACB, 0x6AFB, 0xE5A1, 0x6B04, 0xD5B1, 0x6B0A, 0xCFED, 0x6B0C, 0xEDEB, 0x6B12, 0xD5B2, 0x6B16, 0xD5BC, 0x6B20, 0xFDE2,
+ 0x6B21, 0xF3AD, 0x6B23, 0xFDDB, 0x6B32, 0xE9B0, 0x6B3A, 0xD1A7, 0x6B3D, 0xFDE3, 0x6B3E, 0xCEB3, 0x6B46, 0xFDE4, 0x6B47, 0xFACE,
+ 0x6B4C, 0xCAB0, 0x6B4E, 0xF7A7, 0x6B50, 0xCFB1, 0x6B5F, 0xE6A2, 0x6B61, 0xFCB6, 0x6B62, 0xF2AD, 0x6B63, 0xEFE1, 0x6B64, 0xF3AE,
+ 0x6B65, 0xDCC6, 0x6B66, 0xD9EB, 0x6B6A, 0xE8E0, 0x6B72, 0xE1A8, 0x6B77, 0xD5F6, 0x6B78, 0xCFFD, 0x6B7B, 0xDEDD, 0x6B7F, 0xD9D1,
+ 0x6B83, 0xE4EA, 0x6B84, 0xF2CF, 0x6B86, 0xF7BF, 0x6B89, 0xE2E6, 0x6B8A, 0xE2A8, 0x6B96, 0xE3D6, 0x6B98, 0xEDD1, 0x6B9E, 0xE9F9,
+ 0x6BAE, 0xD6B1, 0x6BAF, 0xDEB2, 0x6BB2, 0xE0E8, 0x6BB5, 0xD3AB, 0x6BB7, 0xEBDC, 0x6BBA, 0xDFAF, 0x6BBC, 0xCAC3, 0x6BBF, 0xEEFC,
+ 0x6BC1, 0xFDC3, 0x6BC5, 0xEBF6, 0x6BC6, 0xCFB2, 0x6BCB, 0xD9EC, 0x6BCD, 0xD9BD, 0x6BCF, 0xD8DF, 0x6BD2, 0xD4B8, 0x6BD3, 0xEBBE,
+ 0x6BD4, 0xDDEF, 0x6BD6, 0xDDF0, 0x6BD7, 0xDDF1, 0x6BD8, 0xDDF2, 0x6BDB, 0xD9BE, 0x6BEB, 0xFBC6, 0x6BEC, 0xCFB3, 0x6C08, 0xEEFD,
+ 0x6C0F, 0xE4AB, 0x6C11, 0xDAC5, 0x6C13, 0xD8EC, 0x6C23, 0xD1A8, 0x6C34, 0xE2A9, 0x6C37, 0xDEBC, 0x6C38, 0xE7B5, 0x6C3E, 0xDBF0,
+ 0x6C40, 0xEFE2, 0x6C41, 0xF1F0, 0x6C42, 0xCFB4, 0x6C4E, 0xDBF1, 0x6C50, 0xE0B1, 0x6C55, 0xDFA5, 0x6C57, 0xF9D2, 0x6C5A, 0xE7FD,
+ 0x6C5D, 0xE6A3, 0x6C5E, 0xFBF1, 0x6C5F, 0xCBB0, 0x6C60, 0xF2AE, 0x6C68, 0xCDE7, 0x6C6A, 0xE8DC, 0x6C6D, 0xE7D7, 0x6C70, 0xF7C0,
+ 0x6C72, 0xD0E3, 0x6C76, 0xDAA1, 0x6C7A, 0xCCBD, 0x6C7D, 0xD1A9, 0x6C7E, 0xDDCC, 0x6C81, 0xE3FE, 0x6C82, 0xD1AA, 0x6C83, 0xE8AA,
+ 0x6C85, 0xEAB6, 0x6C86, 0xF9FA, 0x6C87, 0xE6CC, 0x6C88, 0xF6D8, 0x6C8C, 0xD4C7, 0x6C90, 0xD9CB, 0x6C92, 0xD9D2, 0x6C93, 0xD3CB,
+ 0x6C94, 0xD8F7, 0x6C95, 0xDAA9, 0x6C96, 0xF5F8, 0x6C99, 0xDEDE, 0x6C9A, 0xF2AF, 0x6C9B, 0xF8A9, 0x6CAB, 0xD8C8, 0x6CAE, 0xEEC1,
+ 0x6CB3, 0xF9C1, 0x6CB8, 0xDDF3, 0x6CB9, 0xEAFA, 0x6CBB, 0xF6BD, 0x6CBC, 0xE1BB, 0x6CBD, 0xCDBF, 0x6CBE, 0xF4D4, 0x6CBF, 0xE6CD,
+ 0x6CC1, 0xFCCF, 0x6CC2, 0xFBA2, 0x6CC4, 0xE0DC, 0x6CC9, 0xF4BB, 0x6CCA, 0xDAD5, 0x6CCC, 0xF9B2, 0x6CD3, 0xFBF2, 0x6CD5, 0xDBF6,
+ 0x6CD7, 0xDEDF, 0x6CDB, 0xDBF2, 0x6CE1, 0xF8DC, 0x6CE2, 0xF7EE, 0x6CE3, 0xEBE8, 0x6CE5, 0xD2FA, 0x6CE8, 0xF1BC, 0x6CEB, 0xFADA,
+ 0x6CEE, 0xDAEA, 0x6CEF, 0xDAC6, 0x6CF0, 0xF7C1, 0x6CF3, 0xE7B6, 0x6D0B, 0xE5C7, 0x6D0C, 0xD6AC, 0x6D11, 0xDCC7, 0x6D17, 0xE1A9,
+ 0x6D19, 0xE2AA, 0x6D1B, 0xD5A6, 0x6D1E, 0xD4D7, 0x6D25, 0xF2D0, 0x6D27, 0xEAFB, 0x6D29, 0xE0DD, 0x6D2A, 0xFBF3, 0x6D32, 0xF1BD,
+ 0x6D35, 0xE2E7, 0x6D36, 0xFDD7, 0x6D38, 0xCEC8, 0x6D39, 0xEAB7, 0x6D3B, 0xFCC0, 0x6D3D, 0xFDE7, 0x6D3E, 0xF7EF, 0x6D41, 0xD7B5,
+ 0x6D59, 0xEFBA, 0x6D5A, 0xF1DD, 0x6D5C, 0xDEB3, 0x6D63, 0xE8CB, 0x6D66, 0xF8DD, 0x6D69, 0xFBC7, 0x6D6A, 0xD5C8, 0x6D6C, 0xD7DF,
+ 0x6D6E, 0xDDA9, 0x6D74, 0xE9B1, 0x6D77, 0xFAAD, 0x6D78, 0xF6D9, 0x6D79, 0xFAF4, 0x6D7F, 0xF8AA, 0x6D85, 0xE6EE, 0x6D87, 0xCCDC,
+ 0x6D88, 0xE1BC, 0x6D89, 0xE0EF, 0x6D8C, 0xE9BF, 0x6D8D, 0xFCFD, 0x6D8E, 0xE6CE, 0x6D91, 0xE1D7, 0x6D93, 0xE6CF, 0x6D95, 0xF4F1,
+ 0x6DAF, 0xE4F3, 0x6DB2, 0xE4FB, 0x6DB5, 0xF9E4, 0x6DC0, 0xEFE3, 0x6DC3, 0xCFEE, 0x6DC4, 0xF6BE, 0x6DC5, 0xE0B2, 0x6DC6, 0xFCFE,
+ 0x6DC7, 0xD1AB, 0x6DCB, 0xD7FA, 0x6DCF, 0xFBC8, 0x6DD1, 0xE2D7, 0x6DD8, 0xD4A3, 0x6DD9, 0xF0F8, 0x6DDA, 0xD7A8, 0x6DDE, 0xE1E7,
+ 0x6DE1, 0xD3BF, 0x6DE8, 0xEFE4, 0x6DEA, 0xD7C5, 0x6DEB, 0xEBE2, 0x6DEE, 0xFCE7, 0x6DF1, 0xE4A2, 0x6DF3, 0xE2E8, 0x6DF5, 0xE6D0,
+ 0x6DF7, 0xFBE8, 0x6DF8, 0xF4E8, 0x6DF9, 0xE5F4, 0x6DFA, 0xF4BC, 0x6DFB, 0xF4D5, 0x6E17, 0xDFB6, 0x6E19, 0xFCB9, 0x6E1A, 0xEEC2,
+ 0x6E1B, 0xCAF5, 0x6E1F, 0xEFE5, 0x6E20, 0xCBE2, 0x6E21, 0xD4A4, 0x6E23, 0xDEE0, 0x6E24, 0xDAFD, 0x6E25, 0xE4C6, 0x6E26, 0xE8BE,
+ 0x6E2B, 0xE0DE, 0x6E2C, 0xF6B4, 0x6E2D, 0xEAD2, 0x6E2F, 0xF9FB, 0x6E32, 0xE0C2, 0x6E34, 0xCAE4, 0x6E36, 0xE7B7, 0x6E38, 0xEAFD,
+ 0x6E3A, 0xD9DD, 0x6E3C, 0xDAB4, 0x6E3D, 0xEEAA, 0x6E3E, 0xFBE9, 0x6E43, 0xDBCB, 0x6E44, 0xDAB5, 0x6E4A, 0xF1BE, 0x6E4D, 0xD3AC,
+ 0x6E56, 0xFBC9, 0x6E58, 0xDFCF, 0x6E5B, 0xD3C0, 0x6E5C, 0xE3D7, 0x6E5E, 0xEFE6, 0x6E5F, 0xFCD0, 0x6E67, 0xE9C0, 0x6E6B, 0xF5D3,
+ 0x6E6E, 0xECDC, 0x6E6F, 0xF7B7, 0x6E72, 0xEAB8, 0x6E73, 0xD1F9, 0x6E7A, 0xDCC8, 0x6E90, 0xEAB9, 0x6E96, 0xF1DE, 0x6E9C, 0xD7B6,
+ 0x6E9D, 0xCFB5, 0x6E9F, 0xD9A8, 0x6EA2, 0xECEE, 0x6EA5, 0xDDAA, 0x6EAA, 0xCDA2, 0x6EAB, 0xE8AE, 0x6EAF, 0xE1BD, 0x6EB1, 0xF2D1,
+ 0x6EB6, 0xE9C1, 0x6EBA, 0xD2FC, 0x6EC2, 0xDBB5, 0x6EC4, 0xF3E7, 0x6EC5, 0xD8FE, 0x6EC9, 0xFCD1, 0x6ECB, 0xEDB2, 0x6ECC, 0xF4AF,
+ 0x6ECE, 0xFBA3, 0x6ED1, 0xFCC1, 0x6ED3, 0xEEAB, 0x6ED4, 0xD4A5, 0x6EEF, 0xF4F2, 0x6EF4, 0xEED9, 0x6EF8, 0xFBCA, 0x6EFE, 0xCDE3,
+ 0x6EFF, 0xD8BB, 0x6F01, 0xE5DB, 0x6F02, 0xF8F7, 0x6F06, 0xF6D4, 0x6F0F, 0xD7A9, 0x6F11, 0xCBC9, 0x6F14, 0xE6D1, 0x6F15, 0xF0CC,
+ 0x6F20, 0xD8AE, 0x6F22, 0xF9D3, 0x6F23, 0xD5FE, 0x6F2B, 0xD8BC, 0x6F2C, 0xF2B0, 0x6F31, 0xE2AB, 0x6F32, 0xF3E8, 0x6F38, 0xEFC2,
+ 0x6F3F, 0xEDEC, 0x6F41, 0xE7B8, 0x6F51, 0xDAFE, 0x6F54, 0xCCBE, 0x6F57, 0xF2FC, 0x6F58, 0xDAEB, 0x6F5A, 0xE2D8, 0x6F5B, 0xEDD6,
+ 0x6F5E, 0xD6D1, 0x6F5F, 0xE0B3, 0x6F62, 0xFCD2, 0x6F64, 0xEBC8, 0x6F6D, 0xD3C1, 0x6F6E, 0xF0CD, 0x6F70, 0xCFF7, 0x6F7A, 0xEDD2,
+ 0x6F7C, 0xD4D8, 0x6F7D, 0xDCC9, 0x6F7E, 0xD7F1, 0x6F81, 0xDFBB, 0x6F84, 0xF3A5, 0x6F88, 0xF4CD, 0x6F8D, 0xF1BF, 0x6F8E, 0xF8B1,
+ 0x6F90, 0xE9FA, 0x6F94, 0xFBCB, 0x6F97, 0xCAD5, 0x6FA3, 0xF9D4, 0x6FA4, 0xF7CA, 0x6FA7, 0xD6C8, 0x6FAE, 0xFCE8, 0x6FAF, 0xF3BD,
+ 0x6FB1, 0xEEFE, 0x6FB3, 0xE7FE, 0x6FB9, 0xD3C2, 0x6FBE, 0xD3B6, 0x6FC0, 0xCCAD, 0x6FC1, 0xF6FA, 0x6FC2, 0xD6B2, 0x6FC3, 0xD2D8,
+ 0x6FCA, 0xE7D8, 0x6FD5, 0xE3A5, 0x6FDA, 0xE7B9, 0x6FDF, 0xF0AD, 0x6FE0, 0xFBCC, 0x6FE1, 0xEBA1, 0x6FE4, 0xD4A6, 0x6FE9, 0xFBCD,
+ 0x6FEB, 0xD5BD, 0x6FEC, 0xF1DF, 0x6FEF, 0xF6FB, 0x6FF1, 0xDEB4, 0x6FFE, 0xD5EB, 0x7001, 0xE5C8, 0x7005, 0xFBA4, 0x7006, 0xD4B9,
+ 0x7009, 0xDEE1, 0x700B, 0xE4A3, 0x700F, 0xD7B7, 0x7011, 0xF8EE, 0x7015, 0xDEB5, 0x7018, 0xD6D2, 0x701A, 0xF9D5, 0x701B, 0xE7BA,
+ 0x701C, 0xEBD5, 0x701D, 0xD5F7, 0x701E, 0xEFE7, 0x701F, 0xE1BE, 0x7023, 0xFAAE, 0x7027, 0xD6E9, 0x7028, 0xD6EE, 0x702F, 0xE7BB,
+ 0x7037, 0xECCB, 0x703E, 0xD5B3, 0x704C, 0xCEB4, 0x7050, 0xFBA5, 0x7051, 0xE1EE, 0x7058, 0xF7A8, 0x705D, 0xFBCE, 0x7063, 0xD8BD,
+ 0x706B, 0xFBFD, 0x7070, 0xFCE9, 0x7078, 0xCFB6, 0x707C, 0xEDC7, 0x707D, 0xEEAC, 0x7085, 0xCCDD, 0x708A, 0xF6A7, 0x708E, 0xE6FA,
+ 0x7092, 0xF5A4, 0x7098, 0xFDDC, 0x7099, 0xEDB3, 0x709A, 0xCEC9, 0x70A1, 0xEFE8, 0x70A4, 0xE1BF, 0x70AB, 0xFADB, 0x70AC, 0xCBE3,
+ 0x70AD, 0xF7A9, 0x70AF, 0xFBA6, 0x70B3, 0xDCB9, 0x70B7, 0xF1C0, 0x70B8, 0xEDC8, 0x70B9, 0xEFC3, 0x70C8, 0xD6AD, 0x70CB, 0xFDCE,
+ 0x70CF, 0xE8A1, 0x70D8, 0xFBF4, 0x70D9, 0xD5A7, 0x70DD, 0xF1F6, 0x70DF, 0xE6D3, 0x70F1, 0xCCDE, 0x70F9, 0xF8B2, 0x70FD, 0xDCEB,
+ 0x7104, 0xFDB6, 0x7109, 0xE5EA, 0x710C, 0xF1E0, 0x7119, 0xDBCC, 0x711A, 0xDDCD, 0x711E, 0xD4C8, 0x7121, 0xD9ED, 0x7126, 0xF5A5,
+ 0x7130, 0xE6FB, 0x7136, 0xE6D4, 0x7147, 0xFDC8, 0x7149, 0xD6A1, 0x714A, 0xFDBF, 0x714C, 0xFCD3, 0x714E, 0xEFA1, 0x7150, 0xE7BC,
+ 0x7156, 0xD1EE, 0x7159, 0xE6D5, 0x715C, 0xE9F2, 0x715E, 0xDFB0, 0x7164, 0xD8E0, 0x7165, 0xFCBA, 0x7166, 0xFDAF, 0x7167, 0xF0CE,
+ 0x7169, 0xDBE1, 0x716C, 0xE5C9, 0x716E, 0xEDB4, 0x717D, 0xE0C3, 0x7184, 0xE3D8, 0x7189, 0xE9FB, 0x718A, 0xEAA8, 0x718F, 0xFDB7,
+ 0x7192, 0xFBA7, 0x7194, 0xE9C2, 0x7199, 0xFDF7, 0x719F, 0xE2D9, 0x71A2, 0xDCEC, 0x71AC, 0xE8A2, 0x71B1, 0xE6F0, 0x71B9, 0xFDF8,
+ 0x71BA, 0xFDF9, 0x71BE, 0xF6BF, 0x71C1, 0xE7A7, 0x71C3, 0xE6D7, 0x71C8, 0xD4F3, 0x71C9, 0xD4C9, 0x71CE, 0xD6FA, 0x71D0, 0xD7F2,
+ 0x71D2, 0xE1C0, 0x71D4, 0xDBE2, 0x71D5, 0xE6D8, 0x71DF, 0xE7BD, 0x71E5, 0xF0CF, 0x71E6, 0xF3BE, 0x71E7, 0xE2AC, 0x71ED, 0xF5B7,
+ 0x71EE, 0xE0F0, 0x71FB, 0xFDB8, 0x71FC, 0xE3E8, 0x71FE, 0xD4A7, 0x71FF, 0xE8FC, 0x7200, 0xFAD2, 0x7206, 0xF8EF, 0x7210, 0xD6D3,
+ 0x721B, 0xD5B4, 0x722A, 0xF0D0, 0x722C, 0xF7F0, 0x722D, 0xEEB3, 0x7230, 0xEABA, 0x7232, 0xEAD3, 0x7235, 0xEDC9, 0x7236, 0xDDAB,
+ 0x723A, 0xE5AC, 0x723B, 0xFDA1, 0x723D, 0xDFD0, 0x723E, 0xECB3, 0x7240, 0xDFD1, 0x7246, 0xEDED, 0x7247, 0xF8B8, 0x7248, 0xF7FA,
+ 0x724C, 0xF8AB, 0x7252, 0xF4E0, 0x7258, 0xD4BA, 0x7259, 0xE4B3, 0x725B, 0xE9DA, 0x725D, 0xDEB6, 0x725F, 0xD9BF, 0x7261, 0xD9C0,
+ 0x7262, 0xD6EF, 0x7267, 0xD9CC, 0x7269, 0xDAAA, 0x7272, 0xDFE5, 0x7279, 0xF7E5, 0x727D, 0xCCB2, 0x7280, 0xDFF9, 0x7281, 0xD7E0,
+ 0x72A2, 0xD4BB, 0x72A7, 0xFDFA, 0x72AC, 0xCCB3, 0x72AF, 0xDBF3, 0x72C0, 0xDFD2, 0x72C2, 0xCECA, 0x72C4, 0xEEDA, 0x72CE, 0xE4E4,
+ 0x72D0, 0xFBCF, 0x72D7, 0xCFB7, 0x72D9, 0xEEC3, 0x72E1, 0xCEEA, 0x72E9, 0xE2AD, 0x72F8, 0xD7E1, 0x72F9, 0xFAF5, 0x72FC, 0xD5C9,
+ 0x72FD, 0xF8AC, 0x730A, 0xE7D9, 0x7316, 0xF3E9, 0x731B, 0xD8ED, 0x731C, 0xE3C4, 0x731D, 0xF0F1, 0x7325, 0xE8E5, 0x7329, 0xE0FA,
+ 0x732A, 0xEEC4, 0x732B, 0xD9DE, 0x7336, 0xEBA2, 0x7337, 0xEBA3, 0x733E, 0xFCC2, 0x733F, 0xEABB, 0x7344, 0xE8AB, 0x7345, 0xDEE2,
+ 0x7350, 0xEDEF, 0x7352, 0xE8A3, 0x7357, 0xCFF1, 0x7368, 0xD4BC, 0x736A, 0xFCEA, 0x7370, 0xE7BE, 0x7372, 0xFCF2, 0x7375, 0xD6B4,
+ 0x7378, 0xE2AE, 0x737A, 0xD3B7, 0x737B, 0xFACC, 0x7384, 0xFADC, 0x7386, 0xEDB5, 0x7387, 0xE1E3, 0x7389, 0xE8AC, 0x738B, 0xE8DD,
+ 0x738E, 0xEFE9, 0x7394, 0xF4BD, 0x7396, 0xCFB8, 0x7397, 0xE9DB, 0x7398, 0xD1AC, 0x739F, 0xDAC7, 0x73A7, 0xEBC9, 0x73A9, 0xE8CC,
+ 0x73AD, 0xDEB7, 0x73B2, 0xD6BC, 0x73B3, 0xD3E5, 0x73B9, 0xFADD, 0x73C0, 0xDAD6, 0x73C2, 0xCAB1, 0x73C9, 0xDAC8, 0x73CA, 0xDFA6,
+ 0x73CC, 0xF9B3, 0x73CD, 0xF2D2, 0x73CF, 0xCAC4, 0x73D6, 0xCECB, 0x73D9, 0xCDF5, 0x73DD, 0xFDB0, 0x73DE, 0xD5A8, 0x73E0, 0xF1C1,
+ 0x73E3, 0xE2E9, 0x73E4, 0xDCCA, 0x73E5, 0xECB4, 0x73E6, 0xFAC0, 0x73E9, 0xFBA8, 0x73EA, 0xD0A8, 0x73ED, 0xDAEC, 0x73F7, 0xD9EE,
+ 0x73F9, 0xE0FB, 0x73FD, 0xEFEA, 0x73FE, 0xFADE, 0x7401, 0xE0C4, 0x7403, 0xCFB9, 0x7405, 0xD5CA, 0x7406, 0xD7E2, 0x7407, 0xE2AF,
+ 0x7409, 0xD7B8, 0x7413, 0xE8CD, 0x741B, 0xF6DA, 0x7420, 0xEFA2, 0x7421, 0xE2DA, 0x7422, 0xF6FC, 0x7425, 0xFBD0, 0x7426, 0xD1AD,
+ 0x7428, 0xCDE4, 0x742A, 0xD1AE, 0x742B, 0xDCED, 0x742C, 0xE8CE, 0x742E, 0xF0F9, 0x742F, 0xCEB5, 0x7430, 0xE6FC, 0x7433, 0xD7FB,
+ 0x7434, 0xD0D6, 0x7435, 0xDDF5, 0x7436, 0xF7F1, 0x7438, 0xF6FD, 0x743A, 0xDBF7, 0x743F, 0xFBEA, 0x7440, 0xE9DC, 0x7441, 0xD9C1,
+ 0x7443, 0xF5F2, 0x7444, 0xE0C5, 0x744B, 0xEAD4, 0x7455, 0xF9C2, 0x7457, 0xEABC, 0x7459, 0xD2C5, 0x745A, 0xFBD1, 0x745B, 0xE7C0,
+ 0x745C, 0xEBA5, 0x745E, 0xDFFA, 0x745F, 0xE3A2, 0x7460, 0xD7B9, 0x7462, 0xE9C3, 0x7464, 0xE8FD, 0x7465, 0xE8AF, 0x7468, 0xF2D3,
+ 0x7469, 0xFBA9, 0x746A, 0xD8A5, 0x746F, 0xD5CB, 0x747E, 0xD0C8, 0x7482, 0xD1AF, 0x7483, 0xD7E3, 0x7487, 0xE0C6, 0x7489, 0xD6A2,
+ 0x748B, 0xEDF0, 0x7498, 0xD7F3, 0x749C, 0xFCD4, 0x749E, 0xDAD7, 0x749F, 0xCCDF, 0x74A1, 0xF2D4, 0x74A3, 0xD1B0, 0x74A5, 0xCCE0,
+ 0x74A7, 0xDBFD, 0x74A8, 0xF3BF, 0x74AA, 0xF0D1, 0x74B0, 0xFCBB, 0x74B2, 0xE2B0, 0x74B5, 0xE6A5, 0x74B9, 0xE2DB, 0x74BD, 0xDFDE,
+ 0x74BF, 0xE0C7, 0x74C6, 0xF2EF, 0x74CA, 0xCCE1, 0x74CF, 0xD6EA, 0x74D4, 0xE7C2, 0x74D8, 0xCEB6, 0x74DA, 0xF3C0, 0x74DC, 0xCDFE,
+ 0x74E0, 0xFBD2, 0x74E2, 0xF8F8, 0x74E3, 0xF7FB, 0x74E6, 0xE8BF, 0x74EE, 0xE8B7, 0x74F7, 0xEDB6, 0x7501, 0xDCBA, 0x7504, 0xCCB4,
+ 0x7511, 0xF1F7, 0x7515, 0xE8B8, 0x7518, 0xCAF6, 0x751A, 0xE4A4, 0x751B, 0xF4D6, 0x751F, 0xDFE6, 0x7523, 0xDFA7, 0x7525, 0xDFE7,
+ 0x7526, 0xE1C1, 0x7528, 0xE9C4, 0x752B, 0xDCCB, 0x752C, 0xE9C5, 0x7530, 0xEFA3, 0x7531, 0xEBA6, 0x7532, 0xCBA3, 0x7533, 0xE3E9,
+ 0x7537, 0xD1FB, 0x7538, 0xEFA4, 0x753A, 0xEFEB, 0x7547, 0xD0B4, 0x754C, 0xCDA3, 0x754F, 0xE8E6, 0x7551, 0xEFA5, 0x7553, 0xD3CC,
+ 0x7554, 0xDAED, 0x7559, 0xD7BA, 0x755B, 0xF2D5, 0x755C, 0xF5E5, 0x755D, 0xD9EF, 0x7562, 0xF9B4, 0x7565, 0xD5D4, 0x7566, 0xFDCF,
+ 0x756A, 0xDBE3, 0x756F, 0xF1E1, 0x7570, 0xECB6, 0x7575, 0xFBFE, 0x7576, 0xD3D7, 0x7578, 0xD1B1, 0x757A, 0xCBB1, 0x757F, 0xD1B2,
+ 0x7586, 0xCBB2, 0x7587, 0xF1C2, 0x758A, 0xF4E1, 0x758B, 0xF9B5, 0x758E, 0xE1C3, 0x758F, 0xE1C2, 0x7591, 0xEBF7, 0x759D, 0xDFA8,
+ 0x75A5, 0xCBCA, 0x75AB, 0xE6B9, 0x75B1, 0xF8DE, 0x75B2, 0xF9AA, 0x75B3, 0xCAF7, 0x75B5, 0xEDB7, 0x75B8, 0xD3B8, 0x75B9, 0xF2D6,
+ 0x75BC, 0xD4D9, 0x75BD, 0xEEC5, 0x75BE, 0xF2F0, 0x75C2, 0xCAB2, 0x75C5, 0xDCBB, 0x75C7, 0xF1F8, 0x75CD, 0xECB7, 0x75D2, 0xE5CA,
+ 0x75D4, 0xF6C0, 0x75D5, 0xFDDD, 0x75D8, 0xD4E3, 0x75D9, 0xCCE2, 0x75DB, 0xF7D4, 0x75E2, 0xD7E5, 0x75F0, 0xD3C3, 0x75F2, 0xD8A6,
+ 0x75F4, 0xF6C1, 0x75FA, 0xDDF6, 0x75FC, 0xCDC0, 0x7600, 0xE5DC, 0x760D, 0xE5CB, 0x7619, 0xE1C4, 0x761F, 0xE8B0, 0x7620, 0xF4B0,
+ 0x7621, 0xF3EA, 0x7622, 0xDAEE, 0x7624, 0xD7BB, 0x7626, 0xE2B1, 0x763B, 0xD7AA, 0x7642, 0xD6FB, 0x764C, 0xE4DF, 0x764E, 0xCAD6,
+ 0x7652, 0xEBA8, 0x7656, 0xDBFE, 0x7661, 0xF6C2, 0x7664, 0xEFBB, 0x7669, 0xD4FD, 0x766C, 0xE0C8, 0x7670, 0xE8B9, 0x7672, 0xEFA6,
+ 0x7678, 0xCDA4, 0x767B, 0xD4F4, 0x767C, 0xDBA1, 0x767D, 0xDBDC, 0x767E, 0xDBDD, 0x7684, 0xEEDC, 0x7686, 0xCBCB, 0x7687, 0xFCD5,
+ 0x768E, 0xCEEB, 0x7690, 0xCDC1, 0x7693, 0xFBD3, 0x76AE, 0xF9AB, 0x76BA, 0xF5D4, 0x76BF, 0xD9A9, 0x76C2, 0xE9DD, 0x76C3, 0xDBCD,
+ 0x76C6, 0xDDCE, 0x76C8, 0xE7C3, 0x76CA, 0xECCC, 0x76D2, 0xF9EC, 0x76D6, 0xCBCC, 0x76DB, 0xE0FC, 0x76DC, 0xD4A8, 0x76DE, 0xEDD3,
+ 0x76DF, 0xD8EF, 0x76E1, 0xF2D7, 0x76E3, 0xCAF8, 0x76E4, 0xDAEF, 0x76E7, 0xD6D4, 0x76EE, 0xD9CD, 0x76F2, 0xD8EE, 0x76F4, 0xF2C1,
+ 0x76F8, 0xDFD3, 0x76FC, 0xDAF0, 0x76FE, 0xE2EA, 0x7701, 0xE0FD, 0x7704, 0xD8F8, 0x7708, 0xF7AF, 0x7709, 0xDAB6, 0x770B, 0xCAD7,
+ 0x771E, 0xF2D8, 0x7720, 0xD8F9, 0x7729, 0xFADF, 0x7737, 0xCFEF, 0x7738, 0xD9C2, 0x773A, 0xF0D2, 0x773C, 0xE4D1, 0x7740, 0xF3B7,
+ 0x774D, 0xFAE0, 0x775B, 0xEFEC, 0x7761, 0xE2B2, 0x7763, 0xD4BD, 0x7766, 0xD9CE, 0x776B, 0xF4E2, 0x7779, 0xD4A9, 0x777E, 0xCDC2,
+ 0x777F, 0xE7DA, 0x778B, 0xF2D9, 0x7791, 0xD9AA, 0x779E, 0xD8BE, 0x77A5, 0xDCAD, 0x77AC, 0xE2EB, 0x77AD, 0xD6FC, 0x77B0, 0xCAF9,
+ 0x77B3, 0xD4DA, 0x77BB, 0xF4D7, 0x77BC, 0xCCA1, 0x77BF, 0xCFBA, 0x77D7, 0xF5B8, 0x77DB, 0xD9C3, 0x77DC, 0xD0E8, 0x77E2, 0xE3C5,
+ 0x77E3, 0xEBF8, 0x77E5, 0xF2B1, 0x77E9, 0xCFBB, 0x77ED, 0xD3AD, 0x77EE, 0xE8E1, 0x77EF, 0xCEEC, 0x77F3, 0xE0B4, 0x7802, 0xDEE3,
+ 0x7812, 0xDDF7, 0x7825, 0xF2B2, 0x7826, 0xF3F6, 0x7827, 0xF6DB, 0x782C, 0xD7FE, 0x7832, 0xF8DF, 0x7834, 0xF7F2, 0x7845, 0xD0A9,
+ 0x784F, 0xE6DA, 0x785D, 0xF5A6, 0x786B, 0xD7BC, 0x786C, 0xCCE3, 0x786F, 0xE6DB, 0x787C, 0xDDDD, 0x7881, 0xD1B3, 0x7887, 0xEFED,
+ 0x788C, 0xD6DE, 0x788D, 0xE4F4, 0x788E, 0xE1EF, 0x7891, 0xDDF8, 0x7897, 0xE8CF, 0x78A3, 0xCAE5, 0x78A7, 0xDCA1, 0x78A9, 0xE0B5,
+ 0x78BA, 0xFCAC, 0x78BB, 0xFCAD, 0x78BC, 0xD8A7, 0x78C1, 0xEDB8, 0x78C5, 0xDBB6, 0x78CA, 0xD6F0, 0x78CB, 0xF3AF, 0x78CE, 0xCDA5,
+ 0x78D0, 0xDAF1, 0x78E8, 0xD8A8, 0x78EC, 0xCCE4, 0x78EF, 0xD1B4, 0x78F5, 0xCAD8, 0x78FB, 0xDAF2, 0x7901, 0xF5A7, 0x790E, 0xF5A8,
+ 0x7916, 0xE6A6, 0x792A, 0xD5EC, 0x792B, 0xD5F8, 0x792C, 0xDAF3, 0x793A, 0xE3C6, 0x793E, 0xDEE4, 0x7940, 0xDEE5, 0x7941, 0xD1B5,
+ 0x7947, 0xD1B6, 0x7948, 0xD1B7, 0x7949, 0xF2B3, 0x7950, 0xE9DE, 0x7956, 0xF0D3, 0x7957, 0xF2B4, 0x795A, 0xF0D4, 0x795B, 0xCBE4,
+ 0x795C, 0xFBD4, 0x795D, 0xF5E6, 0x795E, 0xE3EA, 0x7960, 0xDEE6, 0x7965, 0xDFD4, 0x7968, 0xF8F9, 0x796D, 0xF0AE, 0x797A, 0xD1B8,
+ 0x797F, 0xD6DF, 0x7981, 0xD0D7, 0x798D, 0xFCA1, 0x798E, 0xEFEE, 0x798F, 0xDCD8, 0x7991, 0xE9DF, 0x79A6, 0xE5DD, 0x79A7, 0xFDFB,
+ 0x79AA, 0xE0C9, 0x79AE, 0xD6C9, 0x79B1, 0xD4AA, 0x79B3, 0xE5CC, 0x79B9, 0xE9E0, 0x79BD, 0xD0D8, 0x79BE, 0xFCA2, 0x79BF, 0xD4BE,
+ 0x79C0, 0xE2B3, 0x79C1, 0xDEE7, 0x79C9, 0xDCBC, 0x79CA, 0xD2B6, 0x79CB, 0xF5D5, 0x79D1, 0xCEA1, 0x79D2, 0xF5A9, 0x79D5, 0xDDF9,
+ 0x79D8, 0xDDFA, 0x79DF, 0xF0D5, 0x79E4, 0xF6DF, 0x79E6, 0xF2DA, 0x79E7, 0xE4EB, 0x79E9, 0xF2F1, 0x79FB, 0xECB9, 0x7A00, 0xFDFC,
+ 0x7A05, 0xE1AA, 0x7A08, 0xCAD9, 0x7A0B, 0xEFEF, 0x7A0D, 0xF5AA, 0x7A14, 0xECF9, 0x7A17, 0xF8AD, 0x7A19, 0xF2C2, 0x7A1A, 0xF6C3,
+ 0x7A1C, 0xD7D2, 0x7A1F, 0xF9A2, 0x7A20, 0xF0D6, 0x7A2E, 0xF0FA, 0x7A31, 0xF6E0, 0x7A36, 0xE9F3, 0x7A37, 0xF2C3, 0x7A3B, 0xD4AB,
+ 0x7A3C, 0xCAB3, 0x7A3D, 0xCDA6, 0x7A3F, 0xCDC3, 0x7A40, 0xCDDA, 0x7A46, 0xD9CF, 0x7A49, 0xF6C4, 0x7A4D, 0xEEDD, 0x7A4E, 0xE7C4,
+ 0x7A57, 0xE2B4, 0x7A61, 0xDFE2, 0x7A62, 0xE7DB, 0x7A69, 0xE8B1, 0x7A6B, 0xFCAE, 0x7A70, 0xE5CD, 0x7A74, 0xFAEB, 0x7A76, 0xCFBC,
+ 0x7A79, 0xCFE2, 0x7A7A, 0xCDF6, 0x7A7D, 0xEFF0, 0x7A7F, 0xF4BE, 0x7A81, 0xD4CD, 0x7A84, 0xF3B8, 0x7A88, 0xE9A1, 0x7A92, 0xF2F2,
+ 0x7A93, 0xF3EB, 0x7A95, 0xF0D7, 0x7A98, 0xCFD7, 0x7A9F, 0xCFDF, 0x7AA9, 0xE8C0, 0x7AAA, 0xE8C1, 0x7AAE, 0xCFE3, 0x7AAF, 0xE9A2,
+ 0x7ABA, 0xD0AA, 0x7AC4, 0xF3C1, 0x7AC5, 0xD0AB, 0x7AC7, 0xD4E4, 0x7ACA, 0xEFBC, 0x7ACB, 0xD8A1, 0x7AD7, 0xD9DF, 0x7AD9, 0xF3D7,
+ 0x7ADD, 0xDCBD, 0x7ADF, 0xCCE5, 0x7AE0, 0xEDF1, 0x7AE3, 0xF1E2, 0x7AE5, 0xD4DB, 0x7AEA, 0xE2B5, 0x7AED, 0xCAE6, 0x7AEF, 0xD3AE,
+ 0x7AF6, 0xCCE6, 0x7AF9, 0xF1D3, 0x7AFA, 0xF5E7, 0x7AFF, 0xCADA, 0x7B0F, 0xFBEE, 0x7B11, 0xE1C5, 0x7B19, 0xDFE9, 0x7B1B, 0xEEDE,
+ 0x7B1E, 0xF7C2, 0x7B20, 0xD8A2, 0x7B26, 0xDDAC, 0x7B2C, 0xF0AF, 0x7B2D, 0xD6BD, 0x7B39, 0xE1AB, 0x7B46, 0xF9B6, 0x7B49, 0xD4F5,
+ 0x7B4B, 0xD0C9, 0x7B4C, 0xEFA7, 0x7B4D, 0xE2EC, 0x7B4F, 0xDBEA, 0x7B50, 0xCECC, 0x7B51, 0xF5E8, 0x7B52, 0xF7D5, 0x7B54, 0xD3CD,
+ 0x7B56, 0xF3FE, 0x7B60, 0xD0B5, 0x7B6C, 0xE0FE, 0x7B6E, 0xDFFB, 0x7B75, 0xE6DD, 0x7B7D, 0xE8A4, 0x7B87, 0xCBCD, 0x7B8B, 0xEFA8,
+ 0x7B8F, 0xEEB4, 0x7B94, 0xDAD8, 0x7B95, 0xD1B9, 0x7B97, 0xDFA9, 0x7B9A, 0xF3B0, 0x7B9D, 0xCCC4, 0x7BA1, 0xCEB7, 0x7BAD, 0xEFA9,
+ 0x7BB1, 0xDFD5, 0x7BB4, 0xEDD7, 0x7BB8, 0xEEC6, 0x7BC0, 0xEFBD, 0x7BC1, 0xFCD6, 0x7BC4, 0xDBF4, 0x7BC6, 0xEFAA, 0x7BC7, 0xF8B9,
+ 0x7BC9, 0xF5E9, 0x7BD2, 0xE3D9, 0x7BE0, 0xE1C6, 0x7BE4, 0xD4BF, 0x7BE9, 0xDEE8, 0x7C07, 0xF0EA, 0x7C12, 0xF3C2, 0x7C1E, 0xD3AF,
+ 0x7C21, 0xCADB, 0x7C27, 0xFCD7, 0x7C2A, 0xEDD8, 0x7C2B, 0xE1C7, 0x7C3D, 0xF4D8, 0x7C3E, 0xD6B3, 0x7C3F, 0xDDAD, 0x7C43, 0xD5BE,
+ 0x7C4C, 0xF1C3, 0x7C4D, 0xEEDF, 0x7C60, 0xD6EB, 0x7C64, 0xF4D9, 0x7C6C, 0xD7E6, 0x7C73, 0xDAB7, 0x7C83, 0xDDFB, 0x7C89, 0xDDCF,
+ 0x7C92, 0xD8A3, 0x7C95, 0xDAD9, 0x7C97, 0xF0D8, 0x7C98, 0xEFC4, 0x7C9F, 0xE1D8, 0x7CA5, 0xF1D4, 0x7CA7, 0xEDF2, 0x7CAE, 0xD5DB,
+ 0x7CB1, 0xD5DC, 0x7CB2, 0xF3C4, 0x7CB3, 0xCBD7, 0x7CB9, 0xE2B6, 0x7CBE, 0xEFF1, 0x7CCA, 0xFBD5, 0x7CD6, 0xD3D8, 0x7CDE, 0xDDD0,
+ 0x7CDF, 0xF0D9, 0x7CE0, 0xCBB3, 0x7CE7, 0xD5DD, 0x7CFB, 0xCDA7, 0x7CFE, 0xD0AC, 0x7D00, 0xD1BA, 0x7D02, 0xF1C4, 0x7D04, 0xE5B3,
+ 0x7D05, 0xFBF5, 0x7D06, 0xE9E1, 0x7D07, 0xFDE0, 0x7D08, 0xFCBC, 0x7D0A, 0xDAA2, 0x7D0B, 0xDAA3, 0x7D0D, 0xD2A1, 0x7D10, 0xD2EF,
+ 0x7D14, 0xE2ED, 0x7D17, 0xDEE9, 0x7D18, 0xCEDC, 0x7D19, 0xF2B5, 0x7D1A, 0xD0E4, 0x7D1B, 0xDDD1, 0x7D20, 0xE1C8, 0x7D21, 0xDBB7,
+ 0x7D22, 0xDFE3, 0x7D2B, 0xEDB9, 0x7D2C, 0xF1C5, 0x7D2E, 0xF3CF, 0x7D2F, 0xD7AB, 0x7D30, 0xE1AC, 0x7D33, 0xE3EB, 0x7D35, 0xEEC7,
+ 0x7D39, 0xE1C9, 0x7D3A, 0xCAFA, 0x7D42, 0xF0FB, 0x7D43, 0xFAE1, 0x7D44, 0xF0DA, 0x7D45, 0xCCE7, 0x7D46, 0xDAF4, 0x7D50, 0xCCBF,
+ 0x7D5E, 0xCEED, 0x7D61, 0xD5A9, 0x7D62, 0xFAE2, 0x7D66, 0xD0E5, 0x7D68, 0xEBD6, 0x7D6A, 0xECDF, 0x7D6E, 0xDFFC, 0x7D71, 0xF7D6,
+ 0x7D72, 0xDEEA, 0x7D73, 0xCBB4, 0x7D76, 0xEFBE, 0x7D79, 0xCCB5, 0x7D7F, 0xCFBD, 0x7D8E, 0xEFF2, 0x7D8F, 0xE2B7, 0x7D93, 0xCCE8,
+ 0x7D9C, 0xF0FC, 0x7DA0, 0xD6E0, 0x7DA2, 0xF1C6, 0x7DAC, 0xE2B8, 0x7DAD, 0xEBAB, 0x7DB1, 0xCBB5, 0x7DB2, 0xD8D1, 0x7DB4, 0xF4CE,
+ 0x7DB5, 0xF3F7, 0x7DB8, 0xD7C6, 0x7DBA, 0xD1BB, 0x7DBB, 0xF7AA, 0x7DBD, 0xEDCA, 0x7DBE, 0xD7D3, 0x7DBF, 0xD8FA, 0x7DC7, 0xF6C5,
+ 0x7DCA, 0xD1CC, 0x7DCB, 0xDDFC, 0x7DD6, 0xDFFD, 0x7DD8, 0xF9E5, 0x7DDA, 0xE0CA, 0x7DDD, 0xF2FD, 0x7DDE, 0xD3B0, 0x7DE0, 0xF4F3,
+ 0x7DE1, 0xDAC9, 0x7DE3, 0xE6DE, 0x7DE8, 0xF8BA, 0x7DE9, 0xE8D0, 0x7DEC, 0xD8FB, 0x7DEF, 0xEAD5, 0x7DF4, 0xD6A3, 0x7DFB, 0xF6C6,
+ 0x7E09, 0xF2DB, 0x7E0A, 0xE4FC, 0x7E15, 0xE8B2, 0x7E1B, 0xDADA, 0x7E1D, 0xF2DC, 0x7E1E, 0xFBD6, 0x7E1F, 0xE9B2, 0x7E21, 0xEEAD,
+ 0x7E23, 0xFAE3, 0x7E2B, 0xDCEE, 0x7E2E, 0xF5EA, 0x7E2F, 0xE6E0, 0x7E31, 0xF0FD, 0x7E37, 0xD7AC, 0x7E3D, 0xF5C5, 0x7E3E, 0xEEE0,
+ 0x7E41, 0xDBE5, 0x7E43, 0xDDDE, 0x7E46, 0xD9F0, 0x7E47, 0xE9A3, 0x7E52, 0xF1F9, 0x7E54, 0xF2C4, 0x7E55, 0xE0CB, 0x7E5E, 0xE9A4,
+ 0x7E61, 0xE2B9, 0x7E69, 0xE3B1, 0x7E6A, 0xFCEB, 0x7E6B, 0xCDA8, 0x7E6D, 0xCCB6, 0x7E70, 0xF0DB, 0x7E79, 0xE6BA, 0x7E7C, 0xCDA9,
+ 0x7E82, 0xF3C3, 0x7E8C, 0xE1D9, 0x7E8F, 0xEFAB, 0x7E93, 0xE7C5, 0x7E96, 0xE0E9, 0x7E98, 0xF3C5, 0x7E9B, 0xD4C0, 0x7E9C, 0xD5BF,
+ 0x7F36, 0xDDAE, 0x7F38, 0xF9FC, 0x7F3A, 0xCCC0, 0x7F4C, 0xE5A2, 0x7F50, 0xCEB8, 0x7F54, 0xD8D2, 0x7F55, 0xF9D6, 0x7F6A, 0xF1AA,
+ 0x7F6B, 0xCED1, 0x7F6E, 0xF6C7, 0x7F70, 0xDBEB, 0x7F72, 0xDFFE, 0x7F75, 0xD8E1, 0x7F77, 0xF7F3, 0x7F79, 0xD7E7, 0x7F85, 0xD4FE,
+ 0x7F88, 0xD1BC, 0x7F8A, 0xE5CF, 0x7F8C, 0xCBB6, 0x7F8E, 0xDAB8, 0x7F94, 0xCDC4, 0x7F9A, 0xD6BE, 0x7F9E, 0xE2BA, 0x7FA4, 0xCFD8,
+ 0x7FA8, 0xE0CC, 0x7FA9, 0xEBF9, 0x7FB2, 0xFDFD, 0x7FB8, 0xD7E8, 0x7FB9, 0xCBD8, 0x7FBD, 0xE9E2, 0x7FC1, 0xE8BA, 0x7FC5, 0xE3C7,
+ 0x7FCA, 0xECCD, 0x7FCC, 0xECCE, 0x7FCE, 0xD6BF, 0x7FD2, 0xE3A7, 0x7FD4, 0xDFD6, 0x7FD5, 0xFDE8, 0x7FDF, 0xEEE1, 0x7FE0, 0xF6A8,
+ 0x7FE1, 0xDDFD, 0x7FE9, 0xF8BB, 0x7FEB, 0xE8D1, 0x7FF0, 0xF9D7, 0x7FF9, 0xCEEE, 0x7FFC, 0xECCF, 0x8000, 0xE9A5, 0x8001, 0xD6D5,
+ 0x8003, 0xCDC5, 0x8005, 0xEDBA, 0x8006, 0xD1BD, 0x8009, 0xCFBE, 0x800C, 0xECBB, 0x8010, 0xD2B1, 0x8015, 0xCCE9, 0x8017, 0xD9C4,
+ 0x8018, 0xE9FC, 0x802D, 0xD1BE, 0x8033, 0xECBC, 0x8036, 0xE5AD, 0x803D, 0xF7B0, 0x803F, 0xCCEA, 0x8043, 0xD3C4, 0x8046, 0xD6C0,
+ 0x804A, 0xD6FD, 0x8056, 0xE1A1, 0x8058, 0xDEBD, 0x805A, 0xF6A9, 0x805E, 0xDAA4, 0x806F, 0xD6A4, 0x8070, 0xF5C6, 0x8072, 0xE1A2,
+ 0x8073, 0xE9C6, 0x8077, 0xF2C5, 0x807D, 0xF4E9, 0x807E, 0xD6EC, 0x807F, 0xEBD3, 0x8084, 0xECBD, 0x8085, 0xE2DC, 0x8086, 0xDEEB,
+ 0x8087, 0xF0DC, 0x8089, 0xEBBF, 0x808B, 0xD7CE, 0x808C, 0xD1BF, 0x8096, 0xF5AB, 0x809B, 0xF9FD, 0x809D, 0xCADC, 0x80A1, 0xCDC6,
+ 0x80A2, 0xF2B6, 0x80A5, 0xDDFE, 0x80A9, 0xCCB7, 0x80AA, 0xDBB8, 0x80AF, 0xD0E9, 0x80B1, 0xCEDD, 0x80B2, 0xEBC0, 0x80B4, 0xFDA2,
+ 0x80BA, 0xF8CB, 0x80C3, 0xEAD6, 0x80C4, 0xF1B0, 0x80CC, 0xDBCE, 0x80CE, 0xF7C3, 0x80DA, 0xDBCF, 0x80DB, 0xCBA4, 0x80DE, 0xF8E0,
+ 0x80E1, 0xFBD7, 0x80E4, 0xEBCA, 0x80E5, 0xE0A1, 0x80F1, 0xCECD, 0x80F4, 0xD4DC, 0x80F8, 0xFDD8, 0x80FD, 0xD2F6, 0x8102, 0xF2B7,
+ 0x8105, 0xFAF6, 0x8106, 0xF6AA, 0x8107, 0xFAF7, 0x8108, 0xD8E6, 0x810A, 0xF4B1, 0x8118, 0xE8D2, 0x811A, 0xCAC5, 0x811B, 0xCCEB,
+ 0x8123, 0xE2EE, 0x8129, 0xE2BB, 0x812B, 0xF7AD, 0x812F, 0xF8E1, 0x8139, 0xF3EC, 0x813E, 0xDEA1, 0x814B, 0xE4FD, 0x814E, 0xE3EC,
+ 0x8150, 0xDDAF, 0x8151, 0xDDB0, 0x8154, 0xCBB7, 0x8155, 0xE8D3, 0x8165, 0xE1A3, 0x8166, 0xD2E0, 0x816B, 0xF0FE, 0x8170, 0xE9A6,
+ 0x8171, 0xCBF2, 0x8178, 0xEDF3, 0x8179, 0xDCD9, 0x817A, 0xE0CD, 0x817F, 0xF7DA, 0x8180, 0xDBB9, 0x8188, 0xCCAE, 0x818A, 0xDADB,
+ 0x818F, 0xCDC7, 0x819A, 0xDDB1, 0x819C, 0xD8AF, 0x819D, 0xE3A3, 0x81A0, 0xCEEF, 0x81A3, 0xF2F3, 0x81A8, 0xF8B3, 0x81B3, 0xE0CE,
+ 0x81B5, 0xF5FD, 0x81BA, 0xEBEC, 0x81BD, 0xD3C5, 0x81BE, 0xFCEC, 0x81BF, 0xD2DB, 0x81C0, 0xD4EB, 0x81C2, 0xDEA2, 0x81C6, 0xE5E6,
+ 0x81CD, 0xF0B0, 0x81D8, 0xD5C4, 0x81DF, 0xEDF4, 0x81E3, 0xE3ED, 0x81E5, 0xE8C2, 0x81E7, 0xEDF5, 0x81E8, 0xD7FC, 0x81EA, 0xEDBB,
+ 0x81ED, 0xF6AB, 0x81F3, 0xF2B8, 0x81F4, 0xF6C8, 0x81FA, 0xD3E6, 0x81FB, 0xF2DD, 0x81FC, 0xCFBF, 0x81FE, 0xEBAC, 0x8205, 0xCFC0,
+ 0x8207, 0xE6A8, 0x8208, 0xFDE9, 0x820A, 0xCFC1, 0x820C, 0xE0DF, 0x820D, 0xDEEC, 0x8212, 0xE0A2, 0x821B, 0xF4BF, 0x821C, 0xE2EF,
+ 0x821E, 0xD9F1, 0x821F, 0xF1C7, 0x8221, 0xCBB8, 0x822A, 0xF9FE, 0x822B, 0xDBBA, 0x822C, 0xDAF5, 0x8235, 0xF6EC, 0x8236, 0xDADC,
+ 0x8237, 0xFAE4, 0x8239, 0xE0CF, 0x8240, 0xDDB2, 0x8245, 0xE6A9, 0x8247, 0xEFF3, 0x8259, 0xF3ED, 0x8264, 0xEBFA, 0x8266, 0xF9E6,
+ 0x826E, 0xCADD, 0x826F, 0xD5DE, 0x8271, 0xCADE, 0x8272, 0xDFE4, 0x8276, 0xE6FD, 0x8278, 0xF5AC, 0x827E, 0xE4F5, 0x828B, 0xE9E3,
+ 0x828D, 0xEDCB, 0x828E, 0xCFE4, 0x8292, 0xD8D3, 0x8299, 0xDDB3, 0x829A, 0xD4EC, 0x829D, 0xF2B9, 0x829F, 0xDFB7, 0x82A5, 0xCBCE,
+ 0x82A6, 0xFBD8, 0x82A9, 0xD0D9, 0x82AC, 0xDDD2, 0x82AD, 0xF7F4, 0x82AE, 0xE7DC, 0x82AF, 0xE4A5, 0x82B1, 0xFCA3, 0x82B3, 0xDBBB,
+ 0x82B7, 0xF2BA, 0x82B8, 0xE9FD, 0x82B9, 0xD0CA, 0x82BB, 0xF5D6, 0x82BC, 0xD9C5, 0x82BD, 0xE4B4, 0x82BF, 0xEDA7, 0x82D1, 0xEABD,
+ 0x82D2, 0xE6FE, 0x82D4, 0xF7C4, 0x82D5, 0xF5AD, 0x82D7, 0xD9E0, 0x82DB, 0xCAB4, 0x82DE, 0xF8E2, 0x82DF, 0xCFC2, 0x82E1, 0xECBE,
+ 0x82E5, 0xE5B4, 0x82E6, 0xCDC8, 0x82E7, 0xEEC8, 0x82F1, 0xE7C8, 0x82FD, 0xCDC9, 0x82FE, 0xF9B7, 0x8301, 0xF1E8, 0x8302, 0xD9F2,
+ 0x8303, 0xDBF5, 0x8304, 0xCAB5, 0x8305, 0xD9C6, 0x8309, 0xD8C9, 0x8317, 0xD9AB, 0x8328, 0xEDBC, 0x832B, 0xD8D4, 0x832F, 0xDCDA,
+ 0x8331, 0xE2BC, 0x8334, 0xFCED, 0x8335, 0xECE0, 0x8336, 0xD2FE, 0x8338, 0xE9C7, 0x8339, 0xE6AA, 0x8340, 0xE2F0, 0x8347, 0xFABB,
+ 0x8349, 0xF5AE, 0x834A, 0xFBAA, 0x834F, 0xECFB, 0x8351, 0xECBF, 0x8352, 0xFCD8, 0x8373, 0xD4E5, 0x8377, 0xF9C3, 0x837B, 0xEEE2,
+ 0x8389, 0xD7E9, 0x838A, 0xEDF6, 0x838E, 0xDEED, 0x8396, 0xCCEC, 0x8398, 0xE3EE, 0x839E, 0xE8D4, 0x83A2, 0xFAF8, 0x83A9, 0xDDB4,
+ 0x83AA, 0xE4B5, 0x83AB, 0xD8B0, 0x83BD, 0xD8D5, 0x83C1, 0xF4EA, 0x83C5, 0xCEB9, 0x83C9, 0xD6E1, 0x83CA, 0xCFD2, 0x83CC, 0xD0B6,
+ 0x83D3, 0xCEA2, 0x83D6, 0xF3EE, 0x83DC, 0xF3F8, 0x83E9, 0xDCCC, 0x83EB, 0xD0CB, 0x83EF, 0xFCA4, 0x83F0, 0xCDCA, 0x83F1, 0xD7D4,
+ 0x83F2, 0xDEA3, 0x83F4, 0xE4E0, 0x83F9, 0xEEC9, 0x83FD, 0xE2DD, 0x8403, 0xF5FE, 0x8404, 0xD4AC, 0x840A, 0xD5D1, 0x840C, 0xD8F0,
+ 0x840D, 0xF8C3, 0x840E, 0xEAD7, 0x8429, 0xF5D7, 0x842C, 0xD8BF, 0x8431, 0xFDC0, 0x8438, 0xEBAD, 0x843D, 0xD5AA, 0x8449, 0xE7A8,
+ 0x8457, 0xEECA, 0x845B, 0xCAE7, 0x8461, 0xF8E3, 0x8463, 0xD4DD, 0x8466, 0xEAD8, 0x846B, 0xFBD9, 0x846C, 0xEDF7, 0x846F, 0xE5B5,
+ 0x8475, 0xD0AD, 0x847A, 0xF1F1, 0x8490, 0xE2BD, 0x8494, 0xE3C8, 0x8499, 0xD9D5, 0x849C, 0xDFAA, 0x84A1, 0xDBBC, 0x84B2, 0xF8E4,
+ 0x84B8, 0xF1FA, 0x84BB, 0xE5B6, 0x84BC, 0xF3EF, 0x84BF, 0xFBDA, 0x84C0, 0xE1E0, 0x84C2, 0xD9AC, 0x84C4, 0xF5EB, 0x84C6, 0xE0B6,
+ 0x84C9, 0xE9C8, 0x84CB, 0xCBCF, 0x84CD, 0xE3C9, 0x84D1, 0xDEEE, 0x84DA, 0xE2BE, 0x84EC, 0xDCEF, 0x84EE, 0xD6A5, 0x84F4, 0xE2F1,
+ 0x84FC, 0xD6FE, 0x8511, 0xD9A1, 0x8513, 0xD8C0, 0x8514, 0xDCDB, 0x8517, 0xEDBD, 0x8518, 0xDFB8, 0x851A, 0xEAA5, 0x851E, 0xD7AD,
+ 0x8521, 0xF3F9, 0x8523, 0xEDF8, 0x8525, 0xF5C7, 0x852C, 0xE1CA, 0x852D, 0xEBE3, 0x852F, 0xF2DE, 0x853D, 0xF8CC, 0x853F, 0xEAD9,
+ 0x8541, 0xD3C6, 0x8543, 0xDBE6, 0x8549, 0xF5AF, 0x854E, 0xCEF0, 0x8553, 0xE9FE, 0x8559, 0xFBB6, 0x8563, 0xE2F2, 0x8568, 0xCFF2,
+ 0x8569, 0xF7B9, 0x856A, 0xD9F3, 0x856D, 0xE1CB, 0x8584, 0xDADD, 0x8587, 0xDAB9, 0x858F, 0xEBFB, 0x8591, 0xCBB9, 0x8594, 0xEDF9,
+ 0x859B, 0xE0E0, 0x85A6, 0xF4C0, 0x85A8, 0xFDBC, 0x85A9, 0xDFB1, 0x85AA, 0xE3EF, 0x85AF, 0xE0A3, 0x85B0, 0xFDB9, 0x85BA, 0xF0B1,
+ 0x85C1, 0xCDCB, 0x85C9, 0xEDBE, 0x85CD, 0xD5C0, 0x85CE, 0xE3F0, 0x85CF, 0xEDFA, 0x85D5, 0xE9E4, 0x85DC, 0xD5ED, 0x85DD, 0xE7DD,
+ 0x85E4, 0xD4F6, 0x85E5, 0xE5B7, 0x85E9, 0xDBE7, 0x85EA, 0xE2BF, 0x85F7, 0xEECB, 0x85FA, 0xD7F4, 0x85FB, 0xF0DD, 0x85FF, 0xCEAB,
+ 0x8602, 0xE7DE, 0x8606, 0xD6D6, 0x8607, 0xE1CC, 0x860A, 0xE8B3, 0x8616, 0xE5EE, 0x8617, 0xDCA2, 0x861A, 0xE0D0, 0x862D, 0xD5B5,
+ 0x863F, 0xD5A1, 0x864E, 0xFBDB, 0x8650, 0xF9CB, 0x8654, 0xCBF3, 0x8655, 0xF4A5, 0x865B, 0xFAC8, 0x865C, 0xD6D7, 0x865E, 0xE9E5,
+ 0x865F, 0xFBDC, 0x8667, 0xFDD0, 0x8679, 0xFBF6, 0x868A, 0xDAA5, 0x868C, 0xDBBD, 0x8693, 0xECE2, 0x86A3, 0xCDF7, 0x86A4, 0xF0DE,
+ 0x86A9, 0xF6C9, 0x86C7, 0xDEEF, 0x86CB, 0xD3B1, 0x86D4, 0xFCEE, 0x86D9, 0xE8C3, 0x86DB, 0xF1C8, 0x86DF, 0xCEF1, 0x86E4, 0xF9ED,
+ 0x86ED, 0xF2F4, 0x86FE, 0xE4B6, 0x8700, 0xF5B9, 0x8702, 0xDCF0, 0x8703, 0xE3F1, 0x8708, 0xE8A5, 0x8718, 0xF2BB, 0x871A, 0xDEA4,
+ 0x871C, 0xDACC, 0x874E, 0xCAE9, 0x8755, 0xE3DA, 0x8757, 0xFCD9, 0x875F, 0xEADA, 0x8766, 0xF9C4, 0x8768, 0xE3A4, 0x8774, 0xFBDD,
+ 0x8776, 0xEFCA, 0x8778, 0xE8C4, 0x8782, 0xD5CC, 0x878D, 0xEBD7, 0x879F, 0xD9AD, 0x87A2, 0xFBAB, 0x87B3, 0xD3D9, 0x87BA, 0xD5A2,
+ 0x87C4, 0xF6DE, 0x87E0, 0xDAF6, 0x87EC, 0xE0D1, 0x87EF, 0xE9A8, 0x87F2, 0xF5F9, 0x87F9, 0xFAAF, 0x87FB, 0xEBFC, 0x87FE, 0xE0EA,
+ 0x8805, 0xE3B2, 0x881F, 0xD5C5, 0x8822, 0xF1E3, 0x8823, 0xD5EE, 0x8831, 0xCDCC, 0x8836, 0xEDD9, 0x883B, 0xD8C1, 0x8840, 0xFAEC,
+ 0x8846, 0xF1EB, 0x884C, 0xFABC, 0x884D, 0xE6E2, 0x8852, 0xFAE5, 0x8853, 0xE2FA, 0x8857, 0xCAB6, 0x8859, 0xE4B7, 0x885B, 0xEADB,
+ 0x885D, 0xF5FA, 0x8861, 0xFBAC, 0x8862, 0xCFC3, 0x8863, 0xEBFD, 0x8868, 0xF8FA, 0x886B, 0xDFB9, 0x8870, 0xE1F1, 0x8872, 0xD2A4,
+ 0x8877, 0xF5FB, 0x887E, 0xD0DA, 0x887F, 0xD0DB, 0x8881, 0xEABE, 0x8882, 0xD9B1, 0x8888, 0xCAB7, 0x888B, 0xD3E7, 0x888D, 0xF8E5,
+ 0x8892, 0xD3B2, 0x8896, 0xE2C0, 0x8897, 0xF2DF, 0x889E, 0xCDE5, 0x88AB, 0xF9AC, 0x88B4, 0xCDCD, 0x88C1, 0xEEAE, 0x88C2, 0xD6AE,
+ 0x88CF, 0xD7EA, 0x88D4, 0xE7E0, 0x88D5, 0xEBAE, 0x88D9, 0xCFD9, 0x88DC, 0xDCCD, 0x88DD, 0xEDFB, 0x88DF, 0xDEF0, 0x88E1, 0xD7EB,
+ 0x88E8, 0xDEA5, 0x88F3, 0xDFD7, 0x88F4, 0xDBD0, 0x88F5, 0xDBD1, 0x88F8, 0xD5A3, 0x88FD, 0xF0B2, 0x8907, 0xDCDC, 0x8910, 0xCAE8,
+ 0x8912, 0xF8E6, 0x8913, 0xDCCE, 0x8918, 0xEADC, 0x8919, 0xDBD2, 0x8925, 0xE9B3, 0x892A, 0xF7DB, 0x8936, 0xE3A8, 0x8938, 0xD7AE,
+ 0x893B, 0xE0E1, 0x8941, 0xCBBA, 0x8944, 0xE5D1, 0x895F, 0xD0DC, 0x8964, 0xD5C1, 0x896A, 0xD8CA, 0x8972, 0xE3A9, 0x897F, 0xE0A4,
+ 0x8981, 0xE9A9, 0x8983, 0xD3C7, 0x8986, 0xDCDD, 0x8987, 0xF8AE, 0x898B, 0xCCB8, 0x898F, 0xD0AE, 0x8993, 0xD8F2, 0x8996, 0xE3CA,
+ 0x89A1, 0xCCAF, 0x89A9, 0xD4AD, 0x89AA, 0xF6D1, 0x89B2, 0xD0CC, 0x89BA, 0xCAC6, 0x89BD, 0xD5C2, 0x89C0, 0xCEBA, 0x89D2, 0xCAC7,
+ 0x89E3, 0xFAB0, 0x89F4, 0xDFD8, 0x89F8, 0xF5BA, 0x8A00, 0xE5EB, 0x8A02, 0xEFF4, 0x8A03, 0xDDB5, 0x8A08, 0xCDAA, 0x8A0A, 0xE3F2,
+ 0x8A0C, 0xFBF7, 0x8A0E, 0xF7D0, 0x8A13, 0xFDBA, 0x8A16, 0xFDE1, 0x8A17, 0xF6FE, 0x8A18, 0xD1C0, 0x8A1B, 0xE8C5, 0x8A1D, 0xE4B8,
+ 0x8A1F, 0xE1E8, 0x8A23, 0xCCC1, 0x8A25, 0xD2ED, 0x8A2A, 0xDBBE, 0x8A2D, 0xE0E2, 0x8A31, 0xFAC9, 0x8A34, 0xE1CD, 0x8A36, 0xCAB8,
+ 0x8A3A, 0xF2E0, 0x8A3B, 0xF1C9, 0x8A50, 0xDEF1, 0x8A54, 0xF0DF, 0x8A55, 0xF8C4, 0x8A5B, 0xEECC, 0x8A5E, 0xDEF2, 0x8A60, 0xE7C9,
+ 0x8A62, 0xE2F3, 0x8A63, 0xE7E1, 0x8A66, 0xE3CB, 0x8A69, 0xE3CC, 0x8A6D, 0xCFF8, 0x8A6E, 0xEFAC, 0x8A70, 0xFDFE, 0x8A71, 0xFCA5,
+ 0x8A72, 0xFAB1, 0x8A73, 0xDFD9, 0x8A75, 0xE0D2, 0x8A79, 0xF4DA, 0x8A85, 0xF1CA, 0x8A87, 0xCEA3, 0x8A8C, 0xF2BC, 0x8A8D, 0xECE3,
+ 0x8A93, 0xE0A5, 0x8A95, 0xF7AB, 0x8A98, 0xEBAF, 0x8A9E, 0xE5DE, 0x8AA0, 0xE1A4, 0x8AA1, 0xCDAB, 0x8AA3, 0xD9F4, 0x8AA4, 0xE8A6,
+ 0x8AA5, 0xCDCE, 0x8AA6, 0xE1E9, 0x8AA8, 0xFCEF, 0x8AAA, 0xE0E3, 0x8AB0, 0xE2C1, 0x8AB2, 0xCEA4, 0x8AB9, 0xDEA6, 0x8ABC, 0xEBFE,
+ 0x8ABE, 0xEBDD, 0x8ABF, 0xF0E0, 0x8AC2, 0xF4DB, 0x8AC4, 0xE2F4, 0x8AC7, 0xD3C8, 0x8ACB, 0xF4EB, 0x8ACD, 0xEEB5, 0x8ACF, 0xF5D8,
+ 0x8AD2, 0xD5DF, 0x8AD6, 0xD6E5, 0x8ADB, 0xEBB0, 0x8ADC, 0xF4E3, 0x8AE1, 0xE3CD, 0x8AE6, 0xF4F4, 0x8AE7, 0xFAB2, 0x8AEA, 0xEFF5,
+ 0x8AEB, 0xCADF, 0x8AED, 0xEBB1, 0x8AEE, 0xEDBF, 0x8AF1, 0xFDC9, 0x8AF6, 0xE4A6, 0x8AF7, 0xF9A4, 0x8AF8, 0xF0B3, 0x8AFA, 0xE5EC,
+ 0x8AFE, 0xD1E7, 0x8B00, 0xD9C7, 0x8B01, 0xE4D7, 0x8B02, 0xEADD, 0x8B04, 0xD4F7, 0x8B0E, 0xDABA, 0x8B10, 0xDACD, 0x8B14, 0xF9CC,
+ 0x8B16, 0xE1DA, 0x8B17, 0xDBBF, 0x8B19, 0xCCC5, 0x8B1A, 0xECD0, 0x8B1B, 0xCBBB, 0x8B1D, 0xDEF3, 0x8B20, 0xE9AA, 0x8B28, 0xD9C8,
+ 0x8B2B, 0xEEE3, 0x8B2C, 0xD7BD, 0x8B33, 0xCFC4, 0x8B39, 0xD0CD, 0x8B41, 0xFCA6, 0x8B49, 0xF1FB, 0x8B4E, 0xFDD2, 0x8B4F, 0xD1C1,
+ 0x8B58, 0xE3DB, 0x8B5A, 0xD3C9, 0x8B5C, 0xDCCF, 0x8B66, 0xCCED, 0x8B6C, 0xDEA7, 0x8B6F, 0xE6BB, 0x8B70, 0xECA1, 0x8B74, 0xCCB9,
+ 0x8B77, 0xFBDE, 0x8B7D, 0xE7E2, 0x8B80, 0xD4C1, 0x8B8A, 0xDCA8, 0x8B90, 0xE2C2, 0x8B92, 0xF3D8, 0x8B93, 0xE5D3, 0x8B96, 0xF3D9,
+ 0x8B9A, 0xF3C6, 0x8C37, 0xCDDB, 0x8C3F, 0xCDAC, 0x8C41, 0xFCC3, 0x8C46, 0xD4E7, 0x8C48, 0xD1C2, 0x8C4A, 0xF9A5, 0x8C4C, 0xE8D5,
+ 0x8C55, 0xE3CE, 0x8C5A, 0xD4CA, 0x8C61, 0xDFDA, 0x8C6A, 0xFBDF, 0x8C6B, 0xE7E3, 0x8C79, 0xF8FB, 0x8C7A, 0xE3CF, 0x8C82, 0xF5B0,
+ 0x8C8A, 0xD8E7, 0x8C8C, 0xD9C9, 0x8C9D, 0xF8AF, 0x8C9E, 0xEFF6, 0x8CA0, 0xDDB6, 0x8CA1, 0xEEAF, 0x8CA2, 0xCDF8, 0x8CA7, 0xDEB8,
+ 0x8CA8, 0xFCA7, 0x8CA9, 0xF7FC, 0x8CAA, 0xF7B1, 0x8CAB, 0xCEBB, 0x8CAC, 0xF4A1, 0x8CAF, 0xEECD, 0x8CB0, 0xE1AE, 0x8CB3, 0xECC3,
+ 0x8CB4, 0xCFFE, 0x8CB6, 0xF8BF, 0x8CB7, 0xD8E2, 0x8CB8, 0xD3E8, 0x8CBB, 0xDEA8, 0x8CBC, 0xF4E4, 0x8CBD, 0xECC2, 0x8CBF, 0xD9F5,
+ 0x8CC0, 0xF9C5, 0x8CC1, 0xDDD3, 0x8CC2, 0xD6F1, 0x8CC3, 0xECFC, 0x8CC4, 0xFCF0, 0x8CC7, 0xEDC0, 0x8CC8, 0xCAB9, 0x8CCA, 0xEEE4,
+ 0x8CD1, 0xF2E1, 0x8CD3, 0xDEB9, 0x8CDA, 0xD6F2, 0x8CDC, 0xDEF4, 0x8CDE, 0xDFDB, 0x8CE0, 0xDBD3, 0x8CE2, 0xFAE7, 0x8CE3, 0xD8E3,
+ 0x8CE4, 0xF4C1, 0x8CE6, 0xDDB7, 0x8CEA, 0xF2F5, 0x8CED, 0xD4AE, 0x8CF4, 0xD6F3, 0x8CFB, 0xDDB8, 0x8CFC, 0xCFC5, 0x8CFD, 0xDFDF,
+ 0x8D04, 0xF2BE, 0x8D05, 0xF6A1, 0x8D07, 0xEBCB, 0x8D08, 0xF1FC, 0x8D0A, 0xF3C7, 0x8D0D, 0xE0EB, 0x8D13, 0xEDFC, 0x8D16, 0xE1DB,
+ 0x8D64, 0xEEE5, 0x8D66, 0xDEF5, 0x8D6B, 0xFAD3, 0x8D70, 0xF1CB, 0x8D73, 0xD0AF, 0x8D74, 0xDDB9, 0x8D77, 0xD1C3, 0x8D85, 0xF5B1,
+ 0x8D8A, 0xEAC6, 0x8D99, 0xF0E1, 0x8DA3, 0xF6AC, 0x8DA8, 0xF5D9, 0x8DB3, 0xF0EB, 0x8DBA, 0xDDBA, 0x8DBE, 0xF2BF, 0x8DC6, 0xF7C5,
+ 0x8DCB, 0xDBA2, 0x8DCC, 0xF2F6, 0x8DCF, 0xCABA, 0x8DDB, 0xF7F5, 0x8DDD, 0xCBE5, 0x8DE1, 0xEEE6, 0x8DE3, 0xE0D3, 0x8DE8, 0xCEA5,
+ 0x8DEF, 0xD6D8, 0x8DF3, 0xD4AF, 0x8E0A, 0xE9C9, 0x8E0F, 0xD3CE, 0x8E10, 0xF4C2, 0x8E1E, 0xCBE6, 0x8E2A, 0xF1A1, 0x8E30, 0xEBB2,
+ 0x8E35, 0xF1A2, 0x8E42, 0xEBB3, 0x8E44, 0xF0B4, 0x8E47, 0xCBF4, 0x8E48, 0xD4B0, 0x8E49, 0xF3B2, 0x8E4A, 0xFBB7, 0x8E59, 0xF5EC,
+ 0x8E5F, 0xEEE7, 0x8E60, 0xF4B2, 0x8E74, 0xF5ED, 0x8E76, 0xCFF3, 0x8E81, 0xF0E2, 0x8E87, 0xEECE, 0x8E8A, 0xF1CC, 0x8E8D, 0xE5B8,
+ 0x8EAA, 0xD7F5, 0x8EAB, 0xE3F3, 0x8EAC, 0xCFE5, 0x8EC0, 0xCFC6, 0x8ECA, 0xF3B3, 0x8ECB, 0xE4D8, 0x8ECC, 0xCFF9, 0x8ECD, 0xCFDA,
+ 0x8ED2, 0xFACD, 0x8EDF, 0xE6E3, 0x8EEB, 0xF2E2, 0x8EF8, 0xF5EE, 0x8EFB, 0xCABB, 0x8EFE, 0xE3DC, 0x8F03, 0xCEF2, 0x8F05, 0xD6D9,
+ 0x8F09, 0xEEB0, 0x8F12, 0xF4E5, 0x8F13, 0xD8C2, 0x8F14, 0xDCD0, 0x8F15, 0xCCEE, 0x8F1B, 0xD5E0, 0x8F1C, 0xF6CA, 0x8F1D, 0xFDCA,
+ 0x8F1E, 0xD8D6, 0x8F1F, 0xF4CF, 0x8F26, 0xD6A6, 0x8F27, 0xDCBE, 0x8F29, 0xDBD4, 0x8F2A, 0xD7C7, 0x8F2F, 0xF2FE, 0x8F33, 0xF1CD,
+ 0x8F38, 0xE2C3, 0x8F39, 0xDCDE, 0x8F3B, 0xDCDF, 0x8F3E, 0xEFAD, 0x8F3F, 0xE6AB, 0x8F44, 0xF9DD, 0x8F45, 0xEABF, 0x8F49, 0xEFAE,
+ 0x8F4D, 0xF4D0, 0x8F4E, 0xCEF3, 0x8F5D, 0xE6AC, 0x8F5F, 0xCEDE, 0x8F62, 0xD5F9, 0x8F9B, 0xE3F4, 0x8F9C, 0xCDD0, 0x8FA3, 0xD5B8,
+ 0x8FA6, 0xF7FD, 0x8FA8, 0xDCA9, 0x8FAD, 0xDEF6, 0x8FAF, 0xDCAA, 0x8FB0, 0xF2E3, 0x8FB1, 0xE9B4, 0x8FB2, 0xD2DC, 0x8FC2, 0xE9E6,
+ 0x8FC5, 0xE3F6, 0x8FCE, 0xE7CA, 0x8FD1, 0xD0CE, 0x8FD4, 0xDAF7, 0x8FE6, 0xCABC, 0x8FEA, 0xEEE8, 0x8FEB, 0xDADE, 0x8FED, 0xF2F7,
+ 0x8FF0, 0xE2FB, 0x8FF2, 0xCCA6, 0x8FF7, 0xDABB, 0x8FF9, 0xEEE9, 0x8FFD, 0xF5DA, 0x9000, 0xF7DC, 0x9001, 0xE1EA, 0x9002, 0xCEC1,
+ 0x9003, 0xD4B1, 0x9005, 0xFDB1, 0x9006, 0xE6BD, 0x9008, 0xFBAD, 0x900B, 0xF8E7, 0x900D, 0xE1CE, 0x900F, 0xF7E2, 0x9010, 0xF5EF,
+ 0x9011, 0xCFC7, 0x9014, 0xD4B2, 0x9015, 0xCCEF, 0x9017, 0xD4E8, 0x9019, 0xEECF, 0x901A, 0xF7D7, 0x901D, 0xE0A6, 0x901E, 0xD6C1,
+ 0x901F, 0xE1DC, 0x9020, 0xF0E3, 0x9021, 0xF1E4, 0x9022, 0xDCF1, 0x9023, 0xD6A7, 0x902E, 0xF4F5, 0x9031, 0xF1CE, 0x9032, 0xF2E4,
+ 0x9035, 0xD0B0, 0x9038, 0xECEF, 0x903C, 0xF9BA, 0x903E, 0xEBB5, 0x9041, 0xD4ED, 0x9042, 0xE2C4, 0x9047, 0xE9E7, 0x904A, 0xEBB4,
+ 0x904B, 0xEAA1, 0x904D, 0xF8BC, 0x904E, 0xCEA6, 0x9050, 0xF9C6, 0x9051, 0xFCDA, 0x9053, 0xD4B3, 0x9054, 0xD3B9, 0x9055, 0xEADE,
+ 0x9059, 0xE9AB, 0x905C, 0xE1E1, 0x905D, 0xD3CF, 0x905E, 0xF4F6, 0x9060, 0xEAC0, 0x9061, 0xE1CF, 0x9063, 0xCCBA, 0x9069, 0xEEEA,
+ 0x906D, 0xF0E4, 0x906E, 0xF3B4, 0x906F, 0xD4EE, 0x9072, 0xF2C0, 0x9075, 0xF1E5, 0x9077, 0xF4C3, 0x9078, 0xE0D4, 0x907A, 0xEBB6,
+ 0x907C, 0xD7A1, 0x907D, 0xCBE8, 0x907F, 0xF9AD, 0x9080, 0xE9AD, 0x9081, 0xD8E4, 0x9082, 0xFAB3, 0x9083, 0xE2C5, 0x9084, 0xFCBD,
+ 0x9087, 0xECC4, 0x9088, 0xD8B1, 0x908A, 0xDCAB, 0x908F, 0xD5A4, 0x9091, 0xEBE9, 0x9095, 0xE8BB, 0x9099, 0xD8D7, 0x90A2, 0xFBAE,
+ 0x90A3, 0xD1E1, 0x90A6, 0xDBC0, 0x90A8, 0xF5BE, 0x90AA, 0xDEF7, 0x90AF, 0xCAFB, 0x90B0, 0xF7C6, 0x90B1, 0xCFC8, 0x90B5, 0xE1D0,
+ 0x90B8, 0xEED0, 0x90C1, 0xE9F4, 0x90CA, 0xCEF4, 0x90DE, 0xD5CD, 0x90E1, 0xCFDB, 0x90E8, 0xDDBB, 0x90ED, 0xCEAC, 0x90F5, 0xE9E8,
+ 0x90FD, 0xD4B4, 0x9102, 0xE4C7, 0x9112, 0xF5DB, 0x9115, 0xFAC1, 0x9119, 0xDEA9, 0x9127, 0xD4F8, 0x912D, 0xEFF7, 0x9132, 0xD3B3,
+ 0x9149, 0xEBB7, 0x914A, 0xEFF8, 0x914B, 0xF5DC, 0x914C, 0xEDCC, 0x914D, 0xDBD5, 0x914E, 0xF1CF, 0x9152, 0xF1D0, 0x9162, 0xF5B2,
+ 0x9169, 0xD9AE, 0x916A, 0xD5AC, 0x916C, 0xE2C6, 0x9175, 0xFDA3, 0x9177, 0xFBE5, 0x9178, 0xDFAB, 0x9187, 0xE2F5, 0x9189, 0xF6AD,
+ 0x918B, 0xF5B3, 0x918D, 0xF0B5, 0x9192, 0xE1A5, 0x919C, 0xF5DD, 0x91AB, 0xECA2, 0x91AC, 0xEDFD, 0x91AE, 0xF5B4, 0x91AF, 0xFBB8,
+ 0x91B1, 0xDBA3, 0x91B4, 0xD6CA, 0x91B5, 0xCBD9, 0x91C0, 0xE5D4, 0x91C7, 0xF3FA, 0x91C9, 0xEBB8, 0x91CB, 0xE0B7, 0x91CC, 0xD7EC,
+ 0x91CD, 0xF1EC, 0x91CE, 0xE5AF, 0x91CF, 0xD5E1, 0x91D0, 0xD7ED, 0x91D1, 0xD1D1, 0x91D7, 0xE1F2, 0x91D8, 0xEFF9, 0x91DC, 0xDDBC,
+ 0x91DD, 0xF6DC, 0x91E3, 0xF0E5, 0x91E7, 0xF4C4, 0x91EA, 0xE9E9, 0x91F5, 0xF3FB, 0x920D, 0xD4EF, 0x9210, 0xCCA2, 0x9211, 0xF7FE,
+ 0x9212, 0xDFBC, 0x9217, 0xEBCD, 0x921E, 0xD0B7, 0x9234, 0xD6C2, 0x923A, 0xE8AD, 0x923F, 0xEFAF, 0x9240, 0xCBA5, 0x9245, 0xCBE9,
+ 0x9249, 0xFAE8, 0x9257, 0xCCC6, 0x925B, 0xE6E7, 0x925E, 0xEAC7, 0x9262, 0xDBA4, 0x9264, 0xCFC9, 0x9265, 0xE2FC, 0x9266, 0xEFFA,
+ 0x9280, 0xEBDE, 0x9283, 0xF5C8, 0x9285, 0xD4DE, 0x9291, 0xE0D5, 0x9293, 0xEFB0, 0x9296, 0xE2C7, 0x9298, 0xD9AF, 0x929C, 0xF9E7,
+ 0x92B3, 0xE7E5, 0x92B6, 0xCFCA, 0x92B7, 0xE1D1, 0x92B9, 0xE2C8, 0x92CC, 0xEFFB, 0x92CF, 0xFAF9, 0x92D2, 0xDCF2, 0x92E4, 0xE0A7,
+ 0x92EA, 0xF8E8, 0x92F8, 0xCBEA, 0x92FC, 0xCBBC, 0x9304, 0xD6E2, 0x9310, 0xF5DE, 0x9318, 0xF5DF, 0x931A, 0xEEB6, 0x931E, 0xE2F6,
+ 0x931F, 0xD3CA, 0x9320, 0xEFFC, 0x9321, 0xD1C4, 0x9322, 0xEFB1, 0x9324, 0xD1C5, 0x9326, 0xD0DE, 0x9328, 0xD9E1, 0x932B, 0xE0B8,
+ 0x932E, 0xCDD1, 0x932F, 0xF3B9, 0x9348, 0xE7CC, 0x934A, 0xD6A8, 0x934B, 0xCEA7, 0x934D, 0xD4B5, 0x9354, 0xE4C8, 0x935B, 0xD3B4,
+ 0x936E, 0xEBB9, 0x9375, 0xCBF5, 0x937C, 0xF6DD, 0x937E, 0xF1A3, 0x938C, 0xCCC7, 0x9394, 0xE9CA, 0x9396, 0xE1F0, 0x939A, 0xF5E0,
+ 0x93A3, 0xFBAF, 0x93A7, 0xCBD1, 0x93AC, 0xFBE0, 0x93AD, 0xF2E5, 0x93B0, 0xECF0, 0x93C3, 0xF0EC, 0x93D1, 0xEEEB, 0x93DE, 0xE9CB,
+ 0x93E1, 0xCCF0, 0x93E4, 0xD7AF, 0x93F6, 0xF3A1, 0x9404, 0xFCF5, 0x9418, 0xF1A4, 0x9425, 0xE0D6, 0x942B, 0xEFB2, 0x9435, 0xF4D1,
+ 0x9438, 0xF7A1, 0x9444, 0xF1D1, 0x9451, 0xCAFC, 0x9452, 0xCAFD, 0x945B, 0xCECE, 0x947D, 0xF3C8, 0x947F, 0xF3BA, 0x9577, 0xEDFE,
+ 0x9580, 0xDAA6, 0x9583, 0xE0EC, 0x9589, 0xF8CD, 0x958B, 0xCBD2, 0x958F, 0xEBCE, 0x9591, 0xF9D8, 0x9592, 0xF9D9, 0x9593, 0xCAE0,
+ 0x9594, 0xDACA, 0x9598, 0xCBA6, 0x95A3, 0xCAC8, 0x95A4, 0xF9EE, 0x95A5, 0xDBEC, 0x95A8, 0xD0B1, 0x95AD, 0xD5EF, 0x95B1, 0xE6F3,
+ 0x95BB, 0xE7A2, 0x95BC, 0xE4D9, 0x95C7, 0xE4E1, 0x95CA, 0xFCC4, 0x95D4, 0xF9EF, 0x95D5, 0xCFF4, 0x95D6, 0xF7E6, 0x95DC, 0xCEBC,
+ 0x95E1, 0xF4C5, 0x95E2, 0xDCA3, 0x961C, 0xDDBD, 0x9621, 0xF4C6, 0x962A, 0xF8A1, 0x962E, 0xE8D6, 0x9632, 0xDBC1, 0x963B, 0xF0E6,
+ 0x963F, 0xE4B9, 0x9640, 0xF6ED, 0x9642, 0xF9AE, 0x9644, 0xDDBE, 0x964B, 0xD7B0, 0x964C, 0xD8E8, 0x964D, 0xCBBD, 0x9650, 0xF9DA,
+ 0x965B, 0xF8CE, 0x965C, 0xF9F0, 0x965D, 0xE0ED, 0x965E, 0xE3B3, 0x965F, 0xF4B3, 0x9662, 0xEAC2, 0x9663, 0xF2E6, 0x9664, 0xF0B6,
+ 0x966A, 0xDBD6, 0x9670, 0xEBE4, 0x9673, 0xF2E7, 0x9675, 0xD7D5, 0x9676, 0xD4B6, 0x9677, 0xF9E8, 0x9678, 0xD7C1, 0x967D, 0xE5D5,
+ 0x9685, 0xE9EA, 0x9686, 0xD7CC, 0x968A, 0xD3E9, 0x968B, 0xE2C9, 0x968D, 0xFCDB, 0x968E, 0xCDAD, 0x9694, 0xCCB0, 0x9695, 0xEAA2,
+ 0x9698, 0xE4F6, 0x9699, 0xD0C0, 0x969B, 0xF0B7, 0x969C, 0xEEA1, 0x96A3, 0xD7F6, 0x96A7, 0xE2CA, 0x96A8, 0xE2CB, 0x96AA, 0xFACF,
+ 0x96B1, 0xEBDF, 0x96B7, 0xD6CB, 0x96BB, 0xF4B4, 0x96C0, 0xEDCD, 0x96C1, 0xE4D2, 0x96C4, 0xEAA9, 0x96C5, 0xE4BA, 0x96C6, 0xF3A2,
+ 0x96C7, 0xCDD2, 0x96C9, 0xF6CB, 0x96CB, 0xF1E6, 0x96CC, 0xEDC1, 0x96CD, 0xE8BC, 0x96CE, 0xEED1, 0x96D5, 0xF0E7, 0x96D6, 0xE2CC,
+ 0x96D9, 0xE4AA, 0x96DB, 0xF5E1, 0x96DC, 0xEDDA, 0x96E2, 0xD7EE, 0x96E3, 0xD1F1, 0x96E8, 0xE9EB, 0x96E9, 0xE9EC, 0x96EA, 0xE0E4,
+ 0x96EF, 0xDAA7, 0x96F0, 0xDDD4, 0x96F2, 0xEAA3, 0x96F6, 0xD6C3, 0x96F7, 0xD6F4, 0x96F9, 0xDADF, 0x96FB, 0xEFB3, 0x9700, 0xE2CD,
+ 0x9706, 0xEFFD, 0x9707, 0xF2E8, 0x9711, 0xEFC5, 0x9713, 0xE7E7, 0x9716, 0xD7FD, 0x9719, 0xE7CE, 0x971C, 0xDFDC, 0x971E, 0xF9C7,
+ 0x9727, 0xD9F6, 0x9730, 0xDFAC, 0x9732, 0xD6DA, 0x9739, 0xDCA4, 0x973D, 0xF0B8, 0x9742, 0xD5FA, 0x9744, 0xE4F7, 0x9748, 0xD6C4,
+ 0x9751, 0xF4EC, 0x9756, 0xEFFE, 0x975C, 0xF0A1, 0x975E, 0xDEAA, 0x9761, 0xDABC, 0x9762, 0xD8FC, 0x9769, 0xFAD4, 0x976D, 0xECE5,
+ 0x9774, 0xFCA8, 0x9777, 0xECE6, 0x977A, 0xD8CB, 0x978B, 0xFBB9, 0x978D, 0xE4D3, 0x978F, 0xCDF9, 0x97A0, 0xCFD3, 0x97A8, 0xCAEA,
+ 0x97AB, 0xCFD4, 0x97AD, 0xF8BD, 0x97C6, 0xF4C7, 0x97CB, 0xEADF, 0x97D3, 0xF9DB, 0x97DC, 0xD4B7, 0x97F3, 0xEBE5, 0x97F6, 0xE1D2,
+ 0x97FB, 0xEAA4, 0x97FF, 0xFAC2, 0x9800, 0xFBE1, 0x9801, 0xFAED, 0x9802, 0xF0A2, 0x9803, 0xCCF1, 0x9805, 0xFAA3, 0x9806, 0xE2F7,
+ 0x9808, 0xE2CE, 0x980A, 0xE9F5, 0x980C, 0xE1EB, 0x9810, 0xE7E8, 0x9811, 0xE8D7, 0x9812, 0xDAF8, 0x9813, 0xD4CB, 0x9817, 0xF7F6,
+ 0x9818, 0xD6C5, 0x982D, 0xD4E9, 0x9830, 0xFAFA, 0x9838, 0xCCF2, 0x9839, 0xF7DD, 0x983B, 0xDEBA, 0x9846, 0xCEA8, 0x984C, 0xF0B9,
+ 0x984D, 0xE4FE, 0x984E, 0xE4C9, 0x9854, 0xE4D4, 0x9858, 0xEAC3, 0x985A, 0xEFB4, 0x985E, 0xD7BE, 0x9865, 0xFBE2, 0x9867, 0xCDD3,
+ 0x986B, 0xEFB5, 0x986F, 0xFAE9, 0x98A8, 0xF9A6, 0x98AF, 0xDFBD, 0x98B1, 0xF7C7, 0x98C4, 0xF8FD, 0x98C7, 0xF8FC, 0x98DB, 0xDEAB,
+ 0x98DC, 0xDBE8, 0x98DF, 0xE3DD, 0x98E1, 0xE1E2, 0x98E2, 0xD1C6, 0x98ED, 0xF6D0, 0x98EE, 0xEBE6, 0x98EF, 0xDAF9, 0x98F4, 0xECC7,
+ 0x98FC, 0xDEF8, 0x98FD, 0xF8E9, 0x98FE, 0xE3DE, 0x9903, 0xCEF5, 0x9909, 0xFAC3, 0x990A, 0xE5D7, 0x990C, 0xECC8, 0x9910, 0xF3C9,
+ 0x9913, 0xE4BB, 0x9918, 0xE6AE, 0x991E, 0xEFB6, 0x9920, 0xDCBF, 0x9928, 0xCEBD, 0x9945, 0xD8C3, 0x9949, 0xD0CF, 0x994B, 0xCFFA,
+ 0x994C, 0xF3CA, 0x994D, 0xE0D7, 0x9951, 0xD1C7, 0x9952, 0xE9AE, 0x9954, 0xE8BD, 0x9957, 0xFAC4, 0x9996, 0xE2CF, 0x9999, 0xFAC5,
+ 0x999D, 0xF9B8, 0x99A5, 0xDCE0, 0x99A8, 0xFBB0, 0x99AC, 0xD8A9, 0x99AD, 0xE5DF, 0x99AE, 0xF9A7, 0x99B1, 0xF6EE, 0x99B3, 0xF6CC,
+ 0x99B4, 0xE2F8, 0x99B9, 0xECF1, 0x99C1, 0xDAE0, 0x99D0, 0xF1D2, 0x99D1, 0xD2CC, 0x99D2, 0xCFCB, 0x99D5, 0xCABD, 0x99D9, 0xDDBF,
+ 0x99DD, 0xF6EF, 0x99DF, 0xDEF9, 0x99ED, 0xFAB4, 0x99F1, 0xD5AD, 0x99FF, 0xF1E7, 0x9A01, 0xDEBE, 0x9A08, 0xDCC0, 0x9A0E, 0xD1C8,
+ 0x9A0F, 0xD1C9, 0x9A19, 0xF8BE, 0x9A2B, 0xCBF6, 0x9A30, 0xD4F9, 0x9A36, 0xF5E2, 0x9A37, 0xE1D3, 0x9A40, 0xD8E9, 0x9A43, 0xF8FE,
+ 0x9A45, 0xCFCC, 0x9A4D, 0xFDA4, 0x9A55, 0xCEF6, 0x9A57, 0xFAD0, 0x9A5A, 0xCCF3, 0x9A5B, 0xE6BE, 0x9A5F, 0xF6AE, 0x9A62, 0xD5F0,
+ 0x9A65, 0xD1CA, 0x9A69, 0xFCBE, 0x9A6A, 0xD5F1, 0x9AA8, 0xCDE9, 0x9AB8, 0xFAB5, 0x9AD3, 0xE2D0, 0x9AD4, 0xF4F7, 0x9AD8, 0xCDD4,
+ 0x9AE5, 0xE7A3, 0x9AEE, 0xDBA5, 0x9B1A, 0xE2D1, 0x9B27, 0xD7A2, 0x9B2A, 0xF7E3, 0x9B31, 0xEAA6, 0x9B3C, 0xD0A1, 0x9B41, 0xCEDA,
+ 0x9B42, 0xFBEB, 0x9B43, 0xDBA6, 0x9B44, 0xDBDE, 0x9B45, 0xD8E5, 0x9B4F, 0xEAE0, 0x9B54, 0xD8AA, 0x9B5A, 0xE5E0, 0x9B6F, 0xD6DB,
+ 0x9B8E, 0xEFC6, 0x9B91, 0xF8EA, 0x9B9F, 0xE4D5, 0x9BAB, 0xCEF7, 0x9BAE, 0xE0D8, 0x9BC9, 0xD7EF, 0x9BD6, 0xF4ED, 0x9BE4, 0xCDE6,
+ 0x9BE8, 0xCCF4, 0x9C0D, 0xF5E3, 0x9C10, 0xE4CA, 0x9C12, 0xDCE1, 0x9C15, 0xF9C8, 0x9C25, 0xFCBF, 0x9C32, 0xE8A7, 0x9C3B, 0xD8C4,
+ 0x9C47, 0xCBBE, 0x9C49, 0xDCAE, 0x9C57, 0xD7F7, 0x9CE5, 0xF0E8, 0x9CE7, 0xDDC0, 0x9CE9, 0xCFCD, 0x9CF3, 0xDCF3, 0x9CF4, 0xD9B0,
+ 0x9CF6, 0xE6E9, 0x9D09, 0xE4BC, 0x9D1B, 0xEAC4, 0x9D26, 0xE4EC, 0x9D28, 0xE4E5, 0x9D3B, 0xFBF8, 0x9D51, 0xCCBB, 0x9D5D, 0xE4BD,
+ 0x9D60, 0xCDDC, 0x9D61, 0xD9F7, 0x9D6C, 0xDDDF, 0x9D72, 0xEDCE, 0x9DA9, 0xD9D0, 0x9DAF, 0xE5A3, 0x9DB4, 0xF9CD, 0x9DC4, 0xCDAE,
+ 0x9DD7, 0xCFCE, 0x9DF2, 0xF6AF, 0x9DF8, 0xFDD3, 0x9DF9, 0xEBED, 0x9DFA, 0xD6DC, 0x9E1A, 0xE5A4, 0x9E1E, 0xD5B6, 0x9E75, 0xD6DD,
+ 0x9E79, 0xF9E9, 0x9E7D, 0xE7A4, 0x9E7F, 0xD6E3, 0x9E92, 0xD1CB, 0x9E93, 0xD6E4, 0x9E97, 0xD5F2, 0x9E9D, 0xDEFA, 0x9E9F, 0xD7F8,
+ 0x9EA5, 0xD8EA, 0x9EB4, 0xCFD5, 0x9EB5, 0xD8FD, 0x9EBB, 0xD8AB, 0x9EBE, 0xFDCB, 0x9EC3, 0xFCDC, 0x9ECD, 0xE0A8, 0x9ECE, 0xD5F3,
+ 0x9ED1, 0xFDD9, 0x9ED4, 0xCCA3, 0x9ED8, 0xD9F9, 0x9EDB, 0xD3EA, 0x9EDC, 0xF5F5, 0x9EDE, 0xEFC7, 0x9EE8, 0xD3DA, 0x9EF4, 0xDABD,
+ 0x9F07, 0xE8A8, 0x9F08, 0xDCAF, 0x9F0E, 0xF0A3, 0x9F13, 0xCDD5, 0x9F20, 0xE0A9, 0x9F3B, 0xDEAC, 0x9F4A, 0xF0BA, 0x9F4B, 0xEEB1,
+ 0x9F4E, 0xEEB2, 0x9F52, 0xF6CD, 0x9F5F, 0xEED2, 0x9F61, 0xD6C6, 0x9F67, 0xE0E5, 0x9F6A, 0xF3BB, 0x9F6C, 0xE5E1, 0x9F77, 0xE4CB,
+ 0x9F8D, 0xD7A3, 0x9F90, 0xDBC2, 0x9F95, 0xCAFE, 0x9F9C, 0xCFCF, 0xAC00, 0xB0A1, 0xAC01, 0xB0A2, 0xAC02, 0x8141, 0xAC03, 0x8142,
+ 0xAC04, 0xB0A3, 0xAC05, 0x8143, 0xAC06, 0x8144, 0xAC07, 0xB0A4, 0xAC08, 0xB0A5, 0xAC09, 0xB0A6, 0xAC0A, 0xB0A7, 0xAC0B, 0x8145,
+ 0xAC0C, 0x8146, 0xAC0D, 0x8147, 0xAC0E, 0x8148, 0xAC0F, 0x8149, 0xAC10, 0xB0A8, 0xAC11, 0xB0A9, 0xAC12, 0xB0AA, 0xAC13, 0xB0AB,
+ 0xAC14, 0xB0AC, 0xAC15, 0xB0AD, 0xAC16, 0xB0AE, 0xAC17, 0xB0AF, 0xAC18, 0x814A, 0xAC19, 0xB0B0, 0xAC1A, 0xB0B1, 0xAC1B, 0xB0B2,
+ 0xAC1C, 0xB0B3, 0xAC1D, 0xB0B4, 0xAC1E, 0x814B, 0xAC1F, 0x814C, 0xAC20, 0xB0B5, 0xAC21, 0x814D, 0xAC22, 0x814E, 0xAC23, 0x814F,
+ 0xAC24, 0xB0B6, 0xAC25, 0x8150, 0xAC26, 0x8151, 0xAC27, 0x8152, 0xAC28, 0x8153, 0xAC29, 0x8154, 0xAC2A, 0x8155, 0xAC2B, 0x8156,
+ 0xAC2C, 0xB0B7, 0xAC2D, 0xB0B8, 0xAC2E, 0x8157, 0xAC2F, 0xB0B9, 0xAC30, 0xB0BA, 0xAC31, 0xB0BB, 0xAC32, 0x8158, 0xAC33, 0x8159,
+ 0xAC34, 0x815A, 0xAC35, 0x8161, 0xAC36, 0x8162, 0xAC37, 0x8163, 0xAC38, 0xB0BC, 0xAC39, 0xB0BD, 0xAC3A, 0x8164, 0xAC3B, 0x8165,
+ 0xAC3C, 0xB0BE, 0xAC3D, 0x8166, 0xAC3E, 0x8167, 0xAC3F, 0x8168, 0xAC40, 0xB0BF, 0xAC41, 0x8169, 0xAC42, 0x816A, 0xAC43, 0x816B,
+ 0xAC44, 0x816C, 0xAC45, 0x816D, 0xAC46, 0x816E, 0xAC47, 0x816F, 0xAC48, 0x8170, 0xAC49, 0x8171, 0xAC4A, 0x8172, 0xAC4B, 0xB0C0,
+ 0xAC4C, 0x8173, 0xAC4D, 0xB0C1, 0xAC4E, 0x8174, 0xAC4F, 0x8175, 0xAC50, 0x8176, 0xAC51, 0x8177, 0xAC52, 0x8178, 0xAC53, 0x8179,
+ 0xAC54, 0xB0C2, 0xAC55, 0x817A, 0xAC56, 0x8181, 0xAC57, 0x8182, 0xAC58, 0xB0C3, 0xAC59, 0x8183, 0xAC5A, 0x8184, 0xAC5B, 0x8185,
+ 0xAC5C, 0xB0C4, 0xAC5D, 0x8186, 0xAC5E, 0x8187, 0xAC5F, 0x8188, 0xAC60, 0x8189, 0xAC61, 0x818A, 0xAC62, 0x818B, 0xAC63, 0x818C,
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+ 0xAF24, 0x8481, 0xAF25, 0x8482, 0xAF26, 0x8483, 0xAF27, 0x8484, 0xAF28, 0x8485, 0xAF29, 0x8486, 0xAF2A, 0x8487, 0xAF2B, 0x8488,
+ 0xAF2C, 0xB2BF, 0xAF2D, 0xB2C0, 0xAF2E, 0x8489, 0xAF2F, 0x848A, 0xAF30, 0xB2C1, 0xAF31, 0x848B, 0xAF32, 0xB2C2, 0xAF33, 0x848C,
+ 0xAF34, 0xB2C3, 0xAF35, 0x848D, 0xAF36, 0x848E, 0xAF37, 0x848F, 0xAF38, 0x8490, 0xAF39, 0x8491, 0xAF3A, 0x8492, 0xAF3B, 0x8493,
+ 0xAF3C, 0xB2C4, 0xAF3D, 0xB2C5, 0xAF3E, 0x8494, 0xAF3F, 0xB2C6, 0xAF40, 0x8495, 0xAF41, 0xB2C7, 0xAF42, 0xB2C8, 0xAF43, 0xB2C9,
+ 0xAF44, 0x8496, 0xAF45, 0x8497, 0xAF46, 0x8498, 0xAF47, 0x8499, 0xAF48, 0xB2CA, 0xAF49, 0xB2CB, 0xAF4A, 0x849A, 0xAF4B, 0x849B,
+ 0xAF4C, 0x849C, 0xAF4D, 0x849D, 0xAF4E, 0x849E, 0xAF4F, 0x849F, 0xAF50, 0xB2CC, 0xAF51, 0x84A0, 0xAF52, 0x84A1, 0xAF53, 0x84A2,
+ 0xAF54, 0x84A3, 0xAF55, 0x84A4, 0xAF56, 0x84A5, 0xAF57, 0x84A6, 0xAF58, 0x84A7, 0xAF59, 0x84A8, 0xAF5A, 0x84A9, 0xAF5B, 0x84AA,
+ 0xAF5C, 0xB2CD, 0xAF5D, 0xB2CE, 0xAF5E, 0x84AB, 0xAF5F, 0x84AC, 0xAF60, 0x84AD, 0xAF61, 0x84AE, 0xAF62, 0x84AF, 0xAF63, 0x84B0,
+ 0xAF64, 0xB2CF, 0xAF65, 0xB2D0, 0xAF66, 0x84B1, 0xAF67, 0x84B2, 0xAF68, 0x84B3, 0xAF69, 0x84B4, 0xAF6A, 0x84B5, 0xAF6B, 0x84B6,
+ 0xAF6C, 0x84B7, 0xAF6D, 0x84B8, 0xAF6E, 0x84B9, 0xAF6F, 0x84BA, 0xAF70, 0x84BB, 0xAF71, 0x84BC, 0xAF72, 0x84BD, 0xAF73, 0x84BE,
+ 0xAF74, 0x84BF, 0xAF75, 0x84C0, 0xAF76, 0x84C1, 0xAF77, 0x84C2, 0xAF78, 0x84C3, 0xAF79, 0xB2D1, 0xAF7A, 0x84C4, 0xAF7B, 0x84C5,
+ 0xAF7C, 0x84C6, 0xAF7D, 0x84C7, 0xAF7E, 0x84C8, 0xAF7F, 0x84C9, 0xAF80, 0xB2D2, 0xAF81, 0x84CA, 0xAF82, 0x84CB, 0xAF83, 0x84CC,
+ 0xAF84, 0xB2D3, 0xAF85, 0x84CD, 0xAF86, 0x84CE, 0xAF87, 0x84CF, 0xAF88, 0xB2D4, 0xAF89, 0x84D0, 0xAF8A, 0x84D1, 0xAF8B, 0x84D2,
+ 0xAF8C, 0x84D3, 0xAF8D, 0x84D4, 0xAF8E, 0x84D5, 0xAF8F, 0x84D6, 0xAF90, 0xB2D5, 0xAF91, 0xB2D6, 0xAF92, 0x84D7, 0xAF93, 0x84D8,
+ 0xAF94, 0x84D9, 0xAF95, 0xB2D7, 0xAF96, 0x84DA, 0xAF97, 0x84DB, 0xAF98, 0x84DC, 0xAF99, 0x84DD, 0xAF9A, 0x84DE, 0xAF9B, 0x84DF,
+ 0xAF9C, 0xB2D8, 0xAF9D, 0x84E0, 0xAF9E, 0x84E1, 0xAF9F, 0x84E2, 0xAFA0, 0x84E3, 0xAFA1, 0x84E4, 0xAFA2, 0x84E5, 0xAFA3, 0x84E6,
+ 0xAFA4, 0x84E7, 0xAFA5, 0x84E8, 0xAFA6, 0x84E9, 0xAFA7, 0x84EA, 0xAFA8, 0x84EB, 0xAFA9, 0x84EC, 0xAFAA, 0x84ED, 0xAFAB, 0x84EE,
+ 0xAFAC, 0x84EF, 0xAFAD, 0x84F0, 0xAFAE, 0x84F1, 0xAFAF, 0x84F2, 0xAFB0, 0x84F3, 0xAFB1, 0x84F4, 0xAFB2, 0x84F5, 0xAFB3, 0x84F6,
+ 0xAFB4, 0x84F7, 0xAFB5, 0x84F8, 0xAFB6, 0x84F9, 0xAFB7, 0x84FA, 0xAFB8, 0xB2D9, 0xAFB9, 0xB2DA, 0xAFBA, 0x84FB, 0xAFBB, 0x84FC,
+ 0xAFBC, 0xB2DB, 0xAFBD, 0x84FD, 0xAFBE, 0x84FE, 0xAFBF, 0x8541, 0xAFC0, 0xB2DC, 0xAFC1, 0x8542, 0xAFC2, 0x8543, 0xAFC3, 0x8544,
+ 0xAFC4, 0x8545, 0xAFC5, 0x8546, 0xAFC6, 0x8547, 0xAFC7, 0xB2DD, 0xAFC8, 0xB2DE, 0xAFC9, 0xB2DF, 0xAFCA, 0x8548, 0xAFCB, 0xB2E0,
+ 0xAFCC, 0x8549, 0xAFCD, 0xB2E1, 0xAFCE, 0xB2E2, 0xAFCF, 0x854A, 0xAFD0, 0x854B, 0xAFD1, 0x854C, 0xAFD2, 0x854D, 0xAFD3, 0x854E,
+ 0xAFD4, 0xB2E3, 0xAFD5, 0x854F, 0xAFD6, 0x8550, 0xAFD7, 0x8551, 0xAFD8, 0x8552, 0xAFD9, 0x8553, 0xAFDA, 0x8554, 0xAFDB, 0x8555,
+ 0xAFDC, 0xB2E4, 0xAFDD, 0x8556, 0xAFDE, 0x8557, 0xAFDF, 0x8558, 0xAFE0, 0x8559, 0xAFE1, 0x855A, 0xAFE2, 0x8561, 0xAFE3, 0x8562,
+ 0xAFE4, 0x8563, 0xAFE5, 0x8564, 0xAFE6, 0x8565, 0xAFE7, 0x8566, 0xAFE8, 0xB2E5, 0xAFE9, 0xB2E6, 0xAFEA, 0x8567, 0xAFEB, 0x8568,
+ 0xAFEC, 0x8569, 0xAFED, 0x856A, 0xAFEE, 0x856B, 0xAFEF, 0x856C, 0xAFF0, 0xB2E7, 0xAFF1, 0xB2E8, 0xAFF2, 0x856D, 0xAFF3, 0x856E,
+ 0xAFF4, 0xB2E9, 0xAFF5, 0x856F, 0xAFF6, 0x8570, 0xAFF7, 0x8571, 0xAFF8, 0xB2EA, 0xAFF9, 0x8572, 0xAFFA, 0x8573, 0xAFFB, 0x8574,
+ 0xAFFC, 0x8575, 0xAFFD, 0x8576, 0xAFFE, 0x8577, 0xAFFF, 0x8578, 0xB000, 0xB2EB, 0xB001, 0xB2EC, 0xB002, 0x8579, 0xB003, 0x857A,
+ 0xB004, 0xB2ED, 0xB005, 0x8581, 0xB006, 0x8582, 0xB007, 0x8583, 0xB008, 0x8584, 0xB009, 0x8585, 0xB00A, 0x8586, 0xB00B, 0x8587,
+ 0xB00C, 0xB2EE, 0xB00D, 0x8588, 0xB00E, 0x8589, 0xB00F, 0x858A, 0xB010, 0xB2EF, 0xB011, 0x858B, 0xB012, 0x858C, 0xB013, 0x858D,
+ 0xB014, 0xB2F0, 0xB015, 0x858E, 0xB016, 0x858F, 0xB017, 0x8590, 0xB018, 0x8591, 0xB019, 0x8592, 0xB01A, 0x8593, 0xB01B, 0x8594,
+ 0xB01C, 0xB2F1, 0xB01D, 0xB2F2, 0xB01E, 0x8595, 0xB01F, 0x8596, 0xB020, 0x8597, 0xB021, 0x8598, 0xB022, 0x8599, 0xB023, 0x859A,
+ 0xB024, 0x859B, 0xB025, 0x859C, 0xB026, 0x859D, 0xB027, 0x859E, 0xB028, 0xB2F3, 0xB029, 0x859F, 0xB02A, 0x85A0, 0xB02B, 0x85A1,
+ 0xB02C, 0x85A2, 0xB02D, 0x85A3, 0xB02E, 0x85A4, 0xB02F, 0x85A5, 0xB030, 0x85A6, 0xB031, 0x85A7, 0xB032, 0x85A8, 0xB033, 0x85A9,
+ 0xB034, 0x85AA, 0xB035, 0x85AB, 0xB036, 0x85AC, 0xB037, 0x85AD, 0xB038, 0x85AE, 0xB039, 0x85AF, 0xB03A, 0x85B0, 0xB03B, 0x85B1,
+ 0xB03C, 0x85B2, 0xB03D, 0x85B3, 0xB03E, 0x85B4, 0xB03F, 0x85B5, 0xB040, 0x85B6, 0xB041, 0x85B7, 0xB042, 0x85B8, 0xB043, 0x85B9,
+ 0xB044, 0xB2F4, 0xB045, 0xB2F5, 0xB046, 0x85BA, 0xB047, 0x85BB, 0xB048, 0xB2F6, 0xB049, 0x85BC, 0xB04A, 0xB2F7, 0xB04B, 0x85BD,
+ 0xB04C, 0xB2F8, 0xB04D, 0x85BE, 0xB04E, 0xB2F9, 0xB04F, 0x85BF, 0xB050, 0x85C0, 0xB051, 0x85C1, 0xB052, 0x85C2, 0xB053, 0xB2FA,
+ 0xB054, 0xB2FB, 0xB055, 0xB2FC, 0xB056, 0x85C3, 0xB057, 0xB2FD, 0xB058, 0x85C4, 0xB059, 0xB2FE, 0xB05A, 0x85C5, 0xB05B, 0x85C6,
+ 0xB05C, 0x85C7, 0xB05D, 0xB3A1, 0xB05E, 0x85C8, 0xB05F, 0x85C9, 0xB060, 0x85CA, 0xB061, 0x85CB, 0xB062, 0x85CC, 0xB063, 0x85CD,
+ 0xB064, 0x85CE, 0xB065, 0x85CF, 0xB066, 0x85D0, 0xB067, 0x85D1, 0xB068, 0x85D2, 0xB069, 0x85D3, 0xB06A, 0x85D4, 0xB06B, 0x85D5,
+ 0xB06C, 0x85D6, 0xB06D, 0x85D7, 0xB06E, 0x85D8, 0xB06F, 0x85D9, 0xB070, 0x85DA, 0xB071, 0x85DB, 0xB072, 0x85DC, 0xB073, 0x85DD,
+ 0xB074, 0x85DE, 0xB075, 0x85DF, 0xB076, 0x85E0, 0xB077, 0x85E1, 0xB078, 0x85E2, 0xB079, 0x85E3, 0xB07A, 0x85E4, 0xB07B, 0x85E5,
+ 0xB07C, 0xB3A2, 0xB07D, 0xB3A3, 0xB07E, 0x85E6, 0xB07F, 0x85E7, 0xB080, 0xB3A4, 0xB081, 0x85E8, 0xB082, 0x85E9, 0xB083, 0x85EA,
+ 0xB084, 0xB3A5, 0xB085, 0x85EB, 0xB086, 0x85EC, 0xB087, 0x85ED, 0xB088, 0x85EE, 0xB089, 0x85EF, 0xB08A, 0x85F0, 0xB08B, 0x85F1,
+ 0xB08C, 0xB3A6, 0xB08D, 0xB3A7, 0xB08E, 0x85F2, 0xB08F, 0xB3A8, 0xB090, 0x85F3, 0xB091, 0xB3A9, 0xB092, 0x85F4, 0xB093, 0x85F5,
+ 0xB094, 0x85F6, 0xB095, 0x85F7, 0xB096, 0x85F8, 0xB097, 0x85F9, 0xB098, 0xB3AA, 0xB099, 0xB3AB, 0xB09A, 0xB3AC, 0xB09B, 0x85FA,
+ 0xB09C, 0xB3AD, 0xB09D, 0x85FB, 0xB09E, 0x85FC, 0xB09F, 0xB3AE, 0xB0A0, 0xB3AF, 0xB0A1, 0xB3B0, 0xB0A2, 0xB3B1, 0xB0A3, 0x85FD,
+ 0xB0A4, 0x85FE, 0xB0A5, 0x8641, 0xB0A6, 0x8642, 0xB0A7, 0x8643, 0xB0A8, 0xB3B2, 0xB0A9, 0xB3B3, 0xB0AA, 0x8644, 0xB0AB, 0xB3B4,
+ 0xB0AC, 0xB3B5, 0xB0AD, 0xB3B6, 0xB0AE, 0xB3B7, 0xB0AF, 0xB3B8, 0xB0B0, 0x8645, 0xB0B1, 0xB3B9, 0xB0B2, 0x8646, 0xB0B3, 0xB3BA,
+ 0xB0B4, 0xB3BB, 0xB0B5, 0xB3BC, 0xB0B6, 0x8647, 0xB0B7, 0x8648, 0xB0B8, 0xB3BD, 0xB0B9, 0x8649, 0xB0BA, 0x864A, 0xB0BB, 0x864B,
+ 0xB0BC, 0xB3BE, 0xB0BD, 0x864C, 0xB0BE, 0x864D, 0xB0BF, 0x864E, 0xB0C0, 0x864F, 0xB0C1, 0x8650, 0xB0C2, 0x8651, 0xB0C3, 0x8652,
+ 0xB0C4, 0xB3BF, 0xB0C5, 0xB3C0, 0xB0C6, 0x8653, 0xB0C7, 0xB3C1, 0xB0C8, 0xB3C2, 0xB0C9, 0xB3C3, 0xB0CA, 0x8654, 0xB0CB, 0x8655,
+ 0xB0CC, 0x8656, 0xB0CD, 0x8657, 0xB0CE, 0x8658, 0xB0CF, 0x8659, 0xB0D0, 0xB3C4, 0xB0D1, 0xB3C5, 0xB0D2, 0x865A, 0xB0D3, 0x8661,
+ 0xB0D4, 0xB3C6, 0xB0D5, 0x8662, 0xB0D6, 0x8663, 0xB0D7, 0x8664, 0xB0D8, 0xB3C7, 0xB0D9, 0x8665, 0xB0DA, 0x8666, 0xB0DB, 0x8667,
+ 0xB0DC, 0x8668, 0xB0DD, 0x8669, 0xB0DE, 0x866A, 0xB0DF, 0x866B, 0xB0E0, 0xB3C8, 0xB0E1, 0x866C, 0xB0E2, 0x866D, 0xB0E3, 0x866E,
+ 0xB0E4, 0x866F, 0xB0E5, 0xB3C9, 0xB0E6, 0x8670, 0xB0E7, 0x8671, 0xB0E8, 0x8672, 0xB0E9, 0x8673, 0xB0EA, 0x8674, 0xB0EB, 0x8675,
+ 0xB0EC, 0x8676, 0xB0ED, 0x8677, 0xB0EE, 0x8678, 0xB0EF, 0x8679, 0xB0F0, 0x867A, 0xB0F1, 0x8681, 0xB0F2, 0x8682, 0xB0F3, 0x8683,
+ 0xB0F4, 0x8684, 0xB0F5, 0x8685, 0xB0F6, 0x8686, 0xB0F7, 0x8687, 0xB0F8, 0x8688, 0xB0F9, 0x8689, 0xB0FA, 0x868A, 0xB0FB, 0x868B,
+ 0xB0FC, 0x868C, 0xB0FD, 0x868D, 0xB0FE, 0x868E, 0xB0FF, 0x868F, 0xB100, 0x8690, 0xB101, 0x8691, 0xB102, 0x8692, 0xB103, 0x8693,
+ 0xB104, 0x8694, 0xB105, 0x8695, 0xB106, 0x8696, 0xB107, 0x8697, 0xB108, 0xB3CA, 0xB109, 0xB3CB, 0xB10A, 0x8698, 0xB10B, 0xB3CC,
+ 0xB10C, 0xB3CD, 0xB10D, 0x8699, 0xB10E, 0x869A, 0xB10F, 0x869B, 0xB110, 0xB3CE, 0xB111, 0x869C, 0xB112, 0xB3CF, 0xB113, 0xB3D0,
+ 0xB114, 0x869D, 0xB115, 0x869E, 0xB116, 0x869F, 0xB117, 0x86A0, 0xB118, 0xB3D1, 0xB119, 0xB3D2, 0xB11A, 0x86A1, 0xB11B, 0xB3D3,
+ 0xB11C, 0xB3D4, 0xB11D, 0xB3D5, 0xB11E, 0x86A2, 0xB11F, 0x86A3, 0xB120, 0x86A4, 0xB121, 0x86A5, 0xB122, 0x86A6, 0xB123, 0xB3D6,
+ 0xB124, 0xB3D7, 0xB125, 0xB3D8, 0xB126, 0x86A7, 0xB127, 0x86A8, 0xB128, 0xB3D9, 0xB129, 0x86A9, 0xB12A, 0x86AA, 0xB12B, 0x86AB,
+ 0xB12C, 0xB3DA, 0xB12D, 0x86AC, 0xB12E, 0x86AD, 0xB12F, 0x86AE, 0xB130, 0x86AF, 0xB131, 0x86B0, 0xB132, 0x86B1, 0xB133, 0x86B2,
+ 0xB134, 0xB3DB, 0xB135, 0xB3DC, 0xB136, 0x86B3, 0xB137, 0xB3DD, 0xB138, 0xB3DE, 0xB139, 0xB3DF, 0xB13A, 0x86B4, 0xB13B, 0x86B5,
+ 0xB13C, 0x86B6, 0xB13D, 0x86B7, 0xB13E, 0x86B8, 0xB13F, 0x86B9, 0xB140, 0xB3E0, 0xB141, 0xB3E1, 0xB142, 0x86BA, 0xB143, 0x86BB,
+ 0xB144, 0xB3E2, 0xB145, 0x86BC, 0xB146, 0x86BD, 0xB147, 0x86BE, 0xB148, 0xB3E3, 0xB149, 0x86BF, 0xB14A, 0x86C0, 0xB14B, 0x86C1,
+ 0xB14C, 0x86C2, 0xB14D, 0x86C3, 0xB14E, 0x86C4, 0xB14F, 0x86C5, 0xB150, 0xB3E4, 0xB151, 0xB3E5, 0xB152, 0x86C6, 0xB153, 0x86C7,
+ 0xB154, 0xB3E6, 0xB155, 0xB3E7, 0xB156, 0x86C8, 0xB157, 0x86C9, 0xB158, 0xB3E8, 0xB159, 0x86CA, 0xB15A, 0x86CB, 0xB15B, 0x86CC,
+ 0xB15C, 0xB3E9, 0xB15D, 0x86CD, 0xB15E, 0x86CE, 0xB15F, 0x86CF, 0xB160, 0xB3EA, 0xB161, 0x86D0, 0xB162, 0x86D1, 0xB163, 0x86D2,
+ 0xB164, 0x86D3, 0xB165, 0x86D4, 0xB166, 0x86D5, 0xB167, 0x86D6, 0xB168, 0x86D7, 0xB169, 0x86D8, 0xB16A, 0x86D9, 0xB16B, 0x86DA,
+ 0xB16C, 0x86DB, 0xB16D, 0x86DC, 0xB16E, 0x86DD, 0xB16F, 0x86DE, 0xB170, 0x86DF, 0xB171, 0x86E0, 0xB172, 0x86E1, 0xB173, 0x86E2,
+ 0xB174, 0x86E3, 0xB175, 0x86E4, 0xB176, 0x86E5, 0xB177, 0x86E6, 0xB178, 0xB3EB, 0xB179, 0xB3EC, 0xB17A, 0x86E7, 0xB17B, 0x86E8,
+ 0xB17C, 0xB3ED, 0xB17D, 0x86E9, 0xB17E, 0x86EA, 0xB17F, 0x86EB, 0xB180, 0xB3EE, 0xB181, 0x86EC, 0xB182, 0xB3EF, 0xB183, 0x86ED,
+ 0xB184, 0x86EE, 0xB185, 0x86EF, 0xB186, 0x86F0, 0xB187, 0x86F1, 0xB188, 0xB3F0, 0xB189, 0xB3F1, 0xB18A, 0x86F2, 0xB18B, 0xB3F2,
+ 0xB18C, 0x86F3, 0xB18D, 0xB3F3, 0xB18E, 0x86F4, 0xB18F, 0x86F5, 0xB190, 0x86F6, 0xB191, 0x86F7, 0xB192, 0xB3F4, 0xB193, 0xB3F5,
+ 0xB194, 0xB3F6, 0xB195, 0x86F8, 0xB196, 0x86F9, 0xB197, 0x86FA, 0xB198, 0xB3F7, 0xB199, 0x86FB, 0xB19A, 0x86FC, 0xB19B, 0x86FD,
+ 0xB19C, 0xB3F8, 0xB19D, 0x86FE, 0xB19E, 0x8741, 0xB19F, 0x8742, 0xB1A0, 0x8743, 0xB1A1, 0x8744, 0xB1A2, 0x8745, 0xB1A3, 0x8746,
+ 0xB1A4, 0x8747, 0xB1A5, 0x8748, 0xB1A6, 0x8749, 0xB1A7, 0x874A, 0xB1A8, 0xB3F9, 0xB1A9, 0x874B, 0xB1AA, 0x874C, 0xB1AB, 0x874D,
+ 0xB1AC, 0x874E, 0xB1AD, 0x874F, 0xB1AE, 0x8750, 0xB1AF, 0x8751, 0xB1B0, 0x8752, 0xB1B1, 0x8753, 0xB1B2, 0x8754, 0xB1B3, 0x8755,
+ 0xB1B4, 0x8756, 0xB1B5, 0x8757, 0xB1B6, 0x8758, 0xB1B7, 0x8759, 0xB1B8, 0x875A, 0xB1B9, 0x8761, 0xB1BA, 0x8762, 0xB1BB, 0x8763,
+ 0xB1BC, 0x8764, 0xB1BD, 0x8765, 0xB1BE, 0x8766, 0xB1BF, 0x8767, 0xB1C0, 0x8768, 0xB1C1, 0x8769, 0xB1C2, 0x876A, 0xB1C3, 0x876B,
+ 0xB1C4, 0x876C, 0xB1C5, 0x876D, 0xB1C6, 0x876E, 0xB1C7, 0x876F, 0xB1C8, 0x8770, 0xB1C9, 0x8771, 0xB1CA, 0x8772, 0xB1CB, 0x8773,
+ 0xB1CC, 0xB3FA, 0xB1CD, 0x8774, 0xB1CE, 0x8775, 0xB1CF, 0x8776, 0xB1D0, 0xB3FB, 0xB1D1, 0x8777, 0xB1D2, 0x8778, 0xB1D3, 0x8779,
+ 0xB1D4, 0xB3FC, 0xB1D5, 0x877A, 0xB1D6, 0x8781, 0xB1D7, 0x8782, 0xB1D8, 0x8783, 0xB1D9, 0x8784, 0xB1DA, 0x8785, 0xB1DB, 0x8786,
+ 0xB1DC, 0xB3FD, 0xB1DD, 0xB3FE, 0xB1DE, 0x8787, 0xB1DF, 0xB4A1, 0xB1E0, 0x8788, 0xB1E1, 0x8789, 0xB1E2, 0x878A, 0xB1E3, 0x878B,
+ 0xB1E4, 0x878C, 0xB1E5, 0x878D, 0xB1E6, 0x878E, 0xB1E7, 0x878F, 0xB1E8, 0xB4A2, 0xB1E9, 0xB4A3, 0xB1EA, 0x8790, 0xB1EB, 0x8791,
+ 0xB1EC, 0xB4A4, 0xB1ED, 0x8792, 0xB1EE, 0x8793, 0xB1EF, 0x8794, 0xB1F0, 0xB4A5, 0xB1F1, 0x8795, 0xB1F2, 0x8796, 0xB1F3, 0x8797,
+ 0xB1F4, 0x8798, 0xB1F5, 0x8799, 0xB1F6, 0x879A, 0xB1F7, 0x879B, 0xB1F8, 0x879C, 0xB1F9, 0xB4A6, 0xB1FA, 0x879D, 0xB1FB, 0xB4A7,
+ 0xB1FC, 0x879E, 0xB1FD, 0xB4A8, 0xB1FE, 0x879F, 0xB1FF, 0x87A0, 0xB200, 0x87A1, 0xB201, 0x87A2, 0xB202, 0x87A3, 0xB203, 0x87A4,
+ 0xB204, 0xB4A9, 0xB205, 0xB4AA, 0xB206, 0x87A5, 0xB207, 0x87A6, 0xB208, 0xB4AB, 0xB209, 0x87A7, 0xB20A, 0x87A8, 0xB20B, 0xB4AC,
+ 0xB20C, 0xB4AD, 0xB20D, 0x87A9, 0xB20E, 0x87AA, 0xB20F, 0x87AB, 0xB210, 0x87AC, 0xB211, 0x87AD, 0xB212, 0x87AE, 0xB213, 0x87AF,
+ 0xB214, 0xB4AE, 0xB215, 0xB4AF, 0xB216, 0x87B0, 0xB217, 0xB4B0, 0xB218, 0x87B1, 0xB219, 0xB4B1, 0xB21A, 0x87B2, 0xB21B, 0x87B3,
+ 0xB21C, 0x87B4, 0xB21D, 0x87B5, 0xB21E, 0x87B6, 0xB21F, 0x87B7, 0xB220, 0xB4B2, 0xB221, 0x87B8, 0xB222, 0x87B9, 0xB223, 0x87BA,
+ 0xB224, 0x87BB, 0xB225, 0x87BC, 0xB226, 0x87BD, 0xB227, 0x87BE, 0xB228, 0x87BF, 0xB229, 0x87C0, 0xB22A, 0x87C1, 0xB22B, 0x87C2,
+ 0xB22C, 0x87C3, 0xB22D, 0x87C4, 0xB22E, 0x87C5, 0xB22F, 0x87C6, 0xB230, 0x87C7, 0xB231, 0x87C8, 0xB232, 0x87C9, 0xB233, 0x87CA,
+ 0xB234, 0xB4B3, 0xB235, 0x87CB, 0xB236, 0x87CC, 0xB237, 0x87CD, 0xB238, 0x87CE, 0xB239, 0x87CF, 0xB23A, 0x87D0, 0xB23B, 0x87D1,
+ 0xB23C, 0xB4B4, 0xB23D, 0x87D2, 0xB23E, 0x87D3, 0xB23F, 0x87D4, 0xB240, 0x87D5, 0xB241, 0x87D6, 0xB242, 0x87D7, 0xB243, 0x87D8,
+ 0xB244, 0x87D9, 0xB245, 0x87DA, 0xB246, 0x87DB, 0xB247, 0x87DC, 0xB248, 0x87DD, 0xB249, 0x87DE, 0xB24A, 0x87DF, 0xB24B, 0x87E0,
+ 0xB24C, 0x87E1, 0xB24D, 0x87E2, 0xB24E, 0x87E3, 0xB24F, 0x87E4, 0xB250, 0x87E5, 0xB251, 0x87E6, 0xB252, 0x87E7, 0xB253, 0x87E8,
+ 0xB254, 0x87E9, 0xB255, 0x87EA, 0xB256, 0x87EB, 0xB257, 0x87EC, 0xB258, 0xB4B5, 0xB259, 0x87ED, 0xB25A, 0x87EE, 0xB25B, 0x87EF,
+ 0xB25C, 0xB4B6, 0xB25D, 0x87F0, 0xB25E, 0x87F1, 0xB25F, 0x87F2, 0xB260, 0xB4B7, 0xB261, 0x87F3, 0xB262, 0x87F4, 0xB263, 0x87F5,
+ 0xB264, 0x87F6, 0xB265, 0x87F7, 0xB266, 0x87F8, 0xB267, 0x87F9, 0xB268, 0xB4B8, 0xB269, 0xB4B9, 0xB26A, 0x87FA, 0xB26B, 0x87FB,
+ 0xB26C, 0x87FC, 0xB26D, 0x87FD, 0xB26E, 0x87FE, 0xB26F, 0x8841, 0xB270, 0x8842, 0xB271, 0x8843, 0xB272, 0x8844, 0xB273, 0x8845,
+ 0xB274, 0xB4BA, 0xB275, 0xB4BB, 0xB276, 0x8846, 0xB277, 0x8847, 0xB278, 0x8848, 0xB279, 0x8849, 0xB27A, 0x884A, 0xB27B, 0x884B,
+ 0xB27C, 0xB4BC, 0xB27D, 0x884C, 0xB27E, 0x884D, 0xB27F, 0x884E, 0xB280, 0x884F, 0xB281, 0x8850, 0xB282, 0x8851, 0xB283, 0x8852,
+ 0xB284, 0xB4BD, 0xB285, 0xB4BE, 0xB286, 0x8853, 0xB287, 0x8854, 0xB288, 0x8855, 0xB289, 0xB4BF, 0xB28A, 0x8856, 0xB28B, 0x8857,
+ 0xB28C, 0x8858, 0xB28D, 0x8859, 0xB28E, 0x885A, 0xB28F, 0x8861, 0xB290, 0xB4C0, 0xB291, 0xB4C1, 0xB292, 0x8862, 0xB293, 0x8863,
+ 0xB294, 0xB4C2, 0xB295, 0x8864, 0xB296, 0x8865, 0xB297, 0x8866, 0xB298, 0xB4C3, 0xB299, 0xB4C4, 0xB29A, 0xB4C5, 0xB29B, 0x8867,
+ 0xB29C, 0x8868, 0xB29D, 0x8869, 0xB29E, 0x886A, 0xB29F, 0x886B, 0xB2A0, 0xB4C6, 0xB2A1, 0xB4C7, 0xB2A2, 0x886C, 0xB2A3, 0xB4C8,
+ 0xB2A4, 0x886D, 0xB2A5, 0xB4C9, 0xB2A6, 0xB4CA, 0xB2A7, 0x886E, 0xB2A8, 0x886F, 0xB2A9, 0x8870, 0xB2AA, 0xB4CB, 0xB2AB, 0x8871,
+ 0xB2AC, 0xB4CC, 0xB2AD, 0x8872, 0xB2AE, 0x8873, 0xB2AF, 0x8874, 0xB2B0, 0xB4CD, 0xB2B1, 0x8875, 0xB2B2, 0x8876, 0xB2B3, 0x8877,
+ 0xB2B4, 0xB4CE, 0xB2B5, 0x8878, 0xB2B6, 0x8879, 0xB2B7, 0x887A, 0xB2B8, 0x8881, 0xB2B9, 0x8882, 0xB2BA, 0x8883, 0xB2BB, 0x8884,
+ 0xB2BC, 0x8885, 0xB2BD, 0x8886, 0xB2BE, 0x8887, 0xB2BF, 0x8888, 0xB2C0, 0x8889, 0xB2C1, 0x888A, 0xB2C2, 0x888B, 0xB2C3, 0x888C,
+ 0xB2C4, 0x888D, 0xB2C5, 0x888E, 0xB2C6, 0x888F, 0xB2C7, 0x8890, 0xB2C8, 0xB4CF, 0xB2C9, 0xB4D0, 0xB2CA, 0x8891, 0xB2CB, 0x8892,
+ 0xB2CC, 0xB4D1, 0xB2CD, 0x8893, 0xB2CE, 0x8894, 0xB2CF, 0x8895, 0xB2D0, 0xB4D2, 0xB2D1, 0x8896, 0xB2D2, 0xB4D3, 0xB2D3, 0x8897,
+ 0xB2D4, 0x8898, 0xB2D5, 0x8899, 0xB2D6, 0x889A, 0xB2D7, 0x889B, 0xB2D8, 0xB4D4, 0xB2D9, 0xB4D5, 0xB2DA, 0x889C, 0xB2DB, 0xB4D6,
+ 0xB2DC, 0x889D, 0xB2DD, 0xB4D7, 0xB2DE, 0x889E, 0xB2DF, 0x889F, 0xB2E0, 0x88A0, 0xB2E1, 0x88A1, 0xB2E2, 0xB4D8, 0xB2E3, 0x88A2,
+ 0xB2E4, 0xB4D9, 0xB2E5, 0xB4DA, 0xB2E6, 0xB4DB, 0xB2E7, 0x88A3, 0xB2E8, 0xB4DC, 0xB2E9, 0x88A4, 0xB2EA, 0x88A5, 0xB2EB, 0xB4DD,
+ 0xB2EC, 0xB4DE, 0xB2ED, 0xB4DF, 0xB2EE, 0xB4E0, 0xB2EF, 0xB4E1, 0xB2F0, 0x88A6, 0xB2F1, 0x88A7, 0xB2F2, 0x88A8, 0xB2F3, 0xB4E2,
+ 0xB2F4, 0xB4E3, 0xB2F5, 0xB4E4, 0xB2F6, 0x88A9, 0xB2F7, 0xB4E5, 0xB2F8, 0xB4E6, 0xB2F9, 0xB4E7, 0xB2FA, 0xB4E8, 0xB2FB, 0xB4E9,
+ 0xB2FC, 0x88AA, 0xB2FD, 0x88AB, 0xB2FE, 0x88AC, 0xB2FF, 0xB4EA, 0xB300, 0xB4EB, 0xB301, 0xB4EC, 0xB302, 0x88AD, 0xB303, 0x88AE,
+ 0xB304, 0xB4ED, 0xB305, 0x88AF, 0xB306, 0x88B0, 0xB307, 0x88B1, 0xB308, 0xB4EE, 0xB309, 0x88B2, 0xB30A, 0x88B3, 0xB30B, 0x88B4,
+ 0xB30C, 0x88B5, 0xB30D, 0x88B6, 0xB30E, 0x88B7, 0xB30F, 0x88B8, 0xB310, 0xB4EF, 0xB311, 0xB4F0, 0xB312, 0x88B9, 0xB313, 0xB4F1,
+ 0xB314, 0xB4F2, 0xB315, 0xB4F3, 0xB316, 0x88BA, 0xB317, 0x88BB, 0xB318, 0x88BC, 0xB319, 0x88BD, 0xB31A, 0x88BE, 0xB31B, 0x88BF,
+ 0xB31C, 0xB4F4, 0xB31D, 0x88C0, 0xB31E, 0x88C1, 0xB31F, 0x88C2, 0xB320, 0x88C3, 0xB321, 0x88C4, 0xB322, 0x88C5, 0xB323, 0x88C6,
+ 0xB324, 0x88C7, 0xB325, 0x88C8, 0xB326, 0x88C9, 0xB327, 0x88CA, 0xB328, 0x88CB, 0xB329, 0x88CC, 0xB32A, 0x88CD, 0xB32B, 0x88CE,
+ 0xB32C, 0x88CF, 0xB32D, 0x88D0, 0xB32E, 0x88D1, 0xB32F, 0x88D2, 0xB330, 0x88D3, 0xB331, 0x88D4, 0xB332, 0x88D5, 0xB333, 0x88D6,
+ 0xB334, 0x88D7, 0xB335, 0x88D8, 0xB336, 0x88D9, 0xB337, 0x88DA, 0xB338, 0x88DB, 0xB339, 0x88DC, 0xB33A, 0x88DD, 0xB33B, 0x88DE,
+ 0xB33C, 0x88DF, 0xB33D, 0x88E0, 0xB33E, 0x88E1, 0xB33F, 0x88E2, 0xB340, 0x88E3, 0xB341, 0x88E4, 0xB342, 0x88E5, 0xB343, 0x88E6,
+ 0xB344, 0x88E7, 0xB345, 0x88E8, 0xB346, 0x88E9, 0xB347, 0x88EA, 0xB348, 0x88EB, 0xB349, 0x88EC, 0xB34A, 0x88ED, 0xB34B, 0x88EE,
+ 0xB34C, 0x88EF, 0xB34D, 0x88F0, 0xB34E, 0x88F1, 0xB34F, 0x88F2, 0xB350, 0x88F3, 0xB351, 0x88F4, 0xB352, 0x88F5, 0xB353, 0x88F6,
+ 0xB354, 0xB4F5, 0xB355, 0xB4F6, 0xB356, 0xB4F7, 0xB357, 0x88F7, 0xB358, 0xB4F8, 0xB359, 0x88F8, 0xB35A, 0x88F9, 0xB35B, 0xB4F9,
+ 0xB35C, 0xB4FA, 0xB35D, 0x88FA, 0xB35E, 0xB4FB, 0xB35F, 0xB4FC, 0xB360, 0x88FB, 0xB361, 0x88FC, 0xB362, 0x88FD, 0xB363, 0x88FE,
+ 0xB364, 0xB4FD, 0xB365, 0xB4FE, 0xB366, 0x8941, 0xB367, 0xB5A1, 0xB368, 0x8942, 0xB369, 0xB5A2, 0xB36A, 0x8943, 0xB36B, 0xB5A3,
+ 0xB36C, 0x8944, 0xB36D, 0x8945, 0xB36E, 0xB5A4, 0xB36F, 0x8946, 0xB370, 0xB5A5, 0xB371, 0xB5A6, 0xB372, 0x8947, 0xB373, 0x8948,
+ 0xB374, 0xB5A7, 0xB375, 0x8949, 0xB376, 0x894A, 0xB377, 0x894B, 0xB378, 0xB5A8, 0xB379, 0x894C, 0xB37A, 0x894D, 0xB37B, 0x894E,
+ 0xB37C, 0x894F, 0xB37D, 0x8950, 0xB37E, 0x8951, 0xB37F, 0x8952, 0xB380, 0xB5A9, 0xB381, 0xB5AA, 0xB382, 0x8953, 0xB383, 0xB5AB,
+ 0xB384, 0xB5AC, 0xB385, 0xB5AD, 0xB386, 0x8954, 0xB387, 0x8955, 0xB388, 0x8956, 0xB389, 0x8957, 0xB38A, 0x8958, 0xB38B, 0x8959,
+ 0xB38C, 0xB5AE, 0xB38D, 0x895A, 0xB38E, 0x8961, 0xB38F, 0x8962, 0xB390, 0xB5AF, 0xB391, 0x8963, 0xB392, 0x8964, 0xB393, 0x8965,
+ 0xB394, 0xB5B0, 0xB395, 0x8966, 0xB396, 0x8967, 0xB397, 0x8968, 0xB398, 0x8969, 0xB399, 0x896A, 0xB39A, 0x896B, 0xB39B, 0x896C,
+ 0xB39C, 0x896D, 0xB39D, 0x896E, 0xB39E, 0x896F, 0xB39F, 0x8970, 0xB3A0, 0xB5B1, 0xB3A1, 0xB5B2, 0xB3A2, 0x8971, 0xB3A3, 0x8972,
+ 0xB3A4, 0x8973, 0xB3A5, 0x8974, 0xB3A6, 0x8975, 0xB3A7, 0x8976, 0xB3A8, 0xB5B3, 0xB3A9, 0x8977, 0xB3AA, 0x8978, 0xB3AB, 0x8979,
+ 0xB3AC, 0xB5B4, 0xB3AD, 0x897A, 0xB3AE, 0x8981, 0xB3AF, 0x8982, 0xB3B0, 0x8983, 0xB3B1, 0x8984, 0xB3B2, 0x8985, 0xB3B3, 0x8986,
+ 0xB3B4, 0x8987, 0xB3B5, 0x8988, 0xB3B6, 0x8989, 0xB3B7, 0x898A, 0xB3B8, 0x898B, 0xB3B9, 0x898C, 0xB3BA, 0x898D, 0xB3BB, 0x898E,
+ 0xB3BC, 0x898F, 0xB3BD, 0x8990, 0xB3BE, 0x8991, 0xB3BF, 0x8992, 0xB3C0, 0x8993, 0xB3C1, 0x8994, 0xB3C2, 0x8995, 0xB3C3, 0x8996,
+ 0xB3C4, 0xB5B5, 0xB3C5, 0xB5B6, 0xB3C6, 0x8997, 0xB3C7, 0x8998, 0xB3C8, 0xB5B7, 0xB3C9, 0x8999, 0xB3CA, 0x899A, 0xB3CB, 0xB5B8,
+ 0xB3CC, 0xB5B9, 0xB3CD, 0x899B, 0xB3CE, 0xB5BA, 0xB3CF, 0x899C, 0xB3D0, 0xB5BB, 0xB3D1, 0x899D, 0xB3D2, 0x899E, 0xB3D3, 0x899F,
+ 0xB3D4, 0xB5BC, 0xB3D5, 0xB5BD, 0xB3D6, 0x89A0, 0xB3D7, 0xB5BE, 0xB3D8, 0x89A1, 0xB3D9, 0xB5BF, 0xB3DA, 0x89A2, 0xB3DB, 0xB5C0,
+ 0xB3DC, 0x89A3, 0xB3DD, 0xB5C1, 0xB3DE, 0x89A4, 0xB3DF, 0x89A5, 0xB3E0, 0xB5C2, 0xB3E1, 0x89A6, 0xB3E2, 0x89A7, 0xB3E3, 0x89A8,
+ 0xB3E4, 0xB5C3, 0xB3E5, 0x89A9, 0xB3E6, 0x89AA, 0xB3E7, 0x89AB, 0xB3E8, 0xB5C4, 0xB3E9, 0x89AC, 0xB3EA, 0x89AD, 0xB3EB, 0x89AE,
+ 0xB3EC, 0x89AF, 0xB3ED, 0x89B0, 0xB3EE, 0x89B1, 0xB3EF, 0x89B2, 0xB3F0, 0x89B3, 0xB3F1, 0x89B4, 0xB3F2, 0x89B5, 0xB3F3, 0x89B6,
+ 0xB3F4, 0x89B7, 0xB3F5, 0x89B8, 0xB3F6, 0x89B9, 0xB3F7, 0x89BA, 0xB3F8, 0x89BB, 0xB3F9, 0x89BC, 0xB3FA, 0x89BD, 0xB3FB, 0x89BE,
+ 0xB3FC, 0xB5C5, 0xB3FD, 0x89BF, 0xB3FE, 0x89C0, 0xB3FF, 0x89C1, 0xB400, 0x89C2, 0xB401, 0x89C3, 0xB402, 0x89C4, 0xB403, 0x89C5,
+ 0xB404, 0x89C6, 0xB405, 0x89C7, 0xB406, 0x89C8, 0xB407, 0x89C9, 0xB408, 0x89CA, 0xB409, 0x89CB, 0xB40A, 0x89CC, 0xB40B, 0x89CD,
+ 0xB40C, 0x89CE, 0xB40D, 0x89CF, 0xB40E, 0x89D0, 0xB40F, 0x89D1, 0xB410, 0xB5C6, 0xB411, 0x89D2, 0xB412, 0x89D3, 0xB413, 0x89D4,
+ 0xB414, 0x89D5, 0xB415, 0x89D6, 0xB416, 0x89D7, 0xB417, 0x89D8, 0xB418, 0xB5C7, 0xB419, 0x89D9, 0xB41A, 0x89DA, 0xB41B, 0x89DB,
+ 0xB41C, 0xB5C8, 0xB41D, 0x89DC, 0xB41E, 0x89DD, 0xB41F, 0x89DE, 0xB420, 0xB5C9, 0xB421, 0x89DF, 0xB422, 0x89E0, 0xB423, 0x89E1,
+ 0xB424, 0x89E2, 0xB425, 0x89E3, 0xB426, 0x89E4, 0xB427, 0x89E5, 0xB428, 0xB5CA, 0xB429, 0xB5CB, 0xB42A, 0x89E6, 0xB42B, 0xB5CC,
+ 0xB42C, 0x89E7, 0xB42D, 0x89E8, 0xB42E, 0x89E9, 0xB42F, 0x89EA, 0xB430, 0x89EB, 0xB431, 0x89EC, 0xB432, 0x89ED, 0xB433, 0x89EE,
+ 0xB434, 0xB5CD, 0xB435, 0x89EF, 0xB436, 0x89F0, 0xB437, 0x89F1, 0xB438, 0x89F2, 0xB439, 0x89F3, 0xB43A, 0x89F4, 0xB43B, 0x89F5,
+ 0xB43C, 0x89F6, 0xB43D, 0x89F7, 0xB43E, 0x89F8, 0xB43F, 0x89F9, 0xB440, 0x89FA, 0xB441, 0x89FB, 0xB442, 0x89FC, 0xB443, 0x89FD,
+ 0xB444, 0x89FE, 0xB445, 0x8A41, 0xB446, 0x8A42, 0xB447, 0x8A43, 0xB448, 0x8A44, 0xB449, 0x8A45, 0xB44A, 0x8A46, 0xB44B, 0x8A47,
+ 0xB44C, 0x8A48, 0xB44D, 0x8A49, 0xB44E, 0x8A4A, 0xB44F, 0x8A4B, 0xB450, 0xB5CE, 0xB451, 0xB5CF, 0xB452, 0x8A4C, 0xB453, 0x8A4D,
+ 0xB454, 0xB5D0, 0xB455, 0x8A4E, 0xB456, 0x8A4F, 0xB457, 0x8A50, 0xB458, 0xB5D1, 0xB459, 0x8A51, 0xB45A, 0x8A52, 0xB45B, 0x8A53,
+ 0xB45C, 0x8A54, 0xB45D, 0x8A55, 0xB45E, 0x8A56, 0xB45F, 0x8A57, 0xB460, 0xB5D2, 0xB461, 0xB5D3, 0xB462, 0x8A58, 0xB463, 0xB5D4,
+ 0xB464, 0x8A59, 0xB465, 0xB5D5, 0xB466, 0x8A5A, 0xB467, 0x8A61, 0xB468, 0x8A62, 0xB469, 0x8A63, 0xB46A, 0x8A64, 0xB46B, 0x8A65,
+ 0xB46C, 0xB5D6, 0xB46D, 0x8A66, 0xB46E, 0x8A67, 0xB46F, 0x8A68, 0xB470, 0x8A69, 0xB471, 0x8A6A, 0xB472, 0x8A6B, 0xB473, 0x8A6C,
+ 0xB474, 0x8A6D, 0xB475, 0x8A6E, 0xB476, 0x8A6F, 0xB477, 0x8A70, 0xB478, 0x8A71, 0xB479, 0x8A72, 0xB47A, 0x8A73, 0xB47B, 0x8A74,
+ 0xB47C, 0x8A75, 0xB47D, 0x8A76, 0xB47E, 0x8A77, 0xB47F, 0x8A78, 0xB480, 0xB5D7, 0xB481, 0x8A79, 0xB482, 0x8A7A, 0xB483, 0x8A81,
+ 0xB484, 0x8A82, 0xB485, 0x8A83, 0xB486, 0x8A84, 0xB487, 0x8A85, 0xB488, 0xB5D8, 0xB489, 0x8A86, 0xB48A, 0x8A87, 0xB48B, 0x8A88,
+ 0xB48C, 0x8A89, 0xB48D, 0x8A8A, 0xB48E, 0x8A8B, 0xB48F, 0x8A8C, 0xB490, 0x8A8D, 0xB491, 0x8A8E, 0xB492, 0x8A8F, 0xB493, 0x8A90,
+ 0xB494, 0x8A91, 0xB495, 0x8A92, 0xB496, 0x8A93, 0xB497, 0x8A94, 0xB498, 0x8A95, 0xB499, 0x8A96, 0xB49A, 0x8A97, 0xB49B, 0x8A98,
+ 0xB49C, 0x8A99, 0xB49D, 0xB5D9, 0xB49E, 0x8A9A, 0xB49F, 0x8A9B, 0xB4A0, 0x8A9C, 0xB4A1, 0x8A9D, 0xB4A2, 0x8A9E, 0xB4A3, 0x8A9F,
+ 0xB4A4, 0xB5DA, 0xB4A5, 0x8AA0, 0xB4A6, 0x8AA1, 0xB4A7, 0x8AA2, 0xB4A8, 0xB5DB, 0xB4A9, 0x8AA3, 0xB4AA, 0x8AA4, 0xB4AB, 0x8AA5,
+ 0xB4AC, 0xB5DC, 0xB4AD, 0x8AA6, 0xB4AE, 0x8AA7, 0xB4AF, 0x8AA8, 0xB4B0, 0x8AA9, 0xB4B1, 0x8AAA, 0xB4B2, 0x8AAB, 0xB4B3, 0x8AAC,
+ 0xB4B4, 0x8AAD, 0xB4B5, 0xB5DD, 0xB4B6, 0x8AAE, 0xB4B7, 0xB5DE, 0xB4B8, 0x8AAF, 0xB4B9, 0xB5DF, 0xB4BA, 0x8AB0, 0xB4BB, 0x8AB1,
+ 0xB4BC, 0x8AB2, 0xB4BD, 0x8AB3, 0xB4BE, 0x8AB4, 0xB4BF, 0x8AB5, 0xB4C0, 0xB5E0, 0xB4C1, 0x8AB6, 0xB4C2, 0x8AB7, 0xB4C3, 0x8AB8,
+ 0xB4C4, 0xB5E1, 0xB4C5, 0x8AB9, 0xB4C6, 0x8ABA, 0xB4C7, 0x8ABB, 0xB4C8, 0xB5E2, 0xB4C9, 0x8ABC, 0xB4CA, 0x8ABD, 0xB4CB, 0x8ABE,
+ 0xB4CC, 0x8ABF, 0xB4CD, 0x8AC0, 0xB4CE, 0x8AC1, 0xB4CF, 0x8AC2, 0xB4D0, 0xB5E3, 0xB4D1, 0x8AC3, 0xB4D2, 0x8AC4, 0xB4D3, 0x8AC5,
+ 0xB4D4, 0x8AC6, 0xB4D5, 0xB5E4, 0xB4D6, 0x8AC7, 0xB4D7, 0x8AC8, 0xB4D8, 0x8AC9, 0xB4D9, 0x8ACA, 0xB4DA, 0x8ACB, 0xB4DB, 0x8ACC,
+ 0xB4DC, 0xB5E5, 0xB4DD, 0xB5E6, 0xB4DE, 0x8ACD, 0xB4DF, 0x8ACE, 0xB4E0, 0xB5E7, 0xB4E1, 0x8ACF, 0xB4E2, 0x8AD0, 0xB4E3, 0xB5E8,
+ 0xB4E4, 0xB5E9, 0xB4E5, 0x8AD1, 0xB4E6, 0xB5EA, 0xB4E7, 0x8AD2, 0xB4E8, 0x8AD3, 0xB4E9, 0x8AD4, 0xB4EA, 0x8AD5, 0xB4EB, 0x8AD6,
+ 0xB4EC, 0xB5EB, 0xB4ED, 0xB5EC, 0xB4EE, 0x8AD7, 0xB4EF, 0xB5ED, 0xB4F0, 0x8AD8, 0xB4F1, 0xB5EE, 0xB4F2, 0x8AD9, 0xB4F3, 0x8ADA,
+ 0xB4F4, 0x8ADB, 0xB4F5, 0x8ADC, 0xB4F6, 0x8ADD, 0xB4F7, 0x8ADE, 0xB4F8, 0xB5EF, 0xB4F9, 0x8ADF, 0xB4FA, 0x8AE0, 0xB4FB, 0x8AE1,
+ 0xB4FC, 0x8AE2, 0xB4FD, 0x8AE3, 0xB4FE, 0x8AE4, 0xB4FF, 0x8AE5, 0xB500, 0x8AE6, 0xB501, 0x8AE7, 0xB502, 0x8AE8, 0xB503, 0x8AE9,
+ 0xB504, 0x8AEA, 0xB505, 0x8AEB, 0xB506, 0x8AEC, 0xB507, 0x8AED, 0xB508, 0x8AEE, 0xB509, 0x8AEF, 0xB50A, 0x8AF0, 0xB50B, 0x8AF1,
+ 0xB50C, 0x8AF2, 0xB50D, 0x8AF3, 0xB50E, 0x8AF4, 0xB50F, 0x8AF5, 0xB510, 0x8AF6, 0xB511, 0x8AF7, 0xB512, 0x8AF8, 0xB513, 0x8AF9,
+ 0xB514, 0xB5F0, 0xB515, 0xB5F1, 0xB516, 0x8AFA, 0xB517, 0x8AFB, 0xB518, 0xB5F2, 0xB519, 0x8AFC, 0xB51A, 0x8AFD, 0xB51B, 0xB5F3,
+ 0xB51C, 0xB5F4, 0xB51D, 0x8AFE, 0xB51E, 0x8B41, 0xB51F, 0x8B42, 0xB520, 0x8B43, 0xB521, 0x8B44, 0xB522, 0x8B45, 0xB523, 0x8B46,
+ 0xB524, 0xB5F5, 0xB525, 0xB5F6, 0xB526, 0x8B47, 0xB527, 0xB5F7, 0xB528, 0xB5F8, 0xB529, 0xB5F9, 0xB52A, 0xB5FA, 0xB52B, 0x8B48,
+ 0xB52C, 0x8B49, 0xB52D, 0x8B4A, 0xB52E, 0x8B4B, 0xB52F, 0x8B4C, 0xB530, 0xB5FB, 0xB531, 0xB5FC, 0xB532, 0x8B4D, 0xB533, 0x8B4E,
+ 0xB534, 0xB5FD, 0xB535, 0x8B4F, 0xB536, 0x8B50, 0xB537, 0x8B51, 0xB538, 0xB5FE, 0xB539, 0x8B52, 0xB53A, 0x8B53, 0xB53B, 0x8B54,
+ 0xB53C, 0x8B55, 0xB53D, 0x8B56, 0xB53E, 0x8B57, 0xB53F, 0x8B58, 0xB540, 0xB6A1, 0xB541, 0xB6A2, 0xB542, 0x8B59, 0xB543, 0xB6A3,
+ 0xB544, 0xB6A4, 0xB545, 0xB6A5, 0xB546, 0x8B5A, 0xB547, 0x8B61, 0xB548, 0x8B62, 0xB549, 0x8B63, 0xB54A, 0x8B64, 0xB54B, 0xB6A6,
+ 0xB54C, 0xB6A7, 0xB54D, 0xB6A8, 0xB54E, 0x8B65, 0xB54F, 0x8B66, 0xB550, 0xB6A9, 0xB551, 0x8B67, 0xB552, 0x8B68, 0xB553, 0x8B69,
+ 0xB554, 0xB6AA, 0xB555, 0x8B6A, 0xB556, 0x8B6B, 0xB557, 0x8B6C, 0xB558, 0x8B6D, 0xB559, 0x8B6E, 0xB55A, 0x8B6F, 0xB55B, 0x8B70,
+ 0xB55C, 0xB6AB, 0xB55D, 0xB6AC, 0xB55E, 0x8B71, 0xB55F, 0xB6AD, 0xB560, 0xB6AE, 0xB561, 0xB6AF, 0xB562, 0x8B72, 0xB563, 0x8B73,
+ 0xB564, 0x8B74, 0xB565, 0x8B75, 0xB566, 0x8B76, 0xB567, 0x8B77, 0xB568, 0x8B78, 0xB569, 0x8B79, 0xB56A, 0x8B7A, 0xB56B, 0x8B81,
+ 0xB56C, 0x8B82, 0xB56D, 0x8B83, 0xB56E, 0x8B84, 0xB56F, 0x8B85, 0xB570, 0x8B86, 0xB571, 0x8B87, 0xB572, 0x8B88, 0xB573, 0x8B89,
+ 0xB574, 0x8B8A, 0xB575, 0x8B8B, 0xB576, 0x8B8C, 0xB577, 0x8B8D, 0xB578, 0x8B8E, 0xB579, 0x8B8F, 0xB57A, 0x8B90, 0xB57B, 0x8B91,
+ 0xB57C, 0x8B92, 0xB57D, 0x8B93, 0xB57E, 0x8B94, 0xB57F, 0x8B95, 0xB580, 0x8B96, 0xB581, 0x8B97, 0xB582, 0x8B98, 0xB583, 0x8B99,
+ 0xB584, 0x8B9A, 0xB585, 0x8B9B, 0xB586, 0x8B9C, 0xB587, 0x8B9D, 0xB588, 0x8B9E, 0xB589, 0x8B9F, 0xB58A, 0x8BA0, 0xB58B, 0x8BA1,
+ 0xB58C, 0x8BA2, 0xB58D, 0x8BA3, 0xB58E, 0x8BA4, 0xB58F, 0x8BA5, 0xB590, 0x8BA6, 0xB591, 0x8BA7, 0xB592, 0x8BA8, 0xB593, 0x8BA9,
+ 0xB594, 0x8BAA, 0xB595, 0x8BAB, 0xB596, 0x8BAC, 0xB597, 0x8BAD, 0xB598, 0x8BAE, 0xB599, 0x8BAF, 0xB59A, 0x8BB0, 0xB59B, 0x8BB1,
+ 0xB59C, 0x8BB2, 0xB59D, 0x8BB3, 0xB59E, 0x8BB4, 0xB59F, 0x8BB5, 0xB5A0, 0xB6B0, 0xB5A1, 0xB6B1, 0xB5A2, 0x8BB6, 0xB5A3, 0x8BB7,
+ 0xB5A4, 0xB6B2, 0xB5A5, 0x8BB8, 0xB5A6, 0x8BB9, 0xB5A7, 0x8BBA, 0xB5A8, 0xB6B3, 0xB5A9, 0x8BBB, 0xB5AA, 0xB6B4, 0xB5AB, 0xB6B5,
+ 0xB5AC, 0x8BBC, 0xB5AD, 0x8BBD, 0xB5AE, 0x8BBE, 0xB5AF, 0x8BBF, 0xB5B0, 0xB6B6, 0xB5B1, 0xB6B7, 0xB5B2, 0x8BC0, 0xB5B3, 0xB6B8,
+ 0xB5B4, 0xB6B9, 0xB5B5, 0xB6BA, 0xB5B6, 0x8BC1, 0xB5B7, 0x8BC2, 0xB5B8, 0x8BC3, 0xB5B9, 0x8BC4, 0xB5BA, 0x8BC5, 0xB5BB, 0xB6BB,
+ 0xB5BC, 0xB6BC, 0xB5BD, 0xB6BD, 0xB5BE, 0x8BC6, 0xB5BF, 0x8BC7, 0xB5C0, 0xB6BE, 0xB5C1, 0x8BC8, 0xB5C2, 0x8BC9, 0xB5C3, 0x8BCA,
+ 0xB5C4, 0xB6BF, 0xB5C5, 0x8BCB, 0xB5C6, 0x8BCC, 0xB5C7, 0x8BCD, 0xB5C8, 0x8BCE, 0xB5C9, 0x8BCF, 0xB5CA, 0x8BD0, 0xB5CB, 0x8BD1,
+ 0xB5CC, 0xB6C0, 0xB5CD, 0xB6C1, 0xB5CE, 0x8BD2, 0xB5CF, 0xB6C2, 0xB5D0, 0xB6C3, 0xB5D1, 0xB6C4, 0xB5D2, 0x8BD3, 0xB5D3, 0x8BD4,
+ 0xB5D4, 0x8BD5, 0xB5D5, 0x8BD6, 0xB5D6, 0x8BD7, 0xB5D7, 0x8BD8, 0xB5D8, 0xB6C5, 0xB5D9, 0x8BD9, 0xB5DA, 0x8BDA, 0xB5DB, 0x8BDB,
+ 0xB5DC, 0x8BDC, 0xB5DD, 0x8BDD, 0xB5DE, 0x8BDE, 0xB5DF, 0x8BDF, 0xB5E0, 0x8BE0, 0xB5E1, 0x8BE1, 0xB5E2, 0x8BE2, 0xB5E3, 0x8BE3,
+ 0xB5E4, 0x8BE4, 0xB5E5, 0x8BE5, 0xB5E6, 0x8BE6, 0xB5E7, 0x8BE7, 0xB5E8, 0x8BE8, 0xB5E9, 0x8BE9, 0xB5EA, 0x8BEA, 0xB5EB, 0x8BEB,
+ 0xB5EC, 0xB6C6, 0xB5ED, 0x8BEC, 0xB5EE, 0x8BED, 0xB5EF, 0x8BEE, 0xB5F0, 0x8BEF, 0xB5F1, 0x8BF0, 0xB5F2, 0x8BF1, 0xB5F3, 0x8BF2,
+ 0xB5F4, 0x8BF3, 0xB5F5, 0x8BF4, 0xB5F6, 0x8BF5, 0xB5F7, 0x8BF6, 0xB5F8, 0x8BF7, 0xB5F9, 0x8BF8, 0xB5FA, 0x8BF9, 0xB5FB, 0x8BFA,
+ 0xB5FC, 0x8BFB, 0xB5FD, 0x8BFC, 0xB5FE, 0x8BFD, 0xB5FF, 0x8BFE, 0xB600, 0x8C41, 0xB601, 0x8C42, 0xB602, 0x8C43, 0xB603, 0x8C44,
+ 0xB604, 0x8C45, 0xB605, 0x8C46, 0xB606, 0x8C47, 0xB607, 0x8C48, 0xB608, 0x8C49, 0xB609, 0x8C4A, 0xB60A, 0x8C4B, 0xB60B, 0x8C4C,
+ 0xB60C, 0x8C4D, 0xB60D, 0x8C4E, 0xB60E, 0x8C4F, 0xB60F, 0x8C50, 0xB610, 0xB6C7, 0xB611, 0xB6C8, 0xB612, 0x8C51, 0xB613, 0x8C52,
+ 0xB614, 0xB6C9, 0xB615, 0x8C53, 0xB616, 0x8C54, 0xB617, 0x8C55, 0xB618, 0xB6CA, 0xB619, 0x8C56, 0xB61A, 0x8C57, 0xB61B, 0x8C58,
+ 0xB61C, 0x8C59, 0xB61D, 0x8C5A, 0xB61E, 0x8C61, 0xB61F, 0x8C62, 0xB620, 0x8C63, 0xB621, 0x8C64, 0xB622, 0x8C65, 0xB623, 0x8C66,
+ 0xB624, 0x8C67, 0xB625, 0xB6CB, 0xB626, 0x8C68, 0xB627, 0x8C69, 0xB628, 0x8C6A, 0xB629, 0x8C6B, 0xB62A, 0x8C6C, 0xB62B, 0x8C6D,
+ 0xB62C, 0xB6CC, 0xB62D, 0x8C6E, 0xB62E, 0x8C6F, 0xB62F, 0x8C70, 0xB630, 0x8C71, 0xB631, 0x8C72, 0xB632, 0x8C73, 0xB633, 0x8C74,
+ 0xB634, 0xB6CD, 0xB635, 0x8C75, 0xB636, 0x8C76, 0xB637, 0x8C77, 0xB638, 0x8C78, 0xB639, 0x8C79, 0xB63A, 0x8C7A, 0xB63B, 0x8C81,
+ 0xB63C, 0x8C82, 0xB63D, 0x8C83, 0xB63E, 0x8C84, 0xB63F, 0x8C85, 0xB640, 0x8C86, 0xB641, 0x8C87, 0xB642, 0x8C88, 0xB643, 0x8C89,
+ 0xB644, 0x8C8A, 0xB645, 0x8C8B, 0xB646, 0x8C8C, 0xB647, 0x8C8D, 0xB648, 0xB6CE, 0xB649, 0x8C8E, 0xB64A, 0x8C8F, 0xB64B, 0x8C90,
+ 0xB64C, 0x8C91, 0xB64D, 0x8C92, 0xB64E, 0x8C93, 0xB64F, 0x8C94, 0xB650, 0x8C95, 0xB651, 0x8C96, 0xB652, 0x8C97, 0xB653, 0x8C98,
+ 0xB654, 0x8C99, 0xB655, 0x8C9A, 0xB656, 0x8C9B, 0xB657, 0x8C9C, 0xB658, 0x8C9D, 0xB659, 0x8C9E, 0xB65A, 0x8C9F, 0xB65B, 0x8CA0,
+ 0xB65C, 0x8CA1, 0xB65D, 0x8CA2, 0xB65E, 0x8CA3, 0xB65F, 0x8CA4, 0xB660, 0x8CA5, 0xB661, 0x8CA6, 0xB662, 0x8CA7, 0xB663, 0x8CA8,
+ 0xB664, 0xB6CF, 0xB665, 0x8CA9, 0xB666, 0x8CAA, 0xB667, 0x8CAB, 0xB668, 0xB6D0, 0xB669, 0x8CAC, 0xB66A, 0x8CAD, 0xB66B, 0x8CAE,
+ 0xB66C, 0x8CAF, 0xB66D, 0x8CB0, 0xB66E, 0x8CB1, 0xB66F, 0x8CB2, 0xB670, 0x8CB3, 0xB671, 0x8CB4, 0xB672, 0x8CB5, 0xB673, 0x8CB6,
+ 0xB674, 0x8CB7, 0xB675, 0x8CB8, 0xB676, 0x8CB9, 0xB677, 0x8CBA, 0xB678, 0x8CBB, 0xB679, 0x8CBC, 0xB67A, 0x8CBD, 0xB67B, 0x8CBE,
+ 0xB67C, 0x8CBF, 0xB67D, 0x8CC0, 0xB67E, 0x8CC1, 0xB67F, 0x8CC2, 0xB680, 0x8CC3, 0xB681, 0x8CC4, 0xB682, 0x8CC5, 0xB683, 0x8CC6,
+ 0xB684, 0x8CC7, 0xB685, 0x8CC8, 0xB686, 0x8CC9, 0xB687, 0x8CCA, 0xB688, 0x8CCB, 0xB689, 0x8CCC, 0xB68A, 0x8CCD, 0xB68B, 0x8CCE,
+ 0xB68C, 0x8CCF, 0xB68D, 0x8CD0, 0xB68E, 0x8CD1, 0xB68F, 0x8CD2, 0xB690, 0x8CD3, 0xB691, 0x8CD4, 0xB692, 0x8CD5, 0xB693, 0x8CD6,
+ 0xB694, 0x8CD7, 0xB695, 0x8CD8, 0xB696, 0x8CD9, 0xB697, 0x8CDA, 0xB698, 0x8CDB, 0xB699, 0x8CDC, 0xB69A, 0x8CDD, 0xB69B, 0x8CDE,
+ 0xB69C, 0xB6D1, 0xB69D, 0xB6D2, 0xB69E, 0x8CDF, 0xB69F, 0x8CE0, 0xB6A0, 0xB6D3, 0xB6A1, 0x8CE1, 0xB6A2, 0x8CE2, 0xB6A3, 0x8CE3,
+ 0xB6A4, 0xB6D4, 0xB6A5, 0x8CE4, 0xB6A6, 0x8CE5, 0xB6A7, 0x8CE6, 0xB6A8, 0x8CE7, 0xB6A9, 0x8CE8, 0xB6AA, 0x8CE9, 0xB6AB, 0xB6D5,
+ 0xB6AC, 0xB6D6, 0xB6AD, 0x8CEA, 0xB6AE, 0x8CEB, 0xB6AF, 0x8CEC, 0xB6B0, 0x8CED, 0xB6B1, 0xB6D7, 0xB6B2, 0x8CEE, 0xB6B3, 0x8CEF,
+ 0xB6B4, 0x8CF0, 0xB6B5, 0x8CF1, 0xB6B6, 0x8CF2, 0xB6B7, 0x8CF3, 0xB6B8, 0x8CF4, 0xB6B9, 0x8CF5, 0xB6BA, 0x8CF6, 0xB6BB, 0x8CF7,
+ 0xB6BC, 0x8CF8, 0xB6BD, 0x8CF9, 0xB6BE, 0x8CFA, 0xB6BF, 0x8CFB, 0xB6C0, 0x8CFC, 0xB6C1, 0x8CFD, 0xB6C2, 0x8CFE, 0xB6C3, 0x8D41,
+ 0xB6C4, 0x8D42, 0xB6C5, 0x8D43, 0xB6C6, 0x8D44, 0xB6C7, 0x8D45, 0xB6C8, 0x8D46, 0xB6C9, 0x8D47, 0xB6CA, 0x8D48, 0xB6CB, 0x8D49,
+ 0xB6CC, 0x8D4A, 0xB6CD, 0x8D4B, 0xB6CE, 0x8D4C, 0xB6CF, 0x8D4D, 0xB6D0, 0x8D4E, 0xB6D1, 0x8D4F, 0xB6D2, 0x8D50, 0xB6D3, 0x8D51,
+ 0xB6D4, 0xB6D8, 0xB6D5, 0x8D52, 0xB6D6, 0x8D53, 0xB6D7, 0x8D54, 0xB6D8, 0x8D55, 0xB6D9, 0x8D56, 0xB6DA, 0x8D57, 0xB6DB, 0x8D58,
+ 0xB6DC, 0x8D59, 0xB6DD, 0x8D5A, 0xB6DE, 0x8D61, 0xB6DF, 0x8D62, 0xB6E0, 0x8D63, 0xB6E1, 0x8D64, 0xB6E2, 0x8D65, 0xB6E3, 0x8D66,
+ 0xB6E4, 0x8D67, 0xB6E5, 0x8D68, 0xB6E6, 0x8D69, 0xB6E7, 0x8D6A, 0xB6E8, 0x8D6B, 0xB6E9, 0x8D6C, 0xB6EA, 0x8D6D, 0xB6EB, 0x8D6E,
+ 0xB6EC, 0x8D6F, 0xB6ED, 0x8D70, 0xB6EE, 0x8D71, 0xB6EF, 0x8D72, 0xB6F0, 0xB6D9, 0xB6F1, 0x8D73, 0xB6F2, 0x8D74, 0xB6F3, 0x8D75,
+ 0xB6F4, 0xB6DA, 0xB6F5, 0x8D76, 0xB6F6, 0x8D77, 0xB6F7, 0x8D78, 0xB6F8, 0xB6DB, 0xB6F9, 0x8D79, 0xB6FA, 0x8D7A, 0xB6FB, 0x8D81,
+ 0xB6FC, 0x8D82, 0xB6FD, 0x8D83, 0xB6FE, 0x8D84, 0xB6FF, 0x8D85, 0xB700, 0xB6DC, 0xB701, 0xB6DD, 0xB702, 0x8D86, 0xB703, 0x8D87,
+ 0xB704, 0x8D88, 0xB705, 0xB6DE, 0xB706, 0x8D89, 0xB707, 0x8D8A, 0xB708, 0x8D8B, 0xB709, 0x8D8C, 0xB70A, 0x8D8D, 0xB70B, 0x8D8E,
+ 0xB70C, 0x8D8F, 0xB70D, 0x8D90, 0xB70E, 0x8D91, 0xB70F, 0x8D92, 0xB710, 0x8D93, 0xB711, 0x8D94, 0xB712, 0x8D95, 0xB713, 0x8D96,
+ 0xB714, 0x8D97, 0xB715, 0x8D98, 0xB716, 0x8D99, 0xB717, 0x8D9A, 0xB718, 0x8D9B, 0xB719, 0x8D9C, 0xB71A, 0x8D9D, 0xB71B, 0x8D9E,
+ 0xB71C, 0x8D9F, 0xB71D, 0x8DA0, 0xB71E, 0x8DA1, 0xB71F, 0x8DA2, 0xB720, 0x8DA3, 0xB721, 0x8DA4, 0xB722, 0x8DA5, 0xB723, 0x8DA6,
+ 0xB724, 0x8DA7, 0xB725, 0x8DA8, 0xB726, 0x8DA9, 0xB727, 0x8DAA, 0xB728, 0xB6DF, 0xB729, 0xB6E0, 0xB72A, 0x8DAB, 0xB72B, 0x8DAC,
+ 0xB72C, 0xB6E1, 0xB72D, 0x8DAD, 0xB72E, 0x8DAE, 0xB72F, 0xB6E2, 0xB730, 0xB6E3, 0xB731, 0x8DAF, 0xB732, 0x8DB0, 0xB733, 0x8DB1,
+ 0xB734, 0x8DB2, 0xB735, 0x8DB3, 0xB736, 0x8DB4, 0xB737, 0x8DB5, 0xB738, 0xB6E4, 0xB739, 0xB6E5, 0xB73A, 0x8DB6, 0xB73B, 0xB6E6,
+ 0xB73C, 0x8DB7, 0xB73D, 0x8DB8, 0xB73E, 0x8DB9, 0xB73F, 0x8DBA, 0xB740, 0x8DBB, 0xB741, 0x8DBC, 0xB742, 0x8DBD, 0xB743, 0x8DBE,
+ 0xB744, 0xB6E7, 0xB745, 0x8DBF, 0xB746, 0x8DC0, 0xB747, 0x8DC1, 0xB748, 0xB6E8, 0xB749, 0x8DC2, 0xB74A, 0x8DC3, 0xB74B, 0x8DC4,
+ 0xB74C, 0xB6E9, 0xB74D, 0x8DC5, 0xB74E, 0x8DC6, 0xB74F, 0x8DC7, 0xB750, 0x8DC8, 0xB751, 0x8DC9, 0xB752, 0x8DCA, 0xB753, 0x8DCB,
+ 0xB754, 0xB6EA, 0xB755, 0xB6EB, 0xB756, 0x8DCC, 0xB757, 0x8DCD, 0xB758, 0x8DCE, 0xB759, 0x8DCF, 0xB75A, 0x8DD0, 0xB75B, 0x8DD1,
+ 0xB75C, 0x8DD2, 0xB75D, 0x8DD3, 0xB75E, 0x8DD4, 0xB75F, 0x8DD5, 0xB760, 0xB6EC, 0xB761, 0x8DD6, 0xB762, 0x8DD7, 0xB763, 0x8DD8,
+ 0xB764, 0xB6ED, 0xB765, 0x8DD9, 0xB766, 0x8DDA, 0xB767, 0x8DDB, 0xB768, 0xB6EE, 0xB769, 0x8DDC, 0xB76A, 0x8DDD, 0xB76B, 0x8DDE,
+ 0xB76C, 0x8DDF, 0xB76D, 0x8DE0, 0xB76E, 0x8DE1, 0xB76F, 0x8DE2, 0xB770, 0xB6EF, 0xB771, 0xB6F0, 0xB772, 0x8DE3, 0xB773, 0xB6F1,
+ 0xB774, 0x8DE4, 0xB775, 0xB6F2, 0xB776, 0x8DE5, 0xB777, 0x8DE6, 0xB778, 0x8DE7, 0xB779, 0x8DE8, 0xB77A, 0x8DE9, 0xB77B, 0x8DEA,
+ 0xB77C, 0xB6F3, 0xB77D, 0xB6F4, 0xB77E, 0x8DEB, 0xB77F, 0x8DEC, 0xB780, 0xB6F5, 0xB781, 0x8DED, 0xB782, 0x8DEE, 0xB783, 0x8DEF,
+ 0xB784, 0xB6F6, 0xB785, 0x8DF0, 0xB786, 0x8DF1, 0xB787, 0x8DF2, 0xB788, 0x8DF3, 0xB789, 0x8DF4, 0xB78A, 0x8DF5, 0xB78B, 0x8DF6,
+ 0xB78C, 0xB6F7, 0xB78D, 0xB6F8, 0xB78E, 0x8DF7, 0xB78F, 0xB6F9, 0xB790, 0xB6FA, 0xB791, 0xB6FB, 0xB792, 0xB6FC, 0xB793, 0x8DF8,
+ 0xB794, 0x8DF9, 0xB795, 0x8DFA, 0xB796, 0xB6FD, 0xB797, 0xB6FE, 0xB798, 0xB7A1, 0xB799, 0xB7A2, 0xB79A, 0x8DFB, 0xB79B, 0x8DFC,
+ 0xB79C, 0xB7A3, 0xB79D, 0x8DFD, 0xB79E, 0x8DFE, 0xB79F, 0x8E41, 0xB7A0, 0xB7A4, 0xB7A1, 0x8E42, 0xB7A2, 0x8E43, 0xB7A3, 0x8E44,
+ 0xB7A4, 0x8E45, 0xB7A5, 0x8E46, 0xB7A6, 0x8E47, 0xB7A7, 0x8E48, 0xB7A8, 0xB7A5, 0xB7A9, 0xB7A6, 0xB7AA, 0x8E49, 0xB7AB, 0xB7A7,
+ 0xB7AC, 0xB7A8, 0xB7AD, 0xB7A9, 0xB7AE, 0x8E4A, 0xB7AF, 0x8E4B, 0xB7B0, 0x8E4C, 0xB7B1, 0x8E4D, 0xB7B2, 0x8E4E, 0xB7B3, 0x8E4F,
+ 0xB7B4, 0xB7AA, 0xB7B5, 0xB7AB, 0xB7B6, 0x8E50, 0xB7B7, 0x8E51, 0xB7B8, 0xB7AC, 0xB7B9, 0x8E52, 0xB7BA, 0x8E53, 0xB7BB, 0x8E54,
+ 0xB7BC, 0x8E55, 0xB7BD, 0x8E56, 0xB7BE, 0x8E57, 0xB7BF, 0x8E58, 0xB7C0, 0x8E59, 0xB7C1, 0x8E5A, 0xB7C2, 0x8E61, 0xB7C3, 0x8E62,
+ 0xB7C4, 0x8E63, 0xB7C5, 0x8E64, 0xB7C6, 0x8E65, 0xB7C7, 0xB7AD, 0xB7C8, 0x8E66, 0xB7C9, 0xB7AE, 0xB7CA, 0x8E67, 0xB7CB, 0x8E68,
+ 0xB7CC, 0x8E69, 0xB7CD, 0x8E6A, 0xB7CE, 0x8E6B, 0xB7CF, 0x8E6C, 0xB7D0, 0x8E6D, 0xB7D1, 0x8E6E, 0xB7D2, 0x8E6F, 0xB7D3, 0x8E70,
+ 0xB7D4, 0x8E71, 0xB7D5, 0x8E72, 0xB7D6, 0x8E73, 0xB7D7, 0x8E74, 0xB7D8, 0x8E75, 0xB7D9, 0x8E76, 0xB7DA, 0x8E77, 0xB7DB, 0x8E78,
+ 0xB7DC, 0x8E79, 0xB7DD, 0x8E7A, 0xB7DE, 0x8E81, 0xB7DF, 0x8E82, 0xB7E0, 0x8E83, 0xB7E1, 0x8E84, 0xB7E2, 0x8E85, 0xB7E3, 0x8E86,
+ 0xB7E4, 0x8E87, 0xB7E5, 0x8E88, 0xB7E6, 0x8E89, 0xB7E7, 0x8E8A, 0xB7E8, 0x8E8B, 0xB7E9, 0x8E8C, 0xB7EA, 0x8E8D, 0xB7EB, 0x8E8E,
+ 0xB7EC, 0xB7AF, 0xB7ED, 0xB7B0, 0xB7EE, 0x8E8F, 0xB7EF, 0x8E90, 0xB7F0, 0xB7B1, 0xB7F1, 0x8E91, 0xB7F2, 0x8E92, 0xB7F3, 0x8E93,
+ 0xB7F4, 0xB7B2, 0xB7F5, 0x8E94, 0xB7F6, 0x8E95, 0xB7F7, 0x8E96, 0xB7F8, 0x8E97, 0xB7F9, 0x8E98, 0xB7FA, 0x8E99, 0xB7FB, 0x8E9A,
+ 0xB7FC, 0xB7B3, 0xB7FD, 0xB7B4, 0xB7FE, 0x8E9B, 0xB7FF, 0xB7B5, 0xB800, 0xB7B6, 0xB801, 0xB7B7, 0xB802, 0x8E9C, 0xB803, 0x8E9D,
+ 0xB804, 0x8E9E, 0xB805, 0x8E9F, 0xB806, 0x8EA0, 0xB807, 0xB7B8, 0xB808, 0xB7B9, 0xB809, 0xB7BA, 0xB80A, 0x8EA1, 0xB80B, 0x8EA2,
+ 0xB80C, 0xB7BB, 0xB80D, 0x8EA3, 0xB80E, 0x8EA4, 0xB80F, 0x8EA5, 0xB810, 0xB7BC, 0xB811, 0x8EA6, 0xB812, 0x8EA7, 0xB813, 0x8EA8,
+ 0xB814, 0x8EA9, 0xB815, 0x8EAA, 0xB816, 0x8EAB, 0xB817, 0x8EAC, 0xB818, 0xB7BD, 0xB819, 0xB7BE, 0xB81A, 0x8EAD, 0xB81B, 0xB7BF,
+ 0xB81C, 0x8EAE, 0xB81D, 0xB7C0, 0xB81E, 0x8EAF, 0xB81F, 0x8EB0, 0xB820, 0x8EB1, 0xB821, 0x8EB2, 0xB822, 0x8EB3, 0xB823, 0x8EB4,
+ 0xB824, 0xB7C1, 0xB825, 0xB7C2, 0xB826, 0x8EB5, 0xB827, 0x8EB6, 0xB828, 0xB7C3, 0xB829, 0x8EB7, 0xB82A, 0x8EB8, 0xB82B, 0x8EB9,
+ 0xB82C, 0xB7C4, 0xB82D, 0x8EBA, 0xB82E, 0x8EBB, 0xB82F, 0x8EBC, 0xB830, 0x8EBD, 0xB831, 0x8EBE, 0xB832, 0x8EBF, 0xB833, 0x8EC0,
+ 0xB834, 0xB7C5, 0xB835, 0xB7C6, 0xB836, 0x8EC1, 0xB837, 0xB7C7, 0xB838, 0xB7C8, 0xB839, 0xB7C9, 0xB83A, 0x8EC2, 0xB83B, 0x8EC3,
+ 0xB83C, 0x8EC4, 0xB83D, 0x8EC5, 0xB83E, 0x8EC6, 0xB83F, 0x8EC7, 0xB840, 0xB7CA, 0xB841, 0x8EC8, 0xB842, 0x8EC9, 0xB843, 0x8ECA,
+ 0xB844, 0xB7CB, 0xB845, 0x8ECB, 0xB846, 0x8ECC, 0xB847, 0x8ECD, 0xB848, 0x8ECE, 0xB849, 0x8ECF, 0xB84A, 0x8ED0, 0xB84B, 0x8ED1,
+ 0xB84C, 0x8ED2, 0xB84D, 0x8ED3, 0xB84E, 0x8ED4, 0xB84F, 0x8ED5, 0xB850, 0x8ED6, 0xB851, 0xB7CC, 0xB852, 0x8ED7, 0xB853, 0xB7CD,
+ 0xB854, 0x8ED8, 0xB855, 0x8ED9, 0xB856, 0x8EDA, 0xB857, 0x8EDB, 0xB858, 0x8EDC, 0xB859, 0x8EDD, 0xB85A, 0x8EDE, 0xB85B, 0x8EDF,
+ 0xB85C, 0xB7CE, 0xB85D, 0xB7CF, 0xB85E, 0x8EE0, 0xB85F, 0x8EE1, 0xB860, 0xB7D0, 0xB861, 0x8EE2, 0xB862, 0x8EE3, 0xB863, 0x8EE4,
+ 0xB864, 0xB7D1, 0xB865, 0x8EE5, 0xB866, 0x8EE6, 0xB867, 0x8EE7, 0xB868, 0x8EE8, 0xB869, 0x8EE9, 0xB86A, 0x8EEA, 0xB86B, 0x8EEB,
+ 0xB86C, 0xB7D2, 0xB86D, 0xB7D3, 0xB86E, 0x8EEC, 0xB86F, 0xB7D4, 0xB870, 0x8EED, 0xB871, 0xB7D5, 0xB872, 0x8EEE, 0xB873, 0x8EEF,
+ 0xB874, 0x8EF0, 0xB875, 0x8EF1, 0xB876, 0x8EF2, 0xB877, 0x8EF3, 0xB878, 0xB7D6, 0xB879, 0x8EF4, 0xB87A, 0x8EF5, 0xB87B, 0x8EF6,
+ 0xB87C, 0xB7D7, 0xB87D, 0x8EF7, 0xB87E, 0x8EF8, 0xB87F, 0x8EF9, 0xB880, 0x8EFA, 0xB881, 0x8EFB, 0xB882, 0x8EFC, 0xB883, 0x8EFD,
+ 0xB884, 0x8EFE, 0xB885, 0x8F41, 0xB886, 0x8F42, 0xB887, 0x8F43, 0xB888, 0x8F44, 0xB889, 0x8F45, 0xB88A, 0x8F46, 0xB88B, 0x8F47,
+ 0xB88C, 0x8F48, 0xB88D, 0xB7D8, 0xB88E, 0x8F49, 0xB88F, 0x8F4A, 0xB890, 0x8F4B, 0xB891, 0x8F4C, 0xB892, 0x8F4D, 0xB893, 0x8F4E,
+ 0xB894, 0x8F4F, 0xB895, 0x8F50, 0xB896, 0x8F51, 0xB897, 0x8F52, 0xB898, 0x8F53, 0xB899, 0x8F54, 0xB89A, 0x8F55, 0xB89B, 0x8F56,
+ 0xB89C, 0x8F57, 0xB89D, 0x8F58, 0xB89E, 0x8F59, 0xB89F, 0x8F5A, 0xB8A0, 0x8F61, 0xB8A1, 0x8F62, 0xB8A2, 0x8F63, 0xB8A3, 0x8F64,
+ 0xB8A4, 0x8F65, 0xB8A5, 0x8F66, 0xB8A6, 0x8F67, 0xB8A7, 0x8F68, 0xB8A8, 0xB7D9, 0xB8A9, 0x8F69, 0xB8AA, 0x8F6A, 0xB8AB, 0x8F6B,
+ 0xB8AC, 0x8F6C, 0xB8AD, 0x8F6D, 0xB8AE, 0x8F6E, 0xB8AF, 0x8F6F, 0xB8B0, 0xB7DA, 0xB8B1, 0x8F70, 0xB8B2, 0x8F71, 0xB8B3, 0x8F72,
+ 0xB8B4, 0xB7DB, 0xB8B5, 0x8F73, 0xB8B6, 0x8F74, 0xB8B7, 0x8F75, 0xB8B8, 0xB7DC, 0xB8B9, 0x8F76, 0xB8BA, 0x8F77, 0xB8BB, 0x8F78,
+ 0xB8BC, 0x8F79, 0xB8BD, 0x8F7A, 0xB8BE, 0x8F81, 0xB8BF, 0x8F82, 0xB8C0, 0xB7DD, 0xB8C1, 0xB7DE, 0xB8C2, 0x8F83, 0xB8C3, 0xB7DF,
+ 0xB8C4, 0x8F84, 0xB8C5, 0xB7E0, 0xB8C6, 0x8F85, 0xB8C7, 0x8F86, 0xB8C8, 0x8F87, 0xB8C9, 0x8F88, 0xB8CA, 0x8F89, 0xB8CB, 0x8F8A,
+ 0xB8CC, 0xB7E1, 0xB8CD, 0x8F8B, 0xB8CE, 0x8F8C, 0xB8CF, 0x8F8D, 0xB8D0, 0xB7E2, 0xB8D1, 0x8F8E, 0xB8D2, 0x8F8F, 0xB8D3, 0x8F90,
+ 0xB8D4, 0xB7E3, 0xB8D5, 0x8F91, 0xB8D6, 0x8F92, 0xB8D7, 0x8F93, 0xB8D8, 0x8F94, 0xB8D9, 0x8F95, 0xB8DA, 0x8F96, 0xB8DB, 0x8F97,
+ 0xB8DC, 0x8F98, 0xB8DD, 0xB7E4, 0xB8DE, 0x8F99, 0xB8DF, 0xB7E5, 0xB8E0, 0x8F9A, 0xB8E1, 0xB7E6, 0xB8E2, 0x8F9B, 0xB8E3, 0x8F9C,
+ 0xB8E4, 0x8F9D, 0xB8E5, 0x8F9E, 0xB8E6, 0x8F9F, 0xB8E7, 0x8FA0, 0xB8E8, 0xB7E7, 0xB8E9, 0xB7E8, 0xB8EA, 0x8FA1, 0xB8EB, 0x8FA2,
+ 0xB8EC, 0xB7E9, 0xB8ED, 0x8FA3, 0xB8EE, 0x8FA4, 0xB8EF, 0x8FA5, 0xB8F0, 0xB7EA, 0xB8F1, 0x8FA6, 0xB8F2, 0x8FA7, 0xB8F3, 0x8FA8,
+ 0xB8F4, 0x8FA9, 0xB8F5, 0x8FAA, 0xB8F6, 0x8FAB, 0xB8F7, 0x8FAC, 0xB8F8, 0xB7EB, 0xB8F9, 0xB7EC, 0xB8FA, 0x8FAD, 0xB8FB, 0xB7ED,
+ 0xB8FC, 0x8FAE, 0xB8FD, 0xB7EE, 0xB8FE, 0x8FAF, 0xB8FF, 0x8FB0, 0xB900, 0x8FB1, 0xB901, 0x8FB2, 0xB902, 0x8FB3, 0xB903, 0x8FB4,
+ 0xB904, 0xB7EF, 0xB905, 0x8FB5, 0xB906, 0x8FB6, 0xB907, 0x8FB7, 0xB908, 0x8FB8, 0xB909, 0x8FB9, 0xB90A, 0x8FBA, 0xB90B, 0x8FBB,
+ 0xB90C, 0x8FBC, 0xB90D, 0x8FBD, 0xB90E, 0x8FBE, 0xB90F, 0x8FBF, 0xB910, 0x8FC0, 0xB911, 0x8FC1, 0xB912, 0x8FC2, 0xB913, 0x8FC3,
+ 0xB914, 0x8FC4, 0xB915, 0x8FC5, 0xB916, 0x8FC6, 0xB917, 0x8FC7, 0xB918, 0xB7F0, 0xB919, 0x8FC8, 0xB91A, 0x8FC9, 0xB91B, 0x8FCA,
+ 0xB91C, 0x8FCB, 0xB91D, 0x8FCC, 0xB91E, 0x8FCD, 0xB91F, 0x8FCE, 0xB920, 0xB7F1, 0xB921, 0x8FCF, 0xB922, 0x8FD0, 0xB923, 0x8FD1,
+ 0xB924, 0x8FD2, 0xB925, 0x8FD3, 0xB926, 0x8FD4, 0xB927, 0x8FD5, 0xB928, 0x8FD6, 0xB929, 0x8FD7, 0xB92A, 0x8FD8, 0xB92B, 0x8FD9,
+ 0xB92C, 0x8FDA, 0xB92D, 0x8FDB, 0xB92E, 0x8FDC, 0xB92F, 0x8FDD, 0xB930, 0x8FDE, 0xB931, 0x8FDF, 0xB932, 0x8FE0, 0xB933, 0x8FE1,
+ 0xB934, 0x8FE2, 0xB935, 0x8FE3, 0xB936, 0x8FE4, 0xB937, 0x8FE5, 0xB938, 0x8FE6, 0xB939, 0x8FE7, 0xB93A, 0x8FE8, 0xB93B, 0x8FE9,
+ 0xB93C, 0xB7F2, 0xB93D, 0xB7F3, 0xB93E, 0x8FEA, 0xB93F, 0x8FEB, 0xB940, 0xB7F4, 0xB941, 0x8FEC, 0xB942, 0x8FED, 0xB943, 0x8FEE,
+ 0xB944, 0xB7F5, 0xB945, 0x8FEF, 0xB946, 0x8FF0, 0xB947, 0x8FF1, 0xB948, 0x8FF2, 0xB949, 0x8FF3, 0xB94A, 0x8FF4, 0xB94B, 0x8FF5,
+ 0xB94C, 0xB7F6, 0xB94D, 0x8FF6, 0xB94E, 0x8FF7, 0xB94F, 0xB7F7, 0xB950, 0x8FF8, 0xB951, 0xB7F8, 0xB952, 0x8FF9, 0xB953, 0x8FFA,
+ 0xB954, 0x8FFB, 0xB955, 0x8FFC, 0xB956, 0x8FFD, 0xB957, 0x8FFE, 0xB958, 0xB7F9, 0xB959, 0xB7FA, 0xB95A, 0x9041, 0xB95B, 0x9042,
+ 0xB95C, 0xB7FB, 0xB95D, 0x9043, 0xB95E, 0x9044, 0xB95F, 0x9045, 0xB960, 0xB7FC, 0xB961, 0x9046, 0xB962, 0x9047, 0xB963, 0x9048,
+ 0xB964, 0x9049, 0xB965, 0x904A, 0xB966, 0x904B, 0xB967, 0x904C, 0xB968, 0xB7FD, 0xB969, 0xB7FE, 0xB96A, 0x904D, 0xB96B, 0xB8A1,
+ 0xB96C, 0x904E, 0xB96D, 0xB8A2, 0xB96E, 0x904F, 0xB96F, 0x9050, 0xB970, 0x9051, 0xB971, 0x9052, 0xB972, 0x9053, 0xB973, 0x9054,
+ 0xB974, 0xB8A3, 0xB975, 0xB8A4, 0xB976, 0x9055, 0xB977, 0x9056, 0xB978, 0xB8A5, 0xB979, 0x9057, 0xB97A, 0x9058, 0xB97B, 0x9059,
+ 0xB97C, 0xB8A6, 0xB97D, 0x905A, 0xB97E, 0x9061, 0xB97F, 0x9062, 0xB980, 0x9063, 0xB981, 0x9064, 0xB982, 0x9065, 0xB983, 0x9066,
+ 0xB984, 0xB8A7, 0xB985, 0xB8A8, 0xB986, 0x9067, 0xB987, 0xB8A9, 0xB988, 0x9068, 0xB989, 0xB8AA, 0xB98A, 0xB8AB, 0xB98B, 0x9069,
+ 0xB98C, 0x906A, 0xB98D, 0xB8AC, 0xB98E, 0xB8AD, 0xB98F, 0x906B, 0xB990, 0x906C, 0xB991, 0x906D, 0xB992, 0x906E, 0xB993, 0x906F,
+ 0xB994, 0x9070, 0xB995, 0x9071, 0xB996, 0x9072, 0xB997, 0x9073, 0xB998, 0x9074, 0xB999, 0x9075, 0xB99A, 0x9076, 0xB99B, 0x9077,
+ 0xB99C, 0x9078, 0xB99D, 0x9079, 0xB99E, 0x907A, 0xB99F, 0x9081, 0xB9A0, 0x9082, 0xB9A1, 0x9083, 0xB9A2, 0x9084, 0xB9A3, 0x9085,
+ 0xB9A4, 0x9086, 0xB9A5, 0x9087, 0xB9A6, 0x9088, 0xB9A7, 0x9089, 0xB9A8, 0x908A, 0xB9A9, 0x908B, 0xB9AA, 0x908C, 0xB9AB, 0x908D,
+ 0xB9AC, 0xB8AE, 0xB9AD, 0xB8AF, 0xB9AE, 0x908E, 0xB9AF, 0x908F, 0xB9B0, 0xB8B0, 0xB9B1, 0x9090, 0xB9B2, 0x9091, 0xB9B3, 0x9092,
+ 0xB9B4, 0xB8B1, 0xB9B5, 0x9093, 0xB9B6, 0x9094, 0xB9B7, 0x9095, 0xB9B8, 0x9096, 0xB9B9, 0x9097, 0xB9BA, 0x9098, 0xB9BB, 0x9099,
+ 0xB9BC, 0xB8B2, 0xB9BD, 0xB8B3, 0xB9BE, 0x909A, 0xB9BF, 0xB8B4, 0xB9C0, 0x909B, 0xB9C1, 0xB8B5, 0xB9C2, 0x909C, 0xB9C3, 0x909D,
+ 0xB9C4, 0x909E, 0xB9C5, 0x909F, 0xB9C6, 0x90A0, 0xB9C7, 0x90A1, 0xB9C8, 0xB8B6, 0xB9C9, 0xB8B7, 0xB9CA, 0x90A2, 0xB9CB, 0x90A3,
+ 0xB9CC, 0xB8B8, 0xB9CD, 0x90A4, 0xB9CE, 0xB8B9, 0xB9CF, 0xB8BA, 0xB9D0, 0xB8BB, 0xB9D1, 0xB8BC, 0xB9D2, 0xB8BD, 0xB9D3, 0x90A5,
+ 0xB9D4, 0x90A6, 0xB9D5, 0x90A7, 0xB9D6, 0x90A8, 0xB9D7, 0x90A9, 0xB9D8, 0xB8BE, 0xB9D9, 0xB8BF, 0xB9DA, 0x90AA, 0xB9DB, 0xB8C0,
+ 0xB9DC, 0x90AB, 0xB9DD, 0xB8C1, 0xB9DE, 0xB8C2, 0xB9DF, 0x90AC, 0xB9E0, 0x90AD, 0xB9E1, 0xB8C3, 0xB9E2, 0x90AE, 0xB9E3, 0xB8C4,
+ 0xB9E4, 0xB8C5, 0xB9E5, 0xB8C6, 0xB9E6, 0x90AF, 0xB9E7, 0x90B0, 0xB9E8, 0xB8C7, 0xB9E9, 0x90B1, 0xB9EA, 0x90B2, 0xB9EB, 0x90B3,
+ 0xB9EC, 0xB8C8, 0xB9ED, 0x90B4, 0xB9EE, 0x90B5, 0xB9EF, 0x90B6, 0xB9F0, 0x90B7, 0xB9F1, 0x90B8, 0xB9F2, 0x90B9, 0xB9F3, 0x90BA,
+ 0xB9F4, 0xB8C9, 0xB9F5, 0xB8CA, 0xB9F6, 0x90BB, 0xB9F7, 0xB8CB, 0xB9F8, 0xB8CC, 0xB9F9, 0xB8CD, 0xB9FA, 0xB8CE, 0xB9FB, 0x90BC,
+ 0xB9FC, 0x90BD, 0xB9FD, 0x90BE, 0xB9FE, 0x90BF, 0xB9FF, 0x90C0, 0xBA00, 0xB8CF, 0xBA01, 0xB8D0, 0xBA02, 0x90C1, 0xBA03, 0x90C2,
+ 0xBA04, 0x90C3, 0xBA05, 0x90C4, 0xBA06, 0x90C5, 0xBA07, 0x90C6, 0xBA08, 0xB8D1, 0xBA09, 0x90C7, 0xBA0A, 0x90C8, 0xBA0B, 0x90C9,
+ 0xBA0C, 0x90CA, 0xBA0D, 0x90CB, 0xBA0E, 0x90CC, 0xBA0F, 0x90CD, 0xBA10, 0x90CE, 0xBA11, 0x90CF, 0xBA12, 0x90D0, 0xBA13, 0x90D1,
+ 0xBA14, 0x90D2, 0xBA15, 0xB8D2, 0xBA16, 0x90D3, 0xBA17, 0x90D4, 0xBA18, 0x90D5, 0xBA19, 0x90D6, 0xBA1A, 0x90D7, 0xBA1B, 0x90D8,
+ 0xBA1C, 0x90D9, 0xBA1D, 0x90DA, 0xBA1E, 0x90DB, 0xBA1F, 0x90DC, 0xBA20, 0x90DD, 0xBA21, 0x90DE, 0xBA22, 0x90DF, 0xBA23, 0x90E0,
+ 0xBA24, 0x90E1, 0xBA25, 0x90E2, 0xBA26, 0x90E3, 0xBA27, 0x90E4, 0xBA28, 0x90E5, 0xBA29, 0x90E6, 0xBA2A, 0x90E7, 0xBA2B, 0x90E8,
+ 0xBA2C, 0x90E9, 0xBA2D, 0x90EA, 0xBA2E, 0x90EB, 0xBA2F, 0x90EC, 0xBA30, 0x90ED, 0xBA31, 0x90EE, 0xBA32, 0x90EF, 0xBA33, 0x90F0,
+ 0xBA34, 0x90F1, 0xBA35, 0x90F2, 0xBA36, 0x90F3, 0xBA37, 0x90F4, 0xBA38, 0xB8D3, 0xBA39, 0xB8D4, 0xBA3A, 0x90F5, 0xBA3B, 0x90F6,
+ 0xBA3C, 0xB8D5, 0xBA3D, 0x90F7, 0xBA3E, 0x90F8, 0xBA3F, 0x90F9, 0xBA40, 0xB8D6, 0xBA41, 0x90FA, 0xBA42, 0xB8D7, 0xBA43, 0x90FB,
+ 0xBA44, 0x90FC, 0xBA45, 0x90FD, 0xBA46, 0x90FE, 0xBA47, 0x9141, 0xBA48, 0xB8D8, 0xBA49, 0xB8D9, 0xBA4A, 0x9142, 0xBA4B, 0xB8DA,
+ 0xBA4C, 0x9143, 0xBA4D, 0xB8DB, 0xBA4E, 0xB8DC, 0xBA4F, 0x9144, 0xBA50, 0x9145, 0xBA51, 0x9146, 0xBA52, 0x9147, 0xBA53, 0xB8DD,
+ 0xBA54, 0xB8DE, 0xBA55, 0xB8DF, 0xBA56, 0x9148, 0xBA57, 0x9149, 0xBA58, 0xB8E0, 0xBA59, 0x914A, 0xBA5A, 0x914B, 0xBA5B, 0x914C,
+ 0xBA5C, 0xB8E1, 0xBA5D, 0x914D, 0xBA5E, 0x914E, 0xBA5F, 0x914F, 0xBA60, 0x9150, 0xBA61, 0x9151, 0xBA62, 0x9152, 0xBA63, 0x9153,
+ 0xBA64, 0xB8E2, 0xBA65, 0xB8E3, 0xBA66, 0x9154, 0xBA67, 0xB8E4, 0xBA68, 0xB8E5, 0xBA69, 0xB8E6, 0xBA6A, 0x9155, 0xBA6B, 0x9156,
+ 0xBA6C, 0x9157, 0xBA6D, 0x9158, 0xBA6E, 0x9159, 0xBA6F, 0x915A, 0xBA70, 0xB8E7, 0xBA71, 0xB8E8, 0xBA72, 0x9161, 0xBA73, 0x9162,
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+ 0xBFFC, 0x97BC, 0xBFFD, 0x97BD, 0xBFFE, 0x97BE, 0xBFFF, 0x97BF, 0xC000, 0x97C0, 0xC001, 0x97C1, 0xC002, 0x97C2, 0xC003, 0x97C3,
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+ 0xC00C, 0x97CC, 0xC00D, 0x97CD, 0xC00E, 0x97CE, 0xC00F, 0x97CF, 0xC010, 0x97D0, 0xC011, 0x97D1, 0xC012, 0x97D2, 0xC013, 0x97D3,
+ 0xC014, 0x97D4, 0xC015, 0x97D5, 0xC016, 0x97D6, 0xC017, 0x97D7, 0xC018, 0x97D8, 0xC019, 0x97D9, 0xC01A, 0x97DA, 0xC01B, 0x97DB,
+ 0xC01C, 0x97DC, 0xC01D, 0x97DD, 0xC01E, 0x97DE, 0xC01F, 0x97DF, 0xC020, 0x97E0, 0xC021, 0x97E1, 0xC022, 0x97E2, 0xC023, 0x97E3,
+ 0xC024, 0x97E4, 0xC025, 0x97E5, 0xC026, 0x97E6, 0xC027, 0x97E7, 0xC028, 0x97E8, 0xC029, 0x97E9, 0xC02A, 0x97EA, 0xC02B, 0x97EB,
+ 0xC02C, 0x97EC, 0xC02D, 0x97ED, 0xC02E, 0x97EE, 0xC02F, 0x97EF, 0xC030, 0x97F0, 0xC031, 0x97F1, 0xC032, 0x97F2, 0xC033, 0x97F3,
+ 0xC034, 0x97F4, 0xC035, 0x97F5, 0xC036, 0x97F6, 0xC037, 0x97F7, 0xC038, 0x97F8, 0xC039, 0x97F9, 0xC03A, 0x97FA, 0xC03B, 0x97FB,
+ 0xC03C, 0xBBD8, 0xC03D, 0x97FC, 0xC03E, 0x97FD, 0xC03F, 0x97FE, 0xC040, 0x9841, 0xC041, 0x9842, 0xC042, 0x9843, 0xC043, 0x9844,
+ 0xC044, 0x9845, 0xC045, 0x9846, 0xC046, 0x9847, 0xC047, 0x9848, 0xC048, 0x9849, 0xC049, 0x984A, 0xC04A, 0x984B, 0xC04B, 0x984C,
+ 0xC04C, 0x984D, 0xC04D, 0x984E, 0xC04E, 0x984F, 0xC04F, 0x9850, 0xC050, 0x9851, 0xC051, 0xBBD9, 0xC052, 0x9852, 0xC053, 0x9853,
+ 0xC054, 0x9854, 0xC055, 0x9855, 0xC056, 0x9856, 0xC057, 0x9857, 0xC058, 0xBBDA, 0xC059, 0x9858, 0xC05A, 0x9859, 0xC05B, 0x985A,
+ 0xC05C, 0xBBDB, 0xC05D, 0x9861, 0xC05E, 0x9862, 0xC05F, 0x9863, 0xC060, 0xBBDC, 0xC061, 0x9864, 0xC062, 0x9865, 0xC063, 0x9866,
+ 0xC064, 0x9867, 0xC065, 0x9868, 0xC066, 0x9869, 0xC067, 0x986A, 0xC068, 0xBBDD, 0xC069, 0xBBDE, 0xC06A, 0x986B, 0xC06B, 0x986C,
+ 0xC06C, 0x986D, 0xC06D, 0x986E, 0xC06E, 0x986F, 0xC06F, 0x9870, 0xC070, 0x9871, 0xC071, 0x9872, 0xC072, 0x9873, 0xC073, 0x9874,
+ 0xC074, 0x9875, 0xC075, 0x9876, 0xC076, 0x9877, 0xC077, 0x9878, 0xC078, 0x9879, 0xC079, 0x987A, 0xC07A, 0x9881, 0xC07B, 0x9882,
+ 0xC07C, 0x9883, 0xC07D, 0x9884, 0xC07E, 0x9885, 0xC07F, 0x9886, 0xC080, 0x9887, 0xC081, 0x9888, 0xC082, 0x9889, 0xC083, 0x988A,
+ 0xC084, 0x988B, 0xC085, 0x988C, 0xC086, 0x988D, 0xC087, 0x988E, 0xC088, 0x988F, 0xC089, 0x9890, 0xC08A, 0x9891, 0xC08B, 0x9892,
+ 0xC08C, 0x9893, 0xC08D, 0x9894, 0xC08E, 0x9895, 0xC08F, 0x9896, 0xC090, 0xBBDF, 0xC091, 0xBBE0, 0xC092, 0x9897, 0xC093, 0x9898,
+ 0xC094, 0xBBE1, 0xC095, 0x9899, 0xC096, 0x989A, 0xC097, 0x989B, 0xC098, 0xBBE2, 0xC099, 0x989C, 0xC09A, 0x989D, 0xC09B, 0x989E,
+ 0xC09C, 0x989F, 0xC09D, 0x98A0, 0xC09E, 0x98A1, 0xC09F, 0x98A2, 0xC0A0, 0xBBE3, 0xC0A1, 0xBBE4, 0xC0A2, 0x98A3, 0xC0A3, 0xBBE5,
+ 0xC0A4, 0x98A4, 0xC0A5, 0xBBE6, 0xC0A6, 0x98A5, 0xC0A7, 0x98A6, 0xC0A8, 0x98A7, 0xC0A9, 0x98A8, 0xC0AA, 0x98A9, 0xC0AB, 0x98AA,
+ 0xC0AC, 0xBBE7, 0xC0AD, 0xBBE8, 0xC0AE, 0x98AB, 0xC0AF, 0xBBE9, 0xC0B0, 0xBBEA, 0xC0B1, 0x98AC, 0xC0B2, 0x98AD, 0xC0B3, 0xBBEB,
+ 0xC0B4, 0xBBEC, 0xC0B5, 0xBBED, 0xC0B6, 0xBBEE, 0xC0B7, 0x98AE, 0xC0B8, 0x98AF, 0xC0B9, 0x98B0, 0xC0BA, 0x98B1, 0xC0BB, 0x98B2,
+ 0xC0BC, 0xBBEF, 0xC0BD, 0xBBF0, 0xC0BE, 0x98B3, 0xC0BF, 0xBBF1, 0xC0C0, 0xBBF2, 0xC0C1, 0xBBF3, 0xC0C2, 0x98B4, 0xC0C3, 0x98B5,
+ 0xC0C4, 0x98B6, 0xC0C5, 0xBBF4, 0xC0C6, 0x98B7, 0xC0C7, 0x98B8, 0xC0C8, 0xBBF5, 0xC0C9, 0xBBF6, 0xC0CA, 0x98B9, 0xC0CB, 0x98BA,
+ 0xC0CC, 0xBBF7, 0xC0CD, 0x98BB, 0xC0CE, 0x98BC, 0xC0CF, 0x98BD, 0xC0D0, 0xBBF8, 0xC0D1, 0x98BE, 0xC0D2, 0x98BF, 0xC0D3, 0x98C0,
+ 0xC0D4, 0x98C1, 0xC0D5, 0x98C2, 0xC0D6, 0x98C3, 0xC0D7, 0x98C4, 0xC0D8, 0xBBF9, 0xC0D9, 0xBBFA, 0xC0DA, 0x98C5, 0xC0DB, 0xBBFB,
+ 0xC0DC, 0xBBFC, 0xC0DD, 0xBBFD, 0xC0DE, 0x98C6, 0xC0DF, 0x98C7, 0xC0E0, 0x98C8, 0xC0E1, 0x98C9, 0xC0E2, 0x98CA, 0xC0E3, 0x98CB,
+ 0xC0E4, 0xBBFE, 0xC0E5, 0xBCA1, 0xC0E6, 0x98CC, 0xC0E7, 0x98CD, 0xC0E8, 0xBCA2, 0xC0E9, 0x98CE, 0xC0EA, 0x98CF, 0xC0EB, 0x98D0,
+ 0xC0EC, 0xBCA3, 0xC0ED, 0x98D1, 0xC0EE, 0x98D2, 0xC0EF, 0x98D3, 0xC0F0, 0x98D4, 0xC0F1, 0x98D5, 0xC0F2, 0x98D6, 0xC0F3, 0x98D7,
+ 0xC0F4, 0xBCA4, 0xC0F5, 0xBCA5, 0xC0F6, 0x98D8, 0xC0F7, 0xBCA6, 0xC0F8, 0x98D9, 0xC0F9, 0xBCA7, 0xC0FA, 0x98DA, 0xC0FB, 0x98DB,
+ 0xC0FC, 0x98DC, 0xC0FD, 0x98DD, 0xC0FE, 0x98DE, 0xC0FF, 0x98DF, 0xC100, 0xBCA8, 0xC101, 0x98E0, 0xC102, 0x98E1, 0xC103, 0x98E2,
+ 0xC104, 0xBCA9, 0xC105, 0x98E3, 0xC106, 0x98E4, 0xC107, 0x98E5, 0xC108, 0xBCAA, 0xC109, 0x98E6, 0xC10A, 0x98E7, 0xC10B, 0x98E8,
+ 0xC10C, 0x98E9, 0xC10D, 0x98EA, 0xC10E, 0x98EB, 0xC10F, 0x98EC, 0xC110, 0xBCAB, 0xC111, 0x98ED, 0xC112, 0x98EE, 0xC113, 0x98EF,
+ 0xC114, 0x98F0, 0xC115, 0xBCAC, 0xC116, 0x98F1, 0xC117, 0x98F2, 0xC118, 0x98F3, 0xC119, 0x98F4, 0xC11A, 0x98F5, 0xC11B, 0x98F6,
+ 0xC11C, 0xBCAD, 0xC11D, 0xBCAE, 0xC11E, 0xBCAF, 0xC11F, 0xBCB0, 0xC120, 0xBCB1, 0xC121, 0x98F7, 0xC122, 0x98F8, 0xC123, 0xBCB2,
+ 0xC124, 0xBCB3, 0xC125, 0x98F9, 0xC126, 0xBCB4, 0xC127, 0xBCB5, 0xC128, 0x98FA, 0xC129, 0x98FB, 0xC12A, 0x98FC, 0xC12B, 0x98FD,
+ 0xC12C, 0xBCB6, 0xC12D, 0xBCB7, 0xC12E, 0x98FE, 0xC12F, 0xBCB8, 0xC130, 0xBCB9, 0xC131, 0xBCBA, 0xC132, 0x9941, 0xC133, 0x9942,
+ 0xC134, 0x9943, 0xC135, 0x9944, 0xC136, 0xBCBB, 0xC137, 0x9945, 0xC138, 0xBCBC, 0xC139, 0xBCBD, 0xC13A, 0x9946, 0xC13B, 0x9947,
+ 0xC13C, 0xBCBE, 0xC13D, 0x9948, 0xC13E, 0x9949, 0xC13F, 0x994A, 0xC140, 0xBCBF, 0xC141, 0x994B, 0xC142, 0x994C, 0xC143, 0x994D,
+ 0xC144, 0x994E, 0xC145, 0x994F, 0xC146, 0x9950, 0xC147, 0x9951, 0xC148, 0xBCC0, 0xC149, 0xBCC1, 0xC14A, 0x9952, 0xC14B, 0xBCC2,
+ 0xC14C, 0xBCC3, 0xC14D, 0xBCC4, 0xC14E, 0x9953, 0xC14F, 0x9954, 0xC150, 0x9955, 0xC151, 0x9956, 0xC152, 0x9957, 0xC153, 0x9958,
+ 0xC154, 0xBCC5, 0xC155, 0xBCC6, 0xC156, 0x9959, 0xC157, 0x995A, 0xC158, 0xBCC7, 0xC159, 0x9961, 0xC15A, 0x9962, 0xC15B, 0x9963,
+ 0xC15C, 0xBCC8, 0xC15D, 0x9964, 0xC15E, 0x9965, 0xC15F, 0x9966, 0xC160, 0x9967, 0xC161, 0x9968, 0xC162, 0x9969, 0xC163, 0x996A,
+ 0xC164, 0xBCC9, 0xC165, 0xBCCA, 0xC166, 0x996B, 0xC167, 0xBCCB, 0xC168, 0xBCCC, 0xC169, 0xBCCD, 0xC16A, 0x996C, 0xC16B, 0x996D,
+ 0xC16C, 0x996E, 0xC16D, 0x996F, 0xC16E, 0x9970, 0xC16F, 0x9971, 0xC170, 0xBCCE, 0xC171, 0x9972, 0xC172, 0x9973, 0xC173, 0x9974,
+ 0xC174, 0xBCCF, 0xC175, 0x9975, 0xC176, 0x9976, 0xC177, 0x9977, 0xC178, 0xBCD0, 0xC179, 0x9978, 0xC17A, 0x9979, 0xC17B, 0x997A,
+ 0xC17C, 0x9981, 0xC17D, 0x9982, 0xC17E, 0x9983, 0xC17F, 0x9984, 0xC180, 0x9985, 0xC181, 0x9986, 0xC182, 0x9987, 0xC183, 0x9988,
+ 0xC184, 0x9989, 0xC185, 0xBCD1, 0xC186, 0x998A, 0xC187, 0x998B, 0xC188, 0x998C, 0xC189, 0x998D, 0xC18A, 0x998E, 0xC18B, 0x998F,
+ 0xC18C, 0xBCD2, 0xC18D, 0xBCD3, 0xC18E, 0xBCD4, 0xC18F, 0x9990, 0xC190, 0xBCD5, 0xC191, 0x9991, 0xC192, 0x9992, 0xC193, 0x9993,
+ 0xC194, 0xBCD6, 0xC195, 0x9994, 0xC196, 0xBCD7, 0xC197, 0x9995, 0xC198, 0x9996, 0xC199, 0x9997, 0xC19A, 0x9998, 0xC19B, 0x9999,
+ 0xC19C, 0xBCD8, 0xC19D, 0xBCD9, 0xC19E, 0x999A, 0xC19F, 0xBCDA, 0xC1A0, 0x999B, 0xC1A1, 0xBCDB, 0xC1A2, 0x999C, 0xC1A3, 0x999D,
+ 0xC1A4, 0x999E, 0xC1A5, 0xBCDC, 0xC1A6, 0x999F, 0xC1A7, 0x99A0, 0xC1A8, 0xBCDD, 0xC1A9, 0xBCDE, 0xC1AA, 0x99A1, 0xC1AB, 0x99A2,
+ 0xC1AC, 0xBCDF, 0xC1AD, 0x99A3, 0xC1AE, 0x99A4, 0xC1AF, 0x99A5, 0xC1B0, 0xBCE0, 0xC1B1, 0x99A6, 0xC1B2, 0x99A7, 0xC1B3, 0x99A8,
+ 0xC1B4, 0x99A9, 0xC1B5, 0x99AA, 0xC1B6, 0x99AB, 0xC1B7, 0x99AC, 0xC1B8, 0x99AD, 0xC1B9, 0x99AE, 0xC1BA, 0x99AF, 0xC1BB, 0x99B0,
+ 0xC1BC, 0x99B1, 0xC1BD, 0xBCE1, 0xC1BE, 0x99B2, 0xC1BF, 0x99B3, 0xC1C0, 0x99B4, 0xC1C1, 0x99B5, 0xC1C2, 0x99B6, 0xC1C3, 0x99B7,
+ 0xC1C4, 0xBCE2, 0xC1C5, 0x99B8, 0xC1C6, 0x99B9, 0xC1C7, 0x99BA, 0xC1C8, 0xBCE3, 0xC1C9, 0x99BB, 0xC1CA, 0x99BC, 0xC1CB, 0x99BD,
+ 0xC1CC, 0xBCE4, 0xC1CD, 0x99BE, 0xC1CE, 0x99BF, 0xC1CF, 0x99C0, 0xC1D0, 0x99C1, 0xC1D1, 0x99C2, 0xC1D2, 0x99C3, 0xC1D3, 0x99C4,
+ 0xC1D4, 0xBCE5, 0xC1D5, 0x99C5, 0xC1D6, 0x99C6, 0xC1D7, 0xBCE6, 0xC1D8, 0xBCE7, 0xC1D9, 0x99C7, 0xC1DA, 0x99C8, 0xC1DB, 0x99C9,
+ 0xC1DC, 0x99CA, 0xC1DD, 0x99CB, 0xC1DE, 0x99CC, 0xC1DF, 0x99CD, 0xC1E0, 0xBCE8, 0xC1E1, 0x99CE, 0xC1E2, 0x99CF, 0xC1E3, 0x99D0,
+ 0xC1E4, 0xBCE9, 0xC1E5, 0x99D1, 0xC1E6, 0x99D2, 0xC1E7, 0x99D3, 0xC1E8, 0xBCEA, 0xC1E9, 0x99D4, 0xC1EA, 0x99D5, 0xC1EB, 0x99D6,
+ 0xC1EC, 0x99D7, 0xC1ED, 0x99D8, 0xC1EE, 0x99D9, 0xC1EF, 0x99DA, 0xC1F0, 0xBCEB, 0xC1F1, 0xBCEC, 0xC1F2, 0x99DB, 0xC1F3, 0xBCED,
+ 0xC1F4, 0x99DC, 0xC1F5, 0x99DD, 0xC1F6, 0x99DE, 0xC1F7, 0x99DF, 0xC1F8, 0x99E0, 0xC1F9, 0x99E1, 0xC1FA, 0x99E2, 0xC1FB, 0x99E3,
+ 0xC1FC, 0xBCEE, 0xC1FD, 0xBCEF, 0xC1FE, 0x99E4, 0xC1FF, 0x99E5, 0xC200, 0xBCF0, 0xC201, 0x99E6, 0xC202, 0x99E7, 0xC203, 0x99E8,
+ 0xC204, 0xBCF1, 0xC205, 0x99E9, 0xC206, 0x99EA, 0xC207, 0x99EB, 0xC208, 0x99EC, 0xC209, 0x99ED, 0xC20A, 0x99EE, 0xC20B, 0x99EF,
+ 0xC20C, 0xBCF2, 0xC20D, 0xBCF3, 0xC20E, 0x99F0, 0xC20F, 0xBCF4, 0xC210, 0x99F1, 0xC211, 0xBCF5, 0xC212, 0x99F2, 0xC213, 0x99F3,
+ 0xC214, 0x99F4, 0xC215, 0x99F5, 0xC216, 0x99F6, 0xC217, 0x99F7, 0xC218, 0xBCF6, 0xC219, 0xBCF7, 0xC21A, 0x99F8, 0xC21B, 0x99F9,
+ 0xC21C, 0xBCF8, 0xC21D, 0x99FA, 0xC21E, 0x99FB, 0xC21F, 0xBCF9, 0xC220, 0xBCFA, 0xC221, 0x99FC, 0xC222, 0x99FD, 0xC223, 0x99FE,
+ 0xC224, 0x9A41, 0xC225, 0x9A42, 0xC226, 0x9A43, 0xC227, 0x9A44, 0xC228, 0xBCFB, 0xC229, 0xBCFC, 0xC22A, 0x9A45, 0xC22B, 0xBCFD,
+ 0xC22C, 0x9A46, 0xC22D, 0xBCFE, 0xC22E, 0x9A47, 0xC22F, 0xBDA1, 0xC230, 0x9A48, 0xC231, 0xBDA2, 0xC232, 0xBDA3, 0xC233, 0x9A49,
+ 0xC234, 0xBDA4, 0xC235, 0x9A4A, 0xC236, 0x9A4B, 0xC237, 0x9A4C, 0xC238, 0x9A4D, 0xC239, 0x9A4E, 0xC23A, 0x9A4F, 0xC23B, 0x9A50,
+ 0xC23C, 0x9A51, 0xC23D, 0x9A52, 0xC23E, 0x9A53, 0xC23F, 0x9A54, 0xC240, 0x9A55, 0xC241, 0x9A56, 0xC242, 0x9A57, 0xC243, 0x9A58,
+ 0xC244, 0x9A59, 0xC245, 0x9A5A, 0xC246, 0x9A61, 0xC247, 0x9A62, 0xC248, 0xBDA5, 0xC249, 0x9A63, 0xC24A, 0x9A64, 0xC24B, 0x9A65,
+ 0xC24C, 0x9A66, 0xC24D, 0x9A67, 0xC24E, 0x9A68, 0xC24F, 0x9A69, 0xC250, 0xBDA6, 0xC251, 0xBDA7, 0xC252, 0x9A6A, 0xC253, 0x9A6B,
+ 0xC254, 0xBDA8, 0xC255, 0x9A6C, 0xC256, 0x9A6D, 0xC257, 0x9A6E, 0xC258, 0xBDA9, 0xC259, 0x9A6F, 0xC25A, 0x9A70, 0xC25B, 0x9A71,
+ 0xC25C, 0x9A72, 0xC25D, 0x9A73, 0xC25E, 0x9A74, 0xC25F, 0x9A75, 0xC260, 0xBDAA, 0xC261, 0x9A76, 0xC262, 0x9A77, 0xC263, 0x9A78,
+ 0xC264, 0x9A79, 0xC265, 0xBDAB, 0xC266, 0x9A7A, 0xC267, 0x9A81, 0xC268, 0x9A82, 0xC269, 0x9A83, 0xC26A, 0x9A84, 0xC26B, 0x9A85,
+ 0xC26C, 0xBDAC, 0xC26D, 0xBDAD, 0xC26E, 0x9A86, 0xC26F, 0x9A87, 0xC270, 0xBDAE, 0xC271, 0x9A88, 0xC272, 0x9A89, 0xC273, 0x9A8A,
+ 0xC274, 0xBDAF, 0xC275, 0x9A8B, 0xC276, 0x9A8C, 0xC277, 0x9A8D, 0xC278, 0x9A8E, 0xC279, 0x9A8F, 0xC27A, 0x9A90, 0xC27B, 0x9A91,
+ 0xC27C, 0xBDB0, 0xC27D, 0xBDB1, 0xC27E, 0x9A92, 0xC27F, 0xBDB2, 0xC280, 0x9A93, 0xC281, 0xBDB3, 0xC282, 0x9A94, 0xC283, 0x9A95,
+ 0xC284, 0x9A96, 0xC285, 0x9A97, 0xC286, 0x9A98, 0xC287, 0x9A99, 0xC288, 0xBDB4, 0xC289, 0xBDB5, 0xC28A, 0x9A9A, 0xC28B, 0x9A9B,
+ 0xC28C, 0x9A9C, 0xC28D, 0x9A9D, 0xC28E, 0x9A9E, 0xC28F, 0x9A9F, 0xC290, 0xBDB6, 0xC291, 0x9AA0, 0xC292, 0x9AA1, 0xC293, 0x9AA2,
+ 0xC294, 0x9AA3, 0xC295, 0x9AA4, 0xC296, 0x9AA5, 0xC297, 0x9AA6, 0xC298, 0xBDB7, 0xC299, 0x9AA7, 0xC29A, 0x9AA8, 0xC29B, 0xBDB8,
+ 0xC29C, 0x9AA9, 0xC29D, 0xBDB9, 0xC29E, 0x9AAA, 0xC29F, 0x9AAB, 0xC2A0, 0x9AAC, 0xC2A1, 0x9AAD, 0xC2A2, 0x9AAE, 0xC2A3, 0x9AAF,
+ 0xC2A4, 0xBDBA, 0xC2A5, 0xBDBB, 0xC2A6, 0x9AB0, 0xC2A7, 0x9AB1, 0xC2A8, 0xBDBC, 0xC2A9, 0x9AB2, 0xC2AA, 0x9AB3, 0xC2AB, 0x9AB4,
+ 0xC2AC, 0xBDBD, 0xC2AD, 0xBDBE, 0xC2AE, 0x9AB5, 0xC2AF, 0x9AB6, 0xC2B0, 0x9AB7, 0xC2B1, 0x9AB8, 0xC2B2, 0x9AB9, 0xC2B3, 0x9ABA,
+ 0xC2B4, 0xBDBF, 0xC2B5, 0xBDC0, 0xC2B6, 0x9ABB, 0xC2B7, 0xBDC1, 0xC2B8, 0x9ABC, 0xC2B9, 0xBDC2, 0xC2BA, 0x9ABD, 0xC2BB, 0x9ABE,
+ 0xC2BC, 0x9ABF, 0xC2BD, 0x9AC0, 0xC2BE, 0x9AC1, 0xC2BF, 0x9AC2, 0xC2C0, 0x9AC3, 0xC2C1, 0x9AC4, 0xC2C2, 0x9AC5, 0xC2C3, 0x9AC6,
+ 0xC2C4, 0x9AC7, 0xC2C5, 0x9AC8, 0xC2C6, 0x9AC9, 0xC2C7, 0x9ACA, 0xC2C8, 0x9ACB, 0xC2C9, 0x9ACC, 0xC2CA, 0x9ACD, 0xC2CB, 0x9ACE,
+ 0xC2CC, 0x9ACF, 0xC2CD, 0x9AD0, 0xC2CE, 0x9AD1, 0xC2CF, 0x9AD2, 0xC2D0, 0x9AD3, 0xC2D1, 0x9AD4, 0xC2D2, 0x9AD5, 0xC2D3, 0x9AD6,
+ 0xC2D4, 0x9AD7, 0xC2D5, 0x9AD8, 0xC2D6, 0x9AD9, 0xC2D7, 0x9ADA, 0xC2D8, 0x9ADB, 0xC2D9, 0x9ADC, 0xC2DA, 0x9ADD, 0xC2DB, 0x9ADE,
+ 0xC2DC, 0xBDC3, 0xC2DD, 0xBDC4, 0xC2DE, 0x9ADF, 0xC2DF, 0x9AE0, 0xC2E0, 0xBDC5, 0xC2E1, 0x9AE1, 0xC2E2, 0x9AE2, 0xC2E3, 0xBDC6,
+ 0xC2E4, 0xBDC7, 0xC2E5, 0x9AE3, 0xC2E6, 0x9AE4, 0xC2E7, 0x9AE5, 0xC2E8, 0x9AE6, 0xC2E9, 0x9AE7, 0xC2EA, 0x9AE8, 0xC2EB, 0xBDC8,
+ 0xC2EC, 0xBDC9, 0xC2ED, 0xBDCA, 0xC2EE, 0x9AE9, 0xC2EF, 0xBDCB, 0xC2F0, 0x9AEA, 0xC2F1, 0xBDCC, 0xC2F2, 0x9AEB, 0xC2F3, 0x9AEC,
+ 0xC2F4, 0x9AED, 0xC2F5, 0x9AEE, 0xC2F6, 0xBDCD, 0xC2F7, 0x9AEF, 0xC2F8, 0xBDCE, 0xC2F9, 0xBDCF, 0xC2FA, 0x9AF0, 0xC2FB, 0xBDD0,
+ 0xC2FC, 0xBDD1, 0xC2FD, 0x9AF1, 0xC2FE, 0x9AF2, 0xC2FF, 0x9AF3, 0xC300, 0xBDD2, 0xC301, 0x9AF4, 0xC302, 0x9AF5, 0xC303, 0x9AF6,
+ 0xC304, 0x9AF7, 0xC305, 0x9AF8, 0xC306, 0x9AF9, 0xC307, 0x9AFA, 0xC308, 0xBDD3, 0xC309, 0xBDD4, 0xC30A, 0x9AFB, 0xC30B, 0x9AFC,
+ 0xC30C, 0xBDD5, 0xC30D, 0xBDD6, 0xC30E, 0x9AFD, 0xC30F, 0x9AFE, 0xC310, 0x9B41, 0xC311, 0x9B42, 0xC312, 0x9B43, 0xC313, 0xBDD7,
+ 0xC314, 0xBDD8, 0xC315, 0xBDD9, 0xC316, 0x9B44, 0xC317, 0x9B45, 0xC318, 0xBDDA, 0xC319, 0x9B46, 0xC31A, 0x9B47, 0xC31B, 0x9B48,
+ 0xC31C, 0xBDDB, 0xC31D, 0x9B49, 0xC31E, 0x9B4A, 0xC31F, 0x9B4B, 0xC320, 0x9B4C, 0xC321, 0x9B4D, 0xC322, 0x9B4E, 0xC323, 0x9B4F,
+ 0xC324, 0xBDDC, 0xC325, 0xBDDD, 0xC326, 0x9B50, 0xC327, 0x9B51, 0xC328, 0xBDDE, 0xC329, 0xBDDF, 0xC32A, 0x9B52, 0xC32B, 0x9B53,
+ 0xC32C, 0x9B54, 0xC32D, 0x9B55, 0xC32E, 0x9B56, 0xC32F, 0x9B57, 0xC330, 0x9B58, 0xC331, 0x9B59, 0xC332, 0x9B5A, 0xC333, 0x9B61,
+ 0xC334, 0x9B62, 0xC335, 0x9B63, 0xC336, 0x9B64, 0xC337, 0x9B65, 0xC338, 0x9B66, 0xC339, 0x9B67, 0xC33A, 0x9B68, 0xC33B, 0x9B69,
+ 0xC33C, 0x9B6A, 0xC33D, 0x9B6B, 0xC33E, 0x9B6C, 0xC33F, 0x9B6D, 0xC340, 0x9B6E, 0xC341, 0x9B6F, 0xC342, 0x9B70, 0xC343, 0x9B71,
+ 0xC344, 0x9B72, 0xC345, 0xBDE0, 0xC346, 0x9B73, 0xC347, 0x9B74, 0xC348, 0x9B75, 0xC349, 0x9B76, 0xC34A, 0x9B77, 0xC34B, 0x9B78,
+ 0xC34C, 0x9B79, 0xC34D, 0x9B7A, 0xC34E, 0x9B81, 0xC34F, 0x9B82, 0xC350, 0x9B83, 0xC351, 0x9B84, 0xC352, 0x9B85, 0xC353, 0x9B86,
+ 0xC354, 0x9B87, 0xC355, 0x9B88, 0xC356, 0x9B89, 0xC357, 0x9B8A, 0xC358, 0x9B8B, 0xC359, 0x9B8C, 0xC35A, 0x9B8D, 0xC35B, 0x9B8E,
+ 0xC35C, 0x9B8F, 0xC35D, 0x9B90, 0xC35E, 0x9B91, 0xC35F, 0x9B92, 0xC360, 0x9B93, 0xC361, 0x9B94, 0xC362, 0x9B95, 0xC363, 0x9B96,
+ 0xC364, 0x9B97, 0xC365, 0x9B98, 0xC366, 0x9B99, 0xC367, 0x9B9A, 0xC368, 0xBDE1, 0xC369, 0xBDE2, 0xC36A, 0x9B9B, 0xC36B, 0x9B9C,
+ 0xC36C, 0xBDE3, 0xC36D, 0x9B9D, 0xC36E, 0x9B9E, 0xC36F, 0x9B9F, 0xC370, 0xBDE4, 0xC371, 0x9BA0, 0xC372, 0xBDE5, 0xC373, 0x9BA1,
+ 0xC374, 0x9BA2, 0xC375, 0x9BA3, 0xC376, 0x9BA4, 0xC377, 0x9BA5, 0xC378, 0xBDE6, 0xC379, 0xBDE7, 0xC37A, 0x9BA6, 0xC37B, 0x9BA7,
+ 0xC37C, 0xBDE8, 0xC37D, 0xBDE9, 0xC37E, 0x9BA8, 0xC37F, 0x9BA9, 0xC380, 0x9BAA, 0xC381, 0x9BAB, 0xC382, 0x9BAC, 0xC383, 0x9BAD,
+ 0xC384, 0xBDEA, 0xC385, 0x9BAE, 0xC386, 0x9BAF, 0xC387, 0x9BB0, 0xC388, 0xBDEB, 0xC389, 0x9BB1, 0xC38A, 0x9BB2, 0xC38B, 0x9BB3,
+ 0xC38C, 0xBDEC, 0xC38D, 0x9BB4, 0xC38E, 0x9BB5, 0xC38F, 0x9BB6, 0xC390, 0x9BB7, 0xC391, 0x9BB8, 0xC392, 0x9BB9, 0xC393, 0x9BBA,
+ 0xC394, 0x9BBB, 0xC395, 0x9BBC, 0xC396, 0x9BBD, 0xC397, 0x9BBE, 0xC398, 0x9BBF, 0xC399, 0x9BC0, 0xC39A, 0x9BC1, 0xC39B, 0x9BC2,
+ 0xC39C, 0x9BC3, 0xC39D, 0x9BC4, 0xC39E, 0x9BC5, 0xC39F, 0x9BC6, 0xC3A0, 0x9BC7, 0xC3A1, 0x9BC8, 0xC3A2, 0x9BC9, 0xC3A3, 0x9BCA,
+ 0xC3A4, 0x9BCB, 0xC3A5, 0x9BCC, 0xC3A6, 0x9BCD, 0xC3A7, 0x9BCE, 0xC3A8, 0x9BCF, 0xC3A9, 0x9BD0, 0xC3AA, 0x9BD1, 0xC3AB, 0x9BD2,
+ 0xC3AC, 0x9BD3, 0xC3AD, 0x9BD4, 0xC3AE, 0x9BD5, 0xC3AF, 0x9BD6, 0xC3B0, 0x9BD7, 0xC3B1, 0x9BD8, 0xC3B2, 0x9BD9, 0xC3B3, 0x9BDA,
+ 0xC3B4, 0x9BDB, 0xC3B5, 0x9BDC, 0xC3B6, 0x9BDD, 0xC3B7, 0x9BDE, 0xC3B8, 0x9BDF, 0xC3B9, 0x9BE0, 0xC3BA, 0x9BE1, 0xC3BB, 0x9BE2,
+ 0xC3BC, 0x9BE3, 0xC3BD, 0x9BE4, 0xC3BE, 0x9BE5, 0xC3BF, 0x9BE6, 0xC3C0, 0xBDED, 0xC3C1, 0x9BE7, 0xC3C2, 0x9BE8, 0xC3C3, 0x9BE9,
+ 0xC3C4, 0x9BEA, 0xC3C5, 0x9BEB, 0xC3C6, 0x9BEC, 0xC3C7, 0x9BED, 0xC3C8, 0x9BEE, 0xC3C9, 0x9BEF, 0xC3CA, 0x9BF0, 0xC3CB, 0x9BF1,
+ 0xC3CC, 0x9BF2, 0xC3CD, 0x9BF3, 0xC3CE, 0x9BF4, 0xC3CF, 0x9BF5, 0xC3D0, 0x9BF6, 0xC3D1, 0x9BF7, 0xC3D2, 0x9BF8, 0xC3D3, 0x9BF9,
+ 0xC3D4, 0x9BFA, 0xC3D5, 0x9BFB, 0xC3D6, 0x9BFC, 0xC3D7, 0x9BFD, 0xC3D8, 0xBDEE, 0xC3D9, 0xBDEF, 0xC3DA, 0x9BFE, 0xC3DB, 0x9C41,
+ 0xC3DC, 0xBDF0, 0xC3DD, 0x9C42, 0xC3DE, 0x9C43, 0xC3DF, 0xBDF1, 0xC3E0, 0xBDF2, 0xC3E1, 0x9C44, 0xC3E2, 0xBDF3, 0xC3E3, 0x9C45,
+ 0xC3E4, 0x9C46, 0xC3E5, 0x9C47, 0xC3E6, 0x9C48, 0xC3E7, 0x9C49, 0xC3E8, 0xBDF4, 0xC3E9, 0xBDF5, 0xC3EA, 0x9C4A, 0xC3EB, 0x9C4B,
+ 0xC3EC, 0x9C4C, 0xC3ED, 0xBDF6, 0xC3EE, 0x9C4D, 0xC3EF, 0x9C4E, 0xC3F0, 0x9C4F, 0xC3F1, 0x9C50, 0xC3F2, 0x9C51, 0xC3F3, 0x9C52,
+ 0xC3F4, 0xBDF7, 0xC3F5, 0xBDF8, 0xC3F6, 0x9C53, 0xC3F7, 0x9C54, 0xC3F8, 0xBDF9, 0xC3F9, 0x9C55, 0xC3FA, 0x9C56, 0xC3FB, 0x9C57,
+ 0xC3FC, 0x9C58, 0xC3FD, 0x9C59, 0xC3FE, 0x9C5A, 0xC3FF, 0x9C61, 0xC400, 0x9C62, 0xC401, 0x9C63, 0xC402, 0x9C64, 0xC403, 0x9C65,
+ 0xC404, 0x9C66, 0xC405, 0x9C67, 0xC406, 0x9C68, 0xC407, 0x9C69, 0xC408, 0xBDFA, 0xC409, 0x9C6A, 0xC40A, 0x9C6B, 0xC40B, 0x9C6C,
+ 0xC40C, 0x9C6D, 0xC40D, 0x9C6E, 0xC40E, 0x9C6F, 0xC40F, 0x9C70, 0xC410, 0xBDFB, 0xC411, 0x9C71, 0xC412, 0x9C72, 0xC413, 0x9C73,
+ 0xC414, 0x9C74, 0xC415, 0x9C75, 0xC416, 0x9C76, 0xC417, 0x9C77, 0xC418, 0x9C78, 0xC419, 0x9C79, 0xC41A, 0x9C7A, 0xC41B, 0x9C81,
+ 0xC41C, 0x9C82, 0xC41D, 0x9C83, 0xC41E, 0x9C84, 0xC41F, 0x9C85, 0xC420, 0x9C86, 0xC421, 0x9C87, 0xC422, 0x9C88, 0xC423, 0x9C89,
+ 0xC424, 0xBDFC, 0xC425, 0x9C8A, 0xC426, 0x9C8B, 0xC427, 0x9C8C, 0xC428, 0x9C8D, 0xC429, 0x9C8E, 0xC42A, 0x9C8F, 0xC42B, 0x9C90,
+ 0xC42C, 0xBDFD, 0xC42D, 0x9C91, 0xC42E, 0x9C92, 0xC42F, 0x9C93, 0xC430, 0xBDFE, 0xC431, 0x9C94, 0xC432, 0x9C95, 0xC433, 0x9C96,
+ 0xC434, 0xBEA1, 0xC435, 0x9C97, 0xC436, 0x9C98, 0xC437, 0x9C99, 0xC438, 0x9C9A, 0xC439, 0x9C9B, 0xC43A, 0x9C9C, 0xC43B, 0x9C9D,
+ 0xC43C, 0xBEA2, 0xC43D, 0xBEA3, 0xC43E, 0x9C9E, 0xC43F, 0x9C9F, 0xC440, 0x9CA0, 0xC441, 0x9CA1, 0xC442, 0x9CA2, 0xC443, 0x9CA3,
+ 0xC444, 0x9CA4, 0xC445, 0x9CA5, 0xC446, 0x9CA6, 0xC447, 0x9CA7, 0xC448, 0xBEA4, 0xC449, 0x9CA8, 0xC44A, 0x9CA9, 0xC44B, 0x9CAA,
+ 0xC44C, 0x9CAB, 0xC44D, 0x9CAC, 0xC44E, 0x9CAD, 0xC44F, 0x9CAE, 0xC450, 0x9CAF, 0xC451, 0x9CB0, 0xC452, 0x9CB1, 0xC453, 0x9CB2,
+ 0xC454, 0x9CB3, 0xC455, 0x9CB4, 0xC456, 0x9CB5, 0xC457, 0x9CB6, 0xC458, 0x9CB7, 0xC459, 0x9CB8, 0xC45A, 0x9CB9, 0xC45B, 0x9CBA,
+ 0xC45C, 0x9CBB, 0xC45D, 0x9CBC, 0xC45E, 0x9CBD, 0xC45F, 0x9CBE, 0xC460, 0x9CBF, 0xC461, 0x9CC0, 0xC462, 0x9CC1, 0xC463, 0x9CC2,
+ 0xC464, 0xBEA5, 0xC465, 0xBEA6, 0xC466, 0x9CC3, 0xC467, 0x9CC4, 0xC468, 0xBEA7, 0xC469, 0x9CC5, 0xC46A, 0x9CC6, 0xC46B, 0x9CC7,
+ 0xC46C, 0xBEA8, 0xC46D, 0x9CC8, 0xC46E, 0x9CC9, 0xC46F, 0x9CCA, 0xC470, 0x9CCB, 0xC471, 0x9CCC, 0xC472, 0x9CCD, 0xC473, 0x9CCE,
+ 0xC474, 0xBEA9, 0xC475, 0xBEAA, 0xC476, 0x9CCF, 0xC477, 0x9CD0, 0xC478, 0x9CD1, 0xC479, 0xBEAB, 0xC47A, 0x9CD2, 0xC47B, 0x9CD3,
+ 0xC47C, 0x9CD4, 0xC47D, 0x9CD5, 0xC47E, 0x9CD6, 0xC47F, 0x9CD7, 0xC480, 0xBEAC, 0xC481, 0x9CD8, 0xC482, 0x9CD9, 0xC483, 0x9CDA,
+ 0xC484, 0x9CDB, 0xC485, 0x9CDC, 0xC486, 0x9CDD, 0xC487, 0x9CDE, 0xC488, 0x9CDF, 0xC489, 0x9CE0, 0xC48A, 0x9CE1, 0xC48B, 0x9CE2,
+ 0xC48C, 0x9CE3, 0xC48D, 0x9CE4, 0xC48E, 0x9CE5, 0xC48F, 0x9CE6, 0xC490, 0x9CE7, 0xC491, 0x9CE8, 0xC492, 0x9CE9, 0xC493, 0x9CEA,
+ 0xC494, 0xBEAD, 0xC495, 0x9CEB, 0xC496, 0x9CEC, 0xC497, 0x9CED, 0xC498, 0x9CEE, 0xC499, 0x9CEF, 0xC49A, 0x9CF0, 0xC49B, 0x9CF1,
+ 0xC49C, 0xBEAE, 0xC49D, 0x9CF2, 0xC49E, 0x9CF3, 0xC49F, 0x9CF4, 0xC4A0, 0x9CF5, 0xC4A1, 0x9CF6, 0xC4A2, 0x9CF7, 0xC4A3, 0x9CF8,
+ 0xC4A4, 0x9CF9, 0xC4A5, 0x9CFA, 0xC4A6, 0x9CFB, 0xC4A7, 0x9CFC, 0xC4A8, 0x9CFD, 0xC4A9, 0x9CFE, 0xC4AA, 0x9D41, 0xC4AB, 0x9D42,
+ 0xC4AC, 0x9D43, 0xC4AD, 0x9D44, 0xC4AE, 0x9D45, 0xC4AF, 0x9D46, 0xC4B0, 0x9D47, 0xC4B1, 0x9D48, 0xC4B2, 0x9D49, 0xC4B3, 0x9D4A,
+ 0xC4B4, 0x9D4B, 0xC4B5, 0x9D4C, 0xC4B6, 0x9D4D, 0xC4B7, 0x9D4E, 0xC4B8, 0xBEAF, 0xC4B9, 0x9D4F, 0xC4BA, 0x9D50, 0xC4BB, 0x9D51,
+ 0xC4BC, 0xBEB0, 0xC4BD, 0x9D52, 0xC4BE, 0x9D53, 0xC4BF, 0x9D54, 0xC4C0, 0x9D55, 0xC4C1, 0x9D56, 0xC4C2, 0x9D57, 0xC4C3, 0x9D58,
+ 0xC4C4, 0x9D59, 0xC4C5, 0x9D5A, 0xC4C6, 0x9D61, 0xC4C7, 0x9D62, 0xC4C8, 0x9D63, 0xC4C9, 0x9D64, 0xC4CA, 0x9D65, 0xC4CB, 0x9D66,
+ 0xC4CC, 0x9D67, 0xC4CD, 0x9D68, 0xC4CE, 0x9D69, 0xC4CF, 0x9D6A, 0xC4D0, 0x9D6B, 0xC4D1, 0x9D6C, 0xC4D2, 0x9D6D, 0xC4D3, 0x9D6E,
+ 0xC4D4, 0x9D6F, 0xC4D5, 0x9D70, 0xC4D6, 0x9D71, 0xC4D7, 0x9D72, 0xC4D8, 0x9D73, 0xC4D9, 0x9D74, 0xC4DA, 0x9D75, 0xC4DB, 0x9D76,
+ 0xC4DC, 0x9D77, 0xC4DD, 0x9D78, 0xC4DE, 0x9D79, 0xC4DF, 0x9D7A, 0xC4E0, 0x9D81, 0xC4E1, 0x9D82, 0xC4E2, 0x9D83, 0xC4E3, 0x9D84,
+ 0xC4E4, 0x9D85, 0xC4E5, 0x9D86, 0xC4E6, 0x9D87, 0xC4E7, 0x9D88, 0xC4E8, 0x9D89, 0xC4E9, 0xBEB1, 0xC4EA, 0x9D8A, 0xC4EB, 0x9D8B,
+ 0xC4EC, 0x9D8C, 0xC4ED, 0x9D8D, 0xC4EE, 0x9D8E, 0xC4EF, 0x9D8F, 0xC4F0, 0xBEB2, 0xC4F1, 0xBEB3, 0xC4F2, 0x9D90, 0xC4F3, 0x9D91,
+ 0xC4F4, 0xBEB4, 0xC4F5, 0x9D92, 0xC4F6, 0x9D93, 0xC4F7, 0x9D94, 0xC4F8, 0xBEB5, 0xC4F9, 0x9D95, 0xC4FA, 0xBEB6, 0xC4FB, 0x9D96,
+ 0xC4FC, 0x9D97, 0xC4FD, 0x9D98, 0xC4FE, 0x9D99, 0xC4FF, 0xBEB7, 0xC500, 0xBEB8, 0xC501, 0xBEB9, 0xC502, 0x9D9A, 0xC503, 0x9D9B,
+ 0xC504, 0x9D9C, 0xC505, 0x9D9D, 0xC506, 0x9D9E, 0xC507, 0x9D9F, 0xC508, 0x9DA0, 0xC509, 0x9DA1, 0xC50A, 0x9DA2, 0xC50B, 0x9DA3,
+ 0xC50C, 0xBEBA, 0xC50D, 0x9DA4, 0xC50E, 0x9DA5, 0xC50F, 0x9DA6, 0xC510, 0xBEBB, 0xC511, 0x9DA7, 0xC512, 0x9DA8, 0xC513, 0x9DA9,
+ 0xC514, 0xBEBC, 0xC515, 0x9DAA, 0xC516, 0x9DAB, 0xC517, 0x9DAC, 0xC518, 0x9DAD, 0xC519, 0x9DAE, 0xC51A, 0x9DAF, 0xC51B, 0x9DB0,
+ 0xC51C, 0xBEBD, 0xC51D, 0x9DB1, 0xC51E, 0x9DB2, 0xC51F, 0x9DB3, 0xC520, 0x9DB4, 0xC521, 0x9DB5, 0xC522, 0x9DB6, 0xC523, 0x9DB7,
+ 0xC524, 0x9DB8, 0xC525, 0x9DB9, 0xC526, 0x9DBA, 0xC527, 0x9DBB, 0xC528, 0xBEBE, 0xC529, 0xBEBF, 0xC52A, 0x9DBC, 0xC52B, 0x9DBD,
+ 0xC52C, 0xBEC0, 0xC52D, 0x9DBE, 0xC52E, 0x9DBF, 0xC52F, 0x9DC0, 0xC530, 0xBEC1, 0xC531, 0x9DC1, 0xC532, 0x9DC2, 0xC533, 0x9DC3,
+ 0xC534, 0x9DC4, 0xC535, 0x9DC5, 0xC536, 0x9DC6, 0xC537, 0x9DC7, 0xC538, 0xBEC2, 0xC539, 0xBEC3, 0xC53A, 0x9DC8, 0xC53B, 0xBEC4,
+ 0xC53C, 0x9DC9, 0xC53D, 0xBEC5, 0xC53E, 0x9DCA, 0xC53F, 0x9DCB, 0xC540, 0x9DCC, 0xC541, 0x9DCD, 0xC542, 0x9DCE, 0xC543, 0x9DCF,
+ 0xC544, 0xBEC6, 0xC545, 0xBEC7, 0xC546, 0x9DD0, 0xC547, 0x9DD1, 0xC548, 0xBEC8, 0xC549, 0xBEC9, 0xC54A, 0xBECA, 0xC54B, 0x9DD2,
+ 0xC54C, 0xBECB, 0xC54D, 0xBECC, 0xC54E, 0xBECD, 0xC54F, 0x9DD3, 0xC550, 0x9DD4, 0xC551, 0x9DD5, 0xC552, 0x9DD6, 0xC553, 0xBECE,
+ 0xC554, 0xBECF, 0xC555, 0xBED0, 0xC556, 0x9DD7, 0xC557, 0xBED1, 0xC558, 0xBED2, 0xC559, 0xBED3, 0xC55A, 0x9DD8, 0xC55B, 0x9DD9,
+ 0xC55C, 0x9DDA, 0xC55D, 0xBED4, 0xC55E, 0xBED5, 0xC55F, 0x9DDB, 0xC560, 0xBED6, 0xC561, 0xBED7, 0xC562, 0x9DDC, 0xC563, 0x9DDD,
+ 0xC564, 0xBED8, 0xC565, 0x9DDE, 0xC566, 0x9DDF, 0xC567, 0x9DE0, 0xC568, 0xBED9, 0xC569, 0x9DE1, 0xC56A, 0x9DE2, 0xC56B, 0x9DE3,
+ 0xC56C, 0x9DE4, 0xC56D, 0x9DE5, 0xC56E, 0x9DE6, 0xC56F, 0x9DE7, 0xC570, 0xBEDA, 0xC571, 0xBEDB, 0xC572, 0x9DE8, 0xC573, 0xBEDC,
+ 0xC574, 0xBEDD, 0xC575, 0xBEDE, 0xC576, 0x9DE9, 0xC577, 0x9DEA, 0xC578, 0x9DEB, 0xC579, 0x9DEC, 0xC57A, 0x9DED, 0xC57B, 0x9DEE,
+ 0xC57C, 0xBEDF, 0xC57D, 0xBEE0, 0xC57E, 0x9DEF, 0xC57F, 0x9DF0, 0xC580, 0xBEE1, 0xC581, 0x9DF1, 0xC582, 0x9DF2, 0xC583, 0x9DF3,
+ 0xC584, 0xBEE2, 0xC585, 0x9DF4, 0xC586, 0x9DF5, 0xC587, 0xBEE3, 0xC588, 0x9DF6, 0xC589, 0x9DF7, 0xC58A, 0x9DF8, 0xC58B, 0x9DF9,
+ 0xC58C, 0xBEE4, 0xC58D, 0xBEE5, 0xC58E, 0x9DFA, 0xC58F, 0xBEE6, 0xC590, 0x9DFB, 0xC591, 0xBEE7, 0xC592, 0x9DFC, 0xC593, 0x9DFD,
+ 0xC594, 0x9DFE, 0xC595, 0xBEE8, 0xC596, 0x9E41, 0xC597, 0xBEE9, 0xC598, 0xBEEA, 0xC599, 0x9E42, 0xC59A, 0x9E43, 0xC59B, 0x9E44,
+ 0xC59C, 0xBEEB, 0xC59D, 0x9E45, 0xC59E, 0x9E46, 0xC59F, 0x9E47, 0xC5A0, 0xBEEC, 0xC5A1, 0x9E48, 0xC5A2, 0x9E49, 0xC5A3, 0x9E4A,
+ 0xC5A4, 0x9E4B, 0xC5A5, 0x9E4C, 0xC5A6, 0x9E4D, 0xC5A7, 0x9E4E, 0xC5A8, 0x9E4F, 0xC5A9, 0xBEED, 0xC5AA, 0x9E50, 0xC5AB, 0x9E51,
+ 0xC5AC, 0x9E52, 0xC5AD, 0x9E53, 0xC5AE, 0x9E54, 0xC5AF, 0x9E55, 0xC5B0, 0x9E56, 0xC5B1, 0x9E57, 0xC5B2, 0x9E58, 0xC5B3, 0x9E59,
+ 0xC5B4, 0xBEEE, 0xC5B5, 0xBEEF, 0xC5B6, 0x9E5A, 0xC5B7, 0x9E61, 0xC5B8, 0xBEF0, 0xC5B9, 0xBEF1, 0xC5BA, 0x9E62, 0xC5BB, 0xBEF2,
+ 0xC5BC, 0xBEF3, 0xC5BD, 0xBEF4, 0xC5BE, 0xBEF5, 0xC5BF, 0x9E63, 0xC5C0, 0x9E64, 0xC5C1, 0x9E65, 0xC5C2, 0x9E66, 0xC5C3, 0x9E67,
+ 0xC5C4, 0xBEF6, 0xC5C5, 0xBEF7, 0xC5C6, 0xBEF8, 0xC5C7, 0xBEF9, 0xC5C8, 0xBEFA, 0xC5C9, 0xBEFB, 0xC5CA, 0xBEFC, 0xC5CB, 0x9E68,
+ 0xC5CC, 0xBEFD, 0xC5CD, 0x9E69, 0xC5CE, 0xBEFE, 0xC5CF, 0x9E6A, 0xC5D0, 0xBFA1, 0xC5D1, 0xBFA2, 0xC5D2, 0x9E6B, 0xC5D3, 0x9E6C,
+ 0xC5D4, 0xBFA3, 0xC5D5, 0x9E6D, 0xC5D6, 0x9E6E, 0xC5D7, 0x9E6F, 0xC5D8, 0xBFA4, 0xC5D9, 0x9E70, 0xC5DA, 0x9E71, 0xC5DB, 0x9E72,
+ 0xC5DC, 0x9E73, 0xC5DD, 0x9E74, 0xC5DE, 0x9E75, 0xC5DF, 0x9E76, 0xC5E0, 0xBFA5, 0xC5E1, 0xBFA6, 0xC5E2, 0x9E77, 0xC5E3, 0xBFA7,
+ 0xC5E4, 0x9E78, 0xC5E5, 0xBFA8, 0xC5E6, 0x9E79, 0xC5E7, 0x9E7A, 0xC5E8, 0x9E81, 0xC5E9, 0x9E82, 0xC5EA, 0x9E83, 0xC5EB, 0x9E84,
+ 0xC5EC, 0xBFA9, 0xC5ED, 0xBFAA, 0xC5EE, 0xBFAB, 0xC5EF, 0x9E85, 0xC5F0, 0xBFAC, 0xC5F1, 0x9E86, 0xC5F2, 0x9E87, 0xC5F3, 0x9E88,
+ 0xC5F4, 0xBFAD, 0xC5F5, 0x9E89, 0xC5F6, 0xBFAE, 0xC5F7, 0xBFAF, 0xC5F8, 0x9E8A, 0xC5F9, 0x9E8B, 0xC5FA, 0x9E8C, 0xC5FB, 0x9E8D,
+ 0xC5FC, 0xBFB0, 0xC5FD, 0xBFB1, 0xC5FE, 0xBFB2, 0xC5FF, 0xBFB3, 0xC600, 0xBFB4, 0xC601, 0xBFB5, 0xC602, 0x9E8E, 0xC603, 0x9E8F,
+ 0xC604, 0x9E90, 0xC605, 0xBFB6, 0xC606, 0xBFB7, 0xC607, 0xBFB8, 0xC608, 0xBFB9, 0xC609, 0x9E91, 0xC60A, 0x9E92, 0xC60B, 0x9E93,
+ 0xC60C, 0xBFBA, 0xC60D, 0x9E94, 0xC60E, 0x9E95, 0xC60F, 0x9E96, 0xC610, 0xBFBB, 0xC611, 0x9E97, 0xC612, 0x9E98, 0xC613, 0x9E99,
+ 0xC614, 0x9E9A, 0xC615, 0x9E9B, 0xC616, 0x9E9C, 0xC617, 0x9E9D, 0xC618, 0xBFBC, 0xC619, 0xBFBD, 0xC61A, 0x9E9E, 0xC61B, 0xBFBE,
+ 0xC61C, 0xBFBF, 0xC61D, 0x9E9F, 0xC61E, 0x9EA0, 0xC61F, 0x9EA1, 0xC620, 0x9EA2, 0xC621, 0x9EA3, 0xC622, 0x9EA4, 0xC623, 0x9EA5,
+ 0xC624, 0xBFC0, 0xC625, 0xBFC1, 0xC626, 0x9EA6, 0xC627, 0x9EA7, 0xC628, 0xBFC2, 0xC629, 0x9EA8, 0xC62A, 0x9EA9, 0xC62B, 0x9EAA,
+ 0xC62C, 0xBFC3, 0xC62D, 0xBFC4, 0xC62E, 0xBFC5, 0xC62F, 0x9EAB, 0xC630, 0xBFC6, 0xC631, 0x9EAC, 0xC632, 0x9EAD, 0xC633, 0xBFC7,
+ 0xC634, 0xBFC8, 0xC635, 0xBFC9, 0xC636, 0x9EAE, 0xC637, 0xBFCA, 0xC638, 0x9EAF, 0xC639, 0xBFCB, 0xC63A, 0x9EB0, 0xC63B, 0xBFCC,
+ 0xC63C, 0x9EB1, 0xC63D, 0x9EB2, 0xC63E, 0x9EB3, 0xC63F, 0x9EB4, 0xC640, 0xBFCD, 0xC641, 0xBFCE, 0xC642, 0x9EB5, 0xC643, 0x9EB6,
+ 0xC644, 0xBFCF, 0xC645, 0x9EB7, 0xC646, 0x9EB8, 0xC647, 0x9EB9, 0xC648, 0xBFD0, 0xC649, 0x9EBA, 0xC64A, 0x9EBB, 0xC64B, 0x9EBC,
+ 0xC64C, 0x9EBD, 0xC64D, 0x9EBE, 0xC64E, 0x9EBF, 0xC64F, 0x9EC0, 0xC650, 0xBFD1, 0xC651, 0xBFD2, 0xC652, 0x9EC1, 0xC653, 0xBFD3,
+ 0xC654, 0xBFD4, 0xC655, 0xBFD5, 0xC656, 0x9EC2, 0xC657, 0x9EC3, 0xC658, 0x9EC4, 0xC659, 0x9EC5, 0xC65A, 0x9EC6, 0xC65B, 0x9EC7,
+ 0xC65C, 0xBFD6, 0xC65D, 0xBFD7, 0xC65E, 0x9EC8, 0xC65F, 0x9EC9, 0xC660, 0xBFD8, 0xC661, 0x9ECA, 0xC662, 0x9ECB, 0xC663, 0x9ECC,
+ 0xC664, 0x9ECD, 0xC665, 0x9ECE, 0xC666, 0x9ECF, 0xC667, 0x9ED0, 0xC668, 0x9ED1, 0xC669, 0x9ED2, 0xC66A, 0x9ED3, 0xC66B, 0x9ED4,
+ 0xC66C, 0xBFD9, 0xC66D, 0x9ED5, 0xC66E, 0x9ED6, 0xC66F, 0xBFDA, 0xC670, 0x9ED7, 0xC671, 0xBFDB, 0xC672, 0x9ED8, 0xC673, 0x9ED9,
+ 0xC674, 0x9EDA, 0xC675, 0x9EDB, 0xC676, 0x9EDC, 0xC677, 0x9EDD, 0xC678, 0xBFDC, 0xC679, 0xBFDD, 0xC67A, 0x9EDE, 0xC67B, 0x9EDF,
+ 0xC67C, 0xBFDE, 0xC67D, 0x9EE0, 0xC67E, 0x9EE1, 0xC67F, 0x9EE2, 0xC680, 0xBFDF, 0xC681, 0x9EE3, 0xC682, 0x9EE4, 0xC683, 0x9EE5,
+ 0xC684, 0x9EE6, 0xC685, 0x9EE7, 0xC686, 0x9EE8, 0xC687, 0x9EE9, 0xC688, 0xBFE0, 0xC689, 0xBFE1, 0xC68A, 0x9EEA, 0xC68B, 0xBFE2,
+ 0xC68C, 0x9EEB, 0xC68D, 0xBFE3, 0xC68E, 0x9EEC, 0xC68F, 0x9EED, 0xC690, 0x9EEE, 0xC691, 0x9EEF, 0xC692, 0x9EF0, 0xC693, 0x9EF1,
+ 0xC694, 0xBFE4, 0xC695, 0xBFE5, 0xC696, 0x9EF2, 0xC697, 0x9EF3, 0xC698, 0xBFE6, 0xC699, 0x9EF4, 0xC69A, 0x9EF5, 0xC69B, 0x9EF6,
+ 0xC69C, 0xBFE7, 0xC69D, 0x9EF7, 0xC69E, 0x9EF8, 0xC69F, 0x9EF9, 0xC6A0, 0x9EFA, 0xC6A1, 0x9EFB, 0xC6A2, 0x9EFC, 0xC6A3, 0x9EFD,
+ 0xC6A4, 0xBFE8, 0xC6A5, 0xBFE9, 0xC6A6, 0x9EFE, 0xC6A7, 0xBFEA, 0xC6A8, 0x9F41, 0xC6A9, 0xBFEB, 0xC6AA, 0x9F42, 0xC6AB, 0x9F43,
+ 0xC6AC, 0x9F44, 0xC6AD, 0x9F45, 0xC6AE, 0x9F46, 0xC6AF, 0x9F47, 0xC6B0, 0xBFEC, 0xC6B1, 0xBFED, 0xC6B2, 0x9F48, 0xC6B3, 0x9F49,
+ 0xC6B4, 0xBFEE, 0xC6B5, 0x9F4A, 0xC6B6, 0x9F4B, 0xC6B7, 0x9F4C, 0xC6B8, 0xBFEF, 0xC6B9, 0xBFF0, 0xC6BA, 0xBFF1, 0xC6BB, 0x9F4D,
+ 0xC6BC, 0x9F4E, 0xC6BD, 0x9F4F, 0xC6BE, 0x9F50, 0xC6BF, 0x9F51, 0xC6C0, 0xBFF2, 0xC6C1, 0xBFF3, 0xC6C2, 0x9F52, 0xC6C3, 0xBFF4,
+ 0xC6C4, 0x9F53, 0xC6C5, 0xBFF5, 0xC6C6, 0x9F54, 0xC6C7, 0x9F55, 0xC6C8, 0x9F56, 0xC6C9, 0x9F57, 0xC6CA, 0x9F58, 0xC6CB, 0x9F59,
+ 0xC6CC, 0xBFF6, 0xC6CD, 0xBFF7, 0xC6CE, 0x9F5A, 0xC6CF, 0x9F61, 0xC6D0, 0xBFF8, 0xC6D1, 0x9F62, 0xC6D2, 0x9F63, 0xC6D3, 0x9F64,
+ 0xC6D4, 0xBFF9, 0xC6D5, 0x9F65, 0xC6D6, 0x9F66, 0xC6D7, 0x9F67, 0xC6D8, 0x9F68, 0xC6D9, 0x9F69, 0xC6DA, 0x9F6A, 0xC6DB, 0x9F6B,
+ 0xC6DC, 0xBFFA, 0xC6DD, 0xBFFB, 0xC6DE, 0x9F6C, 0xC6DF, 0x9F6D, 0xC6E0, 0xBFFC, 0xC6E1, 0xBFFD, 0xC6E2, 0x9F6E, 0xC6E3, 0x9F6F,
+ 0xC6E4, 0x9F70, 0xC6E5, 0x9F71, 0xC6E6, 0x9F72, 0xC6E7, 0x9F73, 0xC6E8, 0xBFFE, 0xC6E9, 0xC0A1, 0xC6EA, 0x9F74, 0xC6EB, 0x9F75,
+ 0xC6EC, 0xC0A2, 0xC6ED, 0x9F76, 0xC6EE, 0x9F77, 0xC6EF, 0x9F78, 0xC6F0, 0xC0A3, 0xC6F1, 0x9F79, 0xC6F2, 0x9F7A, 0xC6F3, 0x9F81,
+ 0xC6F4, 0x9F82, 0xC6F5, 0x9F83, 0xC6F6, 0x9F84, 0xC6F7, 0x9F85, 0xC6F8, 0xC0A4, 0xC6F9, 0xC0A5, 0xC6FA, 0x9F86, 0xC6FB, 0x9F87,
+ 0xC6FC, 0x9F88, 0xC6FD, 0xC0A6, 0xC6FE, 0x9F89, 0xC6FF, 0x9F8A, 0xC700, 0x9F8B, 0xC701, 0x9F8C, 0xC702, 0x9F8D, 0xC703, 0x9F8E,
+ 0xC704, 0xC0A7, 0xC705, 0xC0A8, 0xC706, 0x9F8F, 0xC707, 0x9F90, 0xC708, 0xC0A9, 0xC709, 0x9F91, 0xC70A, 0x9F92, 0xC70B, 0x9F93,
+ 0xC70C, 0xC0AA, 0xC70D, 0x9F94, 0xC70E, 0x9F95, 0xC70F, 0x9F96, 0xC710, 0x9F97, 0xC711, 0x9F98, 0xC712, 0x9F99, 0xC713, 0x9F9A,
+ 0xC714, 0xC0AB, 0xC715, 0xC0AC, 0xC716, 0x9F9B, 0xC717, 0xC0AD, 0xC718, 0x9F9C, 0xC719, 0xC0AE, 0xC71A, 0x9F9D, 0xC71B, 0x9F9E,
+ 0xC71C, 0x9F9F, 0xC71D, 0x9FA0, 0xC71E, 0x9FA1, 0xC71F, 0x9FA2, 0xC720, 0xC0AF, 0xC721, 0xC0B0, 0xC722, 0x9FA3, 0xC723, 0x9FA4,
+ 0xC724, 0xC0B1, 0xC725, 0x9FA5, 0xC726, 0x9FA6, 0xC727, 0x9FA7, 0xC728, 0xC0B2, 0xC729, 0x9FA8, 0xC72A, 0x9FA9, 0xC72B, 0x9FAA,
+ 0xC72C, 0x9FAB, 0xC72D, 0x9FAC, 0xC72E, 0x9FAD, 0xC72F, 0x9FAE, 0xC730, 0xC0B3, 0xC731, 0xC0B4, 0xC732, 0x9FAF, 0xC733, 0xC0B5,
+ 0xC734, 0x9FB0, 0xC735, 0xC0B6, 0xC736, 0x9FB1, 0xC737, 0xC0B7, 0xC738, 0x9FB2, 0xC739, 0x9FB3, 0xC73A, 0x9FB4, 0xC73B, 0x9FB5,
+ 0xC73C, 0xC0B8, 0xC73D, 0xC0B9, 0xC73E, 0x9FB6, 0xC73F, 0x9FB7, 0xC740, 0xC0BA, 0xC741, 0x9FB8, 0xC742, 0x9FB9, 0xC743, 0x9FBA,
+ 0xC744, 0xC0BB, 0xC745, 0x9FBB, 0xC746, 0x9FBC, 0xC747, 0x9FBD, 0xC748, 0x9FBE, 0xC749, 0x9FBF, 0xC74A, 0xC0BC, 0xC74B, 0x9FC0,
+ 0xC74C, 0xC0BD, 0xC74D, 0xC0BE, 0xC74E, 0x9FC1, 0xC74F, 0xC0BF, 0xC750, 0x9FC2, 0xC751, 0xC0C0, 0xC752, 0xC0C1, 0xC753, 0xC0C2,
+ 0xC754, 0xC0C3, 0xC755, 0xC0C4, 0xC756, 0xC0C5, 0xC757, 0xC0C6, 0xC758, 0xC0C7, 0xC759, 0x9FC3, 0xC75A, 0x9FC4, 0xC75B, 0x9FC5,
+ 0xC75C, 0xC0C8, 0xC75D, 0x9FC6, 0xC75E, 0x9FC7, 0xC75F, 0x9FC8, 0xC760, 0xC0C9, 0xC761, 0x9FC9, 0xC762, 0x9FCA, 0xC763, 0x9FCB,
+ 0xC764, 0x9FCC, 0xC765, 0x9FCD, 0xC766, 0x9FCE, 0xC767, 0x9FCF, 0xC768, 0xC0CA, 0xC769, 0x9FD0, 0xC76A, 0x9FD1, 0xC76B, 0xC0CB,
+ 0xC76C, 0x9FD2, 0xC76D, 0x9FD3, 0xC76E, 0x9FD4, 0xC76F, 0x9FD5, 0xC770, 0x9FD6, 0xC771, 0x9FD7, 0xC772, 0x9FD8, 0xC773, 0x9FD9,
+ 0xC774, 0xC0CC, 0xC775, 0xC0CD, 0xC776, 0x9FDA, 0xC777, 0x9FDB, 0xC778, 0xC0CE, 0xC779, 0x9FDC, 0xC77A, 0x9FDD, 0xC77B, 0x9FDE,
+ 0xC77C, 0xC0CF, 0xC77D, 0xC0D0, 0xC77E, 0xC0D1, 0xC77F, 0x9FDF, 0xC780, 0x9FE0, 0xC781, 0x9FE1, 0xC782, 0x9FE2, 0xC783, 0xC0D2,
+ 0xC784, 0xC0D3, 0xC785, 0xC0D4, 0xC786, 0x9FE3, 0xC787, 0xC0D5, 0xC788, 0xC0D6, 0xC789, 0xC0D7, 0xC78A, 0xC0D8, 0xC78B, 0x9FE4,
+ 0xC78C, 0x9FE5, 0xC78D, 0x9FE6, 0xC78E, 0xC0D9, 0xC78F, 0x9FE7, 0xC790, 0xC0DA, 0xC791, 0xC0DB, 0xC792, 0x9FE8, 0xC793, 0x9FE9,
+ 0xC794, 0xC0DC, 0xC795, 0x9FEA, 0xC796, 0xC0DD, 0xC797, 0xC0DE, 0xC798, 0xC0DF, 0xC799, 0x9FEB, 0xC79A, 0xC0E0, 0xC79B, 0x9FEC,
+ 0xC79C, 0x9FED, 0xC79D, 0x9FEE, 0xC79E, 0x9FEF, 0xC79F, 0x9FF0, 0xC7A0, 0xC0E1, 0xC7A1, 0xC0E2, 0xC7A2, 0x9FF1, 0xC7A3, 0xC0E3,
+ 0xC7A4, 0xC0E4, 0xC7A5, 0xC0E5, 0xC7A6, 0xC0E6, 0xC7A7, 0x9FF2, 0xC7A8, 0x9FF3, 0xC7A9, 0x9FF4, 0xC7AA, 0x9FF5, 0xC7AB, 0x9FF6,
+ 0xC7AC, 0xC0E7, 0xC7AD, 0xC0E8, 0xC7AE, 0x9FF7, 0xC7AF, 0x9FF8, 0xC7B0, 0xC0E9, 0xC7B1, 0x9FF9, 0xC7B2, 0x9FFA, 0xC7B3, 0x9FFB,
+ 0xC7B4, 0xC0EA, 0xC7B5, 0x9FFC, 0xC7B6, 0x9FFD, 0xC7B7, 0x9FFE, 0xC7B8, 0xA041, 0xC7B9, 0xA042, 0xC7BA, 0xA043, 0xC7BB, 0xA044,
+ 0xC7BC, 0xC0EB, 0xC7BD, 0xC0EC, 0xC7BE, 0xA045, 0xC7BF, 0xC0ED, 0xC7C0, 0xC0EE, 0xC7C1, 0xC0EF, 0xC7C2, 0xA046, 0xC7C3, 0xA047,
+ 0xC7C4, 0xA048, 0xC7C5, 0xA049, 0xC7C6, 0xA04A, 0xC7C7, 0xA04B, 0xC7C8, 0xC0F0, 0xC7C9, 0xC0F1, 0xC7CA, 0xA04C, 0xC7CB, 0xA04D,
+ 0xC7CC, 0xC0F2, 0xC7CD, 0xA04E, 0xC7CE, 0xC0F3, 0xC7CF, 0xA04F, 0xC7D0, 0xC0F4, 0xC7D1, 0xA050, 0xC7D2, 0xA051, 0xC7D3, 0xA052,
+ 0xC7D4, 0xA053, 0xC7D5, 0xA054, 0xC7D6, 0xA055, 0xC7D7, 0xA056, 0xC7D8, 0xC0F5, 0xC7D9, 0xA057, 0xC7DA, 0xA058, 0xC7DB, 0xA059,
+ 0xC7DC, 0xA05A, 0xC7DD, 0xC0F6, 0xC7DE, 0xA061, 0xC7DF, 0xA062, 0xC7E0, 0xA063, 0xC7E1, 0xA064, 0xC7E2, 0xA065, 0xC7E3, 0xA066,
+ 0xC7E4, 0xC0F7, 0xC7E5, 0xA067, 0xC7E6, 0xA068, 0xC7E7, 0xA069, 0xC7E8, 0xC0F8, 0xC7E9, 0xA06A, 0xC7EA, 0xA06B, 0xC7EB, 0xA06C,
+ 0xC7EC, 0xC0F9, 0xC7ED, 0xA06D, 0xC7EE, 0xA06E, 0xC7EF, 0xA06F, 0xC7F0, 0xA070, 0xC7F1, 0xA071, 0xC7F2, 0xA072, 0xC7F3, 0xA073,
+ 0xC7F4, 0xA074, 0xC7F5, 0xA075, 0xC7F6, 0xA076, 0xC7F7, 0xA077, 0xC7F8, 0xA078, 0xC7F9, 0xA079, 0xC7FA, 0xA07A, 0xC7FB, 0xA081,
+ 0xC7FC, 0xA082, 0xC7FD, 0xA083, 0xC7FE, 0xA084, 0xC7FF, 0xA085, 0xC800, 0xC0FA, 0xC801, 0xC0FB, 0xC802, 0xA086, 0xC803, 0xA087,
+ 0xC804, 0xC0FC, 0xC805, 0xA088, 0xC806, 0xA089, 0xC807, 0xA08A, 0xC808, 0xC0FD, 0xC809, 0xA08B, 0xC80A, 0xC0FE, 0xC80B, 0xA08C,
+ 0xC80C, 0xA08D, 0xC80D, 0xA08E, 0xC80E, 0xA08F, 0xC80F, 0xA090, 0xC810, 0xC1A1, 0xC811, 0xC1A2, 0xC812, 0xA091, 0xC813, 0xC1A3,
+ 0xC814, 0xA092, 0xC815, 0xC1A4, 0xC816, 0xC1A5, 0xC817, 0xA093, 0xC818, 0xA094, 0xC819, 0xA095, 0xC81A, 0xA096, 0xC81B, 0xA097,
+ 0xC81C, 0xC1A6, 0xC81D, 0xC1A7, 0xC81E, 0xA098, 0xC81F, 0xA099, 0xC820, 0xC1A8, 0xC821, 0xA09A, 0xC822, 0xA09B, 0xC823, 0xA09C,
+ 0xC824, 0xC1A9, 0xC825, 0xA09D, 0xC826, 0xA09E, 0xC827, 0xA09F, 0xC828, 0xA0A0, 0xC829, 0xA0A1, 0xC82A, 0xA0A2, 0xC82B, 0xA0A3,
+ 0xC82C, 0xC1AA, 0xC82D, 0xC1AB, 0xC82E, 0xA0A4, 0xC82F, 0xC1AC, 0xC830, 0xA0A5, 0xC831, 0xC1AD, 0xC832, 0xA0A6, 0xC833, 0xA0A7,
+ 0xC834, 0xA0A8, 0xC835, 0xA0A9, 0xC836, 0xA0AA, 0xC837, 0xA0AB, 0xC838, 0xC1AE, 0xC839, 0xA0AC, 0xC83A, 0xA0AD, 0xC83B, 0xA0AE,
+ 0xC83C, 0xC1AF, 0xC83D, 0xA0AF, 0xC83E, 0xA0B0, 0xC83F, 0xA0B1, 0xC840, 0xC1B0, 0xC841, 0xA0B2, 0xC842, 0xA0B3, 0xC843, 0xA0B4,
+ 0xC844, 0xA0B5, 0xC845, 0xA0B6, 0xC846, 0xA0B7, 0xC847, 0xA0B8, 0xC848, 0xC1B1, 0xC849, 0xC1B2, 0xC84A, 0xA0B9, 0xC84B, 0xA0BA,
+ 0xC84C, 0xC1B3, 0xC84D, 0xC1B4, 0xC84E, 0xA0BB, 0xC84F, 0xA0BC, 0xC850, 0xA0BD, 0xC851, 0xA0BE, 0xC852, 0xA0BF, 0xC853, 0xA0C0,
+ 0xC854, 0xC1B5, 0xC855, 0xA0C1, 0xC856, 0xA0C2, 0xC857, 0xA0C3, 0xC858, 0xA0C4, 0xC859, 0xA0C5, 0xC85A, 0xA0C6, 0xC85B, 0xA0C7,
+ 0xC85C, 0xA0C8, 0xC85D, 0xA0C9, 0xC85E, 0xA0CA, 0xC85F, 0xA0CB, 0xC860, 0xA0CC, 0xC861, 0xA0CD, 0xC862, 0xA0CE, 0xC863, 0xA0CF,
+ 0xC864, 0xA0D0, 0xC865, 0xA0D1, 0xC866, 0xA0D2, 0xC867, 0xA0D3, 0xC868, 0xA0D4, 0xC869, 0xA0D5, 0xC86A, 0xA0D6, 0xC86B, 0xA0D7,
+ 0xC86C, 0xA0D8, 0xC86D, 0xA0D9, 0xC86E, 0xA0DA, 0xC86F, 0xA0DB, 0xC870, 0xC1B6, 0xC871, 0xC1B7, 0xC872, 0xA0DC, 0xC873, 0xA0DD,
+ 0xC874, 0xC1B8, 0xC875, 0xA0DE, 0xC876, 0xA0DF, 0xC877, 0xA0E0, 0xC878, 0xC1B9, 0xC879, 0xA0E1, 0xC87A, 0xC1BA, 0xC87B, 0xA0E2,
+ 0xC87C, 0xA0E3, 0xC87D, 0xA0E4, 0xC87E, 0xA0E5, 0xC87F, 0xA0E6, 0xC880, 0xC1BB, 0xC881, 0xC1BC, 0xC882, 0xA0E7, 0xC883, 0xC1BD,
+ 0xC884, 0xA0E8, 0xC885, 0xC1BE, 0xC886, 0xC1BF, 0xC887, 0xC1C0, 0xC888, 0xA0E9, 0xC889, 0xA0EA, 0xC88A, 0xA0EB, 0xC88B, 0xC1C1,
+ 0xC88C, 0xC1C2, 0xC88D, 0xC1C3, 0xC88E, 0xA0EC, 0xC88F, 0xA0ED, 0xC890, 0xA0EE, 0xC891, 0xA0EF, 0xC892, 0xA0F0, 0xC893, 0xA0F1,
+ 0xC894, 0xC1C4, 0xC895, 0xA0F2, 0xC896, 0xA0F3, 0xC897, 0xA0F4, 0xC898, 0xA0F5, 0xC899, 0xA0F6, 0xC89A, 0xA0F7, 0xC89B, 0xA0F8,
+ 0xC89C, 0xA0F9, 0xC89D, 0xC1C5, 0xC89E, 0xA0FA, 0xC89F, 0xC1C6, 0xC8A0, 0xA0FB, 0xC8A1, 0xC1C7, 0xC8A2, 0xA0FC, 0xC8A3, 0xA0FD,
+ 0xC8A4, 0xA0FE, 0xC8A5, 0xA141, 0xC8A6, 0xA142, 0xC8A7, 0xA143, 0xC8A8, 0xC1C8, 0xC8A9, 0xA144, 0xC8AA, 0xA145, 0xC8AB, 0xA146,
+ 0xC8AC, 0xA147, 0xC8AD, 0xA148, 0xC8AE, 0xA149, 0xC8AF, 0xA14A, 0xC8B0, 0xA14B, 0xC8B1, 0xA14C, 0xC8B2, 0xA14D, 0xC8B3, 0xA14E,
+ 0xC8B4, 0xA14F, 0xC8B5, 0xA150, 0xC8B6, 0xA151, 0xC8B7, 0xA152, 0xC8B8, 0xA153, 0xC8B9, 0xA154, 0xC8BA, 0xA155, 0xC8BB, 0xA156,
+ 0xC8BC, 0xC1C9, 0xC8BD, 0xC1CA, 0xC8BE, 0xA157, 0xC8BF, 0xA158, 0xC8C0, 0xA159, 0xC8C1, 0xA15A, 0xC8C2, 0xA161, 0xC8C3, 0xA162,
+ 0xC8C4, 0xC1CB, 0xC8C5, 0xA163, 0xC8C6, 0xA164, 0xC8C7, 0xA165, 0xC8C8, 0xC1CC, 0xC8C9, 0xA166, 0xC8CA, 0xA167, 0xC8CB, 0xA168,
+ 0xC8CC, 0xC1CD, 0xC8CD, 0xA169, 0xC8CE, 0xA16A, 0xC8CF, 0xA16B, 0xC8D0, 0xA16C, 0xC8D1, 0xA16D, 0xC8D2, 0xA16E, 0xC8D3, 0xA16F,
+ 0xC8D4, 0xC1CE, 0xC8D5, 0xC1CF, 0xC8D6, 0xA170, 0xC8D7, 0xC1D0, 0xC8D8, 0xA171, 0xC8D9, 0xC1D1, 0xC8DA, 0xA172, 0xC8DB, 0xA173,
+ 0xC8DC, 0xA174, 0xC8DD, 0xA175, 0xC8DE, 0xA176, 0xC8DF, 0xA177, 0xC8E0, 0xC1D2, 0xC8E1, 0xC1D3, 0xC8E2, 0xA178, 0xC8E3, 0xA179,
+ 0xC8E4, 0xC1D4, 0xC8E5, 0xA17A, 0xC8E6, 0xA181, 0xC8E7, 0xA182, 0xC8E8, 0xA183, 0xC8E9, 0xA184, 0xC8EA, 0xA185, 0xC8EB, 0xA186,
+ 0xC8EC, 0xA187, 0xC8ED, 0xA188, 0xC8EE, 0xA189, 0xC8EF, 0xA18A, 0xC8F0, 0xA18B, 0xC8F1, 0xA18C, 0xC8F2, 0xA18D, 0xC8F3, 0xA18E,
+ 0xC8F4, 0xA18F, 0xC8F5, 0xC1D5, 0xC8F6, 0xA190, 0xC8F7, 0xA191, 0xC8F8, 0xA192, 0xC8F9, 0xA193, 0xC8FA, 0xA194, 0xC8FB, 0xA195,
+ 0xC8FC, 0xC1D6, 0xC8FD, 0xC1D7, 0xC8FE, 0xA196, 0xC8FF, 0xA197, 0xC900, 0xC1D8, 0xC901, 0xA198, 0xC902, 0xA199, 0xC903, 0xA19A,
+ 0xC904, 0xC1D9, 0xC905, 0xC1DA, 0xC906, 0xC1DB, 0xC907, 0xA19B, 0xC908, 0xA19C, 0xC909, 0xA19D, 0xC90A, 0xA19E, 0xC90B, 0xA19F,
+ 0xC90C, 0xC1DC, 0xC90D, 0xC1DD, 0xC90E, 0xA1A0, 0xC90F, 0xC1DE, 0xC910, 0xA241, 0xC911, 0xC1DF, 0xC912, 0xA242, 0xC913, 0xA243,
+ 0xC914, 0xA244, 0xC915, 0xA245, 0xC916, 0xA246, 0xC917, 0xA247, 0xC918, 0xC1E0, 0xC919, 0xA248, 0xC91A, 0xA249, 0xC91B, 0xA24A,
+ 0xC91C, 0xA24B, 0xC91D, 0xA24C, 0xC91E, 0xA24D, 0xC91F, 0xA24E, 0xC920, 0xA24F, 0xC921, 0xA250, 0xC922, 0xA251, 0xC923, 0xA252,
+ 0xC924, 0xA253, 0xC925, 0xA254, 0xC926, 0xA255, 0xC927, 0xA256, 0xC928, 0xA257, 0xC929, 0xA258, 0xC92A, 0xA259, 0xC92B, 0xA25A,
+ 0xC92C, 0xC1E1, 0xC92D, 0xA261, 0xC92E, 0xA262, 0xC92F, 0xA263, 0xC930, 0xA264, 0xC931, 0xA265, 0xC932, 0xA266, 0xC933, 0xA267,
+ 0xC934, 0xC1E2, 0xC935, 0xA268, 0xC936, 0xA269, 0xC937, 0xA26A, 0xC938, 0xA26B, 0xC939, 0xA26C, 0xC93A, 0xA26D, 0xC93B, 0xA26E,
+ 0xC93C, 0xA26F, 0xC93D, 0xA270, 0xC93E, 0xA271, 0xC93F, 0xA272, 0xC940, 0xA273, 0xC941, 0xA274, 0xC942, 0xA275, 0xC943, 0xA276,
+ 0xC944, 0xA277, 0xC945, 0xA278, 0xC946, 0xA279, 0xC947, 0xA27A, 0xC948, 0xA281, 0xC949, 0xA282, 0xC94A, 0xA283, 0xC94B, 0xA284,
+ 0xC94C, 0xA285, 0xC94D, 0xA286, 0xC94E, 0xA287, 0xC94F, 0xA288, 0xC950, 0xC1E3, 0xC951, 0xC1E4, 0xC952, 0xA289, 0xC953, 0xA28A,
+ 0xC954, 0xC1E5, 0xC955, 0xA28B, 0xC956, 0xA28C, 0xC957, 0xA28D, 0xC958, 0xC1E6, 0xC959, 0xA28E, 0xC95A, 0xA28F, 0xC95B, 0xA290,
+ 0xC95C, 0xA291, 0xC95D, 0xA292, 0xC95E, 0xA293, 0xC95F, 0xA294, 0xC960, 0xC1E7, 0xC961, 0xC1E8, 0xC962, 0xA295, 0xC963, 0xC1E9,
+ 0xC964, 0xA296, 0xC965, 0xA297, 0xC966, 0xA298, 0xC967, 0xA299, 0xC968, 0xA29A, 0xC969, 0xA29B, 0xC96A, 0xA29C, 0xC96B, 0xA29D,
+ 0xC96C, 0xC1EA, 0xC96D, 0xA29E, 0xC96E, 0xA29F, 0xC96F, 0xA2A0, 0xC970, 0xC1EB, 0xC971, 0xA341, 0xC972, 0xA342, 0xC973, 0xA343,
+ 0xC974, 0xC1EC, 0xC975, 0xA344, 0xC976, 0xA345, 0xC977, 0xA346, 0xC978, 0xA347, 0xC979, 0xA348, 0xC97A, 0xA349, 0xC97B, 0xA34A,
+ 0xC97C, 0xC1ED, 0xC97D, 0xA34B, 0xC97E, 0xA34C, 0xC97F, 0xA34D, 0xC980, 0xA34E, 0xC981, 0xA34F, 0xC982, 0xA350, 0xC983, 0xA351,
+ 0xC984, 0xA352, 0xC985, 0xA353, 0xC986, 0xA354, 0xC987, 0xA355, 0xC988, 0xC1EE, 0xC989, 0xC1EF, 0xC98A, 0xA356, 0xC98B, 0xA357,
+ 0xC98C, 0xC1F0, 0xC98D, 0xA358, 0xC98E, 0xA359, 0xC98F, 0xA35A, 0xC990, 0xC1F1, 0xC991, 0xA361, 0xC992, 0xA362, 0xC993, 0xA363,
+ 0xC994, 0xA364, 0xC995, 0xA365, 0xC996, 0xA366, 0xC997, 0xA367, 0xC998, 0xC1F2, 0xC999, 0xC1F3, 0xC99A, 0xA368, 0xC99B, 0xC1F4,
+ 0xC99C, 0xA369, 0xC99D, 0xC1F5, 0xC99E, 0xA36A, 0xC99F, 0xA36B, 0xC9A0, 0xA36C, 0xC9A1, 0xA36D, 0xC9A2, 0xA36E, 0xC9A3, 0xA36F,
+ 0xC9A4, 0xA370, 0xC9A5, 0xA371, 0xC9A6, 0xA372, 0xC9A7, 0xA373, 0xC9A8, 0xA374, 0xC9A9, 0xA375, 0xC9AA, 0xA376, 0xC9AB, 0xA377,
+ 0xC9AC, 0xA378, 0xC9AD, 0xA379, 0xC9AE, 0xA37A, 0xC9AF, 0xA381, 0xC9B0, 0xA382, 0xC9B1, 0xA383, 0xC9B2, 0xA384, 0xC9B3, 0xA385,
+ 0xC9B4, 0xA386, 0xC9B5, 0xA387, 0xC9B6, 0xA388, 0xC9B7, 0xA389, 0xC9B8, 0xA38A, 0xC9B9, 0xA38B, 0xC9BA, 0xA38C, 0xC9BB, 0xA38D,
+ 0xC9BC, 0xA38E, 0xC9BD, 0xA38F, 0xC9BE, 0xA390, 0xC9BF, 0xA391, 0xC9C0, 0xC1F6, 0xC9C1, 0xC1F7, 0xC9C2, 0xA392, 0xC9C3, 0xA393,
+ 0xC9C4, 0xC1F8, 0xC9C5, 0xA394, 0xC9C6, 0xA395, 0xC9C7, 0xC1F9, 0xC9C8, 0xC1FA, 0xC9C9, 0xA396, 0xC9CA, 0xC1FB, 0xC9CB, 0xA397,
+ 0xC9CC, 0xA398, 0xC9CD, 0xA399, 0xC9CE, 0xA39A, 0xC9CF, 0xA39B, 0xC9D0, 0xC1FC, 0xC9D1, 0xC1FD, 0xC9D2, 0xA39C, 0xC9D3, 0xC1FE,
+ 0xC9D4, 0xA39D, 0xC9D5, 0xC2A1, 0xC9D6, 0xC2A2, 0xC9D7, 0xA39E, 0xC9D8, 0xA39F, 0xC9D9, 0xC2A3, 0xC9DA, 0xC2A4, 0xC9DB, 0xA3A0,
+ 0xC9DC, 0xC2A5, 0xC9DD, 0xC2A6, 0xC9DE, 0xA441, 0xC9DF, 0xA442, 0xC9E0, 0xC2A7, 0xC9E1, 0xA443, 0xC9E2, 0xC2A8, 0xC9E3, 0xA444,
+ 0xC9E4, 0xC2A9, 0xC9E5, 0xA445, 0xC9E6, 0xA446, 0xC9E7, 0xC2AA, 0xC9E8, 0xA447, 0xC9E9, 0xA448, 0xC9EA, 0xA449, 0xC9EB, 0xA44A,
+ 0xC9EC, 0xC2AB, 0xC9ED, 0xC2AC, 0xC9EE, 0xA44B, 0xC9EF, 0xC2AD, 0xC9F0, 0xC2AE, 0xC9F1, 0xC2AF, 0xC9F2, 0xA44C, 0xC9F3, 0xA44D,
+ 0xC9F4, 0xA44E, 0xC9F5, 0xA44F, 0xC9F6, 0xA450, 0xC9F7, 0xA451, 0xC9F8, 0xC2B0, 0xC9F9, 0xC2B1, 0xC9FA, 0xA452, 0xC9FB, 0xA453,
+ 0xC9FC, 0xC2B2, 0xC9FD, 0xA454, 0xC9FE, 0xA455, 0xC9FF, 0xA456, 0xCA00, 0xC2B3, 0xCA01, 0xA457, 0xCA02, 0xA458, 0xCA03, 0xA459,
+ 0xCA04, 0xA45A, 0xCA05, 0xA461, 0xCA06, 0xA462, 0xCA07, 0xA463, 0xCA08, 0xC2B4, 0xCA09, 0xC2B5, 0xCA0A, 0xA464, 0xCA0B, 0xC2B6,
+ 0xCA0C, 0xC2B7, 0xCA0D, 0xC2B8, 0xCA0E, 0xA465, 0xCA0F, 0xA466, 0xCA10, 0xA467, 0xCA11, 0xA468, 0xCA12, 0xA469, 0xCA13, 0xA46A,
+ 0xCA14, 0xC2B9, 0xCA15, 0xA46B, 0xCA16, 0xA46C, 0xCA17, 0xA46D, 0xCA18, 0xC2BA, 0xCA19, 0xA46E, 0xCA1A, 0xA46F, 0xCA1B, 0xA470,
+ 0xCA1C, 0xA471, 0xCA1D, 0xA472, 0xCA1E, 0xA473, 0xCA1F, 0xA474, 0xCA20, 0xA475, 0xCA21, 0xA476, 0xCA22, 0xA477, 0xCA23, 0xA478,
+ 0xCA24, 0xA479, 0xCA25, 0xA47A, 0xCA26, 0xA481, 0xCA27, 0xA482, 0xCA28, 0xA483, 0xCA29, 0xC2BB, 0xCA2A, 0xA484, 0xCA2B, 0xA485,
+ 0xCA2C, 0xA486, 0xCA2D, 0xA487, 0xCA2E, 0xA488, 0xCA2F, 0xA489, 0xCA30, 0xA48A, 0xCA31, 0xA48B, 0xCA32, 0xA48C, 0xCA33, 0xA48D,
+ 0xCA34, 0xA48E, 0xCA35, 0xA48F, 0xCA36, 0xA490, 0xCA37, 0xA491, 0xCA38, 0xA492, 0xCA39, 0xA493, 0xCA3A, 0xA494, 0xCA3B, 0xA495,
+ 0xCA3C, 0xA496, 0xCA3D, 0xA497, 0xCA3E, 0xA498, 0xCA3F, 0xA499, 0xCA40, 0xA49A, 0xCA41, 0xA49B, 0xCA42, 0xA49C, 0xCA43, 0xA49D,
+ 0xCA44, 0xA49E, 0xCA45, 0xA49F, 0xCA46, 0xA4A0, 0xCA47, 0xA541, 0xCA48, 0xA542, 0xCA49, 0xA543, 0xCA4A, 0xA544, 0xCA4B, 0xA545,
+ 0xCA4C, 0xC2BC, 0xCA4D, 0xC2BD, 0xCA4E, 0xA546, 0xCA4F, 0xA547, 0xCA50, 0xC2BE, 0xCA51, 0xA548, 0xCA52, 0xA549, 0xCA53, 0xA54A,
+ 0xCA54, 0xC2BF, 0xCA55, 0xA54B, 0xCA56, 0xA54C, 0xCA57, 0xA54D, 0xCA58, 0xA54E, 0xCA59, 0xA54F, 0xCA5A, 0xA550, 0xCA5B, 0xA551,
+ 0xCA5C, 0xC2C0, 0xCA5D, 0xC2C1, 0xCA5E, 0xA552, 0xCA5F, 0xC2C2, 0xCA60, 0xC2C3, 0xCA61, 0xC2C4, 0xCA62, 0xA553, 0xCA63, 0xA554,
+ 0xCA64, 0xA555, 0xCA65, 0xA556, 0xCA66, 0xA557, 0xCA67, 0xA558, 0xCA68, 0xC2C5, 0xCA69, 0xA559, 0xCA6A, 0xA55A, 0xCA6B, 0xA561,
+ 0xCA6C, 0xA562, 0xCA6D, 0xA563, 0xCA6E, 0xA564, 0xCA6F, 0xA565, 0xCA70, 0xA566, 0xCA71, 0xA567, 0xCA72, 0xA568, 0xCA73, 0xA569,
+ 0xCA74, 0xA56A, 0xCA75, 0xA56B, 0xCA76, 0xA56C, 0xCA77, 0xA56D, 0xCA78, 0xA56E, 0xCA79, 0xA56F, 0xCA7A, 0xA570, 0xCA7B, 0xA571,
+ 0xCA7C, 0xA572, 0xCA7D, 0xC2C6, 0xCA7E, 0xA573, 0xCA7F, 0xA574, 0xCA80, 0xA575, 0xCA81, 0xA576, 0xCA82, 0xA577, 0xCA83, 0xA578,
+ 0xCA84, 0xC2C7, 0xCA85, 0xA579, 0xCA86, 0xA57A, 0xCA87, 0xA581, 0xCA88, 0xA582, 0xCA89, 0xA583, 0xCA8A, 0xA584, 0xCA8B, 0xA585,
+ 0xCA8C, 0xA586, 0xCA8D, 0xA587, 0xCA8E, 0xA588, 0xCA8F, 0xA589, 0xCA90, 0xA58A, 0xCA91, 0xA58B, 0xCA92, 0xA58C, 0xCA93, 0xA58D,
+ 0xCA94, 0xA58E, 0xCA95, 0xA58F, 0xCA96, 0xA590, 0xCA97, 0xA591, 0xCA98, 0xC2C8, 0xCA99, 0xA592, 0xCA9A, 0xA593, 0xCA9B, 0xA594,
+ 0xCA9C, 0xA595, 0xCA9D, 0xA596, 0xCA9E, 0xA597, 0xCA9F, 0xA598, 0xCAA0, 0xA599, 0xCAA1, 0xA59A, 0xCAA2, 0xA59B, 0xCAA3, 0xA59C,
+ 0xCAA4, 0xA59D, 0xCAA5, 0xA59E, 0xCAA6, 0xA59F, 0xCAA7, 0xA5A0, 0xCAA8, 0xA641, 0xCAA9, 0xA642, 0xCAAA, 0xA643, 0xCAAB, 0xA644,
+ 0xCAAC, 0xA645, 0xCAAD, 0xA646, 0xCAAE, 0xA647, 0xCAAF, 0xA648, 0xCAB0, 0xA649, 0xCAB1, 0xA64A, 0xCAB2, 0xA64B, 0xCAB3, 0xA64C,
+ 0xCAB4, 0xA64D, 0xCAB5, 0xA64E, 0xCAB6, 0xA64F, 0xCAB7, 0xA650, 0xCAB8, 0xA651, 0xCAB9, 0xA652, 0xCABA, 0xA653, 0xCABB, 0xA654,
+ 0xCABC, 0xC2C9, 0xCABD, 0xC2CA, 0xCABE, 0xA655, 0xCABF, 0xA656, 0xCAC0, 0xC2CB, 0xCAC1, 0xA657, 0xCAC2, 0xA658, 0xCAC3, 0xA659,
+ 0xCAC4, 0xC2CC, 0xCAC5, 0xA65A, 0xCAC6, 0xA661, 0xCAC7, 0xA662, 0xCAC8, 0xA663, 0xCAC9, 0xA664, 0xCACA, 0xA665, 0xCACB, 0xA666,
+ 0xCACC, 0xC2CD, 0xCACD, 0xC2CE, 0xCACE, 0xA667, 0xCACF, 0xC2CF, 0xCAD0, 0xA668, 0xCAD1, 0xC2D0, 0xCAD2, 0xA669, 0xCAD3, 0xC2D1,
+ 0xCAD4, 0xA66A, 0xCAD5, 0xA66B, 0xCAD6, 0xA66C, 0xCAD7, 0xA66D, 0xCAD8, 0xC2D2, 0xCAD9, 0xC2D3, 0xCADA, 0xA66E, 0xCADB, 0xA66F,
+ 0xCADC, 0xA670, 0xCADD, 0xA671, 0xCADE, 0xA672, 0xCADF, 0xA673, 0xCAE0, 0xC2D4, 0xCAE1, 0xA674, 0xCAE2, 0xA675, 0xCAE3, 0xA676,
+ 0xCAE4, 0xA677, 0xCAE5, 0xA678, 0xCAE6, 0xA679, 0xCAE7, 0xA67A, 0xCAE8, 0xA681, 0xCAE9, 0xA682, 0xCAEA, 0xA683, 0xCAEB, 0xA684,
+ 0xCAEC, 0xC2D5, 0xCAED, 0xA685, 0xCAEE, 0xA686, 0xCAEF, 0xA687, 0xCAF0, 0xA688, 0xCAF1, 0xA689, 0xCAF2, 0xA68A, 0xCAF3, 0xA68B,
+ 0xCAF4, 0xC2D6, 0xCAF5, 0xA68C, 0xCAF6, 0xA68D, 0xCAF7, 0xA68E, 0xCAF8, 0xA68F, 0xCAF9, 0xA690, 0xCAFA, 0xA691, 0xCAFB, 0xA692,
+ 0xCAFC, 0xA693, 0xCAFD, 0xA694, 0xCAFE, 0xA695, 0xCAFF, 0xA696, 0xCB00, 0xA697, 0xCB01, 0xA698, 0xCB02, 0xA699, 0xCB03, 0xA69A,
+ 0xCB04, 0xA69B, 0xCB05, 0xA69C, 0xCB06, 0xA69D, 0xCB07, 0xA69E, 0xCB08, 0xC2D7, 0xCB09, 0xA69F, 0xCB0A, 0xA6A0, 0xCB0B, 0xA741,
+ 0xCB0C, 0xA742, 0xCB0D, 0xA743, 0xCB0E, 0xA744, 0xCB0F, 0xA745, 0xCB10, 0xC2D8, 0xCB11, 0xA746, 0xCB12, 0xA747, 0xCB13, 0xA748,
+ 0xCB14, 0xC2D9, 0xCB15, 0xA749, 0xCB16, 0xA74A, 0xCB17, 0xA74B, 0xCB18, 0xC2DA, 0xCB19, 0xA74C, 0xCB1A, 0xA74D, 0xCB1B, 0xA74E,
+ 0xCB1C, 0xA74F, 0xCB1D, 0xA750, 0xCB1E, 0xA751, 0xCB1F, 0xA752, 0xCB20, 0xC2DB, 0xCB21, 0xC2DC, 0xCB22, 0xA753, 0xCB23, 0xA754,
+ 0xCB24, 0xA755, 0xCB25, 0xA756, 0xCB26, 0xA757, 0xCB27, 0xA758, 0xCB28, 0xA759, 0xCB29, 0xA75A, 0xCB2A, 0xA761, 0xCB2B, 0xA762,
+ 0xCB2C, 0xA763, 0xCB2D, 0xA764, 0xCB2E, 0xA765, 0xCB2F, 0xA766, 0xCB30, 0xA767, 0xCB31, 0xA768, 0xCB32, 0xA769, 0xCB33, 0xA76A,
+ 0xCB34, 0xA76B, 0xCB35, 0xA76C, 0xCB36, 0xA76D, 0xCB37, 0xA76E, 0xCB38, 0xA76F, 0xCB39, 0xA770, 0xCB3A, 0xA771, 0xCB3B, 0xA772,
+ 0xCB3C, 0xA773, 0xCB3D, 0xA774, 0xCB3E, 0xA775, 0xCB3F, 0xA776, 0xCB40, 0xA777, 0xCB41, 0xC2DD, 0xCB42, 0xA778, 0xCB43, 0xA779,
+ 0xCB44, 0xA77A, 0xCB45, 0xA781, 0xCB46, 0xA782, 0xCB47, 0xA783, 0xCB48, 0xC2DE, 0xCB49, 0xC2DF, 0xCB4A, 0xA784, 0xCB4B, 0xA785,
+ 0xCB4C, 0xC2E0, 0xCB4D, 0xA786, 0xCB4E, 0xA787, 0xCB4F, 0xA788, 0xCB50, 0xC2E1, 0xCB51, 0xA789, 0xCB52, 0xA78A, 0xCB53, 0xA78B,
+ 0xCB54, 0xA78C, 0xCB55, 0xA78D, 0xCB56, 0xA78E, 0xCB57, 0xA78F, 0xCB58, 0xC2E2, 0xCB59, 0xC2E3, 0xCB5A, 0xA790, 0xCB5B, 0xA791,
+ 0xCB5C, 0xA792, 0xCB5D, 0xC2E4, 0xCB5E, 0xA793, 0xCB5F, 0xA794, 0xCB60, 0xA795, 0xCB61, 0xA796, 0xCB62, 0xA797, 0xCB63, 0xA798,
+ 0xCB64, 0xC2E5, 0xCB65, 0xA799, 0xCB66, 0xA79A, 0xCB67, 0xA79B, 0xCB68, 0xA79C, 0xCB69, 0xA79D, 0xCB6A, 0xA79E, 0xCB6B, 0xA79F,
+ 0xCB6C, 0xA7A0, 0xCB6D, 0xA841, 0xCB6E, 0xA842, 0xCB6F, 0xA843, 0xCB70, 0xA844, 0xCB71, 0xA845, 0xCB72, 0xA846, 0xCB73, 0xA847,
+ 0xCB74, 0xA848, 0xCB75, 0xA849, 0xCB76, 0xA84A, 0xCB77, 0xA84B, 0xCB78, 0xC2E6, 0xCB79, 0xC2E7, 0xCB7A, 0xA84C, 0xCB7B, 0xA84D,
+ 0xCB7C, 0xA84E, 0xCB7D, 0xA84F, 0xCB7E, 0xA850, 0xCB7F, 0xA851, 0xCB80, 0xA852, 0xCB81, 0xA853, 0xCB82, 0xA854, 0xCB83, 0xA855,
+ 0xCB84, 0xA856, 0xCB85, 0xA857, 0xCB86, 0xA858, 0xCB87, 0xA859, 0xCB88, 0xA85A, 0xCB89, 0xA861, 0xCB8A, 0xA862, 0xCB8B, 0xA863,
+ 0xCB8C, 0xA864, 0xCB8D, 0xA865, 0xCB8E, 0xA866, 0xCB8F, 0xA867, 0xCB90, 0xA868, 0xCB91, 0xA869, 0xCB92, 0xA86A, 0xCB93, 0xA86B,
+ 0xCB94, 0xA86C, 0xCB95, 0xA86D, 0xCB96, 0xA86E, 0xCB97, 0xA86F, 0xCB98, 0xA870, 0xCB99, 0xA871, 0xCB9A, 0xA872, 0xCB9B, 0xA873,
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+ 0xCE64, 0xAF75, 0xCE65, 0xAF76, 0xCE66, 0xAF77, 0xCE67, 0xAF78, 0xCE68, 0xC4A7, 0xCE69, 0xC4A8, 0xCE6A, 0xAF79, 0xCE6B, 0xC4A9,
+ 0xCE6C, 0xAF7A, 0xCE6D, 0xC4AA, 0xCE6E, 0xAF81, 0xCE6F, 0xAF82, 0xCE70, 0xAF83, 0xCE71, 0xAF84, 0xCE72, 0xAF85, 0xCE73, 0xAF86,
+ 0xCE74, 0xC4AB, 0xCE75, 0xC4AC, 0xCE76, 0xAF87, 0xCE77, 0xAF88, 0xCE78, 0xC4AD, 0xCE79, 0xAF89, 0xCE7A, 0xAF8A, 0xCE7B, 0xAF8B,
+ 0xCE7C, 0xC4AE, 0xCE7D, 0xAF8C, 0xCE7E, 0xAF8D, 0xCE7F, 0xAF8E, 0xCE80, 0xAF8F, 0xCE81, 0xAF90, 0xCE82, 0xAF91, 0xCE83, 0xAF92,
+ 0xCE84, 0xC4AF, 0xCE85, 0xC4B0, 0xCE86, 0xAF93, 0xCE87, 0xC4B1, 0xCE88, 0xAF94, 0xCE89, 0xC4B2, 0xCE8A, 0xAF95, 0xCE8B, 0xAF96,
+ 0xCE8C, 0xAF97, 0xCE8D, 0xAF98, 0xCE8E, 0xAF99, 0xCE8F, 0xAF9A, 0xCE90, 0xC4B3, 0xCE91, 0xC4B4, 0xCE92, 0xAF9B, 0xCE93, 0xAF9C,
+ 0xCE94, 0xC4B5, 0xCE95, 0xAF9D, 0xCE96, 0xAF9E, 0xCE97, 0xAF9F, 0xCE98, 0xC4B6, 0xCE99, 0xAFA0, 0xCE9A, 0xB041, 0xCE9B, 0xB042,
+ 0xCE9C, 0xB043, 0xCE9D, 0xB044, 0xCE9E, 0xB045, 0xCE9F, 0xB046, 0xCEA0, 0xC4B7, 0xCEA1, 0xC4B8, 0xCEA2, 0xB047, 0xCEA3, 0xC4B9,
+ 0xCEA4, 0xC4BA, 0xCEA5, 0xC4BB, 0xCEA6, 0xB048, 0xCEA7, 0xB049, 0xCEA8, 0xB04A, 0xCEA9, 0xB04B, 0xCEAA, 0xB04C, 0xCEAB, 0xB04D,
+ 0xCEAC, 0xC4BC, 0xCEAD, 0xC4BD, 0xCEAE, 0xB04E, 0xCEAF, 0xB04F, 0xCEB0, 0xB050, 0xCEB1, 0xB051, 0xCEB2, 0xB052, 0xCEB3, 0xB053,
+ 0xCEB4, 0xB054, 0xCEB5, 0xB055, 0xCEB6, 0xB056, 0xCEB7, 0xB057, 0xCEB8, 0xB058, 0xCEB9, 0xB059, 0xCEBA, 0xB05A, 0xCEBB, 0xB061,
+ 0xCEBC, 0xB062, 0xCEBD, 0xB063, 0xCEBE, 0xB064, 0xCEBF, 0xB065, 0xCEC0, 0xB066, 0xCEC1, 0xC4BE, 0xCEC2, 0xB067, 0xCEC3, 0xB068,
+ 0xCEC4, 0xB069, 0xCEC5, 0xB06A, 0xCEC6, 0xB06B, 0xCEC7, 0xB06C, 0xCEC8, 0xB06D, 0xCEC9, 0xB06E, 0xCECA, 0xB06F, 0xCECB, 0xB070,
+ 0xCECC, 0xB071, 0xCECD, 0xB072, 0xCECE, 0xB073, 0xCECF, 0xB074, 0xCED0, 0xB075, 0xCED1, 0xB076, 0xCED2, 0xB077, 0xCED3, 0xB078,
+ 0xCED4, 0xB079, 0xCED5, 0xB07A, 0xCED6, 0xB081, 0xCED7, 0xB082, 0xCED8, 0xB083, 0xCED9, 0xB084, 0xCEDA, 0xB085, 0xCEDB, 0xB086,
+ 0xCEDC, 0xB087, 0xCEDD, 0xB088, 0xCEDE, 0xB089, 0xCEDF, 0xB08A, 0xCEE0, 0xB08B, 0xCEE1, 0xB08C, 0xCEE2, 0xB08D, 0xCEE3, 0xB08E,
+ 0xCEE4, 0xC4BF, 0xCEE5, 0xC4C0, 0xCEE6, 0xB08F, 0xCEE7, 0xB090, 0xCEE8, 0xC4C1, 0xCEE9, 0xB091, 0xCEEA, 0xB092, 0xCEEB, 0xC4C2,
+ 0xCEEC, 0xC4C3, 0xCEED, 0xB093, 0xCEEE, 0xB094, 0xCEEF, 0xB095, 0xCEF0, 0xB096, 0xCEF1, 0xB097, 0xCEF2, 0xB098, 0xCEF3, 0xB099,
+ 0xCEF4, 0xC4C4, 0xCEF5, 0xC4C5, 0xCEF6, 0xB09A, 0xCEF7, 0xC4C6, 0xCEF8, 0xC4C7, 0xCEF9, 0xC4C8, 0xCEFA, 0xB09B, 0xCEFB, 0xB09C,
+ 0xCEFC, 0xB09D, 0xCEFD, 0xB09E, 0xCEFE, 0xB09F, 0xCEFF, 0xB0A0, 0xCF00, 0xC4C9, 0xCF01, 0xC4CA, 0xCF02, 0xB141, 0xCF03, 0xB142,
+ 0xCF04, 0xC4CB, 0xCF05, 0xB143, 0xCF06, 0xB144, 0xCF07, 0xB145, 0xCF08, 0xC4CC, 0xCF09, 0xB146, 0xCF0A, 0xB147, 0xCF0B, 0xB148,
+ 0xCF0C, 0xB149, 0xCF0D, 0xB14A, 0xCF0E, 0xB14B, 0xCF0F, 0xB14C, 0xCF10, 0xC4CD, 0xCF11, 0xC4CE, 0xCF12, 0xB14D, 0xCF13, 0xC4CF,
+ 0xCF14, 0xB14E, 0xCF15, 0xC4D0, 0xCF16, 0xB14F, 0xCF17, 0xB150, 0xCF18, 0xB151, 0xCF19, 0xB152, 0xCF1A, 0xB153, 0xCF1B, 0xB154,
+ 0xCF1C, 0xC4D1, 0xCF1D, 0xB155, 0xCF1E, 0xB156, 0xCF1F, 0xB157, 0xCF20, 0xC4D2, 0xCF21, 0xB158, 0xCF22, 0xB159, 0xCF23, 0xB15A,
+ 0xCF24, 0xC4D3, 0xCF25, 0xB161, 0xCF26, 0xB162, 0xCF27, 0xB163, 0xCF28, 0xB164, 0xCF29, 0xB165, 0xCF2A, 0xB166, 0xCF2B, 0xB167,
+ 0xCF2C, 0xC4D4, 0xCF2D, 0xC4D5, 0xCF2E, 0xB168, 0xCF2F, 0xC4D6, 0xCF30, 0xC4D7, 0xCF31, 0xC4D8, 0xCF32, 0xB169, 0xCF33, 0xB16A,
+ 0xCF34, 0xB16B, 0xCF35, 0xB16C, 0xCF36, 0xB16D, 0xCF37, 0xB16E, 0xCF38, 0xC4D9, 0xCF39, 0xB16F, 0xCF3A, 0xB170, 0xCF3B, 0xB171,
+ 0xCF3C, 0xB172, 0xCF3D, 0xB173, 0xCF3E, 0xB174, 0xCF3F, 0xB175, 0xCF40, 0xB176, 0xCF41, 0xB177, 0xCF42, 0xB178, 0xCF43, 0xB179,
+ 0xCF44, 0xB17A, 0xCF45, 0xB181, 0xCF46, 0xB182, 0xCF47, 0xB183, 0xCF48, 0xB184, 0xCF49, 0xB185, 0xCF4A, 0xB186, 0xCF4B, 0xB187,
+ 0xCF4C, 0xB188, 0xCF4D, 0xB189, 0xCF4E, 0xB18A, 0xCF4F, 0xB18B, 0xCF50, 0xB18C, 0xCF51, 0xB18D, 0xCF52, 0xB18E, 0xCF53, 0xB18F,
+ 0xCF54, 0xC4DA, 0xCF55, 0xC4DB, 0xCF56, 0xB190, 0xCF57, 0xB191, 0xCF58, 0xC4DC, 0xCF59, 0xB192, 0xCF5A, 0xB193, 0xCF5B, 0xB194,
+ 0xCF5C, 0xC4DD, 0xCF5D, 0xB195, 0xCF5E, 0xB196, 0xCF5F, 0xB197, 0xCF60, 0xB198, 0xCF61, 0xB199, 0xCF62, 0xB19A, 0xCF63, 0xB19B,
+ 0xCF64, 0xC4DE, 0xCF65, 0xC4DF, 0xCF66, 0xB19C, 0xCF67, 0xC4E0, 0xCF68, 0xB19D, 0xCF69, 0xC4E1, 0xCF6A, 0xB19E, 0xCF6B, 0xB19F,
+ 0xCF6C, 0xB1A0, 0xCF6D, 0xB241, 0xCF6E, 0xB242, 0xCF6F, 0xB243, 0xCF70, 0xC4E2, 0xCF71, 0xC4E3, 0xCF72, 0xB244, 0xCF73, 0xB245,
+ 0xCF74, 0xC4E4, 0xCF75, 0xB246, 0xCF76, 0xB247, 0xCF77, 0xB248, 0xCF78, 0xC4E5, 0xCF79, 0xB249, 0xCF7A, 0xB24A, 0xCF7B, 0xB24B,
+ 0xCF7C, 0xB24C, 0xCF7D, 0xB24D, 0xCF7E, 0xB24E, 0xCF7F, 0xB24F, 0xCF80, 0xC4E6, 0xCF81, 0xB250, 0xCF82, 0xB251, 0xCF83, 0xB252,
+ 0xCF84, 0xB253, 0xCF85, 0xC4E7, 0xCF86, 0xB254, 0xCF87, 0xB255, 0xCF88, 0xB256, 0xCF89, 0xB257, 0xCF8A, 0xB258, 0xCF8B, 0xB259,
+ 0xCF8C, 0xC4E8, 0xCF8D, 0xB25A, 0xCF8E, 0xB261, 0xCF8F, 0xB262, 0xCF90, 0xB263, 0xCF91, 0xB264, 0xCF92, 0xB265, 0xCF93, 0xB266,
+ 0xCF94, 0xB267, 0xCF95, 0xB268, 0xCF96, 0xB269, 0xCF97, 0xB26A, 0xCF98, 0xB26B, 0xCF99, 0xB26C, 0xCF9A, 0xB26D, 0xCF9B, 0xB26E,
+ 0xCF9C, 0xB26F, 0xCF9D, 0xB270, 0xCF9E, 0xB271, 0xCF9F, 0xB272, 0xCFA0, 0xB273, 0xCFA1, 0xC4E9, 0xCFA2, 0xB274, 0xCFA3, 0xB275,
+ 0xCFA4, 0xB276, 0xCFA5, 0xB277, 0xCFA6, 0xB278, 0xCFA7, 0xB279, 0xCFA8, 0xC4EA, 0xCFA9, 0xB27A, 0xCFAA, 0xB281, 0xCFAB, 0xB282,
+ 0xCFAC, 0xB283, 0xCFAD, 0xB284, 0xCFAE, 0xB285, 0xCFAF, 0xB286, 0xCFB0, 0xC4EB, 0xCFB1, 0xB287, 0xCFB2, 0xB288, 0xCFB3, 0xB289,
+ 0xCFB4, 0xB28A, 0xCFB5, 0xB28B, 0xCFB6, 0xB28C, 0xCFB7, 0xB28D, 0xCFB8, 0xB28E, 0xCFB9, 0xB28F, 0xCFBA, 0xB290, 0xCFBB, 0xB291,
+ 0xCFBC, 0xB292, 0xCFBD, 0xB293, 0xCFBE, 0xB294, 0xCFBF, 0xB295, 0xCFC0, 0xB296, 0xCFC1, 0xB297, 0xCFC2, 0xB298, 0xCFC3, 0xB299,
+ 0xCFC4, 0xC4EC, 0xCFC5, 0xB29A, 0xCFC6, 0xB29B, 0xCFC7, 0xB29C, 0xCFC8, 0xB29D, 0xCFC9, 0xB29E, 0xCFCA, 0xB29F, 0xCFCB, 0xB2A0,
+ 0xCFCC, 0xB341, 0xCFCD, 0xB342, 0xCFCE, 0xB343, 0xCFCF, 0xB344, 0xCFD0, 0xB345, 0xCFD1, 0xB346, 0xCFD2, 0xB347, 0xCFD3, 0xB348,
+ 0xCFD4, 0xB349, 0xCFD5, 0xB34A, 0xCFD6, 0xB34B, 0xCFD7, 0xB34C, 0xCFD8, 0xB34D, 0xCFD9, 0xB34E, 0xCFDA, 0xB34F, 0xCFDB, 0xB350,
+ 0xCFDC, 0xB351, 0xCFDD, 0xB352, 0xCFDE, 0xB353, 0xCFDF, 0xB354, 0xCFE0, 0xC4ED, 0xCFE1, 0xC4EE, 0xCFE2, 0xB355, 0xCFE3, 0xB356,
+ 0xCFE4, 0xC4EF, 0xCFE5, 0xB357, 0xCFE6, 0xB358, 0xCFE7, 0xB359, 0xCFE8, 0xC4F0, 0xCFE9, 0xB35A, 0xCFEA, 0xB361, 0xCFEB, 0xB362,
+ 0xCFEC, 0xB363, 0xCFED, 0xB364, 0xCFEE, 0xB365, 0xCFEF, 0xB366, 0xCFF0, 0xC4F1, 0xCFF1, 0xC4F2, 0xCFF2, 0xB367, 0xCFF3, 0xC4F3,
+ 0xCFF4, 0xB368, 0xCFF5, 0xC4F4, 0xCFF6, 0xB369, 0xCFF7, 0xB36A, 0xCFF8, 0xB36B, 0xCFF9, 0xB36C, 0xCFFA, 0xB36D, 0xCFFB, 0xB36E,
+ 0xCFFC, 0xC4F5, 0xCFFD, 0xB36F, 0xCFFE, 0xB370, 0xCFFF, 0xB371, 0xD000, 0xC4F6, 0xD001, 0xB372, 0xD002, 0xB373, 0xD003, 0xB374,
+ 0xD004, 0xC4F7, 0xD005, 0xB375, 0xD006, 0xB376, 0xD007, 0xB377, 0xD008, 0xB378, 0xD009, 0xB379, 0xD00A, 0xB37A, 0xD00B, 0xB381,
+ 0xD00C, 0xB382, 0xD00D, 0xB383, 0xD00E, 0xB384, 0xD00F, 0xB385, 0xD010, 0xB386, 0xD011, 0xC4F8, 0xD012, 0xB387, 0xD013, 0xB388,
+ 0xD014, 0xB389, 0xD015, 0xB38A, 0xD016, 0xB38B, 0xD017, 0xB38C, 0xD018, 0xC4F9, 0xD019, 0xB38D, 0xD01A, 0xB38E, 0xD01B, 0xB38F,
+ 0xD01C, 0xB390, 0xD01D, 0xB391, 0xD01E, 0xB392, 0xD01F, 0xB393, 0xD020, 0xB394, 0xD021, 0xB395, 0xD022, 0xB396, 0xD023, 0xB397,
+ 0xD024, 0xB398, 0xD025, 0xB399, 0xD026, 0xB39A, 0xD027, 0xB39B, 0xD028, 0xB39C, 0xD029, 0xB39D, 0xD02A, 0xB39E, 0xD02B, 0xB39F,
+ 0xD02C, 0xB3A0, 0xD02D, 0xC4FA, 0xD02E, 0xB441, 0xD02F, 0xB442, 0xD030, 0xB443, 0xD031, 0xB444, 0xD032, 0xB445, 0xD033, 0xB446,
+ 0xD034, 0xC4FB, 0xD035, 0xC4FC, 0xD036, 0xB447, 0xD037, 0xB448, 0xD038, 0xC4FD, 0xD039, 0xB449, 0xD03A, 0xB44A, 0xD03B, 0xB44B,
+ 0xD03C, 0xC4FE, 0xD03D, 0xB44C, 0xD03E, 0xB44D, 0xD03F, 0xB44E, 0xD040, 0xB44F, 0xD041, 0xB450, 0xD042, 0xB451, 0xD043, 0xB452,
+ 0xD044, 0xC5A1, 0xD045, 0xC5A2, 0xD046, 0xB453, 0xD047, 0xC5A3, 0xD048, 0xB454, 0xD049, 0xC5A4, 0xD04A, 0xB455, 0xD04B, 0xB456,
+ 0xD04C, 0xB457, 0xD04D, 0xB458, 0xD04E, 0xB459, 0xD04F, 0xB45A, 0xD050, 0xC5A5, 0xD051, 0xB461, 0xD052, 0xB462, 0xD053, 0xB463,
+ 0xD054, 0xC5A6, 0xD055, 0xB464, 0xD056, 0xB465, 0xD057, 0xB466, 0xD058, 0xC5A7, 0xD059, 0xB467, 0xD05A, 0xB468, 0xD05B, 0xB469,
+ 0xD05C, 0xB46A, 0xD05D, 0xB46B, 0xD05E, 0xB46C, 0xD05F, 0xB46D, 0xD060, 0xC5A8, 0xD061, 0xB46E, 0xD062, 0xB46F, 0xD063, 0xB470,
+ 0xD064, 0xB471, 0xD065, 0xB472, 0xD066, 0xB473, 0xD067, 0xB474, 0xD068, 0xB475, 0xD069, 0xB476, 0xD06A, 0xB477, 0xD06B, 0xB478,
+ 0xD06C, 0xC5A9, 0xD06D, 0xC5AA, 0xD06E, 0xB479, 0xD06F, 0xB47A, 0xD070, 0xC5AB, 0xD071, 0xB481, 0xD072, 0xB482, 0xD073, 0xB483,
+ 0xD074, 0xC5AC, 0xD075, 0xB484, 0xD076, 0xB485, 0xD077, 0xB486, 0xD078, 0xB487, 0xD079, 0xB488, 0xD07A, 0xB489, 0xD07B, 0xB48A,
+ 0xD07C, 0xC5AD, 0xD07D, 0xC5AE, 0xD07E, 0xB48B, 0xD07F, 0xB48C, 0xD080, 0xB48D, 0xD081, 0xC5AF, 0xD082, 0xB48E, 0xD083, 0xB48F,
+ 0xD084, 0xB490, 0xD085, 0xB491, 0xD086, 0xB492, 0xD087, 0xB493, 0xD088, 0xB494, 0xD089, 0xB495, 0xD08A, 0xB496, 0xD08B, 0xB497,
+ 0xD08C, 0xB498, 0xD08D, 0xB499, 0xD08E, 0xB49A, 0xD08F, 0xB49B, 0xD090, 0xB49C, 0xD091, 0xB49D, 0xD092, 0xB49E, 0xD093, 0xB49F,
+ 0xD094, 0xB4A0, 0xD095, 0xB541, 0xD096, 0xB542, 0xD097, 0xB543, 0xD098, 0xB544, 0xD099, 0xB545, 0xD09A, 0xB546, 0xD09B, 0xB547,
+ 0xD09C, 0xB548, 0xD09D, 0xB549, 0xD09E, 0xB54A, 0xD09F, 0xB54B, 0xD0A0, 0xB54C, 0xD0A1, 0xB54D, 0xD0A2, 0xB54E, 0xD0A3, 0xB54F,
+ 0xD0A4, 0xC5B0, 0xD0A5, 0xC5B1, 0xD0A6, 0xB550, 0xD0A7, 0xB551, 0xD0A8, 0xC5B2, 0xD0A9, 0xB552, 0xD0AA, 0xB553, 0xD0AB, 0xB554,
+ 0xD0AC, 0xC5B3, 0xD0AD, 0xB555, 0xD0AE, 0xB556, 0xD0AF, 0xB557, 0xD0B0, 0xB558, 0xD0B1, 0xB559, 0xD0B2, 0xB55A, 0xD0B3, 0xB561,
+ 0xD0B4, 0xC5B4, 0xD0B5, 0xC5B5, 0xD0B6, 0xB562, 0xD0B7, 0xC5B6, 0xD0B8, 0xB563, 0xD0B9, 0xC5B7, 0xD0BA, 0xB564, 0xD0BB, 0xB565,
+ 0xD0BC, 0xB566, 0xD0BD, 0xB567, 0xD0BE, 0xB568, 0xD0BF, 0xB569, 0xD0C0, 0xC5B8, 0xD0C1, 0xC5B9, 0xD0C2, 0xB56A, 0xD0C3, 0xB56B,
+ 0xD0C4, 0xC5BA, 0xD0C5, 0xB56C, 0xD0C6, 0xB56D, 0xD0C7, 0xB56E, 0xD0C8, 0xC5BB, 0xD0C9, 0xC5BC, 0xD0CA, 0xB56F, 0xD0CB, 0xB570,
+ 0xD0CC, 0xB571, 0xD0CD, 0xB572, 0xD0CE, 0xB573, 0xD0CF, 0xB574, 0xD0D0, 0xC5BD, 0xD0D1, 0xC5BE, 0xD0D2, 0xB575, 0xD0D3, 0xC5BF,
+ 0xD0D4, 0xC5C0, 0xD0D5, 0xC5C1, 0xD0D6, 0xB576, 0xD0D7, 0xB577, 0xD0D8, 0xB578, 0xD0D9, 0xB579, 0xD0DA, 0xB57A, 0xD0DB, 0xB581,
+ 0xD0DC, 0xC5C2, 0xD0DD, 0xC5C3, 0xD0DE, 0xB582, 0xD0DF, 0xB583, 0xD0E0, 0xC5C4, 0xD0E1, 0xB584, 0xD0E2, 0xB585, 0xD0E3, 0xB586,
+ 0xD0E4, 0xC5C5, 0xD0E5, 0xB587, 0xD0E6, 0xB588, 0xD0E7, 0xB589, 0xD0E8, 0xB58A, 0xD0E9, 0xB58B, 0xD0EA, 0xB58C, 0xD0EB, 0xB58D,
+ 0xD0EC, 0xC5C6, 0xD0ED, 0xC5C7, 0xD0EE, 0xB58E, 0xD0EF, 0xC5C8, 0xD0F0, 0xC5C9, 0xD0F1, 0xC5CA, 0xD0F2, 0xB58F, 0xD0F3, 0xB590,
+ 0xD0F4, 0xB591, 0xD0F5, 0xB592, 0xD0F6, 0xB593, 0xD0F7, 0xB594, 0xD0F8, 0xC5CB, 0xD0F9, 0xB595, 0xD0FA, 0xB596, 0xD0FB, 0xB597,
+ 0xD0FC, 0xB598, 0xD0FD, 0xB599, 0xD0FE, 0xB59A, 0xD0FF, 0xB59B, 0xD100, 0xB59C, 0xD101, 0xB59D, 0xD102, 0xB59E, 0xD103, 0xB59F,
+ 0xD104, 0xB5A0, 0xD105, 0xB641, 0xD106, 0xB642, 0xD107, 0xB643, 0xD108, 0xB644, 0xD109, 0xB645, 0xD10A, 0xB646, 0xD10B, 0xB647,
+ 0xD10C, 0xB648, 0xD10D, 0xC5CC, 0xD10E, 0xB649, 0xD10F, 0xB64A, 0xD110, 0xB64B, 0xD111, 0xB64C, 0xD112, 0xB64D, 0xD113, 0xB64E,
+ 0xD114, 0xB64F, 0xD115, 0xB650, 0xD116, 0xB651, 0xD117, 0xB652, 0xD118, 0xB653, 0xD119, 0xB654, 0xD11A, 0xB655, 0xD11B, 0xB656,
+ 0xD11C, 0xB657, 0xD11D, 0xB658, 0xD11E, 0xB659, 0xD11F, 0xB65A, 0xD120, 0xB661, 0xD121, 0xB662, 0xD122, 0xB663, 0xD123, 0xB664,
+ 0xD124, 0xB665, 0xD125, 0xB666, 0xD126, 0xB667, 0xD127, 0xB668, 0xD128, 0xB669, 0xD129, 0xB66A, 0xD12A, 0xB66B, 0xD12B, 0xB66C,
+ 0xD12C, 0xB66D, 0xD12D, 0xB66E, 0xD12E, 0xB66F, 0xD12F, 0xB670, 0xD130, 0xC5CD, 0xD131, 0xC5CE, 0xD132, 0xB671, 0xD133, 0xB672,
+ 0xD134, 0xC5CF, 0xD135, 0xB673, 0xD136, 0xB674, 0xD137, 0xB675, 0xD138, 0xC5D0, 0xD139, 0xB676, 0xD13A, 0xC5D1, 0xD13B, 0xB677,
+ 0xD13C, 0xB678, 0xD13D, 0xB679, 0xD13E, 0xB67A, 0xD13F, 0xB681, 0xD140, 0xC5D2, 0xD141, 0xC5D3, 0xD142, 0xB682, 0xD143, 0xC5D4,
+ 0xD144, 0xC5D5, 0xD145, 0xC5D6, 0xD146, 0xB683, 0xD147, 0xB684, 0xD148, 0xB685, 0xD149, 0xB686, 0xD14A, 0xB687, 0xD14B, 0xB688,
+ 0xD14C, 0xC5D7, 0xD14D, 0xC5D8, 0xD14E, 0xB689, 0xD14F, 0xB68A, 0xD150, 0xC5D9, 0xD151, 0xB68B, 0xD152, 0xB68C, 0xD153, 0xB68D,
+ 0xD154, 0xC5DA, 0xD155, 0xB68E, 0xD156, 0xB68F, 0xD157, 0xB690, 0xD158, 0xB691, 0xD159, 0xB692, 0xD15A, 0xB693, 0xD15B, 0xB694,
+ 0xD15C, 0xC5DB, 0xD15D, 0xC5DC, 0xD15E, 0xB695, 0xD15F, 0xC5DD, 0xD160, 0xB696, 0xD161, 0xC5DE, 0xD162, 0xB697, 0xD163, 0xB698,
+ 0xD164, 0xB699, 0xD165, 0xB69A, 0xD166, 0xB69B, 0xD167, 0xB69C, 0xD168, 0xC5DF, 0xD169, 0xB69D, 0xD16A, 0xB69E, 0xD16B, 0xB69F,
+ 0xD16C, 0xC5E0, 0xD16D, 0xB6A0, 0xD16E, 0xB741, 0xD16F, 0xB742, 0xD170, 0xB743, 0xD171, 0xB744, 0xD172, 0xB745, 0xD173, 0xB746,
+ 0xD174, 0xB747, 0xD175, 0xB748, 0xD176, 0xB749, 0xD177, 0xB74A, 0xD178, 0xB74B, 0xD179, 0xB74C, 0xD17A, 0xB74D, 0xD17B, 0xB74E,
+ 0xD17C, 0xC5E1, 0xD17D, 0xB74F, 0xD17E, 0xB750, 0xD17F, 0xB751, 0xD180, 0xB752, 0xD181, 0xB753, 0xD182, 0xB754, 0xD183, 0xB755,
+ 0xD184, 0xC5E2, 0xD185, 0xB756, 0xD186, 0xB757, 0xD187, 0xB758, 0xD188, 0xC5E3, 0xD189, 0xB759, 0xD18A, 0xB75A, 0xD18B, 0xB761,
+ 0xD18C, 0xB762, 0xD18D, 0xB763, 0xD18E, 0xB764, 0xD18F, 0xB765, 0xD190, 0xB766, 0xD191, 0xB767, 0xD192, 0xB768, 0xD193, 0xB769,
+ 0xD194, 0xB76A, 0xD195, 0xB76B, 0xD196, 0xB76C, 0xD197, 0xB76D, 0xD198, 0xB76E, 0xD199, 0xB76F, 0xD19A, 0xB770, 0xD19B, 0xB771,
+ 0xD19C, 0xB772, 0xD19D, 0xB773, 0xD19E, 0xB774, 0xD19F, 0xB775, 0xD1A0, 0xC5E4, 0xD1A1, 0xC5E5, 0xD1A2, 0xB776, 0xD1A3, 0xB777,
+ 0xD1A4, 0xC5E6, 0xD1A5, 0xB778, 0xD1A6, 0xB779, 0xD1A7, 0xB77A, 0xD1A8, 0xC5E7, 0xD1A9, 0xB781, 0xD1AA, 0xB782, 0xD1AB, 0xB783,
+ 0xD1AC, 0xB784, 0xD1AD, 0xB785, 0xD1AE, 0xB786, 0xD1AF, 0xB787, 0xD1B0, 0xC5E8, 0xD1B1, 0xC5E9, 0xD1B2, 0xB788, 0xD1B3, 0xC5EA,
+ 0xD1B4, 0xB789, 0xD1B5, 0xC5EB, 0xD1B6, 0xB78A, 0xD1B7, 0xB78B, 0xD1B8, 0xB78C, 0xD1B9, 0xB78D, 0xD1BA, 0xC5EC, 0xD1BB, 0xB78E,
+ 0xD1BC, 0xC5ED, 0xD1BD, 0xB78F, 0xD1BE, 0xB790, 0xD1BF, 0xB791, 0xD1C0, 0xC5EE, 0xD1C1, 0xB792, 0xD1C2, 0xB793, 0xD1C3, 0xB794,
+ 0xD1C4, 0xB795, 0xD1C5, 0xB796, 0xD1C6, 0xB797, 0xD1C7, 0xB798, 0xD1C8, 0xB799, 0xD1C9, 0xB79A, 0xD1CA, 0xB79B, 0xD1CB, 0xB79C,
+ 0xD1CC, 0xB79D, 0xD1CD, 0xB79E, 0xD1CE, 0xB79F, 0xD1CF, 0xB7A0, 0xD1D0, 0xB841, 0xD1D1, 0xB842, 0xD1D2, 0xB843, 0xD1D3, 0xB844,
+ 0xD1D4, 0xB845, 0xD1D5, 0xB846, 0xD1D6, 0xB847, 0xD1D7, 0xB848, 0xD1D8, 0xC5EF, 0xD1D9, 0xB849, 0xD1DA, 0xB84A, 0xD1DB, 0xB84B,
+ 0xD1DC, 0xB84C, 0xD1DD, 0xB84D, 0xD1DE, 0xB84E, 0xD1DF, 0xB84F, 0xD1E0, 0xB850, 0xD1E1, 0xB851, 0xD1E2, 0xB852, 0xD1E3, 0xB853,
+ 0xD1E4, 0xB854, 0xD1E5, 0xB855, 0xD1E6, 0xB856, 0xD1E7, 0xB857, 0xD1E8, 0xB858, 0xD1E9, 0xB859, 0xD1EA, 0xB85A, 0xD1EB, 0xB861,
+ 0xD1EC, 0xB862, 0xD1ED, 0xB863, 0xD1EE, 0xB864, 0xD1EF, 0xB865, 0xD1F0, 0xB866, 0xD1F1, 0xB867, 0xD1F2, 0xB868, 0xD1F3, 0xB869,
+ 0xD1F4, 0xC5F0, 0xD1F5, 0xB86A, 0xD1F6, 0xB86B, 0xD1F7, 0xB86C, 0xD1F8, 0xC5F1, 0xD1F9, 0xB86D, 0xD1FA, 0xB86E, 0xD1FB, 0xB86F,
+ 0xD1FC, 0xB870, 0xD1FD, 0xB871, 0xD1FE, 0xB872, 0xD1FF, 0xB873, 0xD200, 0xB874, 0xD201, 0xB875, 0xD202, 0xB876, 0xD203, 0xB877,
+ 0xD204, 0xB878, 0xD205, 0xB879, 0xD206, 0xB87A, 0xD207, 0xC5F2, 0xD208, 0xB881, 0xD209, 0xC5F3, 0xD20A, 0xB882, 0xD20B, 0xB883,
+ 0xD20C, 0xB884, 0xD20D, 0xB885, 0xD20E, 0xB886, 0xD20F, 0xB887, 0xD210, 0xC5F4, 0xD211, 0xB888, 0xD212, 0xB889, 0xD213, 0xB88A,
+ 0xD214, 0xB88B, 0xD215, 0xB88C, 0xD216, 0xB88D, 0xD217, 0xB88E, 0xD218, 0xB88F, 0xD219, 0xB890, 0xD21A, 0xB891, 0xD21B, 0xB892,
+ 0xD21C, 0xB893, 0xD21D, 0xB894, 0xD21E, 0xB895, 0xD21F, 0xB896, 0xD220, 0xB897, 0xD221, 0xB898, 0xD222, 0xB899, 0xD223, 0xB89A,
+ 0xD224, 0xB89B, 0xD225, 0xB89C, 0xD226, 0xB89D, 0xD227, 0xB89E, 0xD228, 0xB89F, 0xD229, 0xB8A0, 0xD22A, 0xB941, 0xD22B, 0xB942,
+ 0xD22C, 0xC5F5, 0xD22D, 0xC5F6, 0xD22E, 0xB943, 0xD22F, 0xB944, 0xD230, 0xC5F7, 0xD231, 0xB945, 0xD232, 0xB946, 0xD233, 0xB947,
+ 0xD234, 0xC5F8, 0xD235, 0xB948, 0xD236, 0xB949, 0xD237, 0xB94A, 0xD238, 0xB94B, 0xD239, 0xB94C, 0xD23A, 0xB94D, 0xD23B, 0xB94E,
+ 0xD23C, 0xC5F9, 0xD23D, 0xC5FA, 0xD23E, 0xB94F, 0xD23F, 0xC5FB, 0xD240, 0xB950, 0xD241, 0xC5FC, 0xD242, 0xB951, 0xD243, 0xB952,
+ 0xD244, 0xB953, 0xD245, 0xB954, 0xD246, 0xB955, 0xD247, 0xB956, 0xD248, 0xC5FD, 0xD249, 0xB957, 0xD24A, 0xB958, 0xD24B, 0xB959,
+ 0xD24C, 0xB95A, 0xD24D, 0xB961, 0xD24E, 0xB962, 0xD24F, 0xB963, 0xD250, 0xB964, 0xD251, 0xB965, 0xD252, 0xB966, 0xD253, 0xB967,
+ 0xD254, 0xB968, 0xD255, 0xB969, 0xD256, 0xB96A, 0xD257, 0xB96B, 0xD258, 0xB96C, 0xD259, 0xB96D, 0xD25A, 0xB96E, 0xD25B, 0xB96F,
+ 0xD25C, 0xC5FE, 0xD25D, 0xB970, 0xD25E, 0xB971, 0xD25F, 0xB972, 0xD260, 0xB973, 0xD261, 0xB974, 0xD262, 0xB975, 0xD263, 0xB976,
+ 0xD264, 0xC6A1, 0xD265, 0xB977, 0xD266, 0xB978, 0xD267, 0xB979, 0xD268, 0xB97A, 0xD269, 0xB981, 0xD26A, 0xB982, 0xD26B, 0xB983,
+ 0xD26C, 0xB984, 0xD26D, 0xB985, 0xD26E, 0xB986, 0xD26F, 0xB987, 0xD270, 0xB988, 0xD271, 0xB989, 0xD272, 0xB98A, 0xD273, 0xB98B,
+ 0xD274, 0xB98C, 0xD275, 0xB98D, 0xD276, 0xB98E, 0xD277, 0xB98F, 0xD278, 0xB990, 0xD279, 0xB991, 0xD27A, 0xB992, 0xD27B, 0xB993,
+ 0xD27C, 0xB994, 0xD27D, 0xB995, 0xD27E, 0xB996, 0xD27F, 0xB997, 0xD280, 0xC6A2, 0xD281, 0xC6A3, 0xD282, 0xB998, 0xD283, 0xB999,
+ 0xD284, 0xC6A4, 0xD285, 0xB99A, 0xD286, 0xB99B, 0xD287, 0xB99C, 0xD288, 0xC6A5, 0xD289, 0xB99D, 0xD28A, 0xB99E, 0xD28B, 0xB99F,
+ 0xD28C, 0xB9A0, 0xD28D, 0xBA41, 0xD28E, 0xBA42, 0xD28F, 0xBA43, 0xD290, 0xC6A6, 0xD291, 0xC6A7, 0xD292, 0xBA44, 0xD293, 0xBA45,
+ 0xD294, 0xBA46, 0xD295, 0xC6A8, 0xD296, 0xBA47, 0xD297, 0xBA48, 0xD298, 0xBA49, 0xD299, 0xBA4A, 0xD29A, 0xBA4B, 0xD29B, 0xBA4C,
+ 0xD29C, 0xC6A9, 0xD29D, 0xBA4D, 0xD29E, 0xBA4E, 0xD29F, 0xBA4F, 0xD2A0, 0xC6AA, 0xD2A1, 0xBA50, 0xD2A2, 0xBA51, 0xD2A3, 0xBA52,
+ 0xD2A4, 0xC6AB, 0xD2A5, 0xBA53, 0xD2A6, 0xBA54, 0xD2A7, 0xBA55, 0xD2A8, 0xBA56, 0xD2A9, 0xBA57, 0xD2AA, 0xBA58, 0xD2AB, 0xBA59,
+ 0xD2AC, 0xC6AC, 0xD2AD, 0xBA5A, 0xD2AE, 0xBA61, 0xD2AF, 0xBA62, 0xD2B0, 0xBA63, 0xD2B1, 0xC6AD, 0xD2B2, 0xBA64, 0xD2B3, 0xBA65,
+ 0xD2B4, 0xBA66, 0xD2B5, 0xBA67, 0xD2B6, 0xBA68, 0xD2B7, 0xBA69, 0xD2B8, 0xC6AE, 0xD2B9, 0xC6AF, 0xD2BA, 0xBA6A, 0xD2BB, 0xBA6B,
+ 0xD2BC, 0xC6B0, 0xD2BD, 0xBA6C, 0xD2BE, 0xBA6D, 0xD2BF, 0xC6B1, 0xD2C0, 0xC6B2, 0xD2C1, 0xBA6E, 0xD2C2, 0xC6B3, 0xD2C3, 0xBA6F,
+ 0xD2C4, 0xBA70, 0xD2C5, 0xBA71, 0xD2C6, 0xBA72, 0xD2C7, 0xBA73, 0xD2C8, 0xC6B4, 0xD2C9, 0xC6B5, 0xD2CA, 0xBA74, 0xD2CB, 0xC6B6,
+ 0xD2CC, 0xBA75, 0xD2CD, 0xBA76, 0xD2CE, 0xBA77, 0xD2CF, 0xBA78, 0xD2D0, 0xBA79, 0xD2D1, 0xBA7A, 0xD2D2, 0xBA81, 0xD2D3, 0xBA82,
+ 0xD2D4, 0xC6B7, 0xD2D5, 0xBA83, 0xD2D6, 0xBA84, 0xD2D7, 0xBA85, 0xD2D8, 0xC6B8, 0xD2D9, 0xBA86, 0xD2DA, 0xBA87, 0xD2DB, 0xBA88,
+ 0xD2DC, 0xC6B9, 0xD2DD, 0xBA89, 0xD2DE, 0xBA8A, 0xD2DF, 0xBA8B, 0xD2E0, 0xBA8C, 0xD2E1, 0xBA8D, 0xD2E2, 0xBA8E, 0xD2E3, 0xBA8F,
+ 0xD2E4, 0xC6BA, 0xD2E5, 0xC6BB, 0xD2E6, 0xBA90, 0xD2E7, 0xBA91, 0xD2E8, 0xBA92, 0xD2E9, 0xBA93, 0xD2EA, 0xBA94, 0xD2EB, 0xBA95,
+ 0xD2EC, 0xBA96, 0xD2ED, 0xBA97, 0xD2EE, 0xBA98, 0xD2EF, 0xBA99, 0xD2F0, 0xC6BC, 0xD2F1, 0xC6BD, 0xD2F2, 0xBA9A, 0xD2F3, 0xBA9B,
+ 0xD2F4, 0xC6BE, 0xD2F5, 0xBA9C, 0xD2F6, 0xBA9D, 0xD2F7, 0xBA9E, 0xD2F8, 0xC6BF, 0xD2F9, 0xBA9F, 0xD2FA, 0xBAA0, 0xD2FB, 0xBB41,
+ 0xD2FC, 0xBB42, 0xD2FD, 0xBB43, 0xD2FE, 0xBB44, 0xD2FF, 0xBB45, 0xD300, 0xC6C0, 0xD301, 0xC6C1, 0xD302, 0xBB46, 0xD303, 0xC6C2,
+ 0xD304, 0xBB47, 0xD305, 0xC6C3, 0xD306, 0xBB48, 0xD307, 0xBB49, 0xD308, 0xBB4A, 0xD309, 0xBB4B, 0xD30A, 0xBB4C, 0xD30B, 0xBB4D,
+ 0xD30C, 0xC6C4, 0xD30D, 0xC6C5, 0xD30E, 0xC6C6, 0xD30F, 0xBB4E, 0xD310, 0xC6C7, 0xD311, 0xBB4F, 0xD312, 0xBB50, 0xD313, 0xBB51,
+ 0xD314, 0xC6C8, 0xD315, 0xBB52, 0xD316, 0xC6C9, 0xD317, 0xBB53, 0xD318, 0xBB54, 0xD319, 0xBB55, 0xD31A, 0xBB56, 0xD31B, 0xBB57,
+ 0xD31C, 0xC6CA, 0xD31D, 0xC6CB, 0xD31E, 0xBB58, 0xD31F, 0xC6CC, 0xD320, 0xC6CD, 0xD321, 0xC6CE, 0xD322, 0xBB59, 0xD323, 0xBB5A,
+ 0xD324, 0xBB61, 0xD325, 0xC6CF, 0xD326, 0xBB62, 0xD327, 0xBB63, 0xD328, 0xC6D0, 0xD329, 0xC6D1, 0xD32A, 0xBB64, 0xD32B, 0xBB65,
+ 0xD32C, 0xC6D2, 0xD32D, 0xBB66, 0xD32E, 0xBB67, 0xD32F, 0xBB68, 0xD330, 0xC6D3, 0xD331, 0xBB69, 0xD332, 0xBB6A, 0xD333, 0xBB6B,
+ 0xD334, 0xBB6C, 0xD335, 0xBB6D, 0xD336, 0xBB6E, 0xD337, 0xBB6F, 0xD338, 0xC6D4, 0xD339, 0xC6D5, 0xD33A, 0xBB70, 0xD33B, 0xC6D6,
+ 0xD33C, 0xC6D7, 0xD33D, 0xC6D8, 0xD33E, 0xBB71, 0xD33F, 0xBB72, 0xD340, 0xBB73, 0xD341, 0xBB74, 0xD342, 0xBB75, 0xD343, 0xBB76,
+ 0xD344, 0xC6D9, 0xD345, 0xC6DA, 0xD346, 0xBB77, 0xD347, 0xBB78, 0xD348, 0xBB79, 0xD349, 0xBB7A, 0xD34A, 0xBB81, 0xD34B, 0xBB82,
+ 0xD34C, 0xBB83, 0xD34D, 0xBB84, 0xD34E, 0xBB85, 0xD34F, 0xBB86, 0xD350, 0xBB87, 0xD351, 0xBB88, 0xD352, 0xBB89, 0xD353, 0xBB8A,
+ 0xD354, 0xBB8B, 0xD355, 0xBB8C, 0xD356, 0xBB8D, 0xD357, 0xBB8E, 0xD358, 0xBB8F, 0xD359, 0xBB90, 0xD35A, 0xBB91, 0xD35B, 0xBB92,
+ 0xD35C, 0xBB93, 0xD35D, 0xBB94, 0xD35E, 0xBB95, 0xD35F, 0xBB96, 0xD360, 0xBB97, 0xD361, 0xBB98, 0xD362, 0xBB99, 0xD363, 0xBB9A,
+ 0xD364, 0xBB9B, 0xD365, 0xBB9C, 0xD366, 0xBB9D, 0xD367, 0xBB9E, 0xD368, 0xBB9F, 0xD369, 0xBBA0, 0xD36A, 0xBC41, 0xD36B, 0xBC42,
+ 0xD36C, 0xBC43, 0xD36D, 0xBC44, 0xD36E, 0xBC45, 0xD36F, 0xBC46, 0xD370, 0xBC47, 0xD371, 0xBC48, 0xD372, 0xBC49, 0xD373, 0xBC4A,
+ 0xD374, 0xBC4B, 0xD375, 0xBC4C, 0xD376, 0xBC4D, 0xD377, 0xBC4E, 0xD378, 0xBC4F, 0xD379, 0xBC50, 0xD37A, 0xBC51, 0xD37B, 0xBC52,
+ 0xD37C, 0xC6DB, 0xD37D, 0xC6DC, 0xD37E, 0xBC53, 0xD37F, 0xBC54, 0xD380, 0xC6DD, 0xD381, 0xBC55, 0xD382, 0xBC56, 0xD383, 0xBC57,
+ 0xD384, 0xC6DE, 0xD385, 0xBC58, 0xD386, 0xBC59, 0xD387, 0xBC5A, 0xD388, 0xBC61, 0xD389, 0xBC62, 0xD38A, 0xBC63, 0xD38B, 0xBC64,
+ 0xD38C, 0xC6DF, 0xD38D, 0xC6E0, 0xD38E, 0xBC65, 0xD38F, 0xC6E1, 0xD390, 0xC6E2, 0xD391, 0xC6E3, 0xD392, 0xBC66, 0xD393, 0xBC67,
+ 0xD394, 0xBC68, 0xD395, 0xBC69, 0xD396, 0xBC6A, 0xD397, 0xBC6B, 0xD398, 0xC6E4, 0xD399, 0xC6E5, 0xD39A, 0xBC6C, 0xD39B, 0xBC6D,
+ 0xD39C, 0xC6E6, 0xD39D, 0xBC6E, 0xD39E, 0xBC6F, 0xD39F, 0xBC70, 0xD3A0, 0xC6E7, 0xD3A1, 0xBC71, 0xD3A2, 0xBC72, 0xD3A3, 0xBC73,
+ 0xD3A4, 0xBC74, 0xD3A5, 0xBC75, 0xD3A6, 0xBC76, 0xD3A7, 0xBC77, 0xD3A8, 0xC6E8, 0xD3A9, 0xC6E9, 0xD3AA, 0xBC78, 0xD3AB, 0xC6EA,
+ 0xD3AC, 0xBC79, 0xD3AD, 0xC6EB, 0xD3AE, 0xBC7A, 0xD3AF, 0xBC81, 0xD3B0, 0xBC82, 0xD3B1, 0xBC83, 0xD3B2, 0xBC84, 0xD3B3, 0xBC85,
+ 0xD3B4, 0xC6EC, 0xD3B5, 0xBC86, 0xD3B6, 0xBC87, 0xD3B7, 0xBC88, 0xD3B8, 0xC6ED, 0xD3B9, 0xBC89, 0xD3BA, 0xBC8A, 0xD3BB, 0xBC8B,
+ 0xD3BC, 0xC6EE, 0xD3BD, 0xBC8C, 0xD3BE, 0xBC8D, 0xD3BF, 0xBC8E, 0xD3C0, 0xBC8F, 0xD3C1, 0xBC90, 0xD3C2, 0xBC91, 0xD3C3, 0xBC92,
+ 0xD3C4, 0xC6EF, 0xD3C5, 0xC6F0, 0xD3C6, 0xBC93, 0xD3C7, 0xBC94, 0xD3C8, 0xC6F1, 0xD3C9, 0xC6F2, 0xD3CA, 0xBC95, 0xD3CB, 0xBC96,
+ 0xD3CC, 0xBC97, 0xD3CD, 0xBC98, 0xD3CE, 0xBC99, 0xD3CF, 0xBC9A, 0xD3D0, 0xC6F3, 0xD3D1, 0xBC9B, 0xD3D2, 0xBC9C, 0xD3D3, 0xBC9D,
+ 0xD3D4, 0xBC9E, 0xD3D5, 0xBC9F, 0xD3D6, 0xBCA0, 0xD3D7, 0xBD41, 0xD3D8, 0xC6F4, 0xD3D9, 0xBD42, 0xD3DA, 0xBD43, 0xD3DB, 0xBD44,
+ 0xD3DC, 0xBD45, 0xD3DD, 0xBD46, 0xD3DE, 0xBD47, 0xD3DF, 0xBD48, 0xD3E0, 0xBD49, 0xD3E1, 0xC6F5, 0xD3E2, 0xBD4A, 0xD3E3, 0xC6F6,
+ 0xD3E4, 0xBD4B, 0xD3E5, 0xBD4C, 0xD3E6, 0xBD4D, 0xD3E7, 0xBD4E, 0xD3E8, 0xBD4F, 0xD3E9, 0xBD50, 0xD3EA, 0xBD51, 0xD3EB, 0xBD52,
+ 0xD3EC, 0xC6F7, 0xD3ED, 0xC6F8, 0xD3EE, 0xBD53, 0xD3EF, 0xBD54, 0xD3F0, 0xC6F9, 0xD3F1, 0xBD55, 0xD3F2, 0xBD56, 0xD3F3, 0xBD57,
+ 0xD3F4, 0xC6FA, 0xD3F5, 0xBD58, 0xD3F6, 0xBD59, 0xD3F7, 0xBD5A, 0xD3F8, 0xBD61, 0xD3F9, 0xBD62, 0xD3FA, 0xBD63, 0xD3FB, 0xBD64,
+ 0xD3FC, 0xC6FB, 0xD3FD, 0xC6FC, 0xD3FE, 0xBD65, 0xD3FF, 0xC6FD, 0xD400, 0xBD66, 0xD401, 0xC6FE, 0xD402, 0xBD67, 0xD403, 0xBD68,
+ 0xD404, 0xBD69, 0xD405, 0xBD6A, 0xD406, 0xBD6B, 0xD407, 0xBD6C, 0xD408, 0xC7A1, 0xD409, 0xBD6D, 0xD40A, 0xBD6E, 0xD40B, 0xBD6F,
+ 0xD40C, 0xBD70, 0xD40D, 0xBD71, 0xD40E, 0xBD72, 0xD40F, 0xBD73, 0xD410, 0xBD74, 0xD411, 0xBD75, 0xD412, 0xBD76, 0xD413, 0xBD77,
+ 0xD414, 0xBD78, 0xD415, 0xBD79, 0xD416, 0xBD7A, 0xD417, 0xBD81, 0xD418, 0xBD82, 0xD419, 0xBD83, 0xD41A, 0xBD84, 0xD41B, 0xBD85,
+ 0xD41C, 0xBD86, 0xD41D, 0xC7A2, 0xD41E, 0xBD87, 0xD41F, 0xBD88, 0xD420, 0xBD89, 0xD421, 0xBD8A, 0xD422, 0xBD8B, 0xD423, 0xBD8C,
+ 0xD424, 0xBD8D, 0xD425, 0xBD8E, 0xD426, 0xBD8F, 0xD427, 0xBD90, 0xD428, 0xBD91, 0xD429, 0xBD92, 0xD42A, 0xBD93, 0xD42B, 0xBD94,
+ 0xD42C, 0xBD95, 0xD42D, 0xBD96, 0xD42E, 0xBD97, 0xD42F, 0xBD98, 0xD430, 0xBD99, 0xD431, 0xBD9A, 0xD432, 0xBD9B, 0xD433, 0xBD9C,
+ 0xD434, 0xBD9D, 0xD435, 0xBD9E, 0xD436, 0xBD9F, 0xD437, 0xBDA0, 0xD438, 0xBE41, 0xD439, 0xBE42, 0xD43A, 0xBE43, 0xD43B, 0xBE44,
+ 0xD43C, 0xBE45, 0xD43D, 0xBE46, 0xD43E, 0xBE47, 0xD43F, 0xBE48, 0xD440, 0xC7A3, 0xD441, 0xBE49, 0xD442, 0xBE4A, 0xD443, 0xBE4B,
+ 0xD444, 0xC7A4, 0xD445, 0xBE4C, 0xD446, 0xBE4D, 0xD447, 0xBE4E, 0xD448, 0xBE4F, 0xD449, 0xBE50, 0xD44A, 0xBE51, 0xD44B, 0xBE52,
+ 0xD44C, 0xBE53, 0xD44D, 0xBE54, 0xD44E, 0xBE55, 0xD44F, 0xBE56, 0xD450, 0xBE57, 0xD451, 0xBE58, 0xD452, 0xBE59, 0xD453, 0xBE5A,
+ 0xD454, 0xBE61, 0xD455, 0xBE62, 0xD456, 0xBE63, 0xD457, 0xBE64, 0xD458, 0xBE65, 0xD459, 0xBE66, 0xD45A, 0xBE67, 0xD45B, 0xBE68,
+ 0xD45C, 0xC7A5, 0xD45D, 0xBE69, 0xD45E, 0xBE6A, 0xD45F, 0xBE6B, 0xD460, 0xC7A6, 0xD461, 0xBE6C, 0xD462, 0xBE6D, 0xD463, 0xBE6E,
+ 0xD464, 0xC7A7, 0xD465, 0xBE6F, 0xD466, 0xBE70, 0xD467, 0xBE71, 0xD468, 0xBE72, 0xD469, 0xBE73, 0xD46A, 0xBE74, 0xD46B, 0xBE75,
+ 0xD46C, 0xBE76, 0xD46D, 0xC7A8, 0xD46E, 0xBE77, 0xD46F, 0xC7A9, 0xD470, 0xBE78, 0xD471, 0xBE79, 0xD472, 0xBE7A, 0xD473, 0xBE81,
+ 0xD474, 0xBE82, 0xD475, 0xBE83, 0xD476, 0xBE84, 0xD477, 0xBE85, 0xD478, 0xC7AA, 0xD479, 0xC7AB, 0xD47A, 0xBE86, 0xD47B, 0xBE87,
+ 0xD47C, 0xC7AC, 0xD47D, 0xBE88, 0xD47E, 0xBE89, 0xD47F, 0xC7AD, 0xD480, 0xC7AE, 0xD481, 0xBE8A, 0xD482, 0xC7AF, 0xD483, 0xBE8B,
+ 0xD484, 0xBE8C, 0xD485, 0xBE8D, 0xD486, 0xBE8E, 0xD487, 0xBE8F, 0xD488, 0xC7B0, 0xD489, 0xC7B1, 0xD48A, 0xBE90, 0xD48B, 0xC7B2,
+ 0xD48C, 0xBE91, 0xD48D, 0xC7B3, 0xD48E, 0xBE92, 0xD48F, 0xBE93, 0xD490, 0xBE94, 0xD491, 0xBE95, 0xD492, 0xBE96, 0xD493, 0xBE97,
+ 0xD494, 0xC7B4, 0xD495, 0xBE98, 0xD496, 0xBE99, 0xD497, 0xBE9A, 0xD498, 0xBE9B, 0xD499, 0xBE9C, 0xD49A, 0xBE9D, 0xD49B, 0xBE9E,
+ 0xD49C, 0xBE9F, 0xD49D, 0xBEA0, 0xD49E, 0xBF41, 0xD49F, 0xBF42, 0xD4A0, 0xBF43, 0xD4A1, 0xBF44, 0xD4A2, 0xBF45, 0xD4A3, 0xBF46,
+ 0xD4A4, 0xBF47, 0xD4A5, 0xBF48, 0xD4A6, 0xBF49, 0xD4A7, 0xBF4A, 0xD4A8, 0xBF4B, 0xD4A9, 0xC7B5, 0xD4AA, 0xBF4C, 0xD4AB, 0xBF4D,
+ 0xD4AC, 0xBF4E, 0xD4AD, 0xBF4F, 0xD4AE, 0xBF50, 0xD4AF, 0xBF51, 0xD4B0, 0xBF52, 0xD4B1, 0xBF53, 0xD4B2, 0xBF54, 0xD4B3, 0xBF55,
+ 0xD4B4, 0xBF56, 0xD4B5, 0xBF57, 0xD4B6, 0xBF58, 0xD4B7, 0xBF59, 0xD4B8, 0xBF5A, 0xD4B9, 0xBF61, 0xD4BA, 0xBF62, 0xD4BB, 0xBF63,
+ 0xD4BC, 0xBF64, 0xD4BD, 0xBF65, 0xD4BE, 0xBF66, 0xD4BF, 0xBF67, 0xD4C0, 0xBF68, 0xD4C1, 0xBF69, 0xD4C2, 0xBF6A, 0xD4C3, 0xBF6B,
+ 0xD4C4, 0xBF6C, 0xD4C5, 0xBF6D, 0xD4C6, 0xBF6E, 0xD4C7, 0xBF6F, 0xD4C8, 0xBF70, 0xD4C9, 0xBF71, 0xD4CA, 0xBF72, 0xD4CB, 0xBF73,
+ 0xD4CC, 0xC7B6, 0xD4CD, 0xBF74, 0xD4CE, 0xBF75, 0xD4CF, 0xBF76, 0xD4D0, 0xC7B7, 0xD4D1, 0xBF77, 0xD4D2, 0xBF78, 0xD4D3, 0xBF79,
+ 0xD4D4, 0xC7B8, 0xD4D5, 0xBF7A, 0xD4D6, 0xBF81, 0xD4D7, 0xBF82, 0xD4D8, 0xBF83, 0xD4D9, 0xBF84, 0xD4DA, 0xBF85, 0xD4DB, 0xBF86,
+ 0xD4DC, 0xC7B9, 0xD4DD, 0xBF87, 0xD4DE, 0xBF88, 0xD4DF, 0xC7BA, 0xD4E0, 0xBF89, 0xD4E1, 0xBF8A, 0xD4E2, 0xBF8B, 0xD4E3, 0xBF8C,
+ 0xD4E4, 0xBF8D, 0xD4E5, 0xBF8E, 0xD4E6, 0xBF8F, 0xD4E7, 0xBF90, 0xD4E8, 0xC7BB, 0xD4E9, 0xBF91, 0xD4EA, 0xBF92, 0xD4EB, 0xBF93,
+ 0xD4EC, 0xC7BC, 0xD4ED, 0xBF94, 0xD4EE, 0xBF95, 0xD4EF, 0xBF96, 0xD4F0, 0xC7BD, 0xD4F1, 0xBF97, 0xD4F2, 0xBF98, 0xD4F3, 0xBF99,
+ 0xD4F4, 0xBF9A, 0xD4F5, 0xBF9B, 0xD4F6, 0xBF9C, 0xD4F7, 0xBF9D, 0xD4F8, 0xC7BE, 0xD4F9, 0xBF9E, 0xD4FA, 0xBF9F, 0xD4FB, 0xC7BF,
+ 0xD4FC, 0xBFA0, 0xD4FD, 0xC7C0, 0xD4FE, 0xC041, 0xD4FF, 0xC042, 0xD500, 0xC043, 0xD501, 0xC044, 0xD502, 0xC045, 0xD503, 0xC046,
+ 0xD504, 0xC7C1, 0xD505, 0xC047, 0xD506, 0xC048, 0xD507, 0xC049, 0xD508, 0xC7C2, 0xD509, 0xC04A, 0xD50A, 0xC04B, 0xD50B, 0xC04C,
+ 0xD50C, 0xC7C3, 0xD50D, 0xC04D, 0xD50E, 0xC04E, 0xD50F, 0xC04F, 0xD510, 0xC050, 0xD511, 0xC051, 0xD512, 0xC052, 0xD513, 0xC053,
+ 0xD514, 0xC7C4, 0xD515, 0xC7C5, 0xD516, 0xC054, 0xD517, 0xC7C6, 0xD518, 0xC055, 0xD519, 0xC056, 0xD51A, 0xC057, 0xD51B, 0xC058,
+ 0xD51C, 0xC059, 0xD51D, 0xC05A, 0xD51E, 0xC061, 0xD51F, 0xC062, 0xD520, 0xC063, 0xD521, 0xC064, 0xD522, 0xC065, 0xD523, 0xC066,
+ 0xD524, 0xC067, 0xD525, 0xC068, 0xD526, 0xC069, 0xD527, 0xC06A, 0xD528, 0xC06B, 0xD529, 0xC06C, 0xD52A, 0xC06D, 0xD52B, 0xC06E,
+ 0xD52C, 0xC06F, 0xD52D, 0xC070, 0xD52E, 0xC071, 0xD52F, 0xC072, 0xD530, 0xC073, 0xD531, 0xC074, 0xD532, 0xC075, 0xD533, 0xC076,
+ 0xD534, 0xC077, 0xD535, 0xC078, 0xD536, 0xC079, 0xD537, 0xC07A, 0xD538, 0xC081, 0xD539, 0xC082, 0xD53A, 0xC083, 0xD53B, 0xC084,
+ 0xD53C, 0xC7C7, 0xD53D, 0xC7C8, 0xD53E, 0xC085, 0xD53F, 0xC086, 0xD540, 0xC7C9, 0xD541, 0xC087, 0xD542, 0xC088, 0xD543, 0xC089,
+ 0xD544, 0xC7CA, 0xD545, 0xC08A, 0xD546, 0xC08B, 0xD547, 0xC08C, 0xD548, 0xC08D, 0xD549, 0xC08E, 0xD54A, 0xC08F, 0xD54B, 0xC090,
+ 0xD54C, 0xC7CB, 0xD54D, 0xC7CC, 0xD54E, 0xC091, 0xD54F, 0xC7CD, 0xD550, 0xC092, 0xD551, 0xC7CE, 0xD552, 0xC093, 0xD553, 0xC094,
+ 0xD554, 0xC095, 0xD555, 0xC096, 0xD556, 0xC097, 0xD557, 0xC098, 0xD558, 0xC7CF, 0xD559, 0xC7D0, 0xD55A, 0xC099, 0xD55B, 0xC09A,
+ 0xD55C, 0xC7D1, 0xD55D, 0xC09B, 0xD55E, 0xC09C, 0xD55F, 0xC09D, 0xD560, 0xC7D2, 0xD561, 0xC09E, 0xD562, 0xC09F, 0xD563, 0xC0A0,
+ 0xD564, 0xC141, 0xD565, 0xC7D3, 0xD566, 0xC142, 0xD567, 0xC143, 0xD568, 0xC7D4, 0xD569, 0xC7D5, 0xD56A, 0xC144, 0xD56B, 0xC7D6,
+ 0xD56C, 0xC145, 0xD56D, 0xC7D7, 0xD56E, 0xC146, 0xD56F, 0xC147, 0xD570, 0xC148, 0xD571, 0xC149, 0xD572, 0xC14A, 0xD573, 0xC14B,
+ 0xD574, 0xC7D8, 0xD575, 0xC7D9, 0xD576, 0xC14C, 0xD577, 0xC14D, 0xD578, 0xC7DA, 0xD579, 0xC14E, 0xD57A, 0xC14F, 0xD57B, 0xC150,
+ 0xD57C, 0xC7DB, 0xD57D, 0xC151, 0xD57E, 0xC152, 0xD57F, 0xC153, 0xD580, 0xC154, 0xD581, 0xC155, 0xD582, 0xC156, 0xD583, 0xC157,
+ 0xD584, 0xC7DC, 0xD585, 0xC7DD, 0xD586, 0xC158, 0xD587, 0xC7DE, 0xD588, 0xC7DF, 0xD589, 0xC7E0, 0xD58A, 0xC159, 0xD58B, 0xC15A,
+ 0xD58C, 0xC161, 0xD58D, 0xC162, 0xD58E, 0xC163, 0xD58F, 0xC164, 0xD590, 0xC7E1, 0xD591, 0xC165, 0xD592, 0xC166, 0xD593, 0xC167,
+ 0xD594, 0xC168, 0xD595, 0xC169, 0xD596, 0xC16A, 0xD597, 0xC16B, 0xD598, 0xC16C, 0xD599, 0xC16D, 0xD59A, 0xC16E, 0xD59B, 0xC16F,
+ 0xD59C, 0xC170, 0xD59D, 0xC171, 0xD59E, 0xC172, 0xD59F, 0xC173, 0xD5A0, 0xC174, 0xD5A1, 0xC175, 0xD5A2, 0xC176, 0xD5A3, 0xC177,
+ 0xD5A4, 0xC178, 0xD5A5, 0xC7E2, 0xD5A6, 0xC179, 0xD5A7, 0xC17A, 0xD5A8, 0xC181, 0xD5A9, 0xC182, 0xD5AA, 0xC183, 0xD5AB, 0xC184,
+ 0xD5AC, 0xC185, 0xD5AD, 0xC186, 0xD5AE, 0xC187, 0xD5AF, 0xC188, 0xD5B0, 0xC189, 0xD5B1, 0xC18A, 0xD5B2, 0xC18B, 0xD5B3, 0xC18C,
+ 0xD5B4, 0xC18D, 0xD5B5, 0xC18E, 0xD5B6, 0xC18F, 0xD5B7, 0xC190, 0xD5B8, 0xC191, 0xD5B9, 0xC192, 0xD5BA, 0xC193, 0xD5BB, 0xC194,
+ 0xD5BC, 0xC195, 0xD5BD, 0xC196, 0xD5BE, 0xC197, 0xD5BF, 0xC198, 0xD5C0, 0xC199, 0xD5C1, 0xC19A, 0xD5C2, 0xC19B, 0xD5C3, 0xC19C,
+ 0xD5C4, 0xC19D, 0xD5C5, 0xC19E, 0xD5C6, 0xC19F, 0xD5C7, 0xC1A0, 0xD5C8, 0xC7E3, 0xD5C9, 0xC7E4, 0xD5CA, 0xC241, 0xD5CB, 0xC242,
+ 0xD5CC, 0xC7E5, 0xD5CD, 0xC243, 0xD5CE, 0xC244, 0xD5CF, 0xC245, 0xD5D0, 0xC7E6, 0xD5D1, 0xC246, 0xD5D2, 0xC7E7, 0xD5D3, 0xC247,
+ 0xD5D4, 0xC248, 0xD5D5, 0xC249, 0xD5D6, 0xC24A, 0xD5D7, 0xC24B, 0xD5D8, 0xC7E8, 0xD5D9, 0xC7E9, 0xD5DA, 0xC24C, 0xD5DB, 0xC7EA,
+ 0xD5DC, 0xC24D, 0xD5DD, 0xC7EB, 0xD5DE, 0xC24E, 0xD5DF, 0xC24F, 0xD5E0, 0xC250, 0xD5E1, 0xC251, 0xD5E2, 0xC252, 0xD5E3, 0xC253,
+ 0xD5E4, 0xC7EC, 0xD5E5, 0xC7ED, 0xD5E6, 0xC254, 0xD5E7, 0xC255, 0xD5E8, 0xC7EE, 0xD5E9, 0xC256, 0xD5EA, 0xC257, 0xD5EB, 0xC258,
+ 0xD5EC, 0xC7EF, 0xD5ED, 0xC259, 0xD5EE, 0xC25A, 0xD5EF, 0xC261, 0xD5F0, 0xC262, 0xD5F1, 0xC263, 0xD5F2, 0xC264, 0xD5F3, 0xC265,
+ 0xD5F4, 0xC7F0, 0xD5F5, 0xC7F1, 0xD5F6, 0xC266, 0xD5F7, 0xC7F2, 0xD5F8, 0xC267, 0xD5F9, 0xC7F3, 0xD5FA, 0xC268, 0xD5FB, 0xC269,
+ 0xD5FC, 0xC26A, 0xD5FD, 0xC26B, 0xD5FE, 0xC26C, 0xD5FF, 0xC26D, 0xD600, 0xC7F4, 0xD601, 0xC7F5, 0xD602, 0xC26E, 0xD603, 0xC26F,
+ 0xD604, 0xC7F6, 0xD605, 0xC270, 0xD606, 0xC271, 0xD607, 0xC272, 0xD608, 0xC7F7, 0xD609, 0xC273, 0xD60A, 0xC274, 0xD60B, 0xC275,
+ 0xD60C, 0xC276, 0xD60D, 0xC277, 0xD60E, 0xC278, 0xD60F, 0xC279, 0xD610, 0xC7F8, 0xD611, 0xC7F9, 0xD612, 0xC27A, 0xD613, 0xC7FA,
+ 0xD614, 0xC7FB, 0xD615, 0xC7FC, 0xD616, 0xC281, 0xD617, 0xC282, 0xD618, 0xC283, 0xD619, 0xC284, 0xD61A, 0xC285, 0xD61B, 0xC286,
+ 0xD61C, 0xC7FD, 0xD61D, 0xC287, 0xD61E, 0xC288, 0xD61F, 0xC289, 0xD620, 0xC7FE, 0xD621, 0xC28A, 0xD622, 0xC28B, 0xD623, 0xC28C,
+ 0xD624, 0xC8A1, 0xD625, 0xC28D, 0xD626, 0xC28E, 0xD627, 0xC28F, 0xD628, 0xC290, 0xD629, 0xC291, 0xD62A, 0xC292, 0xD62B, 0xC293,
+ 0xD62C, 0xC294, 0xD62D, 0xC8A2, 0xD62E, 0xC295, 0xD62F, 0xC296, 0xD630, 0xC297, 0xD631, 0xC298, 0xD632, 0xC299, 0xD633, 0xC29A,
+ 0xD634, 0xC29B, 0xD635, 0xC29C, 0xD636, 0xC29D, 0xD637, 0xC29E, 0xD638, 0xC8A3, 0xD639, 0xC8A4, 0xD63A, 0xC29F, 0xD63B, 0xC2A0,
+ 0xD63C, 0xC8A5, 0xD63D, 0xC341, 0xD63E, 0xC342, 0xD63F, 0xC343, 0xD640, 0xC8A6, 0xD641, 0xC344, 0xD642, 0xC345, 0xD643, 0xC346,
+ 0xD644, 0xC347, 0xD645, 0xC8A7, 0xD646, 0xC348, 0xD647, 0xC349, 0xD648, 0xC8A8, 0xD649, 0xC8A9, 0xD64A, 0xC34A, 0xD64B, 0xC8AA,
+ 0xD64C, 0xC34B, 0xD64D, 0xC8AB, 0xD64E, 0xC34C, 0xD64F, 0xC34D, 0xD650, 0xC34E, 0xD651, 0xC8AC, 0xD652, 0xC34F, 0xD653, 0xC350,
+ 0xD654, 0xC8AD, 0xD655, 0xC8AE, 0xD656, 0xC351, 0xD657, 0xC352, 0xD658, 0xC8AF, 0xD659, 0xC353, 0xD65A, 0xC354, 0xD65B, 0xC355,
+ 0xD65C, 0xC8B0, 0xD65D, 0xC356, 0xD65E, 0xC357, 0xD65F, 0xC358, 0xD660, 0xC359, 0xD661, 0xC35A, 0xD662, 0xC361, 0xD663, 0xC362,
+ 0xD664, 0xC363, 0xD665, 0xC364, 0xD666, 0xC365, 0xD667, 0xC8B1, 0xD668, 0xC366, 0xD669, 0xC8B2, 0xD66A, 0xC367, 0xD66B, 0xC368,
+ 0xD66C, 0xC369, 0xD66D, 0xC36A, 0xD66E, 0xC36B, 0xD66F, 0xC36C, 0xD670, 0xC8B3, 0xD671, 0xC8B4, 0xD672, 0xC36D, 0xD673, 0xC36E,
+ 0xD674, 0xC8B5, 0xD675, 0xC36F, 0xD676, 0xC370, 0xD677, 0xC371, 0xD678, 0xC372, 0xD679, 0xC373, 0xD67A, 0xC374, 0xD67B, 0xC375,
+ 0xD67C, 0xC376, 0xD67D, 0xC377, 0xD67E, 0xC378, 0xD67F, 0xC379, 0xD680, 0xC37A, 0xD681, 0xC381, 0xD682, 0xC382, 0xD683, 0xC8B6,
+ 0xD684, 0xC383, 0xD685, 0xC8B7, 0xD686, 0xC384, 0xD687, 0xC385, 0xD688, 0xC386, 0xD689, 0xC387, 0xD68A, 0xC388, 0xD68B, 0xC389,
+ 0xD68C, 0xC8B8, 0xD68D, 0xC8B9, 0xD68E, 0xC38A, 0xD68F, 0xC38B, 0xD690, 0xC8BA, 0xD691, 0xC38C, 0xD692, 0xC38D, 0xD693, 0xC38E,
+ 0xD694, 0xC8BB, 0xD695, 0xC38F, 0xD696, 0xC390, 0xD697, 0xC391, 0xD698, 0xC392, 0xD699, 0xC393, 0xD69A, 0xC394, 0xD69B, 0xC395,
+ 0xD69C, 0xC396, 0xD69D, 0xC8BC, 0xD69E, 0xC397, 0xD69F, 0xC8BD, 0xD6A0, 0xC398, 0xD6A1, 0xC8BE, 0xD6A2, 0xC399, 0xD6A3, 0xC39A,
+ 0xD6A4, 0xC39B, 0xD6A5, 0xC39C, 0xD6A6, 0xC39D, 0xD6A7, 0xC39E, 0xD6A8, 0xC8BF, 0xD6A9, 0xC39F, 0xD6AA, 0xC3A0, 0xD6AB, 0xC441,
+ 0xD6AC, 0xC8C0, 0xD6AD, 0xC442, 0xD6AE, 0xC443, 0xD6AF, 0xC444, 0xD6B0, 0xC8C1, 0xD6B1, 0xC445, 0xD6B2, 0xC446, 0xD6B3, 0xC447,
+ 0xD6B4, 0xC448, 0xD6B5, 0xC449, 0xD6B6, 0xC44A, 0xD6B7, 0xC44B, 0xD6B8, 0xC44C, 0xD6B9, 0xC8C2, 0xD6BA, 0xC44D, 0xD6BB, 0xC8C3,
+ 0xD6BC, 0xC44E, 0xD6BD, 0xC44F, 0xD6BE, 0xC450, 0xD6BF, 0xC451, 0xD6C0, 0xC452, 0xD6C1, 0xC453, 0xD6C2, 0xC454, 0xD6C3, 0xC455,
+ 0xD6C4, 0xC8C4, 0xD6C5, 0xC8C5, 0xD6C6, 0xC456, 0xD6C7, 0xC457, 0xD6C8, 0xC8C6, 0xD6C9, 0xC458, 0xD6CA, 0xC459, 0xD6CB, 0xC45A,
+ 0xD6CC, 0xC8C7, 0xD6CD, 0xC461, 0xD6CE, 0xC462, 0xD6CF, 0xC463, 0xD6D0, 0xC464, 0xD6D1, 0xC8C8, 0xD6D2, 0xC465, 0xD6D3, 0xC466,
+ 0xD6D4, 0xC8C9, 0xD6D5, 0xC467, 0xD6D6, 0xC468, 0xD6D7, 0xC8CA, 0xD6D8, 0xC469, 0xD6D9, 0xC8CB, 0xD6DA, 0xC46A, 0xD6DB, 0xC46B,
+ 0xD6DC, 0xC46C, 0xD6DD, 0xC46D, 0xD6DE, 0xC46E, 0xD6DF, 0xC46F, 0xD6E0, 0xC8CC, 0xD6E1, 0xC470, 0xD6E2, 0xC471, 0xD6E3, 0xC472,
+ 0xD6E4, 0xC8CD, 0xD6E5, 0xC473, 0xD6E6, 0xC474, 0xD6E7, 0xC475, 0xD6E8, 0xC8CE, 0xD6E9, 0xC476, 0xD6EA, 0xC477, 0xD6EB, 0xC478,
+ 0xD6EC, 0xC479, 0xD6ED, 0xC47A, 0xD6EE, 0xC481, 0xD6EF, 0xC482, 0xD6F0, 0xC8CF, 0xD6F1, 0xC483, 0xD6F2, 0xC484, 0xD6F3, 0xC485,
+ 0xD6F4, 0xC486, 0xD6F5, 0xC8D0, 0xD6F6, 0xC487, 0xD6F7, 0xC488, 0xD6F8, 0xC489, 0xD6F9, 0xC48A, 0xD6FA, 0xC48B, 0xD6FB, 0xC48C,
+ 0xD6FC, 0xC8D1, 0xD6FD, 0xC8D2, 0xD6FE, 0xC48D, 0xD6FF, 0xC48E, 0xD700, 0xC8D3, 0xD701, 0xC48F, 0xD702, 0xC490, 0xD703, 0xC491,
+ 0xD704, 0xC8D4, 0xD705, 0xC492, 0xD706, 0xC493, 0xD707, 0xC494, 0xD708, 0xC495, 0xD709, 0xC496, 0xD70A, 0xC497, 0xD70B, 0xC498,
+ 0xD70C, 0xC499, 0xD70D, 0xC49A, 0xD70E, 0xC49B, 0xD70F, 0xC49C, 0xD710, 0xC49D, 0xD711, 0xC8D5, 0xD712, 0xC49E, 0xD713, 0xC49F,
+ 0xD714, 0xC4A0, 0xD715, 0xC541, 0xD716, 0xC542, 0xD717, 0xC543, 0xD718, 0xC8D6, 0xD719, 0xC8D7, 0xD71A, 0xC544, 0xD71B, 0xC545,
+ 0xD71C, 0xC8D8, 0xD71D, 0xC546, 0xD71E, 0xC547, 0xD71F, 0xC548, 0xD720, 0xC8D9, 0xD721, 0xC549, 0xD722, 0xC54A, 0xD723, 0xC54B,
+ 0xD724, 0xC54C, 0xD725, 0xC54D, 0xD726, 0xC54E, 0xD727, 0xC54F, 0xD728, 0xC8DA, 0xD729, 0xC8DB, 0xD72A, 0xC550, 0xD72B, 0xC8DC,
+ 0xD72C, 0xC551, 0xD72D, 0xC8DD, 0xD72E, 0xC552, 0xD72F, 0xC553, 0xD730, 0xC554, 0xD731, 0xC555, 0xD732, 0xC556, 0xD733, 0xC557,
+ 0xD734, 0xC8DE, 0xD735, 0xC8DF, 0xD736, 0xC558, 0xD737, 0xC559, 0xD738, 0xC8E0, 0xD739, 0xC55A, 0xD73A, 0xC561, 0xD73B, 0xC562,
+ 0xD73C, 0xC8E1, 0xD73D, 0xC563, 0xD73E, 0xC564, 0xD73F, 0xC565, 0xD740, 0xC566, 0xD741, 0xC567, 0xD742, 0xC568, 0xD743, 0xC569,
+ 0xD744, 0xC8E2, 0xD745, 0xC56A, 0xD746, 0xC56B, 0xD747, 0xC8E3, 0xD748, 0xC56C, 0xD749, 0xC8E4, 0xD74A, 0xC56D, 0xD74B, 0xC56E,
+ 0xD74C, 0xC56F, 0xD74D, 0xC570, 0xD74E, 0xC571, 0xD74F, 0xC572, 0xD750, 0xC8E5, 0xD751, 0xC8E6, 0xD752, 0xC573, 0xD753, 0xC574,
+ 0xD754, 0xC8E7, 0xD755, 0xC575, 0xD756, 0xC8E8, 0xD757, 0xC8E9, 0xD758, 0xC8EA, 0xD759, 0xC8EB, 0xD75A, 0xC576, 0xD75B, 0xC577,
+ 0xD75C, 0xC578, 0xD75D, 0xC579, 0xD75E, 0xC57A, 0xD75F, 0xC581, 0xD760, 0xC8EC, 0xD761, 0xC8ED, 0xD762, 0xC582, 0xD763, 0xC8EE,
+ 0xD764, 0xC583, 0xD765, 0xC8EF, 0xD766, 0xC584, 0xD767, 0xC585, 0xD768, 0xC586, 0xD769, 0xC8F0, 0xD76A, 0xC587, 0xD76B, 0xC588,
+ 0xD76C, 0xC8F1, 0xD76D, 0xC589, 0xD76E, 0xC58A, 0xD76F, 0xC58B, 0xD770, 0xC8F2, 0xD771, 0xC58C, 0xD772, 0xC58D, 0xD773, 0xC58E,
+ 0xD774, 0xC8F3, 0xD775, 0xC58F, 0xD776, 0xC590, 0xD777, 0xC591, 0xD778, 0xC592, 0xD779, 0xC593, 0xD77A, 0xC594, 0xD77B, 0xC595,
+ 0xD77C, 0xC8F4, 0xD77D, 0xC8F5, 0xD77E, 0xC596, 0xD77F, 0xC597, 0xD780, 0xC598, 0xD781, 0xC8F6, 0xD782, 0xC599, 0xD783, 0xC59A,
+ 0xD784, 0xC59B, 0xD785, 0xC59C, 0xD786, 0xC59D, 0xD787, 0xC59E, 0xD788, 0xC8F7, 0xD789, 0xC8F8, 0xD78A, 0xC59F, 0xD78B, 0xC5A0,
+ 0xD78C, 0xC8F9, 0xD78D, 0xC641, 0xD78E, 0xC642, 0xD78F, 0xC643, 0xD790, 0xC8FA, 0xD791, 0xC644, 0xD792, 0xC645, 0xD793, 0xC646,
+ 0xD794, 0xC647, 0xD795, 0xC648, 0xD796, 0xC649, 0xD797, 0xC64A, 0xD798, 0xC8FB, 0xD799, 0xC8FC, 0xD79A, 0xC64B, 0xD79B, 0xC8FD,
+ 0xD79C, 0xC64C, 0xD79D, 0xC8FE, 0xD79E, 0xC64D, 0xD79F, 0xC64E, 0xD7A0, 0xC64F, 0xD7A1, 0xC650, 0xD7A2, 0xC651, 0xD7A3, 0xC652,
+ 0xF900, 0xCBD0, 0xF901, 0xCBD6, 0xF902, 0xCBE7, 0xF903, 0xCDCF, 0xF904, 0xCDE8, 0xF905, 0xCEAD, 0xF906, 0xCFFB, 0xF907, 0xD0A2,
+ 0xF908, 0xD0B8, 0xF909, 0xD0D0, 0xF90A, 0xD0DD, 0xF90B, 0xD1D4, 0xF90C, 0xD1D5, 0xF90D, 0xD1D8, 0xF90E, 0xD1DB, 0xF90F, 0xD1DC,
+ 0xF910, 0xD1DD, 0xF911, 0xD1DE, 0xF912, 0xD1DF, 0xF913, 0xD1E0, 0xF914, 0xD1E2, 0xF915, 0xD1E3, 0xF916, 0xD1E4, 0xF917, 0xD1E5,
+ 0xF918, 0xD1E6, 0xF919, 0xD1E8, 0xF91A, 0xD1E9, 0xF91B, 0xD1EA, 0xF91C, 0xD1EB, 0xF91D, 0xD1ED, 0xF91E, 0xD1EF, 0xF91F, 0xD1F0,
+ 0xF920, 0xD1F2, 0xF921, 0xD1F6, 0xF922, 0xD1FA, 0xF923, 0xD1FC, 0xF924, 0xD1FD, 0xF925, 0xD1FE, 0xF926, 0xD2A2, 0xF927, 0xD2A3,
+ 0xF928, 0xD2A7, 0xF929, 0xD2A8, 0xF92A, 0xD2A9, 0xF92B, 0xD2AA, 0xF92C, 0xD2AB, 0xF92D, 0xD2AD, 0xF92E, 0xD2B2, 0xF92F, 0xD2BE,
+ 0xF930, 0xD2C2, 0xF931, 0xD2C3, 0xF932, 0xD2C4, 0xF933, 0xD2C6, 0xF934, 0xD2C7, 0xF935, 0xD2C8, 0xF936, 0xD2C9, 0xF937, 0xD2CA,
+ 0xF938, 0xD2CB, 0xF939, 0xD2CD, 0xF93A, 0xD2CE, 0xF93B, 0xD2CF, 0xF93C, 0xD2D0, 0xF93D, 0xD2D1, 0xF93E, 0xD2D2, 0xF93F, 0xD2D3,
+ 0xF940, 0xD2D4, 0xF941, 0xD2D5, 0xF942, 0xD2D6, 0xF943, 0xD2D7, 0xF944, 0xD2D9, 0xF945, 0xD2DA, 0xF946, 0xD2DE, 0xF947, 0xD2DF,
+ 0xF948, 0xD2E1, 0xF949, 0xD2E2, 0xF94A, 0xD2E4, 0xF94B, 0xD2E5, 0xF94C, 0xD2E6, 0xF94D, 0xD2E7, 0xF94E, 0xD2E8, 0xF94F, 0xD2E9,
+ 0xF950, 0xD2EA, 0xF951, 0xD2EB, 0xF952, 0xD2F0, 0xF953, 0xD2F1, 0xF954, 0xD2F2, 0xF955, 0xD2F3, 0xF956, 0xD2F4, 0xF957, 0xD2F5,
+ 0xF958, 0xD2F7, 0xF959, 0xD2F8, 0xF95A, 0xD4E6, 0xF95B, 0xD4FC, 0xF95C, 0xD5A5, 0xF95D, 0xD5AB, 0xF95E, 0xD5AE, 0xF95F, 0xD6B8,
+ 0xF960, 0xD6CD, 0xF961, 0xD7CB, 0xF962, 0xD7E4, 0xF963, 0xDBC5, 0xF964, 0xDBE4, 0xF965, 0xDCA5, 0xF966, 0xDDA5, 0xF967, 0xDDD5,
+ 0xF968, 0xDDF4, 0xF969, 0xDEFC, 0xF96A, 0xDEFE, 0xF96B, 0xDFB3, 0xF96C, 0xDFE1, 0xF96D, 0xDFE8, 0xF96E, 0xE0F1, 0xF96F, 0xE1AD,
+ 0xF970, 0xE1ED, 0xF971, 0xE3F5, 0xF972, 0xE4A1, 0xF973, 0xE4A9, 0xF974, 0xE5AE, 0xF975, 0xE5B1, 0xF976, 0xE5B2, 0xF977, 0xE5B9,
+ 0xF978, 0xE5BB, 0xF979, 0xE5BC, 0xF97A, 0xE5C4, 0xF97B, 0xE5CE, 0xF97C, 0xE5D0, 0xF97D, 0xE5D2, 0xF97E, 0xE5D6, 0xF97F, 0xE5FA,
+ 0xF980, 0xE5FB, 0xF981, 0xE5FC, 0xF982, 0xE5FE, 0xF983, 0xE6A1, 0xF984, 0xE6A4, 0xF985, 0xE6A7, 0xF986, 0xE6AD, 0xF987, 0xE6AF,
+ 0xF988, 0xE6B0, 0xF989, 0xE6B1, 0xF98A, 0xE6B3, 0xF98B, 0xE6B7, 0xF98C, 0xE6B8, 0xF98D, 0xE6BC, 0xF98E, 0xE6C4, 0xF98F, 0xE6C6,
+ 0xF990, 0xE6C7, 0xF991, 0xE6CA, 0xF992, 0xE6D2, 0xF993, 0xE6D6, 0xF994, 0xE6D9, 0xF995, 0xE6DC, 0xF996, 0xE6DF, 0xF997, 0xE6E1,
+ 0xF998, 0xE6E4, 0xF999, 0xE6E5, 0xF99A, 0xE6E6, 0xF99B, 0xE6E8, 0xF99C, 0xE6EA, 0xF99D, 0xE6EB, 0xF99E, 0xE6EC, 0xF99F, 0xE6EF,
+ 0xF9A0, 0xE6F1, 0xF9A1, 0xE6F2, 0xF9A2, 0xE6F5, 0xF9A3, 0xE6F6, 0xF9A4, 0xE6F7, 0xF9A5, 0xE6F9, 0xF9A6, 0xE7A1, 0xF9A7, 0xE7A6,
+ 0xF9A8, 0xE7A9, 0xF9A9, 0xE7AA, 0xF9AA, 0xE7AC, 0xF9AB, 0xE7AD, 0xF9AC, 0xE7B0, 0xF9AD, 0xE7BF, 0xF9AE, 0xE7C1, 0xF9AF, 0xE7C6,
+ 0xF9B0, 0xE7C7, 0xF9B1, 0xE7CB, 0xF9B2, 0xE7CD, 0xF9B3, 0xE7CF, 0xF9B4, 0xE7D0, 0xF9B5, 0xE7D3, 0xF9B6, 0xE7DF, 0xF9B7, 0xE7E4,
+ 0xF9B8, 0xE7E6, 0xF9B9, 0xE7F7, 0xF9BA, 0xE8E7, 0xF9BB, 0xE8E8, 0xF9BC, 0xE8F0, 0xF9BD, 0xE8F1, 0xF9BE, 0xE8F7, 0xF9BF, 0xE8F9,
+ 0xF9C0, 0xE8FB, 0xF9C1, 0xE8FE, 0xF9C2, 0xE9A7, 0xF9C3, 0xE9AC, 0xF9C4, 0xE9CC, 0xF9C5, 0xE9F7, 0xF9C6, 0xEAC1, 0xF9C7, 0xEAE5,
+ 0xF9C8, 0xEAF4, 0xF9C9, 0xEAF7, 0xF9CA, 0xEAFC, 0xF9CB, 0xEAFE, 0xF9CC, 0xEBA4, 0xF9CD, 0xEBA7, 0xF9CE, 0xEBA9, 0xF9CF, 0xEBAA,
+ 0xF9D0, 0xEBBA, 0xF9D1, 0xEBBB, 0xF9D2, 0xEBBD, 0xF9D3, 0xEBC1, 0xF9D4, 0xEBC2, 0xF9D5, 0xEBC6, 0xF9D6, 0xEBC7, 0xF9D7, 0xEBCC,
+ 0xF9D8, 0xEBCF, 0xF9D9, 0xEBD0, 0xF9DA, 0xEBD1, 0xF9DB, 0xEBD2, 0xF9DC, 0xEBD8, 0xF9DD, 0xECA6, 0xF9DE, 0xECA7, 0xF9DF, 0xECAA,
+ 0xF9E0, 0xECAF, 0xF9E1, 0xECB0, 0xF9E2, 0xECB1, 0xF9E3, 0xECB2, 0xF9E4, 0xECB5, 0xF9E5, 0xECB8, 0xF9E6, 0xECBA, 0xF9E7, 0xECC0,
+ 0xF9E8, 0xECC1, 0xF9E9, 0xECC5, 0xF9EA, 0xECC6, 0xF9EB, 0xECC9, 0xF9EC, 0xECCA, 0xF9ED, 0xECD5, 0xF9EE, 0xECDD, 0xF9EF, 0xECDE,
+ 0xF9F0, 0xECE1, 0xF9F1, 0xECE4, 0xF9F2, 0xECE7, 0xF9F3, 0xECE8, 0xF9F4, 0xECF7, 0xF9F5, 0xECF8, 0xF9F6, 0xECFA, 0xF9F7, 0xEDA1,
+ 0xF9F8, 0xEDA2, 0xF9F9, 0xEDA3, 0xF9FA, 0xEDEE, 0xF9FB, 0xEEDB, 0xF9FC, 0xF2BD, 0xF9FD, 0xF2FA, 0xF9FE, 0xF3B1, 0xF9FF, 0xF4A7,
+ 0xFA00, 0xF4EE, 0xFA01, 0xF6F4, 0xFA02, 0xF6F6, 0xFA03, 0xF7B8, 0xFA04, 0xF7C8, 0xFA05, 0xF7D3, 0xFA06, 0xF8DB, 0xFA07, 0xF8F0,
+ 0xFA08, 0xFAA1, 0xFA09, 0xFAA2, 0xFA0A, 0xFAE6, 0xFA0B, 0xFCA9, 0xFF01, 0xA3A1, 0xFF02, 0xA3A2, 0xFF03, 0xA3A3, 0xFF04, 0xA3A4,
+ 0xFF05, 0xA3A5, 0xFF06, 0xA3A6, 0xFF07, 0xA3A7, 0xFF08, 0xA3A8, 0xFF09, 0xA3A9, 0xFF0A, 0xA3AA, 0xFF0B, 0xA3AB, 0xFF0C, 0xA3AC,
+ 0xFF0D, 0xA3AD, 0xFF0E, 0xA3AE, 0xFF0F, 0xA3AF, 0xFF10, 0xA3B0, 0xFF11, 0xA3B1, 0xFF12, 0xA3B2, 0xFF13, 0xA3B3, 0xFF14, 0xA3B4,
+ 0xFF15, 0xA3B5, 0xFF16, 0xA3B6, 0xFF17, 0xA3B7, 0xFF18, 0xA3B8, 0xFF19, 0xA3B9, 0xFF1A, 0xA3BA, 0xFF1B, 0xA3BB, 0xFF1C, 0xA3BC,
+ 0xFF1D, 0xA3BD, 0xFF1E, 0xA3BE, 0xFF1F, 0xA3BF, 0xFF20, 0xA3C0, 0xFF21, 0xA3C1, 0xFF22, 0xA3C2, 0xFF23, 0xA3C3, 0xFF24, 0xA3C4,
+ 0xFF25, 0xA3C5, 0xFF26, 0xA3C6, 0xFF27, 0xA3C7, 0xFF28, 0xA3C8, 0xFF29, 0xA3C9, 0xFF2A, 0xA3CA, 0xFF2B, 0xA3CB, 0xFF2C, 0xA3CC,
+ 0xFF2D, 0xA3CD, 0xFF2E, 0xA3CE, 0xFF2F, 0xA3CF, 0xFF30, 0xA3D0, 0xFF31, 0xA3D1, 0xFF32, 0xA3D2, 0xFF33, 0xA3D3, 0xFF34, 0xA3D4,
+ 0xFF35, 0xA3D5, 0xFF36, 0xA3D6, 0xFF37, 0xA3D7, 0xFF38, 0xA3D8, 0xFF39, 0xA3D9, 0xFF3A, 0xA3DA, 0xFF3B, 0xA3DB, 0xFF3C, 0xA1AC,
+ 0xFF3D, 0xA3DD, 0xFF3E, 0xA3DE, 0xFF3F, 0xA3DF, 0xFF40, 0xA3E0, 0xFF41, 0xA3E1, 0xFF42, 0xA3E2, 0xFF43, 0xA3E3, 0xFF44, 0xA3E4,
+ 0xFF45, 0xA3E5, 0xFF46, 0xA3E6, 0xFF47, 0xA3E7, 0xFF48, 0xA3E8, 0xFF49, 0xA3E9, 0xFF4A, 0xA3EA, 0xFF4B, 0xA3EB, 0xFF4C, 0xA3EC,
+ 0xFF4D, 0xA3ED, 0xFF4E, 0xA3EE, 0xFF4F, 0xA3EF, 0xFF50, 0xA3F0, 0xFF51, 0xA3F1, 0xFF52, 0xA3F2, 0xFF53, 0xA3F3, 0xFF54, 0xA3F4,
+ 0xFF55, 0xA3F5, 0xFF56, 0xA3F6, 0xFF57, 0xA3F7, 0xFF58, 0xA3F8, 0xFF59, 0xA3F9, 0xFF5A, 0xA3FA, 0xFF5B, 0xA3FB, 0xFF5C, 0xA3FC,
+ 0xFF5D, 0xA3FD, 0xFF5E, 0xA2A6, 0xFFE0, 0xA1CB, 0xFFE1, 0xA1CC, 0xFFE2, 0xA1FE, 0xFFE3, 0xA3FE, 0xFFE5, 0xA1CD, 0xFFE6, 0xA3DC,
+ 0, 0
+};
+
+static const WCHAR oem2uni949[] = { /* Korean --> Unicode pairs */
+ 0x8141, 0xAC02, 0x8142, 0xAC03, 0x8143, 0xAC05, 0x8144, 0xAC06, 0x8145, 0xAC0B, 0x8146, 0xAC0C, 0x8147, 0xAC0D, 0x8148, 0xAC0E,
+ 0x8149, 0xAC0F, 0x814A, 0xAC18, 0x814B, 0xAC1E, 0x814C, 0xAC1F, 0x814D, 0xAC21, 0x814E, 0xAC22, 0x814F, 0xAC23, 0x8150, 0xAC25,
+ 0x8151, 0xAC26, 0x8152, 0xAC27, 0x8153, 0xAC28, 0x8154, 0xAC29, 0x8155, 0xAC2A, 0x8156, 0xAC2B, 0x8157, 0xAC2E, 0x8158, 0xAC32,
+ 0x8159, 0xAC33, 0x815A, 0xAC34, 0x8161, 0xAC35, 0x8162, 0xAC36, 0x8163, 0xAC37, 0x8164, 0xAC3A, 0x8165, 0xAC3B, 0x8166, 0xAC3D,
+ 0x8167, 0xAC3E, 0x8168, 0xAC3F, 0x8169, 0xAC41, 0x816A, 0xAC42, 0x816B, 0xAC43, 0x816C, 0xAC44, 0x816D, 0xAC45, 0x816E, 0xAC46,
+ 0x816F, 0xAC47, 0x8170, 0xAC48, 0x8171, 0xAC49, 0x8172, 0xAC4A, 0x8173, 0xAC4C, 0x8174, 0xAC4E, 0x8175, 0xAC4F, 0x8176, 0xAC50,
+ 0x8177, 0xAC51, 0x8178, 0xAC52, 0x8179, 0xAC53, 0x817A, 0xAC55, 0x8181, 0xAC56, 0x8182, 0xAC57, 0x8183, 0xAC59, 0x8184, 0xAC5A,
+ 0x8185, 0xAC5B, 0x8186, 0xAC5D, 0x8187, 0xAC5E, 0x8188, 0xAC5F, 0x8189, 0xAC60, 0x818A, 0xAC61, 0x818B, 0xAC62, 0x818C, 0xAC63,
+ 0x818D, 0xAC64, 0x818E, 0xAC65, 0x818F, 0xAC66, 0x8190, 0xAC67, 0x8191, 0xAC68, 0x8192, 0xAC69, 0x8193, 0xAC6A, 0x8194, 0xAC6B,
+ 0x8195, 0xAC6C, 0x8196, 0xAC6D, 0x8197, 0xAC6E, 0x8198, 0xAC6F, 0x8199, 0xAC72, 0x819A, 0xAC73, 0x819B, 0xAC75, 0x819C, 0xAC76,
+ 0x819D, 0xAC79, 0x819E, 0xAC7B, 0x819F, 0xAC7C, 0x81A0, 0xAC7D, 0x81A1, 0xAC7E, 0x81A2, 0xAC7F, 0x81A3, 0xAC82, 0x81A4, 0xAC87,
+ 0x81A5, 0xAC88, 0x81A6, 0xAC8D, 0x81A7, 0xAC8E, 0x81A8, 0xAC8F, 0x81A9, 0xAC91, 0x81AA, 0xAC92, 0x81AB, 0xAC93, 0x81AC, 0xAC95,
+ 0x81AD, 0xAC96, 0x81AE, 0xAC97, 0x81AF, 0xAC98, 0x81B0, 0xAC99, 0x81B1, 0xAC9A, 0x81B2, 0xAC9B, 0x81B3, 0xAC9E, 0x81B4, 0xACA2,
+ 0x81B5, 0xACA3, 0x81B6, 0xACA4, 0x81B7, 0xACA5, 0x81B8, 0xACA6, 0x81B9, 0xACA7, 0x81BA, 0xACAB, 0x81BB, 0xACAD, 0x81BC, 0xACAE,
+ 0x81BD, 0xACB1, 0x81BE, 0xACB2, 0x81BF, 0xACB3, 0x81C0, 0xACB4, 0x81C1, 0xACB5, 0x81C2, 0xACB6, 0x81C3, 0xACB7, 0x81C4, 0xACBA,
+ 0x81C5, 0xACBE, 0x81C6, 0xACBF, 0x81C7, 0xACC0, 0x81C8, 0xACC2, 0x81C9, 0xACC3, 0x81CA, 0xACC5, 0x81CB, 0xACC6, 0x81CC, 0xACC7,
+ 0x81CD, 0xACC9, 0x81CE, 0xACCA, 0x81CF, 0xACCB, 0x81D0, 0xACCD, 0x81D1, 0xACCE, 0x81D2, 0xACCF, 0x81D3, 0xACD0, 0x81D4, 0xACD1,
+ 0x81D5, 0xACD2, 0x81D6, 0xACD3, 0x81D7, 0xACD4, 0x81D8, 0xACD6, 0x81D9, 0xACD8, 0x81DA, 0xACD9, 0x81DB, 0xACDA, 0x81DC, 0xACDB,
+ 0x81DD, 0xACDC, 0x81DE, 0xACDD, 0x81DF, 0xACDE, 0x81E0, 0xACDF, 0x81E1, 0xACE2, 0x81E2, 0xACE3, 0x81E3, 0xACE5, 0x81E4, 0xACE6,
+ 0x81E5, 0xACE9, 0x81E6, 0xACEB, 0x81E7, 0xACED, 0x81E8, 0xACEE, 0x81E9, 0xACF2, 0x81EA, 0xACF4, 0x81EB, 0xACF7, 0x81EC, 0xACF8,
+ 0x81ED, 0xACF9, 0x81EE, 0xACFA, 0x81EF, 0xACFB, 0x81F0, 0xACFE, 0x81F1, 0xACFF, 0x81F2, 0xAD01, 0x81F3, 0xAD02, 0x81F4, 0xAD03,
+ 0x81F5, 0xAD05, 0x81F6, 0xAD07, 0x81F7, 0xAD08, 0x81F8, 0xAD09, 0x81F9, 0xAD0A, 0x81FA, 0xAD0B, 0x81FB, 0xAD0E, 0x81FC, 0xAD10,
+ 0x81FD, 0xAD12, 0x81FE, 0xAD13, 0x8241, 0xAD14, 0x8242, 0xAD15, 0x8243, 0xAD16, 0x8244, 0xAD17, 0x8245, 0xAD19, 0x8246, 0xAD1A,
+ 0x8247, 0xAD1B, 0x8248, 0xAD1D, 0x8249, 0xAD1E, 0x824A, 0xAD1F, 0x824B, 0xAD21, 0x824C, 0xAD22, 0x824D, 0xAD23, 0x824E, 0xAD24,
+ 0x824F, 0xAD25, 0x8250, 0xAD26, 0x8251, 0xAD27, 0x8252, 0xAD28, 0x8253, 0xAD2A, 0x8254, 0xAD2B, 0x8255, 0xAD2E, 0x8256, 0xAD2F,
+ 0x8257, 0xAD30, 0x8258, 0xAD31, 0x8259, 0xAD32, 0x825A, 0xAD33, 0x8261, 0xAD36, 0x8262, 0xAD37, 0x8263, 0xAD39, 0x8264, 0xAD3A,
+ 0x8265, 0xAD3B, 0x8266, 0xAD3D, 0x8267, 0xAD3E, 0x8268, 0xAD3F, 0x8269, 0xAD40, 0x826A, 0xAD41, 0x826B, 0xAD42, 0x826C, 0xAD43,
+ 0x826D, 0xAD46, 0x826E, 0xAD48, 0x826F, 0xAD4A, 0x8270, 0xAD4B, 0x8271, 0xAD4C, 0x8272, 0xAD4D, 0x8273, 0xAD4E, 0x8274, 0xAD4F,
+ 0x8275, 0xAD51, 0x8276, 0xAD52, 0x8277, 0xAD53, 0x8278, 0xAD55, 0x8279, 0xAD56, 0x827A, 0xAD57, 0x8281, 0xAD59, 0x8282, 0xAD5A,
+ 0x8283, 0xAD5B, 0x8284, 0xAD5C, 0x8285, 0xAD5D, 0x8286, 0xAD5E, 0x8287, 0xAD5F, 0x8288, 0xAD60, 0x8289, 0xAD62, 0x828A, 0xAD64,
+ 0x828B, 0xAD65, 0x828C, 0xAD66, 0x828D, 0xAD67, 0x828E, 0xAD68, 0x828F, 0xAD69, 0x8290, 0xAD6A, 0x8291, 0xAD6B, 0x8292, 0xAD6E,
+ 0x8293, 0xAD6F, 0x8294, 0xAD71, 0x8295, 0xAD72, 0x8296, 0xAD77, 0x8297, 0xAD78, 0x8298, 0xAD79, 0x8299, 0xAD7A, 0x829A, 0xAD7E,
+ 0x829B, 0xAD80, 0x829C, 0xAD83, 0x829D, 0xAD84, 0x829E, 0xAD85, 0x829F, 0xAD86, 0x82A0, 0xAD87, 0x82A1, 0xAD8A, 0x82A2, 0xAD8B,
+ 0x82A3, 0xAD8D, 0x82A4, 0xAD8E, 0x82A5, 0xAD8F, 0x82A6, 0xAD91, 0x82A7, 0xAD92, 0x82A8, 0xAD93, 0x82A9, 0xAD94, 0x82AA, 0xAD95,
+ 0x82AB, 0xAD96, 0x82AC, 0xAD97, 0x82AD, 0xAD98, 0x82AE, 0xAD99, 0x82AF, 0xAD9A, 0x82B0, 0xAD9B, 0x82B1, 0xAD9E, 0x82B2, 0xAD9F,
+ 0x82B3, 0xADA0, 0x82B4, 0xADA1, 0x82B5, 0xADA2, 0x82B6, 0xADA3, 0x82B7, 0xADA5, 0x82B8, 0xADA6, 0x82B9, 0xADA7, 0x82BA, 0xADA8,
+ 0x82BB, 0xADA9, 0x82BC, 0xADAA, 0x82BD, 0xADAB, 0x82BE, 0xADAC, 0x82BF, 0xADAD, 0x82C0, 0xADAE, 0x82C1, 0xADAF, 0x82C2, 0xADB0,
+ 0x82C3, 0xADB1, 0x82C4, 0xADB2, 0x82C5, 0xADB3, 0x82C6, 0xADB4, 0x82C7, 0xADB5, 0x82C8, 0xADB6, 0x82C9, 0xADB8, 0x82CA, 0xADB9,
+ 0x82CB, 0xADBA, 0x82CC, 0xADBB, 0x82CD, 0xADBC, 0x82CE, 0xADBD, 0x82CF, 0xADBE, 0x82D0, 0xADBF, 0x82D1, 0xADC2, 0x82D2, 0xADC3,
+ 0x82D3, 0xADC5, 0x82D4, 0xADC6, 0x82D5, 0xADC7, 0x82D6, 0xADC9, 0x82D7, 0xADCA, 0x82D8, 0xADCB, 0x82D9, 0xADCC, 0x82DA, 0xADCD,
+ 0x82DB, 0xADCE, 0x82DC, 0xADCF, 0x82DD, 0xADD2, 0x82DE, 0xADD4, 0x82DF, 0xADD5, 0x82E0, 0xADD6, 0x82E1, 0xADD7, 0x82E2, 0xADD8,
+ 0x82E3, 0xADD9, 0x82E4, 0xADDA, 0x82E5, 0xADDB, 0x82E6, 0xADDD, 0x82E7, 0xADDE, 0x82E8, 0xADDF, 0x82E9, 0xADE1, 0x82EA, 0xADE2,
+ 0x82EB, 0xADE3, 0x82EC, 0xADE5, 0x82ED, 0xADE6, 0x82EE, 0xADE7, 0x82EF, 0xADE8, 0x82F0, 0xADE9, 0x82F1, 0xADEA, 0x82F2, 0xADEB,
+ 0x82F3, 0xADEC, 0x82F4, 0xADED, 0x82F5, 0xADEE, 0x82F6, 0xADEF, 0x82F7, 0xADF0, 0x82F8, 0xADF1, 0x82F9, 0xADF2, 0x82FA, 0xADF3,
+ 0x82FB, 0xADF4, 0x82FC, 0xADF5, 0x82FD, 0xADF6, 0x82FE, 0xADF7, 0x8341, 0xADFA, 0x8342, 0xADFB, 0x8343, 0xADFD, 0x8344, 0xADFE,
+ 0x8345, 0xAE02, 0x8346, 0xAE03, 0x8347, 0xAE04, 0x8348, 0xAE05, 0x8349, 0xAE06, 0x834A, 0xAE07, 0x834B, 0xAE0A, 0x834C, 0xAE0C,
+ 0x834D, 0xAE0E, 0x834E, 0xAE0F, 0x834F, 0xAE10, 0x8350, 0xAE11, 0x8351, 0xAE12, 0x8352, 0xAE13, 0x8353, 0xAE15, 0x8354, 0xAE16,
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+ 0x8763, 0xB1BB, 0x8764, 0xB1BC, 0x8765, 0xB1BD, 0x8766, 0xB1BE, 0x8767, 0xB1BF, 0x8768, 0xB1C0, 0x8769, 0xB1C1, 0x876A, 0xB1C2,
+ 0x876B, 0xB1C3, 0x876C, 0xB1C4, 0x876D, 0xB1C5, 0x876E, 0xB1C6, 0x876F, 0xB1C7, 0x8770, 0xB1C8, 0x8771, 0xB1C9, 0x8772, 0xB1CA,
+ 0x8773, 0xB1CB, 0x8774, 0xB1CD, 0x8775, 0xB1CE, 0x8776, 0xB1CF, 0x8777, 0xB1D1, 0x8778, 0xB1D2, 0x8779, 0xB1D3, 0x877A, 0xB1D5,
+ 0x8781, 0xB1D6, 0x8782, 0xB1D7, 0x8783, 0xB1D8, 0x8784, 0xB1D9, 0x8785, 0xB1DA, 0x8786, 0xB1DB, 0x8787, 0xB1DE, 0x8788, 0xB1E0,
+ 0x8789, 0xB1E1, 0x878A, 0xB1E2, 0x878B, 0xB1E3, 0x878C, 0xB1E4, 0x878D, 0xB1E5, 0x878E, 0xB1E6, 0x878F, 0xB1E7, 0x8790, 0xB1EA,
+ 0x8791, 0xB1EB, 0x8792, 0xB1ED, 0x8793, 0xB1EE, 0x8794, 0xB1EF, 0x8795, 0xB1F1, 0x8796, 0xB1F2, 0x8797, 0xB1F3, 0x8798, 0xB1F4,
+ 0x8799, 0xB1F5, 0x879A, 0xB1F6, 0x879B, 0xB1F7, 0x879C, 0xB1F8, 0x879D, 0xB1FA, 0x879E, 0xB1FC, 0x879F, 0xB1FE, 0x87A0, 0xB1FF,
+ 0x87A1, 0xB200, 0x87A2, 0xB201, 0x87A3, 0xB202, 0x87A4, 0xB203, 0x87A5, 0xB206, 0x87A6, 0xB207, 0x87A7, 0xB209, 0x87A8, 0xB20A,
+ 0x87A9, 0xB20D, 0x87AA, 0xB20E, 0x87AB, 0xB20F, 0x87AC, 0xB210, 0x87AD, 0xB211, 0x87AE, 0xB212, 0x87AF, 0xB213, 0x87B0, 0xB216,
+ 0x87B1, 0xB218, 0x87B2, 0xB21A, 0x87B3, 0xB21B, 0x87B4, 0xB21C, 0x87B5, 0xB21D, 0x87B6, 0xB21E, 0x87B7, 0xB21F, 0x87B8, 0xB221,
+ 0x87B9, 0xB222, 0x87BA, 0xB223, 0x87BB, 0xB224, 0x87BC, 0xB225, 0x87BD, 0xB226, 0x87BE, 0xB227, 0x87BF, 0xB228, 0x87C0, 0xB229,
+ 0x87C1, 0xB22A, 0x87C2, 0xB22B, 0x87C3, 0xB22C, 0x87C4, 0xB22D, 0x87C5, 0xB22E, 0x87C6, 0xB22F, 0x87C7, 0xB230, 0x87C8, 0xB231,
+ 0x87C9, 0xB232, 0x87CA, 0xB233, 0x87CB, 0xB235, 0x87CC, 0xB236, 0x87CD, 0xB237, 0x87CE, 0xB238, 0x87CF, 0xB239, 0x87D0, 0xB23A,
+ 0x87D1, 0xB23B, 0x87D2, 0xB23D, 0x87D3, 0xB23E, 0x87D4, 0xB23F, 0x87D5, 0xB240, 0x87D6, 0xB241, 0x87D7, 0xB242, 0x87D8, 0xB243,
+ 0x87D9, 0xB244, 0x87DA, 0xB245, 0x87DB, 0xB246, 0x87DC, 0xB247, 0x87DD, 0xB248, 0x87DE, 0xB249, 0x87DF, 0xB24A, 0x87E0, 0xB24B,
+ 0x87E1, 0xB24C, 0x87E2, 0xB24D, 0x87E3, 0xB24E, 0x87E4, 0xB24F, 0x87E5, 0xB250, 0x87E6, 0xB251, 0x87E7, 0xB252, 0x87E8, 0xB253,
+ 0x87E9, 0xB254, 0x87EA, 0xB255, 0x87EB, 0xB256, 0x87EC, 0xB257, 0x87ED, 0xB259, 0x87EE, 0xB25A, 0x87EF, 0xB25B, 0x87F0, 0xB25D,
+ 0x87F1, 0xB25E, 0x87F2, 0xB25F, 0x87F3, 0xB261, 0x87F4, 0xB262, 0x87F5, 0xB263, 0x87F6, 0xB264, 0x87F7, 0xB265, 0x87F8, 0xB266,
+ 0x87F9, 0xB267, 0x87FA, 0xB26A, 0x87FB, 0xB26B, 0x87FC, 0xB26C, 0x87FD, 0xB26D, 0x87FE, 0xB26E, 0x8841, 0xB26F, 0x8842, 0xB270,
+ 0x8843, 0xB271, 0x8844, 0xB272, 0x8845, 0xB273, 0x8846, 0xB276, 0x8847, 0xB277, 0x8848, 0xB278, 0x8849, 0xB279, 0x884A, 0xB27A,
+ 0x884B, 0xB27B, 0x884C, 0xB27D, 0x884D, 0xB27E, 0x884E, 0xB27F, 0x884F, 0xB280, 0x8850, 0xB281, 0x8851, 0xB282, 0x8852, 0xB283,
+ 0x8853, 0xB286, 0x8854, 0xB287, 0x8855, 0xB288, 0x8856, 0xB28A, 0x8857, 0xB28B, 0x8858, 0xB28C, 0x8859, 0xB28D, 0x885A, 0xB28E,
+ 0x8861, 0xB28F, 0x8862, 0xB292, 0x8863, 0xB293, 0x8864, 0xB295, 0x8865, 0xB296, 0x8866, 0xB297, 0x8867, 0xB29B, 0x8868, 0xB29C,
+ 0x8869, 0xB29D, 0x886A, 0xB29E, 0x886B, 0xB29F, 0x886C, 0xB2A2, 0x886D, 0xB2A4, 0x886E, 0xB2A7, 0x886F, 0xB2A8, 0x8870, 0xB2A9,
+ 0x8871, 0xB2AB, 0x8872, 0xB2AD, 0x8873, 0xB2AE, 0x8874, 0xB2AF, 0x8875, 0xB2B1, 0x8876, 0xB2B2, 0x8877, 0xB2B3, 0x8878, 0xB2B5,
+ 0x8879, 0xB2B6, 0x887A, 0xB2B7, 0x8881, 0xB2B8, 0x8882, 0xB2B9, 0x8883, 0xB2BA, 0x8884, 0xB2BB, 0x8885, 0xB2BC, 0x8886, 0xB2BD,
+ 0x8887, 0xB2BE, 0x8888, 0xB2BF, 0x8889, 0xB2C0, 0x888A, 0xB2C1, 0x888B, 0xB2C2, 0x888C, 0xB2C3, 0x888D, 0xB2C4, 0x888E, 0xB2C5,
+ 0x888F, 0xB2C6, 0x8890, 0xB2C7, 0x8891, 0xB2CA, 0x8892, 0xB2CB, 0x8893, 0xB2CD, 0x8894, 0xB2CE, 0x8895, 0xB2CF, 0x8896, 0xB2D1,
+ 0x8897, 0xB2D3, 0x8898, 0xB2D4, 0x8899, 0xB2D5, 0x889A, 0xB2D6, 0x889B, 0xB2D7, 0x889C, 0xB2DA, 0x889D, 0xB2DC, 0x889E, 0xB2DE,
+ 0x889F, 0xB2DF, 0x88A0, 0xB2E0, 0x88A1, 0xB2E1, 0x88A2, 0xB2E3, 0x88A3, 0xB2E7, 0x88A4, 0xB2E9, 0x88A5, 0xB2EA, 0x88A6, 0xB2F0,
+ 0x88A7, 0xB2F1, 0x88A8, 0xB2F2, 0x88A9, 0xB2F6, 0x88AA, 0xB2FC, 0x88AB, 0xB2FD, 0x88AC, 0xB2FE, 0x88AD, 0xB302, 0x88AE, 0xB303,
+ 0x88AF, 0xB305, 0x88B0, 0xB306, 0x88B1, 0xB307, 0x88B2, 0xB309, 0x88B3, 0xB30A, 0x88B4, 0xB30B, 0x88B5, 0xB30C, 0x88B6, 0xB30D,
+ 0x88B7, 0xB30E, 0x88B8, 0xB30F, 0x88B9, 0xB312, 0x88BA, 0xB316, 0x88BB, 0xB317, 0x88BC, 0xB318, 0x88BD, 0xB319, 0x88BE, 0xB31A,
+ 0x88BF, 0xB31B, 0x88C0, 0xB31D, 0x88C1, 0xB31E, 0x88C2, 0xB31F, 0x88C3, 0xB320, 0x88C4, 0xB321, 0x88C5, 0xB322, 0x88C6, 0xB323,
+ 0x88C7, 0xB324, 0x88C8, 0xB325, 0x88C9, 0xB326, 0x88CA, 0xB327, 0x88CB, 0xB328, 0x88CC, 0xB329, 0x88CD, 0xB32A, 0x88CE, 0xB32B,
+ 0x88CF, 0xB32C, 0x88D0, 0xB32D, 0x88D1, 0xB32E, 0x88D2, 0xB32F, 0x88D3, 0xB330, 0x88D4, 0xB331, 0x88D5, 0xB332, 0x88D6, 0xB333,
+ 0x88D7, 0xB334, 0x88D8, 0xB335, 0x88D9, 0xB336, 0x88DA, 0xB337, 0x88DB, 0xB338, 0x88DC, 0xB339, 0x88DD, 0xB33A, 0x88DE, 0xB33B,
+ 0x88DF, 0xB33C, 0x88E0, 0xB33D, 0x88E1, 0xB33E, 0x88E2, 0xB33F, 0x88E3, 0xB340, 0x88E4, 0xB341, 0x88E5, 0xB342, 0x88E6, 0xB343,
+ 0x88E7, 0xB344, 0x88E8, 0xB345, 0x88E9, 0xB346, 0x88EA, 0xB347, 0x88EB, 0xB348, 0x88EC, 0xB349, 0x88ED, 0xB34A, 0x88EE, 0xB34B,
+ 0x88EF, 0xB34C, 0x88F0, 0xB34D, 0x88F1, 0xB34E, 0x88F2, 0xB34F, 0x88F3, 0xB350, 0x88F4, 0xB351, 0x88F5, 0xB352, 0x88F6, 0xB353,
+ 0x88F7, 0xB357, 0x88F8, 0xB359, 0x88F9, 0xB35A, 0x88FA, 0xB35D, 0x88FB, 0xB360, 0x88FC, 0xB361, 0x88FD, 0xB362, 0x88FE, 0xB363,
+ 0x8941, 0xB366, 0x8942, 0xB368, 0x8943, 0xB36A, 0x8944, 0xB36C, 0x8945, 0xB36D, 0x8946, 0xB36F, 0x8947, 0xB372, 0x8948, 0xB373,
+ 0x8949, 0xB375, 0x894A, 0xB376, 0x894B, 0xB377, 0x894C, 0xB379, 0x894D, 0xB37A, 0x894E, 0xB37B, 0x894F, 0xB37C, 0x8950, 0xB37D,
+ 0x8951, 0xB37E, 0x8952, 0xB37F, 0x8953, 0xB382, 0x8954, 0xB386, 0x8955, 0xB387, 0x8956, 0xB388, 0x8957, 0xB389, 0x8958, 0xB38A,
+ 0x8959, 0xB38B, 0x895A, 0xB38D, 0x8961, 0xB38E, 0x8962, 0xB38F, 0x8963, 0xB391, 0x8964, 0xB392, 0x8965, 0xB393, 0x8966, 0xB395,
+ 0x8967, 0xB396, 0x8968, 0xB397, 0x8969, 0xB398, 0x896A, 0xB399, 0x896B, 0xB39A, 0x896C, 0xB39B, 0x896D, 0xB39C, 0x896E, 0xB39D,
+ 0x896F, 0xB39E, 0x8970, 0xB39F, 0x8971, 0xB3A2, 0x8972, 0xB3A3, 0x8973, 0xB3A4, 0x8974, 0xB3A5, 0x8975, 0xB3A6, 0x8976, 0xB3A7,
+ 0x8977, 0xB3A9, 0x8978, 0xB3AA, 0x8979, 0xB3AB, 0x897A, 0xB3AD, 0x8981, 0xB3AE, 0x8982, 0xB3AF, 0x8983, 0xB3B0, 0x8984, 0xB3B1,
+ 0x8985, 0xB3B2, 0x8986, 0xB3B3, 0x8987, 0xB3B4, 0x8988, 0xB3B5, 0x8989, 0xB3B6, 0x898A, 0xB3B7, 0x898B, 0xB3B8, 0x898C, 0xB3B9,
+ 0x898D, 0xB3BA, 0x898E, 0xB3BB, 0x898F, 0xB3BC, 0x8990, 0xB3BD, 0x8991, 0xB3BE, 0x8992, 0xB3BF, 0x8993, 0xB3C0, 0x8994, 0xB3C1,
+ 0x8995, 0xB3C2, 0x8996, 0xB3C3, 0x8997, 0xB3C6, 0x8998, 0xB3C7, 0x8999, 0xB3C9, 0x899A, 0xB3CA, 0x899B, 0xB3CD, 0x899C, 0xB3CF,
+ 0x899D, 0xB3D1, 0x899E, 0xB3D2, 0x899F, 0xB3D3, 0x89A0, 0xB3D6, 0x89A1, 0xB3D8, 0x89A2, 0xB3DA, 0x89A3, 0xB3DC, 0x89A4, 0xB3DE,
+ 0x89A5, 0xB3DF, 0x89A6, 0xB3E1, 0x89A7, 0xB3E2, 0x89A8, 0xB3E3, 0x89A9, 0xB3E5, 0x89AA, 0xB3E6, 0x89AB, 0xB3E7, 0x89AC, 0xB3E9,
+ 0x89AD, 0xB3EA, 0x89AE, 0xB3EB, 0x89AF, 0xB3EC, 0x89B0, 0xB3ED, 0x89B1, 0xB3EE, 0x89B2, 0xB3EF, 0x89B3, 0xB3F0, 0x89B4, 0xB3F1,
+ 0x89B5, 0xB3F2, 0x89B6, 0xB3F3, 0x89B7, 0xB3F4, 0x89B8, 0xB3F5, 0x89B9, 0xB3F6, 0x89BA, 0xB3F7, 0x89BB, 0xB3F8, 0x89BC, 0xB3F9,
+ 0x89BD, 0xB3FA, 0x89BE, 0xB3FB, 0x89BF, 0xB3FD, 0x89C0, 0xB3FE, 0x89C1, 0xB3FF, 0x89C2, 0xB400, 0x89C3, 0xB401, 0x89C4, 0xB402,
+ 0x89C5, 0xB403, 0x89C6, 0xB404, 0x89C7, 0xB405, 0x89C8, 0xB406, 0x89C9, 0xB407, 0x89CA, 0xB408, 0x89CB, 0xB409, 0x89CC, 0xB40A,
+ 0x89CD, 0xB40B, 0x89CE, 0xB40C, 0x89CF, 0xB40D, 0x89D0, 0xB40E, 0x89D1, 0xB40F, 0x89D2, 0xB411, 0x89D3, 0xB412, 0x89D4, 0xB413,
+ 0x89D5, 0xB414, 0x89D6, 0xB415, 0x89D7, 0xB416, 0x89D8, 0xB417, 0x89D9, 0xB419, 0x89DA, 0xB41A, 0x89DB, 0xB41B, 0x89DC, 0xB41D,
+ 0x89DD, 0xB41E, 0x89DE, 0xB41F, 0x89DF, 0xB421, 0x89E0, 0xB422, 0x89E1, 0xB423, 0x89E2, 0xB424, 0x89E3, 0xB425, 0x89E4, 0xB426,
+ 0x89E5, 0xB427, 0x89E6, 0xB42A, 0x89E7, 0xB42C, 0x89E8, 0xB42D, 0x89E9, 0xB42E, 0x89EA, 0xB42F, 0x89EB, 0xB430, 0x89EC, 0xB431,
+ 0x89ED, 0xB432, 0x89EE, 0xB433, 0x89EF, 0xB435, 0x89F0, 0xB436, 0x89F1, 0xB437, 0x89F2, 0xB438, 0x89F3, 0xB439, 0x89F4, 0xB43A,
+ 0x89F5, 0xB43B, 0x89F6, 0xB43C, 0x89F7, 0xB43D, 0x89F8, 0xB43E, 0x89F9, 0xB43F, 0x89FA, 0xB440, 0x89FB, 0xB441, 0x89FC, 0xB442,
+ 0x89FD, 0xB443, 0x89FE, 0xB444, 0x8A41, 0xB445, 0x8A42, 0xB446, 0x8A43, 0xB447, 0x8A44, 0xB448, 0x8A45, 0xB449, 0x8A46, 0xB44A,
+ 0x8A47, 0xB44B, 0x8A48, 0xB44C, 0x8A49, 0xB44D, 0x8A4A, 0xB44E, 0x8A4B, 0xB44F, 0x8A4C, 0xB452, 0x8A4D, 0xB453, 0x8A4E, 0xB455,
+ 0x8A4F, 0xB456, 0x8A50, 0xB457, 0x8A51, 0xB459, 0x8A52, 0xB45A, 0x8A53, 0xB45B, 0x8A54, 0xB45C, 0x8A55, 0xB45D, 0x8A56, 0xB45E,
+ 0x8A57, 0xB45F, 0x8A58, 0xB462, 0x8A59, 0xB464, 0x8A5A, 0xB466, 0x8A61, 0xB467, 0x8A62, 0xB468, 0x8A63, 0xB469, 0x8A64, 0xB46A,
+ 0x8A65, 0xB46B, 0x8A66, 0xB46D, 0x8A67, 0xB46E, 0x8A68, 0xB46F, 0x8A69, 0xB470, 0x8A6A, 0xB471, 0x8A6B, 0xB472, 0x8A6C, 0xB473,
+ 0x8A6D, 0xB474, 0x8A6E, 0xB475, 0x8A6F, 0xB476, 0x8A70, 0xB477, 0x8A71, 0xB478, 0x8A72, 0xB479, 0x8A73, 0xB47A, 0x8A74, 0xB47B,
+ 0x8A75, 0xB47C, 0x8A76, 0xB47D, 0x8A77, 0xB47E, 0x8A78, 0xB47F, 0x8A79, 0xB481, 0x8A7A, 0xB482, 0x8A81, 0xB483, 0x8A82, 0xB484,
+ 0x8A83, 0xB485, 0x8A84, 0xB486, 0x8A85, 0xB487, 0x8A86, 0xB489, 0x8A87, 0xB48A, 0x8A88, 0xB48B, 0x8A89, 0xB48C, 0x8A8A, 0xB48D,
+ 0x8A8B, 0xB48E, 0x8A8C, 0xB48F, 0x8A8D, 0xB490, 0x8A8E, 0xB491, 0x8A8F, 0xB492, 0x8A90, 0xB493, 0x8A91, 0xB494, 0x8A92, 0xB495,
+ 0x8A93, 0xB496, 0x8A94, 0xB497, 0x8A95, 0xB498, 0x8A96, 0xB499, 0x8A97, 0xB49A, 0x8A98, 0xB49B, 0x8A99, 0xB49C, 0x8A9A, 0xB49E,
+ 0x8A9B, 0xB49F, 0x8A9C, 0xB4A0, 0x8A9D, 0xB4A1, 0x8A9E, 0xB4A2, 0x8A9F, 0xB4A3, 0x8AA0, 0xB4A5, 0x8AA1, 0xB4A6, 0x8AA2, 0xB4A7,
+ 0x8AA3, 0xB4A9, 0x8AA4, 0xB4AA, 0x8AA5, 0xB4AB, 0x8AA6, 0xB4AD, 0x8AA7, 0xB4AE, 0x8AA8, 0xB4AF, 0x8AA9, 0xB4B0, 0x8AAA, 0xB4B1,
+ 0x8AAB, 0xB4B2, 0x8AAC, 0xB4B3, 0x8AAD, 0xB4B4, 0x8AAE, 0xB4B6, 0x8AAF, 0xB4B8, 0x8AB0, 0xB4BA, 0x8AB1, 0xB4BB, 0x8AB2, 0xB4BC,
+ 0x8AB3, 0xB4BD, 0x8AB4, 0xB4BE, 0x8AB5, 0xB4BF, 0x8AB6, 0xB4C1, 0x8AB7, 0xB4C2, 0x8AB8, 0xB4C3, 0x8AB9, 0xB4C5, 0x8ABA, 0xB4C6,
+ 0x8ABB, 0xB4C7, 0x8ABC, 0xB4C9, 0x8ABD, 0xB4CA, 0x8ABE, 0xB4CB, 0x8ABF, 0xB4CC, 0x8AC0, 0xB4CD, 0x8AC1, 0xB4CE, 0x8AC2, 0xB4CF,
+ 0x8AC3, 0xB4D1, 0x8AC4, 0xB4D2, 0x8AC5, 0xB4D3, 0x8AC6, 0xB4D4, 0x8AC7, 0xB4D6, 0x8AC8, 0xB4D7, 0x8AC9, 0xB4D8, 0x8ACA, 0xB4D9,
+ 0x8ACB, 0xB4DA, 0x8ACC, 0xB4DB, 0x8ACD, 0xB4DE, 0x8ACE, 0xB4DF, 0x8ACF, 0xB4E1, 0x8AD0, 0xB4E2, 0x8AD1, 0xB4E5, 0x8AD2, 0xB4E7,
+ 0x8AD3, 0xB4E8, 0x8AD4, 0xB4E9, 0x8AD5, 0xB4EA, 0x8AD6, 0xB4EB, 0x8AD7, 0xB4EE, 0x8AD8, 0xB4F0, 0x8AD9, 0xB4F2, 0x8ADA, 0xB4F3,
+ 0x8ADB, 0xB4F4, 0x8ADC, 0xB4F5, 0x8ADD, 0xB4F6, 0x8ADE, 0xB4F7, 0x8ADF, 0xB4F9, 0x8AE0, 0xB4FA, 0x8AE1, 0xB4FB, 0x8AE2, 0xB4FC,
+ 0x8AE3, 0xB4FD, 0x8AE4, 0xB4FE, 0x8AE5, 0xB4FF, 0x8AE6, 0xB500, 0x8AE7, 0xB501, 0x8AE8, 0xB502, 0x8AE9, 0xB503, 0x8AEA, 0xB504,
+ 0x8AEB, 0xB505, 0x8AEC, 0xB506, 0x8AED, 0xB507, 0x8AEE, 0xB508, 0x8AEF, 0xB509, 0x8AF0, 0xB50A, 0x8AF1, 0xB50B, 0x8AF2, 0xB50C,
+ 0x8AF3, 0xB50D, 0x8AF4, 0xB50E, 0x8AF5, 0xB50F, 0x8AF6, 0xB510, 0x8AF7, 0xB511, 0x8AF8, 0xB512, 0x8AF9, 0xB513, 0x8AFA, 0xB516,
+ 0x8AFB, 0xB517, 0x8AFC, 0xB519, 0x8AFD, 0xB51A, 0x8AFE, 0xB51D, 0x8B41, 0xB51E, 0x8B42, 0xB51F, 0x8B43, 0xB520, 0x8B44, 0xB521,
+ 0x8B45, 0xB522, 0x8B46, 0xB523, 0x8B47, 0xB526, 0x8B48, 0xB52B, 0x8B49, 0xB52C, 0x8B4A, 0xB52D, 0x8B4B, 0xB52E, 0x8B4C, 0xB52F,
+ 0x8B4D, 0xB532, 0x8B4E, 0xB533, 0x8B4F, 0xB535, 0x8B50, 0xB536, 0x8B51, 0xB537, 0x8B52, 0xB539, 0x8B53, 0xB53A, 0x8B54, 0xB53B,
+ 0x8B55, 0xB53C, 0x8B56, 0xB53D, 0x8B57, 0xB53E, 0x8B58, 0xB53F, 0x8B59, 0xB542, 0x8B5A, 0xB546, 0x8B61, 0xB547, 0x8B62, 0xB548,
+ 0x8B63, 0xB549, 0x8B64, 0xB54A, 0x8B65, 0xB54E, 0x8B66, 0xB54F, 0x8B67, 0xB551, 0x8B68, 0xB552, 0x8B69, 0xB553, 0x8B6A, 0xB555,
+ 0x8B6B, 0xB556, 0x8B6C, 0xB557, 0x8B6D, 0xB558, 0x8B6E, 0xB559, 0x8B6F, 0xB55A, 0x8B70, 0xB55B, 0x8B71, 0xB55E, 0x8B72, 0xB562,
+ 0x8B73, 0xB563, 0x8B74, 0xB564, 0x8B75, 0xB565, 0x8B76, 0xB566, 0x8B77, 0xB567, 0x8B78, 0xB568, 0x8B79, 0xB569, 0x8B7A, 0xB56A,
+ 0x8B81, 0xB56B, 0x8B82, 0xB56C, 0x8B83, 0xB56D, 0x8B84, 0xB56E, 0x8B85, 0xB56F, 0x8B86, 0xB570, 0x8B87, 0xB571, 0x8B88, 0xB572,
+ 0x8B89, 0xB573, 0x8B8A, 0xB574, 0x8B8B, 0xB575, 0x8B8C, 0xB576, 0x8B8D, 0xB577, 0x8B8E, 0xB578, 0x8B8F, 0xB579, 0x8B90, 0xB57A,
+ 0x8B91, 0xB57B, 0x8B92, 0xB57C, 0x8B93, 0xB57D, 0x8B94, 0xB57E, 0x8B95, 0xB57F, 0x8B96, 0xB580, 0x8B97, 0xB581, 0x8B98, 0xB582,
+ 0x8B99, 0xB583, 0x8B9A, 0xB584, 0x8B9B, 0xB585, 0x8B9C, 0xB586, 0x8B9D, 0xB587, 0x8B9E, 0xB588, 0x8B9F, 0xB589, 0x8BA0, 0xB58A,
+ 0x8BA1, 0xB58B, 0x8BA2, 0xB58C, 0x8BA3, 0xB58D, 0x8BA4, 0xB58E, 0x8BA5, 0xB58F, 0x8BA6, 0xB590, 0x8BA7, 0xB591, 0x8BA8, 0xB592,
+ 0x8BA9, 0xB593, 0x8BAA, 0xB594, 0x8BAB, 0xB595, 0x8BAC, 0xB596, 0x8BAD, 0xB597, 0x8BAE, 0xB598, 0x8BAF, 0xB599, 0x8BB0, 0xB59A,
+ 0x8BB1, 0xB59B, 0x8BB2, 0xB59C, 0x8BB3, 0xB59D, 0x8BB4, 0xB59E, 0x8BB5, 0xB59F, 0x8BB6, 0xB5A2, 0x8BB7, 0xB5A3, 0x8BB8, 0xB5A5,
+ 0x8BB9, 0xB5A6, 0x8BBA, 0xB5A7, 0x8BBB, 0xB5A9, 0x8BBC, 0xB5AC, 0x8BBD, 0xB5AD, 0x8BBE, 0xB5AE, 0x8BBF, 0xB5AF, 0x8BC0, 0xB5B2,
+ 0x8BC1, 0xB5B6, 0x8BC2, 0xB5B7, 0x8BC3, 0xB5B8, 0x8BC4, 0xB5B9, 0x8BC5, 0xB5BA, 0x8BC6, 0xB5BE, 0x8BC7, 0xB5BF, 0x8BC8, 0xB5C1,
+ 0x8BC9, 0xB5C2, 0x8BCA, 0xB5C3, 0x8BCB, 0xB5C5, 0x8BCC, 0xB5C6, 0x8BCD, 0xB5C7, 0x8BCE, 0xB5C8, 0x8BCF, 0xB5C9, 0x8BD0, 0xB5CA,
+ 0x8BD1, 0xB5CB, 0x8BD2, 0xB5CE, 0x8BD3, 0xB5D2, 0x8BD4, 0xB5D3, 0x8BD5, 0xB5D4, 0x8BD6, 0xB5D5, 0x8BD7, 0xB5D6, 0x8BD8, 0xB5D7,
+ 0x8BD9, 0xB5D9, 0x8BDA, 0xB5DA, 0x8BDB, 0xB5DB, 0x8BDC, 0xB5DC, 0x8BDD, 0xB5DD, 0x8BDE, 0xB5DE, 0x8BDF, 0xB5DF, 0x8BE0, 0xB5E0,
+ 0x8BE1, 0xB5E1, 0x8BE2, 0xB5E2, 0x8BE3, 0xB5E3, 0x8BE4, 0xB5E4, 0x8BE5, 0xB5E5, 0x8BE6, 0xB5E6, 0x8BE7, 0xB5E7, 0x8BE8, 0xB5E8,
+ 0x8BE9, 0xB5E9, 0x8BEA, 0xB5EA, 0x8BEB, 0xB5EB, 0x8BEC, 0xB5ED, 0x8BED, 0xB5EE, 0x8BEE, 0xB5EF, 0x8BEF, 0xB5F0, 0x8BF0, 0xB5F1,
+ 0x8BF1, 0xB5F2, 0x8BF2, 0xB5F3, 0x8BF3, 0xB5F4, 0x8BF4, 0xB5F5, 0x8BF5, 0xB5F6, 0x8BF6, 0xB5F7, 0x8BF7, 0xB5F8, 0x8BF8, 0xB5F9,
+ 0x8BF9, 0xB5FA, 0x8BFA, 0xB5FB, 0x8BFB, 0xB5FC, 0x8BFC, 0xB5FD, 0x8BFD, 0xB5FE, 0x8BFE, 0xB5FF, 0x8C41, 0xB600, 0x8C42, 0xB601,
+ 0x8C43, 0xB602, 0x8C44, 0xB603, 0x8C45, 0xB604, 0x8C46, 0xB605, 0x8C47, 0xB606, 0x8C48, 0xB607, 0x8C49, 0xB608, 0x8C4A, 0xB609,
+ 0x8C4B, 0xB60A, 0x8C4C, 0xB60B, 0x8C4D, 0xB60C, 0x8C4E, 0xB60D, 0x8C4F, 0xB60E, 0x8C50, 0xB60F, 0x8C51, 0xB612, 0x8C52, 0xB613,
+ 0x8C53, 0xB615, 0x8C54, 0xB616, 0x8C55, 0xB617, 0x8C56, 0xB619, 0x8C57, 0xB61A, 0x8C58, 0xB61B, 0x8C59, 0xB61C, 0x8C5A, 0xB61D,
+ 0x8C61, 0xB61E, 0x8C62, 0xB61F, 0x8C63, 0xB620, 0x8C64, 0xB621, 0x8C65, 0xB622, 0x8C66, 0xB623, 0x8C67, 0xB624, 0x8C68, 0xB626,
+ 0x8C69, 0xB627, 0x8C6A, 0xB628, 0x8C6B, 0xB629, 0x8C6C, 0xB62A, 0x8C6D, 0xB62B, 0x8C6E, 0xB62D, 0x8C6F, 0xB62E, 0x8C70, 0xB62F,
+ 0x8C71, 0xB630, 0x8C72, 0xB631, 0x8C73, 0xB632, 0x8C74, 0xB633, 0x8C75, 0xB635, 0x8C76, 0xB636, 0x8C77, 0xB637, 0x8C78, 0xB638,
+ 0x8C79, 0xB639, 0x8C7A, 0xB63A, 0x8C81, 0xB63B, 0x8C82, 0xB63C, 0x8C83, 0xB63D, 0x8C84, 0xB63E, 0x8C85, 0xB63F, 0x8C86, 0xB640,
+ 0x8C87, 0xB641, 0x8C88, 0xB642, 0x8C89, 0xB643, 0x8C8A, 0xB644, 0x8C8B, 0xB645, 0x8C8C, 0xB646, 0x8C8D, 0xB647, 0x8C8E, 0xB649,
+ 0x8C8F, 0xB64A, 0x8C90, 0xB64B, 0x8C91, 0xB64C, 0x8C92, 0xB64D, 0x8C93, 0xB64E, 0x8C94, 0xB64F, 0x8C95, 0xB650, 0x8C96, 0xB651,
+ 0x8C97, 0xB652, 0x8C98, 0xB653, 0x8C99, 0xB654, 0x8C9A, 0xB655, 0x8C9B, 0xB656, 0x8C9C, 0xB657, 0x8C9D, 0xB658, 0x8C9E, 0xB659,
+ 0x8C9F, 0xB65A, 0x8CA0, 0xB65B, 0x8CA1, 0xB65C, 0x8CA2, 0xB65D, 0x8CA3, 0xB65E, 0x8CA4, 0xB65F, 0x8CA5, 0xB660, 0x8CA6, 0xB661,
+ 0x8CA7, 0xB662, 0x8CA8, 0xB663, 0x8CA9, 0xB665, 0x8CAA, 0xB666, 0x8CAB, 0xB667, 0x8CAC, 0xB669, 0x8CAD, 0xB66A, 0x8CAE, 0xB66B,
+ 0x8CAF, 0xB66C, 0x8CB0, 0xB66D, 0x8CB1, 0xB66E, 0x8CB2, 0xB66F, 0x8CB3, 0xB670, 0x8CB4, 0xB671, 0x8CB5, 0xB672, 0x8CB6, 0xB673,
+ 0x8CB7, 0xB674, 0x8CB8, 0xB675, 0x8CB9, 0xB676, 0x8CBA, 0xB677, 0x8CBB, 0xB678, 0x8CBC, 0xB679, 0x8CBD, 0xB67A, 0x8CBE, 0xB67B,
+ 0x8CBF, 0xB67C, 0x8CC0, 0xB67D, 0x8CC1, 0xB67E, 0x8CC2, 0xB67F, 0x8CC3, 0xB680, 0x8CC4, 0xB681, 0x8CC5, 0xB682, 0x8CC6, 0xB683,
+ 0x8CC7, 0xB684, 0x8CC8, 0xB685, 0x8CC9, 0xB686, 0x8CCA, 0xB687, 0x8CCB, 0xB688, 0x8CCC, 0xB689, 0x8CCD, 0xB68A, 0x8CCE, 0xB68B,
+ 0x8CCF, 0xB68C, 0x8CD0, 0xB68D, 0x8CD1, 0xB68E, 0x8CD2, 0xB68F, 0x8CD3, 0xB690, 0x8CD4, 0xB691, 0x8CD5, 0xB692, 0x8CD6, 0xB693,
+ 0x8CD7, 0xB694, 0x8CD8, 0xB695, 0x8CD9, 0xB696, 0x8CDA, 0xB697, 0x8CDB, 0xB698, 0x8CDC, 0xB699, 0x8CDD, 0xB69A, 0x8CDE, 0xB69B,
+ 0x8CDF, 0xB69E, 0x8CE0, 0xB69F, 0x8CE1, 0xB6A1, 0x8CE2, 0xB6A2, 0x8CE3, 0xB6A3, 0x8CE4, 0xB6A5, 0x8CE5, 0xB6A6, 0x8CE6, 0xB6A7,
+ 0x8CE7, 0xB6A8, 0x8CE8, 0xB6A9, 0x8CE9, 0xB6AA, 0x8CEA, 0xB6AD, 0x8CEB, 0xB6AE, 0x8CEC, 0xB6AF, 0x8CED, 0xB6B0, 0x8CEE, 0xB6B2,
+ 0x8CEF, 0xB6B3, 0x8CF0, 0xB6B4, 0x8CF1, 0xB6B5, 0x8CF2, 0xB6B6, 0x8CF3, 0xB6B7, 0x8CF4, 0xB6B8, 0x8CF5, 0xB6B9, 0x8CF6, 0xB6BA,
+ 0x8CF7, 0xB6BB, 0x8CF8, 0xB6BC, 0x8CF9, 0xB6BD, 0x8CFA, 0xB6BE, 0x8CFB, 0xB6BF, 0x8CFC, 0xB6C0, 0x8CFD, 0xB6C1, 0x8CFE, 0xB6C2,
+ 0x8D41, 0xB6C3, 0x8D42, 0xB6C4, 0x8D43, 0xB6C5, 0x8D44, 0xB6C6, 0x8D45, 0xB6C7, 0x8D46, 0xB6C8, 0x8D47, 0xB6C9, 0x8D48, 0xB6CA,
+ 0x8D49, 0xB6CB, 0x8D4A, 0xB6CC, 0x8D4B, 0xB6CD, 0x8D4C, 0xB6CE, 0x8D4D, 0xB6CF, 0x8D4E, 0xB6D0, 0x8D4F, 0xB6D1, 0x8D50, 0xB6D2,
+ 0x8D51, 0xB6D3, 0x8D52, 0xB6D5, 0x8D53, 0xB6D6, 0x8D54, 0xB6D7, 0x8D55, 0xB6D8, 0x8D56, 0xB6D9, 0x8D57, 0xB6DA, 0x8D58, 0xB6DB,
+ 0x8D59, 0xB6DC, 0x8D5A, 0xB6DD, 0x8D61, 0xB6DE, 0x8D62, 0xB6DF, 0x8D63, 0xB6E0, 0x8D64, 0xB6E1, 0x8D65, 0xB6E2, 0x8D66, 0xB6E3,
+ 0x8D67, 0xB6E4, 0x8D68, 0xB6E5, 0x8D69, 0xB6E6, 0x8D6A, 0xB6E7, 0x8D6B, 0xB6E8, 0x8D6C, 0xB6E9, 0x8D6D, 0xB6EA, 0x8D6E, 0xB6EB,
+ 0x8D6F, 0xB6EC, 0x8D70, 0xB6ED, 0x8D71, 0xB6EE, 0x8D72, 0xB6EF, 0x8D73, 0xB6F1, 0x8D74, 0xB6F2, 0x8D75, 0xB6F3, 0x8D76, 0xB6F5,
+ 0x8D77, 0xB6F6, 0x8D78, 0xB6F7, 0x8D79, 0xB6F9, 0x8D7A, 0xB6FA, 0x8D81, 0xB6FB, 0x8D82, 0xB6FC, 0x8D83, 0xB6FD, 0x8D84, 0xB6FE,
+ 0x8D85, 0xB6FF, 0x8D86, 0xB702, 0x8D87, 0xB703, 0x8D88, 0xB704, 0x8D89, 0xB706, 0x8D8A, 0xB707, 0x8D8B, 0xB708, 0x8D8C, 0xB709,
+ 0x8D8D, 0xB70A, 0x8D8E, 0xB70B, 0x8D8F, 0xB70C, 0x8D90, 0xB70D, 0x8D91, 0xB70E, 0x8D92, 0xB70F, 0x8D93, 0xB710, 0x8D94, 0xB711,
+ 0x8D95, 0xB712, 0x8D96, 0xB713, 0x8D97, 0xB714, 0x8D98, 0xB715, 0x8D99, 0xB716, 0x8D9A, 0xB717, 0x8D9B, 0xB718, 0x8D9C, 0xB719,
+ 0x8D9D, 0xB71A, 0x8D9E, 0xB71B, 0x8D9F, 0xB71C, 0x8DA0, 0xB71D, 0x8DA1, 0xB71E, 0x8DA2, 0xB71F, 0x8DA3, 0xB720, 0x8DA4, 0xB721,
+ 0x8DA5, 0xB722, 0x8DA6, 0xB723, 0x8DA7, 0xB724, 0x8DA8, 0xB725, 0x8DA9, 0xB726, 0x8DAA, 0xB727, 0x8DAB, 0xB72A, 0x8DAC, 0xB72B,
+ 0x8DAD, 0xB72D, 0x8DAE, 0xB72E, 0x8DAF, 0xB731, 0x8DB0, 0xB732, 0x8DB1, 0xB733, 0x8DB2, 0xB734, 0x8DB3, 0xB735, 0x8DB4, 0xB736,
+ 0x8DB5, 0xB737, 0x8DB6, 0xB73A, 0x8DB7, 0xB73C, 0x8DB8, 0xB73D, 0x8DB9, 0xB73E, 0x8DBA, 0xB73F, 0x8DBB, 0xB740, 0x8DBC, 0xB741,
+ 0x8DBD, 0xB742, 0x8DBE, 0xB743, 0x8DBF, 0xB745, 0x8DC0, 0xB746, 0x8DC1, 0xB747, 0x8DC2, 0xB749, 0x8DC3, 0xB74A, 0x8DC4, 0xB74B,
+ 0x8DC5, 0xB74D, 0x8DC6, 0xB74E, 0x8DC7, 0xB74F, 0x8DC8, 0xB750, 0x8DC9, 0xB751, 0x8DCA, 0xB752, 0x8DCB, 0xB753, 0x8DCC, 0xB756,
+ 0x8DCD, 0xB757, 0x8DCE, 0xB758, 0x8DCF, 0xB759, 0x8DD0, 0xB75A, 0x8DD1, 0xB75B, 0x8DD2, 0xB75C, 0x8DD3, 0xB75D, 0x8DD4, 0xB75E,
+ 0x8DD5, 0xB75F, 0x8DD6, 0xB761, 0x8DD7, 0xB762, 0x8DD8, 0xB763, 0x8DD9, 0xB765, 0x8DDA, 0xB766, 0x8DDB, 0xB767, 0x8DDC, 0xB769,
+ 0x8DDD, 0xB76A, 0x8DDE, 0xB76B, 0x8DDF, 0xB76C, 0x8DE0, 0xB76D, 0x8DE1, 0xB76E, 0x8DE2, 0xB76F, 0x8DE3, 0xB772, 0x8DE4, 0xB774,
+ 0x8DE5, 0xB776, 0x8DE6, 0xB777, 0x8DE7, 0xB778, 0x8DE8, 0xB779, 0x8DE9, 0xB77A, 0x8DEA, 0xB77B, 0x8DEB, 0xB77E, 0x8DEC, 0xB77F,
+ 0x8DED, 0xB781, 0x8DEE, 0xB782, 0x8DEF, 0xB783, 0x8DF0, 0xB785, 0x8DF1, 0xB786, 0x8DF2, 0xB787, 0x8DF3, 0xB788, 0x8DF4, 0xB789,
+ 0x8DF5, 0xB78A, 0x8DF6, 0xB78B, 0x8DF7, 0xB78E, 0x8DF8, 0xB793, 0x8DF9, 0xB794, 0x8DFA, 0xB795, 0x8DFB, 0xB79A, 0x8DFC, 0xB79B,
+ 0x8DFD, 0xB79D, 0x8DFE, 0xB79E, 0x8E41, 0xB79F, 0x8E42, 0xB7A1, 0x8E43, 0xB7A2, 0x8E44, 0xB7A3, 0x8E45, 0xB7A4, 0x8E46, 0xB7A5,
+ 0x8E47, 0xB7A6, 0x8E48, 0xB7A7, 0x8E49, 0xB7AA, 0x8E4A, 0xB7AE, 0x8E4B, 0xB7AF, 0x8E4C, 0xB7B0, 0x8E4D, 0xB7B1, 0x8E4E, 0xB7B2,
+ 0x8E4F, 0xB7B3, 0x8E50, 0xB7B6, 0x8E51, 0xB7B7, 0x8E52, 0xB7B9, 0x8E53, 0xB7BA, 0x8E54, 0xB7BB, 0x8E55, 0xB7BC, 0x8E56, 0xB7BD,
+ 0x8E57, 0xB7BE, 0x8E58, 0xB7BF, 0x8E59, 0xB7C0, 0x8E5A, 0xB7C1, 0x8E61, 0xB7C2, 0x8E62, 0xB7C3, 0x8E63, 0xB7C4, 0x8E64, 0xB7C5,
+ 0x8E65, 0xB7C6, 0x8E66, 0xB7C8, 0x8E67, 0xB7CA, 0x8E68, 0xB7CB, 0x8E69, 0xB7CC, 0x8E6A, 0xB7CD, 0x8E6B, 0xB7CE, 0x8E6C, 0xB7CF,
+ 0x8E6D, 0xB7D0, 0x8E6E, 0xB7D1, 0x8E6F, 0xB7D2, 0x8E70, 0xB7D3, 0x8E71, 0xB7D4, 0x8E72, 0xB7D5, 0x8E73, 0xB7D6, 0x8E74, 0xB7D7,
+ 0x8E75, 0xB7D8, 0x8E76, 0xB7D9, 0x8E77, 0xB7DA, 0x8E78, 0xB7DB, 0x8E79, 0xB7DC, 0x8E7A, 0xB7DD, 0x8E81, 0xB7DE, 0x8E82, 0xB7DF,
+ 0x8E83, 0xB7E0, 0x8E84, 0xB7E1, 0x8E85, 0xB7E2, 0x8E86, 0xB7E3, 0x8E87, 0xB7E4, 0x8E88, 0xB7E5, 0x8E89, 0xB7E6, 0x8E8A, 0xB7E7,
+ 0x8E8B, 0xB7E8, 0x8E8C, 0xB7E9, 0x8E8D, 0xB7EA, 0x8E8E, 0xB7EB, 0x8E8F, 0xB7EE, 0x8E90, 0xB7EF, 0x8E91, 0xB7F1, 0x8E92, 0xB7F2,
+ 0x8E93, 0xB7F3, 0x8E94, 0xB7F5, 0x8E95, 0xB7F6, 0x8E96, 0xB7F7, 0x8E97, 0xB7F8, 0x8E98, 0xB7F9, 0x8E99, 0xB7FA, 0x8E9A, 0xB7FB,
+ 0x8E9B, 0xB7FE, 0x8E9C, 0xB802, 0x8E9D, 0xB803, 0x8E9E, 0xB804, 0x8E9F, 0xB805, 0x8EA0, 0xB806, 0x8EA1, 0xB80A, 0x8EA2, 0xB80B,
+ 0x8EA3, 0xB80D, 0x8EA4, 0xB80E, 0x8EA5, 0xB80F, 0x8EA6, 0xB811, 0x8EA7, 0xB812, 0x8EA8, 0xB813, 0x8EA9, 0xB814, 0x8EAA, 0xB815,
+ 0x8EAB, 0xB816, 0x8EAC, 0xB817, 0x8EAD, 0xB81A, 0x8EAE, 0xB81C, 0x8EAF, 0xB81E, 0x8EB0, 0xB81F, 0x8EB1, 0xB820, 0x8EB2, 0xB821,
+ 0x8EB3, 0xB822, 0x8EB4, 0xB823, 0x8EB5, 0xB826, 0x8EB6, 0xB827, 0x8EB7, 0xB829, 0x8EB8, 0xB82A, 0x8EB9, 0xB82B, 0x8EBA, 0xB82D,
+ 0x8EBB, 0xB82E, 0x8EBC, 0xB82F, 0x8EBD, 0xB830, 0x8EBE, 0xB831, 0x8EBF, 0xB832, 0x8EC0, 0xB833, 0x8EC1, 0xB836, 0x8EC2, 0xB83A,
+ 0x8EC3, 0xB83B, 0x8EC4, 0xB83C, 0x8EC5, 0xB83D, 0x8EC6, 0xB83E, 0x8EC7, 0xB83F, 0x8EC8, 0xB841, 0x8EC9, 0xB842, 0x8ECA, 0xB843,
+ 0x8ECB, 0xB845, 0x8ECC, 0xB846, 0x8ECD, 0xB847, 0x8ECE, 0xB848, 0x8ECF, 0xB849, 0x8ED0, 0xB84A, 0x8ED1, 0xB84B, 0x8ED2, 0xB84C,
+ 0x8ED3, 0xB84D, 0x8ED4, 0xB84E, 0x8ED5, 0xB84F, 0x8ED6, 0xB850, 0x8ED7, 0xB852, 0x8ED8, 0xB854, 0x8ED9, 0xB855, 0x8EDA, 0xB856,
+ 0x8EDB, 0xB857, 0x8EDC, 0xB858, 0x8EDD, 0xB859, 0x8EDE, 0xB85A, 0x8EDF, 0xB85B, 0x8EE0, 0xB85E, 0x8EE1, 0xB85F, 0x8EE2, 0xB861,
+ 0x8EE3, 0xB862, 0x8EE4, 0xB863, 0x8EE5, 0xB865, 0x8EE6, 0xB866, 0x8EE7, 0xB867, 0x8EE8, 0xB868, 0x8EE9, 0xB869, 0x8EEA, 0xB86A,
+ 0x8EEB, 0xB86B, 0x8EEC, 0xB86E, 0x8EED, 0xB870, 0x8EEE, 0xB872, 0x8EEF, 0xB873, 0x8EF0, 0xB874, 0x8EF1, 0xB875, 0x8EF2, 0xB876,
+ 0x8EF3, 0xB877, 0x8EF4, 0xB879, 0x8EF5, 0xB87A, 0x8EF6, 0xB87B, 0x8EF7, 0xB87D, 0x8EF8, 0xB87E, 0x8EF9, 0xB87F, 0x8EFA, 0xB880,
+ 0x8EFB, 0xB881, 0x8EFC, 0xB882, 0x8EFD, 0xB883, 0x8EFE, 0xB884, 0x8F41, 0xB885, 0x8F42, 0xB886, 0x8F43, 0xB887, 0x8F44, 0xB888,
+ 0x8F45, 0xB889, 0x8F46, 0xB88A, 0x8F47, 0xB88B, 0x8F48, 0xB88C, 0x8F49, 0xB88E, 0x8F4A, 0xB88F, 0x8F4B, 0xB890, 0x8F4C, 0xB891,
+ 0x8F4D, 0xB892, 0x8F4E, 0xB893, 0x8F4F, 0xB894, 0x8F50, 0xB895, 0x8F51, 0xB896, 0x8F52, 0xB897, 0x8F53, 0xB898, 0x8F54, 0xB899,
+ 0x8F55, 0xB89A, 0x8F56, 0xB89B, 0x8F57, 0xB89C, 0x8F58, 0xB89D, 0x8F59, 0xB89E, 0x8F5A, 0xB89F, 0x8F61, 0xB8A0, 0x8F62, 0xB8A1,
+ 0x8F63, 0xB8A2, 0x8F64, 0xB8A3, 0x8F65, 0xB8A4, 0x8F66, 0xB8A5, 0x8F67, 0xB8A6, 0x8F68, 0xB8A7, 0x8F69, 0xB8A9, 0x8F6A, 0xB8AA,
+ 0x8F6B, 0xB8AB, 0x8F6C, 0xB8AC, 0x8F6D, 0xB8AD, 0x8F6E, 0xB8AE, 0x8F6F, 0xB8AF, 0x8F70, 0xB8B1, 0x8F71, 0xB8B2, 0x8F72, 0xB8B3,
+ 0x8F73, 0xB8B5, 0x8F74, 0xB8B6, 0x8F75, 0xB8B7, 0x8F76, 0xB8B9, 0x8F77, 0xB8BA, 0x8F78, 0xB8BB, 0x8F79, 0xB8BC, 0x8F7A, 0xB8BD,
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+ 0x9781, 0xBFB9, 0x9782, 0xBFBA, 0x9783, 0xBFBB, 0x9784, 0xBFBC, 0x9785, 0xBFBD, 0x9786, 0xBFBE, 0x9787, 0xBFBF, 0x9788, 0xBFC0,
+ 0x9789, 0xBFC1, 0x978A, 0xBFC2, 0x978B, 0xBFC3, 0x978C, 0xBFC4, 0x978D, 0xBFC6, 0x978E, 0xBFC7, 0x978F, 0xBFC8, 0x9790, 0xBFC9,
+ 0x9791, 0xBFCA, 0x9792, 0xBFCB, 0x9793, 0xBFCE, 0x9794, 0xBFCF, 0x9795, 0xBFD1, 0x9796, 0xBFD2, 0x9797, 0xBFD3, 0x9798, 0xBFD5,
+ 0x9799, 0xBFD6, 0x979A, 0xBFD7, 0x979B, 0xBFD8, 0x979C, 0xBFD9, 0x979D, 0xBFDA, 0x979E, 0xBFDB, 0x979F, 0xBFDD, 0x97A0, 0xBFDE,
+ 0x97A1, 0xBFE0, 0x97A2, 0xBFE2, 0x97A3, 0xBFE3, 0x97A4, 0xBFE4, 0x97A5, 0xBFE5, 0x97A6, 0xBFE6, 0x97A7, 0xBFE7, 0x97A8, 0xBFE8,
+ 0x97A9, 0xBFE9, 0x97AA, 0xBFEA, 0x97AB, 0xBFEB, 0x97AC, 0xBFEC, 0x97AD, 0xBFED, 0x97AE, 0xBFEE, 0x97AF, 0xBFEF, 0x97B0, 0xBFF0,
+ 0x97B1, 0xBFF1, 0x97B2, 0xBFF2, 0x97B3, 0xBFF3, 0x97B4, 0xBFF4, 0x97B5, 0xBFF5, 0x97B6, 0xBFF6, 0x97B7, 0xBFF7, 0x97B8, 0xBFF8,
+ 0x97B9, 0xBFF9, 0x97BA, 0xBFFA, 0x97BB, 0xBFFB, 0x97BC, 0xBFFC, 0x97BD, 0xBFFD, 0x97BE, 0xBFFE, 0x97BF, 0xBFFF, 0x97C0, 0xC000,
+ 0x97C1, 0xC001, 0x97C2, 0xC002, 0x97C3, 0xC003, 0x97C4, 0xC004, 0x97C5, 0xC005, 0x97C6, 0xC006, 0x97C7, 0xC007, 0x97C8, 0xC008,
+ 0x97C9, 0xC009, 0x97CA, 0xC00A, 0x97CB, 0xC00B, 0x97CC, 0xC00C, 0x97CD, 0xC00D, 0x97CE, 0xC00E, 0x97CF, 0xC00F, 0x97D0, 0xC010,
+ 0x97D1, 0xC011, 0x97D2, 0xC012, 0x97D3, 0xC013, 0x97D4, 0xC014, 0x97D5, 0xC015, 0x97D6, 0xC016, 0x97D7, 0xC017, 0x97D8, 0xC018,
+ 0x97D9, 0xC019, 0x97DA, 0xC01A, 0x97DB, 0xC01B, 0x97DC, 0xC01C, 0x97DD, 0xC01D, 0x97DE, 0xC01E, 0x97DF, 0xC01F, 0x97E0, 0xC020,
+ 0x97E1, 0xC021, 0x97E2, 0xC022, 0x97E3, 0xC023, 0x97E4, 0xC024, 0x97E5, 0xC025, 0x97E6, 0xC026, 0x97E7, 0xC027, 0x97E8, 0xC028,
+ 0x97E9, 0xC029, 0x97EA, 0xC02A, 0x97EB, 0xC02B, 0x97EC, 0xC02C, 0x97ED, 0xC02D, 0x97EE, 0xC02E, 0x97EF, 0xC02F, 0x97F0, 0xC030,
+ 0x97F1, 0xC031, 0x97F2, 0xC032, 0x97F3, 0xC033, 0x97F4, 0xC034, 0x97F5, 0xC035, 0x97F6, 0xC036, 0x97F7, 0xC037, 0x97F8, 0xC038,
+ 0x97F9, 0xC039, 0x97FA, 0xC03A, 0x97FB, 0xC03B, 0x97FC, 0xC03D, 0x97FD, 0xC03E, 0x97FE, 0xC03F, 0x9841, 0xC040, 0x9842, 0xC041,
+ 0x9843, 0xC042, 0x9844, 0xC043, 0x9845, 0xC044, 0x9846, 0xC045, 0x9847, 0xC046, 0x9848, 0xC047, 0x9849, 0xC048, 0x984A, 0xC049,
+ 0x984B, 0xC04A, 0x984C, 0xC04B, 0x984D, 0xC04C, 0x984E, 0xC04D, 0x984F, 0xC04E, 0x9850, 0xC04F, 0x9851, 0xC050, 0x9852, 0xC052,
+ 0x9853, 0xC053, 0x9854, 0xC054, 0x9855, 0xC055, 0x9856, 0xC056, 0x9857, 0xC057, 0x9858, 0xC059, 0x9859, 0xC05A, 0x985A, 0xC05B,
+ 0x9861, 0xC05D, 0x9862, 0xC05E, 0x9863, 0xC05F, 0x9864, 0xC061, 0x9865, 0xC062, 0x9866, 0xC063, 0x9867, 0xC064, 0x9868, 0xC065,
+ 0x9869, 0xC066, 0x986A, 0xC067, 0x986B, 0xC06A, 0x986C, 0xC06B, 0x986D, 0xC06C, 0x986E, 0xC06D, 0x986F, 0xC06E, 0x9870, 0xC06F,
+ 0x9871, 0xC070, 0x9872, 0xC071, 0x9873, 0xC072, 0x9874, 0xC073, 0x9875, 0xC074, 0x9876, 0xC075, 0x9877, 0xC076, 0x9878, 0xC077,
+ 0x9879, 0xC078, 0x987A, 0xC079, 0x9881, 0xC07A, 0x9882, 0xC07B, 0x9883, 0xC07C, 0x9884, 0xC07D, 0x9885, 0xC07E, 0x9886, 0xC07F,
+ 0x9887, 0xC080, 0x9888, 0xC081, 0x9889, 0xC082, 0x988A, 0xC083, 0x988B, 0xC084, 0x988C, 0xC085, 0x988D, 0xC086, 0x988E, 0xC087,
+ 0x988F, 0xC088, 0x9890, 0xC089, 0x9891, 0xC08A, 0x9892, 0xC08B, 0x9893, 0xC08C, 0x9894, 0xC08D, 0x9895, 0xC08E, 0x9896, 0xC08F,
+ 0x9897, 0xC092, 0x9898, 0xC093, 0x9899, 0xC095, 0x989A, 0xC096, 0x989B, 0xC097, 0x989C, 0xC099, 0x989D, 0xC09A, 0x989E, 0xC09B,
+ 0x989F, 0xC09C, 0x98A0, 0xC09D, 0x98A1, 0xC09E, 0x98A2, 0xC09F, 0x98A3, 0xC0A2, 0x98A4, 0xC0A4, 0x98A5, 0xC0A6, 0x98A6, 0xC0A7,
+ 0x98A7, 0xC0A8, 0x98A8, 0xC0A9, 0x98A9, 0xC0AA, 0x98AA, 0xC0AB, 0x98AB, 0xC0AE, 0x98AC, 0xC0B1, 0x98AD, 0xC0B2, 0x98AE, 0xC0B7,
+ 0x98AF, 0xC0B8, 0x98B0, 0xC0B9, 0x98B1, 0xC0BA, 0x98B2, 0xC0BB, 0x98B3, 0xC0BE, 0x98B4, 0xC0C2, 0x98B5, 0xC0C3, 0x98B6, 0xC0C4,
+ 0x98B7, 0xC0C6, 0x98B8, 0xC0C7, 0x98B9, 0xC0CA, 0x98BA, 0xC0CB, 0x98BB, 0xC0CD, 0x98BC, 0xC0CE, 0x98BD, 0xC0CF, 0x98BE, 0xC0D1,
+ 0x98BF, 0xC0D2, 0x98C0, 0xC0D3, 0x98C1, 0xC0D4, 0x98C2, 0xC0D5, 0x98C3, 0xC0D6, 0x98C4, 0xC0D7, 0x98C5, 0xC0DA, 0x98C6, 0xC0DE,
+ 0x98C7, 0xC0DF, 0x98C8, 0xC0E0, 0x98C9, 0xC0E1, 0x98CA, 0xC0E2, 0x98CB, 0xC0E3, 0x98CC, 0xC0E6, 0x98CD, 0xC0E7, 0x98CE, 0xC0E9,
+ 0x98CF, 0xC0EA, 0x98D0, 0xC0EB, 0x98D1, 0xC0ED, 0x98D2, 0xC0EE, 0x98D3, 0xC0EF, 0x98D4, 0xC0F0, 0x98D5, 0xC0F1, 0x98D6, 0xC0F2,
+ 0x98D7, 0xC0F3, 0x98D8, 0xC0F6, 0x98D9, 0xC0F8, 0x98DA, 0xC0FA, 0x98DB, 0xC0FB, 0x98DC, 0xC0FC, 0x98DD, 0xC0FD, 0x98DE, 0xC0FE,
+ 0x98DF, 0xC0FF, 0x98E0, 0xC101, 0x98E1, 0xC102, 0x98E2, 0xC103, 0x98E3, 0xC105, 0x98E4, 0xC106, 0x98E5, 0xC107, 0x98E6, 0xC109,
+ 0x98E7, 0xC10A, 0x98E8, 0xC10B, 0x98E9, 0xC10C, 0x98EA, 0xC10D, 0x98EB, 0xC10E, 0x98EC, 0xC10F, 0x98ED, 0xC111, 0x98EE, 0xC112,
+ 0x98EF, 0xC113, 0x98F0, 0xC114, 0x98F1, 0xC116, 0x98F2, 0xC117, 0x98F3, 0xC118, 0x98F4, 0xC119, 0x98F5, 0xC11A, 0x98F6, 0xC11B,
+ 0x98F7, 0xC121, 0x98F8, 0xC122, 0x98F9, 0xC125, 0x98FA, 0xC128, 0x98FB, 0xC129, 0x98FC, 0xC12A, 0x98FD, 0xC12B, 0x98FE, 0xC12E,
+ 0x9941, 0xC132, 0x9942, 0xC133, 0x9943, 0xC134, 0x9944, 0xC135, 0x9945, 0xC137, 0x9946, 0xC13A, 0x9947, 0xC13B, 0x9948, 0xC13D,
+ 0x9949, 0xC13E, 0x994A, 0xC13F, 0x994B, 0xC141, 0x994C, 0xC142, 0x994D, 0xC143, 0x994E, 0xC144, 0x994F, 0xC145, 0x9950, 0xC146,
+ 0x9951, 0xC147, 0x9952, 0xC14A, 0x9953, 0xC14E, 0x9954, 0xC14F, 0x9955, 0xC150, 0x9956, 0xC151, 0x9957, 0xC152, 0x9958, 0xC153,
+ 0x9959, 0xC156, 0x995A, 0xC157, 0x9961, 0xC159, 0x9962, 0xC15A, 0x9963, 0xC15B, 0x9964, 0xC15D, 0x9965, 0xC15E, 0x9966, 0xC15F,
+ 0x9967, 0xC160, 0x9968, 0xC161, 0x9969, 0xC162, 0x996A, 0xC163, 0x996B, 0xC166, 0x996C, 0xC16A, 0x996D, 0xC16B, 0x996E, 0xC16C,
+ 0x996F, 0xC16D, 0x9970, 0xC16E, 0x9971, 0xC16F, 0x9972, 0xC171, 0x9973, 0xC172, 0x9974, 0xC173, 0x9975, 0xC175, 0x9976, 0xC176,
+ 0x9977, 0xC177, 0x9978, 0xC179, 0x9979, 0xC17A, 0x997A, 0xC17B, 0x9981, 0xC17C, 0x9982, 0xC17D, 0x9983, 0xC17E, 0x9984, 0xC17F,
+ 0x9985, 0xC180, 0x9986, 0xC181, 0x9987, 0xC182, 0x9988, 0xC183, 0x9989, 0xC184, 0x998A, 0xC186, 0x998B, 0xC187, 0x998C, 0xC188,
+ 0x998D, 0xC189, 0x998E, 0xC18A, 0x998F, 0xC18B, 0x9990, 0xC18F, 0x9991, 0xC191, 0x9992, 0xC192, 0x9993, 0xC193, 0x9994, 0xC195,
+ 0x9995, 0xC197, 0x9996, 0xC198, 0x9997, 0xC199, 0x9998, 0xC19A, 0x9999, 0xC19B, 0x999A, 0xC19E, 0x999B, 0xC1A0, 0x999C, 0xC1A2,
+ 0x999D, 0xC1A3, 0x999E, 0xC1A4, 0x999F, 0xC1A6, 0x99A0, 0xC1A7, 0x99A1, 0xC1AA, 0x99A2, 0xC1AB, 0x99A3, 0xC1AD, 0x99A4, 0xC1AE,
+ 0x99A5, 0xC1AF, 0x99A6, 0xC1B1, 0x99A7, 0xC1B2, 0x99A8, 0xC1B3, 0x99A9, 0xC1B4, 0x99AA, 0xC1B5, 0x99AB, 0xC1B6, 0x99AC, 0xC1B7,
+ 0x99AD, 0xC1B8, 0x99AE, 0xC1B9, 0x99AF, 0xC1BA, 0x99B0, 0xC1BB, 0x99B1, 0xC1BC, 0x99B2, 0xC1BE, 0x99B3, 0xC1BF, 0x99B4, 0xC1C0,
+ 0x99B5, 0xC1C1, 0x99B6, 0xC1C2, 0x99B7, 0xC1C3, 0x99B8, 0xC1C5, 0x99B9, 0xC1C6, 0x99BA, 0xC1C7, 0x99BB, 0xC1C9, 0x99BC, 0xC1CA,
+ 0x99BD, 0xC1CB, 0x99BE, 0xC1CD, 0x99BF, 0xC1CE, 0x99C0, 0xC1CF, 0x99C1, 0xC1D0, 0x99C2, 0xC1D1, 0x99C3, 0xC1D2, 0x99C4, 0xC1D3,
+ 0x99C5, 0xC1D5, 0x99C6, 0xC1D6, 0x99C7, 0xC1D9, 0x99C8, 0xC1DA, 0x99C9, 0xC1DB, 0x99CA, 0xC1DC, 0x99CB, 0xC1DD, 0x99CC, 0xC1DE,
+ 0x99CD, 0xC1DF, 0x99CE, 0xC1E1, 0x99CF, 0xC1E2, 0x99D0, 0xC1E3, 0x99D1, 0xC1E5, 0x99D2, 0xC1E6, 0x99D3, 0xC1E7, 0x99D4, 0xC1E9,
+ 0x99D5, 0xC1EA, 0x99D6, 0xC1EB, 0x99D7, 0xC1EC, 0x99D8, 0xC1ED, 0x99D9, 0xC1EE, 0x99DA, 0xC1EF, 0x99DB, 0xC1F2, 0x99DC, 0xC1F4,
+ 0x99DD, 0xC1F5, 0x99DE, 0xC1F6, 0x99DF, 0xC1F7, 0x99E0, 0xC1F8, 0x99E1, 0xC1F9, 0x99E2, 0xC1FA, 0x99E3, 0xC1FB, 0x99E4, 0xC1FE,
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+ 0x99FD, 0xC222, 0x99FE, 0xC223, 0x9A41, 0xC224, 0x9A42, 0xC225, 0x9A43, 0xC226, 0x9A44, 0xC227, 0x9A45, 0xC22A, 0x9A46, 0xC22C,
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+ 0x9A4F, 0xC23A, 0x9A50, 0xC23B, 0x9A51, 0xC23C, 0x9A52, 0xC23D, 0x9A53, 0xC23E, 0x9A54, 0xC23F, 0x9A55, 0xC240, 0x9A56, 0xC241,
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+ 0x9A65, 0xC24B, 0x9A66, 0xC24C, 0x9A67, 0xC24D, 0x9A68, 0xC24E, 0x9A69, 0xC24F, 0x9A6A, 0xC252, 0x9A6B, 0xC253, 0x9A6C, 0xC255,
+ 0x9A6D, 0xC256, 0x9A6E, 0xC257, 0x9A6F, 0xC259, 0x9A70, 0xC25A, 0x9A71, 0xC25B, 0x9A72, 0xC25C, 0x9A73, 0xC25D, 0x9A74, 0xC25E,
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+ 0x9A83, 0xC269, 0x9A84, 0xC26A, 0x9A85, 0xC26B, 0x9A86, 0xC26E, 0x9A87, 0xC26F, 0x9A88, 0xC271, 0x9A89, 0xC272, 0x9A8A, 0xC273,
+ 0x9A8B, 0xC275, 0x9A8C, 0xC276, 0x9A8D, 0xC277, 0x9A8E, 0xC278, 0x9A8F, 0xC279, 0x9A90, 0xC27A, 0x9A91, 0xC27B, 0x9A92, 0xC27E,
+ 0x9A93, 0xC280, 0x9A94, 0xC282, 0x9A95, 0xC283, 0x9A96, 0xC284, 0x9A97, 0xC285, 0x9A98, 0xC286, 0x9A99, 0xC287, 0x9A9A, 0xC28A,
+ 0x9A9B, 0xC28B, 0x9A9C, 0xC28C, 0x9A9D, 0xC28D, 0x9A9E, 0xC28E, 0x9A9F, 0xC28F, 0x9AA0, 0xC291, 0x9AA1, 0xC292, 0x9AA2, 0xC293,
+ 0x9AA3, 0xC294, 0x9AA4, 0xC295, 0x9AA5, 0xC296, 0x9AA6, 0xC297, 0x9AA7, 0xC299, 0x9AA8, 0xC29A, 0x9AA9, 0xC29C, 0x9AAA, 0xC29E,
+ 0x9AAB, 0xC29F, 0x9AAC, 0xC2A0, 0x9AAD, 0xC2A1, 0x9AAE, 0xC2A2, 0x9AAF, 0xC2A3, 0x9AB0, 0xC2A6, 0x9AB1, 0xC2A7, 0x9AB2, 0xC2A9,
+ 0x9AB3, 0xC2AA, 0x9AB4, 0xC2AB, 0x9AB5, 0xC2AE, 0x9AB6, 0xC2AF, 0x9AB7, 0xC2B0, 0x9AB8, 0xC2B1, 0x9AB9, 0xC2B2, 0x9ABA, 0xC2B3,
+ 0x9ABB, 0xC2B6, 0x9ABC, 0xC2B8, 0x9ABD, 0xC2BA, 0x9ABE, 0xC2BB, 0x9ABF, 0xC2BC, 0x9AC0, 0xC2BD, 0x9AC1, 0xC2BE, 0x9AC2, 0xC2BF,
+ 0x9AC3, 0xC2C0, 0x9AC4, 0xC2C1, 0x9AC5, 0xC2C2, 0x9AC6, 0xC2C3, 0x9AC7, 0xC2C4, 0x9AC8, 0xC2C5, 0x9AC9, 0xC2C6, 0x9ACA, 0xC2C7,
+ 0x9ACB, 0xC2C8, 0x9ACC, 0xC2C9, 0x9ACD, 0xC2CA, 0x9ACE, 0xC2CB, 0x9ACF, 0xC2CC, 0x9AD0, 0xC2CD, 0x9AD1, 0xC2CE, 0x9AD2, 0xC2CF,
+ 0x9AD3, 0xC2D0, 0x9AD4, 0xC2D1, 0x9AD5, 0xC2D2, 0x9AD6, 0xC2D3, 0x9AD7, 0xC2D4, 0x9AD8, 0xC2D5, 0x9AD9, 0xC2D6, 0x9ADA, 0xC2D7,
+ 0x9ADB, 0xC2D8, 0x9ADC, 0xC2D9, 0x9ADD, 0xC2DA, 0x9ADE, 0xC2DB, 0x9ADF, 0xC2DE, 0x9AE0, 0xC2DF, 0x9AE1, 0xC2E1, 0x9AE2, 0xC2E2,
+ 0x9AE3, 0xC2E5, 0x9AE4, 0xC2E6, 0x9AE5, 0xC2E7, 0x9AE6, 0xC2E8, 0x9AE7, 0xC2E9, 0x9AE8, 0xC2EA, 0x9AE9, 0xC2EE, 0x9AEA, 0xC2F0,
+ 0x9AEB, 0xC2F2, 0x9AEC, 0xC2F3, 0x9AED, 0xC2F4, 0x9AEE, 0xC2F5, 0x9AEF, 0xC2F7, 0x9AF0, 0xC2FA, 0x9AF1, 0xC2FD, 0x9AF2, 0xC2FE,
+ 0x9AF3, 0xC2FF, 0x9AF4, 0xC301, 0x9AF5, 0xC302, 0x9AF6, 0xC303, 0x9AF7, 0xC304, 0x9AF8, 0xC305, 0x9AF9, 0xC306, 0x9AFA, 0xC307,
+ 0x9AFB, 0xC30A, 0x9AFC, 0xC30B, 0x9AFD, 0xC30E, 0x9AFE, 0xC30F, 0x9B41, 0xC310, 0x9B42, 0xC311, 0x9B43, 0xC312, 0x9B44, 0xC316,
+ 0x9B45, 0xC317, 0x9B46, 0xC319, 0x9B47, 0xC31A, 0x9B48, 0xC31B, 0x9B49, 0xC31D, 0x9B4A, 0xC31E, 0x9B4B, 0xC31F, 0x9B4C, 0xC320,
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+ 0x9BB1, 0xC389, 0x9BB2, 0xC38A, 0x9BB3, 0xC38B, 0x9BB4, 0xC38D, 0x9BB5, 0xC38E, 0x9BB6, 0xC38F, 0x9BB7, 0xC390, 0x9BB8, 0xC391,
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+ 0x9BC9, 0xC3A2, 0x9BCA, 0xC3A3, 0x9BCB, 0xC3A4, 0x9BCC, 0xC3A5, 0x9BCD, 0xC3A6, 0x9BCE, 0xC3A7, 0x9BCF, 0xC3A8, 0x9BD0, 0xC3A9,
+ 0x9BD1, 0xC3AA, 0x9BD2, 0xC3AB, 0x9BD3, 0xC3AC, 0x9BD4, 0xC3AD, 0x9BD5, 0xC3AE, 0x9BD6, 0xC3AF, 0x9BD7, 0xC3B0, 0x9BD8, 0xC3B1,
+ 0x9BD9, 0xC3B2, 0x9BDA, 0xC3B3, 0x9BDB, 0xC3B4, 0x9BDC, 0xC3B5, 0x9BDD, 0xC3B6, 0x9BDE, 0xC3B7, 0x9BDF, 0xC3B8, 0x9BE0, 0xC3B9,
+ 0x9BE1, 0xC3BA, 0x9BE2, 0xC3BB, 0x9BE3, 0xC3BC, 0x9BE4, 0xC3BD, 0x9BE5, 0xC3BE, 0x9BE6, 0xC3BF, 0x9BE7, 0xC3C1, 0x9BE8, 0xC3C2,
+ 0x9BE9, 0xC3C3, 0x9BEA, 0xC3C4, 0x9BEB, 0xC3C5, 0x9BEC, 0xC3C6, 0x9BED, 0xC3C7, 0x9BEE, 0xC3C8, 0x9BEF, 0xC3C9, 0x9BF0, 0xC3CA,
+ 0x9BF1, 0xC3CB, 0x9BF2, 0xC3CC, 0x9BF3, 0xC3CD, 0x9BF4, 0xC3CE, 0x9BF5, 0xC3CF, 0x9BF6, 0xC3D0, 0x9BF7, 0xC3D1, 0x9BF8, 0xC3D2,
+ 0x9BF9, 0xC3D3, 0x9BFA, 0xC3D4, 0x9BFB, 0xC3D5, 0x9BFC, 0xC3D6, 0x9BFD, 0xC3D7, 0x9BFE, 0xC3DA, 0x9C41, 0xC3DB, 0x9C42, 0xC3DD,
+ 0x9C43, 0xC3DE, 0x9C44, 0xC3E1, 0x9C45, 0xC3E3, 0x9C46, 0xC3E4, 0x9C47, 0xC3E5, 0x9C48, 0xC3E6, 0x9C49, 0xC3E7, 0x9C4A, 0xC3EA,
+ 0x9C4B, 0xC3EB, 0x9C4C, 0xC3EC, 0x9C4D, 0xC3EE, 0x9C4E, 0xC3EF, 0x9C4F, 0xC3F0, 0x9C50, 0xC3F1, 0x9C51, 0xC3F2, 0x9C52, 0xC3F3,
+ 0x9C53, 0xC3F6, 0x9C54, 0xC3F7, 0x9C55, 0xC3F9, 0x9C56, 0xC3FA, 0x9C57, 0xC3FB, 0x9C58, 0xC3FC, 0x9C59, 0xC3FD, 0x9C5A, 0xC3FE,
+ 0x9C61, 0xC3FF, 0x9C62, 0xC400, 0x9C63, 0xC401, 0x9C64, 0xC402, 0x9C65, 0xC403, 0x9C66, 0xC404, 0x9C67, 0xC405, 0x9C68, 0xC406,
+ 0x9C69, 0xC407, 0x9C6A, 0xC409, 0x9C6B, 0xC40A, 0x9C6C, 0xC40B, 0x9C6D, 0xC40C, 0x9C6E, 0xC40D, 0x9C6F, 0xC40E, 0x9C70, 0xC40F,
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+ 0x9C79, 0xC419, 0x9C7A, 0xC41A, 0x9C81, 0xC41B, 0x9C82, 0xC41C, 0x9C83, 0xC41D, 0x9C84, 0xC41E, 0x9C85, 0xC41F, 0x9C86, 0xC420,
+ 0x9C87, 0xC421, 0x9C88, 0xC422, 0x9C89, 0xC423, 0x9C8A, 0xC425, 0x9C8B, 0xC426, 0x9C8C, 0xC427, 0x9C8D, 0xC428, 0x9C8E, 0xC429,
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+ 0x9C97, 0xC435, 0x9C98, 0xC436, 0x9C99, 0xC437, 0x9C9A, 0xC438, 0x9C9B, 0xC439, 0x9C9C, 0xC43A, 0x9C9D, 0xC43B, 0x9C9E, 0xC43E,
+ 0x9C9F, 0xC43F, 0x9CA0, 0xC440, 0x9CA1, 0xC441, 0x9CA2, 0xC442, 0x9CA3, 0xC443, 0x9CA4, 0xC444, 0x9CA5, 0xC445, 0x9CA6, 0xC446,
+ 0x9CA7, 0xC447, 0x9CA8, 0xC449, 0x9CA9, 0xC44A, 0x9CAA, 0xC44B, 0x9CAB, 0xC44C, 0x9CAC, 0xC44D, 0x9CAD, 0xC44E, 0x9CAE, 0xC44F,
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+ 0x9CD7, 0xC47F, 0x9CD8, 0xC481, 0x9CD9, 0xC482, 0x9CDA, 0xC483, 0x9CDB, 0xC484, 0x9CDC, 0xC485, 0x9CDD, 0xC486, 0x9CDE, 0xC487,
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+ 0x9CF7, 0xC4A2, 0x9CF8, 0xC4A3, 0x9CF9, 0xC4A4, 0x9CFA, 0xC4A5, 0x9CFB, 0xC4A6, 0x9CFC, 0xC4A7, 0x9CFD, 0xC4A8, 0x9CFE, 0xC4A9,
+ 0x9D41, 0xC4AA, 0x9D42, 0xC4AB, 0x9D43, 0xC4AC, 0x9D44, 0xC4AD, 0x9D45, 0xC4AE, 0x9D46, 0xC4AF, 0x9D47, 0xC4B0, 0x9D48, 0xC4B1,
+ 0x9D49, 0xC4B2, 0x9D4A, 0xC4B3, 0x9D4B, 0xC4B4, 0x9D4C, 0xC4B5, 0x9D4D, 0xC4B6, 0x9D4E, 0xC4B7, 0x9D4F, 0xC4B9, 0x9D50, 0xC4BA,
+ 0x9D51, 0xC4BB, 0x9D52, 0xC4BD, 0x9D53, 0xC4BE, 0x9D54, 0xC4BF, 0x9D55, 0xC4C0, 0x9D56, 0xC4C1, 0x9D57, 0xC4C2, 0x9D58, 0xC4C3,
+ 0x9D59, 0xC4C4, 0x9D5A, 0xC4C5, 0x9D61, 0xC4C6, 0x9D62, 0xC4C7, 0x9D63, 0xC4C8, 0x9D64, 0xC4C9, 0x9D65, 0xC4CA, 0x9D66, 0xC4CB,
+ 0x9D67, 0xC4CC, 0x9D68, 0xC4CD, 0x9D69, 0xC4CE, 0x9D6A, 0xC4CF, 0x9D6B, 0xC4D0, 0x9D6C, 0xC4D1, 0x9D6D, 0xC4D2, 0x9D6E, 0xC4D3,
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+ 0x9D85, 0xC4E4, 0x9D86, 0xC4E5, 0x9D87, 0xC4E6, 0x9D88, 0xC4E7, 0x9D89, 0xC4E8, 0x9D8A, 0xC4EA, 0x9D8B, 0xC4EB, 0x9D8C, 0xC4EC,
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+ 0x9F73, 0xC6E7, 0x9F74, 0xC6EA, 0x9F75, 0xC6EB, 0x9F76, 0xC6ED, 0x9F77, 0xC6EE, 0x9F78, 0xC6EF, 0x9F79, 0xC6F1, 0x9F7A, 0xC6F2,
+ 0x9F81, 0xC6F3, 0x9F82, 0xC6F4, 0x9F83, 0xC6F5, 0x9F84, 0xC6F6, 0x9F85, 0xC6F7, 0x9F86, 0xC6FA, 0x9F87, 0xC6FB, 0x9F88, 0xC6FC,
+ 0x9F89, 0xC6FE, 0x9F8A, 0xC6FF, 0x9F8B, 0xC700, 0x9F8C, 0xC701, 0x9F8D, 0xC702, 0x9F8E, 0xC703, 0x9F8F, 0xC706, 0x9F90, 0xC707,
+ 0x9F91, 0xC709, 0x9F92, 0xC70A, 0x9F93, 0xC70B, 0x9F94, 0xC70D, 0x9F95, 0xC70E, 0x9F96, 0xC70F, 0x9F97, 0xC710, 0x9F98, 0xC711,
+ 0x9F99, 0xC712, 0x9F9A, 0xC713, 0x9F9B, 0xC716, 0x9F9C, 0xC718, 0x9F9D, 0xC71A, 0x9F9E, 0xC71B, 0x9F9F, 0xC71C, 0x9FA0, 0xC71D,
+ 0x9FA1, 0xC71E, 0x9FA2, 0xC71F, 0x9FA3, 0xC722, 0x9FA4, 0xC723, 0x9FA5, 0xC725, 0x9FA6, 0xC726, 0x9FA7, 0xC727, 0x9FA8, 0xC729,
+ 0x9FA9, 0xC72A, 0x9FAA, 0xC72B, 0x9FAB, 0xC72C, 0x9FAC, 0xC72D, 0x9FAD, 0xC72E, 0x9FAE, 0xC72F, 0x9FAF, 0xC732, 0x9FB0, 0xC734,
+ 0x9FB1, 0xC736, 0x9FB2, 0xC738, 0x9FB3, 0xC739, 0x9FB4, 0xC73A, 0x9FB5, 0xC73B, 0x9FB6, 0xC73E, 0x9FB7, 0xC73F, 0x9FB8, 0xC741,
+ 0x9FB9, 0xC742, 0x9FBA, 0xC743, 0x9FBB, 0xC745, 0x9FBC, 0xC746, 0x9FBD, 0xC747, 0x9FBE, 0xC748, 0x9FBF, 0xC749, 0x9FC0, 0xC74B,
+ 0x9FC1, 0xC74E, 0x9FC2, 0xC750, 0x9FC3, 0xC759, 0x9FC4, 0xC75A, 0x9FC5, 0xC75B, 0x9FC6, 0xC75D, 0x9FC7, 0xC75E, 0x9FC8, 0xC75F,
+ 0x9FC9, 0xC761, 0x9FCA, 0xC762, 0x9FCB, 0xC763, 0x9FCC, 0xC764, 0x9FCD, 0xC765, 0x9FCE, 0xC766, 0x9FCF, 0xC767, 0x9FD0, 0xC769,
+ 0x9FD1, 0xC76A, 0x9FD2, 0xC76C, 0x9FD3, 0xC76D, 0x9FD4, 0xC76E, 0x9FD5, 0xC76F, 0x9FD6, 0xC770, 0x9FD7, 0xC771, 0x9FD8, 0xC772,
+ 0x9FD9, 0xC773, 0x9FDA, 0xC776, 0x9FDB, 0xC777, 0x9FDC, 0xC779, 0x9FDD, 0xC77A, 0x9FDE, 0xC77B, 0x9FDF, 0xC77F, 0x9FE0, 0xC780,
+ 0x9FE1, 0xC781, 0x9FE2, 0xC782, 0x9FE3, 0xC786, 0x9FE4, 0xC78B, 0x9FE5, 0xC78C, 0x9FE6, 0xC78D, 0x9FE7, 0xC78F, 0x9FE8, 0xC792,
+ 0x9FE9, 0xC793, 0x9FEA, 0xC795, 0x9FEB, 0xC799, 0x9FEC, 0xC79B, 0x9FED, 0xC79C, 0x9FEE, 0xC79D, 0x9FEF, 0xC79E, 0x9FF0, 0xC79F,
+ 0x9FF1, 0xC7A2, 0x9FF2, 0xC7A7, 0x9FF3, 0xC7A8, 0x9FF4, 0xC7A9, 0x9FF5, 0xC7AA, 0x9FF6, 0xC7AB, 0x9FF7, 0xC7AE, 0x9FF8, 0xC7AF,
+ 0x9FF9, 0xC7B1, 0x9FFA, 0xC7B2, 0x9FFB, 0xC7B3, 0x9FFC, 0xC7B5, 0x9FFD, 0xC7B6, 0x9FFE, 0xC7B7, 0xA041, 0xC7B8, 0xA042, 0xC7B9,
+ 0xA043, 0xC7BA, 0xA044, 0xC7BB, 0xA045, 0xC7BE, 0xA046, 0xC7C2, 0xA047, 0xC7C3, 0xA048, 0xC7C4, 0xA049, 0xC7C5, 0xA04A, 0xC7C6,
+ 0xA04B, 0xC7C7, 0xA04C, 0xC7CA, 0xA04D, 0xC7CB, 0xA04E, 0xC7CD, 0xA04F, 0xC7CF, 0xA050, 0xC7D1, 0xA051, 0xC7D2, 0xA052, 0xC7D3,
+ 0xA053, 0xC7D4, 0xA054, 0xC7D5, 0xA055, 0xC7D6, 0xA056, 0xC7D7, 0xA057, 0xC7D9, 0xA058, 0xC7DA, 0xA059, 0xC7DB, 0xA05A, 0xC7DC,
+ 0xA061, 0xC7DE, 0xA062, 0xC7DF, 0xA063, 0xC7E0, 0xA064, 0xC7E1, 0xA065, 0xC7E2, 0xA066, 0xC7E3, 0xA067, 0xC7E5, 0xA068, 0xC7E6,
+ 0xA069, 0xC7E7, 0xA06A, 0xC7E9, 0xA06B, 0xC7EA, 0xA06C, 0xC7EB, 0xA06D, 0xC7ED, 0xA06E, 0xC7EE, 0xA06F, 0xC7EF, 0xA070, 0xC7F0,
+ 0xA071, 0xC7F1, 0xA072, 0xC7F2, 0xA073, 0xC7F3, 0xA074, 0xC7F4, 0xA075, 0xC7F5, 0xA076, 0xC7F6, 0xA077, 0xC7F7, 0xA078, 0xC7F8,
+ 0xA079, 0xC7F9, 0xA07A, 0xC7FA, 0xA081, 0xC7FB, 0xA082, 0xC7FC, 0xA083, 0xC7FD, 0xA084, 0xC7FE, 0xA085, 0xC7FF, 0xA086, 0xC802,
+ 0xA087, 0xC803, 0xA088, 0xC805, 0xA089, 0xC806, 0xA08A, 0xC807, 0xA08B, 0xC809, 0xA08C, 0xC80B, 0xA08D, 0xC80C, 0xA08E, 0xC80D,
+ 0xA08F, 0xC80E, 0xA090, 0xC80F, 0xA091, 0xC812, 0xA092, 0xC814, 0xA093, 0xC817, 0xA094, 0xC818, 0xA095, 0xC819, 0xA096, 0xC81A,
+ 0xA097, 0xC81B, 0xA098, 0xC81E, 0xA099, 0xC81F, 0xA09A, 0xC821, 0xA09B, 0xC822, 0xA09C, 0xC823, 0xA09D, 0xC825, 0xA09E, 0xC826,
+ 0xA09F, 0xC827, 0xA0A0, 0xC828, 0xA0A1, 0xC829, 0xA0A2, 0xC82A, 0xA0A3, 0xC82B, 0xA0A4, 0xC82E, 0xA0A5, 0xC830, 0xA0A6, 0xC832,
+ 0xA0A7, 0xC833, 0xA0A8, 0xC834, 0xA0A9, 0xC835, 0xA0AA, 0xC836, 0xA0AB, 0xC837, 0xA0AC, 0xC839, 0xA0AD, 0xC83A, 0xA0AE, 0xC83B,
+ 0xA0AF, 0xC83D, 0xA0B0, 0xC83E, 0xA0B1, 0xC83F, 0xA0B2, 0xC841, 0xA0B3, 0xC842, 0xA0B4, 0xC843, 0xA0B5, 0xC844, 0xA0B6, 0xC845,
+ 0xA0B7, 0xC846, 0xA0B8, 0xC847, 0xA0B9, 0xC84A, 0xA0BA, 0xC84B, 0xA0BB, 0xC84E, 0xA0BC, 0xC84F, 0xA0BD, 0xC850, 0xA0BE, 0xC851,
+ 0xA0BF, 0xC852, 0xA0C0, 0xC853, 0xA0C1, 0xC855, 0xA0C2, 0xC856, 0xA0C3, 0xC857, 0xA0C4, 0xC858, 0xA0C5, 0xC859, 0xA0C6, 0xC85A,
+ 0xA0C7, 0xC85B, 0xA0C8, 0xC85C, 0xA0C9, 0xC85D, 0xA0CA, 0xC85E, 0xA0CB, 0xC85F, 0xA0CC, 0xC860, 0xA0CD, 0xC861, 0xA0CE, 0xC862,
+ 0xA0CF, 0xC863, 0xA0D0, 0xC864, 0xA0D1, 0xC865, 0xA0D2, 0xC866, 0xA0D3, 0xC867, 0xA0D4, 0xC868, 0xA0D5, 0xC869, 0xA0D6, 0xC86A,
+ 0xA0D7, 0xC86B, 0xA0D8, 0xC86C, 0xA0D9, 0xC86D, 0xA0DA, 0xC86E, 0xA0DB, 0xC86F, 0xA0DC, 0xC872, 0xA0DD, 0xC873, 0xA0DE, 0xC875,
+ 0xA0DF, 0xC876, 0xA0E0, 0xC877, 0xA0E1, 0xC879, 0xA0E2, 0xC87B, 0xA0E3, 0xC87C, 0xA0E4, 0xC87D, 0xA0E5, 0xC87E, 0xA0E6, 0xC87F,
+ 0xA0E7, 0xC882, 0xA0E8, 0xC884, 0xA0E9, 0xC888, 0xA0EA, 0xC889, 0xA0EB, 0xC88A, 0xA0EC, 0xC88E, 0xA0ED, 0xC88F, 0xA0EE, 0xC890,
+ 0xA0EF, 0xC891, 0xA0F0, 0xC892, 0xA0F1, 0xC893, 0xA0F2, 0xC895, 0xA0F3, 0xC896, 0xA0F4, 0xC897, 0xA0F5, 0xC898, 0xA0F6, 0xC899,
+ 0xA0F7, 0xC89A, 0xA0F8, 0xC89B, 0xA0F9, 0xC89C, 0xA0FA, 0xC89E, 0xA0FB, 0xC8A0, 0xA0FC, 0xC8A2, 0xA0FD, 0xC8A3, 0xA0FE, 0xC8A4,
+ 0xA141, 0xC8A5, 0xA142, 0xC8A6, 0xA143, 0xC8A7, 0xA144, 0xC8A9, 0xA145, 0xC8AA, 0xA146, 0xC8AB, 0xA147, 0xC8AC, 0xA148, 0xC8AD,
+ 0xA149, 0xC8AE, 0xA14A, 0xC8AF, 0xA14B, 0xC8B0, 0xA14C, 0xC8B1, 0xA14D, 0xC8B2, 0xA14E, 0xC8B3, 0xA14F, 0xC8B4, 0xA150, 0xC8B5,
+ 0xA151, 0xC8B6, 0xA152, 0xC8B7, 0xA153, 0xC8B8, 0xA154, 0xC8B9, 0xA155, 0xC8BA, 0xA156, 0xC8BB, 0xA157, 0xC8BE, 0xA158, 0xC8BF,
+ 0xA159, 0xC8C0, 0xA15A, 0xC8C1, 0xA161, 0xC8C2, 0xA162, 0xC8C3, 0xA163, 0xC8C5, 0xA164, 0xC8C6, 0xA165, 0xC8C7, 0xA166, 0xC8C9,
+ 0xA167, 0xC8CA, 0xA168, 0xC8CB, 0xA169, 0xC8CD, 0xA16A, 0xC8CE, 0xA16B, 0xC8CF, 0xA16C, 0xC8D0, 0xA16D, 0xC8D1, 0xA16E, 0xC8D2,
+ 0xA16F, 0xC8D3, 0xA170, 0xC8D6, 0xA171, 0xC8D8, 0xA172, 0xC8DA, 0xA173, 0xC8DB, 0xA174, 0xC8DC, 0xA175, 0xC8DD, 0xA176, 0xC8DE,
+ 0xA177, 0xC8DF, 0xA178, 0xC8E2, 0xA179, 0xC8E3, 0xA17A, 0xC8E5, 0xA181, 0xC8E6, 0xA182, 0xC8E7, 0xA183, 0xC8E8, 0xA184, 0xC8E9,
+ 0xA185, 0xC8EA, 0xA186, 0xC8EB, 0xA187, 0xC8EC, 0xA188, 0xC8ED, 0xA189, 0xC8EE, 0xA18A, 0xC8EF, 0xA18B, 0xC8F0, 0xA18C, 0xC8F1,
+ 0xA18D, 0xC8F2, 0xA18E, 0xC8F3, 0xA18F, 0xC8F4, 0xA190, 0xC8F6, 0xA191, 0xC8F7, 0xA192, 0xC8F8, 0xA193, 0xC8F9, 0xA194, 0xC8FA,
+ 0xA195, 0xC8FB, 0xA196, 0xC8FE, 0xA197, 0xC8FF, 0xA198, 0xC901, 0xA199, 0xC902, 0xA19A, 0xC903, 0xA19B, 0xC907, 0xA19C, 0xC908,
+ 0xA19D, 0xC909, 0xA19E, 0xC90A, 0xA19F, 0xC90B, 0xA1A0, 0xC90E, 0xA1A1, 0x3000, 0xA1A2, 0x3001, 0xA1A3, 0x3002, 0xA1A4, 0x00B7,
+ 0xA1A5, 0x2025, 0xA1A6, 0x2026, 0xA1A7, 0x00A8, 0xA1A8, 0x3003, 0xA1A9, 0x00AD, 0xA1AA, 0x2015, 0xA1AB, 0x2225, 0xA1AC, 0xFF3C,
+ 0xA1AD, 0x223C, 0xA1AE, 0x2018, 0xA1AF, 0x2019, 0xA1B0, 0x201C, 0xA1B1, 0x201D, 0xA1B2, 0x3014, 0xA1B3, 0x3015, 0xA1B4, 0x3008,
+ 0xA1B5, 0x3009, 0xA1B6, 0x300A, 0xA1B7, 0x300B, 0xA1B8, 0x300C, 0xA1B9, 0x300D, 0xA1BA, 0x300E, 0xA1BB, 0x300F, 0xA1BC, 0x3010,
+ 0xA1BD, 0x3011, 0xA1BE, 0x00B1, 0xA1BF, 0x00D7, 0xA1C0, 0x00F7, 0xA1C1, 0x2260, 0xA1C2, 0x2264, 0xA1C3, 0x2265, 0xA1C4, 0x221E,
+ 0xA1C5, 0x2234, 0xA1C6, 0x00B0, 0xA1C7, 0x2032, 0xA1C8, 0x2033, 0xA1C9, 0x2103, 0xA1CA, 0x212B, 0xA1CB, 0xFFE0, 0xA1CC, 0xFFE1,
+ 0xA1CD, 0xFFE5, 0xA1CE, 0x2642, 0xA1CF, 0x2640, 0xA1D0, 0x2220, 0xA1D1, 0x22A5, 0xA1D2, 0x2312, 0xA1D3, 0x2202, 0xA1D4, 0x2207,
+ 0xA1D5, 0x2261, 0xA1D6, 0x2252, 0xA1D7, 0x00A7, 0xA1D8, 0x203B, 0xA1D9, 0x2606, 0xA1DA, 0x2605, 0xA1DB, 0x25CB, 0xA1DC, 0x25CF,
+ 0xA1DD, 0x25CE, 0xA1DE, 0x25C7, 0xA1DF, 0x25C6, 0xA1E0, 0x25A1, 0xA1E1, 0x25A0, 0xA1E2, 0x25B3, 0xA1E3, 0x25B2, 0xA1E4, 0x25BD,
+ 0xA1E5, 0x25BC, 0xA1E6, 0x2192, 0xA1E7, 0x2190, 0xA1E8, 0x2191, 0xA1E9, 0x2193, 0xA1EA, 0x2194, 0xA1EB, 0x3013, 0xA1EC, 0x226A,
+ 0xA1ED, 0x226B, 0xA1EE, 0x221A, 0xA1EF, 0x223D, 0xA1F0, 0x221D, 0xA1F1, 0x2235, 0xA1F2, 0x222B, 0xA1F3, 0x222C, 0xA1F4, 0x2208,
+ 0xA1F5, 0x220B, 0xA1F6, 0x2286, 0xA1F7, 0x2287, 0xA1F8, 0x2282, 0xA1F9, 0x2283, 0xA1FA, 0x222A, 0xA1FB, 0x2229, 0xA1FC, 0x2227,
+ 0xA1FD, 0x2228, 0xA1FE, 0xFFE2, 0xA241, 0xC910, 0xA242, 0xC912, 0xA243, 0xC913, 0xA244, 0xC914, 0xA245, 0xC915, 0xA246, 0xC916,
+ 0xA247, 0xC917, 0xA248, 0xC919, 0xA249, 0xC91A, 0xA24A, 0xC91B, 0xA24B, 0xC91C, 0xA24C, 0xC91D, 0xA24D, 0xC91E, 0xA24E, 0xC91F,
+ 0xA24F, 0xC920, 0xA250, 0xC921, 0xA251, 0xC922, 0xA252, 0xC923, 0xA253, 0xC924, 0xA254, 0xC925, 0xA255, 0xC926, 0xA256, 0xC927,
+ 0xA257, 0xC928, 0xA258, 0xC929, 0xA259, 0xC92A, 0xA25A, 0xC92B, 0xA261, 0xC92D, 0xA262, 0xC92E, 0xA263, 0xC92F, 0xA264, 0xC930,
+ 0xA265, 0xC931, 0xA266, 0xC932, 0xA267, 0xC933, 0xA268, 0xC935, 0xA269, 0xC936, 0xA26A, 0xC937, 0xA26B, 0xC938, 0xA26C, 0xC939,
+ 0xA26D, 0xC93A, 0xA26E, 0xC93B, 0xA26F, 0xC93C, 0xA270, 0xC93D, 0xA271, 0xC93E, 0xA272, 0xC93F, 0xA273, 0xC940, 0xA274, 0xC941,
+ 0xA275, 0xC942, 0xA276, 0xC943, 0xA277, 0xC944, 0xA278, 0xC945, 0xA279, 0xC946, 0xA27A, 0xC947, 0xA281, 0xC948, 0xA282, 0xC949,
+ 0xA283, 0xC94A, 0xA284, 0xC94B, 0xA285, 0xC94C, 0xA286, 0xC94D, 0xA287, 0xC94E, 0xA288, 0xC94F, 0xA289, 0xC952, 0xA28A, 0xC953,
+ 0xA28B, 0xC955, 0xA28C, 0xC956, 0xA28D, 0xC957, 0xA28E, 0xC959, 0xA28F, 0xC95A, 0xA290, 0xC95B, 0xA291, 0xC95C, 0xA292, 0xC95D,
+ 0xA293, 0xC95E, 0xA294, 0xC95F, 0xA295, 0xC962, 0xA296, 0xC964, 0xA297, 0xC965, 0xA298, 0xC966, 0xA299, 0xC967, 0xA29A, 0xC968,
+ 0xA29B, 0xC969, 0xA29C, 0xC96A, 0xA29D, 0xC96B, 0xA29E, 0xC96D, 0xA29F, 0xC96E, 0xA2A0, 0xC96F, 0xA2A1, 0x21D2, 0xA2A2, 0x21D4,
+ 0xA2A3, 0x2200, 0xA2A4, 0x2203, 0xA2A5, 0x00B4, 0xA2A6, 0xFF5E, 0xA2A7, 0x02C7, 0xA2A8, 0x02D8, 0xA2A9, 0x02DD, 0xA2AA, 0x02DA,
+ 0xA2AB, 0x02D9, 0xA2AC, 0x00B8, 0xA2AD, 0x02DB, 0xA2AE, 0x00A1, 0xA2AF, 0x00BF, 0xA2B0, 0x02D0, 0xA2B1, 0x222E, 0xA2B2, 0x2211,
+ 0xA2B3, 0x220F, 0xA2B4, 0x00A4, 0xA2B5, 0x2109, 0xA2B6, 0x2030, 0xA2B7, 0x25C1, 0xA2B8, 0x25C0, 0xA2B9, 0x25B7, 0xA2BA, 0x25B6,
+ 0xA2BB, 0x2664, 0xA2BC, 0x2660, 0xA2BD, 0x2661, 0xA2BE, 0x2665, 0xA2BF, 0x2667, 0xA2C0, 0x2663, 0xA2C1, 0x2299, 0xA2C2, 0x25C8,
+ 0xA2C3, 0x25A3, 0xA2C4, 0x25D0, 0xA2C5, 0x25D1, 0xA2C6, 0x2592, 0xA2C7, 0x25A4, 0xA2C8, 0x25A5, 0xA2C9, 0x25A8, 0xA2CA, 0x25A7,
+ 0xA2CB, 0x25A6, 0xA2CC, 0x25A9, 0xA2CD, 0x2668, 0xA2CE, 0x260F, 0xA2CF, 0x260E, 0xA2D0, 0x261C, 0xA2D1, 0x261E, 0xA2D2, 0x00B6,
+ 0xA2D3, 0x2020, 0xA2D4, 0x2021, 0xA2D5, 0x2195, 0xA2D6, 0x2197, 0xA2D7, 0x2199, 0xA2D8, 0x2196, 0xA2D9, 0x2198, 0xA2DA, 0x266D,
+ 0xA2DB, 0x2669, 0xA2DC, 0x266A, 0xA2DD, 0x266C, 0xA2DE, 0x327F, 0xA2DF, 0x321C, 0xA2E0, 0x2116, 0xA2E1, 0x33C7, 0xA2E2, 0x2122,
+ 0xA2E3, 0x33C2, 0xA2E4, 0x33D8, 0xA2E5, 0x2121, 0xA2E6, 0x20AC, 0xA2E7, 0x00AE, 0xA341, 0xC971, 0xA342, 0xC972, 0xA343, 0xC973,
+ 0xA344, 0xC975, 0xA345, 0xC976, 0xA346, 0xC977, 0xA347, 0xC978, 0xA348, 0xC979, 0xA349, 0xC97A, 0xA34A, 0xC97B, 0xA34B, 0xC97D,
+ 0xA34C, 0xC97E, 0xA34D, 0xC97F, 0xA34E, 0xC980, 0xA34F, 0xC981, 0xA350, 0xC982, 0xA351, 0xC983, 0xA352, 0xC984, 0xA353, 0xC985,
+ 0xA354, 0xC986, 0xA355, 0xC987, 0xA356, 0xC98A, 0xA357, 0xC98B, 0xA358, 0xC98D, 0xA359, 0xC98E, 0xA35A, 0xC98F, 0xA361, 0xC991,
+ 0xA362, 0xC992, 0xA363, 0xC993, 0xA364, 0xC994, 0xA365, 0xC995, 0xA366, 0xC996, 0xA367, 0xC997, 0xA368, 0xC99A, 0xA369, 0xC99C,
+ 0xA36A, 0xC99E, 0xA36B, 0xC99F, 0xA36C, 0xC9A0, 0xA36D, 0xC9A1, 0xA36E, 0xC9A2, 0xA36F, 0xC9A3, 0xA370, 0xC9A4, 0xA371, 0xC9A5,
+ 0xA372, 0xC9A6, 0xA373, 0xC9A7, 0xA374, 0xC9A8, 0xA375, 0xC9A9, 0xA376, 0xC9AA, 0xA377, 0xC9AB, 0xA378, 0xC9AC, 0xA379, 0xC9AD,
+ 0xA37A, 0xC9AE, 0xA381, 0xC9AF, 0xA382, 0xC9B0, 0xA383, 0xC9B1, 0xA384, 0xC9B2, 0xA385, 0xC9B3, 0xA386, 0xC9B4, 0xA387, 0xC9B5,
+ 0xA388, 0xC9B6, 0xA389, 0xC9B7, 0xA38A, 0xC9B8, 0xA38B, 0xC9B9, 0xA38C, 0xC9BA, 0xA38D, 0xC9BB, 0xA38E, 0xC9BC, 0xA38F, 0xC9BD,
+ 0xA390, 0xC9BE, 0xA391, 0xC9BF, 0xA392, 0xC9C2, 0xA393, 0xC9C3, 0xA394, 0xC9C5, 0xA395, 0xC9C6, 0xA396, 0xC9C9, 0xA397, 0xC9CB,
+ 0xA398, 0xC9CC, 0xA399, 0xC9CD, 0xA39A, 0xC9CE, 0xA39B, 0xC9CF, 0xA39C, 0xC9D2, 0xA39D, 0xC9D4, 0xA39E, 0xC9D7, 0xA39F, 0xC9D8,
+ 0xA3A0, 0xC9DB, 0xA3A1, 0xFF01, 0xA3A2, 0xFF02, 0xA3A3, 0xFF03, 0xA3A4, 0xFF04, 0xA3A5, 0xFF05, 0xA3A6, 0xFF06, 0xA3A7, 0xFF07,
+ 0xA3A8, 0xFF08, 0xA3A9, 0xFF09, 0xA3AA, 0xFF0A, 0xA3AB, 0xFF0B, 0xA3AC, 0xFF0C, 0xA3AD, 0xFF0D, 0xA3AE, 0xFF0E, 0xA3AF, 0xFF0F,
+ 0xA3B0, 0xFF10, 0xA3B1, 0xFF11, 0xA3B2, 0xFF12, 0xA3B3, 0xFF13, 0xA3B4, 0xFF14, 0xA3B5, 0xFF15, 0xA3B6, 0xFF16, 0xA3B7, 0xFF17,
+ 0xA3B8, 0xFF18, 0xA3B9, 0xFF19, 0xA3BA, 0xFF1A, 0xA3BB, 0xFF1B, 0xA3BC, 0xFF1C, 0xA3BD, 0xFF1D, 0xA3BE, 0xFF1E, 0xA3BF, 0xFF1F,
+ 0xA3C0, 0xFF20, 0xA3C1, 0xFF21, 0xA3C2, 0xFF22, 0xA3C3, 0xFF23, 0xA3C4, 0xFF24, 0xA3C5, 0xFF25, 0xA3C6, 0xFF26, 0xA3C7, 0xFF27,
+ 0xA3C8, 0xFF28, 0xA3C9, 0xFF29, 0xA3CA, 0xFF2A, 0xA3CB, 0xFF2B, 0xA3CC, 0xFF2C, 0xA3CD, 0xFF2D, 0xA3CE, 0xFF2E, 0xA3CF, 0xFF2F,
+ 0xA3D0, 0xFF30, 0xA3D1, 0xFF31, 0xA3D2, 0xFF32, 0xA3D3, 0xFF33, 0xA3D4, 0xFF34, 0xA3D5, 0xFF35, 0xA3D6, 0xFF36, 0xA3D7, 0xFF37,
+ 0xA3D8, 0xFF38, 0xA3D9, 0xFF39, 0xA3DA, 0xFF3A, 0xA3DB, 0xFF3B, 0xA3DC, 0xFFE6, 0xA3DD, 0xFF3D, 0xA3DE, 0xFF3E, 0xA3DF, 0xFF3F,
+ 0xA3E0, 0xFF40, 0xA3E1, 0xFF41, 0xA3E2, 0xFF42, 0xA3E3, 0xFF43, 0xA3E4, 0xFF44, 0xA3E5, 0xFF45, 0xA3E6, 0xFF46, 0xA3E7, 0xFF47,
+ 0xA3E8, 0xFF48, 0xA3E9, 0xFF49, 0xA3EA, 0xFF4A, 0xA3EB, 0xFF4B, 0xA3EC, 0xFF4C, 0xA3ED, 0xFF4D, 0xA3EE, 0xFF4E, 0xA3EF, 0xFF4F,
+ 0xA3F0, 0xFF50, 0xA3F1, 0xFF51, 0xA3F2, 0xFF52, 0xA3F3, 0xFF53, 0xA3F4, 0xFF54, 0xA3F5, 0xFF55, 0xA3F6, 0xFF56, 0xA3F7, 0xFF57,
+ 0xA3F8, 0xFF58, 0xA3F9, 0xFF59, 0xA3FA, 0xFF5A, 0xA3FB, 0xFF5B, 0xA3FC, 0xFF5C, 0xA3FD, 0xFF5D, 0xA3FE, 0xFFE3, 0xA441, 0xC9DE,
+ 0xA442, 0xC9DF, 0xA443, 0xC9E1, 0xA444, 0xC9E3, 0xA445, 0xC9E5, 0xA446, 0xC9E6, 0xA447, 0xC9E8, 0xA448, 0xC9E9, 0xA449, 0xC9EA,
+ 0xA44A, 0xC9EB, 0xA44B, 0xC9EE, 0xA44C, 0xC9F2, 0xA44D, 0xC9F3, 0xA44E, 0xC9F4, 0xA44F, 0xC9F5, 0xA450, 0xC9F6, 0xA451, 0xC9F7,
+ 0xA452, 0xC9FA, 0xA453, 0xC9FB, 0xA454, 0xC9FD, 0xA455, 0xC9FE, 0xA456, 0xC9FF, 0xA457, 0xCA01, 0xA458, 0xCA02, 0xA459, 0xCA03,
+ 0xA45A, 0xCA04, 0xA461, 0xCA05, 0xA462, 0xCA06, 0xA463, 0xCA07, 0xA464, 0xCA0A, 0xA465, 0xCA0E, 0xA466, 0xCA0F, 0xA467, 0xCA10,
+ 0xA468, 0xCA11, 0xA469, 0xCA12, 0xA46A, 0xCA13, 0xA46B, 0xCA15, 0xA46C, 0xCA16, 0xA46D, 0xCA17, 0xA46E, 0xCA19, 0xA46F, 0xCA1A,
+ 0xA470, 0xCA1B, 0xA471, 0xCA1C, 0xA472, 0xCA1D, 0xA473, 0xCA1E, 0xA474, 0xCA1F, 0xA475, 0xCA20, 0xA476, 0xCA21, 0xA477, 0xCA22,
+ 0xA478, 0xCA23, 0xA479, 0xCA24, 0xA47A, 0xCA25, 0xA481, 0xCA26, 0xA482, 0xCA27, 0xA483, 0xCA28, 0xA484, 0xCA2A, 0xA485, 0xCA2B,
+ 0xA486, 0xCA2C, 0xA487, 0xCA2D, 0xA488, 0xCA2E, 0xA489, 0xCA2F, 0xA48A, 0xCA30, 0xA48B, 0xCA31, 0xA48C, 0xCA32, 0xA48D, 0xCA33,
+ 0xA48E, 0xCA34, 0xA48F, 0xCA35, 0xA490, 0xCA36, 0xA491, 0xCA37, 0xA492, 0xCA38, 0xA493, 0xCA39, 0xA494, 0xCA3A, 0xA495, 0xCA3B,
+ 0xA496, 0xCA3C, 0xA497, 0xCA3D, 0xA498, 0xCA3E, 0xA499, 0xCA3F, 0xA49A, 0xCA40, 0xA49B, 0xCA41, 0xA49C, 0xCA42, 0xA49D, 0xCA43,
+ 0xA49E, 0xCA44, 0xA49F, 0xCA45, 0xA4A0, 0xCA46, 0xA4A1, 0x3131, 0xA4A2, 0x3132, 0xA4A3, 0x3133, 0xA4A4, 0x3134, 0xA4A5, 0x3135,
+ 0xA4A6, 0x3136, 0xA4A7, 0x3137, 0xA4A8, 0x3138, 0xA4A9, 0x3139, 0xA4AA, 0x313A, 0xA4AB, 0x313B, 0xA4AC, 0x313C, 0xA4AD, 0x313D,
+ 0xA4AE, 0x313E, 0xA4AF, 0x313F, 0xA4B0, 0x3140, 0xA4B1, 0x3141, 0xA4B2, 0x3142, 0xA4B3, 0x3143, 0xA4B4, 0x3144, 0xA4B5, 0x3145,
+ 0xA4B6, 0x3146, 0xA4B7, 0x3147, 0xA4B8, 0x3148, 0xA4B9, 0x3149, 0xA4BA, 0x314A, 0xA4BB, 0x314B, 0xA4BC, 0x314C, 0xA4BD, 0x314D,
+ 0xA4BE, 0x314E, 0xA4BF, 0x314F, 0xA4C0, 0x3150, 0xA4C1, 0x3151, 0xA4C2, 0x3152, 0xA4C3, 0x3153, 0xA4C4, 0x3154, 0xA4C5, 0x3155,
+ 0xA4C6, 0x3156, 0xA4C7, 0x3157, 0xA4C8, 0x3158, 0xA4C9, 0x3159, 0xA4CA, 0x315A, 0xA4CB, 0x315B, 0xA4CC, 0x315C, 0xA4CD, 0x315D,
+ 0xA4CE, 0x315E, 0xA4CF, 0x315F, 0xA4D0, 0x3160, 0xA4D1, 0x3161, 0xA4D2, 0x3162, 0xA4D3, 0x3163, 0xA4D4, 0x3164, 0xA4D5, 0x3165,
+ 0xA4D6, 0x3166, 0xA4D7, 0x3167, 0xA4D8, 0x3168, 0xA4D9, 0x3169, 0xA4DA, 0x316A, 0xA4DB, 0x316B, 0xA4DC, 0x316C, 0xA4DD, 0x316D,
+ 0xA4DE, 0x316E, 0xA4DF, 0x316F, 0xA4E0, 0x3170, 0xA4E1, 0x3171, 0xA4E2, 0x3172, 0xA4E3, 0x3173, 0xA4E4, 0x3174, 0xA4E5, 0x3175,
+ 0xA4E6, 0x3176, 0xA4E7, 0x3177, 0xA4E8, 0x3178, 0xA4E9, 0x3179, 0xA4EA, 0x317A, 0xA4EB, 0x317B, 0xA4EC, 0x317C, 0xA4ED, 0x317D,
+ 0xA4EE, 0x317E, 0xA4EF, 0x317F, 0xA4F0, 0x3180, 0xA4F1, 0x3181, 0xA4F2, 0x3182, 0xA4F3, 0x3183, 0xA4F4, 0x3184, 0xA4F5, 0x3185,
+ 0xA4F6, 0x3186, 0xA4F7, 0x3187, 0xA4F8, 0x3188, 0xA4F9, 0x3189, 0xA4FA, 0x318A, 0xA4FB, 0x318B, 0xA4FC, 0x318C, 0xA4FD, 0x318D,
+ 0xA4FE, 0x318E, 0xA541, 0xCA47, 0xA542, 0xCA48, 0xA543, 0xCA49, 0xA544, 0xCA4A, 0xA545, 0xCA4B, 0xA546, 0xCA4E, 0xA547, 0xCA4F,
+ 0xA548, 0xCA51, 0xA549, 0xCA52, 0xA54A, 0xCA53, 0xA54B, 0xCA55, 0xA54C, 0xCA56, 0xA54D, 0xCA57, 0xA54E, 0xCA58, 0xA54F, 0xCA59,
+ 0xA550, 0xCA5A, 0xA551, 0xCA5B, 0xA552, 0xCA5E, 0xA553, 0xCA62, 0xA554, 0xCA63, 0xA555, 0xCA64, 0xA556, 0xCA65, 0xA557, 0xCA66,
+ 0xA558, 0xCA67, 0xA559, 0xCA69, 0xA55A, 0xCA6A, 0xA561, 0xCA6B, 0xA562, 0xCA6C, 0xA563, 0xCA6D, 0xA564, 0xCA6E, 0xA565, 0xCA6F,
+ 0xA566, 0xCA70, 0xA567, 0xCA71, 0xA568, 0xCA72, 0xA569, 0xCA73, 0xA56A, 0xCA74, 0xA56B, 0xCA75, 0xA56C, 0xCA76, 0xA56D, 0xCA77,
+ 0xA56E, 0xCA78, 0xA56F, 0xCA79, 0xA570, 0xCA7A, 0xA571, 0xCA7B, 0xA572, 0xCA7C, 0xA573, 0xCA7E, 0xA574, 0xCA7F, 0xA575, 0xCA80,
+ 0xA576, 0xCA81, 0xA577, 0xCA82, 0xA578, 0xCA83, 0xA579, 0xCA85, 0xA57A, 0xCA86, 0xA581, 0xCA87, 0xA582, 0xCA88, 0xA583, 0xCA89,
+ 0xA584, 0xCA8A, 0xA585, 0xCA8B, 0xA586, 0xCA8C, 0xA587, 0xCA8D, 0xA588, 0xCA8E, 0xA589, 0xCA8F, 0xA58A, 0xCA90, 0xA58B, 0xCA91,
+ 0xA58C, 0xCA92, 0xA58D, 0xCA93, 0xA58E, 0xCA94, 0xA58F, 0xCA95, 0xA590, 0xCA96, 0xA591, 0xCA97, 0xA592, 0xCA99, 0xA593, 0xCA9A,
+ 0xA594, 0xCA9B, 0xA595, 0xCA9C, 0xA596, 0xCA9D, 0xA597, 0xCA9E, 0xA598, 0xCA9F, 0xA599, 0xCAA0, 0xA59A, 0xCAA1, 0xA59B, 0xCAA2,
+ 0xA59C, 0xCAA3, 0xA59D, 0xCAA4, 0xA59E, 0xCAA5, 0xA59F, 0xCAA6, 0xA5A0, 0xCAA7, 0xA5A1, 0x2170, 0xA5A2, 0x2171, 0xA5A3, 0x2172,
+ 0xA5A4, 0x2173, 0xA5A5, 0x2174, 0xA5A6, 0x2175, 0xA5A7, 0x2176, 0xA5A8, 0x2177, 0xA5A9, 0x2178, 0xA5AA, 0x2179, 0xA5B0, 0x2160,
+ 0xA5B1, 0x2161, 0xA5B2, 0x2162, 0xA5B3, 0x2163, 0xA5B4, 0x2164, 0xA5B5, 0x2165, 0xA5B6, 0x2166, 0xA5B7, 0x2167, 0xA5B8, 0x2168,
+ 0xA5B9, 0x2169, 0xA5C1, 0x0391, 0xA5C2, 0x0392, 0xA5C3, 0x0393, 0xA5C4, 0x0394, 0xA5C5, 0x0395, 0xA5C6, 0x0396, 0xA5C7, 0x0397,
+ 0xA5C8, 0x0398, 0xA5C9, 0x0399, 0xA5CA, 0x039A, 0xA5CB, 0x039B, 0xA5CC, 0x039C, 0xA5CD, 0x039D, 0xA5CE, 0x039E, 0xA5CF, 0x039F,
+ 0xA5D0, 0x03A0, 0xA5D1, 0x03A1, 0xA5D2, 0x03A3, 0xA5D3, 0x03A4, 0xA5D4, 0x03A5, 0xA5D5, 0x03A6, 0xA5D6, 0x03A7, 0xA5D7, 0x03A8,
+ 0xA5D8, 0x03A9, 0xA5E1, 0x03B1, 0xA5E2, 0x03B2, 0xA5E3, 0x03B3, 0xA5E4, 0x03B4, 0xA5E5, 0x03B5, 0xA5E6, 0x03B6, 0xA5E7, 0x03B7,
+ 0xA5E8, 0x03B8, 0xA5E9, 0x03B9, 0xA5EA, 0x03BA, 0xA5EB, 0x03BB, 0xA5EC, 0x03BC, 0xA5ED, 0x03BD, 0xA5EE, 0x03BE, 0xA5EF, 0x03BF,
+ 0xA5F0, 0x03C0, 0xA5F1, 0x03C1, 0xA5F2, 0x03C3, 0xA5F3, 0x03C4, 0xA5F4, 0x03C5, 0xA5F5, 0x03C6, 0xA5F6, 0x03C7, 0xA5F7, 0x03C8,
+ 0xA5F8, 0x03C9, 0xA641, 0xCAA8, 0xA642, 0xCAA9, 0xA643, 0xCAAA, 0xA644, 0xCAAB, 0xA645, 0xCAAC, 0xA646, 0xCAAD, 0xA647, 0xCAAE,
+ 0xA648, 0xCAAF, 0xA649, 0xCAB0, 0xA64A, 0xCAB1, 0xA64B, 0xCAB2, 0xA64C, 0xCAB3, 0xA64D, 0xCAB4, 0xA64E, 0xCAB5, 0xA64F, 0xCAB6,
+ 0xA650, 0xCAB7, 0xA651, 0xCAB8, 0xA652, 0xCAB9, 0xA653, 0xCABA, 0xA654, 0xCABB, 0xA655, 0xCABE, 0xA656, 0xCABF, 0xA657, 0xCAC1,
+ 0xA658, 0xCAC2, 0xA659, 0xCAC3, 0xA65A, 0xCAC5, 0xA661, 0xCAC6, 0xA662, 0xCAC7, 0xA663, 0xCAC8, 0xA664, 0xCAC9, 0xA665, 0xCACA,
+ 0xA666, 0xCACB, 0xA667, 0xCACE, 0xA668, 0xCAD0, 0xA669, 0xCAD2, 0xA66A, 0xCAD4, 0xA66B, 0xCAD5, 0xA66C, 0xCAD6, 0xA66D, 0xCAD7,
+ 0xA66E, 0xCADA, 0xA66F, 0xCADB, 0xA670, 0xCADC, 0xA671, 0xCADD, 0xA672, 0xCADE, 0xA673, 0xCADF, 0xA674, 0xCAE1, 0xA675, 0xCAE2,
+ 0xA676, 0xCAE3, 0xA677, 0xCAE4, 0xA678, 0xCAE5, 0xA679, 0xCAE6, 0xA67A, 0xCAE7, 0xA681, 0xCAE8, 0xA682, 0xCAE9, 0xA683, 0xCAEA,
+ 0xA684, 0xCAEB, 0xA685, 0xCAED, 0xA686, 0xCAEE, 0xA687, 0xCAEF, 0xA688, 0xCAF0, 0xA689, 0xCAF1, 0xA68A, 0xCAF2, 0xA68B, 0xCAF3,
+ 0xA68C, 0xCAF5, 0xA68D, 0xCAF6, 0xA68E, 0xCAF7, 0xA68F, 0xCAF8, 0xA690, 0xCAF9, 0xA691, 0xCAFA, 0xA692, 0xCAFB, 0xA693, 0xCAFC,
+ 0xA694, 0xCAFD, 0xA695, 0xCAFE, 0xA696, 0xCAFF, 0xA697, 0xCB00, 0xA698, 0xCB01, 0xA699, 0xCB02, 0xA69A, 0xCB03, 0xA69B, 0xCB04,
+ 0xA69C, 0xCB05, 0xA69D, 0xCB06, 0xA69E, 0xCB07, 0xA69F, 0xCB09, 0xA6A0, 0xCB0A, 0xA6A1, 0x2500, 0xA6A2, 0x2502, 0xA6A3, 0x250C,
+ 0xA6A4, 0x2510, 0xA6A5, 0x2518, 0xA6A6, 0x2514, 0xA6A7, 0x251C, 0xA6A8, 0x252C, 0xA6A9, 0x2524, 0xA6AA, 0x2534, 0xA6AB, 0x253C,
+ 0xA6AC, 0x2501, 0xA6AD, 0x2503, 0xA6AE, 0x250F, 0xA6AF, 0x2513, 0xA6B0, 0x251B, 0xA6B1, 0x2517, 0xA6B2, 0x2523, 0xA6B3, 0x2533,
+ 0xA6B4, 0x252B, 0xA6B5, 0x253B, 0xA6B6, 0x254B, 0xA6B7, 0x2520, 0xA6B8, 0x252F, 0xA6B9, 0x2528, 0xA6BA, 0x2537, 0xA6BB, 0x253F,
+ 0xA6BC, 0x251D, 0xA6BD, 0x2530, 0xA6BE, 0x2525, 0xA6BF, 0x2538, 0xA6C0, 0x2542, 0xA6C1, 0x2512, 0xA6C2, 0x2511, 0xA6C3, 0x251A,
+ 0xA6C4, 0x2519, 0xA6C5, 0x2516, 0xA6C6, 0x2515, 0xA6C7, 0x250E, 0xA6C8, 0x250D, 0xA6C9, 0x251E, 0xA6CA, 0x251F, 0xA6CB, 0x2521,
+ 0xA6CC, 0x2522, 0xA6CD, 0x2526, 0xA6CE, 0x2527, 0xA6CF, 0x2529, 0xA6D0, 0x252A, 0xA6D1, 0x252D, 0xA6D2, 0x252E, 0xA6D3, 0x2531,
+ 0xA6D4, 0x2532, 0xA6D5, 0x2535, 0xA6D6, 0x2536, 0xA6D7, 0x2539, 0xA6D8, 0x253A, 0xA6D9, 0x253D, 0xA6DA, 0x253E, 0xA6DB, 0x2540,
+ 0xA6DC, 0x2541, 0xA6DD, 0x2543, 0xA6DE, 0x2544, 0xA6DF, 0x2545, 0xA6E0, 0x2546, 0xA6E1, 0x2547, 0xA6E2, 0x2548, 0xA6E3, 0x2549,
+ 0xA6E4, 0x254A, 0xA741, 0xCB0B, 0xA742, 0xCB0C, 0xA743, 0xCB0D, 0xA744, 0xCB0E, 0xA745, 0xCB0F, 0xA746, 0xCB11, 0xA747, 0xCB12,
+ 0xA748, 0xCB13, 0xA749, 0xCB15, 0xA74A, 0xCB16, 0xA74B, 0xCB17, 0xA74C, 0xCB19, 0xA74D, 0xCB1A, 0xA74E, 0xCB1B, 0xA74F, 0xCB1C,
+ 0xA750, 0xCB1D, 0xA751, 0xCB1E, 0xA752, 0xCB1F, 0xA753, 0xCB22, 0xA754, 0xCB23, 0xA755, 0xCB24, 0xA756, 0xCB25, 0xA757, 0xCB26,
+ 0xA758, 0xCB27, 0xA759, 0xCB28, 0xA75A, 0xCB29, 0xA761, 0xCB2A, 0xA762, 0xCB2B, 0xA763, 0xCB2C, 0xA764, 0xCB2D, 0xA765, 0xCB2E,
+ 0xA766, 0xCB2F, 0xA767, 0xCB30, 0xA768, 0xCB31, 0xA769, 0xCB32, 0xA76A, 0xCB33, 0xA76B, 0xCB34, 0xA76C, 0xCB35, 0xA76D, 0xCB36,
+ 0xA76E, 0xCB37, 0xA76F, 0xCB38, 0xA770, 0xCB39, 0xA771, 0xCB3A, 0xA772, 0xCB3B, 0xA773, 0xCB3C, 0xA774, 0xCB3D, 0xA775, 0xCB3E,
+ 0xA776, 0xCB3F, 0xA777, 0xCB40, 0xA778, 0xCB42, 0xA779, 0xCB43, 0xA77A, 0xCB44, 0xA781, 0xCB45, 0xA782, 0xCB46, 0xA783, 0xCB47,
+ 0xA784, 0xCB4A, 0xA785, 0xCB4B, 0xA786, 0xCB4D, 0xA787, 0xCB4E, 0xA788, 0xCB4F, 0xA789, 0xCB51, 0xA78A, 0xCB52, 0xA78B, 0xCB53,
+ 0xA78C, 0xCB54, 0xA78D, 0xCB55, 0xA78E, 0xCB56, 0xA78F, 0xCB57, 0xA790, 0xCB5A, 0xA791, 0xCB5B, 0xA792, 0xCB5C, 0xA793, 0xCB5E,
+ 0xA794, 0xCB5F, 0xA795, 0xCB60, 0xA796, 0xCB61, 0xA797, 0xCB62, 0xA798, 0xCB63, 0xA799, 0xCB65, 0xA79A, 0xCB66, 0xA79B, 0xCB67,
+ 0xA79C, 0xCB68, 0xA79D, 0xCB69, 0xA79E, 0xCB6A, 0xA79F, 0xCB6B, 0xA7A0, 0xCB6C, 0xA7A1, 0x3395, 0xA7A2, 0x3396, 0xA7A3, 0x3397,
+ 0xA7A4, 0x2113, 0xA7A5, 0x3398, 0xA7A6, 0x33C4, 0xA7A7, 0x33A3, 0xA7A8, 0x33A4, 0xA7A9, 0x33A5, 0xA7AA, 0x33A6, 0xA7AB, 0x3399,
+ 0xA7AC, 0x339A, 0xA7AD, 0x339B, 0xA7AE, 0x339C, 0xA7AF, 0x339D, 0xA7B0, 0x339E, 0xA7B1, 0x339F, 0xA7B2, 0x33A0, 0xA7B3, 0x33A1,
+ 0xA7B4, 0x33A2, 0xA7B5, 0x33CA, 0xA7B6, 0x338D, 0xA7B7, 0x338E, 0xA7B8, 0x338F, 0xA7B9, 0x33CF, 0xA7BA, 0x3388, 0xA7BB, 0x3389,
+ 0xA7BC, 0x33C8, 0xA7BD, 0x33A7, 0xA7BE, 0x33A8, 0xA7BF, 0x33B0, 0xA7C0, 0x33B1, 0xA7C1, 0x33B2, 0xA7C2, 0x33B3, 0xA7C3, 0x33B4,
+ 0xA7C4, 0x33B5, 0xA7C5, 0x33B6, 0xA7C6, 0x33B7, 0xA7C7, 0x33B8, 0xA7C8, 0x33B9, 0xA7C9, 0x3380, 0xA7CA, 0x3381, 0xA7CB, 0x3382,
+ 0xA7CC, 0x3383, 0xA7CD, 0x3384, 0xA7CE, 0x33BA, 0xA7CF, 0x33BB, 0xA7D0, 0x33BC, 0xA7D1, 0x33BD, 0xA7D2, 0x33BE, 0xA7D3, 0x33BF,
+ 0xA7D4, 0x3390, 0xA7D5, 0x3391, 0xA7D6, 0x3392, 0xA7D7, 0x3393, 0xA7D8, 0x3394, 0xA7D9, 0x2126, 0xA7DA, 0x33C0, 0xA7DB, 0x33C1,
+ 0xA7DC, 0x338A, 0xA7DD, 0x338B, 0xA7DE, 0x338C, 0xA7DF, 0x33D6, 0xA7E0, 0x33C5, 0xA7E1, 0x33AD, 0xA7E2, 0x33AE, 0xA7E3, 0x33AF,
+ 0xA7E4, 0x33DB, 0xA7E5, 0x33A9, 0xA7E6, 0x33AA, 0xA7E7, 0x33AB, 0xA7E8, 0x33AC, 0xA7E9, 0x33DD, 0xA7EA, 0x33D0, 0xA7EB, 0x33D3,
+ 0xA7EC, 0x33C3, 0xA7ED, 0x33C9, 0xA7EE, 0x33DC, 0xA7EF, 0x33C6, 0xA841, 0xCB6D, 0xA842, 0xCB6E, 0xA843, 0xCB6F, 0xA844, 0xCB70,
+ 0xA845, 0xCB71, 0xA846, 0xCB72, 0xA847, 0xCB73, 0xA848, 0xCB74, 0xA849, 0xCB75, 0xA84A, 0xCB76, 0xA84B, 0xCB77, 0xA84C, 0xCB7A,
+ 0xA84D, 0xCB7B, 0xA84E, 0xCB7C, 0xA84F, 0xCB7D, 0xA850, 0xCB7E, 0xA851, 0xCB7F, 0xA852, 0xCB80, 0xA853, 0xCB81, 0xA854, 0xCB82,
+ 0xA855, 0xCB83, 0xA856, 0xCB84, 0xA857, 0xCB85, 0xA858, 0xCB86, 0xA859, 0xCB87, 0xA85A, 0xCB88, 0xA861, 0xCB89, 0xA862, 0xCB8A,
+ 0xA863, 0xCB8B, 0xA864, 0xCB8C, 0xA865, 0xCB8D, 0xA866, 0xCB8E, 0xA867, 0xCB8F, 0xA868, 0xCB90, 0xA869, 0xCB91, 0xA86A, 0xCB92,
+ 0xA86B, 0xCB93, 0xA86C, 0xCB94, 0xA86D, 0xCB95, 0xA86E, 0xCB96, 0xA86F, 0xCB97, 0xA870, 0xCB98, 0xA871, 0xCB99, 0xA872, 0xCB9A,
+ 0xA873, 0xCB9B, 0xA874, 0xCB9D, 0xA875, 0xCB9E, 0xA876, 0xCB9F, 0xA877, 0xCBA0, 0xA878, 0xCBA1, 0xA879, 0xCBA2, 0xA87A, 0xCBA3,
+ 0xA881, 0xCBA4, 0xA882, 0xCBA5, 0xA883, 0xCBA6, 0xA884, 0xCBA7, 0xA885, 0xCBA8, 0xA886, 0xCBA9, 0xA887, 0xCBAA, 0xA888, 0xCBAB,
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+ 0xACAF, 0x041D, 0xACB0, 0x041E, 0xACB1, 0x041F, 0xACB2, 0x0420, 0xACB3, 0x0421, 0xACB4, 0x0422, 0xACB5, 0x0423, 0xACB6, 0x0424,
+ 0xACB7, 0x0425, 0xACB8, 0x0426, 0xACB9, 0x0427, 0xACBA, 0x0428, 0xACBB, 0x0429, 0xACBC, 0x042A, 0xACBD, 0x042B, 0xACBE, 0x042C,
+ 0xACBF, 0x042D, 0xACC0, 0x042E, 0xACC1, 0x042F, 0xACD1, 0x0430, 0xACD2, 0x0431, 0xACD3, 0x0432, 0xACD4, 0x0433, 0xACD5, 0x0434,
+ 0xACD6, 0x0435, 0xACD7, 0x0451, 0xACD8, 0x0436, 0xACD9, 0x0437, 0xACDA, 0x0438, 0xACDB, 0x0439, 0xACDC, 0x043A, 0xACDD, 0x043B,
+ 0xACDE, 0x043C, 0xACDF, 0x043D, 0xACE0, 0x043E, 0xACE1, 0x043F, 0xACE2, 0x0440, 0xACE3, 0x0441, 0xACE4, 0x0442, 0xACE5, 0x0443,
+ 0xACE6, 0x0444, 0xACE7, 0x0445, 0xACE8, 0x0446, 0xACE9, 0x0447, 0xACEA, 0x0448, 0xACEB, 0x0449, 0xACEC, 0x044A, 0xACED, 0x044B,
+ 0xACEE, 0x044C, 0xACEF, 0x044D, 0xACF0, 0x044E, 0xACF1, 0x044F, 0xAD41, 0xCD61, 0xAD42, 0xCD62, 0xAD43, 0xCD63, 0xAD44, 0xCD65,
+ 0xAD45, 0xCD66, 0xAD46, 0xCD67, 0xAD47, 0xCD68, 0xAD48, 0xCD69, 0xAD49, 0xCD6A, 0xAD4A, 0xCD6B, 0xAD4B, 0xCD6E, 0xAD4C, 0xCD70,
+ 0xAD4D, 0xCD72, 0xAD4E, 0xCD73, 0xAD4F, 0xCD74, 0xAD50, 0xCD75, 0xAD51, 0xCD76, 0xAD52, 0xCD77, 0xAD53, 0xCD79, 0xAD54, 0xCD7A,
+ 0xAD55, 0xCD7B, 0xAD56, 0xCD7C, 0xAD57, 0xCD7D, 0xAD58, 0xCD7E, 0xAD59, 0xCD7F, 0xAD5A, 0xCD80, 0xAD61, 0xCD81, 0xAD62, 0xCD82,
+ 0xAD63, 0xCD83, 0xAD64, 0xCD84, 0xAD65, 0xCD85, 0xAD66, 0xCD86, 0xAD67, 0xCD87, 0xAD68, 0xCD89, 0xAD69, 0xCD8A, 0xAD6A, 0xCD8B,
+ 0xAD6B, 0xCD8C, 0xAD6C, 0xCD8D, 0xAD6D, 0xCD8E, 0xAD6E, 0xCD8F, 0xAD6F, 0xCD90, 0xAD70, 0xCD91, 0xAD71, 0xCD92, 0xAD72, 0xCD93,
+ 0xAD73, 0xCD96, 0xAD74, 0xCD97, 0xAD75, 0xCD99, 0xAD76, 0xCD9A, 0xAD77, 0xCD9B, 0xAD78, 0xCD9D, 0xAD79, 0xCD9E, 0xAD7A, 0xCD9F,
+ 0xAD81, 0xCDA0, 0xAD82, 0xCDA1, 0xAD83, 0xCDA2, 0xAD84, 0xCDA3, 0xAD85, 0xCDA6, 0xAD86, 0xCDA8, 0xAD87, 0xCDAA, 0xAD88, 0xCDAB,
+ 0xAD89, 0xCDAC, 0xAD8A, 0xCDAD, 0xAD8B, 0xCDAE, 0xAD8C, 0xCDAF, 0xAD8D, 0xCDB1, 0xAD8E, 0xCDB2, 0xAD8F, 0xCDB3, 0xAD90, 0xCDB4,
+ 0xAD91, 0xCDB5, 0xAD92, 0xCDB6, 0xAD93, 0xCDB7, 0xAD94, 0xCDB8, 0xAD95, 0xCDB9, 0xAD96, 0xCDBA, 0xAD97, 0xCDBB, 0xAD98, 0xCDBC,
+ 0xAD99, 0xCDBD, 0xAD9A, 0xCDBE, 0xAD9B, 0xCDBF, 0xAD9C, 0xCDC0, 0xAD9D, 0xCDC1, 0xAD9E, 0xCDC2, 0xAD9F, 0xCDC3, 0xADA0, 0xCDC5,
+ 0xAE41, 0xCDC6, 0xAE42, 0xCDC7, 0xAE43, 0xCDC8, 0xAE44, 0xCDC9, 0xAE45, 0xCDCA, 0xAE46, 0xCDCB, 0xAE47, 0xCDCD, 0xAE48, 0xCDCE,
+ 0xAE49, 0xCDCF, 0xAE4A, 0xCDD1, 0xAE4B, 0xCDD2, 0xAE4C, 0xCDD3, 0xAE4D, 0xCDD4, 0xAE4E, 0xCDD5, 0xAE4F, 0xCDD6, 0xAE50, 0xCDD7,
+ 0xAE51, 0xCDD8, 0xAE52, 0xCDD9, 0xAE53, 0xCDDA, 0xAE54, 0xCDDB, 0xAE55, 0xCDDC, 0xAE56, 0xCDDD, 0xAE57, 0xCDDE, 0xAE58, 0xCDDF,
+ 0xAE59, 0xCDE0, 0xAE5A, 0xCDE1, 0xAE61, 0xCDE2, 0xAE62, 0xCDE3, 0xAE63, 0xCDE4, 0xAE64, 0xCDE5, 0xAE65, 0xCDE6, 0xAE66, 0xCDE7,
+ 0xAE67, 0xCDE9, 0xAE68, 0xCDEA, 0xAE69, 0xCDEB, 0xAE6A, 0xCDED, 0xAE6B, 0xCDEE, 0xAE6C, 0xCDEF, 0xAE6D, 0xCDF1, 0xAE6E, 0xCDF2,
+ 0xAE6F, 0xCDF3, 0xAE70, 0xCDF4, 0xAE71, 0xCDF5, 0xAE72, 0xCDF6, 0xAE73, 0xCDF7, 0xAE74, 0xCDFA, 0xAE75, 0xCDFC, 0xAE76, 0xCDFE,
+ 0xAE77, 0xCDFF, 0xAE78, 0xCE00, 0xAE79, 0xCE01, 0xAE7A, 0xCE02, 0xAE81, 0xCE03, 0xAE82, 0xCE05, 0xAE83, 0xCE06, 0xAE84, 0xCE07,
+ 0xAE85, 0xCE09, 0xAE86, 0xCE0A, 0xAE87, 0xCE0B, 0xAE88, 0xCE0D, 0xAE89, 0xCE0E, 0xAE8A, 0xCE0F, 0xAE8B, 0xCE10, 0xAE8C, 0xCE11,
+ 0xAE8D, 0xCE12, 0xAE8E, 0xCE13, 0xAE8F, 0xCE15, 0xAE90, 0xCE16, 0xAE91, 0xCE17, 0xAE92, 0xCE18, 0xAE93, 0xCE1A, 0xAE94, 0xCE1B,
+ 0xAE95, 0xCE1C, 0xAE96, 0xCE1D, 0xAE97, 0xCE1E, 0xAE98, 0xCE1F, 0xAE99, 0xCE22, 0xAE9A, 0xCE23, 0xAE9B, 0xCE25, 0xAE9C, 0xCE26,
+ 0xAE9D, 0xCE27, 0xAE9E, 0xCE29, 0xAE9F, 0xCE2A, 0xAEA0, 0xCE2B, 0xAF41, 0xCE2C, 0xAF42, 0xCE2D, 0xAF43, 0xCE2E, 0xAF44, 0xCE2F,
+ 0xAF45, 0xCE32, 0xAF46, 0xCE34, 0xAF47, 0xCE36, 0xAF48, 0xCE37, 0xAF49, 0xCE38, 0xAF4A, 0xCE39, 0xAF4B, 0xCE3A, 0xAF4C, 0xCE3B,
+ 0xAF4D, 0xCE3C, 0xAF4E, 0xCE3D, 0xAF4F, 0xCE3E, 0xAF50, 0xCE3F, 0xAF51, 0xCE40, 0xAF52, 0xCE41, 0xAF53, 0xCE42, 0xAF54, 0xCE43,
+ 0xAF55, 0xCE44, 0xAF56, 0xCE45, 0xAF57, 0xCE46, 0xAF58, 0xCE47, 0xAF59, 0xCE48, 0xAF5A, 0xCE49, 0xAF61, 0xCE4A, 0xAF62, 0xCE4B,
+ 0xAF63, 0xCE4C, 0xAF64, 0xCE4D, 0xAF65, 0xCE4E, 0xAF66, 0xCE4F, 0xAF67, 0xCE50, 0xAF68, 0xCE51, 0xAF69, 0xCE52, 0xAF6A, 0xCE53,
+ 0xAF6B, 0xCE54, 0xAF6C, 0xCE55, 0xAF6D, 0xCE56, 0xAF6E, 0xCE57, 0xAF6F, 0xCE5A, 0xAF70, 0xCE5B, 0xAF71, 0xCE5D, 0xAF72, 0xCE5E,
+ 0xAF73, 0xCE62, 0xAF74, 0xCE63, 0xAF75, 0xCE64, 0xAF76, 0xCE65, 0xAF77, 0xCE66, 0xAF78, 0xCE67, 0xAF79, 0xCE6A, 0xAF7A, 0xCE6C,
+ 0xAF81, 0xCE6E, 0xAF82, 0xCE6F, 0xAF83, 0xCE70, 0xAF84, 0xCE71, 0xAF85, 0xCE72, 0xAF86, 0xCE73, 0xAF87, 0xCE76, 0xAF88, 0xCE77,
+ 0xAF89, 0xCE79, 0xAF8A, 0xCE7A, 0xAF8B, 0xCE7B, 0xAF8C, 0xCE7D, 0xAF8D, 0xCE7E, 0xAF8E, 0xCE7F, 0xAF8F, 0xCE80, 0xAF90, 0xCE81,
+ 0xAF91, 0xCE82, 0xAF92, 0xCE83, 0xAF93, 0xCE86, 0xAF94, 0xCE88, 0xAF95, 0xCE8A, 0xAF96, 0xCE8B, 0xAF97, 0xCE8C, 0xAF98, 0xCE8D,
+ 0xAF99, 0xCE8E, 0xAF9A, 0xCE8F, 0xAF9B, 0xCE92, 0xAF9C, 0xCE93, 0xAF9D, 0xCE95, 0xAF9E, 0xCE96, 0xAF9F, 0xCE97, 0xAFA0, 0xCE99,
+ 0xB041, 0xCE9A, 0xB042, 0xCE9B, 0xB043, 0xCE9C, 0xB044, 0xCE9D, 0xB045, 0xCE9E, 0xB046, 0xCE9F, 0xB047, 0xCEA2, 0xB048, 0xCEA6,
+ 0xB049, 0xCEA7, 0xB04A, 0xCEA8, 0xB04B, 0xCEA9, 0xB04C, 0xCEAA, 0xB04D, 0xCEAB, 0xB04E, 0xCEAE, 0xB04F, 0xCEAF, 0xB050, 0xCEB0,
+ 0xB051, 0xCEB1, 0xB052, 0xCEB2, 0xB053, 0xCEB3, 0xB054, 0xCEB4, 0xB055, 0xCEB5, 0xB056, 0xCEB6, 0xB057, 0xCEB7, 0xB058, 0xCEB8,
+ 0xB059, 0xCEB9, 0xB05A, 0xCEBA, 0xB061, 0xCEBB, 0xB062, 0xCEBC, 0xB063, 0xCEBD, 0xB064, 0xCEBE, 0xB065, 0xCEBF, 0xB066, 0xCEC0,
+ 0xB067, 0xCEC2, 0xB068, 0xCEC3, 0xB069, 0xCEC4, 0xB06A, 0xCEC5, 0xB06B, 0xCEC6, 0xB06C, 0xCEC7, 0xB06D, 0xCEC8, 0xB06E, 0xCEC9,
+ 0xB06F, 0xCECA, 0xB070, 0xCECB, 0xB071, 0xCECC, 0xB072, 0xCECD, 0xB073, 0xCECE, 0xB074, 0xCECF, 0xB075, 0xCED0, 0xB076, 0xCED1,
+ 0xB077, 0xCED2, 0xB078, 0xCED3, 0xB079, 0xCED4, 0xB07A, 0xCED5, 0xB081, 0xCED6, 0xB082, 0xCED7, 0xB083, 0xCED8, 0xB084, 0xCED9,
+ 0xB085, 0xCEDA, 0xB086, 0xCEDB, 0xB087, 0xCEDC, 0xB088, 0xCEDD, 0xB089, 0xCEDE, 0xB08A, 0xCEDF, 0xB08B, 0xCEE0, 0xB08C, 0xCEE1,
+ 0xB08D, 0xCEE2, 0xB08E, 0xCEE3, 0xB08F, 0xCEE6, 0xB090, 0xCEE7, 0xB091, 0xCEE9, 0xB092, 0xCEEA, 0xB093, 0xCEED, 0xB094, 0xCEEE,
+ 0xB095, 0xCEEF, 0xB096, 0xCEF0, 0xB097, 0xCEF1, 0xB098, 0xCEF2, 0xB099, 0xCEF3, 0xB09A, 0xCEF6, 0xB09B, 0xCEFA, 0xB09C, 0xCEFB,
+ 0xB09D, 0xCEFC, 0xB09E, 0xCEFD, 0xB09F, 0xCEFE, 0xB0A0, 0xCEFF, 0xB0A1, 0xAC00, 0xB0A2, 0xAC01, 0xB0A3, 0xAC04, 0xB0A4, 0xAC07,
+ 0xB0A5, 0xAC08, 0xB0A6, 0xAC09, 0xB0A7, 0xAC0A, 0xB0A8, 0xAC10, 0xB0A9, 0xAC11, 0xB0AA, 0xAC12, 0xB0AB, 0xAC13, 0xB0AC, 0xAC14,
+ 0xB0AD, 0xAC15, 0xB0AE, 0xAC16, 0xB0AF, 0xAC17, 0xB0B0, 0xAC19, 0xB0B1, 0xAC1A, 0xB0B2, 0xAC1B, 0xB0B3, 0xAC1C, 0xB0B4, 0xAC1D,
+ 0xB0B5, 0xAC20, 0xB0B6, 0xAC24, 0xB0B7, 0xAC2C, 0xB0B8, 0xAC2D, 0xB0B9, 0xAC2F, 0xB0BA, 0xAC30, 0xB0BB, 0xAC31, 0xB0BC, 0xAC38,
+ 0xB0BD, 0xAC39, 0xB0BE, 0xAC3C, 0xB0BF, 0xAC40, 0xB0C0, 0xAC4B, 0xB0C1, 0xAC4D, 0xB0C2, 0xAC54, 0xB0C3, 0xAC58, 0xB0C4, 0xAC5C,
+ 0xB0C5, 0xAC70, 0xB0C6, 0xAC71, 0xB0C7, 0xAC74, 0xB0C8, 0xAC77, 0xB0C9, 0xAC78, 0xB0CA, 0xAC7A, 0xB0CB, 0xAC80, 0xB0CC, 0xAC81,
+ 0xB0CD, 0xAC83, 0xB0CE, 0xAC84, 0xB0CF, 0xAC85, 0xB0D0, 0xAC86, 0xB0D1, 0xAC89, 0xB0D2, 0xAC8A, 0xB0D3, 0xAC8B, 0xB0D4, 0xAC8C,
+ 0xB0D5, 0xAC90, 0xB0D6, 0xAC94, 0xB0D7, 0xAC9C, 0xB0D8, 0xAC9D, 0xB0D9, 0xAC9F, 0xB0DA, 0xACA0, 0xB0DB, 0xACA1, 0xB0DC, 0xACA8,
+ 0xB0DD, 0xACA9, 0xB0DE, 0xACAA, 0xB0DF, 0xACAC, 0xB0E0, 0xACAF, 0xB0E1, 0xACB0, 0xB0E2, 0xACB8, 0xB0E3, 0xACB9, 0xB0E4, 0xACBB,
+ 0xB0E5, 0xACBC, 0xB0E6, 0xACBD, 0xB0E7, 0xACC1, 0xB0E8, 0xACC4, 0xB0E9, 0xACC8, 0xB0EA, 0xACCC, 0xB0EB, 0xACD5, 0xB0EC, 0xACD7,
+ 0xB0ED, 0xACE0, 0xB0EE, 0xACE1, 0xB0EF, 0xACE4, 0xB0F0, 0xACE7, 0xB0F1, 0xACE8, 0xB0F2, 0xACEA, 0xB0F3, 0xACEC, 0xB0F4, 0xACEF,
+ 0xB0F5, 0xACF0, 0xB0F6, 0xACF1, 0xB0F7, 0xACF3, 0xB0F8, 0xACF5, 0xB0F9, 0xACF6, 0xB0FA, 0xACFC, 0xB0FB, 0xACFD, 0xB0FC, 0xAD00,
+ 0xB0FD, 0xAD04, 0xB0FE, 0xAD06, 0xB141, 0xCF02, 0xB142, 0xCF03, 0xB143, 0xCF05, 0xB144, 0xCF06, 0xB145, 0xCF07, 0xB146, 0xCF09,
+ 0xB147, 0xCF0A, 0xB148, 0xCF0B, 0xB149, 0xCF0C, 0xB14A, 0xCF0D, 0xB14B, 0xCF0E, 0xB14C, 0xCF0F, 0xB14D, 0xCF12, 0xB14E, 0xCF14,
+ 0xB14F, 0xCF16, 0xB150, 0xCF17, 0xB151, 0xCF18, 0xB152, 0xCF19, 0xB153, 0xCF1A, 0xB154, 0xCF1B, 0xB155, 0xCF1D, 0xB156, 0xCF1E,
+ 0xB157, 0xCF1F, 0xB158, 0xCF21, 0xB159, 0xCF22, 0xB15A, 0xCF23, 0xB161, 0xCF25, 0xB162, 0xCF26, 0xB163, 0xCF27, 0xB164, 0xCF28,
+ 0xB165, 0xCF29, 0xB166, 0xCF2A, 0xB167, 0xCF2B, 0xB168, 0xCF2E, 0xB169, 0xCF32, 0xB16A, 0xCF33, 0xB16B, 0xCF34, 0xB16C, 0xCF35,
+ 0xB16D, 0xCF36, 0xB16E, 0xCF37, 0xB16F, 0xCF39, 0xB170, 0xCF3A, 0xB171, 0xCF3B, 0xB172, 0xCF3C, 0xB173, 0xCF3D, 0xB174, 0xCF3E,
+ 0xB175, 0xCF3F, 0xB176, 0xCF40, 0xB177, 0xCF41, 0xB178, 0xCF42, 0xB179, 0xCF43, 0xB17A, 0xCF44, 0xB181, 0xCF45, 0xB182, 0xCF46,
+ 0xB183, 0xCF47, 0xB184, 0xCF48, 0xB185, 0xCF49, 0xB186, 0xCF4A, 0xB187, 0xCF4B, 0xB188, 0xCF4C, 0xB189, 0xCF4D, 0xB18A, 0xCF4E,
+ 0xB18B, 0xCF4F, 0xB18C, 0xCF50, 0xB18D, 0xCF51, 0xB18E, 0xCF52, 0xB18F, 0xCF53, 0xB190, 0xCF56, 0xB191, 0xCF57, 0xB192, 0xCF59,
+ 0xB193, 0xCF5A, 0xB194, 0xCF5B, 0xB195, 0xCF5D, 0xB196, 0xCF5E, 0xB197, 0xCF5F, 0xB198, 0xCF60, 0xB199, 0xCF61, 0xB19A, 0xCF62,
+ 0xB19B, 0xCF63, 0xB19C, 0xCF66, 0xB19D, 0xCF68, 0xB19E, 0xCF6A, 0xB19F, 0xCF6B, 0xB1A0, 0xCF6C, 0xB1A1, 0xAD0C, 0xB1A2, 0xAD0D,
+ 0xB1A3, 0xAD0F, 0xB1A4, 0xAD11, 0xB1A5, 0xAD18, 0xB1A6, 0xAD1C, 0xB1A7, 0xAD20, 0xB1A8, 0xAD29, 0xB1A9, 0xAD2C, 0xB1AA, 0xAD2D,
+ 0xB1AB, 0xAD34, 0xB1AC, 0xAD35, 0xB1AD, 0xAD38, 0xB1AE, 0xAD3C, 0xB1AF, 0xAD44, 0xB1B0, 0xAD45, 0xB1B1, 0xAD47, 0xB1B2, 0xAD49,
+ 0xB1B3, 0xAD50, 0xB1B4, 0xAD54, 0xB1B5, 0xAD58, 0xB1B6, 0xAD61, 0xB1B7, 0xAD63, 0xB1B8, 0xAD6C, 0xB1B9, 0xAD6D, 0xB1BA, 0xAD70,
+ 0xB1BB, 0xAD73, 0xB1BC, 0xAD74, 0xB1BD, 0xAD75, 0xB1BE, 0xAD76, 0xB1BF, 0xAD7B, 0xB1C0, 0xAD7C, 0xB1C1, 0xAD7D, 0xB1C2, 0xAD7F,
+ 0xB1C3, 0xAD81, 0xB1C4, 0xAD82, 0xB1C5, 0xAD88, 0xB1C6, 0xAD89, 0xB1C7, 0xAD8C, 0xB1C8, 0xAD90, 0xB1C9, 0xAD9C, 0xB1CA, 0xAD9D,
+ 0xB1CB, 0xADA4, 0xB1CC, 0xADB7, 0xB1CD, 0xADC0, 0xB1CE, 0xADC1, 0xB1CF, 0xADC4, 0xB1D0, 0xADC8, 0xB1D1, 0xADD0, 0xB1D2, 0xADD1,
+ 0xB1D3, 0xADD3, 0xB1D4, 0xADDC, 0xB1D5, 0xADE0, 0xB1D6, 0xADE4, 0xB1D7, 0xADF8, 0xB1D8, 0xADF9, 0xB1D9, 0xADFC, 0xB1DA, 0xADFF,
+ 0xB1DB, 0xAE00, 0xB1DC, 0xAE01, 0xB1DD, 0xAE08, 0xB1DE, 0xAE09, 0xB1DF, 0xAE0B, 0xB1E0, 0xAE0D, 0xB1E1, 0xAE14, 0xB1E2, 0xAE30,
+ 0xB1E3, 0xAE31, 0xB1E4, 0xAE34, 0xB1E5, 0xAE37, 0xB1E6, 0xAE38, 0xB1E7, 0xAE3A, 0xB1E8, 0xAE40, 0xB1E9, 0xAE41, 0xB1EA, 0xAE43,
+ 0xB1EB, 0xAE45, 0xB1EC, 0xAE46, 0xB1ED, 0xAE4A, 0xB1EE, 0xAE4C, 0xB1EF, 0xAE4D, 0xB1F0, 0xAE4E, 0xB1F1, 0xAE50, 0xB1F2, 0xAE54,
+ 0xB1F3, 0xAE56, 0xB1F4, 0xAE5C, 0xB1F5, 0xAE5D, 0xB1F6, 0xAE5F, 0xB1F7, 0xAE60, 0xB1F8, 0xAE61, 0xB1F9, 0xAE65, 0xB1FA, 0xAE68,
+ 0xB1FB, 0xAE69, 0xB1FC, 0xAE6C, 0xB1FD, 0xAE70, 0xB1FE, 0xAE78, 0xB241, 0xCF6D, 0xB242, 0xCF6E, 0xB243, 0xCF6F, 0xB244, 0xCF72,
+ 0xB245, 0xCF73, 0xB246, 0xCF75, 0xB247, 0xCF76, 0xB248, 0xCF77, 0xB249, 0xCF79, 0xB24A, 0xCF7A, 0xB24B, 0xCF7B, 0xB24C, 0xCF7C,
+ 0xB24D, 0xCF7D, 0xB24E, 0xCF7E, 0xB24F, 0xCF7F, 0xB250, 0xCF81, 0xB251, 0xCF82, 0xB252, 0xCF83, 0xB253, 0xCF84, 0xB254, 0xCF86,
+ 0xB255, 0xCF87, 0xB256, 0xCF88, 0xB257, 0xCF89, 0xB258, 0xCF8A, 0xB259, 0xCF8B, 0xB25A, 0xCF8D, 0xB261, 0xCF8E, 0xB262, 0xCF8F,
+ 0xB263, 0xCF90, 0xB264, 0xCF91, 0xB265, 0xCF92, 0xB266, 0xCF93, 0xB267, 0xCF94, 0xB268, 0xCF95, 0xB269, 0xCF96, 0xB26A, 0xCF97,
+ 0xB26B, 0xCF98, 0xB26C, 0xCF99, 0xB26D, 0xCF9A, 0xB26E, 0xCF9B, 0xB26F, 0xCF9C, 0xB270, 0xCF9D, 0xB271, 0xCF9E, 0xB272, 0xCF9F,
+ 0xB273, 0xCFA0, 0xB274, 0xCFA2, 0xB275, 0xCFA3, 0xB276, 0xCFA4, 0xB277, 0xCFA5, 0xB278, 0xCFA6, 0xB279, 0xCFA7, 0xB27A, 0xCFA9,
+ 0xB281, 0xCFAA, 0xB282, 0xCFAB, 0xB283, 0xCFAC, 0xB284, 0xCFAD, 0xB285, 0xCFAE, 0xB286, 0xCFAF, 0xB287, 0xCFB1, 0xB288, 0xCFB2,
+ 0xB289, 0xCFB3, 0xB28A, 0xCFB4, 0xB28B, 0xCFB5, 0xB28C, 0xCFB6, 0xB28D, 0xCFB7, 0xB28E, 0xCFB8, 0xB28F, 0xCFB9, 0xB290, 0xCFBA,
+ 0xB291, 0xCFBB, 0xB292, 0xCFBC, 0xB293, 0xCFBD, 0xB294, 0xCFBE, 0xB295, 0xCFBF, 0xB296, 0xCFC0, 0xB297, 0xCFC1, 0xB298, 0xCFC2,
+ 0xB299, 0xCFC3, 0xB29A, 0xCFC5, 0xB29B, 0xCFC6, 0xB29C, 0xCFC7, 0xB29D, 0xCFC8, 0xB29E, 0xCFC9, 0xB29F, 0xCFCA, 0xB2A0, 0xCFCB,
+ 0xB2A1, 0xAE79, 0xB2A2, 0xAE7B, 0xB2A3, 0xAE7C, 0xB2A4, 0xAE7D, 0xB2A5, 0xAE84, 0xB2A6, 0xAE85, 0xB2A7, 0xAE8C, 0xB2A8, 0xAEBC,
+ 0xB2A9, 0xAEBD, 0xB2AA, 0xAEBE, 0xB2AB, 0xAEC0, 0xB2AC, 0xAEC4, 0xB2AD, 0xAECC, 0xB2AE, 0xAECD, 0xB2AF, 0xAECF, 0xB2B0, 0xAED0,
+ 0xB2B1, 0xAED1, 0xB2B2, 0xAED8, 0xB2B3, 0xAED9, 0xB2B4, 0xAEDC, 0xB2B5, 0xAEE8, 0xB2B6, 0xAEEB, 0xB2B7, 0xAEED, 0xB2B8, 0xAEF4,
+ 0xB2B9, 0xAEF8, 0xB2BA, 0xAEFC, 0xB2BB, 0xAF07, 0xB2BC, 0xAF08, 0xB2BD, 0xAF0D, 0xB2BE, 0xAF10, 0xB2BF, 0xAF2C, 0xB2C0, 0xAF2D,
+ 0xB2C1, 0xAF30, 0xB2C2, 0xAF32, 0xB2C3, 0xAF34, 0xB2C4, 0xAF3C, 0xB2C5, 0xAF3D, 0xB2C6, 0xAF3F, 0xB2C7, 0xAF41, 0xB2C8, 0xAF42,
+ 0xB2C9, 0xAF43, 0xB2CA, 0xAF48, 0xB2CB, 0xAF49, 0xB2CC, 0xAF50, 0xB2CD, 0xAF5C, 0xB2CE, 0xAF5D, 0xB2CF, 0xAF64, 0xB2D0, 0xAF65,
+ 0xB2D1, 0xAF79, 0xB2D2, 0xAF80, 0xB2D3, 0xAF84, 0xB2D4, 0xAF88, 0xB2D5, 0xAF90, 0xB2D6, 0xAF91, 0xB2D7, 0xAF95, 0xB2D8, 0xAF9C,
+ 0xB2D9, 0xAFB8, 0xB2DA, 0xAFB9, 0xB2DB, 0xAFBC, 0xB2DC, 0xAFC0, 0xB2DD, 0xAFC7, 0xB2DE, 0xAFC8, 0xB2DF, 0xAFC9, 0xB2E0, 0xAFCB,
+ 0xB2E1, 0xAFCD, 0xB2E2, 0xAFCE, 0xB2E3, 0xAFD4, 0xB2E4, 0xAFDC, 0xB2E5, 0xAFE8, 0xB2E6, 0xAFE9, 0xB2E7, 0xAFF0, 0xB2E8, 0xAFF1,
+ 0xB2E9, 0xAFF4, 0xB2EA, 0xAFF8, 0xB2EB, 0xB000, 0xB2EC, 0xB001, 0xB2ED, 0xB004, 0xB2EE, 0xB00C, 0xB2EF, 0xB010, 0xB2F0, 0xB014,
+ 0xB2F1, 0xB01C, 0xB2F2, 0xB01D, 0xB2F3, 0xB028, 0xB2F4, 0xB044, 0xB2F5, 0xB045, 0xB2F6, 0xB048, 0xB2F7, 0xB04A, 0xB2F8, 0xB04C,
+ 0xB2F9, 0xB04E, 0xB2FA, 0xB053, 0xB2FB, 0xB054, 0xB2FC, 0xB055, 0xB2FD, 0xB057, 0xB2FE, 0xB059, 0xB341, 0xCFCC, 0xB342, 0xCFCD,
+ 0xB343, 0xCFCE, 0xB344, 0xCFCF, 0xB345, 0xCFD0, 0xB346, 0xCFD1, 0xB347, 0xCFD2, 0xB348, 0xCFD3, 0xB349, 0xCFD4, 0xB34A, 0xCFD5,
+ 0xB34B, 0xCFD6, 0xB34C, 0xCFD7, 0xB34D, 0xCFD8, 0xB34E, 0xCFD9, 0xB34F, 0xCFDA, 0xB350, 0xCFDB, 0xB351, 0xCFDC, 0xB352, 0xCFDD,
+ 0xB353, 0xCFDE, 0xB354, 0xCFDF, 0xB355, 0xCFE2, 0xB356, 0xCFE3, 0xB357, 0xCFE5, 0xB358, 0xCFE6, 0xB359, 0xCFE7, 0xB35A, 0xCFE9,
+ 0xB361, 0xCFEA, 0xB362, 0xCFEB, 0xB363, 0xCFEC, 0xB364, 0xCFED, 0xB365, 0xCFEE, 0xB366, 0xCFEF, 0xB367, 0xCFF2, 0xB368, 0xCFF4,
+ 0xB369, 0xCFF6, 0xB36A, 0xCFF7, 0xB36B, 0xCFF8, 0xB36C, 0xCFF9, 0xB36D, 0xCFFA, 0xB36E, 0xCFFB, 0xB36F, 0xCFFD, 0xB370, 0xCFFE,
+ 0xB371, 0xCFFF, 0xB372, 0xD001, 0xB373, 0xD002, 0xB374, 0xD003, 0xB375, 0xD005, 0xB376, 0xD006, 0xB377, 0xD007, 0xB378, 0xD008,
+ 0xB379, 0xD009, 0xB37A, 0xD00A, 0xB381, 0xD00B, 0xB382, 0xD00C, 0xB383, 0xD00D, 0xB384, 0xD00E, 0xB385, 0xD00F, 0xB386, 0xD010,
+ 0xB387, 0xD012, 0xB388, 0xD013, 0xB389, 0xD014, 0xB38A, 0xD015, 0xB38B, 0xD016, 0xB38C, 0xD017, 0xB38D, 0xD019, 0xB38E, 0xD01A,
+ 0xB38F, 0xD01B, 0xB390, 0xD01C, 0xB391, 0xD01D, 0xB392, 0xD01E, 0xB393, 0xD01F, 0xB394, 0xD020, 0xB395, 0xD021, 0xB396, 0xD022,
+ 0xB397, 0xD023, 0xB398, 0xD024, 0xB399, 0xD025, 0xB39A, 0xD026, 0xB39B, 0xD027, 0xB39C, 0xD028, 0xB39D, 0xD029, 0xB39E, 0xD02A,
+ 0xB39F, 0xD02B, 0xB3A0, 0xD02C, 0xB3A1, 0xB05D, 0xB3A2, 0xB07C, 0xB3A3, 0xB07D, 0xB3A4, 0xB080, 0xB3A5, 0xB084, 0xB3A6, 0xB08C,
+ 0xB3A7, 0xB08D, 0xB3A8, 0xB08F, 0xB3A9, 0xB091, 0xB3AA, 0xB098, 0xB3AB, 0xB099, 0xB3AC, 0xB09A, 0xB3AD, 0xB09C, 0xB3AE, 0xB09F,
+ 0xB3AF, 0xB0A0, 0xB3B0, 0xB0A1, 0xB3B1, 0xB0A2, 0xB3B2, 0xB0A8, 0xB3B3, 0xB0A9, 0xB3B4, 0xB0AB, 0xB3B5, 0xB0AC, 0xB3B6, 0xB0AD,
+ 0xB3B7, 0xB0AE, 0xB3B8, 0xB0AF, 0xB3B9, 0xB0B1, 0xB3BA, 0xB0B3, 0xB3BB, 0xB0B4, 0xB3BC, 0xB0B5, 0xB3BD, 0xB0B8, 0xB3BE, 0xB0BC,
+ 0xB3BF, 0xB0C4, 0xB3C0, 0xB0C5, 0xB3C1, 0xB0C7, 0xB3C2, 0xB0C8, 0xB3C3, 0xB0C9, 0xB3C4, 0xB0D0, 0xB3C5, 0xB0D1, 0xB3C6, 0xB0D4,
+ 0xB3C7, 0xB0D8, 0xB3C8, 0xB0E0, 0xB3C9, 0xB0E5, 0xB3CA, 0xB108, 0xB3CB, 0xB109, 0xB3CC, 0xB10B, 0xB3CD, 0xB10C, 0xB3CE, 0xB110,
+ 0xB3CF, 0xB112, 0xB3D0, 0xB113, 0xB3D1, 0xB118, 0xB3D2, 0xB119, 0xB3D3, 0xB11B, 0xB3D4, 0xB11C, 0xB3D5, 0xB11D, 0xB3D6, 0xB123,
+ 0xB3D7, 0xB124, 0xB3D8, 0xB125, 0xB3D9, 0xB128, 0xB3DA, 0xB12C, 0xB3DB, 0xB134, 0xB3DC, 0xB135, 0xB3DD, 0xB137, 0xB3DE, 0xB138,
+ 0xB3DF, 0xB139, 0xB3E0, 0xB140, 0xB3E1, 0xB141, 0xB3E2, 0xB144, 0xB3E3, 0xB148, 0xB3E4, 0xB150, 0xB3E5, 0xB151, 0xB3E6, 0xB154,
+ 0xB3E7, 0xB155, 0xB3E8, 0xB158, 0xB3E9, 0xB15C, 0xB3EA, 0xB160, 0xB3EB, 0xB178, 0xB3EC, 0xB179, 0xB3ED, 0xB17C, 0xB3EE, 0xB180,
+ 0xB3EF, 0xB182, 0xB3F0, 0xB188, 0xB3F1, 0xB189, 0xB3F2, 0xB18B, 0xB3F3, 0xB18D, 0xB3F4, 0xB192, 0xB3F5, 0xB193, 0xB3F6, 0xB194,
+ 0xB3F7, 0xB198, 0xB3F8, 0xB19C, 0xB3F9, 0xB1A8, 0xB3FA, 0xB1CC, 0xB3FB, 0xB1D0, 0xB3FC, 0xB1D4, 0xB3FD, 0xB1DC, 0xB3FE, 0xB1DD,
+ 0xB441, 0xD02E, 0xB442, 0xD02F, 0xB443, 0xD030, 0xB444, 0xD031, 0xB445, 0xD032, 0xB446, 0xD033, 0xB447, 0xD036, 0xB448, 0xD037,
+ 0xB449, 0xD039, 0xB44A, 0xD03A, 0xB44B, 0xD03B, 0xB44C, 0xD03D, 0xB44D, 0xD03E, 0xB44E, 0xD03F, 0xB44F, 0xD040, 0xB450, 0xD041,
+ 0xB451, 0xD042, 0xB452, 0xD043, 0xB453, 0xD046, 0xB454, 0xD048, 0xB455, 0xD04A, 0xB456, 0xD04B, 0xB457, 0xD04C, 0xB458, 0xD04D,
+ 0xB459, 0xD04E, 0xB45A, 0xD04F, 0xB461, 0xD051, 0xB462, 0xD052, 0xB463, 0xD053, 0xB464, 0xD055, 0xB465, 0xD056, 0xB466, 0xD057,
+ 0xB467, 0xD059, 0xB468, 0xD05A, 0xB469, 0xD05B, 0xB46A, 0xD05C, 0xB46B, 0xD05D, 0xB46C, 0xD05E, 0xB46D, 0xD05F, 0xB46E, 0xD061,
+ 0xB46F, 0xD062, 0xB470, 0xD063, 0xB471, 0xD064, 0xB472, 0xD065, 0xB473, 0xD066, 0xB474, 0xD067, 0xB475, 0xD068, 0xB476, 0xD069,
+ 0xB477, 0xD06A, 0xB478, 0xD06B, 0xB479, 0xD06E, 0xB47A, 0xD06F, 0xB481, 0xD071, 0xB482, 0xD072, 0xB483, 0xD073, 0xB484, 0xD075,
+ 0xB485, 0xD076, 0xB486, 0xD077, 0xB487, 0xD078, 0xB488, 0xD079, 0xB489, 0xD07A, 0xB48A, 0xD07B, 0xB48B, 0xD07E, 0xB48C, 0xD07F,
+ 0xB48D, 0xD080, 0xB48E, 0xD082, 0xB48F, 0xD083, 0xB490, 0xD084, 0xB491, 0xD085, 0xB492, 0xD086, 0xB493, 0xD087, 0xB494, 0xD088,
+ 0xB495, 0xD089, 0xB496, 0xD08A, 0xB497, 0xD08B, 0xB498, 0xD08C, 0xB499, 0xD08D, 0xB49A, 0xD08E, 0xB49B, 0xD08F, 0xB49C, 0xD090,
+ 0xB49D, 0xD091, 0xB49E, 0xD092, 0xB49F, 0xD093, 0xB4A0, 0xD094, 0xB4A1, 0xB1DF, 0xB4A2, 0xB1E8, 0xB4A3, 0xB1E9, 0xB4A4, 0xB1EC,
+ 0xB4A5, 0xB1F0, 0xB4A6, 0xB1F9, 0xB4A7, 0xB1FB, 0xB4A8, 0xB1FD, 0xB4A9, 0xB204, 0xB4AA, 0xB205, 0xB4AB, 0xB208, 0xB4AC, 0xB20B,
+ 0xB4AD, 0xB20C, 0xB4AE, 0xB214, 0xB4AF, 0xB215, 0xB4B0, 0xB217, 0xB4B1, 0xB219, 0xB4B2, 0xB220, 0xB4B3, 0xB234, 0xB4B4, 0xB23C,
+ 0xB4B5, 0xB258, 0xB4B6, 0xB25C, 0xB4B7, 0xB260, 0xB4B8, 0xB268, 0xB4B9, 0xB269, 0xB4BA, 0xB274, 0xB4BB, 0xB275, 0xB4BC, 0xB27C,
+ 0xB4BD, 0xB284, 0xB4BE, 0xB285, 0xB4BF, 0xB289, 0xB4C0, 0xB290, 0xB4C1, 0xB291, 0xB4C2, 0xB294, 0xB4C3, 0xB298, 0xB4C4, 0xB299,
+ 0xB4C5, 0xB29A, 0xB4C6, 0xB2A0, 0xB4C7, 0xB2A1, 0xB4C8, 0xB2A3, 0xB4C9, 0xB2A5, 0xB4CA, 0xB2A6, 0xB4CB, 0xB2AA, 0xB4CC, 0xB2AC,
+ 0xB4CD, 0xB2B0, 0xB4CE, 0xB2B4, 0xB4CF, 0xB2C8, 0xB4D0, 0xB2C9, 0xB4D1, 0xB2CC, 0xB4D2, 0xB2D0, 0xB4D3, 0xB2D2, 0xB4D4, 0xB2D8,
+ 0xB4D5, 0xB2D9, 0xB4D6, 0xB2DB, 0xB4D7, 0xB2DD, 0xB4D8, 0xB2E2, 0xB4D9, 0xB2E4, 0xB4DA, 0xB2E5, 0xB4DB, 0xB2E6, 0xB4DC, 0xB2E8,
+ 0xB4DD, 0xB2EB, 0xB4DE, 0xB2EC, 0xB4DF, 0xB2ED, 0xB4E0, 0xB2EE, 0xB4E1, 0xB2EF, 0xB4E2, 0xB2F3, 0xB4E3, 0xB2F4, 0xB4E4, 0xB2F5,
+ 0xB4E5, 0xB2F7, 0xB4E6, 0xB2F8, 0xB4E7, 0xB2F9, 0xB4E8, 0xB2FA, 0xB4E9, 0xB2FB, 0xB4EA, 0xB2FF, 0xB4EB, 0xB300, 0xB4EC, 0xB301,
+ 0xB4ED, 0xB304, 0xB4EE, 0xB308, 0xB4EF, 0xB310, 0xB4F0, 0xB311, 0xB4F1, 0xB313, 0xB4F2, 0xB314, 0xB4F3, 0xB315, 0xB4F4, 0xB31C,
+ 0xB4F5, 0xB354, 0xB4F6, 0xB355, 0xB4F7, 0xB356, 0xB4F8, 0xB358, 0xB4F9, 0xB35B, 0xB4FA, 0xB35C, 0xB4FB, 0xB35E, 0xB4FC, 0xB35F,
+ 0xB4FD, 0xB364, 0xB4FE, 0xB365, 0xB541, 0xD095, 0xB542, 0xD096, 0xB543, 0xD097, 0xB544, 0xD098, 0xB545, 0xD099, 0xB546, 0xD09A,
+ 0xB547, 0xD09B, 0xB548, 0xD09C, 0xB549, 0xD09D, 0xB54A, 0xD09E, 0xB54B, 0xD09F, 0xB54C, 0xD0A0, 0xB54D, 0xD0A1, 0xB54E, 0xD0A2,
+ 0xB54F, 0xD0A3, 0xB550, 0xD0A6, 0xB551, 0xD0A7, 0xB552, 0xD0A9, 0xB553, 0xD0AA, 0xB554, 0xD0AB, 0xB555, 0xD0AD, 0xB556, 0xD0AE,
+ 0xB557, 0xD0AF, 0xB558, 0xD0B0, 0xB559, 0xD0B1, 0xB55A, 0xD0B2, 0xB561, 0xD0B3, 0xB562, 0xD0B6, 0xB563, 0xD0B8, 0xB564, 0xD0BA,
+ 0xB565, 0xD0BB, 0xB566, 0xD0BC, 0xB567, 0xD0BD, 0xB568, 0xD0BE, 0xB569, 0xD0BF, 0xB56A, 0xD0C2, 0xB56B, 0xD0C3, 0xB56C, 0xD0C5,
+ 0xB56D, 0xD0C6, 0xB56E, 0xD0C7, 0xB56F, 0xD0CA, 0xB570, 0xD0CB, 0xB571, 0xD0CC, 0xB572, 0xD0CD, 0xB573, 0xD0CE, 0xB574, 0xD0CF,
+ 0xB575, 0xD0D2, 0xB576, 0xD0D6, 0xB577, 0xD0D7, 0xB578, 0xD0D8, 0xB579, 0xD0D9, 0xB57A, 0xD0DA, 0xB581, 0xD0DB, 0xB582, 0xD0DE,
+ 0xB583, 0xD0DF, 0xB584, 0xD0E1, 0xB585, 0xD0E2, 0xB586, 0xD0E3, 0xB587, 0xD0E5, 0xB588, 0xD0E6, 0xB589, 0xD0E7, 0xB58A, 0xD0E8,
+ 0xB58B, 0xD0E9, 0xB58C, 0xD0EA, 0xB58D, 0xD0EB, 0xB58E, 0xD0EE, 0xB58F, 0xD0F2, 0xB590, 0xD0F3, 0xB591, 0xD0F4, 0xB592, 0xD0F5,
+ 0xB593, 0xD0F6, 0xB594, 0xD0F7, 0xB595, 0xD0F9, 0xB596, 0xD0FA, 0xB597, 0xD0FB, 0xB598, 0xD0FC, 0xB599, 0xD0FD, 0xB59A, 0xD0FE,
+ 0xB59B, 0xD0FF, 0xB59C, 0xD100, 0xB59D, 0xD101, 0xB59E, 0xD102, 0xB59F, 0xD103, 0xB5A0, 0xD104, 0xB5A1, 0xB367, 0xB5A2, 0xB369,
+ 0xB5A3, 0xB36B, 0xB5A4, 0xB36E, 0xB5A5, 0xB370, 0xB5A6, 0xB371, 0xB5A7, 0xB374, 0xB5A8, 0xB378, 0xB5A9, 0xB380, 0xB5AA, 0xB381,
+ 0xB5AB, 0xB383, 0xB5AC, 0xB384, 0xB5AD, 0xB385, 0xB5AE, 0xB38C, 0xB5AF, 0xB390, 0xB5B0, 0xB394, 0xB5B1, 0xB3A0, 0xB5B2, 0xB3A1,
+ 0xB5B3, 0xB3A8, 0xB5B4, 0xB3AC, 0xB5B5, 0xB3C4, 0xB5B6, 0xB3C5, 0xB5B7, 0xB3C8, 0xB5B8, 0xB3CB, 0xB5B9, 0xB3CC, 0xB5BA, 0xB3CE,
+ 0xB5BB, 0xB3D0, 0xB5BC, 0xB3D4, 0xB5BD, 0xB3D5, 0xB5BE, 0xB3D7, 0xB5BF, 0xB3D9, 0xB5C0, 0xB3DB, 0xB5C1, 0xB3DD, 0xB5C2, 0xB3E0,
+ 0xB5C3, 0xB3E4, 0xB5C4, 0xB3E8, 0xB5C5, 0xB3FC, 0xB5C6, 0xB410, 0xB5C7, 0xB418, 0xB5C8, 0xB41C, 0xB5C9, 0xB420, 0xB5CA, 0xB428,
+ 0xB5CB, 0xB429, 0xB5CC, 0xB42B, 0xB5CD, 0xB434, 0xB5CE, 0xB450, 0xB5CF, 0xB451, 0xB5D0, 0xB454, 0xB5D1, 0xB458, 0xB5D2, 0xB460,
+ 0xB5D3, 0xB461, 0xB5D4, 0xB463, 0xB5D5, 0xB465, 0xB5D6, 0xB46C, 0xB5D7, 0xB480, 0xB5D8, 0xB488, 0xB5D9, 0xB49D, 0xB5DA, 0xB4A4,
+ 0xB5DB, 0xB4A8, 0xB5DC, 0xB4AC, 0xB5DD, 0xB4B5, 0xB5DE, 0xB4B7, 0xB5DF, 0xB4B9, 0xB5E0, 0xB4C0, 0xB5E1, 0xB4C4, 0xB5E2, 0xB4C8,
+ 0xB5E3, 0xB4D0, 0xB5E4, 0xB4D5, 0xB5E5, 0xB4DC, 0xB5E6, 0xB4DD, 0xB5E7, 0xB4E0, 0xB5E8, 0xB4E3, 0xB5E9, 0xB4E4, 0xB5EA, 0xB4E6,
+ 0xB5EB, 0xB4EC, 0xB5EC, 0xB4ED, 0xB5ED, 0xB4EF, 0xB5EE, 0xB4F1, 0xB5EF, 0xB4F8, 0xB5F0, 0xB514, 0xB5F1, 0xB515, 0xB5F2, 0xB518,
+ 0xB5F3, 0xB51B, 0xB5F4, 0xB51C, 0xB5F5, 0xB524, 0xB5F6, 0xB525, 0xB5F7, 0xB527, 0xB5F8, 0xB528, 0xB5F9, 0xB529, 0xB5FA, 0xB52A,
+ 0xB5FB, 0xB530, 0xB5FC, 0xB531, 0xB5FD, 0xB534, 0xB5FE, 0xB538, 0xB641, 0xD105, 0xB642, 0xD106, 0xB643, 0xD107, 0xB644, 0xD108,
+ 0xB645, 0xD109, 0xB646, 0xD10A, 0xB647, 0xD10B, 0xB648, 0xD10C, 0xB649, 0xD10E, 0xB64A, 0xD10F, 0xB64B, 0xD110, 0xB64C, 0xD111,
+ 0xB64D, 0xD112, 0xB64E, 0xD113, 0xB64F, 0xD114, 0xB650, 0xD115, 0xB651, 0xD116, 0xB652, 0xD117, 0xB653, 0xD118, 0xB654, 0xD119,
+ 0xB655, 0xD11A, 0xB656, 0xD11B, 0xB657, 0xD11C, 0xB658, 0xD11D, 0xB659, 0xD11E, 0xB65A, 0xD11F, 0xB661, 0xD120, 0xB662, 0xD121,
+ 0xB663, 0xD122, 0xB664, 0xD123, 0xB665, 0xD124, 0xB666, 0xD125, 0xB667, 0xD126, 0xB668, 0xD127, 0xB669, 0xD128, 0xB66A, 0xD129,
+ 0xB66B, 0xD12A, 0xB66C, 0xD12B, 0xB66D, 0xD12C, 0xB66E, 0xD12D, 0xB66F, 0xD12E, 0xB670, 0xD12F, 0xB671, 0xD132, 0xB672, 0xD133,
+ 0xB673, 0xD135, 0xB674, 0xD136, 0xB675, 0xD137, 0xB676, 0xD139, 0xB677, 0xD13B, 0xB678, 0xD13C, 0xB679, 0xD13D, 0xB67A, 0xD13E,
+ 0xB681, 0xD13F, 0xB682, 0xD142, 0xB683, 0xD146, 0xB684, 0xD147, 0xB685, 0xD148, 0xB686, 0xD149, 0xB687, 0xD14A, 0xB688, 0xD14B,
+ 0xB689, 0xD14E, 0xB68A, 0xD14F, 0xB68B, 0xD151, 0xB68C, 0xD152, 0xB68D, 0xD153, 0xB68E, 0xD155, 0xB68F, 0xD156, 0xB690, 0xD157,
+ 0xB691, 0xD158, 0xB692, 0xD159, 0xB693, 0xD15A, 0xB694, 0xD15B, 0xB695, 0xD15E, 0xB696, 0xD160, 0xB697, 0xD162, 0xB698, 0xD163,
+ 0xB699, 0xD164, 0xB69A, 0xD165, 0xB69B, 0xD166, 0xB69C, 0xD167, 0xB69D, 0xD169, 0xB69E, 0xD16A, 0xB69F, 0xD16B, 0xB6A0, 0xD16D,
+ 0xB6A1, 0xB540, 0xB6A2, 0xB541, 0xB6A3, 0xB543, 0xB6A4, 0xB544, 0xB6A5, 0xB545, 0xB6A6, 0xB54B, 0xB6A7, 0xB54C, 0xB6A8, 0xB54D,
+ 0xB6A9, 0xB550, 0xB6AA, 0xB554, 0xB6AB, 0xB55C, 0xB6AC, 0xB55D, 0xB6AD, 0xB55F, 0xB6AE, 0xB560, 0xB6AF, 0xB561, 0xB6B0, 0xB5A0,
+ 0xB6B1, 0xB5A1, 0xB6B2, 0xB5A4, 0xB6B3, 0xB5A8, 0xB6B4, 0xB5AA, 0xB6B5, 0xB5AB, 0xB6B6, 0xB5B0, 0xB6B7, 0xB5B1, 0xB6B8, 0xB5B3,
+ 0xB6B9, 0xB5B4, 0xB6BA, 0xB5B5, 0xB6BB, 0xB5BB, 0xB6BC, 0xB5BC, 0xB6BD, 0xB5BD, 0xB6BE, 0xB5C0, 0xB6BF, 0xB5C4, 0xB6C0, 0xB5CC,
+ 0xB6C1, 0xB5CD, 0xB6C2, 0xB5CF, 0xB6C3, 0xB5D0, 0xB6C4, 0xB5D1, 0xB6C5, 0xB5D8, 0xB6C6, 0xB5EC, 0xB6C7, 0xB610, 0xB6C8, 0xB611,
+ 0xB6C9, 0xB614, 0xB6CA, 0xB618, 0xB6CB, 0xB625, 0xB6CC, 0xB62C, 0xB6CD, 0xB634, 0xB6CE, 0xB648, 0xB6CF, 0xB664, 0xB6D0, 0xB668,
+ 0xB6D1, 0xB69C, 0xB6D2, 0xB69D, 0xB6D3, 0xB6A0, 0xB6D4, 0xB6A4, 0xB6D5, 0xB6AB, 0xB6D6, 0xB6AC, 0xB6D7, 0xB6B1, 0xB6D8, 0xB6D4,
+ 0xB6D9, 0xB6F0, 0xB6DA, 0xB6F4, 0xB6DB, 0xB6F8, 0xB6DC, 0xB700, 0xB6DD, 0xB701, 0xB6DE, 0xB705, 0xB6DF, 0xB728, 0xB6E0, 0xB729,
+ 0xB6E1, 0xB72C, 0xB6E2, 0xB72F, 0xB6E3, 0xB730, 0xB6E4, 0xB738, 0xB6E5, 0xB739, 0xB6E6, 0xB73B, 0xB6E7, 0xB744, 0xB6E8, 0xB748,
+ 0xB6E9, 0xB74C, 0xB6EA, 0xB754, 0xB6EB, 0xB755, 0xB6EC, 0xB760, 0xB6ED, 0xB764, 0xB6EE, 0xB768, 0xB6EF, 0xB770, 0xB6F0, 0xB771,
+ 0xB6F1, 0xB773, 0xB6F2, 0xB775, 0xB6F3, 0xB77C, 0xB6F4, 0xB77D, 0xB6F5, 0xB780, 0xB6F6, 0xB784, 0xB6F7, 0xB78C, 0xB6F8, 0xB78D,
+ 0xB6F9, 0xB78F, 0xB6FA, 0xB790, 0xB6FB, 0xB791, 0xB6FC, 0xB792, 0xB6FD, 0xB796, 0xB6FE, 0xB797, 0xB741, 0xD16E, 0xB742, 0xD16F,
+ 0xB743, 0xD170, 0xB744, 0xD171, 0xB745, 0xD172, 0xB746, 0xD173, 0xB747, 0xD174, 0xB748, 0xD175, 0xB749, 0xD176, 0xB74A, 0xD177,
+ 0xB74B, 0xD178, 0xB74C, 0xD179, 0xB74D, 0xD17A, 0xB74E, 0xD17B, 0xB74F, 0xD17D, 0xB750, 0xD17E, 0xB751, 0xD17F, 0xB752, 0xD180,
+ 0xB753, 0xD181, 0xB754, 0xD182, 0xB755, 0xD183, 0xB756, 0xD185, 0xB757, 0xD186, 0xB758, 0xD187, 0xB759, 0xD189, 0xB75A, 0xD18A,
+ 0xB761, 0xD18B, 0xB762, 0xD18C, 0xB763, 0xD18D, 0xB764, 0xD18E, 0xB765, 0xD18F, 0xB766, 0xD190, 0xB767, 0xD191, 0xB768, 0xD192,
+ 0xB769, 0xD193, 0xB76A, 0xD194, 0xB76B, 0xD195, 0xB76C, 0xD196, 0xB76D, 0xD197, 0xB76E, 0xD198, 0xB76F, 0xD199, 0xB770, 0xD19A,
+ 0xB771, 0xD19B, 0xB772, 0xD19C, 0xB773, 0xD19D, 0xB774, 0xD19E, 0xB775, 0xD19F, 0xB776, 0xD1A2, 0xB777, 0xD1A3, 0xB778, 0xD1A5,
+ 0xB779, 0xD1A6, 0xB77A, 0xD1A7, 0xB781, 0xD1A9, 0xB782, 0xD1AA, 0xB783, 0xD1AB, 0xB784, 0xD1AC, 0xB785, 0xD1AD, 0xB786, 0xD1AE,
+ 0xB787, 0xD1AF, 0xB788, 0xD1B2, 0xB789, 0xD1B4, 0xB78A, 0xD1B6, 0xB78B, 0xD1B7, 0xB78C, 0xD1B8, 0xB78D, 0xD1B9, 0xB78E, 0xD1BB,
+ 0xB78F, 0xD1BD, 0xB790, 0xD1BE, 0xB791, 0xD1BF, 0xB792, 0xD1C1, 0xB793, 0xD1C2, 0xB794, 0xD1C3, 0xB795, 0xD1C4, 0xB796, 0xD1C5,
+ 0xB797, 0xD1C6, 0xB798, 0xD1C7, 0xB799, 0xD1C8, 0xB79A, 0xD1C9, 0xB79B, 0xD1CA, 0xB79C, 0xD1CB, 0xB79D, 0xD1CC, 0xB79E, 0xD1CD,
+ 0xB79F, 0xD1CE, 0xB7A0, 0xD1CF, 0xB7A1, 0xB798, 0xB7A2, 0xB799, 0xB7A3, 0xB79C, 0xB7A4, 0xB7A0, 0xB7A5, 0xB7A8, 0xB7A6, 0xB7A9,
+ 0xB7A7, 0xB7AB, 0xB7A8, 0xB7AC, 0xB7A9, 0xB7AD, 0xB7AA, 0xB7B4, 0xB7AB, 0xB7B5, 0xB7AC, 0xB7B8, 0xB7AD, 0xB7C7, 0xB7AE, 0xB7C9,
+ 0xB7AF, 0xB7EC, 0xB7B0, 0xB7ED, 0xB7B1, 0xB7F0, 0xB7B2, 0xB7F4, 0xB7B3, 0xB7FC, 0xB7B4, 0xB7FD, 0xB7B5, 0xB7FF, 0xB7B6, 0xB800,
+ 0xB7B7, 0xB801, 0xB7B8, 0xB807, 0xB7B9, 0xB808, 0xB7BA, 0xB809, 0xB7BB, 0xB80C, 0xB7BC, 0xB810, 0xB7BD, 0xB818, 0xB7BE, 0xB819,
+ 0xB7BF, 0xB81B, 0xB7C0, 0xB81D, 0xB7C1, 0xB824, 0xB7C2, 0xB825, 0xB7C3, 0xB828, 0xB7C4, 0xB82C, 0xB7C5, 0xB834, 0xB7C6, 0xB835,
+ 0xB7C7, 0xB837, 0xB7C8, 0xB838, 0xB7C9, 0xB839, 0xB7CA, 0xB840, 0xB7CB, 0xB844, 0xB7CC, 0xB851, 0xB7CD, 0xB853, 0xB7CE, 0xB85C,
+ 0xB7CF, 0xB85D, 0xB7D0, 0xB860, 0xB7D1, 0xB864, 0xB7D2, 0xB86C, 0xB7D3, 0xB86D, 0xB7D4, 0xB86F, 0xB7D5, 0xB871, 0xB7D6, 0xB878,
+ 0xB7D7, 0xB87C, 0xB7D8, 0xB88D, 0xB7D9, 0xB8A8, 0xB7DA, 0xB8B0, 0xB7DB, 0xB8B4, 0xB7DC, 0xB8B8, 0xB7DD, 0xB8C0, 0xB7DE, 0xB8C1,
+ 0xB7DF, 0xB8C3, 0xB7E0, 0xB8C5, 0xB7E1, 0xB8CC, 0xB7E2, 0xB8D0, 0xB7E3, 0xB8D4, 0xB7E4, 0xB8DD, 0xB7E5, 0xB8DF, 0xB7E6, 0xB8E1,
+ 0xB7E7, 0xB8E8, 0xB7E8, 0xB8E9, 0xB7E9, 0xB8EC, 0xB7EA, 0xB8F0, 0xB7EB, 0xB8F8, 0xB7EC, 0xB8F9, 0xB7ED, 0xB8FB, 0xB7EE, 0xB8FD,
+ 0xB7EF, 0xB904, 0xB7F0, 0xB918, 0xB7F1, 0xB920, 0xB7F2, 0xB93C, 0xB7F3, 0xB93D, 0xB7F4, 0xB940, 0xB7F5, 0xB944, 0xB7F6, 0xB94C,
+ 0xB7F7, 0xB94F, 0xB7F8, 0xB951, 0xB7F9, 0xB958, 0xB7FA, 0xB959, 0xB7FB, 0xB95C, 0xB7FC, 0xB960, 0xB7FD, 0xB968, 0xB7FE, 0xB969,
+ 0xB841, 0xD1D0, 0xB842, 0xD1D1, 0xB843, 0xD1D2, 0xB844, 0xD1D3, 0xB845, 0xD1D4, 0xB846, 0xD1D5, 0xB847, 0xD1D6, 0xB848, 0xD1D7,
+ 0xB849, 0xD1D9, 0xB84A, 0xD1DA, 0xB84B, 0xD1DB, 0xB84C, 0xD1DC, 0xB84D, 0xD1DD, 0xB84E, 0xD1DE, 0xB84F, 0xD1DF, 0xB850, 0xD1E0,
+ 0xB851, 0xD1E1, 0xB852, 0xD1E2, 0xB853, 0xD1E3, 0xB854, 0xD1E4, 0xB855, 0xD1E5, 0xB856, 0xD1E6, 0xB857, 0xD1E7, 0xB858, 0xD1E8,
+ 0xB859, 0xD1E9, 0xB85A, 0xD1EA, 0xB861, 0xD1EB, 0xB862, 0xD1EC, 0xB863, 0xD1ED, 0xB864, 0xD1EE, 0xB865, 0xD1EF, 0xB866, 0xD1F0,
+ 0xB867, 0xD1F1, 0xB868, 0xD1F2, 0xB869, 0xD1F3, 0xB86A, 0xD1F5, 0xB86B, 0xD1F6, 0xB86C, 0xD1F7, 0xB86D, 0xD1F9, 0xB86E, 0xD1FA,
+ 0xB86F, 0xD1FB, 0xB870, 0xD1FC, 0xB871, 0xD1FD, 0xB872, 0xD1FE, 0xB873, 0xD1FF, 0xB874, 0xD200, 0xB875, 0xD201, 0xB876, 0xD202,
+ 0xB877, 0xD203, 0xB878, 0xD204, 0xB879, 0xD205, 0xB87A, 0xD206, 0xB881, 0xD208, 0xB882, 0xD20A, 0xB883, 0xD20B, 0xB884, 0xD20C,
+ 0xB885, 0xD20D, 0xB886, 0xD20E, 0xB887, 0xD20F, 0xB888, 0xD211, 0xB889, 0xD212, 0xB88A, 0xD213, 0xB88B, 0xD214, 0xB88C, 0xD215,
+ 0xB88D, 0xD216, 0xB88E, 0xD217, 0xB88F, 0xD218, 0xB890, 0xD219, 0xB891, 0xD21A, 0xB892, 0xD21B, 0xB893, 0xD21C, 0xB894, 0xD21D,
+ 0xB895, 0xD21E, 0xB896, 0xD21F, 0xB897, 0xD220, 0xB898, 0xD221, 0xB899, 0xD222, 0xB89A, 0xD223, 0xB89B, 0xD224, 0xB89C, 0xD225,
+ 0xB89D, 0xD226, 0xB89E, 0xD227, 0xB89F, 0xD228, 0xB8A0, 0xD229, 0xB8A1, 0xB96B, 0xB8A2, 0xB96D, 0xB8A3, 0xB974, 0xB8A4, 0xB975,
+ 0xB8A5, 0xB978, 0xB8A6, 0xB97C, 0xB8A7, 0xB984, 0xB8A8, 0xB985, 0xB8A9, 0xB987, 0xB8AA, 0xB989, 0xB8AB, 0xB98A, 0xB8AC, 0xB98D,
+ 0xB8AD, 0xB98E, 0xB8AE, 0xB9AC, 0xB8AF, 0xB9AD, 0xB8B0, 0xB9B0, 0xB8B1, 0xB9B4, 0xB8B2, 0xB9BC, 0xB8B3, 0xB9BD, 0xB8B4, 0xB9BF,
+ 0xB8B5, 0xB9C1, 0xB8B6, 0xB9C8, 0xB8B7, 0xB9C9, 0xB8B8, 0xB9CC, 0xB8B9, 0xB9CE, 0xB8BA, 0xB9CF, 0xB8BB, 0xB9D0, 0xB8BC, 0xB9D1,
+ 0xB8BD, 0xB9D2, 0xB8BE, 0xB9D8, 0xB8BF, 0xB9D9, 0xB8C0, 0xB9DB, 0xB8C1, 0xB9DD, 0xB8C2, 0xB9DE, 0xB8C3, 0xB9E1, 0xB8C4, 0xB9E3,
+ 0xB8C5, 0xB9E4, 0xB8C6, 0xB9E5, 0xB8C7, 0xB9E8, 0xB8C8, 0xB9EC, 0xB8C9, 0xB9F4, 0xB8CA, 0xB9F5, 0xB8CB, 0xB9F7, 0xB8CC, 0xB9F8,
+ 0xB8CD, 0xB9F9, 0xB8CE, 0xB9FA, 0xB8CF, 0xBA00, 0xB8D0, 0xBA01, 0xB8D1, 0xBA08, 0xB8D2, 0xBA15, 0xB8D3, 0xBA38, 0xB8D4, 0xBA39,
+ 0xB8D5, 0xBA3C, 0xB8D6, 0xBA40, 0xB8D7, 0xBA42, 0xB8D8, 0xBA48, 0xB8D9, 0xBA49, 0xB8DA, 0xBA4B, 0xB8DB, 0xBA4D, 0xB8DC, 0xBA4E,
+ 0xB8DD, 0xBA53, 0xB8DE, 0xBA54, 0xB8DF, 0xBA55, 0xB8E0, 0xBA58, 0xB8E1, 0xBA5C, 0xB8E2, 0xBA64, 0xB8E3, 0xBA65, 0xB8E4, 0xBA67,
+ 0xB8E5, 0xBA68, 0xB8E6, 0xBA69, 0xB8E7, 0xBA70, 0xB8E8, 0xBA71, 0xB8E9, 0xBA74, 0xB8EA, 0xBA78, 0xB8EB, 0xBA83, 0xB8EC, 0xBA84,
+ 0xB8ED, 0xBA85, 0xB8EE, 0xBA87, 0xB8EF, 0xBA8C, 0xB8F0, 0xBAA8, 0xB8F1, 0xBAA9, 0xB8F2, 0xBAAB, 0xB8F3, 0xBAAC, 0xB8F4, 0xBAB0,
+ 0xB8F5, 0xBAB2, 0xB8F6, 0xBAB8, 0xB8F7, 0xBAB9, 0xB8F8, 0xBABB, 0xB8F9, 0xBABD, 0xB8FA, 0xBAC4, 0xB8FB, 0xBAC8, 0xB8FC, 0xBAD8,
+ 0xB8FD, 0xBAD9, 0xB8FE, 0xBAFC, 0xB941, 0xD22A, 0xB942, 0xD22B, 0xB943, 0xD22E, 0xB944, 0xD22F, 0xB945, 0xD231, 0xB946, 0xD232,
+ 0xB947, 0xD233, 0xB948, 0xD235, 0xB949, 0xD236, 0xB94A, 0xD237, 0xB94B, 0xD238, 0xB94C, 0xD239, 0xB94D, 0xD23A, 0xB94E, 0xD23B,
+ 0xB94F, 0xD23E, 0xB950, 0xD240, 0xB951, 0xD242, 0xB952, 0xD243, 0xB953, 0xD244, 0xB954, 0xD245, 0xB955, 0xD246, 0xB956, 0xD247,
+ 0xB957, 0xD249, 0xB958, 0xD24A, 0xB959, 0xD24B, 0xB95A, 0xD24C, 0xB961, 0xD24D, 0xB962, 0xD24E, 0xB963, 0xD24F, 0xB964, 0xD250,
+ 0xB965, 0xD251, 0xB966, 0xD252, 0xB967, 0xD253, 0xB968, 0xD254, 0xB969, 0xD255, 0xB96A, 0xD256, 0xB96B, 0xD257, 0xB96C, 0xD258,
+ 0xB96D, 0xD259, 0xB96E, 0xD25A, 0xB96F, 0xD25B, 0xB970, 0xD25D, 0xB971, 0xD25E, 0xB972, 0xD25F, 0xB973, 0xD260, 0xB974, 0xD261,
+ 0xB975, 0xD262, 0xB976, 0xD263, 0xB977, 0xD265, 0xB978, 0xD266, 0xB979, 0xD267, 0xB97A, 0xD268, 0xB981, 0xD269, 0xB982, 0xD26A,
+ 0xB983, 0xD26B, 0xB984, 0xD26C, 0xB985, 0xD26D, 0xB986, 0xD26E, 0xB987, 0xD26F, 0xB988, 0xD270, 0xB989, 0xD271, 0xB98A, 0xD272,
+ 0xB98B, 0xD273, 0xB98C, 0xD274, 0xB98D, 0xD275, 0xB98E, 0xD276, 0xB98F, 0xD277, 0xB990, 0xD278, 0xB991, 0xD279, 0xB992, 0xD27A,
+ 0xB993, 0xD27B, 0xB994, 0xD27C, 0xB995, 0xD27D, 0xB996, 0xD27E, 0xB997, 0xD27F, 0xB998, 0xD282, 0xB999, 0xD283, 0xB99A, 0xD285,
+ 0xB99B, 0xD286, 0xB99C, 0xD287, 0xB99D, 0xD289, 0xB99E, 0xD28A, 0xB99F, 0xD28B, 0xB9A0, 0xD28C, 0xB9A1, 0xBB00, 0xB9A2, 0xBB04,
+ 0xB9A3, 0xBB0D, 0xB9A4, 0xBB0F, 0xB9A5, 0xBB11, 0xB9A6, 0xBB18, 0xB9A7, 0xBB1C, 0xB9A8, 0xBB20, 0xB9A9, 0xBB29, 0xB9AA, 0xBB2B,
+ 0xB9AB, 0xBB34, 0xB9AC, 0xBB35, 0xB9AD, 0xBB36, 0xB9AE, 0xBB38, 0xB9AF, 0xBB3B, 0xB9B0, 0xBB3C, 0xB9B1, 0xBB3D, 0xB9B2, 0xBB3E,
+ 0xB9B3, 0xBB44, 0xB9B4, 0xBB45, 0xB9B5, 0xBB47, 0xB9B6, 0xBB49, 0xB9B7, 0xBB4D, 0xB9B8, 0xBB4F, 0xB9B9, 0xBB50, 0xB9BA, 0xBB54,
+ 0xB9BB, 0xBB58, 0xB9BC, 0xBB61, 0xB9BD, 0xBB63, 0xB9BE, 0xBB6C, 0xB9BF, 0xBB88, 0xB9C0, 0xBB8C, 0xB9C1, 0xBB90, 0xB9C2, 0xBBA4,
+ 0xB9C3, 0xBBA8, 0xB9C4, 0xBBAC, 0xB9C5, 0xBBB4, 0xB9C6, 0xBBB7, 0xB9C7, 0xBBC0, 0xB9C8, 0xBBC4, 0xB9C9, 0xBBC8, 0xB9CA, 0xBBD0,
+ 0xB9CB, 0xBBD3, 0xB9CC, 0xBBF8, 0xB9CD, 0xBBF9, 0xB9CE, 0xBBFC, 0xB9CF, 0xBBFF, 0xB9D0, 0xBC00, 0xB9D1, 0xBC02, 0xB9D2, 0xBC08,
+ 0xB9D3, 0xBC09, 0xB9D4, 0xBC0B, 0xB9D5, 0xBC0C, 0xB9D6, 0xBC0D, 0xB9D7, 0xBC0F, 0xB9D8, 0xBC11, 0xB9D9, 0xBC14, 0xB9DA, 0xBC15,
+ 0xB9DB, 0xBC16, 0xB9DC, 0xBC17, 0xB9DD, 0xBC18, 0xB9DE, 0xBC1B, 0xB9DF, 0xBC1C, 0xB9E0, 0xBC1D, 0xB9E1, 0xBC1E, 0xB9E2, 0xBC1F,
+ 0xB9E3, 0xBC24, 0xB9E4, 0xBC25, 0xB9E5, 0xBC27, 0xB9E6, 0xBC29, 0xB9E7, 0xBC2D, 0xB9E8, 0xBC30, 0xB9E9, 0xBC31, 0xB9EA, 0xBC34,
+ 0xB9EB, 0xBC38, 0xB9EC, 0xBC40, 0xB9ED, 0xBC41, 0xB9EE, 0xBC43, 0xB9EF, 0xBC44, 0xB9F0, 0xBC45, 0xB9F1, 0xBC49, 0xB9F2, 0xBC4C,
+ 0xB9F3, 0xBC4D, 0xB9F4, 0xBC50, 0xB9F5, 0xBC5D, 0xB9F6, 0xBC84, 0xB9F7, 0xBC85, 0xB9F8, 0xBC88, 0xB9F9, 0xBC8B, 0xB9FA, 0xBC8C,
+ 0xB9FB, 0xBC8E, 0xB9FC, 0xBC94, 0xB9FD, 0xBC95, 0xB9FE, 0xBC97, 0xBA41, 0xD28D, 0xBA42, 0xD28E, 0xBA43, 0xD28F, 0xBA44, 0xD292,
+ 0xBA45, 0xD293, 0xBA46, 0xD294, 0xBA47, 0xD296, 0xBA48, 0xD297, 0xBA49, 0xD298, 0xBA4A, 0xD299, 0xBA4B, 0xD29A, 0xBA4C, 0xD29B,
+ 0xBA4D, 0xD29D, 0xBA4E, 0xD29E, 0xBA4F, 0xD29F, 0xBA50, 0xD2A1, 0xBA51, 0xD2A2, 0xBA52, 0xD2A3, 0xBA53, 0xD2A5, 0xBA54, 0xD2A6,
+ 0xBA55, 0xD2A7, 0xBA56, 0xD2A8, 0xBA57, 0xD2A9, 0xBA58, 0xD2AA, 0xBA59, 0xD2AB, 0xBA5A, 0xD2AD, 0xBA61, 0xD2AE, 0xBA62, 0xD2AF,
+ 0xBA63, 0xD2B0, 0xBA64, 0xD2B2, 0xBA65, 0xD2B3, 0xBA66, 0xD2B4, 0xBA67, 0xD2B5, 0xBA68, 0xD2B6, 0xBA69, 0xD2B7, 0xBA6A, 0xD2BA,
+ 0xBA6B, 0xD2BB, 0xBA6C, 0xD2BD, 0xBA6D, 0xD2BE, 0xBA6E, 0xD2C1, 0xBA6F, 0xD2C3, 0xBA70, 0xD2C4, 0xBA71, 0xD2C5, 0xBA72, 0xD2C6,
+ 0xBA73, 0xD2C7, 0xBA74, 0xD2CA, 0xBA75, 0xD2CC, 0xBA76, 0xD2CD, 0xBA77, 0xD2CE, 0xBA78, 0xD2CF, 0xBA79, 0xD2D0, 0xBA7A, 0xD2D1,
+ 0xBA81, 0xD2D2, 0xBA82, 0xD2D3, 0xBA83, 0xD2D5, 0xBA84, 0xD2D6, 0xBA85, 0xD2D7, 0xBA86, 0xD2D9, 0xBA87, 0xD2DA, 0xBA88, 0xD2DB,
+ 0xBA89, 0xD2DD, 0xBA8A, 0xD2DE, 0xBA8B, 0xD2DF, 0xBA8C, 0xD2E0, 0xBA8D, 0xD2E1, 0xBA8E, 0xD2E2, 0xBA8F, 0xD2E3, 0xBA90, 0xD2E6,
+ 0xBA91, 0xD2E7, 0xBA92, 0xD2E8, 0xBA93, 0xD2E9, 0xBA94, 0xD2EA, 0xBA95, 0xD2EB, 0xBA96, 0xD2EC, 0xBA97, 0xD2ED, 0xBA98, 0xD2EE,
+ 0xBA99, 0xD2EF, 0xBA9A, 0xD2F2, 0xBA9B, 0xD2F3, 0xBA9C, 0xD2F5, 0xBA9D, 0xD2F6, 0xBA9E, 0xD2F7, 0xBA9F, 0xD2F9, 0xBAA0, 0xD2FA,
+ 0xBAA1, 0xBC99, 0xBAA2, 0xBC9A, 0xBAA3, 0xBCA0, 0xBAA4, 0xBCA1, 0xBAA5, 0xBCA4, 0xBAA6, 0xBCA7, 0xBAA7, 0xBCA8, 0xBAA8, 0xBCB0,
+ 0xBAA9, 0xBCB1, 0xBAAA, 0xBCB3, 0xBAAB, 0xBCB4, 0xBAAC, 0xBCB5, 0xBAAD, 0xBCBC, 0xBAAE, 0xBCBD, 0xBAAF, 0xBCC0, 0xBAB0, 0xBCC4,
+ 0xBAB1, 0xBCCD, 0xBAB2, 0xBCCF, 0xBAB3, 0xBCD0, 0xBAB4, 0xBCD1, 0xBAB5, 0xBCD5, 0xBAB6, 0xBCD8, 0xBAB7, 0xBCDC, 0xBAB8, 0xBCF4,
+ 0xBAB9, 0xBCF5, 0xBABA, 0xBCF6, 0xBABB, 0xBCF8, 0xBABC, 0xBCFC, 0xBABD, 0xBD04, 0xBABE, 0xBD05, 0xBABF, 0xBD07, 0xBAC0, 0xBD09,
+ 0xBAC1, 0xBD10, 0xBAC2, 0xBD14, 0xBAC3, 0xBD24, 0xBAC4, 0xBD2C, 0xBAC5, 0xBD40, 0xBAC6, 0xBD48, 0xBAC7, 0xBD49, 0xBAC8, 0xBD4C,
+ 0xBAC9, 0xBD50, 0xBACA, 0xBD58, 0xBACB, 0xBD59, 0xBACC, 0xBD64, 0xBACD, 0xBD68, 0xBACE, 0xBD80, 0xBACF, 0xBD81, 0xBAD0, 0xBD84,
+ 0xBAD1, 0xBD87, 0xBAD2, 0xBD88, 0xBAD3, 0xBD89, 0xBAD4, 0xBD8A, 0xBAD5, 0xBD90, 0xBAD6, 0xBD91, 0xBAD7, 0xBD93, 0xBAD8, 0xBD95,
+ 0xBAD9, 0xBD99, 0xBADA, 0xBD9A, 0xBADB, 0xBD9C, 0xBADC, 0xBDA4, 0xBADD, 0xBDB0, 0xBADE, 0xBDB8, 0xBADF, 0xBDD4, 0xBAE0, 0xBDD5,
+ 0xBAE1, 0xBDD8, 0xBAE2, 0xBDDC, 0xBAE3, 0xBDE9, 0xBAE4, 0xBDF0, 0xBAE5, 0xBDF4, 0xBAE6, 0xBDF8, 0xBAE7, 0xBE00, 0xBAE8, 0xBE03,
+ 0xBAE9, 0xBE05, 0xBAEA, 0xBE0C, 0xBAEB, 0xBE0D, 0xBAEC, 0xBE10, 0xBAED, 0xBE14, 0xBAEE, 0xBE1C, 0xBAEF, 0xBE1D, 0xBAF0, 0xBE1F,
+ 0xBAF1, 0xBE44, 0xBAF2, 0xBE45, 0xBAF3, 0xBE48, 0xBAF4, 0xBE4C, 0xBAF5, 0xBE4E, 0xBAF6, 0xBE54, 0xBAF7, 0xBE55, 0xBAF8, 0xBE57,
+ 0xBAF9, 0xBE59, 0xBAFA, 0xBE5A, 0xBAFB, 0xBE5B, 0xBAFC, 0xBE60, 0xBAFD, 0xBE61, 0xBAFE, 0xBE64, 0xBB41, 0xD2FB, 0xBB42, 0xD2FC,
+ 0xBB43, 0xD2FD, 0xBB44, 0xD2FE, 0xBB45, 0xD2FF, 0xBB46, 0xD302, 0xBB47, 0xD304, 0xBB48, 0xD306, 0xBB49, 0xD307, 0xBB4A, 0xD308,
+ 0xBB4B, 0xD309, 0xBB4C, 0xD30A, 0xBB4D, 0xD30B, 0xBB4E, 0xD30F, 0xBB4F, 0xD311, 0xBB50, 0xD312, 0xBB51, 0xD313, 0xBB52, 0xD315,
+ 0xBB53, 0xD317, 0xBB54, 0xD318, 0xBB55, 0xD319, 0xBB56, 0xD31A, 0xBB57, 0xD31B, 0xBB58, 0xD31E, 0xBB59, 0xD322, 0xBB5A, 0xD323,
+ 0xBB61, 0xD324, 0xBB62, 0xD326, 0xBB63, 0xD327, 0xBB64, 0xD32A, 0xBB65, 0xD32B, 0xBB66, 0xD32D, 0xBB67, 0xD32E, 0xBB68, 0xD32F,
+ 0xBB69, 0xD331, 0xBB6A, 0xD332, 0xBB6B, 0xD333, 0xBB6C, 0xD334, 0xBB6D, 0xD335, 0xBB6E, 0xD336, 0xBB6F, 0xD337, 0xBB70, 0xD33A,
+ 0xBB71, 0xD33E, 0xBB72, 0xD33F, 0xBB73, 0xD340, 0xBB74, 0xD341, 0xBB75, 0xD342, 0xBB76, 0xD343, 0xBB77, 0xD346, 0xBB78, 0xD347,
+ 0xBB79, 0xD348, 0xBB7A, 0xD349, 0xBB81, 0xD34A, 0xBB82, 0xD34B, 0xBB83, 0xD34C, 0xBB84, 0xD34D, 0xBB85, 0xD34E, 0xBB86, 0xD34F,
+ 0xBB87, 0xD350, 0xBB88, 0xD351, 0xBB89, 0xD352, 0xBB8A, 0xD353, 0xBB8B, 0xD354, 0xBB8C, 0xD355, 0xBB8D, 0xD356, 0xBB8E, 0xD357,
+ 0xBB8F, 0xD358, 0xBB90, 0xD359, 0xBB91, 0xD35A, 0xBB92, 0xD35B, 0xBB93, 0xD35C, 0xBB94, 0xD35D, 0xBB95, 0xD35E, 0xBB96, 0xD35F,
+ 0xBB97, 0xD360, 0xBB98, 0xD361, 0xBB99, 0xD362, 0xBB9A, 0xD363, 0xBB9B, 0xD364, 0xBB9C, 0xD365, 0xBB9D, 0xD366, 0xBB9E, 0xD367,
+ 0xBB9F, 0xD368, 0xBBA0, 0xD369, 0xBBA1, 0xBE68, 0xBBA2, 0xBE6A, 0xBBA3, 0xBE70, 0xBBA4, 0xBE71, 0xBBA5, 0xBE73, 0xBBA6, 0xBE74,
+ 0xBBA7, 0xBE75, 0xBBA8, 0xBE7B, 0xBBA9, 0xBE7C, 0xBBAA, 0xBE7D, 0xBBAB, 0xBE80, 0xBBAC, 0xBE84, 0xBBAD, 0xBE8C, 0xBBAE, 0xBE8D,
+ 0xBBAF, 0xBE8F, 0xBBB0, 0xBE90, 0xBBB1, 0xBE91, 0xBBB2, 0xBE98, 0xBBB3, 0xBE99, 0xBBB4, 0xBEA8, 0xBBB5, 0xBED0, 0xBBB6, 0xBED1,
+ 0xBBB7, 0xBED4, 0xBBB8, 0xBED7, 0xBBB9, 0xBED8, 0xBBBA, 0xBEE0, 0xBBBB, 0xBEE3, 0xBBBC, 0xBEE4, 0xBBBD, 0xBEE5, 0xBBBE, 0xBEEC,
+ 0xBBBF, 0xBF01, 0xBBC0, 0xBF08, 0xBBC1, 0xBF09, 0xBBC2, 0xBF18, 0xBBC3, 0xBF19, 0xBBC4, 0xBF1B, 0xBBC5, 0xBF1C, 0xBBC6, 0xBF1D,
+ 0xBBC7, 0xBF40, 0xBBC8, 0xBF41, 0xBBC9, 0xBF44, 0xBBCA, 0xBF48, 0xBBCB, 0xBF50, 0xBBCC, 0xBF51, 0xBBCD, 0xBF55, 0xBBCE, 0xBF94,
+ 0xBBCF, 0xBFB0, 0xBBD0, 0xBFC5, 0xBBD1, 0xBFCC, 0xBBD2, 0xBFCD, 0xBBD3, 0xBFD0, 0xBBD4, 0xBFD4, 0xBBD5, 0xBFDC, 0xBBD6, 0xBFDF,
+ 0xBBD7, 0xBFE1, 0xBBD8, 0xC03C, 0xBBD9, 0xC051, 0xBBDA, 0xC058, 0xBBDB, 0xC05C, 0xBBDC, 0xC060, 0xBBDD, 0xC068, 0xBBDE, 0xC069,
+ 0xBBDF, 0xC090, 0xBBE0, 0xC091, 0xBBE1, 0xC094, 0xBBE2, 0xC098, 0xBBE3, 0xC0A0, 0xBBE4, 0xC0A1, 0xBBE5, 0xC0A3, 0xBBE6, 0xC0A5,
+ 0xBBE7, 0xC0AC, 0xBBE8, 0xC0AD, 0xBBE9, 0xC0AF, 0xBBEA, 0xC0B0, 0xBBEB, 0xC0B3, 0xBBEC, 0xC0B4, 0xBBED, 0xC0B5, 0xBBEE, 0xC0B6,
+ 0xBBEF, 0xC0BC, 0xBBF0, 0xC0BD, 0xBBF1, 0xC0BF, 0xBBF2, 0xC0C0, 0xBBF3, 0xC0C1, 0xBBF4, 0xC0C5, 0xBBF5, 0xC0C8, 0xBBF6, 0xC0C9,
+ 0xBBF7, 0xC0CC, 0xBBF8, 0xC0D0, 0xBBF9, 0xC0D8, 0xBBFA, 0xC0D9, 0xBBFB, 0xC0DB, 0xBBFC, 0xC0DC, 0xBBFD, 0xC0DD, 0xBBFE, 0xC0E4,
+ 0xBC41, 0xD36A, 0xBC42, 0xD36B, 0xBC43, 0xD36C, 0xBC44, 0xD36D, 0xBC45, 0xD36E, 0xBC46, 0xD36F, 0xBC47, 0xD370, 0xBC48, 0xD371,
+ 0xBC49, 0xD372, 0xBC4A, 0xD373, 0xBC4B, 0xD374, 0xBC4C, 0xD375, 0xBC4D, 0xD376, 0xBC4E, 0xD377, 0xBC4F, 0xD378, 0xBC50, 0xD379,
+ 0xBC51, 0xD37A, 0xBC52, 0xD37B, 0xBC53, 0xD37E, 0xBC54, 0xD37F, 0xBC55, 0xD381, 0xBC56, 0xD382, 0xBC57, 0xD383, 0xBC58, 0xD385,
+ 0xBC59, 0xD386, 0xBC5A, 0xD387, 0xBC61, 0xD388, 0xBC62, 0xD389, 0xBC63, 0xD38A, 0xBC64, 0xD38B, 0xBC65, 0xD38E, 0xBC66, 0xD392,
+ 0xBC67, 0xD393, 0xBC68, 0xD394, 0xBC69, 0xD395, 0xBC6A, 0xD396, 0xBC6B, 0xD397, 0xBC6C, 0xD39A, 0xBC6D, 0xD39B, 0xBC6E, 0xD39D,
+ 0xBC6F, 0xD39E, 0xBC70, 0xD39F, 0xBC71, 0xD3A1, 0xBC72, 0xD3A2, 0xBC73, 0xD3A3, 0xBC74, 0xD3A4, 0xBC75, 0xD3A5, 0xBC76, 0xD3A6,
+ 0xBC77, 0xD3A7, 0xBC78, 0xD3AA, 0xBC79, 0xD3AC, 0xBC7A, 0xD3AE, 0xBC81, 0xD3AF, 0xBC82, 0xD3B0, 0xBC83, 0xD3B1, 0xBC84, 0xD3B2,
+ 0xBC85, 0xD3B3, 0xBC86, 0xD3B5, 0xBC87, 0xD3B6, 0xBC88, 0xD3B7, 0xBC89, 0xD3B9, 0xBC8A, 0xD3BA, 0xBC8B, 0xD3BB, 0xBC8C, 0xD3BD,
+ 0xBC8D, 0xD3BE, 0xBC8E, 0xD3BF, 0xBC8F, 0xD3C0, 0xBC90, 0xD3C1, 0xBC91, 0xD3C2, 0xBC92, 0xD3C3, 0xBC93, 0xD3C6, 0xBC94, 0xD3C7,
+ 0xBC95, 0xD3CA, 0xBC96, 0xD3CB, 0xBC97, 0xD3CC, 0xBC98, 0xD3CD, 0xBC99, 0xD3CE, 0xBC9A, 0xD3CF, 0xBC9B, 0xD3D1, 0xBC9C, 0xD3D2,
+ 0xBC9D, 0xD3D3, 0xBC9E, 0xD3D4, 0xBC9F, 0xD3D5, 0xBCA0, 0xD3D6, 0xBCA1, 0xC0E5, 0xBCA2, 0xC0E8, 0xBCA3, 0xC0EC, 0xBCA4, 0xC0F4,
+ 0xBCA5, 0xC0F5, 0xBCA6, 0xC0F7, 0xBCA7, 0xC0F9, 0xBCA8, 0xC100, 0xBCA9, 0xC104, 0xBCAA, 0xC108, 0xBCAB, 0xC110, 0xBCAC, 0xC115,
+ 0xBCAD, 0xC11C, 0xBCAE, 0xC11D, 0xBCAF, 0xC11E, 0xBCB0, 0xC11F, 0xBCB1, 0xC120, 0xBCB2, 0xC123, 0xBCB3, 0xC124, 0xBCB4, 0xC126,
+ 0xBCB5, 0xC127, 0xBCB6, 0xC12C, 0xBCB7, 0xC12D, 0xBCB8, 0xC12F, 0xBCB9, 0xC130, 0xBCBA, 0xC131, 0xBCBB, 0xC136, 0xBCBC, 0xC138,
+ 0xBCBD, 0xC139, 0xBCBE, 0xC13C, 0xBCBF, 0xC140, 0xBCC0, 0xC148, 0xBCC1, 0xC149, 0xBCC2, 0xC14B, 0xBCC3, 0xC14C, 0xBCC4, 0xC14D,
+ 0xBCC5, 0xC154, 0xBCC6, 0xC155, 0xBCC7, 0xC158, 0xBCC8, 0xC15C, 0xBCC9, 0xC164, 0xBCCA, 0xC165, 0xBCCB, 0xC167, 0xBCCC, 0xC168,
+ 0xBCCD, 0xC169, 0xBCCE, 0xC170, 0xBCCF, 0xC174, 0xBCD0, 0xC178, 0xBCD1, 0xC185, 0xBCD2, 0xC18C, 0xBCD3, 0xC18D, 0xBCD4, 0xC18E,
+ 0xBCD5, 0xC190, 0xBCD6, 0xC194, 0xBCD7, 0xC196, 0xBCD8, 0xC19C, 0xBCD9, 0xC19D, 0xBCDA, 0xC19F, 0xBCDB, 0xC1A1, 0xBCDC, 0xC1A5,
+ 0xBCDD, 0xC1A8, 0xBCDE, 0xC1A9, 0xBCDF, 0xC1AC, 0xBCE0, 0xC1B0, 0xBCE1, 0xC1BD, 0xBCE2, 0xC1C4, 0xBCE3, 0xC1C8, 0xBCE4, 0xC1CC,
+ 0xBCE5, 0xC1D4, 0xBCE6, 0xC1D7, 0xBCE7, 0xC1D8, 0xBCE8, 0xC1E0, 0xBCE9, 0xC1E4, 0xBCEA, 0xC1E8, 0xBCEB, 0xC1F0, 0xBCEC, 0xC1F1,
+ 0xBCED, 0xC1F3, 0xBCEE, 0xC1FC, 0xBCEF, 0xC1FD, 0xBCF0, 0xC200, 0xBCF1, 0xC204, 0xBCF2, 0xC20C, 0xBCF3, 0xC20D, 0xBCF4, 0xC20F,
+ 0xBCF5, 0xC211, 0xBCF6, 0xC218, 0xBCF7, 0xC219, 0xBCF8, 0xC21C, 0xBCF9, 0xC21F, 0xBCFA, 0xC220, 0xBCFB, 0xC228, 0xBCFC, 0xC229,
+ 0xBCFD, 0xC22B, 0xBCFE, 0xC22D, 0xBD41, 0xD3D7, 0xBD42, 0xD3D9, 0xBD43, 0xD3DA, 0xBD44, 0xD3DB, 0xBD45, 0xD3DC, 0xBD46, 0xD3DD,
+ 0xBD47, 0xD3DE, 0xBD48, 0xD3DF, 0xBD49, 0xD3E0, 0xBD4A, 0xD3E2, 0xBD4B, 0xD3E4, 0xBD4C, 0xD3E5, 0xBD4D, 0xD3E6, 0xBD4E, 0xD3E7,
+ 0xBD4F, 0xD3E8, 0xBD50, 0xD3E9, 0xBD51, 0xD3EA, 0xBD52, 0xD3EB, 0xBD53, 0xD3EE, 0xBD54, 0xD3EF, 0xBD55, 0xD3F1, 0xBD56, 0xD3F2,
+ 0xBD57, 0xD3F3, 0xBD58, 0xD3F5, 0xBD59, 0xD3F6, 0xBD5A, 0xD3F7, 0xBD61, 0xD3F8, 0xBD62, 0xD3F9, 0xBD63, 0xD3FA, 0xBD64, 0xD3FB,
+ 0xBD65, 0xD3FE, 0xBD66, 0xD400, 0xBD67, 0xD402, 0xBD68, 0xD403, 0xBD69, 0xD404, 0xBD6A, 0xD405, 0xBD6B, 0xD406, 0xBD6C, 0xD407,
+ 0xBD6D, 0xD409, 0xBD6E, 0xD40A, 0xBD6F, 0xD40B, 0xBD70, 0xD40C, 0xBD71, 0xD40D, 0xBD72, 0xD40E, 0xBD73, 0xD40F, 0xBD74, 0xD410,
+ 0xBD75, 0xD411, 0xBD76, 0xD412, 0xBD77, 0xD413, 0xBD78, 0xD414, 0xBD79, 0xD415, 0xBD7A, 0xD416, 0xBD81, 0xD417, 0xBD82, 0xD418,
+ 0xBD83, 0xD419, 0xBD84, 0xD41A, 0xBD85, 0xD41B, 0xBD86, 0xD41C, 0xBD87, 0xD41E, 0xBD88, 0xD41F, 0xBD89, 0xD420, 0xBD8A, 0xD421,
+ 0xBD8B, 0xD422, 0xBD8C, 0xD423, 0xBD8D, 0xD424, 0xBD8E, 0xD425, 0xBD8F, 0xD426, 0xBD90, 0xD427, 0xBD91, 0xD428, 0xBD92, 0xD429,
+ 0xBD93, 0xD42A, 0xBD94, 0xD42B, 0xBD95, 0xD42C, 0xBD96, 0xD42D, 0xBD97, 0xD42E, 0xBD98, 0xD42F, 0xBD99, 0xD430, 0xBD9A, 0xD431,
+ 0xBD9B, 0xD432, 0xBD9C, 0xD433, 0xBD9D, 0xD434, 0xBD9E, 0xD435, 0xBD9F, 0xD436, 0xBDA0, 0xD437, 0xBDA1, 0xC22F, 0xBDA2, 0xC231,
+ 0xBDA3, 0xC232, 0xBDA4, 0xC234, 0xBDA5, 0xC248, 0xBDA6, 0xC250, 0xBDA7, 0xC251, 0xBDA8, 0xC254, 0xBDA9, 0xC258, 0xBDAA, 0xC260,
+ 0xBDAB, 0xC265, 0xBDAC, 0xC26C, 0xBDAD, 0xC26D, 0xBDAE, 0xC270, 0xBDAF, 0xC274, 0xBDB0, 0xC27C, 0xBDB1, 0xC27D, 0xBDB2, 0xC27F,
+ 0xBDB3, 0xC281, 0xBDB4, 0xC288, 0xBDB5, 0xC289, 0xBDB6, 0xC290, 0xBDB7, 0xC298, 0xBDB8, 0xC29B, 0xBDB9, 0xC29D, 0xBDBA, 0xC2A4,
+ 0xBDBB, 0xC2A5, 0xBDBC, 0xC2A8, 0xBDBD, 0xC2AC, 0xBDBE, 0xC2AD, 0xBDBF, 0xC2B4, 0xBDC0, 0xC2B5, 0xBDC1, 0xC2B7, 0xBDC2, 0xC2B9,
+ 0xBDC3, 0xC2DC, 0xBDC4, 0xC2DD, 0xBDC5, 0xC2E0, 0xBDC6, 0xC2E3, 0xBDC7, 0xC2E4, 0xBDC8, 0xC2EB, 0xBDC9, 0xC2EC, 0xBDCA, 0xC2ED,
+ 0xBDCB, 0xC2EF, 0xBDCC, 0xC2F1, 0xBDCD, 0xC2F6, 0xBDCE, 0xC2F8, 0xBDCF, 0xC2F9, 0xBDD0, 0xC2FB, 0xBDD1, 0xC2FC, 0xBDD2, 0xC300,
+ 0xBDD3, 0xC308, 0xBDD4, 0xC309, 0xBDD5, 0xC30C, 0xBDD6, 0xC30D, 0xBDD7, 0xC313, 0xBDD8, 0xC314, 0xBDD9, 0xC315, 0xBDDA, 0xC318,
+ 0xBDDB, 0xC31C, 0xBDDC, 0xC324, 0xBDDD, 0xC325, 0xBDDE, 0xC328, 0xBDDF, 0xC329, 0xBDE0, 0xC345, 0xBDE1, 0xC368, 0xBDE2, 0xC369,
+ 0xBDE3, 0xC36C, 0xBDE4, 0xC370, 0xBDE5, 0xC372, 0xBDE6, 0xC378, 0xBDE7, 0xC379, 0xBDE8, 0xC37C, 0xBDE9, 0xC37D, 0xBDEA, 0xC384,
+ 0xBDEB, 0xC388, 0xBDEC, 0xC38C, 0xBDED, 0xC3C0, 0xBDEE, 0xC3D8, 0xBDEF, 0xC3D9, 0xBDF0, 0xC3DC, 0xBDF1, 0xC3DF, 0xBDF2, 0xC3E0,
+ 0xBDF3, 0xC3E2, 0xBDF4, 0xC3E8, 0xBDF5, 0xC3E9, 0xBDF6, 0xC3ED, 0xBDF7, 0xC3F4, 0xBDF8, 0xC3F5, 0xBDF9, 0xC3F8, 0xBDFA, 0xC408,
+ 0xBDFB, 0xC410, 0xBDFC, 0xC424, 0xBDFD, 0xC42C, 0xBDFE, 0xC430, 0xBE41, 0xD438, 0xBE42, 0xD439, 0xBE43, 0xD43A, 0xBE44, 0xD43B,
+ 0xBE45, 0xD43C, 0xBE46, 0xD43D, 0xBE47, 0xD43E, 0xBE48, 0xD43F, 0xBE49, 0xD441, 0xBE4A, 0xD442, 0xBE4B, 0xD443, 0xBE4C, 0xD445,
+ 0xBE4D, 0xD446, 0xBE4E, 0xD447, 0xBE4F, 0xD448, 0xBE50, 0xD449, 0xBE51, 0xD44A, 0xBE52, 0xD44B, 0xBE53, 0xD44C, 0xBE54, 0xD44D,
+ 0xBE55, 0xD44E, 0xBE56, 0xD44F, 0xBE57, 0xD450, 0xBE58, 0xD451, 0xBE59, 0xD452, 0xBE5A, 0xD453, 0xBE61, 0xD454, 0xBE62, 0xD455,
+ 0xBE63, 0xD456, 0xBE64, 0xD457, 0xBE65, 0xD458, 0xBE66, 0xD459, 0xBE67, 0xD45A, 0xBE68, 0xD45B, 0xBE69, 0xD45D, 0xBE6A, 0xD45E,
+ 0xBE6B, 0xD45F, 0xBE6C, 0xD461, 0xBE6D, 0xD462, 0xBE6E, 0xD463, 0xBE6F, 0xD465, 0xBE70, 0xD466, 0xBE71, 0xD467, 0xBE72, 0xD468,
+ 0xBE73, 0xD469, 0xBE74, 0xD46A, 0xBE75, 0xD46B, 0xBE76, 0xD46C, 0xBE77, 0xD46E, 0xBE78, 0xD470, 0xBE79, 0xD471, 0xBE7A, 0xD472,
+ 0xBE81, 0xD473, 0xBE82, 0xD474, 0xBE83, 0xD475, 0xBE84, 0xD476, 0xBE85, 0xD477, 0xBE86, 0xD47A, 0xBE87, 0xD47B, 0xBE88, 0xD47D,
+ 0xBE89, 0xD47E, 0xBE8A, 0xD481, 0xBE8B, 0xD483, 0xBE8C, 0xD484, 0xBE8D, 0xD485, 0xBE8E, 0xD486, 0xBE8F, 0xD487, 0xBE90, 0xD48A,
+ 0xBE91, 0xD48C, 0xBE92, 0xD48E, 0xBE93, 0xD48F, 0xBE94, 0xD490, 0xBE95, 0xD491, 0xBE96, 0xD492, 0xBE97, 0xD493, 0xBE98, 0xD495,
+ 0xBE99, 0xD496, 0xBE9A, 0xD497, 0xBE9B, 0xD498, 0xBE9C, 0xD499, 0xBE9D, 0xD49A, 0xBE9E, 0xD49B, 0xBE9F, 0xD49C, 0xBEA0, 0xD49D,
+ 0xBEA1, 0xC434, 0xBEA2, 0xC43C, 0xBEA3, 0xC43D, 0xBEA4, 0xC448, 0xBEA5, 0xC464, 0xBEA6, 0xC465, 0xBEA7, 0xC468, 0xBEA8, 0xC46C,
+ 0xBEA9, 0xC474, 0xBEAA, 0xC475, 0xBEAB, 0xC479, 0xBEAC, 0xC480, 0xBEAD, 0xC494, 0xBEAE, 0xC49C, 0xBEAF, 0xC4B8, 0xBEB0, 0xC4BC,
+ 0xBEB1, 0xC4E9, 0xBEB2, 0xC4F0, 0xBEB3, 0xC4F1, 0xBEB4, 0xC4F4, 0xBEB5, 0xC4F8, 0xBEB6, 0xC4FA, 0xBEB7, 0xC4FF, 0xBEB8, 0xC500,
+ 0xBEB9, 0xC501, 0xBEBA, 0xC50C, 0xBEBB, 0xC510, 0xBEBC, 0xC514, 0xBEBD, 0xC51C, 0xBEBE, 0xC528, 0xBEBF, 0xC529, 0xBEC0, 0xC52C,
+ 0xBEC1, 0xC530, 0xBEC2, 0xC538, 0xBEC3, 0xC539, 0xBEC4, 0xC53B, 0xBEC5, 0xC53D, 0xBEC6, 0xC544, 0xBEC7, 0xC545, 0xBEC8, 0xC548,
+ 0xBEC9, 0xC549, 0xBECA, 0xC54A, 0xBECB, 0xC54C, 0xBECC, 0xC54D, 0xBECD, 0xC54E, 0xBECE, 0xC553, 0xBECF, 0xC554, 0xBED0, 0xC555,
+ 0xBED1, 0xC557, 0xBED2, 0xC558, 0xBED3, 0xC559, 0xBED4, 0xC55D, 0xBED5, 0xC55E, 0xBED6, 0xC560, 0xBED7, 0xC561, 0xBED8, 0xC564,
+ 0xBED9, 0xC568, 0xBEDA, 0xC570, 0xBEDB, 0xC571, 0xBEDC, 0xC573, 0xBEDD, 0xC574, 0xBEDE, 0xC575, 0xBEDF, 0xC57C, 0xBEE0, 0xC57D,
+ 0xBEE1, 0xC580, 0xBEE2, 0xC584, 0xBEE3, 0xC587, 0xBEE4, 0xC58C, 0xBEE5, 0xC58D, 0xBEE6, 0xC58F, 0xBEE7, 0xC591, 0xBEE8, 0xC595,
+ 0xBEE9, 0xC597, 0xBEEA, 0xC598, 0xBEEB, 0xC59C, 0xBEEC, 0xC5A0, 0xBEED, 0xC5A9, 0xBEEE, 0xC5B4, 0xBEEF, 0xC5B5, 0xBEF0, 0xC5B8,
+ 0xBEF1, 0xC5B9, 0xBEF2, 0xC5BB, 0xBEF3, 0xC5BC, 0xBEF4, 0xC5BD, 0xBEF5, 0xC5BE, 0xBEF6, 0xC5C4, 0xBEF7, 0xC5C5, 0xBEF8, 0xC5C6,
+ 0xBEF9, 0xC5C7, 0xBEFA, 0xC5C8, 0xBEFB, 0xC5C9, 0xBEFC, 0xC5CA, 0xBEFD, 0xC5CC, 0xBEFE, 0xC5CE, 0xBF41, 0xD49E, 0xBF42, 0xD49F,
+ 0xBF43, 0xD4A0, 0xBF44, 0xD4A1, 0xBF45, 0xD4A2, 0xBF46, 0xD4A3, 0xBF47, 0xD4A4, 0xBF48, 0xD4A5, 0xBF49, 0xD4A6, 0xBF4A, 0xD4A7,
+ 0xBF4B, 0xD4A8, 0xBF4C, 0xD4AA, 0xBF4D, 0xD4AB, 0xBF4E, 0xD4AC, 0xBF4F, 0xD4AD, 0xBF50, 0xD4AE, 0xBF51, 0xD4AF, 0xBF52, 0xD4B0,
+ 0xBF53, 0xD4B1, 0xBF54, 0xD4B2, 0xBF55, 0xD4B3, 0xBF56, 0xD4B4, 0xBF57, 0xD4B5, 0xBF58, 0xD4B6, 0xBF59, 0xD4B7, 0xBF5A, 0xD4B8,
+ 0xBF61, 0xD4B9, 0xBF62, 0xD4BA, 0xBF63, 0xD4BB, 0xBF64, 0xD4BC, 0xBF65, 0xD4BD, 0xBF66, 0xD4BE, 0xBF67, 0xD4BF, 0xBF68, 0xD4C0,
+ 0xBF69, 0xD4C1, 0xBF6A, 0xD4C2, 0xBF6B, 0xD4C3, 0xBF6C, 0xD4C4, 0xBF6D, 0xD4C5, 0xBF6E, 0xD4C6, 0xBF6F, 0xD4C7, 0xBF70, 0xD4C8,
+ 0xBF71, 0xD4C9, 0xBF72, 0xD4CA, 0xBF73, 0xD4CB, 0xBF74, 0xD4CD, 0xBF75, 0xD4CE, 0xBF76, 0xD4CF, 0xBF77, 0xD4D1, 0xBF78, 0xD4D2,
+ 0xBF79, 0xD4D3, 0xBF7A, 0xD4D5, 0xBF81, 0xD4D6, 0xBF82, 0xD4D7, 0xBF83, 0xD4D8, 0xBF84, 0xD4D9, 0xBF85, 0xD4DA, 0xBF86, 0xD4DB,
+ 0xBF87, 0xD4DD, 0xBF88, 0xD4DE, 0xBF89, 0xD4E0, 0xBF8A, 0xD4E1, 0xBF8B, 0xD4E2, 0xBF8C, 0xD4E3, 0xBF8D, 0xD4E4, 0xBF8E, 0xD4E5,
+ 0xBF8F, 0xD4E6, 0xBF90, 0xD4E7, 0xBF91, 0xD4E9, 0xBF92, 0xD4EA, 0xBF93, 0xD4EB, 0xBF94, 0xD4ED, 0xBF95, 0xD4EE, 0xBF96, 0xD4EF,
+ 0xBF97, 0xD4F1, 0xBF98, 0xD4F2, 0xBF99, 0xD4F3, 0xBF9A, 0xD4F4, 0xBF9B, 0xD4F5, 0xBF9C, 0xD4F6, 0xBF9D, 0xD4F7, 0xBF9E, 0xD4F9,
+ 0xBF9F, 0xD4FA, 0xBFA0, 0xD4FC, 0xBFA1, 0xC5D0, 0xBFA2, 0xC5D1, 0xBFA3, 0xC5D4, 0xBFA4, 0xC5D8, 0xBFA5, 0xC5E0, 0xBFA6, 0xC5E1,
+ 0xBFA7, 0xC5E3, 0xBFA8, 0xC5E5, 0xBFA9, 0xC5EC, 0xBFAA, 0xC5ED, 0xBFAB, 0xC5EE, 0xBFAC, 0xC5F0, 0xBFAD, 0xC5F4, 0xBFAE, 0xC5F6,
+ 0xBFAF, 0xC5F7, 0xBFB0, 0xC5FC, 0xBFB1, 0xC5FD, 0xBFB2, 0xC5FE, 0xBFB3, 0xC5FF, 0xBFB4, 0xC600, 0xBFB5, 0xC601, 0xBFB6, 0xC605,
+ 0xBFB7, 0xC606, 0xBFB8, 0xC607, 0xBFB9, 0xC608, 0xBFBA, 0xC60C, 0xBFBB, 0xC610, 0xBFBC, 0xC618, 0xBFBD, 0xC619, 0xBFBE, 0xC61B,
+ 0xBFBF, 0xC61C, 0xBFC0, 0xC624, 0xBFC1, 0xC625, 0xBFC2, 0xC628, 0xBFC3, 0xC62C, 0xBFC4, 0xC62D, 0xBFC5, 0xC62E, 0xBFC6, 0xC630,
+ 0xBFC7, 0xC633, 0xBFC8, 0xC634, 0xBFC9, 0xC635, 0xBFCA, 0xC637, 0xBFCB, 0xC639, 0xBFCC, 0xC63B, 0xBFCD, 0xC640, 0xBFCE, 0xC641,
+ 0xBFCF, 0xC644, 0xBFD0, 0xC648, 0xBFD1, 0xC650, 0xBFD2, 0xC651, 0xBFD3, 0xC653, 0xBFD4, 0xC654, 0xBFD5, 0xC655, 0xBFD6, 0xC65C,
+ 0xBFD7, 0xC65D, 0xBFD8, 0xC660, 0xBFD9, 0xC66C, 0xBFDA, 0xC66F, 0xBFDB, 0xC671, 0xBFDC, 0xC678, 0xBFDD, 0xC679, 0xBFDE, 0xC67C,
+ 0xBFDF, 0xC680, 0xBFE0, 0xC688, 0xBFE1, 0xC689, 0xBFE2, 0xC68B, 0xBFE3, 0xC68D, 0xBFE4, 0xC694, 0xBFE5, 0xC695, 0xBFE6, 0xC698,
+ 0xBFE7, 0xC69C, 0xBFE8, 0xC6A4, 0xBFE9, 0xC6A5, 0xBFEA, 0xC6A7, 0xBFEB, 0xC6A9, 0xBFEC, 0xC6B0, 0xBFED, 0xC6B1, 0xBFEE, 0xC6B4,
+ 0xBFEF, 0xC6B8, 0xBFF0, 0xC6B9, 0xBFF1, 0xC6BA, 0xBFF2, 0xC6C0, 0xBFF3, 0xC6C1, 0xBFF4, 0xC6C3, 0xBFF5, 0xC6C5, 0xBFF6, 0xC6CC,
+ 0xBFF7, 0xC6CD, 0xBFF8, 0xC6D0, 0xBFF9, 0xC6D4, 0xBFFA, 0xC6DC, 0xBFFB, 0xC6DD, 0xBFFC, 0xC6E0, 0xBFFD, 0xC6E1, 0xBFFE, 0xC6E8,
+ 0xC041, 0xD4FE, 0xC042, 0xD4FF, 0xC043, 0xD500, 0xC044, 0xD501, 0xC045, 0xD502, 0xC046, 0xD503, 0xC047, 0xD505, 0xC048, 0xD506,
+ 0xC049, 0xD507, 0xC04A, 0xD509, 0xC04B, 0xD50A, 0xC04C, 0xD50B, 0xC04D, 0xD50D, 0xC04E, 0xD50E, 0xC04F, 0xD50F, 0xC050, 0xD510,
+ 0xC051, 0xD511, 0xC052, 0xD512, 0xC053, 0xD513, 0xC054, 0xD516, 0xC055, 0xD518, 0xC056, 0xD519, 0xC057, 0xD51A, 0xC058, 0xD51B,
+ 0xC059, 0xD51C, 0xC05A, 0xD51D, 0xC061, 0xD51E, 0xC062, 0xD51F, 0xC063, 0xD520, 0xC064, 0xD521, 0xC065, 0xD522, 0xC066, 0xD523,
+ 0xC067, 0xD524, 0xC068, 0xD525, 0xC069, 0xD526, 0xC06A, 0xD527, 0xC06B, 0xD528, 0xC06C, 0xD529, 0xC06D, 0xD52A, 0xC06E, 0xD52B,
+ 0xC06F, 0xD52C, 0xC070, 0xD52D, 0xC071, 0xD52E, 0xC072, 0xD52F, 0xC073, 0xD530, 0xC074, 0xD531, 0xC075, 0xD532, 0xC076, 0xD533,
+ 0xC077, 0xD534, 0xC078, 0xD535, 0xC079, 0xD536, 0xC07A, 0xD537, 0xC081, 0xD538, 0xC082, 0xD539, 0xC083, 0xD53A, 0xC084, 0xD53B,
+ 0xC085, 0xD53E, 0xC086, 0xD53F, 0xC087, 0xD541, 0xC088, 0xD542, 0xC089, 0xD543, 0xC08A, 0xD545, 0xC08B, 0xD546, 0xC08C, 0xD547,
+ 0xC08D, 0xD548, 0xC08E, 0xD549, 0xC08F, 0xD54A, 0xC090, 0xD54B, 0xC091, 0xD54E, 0xC092, 0xD550, 0xC093, 0xD552, 0xC094, 0xD553,
+ 0xC095, 0xD554, 0xC096, 0xD555, 0xC097, 0xD556, 0xC098, 0xD557, 0xC099, 0xD55A, 0xC09A, 0xD55B, 0xC09B, 0xD55D, 0xC09C, 0xD55E,
+ 0xC09D, 0xD55F, 0xC09E, 0xD561, 0xC09F, 0xD562, 0xC0A0, 0xD563, 0xC0A1, 0xC6E9, 0xC0A2, 0xC6EC, 0xC0A3, 0xC6F0, 0xC0A4, 0xC6F8,
+ 0xC0A5, 0xC6F9, 0xC0A6, 0xC6FD, 0xC0A7, 0xC704, 0xC0A8, 0xC705, 0xC0A9, 0xC708, 0xC0AA, 0xC70C, 0xC0AB, 0xC714, 0xC0AC, 0xC715,
+ 0xC0AD, 0xC717, 0xC0AE, 0xC719, 0xC0AF, 0xC720, 0xC0B0, 0xC721, 0xC0B1, 0xC724, 0xC0B2, 0xC728, 0xC0B3, 0xC730, 0xC0B4, 0xC731,
+ 0xC0B5, 0xC733, 0xC0B6, 0xC735, 0xC0B7, 0xC737, 0xC0B8, 0xC73C, 0xC0B9, 0xC73D, 0xC0BA, 0xC740, 0xC0BB, 0xC744, 0xC0BC, 0xC74A,
+ 0xC0BD, 0xC74C, 0xC0BE, 0xC74D, 0xC0BF, 0xC74F, 0xC0C0, 0xC751, 0xC0C1, 0xC752, 0xC0C2, 0xC753, 0xC0C3, 0xC754, 0xC0C4, 0xC755,
+ 0xC0C5, 0xC756, 0xC0C6, 0xC757, 0xC0C7, 0xC758, 0xC0C8, 0xC75C, 0xC0C9, 0xC760, 0xC0CA, 0xC768, 0xC0CB, 0xC76B, 0xC0CC, 0xC774,
+ 0xC0CD, 0xC775, 0xC0CE, 0xC778, 0xC0CF, 0xC77C, 0xC0D0, 0xC77D, 0xC0D1, 0xC77E, 0xC0D2, 0xC783, 0xC0D3, 0xC784, 0xC0D4, 0xC785,
+ 0xC0D5, 0xC787, 0xC0D6, 0xC788, 0xC0D7, 0xC789, 0xC0D8, 0xC78A, 0xC0D9, 0xC78E, 0xC0DA, 0xC790, 0xC0DB, 0xC791, 0xC0DC, 0xC794,
+ 0xC0DD, 0xC796, 0xC0DE, 0xC797, 0xC0DF, 0xC798, 0xC0E0, 0xC79A, 0xC0E1, 0xC7A0, 0xC0E2, 0xC7A1, 0xC0E3, 0xC7A3, 0xC0E4, 0xC7A4,
+ 0xC0E5, 0xC7A5, 0xC0E6, 0xC7A6, 0xC0E7, 0xC7AC, 0xC0E8, 0xC7AD, 0xC0E9, 0xC7B0, 0xC0EA, 0xC7B4, 0xC0EB, 0xC7BC, 0xC0EC, 0xC7BD,
+ 0xC0ED, 0xC7BF, 0xC0EE, 0xC7C0, 0xC0EF, 0xC7C1, 0xC0F0, 0xC7C8, 0xC0F1, 0xC7C9, 0xC0F2, 0xC7CC, 0xC0F3, 0xC7CE, 0xC0F4, 0xC7D0,
+ 0xC0F5, 0xC7D8, 0xC0F6, 0xC7DD, 0xC0F7, 0xC7E4, 0xC0F8, 0xC7E8, 0xC0F9, 0xC7EC, 0xC0FA, 0xC800, 0xC0FB, 0xC801, 0xC0FC, 0xC804,
+ 0xC0FD, 0xC808, 0xC0FE, 0xC80A, 0xC141, 0xD564, 0xC142, 0xD566, 0xC143, 0xD567, 0xC144, 0xD56A, 0xC145, 0xD56C, 0xC146, 0xD56E,
+ 0xC147, 0xD56F, 0xC148, 0xD570, 0xC149, 0xD571, 0xC14A, 0xD572, 0xC14B, 0xD573, 0xC14C, 0xD576, 0xC14D, 0xD577, 0xC14E, 0xD579,
+ 0xC14F, 0xD57A, 0xC150, 0xD57B, 0xC151, 0xD57D, 0xC152, 0xD57E, 0xC153, 0xD57F, 0xC154, 0xD580, 0xC155, 0xD581, 0xC156, 0xD582,
+ 0xC157, 0xD583, 0xC158, 0xD586, 0xC159, 0xD58A, 0xC15A, 0xD58B, 0xC161, 0xD58C, 0xC162, 0xD58D, 0xC163, 0xD58E, 0xC164, 0xD58F,
+ 0xC165, 0xD591, 0xC166, 0xD592, 0xC167, 0xD593, 0xC168, 0xD594, 0xC169, 0xD595, 0xC16A, 0xD596, 0xC16B, 0xD597, 0xC16C, 0xD598,
+ 0xC16D, 0xD599, 0xC16E, 0xD59A, 0xC16F, 0xD59B, 0xC170, 0xD59C, 0xC171, 0xD59D, 0xC172, 0xD59E, 0xC173, 0xD59F, 0xC174, 0xD5A0,
+ 0xC175, 0xD5A1, 0xC176, 0xD5A2, 0xC177, 0xD5A3, 0xC178, 0xD5A4, 0xC179, 0xD5A6, 0xC17A, 0xD5A7, 0xC181, 0xD5A8, 0xC182, 0xD5A9,
+ 0xC183, 0xD5AA, 0xC184, 0xD5AB, 0xC185, 0xD5AC, 0xC186, 0xD5AD, 0xC187, 0xD5AE, 0xC188, 0xD5AF, 0xC189, 0xD5B0, 0xC18A, 0xD5B1,
+ 0xC18B, 0xD5B2, 0xC18C, 0xD5B3, 0xC18D, 0xD5B4, 0xC18E, 0xD5B5, 0xC18F, 0xD5B6, 0xC190, 0xD5B7, 0xC191, 0xD5B8, 0xC192, 0xD5B9,
+ 0xC193, 0xD5BA, 0xC194, 0xD5BB, 0xC195, 0xD5BC, 0xC196, 0xD5BD, 0xC197, 0xD5BE, 0xC198, 0xD5BF, 0xC199, 0xD5C0, 0xC19A, 0xD5C1,
+ 0xC19B, 0xD5C2, 0xC19C, 0xD5C3, 0xC19D, 0xD5C4, 0xC19E, 0xD5C5, 0xC19F, 0xD5C6, 0xC1A0, 0xD5C7, 0xC1A1, 0xC810, 0xC1A2, 0xC811,
+ 0xC1A3, 0xC813, 0xC1A4, 0xC815, 0xC1A5, 0xC816, 0xC1A6, 0xC81C, 0xC1A7, 0xC81D, 0xC1A8, 0xC820, 0xC1A9, 0xC824, 0xC1AA, 0xC82C,
+ 0xC1AB, 0xC82D, 0xC1AC, 0xC82F, 0xC1AD, 0xC831, 0xC1AE, 0xC838, 0xC1AF, 0xC83C, 0xC1B0, 0xC840, 0xC1B1, 0xC848, 0xC1B2, 0xC849,
+ 0xC1B3, 0xC84C, 0xC1B4, 0xC84D, 0xC1B5, 0xC854, 0xC1B6, 0xC870, 0xC1B7, 0xC871, 0xC1B8, 0xC874, 0xC1B9, 0xC878, 0xC1BA, 0xC87A,
+ 0xC1BB, 0xC880, 0xC1BC, 0xC881, 0xC1BD, 0xC883, 0xC1BE, 0xC885, 0xC1BF, 0xC886, 0xC1C0, 0xC887, 0xC1C1, 0xC88B, 0xC1C2, 0xC88C,
+ 0xC1C3, 0xC88D, 0xC1C4, 0xC894, 0xC1C5, 0xC89D, 0xC1C6, 0xC89F, 0xC1C7, 0xC8A1, 0xC1C8, 0xC8A8, 0xC1C9, 0xC8BC, 0xC1CA, 0xC8BD,
+ 0xC1CB, 0xC8C4, 0xC1CC, 0xC8C8, 0xC1CD, 0xC8CC, 0xC1CE, 0xC8D4, 0xC1CF, 0xC8D5, 0xC1D0, 0xC8D7, 0xC1D1, 0xC8D9, 0xC1D2, 0xC8E0,
+ 0xC1D3, 0xC8E1, 0xC1D4, 0xC8E4, 0xC1D5, 0xC8F5, 0xC1D6, 0xC8FC, 0xC1D7, 0xC8FD, 0xC1D8, 0xC900, 0xC1D9, 0xC904, 0xC1DA, 0xC905,
+ 0xC1DB, 0xC906, 0xC1DC, 0xC90C, 0xC1DD, 0xC90D, 0xC1DE, 0xC90F, 0xC1DF, 0xC911, 0xC1E0, 0xC918, 0xC1E1, 0xC92C, 0xC1E2, 0xC934,
+ 0xC1E3, 0xC950, 0xC1E4, 0xC951, 0xC1E5, 0xC954, 0xC1E6, 0xC958, 0xC1E7, 0xC960, 0xC1E8, 0xC961, 0xC1E9, 0xC963, 0xC1EA, 0xC96C,
+ 0xC1EB, 0xC970, 0xC1EC, 0xC974, 0xC1ED, 0xC97C, 0xC1EE, 0xC988, 0xC1EF, 0xC989, 0xC1F0, 0xC98C, 0xC1F1, 0xC990, 0xC1F2, 0xC998,
+ 0xC1F3, 0xC999, 0xC1F4, 0xC99B, 0xC1F5, 0xC99D, 0xC1F6, 0xC9C0, 0xC1F7, 0xC9C1, 0xC1F8, 0xC9C4, 0xC1F9, 0xC9C7, 0xC1FA, 0xC9C8,
+ 0xC1FB, 0xC9CA, 0xC1FC, 0xC9D0, 0xC1FD, 0xC9D1, 0xC1FE, 0xC9D3, 0xC241, 0xD5CA, 0xC242, 0xD5CB, 0xC243, 0xD5CD, 0xC244, 0xD5CE,
+ 0xC245, 0xD5CF, 0xC246, 0xD5D1, 0xC247, 0xD5D3, 0xC248, 0xD5D4, 0xC249, 0xD5D5, 0xC24A, 0xD5D6, 0xC24B, 0xD5D7, 0xC24C, 0xD5DA,
+ 0xC24D, 0xD5DC, 0xC24E, 0xD5DE, 0xC24F, 0xD5DF, 0xC250, 0xD5E0, 0xC251, 0xD5E1, 0xC252, 0xD5E2, 0xC253, 0xD5E3, 0xC254, 0xD5E6,
+ 0xC255, 0xD5E7, 0xC256, 0xD5E9, 0xC257, 0xD5EA, 0xC258, 0xD5EB, 0xC259, 0xD5ED, 0xC25A, 0xD5EE, 0xC261, 0xD5EF, 0xC262, 0xD5F0,
+ 0xC263, 0xD5F1, 0xC264, 0xD5F2, 0xC265, 0xD5F3, 0xC266, 0xD5F6, 0xC267, 0xD5F8, 0xC268, 0xD5FA, 0xC269, 0xD5FB, 0xC26A, 0xD5FC,
+ 0xC26B, 0xD5FD, 0xC26C, 0xD5FE, 0xC26D, 0xD5FF, 0xC26E, 0xD602, 0xC26F, 0xD603, 0xC270, 0xD605, 0xC271, 0xD606, 0xC272, 0xD607,
+ 0xC273, 0xD609, 0xC274, 0xD60A, 0xC275, 0xD60B, 0xC276, 0xD60C, 0xC277, 0xD60D, 0xC278, 0xD60E, 0xC279, 0xD60F, 0xC27A, 0xD612,
+ 0xC281, 0xD616, 0xC282, 0xD617, 0xC283, 0xD618, 0xC284, 0xD619, 0xC285, 0xD61A, 0xC286, 0xD61B, 0xC287, 0xD61D, 0xC288, 0xD61E,
+ 0xC289, 0xD61F, 0xC28A, 0xD621, 0xC28B, 0xD622, 0xC28C, 0xD623, 0xC28D, 0xD625, 0xC28E, 0xD626, 0xC28F, 0xD627, 0xC290, 0xD628,
+ 0xC291, 0xD629, 0xC292, 0xD62A, 0xC293, 0xD62B, 0xC294, 0xD62C, 0xC295, 0xD62E, 0xC296, 0xD62F, 0xC297, 0xD630, 0xC298, 0xD631,
+ 0xC299, 0xD632, 0xC29A, 0xD633, 0xC29B, 0xD634, 0xC29C, 0xD635, 0xC29D, 0xD636, 0xC29E, 0xD637, 0xC29F, 0xD63A, 0xC2A0, 0xD63B,
+ 0xC2A1, 0xC9D5, 0xC2A2, 0xC9D6, 0xC2A3, 0xC9D9, 0xC2A4, 0xC9DA, 0xC2A5, 0xC9DC, 0xC2A6, 0xC9DD, 0xC2A7, 0xC9E0, 0xC2A8, 0xC9E2,
+ 0xC2A9, 0xC9E4, 0xC2AA, 0xC9E7, 0xC2AB, 0xC9EC, 0xC2AC, 0xC9ED, 0xC2AD, 0xC9EF, 0xC2AE, 0xC9F0, 0xC2AF, 0xC9F1, 0xC2B0, 0xC9F8,
+ 0xC2B1, 0xC9F9, 0xC2B2, 0xC9FC, 0xC2B3, 0xCA00, 0xC2B4, 0xCA08, 0xC2B5, 0xCA09, 0xC2B6, 0xCA0B, 0xC2B7, 0xCA0C, 0xC2B8, 0xCA0D,
+ 0xC2B9, 0xCA14, 0xC2BA, 0xCA18, 0xC2BB, 0xCA29, 0xC2BC, 0xCA4C, 0xC2BD, 0xCA4D, 0xC2BE, 0xCA50, 0xC2BF, 0xCA54, 0xC2C0, 0xCA5C,
+ 0xC2C1, 0xCA5D, 0xC2C2, 0xCA5F, 0xC2C3, 0xCA60, 0xC2C4, 0xCA61, 0xC2C5, 0xCA68, 0xC2C6, 0xCA7D, 0xC2C7, 0xCA84, 0xC2C8, 0xCA98,
+ 0xC2C9, 0xCABC, 0xC2CA, 0xCABD, 0xC2CB, 0xCAC0, 0xC2CC, 0xCAC4, 0xC2CD, 0xCACC, 0xC2CE, 0xCACD, 0xC2CF, 0xCACF, 0xC2D0, 0xCAD1,
+ 0xC2D1, 0xCAD3, 0xC2D2, 0xCAD8, 0xC2D3, 0xCAD9, 0xC2D4, 0xCAE0, 0xC2D5, 0xCAEC, 0xC2D6, 0xCAF4, 0xC2D7, 0xCB08, 0xC2D8, 0xCB10,
+ 0xC2D9, 0xCB14, 0xC2DA, 0xCB18, 0xC2DB, 0xCB20, 0xC2DC, 0xCB21, 0xC2DD, 0xCB41, 0xC2DE, 0xCB48, 0xC2DF, 0xCB49, 0xC2E0, 0xCB4C,
+ 0xC2E1, 0xCB50, 0xC2E2, 0xCB58, 0xC2E3, 0xCB59, 0xC2E4, 0xCB5D, 0xC2E5, 0xCB64, 0xC2E6, 0xCB78, 0xC2E7, 0xCB79, 0xC2E8, 0xCB9C,
+ 0xC2E9, 0xCBB8, 0xC2EA, 0xCBD4, 0xC2EB, 0xCBE4, 0xC2EC, 0xCBE7, 0xC2ED, 0xCBE9, 0xC2EE, 0xCC0C, 0xC2EF, 0xCC0D, 0xC2F0, 0xCC10,
+ 0xC2F1, 0xCC14, 0xC2F2, 0xCC1C, 0xC2F3, 0xCC1D, 0xC2F4, 0xCC21, 0xC2F5, 0xCC22, 0xC2F6, 0xCC27, 0xC2F7, 0xCC28, 0xC2F8, 0xCC29,
+ 0xC2F9, 0xCC2C, 0xC2FA, 0xCC2E, 0xC2FB, 0xCC30, 0xC2FC, 0xCC38, 0xC2FD, 0xCC39, 0xC2FE, 0xCC3B, 0xC341, 0xD63D, 0xC342, 0xD63E,
+ 0xC343, 0xD63F, 0xC344, 0xD641, 0xC345, 0xD642, 0xC346, 0xD643, 0xC347, 0xD644, 0xC348, 0xD646, 0xC349, 0xD647, 0xC34A, 0xD64A,
+ 0xC34B, 0xD64C, 0xC34C, 0xD64E, 0xC34D, 0xD64F, 0xC34E, 0xD650, 0xC34F, 0xD652, 0xC350, 0xD653, 0xC351, 0xD656, 0xC352, 0xD657,
+ 0xC353, 0xD659, 0xC354, 0xD65A, 0xC355, 0xD65B, 0xC356, 0xD65D, 0xC357, 0xD65E, 0xC358, 0xD65F, 0xC359, 0xD660, 0xC35A, 0xD661,
+ 0xC361, 0xD662, 0xC362, 0xD663, 0xC363, 0xD664, 0xC364, 0xD665, 0xC365, 0xD666, 0xC366, 0xD668, 0xC367, 0xD66A, 0xC368, 0xD66B,
+ 0xC369, 0xD66C, 0xC36A, 0xD66D, 0xC36B, 0xD66E, 0xC36C, 0xD66F, 0xC36D, 0xD672, 0xC36E, 0xD673, 0xC36F, 0xD675, 0xC370, 0xD676,
+ 0xC371, 0xD677, 0xC372, 0xD678, 0xC373, 0xD679, 0xC374, 0xD67A, 0xC375, 0xD67B, 0xC376, 0xD67C, 0xC377, 0xD67D, 0xC378, 0xD67E,
+ 0xC379, 0xD67F, 0xC37A, 0xD680, 0xC381, 0xD681, 0xC382, 0xD682, 0xC383, 0xD684, 0xC384, 0xD686, 0xC385, 0xD687, 0xC386, 0xD688,
+ 0xC387, 0xD689, 0xC388, 0xD68A, 0xC389, 0xD68B, 0xC38A, 0xD68E, 0xC38B, 0xD68F, 0xC38C, 0xD691, 0xC38D, 0xD692, 0xC38E, 0xD693,
+ 0xC38F, 0xD695, 0xC390, 0xD696, 0xC391, 0xD697, 0xC392, 0xD698, 0xC393, 0xD699, 0xC394, 0xD69A, 0xC395, 0xD69B, 0xC396, 0xD69C,
+ 0xC397, 0xD69E, 0xC398, 0xD6A0, 0xC399, 0xD6A2, 0xC39A, 0xD6A3, 0xC39B, 0xD6A4, 0xC39C, 0xD6A5, 0xC39D, 0xD6A6, 0xC39E, 0xD6A7,
+ 0xC39F, 0xD6A9, 0xC3A0, 0xD6AA, 0xC3A1, 0xCC3C, 0xC3A2, 0xCC3D, 0xC3A3, 0xCC3E, 0xC3A4, 0xCC44, 0xC3A5, 0xCC45, 0xC3A6, 0xCC48,
+ 0xC3A7, 0xCC4C, 0xC3A8, 0xCC54, 0xC3A9, 0xCC55, 0xC3AA, 0xCC57, 0xC3AB, 0xCC58, 0xC3AC, 0xCC59, 0xC3AD, 0xCC60, 0xC3AE, 0xCC64,
+ 0xC3AF, 0xCC66, 0xC3B0, 0xCC68, 0xC3B1, 0xCC70, 0xC3B2, 0xCC75, 0xC3B3, 0xCC98, 0xC3B4, 0xCC99, 0xC3B5, 0xCC9C, 0xC3B6, 0xCCA0,
+ 0xC3B7, 0xCCA8, 0xC3B8, 0xCCA9, 0xC3B9, 0xCCAB, 0xC3BA, 0xCCAC, 0xC3BB, 0xCCAD, 0xC3BC, 0xCCB4, 0xC3BD, 0xCCB5, 0xC3BE, 0xCCB8,
+ 0xC3BF, 0xCCBC, 0xC3C0, 0xCCC4, 0xC3C1, 0xCCC5, 0xC3C2, 0xCCC7, 0xC3C3, 0xCCC9, 0xC3C4, 0xCCD0, 0xC3C5, 0xCCD4, 0xC3C6, 0xCCE4,
+ 0xC3C7, 0xCCEC, 0xC3C8, 0xCCF0, 0xC3C9, 0xCD01, 0xC3CA, 0xCD08, 0xC3CB, 0xCD09, 0xC3CC, 0xCD0C, 0xC3CD, 0xCD10, 0xC3CE, 0xCD18,
+ 0xC3CF, 0xCD19, 0xC3D0, 0xCD1B, 0xC3D1, 0xCD1D, 0xC3D2, 0xCD24, 0xC3D3, 0xCD28, 0xC3D4, 0xCD2C, 0xC3D5, 0xCD39, 0xC3D6, 0xCD5C,
+ 0xC3D7, 0xCD60, 0xC3D8, 0xCD64, 0xC3D9, 0xCD6C, 0xC3DA, 0xCD6D, 0xC3DB, 0xCD6F, 0xC3DC, 0xCD71, 0xC3DD, 0xCD78, 0xC3DE, 0xCD88,
+ 0xC3DF, 0xCD94, 0xC3E0, 0xCD95, 0xC3E1, 0xCD98, 0xC3E2, 0xCD9C, 0xC3E3, 0xCDA4, 0xC3E4, 0xCDA5, 0xC3E5, 0xCDA7, 0xC3E6, 0xCDA9,
+ 0xC3E7, 0xCDB0, 0xC3E8, 0xCDC4, 0xC3E9, 0xCDCC, 0xC3EA, 0xCDD0, 0xC3EB, 0xCDE8, 0xC3EC, 0xCDEC, 0xC3ED, 0xCDF0, 0xC3EE, 0xCDF8,
+ 0xC3EF, 0xCDF9, 0xC3F0, 0xCDFB, 0xC3F1, 0xCDFD, 0xC3F2, 0xCE04, 0xC3F3, 0xCE08, 0xC3F4, 0xCE0C, 0xC3F5, 0xCE14, 0xC3F6, 0xCE19,
+ 0xC3F7, 0xCE20, 0xC3F8, 0xCE21, 0xC3F9, 0xCE24, 0xC3FA, 0xCE28, 0xC3FB, 0xCE30, 0xC3FC, 0xCE31, 0xC3FD, 0xCE33, 0xC3FE, 0xCE35,
+ 0xC441, 0xD6AB, 0xC442, 0xD6AD, 0xC443, 0xD6AE, 0xC444, 0xD6AF, 0xC445, 0xD6B1, 0xC446, 0xD6B2, 0xC447, 0xD6B3, 0xC448, 0xD6B4,
+ 0xC449, 0xD6B5, 0xC44A, 0xD6B6, 0xC44B, 0xD6B7, 0xC44C, 0xD6B8, 0xC44D, 0xD6BA, 0xC44E, 0xD6BC, 0xC44F, 0xD6BD, 0xC450, 0xD6BE,
+ 0xC451, 0xD6BF, 0xC452, 0xD6C0, 0xC453, 0xD6C1, 0xC454, 0xD6C2, 0xC455, 0xD6C3, 0xC456, 0xD6C6, 0xC457, 0xD6C7, 0xC458, 0xD6C9,
+ 0xC459, 0xD6CA, 0xC45A, 0xD6CB, 0xC461, 0xD6CD, 0xC462, 0xD6CE, 0xC463, 0xD6CF, 0xC464, 0xD6D0, 0xC465, 0xD6D2, 0xC466, 0xD6D3,
+ 0xC467, 0xD6D5, 0xC468, 0xD6D6, 0xC469, 0xD6D8, 0xC46A, 0xD6DA, 0xC46B, 0xD6DB, 0xC46C, 0xD6DC, 0xC46D, 0xD6DD, 0xC46E, 0xD6DE,
+ 0xC46F, 0xD6DF, 0xC470, 0xD6E1, 0xC471, 0xD6E2, 0xC472, 0xD6E3, 0xC473, 0xD6E5, 0xC474, 0xD6E6, 0xC475, 0xD6E7, 0xC476, 0xD6E9,
+ 0xC477, 0xD6EA, 0xC478, 0xD6EB, 0xC479, 0xD6EC, 0xC47A, 0xD6ED, 0xC481, 0xD6EE, 0xC482, 0xD6EF, 0xC483, 0xD6F1, 0xC484, 0xD6F2,
+ 0xC485, 0xD6F3, 0xC486, 0xD6F4, 0xC487, 0xD6F6, 0xC488, 0xD6F7, 0xC489, 0xD6F8, 0xC48A, 0xD6F9, 0xC48B, 0xD6FA, 0xC48C, 0xD6FB,
+ 0xC48D, 0xD6FE, 0xC48E, 0xD6FF, 0xC48F, 0xD701, 0xC490, 0xD702, 0xC491, 0xD703, 0xC492, 0xD705, 0xC493, 0xD706, 0xC494, 0xD707,
+ 0xC495, 0xD708, 0xC496, 0xD709, 0xC497, 0xD70A, 0xC498, 0xD70B, 0xC499, 0xD70C, 0xC49A, 0xD70D, 0xC49B, 0xD70E, 0xC49C, 0xD70F,
+ 0xC49D, 0xD710, 0xC49E, 0xD712, 0xC49F, 0xD713, 0xC4A0, 0xD714, 0xC4A1, 0xCE58, 0xC4A2, 0xCE59, 0xC4A3, 0xCE5C, 0xC4A4, 0xCE5F,
+ 0xC4A5, 0xCE60, 0xC4A6, 0xCE61, 0xC4A7, 0xCE68, 0xC4A8, 0xCE69, 0xC4A9, 0xCE6B, 0xC4AA, 0xCE6D, 0xC4AB, 0xCE74, 0xC4AC, 0xCE75,
+ 0xC4AD, 0xCE78, 0xC4AE, 0xCE7C, 0xC4AF, 0xCE84, 0xC4B0, 0xCE85, 0xC4B1, 0xCE87, 0xC4B2, 0xCE89, 0xC4B3, 0xCE90, 0xC4B4, 0xCE91,
+ 0xC4B5, 0xCE94, 0xC4B6, 0xCE98, 0xC4B7, 0xCEA0, 0xC4B8, 0xCEA1, 0xC4B9, 0xCEA3, 0xC4BA, 0xCEA4, 0xC4BB, 0xCEA5, 0xC4BC, 0xCEAC,
+ 0xC4BD, 0xCEAD, 0xC4BE, 0xCEC1, 0xC4BF, 0xCEE4, 0xC4C0, 0xCEE5, 0xC4C1, 0xCEE8, 0xC4C2, 0xCEEB, 0xC4C3, 0xCEEC, 0xC4C4, 0xCEF4,
+ 0xC4C5, 0xCEF5, 0xC4C6, 0xCEF7, 0xC4C7, 0xCEF8, 0xC4C8, 0xCEF9, 0xC4C9, 0xCF00, 0xC4CA, 0xCF01, 0xC4CB, 0xCF04, 0xC4CC, 0xCF08,
+ 0xC4CD, 0xCF10, 0xC4CE, 0xCF11, 0xC4CF, 0xCF13, 0xC4D0, 0xCF15, 0xC4D1, 0xCF1C, 0xC4D2, 0xCF20, 0xC4D3, 0xCF24, 0xC4D4, 0xCF2C,
+ 0xC4D5, 0xCF2D, 0xC4D6, 0xCF2F, 0xC4D7, 0xCF30, 0xC4D8, 0xCF31, 0xC4D9, 0xCF38, 0xC4DA, 0xCF54, 0xC4DB, 0xCF55, 0xC4DC, 0xCF58,
+ 0xC4DD, 0xCF5C, 0xC4DE, 0xCF64, 0xC4DF, 0xCF65, 0xC4E0, 0xCF67, 0xC4E1, 0xCF69, 0xC4E2, 0xCF70, 0xC4E3, 0xCF71, 0xC4E4, 0xCF74,
+ 0xC4E5, 0xCF78, 0xC4E6, 0xCF80, 0xC4E7, 0xCF85, 0xC4E8, 0xCF8C, 0xC4E9, 0xCFA1, 0xC4EA, 0xCFA8, 0xC4EB, 0xCFB0, 0xC4EC, 0xCFC4,
+ 0xC4ED, 0xCFE0, 0xC4EE, 0xCFE1, 0xC4EF, 0xCFE4, 0xC4F0, 0xCFE8, 0xC4F1, 0xCFF0, 0xC4F2, 0xCFF1, 0xC4F3, 0xCFF3, 0xC4F4, 0xCFF5,
+ 0xC4F5, 0xCFFC, 0xC4F6, 0xD000, 0xC4F7, 0xD004, 0xC4F8, 0xD011, 0xC4F9, 0xD018, 0xC4FA, 0xD02D, 0xC4FB, 0xD034, 0xC4FC, 0xD035,
+ 0xC4FD, 0xD038, 0xC4FE, 0xD03C, 0xC541, 0xD715, 0xC542, 0xD716, 0xC543, 0xD717, 0xC544, 0xD71A, 0xC545, 0xD71B, 0xC546, 0xD71D,
+ 0xC547, 0xD71E, 0xC548, 0xD71F, 0xC549, 0xD721, 0xC54A, 0xD722, 0xC54B, 0xD723, 0xC54C, 0xD724, 0xC54D, 0xD725, 0xC54E, 0xD726,
+ 0xC54F, 0xD727, 0xC550, 0xD72A, 0xC551, 0xD72C, 0xC552, 0xD72E, 0xC553, 0xD72F, 0xC554, 0xD730, 0xC555, 0xD731, 0xC556, 0xD732,
+ 0xC557, 0xD733, 0xC558, 0xD736, 0xC559, 0xD737, 0xC55A, 0xD739, 0xC561, 0xD73A, 0xC562, 0xD73B, 0xC563, 0xD73D, 0xC564, 0xD73E,
+ 0xC565, 0xD73F, 0xC566, 0xD740, 0xC567, 0xD741, 0xC568, 0xD742, 0xC569, 0xD743, 0xC56A, 0xD745, 0xC56B, 0xD746, 0xC56C, 0xD748,
+ 0xC56D, 0xD74A, 0xC56E, 0xD74B, 0xC56F, 0xD74C, 0xC570, 0xD74D, 0xC571, 0xD74E, 0xC572, 0xD74F, 0xC573, 0xD752, 0xC574, 0xD753,
+ 0xC575, 0xD755, 0xC576, 0xD75A, 0xC577, 0xD75B, 0xC578, 0xD75C, 0xC579, 0xD75D, 0xC57A, 0xD75E, 0xC581, 0xD75F, 0xC582, 0xD762,
+ 0xC583, 0xD764, 0xC584, 0xD766, 0xC585, 0xD767, 0xC586, 0xD768, 0xC587, 0xD76A, 0xC588, 0xD76B, 0xC589, 0xD76D, 0xC58A, 0xD76E,
+ 0xC58B, 0xD76F, 0xC58C, 0xD771, 0xC58D, 0xD772, 0xC58E, 0xD773, 0xC58F, 0xD775, 0xC590, 0xD776, 0xC591, 0xD777, 0xC592, 0xD778,
+ 0xC593, 0xD779, 0xC594, 0xD77A, 0xC595, 0xD77B, 0xC596, 0xD77E, 0xC597, 0xD77F, 0xC598, 0xD780, 0xC599, 0xD782, 0xC59A, 0xD783,
+ 0xC59B, 0xD784, 0xC59C, 0xD785, 0xC59D, 0xD786, 0xC59E, 0xD787, 0xC59F, 0xD78A, 0xC5A0, 0xD78B, 0xC5A1, 0xD044, 0xC5A2, 0xD045,
+ 0xC5A3, 0xD047, 0xC5A4, 0xD049, 0xC5A5, 0xD050, 0xC5A6, 0xD054, 0xC5A7, 0xD058, 0xC5A8, 0xD060, 0xC5A9, 0xD06C, 0xC5AA, 0xD06D,
+ 0xC5AB, 0xD070, 0xC5AC, 0xD074, 0xC5AD, 0xD07C, 0xC5AE, 0xD07D, 0xC5AF, 0xD081, 0xC5B0, 0xD0A4, 0xC5B1, 0xD0A5, 0xC5B2, 0xD0A8,
+ 0xC5B3, 0xD0AC, 0xC5B4, 0xD0B4, 0xC5B5, 0xD0B5, 0xC5B6, 0xD0B7, 0xC5B7, 0xD0B9, 0xC5B8, 0xD0C0, 0xC5B9, 0xD0C1, 0xC5BA, 0xD0C4,
+ 0xC5BB, 0xD0C8, 0xC5BC, 0xD0C9, 0xC5BD, 0xD0D0, 0xC5BE, 0xD0D1, 0xC5BF, 0xD0D3, 0xC5C0, 0xD0D4, 0xC5C1, 0xD0D5, 0xC5C2, 0xD0DC,
+ 0xC5C3, 0xD0DD, 0xC5C4, 0xD0E0, 0xC5C5, 0xD0E4, 0xC5C6, 0xD0EC, 0xC5C7, 0xD0ED, 0xC5C8, 0xD0EF, 0xC5C9, 0xD0F0, 0xC5CA, 0xD0F1,
+ 0xC5CB, 0xD0F8, 0xC5CC, 0xD10D, 0xC5CD, 0xD130, 0xC5CE, 0xD131, 0xC5CF, 0xD134, 0xC5D0, 0xD138, 0xC5D1, 0xD13A, 0xC5D2, 0xD140,
+ 0xC5D3, 0xD141, 0xC5D4, 0xD143, 0xC5D5, 0xD144, 0xC5D6, 0xD145, 0xC5D7, 0xD14C, 0xC5D8, 0xD14D, 0xC5D9, 0xD150, 0xC5DA, 0xD154,
+ 0xC5DB, 0xD15C, 0xC5DC, 0xD15D, 0xC5DD, 0xD15F, 0xC5DE, 0xD161, 0xC5DF, 0xD168, 0xC5E0, 0xD16C, 0xC5E1, 0xD17C, 0xC5E2, 0xD184,
+ 0xC5E3, 0xD188, 0xC5E4, 0xD1A0, 0xC5E5, 0xD1A1, 0xC5E6, 0xD1A4, 0xC5E7, 0xD1A8, 0xC5E8, 0xD1B0, 0xC5E9, 0xD1B1, 0xC5EA, 0xD1B3,
+ 0xC5EB, 0xD1B5, 0xC5EC, 0xD1BA, 0xC5ED, 0xD1BC, 0xC5EE, 0xD1C0, 0xC5EF, 0xD1D8, 0xC5F0, 0xD1F4, 0xC5F1, 0xD1F8, 0xC5F2, 0xD207,
+ 0xC5F3, 0xD209, 0xC5F4, 0xD210, 0xC5F5, 0xD22C, 0xC5F6, 0xD22D, 0xC5F7, 0xD230, 0xC5F8, 0xD234, 0xC5F9, 0xD23C, 0xC5FA, 0xD23D,
+ 0xC5FB, 0xD23F, 0xC5FC, 0xD241, 0xC5FD, 0xD248, 0xC5FE, 0xD25C, 0xC641, 0xD78D, 0xC642, 0xD78E, 0xC643, 0xD78F, 0xC644, 0xD791,
+ 0xC645, 0xD792, 0xC646, 0xD793, 0xC647, 0xD794, 0xC648, 0xD795, 0xC649, 0xD796, 0xC64A, 0xD797, 0xC64B, 0xD79A, 0xC64C, 0xD79C,
+ 0xC64D, 0xD79E, 0xC64E, 0xD79F, 0xC64F, 0xD7A0, 0xC650, 0xD7A1, 0xC651, 0xD7A2, 0xC652, 0xD7A3, 0xC6A1, 0xD264, 0xC6A2, 0xD280,
+ 0xC6A3, 0xD281, 0xC6A4, 0xD284, 0xC6A5, 0xD288, 0xC6A6, 0xD290, 0xC6A7, 0xD291, 0xC6A8, 0xD295, 0xC6A9, 0xD29C, 0xC6AA, 0xD2A0,
+ 0xC6AB, 0xD2A4, 0xC6AC, 0xD2AC, 0xC6AD, 0xD2B1, 0xC6AE, 0xD2B8, 0xC6AF, 0xD2B9, 0xC6B0, 0xD2BC, 0xC6B1, 0xD2BF, 0xC6B2, 0xD2C0,
+ 0xC6B3, 0xD2C2, 0xC6B4, 0xD2C8, 0xC6B5, 0xD2C9, 0xC6B6, 0xD2CB, 0xC6B7, 0xD2D4, 0xC6B8, 0xD2D8, 0xC6B9, 0xD2DC, 0xC6BA, 0xD2E4,
+ 0xC6BB, 0xD2E5, 0xC6BC, 0xD2F0, 0xC6BD, 0xD2F1, 0xC6BE, 0xD2F4, 0xC6BF, 0xD2F8, 0xC6C0, 0xD300, 0xC6C1, 0xD301, 0xC6C2, 0xD303,
+ 0xC6C3, 0xD305, 0xC6C4, 0xD30C, 0xC6C5, 0xD30D, 0xC6C6, 0xD30E, 0xC6C7, 0xD310, 0xC6C8, 0xD314, 0xC6C9, 0xD316, 0xC6CA, 0xD31C,
+ 0xC6CB, 0xD31D, 0xC6CC, 0xD31F, 0xC6CD, 0xD320, 0xC6CE, 0xD321, 0xC6CF, 0xD325, 0xC6D0, 0xD328, 0xC6D1, 0xD329, 0xC6D2, 0xD32C,
+ 0xC6D3, 0xD330, 0xC6D4, 0xD338, 0xC6D5, 0xD339, 0xC6D6, 0xD33B, 0xC6D7, 0xD33C, 0xC6D8, 0xD33D, 0xC6D9, 0xD344, 0xC6DA, 0xD345,
+ 0xC6DB, 0xD37C, 0xC6DC, 0xD37D, 0xC6DD, 0xD380, 0xC6DE, 0xD384, 0xC6DF, 0xD38C, 0xC6E0, 0xD38D, 0xC6E1, 0xD38F, 0xC6E2, 0xD390,
+ 0xC6E3, 0xD391, 0xC6E4, 0xD398, 0xC6E5, 0xD399, 0xC6E6, 0xD39C, 0xC6E7, 0xD3A0, 0xC6E8, 0xD3A8, 0xC6E9, 0xD3A9, 0xC6EA, 0xD3AB,
+ 0xC6EB, 0xD3AD, 0xC6EC, 0xD3B4, 0xC6ED, 0xD3B8, 0xC6EE, 0xD3BC, 0xC6EF, 0xD3C4, 0xC6F0, 0xD3C5, 0xC6F1, 0xD3C8, 0xC6F2, 0xD3C9,
+ 0xC6F3, 0xD3D0, 0xC6F4, 0xD3D8, 0xC6F5, 0xD3E1, 0xC6F6, 0xD3E3, 0xC6F7, 0xD3EC, 0xC6F8, 0xD3ED, 0xC6F9, 0xD3F0, 0xC6FA, 0xD3F4,
+ 0xC6FB, 0xD3FC, 0xC6FC, 0xD3FD, 0xC6FD, 0xD3FF, 0xC6FE, 0xD401, 0xC7A1, 0xD408, 0xC7A2, 0xD41D, 0xC7A3, 0xD440, 0xC7A4, 0xD444,
+ 0xC7A5, 0xD45C, 0xC7A6, 0xD460, 0xC7A7, 0xD464, 0xC7A8, 0xD46D, 0xC7A9, 0xD46F, 0xC7AA, 0xD478, 0xC7AB, 0xD479, 0xC7AC, 0xD47C,
+ 0xC7AD, 0xD47F, 0xC7AE, 0xD480, 0xC7AF, 0xD482, 0xC7B0, 0xD488, 0xC7B1, 0xD489, 0xC7B2, 0xD48B, 0xC7B3, 0xD48D, 0xC7B4, 0xD494,
+ 0xC7B5, 0xD4A9, 0xC7B6, 0xD4CC, 0xC7B7, 0xD4D0, 0xC7B8, 0xD4D4, 0xC7B9, 0xD4DC, 0xC7BA, 0xD4DF, 0xC7BB, 0xD4E8, 0xC7BC, 0xD4EC,
+ 0xC7BD, 0xD4F0, 0xC7BE, 0xD4F8, 0xC7BF, 0xD4FB, 0xC7C0, 0xD4FD, 0xC7C1, 0xD504, 0xC7C2, 0xD508, 0xC7C3, 0xD50C, 0xC7C4, 0xD514,
+ 0xC7C5, 0xD515, 0xC7C6, 0xD517, 0xC7C7, 0xD53C, 0xC7C8, 0xD53D, 0xC7C9, 0xD540, 0xC7CA, 0xD544, 0xC7CB, 0xD54C, 0xC7CC, 0xD54D,
+ 0xC7CD, 0xD54F, 0xC7CE, 0xD551, 0xC7CF, 0xD558, 0xC7D0, 0xD559, 0xC7D1, 0xD55C, 0xC7D2, 0xD560, 0xC7D3, 0xD565, 0xC7D4, 0xD568,
+ 0xC7D5, 0xD569, 0xC7D6, 0xD56B, 0xC7D7, 0xD56D, 0xC7D8, 0xD574, 0xC7D9, 0xD575, 0xC7DA, 0xD578, 0xC7DB, 0xD57C, 0xC7DC, 0xD584,
+ 0xC7DD, 0xD585, 0xC7DE, 0xD587, 0xC7DF, 0xD588, 0xC7E0, 0xD589, 0xC7E1, 0xD590, 0xC7E2, 0xD5A5, 0xC7E3, 0xD5C8, 0xC7E4, 0xD5C9,
+ 0xC7E5, 0xD5CC, 0xC7E6, 0xD5D0, 0xC7E7, 0xD5D2, 0xC7E8, 0xD5D8, 0xC7E9, 0xD5D9, 0xC7EA, 0xD5DB, 0xC7EB, 0xD5DD, 0xC7EC, 0xD5E4,
+ 0xC7ED, 0xD5E5, 0xC7EE, 0xD5E8, 0xC7EF, 0xD5EC, 0xC7F0, 0xD5F4, 0xC7F1, 0xD5F5, 0xC7F2, 0xD5F7, 0xC7F3, 0xD5F9, 0xC7F4, 0xD600,
+ 0xC7F5, 0xD601, 0xC7F6, 0xD604, 0xC7F7, 0xD608, 0xC7F8, 0xD610, 0xC7F9, 0xD611, 0xC7FA, 0xD613, 0xC7FB, 0xD614, 0xC7FC, 0xD615,
+ 0xC7FD, 0xD61C, 0xC7FE, 0xD620, 0xC8A1, 0xD624, 0xC8A2, 0xD62D, 0xC8A3, 0xD638, 0xC8A4, 0xD639, 0xC8A5, 0xD63C, 0xC8A6, 0xD640,
+ 0xC8A7, 0xD645, 0xC8A8, 0xD648, 0xC8A9, 0xD649, 0xC8AA, 0xD64B, 0xC8AB, 0xD64D, 0xC8AC, 0xD651, 0xC8AD, 0xD654, 0xC8AE, 0xD655,
+ 0xC8AF, 0xD658, 0xC8B0, 0xD65C, 0xC8B1, 0xD667, 0xC8B2, 0xD669, 0xC8B3, 0xD670, 0xC8B4, 0xD671, 0xC8B5, 0xD674, 0xC8B6, 0xD683,
+ 0xC8B7, 0xD685, 0xC8B8, 0xD68C, 0xC8B9, 0xD68D, 0xC8BA, 0xD690, 0xC8BB, 0xD694, 0xC8BC, 0xD69D, 0xC8BD, 0xD69F, 0xC8BE, 0xD6A1,
+ 0xC8BF, 0xD6A8, 0xC8C0, 0xD6AC, 0xC8C1, 0xD6B0, 0xC8C2, 0xD6B9, 0xC8C3, 0xD6BB, 0xC8C4, 0xD6C4, 0xC8C5, 0xD6C5, 0xC8C6, 0xD6C8,
+ 0xC8C7, 0xD6CC, 0xC8C8, 0xD6D1, 0xC8C9, 0xD6D4, 0xC8CA, 0xD6D7, 0xC8CB, 0xD6D9, 0xC8CC, 0xD6E0, 0xC8CD, 0xD6E4, 0xC8CE, 0xD6E8,
+ 0xC8CF, 0xD6F0, 0xC8D0, 0xD6F5, 0xC8D1, 0xD6FC, 0xC8D2, 0xD6FD, 0xC8D3, 0xD700, 0xC8D4, 0xD704, 0xC8D5, 0xD711, 0xC8D6, 0xD718,
+ 0xC8D7, 0xD719, 0xC8D8, 0xD71C, 0xC8D9, 0xD720, 0xC8DA, 0xD728, 0xC8DB, 0xD729, 0xC8DC, 0xD72B, 0xC8DD, 0xD72D, 0xC8DE, 0xD734,
+ 0xC8DF, 0xD735, 0xC8E0, 0xD738, 0xC8E1, 0xD73C, 0xC8E2, 0xD744, 0xC8E3, 0xD747, 0xC8E4, 0xD749, 0xC8E5, 0xD750, 0xC8E6, 0xD751,
+ 0xC8E7, 0xD754, 0xC8E8, 0xD756, 0xC8E9, 0xD757, 0xC8EA, 0xD758, 0xC8EB, 0xD759, 0xC8EC, 0xD760, 0xC8ED, 0xD761, 0xC8EE, 0xD763,
+ 0xC8EF, 0xD765, 0xC8F0, 0xD769, 0xC8F1, 0xD76C, 0xC8F2, 0xD770, 0xC8F3, 0xD774, 0xC8F4, 0xD77C, 0xC8F5, 0xD77D, 0xC8F6, 0xD781,
+ 0xC8F7, 0xD788, 0xC8F8, 0xD789, 0xC8F9, 0xD78C, 0xC8FA, 0xD790, 0xC8FB, 0xD798, 0xC8FC, 0xD799, 0xC8FD, 0xD79B, 0xC8FE, 0xD79D,
+ 0xCAA1, 0x4F3D, 0xCAA2, 0x4F73, 0xCAA3, 0x5047, 0xCAA4, 0x50F9, 0xCAA5, 0x52A0, 0xCAA6, 0x53EF, 0xCAA7, 0x5475, 0xCAA8, 0x54E5,
+ 0xCAA9, 0x5609, 0xCAAA, 0x5AC1, 0xCAAB, 0x5BB6, 0xCAAC, 0x6687, 0xCAAD, 0x67B6, 0xCAAE, 0x67B7, 0xCAAF, 0x67EF, 0xCAB0, 0x6B4C,
+ 0xCAB1, 0x73C2, 0xCAB2, 0x75C2, 0xCAB3, 0x7A3C, 0xCAB4, 0x82DB, 0xCAB5, 0x8304, 0xCAB6, 0x8857, 0xCAB7, 0x8888, 0xCAB8, 0x8A36,
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+ 0xD1D7, 0x61E6, 0xD1D8, 0xF90D, 0xD1D9, 0x62CF, 0xD1DA, 0x62FF, 0xD1DB, 0xF90E, 0xD1DC, 0xF90F, 0xD1DD, 0xF910, 0xD1DE, 0xF911,
+ 0xD1DF, 0xF912, 0xD1E0, 0xF913, 0xD1E1, 0x90A3, 0xD1E2, 0xF914, 0xD1E3, 0xF915, 0xD1E4, 0xF916, 0xD1E5, 0xF917, 0xD1E6, 0xF918,
+ 0xD1E7, 0x8AFE, 0xD1E8, 0xF919, 0xD1E9, 0xF91A, 0xD1EA, 0xF91B, 0xD1EB, 0xF91C, 0xD1EC, 0x6696, 0xD1ED, 0xF91D, 0xD1EE, 0x7156,
+ 0xD1EF, 0xF91E, 0xD1F0, 0xF91F, 0xD1F1, 0x96E3, 0xD1F2, 0xF920, 0xD1F3, 0x634F, 0xD1F4, 0x637A, 0xD1F5, 0x5357, 0xD1F6, 0xF921,
+ 0xD1F7, 0x678F, 0xD1F8, 0x6960, 0xD1F9, 0x6E73, 0xD1FA, 0xF922, 0xD1FB, 0x7537, 0xD1FC, 0xF923, 0xD1FD, 0xF924, 0xD1FE, 0xF925,
+ 0xD2A1, 0x7D0D, 0xD2A2, 0xF926, 0xD2A3, 0xF927, 0xD2A4, 0x8872, 0xD2A5, 0x56CA, 0xD2A6, 0x5A18, 0xD2A7, 0xF928, 0xD2A8, 0xF929,
+ 0xD2A9, 0xF92A, 0xD2AA, 0xF92B, 0xD2AB, 0xF92C, 0xD2AC, 0x4E43, 0xD2AD, 0xF92D, 0xD2AE, 0x5167, 0xD2AF, 0x5948, 0xD2B0, 0x67F0,
+ 0xD2B1, 0x8010, 0xD2B2, 0xF92E, 0xD2B3, 0x5973, 0xD2B4, 0x5E74, 0xD2B5, 0x649A, 0xD2B6, 0x79CA, 0xD2B7, 0x5FF5, 0xD2B8, 0x606C,
+ 0xD2B9, 0x62C8, 0xD2BA, 0x637B, 0xD2BB, 0x5BE7, 0xD2BC, 0x5BD7, 0xD2BD, 0x52AA, 0xD2BE, 0xF92F, 0xD2BF, 0x5974, 0xD2C0, 0x5F29,
+ 0xD2C1, 0x6012, 0xD2C2, 0xF930, 0xD2C3, 0xF931, 0xD2C4, 0xF932, 0xD2C5, 0x7459, 0xD2C6, 0xF933, 0xD2C7, 0xF934, 0xD2C8, 0xF935,
+ 0xD2C9, 0xF936, 0xD2CA, 0xF937, 0xD2CB, 0xF938, 0xD2CC, 0x99D1, 0xD2CD, 0xF939, 0xD2CE, 0xF93A, 0xD2CF, 0xF93B, 0xD2D0, 0xF93C,
+ 0xD2D1, 0xF93D, 0xD2D2, 0xF93E, 0xD2D3, 0xF93F, 0xD2D4, 0xF940, 0xD2D5, 0xF941, 0xD2D6, 0xF942, 0xD2D7, 0xF943, 0xD2D8, 0x6FC3,
+ 0xD2D9, 0xF944, 0xD2DA, 0xF945, 0xD2DB, 0x81BF, 0xD2DC, 0x8FB2, 0xD2DD, 0x60F1, 0xD2DE, 0xF946, 0xD2DF, 0xF947, 0xD2E0, 0x8166,
+ 0xD2E1, 0xF948, 0xD2E2, 0xF949, 0xD2E3, 0x5C3F, 0xD2E4, 0xF94A, 0xD2E5, 0xF94B, 0xD2E6, 0xF94C, 0xD2E7, 0xF94D, 0xD2E8, 0xF94E,
+ 0xD2E9, 0xF94F, 0xD2EA, 0xF950, 0xD2EB, 0xF951, 0xD2EC, 0x5AE9, 0xD2ED, 0x8A25, 0xD2EE, 0x677B, 0xD2EF, 0x7D10, 0xD2F0, 0xF952,
+ 0xD2F1, 0xF953, 0xD2F2, 0xF954, 0xD2F3, 0xF955, 0xD2F4, 0xF956, 0xD2F5, 0xF957, 0xD2F6, 0x80FD, 0xD2F7, 0xF958, 0xD2F8, 0xF959,
+ 0xD2F9, 0x5C3C, 0xD2FA, 0x6CE5, 0xD2FB, 0x533F, 0xD2FC, 0x6EBA, 0xD2FD, 0x591A, 0xD2FE, 0x8336, 0xD3A1, 0x4E39, 0xD3A2, 0x4EB6,
+ 0xD3A3, 0x4F46, 0xD3A4, 0x55AE, 0xD3A5, 0x5718, 0xD3A6, 0x58C7, 0xD3A7, 0x5F56, 0xD3A8, 0x65B7, 0xD3A9, 0x65E6, 0xD3AA, 0x6A80,
+ 0xD3AB, 0x6BB5, 0xD3AC, 0x6E4D, 0xD3AD, 0x77ED, 0xD3AE, 0x7AEF, 0xD3AF, 0x7C1E, 0xD3B0, 0x7DDE, 0xD3B1, 0x86CB, 0xD3B2, 0x8892,
+ 0xD3B3, 0x9132, 0xD3B4, 0x935B, 0xD3B5, 0x64BB, 0xD3B6, 0x6FBE, 0xD3B7, 0x737A, 0xD3B8, 0x75B8, 0xD3B9, 0x9054, 0xD3BA, 0x5556,
+ 0xD3BB, 0x574D, 0xD3BC, 0x61BA, 0xD3BD, 0x64D4, 0xD3BE, 0x66C7, 0xD3BF, 0x6DE1, 0xD3C0, 0x6E5B, 0xD3C1, 0x6F6D, 0xD3C2, 0x6FB9,
+ 0xD3C3, 0x75F0, 0xD3C4, 0x8043, 0xD3C5, 0x81BD, 0xD3C6, 0x8541, 0xD3C7, 0x8983, 0xD3C8, 0x8AC7, 0xD3C9, 0x8B5A, 0xD3CA, 0x931F,
+ 0xD3CB, 0x6C93, 0xD3CC, 0x7553, 0xD3CD, 0x7B54, 0xD3CE, 0x8E0F, 0xD3CF, 0x905D, 0xD3D0, 0x5510, 0xD3D1, 0x5802, 0xD3D2, 0x5858,
+ 0xD3D3, 0x5E62, 0xD3D4, 0x6207, 0xD3D5, 0x649E, 0xD3D6, 0x68E0, 0xD3D7, 0x7576, 0xD3D8, 0x7CD6, 0xD3D9, 0x87B3, 0xD3DA, 0x9EE8,
+ 0xD3DB, 0x4EE3, 0xD3DC, 0x5788, 0xD3DD, 0x576E, 0xD3DE, 0x5927, 0xD3DF, 0x5C0D, 0xD3E0, 0x5CB1, 0xD3E1, 0x5E36, 0xD3E2, 0x5F85,
+ 0xD3E3, 0x6234, 0xD3E4, 0x64E1, 0xD3E5, 0x73B3, 0xD3E6, 0x81FA, 0xD3E7, 0x888B, 0xD3E8, 0x8CB8, 0xD3E9, 0x968A, 0xD3EA, 0x9EDB,
+ 0xD3EB, 0x5B85, 0xD3EC, 0x5FB7, 0xD3ED, 0x60B3, 0xD3EE, 0x5012, 0xD3EF, 0x5200, 0xD3F0, 0x5230, 0xD3F1, 0x5716, 0xD3F2, 0x5835,
+ 0xD3F3, 0x5857, 0xD3F4, 0x5C0E, 0xD3F5, 0x5C60, 0xD3F6, 0x5CF6, 0xD3F7, 0x5D8B, 0xD3F8, 0x5EA6, 0xD3F9, 0x5F92, 0xD3FA, 0x60BC,
+ 0xD3FB, 0x6311, 0xD3FC, 0x6389, 0xD3FD, 0x6417, 0xD3FE, 0x6843, 0xD4A1, 0x68F9, 0xD4A2, 0x6AC2, 0xD4A3, 0x6DD8, 0xD4A4, 0x6E21,
+ 0xD4A5, 0x6ED4, 0xD4A6, 0x6FE4, 0xD4A7, 0x71FE, 0xD4A8, 0x76DC, 0xD4A9, 0x7779, 0xD4AA, 0x79B1, 0xD4AB, 0x7A3B, 0xD4AC, 0x8404,
+ 0xD4AD, 0x89A9, 0xD4AE, 0x8CED, 0xD4AF, 0x8DF3, 0xD4B0, 0x8E48, 0xD4B1, 0x9003, 0xD4B2, 0x9014, 0xD4B3, 0x9053, 0xD4B4, 0x90FD,
+ 0xD4B5, 0x934D, 0xD4B6, 0x9676, 0xD4B7, 0x97DC, 0xD4B8, 0x6BD2, 0xD4B9, 0x7006, 0xD4BA, 0x7258, 0xD4BB, 0x72A2, 0xD4BC, 0x7368,
+ 0xD4BD, 0x7763, 0xD4BE, 0x79BF, 0xD4BF, 0x7BE4, 0xD4C0, 0x7E9B, 0xD4C1, 0x8B80, 0xD4C2, 0x58A9, 0xD4C3, 0x60C7, 0xD4C4, 0x6566,
+ 0xD4C5, 0x65FD, 0xD4C6, 0x66BE, 0xD4C7, 0x6C8C, 0xD4C8, 0x711E, 0xD4C9, 0x71C9, 0xD4CA, 0x8C5A, 0xD4CB, 0x9813, 0xD4CC, 0x4E6D,
+ 0xD4CD, 0x7A81, 0xD4CE, 0x4EDD, 0xD4CF, 0x51AC, 0xD4D0, 0x51CD, 0xD4D1, 0x52D5, 0xD4D2, 0x540C, 0xD4D3, 0x61A7, 0xD4D4, 0x6771,
+ 0xD4D5, 0x6850, 0xD4D6, 0x68DF, 0xD4D7, 0x6D1E, 0xD4D8, 0x6F7C, 0xD4D9, 0x75BC, 0xD4DA, 0x77B3, 0xD4DB, 0x7AE5, 0xD4DC, 0x80F4,
+ 0xD4DD, 0x8463, 0xD4DE, 0x9285, 0xD4DF, 0x515C, 0xD4E0, 0x6597, 0xD4E1, 0x675C, 0xD4E2, 0x6793, 0xD4E3, 0x75D8, 0xD4E4, 0x7AC7,
+ 0xD4E5, 0x8373, 0xD4E6, 0xF95A, 0xD4E7, 0x8C46, 0xD4E8, 0x9017, 0xD4E9, 0x982D, 0xD4EA, 0x5C6F, 0xD4EB, 0x81C0, 0xD4EC, 0x829A,
+ 0xD4ED, 0x9041, 0xD4EE, 0x906F, 0xD4EF, 0x920D, 0xD4F0, 0x5F97, 0xD4F1, 0x5D9D, 0xD4F2, 0x6A59, 0xD4F3, 0x71C8, 0xD4F4, 0x767B,
+ 0xD4F5, 0x7B49, 0xD4F6, 0x85E4, 0xD4F7, 0x8B04, 0xD4F8, 0x9127, 0xD4F9, 0x9A30, 0xD4FA, 0x5587, 0xD4FB, 0x61F6, 0xD4FC, 0xF95B,
+ 0xD4FD, 0x7669, 0xD4FE, 0x7F85, 0xD5A1, 0x863F, 0xD5A2, 0x87BA, 0xD5A3, 0x88F8, 0xD5A4, 0x908F, 0xD5A5, 0xF95C, 0xD5A6, 0x6D1B,
+ 0xD5A7, 0x70D9, 0xD5A8, 0x73DE, 0xD5A9, 0x7D61, 0xD5AA, 0x843D, 0xD5AB, 0xF95D, 0xD5AC, 0x916A, 0xD5AD, 0x99F1, 0xD5AE, 0xF95E,
+ 0xD5AF, 0x4E82, 0xD5B0, 0x5375, 0xD5B1, 0x6B04, 0xD5B2, 0x6B12, 0xD5B3, 0x703E, 0xD5B4, 0x721B, 0xD5B5, 0x862D, 0xD5B6, 0x9E1E,
+ 0xD5B7, 0x524C, 0xD5B8, 0x8FA3, 0xD5B9, 0x5D50, 0xD5BA, 0x64E5, 0xD5BB, 0x652C, 0xD5BC, 0x6B16, 0xD5BD, 0x6FEB, 0xD5BE, 0x7C43,
+ 0xD5BF, 0x7E9C, 0xD5C0, 0x85CD, 0xD5C1, 0x8964, 0xD5C2, 0x89BD, 0xD5C3, 0x62C9, 0xD5C4, 0x81D8, 0xD5C5, 0x881F, 0xD5C6, 0x5ECA,
+ 0xD5C7, 0x6717, 0xD5C8, 0x6D6A, 0xD5C9, 0x72FC, 0xD5CA, 0x7405, 0xD5CB, 0x746F, 0xD5CC, 0x8782, 0xD5CD, 0x90DE, 0xD5CE, 0x4F86,
+ 0xD5CF, 0x5D0D, 0xD5D0, 0x5FA0, 0xD5D1, 0x840A, 0xD5D2, 0x51B7, 0xD5D3, 0x63A0, 0xD5D4, 0x7565, 0xD5D5, 0x4EAE, 0xD5D6, 0x5006,
+ 0xD5D7, 0x5169, 0xD5D8, 0x51C9, 0xD5D9, 0x6881, 0xD5DA, 0x6A11, 0xD5DB, 0x7CAE, 0xD5DC, 0x7CB1, 0xD5DD, 0x7CE7, 0xD5DE, 0x826F,
+ 0xD5DF, 0x8AD2, 0xD5E0, 0x8F1B, 0xD5E1, 0x91CF, 0xD5E2, 0x4FB6, 0xD5E3, 0x5137, 0xD5E4, 0x52F5, 0xD5E5, 0x5442, 0xD5E6, 0x5EEC,
+ 0xD5E7, 0x616E, 0xD5E8, 0x623E, 0xD5E9, 0x65C5, 0xD5EA, 0x6ADA, 0xD5EB, 0x6FFE, 0xD5EC, 0x792A, 0xD5ED, 0x85DC, 0xD5EE, 0x8823,
+ 0xD5EF, 0x95AD, 0xD5F0, 0x9A62, 0xD5F1, 0x9A6A, 0xD5F2, 0x9E97, 0xD5F3, 0x9ECE, 0xD5F4, 0x529B, 0xD5F5, 0x66C6, 0xD5F6, 0x6B77,
+ 0xD5F7, 0x701D, 0xD5F8, 0x792B, 0xD5F9, 0x8F62, 0xD5FA, 0x9742, 0xD5FB, 0x6190, 0xD5FC, 0x6200, 0xD5FD, 0x6523, 0xD5FE, 0x6F23,
+ 0xD6A1, 0x7149, 0xD6A2, 0x7489, 0xD6A3, 0x7DF4, 0xD6A4, 0x806F, 0xD6A5, 0x84EE, 0xD6A6, 0x8F26, 0xD6A7, 0x9023, 0xD6A8, 0x934A,
+ 0xD6A9, 0x51BD, 0xD6AA, 0x5217, 0xD6AB, 0x52A3, 0xD6AC, 0x6D0C, 0xD6AD, 0x70C8, 0xD6AE, 0x88C2, 0xD6AF, 0x5EC9, 0xD6B0, 0x6582,
+ 0xD6B1, 0x6BAE, 0xD6B2, 0x6FC2, 0xD6B3, 0x7C3E, 0xD6B4, 0x7375, 0xD6B5, 0x4EE4, 0xD6B6, 0x4F36, 0xD6B7, 0x56F9, 0xD6B8, 0xF95F,
+ 0xD6B9, 0x5CBA, 0xD6BA, 0x5DBA, 0xD6BB, 0x601C, 0xD6BC, 0x73B2, 0xD6BD, 0x7B2D, 0xD6BE, 0x7F9A, 0xD6BF, 0x7FCE, 0xD6C0, 0x8046,
+ 0xD6C1, 0x901E, 0xD6C2, 0x9234, 0xD6C3, 0x96F6, 0xD6C4, 0x9748, 0xD6C5, 0x9818, 0xD6C6, 0x9F61, 0xD6C7, 0x4F8B, 0xD6C8, 0x6FA7,
+ 0xD6C9, 0x79AE, 0xD6CA, 0x91B4, 0xD6CB, 0x96B7, 0xD6CC, 0x52DE, 0xD6CD, 0xF960, 0xD6CE, 0x6488, 0xD6CF, 0x64C4, 0xD6D0, 0x6AD3,
+ 0xD6D1, 0x6F5E, 0xD6D2, 0x7018, 0xD6D3, 0x7210, 0xD6D4, 0x76E7, 0xD6D5, 0x8001, 0xD6D6, 0x8606, 0xD6D7, 0x865C, 0xD6D8, 0x8DEF,
+ 0xD6D9, 0x8F05, 0xD6DA, 0x9732, 0xD6DB, 0x9B6F, 0xD6DC, 0x9DFA, 0xD6DD, 0x9E75, 0xD6DE, 0x788C, 0xD6DF, 0x797F, 0xD6E0, 0x7DA0,
+ 0xD6E1, 0x83C9, 0xD6E2, 0x9304, 0xD6E3, 0x9E7F, 0xD6E4, 0x9E93, 0xD6E5, 0x8AD6, 0xD6E6, 0x58DF, 0xD6E7, 0x5F04, 0xD6E8, 0x6727,
+ 0xD6E9, 0x7027, 0xD6EA, 0x74CF, 0xD6EB, 0x7C60, 0xD6EC, 0x807E, 0xD6ED, 0x5121, 0xD6EE, 0x7028, 0xD6EF, 0x7262, 0xD6F0, 0x78CA,
+ 0xD6F1, 0x8CC2, 0xD6F2, 0x8CDA, 0xD6F3, 0x8CF4, 0xD6F4, 0x96F7, 0xD6F5, 0x4E86, 0xD6F6, 0x50DA, 0xD6F7, 0x5BEE, 0xD6F8, 0x5ED6,
+ 0xD6F9, 0x6599, 0xD6FA, 0x71CE, 0xD6FB, 0x7642, 0xD6FC, 0x77AD, 0xD6FD, 0x804A, 0xD6FE, 0x84FC, 0xD7A1, 0x907C, 0xD7A2, 0x9B27,
+ 0xD7A3, 0x9F8D, 0xD7A4, 0x58D8, 0xD7A5, 0x5A41, 0xD7A6, 0x5C62, 0xD7A7, 0x6A13, 0xD7A8, 0x6DDA, 0xD7A9, 0x6F0F, 0xD7AA, 0x763B,
+ 0xD7AB, 0x7D2F, 0xD7AC, 0x7E37, 0xD7AD, 0x851E, 0xD7AE, 0x8938, 0xD7AF, 0x93E4, 0xD7B0, 0x964B, 0xD7B1, 0x5289, 0xD7B2, 0x65D2,
+ 0xD7B3, 0x67F3, 0xD7B4, 0x69B4, 0xD7B5, 0x6D41, 0xD7B6, 0x6E9C, 0xD7B7, 0x700F, 0xD7B8, 0x7409, 0xD7B9, 0x7460, 0xD7BA, 0x7559,
+ 0xD7BB, 0x7624, 0xD7BC, 0x786B, 0xD7BD, 0x8B2C, 0xD7BE, 0x985E, 0xD7BF, 0x516D, 0xD7C0, 0x622E, 0xD7C1, 0x9678, 0xD7C2, 0x4F96,
+ 0xD7C3, 0x502B, 0xD7C4, 0x5D19, 0xD7C5, 0x6DEA, 0xD7C6, 0x7DB8, 0xD7C7, 0x8F2A, 0xD7C8, 0x5F8B, 0xD7C9, 0x6144, 0xD7CA, 0x6817,
+ 0xD7CB, 0xF961, 0xD7CC, 0x9686, 0xD7CD, 0x52D2, 0xD7CE, 0x808B, 0xD7CF, 0x51DC, 0xD7D0, 0x51CC, 0xD7D1, 0x695E, 0xD7D2, 0x7A1C,
+ 0xD7D3, 0x7DBE, 0xD7D4, 0x83F1, 0xD7D5, 0x9675, 0xD7D6, 0x4FDA, 0xD7D7, 0x5229, 0xD7D8, 0x5398, 0xD7D9, 0x540F, 0xD7DA, 0x550E,
+ 0xD7DB, 0x5C65, 0xD7DC, 0x60A7, 0xD7DD, 0x674E, 0xD7DE, 0x68A8, 0xD7DF, 0x6D6C, 0xD7E0, 0x7281, 0xD7E1, 0x72F8, 0xD7E2, 0x7406,
+ 0xD7E3, 0x7483, 0xD7E4, 0xF962, 0xD7E5, 0x75E2, 0xD7E6, 0x7C6C, 0xD7E7, 0x7F79, 0xD7E8, 0x7FB8, 0xD7E9, 0x8389, 0xD7EA, 0x88CF,
+ 0xD7EB, 0x88E1, 0xD7EC, 0x91CC, 0xD7ED, 0x91D0, 0xD7EE, 0x96E2, 0xD7EF, 0x9BC9, 0xD7F0, 0x541D, 0xD7F1, 0x6F7E, 0xD7F2, 0x71D0,
+ 0xD7F3, 0x7498, 0xD7F4, 0x85FA, 0xD7F5, 0x8EAA, 0xD7F6, 0x96A3, 0xD7F7, 0x9C57, 0xD7F8, 0x9E9F, 0xD7F9, 0x6797, 0xD7FA, 0x6DCB,
+ 0xD7FB, 0x7433, 0xD7FC, 0x81E8, 0xD7FD, 0x9716, 0xD7FE, 0x782C, 0xD8A1, 0x7ACB, 0xD8A2, 0x7B20, 0xD8A3, 0x7C92, 0xD8A4, 0x6469,
+ 0xD8A5, 0x746A, 0xD8A6, 0x75F2, 0xD8A7, 0x78BC, 0xD8A8, 0x78E8, 0xD8A9, 0x99AC, 0xD8AA, 0x9B54, 0xD8AB, 0x9EBB, 0xD8AC, 0x5BDE,
+ 0xD8AD, 0x5E55, 0xD8AE, 0x6F20, 0xD8AF, 0x819C, 0xD8B0, 0x83AB, 0xD8B1, 0x9088, 0xD8B2, 0x4E07, 0xD8B3, 0x534D, 0xD8B4, 0x5A29,
+ 0xD8B5, 0x5DD2, 0xD8B6, 0x5F4E, 0xD8B7, 0x6162, 0xD8B8, 0x633D, 0xD8B9, 0x6669, 0xD8BA, 0x66FC, 0xD8BB, 0x6EFF, 0xD8BC, 0x6F2B,
+ 0xD8BD, 0x7063, 0xD8BE, 0x779E, 0xD8BF, 0x842C, 0xD8C0, 0x8513, 0xD8C1, 0x883B, 0xD8C2, 0x8F13, 0xD8C3, 0x9945, 0xD8C4, 0x9C3B,
+ 0xD8C5, 0x551C, 0xD8C6, 0x62B9, 0xD8C7, 0x672B, 0xD8C8, 0x6CAB, 0xD8C9, 0x8309, 0xD8CA, 0x896A, 0xD8CB, 0x977A, 0xD8CC, 0x4EA1,
+ 0xD8CD, 0x5984, 0xD8CE, 0x5FD8, 0xD8CF, 0x5FD9, 0xD8D0, 0x671B, 0xD8D1, 0x7DB2, 0xD8D2, 0x7F54, 0xD8D3, 0x8292, 0xD8D4, 0x832B,
+ 0xD8D5, 0x83BD, 0xD8D6, 0x8F1E, 0xD8D7, 0x9099, 0xD8D8, 0x57CB, 0xD8D9, 0x59B9, 0xD8DA, 0x5A92, 0xD8DB, 0x5BD0, 0xD8DC, 0x6627,
+ 0xD8DD, 0x679A, 0xD8DE, 0x6885, 0xD8DF, 0x6BCF, 0xD8E0, 0x7164, 0xD8E1, 0x7F75, 0xD8E2, 0x8CB7, 0xD8E3, 0x8CE3, 0xD8E4, 0x9081,
+ 0xD8E5, 0x9B45, 0xD8E6, 0x8108, 0xD8E7, 0x8C8A, 0xD8E8, 0x964C, 0xD8E9, 0x9A40, 0xD8EA, 0x9EA5, 0xD8EB, 0x5B5F, 0xD8EC, 0x6C13,
+ 0xD8ED, 0x731B, 0xD8EE, 0x76F2, 0xD8EF, 0x76DF, 0xD8F0, 0x840C, 0xD8F1, 0x51AA, 0xD8F2, 0x8993, 0xD8F3, 0x514D, 0xD8F4, 0x5195,
+ 0xD8F5, 0x52C9, 0xD8F6, 0x68C9, 0xD8F7, 0x6C94, 0xD8F8, 0x7704, 0xD8F9, 0x7720, 0xD8FA, 0x7DBF, 0xD8FB, 0x7DEC, 0xD8FC, 0x9762,
+ 0xD8FD, 0x9EB5, 0xD8FE, 0x6EC5, 0xD9A1, 0x8511, 0xD9A2, 0x51A5, 0xD9A3, 0x540D, 0xD9A4, 0x547D, 0xD9A5, 0x660E, 0xD9A6, 0x669D,
+ 0xD9A7, 0x6927, 0xD9A8, 0x6E9F, 0xD9A9, 0x76BF, 0xD9AA, 0x7791, 0xD9AB, 0x8317, 0xD9AC, 0x84C2, 0xD9AD, 0x879F, 0xD9AE, 0x9169,
+ 0xD9AF, 0x9298, 0xD9B0, 0x9CF4, 0xD9B1, 0x8882, 0xD9B2, 0x4FAE, 0xD9B3, 0x5192, 0xD9B4, 0x52DF, 0xD9B5, 0x59C6, 0xD9B6, 0x5E3D,
+ 0xD9B7, 0x6155, 0xD9B8, 0x6478, 0xD9B9, 0x6479, 0xD9BA, 0x66AE, 0xD9BB, 0x67D0, 0xD9BC, 0x6A21, 0xD9BD, 0x6BCD, 0xD9BE, 0x6BDB,
+ 0xD9BF, 0x725F, 0xD9C0, 0x7261, 0xD9C1, 0x7441, 0xD9C2, 0x7738, 0xD9C3, 0x77DB, 0xD9C4, 0x8017, 0xD9C5, 0x82BC, 0xD9C6, 0x8305,
+ 0xD9C7, 0x8B00, 0xD9C8, 0x8B28, 0xD9C9, 0x8C8C, 0xD9CA, 0x6728, 0xD9CB, 0x6C90, 0xD9CC, 0x7267, 0xD9CD, 0x76EE, 0xD9CE, 0x7766,
+ 0xD9CF, 0x7A46, 0xD9D0, 0x9DA9, 0xD9D1, 0x6B7F, 0xD9D2, 0x6C92, 0xD9D3, 0x5922, 0xD9D4, 0x6726, 0xD9D5, 0x8499, 0xD9D6, 0x536F,
+ 0xD9D7, 0x5893, 0xD9D8, 0x5999, 0xD9D9, 0x5EDF, 0xD9DA, 0x63CF, 0xD9DB, 0x6634, 0xD9DC, 0x6773, 0xD9DD, 0x6E3A, 0xD9DE, 0x732B,
+ 0xD9DF, 0x7AD7, 0xD9E0, 0x82D7, 0xD9E1, 0x9328, 0xD9E2, 0x52D9, 0xD9E3, 0x5DEB, 0xD9E4, 0x61AE, 0xD9E5, 0x61CB, 0xD9E6, 0x620A,
+ 0xD9E7, 0x62C7, 0xD9E8, 0x64AB, 0xD9E9, 0x65E0, 0xD9EA, 0x6959, 0xD9EB, 0x6B66, 0xD9EC, 0x6BCB, 0xD9ED, 0x7121, 0xD9EE, 0x73F7,
+ 0xD9EF, 0x755D, 0xD9F0, 0x7E46, 0xD9F1, 0x821E, 0xD9F2, 0x8302, 0xD9F3, 0x856A, 0xD9F4, 0x8AA3, 0xD9F5, 0x8CBF, 0xD9F6, 0x9727,
+ 0xD9F7, 0x9D61, 0xD9F8, 0x58A8, 0xD9F9, 0x9ED8, 0xD9FA, 0x5011, 0xD9FB, 0x520E, 0xD9FC, 0x543B, 0xD9FD, 0x554F, 0xD9FE, 0x6587,
+ 0xDAA1, 0x6C76, 0xDAA2, 0x7D0A, 0xDAA3, 0x7D0B, 0xDAA4, 0x805E, 0xDAA5, 0x868A, 0xDAA6, 0x9580, 0xDAA7, 0x96EF, 0xDAA8, 0x52FF,
+ 0xDAA9, 0x6C95, 0xDAAA, 0x7269, 0xDAAB, 0x5473, 0xDAAC, 0x5A9A, 0xDAAD, 0x5C3E, 0xDAAE, 0x5D4B, 0xDAAF, 0x5F4C, 0xDAB0, 0x5FAE,
+ 0xDAB1, 0x672A, 0xDAB2, 0x68B6, 0xDAB3, 0x6963, 0xDAB4, 0x6E3C, 0xDAB5, 0x6E44, 0xDAB6, 0x7709, 0xDAB7, 0x7C73, 0xDAB8, 0x7F8E,
+ 0xDAB9, 0x8587, 0xDABA, 0x8B0E, 0xDABB, 0x8FF7, 0xDABC, 0x9761, 0xDABD, 0x9EF4, 0xDABE, 0x5CB7, 0xDABF, 0x60B6, 0xDAC0, 0x610D,
+ 0xDAC1, 0x61AB, 0xDAC2, 0x654F, 0xDAC3, 0x65FB, 0xDAC4, 0x65FC, 0xDAC5, 0x6C11, 0xDAC6, 0x6CEF, 0xDAC7, 0x739F, 0xDAC8, 0x73C9,
+ 0xDAC9, 0x7DE1, 0xDACA, 0x9594, 0xDACB, 0x5BC6, 0xDACC, 0x871C, 0xDACD, 0x8B10, 0xDACE, 0x525D, 0xDACF, 0x535A, 0xDAD0, 0x62CD,
+ 0xDAD1, 0x640F, 0xDAD2, 0x64B2, 0xDAD3, 0x6734, 0xDAD4, 0x6A38, 0xDAD5, 0x6CCA, 0xDAD6, 0x73C0, 0xDAD7, 0x749E, 0xDAD8, 0x7B94,
+ 0xDAD9, 0x7C95, 0xDADA, 0x7E1B, 0xDADB, 0x818A, 0xDADC, 0x8236, 0xDADD, 0x8584, 0xDADE, 0x8FEB, 0xDADF, 0x96F9, 0xDAE0, 0x99C1,
+ 0xDAE1, 0x4F34, 0xDAE2, 0x534A, 0xDAE3, 0x53CD, 0xDAE4, 0x53DB, 0xDAE5, 0x62CC, 0xDAE6, 0x642C, 0xDAE7, 0x6500, 0xDAE8, 0x6591,
+ 0xDAE9, 0x69C3, 0xDAEA, 0x6CEE, 0xDAEB, 0x6F58, 0xDAEC, 0x73ED, 0xDAED, 0x7554, 0xDAEE, 0x7622, 0xDAEF, 0x76E4, 0xDAF0, 0x76FC,
+ 0xDAF1, 0x78D0, 0xDAF2, 0x78FB, 0xDAF3, 0x792C, 0xDAF4, 0x7D46, 0xDAF5, 0x822C, 0xDAF6, 0x87E0, 0xDAF7, 0x8FD4, 0xDAF8, 0x9812,
+ 0xDAF9, 0x98EF, 0xDAFA, 0x52C3, 0xDAFB, 0x62D4, 0xDAFC, 0x64A5, 0xDAFD, 0x6E24, 0xDAFE, 0x6F51, 0xDBA1, 0x767C, 0xDBA2, 0x8DCB,
+ 0xDBA3, 0x91B1, 0xDBA4, 0x9262, 0xDBA5, 0x9AEE, 0xDBA6, 0x9B43, 0xDBA7, 0x5023, 0xDBA8, 0x508D, 0xDBA9, 0x574A, 0xDBAA, 0x59A8,
+ 0xDBAB, 0x5C28, 0xDBAC, 0x5E47, 0xDBAD, 0x5F77, 0xDBAE, 0x623F, 0xDBAF, 0x653E, 0xDBB0, 0x65B9, 0xDBB1, 0x65C1, 0xDBB2, 0x6609,
+ 0xDBB3, 0x678B, 0xDBB4, 0x699C, 0xDBB5, 0x6EC2, 0xDBB6, 0x78C5, 0xDBB7, 0x7D21, 0xDBB8, 0x80AA, 0xDBB9, 0x8180, 0xDBBA, 0x822B,
+ 0xDBBB, 0x82B3, 0xDBBC, 0x84A1, 0xDBBD, 0x868C, 0xDBBE, 0x8A2A, 0xDBBF, 0x8B17, 0xDBC0, 0x90A6, 0xDBC1, 0x9632, 0xDBC2, 0x9F90,
+ 0xDBC3, 0x500D, 0xDBC4, 0x4FF3, 0xDBC5, 0xF963, 0xDBC6, 0x57F9, 0xDBC7, 0x5F98, 0xDBC8, 0x62DC, 0xDBC9, 0x6392, 0xDBCA, 0x676F,
+ 0xDBCB, 0x6E43, 0xDBCC, 0x7119, 0xDBCD, 0x76C3, 0xDBCE, 0x80CC, 0xDBCF, 0x80DA, 0xDBD0, 0x88F4, 0xDBD1, 0x88F5, 0xDBD2, 0x8919,
+ 0xDBD3, 0x8CE0, 0xDBD4, 0x8F29, 0xDBD5, 0x914D, 0xDBD6, 0x966A, 0xDBD7, 0x4F2F, 0xDBD8, 0x4F70, 0xDBD9, 0x5E1B, 0xDBDA, 0x67CF,
+ 0xDBDB, 0x6822, 0xDBDC, 0x767D, 0xDBDD, 0x767E, 0xDBDE, 0x9B44, 0xDBDF, 0x5E61, 0xDBE0, 0x6A0A, 0xDBE1, 0x7169, 0xDBE2, 0x71D4,
+ 0xDBE3, 0x756A, 0xDBE4, 0xF964, 0xDBE5, 0x7E41, 0xDBE6, 0x8543, 0xDBE7, 0x85E9, 0xDBE8, 0x98DC, 0xDBE9, 0x4F10, 0xDBEA, 0x7B4F,
+ 0xDBEB, 0x7F70, 0xDBEC, 0x95A5, 0xDBED, 0x51E1, 0xDBEE, 0x5E06, 0xDBEF, 0x68B5, 0xDBF0, 0x6C3E, 0xDBF1, 0x6C4E, 0xDBF2, 0x6CDB,
+ 0xDBF3, 0x72AF, 0xDBF4, 0x7BC4, 0xDBF5, 0x8303, 0xDBF6, 0x6CD5, 0xDBF7, 0x743A, 0xDBF8, 0x50FB, 0xDBF9, 0x5288, 0xDBFA, 0x58C1,
+ 0xDBFB, 0x64D8, 0xDBFC, 0x6A97, 0xDBFD, 0x74A7, 0xDBFE, 0x7656, 0xDCA1, 0x78A7, 0xDCA2, 0x8617, 0xDCA3, 0x95E2, 0xDCA4, 0x9739,
+ 0xDCA5, 0xF965, 0xDCA6, 0x535E, 0xDCA7, 0x5F01, 0xDCA8, 0x8B8A, 0xDCA9, 0x8FA8, 0xDCAA, 0x8FAF, 0xDCAB, 0x908A, 0xDCAC, 0x5225,
+ 0xDCAD, 0x77A5, 0xDCAE, 0x9C49, 0xDCAF, 0x9F08, 0xDCB0, 0x4E19, 0xDCB1, 0x5002, 0xDCB2, 0x5175, 0xDCB3, 0x5C5B, 0xDCB4, 0x5E77,
+ 0xDCB5, 0x661E, 0xDCB6, 0x663A, 0xDCB7, 0x67C4, 0xDCB8, 0x68C5, 0xDCB9, 0x70B3, 0xDCBA, 0x7501, 0xDCBB, 0x75C5, 0xDCBC, 0x79C9,
+ 0xDCBD, 0x7ADD, 0xDCBE, 0x8F27, 0xDCBF, 0x9920, 0xDCC0, 0x9A08, 0xDCC1, 0x4FDD, 0xDCC2, 0x5821, 0xDCC3, 0x5831, 0xDCC4, 0x5BF6,
+ 0xDCC5, 0x666E, 0xDCC6, 0x6B65, 0xDCC7, 0x6D11, 0xDCC8, 0x6E7A, 0xDCC9, 0x6F7D, 0xDCCA, 0x73E4, 0xDCCB, 0x752B, 0xDCCC, 0x83E9,
+ 0xDCCD, 0x88DC, 0xDCCE, 0x8913, 0xDCCF, 0x8B5C, 0xDCD0, 0x8F14, 0xDCD1, 0x4F0F, 0xDCD2, 0x50D5, 0xDCD3, 0x5310, 0xDCD4, 0x535C,
+ 0xDCD5, 0x5B93, 0xDCD6, 0x5FA9, 0xDCD7, 0x670D, 0xDCD8, 0x798F, 0xDCD9, 0x8179, 0xDCDA, 0x832F, 0xDCDB, 0x8514, 0xDCDC, 0x8907,
+ 0xDCDD, 0x8986, 0xDCDE, 0x8F39, 0xDCDF, 0x8F3B, 0xDCE0, 0x99A5, 0xDCE1, 0x9C12, 0xDCE2, 0x672C, 0xDCE3, 0x4E76, 0xDCE4, 0x4FF8,
+ 0xDCE5, 0x5949, 0xDCE6, 0x5C01, 0xDCE7, 0x5CEF, 0xDCE8, 0x5CF0, 0xDCE9, 0x6367, 0xDCEA, 0x68D2, 0xDCEB, 0x70FD, 0xDCEC, 0x71A2,
+ 0xDCED, 0x742B, 0xDCEE, 0x7E2B, 0xDCEF, 0x84EC, 0xDCF0, 0x8702, 0xDCF1, 0x9022, 0xDCF2, 0x92D2, 0xDCF3, 0x9CF3, 0xDCF4, 0x4E0D,
+ 0xDCF5, 0x4ED8, 0xDCF6, 0x4FEF, 0xDCF7, 0x5085, 0xDCF8, 0x5256, 0xDCF9, 0x526F, 0xDCFA, 0x5426, 0xDCFB, 0x5490, 0xDCFC, 0x57E0,
+ 0xDCFD, 0x592B, 0xDCFE, 0x5A66, 0xDDA1, 0x5B5A, 0xDDA2, 0x5B75, 0xDDA3, 0x5BCC, 0xDDA4, 0x5E9C, 0xDDA5, 0xF966, 0xDDA6, 0x6276,
+ 0xDDA7, 0x6577, 0xDDA8, 0x65A7, 0xDDA9, 0x6D6E, 0xDDAA, 0x6EA5, 0xDDAB, 0x7236, 0xDDAC, 0x7B26, 0xDDAD, 0x7C3F, 0xDDAE, 0x7F36,
+ 0xDDAF, 0x8150, 0xDDB0, 0x8151, 0xDDB1, 0x819A, 0xDDB2, 0x8240, 0xDDB3, 0x8299, 0xDDB4, 0x83A9, 0xDDB5, 0x8A03, 0xDDB6, 0x8CA0,
+ 0xDDB7, 0x8CE6, 0xDDB8, 0x8CFB, 0xDDB9, 0x8D74, 0xDDBA, 0x8DBA, 0xDDBB, 0x90E8, 0xDDBC, 0x91DC, 0xDDBD, 0x961C, 0xDDBE, 0x9644,
+ 0xDDBF, 0x99D9, 0xDDC0, 0x9CE7, 0xDDC1, 0x5317, 0xDDC2, 0x5206, 0xDDC3, 0x5429, 0xDDC4, 0x5674, 0xDDC5, 0x58B3, 0xDDC6, 0x5954,
+ 0xDDC7, 0x596E, 0xDDC8, 0x5FFF, 0xDDC9, 0x61A4, 0xDDCA, 0x626E, 0xDDCB, 0x6610, 0xDDCC, 0x6C7E, 0xDDCD, 0x711A, 0xDDCE, 0x76C6,
+ 0xDDCF, 0x7C89, 0xDDD0, 0x7CDE, 0xDDD1, 0x7D1B, 0xDDD2, 0x82AC, 0xDDD3, 0x8CC1, 0xDDD4, 0x96F0, 0xDDD5, 0xF967, 0xDDD6, 0x4F5B,
+ 0xDDD7, 0x5F17, 0xDDD8, 0x5F7F, 0xDDD9, 0x62C2, 0xDDDA, 0x5D29, 0xDDDB, 0x670B, 0xDDDC, 0x68DA, 0xDDDD, 0x787C, 0xDDDE, 0x7E43,
+ 0xDDDF, 0x9D6C, 0xDDE0, 0x4E15, 0xDDE1, 0x5099, 0xDDE2, 0x5315, 0xDDE3, 0x532A, 0xDDE4, 0x5351, 0xDDE5, 0x5983, 0xDDE6, 0x5A62,
+ 0xDDE7, 0x5E87, 0xDDE8, 0x60B2, 0xDDE9, 0x618A, 0xDDEA, 0x6249, 0xDDEB, 0x6279, 0xDDEC, 0x6590, 0xDDED, 0x6787, 0xDDEE, 0x69A7,
+ 0xDDEF, 0x6BD4, 0xDDF0, 0x6BD6, 0xDDF1, 0x6BD7, 0xDDF2, 0x6BD8, 0xDDF3, 0x6CB8, 0xDDF4, 0xF968, 0xDDF5, 0x7435, 0xDDF6, 0x75FA,
+ 0xDDF7, 0x7812, 0xDDF8, 0x7891, 0xDDF9, 0x79D5, 0xDDFA, 0x79D8, 0xDDFB, 0x7C83, 0xDDFC, 0x7DCB, 0xDDFD, 0x7FE1, 0xDDFE, 0x80A5,
+ 0xDEA1, 0x813E, 0xDEA2, 0x81C2, 0xDEA3, 0x83F2, 0xDEA4, 0x871A, 0xDEA5, 0x88E8, 0xDEA6, 0x8AB9, 0xDEA7, 0x8B6C, 0xDEA8, 0x8CBB,
+ 0xDEA9, 0x9119, 0xDEAA, 0x975E, 0xDEAB, 0x98DB, 0xDEAC, 0x9F3B, 0xDEAD, 0x56AC, 0xDEAE, 0x5B2A, 0xDEAF, 0x5F6C, 0xDEB0, 0x658C,
+ 0xDEB1, 0x6AB3, 0xDEB2, 0x6BAF, 0xDEB3, 0x6D5C, 0xDEB4, 0x6FF1, 0xDEB5, 0x7015, 0xDEB6, 0x725D, 0xDEB7, 0x73AD, 0xDEB8, 0x8CA7,
+ 0xDEB9, 0x8CD3, 0xDEBA, 0x983B, 0xDEBB, 0x6191, 0xDEBC, 0x6C37, 0xDEBD, 0x8058, 0xDEBE, 0x9A01, 0xDEBF, 0x4E4D, 0xDEC0, 0x4E8B,
+ 0xDEC1, 0x4E9B, 0xDEC2, 0x4ED5, 0xDEC3, 0x4F3A, 0xDEC4, 0x4F3C, 0xDEC5, 0x4F7F, 0xDEC6, 0x4FDF, 0xDEC7, 0x50FF, 0xDEC8, 0x53F2,
+ 0xDEC9, 0x53F8, 0xDECA, 0x5506, 0xDECB, 0x55E3, 0xDECC, 0x56DB, 0xDECD, 0x58EB, 0xDECE, 0x5962, 0xDECF, 0x5A11, 0xDED0, 0x5BEB,
+ 0xDED1, 0x5BFA, 0xDED2, 0x5C04, 0xDED3, 0x5DF3, 0xDED4, 0x5E2B, 0xDED5, 0x5F99, 0xDED6, 0x601D, 0xDED7, 0x6368, 0xDED8, 0x659C,
+ 0xDED9, 0x65AF, 0xDEDA, 0x67F6, 0xDEDB, 0x67FB, 0xDEDC, 0x68AD, 0xDEDD, 0x6B7B, 0xDEDE, 0x6C99, 0xDEDF, 0x6CD7, 0xDEE0, 0x6E23,
+ 0xDEE1, 0x7009, 0xDEE2, 0x7345, 0xDEE3, 0x7802, 0xDEE4, 0x793E, 0xDEE5, 0x7940, 0xDEE6, 0x7960, 0xDEE7, 0x79C1, 0xDEE8, 0x7BE9,
+ 0xDEE9, 0x7D17, 0xDEEA, 0x7D72, 0xDEEB, 0x8086, 0xDEEC, 0x820D, 0xDEED, 0x838E, 0xDEEE, 0x84D1, 0xDEEF, 0x86C7, 0xDEF0, 0x88DF,
+ 0xDEF1, 0x8A50, 0xDEF2, 0x8A5E, 0xDEF3, 0x8B1D, 0xDEF4, 0x8CDC, 0xDEF5, 0x8D66, 0xDEF6, 0x8FAD, 0xDEF7, 0x90AA, 0xDEF8, 0x98FC,
+ 0xDEF9, 0x99DF, 0xDEFA, 0x9E9D, 0xDEFB, 0x524A, 0xDEFC, 0xF969, 0xDEFD, 0x6714, 0xDEFE, 0xF96A, 0xDFA1, 0x5098, 0xDFA2, 0x522A,
+ 0xDFA3, 0x5C71, 0xDFA4, 0x6563, 0xDFA5, 0x6C55, 0xDFA6, 0x73CA, 0xDFA7, 0x7523, 0xDFA8, 0x759D, 0xDFA9, 0x7B97, 0xDFAA, 0x849C,
+ 0xDFAB, 0x9178, 0xDFAC, 0x9730, 0xDFAD, 0x4E77, 0xDFAE, 0x6492, 0xDFAF, 0x6BBA, 0xDFB0, 0x715E, 0xDFB1, 0x85A9, 0xDFB2, 0x4E09,
+ 0xDFB3, 0xF96B, 0xDFB4, 0x6749, 0xDFB5, 0x68EE, 0xDFB6, 0x6E17, 0xDFB7, 0x829F, 0xDFB8, 0x8518, 0xDFB9, 0x886B, 0xDFBA, 0x63F7,
+ 0xDFBB, 0x6F81, 0xDFBC, 0x9212, 0xDFBD, 0x98AF, 0xDFBE, 0x4E0A, 0xDFBF, 0x50B7, 0xDFC0, 0x50CF, 0xDFC1, 0x511F, 0xDFC2, 0x5546,
+ 0xDFC3, 0x55AA, 0xDFC4, 0x5617, 0xDFC5, 0x5B40, 0xDFC6, 0x5C19, 0xDFC7, 0x5CE0, 0xDFC8, 0x5E38, 0xDFC9, 0x5E8A, 0xDFCA, 0x5EA0,
+ 0xDFCB, 0x5EC2, 0xDFCC, 0x60F3, 0xDFCD, 0x6851, 0xDFCE, 0x6A61, 0xDFCF, 0x6E58, 0xDFD0, 0x723D, 0xDFD1, 0x7240, 0xDFD2, 0x72C0,
+ 0xDFD3, 0x76F8, 0xDFD4, 0x7965, 0xDFD5, 0x7BB1, 0xDFD6, 0x7FD4, 0xDFD7, 0x88F3, 0xDFD8, 0x89F4, 0xDFD9, 0x8A73, 0xDFDA, 0x8C61,
+ 0xDFDB, 0x8CDE, 0xDFDC, 0x971C, 0xDFDD, 0x585E, 0xDFDE, 0x74BD, 0xDFDF, 0x8CFD, 0xDFE0, 0x55C7, 0xDFE1, 0xF96C, 0xDFE2, 0x7A61,
+ 0xDFE3, 0x7D22, 0xDFE4, 0x8272, 0xDFE5, 0x7272, 0xDFE6, 0x751F, 0xDFE7, 0x7525, 0xDFE8, 0xF96D, 0xDFE9, 0x7B19, 0xDFEA, 0x5885,
+ 0xDFEB, 0x58FB, 0xDFEC, 0x5DBC, 0xDFED, 0x5E8F, 0xDFEE, 0x5EB6, 0xDFEF, 0x5F90, 0xDFF0, 0x6055, 0xDFF1, 0x6292, 0xDFF2, 0x637F,
+ 0xDFF3, 0x654D, 0xDFF4, 0x6691, 0xDFF5, 0x66D9, 0xDFF6, 0x66F8, 0xDFF7, 0x6816, 0xDFF8, 0x68F2, 0xDFF9, 0x7280, 0xDFFA, 0x745E,
+ 0xDFFB, 0x7B6E, 0xDFFC, 0x7D6E, 0xDFFD, 0x7DD6, 0xDFFE, 0x7F72, 0xE0A1, 0x80E5, 0xE0A2, 0x8212, 0xE0A3, 0x85AF, 0xE0A4, 0x897F,
+ 0xE0A5, 0x8A93, 0xE0A6, 0x901D, 0xE0A7, 0x92E4, 0xE0A8, 0x9ECD, 0xE0A9, 0x9F20, 0xE0AA, 0x5915, 0xE0AB, 0x596D, 0xE0AC, 0x5E2D,
+ 0xE0AD, 0x60DC, 0xE0AE, 0x6614, 0xE0AF, 0x6673, 0xE0B0, 0x6790, 0xE0B1, 0x6C50, 0xE0B2, 0x6DC5, 0xE0B3, 0x6F5F, 0xE0B4, 0x77F3,
+ 0xE0B5, 0x78A9, 0xE0B6, 0x84C6, 0xE0B7, 0x91CB, 0xE0B8, 0x932B, 0xE0B9, 0x4ED9, 0xE0BA, 0x50CA, 0xE0BB, 0x5148, 0xE0BC, 0x5584,
+ 0xE0BD, 0x5B0B, 0xE0BE, 0x5BA3, 0xE0BF, 0x6247, 0xE0C0, 0x657E, 0xE0C1, 0x65CB, 0xE0C2, 0x6E32, 0xE0C3, 0x717D, 0xE0C4, 0x7401,
+ 0xE0C5, 0x7444, 0xE0C6, 0x7487, 0xE0C7, 0x74BF, 0xE0C8, 0x766C, 0xE0C9, 0x79AA, 0xE0CA, 0x7DDA, 0xE0CB, 0x7E55, 0xE0CC, 0x7FA8,
+ 0xE0CD, 0x817A, 0xE0CE, 0x81B3, 0xE0CF, 0x8239, 0xE0D0, 0x861A, 0xE0D1, 0x87EC, 0xE0D2, 0x8A75, 0xE0D3, 0x8DE3, 0xE0D4, 0x9078,
+ 0xE0D5, 0x9291, 0xE0D6, 0x9425, 0xE0D7, 0x994D, 0xE0D8, 0x9BAE, 0xE0D9, 0x5368, 0xE0DA, 0x5C51, 0xE0DB, 0x6954, 0xE0DC, 0x6CC4,
+ 0xE0DD, 0x6D29, 0xE0DE, 0x6E2B, 0xE0DF, 0x820C, 0xE0E0, 0x859B, 0xE0E1, 0x893B, 0xE0E2, 0x8A2D, 0xE0E3, 0x8AAA, 0xE0E4, 0x96EA,
+ 0xE0E5, 0x9F67, 0xE0E6, 0x5261, 0xE0E7, 0x66B9, 0xE0E8, 0x6BB2, 0xE0E9, 0x7E96, 0xE0EA, 0x87FE, 0xE0EB, 0x8D0D, 0xE0EC, 0x9583,
+ 0xE0ED, 0x965D, 0xE0EE, 0x651D, 0xE0EF, 0x6D89, 0xE0F0, 0x71EE, 0xE0F1, 0xF96E, 0xE0F2, 0x57CE, 0xE0F3, 0x59D3, 0xE0F4, 0x5BAC,
+ 0xE0F5, 0x6027, 0xE0F6, 0x60FA, 0xE0F7, 0x6210, 0xE0F8, 0x661F, 0xE0F9, 0x665F, 0xE0FA, 0x7329, 0xE0FB, 0x73F9, 0xE0FC, 0x76DB,
+ 0xE0FD, 0x7701, 0xE0FE, 0x7B6C, 0xE1A1, 0x8056, 0xE1A2, 0x8072, 0xE1A3, 0x8165, 0xE1A4, 0x8AA0, 0xE1A5, 0x9192, 0xE1A6, 0x4E16,
+ 0xE1A7, 0x52E2, 0xE1A8, 0x6B72, 0xE1A9, 0x6D17, 0xE1AA, 0x7A05, 0xE1AB, 0x7B39, 0xE1AC, 0x7D30, 0xE1AD, 0xF96F, 0xE1AE, 0x8CB0,
+ 0xE1AF, 0x53EC, 0xE1B0, 0x562F, 0xE1B1, 0x5851, 0xE1B2, 0x5BB5, 0xE1B3, 0x5C0F, 0xE1B4, 0x5C11, 0xE1B5, 0x5DE2, 0xE1B6, 0x6240,
+ 0xE1B7, 0x6383, 0xE1B8, 0x6414, 0xE1B9, 0x662D, 0xE1BA, 0x68B3, 0xE1BB, 0x6CBC, 0xE1BC, 0x6D88, 0xE1BD, 0x6EAF, 0xE1BE, 0x701F,
+ 0xE1BF, 0x70A4, 0xE1C0, 0x71D2, 0xE1C1, 0x7526, 0xE1C2, 0x758F, 0xE1C3, 0x758E, 0xE1C4, 0x7619, 0xE1C5, 0x7B11, 0xE1C6, 0x7BE0,
+ 0xE1C7, 0x7C2B, 0xE1C8, 0x7D20, 0xE1C9, 0x7D39, 0xE1CA, 0x852C, 0xE1CB, 0x856D, 0xE1CC, 0x8607, 0xE1CD, 0x8A34, 0xE1CE, 0x900D,
+ 0xE1CF, 0x9061, 0xE1D0, 0x90B5, 0xE1D1, 0x92B7, 0xE1D2, 0x97F6, 0xE1D3, 0x9A37, 0xE1D4, 0x4FD7, 0xE1D5, 0x5C6C, 0xE1D6, 0x675F,
+ 0xE1D7, 0x6D91, 0xE1D8, 0x7C9F, 0xE1D9, 0x7E8C, 0xE1DA, 0x8B16, 0xE1DB, 0x8D16, 0xE1DC, 0x901F, 0xE1DD, 0x5B6B, 0xE1DE, 0x5DFD,
+ 0xE1DF, 0x640D, 0xE1E0, 0x84C0, 0xE1E1, 0x905C, 0xE1E2, 0x98E1, 0xE1E3, 0x7387, 0xE1E4, 0x5B8B, 0xE1E5, 0x609A, 0xE1E6, 0x677E,
+ 0xE1E7, 0x6DDE, 0xE1E8, 0x8A1F, 0xE1E9, 0x8AA6, 0xE1EA, 0x9001, 0xE1EB, 0x980C, 0xE1EC, 0x5237, 0xE1ED, 0xF970, 0xE1EE, 0x7051,
+ 0xE1EF, 0x788E, 0xE1F0, 0x9396, 0xE1F1, 0x8870, 0xE1F2, 0x91D7, 0xE1F3, 0x4FEE, 0xE1F4, 0x53D7, 0xE1F5, 0x55FD, 0xE1F6, 0x56DA,
+ 0xE1F7, 0x5782, 0xE1F8, 0x58FD, 0xE1F9, 0x5AC2, 0xE1FA, 0x5B88, 0xE1FB, 0x5CAB, 0xE1FC, 0x5CC0, 0xE1FD, 0x5E25, 0xE1FE, 0x6101,
+ 0xE2A1, 0x620D, 0xE2A2, 0x624B, 0xE2A3, 0x6388, 0xE2A4, 0x641C, 0xE2A5, 0x6536, 0xE2A6, 0x6578, 0xE2A7, 0x6A39, 0xE2A8, 0x6B8A,
+ 0xE2A9, 0x6C34, 0xE2AA, 0x6D19, 0xE2AB, 0x6F31, 0xE2AC, 0x71E7, 0xE2AD, 0x72E9, 0xE2AE, 0x7378, 0xE2AF, 0x7407, 0xE2B0, 0x74B2,
+ 0xE2B1, 0x7626, 0xE2B2, 0x7761, 0xE2B3, 0x79C0, 0xE2B4, 0x7A57, 0xE2B5, 0x7AEA, 0xE2B6, 0x7CB9, 0xE2B7, 0x7D8F, 0xE2B8, 0x7DAC,
+ 0xE2B9, 0x7E61, 0xE2BA, 0x7F9E, 0xE2BB, 0x8129, 0xE2BC, 0x8331, 0xE2BD, 0x8490, 0xE2BE, 0x84DA, 0xE2BF, 0x85EA, 0xE2C0, 0x8896,
+ 0xE2C1, 0x8AB0, 0xE2C2, 0x8B90, 0xE2C3, 0x8F38, 0xE2C4, 0x9042, 0xE2C5, 0x9083, 0xE2C6, 0x916C, 0xE2C7, 0x9296, 0xE2C8, 0x92B9,
+ 0xE2C9, 0x968B, 0xE2CA, 0x96A7, 0xE2CB, 0x96A8, 0xE2CC, 0x96D6, 0xE2CD, 0x9700, 0xE2CE, 0x9808, 0xE2CF, 0x9996, 0xE2D0, 0x9AD3,
+ 0xE2D1, 0x9B1A, 0xE2D2, 0x53D4, 0xE2D3, 0x587E, 0xE2D4, 0x5919, 0xE2D5, 0x5B70, 0xE2D6, 0x5BBF, 0xE2D7, 0x6DD1, 0xE2D8, 0x6F5A,
+ 0xE2D9, 0x719F, 0xE2DA, 0x7421, 0xE2DB, 0x74B9, 0xE2DC, 0x8085, 0xE2DD, 0x83FD, 0xE2DE, 0x5DE1, 0xE2DF, 0x5F87, 0xE2E0, 0x5FAA,
+ 0xE2E1, 0x6042, 0xE2E2, 0x65EC, 0xE2E3, 0x6812, 0xE2E4, 0x696F, 0xE2E5, 0x6A53, 0xE2E6, 0x6B89, 0xE2E7, 0x6D35, 0xE2E8, 0x6DF3,
+ 0xE2E9, 0x73E3, 0xE2EA, 0x76FE, 0xE2EB, 0x77AC, 0xE2EC, 0x7B4D, 0xE2ED, 0x7D14, 0xE2EE, 0x8123, 0xE2EF, 0x821C, 0xE2F0, 0x8340,
+ 0xE2F1, 0x84F4, 0xE2F2, 0x8563, 0xE2F3, 0x8A62, 0xE2F4, 0x8AC4, 0xE2F5, 0x9187, 0xE2F6, 0x931E, 0xE2F7, 0x9806, 0xE2F8, 0x99B4,
+ 0xE2F9, 0x620C, 0xE2FA, 0x8853, 0xE2FB, 0x8FF0, 0xE2FC, 0x9265, 0xE2FD, 0x5D07, 0xE2FE, 0x5D27, 0xE3A1, 0x5D69, 0xE3A2, 0x745F,
+ 0xE3A3, 0x819D, 0xE3A4, 0x8768, 0xE3A5, 0x6FD5, 0xE3A6, 0x62FE, 0xE3A7, 0x7FD2, 0xE3A8, 0x8936, 0xE3A9, 0x8972, 0xE3AA, 0x4E1E,
+ 0xE3AB, 0x4E58, 0xE3AC, 0x50E7, 0xE3AD, 0x52DD, 0xE3AE, 0x5347, 0xE3AF, 0x627F, 0xE3B0, 0x6607, 0xE3B1, 0x7E69, 0xE3B2, 0x8805,
+ 0xE3B3, 0x965E, 0xE3B4, 0x4F8D, 0xE3B5, 0x5319, 0xE3B6, 0x5636, 0xE3B7, 0x59CB, 0xE3B8, 0x5AA4, 0xE3B9, 0x5C38, 0xE3BA, 0x5C4E,
+ 0xE3BB, 0x5C4D, 0xE3BC, 0x5E02, 0xE3BD, 0x5F11, 0xE3BE, 0x6043, 0xE3BF, 0x65BD, 0xE3C0, 0x662F, 0xE3C1, 0x6642, 0xE3C2, 0x67BE,
+ 0xE3C3, 0x67F4, 0xE3C4, 0x731C, 0xE3C5, 0x77E2, 0xE3C6, 0x793A, 0xE3C7, 0x7FC5, 0xE3C8, 0x8494, 0xE3C9, 0x84CD, 0xE3CA, 0x8996,
+ 0xE3CB, 0x8A66, 0xE3CC, 0x8A69, 0xE3CD, 0x8AE1, 0xE3CE, 0x8C55, 0xE3CF, 0x8C7A, 0xE3D0, 0x57F4, 0xE3D1, 0x5BD4, 0xE3D2, 0x5F0F,
+ 0xE3D3, 0x606F, 0xE3D4, 0x62ED, 0xE3D5, 0x690D, 0xE3D6, 0x6B96, 0xE3D7, 0x6E5C, 0xE3D8, 0x7184, 0xE3D9, 0x7BD2, 0xE3DA, 0x8755,
+ 0xE3DB, 0x8B58, 0xE3DC, 0x8EFE, 0xE3DD, 0x98DF, 0xE3DE, 0x98FE, 0xE3DF, 0x4F38, 0xE3E0, 0x4F81, 0xE3E1, 0x4FE1, 0xE3E2, 0x547B,
+ 0xE3E3, 0x5A20, 0xE3E4, 0x5BB8, 0xE3E5, 0x613C, 0xE3E6, 0x65B0, 0xE3E7, 0x6668, 0xE3E8, 0x71FC, 0xE3E9, 0x7533, 0xE3EA, 0x795E,
+ 0xE3EB, 0x7D33, 0xE3EC, 0x814E, 0xE3ED, 0x81E3, 0xE3EE, 0x8398, 0xE3EF, 0x85AA, 0xE3F0, 0x85CE, 0xE3F1, 0x8703, 0xE3F2, 0x8A0A,
+ 0xE3F3, 0x8EAB, 0xE3F4, 0x8F9B, 0xE3F5, 0xF971, 0xE3F6, 0x8FC5, 0xE3F7, 0x5931, 0xE3F8, 0x5BA4, 0xE3F9, 0x5BE6, 0xE3FA, 0x6089,
+ 0xE3FB, 0x5BE9, 0xE3FC, 0x5C0B, 0xE3FD, 0x5FC3, 0xE3FE, 0x6C81, 0xE4A1, 0xF972, 0xE4A2, 0x6DF1, 0xE4A3, 0x700B, 0xE4A4, 0x751A,
+ 0xE4A5, 0x82AF, 0xE4A6, 0x8AF6, 0xE4A7, 0x4EC0, 0xE4A8, 0x5341, 0xE4A9, 0xF973, 0xE4AA, 0x96D9, 0xE4AB, 0x6C0F, 0xE4AC, 0x4E9E,
+ 0xE4AD, 0x4FC4, 0xE4AE, 0x5152, 0xE4AF, 0x555E, 0xE4B0, 0x5A25, 0xE4B1, 0x5CE8, 0xE4B2, 0x6211, 0xE4B3, 0x7259, 0xE4B4, 0x82BD,
+ 0xE4B5, 0x83AA, 0xE4B6, 0x86FE, 0xE4B7, 0x8859, 0xE4B8, 0x8A1D, 0xE4B9, 0x963F, 0xE4BA, 0x96C5, 0xE4BB, 0x9913, 0xE4BC, 0x9D09,
+ 0xE4BD, 0x9D5D, 0xE4BE, 0x580A, 0xE4BF, 0x5CB3, 0xE4C0, 0x5DBD, 0xE4C1, 0x5E44, 0xE4C2, 0x60E1, 0xE4C3, 0x6115, 0xE4C4, 0x63E1,
+ 0xE4C5, 0x6A02, 0xE4C6, 0x6E25, 0xE4C7, 0x9102, 0xE4C8, 0x9354, 0xE4C9, 0x984E, 0xE4CA, 0x9C10, 0xE4CB, 0x9F77, 0xE4CC, 0x5B89,
+ 0xE4CD, 0x5CB8, 0xE4CE, 0x6309, 0xE4CF, 0x664F, 0xE4D0, 0x6848, 0xE4D1, 0x773C, 0xE4D2, 0x96C1, 0xE4D3, 0x978D, 0xE4D4, 0x9854,
+ 0xE4D5, 0x9B9F, 0xE4D6, 0x65A1, 0xE4D7, 0x8B01, 0xE4D8, 0x8ECB, 0xE4D9, 0x95BC, 0xE4DA, 0x5535, 0xE4DB, 0x5CA9, 0xE4DC, 0x5DD6,
+ 0xE4DD, 0x5EB5, 0xE4DE, 0x6697, 0xE4DF, 0x764C, 0xE4E0, 0x83F4, 0xE4E1, 0x95C7, 0xE4E2, 0x58D3, 0xE4E3, 0x62BC, 0xE4E4, 0x72CE,
+ 0xE4E5, 0x9D28, 0xE4E6, 0x4EF0, 0xE4E7, 0x592E, 0xE4E8, 0x600F, 0xE4E9, 0x663B, 0xE4EA, 0x6B83, 0xE4EB, 0x79E7, 0xE4EC, 0x9D26,
+ 0xE4ED, 0x5393, 0xE4EE, 0x54C0, 0xE4EF, 0x57C3, 0xE4F0, 0x5D16, 0xE4F1, 0x611B, 0xE4F2, 0x66D6, 0xE4F3, 0x6DAF, 0xE4F4, 0x788D,
+ 0xE4F5, 0x827E, 0xE4F6, 0x9698, 0xE4F7, 0x9744, 0xE4F8, 0x5384, 0xE4F9, 0x627C, 0xE4FA, 0x6396, 0xE4FB, 0x6DB2, 0xE4FC, 0x7E0A,
+ 0xE4FD, 0x814B, 0xE4FE, 0x984D, 0xE5A1, 0x6AFB, 0xE5A2, 0x7F4C, 0xE5A3, 0x9DAF, 0xE5A4, 0x9E1A, 0xE5A5, 0x4E5F, 0xE5A6, 0x503B,
+ 0xE5A7, 0x51B6, 0xE5A8, 0x591C, 0xE5A9, 0x60F9, 0xE5AA, 0x63F6, 0xE5AB, 0x6930, 0xE5AC, 0x723A, 0xE5AD, 0x8036, 0xE5AE, 0xF974,
+ 0xE5AF, 0x91CE, 0xE5B0, 0x5F31, 0xE5B1, 0xF975, 0xE5B2, 0xF976, 0xE5B3, 0x7D04, 0xE5B4, 0x82E5, 0xE5B5, 0x846F, 0xE5B6, 0x84BB,
+ 0xE5B7, 0x85E5, 0xE5B8, 0x8E8D, 0xE5B9, 0xF977, 0xE5BA, 0x4F6F, 0xE5BB, 0xF978, 0xE5BC, 0xF979, 0xE5BD, 0x58E4, 0xE5BE, 0x5B43,
+ 0xE5BF, 0x6059, 0xE5C0, 0x63DA, 0xE5C1, 0x6518, 0xE5C2, 0x656D, 0xE5C3, 0x6698, 0xE5C4, 0xF97A, 0xE5C5, 0x694A, 0xE5C6, 0x6A23,
+ 0xE5C7, 0x6D0B, 0xE5C8, 0x7001, 0xE5C9, 0x716C, 0xE5CA, 0x75D2, 0xE5CB, 0x760D, 0xE5CC, 0x79B3, 0xE5CD, 0x7A70, 0xE5CE, 0xF97B,
+ 0xE5CF, 0x7F8A, 0xE5D0, 0xF97C, 0xE5D1, 0x8944, 0xE5D2, 0xF97D, 0xE5D3, 0x8B93, 0xE5D4, 0x91C0, 0xE5D5, 0x967D, 0xE5D6, 0xF97E,
+ 0xE5D7, 0x990A, 0xE5D8, 0x5704, 0xE5D9, 0x5FA1, 0xE5DA, 0x65BC, 0xE5DB, 0x6F01, 0xE5DC, 0x7600, 0xE5DD, 0x79A6, 0xE5DE, 0x8A9E,
+ 0xE5DF, 0x99AD, 0xE5E0, 0x9B5A, 0xE5E1, 0x9F6C, 0xE5E2, 0x5104, 0xE5E3, 0x61B6, 0xE5E4, 0x6291, 0xE5E5, 0x6A8D, 0xE5E6, 0x81C6,
+ 0xE5E7, 0x5043, 0xE5E8, 0x5830, 0xE5E9, 0x5F66, 0xE5EA, 0x7109, 0xE5EB, 0x8A00, 0xE5EC, 0x8AFA, 0xE5ED, 0x5B7C, 0xE5EE, 0x8616,
+ 0xE5EF, 0x4FFA, 0xE5F0, 0x513C, 0xE5F1, 0x56B4, 0xE5F2, 0x5944, 0xE5F3, 0x63A9, 0xE5F4, 0x6DF9, 0xE5F5, 0x5DAA, 0xE5F6, 0x696D,
+ 0xE5F7, 0x5186, 0xE5F8, 0x4E88, 0xE5F9, 0x4F59, 0xE5FA, 0xF97F, 0xE5FB, 0xF980, 0xE5FC, 0xF981, 0xE5FD, 0x5982, 0xE5FE, 0xF982,
+ 0xE6A1, 0xF983, 0xE6A2, 0x6B5F, 0xE6A3, 0x6C5D, 0xE6A4, 0xF984, 0xE6A5, 0x74B5, 0xE6A6, 0x7916, 0xE6A7, 0xF985, 0xE6A8, 0x8207,
+ 0xE6A9, 0x8245, 0xE6AA, 0x8339, 0xE6AB, 0x8F3F, 0xE6AC, 0x8F5D, 0xE6AD, 0xF986, 0xE6AE, 0x9918, 0xE6AF, 0xF987, 0xE6B0, 0xF988,
+ 0xE6B1, 0xF989, 0xE6B2, 0x4EA6, 0xE6B3, 0xF98A, 0xE6B4, 0x57DF, 0xE6B5, 0x5F79, 0xE6B6, 0x6613, 0xE6B7, 0xF98B, 0xE6B8, 0xF98C,
+ 0xE6B9, 0x75AB, 0xE6BA, 0x7E79, 0xE6BB, 0x8B6F, 0xE6BC, 0xF98D, 0xE6BD, 0x9006, 0xE6BE, 0x9A5B, 0xE6BF, 0x56A5, 0xE6C0, 0x5827,
+ 0xE6C1, 0x59F8, 0xE6C2, 0x5A1F, 0xE6C3, 0x5BB4, 0xE6C4, 0xF98E, 0xE6C5, 0x5EF6, 0xE6C6, 0xF98F, 0xE6C7, 0xF990, 0xE6C8, 0x6350,
+ 0xE6C9, 0x633B, 0xE6CA, 0xF991, 0xE6CB, 0x693D, 0xE6CC, 0x6C87, 0xE6CD, 0x6CBF, 0xE6CE, 0x6D8E, 0xE6CF, 0x6D93, 0xE6D0, 0x6DF5,
+ 0xE6D1, 0x6F14, 0xE6D2, 0xF992, 0xE6D3, 0x70DF, 0xE6D4, 0x7136, 0xE6D5, 0x7159, 0xE6D6, 0xF993, 0xE6D7, 0x71C3, 0xE6D8, 0x71D5,
+ 0xE6D9, 0xF994, 0xE6DA, 0x784F, 0xE6DB, 0x786F, 0xE6DC, 0xF995, 0xE6DD, 0x7B75, 0xE6DE, 0x7DE3, 0xE6DF, 0xF996, 0xE6E0, 0x7E2F,
+ 0xE6E1, 0xF997, 0xE6E2, 0x884D, 0xE6E3, 0x8EDF, 0xE6E4, 0xF998, 0xE6E5, 0xF999, 0xE6E6, 0xF99A, 0xE6E7, 0x925B, 0xE6E8, 0xF99B,
+ 0xE6E9, 0x9CF6, 0xE6EA, 0xF99C, 0xE6EB, 0xF99D, 0xE6EC, 0xF99E, 0xE6ED, 0x6085, 0xE6EE, 0x6D85, 0xE6EF, 0xF99F, 0xE6F0, 0x71B1,
+ 0xE6F1, 0xF9A0, 0xE6F2, 0xF9A1, 0xE6F3, 0x95B1, 0xE6F4, 0x53AD, 0xE6F5, 0xF9A2, 0xE6F6, 0xF9A3, 0xE6F7, 0xF9A4, 0xE6F8, 0x67D3,
+ 0xE6F9, 0xF9A5, 0xE6FA, 0x708E, 0xE6FB, 0x7130, 0xE6FC, 0x7430, 0xE6FD, 0x8276, 0xE6FE, 0x82D2, 0xE7A1, 0xF9A6, 0xE7A2, 0x95BB,
+ 0xE7A3, 0x9AE5, 0xE7A4, 0x9E7D, 0xE7A5, 0x66C4, 0xE7A6, 0xF9A7, 0xE7A7, 0x71C1, 0xE7A8, 0x8449, 0xE7A9, 0xF9A8, 0xE7AA, 0xF9A9,
+ 0xE7AB, 0x584B, 0xE7AC, 0xF9AA, 0xE7AD, 0xF9AB, 0xE7AE, 0x5DB8, 0xE7AF, 0x5F71, 0xE7B0, 0xF9AC, 0xE7B1, 0x6620, 0xE7B2, 0x668E,
+ 0xE7B3, 0x6979, 0xE7B4, 0x69AE, 0xE7B5, 0x6C38, 0xE7B6, 0x6CF3, 0xE7B7, 0x6E36, 0xE7B8, 0x6F41, 0xE7B9, 0x6FDA, 0xE7BA, 0x701B,
+ 0xE7BB, 0x702F, 0xE7BC, 0x7150, 0xE7BD, 0x71DF, 0xE7BE, 0x7370, 0xE7BF, 0xF9AD, 0xE7C0, 0x745B, 0xE7C1, 0xF9AE, 0xE7C2, 0x74D4,
+ 0xE7C3, 0x76C8, 0xE7C4, 0x7A4E, 0xE7C5, 0x7E93, 0xE7C6, 0xF9AF, 0xE7C7, 0xF9B0, 0xE7C8, 0x82F1, 0xE7C9, 0x8A60, 0xE7CA, 0x8FCE,
+ 0xE7CB, 0xF9B1, 0xE7CC, 0x9348, 0xE7CD, 0xF9B2, 0xE7CE, 0x9719, 0xE7CF, 0xF9B3, 0xE7D0, 0xF9B4, 0xE7D1, 0x4E42, 0xE7D2, 0x502A,
+ 0xE7D3, 0xF9B5, 0xE7D4, 0x5208, 0xE7D5, 0x53E1, 0xE7D6, 0x66F3, 0xE7D7, 0x6C6D, 0xE7D8, 0x6FCA, 0xE7D9, 0x730A, 0xE7DA, 0x777F,
+ 0xE7DB, 0x7A62, 0xE7DC, 0x82AE, 0xE7DD, 0x85DD, 0xE7DE, 0x8602, 0xE7DF, 0xF9B6, 0xE7E0, 0x88D4, 0xE7E1, 0x8A63, 0xE7E2, 0x8B7D,
+ 0xE7E3, 0x8C6B, 0xE7E4, 0xF9B7, 0xE7E5, 0x92B3, 0xE7E6, 0xF9B8, 0xE7E7, 0x9713, 0xE7E8, 0x9810, 0xE7E9, 0x4E94, 0xE7EA, 0x4F0D,
+ 0xE7EB, 0x4FC9, 0xE7EC, 0x50B2, 0xE7ED, 0x5348, 0xE7EE, 0x543E, 0xE7EF, 0x5433, 0xE7F0, 0x55DA, 0xE7F1, 0x5862, 0xE7F2, 0x58BA,
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+ 0xEFB3, 0x96FB, 0xEFB4, 0x985A, 0xEFB5, 0x986B, 0xEFB6, 0x991E, 0xEFB7, 0x5207, 0xEFB8, 0x622A, 0xEFB9, 0x6298, 0xEFBA, 0x6D59,
+ 0xEFBB, 0x7664, 0xEFBC, 0x7ACA, 0xEFBD, 0x7BC0, 0xEFBE, 0x7D76, 0xEFBF, 0x5360, 0xEFC0, 0x5CBE, 0xEFC1, 0x5E97, 0xEFC2, 0x6F38,
+ 0xEFC3, 0x70B9, 0xEFC4, 0x7C98, 0xEFC5, 0x9711, 0xEFC6, 0x9B8E, 0xEFC7, 0x9EDE, 0xEFC8, 0x63A5, 0xEFC9, 0x647A, 0xEFCA, 0x8776,
+ 0xEFCB, 0x4E01, 0xEFCC, 0x4E95, 0xEFCD, 0x4EAD, 0xEFCE, 0x505C, 0xEFCF, 0x5075, 0xEFD0, 0x5448, 0xEFD1, 0x59C3, 0xEFD2, 0x5B9A,
+ 0xEFD3, 0x5E40, 0xEFD4, 0x5EAD, 0xEFD5, 0x5EF7, 0xEFD6, 0x5F81, 0xEFD7, 0x60C5, 0xEFD8, 0x633A, 0xEFD9, 0x653F, 0xEFDA, 0x6574,
+ 0xEFDB, 0x65CC, 0xEFDC, 0x6676, 0xEFDD, 0x6678, 0xEFDE, 0x67FE, 0xEFDF, 0x6968, 0xEFE0, 0x6A89, 0xEFE1, 0x6B63, 0xEFE2, 0x6C40,
+ 0xEFE3, 0x6DC0, 0xEFE4, 0x6DE8, 0xEFE5, 0x6E1F, 0xEFE6, 0x6E5E, 0xEFE7, 0x701E, 0xEFE8, 0x70A1, 0xEFE9, 0x738E, 0xEFEA, 0x73FD,
+ 0xEFEB, 0x753A, 0xEFEC, 0x775B, 0xEFED, 0x7887, 0xEFEE, 0x798E, 0xEFEF, 0x7A0B, 0xEFF0, 0x7A7D, 0xEFF1, 0x7CBE, 0xEFF2, 0x7D8E,
+ 0xEFF3, 0x8247, 0xEFF4, 0x8A02, 0xEFF5, 0x8AEA, 0xEFF6, 0x8C9E, 0xEFF7, 0x912D, 0xEFF8, 0x914A, 0xEFF9, 0x91D8, 0xEFFA, 0x9266,
+ 0xEFFB, 0x92CC, 0xEFFC, 0x9320, 0xEFFD, 0x9706, 0xEFFE, 0x9756, 0xF0A1, 0x975C, 0xF0A2, 0x9802, 0xF0A3, 0x9F0E, 0xF0A4, 0x5236,
+ 0xF0A5, 0x5291, 0xF0A6, 0x557C, 0xF0A7, 0x5824, 0xF0A8, 0x5E1D, 0xF0A9, 0x5F1F, 0xF0AA, 0x608C, 0xF0AB, 0x63D0, 0xF0AC, 0x68AF,
+ 0xF0AD, 0x6FDF, 0xF0AE, 0x796D, 0xF0AF, 0x7B2C, 0xF0B0, 0x81CD, 0xF0B1, 0x85BA, 0xF0B2, 0x88FD, 0xF0B3, 0x8AF8, 0xF0B4, 0x8E44,
+ 0xF0B5, 0x918D, 0xF0B6, 0x9664, 0xF0B7, 0x969B, 0xF0B8, 0x973D, 0xF0B9, 0x984C, 0xF0BA, 0x9F4A, 0xF0BB, 0x4FCE, 0xF0BC, 0x5146,
+ 0xF0BD, 0x51CB, 0xF0BE, 0x52A9, 0xF0BF, 0x5632, 0xF0C0, 0x5F14, 0xF0C1, 0x5F6B, 0xF0C2, 0x63AA, 0xF0C3, 0x64CD, 0xF0C4, 0x65E9,
+ 0xF0C5, 0x6641, 0xF0C6, 0x66FA, 0xF0C7, 0x66F9, 0xF0C8, 0x671D, 0xF0C9, 0x689D, 0xF0CA, 0x68D7, 0xF0CB, 0x69FD, 0xF0CC, 0x6F15,
+ 0xF0CD, 0x6F6E, 0xF0CE, 0x7167, 0xF0CF, 0x71E5, 0xF0D0, 0x722A, 0xF0D1, 0x74AA, 0xF0D2, 0x773A, 0xF0D3, 0x7956, 0xF0D4, 0x795A,
+ 0xF0D5, 0x79DF, 0xF0D6, 0x7A20, 0xF0D7, 0x7A95, 0xF0D8, 0x7C97, 0xF0D9, 0x7CDF, 0xF0DA, 0x7D44, 0xF0DB, 0x7E70, 0xF0DC, 0x8087,
+ 0xF0DD, 0x85FB, 0xF0DE, 0x86A4, 0xF0DF, 0x8A54, 0xF0E0, 0x8ABF, 0xF0E1, 0x8D99, 0xF0E2, 0x8E81, 0xF0E3, 0x9020, 0xF0E4, 0x906D,
+ 0xF0E5, 0x91E3, 0xF0E6, 0x963B, 0xF0E7, 0x96D5, 0xF0E8, 0x9CE5, 0xF0E9, 0x65CF, 0xF0EA, 0x7C07, 0xF0EB, 0x8DB3, 0xF0EC, 0x93C3,
+ 0xF0ED, 0x5B58, 0xF0EE, 0x5C0A, 0xF0EF, 0x5352, 0xF0F0, 0x62D9, 0xF0F1, 0x731D, 0xF0F2, 0x5027, 0xF0F3, 0x5B97, 0xF0F4, 0x5F9E,
+ 0xF0F5, 0x60B0, 0xF0F6, 0x616B, 0xF0F7, 0x68D5, 0xF0F8, 0x6DD9, 0xF0F9, 0x742E, 0xF0FA, 0x7A2E, 0xF0FB, 0x7D42, 0xF0FC, 0x7D9C,
+ 0xF0FD, 0x7E31, 0xF0FE, 0x816B, 0xF1A1, 0x8E2A, 0xF1A2, 0x8E35, 0xF1A3, 0x937E, 0xF1A4, 0x9418, 0xF1A5, 0x4F50, 0xF1A6, 0x5750,
+ 0xF1A7, 0x5DE6, 0xF1A8, 0x5EA7, 0xF1A9, 0x632B, 0xF1AA, 0x7F6A, 0xF1AB, 0x4E3B, 0xF1AC, 0x4F4F, 0xF1AD, 0x4F8F, 0xF1AE, 0x505A,
+ 0xF1AF, 0x59DD, 0xF1B0, 0x80C4, 0xF1B1, 0x546A, 0xF1B2, 0x5468, 0xF1B3, 0x55FE, 0xF1B4, 0x594F, 0xF1B5, 0x5B99, 0xF1B6, 0x5DDE,
+ 0xF1B7, 0x5EDA, 0xF1B8, 0x665D, 0xF1B9, 0x6731, 0xF1BA, 0x67F1, 0xF1BB, 0x682A, 0xF1BC, 0x6CE8, 0xF1BD, 0x6D32, 0xF1BE, 0x6E4A,
+ 0xF1BF, 0x6F8D, 0xF1C0, 0x70B7, 0xF1C1, 0x73E0, 0xF1C2, 0x7587, 0xF1C3, 0x7C4C, 0xF1C4, 0x7D02, 0xF1C5, 0x7D2C, 0xF1C6, 0x7DA2,
+ 0xF1C7, 0x821F, 0xF1C8, 0x86DB, 0xF1C9, 0x8A3B, 0xF1CA, 0x8A85, 0xF1CB, 0x8D70, 0xF1CC, 0x8E8A, 0xF1CD, 0x8F33, 0xF1CE, 0x9031,
+ 0xF1CF, 0x914E, 0xF1D0, 0x9152, 0xF1D1, 0x9444, 0xF1D2, 0x99D0, 0xF1D3, 0x7AF9, 0xF1D4, 0x7CA5, 0xF1D5, 0x4FCA, 0xF1D6, 0x5101,
+ 0xF1D7, 0x51C6, 0xF1D8, 0x57C8, 0xF1D9, 0x5BEF, 0xF1DA, 0x5CFB, 0xF1DB, 0x6659, 0xF1DC, 0x6A3D, 0xF1DD, 0x6D5A, 0xF1DE, 0x6E96,
+ 0xF1DF, 0x6FEC, 0xF1E0, 0x710C, 0xF1E1, 0x756F, 0xF1E2, 0x7AE3, 0xF1E3, 0x8822, 0xF1E4, 0x9021, 0xF1E5, 0x9075, 0xF1E6, 0x96CB,
+ 0xF1E7, 0x99FF, 0xF1E8, 0x8301, 0xF1E9, 0x4E2D, 0xF1EA, 0x4EF2, 0xF1EB, 0x8846, 0xF1EC, 0x91CD, 0xF1ED, 0x537D, 0xF1EE, 0x6ADB,
+ 0xF1EF, 0x696B, 0xF1F0, 0x6C41, 0xF1F1, 0x847A, 0xF1F2, 0x589E, 0xF1F3, 0x618E, 0xF1F4, 0x66FE, 0xF1F5, 0x62EF, 0xF1F6, 0x70DD,
+ 0xF1F7, 0x7511, 0xF1F8, 0x75C7, 0xF1F9, 0x7E52, 0xF1FA, 0x84B8, 0xF1FB, 0x8B49, 0xF1FC, 0x8D08, 0xF1FD, 0x4E4B, 0xF1FE, 0x53EA,
+ 0xF2A1, 0x54AB, 0xF2A2, 0x5730, 0xF2A3, 0x5740, 0xF2A4, 0x5FD7, 0xF2A5, 0x6301, 0xF2A6, 0x6307, 0xF2A7, 0x646F, 0xF2A8, 0x652F,
+ 0xF2A9, 0x65E8, 0xF2AA, 0x667A, 0xF2AB, 0x679D, 0xF2AC, 0x67B3, 0xF2AD, 0x6B62, 0xF2AE, 0x6C60, 0xF2AF, 0x6C9A, 0xF2B0, 0x6F2C,
+ 0xF2B1, 0x77E5, 0xF2B2, 0x7825, 0xF2B3, 0x7949, 0xF2B4, 0x7957, 0xF2B5, 0x7D19, 0xF2B6, 0x80A2, 0xF2B7, 0x8102, 0xF2B8, 0x81F3,
+ 0xF2B9, 0x829D, 0xF2BA, 0x82B7, 0xF2BB, 0x8718, 0xF2BC, 0x8A8C, 0xF2BD, 0xF9FC, 0xF2BE, 0x8D04, 0xF2BF, 0x8DBE, 0xF2C0, 0x9072,
+ 0xF2C1, 0x76F4, 0xF2C2, 0x7A19, 0xF2C3, 0x7A37, 0xF2C4, 0x7E54, 0xF2C5, 0x8077, 0xF2C6, 0x5507, 0xF2C7, 0x55D4, 0xF2C8, 0x5875,
+ 0xF2C9, 0x632F, 0xF2CA, 0x6422, 0xF2CB, 0x6649, 0xF2CC, 0x664B, 0xF2CD, 0x686D, 0xF2CE, 0x699B, 0xF2CF, 0x6B84, 0xF2D0, 0x6D25,
+ 0xF2D1, 0x6EB1, 0xF2D2, 0x73CD, 0xF2D3, 0x7468, 0xF2D4, 0x74A1, 0xF2D5, 0x755B, 0xF2D6, 0x75B9, 0xF2D7, 0x76E1, 0xF2D8, 0x771E,
+ 0xF2D9, 0x778B, 0xF2DA, 0x79E6, 0xF2DB, 0x7E09, 0xF2DC, 0x7E1D, 0xF2DD, 0x81FB, 0xF2DE, 0x852F, 0xF2DF, 0x8897, 0xF2E0, 0x8A3A,
+ 0xF2E1, 0x8CD1, 0xF2E2, 0x8EEB, 0xF2E3, 0x8FB0, 0xF2E4, 0x9032, 0xF2E5, 0x93AD, 0xF2E6, 0x9663, 0xF2E7, 0x9673, 0xF2E8, 0x9707,
+ 0xF2E9, 0x4F84, 0xF2EA, 0x53F1, 0xF2EB, 0x59EA, 0xF2EC, 0x5AC9, 0xF2ED, 0x5E19, 0xF2EE, 0x684E, 0xF2EF, 0x74C6, 0xF2F0, 0x75BE,
+ 0xF2F1, 0x79E9, 0xF2F2, 0x7A92, 0xF2F3, 0x81A3, 0xF2F4, 0x86ED, 0xF2F5, 0x8CEA, 0xF2F6, 0x8DCC, 0xF2F7, 0x8FED, 0xF2F8, 0x659F,
+ 0xF2F9, 0x6715, 0xF2FA, 0xF9FD, 0xF2FB, 0x57F7, 0xF2FC, 0x6F57, 0xF2FD, 0x7DDD, 0xF2FE, 0x8F2F, 0xF3A1, 0x93F6, 0xF3A2, 0x96C6,
+ 0xF3A3, 0x5FB5, 0xF3A4, 0x61F2, 0xF3A5, 0x6F84, 0xF3A6, 0x4E14, 0xF3A7, 0x4F98, 0xF3A8, 0x501F, 0xF3A9, 0x53C9, 0xF3AA, 0x55DF,
+ 0xF3AB, 0x5D6F, 0xF3AC, 0x5DEE, 0xF3AD, 0x6B21, 0xF3AE, 0x6B64, 0xF3AF, 0x78CB, 0xF3B0, 0x7B9A, 0xF3B1, 0xF9FE, 0xF3B2, 0x8E49,
+ 0xF3B3, 0x8ECA, 0xF3B4, 0x906E, 0xF3B5, 0x6349, 0xF3B6, 0x643E, 0xF3B7, 0x7740, 0xF3B8, 0x7A84, 0xF3B9, 0x932F, 0xF3BA, 0x947F,
+ 0xF3BB, 0x9F6A, 0xF3BC, 0x64B0, 0xF3BD, 0x6FAF, 0xF3BE, 0x71E6, 0xF3BF, 0x74A8, 0xF3C0, 0x74DA, 0xF3C1, 0x7AC4, 0xF3C2, 0x7C12,
+ 0xF3C3, 0x7E82, 0xF3C4, 0x7CB2, 0xF3C5, 0x7E98, 0xF3C6, 0x8B9A, 0xF3C7, 0x8D0A, 0xF3C8, 0x947D, 0xF3C9, 0x9910, 0xF3CA, 0x994C,
+ 0xF3CB, 0x5239, 0xF3CC, 0x5BDF, 0xF3CD, 0x64E6, 0xF3CE, 0x672D, 0xF3CF, 0x7D2E, 0xF3D0, 0x50ED, 0xF3D1, 0x53C3, 0xF3D2, 0x5879,
+ 0xF3D3, 0x6158, 0xF3D4, 0x6159, 0xF3D5, 0x61FA, 0xF3D6, 0x65AC, 0xF3D7, 0x7AD9, 0xF3D8, 0x8B92, 0xF3D9, 0x8B96, 0xF3DA, 0x5009,
+ 0xF3DB, 0x5021, 0xF3DC, 0x5275, 0xF3DD, 0x5531, 0xF3DE, 0x5A3C, 0xF3DF, 0x5EE0, 0xF3E0, 0x5F70, 0xF3E1, 0x6134, 0xF3E2, 0x655E,
+ 0xF3E3, 0x660C, 0xF3E4, 0x6636, 0xF3E5, 0x66A2, 0xF3E6, 0x69CD, 0xF3E7, 0x6EC4, 0xF3E8, 0x6F32, 0xF3E9, 0x7316, 0xF3EA, 0x7621,
+ 0xF3EB, 0x7A93, 0xF3EC, 0x8139, 0xF3ED, 0x8259, 0xF3EE, 0x83D6, 0xF3EF, 0x84BC, 0xF3F0, 0x50B5, 0xF3F1, 0x57F0, 0xF3F2, 0x5BC0,
+ 0xF3F3, 0x5BE8, 0xF3F4, 0x5F69, 0xF3F5, 0x63A1, 0xF3F6, 0x7826, 0xF3F7, 0x7DB5, 0xF3F8, 0x83DC, 0xF3F9, 0x8521, 0xF3FA, 0x91C7,
+ 0xF3FB, 0x91F5, 0xF3FC, 0x518A, 0xF3FD, 0x67F5, 0xF3FE, 0x7B56, 0xF4A1, 0x8CAC, 0xF4A2, 0x51C4, 0xF4A3, 0x59BB, 0xF4A4, 0x60BD,
+ 0xF4A5, 0x8655, 0xF4A6, 0x501C, 0xF4A7, 0xF9FF, 0xF4A8, 0x5254, 0xF4A9, 0x5C3A, 0xF4AA, 0x617D, 0xF4AB, 0x621A, 0xF4AC, 0x62D3,
+ 0xF4AD, 0x64F2, 0xF4AE, 0x65A5, 0xF4AF, 0x6ECC, 0xF4B0, 0x7620, 0xF4B1, 0x810A, 0xF4B2, 0x8E60, 0xF4B3, 0x965F, 0xF4B4, 0x96BB,
+ 0xF4B5, 0x4EDF, 0xF4B6, 0x5343, 0xF4B7, 0x5598, 0xF4B8, 0x5929, 0xF4B9, 0x5DDD, 0xF4BA, 0x64C5, 0xF4BB, 0x6CC9, 0xF4BC, 0x6DFA,
+ 0xF4BD, 0x7394, 0xF4BE, 0x7A7F, 0xF4BF, 0x821B, 0xF4C0, 0x85A6, 0xF4C1, 0x8CE4, 0xF4C2, 0x8E10, 0xF4C3, 0x9077, 0xF4C4, 0x91E7,
+ 0xF4C5, 0x95E1, 0xF4C6, 0x9621, 0xF4C7, 0x97C6, 0xF4C8, 0x51F8, 0xF4C9, 0x54F2, 0xF4CA, 0x5586, 0xF4CB, 0x5FB9, 0xF4CC, 0x64A4,
+ 0xF4CD, 0x6F88, 0xF4CE, 0x7DB4, 0xF4CF, 0x8F1F, 0xF4D0, 0x8F4D, 0xF4D1, 0x9435, 0xF4D2, 0x50C9, 0xF4D3, 0x5C16, 0xF4D4, 0x6CBE,
+ 0xF4D5, 0x6DFB, 0xF4D6, 0x751B, 0xF4D7, 0x77BB, 0xF4D8, 0x7C3D, 0xF4D9, 0x7C64, 0xF4DA, 0x8A79, 0xF4DB, 0x8AC2, 0xF4DC, 0x581E,
+ 0xF4DD, 0x59BE, 0xF4DE, 0x5E16, 0xF4DF, 0x6377, 0xF4E0, 0x7252, 0xF4E1, 0x758A, 0xF4E2, 0x776B, 0xF4E3, 0x8ADC, 0xF4E4, 0x8CBC,
+ 0xF4E5, 0x8F12, 0xF4E6, 0x5EF3, 0xF4E7, 0x6674, 0xF4E8, 0x6DF8, 0xF4E9, 0x807D, 0xF4EA, 0x83C1, 0xF4EB, 0x8ACB, 0xF4EC, 0x9751,
+ 0xF4ED, 0x9BD6, 0xF4EE, 0xFA00, 0xF4EF, 0x5243, 0xF4F0, 0x66FF, 0xF4F1, 0x6D95, 0xF4F2, 0x6EEF, 0xF4F3, 0x7DE0, 0xF4F4, 0x8AE6,
+ 0xF4F5, 0x902E, 0xF4F6, 0x905E, 0xF4F7, 0x9AD4, 0xF4F8, 0x521D, 0xF4F9, 0x527F, 0xF4FA, 0x54E8, 0xF4FB, 0x6194, 0xF4FC, 0x6284,
+ 0xF4FD, 0x62DB, 0xF4FE, 0x68A2, 0xF5A1, 0x6912, 0xF5A2, 0x695A, 0xF5A3, 0x6A35, 0xF5A4, 0x7092, 0xF5A5, 0x7126, 0xF5A6, 0x785D,
+ 0xF5A7, 0x7901, 0xF5A8, 0x790E, 0xF5A9, 0x79D2, 0xF5AA, 0x7A0D, 0xF5AB, 0x8096, 0xF5AC, 0x8278, 0xF5AD, 0x82D5, 0xF5AE, 0x8349,
+ 0xF5AF, 0x8549, 0xF5B0, 0x8C82, 0xF5B1, 0x8D85, 0xF5B2, 0x9162, 0xF5B3, 0x918B, 0xF5B4, 0x91AE, 0xF5B5, 0x4FC3, 0xF5B6, 0x56D1,
+ 0xF5B7, 0x71ED, 0xF5B8, 0x77D7, 0xF5B9, 0x8700, 0xF5BA, 0x89F8, 0xF5BB, 0x5BF8, 0xF5BC, 0x5FD6, 0xF5BD, 0x6751, 0xF5BE, 0x90A8,
+ 0xF5BF, 0x53E2, 0xF5C0, 0x585A, 0xF5C1, 0x5BF5, 0xF5C2, 0x60A4, 0xF5C3, 0x6181, 0xF5C4, 0x6460, 0xF5C5, 0x7E3D, 0xF5C6, 0x8070,
+ 0xF5C7, 0x8525, 0xF5C8, 0x9283, 0xF5C9, 0x64AE, 0xF5CA, 0x50AC, 0xF5CB, 0x5D14, 0xF5CC, 0x6700, 0xF5CD, 0x589C, 0xF5CE, 0x62BD,
+ 0xF5CF, 0x63A8, 0xF5D0, 0x690E, 0xF5D1, 0x6978, 0xF5D2, 0x6A1E, 0xF5D3, 0x6E6B, 0xF5D4, 0x76BA, 0xF5D5, 0x79CB, 0xF5D6, 0x82BB,
+ 0xF5D7, 0x8429, 0xF5D8, 0x8ACF, 0xF5D9, 0x8DA8, 0xF5DA, 0x8FFD, 0xF5DB, 0x9112, 0xF5DC, 0x914B, 0xF5DD, 0x919C, 0xF5DE, 0x9310,
+ 0xF5DF, 0x9318, 0xF5E0, 0x939A, 0xF5E1, 0x96DB, 0xF5E2, 0x9A36, 0xF5E3, 0x9C0D, 0xF5E4, 0x4E11, 0xF5E5, 0x755C, 0xF5E6, 0x795D,
+ 0xF5E7, 0x7AFA, 0xF5E8, 0x7B51, 0xF5E9, 0x7BC9, 0xF5EA, 0x7E2E, 0xF5EB, 0x84C4, 0xF5EC, 0x8E59, 0xF5ED, 0x8E74, 0xF5EE, 0x8EF8,
+ 0xF5EF, 0x9010, 0xF5F0, 0x6625, 0xF5F1, 0x693F, 0xF5F2, 0x7443, 0xF5F3, 0x51FA, 0xF5F4, 0x672E, 0xF5F5, 0x9EDC, 0xF5F6, 0x5145,
+ 0xF5F7, 0x5FE0, 0xF5F8, 0x6C96, 0xF5F9, 0x87F2, 0xF5FA, 0x885D, 0xF5FB, 0x8877, 0xF5FC, 0x60B4, 0xF5FD, 0x81B5, 0xF5FE, 0x8403,
+ 0xF6A1, 0x8D05, 0xF6A2, 0x53D6, 0xF6A3, 0x5439, 0xF6A4, 0x5634, 0xF6A5, 0x5A36, 0xF6A6, 0x5C31, 0xF6A7, 0x708A, 0xF6A8, 0x7FE0,
+ 0xF6A9, 0x805A, 0xF6AA, 0x8106, 0xF6AB, 0x81ED, 0xF6AC, 0x8DA3, 0xF6AD, 0x9189, 0xF6AE, 0x9A5F, 0xF6AF, 0x9DF2, 0xF6B0, 0x5074,
+ 0xF6B1, 0x4EC4, 0xF6B2, 0x53A0, 0xF6B3, 0x60FB, 0xF6B4, 0x6E2C, 0xF6B5, 0x5C64, 0xF6B6, 0x4F88, 0xF6B7, 0x5024, 0xF6B8, 0x55E4,
+ 0xF6B9, 0x5CD9, 0xF6BA, 0x5E5F, 0xF6BB, 0x6065, 0xF6BC, 0x6894, 0xF6BD, 0x6CBB, 0xF6BE, 0x6DC4, 0xF6BF, 0x71BE, 0xF6C0, 0x75D4,
+ 0xF6C1, 0x75F4, 0xF6C2, 0x7661, 0xF6C3, 0x7A1A, 0xF6C4, 0x7A49, 0xF6C5, 0x7DC7, 0xF6C6, 0x7DFB, 0xF6C7, 0x7F6E, 0xF6C8, 0x81F4,
+ 0xF6C9, 0x86A9, 0xF6CA, 0x8F1C, 0xF6CB, 0x96C9, 0xF6CC, 0x99B3, 0xF6CD, 0x9F52, 0xF6CE, 0x5247, 0xF6CF, 0x52C5, 0xF6D0, 0x98ED,
+ 0xF6D1, 0x89AA, 0xF6D2, 0x4E03, 0xF6D3, 0x67D2, 0xF6D4, 0x6F06, 0xF6D5, 0x4FB5, 0xF6D6, 0x5BE2, 0xF6D7, 0x6795, 0xF6D8, 0x6C88,
+ 0xF6D9, 0x6D78, 0xF6DA, 0x741B, 0xF6DB, 0x7827, 0xF6DC, 0x91DD, 0xF6DD, 0x937C, 0xF6DE, 0x87C4, 0xF6DF, 0x79E4, 0xF6E0, 0x7A31,
+ 0xF6E1, 0x5FEB, 0xF6E2, 0x4ED6, 0xF6E3, 0x54A4, 0xF6E4, 0x553E, 0xF6E5, 0x58AE, 0xF6E6, 0x59A5, 0xF6E7, 0x60F0, 0xF6E8, 0x6253,
+ 0xF6E9, 0x62D6, 0xF6EA, 0x6736, 0xF6EB, 0x6955, 0xF6EC, 0x8235, 0xF6ED, 0x9640, 0xF6EE, 0x99B1, 0xF6EF, 0x99DD, 0xF6F0, 0x502C,
+ 0xF6F1, 0x5353, 0xF6F2, 0x5544, 0xF6F3, 0x577C, 0xF6F4, 0xFA01, 0xF6F5, 0x6258, 0xF6F6, 0xFA02, 0xF6F7, 0x64E2, 0xF6F8, 0x666B,
+ 0xF6F9, 0x67DD, 0xF6FA, 0x6FC1, 0xF6FB, 0x6FEF, 0xF6FC, 0x7422, 0xF6FD, 0x7438, 0xF6FE, 0x8A17, 0xF7A1, 0x9438, 0xF7A2, 0x5451,
+ 0xF7A3, 0x5606, 0xF7A4, 0x5766, 0xF7A5, 0x5F48, 0xF7A6, 0x619A, 0xF7A7, 0x6B4E, 0xF7A8, 0x7058, 0xF7A9, 0x70AD, 0xF7AA, 0x7DBB,
+ 0xF7AB, 0x8A95, 0xF7AC, 0x596A, 0xF7AD, 0x812B, 0xF7AE, 0x63A2, 0xF7AF, 0x7708, 0xF7B0, 0x803D, 0xF7B1, 0x8CAA, 0xF7B2, 0x5854,
+ 0xF7B3, 0x642D, 0xF7B4, 0x69BB, 0xF7B5, 0x5B95, 0xF7B6, 0x5E11, 0xF7B7, 0x6E6F, 0xF7B8, 0xFA03, 0xF7B9, 0x8569, 0xF7BA, 0x514C,
+ 0xF7BB, 0x53F0, 0xF7BC, 0x592A, 0xF7BD, 0x6020, 0xF7BE, 0x614B, 0xF7BF, 0x6B86, 0xF7C0, 0x6C70, 0xF7C1, 0x6CF0, 0xF7C2, 0x7B1E,
+ 0xF7C3, 0x80CE, 0xF7C4, 0x82D4, 0xF7C5, 0x8DC6, 0xF7C6, 0x90B0, 0xF7C7, 0x98B1, 0xF7C8, 0xFA04, 0xF7C9, 0x64C7, 0xF7CA, 0x6FA4,
+ 0xF7CB, 0x6491, 0xF7CC, 0x6504, 0xF7CD, 0x514E, 0xF7CE, 0x5410, 0xF7CF, 0x571F, 0xF7D0, 0x8A0E, 0xF7D1, 0x615F, 0xF7D2, 0x6876,
+ 0xF7D3, 0xFA05, 0xF7D4, 0x75DB, 0xF7D5, 0x7B52, 0xF7D6, 0x7D71, 0xF7D7, 0x901A, 0xF7D8, 0x5806, 0xF7D9, 0x69CC, 0xF7DA, 0x817F,
+ 0xF7DB, 0x892A, 0xF7DC, 0x9000, 0xF7DD, 0x9839, 0xF7DE, 0x5078, 0xF7DF, 0x5957, 0xF7E0, 0x59AC, 0xF7E1, 0x6295, 0xF7E2, 0x900F,
+ 0xF7E3, 0x9B2A, 0xF7E4, 0x615D, 0xF7E5, 0x7279, 0xF7E6, 0x95D6, 0xF7E7, 0x5761, 0xF7E8, 0x5A46, 0xF7E9, 0x5DF4, 0xF7EA, 0x628A,
+ 0xF7EB, 0x64AD, 0xF7EC, 0x64FA, 0xF7ED, 0x6777, 0xF7EE, 0x6CE2, 0xF7EF, 0x6D3E, 0xF7F0, 0x722C, 0xF7F1, 0x7436, 0xF7F2, 0x7834,
+ 0xF7F3, 0x7F77, 0xF7F4, 0x82AD, 0xF7F5, 0x8DDB, 0xF7F6, 0x9817, 0xF7F7, 0x5224, 0xF7F8, 0x5742, 0xF7F9, 0x677F, 0xF7FA, 0x7248,
+ 0xF7FB, 0x74E3, 0xF7FC, 0x8CA9, 0xF7FD, 0x8FA6, 0xF7FE, 0x9211, 0xF8A1, 0x962A, 0xF8A2, 0x516B, 0xF8A3, 0x53ED, 0xF8A4, 0x634C,
+ 0xF8A5, 0x4F69, 0xF8A6, 0x5504, 0xF8A7, 0x6096, 0xF8A8, 0x6557, 0xF8A9, 0x6C9B, 0xF8AA, 0x6D7F, 0xF8AB, 0x724C, 0xF8AC, 0x72FD,
+ 0xF8AD, 0x7A17, 0xF8AE, 0x8987, 0xF8AF, 0x8C9D, 0xF8B0, 0x5F6D, 0xF8B1, 0x6F8E, 0xF8B2, 0x70F9, 0xF8B3, 0x81A8, 0xF8B4, 0x610E,
+ 0xF8B5, 0x4FBF, 0xF8B6, 0x504F, 0xF8B7, 0x6241, 0xF8B8, 0x7247, 0xF8B9, 0x7BC7, 0xF8BA, 0x7DE8, 0xF8BB, 0x7FE9, 0xF8BC, 0x904D,
+ 0xF8BD, 0x97AD, 0xF8BE, 0x9A19, 0xF8BF, 0x8CB6, 0xF8C0, 0x576A, 0xF8C1, 0x5E73, 0xF8C2, 0x67B0, 0xF8C3, 0x840D, 0xF8C4, 0x8A55,
+ 0xF8C5, 0x5420, 0xF8C6, 0x5B16, 0xF8C7, 0x5E63, 0xF8C8, 0x5EE2, 0xF8C9, 0x5F0A, 0xF8CA, 0x6583, 0xF8CB, 0x80BA, 0xF8CC, 0x853D,
+ 0xF8CD, 0x9589, 0xF8CE, 0x965B, 0xF8CF, 0x4F48, 0xF8D0, 0x5305, 0xF8D1, 0x530D, 0xF8D2, 0x530F, 0xF8D3, 0x5486, 0xF8D4, 0x54FA,
+ 0xF8D5, 0x5703, 0xF8D6, 0x5E03, 0xF8D7, 0x6016, 0xF8D8, 0x629B, 0xF8D9, 0x62B1, 0xF8DA, 0x6355, 0xF8DB, 0xFA06, 0xF8DC, 0x6CE1,
+ 0xF8DD, 0x6D66, 0xF8DE, 0x75B1, 0xF8DF, 0x7832, 0xF8E0, 0x80DE, 0xF8E1, 0x812F, 0xF8E2, 0x82DE, 0xF8E3, 0x8461, 0xF8E4, 0x84B2,
+ 0xF8E5, 0x888D, 0xF8E6, 0x8912, 0xF8E7, 0x900B, 0xF8E8, 0x92EA, 0xF8E9, 0x98FD, 0xF8EA, 0x9B91, 0xF8EB, 0x5E45, 0xF8EC, 0x66B4,
+ 0xF8ED, 0x66DD, 0xF8EE, 0x7011, 0xF8EF, 0x7206, 0xF8F0, 0xFA07, 0xF8F1, 0x4FF5, 0xF8F2, 0x527D, 0xF8F3, 0x5F6A, 0xF8F4, 0x6153,
+ 0xF8F5, 0x6753, 0xF8F6, 0x6A19, 0xF8F7, 0x6F02, 0xF8F8, 0x74E2, 0xF8F9, 0x7968, 0xF8FA, 0x8868, 0xF8FB, 0x8C79, 0xF8FC, 0x98C7,
+ 0xF8FD, 0x98C4, 0xF8FE, 0x9A43, 0xF9A1, 0x54C1, 0xF9A2, 0x7A1F, 0xF9A3, 0x6953, 0xF9A4, 0x8AF7, 0xF9A5, 0x8C4A, 0xF9A6, 0x98A8,
+ 0xF9A7, 0x99AE, 0xF9A8, 0x5F7C, 0xF9A9, 0x62AB, 0xF9AA, 0x75B2, 0xF9AB, 0x76AE, 0xF9AC, 0x88AB, 0xF9AD, 0x907F, 0xF9AE, 0x9642,
+ 0xF9AF, 0x5339, 0xF9B0, 0x5F3C, 0xF9B1, 0x5FC5, 0xF9B2, 0x6CCC, 0xF9B3, 0x73CC, 0xF9B4, 0x7562, 0xF9B5, 0x758B, 0xF9B6, 0x7B46,
+ 0xF9B7, 0x82FE, 0xF9B8, 0x999D, 0xF9B9, 0x4E4F, 0xF9BA, 0x903C, 0xF9BB, 0x4E0B, 0xF9BC, 0x4F55, 0xF9BD, 0x53A6, 0xF9BE, 0x590F,
+ 0xF9BF, 0x5EC8, 0xF9C0, 0x6630, 0xF9C1, 0x6CB3, 0xF9C2, 0x7455, 0xF9C3, 0x8377, 0xF9C4, 0x8766, 0xF9C5, 0x8CC0, 0xF9C6, 0x9050,
+ 0xF9C7, 0x971E, 0xF9C8, 0x9C15, 0xF9C9, 0x58D1, 0xF9CA, 0x5B78, 0xF9CB, 0x8650, 0xF9CC, 0x8B14, 0xF9CD, 0x9DB4, 0xF9CE, 0x5BD2,
+ 0xF9CF, 0x6068, 0xF9D0, 0x608D, 0xF9D1, 0x65F1, 0xF9D2, 0x6C57, 0xF9D3, 0x6F22, 0xF9D4, 0x6FA3, 0xF9D5, 0x701A, 0xF9D6, 0x7F55,
+ 0xF9D7, 0x7FF0, 0xF9D8, 0x9591, 0xF9D9, 0x9592, 0xF9DA, 0x9650, 0xF9DB, 0x97D3, 0xF9DC, 0x5272, 0xF9DD, 0x8F44, 0xF9DE, 0x51FD,
+ 0xF9DF, 0x542B, 0xF9E0, 0x54B8, 0xF9E1, 0x5563, 0xF9E2, 0x558A, 0xF9E3, 0x6ABB, 0xF9E4, 0x6DB5, 0xF9E5, 0x7DD8, 0xF9E6, 0x8266,
+ 0xF9E7, 0x929C, 0xF9E8, 0x9677, 0xF9E9, 0x9E79, 0xF9EA, 0x5408, 0xF9EB, 0x54C8, 0xF9EC, 0x76D2, 0xF9ED, 0x86E4, 0xF9EE, 0x95A4,
+ 0xF9EF, 0x95D4, 0xF9F0, 0x965C, 0xF9F1, 0x4EA2, 0xF9F2, 0x4F09, 0xF9F3, 0x59EE, 0xF9F4, 0x5AE6, 0xF9F5, 0x5DF7, 0xF9F6, 0x6052,
+ 0xF9F7, 0x6297, 0xF9F8, 0x676D, 0xF9F9, 0x6841, 0xF9FA, 0x6C86, 0xF9FB, 0x6E2F, 0xF9FC, 0x7F38, 0xF9FD, 0x809B, 0xF9FE, 0x822A,
+ 0xFAA1, 0xFA08, 0xFAA2, 0xFA09, 0xFAA3, 0x9805, 0xFAA4, 0x4EA5, 0xFAA5, 0x5055, 0xFAA6, 0x54B3, 0xFAA7, 0x5793, 0xFAA8, 0x595A,
+ 0xFAA9, 0x5B69, 0xFAAA, 0x5BB3, 0xFAAB, 0x61C8, 0xFAAC, 0x6977, 0xFAAD, 0x6D77, 0xFAAE, 0x7023, 0xFAAF, 0x87F9, 0xFAB0, 0x89E3,
+ 0xFAB1, 0x8A72, 0xFAB2, 0x8AE7, 0xFAB3, 0x9082, 0xFAB4, 0x99ED, 0xFAB5, 0x9AB8, 0xFAB6, 0x52BE, 0xFAB7, 0x6838, 0xFAB8, 0x5016,
+ 0xFAB9, 0x5E78, 0xFABA, 0x674F, 0xFABB, 0x8347, 0xFABC, 0x884C, 0xFABD, 0x4EAB, 0xFABE, 0x5411, 0xFABF, 0x56AE, 0xFAC0, 0x73E6,
+ 0xFAC1, 0x9115, 0xFAC2, 0x97FF, 0xFAC3, 0x9909, 0xFAC4, 0x9957, 0xFAC5, 0x9999, 0xFAC6, 0x5653, 0xFAC7, 0x589F, 0xFAC8, 0x865B,
+ 0xFAC9, 0x8A31, 0xFACA, 0x61B2, 0xFACB, 0x6AF6, 0xFACC, 0x737B, 0xFACD, 0x8ED2, 0xFACE, 0x6B47, 0xFACF, 0x96AA, 0xFAD0, 0x9A57,
+ 0xFAD1, 0x5955, 0xFAD2, 0x7200, 0xFAD3, 0x8D6B, 0xFAD4, 0x9769, 0xFAD5, 0x4FD4, 0xFAD6, 0x5CF4, 0xFAD7, 0x5F26, 0xFAD8, 0x61F8,
+ 0xFAD9, 0x665B, 0xFADA, 0x6CEB, 0xFADB, 0x70AB, 0xFADC, 0x7384, 0xFADD, 0x73B9, 0xFADE, 0x73FE, 0xFADF, 0x7729, 0xFAE0, 0x774D,
+ 0xFAE1, 0x7D43, 0xFAE2, 0x7D62, 0xFAE3, 0x7E23, 0xFAE4, 0x8237, 0xFAE5, 0x8852, 0xFAE6, 0xFA0A, 0xFAE7, 0x8CE2, 0xFAE8, 0x9249,
+ 0xFAE9, 0x986F, 0xFAEA, 0x5B51, 0xFAEB, 0x7A74, 0xFAEC, 0x8840, 0xFAED, 0x9801, 0xFAEE, 0x5ACC, 0xFAEF, 0x4FE0, 0xFAF0, 0x5354,
+ 0xFAF1, 0x593E, 0xFAF2, 0x5CFD, 0xFAF3, 0x633E, 0xFAF4, 0x6D79, 0xFAF5, 0x72F9, 0xFAF6, 0x8105, 0xFAF7, 0x8107, 0xFAF8, 0x83A2,
+ 0xFAF9, 0x92CF, 0xFAFA, 0x9830, 0xFAFB, 0x4EA8, 0xFAFC, 0x5144, 0xFAFD, 0x5211, 0xFAFE, 0x578B, 0xFBA1, 0x5F62, 0xFBA2, 0x6CC2,
+ 0xFBA3, 0x6ECE, 0xFBA4, 0x7005, 0xFBA5, 0x7050, 0xFBA6, 0x70AF, 0xFBA7, 0x7192, 0xFBA8, 0x73E9, 0xFBA9, 0x7469, 0xFBAA, 0x834A,
+ 0xFBAB, 0x87A2, 0xFBAC, 0x8861, 0xFBAD, 0x9008, 0xFBAE, 0x90A2, 0xFBAF, 0x93A3, 0xFBB0, 0x99A8, 0xFBB1, 0x516E, 0xFBB2, 0x5F57,
+ 0xFBB3, 0x60E0, 0xFBB4, 0x6167, 0xFBB5, 0x66B3, 0xFBB6, 0x8559, 0xFBB7, 0x8E4A, 0xFBB8, 0x91AF, 0xFBB9, 0x978B, 0xFBBA, 0x4E4E,
+ 0xFBBB, 0x4E92, 0xFBBC, 0x547C, 0xFBBD, 0x58D5, 0xFBBE, 0x58FA, 0xFBBF, 0x597D, 0xFBC0, 0x5CB5, 0xFBC1, 0x5F27, 0xFBC2, 0x6236,
+ 0xFBC3, 0x6248, 0xFBC4, 0x660A, 0xFBC5, 0x6667, 0xFBC6, 0x6BEB, 0xFBC7, 0x6D69, 0xFBC8, 0x6DCF, 0xFBC9, 0x6E56, 0xFBCA, 0x6EF8,
+ 0xFBCB, 0x6F94, 0xFBCC, 0x6FE0, 0xFBCD, 0x6FE9, 0xFBCE, 0x705D, 0xFBCF, 0x72D0, 0xFBD0, 0x7425, 0xFBD1, 0x745A, 0xFBD2, 0x74E0,
+ 0xFBD3, 0x7693, 0xFBD4, 0x795C, 0xFBD5, 0x7CCA, 0xFBD6, 0x7E1E, 0xFBD7, 0x80E1, 0xFBD8, 0x82A6, 0xFBD9, 0x846B, 0xFBDA, 0x84BF,
+ 0xFBDB, 0x864E, 0xFBDC, 0x865F, 0xFBDD, 0x8774, 0xFBDE, 0x8B77, 0xFBDF, 0x8C6A, 0xFBE0, 0x93AC, 0xFBE1, 0x9800, 0xFBE2, 0x9865,
+ 0xFBE3, 0x60D1, 0xFBE4, 0x6216, 0xFBE5, 0x9177, 0xFBE6, 0x5A5A, 0xFBE7, 0x660F, 0xFBE8, 0x6DF7, 0xFBE9, 0x6E3E, 0xFBEA, 0x743F,
+ 0xFBEB, 0x9B42, 0xFBEC, 0x5FFD, 0xFBED, 0x60DA, 0xFBEE, 0x7B0F, 0xFBEF, 0x54C4, 0xFBF0, 0x5F18, 0xFBF1, 0x6C5E, 0xFBF2, 0x6CD3,
+ 0xFBF3, 0x6D2A, 0xFBF4, 0x70D8, 0xFBF5, 0x7D05, 0xFBF6, 0x8679, 0xFBF7, 0x8A0C, 0xFBF8, 0x9D3B, 0xFBF9, 0x5316, 0xFBFA, 0x548C,
+ 0xFBFB, 0x5B05, 0xFBFC, 0x6A3A, 0xFBFD, 0x706B, 0xFBFE, 0x7575, 0xFCA1, 0x798D, 0xFCA2, 0x79BE, 0xFCA3, 0x82B1, 0xFCA4, 0x83EF,
+ 0xFCA5, 0x8A71, 0xFCA6, 0x8B41, 0xFCA7, 0x8CA8, 0xFCA8, 0x9774, 0xFCA9, 0xFA0B, 0xFCAA, 0x64F4, 0xFCAB, 0x652B, 0xFCAC, 0x78BA,
+ 0xFCAD, 0x78BB, 0xFCAE, 0x7A6B, 0xFCAF, 0x4E38, 0xFCB0, 0x559A, 0xFCB1, 0x5950, 0xFCB2, 0x5BA6, 0xFCB3, 0x5E7B, 0xFCB4, 0x60A3,
+ 0xFCB5, 0x63DB, 0xFCB6, 0x6B61, 0xFCB7, 0x6665, 0xFCB8, 0x6853, 0xFCB9, 0x6E19, 0xFCBA, 0x7165, 0xFCBB, 0x74B0, 0xFCBC, 0x7D08,
+ 0xFCBD, 0x9084, 0xFCBE, 0x9A69, 0xFCBF, 0x9C25, 0xFCC0, 0x6D3B, 0xFCC1, 0x6ED1, 0xFCC2, 0x733E, 0xFCC3, 0x8C41, 0xFCC4, 0x95CA,
+ 0xFCC5, 0x51F0, 0xFCC6, 0x5E4C, 0xFCC7, 0x5FA8, 0xFCC8, 0x604D, 0xFCC9, 0x60F6, 0xFCCA, 0x6130, 0xFCCB, 0x614C, 0xFCCC, 0x6643,
+ 0xFCCD, 0x6644, 0xFCCE, 0x69A5, 0xFCCF, 0x6CC1, 0xFCD0, 0x6E5F, 0xFCD1, 0x6EC9, 0xFCD2, 0x6F62, 0xFCD3, 0x714C, 0xFCD4, 0x749C,
+ 0xFCD5, 0x7687, 0xFCD6, 0x7BC1, 0xFCD7, 0x7C27, 0xFCD8, 0x8352, 0xFCD9, 0x8757, 0xFCDA, 0x9051, 0xFCDB, 0x968D, 0xFCDC, 0x9EC3,
+ 0xFCDD, 0x532F, 0xFCDE, 0x56DE, 0xFCDF, 0x5EFB, 0xFCE0, 0x5F8A, 0xFCE1, 0x6062, 0xFCE2, 0x6094, 0xFCE3, 0x61F7, 0xFCE4, 0x6666,
+ 0xFCE5, 0x6703, 0xFCE6, 0x6A9C, 0xFCE7, 0x6DEE, 0xFCE8, 0x6FAE, 0xFCE9, 0x7070, 0xFCEA, 0x736A, 0xFCEB, 0x7E6A, 0xFCEC, 0x81BE,
+ 0xFCED, 0x8334, 0xFCEE, 0x86D4, 0xFCEF, 0x8AA8, 0xFCF0, 0x8CC4, 0xFCF1, 0x5283, 0xFCF2, 0x7372, 0xFCF3, 0x5B96, 0xFCF4, 0x6A6B,
+ 0xFCF5, 0x9404, 0xFCF6, 0x54EE, 0xFCF7, 0x5686, 0xFCF8, 0x5B5D, 0xFCF9, 0x6548, 0xFCFA, 0x6585, 0xFCFB, 0x66C9, 0xFCFC, 0x689F,
+ 0xFCFD, 0x6D8D, 0xFCFE, 0x6DC6, 0xFDA1, 0x723B, 0xFDA2, 0x80B4, 0xFDA3, 0x9175, 0xFDA4, 0x9A4D, 0xFDA5, 0x4FAF, 0xFDA6, 0x5019,
+ 0xFDA7, 0x539A, 0xFDA8, 0x540E, 0xFDA9, 0x543C, 0xFDAA, 0x5589, 0xFDAB, 0x55C5, 0xFDAC, 0x5E3F, 0xFDAD, 0x5F8C, 0xFDAE, 0x673D,
+ 0xFDAF, 0x7166, 0xFDB0, 0x73DD, 0xFDB1, 0x9005, 0xFDB2, 0x52DB, 0xFDB3, 0x52F3, 0xFDB4, 0x5864, 0xFDB5, 0x58CE, 0xFDB6, 0x7104,
+ 0xFDB7, 0x718F, 0xFDB8, 0x71FB, 0xFDB9, 0x85B0, 0xFDBA, 0x8A13, 0xFDBB, 0x6688, 0xFDBC, 0x85A8, 0xFDBD, 0x55A7, 0xFDBE, 0x6684,
+ 0xFDBF, 0x714A, 0xFDC0, 0x8431, 0xFDC1, 0x5349, 0xFDC2, 0x5599, 0xFDC3, 0x6BC1, 0xFDC4, 0x5F59, 0xFDC5, 0x5FBD, 0xFDC6, 0x63EE,
+ 0xFDC7, 0x6689, 0xFDC8, 0x7147, 0xFDC9, 0x8AF1, 0xFDCA, 0x8F1D, 0xFDCB, 0x9EBE, 0xFDCC, 0x4F11, 0xFDCD, 0x643A, 0xFDCE, 0x70CB,
+ 0xFDCF, 0x7566, 0xFDD0, 0x8667, 0xFDD1, 0x6064, 0xFDD2, 0x8B4E, 0xFDD3, 0x9DF8, 0xFDD4, 0x5147, 0xFDD5, 0x51F6, 0xFDD6, 0x5308,
+ 0xFDD7, 0x6D36, 0xFDD8, 0x80F8, 0xFDD9, 0x9ED1, 0xFDDA, 0x6615, 0xFDDB, 0x6B23, 0xFDDC, 0x7098, 0xFDDD, 0x75D5, 0xFDDE, 0x5403,
+ 0xFDDF, 0x5C79, 0xFDE0, 0x7D07, 0xFDE1, 0x8A16, 0xFDE2, 0x6B20, 0xFDE3, 0x6B3D, 0xFDE4, 0x6B46, 0xFDE5, 0x5438, 0xFDE6, 0x6070,
+ 0xFDE7, 0x6D3D, 0xFDE8, 0x7FD5, 0xFDE9, 0x8208, 0xFDEA, 0x50D6, 0xFDEB, 0x51DE, 0xFDEC, 0x559C, 0xFDED, 0x566B, 0xFDEE, 0x56CD,
+ 0xFDEF, 0x59EC, 0xFDF0, 0x5B09, 0xFDF1, 0x5E0C, 0xFDF2, 0x6199, 0xFDF3, 0x6198, 0xFDF4, 0x6231, 0xFDF5, 0x665E, 0xFDF6, 0x66E6,
+ 0xFDF7, 0x7199, 0xFDF8, 0x71B9, 0xFDF9, 0x71BA, 0xFDFA, 0x72A7, 0xFDFB, 0x79A7, 0xFDFC, 0x7A00, 0xFDFD, 0x7FB2, 0xFDFE, 0x8A70,
+ 0, 0
+};
+#endif
+
+#if FF_CODE_PAGE == 950 || FF_CODE_PAGE == 0 /* Traditional Chinese */
+static const WCHAR uni2oem950[] = { /* Unicode --> Big5 pairs */
+ 0x00A7, 0xA1B1, 0x00AF, 0xA1C2, 0x00B0, 0xA258, 0x00B1, 0xA1D3, 0x00B7, 0xA150, 0x00D7, 0xA1D1, 0x00F7, 0xA1D2, 0x02C7, 0xA3BE,
+ 0x02C9, 0xA3BC, 0x02CA, 0xA3BD, 0x02CB, 0xA3BF, 0x02CD, 0xA1C5, 0x02D9, 0xA3BB, 0x0391, 0xA344, 0x0392, 0xA345, 0x0393, 0xA346,
+ 0x0394, 0xA347, 0x0395, 0xA348, 0x0396, 0xA349, 0x0397, 0xA34A, 0x0398, 0xA34B, 0x0399, 0xA34C, 0x039A, 0xA34D, 0x039B, 0xA34E,
+ 0x039C, 0xA34F, 0x039D, 0xA350, 0x039E, 0xA351, 0x039F, 0xA352, 0x03A0, 0xA353, 0x03A1, 0xA354, 0x03A3, 0xA355, 0x03A4, 0xA356,
+ 0x03A5, 0xA357, 0x03A6, 0xA358, 0x03A7, 0xA359, 0x03A8, 0xA35A, 0x03A9, 0xA35B, 0x03B1, 0xA35C, 0x03B2, 0xA35D, 0x03B3, 0xA35E,
+ 0x03B4, 0xA35F, 0x03B5, 0xA360, 0x03B6, 0xA361, 0x03B7, 0xA362, 0x03B8, 0xA363, 0x03B9, 0xA364, 0x03BA, 0xA365, 0x03BB, 0xA366,
+ 0x03BC, 0xA367, 0x03BD, 0xA368, 0x03BE, 0xA369, 0x03BF, 0xA36A, 0x03C0, 0xA36B, 0x03C1, 0xA36C, 0x03C3, 0xA36D, 0x03C4, 0xA36E,
+ 0x03C5, 0xA36F, 0x03C6, 0xA370, 0x03C7, 0xA371, 0x03C8, 0xA372, 0x03C9, 0xA373, 0x2013, 0xA156, 0x2014, 0xA158, 0x2018, 0xA1A5,
+ 0x2019, 0xA1A6, 0x201C, 0xA1A7, 0x201D, 0xA1A8, 0x2025, 0xA14C, 0x2026, 0xA14B, 0x2027, 0xA145, 0x2032, 0xA1AC, 0x2035, 0xA1AB,
+ 0x203B, 0xA1B0, 0x20AC, 0xA3E1, 0x2103, 0xA24A, 0x2105, 0xA1C1, 0x2109, 0xA24B, 0x2160, 0xA2B9, 0x2161, 0xA2BA, 0x2162, 0xA2BB,
+ 0x2163, 0xA2BC, 0x2164, 0xA2BD, 0x2165, 0xA2BE, 0x2166, 0xA2BF, 0x2167, 0xA2C0, 0x2168, 0xA2C1, 0x2169, 0xA2C2, 0x2190, 0xA1F6,
+ 0x2191, 0xA1F4, 0x2192, 0xA1F7, 0x2193, 0xA1F5, 0x2196, 0xA1F8, 0x2197, 0xA1F9, 0x2198, 0xA1FB, 0x2199, 0xA1FA, 0x2215, 0xA241,
+ 0x221A, 0xA1D4, 0x221E, 0xA1DB, 0x221F, 0xA1E8, 0x2220, 0xA1E7, 0x2223, 0xA1FD, 0x2225, 0xA1FC, 0x2229, 0xA1E4, 0x222A, 0xA1E5,
+ 0x222B, 0xA1EC, 0x222E, 0xA1ED, 0x2234, 0xA1EF, 0x2235, 0xA1EE, 0x2252, 0xA1DC, 0x2260, 0xA1DA, 0x2261, 0xA1DD, 0x2266, 0xA1D8,
+ 0x2267, 0xA1D9, 0x2295, 0xA1F2, 0x2299, 0xA1F3, 0x22A5, 0xA1E6, 0x22BF, 0xA1E9, 0x2500, 0xA277, 0x2502, 0xA278, 0x250C, 0xA27A,
+ 0x2510, 0xA27B, 0x2514, 0xA27C, 0x2518, 0xA27D, 0x251C, 0xA275, 0x2524, 0xA274, 0x252C, 0xA273, 0x2534, 0xA272, 0x253C, 0xA271,
+ 0x2550, 0xA2A4, 0x2550, 0xF9F9, 0x2551, 0xF9F8, 0x2552, 0xF9E6, 0x2553, 0xF9EF, 0x2554, 0xF9DD, 0x2555, 0xF9E8, 0x2556, 0xF9F1,
+ 0x2557, 0xF9DF, 0x2558, 0xF9EC, 0x2559, 0xF9F5, 0x255A, 0xF9E3, 0x255B, 0xF9EE, 0x255C, 0xF9F7, 0x255D, 0xF9E5, 0x255E, 0xA2A5,
+ 0x255E, 0xF9E9, 0x255F, 0xF9F2, 0x2560, 0xF9E0, 0x2561, 0xA2A7, 0x2561, 0xF9EB, 0x2562, 0xF9F4, 0x2563, 0xF9E2, 0x2564, 0xF9E7,
+ 0x2565, 0xF9F0, 0x2566, 0xF9DE, 0x2567, 0xF9ED, 0x2568, 0xF9F6, 0x2569, 0xF9E4, 0x256A, 0xA2A6, 0x256A, 0xF9EA, 0x256B, 0xF9F3,
+ 0x256C, 0xF9E1, 0x256D, 0xA27E, 0x256D, 0xF9FA, 0x256E, 0xA2A1, 0x256E, 0xF9FB, 0x256F, 0xA2A3, 0x256F, 0xF9FD, 0x2570, 0xA2A2,
+ 0x2570, 0xF9FC, 0x2571, 0xA2AC, 0x2572, 0xA2AD, 0x2573, 0xA2AE, 0x2574, 0xA15A, 0x2581, 0xA262, 0x2582, 0xA263, 0x2583, 0xA264,
+ 0x2584, 0xA265, 0x2585, 0xA266, 0x2586, 0xA267, 0x2587, 0xA268, 0x2588, 0xA269, 0x2589, 0xA270, 0x258A, 0xA26F, 0x258B, 0xA26E,
+ 0x258C, 0xA26D, 0x258D, 0xA26C, 0x258E, 0xA26B, 0x258F, 0xA26A, 0x2593, 0xF9FE, 0x2594, 0xA276, 0x2595, 0xA279, 0x25A0, 0xA1BD,
+ 0x25A1, 0xA1BC, 0x25B2, 0xA1B6, 0x25B3, 0xA1B5, 0x25BC, 0xA1BF, 0x25BD, 0xA1BE, 0x25C6, 0xA1BB, 0x25C7, 0xA1BA, 0x25CB, 0xA1B3,
+ 0x25CE, 0xA1B7, 0x25CF, 0xA1B4, 0x25E2, 0xA2A8, 0x25E3, 0xA2A9, 0x25E4, 0xA2AB, 0x25E5, 0xA2AA, 0x2605, 0xA1B9, 0x2606, 0xA1B8,
+ 0x2640, 0xA1F0, 0x2642, 0xA1F1, 0x3000, 0xA140, 0x3001, 0xA142, 0x3002, 0xA143, 0x3003, 0xA1B2, 0x3008, 0xA171, 0x3009, 0xA172,
+ 0x300A, 0xA16D, 0x300B, 0xA16E, 0x300C, 0xA175, 0x300D, 0xA176, 0x300E, 0xA179, 0x300F, 0xA17A, 0x3010, 0xA169, 0x3011, 0xA16A,
+ 0x3012, 0xA245, 0x3014, 0xA165, 0x3015, 0xA166, 0x301D, 0xA1A9, 0x301E, 0xA1AA, 0x3021, 0xA2C3, 0x3022, 0xA2C4, 0x3023, 0xA2C5,
+ 0x3024, 0xA2C6, 0x3025, 0xA2C7, 0x3026, 0xA2C8, 0x3027, 0xA2C9, 0x3028, 0xA2CA, 0x3029, 0xA2CB, 0x3105, 0xA374, 0x3106, 0xA375,
+ 0x3107, 0xA376, 0x3108, 0xA377, 0x3109, 0xA378, 0x310A, 0xA379, 0x310B, 0xA37A, 0x310C, 0xA37B, 0x310D, 0xA37C, 0x310E, 0xA37D,
+ 0x310F, 0xA37E, 0x3110, 0xA3A1, 0x3111, 0xA3A2, 0x3112, 0xA3A3, 0x3113, 0xA3A4, 0x3114, 0xA3A5, 0x3115, 0xA3A6, 0x3116, 0xA3A7,
+ 0x3117, 0xA3A8, 0x3118, 0xA3A9, 0x3119, 0xA3AA, 0x311A, 0xA3AB, 0x311B, 0xA3AC, 0x311C, 0xA3AD, 0x311D, 0xA3AE, 0x311E, 0xA3AF,
+ 0x311F, 0xA3B0, 0x3120, 0xA3B1, 0x3121, 0xA3B2, 0x3122, 0xA3B3, 0x3123, 0xA3B4, 0x3124, 0xA3B5, 0x3125, 0xA3B6, 0x3126, 0xA3B7,
+ 0x3127, 0xA3B8, 0x3128, 0xA3B9, 0x3129, 0xA3BA, 0x32A3, 0xA1C0, 0x338E, 0xA255, 0x338F, 0xA256, 0x339C, 0xA250, 0x339D, 0xA251,
+ 0x339E, 0xA252, 0x33A1, 0xA254, 0x33C4, 0xA257, 0x33CE, 0xA253, 0x33D1, 0xA1EB, 0x33D2, 0xA1EA, 0x33D5, 0xA24F, 0x4E00, 0xA440,
+ 0x4E01, 0xA442, 0x4E03, 0xA443, 0x4E07, 0xC945, 0x4E08, 0xA456, 0x4E09, 0xA454, 0x4E0A, 0xA457, 0x4E0B, 0xA455, 0x4E0C, 0xC946,
+ 0x4E0D, 0xA4A3, 0x4E0E, 0xC94F, 0x4E0F, 0xC94D, 0x4E10, 0xA4A2, 0x4E11, 0xA4A1, 0x4E14, 0xA542, 0x4E15, 0xA541, 0x4E16, 0xA540,
+ 0x4E18, 0xA543, 0x4E19, 0xA4FE, 0x4E1E, 0xA5E0, 0x4E1F, 0xA5E1, 0x4E26, 0xA8C3, 0x4E2B, 0xA458, 0x4E2D, 0xA4A4, 0x4E2E, 0xC950,
+ 0x4E30, 0xA4A5, 0x4E31, 0xC963, 0x4E32, 0xA6EA, 0x4E33, 0xCBB1, 0x4E38, 0xA459, 0x4E39, 0xA4A6, 0x4E3B, 0xA544, 0x4E3C, 0xC964,
+ 0x4E42, 0xC940, 0x4E43, 0xA444, 0x4E45, 0xA45B, 0x4E47, 0xC947, 0x4E48, 0xA45C, 0x4E4B, 0xA4A7, 0x4E4D, 0xA545, 0x4E4E, 0xA547,
+ 0x4E4F, 0xA546, 0x4E52, 0xA5E2, 0x4E53, 0xA5E3, 0x4E56, 0xA8C4, 0x4E58, 0xADBC, 0x4E59, 0xA441, 0x4E5C, 0xC941, 0x4E5D, 0xA445,
+ 0x4E5E, 0xA45E, 0x4E5F, 0xA45D, 0x4E69, 0xA5E4, 0x4E73, 0xA8C5, 0x4E7E, 0xB0AE, 0x4E7F, 0xD44B, 0x4E82, 0xB6C3, 0x4E83, 0xDCB1,
+ 0x4E84, 0xDCB2, 0x4E86, 0xA446, 0x4E88, 0xA4A9, 0x4E8B, 0xA8C6, 0x4E8C, 0xA447, 0x4E8D, 0xC948, 0x4E8E, 0xA45F, 0x4E91, 0xA4AA,
+ 0x4E92, 0xA4AC, 0x4E93, 0xC951, 0x4E94, 0xA4AD, 0x4E95, 0xA4AB, 0x4E99, 0xA5E5, 0x4E9B, 0xA8C7, 0x4E9E, 0xA8C8, 0x4E9F, 0xAB45,
+ 0x4EA1, 0xA460, 0x4EA2, 0xA4AE, 0x4EA4, 0xA5E6, 0x4EA5, 0xA5E8, 0x4EA6, 0xA5E7, 0x4EA8, 0xA6EB, 0x4EAB, 0xA8C9, 0x4EAC, 0xA8CA,
+ 0x4EAD, 0xAB46, 0x4EAE, 0xAB47, 0x4EB3, 0xADBD, 0x4EB6, 0xDCB3, 0x4EB9, 0xF6D6, 0x4EBA, 0xA448, 0x4EC0, 0xA4B0, 0x4EC1, 0xA4AF,
+ 0x4EC2, 0xC952, 0x4EC3, 0xA4B1, 0x4EC4, 0xA4B7, 0x4EC6, 0xA4B2, 0x4EC7, 0xA4B3, 0x4EC8, 0xC954, 0x4EC9, 0xC953, 0x4ECA, 0xA4B5,
+ 0x4ECB, 0xA4B6, 0x4ECD, 0xA4B4, 0x4ED4, 0xA54A, 0x4ED5, 0xA54B, 0x4ED6, 0xA54C, 0x4ED7, 0xA54D, 0x4ED8, 0xA549, 0x4ED9, 0xA550,
+ 0x4EDA, 0xC96A, 0x4EDC, 0xC966, 0x4EDD, 0xC969, 0x4EDE, 0xA551, 0x4EDF, 0xA561, 0x4EE1, 0xC968, 0x4EE3, 0xA54E, 0x4EE4, 0xA54F,
+ 0x4EE5, 0xA548, 0x4EE8, 0xC965, 0x4EE9, 0xC967, 0x4EF0, 0xA5F5, 0x4EF1, 0xC9B0, 0x4EF2, 0xA5F2, 0x4EF3, 0xA5F6, 0x4EF4, 0xC9BA,
+ 0x4EF5, 0xC9AE, 0x4EF6, 0xA5F3, 0x4EF7, 0xC9B2, 0x4EFB, 0xA5F4, 0x4EFD, 0xA5F7, 0x4EFF, 0xA5E9, 0x4F00, 0xC9B1, 0x4F01, 0xA5F8,
+ 0x4F02, 0xC9B5, 0x4F04, 0xC9B9, 0x4F05, 0xC9B6, 0x4F08, 0xC9B3, 0x4F09, 0xA5EA, 0x4F0A, 0xA5EC, 0x4F0B, 0xA5F9, 0x4F0D, 0xA5EE,
+ 0x4F0E, 0xC9AB, 0x4F0F, 0xA5F1, 0x4F10, 0xA5EF, 0x4F11, 0xA5F0, 0x4F12, 0xC9BB, 0x4F13, 0xC9B8, 0x4F14, 0xC9AF, 0x4F15, 0xA5ED,
+ 0x4F18, 0xC9AC, 0x4F19, 0xA5EB, 0x4F1D, 0xC9B4, 0x4F22, 0xC9B7, 0x4F2C, 0xC9AD, 0x4F2D, 0xCA66, 0x4F2F, 0xA742, 0x4F30, 0xA6F4,
+ 0x4F33, 0xCA67, 0x4F34, 0xA6F1, 0x4F36, 0xA744, 0x4F38, 0xA6F9, 0x4F3A, 0xA6F8, 0x4F3B, 0xCA5B, 0x4F3C, 0xA6FC, 0x4F3D, 0xA6F7,
+ 0x4F3E, 0xCA60, 0x4F3F, 0xCA68, 0x4F41, 0xCA64, 0x4F43, 0xA6FA, 0x4F46, 0xA6FD, 0x4F47, 0xA6EE, 0x4F48, 0xA747, 0x4F49, 0xCA5D,
+ 0x4F4C, 0xCBBD, 0x4F4D, 0xA6EC, 0x4F4E, 0xA743, 0x4F4F, 0xA6ED, 0x4F50, 0xA6F5, 0x4F51, 0xA6F6, 0x4F52, 0xCA62, 0x4F53, 0xCA5E,
+ 0x4F54, 0xA6FB, 0x4F55, 0xA6F3, 0x4F56, 0xCA5A, 0x4F57, 0xA6EF, 0x4F58, 0xCA65, 0x4F59, 0xA745, 0x4F5A, 0xA748, 0x4F5B, 0xA6F2,
+ 0x4F5C, 0xA740, 0x4F5D, 0xA746, 0x4F5E, 0xA6F0, 0x4F5F, 0xCA63, 0x4F60, 0xA741, 0x4F61, 0xCA69, 0x4F62, 0xCA5C, 0x4F63, 0xA6FE,
+ 0x4F64, 0xCA5F, 0x4F67, 0xCA61, 0x4F69, 0xA8D8, 0x4F6A, 0xCBBF, 0x4F6B, 0xCBCB, 0x4F6C, 0xA8D0, 0x4F6E, 0xCBCC, 0x4F6F, 0xA8CB,
+ 0x4F70, 0xA8D5, 0x4F73, 0xA8CE, 0x4F74, 0xCBB9, 0x4F75, 0xA8D6, 0x4F76, 0xCBB8, 0x4F77, 0xCBBC, 0x4F78, 0xCBC3, 0x4F79, 0xCBC1,
+ 0x4F7A, 0xA8DE, 0x4F7B, 0xA8D9, 0x4F7C, 0xCBB3, 0x4F7D, 0xCBB5, 0x4F7E, 0xA8DB, 0x4F7F, 0xA8CF, 0x4F80, 0xCBB6, 0x4F81, 0xCBC2,
+ 0x4F82, 0xCBC9, 0x4F83, 0xA8D4, 0x4F84, 0xCBBB, 0x4F85, 0xCBB4, 0x4F86, 0xA8D3, 0x4F87, 0xCBB7, 0x4F88, 0xA8D7, 0x4F89, 0xCBBA,
+ 0x4F8B, 0xA8D2, 0x4F8D, 0xA8CD, 0x4F8F, 0xA8DC, 0x4F90, 0xCBC4, 0x4F91, 0xA8DD, 0x4F92, 0xCBC8, 0x4F94, 0xCBC6, 0x4F95, 0xCBCA,
+ 0x4F96, 0xA8DA, 0x4F97, 0xCBBE, 0x4F98, 0xCBB2, 0x4F9A, 0xCBC0, 0x4F9B, 0xA8D1, 0x4F9C, 0xCBC5, 0x4F9D, 0xA8CC, 0x4F9E, 0xCBC7,
+ 0x4FAE, 0xAB56, 0x4FAF, 0xAB4A, 0x4FB2, 0xCDE0, 0x4FB3, 0xCDE8, 0x4FB5, 0xAB49, 0x4FB6, 0xAB51, 0x4FB7, 0xAB5D, 0x4FB9, 0xCDEE,
+ 0x4FBA, 0xCDEC, 0x4FBB, 0xCDE7, 0x4FBF, 0xAB4B, 0x4FC0, 0xCDED, 0x4FC1, 0xCDE3, 0x4FC2, 0xAB59, 0x4FC3, 0xAB50, 0x4FC4, 0xAB58,
+ 0x4FC5, 0xCDDE, 0x4FC7, 0xCDEA, 0x4FC9, 0xCDE1, 0x4FCA, 0xAB54, 0x4FCB, 0xCDE2, 0x4FCD, 0xCDDD, 0x4FCE, 0xAB5B, 0x4FCF, 0xAB4E,
+ 0x4FD0, 0xAB57, 0x4FD1, 0xAB4D, 0x4FD3, 0xCDDF, 0x4FD4, 0xCDE4, 0x4FD6, 0xCDEB, 0x4FD7, 0xAB55, 0x4FD8, 0xAB52, 0x4FD9, 0xCDE6,
+ 0x4FDA, 0xAB5A, 0x4FDB, 0xCDE9, 0x4FDC, 0xCDE5, 0x4FDD, 0xAB4F, 0x4FDE, 0xAB5C, 0x4FDF, 0xAB53, 0x4FE0, 0xAB4C, 0x4FE1, 0xAB48,
+ 0x4FEC, 0xCDEF, 0x4FEE, 0xADD7, 0x4FEF, 0xADC1, 0x4FF1, 0xADD1, 0x4FF3, 0xADD6, 0x4FF4, 0xD0D0, 0x4FF5, 0xD0CF, 0x4FF6, 0xD0D4,
+ 0x4FF7, 0xD0D5, 0x4FF8, 0xADC4, 0x4FFA, 0xADCD, 0x4FFE, 0xADDA, 0x5000, 0xADCE, 0x5005, 0xD0C9, 0x5006, 0xADC7, 0x5007, 0xD0CA,
+ 0x5009, 0xADDC, 0x500B, 0xADD3, 0x500C, 0xADBE, 0x500D, 0xADBF, 0x500E, 0xD0DD, 0x500F, 0xB0BF, 0x5011, 0xADCC, 0x5012, 0xADCB,
+ 0x5013, 0xD0CB, 0x5014, 0xADCF, 0x5015, 0xD45B, 0x5016, 0xADC6, 0x5017, 0xD0D6, 0x5018, 0xADD5, 0x5019, 0xADD4, 0x501A, 0xADCA,
+ 0x501B, 0xD0CE, 0x501C, 0xD0D7, 0x501E, 0xD0C8, 0x501F, 0xADC9, 0x5020, 0xD0D8, 0x5021, 0xADD2, 0x5022, 0xD0CC, 0x5023, 0xADC0,
+ 0x5025, 0xADC3, 0x5026, 0xADC2, 0x5027, 0xD0D9, 0x5028, 0xADD0, 0x5029, 0xADC5, 0x502A, 0xADD9, 0x502B, 0xADDB, 0x502C, 0xD0D3,
+ 0x502D, 0xADD8, 0x502F, 0xD0DB, 0x5030, 0xD0CD, 0x5031, 0xD0DC, 0x5033, 0xD0D1, 0x5035, 0xD0DA, 0x5037, 0xD0D2, 0x503C, 0xADC8,
+ 0x5040, 0xD463, 0x5041, 0xD457, 0x5043, 0xB0B3, 0x5045, 0xD45C, 0x5046, 0xD462, 0x5047, 0xB0B2, 0x5048, 0xD455, 0x5049, 0xB0B6,
+ 0x504A, 0xD459, 0x504B, 0xD452, 0x504C, 0xB0B4, 0x504D, 0xD456, 0x504E, 0xB0B9, 0x504F, 0xB0BE, 0x5051, 0xD467, 0x5053, 0xD451,
+ 0x5055, 0xB0BA, 0x5057, 0xD466, 0x505A, 0xB0B5, 0x505B, 0xD458, 0x505C, 0xB0B1, 0x505D, 0xD453, 0x505E, 0xD44F, 0x505F, 0xD45D,
+ 0x5060, 0xD450, 0x5061, 0xD44E, 0x5062, 0xD45A, 0x5063, 0xD460, 0x5064, 0xD461, 0x5065, 0xB0B7, 0x5068, 0xD85B, 0x5069, 0xD45E,
+ 0x506A, 0xD44D, 0x506B, 0xD45F, 0x506D, 0xB0C1, 0x506E, 0xD464, 0x506F, 0xB0C0, 0x5070, 0xD44C, 0x5072, 0xD454, 0x5073, 0xD465,
+ 0x5074, 0xB0BC, 0x5075, 0xB0BB, 0x5076, 0xB0B8, 0x5077, 0xB0BD, 0x507A, 0xB0AF, 0x507D, 0xB0B0, 0x5080, 0xB3C8, 0x5082, 0xD85E,
+ 0x5083, 0xD857, 0x5085, 0xB3C5, 0x5087, 0xD85F, 0x508B, 0xD855, 0x508C, 0xD858, 0x508D, 0xB3C4, 0x508E, 0xD859, 0x5091, 0xB3C7,
+ 0x5092, 0xD85D, 0x5094, 0xD853, 0x5095, 0xD852, 0x5096, 0xB3C9, 0x5098, 0xB3CA, 0x5099, 0xB3C6, 0x509A, 0xB3CB, 0x509B, 0xD851,
+ 0x509C, 0xD85C, 0x509D, 0xD85A, 0x509E, 0xD854, 0x50A2, 0xB3C3, 0x50A3, 0xD856, 0x50AC, 0xB6CA, 0x50AD, 0xB6C4, 0x50AE, 0xDCB7,
+ 0x50AF, 0xB6CD, 0x50B0, 0xDCBD, 0x50B1, 0xDCC0, 0x50B2, 0xB6C6, 0x50B3, 0xB6C7, 0x50B4, 0xDCBA, 0x50B5, 0xB6C5, 0x50B6, 0xDCC3,
+ 0x50B7, 0xB6CB, 0x50B8, 0xDCC4, 0x50BA, 0xDCBF, 0x50BB, 0xB6CC, 0x50BD, 0xDCB4, 0x50BE, 0xB6C9, 0x50BF, 0xDCB5, 0x50C1, 0xDCBE,
+ 0x50C2, 0xDCBC, 0x50C4, 0xDCB8, 0x50C5, 0xB6C8, 0x50C6, 0xDCB6, 0x50C7, 0xB6CE, 0x50C8, 0xDCBB, 0x50C9, 0xDCC2, 0x50CA, 0xDCB9,
+ 0x50CB, 0xDCC1, 0x50CE, 0xB9B6, 0x50CF, 0xB9B3, 0x50D1, 0xB9B4, 0x50D3, 0xE0F9, 0x50D4, 0xE0F1, 0x50D5, 0xB9B2, 0x50D6, 0xB9AF,
+ 0x50D7, 0xE0F2, 0x50DA, 0xB9B1, 0x50DB, 0xE0F5, 0x50DD, 0xE0F7, 0x50E0, 0xE0FE, 0x50E3, 0xE0FD, 0x50E4, 0xE0F8, 0x50E5, 0xB9AE,
+ 0x50E6, 0xE0F0, 0x50E7, 0xB9AC, 0x50E8, 0xE0F3, 0x50E9, 0xB9B7, 0x50EA, 0xE0F6, 0x50EC, 0xE0FA, 0x50ED, 0xB9B0, 0x50EE, 0xB9AD,
+ 0x50EF, 0xE0FC, 0x50F0, 0xE0FB, 0x50F1, 0xB9B5, 0x50F3, 0xE0F4, 0x50F5, 0xBBF8, 0x50F6, 0xE4EC, 0x50F8, 0xE4E9, 0x50F9, 0xBBF9,
+ 0x50FB, 0xBBF7, 0x50FD, 0xE4F0, 0x50FE, 0xE4ED, 0x50FF, 0xE4E6, 0x5100, 0xBBF6, 0x5102, 0xBBFA, 0x5103, 0xE4E7, 0x5104, 0xBBF5,
+ 0x5105, 0xBBFD, 0x5106, 0xE4EA, 0x5107, 0xE4EB, 0x5108, 0xBBFB, 0x5109, 0xBBFC, 0x510A, 0xE4F1, 0x510B, 0xE4EE, 0x510C, 0xE4EF,
+ 0x5110, 0xBEAA, 0x5111, 0xE8F8, 0x5112, 0xBEA7, 0x5113, 0xE8F5, 0x5114, 0xBEA9, 0x5115, 0xBEAB, 0x5117, 0xE8F6, 0x5118, 0xBEA8,
+ 0x511A, 0xE8F7, 0x511C, 0xE8F4, 0x511F, 0xC076, 0x5120, 0xECBD, 0x5121, 0xC077, 0x5122, 0xECBB, 0x5124, 0xECBC, 0x5125, 0xECBA,
+ 0x5126, 0xECB9, 0x5129, 0xECBE, 0x512A, 0xC075, 0x512D, 0xEFB8, 0x512E, 0xEFB9, 0x5130, 0xE4E8, 0x5131, 0xEFB7, 0x5132, 0xC078,
+ 0x5133, 0xC35F, 0x5134, 0xF1EB, 0x5135, 0xF1EC, 0x5137, 0xC4D7, 0x5138, 0xC4D8, 0x5139, 0xF5C1, 0x513A, 0xF5C0, 0x513B, 0xC56C,
+ 0x513C, 0xC56B, 0x513D, 0xF7D0, 0x513F, 0xA449, 0x5140, 0xA461, 0x5141, 0xA4B9, 0x5143, 0xA4B8, 0x5144, 0xA553, 0x5145, 0xA552,
+ 0x5146, 0xA5FC, 0x5147, 0xA5FB, 0x5148, 0xA5FD, 0x5149, 0xA5FA, 0x514B, 0xA74A, 0x514C, 0xA749, 0x514D, 0xA74B, 0x5152, 0xA8E0,
+ 0x5154, 0xA8DF, 0x5155, 0xA8E1, 0x5157, 0xAB5E, 0x5159, 0xA259, 0x515A, 0xD0DE, 0x515B, 0xA25A, 0x515C, 0xB0C2, 0x515D, 0xA25C,
+ 0x515E, 0xA25B, 0x515F, 0xD860, 0x5161, 0xA25D, 0x5162, 0xB9B8, 0x5163, 0xA25E, 0x5165, 0xA44A, 0x5167, 0xA4BA, 0x5168, 0xA5FE,
+ 0x5169, 0xA8E2, 0x516B, 0xA44B, 0x516C, 0xA4BD, 0x516D, 0xA4BB, 0x516E, 0xA4BC, 0x5171, 0xA640, 0x5175, 0xA74C, 0x5176, 0xA8E4,
+ 0x5177, 0xA8E3, 0x5178, 0xA8E5, 0x517C, 0xADDD, 0x5180, 0xBEAC, 0x5187, 0xC94E, 0x5189, 0xA554, 0x518A, 0xA555, 0x518D, 0xA641,
+ 0x518F, 0xCA6A, 0x5191, 0xAB60, 0x5192, 0xAB5F, 0x5193, 0xD0E0, 0x5194, 0xD0DF, 0x5195, 0xB0C3, 0x5197, 0xA4BE, 0x5198, 0xC955,
+ 0x519E, 0xCBCD, 0x51A0, 0xAB61, 0x51A2, 0xADE0, 0x51A4, 0xADDE, 0x51A5, 0xADDF, 0x51AA, 0xBEAD, 0x51AC, 0xA556, 0x51B0, 0xA642,
+ 0x51B1, 0xC9BC, 0x51B6, 0xA74D, 0x51B7, 0xA74E, 0x51B9, 0xCA6B, 0x51BC, 0xCBCE, 0x51BD, 0xA8E6, 0x51BE, 0xCBCF, 0x51C4, 0xD0E2,
+ 0x51C5, 0xD0E3, 0x51C6, 0xADE3, 0x51C8, 0xD0E4, 0x51CA, 0xD0E1, 0x51CB, 0xADE4, 0x51CC, 0xADE2, 0x51CD, 0xADE1, 0x51CE, 0xD0E5,
+ 0x51D0, 0xD468, 0x51D4, 0xD861, 0x51D7, 0xDCC5, 0x51D8, 0xE140, 0x51DC, 0xBBFE, 0x51DD, 0xBEAE, 0x51DE, 0xE8F9, 0x51E0, 0xA44C,
+ 0x51E1, 0xA45A, 0x51F0, 0xB0C4, 0x51F1, 0xB3CD, 0x51F3, 0xB9B9, 0x51F5, 0xC942, 0x51F6, 0xA4BF, 0x51F8, 0xA559, 0x51F9, 0xA557,
+ 0x51FA, 0xA558, 0x51FD, 0xA8E7, 0x5200, 0xA44D, 0x5201, 0xA44E, 0x5203, 0xA462, 0x5206, 0xA4C0, 0x5207, 0xA4C1, 0x5208, 0xA4C2,
+ 0x5209, 0xC9BE, 0x520A, 0xA55A, 0x520C, 0xC96B, 0x520E, 0xA646, 0x5210, 0xC9BF, 0x5211, 0xA644, 0x5212, 0xA645, 0x5213, 0xC9BD,
+ 0x5216, 0xA647, 0x5217, 0xA643, 0x521C, 0xCA6C, 0x521D, 0xAAEC, 0x521E, 0xCA6D, 0x5221, 0xCA6E, 0x5224, 0xA750, 0x5225, 0xA74F,
+ 0x5228, 0xA753, 0x5229, 0xA751, 0x522A, 0xA752, 0x522E, 0xA8ED, 0x5230, 0xA8EC, 0x5231, 0xCBD4, 0x5232, 0xCBD1, 0x5233, 0xCBD2,
+ 0x5235, 0xCBD0, 0x5236, 0xA8EE, 0x5237, 0xA8EA, 0x5238, 0xA8E9, 0x523A, 0xA8EB, 0x523B, 0xA8E8, 0x5241, 0xA8EF, 0x5243, 0xAB63,
+ 0x5244, 0xCDF0, 0x5246, 0xCBD3, 0x5247, 0xAB68, 0x5249, 0xCDF1, 0x524A, 0xAB64, 0x524B, 0xAB67, 0x524C, 0xAB66, 0x524D, 0xAB65,
+ 0x524E, 0xAB62, 0x5252, 0xD0E8, 0x5254, 0xADE7, 0x5255, 0xD0EB, 0x5256, 0xADE5, 0x525A, 0xD0E7, 0x525B, 0xADE8, 0x525C, 0xADE6,
+ 0x525D, 0xADE9, 0x525E, 0xD0E9, 0x525F, 0xD0EA, 0x5261, 0xD0E6, 0x5262, 0xD0EC, 0x5269, 0xB3D1, 0x526A, 0xB0C5, 0x526B, 0xD469,
+ 0x526C, 0xD46B, 0x526D, 0xD46A, 0x526E, 0xD46C, 0x526F, 0xB0C6, 0x5272, 0xB3CE, 0x5274, 0xB3CF, 0x5275, 0xB3D0, 0x5277, 0xB6D0,
+ 0x5278, 0xDCC7, 0x527A, 0xDCC6, 0x527B, 0xDCC8, 0x527C, 0xDCC9, 0x527D, 0xB6D1, 0x527F, 0xB6CF, 0x5280, 0xE141, 0x5281, 0xE142,
+ 0x5282, 0xB9BB, 0x5283, 0xB9BA, 0x5284, 0xE35A, 0x5287, 0xBC40, 0x5288, 0xBC41, 0x5289, 0xBC42, 0x528A, 0xBC44, 0x528B, 0xE4F2,
+ 0x528C, 0xE4F3, 0x528D, 0xBC43, 0x5291, 0xBEAF, 0x5293, 0xBEB0, 0x5296, 0xF1ED, 0x5297, 0xF5C3, 0x5298, 0xF5C2, 0x5299, 0xF7D1,
+ 0x529B, 0xA44F, 0x529F, 0xA55C, 0x52A0, 0xA55B, 0x52A3, 0xA648, 0x52A6, 0xC9C0, 0x52A9, 0xA755, 0x52AA, 0xA756, 0x52AB, 0xA754,
+ 0x52AC, 0xA757, 0x52AD, 0xCA6F, 0x52AE, 0xCA70, 0x52BB, 0xA8F1, 0x52BC, 0xCBD5, 0x52BE, 0xA8F0, 0x52C0, 0xCDF2, 0x52C1, 0xAB6C,
+ 0x52C2, 0xCDF3, 0x52C3, 0xAB6B, 0x52C7, 0xAB69, 0x52C9, 0xAB6A, 0x52CD, 0xD0ED, 0x52D2, 0xB0C7, 0x52D3, 0xD46E, 0x52D5, 0xB0CA,
+ 0x52D6, 0xD46D, 0x52D7, 0xB1E5, 0x52D8, 0xB0C9, 0x52D9, 0xB0C8, 0x52DB, 0xB3D4, 0x52DD, 0xB3D3, 0x52DE, 0xB3D2, 0x52DF, 0xB6D2,
+ 0x52E2, 0xB6D5, 0x52E3, 0xB6D6, 0x52E4, 0xB6D4, 0x52E6, 0xB6D3, 0x52E9, 0xE143, 0x52EB, 0xE144, 0x52EF, 0xE4F5, 0x52F0, 0xBC45,
+ 0x52F1, 0xE4F4, 0x52F3, 0xBEB1, 0x52F4, 0xECBF, 0x52F5, 0xC079, 0x52F7, 0xF1EE, 0x52F8, 0xC455, 0x52FA, 0xA463, 0x52FB, 0xA4C3,
+ 0x52FC, 0xC956, 0x52FE, 0xA4C4, 0x52FF, 0xA4C5, 0x5305, 0xA55D, 0x5306, 0xA55E, 0x5308, 0xA649, 0x5309, 0xCA71, 0x530A, 0xCBD6,
+ 0x530B, 0xCBD7, 0x530D, 0xAB6D, 0x530E, 0xD0EE, 0x530F, 0xB0CC, 0x5310, 0xB0CB, 0x5311, 0xD863, 0x5312, 0xD862, 0x5315, 0xA450,
+ 0x5316, 0xA4C6, 0x5317, 0xA55F, 0x5319, 0xB0CD, 0x531A, 0xC943, 0x531C, 0xC96C, 0x531D, 0xA560, 0x531F, 0xC9C2, 0x5320, 0xA64B,
+ 0x5321, 0xA64A, 0x5322, 0xC9C1, 0x5323, 0xA758, 0x532A, 0xADEA, 0x532D, 0xD46F, 0x532F, 0xB6D7, 0x5330, 0xE145, 0x5331, 0xB9BC,
+ 0x5334, 0xE8FA, 0x5337, 0xF3FD, 0x5339, 0xA4C7, 0x533C, 0xCBD8, 0x533D, 0xCDF4, 0x533E, 0xB0D0, 0x533F, 0xB0CE, 0x5340, 0xB0CF,
+ 0x5341, 0xA2CC, 0x5341, 0xA451, 0x5343, 0xA464, 0x5344, 0xA2CD, 0x5345, 0xA2CE, 0x5345, 0xA4CA, 0x5347, 0xA4C9, 0x5348, 0xA4C8,
+ 0x5349, 0xA563, 0x534A, 0xA562, 0x534C, 0xC96D, 0x534D, 0xC9C3, 0x5351, 0xA8F5, 0x5352, 0xA8F2, 0x5353, 0xA8F4, 0x5354, 0xA8F3,
+ 0x5357, 0xAB6E, 0x535A, 0xB3D5, 0x535C, 0xA452, 0x535E, 0xA4CB, 0x5360, 0xA565, 0x5361, 0xA564, 0x5363, 0xCA72, 0x5366, 0xA8F6,
+ 0x536C, 0xC957, 0x536E, 0xA567, 0x536F, 0xA566, 0x5370, 0xA64C, 0x5371, 0xA64D, 0x5372, 0xCA73, 0x5373, 0xA759, 0x5375, 0xA75A,
+ 0x5377, 0xA8F7, 0x5378, 0xA8F8, 0x5379, 0xA8F9, 0x537B, 0xAB6F, 0x537C, 0xCDF5, 0x537F, 0xADEB, 0x5382, 0xC944, 0x5384, 0xA4CC,
+ 0x538A, 0xC9C4, 0x538E, 0xCA74, 0x538F, 0xCA75, 0x5392, 0xCBD9, 0x5394, 0xCBDA, 0x5396, 0xCDF7, 0x5397, 0xCDF6, 0x5398, 0xCDF9,
+ 0x5399, 0xCDF8, 0x539A, 0xAB70, 0x539C, 0xD470, 0x539D, 0xADED, 0x539E, 0xD0EF, 0x539F, 0xADEC, 0x53A4, 0xD864, 0x53A5, 0xB3D6,
+ 0x53A7, 0xD865, 0x53AC, 0xE146, 0x53AD, 0xB9BD, 0x53B2, 0xBC46, 0x53B4, 0xF1EF, 0x53B9, 0xC958, 0x53BB, 0xA568, 0x53C3, 0xB0D1,
+ 0x53C8, 0xA453, 0x53C9, 0xA465, 0x53CA, 0xA4CE, 0x53CB, 0xA4CD, 0x53CD, 0xA4CF, 0x53D4, 0xA8FB, 0x53D6, 0xA8FA, 0x53D7, 0xA8FC,
+ 0x53DB, 0xAB71, 0x53DF, 0xADEE, 0x53E1, 0xE8FB, 0x53E2, 0xC24F, 0x53E3, 0xA466, 0x53E4, 0xA56A, 0x53E5, 0xA579, 0x53E6, 0xA574,
+ 0x53E8, 0xA56F, 0x53E9, 0xA56E, 0x53EA, 0xA575, 0x53EB, 0xA573, 0x53EC, 0xA56C, 0x53ED, 0xA57A, 0x53EE, 0xA56D, 0x53EF, 0xA569,
+ 0x53F0, 0xA578, 0x53F1, 0xA577, 0x53F2, 0xA576, 0x53F3, 0xA56B, 0x53F5, 0xA572, 0x53F8, 0xA571, 0x53FB, 0xA57B, 0x53FC, 0xA570,
+ 0x5401, 0xA653, 0x5403, 0xA659, 0x5404, 0xA655, 0x5406, 0xA65B, 0x5407, 0xC9C5, 0x5408, 0xA658, 0x5409, 0xA64E, 0x540A, 0xA651,
+ 0x540B, 0xA654, 0x540C, 0xA650, 0x540D, 0xA657, 0x540E, 0xA65A, 0x540F, 0xA64F, 0x5410, 0xA652, 0x5411, 0xA656, 0x5412, 0xA65C,
+ 0x5418, 0xCA7E, 0x5419, 0xCA7B, 0x541B, 0xA767, 0x541C, 0xCA7C, 0x541D, 0xA75B, 0x541E, 0xA75D, 0x541F, 0xA775, 0x5420, 0xA770,
+ 0x5424, 0xCAA5, 0x5425, 0xCA7D, 0x5426, 0xA75F, 0x5427, 0xA761, 0x5428, 0xCAA4, 0x5429, 0xA768, 0x542A, 0xCA78, 0x542B, 0xA774,
+ 0x542C, 0xA776, 0x542D, 0xA75C, 0x542E, 0xA76D, 0x5430, 0xCA76, 0x5431, 0xA773, 0x5433, 0xA764, 0x5435, 0xA76E, 0x5436, 0xA76F,
+ 0x5437, 0xCA77, 0x5438, 0xA76C, 0x5439, 0xA76A, 0x543B, 0xA76B, 0x543C, 0xA771, 0x543D, 0xCAA1, 0x543E, 0xA75E, 0x5440, 0xA772,
+ 0x5441, 0xCAA3, 0x5442, 0xA766, 0x5443, 0xA763, 0x5445, 0xCA7A, 0x5446, 0xA762, 0x5447, 0xCAA6, 0x5448, 0xA765, 0x544A, 0xA769,
+ 0x544E, 0xA760, 0x544F, 0xCAA2, 0x5454, 0xCA79, 0x5460, 0xCBEB, 0x5461, 0xCBEA, 0x5462, 0xA94F, 0x5463, 0xCBED, 0x5464, 0xCBEF,
+ 0x5465, 0xCBE4, 0x5466, 0xCBE7, 0x5467, 0xCBEE, 0x5468, 0xA950, 0x546B, 0xCBE1, 0x546C, 0xCBE5, 0x546F, 0xCBE9, 0x5470, 0xCE49,
+ 0x5471, 0xA94B, 0x5472, 0xCE4D, 0x5473, 0xA8FD, 0x5474, 0xCBE6, 0x5475, 0xA8FE, 0x5476, 0xA94C, 0x5477, 0xA945, 0x5478, 0xA941,
+ 0x547A, 0xCBE2, 0x547B, 0xA944, 0x547C, 0xA949, 0x547D, 0xA952, 0x547E, 0xCBE3, 0x547F, 0xCBDC, 0x5480, 0xA943, 0x5481, 0xCBDD,
+ 0x5482, 0xCBDF, 0x5484, 0xA946, 0x5486, 0xA948, 0x5487, 0xCBDB, 0x5488, 0xCBE0, 0x548B, 0xA951, 0x548C, 0xA94D, 0x548D, 0xCBE8,
+ 0x548E, 0xA953, 0x5490, 0xA94A, 0x5491, 0xCBDE, 0x5492, 0xA947, 0x5495, 0xA942, 0x5496, 0xA940, 0x5498, 0xCBEC, 0x549A, 0xA94E,
+ 0x54A0, 0xCE48, 0x54A1, 0xCDFB, 0x54A2, 0xCE4B, 0x54A5, 0xCDFD, 0x54A6, 0xAB78, 0x54A7, 0xABA8, 0x54A8, 0xAB74, 0x54A9, 0xABA7,
+ 0x54AA, 0xAB7D, 0x54AB, 0xABA4, 0x54AC, 0xAB72, 0x54AD, 0xCDFC, 0x54AE, 0xCE43, 0x54AF, 0xABA3, 0x54B0, 0xCE4F, 0x54B1, 0xABA5,
+ 0x54B3, 0xAB79, 0x54B6, 0xCE45, 0x54B7, 0xCE42, 0x54B8, 0xAB77, 0x54BA, 0xCDFA, 0x54BB, 0xABA6, 0x54BC, 0xCE4A, 0x54BD, 0xAB7C,
+ 0x54BE, 0xCE4C, 0x54BF, 0xABA9, 0x54C0, 0xAB73, 0x54C1, 0xAB7E, 0x54C2, 0xAB7B, 0x54C3, 0xCE40, 0x54C4, 0xABA1, 0x54C5, 0xCE46,
+ 0x54C6, 0xCE47, 0x54C7, 0xAB7A, 0x54C8, 0xABA2, 0x54C9, 0xAB76, 0x54CE, 0xAB75, 0x54CF, 0xCDFE, 0x54D6, 0xCE44, 0x54DE, 0xCE4E,
+ 0x54E0, 0xD144, 0x54E1, 0xADFB, 0x54E2, 0xD0F1, 0x54E4, 0xD0F6, 0x54E5, 0xADF4, 0x54E6, 0xAE40, 0x54E7, 0xD0F4, 0x54E8, 0xADEF,
+ 0x54E9, 0xADF9, 0x54EA, 0xADFE, 0x54EB, 0xD0FB, 0x54ED, 0xADFA, 0x54EE, 0xADFD, 0x54F1, 0xD0FE, 0x54F2, 0xADF5, 0x54F3, 0xD0F5,
+ 0x54F7, 0xD142, 0x54F8, 0xD143, 0x54FA, 0xADF7, 0x54FB, 0xD141, 0x54FC, 0xADF3, 0x54FD, 0xAE43, 0x54FF, 0xD0F8, 0x5501, 0xADF1,
+ 0x5503, 0xD146, 0x5504, 0xD0F9, 0x5505, 0xD0FD, 0x5506, 0xADF6, 0x5507, 0xAE42, 0x5508, 0xD0FA, 0x5509, 0xADFC, 0x550A, 0xD140,
+ 0x550B, 0xD147, 0x550C, 0xD4A1, 0x550E, 0xD145, 0x550F, 0xAE44, 0x5510, 0xADF0, 0x5511, 0xD0FC, 0x5512, 0xD0F3, 0x5514, 0xADF8,
+ 0x5517, 0xD0F2, 0x551A, 0xD0F7, 0x5526, 0xD0F0, 0x5527, 0xAE41, 0x552A, 0xD477, 0x552C, 0xB0E4, 0x552D, 0xD4A7, 0x552E, 0xB0E2,
+ 0x552F, 0xB0DF, 0x5530, 0xD47C, 0x5531, 0xB0DB, 0x5532, 0xD4A2, 0x5533, 0xB0E6, 0x5534, 0xD476, 0x5535, 0xD47B, 0x5536, 0xD47A,
+ 0x5537, 0xADF2, 0x5538, 0xB0E1, 0x5539, 0xD4A5, 0x553B, 0xD4A8, 0x553C, 0xD473, 0x553E, 0xB3E8, 0x5540, 0xD4A9, 0x5541, 0xB0E7,
+ 0x5543, 0xB0D9, 0x5544, 0xB0D6, 0x5545, 0xD47E, 0x5546, 0xB0D3, 0x5548, 0xD4A6, 0x554A, 0xB0DA, 0x554B, 0xD4AA, 0x554D, 0xD474,
+ 0x554E, 0xD4A4, 0x554F, 0xB0DD, 0x5550, 0xD475, 0x5551, 0xD478, 0x5552, 0xD47D, 0x5555, 0xB0DE, 0x5556, 0xB0DC, 0x5557, 0xB0E8,
+ 0x555C, 0xB0E3, 0x555E, 0xB0D7, 0x555F, 0xB1D2, 0x5561, 0xB0D8, 0x5562, 0xD479, 0x5563, 0xB0E5, 0x5564, 0xB0E0, 0x5565, 0xD4A3,
+ 0x5566, 0xB0D5, 0x556A, 0xB0D4, 0x5575, 0xD471, 0x5576, 0xD472, 0x5577, 0xD86A, 0x557B, 0xB3D7, 0x557C, 0xB3DA, 0x557D, 0xD875,
+ 0x557E, 0xB3EE, 0x557F, 0xD878, 0x5580, 0xB3D8, 0x5581, 0xD871, 0x5582, 0xB3DE, 0x5583, 0xB3E4, 0x5584, 0xB5BD, 0x5587, 0xB3E2,
+ 0x5588, 0xD86E, 0x5589, 0xB3EF, 0x558A, 0xB3DB, 0x558B, 0xB3E3, 0x558C, 0xD876, 0x558D, 0xDCD7, 0x558E, 0xD87B, 0x558F, 0xD86F,
+ 0x5591, 0xD866, 0x5592, 0xD873, 0x5593, 0xD86D, 0x5594, 0xB3E1, 0x5595, 0xD879, 0x5598, 0xB3DD, 0x5599, 0xB3F1, 0x559A, 0xB3EA,
+ 0x559C, 0xB3DF, 0x559D, 0xB3DC, 0x559F, 0xB3E7, 0x55A1, 0xD87A, 0x55A2, 0xD86C, 0x55A3, 0xD872, 0x55A4, 0xD874, 0x55A5, 0xD868,
+ 0x55A6, 0xD877, 0x55A7, 0xB3D9, 0x55A8, 0xD867, 0x55AA, 0xB3E0, 0x55AB, 0xB3F0, 0x55AC, 0xB3EC, 0x55AD, 0xD869, 0x55AE, 0xB3E6,
+ 0x55B1, 0xB3ED, 0x55B2, 0xB3E9, 0x55B3, 0xB3E5, 0x55B5, 0xD870, 0x55BB, 0xB3EB, 0x55BF, 0xDCD5, 0x55C0, 0xDCD1, 0x55C2, 0xDCE0,
+ 0x55C3, 0xDCCA, 0x55C4, 0xDCD3, 0x55C5, 0xB6E5, 0x55C6, 0xB6E6, 0x55C7, 0xB6DE, 0x55C8, 0xDCDC, 0x55C9, 0xB6E8, 0x55CA, 0xDCCF,
+ 0x55CB, 0xDCCE, 0x55CC, 0xDCCC, 0x55CD, 0xDCDE, 0x55CE, 0xB6DC, 0x55CF, 0xDCD8, 0x55D0, 0xDCCD, 0x55D1, 0xB6DF, 0x55D2, 0xDCD6,
+ 0x55D3, 0xB6DA, 0x55D4, 0xDCD2, 0x55D5, 0xDCD9, 0x55D6, 0xDCDB, 0x55D9, 0xDCDF, 0x55DA, 0xB6E3, 0x55DB, 0xDCCB, 0x55DC, 0xB6DD,
+ 0x55DD, 0xDCD0, 0x55DF, 0xB6D8, 0x55E1, 0xB6E4, 0x55E2, 0xDCDA, 0x55E3, 0xB6E0, 0x55E4, 0xB6E1, 0x55E5, 0xB6E7, 0x55E6, 0xB6DB,
+ 0x55E7, 0xA25F, 0x55E8, 0xB6D9, 0x55E9, 0xDCD4, 0x55EF, 0xB6E2, 0x55F2, 0xDCDD, 0x55F6, 0xB9CD, 0x55F7, 0xB9C8, 0x55F9, 0xE155,
+ 0x55FA, 0xE151, 0x55FC, 0xE14B, 0x55FD, 0xB9C2, 0x55FE, 0xB9BE, 0x55FF, 0xE154, 0x5600, 0xB9BF, 0x5601, 0xE14E, 0x5602, 0xE150,
+ 0x5604, 0xE153, 0x5606, 0xB9C4, 0x5608, 0xB9CB, 0x5609, 0xB9C5, 0x560C, 0xE149, 0x560D, 0xB9C6, 0x560E, 0xB9C7, 0x560F, 0xE14C,
+ 0x5610, 0xB9CC, 0x5612, 0xE14A, 0x5613, 0xE14F, 0x5614, 0xB9C3, 0x5615, 0xE148, 0x5616, 0xB9C9, 0x5617, 0xB9C1, 0x561B, 0xB9C0,
+ 0x561C, 0xE14D, 0x561D, 0xE152, 0x561F, 0xB9CA, 0x5627, 0xE147, 0x5629, 0xBC4D, 0x562A, 0xE547, 0x562C, 0xE544, 0x562E, 0xBC47,
+ 0x562F, 0xBC53, 0x5630, 0xBC54, 0x5632, 0xBC4A, 0x5633, 0xE542, 0x5634, 0xBC4C, 0x5635, 0xE4F9, 0x5636, 0xBC52, 0x5638, 0xE546,
+ 0x5639, 0xBC49, 0x563A, 0xE548, 0x563B, 0xBC48, 0x563D, 0xE543, 0x563E, 0xE545, 0x563F, 0xBC4B, 0x5640, 0xE541, 0x5641, 0xE4FA,
+ 0x5642, 0xE4F7, 0x5645, 0xD86B, 0x5646, 0xE4FD, 0x5648, 0xE4F6, 0x5649, 0xE4FC, 0x564A, 0xE4FB, 0x564C, 0xE4F8, 0x564E, 0xBC4F,
+ 0x5653, 0xBC4E, 0x5657, 0xBC50, 0x5658, 0xE4FE, 0x5659, 0xBEB2, 0x565A, 0xE540, 0x565E, 0xE945, 0x5660, 0xE8FD, 0x5662, 0xBEBE,
+ 0x5663, 0xE942, 0x5664, 0xBEB6, 0x5665, 0xBEBA, 0x5666, 0xE941, 0x5668, 0xBEB9, 0x5669, 0xBEB5, 0x566A, 0xBEB8, 0x566B, 0xBEB3,
+ 0x566C, 0xBEBD, 0x566D, 0xE943, 0x566E, 0xE8FE, 0x566F, 0xBEBC, 0x5670, 0xE8FC, 0x5671, 0xBEBB, 0x5672, 0xE944, 0x5673, 0xE940,
+ 0x5674, 0xBC51, 0x5676, 0xBEBF, 0x5677, 0xE946, 0x5678, 0xBEB7, 0x5679, 0xBEB4, 0x567E, 0xECC6, 0x567F, 0xECC8, 0x5680, 0xC07B,
+ 0x5681, 0xECC9, 0x5682, 0xECC7, 0x5683, 0xECC5, 0x5684, 0xECC4, 0x5685, 0xC07D, 0x5686, 0xECC3, 0x5687, 0xC07E, 0x568C, 0xECC1,
+ 0x568D, 0xECC2, 0x568E, 0xC07A, 0x568F, 0xC0A1, 0x5690, 0xC07C, 0x5693, 0xECC0, 0x5695, 0xC250, 0x5697, 0xEFBC, 0x5698, 0xEFBA,
+ 0x5699, 0xEFBF, 0x569A, 0xEFBD, 0x569C, 0xEFBB, 0x569D, 0xEFBE, 0x56A5, 0xC360, 0x56A6, 0xF1F2, 0x56A7, 0xF1F3, 0x56A8, 0xC456,
+ 0x56AA, 0xF1F4, 0x56AB, 0xF1F0, 0x56AC, 0xF1F5, 0x56AD, 0xF1F1, 0x56AE, 0xC251, 0x56B2, 0xF3FE, 0x56B3, 0xF441, 0x56B4, 0xC459,
+ 0x56B5, 0xF440, 0x56B6, 0xC458, 0x56B7, 0xC457, 0x56BC, 0xC45A, 0x56BD, 0xF5C5, 0x56BE, 0xF5C6, 0x56C0, 0xC4DA, 0x56C1, 0xC4D9,
+ 0x56C2, 0xC4DB, 0x56C3, 0xF5C4, 0x56C5, 0xF6D8, 0x56C6, 0xF6D7, 0x56C8, 0xC56D, 0x56C9, 0xC56F, 0x56CA, 0xC56E, 0x56CB, 0xF6D9,
+ 0x56CC, 0xC5C8, 0x56CD, 0xF8A6, 0x56D1, 0xC5F1, 0x56D3, 0xF8A5, 0x56D4, 0xF8EE, 0x56D7, 0xC949, 0x56DA, 0xA57D, 0x56DB, 0xA57C,
+ 0x56DD, 0xA65F, 0x56DE, 0xA65E, 0x56DF, 0xC9C7, 0x56E0, 0xA65D, 0x56E1, 0xC9C6, 0x56E4, 0xA779, 0x56E5, 0xCAA9, 0x56E7, 0xCAA8,
+ 0x56EA, 0xA777, 0x56EB, 0xA77A, 0x56EE, 0xCAA7, 0x56F0, 0xA778, 0x56F7, 0xCBF0, 0x56F9, 0xCBF1, 0x56FA, 0xA954, 0x56FF, 0xABAA,
+ 0x5701, 0xD148, 0x5702, 0xD149, 0x5703, 0xAE45, 0x5704, 0xAE46, 0x5707, 0xD4AC, 0x5708, 0xB0E9, 0x5709, 0xB0EB, 0x570A, 0xD4AB,
+ 0x570B, 0xB0EA, 0x570C, 0xD87C, 0x570D, 0xB3F2, 0x5712, 0xB6E9, 0x5713, 0xB6EA, 0x5714, 0xDCE1, 0x5716, 0xB9CF, 0x5718, 0xB9CE,
+ 0x571A, 0xE549, 0x571B, 0xE948, 0x571C, 0xE947, 0x571E, 0xF96B, 0x571F, 0xA467, 0x5720, 0xC959, 0x5722, 0xC96E, 0x5723, 0xC96F,
+ 0x5728, 0xA662, 0x5729, 0xA666, 0x572A, 0xC9C9, 0x572C, 0xA664, 0x572D, 0xA663, 0x572E, 0xC9C8, 0x572F, 0xA665, 0x5730, 0xA661,
+ 0x5733, 0xA660, 0x5734, 0xC9CA, 0x573B, 0xA7A6, 0x573E, 0xA7A3, 0x5740, 0xA77D, 0x5741, 0xCAAA, 0x5745, 0xCAAB, 0x5747, 0xA7A1,
+ 0x5749, 0xCAAD, 0x574A, 0xA77B, 0x574B, 0xCAAE, 0x574C, 0xCAAC, 0x574D, 0xA77E, 0x574E, 0xA7A2, 0x574F, 0xA7A5, 0x5750, 0xA7A4,
+ 0x5751, 0xA77C, 0x5752, 0xCAAF, 0x5761, 0xA959, 0x5762, 0xCBFE, 0x5764, 0xA95B, 0x5766, 0xA95A, 0x5768, 0xCC40, 0x5769, 0xA958,
+ 0x576A, 0xA957, 0x576B, 0xCBF5, 0x576D, 0xCBF4, 0x576F, 0xCBF2, 0x5770, 0xCBF7, 0x5771, 0xCBF6, 0x5772, 0xCBF3, 0x5773, 0xCBFC,
+ 0x5774, 0xCBFD, 0x5775, 0xCBFA, 0x5776, 0xCBF8, 0x5777, 0xA956, 0x577B, 0xCBFB, 0x577C, 0xA95C, 0x577D, 0xCC41, 0x5780, 0xCBF9,
+ 0x5782, 0xABAB, 0x5783, 0xA955, 0x578B, 0xABAC, 0x578C, 0xCE54, 0x578F, 0xCE5A, 0x5793, 0xABB2, 0x5794, 0xCE58, 0x5795, 0xCE5E,
+ 0x5797, 0xCE55, 0x5798, 0xCE59, 0x5799, 0xCE5B, 0x579A, 0xCE5D, 0x579B, 0xCE57, 0x579D, 0xCE56, 0x579E, 0xCE51, 0x579F, 0xCE52,
+ 0x57A0, 0xABAD, 0x57A2, 0xABAF, 0x57A3, 0xABAE, 0x57A4, 0xCE53, 0x57A5, 0xCE5C, 0x57AE, 0xABB1, 0x57B5, 0xCE50, 0x57B6, 0xD153,
+ 0x57B8, 0xD152, 0x57B9, 0xD157, 0x57BA, 0xD14E, 0x57BC, 0xD151, 0x57BD, 0xD150, 0x57BF, 0xD154, 0x57C1, 0xD158, 0x57C2, 0xAE47,
+ 0x57C3, 0xAE4A, 0x57C6, 0xD14F, 0x57C7, 0xD155, 0x57CB, 0xAE49, 0x57CC, 0xD14A, 0x57CE, 0xABB0, 0x57CF, 0xD4BA, 0x57D0, 0xD156,
+ 0x57D2, 0xD14D, 0x57D4, 0xAE48, 0x57D5, 0xD14C, 0x57DC, 0xD4B1, 0x57DF, 0xB0EC, 0x57E0, 0xB0F0, 0x57E1, 0xD4C1, 0x57E2, 0xD4AF,
+ 0x57E3, 0xD4BD, 0x57E4, 0xB0F1, 0x57E5, 0xD4BF, 0x57E7, 0xD4C5, 0x57E9, 0xD4C9, 0x57EC, 0xD4C0, 0x57ED, 0xD4B4, 0x57EE, 0xD4BC,
+ 0x57F0, 0xD4CA, 0x57F1, 0xD4C8, 0x57F2, 0xD4BE, 0x57F3, 0xD4B9, 0x57F4, 0xD4B2, 0x57F5, 0xD8A6, 0x57F6, 0xD4B0, 0x57F7, 0xB0F5,
+ 0x57F8, 0xD4B7, 0x57F9, 0xB0F6, 0x57FA, 0xB0F2, 0x57FB, 0xD4AD, 0x57FC, 0xD4C3, 0x57FD, 0xD4B5, 0x5800, 0xD4B3, 0x5801, 0xD4C6,
+ 0x5802, 0xB0F3, 0x5804, 0xD4CC, 0x5805, 0xB0ED, 0x5806, 0xB0EF, 0x5807, 0xD4BB, 0x5808, 0xD4B6, 0x5809, 0xAE4B, 0x580A, 0xB0EE,
+ 0x580B, 0xD4B8, 0x580C, 0xD4C7, 0x580D, 0xD4CB, 0x580E, 0xD4C2, 0x5810, 0xD4C4, 0x5814, 0xD4AE, 0x5819, 0xD8A1, 0x581B, 0xD8AA,
+ 0x581C, 0xD8A9, 0x581D, 0xB3FA, 0x581E, 0xD8A2, 0x5820, 0xB3FB, 0x5821, 0xB3F9, 0x5823, 0xD8A4, 0x5824, 0xB3F6, 0x5825, 0xD8A8,
+ 0x5827, 0xD8A3, 0x5828, 0xD8A5, 0x5829, 0xD87D, 0x582A, 0xB3F4, 0x582C, 0xD8B2, 0x582D, 0xD8B1, 0x582E, 0xD8AE, 0x582F, 0xB3F3,
+ 0x5830, 0xB3F7, 0x5831, 0xB3F8, 0x5832, 0xD14B, 0x5833, 0xD8AB, 0x5834, 0xB3F5, 0x5835, 0xB0F4, 0x5836, 0xD8AD, 0x5837, 0xD87E,
+ 0x5838, 0xD8B0, 0x5839, 0xD8AF, 0x583B, 0xD8B3, 0x583D, 0xDCEF, 0x583F, 0xD8AC, 0x5848, 0xD8A7, 0x5849, 0xDCE7, 0x584A, 0xB6F4,
+ 0x584B, 0xB6F7, 0x584C, 0xB6F2, 0x584D, 0xDCE6, 0x584E, 0xDCEA, 0x584F, 0xDCE5, 0x5851, 0xB6EC, 0x5852, 0xB6F6, 0x5853, 0xDCE2,
+ 0x5854, 0xB6F0, 0x5855, 0xDCE9, 0x5857, 0xB6EE, 0x5858, 0xB6ED, 0x5859, 0xDCEC, 0x585A, 0xB6EF, 0x585B, 0xDCEE, 0x585D, 0xDCEB,
+ 0x585E, 0xB6EB, 0x5862, 0xB6F5, 0x5863, 0xDCF0, 0x5864, 0xDCE4, 0x5865, 0xDCED, 0x5868, 0xDCE3, 0x586B, 0xB6F1, 0x586D, 0xB6F3,
+ 0x586F, 0xDCE8, 0x5871, 0xDCF1, 0x5874, 0xE15D, 0x5875, 0xB9D0, 0x5876, 0xE163, 0x5879, 0xB9D5, 0x587A, 0xE15F, 0x587B, 0xE166,
+ 0x587C, 0xE157, 0x587D, 0xB9D7, 0x587E, 0xB9D1, 0x587F, 0xE15C, 0x5880, 0xBC55, 0x5881, 0xE15B, 0x5882, 0xE164, 0x5883, 0xB9D2,
+ 0x5885, 0xB9D6, 0x5886, 0xE15A, 0x5887, 0xE160, 0x5888, 0xE165, 0x5889, 0xE156, 0x588A, 0xB9D4, 0x588B, 0xE15E, 0x588E, 0xE162,
+ 0x588F, 0xE168, 0x5890, 0xE158, 0x5891, 0xE161, 0x5893, 0xB9D3, 0x5894, 0xE167, 0x5898, 0xE159, 0x589C, 0xBC59, 0x589D, 0xE54B,
+ 0x589E, 0xBC57, 0x589F, 0xBC56, 0x58A0, 0xE54D, 0x58A1, 0xE552, 0x58A3, 0xE54E, 0x58A5, 0xE551, 0x58A6, 0xBC5C, 0x58A8, 0xBEA5,
+ 0x58A9, 0xBC5B, 0x58AB, 0xE54A, 0x58AC, 0xE550, 0x58AE, 0xBC5A, 0x58AF, 0xE54F, 0x58B1, 0xE54C, 0x58B3, 0xBC58, 0x58BA, 0xE94D,
+ 0x58BB, 0xF9D9, 0x58BC, 0xE94F, 0x58BD, 0xE94A, 0x58BE, 0xBEC1, 0x58BF, 0xE94C, 0x58C1, 0xBEC0, 0x58C2, 0xE94E, 0x58C5, 0xBEC3,
+ 0x58C6, 0xE950, 0x58C7, 0xBEC2, 0x58C8, 0xE949, 0x58C9, 0xE94B, 0x58CE, 0xC0A5, 0x58CF, 0xECCC, 0x58D1, 0xC0A4, 0x58D2, 0xECCD,
+ 0x58D3, 0xC0A3, 0x58D4, 0xECCB, 0x58D5, 0xC0A2, 0x58D6, 0xECCA, 0x58D8, 0xC253, 0x58D9, 0xC252, 0x58DA, 0xF1F6, 0x58DB, 0xF1F8,
+ 0x58DD, 0xF1F7, 0x58DE, 0xC361, 0x58DF, 0xC362, 0x58E2, 0xC363, 0x58E3, 0xF442, 0x58E4, 0xC45B, 0x58E7, 0xF7D3, 0x58E8, 0xF7D2,
+ 0x58E9, 0xC5F2, 0x58EB, 0xA468, 0x58EC, 0xA4D0, 0x58EF, 0xA7A7, 0x58F4, 0xCE5F, 0x58F9, 0xB3FC, 0x58FA, 0xB3FD, 0x58FC, 0xDCF2,
+ 0x58FD, 0xB9D8, 0x58FE, 0xE169, 0x58FF, 0xE553, 0x5903, 0xC95A, 0x5906, 0xCAB0, 0x590C, 0xCC42, 0x590D, 0xCE60, 0x590E, 0xD159,
+ 0x590F, 0xAE4C, 0x5912, 0xF1F9, 0x5914, 0xC4DC, 0x5915, 0xA469, 0x5916, 0xA57E, 0x5917, 0xC970, 0x5919, 0xA667, 0x591A, 0xA668,
+ 0x591C, 0xA95D, 0x5920, 0xB0F7, 0x5922, 0xB9DA, 0x5924, 0xB9DB, 0x5925, 0xB9D9, 0x5927, 0xA46A, 0x5929, 0xA4D1, 0x592A, 0xA4D3,
+ 0x592B, 0xA4D2, 0x592C, 0xC95B, 0x592D, 0xA4D4, 0x592E, 0xA5A1, 0x592F, 0xC971, 0x5931, 0xA5A2, 0x5937, 0xA669, 0x5938, 0xA66A,
+ 0x593C, 0xC9CB, 0x593E, 0xA7A8, 0x5940, 0xCAB1, 0x5944, 0xA961, 0x5945, 0xCC43, 0x5947, 0xA95F, 0x5948, 0xA960, 0x5949, 0xA95E,
+ 0x594A, 0xD15A, 0x594E, 0xABB6, 0x594F, 0xABB5, 0x5950, 0xABB7, 0x5951, 0xABB4, 0x5953, 0xCE61, 0x5954, 0xA962, 0x5955, 0xABB3,
+ 0x5957, 0xAE4D, 0x5958, 0xAE4E, 0x595A, 0xAE4F, 0x595C, 0xD4CD, 0x5960, 0xB3FE, 0x5961, 0xD8B4, 0x5962, 0xB0F8, 0x5967, 0xB6F8,
+ 0x5969, 0xB9DD, 0x596A, 0xB9DC, 0x596B, 0xE16A, 0x596D, 0xBC5D, 0x596E, 0xBEC4, 0x5970, 0xEFC0, 0x5971, 0xF6DA, 0x5972, 0xF7D4,
+ 0x5973, 0xA46B, 0x5974, 0xA5A3, 0x5976, 0xA5A4, 0x5977, 0xC9D1, 0x5978, 0xA66C, 0x5979, 0xA66F, 0x597B, 0xC9CF, 0x597C, 0xC9CD,
+ 0x597D, 0xA66E, 0x597E, 0xC9D0, 0x597F, 0xC9D2, 0x5980, 0xC9CC, 0x5981, 0xA671, 0x5982, 0xA670, 0x5983, 0xA66D, 0x5984, 0xA66B,
+ 0x5985, 0xC9CE, 0x598A, 0xA7B3, 0x598D, 0xA7B0, 0x598E, 0xCAB6, 0x598F, 0xCAB9, 0x5990, 0xCAB8, 0x5992, 0xA7AA, 0x5993, 0xA7B2,
+ 0x5996, 0xA7AF, 0x5997, 0xCAB5, 0x5998, 0xCAB3, 0x5999, 0xA7AE, 0x599D, 0xA7A9, 0x599E, 0xA7AC, 0x59A0, 0xCAB4, 0x59A1, 0xCABB,
+ 0x59A2, 0xCAB7, 0x59A3, 0xA7AD, 0x59A4, 0xA7B1, 0x59A5, 0xA7B4, 0x59A6, 0xCAB2, 0x59A7, 0xCABA, 0x59A8, 0xA7AB, 0x59AE, 0xA967,
+ 0x59AF, 0xA96F, 0x59B1, 0xCC4F, 0x59B2, 0xCC48, 0x59B3, 0xA970, 0x59B4, 0xCC53, 0x59B5, 0xCC44, 0x59B6, 0xCC4B, 0x59B9, 0xA966,
+ 0x59BA, 0xCC45, 0x59BB, 0xA964, 0x59BC, 0xCC4C, 0x59BD, 0xCC50, 0x59BE, 0xA963, 0x59C0, 0xCC51, 0x59C1, 0xCC4A, 0x59C3, 0xCC4D,
+ 0x59C5, 0xA972, 0x59C6, 0xA969, 0x59C7, 0xCC54, 0x59C8, 0xCC52, 0x59CA, 0xA96E, 0x59CB, 0xA96C, 0x59CC, 0xCC49, 0x59CD, 0xA96B,
+ 0x59CE, 0xCC47, 0x59CF, 0xCC46, 0x59D0, 0xA96A, 0x59D1, 0xA968, 0x59D2, 0xA971, 0x59D3, 0xA96D, 0x59D4, 0xA965, 0x59D6, 0xCC4E,
+ 0x59D8, 0xABB9, 0x59DA, 0xABC0, 0x59DB, 0xCE6F, 0x59DC, 0xABB8, 0x59DD, 0xCE67, 0x59DE, 0xCE63, 0x59E0, 0xCE73, 0x59E1, 0xCE62,
+ 0x59E3, 0xABBB, 0x59E4, 0xCE6C, 0x59E5, 0xABBE, 0x59E6, 0xABC1, 0x59E8, 0xABBC, 0x59E9, 0xCE70, 0x59EA, 0xABBF, 0x59EC, 0xAE56,
+ 0x59ED, 0xCE76, 0x59EE, 0xCE64, 0x59F1, 0xCE66, 0x59F2, 0xCE6D, 0x59F3, 0xCE71, 0x59F4, 0xCE75, 0x59F5, 0xCE72, 0x59F6, 0xCE6B,
+ 0x59F7, 0xCE6E, 0x59FA, 0xCE68, 0x59FB, 0xABC3, 0x59FC, 0xCE6A, 0x59FD, 0xCE69, 0x59FE, 0xCE74, 0x59FF, 0xABBA, 0x5A00, 0xCE65,
+ 0x5A01, 0xABC2, 0x5A03, 0xABBD, 0x5A09, 0xAE5C, 0x5A0A, 0xD162, 0x5A0C, 0xAE5B, 0x5A0F, 0xD160, 0x5A11, 0xAE50, 0x5A13, 0xAE55,
+ 0x5A15, 0xD15F, 0x5A16, 0xD15C, 0x5A17, 0xD161, 0x5A18, 0xAE51, 0x5A19, 0xD15B, 0x5A1B, 0xAE54, 0x5A1C, 0xAE52, 0x5A1E, 0xD163,
+ 0x5A1F, 0xAE53, 0x5A20, 0xAE57, 0x5A23, 0xAE58, 0x5A25, 0xAE5A, 0x5A29, 0xAE59, 0x5A2D, 0xD15D, 0x5A2E, 0xD15E, 0x5A33, 0xD164,
+ 0x5A35, 0xD4D4, 0x5A36, 0xB0F9, 0x5A37, 0xD8C2, 0x5A38, 0xD4D3, 0x5A39, 0xD4E6, 0x5A3C, 0xB140, 0x5A3E, 0xD4E4, 0x5A40, 0xB0FE,
+ 0x5A41, 0xB0FA, 0x5A42, 0xD4ED, 0x5A43, 0xD4DD, 0x5A44, 0xD4E0, 0x5A46, 0xB143, 0x5A47, 0xD4EA, 0x5A48, 0xD4E2, 0x5A49, 0xB0FB,
+ 0x5A4A, 0xB144, 0x5A4C, 0xD4E7, 0x5A4D, 0xD4E5, 0x5A50, 0xD4D6, 0x5A51, 0xD4EB, 0x5A52, 0xD4DF, 0x5A53, 0xD4DA, 0x5A55, 0xD4D0,
+ 0x5A56, 0xD4EC, 0x5A57, 0xD4DC, 0x5A58, 0xD4CF, 0x5A5A, 0xB142, 0x5A5B, 0xD4E1, 0x5A5C, 0xD4EE, 0x5A5D, 0xD4DE, 0x5A5E, 0xD4D2,
+ 0x5A5F, 0xD4D7, 0x5A60, 0xD4CE, 0x5A62, 0xB141, 0x5A64, 0xD4DB, 0x5A65, 0xD4D8, 0x5A66, 0xB0FC, 0x5A67, 0xD4D1, 0x5A69, 0xD4E9,
+ 0x5A6A, 0xB0FD, 0x5A6C, 0xD4D9, 0x5A6D, 0xD4D5, 0x5A70, 0xD4E8, 0x5A77, 0xB440, 0x5A78, 0xD8BB, 0x5A7A, 0xD8B8, 0x5A7B, 0xD8C9,
+ 0x5A7C, 0xD8BD, 0x5A7D, 0xD8CA, 0x5A7F, 0xB442, 0x5A83, 0xD8C6, 0x5A84, 0xD8C3, 0x5A8A, 0xD8C4, 0x5A8B, 0xD8C7, 0x5A8C, 0xD8CB,
+ 0x5A8E, 0xD4E3, 0x5A8F, 0xD8CD, 0x5A90, 0xDD47, 0x5A92, 0xB443, 0x5A93, 0xD8CE, 0x5A94, 0xD8B6, 0x5A95, 0xD8C0, 0x5A97, 0xD8C5,
+ 0x5A9A, 0xB441, 0x5A9B, 0xB444, 0x5A9C, 0xD8CC, 0x5A9D, 0xD8CF, 0x5A9E, 0xD8BA, 0x5A9F, 0xD8B7, 0x5AA2, 0xD8B9, 0x5AA5, 0xD8BE,
+ 0x5AA6, 0xD8BC, 0x5AA7, 0xB445, 0x5AA9, 0xD8C8, 0x5AAC, 0xD8BF, 0x5AAE, 0xD8C1, 0x5AAF, 0xD8B5, 0x5AB0, 0xDCFA, 0x5AB1, 0xDCF8,
+ 0x5AB2, 0xB742, 0x5AB3, 0xB740, 0x5AB4, 0xDD43, 0x5AB5, 0xDCF9, 0x5AB6, 0xDD44, 0x5AB7, 0xDD40, 0x5AB8, 0xDCF7, 0x5AB9, 0xDD46,
+ 0x5ABA, 0xDCF6, 0x5ABB, 0xDCFD, 0x5ABC, 0xB6FE, 0x5ABD, 0xB6FD, 0x5ABE, 0xB6FC, 0x5ABF, 0xDCFB, 0x5AC0, 0xDD41, 0x5AC1, 0xB6F9,
+ 0x5AC2, 0xB741, 0x5AC4, 0xDCF4, 0x5AC6, 0xDCFE, 0x5AC7, 0xDCF3, 0x5AC8, 0xDCFC, 0x5AC9, 0xB6FA, 0x5ACA, 0xDD42, 0x5ACB, 0xDCF5,
+ 0x5ACC, 0xB6FB, 0x5ACD, 0xDD45, 0x5AD5, 0xE16E, 0x5AD6, 0xB9E2, 0x5AD7, 0xB9E1, 0x5AD8, 0xB9E3, 0x5AD9, 0xE17A, 0x5ADA, 0xE170,
+ 0x5ADB, 0xE176, 0x5ADC, 0xE16B, 0x5ADD, 0xE179, 0x5ADE, 0xE178, 0x5ADF, 0xE17C, 0x5AE0, 0xE175, 0x5AE1, 0xB9DE, 0x5AE2, 0xE174,
+ 0x5AE3, 0xB9E4, 0x5AE5, 0xE16D, 0x5AE6, 0xB9DF, 0x5AE8, 0xE17B, 0x5AE9, 0xB9E0, 0x5AEA, 0xE16F, 0x5AEB, 0xE172, 0x5AEC, 0xE177,
+ 0x5AED, 0xE171, 0x5AEE, 0xE16C, 0x5AF3, 0xE173, 0x5AF4, 0xE555, 0x5AF5, 0xBC61, 0x5AF6, 0xE558, 0x5AF7, 0xE557, 0x5AF8, 0xE55A,
+ 0x5AF9, 0xE55C, 0x5AFA, 0xF9DC, 0x5AFB, 0xBC5F, 0x5AFD, 0xE556, 0x5AFF, 0xE554, 0x5B01, 0xE55D, 0x5B02, 0xE55B, 0x5B03, 0xE559,
+ 0x5B05, 0xE55F, 0x5B07, 0xE55E, 0x5B08, 0xBC63, 0x5B09, 0xBC5E, 0x5B0B, 0xBC60, 0x5B0C, 0xBC62, 0x5B0F, 0xE560, 0x5B10, 0xE957,
+ 0x5B13, 0xE956, 0x5B14, 0xE955, 0x5B16, 0xE958, 0x5B17, 0xE951, 0x5B19, 0xE952, 0x5B1A, 0xE95A, 0x5B1B, 0xE953, 0x5B1D, 0xBEC5,
+ 0x5B1E, 0xE95C, 0x5B20, 0xE95B, 0x5B21, 0xE954, 0x5B23, 0xECD1, 0x5B24, 0xC0A8, 0x5B25, 0xECCF, 0x5B26, 0xECD4, 0x5B27, 0xECD3,
+ 0x5B28, 0xE959, 0x5B2A, 0xC0A7, 0x5B2C, 0xECD2, 0x5B2D, 0xECCE, 0x5B2E, 0xECD6, 0x5B2F, 0xECD5, 0x5B30, 0xC0A6, 0x5B32, 0xECD0,
+ 0x5B34, 0xBEC6, 0x5B38, 0xC254, 0x5B3C, 0xEFC1, 0x5B3D, 0xF1FA, 0x5B3E, 0xF1FB, 0x5B3F, 0xF1FC, 0x5B40, 0xC45C, 0x5B43, 0xC45D,
+ 0x5B45, 0xF443, 0x5B47, 0xF5C8, 0x5B48, 0xF5C7, 0x5B4B, 0xF6DB, 0x5B4C, 0xF6DC, 0x5B4D, 0xF7D5, 0x5B4E, 0xF8A7, 0x5B50, 0xA46C,
+ 0x5B51, 0xA46D, 0x5B53, 0xA46E, 0x5B54, 0xA4D5, 0x5B55, 0xA5A5, 0x5B56, 0xC9D3, 0x5B57, 0xA672, 0x5B58, 0xA673, 0x5B5A, 0xA7B7,
+ 0x5B5B, 0xA7B8, 0x5B5C, 0xA7B6, 0x5B5D, 0xA7B5, 0x5B5F, 0xA973, 0x5B62, 0xCC55, 0x5B63, 0xA975, 0x5B64, 0xA974, 0x5B65, 0xCC56,
+ 0x5B69, 0xABC4, 0x5B6B, 0xAE5D, 0x5B6C, 0xD165, 0x5B6E, 0xD4F0, 0x5B70, 0xB145, 0x5B71, 0xB447, 0x5B72, 0xD4EF, 0x5B73, 0xB446,
+ 0x5B75, 0xB9E5, 0x5B77, 0xE17D, 0x5B78, 0xBEC7, 0x5B7A, 0xC0A9, 0x5B7B, 0xECD7, 0x5B7D, 0xC45E, 0x5B7F, 0xC570, 0x5B81, 0xC972,
+ 0x5B83, 0xA5A6, 0x5B84, 0xC973, 0x5B85, 0xA676, 0x5B87, 0xA674, 0x5B88, 0xA675, 0x5B89, 0xA677, 0x5B8B, 0xA7BA, 0x5B8C, 0xA7B9,
+ 0x5B8E, 0xCABC, 0x5B8F, 0xA7BB, 0x5B92, 0xCABD, 0x5B93, 0xCC57, 0x5B95, 0xCC58, 0x5B97, 0xA976, 0x5B98, 0xA978, 0x5B99, 0xA97A,
+ 0x5B9A, 0xA977, 0x5B9B, 0xA97B, 0x5B9C, 0xA979, 0x5BA2, 0xABC8, 0x5BA3, 0xABC5, 0x5BA4, 0xABC7, 0x5BA5, 0xABC9, 0x5BA6, 0xABC6,
+ 0x5BA7, 0xD166, 0x5BA8, 0xCE77, 0x5BAC, 0xD168, 0x5BAD, 0xD167, 0x5BAE, 0xAE63, 0x5BB0, 0xAE5F, 0x5BB3, 0xAE60, 0x5BB4, 0xAE62,
+ 0x5BB5, 0xAE64, 0x5BB6, 0xAE61, 0x5BB8, 0xAE66, 0x5BB9, 0xAE65, 0x5BBF, 0xB14A, 0x5BC0, 0xD4F2, 0x5BC1, 0xD4F1, 0x5BC2, 0xB149,
+ 0x5BC4, 0xB148, 0x5BC5, 0xB147, 0x5BC6, 0xB14B, 0x5BC7, 0xB146, 0x5BCA, 0xD8D5, 0x5BCB, 0xD8D2, 0x5BCC, 0xB449, 0x5BCD, 0xD8D1,
+ 0x5BCE, 0xD8D6, 0x5BD0, 0xB44B, 0x5BD1, 0xD8D4, 0x5BD2, 0xB448, 0x5BD3, 0xB44A, 0x5BD4, 0xD8D3, 0x5BD6, 0xDD48, 0x5BD8, 0xDD49,
+ 0x5BD9, 0xDD4A, 0x5BDE, 0xB9E6, 0x5BDF, 0xB9EE, 0x5BE0, 0xE17E, 0x5BE1, 0xB9E8, 0x5BE2, 0xB9EC, 0x5BE3, 0xE1A1, 0x5BE4, 0xB9ED,
+ 0x5BE5, 0xB9E9, 0x5BE6, 0xB9EA, 0x5BE7, 0xB9E7, 0x5BE8, 0xB9EB, 0x5BE9, 0xBC66, 0x5BEA, 0xD8D0, 0x5BEB, 0xBC67, 0x5BEC, 0xBC65,
+ 0x5BEE, 0xBC64, 0x5BEF, 0xE95D, 0x5BF0, 0xBEC8, 0x5BF1, 0xECD8, 0x5BF2, 0xECD9, 0x5BF5, 0xC364, 0x5BF6, 0xC45F, 0x5BF8, 0xA46F,
+ 0x5BFA, 0xA678, 0x5C01, 0xABCA, 0x5C03, 0xD169, 0x5C04, 0xAE67, 0x5C07, 0xB14E, 0x5C08, 0xB14D, 0x5C09, 0xB14C, 0x5C0A, 0xB44C,
+ 0x5C0B, 0xB44D, 0x5C0C, 0xD8D7, 0x5C0D, 0xB9EF, 0x5C0E, 0xBEC9, 0x5C0F, 0xA470, 0x5C10, 0xC95C, 0x5C11, 0xA4D6, 0x5C12, 0xC974,
+ 0x5C15, 0xC9D4, 0x5C16, 0xA679, 0x5C1A, 0xA97C, 0x5C1F, 0xDD4B, 0x5C22, 0xA471, 0x5C24, 0xA4D7, 0x5C25, 0xC9D5, 0x5C28, 0xCABE,
+ 0x5C2A, 0xCABF, 0x5C2C, 0xA7BC, 0x5C30, 0xD8D8, 0x5C31, 0xB44E, 0x5C33, 0xDD4C, 0x5C37, 0xC0AA, 0x5C38, 0xA472, 0x5C39, 0xA4A8,
+ 0x5C3A, 0xA4D8, 0x5C3B, 0xC975, 0x5C3C, 0xA5A7, 0x5C3E, 0xA7C0, 0x5C3F, 0xA7BF, 0x5C40, 0xA7BD, 0x5C41, 0xA7BE, 0x5C44, 0xCC59,
+ 0x5C45, 0xA97E, 0x5C46, 0xA9A1, 0x5C47, 0xCC5A, 0x5C48, 0xA97D, 0x5C4B, 0xABCE, 0x5C4C, 0xCE78, 0x5C4D, 0xABCD, 0x5C4E, 0xABCB,
+ 0x5C4F, 0xABCC, 0x5C50, 0xAE6A, 0x5C51, 0xAE68, 0x5C54, 0xD16B, 0x5C55, 0xAE69, 0x5C56, 0xD16A, 0x5C58, 0xAE5E, 0x5C59, 0xD4F3,
+ 0x5C5C, 0xB150, 0x5C5D, 0xB151, 0x5C60, 0xB14F, 0x5C62, 0xB9F0, 0x5C63, 0xE1A2, 0x5C64, 0xBC68, 0x5C65, 0xBC69, 0x5C67, 0xE561,
+ 0x5C68, 0xC0AB, 0x5C69, 0xEFC2, 0x5C6A, 0xEFC3, 0x5C6C, 0xC4DD, 0x5C6D, 0xF8A8, 0x5C6E, 0xC94B, 0x5C6F, 0xA4D9, 0x5C71, 0xA473,
+ 0x5C73, 0xC977, 0x5C74, 0xC976, 0x5C79, 0xA67A, 0x5C7A, 0xC9D7, 0x5C7B, 0xC9D8, 0x5C7C, 0xC9D6, 0x5C7E, 0xC9D9, 0x5C86, 0xCAC7,
+ 0x5C88, 0xCAC2, 0x5C89, 0xCAC4, 0x5C8A, 0xCAC6, 0x5C8B, 0xCAC3, 0x5C8C, 0xA7C4, 0x5C8D, 0xCAC0, 0x5C8F, 0xCAC1, 0x5C90, 0xA7C1,
+ 0x5C91, 0xA7C2, 0x5C92, 0xCAC5, 0x5C93, 0xCAC8, 0x5C94, 0xA7C3, 0x5C95, 0xCAC9, 0x5C9D, 0xCC68, 0x5C9F, 0xCC62, 0x5CA0, 0xCC5D,
+ 0x5CA1, 0xA9A3, 0x5CA2, 0xCC65, 0x5CA3, 0xCC63, 0x5CA4, 0xCC5C, 0x5CA5, 0xCC69, 0x5CA6, 0xCC6C, 0x5CA7, 0xCC67, 0x5CA8, 0xCC60,
+ 0x5CA9, 0xA9A5, 0x5CAA, 0xCC66, 0x5CAB, 0xA9A6, 0x5CAC, 0xCC61, 0x5CAD, 0xCC64, 0x5CAE, 0xCC5B, 0x5CAF, 0xCC5F, 0x5CB0, 0xCC6B,
+ 0x5CB1, 0xA9A7, 0x5CB3, 0xA9A8, 0x5CB5, 0xCC5E, 0x5CB6, 0xCC6A, 0x5CB7, 0xA9A2, 0x5CB8, 0xA9A4, 0x5CC6, 0xCEAB, 0x5CC7, 0xCEA4,
+ 0x5CC8, 0xCEAA, 0x5CC9, 0xCEA3, 0x5CCA, 0xCEA5, 0x5CCB, 0xCE7D, 0x5CCC, 0xCE7B, 0x5CCE, 0xCEAC, 0x5CCF, 0xCEA9, 0x5CD0, 0xCE79,
+ 0x5CD2, 0xABD0, 0x5CD3, 0xCEA7, 0x5CD4, 0xCEA8, 0x5CD6, 0xCEA6, 0x5CD7, 0xCE7C, 0x5CD8, 0xCE7A, 0x5CD9, 0xABCF, 0x5CDA, 0xCEA2,
+ 0x5CDB, 0xCE7E, 0x5CDE, 0xCEA1, 0x5CDF, 0xCEAD, 0x5CE8, 0xAE6F, 0x5CEA, 0xAE6E, 0x5CEC, 0xD16C, 0x5CED, 0xAE6B, 0x5CEE, 0xD16E,
+ 0x5CF0, 0xAE70, 0x5CF1, 0xD16F, 0x5CF4, 0xAE73, 0x5CF6, 0xAE71, 0x5CF7, 0xD170, 0x5CF8, 0xCEAE, 0x5CF9, 0xD172, 0x5CFB, 0xAE6D,
+ 0x5CFD, 0xAE6C, 0x5CFF, 0xD16D, 0x5D00, 0xD171, 0x5D01, 0xAE72, 0x5D06, 0xB153, 0x5D07, 0xB152, 0x5D0B, 0xD4F5, 0x5D0C, 0xD4F9,
+ 0x5D0D, 0xD4FB, 0x5D0E, 0xB154, 0x5D0F, 0xD4FE, 0x5D11, 0xB158, 0x5D12, 0xD541, 0x5D14, 0xB15A, 0x5D16, 0xB156, 0x5D17, 0xB15E,
+ 0x5D19, 0xB15B, 0x5D1A, 0xD4F7, 0x5D1B, 0xB155, 0x5D1D, 0xD4F6, 0x5D1E, 0xD4F4, 0x5D1F, 0xD543, 0x5D20, 0xD4F8, 0x5D22, 0xB157,
+ 0x5D23, 0xD542, 0x5D24, 0xB15C, 0x5D25, 0xD4FD, 0x5D26, 0xD4FC, 0x5D27, 0xB15D, 0x5D28, 0xD4FA, 0x5D29, 0xB159, 0x5D2E, 0xD544,
+ 0x5D30, 0xD540, 0x5D31, 0xD8E7, 0x5D32, 0xD8EE, 0x5D33, 0xD8E3, 0x5D34, 0xB451, 0x5D35, 0xD8DF, 0x5D36, 0xD8EF, 0x5D37, 0xD8D9,
+ 0x5D38, 0xD8EC, 0x5D39, 0xD8EA, 0x5D3A, 0xD8E4, 0x5D3C, 0xD8ED, 0x5D3D, 0xD8E6, 0x5D3F, 0xD8DE, 0x5D40, 0xD8F0, 0x5D41, 0xD8DC,
+ 0x5D42, 0xD8E9, 0x5D43, 0xD8DA, 0x5D45, 0xD8F1, 0x5D47, 0xB452, 0x5D49, 0xD8EB, 0x5D4A, 0xDD4F, 0x5D4B, 0xD8DD, 0x5D4C, 0xB44F,
+ 0x5D4E, 0xD8E1, 0x5D50, 0xB450, 0x5D51, 0xD8E0, 0x5D52, 0xD8E5, 0x5D55, 0xD8E2, 0x5D59, 0xD8E8, 0x5D5E, 0xDD53, 0x5D62, 0xDD56,
+ 0x5D63, 0xDD4E, 0x5D65, 0xDD50, 0x5D67, 0xDD55, 0x5D68, 0xDD54, 0x5D69, 0xB743, 0x5D6B, 0xD8DB, 0x5D6C, 0xDD52, 0x5D6F, 0xB744,
+ 0x5D71, 0xDD4D, 0x5D72, 0xDD51, 0x5D77, 0xE1A9, 0x5D79, 0xE1B0, 0x5D7A, 0xE1A7, 0x5D7C, 0xE1AE, 0x5D7D, 0xE1A5, 0x5D7E, 0xE1AD,
+ 0x5D7F, 0xE1B1, 0x5D80, 0xE1A4, 0x5D81, 0xE1A8, 0x5D82, 0xE1A3, 0x5D84, 0xB9F1, 0x5D86, 0xE1A6, 0x5D87, 0xB9F2, 0x5D88, 0xE1AC,
+ 0x5D89, 0xE1AB, 0x5D8A, 0xE1AA, 0x5D8D, 0xE1AF, 0x5D92, 0xE565, 0x5D93, 0xE567, 0x5D94, 0xBC6B, 0x5D95, 0xE568, 0x5D97, 0xE563,
+ 0x5D99, 0xE562, 0x5D9A, 0xE56C, 0x5D9C, 0xE56A, 0x5D9D, 0xBC6A, 0x5D9E, 0xE56D, 0x5D9F, 0xE564, 0x5DA0, 0xE569, 0x5DA1, 0xE56B,
+ 0x5DA2, 0xE566, 0x5DA7, 0xE961, 0x5DA8, 0xE966, 0x5DA9, 0xE960, 0x5DAA, 0xE965, 0x5DAC, 0xE95E, 0x5DAD, 0xE968, 0x5DAE, 0xE964,
+ 0x5DAF, 0xE969, 0x5DB0, 0xE963, 0x5DB1, 0xE95F, 0x5DB2, 0xE967, 0x5DB4, 0xE96A, 0x5DB5, 0xE962, 0x5DB7, 0xECDA, 0x5DB8, 0xC0AF,
+ 0x5DBA, 0xC0AD, 0x5DBC, 0xC0AC, 0x5DBD, 0xC0AE, 0x5DC0, 0xEFC4, 0x5DC2, 0xF172, 0x5DC3, 0xF1FD, 0x5DC6, 0xF444, 0x5DC7, 0xF445,
+ 0x5DC9, 0xC460, 0x5DCB, 0xF5C9, 0x5DCD, 0xC4DE, 0x5DCF, 0xF5CA, 0x5DD1, 0xF6DE, 0x5DD2, 0xC572, 0x5DD4, 0xC571, 0x5DD5, 0xF6DD,
+ 0x5DD6, 0xC5C9, 0x5DD8, 0xF7D6, 0x5DDD, 0xA474, 0x5DDE, 0xA67B, 0x5DDF, 0xC9DA, 0x5DE0, 0xCACA, 0x5DE1, 0xA8B5, 0x5DE2, 0xB15F,
+ 0x5DE5, 0xA475, 0x5DE6, 0xA5AA, 0x5DE7, 0xA5A9, 0x5DE8, 0xA5A8, 0x5DEB, 0xA7C5, 0x5DEE, 0xAE74, 0x5DF0, 0xDD57, 0x5DF1, 0xA476,
+ 0x5DF2, 0xA477, 0x5DF3, 0xA478, 0x5DF4, 0xA4DA, 0x5DF7, 0xABD1, 0x5DF9, 0xCEAF, 0x5DFD, 0xB453, 0x5DFE, 0xA479, 0x5DFF, 0xC95D,
+ 0x5E02, 0xA5AB, 0x5E03, 0xA5AC, 0x5E04, 0xC978, 0x5E06, 0xA67C, 0x5E0A, 0xCACB, 0x5E0C, 0xA7C6, 0x5E0E, 0xCACC, 0x5E11, 0xA9AE,
+ 0x5E14, 0xCC6E, 0x5E15, 0xA9AC, 0x5E16, 0xA9AB, 0x5E17, 0xCC6D, 0x5E18, 0xA9A9, 0x5E19, 0xCC6F, 0x5E1A, 0xA9AA, 0x5E1B, 0xA9AD,
+ 0x5E1D, 0xABD2, 0x5E1F, 0xABD4, 0x5E20, 0xCEB3, 0x5E21, 0xCEB0, 0x5E22, 0xCEB1, 0x5E23, 0xCEB2, 0x5E24, 0xCEB4, 0x5E25, 0xABD3,
+ 0x5E28, 0xD174, 0x5E29, 0xD173, 0x5E2B, 0xAE76, 0x5E2D, 0xAE75, 0x5E33, 0xB162, 0x5E34, 0xD546, 0x5E36, 0xB161, 0x5E37, 0xB163,
+ 0x5E38, 0xB160, 0x5E3D, 0xB455, 0x5E3E, 0xD545, 0x5E40, 0xB456, 0x5E41, 0xD8F3, 0x5E43, 0xB457, 0x5E44, 0xD8F2, 0x5E45, 0xB454,
+ 0x5E4A, 0xDD5A, 0x5E4B, 0xDD5C, 0x5E4C, 0xB745, 0x5E4D, 0xDD5B, 0x5E4E, 0xDD59, 0x5E4F, 0xDD58, 0x5E53, 0xE1B4, 0x5E54, 0xB9F7,
+ 0x5E55, 0xB9F5, 0x5E57, 0xB9F6, 0x5E58, 0xE1B2, 0x5E59, 0xE1B3, 0x5E5B, 0xB9F3, 0x5E5C, 0xE571, 0x5E5D, 0xE56F, 0x5E5F, 0xBC6D,
+ 0x5E60, 0xE570, 0x5E61, 0xBC6E, 0x5E62, 0xBC6C, 0x5E63, 0xB9F4, 0x5E66, 0xE96D, 0x5E67, 0xE96B, 0x5E68, 0xE96C, 0x5E69, 0xE56E,
+ 0x5E6A, 0xECDC, 0x5E6B, 0xC0B0, 0x5E6C, 0xECDB, 0x5E6D, 0xEFC5, 0x5E6E, 0xEFC6, 0x5E6F, 0xE96E, 0x5E70, 0xF1FE, 0x5E72, 0xA47A,
+ 0x5E73, 0xA5AD, 0x5E74, 0xA67E, 0x5E75, 0xC9DB, 0x5E76, 0xA67D, 0x5E78, 0xA9AF, 0x5E79, 0xB746, 0x5E7B, 0xA4DB, 0x5E7C, 0xA5AE,
+ 0x5E7D, 0xABD5, 0x5E7E, 0xB458, 0x5E80, 0xC979, 0x5E82, 0xC97A, 0x5E84, 0xC9DC, 0x5E87, 0xA7C8, 0x5E88, 0xCAD0, 0x5E89, 0xCACE,
+ 0x5E8A, 0xA7C9, 0x5E8B, 0xCACD, 0x5E8C, 0xCACF, 0x5E8D, 0xCAD1, 0x5E8F, 0xA7C7, 0x5E95, 0xA9B3, 0x5E96, 0xA9B4, 0x5E97, 0xA9B1,
+ 0x5E9A, 0xA9B0, 0x5E9B, 0xCEB8, 0x5E9C, 0xA9B2, 0x5EA0, 0xABD6, 0x5EA2, 0xCEB7, 0x5EA3, 0xCEB9, 0x5EA4, 0xCEB6, 0x5EA5, 0xCEBA,
+ 0x5EA6, 0xABD7, 0x5EA7, 0xAE79, 0x5EA8, 0xD175, 0x5EAA, 0xD177, 0x5EAB, 0xAE77, 0x5EAC, 0xD178, 0x5EAD, 0xAE78, 0x5EAE, 0xD176,
+ 0x5EB0, 0xCEB5, 0x5EB1, 0xD547, 0x5EB2, 0xD54A, 0x5EB3, 0xD54B, 0x5EB4, 0xD548, 0x5EB5, 0xB167, 0x5EB6, 0xB166, 0x5EB7, 0xB164,
+ 0x5EB8, 0xB165, 0x5EB9, 0xD549, 0x5EBE, 0xB168, 0x5EC1, 0xB45A, 0x5EC2, 0xB45B, 0x5EC4, 0xB45C, 0x5EC5, 0xDD5D, 0x5EC6, 0xDD5F,
+ 0x5EC7, 0xDD61, 0x5EC8, 0xB748, 0x5EC9, 0xB747, 0x5ECA, 0xB459, 0x5ECB, 0xDD60, 0x5ECC, 0xDD5E, 0x5ECE, 0xE1B8, 0x5ED1, 0xE1B6,
+ 0x5ED2, 0xE1BC, 0x5ED3, 0xB9F8, 0x5ED4, 0xE1BD, 0x5ED5, 0xE1BA, 0x5ED6, 0xB9F9, 0x5ED7, 0xE1B7, 0x5ED8, 0xE1B5, 0x5ED9, 0xE1BB,
+ 0x5EDA, 0xBC70, 0x5EDB, 0xE573, 0x5EDC, 0xE1B9, 0x5EDD, 0xBC72, 0x5EDE, 0xE574, 0x5EDF, 0xBC71, 0x5EE0, 0xBC74, 0x5EE1, 0xE575,
+ 0x5EE2, 0xBC6F, 0x5EE3, 0xBC73, 0x5EE5, 0xE973, 0x5EE6, 0xE971, 0x5EE7, 0xE970, 0x5EE8, 0xE972, 0x5EE9, 0xE96F, 0x5EEC, 0xC366,
+ 0x5EEE, 0xF446, 0x5EEF, 0xF447, 0x5EF1, 0xF5CB, 0x5EF2, 0xF6DF, 0x5EF3, 0xC655, 0x5EF6, 0xA9B5, 0x5EF7, 0xA7CA, 0x5EFA, 0xABD8,
+ 0x5EFE, 0xA47B, 0x5EFF, 0xA4DC, 0x5F01, 0xA5AF, 0x5F02, 0xC9DD, 0x5F04, 0xA7CB, 0x5F05, 0xCAD2, 0x5F07, 0xCEBB, 0x5F08, 0xABD9,
+ 0x5F0A, 0xB9FA, 0x5F0B, 0xA47C, 0x5F0F, 0xA6A1, 0x5F12, 0xB749, 0x5F13, 0xA47D, 0x5F14, 0xA4DD, 0x5F15, 0xA4DE, 0x5F17, 0xA5B1,
+ 0x5F18, 0xA5B0, 0x5F1A, 0xC9DE, 0x5F1B, 0xA6A2, 0x5F1D, 0xCAD3, 0x5F1F, 0xA7CC, 0x5F22, 0xCC71, 0x5F23, 0xCC72, 0x5F24, 0xCC73,
+ 0x5F26, 0xA9B6, 0x5F27, 0xA9B7, 0x5F28, 0xCC70, 0x5F29, 0xA9B8, 0x5F2D, 0xABDA, 0x5F2E, 0xCEBC, 0x5F30, 0xD17A, 0x5F31, 0xAE7A,
+ 0x5F33, 0xD179, 0x5F35, 0xB169, 0x5F36, 0xD54C, 0x5F37, 0xB16A, 0x5F38, 0xD54D, 0x5F3C, 0xB45D, 0x5F40, 0xDD62, 0x5F43, 0xE1BF,
+ 0x5F44, 0xE1BE, 0x5F46, 0xB9FB, 0x5F48, 0xBC75, 0x5F49, 0xE576, 0x5F4A, 0xBECA, 0x5F4B, 0xE974, 0x5F4C, 0xC0B1, 0x5F4E, 0xC573,
+ 0x5F4F, 0xF7D8, 0x5F54, 0xCC74, 0x5F56, 0xCEBD, 0x5F57, 0xB16B, 0x5F58, 0xD8F4, 0x5F59, 0xB74A, 0x5F5D, 0xC255, 0x5F62, 0xA7CE,
+ 0x5F64, 0xA7CD, 0x5F65, 0xABDB, 0x5F67, 0xD17B, 0x5F69, 0xB16D, 0x5F6A, 0xB343, 0x5F6B, 0xB16E, 0x5F6C, 0xB16C, 0x5F6D, 0xB45E,
+ 0x5F6F, 0xE1C0, 0x5F70, 0xB9FC, 0x5F71, 0xBC76, 0x5F73, 0xC94C, 0x5F74, 0xC9DF, 0x5F76, 0xCAD5, 0x5F77, 0xA7CF, 0x5F78, 0xCAD4,
+ 0x5F79, 0xA7D0, 0x5F7C, 0xA9BC, 0x5F7D, 0xCC77, 0x5F7E, 0xCC76, 0x5F7F, 0xA9BB, 0x5F80, 0xA9B9, 0x5F81, 0xA9BA, 0x5F82, 0xCC75,
+ 0x5F85, 0xABDD, 0x5F86, 0xCEBE, 0x5F87, 0xABE0, 0x5F88, 0xABDC, 0x5F89, 0xABE2, 0x5F8A, 0xABDE, 0x5F8B, 0xABDF, 0x5F8C, 0xABE1,
+ 0x5F90, 0xAE7D, 0x5F91, 0xAE7C, 0x5F92, 0xAE7B, 0x5F96, 0xD54F, 0x5F97, 0xB16F, 0x5F98, 0xB172, 0x5F99, 0xB170, 0x5F9B, 0xD54E,
+ 0x5F9C, 0xB175, 0x5F9E, 0xB171, 0x5F9F, 0xD550, 0x5FA0, 0xB174, 0x5FA1, 0xB173, 0x5FA5, 0xD8F6, 0x5FA6, 0xD8F5, 0x5FA8, 0xB461,
+ 0x5FA9, 0xB45F, 0x5FAA, 0xB460, 0x5FAB, 0xD8F7, 0x5FAC, 0xB74B, 0x5FAD, 0xDD64, 0x5FAE, 0xB74C, 0x5FAF, 0xDD63, 0x5FB2, 0xE577,
+ 0x5FB5, 0xBC78, 0x5FB6, 0xE1C1, 0x5FB7, 0xBC77, 0x5FB9, 0xB9FD, 0x5FBB, 0xECDE, 0x5FBC, 0xE975, 0x5FBD, 0xC0B2, 0x5FBE, 0xECDD,
+ 0x5FBF, 0xF240, 0x5FC0, 0xF448, 0x5FC1, 0xF449, 0x5FC3, 0xA4DF, 0x5FC5, 0xA5B2, 0x5FC9, 0xC97B, 0x5FCC, 0xA7D2, 0x5FCD, 0xA7D4,
+ 0x5FCF, 0xC9E2, 0x5FD0, 0xCAD8, 0x5FD1, 0xCAD7, 0x5FD2, 0xCAD6, 0x5FD4, 0xC9E1, 0x5FD5, 0xC9E0, 0x5FD6, 0xA6A4, 0x5FD7, 0xA7D3,
+ 0x5FD8, 0xA7D1, 0x5FD9, 0xA6A3, 0x5FDD, 0xA9BD, 0x5FDE, 0xCC78, 0x5FE0, 0xA9BE, 0x5FE1, 0xCADD, 0x5FE3, 0xCADF, 0x5FE4, 0xCADE,
+ 0x5FE5, 0xCC79, 0x5FE8, 0xCADA, 0x5FEA, 0xA7D8, 0x5FEB, 0xA7D6, 0x5FED, 0xCAD9, 0x5FEE, 0xCADB, 0x5FEF, 0xCAE1, 0x5FF1, 0xA7D5,
+ 0x5FF3, 0xCADC, 0x5FF4, 0xCAE5, 0x5FF5, 0xA9C0, 0x5FF7, 0xCAE2, 0x5FF8, 0xA7D7, 0x5FFA, 0xCAE0, 0x5FFB, 0xCAE3, 0x5FFD, 0xA9BF,
+ 0x5FFF, 0xA9C1, 0x6000, 0xCAE4, 0x6009, 0xCCAF, 0x600A, 0xCCA2, 0x600B, 0xCC7E, 0x600C, 0xCCAE, 0x600D, 0xCCA9, 0x600E, 0xABE7,
+ 0x600F, 0xA9C2, 0x6010, 0xCCAA, 0x6011, 0xCCAD, 0x6012, 0xABE3, 0x6013, 0xCCAC, 0x6014, 0xA9C3, 0x6015, 0xA9C8, 0x6016, 0xA9C6,
+ 0x6017, 0xCCA3, 0x6019, 0xCC7C, 0x601A, 0xCCA5, 0x601B, 0xA9CD, 0x601C, 0xCCB0, 0x601D, 0xABE4, 0x601E, 0xCCA6, 0x6020, 0xABE5,
+ 0x6021, 0xA9C9, 0x6022, 0xCCA8, 0x6024, 0xCECD, 0x6025, 0xABE6, 0x6026, 0xCC7B, 0x6027, 0xA9CA, 0x6028, 0xABE8, 0x6029, 0xA9CB,
+ 0x602A, 0xA9C7, 0x602B, 0xA9CC, 0x602C, 0xCCA7, 0x602D, 0xCC7A, 0x602E, 0xCCAB, 0x602F, 0xA9C4, 0x6032, 0xCC7D, 0x6033, 0xCCA4,
+ 0x6034, 0xCCA1, 0x6035, 0xA9C5, 0x6037, 0xCEBF, 0x6039, 0xCEC0, 0x6040, 0xCECA, 0x6041, 0xD1A1, 0x6042, 0xCECB, 0x6043, 0xABEE,
+ 0x6044, 0xCECE, 0x6045, 0xCEC4, 0x6046, 0xABED, 0x6047, 0xCEC6, 0x6049, 0xCEC7, 0x604C, 0xCEC9, 0x604D, 0xABE9, 0x6050, 0xAEA3,
+ 0x6052, 0xF9DA, 0x6053, 0xCEC5, 0x6054, 0xCEC1, 0x6055, 0xAEA4, 0x6058, 0xCECF, 0x6059, 0xAE7E, 0x605A, 0xD17D, 0x605B, 0xCEC8,
+ 0x605D, 0xD17C, 0x605E, 0xCEC3, 0x605F, 0xCECC, 0x6062, 0xABEC, 0x6063, 0xAEA1, 0x6064, 0xABF2, 0x6065, 0xAEA2, 0x6066, 0xCED0,
+ 0x6067, 0xD17E, 0x6068, 0xABEB, 0x6069, 0xAEA6, 0x606A, 0xABF1, 0x606B, 0xABF0, 0x606C, 0xABEF, 0x606D, 0xAEA5, 0x606E, 0xCED1,
+ 0x606F, 0xAEA7, 0x6070, 0xABEA, 0x6072, 0xCEC2, 0x607F, 0xB176, 0x6080, 0xD1A4, 0x6081, 0xD1A6, 0x6083, 0xD1A8, 0x6084, 0xAEA8,
+ 0x6085, 0xAEAE, 0x6086, 0xD553, 0x6087, 0xD1AC, 0x6088, 0xD1A3, 0x6089, 0xB178, 0x608A, 0xD551, 0x608C, 0xAEAD, 0x608D, 0xAEAB,
+ 0x608E, 0xD1AE, 0x6090, 0xD552, 0x6092, 0xD1A5, 0x6094, 0xAEAC, 0x6095, 0xD1A9, 0x6096, 0xAEAF, 0x6097, 0xD1AB, 0x609A, 0xAEAA,
+ 0x609B, 0xD1AA, 0x609C, 0xD1AD, 0x609D, 0xD1A7, 0x609F, 0xAEA9, 0x60A0, 0xB179, 0x60A2, 0xD1A2, 0x60A3, 0xB177, 0x60A8, 0xB17A,
+ 0x60B0, 0xD555, 0x60B1, 0xD55E, 0x60B2, 0xB464, 0x60B4, 0xB17C, 0x60B5, 0xB1A3, 0x60B6, 0xB465, 0x60B7, 0xD560, 0x60B8, 0xB1AA,
+ 0x60B9, 0xD8F9, 0x60BA, 0xD556, 0x60BB, 0xB1A2, 0x60BC, 0xB1A5, 0x60BD, 0xB17E, 0x60BE, 0xD554, 0x60BF, 0xD562, 0x60C0, 0xD565,
+ 0x60C1, 0xD949, 0x60C3, 0xD563, 0x60C4, 0xD8FD, 0x60C5, 0xB1A1, 0x60C6, 0xB1A8, 0x60C7, 0xB1AC, 0x60C8, 0xD55D, 0x60C9, 0xD8F8,
+ 0x60CA, 0xD561, 0x60CB, 0xB17B, 0x60CC, 0xD8FA, 0x60CD, 0xD564, 0x60CE, 0xD8FC, 0x60CF, 0xD559, 0x60D1, 0xB462, 0x60D3, 0xD557,
+ 0x60D4, 0xD558, 0x60D5, 0xB1A7, 0x60D8, 0xB1A6, 0x60D9, 0xD55B, 0x60DA, 0xB1AB, 0x60DB, 0xD55F, 0x60DC, 0xB1A4, 0x60DD, 0xD55C,
+ 0x60DF, 0xB1A9, 0x60E0, 0xB466, 0x60E1, 0xB463, 0x60E2, 0xD8FB, 0x60E4, 0xD55A, 0x60E6, 0xB17D, 0x60F0, 0xB46B, 0x60F1, 0xB46F,
+ 0x60F2, 0xD940, 0x60F3, 0xB751, 0x60F4, 0xB46D, 0x60F5, 0xD944, 0x60F6, 0xB471, 0x60F7, 0xDD65, 0x60F8, 0xD946, 0x60F9, 0xB753,
+ 0x60FA, 0xB469, 0x60FB, 0xB46C, 0x60FC, 0xD947, 0x60FE, 0xD948, 0x60FF, 0xD94E, 0x6100, 0xB473, 0x6101, 0xB754, 0x6103, 0xD94A,
+ 0x6104, 0xD94F, 0x6105, 0xD943, 0x6106, 0xB75E, 0x6108, 0xB755, 0x6109, 0xB472, 0x610A, 0xD941, 0x610B, 0xD950, 0x610D, 0xB75D,
+ 0x610E, 0xB470, 0x610F, 0xB74E, 0x6110, 0xD94D, 0x6112, 0xB474, 0x6113, 0xD945, 0x6114, 0xD8FE, 0x6115, 0xB46A, 0x6116, 0xD942,
+ 0x6118, 0xD94B, 0x611A, 0xB74D, 0x611B, 0xB752, 0x611C, 0xB467, 0x611D, 0xD94C, 0x611F, 0xB750, 0x6123, 0xB468, 0x6127, 0xB75C,
+ 0x6128, 0xE1C3, 0x6129, 0xDD70, 0x612B, 0xDD68, 0x612C, 0xE1C2, 0x612E, 0xDD6C, 0x612F, 0xDD6E, 0x6132, 0xDD6B, 0x6134, 0xB75B,
+ 0x6136, 0xDD6A, 0x6137, 0xB75F, 0x613B, 0xE1D2, 0x613E, 0xB75A, 0x613F, 0xBA40, 0x6140, 0xDD71, 0x6141, 0xE1C4, 0x6144, 0xB758,
+ 0x6145, 0xDD69, 0x6146, 0xDD6D, 0x6147, 0xB9FE, 0x6148, 0xB74F, 0x6149, 0xDD66, 0x614A, 0xDD67, 0x614B, 0xBA41, 0x614C, 0xB757,
+ 0x614D, 0xB759, 0x614E, 0xB756, 0x614F, 0xDD6F, 0x6152, 0xE1C8, 0x6153, 0xE1C9, 0x6154, 0xE1CE, 0x6155, 0xBC7D, 0x6156, 0xE1D5,
+ 0x6158, 0xBA47, 0x615A, 0xBA46, 0x615B, 0xE1D0, 0x615D, 0xBC7C, 0x615E, 0xE1C5, 0x615F, 0xBA45, 0x6161, 0xE1D4, 0x6162, 0xBA43,
+ 0x6163, 0xBA44, 0x6165, 0xE1D1, 0x6166, 0xE5AA, 0x6167, 0xBC7A, 0x6168, 0xB46E, 0x616A, 0xE1D3, 0x616B, 0xBCA3, 0x616C, 0xE1CB,
+ 0x616E, 0xBC7B, 0x6170, 0xBCA2, 0x6171, 0xE1C6, 0x6172, 0xE1CA, 0x6173, 0xE1C7, 0x6174, 0xE1CD, 0x6175, 0xBA48, 0x6176, 0xBC79,
+ 0x6177, 0xBA42, 0x6179, 0xE57A, 0x617A, 0xE1CF, 0x617C, 0xBCA1, 0x617E, 0xBCA4, 0x6180, 0xE1CC, 0x6182, 0xBC7E, 0x6183, 0xE579,
+ 0x6189, 0xE57E, 0x618A, 0xBECE, 0x618B, 0xE578, 0x618C, 0xE9A3, 0x618D, 0xE5A9, 0x618E, 0xBCA8, 0x6190, 0xBCA6, 0x6191, 0xBECC,
+ 0x6192, 0xE5A6, 0x6193, 0xE5A2, 0x6194, 0xBCAC, 0x6196, 0xE978, 0x619A, 0xBCAA, 0x619B, 0xE5A1, 0x619D, 0xE976, 0x619F, 0xE5A5,
+ 0x61A1, 0xE5A8, 0x61A2, 0xE57D, 0x61A4, 0xBCAB, 0x61A7, 0xBCA5, 0x61A8, 0xE977, 0x61A9, 0xBECD, 0x61AA, 0xE5A7, 0x61AB, 0xBCA7,
+ 0x61AC, 0xBCA9, 0x61AD, 0xE5A4, 0x61AE, 0xBCAD, 0x61AF, 0xE5A3, 0x61B0, 0xE57C, 0x61B1, 0xE57B, 0x61B2, 0xBECB, 0x61B3, 0xE5AB,
+ 0x61B4, 0xE97A, 0x61B5, 0xECE0, 0x61B6, 0xBED0, 0x61B8, 0xE9A2, 0x61BA, 0xE97E, 0x61BC, 0xECE1, 0x61BE, 0xBED1, 0x61BF, 0xE9A1,
+ 0x61C1, 0xE97C, 0x61C2, 0xC0B4, 0x61C3, 0xECDF, 0x61C5, 0xE979, 0x61C6, 0xE97B, 0x61C7, 0xC0B5, 0x61C8, 0xBED3, 0x61C9, 0xC0B3,
+ 0x61CA, 0xBED2, 0x61CB, 0xC0B7, 0x61CC, 0xE97D, 0x61CD, 0xBECF, 0x61D6, 0xEFCF, 0x61D8, 0xEFC7, 0x61DE, 0xECE7, 0x61DF, 0xEFC8,
+ 0x61E0, 0xECE3, 0x61E3, 0xC256, 0x61E4, 0xECE5, 0x61E5, 0xECE4, 0x61E6, 0xC0B6, 0x61E7, 0xECE2, 0x61E8, 0xECE6, 0x61E9, 0xEFD0,
+ 0x61EA, 0xEFCC, 0x61EB, 0xEFCE, 0x61ED, 0xEFC9, 0x61EE, 0xEFCA, 0x61F0, 0xEFCD, 0x61F1, 0xEFCB, 0x61F2, 0xC367, 0x61F5, 0xC36A,
+ 0x61F6, 0xC369, 0x61F7, 0xC368, 0x61F8, 0xC461, 0x61F9, 0xF44A, 0x61FA, 0xC462, 0x61FB, 0xF241, 0x61FC, 0xC4DF, 0x61FD, 0xF5CC,
+ 0x61FE, 0xC4E0, 0x61FF, 0xC574, 0x6200, 0xC5CA, 0x6201, 0xF7D9, 0x6203, 0xF7DA, 0x6204, 0xF7DB, 0x6207, 0xF9BA, 0x6208, 0xA4E0,
+ 0x6209, 0xC97C, 0x620A, 0xA5B3, 0x620C, 0xA6A6, 0x620D, 0xA6A7, 0x620E, 0xA6A5, 0x6210, 0xA6A8, 0x6211, 0xA7DA, 0x6212, 0xA7D9,
+ 0x6214, 0xCCB1, 0x6215, 0xA9CF, 0x6216, 0xA9CE, 0x6219, 0xD1AF, 0x621A, 0xB1AD, 0x621B, 0xB1AE, 0x621F, 0xB475, 0x6220, 0xDD72,
+ 0x6221, 0xB760, 0x6222, 0xB761, 0x6223, 0xDD74, 0x6224, 0xDD76, 0x6225, 0xDD75, 0x6227, 0xE1D7, 0x6229, 0xE1D6, 0x622A, 0xBA49,
+ 0x622B, 0xE1D8, 0x622D, 0xE5AC, 0x622E, 0xBCAE, 0x6230, 0xBED4, 0x6232, 0xC0B8, 0x6233, 0xC257, 0x6234, 0xC0B9, 0x6236, 0xA4E1,
+ 0x623A, 0xCAE6, 0x623D, 0xCCB2, 0x623E, 0xA9D1, 0x623F, 0xA9D0, 0x6240, 0xA9D2, 0x6241, 0xABF3, 0x6242, 0xCED2, 0x6243, 0xCED3,
+ 0x6246, 0xD1B0, 0x6247, 0xAEB0, 0x6248, 0xB1AF, 0x6249, 0xB476, 0x624A, 0xD951, 0x624B, 0xA4E2, 0x624D, 0xA47E, 0x624E, 0xA4E3,
+ 0x6250, 0xC97D, 0x6251, 0xA5B7, 0x6252, 0xA5B6, 0x6253, 0xA5B4, 0x6254, 0xA5B5, 0x6258, 0xA6AB, 0x6259, 0xC9E9, 0x625A, 0xC9EB,
+ 0x625B, 0xA6AA, 0x625C, 0xC9E3, 0x625E, 0xC9E4, 0x6260, 0xC9EA, 0x6261, 0xC9E6, 0x6262, 0xC9E8, 0x6263, 0xA6A9, 0x6264, 0xC9E5,
+ 0x6265, 0xC9EC, 0x6266, 0xC9E7, 0x626D, 0xA7E1, 0x626E, 0xA7EA, 0x626F, 0xA7E8, 0x6270, 0xCAF0, 0x6271, 0xCAED, 0x6272, 0xCAF5,
+ 0x6273, 0xA7E6, 0x6274, 0xCAF6, 0x6276, 0xA7DF, 0x6277, 0xCAF3, 0x6279, 0xA7E5, 0x627A, 0xCAEF, 0x627B, 0xCAEE, 0x627C, 0xA7E3,
+ 0x627D, 0xCAF4, 0x627E, 0xA7E4, 0x627F, 0xA9D3, 0x6280, 0xA7DE, 0x6281, 0xCAF1, 0x6283, 0xCAE7, 0x6284, 0xA7DB, 0x6286, 0xA7EE,
+ 0x6287, 0xCAEC, 0x6288, 0xCAF2, 0x6289, 0xA7E0, 0x628A, 0xA7E2, 0x628C, 0xCAE8, 0x628E, 0xCAE9, 0x628F, 0xCAEA, 0x6291, 0xA7ED,
+ 0x6292, 0xA7E7, 0x6293, 0xA7EC, 0x6294, 0xCAEB, 0x6295, 0xA7EB, 0x6296, 0xA7DD, 0x6297, 0xA7DC, 0x6298, 0xA7E9, 0x62A8, 0xA9E1,
+ 0x62A9, 0xCCBE, 0x62AA, 0xCCB7, 0x62AB, 0xA9DC, 0x62AC, 0xA9EF, 0x62AD, 0xCCB3, 0x62AE, 0xCCBA, 0x62AF, 0xCCBC, 0x62B0, 0xCCBF,
+ 0x62B1, 0xA9EA, 0x62B3, 0xCCBB, 0x62B4, 0xCCB4, 0x62B5, 0xA9E8, 0x62B6, 0xCCB8, 0x62B8, 0xCCC0, 0x62B9, 0xA9D9, 0x62BB, 0xCCBD,
+ 0x62BC, 0xA9E3, 0x62BD, 0xA9E2, 0x62BE, 0xCCB6, 0x62BF, 0xA9D7, 0x62C2, 0xA9D8, 0x62C4, 0xA9D6, 0x62C6, 0xA9EE, 0x62C7, 0xA9E6,
+ 0x62C8, 0xA9E0, 0x62C9, 0xA9D4, 0x62CA, 0xCCB9, 0x62CB, 0xA9DF, 0x62CC, 0xA9D5, 0x62CD, 0xA9E7, 0x62CE, 0xA9F0, 0x62CF, 0xCED4,
+ 0x62D0, 0xA9E4, 0x62D1, 0xCCB5, 0x62D2, 0xA9DA, 0x62D3, 0xA9DD, 0x62D4, 0xA9DE, 0x62D6, 0xA9EC, 0x62D7, 0xA9ED, 0x62D8, 0xA9EB,
+ 0x62D9, 0xA9E5, 0x62DA, 0xA9E9, 0x62DB, 0xA9DB, 0x62DC, 0xABF4, 0x62EB, 0xCEDA, 0x62EC, 0xAC41, 0x62ED, 0xABF8, 0x62EE, 0xABFA,
+ 0x62EF, 0xAC40, 0x62F0, 0xCEE6, 0x62F1, 0xABFD, 0x62F2, 0xD1B1, 0x62F3, 0xAEB1, 0x62F4, 0xAC43, 0x62F5, 0xCED7, 0x62F6, 0xCEDF,
+ 0x62F7, 0xABFE, 0x62F8, 0xCEDE, 0x62F9, 0xCEDB, 0x62FA, 0xCEE3, 0x62FB, 0xCEE5, 0x62FC, 0xABF7, 0x62FD, 0xABFB, 0x62FE, 0xAC42,
+ 0x62FF, 0xAEB3, 0x6300, 0xCEE0, 0x6301, 0xABF9, 0x6302, 0xAC45, 0x6303, 0xCED9, 0x6307, 0xABFC, 0x6308, 0xAEB2, 0x6309, 0xABF6,
+ 0x630B, 0xCED6, 0x630C, 0xCEDD, 0x630D, 0xCED5, 0x630E, 0xCED8, 0x630F, 0xCEDC, 0x6310, 0xD1B2, 0x6311, 0xAC44, 0x6313, 0xCEE1,
+ 0x6314, 0xCEE2, 0x6315, 0xCEE4, 0x6316, 0xABF5, 0x6328, 0xAEC1, 0x6329, 0xD1BE, 0x632A, 0xAEBF, 0x632B, 0xAEC0, 0x632C, 0xD1B4,
+ 0x632D, 0xD1C4, 0x632F, 0xAEB6, 0x6332, 0xD566, 0x6333, 0xD1C6, 0x6334, 0xD1C0, 0x6336, 0xD1B7, 0x6338, 0xD1C9, 0x6339, 0xD1BA,
+ 0x633A, 0xAEBC, 0x633B, 0xD57D, 0x633C, 0xD1BD, 0x633D, 0xAEBE, 0x633E, 0xAEB5, 0x6340, 0xD1CB, 0x6341, 0xD1BF, 0x6342, 0xAEB8,
+ 0x6343, 0xD1B8, 0x6344, 0xD1B5, 0x6345, 0xD1B6, 0x6346, 0xAEB9, 0x6347, 0xD1C5, 0x6348, 0xD1CC, 0x6349, 0xAEBB, 0x634A, 0xD1BC,
+ 0x634B, 0xD1BB, 0x634C, 0xAEC3, 0x634D, 0xAEC2, 0x634E, 0xAEB4, 0x634F, 0xAEBA, 0x6350, 0xAEBD, 0x6351, 0xD1C8, 0x6354, 0xD1C2,
+ 0x6355, 0xAEB7, 0x6356, 0xD1B3, 0x6357, 0xD1CA, 0x6358, 0xD1C1, 0x6359, 0xD1C3, 0x635A, 0xD1C7, 0x6365, 0xD567, 0x6367, 0xB1B7,
+ 0x6368, 0xB1CB, 0x6369, 0xB1CA, 0x636B, 0xB1BF, 0x636D, 0xD579, 0x636E, 0xD575, 0x636F, 0xD572, 0x6370, 0xD5A6, 0x6371, 0xB1BA,
+ 0x6372, 0xB1B2, 0x6375, 0xD577, 0x6376, 0xB4A8, 0x6377, 0xB1B6, 0x6378, 0xD5A1, 0x637A, 0xB1CC, 0x637B, 0xB1C9, 0x637C, 0xD57B,
+ 0x637D, 0xD56A, 0x6380, 0xB1C8, 0x6381, 0xD5A3, 0x6382, 0xD569, 0x6383, 0xB1BD, 0x6384, 0xB1C1, 0x6385, 0xD5A2, 0x6387, 0xD573,
+ 0x6388, 0xB1C2, 0x6389, 0xB1BC, 0x638A, 0xD568, 0x638C, 0xB478, 0x638D, 0xD5A5, 0x638E, 0xD571, 0x638F, 0xB1C7, 0x6390, 0xD574,
+ 0x6391, 0xD5A4, 0x6392, 0xB1C6, 0x6394, 0xD952, 0x6396, 0xB1B3, 0x6397, 0xD56F, 0x6398, 0xB1B8, 0x6399, 0xB1C3, 0x639B, 0xB1BE,
+ 0x639C, 0xD578, 0x639D, 0xD56E, 0x639E, 0xD56C, 0x639F, 0xD57E, 0x63A0, 0xB1B0, 0x63A1, 0xB1C4, 0x63A2, 0xB1B4, 0x63A3, 0xB477,
+ 0x63A4, 0xD57C, 0x63A5, 0xB1B5, 0x63A7, 0xB1B1, 0x63A8, 0xB1C0, 0x63A9, 0xB1BB, 0x63AA, 0xB1B9, 0x63AB, 0xD570, 0x63AC, 0xB1C5,
+ 0x63AD, 0xD56D, 0x63AE, 0xD57A, 0x63AF, 0xD576, 0x63B0, 0xD954, 0x63B1, 0xD953, 0x63BD, 0xD56B, 0x63BE, 0xD964, 0x63C0, 0xB47A,
+ 0x63C2, 0xD96A, 0x63C3, 0xD959, 0x63C4, 0xD967, 0x63C5, 0xDD77, 0x63C6, 0xB47D, 0x63C7, 0xD96B, 0x63C8, 0xD96E, 0x63C9, 0xB47C,
+ 0x63CA, 0xD95C, 0x63CB, 0xD96D, 0x63CC, 0xD96C, 0x63CD, 0xB47E, 0x63CE, 0xD955, 0x63CF, 0xB479, 0x63D0, 0xB4A3, 0x63D2, 0xB4A1,
+ 0x63D3, 0xD969, 0x63D5, 0xD95F, 0x63D6, 0xB4A5, 0x63D7, 0xD970, 0x63D8, 0xD968, 0x63D9, 0xD971, 0x63DA, 0xB4AD, 0x63DB, 0xB4AB,
+ 0x63DC, 0xD966, 0x63DD, 0xD965, 0x63DF, 0xD963, 0x63E0, 0xD95D, 0x63E1, 0xB4A4, 0x63E3, 0xB4A2, 0x63E4, 0xD1B9, 0x63E5, 0xD956,
+ 0x63E7, 0xDDB7, 0x63E8, 0xD957, 0x63E9, 0xB47B, 0x63EA, 0xB4AA, 0x63EB, 0xDD79, 0x63ED, 0xB4A6, 0x63EE, 0xB4A7, 0x63EF, 0xD958,
+ 0x63F0, 0xD96F, 0x63F1, 0xDD78, 0x63F2, 0xD960, 0x63F3, 0xD95B, 0x63F4, 0xB4A9, 0x63F5, 0xD961, 0x63F6, 0xD95E, 0x63F9, 0xB4AE,
+ 0x6406, 0xB770, 0x6409, 0xDD7C, 0x640A, 0xDDB1, 0x640B, 0xDDB6, 0x640C, 0xDDAA, 0x640D, 0xB76C, 0x640E, 0xDDBB, 0x640F, 0xB769,
+ 0x6410, 0xDD7A, 0x6412, 0xDD7B, 0x6413, 0xB762, 0x6414, 0xB76B, 0x6415, 0xDDA4, 0x6416, 0xB76E, 0x6417, 0xB76F, 0x6418, 0xDDA5,
+ 0x641A, 0xDDB2, 0x641B, 0xDDB8, 0x641C, 0xB76A, 0x641E, 0xB764, 0x641F, 0xDDA3, 0x6420, 0xDD7D, 0x6421, 0xDDBA, 0x6422, 0xDDA8,
+ 0x6423, 0xDDA9, 0x6424, 0xDD7E, 0x6425, 0xDDB4, 0x6426, 0xDDAB, 0x6427, 0xDDB5, 0x6428, 0xDDAD, 0x642A, 0xB765, 0x642B, 0xE1D9,
+ 0x642C, 0xB768, 0x642D, 0xB766, 0x642E, 0xDDB9, 0x642F, 0xDDB0, 0x6430, 0xDDAC, 0x6433, 0xDDA1, 0x6434, 0xBA53, 0x6435, 0xDDAF,
+ 0x6436, 0xB76D, 0x6437, 0xDDA7, 0x6439, 0xDDA6, 0x643D, 0xB767, 0x643E, 0xB763, 0x643F, 0xE1EE, 0x6440, 0xDDB3, 0x6441, 0xDDAE,
+ 0x6443, 0xDDA2, 0x644B, 0xE1E9, 0x644D, 0xE1DA, 0x644E, 0xE1E5, 0x6450, 0xE1EC, 0x6451, 0xBA51, 0x6452, 0xB4AC, 0x6453, 0xE1EA,
+ 0x6454, 0xBA4C, 0x6458, 0xBA4B, 0x6459, 0xE1F1, 0x645B, 0xE1DB, 0x645C, 0xE1E8, 0x645D, 0xE1DC, 0x645E, 0xE1E7, 0x645F, 0xBA4F,
+ 0x6460, 0xE1EB, 0x6461, 0xD962, 0x6465, 0xE1F2, 0x6466, 0xE1E3, 0x6467, 0xBA52, 0x6468, 0xE5BA, 0x6469, 0xBCAF, 0x646B, 0xE1F0,
+ 0x646C, 0xE1EF, 0x646D, 0xBA54, 0x646E, 0xE5AD, 0x646F, 0xBCB0, 0x6470, 0xE5AE, 0x6472, 0xE1DF, 0x6473, 0xE1E0, 0x6474, 0xE1DD,
+ 0x6475, 0xE1E2, 0x6476, 0xE1DE, 0x6477, 0xE1F3, 0x6478, 0xBA4E, 0x6479, 0xBCB1, 0x647A, 0xBA50, 0x647B, 0xBA55, 0x647D, 0xE1E1,
+ 0x647F, 0xE1ED, 0x6482, 0xE1E6, 0x6485, 0xE5B1, 0x6487, 0xBA4A, 0x6488, 0xBCB4, 0x6489, 0xE9AA, 0x648A, 0xE5B6, 0x648B, 0xE5B5,
+ 0x648C, 0xE5B7, 0x648F, 0xE5B4, 0x6490, 0xBCB5, 0x6492, 0xBCBB, 0x6493, 0xBCB8, 0x6495, 0xBCB9, 0x6496, 0xE5AF, 0x6497, 0xE5B2,
+ 0x6498, 0xE5BC, 0x6499, 0xBCC1, 0x649A, 0xBCBF, 0x649C, 0xE5B3, 0x649D, 0xD95A, 0x649E, 0xBCB2, 0x649F, 0xE5B9, 0x64A0, 0xE5B0,
+ 0x64A2, 0xBCC2, 0x64A3, 0xE5B8, 0x64A4, 0xBA4D, 0x64A5, 0xBCB7, 0x64A6, 0xE1E4, 0x64A9, 0xBCBA, 0x64AB, 0xBCBE, 0x64AC, 0xBCC0,
+ 0x64AD, 0xBCBD, 0x64AE, 0xBCBC, 0x64B0, 0xBCB6, 0x64B1, 0xE5BB, 0x64B2, 0xBCB3, 0x64B3, 0xBCC3, 0x64BB, 0xBED8, 0x64BC, 0xBED9,
+ 0x64BD, 0xE9A9, 0x64BE, 0xBEE2, 0x64BF, 0xBEDF, 0x64C1, 0xBED6, 0x64C2, 0xBEDD, 0x64C3, 0xE9AB, 0x64C4, 0xBEDB, 0x64C5, 0xBED5,
+ 0x64C7, 0xBEDC, 0x64C9, 0xE9A8, 0x64CA, 0xC0BB, 0x64CB, 0xBED7, 0x64CD, 0xBEDE, 0x64CE, 0xC0BA, 0x64CF, 0xE9A7, 0x64D0, 0xE9A6,
+ 0x64D2, 0xBEE0, 0x64D4, 0xBEE1, 0x64D6, 0xE9A5, 0x64D7, 0xE9A4, 0x64D8, 0xC0BC, 0x64D9, 0xE9AE, 0x64DA, 0xBEDA, 0x64DB, 0xE9AC,
+ 0x64E0, 0xC0BD, 0x64E2, 0xC0C2, 0x64E3, 0xECEA, 0x64E4, 0xECEC, 0x64E6, 0xC0BF, 0x64E8, 0xECED, 0x64E9, 0xECE9, 0x64EB, 0xECEB,
+ 0x64EC, 0xC0C0, 0x64ED, 0xC0C3, 0x64EF, 0xECE8, 0x64F0, 0xC0BE, 0x64F1, 0xC0C1, 0x64F2, 0xC259, 0x64F3, 0xE9AD, 0x64F4, 0xC258,
+ 0x64F7, 0xC25E, 0x64F8, 0xEFD4, 0x64FA, 0xC25C, 0x64FB, 0xC25D, 0x64FC, 0xEFD7, 0x64FD, 0xEFD3, 0x64FE, 0xC25A, 0x64FF, 0xEFD1,
+ 0x6500, 0xC36B, 0x6501, 0xEFD5, 0x6503, 0xEFD6, 0x6504, 0xEFD2, 0x6506, 0xC25B, 0x6507, 0xF242, 0x6509, 0xF245, 0x650C, 0xF246,
+ 0x650D, 0xF244, 0x650E, 0xF247, 0x650F, 0xC36C, 0x6510, 0xF243, 0x6513, 0xF44E, 0x6514, 0xC464, 0x6515, 0xF44D, 0x6516, 0xF44C,
+ 0x6517, 0xF44B, 0x6518, 0xC463, 0x6519, 0xC465, 0x651B, 0xF5CD, 0x651C, 0xC4E2, 0x651D, 0xC4E1, 0x6520, 0xF6E1, 0x6521, 0xF6E0,
+ 0x6522, 0xF6E3, 0x6523, 0xC5CB, 0x6524, 0xC575, 0x6525, 0xF7DD, 0x6526, 0xF6E2, 0x6529, 0xF7DC, 0x652A, 0xC5CD, 0x652B, 0xC5CC,
+ 0x652C, 0xC5F3, 0x652D, 0xF8A9, 0x652E, 0xF8EF, 0x652F, 0xA4E4, 0x6532, 0xD972, 0x6533, 0xE9AF, 0x6536, 0xA6AC, 0x6537, 0xCAF7,
+ 0x6538, 0xA7F1, 0x6539, 0xA7EF, 0x653B, 0xA7F0, 0x653D, 0xCCC1, 0x653E, 0xA9F1, 0x653F, 0xAC46, 0x6541, 0xCEE7, 0x6543, 0xCEE8,
+ 0x6545, 0xAC47, 0x6546, 0xD1CE, 0x6548, 0xAEC4, 0x6549, 0xAEC5, 0x654A, 0xD1CD, 0x654F, 0xB1D3, 0x6551, 0xB1CF, 0x6553, 0xD5A7,
+ 0x6554, 0xB1D6, 0x6555, 0xB1D5, 0x6556, 0xB1CE, 0x6557, 0xB1D1, 0x6558, 0xB1D4, 0x6559, 0xB1D0, 0x655C, 0xD976, 0x655D, 0xB1CD,
+ 0x655E, 0xB4AF, 0x6562, 0xB4B1, 0x6563, 0xB4B2, 0x6564, 0xD975, 0x6565, 0xD978, 0x6566, 0xB4B0, 0x6567, 0xD973, 0x6568, 0xD977,
+ 0x656A, 0xD974, 0x656C, 0xB771, 0x656F, 0xDDBC, 0x6572, 0xBA56, 0x6573, 0xE1F4, 0x6574, 0xBEE3, 0x6575, 0xBCC4, 0x6576, 0xE5BD,
+ 0x6577, 0xBCC5, 0x6578, 0xBCC6, 0x6579, 0xE5BF, 0x657A, 0xE5BE, 0x657B, 0xE5C0, 0x657C, 0xE9B1, 0x657F, 0xE9B0, 0x6580, 0xECEF,
+ 0x6581, 0xECEE, 0x6582, 0xC0C4, 0x6583, 0xC0C5, 0x6584, 0xF248, 0x6587, 0xA4E5, 0x658C, 0xD979, 0x6590, 0xB4B4, 0x6591, 0xB4B3,
+ 0x6592, 0xDDBD, 0x6594, 0xEFD8, 0x6595, 0xC4E3, 0x6596, 0xF7DE, 0x6597, 0xA4E6, 0x6599, 0xAEC6, 0x659B, 0xB1D8, 0x659C, 0xB1D7,
+ 0x659D, 0xD97A, 0x659E, 0xD97B, 0x659F, 0xB772, 0x65A0, 0xE1F5, 0x65A1, 0xBA57, 0x65A2, 0xE9B2, 0x65A4, 0xA4E7, 0x65A5, 0xA5B8,
+ 0x65A7, 0xA9F2, 0x65A8, 0xCCC2, 0x65AA, 0xCEE9, 0x65AB, 0xAC48, 0x65AC, 0xB1D9, 0x65AE, 0xD97C, 0x65AF, 0xB4B5, 0x65B0, 0xB773,
+ 0x65B2, 0xE5C1, 0x65B3, 0xE5C2, 0x65B6, 0xECF0, 0x65B7, 0xC25F, 0x65B8, 0xF8F0, 0x65B9, 0xA4E8, 0x65BB, 0xCCC3, 0x65BC, 0xA9F3,
+ 0x65BD, 0xAC49, 0x65BF, 0xCEEA, 0x65C1, 0xAEC7, 0x65C2, 0xD1D2, 0x65C3, 0xD1D0, 0x65C4, 0xD1D1, 0x65C5, 0xAEC8, 0x65C6, 0xD1CF,
+ 0x65CB, 0xB1DB, 0x65CC, 0xB1DC, 0x65CD, 0xD5A8, 0x65CE, 0xB1DD, 0x65CF, 0xB1DA, 0x65D0, 0xD97D, 0x65D2, 0xD97E, 0x65D3, 0xDDBE,
+ 0x65D6, 0xBA59, 0x65D7, 0xBA58, 0x65DA, 0xECF1, 0x65DB, 0xEFD9, 0x65DD, 0xF24A, 0x65DE, 0xF249, 0x65DF, 0xF44F, 0x65E1, 0xC95E,
+ 0x65E2, 0xAC4A, 0x65E5, 0xA4E9, 0x65E6, 0xA5B9, 0x65E8, 0xA6AE, 0x65E9, 0xA6AD, 0x65EC, 0xA6AF, 0x65ED, 0xA6B0, 0x65EE, 0xC9EE,
+ 0x65EF, 0xC9ED, 0x65F0, 0xCAF8, 0x65F1, 0xA7F2, 0x65F2, 0xCAFB, 0x65F3, 0xCAFA, 0x65F4, 0xCAF9, 0x65F5, 0xCAFC, 0x65FA, 0xA9F4,
+ 0x65FB, 0xCCC9, 0x65FC, 0xCCC5, 0x65FD, 0xCCCE, 0x6600, 0xA9FB, 0x6602, 0xA9F9, 0x6603, 0xCCCA, 0x6604, 0xCCC6, 0x6605, 0xCCCD,
+ 0x6606, 0xA9F8, 0x6607, 0xAA40, 0x6608, 0xCCC8, 0x6609, 0xCCC4, 0x660A, 0xA9FE, 0x660B, 0xCCCB, 0x660C, 0xA9F7, 0x660D, 0xCCCC,
+ 0x660E, 0xA9FA, 0x660F, 0xA9FC, 0x6610, 0xCCD0, 0x6611, 0xCCCF, 0x6612, 0xCCC7, 0x6613, 0xA9F6, 0x6614, 0xA9F5, 0x6615, 0xA9FD,
+ 0x661C, 0xCEEF, 0x661D, 0xCEF5, 0x661F, 0xAC50, 0x6620, 0xAC4D, 0x6621, 0xCEEC, 0x6622, 0xCEF1, 0x6624, 0xAC53, 0x6625, 0xAC4B,
+ 0x6626, 0xCEF0, 0x6627, 0xAC4E, 0x6628, 0xAC51, 0x662B, 0xCEF3, 0x662D, 0xAC4C, 0x662E, 0xCEF8, 0x662F, 0xAC4F, 0x6631, 0xAC52,
+ 0x6632, 0xCEED, 0x6633, 0xCEF2, 0x6634, 0xCEF6, 0x6635, 0xCEEE, 0x6636, 0xCEEB, 0x6639, 0xCEF7, 0x663A, 0xCEF4, 0x6641, 0xAED0,
+ 0x6642, 0xAEC9, 0x6643, 0xAECC, 0x6645, 0xAECF, 0x6647, 0xD1D5, 0x6649, 0xAECA, 0x664A, 0xD1D3, 0x664C, 0xAECE, 0x664F, 0xAECB,
+ 0x6651, 0xD1D6, 0x6652, 0xAECD, 0x6659, 0xD5AC, 0x665A, 0xB1DF, 0x665B, 0xD5AB, 0x665C, 0xD5AD, 0x665D, 0xB1DE, 0x665E, 0xB1E3,
+ 0x665F, 0xD1D4, 0x6661, 0xD5AA, 0x6662, 0xD5AE, 0x6664, 0xB1E0, 0x6665, 0xD5A9, 0x6666, 0xB1E2, 0x6668, 0xB1E1, 0x666A, 0xD9A7,
+ 0x666C, 0xD9A2, 0x666E, 0xB4B6, 0x666F, 0xB4BA, 0x6670, 0xB4B7, 0x6671, 0xD9A5, 0x6672, 0xD9A8, 0x6674, 0xB4B8, 0x6676, 0xB4B9,
+ 0x6677, 0xB4BE, 0x6678, 0xDDC7, 0x6679, 0xD9A6, 0x667A, 0xB4BC, 0x667B, 0xD9A3, 0x667C, 0xD9A1, 0x667E, 0xB4BD, 0x6680, 0xD9A4,
+ 0x6684, 0xB779, 0x6686, 0xDDBF, 0x6687, 0xB776, 0x6688, 0xB777, 0x6689, 0xB775, 0x668A, 0xDDC4, 0x668B, 0xDDC3, 0x668C, 0xDDC0,
+ 0x668D, 0xB77B, 0x6690, 0xDDC2, 0x6691, 0xB4BB, 0x6694, 0xDDC6, 0x6695, 0xDDC1, 0x6696, 0xB778, 0x6697, 0xB774, 0x6698, 0xB77A,
+ 0x6699, 0xDDC5, 0x669D, 0xBA5C, 0x669F, 0xE1F8, 0x66A0, 0xE1F7, 0x66A1, 0xE1F6, 0x66A2, 0xBA5A, 0x66A8, 0xBA5B, 0x66A9, 0xE5C5,
+ 0x66AA, 0xE5C8, 0x66AB, 0xBCC8, 0x66AE, 0xBCC7, 0x66AF, 0xE5C9, 0x66B0, 0xE5C4, 0x66B1, 0xBCCA, 0x66B2, 0xE5C6, 0x66B4, 0xBCC9,
+ 0x66B5, 0xE5C3, 0x66B7, 0xE5C7, 0x66B8, 0xBEE9, 0x66B9, 0xBEE6, 0x66BA, 0xE9BB, 0x66BB, 0xE9BA, 0x66BD, 0xE9B9, 0x66BE, 0xE9B4,
+ 0x66C0, 0xE9B5, 0x66C4, 0xBEE7, 0x66C6, 0xBEE4, 0x66C7, 0xBEE8, 0x66C8, 0xE9B3, 0x66C9, 0xBEE5, 0x66CA, 0xE9B6, 0x66CB, 0xE9B7,
+ 0x66CC, 0xE9BC, 0x66CF, 0xE9B8, 0x66D2, 0xECF2, 0x66D6, 0xC0C7, 0x66D8, 0xEFDC, 0x66D9, 0xC0C6, 0x66DA, 0xEFDA, 0x66DB, 0xEFDB,
+ 0x66DC, 0xC260, 0x66DD, 0xC36E, 0x66DE, 0xF24B, 0x66E0, 0xC36D, 0x66E3, 0xF451, 0x66E4, 0xF452, 0x66E6, 0xC466, 0x66E8, 0xF450,
+ 0x66E9, 0xC4E4, 0x66EB, 0xF7DF, 0x66EC, 0xC5CE, 0x66ED, 0xF8AA, 0x66EE, 0xF8AB, 0x66F0, 0xA4EA, 0x66F2, 0xA6B1, 0x66F3, 0xA6B2,
+ 0x66F4, 0xA7F3, 0x66F6, 0xCCD1, 0x66F7, 0xAC54, 0x66F8, 0xAED1, 0x66F9, 0xB1E4, 0x66FC, 0xB0D2, 0x66FE, 0xB4BF, 0x66FF, 0xB4C0,
+ 0x6700, 0xB3CC, 0x6701, 0xD9A9, 0x6703, 0xB77C, 0x6704, 0xE1FA, 0x6705, 0xE1F9, 0x6708, 0xA4EB, 0x6709, 0xA6B3, 0x670A, 0xCCD2,
+ 0x670B, 0xAA42, 0x670D, 0xAA41, 0x670F, 0xCEF9, 0x6710, 0xCEFA, 0x6712, 0xD1D7, 0x6713, 0xD1D8, 0x6714, 0xAED2, 0x6715, 0xAED3,
+ 0x6717, 0xAED4, 0x6718, 0xD5AF, 0x671B, 0xB1E6, 0x671D, 0xB4C2, 0x671F, 0xB4C1, 0x6720, 0xDDC8, 0x6721, 0xDF7A, 0x6722, 0xE1FB,
+ 0x6723, 0xE9BD, 0x6726, 0xC261, 0x6727, 0xC467, 0x6728, 0xA4EC, 0x672A, 0xA5BC, 0x672B, 0xA5BD, 0x672C, 0xA5BB, 0x672D, 0xA5BE,
+ 0x672E, 0xA5BA, 0x6731, 0xA6B6, 0x6733, 0xC9F6, 0x6734, 0xA6B5, 0x6735, 0xA6B7, 0x6738, 0xC9F1, 0x6739, 0xC9F0, 0x673A, 0xC9F3,
+ 0x673B, 0xC9F2, 0x673C, 0xC9F5, 0x673D, 0xA6B4, 0x673E, 0xC9EF, 0x673F, 0xC9F4, 0x6745, 0xCAFD, 0x6746, 0xA7FD, 0x6747, 0xCAFE,
+ 0x6748, 0xCB43, 0x6749, 0xA7FC, 0x674B, 0xCB47, 0x674C, 0xCB42, 0x674D, 0xCB45, 0x674E, 0xA7F5, 0x674F, 0xA7F6, 0x6750, 0xA7F7,
+ 0x6751, 0xA7F8, 0x6753, 0xA840, 0x6755, 0xCB41, 0x6756, 0xA7FA, 0x6757, 0xA841, 0x6759, 0xCB40, 0x675A, 0xCB46, 0x675C, 0xA7F9,
+ 0x675D, 0xCB44, 0x675E, 0xA7FB, 0x675F, 0xA7F4, 0x6760, 0xA7FE, 0x676A, 0xAA57, 0x676C, 0xCCD4, 0x676D, 0xAA43, 0x676F, 0xAA4D,
+ 0x6770, 0xAA4E, 0x6771, 0xAA46, 0x6772, 0xAA58, 0x6773, 0xAA48, 0x6774, 0xCCDC, 0x6775, 0xAA53, 0x6776, 0xCCD7, 0x6777, 0xAA49,
+ 0x6778, 0xCCE6, 0x6779, 0xCCE7, 0x677A, 0xCCDF, 0x677B, 0xCCD8, 0x677C, 0xAA56, 0x677D, 0xCCE4, 0x677E, 0xAA51, 0x677F, 0xAA4F,
+ 0x6781, 0xCCE5, 0x6783, 0xCCE3, 0x6784, 0xCCDB, 0x6785, 0xCCD3, 0x6786, 0xCCDA, 0x6787, 0xAA4A, 0x6789, 0xAA50, 0x678B, 0xAA44,
+ 0x678C, 0xCCDE, 0x678D, 0xCCDD, 0x678E, 0xCCD5, 0x6790, 0xAA52, 0x6791, 0xCCE1, 0x6792, 0xCCD6, 0x6793, 0xAA55, 0x6794, 0xCCE8,
+ 0x6795, 0xAA45, 0x6797, 0xAA4C, 0x6798, 0xCCD9, 0x6799, 0xCCE2, 0x679A, 0xAA54, 0x679C, 0xAA47, 0x679D, 0xAA4B, 0x679F, 0xCCE0,
+ 0x67AE, 0xCF5B, 0x67AF, 0xAC5C, 0x67B0, 0xAC69, 0x67B2, 0xCF56, 0x67B3, 0xCF4C, 0x67B4, 0xAC62, 0x67B5, 0xCF4A, 0x67B6, 0xAC5B,
+ 0x67B7, 0xCF45, 0x67B8, 0xAC65, 0x67B9, 0xCF52, 0x67BA, 0xCEFE, 0x67BB, 0xCF41, 0x67C0, 0xCF44, 0x67C1, 0xCEFB, 0x67C2, 0xCF51,
+ 0x67C3, 0xCF61, 0x67C4, 0xAC60, 0x67C5, 0xCF46, 0x67C6, 0xCF58, 0x67C8, 0xCEFD, 0x67C9, 0xCF5F, 0x67CA, 0xCF60, 0x67CB, 0xCF63,
+ 0x67CC, 0xCF5A, 0x67CD, 0xCF4B, 0x67CE, 0xCF53, 0x67CF, 0xAC66, 0x67D0, 0xAC59, 0x67D1, 0xAC61, 0x67D2, 0xAC6D, 0x67D3, 0xAC56,
+ 0x67D4, 0xAC58, 0x67D8, 0xCF43, 0x67D9, 0xAC6A, 0x67DA, 0xAC63, 0x67DB, 0xCF5D, 0x67DC, 0xCF40, 0x67DD, 0xAC6C, 0x67DE, 0xAC67,
+ 0x67DF, 0xCF49, 0x67E2, 0xAC6B, 0x67E3, 0xCF50, 0x67E4, 0xCF48, 0x67E5, 0xAC64, 0x67E6, 0xCF5C, 0x67E7, 0xCF54, 0x67E9, 0xAC5E,
+ 0x67EA, 0xCF62, 0x67EB, 0xCF47, 0x67EC, 0xAC5A, 0x67ED, 0xCF59, 0x67EE, 0xCF4F, 0x67EF, 0xAC5F, 0x67F0, 0xCF55, 0x67F1, 0xAC57,
+ 0x67F2, 0xCEFC, 0x67F3, 0xAC68, 0x67F4, 0xAEE3, 0x67F5, 0xAC5D, 0x67F6, 0xCF4E, 0x67F7, 0xCF4D, 0x67F8, 0xCF42, 0x67FA, 0xCF5E,
+ 0x67FC, 0xCF57, 0x67FF, 0xAC55, 0x6812, 0xD1EC, 0x6813, 0xAEEA, 0x6814, 0xD1ED, 0x6816, 0xD1E1, 0x6817, 0xAEDF, 0x6818, 0xAEEB,
+ 0x681A, 0xD1DA, 0x681C, 0xD1E3, 0x681D, 0xD1EB, 0x681F, 0xD1D9, 0x6820, 0xD1F4, 0x6821, 0xAED5, 0x6825, 0xD1F3, 0x6826, 0xD1EE,
+ 0x6828, 0xD1EF, 0x6829, 0xAEDD, 0x682A, 0xAEE8, 0x682B, 0xD1E5, 0x682D, 0xD1E6, 0x682E, 0xD1F0, 0x682F, 0xD1E7, 0x6831, 0xD1E2,
+ 0x6832, 0xD1DC, 0x6833, 0xD1DD, 0x6834, 0xD1EA, 0x6835, 0xD1E4, 0x6838, 0xAED6, 0x6839, 0xAEDA, 0x683A, 0xD1F2, 0x683B, 0xD1DE,
+ 0x683C, 0xAEE6, 0x683D, 0xAEE2, 0x6840, 0xAEE5, 0x6841, 0xAEEC, 0x6842, 0xAEDB, 0x6843, 0xAEE7, 0x6844, 0xD1E9, 0x6845, 0xAEE9,
+ 0x6846, 0xAED8, 0x6848, 0xAED7, 0x6849, 0xD1DB, 0x684B, 0xD1DF, 0x684C, 0xAEE0, 0x684D, 0xD1F1, 0x684E, 0xD1E8, 0x684F, 0xD1E0,
+ 0x6850, 0xAEE4, 0x6851, 0xAEE1, 0x6853, 0xAED9, 0x6854, 0xAEDC, 0x686B, 0xD5C4, 0x686D, 0xD5B4, 0x686E, 0xD5B5, 0x686F, 0xD5B9,
+ 0x6871, 0xD5C8, 0x6872, 0xD5C5, 0x6874, 0xD5BE, 0x6875, 0xD5BD, 0x6876, 0xB1ED, 0x6877, 0xD5C1, 0x6878, 0xD5D0, 0x6879, 0xD5B0,
+ 0x687B, 0xD5D1, 0x687C, 0xD5C3, 0x687D, 0xD5D5, 0x687E, 0xD5C9, 0x687F, 0xB1EC, 0x6880, 0xD5C7, 0x6881, 0xB1E7, 0x6882, 0xB1FC,
+ 0x6883, 0xB1F2, 0x6885, 0xB1F6, 0x6886, 0xB1F5, 0x6887, 0xD5B1, 0x6889, 0xD5CE, 0x688A, 0xD5D4, 0x688B, 0xD5CC, 0x688C, 0xD5D3,
+ 0x688F, 0xD5C0, 0x6890, 0xD5B2, 0x6891, 0xD5D2, 0x6892, 0xD5C2, 0x6893, 0xB1EA, 0x6894, 0xB1F7, 0x6896, 0xD5CB, 0x6897, 0xB1F0,
+ 0x689B, 0xD5CA, 0x689C, 0xD5B3, 0x689D, 0xB1F8, 0x689F, 0xB1FA, 0x68A0, 0xD5CD, 0x68A1, 0xB1FB, 0x68A2, 0xB1E9, 0x68A3, 0xD5BA,
+ 0x68A4, 0xD5CF, 0x68A7, 0xB1EF, 0x68A8, 0xB1F9, 0x68A9, 0xD5BC, 0x68AA, 0xD5C6, 0x68AB, 0xD5B7, 0x68AC, 0xD5BB, 0x68AD, 0xB1F4,
+ 0x68AE, 0xD5B6, 0x68AF, 0xB1E8, 0x68B0, 0xB1F1, 0x68B1, 0xB1EE, 0x68B2, 0xD5BF, 0x68B3, 0xAEDE, 0x68B4, 0xD9C0, 0x68B5, 0xB1EB,
+ 0x68C4, 0xB1F3, 0x68C6, 0xD9C3, 0x68C7, 0xD9D9, 0x68C8, 0xD9CE, 0x68C9, 0xB4D6, 0x68CB, 0xB4D1, 0x68CC, 0xD9BD, 0x68CD, 0xB4D2,
+ 0x68CE, 0xD9CD, 0x68D0, 0xD9C6, 0x68D1, 0xD9D3, 0x68D2, 0xB4CE, 0x68D3, 0xD9AB, 0x68D4, 0xD9D5, 0x68D5, 0xB4C4, 0x68D6, 0xD9B3,
+ 0x68D7, 0xB4C7, 0x68D8, 0xB4C6, 0x68DA, 0xB4D7, 0x68DC, 0xD9AD, 0x68DD, 0xD9CF, 0x68DE, 0xD9D0, 0x68DF, 0xB4C9, 0x68E0, 0xB4C5,
+ 0x68E1, 0xD9BB, 0x68E3, 0xB4D0, 0x68E4, 0xD9B6, 0x68E6, 0xD9D1, 0x68E7, 0xB4CC, 0x68E8, 0xD9C9, 0x68E9, 0xD9D6, 0x68EA, 0xD9B0,
+ 0x68EB, 0xD9B5, 0x68EC, 0xD9AF, 0x68EE, 0xB4CB, 0x68EF, 0xD9C2, 0x68F0, 0xDDDE, 0x68F1, 0xD9B1, 0x68F2, 0xB4CF, 0x68F3, 0xD9BA,
+ 0x68F4, 0xD9D2, 0x68F5, 0xB4CA, 0x68F6, 0xD9B7, 0x68F7, 0xD9B4, 0x68F8, 0xD9C5, 0x68F9, 0xB4CD, 0x68FA, 0xB4C3, 0x68FB, 0xB4D9,
+ 0x68FC, 0xD9C8, 0x68FD, 0xD9C7, 0x6904, 0xD9AC, 0x6905, 0xB4C8, 0x6906, 0xD9D4, 0x6907, 0xD9BC, 0x6908, 0xD9BE, 0x690A, 0xD9CB,
+ 0x690B, 0xD9CA, 0x690C, 0xD9AA, 0x690D, 0xB4D3, 0x690E, 0xB4D5, 0x690F, 0xD9B2, 0x6910, 0xD9B9, 0x6911, 0xD9C1, 0x6912, 0xB4D4,
+ 0x6913, 0xD9B8, 0x6914, 0xD9C4, 0x6915, 0xD9D7, 0x6917, 0xD9CC, 0x6925, 0xD9D8, 0x692A, 0xD9AE, 0x692F, 0xDDF2, 0x6930, 0xB7A6,
+ 0x6932, 0xDDF0, 0x6933, 0xDDDB, 0x6934, 0xDDE0, 0x6935, 0xDDD9, 0x6937, 0xDDEC, 0x6938, 0xDDCB, 0x6939, 0xDDD2, 0x693B, 0xDDEA,
+ 0x693C, 0xDDF4, 0x693D, 0xDDDC, 0x693F, 0xDDCF, 0x6940, 0xDDE2, 0x6941, 0xDDE7, 0x6942, 0xDDD3, 0x6944, 0xDDE4, 0x6945, 0xDDD0,
+ 0x6948, 0xDDD7, 0x6949, 0xDDD8, 0x694A, 0xB7A8, 0x694B, 0xDDEB, 0x694C, 0xDDE9, 0x694E, 0xDDCC, 0x694F, 0xDDEE, 0x6951, 0xDDEF,
+ 0x6952, 0xDDF1, 0x6953, 0xB7AC, 0x6954, 0xB7A4, 0x6956, 0xD5B8, 0x6957, 0xDDD4, 0x6958, 0xDDE6, 0x6959, 0xDDD5, 0x695A, 0xB7A1,
+ 0x695B, 0xB7B1, 0x695C, 0xDDED, 0x695D, 0xB7AF, 0x695E, 0xB7AB, 0x695F, 0xDDCA, 0x6960, 0xB7A3, 0x6962, 0xDDCD, 0x6963, 0xB7B0,
+ 0x6965, 0xDDDD, 0x6966, 0xDDC9, 0x6968, 0xB7A9, 0x6969, 0xDDE1, 0x696A, 0xDDD1, 0x696B, 0xB7AA, 0x696C, 0xDDDA, 0x696D, 0xB77E,
+ 0x696E, 0xB4D8, 0x696F, 0xDDE3, 0x6970, 0xD9BF, 0x6971, 0xDDCE, 0x6974, 0xDDE8, 0x6975, 0xB7A5, 0x6976, 0xDDE5, 0x6977, 0xB7A2,
+ 0x6978, 0xDDDF, 0x6979, 0xB7AD, 0x697A, 0xDDD6, 0x697B, 0xDDF3, 0x6982, 0xB7A7, 0x6983, 0xDEC6, 0x6986, 0xB7AE, 0x698D, 0xE24A,
+ 0x698E, 0xE248, 0x6990, 0xE25E, 0x6991, 0xE246, 0x6993, 0xE258, 0x6994, 0xB77D, 0x6995, 0xBA5F, 0x6996, 0xE242, 0x6997, 0xE25D,
+ 0x6999, 0xE247, 0x699A, 0xE255, 0x699B, 0xBA64, 0x699C, 0xBA5D, 0x699E, 0xE25B, 0x69A0, 0xE240, 0x69A1, 0xE25A, 0x69A3, 0xBA6F,
+ 0x69A4, 0xE251, 0x69A5, 0xE261, 0x69A6, 0xBA6D, 0x69A7, 0xE249, 0x69A8, 0xBA5E, 0x69A9, 0xE24B, 0x69AA, 0xE259, 0x69AB, 0xBA67,
+ 0x69AC, 0xE244, 0x69AD, 0xBA6B, 0x69AE, 0xBA61, 0x69AF, 0xE24D, 0x69B0, 0xE243, 0x69B1, 0xE1FC, 0x69B3, 0xE257, 0x69B4, 0xBA68,
+ 0x69B5, 0xE260, 0x69B6, 0xE1FD, 0x69B7, 0xBA65, 0x69B9, 0xE253, 0x69BB, 0xBA66, 0x69BC, 0xE245, 0x69BD, 0xE250, 0x69BE, 0xE24C,
+ 0x69BF, 0xE24E, 0x69C1, 0xBA60, 0x69C2, 0xE25F, 0x69C3, 0xBA6E, 0x69C4, 0xE24F, 0x69C6, 0xE262, 0x69C9, 0xE1FE, 0x69CA, 0xE254,
+ 0x69CB, 0xBA63, 0x69CC, 0xBA6C, 0x69CD, 0xBA6A, 0x69CE, 0xE241, 0x69CF, 0xE256, 0x69D0, 0xBA69, 0x69D3, 0xBA62, 0x69D4, 0xE252,
+ 0x69D9, 0xE25C, 0x69E2, 0xE5D5, 0x69E4, 0xE5D1, 0x69E5, 0xE5CD, 0x69E6, 0xE5E1, 0x69E7, 0xE5DE, 0x69E8, 0xBCCD, 0x69EB, 0xE5E5,
+ 0x69EC, 0xE5D4, 0x69ED, 0xBCD8, 0x69EE, 0xE5DB, 0x69F1, 0xE5D0, 0x69F2, 0xE5DA, 0x69F3, 0xBCD5, 0x69F4, 0xE5EE, 0x69F6, 0xE5EB,
+ 0x69F7, 0xE5DD, 0x69F8, 0xE5CE, 0x69FB, 0xE5E2, 0x69FC, 0xE5E4, 0x69FD, 0xBCD1, 0x69FE, 0xE5D8, 0x69FF, 0xE5D3, 0x6A00, 0xE5CA,
+ 0x6A01, 0xBCCE, 0x6A02, 0xBCD6, 0x6A04, 0xE5E7, 0x6A05, 0xBCD7, 0x6A06, 0xE5CB, 0x6A07, 0xE5ED, 0x6A08, 0xE5E0, 0x6A09, 0xE5E6,
+ 0x6A0A, 0xBCD4, 0x6A0D, 0xE5E3, 0x6A0F, 0xE5EA, 0x6A11, 0xBCD9, 0x6A13, 0xBCD3, 0x6A14, 0xE5DC, 0x6A15, 0xE5CF, 0x6A16, 0xE5EF,
+ 0x6A17, 0xE5CC, 0x6A18, 0xE5E8, 0x6A19, 0xBCD0, 0x6A1B, 0xE5D6, 0x6A1D, 0xE5D7, 0x6A1E, 0xBCCF, 0x6A1F, 0xBCCC, 0x6A20, 0xE5D2,
+ 0x6A21, 0xBCD2, 0x6A23, 0xBCCB, 0x6A25, 0xE5E9, 0x6A26, 0xE5EC, 0x6A27, 0xE5D9, 0x6A28, 0xE9CA, 0x6A32, 0xE9C2, 0x6A34, 0xE9BE,
+ 0x6A35, 0xBEF6, 0x6A38, 0xBEEB, 0x6A39, 0xBEF0, 0x6A3A, 0xBEEC, 0x6A3B, 0xE9CC, 0x6A3C, 0xE9D7, 0x6A3D, 0xBEEA, 0x6A3E, 0xE9C4,
+ 0x6A3F, 0xE9CD, 0x6A40, 0xE5DF, 0x6A41, 0xE9CE, 0x6A44, 0xBEF1, 0x6A46, 0xE9DD, 0x6A47, 0xBEF5, 0x6A48, 0xBEF8, 0x6A49, 0xE9C0,
+ 0x6A4B, 0xBEF4, 0x6A4D, 0xE9DB, 0x6A4E, 0xE9DC, 0x6A4F, 0xE9D2, 0x6A50, 0xE9D1, 0x6A51, 0xE9C9, 0x6A54, 0xE9D3, 0x6A55, 0xE9DA,
+ 0x6A56, 0xE9D9, 0x6A58, 0xBEEF, 0x6A59, 0xBEED, 0x6A5A, 0xE9CB, 0x6A5B, 0xE9C8, 0x6A5D, 0xE9C5, 0x6A5E, 0xE9D8, 0x6A5F, 0xBEF7,
+ 0x6A60, 0xE9D6, 0x6A61, 0xBEF3, 0x6A62, 0xBEF2, 0x6A64, 0xE9D0, 0x6A66, 0xE9BF, 0x6A67, 0xE9C1, 0x6A68, 0xE9C3, 0x6A69, 0xE9D5,
+ 0x6A6A, 0xE9CF, 0x6A6B, 0xBEEE, 0x6A6D, 0xE9C6, 0x6A6F, 0xE9D4, 0x6A76, 0xE9C7, 0x6A7E, 0xC0CF, 0x6A7F, 0xED45, 0x6A80, 0xC0C8,
+ 0x6A81, 0xECF5, 0x6A83, 0xED41, 0x6A84, 0xC0CA, 0x6A85, 0xED48, 0x6A87, 0xECFC, 0x6A89, 0xECF7, 0x6A8C, 0xED49, 0x6A8D, 0xECF3,
+ 0x6A8E, 0xECFE, 0x6A90, 0xC0D1, 0x6A91, 0xED44, 0x6A92, 0xED4A, 0x6A93, 0xECFD, 0x6A94, 0xC0C9, 0x6A95, 0xED40, 0x6A96, 0xECF4,
+ 0x6A97, 0xC0D0, 0x6A9A, 0xED47, 0x6A9B, 0xECF9, 0x6A9C, 0xC0CC, 0x6A9E, 0xECFB, 0x6A9F, 0xECF8, 0x6AA0, 0xC0D2, 0x6AA1, 0xECFA,
+ 0x6AA2, 0xC0CB, 0x6AA3, 0xC0CE, 0x6AA4, 0xED43, 0x6AA5, 0xECF6, 0x6AA6, 0xED46, 0x6AA8, 0xED42, 0x6AAC, 0xC263, 0x6AAD, 0xEFE7,
+ 0x6AAE, 0xC268, 0x6AAF, 0xC269, 0x6AB3, 0xC262, 0x6AB4, 0xEFE6, 0x6AB6, 0xEFE3, 0x6AB7, 0xEFE4, 0x6AB8, 0xC266, 0x6AB9, 0xEFDE,
+ 0x6ABA, 0xEFE2, 0x6ABB, 0xC265, 0x6ABD, 0xEFDF, 0x6AC2, 0xC267, 0x6AC3, 0xC264, 0x6AC5, 0xEFDD, 0x6AC6, 0xEFE1, 0x6AC7, 0xEFE5,
+ 0x6ACB, 0xF251, 0x6ACC, 0xF24E, 0x6ACD, 0xF257, 0x6ACF, 0xF256, 0x6AD0, 0xF254, 0x6AD1, 0xF24F, 0x6AD3, 0xC372, 0x6AD9, 0xF250,
+ 0x6ADA, 0xC371, 0x6ADB, 0xC0CD, 0x6ADC, 0xF253, 0x6ADD, 0xC370, 0x6ADE, 0xF258, 0x6ADF, 0xF252, 0x6AE0, 0xF24D, 0x6AE1, 0xEFE0,
+ 0x6AE5, 0xC36F, 0x6AE7, 0xF24C, 0x6AE8, 0xF456, 0x6AEA, 0xF455, 0x6AEB, 0xF255, 0x6AEC, 0xC468, 0x6AEE, 0xF459, 0x6AEF, 0xF45A,
+ 0x6AF0, 0xF454, 0x6AF1, 0xF458, 0x6AF3, 0xF453, 0x6AF8, 0xF5D1, 0x6AF9, 0xF457, 0x6AFA, 0xC4E7, 0x6AFB, 0xC4E5, 0x6AFC, 0xF5CF,
+ 0x6B00, 0xF5D2, 0x6B02, 0xF5CE, 0x6B03, 0xF5D0, 0x6B04, 0xC4E6, 0x6B08, 0xF6E5, 0x6B09, 0xF6E6, 0x6B0A, 0xC576, 0x6B0B, 0xF6E4,
+ 0x6B0F, 0xF7E2, 0x6B10, 0xC5CF, 0x6B11, 0xF7E0, 0x6B12, 0xF7E1, 0x6B13, 0xF8AC, 0x6B16, 0xC656, 0x6B17, 0xF8F3, 0x6B18, 0xF8F1,
+ 0x6B19, 0xF8F2, 0x6B1A, 0xF8F4, 0x6B1E, 0xF9BB, 0x6B20, 0xA4ED, 0x6B21, 0xA6B8, 0x6B23, 0xAA59, 0x6B25, 0xCCE9, 0x6B28, 0xCF64,
+ 0x6B2C, 0xD1F5, 0x6B2D, 0xD1F7, 0x6B2F, 0xD1F6, 0x6B31, 0xD1F8, 0x6B32, 0xB1FD, 0x6B33, 0xD5D7, 0x6B34, 0xD1F9, 0x6B36, 0xD5D6,
+ 0x6B37, 0xD5D8, 0x6B38, 0xD5D9, 0x6B39, 0xD9DA, 0x6B3A, 0xB4DB, 0x6B3B, 0xD9DB, 0x6B3C, 0xD9DD, 0x6B3D, 0xB4DC, 0x6B3E, 0xB4DA,
+ 0x6B3F, 0xD9DC, 0x6B41, 0xDDFA, 0x6B42, 0xDDF8, 0x6B43, 0xDDF7, 0x6B45, 0xDDF6, 0x6B46, 0xDDF5, 0x6B47, 0xB7B2, 0x6B48, 0xDDF9,
+ 0x6B49, 0xBA70, 0x6B4A, 0xE263, 0x6B4B, 0xE265, 0x6B4C, 0xBA71, 0x6B4D, 0xE264, 0x6B4E, 0xBCDB, 0x6B50, 0xBCDA, 0x6B51, 0xE5F0,
+ 0x6B54, 0xE9DF, 0x6B55, 0xE9DE, 0x6B56, 0xE9E0, 0x6B59, 0xBEF9, 0x6B5B, 0xED4B, 0x6B5C, 0xC0D3, 0x6B5E, 0xEFE8, 0x6B5F, 0xC26A,
+ 0x6B60, 0xF259, 0x6B61, 0xC577, 0x6B62, 0xA4EE, 0x6B63, 0xA5BF, 0x6B64, 0xA6B9, 0x6B65, 0xA842, 0x6B66, 0xAA5A, 0x6B67, 0xAA5B,
+ 0x6B6A, 0xAC6E, 0x6B6D, 0xD1FA, 0x6B72, 0xB7B3, 0x6B76, 0xE6D1, 0x6B77, 0xBEFA, 0x6B78, 0xC26B, 0x6B79, 0xA4EF, 0x6B7B, 0xA6BA,
+ 0x6B7E, 0xCCEB, 0x6B7F, 0xAA5C, 0x6B80, 0xCCEA, 0x6B82, 0xCF65, 0x6B83, 0xAC6F, 0x6B84, 0xCF66, 0x6B86, 0xAC70, 0x6B88, 0xD1FC,
+ 0x6B89, 0xAEEE, 0x6B8A, 0xAEED, 0x6B8C, 0xD5DE, 0x6B8D, 0xD5DC, 0x6B8E, 0xD5DD, 0x6B8F, 0xD5DB, 0x6B91, 0xD5DA, 0x6B94, 0xD9DE,
+ 0x6B95, 0xD9E1, 0x6B96, 0xB4DE, 0x6B97, 0xD9DF, 0x6B98, 0xB4DD, 0x6B99, 0xD9E0, 0x6B9B, 0xDDFB, 0x6B9E, 0xE266, 0x6B9F, 0xE267,
+ 0x6BA0, 0xE268, 0x6BA2, 0xE5F3, 0x6BA3, 0xE5F2, 0x6BA4, 0xBCDC, 0x6BA5, 0xE5F1, 0x6BA6, 0xE5F4, 0x6BA7, 0xE9E1, 0x6BAA, 0xE9E2,
+ 0x6BAB, 0xE9E3, 0x6BAD, 0xED4C, 0x6BAE, 0xC0D4, 0x6BAF, 0xC26C, 0x6BB0, 0xF25A, 0x6BB2, 0xC4E8, 0x6BB3, 0xC95F, 0x6BB5, 0xAC71,
+ 0x6BB6, 0xCF67, 0x6BB7, 0xAEEF, 0x6BBA, 0xB1FE, 0x6BBC, 0xB4DF, 0x6BBD, 0xD9E2, 0x6BBF, 0xB7B5, 0x6BC0, 0xB7B4, 0x6BC3, 0xE269,
+ 0x6BC4, 0xE26A, 0x6BC5, 0xBCDD, 0x6BC6, 0xBCDE, 0x6BC7, 0xE9E5, 0x6BC8, 0xE9E4, 0x6BC9, 0xEFE9, 0x6BCA, 0xF7E3, 0x6BCB, 0xA4F0,
+ 0x6BCC, 0xC960, 0x6BCD, 0xA5C0, 0x6BCF, 0xA843, 0x6BD0, 0xCB48, 0x6BD2, 0xAC72, 0x6BD3, 0xB7B6, 0x6BD4, 0xA4F1, 0x6BD6, 0xCF68,
+ 0x6BD7, 0xAC73, 0x6BD8, 0xCF69, 0x6BDA, 0xC0D5, 0x6BDB, 0xA4F2, 0x6BDE, 0xCCEC, 0x6BE0, 0xCF6A, 0x6BE2, 0xD242, 0x6BE3, 0xD241,
+ 0x6BE4, 0xD1FE, 0x6BE6, 0xD1FD, 0x6BE7, 0xD243, 0x6BE8, 0xD240, 0x6BEB, 0xB240, 0x6BEC, 0xB241, 0x6BEF, 0xB4E0, 0x6BF0, 0xD9E3,
+ 0x6BF2, 0xD9E4, 0x6BF3, 0xD9E5, 0x6BF7, 0xDE41, 0x6BF8, 0xDE42, 0x6BF9, 0xDE40, 0x6BFB, 0xDDFD, 0x6BFC, 0xDDFE, 0x6BFD, 0xB7B7,
+ 0x6BFE, 0xE26B, 0x6BFF, 0xE5F7, 0x6C00, 0xE5F6, 0x6C01, 0xE5F5, 0x6C02, 0xE5F8, 0x6C03, 0xE9E7, 0x6C04, 0xE9E6, 0x6C05, 0xBEFB,
+ 0x6C06, 0xE9E8, 0x6C08, 0xC0D6, 0x6C09, 0xED4D, 0x6C0B, 0xEFEA, 0x6C0C, 0xF25B, 0x6C0D, 0xF6E7, 0x6C0F, 0xA4F3, 0x6C10, 0xA5C2,
+ 0x6C11, 0xA5C1, 0x6C13, 0xAA5D, 0x6C14, 0xC961, 0x6C15, 0xC97E, 0x6C16, 0xA6BB, 0x6C18, 0xC9F7, 0x6C19, 0xCB49, 0x6C1A, 0xCB4A,
+ 0x6C1B, 0xAA5E, 0x6C1D, 0xCCED, 0x6C1F, 0xAC74, 0x6C20, 0xCF6B, 0x6C21, 0xCF6C, 0x6C23, 0xAEF0, 0x6C24, 0xAEF4, 0x6C25, 0xD244,
+ 0x6C26, 0xAEF3, 0x6C27, 0xAEF1, 0x6C28, 0xAEF2, 0x6C2A, 0xD5DF, 0x6C2B, 0xB242, 0x6C2C, 0xB4E3, 0x6C2E, 0xB4E1, 0x6C2F, 0xB4E2,
+ 0x6C30, 0xD9E6, 0x6C33, 0xBA72, 0x6C34, 0xA4F4, 0x6C36, 0xC9A1, 0x6C38, 0xA5C3, 0x6C3B, 0xC9A4, 0x6C3E, 0xA5C6, 0x6C3F, 0xC9A3,
+ 0x6C40, 0xA5C5, 0x6C41, 0xA5C4, 0x6C42, 0xA844, 0x6C43, 0xC9A2, 0x6C46, 0xC9F8, 0x6C4A, 0xC9FC, 0x6C4B, 0xC9FE, 0x6C4C, 0xCA40,
+ 0x6C4D, 0xA6C5, 0x6C4E, 0xA6C6, 0x6C4F, 0xC9FB, 0x6C50, 0xA6C1, 0x6C52, 0xC9F9, 0x6C54, 0xC9FD, 0x6C55, 0xA6C2, 0x6C57, 0xA6BD,
+ 0x6C59, 0xA6BE, 0x6C5B, 0xA6C4, 0x6C5C, 0xC9FA, 0x6C5D, 0xA6BC, 0x6C5E, 0xA845, 0x6C5F, 0xA6BF, 0x6C60, 0xA6C0, 0x6C61, 0xA6C3,
+ 0x6C65, 0xCB5B, 0x6C66, 0xCB59, 0x6C67, 0xCB4C, 0x6C68, 0xA851, 0x6C69, 0xCB53, 0x6C6A, 0xA84C, 0x6C6B, 0xCB4D, 0x6C6D, 0xCB55,
+ 0x6C6F, 0xCB52, 0x6C70, 0xA84F, 0x6C71, 0xCB51, 0x6C72, 0xA856, 0x6C73, 0xCB5A, 0x6C74, 0xA858, 0x6C76, 0xA85A, 0x6C78, 0xCB4B,
+ 0x6C7A, 0xA84D, 0x6C7B, 0xCB5C, 0x6C7D, 0xA854, 0x6C7E, 0xA857, 0x6C80, 0xCD45, 0x6C81, 0xA847, 0x6C82, 0xA85E, 0x6C83, 0xA855,
+ 0x6C84, 0xCB4E, 0x6C85, 0xA84A, 0x6C86, 0xA859, 0x6C87, 0xCB56, 0x6C88, 0xA848, 0x6C89, 0xA849, 0x6C8A, 0xCD43, 0x6C8B, 0xCB4F,
+ 0x6C8C, 0xA850, 0x6C8D, 0xA85B, 0x6C8E, 0xCB5D, 0x6C8F, 0xCB50, 0x6C90, 0xA84E, 0x6C92, 0xA853, 0x6C93, 0xCCEE, 0x6C94, 0xA85C,
+ 0x6C95, 0xCB57, 0x6C96, 0xA852, 0x6C98, 0xA85D, 0x6C99, 0xA846, 0x6C9A, 0xCB54, 0x6C9B, 0xA84B, 0x6C9C, 0xCB58, 0x6C9D, 0xCD44,
+ 0x6CAB, 0xAA6A, 0x6CAC, 0xAA7A, 0x6CAD, 0xCCF5, 0x6CAE, 0xAA71, 0x6CB0, 0xCD4B, 0x6CB1, 0xAA62, 0x6CB3, 0xAA65, 0x6CB4, 0xCD42,
+ 0x6CB6, 0xCCF3, 0x6CB7, 0xCCF7, 0x6CB8, 0xAA6D, 0x6CB9, 0xAA6F, 0x6CBA, 0xCCFA, 0x6CBB, 0xAA76, 0x6CBC, 0xAA68, 0x6CBD, 0xAA66,
+ 0x6CBE, 0xAA67, 0x6CBF, 0xAA75, 0x6CC0, 0xCD47, 0x6CC1, 0xAA70, 0x6CC2, 0xCCF9, 0x6CC3, 0xCCFB, 0x6CC4, 0xAA6E, 0x6CC5, 0xAA73,
+ 0x6CC6, 0xCCFC, 0x6CC7, 0xCD4A, 0x6CC9, 0xAC75, 0x6CCA, 0xAA79, 0x6CCC, 0xAA63, 0x6CCD, 0xCD49, 0x6CCF, 0xCD4D, 0x6CD0, 0xCCF8,
+ 0x6CD1, 0xCD4F, 0x6CD2, 0xCD40, 0x6CD3, 0xAA6C, 0x6CD4, 0xCCF4, 0x6CD5, 0xAA6B, 0x6CD6, 0xAA7D, 0x6CD7, 0xAA72, 0x6CD9, 0xCCF2,
+ 0x6CDA, 0xCF75, 0x6CDB, 0xAA78, 0x6CDC, 0xAA7C, 0x6CDD, 0xCD41, 0x6CDE, 0xCD46, 0x6CE0, 0xAA7E, 0x6CE1, 0xAA77, 0x6CE2, 0xAA69,
+ 0x6CE3, 0xAA5F, 0x6CE5, 0xAA64, 0x6CE7, 0xCCF6, 0x6CE8, 0xAA60, 0x6CE9, 0xCD4E, 0x6CEB, 0xCCF0, 0x6CEC, 0xCCEF, 0x6CED, 0xCCFD,
+ 0x6CEE, 0xCCF1, 0x6CEF, 0xAA7B, 0x6CF0, 0xAEF5, 0x6CF1, 0xAA74, 0x6CF2, 0xCCFE, 0x6CF3, 0xAA61, 0x6CF5, 0xACA6, 0x6CF9, 0xCD4C,
+ 0x6D00, 0xCF7C, 0x6D01, 0xCFA1, 0x6D03, 0xCFA4, 0x6D04, 0xCF77, 0x6D07, 0xCFA7, 0x6D08, 0xCFAA, 0x6D09, 0xCFAC, 0x6D0A, 0xCF74,
+ 0x6D0B, 0xAC76, 0x6D0C, 0xAC7B, 0x6D0D, 0xD249, 0x6D0E, 0xACAD, 0x6D0F, 0xCFA5, 0x6D10, 0xCFAD, 0x6D11, 0xCF7B, 0x6D12, 0xCF73,
+ 0x6D16, 0xD264, 0x6D17, 0xAC7E, 0x6D18, 0xCFA2, 0x6D19, 0xCF78, 0x6D1A, 0xCF7A, 0x6D1B, 0xACA5, 0x6D1D, 0xCF7D, 0x6D1E, 0xAC7D,
+ 0x6D1F, 0xCF70, 0x6D20, 0xCFA8, 0x6D22, 0xCFAB, 0x6D25, 0xAC7A, 0x6D27, 0xACA8, 0x6D28, 0xCF6D, 0x6D29, 0xACAA, 0x6D2A, 0xAC78,
+ 0x6D2B, 0xACAE, 0x6D2C, 0xCFA9, 0x6D2D, 0xCF6F, 0x6D2E, 0xACAB, 0x6D2F, 0xD25E, 0x6D30, 0xCD48, 0x6D31, 0xAC7C, 0x6D32, 0xAC77,
+ 0x6D33, 0xCF76, 0x6D34, 0xCF6E, 0x6D35, 0xACAC, 0x6D36, 0xACA4, 0x6D37, 0xCFA3, 0x6D38, 0xACA9, 0x6D39, 0xACA7, 0x6D3A, 0xCF79,
+ 0x6D3B, 0xACA1, 0x6D3C, 0xCF71, 0x6D3D, 0xACA2, 0x6D3E, 0xACA3, 0x6D3F, 0xCF72, 0x6D40, 0xCFA6, 0x6D41, 0xAC79, 0x6D42, 0xCF7E,
+ 0x6D58, 0xD24C, 0x6D59, 0xAEFD, 0x6D5A, 0xAF43, 0x6D5E, 0xD255, 0x6D5F, 0xD25B, 0x6D60, 0xD257, 0x6D61, 0xD24A, 0x6D62, 0xD24D,
+ 0x6D63, 0xD246, 0x6D64, 0xD247, 0x6D65, 0xAF4A, 0x6D66, 0xAEFA, 0x6D67, 0xD256, 0x6D68, 0xD25F, 0x6D69, 0xAF45, 0x6D6A, 0xAEF6,
+ 0x6D6C, 0xAF40, 0x6D6D, 0xD24E, 0x6D6E, 0xAF42, 0x6D6F, 0xD24F, 0x6D70, 0xD259, 0x6D74, 0xAF44, 0x6D75, 0xD268, 0x6D76, 0xD248,
+ 0x6D77, 0xAEFC, 0x6D78, 0xAEFB, 0x6D79, 0xAF48, 0x6D7A, 0xD245, 0x6D7B, 0xD266, 0x6D7C, 0xD25A, 0x6D7D, 0xD267, 0x6D7E, 0xD261,
+ 0x6D7F, 0xD253, 0x6D80, 0xD262, 0x6D82, 0xD25C, 0x6D83, 0xD265, 0x6D84, 0xD263, 0x6D85, 0xAF49, 0x6D86, 0xD254, 0x6D87, 0xAEF9,
+ 0x6D88, 0xAEF8, 0x6D89, 0xAF41, 0x6D8A, 0xAF47, 0x6D8B, 0xD260, 0x6D8C, 0xAF46, 0x6D8D, 0xD251, 0x6D8E, 0xB243, 0x6D90, 0xD269,
+ 0x6D91, 0xD250, 0x6D92, 0xD24B, 0x6D93, 0xAEFE, 0x6D94, 0xAF4B, 0x6D95, 0xAEF7, 0x6D97, 0xD258, 0x6D98, 0xD25D, 0x6DAA, 0xB265,
+ 0x6DAB, 0xD5E1, 0x6DAC, 0xD5E5, 0x6DAE, 0xB252, 0x6DAF, 0xB250, 0x6DB2, 0xB247, 0x6DB3, 0xD5E3, 0x6DB4, 0xD5E2, 0x6DB5, 0xB25B,
+ 0x6DB7, 0xD5E8, 0x6DB8, 0xB255, 0x6DBA, 0xD5FA, 0x6DBB, 0xD647, 0x6DBC, 0xB244, 0x6DBD, 0xD5F7, 0x6DBE, 0xD5F0, 0x6DBF, 0xB267,
+ 0x6DC0, 0xD5E0, 0x6DC2, 0xD5FC, 0x6DC4, 0xB264, 0x6DC5, 0xB258, 0x6DC6, 0xB263, 0x6DC7, 0xB24E, 0x6DC8, 0xD5EC, 0x6DC9, 0xD5FE,
+ 0x6DCA, 0xD5F6, 0x6DCB, 0xB24F, 0x6DCC, 0xB249, 0x6DCD, 0xD645, 0x6DCF, 0xD5FD, 0x6DD0, 0xD640, 0x6DD1, 0xB251, 0x6DD2, 0xB259,
+ 0x6DD3, 0xD642, 0x6DD4, 0xD5EA, 0x6DD5, 0xD5FB, 0x6DD6, 0xD5EF, 0x6DD7, 0xD644, 0x6DD8, 0xB25E, 0x6DD9, 0xB246, 0x6DDA, 0xB25C,
+ 0x6DDB, 0xD5F4, 0x6DDC, 0xD5F2, 0x6DDD, 0xD5F3, 0x6DDE, 0xB253, 0x6DDF, 0xD5EE, 0x6DE0, 0xD5ED, 0x6DE1, 0xB248, 0x6DE2, 0xD5E7,
+ 0x6DE3, 0xD646, 0x6DE4, 0xB24A, 0x6DE5, 0xD5F1, 0x6DE6, 0xB268, 0x6DE8, 0xB262, 0x6DE9, 0xD5E6, 0x6DEA, 0xB25F, 0x6DEB, 0xB25D,
+ 0x6DEC, 0xB266, 0x6DED, 0xD5F8, 0x6DEE, 0xB261, 0x6DEF, 0xD252, 0x6DF0, 0xD5F9, 0x6DF1, 0xB260, 0x6DF2, 0xD641, 0x6DF3, 0xB245,
+ 0x6DF4, 0xD5F5, 0x6DF5, 0xB257, 0x6DF6, 0xD5E9, 0x6DF7, 0xB256, 0x6DF9, 0xB254, 0x6DFA, 0xB24C, 0x6DFB, 0xB24B, 0x6DFC, 0xD9E7,
+ 0x6DFD, 0xD643, 0x6E00, 0xD5EB, 0x6E03, 0xD9FC, 0x6E05, 0xB24D, 0x6E19, 0xB541, 0x6E1A, 0xB25A, 0x6E1B, 0xB4EE, 0x6E1C, 0xD9F6,
+ 0x6E1D, 0xB4FC, 0x6E1F, 0xD9EA, 0x6E20, 0xB4EB, 0x6E21, 0xB4E7, 0x6E22, 0xDA49, 0x6E23, 0xB4ED, 0x6E24, 0xB4F1, 0x6E25, 0xB4EC,
+ 0x6E26, 0xB4F5, 0x6E27, 0xDA4D, 0x6E28, 0xDA44, 0x6E2B, 0xD9F1, 0x6E2C, 0xB4FA, 0x6E2D, 0xB4F4, 0x6E2E, 0xD9FD, 0x6E2F, 0xB4E4,
+ 0x6E30, 0xDA4A, 0x6E31, 0xDA43, 0x6E32, 0xB4E8, 0x6E33, 0xD9F7, 0x6E34, 0xB4F7, 0x6E35, 0xDA55, 0x6E36, 0xDA56, 0x6E38, 0xB4E5,
+ 0x6E39, 0xDA48, 0x6E3A, 0xB4F9, 0x6E3B, 0xD9FB, 0x6E3C, 0xD9ED, 0x6E3D, 0xD9EE, 0x6E3E, 0xB4FD, 0x6E3F, 0xD9F2, 0x6E40, 0xD9F9,
+ 0x6E41, 0xD9F3, 0x6E43, 0xB4FB, 0x6E44, 0xB544, 0x6E45, 0xD9EF, 0x6E46, 0xD9E8, 0x6E47, 0xD9E9, 0x6E49, 0xD9EB, 0x6E4A, 0xB4EA,
+ 0x6E4B, 0xD9F8, 0x6E4D, 0xB4F8, 0x6E4E, 0xB542, 0x6E51, 0xD9FA, 0x6E52, 0xDA53, 0x6E53, 0xDA4B, 0x6E54, 0xB4E6, 0x6E55, 0xDA51,
+ 0x6E56, 0xB4F2, 0x6E58, 0xB4F0, 0x6E5A, 0xDA57, 0x6E5B, 0xB4EF, 0x6E5C, 0xDA41, 0x6E5D, 0xD9F4, 0x6E5E, 0xD9FE, 0x6E5F, 0xB547,
+ 0x6E60, 0xDA45, 0x6E61, 0xDA42, 0x6E62, 0xD9F0, 0x6E63, 0xB543, 0x6E64, 0xDA4F, 0x6E65, 0xDA4C, 0x6E66, 0xDA54, 0x6E67, 0xB4E9,
+ 0x6E68, 0xDA40, 0x6E69, 0xB546, 0x6E6B, 0xDA47, 0x6E6E, 0xB4F3, 0x6E6F, 0xB4F6, 0x6E71, 0xDA46, 0x6E72, 0xB545, 0x6E73, 0xD9F5,
+ 0x6E74, 0xD5E4, 0x6E77, 0xDA50, 0x6E78, 0xDA4E, 0x6E79, 0xDA52, 0x6E88, 0xD9EC, 0x6E89, 0xB540, 0x6E8D, 0xDE61, 0x6E8E, 0xDE60,
+ 0x6E8F, 0xDE46, 0x6E90, 0xB7BD, 0x6E92, 0xDE5F, 0x6E93, 0xDE49, 0x6E94, 0xDE4A, 0x6E96, 0xB7C7, 0x6E97, 0xDE68, 0x6E98, 0xB7C2,
+ 0x6E99, 0xDE5E, 0x6E9B, 0xDE43, 0x6E9C, 0xB7C8, 0x6E9D, 0xB7BE, 0x6E9E, 0xDE52, 0x6E9F, 0xDE48, 0x6EA0, 0xDE4B, 0x6EA1, 0xDE63,
+ 0x6EA2, 0xB7B8, 0x6EA3, 0xDE6A, 0x6EA4, 0xDE62, 0x6EA5, 0xB7C1, 0x6EA6, 0xDE57, 0x6EA7, 0xB7CC, 0x6EAA, 0xB7CB, 0x6EAB, 0xB7C5,
+ 0x6EAE, 0xDE69, 0x6EAF, 0xB7B9, 0x6EB0, 0xDE55, 0x6EB1, 0xDE4C, 0x6EB2, 0xDE59, 0x6EB3, 0xDE65, 0x6EB4, 0xB7CD, 0x6EB6, 0xB7BB,
+ 0x6EB7, 0xDE54, 0x6EB9, 0xDE4D, 0x6EBA, 0xB7C4, 0x6EBC, 0xB7C3, 0x6EBD, 0xDE50, 0x6EBE, 0xDE5A, 0x6EBF, 0xDE64, 0x6EC0, 0xDE47,
+ 0x6EC1, 0xDE51, 0x6EC2, 0xB7BC, 0x6EC3, 0xDE5B, 0x6EC4, 0xB7C9, 0x6EC5, 0xB7C0, 0x6EC6, 0xDE4E, 0x6EC7, 0xB7BF, 0x6EC8, 0xDE45,
+ 0x6EC9, 0xDE53, 0x6ECA, 0xDE67, 0x6ECB, 0xB4FE, 0x6ECC, 0xBAB0, 0x6ECD, 0xDE56, 0x6ECE, 0xE26C, 0x6ECF, 0xDE58, 0x6ED0, 0xDE66,
+ 0x6ED1, 0xB7C6, 0x6ED2, 0xDE4F, 0x6ED3, 0xB7BA, 0x6ED4, 0xB7CA, 0x6ED5, 0xBCF0, 0x6ED6, 0xDE44, 0x6ED8, 0xDE5D, 0x6EDC, 0xDE5C,
+ 0x6EEB, 0xE2AA, 0x6EEC, 0xBAAD, 0x6EED, 0xE27D, 0x6EEE, 0xE2A4, 0x6EEF, 0xBAA2, 0x6EF1, 0xE26E, 0x6EF2, 0xBAAF, 0x6EF4, 0xBA77,
+ 0x6EF5, 0xE26D, 0x6EF6, 0xE2B0, 0x6EF7, 0xBAB1, 0x6EF8, 0xE271, 0x6EF9, 0xE2A3, 0x6EFB, 0xE273, 0x6EFC, 0xE2B3, 0x6EFD, 0xE2AF,
+ 0x6EFE, 0xBA75, 0x6EFF, 0xBAA1, 0x6F00, 0xE653, 0x6F01, 0xBAAE, 0x6F02, 0xBA7D, 0x6F03, 0xE26F, 0x6F05, 0xE2AE, 0x6F06, 0xBAA3,
+ 0x6F07, 0xE2AB, 0x6F08, 0xE2B8, 0x6F09, 0xE275, 0x6F0A, 0xE27E, 0x6F0D, 0xE2B6, 0x6F0E, 0xE2AC, 0x6F0F, 0xBA7C, 0x6F12, 0xE27C,
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+ 0x70D2, 0xD272, 0x70D3, 0xD26B, 0x70D4, 0xD275, 0x70D7, 0xD271, 0x70D8, 0xAF4D, 0x70D9, 0xAF4F, 0x70DA, 0xD27A, 0x70DC, 0xD26A,
+ 0x70DD, 0xD26D, 0x70DE, 0xD273, 0x70E0, 0xD274, 0x70E1, 0xD27C, 0x70E2, 0xD270, 0x70E4, 0xAF4E, 0x70EF, 0xB26D, 0x70F0, 0xD64E,
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+ 0x71C1, 0xEA4D, 0x71C2, 0xEA48, 0x71C3, 0xBF55, 0x71C4, 0xBF56, 0x71C5, 0xEA47, 0x71C6, 0xEA56, 0x71C7, 0xEA51, 0x71C8, 0xBF4F,
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+ 0x723D, 0xB26E, 0x723E, 0xBAB8, 0x723F, 0xC962, 0x7241, 0xCFB7, 0x7242, 0xD27D, 0x7244, 0xE2C5, 0x7246, 0xC0F0, 0x7247, 0xA4F9,
+ 0x7248, 0xAAA9, 0x7249, 0xCFB8, 0x724A, 0xCFB9, 0x724B, 0xDA66, 0x724C, 0xB550, 0x724F, 0xDEA4, 0x7252, 0xB7DE, 0x7253, 0xE2C6,
+ 0x7256, 0xBCF8, 0x7258, 0xC37C, 0x7259, 0xA4FA, 0x725A, 0xDA67, 0x725B, 0xA4FB, 0x725D, 0xA6C9, 0x725E, 0xCA42, 0x725F, 0xA6C8,
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+ 0x7278, 0xD27E, 0x7279, 0xAF53, 0x727B, 0xD65D, 0x727C, 0xD65E, 0x727D, 0xB26F, 0x727E, 0xD65C, 0x727F, 0xD65F, 0x7280, 0xB552,
+ 0x7281, 0xB270, 0x7284, 0xB551, 0x7285, 0xDA6B, 0x7286, 0xDA6A, 0x7288, 0xDA68, 0x7289, 0xDA69, 0x728B, 0xDA6C, 0x728C, 0xDEA6,
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+ 0x7297, 0xE2C7, 0x7298, 0xE673, 0x729A, 0xE674, 0x729B, 0xBCF9, 0x729D, 0xEA59, 0x729E, 0xEA5A, 0x72A1, 0xF272, 0x72A2, 0xC37D,
+ 0x72A3, 0xF271, 0x72A4, 0xF270, 0x72A5, 0xF26E, 0x72A6, 0xF26F, 0x72A7, 0xC4EB, 0x72A8, 0xF46C, 0x72A9, 0xF6EE, 0x72AA, 0xF8F7,
+ 0x72AC, 0xA4FC, 0x72AE, 0xC9A5, 0x72AF, 0xA5C7, 0x72B0, 0xC9A6, 0x72B4, 0xCA43, 0x72B5, 0xCA44, 0x72BA, 0xCB66, 0x72BD, 0xCB62,
+ 0x72BF, 0xCB61, 0x72C0, 0xAAAC, 0x72C1, 0xCB65, 0x72C2, 0xA867, 0x72C3, 0xCB63, 0x72C4, 0xA866, 0x72C5, 0xCB67, 0x72C6, 0xCB64,
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+ 0x72D4, 0xCD62, 0x72D6, 0xCD5C, 0x72D7, 0xAAAF, 0x72D8, 0xCD5E, 0x72D9, 0xAAAE, 0x72DA, 0xCD63, 0x72DC, 0xCD60, 0x72DF, 0xCFC2,
+ 0x72E0, 0xACBD, 0x72E1, 0xACBE, 0x72E3, 0xCFC5, 0x72E4, 0xCFBF, 0x72E6, 0xCFC4, 0x72E8, 0xCFC0, 0x72E9, 0xACBC, 0x72EA, 0xCFC3,
+ 0x72EB, 0xCFC1, 0x72F3, 0xD2A8, 0x72F4, 0xD2A5, 0x72F6, 0xD2A7, 0x72F7, 0xAF58, 0x72F8, 0xAF57, 0x72F9, 0xAF55, 0x72FA, 0xD2A4,
+ 0x72FB, 0xD2A9, 0x72FC, 0xAF54, 0x72FD, 0xAF56, 0x72FE, 0xD2A6, 0x72FF, 0xD667, 0x7300, 0xD2A3, 0x7301, 0xD2AA, 0x7307, 0xD662,
+ 0x7308, 0xD666, 0x730A, 0xD665, 0x730B, 0xDA6E, 0x730C, 0xDA79, 0x730F, 0xD668, 0x7311, 0xD663, 0x7312, 0xDA6D, 0x7313, 0xB274,
+ 0x7316, 0xB273, 0x7317, 0xD661, 0x7318, 0xD664, 0x7319, 0xB275, 0x731B, 0xB272, 0x731C, 0xB271, 0x731D, 0xD660, 0x731E, 0xD669,
+ 0x7322, 0xDA70, 0x7323, 0xDA77, 0x7325, 0xB554, 0x7326, 0xDA76, 0x7327, 0xDA73, 0x7329, 0xB556, 0x732D, 0xDA75, 0x7330, 0xDA6F,
+ 0x7331, 0xDA71, 0x7332, 0xDA74, 0x7333, 0xDA72, 0x7334, 0xB555, 0x7335, 0xDA78, 0x7336, 0xB553, 0x7337, 0xB7DF, 0x733A, 0xDEAD,
+ 0x733B, 0xDEAC, 0x733C, 0xDEAA, 0x733E, 0xB7E2, 0x733F, 0xB7E1, 0x7340, 0xDEAE, 0x7342, 0xDEAB, 0x7343, 0xE2CA, 0x7344, 0xBABB,
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+ 0x77B6, 0xED7E, 0x77B7, 0xED7D, 0x77BA, 0xF055, 0x77BB, 0xC2A4, 0x77BC, 0xC2A5, 0x77BD, 0xC2A2, 0x77BF, 0xC2A3, 0x77C2, 0xF054,
+ 0x77C4, 0xF27B, 0x77C7, 0xC3A9, 0x77C9, 0xF279, 0x77CA, 0xF27A, 0x77CC, 0xF474, 0x77CD, 0xF477, 0x77CE, 0xF475, 0x77CF, 0xF476,
+ 0x77D0, 0xF5E0, 0x77D3, 0xC4EF, 0x77D4, 0xF7EB, 0x77D5, 0xF8B4, 0x77D7, 0xC5F7, 0x77D8, 0xF8F8, 0x77D9, 0xF8F9, 0x77DA, 0xC666,
+ 0x77DB, 0xA5D9, 0x77DC, 0xACE1, 0x77DE, 0xDAC3, 0x77E0, 0xDEE3, 0x77E2, 0xA5DA, 0x77E3, 0xA86F, 0x77E5, 0xAABE, 0x77E7, 0xCFE8,
+ 0x77E8, 0xCFE9, 0x77E9, 0xAF78, 0x77EC, 0xDAC4, 0x77ED, 0xB575, 0x77EE, 0xB847, 0x77EF, 0xC142, 0x77F0, 0xEDA4, 0x77F1, 0xF27C,
+ 0x77F2, 0xF478, 0x77F3, 0xA5DB, 0x77F7, 0xCDA1, 0x77F8, 0xCD7A, 0x77F9, 0xCD7C, 0x77FA, 0xCD7E, 0x77FB, 0xCD7D, 0x77FC, 0xCD7B,
+ 0x77FD, 0xAABF, 0x7802, 0xACE2, 0x7803, 0xCFF2, 0x7805, 0xCFED, 0x7806, 0xCFEA, 0x7809, 0xCFF1, 0x780C, 0xACE4, 0x780D, 0xACE5,
+ 0x780E, 0xCFF0, 0x780F, 0xCFEF, 0x7810, 0xCFEE, 0x7811, 0xCFEB, 0x7812, 0xCFEC, 0x7813, 0xCFF3, 0x7814, 0xACE3, 0x781D, 0xAF7C,
+ 0x781F, 0xAFA4, 0x7820, 0xAFA3, 0x7821, 0xD2E1, 0x7822, 0xD2DB, 0x7823, 0xD2D9, 0x7825, 0xAFA1, 0x7826, 0xD6B9, 0x7827, 0xAF7A,
+ 0x7828, 0xD2DE, 0x7829, 0xD2E2, 0x782A, 0xD2E4, 0x782B, 0xD2E0, 0x782C, 0xD2DA, 0x782D, 0xAFA2, 0x782E, 0xD2DF, 0x782F, 0xD2DD,
+ 0x7830, 0xAF79, 0x7831, 0xD2E5, 0x7832, 0xAFA5, 0x7833, 0xD2E3, 0x7834, 0xAF7D, 0x7835, 0xD2DC, 0x7837, 0xAF7E, 0x7838, 0xAF7B,
+ 0x7843, 0xB2B9, 0x7845, 0xD6BA, 0x7848, 0xD6B3, 0x7849, 0xD6B5, 0x784A, 0xD6B7, 0x784C, 0xD6B8, 0x784D, 0xD6B6, 0x784E, 0xB2BA,
+ 0x7850, 0xD6BB, 0x7852, 0xD6B4, 0x785C, 0xDAC8, 0x785D, 0xB576, 0x785E, 0xDAD0, 0x7860, 0xDAC5, 0x7862, 0xDAD1, 0x7864, 0xDAC6,
+ 0x7865, 0xDAC7, 0x7868, 0xDACF, 0x7869, 0xDACE, 0x786A, 0xDACB, 0x786B, 0xB2B8, 0x786C, 0xB577, 0x786D, 0xDAC9, 0x786E, 0xDACC,
+ 0x786F, 0xB578, 0x7870, 0xDACD, 0x7871, 0xDACA, 0x7879, 0xDEEE, 0x787B, 0xDEF2, 0x787C, 0xB84E, 0x787E, 0xE2F0, 0x787F, 0xB851,
+ 0x7880, 0xDEF0, 0x7881, 0xF9D6, 0x7883, 0xDEED, 0x7884, 0xDEE8, 0x7885, 0xDEEA, 0x7886, 0xDEEB, 0x7887, 0xDEE4, 0x7889, 0xB84D,
+ 0x788C, 0xB84C, 0x788E, 0xB848, 0x788F, 0xDEE7, 0x7891, 0xB84F, 0x7893, 0xB850, 0x7894, 0xDEE6, 0x7895, 0xDEE9, 0x7896, 0xDEF1,
+ 0x7897, 0xB84A, 0x7898, 0xB84B, 0x7899, 0xDEEF, 0x789A, 0xDEE5, 0x789E, 0xE2F2, 0x789F, 0xBAD0, 0x78A0, 0xE2F4, 0x78A1, 0xDEEC,
+ 0x78A2, 0xE2F6, 0x78A3, 0xBAD4, 0x78A4, 0xE2F7, 0x78A5, 0xE2F3, 0x78A7, 0xBAD1, 0x78A8, 0xE2EF, 0x78A9, 0xBAD3, 0x78AA, 0xE2EC,
+ 0x78AB, 0xE2F1, 0x78AC, 0xE2F5, 0x78AD, 0xE2EE, 0x78B0, 0xB849, 0x78B2, 0xE2EB, 0x78B3, 0xBAD2, 0x78B4, 0xE2ED, 0x78BA, 0xBD54,
+ 0x78BB, 0xE6C1, 0x78BC, 0xBD58, 0x78BE, 0xBD56, 0x78C1, 0xBACF, 0x78C3, 0xE6C8, 0x78C4, 0xE6C9, 0x78C5, 0xBD53, 0x78C8, 0xE6C7,
+ 0x78C9, 0xE6CA, 0x78CA, 0xBD55, 0x78CB, 0xBD52, 0x78CC, 0xE6C3, 0x78CD, 0xE6C0, 0x78CE, 0xE6C5, 0x78CF, 0xE6C2, 0x78D0, 0xBD59,
+ 0x78D1, 0xE6C4, 0x78D4, 0xE6C6, 0x78D5, 0xBD57, 0x78DA, 0xBF6A, 0x78DB, 0xEAA8, 0x78DD, 0xEAA2, 0x78DE, 0xEAA6, 0x78DF, 0xEAAC,
+ 0x78E0, 0xEAAD, 0x78E1, 0xEAA9, 0x78E2, 0xEAAA, 0x78E3, 0xEAA7, 0x78E5, 0xEAA4, 0x78E7, 0xBF6C, 0x78E8, 0xBF69, 0x78E9, 0xEAA3,
+ 0x78EA, 0xEAA5, 0x78EC, 0xBF6B, 0x78ED, 0xEAAB, 0x78EF, 0xC146, 0x78F2, 0xEDAA, 0x78F3, 0xEDA5, 0x78F4, 0xC145, 0x78F7, 0xC143,
+ 0x78F9, 0xEDAC, 0x78FA, 0xC144, 0x78FB, 0xEDA8, 0x78FC, 0xEDA9, 0x78FD, 0xEDA6, 0x78FE, 0xEDAD, 0x78FF, 0xF056, 0x7901, 0xC147,
+ 0x7902, 0xEDA7, 0x7904, 0xEDAE, 0x7905, 0xEDAB, 0x7909, 0xF05A, 0x790C, 0xF057, 0x790E, 0xC2A6, 0x7910, 0xF05B, 0x7911, 0xF05D,
+ 0x7912, 0xF05C, 0x7913, 0xF058, 0x7914, 0xF059, 0x7917, 0xF2A3, 0x7919, 0xC3AA, 0x791B, 0xF27E, 0x791C, 0xF2A2, 0x791D, 0xF27D,
+ 0x791E, 0xF2A4, 0x7921, 0xF2A1, 0x7923, 0xF47A, 0x7924, 0xF47D, 0x7925, 0xF479, 0x7926, 0xC471, 0x7927, 0xF47B, 0x7928, 0xF47C,
+ 0x7929, 0xF47E, 0x792A, 0xC472, 0x792B, 0xC474, 0x792C, 0xC473, 0x792D, 0xF5E1, 0x792F, 0xF5E3, 0x7931, 0xF5E2, 0x7935, 0xF6F6,
+ 0x7938, 0xF8B5, 0x7939, 0xF8FA, 0x793A, 0xA5DC, 0x793D, 0xCB72, 0x793E, 0xAAC0, 0x793F, 0xCDA3, 0x7940, 0xAAC1, 0x7941, 0xAAC2,
+ 0x7942, 0xCDA2, 0x7944, 0xCFF8, 0x7945, 0xCFF7, 0x7946, 0xACE6, 0x7947, 0xACE9, 0x7948, 0xACE8, 0x7949, 0xACE7, 0x794A, 0xCFF4,
+ 0x794B, 0xCFF6, 0x794C, 0xCFF5, 0x794F, 0xD2E8, 0x7950, 0xAFA7, 0x7951, 0xD2EC, 0x7952, 0xD2EB, 0x7953, 0xD2EA, 0x7954, 0xD2E6,
+ 0x7955, 0xAFA6, 0x7956, 0xAFAA, 0x7957, 0xAFAD, 0x795A, 0xAFAE, 0x795B, 0xD2E7, 0x795C, 0xD2E9, 0x795D, 0xAFAC, 0x795E, 0xAFAB,
+ 0x795F, 0xAFA9, 0x7960, 0xAFA8, 0x7961, 0xD6C2, 0x7963, 0xD6C0, 0x7964, 0xD6BC, 0x7965, 0xB2BB, 0x7967, 0xD6BD, 0x7968, 0xB2BC,
+ 0x7969, 0xD6BE, 0x796A, 0xD6BF, 0x796B, 0xD6C1, 0x796D, 0xB2BD, 0x7970, 0xDAD5, 0x7972, 0xDAD4, 0x7973, 0xDAD3, 0x7974, 0xDAD2,
+ 0x7979, 0xDEF6, 0x797A, 0xB852, 0x797C, 0xDEF3, 0x797D, 0xDEF5, 0x797F, 0xB853, 0x7981, 0xB854, 0x7982, 0xDEF4, 0x7988, 0xE341,
+ 0x798A, 0xE2F9, 0x798B, 0xE2FA, 0x798D, 0xBAD7, 0x798E, 0xBAD5, 0x798F, 0xBAD6, 0x7990, 0xE343, 0x7992, 0xE342, 0x7993, 0xE2FE,
+ 0x7994, 0xE2FD, 0x7995, 0xE2FC, 0x7996, 0xE2FB, 0x7997, 0xE340, 0x7998, 0xE2F8, 0x799A, 0xE6CB, 0x799B, 0xE6D0, 0x799C, 0xE6CE,
+ 0x79A0, 0xE6CD, 0x79A1, 0xE6CC, 0x79A2, 0xE6CF, 0x79A4, 0xEAAE, 0x79A6, 0xBF6D, 0x79A7, 0xC148, 0x79A8, 0xEDB0, 0x79AA, 0xC149,
+ 0x79AB, 0xEDAF, 0x79AC, 0xF05F, 0x79AD, 0xF05E, 0x79AE, 0xC2A7, 0x79B0, 0xF2A5, 0x79B1, 0xC3AB, 0x79B2, 0xF4A1, 0x79B3, 0xC5A1,
+ 0x79B4, 0xF6F7, 0x79B6, 0xF8B7, 0x79B7, 0xF8B6, 0x79B8, 0xC9A8, 0x79B9, 0xACEA, 0x79BA, 0xACEB, 0x79BB, 0xD6C3, 0x79BD, 0xB856,
+ 0x79BE, 0xA5DD, 0x79BF, 0xA872, 0x79C0, 0xA871, 0x79C1, 0xA870, 0x79C5, 0xCDA4, 0x79C8, 0xAAC4, 0x79C9, 0xAAC3, 0x79CB, 0xACEE,
+ 0x79CD, 0xCFFA, 0x79CE, 0xCFFD, 0x79CF, 0xCFFB, 0x79D1, 0xACEC, 0x79D2, 0xACED, 0x79D5, 0xCFF9, 0x79D6, 0xCFFC, 0x79D8, 0xAFB5,
+ 0x79DC, 0xD2F3, 0x79DD, 0xD2F5, 0x79DE, 0xD2F4, 0x79DF, 0xAFB2, 0x79E0, 0xD2EF, 0x79E3, 0xAFB0, 0x79E4, 0xAFAF, 0x79E6, 0xAFB3,
+ 0x79E7, 0xAFB1, 0x79E9, 0xAFB4, 0x79EA, 0xD2F2, 0x79EB, 0xD2ED, 0x79EC, 0xD2EE, 0x79ED, 0xD2F1, 0x79EE, 0xD2F0, 0x79F6, 0xD6C6,
+ 0x79F7, 0xD6C7, 0x79F8, 0xD6C5, 0x79FA, 0xD6C4, 0x79FB, 0xB2BE, 0x7A00, 0xB57D, 0x7A02, 0xDAD6, 0x7A03, 0xDAD8, 0x7A04, 0xDADA,
+ 0x7A05, 0xB57C, 0x7A08, 0xB57A, 0x7A0A, 0xDAD7, 0x7A0B, 0xB57B, 0x7A0C, 0xDAD9, 0x7A0D, 0xB579, 0x7A10, 0xDF41, 0x7A11, 0xDEF7,
+ 0x7A12, 0xDEFA, 0x7A13, 0xDEFE, 0x7A14, 0xB85A, 0x7A15, 0xDEFC, 0x7A17, 0xDEFB, 0x7A18, 0xDEF8, 0x7A19, 0xDEF9, 0x7A1A, 0xB858,
+ 0x7A1B, 0xDF40, 0x7A1C, 0xB857, 0x7A1E, 0xB85C, 0x7A1F, 0xB85B, 0x7A20, 0xB859, 0x7A22, 0xDEFD, 0x7A26, 0xE349, 0x7A28, 0xE348,
+ 0x7A2B, 0xE344, 0x7A2E, 0xBAD8, 0x7A2F, 0xE347, 0x7A30, 0xE346, 0x7A31, 0xBAD9, 0x7A37, 0xBD5E, 0x7A39, 0xE6D2, 0x7A3B, 0xBD5F,
+ 0x7A3C, 0xBD5B, 0x7A3D, 0xBD5D, 0x7A3F, 0xBD5A, 0x7A40, 0xBD5C, 0x7A44, 0xEAAF, 0x7A46, 0xBF70, 0x7A47, 0xEAB1, 0x7A48, 0xEAB0,
+ 0x7A4A, 0xE345, 0x7A4B, 0xBF72, 0x7A4C, 0xBF71, 0x7A4D, 0xBF6E, 0x7A4E, 0xBF6F, 0x7A54, 0xEDB5, 0x7A56, 0xEDB3, 0x7A57, 0xC14A,
+ 0x7A58, 0xEDB4, 0x7A5A, 0xEDB6, 0x7A5B, 0xEDB2, 0x7A5C, 0xEDB1, 0x7A5F, 0xF060, 0x7A60, 0xC2AA, 0x7A61, 0xC2A8, 0x7A62, 0xC2A9,
+ 0x7A67, 0xF2A6, 0x7A68, 0xF2A7, 0x7A69, 0xC3AD, 0x7A6B, 0xC3AC, 0x7A6C, 0xF4A3, 0x7A6D, 0xF4A4, 0x7A6E, 0xF4A2, 0x7A70, 0xF6F8,
+ 0x7A71, 0xF6F9, 0x7A74, 0xA5DE, 0x7A75, 0xCA48, 0x7A76, 0xA873, 0x7A78, 0xCDA5, 0x7A79, 0xAAC6, 0x7A7A, 0xAAC5, 0x7A7B, 0xCDA6,
+ 0x7A7E, 0xD040, 0x7A7F, 0xACEF, 0x7A80, 0xCFFE, 0x7A81, 0xACF0, 0x7A84, 0xAFB6, 0x7A85, 0xD2F8, 0x7A86, 0xD2F6, 0x7A87, 0xD2FC,
+ 0x7A88, 0xAFB7, 0x7A89, 0xD2F7, 0x7A8A, 0xD2FB, 0x7A8B, 0xD2F9, 0x7A8C, 0xD2FA, 0x7A8F, 0xD6C8, 0x7A90, 0xD6CA, 0x7A92, 0xB2BF,
+ 0x7A94, 0xD6C9, 0x7A95, 0xB2C0, 0x7A96, 0xB5A2, 0x7A97, 0xB5A1, 0x7A98, 0xB57E, 0x7A99, 0xDADB, 0x7A9E, 0xDF44, 0x7A9F, 0xB85D,
+ 0x7AA0, 0xB85E, 0x7AA2, 0xDF43, 0x7AA3, 0xDF42, 0x7AA8, 0xE34A, 0x7AA9, 0xBADB, 0x7AAA, 0xBADA, 0x7AAB, 0xE34B, 0x7AAC, 0xE34C,
+ 0x7AAE, 0xBD61, 0x7AAF, 0xBD60, 0x7AB1, 0xEAB5, 0x7AB2, 0xE6D3, 0x7AB3, 0xE6D5, 0x7AB4, 0xE6D4, 0x7AB5, 0xEAB4, 0x7AB6, 0xEAB2,
+ 0x7AB7, 0xEAB6, 0x7AB8, 0xEAB3, 0x7ABA, 0xBF73, 0x7ABE, 0xEDB7, 0x7ABF, 0xC14B, 0x7AC0, 0xEDB8, 0x7AC1, 0xEDB9, 0x7AC4, 0xC2AB,
+ 0x7AC5, 0xC2AC, 0x7AC7, 0xC475, 0x7ACA, 0xC5D1, 0x7ACB, 0xA5DF, 0x7AD1, 0xD041, 0x7AD8, 0xD2FD, 0x7AD9, 0xAFB8, 0x7ADF, 0xB3BA,
+ 0x7AE0, 0xB3B9, 0x7AE3, 0xB5A4, 0x7AE4, 0xDADD, 0x7AE5, 0xB5A3, 0x7AE6, 0xDADC, 0x7AEB, 0xDF45, 0x7AED, 0xBADC, 0x7AEE, 0xE34D,
+ 0x7AEF, 0xBADD, 0x7AF6, 0xC476, 0x7AF7, 0xF4A5, 0x7AF9, 0xA6CB, 0x7AFA, 0xAAC7, 0x7AFB, 0xCDA7, 0x7AFD, 0xACF2, 0x7AFF, 0xACF1,
+ 0x7B00, 0xD042, 0x7B01, 0xD043, 0x7B04, 0xD340, 0x7B05, 0xD342, 0x7B06, 0xAFB9, 0x7B08, 0xD344, 0x7B09, 0xD347, 0x7B0A, 0xD345,
+ 0x7B0E, 0xD346, 0x7B0F, 0xD343, 0x7B10, 0xD2FE, 0x7B11, 0xAFBA, 0x7B12, 0xD348, 0x7B13, 0xD341, 0x7B18, 0xD6D3, 0x7B19, 0xB2C6,
+ 0x7B1A, 0xD6DC, 0x7B1B, 0xB2C3, 0x7B1D, 0xD6D5, 0x7B1E, 0xB2C7, 0x7B20, 0xB2C1, 0x7B22, 0xD6D0, 0x7B23, 0xD6DD, 0x7B24, 0xD6D1,
+ 0x7B25, 0xD6CE, 0x7B26, 0xB2C5, 0x7B28, 0xB2C2, 0x7B2A, 0xD6D4, 0x7B2B, 0xD6D7, 0x7B2C, 0xB2C4, 0x7B2D, 0xD6D8, 0x7B2E, 0xB2C8,
+ 0x7B2F, 0xD6D9, 0x7B30, 0xD6CF, 0x7B31, 0xD6D6, 0x7B32, 0xD6DA, 0x7B33, 0xD6D2, 0x7B34, 0xD6CD, 0x7B35, 0xD6CB, 0x7B38, 0xD6DB,
+ 0x7B3B, 0xDADF, 0x7B40, 0xDAE4, 0x7B44, 0xDAE0, 0x7B45, 0xDAE6, 0x7B46, 0xB5A7, 0x7B47, 0xD6CC, 0x7B48, 0xDAE1, 0x7B49, 0xB5A5,
+ 0x7B4A, 0xDADE, 0x7B4B, 0xB5AC, 0x7B4C, 0xDAE2, 0x7B4D, 0xB5AB, 0x7B4E, 0xDAE3, 0x7B4F, 0xB5AD, 0x7B50, 0xB5A8, 0x7B51, 0xB5AE,
+ 0x7B52, 0xB5A9, 0x7B54, 0xB5AA, 0x7B56, 0xB5A6, 0x7B58, 0xDAE5, 0x7B60, 0xB861, 0x7B61, 0xDF50, 0x7B63, 0xDF53, 0x7B64, 0xDF47,
+ 0x7B65, 0xDF4C, 0x7B66, 0xDF46, 0x7B67, 0xB863, 0x7B69, 0xDF4A, 0x7B6D, 0xDF48, 0x7B6E, 0xB862, 0x7B70, 0xDF4F, 0x7B71, 0xDF4E,
+ 0x7B72, 0xDF4B, 0x7B73, 0xDF4D, 0x7B74, 0xDF49, 0x7B75, 0xBAE1, 0x7B76, 0xDF52, 0x7B77, 0xB85F, 0x7B78, 0xDF51, 0x7B82, 0xE35D,
+ 0x7B84, 0xBAE8, 0x7B85, 0xE358, 0x7B87, 0xBAE7, 0x7B88, 0xE34E, 0x7B8A, 0xE350, 0x7B8B, 0xBAE0, 0x7B8C, 0xE355, 0x7B8D, 0xE354,
+ 0x7B8E, 0xE357, 0x7B8F, 0xBAE5, 0x7B90, 0xE352, 0x7B91, 0xE351, 0x7B94, 0xBAE4, 0x7B95, 0xBADF, 0x7B96, 0xE353, 0x7B97, 0xBAE2,
+ 0x7B98, 0xE359, 0x7B99, 0xE35B, 0x7B9B, 0xE356, 0x7B9C, 0xE34F, 0x7B9D, 0xBAE3, 0x7BA0, 0xBD69, 0x7BA1, 0xBADE, 0x7BA4, 0xE35C,
+ 0x7BAC, 0xE6D9, 0x7BAD, 0xBD62, 0x7BAF, 0xE6DB, 0x7BB1, 0xBD63, 0x7BB4, 0xBD65, 0x7BB5, 0xE6DE, 0x7BB7, 0xE6D6, 0x7BB8, 0xBAE6,
+ 0x7BB9, 0xE6DC, 0x7BBE, 0xE6D8, 0x7BC0, 0xB860, 0x7BC1, 0xBD68, 0x7BC4, 0xBD64, 0x7BC6, 0xBD66, 0x7BC7, 0xBD67, 0x7BC9, 0xBF76,
+ 0x7BCA, 0xE6DD, 0x7BCB, 0xE6D7, 0x7BCC, 0xBD6A, 0x7BCE, 0xE6DA, 0x7BD4, 0xEAC0, 0x7BD5, 0xEABB, 0x7BD8, 0xEAC5, 0x7BD9, 0xBF74,
+ 0x7BDA, 0xEABD, 0x7BDB, 0xBF78, 0x7BDC, 0xEAC3, 0x7BDD, 0xEABA, 0x7BDE, 0xEAB7, 0x7BDF, 0xEAC6, 0x7BE0, 0xC151, 0x7BE1, 0xBF79,
+ 0x7BE2, 0xEAC2, 0x7BE3, 0xEAB8, 0x7BE4, 0xBF77, 0x7BE5, 0xEABC, 0x7BE6, 0xBF7B, 0x7BE7, 0xEAB9, 0x7BE8, 0xEABE, 0x7BE9, 0xBF7A,
+ 0x7BEA, 0xEAC1, 0x7BEB, 0xEAC4, 0x7BF0, 0xEDCB, 0x7BF1, 0xEDCC, 0x7BF2, 0xEDBC, 0x7BF3, 0xEDC3, 0x7BF4, 0xEDC1, 0x7BF7, 0xC14F,
+ 0x7BF8, 0xEDC8, 0x7BF9, 0xEABF, 0x7BFB, 0xEDBF, 0x7BFD, 0xEDC9, 0x7BFE, 0xC14E, 0x7BFF, 0xEDBE, 0x7C00, 0xEDBD, 0x7C01, 0xEDC7,
+ 0x7C02, 0xEDC4, 0x7C03, 0xEDC6, 0x7C05, 0xEDBA, 0x7C06, 0xEDCA, 0x7C07, 0xC14C, 0x7C09, 0xEDC5, 0x7C0A, 0xEDCE, 0x7C0B, 0xEDC2,
+ 0x7C0C, 0xC150, 0x7C0D, 0xC14D, 0x7C0E, 0xEDC0, 0x7C0F, 0xEDBB, 0x7C10, 0xEDCD, 0x7C11, 0xBF75, 0x7C19, 0xF063, 0x7C1C, 0xF061,
+ 0x7C1D, 0xF067, 0x7C1E, 0xC2B0, 0x7C1F, 0xF065, 0x7C20, 0xF064, 0x7C21, 0xC2B2, 0x7C22, 0xF06A, 0x7C23, 0xC2B1, 0x7C25, 0xF06B,
+ 0x7C26, 0xF068, 0x7C27, 0xC2AE, 0x7C28, 0xF069, 0x7C29, 0xF062, 0x7C2A, 0xC2AF, 0x7C2B, 0xC2AD, 0x7C2C, 0xF2AB, 0x7C2D, 0xF066,
+ 0x7C30, 0xF06C, 0x7C33, 0xF2A8, 0x7C37, 0xC3B2, 0x7C38, 0xC3B0, 0x7C39, 0xF2AA, 0x7C3B, 0xF2AC, 0x7C3C, 0xF2A9, 0x7C3D, 0xC3B1,
+ 0x7C3E, 0xC3AE, 0x7C3F, 0xC3AF, 0x7C40, 0xC3B3, 0x7C43, 0xC478, 0x7C45, 0xF4AA, 0x7C47, 0xF4A9, 0x7C48, 0xF4A7, 0x7C49, 0xF4A6,
+ 0x7C4A, 0xF4A8, 0x7C4C, 0xC477, 0x7C4D, 0xC479, 0x7C50, 0xC4F0, 0x7C53, 0xF5E5, 0x7C54, 0xF5E4, 0x7C57, 0xF6FA, 0x7C59, 0xF6FC,
+ 0x7C5A, 0xF6FE, 0x7C5B, 0xF6FD, 0x7C5C, 0xF6FB, 0x7C5F, 0xC5A3, 0x7C60, 0xC5A2, 0x7C63, 0xC5D3, 0x7C64, 0xC5D2, 0x7C65, 0xC5D4,
+ 0x7C66, 0xF7ED, 0x7C67, 0xF7EC, 0x7C69, 0xF8FB, 0x7C6A, 0xF8B8, 0x7C6B, 0xF8FC, 0x7C6C, 0xC658, 0x7C6E, 0xC659, 0x7C6F, 0xF96D,
+ 0x7C72, 0xC67E, 0x7C73, 0xA6CC, 0x7C75, 0xCDA8, 0x7C78, 0xD045, 0x7C79, 0xD046, 0x7C7A, 0xD044, 0x7C7D, 0xACF3, 0x7C7F, 0xD047,
+ 0x7C80, 0xD048, 0x7C81, 0xD049, 0x7C84, 0xD349, 0x7C85, 0xD34F, 0x7C88, 0xD34D, 0x7C89, 0xAFBB, 0x7C8A, 0xD34B, 0x7C8C, 0xD34C,
+ 0x7C8D, 0xD34E, 0x7C91, 0xD34A, 0x7C92, 0xB2C9, 0x7C94, 0xD6DE, 0x7C95, 0xB2CB, 0x7C96, 0xD6E0, 0x7C97, 0xB2CA, 0x7C98, 0xD6DF,
+ 0x7C9E, 0xDAE8, 0x7C9F, 0xB5AF, 0x7CA1, 0xDAEA, 0x7CA2, 0xDAE7, 0x7CA3, 0xD6E1, 0x7CA5, 0xB5B0, 0x7CA7, 0xF9DB, 0x7CA8, 0xDAE9,
+ 0x7CAF, 0xDF56, 0x7CB1, 0xB864, 0x7CB2, 0xDF54, 0x7CB3, 0xB865, 0x7CB4, 0xDF55, 0x7CB5, 0xB866, 0x7CB9, 0xBAE9, 0x7CBA, 0xE361,
+ 0x7CBB, 0xE35E, 0x7CBC, 0xE360, 0x7CBD, 0xBAEA, 0x7CBE, 0xBAEB, 0x7CBF, 0xE35F, 0x7CC5, 0xE6DF, 0x7CC8, 0xE6E0, 0x7CCA, 0xBD6B,
+ 0x7CCB, 0xE6E2, 0x7CCC, 0xE6E1, 0x7CCE, 0xA261, 0x7CD0, 0xEACA, 0x7CD1, 0xEACB, 0x7CD2, 0xEAC7, 0x7CD4, 0xEAC8, 0x7CD5, 0xBF7C,
+ 0x7CD6, 0xBF7D, 0x7CD7, 0xEAC9, 0x7CD9, 0xC157, 0x7CDC, 0xC153, 0x7CDD, 0xC158, 0x7CDE, 0xC154, 0x7CDF, 0xC156, 0x7CE0, 0xC152,
+ 0x7CE2, 0xC155, 0x7CE7, 0xC2B3, 0x7CE8, 0xEDCF, 0x7CEA, 0xF2AE, 0x7CEC, 0xF2AD, 0x7CEE, 0xF4AB, 0x7CEF, 0xC47A, 0x7CF0, 0xC47B,
+ 0x7CF1, 0xF741, 0x7CF2, 0xF5E6, 0x7CF4, 0xF740, 0x7CF6, 0xF8FD, 0x7CF7, 0xF9A4, 0x7CF8, 0xA6CD, 0x7CFB, 0xA874, 0x7CFD, 0xCDA9,
+ 0x7CFE, 0xAAC8, 0x7D00, 0xACF6, 0x7D01, 0xD04C, 0x7D02, 0xACF4, 0x7D03, 0xD04A, 0x7D04, 0xACF9, 0x7D05, 0xACF5, 0x7D06, 0xACFA,
+ 0x7D07, 0xACF8, 0x7D08, 0xD04B, 0x7D09, 0xACF7, 0x7D0A, 0xAFBF, 0x7D0B, 0xAFBE, 0x7D0C, 0xD35A, 0x7D0D, 0xAFC7, 0x7D0E, 0xD353,
+ 0x7D0F, 0xD359, 0x7D10, 0xAFC3, 0x7D11, 0xD352, 0x7D12, 0xD358, 0x7D13, 0xD356, 0x7D14, 0xAFC2, 0x7D15, 0xAFC4, 0x7D16, 0xD355,
+ 0x7D17, 0xAFBD, 0x7D18, 0xD354, 0x7D19, 0xAFC8, 0x7D1A, 0xAFC5, 0x7D1B, 0xAFC9, 0x7D1C, 0xAFC6, 0x7D1D, 0xD351, 0x7D1E, 0xD350,
+ 0x7D1F, 0xD357, 0x7D20, 0xAFC0, 0x7D21, 0xAFBC, 0x7D22, 0xAFC1, 0x7D28, 0xD6F0, 0x7D29, 0xD6E9, 0x7D2B, 0xB5B5, 0x7D2C, 0xD6E8,
+ 0x7D2E, 0xB2CF, 0x7D2F, 0xB2D6, 0x7D30, 0xB2D3, 0x7D31, 0xB2D9, 0x7D32, 0xB2D8, 0x7D33, 0xB2D4, 0x7D35, 0xD6E2, 0x7D36, 0xD6E5,
+ 0x7D38, 0xD6E4, 0x7D39, 0xB2D0, 0x7D3A, 0xD6E6, 0x7D3B, 0xD6EF, 0x7D3C, 0xB2D1, 0x7D3D, 0xD6E3, 0x7D3E, 0xD6EC, 0x7D3F, 0xD6ED,
+ 0x7D40, 0xB2D2, 0x7D41, 0xD6EA, 0x7D42, 0xB2D7, 0x7D43, 0xB2CD, 0x7D44, 0xB2D5, 0x7D45, 0xD6E7, 0x7D46, 0xB2CC, 0x7D47, 0xD6EB,
+ 0x7D4A, 0xD6EE, 0x7D4E, 0xDAFB, 0x7D4F, 0xDAF2, 0x7D50, 0xB5B2, 0x7D51, 0xDAF9, 0x7D52, 0xDAF6, 0x7D53, 0xDAEE, 0x7D54, 0xDAF7,
+ 0x7D55, 0xB5B4, 0x7D56, 0xDAEF, 0x7D58, 0xDAEB, 0x7D5B, 0xB86C, 0x7D5C, 0xDAF4, 0x7D5E, 0xB5B1, 0x7D5F, 0xDAFA, 0x7D61, 0xB5B8,
+ 0x7D62, 0xB5BA, 0x7D63, 0xDAED, 0x7D66, 0xB5B9, 0x7D67, 0xDAF0, 0x7D68, 0xB5B3, 0x7D69, 0xDAF8, 0x7D6A, 0xDAF1, 0x7D6B, 0xDAF5,
+ 0x7D6D, 0xDAF3, 0x7D6E, 0xB5B6, 0x7D6F, 0xDAEC, 0x7D70, 0xB5BB, 0x7D71, 0xB2CE, 0x7D72, 0xB5B7, 0x7D73, 0xB5BC, 0x7D79, 0xB868,
+ 0x7D7A, 0xDF5D, 0x7D7B, 0xDF5F, 0x7D7C, 0xDF61, 0x7D7D, 0xDF65, 0x7D7F, 0xDF5B, 0x7D80, 0xDF59, 0x7D81, 0xB86A, 0x7D83, 0xDF60,
+ 0x7D84, 0xDF64, 0x7D85, 0xDF5C, 0x7D86, 0xDF58, 0x7D88, 0xDF57, 0x7D8C, 0xDF62, 0x7D8D, 0xDF5A, 0x7D8E, 0xDF5E, 0x7D8F, 0xB86B,
+ 0x7D91, 0xB869, 0x7D92, 0xDF66, 0x7D93, 0xB867, 0x7D94, 0xDF63, 0x7D96, 0xE372, 0x7D9C, 0xBAEE, 0x7D9D, 0xE36A, 0x7D9E, 0xBD78,
+ 0x7D9F, 0xE374, 0x7DA0, 0xBAF1, 0x7DA1, 0xE378, 0x7DA2, 0xBAF7, 0x7DA3, 0xE365, 0x7DA6, 0xE375, 0x7DA7, 0xE362, 0x7DA9, 0xE377,
+ 0x7DAA, 0xE366, 0x7DAC, 0xBAFE, 0x7DAD, 0xBAFB, 0x7DAE, 0xE376, 0x7DAF, 0xE370, 0x7DB0, 0xBAED, 0x7DB1, 0xBAF5, 0x7DB2, 0xBAF4,
+ 0x7DB4, 0xBAF3, 0x7DB5, 0xBAF9, 0x7DB7, 0xE363, 0x7DB8, 0xBAFA, 0x7DB9, 0xE371, 0x7DBA, 0xBAF6, 0x7DBB, 0xBAEC, 0x7DBC, 0xE373,
+ 0x7DBD, 0xBAEF, 0x7DBE, 0xBAF0, 0x7DBF, 0xBAF8, 0x7DC0, 0xE368, 0x7DC1, 0xE367, 0x7DC2, 0xE364, 0x7DC4, 0xE36C, 0x7DC5, 0xE369,
+ 0x7DC6, 0xE36D, 0x7DC7, 0xBAFD, 0x7DC9, 0xE379, 0x7DCA, 0xBAF2, 0x7DCB, 0xE36E, 0x7DCC, 0xE36F, 0x7DCE, 0xE36B, 0x7DD2, 0xBAFC,
+ 0x7DD7, 0xE6E7, 0x7DD8, 0xBD70, 0x7DD9, 0xBD79, 0x7DDA, 0xBD75, 0x7DDB, 0xE6E4, 0x7DDD, 0xBD72, 0x7DDE, 0xBD76, 0x7DDF, 0xE6F0,
+ 0x7DE0, 0xBD6C, 0x7DE1, 0xE6E8, 0x7DE3, 0xBD74, 0x7DE6, 0xE6EB, 0x7DE7, 0xE6E6, 0x7DE8, 0xBD73, 0x7DE9, 0xBD77, 0x7DEA, 0xE6E5,
+ 0x7DEC, 0xBD71, 0x7DEE, 0xE6EF, 0x7DEF, 0xBD6E, 0x7DF0, 0xE6EE, 0x7DF1, 0xE6ED, 0x7DF2, 0xBD7A, 0x7DF3, 0xE572, 0x7DF4, 0xBD6D,
+ 0x7DF6, 0xE6EC, 0x7DF7, 0xE6E3, 0x7DF9, 0xBD7B, 0x7DFA, 0xE6EA, 0x7DFB, 0xBD6F, 0x7E03, 0xE6E9, 0x7E08, 0xBFA2, 0x7E09, 0xBFA7,
+ 0x7E0A, 0xBF7E, 0x7E0B, 0xEAD8, 0x7E0C, 0xEACF, 0x7E0D, 0xEADB, 0x7E0E, 0xEAD3, 0x7E0F, 0xEAD9, 0x7E10, 0xBFA8, 0x7E11, 0xBFA1,
+ 0x7E12, 0xEACC, 0x7E13, 0xEAD2, 0x7E14, 0xEADC, 0x7E15, 0xEAD5, 0x7E16, 0xEADA, 0x7E17, 0xEACE, 0x7E1A, 0xEAD6, 0x7E1B, 0xBFA3,
+ 0x7E1C, 0xEAD4, 0x7E1D, 0xBFA6, 0x7E1E, 0xBFA5, 0x7E1F, 0xEAD0, 0x7E20, 0xEAD1, 0x7E21, 0xEACD, 0x7E22, 0xEAD7, 0x7E23, 0xBFA4,
+ 0x7E24, 0xEADE, 0x7E25, 0xEADD, 0x7E29, 0xEDDA, 0x7E2A, 0xEDD6, 0x7E2B, 0xC15F, 0x7E2D, 0xEDD0, 0x7E2E, 0xC159, 0x7E2F, 0xC169,
+ 0x7E30, 0xEDDC, 0x7E31, 0xC161, 0x7E32, 0xC15D, 0x7E33, 0xEDD3, 0x7E34, 0xC164, 0x7E35, 0xC167, 0x7E36, 0xEDDE, 0x7E37, 0xC15C,
+ 0x7E38, 0xEDD5, 0x7E39, 0xC165, 0x7E3A, 0xEDE0, 0x7E3B, 0xEDDD, 0x7E3C, 0xEDD1, 0x7E3D, 0xC160, 0x7E3E, 0xC15A, 0x7E3F, 0xC168,
+ 0x7E40, 0xEDD8, 0x7E41, 0xC163, 0x7E42, 0xEDD2, 0x7E43, 0xC15E, 0x7E44, 0xEDDF, 0x7E45, 0xC162, 0x7E46, 0xC15B, 0x7E47, 0xEDD9,
+ 0x7E48, 0xC166, 0x7E49, 0xEDD7, 0x7E4C, 0xEDDB, 0x7E50, 0xF06E, 0x7E51, 0xF074, 0x7E52, 0xC2B9, 0x7E53, 0xF077, 0x7E54, 0xC2B4,
+ 0x7E55, 0xC2B5, 0x7E56, 0xF06F, 0x7E57, 0xF076, 0x7E58, 0xF071, 0x7E59, 0xC2BA, 0x7E5A, 0xC2B7, 0x7E5C, 0xF06D, 0x7E5E, 0xC2B6,
+ 0x7E5F, 0xF073, 0x7E60, 0xF075, 0x7E61, 0xC2B8, 0x7E62, 0xF072, 0x7E63, 0xF070, 0x7E68, 0xF2B8, 0x7E69, 0xC3B7, 0x7E6A, 0xC3B8,
+ 0x7E6B, 0xC3B4, 0x7E6D, 0xC3B5, 0x7E6F, 0xF2B4, 0x7E70, 0xF2B2, 0x7E72, 0xF2B6, 0x7E73, 0xC3BA, 0x7E74, 0xF2B7, 0x7E75, 0xF2B0,
+ 0x7E76, 0xF2AF, 0x7E77, 0xF2B3, 0x7E78, 0xF2B1, 0x7E79, 0xC3B6, 0x7E7A, 0xF2B5, 0x7E7B, 0xF4AC, 0x7E7C, 0xC47E, 0x7E7D, 0xC47D,
+ 0x7E7E, 0xF4AD, 0x7E80, 0xF4AF, 0x7E81, 0xF4AE, 0x7E82, 0xC4A1, 0x7E86, 0xF5EB, 0x7E87, 0xF5E8, 0x7E88, 0xF5E9, 0x7E8A, 0xF5E7,
+ 0x7E8B, 0xF5EA, 0x7E8C, 0xC4F2, 0x7E8D, 0xF5EC, 0x7E8F, 0xC4F1, 0x7E91, 0xF742, 0x7E93, 0xC5D5, 0x7E94, 0xC5D7, 0x7E95, 0xF7EE,
+ 0x7E96, 0xC5D6, 0x7E97, 0xF8B9, 0x7E98, 0xF940, 0x7E99, 0xF942, 0x7E9A, 0xF8FE, 0x7E9B, 0xF941, 0x7E9C, 0xC66C, 0x7F36, 0xA6CE,
+ 0x7F38, 0xACFB, 0x7F39, 0xD26F, 0x7F3A, 0xAFCA, 0x7F3D, 0xB2DA, 0x7F3E, 0xDAFC, 0x7F3F, 0xDAFD, 0x7F43, 0xEADF, 0x7F44, 0xC16A,
+ 0x7F45, 0xEDE1, 0x7F48, 0xC2BB, 0x7F4A, 0xF2BA, 0x7F4B, 0xF2B9, 0x7F4C, 0xC4A2, 0x7F4D, 0xF5ED, 0x7F4F, 0xF743, 0x7F50, 0xC5F8,
+ 0x7F51, 0xCA49, 0x7F54, 0xAAC9, 0x7F55, 0xA875, 0x7F58, 0xD04D, 0x7F5B, 0xD360, 0x7F5C, 0xD35B, 0x7F5D, 0xD35F, 0x7F5E, 0xD35D,
+ 0x7F5F, 0xAFCB, 0x7F60, 0xD35E, 0x7F61, 0xD35C, 0x7F63, 0xD6F1, 0x7F65, 0xDAFE, 0x7F66, 0xDB40, 0x7F67, 0xDF69, 0x7F68, 0xDF6A,
+ 0x7F69, 0xB86E, 0x7F6A, 0xB86F, 0x7F6B, 0xDF68, 0x7F6C, 0xDF6B, 0x7F6D, 0xDF67, 0x7F6E, 0xB86D, 0x7F70, 0xBB40, 0x7F72, 0xB870,
+ 0x7F73, 0xE37A, 0x7F75, 0xBD7C, 0x7F76, 0xE6F1, 0x7F77, 0xBD7D, 0x7F79, 0xBFA9, 0x7F7A, 0xEAE2, 0x7F7B, 0xEAE0, 0x7F7C, 0xEAE1,
+ 0x7F7D, 0xEDE4, 0x7F7E, 0xEDE3, 0x7F7F, 0xEDE2, 0x7F83, 0xF2BB, 0x7F85, 0xC3B9, 0x7F86, 0xF2BC, 0x7F87, 0xF744, 0x7F88, 0xC5F9,
+ 0x7F89, 0xF8BA, 0x7F8A, 0xA6CF, 0x7F8B, 0xAACB, 0x7F8C, 0xAACA, 0x7F8D, 0xD04F, 0x7F8E, 0xACFC, 0x7F91, 0xD04E, 0x7F92, 0xD362,
+ 0x7F94, 0xAFCC, 0x7F95, 0xD6F2, 0x7F96, 0xD361, 0x7F9A, 0xB2DC, 0x7F9B, 0xD6F5, 0x7F9C, 0xD6F3, 0x7F9D, 0xD6F4, 0x7F9E, 0xB2DB,
+ 0x7FA0, 0xDB42, 0x7FA1, 0xDB43, 0x7FA2, 0xDB41, 0x7FA4, 0xB873, 0x7FA5, 0xDF6D, 0x7FA6, 0xDF6C, 0x7FA7, 0xDF6E, 0x7FA8, 0xB872,
+ 0x7FA9, 0xB871, 0x7FAC, 0xE6F2, 0x7FAD, 0xE6F4, 0x7FAF, 0xBD7E, 0x7FB0, 0xE6F3, 0x7FB1, 0xEAE3, 0x7FB2, 0xBFAA, 0x7FB3, 0xF079,
+ 0x7FB5, 0xF078, 0x7FB6, 0xC3BB, 0x7FB7, 0xF2BD, 0x7FB8, 0xC3BD, 0x7FB9, 0xC3BC, 0x7FBA, 0xF4B0, 0x7FBB, 0xF5EE, 0x7FBC, 0xC4F3,
+ 0x7FBD, 0xA6D0, 0x7FBE, 0xD050, 0x7FBF, 0xACFD, 0x7FC0, 0xD365, 0x7FC1, 0xAFCE, 0x7FC2, 0xD364, 0x7FC3, 0xD363, 0x7FC5, 0xAFCD,
+ 0x7FC7, 0xD6FB, 0x7FC9, 0xD6FD, 0x7FCA, 0xD6F6, 0x7FCB, 0xD6F7, 0x7FCC, 0xB2DD, 0x7FCD, 0xD6F8, 0x7FCE, 0xB2DE, 0x7FCF, 0xD6FC,
+ 0x7FD0, 0xD6F9, 0x7FD1, 0xD6FA, 0x7FD2, 0xB2DF, 0x7FD4, 0xB5BE, 0x7FD5, 0xB5BF, 0x7FD7, 0xDB44, 0x7FDB, 0xDF6F, 0x7FDC, 0xDF70,
+ 0x7FDE, 0xE37E, 0x7FDF, 0xBB43, 0x7FE0, 0xBB41, 0x7FE1, 0xBB42, 0x7FE2, 0xE37B, 0x7FE3, 0xE37C, 0x7FE5, 0xE37D, 0x7FE6, 0xE6F9,
+ 0x7FE8, 0xE6FA, 0x7FE9, 0xBDA1, 0x7FEA, 0xE6F7, 0x7FEB, 0xE6F6, 0x7FEC, 0xE6F8, 0x7FED, 0xE6F5, 0x7FEE, 0xBFAD, 0x7FEF, 0xEAE4,
+ 0x7FF0, 0xBFAB, 0x7FF1, 0xBFAC, 0x7FF2, 0xEDE6, 0x7FF3, 0xC16B, 0x7FF4, 0xEDE5, 0x7FF5, 0xEFA8, 0x7FF7, 0xF07A, 0x7FF8, 0xF07B,
+ 0x7FF9, 0xC2BC, 0x7FFB, 0xC2BD, 0x7FFC, 0xC16C, 0x7FFD, 0xF2BE, 0x7FFE, 0xF2BF, 0x7FFF, 0xF4B1, 0x8000, 0xC4A3, 0x8001, 0xA6D1,
+ 0x8003, 0xA6D2, 0x8004, 0xACFE, 0x8005, 0xAACC, 0x8006, 0xAFCF, 0x8007, 0xD051, 0x800B, 0xB5C0, 0x800C, 0xA6D3, 0x800D, 0xAD41,
+ 0x800E, 0xD052, 0x800F, 0xD053, 0x8010, 0xAD40, 0x8011, 0xAD42, 0x8012, 0xA6D4, 0x8014, 0xD054, 0x8015, 0xAFD1, 0x8016, 0xD366,
+ 0x8017, 0xAFD3, 0x8018, 0xAFD0, 0x8019, 0xAFD2, 0x801B, 0xD741, 0x801C, 0xB2E0, 0x801E, 0xD740, 0x801F, 0xD6FE, 0x8021, 0xDF71,
+ 0x8024, 0xE3A1, 0x8026, 0xBDA2, 0x8028, 0xBFAE, 0x8029, 0xEAE6, 0x802A, 0xEAE5, 0x802C, 0xEDE7, 0x8030, 0xF5EF, 0x8033, 0xA6D5,
+ 0x8034, 0xCB73, 0x8035, 0xCDAA, 0x8036, 0xAD43, 0x8037, 0xD055, 0x8039, 0xD368, 0x803D, 0xAFD4, 0x803E, 0xD367, 0x803F, 0xAFD5,
+ 0x8043, 0xD743, 0x8046, 0xB2E2, 0x8047, 0xD742, 0x8048, 0xD744, 0x804A, 0xB2E1, 0x804F, 0xDB46, 0x8050, 0xDB47, 0x8051, 0xDB45,
+ 0x8052, 0xB5C1, 0x8056, 0xB874, 0x8058, 0xB875, 0x805A, 0xBB45, 0x805C, 0xE3A3, 0x805D, 0xE3A2, 0x805E, 0xBB44, 0x8064, 0xE6FB,
+ 0x8067, 0xE6FC, 0x806C, 0xEAE7, 0x806F, 0xC170, 0x8070, 0xC16F, 0x8071, 0xC16D, 0x8072, 0xC16E, 0x8073, 0xC171, 0x8075, 0xF07C,
+ 0x8076, 0xC2BF, 0x8077, 0xC2BE, 0x8078, 0xF2C0, 0x8079, 0xF4B2, 0x807D, 0xC5A5, 0x807E, 0xC5A4, 0x807F, 0xA6D6, 0x8082, 0xD1FB,
+ 0x8084, 0xB877, 0x8085, 0xB5C2, 0x8086, 0xB876, 0x8087, 0xBB46, 0x8089, 0xA6D7, 0x808A, 0xC9A9, 0x808B, 0xA6D8, 0x808C, 0xA6D9,
+ 0x808F, 0xCDAB, 0x8090, 0xCB76, 0x8092, 0xCB77, 0x8093, 0xA877, 0x8095, 0xCB74, 0x8096, 0xA876, 0x8098, 0xA879, 0x8099, 0xCB75,
+ 0x809A, 0xA87B, 0x809B, 0xA87A, 0x809C, 0xCB78, 0x809D, 0xA878, 0x80A1, 0xAAD1, 0x80A2, 0xAACF, 0x80A3, 0xCDAD, 0x80A5, 0xAACE,
+ 0x80A9, 0xAAD3, 0x80AA, 0xAAD5, 0x80AB, 0xAAD2, 0x80AD, 0xCDB0, 0x80AE, 0xCDAC, 0x80AF, 0xAAD6, 0x80B1, 0xAAD0, 0x80B2, 0xA87C,
+ 0x80B4, 0xAAD4, 0x80B5, 0xCDAF, 0x80B8, 0xCDAE, 0x80BA, 0xAACD, 0x80C2, 0xD05B, 0x80C3, 0xAD47, 0x80C4, 0xAD48, 0x80C5, 0xD05D,
+ 0x80C7, 0xD057, 0x80C8, 0xD05A, 0x80C9, 0xD063, 0x80CA, 0xD061, 0x80CC, 0xAD49, 0x80CD, 0xD067, 0x80CE, 0xAD4C, 0x80CF, 0xD064,
+ 0x80D0, 0xD05C, 0x80D1, 0xD059, 0x80D4, 0xDB49, 0x80D5, 0xD062, 0x80D6, 0xAD44, 0x80D7, 0xD065, 0x80D8, 0xD056, 0x80D9, 0xD05F,
+ 0x80DA, 0xAD46, 0x80DB, 0xAD4B, 0x80DC, 0xD060, 0x80DD, 0xAD4F, 0x80DE, 0xAD4D, 0x80E0, 0xD058, 0x80E1, 0xAD4A, 0x80E3, 0xD05E,
+ 0x80E4, 0xAD4E, 0x80E5, 0xAD45, 0x80E6, 0xD066, 0x80ED, 0xAFDA, 0x80EF, 0xAFE3, 0x80F0, 0xAFD8, 0x80F1, 0xAFD6, 0x80F2, 0xD36A,
+ 0x80F3, 0xAFDE, 0x80F4, 0xAFDB, 0x80F5, 0xD36C, 0x80F8, 0xAFDD, 0x80F9, 0xD36B, 0x80FA, 0xD369, 0x80FB, 0xD36E, 0x80FC, 0xAFE2,
+ 0x80FD, 0xAFE0, 0x80FE, 0xDB48, 0x8100, 0xD36F, 0x8101, 0xD36D, 0x8102, 0xAFD7, 0x8105, 0xAFD9, 0x8106, 0xAFDC, 0x8108, 0xAFDF,
+ 0x810A, 0xAFE1, 0x8115, 0xD74E, 0x8116, 0xB2E4, 0x8118, 0xD745, 0x8119, 0xD747, 0x811B, 0xD748, 0x811D, 0xD750, 0x811E, 0xD74C,
+ 0x811F, 0xD74A, 0x8121, 0xD74D, 0x8122, 0xD751, 0x8123, 0xB2E5, 0x8124, 0xB2E9, 0x8125, 0xD746, 0x8127, 0xD74F, 0x8129, 0xB2E7,
+ 0x812B, 0xB2E6, 0x812C, 0xD74B, 0x812D, 0xD749, 0x812F, 0xB2E3, 0x8130, 0xB2E8, 0x8139, 0xB5C8, 0x813A, 0xDB51, 0x813D, 0xDB4F,
+ 0x813E, 0xB5CA, 0x8143, 0xDB4A, 0x8144, 0xDFA1, 0x8146, 0xB5C9, 0x8147, 0xDB4E, 0x814A, 0xDB4B, 0x814B, 0xB5C5, 0x814C, 0xB5CB,
+ 0x814D, 0xDB50, 0x814E, 0xB5C7, 0x814F, 0xDB4D, 0x8150, 0xBB47, 0x8151, 0xB5C6, 0x8152, 0xDB4C, 0x8153, 0xB5CC, 0x8154, 0xB5C4,
+ 0x8155, 0xB5C3, 0x815B, 0xDF77, 0x815C, 0xDF75, 0x815E, 0xDF7B, 0x8160, 0xDF73, 0x8161, 0xDFA2, 0x8162, 0xDF78, 0x8164, 0xDF72,
+ 0x8165, 0xB87B, 0x8166, 0xB8A3, 0x8167, 0xDF7D, 0x8169, 0xDF76, 0x816B, 0xB87E, 0x816E, 0xB87C, 0x816F, 0xDF7E, 0x8170, 0xB879,
+ 0x8171, 0xB878, 0x8172, 0xDF79, 0x8173, 0xB87D, 0x8174, 0xB5CD, 0x8176, 0xDF7C, 0x8177, 0xDF74, 0x8178, 0xB87A, 0x8179, 0xB8A1,
+ 0x817A, 0xB8A2, 0x817F, 0xBB4C, 0x8180, 0xBB48, 0x8182, 0xBB4D, 0x8183, 0xE3A6, 0x8186, 0xE3A5, 0x8187, 0xE3A7, 0x8188, 0xBB4A,
+ 0x8189, 0xE3A4, 0x818A, 0xBB4B, 0x818B, 0xE3AA, 0x818C, 0xE3A9, 0x818D, 0xE3A8, 0x818F, 0xBB49, 0x8195, 0xE741, 0x8197, 0xE744,
+ 0x8198, 0xBDA8, 0x8199, 0xE743, 0x819A, 0xBDA7, 0x819B, 0xBDA3, 0x819C, 0xBDA4, 0x819D, 0xBDA5, 0x819E, 0xE740, 0x819F, 0xE6FE,
+ 0x81A0, 0xBDA6, 0x81A2, 0xE742, 0x81A3, 0xE6FD, 0x81A6, 0xEAE9, 0x81A7, 0xEAF3, 0x81A8, 0xBFB1, 0x81A9, 0xBFB0, 0x81AB, 0xEAED,
+ 0x81AC, 0xEAEF, 0x81AE, 0xEAEA, 0x81B0, 0xEAEE, 0x81B1, 0xEAE8, 0x81B2, 0xEAF1, 0x81B3, 0xBFAF, 0x81B4, 0xEAF0, 0x81B5, 0xEAEC,
+ 0x81B7, 0xEAF2, 0x81B9, 0xEAEB, 0x81BA, 0xC174, 0x81BB, 0xEDE8, 0x81BC, 0xEDEE, 0x81BD, 0xC178, 0x81BE, 0xC17A, 0x81BF, 0xC177,
+ 0x81C0, 0xC176, 0x81C2, 0xC175, 0x81C3, 0xC173, 0x81C4, 0xEDE9, 0x81C5, 0xEDEC, 0x81C6, 0xC172, 0x81C7, 0xEDED, 0x81C9, 0xC179,
+ 0x81CA, 0xEDEB, 0x81CC, 0xEDEA, 0x81CD, 0xC2C0, 0x81CF, 0xC2C1, 0x81D0, 0xF0A1, 0x81D1, 0xF07D, 0x81D2, 0xF07E, 0x81D5, 0xF2C2,
+ 0x81D7, 0xF2C1, 0x81D8, 0xC3BE, 0x81D9, 0xF4B4, 0x81DA, 0xC4A4, 0x81DB, 0xF4B3, 0x81DD, 0xF5F0, 0x81DE, 0xF745, 0x81DF, 0xC5A6,
+ 0x81E0, 0xF943, 0x81E1, 0xF944, 0x81E2, 0xC5D8, 0x81E3, 0xA6DA, 0x81E5, 0xAAD7, 0x81E6, 0xDB52, 0x81E7, 0xBB4E, 0x81E8, 0xC17B,
+ 0x81E9, 0xEDEF, 0x81EA, 0xA6DB, 0x81EC, 0xAFE5, 0x81ED, 0xAFE4, 0x81EE, 0xDB53, 0x81F2, 0xEAF4, 0x81F3, 0xA6DC, 0x81F4, 0xAD50,
+ 0x81F7, 0xDB54, 0x81F8, 0xDB55, 0x81F9, 0xDB56, 0x81FA, 0xBB4F, 0x81FB, 0xBFB2, 0x81FC, 0xA6DD, 0x81FE, 0xAAD8, 0x81FF, 0xD068,
+ 0x8200, 0xAFE6, 0x8201, 0xD370, 0x8202, 0xB2EA, 0x8204, 0xDB57, 0x8205, 0xB8A4, 0x8207, 0xBB50, 0x8208, 0xBFB3, 0x8209, 0xC17C,
+ 0x820A, 0xC2C2, 0x820B, 0xF4B5, 0x820C, 0xA6DE, 0x820D, 0xAAD9, 0x8210, 0xAFE7, 0x8211, 0xD752, 0x8212, 0xB5CE, 0x8214, 0xBB51,
+ 0x8215, 0xE3AB, 0x8216, 0xE745, 0x821B, 0xA6DF, 0x821C, 0xB5CF, 0x821D, 0xDFA3, 0x821E, 0xBB52, 0x821F, 0xA6E0, 0x8220, 0xCDB1,
+ 0x8221, 0xD069, 0x8222, 0xAD51, 0x8225, 0xD372, 0x8228, 0xAFEA, 0x822A, 0xAFE8, 0x822B, 0xAFE9, 0x822C, 0xAFEB, 0x822F, 0xD371,
+ 0x8232, 0xD757, 0x8233, 0xD754, 0x8234, 0xD756, 0x8235, 0xB2EB, 0x8236, 0xB2ED, 0x8237, 0xB2EC, 0x8238, 0xD753, 0x8239, 0xB2EE,
+ 0x823A, 0xD755, 0x823C, 0xDB58, 0x823D, 0xDB59, 0x823F, 0xDB5A, 0x8240, 0xDFA6, 0x8242, 0xDFA7, 0x8244, 0xDFA5, 0x8245, 0xDFA8,
+ 0x8247, 0xB8A5, 0x8249, 0xDFA4, 0x824B, 0xBB53, 0x824E, 0xE74A, 0x824F, 0xE746, 0x8250, 0xE749, 0x8251, 0xE74B, 0x8252, 0xE748,
+ 0x8253, 0xE747, 0x8255, 0xEAF5, 0x8256, 0xEAF6, 0x8257, 0xEAF7, 0x8258, 0xBFB4, 0x8259, 0xBFB5, 0x825A, 0xEDF1, 0x825B, 0xEDF0,
+ 0x825C, 0xEDF2, 0x825E, 0xF0A3, 0x825F, 0xF0A2, 0x8261, 0xF2C4, 0x8263, 0xF2C5, 0x8264, 0xF2C3, 0x8266, 0xC4A5, 0x8268, 0xF4B6,
+ 0x8269, 0xF4B7, 0x826B, 0xF746, 0x826C, 0xF7EF, 0x826D, 0xF8BB, 0x826E, 0xA6E1, 0x826F, 0xA87D, 0x8271, 0xC17D, 0x8272, 0xA6E2,
+ 0x8274, 0xD758, 0x8275, 0xDB5B, 0x8277, 0xC641, 0x8278, 0xCA4A, 0x827C, 0xCA4B, 0x827D, 0xCA4D, 0x827E, 0xA6E3, 0x827F, 0xCA4E,
+ 0x8280, 0xCA4C, 0x8283, 0xCBA2, 0x8284, 0xCBA3, 0x8285, 0xCB7B, 0x828A, 0xCBA1, 0x828B, 0xA8A1, 0x828D, 0xA8A2, 0x828E, 0xCB7C,
+ 0x828F, 0xCB7A, 0x8290, 0xCB79, 0x8291, 0xCB7D, 0x8292, 0xA87E, 0x8293, 0xCB7E, 0x8294, 0xD06A, 0x8298, 0xCDB6, 0x8299, 0xAADC,
+ 0x829A, 0xCDB5, 0x829B, 0xCDB7, 0x829D, 0xAADB, 0x829E, 0xCDBC, 0x829F, 0xAADF, 0x82A0, 0xCDB2, 0x82A1, 0xCDC0, 0x82A2, 0xCDC6,
+ 0x82A3, 0xAAE6, 0x82A4, 0xCDC3, 0x82A5, 0xAAE3, 0x82A7, 0xCDB9, 0x82A8, 0xCDBF, 0x82A9, 0xCDC1, 0x82AB, 0xCDB4, 0x82AC, 0xAAE2,
+ 0x82AD, 0xAADD, 0x82AE, 0xCDBA, 0x82AF, 0xAAE4, 0x82B0, 0xAAE7, 0x82B1, 0xAAE1, 0x82B3, 0xAADA, 0x82B4, 0xCDBE, 0x82B5, 0xCDB8,
+ 0x82B6, 0xCDC5, 0x82B7, 0xAAE9, 0x82B8, 0xAAE5, 0x82B9, 0xAAE0, 0x82BA, 0xCDBD, 0x82BB, 0xAFEC, 0x82BC, 0xCDBB, 0x82BD, 0xAADE,
+ 0x82BE, 0xAAE8, 0x82C0, 0xCDB3, 0x82C2, 0xCDC2, 0x82C3, 0xCDC4, 0x82D1, 0xAD62, 0x82D2, 0xAD5C, 0x82D3, 0xAD64, 0x82D4, 0xAD61,
+ 0x82D5, 0xD071, 0x82D6, 0xD074, 0x82D7, 0xAD5D, 0x82D9, 0xD06B, 0x82DB, 0xAD56, 0x82DC, 0xAD60, 0x82DE, 0xAD63, 0x82DF, 0xAD65,
+ 0x82E0, 0xD0A2, 0x82E1, 0xD077, 0x82E3, 0xAD55, 0x82E4, 0xD0A1, 0x82E5, 0xAD59, 0x82E6, 0xAD57, 0x82E7, 0xAD52, 0x82E8, 0xD06F,
+ 0x82EA, 0xD07E, 0x82EB, 0xD073, 0x82EC, 0xD076, 0x82ED, 0xD0A5, 0x82EF, 0xAD66, 0x82F0, 0xD07D, 0x82F1, 0xAD5E, 0x82F2, 0xD078,
+ 0x82F3, 0xD0A4, 0x82F4, 0xD075, 0x82F5, 0xD079, 0x82F6, 0xD07C, 0x82F9, 0xD06D, 0x82FA, 0xD0A3, 0x82FB, 0xD07B, 0x82FE, 0xD06C,
+ 0x8300, 0xD070, 0x8301, 0xAD5F, 0x8302, 0xAD5A, 0x8303, 0xAD53, 0x8304, 0xAD58, 0x8305, 0xAD54, 0x8306, 0xAD67, 0x8307, 0xD06E,
+ 0x8308, 0xD3A5, 0x8309, 0xAD5B, 0x830C, 0xD07A, 0x830D, 0xCE41, 0x8316, 0xD3A8, 0x8317, 0xAFFA, 0x8319, 0xD376, 0x831B, 0xD3A3,
+ 0x831C, 0xD37D, 0x831E, 0xD3B2, 0x8320, 0xD3AA, 0x8322, 0xD37E, 0x8324, 0xD3A9, 0x8325, 0xD378, 0x8326, 0xD37C, 0x8327, 0xD3B5,
+ 0x8328, 0xAFFD, 0x8329, 0xD3AD, 0x832A, 0xD3A4, 0x832B, 0xAFED, 0x832C, 0xD3B3, 0x832D, 0xD374, 0x832F, 0xD3AC, 0x8331, 0xAFFC,
+ 0x8332, 0xAFF7, 0x8333, 0xD373, 0x8334, 0xAFF5, 0x8335, 0xAFF4, 0x8336, 0xAFF9, 0x8337, 0xD3AB, 0x8338, 0xAFF1, 0x8339, 0xAFF8,
+ 0x833A, 0xD072, 0x833B, 0xDB5C, 0x833C, 0xD3A6, 0x833F, 0xD37A, 0x8340, 0xAFFB, 0x8341, 0xD37B, 0x8342, 0xD3A1, 0x8343, 0xAFFE,
+ 0x8344, 0xD375, 0x8345, 0xD3AF, 0x8347, 0xD3AE, 0x8348, 0xD3B6, 0x8349, 0xAFF3, 0x834A, 0xAFF0, 0x834B, 0xD3B4, 0x834C, 0xD3B0,
+ 0x834D, 0xD3A7, 0x834E, 0xD3A2, 0x834F, 0xAFF6, 0x8350, 0xAFF2, 0x8351, 0xD377, 0x8352, 0xAFEE, 0x8353, 0xD3B1, 0x8354, 0xAFEF,
+ 0x8356, 0xD379, 0x8373, 0xD75E, 0x8374, 0xD760, 0x8375, 0xD765, 0x8376, 0xD779, 0x8377, 0xB2FC, 0x8378, 0xB2F2, 0x837A, 0xD75D,
+ 0x837B, 0xB2FD, 0x837C, 0xB2FE, 0x837D, 0xD768, 0x837E, 0xD76F, 0x837F, 0xD775, 0x8381, 0xD762, 0x8383, 0xD769, 0x8386, 0xB340,
+ 0x8387, 0xD777, 0x8388, 0xD772, 0x8389, 0xB2FA, 0x838A, 0xB2F8, 0x838B, 0xD76E, 0x838C, 0xD76A, 0x838D, 0xD75C, 0x838E, 0xB2EF,
+ 0x838F, 0xD761, 0x8390, 0xD759, 0x8392, 0xB2F7, 0x8393, 0xB2F9, 0x8394, 0xD766, 0x8395, 0xD763, 0x8396, 0xB2F4, 0x8397, 0xD773,
+ 0x8398, 0xB2F1, 0x8399, 0xD764, 0x839A, 0xD77A, 0x839B, 0xD76C, 0x839D, 0xD76B, 0x839E, 0xB2F0, 0x83A0, 0xB2FB, 0x83A2, 0xB2F3,
+ 0x83A3, 0xD75A, 0x83A4, 0xD75F, 0x83A5, 0xD770, 0x83A6, 0xD776, 0x83A7, 0xB341, 0x83A8, 0xD75B, 0x83A9, 0xD767, 0x83AA, 0xD76D,
+ 0x83AB, 0xB2F6, 0x83AE, 0xD778, 0x83AF, 0xD771, 0x83B0, 0xD774, 0x83BD, 0xB2F5, 0x83BF, 0xDB6C, 0x83C0, 0xDB60, 0x83C1, 0xB5D7,
+ 0x83C2, 0xDB7D, 0x83C3, 0xDBA7, 0x83C4, 0xDBAA, 0x83C5, 0xB5D5, 0x83C6, 0xDB68, 0x83C7, 0xDBA3, 0x83C8, 0xDB69, 0x83C9, 0xDB77,
+ 0x83CA, 0xB5E2, 0x83CB, 0xDB73, 0x83CC, 0xB5DF, 0x83CE, 0xDB74, 0x83CF, 0xDB5D, 0x83D1, 0xDBA4, 0x83D4, 0xB5E8, 0x83D5, 0xDBA1,
+ 0x83D6, 0xDB75, 0x83D7, 0xDBAC, 0x83D8, 0xDB70, 0x83D9, 0xDFC8, 0x83DB, 0xDBAF, 0x83DC, 0xB5E6, 0x83DD, 0xDB6E, 0x83DE, 0xDB7A,
+ 0x83DF, 0xB5E9, 0x83E0, 0xB5D4, 0x83E1, 0xDB72, 0x83E2, 0xDBAD, 0x83E3, 0xDB6B, 0x83E4, 0xDB64, 0x83E5, 0xDB6F, 0x83E7, 0xDB63,
+ 0x83E8, 0xDB61, 0x83E9, 0xB5D0, 0x83EA, 0xDBA5, 0x83EB, 0xDB6A, 0x83EC, 0xDBA8, 0x83EE, 0xDBA9, 0x83EF, 0xB5D8, 0x83F0, 0xB5DD,
+ 0x83F1, 0xB5D9, 0x83F2, 0xB5E1, 0x83F3, 0xDB7E, 0x83F4, 0xB5DA, 0x83F5, 0xDB76, 0x83F6, 0xDB66, 0x83F8, 0xB5D2, 0x83F9, 0xDB5E,
+ 0x83FA, 0xDBA2, 0x83FB, 0xDBAB, 0x83FC, 0xDB65, 0x83FD, 0xB5E0, 0x83FE, 0xDBB0, 0x83FF, 0xDB71, 0x8401, 0xDB6D, 0x8403, 0xB5D1,
+ 0x8404, 0xB5E5, 0x8406, 0xDB7C, 0x8407, 0xB5E7, 0x8409, 0xDB78, 0x840A, 0xB5DC, 0x840B, 0xB5D6, 0x840C, 0xB5DE, 0x840D, 0xB5D3,
+ 0x840E, 0xB5E4, 0x840F, 0xDB79, 0x8410, 0xDB67, 0x8411, 0xDB7B, 0x8412, 0xDB62, 0x8413, 0xDBA6, 0x841B, 0xDBAE, 0x8423, 0xDB5F,
+ 0x8429, 0xDFC7, 0x842B, 0xDFDD, 0x842C, 0xB855, 0x842D, 0xDFCC, 0x842F, 0xDFCA, 0x8430, 0xDFB5, 0x8431, 0xB8A9, 0x8432, 0xDFC5,
+ 0x8433, 0xDFD9, 0x8434, 0xDFC1, 0x8435, 0xB8B1, 0x8436, 0xDFD8, 0x8437, 0xDFBF, 0x8438, 0xB5E3, 0x8439, 0xDFCF, 0x843A, 0xDFC0,
+ 0x843B, 0xDFD6, 0x843C, 0xB8B0, 0x843D, 0xB8A8, 0x843F, 0xDFAA, 0x8440, 0xDFB2, 0x8442, 0xDFCB, 0x8443, 0xDFC3, 0x8444, 0xDFDC,
+ 0x8445, 0xDFC6, 0x8446, 0xB8B6, 0x8447, 0xDFD7, 0x8449, 0xB8AD, 0x844B, 0xDFC9, 0x844C, 0xDFD1, 0x844D, 0xDFB6, 0x844E, 0xDFD0,
+ 0x8450, 0xDFE1, 0x8451, 0xDFB1, 0x8452, 0xDFD2, 0x8454, 0xDFDF, 0x8456, 0xDFAB, 0x8457, 0xB5DB, 0x8459, 0xDFB9, 0x845A, 0xDFB8,
+ 0x845B, 0xB8AF, 0x845D, 0xDFBC, 0x845E, 0xDFBE, 0x845F, 0xDFCD, 0x8460, 0xDFDE, 0x8461, 0xB8B2, 0x8463, 0xB8B3, 0x8465, 0xDFB0,
+ 0x8466, 0xB8AB, 0x8467, 0xDFB4, 0x8468, 0xDFDA, 0x8469, 0xB8B4, 0x846B, 0xB8AC, 0x846C, 0xB8AE, 0x846D, 0xB8B5, 0x846E, 0xDFE0,
+ 0x846F, 0xDFD3, 0x8470, 0xDFCE, 0x8473, 0xDFBB, 0x8474, 0xDFBA, 0x8475, 0xB8AA, 0x8476, 0xDFAC, 0x8477, 0xB8A7, 0x8478, 0xDFC4,
+ 0x8479, 0xDFAD, 0x847A, 0xDFC2, 0x847D, 0xDFB7, 0x847E, 0xDFDB, 0x8482, 0xB8A6, 0x8486, 0xDFB3, 0x848D, 0xDFAF, 0x848E, 0xDFD5,
+ 0x848F, 0xDFAE, 0x8490, 0xBB60, 0x8491, 0xE3D3, 0x8494, 0xE3C2, 0x8497, 0xE3AC, 0x8498, 0xE3CA, 0x8499, 0xBB58, 0x849A, 0xE3BB,
+ 0x849B, 0xE3C5, 0x849C, 0xBB5B, 0x849D, 0xE3BE, 0x849E, 0xBB59, 0x849F, 0xE3AF, 0x84A0, 0xE3CD, 0x84A1, 0xE3AE, 0x84A2, 0xE3C1,
+ 0x84A4, 0xE3AD, 0x84A7, 0xE3BF, 0x84A8, 0xE3C8, 0x84A9, 0xE3C6, 0x84AA, 0xE3BA, 0x84AB, 0xE3B5, 0x84AC, 0xE3B3, 0x84AE, 0xE3B4,
+ 0x84AF, 0xE3C7, 0x84B0, 0xE3D2, 0x84B1, 0xE3BC, 0x84B2, 0xBB5A, 0x84B4, 0xE3B7, 0x84B6, 0xE3CB, 0x84B8, 0xBB5D, 0x84B9, 0xE3B6,
+ 0x84BA, 0xE3B0, 0x84BB, 0xE3C0, 0x84BC, 0xBB61, 0x84BF, 0xBB55, 0x84C0, 0xBB5E, 0x84C1, 0xE3B8, 0x84C2, 0xE3B2, 0x84C4, 0xBB57,
+ 0x84C5, 0xDFD4, 0x84C6, 0xBB56, 0x84C7, 0xE3C3, 0x84C9, 0xBB54, 0x84CA, 0xBB63, 0x84CB, 0xBB5C, 0x84CC, 0xE3C4, 0x84CD, 0xE3B9,
+ 0x84CE, 0xE3B1, 0x84CF, 0xE3CC, 0x84D0, 0xE3BD, 0x84D1, 0xBB62, 0x84D2, 0xE3D0, 0x84D3, 0xBB5F, 0x84D4, 0xE3CF, 0x84D6, 0xE3C9,
+ 0x84D7, 0xE3CE, 0x84DB, 0xE3D1, 0x84E7, 0xE773, 0x84E8, 0xE774, 0x84E9, 0xE767, 0x84EA, 0xE766, 0x84EB, 0xE762, 0x84EC, 0xBDB4,
+ 0x84EE, 0xBDAC, 0x84EF, 0xE776, 0x84F0, 0xE775, 0x84F1, 0xDFA9, 0x84F2, 0xE75F, 0x84F3, 0xE763, 0x84F4, 0xE75D, 0x84F6, 0xE770,
+ 0x84F7, 0xE761, 0x84F9, 0xE777, 0x84FA, 0xE75A, 0x84FB, 0xE758, 0x84FC, 0xE764, 0x84FD, 0xE76E, 0x84FE, 0xE769, 0x84FF, 0xBDB6,
+ 0x8500, 0xE74F, 0x8502, 0xE76D, 0x8506, 0xBDB7, 0x8507, 0xDFBD, 0x8508, 0xE75B, 0x8509, 0xE752, 0x850A, 0xE755, 0x850B, 0xE77B,
+ 0x850C, 0xE75C, 0x850D, 0xE753, 0x850E, 0xE751, 0x850F, 0xE74E, 0x8511, 0xBDB0, 0x8512, 0xE765, 0x8513, 0xBDAF, 0x8514, 0xBDB3,
+ 0x8515, 0xE760, 0x8516, 0xE768, 0x8517, 0xBDA9, 0x8518, 0xE778, 0x8519, 0xE77C, 0x851A, 0xBDAB, 0x851C, 0xE757, 0x851D, 0xE76B,
+ 0x851E, 0xE76F, 0x851F, 0xE754, 0x8520, 0xE779, 0x8521, 0xBDB2, 0x8523, 0xBDB1, 0x8524, 0xE74C, 0x8525, 0xBDB5, 0x8526, 0xE772,
+ 0x8527, 0xE756, 0x8528, 0xE76A, 0x8529, 0xE750, 0x852A, 0xE75E, 0x852B, 0xE759, 0x852C, 0xBDAD, 0x852D, 0xBDAE, 0x852E, 0xE76C,
+ 0x852F, 0xE77D, 0x8530, 0xE77A, 0x8531, 0xE771, 0x853B, 0xE74D, 0x853D, 0xBDAA, 0x853E, 0xEB49, 0x8540, 0xEB40, 0x8541, 0xEB43,
+ 0x8543, 0xBFBB, 0x8544, 0xEB45, 0x8545, 0xEAF9, 0x8546, 0xEB41, 0x8547, 0xEB47, 0x8548, 0xBFB8, 0x8549, 0xBFBC, 0x854A, 0xBFB6,
+ 0x854D, 0xEAFB, 0x854E, 0xEB4C, 0x8551, 0xEB46, 0x8553, 0xEAFC, 0x8554, 0xEB55, 0x8555, 0xEB4F, 0x8556, 0xEAF8, 0x8557, 0xEE46,
+ 0x8558, 0xEAFE, 0x8559, 0xBFB7, 0x855B, 0xEB4A, 0x855D, 0xEB54, 0x855E, 0xBFBF, 0x8560, 0xEB51, 0x8561, 0xEAFD, 0x8562, 0xEB44,
+ 0x8563, 0xEB48, 0x8564, 0xEB42, 0x8565, 0xEB56, 0x8566, 0xEB53, 0x8567, 0xEB50, 0x8568, 0xBFB9, 0x8569, 0xBFBA, 0x856A, 0xBFBE,
+ 0x856B, 0xEAFA, 0x856C, 0xEB57, 0x856D, 0xBFBD, 0x856E, 0xEB4D, 0x8571, 0xEB4B, 0x8575, 0xEB4E, 0x8576, 0xEE53, 0x8577, 0xEE40,
+ 0x8578, 0xEE45, 0x8579, 0xEE52, 0x857A, 0xEE44, 0x857B, 0xEDFB, 0x857C, 0xEE41, 0x857E, 0xC1A2, 0x8580, 0xEDF4, 0x8581, 0xEE4D,
+ 0x8582, 0xEE4F, 0x8583, 0xEDF3, 0x8584, 0xC1A1, 0x8585, 0xEE51, 0x8586, 0xEE49, 0x8587, 0xC1A8, 0x8588, 0xEE50, 0x8589, 0xEE42,
+ 0x858A, 0xC1AA, 0x858B, 0xEDF9, 0x858C, 0xEB52, 0x858D, 0xEE4A, 0x858E, 0xEE47, 0x858F, 0xEDF5, 0x8590, 0xEE55, 0x8591, 0xC1A4,
+ 0x8594, 0xC1A5, 0x8595, 0xEDF7, 0x8596, 0xEE48, 0x8598, 0xEE54, 0x8599, 0xEE4B, 0x859A, 0xEDFD, 0x859B, 0xC1A7, 0x859C, 0xC1A3,
+ 0x859D, 0xEE4C, 0x859E, 0xEDFE, 0x859F, 0xEE56, 0x85A0, 0xEDF8, 0x85A1, 0xEE43, 0x85A2, 0xEE4E, 0x85A3, 0xEDFA, 0x85A4, 0xEDFC,
+ 0x85A6, 0xC2CB, 0x85A7, 0xEDF6, 0x85A8, 0xC1A9, 0x85A9, 0xC2C4, 0x85AA, 0xC17E, 0x85AF, 0xC1A6, 0x85B0, 0xC2C8, 0x85B1, 0xF0B3,
+ 0x85B3, 0xF0A9, 0x85B4, 0xF0A4, 0x85B5, 0xF0AA, 0x85B6, 0xF0B4, 0x85B7, 0xF0B8, 0x85B8, 0xF0B7, 0x85B9, 0xC2CA, 0x85BA, 0xC2C9,
+ 0x85BD, 0xF0AB, 0x85BE, 0xF0B9, 0x85BF, 0xF0AE, 0x85C0, 0xF0A6, 0x85C2, 0xF0A8, 0x85C3, 0xF0A7, 0x85C4, 0xF0AD, 0x85C5, 0xF0B2,
+ 0x85C6, 0xF0A5, 0x85C7, 0xF0AC, 0x85C8, 0xF0B1, 0x85C9, 0xC2C7, 0x85CB, 0xF0AF, 0x85CD, 0xC2C5, 0x85CE, 0xF0B0, 0x85CF, 0xC2C3,
+ 0x85D0, 0xC2C6, 0x85D1, 0xF2D5, 0x85D2, 0xF0B5, 0x85D5, 0xC3C2, 0x85D7, 0xF2CD, 0x85D8, 0xF2D1, 0x85D9, 0xF2C9, 0x85DA, 0xF2CC,
+ 0x85DC, 0xF2D4, 0x85DD, 0xC3C0, 0x85DE, 0xF2D9, 0x85DF, 0xF2D2, 0x85E1, 0xF2CA, 0x85E2, 0xF2DA, 0x85E3, 0xF2D3, 0x85E4, 0xC3C3,
+ 0x85E5, 0xC3C4, 0x85E6, 0xF2D7, 0x85E8, 0xF2CB, 0x85E9, 0xC3BF, 0x85EA, 0xC3C1, 0x85EB, 0xF2C6, 0x85EC, 0xF2CE, 0x85ED, 0xF2C8,
+ 0x85EF, 0xF2D8, 0x85F0, 0xF2D6, 0x85F1, 0xF2C7, 0x85F2, 0xF2CF, 0x85F6, 0xF4BE, 0x85F7, 0xC3C5, 0x85F8, 0xF2D0, 0x85F9, 0xC4A7,
+ 0x85FA, 0xC4A9, 0x85FB, 0xC4A6, 0x85FD, 0xF4C3, 0x85FE, 0xF4BB, 0x85FF, 0xF4B9, 0x8600, 0xF4BD, 0x8601, 0xF4BA, 0x8604, 0xF4BF,
+ 0x8605, 0xF4C1, 0x8606, 0xC4AA, 0x8607, 0xC4AC, 0x8609, 0xF4C0, 0x860A, 0xC4AD, 0x860B, 0xC4AB, 0x860C, 0xF4C2, 0x8611, 0xC4A8,
+ 0x8617, 0xC4F4, 0x8618, 0xF5F1, 0x8619, 0xF5F7, 0x861A, 0xC4F6, 0x861B, 0xF4BC, 0x861C, 0xF5F6, 0x861E, 0xF5FD, 0x861F, 0xF5F4,
+ 0x8620, 0xF5FB, 0x8621, 0xF5FA, 0x8622, 0xF4B8, 0x8623, 0xF5F5, 0x8624, 0xF0B6, 0x8625, 0xF5FE, 0x8626, 0xF5F3, 0x8627, 0xF5F8,
+ 0x8629, 0xF5FC, 0x862A, 0xF5F2, 0x862C, 0xF74A, 0x862D, 0xC4F5, 0x862E, 0xF5F9, 0x8631, 0xF7F4, 0x8632, 0xF74B, 0x8633, 0xF749,
+ 0x8634, 0xF747, 0x8635, 0xF748, 0x8636, 0xF74C, 0x8638, 0xC5D9, 0x8639, 0xF7F2, 0x863A, 0xF7F0, 0x863B, 0xF7F5, 0x863C, 0xF7F3,
+ 0x863E, 0xF7F6, 0x863F, 0xC5DA, 0x8640, 0xF7F1, 0x8643, 0xF8BC, 0x8646, 0xF945, 0x8647, 0xF946, 0x8648, 0xF947, 0x864B, 0xF9C7,
+ 0x864C, 0xF9BD, 0x864D, 0xCA4F, 0x864E, 0xAAEA, 0x8650, 0xAD68, 0x8652, 0xD3B8, 0x8653, 0xD3B7, 0x8654, 0xB040, 0x8655, 0xB342,
+ 0x8656, 0xD77C, 0x8659, 0xD77B, 0x865B, 0xB5EA, 0x865C, 0xB8B8, 0x865E, 0xB8B7, 0x865F, 0xB8B9, 0x8661, 0xE3D4, 0x8662, 0xE77E,
+ 0x8663, 0xEB58, 0x8664, 0xEB5A, 0x8665, 0xEB59, 0x8667, 0xC1AB, 0x8668, 0xEE57, 0x8669, 0xF0BA, 0x866A, 0xF9A5, 0x866B, 0xA6E4,
+ 0x866D, 0xCDC9, 0x866E, 0xCDCA, 0x866F, 0xCDC8, 0x8670, 0xCDC7, 0x8671, 0xAAEB, 0x8673, 0xD0A9, 0x8674, 0xD0A7, 0x8677, 0xD0A6,
+ 0x8679, 0xAD69, 0x867A, 0xAD6B, 0x867B, 0xAD6A, 0x867C, 0xD0A8, 0x8685, 0xD3C4, 0x8686, 0xD3C1, 0x8687, 0xD3BF, 0x868A, 0xB041,
+ 0x868B, 0xD3C2, 0x868C, 0xB046, 0x868D, 0xD3BC, 0x868E, 0xD3CB, 0x8690, 0xD3CD, 0x8691, 0xD3BD, 0x8693, 0xB043, 0x8694, 0xD3CE,
+ 0x8695, 0xD3C9, 0x8696, 0xD3BB, 0x8697, 0xD3C0, 0x8698, 0xD3CA, 0x8699, 0xD3C6, 0x869A, 0xD3C3, 0x869C, 0xB048, 0x869D, 0xD3CC,
+ 0x869E, 0xD3BE, 0x86A1, 0xD3C7, 0x86A2, 0xD3B9, 0x86A3, 0xB047, 0x86A4, 0xB044, 0x86A5, 0xD3C5, 0x86A7, 0xD3C8, 0x86A8, 0xD3BA,
+ 0x86A9, 0xB045, 0x86AA, 0xB042, 0x86AF, 0xB34C, 0x86B0, 0xD7A5, 0x86B1, 0xB34B, 0x86B3, 0xD7A8, 0x86B4, 0xD7AB, 0x86B5, 0xB348,
+ 0x86B6, 0xB346, 0x86B7, 0xD77E, 0x86B8, 0xD7A9, 0x86B9, 0xD7A7, 0x86BA, 0xD7A4, 0x86BB, 0xD7AC, 0x86BC, 0xD7AD, 0x86BD, 0xD7AF,
+ 0x86BE, 0xD7B0, 0x86BF, 0xD77D, 0x86C0, 0xB345, 0x86C1, 0xD7A2, 0x86C2, 0xD7A1, 0x86C3, 0xD7AE, 0x86C4, 0xB347, 0x86C5, 0xD7A3,
+ 0x86C6, 0xB349, 0x86C7, 0xB344, 0x86C8, 0xD7A6, 0x86C9, 0xB34D, 0x86CB, 0xB34A, 0x86CC, 0xD7AA, 0x86D0, 0xB5F1, 0x86D1, 0xDBBF,
+ 0x86D3, 0xDBB4, 0x86D4, 0xB5EE, 0x86D6, 0xDFE7, 0x86D7, 0xDBBD, 0x86D8, 0xDBB1, 0x86D9, 0xB5EC, 0x86DA, 0xDBB6, 0x86DB, 0xB5EF,
+ 0x86DC, 0xDBBA, 0x86DD, 0xDBB8, 0x86DE, 0xB5F2, 0x86DF, 0xB5EB, 0x86E2, 0xDBB2, 0x86E3, 0xDBB5, 0x86E4, 0xB5F0, 0x86E6, 0xDBB3,
+ 0x86E8, 0xDBBE, 0x86E9, 0xDBBC, 0x86EA, 0xDBB7, 0x86EB, 0xDBB9, 0x86EC, 0xDBBB, 0x86ED, 0xB5ED, 0x86F5, 0xDFE8, 0x86F6, 0xDFEE,
+ 0x86F7, 0xDFE4, 0x86F8, 0xDFEA, 0x86F9, 0xB8BA, 0x86FA, 0xDFE6, 0x86FB, 0xB8C0, 0x86FE, 0xB8BF, 0x8700, 0xB8BE, 0x8701, 0xDFED,
+ 0x8702, 0xB8C1, 0x8703, 0xB8C2, 0x8704, 0xDFE3, 0x8705, 0xDFF0, 0x8706, 0xB8C3, 0x8707, 0xB8BD, 0x8708, 0xB8BC, 0x8709, 0xDFEC,
+ 0x870A, 0xB8C4, 0x870B, 0xDFE2, 0x870C, 0xDFE5, 0x870D, 0xDFEF, 0x870E, 0xDFEB, 0x8711, 0xE3F4, 0x8712, 0xE3E9, 0x8713, 0xB8BB,
+ 0x8718, 0xBB6A, 0x8719, 0xE3DD, 0x871A, 0xE3F2, 0x871B, 0xE3DE, 0x871C, 0xBB65, 0x871E, 0xE3DB, 0x8720, 0xE3E4, 0x8721, 0xE3DC,
+ 0x8722, 0xBB67, 0x8723, 0xE3D6, 0x8724, 0xE3F1, 0x8725, 0xBB68, 0x8726, 0xE3EE, 0x8727, 0xE3EF, 0x8728, 0xE3D7, 0x8729, 0xBB6D,
+ 0x872A, 0xE3E6, 0x872C, 0xE3E0, 0x872D, 0xE3E7, 0x872E, 0xE3DA, 0x8730, 0xE3F3, 0x8731, 0xE3EB, 0x8732, 0xE3E5, 0x8733, 0xE3D5,
+ 0x8734, 0xBB69, 0x8735, 0xE3EC, 0x8737, 0xBB6C, 0x8738, 0xE3F0, 0x873A, 0xE3EA, 0x873B, 0xBB66, 0x873C, 0xE3E8, 0x873E, 0xE3E2,
+ 0x873F, 0xBB64, 0x8740, 0xE3D9, 0x8741, 0xE3E1, 0x8742, 0xE3ED, 0x8743, 0xE3DF, 0x8746, 0xE3E3, 0x874C, 0xBDC1, 0x874D, 0xDFE9,
+ 0x874E, 0xE7B2, 0x874F, 0xE7BB, 0x8750, 0xE7B1, 0x8751, 0xE7AD, 0x8752, 0xE7AA, 0x8753, 0xBDC2, 0x8754, 0xE7A8, 0x8755, 0xBB6B,
+ 0x8756, 0xE7A1, 0x8757, 0xBDC0, 0x8758, 0xE7A7, 0x8759, 0xBDBF, 0x875A, 0xE7AC, 0x875B, 0xE7A9, 0x875C, 0xE7B9, 0x875D, 0xE7B4,
+ 0x875E, 0xE7AE, 0x875F, 0xE7B3, 0x8760, 0xBDBB, 0x8761, 0xE7AB, 0x8762, 0xE7BE, 0x8763, 0xE7A2, 0x8764, 0xE7A3, 0x8765, 0xE7BA,
+ 0x8766, 0xBDBC, 0x8767, 0xE7BF, 0x8768, 0xBDBE, 0x8769, 0xE7C0, 0x876A, 0xE7B0, 0x876B, 0xE3D8, 0x876C, 0xE7B6, 0x876D, 0xE7AF,
+ 0x876E, 0xE7B8, 0x876F, 0xE7B5, 0x8773, 0xE7A6, 0x8774, 0xBDB9, 0x8775, 0xE7BD, 0x8776, 0xBDBA, 0x8777, 0xE7A4, 0x8778, 0xBDBD,
+ 0x8779, 0xEB64, 0x877A, 0xE7B7, 0x877B, 0xE7BC, 0x8781, 0xEB61, 0x8782, 0xBDB8, 0x8783, 0xBFC0, 0x8784, 0xEB6B, 0x8785, 0xEB67,
+ 0x8787, 0xEB65, 0x8788, 0xEB60, 0x8789, 0xEB6F, 0x878D, 0xBFC4, 0x878F, 0xEB5C, 0x8790, 0xEB68, 0x8791, 0xEB69, 0x8792, 0xEB5F,
+ 0x8793, 0xEB5E, 0x8794, 0xEB6C, 0x8796, 0xEB62, 0x8797, 0xEB5D, 0x8798, 0xEB63, 0x879A, 0xEB6E, 0x879B, 0xEB5B, 0x879C, 0xEB6D,
+ 0x879D, 0xEB6A, 0x879E, 0xBFC2, 0x879F, 0xBFC1, 0x87A2, 0xBFC3, 0x87A3, 0xEB66, 0x87A4, 0xF0CB, 0x87AA, 0xEE59, 0x87AB, 0xC1B1,
+ 0x87AC, 0xEE5D, 0x87AD, 0xEE5A, 0x87AE, 0xEE61, 0x87AF, 0xEE67, 0x87B0, 0xEE5C, 0x87B2, 0xEE70, 0x87B3, 0xC1AE, 0x87B4, 0xEE6A,
+ 0x87B5, 0xEE5F, 0x87B6, 0xEE6B, 0x87B7, 0xEE66, 0x87B8, 0xEE6D, 0x87B9, 0xEE5E, 0x87BA, 0xC1B3, 0x87BB, 0xC1B2, 0x87BC, 0xEE60,
+ 0x87BD, 0xEE6E, 0x87BE, 0xEE58, 0x87BF, 0xEE6C, 0x87C0, 0xC1AC, 0x87C2, 0xEE64, 0x87C3, 0xEE63, 0x87C4, 0xEE68, 0x87C5, 0xEE5B,
+ 0x87C6, 0xC1B0, 0x87C8, 0xC1B4, 0x87C9, 0xEE62, 0x87CA, 0xEE69, 0x87CB, 0xC1B5, 0x87CC, 0xEE65, 0x87D1, 0xC1AD, 0x87D2, 0xC1AF,
+ 0x87D3, 0xF0C7, 0x87D4, 0xF0C5, 0x87D7, 0xF0CC, 0x87D8, 0xF0C9, 0x87D9, 0xF0CD, 0x87DB, 0xF0BE, 0x87DC, 0xF0C6, 0x87DD, 0xF0D1,
+ 0x87DE, 0xEE6F, 0x87DF, 0xF0C2, 0x87E0, 0xC2CF, 0x87E1, 0xE7A5, 0x87E2, 0xF0BD, 0x87E3, 0xF0CA, 0x87E4, 0xF0C4, 0x87E5, 0xF0C1,
+ 0x87E6, 0xF0BC, 0x87E7, 0xF0BB, 0x87E8, 0xF0D0, 0x87EA, 0xF0C0, 0x87EB, 0xF0BF, 0x87EC, 0xC2CD, 0x87ED, 0xF0C8, 0x87EF, 0xC2CC,
+ 0x87F2, 0xC2CE, 0x87F3, 0xF0C3, 0x87F4, 0xF0CF, 0x87F6, 0xF2DE, 0x87F7, 0xF2DF, 0x87F9, 0xC3C9, 0x87FA, 0xF2DC, 0x87FB, 0xC3C6,
+ 0x87FC, 0xF2E4, 0x87FE, 0xC3CA, 0x87FF, 0xF2E6, 0x8800, 0xF2DB, 0x8801, 0xF0CE, 0x8802, 0xF2E8, 0x8803, 0xF2DD, 0x8805, 0xC3C7,
+ 0x8806, 0xF2E3, 0x8808, 0xF2E5, 0x8809, 0xF2E0, 0x880A, 0xF2E7, 0x880B, 0xF2E2, 0x880C, 0xF2E1, 0x880D, 0xC3C8, 0x8810, 0xF4C5,
+ 0x8811, 0xF4C6, 0x8813, 0xF4C8, 0x8814, 0xC4AE, 0x8815, 0xC4AF, 0x8816, 0xF4C9, 0x8817, 0xF4C7, 0x8819, 0xF4C4, 0x881B, 0xF642,
+ 0x881C, 0xF645, 0x881D, 0xF641, 0x881F, 0xC4FA, 0x8820, 0xF643, 0x8821, 0xC4F9, 0x8822, 0xC4F8, 0x8823, 0xC4F7, 0x8824, 0xF644,
+ 0x8825, 0xF751, 0x8826, 0xF74F, 0x8828, 0xF74E, 0x8829, 0xF640, 0x882A, 0xF750, 0x882B, 0xF646, 0x882C, 0xF74D, 0x882E, 0xF7F9,
+ 0x882F, 0xF7D7, 0x8830, 0xF7F7, 0x8831, 0xC5DB, 0x8832, 0xF7F8, 0x8833, 0xF7FA, 0x8835, 0xF8BF, 0x8836, 0xC5FA, 0x8837, 0xF8BE,
+ 0x8838, 0xF8BD, 0x8839, 0xC5FB, 0x883B, 0xC65A, 0x883C, 0xF96E, 0x883D, 0xF9A7, 0x883E, 0xF9A6, 0x883F, 0xF9A8, 0x8840, 0xA6E5,
+ 0x8841, 0xD0AA, 0x8843, 0xD3CF, 0x8844, 0xD3D0, 0x8848, 0xDBC0, 0x884A, 0xF647, 0x884B, 0xF8C0, 0x884C, 0xA6E6, 0x884D, 0xAD6C,
+ 0x884E, 0xD0AB, 0x8852, 0xD7B1, 0x8853, 0xB34E, 0x8855, 0xDBC2, 0x8856, 0xDBC1, 0x8857, 0xB5F3, 0x8859, 0xB8C5, 0x885A, 0xE7C1,
+ 0x885B, 0xBDC3, 0x885D, 0xBDC4, 0x8861, 0xBFC5, 0x8862, 0xC5FC, 0x8863, 0xA6E7, 0x8867, 0xD0AC, 0x8868, 0xAAED, 0x8869, 0xD0AE,
+ 0x886A, 0xD0AD, 0x886B, 0xAD6D, 0x886D, 0xD3D1, 0x886F, 0xD3D8, 0x8870, 0xB049, 0x8871, 0xD3D6, 0x8872, 0xD3D4, 0x8874, 0xD3DB,
+ 0x8875, 0xD3D2, 0x8876, 0xD3D3, 0x8877, 0xB04A, 0x8879, 0xB04E, 0x887C, 0xD3DC, 0x887D, 0xB04D, 0x887E, 0xD3DA, 0x887F, 0xD3D7,
+ 0x8880, 0xD3D5, 0x8881, 0xB04B, 0x8882, 0xB04C, 0x8883, 0xD3D9, 0x8888, 0xB350, 0x8889, 0xD7B2, 0x888B, 0xB355, 0x888C, 0xD7C2,
+ 0x888D, 0xB354, 0x888E, 0xD7C4, 0x8891, 0xD7B8, 0x8892, 0xB352, 0x8893, 0xD7C3, 0x8895, 0xD7B3, 0x8896, 0xB353, 0x8897, 0xD7BF,
+ 0x8898, 0xD7BB, 0x8899, 0xD7BD, 0x889A, 0xD7B7, 0x889B, 0xD7BE, 0x889E, 0xB34F, 0x889F, 0xD7BA, 0x88A1, 0xD7B9, 0x88A2, 0xD7B5,
+ 0x88A4, 0xD7C0, 0x88A7, 0xD7BC, 0x88A8, 0xD7B4, 0x88AA, 0xD7B6, 0x88AB, 0xB351, 0x88AC, 0xD7C1, 0x88B1, 0xB5F6, 0x88B2, 0xDBCD,
+ 0x88B6, 0xDBC9, 0x88B7, 0xDBCB, 0x88B8, 0xDBC6, 0x88B9, 0xDBC5, 0x88BA, 0xDBC3, 0x88BC, 0xDBCA, 0x88BD, 0xDBCC, 0x88BE, 0xDBC8,
+ 0x88C0, 0xDBC7, 0x88C1, 0xB5F4, 0x88C2, 0xB5F5, 0x88C9, 0xDBCF, 0x88CA, 0xB8CD, 0x88CB, 0xDFF2, 0x88CC, 0xDFF8, 0x88CD, 0xDFF3,
+ 0x88CE, 0xDFF4, 0x88CF, 0xF9D8, 0x88D0, 0xDFF9, 0x88D2, 0xB8CF, 0x88D4, 0xB8C7, 0x88D5, 0xB8CE, 0x88D6, 0xDFF1, 0x88D7, 0xDBC4,
+ 0x88D8, 0xB8CA, 0x88D9, 0xB8C8, 0x88DA, 0xDFF7, 0x88DB, 0xDFF6, 0x88DC, 0xB8C9, 0x88DD, 0xB8CB, 0x88DE, 0xDFF5, 0x88DF, 0xB8C6,
+ 0x88E1, 0xB8CC, 0x88E7, 0xE3F6, 0x88E8, 0xBB74, 0x88EB, 0xE442, 0x88EC, 0xE441, 0x88EE, 0xE3FB, 0x88EF, 0xBB76, 0x88F0, 0xE440,
+ 0x88F1, 0xE3F7, 0x88F2, 0xE3F8, 0x88F3, 0xBB6E, 0x88F4, 0xBB70, 0x88F6, 0xE3FD, 0x88F7, 0xE3F5, 0x88F8, 0xBB72, 0x88F9, 0xBB71,
+ 0x88FA, 0xE3F9, 0x88FB, 0xE3FE, 0x88FC, 0xE3FC, 0x88FD, 0xBB73, 0x88FE, 0xE3FA, 0x8901, 0xDBCE, 0x8902, 0xBB6F, 0x8905, 0xE7C2,
+ 0x8906, 0xE7C9, 0x8907, 0xBDC6, 0x8909, 0xE7CD, 0x890A, 0xBDCA, 0x890B, 0xE7C5, 0x890C, 0xE7C3, 0x890E, 0xE7CC, 0x8910, 0xBDC5,
+ 0x8911, 0xE7CB, 0x8912, 0xBDC7, 0x8913, 0xBDC8, 0x8914, 0xE7C4, 0x8915, 0xBDC9, 0x8916, 0xE7CA, 0x8917, 0xE7C6, 0x8918, 0xE7C7,
+ 0x8919, 0xE7C8, 0x891A, 0xBB75, 0x891E, 0xEB70, 0x891F, 0xEB7C, 0x8921, 0xBFCA, 0x8922, 0xEB77, 0x8923, 0xEB79, 0x8925, 0xBFC8,
+ 0x8926, 0xEB71, 0x8927, 0xEB75, 0x8929, 0xEB78, 0x892A, 0xBFC6, 0x892B, 0xBFC9, 0x892C, 0xEB7B, 0x892D, 0xEB73, 0x892E, 0xEB74,
+ 0x892F, 0xEB7A, 0x8930, 0xEB72, 0x8931, 0xEB76, 0x8932, 0xBFC7, 0x8933, 0xEE72, 0x8935, 0xEE71, 0x8936, 0xC1B7, 0x8937, 0xEE77,
+ 0x8938, 0xC1B9, 0x893B, 0xC1B6, 0x893C, 0xEE73, 0x893D, 0xC1BA, 0x893E, 0xEE74, 0x8941, 0xEE75, 0x8942, 0xEE78, 0x8944, 0xC1B8,
+ 0x8946, 0xF0D6, 0x8949, 0xF0D9, 0x894B, 0xF0D3, 0x894C, 0xF0D5, 0x894F, 0xF0D4, 0x8950, 0xF0D7, 0x8951, 0xF0D8, 0x8952, 0xEE76,
+ 0x8953, 0xF0D2, 0x8956, 0xC3CD, 0x8957, 0xF2EC, 0x8958, 0xF2EF, 0x8959, 0xF2F1, 0x895A, 0xF2EA, 0x895B, 0xF2EB, 0x895C, 0xF2EE,
+ 0x895D, 0xF2F0, 0x895E, 0xC3CE, 0x895F, 0xC3CC, 0x8960, 0xC3CB, 0x8961, 0xF2ED, 0x8962, 0xF2E9, 0x8963, 0xF4CA, 0x8964, 0xC4B0,
+ 0x8966, 0xF4CB, 0x8969, 0xF649, 0x896A, 0xC4FB, 0x896B, 0xF64B, 0x896C, 0xC4FC, 0x896D, 0xF648, 0x896E, 0xF64A, 0x896F, 0xC5A8,
+ 0x8971, 0xF752, 0x8972, 0xC5A7, 0x8973, 0xF7FD, 0x8974, 0xF7FC, 0x8976, 0xF7FB, 0x8979, 0xF948, 0x897A, 0xF949, 0x897B, 0xF94B,
+ 0x897C, 0xF94A, 0x897E, 0xCA50, 0x897F, 0xA6E8, 0x8981, 0xAD6E, 0x8982, 0xD7C5, 0x8983, 0xB5F7, 0x8985, 0xDFFA, 0x8986, 0xC2D0,
+ 0x8988, 0xF2F2, 0x898B, 0xA8A3, 0x898F, 0xB357, 0x8993, 0xB356, 0x8995, 0xDBD0, 0x8996, 0xB5F8, 0x8997, 0xDBD2, 0x8998, 0xDBD1,
+ 0x899B, 0xDFFB, 0x899C, 0xB8D0, 0x899D, 0xE443, 0x899E, 0xE446, 0x899F, 0xE445, 0x89A1, 0xE444, 0x89A2, 0xE7CE, 0x89A3, 0xE7D0,
+ 0x89A4, 0xE7CF, 0x89A6, 0xBFCC, 0x89AA, 0xBFCB, 0x89AC, 0xC1BB, 0x89AD, 0xEE79, 0x89AE, 0xEE7B, 0x89AF, 0xEE7A, 0x89B2, 0xC2D1,
+ 0x89B6, 0xF2F4, 0x89B7, 0xF2F3, 0x89B9, 0xF4CC, 0x89BA, 0xC4B1, 0x89BD, 0xC4FD, 0x89BE, 0xF754, 0x89BF, 0xF753, 0x89C0, 0xC65B,
+ 0x89D2, 0xA8A4, 0x89D3, 0xD0AF, 0x89D4, 0xAD6F, 0x89D5, 0xD7C8, 0x89D6, 0xD7C6, 0x89D9, 0xD7C7, 0x89DA, 0xDBD4, 0x89DB, 0xDBD5,
+ 0x89DC, 0xE043, 0x89DD, 0xDBD3, 0x89DF, 0xDFFC, 0x89E0, 0xE041, 0x89E1, 0xE040, 0x89E2, 0xE042, 0x89E3, 0xB8D1, 0x89E4, 0xDFFE,
+ 0x89E5, 0xDFFD, 0x89E6, 0xE044, 0x89E8, 0xE449, 0x89E9, 0xE447, 0x89EB, 0xE448, 0x89EC, 0xE7D3, 0x89ED, 0xE7D1, 0x89F0, 0xE7D2,
+ 0x89F1, 0xEB7D, 0x89F2, 0xEE7C, 0x89F3, 0xEE7D, 0x89F4, 0xC2D2, 0x89F6, 0xF2F5, 0x89F7, 0xF4CD, 0x89F8, 0xC4B2, 0x89FA, 0xF64C,
+ 0x89FB, 0xF755, 0x89FC, 0xC5A9, 0x89FE, 0xF7FE, 0x89FF, 0xF94C, 0x8A00, 0xA8A5, 0x8A02, 0xAD71, 0x8A03, 0xAD72, 0x8A04, 0xD0B0,
+ 0x8A07, 0xD0B1, 0x8A08, 0xAD70, 0x8A0A, 0xB054, 0x8A0C, 0xB052, 0x8A0E, 0xB051, 0x8A0F, 0xB058, 0x8A10, 0xB050, 0x8A11, 0xB059,
+ 0x8A12, 0xD3DD, 0x8A13, 0xB056, 0x8A15, 0xB053, 0x8A16, 0xB057, 0x8A17, 0xB055, 0x8A18, 0xB04F, 0x8A1B, 0xB35F, 0x8A1D, 0xB359,
+ 0x8A1E, 0xD7CC, 0x8A1F, 0xB35E, 0x8A22, 0xB360, 0x8A23, 0xB35A, 0x8A25, 0xB35B, 0x8A27, 0xD7CA, 0x8A2A, 0xB358, 0x8A2C, 0xD7CB,
+ 0x8A2D, 0xB35D, 0x8A30, 0xD7C9, 0x8A31, 0xB35C, 0x8A34, 0xB644, 0x8A36, 0xB646, 0x8A39, 0xDBD8, 0x8A3A, 0xB645, 0x8A3B, 0xB5F9,
+ 0x8A3C, 0xB5FD, 0x8A3E, 0xB8E4, 0x8A3F, 0xE049, 0x8A40, 0xDBDA, 0x8A41, 0xB5FE, 0x8A44, 0xDBDD, 0x8A45, 0xDBDE, 0x8A46, 0xB643,
+ 0x8A48, 0xDBE0, 0x8A4A, 0xDBE2, 0x8A4C, 0xDBE3, 0x8A4D, 0xDBD7, 0x8A4E, 0xDBD6, 0x8A4F, 0xDBE4, 0x8A50, 0xB642, 0x8A51, 0xDBE1,
+ 0x8A52, 0xDBDF, 0x8A54, 0xB640, 0x8A55, 0xB5FB, 0x8A56, 0xB647, 0x8A57, 0xDBDB, 0x8A58, 0xDBDC, 0x8A59, 0xDBD9, 0x8A5B, 0xB641,
+ 0x8A5E, 0xB5FC, 0x8A60, 0xB5FA, 0x8A61, 0xE048, 0x8A62, 0xB8DF, 0x8A63, 0xB8DA, 0x8A66, 0xB8D5, 0x8A68, 0xB8E5, 0x8A69, 0xB8D6,
+ 0x8A6B, 0xB8D2, 0x8A6C, 0xB8E1, 0x8A6D, 0xB8DE, 0x8A6E, 0xB8E0, 0x8A70, 0xB8D7, 0x8A71, 0xB8DC, 0x8A72, 0xB8D3, 0x8A73, 0xB8D4,
+ 0x8A74, 0xE050, 0x8A75, 0xE04D, 0x8A76, 0xE045, 0x8A77, 0xE04A, 0x8A79, 0xB8E2, 0x8A7A, 0xE051, 0x8A7B, 0xB8E3, 0x8A7C, 0xB8D9,
+ 0x8A7F, 0xE047, 0x8A81, 0xE04F, 0x8A82, 0xE04B, 0x8A83, 0xE04E, 0x8A84, 0xE04C, 0x8A85, 0xB8DD, 0x8A86, 0xE046, 0x8A87, 0xB8D8,
+ 0x8A8B, 0xE44C, 0x8A8C, 0xBB78, 0x8A8D, 0xBB7B, 0x8A8F, 0xE44E, 0x8A91, 0xBBA5, 0x8A92, 0xE44D, 0x8A93, 0xBB7D, 0x8A95, 0xBDCF,
+ 0x8A96, 0xE44F, 0x8A98, 0xBBA4, 0x8A99, 0xE44B, 0x8A9A, 0xBBA6, 0x8A9E, 0xBB79, 0x8AA0, 0xB8DB, 0x8AA1, 0xBB7C, 0x8AA3, 0xBB7A,
+ 0x8AA4, 0xBB7E, 0x8AA5, 0xBBA2, 0x8AA6, 0xBB77, 0x8AA7, 0xBBA7, 0x8AA8, 0xBBA3, 0x8AAA, 0xBBA1, 0x8AAB, 0xE44A, 0x8AB0, 0xBDD6,
+ 0x8AB2, 0xBDD2, 0x8AB6, 0xBDD9, 0x8AB8, 0xE7D6, 0x8AB9, 0xBDDA, 0x8ABA, 0xE7E2, 0x8ABB, 0xE7DB, 0x8ABC, 0xBDCB, 0x8ABD, 0xE7E3,
+ 0x8ABE, 0xE7DD, 0x8ABF, 0xBDD5, 0x8AC0, 0xE7DE, 0x8AC2, 0xBDD4, 0x8AC3, 0xE7E1, 0x8AC4, 0xBDCE, 0x8AC5, 0xE7DF, 0x8AC6, 0xE7D5,
+ 0x8AC7, 0xBDCD, 0x8AC8, 0xEBAA, 0x8AC9, 0xBDD3, 0x8ACB, 0xBDD0, 0x8ACD, 0xBDD8, 0x8ACF, 0xE7D4, 0x8AD1, 0xE7D8, 0x8AD2, 0xBDCC,
+ 0x8AD3, 0xE7D7, 0x8AD4, 0xE7D9, 0x8AD5, 0xE7DA, 0x8AD6, 0xBDD7, 0x8AD7, 0xE7DC, 0x8AD8, 0xE7E0, 0x8AD9, 0xE7E4, 0x8ADB, 0xBDDB,
+ 0x8ADC, 0xBFD2, 0x8ADD, 0xEBA5, 0x8ADE, 0xEBAB, 0x8ADF, 0xEBA8, 0x8AE0, 0xEB7E, 0x8AE1, 0xEBAC, 0x8AE2, 0xEBA1, 0x8AE4, 0xEBA7,
+ 0x8AE6, 0xBFCD, 0x8AE7, 0xBFD3, 0x8AE8, 0xEBAD, 0x8AEB, 0xBFCF, 0x8AED, 0xBFD9, 0x8AEE, 0xBFD4, 0x8AEF, 0xEBAF, 0x8AF0, 0xEBA9,
+ 0x8AF1, 0xBFD0, 0x8AF2, 0xEBA2, 0x8AF3, 0xBFDA, 0x8AF4, 0xEBA3, 0x8AF5, 0xEBA4, 0x8AF6, 0xBFDB, 0x8AF7, 0xBFD8, 0x8AF8, 0xBDD1,
+ 0x8AFA, 0xBFCE, 0x8AFB, 0xEBB0, 0x8AFC, 0xBFDC, 0x8AFE, 0xBFD5, 0x8AFF, 0xEBAE, 0x8B00, 0xBFD1, 0x8B01, 0xBFD6, 0x8B02, 0xBFD7,
+ 0x8B04, 0xC1C3, 0x8B05, 0xEEA4, 0x8B06, 0xEEAD, 0x8B07, 0xEEAA, 0x8B08, 0xEEAC, 0x8B0A, 0xC1C0, 0x8B0B, 0xEEA5, 0x8B0D, 0xEEAB,
+ 0x8B0E, 0xC1BC, 0x8B0F, 0xEEA7, 0x8B10, 0xC1C4, 0x8B11, 0xEEA3, 0x8B12, 0xEEA8, 0x8B13, 0xEEAF, 0x8B14, 0xEBA6, 0x8B15, 0xEEA9,
+ 0x8B16, 0xEEA2, 0x8B17, 0xC1BD, 0x8B18, 0xEEA1, 0x8B19, 0xC1BE, 0x8B1A, 0xEEB0, 0x8B1B, 0xC1BF, 0x8B1C, 0xEEAE, 0x8B1D, 0xC1C2,
+ 0x8B1E, 0xEE7E, 0x8B20, 0xC1C1, 0x8B22, 0xEEA6, 0x8B23, 0xF0DC, 0x8B24, 0xF0EA, 0x8B25, 0xF0E5, 0x8B26, 0xF0E7, 0x8B27, 0xF0DB,
+ 0x8B28, 0xC2D3, 0x8B2A, 0xF0DA, 0x8B2B, 0xC2D6, 0x8B2C, 0xC2D5, 0x8B2E, 0xF0E9, 0x8B2F, 0xF0E1, 0x8B30, 0xF0DE, 0x8B31, 0xF0E4,
+ 0x8B33, 0xF0DD, 0x8B35, 0xF0DF, 0x8B36, 0xF0E8, 0x8B37, 0xF0E6, 0x8B39, 0xC2D4, 0x8B3A, 0xF0ED, 0x8B3B, 0xF0EB, 0x8B3C, 0xF0E2,
+ 0x8B3D, 0xF0EC, 0x8B3E, 0xF0E3, 0x8B40, 0xF2F9, 0x8B41, 0xC3CF, 0x8B42, 0xF341, 0x8B45, 0xF64F, 0x8B46, 0xC3D6, 0x8B47, 0xF0E0,
+ 0x8B48, 0xF2F7, 0x8B49, 0xC3D2, 0x8B4A, 0xF2F8, 0x8B4B, 0xF2FD, 0x8B4E, 0xC3D4, 0x8B4F, 0xC3D5, 0x8B50, 0xF2F6, 0x8B51, 0xF340,
+ 0x8B52, 0xF342, 0x8B53, 0xF2FA, 0x8B54, 0xF2FC, 0x8B55, 0xF2FE, 0x8B56, 0xF2FB, 0x8B57, 0xF343, 0x8B58, 0xC3D1, 0x8B59, 0xC3D7,
+ 0x8B5A, 0xC3D3, 0x8B5C, 0xC3D0, 0x8B5D, 0xF4D0, 0x8B5F, 0xC4B7, 0x8B60, 0xF4CE, 0x8B63, 0xF4D2, 0x8B65, 0xF4D3, 0x8B66, 0xC4B5,
+ 0x8B67, 0xF4D4, 0x8B68, 0xF4D1, 0x8B6A, 0xF4CF, 0x8B6B, 0xC4B8, 0x8B6C, 0xC4B4, 0x8B6D, 0xF4D5, 0x8B6F, 0xC4B6, 0x8B70, 0xC4B3,
+ 0x8B74, 0xC4FE, 0x8B77, 0xC540, 0x8B78, 0xF64E, 0x8B79, 0xF64D, 0x8B7A, 0xF650, 0x8B7B, 0xF651, 0x8B7D, 0xC541, 0x8B7E, 0xF756,
+ 0x8B7F, 0xF75B, 0x8B80, 0xC5AA, 0x8B82, 0xF758, 0x8B84, 0xF757, 0x8B85, 0xF75A, 0x8B86, 0xF759, 0x8B88, 0xF843, 0x8B8A, 0xC5DC,
+ 0x8B8B, 0xF842, 0x8B8C, 0xF840, 0x8B8E, 0xF841, 0x8B92, 0xC5FE, 0x8B93, 0xC5FD, 0x8B94, 0xF8C1, 0x8B95, 0xF8C2, 0x8B96, 0xC640,
+ 0x8B98, 0xF94D, 0x8B99, 0xF94E, 0x8B9A, 0xC667, 0x8B9C, 0xC66D, 0x8B9E, 0xF9A9, 0x8B9F, 0xF9C8, 0x8C37, 0xA8A6, 0x8C39, 0xD7CD,
+ 0x8C3B, 0xD7CE, 0x8C3C, 0xE052, 0x8C3D, 0xE450, 0x8C3E, 0xE7E5, 0x8C3F, 0xC1C6, 0x8C41, 0xC1C5, 0x8C42, 0xF0EE, 0x8C43, 0xF344,
+ 0x8C45, 0xF844, 0x8C46, 0xA8A7, 0x8C47, 0xD3DE, 0x8C48, 0xB05A, 0x8C49, 0xB361, 0x8C4A, 0xE054, 0x8C4B, 0xE053, 0x8C4C, 0xBDDC,
+ 0x8C4D, 0xE7E6, 0x8C4E, 0xBDDD, 0x8C4F, 0xEEB1, 0x8C50, 0xC2D7, 0x8C54, 0xC676, 0x8C55, 0xA8A8, 0x8C56, 0xCDCB, 0x8C57, 0xD3DF,
+ 0x8C5A, 0xB362, 0x8C5C, 0xD7CF, 0x8C5D, 0xD7D0, 0x8C5F, 0xDBE5, 0x8C61, 0xB648, 0x8C62, 0xB8E6, 0x8C64, 0xE056, 0x8C65, 0xE055,
+ 0x8C66, 0xE057, 0x8C68, 0xE451, 0x8C69, 0xE452, 0x8C6A, 0xBBA8, 0x8C6B, 0xBFDD, 0x8C6C, 0xBDDE, 0x8C6D, 0xBFDE, 0x8C6F, 0xEEB5,
+ 0x8C70, 0xEEB2, 0x8C71, 0xEEB4, 0x8C72, 0xEEB3, 0x8C73, 0xC1C7, 0x8C75, 0xF0EF, 0x8C76, 0xF346, 0x8C77, 0xF345, 0x8C78, 0xCBA4,
+ 0x8C79, 0xB05C, 0x8C7A, 0xB05B, 0x8C7B, 0xD3E0, 0x8C7D, 0xD7D1, 0x8C80, 0xDBE7, 0x8C81, 0xDBE6, 0x8C82, 0xB649, 0x8C84, 0xE059,
+ 0x8C85, 0xE05A, 0x8C86, 0xE058, 0x8C89, 0xB8E8, 0x8C8A, 0xB8E7, 0x8C8C, 0xBBAA, 0x8C8D, 0xBBA9, 0x8C8F, 0xE7E7, 0x8C90, 0xEBB3,
+ 0x8C91, 0xEBB1, 0x8C92, 0xEBB2, 0x8C93, 0xBFDF, 0x8C94, 0xEEB7, 0x8C95, 0xEEB6, 0x8C97, 0xF0F2, 0x8C98, 0xF0F1, 0x8C99, 0xF0F0,
+ 0x8C9A, 0xF347, 0x8C9C, 0xF9AA, 0x8C9D, 0xA8A9, 0x8C9E, 0xAD73, 0x8CA0, 0xAD74, 0x8CA1, 0xB05D, 0x8CA2, 0xB05E, 0x8CA3, 0xD3E2,
+ 0x8CA4, 0xD3E1, 0x8CA5, 0xD7D2, 0x8CA7, 0xB368, 0x8CA8, 0xB366, 0x8CA9, 0xB363, 0x8CAA, 0xB367, 0x8CAB, 0xB365, 0x8CAC, 0xB364,
+ 0x8CAF, 0xB64A, 0x8CB0, 0xDBEA, 0x8CB2, 0xB8ED, 0x8CB3, 0xB64C, 0x8CB4, 0xB651, 0x8CB5, 0xDBEC, 0x8CB6, 0xB653, 0x8CB7, 0xB652,
+ 0x8CB8, 0xB655, 0x8CB9, 0xDBEB, 0x8CBA, 0xDBE8, 0x8CBB, 0xB64F, 0x8CBC, 0xB64B, 0x8CBD, 0xB64D, 0x8CBE, 0xDBE9, 0x8CBF, 0xB654,
+ 0x8CC0, 0xB650, 0x8CC1, 0xB64E, 0x8CC2, 0xB8EF, 0x8CC3, 0xB8EE, 0x8CC4, 0xB8EC, 0x8CC5, 0xB8F0, 0x8CC7, 0xB8EA, 0x8CC8, 0xB8EB,
+ 0x8CCA, 0xB8E9, 0x8CCC, 0xE05B, 0x8CCF, 0xE454, 0x8CD1, 0xBBAC, 0x8CD2, 0xBBAD, 0x8CD3, 0xBBAB, 0x8CD5, 0xE453, 0x8CD7, 0xE455,
+ 0x8CD9, 0xE7EA, 0x8CDA, 0xE7EC, 0x8CDC, 0xBDE7, 0x8CDD, 0xE7ED, 0x8CDE, 0xBDE0, 0x8CDF, 0xE7E9, 0x8CE0, 0xBDDF, 0x8CE1, 0xBDE9,
+ 0x8CE2, 0xBDE5, 0x8CE3, 0xBDE6, 0x8CE4, 0xBDE2, 0x8CE5, 0xE7E8, 0x8CE6, 0xBDE1, 0x8CE7, 0xE7EE, 0x8CE8, 0xE7EB, 0x8CEA, 0xBDE8,
+ 0x8CEC, 0xBDE3, 0x8CED, 0xBDE4, 0x8CEE, 0xEBB5, 0x8CF0, 0xEBB7, 0x8CF1, 0xEBB6, 0x8CF3, 0xEBB8, 0x8CF4, 0xBFE0, 0x8CF5, 0xEBB4,
+ 0x8CF8, 0xC1CB, 0x8CF9, 0xEEB8, 0x8CFA, 0xC1C8, 0x8CFB, 0xC1CC, 0x8CFC, 0xC1CA, 0x8CFD, 0xC1C9, 0x8CFE, 0xF0F3, 0x8D00, 0xF0F6,
+ 0x8D02, 0xF0F5, 0x8D04, 0xF0F4, 0x8D05, 0xC2D8, 0x8D06, 0xF348, 0x8D07, 0xF349, 0x8D08, 0xC3D8, 0x8D09, 0xF34A, 0x8D0A, 0xC3D9,
+ 0x8D0D, 0xC4BA, 0x8D0F, 0xC4B9, 0x8D10, 0xF652, 0x8D13, 0xC542, 0x8D14, 0xF653, 0x8D15, 0xF75C, 0x8D16, 0xC5AB, 0x8D17, 0xC5AC,
+ 0x8D19, 0xF845, 0x8D1B, 0xC642, 0x8D64, 0xA8AA, 0x8D66, 0xB36A, 0x8D67, 0xB369, 0x8D68, 0xE05C, 0x8D69, 0xE05D, 0x8D6B, 0xBBAE,
+ 0x8D6C, 0xEBB9, 0x8D6D, 0xBDEA, 0x8D6E, 0xEBBA, 0x8D6F, 0xEEB9, 0x8D70, 0xA8AB, 0x8D72, 0xD0B2, 0x8D73, 0xAD76, 0x8D74, 0xAD75,
+ 0x8D76, 0xD3E3, 0x8D77, 0xB05F, 0x8D78, 0xD3E4, 0x8D79, 0xD7D5, 0x8D7B, 0xD7D4, 0x8D7D, 0xD7D3, 0x8D80, 0xDBEE, 0x8D81, 0xB658,
+ 0x8D84, 0xDBED, 0x8D85, 0xB657, 0x8D89, 0xDBEF, 0x8D8A, 0xB656, 0x8D8C, 0xE05F, 0x8D8D, 0xE062, 0x8D8E, 0xE060, 0x8D8F, 0xE061,
+ 0x8D90, 0xE065, 0x8D91, 0xE05E, 0x8D92, 0xE066, 0x8D93, 0xE063, 0x8D94, 0xE064, 0x8D95, 0xBBB0, 0x8D96, 0xE456, 0x8D99, 0xBBAF,
+ 0x8D9B, 0xE7F2, 0x8D9C, 0xE7F0, 0x8D9F, 0xBDEB, 0x8DA0, 0xE7EF, 0x8DA1, 0xE7F1, 0x8DA3, 0xBDEC, 0x8DA5, 0xEBBB, 0x8DA7, 0xEBBC,
+ 0x8DA8, 0xC1CD, 0x8DAA, 0xF34C, 0x8DAB, 0xF34E, 0x8DAC, 0xF34B, 0x8DAD, 0xF34D, 0x8DAE, 0xF4D6, 0x8DAF, 0xF654, 0x8DB2, 0xF96F,
+ 0x8DB3, 0xA8AC, 0x8DB4, 0xAD77, 0x8DB5, 0xD3E5, 0x8DB6, 0xD3E7, 0x8DB7, 0xD3E6, 0x8DB9, 0xD7D8, 0x8DBA, 0xB36C, 0x8DBC, 0xD7D6,
+ 0x8DBE, 0xB36B, 0x8DBF, 0xD7D9, 0x8DC1, 0xD7DA, 0x8DC2, 0xD7D7, 0x8DC5, 0xDBFB, 0x8DC6, 0xB660, 0x8DC7, 0xDBF3, 0x8DC8, 0xDBF9,
+ 0x8DCB, 0xB65B, 0x8DCC, 0xB65E, 0x8DCD, 0xDBF2, 0x8DCE, 0xB659, 0x8DCF, 0xDBF6, 0x8DD0, 0xE06C, 0x8DD1, 0xB65D, 0x8DD3, 0xDBF1,
+ 0x8DD5, 0xDBF7, 0x8DD6, 0xDBF4, 0x8DD7, 0xDBFA, 0x8DD8, 0xDBF0, 0x8DD9, 0xDBF8, 0x8DDA, 0xB65C, 0x8DDB, 0xB65F, 0x8DDC, 0xDBF5,
+ 0x8DDD, 0xB65A, 0x8DDF, 0xB8F2, 0x8DE0, 0xE068, 0x8DE1, 0xB8F1, 0x8DE2, 0xE06F, 0x8DE3, 0xE06E, 0x8DE4, 0xB8F8, 0x8DE6, 0xB8F9,
+ 0x8DE7, 0xE070, 0x8DE8, 0xB8F3, 0x8DE9, 0xE06D, 0x8DEA, 0xB8F7, 0x8DEB, 0xE072, 0x8DEC, 0xE069, 0x8DEE, 0xE06B, 0x8DEF, 0xB8F4,
+ 0x8DF0, 0xE067, 0x8DF1, 0xE06A, 0x8DF2, 0xE071, 0x8DF3, 0xB8F5, 0x8DF4, 0xE073, 0x8DFA, 0xB8F6, 0x8DFC, 0xBBB1, 0x8DFD, 0xE45B,
+ 0x8DFE, 0xE461, 0x8DFF, 0xE459, 0x8E00, 0xE462, 0x8E02, 0xE458, 0x8E03, 0xE45D, 0x8E04, 0xE463, 0x8E05, 0xE460, 0x8E06, 0xE45F,
+ 0x8E07, 0xE45E, 0x8E09, 0xE457, 0x8E0A, 0xE45C, 0x8E0D, 0xE45A, 0x8E0F, 0xBDF1, 0x8E10, 0xBDEE, 0x8E11, 0xE7FB, 0x8E12, 0xE841,
+ 0x8E13, 0xE843, 0x8E14, 0xE840, 0x8E15, 0xE7F8, 0x8E16, 0xE7FA, 0x8E17, 0xE845, 0x8E18, 0xE842, 0x8E19, 0xE7FC, 0x8E1A, 0xE846,
+ 0x8E1B, 0xE7F9, 0x8E1C, 0xE844, 0x8E1D, 0xBDEF, 0x8E1E, 0xBDF5, 0x8E1F, 0xBDF3, 0x8E20, 0xE7F3, 0x8E21, 0xBDF4, 0x8E22, 0xBDF0,
+ 0x8E23, 0xE7F4, 0x8E24, 0xE7F6, 0x8E25, 0xE7F5, 0x8E26, 0xE7FD, 0x8E27, 0xE7FE, 0x8E29, 0xBDF2, 0x8E2B, 0xBDED, 0x8E2E, 0xE7F7,
+ 0x8E30, 0xEBC6, 0x8E31, 0xBFE2, 0x8E33, 0xEBBD, 0x8E34, 0xBFE3, 0x8E35, 0xBFE6, 0x8E36, 0xEBC2, 0x8E38, 0xEBBF, 0x8E39, 0xBFE5,
+ 0x8E3C, 0xEBC3, 0x8E3D, 0xEBC4, 0x8E3E, 0xEBBE, 0x8E3F, 0xEBC7, 0x8E40, 0xEBC0, 0x8E41, 0xEBC5, 0x8E42, 0xBFE4, 0x8E44, 0xBFE1,
+ 0x8E45, 0xEBC1, 0x8E47, 0xEEBF, 0x8E48, 0xC1D0, 0x8E49, 0xC1CE, 0x8E4A, 0xC1D1, 0x8E4B, 0xC1CF, 0x8E4C, 0xEEBE, 0x8E4D, 0xEEBB,
+ 0x8E4E, 0xEEBA, 0x8E50, 0xEEBD, 0x8E53, 0xEEBC, 0x8E54, 0xF145, 0x8E55, 0xC2DE, 0x8E56, 0xF0FB, 0x8E57, 0xF0FA, 0x8E59, 0xC2D9,
+ 0x8E5A, 0xF141, 0x8E5B, 0xF140, 0x8E5C, 0xF0F7, 0x8E5D, 0xF143, 0x8E5E, 0xF0FC, 0x8E5F, 0xC2DD, 0x8E60, 0xF0F9, 0x8E61, 0xF142,
+ 0x8E62, 0xF0F8, 0x8E63, 0xC2DA, 0x8E64, 0xC2DC, 0x8E65, 0xF0FD, 0x8E66, 0xC2DB, 0x8E67, 0xF0FE, 0x8E69, 0xF144, 0x8E6A, 0xF352,
+ 0x8E6C, 0xC3DE, 0x8E6D, 0xF34F, 0x8E6F, 0xF353, 0x8E72, 0xC3DB, 0x8E73, 0xF351, 0x8E74, 0xC3E0, 0x8E76, 0xC3DD, 0x8E78, 0xF350,
+ 0x8E7A, 0xC3DF, 0x8E7B, 0xF354, 0x8E7C, 0xC3DA, 0x8E81, 0xC4BC, 0x8E82, 0xC4BE, 0x8E84, 0xF4D9, 0x8E85, 0xC4BD, 0x8E86, 0xF4D7,
+ 0x8E87, 0xC3DC, 0x8E88, 0xF4D8, 0x8E89, 0xC4BB, 0x8E8A, 0xC543, 0x8E8B, 0xC545, 0x8E8C, 0xF656, 0x8E8D, 0xC544, 0x8E8E, 0xF655,
+ 0x8E90, 0xF761, 0x8E91, 0xC5AD, 0x8E92, 0xF760, 0x8E93, 0xC5AE, 0x8E94, 0xF75E, 0x8E95, 0xF75D, 0x8E96, 0xF762, 0x8E97, 0xF763,
+ 0x8E98, 0xF846, 0x8E9A, 0xF75F, 0x8E9D, 0xF8C6, 0x8E9E, 0xF8C3, 0x8E9F, 0xF8C4, 0x8EA0, 0xF8C5, 0x8EA1, 0xC65C, 0x8EA3, 0xF951,
+ 0x8EA4, 0xF950, 0x8EA5, 0xF94F, 0x8EA6, 0xF970, 0x8EA8, 0xF9BE, 0x8EA9, 0xF9AB, 0x8EAA, 0xC66E, 0x8EAB, 0xA8AD, 0x8EAC, 0xB060,
+ 0x8EB2, 0xB8FA, 0x8EBA, 0xBDF6, 0x8EBD, 0xEBC8, 0x8EC0, 0xC2DF, 0x8EC2, 0xF355, 0x8EC9, 0xF9AC, 0x8ECA, 0xA8AE, 0x8ECB, 0xAAEE,
+ 0x8ECC, 0xAD79, 0x8ECD, 0xAD78, 0x8ECF, 0xB063, 0x8ED1, 0xD3E8, 0x8ED2, 0xB061, 0x8ED3, 0xD3E9, 0x8ED4, 0xB062, 0x8ED7, 0xD7DF,
+ 0x8ED8, 0xD7DB, 0x8EDB, 0xB36D, 0x8EDC, 0xD7DE, 0x8EDD, 0xD7DD, 0x8EDE, 0xD7DC, 0x8EDF, 0xB36E, 0x8EE0, 0xD7E0, 0x8EE1, 0xD7E1,
+ 0x8EE5, 0xDC43, 0x8EE6, 0xDC41, 0x8EE7, 0xDC45, 0x8EE8, 0xDC46, 0x8EE9, 0xDC4C, 0x8EEB, 0xDC48, 0x8EEC, 0xDC4A, 0x8EEE, 0xDC42,
+ 0x8EEF, 0xDBFC, 0x8EF1, 0xDC49, 0x8EF4, 0xDC4B, 0x8EF5, 0xDC44, 0x8EF6, 0xDC47, 0x8EF7, 0xDBFD, 0x8EF8, 0xB662, 0x8EF9, 0xDC40,
+ 0x8EFA, 0xDBFE, 0x8EFB, 0xB661, 0x8EFC, 0xB663, 0x8EFE, 0xB8FD, 0x8EFF, 0xE075, 0x8F00, 0xE077, 0x8F01, 0xE076, 0x8F02, 0xE07B,
+ 0x8F03, 0xB8FB, 0x8F05, 0xE078, 0x8F06, 0xE074, 0x8F07, 0xE079, 0x8F08, 0xE07A, 0x8F09, 0xB8FC, 0x8F0A, 0xB8FE, 0x8F0B, 0xE07C,
+ 0x8F0D, 0xE467, 0x8F0E, 0xE466, 0x8F10, 0xE464, 0x8F11, 0xE465, 0x8F12, 0xBBB3, 0x8F13, 0xBBB5, 0x8F14, 0xBBB2, 0x8F15, 0xBBB4,
+ 0x8F16, 0xE84D, 0x8F17, 0xE84E, 0x8F18, 0xE849, 0x8F1A, 0xE84A, 0x8F1B, 0xBDF8, 0x8F1C, 0xBDFD, 0x8F1D, 0xBDF7, 0x8F1E, 0xBDFE,
+ 0x8F1F, 0xBDF9, 0x8F20, 0xE84B, 0x8F23, 0xE84C, 0x8F24, 0xE848, 0x8F25, 0xBE40, 0x8F26, 0xBDFB, 0x8F29, 0xBDFA, 0x8F2A, 0xBDFC,
+ 0x8F2C, 0xE847, 0x8F2E, 0xEBCA, 0x8F2F, 0xBFE8, 0x8F32, 0xEBCC, 0x8F33, 0xBFEA, 0x8F34, 0xEBCF, 0x8F35, 0xEBCB, 0x8F36, 0xEBC9,
+ 0x8F37, 0xEBCE, 0x8F38, 0xBFE9, 0x8F39, 0xEBCD, 0x8F3B, 0xBFE7, 0x8F3E, 0xC1D3, 0x8F3F, 0xC1D6, 0x8F40, 0xEEC1, 0x8F42, 0xC1D4,
+ 0x8F43, 0xEEC0, 0x8F44, 0xC1D2, 0x8F45, 0xC1D5, 0x8F46, 0xF146, 0x8F47, 0xF147, 0x8F48, 0xF148, 0x8F49, 0xC2E0, 0x8F4B, 0xF149,
+ 0x8F4D, 0xC2E1, 0x8F4E, 0xC3E2, 0x8F4F, 0xF358, 0x8F50, 0xF359, 0x8F51, 0xF357, 0x8F52, 0xF356, 0x8F53, 0xF35A, 0x8F54, 0xC3E1,
+ 0x8F55, 0xF4DD, 0x8F56, 0xF4DB, 0x8F57, 0xF4DC, 0x8F58, 0xF4DE, 0x8F59, 0xF4DA, 0x8F5A, 0xF4DF, 0x8F5B, 0xF658, 0x8F5D, 0xF659,
+ 0x8F5E, 0xF657, 0x8F5F, 0xC546, 0x8F60, 0xF764, 0x8F61, 0xC5AF, 0x8F62, 0xF765, 0x8F63, 0xF848, 0x8F64, 0xF847, 0x8F9B, 0xA8AF,
+ 0x8F9C, 0xB664, 0x8F9F, 0xB940, 0x8FA3, 0xBBB6, 0x8FA6, 0xBFEC, 0x8FA8, 0xBFEB, 0x8FAD, 0xC3E3, 0x8FAE, 0xC47C, 0x8FAF, 0xC547,
+ 0x8FB0, 0xA8B0, 0x8FB1, 0xB064, 0x8FB2, 0xB941, 0x8FB4, 0xF35B, 0x8FBF, 0xCBA6, 0x8FC2, 0xA8B1, 0x8FC4, 0xA8B4, 0x8FC5, 0xA8B3,
+ 0x8FC6, 0xA8B2, 0x8FC9, 0xCBA5, 0x8FCB, 0xCDCD, 0x8FCD, 0xCDCF, 0x8FCE, 0xAAEF, 0x8FD1, 0xAAF1, 0x8FD2, 0xCDCC, 0x8FD3, 0xCDCE,
+ 0x8FD4, 0xAAF0, 0x8FD5, 0xCDD1, 0x8FD6, 0xCDD0, 0x8FD7, 0xCDD2, 0x8FE0, 0xD0B6, 0x8FE1, 0xD0B4, 0x8FE2, 0xAD7C, 0x8FE3, 0xD0B3,
+ 0x8FE4, 0xADA3, 0x8FE5, 0xAD7E, 0x8FE6, 0xAD7B, 0x8FE8, 0xADA4, 0x8FEA, 0xAD7D, 0x8FEB, 0xADA2, 0x8FED, 0xADA1, 0x8FEE, 0xD0B5,
+ 0x8FF0, 0xAD7A, 0x8FF4, 0xB06A, 0x8FF5, 0xD3EB, 0x8FF6, 0xD3F1, 0x8FF7, 0xB067, 0x8FF8, 0xB06E, 0x8FFA, 0xB069, 0x8FFB, 0xD3EE,
+ 0x8FFC, 0xD3F0, 0x8FFD, 0xB06C, 0x8FFE, 0xD3EA, 0x8FFF, 0xD3ED, 0x9000, 0xB068, 0x9001, 0xB065, 0x9002, 0xD3EC, 0x9003, 0xB06B,
+ 0x9004, 0xD3EF, 0x9005, 0xB06D, 0x9006, 0xB066, 0x900B, 0xD7E3, 0x900C, 0xD7E6, 0x900D, 0xB370, 0x900F, 0xB37A, 0x9010, 0xB376,
+ 0x9011, 0xD7E4, 0x9014, 0xB37E, 0x9015, 0xB377, 0x9016, 0xB37C, 0x9017, 0xB372, 0x9019, 0xB36F, 0x901A, 0xB371, 0x901B, 0xB37D,
+ 0x901C, 0xD7E5, 0x901D, 0xB375, 0x901E, 0xB378, 0x901F, 0xB374, 0x9020, 0xB379, 0x9021, 0xD7E7, 0x9022, 0xB37B, 0x9023, 0xB373,
+ 0x9024, 0xD7E2, 0x902D, 0xDC4D, 0x902E, 0xB665, 0x902F, 0xDC4F, 0x9031, 0xB667, 0x9032, 0xB669, 0x9034, 0xDC4E, 0x9035, 0xB666,
+ 0x9036, 0xB66A, 0x9038, 0xB668, 0x903C, 0xB947, 0x903D, 0xE0A3, 0x903E, 0xB94F, 0x903F, 0xE07E, 0x9041, 0xB950, 0x9042, 0xB945,
+ 0x9044, 0xE0A1, 0x9047, 0xB94A, 0x9049, 0xE0A2, 0x904A, 0xB943, 0x904B, 0xB942, 0x904D, 0xB94D, 0x904E, 0xB94C, 0x904F, 0xB94B,
+ 0x9050, 0xB949, 0x9051, 0xB94E, 0x9052, 0xE07D, 0x9053, 0xB944, 0x9054, 0xB946, 0x9055, 0xB948, 0x9058, 0xBBB8, 0x9059, 0xBBBB,
+ 0x905B, 0xBBBF, 0x905C, 0xBBB9, 0x905D, 0xBBBE, 0x905E, 0xBBBC, 0x9060, 0xBBB7, 0x9062, 0xBBBD, 0x9063, 0xBBBA, 0x9067, 0xE852,
+ 0x9068, 0xBE43, 0x9069, 0xBE41, 0x906B, 0xE853, 0x906D, 0xBE44, 0x906E, 0xBE42, 0x906F, 0xE851, 0x9070, 0xE850, 0x9072, 0xBFF0,
+ 0x9073, 0xE84F, 0x9074, 0xBFEE, 0x9075, 0xBFED, 0x9076, 0xEBD0, 0x9077, 0xBE45, 0x9078, 0xBFEF, 0x9079, 0xEBD1, 0x907A, 0xBFF2,
+ 0x907B, 0xEBD2, 0x907C, 0xBFF1, 0x907D, 0xC1D8, 0x907E, 0xEEC3, 0x907F, 0xC1D7, 0x9080, 0xC1DC, 0x9081, 0xC1DA, 0x9082, 0xC1DB,
+ 0x9083, 0xC2E3, 0x9084, 0xC1D9, 0x9085, 0xEEC2, 0x9086, 0xEBD3, 0x9087, 0xC2E2, 0x9088, 0xC2E4, 0x908A, 0xC3E4, 0x908B, 0xC3E5,
+ 0x908D, 0xF4E0, 0x908F, 0xC5DE, 0x9090, 0xC5DD, 0x9091, 0xA8B6, 0x9094, 0xCA55, 0x9095, 0xB06F, 0x9097, 0xCA52, 0x9098, 0xCA53,
+ 0x9099, 0xCA51, 0x909B, 0xCA54, 0x909E, 0xCBAA, 0x909F, 0xCBA7, 0x90A0, 0xCBAC, 0x90A1, 0xCBA8, 0x90A2, 0xA8B7, 0x90A3, 0xA8BA,
+ 0x90A5, 0xCBA9, 0x90A6, 0xA8B9, 0x90A7, 0xCBAB, 0x90AA, 0xA8B8, 0x90AF, 0xCDD5, 0x90B0, 0xCDD7, 0x90B1, 0xAAF4, 0x90B2, 0xCDD3,
+ 0x90B3, 0xCDD6, 0x90B4, 0xCDD4, 0x90B5, 0xAAF2, 0x90B6, 0xAAF5, 0x90B8, 0xAAF3, 0x90BD, 0xD0B8, 0x90BE, 0xD0BC, 0x90BF, 0xD0B9,
+ 0x90C1, 0xADA7, 0x90C3, 0xADA8, 0x90C5, 0xD0BB, 0x90C7, 0xD0BD, 0x90C8, 0xD0BF, 0x90CA, 0xADA5, 0x90CB, 0xD0BE, 0x90CE, 0xADA6,
+ 0x90D4, 0xD7EE, 0x90D5, 0xD0BA, 0x90D6, 0xD3F2, 0x90D7, 0xD3FB, 0x90D8, 0xD3F9, 0x90D9, 0xD3F4, 0x90DA, 0xD3F5, 0x90DB, 0xD3FA,
+ 0x90DC, 0xD3FC, 0x90DD, 0xB071, 0x90DF, 0xD3F7, 0x90E0, 0xD3F3, 0x90E1, 0xB070, 0x90E2, 0xB072, 0x90E3, 0xD3F6, 0x90E4, 0xD3FD,
+ 0x90E5, 0xD3F8, 0x90E8, 0xB3A1, 0x90E9, 0xD7F1, 0x90EA, 0xD7E9, 0x90EB, 0xD7EF, 0x90EC, 0xD7F0, 0x90ED, 0xB3A2, 0x90EF, 0xD7E8,
+ 0x90F0, 0xD7EA, 0x90F1, 0xD0B7, 0x90F2, 0xD7EC, 0x90F3, 0xD7ED, 0x90F4, 0xD7EB, 0x90F5, 0xB66C, 0x90F9, 0xDC56, 0x90FA, 0xEBD4,
+ 0x90FB, 0xDC57, 0x90FC, 0xDC54, 0x90FD, 0xB3A3, 0x90FE, 0xB66E, 0x90FF, 0xDC53, 0x9100, 0xDC59, 0x9101, 0xDC58, 0x9102, 0xB66B,
+ 0x9103, 0xDC5C, 0x9104, 0xDC52, 0x9105, 0xDC5B, 0x9106, 0xDC50, 0x9107, 0xDC5A, 0x9108, 0xDC55, 0x9109, 0xB66D, 0x910B, 0xE0AA,
+ 0x910D, 0xE0A5, 0x910E, 0xE0AB, 0x910F, 0xE0A6, 0x9110, 0xE0A4, 0x9111, 0xE0A7, 0x9112, 0xB951, 0x9114, 0xE0A9, 0x9116, 0xE0A8,
+ 0x9117, 0xB952, 0x9118, 0xBBC1, 0x9119, 0xBBC0, 0x911A, 0xE46E, 0x911B, 0xE471, 0x911C, 0xE469, 0x911D, 0xE46D, 0x911E, 0xBBC2,
+ 0x911F, 0xE46C, 0x9120, 0xE46A, 0x9121, 0xE470, 0x9122, 0xE46B, 0x9123, 0xE468, 0x9124, 0xE46F, 0x9126, 0xE859, 0x9127, 0xBE48,
+ 0x9128, 0xF14A, 0x9129, 0xE856, 0x912A, 0xE857, 0x912B, 0xE855, 0x912C, 0xDC51, 0x912D, 0xBE47, 0x912E, 0xE85A, 0x912F, 0xE854,
+ 0x9130, 0xBE46, 0x9131, 0xBE49, 0x9132, 0xE858, 0x9133, 0xEBD5, 0x9134, 0xBFF3, 0x9135, 0xEBD6, 0x9136, 0xEBD7, 0x9138, 0xEEC4,
+ 0x9139, 0xC1DD, 0x913A, 0xF14B, 0x913B, 0xF14C, 0x913E, 0xF14D, 0x913F, 0xF35D, 0x9140, 0xF35C, 0x9141, 0xF4E2, 0x9143, 0xF4E1,
+ 0x9144, 0xF65B, 0x9145, 0xF65C, 0x9146, 0xF65A, 0x9147, 0xF766, 0x9148, 0xC5B0, 0x9149, 0xA8BB, 0x914A, 0xADAA, 0x914B, 0xADA9,
+ 0x914C, 0xB075, 0x914D, 0xB074, 0x914E, 0xD440, 0x914F, 0xD441, 0x9150, 0xD3FE, 0x9152, 0xB073, 0x9153, 0xD7F5, 0x9155, 0xD7F6,
+ 0x9156, 0xD7F2, 0x9157, 0xB3A4, 0x9158, 0xD7F3, 0x915A, 0xD7F4, 0x915F, 0xDC5F, 0x9160, 0xDC61, 0x9161, 0xDC5D, 0x9162, 0xDC60,
+ 0x9163, 0xB66F, 0x9164, 0xDC5E, 0x9165, 0xB670, 0x9168, 0xDD73, 0x9169, 0xB955, 0x916A, 0xB954, 0x916C, 0xB953, 0x916E, 0xE0AC,
+ 0x916F, 0xE0AD, 0x9172, 0xE473, 0x9173, 0xE475, 0x9174, 0xBBC6, 0x9175, 0xBBC3, 0x9177, 0xBBC5, 0x9178, 0xBBC4, 0x9179, 0xE474,
+ 0x917A, 0xE472, 0x9180, 0xE861, 0x9181, 0xE85E, 0x9182, 0xE85F, 0x9183, 0xBE4D, 0x9184, 0xE860, 0x9185, 0xE85B, 0x9186, 0xE85C,
+ 0x9187, 0xBE4A, 0x9189, 0xBE4B, 0x918A, 0xE85D, 0x918B, 0xBE4C, 0x918D, 0xEBDB, 0x918F, 0xEBDC, 0x9190, 0xEBD9, 0x9191, 0xEBDA,
+ 0x9192, 0xBFF4, 0x9193, 0xEBD8, 0x9199, 0xEEC8, 0x919A, 0xEEC5, 0x919B, 0xEEC7, 0x919C, 0xC1E0, 0x919D, 0xEECB, 0x919E, 0xC1DF,
+ 0x919F, 0xEEC9, 0x91A0, 0xEECC, 0x91A1, 0xEECA, 0x91A2, 0xEEC6, 0x91A3, 0xC1DE, 0x91A5, 0xF14F, 0x91A7, 0xF150, 0x91A8, 0xF14E,
+ 0x91AA, 0xF152, 0x91AB, 0xC2E5, 0x91AC, 0xC2E6, 0x91AD, 0xF35F, 0x91AE, 0xC3E7, 0x91AF, 0xF151, 0x91B0, 0xF35E, 0x91B1, 0xC3E6,
+ 0x91B2, 0xF4E5, 0x91B3, 0xF4E6, 0x91B4, 0xC4BF, 0x91B5, 0xF4E4, 0x91B7, 0xF4E3, 0x91B9, 0xF65D, 0x91BA, 0xC548, 0x91BC, 0xF849,
+ 0x91BD, 0xF8C8, 0x91BE, 0xF8C7, 0x91C0, 0xC643, 0x91C1, 0xC65D, 0x91C2, 0xF8C9, 0x91C3, 0xF971, 0x91C5, 0xC66F, 0x91C6, 0xA8BC,
+ 0x91C7, 0xAAF6, 0x91C9, 0xB956, 0x91CB, 0xC4C0, 0x91CC, 0xA8BD, 0x91CD, 0xADAB, 0x91CE, 0xB3A5, 0x91CF, 0xB671, 0x91D0, 0xC2E7,
+ 0x91D1, 0xAAF7, 0x91D3, 0xD0C1, 0x91D4, 0xD0C0, 0x91D5, 0xD442, 0x91D7, 0xB078, 0x91D8, 0xB076, 0x91D9, 0xB07A, 0x91DA, 0xD444,
+ 0x91DC, 0xB079, 0x91DD, 0xB077, 0x91E2, 0xD443, 0x91E3, 0xB3A8, 0x91E4, 0xD7FC, 0x91E6, 0xB3A7, 0x91E7, 0xB3A9, 0x91E8, 0xD842,
+ 0x91E9, 0xB3AB, 0x91EA, 0xD7FE, 0x91EB, 0xD840, 0x91EC, 0xD7F7, 0x91ED, 0xB3AA, 0x91EE, 0xD843, 0x91F1, 0xD7F9, 0x91F3, 0xD7FA,
+ 0x91F4, 0xD7F8, 0x91F5, 0xB3A6, 0x91F7, 0xD841, 0x91F8, 0xD7FB, 0x91F9, 0xD7FD, 0x91FD, 0xDC6D, 0x91FF, 0xDC6C, 0x9200, 0xDC6A,
+ 0x9201, 0xDC62, 0x9202, 0xDC71, 0x9203, 0xDC65, 0x9204, 0xDC6F, 0x9205, 0xDC76, 0x9206, 0xDC6E, 0x9207, 0xB679, 0x9209, 0xB675,
+ 0x920A, 0xDC63, 0x920C, 0xDC69, 0x920D, 0xB677, 0x920F, 0xDC68, 0x9210, 0xB678, 0x9211, 0xB67A, 0x9212, 0xDC6B, 0x9214, 0xB672,
+ 0x9215, 0xB673, 0x9216, 0xDC77, 0x9217, 0xDC75, 0x9219, 0xDC74, 0x921A, 0xDC66, 0x921C, 0xDC72, 0x921E, 0xB676, 0x9223, 0xB674,
+ 0x9224, 0xDC73, 0x9225, 0xDC64, 0x9226, 0xDC67, 0x9227, 0xDC70, 0x922D, 0xE4BA, 0x922E, 0xE0B7, 0x9230, 0xE0B0, 0x9231, 0xE0C3,
+ 0x9232, 0xE0CC, 0x9233, 0xE0B3, 0x9234, 0xB961, 0x9236, 0xE0C0, 0x9237, 0xB957, 0x9238, 0xB959, 0x9239, 0xB965, 0x923A, 0xE0B1,
+ 0x923D, 0xB95A, 0x923E, 0xB95C, 0x923F, 0xB966, 0x9240, 0xB95B, 0x9245, 0xB964, 0x9246, 0xE0B9, 0x9248, 0xE0AE, 0x9249, 0xB962,
+ 0x924A, 0xE0B8, 0x924B, 0xB95E, 0x924C, 0xE0CA, 0x924D, 0xB963, 0x924E, 0xE0C8, 0x924F, 0xE0BC, 0x9250, 0xE0C6, 0x9251, 0xB960,
+ 0x9252, 0xE0AF, 0x9253, 0xE0C9, 0x9254, 0xE0C4, 0x9256, 0xE0CB, 0x9257, 0xB958, 0x925A, 0xB967, 0x925B, 0xB95D, 0x925E, 0xE0B5,
+ 0x9260, 0xE0BD, 0x9261, 0xE0C1, 0x9263, 0xE0C5, 0x9264, 0xB95F, 0x9265, 0xE0B4, 0x9266, 0xE0B2, 0x9267, 0xE0BE, 0x926C, 0xE0BB,
+ 0x926D, 0xE0BA, 0x926F, 0xE0BF, 0x9270, 0xE0C2, 0x9272, 0xE0C7, 0x9276, 0xE478, 0x9278, 0xBBC7, 0x9279, 0xE4A4, 0x927A, 0xE47A,
+ 0x927B, 0xBBCC, 0x927C, 0xBBD0, 0x927D, 0xE4AD, 0x927E, 0xE4B5, 0x927F, 0xE4A6, 0x9280, 0xBBC8, 0x9282, 0xE4AA, 0x9283, 0xE0B6,
+ 0x9285, 0xBBC9, 0x9286, 0xE4B1, 0x9287, 0xE4B6, 0x9288, 0xE4AE, 0x928A, 0xE4B0, 0x928B, 0xE4B9, 0x928C, 0xE4B2, 0x928D, 0xE47E,
+ 0x928E, 0xE4A9, 0x9291, 0xBBD1, 0x9293, 0xBBCD, 0x9294, 0xE47C, 0x9295, 0xE4AB, 0x9296, 0xBBCB, 0x9297, 0xE4A5, 0x9298, 0xBBCA,
+ 0x9299, 0xE4B3, 0x929A, 0xE4A2, 0x929B, 0xE479, 0x929C, 0xBBCE, 0x929D, 0xE4B8, 0x92A0, 0xE47B, 0x92A1, 0xE4AF, 0x92A2, 0xE4AC,
+ 0x92A3, 0xE4A7, 0x92A4, 0xE477, 0x92A5, 0xE476, 0x92A6, 0xE4A1, 0x92A7, 0xE4B4, 0x92A8, 0xBBCF, 0x92A9, 0xE4B7, 0x92AA, 0xE47D,
+ 0x92AB, 0xE4A3, 0x92AC, 0xBE52, 0x92B2, 0xBE5A, 0x92B3, 0xBE55, 0x92B4, 0xE8A4, 0x92B5, 0xE8A1, 0x92B6, 0xE867, 0x92B7, 0xBE50,
+ 0x92B9, 0xF9D7, 0x92BB, 0xBE4F, 0x92BC, 0xBE56, 0x92C0, 0xE865, 0x92C1, 0xBE54, 0x92C2, 0xE871, 0x92C3, 0xE863, 0x92C4, 0xE864,
+ 0x92C5, 0xBE4E, 0x92C6, 0xE8A3, 0x92C7, 0xBE58, 0x92C8, 0xE874, 0x92C9, 0xE879, 0x92CA, 0xE873, 0x92CB, 0xEBEE, 0x92CC, 0xE86F,
+ 0x92CD, 0xE877, 0x92CE, 0xE875, 0x92CF, 0xE868, 0x92D0, 0xE862, 0x92D1, 0xE87D, 0x92D2, 0xBE57, 0x92D3, 0xE87E, 0x92D5, 0xE878,
+ 0x92D7, 0xE86D, 0x92D8, 0xE86B, 0x92D9, 0xE866, 0x92DD, 0xE86E, 0x92DE, 0xE87B, 0x92DF, 0xE86A, 0x92E0, 0xE87A, 0x92E1, 0xE8A2,
+ 0x92E4, 0xBE53, 0x92E6, 0xE876, 0x92E7, 0xE87C, 0x92E8, 0xE872, 0x92E9, 0xE86C, 0x92EA, 0xBE51, 0x92EE, 0xE4A8, 0x92EF, 0xE870,
+ 0x92F0, 0xBE59, 0x92F1, 0xE869, 0x92F7, 0xEBF4, 0x92F8, 0xBFF7, 0x92F9, 0xEBF3, 0x92FA, 0xEBF0, 0x92FB, 0xEC44, 0x92FC, 0xBFFB,
+ 0x92FE, 0xEC41, 0x92FF, 0xEBF8, 0x9300, 0xEC43, 0x9301, 0xEBE9, 0x9302, 0xEBF6, 0x9304, 0xBFFD, 0x9306, 0xEBE1, 0x9308, 0xEBDF,
+ 0x9309, 0xEC42, 0x930B, 0xEC40, 0x930C, 0xEBFE, 0x930D, 0xEBED, 0x930E, 0xEBEC, 0x930F, 0xEBE2, 0x9310, 0xC040, 0x9312, 0xEBE8,
+ 0x9313, 0xEBF2, 0x9314, 0xEBFD, 0x9315, 0xC043, 0x9316, 0xEC45, 0x9318, 0xC1E8, 0x9319, 0xC045, 0x931A, 0xBFFE, 0x931B, 0xEBE6,
+ 0x931D, 0xEBEF, 0x931E, 0xEBDE, 0x931F, 0xEBE0, 0x9320, 0xBFF5, 0x9321, 0xC042, 0x9322, 0xBFFA, 0x9323, 0xEBE7, 0x9324, 0xEBF7,
+ 0x9325, 0xEBF1, 0x9326, 0xC041, 0x9327, 0xEBDD, 0x9328, 0xC1E3, 0x9329, 0xEBF9, 0x932A, 0xEBFC, 0x932B, 0xBFFC, 0x932D, 0xEBEB,
+ 0x932E, 0xC044, 0x932F, 0xBFF9, 0x9333, 0xBFF8, 0x9334, 0xEBF5, 0x9335, 0xEBFB, 0x9336, 0xBFF6, 0x9338, 0xEBE4, 0x9339, 0xEBFA,
+ 0x933C, 0xEBE5, 0x9346, 0xEBEA, 0x9347, 0xEED2, 0x9349, 0xEED7, 0x934A, 0xC1E5, 0x934B, 0xC1E7, 0x934C, 0xEEDD, 0x934D, 0xC1E1,
+ 0x934E, 0xEEEC, 0x934F, 0xEEE3, 0x9350, 0xEED8, 0x9351, 0xEED9, 0x9352, 0xEEE2, 0x9354, 0xC1EE, 0x9355, 0xEEE1, 0x9356, 0xEED1,
+ 0x9357, 0xEEE0, 0x9358, 0xEED4, 0x9359, 0xEEED, 0x935A, 0xC1ED, 0x935B, 0xC1EB, 0x935C, 0xEED5, 0x935E, 0xEEE8, 0x9360, 0xEEDA,
+ 0x9361, 0xEEE7, 0x9363, 0xEEE9, 0x9364, 0xEED0, 0x9365, 0xC1E6, 0x9367, 0xEEEA, 0x936A, 0xEEDE, 0x936C, 0xC1EA, 0x936D, 0xEEDB,
+ 0x9370, 0xC1EC, 0x9371, 0xEEE4, 0x9375, 0xC1E4, 0x9376, 0xEED6, 0x9377, 0xEEE5, 0x9379, 0xEEDF, 0x937A, 0xEBE3, 0x937B, 0xEEE6,
+ 0x937C, 0xEED3, 0x937E, 0xC1E9, 0x9380, 0xEEEB, 0x9382, 0xC1E2, 0x9383, 0xEECE, 0x9388, 0xF160, 0x9389, 0xF159, 0x938A, 0xC2E9,
+ 0x938C, 0xF154, 0x938D, 0xF163, 0x938E, 0xF15B, 0x938F, 0xEEDC, 0x9391, 0xF165, 0x9392, 0xF155, 0x9394, 0xC2E8, 0x9395, 0xF15F,
+ 0x9396, 0xC2EA, 0x9397, 0xC2F2, 0x9398, 0xC2F0, 0x9399, 0xF161, 0x939A, 0xC2F1, 0x939B, 0xF157, 0x939D, 0xF158, 0x939E, 0xF15D,
+ 0x939F, 0xF162, 0x93A1, 0xEECD, 0x93A2, 0xC2EB, 0x93A3, 0xF16A, 0x93A4, 0xF167, 0x93A5, 0xF16B, 0x93A6, 0xF15E, 0x93A7, 0xF15A,
+ 0x93A8, 0xF168, 0x93A9, 0xF36A, 0x93AA, 0xF15C, 0x93AC, 0xC2EE, 0x93AE, 0xC2ED, 0x93AF, 0xEECF, 0x93B0, 0xC2EF, 0x93B1, 0xF164,
+ 0x93B2, 0xF166, 0x93B3, 0xC2EC, 0x93B4, 0xF169, 0x93B5, 0xF153, 0x93B7, 0xF156, 0x93C0, 0xF373, 0x93C2, 0xF363, 0x93C3, 0xC3EB,
+ 0x93C4, 0xF371, 0x93C7, 0xF361, 0x93C8, 0xC3EC, 0x93CA, 0xF36C, 0x93CC, 0xF368, 0x93CD, 0xC3F1, 0x93CE, 0xF372, 0x93CF, 0xF362,
+ 0x93D0, 0xF365, 0x93D1, 0xC3E9, 0x93D2, 0xF374, 0x93D4, 0xF36D, 0x93D5, 0xF370, 0x93D6, 0xC3EF, 0x93D7, 0xC3F4, 0x93D8, 0xC3F2,
+ 0x93D9, 0xF369, 0x93DA, 0xF364, 0x93DC, 0xC3ED, 0x93DD, 0xC3EE, 0x93DE, 0xF360, 0x93DF, 0xC3EA, 0x93E1, 0xC3E8, 0x93E2, 0xC3F0,
+ 0x93E3, 0xF36F, 0x93E4, 0xC3F3, 0x93E6, 0xF36B, 0x93E7, 0xF375, 0x93E8, 0xC3F5, 0x93EC, 0xF367, 0x93EE, 0xF36E, 0x93F5, 0xF4F3,
+ 0x93F6, 0xF542, 0x93F7, 0xF4F5, 0x93F8, 0xF4FC, 0x93F9, 0xF366, 0x93FA, 0xF4FA, 0x93FB, 0xF4E9, 0x93FC, 0xF540, 0x93FD, 0xC4C3,
+ 0x93FE, 0xF4ED, 0x93FF, 0xF4FE, 0x9400, 0xF4F4, 0x9403, 0xC4C2, 0x9406, 0xF544, 0x9407, 0xF4F6, 0x9409, 0xF4FB, 0x940A, 0xF4FD,
+ 0x940B, 0xF4E7, 0x940C, 0xF541, 0x940D, 0xF4F2, 0x940E, 0xF4F7, 0x940F, 0xF4EB, 0x9410, 0xF4EF, 0x9411, 0xF543, 0x9412, 0xF4F9,
+ 0x9413, 0xF4E8, 0x9414, 0xF4EC, 0x9415, 0xF4EE, 0x9416, 0xF4F8, 0x9418, 0xC4C1, 0x9419, 0xF4F1, 0x9420, 0xF4EA, 0x9428, 0xF4F0,
+ 0x9429, 0xF661, 0x942A, 0xF666, 0x942B, 0xC54F, 0x942C, 0xF668, 0x942E, 0xC549, 0x9430, 0xF664, 0x9431, 0xF66A, 0x9432, 0xC54E,
+ 0x9433, 0xC54A, 0x9435, 0xC54B, 0x9436, 0xF660, 0x9437, 0xF667, 0x9438, 0xC54D, 0x9439, 0xF665, 0x943A, 0xC54C, 0x943B, 0xF65F,
+ 0x943C, 0xF663, 0x943D, 0xF662, 0x943F, 0xF65E, 0x9440, 0xF669, 0x9444, 0xC5B1, 0x9445, 0xF76D, 0x9446, 0xF770, 0x9447, 0xF76C,
+ 0x9448, 0xF76E, 0x9449, 0xF76F, 0x944A, 0xF769, 0x944B, 0xF76A, 0x944C, 0xF767, 0x944F, 0xF76B, 0x9450, 0xF768, 0x9451, 0xC5B2,
+ 0x9452, 0xC5B3, 0x9455, 0xF84B, 0x9457, 0xF84D, 0x945D, 0xF84C, 0x945E, 0xF84E, 0x9460, 0xC5E0, 0x9462, 0xF84A, 0x9463, 0xC5DF,
+ 0x9464, 0xC5E1, 0x9468, 0xF8CB, 0x9469, 0xF8CC, 0x946A, 0xC644, 0x946B, 0xF8CA, 0x946D, 0xF953, 0x946E, 0xF952, 0x946F, 0xF954,
+ 0x9470, 0xC65F, 0x9471, 0xF955, 0x9472, 0xC65E, 0x9473, 0xF956, 0x9474, 0xF972, 0x9475, 0xF975, 0x9476, 0xF974, 0x9477, 0xC668,
+ 0x9478, 0xF973, 0x947C, 0xC672, 0x947D, 0xC670, 0x947E, 0xC671, 0x947F, 0xC677, 0x9480, 0xF9C0, 0x9481, 0xF9C1, 0x9482, 0xF9BF,
+ 0x9483, 0xF9C9, 0x9577, 0xAAF8, 0x957A, 0xD844, 0x957B, 0xDC78, 0x957C, 0xE8A5, 0x957D, 0xF376, 0x9580, 0xAAF9, 0x9582, 0xADAC,
+ 0x9583, 0xB07B, 0x9586, 0xD845, 0x9588, 0xD846, 0x9589, 0xB3AC, 0x958B, 0xB67D, 0x958C, 0xDC7A, 0x958D, 0xDC79, 0x958E, 0xB6A3,
+ 0x958F, 0xB67C, 0x9590, 0xDC7B, 0x9591, 0xB67E, 0x9592, 0xB6A2, 0x9593, 0xB6A1, 0x9594, 0xB67B, 0x9598, 0xB968, 0x959B, 0xE0D0,
+ 0x959C, 0xE0CE, 0x959E, 0xE0CF, 0x959F, 0xE0CD, 0x95A1, 0xBBD2, 0x95A3, 0xBBD5, 0x95A4, 0xBBD7, 0x95A5, 0xBBD6, 0x95A8, 0xBBD3,
+ 0x95A9, 0xBBD4, 0x95AB, 0xE8A7, 0x95AC, 0xE8A6, 0x95AD, 0xBE5B, 0x95AE, 0xE8A8, 0x95B0, 0xE8A9, 0x95B1, 0xBE5C, 0x95B5, 0xEC4D,
+ 0x95B6, 0xEC4B, 0x95B7, 0xEEF3, 0x95B9, 0xEC49, 0x95BA, 0xEC4A, 0x95BB, 0xC046, 0x95BC, 0xEC46, 0x95BD, 0xEC4E, 0x95BE, 0xEC48,
+ 0x95BF, 0xEC4C, 0x95C0, 0xEEEF, 0x95C3, 0xEEF1, 0x95C5, 0xEEF2, 0x95C6, 0xC1F3, 0x95C7, 0xEEEE, 0x95C8, 0xC1F2, 0x95C9, 0xEEF0,
+ 0x95CA, 0xC1EF, 0x95CB, 0xC1F0, 0x95CC, 0xC1F1, 0x95CD, 0xEC47, 0x95D0, 0xC2F5, 0x95D1, 0xF16E, 0x95D2, 0xF16C, 0x95D3, 0xF16D,
+ 0x95D4, 0xC2F3, 0x95D5, 0xC2F6, 0x95D6, 0xC2F4, 0x95DA, 0xF377, 0x95DB, 0xF378, 0x95DC, 0xC3F6, 0x95DE, 0xF545, 0x95DF, 0xF547,
+ 0x95E0, 0xF546, 0x95E1, 0xC4C4, 0x95E2, 0xC550, 0x95E3, 0xF66D, 0x95E4, 0xF66C, 0x95E5, 0xF66B, 0x961C, 0xAAFA, 0x961E, 0xC9AA,
+ 0x9620, 0xCA58, 0x9621, 0xA6E9, 0x9622, 0xCA56, 0x9623, 0xCA59, 0x9624, 0xCA57, 0x9628, 0xCBAE, 0x962A, 0xA8C1, 0x962C, 0xA8C2,
+ 0x962D, 0xCBB0, 0x962E, 0xA8BF, 0x962F, 0xCBAF, 0x9630, 0xCBAD, 0x9631, 0xA8C0, 0x9632, 0xA8BE, 0x9639, 0xCDD8, 0x963A, 0xCDDB,
+ 0x963B, 0xAAFD, 0x963C, 0xCDDA, 0x963D, 0xCDD9, 0x963F, 0xAAFC, 0x9640, 0xAAFB, 0x9642, 0xAB40, 0x9643, 0xCDDC, 0x9644, 0xAAFE,
+ 0x964A, 0xD0C6, 0x964B, 0xADAE, 0x964C, 0xADAF, 0x964D, 0xADB0, 0x964E, 0xD0C7, 0x964F, 0xD0C3, 0x9650, 0xADAD, 0x9651, 0xD0C4,
+ 0x9653, 0xD0C5, 0x9654, 0xD0C2, 0x9658, 0xB0A4, 0x965B, 0xB0A1, 0x965C, 0xD445, 0x965D, 0xB0A2, 0x965E, 0xB0A5, 0x965F, 0xD446,
+ 0x9661, 0xB07E, 0x9662, 0xB07C, 0x9663, 0xB07D, 0x9664, 0xB0A3, 0x966A, 0xB3AD, 0x966B, 0xD849, 0x966C, 0xB3B5, 0x966D, 0xD848,
+ 0x966F, 0xD84B, 0x9670, 0xB3B1, 0x9671, 0xD84A, 0x9672, 0xB6AB, 0x9673, 0xB3AF, 0x9674, 0xB3B2, 0x9675, 0xB3AE, 0x9676, 0xB3B3,
+ 0x9677, 0xB3B4, 0x9678, 0xB3B0, 0x967C, 0xD847, 0x967D, 0xB6A7, 0x967E, 0xDC7D, 0x9680, 0xDCA3, 0x9683, 0xDCA2, 0x9684, 0xB6AC,
+ 0x9685, 0xB6A8, 0x9686, 0xB6A9, 0x9687, 0xDC7C, 0x9688, 0xDC7E, 0x9689, 0xDCA1, 0x968A, 0xB6A4, 0x968B, 0xB6A6, 0x968D, 0xB6AA,
+ 0x968E, 0xB6A5, 0x9691, 0xE0D3, 0x9692, 0xE0D1, 0x9693, 0xE0D2, 0x9694, 0xB96A, 0x9695, 0xB96B, 0x9697, 0xE0D4, 0x9698, 0xB969,
+ 0x9699, 0xBBD8, 0x969B, 0xBBDA, 0x969C, 0xBBD9, 0x969E, 0xE4BB, 0x96A1, 0xE4BC, 0x96A2, 0xE8AB, 0x96A4, 0xE8AA, 0x96A7, 0xC047,
+ 0x96A8, 0xC048, 0x96A9, 0xEC4F, 0x96AA, 0xC049, 0x96AC, 0xEEF6, 0x96AE, 0xEEF4, 0x96B0, 0xEEF5, 0x96B1, 0xC1F4, 0x96B3, 0xF16F,
+ 0x96B4, 0xC3F7, 0x96B8, 0xC1F5, 0x96B9, 0xAB41, 0x96BB, 0xB0A6, 0x96BC, 0xD447, 0x96BF, 0xD84C, 0x96C0, 0xB3B6, 0x96C1, 0xB6AD,
+ 0x96C2, 0xDCA4, 0x96C3, 0xDCA6, 0x96C4, 0xB6AF, 0x96C5, 0xB6AE, 0x96C6, 0xB6B0, 0x96C7, 0xB6B1, 0x96C8, 0xDCA5, 0x96C9, 0xB96E,
+ 0x96CA, 0xB96F, 0x96CB, 0xB96D, 0x96CC, 0xBBDB, 0x96CD, 0xB96C, 0x96CE, 0xE0D5, 0x96D2, 0xBBDC, 0x96D3, 0xE8AC, 0x96D4, 0xEC50,
+ 0x96D5, 0xC04A, 0x96D6, 0xC1F6, 0x96D7, 0xF170, 0x96D8, 0xF174, 0x96D9, 0xC2F9, 0x96DA, 0xF171, 0x96DB, 0xC2FA, 0x96DC, 0xC2F8,
+ 0x96DD, 0xF175, 0x96DE, 0xC2FB, 0x96DF, 0xF173, 0x96E1, 0xF379, 0x96E2, 0xC2F7, 0x96E3, 0xC3F8, 0x96E5, 0xF8CD, 0x96E8, 0xAB42,
+ 0x96E9, 0xB3B8, 0x96EA, 0xB3B7, 0x96EF, 0xB6B2, 0x96F0, 0xDCA8, 0x96F1, 0xDCA7, 0x96F2, 0xB6B3, 0x96F5, 0xE0D9, 0x96F6, 0xB973,
+ 0x96F7, 0xB970, 0x96F8, 0xE0D8, 0x96F9, 0xB972, 0x96FA, 0xE0D6, 0x96FB, 0xB971, 0x96FD, 0xE0D7, 0x96FF, 0xE4BD, 0x9700, 0xBBDD,
+ 0x9702, 0xE8AF, 0x9704, 0xBE5D, 0x9705, 0xE8AD, 0x9706, 0xBE5E, 0x9707, 0xBE5F, 0x9708, 0xE8AE, 0x9709, 0xBE60, 0x970B, 0xEC51,
+ 0x970D, 0xC04E, 0x970E, 0xC04B, 0x970F, 0xC050, 0x9710, 0xEC53, 0x9711, 0xC04C, 0x9712, 0xEC52, 0x9713, 0xC04F, 0x9716, 0xC04D,
+ 0x9718, 0xEEF9, 0x9719, 0xEEFB, 0x971C, 0xC1F7, 0x971D, 0xEEFA, 0x971E, 0xC1F8, 0x971F, 0xEEF8, 0x9720, 0xEEF7, 0x9722, 0xF177,
+ 0x9723, 0xF176, 0x9724, 0xC2FC, 0x9725, 0xF178, 0x9726, 0xF37E, 0x9727, 0xC3FA, 0x9728, 0xF37D, 0x9729, 0xF37A, 0x972A, 0xC3F9,
+ 0x972B, 0xF37B, 0x972C, 0xF37C, 0x972E, 0xF548, 0x972F, 0xF549, 0x9730, 0xC4C5, 0x9732, 0xC553, 0x9735, 0xF66E, 0x9738, 0xC551,
+ 0x9739, 0xC552, 0x973A, 0xF66F, 0x973D, 0xC5B4, 0x973E, 0xC5B5, 0x973F, 0xF771, 0x9742, 0xC645, 0x9743, 0xF8CF, 0x9744, 0xC647,
+ 0x9746, 0xF8CE, 0x9747, 0xF8D0, 0x9748, 0xC646, 0x9749, 0xF957, 0x974B, 0xF9AD, 0x9752, 0xAB43, 0x9756, 0xB974, 0x9758, 0xE4BE,
+ 0x975A, 0xE8B0, 0x975B, 0xC051, 0x975C, 0xC052, 0x975E, 0xAB44, 0x9760, 0xBE61, 0x9761, 0xC3FB, 0x9762, 0xADB1, 0x9766, 0xC053,
+ 0x9768, 0xC5E2, 0x9769, 0xADB2, 0x976A, 0xD84D, 0x976C, 0xDCA9, 0x976E, 0xDCAB, 0x9770, 0xDCAA, 0x9772, 0xE0DD, 0x9773, 0xE0DA,
+ 0x9774, 0xB975, 0x9776, 0xB976, 0x9777, 0xE0DB, 0x9778, 0xE0DC, 0x977A, 0xE4C0, 0x977B, 0xE4C5, 0x977C, 0xBBDE, 0x977D, 0xE4BF,
+ 0x977E, 0xE4C1, 0x977F, 0xE4C8, 0x9780, 0xE4C3, 0x9781, 0xE4C7, 0x9782, 0xE4C4, 0x9783, 0xE4C2, 0x9784, 0xE4C6, 0x9785, 0xBBDF,
+ 0x9788, 0xE8B3, 0x978A, 0xE8B1, 0x978B, 0xBE63, 0x978D, 0xBE62, 0x978E, 0xE8B2, 0x978F, 0xBE64, 0x9794, 0xEC56, 0x9797, 0xEC55,
+ 0x9798, 0xC054, 0x9799, 0xEC54, 0x979A, 0xEEFC, 0x979C, 0xEEFE, 0x979D, 0xEF41, 0x979E, 0xEF40, 0x97A0, 0xC1F9, 0x97A1, 0xEEFD,
+ 0x97A2, 0xF1A1, 0x97A3, 0xC2FD, 0x97A4, 0xF17D, 0x97A5, 0xF1A2, 0x97A6, 0xC2FE, 0x97A8, 0xF17B, 0x97AA, 0xF17E, 0x97AB, 0xF17C,
+ 0x97AC, 0xF179, 0x97AD, 0xC340, 0x97AE, 0xF17A, 0x97B3, 0xF3A1, 0x97B6, 0xF3A3, 0x97B7, 0xF3A2, 0x97B9, 0xF54A, 0x97BB, 0xF54B,
+ 0x97BF, 0xF670, 0x97C1, 0xC5B7, 0x97C3, 0xC5B6, 0x97C4, 0xF84F, 0x97C5, 0xF850, 0x97C6, 0xC648, 0x97C7, 0xF8D1, 0x97C9, 0xC669,
+ 0x97CB, 0xADB3, 0x97CC, 0xB6B4, 0x97CD, 0xE4CA, 0x97CE, 0xE4C9, 0x97CF, 0xE8B5, 0x97D0, 0xE8B4, 0x97D3, 0xC1FA, 0x97D4, 0xEF43,
+ 0x97D5, 0xEF42, 0x97D6, 0xF1A5, 0x97D7, 0xF1A3, 0x97D8, 0xF1A6, 0x97D9, 0xF1A4, 0x97DC, 0xC3FC, 0x97DD, 0xF3A4, 0x97DE, 0xF3A5,
+ 0x97DF, 0xF3A6, 0x97E1, 0xF671, 0x97E3, 0xF772, 0x97E5, 0xF8D2, 0x97ED, 0xADB4, 0x97F0, 0xEC57, 0x97F1, 0xEF44, 0x97F3, 0xADB5,
+ 0x97F6, 0xBBE0, 0x97F8, 0xEC58, 0x97F9, 0xC341, 0x97FA, 0xF1A7, 0x97FB, 0xC3FD, 0x97FD, 0xF54C, 0x97FE, 0xF54D, 0x97FF, 0xC554,
+ 0x9800, 0xF851, 0x9801, 0xADB6, 0x9802, 0xB3BB, 0x9803, 0xB3BC, 0x9804, 0xD84E, 0x9805, 0xB6B5, 0x9806, 0xB6B6, 0x9807, 0xDCAC,
+ 0x9808, 0xB6B7, 0x980A, 0xB97A, 0x980C, 0xB97C, 0x980D, 0xE0DF, 0x980E, 0xE0E0, 0x980F, 0xE0DE, 0x9810, 0xB977, 0x9811, 0xB978,
+ 0x9812, 0xB97B, 0x9813, 0xB979, 0x9816, 0xE4CB, 0x9817, 0xBBE1, 0x9818, 0xBBE2, 0x981B, 0xE8BC, 0x981C, 0xBE67, 0x981D, 0xE8B7,
+ 0x981E, 0xE8B6, 0x9820, 0xE8BB, 0x9821, 0xBE65, 0x9824, 0xC05B, 0x9826, 0xE8B8, 0x9827, 0xE8BD, 0x9828, 0xE8BA, 0x9829, 0xE8B9,
+ 0x982B, 0xBE66, 0x982D, 0xC059, 0x982F, 0xEC5A, 0x9830, 0xC055, 0x9832, 0xEC5B, 0x9835, 0xEC59, 0x9837, 0xC058, 0x9838, 0xC056,
+ 0x9839, 0xC05A, 0x983B, 0xC057, 0x9841, 0xEF45, 0x9843, 0xEF4A, 0x9844, 0xEF46, 0x9845, 0xEF49, 0x9846, 0xC1FB, 0x9848, 0xEDD4,
+ 0x9849, 0xEF48, 0x984A, 0xEF47, 0x984C, 0xC344, 0x984D, 0xC342, 0x984E, 0xC345, 0x984F, 0xC343, 0x9850, 0xF1A8, 0x9851, 0xF1A9,
+ 0x9852, 0xF1AA, 0x9853, 0xC346, 0x9857, 0xF3AA, 0x9858, 0xC440, 0x9859, 0xF3A8, 0x985B, 0xC441, 0x985C, 0xF3A7, 0x985D, 0xF3A9,
+ 0x985E, 0xC3FE, 0x985F, 0xF551, 0x9860, 0xF54E, 0x9862, 0xF54F, 0x9863, 0xF550, 0x9864, 0xF672, 0x9865, 0xC556, 0x9867, 0xC555,
+ 0x9869, 0xF774, 0x986A, 0xF773, 0x986B, 0xC5B8, 0x986F, 0xC5E3, 0x9870, 0xC649, 0x9871, 0xC660, 0x9872, 0xF958, 0x9873, 0xF9AE,
+ 0x9874, 0xF9AF, 0x98A8, 0xADB7, 0x98A9, 0xDCAD, 0x98AC, 0xE0E1, 0x98AD, 0xE4CC, 0x98AE, 0xE4CD, 0x98AF, 0xBBE3, 0x98B1, 0xBBE4,
+ 0x98B2, 0xE8BE, 0x98B3, 0xBE68, 0x98B6, 0xC1FC, 0x98B8, 0xF1AB, 0x98BA, 0xC347, 0x98BB, 0xF3AD, 0x98BC, 0xC442, 0x98BD, 0xF3AC,
+ 0x98BE, 0xF3AE, 0x98BF, 0xF3AB, 0x98C0, 0xF675, 0x98C1, 0xF552, 0x98C2, 0xF553, 0x98C4, 0xC4C6, 0x98C6, 0xF674, 0x98C9, 0xF673,
+ 0x98CB, 0xF775, 0x98CC, 0xF9B0, 0x98DB, 0xADB8, 0x98DF, 0xADB9, 0x98E2, 0xB0A7, 0x98E3, 0xD448, 0x98E5, 0xD84F, 0x98E7, 0xB6B8,
+ 0x98E9, 0xB6BB, 0x98EA, 0xB6B9, 0x98EB, 0xDCAE, 0x98ED, 0xB6BD, 0x98EF, 0xB6BA, 0x98F2, 0xB6BC, 0x98F4, 0xB97E, 0x98F6, 0xE0E2,
+ 0x98F9, 0xE0E3, 0x98FA, 0xE8C0, 0x98FC, 0xB97D, 0x98FD, 0xB9A1, 0x98FE, 0xB9A2, 0x9900, 0xE4CF, 0x9902, 0xE4CE, 0x9903, 0xBBE5,
+ 0x9905, 0xBBE6, 0x9907, 0xE4D0, 0x9908, 0xE8BF, 0x9909, 0xBBE8, 0x990A, 0xBE69, 0x990C, 0xBBE7, 0x9910, 0xC05C, 0x9911, 0xE8C1,
+ 0x9912, 0xBE6B, 0x9913, 0xBE6A, 0x9914, 0xE8C2, 0x9915, 0xE8C5, 0x9916, 0xE8C3, 0x9917, 0xE8C4, 0x9918, 0xBE6C, 0x991A, 0xC061,
+ 0x991B, 0xC05F, 0x991E, 0xC05E, 0x991F, 0xEC5D, 0x9921, 0xC060, 0x9924, 0xEC5C, 0x9925, 0xEF4B, 0x9927, 0xEC5E, 0x9928, 0xC05D,
+ 0x9929, 0xEC5F, 0x992A, 0xEF4E, 0x992B, 0xEF4C, 0x992C, 0xEF4D, 0x992D, 0xEF52, 0x992E, 0xC34B, 0x992F, 0xEF51, 0x9930, 0xEF54,
+ 0x9931, 0xEF53, 0x9932, 0xEF50, 0x9933, 0xEF4F, 0x9935, 0xC1FD, 0x993A, 0xF1AE, 0x993C, 0xF1AD, 0x993D, 0xC34A, 0x993E, 0xC348,
+ 0x993F, 0xC349, 0x9941, 0xF1AC, 0x9943, 0xF3B1, 0x9945, 0xC443, 0x9947, 0xF3B0, 0x9948, 0xF3AF, 0x9949, 0xC444, 0x994B, 0xF558,
+ 0x994C, 0xF557, 0x994E, 0xF555, 0x9950, 0xF554, 0x9951, 0xC4C8, 0x9952, 0xC4C7, 0x9953, 0xF559, 0x9954, 0xF776, 0x9955, 0xC5B9,
+ 0x9956, 0xF677, 0x9957, 0xC557, 0x9958, 0xF676, 0x9959, 0xF556, 0x995B, 0xF777, 0x995C, 0xC5E4, 0x995E, 0xC661, 0x995F, 0xF959,
+ 0x9961, 0xF9B1, 0x9996, 0xADBA, 0x9997, 0xD850, 0x9998, 0xEF55, 0x9999, 0xADBB, 0x999C, 0xE4D2, 0x999D, 0xE4D1, 0x999E, 0xEC60,
+ 0x99A1, 0xEF57, 0x99A3, 0xEF56, 0x99A5, 0xC34C, 0x99A6, 0xF3B2, 0x99A7, 0xF3B3, 0x99A8, 0xC4C9, 0x99AB, 0xF9B2, 0x99AC, 0xB0A8,
+ 0x99AD, 0xB6BF, 0x99AE, 0xB6BE, 0x99AF, 0xE0E4, 0x99B0, 0xE0E6, 0x99B1, 0xB9A4, 0x99B2, 0xE0E5, 0x99B3, 0xB9A3, 0x99B4, 0xB9A5,
+ 0x99B5, 0xE0E7, 0x99B9, 0xE4D4, 0x99BA, 0xE4D6, 0x99BB, 0xE4D5, 0x99BD, 0xE4D8, 0x99C1, 0xBBE9, 0x99C2, 0xE4D7, 0x99C3, 0xE4D3,
+ 0x99C7, 0xE4D9, 0x99C9, 0xE8CC, 0x99CB, 0xE8CF, 0x99CC, 0xE8D1, 0x99CD, 0xE8C7, 0x99CE, 0xE8CB, 0x99CF, 0xE8C8, 0x99D0, 0xBE6E,
+ 0x99D1, 0xBE71, 0x99D2, 0xBE73, 0x99D3, 0xE8C9, 0x99D4, 0xE8CA, 0x99D5, 0xBE72, 0x99D6, 0xE8CD, 0x99D7, 0xE8D0, 0x99D8, 0xE8CE,
+ 0x99D9, 0xBE74, 0x99DB, 0xBE70, 0x99DC, 0xE8C6, 0x99DD, 0xBE6D, 0x99DF, 0xBE6F, 0x99E2, 0xC063, 0x99E3, 0xEC66, 0x99E4, 0xEC64,
+ 0x99E5, 0xEC63, 0x99E7, 0xEC69, 0x99E9, 0xEC68, 0x99EA, 0xEC67, 0x99EC, 0xEC62, 0x99ED, 0xC062, 0x99EE, 0xEC61, 0x99F0, 0xEC65,
+ 0x99F1, 0xC064, 0x99F4, 0xEF5A, 0x99F6, 0xEF5E, 0x99F7, 0xEF5B, 0x99F8, 0xEF5D, 0x99F9, 0xEF5C, 0x99FA, 0xEF59, 0x99FB, 0xEF5F,
+ 0x99FC, 0xEF62, 0x99FD, 0xEF60, 0x99FE, 0xEF61, 0x99FF, 0xC240, 0x9A01, 0xC1FE, 0x9A02, 0xEF58, 0x9A03, 0xEF63, 0x9A04, 0xF1B3,
+ 0x9A05, 0xF1B6, 0x9A06, 0xF1B8, 0x9A07, 0xF1B7, 0x9A09, 0xF1B1, 0x9A0A, 0xF1B5, 0x9A0B, 0xF1B0, 0x9A0D, 0xF1B2, 0x9A0E, 0xC34D,
+ 0x9A0F, 0xF1AF, 0x9A11, 0xF1B4, 0x9A14, 0xF3C0, 0x9A15, 0xF3B5, 0x9A16, 0xC445, 0x9A19, 0xC446, 0x9A1A, 0xF3B4, 0x9A1B, 0xF3B9,
+ 0x9A1C, 0xF3BF, 0x9A1D, 0xF3B7, 0x9A1E, 0xF3BE, 0x9A20, 0xF3BB, 0x9A22, 0xF3BA, 0x9A23, 0xF3BD, 0x9A24, 0xF3B8, 0x9A25, 0xF3B6,
+ 0x9A27, 0xF3BC, 0x9A29, 0xF560, 0x9A2A, 0xF55E, 0x9A2B, 0xC4CA, 0x9A2C, 0xF55D, 0x9A2D, 0xF563, 0x9A2E, 0xF561, 0x9A30, 0xC4CB,
+ 0x9A31, 0xF55C, 0x9A32, 0xF55A, 0x9A34, 0xF55B, 0x9A35, 0xC4CD, 0x9A36, 0xF55F, 0x9A37, 0xC4CC, 0x9A38, 0xF562, 0x9A39, 0xF678,
+ 0x9A3A, 0xF67E, 0x9A3D, 0xF679, 0x9A3E, 0xC55B, 0x9A3F, 0xF6A1, 0x9A40, 0xC55A, 0x9A41, 0xF67D, 0x9A42, 0xF67C, 0x9A43, 0xC559,
+ 0x9A44, 0xF67B, 0x9A45, 0xC558, 0x9A46, 0xF67A, 0x9A48, 0xF77D, 0x9A49, 0xF7A1, 0x9A4A, 0xF77E, 0x9A4C, 0xF77B, 0x9A4D, 0xC5BB,
+ 0x9A4E, 0xF778, 0x9A4F, 0xF77C, 0x9A50, 0xF7A3, 0x9A52, 0xF7A2, 0x9A53, 0xF779, 0x9A54, 0xF77A, 0x9A55, 0xC5BA, 0x9A56, 0xF852,
+ 0x9A57, 0xC5E7, 0x9A59, 0xF853, 0x9A5A, 0xC5E5, 0x9A5B, 0xC5E6, 0x9A5E, 0xF8D3, 0x9A5F, 0xC64A, 0x9A60, 0xF976, 0x9A62, 0xC66A,
+ 0x9A64, 0xF9B3, 0x9A65, 0xC66B, 0x9A66, 0xF9B4, 0x9A67, 0xF9B5, 0x9A68, 0xF9C3, 0x9A69, 0xF9C2, 0x9A6A, 0xC67A, 0x9A6B, 0xF9CD,
+ 0x9AA8, 0xB0A9, 0x9AAB, 0xE0E9, 0x9AAD, 0xE0E8, 0x9AAF, 0xBBEA, 0x9AB0, 0xBBEB, 0x9AB1, 0xE4DA, 0x9AB3, 0xE8D2, 0x9AB4, 0xEC6C,
+ 0x9AB7, 0xBE75, 0x9AB8, 0xC065, 0x9AB9, 0xEC6A, 0x9ABB, 0xEC6D, 0x9ABC, 0xC066, 0x9ABE, 0xEF64, 0x9ABF, 0xEC6B, 0x9AC0, 0xF1B9,
+ 0x9AC1, 0xC34E, 0x9AC2, 0xF3C1, 0x9AC6, 0xF566, 0x9AC7, 0xF564, 0x9ACA, 0xF565, 0x9ACD, 0xF6A2, 0x9ACF, 0xC55C, 0x9AD0, 0xF7A4,
+ 0x9AD1, 0xC5EA, 0x9AD2, 0xC5BC, 0x9AD3, 0xC5E8, 0x9AD4, 0xC5E9, 0x9AD5, 0xF8D4, 0x9AD6, 0xC662, 0x9AD8, 0xB0AA, 0x9ADC, 0xF1BA,
+ 0x9ADF, 0xD449, 0x9AE1, 0xB9A6, 0x9AE3, 0xE4DB, 0x9AE6, 0xBBEC, 0x9AE7, 0xE4DC, 0x9AEB, 0xE8D4, 0x9AEC, 0xE8D3, 0x9AED, 0xC068,
+ 0x9AEE, 0xBE76, 0x9AEF, 0xBE77, 0x9AF1, 0xE8D7, 0x9AF2, 0xE8D6, 0x9AF3, 0xE8D5, 0x9AF6, 0xEC6E, 0x9AF7, 0xEC71, 0x9AF9, 0xEC70,
+ 0x9AFA, 0xEC6F, 0x9AFB, 0xC067, 0x9AFC, 0xEF68, 0x9AFD, 0xEF66, 0x9AFE, 0xEF65, 0x9B01, 0xEF67, 0x9B03, 0xC34F, 0x9B04, 0xF1BC,
+ 0x9B05, 0xF1BD, 0x9B06, 0xC350, 0x9B08, 0xF1BB, 0x9B0A, 0xF3C3, 0x9B0B, 0xF3C2, 0x9B0C, 0xF3C5, 0x9B0D, 0xC447, 0x9B0E, 0xF3C4,
+ 0x9B10, 0xF567, 0x9B11, 0xF569, 0x9B12, 0xF568, 0x9B15, 0xF6A3, 0x9B16, 0xF6A6, 0x9B17, 0xF6A4, 0x9B18, 0xF6A5, 0x9B19, 0xF7A5,
+ 0x9B1A, 0xC5BD, 0x9B1E, 0xF854, 0x9B1F, 0xF855, 0x9B20, 0xF856, 0x9B22, 0xC64B, 0x9B23, 0xC663, 0x9B24, 0xF9B6, 0x9B25, 0xB0AB,
+ 0x9B27, 0xBE78, 0x9B28, 0xC069, 0x9B29, 0xF1BE, 0x9B2B, 0xF7A6, 0x9B2E, 0xF9C4, 0x9B2F, 0xD44A, 0x9B31, 0xC67B, 0x9B32, 0xB0AC,
+ 0x9B33, 0xEC72, 0x9B35, 0xF1BF, 0x9B37, 0xF3C6, 0x9B3A, 0xF6A7, 0x9B3B, 0xF7A7, 0x9B3C, 0xB0AD, 0x9B3E, 0xE4DD, 0x9B3F, 0xE4DE,
+ 0x9B41, 0xBBED, 0x9B42, 0xBBEE, 0x9B43, 0xE8D9, 0x9B44, 0xBE7A, 0x9B45, 0xBE79, 0x9B46, 0xE8D8, 0x9B48, 0xEF69, 0x9B4A, 0xF1C0,
+ 0x9B4B, 0xF1C2, 0x9B4C, 0xF1C1, 0x9B4D, 0xC353, 0x9B4E, 0xC352, 0x9B4F, 0xC351, 0x9B51, 0xC55E, 0x9B52, 0xF6A8, 0x9B54, 0xC55D,
+ 0x9B55, 0xF7A9, 0x9B56, 0xF7A8, 0x9B58, 0xC64C, 0x9B59, 0xF8D5, 0x9B5A, 0xB3BD, 0x9B5B, 0xE0EA, 0x9B5F, 0xE4E1, 0x9B60, 0xE4DF,
+ 0x9B61, 0xE4E0, 0x9B64, 0xE8E2, 0x9B66, 0xE8DD, 0x9B67, 0xE8DA, 0x9B68, 0xE8E1, 0x9B6C, 0xE8E3, 0x9B6F, 0xBE7C, 0x9B70, 0xE8E0,
+ 0x9B71, 0xE8DC, 0x9B74, 0xE8DB, 0x9B75, 0xE8DF, 0x9B76, 0xE8DE, 0x9B77, 0xBE7B, 0x9B7A, 0xEC7D, 0x9B7B, 0xEC78, 0x9B7C, 0xEC76,
+ 0x9B7D, 0xECA1, 0x9B7E, 0xEC77, 0x9B80, 0xEC73, 0x9B82, 0xEC79, 0x9B85, 0xEC74, 0x9B86, 0xEF72, 0x9B87, 0xEC75, 0x9B88, 0xECA2,
+ 0x9B90, 0xEC7C, 0x9B91, 0xC06A, 0x9B92, 0xEC7B, 0x9B93, 0xEC7A, 0x9B95, 0xEC7E, 0x9B9A, 0xEF6A, 0x9B9B, 0xEF6D, 0x9B9E, 0xEF6C,
+ 0x9BA0, 0xEF74, 0x9BA1, 0xEF6F, 0x9BA2, 0xEF73, 0x9BA4, 0xEF71, 0x9BA5, 0xEF70, 0x9BA6, 0xEF6E, 0x9BA8, 0xEF6B, 0x9BAA, 0xC243,
+ 0x9BAB, 0xC242, 0x9BAD, 0xC244, 0x9BAE, 0xC241, 0x9BAF, 0xEF75, 0x9BB5, 0xF1C8, 0x9BB6, 0xF1CB, 0x9BB8, 0xF1C9, 0x9BB9, 0xF1CD,
+ 0x9BBD, 0xF1CE, 0x9BBF, 0xF1C6, 0x9BC0, 0xC358, 0x9BC1, 0xF1C7, 0x9BC3, 0xF1C5, 0x9BC4, 0xF1CC, 0x9BC6, 0xF1C4, 0x9BC7, 0xF1C3,
+ 0x9BC8, 0xC357, 0x9BC9, 0xC355, 0x9BCA, 0xC354, 0x9BD3, 0xF1CA, 0x9BD4, 0xF3CF, 0x9BD5, 0xF3D5, 0x9BD6, 0xC44A, 0x9BD7, 0xF3D0,
+ 0x9BD9, 0xF3D3, 0x9BDA, 0xF3D7, 0x9BDB, 0xC44B, 0x9BDC, 0xF3D2, 0x9BDE, 0xF3CA, 0x9BE0, 0xF3C9, 0x9BE1, 0xF3D6, 0x9BE2, 0xF3CD,
+ 0x9BE4, 0xF3CB, 0x9BE5, 0xF3D4, 0x9BE6, 0xF3CC, 0x9BE7, 0xC449, 0x9BE8, 0xC448, 0x9BEA, 0xF3C7, 0x9BEB, 0xF3C8, 0x9BEC, 0xF3D1,
+ 0x9BF0, 0xF3CE, 0x9BF7, 0xF56C, 0x9BF8, 0xF56F, 0x9BFD, 0xC356, 0x9C05, 0xF56D, 0x9C06, 0xF573, 0x9C07, 0xF571, 0x9C08, 0xF56B,
+ 0x9C09, 0xF576, 0x9C0B, 0xF56A, 0x9C0D, 0xC4CF, 0x9C0E, 0xF572, 0x9C12, 0xF56E, 0x9C13, 0xC4CE, 0x9C14, 0xF575, 0x9C17, 0xF574,
+ 0x9C1C, 0xF6AB, 0x9C1D, 0xF6AA, 0x9C21, 0xF6B1, 0x9C23, 0xF6AD, 0x9C24, 0xF6B0, 0x9C25, 0xC560, 0x9C28, 0xF6AE, 0x9C29, 0xF6AF,
+ 0x9C2B, 0xF6A9, 0x9C2C, 0xF6AC, 0x9C2D, 0xC55F, 0x9C31, 0xC5BF, 0x9C32, 0xF7B4, 0x9C33, 0xF7AF, 0x9C34, 0xF7B3, 0x9C36, 0xF7B6,
+ 0x9C37, 0xF7B2, 0x9C39, 0xF7AE, 0x9C3B, 0xC5C1, 0x9C3C, 0xF7B1, 0x9C3D, 0xF7B5, 0x9C3E, 0xC5C0, 0x9C3F, 0xF7AC, 0x9C40, 0xF570,
+ 0x9C41, 0xF7B0, 0x9C44, 0xF7AD, 0x9C46, 0xF7AA, 0x9C48, 0xF7AB, 0x9C49, 0xC5BE, 0x9C4A, 0xF85A, 0x9C4B, 0xF85C, 0x9C4C, 0xF85F,
+ 0x9C4D, 0xF85B, 0x9C4E, 0xF860, 0x9C50, 0xF859, 0x9C52, 0xF857, 0x9C54, 0xC5EB, 0x9C55, 0xF85D, 0x9C56, 0xC5ED, 0x9C57, 0xC5EC,
+ 0x9C58, 0xF858, 0x9C59, 0xF85E, 0x9C5E, 0xF8DA, 0x9C5F, 0xC64D, 0x9C60, 0xF8DB, 0x9C62, 0xF8D9, 0x9C63, 0xF8D6, 0x9C66, 0xF8D8,
+ 0x9C67, 0xF8D7, 0x9C68, 0xF95A, 0x9C6D, 0xF95C, 0x9C6E, 0xF95B, 0x9C71, 0xF979, 0x9C73, 0xF978, 0x9C74, 0xF977, 0x9C75, 0xF97A,
+ 0x9C77, 0xC673, 0x9C78, 0xC674, 0x9C79, 0xF9CA, 0x9C7A, 0xF9CE, 0x9CE5, 0xB3BE, 0x9CE6, 0xDCAF, 0x9CE7, 0xE0ED, 0x9CE9, 0xB9A7,
+ 0x9CEA, 0xE0EB, 0x9CED, 0xE0EC, 0x9CF1, 0xE4E2, 0x9CF2, 0xE4E3, 0x9CF3, 0xBBF1, 0x9CF4, 0xBBEF, 0x9CF5, 0xE4E4, 0x9CF6, 0xBBF0,
+ 0x9CF7, 0xE8E8, 0x9CF9, 0xE8EB, 0x9CFA, 0xE8E5, 0x9CFB, 0xE8EC, 0x9CFC, 0xE8E4, 0x9CFD, 0xE8E6, 0x9CFF, 0xE8E7, 0x9D00, 0xE8EA,
+ 0x9D03, 0xBEA1, 0x9D04, 0xE8EF, 0x9D05, 0xE8EE, 0x9D06, 0xBE7D, 0x9D07, 0xE8E9, 0x9D08, 0xE8ED, 0x9D09, 0xBE7E, 0x9D10, 0xECAC,
+ 0x9D12, 0xC06F, 0x9D14, 0xECA7, 0x9D15, 0xC06B, 0x9D17, 0xECA4, 0x9D18, 0xECAA, 0x9D19, 0xECAD, 0x9D1B, 0xC070, 0x9D1D, 0xECA9,
+ 0x9D1E, 0xECA6, 0x9D1F, 0xECAE, 0x9D20, 0xECA5, 0x9D22, 0xECAB, 0x9D23, 0xC06C, 0x9D25, 0xECA3, 0x9D26, 0xC06D, 0x9D28, 0xC06E,
+ 0x9D29, 0xECA8, 0x9D2D, 0xEFA9, 0x9D2E, 0xEF7A, 0x9D2F, 0xEF7B, 0x9D30, 0xEF7E, 0x9D31, 0xEF7C, 0x9D33, 0xEF76, 0x9D36, 0xEF79,
+ 0x9D37, 0xEFA5, 0x9D38, 0xEF7D, 0x9D3B, 0xC245, 0x9D3D, 0xEFA7, 0x9D3E, 0xEFA4, 0x9D3F, 0xC246, 0x9D40, 0xEFA6, 0x9D41, 0xEF77,
+ 0x9D42, 0xEFA2, 0x9D43, 0xEFA3, 0x9D45, 0xEFA1, 0x9D4A, 0xF1D2, 0x9D4B, 0xF1D4, 0x9D4C, 0xF1D7, 0x9D4F, 0xF1D1, 0x9D51, 0xC359,
+ 0x9D52, 0xF1D9, 0x9D53, 0xF1D0, 0x9D54, 0xF1DA, 0x9D56, 0xF1D6, 0x9D57, 0xF1D8, 0x9D58, 0xF1DC, 0x9D59, 0xF1D5, 0x9D5A, 0xF1DD,
+ 0x9D5B, 0xF1D3, 0x9D5C, 0xF1CF, 0x9D5D, 0xC35A, 0x9D5F, 0xF1DB, 0x9D60, 0xC35B, 0x9D61, 0xC44D, 0x9D67, 0xEF78, 0x9D68, 0xF3F1,
+ 0x9D69, 0xF3E8, 0x9D6A, 0xC44F, 0x9D6B, 0xF3E4, 0x9D6C, 0xC450, 0x9D6F, 0xF3ED, 0x9D70, 0xF3E7, 0x9D71, 0xF3DD, 0x9D72, 0xC44E,
+ 0x9D73, 0xF3EA, 0x9D74, 0xF3E5, 0x9D75, 0xF3E6, 0x9D77, 0xF3D8, 0x9D78, 0xF3DF, 0x9D79, 0xF3EE, 0x9D7B, 0xF3EB, 0x9D7D, 0xF3E3,
+ 0x9D7F, 0xF3EF, 0x9D80, 0xF3DE, 0x9D81, 0xF3D9, 0x9D82, 0xF3EC, 0x9D84, 0xF3DB, 0x9D85, 0xF3E9, 0x9D86, 0xF3E0, 0x9D87, 0xF3F0,
+ 0x9D88, 0xF3DC, 0x9D89, 0xC44C, 0x9D8A, 0xF3DA, 0x9D8B, 0xF3E1, 0x9D8C, 0xF3E2, 0x9D90, 0xF57D, 0x9D92, 0xF57B, 0x9D94, 0xF5A2,
+ 0x9D96, 0xF5AE, 0x9D97, 0xF5A5, 0x9D98, 0xF57C, 0x9D99, 0xF578, 0x9D9A, 0xF5A7, 0x9D9B, 0xF57E, 0x9D9C, 0xF5A3, 0x9D9D, 0xF57A,
+ 0x9D9E, 0xF5AA, 0x9D9F, 0xF577, 0x9DA0, 0xF5A1, 0x9DA1, 0xF5A6, 0x9DA2, 0xF5A8, 0x9DA3, 0xF5AB, 0x9DA4, 0xF579, 0x9DA6, 0xF5AF,
+ 0x9DA7, 0xF5B0, 0x9DA8, 0xF5A9, 0x9DA9, 0xF5AD, 0x9DAA, 0xF5A4, 0x9DAC, 0xF6C1, 0x9DAD, 0xF6C4, 0x9DAF, 0xC561, 0x9DB1, 0xF6C3,
+ 0x9DB2, 0xF6C8, 0x9DB3, 0xF6C6, 0x9DB4, 0xC562, 0x9DB5, 0xF6BD, 0x9DB6, 0xF6B3, 0x9DB7, 0xF6B2, 0x9DB8, 0xC564, 0x9DB9, 0xF6BF,
+ 0x9DBA, 0xF6C0, 0x9DBB, 0xF6BC, 0x9DBC, 0xF6B4, 0x9DBE, 0xF6B9, 0x9DBF, 0xF5AC, 0x9DC1, 0xF6B5, 0x9DC2, 0xC563, 0x9DC3, 0xF6BB,
+ 0x9DC5, 0xF6BA, 0x9DC7, 0xF6B6, 0x9DC8, 0xF6C2, 0x9DCA, 0xF6B7, 0x9DCB, 0xF7BB, 0x9DCC, 0xF6C5, 0x9DCD, 0xF6C7, 0x9DCE, 0xF6BE,
+ 0x9DCF, 0xF6B8, 0x9DD0, 0xF7BC, 0x9DD1, 0xF7BE, 0x9DD2, 0xF7B8, 0x9DD3, 0xC5C2, 0x9DD5, 0xF7C5, 0x9DD6, 0xF7C3, 0x9DD7, 0xC5C3,
+ 0x9DD8, 0xF7C2, 0x9DD9, 0xF7C1, 0x9DDA, 0xF7BA, 0x9DDB, 0xF7B7, 0x9DDC, 0xF7BD, 0x9DDD, 0xF7C6, 0x9DDE, 0xF7B9, 0x9DDF, 0xF7BF,
+ 0x9DE1, 0xF869, 0x9DE2, 0xF86E, 0x9DE3, 0xF864, 0x9DE4, 0xF867, 0x9DE5, 0xC5EE, 0x9DE6, 0xF86B, 0x9DE8, 0xF872, 0x9DE9, 0xF7C0,
+ 0x9DEB, 0xF865, 0x9DEC, 0xF86F, 0x9DED, 0xF873, 0x9DEE, 0xF86A, 0x9DEF, 0xF863, 0x9DF0, 0xF86D, 0x9DF2, 0xF86C, 0x9DF3, 0xF871,
+ 0x9DF4, 0xF870, 0x9DF5, 0xF7C4, 0x9DF6, 0xF868, 0x9DF7, 0xF862, 0x9DF8, 0xF866, 0x9DF9, 0xC64E, 0x9DFA, 0xC64F, 0x9DFB, 0xF861,
+ 0x9DFD, 0xF8E6, 0x9DFE, 0xF8DD, 0x9DFF, 0xF8E5, 0x9E00, 0xF8E2, 0x9E01, 0xF8E3, 0x9E02, 0xF8DC, 0x9E03, 0xF8DF, 0x9E04, 0xF8E7,
+ 0x9E05, 0xF8E1, 0x9E06, 0xF8E0, 0x9E07, 0xF8DE, 0x9E09, 0xF8E4, 0x9E0B, 0xF95D, 0x9E0D, 0xF95E, 0x9E0F, 0xF960, 0x9E10, 0xF95F,
+ 0x9E11, 0xF962, 0x9E12, 0xF961, 0x9E13, 0xF97C, 0x9E14, 0xF97B, 0x9E15, 0xF9B7, 0x9E17, 0xF9B8, 0x9E19, 0xF9C5, 0x9E1A, 0xC678,
+ 0x9E1B, 0xC67C, 0x9E1D, 0xF9CF, 0x9E1E, 0xC67D, 0x9E75, 0xB3BF, 0x9E79, 0xC4D0, 0x9E7A, 0xF6C9, 0x9E7C, 0xC650, 0x9E7D, 0xC651,
+ 0x9E7F, 0xB3C0, 0x9E80, 0xE0EE, 0x9E82, 0xB9A8, 0x9E83, 0xE8F0, 0x9E86, 0xECB0, 0x9E87, 0xECB1, 0x9E88, 0xECAF, 0x9E89, 0xEFAB,
+ 0x9E8A, 0xEFAA, 0x9E8B, 0xC247, 0x9E8C, 0xF1DF, 0x9E8D, 0xEFAC, 0x9E8E, 0xF1DE, 0x9E91, 0xF3F3, 0x9E92, 0xC451, 0x9E93, 0xC453,
+ 0x9E94, 0xF3F2, 0x9E97, 0xC452, 0x9E99, 0xF5B1, 0x9E9A, 0xF5B3, 0x9E9B, 0xF5B2, 0x9E9C, 0xF6CA, 0x9E9D, 0xC565, 0x9E9F, 0xC5EF,
+ 0x9EA0, 0xF8E8, 0x9EA1, 0xF963, 0x9EA4, 0xF9D2, 0x9EA5, 0xB3C1, 0x9EA7, 0xE4E5, 0x9EA9, 0xBEA2, 0x9EAD, 0xECB3, 0x9EAE, 0xECB2,
+ 0x9EB0, 0xEFAD, 0x9EB4, 0xC454, 0x9EB5, 0xC4D1, 0x9EB6, 0xF7C7, 0x9EB7, 0xF9CB, 0x9EBB, 0xB3C2, 0x9EBC, 0xBBF2, 0x9EBE, 0xBEA3,
+ 0x9EC0, 0xF3F4, 0x9EC2, 0xF874, 0x9EC3, 0xB6C0, 0x9EC8, 0xEFAE, 0x9ECC, 0xC664, 0x9ECD, 0xB6C1, 0x9ECE, 0xBEA4, 0x9ECF, 0xC248,
+ 0x9ED0, 0xF875, 0x9ED1, 0xB6C2, 0x9ED3, 0xE8F1, 0x9ED4, 0xC072, 0x9ED5, 0xECB4, 0x9ED6, 0xECB5, 0x9ED8, 0xC071, 0x9EDA, 0xEFAF,
+ 0x9EDB, 0xC24C, 0x9EDC, 0xC24A, 0x9EDD, 0xC24B, 0x9EDE, 0xC249, 0x9EDF, 0xF1E0, 0x9EE0, 0xC35C, 0x9EE4, 0xF5B5, 0x9EE5, 0xF5B4,
+ 0x9EE6, 0xF5B7, 0x9EE7, 0xF5B6, 0x9EE8, 0xC4D2, 0x9EEB, 0xF6CB, 0x9EED, 0xF6CD, 0x9EEE, 0xF6CC, 0x9EEF, 0xC566, 0x9EF0, 0xF7C8,
+ 0x9EF2, 0xF876, 0x9EF3, 0xF877, 0x9EF4, 0xC5F0, 0x9EF5, 0xF964, 0x9EF6, 0xF97D, 0x9EF7, 0xC675, 0x9EF9, 0xDCB0, 0x9EFA, 0xECB6,
+ 0x9EFB, 0xEFB0, 0x9EFC, 0xF3F5, 0x9EFD, 0xE0EF, 0x9EFF, 0xEFB1, 0x9F00, 0xF1E2, 0x9F01, 0xF1E1, 0x9F06, 0xF878, 0x9F07, 0xC652,
+ 0x9F09, 0xF965, 0x9F0A, 0xF97E, 0x9F0E, 0xB9A9, 0x9F0F, 0xE8F2, 0x9F10, 0xE8F3, 0x9F12, 0xECB7, 0x9F13, 0xB9AA, 0x9F15, 0xC35D,
+ 0x9F16, 0xF1E3, 0x9F18, 0xF6CF, 0x9F19, 0xC567, 0x9F1A, 0xF6D0, 0x9F1B, 0xF6CE, 0x9F1C, 0xF879, 0x9F1E, 0xF8E9, 0x9F20, 0xB9AB,
+ 0x9F22, 0xEFB4, 0x9F23, 0xEFB3, 0x9F24, 0xEFB2, 0x9F25, 0xF1E4, 0x9F28, 0xF1E8, 0x9F29, 0xF1E7, 0x9F2A, 0xF1E6, 0x9F2B, 0xF1E5,
+ 0x9F2C, 0xC35E, 0x9F2D, 0xF3F6, 0x9F2E, 0xF5B9, 0x9F2F, 0xC4D3, 0x9F30, 0xF5B8, 0x9F31, 0xF6D1, 0x9F32, 0xF7CB, 0x9F33, 0xF7CA,
+ 0x9F34, 0xC5C4, 0x9F35, 0xF7C9, 0x9F36, 0xF87C, 0x9F37, 0xF87B, 0x9F38, 0xF87A, 0x9F3B, 0xBBF3, 0x9F3D, 0xECB8, 0x9F3E, 0xC24D,
+ 0x9F40, 0xF3F7, 0x9F41, 0xF3F8, 0x9F42, 0xF7CC, 0x9F43, 0xF87D, 0x9F46, 0xF8EA, 0x9F47, 0xF966, 0x9F48, 0xF9B9, 0x9F49, 0xF9D4,
+ 0x9F4A, 0xBBF4, 0x9F4B, 0xC24E, 0x9F4C, 0xF1E9, 0x9F4D, 0xF3F9, 0x9F4E, 0xF6D2, 0x9F4F, 0xF87E, 0x9F52, 0xBEA6, 0x9F54, 0xEFB5,
+ 0x9F55, 0xF1EA, 0x9F56, 0xF3FA, 0x9F57, 0xF3FB, 0x9F58, 0xF3FC, 0x9F59, 0xF5BE, 0x9F5B, 0xF5BA, 0x9F5C, 0xC568, 0x9F5D, 0xF5BD,
+ 0x9F5E, 0xF5BC, 0x9F5F, 0xC4D4, 0x9F60, 0xF5BB, 0x9F61, 0xC4D6, 0x9F63, 0xC4D5, 0x9F64, 0xF6D4, 0x9F65, 0xF6D3, 0x9F66, 0xC569,
+ 0x9F67, 0xC56A, 0x9F6A, 0xC5C6, 0x9F6B, 0xF7CD, 0x9F6C, 0xC5C5, 0x9F6E, 0xF8A3, 0x9F6F, 0xF8A4, 0x9F70, 0xF8A2, 0x9F71, 0xF8A1,
+ 0x9F72, 0xC654, 0x9F74, 0xF8EB, 0x9F75, 0xF8EC, 0x9F76, 0xF8ED, 0x9F77, 0xC653, 0x9F78, 0xF967, 0x9F79, 0xF96A, 0x9F7A, 0xF969,
+ 0x9F7B, 0xF968, 0x9F7E, 0xF9D3, 0x9F8D, 0xC073, 0x9F90, 0xC365, 0x9F91, 0xF5BF, 0x9F92, 0xF6D5, 0x9F94, 0xC5C7, 0x9F95, 0xF7CE,
+ 0x9F98, 0xF9D5, 0x9F9C, 0xC074, 0x9FA0, 0xEFB6, 0x9FA2, 0xF7CF, 0x9FA4, 0xF9A1, 0xFA0C, 0xC94A, 0xFA0D, 0xDDFC, 0xFE30, 0xA14A,
+ 0xFE31, 0xA157, 0xFE33, 0xA159, 0xFE34, 0xA15B, 0xFE35, 0xA15F, 0xFE36, 0xA160, 0xFE37, 0xA163, 0xFE38, 0xA164, 0xFE39, 0xA167,
+ 0xFE3A, 0xA168, 0xFE3B, 0xA16B, 0xFE3C, 0xA16C, 0xFE3D, 0xA16F, 0xFE3E, 0xA170, 0xFE3F, 0xA173, 0xFE40, 0xA174, 0xFE41, 0xA177,
+ 0xFE42, 0xA178, 0xFE43, 0xA17B, 0xFE44, 0xA17C, 0xFE49, 0xA1C6, 0xFE4A, 0xA1C7, 0xFE4B, 0xA1CA, 0xFE4C, 0xA1CB, 0xFE4D, 0xA1C8,
+ 0xFE4E, 0xA1C9, 0xFE4F, 0xA15C, 0xFE50, 0xA14D, 0xFE51, 0xA14E, 0xFE52, 0xA14F, 0xFE54, 0xA151, 0xFE55, 0xA152, 0xFE56, 0xA153,
+ 0xFE57, 0xA154, 0xFE59, 0xA17D, 0xFE5A, 0xA17E, 0xFE5B, 0xA1A1, 0xFE5C, 0xA1A2, 0xFE5D, 0xA1A3, 0xFE5E, 0xA1A4, 0xFE5F, 0xA1CC,
+ 0xFE60, 0xA1CD, 0xFE61, 0xA1CE, 0xFE62, 0xA1DE, 0xFE63, 0xA1DF, 0xFE64, 0xA1E0, 0xFE65, 0xA1E1, 0xFE66, 0xA1E2, 0xFE68, 0xA242,
+ 0xFE69, 0xA24C, 0xFE6A, 0xA24D, 0xFE6B, 0xA24E, 0xFF01, 0xA149, 0xFF03, 0xA1AD, 0xFF04, 0xA243, 0xFF05, 0xA248, 0xFF06, 0xA1AE,
+ 0xFF08, 0xA15D, 0xFF09, 0xA15E, 0xFF0A, 0xA1AF, 0xFF0B, 0xA1CF, 0xFF0C, 0xA141, 0xFF0D, 0xA1D0, 0xFF0E, 0xA144, 0xFF0F, 0xA1FE,
+ 0xFF10, 0xA2AF, 0xFF11, 0xA2B0, 0xFF12, 0xA2B1, 0xFF13, 0xA2B2, 0xFF14, 0xA2B3, 0xFF15, 0xA2B4, 0xFF16, 0xA2B5, 0xFF17, 0xA2B6,
+ 0xFF18, 0xA2B7, 0xFF19, 0xA2B8, 0xFF1A, 0xA147, 0xFF1B, 0xA146, 0xFF1C, 0xA1D5, 0xFF1D, 0xA1D7, 0xFF1E, 0xA1D6, 0xFF1F, 0xA148,
+ 0xFF20, 0xA249, 0xFF21, 0xA2CF, 0xFF22, 0xA2D0, 0xFF23, 0xA2D1, 0xFF24, 0xA2D2, 0xFF25, 0xA2D3, 0xFF26, 0xA2D4, 0xFF27, 0xA2D5,
+ 0xFF28, 0xA2D6, 0xFF29, 0xA2D7, 0xFF2A, 0xA2D8, 0xFF2B, 0xA2D9, 0xFF2C, 0xA2DA, 0xFF2D, 0xA2DB, 0xFF2E, 0xA2DC, 0xFF2F, 0xA2DD,
+ 0xFF30, 0xA2DE, 0xFF31, 0xA2DF, 0xFF32, 0xA2E0, 0xFF33, 0xA2E1, 0xFF34, 0xA2E2, 0xFF35, 0xA2E3, 0xFF36, 0xA2E4, 0xFF37, 0xA2E5,
+ 0xFF38, 0xA2E6, 0xFF39, 0xA2E7, 0xFF3A, 0xA2E8, 0xFF3C, 0xA240, 0xFF3F, 0xA1C4, 0xFF41, 0xA2E9, 0xFF42, 0xA2EA, 0xFF43, 0xA2EB,
+ 0xFF44, 0xA2EC, 0xFF45, 0xA2ED, 0xFF46, 0xA2EE, 0xFF47, 0xA2EF, 0xFF48, 0xA2F0, 0xFF49, 0xA2F1, 0xFF4A, 0xA2F2, 0xFF4B, 0xA2F3,
+ 0xFF4C, 0xA2F4, 0xFF4D, 0xA2F5, 0xFF4E, 0xA2F6, 0xFF4F, 0xA2F7, 0xFF50, 0xA2F8, 0xFF51, 0xA2F9, 0xFF52, 0xA2FA, 0xFF53, 0xA2FB,
+ 0xFF54, 0xA2FC, 0xFF55, 0xA2FD, 0xFF56, 0xA2FE, 0xFF57, 0xA340, 0xFF58, 0xA341, 0xFF59, 0xA342, 0xFF5A, 0xA343, 0xFF5B, 0xA161,
+ 0xFF5C, 0xA155, 0xFF5D, 0xA162, 0xFF5E, 0xA1E3, 0xFFE0, 0xA246, 0xFFE1, 0xA247, 0xFFE3, 0xA1C3, 0xFFE5, 0xA244, 0, 0
+};
+
+static const WCHAR oem2uni950[] = { /* Big5 --> Unicode pairs */
+ 0xA140, 0x3000, 0xA141, 0xFF0C, 0xA142, 0x3001, 0xA143, 0x3002, 0xA144, 0xFF0E, 0xA145, 0x2027, 0xA146, 0xFF1B, 0xA147, 0xFF1A,
+ 0xA148, 0xFF1F, 0xA149, 0xFF01, 0xA14A, 0xFE30, 0xA14B, 0x2026, 0xA14C, 0x2025, 0xA14D, 0xFE50, 0xA14E, 0xFE51, 0xA14F, 0xFE52,
+ 0xA150, 0x00B7, 0xA151, 0xFE54, 0xA152, 0xFE55, 0xA153, 0xFE56, 0xA154, 0xFE57, 0xA155, 0xFF5C, 0xA156, 0x2013, 0xA157, 0xFE31,
+ 0xA158, 0x2014, 0xA159, 0xFE33, 0xA15A, 0x2574, 0xA15B, 0xFE34, 0xA15C, 0xFE4F, 0xA15D, 0xFF08, 0xA15E, 0xFF09, 0xA15F, 0xFE35,
+ 0xA160, 0xFE36, 0xA161, 0xFF5B, 0xA162, 0xFF5D, 0xA163, 0xFE37, 0xA164, 0xFE38, 0xA165, 0x3014, 0xA166, 0x3015, 0xA167, 0xFE39,
+ 0xA168, 0xFE3A, 0xA169, 0x3010, 0xA16A, 0x3011, 0xA16B, 0xFE3B, 0xA16C, 0xFE3C, 0xA16D, 0x300A, 0xA16E, 0x300B, 0xA16F, 0xFE3D,
+ 0xA170, 0xFE3E, 0xA171, 0x3008, 0xA172, 0x3009, 0xA173, 0xFE3F, 0xA174, 0xFE40, 0xA175, 0x300C, 0xA176, 0x300D, 0xA177, 0xFE41,
+ 0xA178, 0xFE42, 0xA179, 0x300E, 0xA17A, 0x300F, 0xA17B, 0xFE43, 0xA17C, 0xFE44, 0xA17D, 0xFE59, 0xA17E, 0xFE5A, 0xA1A1, 0xFE5B,
+ 0xA1A2, 0xFE5C, 0xA1A3, 0xFE5D, 0xA1A4, 0xFE5E, 0xA1A5, 0x2018, 0xA1A6, 0x2019, 0xA1A7, 0x201C, 0xA1A8, 0x201D, 0xA1A9, 0x301D,
+ 0xA1AA, 0x301E, 0xA1AB, 0x2035, 0xA1AC, 0x2032, 0xA1AD, 0xFF03, 0xA1AE, 0xFF06, 0xA1AF, 0xFF0A, 0xA1B0, 0x203B, 0xA1B1, 0x00A7,
+ 0xA1B2, 0x3003, 0xA1B3, 0x25CB, 0xA1B4, 0x25CF, 0xA1B5, 0x25B3, 0xA1B6, 0x25B2, 0xA1B7, 0x25CE, 0xA1B8, 0x2606, 0xA1B9, 0x2605,
+ 0xA1BA, 0x25C7, 0xA1BB, 0x25C6, 0xA1BC, 0x25A1, 0xA1BD, 0x25A0, 0xA1BE, 0x25BD, 0xA1BF, 0x25BC, 0xA1C0, 0x32A3, 0xA1C1, 0x2105,
+ 0xA1C2, 0x00AF, 0xA1C3, 0xFFE3, 0xA1C4, 0xFF3F, 0xA1C5, 0x02CD, 0xA1C6, 0xFE49, 0xA1C7, 0xFE4A, 0xA1C8, 0xFE4D, 0xA1C9, 0xFE4E,
+ 0xA1CA, 0xFE4B, 0xA1CB, 0xFE4C, 0xA1CC, 0xFE5F, 0xA1CD, 0xFE60, 0xA1CE, 0xFE61, 0xA1CF, 0xFF0B, 0xA1D0, 0xFF0D, 0xA1D1, 0x00D7,
+ 0xA1D2, 0x00F7, 0xA1D3, 0x00B1, 0xA1D4, 0x221A, 0xA1D5, 0xFF1C, 0xA1D6, 0xFF1E, 0xA1D7, 0xFF1D, 0xA1D8, 0x2266, 0xA1D9, 0x2267,
+ 0xA1DA, 0x2260, 0xA1DB, 0x221E, 0xA1DC, 0x2252, 0xA1DD, 0x2261, 0xA1DE, 0xFE62, 0xA1DF, 0xFE63, 0xA1E0, 0xFE64, 0xA1E1, 0xFE65,
+ 0xA1E2, 0xFE66, 0xA1E3, 0xFF5E, 0xA1E4, 0x2229, 0xA1E5, 0x222A, 0xA1E6, 0x22A5, 0xA1E7, 0x2220, 0xA1E8, 0x221F, 0xA1E9, 0x22BF,
+ 0xA1EA, 0x33D2, 0xA1EB, 0x33D1, 0xA1EC, 0x222B, 0xA1ED, 0x222E, 0xA1EE, 0x2235, 0xA1EF, 0x2234, 0xA1F0, 0x2640, 0xA1F1, 0x2642,
+ 0xA1F2, 0x2295, 0xA1F3, 0x2299, 0xA1F4, 0x2191, 0xA1F5, 0x2193, 0xA1F6, 0x2190, 0xA1F7, 0x2192, 0xA1F8, 0x2196, 0xA1F9, 0x2197,
+ 0xA1FA, 0x2199, 0xA1FB, 0x2198, 0xA1FC, 0x2225, 0xA1FD, 0x2223, 0xA1FE, 0xFF0F, 0xA240, 0xFF3C, 0xA241, 0x2215, 0xA242, 0xFE68,
+ 0xA243, 0xFF04, 0xA244, 0xFFE5, 0xA245, 0x3012, 0xA246, 0xFFE0, 0xA247, 0xFFE1, 0xA248, 0xFF05, 0xA249, 0xFF20, 0xA24A, 0x2103,
+ 0xA24B, 0x2109, 0xA24C, 0xFE69, 0xA24D, 0xFE6A, 0xA24E, 0xFE6B, 0xA24F, 0x33D5, 0xA250, 0x339C, 0xA251, 0x339D, 0xA252, 0x339E,
+ 0xA253, 0x33CE, 0xA254, 0x33A1, 0xA255, 0x338E, 0xA256, 0x338F, 0xA257, 0x33C4, 0xA258, 0x00B0, 0xA259, 0x5159, 0xA25A, 0x515B,
+ 0xA25B, 0x515E, 0xA25C, 0x515D, 0xA25D, 0x5161, 0xA25E, 0x5163, 0xA25F, 0x55E7, 0xA260, 0x74E9, 0xA261, 0x7CCE, 0xA262, 0x2581,
+ 0xA263, 0x2582, 0xA264, 0x2583, 0xA265, 0x2584, 0xA266, 0x2585, 0xA267, 0x2586, 0xA268, 0x2587, 0xA269, 0x2588, 0xA26A, 0x258F,
+ 0xA26B, 0x258E, 0xA26C, 0x258D, 0xA26D, 0x258C, 0xA26E, 0x258B, 0xA26F, 0x258A, 0xA270, 0x2589, 0xA271, 0x253C, 0xA272, 0x2534,
+ 0xA273, 0x252C, 0xA274, 0x2524, 0xA275, 0x251C, 0xA276, 0x2594, 0xA277, 0x2500, 0xA278, 0x2502, 0xA279, 0x2595, 0xA27A, 0x250C,
+ 0xA27B, 0x2510, 0xA27C, 0x2514, 0xA27D, 0x2518, 0xA27E, 0x256D, 0xA2A1, 0x256E, 0xA2A2, 0x2570, 0xA2A3, 0x256F, 0xA2A4, 0x2550,
+ 0xA2A5, 0x255E, 0xA2A6, 0x256A, 0xA2A7, 0x2561, 0xA2A8, 0x25E2, 0xA2A9, 0x25E3, 0xA2AA, 0x25E5, 0xA2AB, 0x25E4, 0xA2AC, 0x2571,
+ 0xA2AD, 0x2572, 0xA2AE, 0x2573, 0xA2AF, 0xFF10, 0xA2B0, 0xFF11, 0xA2B1, 0xFF12, 0xA2B2, 0xFF13, 0xA2B3, 0xFF14, 0xA2B4, 0xFF15,
+ 0xA2B5, 0xFF16, 0xA2B6, 0xFF17, 0xA2B7, 0xFF18, 0xA2B8, 0xFF19, 0xA2B9, 0x2160, 0xA2BA, 0x2161, 0xA2BB, 0x2162, 0xA2BC, 0x2163,
+ 0xA2BD, 0x2164, 0xA2BE, 0x2165, 0xA2BF, 0x2166, 0xA2C0, 0x2167, 0xA2C1, 0x2168, 0xA2C2, 0x2169, 0xA2C3, 0x3021, 0xA2C4, 0x3022,
+ 0xA2C5, 0x3023, 0xA2C6, 0x3024, 0xA2C7, 0x3025, 0xA2C8, 0x3026, 0xA2C9, 0x3027, 0xA2CA, 0x3028, 0xA2CB, 0x3029, 0xA2CC, 0x5341,
+ 0xA2CD, 0x5344, 0xA2CE, 0x5345, 0xA2CF, 0xFF21, 0xA2D0, 0xFF22, 0xA2D1, 0xFF23, 0xA2D2, 0xFF24, 0xA2D3, 0xFF25, 0xA2D4, 0xFF26,
+ 0xA2D5, 0xFF27, 0xA2D6, 0xFF28, 0xA2D7, 0xFF29, 0xA2D8, 0xFF2A, 0xA2D9, 0xFF2B, 0xA2DA, 0xFF2C, 0xA2DB, 0xFF2D, 0xA2DC, 0xFF2E,
+ 0xA2DD, 0xFF2F, 0xA2DE, 0xFF30, 0xA2DF, 0xFF31, 0xA2E0, 0xFF32, 0xA2E1, 0xFF33, 0xA2E2, 0xFF34, 0xA2E3, 0xFF35, 0xA2E4, 0xFF36,
+ 0xA2E5, 0xFF37, 0xA2E6, 0xFF38, 0xA2E7, 0xFF39, 0xA2E8, 0xFF3A, 0xA2E9, 0xFF41, 0xA2EA, 0xFF42, 0xA2EB, 0xFF43, 0xA2EC, 0xFF44,
+ 0xA2ED, 0xFF45, 0xA2EE, 0xFF46, 0xA2EF, 0xFF47, 0xA2F0, 0xFF48, 0xA2F1, 0xFF49, 0xA2F2, 0xFF4A, 0xA2F3, 0xFF4B, 0xA2F4, 0xFF4C,
+ 0xA2F5, 0xFF4D, 0xA2F6, 0xFF4E, 0xA2F7, 0xFF4F, 0xA2F8, 0xFF50, 0xA2F9, 0xFF51, 0xA2FA, 0xFF52, 0xA2FB, 0xFF53, 0xA2FC, 0xFF54,
+ 0xA2FD, 0xFF55, 0xA2FE, 0xFF56, 0xA340, 0xFF57, 0xA341, 0xFF58, 0xA342, 0xFF59, 0xA343, 0xFF5A, 0xA344, 0x0391, 0xA345, 0x0392,
+ 0xA346, 0x0393, 0xA347, 0x0394, 0xA348, 0x0395, 0xA349, 0x0396, 0xA34A, 0x0397, 0xA34B, 0x0398, 0xA34C, 0x0399, 0xA34D, 0x039A,
+ 0xA34E, 0x039B, 0xA34F, 0x039C, 0xA350, 0x039D, 0xA351, 0x039E, 0xA352, 0x039F, 0xA353, 0x03A0, 0xA354, 0x03A1, 0xA355, 0x03A3,
+ 0xA356, 0x03A4, 0xA357, 0x03A5, 0xA358, 0x03A6, 0xA359, 0x03A7, 0xA35A, 0x03A8, 0xA35B, 0x03A9, 0xA35C, 0x03B1, 0xA35D, 0x03B2,
+ 0xA35E, 0x03B3, 0xA35F, 0x03B4, 0xA360, 0x03B5, 0xA361, 0x03B6, 0xA362, 0x03B7, 0xA363, 0x03B8, 0xA364, 0x03B9, 0xA365, 0x03BA,
+ 0xA366, 0x03BB, 0xA367, 0x03BC, 0xA368, 0x03BD, 0xA369, 0x03BE, 0xA36A, 0x03BF, 0xA36B, 0x03C0, 0xA36C, 0x03C1, 0xA36D, 0x03C3,
+ 0xA36E, 0x03C4, 0xA36F, 0x03C5, 0xA370, 0x03C6, 0xA371, 0x03C7, 0xA372, 0x03C8, 0xA373, 0x03C9, 0xA374, 0x3105, 0xA375, 0x3106,
+ 0xA376, 0x3107, 0xA377, 0x3108, 0xA378, 0x3109, 0xA379, 0x310A, 0xA37A, 0x310B, 0xA37B, 0x310C, 0xA37C, 0x310D, 0xA37D, 0x310E,
+ 0xA37E, 0x310F, 0xA3A1, 0x3110, 0xA3A2, 0x3111, 0xA3A3, 0x3112, 0xA3A4, 0x3113, 0xA3A5, 0x3114, 0xA3A6, 0x3115, 0xA3A7, 0x3116,
+ 0xA3A8, 0x3117, 0xA3A9, 0x3118, 0xA3AA, 0x3119, 0xA3AB, 0x311A, 0xA3AC, 0x311B, 0xA3AD, 0x311C, 0xA3AE, 0x311D, 0xA3AF, 0x311E,
+ 0xA3B0, 0x311F, 0xA3B1, 0x3120, 0xA3B2, 0x3121, 0xA3B3, 0x3122, 0xA3B4, 0x3123, 0xA3B5, 0x3124, 0xA3B6, 0x3125, 0xA3B7, 0x3126,
+ 0xA3B8, 0x3127, 0xA3B9, 0x3128, 0xA3BA, 0x3129, 0xA3BB, 0x02D9, 0xA3BC, 0x02C9, 0xA3BD, 0x02CA, 0xA3BE, 0x02C7, 0xA3BF, 0x02CB,
+ 0xA3E1, 0x20AC, 0xA440, 0x4E00, 0xA441, 0x4E59, 0xA442, 0x4E01, 0xA443, 0x4E03, 0xA444, 0x4E43, 0xA445, 0x4E5D, 0xA446, 0x4E86,
+ 0xA447, 0x4E8C, 0xA448, 0x4EBA, 0xA449, 0x513F, 0xA44A, 0x5165, 0xA44B, 0x516B, 0xA44C, 0x51E0, 0xA44D, 0x5200, 0xA44E, 0x5201,
+ 0xA44F, 0x529B, 0xA450, 0x5315, 0xA451, 0x5341, 0xA452, 0x535C, 0xA453, 0x53C8, 0xA454, 0x4E09, 0xA455, 0x4E0B, 0xA456, 0x4E08,
+ 0xA457, 0x4E0A, 0xA458, 0x4E2B, 0xA459, 0x4E38, 0xA45A, 0x51E1, 0xA45B, 0x4E45, 0xA45C, 0x4E48, 0xA45D, 0x4E5F, 0xA45E, 0x4E5E,
+ 0xA45F, 0x4E8E, 0xA460, 0x4EA1, 0xA461, 0x5140, 0xA462, 0x5203, 0xA463, 0x52FA, 0xA464, 0x5343, 0xA465, 0x53C9, 0xA466, 0x53E3,
+ 0xA467, 0x571F, 0xA468, 0x58EB, 0xA469, 0x5915, 0xA46A, 0x5927, 0xA46B, 0x5973, 0xA46C, 0x5B50, 0xA46D, 0x5B51, 0xA46E, 0x5B53,
+ 0xA46F, 0x5BF8, 0xA470, 0x5C0F, 0xA471, 0x5C22, 0xA472, 0x5C38, 0xA473, 0x5C71, 0xA474, 0x5DDD, 0xA475, 0x5DE5, 0xA476, 0x5DF1,
+ 0xA477, 0x5DF2, 0xA478, 0x5DF3, 0xA479, 0x5DFE, 0xA47A, 0x5E72, 0xA47B, 0x5EFE, 0xA47C, 0x5F0B, 0xA47D, 0x5F13, 0xA47E, 0x624D,
+ 0xA4A1, 0x4E11, 0xA4A2, 0x4E10, 0xA4A3, 0x4E0D, 0xA4A4, 0x4E2D, 0xA4A5, 0x4E30, 0xA4A6, 0x4E39, 0xA4A7, 0x4E4B, 0xA4A8, 0x5C39,
+ 0xA4A9, 0x4E88, 0xA4AA, 0x4E91, 0xA4AB, 0x4E95, 0xA4AC, 0x4E92, 0xA4AD, 0x4E94, 0xA4AE, 0x4EA2, 0xA4AF, 0x4EC1, 0xA4B0, 0x4EC0,
+ 0xA4B1, 0x4EC3, 0xA4B2, 0x4EC6, 0xA4B3, 0x4EC7, 0xA4B4, 0x4ECD, 0xA4B5, 0x4ECA, 0xA4B6, 0x4ECB, 0xA4B7, 0x4EC4, 0xA4B8, 0x5143,
+ 0xA4B9, 0x5141, 0xA4BA, 0x5167, 0xA4BB, 0x516D, 0xA4BC, 0x516E, 0xA4BD, 0x516C, 0xA4BE, 0x5197, 0xA4BF, 0x51F6, 0xA4C0, 0x5206,
+ 0xA4C1, 0x5207, 0xA4C2, 0x5208, 0xA4C3, 0x52FB, 0xA4C4, 0x52FE, 0xA4C5, 0x52FF, 0xA4C6, 0x5316, 0xA4C7, 0x5339, 0xA4C8, 0x5348,
+ 0xA4C9, 0x5347, 0xA4CA, 0x5345, 0xA4CB, 0x535E, 0xA4CC, 0x5384, 0xA4CD, 0x53CB, 0xA4CE, 0x53CA, 0xA4CF, 0x53CD, 0xA4D0, 0x58EC,
+ 0xA4D1, 0x5929, 0xA4D2, 0x592B, 0xA4D3, 0x592A, 0xA4D4, 0x592D, 0xA4D5, 0x5B54, 0xA4D6, 0x5C11, 0xA4D7, 0x5C24, 0xA4D8, 0x5C3A,
+ 0xA4D9, 0x5C6F, 0xA4DA, 0x5DF4, 0xA4DB, 0x5E7B, 0xA4DC, 0x5EFF, 0xA4DD, 0x5F14, 0xA4DE, 0x5F15, 0xA4DF, 0x5FC3, 0xA4E0, 0x6208,
+ 0xA4E1, 0x6236, 0xA4E2, 0x624B, 0xA4E3, 0x624E, 0xA4E4, 0x652F, 0xA4E5, 0x6587, 0xA4E6, 0x6597, 0xA4E7, 0x65A4, 0xA4E8, 0x65B9,
+ 0xA4E9, 0x65E5, 0xA4EA, 0x66F0, 0xA4EB, 0x6708, 0xA4EC, 0x6728, 0xA4ED, 0x6B20, 0xA4EE, 0x6B62, 0xA4EF, 0x6B79, 0xA4F0, 0x6BCB,
+ 0xA4F1, 0x6BD4, 0xA4F2, 0x6BDB, 0xA4F3, 0x6C0F, 0xA4F4, 0x6C34, 0xA4F5, 0x706B, 0xA4F6, 0x722A, 0xA4F7, 0x7236, 0xA4F8, 0x723B,
+ 0xA4F9, 0x7247, 0xA4FA, 0x7259, 0xA4FB, 0x725B, 0xA4FC, 0x72AC, 0xA4FD, 0x738B, 0xA4FE, 0x4E19, 0xA540, 0x4E16, 0xA541, 0x4E15,
+ 0xA542, 0x4E14, 0xA543, 0x4E18, 0xA544, 0x4E3B, 0xA545, 0x4E4D, 0xA546, 0x4E4F, 0xA547, 0x4E4E, 0xA548, 0x4EE5, 0xA549, 0x4ED8,
+ 0xA54A, 0x4ED4, 0xA54B, 0x4ED5, 0xA54C, 0x4ED6, 0xA54D, 0x4ED7, 0xA54E, 0x4EE3, 0xA54F, 0x4EE4, 0xA550, 0x4ED9, 0xA551, 0x4EDE,
+ 0xA552, 0x5145, 0xA553, 0x5144, 0xA554, 0x5189, 0xA555, 0x518A, 0xA556, 0x51AC, 0xA557, 0x51F9, 0xA558, 0x51FA, 0xA559, 0x51F8,
+ 0xA55A, 0x520A, 0xA55B, 0x52A0, 0xA55C, 0x529F, 0xA55D, 0x5305, 0xA55E, 0x5306, 0xA55F, 0x5317, 0xA560, 0x531D, 0xA561, 0x4EDF,
+ 0xA562, 0x534A, 0xA563, 0x5349, 0xA564, 0x5361, 0xA565, 0x5360, 0xA566, 0x536F, 0xA567, 0x536E, 0xA568, 0x53BB, 0xA569, 0x53EF,
+ 0xA56A, 0x53E4, 0xA56B, 0x53F3, 0xA56C, 0x53EC, 0xA56D, 0x53EE, 0xA56E, 0x53E9, 0xA56F, 0x53E8, 0xA570, 0x53FC, 0xA571, 0x53F8,
+ 0xA572, 0x53F5, 0xA573, 0x53EB, 0xA574, 0x53E6, 0xA575, 0x53EA, 0xA576, 0x53F2, 0xA577, 0x53F1, 0xA578, 0x53F0, 0xA579, 0x53E5,
+ 0xA57A, 0x53ED, 0xA57B, 0x53FB, 0xA57C, 0x56DB, 0xA57D, 0x56DA, 0xA57E, 0x5916, 0xA5A1, 0x592E, 0xA5A2, 0x5931, 0xA5A3, 0x5974,
+ 0xA5A4, 0x5976, 0xA5A5, 0x5B55, 0xA5A6, 0x5B83, 0xA5A7, 0x5C3C, 0xA5A8, 0x5DE8, 0xA5A9, 0x5DE7, 0xA5AA, 0x5DE6, 0xA5AB, 0x5E02,
+ 0xA5AC, 0x5E03, 0xA5AD, 0x5E73, 0xA5AE, 0x5E7C, 0xA5AF, 0x5F01, 0xA5B0, 0x5F18, 0xA5B1, 0x5F17, 0xA5B2, 0x5FC5, 0xA5B3, 0x620A,
+ 0xA5B4, 0x6253, 0xA5B5, 0x6254, 0xA5B6, 0x6252, 0xA5B7, 0x6251, 0xA5B8, 0x65A5, 0xA5B9, 0x65E6, 0xA5BA, 0x672E, 0xA5BB, 0x672C,
+ 0xA5BC, 0x672A, 0xA5BD, 0x672B, 0xA5BE, 0x672D, 0xA5BF, 0x6B63, 0xA5C0, 0x6BCD, 0xA5C1, 0x6C11, 0xA5C2, 0x6C10, 0xA5C3, 0x6C38,
+ 0xA5C4, 0x6C41, 0xA5C5, 0x6C40, 0xA5C6, 0x6C3E, 0xA5C7, 0x72AF, 0xA5C8, 0x7384, 0xA5C9, 0x7389, 0xA5CA, 0x74DC, 0xA5CB, 0x74E6,
+ 0xA5CC, 0x7518, 0xA5CD, 0x751F, 0xA5CE, 0x7528, 0xA5CF, 0x7529, 0xA5D0, 0x7530, 0xA5D1, 0x7531, 0xA5D2, 0x7532, 0xA5D3, 0x7533,
+ 0xA5D4, 0x758B, 0xA5D5, 0x767D, 0xA5D6, 0x76AE, 0xA5D7, 0x76BF, 0xA5D8, 0x76EE, 0xA5D9, 0x77DB, 0xA5DA, 0x77E2, 0xA5DB, 0x77F3,
+ 0xA5DC, 0x793A, 0xA5DD, 0x79BE, 0xA5DE, 0x7A74, 0xA5DF, 0x7ACB, 0xA5E0, 0x4E1E, 0xA5E1, 0x4E1F, 0xA5E2, 0x4E52, 0xA5E3, 0x4E53,
+ 0xA5E4, 0x4E69, 0xA5E5, 0x4E99, 0xA5E6, 0x4EA4, 0xA5E7, 0x4EA6, 0xA5E8, 0x4EA5, 0xA5E9, 0x4EFF, 0xA5EA, 0x4F09, 0xA5EB, 0x4F19,
+ 0xA5EC, 0x4F0A, 0xA5ED, 0x4F15, 0xA5EE, 0x4F0D, 0xA5EF, 0x4F10, 0xA5F0, 0x4F11, 0xA5F1, 0x4F0F, 0xA5F2, 0x4EF2, 0xA5F3, 0x4EF6,
+ 0xA5F4, 0x4EFB, 0xA5F5, 0x4EF0, 0xA5F6, 0x4EF3, 0xA5F7, 0x4EFD, 0xA5F8, 0x4F01, 0xA5F9, 0x4F0B, 0xA5FA, 0x5149, 0xA5FB, 0x5147,
+ 0xA5FC, 0x5146, 0xA5FD, 0x5148, 0xA5FE, 0x5168, 0xA640, 0x5171, 0xA641, 0x518D, 0xA642, 0x51B0, 0xA643, 0x5217, 0xA644, 0x5211,
+ 0xA645, 0x5212, 0xA646, 0x520E, 0xA647, 0x5216, 0xA648, 0x52A3, 0xA649, 0x5308, 0xA64A, 0x5321, 0xA64B, 0x5320, 0xA64C, 0x5370,
+ 0xA64D, 0x5371, 0xA64E, 0x5409, 0xA64F, 0x540F, 0xA650, 0x540C, 0xA651, 0x540A, 0xA652, 0x5410, 0xA653, 0x5401, 0xA654, 0x540B,
+ 0xA655, 0x5404, 0xA656, 0x5411, 0xA657, 0x540D, 0xA658, 0x5408, 0xA659, 0x5403, 0xA65A, 0x540E, 0xA65B, 0x5406, 0xA65C, 0x5412,
+ 0xA65D, 0x56E0, 0xA65E, 0x56DE, 0xA65F, 0x56DD, 0xA660, 0x5733, 0xA661, 0x5730, 0xA662, 0x5728, 0xA663, 0x572D, 0xA664, 0x572C,
+ 0xA665, 0x572F, 0xA666, 0x5729, 0xA667, 0x5919, 0xA668, 0x591A, 0xA669, 0x5937, 0xA66A, 0x5938, 0xA66B, 0x5984, 0xA66C, 0x5978,
+ 0xA66D, 0x5983, 0xA66E, 0x597D, 0xA66F, 0x5979, 0xA670, 0x5982, 0xA671, 0x5981, 0xA672, 0x5B57, 0xA673, 0x5B58, 0xA674, 0x5B87,
+ 0xA675, 0x5B88, 0xA676, 0x5B85, 0xA677, 0x5B89, 0xA678, 0x5BFA, 0xA679, 0x5C16, 0xA67A, 0x5C79, 0xA67B, 0x5DDE, 0xA67C, 0x5E06,
+ 0xA67D, 0x5E76, 0xA67E, 0x5E74, 0xA6A1, 0x5F0F, 0xA6A2, 0x5F1B, 0xA6A3, 0x5FD9, 0xA6A4, 0x5FD6, 0xA6A5, 0x620E, 0xA6A6, 0x620C,
+ 0xA6A7, 0x620D, 0xA6A8, 0x6210, 0xA6A9, 0x6263, 0xA6AA, 0x625B, 0xA6AB, 0x6258, 0xA6AC, 0x6536, 0xA6AD, 0x65E9, 0xA6AE, 0x65E8,
+ 0xA6AF, 0x65EC, 0xA6B0, 0x65ED, 0xA6B1, 0x66F2, 0xA6B2, 0x66F3, 0xA6B3, 0x6709, 0xA6B4, 0x673D, 0xA6B5, 0x6734, 0xA6B6, 0x6731,
+ 0xA6B7, 0x6735, 0xA6B8, 0x6B21, 0xA6B9, 0x6B64, 0xA6BA, 0x6B7B, 0xA6BB, 0x6C16, 0xA6BC, 0x6C5D, 0xA6BD, 0x6C57, 0xA6BE, 0x6C59,
+ 0xA6BF, 0x6C5F, 0xA6C0, 0x6C60, 0xA6C1, 0x6C50, 0xA6C2, 0x6C55, 0xA6C3, 0x6C61, 0xA6C4, 0x6C5B, 0xA6C5, 0x6C4D, 0xA6C6, 0x6C4E,
+ 0xA6C7, 0x7070, 0xA6C8, 0x725F, 0xA6C9, 0x725D, 0xA6CA, 0x767E, 0xA6CB, 0x7AF9, 0xA6CC, 0x7C73, 0xA6CD, 0x7CF8, 0xA6CE, 0x7F36,
+ 0xA6CF, 0x7F8A, 0xA6D0, 0x7FBD, 0xA6D1, 0x8001, 0xA6D2, 0x8003, 0xA6D3, 0x800C, 0xA6D4, 0x8012, 0xA6D5, 0x8033, 0xA6D6, 0x807F,
+ 0xA6D7, 0x8089, 0xA6D8, 0x808B, 0xA6D9, 0x808C, 0xA6DA, 0x81E3, 0xA6DB, 0x81EA, 0xA6DC, 0x81F3, 0xA6DD, 0x81FC, 0xA6DE, 0x820C,
+ 0xA6DF, 0x821B, 0xA6E0, 0x821F, 0xA6E1, 0x826E, 0xA6E2, 0x8272, 0xA6E3, 0x827E, 0xA6E4, 0x866B, 0xA6E5, 0x8840, 0xA6E6, 0x884C,
+ 0xA6E7, 0x8863, 0xA6E8, 0x897F, 0xA6E9, 0x9621, 0xA6EA, 0x4E32, 0xA6EB, 0x4EA8, 0xA6EC, 0x4F4D, 0xA6ED, 0x4F4F, 0xA6EE, 0x4F47,
+ 0xA6EF, 0x4F57, 0xA6F0, 0x4F5E, 0xA6F1, 0x4F34, 0xA6F2, 0x4F5B, 0xA6F3, 0x4F55, 0xA6F4, 0x4F30, 0xA6F5, 0x4F50, 0xA6F6, 0x4F51,
+ 0xA6F7, 0x4F3D, 0xA6F8, 0x4F3A, 0xA6F9, 0x4F38, 0xA6FA, 0x4F43, 0xA6FB, 0x4F54, 0xA6FC, 0x4F3C, 0xA6FD, 0x4F46, 0xA6FE, 0x4F63,
+ 0xA740, 0x4F5C, 0xA741, 0x4F60, 0xA742, 0x4F2F, 0xA743, 0x4F4E, 0xA744, 0x4F36, 0xA745, 0x4F59, 0xA746, 0x4F5D, 0xA747, 0x4F48,
+ 0xA748, 0x4F5A, 0xA749, 0x514C, 0xA74A, 0x514B, 0xA74B, 0x514D, 0xA74C, 0x5175, 0xA74D, 0x51B6, 0xA74E, 0x51B7, 0xA74F, 0x5225,
+ 0xA750, 0x5224, 0xA751, 0x5229, 0xA752, 0x522A, 0xA753, 0x5228, 0xA754, 0x52AB, 0xA755, 0x52A9, 0xA756, 0x52AA, 0xA757, 0x52AC,
+ 0xA758, 0x5323, 0xA759, 0x5373, 0xA75A, 0x5375, 0xA75B, 0x541D, 0xA75C, 0x542D, 0xA75D, 0x541E, 0xA75E, 0x543E, 0xA75F, 0x5426,
+ 0xA760, 0x544E, 0xA761, 0x5427, 0xA762, 0x5446, 0xA763, 0x5443, 0xA764, 0x5433, 0xA765, 0x5448, 0xA766, 0x5442, 0xA767, 0x541B,
+ 0xA768, 0x5429, 0xA769, 0x544A, 0xA76A, 0x5439, 0xA76B, 0x543B, 0xA76C, 0x5438, 0xA76D, 0x542E, 0xA76E, 0x5435, 0xA76F, 0x5436,
+ 0xA770, 0x5420, 0xA771, 0x543C, 0xA772, 0x5440, 0xA773, 0x5431, 0xA774, 0x542B, 0xA775, 0x541F, 0xA776, 0x542C, 0xA777, 0x56EA,
+ 0xA778, 0x56F0, 0xA779, 0x56E4, 0xA77A, 0x56EB, 0xA77B, 0x574A, 0xA77C, 0x5751, 0xA77D, 0x5740, 0xA77E, 0x574D, 0xA7A1, 0x5747,
+ 0xA7A2, 0x574E, 0xA7A3, 0x573E, 0xA7A4, 0x5750, 0xA7A5, 0x574F, 0xA7A6, 0x573B, 0xA7A7, 0x58EF, 0xA7A8, 0x593E, 0xA7A9, 0x599D,
+ 0xA7AA, 0x5992, 0xA7AB, 0x59A8, 0xA7AC, 0x599E, 0xA7AD, 0x59A3, 0xA7AE, 0x5999, 0xA7AF, 0x5996, 0xA7B0, 0x598D, 0xA7B1, 0x59A4,
+ 0xA7B2, 0x5993, 0xA7B3, 0x598A, 0xA7B4, 0x59A5, 0xA7B5, 0x5B5D, 0xA7B6, 0x5B5C, 0xA7B7, 0x5B5A, 0xA7B8, 0x5B5B, 0xA7B9, 0x5B8C,
+ 0xA7BA, 0x5B8B, 0xA7BB, 0x5B8F, 0xA7BC, 0x5C2C, 0xA7BD, 0x5C40, 0xA7BE, 0x5C41, 0xA7BF, 0x5C3F, 0xA7C0, 0x5C3E, 0xA7C1, 0x5C90,
+ 0xA7C2, 0x5C91, 0xA7C3, 0x5C94, 0xA7C4, 0x5C8C, 0xA7C5, 0x5DEB, 0xA7C6, 0x5E0C, 0xA7C7, 0x5E8F, 0xA7C8, 0x5E87, 0xA7C9, 0x5E8A,
+ 0xA7CA, 0x5EF7, 0xA7CB, 0x5F04, 0xA7CC, 0x5F1F, 0xA7CD, 0x5F64, 0xA7CE, 0x5F62, 0xA7CF, 0x5F77, 0xA7D0, 0x5F79, 0xA7D1, 0x5FD8,
+ 0xA7D2, 0x5FCC, 0xA7D3, 0x5FD7, 0xA7D4, 0x5FCD, 0xA7D5, 0x5FF1, 0xA7D6, 0x5FEB, 0xA7D7, 0x5FF8, 0xA7D8, 0x5FEA, 0xA7D9, 0x6212,
+ 0xA7DA, 0x6211, 0xA7DB, 0x6284, 0xA7DC, 0x6297, 0xA7DD, 0x6296, 0xA7DE, 0x6280, 0xA7DF, 0x6276, 0xA7E0, 0x6289, 0xA7E1, 0x626D,
+ 0xA7E2, 0x628A, 0xA7E3, 0x627C, 0xA7E4, 0x627E, 0xA7E5, 0x6279, 0xA7E6, 0x6273, 0xA7E7, 0x6292, 0xA7E8, 0x626F, 0xA7E9, 0x6298,
+ 0xA7EA, 0x626E, 0xA7EB, 0x6295, 0xA7EC, 0x6293, 0xA7ED, 0x6291, 0xA7EE, 0x6286, 0xA7EF, 0x6539, 0xA7F0, 0x653B, 0xA7F1, 0x6538,
+ 0xA7F2, 0x65F1, 0xA7F3, 0x66F4, 0xA7F4, 0x675F, 0xA7F5, 0x674E, 0xA7F6, 0x674F, 0xA7F7, 0x6750, 0xA7F8, 0x6751, 0xA7F9, 0x675C,
+ 0xA7FA, 0x6756, 0xA7FB, 0x675E, 0xA7FC, 0x6749, 0xA7FD, 0x6746, 0xA7FE, 0x6760, 0xA840, 0x6753, 0xA841, 0x6757, 0xA842, 0x6B65,
+ 0xA843, 0x6BCF, 0xA844, 0x6C42, 0xA845, 0x6C5E, 0xA846, 0x6C99, 0xA847, 0x6C81, 0xA848, 0x6C88, 0xA849, 0x6C89, 0xA84A, 0x6C85,
+ 0xA84B, 0x6C9B, 0xA84C, 0x6C6A, 0xA84D, 0x6C7A, 0xA84E, 0x6C90, 0xA84F, 0x6C70, 0xA850, 0x6C8C, 0xA851, 0x6C68, 0xA852, 0x6C96,
+ 0xA853, 0x6C92, 0xA854, 0x6C7D, 0xA855, 0x6C83, 0xA856, 0x6C72, 0xA857, 0x6C7E, 0xA858, 0x6C74, 0xA859, 0x6C86, 0xA85A, 0x6C76,
+ 0xA85B, 0x6C8D, 0xA85C, 0x6C94, 0xA85D, 0x6C98, 0xA85E, 0x6C82, 0xA85F, 0x7076, 0xA860, 0x707C, 0xA861, 0x707D, 0xA862, 0x7078,
+ 0xA863, 0x7262, 0xA864, 0x7261, 0xA865, 0x7260, 0xA866, 0x72C4, 0xA867, 0x72C2, 0xA868, 0x7396, 0xA869, 0x752C, 0xA86A, 0x752B,
+ 0xA86B, 0x7537, 0xA86C, 0x7538, 0xA86D, 0x7682, 0xA86E, 0x76EF, 0xA86F, 0x77E3, 0xA870, 0x79C1, 0xA871, 0x79C0, 0xA872, 0x79BF,
+ 0xA873, 0x7A76, 0xA874, 0x7CFB, 0xA875, 0x7F55, 0xA876, 0x8096, 0xA877, 0x8093, 0xA878, 0x809D, 0xA879, 0x8098, 0xA87A, 0x809B,
+ 0xA87B, 0x809A, 0xA87C, 0x80B2, 0xA87D, 0x826F, 0xA87E, 0x8292, 0xA8A1, 0x828B, 0xA8A2, 0x828D, 0xA8A3, 0x898B, 0xA8A4, 0x89D2,
+ 0xA8A5, 0x8A00, 0xA8A6, 0x8C37, 0xA8A7, 0x8C46, 0xA8A8, 0x8C55, 0xA8A9, 0x8C9D, 0xA8AA, 0x8D64, 0xA8AB, 0x8D70, 0xA8AC, 0x8DB3,
+ 0xA8AD, 0x8EAB, 0xA8AE, 0x8ECA, 0xA8AF, 0x8F9B, 0xA8B0, 0x8FB0, 0xA8B1, 0x8FC2, 0xA8B2, 0x8FC6, 0xA8B3, 0x8FC5, 0xA8B4, 0x8FC4,
+ 0xA8B5, 0x5DE1, 0xA8B6, 0x9091, 0xA8B7, 0x90A2, 0xA8B8, 0x90AA, 0xA8B9, 0x90A6, 0xA8BA, 0x90A3, 0xA8BB, 0x9149, 0xA8BC, 0x91C6,
+ 0xA8BD, 0x91CC, 0xA8BE, 0x9632, 0xA8BF, 0x962E, 0xA8C0, 0x9631, 0xA8C1, 0x962A, 0xA8C2, 0x962C, 0xA8C3, 0x4E26, 0xA8C4, 0x4E56,
+ 0xA8C5, 0x4E73, 0xA8C6, 0x4E8B, 0xA8C7, 0x4E9B, 0xA8C8, 0x4E9E, 0xA8C9, 0x4EAB, 0xA8CA, 0x4EAC, 0xA8CB, 0x4F6F, 0xA8CC, 0x4F9D,
+ 0xA8CD, 0x4F8D, 0xA8CE, 0x4F73, 0xA8CF, 0x4F7F, 0xA8D0, 0x4F6C, 0xA8D1, 0x4F9B, 0xA8D2, 0x4F8B, 0xA8D3, 0x4F86, 0xA8D4, 0x4F83,
+ 0xA8D5, 0x4F70, 0xA8D6, 0x4F75, 0xA8D7, 0x4F88, 0xA8D8, 0x4F69, 0xA8D9, 0x4F7B, 0xA8DA, 0x4F96, 0xA8DB, 0x4F7E, 0xA8DC, 0x4F8F,
+ 0xA8DD, 0x4F91, 0xA8DE, 0x4F7A, 0xA8DF, 0x5154, 0xA8E0, 0x5152, 0xA8E1, 0x5155, 0xA8E2, 0x5169, 0xA8E3, 0x5177, 0xA8E4, 0x5176,
+ 0xA8E5, 0x5178, 0xA8E6, 0x51BD, 0xA8E7, 0x51FD, 0xA8E8, 0x523B, 0xA8E9, 0x5238, 0xA8EA, 0x5237, 0xA8EB, 0x523A, 0xA8EC, 0x5230,
+ 0xA8ED, 0x522E, 0xA8EE, 0x5236, 0xA8EF, 0x5241, 0xA8F0, 0x52BE, 0xA8F1, 0x52BB, 0xA8F2, 0x5352, 0xA8F3, 0x5354, 0xA8F4, 0x5353,
+ 0xA8F5, 0x5351, 0xA8F6, 0x5366, 0xA8F7, 0x5377, 0xA8F8, 0x5378, 0xA8F9, 0x5379, 0xA8FA, 0x53D6, 0xA8FB, 0x53D4, 0xA8FC, 0x53D7,
+ 0xA8FD, 0x5473, 0xA8FE, 0x5475, 0xA940, 0x5496, 0xA941, 0x5478, 0xA942, 0x5495, 0xA943, 0x5480, 0xA944, 0x547B, 0xA945, 0x5477,
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+ 0xA956, 0x5777, 0xA957, 0x576A, 0xA958, 0x5769, 0xA959, 0x5761, 0xA95A, 0x5766, 0xA95B, 0x5764, 0xA95C, 0x577C, 0xA95D, 0x591C,
+ 0xA95E, 0x5949, 0xA95F, 0x5947, 0xA960, 0x5948, 0xA961, 0x5944, 0xA962, 0x5954, 0xA963, 0x59BE, 0xA964, 0x59BB, 0xA965, 0x59D4,
+ 0xA966, 0x59B9, 0xA967, 0x59AE, 0xA968, 0x59D1, 0xA969, 0x59C6, 0xA96A, 0x59D0, 0xA96B, 0x59CD, 0xA96C, 0x59CB, 0xA96D, 0x59D3,
+ 0xA96E, 0x59CA, 0xA96F, 0x59AF, 0xA970, 0x59B3, 0xA971, 0x59D2, 0xA972, 0x59C5, 0xA973, 0x5B5F, 0xA974, 0x5B64, 0xA975, 0x5B63,
+ 0xA976, 0x5B97, 0xA977, 0x5B9A, 0xA978, 0x5B98, 0xA979, 0x5B9C, 0xA97A, 0x5B99, 0xA97B, 0x5B9B, 0xA97C, 0x5C1A, 0xA97D, 0x5C48,
+ 0xA97E, 0x5C45, 0xA9A1, 0x5C46, 0xA9A2, 0x5CB7, 0xA9A3, 0x5CA1, 0xA9A4, 0x5CB8, 0xA9A5, 0x5CA9, 0xA9A6, 0x5CAB, 0xA9A7, 0x5CB1,
+ 0xA9A8, 0x5CB3, 0xA9A9, 0x5E18, 0xA9AA, 0x5E1A, 0xA9AB, 0x5E16, 0xA9AC, 0x5E15, 0xA9AD, 0x5E1B, 0xA9AE, 0x5E11, 0xA9AF, 0x5E78,
+ 0xA9B0, 0x5E9A, 0xA9B1, 0x5E97, 0xA9B2, 0x5E9C, 0xA9B3, 0x5E95, 0xA9B4, 0x5E96, 0xA9B5, 0x5EF6, 0xA9B6, 0x5F26, 0xA9B7, 0x5F27,
+ 0xA9B8, 0x5F29, 0xA9B9, 0x5F80, 0xA9BA, 0x5F81, 0xA9BB, 0x5F7F, 0xA9BC, 0x5F7C, 0xA9BD, 0x5FDD, 0xA9BE, 0x5FE0, 0xA9BF, 0x5FFD,
+ 0xA9C0, 0x5FF5, 0xA9C1, 0x5FFF, 0xA9C2, 0x600F, 0xA9C3, 0x6014, 0xA9C4, 0x602F, 0xA9C5, 0x6035, 0xA9C6, 0x6016, 0xA9C7, 0x602A,
+ 0xA9C8, 0x6015, 0xA9C9, 0x6021, 0xA9CA, 0x6027, 0xA9CB, 0x6029, 0xA9CC, 0x602B, 0xA9CD, 0x601B, 0xA9CE, 0x6216, 0xA9CF, 0x6215,
+ 0xA9D0, 0x623F, 0xA9D1, 0x623E, 0xA9D2, 0x6240, 0xA9D3, 0x627F, 0xA9D4, 0x62C9, 0xA9D5, 0x62CC, 0xA9D6, 0x62C4, 0xA9D7, 0x62BF,
+ 0xA9D8, 0x62C2, 0xA9D9, 0x62B9, 0xA9DA, 0x62D2, 0xA9DB, 0x62DB, 0xA9DC, 0x62AB, 0xA9DD, 0x62D3, 0xA9DE, 0x62D4, 0xA9DF, 0x62CB,
+ 0xA9E0, 0x62C8, 0xA9E1, 0x62A8, 0xA9E2, 0x62BD, 0xA9E3, 0x62BC, 0xA9E4, 0x62D0, 0xA9E5, 0x62D9, 0xA9E6, 0x62C7, 0xA9E7, 0x62CD,
+ 0xA9E8, 0x62B5, 0xA9E9, 0x62DA, 0xA9EA, 0x62B1, 0xA9EB, 0x62D8, 0xA9EC, 0x62D6, 0xA9ED, 0x62D7, 0xA9EE, 0x62C6, 0xA9EF, 0x62AC,
+ 0xA9F0, 0x62CE, 0xA9F1, 0x653E, 0xA9F2, 0x65A7, 0xA9F3, 0x65BC, 0xA9F4, 0x65FA, 0xA9F5, 0x6614, 0xA9F6, 0x6613, 0xA9F7, 0x660C,
+ 0xA9F8, 0x6606, 0xA9F9, 0x6602, 0xA9FA, 0x660E, 0xA9FB, 0x6600, 0xA9FC, 0x660F, 0xA9FD, 0x6615, 0xA9FE, 0x660A, 0xAA40, 0x6607,
+ 0xAA41, 0x670D, 0xAA42, 0x670B, 0xAA43, 0x676D, 0xAA44, 0x678B, 0xAA45, 0x6795, 0xAA46, 0x6771, 0xAA47, 0x679C, 0xAA48, 0x6773,
+ 0xAA49, 0x6777, 0xAA4A, 0x6787, 0xAA4B, 0x679D, 0xAA4C, 0x6797, 0xAA4D, 0x676F, 0xAA4E, 0x6770, 0xAA4F, 0x677F, 0xAA50, 0x6789,
+ 0xAA51, 0x677E, 0xAA52, 0x6790, 0xAA53, 0x6775, 0xAA54, 0x679A, 0xAA55, 0x6793, 0xAA56, 0x677C, 0xAA57, 0x676A, 0xAA58, 0x6772,
+ 0xAA59, 0x6B23, 0xAA5A, 0x6B66, 0xAA5B, 0x6B67, 0xAA5C, 0x6B7F, 0xAA5D, 0x6C13, 0xAA5E, 0x6C1B, 0xAA5F, 0x6CE3, 0xAA60, 0x6CE8,
+ 0xAA61, 0x6CF3, 0xAA62, 0x6CB1, 0xAA63, 0x6CCC, 0xAA64, 0x6CE5, 0xAA65, 0x6CB3, 0xAA66, 0x6CBD, 0xAA67, 0x6CBE, 0xAA68, 0x6CBC,
+ 0xAA69, 0x6CE2, 0xAA6A, 0x6CAB, 0xAA6B, 0x6CD5, 0xAA6C, 0x6CD3, 0xAA6D, 0x6CB8, 0xAA6E, 0x6CC4, 0xAA6F, 0x6CB9, 0xAA70, 0x6CC1,
+ 0xAA71, 0x6CAE, 0xAA72, 0x6CD7, 0xAA73, 0x6CC5, 0xAA74, 0x6CF1, 0xAA75, 0x6CBF, 0xAA76, 0x6CBB, 0xAA77, 0x6CE1, 0xAA78, 0x6CDB,
+ 0xAA79, 0x6CCA, 0xAA7A, 0x6CAC, 0xAA7B, 0x6CEF, 0xAA7C, 0x6CDC, 0xAA7D, 0x6CD6, 0xAA7E, 0x6CE0, 0xAAA1, 0x7095, 0xAAA2, 0x708E,
+ 0xAAA3, 0x7092, 0xAAA4, 0x708A, 0xAAA5, 0x7099, 0xAAA6, 0x722C, 0xAAA7, 0x722D, 0xAAA8, 0x7238, 0xAAA9, 0x7248, 0xAAAA, 0x7267,
+ 0xAAAB, 0x7269, 0xAAAC, 0x72C0, 0xAAAD, 0x72CE, 0xAAAE, 0x72D9, 0xAAAF, 0x72D7, 0xAAB0, 0x72D0, 0xAAB1, 0x73A9, 0xAAB2, 0x73A8,
+ 0xAAB3, 0x739F, 0xAAB4, 0x73AB, 0xAAB5, 0x73A5, 0xAAB6, 0x753D, 0xAAB7, 0x759D, 0xAAB8, 0x7599, 0xAAB9, 0x759A, 0xAABA, 0x7684,
+ 0xAABB, 0x76C2, 0xAABC, 0x76F2, 0xAABD, 0x76F4, 0xAABE, 0x77E5, 0xAABF, 0x77FD, 0xAAC0, 0x793E, 0xAAC1, 0x7940, 0xAAC2, 0x7941,
+ 0xAAC3, 0x79C9, 0xAAC4, 0x79C8, 0xAAC5, 0x7A7A, 0xAAC6, 0x7A79, 0xAAC7, 0x7AFA, 0xAAC8, 0x7CFE, 0xAAC9, 0x7F54, 0xAACA, 0x7F8C,
+ 0xAACB, 0x7F8B, 0xAACC, 0x8005, 0xAACD, 0x80BA, 0xAACE, 0x80A5, 0xAACF, 0x80A2, 0xAAD0, 0x80B1, 0xAAD1, 0x80A1, 0xAAD2, 0x80AB,
+ 0xAAD3, 0x80A9, 0xAAD4, 0x80B4, 0xAAD5, 0x80AA, 0xAAD6, 0x80AF, 0xAAD7, 0x81E5, 0xAAD8, 0x81FE, 0xAAD9, 0x820D, 0xAADA, 0x82B3,
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+ 0xAF78, 0x77E9, 0xAF79, 0x7830, 0xAF7A, 0x7827, 0xAF7B, 0x7838, 0xAF7C, 0x781D, 0xAF7D, 0x7834, 0xAF7E, 0x7837, 0xAFA1, 0x7825,
+ 0xAFA2, 0x782D, 0xAFA3, 0x7820, 0xAFA4, 0x781F, 0xAFA5, 0x7832, 0xAFA6, 0x7955, 0xAFA7, 0x7950, 0xAFA8, 0x7960, 0xAFA9, 0x795F,
+ 0xAFAA, 0x7956, 0xAFAB, 0x795E, 0xAFAC, 0x795D, 0xAFAD, 0x7957, 0xAFAE, 0x795A, 0xAFAF, 0x79E4, 0xAFB0, 0x79E3, 0xAFB1, 0x79E7,
+ 0xAFB2, 0x79DF, 0xAFB3, 0x79E6, 0xAFB4, 0x79E9, 0xAFB5, 0x79D8, 0xAFB6, 0x7A84, 0xAFB7, 0x7A88, 0xAFB8, 0x7AD9, 0xAFB9, 0x7B06,
+ 0xAFBA, 0x7B11, 0xAFBB, 0x7C89, 0xAFBC, 0x7D21, 0xAFBD, 0x7D17, 0xAFBE, 0x7D0B, 0xAFBF, 0x7D0A, 0xAFC0, 0x7D20, 0xAFC1, 0x7D22,
+ 0xAFC2, 0x7D14, 0xAFC3, 0x7D10, 0xAFC4, 0x7D15, 0xAFC5, 0x7D1A, 0xAFC6, 0x7D1C, 0xAFC7, 0x7D0D, 0xAFC8, 0x7D19, 0xAFC9, 0x7D1B,
+ 0xAFCA, 0x7F3A, 0xAFCB, 0x7F5F, 0xAFCC, 0x7F94, 0xAFCD, 0x7FC5, 0xAFCE, 0x7FC1, 0xAFCF, 0x8006, 0xAFD0, 0x8018, 0xAFD1, 0x8015,
+ 0xAFD2, 0x8019, 0xAFD3, 0x8017, 0xAFD4, 0x803D, 0xAFD5, 0x803F, 0xAFD6, 0x80F1, 0xAFD7, 0x8102, 0xAFD8, 0x80F0, 0xAFD9, 0x8105,
+ 0xAFDA, 0x80ED, 0xAFDB, 0x80F4, 0xAFDC, 0x8106, 0xAFDD, 0x80F8, 0xAFDE, 0x80F3, 0xAFDF, 0x8108, 0xAFE0, 0x80FD, 0xAFE1, 0x810A,
+ 0xAFE2, 0x80FC, 0xAFE3, 0x80EF, 0xAFE4, 0x81ED, 0xAFE5, 0x81EC, 0xAFE6, 0x8200, 0xAFE7, 0x8210, 0xAFE8, 0x822A, 0xAFE9, 0x822B,
+ 0xAFEA, 0x8228, 0xAFEB, 0x822C, 0xAFEC, 0x82BB, 0xAFED, 0x832B, 0xAFEE, 0x8352, 0xAFEF, 0x8354, 0xAFF0, 0x834A, 0xAFF1, 0x8338,
+ 0xAFF2, 0x8350, 0xAFF3, 0x8349, 0xAFF4, 0x8335, 0xAFF5, 0x8334, 0xAFF6, 0x834F, 0xAFF7, 0x8332, 0xAFF8, 0x8339, 0xAFF9, 0x8336,
+ 0xAFFA, 0x8317, 0xAFFB, 0x8340, 0xAFFC, 0x8331, 0xAFFD, 0x8328, 0xAFFE, 0x8343, 0xB040, 0x8654, 0xB041, 0x868A, 0xB042, 0x86AA,
+ 0xB043, 0x8693, 0xB044, 0x86A4, 0xB045, 0x86A9, 0xB046, 0x868C, 0xB047, 0x86A3, 0xB048, 0x869C, 0xB049, 0x8870, 0xB04A, 0x8877,
+ 0xB04B, 0x8881, 0xB04C, 0x8882, 0xB04D, 0x887D, 0xB04E, 0x8879, 0xB04F, 0x8A18, 0xB050, 0x8A10, 0xB051, 0x8A0E, 0xB052, 0x8A0C,
+ 0xB053, 0x8A15, 0xB054, 0x8A0A, 0xB055, 0x8A17, 0xB056, 0x8A13, 0xB057, 0x8A16, 0xB058, 0x8A0F, 0xB059, 0x8A11, 0xB05A, 0x8C48,
+ 0xB05B, 0x8C7A, 0xB05C, 0x8C79, 0xB05D, 0x8CA1, 0xB05E, 0x8CA2, 0xB05F, 0x8D77, 0xB060, 0x8EAC, 0xB061, 0x8ED2, 0xB062, 0x8ED4,
+ 0xB063, 0x8ECF, 0xB064, 0x8FB1, 0xB065, 0x9001, 0xB066, 0x9006, 0xB067, 0x8FF7, 0xB068, 0x9000, 0xB069, 0x8FFA, 0xB06A, 0x8FF4,
+ 0xB06B, 0x9003, 0xB06C, 0x8FFD, 0xB06D, 0x9005, 0xB06E, 0x8FF8, 0xB06F, 0x9095, 0xB070, 0x90E1, 0xB071, 0x90DD, 0xB072, 0x90E2,
+ 0xB073, 0x9152, 0xB074, 0x914D, 0xB075, 0x914C, 0xB076, 0x91D8, 0xB077, 0x91DD, 0xB078, 0x91D7, 0xB079, 0x91DC, 0xB07A, 0x91D9,
+ 0xB07B, 0x9583, 0xB07C, 0x9662, 0xB07D, 0x9663, 0xB07E, 0x9661, 0xB0A1, 0x965B, 0xB0A2, 0x965D, 0xB0A3, 0x9664, 0xB0A4, 0x9658,
+ 0xB0A5, 0x965E, 0xB0A6, 0x96BB, 0xB0A7, 0x98E2, 0xB0A8, 0x99AC, 0xB0A9, 0x9AA8, 0xB0AA, 0x9AD8, 0xB0AB, 0x9B25, 0xB0AC, 0x9B32,
+ 0xB0AD, 0x9B3C, 0xB0AE, 0x4E7E, 0xB0AF, 0x507A, 0xB0B0, 0x507D, 0xB0B1, 0x505C, 0xB0B2, 0x5047, 0xB0B3, 0x5043, 0xB0B4, 0x504C,
+ 0xB0B5, 0x505A, 0xB0B6, 0x5049, 0xB0B7, 0x5065, 0xB0B8, 0x5076, 0xB0B9, 0x504E, 0xB0BA, 0x5055, 0xB0BB, 0x5075, 0xB0BC, 0x5074,
+ 0xB0BD, 0x5077, 0xB0BE, 0x504F, 0xB0BF, 0x500F, 0xB0C0, 0x506F, 0xB0C1, 0x506D, 0xB0C2, 0x515C, 0xB0C3, 0x5195, 0xB0C4, 0x51F0,
+ 0xB0C5, 0x526A, 0xB0C6, 0x526F, 0xB0C7, 0x52D2, 0xB0C8, 0x52D9, 0xB0C9, 0x52D8, 0xB0CA, 0x52D5, 0xB0CB, 0x5310, 0xB0CC, 0x530F,
+ 0xB0CD, 0x5319, 0xB0CE, 0x533F, 0xB0CF, 0x5340, 0xB0D0, 0x533E, 0xB0D1, 0x53C3, 0xB0D2, 0x66FC, 0xB0D3, 0x5546, 0xB0D4, 0x556A,
+ 0xB0D5, 0x5566, 0xB0D6, 0x5544, 0xB0D7, 0x555E, 0xB0D8, 0x5561, 0xB0D9, 0x5543, 0xB0DA, 0x554A, 0xB0DB, 0x5531, 0xB0DC, 0x5556,
+ 0xB0DD, 0x554F, 0xB0DE, 0x5555, 0xB0DF, 0x552F, 0xB0E0, 0x5564, 0xB0E1, 0x5538, 0xB0E2, 0x552E, 0xB0E3, 0x555C, 0xB0E4, 0x552C,
+ 0xB0E5, 0x5563, 0xB0E6, 0x5533, 0xB0E7, 0x5541, 0xB0E8, 0x5557, 0xB0E9, 0x5708, 0xB0EA, 0x570B, 0xB0EB, 0x5709, 0xB0EC, 0x57DF,
+ 0xB0ED, 0x5805, 0xB0EE, 0x580A, 0xB0EF, 0x5806, 0xB0F0, 0x57E0, 0xB0F1, 0x57E4, 0xB0F2, 0x57FA, 0xB0F3, 0x5802, 0xB0F4, 0x5835,
+ 0xB0F5, 0x57F7, 0xB0F6, 0x57F9, 0xB0F7, 0x5920, 0xB0F8, 0x5962, 0xB0F9, 0x5A36, 0xB0FA, 0x5A41, 0xB0FB, 0x5A49, 0xB0FC, 0x5A66,
+ 0xB0FD, 0x5A6A, 0xB0FE, 0x5A40, 0xB140, 0x5A3C, 0xB141, 0x5A62, 0xB142, 0x5A5A, 0xB143, 0x5A46, 0xB144, 0x5A4A, 0xB145, 0x5B70,
+ 0xB146, 0x5BC7, 0xB147, 0x5BC5, 0xB148, 0x5BC4, 0xB149, 0x5BC2, 0xB14A, 0x5BBF, 0xB14B, 0x5BC6, 0xB14C, 0x5C09, 0xB14D, 0x5C08,
+ 0xB14E, 0x5C07, 0xB14F, 0x5C60, 0xB150, 0x5C5C, 0xB151, 0x5C5D, 0xB152, 0x5D07, 0xB153, 0x5D06, 0xB154, 0x5D0E, 0xB155, 0x5D1B,
+ 0xB156, 0x5D16, 0xB157, 0x5D22, 0xB158, 0x5D11, 0xB159, 0x5D29, 0xB15A, 0x5D14, 0xB15B, 0x5D19, 0xB15C, 0x5D24, 0xB15D, 0x5D27,
+ 0xB15E, 0x5D17, 0xB15F, 0x5DE2, 0xB160, 0x5E38, 0xB161, 0x5E36, 0xB162, 0x5E33, 0xB163, 0x5E37, 0xB164, 0x5EB7, 0xB165, 0x5EB8,
+ 0xB166, 0x5EB6, 0xB167, 0x5EB5, 0xB168, 0x5EBE, 0xB169, 0x5F35, 0xB16A, 0x5F37, 0xB16B, 0x5F57, 0xB16C, 0x5F6C, 0xB16D, 0x5F69,
+ 0xB16E, 0x5F6B, 0xB16F, 0x5F97, 0xB170, 0x5F99, 0xB171, 0x5F9E, 0xB172, 0x5F98, 0xB173, 0x5FA1, 0xB174, 0x5FA0, 0xB175, 0x5F9C,
+ 0xB176, 0x607F, 0xB177, 0x60A3, 0xB178, 0x6089, 0xB179, 0x60A0, 0xB17A, 0x60A8, 0xB17B, 0x60CB, 0xB17C, 0x60B4, 0xB17D, 0x60E6,
+ 0xB17E, 0x60BD, 0xB1A1, 0x60C5, 0xB1A2, 0x60BB, 0xB1A3, 0x60B5, 0xB1A4, 0x60DC, 0xB1A5, 0x60BC, 0xB1A6, 0x60D8, 0xB1A7, 0x60D5,
+ 0xB1A8, 0x60C6, 0xB1A9, 0x60DF, 0xB1AA, 0x60B8, 0xB1AB, 0x60DA, 0xB1AC, 0x60C7, 0xB1AD, 0x621A, 0xB1AE, 0x621B, 0xB1AF, 0x6248,
+ 0xB1B0, 0x63A0, 0xB1B1, 0x63A7, 0xB1B2, 0x6372, 0xB1B3, 0x6396, 0xB1B4, 0x63A2, 0xB1B5, 0x63A5, 0xB1B6, 0x6377, 0xB1B7, 0x6367,
+ 0xB1B8, 0x6398, 0xB1B9, 0x63AA, 0xB1BA, 0x6371, 0xB1BB, 0x63A9, 0xB1BC, 0x6389, 0xB1BD, 0x6383, 0xB1BE, 0x639B, 0xB1BF, 0x636B,
+ 0xB1C0, 0x63A8, 0xB1C1, 0x6384, 0xB1C2, 0x6388, 0xB1C3, 0x6399, 0xB1C4, 0x63A1, 0xB1C5, 0x63AC, 0xB1C6, 0x6392, 0xB1C7, 0x638F,
+ 0xB1C8, 0x6380, 0xB1C9, 0x637B, 0xB1CA, 0x6369, 0xB1CB, 0x6368, 0xB1CC, 0x637A, 0xB1CD, 0x655D, 0xB1CE, 0x6556, 0xB1CF, 0x6551,
+ 0xB1D0, 0x6559, 0xB1D1, 0x6557, 0xB1D2, 0x555F, 0xB1D3, 0x654F, 0xB1D4, 0x6558, 0xB1D5, 0x6555, 0xB1D6, 0x6554, 0xB1D7, 0x659C,
+ 0xB1D8, 0x659B, 0xB1D9, 0x65AC, 0xB1DA, 0x65CF, 0xB1DB, 0x65CB, 0xB1DC, 0x65CC, 0xB1DD, 0x65CE, 0xB1DE, 0x665D, 0xB1DF, 0x665A,
+ 0xB1E0, 0x6664, 0xB1E1, 0x6668, 0xB1E2, 0x6666, 0xB1E3, 0x665E, 0xB1E4, 0x66F9, 0xB1E5, 0x52D7, 0xB1E6, 0x671B, 0xB1E7, 0x6881,
+ 0xB1E8, 0x68AF, 0xB1E9, 0x68A2, 0xB1EA, 0x6893, 0xB1EB, 0x68B5, 0xB1EC, 0x687F, 0xB1ED, 0x6876, 0xB1EE, 0x68B1, 0xB1EF, 0x68A7,
+ 0xB1F0, 0x6897, 0xB1F1, 0x68B0, 0xB1F2, 0x6883, 0xB1F3, 0x68C4, 0xB1F4, 0x68AD, 0xB1F5, 0x6886, 0xB1F6, 0x6885, 0xB1F7, 0x6894,
+ 0xB1F8, 0x689D, 0xB1F9, 0x68A8, 0xB1FA, 0x689F, 0xB1FB, 0x68A1, 0xB1FC, 0x6882, 0xB1FD, 0x6B32, 0xB1FE, 0x6BBA, 0xB240, 0x6BEB,
+ 0xB241, 0x6BEC, 0xB242, 0x6C2B, 0xB243, 0x6D8E, 0xB244, 0x6DBC, 0xB245, 0x6DF3, 0xB246, 0x6DD9, 0xB247, 0x6DB2, 0xB248, 0x6DE1,
+ 0xB249, 0x6DCC, 0xB24A, 0x6DE4, 0xB24B, 0x6DFB, 0xB24C, 0x6DFA, 0xB24D, 0x6E05, 0xB24E, 0x6DC7, 0xB24F, 0x6DCB, 0xB250, 0x6DAF,
+ 0xB251, 0x6DD1, 0xB252, 0x6DAE, 0xB253, 0x6DDE, 0xB254, 0x6DF9, 0xB255, 0x6DB8, 0xB256, 0x6DF7, 0xB257, 0x6DF5, 0xB258, 0x6DC5,
+ 0xB259, 0x6DD2, 0xB25A, 0x6E1A, 0xB25B, 0x6DB5, 0xB25C, 0x6DDA, 0xB25D, 0x6DEB, 0xB25E, 0x6DD8, 0xB25F, 0x6DEA, 0xB260, 0x6DF1,
+ 0xB261, 0x6DEE, 0xB262, 0x6DE8, 0xB263, 0x6DC6, 0xB264, 0x6DC4, 0xB265, 0x6DAA, 0xB266, 0x6DEC, 0xB267, 0x6DBF, 0xB268, 0x6DE6,
+ 0xB269, 0x70F9, 0xB26A, 0x7109, 0xB26B, 0x710A, 0xB26C, 0x70FD, 0xB26D, 0x70EF, 0xB26E, 0x723D, 0xB26F, 0x727D, 0xB270, 0x7281,
+ 0xB271, 0x731C, 0xB272, 0x731B, 0xB273, 0x7316, 0xB274, 0x7313, 0xB275, 0x7319, 0xB276, 0x7387, 0xB277, 0x7405, 0xB278, 0x740A,
+ 0xB279, 0x7403, 0xB27A, 0x7406, 0xB27B, 0x73FE, 0xB27C, 0x740D, 0xB27D, 0x74E0, 0xB27E, 0x74F6, 0xB2A1, 0x74F7, 0xB2A2, 0x751C,
+ 0xB2A3, 0x7522, 0xB2A4, 0x7565, 0xB2A5, 0x7566, 0xB2A6, 0x7562, 0xB2A7, 0x7570, 0xB2A8, 0x758F, 0xB2A9, 0x75D4, 0xB2AA, 0x75D5,
+ 0xB2AB, 0x75B5, 0xB2AC, 0x75CA, 0xB2AD, 0x75CD, 0xB2AE, 0x768E, 0xB2AF, 0x76D4, 0xB2B0, 0x76D2, 0xB2B1, 0x76DB, 0xB2B2, 0x7737,
+ 0xB2B3, 0x773E, 0xB2B4, 0x773C, 0xB2B5, 0x7736, 0xB2B6, 0x7738, 0xB2B7, 0x773A, 0xB2B8, 0x786B, 0xB2B9, 0x7843, 0xB2BA, 0x784E,
+ 0xB2BB, 0x7965, 0xB2BC, 0x7968, 0xB2BD, 0x796D, 0xB2BE, 0x79FB, 0xB2BF, 0x7A92, 0xB2C0, 0x7A95, 0xB2C1, 0x7B20, 0xB2C2, 0x7B28,
+ 0xB2C3, 0x7B1B, 0xB2C4, 0x7B2C, 0xB2C5, 0x7B26, 0xB2C6, 0x7B19, 0xB2C7, 0x7B1E, 0xB2C8, 0x7B2E, 0xB2C9, 0x7C92, 0xB2CA, 0x7C97,
+ 0xB2CB, 0x7C95, 0xB2CC, 0x7D46, 0xB2CD, 0x7D43, 0xB2CE, 0x7D71, 0xB2CF, 0x7D2E, 0xB2D0, 0x7D39, 0xB2D1, 0x7D3C, 0xB2D2, 0x7D40,
+ 0xB2D3, 0x7D30, 0xB2D4, 0x7D33, 0xB2D5, 0x7D44, 0xB2D6, 0x7D2F, 0xB2D7, 0x7D42, 0xB2D8, 0x7D32, 0xB2D9, 0x7D31, 0xB2DA, 0x7F3D,
+ 0xB2DB, 0x7F9E, 0xB2DC, 0x7F9A, 0xB2DD, 0x7FCC, 0xB2DE, 0x7FCE, 0xB2DF, 0x7FD2, 0xB2E0, 0x801C, 0xB2E1, 0x804A, 0xB2E2, 0x8046,
+ 0xB2E3, 0x812F, 0xB2E4, 0x8116, 0xB2E5, 0x8123, 0xB2E6, 0x812B, 0xB2E7, 0x8129, 0xB2E8, 0x8130, 0xB2E9, 0x8124, 0xB2EA, 0x8202,
+ 0xB2EB, 0x8235, 0xB2EC, 0x8237, 0xB2ED, 0x8236, 0xB2EE, 0x8239, 0xB2EF, 0x838E, 0xB2F0, 0x839E, 0xB2F1, 0x8398, 0xB2F2, 0x8378,
+ 0xB2F3, 0x83A2, 0xB2F4, 0x8396, 0xB2F5, 0x83BD, 0xB2F6, 0x83AB, 0xB2F7, 0x8392, 0xB2F8, 0x838A, 0xB2F9, 0x8393, 0xB2FA, 0x8389,
+ 0xB2FB, 0x83A0, 0xB2FC, 0x8377, 0xB2FD, 0x837B, 0xB2FE, 0x837C, 0xB340, 0x8386, 0xB341, 0x83A7, 0xB342, 0x8655, 0xB343, 0x5F6A,
+ 0xB344, 0x86C7, 0xB345, 0x86C0, 0xB346, 0x86B6, 0xB347, 0x86C4, 0xB348, 0x86B5, 0xB349, 0x86C6, 0xB34A, 0x86CB, 0xB34B, 0x86B1,
+ 0xB34C, 0x86AF, 0xB34D, 0x86C9, 0xB34E, 0x8853, 0xB34F, 0x889E, 0xB350, 0x8888, 0xB351, 0x88AB, 0xB352, 0x8892, 0xB353, 0x8896,
+ 0xB354, 0x888D, 0xB355, 0x888B, 0xB356, 0x8993, 0xB357, 0x898F, 0xB358, 0x8A2A, 0xB359, 0x8A1D, 0xB35A, 0x8A23, 0xB35B, 0x8A25,
+ 0xB35C, 0x8A31, 0xB35D, 0x8A2D, 0xB35E, 0x8A1F, 0xB35F, 0x8A1B, 0xB360, 0x8A22, 0xB361, 0x8C49, 0xB362, 0x8C5A, 0xB363, 0x8CA9,
+ 0xB364, 0x8CAC, 0xB365, 0x8CAB, 0xB366, 0x8CA8, 0xB367, 0x8CAA, 0xB368, 0x8CA7, 0xB369, 0x8D67, 0xB36A, 0x8D66, 0xB36B, 0x8DBE,
+ 0xB36C, 0x8DBA, 0xB36D, 0x8EDB, 0xB36E, 0x8EDF, 0xB36F, 0x9019, 0xB370, 0x900D, 0xB371, 0x901A, 0xB372, 0x9017, 0xB373, 0x9023,
+ 0xB374, 0x901F, 0xB375, 0x901D, 0xB376, 0x9010, 0xB377, 0x9015, 0xB378, 0x901E, 0xB379, 0x9020, 0xB37A, 0x900F, 0xB37B, 0x9022,
+ 0xB37C, 0x9016, 0xB37D, 0x901B, 0xB37E, 0x9014, 0xB3A1, 0x90E8, 0xB3A2, 0x90ED, 0xB3A3, 0x90FD, 0xB3A4, 0x9157, 0xB3A5, 0x91CE,
+ 0xB3A6, 0x91F5, 0xB3A7, 0x91E6, 0xB3A8, 0x91E3, 0xB3A9, 0x91E7, 0xB3AA, 0x91ED, 0xB3AB, 0x91E9, 0xB3AC, 0x9589, 0xB3AD, 0x966A,
+ 0xB3AE, 0x9675, 0xB3AF, 0x9673, 0xB3B0, 0x9678, 0xB3B1, 0x9670, 0xB3B2, 0x9674, 0xB3B3, 0x9676, 0xB3B4, 0x9677, 0xB3B5, 0x966C,
+ 0xB3B6, 0x96C0, 0xB3B7, 0x96EA, 0xB3B8, 0x96E9, 0xB3B9, 0x7AE0, 0xB3BA, 0x7ADF, 0xB3BB, 0x9802, 0xB3BC, 0x9803, 0xB3BD, 0x9B5A,
+ 0xB3BE, 0x9CE5, 0xB3BF, 0x9E75, 0xB3C0, 0x9E7F, 0xB3C1, 0x9EA5, 0xB3C2, 0x9EBB, 0xB3C3, 0x50A2, 0xB3C4, 0x508D, 0xB3C5, 0x5085,
+ 0xB3C6, 0x5099, 0xB3C7, 0x5091, 0xB3C8, 0x5080, 0xB3C9, 0x5096, 0xB3CA, 0x5098, 0xB3CB, 0x509A, 0xB3CC, 0x6700, 0xB3CD, 0x51F1,
+ 0xB3CE, 0x5272, 0xB3CF, 0x5274, 0xB3D0, 0x5275, 0xB3D1, 0x5269, 0xB3D2, 0x52DE, 0xB3D3, 0x52DD, 0xB3D4, 0x52DB, 0xB3D5, 0x535A,
+ 0xB3D6, 0x53A5, 0xB3D7, 0x557B, 0xB3D8, 0x5580, 0xB3D9, 0x55A7, 0xB3DA, 0x557C, 0xB3DB, 0x558A, 0xB3DC, 0x559D, 0xB3DD, 0x5598,
+ 0xB3DE, 0x5582, 0xB3DF, 0x559C, 0xB3E0, 0x55AA, 0xB3E1, 0x5594, 0xB3E2, 0x5587, 0xB3E3, 0x558B, 0xB3E4, 0x5583, 0xB3E5, 0x55B3,
+ 0xB3E6, 0x55AE, 0xB3E7, 0x559F, 0xB3E8, 0x553E, 0xB3E9, 0x55B2, 0xB3EA, 0x559A, 0xB3EB, 0x55BB, 0xB3EC, 0x55AC, 0xB3ED, 0x55B1,
+ 0xB3EE, 0x557E, 0xB3EF, 0x5589, 0xB3F0, 0x55AB, 0xB3F1, 0x5599, 0xB3F2, 0x570D, 0xB3F3, 0x582F, 0xB3F4, 0x582A, 0xB3F5, 0x5834,
+ 0xB3F6, 0x5824, 0xB3F7, 0x5830, 0xB3F8, 0x5831, 0xB3F9, 0x5821, 0xB3FA, 0x581D, 0xB3FB, 0x5820, 0xB3FC, 0x58F9, 0xB3FD, 0x58FA,
+ 0xB3FE, 0x5960, 0xB440, 0x5A77, 0xB441, 0x5A9A, 0xB442, 0x5A7F, 0xB443, 0x5A92, 0xB444, 0x5A9B, 0xB445, 0x5AA7, 0xB446, 0x5B73,
+ 0xB447, 0x5B71, 0xB448, 0x5BD2, 0xB449, 0x5BCC, 0xB44A, 0x5BD3, 0xB44B, 0x5BD0, 0xB44C, 0x5C0A, 0xB44D, 0x5C0B, 0xB44E, 0x5C31,
+ 0xB44F, 0x5D4C, 0xB450, 0x5D50, 0xB451, 0x5D34, 0xB452, 0x5D47, 0xB453, 0x5DFD, 0xB454, 0x5E45, 0xB455, 0x5E3D, 0xB456, 0x5E40,
+ 0xB457, 0x5E43, 0xB458, 0x5E7E, 0xB459, 0x5ECA, 0xB45A, 0x5EC1, 0xB45B, 0x5EC2, 0xB45C, 0x5EC4, 0xB45D, 0x5F3C, 0xB45E, 0x5F6D,
+ 0xB45F, 0x5FA9, 0xB460, 0x5FAA, 0xB461, 0x5FA8, 0xB462, 0x60D1, 0xB463, 0x60E1, 0xB464, 0x60B2, 0xB465, 0x60B6, 0xB466, 0x60E0,
+ 0xB467, 0x611C, 0xB468, 0x6123, 0xB469, 0x60FA, 0xB46A, 0x6115, 0xB46B, 0x60F0, 0xB46C, 0x60FB, 0xB46D, 0x60F4, 0xB46E, 0x6168,
+ 0xB46F, 0x60F1, 0xB470, 0x610E, 0xB471, 0x60F6, 0xB472, 0x6109, 0xB473, 0x6100, 0xB474, 0x6112, 0xB475, 0x621F, 0xB476, 0x6249,
+ 0xB477, 0x63A3, 0xB478, 0x638C, 0xB479, 0x63CF, 0xB47A, 0x63C0, 0xB47B, 0x63E9, 0xB47C, 0x63C9, 0xB47D, 0x63C6, 0xB47E, 0x63CD,
+ 0xB4A1, 0x63D2, 0xB4A2, 0x63E3, 0xB4A3, 0x63D0, 0xB4A4, 0x63E1, 0xB4A5, 0x63D6, 0xB4A6, 0x63ED, 0xB4A7, 0x63EE, 0xB4A8, 0x6376,
+ 0xB4A9, 0x63F4, 0xB4AA, 0x63EA, 0xB4AB, 0x63DB, 0xB4AC, 0x6452, 0xB4AD, 0x63DA, 0xB4AE, 0x63F9, 0xB4AF, 0x655E, 0xB4B0, 0x6566,
+ 0xB4B1, 0x6562, 0xB4B2, 0x6563, 0xB4B3, 0x6591, 0xB4B4, 0x6590, 0xB4B5, 0x65AF, 0xB4B6, 0x666E, 0xB4B7, 0x6670, 0xB4B8, 0x6674,
+ 0xB4B9, 0x6676, 0xB4BA, 0x666F, 0xB4BB, 0x6691, 0xB4BC, 0x667A, 0xB4BD, 0x667E, 0xB4BE, 0x6677, 0xB4BF, 0x66FE, 0xB4C0, 0x66FF,
+ 0xB4C1, 0x671F, 0xB4C2, 0x671D, 0xB4C3, 0x68FA, 0xB4C4, 0x68D5, 0xB4C5, 0x68E0, 0xB4C6, 0x68D8, 0xB4C7, 0x68D7, 0xB4C8, 0x6905,
+ 0xB4C9, 0x68DF, 0xB4CA, 0x68F5, 0xB4CB, 0x68EE, 0xB4CC, 0x68E7, 0xB4CD, 0x68F9, 0xB4CE, 0x68D2, 0xB4CF, 0x68F2, 0xB4D0, 0x68E3,
+ 0xB4D1, 0x68CB, 0xB4D2, 0x68CD, 0xB4D3, 0x690D, 0xB4D4, 0x6912, 0xB4D5, 0x690E, 0xB4D6, 0x68C9, 0xB4D7, 0x68DA, 0xB4D8, 0x696E,
+ 0xB4D9, 0x68FB, 0xB4DA, 0x6B3E, 0xB4DB, 0x6B3A, 0xB4DC, 0x6B3D, 0xB4DD, 0x6B98, 0xB4DE, 0x6B96, 0xB4DF, 0x6BBC, 0xB4E0, 0x6BEF,
+ 0xB4E1, 0x6C2E, 0xB4E2, 0x6C2F, 0xB4E3, 0x6C2C, 0xB4E4, 0x6E2F, 0xB4E5, 0x6E38, 0xB4E6, 0x6E54, 0xB4E7, 0x6E21, 0xB4E8, 0x6E32,
+ 0xB4E9, 0x6E67, 0xB4EA, 0x6E4A, 0xB4EB, 0x6E20, 0xB4EC, 0x6E25, 0xB4ED, 0x6E23, 0xB4EE, 0x6E1B, 0xB4EF, 0x6E5B, 0xB4F0, 0x6E58,
+ 0xB4F1, 0x6E24, 0xB4F2, 0x6E56, 0xB4F3, 0x6E6E, 0xB4F4, 0x6E2D, 0xB4F5, 0x6E26, 0xB4F6, 0x6E6F, 0xB4F7, 0x6E34, 0xB4F8, 0x6E4D,
+ 0xB4F9, 0x6E3A, 0xB4FA, 0x6E2C, 0xB4FB, 0x6E43, 0xB4FC, 0x6E1D, 0xB4FD, 0x6E3E, 0xB4FE, 0x6ECB, 0xB540, 0x6E89, 0xB541, 0x6E19,
+ 0xB542, 0x6E4E, 0xB543, 0x6E63, 0xB544, 0x6E44, 0xB545, 0x6E72, 0xB546, 0x6E69, 0xB547, 0x6E5F, 0xB548, 0x7119, 0xB549, 0x711A,
+ 0xB54A, 0x7126, 0xB54B, 0x7130, 0xB54C, 0x7121, 0xB54D, 0x7136, 0xB54E, 0x716E, 0xB54F, 0x711C, 0xB550, 0x724C, 0xB551, 0x7284,
+ 0xB552, 0x7280, 0xB553, 0x7336, 0xB554, 0x7325, 0xB555, 0x7334, 0xB556, 0x7329, 0xB557, 0x743A, 0xB558, 0x742A, 0xB559, 0x7433,
+ 0xB55A, 0x7422, 0xB55B, 0x7425, 0xB55C, 0x7435, 0xB55D, 0x7436, 0xB55E, 0x7434, 0xB55F, 0x742F, 0xB560, 0x741B, 0xB561, 0x7426,
+ 0xB562, 0x7428, 0xB563, 0x7525, 0xB564, 0x7526, 0xB565, 0x756B, 0xB566, 0x756A, 0xB567, 0x75E2, 0xB568, 0x75DB, 0xB569, 0x75E3,
+ 0xB56A, 0x75D9, 0xB56B, 0x75D8, 0xB56C, 0x75DE, 0xB56D, 0x75E0, 0xB56E, 0x767B, 0xB56F, 0x767C, 0xB570, 0x7696, 0xB571, 0x7693,
+ 0xB572, 0x76B4, 0xB573, 0x76DC, 0xB574, 0x774F, 0xB575, 0x77ED, 0xB576, 0x785D, 0xB577, 0x786C, 0xB578, 0x786F, 0xB579, 0x7A0D,
+ 0xB57A, 0x7A08, 0xB57B, 0x7A0B, 0xB57C, 0x7A05, 0xB57D, 0x7A00, 0xB57E, 0x7A98, 0xB5A1, 0x7A97, 0xB5A2, 0x7A96, 0xB5A3, 0x7AE5,
+ 0xB5A4, 0x7AE3, 0xB5A5, 0x7B49, 0xB5A6, 0x7B56, 0xB5A7, 0x7B46, 0xB5A8, 0x7B50, 0xB5A9, 0x7B52, 0xB5AA, 0x7B54, 0xB5AB, 0x7B4D,
+ 0xB5AC, 0x7B4B, 0xB5AD, 0x7B4F, 0xB5AE, 0x7B51, 0xB5AF, 0x7C9F, 0xB5B0, 0x7CA5, 0xB5B1, 0x7D5E, 0xB5B2, 0x7D50, 0xB5B3, 0x7D68,
+ 0xB5B4, 0x7D55, 0xB5B5, 0x7D2B, 0xB5B6, 0x7D6E, 0xB5B7, 0x7D72, 0xB5B8, 0x7D61, 0xB5B9, 0x7D66, 0xB5BA, 0x7D62, 0xB5BB, 0x7D70,
+ 0xB5BC, 0x7D73, 0xB5BD, 0x5584, 0xB5BE, 0x7FD4, 0xB5BF, 0x7FD5, 0xB5C0, 0x800B, 0xB5C1, 0x8052, 0xB5C2, 0x8085, 0xB5C3, 0x8155,
+ 0xB5C4, 0x8154, 0xB5C5, 0x814B, 0xB5C6, 0x8151, 0xB5C7, 0x814E, 0xB5C8, 0x8139, 0xB5C9, 0x8146, 0xB5CA, 0x813E, 0xB5CB, 0x814C,
+ 0xB5CC, 0x8153, 0xB5CD, 0x8174, 0xB5CE, 0x8212, 0xB5CF, 0x821C, 0xB5D0, 0x83E9, 0xB5D1, 0x8403, 0xB5D2, 0x83F8, 0xB5D3, 0x840D,
+ 0xB5D4, 0x83E0, 0xB5D5, 0x83C5, 0xB5D6, 0x840B, 0xB5D7, 0x83C1, 0xB5D8, 0x83EF, 0xB5D9, 0x83F1, 0xB5DA, 0x83F4, 0xB5DB, 0x8457,
+ 0xB5DC, 0x840A, 0xB5DD, 0x83F0, 0xB5DE, 0x840C, 0xB5DF, 0x83CC, 0xB5E0, 0x83FD, 0xB5E1, 0x83F2, 0xB5E2, 0x83CA, 0xB5E3, 0x8438,
+ 0xB5E4, 0x840E, 0xB5E5, 0x8404, 0xB5E6, 0x83DC, 0xB5E7, 0x8407, 0xB5E8, 0x83D4, 0xB5E9, 0x83DF, 0xB5EA, 0x865B, 0xB5EB, 0x86DF,
+ 0xB5EC, 0x86D9, 0xB5ED, 0x86ED, 0xB5EE, 0x86D4, 0xB5EF, 0x86DB, 0xB5F0, 0x86E4, 0xB5F1, 0x86D0, 0xB5F2, 0x86DE, 0xB5F3, 0x8857,
+ 0xB5F4, 0x88C1, 0xB5F5, 0x88C2, 0xB5F6, 0x88B1, 0xB5F7, 0x8983, 0xB5F8, 0x8996, 0xB5F9, 0x8A3B, 0xB5FA, 0x8A60, 0xB5FB, 0x8A55,
+ 0xB5FC, 0x8A5E, 0xB5FD, 0x8A3C, 0xB5FE, 0x8A41, 0xB640, 0x8A54, 0xB641, 0x8A5B, 0xB642, 0x8A50, 0xB643, 0x8A46, 0xB644, 0x8A34,
+ 0xB645, 0x8A3A, 0xB646, 0x8A36, 0xB647, 0x8A56, 0xB648, 0x8C61, 0xB649, 0x8C82, 0xB64A, 0x8CAF, 0xB64B, 0x8CBC, 0xB64C, 0x8CB3,
+ 0xB64D, 0x8CBD, 0xB64E, 0x8CC1, 0xB64F, 0x8CBB, 0xB650, 0x8CC0, 0xB651, 0x8CB4, 0xB652, 0x8CB7, 0xB653, 0x8CB6, 0xB654, 0x8CBF,
+ 0xB655, 0x8CB8, 0xB656, 0x8D8A, 0xB657, 0x8D85, 0xB658, 0x8D81, 0xB659, 0x8DCE, 0xB65A, 0x8DDD, 0xB65B, 0x8DCB, 0xB65C, 0x8DDA,
+ 0xB65D, 0x8DD1, 0xB65E, 0x8DCC, 0xB65F, 0x8DDB, 0xB660, 0x8DC6, 0xB661, 0x8EFB, 0xB662, 0x8EF8, 0xB663, 0x8EFC, 0xB664, 0x8F9C,
+ 0xB665, 0x902E, 0xB666, 0x9035, 0xB667, 0x9031, 0xB668, 0x9038, 0xB669, 0x9032, 0xB66A, 0x9036, 0xB66B, 0x9102, 0xB66C, 0x90F5,
+ 0xB66D, 0x9109, 0xB66E, 0x90FE, 0xB66F, 0x9163, 0xB670, 0x9165, 0xB671, 0x91CF, 0xB672, 0x9214, 0xB673, 0x9215, 0xB674, 0x9223,
+ 0xB675, 0x9209, 0xB676, 0x921E, 0xB677, 0x920D, 0xB678, 0x9210, 0xB679, 0x9207, 0xB67A, 0x9211, 0xB67B, 0x9594, 0xB67C, 0x958F,
+ 0xB67D, 0x958B, 0xB67E, 0x9591, 0xB6A1, 0x9593, 0xB6A2, 0x9592, 0xB6A3, 0x958E, 0xB6A4, 0x968A, 0xB6A5, 0x968E, 0xB6A6, 0x968B,
+ 0xB6A7, 0x967D, 0xB6A8, 0x9685, 0xB6A9, 0x9686, 0xB6AA, 0x968D, 0xB6AB, 0x9672, 0xB6AC, 0x9684, 0xB6AD, 0x96C1, 0xB6AE, 0x96C5,
+ 0xB6AF, 0x96C4, 0xB6B0, 0x96C6, 0xB6B1, 0x96C7, 0xB6B2, 0x96EF, 0xB6B3, 0x96F2, 0xB6B4, 0x97CC, 0xB6B5, 0x9805, 0xB6B6, 0x9806,
+ 0xB6B7, 0x9808, 0xB6B8, 0x98E7, 0xB6B9, 0x98EA, 0xB6BA, 0x98EF, 0xB6BB, 0x98E9, 0xB6BC, 0x98F2, 0xB6BD, 0x98ED, 0xB6BE, 0x99AE,
+ 0xB6BF, 0x99AD, 0xB6C0, 0x9EC3, 0xB6C1, 0x9ECD, 0xB6C2, 0x9ED1, 0xB6C3, 0x4E82, 0xB6C4, 0x50AD, 0xB6C5, 0x50B5, 0xB6C6, 0x50B2,
+ 0xB6C7, 0x50B3, 0xB6C8, 0x50C5, 0xB6C9, 0x50BE, 0xB6CA, 0x50AC, 0xB6CB, 0x50B7, 0xB6CC, 0x50BB, 0xB6CD, 0x50AF, 0xB6CE, 0x50C7,
+ 0xB6CF, 0x527F, 0xB6D0, 0x5277, 0xB6D1, 0x527D, 0xB6D2, 0x52DF, 0xB6D3, 0x52E6, 0xB6D4, 0x52E4, 0xB6D5, 0x52E2, 0xB6D6, 0x52E3,
+ 0xB6D7, 0x532F, 0xB6D8, 0x55DF, 0xB6D9, 0x55E8, 0xB6DA, 0x55D3, 0xB6DB, 0x55E6, 0xB6DC, 0x55CE, 0xB6DD, 0x55DC, 0xB6DE, 0x55C7,
+ 0xB6DF, 0x55D1, 0xB6E0, 0x55E3, 0xB6E1, 0x55E4, 0xB6E2, 0x55EF, 0xB6E3, 0x55DA, 0xB6E4, 0x55E1, 0xB6E5, 0x55C5, 0xB6E6, 0x55C6,
+ 0xB6E7, 0x55E5, 0xB6E8, 0x55C9, 0xB6E9, 0x5712, 0xB6EA, 0x5713, 0xB6EB, 0x585E, 0xB6EC, 0x5851, 0xB6ED, 0x5858, 0xB6EE, 0x5857,
+ 0xB6EF, 0x585A, 0xB6F0, 0x5854, 0xB6F1, 0x586B, 0xB6F2, 0x584C, 0xB6F3, 0x586D, 0xB6F4, 0x584A, 0xB6F5, 0x5862, 0xB6F6, 0x5852,
+ 0xB6F7, 0x584B, 0xB6F8, 0x5967, 0xB6F9, 0x5AC1, 0xB6FA, 0x5AC9, 0xB6FB, 0x5ACC, 0xB6FC, 0x5ABE, 0xB6FD, 0x5ABD, 0xB6FE, 0x5ABC,
+ 0xB740, 0x5AB3, 0xB741, 0x5AC2, 0xB742, 0x5AB2, 0xB743, 0x5D69, 0xB744, 0x5D6F, 0xB745, 0x5E4C, 0xB746, 0x5E79, 0xB747, 0x5EC9,
+ 0xB748, 0x5EC8, 0xB749, 0x5F12, 0xB74A, 0x5F59, 0xB74B, 0x5FAC, 0xB74C, 0x5FAE, 0xB74D, 0x611A, 0xB74E, 0x610F, 0xB74F, 0x6148,
+ 0xB750, 0x611F, 0xB751, 0x60F3, 0xB752, 0x611B, 0xB753, 0x60F9, 0xB754, 0x6101, 0xB755, 0x6108, 0xB756, 0x614E, 0xB757, 0x614C,
+ 0xB758, 0x6144, 0xB759, 0x614D, 0xB75A, 0x613E, 0xB75B, 0x6134, 0xB75C, 0x6127, 0xB75D, 0x610D, 0xB75E, 0x6106, 0xB75F, 0x6137,
+ 0xB760, 0x6221, 0xB761, 0x6222, 0xB762, 0x6413, 0xB763, 0x643E, 0xB764, 0x641E, 0xB765, 0x642A, 0xB766, 0x642D, 0xB767, 0x643D,
+ 0xB768, 0x642C, 0xB769, 0x640F, 0xB76A, 0x641C, 0xB76B, 0x6414, 0xB76C, 0x640D, 0xB76D, 0x6436, 0xB76E, 0x6416, 0xB76F, 0x6417,
+ 0xB770, 0x6406, 0xB771, 0x656C, 0xB772, 0x659F, 0xB773, 0x65B0, 0xB774, 0x6697, 0xB775, 0x6689, 0xB776, 0x6687, 0xB777, 0x6688,
+ 0xB778, 0x6696, 0xB779, 0x6684, 0xB77A, 0x6698, 0xB77B, 0x668D, 0xB77C, 0x6703, 0xB77D, 0x6994, 0xB77E, 0x696D, 0xB7A1, 0x695A,
+ 0xB7A2, 0x6977, 0xB7A3, 0x6960, 0xB7A4, 0x6954, 0xB7A5, 0x6975, 0xB7A6, 0x6930, 0xB7A7, 0x6982, 0xB7A8, 0x694A, 0xB7A9, 0x6968,
+ 0xB7AA, 0x696B, 0xB7AB, 0x695E, 0xB7AC, 0x6953, 0xB7AD, 0x6979, 0xB7AE, 0x6986, 0xB7AF, 0x695D, 0xB7B0, 0x6963, 0xB7B1, 0x695B,
+ 0xB7B2, 0x6B47, 0xB7B3, 0x6B72, 0xB7B4, 0x6BC0, 0xB7B5, 0x6BBF, 0xB7B6, 0x6BD3, 0xB7B7, 0x6BFD, 0xB7B8, 0x6EA2, 0xB7B9, 0x6EAF,
+ 0xB7BA, 0x6ED3, 0xB7BB, 0x6EB6, 0xB7BC, 0x6EC2, 0xB7BD, 0x6E90, 0xB7BE, 0x6E9D, 0xB7BF, 0x6EC7, 0xB7C0, 0x6EC5, 0xB7C1, 0x6EA5,
+ 0xB7C2, 0x6E98, 0xB7C3, 0x6EBC, 0xB7C4, 0x6EBA, 0xB7C5, 0x6EAB, 0xB7C6, 0x6ED1, 0xB7C7, 0x6E96, 0xB7C8, 0x6E9C, 0xB7C9, 0x6EC4,
+ 0xB7CA, 0x6ED4, 0xB7CB, 0x6EAA, 0xB7CC, 0x6EA7, 0xB7CD, 0x6EB4, 0xB7CE, 0x714E, 0xB7CF, 0x7159, 0xB7D0, 0x7169, 0xB7D1, 0x7164,
+ 0xB7D2, 0x7149, 0xB7D3, 0x7167, 0xB7D4, 0x715C, 0xB7D5, 0x716C, 0xB7D6, 0x7166, 0xB7D7, 0x714C, 0xB7D8, 0x7165, 0xB7D9, 0x715E,
+ 0xB7DA, 0x7146, 0xB7DB, 0x7168, 0xB7DC, 0x7156, 0xB7DD, 0x723A, 0xB7DE, 0x7252, 0xB7DF, 0x7337, 0xB7E0, 0x7345, 0xB7E1, 0x733F,
+ 0xB7E2, 0x733E, 0xB7E3, 0x746F, 0xB7E4, 0x745A, 0xB7E5, 0x7455, 0xB7E6, 0x745F, 0xB7E7, 0x745E, 0xB7E8, 0x7441, 0xB7E9, 0x743F,
+ 0xB7EA, 0x7459, 0xB7EB, 0x745B, 0xB7EC, 0x745C, 0xB7ED, 0x7576, 0xB7EE, 0x7578, 0xB7EF, 0x7600, 0xB7F0, 0x75F0, 0xB7F1, 0x7601,
+ 0xB7F2, 0x75F2, 0xB7F3, 0x75F1, 0xB7F4, 0x75FA, 0xB7F5, 0x75FF, 0xB7F6, 0x75F4, 0xB7F7, 0x75F3, 0xB7F8, 0x76DE, 0xB7F9, 0x76DF,
+ 0xB7FA, 0x775B, 0xB7FB, 0x776B, 0xB7FC, 0x7766, 0xB7FD, 0x775E, 0xB7FE, 0x7763, 0xB840, 0x7779, 0xB841, 0x776A, 0xB842, 0x776C,
+ 0xB843, 0x775C, 0xB844, 0x7765, 0xB845, 0x7768, 0xB846, 0x7762, 0xB847, 0x77EE, 0xB848, 0x788E, 0xB849, 0x78B0, 0xB84A, 0x7897,
+ 0xB84B, 0x7898, 0xB84C, 0x788C, 0xB84D, 0x7889, 0xB84E, 0x787C, 0xB84F, 0x7891, 0xB850, 0x7893, 0xB851, 0x787F, 0xB852, 0x797A,
+ 0xB853, 0x797F, 0xB854, 0x7981, 0xB855, 0x842C, 0xB856, 0x79BD, 0xB857, 0x7A1C, 0xB858, 0x7A1A, 0xB859, 0x7A20, 0xB85A, 0x7A14,
+ 0xB85B, 0x7A1F, 0xB85C, 0x7A1E, 0xB85D, 0x7A9F, 0xB85E, 0x7AA0, 0xB85F, 0x7B77, 0xB860, 0x7BC0, 0xB861, 0x7B60, 0xB862, 0x7B6E,
+ 0xB863, 0x7B67, 0xB864, 0x7CB1, 0xB865, 0x7CB3, 0xB866, 0x7CB5, 0xB867, 0x7D93, 0xB868, 0x7D79, 0xB869, 0x7D91, 0xB86A, 0x7D81,
+ 0xB86B, 0x7D8F, 0xB86C, 0x7D5B, 0xB86D, 0x7F6E, 0xB86E, 0x7F69, 0xB86F, 0x7F6A, 0xB870, 0x7F72, 0xB871, 0x7FA9, 0xB872, 0x7FA8,
+ 0xB873, 0x7FA4, 0xB874, 0x8056, 0xB875, 0x8058, 0xB876, 0x8086, 0xB877, 0x8084, 0xB878, 0x8171, 0xB879, 0x8170, 0xB87A, 0x8178,
+ 0xB87B, 0x8165, 0xB87C, 0x816E, 0xB87D, 0x8173, 0xB87E, 0x816B, 0xB8A1, 0x8179, 0xB8A2, 0x817A, 0xB8A3, 0x8166, 0xB8A4, 0x8205,
+ 0xB8A5, 0x8247, 0xB8A6, 0x8482, 0xB8A7, 0x8477, 0xB8A8, 0x843D, 0xB8A9, 0x8431, 0xB8AA, 0x8475, 0xB8AB, 0x8466, 0xB8AC, 0x846B,
+ 0xB8AD, 0x8449, 0xB8AE, 0x846C, 0xB8AF, 0x845B, 0xB8B0, 0x843C, 0xB8B1, 0x8435, 0xB8B2, 0x8461, 0xB8B3, 0x8463, 0xB8B4, 0x8469,
+ 0xB8B5, 0x846D, 0xB8B6, 0x8446, 0xB8B7, 0x865E, 0xB8B8, 0x865C, 0xB8B9, 0x865F, 0xB8BA, 0x86F9, 0xB8BB, 0x8713, 0xB8BC, 0x8708,
+ 0xB8BD, 0x8707, 0xB8BE, 0x8700, 0xB8BF, 0x86FE, 0xB8C0, 0x86FB, 0xB8C1, 0x8702, 0xB8C2, 0x8703, 0xB8C3, 0x8706, 0xB8C4, 0x870A,
+ 0xB8C5, 0x8859, 0xB8C6, 0x88DF, 0xB8C7, 0x88D4, 0xB8C8, 0x88D9, 0xB8C9, 0x88DC, 0xB8CA, 0x88D8, 0xB8CB, 0x88DD, 0xB8CC, 0x88E1,
+ 0xB8CD, 0x88CA, 0xB8CE, 0x88D5, 0xB8CF, 0x88D2, 0xB8D0, 0x899C, 0xB8D1, 0x89E3, 0xB8D2, 0x8A6B, 0xB8D3, 0x8A72, 0xB8D4, 0x8A73,
+ 0xB8D5, 0x8A66, 0xB8D6, 0x8A69, 0xB8D7, 0x8A70, 0xB8D8, 0x8A87, 0xB8D9, 0x8A7C, 0xB8DA, 0x8A63, 0xB8DB, 0x8AA0, 0xB8DC, 0x8A71,
+ 0xB8DD, 0x8A85, 0xB8DE, 0x8A6D, 0xB8DF, 0x8A62, 0xB8E0, 0x8A6E, 0xB8E1, 0x8A6C, 0xB8E2, 0x8A79, 0xB8E3, 0x8A7B, 0xB8E4, 0x8A3E,
+ 0xB8E5, 0x8A68, 0xB8E6, 0x8C62, 0xB8E7, 0x8C8A, 0xB8E8, 0x8C89, 0xB8E9, 0x8CCA, 0xB8EA, 0x8CC7, 0xB8EB, 0x8CC8, 0xB8EC, 0x8CC4,
+ 0xB8ED, 0x8CB2, 0xB8EE, 0x8CC3, 0xB8EF, 0x8CC2, 0xB8F0, 0x8CC5, 0xB8F1, 0x8DE1, 0xB8F2, 0x8DDF, 0xB8F3, 0x8DE8, 0xB8F4, 0x8DEF,
+ 0xB8F5, 0x8DF3, 0xB8F6, 0x8DFA, 0xB8F7, 0x8DEA, 0xB8F8, 0x8DE4, 0xB8F9, 0x8DE6, 0xB8FA, 0x8EB2, 0xB8FB, 0x8F03, 0xB8FC, 0x8F09,
+ 0xB8FD, 0x8EFE, 0xB8FE, 0x8F0A, 0xB940, 0x8F9F, 0xB941, 0x8FB2, 0xB942, 0x904B, 0xB943, 0x904A, 0xB944, 0x9053, 0xB945, 0x9042,
+ 0xB946, 0x9054, 0xB947, 0x903C, 0xB948, 0x9055, 0xB949, 0x9050, 0xB94A, 0x9047, 0xB94B, 0x904F, 0xB94C, 0x904E, 0xB94D, 0x904D,
+ 0xB94E, 0x9051, 0xB94F, 0x903E, 0xB950, 0x9041, 0xB951, 0x9112, 0xB952, 0x9117, 0xB953, 0x916C, 0xB954, 0x916A, 0xB955, 0x9169,
+ 0xB956, 0x91C9, 0xB957, 0x9237, 0xB958, 0x9257, 0xB959, 0x9238, 0xB95A, 0x923D, 0xB95B, 0x9240, 0xB95C, 0x923E, 0xB95D, 0x925B,
+ 0xB95E, 0x924B, 0xB95F, 0x9264, 0xB960, 0x9251, 0xB961, 0x9234, 0xB962, 0x9249, 0xB963, 0x924D, 0xB964, 0x9245, 0xB965, 0x9239,
+ 0xB966, 0x923F, 0xB967, 0x925A, 0xB968, 0x9598, 0xB969, 0x9698, 0xB96A, 0x9694, 0xB96B, 0x9695, 0xB96C, 0x96CD, 0xB96D, 0x96CB,
+ 0xB96E, 0x96C9, 0xB96F, 0x96CA, 0xB970, 0x96F7, 0xB971, 0x96FB, 0xB972, 0x96F9, 0xB973, 0x96F6, 0xB974, 0x9756, 0xB975, 0x9774,
+ 0xB976, 0x9776, 0xB977, 0x9810, 0xB978, 0x9811, 0xB979, 0x9813, 0xB97A, 0x980A, 0xB97B, 0x9812, 0xB97C, 0x980C, 0xB97D, 0x98FC,
+ 0xB97E, 0x98F4, 0xB9A1, 0x98FD, 0xB9A2, 0x98FE, 0xB9A3, 0x99B3, 0xB9A4, 0x99B1, 0xB9A5, 0x99B4, 0xB9A6, 0x9AE1, 0xB9A7, 0x9CE9,
+ 0xB9A8, 0x9E82, 0xB9A9, 0x9F0E, 0xB9AA, 0x9F13, 0xB9AB, 0x9F20, 0xB9AC, 0x50E7, 0xB9AD, 0x50EE, 0xB9AE, 0x50E5, 0xB9AF, 0x50D6,
+ 0xB9B0, 0x50ED, 0xB9B1, 0x50DA, 0xB9B2, 0x50D5, 0xB9B3, 0x50CF, 0xB9B4, 0x50D1, 0xB9B5, 0x50F1, 0xB9B6, 0x50CE, 0xB9B7, 0x50E9,
+ 0xB9B8, 0x5162, 0xB9B9, 0x51F3, 0xB9BA, 0x5283, 0xB9BB, 0x5282, 0xB9BC, 0x5331, 0xB9BD, 0x53AD, 0xB9BE, 0x55FE, 0xB9BF, 0x5600,
+ 0xB9C0, 0x561B, 0xB9C1, 0x5617, 0xB9C2, 0x55FD, 0xB9C3, 0x5614, 0xB9C4, 0x5606, 0xB9C5, 0x5609, 0xB9C6, 0x560D, 0xB9C7, 0x560E,
+ 0xB9C8, 0x55F7, 0xB9C9, 0x5616, 0xB9CA, 0x561F, 0xB9CB, 0x5608, 0xB9CC, 0x5610, 0xB9CD, 0x55F6, 0xB9CE, 0x5718, 0xB9CF, 0x5716,
+ 0xB9D0, 0x5875, 0xB9D1, 0x587E, 0xB9D2, 0x5883, 0xB9D3, 0x5893, 0xB9D4, 0x588A, 0xB9D5, 0x5879, 0xB9D6, 0x5885, 0xB9D7, 0x587D,
+ 0xB9D8, 0x58FD, 0xB9D9, 0x5925, 0xB9DA, 0x5922, 0xB9DB, 0x5924, 0xB9DC, 0x596A, 0xB9DD, 0x5969, 0xB9DE, 0x5AE1, 0xB9DF, 0x5AE6,
+ 0xB9E0, 0x5AE9, 0xB9E1, 0x5AD7, 0xB9E2, 0x5AD6, 0xB9E3, 0x5AD8, 0xB9E4, 0x5AE3, 0xB9E5, 0x5B75, 0xB9E6, 0x5BDE, 0xB9E7, 0x5BE7,
+ 0xB9E8, 0x5BE1, 0xB9E9, 0x5BE5, 0xB9EA, 0x5BE6, 0xB9EB, 0x5BE8, 0xB9EC, 0x5BE2, 0xB9ED, 0x5BE4, 0xB9EE, 0x5BDF, 0xB9EF, 0x5C0D,
+ 0xB9F0, 0x5C62, 0xB9F1, 0x5D84, 0xB9F2, 0x5D87, 0xB9F3, 0x5E5B, 0xB9F4, 0x5E63, 0xB9F5, 0x5E55, 0xB9F6, 0x5E57, 0xB9F7, 0x5E54,
+ 0xB9F8, 0x5ED3, 0xB9F9, 0x5ED6, 0xB9FA, 0x5F0A, 0xB9FB, 0x5F46, 0xB9FC, 0x5F70, 0xB9FD, 0x5FB9, 0xB9FE, 0x6147, 0xBA40, 0x613F,
+ 0xBA41, 0x614B, 0xBA42, 0x6177, 0xBA43, 0x6162, 0xBA44, 0x6163, 0xBA45, 0x615F, 0xBA46, 0x615A, 0xBA47, 0x6158, 0xBA48, 0x6175,
+ 0xBA49, 0x622A, 0xBA4A, 0x6487, 0xBA4B, 0x6458, 0xBA4C, 0x6454, 0xBA4D, 0x64A4, 0xBA4E, 0x6478, 0xBA4F, 0x645F, 0xBA50, 0x647A,
+ 0xBA51, 0x6451, 0xBA52, 0x6467, 0xBA53, 0x6434, 0xBA54, 0x646D, 0xBA55, 0x647B, 0xBA56, 0x6572, 0xBA57, 0x65A1, 0xBA58, 0x65D7,
+ 0xBA59, 0x65D6, 0xBA5A, 0x66A2, 0xBA5B, 0x66A8, 0xBA5C, 0x669D, 0xBA5D, 0x699C, 0xBA5E, 0x69A8, 0xBA5F, 0x6995, 0xBA60, 0x69C1,
+ 0xBA61, 0x69AE, 0xBA62, 0x69D3, 0xBA63, 0x69CB, 0xBA64, 0x699B, 0xBA65, 0x69B7, 0xBA66, 0x69BB, 0xBA67, 0x69AB, 0xBA68, 0x69B4,
+ 0xBA69, 0x69D0, 0xBA6A, 0x69CD, 0xBA6B, 0x69AD, 0xBA6C, 0x69CC, 0xBA6D, 0x69A6, 0xBA6E, 0x69C3, 0xBA6F, 0x69A3, 0xBA70, 0x6B49,
+ 0xBA71, 0x6B4C, 0xBA72, 0x6C33, 0xBA73, 0x6F33, 0xBA74, 0x6F14, 0xBA75, 0x6EFE, 0xBA76, 0x6F13, 0xBA77, 0x6EF4, 0xBA78, 0x6F29,
+ 0xBA79, 0x6F3E, 0xBA7A, 0x6F20, 0xBA7B, 0x6F2C, 0xBA7C, 0x6F0F, 0xBA7D, 0x6F02, 0xBA7E, 0x6F22, 0xBAA1, 0x6EFF, 0xBAA2, 0x6EEF,
+ 0xBAA3, 0x6F06, 0xBAA4, 0x6F31, 0xBAA5, 0x6F38, 0xBAA6, 0x6F32, 0xBAA7, 0x6F23, 0xBAA8, 0x6F15, 0xBAA9, 0x6F2B, 0xBAAA, 0x6F2F,
+ 0xBAAB, 0x6F88, 0xBAAC, 0x6F2A, 0xBAAD, 0x6EEC, 0xBAAE, 0x6F01, 0xBAAF, 0x6EF2, 0xBAB0, 0x6ECC, 0xBAB1, 0x6EF7, 0xBAB2, 0x7194,
+ 0xBAB3, 0x7199, 0xBAB4, 0x717D, 0xBAB5, 0x718A, 0xBAB6, 0x7184, 0xBAB7, 0x7192, 0xBAB8, 0x723E, 0xBAB9, 0x7292, 0xBABA, 0x7296,
+ 0xBABB, 0x7344, 0xBABC, 0x7350, 0xBABD, 0x7464, 0xBABE, 0x7463, 0xBABF, 0x746A, 0xBAC0, 0x7470, 0xBAC1, 0x746D, 0xBAC2, 0x7504,
+ 0xBAC3, 0x7591, 0xBAC4, 0x7627, 0xBAC5, 0x760D, 0xBAC6, 0x760B, 0xBAC7, 0x7609, 0xBAC8, 0x7613, 0xBAC9, 0x76E1, 0xBACA, 0x76E3,
+ 0xBACB, 0x7784, 0xBACC, 0x777D, 0xBACD, 0x777F, 0xBACE, 0x7761, 0xBACF, 0x78C1, 0xBAD0, 0x789F, 0xBAD1, 0x78A7, 0xBAD2, 0x78B3,
+ 0xBAD3, 0x78A9, 0xBAD4, 0x78A3, 0xBAD5, 0x798E, 0xBAD6, 0x798F, 0xBAD7, 0x798D, 0xBAD8, 0x7A2E, 0xBAD9, 0x7A31, 0xBADA, 0x7AAA,
+ 0xBADB, 0x7AA9, 0xBADC, 0x7AED, 0xBADD, 0x7AEF, 0xBADE, 0x7BA1, 0xBADF, 0x7B95, 0xBAE0, 0x7B8B, 0xBAE1, 0x7B75, 0xBAE2, 0x7B97,
+ 0xBAE3, 0x7B9D, 0xBAE4, 0x7B94, 0xBAE5, 0x7B8F, 0xBAE6, 0x7BB8, 0xBAE7, 0x7B87, 0xBAE8, 0x7B84, 0xBAE9, 0x7CB9, 0xBAEA, 0x7CBD,
+ 0xBAEB, 0x7CBE, 0xBAEC, 0x7DBB, 0xBAED, 0x7DB0, 0xBAEE, 0x7D9C, 0xBAEF, 0x7DBD, 0xBAF0, 0x7DBE, 0xBAF1, 0x7DA0, 0xBAF2, 0x7DCA,
+ 0xBAF3, 0x7DB4, 0xBAF4, 0x7DB2, 0xBAF5, 0x7DB1, 0xBAF6, 0x7DBA, 0xBAF7, 0x7DA2, 0xBAF8, 0x7DBF, 0xBAF9, 0x7DB5, 0xBAFA, 0x7DB8,
+ 0xBAFB, 0x7DAD, 0xBAFC, 0x7DD2, 0xBAFD, 0x7DC7, 0xBAFE, 0x7DAC, 0xBB40, 0x7F70, 0xBB41, 0x7FE0, 0xBB42, 0x7FE1, 0xBB43, 0x7FDF,
+ 0xBB44, 0x805E, 0xBB45, 0x805A, 0xBB46, 0x8087, 0xBB47, 0x8150, 0xBB48, 0x8180, 0xBB49, 0x818F, 0xBB4A, 0x8188, 0xBB4B, 0x818A,
+ 0xBB4C, 0x817F, 0xBB4D, 0x8182, 0xBB4E, 0x81E7, 0xBB4F, 0x81FA, 0xBB50, 0x8207, 0xBB51, 0x8214, 0xBB52, 0x821E, 0xBB53, 0x824B,
+ 0xBB54, 0x84C9, 0xBB55, 0x84BF, 0xBB56, 0x84C6, 0xBB57, 0x84C4, 0xBB58, 0x8499, 0xBB59, 0x849E, 0xBB5A, 0x84B2, 0xBB5B, 0x849C,
+ 0xBB5C, 0x84CB, 0xBB5D, 0x84B8, 0xBB5E, 0x84C0, 0xBB5F, 0x84D3, 0xBB60, 0x8490, 0xBB61, 0x84BC, 0xBB62, 0x84D1, 0xBB63, 0x84CA,
+ 0xBB64, 0x873F, 0xBB65, 0x871C, 0xBB66, 0x873B, 0xBB67, 0x8722, 0xBB68, 0x8725, 0xBB69, 0x8734, 0xBB6A, 0x8718, 0xBB6B, 0x8755,
+ 0xBB6C, 0x8737, 0xBB6D, 0x8729, 0xBB6E, 0x88F3, 0xBB6F, 0x8902, 0xBB70, 0x88F4, 0xBB71, 0x88F9, 0xBB72, 0x88F8, 0xBB73, 0x88FD,
+ 0xBB74, 0x88E8, 0xBB75, 0x891A, 0xBB76, 0x88EF, 0xBB77, 0x8AA6, 0xBB78, 0x8A8C, 0xBB79, 0x8A9E, 0xBB7A, 0x8AA3, 0xBB7B, 0x8A8D,
+ 0xBB7C, 0x8AA1, 0xBB7D, 0x8A93, 0xBB7E, 0x8AA4, 0xBBA1, 0x8AAA, 0xBBA2, 0x8AA5, 0xBBA3, 0x8AA8, 0xBBA4, 0x8A98, 0xBBA5, 0x8A91,
+ 0xBBA6, 0x8A9A, 0xBBA7, 0x8AA7, 0xBBA8, 0x8C6A, 0xBBA9, 0x8C8D, 0xBBAA, 0x8C8C, 0xBBAB, 0x8CD3, 0xBBAC, 0x8CD1, 0xBBAD, 0x8CD2,
+ 0xBBAE, 0x8D6B, 0xBBAF, 0x8D99, 0xBBB0, 0x8D95, 0xBBB1, 0x8DFC, 0xBBB2, 0x8F14, 0xBBB3, 0x8F12, 0xBBB4, 0x8F15, 0xBBB5, 0x8F13,
+ 0xBBB6, 0x8FA3, 0xBBB7, 0x9060, 0xBBB8, 0x9058, 0xBBB9, 0x905C, 0xBBBA, 0x9063, 0xBBBB, 0x9059, 0xBBBC, 0x905E, 0xBBBD, 0x9062,
+ 0xBBBE, 0x905D, 0xBBBF, 0x905B, 0xBBC0, 0x9119, 0xBBC1, 0x9118, 0xBBC2, 0x911E, 0xBBC3, 0x9175, 0xBBC4, 0x9178, 0xBBC5, 0x9177,
+ 0xBBC6, 0x9174, 0xBBC7, 0x9278, 0xBBC8, 0x9280, 0xBBC9, 0x9285, 0xBBCA, 0x9298, 0xBBCB, 0x9296, 0xBBCC, 0x927B, 0xBBCD, 0x9293,
+ 0xBBCE, 0x929C, 0xBBCF, 0x92A8, 0xBBD0, 0x927C, 0xBBD1, 0x9291, 0xBBD2, 0x95A1, 0xBBD3, 0x95A8, 0xBBD4, 0x95A9, 0xBBD5, 0x95A3,
+ 0xBBD6, 0x95A5, 0xBBD7, 0x95A4, 0xBBD8, 0x9699, 0xBBD9, 0x969C, 0xBBDA, 0x969B, 0xBBDB, 0x96CC, 0xBBDC, 0x96D2, 0xBBDD, 0x9700,
+ 0xBBDE, 0x977C, 0xBBDF, 0x9785, 0xBBE0, 0x97F6, 0xBBE1, 0x9817, 0xBBE2, 0x9818, 0xBBE3, 0x98AF, 0xBBE4, 0x98B1, 0xBBE5, 0x9903,
+ 0xBBE6, 0x9905, 0xBBE7, 0x990C, 0xBBE8, 0x9909, 0xBBE9, 0x99C1, 0xBBEA, 0x9AAF, 0xBBEB, 0x9AB0, 0xBBEC, 0x9AE6, 0xBBED, 0x9B41,
+ 0xBBEE, 0x9B42, 0xBBEF, 0x9CF4, 0xBBF0, 0x9CF6, 0xBBF1, 0x9CF3, 0xBBF2, 0x9EBC, 0xBBF3, 0x9F3B, 0xBBF4, 0x9F4A, 0xBBF5, 0x5104,
+ 0xBBF6, 0x5100, 0xBBF7, 0x50FB, 0xBBF8, 0x50F5, 0xBBF9, 0x50F9, 0xBBFA, 0x5102, 0xBBFB, 0x5108, 0xBBFC, 0x5109, 0xBBFD, 0x5105,
+ 0xBBFE, 0x51DC, 0xBC40, 0x5287, 0xBC41, 0x5288, 0xBC42, 0x5289, 0xBC43, 0x528D, 0xBC44, 0x528A, 0xBC45, 0x52F0, 0xBC46, 0x53B2,
+ 0xBC47, 0x562E, 0xBC48, 0x563B, 0xBC49, 0x5639, 0xBC4A, 0x5632, 0xBC4B, 0x563F, 0xBC4C, 0x5634, 0xBC4D, 0x5629, 0xBC4E, 0x5653,
+ 0xBC4F, 0x564E, 0xBC50, 0x5657, 0xBC51, 0x5674, 0xBC52, 0x5636, 0xBC53, 0x562F, 0xBC54, 0x5630, 0xBC55, 0x5880, 0xBC56, 0x589F,
+ 0xBC57, 0x589E, 0xBC58, 0x58B3, 0xBC59, 0x589C, 0xBC5A, 0x58AE, 0xBC5B, 0x58A9, 0xBC5C, 0x58A6, 0xBC5D, 0x596D, 0xBC5E, 0x5B09,
+ 0xBC5F, 0x5AFB, 0xBC60, 0x5B0B, 0xBC61, 0x5AF5, 0xBC62, 0x5B0C, 0xBC63, 0x5B08, 0xBC64, 0x5BEE, 0xBC65, 0x5BEC, 0xBC66, 0x5BE9,
+ 0xBC67, 0x5BEB, 0xBC68, 0x5C64, 0xBC69, 0x5C65, 0xBC6A, 0x5D9D, 0xBC6B, 0x5D94, 0xBC6C, 0x5E62, 0xBC6D, 0x5E5F, 0xBC6E, 0x5E61,
+ 0xBC6F, 0x5EE2, 0xBC70, 0x5EDA, 0xBC71, 0x5EDF, 0xBC72, 0x5EDD, 0xBC73, 0x5EE3, 0xBC74, 0x5EE0, 0xBC75, 0x5F48, 0xBC76, 0x5F71,
+ 0xBC77, 0x5FB7, 0xBC78, 0x5FB5, 0xBC79, 0x6176, 0xBC7A, 0x6167, 0xBC7B, 0x616E, 0xBC7C, 0x615D, 0xBC7D, 0x6155, 0xBC7E, 0x6182,
+ 0xBCA1, 0x617C, 0xBCA2, 0x6170, 0xBCA3, 0x616B, 0xBCA4, 0x617E, 0xBCA5, 0x61A7, 0xBCA6, 0x6190, 0xBCA7, 0x61AB, 0xBCA8, 0x618E,
+ 0xBCA9, 0x61AC, 0xBCAA, 0x619A, 0xBCAB, 0x61A4, 0xBCAC, 0x6194, 0xBCAD, 0x61AE, 0xBCAE, 0x622E, 0xBCAF, 0x6469, 0xBCB0, 0x646F,
+ 0xBCB1, 0x6479, 0xBCB2, 0x649E, 0xBCB3, 0x64B2, 0xBCB4, 0x6488, 0xBCB5, 0x6490, 0xBCB6, 0x64B0, 0xBCB7, 0x64A5, 0xBCB8, 0x6493,
+ 0xBCB9, 0x6495, 0xBCBA, 0x64A9, 0xBCBB, 0x6492, 0xBCBC, 0x64AE, 0xBCBD, 0x64AD, 0xBCBE, 0x64AB, 0xBCBF, 0x649A, 0xBCC0, 0x64AC,
+ 0xBCC1, 0x6499, 0xBCC2, 0x64A2, 0xBCC3, 0x64B3, 0xBCC4, 0x6575, 0xBCC5, 0x6577, 0xBCC6, 0x6578, 0xBCC7, 0x66AE, 0xBCC8, 0x66AB,
+ 0xBCC9, 0x66B4, 0xBCCA, 0x66B1, 0xBCCB, 0x6A23, 0xBCCC, 0x6A1F, 0xBCCD, 0x69E8, 0xBCCE, 0x6A01, 0xBCCF, 0x6A1E, 0xBCD0, 0x6A19,
+ 0xBCD1, 0x69FD, 0xBCD2, 0x6A21, 0xBCD3, 0x6A13, 0xBCD4, 0x6A0A, 0xBCD5, 0x69F3, 0xBCD6, 0x6A02, 0xBCD7, 0x6A05, 0xBCD8, 0x69ED,
+ 0xBCD9, 0x6A11, 0xBCDA, 0x6B50, 0xBCDB, 0x6B4E, 0xBCDC, 0x6BA4, 0xBCDD, 0x6BC5, 0xBCDE, 0x6BC6, 0xBCDF, 0x6F3F, 0xBCE0, 0x6F7C,
+ 0xBCE1, 0x6F84, 0xBCE2, 0x6F51, 0xBCE3, 0x6F66, 0xBCE4, 0x6F54, 0xBCE5, 0x6F86, 0xBCE6, 0x6F6D, 0xBCE7, 0x6F5B, 0xBCE8, 0x6F78,
+ 0xBCE9, 0x6F6E, 0xBCEA, 0x6F8E, 0xBCEB, 0x6F7A, 0xBCEC, 0x6F70, 0xBCED, 0x6F64, 0xBCEE, 0x6F97, 0xBCEF, 0x6F58, 0xBCF0, 0x6ED5,
+ 0xBCF1, 0x6F6F, 0xBCF2, 0x6F60, 0xBCF3, 0x6F5F, 0xBCF4, 0x719F, 0xBCF5, 0x71AC, 0xBCF6, 0x71B1, 0xBCF7, 0x71A8, 0xBCF8, 0x7256,
+ 0xBCF9, 0x729B, 0xBCFA, 0x734E, 0xBCFB, 0x7357, 0xBCFC, 0x7469, 0xBCFD, 0x748B, 0xBCFE, 0x7483, 0xBD40, 0x747E, 0xBD41, 0x7480,
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+ 0xBDCC, 0x8AD2, 0xBDCD, 0x8AC7, 0xBDCE, 0x8AC4, 0xBDCF, 0x8A95, 0xBDD0, 0x8ACB, 0xBDD1, 0x8AF8, 0xBDD2, 0x8AB2, 0xBDD3, 0x8AC9,
+ 0xBDD4, 0x8AC2, 0xBDD5, 0x8ABF, 0xBDD6, 0x8AB0, 0xBDD7, 0x8AD6, 0xBDD8, 0x8ACD, 0xBDD9, 0x8AB6, 0xBDDA, 0x8AB9, 0xBDDB, 0x8ADB,
+ 0xBDDC, 0x8C4C, 0xBDDD, 0x8C4E, 0xBDDE, 0x8C6C, 0xBDDF, 0x8CE0, 0xBDE0, 0x8CDE, 0xBDE1, 0x8CE6, 0xBDE2, 0x8CE4, 0xBDE3, 0x8CEC,
+ 0xBDE4, 0x8CED, 0xBDE5, 0x8CE2, 0xBDE6, 0x8CE3, 0xBDE7, 0x8CDC, 0xBDE8, 0x8CEA, 0xBDE9, 0x8CE1, 0xBDEA, 0x8D6D, 0xBDEB, 0x8D9F,
+ 0xBDEC, 0x8DA3, 0xBDED, 0x8E2B, 0xBDEE, 0x8E10, 0xBDEF, 0x8E1D, 0xBDF0, 0x8E22, 0xBDF1, 0x8E0F, 0xBDF2, 0x8E29, 0xBDF3, 0x8E1F,
+ 0xBDF4, 0x8E21, 0xBDF5, 0x8E1E, 0xBDF6, 0x8EBA, 0xBDF7, 0x8F1D, 0xBDF8, 0x8F1B, 0xBDF9, 0x8F1F, 0xBDFA, 0x8F29, 0xBDFB, 0x8F26,
+ 0xBDFC, 0x8F2A, 0xBDFD, 0x8F1C, 0xBDFE, 0x8F1E, 0xBE40, 0x8F25, 0xBE41, 0x9069, 0xBE42, 0x906E, 0xBE43, 0x9068, 0xBE44, 0x906D,
+ 0xBE45, 0x9077, 0xBE46, 0x9130, 0xBE47, 0x912D, 0xBE48, 0x9127, 0xBE49, 0x9131, 0xBE4A, 0x9187, 0xBE4B, 0x9189, 0xBE4C, 0x918B,
+ 0xBE4D, 0x9183, 0xBE4E, 0x92C5, 0xBE4F, 0x92BB, 0xBE50, 0x92B7, 0xBE51, 0x92EA, 0xBE52, 0x92AC, 0xBE53, 0x92E4, 0xBE54, 0x92C1,
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+ 0xBFA2, 0x7E08, 0xBFA3, 0x7E1B, 0xBFA4, 0x7E23, 0xBFA5, 0x7E1E, 0xBFA6, 0x7E1D, 0xBFA7, 0x7E09, 0xBFA8, 0x7E10, 0xBFA9, 0x7F79,
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+ 0xBFEA, 0x8F33, 0xBFEB, 0x8FA8, 0xBFEC, 0x8FA6, 0xBFED, 0x9075, 0xBFEE, 0x9074, 0xBFEF, 0x9078, 0xBFF0, 0x9072, 0xBFF1, 0x907C,
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+ 0xC073, 0x9F8D, 0xC074, 0x9F9C, 0xC075, 0x512A, 0xC076, 0x511F, 0xC077, 0x5121, 0xC078, 0x5132, 0xC079, 0x52F5, 0xC07A, 0x568E,
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+ 0xC0AD, 0x5DBA, 0xC0AE, 0x5DBD, 0xC0AF, 0x5DB8, 0xC0B0, 0x5E6B, 0xC0B1, 0x5F4C, 0xC0B2, 0x5FBD, 0xC0B3, 0x61C9, 0xC0B4, 0x61C2,
+ 0xC0B5, 0x61C7, 0xC0B6, 0x61E6, 0xC0B7, 0x61CB, 0xC0B8, 0x6232, 0xC0B9, 0x6234, 0xC0BA, 0x64CE, 0xC0BB, 0x64CA, 0xC0BC, 0x64D8,
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+ 0xC0CD, 0x6ADB, 0xC0CE, 0x6AA3, 0xC0CF, 0x6A7E, 0xC0D0, 0x6A97, 0xC0D1, 0x6A90, 0xC0D2, 0x6AA0, 0xC0D3, 0x6B5C, 0xC0D4, 0x6BAE,
+ 0xC0D5, 0x6BDA, 0xC0D6, 0x6C08, 0xC0D7, 0x6FD8, 0xC0D8, 0x6FF1, 0xC0D9, 0x6FDF, 0xC0DA, 0x6FE0, 0xC0DB, 0x6FDB, 0xC0DC, 0x6FE4,
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+ 0xC0ED, 0x71F4, 0xC0EE, 0x71E0, 0xC0EF, 0x7235, 0xC0F0, 0x7246, 0xC0F1, 0x7370, 0xC0F2, 0x7372, 0xC0F3, 0x74A9, 0xC0F4, 0x74B0,
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+ 0xC15E, 0x7E43, 0xC15F, 0x7E2B, 0xC160, 0x7E3D, 0xC161, 0x7E31, 0xC162, 0x7E45, 0xC163, 0x7E41, 0xC164, 0x7E34, 0xC165, 0x7E39,
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+ 0xC176, 0x81C0, 0xC177, 0x81BF, 0xC178, 0x81BD, 0xC179, 0x81C9, 0xC17A, 0x81BE, 0xC17B, 0x81E8, 0xC17C, 0x8209, 0xC17D, 0x8271,
+ 0xC17E, 0x85AA, 0xC1A1, 0x8584, 0xC1A2, 0x857E, 0xC1A3, 0x859C, 0xC1A4, 0x8591, 0xC1A5, 0x8594, 0xC1A6, 0x85AF, 0xC1A7, 0x859B,
+ 0xC1A8, 0x8587, 0xC1A9, 0x85A8, 0xC1AA, 0x858A, 0xC1AB, 0x8667, 0xC1AC, 0x87C0, 0xC1AD, 0x87D1, 0xC1AE, 0x87B3, 0xC1AF, 0x87D2,
+ 0xC1B0, 0x87C6, 0xC1B1, 0x87AB, 0xC1B2, 0x87BB, 0xC1B3, 0x87BA, 0xC1B4, 0x87C8, 0xC1B5, 0x87CB, 0xC1B6, 0x893B, 0xC1B7, 0x8936,
+ 0xC1B8, 0x8944, 0xC1B9, 0x8938, 0xC1BA, 0x893D, 0xC1BB, 0x89AC, 0xC1BC, 0x8B0E, 0xC1BD, 0x8B17, 0xC1BE, 0x8B19, 0xC1BF, 0x8B1B,
+ 0xC1C0, 0x8B0A, 0xC1C1, 0x8B20, 0xC1C2, 0x8B1D, 0xC1C3, 0x8B04, 0xC1C4, 0x8B10, 0xC1C5, 0x8C41, 0xC1C6, 0x8C3F, 0xC1C7, 0x8C73,
+ 0xC1C8, 0x8CFA, 0xC1C9, 0x8CFD, 0xC1CA, 0x8CFC, 0xC1CB, 0x8CF8, 0xC1CC, 0x8CFB, 0xC1CD, 0x8DA8, 0xC1CE, 0x8E49, 0xC1CF, 0x8E4B,
+ 0xC1D0, 0x8E48, 0xC1D1, 0x8E4A, 0xC1D2, 0x8F44, 0xC1D3, 0x8F3E, 0xC1D4, 0x8F42, 0xC1D5, 0x8F45, 0xC1D6, 0x8F3F, 0xC1D7, 0x907F,
+ 0xC1D8, 0x907D, 0xC1D9, 0x9084, 0xC1DA, 0x9081, 0xC1DB, 0x9082, 0xC1DC, 0x9080, 0xC1DD, 0x9139, 0xC1DE, 0x91A3, 0xC1DF, 0x919E,
+ 0xC1E0, 0x919C, 0xC1E1, 0x934D, 0xC1E2, 0x9382, 0xC1E3, 0x9328, 0xC1E4, 0x9375, 0xC1E5, 0x934A, 0xC1E6, 0x9365, 0xC1E7, 0x934B,
+ 0xC1E8, 0x9318, 0xC1E9, 0x937E, 0xC1EA, 0x936C, 0xC1EB, 0x935B, 0xC1EC, 0x9370, 0xC1ED, 0x935A, 0xC1EE, 0x9354, 0xC1EF, 0x95CA,
+ 0xC1F0, 0x95CB, 0xC1F1, 0x95CC, 0xC1F2, 0x95C8, 0xC1F3, 0x95C6, 0xC1F4, 0x96B1, 0xC1F5, 0x96B8, 0xC1F6, 0x96D6, 0xC1F7, 0x971C,
+ 0xC1F8, 0x971E, 0xC1F9, 0x97A0, 0xC1FA, 0x97D3, 0xC1FB, 0x9846, 0xC1FC, 0x98B6, 0xC1FD, 0x9935, 0xC1FE, 0x9A01, 0xC240, 0x99FF,
+ 0xC241, 0x9BAE, 0xC242, 0x9BAB, 0xC243, 0x9BAA, 0xC244, 0x9BAD, 0xC245, 0x9D3B, 0xC246, 0x9D3F, 0xC247, 0x9E8B, 0xC248, 0x9ECF,
+ 0xC249, 0x9EDE, 0xC24A, 0x9EDC, 0xC24B, 0x9EDD, 0xC24C, 0x9EDB, 0xC24D, 0x9F3E, 0xC24E, 0x9F4B, 0xC24F, 0x53E2, 0xC250, 0x5695,
+ 0xC251, 0x56AE, 0xC252, 0x58D9, 0xC253, 0x58D8, 0xC254, 0x5B38, 0xC255, 0x5F5D, 0xC256, 0x61E3, 0xC257, 0x6233, 0xC258, 0x64F4,
+ 0xC259, 0x64F2, 0xC25A, 0x64FE, 0xC25B, 0x6506, 0xC25C, 0x64FA, 0xC25D, 0x64FB, 0xC25E, 0x64F7, 0xC25F, 0x65B7, 0xC260, 0x66DC,
+ 0xC261, 0x6726, 0xC262, 0x6AB3, 0xC263, 0x6AAC, 0xC264, 0x6AC3, 0xC265, 0x6ABB, 0xC266, 0x6AB8, 0xC267, 0x6AC2, 0xC268, 0x6AAE,
+ 0xC269, 0x6AAF, 0xC26A, 0x6B5F, 0xC26B, 0x6B78, 0xC26C, 0x6BAF, 0xC26D, 0x7009, 0xC26E, 0x700B, 0xC26F, 0x6FFE, 0xC270, 0x7006,
+ 0xC271, 0x6FFA, 0xC272, 0x7011, 0xC273, 0x700F, 0xC274, 0x71FB, 0xC275, 0x71FC, 0xC276, 0x71FE, 0xC277, 0x71F8, 0xC278, 0x7377,
+ 0xC279, 0x7375, 0xC27A, 0x74A7, 0xC27B, 0x74BF, 0xC27C, 0x7515, 0xC27D, 0x7656, 0xC27E, 0x7658, 0xC2A1, 0x7652, 0xC2A2, 0x77BD,
+ 0xC2A3, 0x77BF, 0xC2A4, 0x77BB, 0xC2A5, 0x77BC, 0xC2A6, 0x790E, 0xC2A7, 0x79AE, 0xC2A8, 0x7A61, 0xC2A9, 0x7A62, 0xC2AA, 0x7A60,
+ 0xC2AB, 0x7AC4, 0xC2AC, 0x7AC5, 0xC2AD, 0x7C2B, 0xC2AE, 0x7C27, 0xC2AF, 0x7C2A, 0xC2B0, 0x7C1E, 0xC2B1, 0x7C23, 0xC2B2, 0x7C21,
+ 0xC2B3, 0x7CE7, 0xC2B4, 0x7E54, 0xC2B5, 0x7E55, 0xC2B6, 0x7E5E, 0xC2B7, 0x7E5A, 0xC2B8, 0x7E61, 0xC2B9, 0x7E52, 0xC2BA, 0x7E59,
+ 0xC2BB, 0x7F48, 0xC2BC, 0x7FF9, 0xC2BD, 0x7FFB, 0xC2BE, 0x8077, 0xC2BF, 0x8076, 0xC2C0, 0x81CD, 0xC2C1, 0x81CF, 0xC2C2, 0x820A,
+ 0xC2C3, 0x85CF, 0xC2C4, 0x85A9, 0xC2C5, 0x85CD, 0xC2C6, 0x85D0, 0xC2C7, 0x85C9, 0xC2C8, 0x85B0, 0xC2C9, 0x85BA, 0xC2CA, 0x85B9,
+ 0xC2CB, 0x85A6, 0xC2CC, 0x87EF, 0xC2CD, 0x87EC, 0xC2CE, 0x87F2, 0xC2CF, 0x87E0, 0xC2D0, 0x8986, 0xC2D1, 0x89B2, 0xC2D2, 0x89F4,
+ 0xC2D3, 0x8B28, 0xC2D4, 0x8B39, 0xC2D5, 0x8B2C, 0xC2D6, 0x8B2B, 0xC2D7, 0x8C50, 0xC2D8, 0x8D05, 0xC2D9, 0x8E59, 0xC2DA, 0x8E63,
+ 0xC2DB, 0x8E66, 0xC2DC, 0x8E64, 0xC2DD, 0x8E5F, 0xC2DE, 0x8E55, 0xC2DF, 0x8EC0, 0xC2E0, 0x8F49, 0xC2E1, 0x8F4D, 0xC2E2, 0x9087,
+ 0xC2E3, 0x9083, 0xC2E4, 0x9088, 0xC2E5, 0x91AB, 0xC2E6, 0x91AC, 0xC2E7, 0x91D0, 0xC2E8, 0x9394, 0xC2E9, 0x938A, 0xC2EA, 0x9396,
+ 0xC2EB, 0x93A2, 0xC2EC, 0x93B3, 0xC2ED, 0x93AE, 0xC2EE, 0x93AC, 0xC2EF, 0x93B0, 0xC2F0, 0x9398, 0xC2F1, 0x939A, 0xC2F2, 0x9397,
+ 0xC2F3, 0x95D4, 0xC2F4, 0x95D6, 0xC2F5, 0x95D0, 0xC2F6, 0x95D5, 0xC2F7, 0x96E2, 0xC2F8, 0x96DC, 0xC2F9, 0x96D9, 0xC2FA, 0x96DB,
+ 0xC2FB, 0x96DE, 0xC2FC, 0x9724, 0xC2FD, 0x97A3, 0xC2FE, 0x97A6, 0xC340, 0x97AD, 0xC341, 0x97F9, 0xC342, 0x984D, 0xC343, 0x984F,
+ 0xC344, 0x984C, 0xC345, 0x984E, 0xC346, 0x9853, 0xC347, 0x98BA, 0xC348, 0x993E, 0xC349, 0x993F, 0xC34A, 0x993D, 0xC34B, 0x992E,
+ 0xC34C, 0x99A5, 0xC34D, 0x9A0E, 0xC34E, 0x9AC1, 0xC34F, 0x9B03, 0xC350, 0x9B06, 0xC351, 0x9B4F, 0xC352, 0x9B4E, 0xC353, 0x9B4D,
+ 0xC354, 0x9BCA, 0xC355, 0x9BC9, 0xC356, 0x9BFD, 0xC357, 0x9BC8, 0xC358, 0x9BC0, 0xC359, 0x9D51, 0xC35A, 0x9D5D, 0xC35B, 0x9D60,
+ 0xC35C, 0x9EE0, 0xC35D, 0x9F15, 0xC35E, 0x9F2C, 0xC35F, 0x5133, 0xC360, 0x56A5, 0xC361, 0x58DE, 0xC362, 0x58DF, 0xC363, 0x58E2,
+ 0xC364, 0x5BF5, 0xC365, 0x9F90, 0xC366, 0x5EEC, 0xC367, 0x61F2, 0xC368, 0x61F7, 0xC369, 0x61F6, 0xC36A, 0x61F5, 0xC36B, 0x6500,
+ 0xC36C, 0x650F, 0xC36D, 0x66E0, 0xC36E, 0x66DD, 0xC36F, 0x6AE5, 0xC370, 0x6ADD, 0xC371, 0x6ADA, 0xC372, 0x6AD3, 0xC373, 0x701B,
+ 0xC374, 0x701F, 0xC375, 0x7028, 0xC376, 0x701A, 0xC377, 0x701D, 0xC378, 0x7015, 0xC379, 0x7018, 0xC37A, 0x7206, 0xC37B, 0x720D,
+ 0xC37C, 0x7258, 0xC37D, 0x72A2, 0xC37E, 0x7378, 0xC3A1, 0x737A, 0xC3A2, 0x74BD, 0xC3A3, 0x74CA, 0xC3A4, 0x74E3, 0xC3A5, 0x7587,
+ 0xC3A6, 0x7586, 0xC3A7, 0x765F, 0xC3A8, 0x7661, 0xC3A9, 0x77C7, 0xC3AA, 0x7919, 0xC3AB, 0x79B1, 0xC3AC, 0x7A6B, 0xC3AD, 0x7A69,
+ 0xC3AE, 0x7C3E, 0xC3AF, 0x7C3F, 0xC3B0, 0x7C38, 0xC3B1, 0x7C3D, 0xC3B2, 0x7C37, 0xC3B3, 0x7C40, 0xC3B4, 0x7E6B, 0xC3B5, 0x7E6D,
+ 0xC3B6, 0x7E79, 0xC3B7, 0x7E69, 0xC3B8, 0x7E6A, 0xC3B9, 0x7F85, 0xC3BA, 0x7E73, 0xC3BB, 0x7FB6, 0xC3BC, 0x7FB9, 0xC3BD, 0x7FB8,
+ 0xC3BE, 0x81D8, 0xC3BF, 0x85E9, 0xC3C0, 0x85DD, 0xC3C1, 0x85EA, 0xC3C2, 0x85D5, 0xC3C3, 0x85E4, 0xC3C4, 0x85E5, 0xC3C5, 0x85F7,
+ 0xC3C6, 0x87FB, 0xC3C7, 0x8805, 0xC3C8, 0x880D, 0xC3C9, 0x87F9, 0xC3CA, 0x87FE, 0xC3CB, 0x8960, 0xC3CC, 0x895F, 0xC3CD, 0x8956,
+ 0xC3CE, 0x895E, 0xC3CF, 0x8B41, 0xC3D0, 0x8B5C, 0xC3D1, 0x8B58, 0xC3D2, 0x8B49, 0xC3D3, 0x8B5A, 0xC3D4, 0x8B4E, 0xC3D5, 0x8B4F,
+ 0xC3D6, 0x8B46, 0xC3D7, 0x8B59, 0xC3D8, 0x8D08, 0xC3D9, 0x8D0A, 0xC3DA, 0x8E7C, 0xC3DB, 0x8E72, 0xC3DC, 0x8E87, 0xC3DD, 0x8E76,
+ 0xC3DE, 0x8E6C, 0xC3DF, 0x8E7A, 0xC3E0, 0x8E74, 0xC3E1, 0x8F54, 0xC3E2, 0x8F4E, 0xC3E3, 0x8FAD, 0xC3E4, 0x908A, 0xC3E5, 0x908B,
+ 0xC3E6, 0x91B1, 0xC3E7, 0x91AE, 0xC3E8, 0x93E1, 0xC3E9, 0x93D1, 0xC3EA, 0x93DF, 0xC3EB, 0x93C3, 0xC3EC, 0x93C8, 0xC3ED, 0x93DC,
+ 0xC3EE, 0x93DD, 0xC3EF, 0x93D6, 0xC3F0, 0x93E2, 0xC3F1, 0x93CD, 0xC3F2, 0x93D8, 0xC3F3, 0x93E4, 0xC3F4, 0x93D7, 0xC3F5, 0x93E8,
+ 0xC3F6, 0x95DC, 0xC3F7, 0x96B4, 0xC3F8, 0x96E3, 0xC3F9, 0x972A, 0xC3FA, 0x9727, 0xC3FB, 0x9761, 0xC3FC, 0x97DC, 0xC3FD, 0x97FB,
+ 0xC3FE, 0x985E, 0xC440, 0x9858, 0xC441, 0x985B, 0xC442, 0x98BC, 0xC443, 0x9945, 0xC444, 0x9949, 0xC445, 0x9A16, 0xC446, 0x9A19,
+ 0xC447, 0x9B0D, 0xC448, 0x9BE8, 0xC449, 0x9BE7, 0xC44A, 0x9BD6, 0xC44B, 0x9BDB, 0xC44C, 0x9D89, 0xC44D, 0x9D61, 0xC44E, 0x9D72,
+ 0xC44F, 0x9D6A, 0xC450, 0x9D6C, 0xC451, 0x9E92, 0xC452, 0x9E97, 0xC453, 0x9E93, 0xC454, 0x9EB4, 0xC455, 0x52F8, 0xC456, 0x56A8,
+ 0xC457, 0x56B7, 0xC458, 0x56B6, 0xC459, 0x56B4, 0xC45A, 0x56BC, 0xC45B, 0x58E4, 0xC45C, 0x5B40, 0xC45D, 0x5B43, 0xC45E, 0x5B7D,
+ 0xC45F, 0x5BF6, 0xC460, 0x5DC9, 0xC461, 0x61F8, 0xC462, 0x61FA, 0xC463, 0x6518, 0xC464, 0x6514, 0xC465, 0x6519, 0xC466, 0x66E6,
+ 0xC467, 0x6727, 0xC468, 0x6AEC, 0xC469, 0x703E, 0xC46A, 0x7030, 0xC46B, 0x7032, 0xC46C, 0x7210, 0xC46D, 0x737B, 0xC46E, 0x74CF,
+ 0xC46F, 0x7662, 0xC470, 0x7665, 0xC471, 0x7926, 0xC472, 0x792A, 0xC473, 0x792C, 0xC474, 0x792B, 0xC475, 0x7AC7, 0xC476, 0x7AF6,
+ 0xC477, 0x7C4C, 0xC478, 0x7C43, 0xC479, 0x7C4D, 0xC47A, 0x7CEF, 0xC47B, 0x7CF0, 0xC47C, 0x8FAE, 0xC47D, 0x7E7D, 0xC47E, 0x7E7C,
+ 0xC4A1, 0x7E82, 0xC4A2, 0x7F4C, 0xC4A3, 0x8000, 0xC4A4, 0x81DA, 0xC4A5, 0x8266, 0xC4A6, 0x85FB, 0xC4A7, 0x85F9, 0xC4A8, 0x8611,
+ 0xC4A9, 0x85FA, 0xC4AA, 0x8606, 0xC4AB, 0x860B, 0xC4AC, 0x8607, 0xC4AD, 0x860A, 0xC4AE, 0x8814, 0xC4AF, 0x8815, 0xC4B0, 0x8964,
+ 0xC4B1, 0x89BA, 0xC4B2, 0x89F8, 0xC4B3, 0x8B70, 0xC4B4, 0x8B6C, 0xC4B5, 0x8B66, 0xC4B6, 0x8B6F, 0xC4B7, 0x8B5F, 0xC4B8, 0x8B6B,
+ 0xC4B9, 0x8D0F, 0xC4BA, 0x8D0D, 0xC4BB, 0x8E89, 0xC4BC, 0x8E81, 0xC4BD, 0x8E85, 0xC4BE, 0x8E82, 0xC4BF, 0x91B4, 0xC4C0, 0x91CB,
+ 0xC4C1, 0x9418, 0xC4C2, 0x9403, 0xC4C3, 0x93FD, 0xC4C4, 0x95E1, 0xC4C5, 0x9730, 0xC4C6, 0x98C4, 0xC4C7, 0x9952, 0xC4C8, 0x9951,
+ 0xC4C9, 0x99A8, 0xC4CA, 0x9A2B, 0xC4CB, 0x9A30, 0xC4CC, 0x9A37, 0xC4CD, 0x9A35, 0xC4CE, 0x9C13, 0xC4CF, 0x9C0D, 0xC4D0, 0x9E79,
+ 0xC4D1, 0x9EB5, 0xC4D2, 0x9EE8, 0xC4D3, 0x9F2F, 0xC4D4, 0x9F5F, 0xC4D5, 0x9F63, 0xC4D6, 0x9F61, 0xC4D7, 0x5137, 0xC4D8, 0x5138,
+ 0xC4D9, 0x56C1, 0xC4DA, 0x56C0, 0xC4DB, 0x56C2, 0xC4DC, 0x5914, 0xC4DD, 0x5C6C, 0xC4DE, 0x5DCD, 0xC4DF, 0x61FC, 0xC4E0, 0x61FE,
+ 0xC4E1, 0x651D, 0xC4E2, 0x651C, 0xC4E3, 0x6595, 0xC4E4, 0x66E9, 0xC4E5, 0x6AFB, 0xC4E6, 0x6B04, 0xC4E7, 0x6AFA, 0xC4E8, 0x6BB2,
+ 0xC4E9, 0x704C, 0xC4EA, 0x721B, 0xC4EB, 0x72A7, 0xC4EC, 0x74D6, 0xC4ED, 0x74D4, 0xC4EE, 0x7669, 0xC4EF, 0x77D3, 0xC4F0, 0x7C50,
+ 0xC4F1, 0x7E8F, 0xC4F2, 0x7E8C, 0xC4F3, 0x7FBC, 0xC4F4, 0x8617, 0xC4F5, 0x862D, 0xC4F6, 0x861A, 0xC4F7, 0x8823, 0xC4F8, 0x8822,
+ 0xC4F9, 0x8821, 0xC4FA, 0x881F, 0xC4FB, 0x896A, 0xC4FC, 0x896C, 0xC4FD, 0x89BD, 0xC4FE, 0x8B74, 0xC540, 0x8B77, 0xC541, 0x8B7D,
+ 0xC542, 0x8D13, 0xC543, 0x8E8A, 0xC544, 0x8E8D, 0xC545, 0x8E8B, 0xC546, 0x8F5F, 0xC547, 0x8FAF, 0xC548, 0x91BA, 0xC549, 0x942E,
+ 0xC54A, 0x9433, 0xC54B, 0x9435, 0xC54C, 0x943A, 0xC54D, 0x9438, 0xC54E, 0x9432, 0xC54F, 0x942B, 0xC550, 0x95E2, 0xC551, 0x9738,
+ 0xC552, 0x9739, 0xC553, 0x9732, 0xC554, 0x97FF, 0xC555, 0x9867, 0xC556, 0x9865, 0xC557, 0x9957, 0xC558, 0x9A45, 0xC559, 0x9A43,
+ 0xC55A, 0x9A40, 0xC55B, 0x9A3E, 0xC55C, 0x9ACF, 0xC55D, 0x9B54, 0xC55E, 0x9B51, 0xC55F, 0x9C2D, 0xC560, 0x9C25, 0xC561, 0x9DAF,
+ 0xC562, 0x9DB4, 0xC563, 0x9DC2, 0xC564, 0x9DB8, 0xC565, 0x9E9D, 0xC566, 0x9EEF, 0xC567, 0x9F19, 0xC568, 0x9F5C, 0xC569, 0x9F66,
+ 0xC56A, 0x9F67, 0xC56B, 0x513C, 0xC56C, 0x513B, 0xC56D, 0x56C8, 0xC56E, 0x56CA, 0xC56F, 0x56C9, 0xC570, 0x5B7F, 0xC571, 0x5DD4,
+ 0xC572, 0x5DD2, 0xC573, 0x5F4E, 0xC574, 0x61FF, 0xC575, 0x6524, 0xC576, 0x6B0A, 0xC577, 0x6B61, 0xC578, 0x7051, 0xC579, 0x7058,
+ 0xC57A, 0x7380, 0xC57B, 0x74E4, 0xC57C, 0x758A, 0xC57D, 0x766E, 0xC57E, 0x766C, 0xC5A1, 0x79B3, 0xC5A2, 0x7C60, 0xC5A3, 0x7C5F,
+ 0xC5A4, 0x807E, 0xC5A5, 0x807D, 0xC5A6, 0x81DF, 0xC5A7, 0x8972, 0xC5A8, 0x896F, 0xC5A9, 0x89FC, 0xC5AA, 0x8B80, 0xC5AB, 0x8D16,
+ 0xC5AC, 0x8D17, 0xC5AD, 0x8E91, 0xC5AE, 0x8E93, 0xC5AF, 0x8F61, 0xC5B0, 0x9148, 0xC5B1, 0x9444, 0xC5B2, 0x9451, 0xC5B3, 0x9452,
+ 0xC5B4, 0x973D, 0xC5B5, 0x973E, 0xC5B6, 0x97C3, 0xC5B7, 0x97C1, 0xC5B8, 0x986B, 0xC5B9, 0x9955, 0xC5BA, 0x9A55, 0xC5BB, 0x9A4D,
+ 0xC5BC, 0x9AD2, 0xC5BD, 0x9B1A, 0xC5BE, 0x9C49, 0xC5BF, 0x9C31, 0xC5C0, 0x9C3E, 0xC5C1, 0x9C3B, 0xC5C2, 0x9DD3, 0xC5C3, 0x9DD7,
+ 0xC5C4, 0x9F34, 0xC5C5, 0x9F6C, 0xC5C6, 0x9F6A, 0xC5C7, 0x9F94, 0xC5C8, 0x56CC, 0xC5C9, 0x5DD6, 0xC5CA, 0x6200, 0xC5CB, 0x6523,
+ 0xC5CC, 0x652B, 0xC5CD, 0x652A, 0xC5CE, 0x66EC, 0xC5CF, 0x6B10, 0xC5D0, 0x74DA, 0xC5D1, 0x7ACA, 0xC5D2, 0x7C64, 0xC5D3, 0x7C63,
+ 0xC5D4, 0x7C65, 0xC5D5, 0x7E93, 0xC5D6, 0x7E96, 0xC5D7, 0x7E94, 0xC5D8, 0x81E2, 0xC5D9, 0x8638, 0xC5DA, 0x863F, 0xC5DB, 0x8831,
+ 0xC5DC, 0x8B8A, 0xC5DD, 0x9090, 0xC5DE, 0x908F, 0xC5DF, 0x9463, 0xC5E0, 0x9460, 0xC5E1, 0x9464, 0xC5E2, 0x9768, 0xC5E3, 0x986F,
+ 0xC5E4, 0x995C, 0xC5E5, 0x9A5A, 0xC5E6, 0x9A5B, 0xC5E7, 0x9A57, 0xC5E8, 0x9AD3, 0xC5E9, 0x9AD4, 0xC5EA, 0x9AD1, 0xC5EB, 0x9C54,
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+ 0xD1B8, 0x6343, 0xD1B9, 0x63E4, 0xD1BA, 0x6339, 0xD1BB, 0x634B, 0xD1BC, 0x634A, 0xD1BD, 0x633C, 0xD1BE, 0x6329, 0xD1BF, 0x6341,
+ 0xD1C0, 0x6334, 0xD1C1, 0x6358, 0xD1C2, 0x6354, 0xD1C3, 0x6359, 0xD1C4, 0x632D, 0xD1C5, 0x6347, 0xD1C6, 0x6333, 0xD1C7, 0x635A,
+ 0xD1C8, 0x6351, 0xD1C9, 0x6338, 0xD1CA, 0x6357, 0xD1CB, 0x6340, 0xD1CC, 0x6348, 0xD1CD, 0x654A, 0xD1CE, 0x6546, 0xD1CF, 0x65C6,
+ 0xD1D0, 0x65C3, 0xD1D1, 0x65C4, 0xD1D2, 0x65C2, 0xD1D3, 0x664A, 0xD1D4, 0x665F, 0xD1D5, 0x6647, 0xD1D6, 0x6651, 0xD1D7, 0x6712,
+ 0xD1D8, 0x6713, 0xD1D9, 0x681F, 0xD1DA, 0x681A, 0xD1DB, 0x6849, 0xD1DC, 0x6832, 0xD1DD, 0x6833, 0xD1DE, 0x683B, 0xD1DF, 0x684B,
+ 0xD1E0, 0x684F, 0xD1E1, 0x6816, 0xD1E2, 0x6831, 0xD1E3, 0x681C, 0xD1E4, 0x6835, 0xD1E5, 0x682B, 0xD1E6, 0x682D, 0xD1E7, 0x682F,
+ 0xD1E8, 0x684E, 0xD1E9, 0x6844, 0xD1EA, 0x6834, 0xD1EB, 0x681D, 0xD1EC, 0x6812, 0xD1ED, 0x6814, 0xD1EE, 0x6826, 0xD1EF, 0x6828,
+ 0xD1F0, 0x682E, 0xD1F1, 0x684D, 0xD1F2, 0x683A, 0xD1F3, 0x6825, 0xD1F4, 0x6820, 0xD1F5, 0x6B2C, 0xD1F6, 0x6B2F, 0xD1F7, 0x6B2D,
+ 0xD1F8, 0x6B31, 0xD1F9, 0x6B34, 0xD1FA, 0x6B6D, 0xD1FB, 0x8082, 0xD1FC, 0x6B88, 0xD1FD, 0x6BE6, 0xD1FE, 0x6BE4, 0xD240, 0x6BE8,
+ 0xD241, 0x6BE3, 0xD242, 0x6BE2, 0xD243, 0x6BE7, 0xD244, 0x6C25, 0xD245, 0x6D7A, 0xD246, 0x6D63, 0xD247, 0x6D64, 0xD248, 0x6D76,
+ 0xD249, 0x6D0D, 0xD24A, 0x6D61, 0xD24B, 0x6D92, 0xD24C, 0x6D58, 0xD24D, 0x6D62, 0xD24E, 0x6D6D, 0xD24F, 0x6D6F, 0xD250, 0x6D91,
+ 0xD251, 0x6D8D, 0xD252, 0x6DEF, 0xD253, 0x6D7F, 0xD254, 0x6D86, 0xD255, 0x6D5E, 0xD256, 0x6D67, 0xD257, 0x6D60, 0xD258, 0x6D97,
+ 0xD259, 0x6D70, 0xD25A, 0x6D7C, 0xD25B, 0x6D5F, 0xD25C, 0x6D82, 0xD25D, 0x6D98, 0xD25E, 0x6D2F, 0xD25F, 0x6D68, 0xD260, 0x6D8B,
+ 0xD261, 0x6D7E, 0xD262, 0x6D80, 0xD263, 0x6D84, 0xD264, 0x6D16, 0xD265, 0x6D83, 0xD266, 0x6D7B, 0xD267, 0x6D7D, 0xD268, 0x6D75,
+ 0xD269, 0x6D90, 0xD26A, 0x70DC, 0xD26B, 0x70D3, 0xD26C, 0x70D1, 0xD26D, 0x70DD, 0xD26E, 0x70CB, 0xD26F, 0x7F39, 0xD270, 0x70E2,
+ 0xD271, 0x70D7, 0xD272, 0x70D2, 0xD273, 0x70DE, 0xD274, 0x70E0, 0xD275, 0x70D4, 0xD276, 0x70CD, 0xD277, 0x70C5, 0xD278, 0x70C6,
+ 0xD279, 0x70C7, 0xD27A, 0x70DA, 0xD27B, 0x70CE, 0xD27C, 0x70E1, 0xD27D, 0x7242, 0xD27E, 0x7278, 0xD2A1, 0x7277, 0xD2A2, 0x7276,
+ 0xD2A3, 0x7300, 0xD2A4, 0x72FA, 0xD2A5, 0x72F4, 0xD2A6, 0x72FE, 0xD2A7, 0x72F6, 0xD2A8, 0x72F3, 0xD2A9, 0x72FB, 0xD2AA, 0x7301,
+ 0xD2AB, 0x73D3, 0xD2AC, 0x73D9, 0xD2AD, 0x73E5, 0xD2AE, 0x73D6, 0xD2AF, 0x73BC, 0xD2B0, 0x73E7, 0xD2B1, 0x73E3, 0xD2B2, 0x73E9,
+ 0xD2B3, 0x73DC, 0xD2B4, 0x73D2, 0xD2B5, 0x73DB, 0xD2B6, 0x73D4, 0xD2B7, 0x73DD, 0xD2B8, 0x73DA, 0xD2B9, 0x73D7, 0xD2BA, 0x73D8,
+ 0xD2BB, 0x73E8, 0xD2BC, 0x74DE, 0xD2BD, 0x74DF, 0xD2BE, 0x74F4, 0xD2BF, 0x74F5, 0xD2C0, 0x7521, 0xD2C1, 0x755B, 0xD2C2, 0x755F,
+ 0xD2C3, 0x75B0, 0xD2C4, 0x75C1, 0xD2C5, 0x75BB, 0xD2C6, 0x75C4, 0xD2C7, 0x75C0, 0xD2C8, 0x75BF, 0xD2C9, 0x75B6, 0xD2CA, 0x75BA,
+ 0xD2CB, 0x768A, 0xD2CC, 0x76C9, 0xD2CD, 0x771D, 0xD2CE, 0x771B, 0xD2CF, 0x7710, 0xD2D0, 0x7713, 0xD2D1, 0x7712, 0xD2D2, 0x7723,
+ 0xD2D3, 0x7711, 0xD2D4, 0x7715, 0xD2D5, 0x7719, 0xD2D6, 0x771A, 0xD2D7, 0x7722, 0xD2D8, 0x7727, 0xD2D9, 0x7823, 0xD2DA, 0x782C,
+ 0xD2DB, 0x7822, 0xD2DC, 0x7835, 0xD2DD, 0x782F, 0xD2DE, 0x7828, 0xD2DF, 0x782E, 0xD2E0, 0x782B, 0xD2E1, 0x7821, 0xD2E2, 0x7829,
+ 0xD2E3, 0x7833, 0xD2E4, 0x782A, 0xD2E5, 0x7831, 0xD2E6, 0x7954, 0xD2E7, 0x795B, 0xD2E8, 0x794F, 0xD2E9, 0x795C, 0xD2EA, 0x7953,
+ 0xD2EB, 0x7952, 0xD2EC, 0x7951, 0xD2ED, 0x79EB, 0xD2EE, 0x79EC, 0xD2EF, 0x79E0, 0xD2F0, 0x79EE, 0xD2F1, 0x79ED, 0xD2F2, 0x79EA,
+ 0xD2F3, 0x79DC, 0xD2F4, 0x79DE, 0xD2F5, 0x79DD, 0xD2F6, 0x7A86, 0xD2F7, 0x7A89, 0xD2F8, 0x7A85, 0xD2F9, 0x7A8B, 0xD2FA, 0x7A8C,
+ 0xD2FB, 0x7A8A, 0xD2FC, 0x7A87, 0xD2FD, 0x7AD8, 0xD2FE, 0x7B10, 0xD340, 0x7B04, 0xD341, 0x7B13, 0xD342, 0x7B05, 0xD343, 0x7B0F,
+ 0xD344, 0x7B08, 0xD345, 0x7B0A, 0xD346, 0x7B0E, 0xD347, 0x7B09, 0xD348, 0x7B12, 0xD349, 0x7C84, 0xD34A, 0x7C91, 0xD34B, 0x7C8A,
+ 0xD34C, 0x7C8C, 0xD34D, 0x7C88, 0xD34E, 0x7C8D, 0xD34F, 0x7C85, 0xD350, 0x7D1E, 0xD351, 0x7D1D, 0xD352, 0x7D11, 0xD353, 0x7D0E,
+ 0xD354, 0x7D18, 0xD355, 0x7D16, 0xD356, 0x7D13, 0xD357, 0x7D1F, 0xD358, 0x7D12, 0xD359, 0x7D0F, 0xD35A, 0x7D0C, 0xD35B, 0x7F5C,
+ 0xD35C, 0x7F61, 0xD35D, 0x7F5E, 0xD35E, 0x7F60, 0xD35F, 0x7F5D, 0xD360, 0x7F5B, 0xD361, 0x7F96, 0xD362, 0x7F92, 0xD363, 0x7FC3,
+ 0xD364, 0x7FC2, 0xD365, 0x7FC0, 0xD366, 0x8016, 0xD367, 0x803E, 0xD368, 0x8039, 0xD369, 0x80FA, 0xD36A, 0x80F2, 0xD36B, 0x80F9,
+ 0xD36C, 0x80F5, 0xD36D, 0x8101, 0xD36E, 0x80FB, 0xD36F, 0x8100, 0xD370, 0x8201, 0xD371, 0x822F, 0xD372, 0x8225, 0xD373, 0x8333,
+ 0xD374, 0x832D, 0xD375, 0x8344, 0xD376, 0x8319, 0xD377, 0x8351, 0xD378, 0x8325, 0xD379, 0x8356, 0xD37A, 0x833F, 0xD37B, 0x8341,
+ 0xD37C, 0x8326, 0xD37D, 0x831C, 0xD37E, 0x8322, 0xD3A1, 0x8342, 0xD3A2, 0x834E, 0xD3A3, 0x831B, 0xD3A4, 0x832A, 0xD3A5, 0x8308,
+ 0xD3A6, 0x833C, 0xD3A7, 0x834D, 0xD3A8, 0x8316, 0xD3A9, 0x8324, 0xD3AA, 0x8320, 0xD3AB, 0x8337, 0xD3AC, 0x832F, 0xD3AD, 0x8329,
+ 0xD3AE, 0x8347, 0xD3AF, 0x8345, 0xD3B0, 0x834C, 0xD3B1, 0x8353, 0xD3B2, 0x831E, 0xD3B3, 0x832C, 0xD3B4, 0x834B, 0xD3B5, 0x8327,
+ 0xD3B6, 0x8348, 0xD3B7, 0x8653, 0xD3B8, 0x8652, 0xD3B9, 0x86A2, 0xD3BA, 0x86A8, 0xD3BB, 0x8696, 0xD3BC, 0x868D, 0xD3BD, 0x8691,
+ 0xD3BE, 0x869E, 0xD3BF, 0x8687, 0xD3C0, 0x8697, 0xD3C1, 0x8686, 0xD3C2, 0x868B, 0xD3C3, 0x869A, 0xD3C4, 0x8685, 0xD3C5, 0x86A5,
+ 0xD3C6, 0x8699, 0xD3C7, 0x86A1, 0xD3C8, 0x86A7, 0xD3C9, 0x8695, 0xD3CA, 0x8698, 0xD3CB, 0x868E, 0xD3CC, 0x869D, 0xD3CD, 0x8690,
+ 0xD3CE, 0x8694, 0xD3CF, 0x8843, 0xD3D0, 0x8844, 0xD3D1, 0x886D, 0xD3D2, 0x8875, 0xD3D3, 0x8876, 0xD3D4, 0x8872, 0xD3D5, 0x8880,
+ 0xD3D6, 0x8871, 0xD3D7, 0x887F, 0xD3D8, 0x886F, 0xD3D9, 0x8883, 0xD3DA, 0x887E, 0xD3DB, 0x8874, 0xD3DC, 0x887C, 0xD3DD, 0x8A12,
+ 0xD3DE, 0x8C47, 0xD3DF, 0x8C57, 0xD3E0, 0x8C7B, 0xD3E1, 0x8CA4, 0xD3E2, 0x8CA3, 0xD3E3, 0x8D76, 0xD3E4, 0x8D78, 0xD3E5, 0x8DB5,
+ 0xD3E6, 0x8DB7, 0xD3E7, 0x8DB6, 0xD3E8, 0x8ED1, 0xD3E9, 0x8ED3, 0xD3EA, 0x8FFE, 0xD3EB, 0x8FF5, 0xD3EC, 0x9002, 0xD3ED, 0x8FFF,
+ 0xD3EE, 0x8FFB, 0xD3EF, 0x9004, 0xD3F0, 0x8FFC, 0xD3F1, 0x8FF6, 0xD3F2, 0x90D6, 0xD3F3, 0x90E0, 0xD3F4, 0x90D9, 0xD3F5, 0x90DA,
+ 0xD3F6, 0x90E3, 0xD3F7, 0x90DF, 0xD3F8, 0x90E5, 0xD3F9, 0x90D8, 0xD3FA, 0x90DB, 0xD3FB, 0x90D7, 0xD3FC, 0x90DC, 0xD3FD, 0x90E4,
+ 0xD3FE, 0x9150, 0xD440, 0x914E, 0xD441, 0x914F, 0xD442, 0x91D5, 0xD443, 0x91E2, 0xD444, 0x91DA, 0xD445, 0x965C, 0xD446, 0x965F,
+ 0xD447, 0x96BC, 0xD448, 0x98E3, 0xD449, 0x9ADF, 0xD44A, 0x9B2F, 0xD44B, 0x4E7F, 0xD44C, 0x5070, 0xD44D, 0x506A, 0xD44E, 0x5061,
+ 0xD44F, 0x505E, 0xD450, 0x5060, 0xD451, 0x5053, 0xD452, 0x504B, 0xD453, 0x505D, 0xD454, 0x5072, 0xD455, 0x5048, 0xD456, 0x504D,
+ 0xD457, 0x5041, 0xD458, 0x505B, 0xD459, 0x504A, 0xD45A, 0x5062, 0xD45B, 0x5015, 0xD45C, 0x5045, 0xD45D, 0x505F, 0xD45E, 0x5069,
+ 0xD45F, 0x506B, 0xD460, 0x5063, 0xD461, 0x5064, 0xD462, 0x5046, 0xD463, 0x5040, 0xD464, 0x506E, 0xD465, 0x5073, 0xD466, 0x5057,
+ 0xD467, 0x5051, 0xD468, 0x51D0, 0xD469, 0x526B, 0xD46A, 0x526D, 0xD46B, 0x526C, 0xD46C, 0x526E, 0xD46D, 0x52D6, 0xD46E, 0x52D3,
+ 0xD46F, 0x532D, 0xD470, 0x539C, 0xD471, 0x5575, 0xD472, 0x5576, 0xD473, 0x553C, 0xD474, 0x554D, 0xD475, 0x5550, 0xD476, 0x5534,
+ 0xD477, 0x552A, 0xD478, 0x5551, 0xD479, 0x5562, 0xD47A, 0x5536, 0xD47B, 0x5535, 0xD47C, 0x5530, 0xD47D, 0x5552, 0xD47E, 0x5545,
+ 0xD4A1, 0x550C, 0xD4A2, 0x5532, 0xD4A3, 0x5565, 0xD4A4, 0x554E, 0xD4A5, 0x5539, 0xD4A6, 0x5548, 0xD4A7, 0x552D, 0xD4A8, 0x553B,
+ 0xD4A9, 0x5540, 0xD4AA, 0x554B, 0xD4AB, 0x570A, 0xD4AC, 0x5707, 0xD4AD, 0x57FB, 0xD4AE, 0x5814, 0xD4AF, 0x57E2, 0xD4B0, 0x57F6,
+ 0xD4B1, 0x57DC, 0xD4B2, 0x57F4, 0xD4B3, 0x5800, 0xD4B4, 0x57ED, 0xD4B5, 0x57FD, 0xD4B6, 0x5808, 0xD4B7, 0x57F8, 0xD4B8, 0x580B,
+ 0xD4B9, 0x57F3, 0xD4BA, 0x57CF, 0xD4BB, 0x5807, 0xD4BC, 0x57EE, 0xD4BD, 0x57E3, 0xD4BE, 0x57F2, 0xD4BF, 0x57E5, 0xD4C0, 0x57EC,
+ 0xD4C1, 0x57E1, 0xD4C2, 0x580E, 0xD4C3, 0x57FC, 0xD4C4, 0x5810, 0xD4C5, 0x57E7, 0xD4C6, 0x5801, 0xD4C7, 0x580C, 0xD4C8, 0x57F1,
+ 0xD4C9, 0x57E9, 0xD4CA, 0x57F0, 0xD4CB, 0x580D, 0xD4CC, 0x5804, 0xD4CD, 0x595C, 0xD4CE, 0x5A60, 0xD4CF, 0x5A58, 0xD4D0, 0x5A55,
+ 0xD4D1, 0x5A67, 0xD4D2, 0x5A5E, 0xD4D3, 0x5A38, 0xD4D4, 0x5A35, 0xD4D5, 0x5A6D, 0xD4D6, 0x5A50, 0xD4D7, 0x5A5F, 0xD4D8, 0x5A65,
+ 0xD4D9, 0x5A6C, 0xD4DA, 0x5A53, 0xD4DB, 0x5A64, 0xD4DC, 0x5A57, 0xD4DD, 0x5A43, 0xD4DE, 0x5A5D, 0xD4DF, 0x5A52, 0xD4E0, 0x5A44,
+ 0xD4E1, 0x5A5B, 0xD4E2, 0x5A48, 0xD4E3, 0x5A8E, 0xD4E4, 0x5A3E, 0xD4E5, 0x5A4D, 0xD4E6, 0x5A39, 0xD4E7, 0x5A4C, 0xD4E8, 0x5A70,
+ 0xD4E9, 0x5A69, 0xD4EA, 0x5A47, 0xD4EB, 0x5A51, 0xD4EC, 0x5A56, 0xD4ED, 0x5A42, 0xD4EE, 0x5A5C, 0xD4EF, 0x5B72, 0xD4F0, 0x5B6E,
+ 0xD4F1, 0x5BC1, 0xD4F2, 0x5BC0, 0xD4F3, 0x5C59, 0xD4F4, 0x5D1E, 0xD4F5, 0x5D0B, 0xD4F6, 0x5D1D, 0xD4F7, 0x5D1A, 0xD4F8, 0x5D20,
+ 0xD4F9, 0x5D0C, 0xD4FA, 0x5D28, 0xD4FB, 0x5D0D, 0xD4FC, 0x5D26, 0xD4FD, 0x5D25, 0xD4FE, 0x5D0F, 0xD540, 0x5D30, 0xD541, 0x5D12,
+ 0xD542, 0x5D23, 0xD543, 0x5D1F, 0xD544, 0x5D2E, 0xD545, 0x5E3E, 0xD546, 0x5E34, 0xD547, 0x5EB1, 0xD548, 0x5EB4, 0xD549, 0x5EB9,
+ 0xD54A, 0x5EB2, 0xD54B, 0x5EB3, 0xD54C, 0x5F36, 0xD54D, 0x5F38, 0xD54E, 0x5F9B, 0xD54F, 0x5F96, 0xD550, 0x5F9F, 0xD551, 0x608A,
+ 0xD552, 0x6090, 0xD553, 0x6086, 0xD554, 0x60BE, 0xD555, 0x60B0, 0xD556, 0x60BA, 0xD557, 0x60D3, 0xD558, 0x60D4, 0xD559, 0x60CF,
+ 0xD55A, 0x60E4, 0xD55B, 0x60D9, 0xD55C, 0x60DD, 0xD55D, 0x60C8, 0xD55E, 0x60B1, 0xD55F, 0x60DB, 0xD560, 0x60B7, 0xD561, 0x60CA,
+ 0xD562, 0x60BF, 0xD563, 0x60C3, 0xD564, 0x60CD, 0xD565, 0x60C0, 0xD566, 0x6332, 0xD567, 0x6365, 0xD568, 0x638A, 0xD569, 0x6382,
+ 0xD56A, 0x637D, 0xD56B, 0x63BD, 0xD56C, 0x639E, 0xD56D, 0x63AD, 0xD56E, 0x639D, 0xD56F, 0x6397, 0xD570, 0x63AB, 0xD571, 0x638E,
+ 0xD572, 0x636F, 0xD573, 0x6387, 0xD574, 0x6390, 0xD575, 0x636E, 0xD576, 0x63AF, 0xD577, 0x6375, 0xD578, 0x639C, 0xD579, 0x636D,
+ 0xD57A, 0x63AE, 0xD57B, 0x637C, 0xD57C, 0x63A4, 0xD57D, 0x633B, 0xD57E, 0x639F, 0xD5A1, 0x6378, 0xD5A2, 0x6385, 0xD5A3, 0x6381,
+ 0xD5A4, 0x6391, 0xD5A5, 0x638D, 0xD5A6, 0x6370, 0xD5A7, 0x6553, 0xD5A8, 0x65CD, 0xD5A9, 0x6665, 0xD5AA, 0x6661, 0xD5AB, 0x665B,
+ 0xD5AC, 0x6659, 0xD5AD, 0x665C, 0xD5AE, 0x6662, 0xD5AF, 0x6718, 0xD5B0, 0x6879, 0xD5B1, 0x6887, 0xD5B2, 0x6890, 0xD5B3, 0x689C,
+ 0xD5B4, 0x686D, 0xD5B5, 0x686E, 0xD5B6, 0x68AE, 0xD5B7, 0x68AB, 0xD5B8, 0x6956, 0xD5B9, 0x686F, 0xD5BA, 0x68A3, 0xD5BB, 0x68AC,
+ 0xD5BC, 0x68A9, 0xD5BD, 0x6875, 0xD5BE, 0x6874, 0xD5BF, 0x68B2, 0xD5C0, 0x688F, 0xD5C1, 0x6877, 0xD5C2, 0x6892, 0xD5C3, 0x687C,
+ 0xD5C4, 0x686B, 0xD5C5, 0x6872, 0xD5C6, 0x68AA, 0xD5C7, 0x6880, 0xD5C8, 0x6871, 0xD5C9, 0x687E, 0xD5CA, 0x689B, 0xD5CB, 0x6896,
+ 0xD5CC, 0x688B, 0xD5CD, 0x68A0, 0xD5CE, 0x6889, 0xD5CF, 0x68A4, 0xD5D0, 0x6878, 0xD5D1, 0x687B, 0xD5D2, 0x6891, 0xD5D3, 0x688C,
+ 0xD5D4, 0x688A, 0xD5D5, 0x687D, 0xD5D6, 0x6B36, 0xD5D7, 0x6B33, 0xD5D8, 0x6B37, 0xD5D9, 0x6B38, 0xD5DA, 0x6B91, 0xD5DB, 0x6B8F,
+ 0xD5DC, 0x6B8D, 0xD5DD, 0x6B8E, 0xD5DE, 0x6B8C, 0xD5DF, 0x6C2A, 0xD5E0, 0x6DC0, 0xD5E1, 0x6DAB, 0xD5E2, 0x6DB4, 0xD5E3, 0x6DB3,
+ 0xD5E4, 0x6E74, 0xD5E5, 0x6DAC, 0xD5E6, 0x6DE9, 0xD5E7, 0x6DE2, 0xD5E8, 0x6DB7, 0xD5E9, 0x6DF6, 0xD5EA, 0x6DD4, 0xD5EB, 0x6E00,
+ 0xD5EC, 0x6DC8, 0xD5ED, 0x6DE0, 0xD5EE, 0x6DDF, 0xD5EF, 0x6DD6, 0xD5F0, 0x6DBE, 0xD5F1, 0x6DE5, 0xD5F2, 0x6DDC, 0xD5F3, 0x6DDD,
+ 0xD5F4, 0x6DDB, 0xD5F5, 0x6DF4, 0xD5F6, 0x6DCA, 0xD5F7, 0x6DBD, 0xD5F8, 0x6DED, 0xD5F9, 0x6DF0, 0xD5FA, 0x6DBA, 0xD5FB, 0x6DD5,
+ 0xD5FC, 0x6DC2, 0xD5FD, 0x6DCF, 0xD5FE, 0x6DC9, 0xD640, 0x6DD0, 0xD641, 0x6DF2, 0xD642, 0x6DD3, 0xD643, 0x6DFD, 0xD644, 0x6DD7,
+ 0xD645, 0x6DCD, 0xD646, 0x6DE3, 0xD647, 0x6DBB, 0xD648, 0x70FA, 0xD649, 0x710D, 0xD64A, 0x70F7, 0xD64B, 0x7117, 0xD64C, 0x70F4,
+ 0xD64D, 0x710C, 0xD64E, 0x70F0, 0xD64F, 0x7104, 0xD650, 0x70F3, 0xD651, 0x7110, 0xD652, 0x70FC, 0xD653, 0x70FF, 0xD654, 0x7106,
+ 0xD655, 0x7113, 0xD656, 0x7100, 0xD657, 0x70F8, 0xD658, 0x70F6, 0xD659, 0x710B, 0xD65A, 0x7102, 0xD65B, 0x710E, 0xD65C, 0x727E,
+ 0xD65D, 0x727B, 0xD65E, 0x727C, 0xD65F, 0x727F, 0xD660, 0x731D, 0xD661, 0x7317, 0xD662, 0x7307, 0xD663, 0x7311, 0xD664, 0x7318,
+ 0xD665, 0x730A, 0xD666, 0x7308, 0xD667, 0x72FF, 0xD668, 0x730F, 0xD669, 0x731E, 0xD66A, 0x7388, 0xD66B, 0x73F6, 0xD66C, 0x73F8,
+ 0xD66D, 0x73F5, 0xD66E, 0x7404, 0xD66F, 0x7401, 0xD670, 0x73FD, 0xD671, 0x7407, 0xD672, 0x7400, 0xD673, 0x73FA, 0xD674, 0x73FC,
+ 0xD675, 0x73FF, 0xD676, 0x740C, 0xD677, 0x740B, 0xD678, 0x73F4, 0xD679, 0x7408, 0xD67A, 0x7564, 0xD67B, 0x7563, 0xD67C, 0x75CE,
+ 0xD67D, 0x75D2, 0xD67E, 0x75CF, 0xD6A1, 0x75CB, 0xD6A2, 0x75CC, 0xD6A3, 0x75D1, 0xD6A4, 0x75D0, 0xD6A5, 0x768F, 0xD6A6, 0x7689,
+ 0xD6A7, 0x76D3, 0xD6A8, 0x7739, 0xD6A9, 0x772F, 0xD6AA, 0x772D, 0xD6AB, 0x7731, 0xD6AC, 0x7732, 0xD6AD, 0x7734, 0xD6AE, 0x7733,
+ 0xD6AF, 0x773D, 0xD6B0, 0x7725, 0xD6B1, 0x773B, 0xD6B2, 0x7735, 0xD6B3, 0x7848, 0xD6B4, 0x7852, 0xD6B5, 0x7849, 0xD6B6, 0x784D,
+ 0xD6B7, 0x784A, 0xD6B8, 0x784C, 0xD6B9, 0x7826, 0xD6BA, 0x7845, 0xD6BB, 0x7850, 0xD6BC, 0x7964, 0xD6BD, 0x7967, 0xD6BE, 0x7969,
+ 0xD6BF, 0x796A, 0xD6C0, 0x7963, 0xD6C1, 0x796B, 0xD6C2, 0x7961, 0xD6C3, 0x79BB, 0xD6C4, 0x79FA, 0xD6C5, 0x79F8, 0xD6C6, 0x79F6,
+ 0xD6C7, 0x79F7, 0xD6C8, 0x7A8F, 0xD6C9, 0x7A94, 0xD6CA, 0x7A90, 0xD6CB, 0x7B35, 0xD6CC, 0x7B47, 0xD6CD, 0x7B34, 0xD6CE, 0x7B25,
+ 0xD6CF, 0x7B30, 0xD6D0, 0x7B22, 0xD6D1, 0x7B24, 0xD6D2, 0x7B33, 0xD6D3, 0x7B18, 0xD6D4, 0x7B2A, 0xD6D5, 0x7B1D, 0xD6D6, 0x7B31,
+ 0xD6D7, 0x7B2B, 0xD6D8, 0x7B2D, 0xD6D9, 0x7B2F, 0xD6DA, 0x7B32, 0xD6DB, 0x7B38, 0xD6DC, 0x7B1A, 0xD6DD, 0x7B23, 0xD6DE, 0x7C94,
+ 0xD6DF, 0x7C98, 0xD6E0, 0x7C96, 0xD6E1, 0x7CA3, 0xD6E2, 0x7D35, 0xD6E3, 0x7D3D, 0xD6E4, 0x7D38, 0xD6E5, 0x7D36, 0xD6E6, 0x7D3A,
+ 0xD6E7, 0x7D45, 0xD6E8, 0x7D2C, 0xD6E9, 0x7D29, 0xD6EA, 0x7D41, 0xD6EB, 0x7D47, 0xD6EC, 0x7D3E, 0xD6ED, 0x7D3F, 0xD6EE, 0x7D4A,
+ 0xD6EF, 0x7D3B, 0xD6F0, 0x7D28, 0xD6F1, 0x7F63, 0xD6F2, 0x7F95, 0xD6F3, 0x7F9C, 0xD6F4, 0x7F9D, 0xD6F5, 0x7F9B, 0xD6F6, 0x7FCA,
+ 0xD6F7, 0x7FCB, 0xD6F8, 0x7FCD, 0xD6F9, 0x7FD0, 0xD6FA, 0x7FD1, 0xD6FB, 0x7FC7, 0xD6FC, 0x7FCF, 0xD6FD, 0x7FC9, 0xD6FE, 0x801F,
+ 0xD740, 0x801E, 0xD741, 0x801B, 0xD742, 0x8047, 0xD743, 0x8043, 0xD744, 0x8048, 0xD745, 0x8118, 0xD746, 0x8125, 0xD747, 0x8119,
+ 0xD748, 0x811B, 0xD749, 0x812D, 0xD74A, 0x811F, 0xD74B, 0x812C, 0xD74C, 0x811E, 0xD74D, 0x8121, 0xD74E, 0x8115, 0xD74F, 0x8127,
+ 0xD750, 0x811D, 0xD751, 0x8122, 0xD752, 0x8211, 0xD753, 0x8238, 0xD754, 0x8233, 0xD755, 0x823A, 0xD756, 0x8234, 0xD757, 0x8232,
+ 0xD758, 0x8274, 0xD759, 0x8390, 0xD75A, 0x83A3, 0xD75B, 0x83A8, 0xD75C, 0x838D, 0xD75D, 0x837A, 0xD75E, 0x8373, 0xD75F, 0x83A4,
+ 0xD760, 0x8374, 0xD761, 0x838F, 0xD762, 0x8381, 0xD763, 0x8395, 0xD764, 0x8399, 0xD765, 0x8375, 0xD766, 0x8394, 0xD767, 0x83A9,
+ 0xD768, 0x837D, 0xD769, 0x8383, 0xD76A, 0x838C, 0xD76B, 0x839D, 0xD76C, 0x839B, 0xD76D, 0x83AA, 0xD76E, 0x838B, 0xD76F, 0x837E,
+ 0xD770, 0x83A5, 0xD771, 0x83AF, 0xD772, 0x8388, 0xD773, 0x8397, 0xD774, 0x83B0, 0xD775, 0x837F, 0xD776, 0x83A6, 0xD777, 0x8387,
+ 0xD778, 0x83AE, 0xD779, 0x8376, 0xD77A, 0x839A, 0xD77B, 0x8659, 0xD77C, 0x8656, 0xD77D, 0x86BF, 0xD77E, 0x86B7, 0xD7A1, 0x86C2,
+ 0xD7A2, 0x86C1, 0xD7A3, 0x86C5, 0xD7A4, 0x86BA, 0xD7A5, 0x86B0, 0xD7A6, 0x86C8, 0xD7A7, 0x86B9, 0xD7A8, 0x86B3, 0xD7A9, 0x86B8,
+ 0xD7AA, 0x86CC, 0xD7AB, 0x86B4, 0xD7AC, 0x86BB, 0xD7AD, 0x86BC, 0xD7AE, 0x86C3, 0xD7AF, 0x86BD, 0xD7B0, 0x86BE, 0xD7B1, 0x8852,
+ 0xD7B2, 0x8889, 0xD7B3, 0x8895, 0xD7B4, 0x88A8, 0xD7B5, 0x88A2, 0xD7B6, 0x88AA, 0xD7B7, 0x889A, 0xD7B8, 0x8891, 0xD7B9, 0x88A1,
+ 0xD7BA, 0x889F, 0xD7BB, 0x8898, 0xD7BC, 0x88A7, 0xD7BD, 0x8899, 0xD7BE, 0x889B, 0xD7BF, 0x8897, 0xD7C0, 0x88A4, 0xD7C1, 0x88AC,
+ 0xD7C2, 0x888C, 0xD7C3, 0x8893, 0xD7C4, 0x888E, 0xD7C5, 0x8982, 0xD7C6, 0x89D6, 0xD7C7, 0x89D9, 0xD7C8, 0x89D5, 0xD7C9, 0x8A30,
+ 0xD7CA, 0x8A27, 0xD7CB, 0x8A2C, 0xD7CC, 0x8A1E, 0xD7CD, 0x8C39, 0xD7CE, 0x8C3B, 0xD7CF, 0x8C5C, 0xD7D0, 0x8C5D, 0xD7D1, 0x8C7D,
+ 0xD7D2, 0x8CA5, 0xD7D3, 0x8D7D, 0xD7D4, 0x8D7B, 0xD7D5, 0x8D79, 0xD7D6, 0x8DBC, 0xD7D7, 0x8DC2, 0xD7D8, 0x8DB9, 0xD7D9, 0x8DBF,
+ 0xD7DA, 0x8DC1, 0xD7DB, 0x8ED8, 0xD7DC, 0x8EDE, 0xD7DD, 0x8EDD, 0xD7DE, 0x8EDC, 0xD7DF, 0x8ED7, 0xD7E0, 0x8EE0, 0xD7E1, 0x8EE1,
+ 0xD7E2, 0x9024, 0xD7E3, 0x900B, 0xD7E4, 0x9011, 0xD7E5, 0x901C, 0xD7E6, 0x900C, 0xD7E7, 0x9021, 0xD7E8, 0x90EF, 0xD7E9, 0x90EA,
+ 0xD7EA, 0x90F0, 0xD7EB, 0x90F4, 0xD7EC, 0x90F2, 0xD7ED, 0x90F3, 0xD7EE, 0x90D4, 0xD7EF, 0x90EB, 0xD7F0, 0x90EC, 0xD7F1, 0x90E9,
+ 0xD7F2, 0x9156, 0xD7F3, 0x9158, 0xD7F4, 0x915A, 0xD7F5, 0x9153, 0xD7F6, 0x9155, 0xD7F7, 0x91EC, 0xD7F8, 0x91F4, 0xD7F9, 0x91F1,
+ 0xD7FA, 0x91F3, 0xD7FB, 0x91F8, 0xD7FC, 0x91E4, 0xD7FD, 0x91F9, 0xD7FE, 0x91EA, 0xD840, 0x91EB, 0xD841, 0x91F7, 0xD842, 0x91E8,
+ 0xD843, 0x91EE, 0xD844, 0x957A, 0xD845, 0x9586, 0xD846, 0x9588, 0xD847, 0x967C, 0xD848, 0x966D, 0xD849, 0x966B, 0xD84A, 0x9671,
+ 0xD84B, 0x966F, 0xD84C, 0x96BF, 0xD84D, 0x976A, 0xD84E, 0x9804, 0xD84F, 0x98E5, 0xD850, 0x9997, 0xD851, 0x509B, 0xD852, 0x5095,
+ 0xD853, 0x5094, 0xD854, 0x509E, 0xD855, 0x508B, 0xD856, 0x50A3, 0xD857, 0x5083, 0xD858, 0x508C, 0xD859, 0x508E, 0xD85A, 0x509D,
+ 0xD85B, 0x5068, 0xD85C, 0x509C, 0xD85D, 0x5092, 0xD85E, 0x5082, 0xD85F, 0x5087, 0xD860, 0x515F, 0xD861, 0x51D4, 0xD862, 0x5312,
+ 0xD863, 0x5311, 0xD864, 0x53A4, 0xD865, 0x53A7, 0xD866, 0x5591, 0xD867, 0x55A8, 0xD868, 0x55A5, 0xD869, 0x55AD, 0xD86A, 0x5577,
+ 0xD86B, 0x5645, 0xD86C, 0x55A2, 0xD86D, 0x5593, 0xD86E, 0x5588, 0xD86F, 0x558F, 0xD870, 0x55B5, 0xD871, 0x5581, 0xD872, 0x55A3,
+ 0xD873, 0x5592, 0xD874, 0x55A4, 0xD875, 0x557D, 0xD876, 0x558C, 0xD877, 0x55A6, 0xD878, 0x557F, 0xD879, 0x5595, 0xD87A, 0x55A1,
+ 0xD87B, 0x558E, 0xD87C, 0x570C, 0xD87D, 0x5829, 0xD87E, 0x5837, 0xD8A1, 0x5819, 0xD8A2, 0x581E, 0xD8A3, 0x5827, 0xD8A4, 0x5823,
+ 0xD8A5, 0x5828, 0xD8A6, 0x57F5, 0xD8A7, 0x5848, 0xD8A8, 0x5825, 0xD8A9, 0x581C, 0xD8AA, 0x581B, 0xD8AB, 0x5833, 0xD8AC, 0x583F,
+ 0xD8AD, 0x5836, 0xD8AE, 0x582E, 0xD8AF, 0x5839, 0xD8B0, 0x5838, 0xD8B1, 0x582D, 0xD8B2, 0x582C, 0xD8B3, 0x583B, 0xD8B4, 0x5961,
+ 0xD8B5, 0x5AAF, 0xD8B6, 0x5A94, 0xD8B7, 0x5A9F, 0xD8B8, 0x5A7A, 0xD8B9, 0x5AA2, 0xD8BA, 0x5A9E, 0xD8BB, 0x5A78, 0xD8BC, 0x5AA6,
+ 0xD8BD, 0x5A7C, 0xD8BE, 0x5AA5, 0xD8BF, 0x5AAC, 0xD8C0, 0x5A95, 0xD8C1, 0x5AAE, 0xD8C2, 0x5A37, 0xD8C3, 0x5A84, 0xD8C4, 0x5A8A,
+ 0xD8C5, 0x5A97, 0xD8C6, 0x5A83, 0xD8C7, 0x5A8B, 0xD8C8, 0x5AA9, 0xD8C9, 0x5A7B, 0xD8CA, 0x5A7D, 0xD8CB, 0x5A8C, 0xD8CC, 0x5A9C,
+ 0xD8CD, 0x5A8F, 0xD8CE, 0x5A93, 0xD8CF, 0x5A9D, 0xD8D0, 0x5BEA, 0xD8D1, 0x5BCD, 0xD8D2, 0x5BCB, 0xD8D3, 0x5BD4, 0xD8D4, 0x5BD1,
+ 0xD8D5, 0x5BCA, 0xD8D6, 0x5BCE, 0xD8D7, 0x5C0C, 0xD8D8, 0x5C30, 0xD8D9, 0x5D37, 0xD8DA, 0x5D43, 0xD8DB, 0x5D6B, 0xD8DC, 0x5D41,
+ 0xD8DD, 0x5D4B, 0xD8DE, 0x5D3F, 0xD8DF, 0x5D35, 0xD8E0, 0x5D51, 0xD8E1, 0x5D4E, 0xD8E2, 0x5D55, 0xD8E3, 0x5D33, 0xD8E4, 0x5D3A,
+ 0xD8E5, 0x5D52, 0xD8E6, 0x5D3D, 0xD8E7, 0x5D31, 0xD8E8, 0x5D59, 0xD8E9, 0x5D42, 0xD8EA, 0x5D39, 0xD8EB, 0x5D49, 0xD8EC, 0x5D38,
+ 0xD8ED, 0x5D3C, 0xD8EE, 0x5D32, 0xD8EF, 0x5D36, 0xD8F0, 0x5D40, 0xD8F1, 0x5D45, 0xD8F2, 0x5E44, 0xD8F3, 0x5E41, 0xD8F4, 0x5F58,
+ 0xD8F5, 0x5FA6, 0xD8F6, 0x5FA5, 0xD8F7, 0x5FAB, 0xD8F8, 0x60C9, 0xD8F9, 0x60B9, 0xD8FA, 0x60CC, 0xD8FB, 0x60E2, 0xD8FC, 0x60CE,
+ 0xD8FD, 0x60C4, 0xD8FE, 0x6114, 0xD940, 0x60F2, 0xD941, 0x610A, 0xD942, 0x6116, 0xD943, 0x6105, 0xD944, 0x60F5, 0xD945, 0x6113,
+ 0xD946, 0x60F8, 0xD947, 0x60FC, 0xD948, 0x60FE, 0xD949, 0x60C1, 0xD94A, 0x6103, 0xD94B, 0x6118, 0xD94C, 0x611D, 0xD94D, 0x6110,
+ 0xD94E, 0x60FF, 0xD94F, 0x6104, 0xD950, 0x610B, 0xD951, 0x624A, 0xD952, 0x6394, 0xD953, 0x63B1, 0xD954, 0x63B0, 0xD955, 0x63CE,
+ 0xD956, 0x63E5, 0xD957, 0x63E8, 0xD958, 0x63EF, 0xD959, 0x63C3, 0xD95A, 0x649D, 0xD95B, 0x63F3, 0xD95C, 0x63CA, 0xD95D, 0x63E0,
+ 0xD95E, 0x63F6, 0xD95F, 0x63D5, 0xD960, 0x63F2, 0xD961, 0x63F5, 0xD962, 0x6461, 0xD963, 0x63DF, 0xD964, 0x63BE, 0xD965, 0x63DD,
+ 0xD966, 0x63DC, 0xD967, 0x63C4, 0xD968, 0x63D8, 0xD969, 0x63D3, 0xD96A, 0x63C2, 0xD96B, 0x63C7, 0xD96C, 0x63CC, 0xD96D, 0x63CB,
+ 0xD96E, 0x63C8, 0xD96F, 0x63F0, 0xD970, 0x63D7, 0xD971, 0x63D9, 0xD972, 0x6532, 0xD973, 0x6567, 0xD974, 0x656A, 0xD975, 0x6564,
+ 0xD976, 0x655C, 0xD977, 0x6568, 0xD978, 0x6565, 0xD979, 0x658C, 0xD97A, 0x659D, 0xD97B, 0x659E, 0xD97C, 0x65AE, 0xD97D, 0x65D0,
+ 0xD97E, 0x65D2, 0xD9A1, 0x667C, 0xD9A2, 0x666C, 0xD9A3, 0x667B, 0xD9A4, 0x6680, 0xD9A5, 0x6671, 0xD9A6, 0x6679, 0xD9A7, 0x666A,
+ 0xD9A8, 0x6672, 0xD9A9, 0x6701, 0xD9AA, 0x690C, 0xD9AB, 0x68D3, 0xD9AC, 0x6904, 0xD9AD, 0x68DC, 0xD9AE, 0x692A, 0xD9AF, 0x68EC,
+ 0xD9B0, 0x68EA, 0xD9B1, 0x68F1, 0xD9B2, 0x690F, 0xD9B3, 0x68D6, 0xD9B4, 0x68F7, 0xD9B5, 0x68EB, 0xD9B6, 0x68E4, 0xD9B7, 0x68F6,
+ 0xD9B8, 0x6913, 0xD9B9, 0x6910, 0xD9BA, 0x68F3, 0xD9BB, 0x68E1, 0xD9BC, 0x6907, 0xD9BD, 0x68CC, 0xD9BE, 0x6908, 0xD9BF, 0x6970,
+ 0xD9C0, 0x68B4, 0xD9C1, 0x6911, 0xD9C2, 0x68EF, 0xD9C3, 0x68C6, 0xD9C4, 0x6914, 0xD9C5, 0x68F8, 0xD9C6, 0x68D0, 0xD9C7, 0x68FD,
+ 0xD9C8, 0x68FC, 0xD9C9, 0x68E8, 0xD9CA, 0x690B, 0xD9CB, 0x690A, 0xD9CC, 0x6917, 0xD9CD, 0x68CE, 0xD9CE, 0x68C8, 0xD9CF, 0x68DD,
+ 0xD9D0, 0x68DE, 0xD9D1, 0x68E6, 0xD9D2, 0x68F4, 0xD9D3, 0x68D1, 0xD9D4, 0x6906, 0xD9D5, 0x68D4, 0xD9D6, 0x68E9, 0xD9D7, 0x6915,
+ 0xD9D8, 0x6925, 0xD9D9, 0x68C7, 0xD9DA, 0x6B39, 0xD9DB, 0x6B3B, 0xD9DC, 0x6B3F, 0xD9DD, 0x6B3C, 0xD9DE, 0x6B94, 0xD9DF, 0x6B97,
+ 0xD9E0, 0x6B99, 0xD9E1, 0x6B95, 0xD9E2, 0x6BBD, 0xD9E3, 0x6BF0, 0xD9E4, 0x6BF2, 0xD9E5, 0x6BF3, 0xD9E6, 0x6C30, 0xD9E7, 0x6DFC,
+ 0xD9E8, 0x6E46, 0xD9E9, 0x6E47, 0xD9EA, 0x6E1F, 0xD9EB, 0x6E49, 0xD9EC, 0x6E88, 0xD9ED, 0x6E3C, 0xD9EE, 0x6E3D, 0xD9EF, 0x6E45,
+ 0xD9F0, 0x6E62, 0xD9F1, 0x6E2B, 0xD9F2, 0x6E3F, 0xD9F3, 0x6E41, 0xD9F4, 0x6E5D, 0xD9F5, 0x6E73, 0xD9F6, 0x6E1C, 0xD9F7, 0x6E33,
+ 0xD9F8, 0x6E4B, 0xD9F9, 0x6E40, 0xD9FA, 0x6E51, 0xD9FB, 0x6E3B, 0xD9FC, 0x6E03, 0xD9FD, 0x6E2E, 0xD9FE, 0x6E5E, 0xDA40, 0x6E68,
+ 0xDA41, 0x6E5C, 0xDA42, 0x6E61, 0xDA43, 0x6E31, 0xDA44, 0x6E28, 0xDA45, 0x6E60, 0xDA46, 0x6E71, 0xDA47, 0x6E6B, 0xDA48, 0x6E39,
+ 0xDA49, 0x6E22, 0xDA4A, 0x6E30, 0xDA4B, 0x6E53, 0xDA4C, 0x6E65, 0xDA4D, 0x6E27, 0xDA4E, 0x6E78, 0xDA4F, 0x6E64, 0xDA50, 0x6E77,
+ 0xDA51, 0x6E55, 0xDA52, 0x6E79, 0xDA53, 0x6E52, 0xDA54, 0x6E66, 0xDA55, 0x6E35, 0xDA56, 0x6E36, 0xDA57, 0x6E5A, 0xDA58, 0x7120,
+ 0xDA59, 0x711E, 0xDA5A, 0x712F, 0xDA5B, 0x70FB, 0xDA5C, 0x712E, 0xDA5D, 0x7131, 0xDA5E, 0x7123, 0xDA5F, 0x7125, 0xDA60, 0x7122,
+ 0xDA61, 0x7132, 0xDA62, 0x711F, 0xDA63, 0x7128, 0xDA64, 0x713A, 0xDA65, 0x711B, 0xDA66, 0x724B, 0xDA67, 0x725A, 0xDA68, 0x7288,
+ 0xDA69, 0x7289, 0xDA6A, 0x7286, 0xDA6B, 0x7285, 0xDA6C, 0x728B, 0xDA6D, 0x7312, 0xDA6E, 0x730B, 0xDA6F, 0x7330, 0xDA70, 0x7322,
+ 0xDA71, 0x7331, 0xDA72, 0x7333, 0xDA73, 0x7327, 0xDA74, 0x7332, 0xDA75, 0x732D, 0xDA76, 0x7326, 0xDA77, 0x7323, 0xDA78, 0x7335,
+ 0xDA79, 0x730C, 0xDA7A, 0x742E, 0xDA7B, 0x742C, 0xDA7C, 0x7430, 0xDA7D, 0x742B, 0xDA7E, 0x7416, 0xDAA1, 0x741A, 0xDAA2, 0x7421,
+ 0xDAA3, 0x742D, 0xDAA4, 0x7431, 0xDAA5, 0x7424, 0xDAA6, 0x7423, 0xDAA7, 0x741D, 0xDAA8, 0x7429, 0xDAA9, 0x7420, 0xDAAA, 0x7432,
+ 0xDAAB, 0x74FB, 0xDAAC, 0x752F, 0xDAAD, 0x756F, 0xDAAE, 0x756C, 0xDAAF, 0x75E7, 0xDAB0, 0x75DA, 0xDAB1, 0x75E1, 0xDAB2, 0x75E6,
+ 0xDAB3, 0x75DD, 0xDAB4, 0x75DF, 0xDAB5, 0x75E4, 0xDAB6, 0x75D7, 0xDAB7, 0x7695, 0xDAB8, 0x7692, 0xDAB9, 0x76DA, 0xDABA, 0x7746,
+ 0xDABB, 0x7747, 0xDABC, 0x7744, 0xDABD, 0x774D, 0xDABE, 0x7745, 0xDABF, 0x774A, 0xDAC0, 0x774E, 0xDAC1, 0x774B, 0xDAC2, 0x774C,
+ 0xDAC3, 0x77DE, 0xDAC4, 0x77EC, 0xDAC5, 0x7860, 0xDAC6, 0x7864, 0xDAC7, 0x7865, 0xDAC8, 0x785C, 0xDAC9, 0x786D, 0xDACA, 0x7871,
+ 0xDACB, 0x786A, 0xDACC, 0x786E, 0xDACD, 0x7870, 0xDACE, 0x7869, 0xDACF, 0x7868, 0xDAD0, 0x785E, 0xDAD1, 0x7862, 0xDAD2, 0x7974,
+ 0xDAD3, 0x7973, 0xDAD4, 0x7972, 0xDAD5, 0x7970, 0xDAD6, 0x7A02, 0xDAD7, 0x7A0A, 0xDAD8, 0x7A03, 0xDAD9, 0x7A0C, 0xDADA, 0x7A04,
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+ 0xE0A5, 0x910D, 0xE0A6, 0x910F, 0xE0A7, 0x9111, 0xE0A8, 0x9116, 0xE0A9, 0x9114, 0xE0AA, 0x910B, 0xE0AB, 0x910E, 0xE0AC, 0x916E,
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+ 0xE3A6, 0x8183, 0xE3A7, 0x8187, 0xE3A8, 0x818D, 0xE3A9, 0x818C, 0xE3AA, 0x818B, 0xE3AB, 0x8215, 0xE3AC, 0x8497, 0xE3AD, 0x84A4,
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+ 0xF176, 0x9723, 0xF177, 0x9722, 0xF178, 0x9725, 0xF179, 0x97AC, 0xF17A, 0x97AE, 0xF17B, 0x97A8, 0xF17C, 0x97AB, 0xF17D, 0x97A4,
+ 0xF17E, 0x97AA, 0xF1A1, 0x97A2, 0xF1A2, 0x97A5, 0xF1A3, 0x97D7, 0xF1A4, 0x97D9, 0xF1A5, 0x97D6, 0xF1A6, 0x97D8, 0xF1A7, 0x97FA,
+ 0xF1A8, 0x9850, 0xF1A9, 0x9851, 0xF1AA, 0x9852, 0xF1AB, 0x98B8, 0xF1AC, 0x9941, 0xF1AD, 0x993C, 0xF1AE, 0x993A, 0xF1AF, 0x9A0F,
+ 0xF1B0, 0x9A0B, 0xF1B1, 0x9A09, 0xF1B2, 0x9A0D, 0xF1B3, 0x9A04, 0xF1B4, 0x9A11, 0xF1B5, 0x9A0A, 0xF1B6, 0x9A05, 0xF1B7, 0x9A07,
+ 0xF1B8, 0x9A06, 0xF1B9, 0x9AC0, 0xF1BA, 0x9ADC, 0xF1BB, 0x9B08, 0xF1BC, 0x9B04, 0xF1BD, 0x9B05, 0xF1BE, 0x9B29, 0xF1BF, 0x9B35,
+ 0xF1C0, 0x9B4A, 0xF1C1, 0x9B4C, 0xF1C2, 0x9B4B, 0xF1C3, 0x9BC7, 0xF1C4, 0x9BC6, 0xF1C5, 0x9BC3, 0xF1C6, 0x9BBF, 0xF1C7, 0x9BC1,
+ 0xF1C8, 0x9BB5, 0xF1C9, 0x9BB8, 0xF1CA, 0x9BD3, 0xF1CB, 0x9BB6, 0xF1CC, 0x9BC4, 0xF1CD, 0x9BB9, 0xF1CE, 0x9BBD, 0xF1CF, 0x9D5C,
+ 0xF1D0, 0x9D53, 0xF1D1, 0x9D4F, 0xF1D2, 0x9D4A, 0xF1D3, 0x9D5B, 0xF1D4, 0x9D4B, 0xF1D5, 0x9D59, 0xF1D6, 0x9D56, 0xF1D7, 0x9D4C,
+ 0xF1D8, 0x9D57, 0xF1D9, 0x9D52, 0xF1DA, 0x9D54, 0xF1DB, 0x9D5F, 0xF1DC, 0x9D58, 0xF1DD, 0x9D5A, 0xF1DE, 0x9E8E, 0xF1DF, 0x9E8C,
+ 0xF1E0, 0x9EDF, 0xF1E1, 0x9F01, 0xF1E2, 0x9F00, 0xF1E3, 0x9F16, 0xF1E4, 0x9F25, 0xF1E5, 0x9F2B, 0xF1E6, 0x9F2A, 0xF1E7, 0x9F29,
+ 0xF1E8, 0x9F28, 0xF1E9, 0x9F4C, 0xF1EA, 0x9F55, 0xF1EB, 0x5134, 0xF1EC, 0x5135, 0xF1ED, 0x5296, 0xF1EE, 0x52F7, 0xF1EF, 0x53B4,
+ 0xF1F0, 0x56AB, 0xF1F1, 0x56AD, 0xF1F2, 0x56A6, 0xF1F3, 0x56A7, 0xF1F4, 0x56AA, 0xF1F5, 0x56AC, 0xF1F6, 0x58DA, 0xF1F7, 0x58DD,
+ 0xF1F8, 0x58DB, 0xF1F9, 0x5912, 0xF1FA, 0x5B3D, 0xF1FB, 0x5B3E, 0xF1FC, 0x5B3F, 0xF1FD, 0x5DC3, 0xF1FE, 0x5E70, 0xF240, 0x5FBF,
+ 0xF241, 0x61FB, 0xF242, 0x6507, 0xF243, 0x6510, 0xF244, 0x650D, 0xF245, 0x6509, 0xF246, 0x650C, 0xF247, 0x650E, 0xF248, 0x6584,
+ 0xF249, 0x65DE, 0xF24A, 0x65DD, 0xF24B, 0x66DE, 0xF24C, 0x6AE7, 0xF24D, 0x6AE0, 0xF24E, 0x6ACC, 0xF24F, 0x6AD1, 0xF250, 0x6AD9,
+ 0xF251, 0x6ACB, 0xF252, 0x6ADF, 0xF253, 0x6ADC, 0xF254, 0x6AD0, 0xF255, 0x6AEB, 0xF256, 0x6ACF, 0xF257, 0x6ACD, 0xF258, 0x6ADE,
+ 0xF259, 0x6B60, 0xF25A, 0x6BB0, 0xF25B, 0x6C0C, 0xF25C, 0x7019, 0xF25D, 0x7027, 0xF25E, 0x7020, 0xF25F, 0x7016, 0xF260, 0x702B,
+ 0xF261, 0x7021, 0xF262, 0x7022, 0xF263, 0x7023, 0xF264, 0x7029, 0xF265, 0x7017, 0xF266, 0x7024, 0xF267, 0x701C, 0xF268, 0x702A,
+ 0xF269, 0x720C, 0xF26A, 0x720A, 0xF26B, 0x7207, 0xF26C, 0x7202, 0xF26D, 0x7205, 0xF26E, 0x72A5, 0xF26F, 0x72A6, 0xF270, 0x72A4,
+ 0xF271, 0x72A3, 0xF272, 0x72A1, 0xF273, 0x74CB, 0xF274, 0x74C5, 0xF275, 0x74B7, 0xF276, 0x74C3, 0xF277, 0x7516, 0xF278, 0x7660,
+ 0xF279, 0x77C9, 0xF27A, 0x77CA, 0xF27B, 0x77C4, 0xF27C, 0x77F1, 0xF27D, 0x791D, 0xF27E, 0x791B, 0xF2A1, 0x7921, 0xF2A2, 0x791C,
+ 0xF2A3, 0x7917, 0xF2A4, 0x791E, 0xF2A5, 0x79B0, 0xF2A6, 0x7A67, 0xF2A7, 0x7A68, 0xF2A8, 0x7C33, 0xF2A9, 0x7C3C, 0xF2AA, 0x7C39,
+ 0xF2AB, 0x7C2C, 0xF2AC, 0x7C3B, 0xF2AD, 0x7CEC, 0xF2AE, 0x7CEA, 0xF2AF, 0x7E76, 0xF2B0, 0x7E75, 0xF2B1, 0x7E78, 0xF2B2, 0x7E70,
+ 0xF2B3, 0x7E77, 0xF2B4, 0x7E6F, 0xF2B5, 0x7E7A, 0xF2B6, 0x7E72, 0xF2B7, 0x7E74, 0xF2B8, 0x7E68, 0xF2B9, 0x7F4B, 0xF2BA, 0x7F4A,
+ 0xF2BB, 0x7F83, 0xF2BC, 0x7F86, 0xF2BD, 0x7FB7, 0xF2BE, 0x7FFD, 0xF2BF, 0x7FFE, 0xF2C0, 0x8078, 0xF2C1, 0x81D7, 0xF2C2, 0x81D5,
+ 0xF2C3, 0x8264, 0xF2C4, 0x8261, 0xF2C5, 0x8263, 0xF2C6, 0x85EB, 0xF2C7, 0x85F1, 0xF2C8, 0x85ED, 0xF2C9, 0x85D9, 0xF2CA, 0x85E1,
+ 0xF2CB, 0x85E8, 0xF2CC, 0x85DA, 0xF2CD, 0x85D7, 0xF2CE, 0x85EC, 0xF2CF, 0x85F2, 0xF2D0, 0x85F8, 0xF2D1, 0x85D8, 0xF2D2, 0x85DF,
+ 0xF2D3, 0x85E3, 0xF2D4, 0x85DC, 0xF2D5, 0x85D1, 0xF2D6, 0x85F0, 0xF2D7, 0x85E6, 0xF2D8, 0x85EF, 0xF2D9, 0x85DE, 0xF2DA, 0x85E2,
+ 0xF2DB, 0x8800, 0xF2DC, 0x87FA, 0xF2DD, 0x8803, 0xF2DE, 0x87F6, 0xF2DF, 0x87F7, 0xF2E0, 0x8809, 0xF2E1, 0x880C, 0xF2E2, 0x880B,
+ 0xF2E3, 0x8806, 0xF2E4, 0x87FC, 0xF2E5, 0x8808, 0xF2E6, 0x87FF, 0xF2E7, 0x880A, 0xF2E8, 0x8802, 0xF2E9, 0x8962, 0xF2EA, 0x895A,
+ 0xF2EB, 0x895B, 0xF2EC, 0x8957, 0xF2ED, 0x8961, 0xF2EE, 0x895C, 0xF2EF, 0x8958, 0xF2F0, 0x895D, 0xF2F1, 0x8959, 0xF2F2, 0x8988,
+ 0xF2F3, 0x89B7, 0xF2F4, 0x89B6, 0xF2F5, 0x89F6, 0xF2F6, 0x8B50, 0xF2F7, 0x8B48, 0xF2F8, 0x8B4A, 0xF2F9, 0x8B40, 0xF2FA, 0x8B53,
+ 0xF2FB, 0x8B56, 0xF2FC, 0x8B54, 0xF2FD, 0x8B4B, 0xF2FE, 0x8B55, 0xF340, 0x8B51, 0xF341, 0x8B42, 0xF342, 0x8B52, 0xF343, 0x8B57,
+ 0xF344, 0x8C43, 0xF345, 0x8C77, 0xF346, 0x8C76, 0xF347, 0x8C9A, 0xF348, 0x8D06, 0xF349, 0x8D07, 0xF34A, 0x8D09, 0xF34B, 0x8DAC,
+ 0xF34C, 0x8DAA, 0xF34D, 0x8DAD, 0xF34E, 0x8DAB, 0xF34F, 0x8E6D, 0xF350, 0x8E78, 0xF351, 0x8E73, 0xF352, 0x8E6A, 0xF353, 0x8E6F,
+ 0xF354, 0x8E7B, 0xF355, 0x8EC2, 0xF356, 0x8F52, 0xF357, 0x8F51, 0xF358, 0x8F4F, 0xF359, 0x8F50, 0xF35A, 0x8F53, 0xF35B, 0x8FB4,
+ 0xF35C, 0x9140, 0xF35D, 0x913F, 0xF35E, 0x91B0, 0xF35F, 0x91AD, 0xF360, 0x93DE, 0xF361, 0x93C7, 0xF362, 0x93CF, 0xF363, 0x93C2,
+ 0xF364, 0x93DA, 0xF365, 0x93D0, 0xF366, 0x93F9, 0xF367, 0x93EC, 0xF368, 0x93CC, 0xF369, 0x93D9, 0xF36A, 0x93A9, 0xF36B, 0x93E6,
+ 0xF36C, 0x93CA, 0xF36D, 0x93D4, 0xF36E, 0x93EE, 0xF36F, 0x93E3, 0xF370, 0x93D5, 0xF371, 0x93C4, 0xF372, 0x93CE, 0xF373, 0x93C0,
+ 0xF374, 0x93D2, 0xF375, 0x93E7, 0xF376, 0x957D, 0xF377, 0x95DA, 0xF378, 0x95DB, 0xF379, 0x96E1, 0xF37A, 0x9729, 0xF37B, 0x972B,
+ 0xF37C, 0x972C, 0xF37D, 0x9728, 0xF37E, 0x9726, 0xF3A1, 0x97B3, 0xF3A2, 0x97B7, 0xF3A3, 0x97B6, 0xF3A4, 0x97DD, 0xF3A5, 0x97DE,
+ 0xF3A6, 0x97DF, 0xF3A7, 0x985C, 0xF3A8, 0x9859, 0xF3A9, 0x985D, 0xF3AA, 0x9857, 0xF3AB, 0x98BF, 0xF3AC, 0x98BD, 0xF3AD, 0x98BB,
+ 0xF3AE, 0x98BE, 0xF3AF, 0x9948, 0xF3B0, 0x9947, 0xF3B1, 0x9943, 0xF3B2, 0x99A6, 0xF3B3, 0x99A7, 0xF3B4, 0x9A1A, 0xF3B5, 0x9A15,
+ 0xF3B6, 0x9A25, 0xF3B7, 0x9A1D, 0xF3B8, 0x9A24, 0xF3B9, 0x9A1B, 0xF3BA, 0x9A22, 0xF3BB, 0x9A20, 0xF3BC, 0x9A27, 0xF3BD, 0x9A23,
+ 0xF3BE, 0x9A1E, 0xF3BF, 0x9A1C, 0xF3C0, 0x9A14, 0xF3C1, 0x9AC2, 0xF3C2, 0x9B0B, 0xF3C3, 0x9B0A, 0xF3C4, 0x9B0E, 0xF3C5, 0x9B0C,
+ 0xF3C6, 0x9B37, 0xF3C7, 0x9BEA, 0xF3C8, 0x9BEB, 0xF3C9, 0x9BE0, 0xF3CA, 0x9BDE, 0xF3CB, 0x9BE4, 0xF3CC, 0x9BE6, 0xF3CD, 0x9BE2,
+ 0xF3CE, 0x9BF0, 0xF3CF, 0x9BD4, 0xF3D0, 0x9BD7, 0xF3D1, 0x9BEC, 0xF3D2, 0x9BDC, 0xF3D3, 0x9BD9, 0xF3D4, 0x9BE5, 0xF3D5, 0x9BD5,
+ 0xF3D6, 0x9BE1, 0xF3D7, 0x9BDA, 0xF3D8, 0x9D77, 0xF3D9, 0x9D81, 0xF3DA, 0x9D8A, 0xF3DB, 0x9D84, 0xF3DC, 0x9D88, 0xF3DD, 0x9D71,
+ 0xF3DE, 0x9D80, 0xF3DF, 0x9D78, 0xF3E0, 0x9D86, 0xF3E1, 0x9D8B, 0xF3E2, 0x9D8C, 0xF3E3, 0x9D7D, 0xF3E4, 0x9D6B, 0xF3E5, 0x9D74,
+ 0xF3E6, 0x9D75, 0xF3E7, 0x9D70, 0xF3E8, 0x9D69, 0xF3E9, 0x9D85, 0xF3EA, 0x9D73, 0xF3EB, 0x9D7B, 0xF3EC, 0x9D82, 0xF3ED, 0x9D6F,
+ 0xF3EE, 0x9D79, 0xF3EF, 0x9D7F, 0xF3F0, 0x9D87, 0xF3F1, 0x9D68, 0xF3F2, 0x9E94, 0xF3F3, 0x9E91, 0xF3F4, 0x9EC0, 0xF3F5, 0x9EFC,
+ 0xF3F6, 0x9F2D, 0xF3F7, 0x9F40, 0xF3F8, 0x9F41, 0xF3F9, 0x9F4D, 0xF3FA, 0x9F56, 0xF3FB, 0x9F57, 0xF3FC, 0x9F58, 0xF3FD, 0x5337,
+ 0xF3FE, 0x56B2, 0xF440, 0x56B5, 0xF441, 0x56B3, 0xF442, 0x58E3, 0xF443, 0x5B45, 0xF444, 0x5DC6, 0xF445, 0x5DC7, 0xF446, 0x5EEE,
+ 0xF447, 0x5EEF, 0xF448, 0x5FC0, 0xF449, 0x5FC1, 0xF44A, 0x61F9, 0xF44B, 0x6517, 0xF44C, 0x6516, 0xF44D, 0x6515, 0xF44E, 0x6513,
+ 0xF44F, 0x65DF, 0xF450, 0x66E8, 0xF451, 0x66E3, 0xF452, 0x66E4, 0xF453, 0x6AF3, 0xF454, 0x6AF0, 0xF455, 0x6AEA, 0xF456, 0x6AE8,
+ 0xF457, 0x6AF9, 0xF458, 0x6AF1, 0xF459, 0x6AEE, 0xF45A, 0x6AEF, 0xF45B, 0x703C, 0xF45C, 0x7035, 0xF45D, 0x702F, 0xF45E, 0x7037,
+ 0xF45F, 0x7034, 0xF460, 0x7031, 0xF461, 0x7042, 0xF462, 0x7038, 0xF463, 0x703F, 0xF464, 0x703A, 0xF465, 0x7039, 0xF466, 0x7040,
+ 0xF467, 0x703B, 0xF468, 0x7033, 0xF469, 0x7041, 0xF46A, 0x7213, 0xF46B, 0x7214, 0xF46C, 0x72A8, 0xF46D, 0x737D, 0xF46E, 0x737C,
+ 0xF46F, 0x74BA, 0xF470, 0x76AB, 0xF471, 0x76AA, 0xF472, 0x76BE, 0xF473, 0x76ED, 0xF474, 0x77CC, 0xF475, 0x77CE, 0xF476, 0x77CF,
+ 0xF477, 0x77CD, 0xF478, 0x77F2, 0xF479, 0x7925, 0xF47A, 0x7923, 0xF47B, 0x7927, 0xF47C, 0x7928, 0xF47D, 0x7924, 0xF47E, 0x7929,
+ 0xF4A1, 0x79B2, 0xF4A2, 0x7A6E, 0xF4A3, 0x7A6C, 0xF4A4, 0x7A6D, 0xF4A5, 0x7AF7, 0xF4A6, 0x7C49, 0xF4A7, 0x7C48, 0xF4A8, 0x7C4A,
+ 0xF4A9, 0x7C47, 0xF4AA, 0x7C45, 0xF4AB, 0x7CEE, 0xF4AC, 0x7E7B, 0xF4AD, 0x7E7E, 0xF4AE, 0x7E81, 0xF4AF, 0x7E80, 0xF4B0, 0x7FBA,
+ 0xF4B1, 0x7FFF, 0xF4B2, 0x8079, 0xF4B3, 0x81DB, 0xF4B4, 0x81D9, 0xF4B5, 0x820B, 0xF4B6, 0x8268, 0xF4B7, 0x8269, 0xF4B8, 0x8622,
+ 0xF4B9, 0x85FF, 0xF4BA, 0x8601, 0xF4BB, 0x85FE, 0xF4BC, 0x861B, 0xF4BD, 0x8600, 0xF4BE, 0x85F6, 0xF4BF, 0x8604, 0xF4C0, 0x8609,
+ 0xF4C1, 0x8605, 0xF4C2, 0x860C, 0xF4C3, 0x85FD, 0xF4C4, 0x8819, 0xF4C5, 0x8810, 0xF4C6, 0x8811, 0xF4C7, 0x8817, 0xF4C8, 0x8813,
+ 0xF4C9, 0x8816, 0xF4CA, 0x8963, 0xF4CB, 0x8966, 0xF4CC, 0x89B9, 0xF4CD, 0x89F7, 0xF4CE, 0x8B60, 0xF4CF, 0x8B6A, 0xF4D0, 0x8B5D,
+ 0xF4D1, 0x8B68, 0xF4D2, 0x8B63, 0xF4D3, 0x8B65, 0xF4D4, 0x8B67, 0xF4D5, 0x8B6D, 0xF4D6, 0x8DAE, 0xF4D7, 0x8E86, 0xF4D8, 0x8E88,
+ 0xF4D9, 0x8E84, 0xF4DA, 0x8F59, 0xF4DB, 0x8F56, 0xF4DC, 0x8F57, 0xF4DD, 0x8F55, 0xF4DE, 0x8F58, 0xF4DF, 0x8F5A, 0xF4E0, 0x908D,
+ 0xF4E1, 0x9143, 0xF4E2, 0x9141, 0xF4E3, 0x91B7, 0xF4E4, 0x91B5, 0xF4E5, 0x91B2, 0xF4E6, 0x91B3, 0xF4E7, 0x940B, 0xF4E8, 0x9413,
+ 0xF4E9, 0x93FB, 0xF4EA, 0x9420, 0xF4EB, 0x940F, 0xF4EC, 0x9414, 0xF4ED, 0x93FE, 0xF4EE, 0x9415, 0xF4EF, 0x9410, 0xF4F0, 0x9428,
+ 0xF4F1, 0x9419, 0xF4F2, 0x940D, 0xF4F3, 0x93F5, 0xF4F4, 0x9400, 0xF4F5, 0x93F7, 0xF4F6, 0x9407, 0xF4F7, 0x940E, 0xF4F8, 0x9416,
+ 0xF4F9, 0x9412, 0xF4FA, 0x93FA, 0xF4FB, 0x9409, 0xF4FC, 0x93F8, 0xF4FD, 0x940A, 0xF4FE, 0x93FF, 0xF540, 0x93FC, 0xF541, 0x940C,
+ 0xF542, 0x93F6, 0xF543, 0x9411, 0xF544, 0x9406, 0xF545, 0x95DE, 0xF546, 0x95E0, 0xF547, 0x95DF, 0xF548, 0x972E, 0xF549, 0x972F,
+ 0xF54A, 0x97B9, 0xF54B, 0x97BB, 0xF54C, 0x97FD, 0xF54D, 0x97FE, 0xF54E, 0x9860, 0xF54F, 0x9862, 0xF550, 0x9863, 0xF551, 0x985F,
+ 0xF552, 0x98C1, 0xF553, 0x98C2, 0xF554, 0x9950, 0xF555, 0x994E, 0xF556, 0x9959, 0xF557, 0x994C, 0xF558, 0x994B, 0xF559, 0x9953,
+ 0xF55A, 0x9A32, 0xF55B, 0x9A34, 0xF55C, 0x9A31, 0xF55D, 0x9A2C, 0xF55E, 0x9A2A, 0xF55F, 0x9A36, 0xF560, 0x9A29, 0xF561, 0x9A2E,
+ 0xF562, 0x9A38, 0xF563, 0x9A2D, 0xF564, 0x9AC7, 0xF565, 0x9ACA, 0xF566, 0x9AC6, 0xF567, 0x9B10, 0xF568, 0x9B12, 0xF569, 0x9B11,
+ 0xF56A, 0x9C0B, 0xF56B, 0x9C08, 0xF56C, 0x9BF7, 0xF56D, 0x9C05, 0xF56E, 0x9C12, 0xF56F, 0x9BF8, 0xF570, 0x9C40, 0xF571, 0x9C07,
+ 0xF572, 0x9C0E, 0xF573, 0x9C06, 0xF574, 0x9C17, 0xF575, 0x9C14, 0xF576, 0x9C09, 0xF577, 0x9D9F, 0xF578, 0x9D99, 0xF579, 0x9DA4,
+ 0xF57A, 0x9D9D, 0xF57B, 0x9D92, 0xF57C, 0x9D98, 0xF57D, 0x9D90, 0xF57E, 0x9D9B, 0xF5A1, 0x9DA0, 0xF5A2, 0x9D94, 0xF5A3, 0x9D9C,
+ 0xF5A4, 0x9DAA, 0xF5A5, 0x9D97, 0xF5A6, 0x9DA1, 0xF5A7, 0x9D9A, 0xF5A8, 0x9DA2, 0xF5A9, 0x9DA8, 0xF5AA, 0x9D9E, 0xF5AB, 0x9DA3,
+ 0xF5AC, 0x9DBF, 0xF5AD, 0x9DA9, 0xF5AE, 0x9D96, 0xF5AF, 0x9DA6, 0xF5B0, 0x9DA7, 0xF5B1, 0x9E99, 0xF5B2, 0x9E9B, 0xF5B3, 0x9E9A,
+ 0xF5B4, 0x9EE5, 0xF5B5, 0x9EE4, 0xF5B6, 0x9EE7, 0xF5B7, 0x9EE6, 0xF5B8, 0x9F30, 0xF5B9, 0x9F2E, 0xF5BA, 0x9F5B, 0xF5BB, 0x9F60,
+ 0xF5BC, 0x9F5E, 0xF5BD, 0x9F5D, 0xF5BE, 0x9F59, 0xF5BF, 0x9F91, 0xF5C0, 0x513A, 0xF5C1, 0x5139, 0xF5C2, 0x5298, 0xF5C3, 0x5297,
+ 0xF5C4, 0x56C3, 0xF5C5, 0x56BD, 0xF5C6, 0x56BE, 0xF5C7, 0x5B48, 0xF5C8, 0x5B47, 0xF5C9, 0x5DCB, 0xF5CA, 0x5DCF, 0xF5CB, 0x5EF1,
+ 0xF5CC, 0x61FD, 0xF5CD, 0x651B, 0xF5CE, 0x6B02, 0xF5CF, 0x6AFC, 0xF5D0, 0x6B03, 0xF5D1, 0x6AF8, 0xF5D2, 0x6B00, 0xF5D3, 0x7043,
+ 0xF5D4, 0x7044, 0xF5D5, 0x704A, 0xF5D6, 0x7048, 0xF5D7, 0x7049, 0xF5D8, 0x7045, 0xF5D9, 0x7046, 0xF5DA, 0x721D, 0xF5DB, 0x721A,
+ 0xF5DC, 0x7219, 0xF5DD, 0x737E, 0xF5DE, 0x7517, 0xF5DF, 0x766A, 0xF5E0, 0x77D0, 0xF5E1, 0x792D, 0xF5E2, 0x7931, 0xF5E3, 0x792F,
+ 0xF5E4, 0x7C54, 0xF5E5, 0x7C53, 0xF5E6, 0x7CF2, 0xF5E7, 0x7E8A, 0xF5E8, 0x7E87, 0xF5E9, 0x7E88, 0xF5EA, 0x7E8B, 0xF5EB, 0x7E86,
+ 0xF5EC, 0x7E8D, 0xF5ED, 0x7F4D, 0xF5EE, 0x7FBB, 0xF5EF, 0x8030, 0xF5F0, 0x81DD, 0xF5F1, 0x8618, 0xF5F2, 0x862A, 0xF5F3, 0x8626,
+ 0xF5F4, 0x861F, 0xF5F5, 0x8623, 0xF5F6, 0x861C, 0xF5F7, 0x8619, 0xF5F8, 0x8627, 0xF5F9, 0x862E, 0xF5FA, 0x8621, 0xF5FB, 0x8620,
+ 0xF5FC, 0x8629, 0xF5FD, 0x861E, 0xF5FE, 0x8625, 0xF640, 0x8829, 0xF641, 0x881D, 0xF642, 0x881B, 0xF643, 0x8820, 0xF644, 0x8824,
+ 0xF645, 0x881C, 0xF646, 0x882B, 0xF647, 0x884A, 0xF648, 0x896D, 0xF649, 0x8969, 0xF64A, 0x896E, 0xF64B, 0x896B, 0xF64C, 0x89FA,
+ 0xF64D, 0x8B79, 0xF64E, 0x8B78, 0xF64F, 0x8B45, 0xF650, 0x8B7A, 0xF651, 0x8B7B, 0xF652, 0x8D10, 0xF653, 0x8D14, 0xF654, 0x8DAF,
+ 0xF655, 0x8E8E, 0xF656, 0x8E8C, 0xF657, 0x8F5E, 0xF658, 0x8F5B, 0xF659, 0x8F5D, 0xF65A, 0x9146, 0xF65B, 0x9144, 0xF65C, 0x9145,
+ 0xF65D, 0x91B9, 0xF65E, 0x943F, 0xF65F, 0x943B, 0xF660, 0x9436, 0xF661, 0x9429, 0xF662, 0x943D, 0xF663, 0x943C, 0xF664, 0x9430,
+ 0xF665, 0x9439, 0xF666, 0x942A, 0xF667, 0x9437, 0xF668, 0x942C, 0xF669, 0x9440, 0xF66A, 0x9431, 0xF66B, 0x95E5, 0xF66C, 0x95E4,
+ 0xF66D, 0x95E3, 0xF66E, 0x9735, 0xF66F, 0x973A, 0xF670, 0x97BF, 0xF671, 0x97E1, 0xF672, 0x9864, 0xF673, 0x98C9, 0xF674, 0x98C6,
+ 0xF675, 0x98C0, 0xF676, 0x9958, 0xF677, 0x9956, 0xF678, 0x9A39, 0xF679, 0x9A3D, 0xF67A, 0x9A46, 0xF67B, 0x9A44, 0xF67C, 0x9A42,
+ 0xF67D, 0x9A41, 0xF67E, 0x9A3A, 0xF6A1, 0x9A3F, 0xF6A2, 0x9ACD, 0xF6A3, 0x9B15, 0xF6A4, 0x9B17, 0xF6A5, 0x9B18, 0xF6A6, 0x9B16,
+ 0xF6A7, 0x9B3A, 0xF6A8, 0x9B52, 0xF6A9, 0x9C2B, 0xF6AA, 0x9C1D, 0xF6AB, 0x9C1C, 0xF6AC, 0x9C2C, 0xF6AD, 0x9C23, 0xF6AE, 0x9C28,
+ 0xF6AF, 0x9C29, 0xF6B0, 0x9C24, 0xF6B1, 0x9C21, 0xF6B2, 0x9DB7, 0xF6B3, 0x9DB6, 0xF6B4, 0x9DBC, 0xF6B5, 0x9DC1, 0xF6B6, 0x9DC7,
+ 0xF6B7, 0x9DCA, 0xF6B8, 0x9DCF, 0xF6B9, 0x9DBE, 0xF6BA, 0x9DC5, 0xF6BB, 0x9DC3, 0xF6BC, 0x9DBB, 0xF6BD, 0x9DB5, 0xF6BE, 0x9DCE,
+ 0xF6BF, 0x9DB9, 0xF6C0, 0x9DBA, 0xF6C1, 0x9DAC, 0xF6C2, 0x9DC8, 0xF6C3, 0x9DB1, 0xF6C4, 0x9DAD, 0xF6C5, 0x9DCC, 0xF6C6, 0x9DB3,
+ 0xF6C7, 0x9DCD, 0xF6C8, 0x9DB2, 0xF6C9, 0x9E7A, 0xF6CA, 0x9E9C, 0xF6CB, 0x9EEB, 0xF6CC, 0x9EEE, 0xF6CD, 0x9EED, 0xF6CE, 0x9F1B,
+ 0xF6CF, 0x9F18, 0xF6D0, 0x9F1A, 0xF6D1, 0x9F31, 0xF6D2, 0x9F4E, 0xF6D3, 0x9F65, 0xF6D4, 0x9F64, 0xF6D5, 0x9F92, 0xF6D6, 0x4EB9,
+ 0xF6D7, 0x56C6, 0xF6D8, 0x56C5, 0xF6D9, 0x56CB, 0xF6DA, 0x5971, 0xF6DB, 0x5B4B, 0xF6DC, 0x5B4C, 0xF6DD, 0x5DD5, 0xF6DE, 0x5DD1,
+ 0xF6DF, 0x5EF2, 0xF6E0, 0x6521, 0xF6E1, 0x6520, 0xF6E2, 0x6526, 0xF6E3, 0x6522, 0xF6E4, 0x6B0B, 0xF6E5, 0x6B08, 0xF6E6, 0x6B09,
+ 0xF6E7, 0x6C0D, 0xF6E8, 0x7055, 0xF6E9, 0x7056, 0xF6EA, 0x7057, 0xF6EB, 0x7052, 0xF6EC, 0x721E, 0xF6ED, 0x721F, 0xF6EE, 0x72A9,
+ 0xF6EF, 0x737F, 0xF6F0, 0x74D8, 0xF6F1, 0x74D5, 0xF6F2, 0x74D9, 0xF6F3, 0x74D7, 0xF6F4, 0x766D, 0xF6F5, 0x76AD, 0xF6F6, 0x7935,
+ 0xF6F7, 0x79B4, 0xF6F8, 0x7A70, 0xF6F9, 0x7A71, 0xF6FA, 0x7C57, 0xF6FB, 0x7C5C, 0xF6FC, 0x7C59, 0xF6FD, 0x7C5B, 0xF6FE, 0x7C5A,
+ 0xF740, 0x7CF4, 0xF741, 0x7CF1, 0xF742, 0x7E91, 0xF743, 0x7F4F, 0xF744, 0x7F87, 0xF745, 0x81DE, 0xF746, 0x826B, 0xF747, 0x8634,
+ 0xF748, 0x8635, 0xF749, 0x8633, 0xF74A, 0x862C, 0xF74B, 0x8632, 0xF74C, 0x8636, 0xF74D, 0x882C, 0xF74E, 0x8828, 0xF74F, 0x8826,
+ 0xF750, 0x882A, 0xF751, 0x8825, 0xF752, 0x8971, 0xF753, 0x89BF, 0xF754, 0x89BE, 0xF755, 0x89FB, 0xF756, 0x8B7E, 0xF757, 0x8B84,
+ 0xF758, 0x8B82, 0xF759, 0x8B86, 0xF75A, 0x8B85, 0xF75B, 0x8B7F, 0xF75C, 0x8D15, 0xF75D, 0x8E95, 0xF75E, 0x8E94, 0xF75F, 0x8E9A,
+ 0xF760, 0x8E92, 0xF761, 0x8E90, 0xF762, 0x8E96, 0xF763, 0x8E97, 0xF764, 0x8F60, 0xF765, 0x8F62, 0xF766, 0x9147, 0xF767, 0x944C,
+ 0xF768, 0x9450, 0xF769, 0x944A, 0xF76A, 0x944B, 0xF76B, 0x944F, 0xF76C, 0x9447, 0xF76D, 0x9445, 0xF76E, 0x9448, 0xF76F, 0x9449,
+ 0xF770, 0x9446, 0xF771, 0x973F, 0xF772, 0x97E3, 0xF773, 0x986A, 0xF774, 0x9869, 0xF775, 0x98CB, 0xF776, 0x9954, 0xF777, 0x995B,
+ 0xF778, 0x9A4E, 0xF779, 0x9A53, 0xF77A, 0x9A54, 0xF77B, 0x9A4C, 0xF77C, 0x9A4F, 0xF77D, 0x9A48, 0xF77E, 0x9A4A, 0xF7A1, 0x9A49,
+ 0xF7A2, 0x9A52, 0xF7A3, 0x9A50, 0xF7A4, 0x9AD0, 0xF7A5, 0x9B19, 0xF7A6, 0x9B2B, 0xF7A7, 0x9B3B, 0xF7A8, 0x9B56, 0xF7A9, 0x9B55,
+ 0xF7AA, 0x9C46, 0xF7AB, 0x9C48, 0xF7AC, 0x9C3F, 0xF7AD, 0x9C44, 0xF7AE, 0x9C39, 0xF7AF, 0x9C33, 0xF7B0, 0x9C41, 0xF7B1, 0x9C3C,
+ 0xF7B2, 0x9C37, 0xF7B3, 0x9C34, 0xF7B4, 0x9C32, 0xF7B5, 0x9C3D, 0xF7B6, 0x9C36, 0xF7B7, 0x9DDB, 0xF7B8, 0x9DD2, 0xF7B9, 0x9DDE,
+ 0xF7BA, 0x9DDA, 0xF7BB, 0x9DCB, 0xF7BC, 0x9DD0, 0xF7BD, 0x9DDC, 0xF7BE, 0x9DD1, 0xF7BF, 0x9DDF, 0xF7C0, 0x9DE9, 0xF7C1, 0x9DD9,
+ 0xF7C2, 0x9DD8, 0xF7C3, 0x9DD6, 0xF7C4, 0x9DF5, 0xF7C5, 0x9DD5, 0xF7C6, 0x9DDD, 0xF7C7, 0x9EB6, 0xF7C8, 0x9EF0, 0xF7C9, 0x9F35,
+ 0xF7CA, 0x9F33, 0xF7CB, 0x9F32, 0xF7CC, 0x9F42, 0xF7CD, 0x9F6B, 0xF7CE, 0x9F95, 0xF7CF, 0x9FA2, 0xF7D0, 0x513D, 0xF7D1, 0x5299,
+ 0xF7D2, 0x58E8, 0xF7D3, 0x58E7, 0xF7D4, 0x5972, 0xF7D5, 0x5B4D, 0xF7D6, 0x5DD8, 0xF7D7, 0x882F, 0xF7D8, 0x5F4F, 0xF7D9, 0x6201,
+ 0xF7DA, 0x6203, 0xF7DB, 0x6204, 0xF7DC, 0x6529, 0xF7DD, 0x6525, 0xF7DE, 0x6596, 0xF7DF, 0x66EB, 0xF7E0, 0x6B11, 0xF7E1, 0x6B12,
+ 0xF7E2, 0x6B0F, 0xF7E3, 0x6BCA, 0xF7E4, 0x705B, 0xF7E5, 0x705A, 0xF7E6, 0x7222, 0xF7E7, 0x7382, 0xF7E8, 0x7381, 0xF7E9, 0x7383,
+ 0xF7EA, 0x7670, 0xF7EB, 0x77D4, 0xF7EC, 0x7C67, 0xF7ED, 0x7C66, 0xF7EE, 0x7E95, 0xF7EF, 0x826C, 0xF7F0, 0x863A, 0xF7F1, 0x8640,
+ 0xF7F2, 0x8639, 0xF7F3, 0x863C, 0xF7F4, 0x8631, 0xF7F5, 0x863B, 0xF7F6, 0x863E, 0xF7F7, 0x8830, 0xF7F8, 0x8832, 0xF7F9, 0x882E,
+ 0xF7FA, 0x8833, 0xF7FB, 0x8976, 0xF7FC, 0x8974, 0xF7FD, 0x8973, 0xF7FE, 0x89FE, 0xF840, 0x8B8C, 0xF841, 0x8B8E, 0xF842, 0x8B8B,
+ 0xF843, 0x8B88, 0xF844, 0x8C45, 0xF845, 0x8D19, 0xF846, 0x8E98, 0xF847, 0x8F64, 0xF848, 0x8F63, 0xF849, 0x91BC, 0xF84A, 0x9462,
+ 0xF84B, 0x9455, 0xF84C, 0x945D, 0xF84D, 0x9457, 0xF84E, 0x945E, 0xF84F, 0x97C4, 0xF850, 0x97C5, 0xF851, 0x9800, 0xF852, 0x9A56,
+ 0xF853, 0x9A59, 0xF854, 0x9B1E, 0xF855, 0x9B1F, 0xF856, 0x9B20, 0xF857, 0x9C52, 0xF858, 0x9C58, 0xF859, 0x9C50, 0xF85A, 0x9C4A,
+ 0xF85B, 0x9C4D, 0xF85C, 0x9C4B, 0xF85D, 0x9C55, 0xF85E, 0x9C59, 0xF85F, 0x9C4C, 0xF860, 0x9C4E, 0xF861, 0x9DFB, 0xF862, 0x9DF7,
+ 0xF863, 0x9DEF, 0xF864, 0x9DE3, 0xF865, 0x9DEB, 0xF866, 0x9DF8, 0xF867, 0x9DE4, 0xF868, 0x9DF6, 0xF869, 0x9DE1, 0xF86A, 0x9DEE,
+ 0xF86B, 0x9DE6, 0xF86C, 0x9DF2, 0xF86D, 0x9DF0, 0xF86E, 0x9DE2, 0xF86F, 0x9DEC, 0xF870, 0x9DF4, 0xF871, 0x9DF3, 0xF872, 0x9DE8,
+ 0xF873, 0x9DED, 0xF874, 0x9EC2, 0xF875, 0x9ED0, 0xF876, 0x9EF2, 0xF877, 0x9EF3, 0xF878, 0x9F06, 0xF879, 0x9F1C, 0xF87A, 0x9F38,
+ 0xF87B, 0x9F37, 0xF87C, 0x9F36, 0xF87D, 0x9F43, 0xF87E, 0x9F4F, 0xF8A1, 0x9F71, 0xF8A2, 0x9F70, 0xF8A3, 0x9F6E, 0xF8A4, 0x9F6F,
+ 0xF8A5, 0x56D3, 0xF8A6, 0x56CD, 0xF8A7, 0x5B4E, 0xF8A8, 0x5C6D, 0xF8A9, 0x652D, 0xF8AA, 0x66ED, 0xF8AB, 0x66EE, 0xF8AC, 0x6B13,
+ 0xF8AD, 0x705F, 0xF8AE, 0x7061, 0xF8AF, 0x705D, 0xF8B0, 0x7060, 0xF8B1, 0x7223, 0xF8B2, 0x74DB, 0xF8B3, 0x74E5, 0xF8B4, 0x77D5,
+ 0xF8B5, 0x7938, 0xF8B6, 0x79B7, 0xF8B7, 0x79B6, 0xF8B8, 0x7C6A, 0xF8B9, 0x7E97, 0xF8BA, 0x7F89, 0xF8BB, 0x826D, 0xF8BC, 0x8643,
+ 0xF8BD, 0x8838, 0xF8BE, 0x8837, 0xF8BF, 0x8835, 0xF8C0, 0x884B, 0xF8C1, 0x8B94, 0xF8C2, 0x8B95, 0xF8C3, 0x8E9E, 0xF8C4, 0x8E9F,
+ 0xF8C5, 0x8EA0, 0xF8C6, 0x8E9D, 0xF8C7, 0x91BE, 0xF8C8, 0x91BD, 0xF8C9, 0x91C2, 0xF8CA, 0x946B, 0xF8CB, 0x9468, 0xF8CC, 0x9469,
+ 0xF8CD, 0x96E5, 0xF8CE, 0x9746, 0xF8CF, 0x9743, 0xF8D0, 0x9747, 0xF8D1, 0x97C7, 0xF8D2, 0x97E5, 0xF8D3, 0x9A5E, 0xF8D4, 0x9AD5,
+ 0xF8D5, 0x9B59, 0xF8D6, 0x9C63, 0xF8D7, 0x9C67, 0xF8D8, 0x9C66, 0xF8D9, 0x9C62, 0xF8DA, 0x9C5E, 0xF8DB, 0x9C60, 0xF8DC, 0x9E02,
+ 0xF8DD, 0x9DFE, 0xF8DE, 0x9E07, 0xF8DF, 0x9E03, 0xF8E0, 0x9E06, 0xF8E1, 0x9E05, 0xF8E2, 0x9E00, 0xF8E3, 0x9E01, 0xF8E4, 0x9E09,
+ 0xF8E5, 0x9DFF, 0xF8E6, 0x9DFD, 0xF8E7, 0x9E04, 0xF8E8, 0x9EA0, 0xF8E9, 0x9F1E, 0xF8EA, 0x9F46, 0xF8EB, 0x9F74, 0xF8EC, 0x9F75,
+ 0xF8ED, 0x9F76, 0xF8EE, 0x56D4, 0xF8EF, 0x652E, 0xF8F0, 0x65B8, 0xF8F1, 0x6B18, 0xF8F2, 0x6B19, 0xF8F3, 0x6B17, 0xF8F4, 0x6B1A,
+ 0xF8F5, 0x7062, 0xF8F6, 0x7226, 0xF8F7, 0x72AA, 0xF8F8, 0x77D8, 0xF8F9, 0x77D9, 0xF8FA, 0x7939, 0xF8FB, 0x7C69, 0xF8FC, 0x7C6B,
+ 0xF8FD, 0x7CF6, 0xF8FE, 0x7E9A, 0xF940, 0x7E98, 0xF941, 0x7E9B, 0xF942, 0x7E99, 0xF943, 0x81E0, 0xF944, 0x81E1, 0xF945, 0x8646,
+ 0xF946, 0x8647, 0xF947, 0x8648, 0xF948, 0x8979, 0xF949, 0x897A, 0xF94A, 0x897C, 0xF94B, 0x897B, 0xF94C, 0x89FF, 0xF94D, 0x8B98,
+ 0xF94E, 0x8B99, 0xF94F, 0x8EA5, 0xF950, 0x8EA4, 0xF951, 0x8EA3, 0xF952, 0x946E, 0xF953, 0x946D, 0xF954, 0x946F, 0xF955, 0x9471,
+ 0xF956, 0x9473, 0xF957, 0x9749, 0xF958, 0x9872, 0xF959, 0x995F, 0xF95A, 0x9C68, 0xF95B, 0x9C6E, 0xF95C, 0x9C6D, 0xF95D, 0x9E0B,
+ 0xF95E, 0x9E0D, 0xF95F, 0x9E10, 0xF960, 0x9E0F, 0xF961, 0x9E12, 0xF962, 0x9E11, 0xF963, 0x9EA1, 0xF964, 0x9EF5, 0xF965, 0x9F09,
+ 0xF966, 0x9F47, 0xF967, 0x9F78, 0xF968, 0x9F7B, 0xF969, 0x9F7A, 0xF96A, 0x9F79, 0xF96B, 0x571E, 0xF96C, 0x7066, 0xF96D, 0x7C6F,
+ 0xF96E, 0x883C, 0xF96F, 0x8DB2, 0xF970, 0x8EA6, 0xF971, 0x91C3, 0xF972, 0x9474, 0xF973, 0x9478, 0xF974, 0x9476, 0xF975, 0x9475,
+ 0xF976, 0x9A60, 0xF977, 0x9C74, 0xF978, 0x9C73, 0xF979, 0x9C71, 0xF97A, 0x9C75, 0xF97B, 0x9E14, 0xF97C, 0x9E13, 0xF97D, 0x9EF6,
+ 0xF97E, 0x9F0A, 0xF9A1, 0x9FA4, 0xF9A2, 0x7068, 0xF9A3, 0x7065, 0xF9A4, 0x7CF7, 0xF9A5, 0x866A, 0xF9A6, 0x883E, 0xF9A7, 0x883D,
+ 0xF9A8, 0x883F, 0xF9A9, 0x8B9E, 0xF9AA, 0x8C9C, 0xF9AB, 0x8EA9, 0xF9AC, 0x8EC9, 0xF9AD, 0x974B, 0xF9AE, 0x9873, 0xF9AF, 0x9874,
+ 0xF9B0, 0x98CC, 0xF9B1, 0x9961, 0xF9B2, 0x99AB, 0xF9B3, 0x9A64, 0xF9B4, 0x9A66, 0xF9B5, 0x9A67, 0xF9B6, 0x9B24, 0xF9B7, 0x9E15,
+ 0xF9B8, 0x9E17, 0xF9B9, 0x9F48, 0xF9BA, 0x6207, 0xF9BB, 0x6B1E, 0xF9BC, 0x7227, 0xF9BD, 0x864C, 0xF9BE, 0x8EA8, 0xF9BF, 0x9482,
+ 0xF9C0, 0x9480, 0xF9C1, 0x9481, 0xF9C2, 0x9A69, 0xF9C3, 0x9A68, 0xF9C4, 0x9B2E, 0xF9C5, 0x9E19, 0xF9C6, 0x7229, 0xF9C7, 0x864B,
+ 0xF9C8, 0x8B9F, 0xF9C9, 0x9483, 0xF9CA, 0x9C79, 0xF9CB, 0x9EB7, 0xF9CC, 0x7675, 0xF9CD, 0x9A6B, 0xF9CE, 0x9C7A, 0xF9CF, 0x9E1D,
+ 0xF9D0, 0x7069, 0xF9D1, 0x706A, 0xF9D2, 0x9EA4, 0xF9D3, 0x9F7E, 0xF9D4, 0x9F49, 0xF9D5, 0x9F98, 0xF9D6, 0x7881, 0xF9D7, 0x92B9,
+ 0xF9D8, 0x88CF, 0xF9D9, 0x58BB, 0xF9DA, 0x6052, 0xF9DB, 0x7CA7, 0xF9DC, 0x5AFA, 0xF9DD, 0x2554, 0xF9DE, 0x2566, 0xF9DF, 0x2557,
+ 0xF9E0, 0x2560, 0xF9E1, 0x256C, 0xF9E2, 0x2563, 0xF9E3, 0x255A, 0xF9E4, 0x2569, 0xF9E5, 0x255D, 0xF9E6, 0x2552, 0xF9E7, 0x2564,
+ 0xF9E8, 0x2555, 0xF9E9, 0x255E, 0xF9EA, 0x256A, 0xF9EB, 0x2561, 0xF9EC, 0x2558, 0xF9ED, 0x2567, 0xF9EE, 0x255B, 0xF9EF, 0x2553,
+ 0xF9F0, 0x2565, 0xF9F1, 0x2556, 0xF9F2, 0x255F, 0xF9F3, 0x256B, 0xF9F4, 0x2562, 0xF9F5, 0x2559, 0xF9F6, 0x2568, 0xF9F7, 0x255C,
+ 0xF9F8, 0x2551, 0xF9F9, 0x2550, 0xF9FA, 0x256D, 0xF9FB, 0x256E, 0xF9FC, 0x2570, 0xF9FD, 0x256F, 0xF9FE, 0x2593, 0, 0
+};
+#endif
+
+#if FF_CODE_PAGE == 437 || FF_CODE_PAGE == 0
+static const WCHAR uc437[] = { /* CP437(U.S.) to Unicode conversion table */
+ 0x00C7, 0x00FC, 0x00E9, 0x00E2, 0x00E4, 0x00E0, 0x00E5, 0x00E7, 0x00EA, 0x00EB, 0x00E8, 0x00EF, 0x00EE, 0x00EC, 0x00C4, 0x00C5,
+ 0x00C9, 0x00E6, 0x00C6, 0x00F4, 0x00F6, 0x00F2, 0x00FB, 0x00F9, 0x00FF, 0x00D6, 0x00DC, 0x00A2, 0x00A3, 0x00A5, 0x20A7, 0x0192,
+ 0x00E1, 0x00ED, 0x00F3, 0x00FA, 0x00F1, 0x00D1, 0x00AA, 0x00BA, 0x00BF, 0x2310, 0x00AC, 0x00BD, 0x00BC, 0x00A1, 0x00AB, 0x00BB,
+ 0x2591, 0x2592, 0x2593, 0x2502, 0x2524, 0x2561, 0x2562, 0x2556, 0x2555, 0x2563, 0x2551, 0x2557, 0x255D, 0x255C, 0x255B, 0x2510,
+ 0x2514, 0x2534, 0x252C, 0x251C, 0x2500, 0x253C, 0x255E, 0x255F, 0x255A, 0x2554, 0x2569, 0x2566, 0x2560, 0x2550, 0x256C, 0x2567,
+ 0x2568, 0x2564, 0x2565, 0x2559, 0x2558, 0x2552, 0x2553, 0x256B, 0x256A, 0x2518, 0x250C, 0x2588, 0x2584, 0x258C, 0x2590, 0x2580,
+ 0x03B1, 0x00DF, 0x0393, 0x03C0, 0x03A3, 0x03C3, 0x00B5, 0x03C4, 0x03A6, 0x0398, 0x03A9, 0x03B4, 0x221E, 0x03C6, 0x03B5, 0x2229,
+ 0x2261, 0x00B1, 0x2265, 0x2264, 0x2320, 0x2321, 0x00F7, 0x2248, 0x00B0, 0x2219, 0x00B7, 0x221A, 0x207F, 0x00B2, 0x25A0, 0x00A0
+};
+#endif
+#if FF_CODE_PAGE == 720 || FF_CODE_PAGE == 0
+static const WCHAR uc720[] = { /* CP720(Arabic) to Unicode conversion table */
+ 0x0000, 0x0000, 0x00E9, 0x00E2, 0x0000, 0x00E0, 0x0000, 0x00E7, 0x00EA, 0x00EB, 0x00E8, 0x00EF, 0x00EE, 0x0000, 0x0000, 0x0000,
+ 0x0000, 0x0651, 0x0652, 0x00F4, 0x00A4, 0x0640, 0x00FB, 0x00F9, 0x0621, 0x0622, 0x0623, 0x0624, 0x00A3, 0x0625, 0x0626, 0x0627,
+ 0x0628, 0x0629, 0x062A, 0x062B, 0x062C, 0x062D, 0x062E, 0x062F, 0x0630, 0x0631, 0x0632, 0x0633, 0x0634, 0x0635, 0x00AB, 0x00BB,
+ 0x2591, 0x2592, 0x2593, 0x2502, 0x2524, 0x2561, 0x2562, 0x2556, 0x2555, 0x2563, 0x2551, 0x2557, 0x255D, 0x255C, 0x255B, 0x2510,
+ 0x2514, 0x2534, 0x252C, 0x251C, 0x2500, 0x253C, 0x255E, 0x255F, 0x255A, 0x2554, 0x2569, 0x2566, 0x2560, 0x2550, 0x256C, 0x2567,
+ 0x2568, 0x2564, 0x2565, 0x2559, 0x2558, 0x2552, 0x2553, 0x256B, 0x256A, 0x2518, 0x250C, 0x2588, 0x2584, 0x258C, 0x2590, 0x2580,
+ 0x0636, 0x0637, 0x0638, 0x0639, 0x063A, 0x0641, 0x00B5, 0x0642, 0x0643, 0x0644, 0x0645, 0x0646, 0x0647, 0x0648, 0x0649, 0x064A,
+ 0x2261, 0x064B, 0x064C, 0x064D, 0x064E, 0x064F, 0x0650, 0x2248, 0x00B0, 0x2219, 0x00B7, 0x221A, 0x207F, 0x00B2, 0x25A0, 0x00A0
+};
+#endif
+#if FF_CODE_PAGE == 737 || FF_CODE_PAGE == 0
+static const WCHAR uc737[] = { /* CP737(Greek) to Unicode conversion table */
+ 0x0391, 0x0392, 0x0393, 0x0394, 0x0395, 0x0396, 0x0397, 0x0398, 0x0399, 0x039A, 0x039B, 0x039C, 0x039D, 0x039E, 0x039F, 0x03A0,
+ 0x03A1, 0x03A3, 0x03A4, 0x03A5, 0x03A6, 0x03A7, 0x03A8, 0x03A9, 0x03B1, 0x03B2, 0x03B3, 0x03B4, 0x03B5, 0x03B6, 0x03B7, 0x03B8,
+ 0x03B9, 0x03BA, 0x03BB, 0x03BC, 0x03BD, 0x03BE, 0x03BF, 0x03C0, 0x03C1, 0x03C3, 0x03C2, 0x03C4, 0x03C5, 0x03C6, 0x03C7, 0x03C8,
+ 0x2591, 0x2592, 0x2593, 0x2502, 0x2524, 0x2561, 0x2562, 0x2556, 0x2555, 0x2563, 0x2551, 0x2557, 0x255D, 0x255C, 0x255B, 0x2510,
+ 0x2514, 0x2534, 0x252C, 0x251C, 0x2500, 0x253C, 0x255E, 0x255F, 0x255A, 0x2554, 0x2569, 0x2566, 0x2560, 0x2550, 0x256C, 0x2567,
+ 0x2568, 0x2564, 0x2565, 0x2559, 0x2558, 0x2552, 0x2553, 0x256B, 0x256A, 0x2518, 0x250C, 0x2588, 0x2584, 0x258C, 0x2590, 0x2580,
+ 0x03C9, 0x03AC, 0x03AD, 0x03AE, 0x03CA, 0x03AF, 0x03CC, 0x03CD, 0x03CB, 0x03CE, 0x0386, 0x0388, 0x0389, 0x038A, 0x038C, 0x038E,
+ 0x038F, 0x00B1, 0x2265, 0x2264, 0x03AA, 0x03AB, 0x00F7, 0x2248, 0x00B0, 0x2219, 0x00B7, 0x221A, 0x207F, 0x00B2, 0x25A0, 0x00A0
+};
+#endif
+#if FF_CODE_PAGE == 771 || FF_CODE_PAGE == 0
+static const WCHAR uc771[] = { /* CP771(KBL) to Unicode conversion table */
+ 0x0410, 0x0411, 0x0412, 0x0413, 0x0414, 0x0415, 0x0416, 0x0417, 0x0418, 0x0419, 0x041A, 0x041B, 0x041C, 0x041D, 0x041E, 0x041F,
+ 0x0420, 0x0421, 0x0422, 0x0423, 0x0424, 0x0425, 0x0426, 0x0427, 0x0428, 0x0429, 0x042A, 0x042B, 0x042C, 0x042D, 0x042E, 0x042F,
+ 0x0430, 0x0431, 0x0432, 0x0433, 0x0434, 0x0435, 0x0436, 0x0437, 0x0438, 0x0439, 0x043A, 0x043B, 0x043C, 0x043D, 0x043E, 0x043F,
+ 0x2591, 0x2592, 0x2593, 0x2502, 0x2524, 0x2561, 0x2562, 0x2556, 0x2555, 0x2563, 0x2551, 0x2557, 0x255D, 0x255C, 0x2558, 0x2510,
+ 0x2514, 0x2534, 0x252C, 0x251C, 0x2500, 0x253C, 0x255E, 0x255F, 0x255A, 0x2554, 0x2569, 0x2566, 0x2560, 0x2550, 0x256C, 0x2567,
+ 0x2568, 0x2564, 0x2565, 0x2559, 0x2558, 0x2552, 0x2553, 0x256B, 0x256A, 0x2518, 0x250C, 0x2588, 0x0104, 0x0105, 0x010C, 0x010D,
+ 0x0440, 0x0441, 0x0442, 0x0443, 0x0444, 0x0445, 0x0446, 0x0447, 0x0448, 0x0449, 0x044A, 0x044B, 0x044C, 0x044D, 0x044E, 0x044F,
+ 0x0118, 0x0119, 0x0116, 0x0117, 0x012E, 0x012F, 0x0160, 0x0161, 0x0172, 0x0173, 0x016A, 0x016B, 0x017D, 0x017E, 0x25A0, 0x00A0
+};
+#endif
+#if FF_CODE_PAGE == 775 || FF_CODE_PAGE == 0
+static const WCHAR uc775[] = { /* CP775(Baltic) to Unicode conversion table */
+ 0x0106, 0x00FC, 0x00E9, 0x0101, 0x00E4, 0x0123, 0x00E5, 0x0107, 0x0142, 0x0113, 0x0156, 0x0157, 0x012B, 0x0179, 0x00C4, 0x00C5,
+ 0x00C9, 0x00E6, 0x00C6, 0x014D, 0x00F6, 0x0122, 0x00A2, 0x015A, 0x015B, 0x00D6, 0x00DC, 0x00F8, 0x00A3, 0x00D8, 0x00D7, 0x00A4,
+ 0x0100, 0x012A, 0x00F3, 0x017B, 0x017C, 0x017A, 0x201D, 0x00A6, 0x00A9, 0x00AE, 0x00AC, 0x00BD, 0x00BC, 0x0141, 0x00AB, 0x00BB,
+ 0x2591, 0x2592, 0x2593, 0x2502, 0x2524, 0x0104, 0x010C, 0x0118, 0x0116, 0x2563, 0x2551, 0x2557, 0x255D, 0x012E, 0x0160, 0x2510,
+ 0x2514, 0x2534, 0x252C, 0x251C, 0x2500, 0x253C, 0x0172, 0x016A, 0x255A, 0x2554, 0x2569, 0x2566, 0x2560, 0x2550, 0x256C, 0x017D,
+ 0x0105, 0x010D, 0x0119, 0x0117, 0x012F, 0x0161, 0x0173, 0x016B, 0x017E, 0x2518, 0x250C, 0x2588, 0x2584, 0x258C, 0x2590, 0x2580,
+ 0x00D3, 0x00DF, 0x014C, 0x0143, 0x00F5, 0x00D5, 0x00B5, 0x0144, 0x0136, 0x0137, 0x013B, 0x013C, 0x0146, 0x0112, 0x0145, 0x2019,
+ 0x00AD, 0x00B1, 0x201C, 0x00BE, 0x00B6, 0x00A7, 0x00F7, 0x201E, 0x00B0, 0x2219, 0x00B7, 0x00B9, 0x00B3, 0x00B2, 0x25A0, 0x00A0
+};
+#endif
+#if FF_CODE_PAGE == 850 || FF_CODE_PAGE == 0
+static const WCHAR uc850[] = { /* CP850(Latin 1) to Unicode conversion table */
+ 0x00C7, 0x00FC, 0x00E9, 0x00E2, 0x00E4, 0x00E0, 0x00E5, 0x00E7, 0x00EA, 0x00EB, 0x00E8, 0x00EF, 0x00EE, 0x00EC, 0x00C4, 0x00C5,
+ 0x00C9, 0x00E6, 0x00C6, 0x00F4, 0x00F6, 0x00F2, 0x00FB, 0x00F9, 0x00FF, 0x00D6, 0x00DC, 0x00F8, 0x00A3, 0x00D8, 0x00D7, 0x0192,
+ 0x00E1, 0x00ED, 0x00F3, 0x00FA, 0x00F1, 0x00D1, 0x00AA, 0x00BA, 0x00BF, 0x00AE, 0x00AC, 0x00BD, 0x00BC, 0x00A1, 0x00AB, 0x00BB,
+ 0x2591, 0x2592, 0x2593, 0x2502, 0x2524, 0x00C1, 0x00C2, 0x00C0, 0x00A9, 0x2563, 0x2551, 0x2557, 0x255D, 0x00A2, 0x00A5, 0x2510,
+ 0x2514, 0x2534, 0x252C, 0x251C, 0x2500, 0x253C, 0x00E3, 0x00C3, 0x255A, 0x2554, 0x2569, 0x2566, 0x2560, 0x2550, 0x256C, 0x00A4,
+ 0x00F0, 0x00D0, 0x00CA, 0x00CB, 0x00C8, 0x0131, 0x00CD, 0x00CE, 0x00CF, 0x2518, 0x250C, 0x2588, 0x2584, 0x00A6, 0x00CC, 0x2580,
+ 0x00D3, 0x00DF, 0x00D4, 0x00D2, 0x00F5, 0x00D5, 0x00B5, 0x00FE, 0x00DE, 0x00DA, 0x00DB, 0x00D9, 0x00FD, 0x00DD, 0x00AF, 0x00B4,
+ 0x00AD, 0x00B1, 0x2017, 0x00BE, 0x00B6, 0x00A7, 0x00F7, 0x00B8, 0x00B0, 0x00A8, 0x00B7, 0x00B9, 0x00B3, 0x00B2, 0x25A0, 0x00A0
+};
+#endif
+#if FF_CODE_PAGE == 852 || FF_CODE_PAGE == 0
+static const WCHAR uc852[] = { /* CP852(Latin 2) to Unicode conversion table */
+ 0x00C7, 0x00FC, 0x00E9, 0x00E2, 0x00E4, 0x016F, 0x0107, 0x00E7, 0x0142, 0x00EB, 0x0150, 0x0151, 0x00EE, 0x0179, 0x00C4, 0x0106,
+ 0x00C9, 0x0139, 0x013A, 0x00F4, 0x00F6, 0x013D, 0x013E, 0x015A, 0x015B, 0x00D6, 0x00DC, 0x0164, 0x0165, 0x0141, 0x00D7, 0x010D,
+ 0x00E1, 0x00ED, 0x00F3, 0x00FA, 0x0104, 0x0105, 0x017D, 0x017E, 0x0118, 0x0119, 0x00AC, 0x017A, 0x010C, 0x015F, 0x00AB, 0x00BB,
+ 0x2591, 0x2592, 0x2593, 0x2502, 0x2524, 0x00C1, 0x00C2, 0x011A, 0x015E, 0x2563, 0x2551, 0x2557, 0x255D, 0x017B, 0x017C, 0x2510,
+ 0x2514, 0x2534, 0x252C, 0x251C, 0x2500, 0x253C, 0x0102, 0x0103, 0x255A, 0x2554, 0x2569, 0x2566, 0x2560, 0x2550, 0x256C, 0x00A4,
+ 0x0111, 0x0110, 0x010E, 0x00CB, 0x010F, 0x0147, 0x00CD, 0x00CE, 0x011B, 0x2518, 0x250C, 0x2588, 0x2584, 0x0162, 0x016E, 0x2580,
+ 0x00D3, 0x00DF, 0x00D4, 0x0143, 0x0144, 0x0148, 0x0160, 0x0161, 0x0154, 0x00DA, 0x0155, 0x0170, 0x00FD, 0x00DD, 0x0163, 0x00B4,
+ 0x00AD, 0x02DD, 0x02DB, 0x02C7, 0x02D8, 0x00A7, 0x00F7, 0x00B8, 0x00B0, 0x00A8, 0x02D9, 0x0171, 0x0158, 0x0159, 0x25A0, 0x00A0
+};
+#endif
+#if FF_CODE_PAGE == 855 || FF_CODE_PAGE == 0
+static const WCHAR uc855[] = { /* CP855(Cyrillic) to Unicode conversion table */
+ 0x0452, 0x0402, 0x0453, 0x0403, 0x0451, 0x0401, 0x0454, 0x0404, 0x0455, 0x0405, 0x0456, 0x0406, 0x0457, 0x0407, 0x0458, 0x0408,
+ 0x0459, 0x0409, 0x045A, 0x040A, 0x045B, 0x040B, 0x045C, 0x040C, 0x045E, 0x040E, 0x045F, 0x040F, 0x044E, 0x042E, 0x044A, 0x042A,
+ 0x0430, 0x0410, 0x0431, 0x0411, 0x0446, 0x0426, 0x0434, 0x0414, 0x0435, 0x0415, 0x0444, 0x0424, 0x0433, 0x0413, 0x00AB, 0x00BB,
+ 0x2591, 0x2592, 0x2593, 0x2502, 0x2524, 0x0445, 0x0425, 0x0438, 0x0418, 0x2563, 0x2551, 0x2557, 0x255D, 0x0439, 0x0419, 0x2510,
+ 0x2514, 0x2534, 0x252C, 0x251C, 0x2500, 0x253C, 0x043A, 0x041A, 0x255A, 0x2554, 0x2569, 0x2566, 0x2560, 0x2550, 0x256C, 0x00A4,
+ 0x043B, 0x041B, 0x043C, 0x041C, 0x043D, 0x041D, 0x043E, 0x041E, 0x043F, 0x2518, 0x250C, 0x2588, 0x2584, 0x041F, 0x044F, 0x2580,
+ 0x042F, 0x0440, 0x0420, 0x0441, 0x0421, 0x0442, 0x0422, 0x0443, 0x0423, 0x0436, 0x0416, 0x0432, 0x0412, 0x044C, 0x042C, 0x2116,
+ 0x00AD, 0x044B, 0x042B, 0x0437, 0x0417, 0x0448, 0x0428, 0x044D, 0x042D, 0x0449, 0x0429, 0x0447, 0x0427, 0x00A7, 0x25A0, 0x00A0
+};
+#endif
+#if FF_CODE_PAGE == 857 || FF_CODE_PAGE == 0
+static const WCHAR uc857[] = { /* CP857(Turkish) to Unicode conversion table */
+ 0x00C7, 0x00FC, 0x00E9, 0x00E2, 0x00E4, 0x00E0, 0x00E5, 0x00E7, 0x00EA, 0x00EB, 0x00E8, 0x00EF, 0x00EE, 0x0131, 0x00C4, 0x00C5,
+ 0x00C9, 0x00E6, 0x00C6, 0x00F4, 0x00F6, 0x00F2, 0x00FB, 0x00F9, 0x0130, 0x00D6, 0x00DC, 0x00F8, 0x00A3, 0x00D8, 0x015E, 0x015F,
+ 0x00E1, 0x00ED, 0x00F3, 0x00FA, 0x00F1, 0x00D1, 0x011E, 0x011F, 0x00BF, 0x00AE, 0x00AC, 0x00BD, 0x00BC, 0x00A1, 0x00AB, 0x00BB,
+ 0x2591, 0x2592, 0x2593, 0x2502, 0x2524, 0x00C1, 0x00C2, 0x00C0, 0x00A9, 0x2563, 0x2551, 0x2557, 0x255D, 0x00A2, 0x00A5, 0x2510,
+ 0x2514, 0x2534, 0x252C, 0x251C, 0x2500, 0x253C, 0x00E3, 0x00C3, 0x255A, 0x2554, 0x2569, 0x2566, 0x2560, 0x2550, 0x256C, 0x00A4,
+ 0x00BA, 0x00AA, 0x00CA, 0x00CB, 0x00C8, 0x0000, 0x00CD, 0x00CE, 0x00CF, 0x2518, 0x250C, 0x2588, 0x2584, 0x00A6, 0x00CC, 0x2580,
+ 0x00D3, 0x00DF, 0x00D4, 0x00D2, 0x00F5, 0x00D5, 0x00B5, 0x0000, 0x00D7, 0x00DA, 0x00DB, 0x00D9, 0x00EC, 0x00FF, 0x00AF, 0x00B4,
+ 0x00AD, 0x00B1, 0x0000, 0x00BE, 0x00B6, 0x00A7, 0x00F7, 0x00B8, 0x00B0, 0x00A8, 0x00B7, 0x00B9, 0x00B3, 0x00B2, 0x25A0, 0x00A0
+};
+#endif
+#if FF_CODE_PAGE == 860 || FF_CODE_PAGE == 0
+static const WCHAR uc860[] = { /* CP860(Portuguese) to Unicode conversion table */
+ 0x00C7, 0x00FC, 0x00E9, 0x00E2, 0x00E3, 0x00E0, 0x00C1, 0x00E7, 0x00EA, 0x00CA, 0x00E8, 0x00CD, 0x00D4, 0x00EC, 0x00C3, 0x00C2,
+ 0x00C9, 0x00C0, 0x00C8, 0x00F4, 0x00F5, 0x00F2, 0x00DA, 0x00F9, 0x00CC, 0x00D5, 0x00DC, 0x00A2, 0x00A3, 0x00D9, 0x20A7, 0x00D3,
+ 0x00E1, 0x00ED, 0x00F3, 0x00FA, 0x00F1, 0x00D1, 0x00AA, 0x00BA, 0x00BF, 0x00D2, 0x00AC, 0x00BD, 0x00BC, 0x00A1, 0x00AB, 0x00BB,
+ 0x2591, 0x2592, 0x2593, 0x2502, 0x2524, 0x2561, 0x2562, 0x2556, 0x2555, 0x2563, 0x2551, 0x2557, 0x255D, 0x255C, 0x2558, 0x2510,
+ 0x2514, 0x2534, 0x252C, 0x251C, 0x2500, 0x253C, 0x255E, 0x255F, 0x255A, 0x2554, 0x2569, 0x2566, 0x2560, 0x2550, 0x256C, 0x2567,
+ 0x2568, 0x2564, 0x2565, 0x2559, 0x2558, 0x2552, 0x2553, 0x256B, 0x256A, 0x2518, 0x250C, 0x2588, 0x2584, 0x258C, 0x2590, 0x2580,
+ 0x03B1, 0x00DF, 0x0393, 0x03C0, 0x03A3, 0x03C3, 0x00B5, 0x03C4, 0x03A6, 0x0398, 0x03A9, 0x03B4, 0x221E, 0x03C6, 0x03B5, 0x2229,
+ 0x2261, 0x00B1, 0x2265, 0x2264, 0x2320, 0x2321, 0x00F7, 0x2248, 0x00B0, 0x2219, 0x00B7, 0x221A, 0x207F, 0x00B2, 0x25A0, 0x00A0
+};
+#endif
+#if FF_CODE_PAGE == 861 || FF_CODE_PAGE == 0
+static const WCHAR uc861[] = { /* CP861(Icelandic) to Unicode conversion table */
+ 0x00C7, 0x00FC, 0x00E9, 0x00E2, 0x00E4, 0x00E0, 0x00E6, 0x00E7, 0x00EA, 0x00EB, 0x00E8, 0x00D0, 0x00F0, 0x00DE, 0x00C4, 0x00C5,
+ 0x00C9, 0x00E6, 0x00C6, 0x00F4, 0x00F6, 0x00FE, 0x00FB, 0x00DD, 0x00FD, 0x00D6, 0x00DC, 0x00F8, 0x00A3, 0x00D8, 0x20A7, 0x0192,
+ 0x00E1, 0x00ED, 0x00F3, 0x00FA, 0x00C1, 0x00CD, 0x00D3, 0x00DA, 0x00BF, 0x2310, 0x00AC, 0x00BD, 0x00BC, 0x00A1, 0x00AB, 0x00BB,
+ 0x2591, 0x2592, 0x2593, 0x2502, 0x2524, 0x2561, 0x2562, 0x2556, 0x2555, 0x2563, 0x2551, 0x2557, 0x255D, 0x255C, 0x255B, 0x2510,
+ 0x2514, 0x2534, 0x252C, 0x251C, 0x2500, 0x253C, 0x255E, 0x255F, 0x255A, 0x2554, 0x2569, 0x2566, 0x2560, 0x2550, 0x256C, 0x2567,
+ 0x2568, 0x2564, 0x2565, 0x2559, 0x2558, 0x2552, 0x2553, 0x256B, 0x256A, 0x2518, 0x250C, 0x2588, 0x2584, 0x258C, 0x2590, 0x2580,
+ 0x03B1, 0x00DF, 0x0393, 0x03C0, 0x03A3, 0x03C3, 0x00B5, 0x03C4, 0x03A6, 0x0398, 0x03A9, 0x03B4, 0x221E, 0x03C6, 0x03B5, 0x2229,
+ 0x2261, 0x00B1, 0x2265, 0x2264, 0x2320, 0x2321, 0x00F7, 0x2248, 0x00B0, 0x2219, 0x00B7, 0x221A, 0x207F, 0x00B2, 0x25A0, 0x00A0
+};
+#endif
+#if FF_CODE_PAGE == 862 || FF_CODE_PAGE == 0
+static const WCHAR uc862[] = { /* CP862(Hebrew) to Unicode conversion table */
+ 0x05D0, 0x05D1, 0x05D2, 0x05D3, 0x05D4, 0x05D5, 0x05D6, 0x05D7, 0x05D8, 0x05D9, 0x05DA, 0x05DB, 0x05DC, 0x05DD, 0x05DE, 0x05DF,
+ 0x05E0, 0x05E1, 0x05E2, 0x05E3, 0x05E4, 0x05E5, 0x05E6, 0x05E7, 0x05E8, 0x05E9, 0x05EA, 0x00A2, 0x00A3, 0x00A5, 0x20A7, 0x0192,
+ 0x00E1, 0x00ED, 0x00F3, 0x00FA, 0x00F1, 0x00D1, 0x00AA, 0x00BA, 0x00BF, 0x2310, 0x00AC, 0x00BD, 0x00BC, 0x00A1, 0x00AB, 0x00BB,
+ 0x2591, 0x2592, 0x2593, 0x2502, 0x2524, 0x2561, 0x2562, 0x2556, 0x2555, 0x2563, 0x2551, 0x2557, 0x255D, 0x255C, 0x255B, 0x2510,
+ 0x2514, 0x2534, 0x252C, 0x251C, 0x2500, 0x253C, 0x255E, 0x255F, 0x255A, 0x2554, 0x2569, 0x2566, 0x2560, 0x2550, 0x256C, 0x2567,
+ 0x2568, 0x2564, 0x2565, 0x2559, 0x2558, 0x2552, 0x2553, 0x256B, 0x256A, 0x2518, 0x250C, 0x2588, 0x2584, 0x258C, 0x2590, 0x2580,
+ 0x03B1, 0x00DF, 0x0393, 0x03C0, 0x03A3, 0x03C3, 0x00B5, 0x03C4, 0x03A6, 0x0398, 0x03A9, 0x03B4, 0x221E, 0x03C6, 0x03B5, 0x2229,
+ 0x2261, 0x00B1, 0x2265, 0x2264, 0x2320, 0x2321, 0x00F7, 0x2248, 0x00B0, 0x2219, 0x00B7, 0x221A, 0x207F, 0x00B2, 0x25A0, 0x00A0
+};
+#endif
+#if FF_CODE_PAGE == 863 || FF_CODE_PAGE == 0
+static const WCHAR uc863[] = { /* CP863(Canadian French) to Unicode conversion table */
+ 0x00C7, 0x00FC, 0x00E9, 0x00E2, 0x00C2, 0x00E0, 0x00B6, 0x00E7, 0x00EA, 0x00EB, 0x00E8, 0x00EF, 0x00EE, 0x00EC, 0x2017, 0x00C0,
+ 0x00C9, 0x00C8, 0x00CA, 0x00F4, 0x00CB, 0x00CF, 0x00FB, 0x00F9, 0x00A4, 0x00D4, 0x00DC, 0x00A2, 0x00A3, 0x00D9, 0x00DB, 0x0192,
+ 0x00A6, 0x00B4, 0x00F3, 0x00FA, 0x00A8, 0x00BB, 0x00B3, 0x00AF, 0x00CE, 0x3210, 0x00AC, 0x00BD, 0x00BC, 0x00BE, 0x00AB, 0x00BB,
+ 0x2591, 0x2592, 0x2593, 0x2502, 0x2524, 0x2561, 0x2562, 0x2556, 0x2555, 0x2563, 0x2551, 0x2557, 0x255D, 0x255C, 0x255B, 0x2510,
+ 0x2514, 0x2534, 0x252C, 0x251C, 0x2500, 0x253C, 0x255E, 0x255F, 0x255A, 0x2554, 0x2569, 0x2566, 0x2560, 0x2550, 0x256C, 0x2567,
+ 0x2568, 0x2564, 0x2565, 0x2559, 0x2558, 0x2552, 0x2553, 0x256B, 0x256A, 0x2518, 0x250C, 0x2588, 0x2584, 0x258C, 0x2590, 0x2580,
+ 0x03B1, 0x00DF, 0x0393, 0x03C0, 0x03A3, 0x03C3, 0x00B5, 0x03C4, 0x03A6, 0x0398, 0x03A9, 0x03B4, 0x221E, 0x03C6, 0x03B5, 0x2219,
+ 0x2261, 0x00B1, 0x2265, 0x2264, 0x2320, 0x2321, 0x00F7, 0x2248, 0x00B0, 0x2219, 0x00B7, 0x221A, 0x207F, 0x00B2, 0x25A0, 0x00A0
+};
+#endif
+#if FF_CODE_PAGE == 864 || FF_CODE_PAGE == 0
+static const WCHAR uc864[] = { /* CP864(Arabic) to Unicode conversion table */
+ 0x00B0, 0x00B7, 0x2219, 0x221A, 0x2592, 0x2500, 0x2502, 0x253C, 0x2524, 0x252C, 0x251C, 0x2534, 0x2510, 0x250C, 0x2514, 0x2518,
+ 0x03B2, 0x221E, 0x03C6, 0x00B1, 0x00BD, 0x00BC, 0x2248, 0x00AB, 0x00BB, 0xFEF7, 0xFEF8, 0x0000, 0x0000, 0xFEFB, 0xFEFC, 0x0000,
+ 0x00A0, 0x00AD, 0xFE82, 0x00A3, 0x00A4, 0xFE84, 0x0000, 0x20AC, 0xFE8E, 0xFE8F, 0xFE95, 0xFE99, 0x060C, 0xFE9D, 0xFEA1, 0xFEA5,
+ 0x0660, 0x0661, 0x0662, 0x0663, 0x0664, 0x0665, 0x0666, 0x0667, 0x0668, 0x0669, 0xFED1, 0x061B, 0xFEB1, 0xFEB5, 0xFEB9, 0x061F,
+ 0x00A2, 0xFE80, 0xFE81, 0xFE83, 0xFE85, 0xFECA, 0xFE8B, 0xFE8D, 0xFE91, 0xFE93, 0xFE97, 0xFE9B, 0xFE9F, 0xFEA3, 0xFEA7, 0xFEA9,
+ 0xFEAB, 0xFEAD, 0xFEAF, 0xFEB3, 0xFEB7, 0xFEBB, 0xFEBF, 0xFEC1, 0xFEC5, 0xFECB, 0xFECF, 0x00A6, 0x00AC, 0x00F7, 0x00D7, 0xFEC9,
+ 0x0640, 0xFED3, 0xFED7, 0xFEDB, 0xFEDF, 0xFEE3, 0xFEE7, 0xFEEB, 0xFEED, 0xFEEF, 0xFEF3, 0xFEBD, 0xFECC, 0xFECE, 0xFECD, 0xFEE1,
+ 0xFE7D, 0x0651, 0xFEE5, 0xFEE9, 0xFEEC, 0xFEF0, 0xFEF2, 0xFED0, 0xFED5, 0xFEF5, 0xFEF6, 0xFEDD, 0xFED9, 0xFEF1, 0x25A0, 0x0000
+};
+#endif
+#if FF_CODE_PAGE == 865 || FF_CODE_PAGE == 0
+static const WCHAR uc865[] = { /* CP865(Nordic) to Unicode conversion table */
+ 0x00C7, 0x00FC, 0x00E9, 0x00E2, 0x00E4, 0x00E0, 0x00E5, 0x00E7, 0x00EA, 0x00EB, 0x00E8, 0x00EF, 0x00EE, 0x00EC, 0x00C4, 0x00C5,
+ 0x00C5, 0x00E6, 0x00C6, 0x00F4, 0x00F6, 0x00F2, 0x00FB, 0x00F9, 0x00FF, 0x00D6, 0x00DC, 0x00F8, 0x00A3, 0x00D8, 0x20A7, 0x0192,
+ 0x00E1, 0x00ED, 0x00F3, 0x00FA, 0x00F1, 0x00D1, 0x00AA, 0x00BA, 0x00BF, 0x2310, 0x00AC, 0x00BD, 0x00BC, 0x00A1, 0x00AB, 0x00A4,
+ 0x2591, 0x2592, 0x2593, 0x2502, 0x2524, 0x2561, 0x2562, 0x2556, 0x2555, 0x2563, 0x2551, 0x2557, 0x255D, 0x255C, 0x2558, 0x2510,
+ 0x2514, 0x2534, 0x252C, 0x251C, 0x2500, 0x253C, 0x255E, 0x255F, 0x255A, 0x2554, 0x2569, 0x2566, 0x2560, 0x2550, 0x256C, 0x2567,
+ 0x2568, 0x2564, 0x2565, 0x2559, 0x2558, 0x2552, 0x2553, 0x256B, 0x256A, 0x2518, 0x250C, 0x2588, 0x2584, 0x258C, 0x2590, 0x2580,
+ 0x03B1, 0x00DF, 0x0393, 0x03C0, 0x03A3, 0x03C3, 0x00B5, 0x03C4, 0x03A6, 0x0398, 0x03A9, 0x03B4, 0x221E, 0x03C6, 0x03B5, 0x2229,
+ 0x2261, 0x00B1, 0x2265, 0x2264, 0x2320, 0x2321, 0x00F7, 0x2248, 0x00B0, 0x2219, 0x00B7, 0x221A, 0x207F, 0x00B2, 0x25A0, 0x00A0
+};
+#endif
+#if FF_CODE_PAGE == 866 || FF_CODE_PAGE == 0
+static const WCHAR uc866[] = { /* CP866(Russian) to Unicode conversion table */
+ 0x0410, 0x0411, 0x0412, 0x0413, 0x0414, 0x0415, 0x0416, 0x0417, 0x0418, 0x0419, 0x041A, 0x041B, 0x041C, 0x041D, 0x041E, 0x041F,
+ 0x0420, 0x0421, 0x0422, 0x0423, 0x0424, 0x0425, 0x0426, 0x0427, 0x0428, 0x0429, 0x042A, 0x042B, 0x042C, 0x042D, 0x042E, 0x042F,
+ 0x0430, 0x0431, 0x0432, 0x0433, 0x0434, 0x0435, 0x0436, 0x0437, 0x0438, 0x0439, 0x043A, 0x043B, 0x043C, 0x043D, 0x043E, 0x043F,
+ 0x2591, 0x2592, 0x2593, 0x2502, 0x2524, 0x2561, 0x2562, 0x2556, 0x2555, 0x2563, 0x2551, 0x2557, 0x255D, 0x255C, 0x255B, 0x2510,
+ 0x2514, 0x2534, 0x252C, 0x251C, 0x2500, 0x253C, 0x255E, 0x255F, 0x255A, 0x2554, 0x2569, 0x2566, 0x2560, 0x2550, 0x256C, 0x2567,
+ 0x2568, 0x2564, 0x2565, 0x2559, 0x2558, 0x2552, 0x2553, 0x256B, 0x256A, 0x2518, 0x250C, 0x2588, 0x2584, 0x258C, 0x2590, 0x2580,
+ 0x0440, 0x0441, 0x0442, 0x0443, 0x0444, 0x0445, 0x0446, 0x0447, 0x0448, 0x0449, 0x044A, 0x044B, 0x044C, 0x044D, 0x044E, 0x044F,
+ 0x0401, 0x0451, 0x0404, 0x0454, 0x0407, 0x0457, 0x040E, 0x045E, 0x00B0, 0x2219, 0x00B7, 0x221A, 0x2116, 0x00A4, 0x25A0, 0x00A0
+};
+#endif
+#if FF_CODE_PAGE == 869 || FF_CODE_PAGE == 0
+static const WCHAR uc869[] = { /* CP869(Greek 2) to Unicode conversion table */
+ 0x00B7, 0x00B7, 0x00B7, 0x00B7, 0x00B7, 0x00B7, 0x0386, 0x00B7, 0x00B7, 0x00AC, 0x00A6, 0x2018, 0x2019, 0x0388, 0x2015, 0x0389,
+ 0x038A, 0x03AA, 0x038C, 0x00B7, 0x00B7, 0x038E, 0x03AB, 0x00A9, 0x038F, 0x00B2, 0x00B3, 0x03AC, 0x00A3, 0x03AD, 0x03AE, 0x03AF,
+ 0x03CA, 0x0390, 0x03CC, 0x03CD, 0x0391, 0x0392, 0x0393, 0x0394, 0x0395, 0x0396, 0x0397, 0x00BD, 0x0398, 0x0399, 0x00AB, 0x00BB,
+ 0x2591, 0x2592, 0x2593, 0x2502, 0x2524, 0x039A, 0x039B, 0x039C, 0x039D, 0x2563, 0x2551, 0x2557, 0x255D, 0x039E, 0x039F, 0x2510,
+ 0x2514, 0x2534, 0x252C, 0x251C, 0x2500, 0x253C, 0x0A30, 0x03A1, 0x255A, 0x2554, 0x2569, 0x2566, 0x2560, 0x2550, 0x256C, 0x03A3,
+ 0x03A4, 0x03A5, 0x03A6, 0x03A7, 0x03A8, 0x03A9, 0x03B1, 0x03B2, 0x03B3, 0x2518, 0x250C, 0x2588, 0x2584, 0x03B4, 0x03B5, 0x2580,
+ 0x03B6, 0x03B7, 0x03B8, 0x03B9, 0x03BA, 0x03BB, 0x03BC, 0x03BD, 0x03BE, 0x03BF, 0x03C0, 0x03C1, 0x03C3, 0x03C2, 0x03C4, 0x0384,
+ 0x00AD, 0x00B1, 0x03C5, 0x03C6, 0x03C7, 0x00A7, 0x03C8, 0x0385, 0x00B0, 0x00A8, 0x03C9, 0x03CB, 0x03B0, 0x03CE, 0x25A0, 0x00A0
+};
+#endif
+
+
+
+
+/*------------------------------------------------------------------------*/
+/* OEM <==> Unicode conversions for static code page configuration */
+/* SBCS fixed code page */
+/*------------------------------------------------------------------------*/
+
+#if FF_CODE_PAGE != 0 && FF_CODE_PAGE < 900
+WCHAR ff_uni2oem ( /* Returns OEM code character, zero on error */
+ DWORD uni, /* UTF-16 encoded character to be converted */
+ WORD cp /* Code page for the conversion */
+)
+{
+ WCHAR c = 0;
+ const WCHAR *p = CVTBL(uc, FF_CODE_PAGE);
+
+
+ if (uni < 0x80) { /* ASCII? */
+ c = (WCHAR)uni;
+
+ } else { /* Non-ASCII */
+ if (uni < 0x10000 && cp == FF_CODE_PAGE) { /* Is it in BMP and valid code page? */
+ for (c = 0; c < 0x80 && uni != p[c]; c++) ;
+ c = (c + 0x80) & 0xFF;
+ }
+ }
+
+ return c;
+}
+
+WCHAR ff_oem2uni ( /* Returns Unicode character, zero on error */
+ WCHAR oem, /* OEM code to be converted */
+ WORD cp /* Code page for the conversion */
+)
+{
+ WCHAR c = 0;
+ const WCHAR *p = CVTBL(uc, FF_CODE_PAGE);
+
+
+ if (oem < 0x80) { /* ASCII? */
+ c = oem;
+
+ } else { /* Extended char */
+ if (cp == FF_CODE_PAGE) { /* Is it a valid code page? */
+ if (oem < 0x100) c = p[oem - 0x80];
+ }
+ }
+
+ return c;
+}
+
+#endif
+
+
+
+/*------------------------------------------------------------------------*/
+/* OEM <==> Unicode conversions for static code page configuration */
+/* DBCS fixed code page */
+/*------------------------------------------------------------------------*/
+
+#if FF_CODE_PAGE >= 900
+WCHAR ff_uni2oem ( /* Returns OEM code character, zero on error */
+ DWORD uni, /* UTF-16 encoded character to be converted */
+ WORD cp /* Code page for the conversion */
+)
+{
+ const WCHAR *p;
+ WCHAR c = 0, uc;
+ UINT i = 0, n, li, hi;
+
+
+ if (uni < 0x80) { /* ASCII? */
+ c = (WCHAR)uni;
+
+ } else { /* Non-ASCII */
+ if (uni < 0x10000 && cp == FF_CODE_PAGE) { /* Is it in BMP and valid code page? */
+ uc = (WCHAR)uni;
+ p = CVTBL(uni2oem, FF_CODE_PAGE);
+ hi = sizeof CVTBL(uni2oem, FF_CODE_PAGE) / 4 - 1;
+ li = 0;
+ for (n = 16; n; n--) {
+ i = li + (hi - li) / 2;
+ if (uc == p[i * 2]) break;
+ if (uc > p[i * 2]) {
+ li = i;
+ } else {
+ hi = i;
+ }
+ }
+ if (n != 0) c = p[i * 2 + 1];
+ }
+ }
+
+ return c;
+}
+
+
+WCHAR ff_oem2uni ( /* Returns Unicode character, zero on error */
+ WCHAR oem, /* OEM code to be converted */
+ WORD cp /* Code page for the conversion */
+)
+{
+ const WCHAR *p;
+ WCHAR c = 0;
+ UINT i = 0, n, li, hi;
+
+
+ if (oem < 0x80) { /* ASCII? */
+ c = oem;
+
+ } else { /* Extended char */
+ if (cp == FF_CODE_PAGE) { /* Is it valid code page? */
+ p = CVTBL(oem2uni, FF_CODE_PAGE);
+ hi = sizeof CVTBL(oem2uni, FF_CODE_PAGE) / 4 - 1;
+ li = 0;
+ for (n = 16; n; n--) {
+ i = li + (hi - li) / 2;
+ if (oem == p[i * 2]) break;
+ if (oem > p[i * 2]) {
+ li = i;
+ } else {
+ hi = i;
+ }
+ }
+ if (n != 0) c = p[i * 2 + 1];
+ }
+ }
+
+ return c;
+}
+#endif
+
+
+
+/*------------------------------------------------------------------------*/
+/* OEM <==> Unicode conversions for dynamic code page configuration */
+/*------------------------------------------------------------------------*/
+
+#if FF_CODE_PAGE == 0
+
+static const WORD cp_code[] = { 437, 720, 737, 771, 775, 850, 852, 855, 857, 860, 861, 862, 863, 864, 865, 866, 869, 0};
+static const WCHAR* const cp_table[] = {uc437, uc720, uc737, uc771, uc775, uc850, uc852, uc855, uc857, uc860, uc861, uc862, uc863, uc864, uc865, uc866, uc869, 0};
+
+
+WCHAR ff_uni2oem ( /* Returns OEM code character, zero on error */
+ DWORD uni, /* UTF-16 encoded character to be converted */
+ WORD cp /* Code page for the conversion */
+)
+{
+ const WCHAR *p;
+ WCHAR c = 0, uc;
+ UINT i, n, li, hi;
+
+
+ if (uni < 0x80) { /* ASCII? */
+ c = (WCHAR)uni;
+
+ } else { /* Non-ASCII */
+ if (uni < 0x10000) { /* Is it in BMP? */
+ uc = (WCHAR)uni;
+ p = 0;
+ if (cp < 900) { /* SBCS */
+ for (i = 0; cp_code[i] != 0 && cp_code[i] != cp; i++) ; /* Get conversion table */
+ p = cp_table[i];
+ if (p) { /* Is it valid code page ? */
+ for (c = 0; c < 0x80 && uc != p[c]; c++) ; /* Find OEM code in the table */
+ c = (c + 0x80) & 0xFF;
+ }
+ } else { /* DBCS */
+ switch (cp) { /* Get conversion table */
+ case 932 : p = uni2oem932; hi = sizeof uni2oem932 / 4 - 1; break;
+ case 936 : p = uni2oem936; hi = sizeof uni2oem936 / 4 - 1; break;
+ case 949 : p = uni2oem949; hi = sizeof uni2oem949 / 4 - 1; break;
+ case 950 : p = uni2oem950; hi = sizeof uni2oem950 / 4 - 1; break;
+ }
+ if (p) { /* Is it valid code page? */
+ li = 0;
+ for (n = 16; n; n--) { /* Find OEM code */
+ i = li + (hi - li) / 2;
+ if (uc == p[i * 2]) break;
+ if (uc > p[i * 2]) {
+ li = i;
+ } else {
+ hi = i;
+ }
+ }
+ if (n != 0) c = p[i * 2 + 1];
+ }
+ }
+ }
+ }
+
+ return c;
+}
+
+
+WCHAR ff_oem2uni ( /* Returns Unicode character, zero on error */
+ WCHAR oem, /* OEM code to be converted (DBC if >=0x100) */
+ WORD cp /* Code page for the conversion */
+)
+{
+ const WCHAR *p;
+ WCHAR c = 0;
+ UINT i, n, li, hi;
+
+
+ if (oem < 0x80) { /* ASCII? */
+ c = oem;
+
+ } else { /* Extended char */
+ p = 0;
+ if (cp < 900) { /* SBCS */
+ for (i = 0; cp_code[i] != 0 && cp_code[i] != cp; i++) ; /* Get table */
+ p = cp_table[i];
+ if (p) { /* Is it a valid CP ? */
+ if (oem < 0x100) c = p[oem - 0x80];
+ }
+ } else { /* DBCS */
+ switch (cp) {
+ case 932 : p = oem2uni932; hi = sizeof oem2uni932 / 4 - 1; break;
+ case 936 : p = oem2uni936; hi = sizeof oem2uni936 / 4 - 1; break;
+ case 949 : p = oem2uni949; hi = sizeof oem2uni949 / 4 - 1; break;
+ case 950 : p = oem2uni950; hi = sizeof oem2uni950 / 4 - 1; break;
+ }
+ if (p) {
+ li = 0;
+ for (n = 16; n; n--) {
+ i = li + (hi - li) / 2;
+ if (oem == p[i * 2]) break;
+ if (oem > p[i * 2]) {
+ li = i;
+ } else {
+ hi = i;
+ }
+ }
+ if (n != 0) c = p[i * 2 + 1];
+ }
+ }
+ }
+
+ return c;
+}
+#endif
+
+
+
+/*------------------------------------------------------------------------*/
+/* Unicode up-case conversion */
+/*------------------------------------------------------------------------*/
+
+DWORD ff_wtoupper ( /* Returns up-converted code point */
+ DWORD uni /* Unicode code point to be up-converted */
+)
+{
+ const WORD *p;
+ WORD uc, bc, nc, cmd;
+ static const WORD cvt1[] = { /* Compressed up conversion table for U+0000 - U+0FFF */
+ /* Basic Latin */
+ 0x0061,0x031A,
+ /* Latin-1 Supplement */
+ 0x00E0,0x0317,
+ 0x00F8,0x0307,
+ 0x00FF,0x0001,0x0178,
+ /* Latin Extended-A */
+ 0x0100,0x0130,
+ 0x0132,0x0106,
+ 0x0139,0x0110,
+ 0x014A,0x012E,
+ 0x0179,0x0106,
+ /* Latin Extended-B */
+ 0x0180,0x004D,0x0243,0x0181,0x0182,0x0182,0x0184,0x0184,0x0186,0x0187,0x0187,0x0189,0x018A,0x018B,0x018B,0x018D,0x018E,0x018F,0x0190,0x0191,0x0191,0x0193,0x0194,0x01F6,0x0196,0x0197,0x0198,0x0198,0x023D,0x019B,0x019C,0x019D,0x0220,0x019F,0x01A0,0x01A0,0x01A2,0x01A2,0x01A4,0x01A4,0x01A6,0x01A7,0x01A7,0x01A9,0x01AA,0x01AB,0x01AC,0x01AC,0x01AE,0x01AF,0x01AF,0x01B1,0x01B2,0x01B3,0x01B3,0x01B5,0x01B5,0x01B7,0x01B8,0x01B8,0x01BA,0x01BB,0x01BC,0x01BC,0x01BE,0x01F7,0x01C0,0x01C1,0x01C2,0x01C3,0x01C4,0x01C5,0x01C4,0x01C7,0x01C8,0x01C7,0x01CA,0x01CB,0x01CA,
+ 0x01CD,0x0110,
+ 0x01DD,0x0001,0x018E,
+ 0x01DE,0x0112,
+ 0x01F3,0x0003,0x01F1,0x01F4,0x01F4,
+ 0x01F8,0x0128,
+ 0x0222,0x0112,
+ 0x023A,0x0009,0x2C65,0x023B,0x023B,0x023D,0x2C66,0x023F,0x0240,0x0241,0x0241,
+ 0x0246,0x010A,
+ /* IPA Extensions */
+ 0x0253,0x0040,0x0181,0x0186,0x0255,0x0189,0x018A,0x0258,0x018F,0x025A,0x0190,0x025C,0x025D,0x025E,0x025F,0x0193,0x0261,0x0262,0x0194,0x0264,0x0265,0x0266,0x0267,0x0197,0x0196,0x026A,0x2C62,0x026C,0x026D,0x026E,0x019C,0x0270,0x0271,0x019D,0x0273,0x0274,0x019F,0x0276,0x0277,0x0278,0x0279,0x027A,0x027B,0x027C,0x2C64,0x027E,0x027F,0x01A6,0x0281,0x0282,0x01A9,0x0284,0x0285,0x0286,0x0287,0x01AE,0x0244,0x01B1,0x01B2,0x0245,0x028D,0x028E,0x028F,0x0290,0x0291,0x01B7,
+ /* Greek, Coptic */
+ 0x037B,0x0003,0x03FD,0x03FE,0x03FF,
+ 0x03AC,0x0004,0x0386,0x0388,0x0389,0x038A,
+ 0x03B1,0x0311,
+ 0x03C2,0x0002,0x03A3,0x03A3,
+ 0x03C4,0x0308,
+ 0x03CC,0x0003,0x038C,0x038E,0x038F,
+ 0x03D8,0x0118,
+ 0x03F2,0x000A,0x03F9,0x03F3,0x03F4,0x03F5,0x03F6,0x03F7,0x03F7,0x03F9,0x03FA,0x03FA,
+ /* Cyrillic */
+ 0x0430,0x0320,
+ 0x0450,0x0710,
+ 0x0460,0x0122,
+ 0x048A,0x0136,
+ 0x04C1,0x010E,
+ 0x04CF,0x0001,0x04C0,
+ 0x04D0,0x0144,
+ /* Armenian */
+ 0x0561,0x0426,
+
+ 0x0000 /* EOT */
+ };
+ static const WORD cvt2[] = { /* Compressed up conversion table for U+1000 - U+FFFF */
+ /* Phonetic Extensions */
+ 0x1D7D,0x0001,0x2C63,
+ /* Latin Extended Additional */
+ 0x1E00,0x0196,
+ 0x1EA0,0x015A,
+ /* Greek Extended */
+ 0x1F00,0x0608,
+ 0x1F10,0x0606,
+ 0x1F20,0x0608,
+ 0x1F30,0x0608,
+ 0x1F40,0x0606,
+ 0x1F51,0x0007,0x1F59,0x1F52,0x1F5B,0x1F54,0x1F5D,0x1F56,0x1F5F,
+ 0x1F60,0x0608,
+ 0x1F70,0x000E,0x1FBA,0x1FBB,0x1FC8,0x1FC9,0x1FCA,0x1FCB,0x1FDA,0x1FDB,0x1FF8,0x1FF9,0x1FEA,0x1FEB,0x1FFA,0x1FFB,
+ 0x1F80,0x0608,
+ 0x1F90,0x0608,
+ 0x1FA0,0x0608,
+ 0x1FB0,0x0004,0x1FB8,0x1FB9,0x1FB2,0x1FBC,
+ 0x1FCC,0x0001,0x1FC3,
+ 0x1FD0,0x0602,
+ 0x1FE0,0x0602,
+ 0x1FE5,0x0001,0x1FEC,
+ 0x1FF3,0x0001,0x1FFC,
+ /* Letterlike Symbols */
+ 0x214E,0x0001,0x2132,
+ /* Number forms */
+ 0x2170,0x0210,
+ 0x2184,0x0001,0x2183,
+ /* Enclosed Alphanumerics */
+ 0x24D0,0x051A,
+ 0x2C30,0x042F,
+ /* Latin Extended-C */
+ 0x2C60,0x0102,
+ 0x2C67,0x0106, 0x2C75,0x0102,
+ /* Coptic */
+ 0x2C80,0x0164,
+ /* Georgian Supplement */
+ 0x2D00,0x0826,
+ /* Full-width */
+ 0xFF41,0x031A,
+
+ 0x0000 /* EOT */
+ };
+
+
+ if (uni < 0x10000) { /* Is it in BMP? */
+ uc = (WORD)uni;
+ p = uc < 0x1000 ? cvt1 : cvt2;
+ for (;;) {
+ bc = *p++; /* Get the block base */
+ if (bc == 0 || uc < bc) break; /* Not matched? */
+ nc = *p++; cmd = nc >> 8; nc &= 0xFF; /* Get processing command and block size */
+ if (uc < bc + nc) { /* In the block? */
+ switch (cmd) {
+ case 0: uc = p[uc - bc]; break; /* Table conversion */
+ case 1: uc -= (uc - bc) & 1; break; /* Case pairs */
+ case 2: uc -= 16; break; /* Shift -16 */
+ case 3: uc -= 32; break; /* Shift -32 */
+ case 4: uc -= 48; break; /* Shift -48 */
+ case 5: uc -= 26; break; /* Shift -26 */
+ case 6: uc += 8; break; /* Shift +8 */
+ case 7: uc -= 80; break; /* Shift -80 */
+ case 8: uc -= 0x1C60; break; /* Shift -0x1C60 */
+ }
+ break;
+ }
+ if (cmd == 0) p += nc; /* Skip table if needed */
+ }
+ uni = uc;
+ }
+
+ return uni;
+}
+
+
+#endif /* #if FF_USE_LFN */
diff --git a/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/xilffs_v4_2/src/include/diskio.h b/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/xilffs_v4_2/src/include/diskio.h
new file mode 100644
index 0000000..edd697a
--- /dev/null
+++ b/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/xilffs_v4_2/src/include/diskio.h
@@ -0,0 +1,79 @@
+/*-----------------------------------------------------------------------/
+/ Low level disk interface module include file (C)ChaN, 2014 /
+/-----------------------------------------------------------------------*/
+
+#ifndef DISKIO_DEFINED
+#define DISKIO_DEFINED
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#define USE_WRITE 1 /* 1: Enable disk_write function */
+#define USE_IOCTL 1 /* 1: Enable disk_ioctl function */
+
+#include "integer.h"
+#include "xil_types.h"
+
+/* Status of Disk Functions */
+typedef BYTE DSTATUS;
+
+/* Results of Disk Functions */
+typedef enum {
+ RES_OK = 0, /* 0: Successful */
+ RES_ERROR, /* 1: R/W Error */
+ RES_WRPRT, /* 2: Write Protected */
+ RES_NOTRDY, /* 3: Not Ready */
+ RES_PARERR /* 4: Invalid Parameter */
+} DRESULT;
+
+
+/*---------------------------------------*/
+/* Prototypes for disk control functions */
+
+DSTATUS disk_initialize (BYTE pdrv);
+DSTATUS disk_status (BYTE pdrv);
+DRESULT disk_read (BYTE pdrv, BYTE* buff, DWORD sector, UINT count);
+DRESULT disk_write (BYTE pdrv, const BYTE* buff, DWORD sector, UINT count);
+DRESULT disk_ioctl (BYTE pdrv, BYTE cmd, void* buff);
+
+
+/* Disk Status Bits (DSTATUS) */
+
+#define STA_NOINIT 0x01U /* Drive not initialized */
+#define STA_NODISK 0x02U /* No medium in the drive */
+#define STA_PROTECT 0x04U /* Write protected */
+
+
+/* Command code for disk_ioctrl function */
+
+/* Generic command (used by FatFs) */
+#define CTRL_SYNC 0U /* Flush disk cache (for write functions) */
+#define GET_SECTOR_COUNT 1U /* Get media size (for only f_mkfs()) */
+#define GET_SECTOR_SIZE 2U /* Get sector size (for multiple sector size (_MAX_SS >= 1024)) */
+#define GET_BLOCK_SIZE 3U /* Get erase block size (for only f_mkfs()) */
+#define CTRL_ERASE_SECTOR 4U /* Force erased a block of sectors (for only _USE_ERASE) */
+
+/* Generic command (not used by FatFs) */
+#define CTRL_POWER 5U /* Get/Set power status */
+#define CTRL_LOCK 6U /* Lock/Unlock media removal */
+#define CTRL_EJECT 7U /* Eject media */
+#define CTRL_FORMAT 8U /* Create physical format on the media */
+
+/* MMC/SDC specific ioctl command */
+#define MMC_GET_TYPE 10U /* Get card type */
+#define MMC_GET_CSD 11U /* Get CSD */
+#define MMC_GET_CID 12U /* Get CID */
+#define MMC_GET_OCR 13U /* Get OCR */
+#define MMC_GET_SDSTAT 14U /* Get SD status */
+
+/* ATA/CF specific ioctl command */
+#define ATA_GET_REV 20U /* Get F/W revision */
+#define ATA_GET_MODEL 21U /* Get model name */
+#define ATA_GET_SN 22U /* Get serial number */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff --git a/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/xilffs_v4_2/src/include/ff.h b/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/xilffs_v4_2/src/include/ff.h
new file mode 100644
index 0000000..967451e
--- /dev/null
+++ b/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/xilffs_v4_2/src/include/ff.h
@@ -0,0 +1,395 @@
+/*----------------------------------------------------------------------------/
+/ FatFs - Generic FAT Filesystem module R0.13b /
+/-----------------------------------------------------------------------------/
+/
+/ Copyright (C) 2018, ChaN, all right reserved.
+/
+/ FatFs module is an open source software. Redistribution and use of FatFs in
+/ source and binary forms, with or without modification, are permitted provided
+/ that the following condition is met:
+
+/ 1. Redistributions of source code must retain the above copyright notice,
+/ this condition and the following disclaimer.
+/
+/ This software is provided by the copyright holder and contributors "AS IS"
+/ and any warranties related to this software are DISCLAIMED.
+/ The copyright owner or contributors be NOT LIABLE for any damages caused
+/ by use of this software.
+/
+/----------------------------------------------------------------------------*/
+
+
+#ifndef FF_DEFINED
+#define FF_DEFINED 63463 /* Revision ID */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include "xil_types.h"
+#include "integer.h" /* Basic integer types */
+#include "ffconf.h" /* FatFs configuration options */
+
+#if FF_DEFINED != FFCONF_DEF
+#error Wrong configuration file (ffconf.h).
+#endif
+
+
+
+/* Definitions of volume management */
+
+#if FF_MULTI_PARTITION /* Multiple partition configuration */
+typedef struct {
+ BYTE pd; /* Physical drive number */
+ BYTE pt; /* Partition: 0:Auto detect, 1-4:Forced partition) */
+} PARTITION;
+extern PARTITION VolToPart[]; /* Volume - Partition resolution table */
+#endif
+
+#if FF_STR_VOLUME_ID
+#ifndef FF_VOLUME_STRS
+extern const char* VolumeStr[FF_VOLUMES]; /* User defied volume ID */
+#endif
+#endif
+
+
+
+/* Type of path name strings on FatFs API */
+
+#ifndef _INC_TCHAR
+#define _INC_TCHAR
+
+#if FF_USE_LFN && FF_LFN_UNICODE == 1 /* Unicode in UTF-16 encoding */
+typedef WCHAR TCHAR;
+#define _T(x) L ## x
+#define _TEXT(x) L ## x
+#elif FF_USE_LFN && FF_LFN_UNICODE == 2 /* Unicode in UTF-8 encoding */
+typedef char TCHAR;
+#define _T(x) u8 ## x
+#define _TEXT(x) u8 ## x
+#elif FF_USE_LFN && FF_LFN_UNICODE == 3 /* Unicode in UTF-32 encoding */
+typedef DWORD TCHAR;
+#define _T(x) U ## x
+#define _TEXT(x) U ## x
+#elif FF_USE_LFN && (FF_LFN_UNICODE < 0 || FF_LFN_UNICODE > 3)
+#error Wrong FF_LFN_UNICODE setting
+#else /* ANSI/OEM code in SBCS/DBCS */
+typedef char TCHAR;
+#define _T(x) x
+#define _TEXT(x) x
+#endif
+
+#endif
+
+
+
+/* Type of file size variables */
+
+#if FF_FS_EXFAT
+typedef QWORD FSIZE_t;
+#else
+typedef DWORD FSIZE_t;
+#endif
+
+
+
+/* Filesystem object structure (FATFS) */
+
+typedef struct {
+ BYTE fs_type; /* Filesystem type (0:N/A) */
+ BYTE pdrv; /* Physical drive number */
+ BYTE n_fats; /* Number of FATs (1 or 2) */
+ BYTE wflag; /* win[] flag (b0:dirty) */
+ BYTE fsi_flag; /* FSINFO flags (b7:disabled, b0:dirty) */
+ WORD id; /* Volume mount ID */
+ WORD n_rootdir; /* Number of root directory entries (FAT12/16) */
+ WORD csize; /* Cluster size [sectors] */
+#if FF_MAX_SS != FF_MIN_SS
+ WORD ssize; /* Sector size (512, 1024, 2048 or 4096) */
+#endif
+#if FF_USE_LFN
+ WCHAR* lfnbuf; /* LFN working buffer */
+#endif
+#if FF_FS_EXFAT
+ BYTE* dirbuf; /* Directory entry block scratchpad buffer for exFAT */
+#endif
+#if FF_FS_REENTRANT
+ FF_SYNC_t sobj; /* Identifier of sync object */
+#endif
+#if !FF_FS_READONLY
+ DWORD last_clst; /* Last allocated cluster */
+ DWORD free_clst; /* Number of free clusters */
+#endif
+#if FF_FS_RPATH
+ DWORD cdir; /* Current directory start cluster (0:root) */
+#if FF_FS_EXFAT
+ DWORD cdc_scl; /* Containing directory start cluster (invalid when cdir is 0) */
+ DWORD cdc_size; /* b31-b8:Size of containing directory, b7-b0: Chain status */
+ DWORD cdc_ofs; /* Offset in the containing directory (invalid when cdir is 0) */
+#endif
+#endif
+ DWORD n_fatent; /* Number of FAT entries (number of clusters + 2) */
+ DWORD fsize; /* Size of an FAT [sectors] */
+ DWORD volbase; /* Volume base sector */
+ DWORD fatbase; /* FAT base sector */
+ DWORD dirbase; /* Root directory base sector/cluster */
+ DWORD database; /* Data base sector */
+ DWORD winsect; /* Current sector appearing in the win[] */
+#ifdef __ICCARM__
+#pragma data_alignment = 32
+ BYTE win[FF_MAX_SS];
+#else
+#ifdef __aarch64__
+ BYTE win[FF_MAX_SS] __attribute__ ((aligned(64))); /* Disk access window for Directory, FAT (and file data at tiny cfg) */
+#else
+ BYTE win[FF_MAX_SS] __attribute__ ((aligned(32))); /* Disk access window for Directory, FAT (and file data at tiny cfg) */
+#endif
+#endif
+} FATFS;
+
+
+
+/* Object ID and allocation information (FFOBJID) */
+
+typedef struct {
+ FATFS* fs; /* Pointer to the hosting volume of this object */
+ WORD id; /* Hosting volume mount ID */
+ BYTE attr; /* Object attribute */
+ BYTE stat; /* Object chain status (b1-0: =0:not contiguous, =2:contiguous, =3:flagmented in this session, b2:sub-directory stretched) */
+ DWORD sclust; /* Object data start cluster (0:no cluster or root directory) */
+ FSIZE_t objsize; /* Object size (valid when sclust != 0) */
+#if FF_FS_EXFAT
+ DWORD n_cont; /* Size of first fragment - 1 (valid when stat == 3) */
+ DWORD n_frag; /* Size of last fragment needs to be written to FAT (valid when not zero) */
+ DWORD c_scl; /* Containing directory start cluster (valid when sclust != 0) */
+ DWORD c_size; /* b31-b8:Size of containing directory, b7-b0: Chain status (valid when c_scl != 0) */
+ DWORD c_ofs; /* Offset in the containing directory (valid when file object and sclust != 0) */
+#endif
+#if FF_FS_LOCK
+ UINT lockid; /* File lock ID origin from 1 (index of file semaphore table Files[]) */
+#endif
+} FFOBJID;
+
+
+
+/* File object structure (FIL) */
+
+typedef struct {
+ FFOBJID obj; /* Object identifier (must be the 1st member to detect invalid object pointer) */
+ BYTE flag; /* File status flags */
+ BYTE err; /* Abort flag (error code) */
+ FSIZE_t fptr; /* File read/write pointer (Zeroed on file open) */
+ DWORD clust; /* Current cluster of fpter (invalid when fptr is 0) */
+ DWORD sect; /* Sector number appearing in buf[] (0:invalid) */
+#if !FF_FS_READONLY
+ DWORD dir_sect; /* Sector number containing the directory entry (not used at exFAT) */
+ BYTE* dir_ptr; /* Pointer to the directory entry in the win[] (not used at exFAT) */
+#endif
+#if FF_USE_FASTSEEK
+ DWORD* cltbl; /* Pointer to the cluster link map table (nulled on open, set by application) */
+#endif
+#if !FF_FS_TINY
+#ifdef __ICCARM__
+#pragma data_alignment = 32
+ BYTE buf[FF_MAX_SS]; /* File private data read/write window */
+#else
+#ifdef __aarch64__
+ BYTE buf[FF_MAX_SS] __attribute__ ((aligned(64))); /* File private data read/write window */
+#else
+ BYTE buf[FF_MAX_SS] __attribute__ ((aligned(32))); /* File private data read/write window */
+#endif
+#endif
+#endif
+} FIL;
+
+
+
+/* Directory object structure (DIR) */
+
+typedef struct {
+ FFOBJID obj; /* Object identifier */
+ DWORD dptr; /* Current read/write offset */
+ DWORD clust; /* Current cluster */
+ DWORD sect; /* Current sector (0:Read operation has terminated) */
+ BYTE* dir; /* Pointer to the directory item in the win[] */
+ BYTE fn[12]; /* SFN (in/out) {body[8],ext[3],status[1]} */
+#if FF_USE_LFN
+ DWORD blk_ofs; /* Offset of current entry block being processed (0xFFFFFFFF:Invalid) */
+#endif
+#if FF_USE_FIND
+ const TCHAR* pat; /* Pointer to the name matching pattern */
+#endif
+} DIR;
+
+
+
+/* File information structure (FILINFO) */
+
+typedef struct {
+ FSIZE_t fsize; /* File size */
+ WORD fdate; /* Modified date */
+ WORD ftime; /* Modified time */
+ BYTE fattrib; /* File attribute */
+#if FF_USE_LFN
+ TCHAR altname[FF_SFN_BUF + 1];/* Altenative file name */
+ TCHAR fname[FF_LFN_BUF + 1]; /* Primary file name */
+#else
+ TCHAR fname[12 + 1]; /* File name */
+#endif
+} FILINFO;
+
+
+
+/* File function return code (FRESULT) */
+
+typedef enum {
+ FR_OK = 0, /* (0) Succeeded */
+ FR_DISK_ERR, /* (1) A hard error occurred in the low level disk I/O layer */
+ FR_INT_ERR, /* (2) Assertion failed */
+ FR_NOT_READY, /* (3) The physical drive cannot work */
+ FR_NO_FILE, /* (4) Could not find the file */
+ FR_NO_PATH, /* (5) Could not find the path */
+ FR_INVALID_NAME, /* (6) The path name format is invalid */
+ FR_DENIED, /* (7) Access denied due to prohibited access or directory full */
+ FR_EXIST, /* (8) Access denied due to prohibited access */
+ FR_INVALID_OBJECT, /* (9) The file/directory object is invalid */
+ FR_WRITE_PROTECTED, /* (10) The physical drive is write protected */
+ FR_INVALID_DRIVE, /* (11) The logical drive number is invalid */
+ FR_NOT_ENABLED, /* (12) The volume has no work area */
+ FR_NO_FILESYSTEM, /* (13) There is no valid FAT volume */
+ FR_MKFS_ABORTED, /* (14) The f_mkfs() aborted due to any problem */
+ FR_TIMEOUT, /* (15) Could not get a grant to access the volume within defined period */
+ FR_LOCKED, /* (16) The operation is rejected according to the file sharing policy */
+ FR_NOT_ENOUGH_CORE, /* (17) LFN working buffer could not be allocated */
+ FR_TOO_MANY_OPEN_FILES, /* (18) Number of open files > FF_FS_LOCK */
+ FR_INVALID_PARAMETER /* (19) Given parameter is invalid */
+} FRESULT;
+
+
+
+/*--------------------------------------------------------------*/
+/* FatFs module application interface */
+
+FRESULT f_open (FIL* fp, const TCHAR* path, BYTE mode); /* Open or create a file */
+FRESULT f_close (FIL* fp); /* Close an open file object */
+FRESULT f_read (FIL* fp, void* buff, UINT btr, UINT* br); /* Read data from the file */
+FRESULT f_write (FIL* fp, const void* buff, UINT btw, UINT* bw); /* Write data to the file */
+FRESULT f_lseek (FIL* fp, FSIZE_t ofs); /* Move file pointer of the file object */
+FRESULT f_truncate (FIL* fp); /* Truncate the file */
+FRESULT f_sync (FIL* fp); /* Flush cached data of the writing file */
+FRESULT f_opendir (DIR* dp, const TCHAR* path); /* Open a directory */
+FRESULT f_closedir (DIR* dp); /* Close an open directory */
+FRESULT f_readdir (DIR* dp, FILINFO* fno); /* Read a directory item */
+FRESULT f_findfirst (DIR* dp, FILINFO* fno, const TCHAR* path, const TCHAR* pattern); /* Find first file */
+FRESULT f_findnext (DIR* dp, FILINFO* fno); /* Find next file */
+FRESULT f_mkdir (const TCHAR* path); /* Create a sub directory */
+FRESULT f_unlink (const TCHAR* path); /* Delete an existing file or directory */
+FRESULT f_rename (const TCHAR* path_old, const TCHAR* path_new); /* Rename/Move a file or directory */
+FRESULT f_stat (const TCHAR* path, FILINFO* fno); /* Get file status */
+FRESULT f_chmod (const TCHAR* path, BYTE attr, BYTE mask); /* Change attribute of a file/dir */
+FRESULT f_utime (const TCHAR* path, const FILINFO* fno); /* Change timestamp of a file/dir */
+FRESULT f_chdir (const TCHAR* path); /* Change current directory */
+FRESULT f_chdrive (const TCHAR* path); /* Change current drive */
+FRESULT f_getcwd (TCHAR* buff, UINT len); /* Get current directory */
+FRESULT f_getfree (const TCHAR* path, DWORD* nclst, FATFS** fatfs); /* Get number of free clusters on the drive */
+FRESULT f_getlabel (const TCHAR* path, TCHAR* label, DWORD* vsn); /* Get volume label */
+FRESULT f_setlabel (const TCHAR* label); /* Set volume label */
+FRESULT f_forward (FIL* fp, UINT(*func)(const BYTE*,UINT), UINT btf, UINT* bf); /* Forward data to the stream */
+FRESULT f_expand (FIL* fp, FSIZE_t szf, BYTE opt); /* Allocate a contiguous block to the file */
+FRESULT f_mount (FATFS* fs, const TCHAR* path, BYTE opt); /* Mount/Unmount a logical drive */
+FRESULT f_mkfs (const TCHAR* path, BYTE opt, DWORD au, void* work, UINT len); /* Create a FAT volume */
+FRESULT f_fdisk (BYTE pdrv, const DWORD* szt, void* work); /* Divide a physical drive into some partitions */
+FRESULT f_setcp (WORD cp); /* Set current code page */
+int f_putc (TCHAR c, FIL* fp); /* Put a character to the file */
+int f_puts (const TCHAR* str, FIL* cp); /* Put a string to the file */
+int f_printf (FIL* fp, const TCHAR* str, ...); /* Put a formatted string to the file */
+TCHAR* f_gets (TCHAR* buff, int len, FIL* fp); /* Get a string from the file */
+
+#define f_eof(fp) ((int)((fp)->fptr == (fp)->obj.objsize))
+#define f_error(fp) ((fp)->err)
+#define f_tell(fp) ((fp)->fptr)
+#define f_size(fp) ((fp)->obj.objsize)
+#define f_rewind(fp) f_lseek((fp), 0)
+#define f_rewinddir(dp) f_readdir((dp), 0)
+#define f_rmdir(path) f_unlink(path)
+#define f_unmount(path) f_mount(0, path, 0)
+
+#ifndef EOF
+#define EOF (-1)
+#endif
+
+
+
+
+/*--------------------------------------------------------------*/
+/* Additional user defined functions */
+
+/* RTC function */
+#if !FF_FS_READONLY && !FF_FS_NORTC
+DWORD get_fattime (void);
+#endif
+
+/* LFN support functions */
+#if FF_USE_LFN >= 1 /* Code conversion (defined in unicode.c) */
+WCHAR ff_oem2uni (WCHAR oem, WORD cp); /* OEM code to Unicode conversion */
+WCHAR ff_uni2oem (DWORD uni, WORD cp); /* Unicode to OEM code conversion */
+DWORD ff_wtoupper (DWORD uni); /* Unicode upper-case conversion */
+#endif
+#if FF_USE_LFN == 3 /* Dynamic memory allocation */
+void* ff_memalloc (UINT msize); /* Allocate memory block */
+void ff_memfree (void* mblock); /* Free memory block */
+#endif
+
+/* Sync functions */
+#if FF_FS_REENTRANT
+int ff_cre_syncobj (BYTE vol, FF_SYNC_t* sobj); /* Create a sync object */
+int ff_req_grant (FF_SYNC_t sobj); /* Lock sync object */
+void ff_rel_grant (FF_SYNC_t sobj); /* Unlock sync object */
+int ff_del_syncobj (FF_SYNC_t sobj); /* Delete a sync object */
+#endif
+
+
+
+
+/*--------------------------------------------------------------*/
+/* Flags and offset address */
+
+
+/* File access mode and open method flags (3rd argument of f_open) */
+#define FA_READ 0x01
+#define FA_WRITE 0x02
+#define FA_OPEN_EXISTING 0x00
+#define FA_CREATE_NEW 0x04
+#define FA_CREATE_ALWAYS 0x08
+#define FA_OPEN_ALWAYS 0x10
+#define FA_OPEN_APPEND 0x30
+
+/* Fast seek controls (2nd argument of f_lseek) */
+#define CREATE_LINKMAP ((FSIZE_t)0 - 1)
+
+/* Format options (2nd argument of f_mkfs) */
+#define FM_FAT 0x01
+#define FM_FAT32 0x02
+#define FM_EXFAT 0x04
+#define FM_ANY 0x07
+#define FM_SFD 0x08
+
+/* Filesystem type (FATFS.fs_type) */
+#define FS_FAT12 1
+#define FS_FAT16 2
+#define FS_FAT32 3
+#define FS_EXFAT 4
+
+/* File attribute bits for directory entry (FILINFO.fattrib) */
+#define AM_RDO 0x01 /* Read only */
+#define AM_HID 0x02 /* Hidden */
+#define AM_SYS 0x04 /* System */
+#define AM_DIR 0x10 /* Directory */
+#define AM_ARC 0x20 /* Archive */
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* FF_DEFINED */
diff --git a/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/xilffs_v4_2/src/include/ffconf.h b/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/xilffs_v4_2/src/include/ffconf.h
new file mode 100644
index 0000000..cd9ec37
--- /dev/null
+++ b/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/xilffs_v4_2/src/include/ffconf.h
@@ -0,0 +1,380 @@
+/*---------------------------------------------------------------------------/
+/ FatFs - Configuration file
+/---------------------------------------------------------------------------*/
+
+
+#define FFCONF_DEF 63463 /* Revision ID */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include "xparameters.h"
+
+/*---------------------------------------------------------------------------/
+/ Function Configurations
+/---------------------------------------------------------------------------*/
+
+#ifdef FILE_SYSTEM_READ_ONLY
+#define FF_FS_READONLY 1 /* 1:Read only */
+#else
+#define FF_FS_READONLY 0 /* 0:Read/Write */
+#endif
+/* This option switches read-only configuration. (0:Read/Write or 1:Read-only)
+/ Read-only configuration removes writing API functions, f_write(), f_sync(),
+/ f_unlink(), f_mkdir(), f_chmod(), f_rename(), f_truncate(), f_getfree()
+/ and optional writing functions as well. */
+
+
+#define FF_FS_MINIMIZE 0
+/* This option defines minimization level to remove some basic API functions.
+/
+/ 0: Basic functions are fully enabled.
+/ 1: f_stat(), f_getfree(), f_unlink(), f_mkdir(), f_truncate() and f_rename()
+/ are removed.
+/ 2: f_opendir(), f_readdir() and f_closedir() are removed in addition to 1.
+/ 3: f_lseek() function is removed in addition to 2. */
+
+
+#if FILE_SYSTEM_USE_STRFUNC == 0
+#define FF_USE_STRFUNC 0 /* 0:Disable */
+#elif FILE_SYSTEM_USE_STRFUNC == 1
+#define FF_USE_STRFUNC 1 /* 1:Enable */
+#elif FILE_SYSTEM_USE_STRFUNC == 2
+#define FF_USE_STRFUNC 2 /* 2:Enable */
+#endif
+/* This option switches string functions, f_gets(), f_putc(), f_puts() and f_printf().
+/
+/ 0: Disable string functions.
+/ 1: Enable without LF-CRLF conversion.
+/ 2: Enable with LF-CRLF conversion. */
+
+
+#define FF_USE_FIND 0
+/* This option switches filtered directory read functions, f_findfirst() and
+/ f_findnext(). (0:Disable, 1:Enable 2:Enable with matching altname[] too) */
+
+#ifdef FILE_SYSTEM_USE_MKFS
+#define FF_USE_MKFS 1 /* 1:Enable */
+#else
+#define FF_USE_MKFS 0 /* 0:Disable */
+#endif
+/* This option switches f_mkfs() function. (0:Disable or 1:Enable) */
+
+
+#define FF_USE_FASTSEEK 0
+/* This option switches fast seek function. (0:Disable or 1:Enable) */
+
+
+#define FF_USE_EXPAND 0
+/* This option switches f_expand function. (0:Disable or 1:Enable) */
+
+
+#ifdef FILE_SYSTEM_USE_CHMOD
+#define FF_USE_CHMOD 1 /* 1:Enable */
+#else
+#define FF_USE_CHMOD 0 /* 0:Disable */
+#endif
+/* This option switches attribute manipulation functions, f_chmod() and f_utime().
+/ (0:Disable or 1:Enable) Also FF_FS_READONLY needs to be 0 to enable this option. */
+
+
+#define FF_USE_LABEL 0
+/* This option switches volume label functions, f_getlabel() and f_setlabel().
+/ (0:Disable or 1:Enable) */
+
+
+#define FF_USE_FORWARD 0
+/* This option switches f_forward() function. (0:Disable or 1:Enable) */
+
+
+/*---------------------------------------------------------------------------/
+/ Locale and Namespace Configurations
+/---------------------------------------------------------------------------*/
+
+#define FF_CODE_PAGE 932
+/* This option specifies the OEM code page to be used on the target system.
+/ Incorrect code page setting can cause a file open failure.
+/
+/ 437 - U.S.
+/ 720 - Arabic
+/ 737 - Greek
+/ 771 - KBL
+/ 775 - Baltic
+/ 850 - Latin 1
+/ 852 - Latin 2
+/ 855 - Cyrillic
+/ 857 - Turkish
+/ 860 - Portuguese
+/ 861 - Icelandic
+/ 862 - Hebrew
+/ 863 - Canadian French
+/ 864 - Arabic
+/ 865 - Nordic
+/ 866 - Russian
+/ 869 - Greek 2
+/ 932 - Japanese (DBCS)
+/ 936 - Simplified Chinese (DBCS)
+/ 949 - Korean (DBCS)
+/ 950 - Traditional Chinese (DBCS)
+/ 0 - Include all code pages above and configured by f_setcp()
+*/
+
+
+#ifdef FILE_SYSTEM_USE_LFN
+#define FF_USE_LFN FILE_SYSTEM_USE_LFN /* 0 to 3 */
+#else
+#define FF_USE_LFN 0 /* 0 to 3 */
+#endif
+#define FF_MAX_LFN 255
+/* The FF_USE_LFN switches the support for LFN (long file name).
+/
+/ 0: Disable LFN. FF_MAX_LFN has no effect.
+/ 1: Enable LFN with static working buffer on the BSS. Always NOT thread-safe.
+/ 2: Enable LFN with dynamic working buffer on the STACK.
+/ 3: Enable LFN with dynamic working buffer on the HEAP.
+/
+/ To enable the LFN, ffunicode.c needs to be added to the project. The LFN function
+/ requiers certain internal working buffer occupies (FF_MAX_LFN + 1) * 2 bytes and
+/ additional (FF_MAX_LFN + 44) / 15 * 32 bytes when exFAT is enabled.
+/ The FF_MAX_LFN defines size of the working buffer in UTF-16 code unit and it can
+/ be in range of 12 to 255. It is recommended to be set 255 to fully support LFN
+/ specification.
+/ When use stack for the working buffer, take care on stack overflow. When use heap
+/ memory for the working buffer, memory management functions, ff_memalloc() and
+/ ff_memfree() in ffsystem.c, need to be added to the project. */
+
+
+#define FF_LFN_UNICODE 0
+/* This option switches the character encoding on the API when LFN is enabled.
+/
+/ 0: ANSI/OEM in current CP (TCHAR = char)
+/ 1: Unicode in UTF-16 (TCHAR = WCHAR)
+/ 2: Unicode in UTF-8 (TCHAR = char)
+/ 3: Unicode in UTF-32 (TCHAR = DWORD)
+/
+/ Also behavior of string I/O functions will be affected by this option.
+/ When LFN is not enabled, this option has no effect. */
+
+
+#define FF_LFN_BUF 255
+#define FF_SFN_BUF 12
+/* This set of options defines size of file name members in the FILINFO structure
+/ which is used to read out directory items. These values should be suffcient for
+/ the file names to read. The maximum possible length of the read file name depends
+/ on character encoding. When LFN is not enabled, these options have no effect. */
+
+
+#define FF_STRF_ENCODE 3
+/* When FF_LFN_UNICODE >= 1 with LFN enabled, string I/O functions, f_gets(),
+/ f_putc(), f_puts and f_printf() convert the character encoding in it.
+/ This option selects assumption of character encoding ON THE FILE to be
+/ read/written via those functions.
+/
+/ 0: ANSI/OEM in current CP
+/ 1: Unicode in UTF-16LE
+/ 2: Unicode in UTF-16BE
+/ 3: Unicode in UTF-8
+*/
+
+
+#if FILE_SYSTEM_SET_FS_RPATH == 0
+#define FF_FS_RPATH 0U
+#elif FILE_SYSTEM_SET_FS_RPATH == 1
+#define FF_FS_RPATH 1U
+#elif FILE_SYSTEM_SET_FS_RPATH == 2
+#define FF_FS_RPATH 2U
+#endif
+/* This option configures support for relative path.
+/
+/ 0: Disable relative path and remove related functions.
+/ 1: Enable relative path. f_chdir() and f_chdrive() are available.
+/ 2: f_getcwd() function is available in addition to 1.
+*/
+
+
+/*---------------------------------------------------------------------------/
+/ Drive/Volume Configurations
+/---------------------------------------------------------------------------*/
+
+#if FILE_SYSTEM_NUM_LOGIC_VOL == 1
+#define FF_VOLUMES 1U
+#elif FILE_SYSTEM_NUM_LOGIC_VOL == 2
+#define FF_VOLUMES 2U
+#elif FILE_SYSTEM_NUM_LOGIC_VOL == 3
+#define FF_VOLUMES 3U
+#elif FILE_SYSTEM_NUM_LOGIC_VOL == 4
+#define FF_VOLUMES 4U
+#elif FILE_SYSTEM_NUM_LOGIC_VOL == 5
+#define FF_VOLUMES 5U
+#elif FILE_SYSTEM_NUM_LOGIC_VOL == 6
+#define FF_VOLUMES 6U
+#elif FILE_SYSTEM_NUM_LOGIC_VOL == 7
+#define FF_VOLUMES 7U
+#elif FILE_SYSTEM_NUM_LOGIC_VOL == 8
+#define FF_VOLUMES 8U
+#elif FILE_SYSTEM_NUM_LOGIC_VOL == 9
+#define FF_VOLUMES 9U
+#else
+#define FF_VOLUMES 10U
+#endif
+/* Number of volumes (logical drives) to be used. (1-10) */
+
+
+#define FF_STR_VOLUME_ID 0
+#define FF_VOLUME_STRS "RAM","NAND","CF","SD","SD2","USB","USB2","USB3"
+/* FF_STR_VOLUME_ID switches support for volume ID in arbitrary strings.
+/ When FF_STR_VOLUME_ID is set to 1 or 2, arbitrary strings can be used as drive
+/ number in the path name. FF_VOLUME_STRS defines the volume ID strings for each
+/ logical drives. Number of items must not be less than FF_VOLUMES. Valid
+/ characters for the volume ID strings are A-Z, a-z and 0-9, however, they are
+/ compared in case-insensitive. If FF_STR_VOLUME_ID >= 1 and FF_VOLUME_STRS is
+/ not defined, a user defined volume string table needs to be defined as:
+/
+/ const char* VolumeStr[FF_VOLUMES] = {"ram","flash","sd","usb",...
+*/
+
+
+#ifdef FILE_SYSTEM_MULTI_PARTITION
+#define FF_MULTI_PARTITION 1 /* 1:Enable multiple partition */
+#else
+#define FF_MULTI_PARTITION 0 /* 0:Single partition */
+#endif
+/* This option switches support for multiple volumes on the physical drive.
+/ By default (0), each logical drive number is bound to the same physical drive
+/ number and only an FAT volume found on the physical drive will be mounted.
+/ When this function is enabled (1), each logical drive number can be bound to
+/ arbitrary physical drive and partition listed in the VolToPart[]. Also f_fdisk()
+/ function will be available. */
+
+
+#define FF_MIN_SS 512
+#define FF_MAX_SS 512
+/* This set of options configures the range of sector size to be supported. (512,
+/ 1024, 2048 or 4096) Always set both 512 for most systems, generic memory card and
+/ harddisk. But a larger value may be required for on-board flash memory and some
+/ type of optical media. When FF_MAX_SS is larger than FF_MIN_SS, FatFs is configured
+/ for variable sector size mode and disk_ioctl() function needs to implement
+/ GET_SECTOR_SIZE command. */
+
+
+#define FF_USE_TRIM 0
+/* This option switches support for ATA-TRIM. (0:Disable or 1:Enable)
+/ To enable Trim function, also CTRL_TRIM command should be implemented to the
+/ disk_ioctl() function. */
+
+
+#define FF_FS_NOFSINFO 0
+/* If you need to know correct free space on the FAT32 volume, set bit 0 of this
+/ option, and f_getfree() function at first time after volume mount will force
+/ a full FAT scan. Bit 1 controls the use of last allocated cluster number.
+/
+/ bit0=0: Use free cluster count in the FSINFO if available.
+/ bit0=1: Do not trust free cluster count in the FSINFO.
+/ bit1=0: Use last allocated cluster number in the FSINFO if available.
+/ bit1=1: Do not trust last allocated cluster number in the FSINFO.
+*/
+
+
+
+/*---------------------------------------------------------------------------/
+/ System Configurations
+/---------------------------------------------------------------------------*/
+
+#define FF_FS_TINY 0
+/* This option switches tiny buffer configuration. (0:Normal or 1:Tiny)
+/ At the tiny configuration, size of file object (FIL) is shrunk FF_MAX_SS bytes.
+/ Instead of private sector buffer eliminated from the file object, common sector
+/ buffer in the filesystem object (FATFS) is used for the file data transfer. */
+
+
+#ifdef FILE_SYSTEM_FS_EXFAT
+#define FF_FS_EXFAT 1
+#else
+#define FF_FS_EXFAT 0
+#endif
+/* This option switches support for exFAT filesystem. (0:Disable or 1:Enable)
+/ To enable exFAT, also LFN needs to be enabled.
+/ Note that enabling exFAT discards ANSI C (C89) compatibility. */
+
+
+#define FF_FS_NORTC 0
+#define FF_NORTC_MON 1
+#define FF_NORTC_MDAY 1
+#define FF_NORTC_YEAR 2018
+/* The option FF_FS_NORTC switches timestamp functiton. If the system does not have
+/ any RTC function or valid timestamp is not needed, set FF_FS_NORTC = 1 to disable
+/ the timestamp function. Every object modified by FatFs will have a fixed timestamp
+/ defined by FF_NORTC_MON, FF_NORTC_MDAY and FF_NORTC_YEAR in local time.
+/ To enable timestamp function (FF_FS_NORTC = 0), get_fattime() function need to be
+/ added to the project to read current time form real-time clock. FF_NORTC_MON,
+/ FF_NORTC_MDAY and FF_NORTC_YEAR have no effect.
+/ These options have no effect at read-only configuration (FF_FS_READONLY = 1). */
+
+
+#define FF_FS_LOCK 0
+/* The option FF_FS_LOCK switches file lock function to control duplicated file open
+/ and illegal operation to open objects. This option must be 0 when FF_FS_READONLY
+/ is 1.
+/
+/ 0: Disable file lock function. To avoid volume corruption, application program
+/ should avoid illegal open, remove and rename to the open objects.
+/ >0: Enable file lock function. The value defines how many files/sub-directories
+/ can be opened simultaneously under file lock control. Note that the file
+/ lock control is independent of re-entrancy. */
+
+
+#define FF_FS_REENTRANT 0
+#define FF_FS_TIMEOUT 1000
+#define FF_SYNC_t HANDLE
+/* The option FF_FS_REENTRANT switches the re-entrancy (thread safe) of the FatFs
+/ module itself. Note that regardless of this option, file access to different
+/ volume is always re-entrant and volume control functions, f_mount(), f_mkfs()
+/ and f_fdisk() function, are always not re-entrant. Only file/directory access
+/ to the same volume is under control of this function.
+/
+/ 0: Disable re-entrancy. FF_FS_TIMEOUT and FF_SYNC_t have no effect.
+/ 1: Enable re-entrancy. Also user provided synchronization handlers,
+/ ff_req_grant(), ff_rel_grant(), ff_del_syncobj() and ff_cre_syncobj()
+/ function, must be added to the project. Samples are available in
+/ option/syscall.c.
+/
+/ The FF_FS_TIMEOUT defines timeout period in unit of time tick.
+/ The FF_SYNC_t defines O/S dependent sync object type. e.g. HANDLE, ID, OS_EVENT*,
+/ SemaphoreHandle_t and etc. A header file for O/S definitions needs to be
+/ included somewhere in the scope of ff.h. */
+
+/* #include <windows.h> // O/S definitions */
+
+#ifdef FILE_SYSTEM_WORD_ACCESS
+#define FF_WORD_ACCESS 1
+#else
+#define FF_WORD_ACCESS 0
+#endif
+/* The FF_WORD_ACCESS option is an only platform dependent option. It defines
+/ which access method is used to the word data on the FAT volume.
+/
+/ 0: Byte-by-byte access. Always compatible with all platforms.
+/ 1: Word access. Do not choose this unless under both the following conditions.
+/
+/ * Address misaligned memory access is always allowed for ALL instructions.
+/ * Byte order on the memory is little-endian.
+/
+/ If it is the case, FF_WORD_ACCESS can also be set to 1 to improve performance and
+/ reduce code size. Following table shows an example of some processor types.
+/
+/ ARM7TDMI 0 ColdFire 0 V850E 0
+/ Cortex-M3 0 Z80 0/1 V850ES 0/1
+/ Cortex-M0 0 RX600(LE) 0/1 TLCS-870 0/1
+/ AVR 0/1 RX600(BE) 0 TLCS-900 0/1
+/ AVR32 0 RL78 0 R32C 0
+/ PIC18 0/1 SH-2 0 M16C 0/1
+/ PIC24 0 H8S 0 MSP430 0
+/ PIC32 0 H8/300H 0 x86 0/1
+*/
+
+#ifdef __cplusplus
+}
+#endif
+
+/*--- End of configuration options ---*/
diff --git a/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/xilffs_v4_2/src/include/integer.h b/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/xilffs_v4_2/src/include/integer.h
new file mode 100644
index 0000000..b3c70ca
--- /dev/null
+++ b/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/xilffs_v4_2/src/include/integer.h
@@ -0,0 +1,36 @@
+/*-------------------------------------------*/
+/* Integer type definitions for FatFs module */
+/*-------------------------------------------*/
+
+#ifndef FF_INTEGER
+#define FF_INTEGER
+
+#ifdef _WIN32 /* FatFs development platform */
+
+#include <windows.h>
+typedef unsigned __int64 QWORD;
+
+#else /* Embedded platform */
+
+/* These types MUST be 16-bit or 32-bit */
+typedef int INT;
+typedef unsigned int UINT;
+
+/* This type MUST be 8-bit */
+typedef unsigned char BYTE;
+
+/* These types MUST be 16-bit */
+typedef short SHORT;
+typedef unsigned short WORD;
+typedef unsigned short WCHAR;
+
+/* These types MUST be 32-bit */
+typedef long LONG;
+typedef unsigned long DWORD;
+
+/* This type MUST be 64-bit (Remove this for ANSI C (C89) compatibility) */
+typedef unsigned long long QWORD;
+
+#endif
+
+#endif
diff --git a/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/xilrsa_v1_5/src/Makefile b/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/xilrsa_v1_5/src/Makefile
new file mode 100644
index 0000000..b916b90
--- /dev/null
+++ b/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/xilrsa_v1_5/src/Makefile
@@ -0,0 +1,50 @@
+###############################################################################
+#
+# Copyright (C) 2014 - 2016 Xilinx, Inc. All rights reserved.
+#
+# Permission is hereby granted, free of charge, to any person obtaining a copy
+# of this software and associated documentation files (the "Software"), to deal
+# in the Software without restriction, including without limitation the rights
+# to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+# copies of the Software, and to permit persons to whom the Software is
+# furnished to do so, subject to the following conditions:
+#
+# The above copyright notice and this permission notice shall be included in
+# all copies or substantial portions of the Software.
+#
+# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+# THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+# LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+# OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+# THE SOFTWARE.
+#
+#
+#
+###############################################################################
+
+COMPILER=
+ARCHIVER=
+CP=cp
+COMPILER_FLAGS=
+LIB=librsa.a
+
+RELEASEDIR=../../../lib
+INCLUDEDIR=../../../include
+INCLUDES=-I./include/ -I${INCLUDEDIR}
+LIBRSA_DIR = .
+
+EXPORT_INCLUDE_DIR = $(LIBRSA_DIR)/include
+
+libs:
+ cp $(LIBRSA_DIR)/librsa.a $(RELEASEDIR)
+
+.PHONY: include
+include: xilrsa_includes
+
+xilrsa_includes:
+ cp -r ${EXPORT_INCLUDE_DIR}/xilrsa.h ${INCLUDEDIR}
+
+clean:
+ rm -rf $(RELEASEDIR)/$(LIB)
diff --git a/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/xilrsa_v1_5/src/include/xilrsa.h b/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/xilrsa_v1_5/src/include/xilrsa.h
new file mode 100644
index 0000000..7eef0a9
--- /dev/null
+++ b/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/xilrsa_v1_5/src/include/xilrsa.h
@@ -0,0 +1,250 @@
+/******************************************************************************
+*
+* Copyright (C) 2014 - 17 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+* THE SOFTWARE.
+*
+*
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xilrsa.h
+* @addtogroup xilrsa_apis XilRSA APIs and Descriptions
+* @{
+* @cond xilrsa_internal
+* This file contains the RSA algorithm functions
+*
+* <pre>
+* MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ----- ---- -------- -------------------------------------------------------
+* 1.0 hk 27/01/14 First release
+* 1.4 vns 07/06/17 Added dooxygen tags.
+*
+* </pre>
+*
+* @note
+*
+******************************************************************************/
+#ifndef ___XIL_RSA_H___
+#define ___XIL_RSA_H___
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+/***************************** Include Files *********************************/
+
+/*
+ * Digit size selection (32 or 16-bit). If supported by the CPU/compiler,
+ * 32-bit digits are approximately 4 times faster
+ */
+
+//#define RSA_DIGIT_16
+#define RSA_DIGIT_32
+
+/*
+ * RSA loop unrolling selection
+ * RSA main loop can be unrolled 2, 4 or 8 ways
+ */
+#define RSA_UNROLL 1
+
+/*
+ * Select if ARM-optimized code is to be used. Only GCC for ARM is supported
+ */
+//#define RSA_ARM_OPTIMIZED
+
+/*
+ * Check the compatibility of the selection
+ */
+#if defined(RSA_DIGIT_16) && defined(RSA_DIGIT_32)
+ #error Please select a digit size
+#endif
+#if !defined(RSA_DIGIT_16) && !defined(RSA_DIGIT_32)
+ #error Please select just one digit size
+#endif
+#if (!defined(__GNUC__) || !defined(__arm__)) && defined(RSA_ARM_OPTIMIZED)
+ #error Assembly level code is only supported for the GCC/ARM combination
+#endif
+#if (RSA_UNROLL != 1) && (RSA_UNROLL != 2) && (RSA_UNROLL != 4) && (RSA_UNROLL != 8)
+ #error Only 1, 2, 4, and 8 unrolling are supported
+#endif
+
+#ifdef RSA_DIGIT_16
+#define RSA_DIGIT unsigned short
+#define RSA_SDIGIT short
+#define RSA_DDIGIT unsigned long
+#endif
+#ifdef RSA_DIGIT_32
+#define RSA_DIGIT unsigned long
+#define RSA_SDIGIT long
+#define RSA_DDIGIT unsigned long long
+#endif
+
+#define RSA_NUMBER RSA_DIGIT *
+#define RSA_NBITS 2048
+#define RSA_NDIGITS (RSA_NBITS/(sizeof(RSA_DIGIT)*8))
+#define RSA_NBYTES (RSA_NDIGITS*sizeof(RSA_DIGIT))
+
+/*
+ * Double-digit to single digit conversion
+ */
+#define RSA_MSB(x) (x >> (sizeof(RSA_DIGIT)*8))
+#define RSA_LSB(x) (x & (RSA_DIGIT)~0)
+
+#define SHA_BLKSIZE 512
+#define SHA_BLKBYTES (SHA_BLKSIZE/8)
+#define SHA_BLKWORDS (SHA_BLKBYTES/4)
+
+#define SHA_VALSIZE 256
+#define SHA_VALBYTES (SHA_VALSIZE/8)
+#define SHA_VALWORDS (SHA_VALBYTES/4)
+
+/*
+ * SHA-256 context structure
+ * Includes SHA-256 state, coalescing buffer to collect the processed strings, and
+ * total byte length counter (used both to manage the buffer and for padding)
+ */
+ //! [sha2_context]
+typedef struct
+{
+ unsigned int state[8];
+ unsigned char buffer[SHA_BLKBYTES];
+ unsigned long long bytes;
+} sha2_context;
+//! [sha2_context]
+/** @}
+@endcond */
+
+/*
+ * RSA-2048 user interfaces
+ */
+/*****************************************************************************/
+/**
+ * @brief
+ * This function is used to encrypt the data using 2048 bit private key.
+ *
+ * @param modular A char pointer which contains the key modulus
+ * @param modular_ext A char pointer which contains the key modulus
+ * extension
+ * @param exponent A char pointer which contains the private key
+ * exponent
+ * @param result A char pointer which contains the encrypted data
+ *
+ * @return None
+ *
+ ******************************************************************************/
+void rsa2048_exp(const unsigned char *base, const unsigned char * modular,
+ const unsigned char *modular_ext, const unsigned char *exponent,
+ unsigned char *result);
+/*****************************************************************************/
+/**
+ * @brief
+ * This function is used to decrypt the data using 2048 bit public key
+ *
+ * @param a RSA_NUMBER containing the decrypted data.
+ * @param x RSA_NUMBER containing the input data
+ * @param e Unsigned number containing the public key exponent
+ * @param m RSA_NUMBER containing the public key modulus
+ * @param rrm RSA_NUMBER containing the public key modulus extension.
+ *
+ * @return None
+ *
+ ******************************************************************************/
+void rsa2048_pubexp(RSA_NUMBER a, RSA_NUMBER x,
+ unsigned long e, RSA_NUMBER m, RSA_NUMBER rrm);
+
+/*
+ * SHA-256 user interfaces
+ */
+/*****************************************************************************/
+/**
+ * @brief
+ * This function calculates the hash for the input data using SHA-256
+ * algorithm. This function internally calls the sha2_init, updates and
+ * finishes functions and updates the result.
+ *
+ * @param In Char pointer which contains the input data.
+ * @param Size Length of the input data
+ * @param Out Pointer to location where resulting hash will be
+ * written.
+ *
+ * @return None
+ *
+ ******************************************************************************/
+void sha_256(const unsigned char *in, const unsigned int size, unsigned char *out);
+/*****************************************************************************/
+/**
+ * @brief
+ * This function initializes the SHA2 context.
+ *
+ * @param ctx Pointer to sha2_context structure that stores status and
+ * buffer.
+ *
+ * @return None
+ *
+ ******************************************************************************/
+void sha2_starts(sha2_context *ctx);
+/*****************************************************************************/
+/**
+ * @brief
+ * This function adds the input data to SHA256 calculation.
+ *
+ * @param ctx Pointer to sha2_context structure that stores status and
+ * buffer.
+ * @param input Pointer to the data to add.
+ * @param Out Length of the input data.
+ *
+ * @return None
+ *
+ ******************************************************************************/
+void sha2_update(sha2_context *ctx, unsigned char* input, unsigned int ilen);
+/*****************************************************************************/
+/**
+ * @brief
+ * This function finishes the SHA calculation.
+ *
+ * @param ctx Pointer to sha2_context structure that stores status and
+ * buffer.
+ * @param output Pointer to the calculated hash data.
+ *
+ * @return None
+ *
+ *
+ ******************************************************************************/
+void sha2_finish(sha2_context *ctx, unsigned char* output);
+
+/*
+ * Preprocessing interface (pre-computation of R*R mod M)
+ */
+/**@cond xilrsa_internal */
+void modular_ext(const unsigned char *modular, unsigned char *res);
+/** @}
+@endcond */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* ___XIL_RSA_H___ */
+/** @} */
+
+
diff --git a/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/xilrsa_v1_5/src/librsa.a b/hello_world/sw/fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/xilrsa_v1_5/src/librsa.a
new file mode 100644
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diff --git a/hello_world/sw/fsbl/zynq_fsbl_bsp/system.mss b/hello_world/sw/fsbl/zynq_fsbl_bsp/system.mss
new file mode 100644
index 0000000..64c2ec2
--- /dev/null
+++ b/hello_world/sw/fsbl/zynq_fsbl_bsp/system.mss
@@ -0,0 +1,269 @@
+
+ PARAMETER VERSION = 2.2.0
+
+
+BEGIN OS
+ PARAMETER OS_NAME = standalone
+ PARAMETER OS_VER = 7.1
+ PARAMETER PROC_INSTANCE = ps7_cortexa9_0
+ PARAMETER stdin = ps7_uart_1
+ PARAMETER stdout = ps7_uart_1
+END
+
+
+BEGIN PROCESSOR
+ PARAMETER DRIVER_NAME = cpu_cortexa9
+ PARAMETER DRIVER_VER = 2.8
+ PARAMETER HW_INSTANCE = ps7_cortexa9_0
+END
+
+
+BEGIN DRIVER
+ PARAMETER DRIVER_NAME = bram
+ PARAMETER DRIVER_VER = 4.3
+ PARAMETER HW_INSTANCE = i_bram_ctrl_ex_stack
+END
+
+BEGIN DRIVER
+ PARAMETER DRIVER_NAME = bram
+ PARAMETER DRIVER_VER = 4.3
+ PARAMETER HW_INSTANCE = i_bram_ctrl_key
+END
+
+BEGIN DRIVER
+ PARAMETER DRIVER_NAME = bram
+ PARAMETER DRIVER_VER = 4.3
+ PARAMETER HW_INSTANCE = i_bram_ctrl_logic_analyzer
+END
+
+BEGIN DRIVER
+ PARAMETER DRIVER_NAME = bram
+ PARAMETER DRIVER_VER = 4.3
+ PARAMETER HW_INSTANCE = i_bram_ctrl_sw_att
+END
+
+BEGIN DRIVER
+ PARAMETER DRIVER_NAME = generic
+ PARAMETER DRIVER_VER = 2.0
+ PARAMETER HW_INSTANCE = ps7_afi_0
+END
+
+BEGIN DRIVER
+ PARAMETER DRIVER_NAME = generic
+ PARAMETER DRIVER_VER = 2.0
+ PARAMETER HW_INSTANCE = ps7_afi_1
+END
+
+BEGIN DRIVER
+ PARAMETER DRIVER_NAME = generic
+ PARAMETER DRIVER_VER = 2.0
+ PARAMETER HW_INSTANCE = ps7_afi_2
+END
+
+BEGIN DRIVER
+ PARAMETER DRIVER_NAME = generic
+ PARAMETER DRIVER_VER = 2.0
+ PARAMETER HW_INSTANCE = ps7_afi_3
+END
+
+BEGIN DRIVER
+ PARAMETER DRIVER_NAME = coresightps_dcc
+ PARAMETER DRIVER_VER = 1.6
+ PARAMETER HW_INSTANCE = ps7_coresight_comp_0
+END
+
+BEGIN DRIVER
+ PARAMETER DRIVER_NAME = ddrps
+ PARAMETER DRIVER_VER = 1.0
+ PARAMETER HW_INSTANCE = ps7_ddr_0
+END
+
+BEGIN DRIVER
+ PARAMETER DRIVER_NAME = generic
+ PARAMETER DRIVER_VER = 2.0
+ PARAMETER HW_INSTANCE = ps7_ddrc_0
+END
+
+BEGIN DRIVER
+ PARAMETER DRIVER_NAME = devcfg
+ PARAMETER DRIVER_VER = 3.5
+ PARAMETER HW_INSTANCE = ps7_dev_cfg_0
+END
+
+BEGIN DRIVER
+ PARAMETER DRIVER_NAME = dmaps
+ PARAMETER DRIVER_VER = 2.5
+ PARAMETER HW_INSTANCE = ps7_dma_ns
+END
+
+BEGIN DRIVER
+ PARAMETER DRIVER_NAME = dmaps
+ PARAMETER DRIVER_VER = 2.5
+ PARAMETER HW_INSTANCE = ps7_dma_s
+END
+
+BEGIN DRIVER
+ PARAMETER DRIVER_NAME = emacps
+ PARAMETER DRIVER_VER = 3.10
+ PARAMETER HW_INSTANCE = ps7_ethernet_0
+END
+
+BEGIN DRIVER
+ PARAMETER DRIVER_NAME = generic
+ PARAMETER DRIVER_VER = 2.0
+ PARAMETER HW_INSTANCE = ps7_globaltimer_0
+END
+
+BEGIN DRIVER
+ PARAMETER DRIVER_NAME = gpiops
+ PARAMETER DRIVER_VER = 3.6
+ PARAMETER HW_INSTANCE = ps7_gpio_0
+END
+
+BEGIN DRIVER
+ PARAMETER DRIVER_NAME = generic
+ PARAMETER DRIVER_VER = 2.0
+ PARAMETER HW_INSTANCE = ps7_gpv_0
+END
+
+BEGIN DRIVER
+ PARAMETER DRIVER_NAME = generic
+ PARAMETER DRIVER_VER = 2.0
+ PARAMETER HW_INSTANCE = ps7_intc_dist_0
+END
+
+BEGIN DRIVER
+ PARAMETER DRIVER_NAME = generic
+ PARAMETER DRIVER_VER = 2.0
+ PARAMETER HW_INSTANCE = ps7_iop_bus_config_0
+END
+
+BEGIN DRIVER
+ PARAMETER DRIVER_NAME = generic
+ PARAMETER DRIVER_VER = 2.0
+ PARAMETER HW_INSTANCE = ps7_l2cachec_0
+END
+
+BEGIN DRIVER
+ PARAMETER DRIVER_NAME = generic
+ PARAMETER DRIVER_VER = 2.0
+ PARAMETER HW_INSTANCE = ps7_ocmc_0
+END
+
+BEGIN DRIVER
+ PARAMETER DRIVER_NAME = generic
+ PARAMETER DRIVER_VER = 2.0
+ PARAMETER HW_INSTANCE = ps7_pl310_0
+END
+
+BEGIN DRIVER
+ PARAMETER DRIVER_NAME = generic
+ PARAMETER DRIVER_VER = 2.0
+ PARAMETER HW_INSTANCE = ps7_pmu_0
+END
+
+BEGIN DRIVER
+ PARAMETER DRIVER_NAME = qspips
+ PARAMETER DRIVER_VER = 3.6
+ PARAMETER HW_INSTANCE = ps7_qspi_0
+END
+
+BEGIN DRIVER
+ PARAMETER DRIVER_NAME = generic
+ PARAMETER DRIVER_VER = 2.0
+ PARAMETER HW_INSTANCE = ps7_qspi_linear_0
+END
+
+BEGIN DRIVER
+ PARAMETER DRIVER_NAME = generic
+ PARAMETER DRIVER_VER = 2.0
+ PARAMETER HW_INSTANCE = ps7_ram_0
+END
+
+BEGIN DRIVER
+ PARAMETER DRIVER_NAME = generic
+ PARAMETER DRIVER_VER = 2.0
+ PARAMETER HW_INSTANCE = ps7_ram_1
+END
+
+BEGIN DRIVER
+ PARAMETER DRIVER_NAME = generic
+ PARAMETER DRIVER_VER = 2.0
+ PARAMETER HW_INSTANCE = ps7_scuc_0
+END
+
+BEGIN DRIVER
+ PARAMETER DRIVER_NAME = scugic
+ PARAMETER DRIVER_VER = 4.1
+ PARAMETER HW_INSTANCE = ps7_scugic_0
+END
+
+BEGIN DRIVER
+ PARAMETER DRIVER_NAME = scutimer
+ PARAMETER DRIVER_VER = 2.1
+ PARAMETER HW_INSTANCE = ps7_scutimer_0
+END
+
+BEGIN DRIVER
+ PARAMETER DRIVER_NAME = scuwdt
+ PARAMETER DRIVER_VER = 2.1
+ PARAMETER HW_INSTANCE = ps7_scuwdt_0
+END
+
+BEGIN DRIVER
+ PARAMETER DRIVER_NAME = sdps
+ PARAMETER DRIVER_VER = 3.8
+ PARAMETER HW_INSTANCE = ps7_sd_0
+END
+
+BEGIN DRIVER
+ PARAMETER DRIVER_NAME = generic
+ PARAMETER DRIVER_VER = 2.0
+ PARAMETER HW_INSTANCE = ps7_slcr_0
+END
+
+BEGIN DRIVER
+ PARAMETER DRIVER_NAME = generic
+ PARAMETER DRIVER_VER = 2.0
+ PARAMETER HW_INSTANCE = ps7_trace_0
+END
+
+BEGIN DRIVER
+ PARAMETER DRIVER_NAME = ttcps
+ PARAMETER DRIVER_VER = 3.10
+ PARAMETER HW_INSTANCE = ps7_ttc_0
+END
+
+BEGIN DRIVER
+ PARAMETER DRIVER_NAME = uartps
+ PARAMETER DRIVER_VER = 3.8
+ PARAMETER HW_INSTANCE = ps7_uart_1
+END
+
+BEGIN DRIVER
+ PARAMETER DRIVER_NAME = usbps
+ PARAMETER DRIVER_VER = 2.4
+ PARAMETER HW_INSTANCE = ps7_usb_0
+END
+
+BEGIN DRIVER
+ PARAMETER DRIVER_NAME = xadcps
+ PARAMETER DRIVER_VER = 2.3
+ PARAMETER HW_INSTANCE = ps7_xadc_0
+END
+
+
+BEGIN LIBRARY
+ PARAMETER LIBRARY_NAME = xilffs
+ PARAMETER LIBRARY_VER = 4.2
+ PARAMETER PROC_INSTANCE = ps7_cortexa9_0
+END
+
+
+BEGIN LIBRARY
+ PARAMETER LIBRARY_NAME = xilrsa
+ PARAMETER LIBRARY_VER = 1.5
+ PARAMETER PROC_INSTANCE = ps7_cortexa9_0
+END
+
+
diff --git a/openocd_zynq.tcl b/openocd_zynq.tcl
new file mode 100644
index 0000000..87e269d
--- /dev/null
+++ b/openocd_zynq.tcl
@@ -0,0 +1,25 @@
+#
+# Digilent Zybo Board Rev.C, Rev.D with Xilinx Zynq chip
+#
+# http://zedboard.com/product/zedboard
+#
+
+adapter driver ftdi
+ftdi_device_desc "Digilent Adept USB Device"
+ftdi_vid_pid 0x0403 0x6010
+
+ftdi_layout_init 0x3088 0x1f8b
+ftdi_layout_signal nSRST -data 0x3000 -oe 0x3000
+ftdi_layout_signal LED -data 0x0010
+
+reset_config srst_only
+adapter srst delay 40
+
+source [find target/zynq_7000.cfg]
+
+# overwrite setting in zynq_7000.cfg
+adapter speed 8000
+pld device virtex2 zynq_pl.bs 1
+
+init
+scan_chain ;# displays the TAPs in the scan chain configuration and their status
diff --git a/vivadoMakefile.tcl b/vivadoMakefile.tcl
new file mode 100755
index 0000000..36fa781
--- /dev/null
+++ b/vivadoMakefile.tcl
@@ -0,0 +1,258 @@
+#!/bin/sh
+# the next line restarts using vivado \
+exec vivado -mode batch -source "$0" -tclargs ${1+"$@"}
+
+#
+# Copyright (C) 2021 Jonathan Certes
+#
+# This program is free software: you can redistribute it and/or modify it under
+# the terms of the GNU General Public License as published by the Free Software
+# Foundation, either version 3 of the License, or (at your option) any later
+# version.
+#
+# This program is distributed in the hope that it will be useful, but WITHOUT
+# ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS
+# FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License along with
+# this program. If not, see <http://www.gnu.org/licenses/>.
+#
+
+set theHdlList [list]
+set theSchematicList [list]
+set theConstraintList [list]
+set theTopLevelName ""
+set theFpga "xc7z007sclg400-1"
+
+set dryRun 0
+set doExport 0
+set theExportedOutput "output.xsa"
+
+#===============================================================================
+# parse argv:
+#===============================================================================
+
+if { [info exists argv] } {
+
+ set theOption ""
+ foreach theArg $argv {
+ if { [string first "--" $theArg] == 0 } {
+
+ set theOption $theArg
+ switch $theOption {
+ "--hdl" {}
+ "--schem" {}
+ "--constr" {}
+ "--top" {}
+ "--output" {}
+ "--fpga" {}
+ "--dry-run" { set dryRun 1 }
+ "--do-export" { set doExport 1 }
+ default {
+ puts "unknown option \"$theOption\", ignoring"
+ }
+ }
+
+ } else {
+
+ switch $theOption {
+ "--hdl" { lappend theHdlList $theArg }
+ "--schem" { lappend theSchematicList $theArg }
+ "--constr" { lappend theConstraintList $theArg }
+ "--fpga" { set theFpga $theArg }
+ "--top" { set theTopLevelName $theArg }
+ "--output" { set theExportedOutput $theArg }
+ default {
+ puts "unknown option \"$theOption\", ignoring arg: $theArg"
+ }
+ }
+
+ }
+ }
+
+}
+
+set hasError 0
+foreach theHdl $theHdlList {
+ if { ![file exists $theHdl] || ![file isfile $theHdl] } {
+ puts "** Error ** HDL file does not exist: $theHdl"
+ set hasError 1
+ }
+}
+#
+foreach theSchematic $theSchematicList {
+ if { ![file exists $theSchematic] || ![file isfile $theSchematic] } {
+ puts "** Error ** schematic file does not exist: $theSchematic"
+ set hasError 1
+ }
+}
+#
+foreach theConstraint $theConstraintList {
+ if { ![file exists $theConstraint] || ![file isfile $theConstraint] } {
+ puts "** Error ** constraint file does not exist: $theConstraint"
+ set hasError 1
+ }
+}
+
+if { $hasError } {
+ exit 0
+}
+
+
+#===============================================================================
+# use vivado API to create/update the project and export:
+#===============================================================================
+
+set theWorkspace "vivado.workspace"
+set theProject [file tail [pwd]]
+
+set theHdlList [lsort ${theHdlList}]
+set theSchematicList [lsort ${theSchematicList}]
+set theConstraintList [lsort ${theConstraintList}]
+set needToRun 0
+
+
+##
+# creates or opens the project:
+#
+set theProjectFile [file join ${theWorkspace} "${theProject}.xpr"]
+if { [file exists ${theProjectFile}] } {
+ open_project ${theProjectFile}
+} else {
+ create_project ${theProject} vivado.workspace -part ${theFpga} -force
+}
+
+
+##
+# adds the HDL files to the project if not already in it:
+#
+set alreadyInList [get_files -filter { FILE_TYPE == Verilog ||
+ FILE_TYPE == VHDL }]
+#
+foreach theHdl $theHdlList {
+ set theHdl [file normalize ${theHdl}]
+ if { [lsearch ${alreadyInList} ${theHdl}] == -1 } {
+ add_files ${theHdl}
+ set needToRun 1
+ }
+ #
+ if { ![file exists ${theTopLevelName}.bit] ||
+ [file mtime ${theHdl}] > [file mtime ${theTopLevelName}.bit] } {
+ set needToRun 1
+ }
+}
+
+
+##
+# creates the schematics in the project if not already in it:
+#
+set alreadyInList [get_files -filter { FILE_TYPE == "Block Designs" }]
+set alreadyInList [lsort ${alreadyInList}]
+#
+if { [llength ${alreadyInList}] != [llength ${theSchematicList}] } {
+ set needToRun 1
+} else {
+ for { set i 0 } { ${i} < [llength ${alreadyInList}] } { incr i } {
+ set theDestination [lindex ${alreadyInList} ${i}]
+ set theSchematic [lindex ${theSchematicList} ${i}]
+ if { [file mtime ${theSchematic}] > [file mtime ${theDestination}] } {
+ set needToRun 1
+ break
+ }
+ }
+}
+#
+if { ${needToRun} } {
+ foreach theBlockDesign ${alreadyInList} {
+ remove_files ${theBlockDesign}
+ file delete -force ${theBlockDesign}
+ }
+
+ for { set j 0 } { ${j} < [llength ${theSchematicList}] } { incr j } {
+ set theSchematic [lindex ${theSchematicList} ${j}]
+ create_bd_design "design_${j}"
+ set theError [catch {
+ source ${theSchematic}
+ } theReturn]
+ #
+ if { $theError } {
+ puts "** Error ** Source of the following script: ${theSchematic}"
+ puts ${theReturn}
+ }
+ save_bd_design "design_${j}"
+ # export as pdf:
+ write_bd_layout -format "pdf" \
+ -orientation "landscape" \
+ -force "design_${j}.pdf"
+ #
+ close_bd_design "design_${j}"
+ }
+
+ set theFiles [get_files -filter { FILE_TYPE == "Block Designs" }]
+ make_wrapper -files ${theFiles} -top -import
+}
+
+
+##
+# adds the contstraints files to the project if not already in it:
+#
+set alreadyInList [get_files -filter {FILE_TYPE == XDC}]
+#
+foreach theConstraint ${theConstraintList} {
+ set theConstraint [file normalize ${theConstraint}]
+ if { [lsearch ${alreadyInList} ${theConstraint}] == -1 } {
+ add_files ${theConstraint}
+ set needToRun 1
+ }
+ #
+ if { ![file exists ${theTopLevelName}.bit] ||
+ [file mtime ${theConstraint}] > [file mtime ${theTopLevelName}.bit] } {
+ set needToRun 1
+ }
+}
+
+
+##
+# selects top level:
+#
+set_property "source_mgmt_mode" "None" [current_project] ;# manual compile order
+if { [get_property top [current_fileset]] != ${theTopLevelName} } {
+ set_property "top" ${theTopLevelName} [current_fileset]
+ set needToRun 1
+}
+
+
+##
+# synthesis:
+#
+if { ${needToRun} } {
+ if { ${dryRun} != 0 } {
+ puts "dry-run: generation of the bitstream!"
+ } else {
+ reset_runs *
+ launch_runs "impl_1" -to_step "write_bitstream" -jobs 4
+ wait_on_run "impl_1"
+ if { ![file exists ${theTopLevelName}.bit] } {
+ file link -symbolic ${theTopLevelName}.bit \
+[file join ${theWorkspace} ${theProject}.runs "impl_1" ${theTopLevelName}.bit]
+ }
+ }
+} else {
+ puts "No modification since last time."
+}
+
+
+##
+# export:
+#
+if { ${doExport} } {
+ if { ${dryRun} != 0 } {
+ puts "dry-run: export of xsa"
+ } else {
+ write_hw_platform -fixed -force -file ${theExportedOutput}
+ }
+}
+
+
+close_project
+
--
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