diff --git a/QDMA/DPDK/RELEASE b/QDMA/DPDK/RELEASE
old mode 100644
new mode 100755
index 288ad98e37ac2e1d056fdb4bcca95c0ff3d054fa..e3bac5a84098c7fdb192b52223763db433c50ee6
--- a/QDMA/DPDK/RELEASE
+++ b/QDMA/DPDK/RELEASE
@@ -1,11 +1,13 @@
-RELEASE: 2022.1.1
+RELEASE: 2022.1.3
=================
This release is based on DPDK v20.11 and contains QDMA poll mode driver and
QDMA test application.
-This release is validated for
+This release is validated for
+ - On VCU1525 for QDMA5.0 2022.1 example design
- On VCU1525 for QDMA4.0 2020.2 example design
+ - On VCU1525 for QDMA3.1 2019.2 example design
- On XCVP1202 for CPM5 2022.1 example design
This release includes a patch file for dpdk-pktgen v20.12.0 that extends
@@ -101,13 +103,16 @@ CPM5
----------------------
- Added VF 4K queues support for CPM5 design. This feature is applicable only when corresponding RTL support is added.
+2022.1.2 Patch Updates
+----------------------
+- Added support for QDMA5.0 which has some performance optimization changes compared to QDMA4.0
+
+2022.1.3 Patch Updates
+----------------------
+- Added PF/VF 4K queues support for CPM5 design. This feature is applicable only when corresponding RTL support is added.
+
KNOWN ISSUE:
============
-- CPM5 Only
- - Sufficient host memory is required to accommodate 4K queues. Tested only upto 2048 queues for PFs with our test environment though driver supports 4K queues.
- - Tandem Boot support not available completely
- - VF 4K queue support is not fully verified due to pdi issues
-
- All Designs
- Function Level Reset(FLR) of PF device when VFs are attached to this PF results in mailbox communication failure
- DPDK C2H and Forwarding performance values for 8 queue is lesser compared to 4 queue case for both PF and VF.
@@ -127,7 +132,8 @@ DRIVER LIMITATIONS:
/*-
* BSD LICENSE
*
- * Copyright(c) 2017-2022 Xilinx, Inc. All rights reserved.
+ * Copyright (c) 2017-2022 Xilinx, Inc. All rights reserved.
+ * Copyright (c) 2022, Advanced Micro Devices, Inc. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
diff --git a/QDMA/DPDK/drivers/net/qdma/meson.build b/QDMA/DPDK/drivers/net/qdma/meson.build
old mode 100644
new mode 100755
index d280ba39db12d31d3bfb41c98cf3840e2176ce49..43fa60ad218d6ccdb24bbb723dae12c1073fe3c9
--- a/QDMA/DPDK/drivers/net/qdma/meson.build
+++ b/QDMA/DPDK/drivers/net/qdma/meson.build
@@ -1,6 +1,7 @@
# BSD LICENSE
#
-# Copyright(c) 2021-2022 Xilinx, Inc. All rights reserved.
+# Copyright (c) 2021-2022 Xilinx, Inc. All rights reserved.
+# Copyright (c) 2022, Advanced Micro Devices, Inc. All rights reserved.
#
# Redistribution and use in source and binary forms, with or without
# modification, are permitted provided that the following conditions
diff --git a/QDMA/DPDK/drivers/net/qdma/qdma.h b/QDMA/DPDK/drivers/net/qdma/qdma.h
old mode 100644
new mode 100755
index ef34b71f0c8d96569e1fa0994fa2868729517c1f..9cae38cef4ce5d20c986c3a08ff6f9ad24bf6ffd
--- a/QDMA/DPDK/drivers/net/qdma/qdma.h
+++ b/QDMA/DPDK/drivers/net/qdma/qdma.h
@@ -1,7 +1,8 @@
/*-
* BSD LICENSE
*
- * Copyright(c) 2017-2022 Xilinx, Inc. All rights reserved.
+ * Copyright (c) 2017-2022 Xilinx, Inc. All rights reserved.
+ * Copyright (c) 2022, Advanced Micro Devices, Inc. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
@@ -199,7 +200,7 @@ struct qdma_rx_queue {
enum rte_pmd_qdma_bypass_desc_len bypass_desc_sz:7;
uint8_t func_id; /**< RX queue index. */
- uint32_t ep_addr;
+ uint64_t ep_addr;
int8_t ringszidx;
int8_t cmpt_ringszidx;
@@ -252,7 +253,7 @@ struct qdma_tx_queue {
struct qdma_pkt_stats stats;
- uint32_t ep_addr;
+ uint64_t ep_addr;
uint32_t queue_id; /* TX queue index. */
uint32_t num_queues; /* TX queue index. */
const struct rte_memzone *tx_mz;
diff --git a/QDMA/DPDK/drivers/net/qdma/qdma_access/eqdma_cpm5_access/eqdma_cpm5_access.c b/QDMA/DPDK/drivers/net/qdma/qdma_access/eqdma_cpm5_access/eqdma_cpm5_access.c
old mode 100644
new mode 100755
index 28a05eff7aebd639309f69507871b4e327516e5c..4e06d5f761e00169f7dd2a113b79ce81f3bbb440
--- a/QDMA/DPDK/drivers/net/qdma/qdma_access/eqdma_cpm5_access/eqdma_cpm5_access.c
+++ b/QDMA/DPDK/drivers/net/qdma/qdma_access/eqdma_cpm5_access/eqdma_cpm5_access.c
@@ -1,5 +1,6 @@
/*
- * Copyright(c) 2019-2022 Xilinx, Inc. All rights reserved.
+ * Copyright (c) 2019-2022, Xilinx, Inc. All rights reserved.
+ * Copyright (c) 2022, Advanced Micro Devices, Inc. All rights reserved.
*
* BSD LICENSE
*
@@ -2209,7 +2210,7 @@ static int dump_eqdma_cpm5_context(struct qdma_descq_context *queue_context,
int n;
int len = 0;
int rv;
- char banner[DEBGFS_LINE_SZ];
+ char banner[DEBGFS_LINE_SZ] = "";
if (queue_context == NULL) {
qdma_log_error("%s: queue_context is NULL, err:%d\n",
@@ -2668,7 +2669,7 @@ static int dump_eqdma_cpm5_intr_context(struct qdma_indirect_intr_ctxt
int n;
int len = 0;
int rv;
- char banner[DEBGFS_LINE_SZ];
+ char banner[DEBGFS_LINE_SZ] = "";
eqdma_cpm5_fill_intr_ctxt(intr_ctx);
@@ -2792,7 +2793,7 @@ int eqdma_cpm5_get_version(void *dev_hndl, uint8_t is_vf,
reg_val = qdma_reg_read(dev_hndl, reg_addr);
- qdma_fetch_version_details(is_vf, reg_val, version_info);
+ qdma_fetch_version_details(dev_hndl, is_vf, reg_val, version_info);
return QDMA_SUCCESS;
}
diff --git a/QDMA/DPDK/drivers/net/qdma/qdma_access/eqdma_cpm5_access/eqdma_cpm5_access.h b/QDMA/DPDK/drivers/net/qdma/qdma_access/eqdma_cpm5_access/eqdma_cpm5_access.h
old mode 100644
new mode 100755
index ebfae2794666aabcb613dae2754fbc591c5f82cb..8c14e0403baf6b1a220bb4a18b7069c58d2cdc37
--- a/QDMA/DPDK/drivers/net/qdma/qdma_access/eqdma_cpm5_access/eqdma_cpm5_access.h
+++ b/QDMA/DPDK/drivers/net/qdma/qdma_access/eqdma_cpm5_access/eqdma_cpm5_access.h
@@ -1,5 +1,6 @@
/*
- * Copyright(c) 2019-2022 Xilinx, Inc. All rights reserved.
+ * Copyright (c) 2019-2022, Xilinx, Inc. All rights reserved.
+ * Copyright (c) 2022, Advanced Micro Devices, Inc. All rights reserved.
*
* BSD LICENSE
*
diff --git a/QDMA/DPDK/drivers/net/qdma/qdma_access/eqdma_cpm5_access/eqdma_cpm5_reg.h b/QDMA/DPDK/drivers/net/qdma/qdma_access/eqdma_cpm5_access/eqdma_cpm5_reg.h
old mode 100644
new mode 100755
index 2943aef3b8a88a3676434d52620c706ad721b8e7..1099ede25c6bd9af6fee7e02c0ed8d3486c978e0
--- a/QDMA/DPDK/drivers/net/qdma/qdma_access/eqdma_cpm5_access/eqdma_cpm5_reg.h
+++ b/QDMA/DPDK/drivers/net/qdma/qdma_access/eqdma_cpm5_access/eqdma_cpm5_reg.h
@@ -1,5 +1,6 @@
/*
- * Copyright(c) 2019-2022 Xilinx, Inc. All rights reserved.
+ * Copyright (c) 2019-2022 Xilinx, Inc. All rights reserved.
+ * Copyright (c) 2022, Advanced Micro Devices, Inc. All rights reserved.
*
* BSD LICENSE
*
@@ -30,8 +31,8 @@
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
-#ifndef __EQDMA_SOFT_REG_H
-#define __EQDMA_SOFT_REG_H
+#ifndef __EQDMA_CPM5_REG_H
+#define __EQDMA_CPM5_REG_H
#ifdef __cplusplus
@@ -89,49 +90,49 @@ extern "C" {
uint32_t eqdma_cpm5_config_num_regs_get(void);
struct xreg_info *eqdma_cpm5_config_regs_get(void);
-#define EQDMA_CPM5_CFG_BLK_IDENTIFIER_ADDR 0x00
+#define EQDMA_CPM5_CFG_BLK_IDENTIFIER_ADDR 0x00
#define CFG_BLK_IDENTIFIER_MASK GENMASK(31, 20)
#define CFG_BLK_IDENTIFIER_1_MASK GENMASK(19, 16)
#define CFG_BLK_IDENTIFIER_RSVD_1_MASK GENMASK(15, 8)
#define CFG_BLK_IDENTIFIER_VERSION_MASK GENMASK(7, 0)
-#define EQDMA_CPM5_CFG_BLK_PCIE_MAX_PLD_SIZE_ADDR 0x08
+#define EQDMA_CPM5_CFG_BLK_PCIE_MAX_PLD_SIZE_ADDR 0x08
#define CFG_BLK_PCIE_MAX_PLD_SIZE_RSVD_1_MASK GENMASK(31, 7)
#define CFG_BLK_PCIE_MAX_PLD_SIZE_PROG_MASK GENMASK(6, 4)
#define CFG_BLK_PCIE_MAX_PLD_SIZE_RSVD_2_MASK BIT(3)
#define CFG_BLK_PCIE_MAX_PLD_SIZE_ISSUED_MASK GENMASK(2, 0)
-#define EQDMA_CPM5_CFG_BLK_PCIE_MAX_READ_REQ_SIZE_ADDR 0x0C
+#define EQDMA_CPM5_CFG_BLK_PCIE_MAX_READ_REQ_SIZE_ADDR 0x0C
#define CFG_BLK_PCIE_MAX_READ_REQ_SIZE_RSVD_1_MASK GENMASK(31, 7)
#define CFG_BLK_PCIE_MAX_READ_REQ_SIZE_PROG_MASK GENMASK(6, 4)
#define CFG_BLK_PCIE_MAX_READ_REQ_SIZE_RSVD_2_MASK BIT(3)
#define CFG_BLK_PCIE_MAX_READ_REQ_SIZE_ISSUED_MASK GENMASK(2, 0)
-#define EQDMA_CPM5_CFG_BLK_SYSTEM_ID_ADDR 0x10
+#define EQDMA_CPM5_CFG_BLK_SYSTEM_ID_ADDR 0x10
#define CFG_BLK_SYSTEM_ID_RSVD_1_MASK GENMASK(31, 17)
#define CFG_BLK_SYSTEM_ID_INST_TYPE_MASK BIT(16)
#define CFG_BLK_SYSTEM_ID_MASK GENMASK(15, 0)
-#define EQDMA_CPM5_CFG_BLK_MSIX_ENABLE_ADDR 0x014
+#define EQDMA_CPM5_CFG_BLK_MSIX_ENABLE_ADDR 0x014
#define CFG_BLK_MSIX_ENABLE_MASK GENMASK(31, 0)
-#define EQDMA_CPM5_CFG_PCIE_DATA_WIDTH_ADDR 0x18
+#define EQDMA_CPM5_CFG_PCIE_DATA_WIDTH_ADDR 0x18
#define CFG_PCIE_DATA_WIDTH_RSVD_1_MASK GENMASK(31, 3)
#define CFG_PCIE_DATA_WIDTH_DATAPATH_MASK GENMASK(2, 0)
-#define EQDMA_CPM5_CFG_PCIE_CTL_ADDR 0x1C
+#define EQDMA_CPM5_CFG_PCIE_CTL_ADDR 0x1C
#define CFG_PCIE_CTL_RSVD_1_MASK GENMASK(31, 18)
#define CFG_PCIE_CTL_MGMT_AXIL_CTRL_MASK GENMASK(17, 16)
#define CFG_PCIE_CTL_RSVD_2_MASK GENMASK(15, 2)
#define CFG_PCIE_CTL_RRQ_DISABLE_MASK BIT(1)
#define CFG_PCIE_CTL_RELAXED_ORDERING_MASK BIT(0)
-#define EQDMA_CPM5_CFG_BLK_MSI_ENABLE_ADDR 0x20
+#define EQDMA_CPM5_CFG_BLK_MSI_ENABLE_ADDR 0x20
#define CFG_BLK_MSI_ENABLE_MASK GENMASK(31, 0)
-#define EQDMA_CPM5_CFG_AXI_USER_MAX_PLD_SIZE_ADDR 0x40
+#define EQDMA_CPM5_CFG_AXI_USER_MAX_PLD_SIZE_ADDR 0x40
#define CFG_AXI_USER_MAX_PLD_SIZE_RSVD_1_MASK GENMASK(31, 7)
#define CFG_AXI_USER_MAX_PLD_SIZE_ISSUED_MASK GENMASK(6, 4)
#define CFG_AXI_USER_MAX_PLD_SIZE_RSVD_2_MASK BIT(3)
#define CFG_AXI_USER_MAX_PLD_SIZE_PROG_MASK GENMASK(2, 0)
-#define EQDMA_CPM5_CFG_AXI_USER_MAX_READ_REQ_SIZE_ADDR 0x44
+#define EQDMA_CPM5_CFG_AXI_USER_MAX_READ_REQ_SIZE_ADDR 0x44
#define CFG_AXI_USER_MAX_READ_REQ_SIZE_RSVD_1_MASK GENMASK(31, 7)
#define CFG_AXI_USER_MAX_READ_REQ_SIZE_USISSUED_MASK GENMASK(6, 4)
#define CFG_AXI_USER_MAX_READ_REQ_SIZE_RSVD_2_MASK BIT(3)
#define CFG_AXI_USER_MAX_READ_REQ_SIZE_USPROG_MASK GENMASK(2, 0)
-#define EQDMA_CPM5_CFG_BLK_MISC_CTL_ADDR 0x4C
+#define EQDMA_CPM5_CFG_BLK_MISC_CTL_ADDR 0x4C
#define CFG_BLK_MISC_CTL_RSVD_1_MASK GENMASK(31, 24)
#define CFG_BLK_MISC_CTL_10B_TAG_EN_MASK BIT(23)
#define CFG_BLK_MISC_CTL_RSVD_2_MASK BIT(22)
@@ -140,37 +141,37 @@ struct xreg_info *eqdma_cpm5_config_regs_get(void);
#define CFG_BLK_MISC_CTL_NUM_TAG_MASK GENMASK(19, 8)
#define CFG_BLK_MISC_CTL_RSVD_3_MASK GENMASK(7, 5)
#define CFG_BLK_MISC_CTL_RQ_METERING_MULTIPLIER_MASK GENMASK(4, 0)
-#define EQDMA_CPM5_CFG_PL_CRED_CTL_ADDR 0x68
+#define EQDMA_CPM5_CFG_PL_CRED_CTL_ADDR 0x68
#define CFG_PL_CRED_CTL_RSVD_1_MASK GENMASK(31, 5)
#define CFG_PL_CRED_CTL_SLAVE_CRD_RLS_MASK BIT(4)
#define CFG_PL_CRED_CTL_RSVD_2_MASK GENMASK(3, 1)
#define CFG_PL_CRED_CTL_MASTER_CRD_RST_MASK BIT(0)
-#define EQDMA_CPM5_CFG_BLK_SCRATCH_ADDR 0x80
+#define EQDMA_CPM5_CFG_BLK_SCRATCH_ADDR 0x80
#define CFG_BLK_SCRATCH_MASK GENMASK(31, 0)
-#define EQDMA_CPM5_CFG_GIC_ADDR 0xA0
+#define EQDMA_CPM5_CFG_GIC_ADDR 0xA0
#define CFG_GIC_RSVD_1_MASK GENMASK(31, 1)
#define CFG_GIC_GIC_IRQ_MASK BIT(0)
-#define EQDMA_CPM5_RAM_SBE_MSK_1_A_ADDR 0xE0
+#define EQDMA_CPM5_RAM_SBE_MSK_1_A_ADDR 0xE0
#define RAM_SBE_MSK_1_A_MASK GENMASK(31, 0)
-#define EQDMA_CPM5_RAM_SBE_STS_1_A_ADDR 0xE4
+#define EQDMA_CPM5_RAM_SBE_STS_1_A_ADDR 0xE4
#define RAM_SBE_STS_1_A_RSVD_MASK GENMASK(31, 5)
#define RAM_SBE_STS_1_A_PFCH_CTXT_CAM_RAM_1_MASK BIT(4)
#define RAM_SBE_STS_1_A_PFCH_CTXT_CAM_RAM_0_MASK BIT(3)
#define RAM_SBE_STS_1_A_TAG_EVEN_RAM_MASK BIT(2)
#define RAM_SBE_STS_1_A_TAG_ODD_RAM_MASK BIT(1)
#define RAM_SBE_STS_1_A_RC_RRQ_EVEN_RAM_MASK BIT(0)
-#define EQDMA_CPM5_RAM_DBE_MSK_1_A_ADDR 0xE8
+#define EQDMA_CPM5_RAM_DBE_MSK_1_A_ADDR 0xE8
#define RAM_DBE_MSK_1_A_MASK GENMASK(31, 0)
-#define EQDMA_CPM5_RAM_DBE_STS_1_A_ADDR 0xEC
+#define EQDMA_CPM5_RAM_DBE_STS_1_A_ADDR 0xEC
#define RAM_DBE_STS_1_A_RSVD_MASK GENMASK(31, 5)
#define RAM_DBE_STS_1_A_PFCH_CTXT_CAM_RAM_1_MASK BIT(4)
#define RAM_DBE_STS_1_A_PFCH_CTXT_CAM_RAM_0_MASK BIT(3)
#define RAM_DBE_STS_1_A_TAG_EVEN_RAM_MASK BIT(2)
#define RAM_DBE_STS_1_A_TAG_ODD_RAM_MASK BIT(1)
#define RAM_DBE_STS_1_A_RC_RRQ_EVEN_RAM_MASK BIT(0)
-#define EQDMA_CPM5_RAM_SBE_MSK_A_ADDR 0xF0
+#define EQDMA_CPM5_RAM_SBE_MSK_A_ADDR 0xF0
#define RAM_SBE_MSK_A_MASK GENMASK(31, 0)
-#define EQDMA_CPM5_RAM_SBE_STS_A_ADDR 0xF4
+#define EQDMA_CPM5_RAM_SBE_STS_A_ADDR 0xF4
#define RAM_SBE_STS_A_RC_RRQ_ODD_RAM_MASK BIT(31)
#define RAM_SBE_STS_A_PEND_FIFO_RAM_MASK BIT(30)
#define RAM_SBE_STS_A_PFCH_LL_RAM_MASK BIT(29)
@@ -200,9 +201,9 @@ struct xreg_info *eqdma_cpm5_config_regs_get(void);
#define RAM_SBE_STS_A_MI_H2C2_DAT_MASK BIT(2)
#define RAM_SBE_STS_A_MI_H2C1_DAT_MASK BIT(1)
#define RAM_SBE_STS_A_MI_H2C0_DAT_MASK BIT(0)
-#define EQDMA_CPM5_RAM_DBE_MSK_A_ADDR 0xF8
+#define EQDMA_CPM5_RAM_DBE_MSK_A_ADDR 0xF8
#define RAM_DBE_MSK_A_MASK GENMASK(31, 0)
-#define EQDMA_CPM5_RAM_DBE_STS_A_ADDR 0xFC
+#define EQDMA_CPM5_RAM_DBE_STS_A_ADDR 0xFC
#define RAM_DBE_STS_A_RC_RRQ_ODD_RAM_MASK BIT(31)
#define RAM_DBE_STS_A_PEND_FIFO_RAM_MASK BIT(30)
#define RAM_DBE_STS_A_PFCH_LL_RAM_MASK BIT(29)
@@ -232,10 +233,10 @@ struct xreg_info *eqdma_cpm5_config_regs_get(void);
#define RAM_DBE_STS_A_MI_H2C2_DAT_MASK BIT(2)
#define RAM_DBE_STS_A_MI_H2C1_DAT_MASK BIT(1)
#define RAM_DBE_STS_A_MI_H2C0_DAT_MASK BIT(0)
-#define EQDMA_CPM5_GLBL2_IDENTIFIER_ADDR 0x100
+#define EQDMA_CPM5_GLBL2_IDENTIFIER_ADDR 0x100
#define GLBL2_IDENTIFIER_MASK GENMASK(31, 8)
#define GLBL2_IDENTIFIER_VERSION_MASK GENMASK(7, 0)
-#define EQDMA_CPM5_GLBL2_CHANNEL_INST_ADDR 0x114
+#define EQDMA_CPM5_GLBL2_CHANNEL_INST_ADDR 0x114
#define GLBL2_CHANNEL_INST_RSVD_1_MASK GENMASK(31, 18)
#define GLBL2_CHANNEL_INST_C2H_ST_MASK BIT(17)
#define GLBL2_CHANNEL_INST_H2C_ST_MASK BIT(16)
@@ -243,7 +244,7 @@ struct xreg_info *eqdma_cpm5_config_regs_get(void);
#define GLBL2_CHANNEL_INST_C2H_ENG_MASK GENMASK(11, 8)
#define GLBL2_CHANNEL_INST_RSVD_3_MASK GENMASK(7, 4)
#define GLBL2_CHANNEL_INST_H2C_ENG_MASK GENMASK(3, 0)
-#define EQDMA_CPM5_GLBL2_CHANNEL_MDMA_ADDR 0x118
+#define EQDMA_CPM5_GLBL2_CHANNEL_MDMA_ADDR 0x118
#define GLBL2_CHANNEL_MDMA_RSVD_1_MASK GENMASK(31, 18)
#define GLBL2_CHANNEL_MDMA_C2H_ST_MASK BIT(17)
#define GLBL2_CHANNEL_MDMA_H2C_ST_MASK BIT(16)
@@ -251,7 +252,7 @@ struct xreg_info *eqdma_cpm5_config_regs_get(void);
#define GLBL2_CHANNEL_MDMA_C2H_ENG_MASK GENMASK(11, 8)
#define GLBL2_CHANNEL_MDMA_RSVD_3_MASK GENMASK(7, 4)
#define GLBL2_CHANNEL_MDMA_H2C_ENG_MASK GENMASK(3, 0)
-#define EQDMA_CPM5_GLBL2_CHANNEL_STRM_ADDR 0x11C
+#define EQDMA_CPM5_GLBL2_CHANNEL_STRM_ADDR 0x11C
#define GLBL2_CHANNEL_STRM_RSVD_1_MASK GENMASK(31, 18)
#define GLBL2_CHANNEL_STRM_C2H_ST_MASK BIT(17)
#define GLBL2_CHANNEL_STRM_H2C_ST_MASK BIT(16)
@@ -259,24 +260,24 @@ struct xreg_info *eqdma_cpm5_config_regs_get(void);
#define GLBL2_CHANNEL_STRM_C2H_ENG_MASK GENMASK(11, 8)
#define GLBL2_CHANNEL_STRM_RSVD_3_MASK GENMASK(7, 4)
#define GLBL2_CHANNEL_STRM_H2C_ENG_MASK GENMASK(3, 0)
-#define EQDMA_CPM5_GLBL2_CHANNEL_CAP_ADDR 0x120
+#define EQDMA_CPM5_GLBL2_CHANNEL_CAP_ADDR 0x120
#define GLBL2_CHANNEL_CAP_RSVD_1_MASK GENMASK(31, 12)
#define GLBL2_CHANNEL_CAP_MULTIQ_MAX_MASK GENMASK(11, 0)
-#define EQDMA_CPM5_GLBL2_CHANNEL_PASID_CAP_ADDR 0x128
+#define EQDMA_CPM5_GLBL2_CHANNEL_PASID_CAP_ADDR 0x128
#define GLBL2_CHANNEL_PASID_CAP_RSVD_1_MASK GENMASK(31, 2)
#define GLBL2_CHANNEL_PASID_CAP_BRIDGEEN_MASK BIT(1)
#define GLBL2_CHANNEL_PASID_CAP_DMAEN_MASK BIT(0)
-#define EQDMA_CPM5_GLBL2_SYSTEM_ID_ADDR 0x130
+#define EQDMA_CPM5_GLBL2_SYSTEM_ID_ADDR 0x130
#define GLBL2_SYSTEM_ID_RSVD_1_MASK GENMASK(31, 16)
#define GLBL2_SYSTEM_ID_MASK GENMASK(15, 0)
-#define EQDMA_CPM5_GLBL2_MISC_CAP_ADDR 0x134
+#define EQDMA_CPM5_GLBL2_MISC_CAP_ADDR 0x134
#define GLBL2_MISC_CAP_MASK GENMASK(31, 0)
-#define EQDMA_CPM5_GLBL2_DBG_PCIE_RQ0_ADDR 0x1B8
+#define EQDMA_CPM5_GLBL2_DBG_PCIE_RQ0_ADDR 0x1B8
#define GLBL2_PCIE_RQ0_NPH_AVL_MASK GENMASK(31, 20)
#define GLBL2_PCIE_RQ0_RCB_AVL_MASK GENMASK(19, 9)
#define GLBL2_PCIE_RQ0_SLV_RD_CREDS_MASK GENMASK(8, 2)
#define GLBL2_PCIE_RQ0_TAG_EP_MASK GENMASK(1, 0)
-#define EQDMA_CPM5_GLBL2_DBG_PCIE_RQ1_ADDR 0x1BC
+#define EQDMA_CPM5_GLBL2_DBG_PCIE_RQ1_ADDR 0x1BC
#define GLBL2_PCIE_RQ1_RSVD_1_MASK GENMASK(31, 21)
#define GLBL2_PCIE_RQ1_TAG_FL_MASK GENMASK(20, 19)
#define GLBL2_PCIE_RQ1_WTLP_HEADER_FIFO_FL_MASK BIT(18)
@@ -294,7 +295,7 @@ struct xreg_info *eqdma_cpm5_config_regs_get(void);
#define GLBL2_PCIE_RQ1_RREQ1_RDY_MASK BIT(2)
#define GLBL2_PCIE_RQ1_WTLP_REQ_MASK BIT(1)
#define GLBL2_PCIE_RQ1_WTLP_STRADDLE_MASK BIT(0)
-#define EQDMA_CPM5_GLBL2_DBG_AXIMM_WR0_ADDR 0x1C0
+#define EQDMA_CPM5_GLBL2_DBG_AXIMM_WR0_ADDR 0x1C0
#define GLBL2_AXIMM_WR0_RSVD_1_MASK GENMASK(31, 27)
#define GLBL2_AXIMM_WR0_WR_REQ_MASK BIT(26)
#define GLBL2_AXIMM_WR0_WR_CHN_MASK GENMASK(25, 23)
@@ -310,14 +311,14 @@ struct xreg_info *eqdma_cpm5_config_regs_get(void);
#define GLBL2_AXIMM_WR0_AWID_MASK GENMASK(4, 2)
#define GLBL2_AXIMM_WR0_AWVALID_MASK BIT(1)
#define GLBL2_AXIMM_WR0_AWREADY_MASK BIT(0)
-#define EQDMA_CPM5_GLBL2_DBG_AXIMM_WR1_ADDR 0x1C4
+#define EQDMA_CPM5_GLBL2_DBG_AXIMM_WR1_ADDR 0x1C4
#define GLBL2_AXIMM_WR1_RSVD_1_MASK GENMASK(31, 30)
#define GLBL2_AXIMM_WR1_BRSP_CNT4_MASK GENMASK(29, 24)
#define GLBL2_AXIMM_WR1_BRSP_CNT3_MASK GENMASK(23, 18)
#define GLBL2_AXIMM_WR1_BRSP_CNT2_MASK GENMASK(17, 12)
#define GLBL2_AXIMM_WR1_BRSP_CNT1_MASK GENMASK(11, 6)
#define GLBL2_AXIMM_WR1_BRSP_CNT0_MASK GENMASK(5, 0)
-#define EQDMA_CPM5_GLBL2_DBG_AXIMM_RD0_ADDR 0x1C8
+#define EQDMA_CPM5_GLBL2_DBG_AXIMM_RD0_ADDR 0x1C8
#define GLBL2_AXIMM_RD0_RSVD_1_MASK GENMASK(31, 23)
#define GLBL2_AXIMM_RD0_PND_CNT_MASK GENMASK(22, 17)
#define GLBL2_AXIMM_RD0_RD_REQ_MASK BIT(16)
@@ -329,14 +330,14 @@ struct xreg_info *eqdma_cpm5_config_regs_get(void);
#define GLBL2_AXIMM_RD0_ARID_MASK GENMASK(4, 2)
#define GLBL2_AXIMM_RD0_ARVALID_MASK BIT(1)
#define GLBL2_AXIMM_RD0_ARREADY_MASK BIT(0)
-#define EQDMA_CPM5_GLBL2_DBG_AXIMM_RD1_ADDR 0x1CC
+#define EQDMA_CPM5_GLBL2_DBG_AXIMM_RD1_ADDR 0x1CC
#define GLBL2_AXIMM_RD1_RSVD_1_MASK GENMASK(31, 30)
#define GLBL2_AXIMM_RD1_RRSP_CNT4_MASK GENMASK(29, 24)
#define GLBL2_AXIMM_RD1_RRSP_CNT3_MASK GENMASK(23, 18)
#define GLBL2_AXIMM_RD1_RRSP_CNT2_MASK GENMASK(17, 12)
#define GLBL2_AXIMM_RD1_RRSP_CNT1_MASK GENMASK(11, 6)
#define GLBL2_AXIMM_RD1_RRSP_CNT0_MASK GENMASK(5, 0)
-#define EQDMA_CPM5_GLBL2_DBG_FAB0_ADDR 0x1D0
+#define EQDMA_CPM5_GLBL2_DBG_FAB0_ADDR 0x1D0
#define GLBL2_FAB0_H2C_INB_CONV_IN_VLD_MASK BIT(31)
#define GLBL2_FAB0_H2C_INB_CONV_IN_RDY_MASK BIT(30)
#define GLBL2_FAB0_H2C_SEG_IN_VLD_MASK BIT(29)
@@ -357,7 +358,7 @@ struct xreg_info *eqdma_cpm5_config_regs_get(void);
#define GLBL2_FAB0_IRQ_IN_AFIFO_FULL_MASK BIT(2)
#define GLBL2_FAB0_IRQ_IN_AFIFO_EMPTY_MASK BIT(1)
#define GLBL2_FAB0_IMM_CRD_AFIFO_EMPTY_MASK BIT(0)
-#define EQDMA_CPM5_GLBL2_DBG_FAB1_ADDR 0x1D4
+#define EQDMA_CPM5_GLBL2_DBG_FAB1_ADDR 0x1D4
#define GLBL2_FAB1_BYP_OUT_CRDT_STAT_MASK GENMASK(31, 25)
#define GLBL2_FAB1_TM_DSC_STS_CRDT_STAT_MASK GENMASK(24, 18)
#define GLBL2_FAB1_C2H_CMN_AFIFO_FULL_MASK BIT(17)
@@ -370,66 +371,66 @@ struct xreg_info *eqdma_cpm5_config_regs_get(void);
#define GLBL2_FAB1_H2C_BYP_IN_AFIFO_FULL_MASK BIT(4)
#define GLBL2_FAB1_RSVD_4_MASK GENMASK(3, 1)
#define GLBL2_FAB1_H2C_BYP_IN_AFIFO_EMPTY_MASK BIT(0)
-#define EQDMA_CPM5_GLBL2_DBG_MATCH_SEL_ADDR 0x1F4
+#define EQDMA_CPM5_GLBL2_DBG_MATCH_SEL_ADDR 0x1F4
#define GLBL2_MATCH_SEL_RSV_MASK GENMASK(31, 18)
#define GLBL2_MATCH_SEL_CSR_SEL_MASK GENMASK(17, 13)
#define GLBL2_MATCH_SEL_CSR_EN_MASK BIT(12)
#define GLBL2_MATCH_SEL_ROTATE1_MASK GENMASK(11, 10)
#define GLBL2_MATCH_SEL_ROTATE0_MASK GENMASK(9, 8)
#define GLBL2_MATCH_SEL_SEL_MASK GENMASK(7, 0)
-#define EQDMA_CPM5_GLBL2_DBG_MATCH_MSK_ADDR 0x1F8
+#define EQDMA_CPM5_GLBL2_DBG_MATCH_MSK_ADDR 0x1F8
#define GLBL2_MATCH_MSK_MASK GENMASK(31, 0)
-#define EQDMA_CPM5_GLBL2_DBG_MATCH_PAT_ADDR 0x1FC
+#define EQDMA_CPM5_GLBL2_DBG_MATCH_PAT_ADDR 0x1FC
#define GLBL2_MATCH_PAT_PATTERN_MASK GENMASK(31, 0)
-#define EQDMA_CPM5_GLBL_RNG_SZ_1_ADDR 0x204
+#define EQDMA_CPM5_GLBL_RNG_SZ_1_ADDR 0x204
#define GLBL_RNG_SZ_1_RSVD_1_MASK GENMASK(31, 16)
#define GLBL_RNG_SZ_1_RING_SIZE_MASK GENMASK(15, 0)
-#define EQDMA_CPM5_GLBL_RNG_SZ_2_ADDR 0x208
+#define EQDMA_CPM5_GLBL_RNG_SZ_2_ADDR 0x208
#define GLBL_RNG_SZ_2_RSVD_1_MASK GENMASK(31, 16)
#define GLBL_RNG_SZ_2_RING_SIZE_MASK GENMASK(15, 0)
-#define EQDMA_CPM5_GLBL_RNG_SZ_3_ADDR 0x20C
+#define EQDMA_CPM5_GLBL_RNG_SZ_3_ADDR 0x20C
#define GLBL_RNG_SZ_3_RSVD_1_MASK GENMASK(31, 16)
#define GLBL_RNG_SZ_3_RING_SIZE_MASK GENMASK(15, 0)
-#define EQDMA_CPM5_GLBL_RNG_SZ_4_ADDR 0x210
+#define EQDMA_CPM5_GLBL_RNG_SZ_4_ADDR 0x210
#define GLBL_RNG_SZ_4_RSVD_1_MASK GENMASK(31, 16)
#define GLBL_RNG_SZ_4_RING_SIZE_MASK GENMASK(15, 0)
-#define EQDMA_CPM5_GLBL_RNG_SZ_5_ADDR 0x214
+#define EQDMA_CPM5_GLBL_RNG_SZ_5_ADDR 0x214
#define GLBL_RNG_SZ_5_RSVD_1_MASK GENMASK(31, 16)
#define GLBL_RNG_SZ_5_RING_SIZE_MASK GENMASK(15, 0)
-#define EQDMA_CPM5_GLBL_RNG_SZ_6_ADDR 0x218
+#define EQDMA_CPM5_GLBL_RNG_SZ_6_ADDR 0x218
#define GLBL_RNG_SZ_6_RSVD_1_MASK GENMASK(31, 16)
#define GLBL_RNG_SZ_6_RING_SIZE_MASK GENMASK(15, 0)
-#define EQDMA_CPM5_GLBL_RNG_SZ_7_ADDR 0x21C
+#define EQDMA_CPM5_GLBL_RNG_SZ_7_ADDR 0x21C
#define GLBL_RNG_SZ_7_RSVD_1_MASK GENMASK(31, 16)
#define GLBL_RNG_SZ_7_RING_SIZE_MASK GENMASK(15, 0)
-#define EQDMA_CPM5_GLBL_RNG_SZ_8_ADDR 0x220
+#define EQDMA_CPM5_GLBL_RNG_SZ_8_ADDR 0x220
#define GLBL_RNG_SZ_8_RSVD_1_MASK GENMASK(31, 16)
#define GLBL_RNG_SZ_8_RING_SIZE_MASK GENMASK(15, 0)
-#define EQDMA_CPM5_GLBL_RNG_SZ_9_ADDR 0x224
+#define EQDMA_CPM5_GLBL_RNG_SZ_9_ADDR 0x224
#define GLBL_RNG_SZ_9_RSVD_1_MASK GENMASK(31, 16)
#define GLBL_RNG_SZ_9_RING_SIZE_MASK GENMASK(15, 0)
-#define EQDMA_CPM5_GLBL_RNG_SZ_A_ADDR 0x228
+#define EQDMA_CPM5_GLBL_RNG_SZ_A_ADDR 0x228
#define GLBL_RNG_SZ_A_RSVD_1_MASK GENMASK(31, 16)
#define GLBL_RNG_SZ_A_RING_SIZE_MASK GENMASK(15, 0)
-#define EQDMA_CPM5_GLBL_RNG_SZ_B_ADDR 0x22C
+#define EQDMA_CPM5_GLBL_RNG_SZ_B_ADDR 0x22C
#define GLBL_RNG_SZ_B_RSVD_1_MASK GENMASK(31, 16)
#define GLBL_RNG_SZ_B_RING_SIZE_MASK GENMASK(15, 0)
-#define EQDMA_CPM5_GLBL_RNG_SZ_C_ADDR 0x230
+#define EQDMA_CPM5_GLBL_RNG_SZ_C_ADDR 0x230
#define GLBL_RNG_SZ_C_RSVD_1_MASK GENMASK(31, 16)
#define GLBL_RNG_SZ_C_RING_SIZE_MASK GENMASK(15, 0)
-#define EQDMA_CPM5_GLBL_RNG_SZ_D_ADDR 0x234
+#define EQDMA_CPM5_GLBL_RNG_SZ_D_ADDR 0x234
#define GLBL_RNG_SZ_D_RSVD_1_MASK GENMASK(31, 16)
#define GLBL_RNG_SZ_D_RING_SIZE_MASK GENMASK(15, 0)
-#define EQDMA_CPM5_GLBL_RNG_SZ_E_ADDR 0x238
+#define EQDMA_CPM5_GLBL_RNG_SZ_E_ADDR 0x238
#define GLBL_RNG_SZ_E_RSVD_1_MASK GENMASK(31, 16)
#define GLBL_RNG_SZ_E_RING_SIZE_MASK GENMASK(15, 0)
-#define EQDMA_CPM5_GLBL_RNG_SZ_F_ADDR 0x23C
+#define EQDMA_CPM5_GLBL_RNG_SZ_F_ADDR 0x23C
#define GLBL_RNG_SZ_F_RSVD_1_MASK GENMASK(31, 16)
#define GLBL_RNG_SZ_F_RING_SIZE_MASK GENMASK(15, 0)
-#define EQDMA_CPM5_GLBL_RNG_SZ_10_ADDR 0x240
+#define EQDMA_CPM5_GLBL_RNG_SZ_10_ADDR 0x240
#define GLBL_RNG_SZ_10_RSVD_1_MASK GENMASK(31, 16)
#define GLBL_RNG_SZ_10_RING_SIZE_MASK GENMASK(15, 0)
-#define EQDMA_CPM5_GLBL_ERR_STAT_ADDR 0x248
+#define EQDMA_CPM5_GLBL_ERR_STAT_ADDR 0x248
#define GLBL_ERR_STAT_RSVD_1_MASK GENMASK(31, 18)
#define GLBL_ERR_STAT_ERR_FAB_MASK BIT(17)
#define GLBL_ERR_STAT_ERR_H2C_ST_MASK BIT(16)
@@ -444,16 +445,16 @@ struct xreg_info *eqdma_cpm5_config_regs_get(void);
#define GLBL_ERR_STAT_ERR_DSC_MASK BIT(2)
#define GLBL_ERR_STAT_ERR_RAM_DBE_MASK BIT(1)
#define GLBL_ERR_STAT_ERR_RAM_SBE_MASK BIT(0)
-#define EQDMA_CPM5_GLBL_ERR_MASK_ADDR 0x24C
+#define EQDMA_CPM5_GLBL_ERR_MASK_ADDR 0x24C
#define GLBL_ERR_MASK GENMASK(31, 0)
-#define EQDMA_CPM5_GLBL_DSC_CFG_ADDR 0x250
+#define EQDMA_CPM5_GLBL_DSC_CFG_ADDR 0x250
#define GLBL_DSC_CFG_RSVD_1_MASK GENMASK(31, 10)
#define GLBL_DSC_CFG_UNC_OVR_COR_MASK BIT(9)
#define GLBL_DSC_CFG_CTXT_FER_DIS_MASK BIT(8)
#define GLBL_DSC_CFG_RSVD_2_MASK GENMASK(7, 6)
#define GLBL_DSC_CFG_MAXFETCH_MASK GENMASK(5, 3)
#define GLBL_DSC_CFG_WB_ACC_INT_MASK GENMASK(2, 0)
-#define EQDMA_CPM5_GLBL_DSC_ERR_STS_ADDR 0x254
+#define EQDMA_CPM5_GLBL_DSC_ERR_STS_ADDR 0x254
#define GLBL_DSC_ERR_STS_RSVD_1_MASK GENMASK(31, 26)
#define GLBL_DSC_ERR_STS_PORT_ID_MASK BIT(25)
#define GLBL_DSC_ERR_STS_SBE_MASK BIT(24)
@@ -472,20 +473,20 @@ struct xreg_info *eqdma_cpm5_config_regs_get(void);
#define GLBL_DSC_ERR_STS_BCNT_MASK BIT(3)
#define GLBL_DSC_ERR_STS_UR_CA_MASK BIT(2)
#define GLBL_DSC_ERR_STS_POISON_MASK BIT(1)
-#define EQDMA_CPM5_GLBL_DSC_ERR_MSK_ADDR 0x258
+#define EQDMA_CPM5_GLBL_DSC_ERR_MSK_ADDR 0x258
#define GLBL_DSC_ERR_MSK_MASK GENMASK(31, 0)
-#define EQDMA_CPM5_GLBL_DSC_ERR_LOG0_ADDR 0x25C
+#define EQDMA_CPM5_GLBL_DSC_ERR_LOG0_ADDR 0x25C
#define GLBL_DSC_ERR_LOG0_VALID_MASK BIT(31)
#define GLBL_DSC_ERR_LOG0_SEL_MASK BIT(30)
#define GLBL_DSC_ERR_LOG0_RSVD_1_MASK GENMASK(29, 13)
#define GLBL_DSC_ERR_LOG0_QID_MASK GENMASK(12, 0)
-#define EQDMA_CPM5_GLBL_DSC_ERR_LOG1_ADDR 0x260
+#define EQDMA_CPM5_GLBL_DSC_ERR_LOG1_ADDR 0x260
#define GLBL_DSC_ERR_LOG1_RSVD_1_MASK GENMASK(31, 28)
#define GLBL_DSC_ERR_LOG1_CIDX_MASK GENMASK(27, 12)
#define GLBL_DSC_ERR_LOG1_RSVD_2_MASK GENMASK(11, 9)
#define GLBL_DSC_ERR_LOG1_SUB_TYPE_MASK GENMASK(8, 5)
#define GLBL_DSC_ERR_LOG1_ERR_TYPE_MASK GENMASK(4, 0)
-#define EQDMA_CPM5_GLBL_TRQ_ERR_STS_ADDR 0x264
+#define EQDMA_CPM5_GLBL_TRQ_ERR_STS_ADDR 0x264
#define GLBL_TRQ_ERR_STS_RSVD_1_MASK GENMASK(31, 8)
#define GLBL_TRQ_ERR_STS_TCP_QSPC_TIMEOUT_MASK BIT(7)
#define GLBL_TRQ_ERR_STS_RSVD_2_MASK BIT(6)
@@ -495,14 +496,14 @@ struct xreg_info *eqdma_cpm5_config_regs_get(void);
#define GLBL_TRQ_ERR_STS_RSVD_3_MASK BIT(2)
#define GLBL_TRQ_ERR_STS_VF_ACCESS_ERR_MASK BIT(1)
#define GLBL_TRQ_ERR_STS_CSR_UNMAPPED_MASK BIT(0)
-#define EQDMA_CPM5_GLBL_TRQ_ERR_MSK_ADDR 0x268
+#define EQDMA_CPM5_GLBL_TRQ_ERR_MSK_ADDR 0x268
#define GLBL_TRQ_ERR_MSK_MASK GENMASK(31, 0)
-#define EQDMA_CPM5_GLBL_TRQ_ERR_LOG_ADDR 0x26C
+#define EQDMA_CPM5_GLBL_TRQ_ERR_LOG_ADDR 0x26C
#define GLBL_TRQ_ERR_LOG_SRC_MASK BIT(31)
#define GLBL_TRQ_ERR_LOG_TARGET_MASK GENMASK(30, 27)
#define GLBL_TRQ_ERR_LOG_FUNC_MASK GENMASK(26, 17)
#define GLBL_TRQ_ERR_LOG_ADDRESS_MASK GENMASK(16, 0)
-#define EQDMA_CPM5_GLBL_DSC_DBG_DAT0_ADDR 0x270
+#define EQDMA_CPM5_GLBL_DSC_DBG_DAT0_ADDR 0x270
#define GLBL_DSC_DAT0_RSVD_1_MASK GENMASK(31, 30)
#define GLBL_DSC_DAT0_CTXT_ARB_DIR_MASK BIT(29)
#define GLBL_DSC_DAT0_CTXT_ARB_QID_MASK GENMASK(28, 17)
@@ -514,23 +515,23 @@ struct xreg_info *eqdma_cpm5_config_regs_get(void);
#define GLBL_DSC_DAT0_RRQ_FIFO_SPC_STALL_MASK GENMASK(5, 4)
#define GLBL_DSC_DAT0_FAB_MRKR_RSP_STALL_MASK GENMASK(3, 2)
#define GLBL_DSC_DAT0_DSC_OUT_STALL_MASK GENMASK(1, 0)
-#define EQDMA_CPM5_GLBL_DSC_DBG_DAT1_ADDR 0x274
+#define EQDMA_CPM5_GLBL_DSC_DBG_DAT1_ADDR 0x274
#define GLBL_DSC_DAT1_RSVD_1_MASK GENMASK(31, 28)
#define GLBL_DSC_DAT1_EVT_SPC_C2H_MASK GENMASK(27, 22)
#define GLBL_DSC_DAT1_EVT_SP_H2C_MASK GENMASK(21, 16)
#define GLBL_DSC_DAT1_DSC_SPC_C2H_MASK GENMASK(15, 8)
#define GLBL_DSC_DAT1_DSC_SPC_H2C_MASK GENMASK(7, 0)
-#define EQDMA_CPM5_GLBL_DSC_DBG_CTL_ADDR 0x278
+#define EQDMA_CPM5_GLBL_DSC_DBG_CTL_ADDR 0x278
#define GLBL_DSC_CTL_RSVD_1_MASK GENMASK(31, 3)
#define GLBL_DSC_CTL_SELECT_MASK GENMASK(2, 0)
-#define EQDMA_CPM5_GLBL_DSC_ERR_LOG2_ADDR 0x27c
+#define EQDMA_CPM5_GLBL_DSC_ERR_LOG2_ADDR 0x27c
#define GLBL_DSC_ERR_LOG2_OLD_PIDX_MASK GENMASK(31, 16)
#define GLBL_DSC_ERR_LOG2_NEW_PIDX_MASK GENMASK(15, 0)
-#define EQDMA_CPM5_GLBL_GLBL_INTERRUPT_CFG_ADDR 0x2c4
+#define EQDMA_CPM5_GLBL_GLBL_INTERRUPT_CFG_ADDR 0x2c4
#define GLBL_GLBL_INTERRUPT_CFG_RSVD_1_MASK GENMASK(31, 2)
#define GLBL_GLBL_INTERRUPT_CFG_LGCY_INTR_PENDING_MASK BIT(1)
#define GLBL_GLBL_INTERRUPT_CFG_EN_LGCY_INTR_MASK BIT(0)
-#define EQDMA_CPM5_GLBL_VCH_HOST_PROFILE_ADDR 0x2c8
+#define EQDMA_CPM5_GLBL_VCH_HOST_PROFILE_ADDR 0x2c8
#define GLBL_VCH_HOST_PROFILE_RSVD_1_MASK GENMASK(31, 28)
#define GLBL_VCH_HOST_PROFILE_2C_MM_MASK GENMASK(27, 24)
#define GLBL_VCH_HOST_PROFILE_2C_ST_MASK GENMASK(23, 20)
@@ -539,68 +540,63 @@ struct xreg_info *eqdma_cpm5_config_regs_get(void);
#define GLBL_VCH_HOST_PROFILE_VCH_INT_AGGR_MASK GENMASK(11, 8)
#define GLBL_VCH_HOST_PROFILE_VCH_CMPT_MASK GENMASK(7, 4)
#define GLBL_VCH_HOST_PROFILE_VCH_C2H_PLD_MASK GENMASK(3, 0)
-#define EQDMA_CPM5_GLBL_BRIDGE_HOST_PROFILE_ADDR 0x308
+#define EQDMA_CPM5_GLBL_BRIDGE_HOST_PROFILE_ADDR 0x308
#define GLBL_BRIDGE_HOST_PROFILE_RSVD_1_MASK GENMASK(31, 4)
#define GLBL_BRIDGE_HOST_PROFILE_BDGID_MASK GENMASK(3, 0)
-#define EQDMA_CPM5_AXIMM_IRQ_DEST_ADDR_ADDR 0x30c
+#define EQDMA_CPM5_AXIMM_IRQ_DEST_ADDR_ADDR 0x30c
#define AXIMM_IRQ_DEST_ADDR_ADDR_MASK GENMASK(31, 0)
-#define EQDMA_CPM5_FAB_ERR_LOG_ADDR 0x314
+#define EQDMA_CPM5_FAB_ERR_LOG_ADDR 0x314
#define FAB_ERR_LOG_RSVD_1_MASK GENMASK(31, 7)
#define FAB_ERR_LOG_SRC_MASK GENMASK(6, 0)
-#define EQDMA_CPM5_GLBL_REQ_ERR_STS_ADDR 0x318
-#define GLBL_REQ_ERR_STS_RSVD_1_MASK GENMASK(31, 11)
-#define GLBL_REQ_ERR_STS_RC_DISCONTINUE_MASK BIT(10)
-#define GLBL_REQ_ERR_STS_RC_PRTY_MASK BIT(9)
-#define GLBL_REQ_ERR_STS_RC_FLR_MASK BIT(8)
-#define GLBL_REQ_ERR_STS_RC_TIMEOUT_MASK BIT(7)
-#define GLBL_REQ_ERR_STS_RC_INV_BCNT_MASK BIT(6)
-#define GLBL_REQ_ERR_STS_RC_INV_TAG_MASK BIT(5)
-#define GLBL_REQ_ERR_STS_RC_START_ADDR_MISMCH_MASK BIT(4)
-#define GLBL_REQ_ERR_STS_RC_RID_TC_ATTR_MISMCH_MASK BIT(3)
-#define GLBL_REQ_ERR_STS_RC_NO_DATA_MASK BIT(2)
-#define GLBL_REQ_ERR_STS_RC_UR_CA_CRS_MASK BIT(1)
-#define GLBL_REQ_ERR_STS_RC_POISONED_MASK BIT(0)
-#define EQDMA_CPM5_GLBL_REQ_ERR_MSK_ADDR 0x31C
-#define GLBL_REQ_ERR_MSK_MASK GENMASK(31, 0)
-#define EQDMA_CPM5_IND_CTXT_DATA_ADDR 0x804
+#define EQDMA_CPM5_IND_CTXT_DATA_ADDR 0x804
#define IND_CTXT_DATA_DATA_MASK GENMASK(31, 0)
-#define EQDMA_CPM5_IND_CTXT_MASK_ADDR 0x824
+#define EQDMA_CPM5_IND_CTXT_MASK_ADDR 0x824
#define IND_CTXT_MASK GENMASK(31, 0)
-#define EQDMA_CPM5_IND_CTXT_CMD_ADDR 0x844
+#define EQDMA_CPM5_IND_CTXT_CMD_ADDR 0x844
#define IND_CTXT_CMD_RSVD_1_MASK GENMASK(31, 20)
#define IND_CTXT_CMD_QID_MASK GENMASK(19, 7)
#define IND_CTXT_CMD_OP_MASK GENMASK(6, 5)
#define IND_CTXT_CMD_SEL_MASK GENMASK(4, 1)
#define IND_CTXT_CMD_BUSY_MASK BIT(0)
-#define EQDMA_CPM5_C2H_TIMER_CNT_ADDR 0xA00
+#define EQDMA_CPM5_C2H_TIMER_CNT_ADDR 0xA00
#define C2H_TIMER_CNT_RSVD_1_MASK GENMASK(31, 16)
#define C2H_TIMER_CNT_MASK GENMASK(15, 0)
-#define EQDMA_CPM5_C2H_CNT_TH_ADDR 0xA40
+#define EQDMA_CPM5_C2H_CNT_TH_ADDR 0xA40
#define C2H_CNT_TH_RSVD_1_MASK GENMASK(31, 16)
#define C2H_CNT_TH_THESHOLD_CNT_MASK GENMASK(15, 0)
-#define EQDMA_CPM5_C2H_STAT_S_AXIS_C2H_ACCEPTED_ADDR 0xA88
-#define C2H_STAT_S_AXIS_C2H_ACCEPTED_MASK GENMASK(31, 0)
-#define EQDMA_CPM5_C2H_STAT_S_AXIS_WRB_ACCEPTED_ADDR 0xA8C
-#define C2H_STAT_S_AXIS_WRB_ACCEPTED_MASK GENMASK(31, 0)
-#define EQDMA_CPM5_C2H_STAT_DESC_RSP_PKT_ACCEPTED_ADDR 0xA90
-#define C2H_STAT_DESC_RSP_PKT_ACCEPTED_D_MASK GENMASK(31, 0)
-#define EQDMA_CPM5_C2H_STAT_AXIS_PKG_CMP_ADDR 0xA94
-#define C2H_STAT_AXIS_PKG_CMP_MASK GENMASK(31, 0)
-#define EQDMA_CPM5_C2H_STAT_DESC_RSP_ACCEPTED_ADDR 0xA98
-#define C2H_STAT_DESC_RSP_ACCEPTED_D_MASK GENMASK(31, 0)
-#define EQDMA_CPM5_C2H_STAT_DESC_RSP_CMP_ADDR 0xA9C
-#define C2H_STAT_DESC_RSP_CMP_D_MASK GENMASK(31, 0)
-#define EQDMA_CPM5_C2H_STAT_WRQ_OUT_ADDR 0xAA0
-#define C2H_STAT_WRQ_OUT_MASK GENMASK(31, 0)
-#define EQDMA_CPM5_C2H_STAT_WPL_REN_ACCEPTED_ADDR 0xAA4
-#define C2H_STAT_WPL_REN_ACCEPTED_MASK GENMASK(31, 0)
-#define EQDMA_CPM5_C2H_STAT_TOTAL_WRQ_LEN_ADDR 0xAA8
-#define C2H_STAT_TOTAL_WRQ_LEN_MASK GENMASK(31, 0)
-#define EQDMA_CPM5_C2H_STAT_TOTAL_WPL_LEN_ADDR 0xAAC
-#define C2H_STAT_TOTAL_WPL_LEN_MASK GENMASK(31, 0)
-#define EQDMA_CPM5_C2H_BUF_SZ_ADDR 0xAB0
+#define EQDMA_CPM5_C2H_STAT_S_AXIS_C2H_ACCEPTED_ADDR 0xA88
+#define C2H_STAT_S_AXIS_C2H_ACCEPTED_RSVD_1_MASK GENMASK(31, 18)
+#define C2H_STAT_S_AXIS_C2H_ACCEPTED_MASK GENMASK(17, 0)
+#define EQDMA_CPM5_C2H_STAT_S_AXIS_WRB_ACCEPTED_ADDR 0xA8C
+#define C2H_STAT_S_AXIS_WRB_ACCEPTED_RSVD_1_MASK GENMASK(31, 18)
+#define C2H_STAT_S_AXIS_WRB_ACCEPTED_MASK GENMASK(17, 0)
+#define EQDMA_CPM5_C2H_STAT_DESC_RSP_PKT_ACCEPTED_ADDR 0xA90
+#define C2H_STAT_DESC_RSP_PKT_ACCEPTED_RSVD_1_MASK GENMASK(31, 18)
+#define C2H_STAT_DESC_RSP_PKT_ACCEPTED_D_MASK GENMASK(17, 0)
+#define EQDMA_CPM5_C2H_STAT_AXIS_PKG_CMP_ADDR 0xA94
+#define C2H_STAT_AXIS_PKG_CMP_RSVD_1_MASK GENMASK(31, 18)
+#define C2H_STAT_AXIS_PKG_CMP_MASK GENMASK(17, 0)
+#define EQDMA_CPM5_C2H_STAT_DESC_RSP_ACCEPTED_ADDR 0xA98
+#define C2H_STAT_DESC_RSP_ACCEPTED_RSVD_1_MASK GENMASK(31, 18)
+#define C2H_STAT_DESC_RSP_ACCEPTED_D_MASK GENMASK(17, 0)
+#define EQDMA_CPM5_C2H_STAT_DESC_RSP_CMP_ADDR 0xA9C
+#define C2H_STAT_DESC_RSP_CMP_RSVD_1_MASK GENMASK(31, 18)
+#define C2H_STAT_DESC_RSP_CMP_D_MASK GENMASK(17, 0)
+#define EQDMA_CPM5_C2H_STAT_WRQ_OUT_ADDR 0xAA0
+#define C2H_STAT_WRQ_OUT_RSVD_1_MASK GENMASK(31, 18)
+#define C2H_STAT_WRQ_OUT_MASK GENMASK(17, 0)
+#define EQDMA_CPM5_C2H_STAT_WPL_REN_ACCEPTED_ADDR 0xAA4
+#define C2H_STAT_WPL_REN_ACCEPTED_RSVD_1_MASK GENMASK(31, 18)
+#define C2H_STAT_WPL_REN_ACCEPTED_MASK GENMASK(17, 0)
+#define EQDMA_CPM5_C2H_STAT_TOTAL_WRQ_LEN_ADDR 0xAA8
+#define C2H_STAT_TOTAL_WRQ_LEN_RSVD_1_MASK GENMASK(31, 18)
+#define C2H_STAT_TOTAL_WRQ_LEN_MASK GENMASK(17, 0)
+#define EQDMA_CPM5_C2H_STAT_TOTAL_WPL_LEN_ADDR 0xAAC
+#define C2H_STAT_TOTAL_WPL_LEN_RSVD_1_MASK GENMASK(31, 18)
+#define C2H_STAT_TOTAL_WPL_LEN_MASK GENMASK(17, 0)
+#define EQDMA_CPM5_C2H_BUF_SZ_ADDR 0xAB0
#define C2H_BUF_SZ_IZE_MASK GENMASK(31, 0)
-#define EQDMA_CPM5_C2H_ERR_STAT_ADDR 0xAF0
+#define EQDMA_CPM5_C2H_ERR_STAT_ADDR 0xAF0
#define C2H_ERR_STAT_RSVD_1_MASK GENMASK(31, 21)
#define C2H_ERR_STAT_WRB_PORT_ID_ERR_MASK BIT(20)
#define C2H_ERR_STAT_HDR_PAR_ERR_MASK BIT(19)
@@ -623,9 +619,9 @@ struct xreg_info *eqdma_cpm5_config_regs_get(void);
#define C2H_ERR_STAT_SH_CMPT_DSC_ERR_MASK BIT(2)
#define C2H_ERR_STAT_LEN_MISMATCH_MASK BIT(1)
#define C2H_ERR_STAT_MTY_MISMATCH_MASK BIT(0)
-#define EQDMA_CPM5_C2H_ERR_MASK_ADDR 0xAF4
+#define EQDMA_CPM5_C2H_ERR_MASK_ADDR 0xAF4
#define C2H_ERR_EN_MASK GENMASK(31, 0)
-#define EQDMA_CPM5_C2H_FATAL_ERR_STAT_ADDR 0xAF8
+#define EQDMA_CPM5_C2H_FATAL_ERR_STAT_ADDR 0xAF8
#define C2H_FATAL_ERR_STAT_RSVD_1_MASK GENMASK(31, 21)
#define C2H_FATAL_ERR_STAT_HDR_ECC_UNC_ERR_MASK BIT(20)
#define C2H_FATAL_ERR_STAT_AVL_RING_FIFO_RAM_RDBE_MASK BIT(19)
@@ -645,13 +641,13 @@ struct xreg_info *eqdma_cpm5_config_regs_get(void);
#define C2H_FATAL_ERR_STAT_RESERVED1_MASK BIT(2)
#define C2H_FATAL_ERR_STAT_LEN_MISMATCH_MASK BIT(1)
#define C2H_FATAL_ERR_STAT_MTY_MISMATCH_MASK BIT(0)
-#define EQDMA_CPM5_C2H_FATAL_ERR_MASK_ADDR 0xAFC
+#define EQDMA_CPM5_C2H_FATAL_ERR_MASK_ADDR 0xAFC
#define C2H_FATAL_ERR_C2HEN_MASK GENMASK(31, 0)
-#define EQDMA_CPM5_C2H_FATAL_ERR_ENABLE_ADDR 0xB00
+#define EQDMA_CPM5_C2H_FATAL_ERR_ENABLE_ADDR 0xB00
#define C2H_FATAL_ERR_ENABLE_RSVD_1_MASK GENMASK(31, 2)
#define C2H_FATAL_ERR_ENABLE_WPL_PAR_INV_MASK BIT(1)
#define C2H_FATAL_ERR_ENABLE_WRQ_DIS_MASK BIT(0)
-#define EQDMA_CPM5_GLBL_ERR_INT_ADDR 0xB04
+#define EQDMA_CPM5_GLBL_ERR_INT_ADDR 0xB04
#define GLBL_ERR_INT_RSVD_1_MASK GENMASK(31, 30)
#define GLBL_ERR_INT_HOST_ID_MASK GENMASK(29, 26)
#define GLBL_ERR_INT_DIS_INTR_ON_VF_MASK BIT(25)
@@ -659,28 +655,31 @@ struct xreg_info *eqdma_cpm5_config_regs_get(void);
#define GLBL_ERR_INT_EN_COAL_MASK BIT(23)
#define GLBL_ERR_INT_VEC_MASK GENMASK(22, 12)
#define GLBL_ERR_INT_FUNC_MASK GENMASK(11, 0)
-#define EQDMA_CPM5_C2H_PFCH_CFG_ADDR 0xB08
+#define EQDMA_CPM5_C2H_PFCH_CFG_ADDR 0xB08
#define C2H_PFCH_CFG_EVTFL_TH_MASK GENMASK(31, 16)
#define C2H_PFCH_CFG_FL_TH_MASK GENMASK(15, 0)
-#define EQDMA_CPM5_C2H_PFCH_CFG_1_ADDR 0xA80
+#define EQDMA_CPM5_C2H_PFCH_CFG_1_ADDR 0xA80
#define C2H_PFCH_CFG_1_EVT_QCNT_TH_MASK GENMASK(31, 16)
#define C2H_PFCH_CFG_1_QCNT_MASK GENMASK(15, 0)
-#define EQDMA_CPM5_C2H_PFCH_CFG_2_ADDR 0xA84
+#define EQDMA_CPM5_C2H_PFCH_CFG_2_ADDR 0xA84
#define C2H_PFCH_CFG_2_FENCE_MASK BIT(31)
#define C2H_PFCH_CFG_2_RSVD_MASK GENMASK(30, 29)
#define C2H_PFCH_CFG_2_VAR_DESC_NO_DROP_MASK BIT(28)
#define C2H_PFCH_CFG_2_LL_SZ_TH_MASK GENMASK(27, 12)
#define C2H_PFCH_CFG_2_VAR_DESC_NUM_MASK GENMASK(11, 6)
#define C2H_PFCH_CFG_2_NUM_MASK GENMASK(5, 0)
-#define EQDMA_CPM5_C2H_INT_TIMER_TICK_ADDR 0xB0C
+#define EQDMA_CPM5_C2H_INT_TIMER_TICK_ADDR 0xB0C
#define C2H_INT_TIMER_TICK_MASK GENMASK(31, 0)
-#define EQDMA_CPM5_C2H_STAT_DESC_RSP_DROP_ACCEPTED_ADDR 0xB10
-#define C2H_STAT_DESC_RSP_DROP_ACCEPTED_D_MASK GENMASK(31, 0)
-#define EQDMA_CPM5_C2H_STAT_DESC_RSP_ERR_ACCEPTED_ADDR 0xB14
-#define C2H_STAT_DESC_RSP_ERR_ACCEPTED_D_MASK GENMASK(31, 0)
-#define EQDMA_CPM5_C2H_STAT_DESC_REQ_ADDR 0xB18
-#define C2H_STAT_DESC_REQ_MASK GENMASK(31, 0)
-#define EQDMA_CPM5_C2H_STAT_DBG_DMA_ENG_0_ADDR 0xB1C
+#define EQDMA_CPM5_C2H_STAT_DESC_RSP_DROP_ACCEPTED_ADDR 0xB10
+#define C2H_STAT_DESC_RSP_DROP_ACCEPTED_RSVD_1_MASK GENMASK(31, 18)
+#define C2H_STAT_DESC_RSP_DROP_ACCEPTED_D_MASK GENMASK(17, 0)
+#define EQDMA_CPM5_C2H_STAT_DESC_RSP_ERR_ACCEPTED_ADDR 0xB14
+#define C2H_STAT_DESC_RSP_ERR_ACCEPTED_RSVD_1_MASK GENMASK(31, 18)
+#define C2H_STAT_DESC_RSP_ERR_ACCEPTED_D_MASK GENMASK(17, 0)
+#define EQDMA_CPM5_C2H_STAT_DESC_REQ_ADDR 0xB18
+#define C2H_STAT_DESC_REQ_RSVD_1_MASK GENMASK(31, 18)
+#define C2H_STAT_DESC_REQ_MASK GENMASK(17, 0)
+#define EQDMA_CPM5_C2H_STAT_DBG_DMA_ENG_0_ADDR 0xB1C
#define C2H_STAT_DMA_ENG_0_S_AXIS_C2H_TVALID_MASK BIT(31)
#define C2H_STAT_DMA_ENG_0_S_AXIS_C2H_TREADY_MASK BIT(30)
#define C2H_STAT_DMA_ENG_0_S_AXIS_WRB_TVALID_MASK GENMASK(29, 27)
@@ -693,17 +692,17 @@ struct xreg_info *eqdma_cpm5_config_regs_get(void);
#define C2H_STAT_DMA_ENG_0_WRB_FIFO_OUT_CNT_MASK GENMASK(7, 5)
#define C2H_STAT_DMA_ENG_0_WRB_SM_CS_MASK BIT(4)
#define C2H_STAT_DMA_ENG_0_MAIN_SM_CS_MASK GENMASK(3, 0)
-#define EQDMA_CPM5_C2H_STAT_DBG_DMA_ENG_1_ADDR 0xB20
+#define EQDMA_CPM5_C2H_STAT_DBG_DMA_ENG_1_ADDR 0xB20
#define C2H_STAT_DMA_ENG_1_RSVD_1_MASK GENMASK(31, 29)
#define C2H_STAT_DMA_ENG_1_QID_FIFO_OUT_CNT_MASK GENMASK(28, 18)
#define C2H_STAT_DMA_ENG_1_PLD_FIFO_OUT_CNT_MASK GENMASK(17, 7)
#define C2H_STAT_DMA_ENG_1_PLD_ST_FIFO_CNT_MASK GENMASK(6, 0)
-#define EQDMA_CPM5_C2H_STAT_DBG_DMA_ENG_2_ADDR 0xB24
+#define EQDMA_CPM5_C2H_STAT_DBG_DMA_ENG_2_ADDR 0xB24
#define C2H_STAT_DMA_ENG_2_RSVD_1_MASK GENMASK(31, 29)
#define C2H_STAT_DMA_ENG_2_QID_FIFO_OUT_CNT_MASK GENMASK(28, 18)
#define C2H_STAT_DMA_ENG_2_PLD_FIFO_OUT_CNT_MASK GENMASK(17, 7)
#define C2H_STAT_DMA_ENG_2_PLD_ST_FIFO_CNT_MASK GENMASK(6, 0)
-#define EQDMA_CPM5_C2H_STAT_DBG_DMA_ENG_3_ADDR 0xB28
+#define EQDMA_CPM5_C2H_STAT_DBG_DMA_ENG_3_ADDR 0xB28
#define C2H_STAT_DMA_ENG_3_RSVD_1_MASK GENMASK(31, 24)
#define C2H_STAT_DMA_ENG_3_WRQ_FIFO_OUT_CNT_MASK GENMASK(23, 19)
#define C2H_STAT_DMA_ENG_3_QID_FIFO_OUT_VLD_MASK BIT(18)
@@ -725,84 +724,84 @@ struct xreg_info *eqdma_cpm5_config_regs_get(void);
#define C2H_STAT_DMA_ENG_3_WRQ_PACKET_PRE_EOR_MASK BIT(2)
#define C2H_STAT_DMA_ENG_3_WCP_FIFO_IN_RDY_MASK BIT(1)
#define C2H_STAT_DMA_ENG_3_PLD_ST_FIFO_IN_RDY_MASK BIT(0)
-#define EQDMA_CPM5_C2H_DBG_PFCH_ERR_CTXT_ADDR 0xB2C
+#define EQDMA_CPM5_C2H_DBG_PFCH_ERR_CTXT_ADDR 0xB2C
#define C2H_PFCH_ERR_CTXT_RSVD_1_MASK GENMASK(31, 14)
#define C2H_PFCH_ERR_CTXT_ERR_STAT_MASK BIT(13)
#define C2H_PFCH_ERR_CTXT_CMD_WR_MASK BIT(12)
#define C2H_PFCH_ERR_CTXT_QID_MASK GENMASK(11, 1)
#define C2H_PFCH_ERR_CTXT_DONE_MASK BIT(0)
-#define EQDMA_CPM5_C2H_FIRST_ERR_QID_ADDR 0xB30
+#define EQDMA_CPM5_C2H_FIRST_ERR_QID_ADDR 0xB30
#define C2H_FIRST_ERR_QID_RSVD_1_MASK GENMASK(31, 21)
#define C2H_FIRST_ERR_QID_ERR_TYPE_MASK GENMASK(20, 16)
#define C2H_FIRST_ERR_QID_RSVD_MASK GENMASK(15, 13)
#define C2H_FIRST_ERR_QID_QID_MASK GENMASK(12, 0)
-#define EQDMA_CPM5_STAT_NUM_WRB_IN_ADDR 0xB34
+#define EQDMA_CPM5_STAT_NUM_WRB_IN_ADDR 0xB34
#define STAT_NUM_WRB_IN_RSVD_1_MASK GENMASK(31, 16)
#define STAT_NUM_WRB_IN_WRB_CNT_MASK GENMASK(15, 0)
-#define EQDMA_CPM5_STAT_NUM_WRB_OUT_ADDR 0xB38
+#define EQDMA_CPM5_STAT_NUM_WRB_OUT_ADDR 0xB38
#define STAT_NUM_WRB_OUT_RSVD_1_MASK GENMASK(31, 16)
#define STAT_NUM_WRB_OUT_WRB_CNT_MASK GENMASK(15, 0)
-#define EQDMA_CPM5_STAT_NUM_WRB_DRP_ADDR 0xB3C
+#define EQDMA_CPM5_STAT_NUM_WRB_DRP_ADDR 0xB3C
#define STAT_NUM_WRB_DRP_RSVD_1_MASK GENMASK(31, 16)
#define STAT_NUM_WRB_DRP_WRB_CNT_MASK GENMASK(15, 0)
-#define EQDMA_CPM5_STAT_NUM_STAT_DESC_OUT_ADDR 0xB40
+#define EQDMA_CPM5_STAT_NUM_STAT_DESC_OUT_ADDR 0xB40
#define STAT_NUM_STAT_DESC_OUT_RSVD_1_MASK GENMASK(31, 16)
#define STAT_NUM_STAT_DESC_OUT_CNT_MASK GENMASK(15, 0)
-#define EQDMA_CPM5_STAT_NUM_DSC_CRDT_SENT_ADDR 0xB44
+#define EQDMA_CPM5_STAT_NUM_DSC_CRDT_SENT_ADDR 0xB44
#define STAT_NUM_DSC_CRDT_SENT_RSVD_1_MASK GENMASK(31, 16)
#define STAT_NUM_DSC_CRDT_SENT_CNT_MASK GENMASK(15, 0)
-#define EQDMA_CPM5_STAT_NUM_FCH_DSC_RCVD_ADDR 0xB48
+#define EQDMA_CPM5_STAT_NUM_FCH_DSC_RCVD_ADDR 0xB48
#define STAT_NUM_FCH_DSC_RCVD_RSVD_1_MASK GENMASK(31, 16)
#define STAT_NUM_FCH_DSC_RCVD_DSC_CNT_MASK GENMASK(15, 0)
-#define EQDMA_CPM5_STAT_NUM_BYP_DSC_RCVD_ADDR 0xB4C
+#define EQDMA_CPM5_STAT_NUM_BYP_DSC_RCVD_ADDR 0xB4C
#define STAT_NUM_BYP_DSC_RCVD_RSVD_1_MASK GENMASK(31, 11)
#define STAT_NUM_BYP_DSC_RCVD_DSC_CNT_MASK GENMASK(10, 0)
-#define EQDMA_CPM5_C2H_WRB_COAL_CFG_ADDR 0xB50
+#define EQDMA_CPM5_C2H_WRB_COAL_CFG_ADDR 0xB50
#define C2H_WRB_COAL_CFG_MAX_BUF_SZ_MASK GENMASK(31, 26)
#define C2H_WRB_COAL_CFG_TICK_VAL_MASK GENMASK(25, 14)
#define C2H_WRB_COAL_CFG_TICK_CNT_MASK GENMASK(13, 2)
#define C2H_WRB_COAL_CFG_SET_GLB_FLUSH_MASK BIT(1)
#define C2H_WRB_COAL_CFG_DONE_GLB_FLUSH_MASK BIT(0)
-#define EQDMA_CPM5_C2H_INTR_H2C_REQ_ADDR 0xB54
+#define EQDMA_CPM5_C2H_INTR_H2C_REQ_ADDR 0xB54
#define C2H_INTR_H2C_REQ_RSVD_1_MASK GENMASK(31, 18)
#define C2H_INTR_H2C_REQ_CNT_MASK GENMASK(17, 0)
-#define EQDMA_CPM5_C2H_INTR_C2H_MM_REQ_ADDR 0xB58
+#define EQDMA_CPM5_C2H_INTR_C2H_MM_REQ_ADDR 0xB58
#define C2H_INTR_C2H_MM_REQ_RSVD_1_MASK GENMASK(31, 18)
#define C2H_INTR_C2H_MM_REQ_CNT_MASK GENMASK(17, 0)
-#define EQDMA_CPM5_C2H_INTR_ERR_INT_REQ_ADDR 0xB5C
+#define EQDMA_CPM5_C2H_INTR_ERR_INT_REQ_ADDR 0xB5C
#define C2H_INTR_ERR_INT_REQ_RSVD_1_MASK GENMASK(31, 18)
#define C2H_INTR_ERR_INT_REQ_CNT_MASK GENMASK(17, 0)
-#define EQDMA_CPM5_C2H_INTR_C2H_ST_REQ_ADDR 0xB60
+#define EQDMA_CPM5_C2H_INTR_C2H_ST_REQ_ADDR 0xB60
#define C2H_INTR_C2H_ST_REQ_RSVD_1_MASK GENMASK(31, 18)
#define C2H_INTR_C2H_ST_REQ_CNT_MASK GENMASK(17, 0)
-#define EQDMA_CPM5_C2H_INTR_H2C_ERR_C2H_MM_MSIX_ACK_ADDR 0xB64
+#define EQDMA_CPM5_C2H_INTR_H2C_ERR_C2H_MM_MSIX_ACK_ADDR 0xB64
#define C2H_INTR_H2C_ERR_C2H_MM_MSIX_ACK_RSVD_1_MASK GENMASK(31, 18)
#define C2H_INTR_H2C_ERR_C2H_MM_MSIX_ACK_CNT_MASK GENMASK(17, 0)
-#define EQDMA_CPM5_C2H_INTR_H2C_ERR_C2H_MM_MSIX_FAIL_ADDR 0xB68
+#define EQDMA_CPM5_C2H_INTR_H2C_ERR_C2H_MM_MSIX_FAIL_ADDR 0xB68
#define C2H_INTR_H2C_ERR_C2H_MM_MSIX_FAIL_RSVD_1_MASK GENMASK(31, 18)
#define C2H_INTR_H2C_ERR_C2H_MM_MSIX_FAIL_CNT_MASK GENMASK(17, 0)
-#define EQDMA_CPM5_C2H_INTR_H2C_ERR_C2H_MM_MSIX_NO_MSIX_ADDR 0xB6C
+#define EQDMA_CPM5_C2H_INTR_H2C_ERR_C2H_MM_MSIX_NO_MSIX_ADDR 0xB6C
#define C2H_INTR_H2C_ERR_C2H_MM_MSIX_NO_MSIX_RSVD_1_MASK GENMASK(31, 18)
#define C2H_INTR_H2C_ERR_C2H_MM_MSIX_NO_MSIX_CNT_MASK GENMASK(17, 0)
-#define EQDMA_CPM5_C2H_INTR_H2C_ERR_C2H_MM_CTXT_INVAL_ADDR 0xB70
+#define EQDMA_CPM5_C2H_INTR_H2C_ERR_C2H_MM_CTXT_INVAL_ADDR 0xB70
#define C2H_INTR_H2C_ERR_C2H_MM_CTXT_INVAL_RSVD_1_MASK GENMASK(31, 18)
#define C2H_INTR_H2C_ERR_C2H_MM_CTXT_INVAL_CNT_MASK GENMASK(17, 0)
-#define EQDMA_CPM5_C2H_INTR_C2H_ST_MSIX_ACK_ADDR 0xB74
+#define EQDMA_CPM5_C2H_INTR_C2H_ST_MSIX_ACK_ADDR 0xB74
#define C2H_INTR_C2H_ST_MSIX_ACK_RSVD_1_MASK GENMASK(31, 18)
#define C2H_INTR_C2H_ST_MSIX_ACK_CNT_MASK GENMASK(17, 0)
-#define EQDMA_CPM5_C2H_INTR_C2H_ST_MSIX_FAIL_ADDR 0xB78
+#define EQDMA_CPM5_C2H_INTR_C2H_ST_MSIX_FAIL_ADDR 0xB78
#define C2H_INTR_C2H_ST_MSIX_FAIL_RSVD_1_MASK GENMASK(31, 18)
#define C2H_INTR_C2H_ST_MSIX_FAIL_CNT_MASK GENMASK(17, 0)
-#define EQDMA_CPM5_C2H_INTR_C2H_ST_NO_MSIX_ADDR 0xB7C
+#define EQDMA_CPM5_C2H_INTR_C2H_ST_NO_MSIX_ADDR 0xB7C
#define C2H_INTR_C2H_ST_NO_MSIX_RSVD_1_MASK GENMASK(31, 18)
#define C2H_INTR_C2H_ST_NO_MSIX_CNT_MASK GENMASK(17, 0)
-#define EQDMA_CPM5_C2H_INTR_C2H_ST_CTXT_INVAL_ADDR 0xB80
+#define EQDMA_CPM5_C2H_INTR_C2H_ST_CTXT_INVAL_ADDR 0xB80
#define C2H_INTR_C2H_ST_CTXT_INVAL_RSVD_1_MASK GENMASK(31, 18)
#define C2H_INTR_C2H_ST_CTXT_INVAL_CNT_MASK GENMASK(17, 0)
-#define EQDMA_CPM5_C2H_STAT_WR_CMP_ADDR 0xB84
+#define EQDMA_CPM5_C2H_STAT_WR_CMP_ADDR 0xB84
#define C2H_STAT_WR_CMP_RSVD_1_MASK GENMASK(31, 18)
#define C2H_STAT_WR_CMP_CNT_MASK GENMASK(17, 0)
-#define EQDMA_CPM5_C2H_STAT_DBG_DMA_ENG_4_ADDR 0xB88
+#define EQDMA_CPM5_C2H_STAT_DBG_DMA_ENG_4_ADDR 0xB88
#define C2H_STAT_DMA_ENG_4_RSVD_1_MASK GENMASK(31, 24)
#define C2H_STAT_DMA_ENG_4_WRQ_FIFO_OUT_CNT_MASK GENMASK(23, 19)
#define C2H_STAT_DMA_ENG_4_QID_FIFO_OUT_VLD_MASK BIT(18)
@@ -824,7 +823,7 @@ struct xreg_info *eqdma_cpm5_config_regs_get(void);
#define C2H_STAT_DMA_ENG_4_WRQ_PACKET_PRE_EOR_MASK BIT(2)
#define C2H_STAT_DMA_ENG_4_WCP_FIFO_IN_RDY_MASK BIT(1)
#define C2H_STAT_DMA_ENG_4_PLD_ST_FIFO_IN_RDY_MASK BIT(0)
-#define EQDMA_CPM5_C2H_STAT_DBG_DMA_ENG_5_ADDR 0xB8C
+#define EQDMA_CPM5_C2H_STAT_DBG_DMA_ENG_5_ADDR 0xB8C
#define C2H_STAT_DMA_ENG_5_RSVD_1_MASK GENMASK(31, 30)
#define C2H_STAT_DMA_ENG_5_WRB_SM_VIRT_CH_MASK BIT(29)
#define C2H_STAT_DMA_ENG_5_WRB_FIFO_IN_REQ_MASK GENMASK(28, 24)
@@ -836,93 +835,93 @@ struct xreg_info *eqdma_cpm5_config_regs_get(void);
#define C2H_STAT_DMA_ENG_5_ARB_FIFO_OUT_DATA_NUM_BUF_OV_MASK BIT(2)
#define C2H_STAT_DMA_ENG_5_ARB_FIFO_OUT_DATA_MARKER_MASK BIT(1)
#define C2H_STAT_DMA_ENG_5_ARB_FIFO_OUT_DATA_HAS_CMPT_MASK BIT(0)
-#define EQDMA_CPM5_C2H_DBG_PFCH_QID_ADDR 0xB90
+#define EQDMA_CPM5_C2H_DBG_PFCH_QID_ADDR 0xB90
#define C2H_PFCH_QID_RSVD_1_MASK GENMASK(31, 16)
#define C2H_PFCH_QID_ERR_CTXT_MASK BIT(15)
#define C2H_PFCH_QID_TARGET_MASK GENMASK(14, 12)
#define C2H_PFCH_QID_QID_OR_TAG_MASK GENMASK(11, 0)
-#define EQDMA_CPM5_C2H_DBG_PFCH_ADDR 0xB94
+#define EQDMA_CPM5_C2H_DBG_PFCH_ADDR 0xB94
#define C2H_PFCH_DATA_MASK GENMASK(31, 0)
-#define EQDMA_CPM5_C2H_INT_DBG_ADDR 0xB98
+#define EQDMA_CPM5_C2H_INT_DBG_ADDR 0xB98
#define C2H_INT_RSVD_1_MASK GENMASK(31, 8)
#define C2H_INT_INT_COAL_SM_MASK GENMASK(7, 4)
#define C2H_INT_INT_SM_MASK GENMASK(3, 0)
-#define EQDMA_CPM5_C2H_STAT_IMM_ACCEPTED_ADDR 0xB9C
+#define EQDMA_CPM5_C2H_STAT_IMM_ACCEPTED_ADDR 0xB9C
#define C2H_STAT_IMM_ACCEPTED_RSVD_1_MASK GENMASK(31, 18)
#define C2H_STAT_IMM_ACCEPTED_CNT_MASK GENMASK(17, 0)
-#define EQDMA_CPM5_C2H_STAT_MARKER_ACCEPTED_ADDR 0xBA0
+#define EQDMA_CPM5_C2H_STAT_MARKER_ACCEPTED_ADDR 0xBA0
#define C2H_STAT_MARKER_ACCEPTED_RSVD_1_MASK GENMASK(31, 18)
#define C2H_STAT_MARKER_ACCEPTED_CNT_MASK GENMASK(17, 0)
-#define EQDMA_CPM5_C2H_STAT_DISABLE_CMP_ACCEPTED_ADDR 0xBA4
+#define EQDMA_CPM5_C2H_STAT_DISABLE_CMP_ACCEPTED_ADDR 0xBA4
#define C2H_STAT_DISABLE_CMP_ACCEPTED_RSVD_1_MASK GENMASK(31, 18)
#define C2H_STAT_DISABLE_CMP_ACCEPTED_CNT_MASK GENMASK(17, 0)
-#define EQDMA_CPM5_C2H_PLD_FIFO_CRDT_CNT_ADDR 0xBA8
+#define EQDMA_CPM5_C2H_PLD_FIFO_CRDT_CNT_ADDR 0xBA8
#define C2H_PLD_FIFO_CRDT_CNT_RSVD_1_MASK GENMASK(31, 18)
#define C2H_PLD_FIFO_CRDT_CNT_CNT_MASK GENMASK(17, 0)
-#define EQDMA_CPM5_C2H_INTR_DYN_REQ_ADDR 0xBAC
+#define EQDMA_CPM5_C2H_INTR_DYN_REQ_ADDR 0xBAC
#define C2H_INTR_DYN_REQ_RSVD_1_MASK GENMASK(31, 18)
#define C2H_INTR_DYN_REQ_CNT_MASK GENMASK(17, 0)
-#define EQDMA_CPM5_C2H_INTR_DYN_MISC_ADDR 0xBB0
+#define EQDMA_CPM5_C2H_INTR_DYN_MISC_ADDR 0xBB0
#define C2H_INTR_DYN_MISC_RSVD_1_MASK GENMASK(31, 18)
#define C2H_INTR_DYN_MISC_CNT_MASK GENMASK(17, 0)
-#define EQDMA_CPM5_C2H_DROP_LEN_MISMATCH_ADDR 0xBB4
+#define EQDMA_CPM5_C2H_DROP_LEN_MISMATCH_ADDR 0xBB4
#define C2H_DROP_LEN_MISMATCH_RSVD_1_MASK GENMASK(31, 18)
#define C2H_DROP_LEN_MISMATCH_CNT_MASK GENMASK(17, 0)
-#define EQDMA_CPM5_C2H_DROP_DESC_RSP_LEN_ADDR 0xBB8
+#define EQDMA_CPM5_C2H_DROP_DESC_RSP_LEN_ADDR 0xBB8
#define C2H_DROP_DESC_RSP_LEN_RSVD_1_MASK GENMASK(31, 18)
#define C2H_DROP_DESC_RSP_LEN_CNT_MASK GENMASK(17, 0)
-#define EQDMA_CPM5_C2H_DROP_QID_FIFO_LEN_ADDR 0xBBC
+#define EQDMA_CPM5_C2H_DROP_QID_FIFO_LEN_ADDR 0xBBC
#define C2H_DROP_QID_FIFO_LEN_RSVD_1_MASK GENMASK(31, 18)
#define C2H_DROP_QID_FIFO_LEN_CNT_MASK GENMASK(17, 0)
-#define EQDMA_CPM5_C2H_DROP_PLD_CNT_ADDR 0xBC0
+#define EQDMA_CPM5_C2H_DROP_PLD_CNT_ADDR 0xBC0
#define C2H_DROP_PLD_CNT_RSVD_1_MASK GENMASK(31, 18)
#define C2H_DROP_PLD_CNT_CNT_MASK GENMASK(17, 0)
-#define EQDMA_CPM5_C2H_CMPT_FORMAT_0_ADDR 0xBC4
+#define EQDMA_CPM5_C2H_CMPT_FORMAT_0_ADDR 0xBC4
#define C2H_CMPT_FORMAT_0_DESC_ERR_LOC_MASK GENMASK(31, 16)
#define C2H_CMPT_FORMAT_0_COLOR_LOC_MASK GENMASK(15, 0)
-#define EQDMA_CPM5_C2H_CMPT_FORMAT_1_ADDR 0xBC8
+#define EQDMA_CPM5_C2H_CMPT_FORMAT_1_ADDR 0xBC8
#define C2H_CMPT_FORMAT_1_DESC_ERR_LOC_MASK GENMASK(31, 16)
#define C2H_CMPT_FORMAT_1_COLOR_LOC_MASK GENMASK(15, 0)
-#define EQDMA_CPM5_C2H_CMPT_FORMAT_2_ADDR 0xBCC
+#define EQDMA_CPM5_C2H_CMPT_FORMAT_2_ADDR 0xBCC
#define C2H_CMPT_FORMAT_2_DESC_ERR_LOC_MASK GENMASK(31, 16)
#define C2H_CMPT_FORMAT_2_COLOR_LOC_MASK GENMASK(15, 0)
-#define EQDMA_CPM5_C2H_CMPT_FORMAT_3_ADDR 0xBD0
+#define EQDMA_CPM5_C2H_CMPT_FORMAT_3_ADDR 0xBD0
#define C2H_CMPT_FORMAT_3_DESC_ERR_LOC_MASK GENMASK(31, 16)
#define C2H_CMPT_FORMAT_3_COLOR_LOC_MASK GENMASK(15, 0)
-#define EQDMA_CPM5_C2H_CMPT_FORMAT_4_ADDR 0xBD4
+#define EQDMA_CPM5_C2H_CMPT_FORMAT_4_ADDR 0xBD4
#define C2H_CMPT_FORMAT_4_DESC_ERR_LOC_MASK GENMASK(31, 16)
#define C2H_CMPT_FORMAT_4_COLOR_LOC_MASK GENMASK(15, 0)
-#define EQDMA_CPM5_C2H_CMPT_FORMAT_5_ADDR 0xBD8
+#define EQDMA_CPM5_C2H_CMPT_FORMAT_5_ADDR 0xBD8
#define C2H_CMPT_FORMAT_5_DESC_ERR_LOC_MASK GENMASK(31, 16)
#define C2H_CMPT_FORMAT_5_COLOR_LOC_MASK GENMASK(15, 0)
-#define EQDMA_CPM5_C2H_CMPT_FORMAT_6_ADDR 0xBDC
+#define EQDMA_CPM5_C2H_CMPT_FORMAT_6_ADDR 0xBDC
#define C2H_CMPT_FORMAT_6_DESC_ERR_LOC_MASK GENMASK(31, 16)
#define C2H_CMPT_FORMAT_6_COLOR_LOC_MASK GENMASK(15, 0)
-#define EQDMA_CPM5_C2H_PFCH_CACHE_DEPTH_ADDR 0xBE0
+#define EQDMA_CPM5_C2H_PFCH_CACHE_DEPTH_ADDR 0xBE0
#define C2H_PFCH_CACHE_DEPTH_MAX_STBUF_MASK GENMASK(23, 16)
#define C2H_PFCH_CACHE_DEPTH_MASK GENMASK(7, 0)
-#define EQDMA_CPM5_C2H_WRB_COAL_BUF_DEPTH_ADDR 0xBE4
+#define EQDMA_CPM5_C2H_WRB_COAL_BUF_DEPTH_ADDR 0xBE4
#define C2H_WRB_COAL_BUF_DEPTH_RSVD_1_MASK GENMASK(31, 8)
#define C2H_WRB_COAL_BUF_DEPTH_BUFFER_MASK GENMASK(7, 0)
-#define EQDMA_CPM5_C2H_PFCH_CRDT_ADDR 0xBE8
+#define EQDMA_CPM5_C2H_PFCH_CRDT_ADDR 0xBE8
#define C2H_PFCH_CRDT_RSVD_1_MASK GENMASK(31, 1)
#define C2H_PFCH_CRDT_RSVD_2_MASK BIT(0)
-#define EQDMA_CPM5_C2H_STAT_HAS_CMPT_ACCEPTED_ADDR 0xBEC
+#define EQDMA_CPM5_C2H_STAT_HAS_CMPT_ACCEPTED_ADDR 0xBEC
#define C2H_STAT_HAS_CMPT_ACCEPTED_RSVD_1_MASK GENMASK(31, 18)
#define C2H_STAT_HAS_CMPT_ACCEPTED_CNT_MASK GENMASK(17, 0)
-#define EQDMA_CPM5_C2H_STAT_HAS_PLD_ACCEPTED_ADDR 0xBF0
+#define EQDMA_CPM5_C2H_STAT_HAS_PLD_ACCEPTED_ADDR 0xBF0
#define C2H_STAT_HAS_PLD_ACCEPTED_RSVD_1_MASK GENMASK(31, 18)
#define C2H_STAT_HAS_PLD_ACCEPTED_CNT_MASK GENMASK(17, 0)
-#define EQDMA_CPM5_C2H_PLD_PKT_ID_ADDR 0xBF4
+#define EQDMA_CPM5_C2H_PLD_PKT_ID_ADDR 0xBF4
#define C2H_PLD_PKT_ID_CMPT_WAIT_MASK GENMASK(31, 16)
#define C2H_PLD_PKT_ID_DATA_MASK GENMASK(15, 0)
-#define EQDMA_CPM5_C2H_PLD_PKT_ID_1_ADDR 0xBF8
+#define EQDMA_CPM5_C2H_PLD_PKT_ID_1_ADDR 0xBF8
#define C2H_PLD_PKT_ID_1_CMPT_WAIT_MASK GENMASK(31, 16)
#define C2H_PLD_PKT_ID_1_DATA_MASK GENMASK(15, 0)
-#define EQDMA_CPM5_C2H_DROP_PLD_CNT_1_ADDR 0xBFC
+#define EQDMA_CPM5_C2H_DROP_PLD_CNT_1_ADDR 0xBFC
#define C2H_DROP_PLD_CNT_1_RSVD_1_MASK GENMASK(31, 18)
#define C2H_DROP_PLD_CNT_1_CNT_MASK GENMASK(17, 0)
-#define EQDMA_CPM5_H2C_ERR_STAT_ADDR 0xE00
+#define EQDMA_CPM5_H2C_ERR_STAT_ADDR 0xE00
#define H2C_ERR_STAT_RSVD_1_MASK GENMASK(31, 6)
#define H2C_ERR_STAT_PAR_ERR_MASK BIT(5)
#define H2C_ERR_STAT_SBE_MASK BIT(4)
@@ -930,23 +929,23 @@ struct xreg_info *eqdma_cpm5_config_regs_get(void);
#define H2C_ERR_STAT_NO_DMA_DS_MASK BIT(2)
#define H2C_ERR_STAT_SDI_MRKR_REQ_MOP_ERR_MASK BIT(1)
#define H2C_ERR_STAT_ZERO_LEN_DS_MASK BIT(0)
-#define EQDMA_CPM5_H2C_ERR_MASK_ADDR 0xE04
+#define EQDMA_CPM5_H2C_ERR_MASK_ADDR 0xE04
#define H2C_ERR_EN_MASK GENMASK(31, 0)
-#define EQDMA_CPM5_H2C_FIRST_ERR_QID_ADDR 0xE08
+#define EQDMA_CPM5_H2C_FIRST_ERR_QID_ADDR 0xE08
#define H2C_FIRST_ERR_QID_RSVD_1_MASK GENMASK(31, 20)
#define H2C_FIRST_ERR_QID_ERR_TYPE_MASK GENMASK(19, 16)
#define H2C_FIRST_ERR_QID_RSVD_2_MASK GENMASK(15, 13)
#define H2C_FIRST_ERR_QID_QID_MASK GENMASK(12, 0)
-#define EQDMA_CPM5_H2C_DBG_REG0_ADDR 0xE0C
+#define EQDMA_CPM5_H2C_DBG_REG0_ADDR 0xE0C
#define H2C_REG0_NUM_DSC_RCVD_MASK GENMASK(31, 16)
#define H2C_REG0_NUM_WRB_SENT_MASK GENMASK(15, 0)
-#define EQDMA_CPM5_H2C_DBG_REG1_ADDR 0xE10
+#define EQDMA_CPM5_H2C_DBG_REG1_ADDR 0xE10
#define H2C_REG1_NUM_REQ_SENT_MASK GENMASK(31, 16)
#define H2C_REG1_NUM_CMP_SENT_MASK GENMASK(15, 0)
-#define EQDMA_CPM5_H2C_DBG_REG2_ADDR 0xE14
+#define EQDMA_CPM5_H2C_DBG_REG2_ADDR 0xE14
#define H2C_REG2_RSVD_1_MASK GENMASK(31, 16)
#define H2C_REG2_NUM_ERR_DSC_RCVD_MASK GENMASK(15, 0)
-#define EQDMA_CPM5_H2C_DBG_REG3_ADDR 0xE18
+#define EQDMA_CPM5_H2C_DBG_REG3_ADDR 0xE18
#define H2C_REG3_RSVD_1_MASK BIT(31)
#define H2C_REG3_DSCO_FIFO_EMPTY_MASK BIT(30)
#define H2C_REG3_DSCO_FIFO_FULL_MASK BIT(29)
@@ -958,34 +957,34 @@ struct xreg_info *eqdma_cpm5_config_regs_get(void);
#define H2C_REG3_CUR_RQ_STATE_MASK GENMASK(3, 2)
#define H2C_REG3_DSCI_FIFO_FULL_MASK BIT(1)
#define H2C_REG3_DSCI_FIFO_EMPTY_MASK BIT(0)
-#define EQDMA_CPM5_H2C_DBG_REG4_ADDR 0xE1C
+#define EQDMA_CPM5_H2C_DBG_REG4_ADDR 0xE1C
#define H2C_REG4_RDREQ_ADDR_MASK GENMASK(31, 0)
-#define EQDMA_CPM5_H2C_FATAL_ERR_EN_ADDR 0xE20
+#define EQDMA_CPM5_H2C_FATAL_ERR_EN_ADDR 0xE20
#define H2C_FATAL_ERR_EN_RSVD_1_MASK GENMASK(31, 1)
#define H2C_FATAL_ERR_EN_H2C_MASK BIT(0)
-#define EQDMA_CPM5_H2C_REQ_THROT_PCIE_ADDR 0xE24
+#define EQDMA_CPM5_H2C_REQ_THROT_PCIE_ADDR 0xE24
#define H2C_REQ_THROT_PCIE_EN_REQ_MASK BIT(31)
#define H2C_REQ_THROT_PCIE_MASK GENMASK(30, 19)
#define H2C_REQ_THROT_PCIE_EN_DATA_MASK BIT(18)
#define H2C_REQ_THROT_PCIE_DATA_THRESH_MASK GENMASK(17, 0)
-#define EQDMA_CPM5_H2C_ALN_DBG_REG0_ADDR 0xE28
+#define EQDMA_CPM5_H2C_ALN_DBG_REG0_ADDR 0xE28
#define H2C_ALN_REG0_NUM_PKT_SENT_MASK GENMASK(15, 0)
-#define EQDMA_CPM5_H2C_REQ_THROT_AXIMM_ADDR 0xE2C
+#define EQDMA_CPM5_H2C_REQ_THROT_AXIMM_ADDR 0xE2C
#define H2C_REQ_THROT_AXIMM_EN_REQ_MASK BIT(31)
#define H2C_REQ_THROT_AXIMM_MASK GENMASK(30, 19)
#define H2C_REQ_THROT_AXIMM_EN_DATA_MASK BIT(18)
#define H2C_REQ_THROT_AXIMM_DATA_THRESH_MASK GENMASK(17, 0)
-#define EQDMA_CPM5_C2H_MM_CTL_ADDR 0x1004
+#define EQDMA_CPM5_C2H_MM_CTL_ADDR 0x1004
#define C2H_MM_CTL_RESERVED1_MASK GENMASK(31, 9)
#define C2H_MM_CTL_ERRC_EN_MASK BIT(8)
#define C2H_MM_CTL_RESERVED0_MASK GENMASK(7, 1)
#define C2H_MM_CTL_RUN_MASK BIT(0)
-#define EQDMA_CPM5_C2H_MM_STATUS_ADDR 0x1040
+#define EQDMA_CPM5_C2H_MM_STATUS_ADDR 0x1040
#define C2H_MM_STATUS_RSVD_1_MASK GENMASK(31, 1)
#define C2H_MM_STATUS_RUN_MASK BIT(0)
-#define EQDMA_CPM5_C2H_MM_CMPL_DESC_CNT_ADDR 0x1048
+#define EQDMA_CPM5_C2H_MM_CMPL_DESC_CNT_ADDR 0x1048
#define C2H_MM_CMPL_DESC_CNT_C2H_CO_MASK GENMASK(31, 0)
-#define EQDMA_CPM5_C2H_MM_ERR_CODE_ENABLE_MASK_ADDR 0x1054
+#define EQDMA_CPM5_C2H_MM_ERR_CODE_ENABLE_MASK_ADDR 0x1054
#define C2H_MM_ERR_CODE_ENABLE_RESERVED1_MASK BIT(31)
#define C2H_MM_ERR_CODE_ENABLE_WR_UC_RAM_MASK BIT(30)
#define C2H_MM_ERR_CODE_ENABLE_WR_UR_MASK BIT(29)
@@ -993,34 +992,34 @@ struct xreg_info *eqdma_cpm5_config_regs_get(void);
#define C2H_MM_ERR_CODE_ENABLE_RESERVED0_MASK GENMASK(27, 2)
#define C2H_MM_ERR_CODE_ENABLE_RD_SLV_ERR_MASK BIT(1)
#define C2H_MM_ERR_CODE_ENABLE_WR_SLV_ERR_MASK BIT(0)
-#define EQDMA_CPM5_C2H_MM_ERR_CODE_ADDR 0x1058
+#define EQDMA_CPM5_C2H_MM_ERR_CODE_ADDR 0x1058
#define C2H_MM_ERR_CODE_RESERVED1_MASK GENMASK(31, 28)
#define C2H_MM_ERR_CODE_CIDX_MASK GENMASK(27, 12)
#define C2H_MM_ERR_CODE_RESERVED0_MASK GENMASK(11, 10)
#define C2H_MM_ERR_CODE_SUB_TYPE_MASK GENMASK(9, 5)
#define C2H_MM_ERR_CODE_MASK GENMASK(4, 0)
-#define EQDMA_CPM5_C2H_MM_ERR_INFO_ADDR 0x105C
+#define EQDMA_CPM5_C2H_MM_ERR_INFO_ADDR 0x105C
#define C2H_MM_ERR_INFO_VALID_MASK BIT(31)
#define C2H_MM_ERR_INFO_SEL_MASK BIT(30)
#define C2H_MM_ERR_INFO_RSVD_1_MASK GENMASK(29, 24)
#define C2H_MM_ERR_INFO_QID_MASK GENMASK(23, 0)
-#define EQDMA_CPM5_C2H_MM_PERF_MON_CTL_ADDR 0x10C0
+#define EQDMA_CPM5_C2H_MM_PERF_MON_CTL_ADDR 0x10C0
#define C2H_MM_PERF_MON_CTL_RSVD_1_MASK GENMASK(31, 4)
#define C2H_MM_PERF_MON_CTL_IMM_START_MASK BIT(3)
#define C2H_MM_PERF_MON_CTL_RUN_START_MASK BIT(2)
#define C2H_MM_PERF_MON_CTL_IMM_CLEAR_MASK BIT(1)
#define C2H_MM_PERF_MON_CTL_RUN_CLEAR_MASK BIT(0)
-#define EQDMA_CPM5_C2H_MM_PERF_MON_CYCLE_CNT0_ADDR 0x10C4
+#define EQDMA_CPM5_C2H_MM_PERF_MON_CYCLE_CNT0_ADDR 0x10C4
#define C2H_MM_PERF_MON_CYCLE_CNT0_CYC_CNT_MASK GENMASK(31, 0)
-#define EQDMA_CPM5_C2H_MM_PERF_MON_CYCLE_CNT1_ADDR 0x10C8
+#define EQDMA_CPM5_C2H_MM_PERF_MON_CYCLE_CNT1_ADDR 0x10C8
#define C2H_MM_PERF_MON_CYCLE_CNT1_RSVD_1_MASK GENMASK(31, 10)
#define C2H_MM_PERF_MON_CYCLE_CNT1_CYC_CNT_MASK GENMASK(9, 0)
-#define EQDMA_CPM5_C2H_MM_PERF_MON_DATA_CNT0_ADDR 0x10CC
+#define EQDMA_CPM5_C2H_MM_PERF_MON_DATA_CNT0_ADDR 0x10CC
#define C2H_MM_PERF_MON_DATA_CNT0_DCNT_MASK GENMASK(31, 0)
-#define EQDMA_CPM5_C2H_MM_PERF_MON_DATA_CNT1_ADDR 0x10D0
+#define EQDMA_CPM5_C2H_MM_PERF_MON_DATA_CNT1_ADDR 0x10D0
#define C2H_MM_PERF_MON_DATA_CNT1_RSVD_1_MASK GENMASK(31, 10)
#define C2H_MM_PERF_MON_DATA_CNT1_DCNT_MASK GENMASK(9, 0)
-#define EQDMA_CPM5_C2H_MM_DBG_ADDR 0x10E8
+#define EQDMA_CPM5_C2H_MM_DBG_ADDR 0x10E8
#define C2H_MM_RSVD_1_MASK GENMASK(31, 24)
#define C2H_MM_RRQ_ENTRIES_MASK GENMASK(23, 17)
#define C2H_MM_DAT_FIFO_SPC_MASK GENMASK(16, 7)
@@ -1031,17 +1030,17 @@ struct xreg_info *eqdma_cpm5_config_regs_get(void);
#define C2H_MM_WBK_STALL_MASK BIT(2)
#define C2H_MM_DSC_FIFO_EP_MASK BIT(1)
#define C2H_MM_DSC_FIFO_FL_MASK BIT(0)
-#define EQDMA_CPM5_H2C_MM_CTL_ADDR 0x1204
+#define EQDMA_CPM5_H2C_MM_CTL_ADDR 0x1204
#define H2C_MM_CTL_RESERVED1_MASK GENMASK(31, 9)
#define H2C_MM_CTL_ERRC_EN_MASK BIT(8)
#define H2C_MM_CTL_RESERVED0_MASK GENMASK(7, 1)
#define H2C_MM_CTL_RUN_MASK BIT(0)
-#define EQDMA_CPM5_H2C_MM_STATUS_ADDR 0x1240
+#define EQDMA_CPM5_H2C_MM_STATUS_ADDR 0x1240
#define H2C_MM_STATUS_RSVD_1_MASK GENMASK(31, 1)
#define H2C_MM_STATUS_RUN_MASK BIT(0)
-#define EQDMA_CPM5_H2C_MM_CMPL_DESC_CNT_ADDR 0x1248
+#define EQDMA_CPM5_H2C_MM_CMPL_DESC_CNT_ADDR 0x1248
#define H2C_MM_CMPL_DESC_CNT_H2C_CO_MASK GENMASK(31, 0)
-#define EQDMA_CPM5_H2C_MM_ERR_CODE_ENABLE_MASK_ADDR 0x1254
+#define EQDMA_CPM5_H2C_MM_ERR_CODE_ENABLE_MASK_ADDR 0x1254
#define H2C_MM_ERR_CODE_ENABLE_RESERVED5_MASK GENMASK(31, 30)
#define H2C_MM_ERR_CODE_ENABLE_WR_SLV_ERR_MASK BIT(29)
#define H2C_MM_ERR_CODE_ENABLE_WR_DEC_ERR_MASK BIT(28)
@@ -1058,34 +1057,34 @@ struct xreg_info *eqdma_cpm5_config_regs_get(void);
#define H2C_MM_ERR_CODE_ENABLE_RD_UR_CA_MASK BIT(2)
#define H2C_MM_ERR_CODE_ENABLE_RD_HRD_POISON_ERR_MASK BIT(1)
#define H2C_MM_ERR_CODE_ENABLE_RESERVED0_MASK BIT(0)
-#define EQDMA_CPM5_H2C_MM_ERR_CODE_ADDR 0x1258
+#define EQDMA_CPM5_H2C_MM_ERR_CODE_ADDR 0x1258
#define H2C_MM_ERR_CODE_RSVD_1_MASK GENMASK(31, 28)
#define H2C_MM_ERR_CODE_CIDX_MASK GENMASK(27, 12)
#define H2C_MM_ERR_CODE_RESERVED0_MASK GENMASK(11, 10)
#define H2C_MM_ERR_CODE_SUB_TYPE_MASK GENMASK(9, 5)
#define H2C_MM_ERR_CODE_MASK GENMASK(4, 0)
-#define EQDMA_CPM5_H2C_MM_ERR_INFO_ADDR 0x125C
+#define EQDMA_CPM5_H2C_MM_ERR_INFO_ADDR 0x125C
#define H2C_MM_ERR_INFO_VALID_MASK BIT(31)
#define H2C_MM_ERR_INFO_SEL_MASK BIT(30)
#define H2C_MM_ERR_INFO_RSVD_1_MASK GENMASK(29, 24)
#define H2C_MM_ERR_INFO_QID_MASK GENMASK(23, 0)
-#define EQDMA_CPM5_H2C_MM_PERF_MON_CTL_ADDR 0x12C0
+#define EQDMA_CPM5_H2C_MM_PERF_MON_CTL_ADDR 0x12C0
#define H2C_MM_PERF_MON_CTL_RSVD_1_MASK GENMASK(31, 4)
#define H2C_MM_PERF_MON_CTL_IMM_START_MASK BIT(3)
#define H2C_MM_PERF_MON_CTL_RUN_START_MASK BIT(2)
#define H2C_MM_PERF_MON_CTL_IMM_CLEAR_MASK BIT(1)
#define H2C_MM_PERF_MON_CTL_RUN_CLEAR_MASK BIT(0)
-#define EQDMA_CPM5_H2C_MM_PERF_MON_CYCLE_CNT0_ADDR 0x12C4
+#define EQDMA_CPM5_H2C_MM_PERF_MON_CYCLE_CNT0_ADDR 0x12C4
#define H2C_MM_PERF_MON_CYCLE_CNT0_CYC_CNT_MASK GENMASK(31, 0)
-#define EQDMA_CPM5_H2C_MM_PERF_MON_CYCLE_CNT1_ADDR 0x12C8
+#define EQDMA_CPM5_H2C_MM_PERF_MON_CYCLE_CNT1_ADDR 0x12C8
#define H2C_MM_PERF_MON_CYCLE_CNT1_RSVD_1_MASK GENMASK(31, 10)
#define H2C_MM_PERF_MON_CYCLE_CNT1_CYC_CNT_MASK GENMASK(9, 0)
-#define EQDMA_CPM5_H2C_MM_PERF_MON_DATA_CNT0_ADDR 0x12CC
+#define EQDMA_CPM5_H2C_MM_PERF_MON_DATA_CNT0_ADDR 0x12CC
#define H2C_MM_PERF_MON_DATA_CNT0_DCNT_MASK GENMASK(31, 0)
-#define EQDMA_CPM5_H2C_MM_PERF_MON_DATA_CNT1_ADDR 0x12D0
+#define EQDMA_CPM5_H2C_MM_PERF_MON_DATA_CNT1_ADDR 0x12D0
#define H2C_MM_PERF_MON_DATA_CNT1_RSVD_1_MASK GENMASK(31, 10)
#define H2C_MM_PERF_MON_DATA_CNT1_DCNT_MASK GENMASK(9, 0)
-#define EQDMA_CPM5_H2C_MM_DBG_ADDR 0x12E8
+#define EQDMA_CPM5_H2C_MM_DBG_ADDR 0x12E8
#define H2C_MM_RSVD_1_MASK GENMASK(31, 24)
#define H2C_MM_RRQ_ENTRIES_MASK GENMASK(23, 17)
#define H2C_MM_DAT_FIFO_SPC_MASK GENMASK(16, 7)
@@ -1096,26 +1095,41 @@ struct xreg_info *eqdma_cpm5_config_regs_get(void);
#define H2C_MM_WBK_STALL_MASK BIT(2)
#define H2C_MM_DSC_FIFO_EP_MASK BIT(1)
#define H2C_MM_DSC_FIFO_FL_MASK BIT(0)
-#define EQDMA_CPM5_C2H_CRDT_COAL_CFG_1_ADDR 0x1400
+#define EQDMA_CPM5_C2H_CRDT_COAL_CFG_1_ADDR 0x1400
#define C2H_CRDT_COAL_CFG_1_RSVD_1_MASK GENMASK(31, 18)
#define C2H_CRDT_COAL_CFG_1_PLD_FIFO_TH_MASK GENMASK(17, 10)
#define C2H_CRDT_COAL_CFG_1_TIMER_TH_MASK GENMASK(9, 0)
-#define EQDMA_CPM5_C2H_CRDT_COAL_CFG_2_ADDR 0x1404
+#define EQDMA_CPM5_C2H_CRDT_COAL_CFG_2_ADDR 0x1404
#define C2H_CRDT_COAL_CFG_2_RSVD_1_MASK GENMASK(31, 24)
#define C2H_CRDT_COAL_CFG_2_FIFO_TH_MASK GENMASK(23, 16)
#define C2H_CRDT_COAL_CFG_2_RESERVED1_MASK GENMASK(15, 11)
#define C2H_CRDT_COAL_CFG_2_NT_TH_MASK GENMASK(10, 0)
-#define EQDMA_CPM5_C2H_PFCH_BYP_QID_ADDR 0x1408
+#define EQDMA_CPM5_C2H_PFCH_BYP_QID_ADDR 0x1408
#define C2H_PFCH_BYP_QID_RSVD_1_MASK GENMASK(31, 12)
#define C2H_PFCH_BYP_QID_MASK GENMASK(11, 0)
-#define EQDMA_CPM5_C2H_PFCH_BYP_TAG_ADDR 0x140C
+#define EQDMA_CPM5_C2H_PFCH_BYP_TAG_ADDR 0x140C
#define C2H_PFCH_BYP_TAG_RSVD_1_MASK GENMASK(31, 20)
#define C2H_PFCH_BYP_TAG_BYP_QID_MASK GENMASK(19, 8)
#define C2H_PFCH_BYP_TAG_RSVD_2_MASK BIT(7)
#define C2H_PFCH_BYP_TAG_MASK GENMASK(6, 0)
-#define EQDMA_CPM5_C2H_WATER_MARK_ADDR 0x1500
+#define EQDMA_CPM5_C2H_WATER_MARK_ADDR 0x1500
#define C2H_WATER_MARK_HIGH_WM_MASK GENMASK(31, 16)
#define C2H_WATER_MARK_LOW_WM_MASK GENMASK(15, 0)
+#define EQDMA_CPM5_C2H_NOTIFY_EMPTY_ADDR 0x1800
+#define C2H_NOTIFY_EMPTY_RSVD_1_MASK GENMASK(31, 16)
+#define C2H_NOTIFY_EMPTY_NOE_MASK GENMASK(15, 0)
+#define EQDMA_CPM5_C2H_STAT_S_AXIS_C2H_ACCEPTED_1_ADDR 0x1804
+#define C2H_STAT_S_AXIS_C2H_ACCEPTED_1_MASK GENMASK(31, 0)
+#define EQDMA_CPM5_C2H_STAT_S_AXIS_WRB_ACCEPTED_1_ADDR 0x1808
+#define C2H_STAT_S_AXIS_WRB_ACCEPTED_1_MASK GENMASK(31, 0)
+#define EQDMA_CPM5_C2H_STAT_DESC_RSP_PKT_ACCEPTED_1_ADDR 0x180C
+#define C2H_STAT_DESC_RSP_PKT_ACCEPTED_1_D_MASK GENMASK(31, 0)
+#define EQDMA_CPM5_C2H_STAT_AXIS_PKG_CMP_1_ADDR 0x1810
+#define C2H_STAT_AXIS_PKG_CMP_1_MASK GENMASK(31, 0)
+#define EQDMA_CPM5_C2H_STAT_S_AXIS_WRB_ACCEPTED_2_ADDR 0x1814
+#define C2H_STAT_S_AXIS_WRB_ACCEPTED_2_MASK GENMASK(31, 0)
+#define EQDMA_CPM5_C2H_ST_PLD_FIFO_DEPTH_ADDR 0x1818
+#define C2H_ST_PLD_FIFO_DEPTH_MASK GENMASK(31, 0)
#define SW_IND_CTXT_DATA_W7_VIRTIO_DSC_BASE_H_MASK GENMASK(10, 0)
#define SW_IND_CTXT_DATA_W6_VIRTIO_DSC_BASE_M_MASK GENMASK(31, 0)
#define SW_IND_CTXT_DATA_W5_VIRTIO_DSC_BASE_L_MASK GENMASK(31, 11)
@@ -1233,6 +1247,50 @@ struct xreg_info *eqdma_cpm5_config_regs_get(void);
#define INTR_CTXT_DATA_W0_RSVD1_MASK BIT(12)
#define INTR_CTXT_DATA_W0_VEC_MASK GENMASK(11, 1)
#define INTR_CTXT_DATA_W0_VALID_MASK BIT(0)
+#define HOSTID_TABLE_W6_SMID_MASK GENMASK(9, 0)
+#define HOSTID_TABLE_W5_H2C_MM_AWPROT_MASK GENMASK(27, 26)
+#define HOSTID_TABLE_W5_H2C_MM_AWCACHE_MASK GENMASK(25, 22)
+#define HOSTID_TABLE_W5_H2C_MM_AWSTEERING_MASK GENMASK(20, 18)
+#define HOSTID_TABLE_W5_DSC_AWPROT_MASK GENMASK(17, 16)
+#define HOSTID_TABLE_W5_DSC_AWCACHE_MASK GENMASK(15, 12)
+#define HOSTID_TABLE_W5_DSC_AWSTEERING_MASK GENMASK(11, 8)
+#define HOSTID_TABLE_W5_INT_MSG_AWPROT_MASK GENMASK(7, 6)
+#define HOSTID_TABLE_W5_INT_MSG_AWCACHE_MASK GENMASK(5, 2)
+#define HOSTID_TABLE_W5_INT_MSG_AWSTEERING_H_MASK GENMASK(0, 0)
+#define HOSTID_TABLE_W4_INT_MSG_AWSTEERING_L_MASK GENMASK(31, 30)
+#define HOSTID_TABLE_W4_INT_AGGR_AWPROT_MASK GENMASK(29, 28)
+#define HOSTID_TABLE_W4_INT_AGGR_AWCACHE_MASK GENMASK(27, 24)
+#define HOSTID_TABLE_W4_INT_AGGR_AWSTEERING_MASK GENMASK(22, 20)
+#define HOSTID_TABLE_W4_CMPT_AWPROT_MASK GENMASK(19, 18)
+#define HOSTID_TABLE_W4_CMPT_AWCACHE_MASK GENMASK(17, 14)
+#define HOSTID_TABLE_W4_CMPT_AWSTEERING_MASK GENMASK(12, 10)
+#define HOSTID_TABLE_W4_C2H_PLD_AWPROT_MASK GENMASK(9, 8)
+#define HOSTID_TABLE_W4_C2H_PLD_AWCACHE_MASK GENMASK(7, 4)
+#define HOSTID_TABLE_W4_C2H_PLD_AWSTEERING_MASK GENMASK(2, 0)
+#define HOSTID_TABLE_W3_C2H_MM_ARPROT_MASK GENMASK(7, 6)
+#define HOSTID_TABLE_W3_C2H_MM_ARCACHE_MASK GENMASK(5, 2)
+#define HOSTID_TABLE_W3_C2H_MM_ARSTEERING_H_MASK GENMASK(0, 0)
+#define HOSTID_TABLE_W2_C2H_MM_ARSTEERING_L_MASK GENMASK(31, 30)
+#define HOSTID_TABLE_W2_H2C_MM_ARPROT_MASK GENMASK(29, 28)
+#define HOSTID_TABLE_W2_H2C_MM_ARCACHE_MASK GENMASK(27, 24)
+#define HOSTID_TABLE_W2_H2C_MM_ARSTEERING_MASK GENMASK(22, 20)
+#define HOSTID_TABLE_W2_H2C_ST_ARPROT_MASK GENMASK(19, 18)
+#define HOSTID_TABLE_W2_H2C_ST_ARCACHE_MASK GENMASK(17, 14)
+#define HOSTID_TABLE_W2_H2C_ST_ARSTEERING_MASK GENMASK(12, 10)
+#define HOSTID_TABLE_W2_DSC_ARPOT_MASK GENMASK(9, 8)
+#define HOSTID_TABLE_W2_DSC_ARCACHE_MASK GENMASK(7, 4)
+#define HOSTID_TABLE_W2_DSC_ARSTEERING_MASK GENMASK(2, 0)
+#define HOSTID_TABLE_W0_VCH_H2C_MM_MASK GENMASK(27, 24)
+#define HOSTID_TABLE_W0_VCH_H2C_ST_MASK GENMASK(23, 20)
+#define HOSTID_TABLE_W0_VCH_DSC_MASK GENMASK(19, 16)
+#define HOSTID_TABLE_W0_VCH_INT_MSG_MASK GENMASK(15, 12)
+#define HOSTID_TABLE_W0_VCH_INT_AGGR_MASK GENMASK(11, 8)
+#define HOSTID_TABLE_W0_VCH_CMPT_MASK GENMASK(7, 4)
+#define HOSTID_TABLE_W0_VCH_H2C_PLD_MASK GENMASK(3, 0)
+#define CTXT_SELC_FNC_STS_W0_MSIX_MASK GENMASK(3, 3)
+#define CTXT_SELC_FNC_STS_W0_MSIX_ENABLE_MASK GENMASK(2, 2)
+#define CTXT_SELC_FNC_STS_W0_MEM_SPACE_ENABLE_MASK GENMASK(1, 1)
+#define CTXT_SELC_FNC_STS_W0_BUS_MASTER_ENABLE_MASK GENMASK(0, 0)
#ifdef __cplusplus
}
diff --git a/QDMA/DPDK/drivers/net/qdma/qdma_access/eqdma_cpm5_access/eqdma_cpm5_reg_dump.c b/QDMA/DPDK/drivers/net/qdma/qdma_access/eqdma_cpm5_access/eqdma_cpm5_reg_dump.c
old mode 100644
new mode 100755
index f9a666e5711d71f5273a9a2dc0f85bd91894ab8b..af9a175c3368712be4eed045affb5b2fbf58e28a
--- a/QDMA/DPDK/drivers/net/qdma/qdma_access/eqdma_cpm5_access/eqdma_cpm5_reg_dump.c
+++ b/QDMA/DPDK/drivers/net/qdma/qdma_access/eqdma_cpm5_access/eqdma_cpm5_reg_dump.c
@@ -1,5 +1,6 @@
/*
- * Copyright(c) 2019-2022 Xilinx, Inc. All rights reserved.
+ * Copyright (c) 2019-2022 Xilinx, Inc. All rights reserved.
+ * Copyright (c) 2022, Advanced Micro Devices, Inc. All rights reserved.
*
* BSD LICENSE
*
@@ -1182,42 +1183,6 @@ static struct regfield_info
};
-static struct regfield_info
- glbl_req_err_sts_field_info[] = {
- {"GLBL_REQ_ERR_STS_RSVD_1",
- GLBL_REQ_ERR_STS_RSVD_1_MASK},
- {"GLBL_REQ_ERR_STS_RC_DISCONTINUE",
- GLBL_REQ_ERR_STS_RC_DISCONTINUE_MASK},
- {"GLBL_REQ_ERR_STS_RC_PRTY",
- GLBL_REQ_ERR_STS_RC_PRTY_MASK},
- {"GLBL_REQ_ERR_STS_RC_FLR",
- GLBL_REQ_ERR_STS_RC_FLR_MASK},
- {"GLBL_REQ_ERR_STS_RC_TIMEOUT",
- GLBL_REQ_ERR_STS_RC_TIMEOUT_MASK},
- {"GLBL_REQ_ERR_STS_RC_INV_BCNT",
- GLBL_REQ_ERR_STS_RC_INV_BCNT_MASK},
- {"GLBL_REQ_ERR_STS_RC_INV_TAG",
- GLBL_REQ_ERR_STS_RC_INV_TAG_MASK},
- {"GLBL_REQ_ERR_STS_RC_START_ADDR_MISMCH",
- GLBL_REQ_ERR_STS_RC_START_ADDR_MISMCH_MASK},
- {"GLBL_REQ_ERR_STS_RC_RID_TC_ATTR_MISMCH",
- GLBL_REQ_ERR_STS_RC_RID_TC_ATTR_MISMCH_MASK},
- {"GLBL_REQ_ERR_STS_RC_NO_DATA",
- GLBL_REQ_ERR_STS_RC_NO_DATA_MASK},
- {"GLBL_REQ_ERR_STS_RC_UR_CA_CRS",
- GLBL_REQ_ERR_STS_RC_UR_CA_CRS_MASK},
- {"GLBL_REQ_ERR_STS_RC_POISONED",
- GLBL_REQ_ERR_STS_RC_POISONED_MASK},
-};
-
-
-static struct regfield_info
- glbl_req_err_msk_field_info[] = {
- {"GLBL_REQ_ERR_MSK",
- GLBL_REQ_ERR_MSK_MASK},
-};
-
-
static struct regfield_info
ind_ctxt_data_field_info[] = {
{"IND_CTXT_DATA_DATA",
@@ -1267,6 +1232,8 @@ static struct regfield_info
static struct regfield_info
c2h_stat_s_axis_c2h_accepted_field_info[] = {
+ {"C2H_STAT_S_AXIS_C2H_ACCEPTED_RSVD_1",
+ C2H_STAT_S_AXIS_C2H_ACCEPTED_RSVD_1_MASK},
{"C2H_STAT_S_AXIS_C2H_ACCEPTED",
C2H_STAT_S_AXIS_C2H_ACCEPTED_MASK},
};
@@ -1274,6 +1241,8 @@ static struct regfield_info
static struct regfield_info
c2h_stat_s_axis_wrb_accepted_field_info[] = {
+ {"C2H_STAT_S_AXIS_WRB_ACCEPTED_RSVD_1",
+ C2H_STAT_S_AXIS_WRB_ACCEPTED_RSVD_1_MASK},
{"C2H_STAT_S_AXIS_WRB_ACCEPTED",
C2H_STAT_S_AXIS_WRB_ACCEPTED_MASK},
};
@@ -1281,6 +1250,8 @@ static struct regfield_info
static struct regfield_info
c2h_stat_desc_rsp_pkt_accepted_field_info[] = {
+ {"C2H_STAT_DESC_RSP_PKT_ACCEPTED_RSVD_1",
+ C2H_STAT_DESC_RSP_PKT_ACCEPTED_RSVD_1_MASK},
{"C2H_STAT_DESC_RSP_PKT_ACCEPTED_D",
C2H_STAT_DESC_RSP_PKT_ACCEPTED_D_MASK},
};
@@ -1288,6 +1259,8 @@ static struct regfield_info
static struct regfield_info
c2h_stat_axis_pkg_cmp_field_info[] = {
+ {"C2H_STAT_AXIS_PKG_CMP_RSVD_1",
+ C2H_STAT_AXIS_PKG_CMP_RSVD_1_MASK},
{"C2H_STAT_AXIS_PKG_CMP",
C2H_STAT_AXIS_PKG_CMP_MASK},
};
@@ -1295,6 +1268,8 @@ static struct regfield_info
static struct regfield_info
c2h_stat_desc_rsp_accepted_field_info[] = {
+ {"C2H_STAT_DESC_RSP_ACCEPTED_RSVD_1",
+ C2H_STAT_DESC_RSP_ACCEPTED_RSVD_1_MASK},
{"C2H_STAT_DESC_RSP_ACCEPTED_D",
C2H_STAT_DESC_RSP_ACCEPTED_D_MASK},
};
@@ -1302,6 +1277,8 @@ static struct regfield_info
static struct regfield_info
c2h_stat_desc_rsp_cmp_field_info[] = {
+ {"C2H_STAT_DESC_RSP_CMP_RSVD_1",
+ C2H_STAT_DESC_RSP_CMP_RSVD_1_MASK},
{"C2H_STAT_DESC_RSP_CMP_D",
C2H_STAT_DESC_RSP_CMP_D_MASK},
};
@@ -1309,6 +1286,8 @@ static struct regfield_info
static struct regfield_info
c2h_stat_wrq_out_field_info[] = {
+ {"C2H_STAT_WRQ_OUT_RSVD_1",
+ C2H_STAT_WRQ_OUT_RSVD_1_MASK},
{"C2H_STAT_WRQ_OUT",
C2H_STAT_WRQ_OUT_MASK},
};
@@ -1316,6 +1295,8 @@ static struct regfield_info
static struct regfield_info
c2h_stat_wpl_ren_accepted_field_info[] = {
+ {"C2H_STAT_WPL_REN_ACCEPTED_RSVD_1",
+ C2H_STAT_WPL_REN_ACCEPTED_RSVD_1_MASK},
{"C2H_STAT_WPL_REN_ACCEPTED",
C2H_STAT_WPL_REN_ACCEPTED_MASK},
};
@@ -1323,6 +1304,8 @@ static struct regfield_info
static struct regfield_info
c2h_stat_total_wrq_len_field_info[] = {
+ {"C2H_STAT_TOTAL_WRQ_LEN_RSVD_1",
+ C2H_STAT_TOTAL_WRQ_LEN_RSVD_1_MASK},
{"C2H_STAT_TOTAL_WRQ_LEN",
C2H_STAT_TOTAL_WRQ_LEN_MASK},
};
@@ -1330,6 +1313,8 @@ static struct regfield_info
static struct regfield_info
c2h_stat_total_wpl_len_field_info[] = {
+ {"C2H_STAT_TOTAL_WPL_LEN_RSVD_1",
+ C2H_STAT_TOTAL_WPL_LEN_RSVD_1_MASK},
{"C2H_STAT_TOTAL_WPL_LEN",
C2H_STAT_TOTAL_WPL_LEN_MASK},
};
@@ -1522,6 +1507,8 @@ static struct regfield_info
static struct regfield_info
c2h_stat_desc_rsp_drop_accepted_field_info[] = {
+ {"C2H_STAT_DESC_RSP_DROP_ACCEPTED_RSVD_1",
+ C2H_STAT_DESC_RSP_DROP_ACCEPTED_RSVD_1_MASK},
{"C2H_STAT_DESC_RSP_DROP_ACCEPTED_D",
C2H_STAT_DESC_RSP_DROP_ACCEPTED_D_MASK},
};
@@ -1529,6 +1516,8 @@ static struct regfield_info
static struct regfield_info
c2h_stat_desc_rsp_err_accepted_field_info[] = {
+ {"C2H_STAT_DESC_RSP_ERR_ACCEPTED_RSVD_1",
+ C2H_STAT_DESC_RSP_ERR_ACCEPTED_RSVD_1_MASK},
{"C2H_STAT_DESC_RSP_ERR_ACCEPTED_D",
C2H_STAT_DESC_RSP_ERR_ACCEPTED_D_MASK},
};
@@ -1536,6 +1525,8 @@ static struct regfield_info
static struct regfield_info
c2h_stat_desc_req_field_info[] = {
+ {"C2H_STAT_DESC_REQ_RSVD_1",
+ C2H_STAT_DESC_REQ_RSVD_1_MASK},
{"C2H_STAT_DESC_REQ",
C2H_STAT_DESC_REQ_MASK},
};
@@ -2706,6 +2697,57 @@ static struct regfield_info
C2H_WATER_MARK_LOW_WM_MASK},
};
+
+static struct regfield_info
+ c2h_notify_empty_field_info[] = {
+ {"C2H_NOTIFY_EMPTY_RSVD_1",
+ C2H_NOTIFY_EMPTY_RSVD_1_MASK},
+ {"C2H_NOTIFY_EMPTY_NOE",
+ C2H_NOTIFY_EMPTY_NOE_MASK},
+};
+
+
+static struct regfield_info
+ c2h_stat_s_axis_c2h_accepted_1_field_info[] = {
+ {"C2H_STAT_S_AXIS_C2H_ACCEPTED_1",
+ C2H_STAT_S_AXIS_C2H_ACCEPTED_1_MASK},
+};
+
+
+static struct regfield_info
+ c2h_stat_s_axis_wrb_accepted_1_field_info[] = {
+ {"C2H_STAT_S_AXIS_WRB_ACCEPTED_1",
+ C2H_STAT_S_AXIS_WRB_ACCEPTED_1_MASK},
+};
+
+
+static struct regfield_info
+ c2h_stat_desc_rsp_pkt_accepted_1_field_info[] = {
+ {"C2H_STAT_DESC_RSP_PKT_ACCEPTED_1_D",
+ C2H_STAT_DESC_RSP_PKT_ACCEPTED_1_D_MASK},
+};
+
+
+static struct regfield_info
+ c2h_stat_axis_pkg_cmp_1_field_info[] = {
+ {"C2H_STAT_AXIS_PKG_CMP_1",
+ C2H_STAT_AXIS_PKG_CMP_1_MASK},
+};
+
+
+static struct regfield_info
+ c2h_stat_s_axis_wrb_accepted_2_field_info[] = {
+ {"C2H_STAT_S_AXIS_WRB_ACCEPTED_2",
+ C2H_STAT_S_AXIS_WRB_ACCEPTED_2_MASK},
+};
+
+
+static struct regfield_info
+ c2h_st_pld_fifo_depth_field_info[] = {
+ {"C2H_ST_PLD_FIFO_DEPTH",
+ C2H_ST_PLD_FIFO_DEPTH_MASK},
+};
+
static struct xreg_info eqdma_cpm5_config_regs[] = {
{"CFG_BLK_IDENTIFIER", 0x00,
1, 0, 0, 0,
@@ -3163,18 +3205,6 @@ static struct xreg_info eqdma_cpm5_config_regs[] = {
ARRAY_SIZE(fab_err_log_field_info),
fab_err_log_field_info
},
-{"GLBL_REQ_ERR_STS", 0x318,
- 1, 0, 0, 0,
- 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY,
- ARRAY_SIZE(glbl_req_err_sts_field_info),
- glbl_req_err_sts_field_info
-},
-{"GLBL_REQ_ERR_MSK", 0x31c,
- 1, 0, 0, 0,
- 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY,
- ARRAY_SIZE(glbl_req_err_msk_field_info),
- glbl_req_err_msk_field_info
-},
{"IND_CTXT_DATA", 0x804,
1, 0, 0, 0,
0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY,
@@ -3207,61 +3237,61 @@ static struct xreg_info eqdma_cpm5_config_regs[] = {
},
{"C2H_STAT_S_AXIS_C2H_ACCEPTED", 0xa88,
1, 0, 0, 0,
- 1, QDMA_ST_MODE, QDMA_REG_READ_PF_VF,
+ 0, QDMA_ST_MODE, QDMA_REG_READ_PF_VF,
ARRAY_SIZE(c2h_stat_s_axis_c2h_accepted_field_info),
c2h_stat_s_axis_c2h_accepted_field_info
},
{"C2H_STAT_S_AXIS_WRB_ACCEPTED", 0xa8c,
1, 0, 0, 0,
- 1, QDMA_ST_MODE, QDMA_REG_READ_PF_VF,
+ 0, QDMA_ST_MODE, QDMA_REG_READ_PF_VF,
ARRAY_SIZE(c2h_stat_s_axis_wrb_accepted_field_info),
c2h_stat_s_axis_wrb_accepted_field_info
},
{"C2H_STAT_DESC_RSP_PKT_ACCEPTED", 0xa90,
1, 0, 0, 0,
- 1, QDMA_ST_MODE, QDMA_REG_READ_PF_VF,
+ 0, QDMA_ST_MODE, QDMA_REG_READ_PF_VF,
ARRAY_SIZE(c2h_stat_desc_rsp_pkt_accepted_field_info),
c2h_stat_desc_rsp_pkt_accepted_field_info
},
{"C2H_STAT_AXIS_PKG_CMP", 0xa94,
1, 0, 0, 0,
- 1, QDMA_ST_MODE, QDMA_REG_READ_PF_VF,
+ 0, QDMA_ST_MODE, QDMA_REG_READ_PF_VF,
ARRAY_SIZE(c2h_stat_axis_pkg_cmp_field_info),
c2h_stat_axis_pkg_cmp_field_info
},
{"C2H_STAT_DESC_RSP_ACCEPTED", 0xa98,
1, 0, 0, 0,
- 1, QDMA_ST_MODE, QDMA_REG_READ_PF_ONLY,
+ 0, QDMA_ST_MODE, QDMA_REG_READ_PF_ONLY,
ARRAY_SIZE(c2h_stat_desc_rsp_accepted_field_info),
c2h_stat_desc_rsp_accepted_field_info
},
{"C2H_STAT_DESC_RSP_CMP", 0xa9c,
1, 0, 0, 0,
- 1, QDMA_ST_MODE, QDMA_REG_READ_PF_ONLY,
+ 0, QDMA_ST_MODE, QDMA_REG_READ_PF_ONLY,
ARRAY_SIZE(c2h_stat_desc_rsp_cmp_field_info),
c2h_stat_desc_rsp_cmp_field_info
},
{"C2H_STAT_WRQ_OUT", 0xaa0,
1, 0, 0, 0,
- 1, QDMA_ST_MODE, QDMA_REG_READ_PF_ONLY,
+ 0, QDMA_ST_MODE, QDMA_REG_READ_PF_ONLY,
ARRAY_SIZE(c2h_stat_wrq_out_field_info),
c2h_stat_wrq_out_field_info
},
{"C2H_STAT_WPL_REN_ACCEPTED", 0xaa4,
1, 0, 0, 0,
- 1, QDMA_ST_MODE, QDMA_REG_READ_PF_ONLY,
+ 0, QDMA_ST_MODE, QDMA_REG_READ_PF_ONLY,
ARRAY_SIZE(c2h_stat_wpl_ren_accepted_field_info),
c2h_stat_wpl_ren_accepted_field_info
},
{"C2H_STAT_TOTAL_WRQ_LEN", 0xaa8,
1, 0, 0, 0,
- 1, QDMA_ST_MODE, QDMA_REG_READ_PF_ONLY,
+ 0, QDMA_ST_MODE, QDMA_REG_READ_PF_ONLY,
ARRAY_SIZE(c2h_stat_total_wrq_len_field_info),
c2h_stat_total_wrq_len_field_info
},
{"C2H_STAT_TOTAL_WPL_LEN", 0xaac,
1, 0, 0, 0,
- 1, QDMA_ST_MODE, QDMA_REG_READ_PF_ONLY,
+ 0, QDMA_ST_MODE, QDMA_REG_READ_PF_ONLY,
ARRAY_SIZE(c2h_stat_total_wpl_len_field_info),
c2h_stat_total_wpl_len_field_info
},
@@ -3315,13 +3345,13 @@ static struct xreg_info eqdma_cpm5_config_regs[] = {
},
{"C2H_PFCH_CFG_1", 0xa80,
1, 0, 0, 0,
- 0, QDMA_COMPLETION_MODE, QDMA_REG_READ_PF_ONLY,
+ 0, QDMA_ST_MODE, QDMA_REG_READ_PF_VF,
ARRAY_SIZE(c2h_pfch_cfg_1_field_info),
c2h_pfch_cfg_1_field_info
},
{"C2H_PFCH_CFG_2", 0xa84,
1, 0, 0, 0,
- 0, QDMA_COMPLETION_MODE, QDMA_REG_READ_PF_ONLY,
+ 0, QDMA_ST_MODE, QDMA_REG_READ_PF_VF,
ARRAY_SIZE(c2h_pfch_cfg_2_field_info),
c2h_pfch_cfg_2_field_info
},
@@ -3333,43 +3363,43 @@ static struct xreg_info eqdma_cpm5_config_regs[] = {
},
{"C2H_STAT_DESC_RSP_DROP_ACCEPTED", 0xb10,
1, 0, 0, 0,
- 1, QDMA_ST_MODE, QDMA_REG_READ_PF_VF,
+ 0, QDMA_ST_MODE, QDMA_REG_READ_PF_VF,
ARRAY_SIZE(c2h_stat_desc_rsp_drop_accepted_field_info),
c2h_stat_desc_rsp_drop_accepted_field_info
},
{"C2H_STAT_DESC_RSP_ERR_ACCEPTED", 0xb14,
1, 0, 0, 0,
- 1, QDMA_ST_MODE, QDMA_REG_READ_PF_VF,
+ 0, QDMA_ST_MODE, QDMA_REG_READ_PF_VF,
ARRAY_SIZE(c2h_stat_desc_rsp_err_accepted_field_info),
c2h_stat_desc_rsp_err_accepted_field_info
},
{"C2H_STAT_DESC_REQ", 0xb18,
1, 0, 0, 0,
- 1, QDMA_ST_MODE, QDMA_REG_READ_PF_ONLY,
+ 0, QDMA_ST_MODE, QDMA_REG_READ_PF_ONLY,
ARRAY_SIZE(c2h_stat_desc_req_field_info),
c2h_stat_desc_req_field_info
},
{"C2H_STAT_DBG_DMA_ENG_0", 0xb1c,
1, 0, 0, 0,
- 1, QDMA_ST_MODE, QDMA_REG_READ_PF_ONLY,
+ 0, QDMA_ST_MODE, QDMA_REG_READ_PF_ONLY,
ARRAY_SIZE(c2h_stat_dbg_dma_eng_0_field_info),
c2h_stat_dbg_dma_eng_0_field_info
},
{"C2H_STAT_DBG_DMA_ENG_1", 0xb20,
1, 0, 0, 0,
- 1, QDMA_ST_MODE, QDMA_REG_READ_PF_ONLY,
+ 0, QDMA_ST_MODE, QDMA_REG_READ_PF_ONLY,
ARRAY_SIZE(c2h_stat_dbg_dma_eng_1_field_info),
c2h_stat_dbg_dma_eng_1_field_info
},
{"C2H_STAT_DBG_DMA_ENG_2", 0xb24,
1, 0, 0, 0,
- 1, QDMA_ST_MODE, QDMA_REG_READ_PF_ONLY,
+ 0, QDMA_ST_MODE, QDMA_REG_READ_PF_ONLY,
ARRAY_SIZE(c2h_stat_dbg_dma_eng_2_field_info),
c2h_stat_dbg_dma_eng_2_field_info
},
{"C2H_STAT_DBG_DMA_ENG_3", 0xb28,
1, 0, 0, 0,
- 1, QDMA_ST_MODE, QDMA_REG_READ_PF_ONLY,
+ 0, QDMA_ST_MODE, QDMA_REG_READ_PF_ONLY,
ARRAY_SIZE(c2h_stat_dbg_dma_eng_3_field_info),
c2h_stat_dbg_dma_eng_3_field_info
},
@@ -3387,25 +3417,25 @@ static struct xreg_info eqdma_cpm5_config_regs[] = {
},
{"STAT_NUM_WRB_IN", 0xb34,
1, 0, 0, 0,
- 1, QDMA_ST_MODE, QDMA_REG_READ_PF_ONLY,
+ 0, QDMA_ST_MODE, QDMA_REG_READ_PF_ONLY,
ARRAY_SIZE(stat_num_wrb_in_field_info),
stat_num_wrb_in_field_info
},
{"STAT_NUM_WRB_OUT", 0xb38,
1, 0, 0, 0,
- 1, QDMA_ST_MODE, QDMA_REG_READ_PF_ONLY,
+ 0, QDMA_ST_MODE, QDMA_REG_READ_PF_ONLY,
ARRAY_SIZE(stat_num_wrb_out_field_info),
stat_num_wrb_out_field_info
},
{"STAT_NUM_WRB_DRP", 0xb3c,
1, 0, 0, 0,
- 1, QDMA_ST_MODE, QDMA_REG_READ_PF_ONLY,
+ 0, QDMA_ST_MODE, QDMA_REG_READ_PF_ONLY,
ARRAY_SIZE(stat_num_wrb_drp_field_info),
stat_num_wrb_drp_field_info
},
{"STAT_NUM_STAT_DESC_OUT", 0xb40,
1, 0, 0, 0,
- 1, QDMA_ST_MODE, QDMA_REG_READ_PF_ONLY,
+ 0, QDMA_ST_MODE, QDMA_REG_READ_PF_ONLY,
ARRAY_SIZE(stat_num_stat_desc_out_field_info),
stat_num_stat_desc_out_field_info
},
@@ -3663,13 +3693,13 @@ static struct xreg_info eqdma_cpm5_config_regs[] = {
},
{"C2H_STAT_HAS_CMPT_ACCEPTED", 0xbec,
1, 0, 0, 0,
- 1, QDMA_ST_MODE, QDMA_REG_READ_PF_ONLY,
+ 0, QDMA_ST_MODE, QDMA_REG_READ_PF_ONLY,
ARRAY_SIZE(c2h_stat_has_cmpt_accepted_field_info),
c2h_stat_has_cmpt_accepted_field_info
},
{"C2H_STAT_HAS_PLD_ACCEPTED", 0xbf0,
1, 0, 0, 0,
- 1, QDMA_ST_MODE, QDMA_REG_READ_PF_ONLY,
+ 0, QDMA_ST_MODE, QDMA_REG_READ_PF_ONLY,
ARRAY_SIZE(c2h_stat_has_pld_accepted_field_info),
c2h_stat_has_pld_accepted_field_info
},
@@ -3711,31 +3741,31 @@ static struct xreg_info eqdma_cpm5_config_regs[] = {
},
{"H2C_DBG_REG0", 0xe0c,
1, 0, 0, 0,
- 1, QDMA_ST_MODE, QDMA_REG_READ_PF_ONLY,
+ 0, QDMA_ST_MODE, QDMA_REG_READ_PF_ONLY,
ARRAY_SIZE(h2c_dbg_reg0_field_info),
h2c_dbg_reg0_field_info
},
{"H2C_DBG_REG1", 0xe10,
1, 0, 0, 0,
- 1, QDMA_ST_MODE, QDMA_REG_READ_PF_ONLY,
+ 0, QDMA_ST_MODE, QDMA_REG_READ_PF_ONLY,
ARRAY_SIZE(h2c_dbg_reg1_field_info),
h2c_dbg_reg1_field_info
},
{"H2C_DBG_REG2", 0xe14,
1, 0, 0, 0,
- 1, QDMA_ST_MODE, QDMA_REG_READ_PF_ONLY,
+ 0, QDMA_ST_MODE, QDMA_REG_READ_PF_ONLY,
ARRAY_SIZE(h2c_dbg_reg2_field_info),
h2c_dbg_reg2_field_info
},
{"H2C_DBG_REG3", 0xe18,
1, 0, 0, 0,
- 1, QDMA_ST_MODE, QDMA_REG_READ_PF_ONLY,
+ 0, QDMA_ST_MODE, QDMA_REG_READ_PF_ONLY,
ARRAY_SIZE(h2c_dbg_reg3_field_info),
h2c_dbg_reg3_field_info
},
{"H2C_DBG_REG4", 0xe1c,
1, 0, 0, 0,
- 1, QDMA_ST_MODE, QDMA_REG_READ_PF_ONLY,
+ 0, QDMA_ST_MODE, QDMA_REG_READ_PF_ONLY,
ARRAY_SIZE(h2c_dbg_reg4_field_info),
h2c_dbg_reg4_field_info
},
@@ -3753,7 +3783,7 @@ static struct xreg_info eqdma_cpm5_config_regs[] = {
},
{"H2C_ALN_DBG_REG0", 0xe28,
1, 0, 0, 0,
- 1, QDMA_ST_MODE, QDMA_REG_READ_PF_ONLY,
+ 0, QDMA_ST_MODE, QDMA_REG_READ_PF_ONLY,
ARRAY_SIZE(h2c_aln_dbg_reg0_field_info),
h2c_aln_dbg_reg0_field_info
},
@@ -3937,6 +3967,48 @@ static struct xreg_info eqdma_cpm5_config_regs[] = {
ARRAY_SIZE(c2h_water_mark_field_info),
c2h_water_mark_field_info
},
+{"C2H_NOTIFY_EMPTY", 0x1800,
+ 1, 0, 0, 0,
+ 0, QDMA_ST_MODE, QDMA_REG_READ_PF_ONLY,
+ ARRAY_SIZE(c2h_notify_empty_field_info),
+ c2h_notify_empty_field_info
+},
+{"C2H_STAT_S_AXIS_C2H_ACCEPTED_1", 0x1804,
+ 1, 0, 0, 0,
+ 0, QDMA_ST_MODE, QDMA_REG_READ_PF_ONLY,
+ ARRAY_SIZE(c2h_stat_s_axis_c2h_accepted_1_field_info),
+ c2h_stat_s_axis_c2h_accepted_1_field_info
+},
+{"C2H_STAT_S_AXIS_WRB_ACCEPTED_1", 0x1808,
+ 1, 0, 0, 0,
+ 0, QDMA_ST_MODE, QDMA_REG_READ_PF_ONLY,
+ ARRAY_SIZE(c2h_stat_s_axis_wrb_accepted_1_field_info),
+ c2h_stat_s_axis_wrb_accepted_1_field_info
+},
+{"C2H_STAT_DESC_RSP_PKT_ACCEPTED_1", 0x180c,
+ 1, 0, 0, 0,
+ 0, QDMA_ST_MODE, QDMA_REG_READ_PF_ONLY,
+ ARRAY_SIZE(c2h_stat_desc_rsp_pkt_accepted_1_field_info),
+ c2h_stat_desc_rsp_pkt_accepted_1_field_info
+},
+{"C2H_STAT_AXIS_PKG_CMP_1", 0x1810,
+ 1, 0, 0, 0,
+ 0, QDMA_ST_MODE, QDMA_REG_READ_PF_ONLY,
+ ARRAY_SIZE(c2h_stat_axis_pkg_cmp_1_field_info),
+ c2h_stat_axis_pkg_cmp_1_field_info
+},
+{"C2H_STAT_S_AXIS_WRB_ACCEPTED_2", 0x1814,
+ 1, 0, 0, 0,
+ 0, QDMA_ST_MODE, QDMA_REG_READ_PF_ONLY,
+ ARRAY_SIZE(c2h_stat_s_axis_wrb_accepted_2_field_info),
+ c2h_stat_s_axis_wrb_accepted_2_field_info
+},
+{"C2H_ST_PLD_FIFO_DEPTH", 0x1818,
+ 1, 0, 0, 0,
+ 0, QDMA_ST_MODE, QDMA_REG_READ_PF_ONLY,
+ ARRAY_SIZE(c2h_st_pld_fifo_depth_field_info),
+ c2h_st_pld_fifo_depth_field_info
+},
};
diff --git a/QDMA/DPDK/drivers/net/qdma/qdma_access/eqdma_soft_access/eqdma_soft_access.c b/QDMA/DPDK/drivers/net/qdma/qdma_access/eqdma_soft_access/eqdma_soft_access.c
old mode 100644
new mode 100755
index 15b2086a0368daa3138b3070ce3890b83d496100..2be31a0eb2ff6dcf03a7ab0bd7b245b685753edc
--- a/QDMA/DPDK/drivers/net/qdma/qdma_access/eqdma_soft_access/eqdma_soft_access.c
+++ b/QDMA/DPDK/drivers/net/qdma/qdma_access/eqdma_soft_access/eqdma_soft_access.c
@@ -1,5 +1,6 @@
/*
- * Copyright(c) 2019-2022 Xilinx, Inc. All rights reserved.
+ * Copyright (c) 2019-2022, Xilinx, Inc. All rights reserved.
+ * Copyright (c) 2022, Advanced Micro Devices, Inc. All rights reserved.
*
* BSD LICENSE
*
@@ -65,12 +66,23 @@
#define EQDMA_MM_C2H_ERR_ALL_MASK 0X70000003
#define EQDMA_MM_H2C0_ERR_ALL_MASK 0X3041013E
-/* H2C Throttle settings */
+/* H2C Throttle settings for QDMA 4.0 */
#define EQDMA_H2C_THROT_DATA_THRESH 0x5000
#define EQDMA_THROT_EN_DATA 1
#define EQDMA_THROT_EN_REQ 0
#define EQDMA_H2C_THROT_REQ_THRESH 0xC0
+/* H2C Throttle settings for QDMA 5.0 */
+#define EQDMA5_H2C_THROT_DATA_THRESH 0x5000
+#define EQDMA5_THROT_EN_DATA 1
+#define EQDMA5_THROT_EN_REQ 1
+#define EQDMA5_H2C_THROT_REQ_THRESH 0xC0
+
+/* CSR Default values for QDMA 5.0 */
+#define EQDMA5_DEFAULT_H2C_UODSC_LIMIT 4
+#define EQDMA5_DEFAULT_MAX_DSC_FETCH 3
+#define EQDMA5_DEFAULT_WRB_INT QDMA_WRB_INTERVAL_128
+
/** Auxillary Bitmasks for fields spanning multiple words */
#define EQDMA_SW_CTXT_PASID_GET_H_MASK GENMASK(21, 12)
#define EQDMA_SW_CTXT_PASID_GET_L_MASK GENMASK(11, 0)
@@ -100,6 +112,9 @@
#define EQDMA_FMAP_CTXT_W1_QID_MAX_MASK GENMASK(11, 0)
#define EQDMA_FMAP_CTXT_W0_QID_MASK GENMASK(10, 0)
+#define EQDMA_GLBL2_IP_VERSION_MASK GENMASK(23, 20)
+#define EQDMA_GLBL2_VF_IP_VERSION_MASK GENMASK(7, 4)
+
static void eqdma_hw_st_h2c_err_process(void *dev_hndl);
static void eqdma_hw_st_c2h_err_process(void *dev_hndl);
static void eqdma_hw_desc_err_process(void *dev_hndl);
@@ -1893,6 +1908,34 @@ static int eqdma_indirect_reg_write(void *dev_hndl, enum ind_ctxt_cmd_sel sel,
return QDMA_SUCCESS;
}
+int eqdma_get_ip_version(void *dev_hndl, uint8_t is_vf,
+ uint32_t *ip_version)
+{
+ uint32_t ver_reg_val = 0;
+ uint32_t reg_addr = (is_vf) ? EQDMA_OFFSET_VF_VERSION :
+ EQDMA_GLBL2_MISC_CAP_ADDR;
+
+ if (!dev_hndl) {
+ qdma_log_error("%s: dev_handle is NULL, err:%d\n",
+ __func__, -QDMA_ERR_INV_PARAM);
+ return -QDMA_ERR_INV_PARAM;
+ }
+
+ ver_reg_val = qdma_reg_read(dev_hndl, reg_addr);
+
+ if (!is_vf) {
+ *ip_version =
+ FIELD_GET(EQDMA_GLBL2_IP_VERSION_MASK,
+ ver_reg_val);
+ } else {
+ *ip_version =
+ FIELD_GET(EQDMA_GLBL2_VF_IP_VERSION_MASK,
+ ver_reg_val);
+ }
+
+ return QDMA_SUCCESS;
+}
+
/*
* eqdma_fill_sw_ctxt() - Helper function to fill sw context into structure
*
@@ -2072,6 +2115,8 @@ static void eqdma_fill_intr_ctxt(struct qdma_indirect_intr_ctxt *intr_ctxt)
*****************************************************************************/
int eqdma_set_default_global_csr(void *dev_hndl)
{
+ int rv = QDMA_SUCCESS;
+
/* Default values */
uint32_t cfg_val = 0, reg_val = 0;
uint32_t rng_sz[QDMA_NUM_RING_SIZES] = {2049, 65, 129, 193, 257, 385,
@@ -2084,6 +2129,7 @@ int eqdma_set_default_global_csr(void *dev_hndl)
2048, 3968, 4096, 4096, 4096, 4096, 4096, 4096, 4096, 8192,
9018, 16384};
struct qdma_dev_attributes dev_cap;
+ uint32_t eqdma_ip_version;
if (!dev_hndl) {
qdma_log_error("%s: dev_handle is NULL, err:%d\n", __func__,
@@ -2093,6 +2139,10 @@ int eqdma_set_default_global_csr(void *dev_hndl)
eqdma_get_device_attributes(dev_hndl, &dev_cap);
+ rv = eqdma_get_ip_version(dev_hndl, 0, &eqdma_ip_version);
+ if (rv != QDMA_SUCCESS)
+ return rv;
+
/* Configuring CSR registers */
/* Global ring sizes */
qdma_write_csr_values(dev_hndl, EQDMA_GLBL_RNG_SZ_1_ADDR, 0,
@@ -2107,13 +2157,30 @@ int eqdma_set_default_global_csr(void *dev_hndl)
qdma_write_csr_values(dev_hndl, EQDMA_C2H_TIMER_CNT_ADDR, 0,
QDMA_NUM_C2H_TIMERS, tmr_cnt);
-
/* Writeback Interval */
- reg_val =
- FIELD_SET(GLBL_DSC_CFG_MAXFETCH_MASK,
- DEFAULT_MAX_DSC_FETCH) |
- FIELD_SET(GLBL_DSC_CFG_WB_ACC_INT_MASK,
- DEFAULT_WRB_INT);
+ if (eqdma_ip_version == EQDMA_IP_VERSION_4) {
+ reg_val =
+ FIELD_SET(GLBL_DSC_CFG_MAXFETCH_MASK,
+ DEFAULT_MAX_DSC_FETCH) |
+ FIELD_SET(GLBL_DSC_CFG_WB_ACC_INT_MASK,
+ DEFAULT_WRB_INT);
+ } else if (eqdma_ip_version == EQDMA_IP_VERSION_5) {
+ /* For QDMA4.0 and QDMA5.0, HW design and register map
+ * is same except some performance optimizations
+ */
+ reg_val =
+ FIELD_SET(GLBL_DSC_CFG_H2C_UODSC_LIMIT_MASK,
+ EQDMA5_DEFAULT_H2C_UODSC_LIMIT) |
+ FIELD_SET(GLBL_DSC_CFG_MAXFETCH_MASK,
+ EQDMA5_DEFAULT_MAX_DSC_FETCH) |
+ FIELD_SET(GLBL_DSC_CFG_WB_ACC_INT_MASK,
+ EQDMA5_DEFAULT_WRB_INT);
+ } else {
+ qdma_log_error("%s: ip_type = %d is invalid, err:%d\n",
+ __func__, eqdma_ip_version,
+ -QDMA_ERR_INV_PARAM);
+ return -QDMA_ERR_INV_PARAM;
+ }
qdma_reg_write(dev_hndl, EQDMA_GLBL_DSC_CFG_ADDR, reg_val);
}
@@ -2151,16 +2218,35 @@ int eqdma_set_default_global_csr(void *dev_hndl)
qdma_reg_write(dev_hndl, EQDMA_C2H_WRB_COAL_CFG_ADDR, reg_val);
/* H2C throttle Configuration*/
-
- reg_val =
- FIELD_SET(H2C_REQ_THROT_PCIE_DATA_THRESH_MASK,
- EQDMA_H2C_THROT_DATA_THRESH) |
- FIELD_SET(H2C_REQ_THROT_PCIE_EN_DATA_MASK,
- EQDMA_THROT_EN_DATA) |
- FIELD_SET(H2C_REQ_THROT_PCIE_MASK,
- EQDMA_H2C_THROT_REQ_THRESH) |
- FIELD_SET(H2C_REQ_THROT_PCIE_EN_REQ_MASK,
- EQDMA_THROT_EN_REQ);
+ if (eqdma_ip_version == EQDMA_IP_VERSION_4) {
+ reg_val =
+ FIELD_SET(H2C_REQ_THROT_PCIE_DATA_THRESH_MASK,
+ EQDMA_H2C_THROT_DATA_THRESH) |
+ FIELD_SET(H2C_REQ_THROT_PCIE_EN_DATA_MASK,
+ EQDMA_THROT_EN_DATA) |
+ FIELD_SET(H2C_REQ_THROT_PCIE_MASK,
+ EQDMA_H2C_THROT_REQ_THRESH) |
+ FIELD_SET(H2C_REQ_THROT_PCIE_EN_REQ_MASK,
+ EQDMA_THROT_EN_REQ);
+ } else if (eqdma_ip_version == EQDMA_IP_VERSION_5) {
+ /* For QDMA4.0 and QDMA5.0, HW design and register map
+ * is same except some performance optimizations
+ */
+ reg_val =
+ FIELD_SET(H2C_REQ_THROT_PCIE_DATA_THRESH_MASK,
+ EQDMA5_H2C_THROT_DATA_THRESH) |
+ FIELD_SET(H2C_REQ_THROT_PCIE_EN_DATA_MASK,
+ EQDMA5_THROT_EN_DATA) |
+ FIELD_SET(H2C_REQ_THROT_PCIE_MASK,
+ EQDMA5_H2C_THROT_REQ_THRESH) |
+ FIELD_SET(H2C_REQ_THROT_PCIE_EN_REQ_MASK,
+ EQDMA5_THROT_EN_REQ);
+ } else {
+ qdma_log_error("%s: ip_type = %d is invalid, err:%d\n",
+ __func__, eqdma_ip_version,
+ -QDMA_ERR_INV_PARAM);
+ return -QDMA_ERR_INV_PARAM;
+ }
qdma_reg_write(dev_hndl, EQDMA_H2C_REQ_THROT_PCIE_ADDR,
reg_val);
}
@@ -2762,7 +2848,7 @@ int eqdma_get_version(void *dev_hndl, uint8_t is_vf,
reg_val = qdma_reg_read(dev_hndl, reg_addr);
- qdma_fetch_version_details(is_vf, reg_val, version_info);
+ qdma_fetch_version_details(dev_hndl, is_vf, reg_val, version_info);
return QDMA_SUCCESS;
}
diff --git a/QDMA/DPDK/drivers/net/qdma/qdma_access/eqdma_soft_access/eqdma_soft_access.h b/QDMA/DPDK/drivers/net/qdma/qdma_access/eqdma_soft_access/eqdma_soft_access.h
old mode 100644
new mode 100755
index d8f60783be42472977d460b2d9cc79e4d3dc4f4b..b2df4fe19b43bd1ccada99a32e6719d31ea12439
--- a/QDMA/DPDK/drivers/net/qdma/qdma_access/eqdma_soft_access/eqdma_soft_access.h
+++ b/QDMA/DPDK/drivers/net/qdma/qdma_access/eqdma_soft_access/eqdma_soft_access.h
@@ -1,5 +1,6 @@
/*
- * Copyright(c) 2019-2022 Xilinx, Inc. All rights reserved.
+ * Copyright (c) 2019-2022, Xilinx, Inc. All rights reserved.
+ * Copyright (c) 2022, Advanced Micro Devices, Inc. All rights reserved.
*
* BSD LICENSE
*
@@ -233,6 +234,13 @@ struct eqdma_hw_err_info {
void (*eqdma_hw_err_process)(void *dev_hndl);
};
+/* In QDMA_GLBL2_MISC_CAP(0x134) register,
+ * Bits [23:20] gives QDMA IP version.
+ * 0: QDMA3.1, 1: QDMA4.0, 2: QDMA5.0
+ */
+#define EQDMA_IP_VERSION_4 1
+#define EQDMA_IP_VERSION_5 2
+
#define EQDMA_OFFSET_VF_VERSION 0x5014
#define EQDMA_OFFSET_VF_USER_BAR 0x5018
@@ -248,6 +256,9 @@ int eqdma_init_ctxt_memory(void *dev_hndl);
int eqdma_get_version(void *dev_hndl, uint8_t is_vf,
struct qdma_hw_version_info *version_info);
+int eqdma_get_ip_version(void *dev_hndl, uint8_t is_vf,
+ uint32_t *ip_version);
+
int eqdma_sw_ctx_conf(void *dev_hndl, uint8_t c2h, uint16_t hw_qid,
struct qdma_descq_sw_ctxt *ctxt,
enum qdma_hw_access_type access_type);
diff --git a/QDMA/DPDK/drivers/net/qdma/qdma_access/eqdma_soft_access/eqdma_soft_reg.h b/QDMA/DPDK/drivers/net/qdma/qdma_access/eqdma_soft_access/eqdma_soft_reg.h
old mode 100644
new mode 100755
index 95792170057447fb21d6c955b5b017f4b7d82926..4f326ea026a2e8eae2ae6f50c1824fe747434c9c
--- a/QDMA/DPDK/drivers/net/qdma/qdma_access/eqdma_soft_access/eqdma_soft_reg.h
+++ b/QDMA/DPDK/drivers/net/qdma/qdma_access/eqdma_soft_access/eqdma_soft_reg.h
@@ -1,5 +1,6 @@
/*
- * Copyright(c) 2019-2022 Xilinx, Inc. All rights reserved.
+ * Copyright (c) 2019-2022 Xilinx, Inc. All rights reserved.
+ * Copyright (c) 2022, Advanced Micro Devices, Inc. All rights reserved.
*
* BSD LICENSE
*
@@ -271,6 +272,35 @@ struct xreg_info *eqdma_config_regs_get(void);
#define GLBL2_SYSTEM_ID_MASK GENMASK(15, 0)
#define EQDMA_GLBL2_MISC_CAP_ADDR 0x134
#define GLBL2_MISC_CAP_MASK GENMASK(31, 0)
+#define EQDMA_GLBL2_RRQ_BRG_THROT_ADDR 0x158
+#define GLBL2_RRQ_BRG_THROT_REQ_EN_MASK BIT(31)
+#define GLBL2_RRQ_BRG_THROT_REQ_MASK GENMASK(30, 19)
+#define GLBL2_RRQ_BRG_THROT_DAT_EN_MASK BIT(18)
+#define GLBL2_RRQ_BRG_THROT_DAT_MASK GENMASK(17, 0)
+#define EQDMA_GLBL2_RRQ_PCIE_THROT_ADDR 0x15C
+#define GLBL2_RRQ_PCIE_THROT_REQ_EN_MASK BIT(31)
+#define GLBL2_RRQ_PCIE_THROT_REQ_MASK GENMASK(30, 19)
+#define GLBL2_RRQ_PCIE_THROT_DAT_EN_MASK BIT(18)
+#define GLBL2_RRQ_PCIE_THROT_DAT_MASK GENMASK(17, 0)
+#define EQDMA_GLBL2_RRQ_AXIMM_THROT_ADDR 0x160
+#define GLBL2_RRQ_AXIMM_THROT_REQ_EN_MASK BIT(31)
+#define GLBL2_RRQ_AXIMM_THROT_REQ_MASK GENMASK(30, 19)
+#define GLBL2_RRQ_AXIMM_THROT_DAT_EN_MASK BIT(18)
+#define GLBL2_RRQ_AXIMM_THROT_DAT_MASK GENMASK(17, 0)
+#define EQDMA_GLBL2_RRQ_PCIE_LAT0_ADDR 0x164
+#define GLBL2_RRQ_PCIE_LAT0_MAX_MASK GENMASK(31, 16)
+#define GLBL2_RRQ_PCIE_LAT0_MIN_MASK GENMASK(15, 0)
+#define EQDMA_GLBL2_RRQ_PCIE_LAT1_ADDR 0x168
+#define GLBL2_RRQ_PCIE_LAT1_RSVD_MASK GENMASK(31, 17)
+#define GLBL2_RRQ_PCIE_LAT1_OVFL_MASK BIT(16)
+#define GLBL2_RRQ_PCIE_LAT1_AVG_MASK GENMASK(15, 0)
+#define EQDMA_GLBL2_RRQ_AXIMM_LAT0_ADDR 0x16C
+#define GLBL2_RRQ_AXIMM_LAT0_MAX_MASK GENMASK(31, 16)
+#define GLBL2_RRQ_AXIMM_LAT0_MIN_MASK GENMASK(15, 0)
+#define EQDMA_GLBL2_RRQ_AXIMM_LAT1_ADDR 0x170
+#define GLBL2_RRQ_AXIMM_LAT1_RSVD_MASK GENMASK(31, 17)
+#define GLBL2_RRQ_AXIMM_LAT1_OVFL_MASK BIT(16)
+#define GLBL2_RRQ_AXIMM_LAT1_AVG_MASK GENMASK(15, 0)
#define EQDMA_GLBL2_DBG_PCIE_RQ0_ADDR 0x1B8
#define GLBL2_PCIE_RQ0_NPH_AVL_MASK GENMASK(31, 20)
#define GLBL2_PCIE_RQ0_RCB_AVL_MASK GENMASK(19, 9)
@@ -447,7 +477,9 @@ struct xreg_info *eqdma_config_regs_get(void);
#define EQDMA_GLBL_ERR_MASK_ADDR 0x24C
#define GLBL_ERR_MASK GENMASK(31, 0)
#define EQDMA_GLBL_DSC_CFG_ADDR 0x250
-#define GLBL_DSC_CFG_RSVD_1_MASK GENMASK(31, 10)
+#define GLBL_DSC_CFG_RSVD_1_MASK GENMASK(31, 30)
+#define GLBL_DSC_CFG_C2H_UODSC_LIMIT_MASK GENMASK(29, 20)
+#define GLBL_DSC_CFG_H2C_UODSC_LIMIT_MASK GENMASK(19, 10)
#define GLBL_DSC_CFG_UNC_OVR_COR_MASK BIT(9)
#define GLBL_DSC_CFG_CTXT_FER_DIS_MASK BIT(8)
#define GLBL_DSC_CFG_RSVD_2_MASK GENMASK(7, 6)
@@ -521,7 +553,9 @@ struct xreg_info *eqdma_config_regs_get(void);
#define GLBL_DSC_DAT1_DSC_SPC_C2H_MASK GENMASK(15, 8)
#define GLBL_DSC_DAT1_DSC_SPC_H2C_MASK GENMASK(7, 0)
#define EQDMA_GLBL_DSC_DBG_CTL_ADDR 0x278
-#define GLBL_DSC_CTL_RSVD_1_MASK GENMASK(31, 3)
+#define GLBL_DSC_CTL_RSVD_1_MASK GENMASK(31, 16)
+#define GLBL_DSC_CTL_LAT_QID_MASK GENMASK(15, 4)
+#define GLBL_DSC_CTL_DSC_ENG_LAT_CLR_MASK BIT(3)
#define GLBL_DSC_CTL_SELECT_MASK GENMASK(2, 0)
#define EQDMA_GLBL_DSC_ERR_LOG2_ADDR 0x27c
#define GLBL_DSC_ERR_LOG2_OLD_PIDX_MASK GENMASK(31, 16)
@@ -562,6 +596,183 @@ struct xreg_info *eqdma_config_regs_get(void);
#define GLBL_REQ_ERR_STS_RC_POISONED_MASK BIT(0)
#define EQDMA_GLBL_REQ_ERR_MSK_ADDR 0x31C
#define GLBL_REQ_ERR_MSK_MASK GENMASK(31, 0)
+#define EQDMA_GLBL_DSC_DBG_LAT0_A_ADDR 0x320
+#define GLBL_DSC_LAT0_A_LAT_MAX_MASK GENMASK(31, 16)
+#define GLBL_DSC_LAT0_A_LAT_MIN_MASK GENMASK(15, 0)
+#define EQDMA_GLBL_DSC_DBG_LAT1_A_ADDR 0x324
+#define GLBL_DSC_LAT1_A_RSVD_MASK GENMASK(31, 17)
+#define GLBL_DSC_LAT1_A_LAT_OVF_MASK BIT(16)
+#define GLBL_DSC_LAT1_A_LAT_AVG_MASK GENMASK(15, 0)
+#define EQDMA_GLBL_DSC_CRD_CTR0_A_ADDR 0x328
+#define GLBL_DSC_CRD_CTR0_A_CRD_RCV_CNT_MASK GENMASK(31, 0)
+#define EQDMA_GLBL_DSC_CRD_CTR1_A_ADDR 0x32C
+#define GLBL_DSC_CRD_CTR1_A_CRD_RCV_CNT_MASK GENMASK(31, 0)
+#define EQDMA_GLBL_DSC_CRD_CTR2_A_ADDR 0x330
+#define GLBL_DSC_CRD_CTR2_A_CRD_RCV_NRDY_CNT_MASK GENMASK(31, 0)
+#define EQDMA_GLBL_DSC_CRD_CTR3_A_ADDR 0x334
+#define GLBL_DSC_CRD_CTR3_A_CRD_RCV_NRDY_CNT_MASK GENMASK(31, 0)
+#define EQDMA_GLBL_DSC_IMM_CRD_CTR0_A_ADDR 0x338
+#define GLBL_DSC_IMM_CRD_CTR0_A_RCV_CNT_MASK GENMASK(31, 0)
+#define EQDMA_GLBL_DSC_IMM_CRD_CTR1_A_ADDR 0x33C
+#define GLBL_DSC_IMM_CRD_CTR1_A_RCV_CNT_MASK GENMASK(31, 0)
+#define EQDMA_GLBL_DSC_IMM_CRD_CTR2_A_ADDR 0x340
+#define GLBL_DSC_IMM_CRD_CTR2_A_RCV_NRDY_CNT_MASK GENMASK(31, 0)
+#define EQDMA_GLBL_DSC_IMM_CRD_CTR3_A_ADDR 0x344
+#define GLBL_DSC_IMM_CRD_CTR3_A_RCV_NRDY_CNT_MASK GENMASK(31, 0)
+#define EQDMA_GLBL_DSC_H2C_OUT_CTR0_A_ADDR 0x348
+#define GLBL_DSC_H2C_OUT_CTR0_A_H2CVLD_CNT_MASK GENMASK(31, 0)
+#define EQDMA_GLBL_DSC_H2C_OUT_CTR1_A_ADDR 0x34C
+#define GLBL_DSC_H2C_OUT_CTR1_A_H2CVLD_CNT_MASK GENMASK(31, 0)
+#define EQDMA_GLBL_DSC_H2C_OUT_CTR2_A_ADDR 0x350
+#define GLBL_DSC_H2C_OUT_CTR2_A_H2CVLD_NRDY_CNT_MASK GENMASK(31, 0)
+#define EQDMA_GLBL_DSC_H2C_OUT_CTR3_A_ADDR 0x354
+#define GLBL_DSC_H2C_OUT_CTR3_A_H2CVLD_NRDY_CNT_MASK GENMASK(31, 0)
+#define EQDMA_GLBL_DSC_C2H_OUT_CTR0_A_ADDR 0x358
+#define GLBL_DSC_C2H_OUT_CTR0_A_C2HVLD_CNT_MASK GENMASK(31, 0)
+#define EQDMA_GLBL_DSC_C2H_OUT_CTR1_A_ADDR 0x35C
+#define GLBL_DSC_C2H_OUT_CTR1_A_C2HVLD_CNT_MASK GENMASK(31, 0)
+#define EQDMA_GLBL_DSC_C2H_OUT_CTR2_A_ADDR 0x360
+#define GLBL_DSC_C2H_OUT_CTR2_A_C2HVLD_NRDY_CNT_MASK GENMASK(31, 0)
+#define EQDMA_GLBL_DSC_C2H_OUT_CTR3_A_ADDR 0x364
+#define GLBL_DSC_C2H_OUT_CTR3_A_C2HVLD_NRDY_CNT_MASK GENMASK(31, 0)
+#define EQDMA_T_ADDR 0x368
+#define T_USER_CTR_MAX_MASK GENMASK(31, 0)
+#define EQDMA_GLBL_PERF_CNTR_CTL_A1_ADDR 0x36C
+#define GLBL_PERF_CNTR_CTL_A1_RSVD_MASK GENMASK(31, 18)
+#define GLBL_PERF_CNTR_CTL_A1_USER_CTR_CLEAR_MASK BIT(17)
+#define GLBL_PERF_CNTR_CTL_A1_USER_CTR_READ_MASK BIT(16)
+#define GLBL_PERF_CNTR_CTL_A1_USER_CTR_MAX_MASK GENMASK(15, 0)
+#define EQDMA_GLBL_FREE_CNT_A0_ADDR 0x370
+#define GLBL_FREE_CNT_A0_S_MASK GENMASK(31, 0)
+#define EQDMA_GLBL_FREE_CNT_A1_ADDR 0x374
+#define GLBL_FREE_CNT_A1_RSVD_MASK GENMASK(31, 16)
+#define GLBL_FREE_CNT_A1_S_MASK GENMASK(15, 0)
+#define EQDMA_GLBL_AXIS_H2C_CNT_A0_ADDR 0x378
+#define GLBL_AXIS_H2C_CNT_A0_MPKT_CNTS_MASK GENMASK(31, 0)
+#define EQDMA_GLBL_AXIS_H2C_CNT_A1_ADDR 0x37C
+#define GLBL_AXIS_H2C_CNT_A1_MIDLE_CNTS_MASK GENMASK(15, 0)
+#define GLBL_AXIS_H2C_CNT_A1_MPKT_CNTS_MASK GENMASK(15, 0)
+#define EQDMA_GLBL_AXIS_H2C_CNT_A2_ADDR 0x380
+#define GLBL_AXIS_H2C_CNT_A2_MIDLE_CNTS_MASK GENMASK(31, 0)
+#define EQDMA_GLBL_AXIS_H2C_CNT_A3_ADDR 0x384
+#define GLBL_AXIS_H2C_CNT_A3_MACTV_CNTS_MASK GENMASK(31, 0)
+#define EQDMA_GLBL_AXIS_H2C_CNT_A4_ADDR 0x388
+#define GLBL_AXIS_H2C_CNT_A4_MBUSY_CNTS_MASK GENMASK(15, 0)
+#define GLBL_AXIS_H2C_CNT_A4_MACTV_CNTS_MASK GENMASK(15, 0)
+#define EQDMA_GLBL_AXIS_H2C_CNT_A5_ADDR 0x38C
+#define GLBL_AXIS_H2C_CNT_A5_MBUSY_CNTS_MASK GENMASK(31, 0)
+#define EQDMA_GLBL_AXIS_C2H_CNT_A0_ADDR 0x390
+#define GLBL_AXIS_C2H_CNT_A0_SPKT_CNTS_MASK GENMASK(31, 0)
+#define EQDMA_GLBL_AXIS_C2H_CNT_A1_ADDR 0x394
+#define GLBL_AXIS_C2H_CNT_A1_SIDLE_CNTS_MASK GENMASK(15, 0)
+#define GLBL_AXIS_C2H_CNT_A1_SPKT_CNTS_MASK GENMASK(15, 0)
+#define EQDMA_GLBL_AXIS_C2H_CNT_A2_ADDR 0x398
+#define GLBL_AXIS_C2H_CNT_A2_SIDLE_CNTS_MASK GENMASK(31, 0)
+#define EQDMA_GLBL_AXIS_C2H_CNT_A3_ADDR 0x39C
+#define GLBL_AXIS_C2H_CNT_A3_SACTV_CNTS_MASK GENMASK(31, 0)
+#define EQDMA_GLBL_AXIS_C2H_CNT_A4_ADDR 0x3A0
+#define GLBL_AXIS_C2H_CNT_A4_SBUSY_CNTS_MASK GENMASK(15, 0)
+#define GLBL_AXIS_C2H_CNT_A4_SACTV_CNTS_MASK GENMASK(15, 0)
+#define EQDMA_GLBL_AXIS_C2H_CNT_A5_ADDR 0x3A4
+#define GLBL_AXIS_C2H_CNT_A5_SBUSY_CNTS_MASK GENMASK(31, 0)
+#define EQDMA_GLBL_M_AXI_WR_CNT_A0_ADDR 0x3A8
+#define GLBL_M_AXI_WR_CNT_A0_PKT_CNTS_MASK GENMASK(31, 0)
+#define EQDMA_GLBL_M_AXI_WR_CNT_A1_ADDR 0x3AC
+#define GLBL_M_AXI_WR_CNT_A1_IDLE_CNTS_MASK GENMASK(15, 0)
+#define GLBL_M_AXI_WR_CNT_A1_PKT_CNTS_MASK GENMASK(15, 0)
+#define EQDMA_GLBL_M_AXI_WR_CNT_A2_ADDR 0x3B0
+#define GLBL_M_AXI_WR_CNT_A2_IDLE_CNTS_MASK GENMASK(31, 0)
+#define EQDMA_GLBL_M_AXI_WR_CNT_A3_ADDR 0x3B4
+#define GLBL_M_AXI_WR_CNT_A3_ACTV_CNTS_MASK GENMASK(31, 0)
+#define EQDMA_GLBL_M_AXI_WR_CNT_A4_ADDR 0x3B8
+#define GLBL_M_AXI_WR_CNT_A4_BUSY_CNTS_MASK GENMASK(15, 0)
+#define GLBL_M_AXI_WR_CNT_A4_ACTV_CNTS_MASK GENMASK(15, 0)
+#define EQDMA_GLBL_M_AXI_WR_CNT_A5_ADDR 0x3BC
+#define GLBL_M_AXI_WR_CNT_A5_BUSY_CNTS_MASK GENMASK(31, 0)
+#define EQDMA_GLBL_M_AXI_RD_CNT_A0_ADDR 0x3C0
+#define GLBL_M_AXI_RD_CNT_A0_PKT_CNTS_MASK GENMASK(31, 0)
+#define EQDMA_GLBL_M_AXI_RD_CNT_A1_ADDR 0x3C4
+#define GLBL_M_AXI_RD_CNT_A1_IDLE_CNTS_MASK GENMASK(15, 0)
+#define GLBL_M_AXI_RD_CNT_A1_PKT_CNTS_MASK GENMASK(15, 0)
+#define EQDMA_GLBL_M_AXI_RD_CNT_A2_ADDR 0x3C8
+#define GLBL_M_AXI_RD_CNT_A2_IDLE_CNTS_MASK GENMASK(31, 0)
+#define EQDMA_GLBL_M_AXI_RD_CNT_A3_ADDR 0x3CC
+#define GLBL_M_AXI_RD_CNT_A3_ACTV_CNTS_MASK GENMASK(31, 0)
+#define EQDMA_GLBL_M_AXI_RD_CNT_A4_ADDR 0x3D0
+#define GLBL_M_AXI_RD_CNT_A4_BUSY_CNTS_MASK GENMASK(15, 0)
+#define GLBL_M_AXI_RD_CNT_A4_ACTV_CNTS_MASK GENMASK(15, 0)
+#define EQDMA_GLBL_M_AXI_RD_CNT_A5_ADDR 0x3D4
+#define GLBL_M_AXI_RD_CNT_A5_BUSY_CNTS_MASK GENMASK(31, 0)
+#define EQDMA_GLBL_M_AXIB_WR_CNT_A0_ADDR 0x3D8
+#define GLBL_M_AXIB_WR_CNT_A0_PKT_CNTS_MASK GENMASK(31, 0)
+#define EQDMA_GLBL_M_AXIB_WR_CNT_A1_ADDR 0x3DC
+#define GLBL_M_AXIB_WR_CNT_A1_IDLE_CNTS_MASK GENMASK(15, 0)
+#define GLBL_M_AXIB_WR_CNT_A1_PKT_CNTS_MASK GENMASK(15, 0)
+#define EQDMA_GLBL_M_AXIB_WR_CNT_A2_ADDR 0x3E0
+#define GLBL_M_AXIB_WR_CNT_A2_IDLE_CNTS_MASK GENMASK(31, 0)
+#define EQDMA_GLBL_M_AXIB_WR_CNT_A3_ADDR 0x3E4
+#define GLBL_M_AXIB_WR_CNT_A3_ACTV_CNTS_MASK GENMASK(31, 0)
+#define EQDMA_GLBL_M_AXIB_WR_CNT_A4_ADDR 0x3E8
+#define GLBL_M_AXIB_WR_CNT_A4_BUSY_CNTS_MASK GENMASK(15, 0)
+#define GLBL_M_AXIB_WR_CNT_A4_ACTV_CNTS_MASK GENMASK(15, 0)
+#define EQDMA_GLBL_M_AXIB_WR_CNT_A5_ADDR 0x3EC
+#define GLBL_M_AXIB_WR_CNT_A5_BUSY_CNTS_MASK GENMASK(31, 0)
+#define EQDMA_GLBL_M_AXIB_RD_CNT_A0_ADDR 0x3F0
+#define GLBL_M_AXIB_RD_CNT_A0_PKT_CNTS_MASK GENMASK(31, 0)
+#define EQDMA_GLBL_M_AXIB_RD_CNT_A1_ADDR 0x3F4
+#define GLBL_M_AXIB_RD_CNT_A1_IDLE_CNTS_MASK GENMASK(15, 0)
+#define GLBL_M_AXIB_RD_CNT_A1_PKT_CNTS_MASK GENMASK(15, 0)
+#define EQDMA_GLBL_M_AXIB_RD_CNT_A2_ADDR 0x3F8
+#define GLBL_M_AXIB_RD_CNT_A2_IDLE_CNTS_MASK GENMASK(31, 0)
+#define EQDMA_GLBL_M_AXIB_RD_CNT_A3_ADDR 0x3FC
+#define GLBL_M_AXIB_RD_CNT_A3_ACTV_CNTS_MASK GENMASK(31, 0)
+#define EQDMA_GLBL_M_AXIB_RD_CNT_A4_ADDR 0x400
+#define GLBL_M_AXIB_RD_CNT_A4_BUSY_CNTS_MASK GENMASK(15, 0)
+#define GLBL_M_AXIB_RD_CNT_A4_ACTV_CNTS_MASK GENMASK(15, 0)
+#define EQDMA_GLBL_M_AXIB_RD_CNT_A5_ADDR 0x404
+#define GLBL_M_AXIB_RD_CNT_A5_BUSY_CNTS_MASK GENMASK(31, 0)
+#define EQDMA_GLBL_S_AXI_WR_CNT_A0_ADDR 0x408
+#define GLBL_S_AXI_WR_CNT_A0_PKT_CNTS_MASK GENMASK(31, 0)
+#define EQDMA_GLBL_S_AXI_WR_CNT_A1_ADDR 0x40C
+#define GLBL_S_AXI_WR_CNT_A1_IDLE_CNTS_MASK GENMASK(15, 0)
+#define GLBL_S_AXI_WR_CNT_A1_PKT_CNTS_MASK GENMASK(15, 0)
+#define EQDMA_GLBL_S_AXI_WR_CNT_A2_ADDR 0x410
+#define GLBL_S_AXI_WR_CNT_A2_IDLE_CNTS_MASK GENMASK(31, 0)
+#define EQDMA_GLBL_S_AXI_WR_CNT_A3_ADDR 0x414
+#define GLBL_S_AXI_WR_CNT_A3_ACTV_CNTS_MASK GENMASK(31, 0)
+#define EQDMA_GLBL_S_AXI_WR_CNT_A4_ADDR 0x418
+#define GLBL_S_AXI_WR_CNT_A4_BUSY_CNTS_MASK GENMASK(15, 0)
+#define GLBL_S_AXI_WR_CNT_A4_ACTV_CNTS_MASK GENMASK(15, 0)
+#define EQDMA_GLBL_S_AXI_WR_CNT_A5_ADDR 0x41C
+#define GLBL_S_AXI_WR_CNT_A5_BUSY_CNTS_MASK GENMASK(31, 0)
+#define EQDMA_GLBL_S_AXI_RD_CNT_A0_ADDR 0x420
+#define GLBL_S_AXI_RD_CNT_A0_PKT_CNTS_MASK GENMASK(31, 0)
+#define EQDMA_GLBL_S_AXI_RD_CNT_A1_ADDR 0x424
+#define GLBL_S_AXI_RD_CNT_A1_IDLE_CNTS_MASK GENMASK(15, 0)
+#define GLBL_S_AXI_RD_CNT_A1_PKT_CNTS_MASK GENMASK(15, 0)
+#define EQDMA_GLBL_S_AXI_RD_CNT_A2_ADDR 0x428
+#define GLBL_S_AXI_RD_CNT_A2_IDLE_CNTS_MASK GENMASK(31, 0)
+#define EQDMA_GLBL_S_AXI_RD_CNT_A3_ADDR 0x42C
+#define GLBL_S_AXI_RD_CNT_A3_ACTV_CNTS_MASK GENMASK(31, 0)
+#define EQDMA_GLBL_S_AXI_RD_CNT_A4_ADDR 0x430
+#define GLBL_S_AXI_RD_CNT_A4_BUSY_CNTS_MASK GENMASK(15, 0)
+#define GLBL_S_AXI_RD_CNT_A4_ACTV_CNTS_MASK GENMASK(15, 0)
+#define EQDMA_GLBL_S_AXI_RD_CNT_A5_ADDR 0x434
+#define GLBL_S_AXI_RD_CNT_A5_BUSY_CNTS_MASK GENMASK(31, 0)
+#define EQDMA_GLBL_S_AXIS_CMP_CNT_A0_ADDR 0x438
+#define GLBL_S_AXIS_CMP_CNT_A0_PKT_CNTS_MASK GENMASK(31, 0)
+#define EQDMA_GLBL_S_AXIS_CMP_CNT_A1_ADDR 0x43C
+#define GLBL_S_AXIS_CMP_CNT_A1_IDLE_CNTS_MASK GENMASK(15, 0)
+#define GLBL_S_AXIS_CMP_CNT_A1_PKT_CNTS_MASK GENMASK(15, 0)
+#define EQDMA_GLBL_S_AXIS_CMP_CNT_A2_ADDR 0x440
+#define GLBL_S_AXIS_CMP_CNT_A2_IDLE_CNTS_MASK GENMASK(31, 0)
+#define EQDMA_GLBL_S_AXIS_CMP_CNT_A3_ADDR 0x444
+#define GLBL_S_AXIS_CMP_CNT_A3_ACTV_CNTS_MASK GENMASK(31, 0)
+#define EQDMA_GLBL_S_AXIS_CMP_CNT_A4_ADDR 0x448
+#define GLBL_S_AXIS_CMP_CNT_A4_BUSY_CNTS_MASK GENMASK(15, 0)
+#define GLBL_S_AXIS_CMP_CNT_A4_ACTV_CNTS_MASK GENMASK(15, 0)
+#define EQDMA_GLBL_S_AXIS_CMP_CNT_A5_ADDR 0x44C
+#define GLBL_S_AXIS_CMP_CNT_A5_BUSY_CNTS_MASK GENMASK(31, 0)
#define EQDMA_IND_CTXT_DATA_ADDR 0x804
#define IND_CTXT_DATA_DATA_MASK GENMASK(31, 0)
#define EQDMA_IND_CTXT_MASK_ADDR 0x824
@@ -578,6 +789,16 @@ struct xreg_info *eqdma_config_regs_get(void);
#define EQDMA_C2H_CNT_TH_ADDR 0xA40
#define C2H_CNT_TH_RSVD_1_MASK GENMASK(31, 16)
#define C2H_CNT_TH_THESHOLD_CNT_MASK GENMASK(15, 0)
+#define EQDMA_C2H_PFCH_CFG_1_ADDR 0xA80
+#define C2H_PFCH_CFG_1_EVT_QCNT_TH_MASK GENMASK(31, 16)
+#define C2H_PFCH_CFG_1_QCNT_MASK GENMASK(15, 0)
+#define EQDMA_C2H_PFCH_CFG_2_ADDR 0xA84
+#define C2H_PFCH_CFG_2_FENCE_MASK BIT(31)
+#define C2H_PFCH_CFG_2_RSVD_MASK GENMASK(30, 29)
+#define C2H_PFCH_CFG_2_VAR_DESC_NO_DROP_MASK BIT(28)
+#define C2H_PFCH_CFG_2_LL_SZ_TH_MASK GENMASK(27, 12)
+#define C2H_PFCH_CFG_2_VAR_DESC_NUM_MASK GENMASK(11, 6)
+#define C2H_PFCH_CFG_2_NUM_MASK GENMASK(5, 0)
#define EQDMA_C2H_STAT_S_AXIS_C2H_ACCEPTED_ADDR 0xA88
#define C2H_STAT_S_AXIS_C2H_ACCEPTED_MASK GENMASK(31, 0)
#define EQDMA_C2H_STAT_S_AXIS_WRB_ACCEPTED_ADDR 0xA8C
@@ -662,16 +883,6 @@ struct xreg_info *eqdma_config_regs_get(void);
#define EQDMA_C2H_PFCH_CFG_ADDR 0xB08
#define C2H_PFCH_CFG_EVTFL_TH_MASK GENMASK(31, 16)
#define C2H_PFCH_CFG_FL_TH_MASK GENMASK(15, 0)
-#define EQDMA_C2H_PFCH_CFG_1_ADDR 0xA80
-#define C2H_PFCH_CFG_1_EVT_QCNT_TH_MASK GENMASK(31, 16)
-#define C2H_PFCH_CFG_1_QCNT_MASK GENMASK(15, 0)
-#define EQDMA_C2H_PFCH_CFG_2_ADDR 0xA84
-#define C2H_PFCH_CFG_2_FENCE_MASK BIT(31)
-#define C2H_PFCH_CFG_2_RSVD_MASK GENMASK(30, 29)
-#define C2H_PFCH_CFG_2_VAR_DESC_NO_DROP_MASK BIT(28)
-#define C2H_PFCH_CFG_2_LL_SZ_TH_MASK GENMASK(27, 12)
-#define C2H_PFCH_CFG_2_VAR_DESC_NUM_MASK GENMASK(11, 6)
-#define C2H_PFCH_CFG_2_NUM_MASK GENMASK(5, 0)
#define EQDMA_C2H_INT_TIMER_TICK_ADDR 0xB0C
#define C2H_INT_TIMER_TICK_MASK GENMASK(31, 0)
#define EQDMA_C2H_STAT_DESC_RSP_DROP_ACCEPTED_ADDR 0xB10
@@ -694,35 +905,33 @@ struct xreg_info *eqdma_config_regs_get(void);
#define C2H_STAT_DMA_ENG_0_WRB_SM_CS_MASK BIT(4)
#define C2H_STAT_DMA_ENG_0_MAIN_SM_CS_MASK GENMASK(3, 0)
#define EQDMA_C2H_STAT_DBG_DMA_ENG_1_ADDR 0xB20
-#define C2H_STAT_DMA_ENG_1_RSVD_1_MASK GENMASK(31, 29)
+#define C2H_STAT_DMA_ENG_1_WRB_USER_0_CMPT_TYPE_MASK GENMASK(31, 30)
+#define C2H_STAT_DMA_ENG_1_DESC_RSP_FIFO_OUT_VLD_MASK GENMASK(29, 29)
#define C2H_STAT_DMA_ENG_1_QID_FIFO_OUT_CNT_MASK GENMASK(28, 18)
#define C2H_STAT_DMA_ENG_1_PLD_FIFO_OUT_CNT_MASK GENMASK(17, 7)
#define C2H_STAT_DMA_ENG_1_PLD_ST_FIFO_CNT_MASK GENMASK(6, 0)
#define EQDMA_C2H_STAT_DBG_DMA_ENG_2_ADDR 0xB24
-#define C2H_STAT_DMA_ENG_2_RSVD_1_MASK GENMASK(31, 29)
-#define C2H_STAT_DMA_ENG_2_QID_FIFO_OUT_CNT_MASK GENMASK(28, 18)
-#define C2H_STAT_DMA_ENG_2_PLD_FIFO_OUT_CNT_MASK GENMASK(17, 7)
-#define C2H_STAT_DMA_ENG_2_PLD_ST_FIFO_CNT_MASK GENMASK(6, 0)
+#define C2H_STAT_DMA_ENG_2_WRB_USER_1_CMPT_TYPE_MASK GENMASK(31, 30)
+#define C2H_STAT_DMA_ENG_2_DESC_RSP_FIFO_OUT_VLD_1_MASK GENMASK(29, 29)
+#define C2H_STAT_DMA_ENG_2_QID_FIFO_OUT_CNT_1_MASK GENMASK(28, 18)
+#define C2H_STAT_DMA_ENG_2_PLD_FIFO_OUT_CNT_1_MASK GENMASK(17, 7)
+#define C2H_STAT_DMA_ENG_2_PLD_ST_FIFO_CNT_1_MASK GENMASK(6, 0)
#define EQDMA_C2H_STAT_DBG_DMA_ENG_3_ADDR 0xB28
-#define C2H_STAT_DMA_ENG_3_RSVD_1_MASK GENMASK(31, 24)
-#define C2H_STAT_DMA_ENG_3_WRQ_FIFO_OUT_CNT_MASK GENMASK(23, 19)
-#define C2H_STAT_DMA_ENG_3_QID_FIFO_OUT_VLD_MASK BIT(18)
-#define C2H_STAT_DMA_ENG_3_PLD_FIFO_OUT_VLD_MASK BIT(17)
-#define C2H_STAT_DMA_ENG_3_PLD_ST_FIFO_OUT_VLD_MASK BIT(16)
-#define C2H_STAT_DMA_ENG_3_PLD_ST_FIFO_OUT_DATA_EOP_MASK BIT(15)
-#define C2H_STAT_DMA_ENG_3_PLD_ST_FIFO_OUT_DATA_AVL_IDX_ENABLE_MASK BIT(14)
-#define C2H_STAT_DMA_ENG_3_PLD_ST_FIFO_OUT_DATA_DROP_MASK BIT(13)
-#define C2H_STAT_DMA_ENG_3_PLD_ST_FIFO_OUT_DATA_ERR_MASK BIT(12)
-#define C2H_STAT_DMA_ENG_3_DESC_CNT_FIFO_IN_RDY_MASK BIT(11)
-#define C2H_STAT_DMA_ENG_3_DESC_RSP_FIFO_IN_RDY_MASK BIT(10)
-#define C2H_STAT_DMA_ENG_3_PLD_PKT_ID_LARGER_0_MASK BIT(9)
-#define C2H_STAT_DMA_ENG_3_WRQ_VLD_MASK BIT(8)
-#define C2H_STAT_DMA_ENG_3_WRQ_RDY_MASK BIT(7)
-#define C2H_STAT_DMA_ENG_3_WRQ_FIFO_OUT_RDY_MASK BIT(6)
-#define C2H_STAT_DMA_ENG_3_WRQ_PACKET_OUT_DATA_DROP_MASK BIT(5)
-#define C2H_STAT_DMA_ENG_3_WRQ_PACKET_OUT_DATA_ERR_MASK BIT(4)
-#define C2H_STAT_DMA_ENG_3_WRQ_PACKET_OUT_DATA_MARKER_MASK BIT(3)
-#define C2H_STAT_DMA_ENG_3_WRQ_PACKET_PRE_EOR_MASK BIT(2)
+#define C2H_STAT_DMA_ENG_3_QID_FIFO_OUT_DAT_HAS_CMPT_MASK BIT(31)
+#define C2H_STAT_DMA_ENG_3_QID_FIFO_OUT_DAT_MARKER_MASK BIT(30)
+#define C2H_STAT_DMA_ENG_3_QID_FIFO_OUT_DAT_DROP_REQ_MASK BIT(29)
+#define C2H_STAT_DMA_ENG_3_QID_FIFO_OUT_DAT_QID_MASK GENMASK(28, 17)
+#define C2H_STAT_DMA_ENG_3_WR_HDR_FIFO_OUT_CNT_MASK GENMASK(16, 12)
+#define C2H_STAT_DMA_ENG_3_QID_FIFO_OUT_VLD_MASK BIT(11)
+#define C2H_STAT_DMA_ENG_3_PLD_FIFO_OUT_VLD_MASK BIT(10)
+#define C2H_STAT_DMA_ENG_3_PLD_ST_FIFO_OUT_VLD_MASK BIT(9)
+#define C2H_STAT_DMA_ENG_3_PLD_ST_FIFO_OUT_DATA_EOP_MASK BIT(8)
+#define C2H_STAT_DMA_ENG_3_PLD_ST_FIFO_OUT_DATA_AVL_IDX_ENABLE_MASK BIT(7)
+#define C2H_STAT_DMA_ENG_3_PLD_ST_FIFO_OUT_DATA_DROP_MASK BIT(6)
+#define C2H_STAT_DMA_ENG_3_PLD_ST_FIFO_OUT_DATA_ERR_MASK BIT(5)
+#define C2H_STAT_DMA_ENG_3_DESC_CNT_FIFO_IN_RDY_MASK BIT(4)
+#define C2H_STAT_DMA_ENG_3_DESC_RSP_FIFO_IN_RDY_MASK BIT(3)
+#define C2H_STAT_DMA_ENG_3_PLD_PKT_ID_LARGER_MASK BIT(2)
#define C2H_STAT_DMA_ENG_3_WCP_FIFO_IN_RDY_MASK BIT(1)
#define C2H_STAT_DMA_ENG_3_PLD_ST_FIFO_IN_RDY_MASK BIT(0)
#define EQDMA_C2H_DBG_PFCH_ERR_CTXT_ADDR 0xB2C
@@ -803,31 +1012,27 @@ struct xreg_info *eqdma_config_regs_get(void);
#define C2H_STAT_WR_CMP_RSVD_1_MASK GENMASK(31, 18)
#define C2H_STAT_WR_CMP_CNT_MASK GENMASK(17, 0)
#define EQDMA_C2H_STAT_DBG_DMA_ENG_4_ADDR 0xB88
-#define C2H_STAT_DMA_ENG_4_RSVD_1_MASK GENMASK(31, 24)
-#define C2H_STAT_DMA_ENG_4_WRQ_FIFO_OUT_CNT_MASK GENMASK(23, 19)
-#define C2H_STAT_DMA_ENG_4_QID_FIFO_OUT_VLD_MASK BIT(18)
-#define C2H_STAT_DMA_ENG_4_PLD_FIFO_OUT_VLD_MASK BIT(17)
-#define C2H_STAT_DMA_ENG_4_PLD_ST_FIFO_OUT_VLD_MASK BIT(16)
-#define C2H_STAT_DMA_ENG_4_PLD_ST_FIFO_OUT_DATA_EOP_MASK BIT(15)
-#define C2H_STAT_DMA_ENG_4_PLD_ST_FIFO_OUT_DATA_AVL_IDX_ENABLE_MASK BIT(14)
-#define C2H_STAT_DMA_ENG_4_PLD_ST_FIFO_OUT_DATA_DROP_MASK BIT(13)
-#define C2H_STAT_DMA_ENG_4_PLD_ST_FIFO_OUT_DATA_ERR_MASK BIT(12)
-#define C2H_STAT_DMA_ENG_4_DESC_CNT_FIFO_IN_RDY_MASK BIT(11)
-#define C2H_STAT_DMA_ENG_4_DESC_RSP_FIFO_IN_RDY_MASK BIT(10)
-#define C2H_STAT_DMA_ENG_4_PLD_PKT_ID_LARGER_0_MASK BIT(9)
-#define C2H_STAT_DMA_ENG_4_WRQ_VLD_MASK BIT(8)
-#define C2H_STAT_DMA_ENG_4_WRQ_RDY_MASK BIT(7)
-#define C2H_STAT_DMA_ENG_4_WRQ_FIFO_OUT_RDY_MASK BIT(6)
-#define C2H_STAT_DMA_ENG_4_WRQ_PACKET_OUT_DATA_DROP_MASK BIT(5)
-#define C2H_STAT_DMA_ENG_4_WRQ_PACKET_OUT_DATA_ERR_MASK BIT(4)
-#define C2H_STAT_DMA_ENG_4_WRQ_PACKET_OUT_DATA_MARKER_MASK BIT(3)
-#define C2H_STAT_DMA_ENG_4_WRQ_PACKET_PRE_EOR_MASK BIT(2)
-#define C2H_STAT_DMA_ENG_4_WCP_FIFO_IN_RDY_MASK BIT(1)
-#define C2H_STAT_DMA_ENG_4_PLD_ST_FIFO_IN_RDY_MASK BIT(0)
+#define C2H_STAT_DMA_ENG_4_QID_FIFO_OUT_DAT_HAS_CMPT_1_MASK BIT(31)
+#define C2H_STAT_DMA_ENG_4_QID_FIFO_OUT_DAT_MARKER_1_MASK BIT(30)
+#define C2H_STAT_DMA_ENG_4_QID_FIFO_OUT_DAT_DROP_REQ_1_MASK BIT(29)
+#define C2H_STAT_DMA_ENG_4_QID_FIFO_OUT_DAT_QID_1_MASK GENMASK(28, 17)
+#define C2H_STAT_DMA_ENG_4_WR_HDR_FIFO_OUT_CNT_1_MASK GENMASK(16, 12)
+#define C2H_STAT_DMA_ENG_4_QID_FIFO_OUT_VLD_1_MASK BIT(11)
+#define C2H_STAT_DMA_ENG_4_PLD_FIFO_OUT_VLD_1_MASK BIT(10)
+#define C2H_STAT_DMA_ENG_4_PLD_ST_FIFO_OUT_VLD_1_MASK BIT(9)
+#define C2H_STAT_DMA_ENG_4_PLD_ST_FIFO_OUT_DATA_EOP_1_MASK BIT(8)
+#define C2H_STAT_DMA_ENG_4_PLD_ST_FIFO_OUT_DATA_AVL_IDX_ENABLE_1_MASK BIT(7)
+#define C2H_STAT_DMA_ENG_4_PLD_ST_FIFO_OUT_DATA_DROP_1_MASK BIT(6)
+#define C2H_STAT_DMA_ENG_4_PLD_ST_FIFO_OUT_DATA_ERR_1_MASK BIT(5)
+#define C2H_STAT_DMA_ENG_4_DESC_CNT_FIFO_IN_RDY_1_MASK BIT(4)
+#define C2H_STAT_DMA_ENG_4_DESC_RSP_FIFO_IN_RDY_1_MASK BIT(3)
+#define C2H_STAT_DMA_ENG_4_PLD_PKT_ID_LARGER_1_MASK BIT(2)
+#define C2H_STAT_DMA_ENG_4_WCP_FIFO_IN_RDY_1_MASK BIT(1)
+#define C2H_STAT_DMA_ENG_4_PLD_ST_FIFO_IN_RDY_1_MASK BIT(0)
#define EQDMA_C2H_STAT_DBG_DMA_ENG_5_ADDR 0xB8C
-#define C2H_STAT_DMA_ENG_5_RSVD_1_MASK GENMASK(31, 30)
-#define C2H_STAT_DMA_ENG_5_WRB_SM_VIRT_CH_MASK BIT(29)
-#define C2H_STAT_DMA_ENG_5_WRB_FIFO_IN_REQ_MASK GENMASK(28, 24)
+#define C2H_STAT_DMA_ENG_5_ARB_FIFO_IN_RDY_MASK BIT(31)
+#define C2H_STAT_DMA_ENG_5_WRB_SM_VIRT_CH_MASK BIT(30)
+#define C2H_STAT_DMA_ENG_5_WRB_FIFO_IN_REQ_MASK GENMASK(29, 24)
#define C2H_STAT_DMA_ENG_5_ARB_FIFO_OUT_CNT_MASK GENMASK(23, 22)
#define C2H_STAT_DMA_ENG_5_ARB_FIFO_OUT_DATA_LEN_MASK GENMASK(21, 6)
#define C2H_STAT_DMA_ENG_5_ARB_FIFO_OUT_DATA_VIRT_CH_MASK BIT(5)
@@ -1096,6 +1301,10 @@ struct xreg_info *eqdma_config_regs_get(void);
#define H2C_MM_WBK_STALL_MASK BIT(2)
#define H2C_MM_DSC_FIFO_EP_MASK BIT(1)
#define H2C_MM_DSC_FIFO_FL_MASK BIT(0)
+#define EQDMA_H2C_MM_DATA_THROTTLE_ADDR 0x12EC
+#define H2C_MM_DATA_THROTTLE_RSVD_1_MASK GENMASK(31, 17)
+#define H2C_MM_DATA_THROTTLE_DAT_EN_MASK BIT(16)
+#define H2C_MM_DATA_THROTTLE_DAT_MASK GENMASK(15, 0)
#define EQDMA_C2H_CRDT_COAL_CFG_1_ADDR 0x1400
#define C2H_CRDT_COAL_CFG_1_RSVD_1_MASK GENMASK(31, 18)
#define C2H_CRDT_COAL_CFG_1_PLD_FIFO_TH_MASK GENMASK(17, 10)
@@ -1113,9 +1322,54 @@ struct xreg_info *eqdma_config_regs_get(void);
#define C2H_PFCH_BYP_TAG_BYP_QID_MASK GENMASK(19, 8)
#define C2H_PFCH_BYP_TAG_RSVD_2_MASK BIT(7)
#define C2H_PFCH_BYP_TAG_MASK GENMASK(6, 0)
-#define EQDMA_C2H_WATER_MARK_ADDR 0x1500
+#define EQDMA_C2H_WATER_MARK_ADDR 0x1410
#define C2H_WATER_MARK_HIGH_WM_MASK GENMASK(31, 16)
#define C2H_WATER_MARK_LOW_WM_MASK GENMASK(15, 0)
+#define EQDMA_C2H_NOTIFY_EMPTY_ADDR 0x1450
+#define C2H_NOTIFY_EMPTY_RSVD_1_MASK GENMASK(31, 16)
+#define C2H_NOTIFY_EMPTY_NOE_MASK GENMASK(15, 0)
+#define EQDMA_C2H_STAT_S_AXIS_C2H_ACCEPTED_1_ADDR 0x1454
+#define C2H_STAT_S_AXIS_C2H_ACCEPTED_1_MASK GENMASK(31, 0)
+#define EQDMA_C2H_STAT_S_AXIS_WRB_ACCEPTED_1_ADDR 0x1458
+#define C2H_STAT_S_AXIS_WRB_ACCEPTED_1_MASK GENMASK(31, 0)
+#define EQDMA_C2H_STAT_DESC_RSP_PKT_ACCEPTED_1_ADDR 0x145C
+#define C2H_STAT_DESC_RSP_PKT_ACCEPTED_1_D_MASK GENMASK(31, 0)
+#define EQDMA_C2H_STAT_AXIS_PKG_CMP_1_ADDR 0x1460
+#define C2H_STAT_AXIS_PKG_CMP_1_MASK GENMASK(31, 0)
+#define EQDMA_C2H_STAT_S_AXIS_WRB_ACCEPTED_2_ADDR 0x1464
+#define C2H_STAT_S_AXIS_WRB_ACCEPTED_2_MASK GENMASK(31, 0)
+#define EQDMA_C2H_ST_PLD_FIFO_DEPTH_ADDR 0x1468
+#define C2H_ST_PLD_FIFO_DEPTH_MASK GENMASK(31, 0)
+#define EQDMA_C2H_STAT_DBG_DMA_ENG_6_ADDR 0x146C
+#define C2H_STAT_DMA_ENG_6_RSVD_MASK GENMASK(31, 29)
+#define C2H_STAT_DMA_ENG_6_PLD_ST_FIFO_OUT_DATA_QID_MASK GENMASK(28, 17)
+#define C2H_STAT_DMA_ENG_6_PLD_STS_FIFO_OUT_DATA_PLD_ST_PKT_ID_MASK \
+ GENMASK(16, 1)
+#define C2H_STAT_DMA_ENG_6_PLD_PKT_ID_LARGER_PLD_ST_MASK BIT(0)
+#define EQDMA_C2H_STAT_DBG_DMA_ENG_7_ADDR 0x1470
+#define C2H_STAT_DMA_ENG_7_RSVD_MASK GENMASK(31, 29)
+#define C2H_STAT_DMA_ENG_7_PLD_ST_FIFO_OUT_DATA_QID_1_MASK GENMASK(28, 17)
+#define C2H_STAT_DMA_ENG_7_PLD_STS_FIFO_OUT_DATA_PLD_ST_PKT_ID_1_MASK \
+ GENMASK(16, 1)
+#define C2H_STAT_DMA_ENG_7_PLD_PKT_ID_LARGER_PLD_ST_1_MASK BIT(0)
+#define EQDMA_C2H_STAT_PCIE_CMP_1_ADDR 0x1474
+#define C2H_STAT_PCIE_CMP_1_DEPTH_MASK GENMASK(31, 0)
+#define EQDMA_C2H_PLD_FIFO_ALMOST_FULL_ADDR 0x1478
+#define C2H_PLD_FIFO_ALMOST_FULL_ENABLE_MASK BIT(31)
+#define C2H_PLD_FIFO_ALMOST_FULL_TH_MASK GENMASK(30, 0)
+#define EQDMA_PFCH_CFG_3_ADDR 0x147C
+#define PFCH_CFG_3_RSVD_MASK GENMASK(31, 16)
+#define PFCH_CFG_3_VAR_DESC_FL_FREE_CNT_TH_MASK GENMASK(15, 7)
+#define PFCH_CFG_3_VAR_DESC_LG_PKT_CAM_CN_TH_MASK GENMASK(6, 0)
+#define EQDMA_CMPT_CFG_0_ADDR 0x1480
+#define CMPT_CFG_0_RSVD_MASK GENMASK(31, 2)
+#define CMPT_CFG_0_VIO_SPRS_INT_AFTER_RTY_MASK BIT(1)
+#define CMPT_CFG_0_VIO_EVNT_SUP_EN_MASK BIT(0)
+#define EQDMA_PFCH_CFG_4_ADDR 0x1484
+#define PFCH_CFG_4_GLB_EVT_TIMER_TICK_MASK GENMASK(31, 17)
+#define PFCH_CFG_4_DISABLE_GLB_EVT_TIMER_MASK BIT(16)
+#define PFCH_CFG_4_EVT_TIMER_TICK_MASK GENMASK(15, 1)
+#define PFCH_CFG_4_DISABLE_EVT_TIMER_MASK BIT(0)
#define SW_IND_CTXT_DATA_W7_VIRTIO_DSC_BASE_H_MASK GENMASK(10, 0)
#define SW_IND_CTXT_DATA_W6_VIRTIO_DSC_BASE_M_MASK GENMASK(31, 0)
#define SW_IND_CTXT_DATA_W5_VIRTIO_DSC_BASE_L_MASK GENMASK(31, 11)
@@ -1233,6 +1487,50 @@ struct xreg_info *eqdma_config_regs_get(void);
#define INTR_CTXT_DATA_W0_RSVD1_MASK BIT(12)
#define INTR_CTXT_DATA_W0_VEC_MASK GENMASK(11, 1)
#define INTR_CTXT_DATA_W0_VALID_MASK BIT(0)
+#define HOSTID_TABLE_W6_SMID_MASK GENMASK(9, 0)
+#define HOSTID_TABLE_W5_H2C_MM_AWPROT_MASK GENMASK(27, 26)
+#define HOSTID_TABLE_W5_H2C_MM_AWCACHE_MASK GENMASK(25, 22)
+#define HOSTID_TABLE_W5_H2C_MM_AWSTEERING_MASK GENMASK(20, 18)
+#define HOSTID_TABLE_W5_DSC_AWPROT_MASK GENMASK(17, 16)
+#define HOSTID_TABLE_W5_DSC_AWCACHE_MASK GENMASK(15, 12)
+#define HOSTID_TABLE_W5_DSC_AWSTEERING_MASK GENMASK(11, 8)
+#define HOSTID_TABLE_W5_INT_MSG_AWPROT_MASK GENMASK(7, 6)
+#define HOSTID_TABLE_W5_INT_MSG_AWCACHE_MASK GENMASK(5, 2)
+#define HOSTID_TABLE_W5_INT_MSG_AWSTEERING_H_MASK GENMASK(0, 0)
+#define HOSTID_TABLE_W4_INT_MSG_AWSTEERING_L_MASK GENMASK(31, 30)
+#define HOSTID_TABLE_W4_INT_AGGR_AWPROT_MASK GENMASK(29, 28)
+#define HOSTID_TABLE_W4_INT_AGGR_AWCACHE_MASK GENMASK(27, 24)
+#define HOSTID_TABLE_W4_INT_AGGR_AWSTEERING_MASK GENMASK(22, 20)
+#define HOSTID_TABLE_W4_CMPT_AWPROT_MASK GENMASK(19, 18)
+#define HOSTID_TABLE_W4_CMPT_AWCACHE_MASK GENMASK(17, 14)
+#define HOSTID_TABLE_W4_CMPT_AWSTEERING_MASK GENMASK(12, 10)
+#define HOSTID_TABLE_W4_C2H_PLD_AWPROT_MASK GENMASK(9, 8)
+#define HOSTID_TABLE_W4_C2H_PLD_AWCACHE_MASK GENMASK(7, 4)
+#define HOSTID_TABLE_W4_C2H_PLD_AWSTEERING_MASK GENMASK(2, 0)
+#define HOSTID_TABLE_W3_C2H_MM_ARPROT_MASK GENMASK(7, 6)
+#define HOSTID_TABLE_W3_C2H_MM_ARCACHE_MASK GENMASK(5, 2)
+#define HOSTID_TABLE_W3_C2H_MM_ARSTEERING_H_MASK GENMASK(0, 0)
+#define HOSTID_TABLE_W2_C2H_MM_ARSTEERING_L_MASK GENMASK(31, 30)
+#define HOSTID_TABLE_W2_H2C_MM_ARPROT_MASK GENMASK(29, 28)
+#define HOSTID_TABLE_W2_H2C_MM_ARCACHE_MASK GENMASK(27, 24)
+#define HOSTID_TABLE_W2_H2C_MM_ARSTEERING_MASK GENMASK(22, 20)
+#define HOSTID_TABLE_W2_H2C_ST_ARPROT_MASK GENMASK(19, 18)
+#define HOSTID_TABLE_W2_H2C_ST_ARCACHE_MASK GENMASK(17, 14)
+#define HOSTID_TABLE_W2_H2C_ST_ARSTEERING_MASK GENMASK(12, 10)
+#define HOSTID_TABLE_W2_DSC_ARPOT_MASK GENMASK(9, 8)
+#define HOSTID_TABLE_W2_DSC_ARCACHE_MASK GENMASK(7, 4)
+#define HOSTID_TABLE_W2_DSC_ARSTEERING_MASK GENMASK(2, 0)
+#define HOSTID_TABLE_W0_VCH_H2C_MM_MASK GENMASK(27, 24)
+#define HOSTID_TABLE_W0_VCH_H2C_ST_MASK GENMASK(23, 20)
+#define HOSTID_TABLE_W0_VCH_DSC_MASK GENMASK(19, 16)
+#define HOSTID_TABLE_W0_VCH_INT_MSG_MASK GENMASK(15, 12)
+#define HOSTID_TABLE_W0_VCH_INT_AGGR_MASK GENMASK(11, 8)
+#define HOSTID_TABLE_W0_VCH_CMPT_MASK GENMASK(7, 4)
+#define HOSTID_TABLE_W0_VCH_H2C_PLD_MASK GENMASK(3, 0)
+#define CTXT_SELC_FNC_STS_W0_MSIX_MASK GENMASK(3, 3)
+#define CTXT_SELC_FNC_STS_W0_MSIX_ENABLE_MASK GENMASK(2, 2)
+#define CTXT_SELC_FNC_STS_W0_MEM_SPACE_ENABLE_MASK GENMASK(1, 1)
+#define CTXT_SELC_FNC_STS_W0_BUS_MASTER_ENABLE_MASK GENMASK(0, 0)
#ifdef __cplusplus
}
diff --git a/QDMA/DPDK/drivers/net/qdma/qdma_access/eqdma_soft_access/eqdma_soft_reg_dump.c b/QDMA/DPDK/drivers/net/qdma/qdma_access/eqdma_soft_access/eqdma_soft_reg_dump.c
old mode 100644
new mode 100755
index 7902dd7d139ee84e0911be1e711b8392deac231a..41950f9ced5f35fa6ca04a096d9538dd93ff387d
--- a/QDMA/DPDK/drivers/net/qdma/qdma_access/eqdma_soft_access/eqdma_soft_reg_dump.c
+++ b/QDMA/DPDK/drivers/net/qdma/qdma_access/eqdma_soft_access/eqdma_soft_reg_dump.c
@@ -1,5 +1,6 @@
/*
- * Copyright(c) 2019-2022 Xilinx, Inc. All rights reserved.
+ * Copyright (c) 2019-2022 Xilinx, Inc. All rights reserved.
+ * Copyright (c) 2022, Advanced Micro Devices, Inc. All rights reserved.
*
* BSD LICENSE
*
@@ -492,6 +493,85 @@ static struct regfield_info
};
+static struct regfield_info
+ glbl2_rrq_brg_throt_field_info[] = {
+ {"GLBL2_RRQ_BRG_THROT_REQ_EN",
+ GLBL2_RRQ_BRG_THROT_REQ_EN_MASK},
+ {"GLBL2_RRQ_BRG_THROT_REQ",
+ GLBL2_RRQ_BRG_THROT_REQ_MASK},
+ {"GLBL2_RRQ_BRG_THROT_DAT_EN",
+ GLBL2_RRQ_BRG_THROT_DAT_EN_MASK},
+ {"GLBL2_RRQ_BRG_THROT_DAT",
+ GLBL2_RRQ_BRG_THROT_DAT_MASK},
+};
+
+
+static struct regfield_info
+ glbl2_rrq_pcie_throt_field_info[] = {
+ {"GLBL2_RRQ_PCIE_THROT_REQ_EN",
+ GLBL2_RRQ_PCIE_THROT_REQ_EN_MASK},
+ {"GLBL2_RRQ_PCIE_THROT_REQ",
+ GLBL2_RRQ_PCIE_THROT_REQ_MASK},
+ {"GLBL2_RRQ_PCIE_THROT_DAT_EN",
+ GLBL2_RRQ_PCIE_THROT_DAT_EN_MASK},
+ {"GLBL2_RRQ_PCIE_THROT_DAT",
+ GLBL2_RRQ_PCIE_THROT_DAT_MASK},
+};
+
+
+static struct regfield_info
+ glbl2_rrq_aximm_throt_field_info[] = {
+ {"GLBL2_RRQ_AXIMM_THROT_REQ_EN",
+ GLBL2_RRQ_AXIMM_THROT_REQ_EN_MASK},
+ {"GLBL2_RRQ_AXIMM_THROT_REQ",
+ GLBL2_RRQ_AXIMM_THROT_REQ_MASK},
+ {"GLBL2_RRQ_AXIMM_THROT_DAT_EN",
+ GLBL2_RRQ_AXIMM_THROT_DAT_EN_MASK},
+ {"GLBL2_RRQ_AXIMM_THROT_DAT",
+ GLBL2_RRQ_AXIMM_THROT_DAT_MASK},
+};
+
+
+static struct regfield_info
+ glbl2_rrq_pcie_lat0_field_info[] = {
+ {"GLBL2_RRQ_PCIE_LAT0_MAX",
+ GLBL2_RRQ_PCIE_LAT0_MAX_MASK},
+ {"GLBL2_RRQ_PCIE_LAT0_MIN",
+ GLBL2_RRQ_PCIE_LAT0_MIN_MASK},
+};
+
+
+static struct regfield_info
+ glbl2_rrq_pcie_lat1_field_info[] = {
+ {"GLBL2_RRQ_PCIE_LAT1_RSVD",
+ GLBL2_RRQ_PCIE_LAT1_RSVD_MASK},
+ {"GLBL2_RRQ_PCIE_LAT1_OVFL",
+ GLBL2_RRQ_PCIE_LAT1_OVFL_MASK},
+ {"GLBL2_RRQ_PCIE_LAT1_AVG",
+ GLBL2_RRQ_PCIE_LAT1_AVG_MASK},
+};
+
+
+static struct regfield_info
+ glbl2_rrq_aximm_lat0_field_info[] = {
+ {"GLBL2_RRQ_AXIMM_LAT0_MAX",
+ GLBL2_RRQ_AXIMM_LAT0_MAX_MASK},
+ {"GLBL2_RRQ_AXIMM_LAT0_MIN",
+ GLBL2_RRQ_AXIMM_LAT0_MIN_MASK},
+};
+
+
+static struct regfield_info
+ glbl2_rrq_aximm_lat1_field_info[] = {
+ {"GLBL2_RRQ_AXIMM_LAT1_RSVD",
+ GLBL2_RRQ_AXIMM_LAT1_RSVD_MASK},
+ {"GLBL2_RRQ_AXIMM_LAT1_OVFL",
+ GLBL2_RRQ_AXIMM_LAT1_OVFL_MASK},
+ {"GLBL2_RRQ_AXIMM_LAT1_AVG",
+ GLBL2_RRQ_AXIMM_LAT1_AVG_MASK},
+};
+
+
static struct regfield_info
glbl2_dbg_pcie_rq0_field_info[] = {
{"GLBL2_PCIE_RQ0_NPH_AVL",
@@ -933,6 +1013,10 @@ static struct regfield_info
glbl_dsc_cfg_field_info[] = {
{"GLBL_DSC_CFG_RSVD_1",
GLBL_DSC_CFG_RSVD_1_MASK},
+ {"GLBL_DSC_CFG_C2H_UODSC_LIMIT",
+ GLBL_DSC_CFG_C2H_UODSC_LIMIT_MASK},
+ {"GLBL_DSC_CFG_H2C_UODSC_LIMIT",
+ GLBL_DSC_CFG_H2C_UODSC_LIMIT_MASK},
{"GLBL_DSC_CFG_UNC_OVR_COR",
GLBL_DSC_CFG_UNC_OVR_COR_MASK},
{"GLBL_DSC_CFG_CTXT_FER_DIS",
@@ -1111,6 +1195,10 @@ static struct regfield_info
glbl_dsc_dbg_ctl_field_info[] = {
{"GLBL_DSC_CTL_RSVD_1",
GLBL_DSC_CTL_RSVD_1_MASK},
+ {"GLBL_DSC_CTL_LAT_QID",
+ GLBL_DSC_CTL_LAT_QID_MASK},
+ {"GLBL_DSC_CTL_DSC_ENG_LAT_CLR",
+ GLBL_DSC_CTL_DSC_ENG_LAT_CLR_MASK},
{"GLBL_DSC_CTL_SELECT",
GLBL_DSC_CTL_SELECT_MASK},
};
@@ -1219,1961 +1307,3168 @@ static struct regfield_info
static struct regfield_info
- ind_ctxt_data_field_info[] = {
- {"IND_CTXT_DATA_DATA",
- IND_CTXT_DATA_DATA_MASK},
+ glbl_dsc_dbg_lat0_a_field_info[] = {
+ {"GLBL_DSC_LAT0_A_LAT_MAX",
+ GLBL_DSC_LAT0_A_LAT_MAX_MASK},
+ {"GLBL_DSC_LAT0_A_LAT_MIN",
+ GLBL_DSC_LAT0_A_LAT_MIN_MASK},
};
static struct regfield_info
- ind_ctxt_mask_field_info[] = {
- {"IND_CTXT",
- IND_CTXT_MASK},
+ glbl_dsc_dbg_lat1_a_field_info[] = {
+ {"GLBL_DSC_LAT1_A_RSVD",
+ GLBL_DSC_LAT1_A_RSVD_MASK},
+ {"GLBL_DSC_LAT1_A_LAT_OVF",
+ GLBL_DSC_LAT1_A_LAT_OVF_MASK},
+ {"GLBL_DSC_LAT1_A_LAT_AVG",
+ GLBL_DSC_LAT1_A_LAT_AVG_MASK},
};
static struct regfield_info
- ind_ctxt_cmd_field_info[] = {
- {"IND_CTXT_CMD_RSVD_1",
- IND_CTXT_CMD_RSVD_1_MASK},
- {"IND_CTXT_CMD_QID",
- IND_CTXT_CMD_QID_MASK},
- {"IND_CTXT_CMD_OP",
- IND_CTXT_CMD_OP_MASK},
- {"IND_CTXT_CMD_SEL",
- IND_CTXT_CMD_SEL_MASK},
- {"IND_CTXT_CMD_BUSY",
- IND_CTXT_CMD_BUSY_MASK},
+ glbl_dsc_crd_ctr0_a_field_info[] = {
+ {"GLBL_DSC_CRD_CTR0_A_CRD_RCV_CNT",
+ GLBL_DSC_CRD_CTR0_A_CRD_RCV_CNT_MASK},
};
static struct regfield_info
- c2h_timer_cnt_field_info[] = {
- {"C2H_TIMER_CNT_RSVD_1",
- C2H_TIMER_CNT_RSVD_1_MASK},
- {"C2H_TIMER_CNT",
- C2H_TIMER_CNT_MASK},
+ glbl_dsc_crd_ctr1_a_field_info[] = {
+ {"GLBL_DSC_CRD_CTR1_A_CRD_RCV_CNT",
+ GLBL_DSC_CRD_CTR1_A_CRD_RCV_CNT_MASK},
};
static struct regfield_info
- c2h_cnt_th_field_info[] = {
- {"C2H_CNT_TH_RSVD_1",
- C2H_CNT_TH_RSVD_1_MASK},
- {"C2H_CNT_TH_THESHOLD_CNT",
- C2H_CNT_TH_THESHOLD_CNT_MASK},
+ glbl_dsc_crd_ctr2_a_field_info[] = {
+ {"GLBL_DSC_CRD_CTR2_A_CRD_RCV_NRDY_CNT",
+ GLBL_DSC_CRD_CTR2_A_CRD_RCV_NRDY_CNT_MASK},
};
static struct regfield_info
- c2h_stat_s_axis_c2h_accepted_field_info[] = {
- {"C2H_STAT_S_AXIS_C2H_ACCEPTED",
- C2H_STAT_S_AXIS_C2H_ACCEPTED_MASK},
+ glbl_dsc_crd_ctr3_a_field_info[] = {
+ {"GLBL_DSC_CRD_CTR3_A_CRD_RCV_NRDY_CNT",
+ GLBL_DSC_CRD_CTR3_A_CRD_RCV_NRDY_CNT_MASK},
};
static struct regfield_info
- c2h_stat_s_axis_wrb_accepted_field_info[] = {
- {"C2H_STAT_S_AXIS_WRB_ACCEPTED",
- C2H_STAT_S_AXIS_WRB_ACCEPTED_MASK},
+ glbl_dsc_imm_crd_ctr0_a_field_info[] = {
+ {"GLBL_DSC_IMM_CRD_CTR0_A_RCV_CNT",
+ GLBL_DSC_IMM_CRD_CTR0_A_RCV_CNT_MASK},
};
static struct regfield_info
- c2h_stat_desc_rsp_pkt_accepted_field_info[] = {
- {"C2H_STAT_DESC_RSP_PKT_ACCEPTED_D",
- C2H_STAT_DESC_RSP_PKT_ACCEPTED_D_MASK},
+ glbl_dsc_imm_crd_ctr1_a_field_info[] = {
+ {"GLBL_DSC_IMM_CRD_CTR1_A_RCV_CNT",
+ GLBL_DSC_IMM_CRD_CTR1_A_RCV_CNT_MASK},
};
static struct regfield_info
- c2h_stat_axis_pkg_cmp_field_info[] = {
- {"C2H_STAT_AXIS_PKG_CMP",
- C2H_STAT_AXIS_PKG_CMP_MASK},
+ glbl_dsc_imm_crd_ctr2_a_field_info[] = {
+ {"GLBL_DSC_IMM_CRD_CTR2_A_RCV_NRDY_CNT",
+ GLBL_DSC_IMM_CRD_CTR2_A_RCV_NRDY_CNT_MASK},
};
static struct regfield_info
- c2h_stat_desc_rsp_accepted_field_info[] = {
- {"C2H_STAT_DESC_RSP_ACCEPTED_D",
- C2H_STAT_DESC_RSP_ACCEPTED_D_MASK},
+ glbl_dsc_imm_crd_ctr3_a_field_info[] = {
+ {"GLBL_DSC_IMM_CRD_CTR3_A_RCV_NRDY_CNT",
+ GLBL_DSC_IMM_CRD_CTR3_A_RCV_NRDY_CNT_MASK},
};
static struct regfield_info
- c2h_stat_desc_rsp_cmp_field_info[] = {
- {"C2H_STAT_DESC_RSP_CMP_D",
- C2H_STAT_DESC_RSP_CMP_D_MASK},
+ glbl_dsc_h2c_out_ctr0_a_field_info[] = {
+ {"GLBL_DSC_H2C_OUT_CTR0_A_H2CVLD_CNT",
+ GLBL_DSC_H2C_OUT_CTR0_A_H2CVLD_CNT_MASK},
};
static struct regfield_info
- c2h_stat_wrq_out_field_info[] = {
- {"C2H_STAT_WRQ_OUT",
- C2H_STAT_WRQ_OUT_MASK},
+ glbl_dsc_h2c_out_ctr1_a_field_info[] = {
+ {"GLBL_DSC_H2C_OUT_CTR1_A_H2CVLD_CNT",
+ GLBL_DSC_H2C_OUT_CTR1_A_H2CVLD_CNT_MASK},
};
static struct regfield_info
- c2h_stat_wpl_ren_accepted_field_info[] = {
- {"C2H_STAT_WPL_REN_ACCEPTED",
- C2H_STAT_WPL_REN_ACCEPTED_MASK},
+ glbl_dsc_h2c_out_ctr2_a_field_info[] = {
+ {"GLBL_DSC_H2C_OUT_CTR2_A_H2CVLD_NRDY_CNT",
+ GLBL_DSC_H2C_OUT_CTR2_A_H2CVLD_NRDY_CNT_MASK},
};
static struct regfield_info
- c2h_stat_total_wrq_len_field_info[] = {
- {"C2H_STAT_TOTAL_WRQ_LEN",
- C2H_STAT_TOTAL_WRQ_LEN_MASK},
+ glbl_dsc_h2c_out_ctr3_a_field_info[] = {
+ {"GLBL_DSC_H2C_OUT_CTR3_A_H2CVLD_NRDY_CNT",
+ GLBL_DSC_H2C_OUT_CTR3_A_H2CVLD_NRDY_CNT_MASK},
};
static struct regfield_info
- c2h_stat_total_wpl_len_field_info[] = {
- {"C2H_STAT_TOTAL_WPL_LEN",
- C2H_STAT_TOTAL_WPL_LEN_MASK},
+ glbl_dsc_c2h_out_ctr0_a_field_info[] = {
+ {"GLBL_DSC_C2H_OUT_CTR0_A_C2HVLD_CNT",
+ GLBL_DSC_C2H_OUT_CTR0_A_C2HVLD_CNT_MASK},
};
static struct regfield_info
- c2h_buf_sz_field_info[] = {
- {"C2H_BUF_SZ_IZE",
- C2H_BUF_SZ_IZE_MASK},
+ glbl_dsc_c2h_out_ctr1_a_field_info[] = {
+ {"GLBL_DSC_C2H_OUT_CTR1_A_C2HVLD_CNT",
+ GLBL_DSC_C2H_OUT_CTR1_A_C2HVLD_CNT_MASK},
};
static struct regfield_info
- c2h_err_stat_field_info[] = {
- {"C2H_ERR_STAT_RSVD_1",
- C2H_ERR_STAT_RSVD_1_MASK},
- {"C2H_ERR_STAT_WRB_PORT_ID_ERR",
- C2H_ERR_STAT_WRB_PORT_ID_ERR_MASK},
- {"C2H_ERR_STAT_HDR_PAR_ERR",
- C2H_ERR_STAT_HDR_PAR_ERR_MASK},
- {"C2H_ERR_STAT_HDR_ECC_COR_ERR",
- C2H_ERR_STAT_HDR_ECC_COR_ERR_MASK},
- {"C2H_ERR_STAT_HDR_ECC_UNC_ERR",
- C2H_ERR_STAT_HDR_ECC_UNC_ERR_MASK},
- {"C2H_ERR_STAT_AVL_RING_DSC_ERR",
- C2H_ERR_STAT_AVL_RING_DSC_ERR_MASK},
- {"C2H_ERR_STAT_WRB_PRTY_ERR",
- C2H_ERR_STAT_WRB_PRTY_ERR_MASK},
- {"C2H_ERR_STAT_WRB_CIDX_ERR",
- C2H_ERR_STAT_WRB_CIDX_ERR_MASK},
- {"C2H_ERR_STAT_WRB_QFULL_ERR",
- C2H_ERR_STAT_WRB_QFULL_ERR_MASK},
- {"C2H_ERR_STAT_WRB_INV_Q_ERR",
- C2H_ERR_STAT_WRB_INV_Q_ERR_MASK},
- {"C2H_ERR_STAT_RSVD_2",
- C2H_ERR_STAT_RSVD_2_MASK},
- {"C2H_ERR_STAT_PORT_ID_CTXT_MISMATCH",
- C2H_ERR_STAT_PORT_ID_CTXT_MISMATCH_MASK},
- {"C2H_ERR_STAT_ERR_DESC_CNT",
- C2H_ERR_STAT_ERR_DESC_CNT_MASK},
- {"C2H_ERR_STAT_RSVD_3",
- C2H_ERR_STAT_RSVD_3_MASK},
- {"C2H_ERR_STAT_MSI_INT_FAIL",
- C2H_ERR_STAT_MSI_INT_FAIL_MASK},
- {"C2H_ERR_STAT_ENG_WPL_DATA_PAR_ERR",
- C2H_ERR_STAT_ENG_WPL_DATA_PAR_ERR_MASK},
- {"C2H_ERR_STAT_RSVD_4",
- C2H_ERR_STAT_RSVD_4_MASK},
- {"C2H_ERR_STAT_DESC_RSP_ERR",
- C2H_ERR_STAT_DESC_RSP_ERR_MASK},
- {"C2H_ERR_STAT_QID_MISMATCH",
- C2H_ERR_STAT_QID_MISMATCH_MASK},
- {"C2H_ERR_STAT_SH_CMPT_DSC_ERR",
- C2H_ERR_STAT_SH_CMPT_DSC_ERR_MASK},
- {"C2H_ERR_STAT_LEN_MISMATCH",
- C2H_ERR_STAT_LEN_MISMATCH_MASK},
- {"C2H_ERR_STAT_MTY_MISMATCH",
- C2H_ERR_STAT_MTY_MISMATCH_MASK},
+ glbl_dsc_c2h_out_ctr2_a_field_info[] = {
+ {"GLBL_DSC_C2H_OUT_CTR2_A_C2HVLD_NRDY_CNT",
+ GLBL_DSC_C2H_OUT_CTR2_A_C2HVLD_NRDY_CNT_MASK},
};
static struct regfield_info
- c2h_err_mask_field_info[] = {
- {"C2H_ERR_EN",
- C2H_ERR_EN_MASK},
+ glbl_dsc_c2h_out_ctr3_a_field_info[] = {
+ {"GLBL_DSC_C2H_OUT_CTR3_A_C2HVLD_NRDY_CNT",
+ GLBL_DSC_C2H_OUT_CTR3_A_C2HVLD_NRDY_CNT_MASK},
};
static struct regfield_info
- c2h_fatal_err_stat_field_info[] = {
- {"C2H_FATAL_ERR_STAT_RSVD_1",
- C2H_FATAL_ERR_STAT_RSVD_1_MASK},
- {"C2H_FATAL_ERR_STAT_HDR_ECC_UNC_ERR",
- C2H_FATAL_ERR_STAT_HDR_ECC_UNC_ERR_MASK},
- {"C2H_FATAL_ERR_STAT_AVL_RING_FIFO_RAM_RDBE",
- C2H_FATAL_ERR_STAT_AVL_RING_FIFO_RAM_RDBE_MASK},
- {"C2H_FATAL_ERR_STAT_WPL_DATA_PAR_ERR",
- C2H_FATAL_ERR_STAT_WPL_DATA_PAR_ERR_MASK},
- {"C2H_FATAL_ERR_STAT_PLD_FIFO_RAM_RDBE",
- C2H_FATAL_ERR_STAT_PLD_FIFO_RAM_RDBE_MASK},
- {"C2H_FATAL_ERR_STAT_QID_FIFO_RAM_RDBE",
- C2H_FATAL_ERR_STAT_QID_FIFO_RAM_RDBE_MASK},
- {"C2H_FATAL_ERR_STAT_CMPT_FIFO_RAM_RDBE",
- C2H_FATAL_ERR_STAT_CMPT_FIFO_RAM_RDBE_MASK},
- {"C2H_FATAL_ERR_STAT_WRB_COAL_DATA_RAM_RDBE",
- C2H_FATAL_ERR_STAT_WRB_COAL_DATA_RAM_RDBE_MASK},
- {"C2H_FATAL_ERR_STAT_RESERVED2",
- C2H_FATAL_ERR_STAT_RESERVED2_MASK},
- {"C2H_FATAL_ERR_STAT_INT_CTXT_RAM_RDBE",
- C2H_FATAL_ERR_STAT_INT_CTXT_RAM_RDBE_MASK},
- {"C2H_FATAL_ERR_STAT_DESC_REQ_FIFO_RAM_RDBE",
- C2H_FATAL_ERR_STAT_DESC_REQ_FIFO_RAM_RDBE_MASK},
- {"C2H_FATAL_ERR_STAT_PFCH_CTXT_RAM_RDBE",
- C2H_FATAL_ERR_STAT_PFCH_CTXT_RAM_RDBE_MASK},
- {"C2H_FATAL_ERR_STAT_WRB_CTXT_RAM_RDBE",
- C2H_FATAL_ERR_STAT_WRB_CTXT_RAM_RDBE_MASK},
- {"C2H_FATAL_ERR_STAT_PFCH_LL_RAM_RDBE",
- C2H_FATAL_ERR_STAT_PFCH_LL_RAM_RDBE_MASK},
- {"C2H_FATAL_ERR_STAT_TIMER_FIFO_RAM_RDBE",
- C2H_FATAL_ERR_STAT_TIMER_FIFO_RAM_RDBE_MASK},
- {"C2H_FATAL_ERR_STAT_QID_MISMATCH",
- C2H_FATAL_ERR_STAT_QID_MISMATCH_MASK},
- {"C2H_FATAL_ERR_STAT_RESERVED1",
- C2H_FATAL_ERR_STAT_RESERVED1_MASK},
- {"C2H_FATAL_ERR_STAT_LEN_MISMATCH",
- C2H_FATAL_ERR_STAT_LEN_MISMATCH_MASK},
- {"C2H_FATAL_ERR_STAT_MTY_MISMATCH",
- C2H_FATAL_ERR_STAT_MTY_MISMATCH_MASK},
+ t_field_info[] = {
+ {"T_USER_CTR_MAX",
+ T_USER_CTR_MAX_MASK},
};
static struct regfield_info
- c2h_fatal_err_mask_field_info[] = {
- {"C2H_FATAL_ERR_C2HEN",
- C2H_FATAL_ERR_C2HEN_MASK},
+ glbl_perf_cntr_ctl_a1_field_info[] = {
+ {"GLBL_PERF_CNTR_CTL_A1_RSVD",
+ GLBL_PERF_CNTR_CTL_A1_RSVD_MASK},
+ {"GLBL_PERF_CNTR_CTL_A1_USER_CTR_CLEAR",
+ GLBL_PERF_CNTR_CTL_A1_USER_CTR_CLEAR_MASK},
+ {"GLBL_PERF_CNTR_CTL_A1_USER_CTR_READ",
+ GLBL_PERF_CNTR_CTL_A1_USER_CTR_READ_MASK},
+ {"GLBL_PERF_CNTR_CTL_A1_USER_CTR_MAX",
+ GLBL_PERF_CNTR_CTL_A1_USER_CTR_MAX_MASK},
};
static struct regfield_info
- c2h_fatal_err_enable_field_info[] = {
- {"C2H_FATAL_ERR_ENABLE_RSVD_1",
- C2H_FATAL_ERR_ENABLE_RSVD_1_MASK},
- {"C2H_FATAL_ERR_ENABLE_WPL_PAR_INV",
- C2H_FATAL_ERR_ENABLE_WPL_PAR_INV_MASK},
- {"C2H_FATAL_ERR_ENABLE_WRQ_DIS",
- C2H_FATAL_ERR_ENABLE_WRQ_DIS_MASK},
+ glbl_free_cnt_a0_field_info[] = {
+ {"GLBL_FREE_CNT_A0_S",
+ GLBL_FREE_CNT_A0_S_MASK},
};
static struct regfield_info
- glbl_err_int_field_info[] = {
- {"GLBL_ERR_INT_RSVD_1",
- GLBL_ERR_INT_RSVD_1_MASK},
- {"GLBL_ERR_INT_HOST_ID",
- GLBL_ERR_INT_HOST_ID_MASK},
- {"GLBL_ERR_INT_DIS_INTR_ON_VF",
- GLBL_ERR_INT_DIS_INTR_ON_VF_MASK},
- {"GLBL_ERR_INT_ARM",
- GLBL_ERR_INT_ARM_MASK},
- {"GLBL_ERR_INT_EN_COAL",
- GLBL_ERR_INT_EN_COAL_MASK},
- {"GLBL_ERR_INT_VEC",
- GLBL_ERR_INT_VEC_MASK},
- {"GLBL_ERR_INT_FUNC",
- GLBL_ERR_INT_FUNC_MASK},
+ glbl_free_cnt_a1_field_info[] = {
+ {"GLBL_FREE_CNT_A1_RSVD",
+ GLBL_FREE_CNT_A1_RSVD_MASK},
+ {"GLBL_FREE_CNT_A1_S",
+ GLBL_FREE_CNT_A1_S_MASK},
};
static struct regfield_info
- c2h_pfch_cfg_field_info[] = {
- {"C2H_PFCH_CFG_EVTFL_TH",
- C2H_PFCH_CFG_EVTFL_TH_MASK},
- {"C2H_PFCH_CFG_FL_TH",
- C2H_PFCH_CFG_FL_TH_MASK},
+ glbl_axis_h2c_cnt_a0_field_info[] = {
+ {"GLBL_AXIS_H2C_CNT_A0_MPKT_CNTS",
+ GLBL_AXIS_H2C_CNT_A0_MPKT_CNTS_MASK},
};
static struct regfield_info
- c2h_pfch_cfg_1_field_info[] = {
- {"C2H_PFCH_CFG_1_EVT_QCNT_TH",
- C2H_PFCH_CFG_1_EVT_QCNT_TH_MASK},
- {"C2H_PFCH_CFG_1_QCNT",
- C2H_PFCH_CFG_1_QCNT_MASK},
+ glbl_axis_h2c_cnt_a1_field_info[] = {
+ {"GLBL_AXIS_H2C_CNT_A1_MIDLE_CNTS",
+ GLBL_AXIS_H2C_CNT_A1_MIDLE_CNTS_MASK},
+ {"GLBL_AXIS_H2C_CNT_A1_MPKT_CNTS",
+ GLBL_AXIS_H2C_CNT_A1_MPKT_CNTS_MASK},
};
static struct regfield_info
- c2h_pfch_cfg_2_field_info[] = {
- {"C2H_PFCH_CFG_2_FENCE",
- C2H_PFCH_CFG_2_FENCE_MASK},
- {"C2H_PFCH_CFG_2_RSVD",
- C2H_PFCH_CFG_2_RSVD_MASK},
- {"C2H_PFCH_CFG_2_VAR_DESC_NO_DROP",
- C2H_PFCH_CFG_2_VAR_DESC_NO_DROP_MASK},
- {"C2H_PFCH_CFG_2_LL_SZ_TH",
- C2H_PFCH_CFG_2_LL_SZ_TH_MASK},
- {"C2H_PFCH_CFG_2_VAR_DESC_NUM",
- C2H_PFCH_CFG_2_VAR_DESC_NUM_MASK},
- {"C2H_PFCH_CFG_2_NUM",
- C2H_PFCH_CFG_2_NUM_MASK},
+ glbl_axis_h2c_cnt_a2_field_info[] = {
+ {"GLBL_AXIS_H2C_CNT_A2_MIDLE_CNTS",
+ GLBL_AXIS_H2C_CNT_A2_MIDLE_CNTS_MASK},
};
static struct regfield_info
- c2h_int_timer_tick_field_info[] = {
- {"C2H_INT_TIMER_TICK",
- C2H_INT_TIMER_TICK_MASK},
+ glbl_axis_h2c_cnt_a3_field_info[] = {
+ {"GLBL_AXIS_H2C_CNT_A3_MACTV_CNTS",
+ GLBL_AXIS_H2C_CNT_A3_MACTV_CNTS_MASK},
};
static struct regfield_info
- c2h_stat_desc_rsp_drop_accepted_field_info[] = {
- {"C2H_STAT_DESC_RSP_DROP_ACCEPTED_D",
- C2H_STAT_DESC_RSP_DROP_ACCEPTED_D_MASK},
+ glbl_axis_h2c_cnt_a4_field_info[] = {
+ {"GLBL_AXIS_H2C_CNT_A4_MBUSY_CNTS",
+ GLBL_AXIS_H2C_CNT_A4_MBUSY_CNTS_MASK},
+ {"GLBL_AXIS_H2C_CNT_A4_MACTV_CNTS",
+ GLBL_AXIS_H2C_CNT_A4_MACTV_CNTS_MASK},
};
static struct regfield_info
- c2h_stat_desc_rsp_err_accepted_field_info[] = {
- {"C2H_STAT_DESC_RSP_ERR_ACCEPTED_D",
- C2H_STAT_DESC_RSP_ERR_ACCEPTED_D_MASK},
+ glbl_axis_h2c_cnt_a5_field_info[] = {
+ {"GLBL_AXIS_H2C_CNT_A5_MBUSY_CNTS",
+ GLBL_AXIS_H2C_CNT_A5_MBUSY_CNTS_MASK},
};
static struct regfield_info
- c2h_stat_desc_req_field_info[] = {
- {"C2H_STAT_DESC_REQ",
- C2H_STAT_DESC_REQ_MASK},
+ glbl_axis_c2h_cnt_a0_field_info[] = {
+ {"GLBL_AXIS_C2H_CNT_A0_SPKT_CNTS",
+ GLBL_AXIS_C2H_CNT_A0_SPKT_CNTS_MASK},
};
static struct regfield_info
- c2h_stat_dbg_dma_eng_0_field_info[] = {
- {"C2H_STAT_DMA_ENG_0_S_AXIS_C2H_TVALID",
- C2H_STAT_DMA_ENG_0_S_AXIS_C2H_TVALID_MASK},
- {"C2H_STAT_DMA_ENG_0_S_AXIS_C2H_TREADY",
- C2H_STAT_DMA_ENG_0_S_AXIS_C2H_TREADY_MASK},
- {"C2H_STAT_DMA_ENG_0_S_AXIS_WRB_TVALID",
- C2H_STAT_DMA_ENG_0_S_AXIS_WRB_TVALID_MASK},
- {"C2H_STAT_DMA_ENG_0_S_AXIS_WRB_TREADY",
- C2H_STAT_DMA_ENG_0_S_AXIS_WRB_TREADY_MASK},
- {"C2H_STAT_DMA_ENG_0_PLD_FIFO_IN_RDY",
- C2H_STAT_DMA_ENG_0_PLD_FIFO_IN_RDY_MASK},
- {"C2H_STAT_DMA_ENG_0_QID_FIFO_IN_RDY",
- C2H_STAT_DMA_ENG_0_QID_FIFO_IN_RDY_MASK},
- {"C2H_STAT_DMA_ENG_0_ARB_FIFO_OUT_VLD",
- C2H_STAT_DMA_ENG_0_ARB_FIFO_OUT_VLD_MASK},
- {"C2H_STAT_DMA_ENG_0_ARB_FIFO_OUT_QID",
- C2H_STAT_DMA_ENG_0_ARB_FIFO_OUT_QID_MASK},
- {"C2H_STAT_DMA_ENG_0_WRB_FIFO_IN_RDY",
- C2H_STAT_DMA_ENG_0_WRB_FIFO_IN_RDY_MASK},
- {"C2H_STAT_DMA_ENG_0_WRB_FIFO_OUT_CNT",
- C2H_STAT_DMA_ENG_0_WRB_FIFO_OUT_CNT_MASK},
- {"C2H_STAT_DMA_ENG_0_WRB_SM_CS",
- C2H_STAT_DMA_ENG_0_WRB_SM_CS_MASK},
- {"C2H_STAT_DMA_ENG_0_MAIN_SM_CS",
- C2H_STAT_DMA_ENG_0_MAIN_SM_CS_MASK},
+ glbl_axis_c2h_cnt_a1_field_info[] = {
+ {"GLBL_AXIS_C2H_CNT_A1_SIDLE_CNTS",
+ GLBL_AXIS_C2H_CNT_A1_SIDLE_CNTS_MASK},
+ {"GLBL_AXIS_C2H_CNT_A1_SPKT_CNTS",
+ GLBL_AXIS_C2H_CNT_A1_SPKT_CNTS_MASK},
};
static struct regfield_info
- c2h_stat_dbg_dma_eng_1_field_info[] = {
- {"C2H_STAT_DMA_ENG_1_RSVD_1",
- C2H_STAT_DMA_ENG_1_RSVD_1_MASK},
- {"C2H_STAT_DMA_ENG_1_QID_FIFO_OUT_CNT",
- C2H_STAT_DMA_ENG_1_QID_FIFO_OUT_CNT_MASK},
- {"C2H_STAT_DMA_ENG_1_PLD_FIFO_OUT_CNT",
- C2H_STAT_DMA_ENG_1_PLD_FIFO_OUT_CNT_MASK},
- {"C2H_STAT_DMA_ENG_1_PLD_ST_FIFO_CNT",
- C2H_STAT_DMA_ENG_1_PLD_ST_FIFO_CNT_MASK},
+ glbl_axis_c2h_cnt_a2_field_info[] = {
+ {"GLBL_AXIS_C2H_CNT_A2_SIDLE_CNTS",
+ GLBL_AXIS_C2H_CNT_A2_SIDLE_CNTS_MASK},
};
static struct regfield_info
- c2h_stat_dbg_dma_eng_2_field_info[] = {
- {"C2H_STAT_DMA_ENG_2_RSVD_1",
- C2H_STAT_DMA_ENG_2_RSVD_1_MASK},
- {"C2H_STAT_DMA_ENG_2_QID_FIFO_OUT_CNT",
- C2H_STAT_DMA_ENG_2_QID_FIFO_OUT_CNT_MASK},
- {"C2H_STAT_DMA_ENG_2_PLD_FIFO_OUT_CNT",
- C2H_STAT_DMA_ENG_2_PLD_FIFO_OUT_CNT_MASK},
- {"C2H_STAT_DMA_ENG_2_PLD_ST_FIFO_CNT",
- C2H_STAT_DMA_ENG_2_PLD_ST_FIFO_CNT_MASK},
+ glbl_axis_c2h_cnt_a3_field_info[] = {
+ {"GLBL_AXIS_C2H_CNT_A3_SACTV_CNTS",
+ GLBL_AXIS_C2H_CNT_A3_SACTV_CNTS_MASK},
};
static struct regfield_info
- c2h_stat_dbg_dma_eng_3_field_info[] = {
- {"C2H_STAT_DMA_ENG_3_RSVD_1",
- C2H_STAT_DMA_ENG_3_RSVD_1_MASK},
- {"C2H_STAT_DMA_ENG_3_WRQ_FIFO_OUT_CNT",
- C2H_STAT_DMA_ENG_3_WRQ_FIFO_OUT_CNT_MASK},
- {"C2H_STAT_DMA_ENG_3_QID_FIFO_OUT_VLD",
- C2H_STAT_DMA_ENG_3_QID_FIFO_OUT_VLD_MASK},
- {"C2H_STAT_DMA_ENG_3_PLD_FIFO_OUT_VLD",
- C2H_STAT_DMA_ENG_3_PLD_FIFO_OUT_VLD_MASK},
- {"C2H_STAT_DMA_ENG_3_PLD_ST_FIFO_OUT_VLD",
- C2H_STAT_DMA_ENG_3_PLD_ST_FIFO_OUT_VLD_MASK},
- {"C2H_STAT_DMA_ENG_3_PLD_ST_FIFO_OUT_DATA_EOP",
- C2H_STAT_DMA_ENG_3_PLD_ST_FIFO_OUT_DATA_EOP_MASK},
- {"C2H_STAT_DMA_ENG_3_PLD_ST_FIFO_OUT_DATA_AVL_IDX_ENABLE",
- C2H_STAT_DMA_ENG_3_PLD_ST_FIFO_OUT_DATA_AVL_IDX_ENABLE_MASK},
- {"C2H_STAT_DMA_ENG_3_PLD_ST_FIFO_OUT_DATA_DROP",
- C2H_STAT_DMA_ENG_3_PLD_ST_FIFO_OUT_DATA_DROP_MASK},
- {"C2H_STAT_DMA_ENG_3_PLD_ST_FIFO_OUT_DATA_ERR",
- C2H_STAT_DMA_ENG_3_PLD_ST_FIFO_OUT_DATA_ERR_MASK},
- {"C2H_STAT_DMA_ENG_3_DESC_CNT_FIFO_IN_RDY",
- C2H_STAT_DMA_ENG_3_DESC_CNT_FIFO_IN_RDY_MASK},
- {"C2H_STAT_DMA_ENG_3_DESC_RSP_FIFO_IN_RDY",
- C2H_STAT_DMA_ENG_3_DESC_RSP_FIFO_IN_RDY_MASK},
- {"C2H_STAT_DMA_ENG_3_PLD_PKT_ID_LARGER_0",
- C2H_STAT_DMA_ENG_3_PLD_PKT_ID_LARGER_0_MASK},
- {"C2H_STAT_DMA_ENG_3_WRQ_VLD",
- C2H_STAT_DMA_ENG_3_WRQ_VLD_MASK},
- {"C2H_STAT_DMA_ENG_3_WRQ_RDY",
- C2H_STAT_DMA_ENG_3_WRQ_RDY_MASK},
- {"C2H_STAT_DMA_ENG_3_WRQ_FIFO_OUT_RDY",
- C2H_STAT_DMA_ENG_3_WRQ_FIFO_OUT_RDY_MASK},
- {"C2H_STAT_DMA_ENG_3_WRQ_PACKET_OUT_DATA_DROP",
- C2H_STAT_DMA_ENG_3_WRQ_PACKET_OUT_DATA_DROP_MASK},
- {"C2H_STAT_DMA_ENG_3_WRQ_PACKET_OUT_DATA_ERR",
- C2H_STAT_DMA_ENG_3_WRQ_PACKET_OUT_DATA_ERR_MASK},
- {"C2H_STAT_DMA_ENG_3_WRQ_PACKET_OUT_DATA_MARKER",
- C2H_STAT_DMA_ENG_3_WRQ_PACKET_OUT_DATA_MARKER_MASK},
- {"C2H_STAT_DMA_ENG_3_WRQ_PACKET_PRE_EOR",
- C2H_STAT_DMA_ENG_3_WRQ_PACKET_PRE_EOR_MASK},
- {"C2H_STAT_DMA_ENG_3_WCP_FIFO_IN_RDY",
- C2H_STAT_DMA_ENG_3_WCP_FIFO_IN_RDY_MASK},
- {"C2H_STAT_DMA_ENG_3_PLD_ST_FIFO_IN_RDY",
- C2H_STAT_DMA_ENG_3_PLD_ST_FIFO_IN_RDY_MASK},
+ glbl_axis_c2h_cnt_a4_field_info[] = {
+ {"GLBL_AXIS_C2H_CNT_A4_SBUSY_CNTS",
+ GLBL_AXIS_C2H_CNT_A4_SBUSY_CNTS_MASK},
+ {"GLBL_AXIS_C2H_CNT_A4_SACTV_CNTS",
+ GLBL_AXIS_C2H_CNT_A4_SACTV_CNTS_MASK},
};
static struct regfield_info
- c2h_dbg_pfch_err_ctxt_field_info[] = {
- {"C2H_PFCH_ERR_CTXT_RSVD_1",
- C2H_PFCH_ERR_CTXT_RSVD_1_MASK},
- {"C2H_PFCH_ERR_CTXT_ERR_STAT",
- C2H_PFCH_ERR_CTXT_ERR_STAT_MASK},
- {"C2H_PFCH_ERR_CTXT_CMD_WR",
- C2H_PFCH_ERR_CTXT_CMD_WR_MASK},
- {"C2H_PFCH_ERR_CTXT_QID",
- C2H_PFCH_ERR_CTXT_QID_MASK},
- {"C2H_PFCH_ERR_CTXT_DONE",
- C2H_PFCH_ERR_CTXT_DONE_MASK},
+ glbl_axis_c2h_cnt_a5_field_info[] = {
+ {"GLBL_AXIS_C2H_CNT_A5_SBUSY_CNTS",
+ GLBL_AXIS_C2H_CNT_A5_SBUSY_CNTS_MASK},
};
static struct regfield_info
- c2h_first_err_qid_field_info[] = {
- {"C2H_FIRST_ERR_QID_RSVD_1",
- C2H_FIRST_ERR_QID_RSVD_1_MASK},
- {"C2H_FIRST_ERR_QID_ERR_TYPE",
- C2H_FIRST_ERR_QID_ERR_TYPE_MASK},
- {"C2H_FIRST_ERR_QID_RSVD",
- C2H_FIRST_ERR_QID_RSVD_MASK},
- {"C2H_FIRST_ERR_QID_QID",
- C2H_FIRST_ERR_QID_QID_MASK},
+ glbl_m_axi_wr_cnt_a0_field_info[] = {
+ {"GLBL_M_AXI_WR_CNT_A0_PKT_CNTS",
+ GLBL_M_AXI_WR_CNT_A0_PKT_CNTS_MASK},
};
static struct regfield_info
- stat_num_wrb_in_field_info[] = {
- {"STAT_NUM_WRB_IN_RSVD_1",
- STAT_NUM_WRB_IN_RSVD_1_MASK},
- {"STAT_NUM_WRB_IN_WRB_CNT",
- STAT_NUM_WRB_IN_WRB_CNT_MASK},
+ glbl_m_axi_wr_cnt_a1_field_info[] = {
+ {"GLBL_M_AXI_WR_CNT_A1_IDLE_CNTS",
+ GLBL_M_AXI_WR_CNT_A1_IDLE_CNTS_MASK},
+ {"GLBL_M_AXI_WR_CNT_A1_PKT_CNTS",
+ GLBL_M_AXI_WR_CNT_A1_PKT_CNTS_MASK},
};
static struct regfield_info
- stat_num_wrb_out_field_info[] = {
- {"STAT_NUM_WRB_OUT_RSVD_1",
- STAT_NUM_WRB_OUT_RSVD_1_MASK},
- {"STAT_NUM_WRB_OUT_WRB_CNT",
- STAT_NUM_WRB_OUT_WRB_CNT_MASK},
+ glbl_m_axi_wr_cnt_a2_field_info[] = {
+ {"GLBL_M_AXI_WR_CNT_A2_IDLE_CNTS",
+ GLBL_M_AXI_WR_CNT_A2_IDLE_CNTS_MASK},
};
static struct regfield_info
- stat_num_wrb_drp_field_info[] = {
- {"STAT_NUM_WRB_DRP_RSVD_1",
- STAT_NUM_WRB_DRP_RSVD_1_MASK},
- {"STAT_NUM_WRB_DRP_WRB_CNT",
- STAT_NUM_WRB_DRP_WRB_CNT_MASK},
+ glbl_m_axi_wr_cnt_a3_field_info[] = {
+ {"GLBL_M_AXI_WR_CNT_A3_ACTV_CNTS",
+ GLBL_M_AXI_WR_CNT_A3_ACTV_CNTS_MASK},
};
static struct regfield_info
- stat_num_stat_desc_out_field_info[] = {
- {"STAT_NUM_STAT_DESC_OUT_RSVD_1",
- STAT_NUM_STAT_DESC_OUT_RSVD_1_MASK},
- {"STAT_NUM_STAT_DESC_OUT_CNT",
- STAT_NUM_STAT_DESC_OUT_CNT_MASK},
+ glbl_m_axi_wr_cnt_a4_field_info[] = {
+ {"GLBL_M_AXI_WR_CNT_A4_BUSY_CNTS",
+ GLBL_M_AXI_WR_CNT_A4_BUSY_CNTS_MASK},
+ {"GLBL_M_AXI_WR_CNT_A4_ACTV_CNTS",
+ GLBL_M_AXI_WR_CNT_A4_ACTV_CNTS_MASK},
};
static struct regfield_info
- stat_num_dsc_crdt_sent_field_info[] = {
- {"STAT_NUM_DSC_CRDT_SENT_RSVD_1",
- STAT_NUM_DSC_CRDT_SENT_RSVD_1_MASK},
- {"STAT_NUM_DSC_CRDT_SENT_CNT",
- STAT_NUM_DSC_CRDT_SENT_CNT_MASK},
+ glbl_m_axi_wr_cnt_a5_field_info[] = {
+ {"GLBL_M_AXI_WR_CNT_A5_BUSY_CNTS",
+ GLBL_M_AXI_WR_CNT_A5_BUSY_CNTS_MASK},
};
static struct regfield_info
- stat_num_fch_dsc_rcvd_field_info[] = {
- {"STAT_NUM_FCH_DSC_RCVD_RSVD_1",
- STAT_NUM_FCH_DSC_RCVD_RSVD_1_MASK},
- {"STAT_NUM_FCH_DSC_RCVD_DSC_CNT",
- STAT_NUM_FCH_DSC_RCVD_DSC_CNT_MASK},
+ glbl_m_axi_rd_cnt_a0_field_info[] = {
+ {"GLBL_M_AXI_RD_CNT_A0_PKT_CNTS",
+ GLBL_M_AXI_RD_CNT_A0_PKT_CNTS_MASK},
};
static struct regfield_info
- stat_num_byp_dsc_rcvd_field_info[] = {
- {"STAT_NUM_BYP_DSC_RCVD_RSVD_1",
- STAT_NUM_BYP_DSC_RCVD_RSVD_1_MASK},
- {"STAT_NUM_BYP_DSC_RCVD_DSC_CNT",
- STAT_NUM_BYP_DSC_RCVD_DSC_CNT_MASK},
+ glbl_m_axi_rd_cnt_a1_field_info[] = {
+ {"GLBL_M_AXI_RD_CNT_A1_IDLE_CNTS",
+ GLBL_M_AXI_RD_CNT_A1_IDLE_CNTS_MASK},
+ {"GLBL_M_AXI_RD_CNT_A1_PKT_CNTS",
+ GLBL_M_AXI_RD_CNT_A1_PKT_CNTS_MASK},
};
static struct regfield_info
- c2h_wrb_coal_cfg_field_info[] = {
- {"C2H_WRB_COAL_CFG_MAX_BUF_SZ",
- C2H_WRB_COAL_CFG_MAX_BUF_SZ_MASK},
- {"C2H_WRB_COAL_CFG_TICK_VAL",
- C2H_WRB_COAL_CFG_TICK_VAL_MASK},
- {"C2H_WRB_COAL_CFG_TICK_CNT",
- C2H_WRB_COAL_CFG_TICK_CNT_MASK},
- {"C2H_WRB_COAL_CFG_SET_GLB_FLUSH",
- C2H_WRB_COAL_CFG_SET_GLB_FLUSH_MASK},
- {"C2H_WRB_COAL_CFG_DONE_GLB_FLUSH",
- C2H_WRB_COAL_CFG_DONE_GLB_FLUSH_MASK},
+ glbl_m_axi_rd_cnt_a2_field_info[] = {
+ {"GLBL_M_AXI_RD_CNT_A2_IDLE_CNTS",
+ GLBL_M_AXI_RD_CNT_A2_IDLE_CNTS_MASK},
};
static struct regfield_info
- c2h_intr_h2c_req_field_info[] = {
- {"C2H_INTR_H2C_REQ_RSVD_1",
- C2H_INTR_H2C_REQ_RSVD_1_MASK},
- {"C2H_INTR_H2C_REQ_CNT",
- C2H_INTR_H2C_REQ_CNT_MASK},
+ glbl_m_axi_rd_cnt_a3_field_info[] = {
+ {"GLBL_M_AXI_RD_CNT_A3_ACTV_CNTS",
+ GLBL_M_AXI_RD_CNT_A3_ACTV_CNTS_MASK},
};
static struct regfield_info
- c2h_intr_c2h_mm_req_field_info[] = {
- {"C2H_INTR_C2H_MM_REQ_RSVD_1",
- C2H_INTR_C2H_MM_REQ_RSVD_1_MASK},
- {"C2H_INTR_C2H_MM_REQ_CNT",
- C2H_INTR_C2H_MM_REQ_CNT_MASK},
+ glbl_m_axi_rd_cnt_a4_field_info[] = {
+ {"GLBL_M_AXI_RD_CNT_A4_BUSY_CNTS",
+ GLBL_M_AXI_RD_CNT_A4_BUSY_CNTS_MASK},
+ {"GLBL_M_AXI_RD_CNT_A4_ACTV_CNTS",
+ GLBL_M_AXI_RD_CNT_A4_ACTV_CNTS_MASK},
};
static struct regfield_info
- c2h_intr_err_int_req_field_info[] = {
- {"C2H_INTR_ERR_INT_REQ_RSVD_1",
- C2H_INTR_ERR_INT_REQ_RSVD_1_MASK},
- {"C2H_INTR_ERR_INT_REQ_CNT",
- C2H_INTR_ERR_INT_REQ_CNT_MASK},
+ glbl_m_axi_rd_cnt_a5_field_info[] = {
+ {"GLBL_M_AXI_RD_CNT_A5_BUSY_CNTS",
+ GLBL_M_AXI_RD_CNT_A5_BUSY_CNTS_MASK},
};
static struct regfield_info
- c2h_intr_c2h_st_req_field_info[] = {
- {"C2H_INTR_C2H_ST_REQ_RSVD_1",
- C2H_INTR_C2H_ST_REQ_RSVD_1_MASK},
- {"C2H_INTR_C2H_ST_REQ_CNT",
- C2H_INTR_C2H_ST_REQ_CNT_MASK},
+ glbl_m_axib_wr_cnt_a0_field_info[] = {
+ {"GLBL_M_AXIB_WR_CNT_A0_PKT_CNTS",
+ GLBL_M_AXIB_WR_CNT_A0_PKT_CNTS_MASK},
};
static struct regfield_info
- c2h_intr_h2c_err_c2h_mm_msix_ack_field_info[] = {
- {"C2H_INTR_H2C_ERR_C2H_MM_MSIX_ACK_RSVD_1",
- C2H_INTR_H2C_ERR_C2H_MM_MSIX_ACK_RSVD_1_MASK},
- {"C2H_INTR_H2C_ERR_C2H_MM_MSIX_ACK_CNT",
- C2H_INTR_H2C_ERR_C2H_MM_MSIX_ACK_CNT_MASK},
+ glbl_m_axib_wr_cnt_a1_field_info[] = {
+ {"GLBL_M_AXIB_WR_CNT_A1_IDLE_CNTS",
+ GLBL_M_AXIB_WR_CNT_A1_IDLE_CNTS_MASK},
+ {"GLBL_M_AXIB_WR_CNT_A1_PKT_CNTS",
+ GLBL_M_AXIB_WR_CNT_A1_PKT_CNTS_MASK},
};
static struct regfield_info
- c2h_intr_h2c_err_c2h_mm_msix_fail_field_info[] = {
- {"C2H_INTR_H2C_ERR_C2H_MM_MSIX_FAIL_RSVD_1",
- C2H_INTR_H2C_ERR_C2H_MM_MSIX_FAIL_RSVD_1_MASK},
- {"C2H_INTR_H2C_ERR_C2H_MM_MSIX_FAIL_CNT",
- C2H_INTR_H2C_ERR_C2H_MM_MSIX_FAIL_CNT_MASK},
+ glbl_m_axib_wr_cnt_a2_field_info[] = {
+ {"GLBL_M_AXIB_WR_CNT_A2_IDLE_CNTS",
+ GLBL_M_AXIB_WR_CNT_A2_IDLE_CNTS_MASK},
};
static struct regfield_info
- c2h_intr_h2c_err_c2h_mm_msix_no_msix_field_info[] = {
- {"C2H_INTR_H2C_ERR_C2H_MM_MSIX_NO_MSIX_RSVD_1",
- C2H_INTR_H2C_ERR_C2H_MM_MSIX_NO_MSIX_RSVD_1_MASK},
- {"C2H_INTR_H2C_ERR_C2H_MM_MSIX_NO_MSIX_CNT",
- C2H_INTR_H2C_ERR_C2H_MM_MSIX_NO_MSIX_CNT_MASK},
+ glbl_m_axib_wr_cnt_a3_field_info[] = {
+ {"GLBL_M_AXIB_WR_CNT_A3_ACTV_CNTS",
+ GLBL_M_AXIB_WR_CNT_A3_ACTV_CNTS_MASK},
};
static struct regfield_info
- c2h_intr_h2c_err_c2h_mm_ctxt_inval_field_info[] = {
- {"C2H_INTR_H2C_ERR_C2H_MM_CTXT_INVAL_RSVD_1",
- C2H_INTR_H2C_ERR_C2H_MM_CTXT_INVAL_RSVD_1_MASK},
- {"C2H_INTR_H2C_ERR_C2H_MM_CTXT_INVAL_CNT",
- C2H_INTR_H2C_ERR_C2H_MM_CTXT_INVAL_CNT_MASK},
+ glbl_m_axib_wr_cnt_a4_field_info[] = {
+ {"GLBL_M_AXIB_WR_CNT_A4_BUSY_CNTS",
+ GLBL_M_AXIB_WR_CNT_A4_BUSY_CNTS_MASK},
+ {"GLBL_M_AXIB_WR_CNT_A4_ACTV_CNTS",
+ GLBL_M_AXIB_WR_CNT_A4_ACTV_CNTS_MASK},
};
static struct regfield_info
- c2h_intr_c2h_st_msix_ack_field_info[] = {
- {"C2H_INTR_C2H_ST_MSIX_ACK_RSVD_1",
- C2H_INTR_C2H_ST_MSIX_ACK_RSVD_1_MASK},
- {"C2H_INTR_C2H_ST_MSIX_ACK_CNT",
- C2H_INTR_C2H_ST_MSIX_ACK_CNT_MASK},
+ glbl_m_axib_wr_cnt_a5_field_info[] = {
+ {"GLBL_M_AXIB_WR_CNT_A5_BUSY_CNTS",
+ GLBL_M_AXIB_WR_CNT_A5_BUSY_CNTS_MASK},
};
static struct regfield_info
- c2h_intr_c2h_st_msix_fail_field_info[] = {
- {"C2H_INTR_C2H_ST_MSIX_FAIL_RSVD_1",
- C2H_INTR_C2H_ST_MSIX_FAIL_RSVD_1_MASK},
- {"C2H_INTR_C2H_ST_MSIX_FAIL_CNT",
- C2H_INTR_C2H_ST_MSIX_FAIL_CNT_MASK},
+ glbl_m_axib_rd_cnt_a0_field_info[] = {
+ {"GLBL_M_AXIB_RD_CNT_A0_PKT_CNTS",
+ GLBL_M_AXIB_RD_CNT_A0_PKT_CNTS_MASK},
};
static struct regfield_info
- c2h_intr_c2h_st_no_msix_field_info[] = {
- {"C2H_INTR_C2H_ST_NO_MSIX_RSVD_1",
- C2H_INTR_C2H_ST_NO_MSIX_RSVD_1_MASK},
- {"C2H_INTR_C2H_ST_NO_MSIX_CNT",
- C2H_INTR_C2H_ST_NO_MSIX_CNT_MASK},
+ glbl_m_axib_rd_cnt_a1_field_info[] = {
+ {"GLBL_M_AXIB_RD_CNT_A1_IDLE_CNTS",
+ GLBL_M_AXIB_RD_CNT_A1_IDLE_CNTS_MASK},
+ {"GLBL_M_AXIB_RD_CNT_A1_PKT_CNTS",
+ GLBL_M_AXIB_RD_CNT_A1_PKT_CNTS_MASK},
};
static struct regfield_info
- c2h_intr_c2h_st_ctxt_inval_field_info[] = {
- {"C2H_INTR_C2H_ST_CTXT_INVAL_RSVD_1",
- C2H_INTR_C2H_ST_CTXT_INVAL_RSVD_1_MASK},
- {"C2H_INTR_C2H_ST_CTXT_INVAL_CNT",
- C2H_INTR_C2H_ST_CTXT_INVAL_CNT_MASK},
+ glbl_m_axib_rd_cnt_a2_field_info[] = {
+ {"GLBL_M_AXIB_RD_CNT_A2_IDLE_CNTS",
+ GLBL_M_AXIB_RD_CNT_A2_IDLE_CNTS_MASK},
};
static struct regfield_info
- c2h_stat_wr_cmp_field_info[] = {
- {"C2H_STAT_WR_CMP_RSVD_1",
- C2H_STAT_WR_CMP_RSVD_1_MASK},
- {"C2H_STAT_WR_CMP_CNT",
- C2H_STAT_WR_CMP_CNT_MASK},
+ glbl_m_axib_rd_cnt_a3_field_info[] = {
+ {"GLBL_M_AXIB_RD_CNT_A3_ACTV_CNTS",
+ GLBL_M_AXIB_RD_CNT_A3_ACTV_CNTS_MASK},
};
static struct regfield_info
- c2h_stat_dbg_dma_eng_4_field_info[] = {
- {"C2H_STAT_DMA_ENG_4_RSVD_1",
- C2H_STAT_DMA_ENG_4_RSVD_1_MASK},
- {"C2H_STAT_DMA_ENG_4_WRQ_FIFO_OUT_CNT",
- C2H_STAT_DMA_ENG_4_WRQ_FIFO_OUT_CNT_MASK},
- {"C2H_STAT_DMA_ENG_4_QID_FIFO_OUT_VLD",
- C2H_STAT_DMA_ENG_4_QID_FIFO_OUT_VLD_MASK},
- {"C2H_STAT_DMA_ENG_4_PLD_FIFO_OUT_VLD",
- C2H_STAT_DMA_ENG_4_PLD_FIFO_OUT_VLD_MASK},
- {"C2H_STAT_DMA_ENG_4_PLD_ST_FIFO_OUT_VLD",
- C2H_STAT_DMA_ENG_4_PLD_ST_FIFO_OUT_VLD_MASK},
- {"C2H_STAT_DMA_ENG_4_PLD_ST_FIFO_OUT_DATA_EOP",
- C2H_STAT_DMA_ENG_4_PLD_ST_FIFO_OUT_DATA_EOP_MASK},
- {"C2H_STAT_DMA_ENG_4_PLD_ST_FIFO_OUT_DATA_AVL_IDX_ENABLE",
- C2H_STAT_DMA_ENG_4_PLD_ST_FIFO_OUT_DATA_AVL_IDX_ENABLE_MASK},
- {"C2H_STAT_DMA_ENG_4_PLD_ST_FIFO_OUT_DATA_DROP",
- C2H_STAT_DMA_ENG_4_PLD_ST_FIFO_OUT_DATA_DROP_MASK},
- {"C2H_STAT_DMA_ENG_4_PLD_ST_FIFO_OUT_DATA_ERR",
- C2H_STAT_DMA_ENG_4_PLD_ST_FIFO_OUT_DATA_ERR_MASK},
- {"C2H_STAT_DMA_ENG_4_DESC_CNT_FIFO_IN_RDY",
- C2H_STAT_DMA_ENG_4_DESC_CNT_FIFO_IN_RDY_MASK},
- {"C2H_STAT_DMA_ENG_4_DESC_RSP_FIFO_IN_RDY",
- C2H_STAT_DMA_ENG_4_DESC_RSP_FIFO_IN_RDY_MASK},
- {"C2H_STAT_DMA_ENG_4_PLD_PKT_ID_LARGER_0",
- C2H_STAT_DMA_ENG_4_PLD_PKT_ID_LARGER_0_MASK},
- {"C2H_STAT_DMA_ENG_4_WRQ_VLD",
- C2H_STAT_DMA_ENG_4_WRQ_VLD_MASK},
- {"C2H_STAT_DMA_ENG_4_WRQ_RDY",
- C2H_STAT_DMA_ENG_4_WRQ_RDY_MASK},
- {"C2H_STAT_DMA_ENG_4_WRQ_FIFO_OUT_RDY",
- C2H_STAT_DMA_ENG_4_WRQ_FIFO_OUT_RDY_MASK},
- {"C2H_STAT_DMA_ENG_4_WRQ_PACKET_OUT_DATA_DROP",
- C2H_STAT_DMA_ENG_4_WRQ_PACKET_OUT_DATA_DROP_MASK},
- {"C2H_STAT_DMA_ENG_4_WRQ_PACKET_OUT_DATA_ERR",
- C2H_STAT_DMA_ENG_4_WRQ_PACKET_OUT_DATA_ERR_MASK},
- {"C2H_STAT_DMA_ENG_4_WRQ_PACKET_OUT_DATA_MARKER",
- C2H_STAT_DMA_ENG_4_WRQ_PACKET_OUT_DATA_MARKER_MASK},
- {"C2H_STAT_DMA_ENG_4_WRQ_PACKET_PRE_EOR",
- C2H_STAT_DMA_ENG_4_WRQ_PACKET_PRE_EOR_MASK},
- {"C2H_STAT_DMA_ENG_4_WCP_FIFO_IN_RDY",
- C2H_STAT_DMA_ENG_4_WCP_FIFO_IN_RDY_MASK},
- {"C2H_STAT_DMA_ENG_4_PLD_ST_FIFO_IN_RDY",
- C2H_STAT_DMA_ENG_4_PLD_ST_FIFO_IN_RDY_MASK},
+ glbl_m_axib_rd_cnt_a4_field_info[] = {
+ {"GLBL_M_AXIB_RD_CNT_A4_BUSY_CNTS",
+ GLBL_M_AXIB_RD_CNT_A4_BUSY_CNTS_MASK},
+ {"GLBL_M_AXIB_RD_CNT_A4_ACTV_CNTS",
+ GLBL_M_AXIB_RD_CNT_A4_ACTV_CNTS_MASK},
};
static struct regfield_info
- c2h_stat_dbg_dma_eng_5_field_info[] = {
- {"C2H_STAT_DMA_ENG_5_RSVD_1",
- C2H_STAT_DMA_ENG_5_RSVD_1_MASK},
- {"C2H_STAT_DMA_ENG_5_WRB_SM_VIRT_CH",
- C2H_STAT_DMA_ENG_5_WRB_SM_VIRT_CH_MASK},
- {"C2H_STAT_DMA_ENG_5_WRB_FIFO_IN_REQ",
- C2H_STAT_DMA_ENG_5_WRB_FIFO_IN_REQ_MASK},
- {"C2H_STAT_DMA_ENG_5_ARB_FIFO_OUT_CNT",
- C2H_STAT_DMA_ENG_5_ARB_FIFO_OUT_CNT_MASK},
- {"C2H_STAT_DMA_ENG_5_ARB_FIFO_OUT_DATA_LEN",
- C2H_STAT_DMA_ENG_5_ARB_FIFO_OUT_DATA_LEN_MASK},
- {"C2H_STAT_DMA_ENG_5_ARB_FIFO_OUT_DATA_VIRT_CH",
- C2H_STAT_DMA_ENG_5_ARB_FIFO_OUT_DATA_VIRT_CH_MASK},
- {"C2H_STAT_DMA_ENG_5_ARB_FIFO_OUT_DATA_VAR_DESC",
- C2H_STAT_DMA_ENG_5_ARB_FIFO_OUT_DATA_VAR_DESC_MASK},
- {"C2H_STAT_DMA_ENG_5_ARB_FIFO_OUT_DATA_DROP_REQ",
- C2H_STAT_DMA_ENG_5_ARB_FIFO_OUT_DATA_DROP_REQ_MASK},
- {"C2H_STAT_DMA_ENG_5_ARB_FIFO_OUT_DATA_NUM_BUF_OV",
- C2H_STAT_DMA_ENG_5_ARB_FIFO_OUT_DATA_NUM_BUF_OV_MASK},
- {"C2H_STAT_DMA_ENG_5_ARB_FIFO_OUT_DATA_MARKER",
- C2H_STAT_DMA_ENG_5_ARB_FIFO_OUT_DATA_MARKER_MASK},
- {"C2H_STAT_DMA_ENG_5_ARB_FIFO_OUT_DATA_HAS_CMPT",
- C2H_STAT_DMA_ENG_5_ARB_FIFO_OUT_DATA_HAS_CMPT_MASK},
+ glbl_m_axib_rd_cnt_a5_field_info[] = {
+ {"GLBL_M_AXIB_RD_CNT_A5_BUSY_CNTS",
+ GLBL_M_AXIB_RD_CNT_A5_BUSY_CNTS_MASK},
};
static struct regfield_info
- c2h_dbg_pfch_qid_field_info[] = {
- {"C2H_PFCH_QID_RSVD_1",
- C2H_PFCH_QID_RSVD_1_MASK},
- {"C2H_PFCH_QID_ERR_CTXT",
- C2H_PFCH_QID_ERR_CTXT_MASK},
- {"C2H_PFCH_QID_TARGET",
- C2H_PFCH_QID_TARGET_MASK},
- {"C2H_PFCH_QID_QID_OR_TAG",
- C2H_PFCH_QID_QID_OR_TAG_MASK},
+ glbl_s_axi_wr_cnt_a0_field_info[] = {
+ {"GLBL_S_AXI_WR_CNT_A0_PKT_CNTS",
+ GLBL_S_AXI_WR_CNT_A0_PKT_CNTS_MASK},
};
static struct regfield_info
- c2h_dbg_pfch_field_info[] = {
- {"C2H_PFCH_DATA",
- C2H_PFCH_DATA_MASK},
+ glbl_s_axi_wr_cnt_a1_field_info[] = {
+ {"GLBL_S_AXI_WR_CNT_A1_IDLE_CNTS",
+ GLBL_S_AXI_WR_CNT_A1_IDLE_CNTS_MASK},
+ {"GLBL_S_AXI_WR_CNT_A1_PKT_CNTS",
+ GLBL_S_AXI_WR_CNT_A1_PKT_CNTS_MASK},
};
static struct regfield_info
- c2h_int_dbg_field_info[] = {
- {"C2H_INT_RSVD_1",
- C2H_INT_RSVD_1_MASK},
- {"C2H_INT_INT_COAL_SM",
- C2H_INT_INT_COAL_SM_MASK},
- {"C2H_INT_INT_SM",
- C2H_INT_INT_SM_MASK},
+ glbl_s_axi_wr_cnt_a2_field_info[] = {
+ {"GLBL_S_AXI_WR_CNT_A2_IDLE_CNTS",
+ GLBL_S_AXI_WR_CNT_A2_IDLE_CNTS_MASK},
};
static struct regfield_info
- c2h_stat_imm_accepted_field_info[] = {
- {"C2H_STAT_IMM_ACCEPTED_RSVD_1",
- C2H_STAT_IMM_ACCEPTED_RSVD_1_MASK},
- {"C2H_STAT_IMM_ACCEPTED_CNT",
- C2H_STAT_IMM_ACCEPTED_CNT_MASK},
+ glbl_s_axi_wr_cnt_a3_field_info[] = {
+ {"GLBL_S_AXI_WR_CNT_A3_ACTV_CNTS",
+ GLBL_S_AXI_WR_CNT_A3_ACTV_CNTS_MASK},
};
static struct regfield_info
- c2h_stat_marker_accepted_field_info[] = {
- {"C2H_STAT_MARKER_ACCEPTED_RSVD_1",
- C2H_STAT_MARKER_ACCEPTED_RSVD_1_MASK},
- {"C2H_STAT_MARKER_ACCEPTED_CNT",
- C2H_STAT_MARKER_ACCEPTED_CNT_MASK},
+ glbl_s_axi_wr_cnt_a4_field_info[] = {
+ {"GLBL_S_AXI_WR_CNT_A4_BUSY_CNTS",
+ GLBL_S_AXI_WR_CNT_A4_BUSY_CNTS_MASK},
+ {"GLBL_S_AXI_WR_CNT_A4_ACTV_CNTS",
+ GLBL_S_AXI_WR_CNT_A4_ACTV_CNTS_MASK},
};
static struct regfield_info
- c2h_stat_disable_cmp_accepted_field_info[] = {
- {"C2H_STAT_DISABLE_CMP_ACCEPTED_RSVD_1",
- C2H_STAT_DISABLE_CMP_ACCEPTED_RSVD_1_MASK},
- {"C2H_STAT_DISABLE_CMP_ACCEPTED_CNT",
- C2H_STAT_DISABLE_CMP_ACCEPTED_CNT_MASK},
+ glbl_s_axi_wr_cnt_a5_field_info[] = {
+ {"GLBL_S_AXI_WR_CNT_A5_BUSY_CNTS",
+ GLBL_S_AXI_WR_CNT_A5_BUSY_CNTS_MASK},
};
static struct regfield_info
- c2h_pld_fifo_crdt_cnt_field_info[] = {
- {"C2H_PLD_FIFO_CRDT_CNT_RSVD_1",
- C2H_PLD_FIFO_CRDT_CNT_RSVD_1_MASK},
- {"C2H_PLD_FIFO_CRDT_CNT_CNT",
- C2H_PLD_FIFO_CRDT_CNT_CNT_MASK},
+ glbl_s_axi_rd_cnt_a0_field_info[] = {
+ {"GLBL_S_AXI_RD_CNT_A0_PKT_CNTS",
+ GLBL_S_AXI_RD_CNT_A0_PKT_CNTS_MASK},
};
static struct regfield_info
- c2h_intr_dyn_req_field_info[] = {
- {"C2H_INTR_DYN_REQ_RSVD_1",
- C2H_INTR_DYN_REQ_RSVD_1_MASK},
- {"C2H_INTR_DYN_REQ_CNT",
- C2H_INTR_DYN_REQ_CNT_MASK},
+ glbl_s_axi_rd_cnt_a1_field_info[] = {
+ {"GLBL_S_AXI_RD_CNT_A1_IDLE_CNTS",
+ GLBL_S_AXI_RD_CNT_A1_IDLE_CNTS_MASK},
+ {"GLBL_S_AXI_RD_CNT_A1_PKT_CNTS",
+ GLBL_S_AXI_RD_CNT_A1_PKT_CNTS_MASK},
};
static struct regfield_info
- c2h_intr_dyn_misc_field_info[] = {
- {"C2H_INTR_DYN_MISC_RSVD_1",
- C2H_INTR_DYN_MISC_RSVD_1_MASK},
- {"C2H_INTR_DYN_MISC_CNT",
- C2H_INTR_DYN_MISC_CNT_MASK},
+ glbl_s_axi_rd_cnt_a2_field_info[] = {
+ {"GLBL_S_AXI_RD_CNT_A2_IDLE_CNTS",
+ GLBL_S_AXI_RD_CNT_A2_IDLE_CNTS_MASK},
};
static struct regfield_info
- c2h_drop_len_mismatch_field_info[] = {
- {"C2H_DROP_LEN_MISMATCH_RSVD_1",
- C2H_DROP_LEN_MISMATCH_RSVD_1_MASK},
- {"C2H_DROP_LEN_MISMATCH_CNT",
- C2H_DROP_LEN_MISMATCH_CNT_MASK},
+ glbl_s_axi_rd_cnt_a3_field_info[] = {
+ {"GLBL_S_AXI_RD_CNT_A3_ACTV_CNTS",
+ GLBL_S_AXI_RD_CNT_A3_ACTV_CNTS_MASK},
};
static struct regfield_info
- c2h_drop_desc_rsp_len_field_info[] = {
- {"C2H_DROP_DESC_RSP_LEN_RSVD_1",
- C2H_DROP_DESC_RSP_LEN_RSVD_1_MASK},
- {"C2H_DROP_DESC_RSP_LEN_CNT",
- C2H_DROP_DESC_RSP_LEN_CNT_MASK},
+ glbl_s_axi_rd_cnt_a4_field_info[] = {
+ {"GLBL_S_AXI_RD_CNT_A4_BUSY_CNTS",
+ GLBL_S_AXI_RD_CNT_A4_BUSY_CNTS_MASK},
+ {"GLBL_S_AXI_RD_CNT_A4_ACTV_CNTS",
+ GLBL_S_AXI_RD_CNT_A4_ACTV_CNTS_MASK},
};
static struct regfield_info
- c2h_drop_qid_fifo_len_field_info[] = {
- {"C2H_DROP_QID_FIFO_LEN_RSVD_1",
- C2H_DROP_QID_FIFO_LEN_RSVD_1_MASK},
- {"C2H_DROP_QID_FIFO_LEN_CNT",
- C2H_DROP_QID_FIFO_LEN_CNT_MASK},
+ glbl_s_axi_rd_cnt_a5_field_info[] = {
+ {"GLBL_S_AXI_RD_CNT_A5_BUSY_CNTS",
+ GLBL_S_AXI_RD_CNT_A5_BUSY_CNTS_MASK},
};
static struct regfield_info
- c2h_drop_pld_cnt_field_info[] = {
- {"C2H_DROP_PLD_CNT_RSVD_1",
- C2H_DROP_PLD_CNT_RSVD_1_MASK},
- {"C2H_DROP_PLD_CNT_CNT",
- C2H_DROP_PLD_CNT_CNT_MASK},
-};
-
-
-static struct regfield_info
- c2h_cmpt_format_0_field_info[] = {
- {"C2H_CMPT_FORMAT_0_DESC_ERR_LOC",
- C2H_CMPT_FORMAT_0_DESC_ERR_LOC_MASK},
- {"C2H_CMPT_FORMAT_0_COLOR_LOC",
- C2H_CMPT_FORMAT_0_COLOR_LOC_MASK},
-};
-
-
-static struct regfield_info
- c2h_cmpt_format_1_field_info[] = {
- {"C2H_CMPT_FORMAT_1_DESC_ERR_LOC",
- C2H_CMPT_FORMAT_1_DESC_ERR_LOC_MASK},
- {"C2H_CMPT_FORMAT_1_COLOR_LOC",
- C2H_CMPT_FORMAT_1_COLOR_LOC_MASK},
-};
-
-
-static struct regfield_info
- c2h_cmpt_format_2_field_info[] = {
- {"C2H_CMPT_FORMAT_2_DESC_ERR_LOC",
- C2H_CMPT_FORMAT_2_DESC_ERR_LOC_MASK},
- {"C2H_CMPT_FORMAT_2_COLOR_LOC",
- C2H_CMPT_FORMAT_2_COLOR_LOC_MASK},
+ glbl_s_axis_cmp_cnt_a0_field_info[] = {
+ {"GLBL_S_AXIS_CMP_CNT_A0_PKT_CNTS",
+ GLBL_S_AXIS_CMP_CNT_A0_PKT_CNTS_MASK},
};
static struct regfield_info
- c2h_cmpt_format_3_field_info[] = {
- {"C2H_CMPT_FORMAT_3_DESC_ERR_LOC",
- C2H_CMPT_FORMAT_3_DESC_ERR_LOC_MASK},
- {"C2H_CMPT_FORMAT_3_COLOR_LOC",
- C2H_CMPT_FORMAT_3_COLOR_LOC_MASK},
+ glbl_s_axis_cmp_cnt_a1_field_info[] = {
+ {"GLBL_S_AXIS_CMP_CNT_A1_IDLE_CNTS",
+ GLBL_S_AXIS_CMP_CNT_A1_IDLE_CNTS_MASK},
+ {"GLBL_S_AXIS_CMP_CNT_A1_PKT_CNTS",
+ GLBL_S_AXIS_CMP_CNT_A1_PKT_CNTS_MASK},
};
static struct regfield_info
- c2h_cmpt_format_4_field_info[] = {
- {"C2H_CMPT_FORMAT_4_DESC_ERR_LOC",
- C2H_CMPT_FORMAT_4_DESC_ERR_LOC_MASK},
- {"C2H_CMPT_FORMAT_4_COLOR_LOC",
- C2H_CMPT_FORMAT_4_COLOR_LOC_MASK},
+ glbl_s_axis_cmp_cnt_a2_field_info[] = {
+ {"GLBL_S_AXIS_CMP_CNT_A2_IDLE_CNTS",
+ GLBL_S_AXIS_CMP_CNT_A2_IDLE_CNTS_MASK},
};
static struct regfield_info
- c2h_cmpt_format_5_field_info[] = {
- {"C2H_CMPT_FORMAT_5_DESC_ERR_LOC",
- C2H_CMPT_FORMAT_5_DESC_ERR_LOC_MASK},
- {"C2H_CMPT_FORMAT_5_COLOR_LOC",
- C2H_CMPT_FORMAT_5_COLOR_LOC_MASK},
+ glbl_s_axis_cmp_cnt_a3_field_info[] = {
+ {"GLBL_S_AXIS_CMP_CNT_A3_ACTV_CNTS",
+ GLBL_S_AXIS_CMP_CNT_A3_ACTV_CNTS_MASK},
};
static struct regfield_info
- c2h_cmpt_format_6_field_info[] = {
- {"C2H_CMPT_FORMAT_6_DESC_ERR_LOC",
- C2H_CMPT_FORMAT_6_DESC_ERR_LOC_MASK},
- {"C2H_CMPT_FORMAT_6_COLOR_LOC",
- C2H_CMPT_FORMAT_6_COLOR_LOC_MASK},
+ glbl_s_axis_cmp_cnt_a4_field_info[] = {
+ {"GLBL_S_AXIS_CMP_CNT_A4_BUSY_CNTS",
+ GLBL_S_AXIS_CMP_CNT_A4_BUSY_CNTS_MASK},
+ {"GLBL_S_AXIS_CMP_CNT_A4_ACTV_CNTS",
+ GLBL_S_AXIS_CMP_CNT_A4_ACTV_CNTS_MASK},
};
static struct regfield_info
- c2h_pfch_cache_depth_field_info[] = {
- {"C2H_PFCH_CACHE_DEPTH_MAX_STBUF",
- C2H_PFCH_CACHE_DEPTH_MAX_STBUF_MASK},
- {"C2H_PFCH_CACHE_DEPTH",
- C2H_PFCH_CACHE_DEPTH_MASK},
+ glbl_s_axis_cmp_cnt_a5_field_info[] = {
+ {"GLBL_S_AXIS_CMP_CNT_A5_BUSY_CNTS",
+ GLBL_S_AXIS_CMP_CNT_A5_BUSY_CNTS_MASK},
};
static struct regfield_info
- c2h_wrb_coal_buf_depth_field_info[] = {
- {"C2H_WRB_COAL_BUF_DEPTH_RSVD_1",
- C2H_WRB_COAL_BUF_DEPTH_RSVD_1_MASK},
- {"C2H_WRB_COAL_BUF_DEPTH_BUFFER",
- C2H_WRB_COAL_BUF_DEPTH_BUFFER_MASK},
+ ind_ctxt_data_field_info[] = {
+ {"IND_CTXT_DATA_DATA",
+ IND_CTXT_DATA_DATA_MASK},
};
static struct regfield_info
- c2h_pfch_crdt_field_info[] = {
- {"C2H_PFCH_CRDT_RSVD_1",
- C2H_PFCH_CRDT_RSVD_1_MASK},
- {"C2H_PFCH_CRDT_RSVD_2",
- C2H_PFCH_CRDT_RSVD_2_MASK},
+ ind_ctxt_mask_field_info[] = {
+ {"IND_CTXT",
+ IND_CTXT_MASK},
};
static struct regfield_info
- c2h_stat_has_cmpt_accepted_field_info[] = {
- {"C2H_STAT_HAS_CMPT_ACCEPTED_RSVD_1",
- C2H_STAT_HAS_CMPT_ACCEPTED_RSVD_1_MASK},
- {"C2H_STAT_HAS_CMPT_ACCEPTED_CNT",
- C2H_STAT_HAS_CMPT_ACCEPTED_CNT_MASK},
+ ind_ctxt_cmd_field_info[] = {
+ {"IND_CTXT_CMD_RSVD_1",
+ IND_CTXT_CMD_RSVD_1_MASK},
+ {"IND_CTXT_CMD_QID",
+ IND_CTXT_CMD_QID_MASK},
+ {"IND_CTXT_CMD_OP",
+ IND_CTXT_CMD_OP_MASK},
+ {"IND_CTXT_CMD_SEL",
+ IND_CTXT_CMD_SEL_MASK},
+ {"IND_CTXT_CMD_BUSY",
+ IND_CTXT_CMD_BUSY_MASK},
};
static struct regfield_info
- c2h_stat_has_pld_accepted_field_info[] = {
- {"C2H_STAT_HAS_PLD_ACCEPTED_RSVD_1",
- C2H_STAT_HAS_PLD_ACCEPTED_RSVD_1_MASK},
- {"C2H_STAT_HAS_PLD_ACCEPTED_CNT",
- C2H_STAT_HAS_PLD_ACCEPTED_CNT_MASK},
+ c2h_timer_cnt_field_info[] = {
+ {"C2H_TIMER_CNT_RSVD_1",
+ C2H_TIMER_CNT_RSVD_1_MASK},
+ {"C2H_TIMER_CNT",
+ C2H_TIMER_CNT_MASK},
};
static struct regfield_info
- c2h_pld_pkt_id_field_info[] = {
- {"C2H_PLD_PKT_ID_CMPT_WAIT",
- C2H_PLD_PKT_ID_CMPT_WAIT_MASK},
- {"C2H_PLD_PKT_ID_DATA",
- C2H_PLD_PKT_ID_DATA_MASK},
+ c2h_cnt_th_field_info[] = {
+ {"C2H_CNT_TH_RSVD_1",
+ C2H_CNT_TH_RSVD_1_MASK},
+ {"C2H_CNT_TH_THESHOLD_CNT",
+ C2H_CNT_TH_THESHOLD_CNT_MASK},
};
static struct regfield_info
- c2h_pld_pkt_id_1_field_info[] = {
- {"C2H_PLD_PKT_ID_1_CMPT_WAIT",
- C2H_PLD_PKT_ID_1_CMPT_WAIT_MASK},
- {"C2H_PLD_PKT_ID_1_DATA",
- C2H_PLD_PKT_ID_1_DATA_MASK},
+ c2h_pfch_cfg_1_field_info[] = {
+ {"C2H_PFCH_CFG_1_EVT_QCNT_TH",
+ C2H_PFCH_CFG_1_EVT_QCNT_TH_MASK},
+ {"C2H_PFCH_CFG_1_QCNT",
+ C2H_PFCH_CFG_1_QCNT_MASK},
};
static struct regfield_info
- c2h_drop_pld_cnt_1_field_info[] = {
- {"C2H_DROP_PLD_CNT_1_RSVD_1",
- C2H_DROP_PLD_CNT_1_RSVD_1_MASK},
- {"C2H_DROP_PLD_CNT_1_CNT",
- C2H_DROP_PLD_CNT_1_CNT_MASK},
+ c2h_pfch_cfg_2_field_info[] = {
+ {"C2H_PFCH_CFG_2_FENCE",
+ C2H_PFCH_CFG_2_FENCE_MASK},
+ {"C2H_PFCH_CFG_2_RSVD",
+ C2H_PFCH_CFG_2_RSVD_MASK},
+ {"C2H_PFCH_CFG_2_VAR_DESC_NO_DROP",
+ C2H_PFCH_CFG_2_VAR_DESC_NO_DROP_MASK},
+ {"C2H_PFCH_CFG_2_LL_SZ_TH",
+ C2H_PFCH_CFG_2_LL_SZ_TH_MASK},
+ {"C2H_PFCH_CFG_2_VAR_DESC_NUM",
+ C2H_PFCH_CFG_2_VAR_DESC_NUM_MASK},
+ {"C2H_PFCH_CFG_2_NUM",
+ C2H_PFCH_CFG_2_NUM_MASK},
};
static struct regfield_info
- h2c_err_stat_field_info[] = {
- {"H2C_ERR_STAT_RSVD_1",
- H2C_ERR_STAT_RSVD_1_MASK},
- {"H2C_ERR_STAT_PAR_ERR",
- H2C_ERR_STAT_PAR_ERR_MASK},
- {"H2C_ERR_STAT_SBE",
- H2C_ERR_STAT_SBE_MASK},
- {"H2C_ERR_STAT_DBE",
- H2C_ERR_STAT_DBE_MASK},
- {"H2C_ERR_STAT_NO_DMA_DS",
- H2C_ERR_STAT_NO_DMA_DS_MASK},
- {"H2C_ERR_STAT_SDI_MRKR_REQ_MOP_ERR",
- H2C_ERR_STAT_SDI_MRKR_REQ_MOP_ERR_MASK},
- {"H2C_ERR_STAT_ZERO_LEN_DS",
- H2C_ERR_STAT_ZERO_LEN_DS_MASK},
+ c2h_stat_s_axis_c2h_accepted_field_info[] = {
+ {"C2H_STAT_S_AXIS_C2H_ACCEPTED",
+ C2H_STAT_S_AXIS_C2H_ACCEPTED_MASK},
};
static struct regfield_info
- h2c_err_mask_field_info[] = {
- {"H2C_ERR_EN",
- H2C_ERR_EN_MASK},
+ c2h_stat_s_axis_wrb_accepted_field_info[] = {
+ {"C2H_STAT_S_AXIS_WRB_ACCEPTED",
+ C2H_STAT_S_AXIS_WRB_ACCEPTED_MASK},
};
static struct regfield_info
- h2c_first_err_qid_field_info[] = {
- {"H2C_FIRST_ERR_QID_RSVD_1",
- H2C_FIRST_ERR_QID_RSVD_1_MASK},
- {"H2C_FIRST_ERR_QID_ERR_TYPE",
- H2C_FIRST_ERR_QID_ERR_TYPE_MASK},
- {"H2C_FIRST_ERR_QID_RSVD_2",
- H2C_FIRST_ERR_QID_RSVD_2_MASK},
- {"H2C_FIRST_ERR_QID_QID",
- H2C_FIRST_ERR_QID_QID_MASK},
+ c2h_stat_desc_rsp_pkt_accepted_field_info[] = {
+ {"C2H_STAT_DESC_RSP_PKT_ACCEPTED_D",
+ C2H_STAT_DESC_RSP_PKT_ACCEPTED_D_MASK},
};
static struct regfield_info
- h2c_dbg_reg0_field_info[] = {
- {"H2C_REG0_NUM_DSC_RCVD",
- H2C_REG0_NUM_DSC_RCVD_MASK},
- {"H2C_REG0_NUM_WRB_SENT",
- H2C_REG0_NUM_WRB_SENT_MASK},
+ c2h_stat_axis_pkg_cmp_field_info[] = {
+ {"C2H_STAT_AXIS_PKG_CMP",
+ C2H_STAT_AXIS_PKG_CMP_MASK},
};
static struct regfield_info
- h2c_dbg_reg1_field_info[] = {
- {"H2C_REG1_NUM_REQ_SENT",
- H2C_REG1_NUM_REQ_SENT_MASK},
- {"H2C_REG1_NUM_CMP_SENT",
- H2C_REG1_NUM_CMP_SENT_MASK},
+ c2h_stat_desc_rsp_accepted_field_info[] = {
+ {"C2H_STAT_DESC_RSP_ACCEPTED_D",
+ C2H_STAT_DESC_RSP_ACCEPTED_D_MASK},
};
static struct regfield_info
- h2c_dbg_reg2_field_info[] = {
- {"H2C_REG2_RSVD_1",
- H2C_REG2_RSVD_1_MASK},
- {"H2C_REG2_NUM_ERR_DSC_RCVD",
- H2C_REG2_NUM_ERR_DSC_RCVD_MASK},
+ c2h_stat_desc_rsp_cmp_field_info[] = {
+ {"C2H_STAT_DESC_RSP_CMP_D",
+ C2H_STAT_DESC_RSP_CMP_D_MASK},
};
static struct regfield_info
- h2c_dbg_reg3_field_info[] = {
- {"H2C_REG3_RSVD_1",
- H2C_REG3_RSVD_1_MASK},
- {"H2C_REG3_DSCO_FIFO_EMPTY",
- H2C_REG3_DSCO_FIFO_EMPTY_MASK},
- {"H2C_REG3_DSCO_FIFO_FULL",
- H2C_REG3_DSCO_FIFO_FULL_MASK},
- {"H2C_REG3_CUR_RC_STATE",
- H2C_REG3_CUR_RC_STATE_MASK},
- {"H2C_REG3_RDREQ_LINES",
- H2C_REG3_RDREQ_LINES_MASK},
- {"H2C_REG3_RDATA_LINES_AVAIL",
- H2C_REG3_RDATA_LINES_AVAIL_MASK},
- {"H2C_REG3_PEND_FIFO_EMPTY",
- H2C_REG3_PEND_FIFO_EMPTY_MASK},
- {"H2C_REG3_PEND_FIFO_FULL",
- H2C_REG3_PEND_FIFO_FULL_MASK},
- {"H2C_REG3_CUR_RQ_STATE",
- H2C_REG3_CUR_RQ_STATE_MASK},
- {"H2C_REG3_DSCI_FIFO_FULL",
- H2C_REG3_DSCI_FIFO_FULL_MASK},
- {"H2C_REG3_DSCI_FIFO_EMPTY",
- H2C_REG3_DSCI_FIFO_EMPTY_MASK},
+ c2h_stat_wrq_out_field_info[] = {
+ {"C2H_STAT_WRQ_OUT",
+ C2H_STAT_WRQ_OUT_MASK},
};
static struct regfield_info
- h2c_dbg_reg4_field_info[] = {
- {"H2C_REG4_RDREQ_ADDR",
- H2C_REG4_RDREQ_ADDR_MASK},
+ c2h_stat_wpl_ren_accepted_field_info[] = {
+ {"C2H_STAT_WPL_REN_ACCEPTED",
+ C2H_STAT_WPL_REN_ACCEPTED_MASK},
};
static struct regfield_info
- h2c_fatal_err_en_field_info[] = {
- {"H2C_FATAL_ERR_EN_RSVD_1",
- H2C_FATAL_ERR_EN_RSVD_1_MASK},
- {"H2C_FATAL_ERR_EN_H2C",
- H2C_FATAL_ERR_EN_H2C_MASK},
+ c2h_stat_total_wrq_len_field_info[] = {
+ {"C2H_STAT_TOTAL_WRQ_LEN",
+ C2H_STAT_TOTAL_WRQ_LEN_MASK},
};
static struct regfield_info
- h2c_req_throt_pcie_field_info[] = {
- {"H2C_REQ_THROT_PCIE_EN_REQ",
- H2C_REQ_THROT_PCIE_EN_REQ_MASK},
- {"H2C_REQ_THROT_PCIE",
- H2C_REQ_THROT_PCIE_MASK},
- {"H2C_REQ_THROT_PCIE_EN_DATA",
- H2C_REQ_THROT_PCIE_EN_DATA_MASK},
- {"H2C_REQ_THROT_PCIE_DATA_THRESH",
- H2C_REQ_THROT_PCIE_DATA_THRESH_MASK},
+ c2h_stat_total_wpl_len_field_info[] = {
+ {"C2H_STAT_TOTAL_WPL_LEN",
+ C2H_STAT_TOTAL_WPL_LEN_MASK},
};
static struct regfield_info
- h2c_aln_dbg_reg0_field_info[] = {
- {"H2C_ALN_REG0_NUM_PKT_SENT",
- H2C_ALN_REG0_NUM_PKT_SENT_MASK},
+ c2h_buf_sz_field_info[] = {
+ {"C2H_BUF_SZ_IZE",
+ C2H_BUF_SZ_IZE_MASK},
};
static struct regfield_info
- h2c_req_throt_aximm_field_info[] = {
- {"H2C_REQ_THROT_AXIMM_EN_REQ",
- H2C_REQ_THROT_AXIMM_EN_REQ_MASK},
- {"H2C_REQ_THROT_AXIMM",
- H2C_REQ_THROT_AXIMM_MASK},
- {"H2C_REQ_THROT_AXIMM_EN_DATA",
- H2C_REQ_THROT_AXIMM_EN_DATA_MASK},
- {"H2C_REQ_THROT_AXIMM_DATA_THRESH",
- H2C_REQ_THROT_AXIMM_DATA_THRESH_MASK},
+ c2h_err_stat_field_info[] = {
+ {"C2H_ERR_STAT_RSVD_1",
+ C2H_ERR_STAT_RSVD_1_MASK},
+ {"C2H_ERR_STAT_WRB_PORT_ID_ERR",
+ C2H_ERR_STAT_WRB_PORT_ID_ERR_MASK},
+ {"C2H_ERR_STAT_HDR_PAR_ERR",
+ C2H_ERR_STAT_HDR_PAR_ERR_MASK},
+ {"C2H_ERR_STAT_HDR_ECC_COR_ERR",
+ C2H_ERR_STAT_HDR_ECC_COR_ERR_MASK},
+ {"C2H_ERR_STAT_HDR_ECC_UNC_ERR",
+ C2H_ERR_STAT_HDR_ECC_UNC_ERR_MASK},
+ {"C2H_ERR_STAT_AVL_RING_DSC_ERR",
+ C2H_ERR_STAT_AVL_RING_DSC_ERR_MASK},
+ {"C2H_ERR_STAT_WRB_PRTY_ERR",
+ C2H_ERR_STAT_WRB_PRTY_ERR_MASK},
+ {"C2H_ERR_STAT_WRB_CIDX_ERR",
+ C2H_ERR_STAT_WRB_CIDX_ERR_MASK},
+ {"C2H_ERR_STAT_WRB_QFULL_ERR",
+ C2H_ERR_STAT_WRB_QFULL_ERR_MASK},
+ {"C2H_ERR_STAT_WRB_INV_Q_ERR",
+ C2H_ERR_STAT_WRB_INV_Q_ERR_MASK},
+ {"C2H_ERR_STAT_RSVD_2",
+ C2H_ERR_STAT_RSVD_2_MASK},
+ {"C2H_ERR_STAT_PORT_ID_CTXT_MISMATCH",
+ C2H_ERR_STAT_PORT_ID_CTXT_MISMATCH_MASK},
+ {"C2H_ERR_STAT_ERR_DESC_CNT",
+ C2H_ERR_STAT_ERR_DESC_CNT_MASK},
+ {"C2H_ERR_STAT_RSVD_3",
+ C2H_ERR_STAT_RSVD_3_MASK},
+ {"C2H_ERR_STAT_MSI_INT_FAIL",
+ C2H_ERR_STAT_MSI_INT_FAIL_MASK},
+ {"C2H_ERR_STAT_ENG_WPL_DATA_PAR_ERR",
+ C2H_ERR_STAT_ENG_WPL_DATA_PAR_ERR_MASK},
+ {"C2H_ERR_STAT_RSVD_4",
+ C2H_ERR_STAT_RSVD_4_MASK},
+ {"C2H_ERR_STAT_DESC_RSP_ERR",
+ C2H_ERR_STAT_DESC_RSP_ERR_MASK},
+ {"C2H_ERR_STAT_QID_MISMATCH",
+ C2H_ERR_STAT_QID_MISMATCH_MASK},
+ {"C2H_ERR_STAT_SH_CMPT_DSC_ERR",
+ C2H_ERR_STAT_SH_CMPT_DSC_ERR_MASK},
+ {"C2H_ERR_STAT_LEN_MISMATCH",
+ C2H_ERR_STAT_LEN_MISMATCH_MASK},
+ {"C2H_ERR_STAT_MTY_MISMATCH",
+ C2H_ERR_STAT_MTY_MISMATCH_MASK},
};
static struct regfield_info
- c2h_mm_ctl_field_info[] = {
- {"C2H_MM_CTL_RESERVED1",
- C2H_MM_CTL_RESERVED1_MASK},
- {"C2H_MM_CTL_ERRC_EN",
- C2H_MM_CTL_ERRC_EN_MASK},
- {"C2H_MM_CTL_RESERVED0",
- C2H_MM_CTL_RESERVED0_MASK},
- {"C2H_MM_CTL_RUN",
- C2H_MM_CTL_RUN_MASK},
+ c2h_err_mask_field_info[] = {
+ {"C2H_ERR_EN",
+ C2H_ERR_EN_MASK},
};
static struct regfield_info
- c2h_mm_status_field_info[] = {
- {"C2H_MM_STATUS_RSVD_1",
- C2H_MM_STATUS_RSVD_1_MASK},
- {"C2H_MM_STATUS_RUN",
- C2H_MM_STATUS_RUN_MASK},
+ c2h_fatal_err_stat_field_info[] = {
+ {"C2H_FATAL_ERR_STAT_RSVD_1",
+ C2H_FATAL_ERR_STAT_RSVD_1_MASK},
+ {"C2H_FATAL_ERR_STAT_HDR_ECC_UNC_ERR",
+ C2H_FATAL_ERR_STAT_HDR_ECC_UNC_ERR_MASK},
+ {"C2H_FATAL_ERR_STAT_AVL_RING_FIFO_RAM_RDBE",
+ C2H_FATAL_ERR_STAT_AVL_RING_FIFO_RAM_RDBE_MASK},
+ {"C2H_FATAL_ERR_STAT_WPL_DATA_PAR_ERR",
+ C2H_FATAL_ERR_STAT_WPL_DATA_PAR_ERR_MASK},
+ {"C2H_FATAL_ERR_STAT_PLD_FIFO_RAM_RDBE",
+ C2H_FATAL_ERR_STAT_PLD_FIFO_RAM_RDBE_MASK},
+ {"C2H_FATAL_ERR_STAT_QID_FIFO_RAM_RDBE",
+ C2H_FATAL_ERR_STAT_QID_FIFO_RAM_RDBE_MASK},
+ {"C2H_FATAL_ERR_STAT_CMPT_FIFO_RAM_RDBE",
+ C2H_FATAL_ERR_STAT_CMPT_FIFO_RAM_RDBE_MASK},
+ {"C2H_FATAL_ERR_STAT_WRB_COAL_DATA_RAM_RDBE",
+ C2H_FATAL_ERR_STAT_WRB_COAL_DATA_RAM_RDBE_MASK},
+ {"C2H_FATAL_ERR_STAT_RESERVED2",
+ C2H_FATAL_ERR_STAT_RESERVED2_MASK},
+ {"C2H_FATAL_ERR_STAT_INT_CTXT_RAM_RDBE",
+ C2H_FATAL_ERR_STAT_INT_CTXT_RAM_RDBE_MASK},
+ {"C2H_FATAL_ERR_STAT_DESC_REQ_FIFO_RAM_RDBE",
+ C2H_FATAL_ERR_STAT_DESC_REQ_FIFO_RAM_RDBE_MASK},
+ {"C2H_FATAL_ERR_STAT_PFCH_CTXT_RAM_RDBE",
+ C2H_FATAL_ERR_STAT_PFCH_CTXT_RAM_RDBE_MASK},
+ {"C2H_FATAL_ERR_STAT_WRB_CTXT_RAM_RDBE",
+ C2H_FATAL_ERR_STAT_WRB_CTXT_RAM_RDBE_MASK},
+ {"C2H_FATAL_ERR_STAT_PFCH_LL_RAM_RDBE",
+ C2H_FATAL_ERR_STAT_PFCH_LL_RAM_RDBE_MASK},
+ {"C2H_FATAL_ERR_STAT_TIMER_FIFO_RAM_RDBE",
+ C2H_FATAL_ERR_STAT_TIMER_FIFO_RAM_RDBE_MASK},
+ {"C2H_FATAL_ERR_STAT_QID_MISMATCH",
+ C2H_FATAL_ERR_STAT_QID_MISMATCH_MASK},
+ {"C2H_FATAL_ERR_STAT_RESERVED1",
+ C2H_FATAL_ERR_STAT_RESERVED1_MASK},
+ {"C2H_FATAL_ERR_STAT_LEN_MISMATCH",
+ C2H_FATAL_ERR_STAT_LEN_MISMATCH_MASK},
+ {"C2H_FATAL_ERR_STAT_MTY_MISMATCH",
+ C2H_FATAL_ERR_STAT_MTY_MISMATCH_MASK},
};
static struct regfield_info
- c2h_mm_cmpl_desc_cnt_field_info[] = {
- {"C2H_MM_CMPL_DESC_CNT_C2H_CO",
- C2H_MM_CMPL_DESC_CNT_C2H_CO_MASK},
+ c2h_fatal_err_mask_field_info[] = {
+ {"C2H_FATAL_ERR_C2HEN",
+ C2H_FATAL_ERR_C2HEN_MASK},
};
static struct regfield_info
- c2h_mm_err_code_enable_mask_field_info[] = {
- {"C2H_MM_ERR_CODE_ENABLE_RESERVED1",
- C2H_MM_ERR_CODE_ENABLE_RESERVED1_MASK},
- {"C2H_MM_ERR_CODE_ENABLE_WR_UC_RAM",
- C2H_MM_ERR_CODE_ENABLE_WR_UC_RAM_MASK},
- {"C2H_MM_ERR_CODE_ENABLE_WR_UR",
- C2H_MM_ERR_CODE_ENABLE_WR_UR_MASK},
- {"C2H_MM_ERR_CODE_ENABLE_WR_FLR",
- C2H_MM_ERR_CODE_ENABLE_WR_FLR_MASK},
- {"C2H_MM_ERR_CODE_ENABLE_RESERVED0",
- C2H_MM_ERR_CODE_ENABLE_RESERVED0_MASK},
- {"C2H_MM_ERR_CODE_ENABLE_RD_SLV_ERR",
- C2H_MM_ERR_CODE_ENABLE_RD_SLV_ERR_MASK},
- {"C2H_MM_ERR_CODE_ENABLE_WR_SLV_ERR",
- C2H_MM_ERR_CODE_ENABLE_WR_SLV_ERR_MASK},
+ c2h_fatal_err_enable_field_info[] = {
+ {"C2H_FATAL_ERR_ENABLE_RSVD_1",
+ C2H_FATAL_ERR_ENABLE_RSVD_1_MASK},
+ {"C2H_FATAL_ERR_ENABLE_WPL_PAR_INV",
+ C2H_FATAL_ERR_ENABLE_WPL_PAR_INV_MASK},
+ {"C2H_FATAL_ERR_ENABLE_WRQ_DIS",
+ C2H_FATAL_ERR_ENABLE_WRQ_DIS_MASK},
};
static struct regfield_info
- c2h_mm_err_code_field_info[] = {
- {"C2H_MM_ERR_CODE_RESERVED1",
- C2H_MM_ERR_CODE_RESERVED1_MASK},
- {"C2H_MM_ERR_CODE_CIDX",
- C2H_MM_ERR_CODE_CIDX_MASK},
- {"C2H_MM_ERR_CODE_RESERVED0",
- C2H_MM_ERR_CODE_RESERVED0_MASK},
- {"C2H_MM_ERR_CODE_SUB_TYPE",
- C2H_MM_ERR_CODE_SUB_TYPE_MASK},
- {"C2H_MM_ERR_CODE",
- C2H_MM_ERR_CODE_MASK},
+ glbl_err_int_field_info[] = {
+ {"GLBL_ERR_INT_RSVD_1",
+ GLBL_ERR_INT_RSVD_1_MASK},
+ {"GLBL_ERR_INT_HOST_ID",
+ GLBL_ERR_INT_HOST_ID_MASK},
+ {"GLBL_ERR_INT_DIS_INTR_ON_VF",
+ GLBL_ERR_INT_DIS_INTR_ON_VF_MASK},
+ {"GLBL_ERR_INT_ARM",
+ GLBL_ERR_INT_ARM_MASK},
+ {"GLBL_ERR_INT_EN_COAL",
+ GLBL_ERR_INT_EN_COAL_MASK},
+ {"GLBL_ERR_INT_VEC",
+ GLBL_ERR_INT_VEC_MASK},
+ {"GLBL_ERR_INT_FUNC",
+ GLBL_ERR_INT_FUNC_MASK},
};
static struct regfield_info
- c2h_mm_err_info_field_info[] = {
- {"C2H_MM_ERR_INFO_VALID",
- C2H_MM_ERR_INFO_VALID_MASK},
- {"C2H_MM_ERR_INFO_SEL",
- C2H_MM_ERR_INFO_SEL_MASK},
- {"C2H_MM_ERR_INFO_RSVD_1",
- C2H_MM_ERR_INFO_RSVD_1_MASK},
- {"C2H_MM_ERR_INFO_QID",
- C2H_MM_ERR_INFO_QID_MASK},
+ c2h_pfch_cfg_field_info[] = {
+ {"C2H_PFCH_CFG_EVTFL_TH",
+ C2H_PFCH_CFG_EVTFL_TH_MASK},
+ {"C2H_PFCH_CFG_FL_TH",
+ C2H_PFCH_CFG_FL_TH_MASK},
};
static struct regfield_info
- c2h_mm_perf_mon_ctl_field_info[] = {
- {"C2H_MM_PERF_MON_CTL_RSVD_1",
- C2H_MM_PERF_MON_CTL_RSVD_1_MASK},
- {"C2H_MM_PERF_MON_CTL_IMM_START",
- C2H_MM_PERF_MON_CTL_IMM_START_MASK},
- {"C2H_MM_PERF_MON_CTL_RUN_START",
- C2H_MM_PERF_MON_CTL_RUN_START_MASK},
- {"C2H_MM_PERF_MON_CTL_IMM_CLEAR",
- C2H_MM_PERF_MON_CTL_IMM_CLEAR_MASK},
- {"C2H_MM_PERF_MON_CTL_RUN_CLEAR",
- C2H_MM_PERF_MON_CTL_RUN_CLEAR_MASK},
+ c2h_int_timer_tick_field_info[] = {
+ {"C2H_INT_TIMER_TICK",
+ C2H_INT_TIMER_TICK_MASK},
};
static struct regfield_info
- c2h_mm_perf_mon_cycle_cnt0_field_info[] = {
- {"C2H_MM_PERF_MON_CYCLE_CNT0_CYC_CNT",
- C2H_MM_PERF_MON_CYCLE_CNT0_CYC_CNT_MASK},
+ c2h_stat_desc_rsp_drop_accepted_field_info[] = {
+ {"C2H_STAT_DESC_RSP_DROP_ACCEPTED_D",
+ C2H_STAT_DESC_RSP_DROP_ACCEPTED_D_MASK},
};
static struct regfield_info
- c2h_mm_perf_mon_cycle_cnt1_field_info[] = {
- {"C2H_MM_PERF_MON_CYCLE_CNT1_RSVD_1",
- C2H_MM_PERF_MON_CYCLE_CNT1_RSVD_1_MASK},
- {"C2H_MM_PERF_MON_CYCLE_CNT1_CYC_CNT",
- C2H_MM_PERF_MON_CYCLE_CNT1_CYC_CNT_MASK},
+ c2h_stat_desc_rsp_err_accepted_field_info[] = {
+ {"C2H_STAT_DESC_RSP_ERR_ACCEPTED_D",
+ C2H_STAT_DESC_RSP_ERR_ACCEPTED_D_MASK},
};
static struct regfield_info
- c2h_mm_perf_mon_data_cnt0_field_info[] = {
- {"C2H_MM_PERF_MON_DATA_CNT0_DCNT",
- C2H_MM_PERF_MON_DATA_CNT0_DCNT_MASK},
+ c2h_stat_desc_req_field_info[] = {
+ {"C2H_STAT_DESC_REQ",
+ C2H_STAT_DESC_REQ_MASK},
};
static struct regfield_info
- c2h_mm_perf_mon_data_cnt1_field_info[] = {
- {"C2H_MM_PERF_MON_DATA_CNT1_RSVD_1",
- C2H_MM_PERF_MON_DATA_CNT1_RSVD_1_MASK},
- {"C2H_MM_PERF_MON_DATA_CNT1_DCNT",
- C2H_MM_PERF_MON_DATA_CNT1_DCNT_MASK},
+ c2h_stat_dbg_dma_eng_0_field_info[] = {
+ {"C2H_STAT_DMA_ENG_0_S_AXIS_C2H_TVALID",
+ C2H_STAT_DMA_ENG_0_S_AXIS_C2H_TVALID_MASK},
+ {"C2H_STAT_DMA_ENG_0_S_AXIS_C2H_TREADY",
+ C2H_STAT_DMA_ENG_0_S_AXIS_C2H_TREADY_MASK},
+ {"C2H_STAT_DMA_ENG_0_S_AXIS_WRB_TVALID",
+ C2H_STAT_DMA_ENG_0_S_AXIS_WRB_TVALID_MASK},
+ {"C2H_STAT_DMA_ENG_0_S_AXIS_WRB_TREADY",
+ C2H_STAT_DMA_ENG_0_S_AXIS_WRB_TREADY_MASK},
+ {"C2H_STAT_DMA_ENG_0_PLD_FIFO_IN_RDY",
+ C2H_STAT_DMA_ENG_0_PLD_FIFO_IN_RDY_MASK},
+ {"C2H_STAT_DMA_ENG_0_QID_FIFO_IN_RDY",
+ C2H_STAT_DMA_ENG_0_QID_FIFO_IN_RDY_MASK},
+ {"C2H_STAT_DMA_ENG_0_ARB_FIFO_OUT_VLD",
+ C2H_STAT_DMA_ENG_0_ARB_FIFO_OUT_VLD_MASK},
+ {"C2H_STAT_DMA_ENG_0_ARB_FIFO_OUT_QID",
+ C2H_STAT_DMA_ENG_0_ARB_FIFO_OUT_QID_MASK},
+ {"C2H_STAT_DMA_ENG_0_WRB_FIFO_IN_RDY",
+ C2H_STAT_DMA_ENG_0_WRB_FIFO_IN_RDY_MASK},
+ {"C2H_STAT_DMA_ENG_0_WRB_FIFO_OUT_CNT",
+ C2H_STAT_DMA_ENG_0_WRB_FIFO_OUT_CNT_MASK},
+ {"C2H_STAT_DMA_ENG_0_WRB_SM_CS",
+ C2H_STAT_DMA_ENG_0_WRB_SM_CS_MASK},
+ {"C2H_STAT_DMA_ENG_0_MAIN_SM_CS",
+ C2H_STAT_DMA_ENG_0_MAIN_SM_CS_MASK},
};
static struct regfield_info
- c2h_mm_dbg_field_info[] = {
- {"C2H_MM_RSVD_1",
- C2H_MM_RSVD_1_MASK},
- {"C2H_MM_RRQ_ENTRIES",
- C2H_MM_RRQ_ENTRIES_MASK},
- {"C2H_MM_DAT_FIFO_SPC",
- C2H_MM_DAT_FIFO_SPC_MASK},
- {"C2H_MM_RD_STALL",
- C2H_MM_RD_STALL_MASK},
- {"C2H_MM_RRQ_FIFO_FI",
- C2H_MM_RRQ_FIFO_FI_MASK},
- {"C2H_MM_WR_STALL",
- C2H_MM_WR_STALL_MASK},
- {"C2H_MM_WRQ_FIFO_FI",
- C2H_MM_WRQ_FIFO_FI_MASK},
- {"C2H_MM_WBK_STALL",
- C2H_MM_WBK_STALL_MASK},
- {"C2H_MM_DSC_FIFO_EP",
- C2H_MM_DSC_FIFO_EP_MASK},
- {"C2H_MM_DSC_FIFO_FL",
- C2H_MM_DSC_FIFO_FL_MASK},
+ c2h_stat_dbg_dma_eng_1_field_info[] = {
+ {"C2H_STAT_DMA_ENG_1_WRB_USER_0_CMPT_TYPE",
+ C2H_STAT_DMA_ENG_1_WRB_USER_0_CMPT_TYPE_MASK},
+ {"C2H_STAT_DMA_ENG_1_DESC_RSP_FIFO_OUT_VLD",
+ C2H_STAT_DMA_ENG_1_DESC_RSP_FIFO_OUT_VLD_MASK},
+ {"C2H_STAT_DMA_ENG_1_QID_FIFO_OUT_CNT",
+ C2H_STAT_DMA_ENG_1_QID_FIFO_OUT_CNT_MASK},
+ {"C2H_STAT_DMA_ENG_1_PLD_FIFO_OUT_CNT",
+ C2H_STAT_DMA_ENG_1_PLD_FIFO_OUT_CNT_MASK},
+ {"C2H_STAT_DMA_ENG_1_PLD_ST_FIFO_CNT",
+ C2H_STAT_DMA_ENG_1_PLD_ST_FIFO_CNT_MASK},
};
static struct regfield_info
- h2c_mm_ctl_field_info[] = {
- {"H2C_MM_CTL_RESERVED1",
- H2C_MM_CTL_RESERVED1_MASK},
- {"H2C_MM_CTL_ERRC_EN",
- H2C_MM_CTL_ERRC_EN_MASK},
- {"H2C_MM_CTL_RESERVED0",
- H2C_MM_CTL_RESERVED0_MASK},
- {"H2C_MM_CTL_RUN",
- H2C_MM_CTL_RUN_MASK},
+ c2h_stat_dbg_dma_eng_2_field_info[] = {
+ {"C2H_STAT_DMA_ENG_2_WRB_USER_1_CMPT_TYPE",
+ C2H_STAT_DMA_ENG_2_WRB_USER_1_CMPT_TYPE_MASK},
+ {"C2H_STAT_DMA_ENG_2_DESC_RSP_FIFO_OUT_VLD_1",
+ C2H_STAT_DMA_ENG_2_DESC_RSP_FIFO_OUT_VLD_1_MASK},
+ {"C2H_STAT_DMA_ENG_2_QID_FIFO_OUT_CNT_1",
+ C2H_STAT_DMA_ENG_2_QID_FIFO_OUT_CNT_1_MASK},
+ {"C2H_STAT_DMA_ENG_2_PLD_FIFO_OUT_CNT_1",
+ C2H_STAT_DMA_ENG_2_PLD_FIFO_OUT_CNT_1_MASK},
+ {"C2H_STAT_DMA_ENG_2_PLD_ST_FIFO_CNT_1",
+ C2H_STAT_DMA_ENG_2_PLD_ST_FIFO_CNT_1_MASK},
};
static struct regfield_info
- h2c_mm_status_field_info[] = {
- {"H2C_MM_STATUS_RSVD_1",
- H2C_MM_STATUS_RSVD_1_MASK},
- {"H2C_MM_STATUS_RUN",
- H2C_MM_STATUS_RUN_MASK},
+ c2h_stat_dbg_dma_eng_3_field_info[] = {
+ {"C2H_STAT_DMA_ENG_3_QID_FIFO_OUT_DAT_HAS_CMPT",
+ C2H_STAT_DMA_ENG_3_QID_FIFO_OUT_DAT_HAS_CMPT_MASK},
+ {"C2H_STAT_DMA_ENG_3_QID_FIFO_OUT_DAT_MARKER",
+ C2H_STAT_DMA_ENG_3_QID_FIFO_OUT_DAT_MARKER_MASK},
+ {"C2H_STAT_DMA_ENG_3_QID_FIFO_OUT_DAT_DROP_REQ",
+ C2H_STAT_DMA_ENG_3_QID_FIFO_OUT_DAT_DROP_REQ_MASK},
+ {"C2H_STAT_DMA_ENG_3_QID_FIFO_OUT_DAT_QID",
+ C2H_STAT_DMA_ENG_3_QID_FIFO_OUT_DAT_QID_MASK},
+ {"C2H_STAT_DMA_ENG_3_WR_HDR_FIFO_OUT_CNT",
+ C2H_STAT_DMA_ENG_3_WR_HDR_FIFO_OUT_CNT_MASK},
+ {"C2H_STAT_DMA_ENG_3_QID_FIFO_OUT_VLD",
+ C2H_STAT_DMA_ENG_3_QID_FIFO_OUT_VLD_MASK},
+ {"C2H_STAT_DMA_ENG_3_PLD_FIFO_OUT_VLD",
+ C2H_STAT_DMA_ENG_3_PLD_FIFO_OUT_VLD_MASK},
+ {"C2H_STAT_DMA_ENG_3_PLD_ST_FIFO_OUT_VLD",
+ C2H_STAT_DMA_ENG_3_PLD_ST_FIFO_OUT_VLD_MASK},
+ {"C2H_STAT_DMA_ENG_3_PLD_ST_FIFO_OUT_DATA_EOP",
+ C2H_STAT_DMA_ENG_3_PLD_ST_FIFO_OUT_DATA_EOP_MASK},
+ {"C2H_STAT_DMA_ENG_3_PLD_ST_FIFO_OUT_DATA_AVL_IDX_ENABLE",
+ C2H_STAT_DMA_ENG_3_PLD_ST_FIFO_OUT_DATA_AVL_IDX_ENABLE_MASK},
+ {"C2H_STAT_DMA_ENG_3_PLD_ST_FIFO_OUT_DATA_DROP",
+ C2H_STAT_DMA_ENG_3_PLD_ST_FIFO_OUT_DATA_DROP_MASK},
+ {"C2H_STAT_DMA_ENG_3_PLD_ST_FIFO_OUT_DATA_ERR",
+ C2H_STAT_DMA_ENG_3_PLD_ST_FIFO_OUT_DATA_ERR_MASK},
+ {"C2H_STAT_DMA_ENG_3_DESC_CNT_FIFO_IN_RDY",
+ C2H_STAT_DMA_ENG_3_DESC_CNT_FIFO_IN_RDY_MASK},
+ {"C2H_STAT_DMA_ENG_3_DESC_RSP_FIFO_IN_RDY",
+ C2H_STAT_DMA_ENG_3_DESC_RSP_FIFO_IN_RDY_MASK},
+ {"C2H_STAT_DMA_ENG_3_PLD_PKT_ID_LARGER",
+ C2H_STAT_DMA_ENG_3_PLD_PKT_ID_LARGER_MASK},
+ {"C2H_STAT_DMA_ENG_3_WCP_FIFO_IN_RDY",
+ C2H_STAT_DMA_ENG_3_WCP_FIFO_IN_RDY_MASK},
+ {"C2H_STAT_DMA_ENG_3_PLD_ST_FIFO_IN_RDY",
+ C2H_STAT_DMA_ENG_3_PLD_ST_FIFO_IN_RDY_MASK},
};
static struct regfield_info
- h2c_mm_cmpl_desc_cnt_field_info[] = {
- {"H2C_MM_CMPL_DESC_CNT_H2C_CO",
- H2C_MM_CMPL_DESC_CNT_H2C_CO_MASK},
+ c2h_dbg_pfch_err_ctxt_field_info[] = {
+ {"C2H_PFCH_ERR_CTXT_RSVD_1",
+ C2H_PFCH_ERR_CTXT_RSVD_1_MASK},
+ {"C2H_PFCH_ERR_CTXT_ERR_STAT",
+ C2H_PFCH_ERR_CTXT_ERR_STAT_MASK},
+ {"C2H_PFCH_ERR_CTXT_CMD_WR",
+ C2H_PFCH_ERR_CTXT_CMD_WR_MASK},
+ {"C2H_PFCH_ERR_CTXT_QID",
+ C2H_PFCH_ERR_CTXT_QID_MASK},
+ {"C2H_PFCH_ERR_CTXT_DONE",
+ C2H_PFCH_ERR_CTXT_DONE_MASK},
};
static struct regfield_info
- h2c_mm_err_code_enable_mask_field_info[] = {
- {"H2C_MM_ERR_CODE_ENABLE_RESERVED5",
- H2C_MM_ERR_CODE_ENABLE_RESERVED5_MASK},
- {"H2C_MM_ERR_CODE_ENABLE_WR_SLV_ERR",
- H2C_MM_ERR_CODE_ENABLE_WR_SLV_ERR_MASK},
- {"H2C_MM_ERR_CODE_ENABLE_WR_DEC_ERR",
- H2C_MM_ERR_CODE_ENABLE_WR_DEC_ERR_MASK},
- {"H2C_MM_ERR_CODE_ENABLE_RESERVED4",
- H2C_MM_ERR_CODE_ENABLE_RESERVED4_MASK},
- {"H2C_MM_ERR_CODE_ENABLE_RD_RQ_DIS_ERR",
- H2C_MM_ERR_CODE_ENABLE_RD_RQ_DIS_ERR_MASK},
- {"H2C_MM_ERR_CODE_ENABLE_RESERVED3",
- H2C_MM_ERR_CODE_ENABLE_RESERVED3_MASK},
- {"H2C_MM_ERR_CODE_ENABLE_RD_DAT_POISON_ERR",
- H2C_MM_ERR_CODE_ENABLE_RD_DAT_POISON_ERR_MASK},
- {"H2C_MM_ERR_CODE_ENABLE_RESERVED2",
- H2C_MM_ERR_CODE_ENABLE_RESERVED2_MASK},
- {"H2C_MM_ERR_CODE_ENABLE_RD_FLR_ERR",
- H2C_MM_ERR_CODE_ENABLE_RD_FLR_ERR_MASK},
- {"H2C_MM_ERR_CODE_ENABLE_RESERVED1",
- H2C_MM_ERR_CODE_ENABLE_RESERVED1_MASK},
- {"H2C_MM_ERR_CODE_ENABLE_RD_HDR_ADR_ERR",
- H2C_MM_ERR_CODE_ENABLE_RD_HDR_ADR_ERR_MASK},
- {"H2C_MM_ERR_CODE_ENABLE_RD_HDR_PARA",
- H2C_MM_ERR_CODE_ENABLE_RD_HDR_PARA_MASK},
- {"H2C_MM_ERR_CODE_ENABLE_RD_HDR_BYTE_ERR",
- H2C_MM_ERR_CODE_ENABLE_RD_HDR_BYTE_ERR_MASK},
- {"H2C_MM_ERR_CODE_ENABLE_RD_UR_CA",
- H2C_MM_ERR_CODE_ENABLE_RD_UR_CA_MASK},
- {"H2C_MM_ERR_CODE_ENABLE_RD_HRD_POISON_ERR",
- H2C_MM_ERR_CODE_ENABLE_RD_HRD_POISON_ERR_MASK},
- {"H2C_MM_ERR_CODE_ENABLE_RESERVED0",
- H2C_MM_ERR_CODE_ENABLE_RESERVED0_MASK},
+ c2h_first_err_qid_field_info[] = {
+ {"C2H_FIRST_ERR_QID_RSVD_1",
+ C2H_FIRST_ERR_QID_RSVD_1_MASK},
+ {"C2H_FIRST_ERR_QID_ERR_TYPE",
+ C2H_FIRST_ERR_QID_ERR_TYPE_MASK},
+ {"C2H_FIRST_ERR_QID_RSVD",
+ C2H_FIRST_ERR_QID_RSVD_MASK},
+ {"C2H_FIRST_ERR_QID_QID",
+ C2H_FIRST_ERR_QID_QID_MASK},
};
static struct regfield_info
- h2c_mm_err_code_field_info[] = {
- {"H2C_MM_ERR_CODE_RSVD_1",
- H2C_MM_ERR_CODE_RSVD_1_MASK},
- {"H2C_MM_ERR_CODE_CIDX",
- H2C_MM_ERR_CODE_CIDX_MASK},
- {"H2C_MM_ERR_CODE_RESERVED0",
- H2C_MM_ERR_CODE_RESERVED0_MASK},
- {"H2C_MM_ERR_CODE_SUB_TYPE",
- H2C_MM_ERR_CODE_SUB_TYPE_MASK},
- {"H2C_MM_ERR_CODE",
- H2C_MM_ERR_CODE_MASK},
+ stat_num_wrb_in_field_info[] = {
+ {"STAT_NUM_WRB_IN_RSVD_1",
+ STAT_NUM_WRB_IN_RSVD_1_MASK},
+ {"STAT_NUM_WRB_IN_WRB_CNT",
+ STAT_NUM_WRB_IN_WRB_CNT_MASK},
};
static struct regfield_info
- h2c_mm_err_info_field_info[] = {
- {"H2C_MM_ERR_INFO_VALID",
- H2C_MM_ERR_INFO_VALID_MASK},
- {"H2C_MM_ERR_INFO_SEL",
- H2C_MM_ERR_INFO_SEL_MASK},
- {"H2C_MM_ERR_INFO_RSVD_1",
- H2C_MM_ERR_INFO_RSVD_1_MASK},
- {"H2C_MM_ERR_INFO_QID",
- H2C_MM_ERR_INFO_QID_MASK},
+ stat_num_wrb_out_field_info[] = {
+ {"STAT_NUM_WRB_OUT_RSVD_1",
+ STAT_NUM_WRB_OUT_RSVD_1_MASK},
+ {"STAT_NUM_WRB_OUT_WRB_CNT",
+ STAT_NUM_WRB_OUT_WRB_CNT_MASK},
};
static struct regfield_info
- h2c_mm_perf_mon_ctl_field_info[] = {
- {"H2C_MM_PERF_MON_CTL_RSVD_1",
- H2C_MM_PERF_MON_CTL_RSVD_1_MASK},
- {"H2C_MM_PERF_MON_CTL_IMM_START",
- H2C_MM_PERF_MON_CTL_IMM_START_MASK},
- {"H2C_MM_PERF_MON_CTL_RUN_START",
- H2C_MM_PERF_MON_CTL_RUN_START_MASK},
- {"H2C_MM_PERF_MON_CTL_IMM_CLEAR",
- H2C_MM_PERF_MON_CTL_IMM_CLEAR_MASK},
- {"H2C_MM_PERF_MON_CTL_RUN_CLEAR",
- H2C_MM_PERF_MON_CTL_RUN_CLEAR_MASK},
+ stat_num_wrb_drp_field_info[] = {
+ {"STAT_NUM_WRB_DRP_RSVD_1",
+ STAT_NUM_WRB_DRP_RSVD_1_MASK},
+ {"STAT_NUM_WRB_DRP_WRB_CNT",
+ STAT_NUM_WRB_DRP_WRB_CNT_MASK},
};
static struct regfield_info
- h2c_mm_perf_mon_cycle_cnt0_field_info[] = {
- {"H2C_MM_PERF_MON_CYCLE_CNT0_CYC_CNT",
- H2C_MM_PERF_MON_CYCLE_CNT0_CYC_CNT_MASK},
+ stat_num_stat_desc_out_field_info[] = {
+ {"STAT_NUM_STAT_DESC_OUT_RSVD_1",
+ STAT_NUM_STAT_DESC_OUT_RSVD_1_MASK},
+ {"STAT_NUM_STAT_DESC_OUT_CNT",
+ STAT_NUM_STAT_DESC_OUT_CNT_MASK},
};
static struct regfield_info
- h2c_mm_perf_mon_cycle_cnt1_field_info[] = {
- {"H2C_MM_PERF_MON_CYCLE_CNT1_RSVD_1",
- H2C_MM_PERF_MON_CYCLE_CNT1_RSVD_1_MASK},
- {"H2C_MM_PERF_MON_CYCLE_CNT1_CYC_CNT",
- H2C_MM_PERF_MON_CYCLE_CNT1_CYC_CNT_MASK},
+ stat_num_dsc_crdt_sent_field_info[] = {
+ {"STAT_NUM_DSC_CRDT_SENT_RSVD_1",
+ STAT_NUM_DSC_CRDT_SENT_RSVD_1_MASK},
+ {"STAT_NUM_DSC_CRDT_SENT_CNT",
+ STAT_NUM_DSC_CRDT_SENT_CNT_MASK},
};
static struct regfield_info
- h2c_mm_perf_mon_data_cnt0_field_info[] = {
- {"H2C_MM_PERF_MON_DATA_CNT0_DCNT",
- H2C_MM_PERF_MON_DATA_CNT0_DCNT_MASK},
+ stat_num_fch_dsc_rcvd_field_info[] = {
+ {"STAT_NUM_FCH_DSC_RCVD_RSVD_1",
+ STAT_NUM_FCH_DSC_RCVD_RSVD_1_MASK},
+ {"STAT_NUM_FCH_DSC_RCVD_DSC_CNT",
+ STAT_NUM_FCH_DSC_RCVD_DSC_CNT_MASK},
};
static struct regfield_info
- h2c_mm_perf_mon_data_cnt1_field_info[] = {
- {"H2C_MM_PERF_MON_DATA_CNT1_RSVD_1",
- H2C_MM_PERF_MON_DATA_CNT1_RSVD_1_MASK},
- {"H2C_MM_PERF_MON_DATA_CNT1_DCNT",
- H2C_MM_PERF_MON_DATA_CNT1_DCNT_MASK},
+ stat_num_byp_dsc_rcvd_field_info[] = {
+ {"STAT_NUM_BYP_DSC_RCVD_RSVD_1",
+ STAT_NUM_BYP_DSC_RCVD_RSVD_1_MASK},
+ {"STAT_NUM_BYP_DSC_RCVD_DSC_CNT",
+ STAT_NUM_BYP_DSC_RCVD_DSC_CNT_MASK},
};
static struct regfield_info
- h2c_mm_dbg_field_info[] = {
- {"H2C_MM_RSVD_1",
- H2C_MM_RSVD_1_MASK},
- {"H2C_MM_RRQ_ENTRIES",
- H2C_MM_RRQ_ENTRIES_MASK},
- {"H2C_MM_DAT_FIFO_SPC",
- H2C_MM_DAT_FIFO_SPC_MASK},
- {"H2C_MM_RD_STALL",
- H2C_MM_RD_STALL_MASK},
- {"H2C_MM_RRQ_FIFO_FI",
- H2C_MM_RRQ_FIFO_FI_MASK},
- {"H2C_MM_WR_STALL",
- H2C_MM_WR_STALL_MASK},
- {"H2C_MM_WRQ_FIFO_FI",
- H2C_MM_WRQ_FIFO_FI_MASK},
- {"H2C_MM_WBK_STALL",
- H2C_MM_WBK_STALL_MASK},
- {"H2C_MM_DSC_FIFO_EP",
- H2C_MM_DSC_FIFO_EP_MASK},
- {"H2C_MM_DSC_FIFO_FL",
- H2C_MM_DSC_FIFO_FL_MASK},
+ c2h_wrb_coal_cfg_field_info[] = {
+ {"C2H_WRB_COAL_CFG_MAX_BUF_SZ",
+ C2H_WRB_COAL_CFG_MAX_BUF_SZ_MASK},
+ {"C2H_WRB_COAL_CFG_TICK_VAL",
+ C2H_WRB_COAL_CFG_TICK_VAL_MASK},
+ {"C2H_WRB_COAL_CFG_TICK_CNT",
+ C2H_WRB_COAL_CFG_TICK_CNT_MASK},
+ {"C2H_WRB_COAL_CFG_SET_GLB_FLUSH",
+ C2H_WRB_COAL_CFG_SET_GLB_FLUSH_MASK},
+ {"C2H_WRB_COAL_CFG_DONE_GLB_FLUSH",
+ C2H_WRB_COAL_CFG_DONE_GLB_FLUSH_MASK},
};
static struct regfield_info
- c2h_crdt_coal_cfg_1_field_info[] = {
- {"C2H_CRDT_COAL_CFG_1_RSVD_1",
- C2H_CRDT_COAL_CFG_1_RSVD_1_MASK},
- {"C2H_CRDT_COAL_CFG_1_PLD_FIFO_TH",
- C2H_CRDT_COAL_CFG_1_PLD_FIFO_TH_MASK},
- {"C2H_CRDT_COAL_CFG_1_TIMER_TH",
- C2H_CRDT_COAL_CFG_1_TIMER_TH_MASK},
+ c2h_intr_h2c_req_field_info[] = {
+ {"C2H_INTR_H2C_REQ_RSVD_1",
+ C2H_INTR_H2C_REQ_RSVD_1_MASK},
+ {"C2H_INTR_H2C_REQ_CNT",
+ C2H_INTR_H2C_REQ_CNT_MASK},
};
static struct regfield_info
- c2h_crdt_coal_cfg_2_field_info[] = {
- {"C2H_CRDT_COAL_CFG_2_RSVD_1",
- C2H_CRDT_COAL_CFG_2_RSVD_1_MASK},
- {"C2H_CRDT_COAL_CFG_2_FIFO_TH",
- C2H_CRDT_COAL_CFG_2_FIFO_TH_MASK},
- {"C2H_CRDT_COAL_CFG_2_RESERVED1",
- C2H_CRDT_COAL_CFG_2_RESERVED1_MASK},
- {"C2H_CRDT_COAL_CFG_2_NT_TH",
- C2H_CRDT_COAL_CFG_2_NT_TH_MASK},
+ c2h_intr_c2h_mm_req_field_info[] = {
+ {"C2H_INTR_C2H_MM_REQ_RSVD_1",
+ C2H_INTR_C2H_MM_REQ_RSVD_1_MASK},
+ {"C2H_INTR_C2H_MM_REQ_CNT",
+ C2H_INTR_C2H_MM_REQ_CNT_MASK},
};
static struct regfield_info
- c2h_pfch_byp_qid_field_info[] = {
- {"C2H_PFCH_BYP_QID_RSVD_1",
- C2H_PFCH_BYP_QID_RSVD_1_MASK},
- {"C2H_PFCH_BYP_QID",
- C2H_PFCH_BYP_QID_MASK},
+ c2h_intr_err_int_req_field_info[] = {
+ {"C2H_INTR_ERR_INT_REQ_RSVD_1",
+ C2H_INTR_ERR_INT_REQ_RSVD_1_MASK},
+ {"C2H_INTR_ERR_INT_REQ_CNT",
+ C2H_INTR_ERR_INT_REQ_CNT_MASK},
};
static struct regfield_info
- c2h_pfch_byp_tag_field_info[] = {
- {"C2H_PFCH_BYP_TAG_RSVD_1",
- C2H_PFCH_BYP_TAG_RSVD_1_MASK},
- {"C2H_PFCH_BYP_TAG_BYP_QID",
- C2H_PFCH_BYP_TAG_BYP_QID_MASK},
- {"C2H_PFCH_BYP_TAG_RSVD_2",
- C2H_PFCH_BYP_TAG_RSVD_2_MASK},
- {"C2H_PFCH_BYP_TAG",
- C2H_PFCH_BYP_TAG_MASK},
+ c2h_intr_c2h_st_req_field_info[] = {
+ {"C2H_INTR_C2H_ST_REQ_RSVD_1",
+ C2H_INTR_C2H_ST_REQ_RSVD_1_MASK},
+ {"C2H_INTR_C2H_ST_REQ_CNT",
+ C2H_INTR_C2H_ST_REQ_CNT_MASK},
};
static struct regfield_info
- c2h_water_mark_field_info[] = {
- {"C2H_WATER_MARK_HIGH_WM",
- C2H_WATER_MARK_HIGH_WM_MASK},
- {"C2H_WATER_MARK_LOW_WM",
- C2H_WATER_MARK_LOW_WM_MASK},
+ c2h_intr_h2c_err_c2h_mm_msix_ack_field_info[] = {
+ {"C2H_INTR_H2C_ERR_C2H_MM_MSIX_ACK_RSVD_1",
+ C2H_INTR_H2C_ERR_C2H_MM_MSIX_ACK_RSVD_1_MASK},
+ {"C2H_INTR_H2C_ERR_C2H_MM_MSIX_ACK_CNT",
+ C2H_INTR_H2C_ERR_C2H_MM_MSIX_ACK_CNT_MASK},
};
-static struct xreg_info eqdma_config_regs[] = {
-{"CFG_BLK_IDENTIFIER", 0x00,
+
+static struct regfield_info
+ c2h_intr_h2c_err_c2h_mm_msix_fail_field_info[] = {
+ {"C2H_INTR_H2C_ERR_C2H_MM_MSIX_FAIL_RSVD_1",
+ C2H_INTR_H2C_ERR_C2H_MM_MSIX_FAIL_RSVD_1_MASK},
+ {"C2H_INTR_H2C_ERR_C2H_MM_MSIX_FAIL_CNT",
+ C2H_INTR_H2C_ERR_C2H_MM_MSIX_FAIL_CNT_MASK},
+};
+
+
+static struct regfield_info
+ c2h_intr_h2c_err_c2h_mm_msix_no_msix_field_info[] = {
+ {"C2H_INTR_H2C_ERR_C2H_MM_MSIX_NO_MSIX_RSVD_1",
+ C2H_INTR_H2C_ERR_C2H_MM_MSIX_NO_MSIX_RSVD_1_MASK},
+ {"C2H_INTR_H2C_ERR_C2H_MM_MSIX_NO_MSIX_CNT",
+ C2H_INTR_H2C_ERR_C2H_MM_MSIX_NO_MSIX_CNT_MASK},
+};
+
+
+static struct regfield_info
+ c2h_intr_h2c_err_c2h_mm_ctxt_inval_field_info[] = {
+ {"C2H_INTR_H2C_ERR_C2H_MM_CTXT_INVAL_RSVD_1",
+ C2H_INTR_H2C_ERR_C2H_MM_CTXT_INVAL_RSVD_1_MASK},
+ {"C2H_INTR_H2C_ERR_C2H_MM_CTXT_INVAL_CNT",
+ C2H_INTR_H2C_ERR_C2H_MM_CTXT_INVAL_CNT_MASK},
+};
+
+
+static struct regfield_info
+ c2h_intr_c2h_st_msix_ack_field_info[] = {
+ {"C2H_INTR_C2H_ST_MSIX_ACK_RSVD_1",
+ C2H_INTR_C2H_ST_MSIX_ACK_RSVD_1_MASK},
+ {"C2H_INTR_C2H_ST_MSIX_ACK_CNT",
+ C2H_INTR_C2H_ST_MSIX_ACK_CNT_MASK},
+};
+
+
+static struct regfield_info
+ c2h_intr_c2h_st_msix_fail_field_info[] = {
+ {"C2H_INTR_C2H_ST_MSIX_FAIL_RSVD_1",
+ C2H_INTR_C2H_ST_MSIX_FAIL_RSVD_1_MASK},
+ {"C2H_INTR_C2H_ST_MSIX_FAIL_CNT",
+ C2H_INTR_C2H_ST_MSIX_FAIL_CNT_MASK},
+};
+
+
+static struct regfield_info
+ c2h_intr_c2h_st_no_msix_field_info[] = {
+ {"C2H_INTR_C2H_ST_NO_MSIX_RSVD_1",
+ C2H_INTR_C2H_ST_NO_MSIX_RSVD_1_MASK},
+ {"C2H_INTR_C2H_ST_NO_MSIX_CNT",
+ C2H_INTR_C2H_ST_NO_MSIX_CNT_MASK},
+};
+
+
+static struct regfield_info
+ c2h_intr_c2h_st_ctxt_inval_field_info[] = {
+ {"C2H_INTR_C2H_ST_CTXT_INVAL_RSVD_1",
+ C2H_INTR_C2H_ST_CTXT_INVAL_RSVD_1_MASK},
+ {"C2H_INTR_C2H_ST_CTXT_INVAL_CNT",
+ C2H_INTR_C2H_ST_CTXT_INVAL_CNT_MASK},
+};
+
+
+static struct regfield_info
+ c2h_stat_wr_cmp_field_info[] = {
+ {"C2H_STAT_WR_CMP_RSVD_1",
+ C2H_STAT_WR_CMP_RSVD_1_MASK},
+ {"C2H_STAT_WR_CMP_CNT",
+ C2H_STAT_WR_CMP_CNT_MASK},
+};
+
+
+static struct regfield_info
+ c2h_stat_dbg_dma_eng_4_field_info[] = {
+ {"C2H_STAT_DMA_ENG_4_QID_FIFO_OUT_DAT_HAS_CMPT_1",
+ C2H_STAT_DMA_ENG_4_QID_FIFO_OUT_DAT_HAS_CMPT_1_MASK},
+ {"C2H_STAT_DMA_ENG_4_QID_FIFO_OUT_DAT_MARKER_1",
+ C2H_STAT_DMA_ENG_4_QID_FIFO_OUT_DAT_MARKER_1_MASK},
+ {"C2H_STAT_DMA_ENG_4_QID_FIFO_OUT_DAT_DROP_REQ_1",
+ C2H_STAT_DMA_ENG_4_QID_FIFO_OUT_DAT_DROP_REQ_1_MASK},
+ {"C2H_STAT_DMA_ENG_4_QID_FIFO_OUT_DAT_QID_1",
+ C2H_STAT_DMA_ENG_4_QID_FIFO_OUT_DAT_QID_1_MASK},
+ {"C2H_STAT_DMA_ENG_4_WR_HDR_FIFO_OUT_CNT_1",
+ C2H_STAT_DMA_ENG_4_WR_HDR_FIFO_OUT_CNT_1_MASK},
+ {"C2H_STAT_DMA_ENG_4_QID_FIFO_OUT_VLD_1",
+ C2H_STAT_DMA_ENG_4_QID_FIFO_OUT_VLD_1_MASK},
+ {"C2H_STAT_DMA_ENG_4_PLD_FIFO_OUT_VLD_1",
+ C2H_STAT_DMA_ENG_4_PLD_FIFO_OUT_VLD_1_MASK},
+ {"C2H_STAT_DMA_ENG_4_PLD_ST_FIFO_OUT_VLD_1",
+ C2H_STAT_DMA_ENG_4_PLD_ST_FIFO_OUT_VLD_1_MASK},
+ {"C2H_STAT_DMA_ENG_4_PLD_ST_FIFO_OUT_DATA_EOP_1",
+ C2H_STAT_DMA_ENG_4_PLD_ST_FIFO_OUT_DATA_EOP_1_MASK},
+ {"C2H_STAT_DMA_ENG_4_PLD_ST_FIFO_OUT_DATA_AVL_IDX_ENABLE_1",
+ C2H_STAT_DMA_ENG_4_PLD_ST_FIFO_OUT_DATA_AVL_IDX_ENABLE_1_MASK},
+ {"C2H_STAT_DMA_ENG_4_PLD_ST_FIFO_OUT_DATA_DROP_1",
+ C2H_STAT_DMA_ENG_4_PLD_ST_FIFO_OUT_DATA_DROP_1_MASK},
+ {"C2H_STAT_DMA_ENG_4_PLD_ST_FIFO_OUT_DATA_ERR_1",
+ C2H_STAT_DMA_ENG_4_PLD_ST_FIFO_OUT_DATA_ERR_1_MASK},
+ {"C2H_STAT_DMA_ENG_4_DESC_CNT_FIFO_IN_RDY_1",
+ C2H_STAT_DMA_ENG_4_DESC_CNT_FIFO_IN_RDY_1_MASK},
+ {"C2H_STAT_DMA_ENG_4_DESC_RSP_FIFO_IN_RDY_1",
+ C2H_STAT_DMA_ENG_4_DESC_RSP_FIFO_IN_RDY_1_MASK},
+ {"C2H_STAT_DMA_ENG_4_PLD_PKT_ID_LARGER_1",
+ C2H_STAT_DMA_ENG_4_PLD_PKT_ID_LARGER_1_MASK},
+ {"C2H_STAT_DMA_ENG_4_WCP_FIFO_IN_RDY_1",
+ C2H_STAT_DMA_ENG_4_WCP_FIFO_IN_RDY_1_MASK},
+ {"C2H_STAT_DMA_ENG_4_PLD_ST_FIFO_IN_RDY_1",
+ C2H_STAT_DMA_ENG_4_PLD_ST_FIFO_IN_RDY_1_MASK},
+};
+
+
+static struct regfield_info
+ c2h_stat_dbg_dma_eng_5_field_info[] = {
+ {"C2H_STAT_DMA_ENG_5_ARB_FIFO_IN_RDY",
+ C2H_STAT_DMA_ENG_5_ARB_FIFO_IN_RDY_MASK},
+ {"C2H_STAT_DMA_ENG_5_WRB_SM_VIRT_CH",
+ C2H_STAT_DMA_ENG_5_WRB_SM_VIRT_CH_MASK},
+ {"C2H_STAT_DMA_ENG_5_WRB_FIFO_IN_REQ",
+ C2H_STAT_DMA_ENG_5_WRB_FIFO_IN_REQ_MASK},
+ {"C2H_STAT_DMA_ENG_5_ARB_FIFO_OUT_CNT",
+ C2H_STAT_DMA_ENG_5_ARB_FIFO_OUT_CNT_MASK},
+ {"C2H_STAT_DMA_ENG_5_ARB_FIFO_OUT_DATA_LEN",
+ C2H_STAT_DMA_ENG_5_ARB_FIFO_OUT_DATA_LEN_MASK},
+ {"C2H_STAT_DMA_ENG_5_ARB_FIFO_OUT_DATA_VIRT_CH",
+ C2H_STAT_DMA_ENG_5_ARB_FIFO_OUT_DATA_VIRT_CH_MASK},
+ {"C2H_STAT_DMA_ENG_5_ARB_FIFO_OUT_DATA_VAR_DESC",
+ C2H_STAT_DMA_ENG_5_ARB_FIFO_OUT_DATA_VAR_DESC_MASK},
+ {"C2H_STAT_DMA_ENG_5_ARB_FIFO_OUT_DATA_DROP_REQ",
+ C2H_STAT_DMA_ENG_5_ARB_FIFO_OUT_DATA_DROP_REQ_MASK},
+ {"C2H_STAT_DMA_ENG_5_ARB_FIFO_OUT_DATA_NUM_BUF_OV",
+ C2H_STAT_DMA_ENG_5_ARB_FIFO_OUT_DATA_NUM_BUF_OV_MASK},
+ {"C2H_STAT_DMA_ENG_5_ARB_FIFO_OUT_DATA_MARKER",
+ C2H_STAT_DMA_ENG_5_ARB_FIFO_OUT_DATA_MARKER_MASK},
+ {"C2H_STAT_DMA_ENG_5_ARB_FIFO_OUT_DATA_HAS_CMPT",
+ C2H_STAT_DMA_ENG_5_ARB_FIFO_OUT_DATA_HAS_CMPT_MASK},
+};
+
+
+static struct regfield_info
+ c2h_dbg_pfch_qid_field_info[] = {
+ {"C2H_PFCH_QID_RSVD_1",
+ C2H_PFCH_QID_RSVD_1_MASK},
+ {"C2H_PFCH_QID_ERR_CTXT",
+ C2H_PFCH_QID_ERR_CTXT_MASK},
+ {"C2H_PFCH_QID_TARGET",
+ C2H_PFCH_QID_TARGET_MASK},
+ {"C2H_PFCH_QID_QID_OR_TAG",
+ C2H_PFCH_QID_QID_OR_TAG_MASK},
+};
+
+
+static struct regfield_info
+ c2h_dbg_pfch_field_info[] = {
+ {"C2H_PFCH_DATA",
+ C2H_PFCH_DATA_MASK},
+};
+
+
+static struct regfield_info
+ c2h_int_dbg_field_info[] = {
+ {"C2H_INT_RSVD_1",
+ C2H_INT_RSVD_1_MASK},
+ {"C2H_INT_INT_COAL_SM",
+ C2H_INT_INT_COAL_SM_MASK},
+ {"C2H_INT_INT_SM",
+ C2H_INT_INT_SM_MASK},
+};
+
+
+static struct regfield_info
+ c2h_stat_imm_accepted_field_info[] = {
+ {"C2H_STAT_IMM_ACCEPTED_RSVD_1",
+ C2H_STAT_IMM_ACCEPTED_RSVD_1_MASK},
+ {"C2H_STAT_IMM_ACCEPTED_CNT",
+ C2H_STAT_IMM_ACCEPTED_CNT_MASK},
+};
+
+
+static struct regfield_info
+ c2h_stat_marker_accepted_field_info[] = {
+ {"C2H_STAT_MARKER_ACCEPTED_RSVD_1",
+ C2H_STAT_MARKER_ACCEPTED_RSVD_1_MASK},
+ {"C2H_STAT_MARKER_ACCEPTED_CNT",
+ C2H_STAT_MARKER_ACCEPTED_CNT_MASK},
+};
+
+
+static struct regfield_info
+ c2h_stat_disable_cmp_accepted_field_info[] = {
+ {"C2H_STAT_DISABLE_CMP_ACCEPTED_RSVD_1",
+ C2H_STAT_DISABLE_CMP_ACCEPTED_RSVD_1_MASK},
+ {"C2H_STAT_DISABLE_CMP_ACCEPTED_CNT",
+ C2H_STAT_DISABLE_CMP_ACCEPTED_CNT_MASK},
+};
+
+
+static struct regfield_info
+ c2h_pld_fifo_crdt_cnt_field_info[] = {
+ {"C2H_PLD_FIFO_CRDT_CNT_RSVD_1",
+ C2H_PLD_FIFO_CRDT_CNT_RSVD_1_MASK},
+ {"C2H_PLD_FIFO_CRDT_CNT_CNT",
+ C2H_PLD_FIFO_CRDT_CNT_CNT_MASK},
+};
+
+
+static struct regfield_info
+ c2h_intr_dyn_req_field_info[] = {
+ {"C2H_INTR_DYN_REQ_RSVD_1",
+ C2H_INTR_DYN_REQ_RSVD_1_MASK},
+ {"C2H_INTR_DYN_REQ_CNT",
+ C2H_INTR_DYN_REQ_CNT_MASK},
+};
+
+
+static struct regfield_info
+ c2h_intr_dyn_misc_field_info[] = {
+ {"C2H_INTR_DYN_MISC_RSVD_1",
+ C2H_INTR_DYN_MISC_RSVD_1_MASK},
+ {"C2H_INTR_DYN_MISC_CNT",
+ C2H_INTR_DYN_MISC_CNT_MASK},
+};
+
+
+static struct regfield_info
+ c2h_drop_len_mismatch_field_info[] = {
+ {"C2H_DROP_LEN_MISMATCH_RSVD_1",
+ C2H_DROP_LEN_MISMATCH_RSVD_1_MASK},
+ {"C2H_DROP_LEN_MISMATCH_CNT",
+ C2H_DROP_LEN_MISMATCH_CNT_MASK},
+};
+
+
+static struct regfield_info
+ c2h_drop_desc_rsp_len_field_info[] = {
+ {"C2H_DROP_DESC_RSP_LEN_RSVD_1",
+ C2H_DROP_DESC_RSP_LEN_RSVD_1_MASK},
+ {"C2H_DROP_DESC_RSP_LEN_CNT",
+ C2H_DROP_DESC_RSP_LEN_CNT_MASK},
+};
+
+
+static struct regfield_info
+ c2h_drop_qid_fifo_len_field_info[] = {
+ {"C2H_DROP_QID_FIFO_LEN_RSVD_1",
+ C2H_DROP_QID_FIFO_LEN_RSVD_1_MASK},
+ {"C2H_DROP_QID_FIFO_LEN_CNT",
+ C2H_DROP_QID_FIFO_LEN_CNT_MASK},
+};
+
+
+static struct regfield_info
+ c2h_drop_pld_cnt_field_info[] = {
+ {"C2H_DROP_PLD_CNT_RSVD_1",
+ C2H_DROP_PLD_CNT_RSVD_1_MASK},
+ {"C2H_DROP_PLD_CNT_CNT",
+ C2H_DROP_PLD_CNT_CNT_MASK},
+};
+
+
+static struct regfield_info
+ c2h_cmpt_format_0_field_info[] = {
+ {"C2H_CMPT_FORMAT_0_DESC_ERR_LOC",
+ C2H_CMPT_FORMAT_0_DESC_ERR_LOC_MASK},
+ {"C2H_CMPT_FORMAT_0_COLOR_LOC",
+ C2H_CMPT_FORMAT_0_COLOR_LOC_MASK},
+};
+
+
+static struct regfield_info
+ c2h_cmpt_format_1_field_info[] = {
+ {"C2H_CMPT_FORMAT_1_DESC_ERR_LOC",
+ C2H_CMPT_FORMAT_1_DESC_ERR_LOC_MASK},
+ {"C2H_CMPT_FORMAT_1_COLOR_LOC",
+ C2H_CMPT_FORMAT_1_COLOR_LOC_MASK},
+};
+
+
+static struct regfield_info
+ c2h_cmpt_format_2_field_info[] = {
+ {"C2H_CMPT_FORMAT_2_DESC_ERR_LOC",
+ C2H_CMPT_FORMAT_2_DESC_ERR_LOC_MASK},
+ {"C2H_CMPT_FORMAT_2_COLOR_LOC",
+ C2H_CMPT_FORMAT_2_COLOR_LOC_MASK},
+};
+
+
+static struct regfield_info
+ c2h_cmpt_format_3_field_info[] = {
+ {"C2H_CMPT_FORMAT_3_DESC_ERR_LOC",
+ C2H_CMPT_FORMAT_3_DESC_ERR_LOC_MASK},
+ {"C2H_CMPT_FORMAT_3_COLOR_LOC",
+ C2H_CMPT_FORMAT_3_COLOR_LOC_MASK},
+};
+
+
+static struct regfield_info
+ c2h_cmpt_format_4_field_info[] = {
+ {"C2H_CMPT_FORMAT_4_DESC_ERR_LOC",
+ C2H_CMPT_FORMAT_4_DESC_ERR_LOC_MASK},
+ {"C2H_CMPT_FORMAT_4_COLOR_LOC",
+ C2H_CMPT_FORMAT_4_COLOR_LOC_MASK},
+};
+
+
+static struct regfield_info
+ c2h_cmpt_format_5_field_info[] = {
+ {"C2H_CMPT_FORMAT_5_DESC_ERR_LOC",
+ C2H_CMPT_FORMAT_5_DESC_ERR_LOC_MASK},
+ {"C2H_CMPT_FORMAT_5_COLOR_LOC",
+ C2H_CMPT_FORMAT_5_COLOR_LOC_MASK},
+};
+
+
+static struct regfield_info
+ c2h_cmpt_format_6_field_info[] = {
+ {"C2H_CMPT_FORMAT_6_DESC_ERR_LOC",
+ C2H_CMPT_FORMAT_6_DESC_ERR_LOC_MASK},
+ {"C2H_CMPT_FORMAT_6_COLOR_LOC",
+ C2H_CMPT_FORMAT_6_COLOR_LOC_MASK},
+};
+
+
+static struct regfield_info
+ c2h_pfch_cache_depth_field_info[] = {
+ {"C2H_PFCH_CACHE_DEPTH_MAX_STBUF",
+ C2H_PFCH_CACHE_DEPTH_MAX_STBUF_MASK},
+ {"C2H_PFCH_CACHE_DEPTH",
+ C2H_PFCH_CACHE_DEPTH_MASK},
+};
+
+
+static struct regfield_info
+ c2h_wrb_coal_buf_depth_field_info[] = {
+ {"C2H_WRB_COAL_BUF_DEPTH_RSVD_1",
+ C2H_WRB_COAL_BUF_DEPTH_RSVD_1_MASK},
+ {"C2H_WRB_COAL_BUF_DEPTH_BUFFER",
+ C2H_WRB_COAL_BUF_DEPTH_BUFFER_MASK},
+};
+
+
+static struct regfield_info
+ c2h_pfch_crdt_field_info[] = {
+ {"C2H_PFCH_CRDT_RSVD_1",
+ C2H_PFCH_CRDT_RSVD_1_MASK},
+ {"C2H_PFCH_CRDT_RSVD_2",
+ C2H_PFCH_CRDT_RSVD_2_MASK},
+};
+
+
+static struct regfield_info
+ c2h_stat_has_cmpt_accepted_field_info[] = {
+ {"C2H_STAT_HAS_CMPT_ACCEPTED_RSVD_1",
+ C2H_STAT_HAS_CMPT_ACCEPTED_RSVD_1_MASK},
+ {"C2H_STAT_HAS_CMPT_ACCEPTED_CNT",
+ C2H_STAT_HAS_CMPT_ACCEPTED_CNT_MASK},
+};
+
+
+static struct regfield_info
+ c2h_stat_has_pld_accepted_field_info[] = {
+ {"C2H_STAT_HAS_PLD_ACCEPTED_RSVD_1",
+ C2H_STAT_HAS_PLD_ACCEPTED_RSVD_1_MASK},
+ {"C2H_STAT_HAS_PLD_ACCEPTED_CNT",
+ C2H_STAT_HAS_PLD_ACCEPTED_CNT_MASK},
+};
+
+
+static struct regfield_info
+ c2h_pld_pkt_id_field_info[] = {
+ {"C2H_PLD_PKT_ID_CMPT_WAIT",
+ C2H_PLD_PKT_ID_CMPT_WAIT_MASK},
+ {"C2H_PLD_PKT_ID_DATA",
+ C2H_PLD_PKT_ID_DATA_MASK},
+};
+
+
+static struct regfield_info
+ c2h_pld_pkt_id_1_field_info[] = {
+ {"C2H_PLD_PKT_ID_1_CMPT_WAIT",
+ C2H_PLD_PKT_ID_1_CMPT_WAIT_MASK},
+ {"C2H_PLD_PKT_ID_1_DATA",
+ C2H_PLD_PKT_ID_1_DATA_MASK},
+};
+
+
+static struct regfield_info
+ c2h_drop_pld_cnt_1_field_info[] = {
+ {"C2H_DROP_PLD_CNT_1_RSVD_1",
+ C2H_DROP_PLD_CNT_1_RSVD_1_MASK},
+ {"C2H_DROP_PLD_CNT_1_CNT",
+ C2H_DROP_PLD_CNT_1_CNT_MASK},
+};
+
+
+static struct regfield_info
+ h2c_err_stat_field_info[] = {
+ {"H2C_ERR_STAT_RSVD_1",
+ H2C_ERR_STAT_RSVD_1_MASK},
+ {"H2C_ERR_STAT_PAR_ERR",
+ H2C_ERR_STAT_PAR_ERR_MASK},
+ {"H2C_ERR_STAT_SBE",
+ H2C_ERR_STAT_SBE_MASK},
+ {"H2C_ERR_STAT_DBE",
+ H2C_ERR_STAT_DBE_MASK},
+ {"H2C_ERR_STAT_NO_DMA_DS",
+ H2C_ERR_STAT_NO_DMA_DS_MASK},
+ {"H2C_ERR_STAT_SDI_MRKR_REQ_MOP_ERR",
+ H2C_ERR_STAT_SDI_MRKR_REQ_MOP_ERR_MASK},
+ {"H2C_ERR_STAT_ZERO_LEN_DS",
+ H2C_ERR_STAT_ZERO_LEN_DS_MASK},
+};
+
+
+static struct regfield_info
+ h2c_err_mask_field_info[] = {
+ {"H2C_ERR_EN",
+ H2C_ERR_EN_MASK},
+};
+
+
+static struct regfield_info
+ h2c_first_err_qid_field_info[] = {
+ {"H2C_FIRST_ERR_QID_RSVD_1",
+ H2C_FIRST_ERR_QID_RSVD_1_MASK},
+ {"H2C_FIRST_ERR_QID_ERR_TYPE",
+ H2C_FIRST_ERR_QID_ERR_TYPE_MASK},
+ {"H2C_FIRST_ERR_QID_RSVD_2",
+ H2C_FIRST_ERR_QID_RSVD_2_MASK},
+ {"H2C_FIRST_ERR_QID_QID",
+ H2C_FIRST_ERR_QID_QID_MASK},
+};
+
+
+static struct regfield_info
+ h2c_dbg_reg0_field_info[] = {
+ {"H2C_REG0_NUM_DSC_RCVD",
+ H2C_REG0_NUM_DSC_RCVD_MASK},
+ {"H2C_REG0_NUM_WRB_SENT",
+ H2C_REG0_NUM_WRB_SENT_MASK},
+};
+
+
+static struct regfield_info
+ h2c_dbg_reg1_field_info[] = {
+ {"H2C_REG1_NUM_REQ_SENT",
+ H2C_REG1_NUM_REQ_SENT_MASK},
+ {"H2C_REG1_NUM_CMP_SENT",
+ H2C_REG1_NUM_CMP_SENT_MASK},
+};
+
+
+static struct regfield_info
+ h2c_dbg_reg2_field_info[] = {
+ {"H2C_REG2_RSVD_1",
+ H2C_REG2_RSVD_1_MASK},
+ {"H2C_REG2_NUM_ERR_DSC_RCVD",
+ H2C_REG2_NUM_ERR_DSC_RCVD_MASK},
+};
+
+
+static struct regfield_info
+ h2c_dbg_reg3_field_info[] = {
+ {"H2C_REG3_RSVD_1",
+ H2C_REG3_RSVD_1_MASK},
+ {"H2C_REG3_DSCO_FIFO_EMPTY",
+ H2C_REG3_DSCO_FIFO_EMPTY_MASK},
+ {"H2C_REG3_DSCO_FIFO_FULL",
+ H2C_REG3_DSCO_FIFO_FULL_MASK},
+ {"H2C_REG3_CUR_RC_STATE",
+ H2C_REG3_CUR_RC_STATE_MASK},
+ {"H2C_REG3_RDREQ_LINES",
+ H2C_REG3_RDREQ_LINES_MASK},
+ {"H2C_REG3_RDATA_LINES_AVAIL",
+ H2C_REG3_RDATA_LINES_AVAIL_MASK},
+ {"H2C_REG3_PEND_FIFO_EMPTY",
+ H2C_REG3_PEND_FIFO_EMPTY_MASK},
+ {"H2C_REG3_PEND_FIFO_FULL",
+ H2C_REG3_PEND_FIFO_FULL_MASK},
+ {"H2C_REG3_CUR_RQ_STATE",
+ H2C_REG3_CUR_RQ_STATE_MASK},
+ {"H2C_REG3_DSCI_FIFO_FULL",
+ H2C_REG3_DSCI_FIFO_FULL_MASK},
+ {"H2C_REG3_DSCI_FIFO_EMPTY",
+ H2C_REG3_DSCI_FIFO_EMPTY_MASK},
+};
+
+
+static struct regfield_info
+ h2c_dbg_reg4_field_info[] = {
+ {"H2C_REG4_RDREQ_ADDR",
+ H2C_REG4_RDREQ_ADDR_MASK},
+};
+
+
+static struct regfield_info
+ h2c_fatal_err_en_field_info[] = {
+ {"H2C_FATAL_ERR_EN_RSVD_1",
+ H2C_FATAL_ERR_EN_RSVD_1_MASK},
+ {"H2C_FATAL_ERR_EN_H2C",
+ H2C_FATAL_ERR_EN_H2C_MASK},
+};
+
+
+static struct regfield_info
+ h2c_req_throt_pcie_field_info[] = {
+ {"H2C_REQ_THROT_PCIE_EN_REQ",
+ H2C_REQ_THROT_PCIE_EN_REQ_MASK},
+ {"H2C_REQ_THROT_PCIE",
+ H2C_REQ_THROT_PCIE_MASK},
+ {"H2C_REQ_THROT_PCIE_EN_DATA",
+ H2C_REQ_THROT_PCIE_EN_DATA_MASK},
+ {"H2C_REQ_THROT_PCIE_DATA_THRESH",
+ H2C_REQ_THROT_PCIE_DATA_THRESH_MASK},
+};
+
+
+static struct regfield_info
+ h2c_aln_dbg_reg0_field_info[] = {
+ {"H2C_ALN_REG0_NUM_PKT_SENT",
+ H2C_ALN_REG0_NUM_PKT_SENT_MASK},
+};
+
+
+static struct regfield_info
+ h2c_req_throt_aximm_field_info[] = {
+ {"H2C_REQ_THROT_AXIMM_EN_REQ",
+ H2C_REQ_THROT_AXIMM_EN_REQ_MASK},
+ {"H2C_REQ_THROT_AXIMM",
+ H2C_REQ_THROT_AXIMM_MASK},
+ {"H2C_REQ_THROT_AXIMM_EN_DATA",
+ H2C_REQ_THROT_AXIMM_EN_DATA_MASK},
+ {"H2C_REQ_THROT_AXIMM_DATA_THRESH",
+ H2C_REQ_THROT_AXIMM_DATA_THRESH_MASK},
+};
+
+
+static struct regfield_info
+ c2h_mm_ctl_field_info[] = {
+ {"C2H_MM_CTL_RESERVED1",
+ C2H_MM_CTL_RESERVED1_MASK},
+ {"C2H_MM_CTL_ERRC_EN",
+ C2H_MM_CTL_ERRC_EN_MASK},
+ {"C2H_MM_CTL_RESERVED0",
+ C2H_MM_CTL_RESERVED0_MASK},
+ {"C2H_MM_CTL_RUN",
+ C2H_MM_CTL_RUN_MASK},
+};
+
+
+static struct regfield_info
+ c2h_mm_status_field_info[] = {
+ {"C2H_MM_STATUS_RSVD_1",
+ C2H_MM_STATUS_RSVD_1_MASK},
+ {"C2H_MM_STATUS_RUN",
+ C2H_MM_STATUS_RUN_MASK},
+};
+
+
+static struct regfield_info
+ c2h_mm_cmpl_desc_cnt_field_info[] = {
+ {"C2H_MM_CMPL_DESC_CNT_C2H_CO",
+ C2H_MM_CMPL_DESC_CNT_C2H_CO_MASK},
+};
+
+
+static struct regfield_info
+ c2h_mm_err_code_enable_mask_field_info[] = {
+ {"C2H_MM_ERR_CODE_ENABLE_RESERVED1",
+ C2H_MM_ERR_CODE_ENABLE_RESERVED1_MASK},
+ {"C2H_MM_ERR_CODE_ENABLE_WR_UC_RAM",
+ C2H_MM_ERR_CODE_ENABLE_WR_UC_RAM_MASK},
+ {"C2H_MM_ERR_CODE_ENABLE_WR_UR",
+ C2H_MM_ERR_CODE_ENABLE_WR_UR_MASK},
+ {"C2H_MM_ERR_CODE_ENABLE_WR_FLR",
+ C2H_MM_ERR_CODE_ENABLE_WR_FLR_MASK},
+ {"C2H_MM_ERR_CODE_ENABLE_RESERVED0",
+ C2H_MM_ERR_CODE_ENABLE_RESERVED0_MASK},
+ {"C2H_MM_ERR_CODE_ENABLE_RD_SLV_ERR",
+ C2H_MM_ERR_CODE_ENABLE_RD_SLV_ERR_MASK},
+ {"C2H_MM_ERR_CODE_ENABLE_WR_SLV_ERR",
+ C2H_MM_ERR_CODE_ENABLE_WR_SLV_ERR_MASK},
+};
+
+
+static struct regfield_info
+ c2h_mm_err_code_field_info[] = {
+ {"C2H_MM_ERR_CODE_RESERVED1",
+ C2H_MM_ERR_CODE_RESERVED1_MASK},
+ {"C2H_MM_ERR_CODE_CIDX",
+ C2H_MM_ERR_CODE_CIDX_MASK},
+ {"C2H_MM_ERR_CODE_RESERVED0",
+ C2H_MM_ERR_CODE_RESERVED0_MASK},
+ {"C2H_MM_ERR_CODE_SUB_TYPE",
+ C2H_MM_ERR_CODE_SUB_TYPE_MASK},
+ {"C2H_MM_ERR_CODE",
+ C2H_MM_ERR_CODE_MASK},
+};
+
+
+static struct regfield_info
+ c2h_mm_err_info_field_info[] = {
+ {"C2H_MM_ERR_INFO_VALID",
+ C2H_MM_ERR_INFO_VALID_MASK},
+ {"C2H_MM_ERR_INFO_SEL",
+ C2H_MM_ERR_INFO_SEL_MASK},
+ {"C2H_MM_ERR_INFO_RSVD_1",
+ C2H_MM_ERR_INFO_RSVD_1_MASK},
+ {"C2H_MM_ERR_INFO_QID",
+ C2H_MM_ERR_INFO_QID_MASK},
+};
+
+
+static struct regfield_info
+ c2h_mm_perf_mon_ctl_field_info[] = {
+ {"C2H_MM_PERF_MON_CTL_RSVD_1",
+ C2H_MM_PERF_MON_CTL_RSVD_1_MASK},
+ {"C2H_MM_PERF_MON_CTL_IMM_START",
+ C2H_MM_PERF_MON_CTL_IMM_START_MASK},
+ {"C2H_MM_PERF_MON_CTL_RUN_START",
+ C2H_MM_PERF_MON_CTL_RUN_START_MASK},
+ {"C2H_MM_PERF_MON_CTL_IMM_CLEAR",
+ C2H_MM_PERF_MON_CTL_IMM_CLEAR_MASK},
+ {"C2H_MM_PERF_MON_CTL_RUN_CLEAR",
+ C2H_MM_PERF_MON_CTL_RUN_CLEAR_MASK},
+};
+
+
+static struct regfield_info
+ c2h_mm_perf_mon_cycle_cnt0_field_info[] = {
+ {"C2H_MM_PERF_MON_CYCLE_CNT0_CYC_CNT",
+ C2H_MM_PERF_MON_CYCLE_CNT0_CYC_CNT_MASK},
+};
+
+
+static struct regfield_info
+ c2h_mm_perf_mon_cycle_cnt1_field_info[] = {
+ {"C2H_MM_PERF_MON_CYCLE_CNT1_RSVD_1",
+ C2H_MM_PERF_MON_CYCLE_CNT1_RSVD_1_MASK},
+ {"C2H_MM_PERF_MON_CYCLE_CNT1_CYC_CNT",
+ C2H_MM_PERF_MON_CYCLE_CNT1_CYC_CNT_MASK},
+};
+
+
+static struct regfield_info
+ c2h_mm_perf_mon_data_cnt0_field_info[] = {
+ {"C2H_MM_PERF_MON_DATA_CNT0_DCNT",
+ C2H_MM_PERF_MON_DATA_CNT0_DCNT_MASK},
+};
+
+
+static struct regfield_info
+ c2h_mm_perf_mon_data_cnt1_field_info[] = {
+ {"C2H_MM_PERF_MON_DATA_CNT1_RSVD_1",
+ C2H_MM_PERF_MON_DATA_CNT1_RSVD_1_MASK},
+ {"C2H_MM_PERF_MON_DATA_CNT1_DCNT",
+ C2H_MM_PERF_MON_DATA_CNT1_DCNT_MASK},
+};
+
+
+static struct regfield_info
+ c2h_mm_dbg_field_info[] = {
+ {"C2H_MM_RSVD_1",
+ C2H_MM_RSVD_1_MASK},
+ {"C2H_MM_RRQ_ENTRIES",
+ C2H_MM_RRQ_ENTRIES_MASK},
+ {"C2H_MM_DAT_FIFO_SPC",
+ C2H_MM_DAT_FIFO_SPC_MASK},
+ {"C2H_MM_RD_STALL",
+ C2H_MM_RD_STALL_MASK},
+ {"C2H_MM_RRQ_FIFO_FI",
+ C2H_MM_RRQ_FIFO_FI_MASK},
+ {"C2H_MM_WR_STALL",
+ C2H_MM_WR_STALL_MASK},
+ {"C2H_MM_WRQ_FIFO_FI",
+ C2H_MM_WRQ_FIFO_FI_MASK},
+ {"C2H_MM_WBK_STALL",
+ C2H_MM_WBK_STALL_MASK},
+ {"C2H_MM_DSC_FIFO_EP",
+ C2H_MM_DSC_FIFO_EP_MASK},
+ {"C2H_MM_DSC_FIFO_FL",
+ C2H_MM_DSC_FIFO_FL_MASK},
+};
+
+
+static struct regfield_info
+ h2c_mm_ctl_field_info[] = {
+ {"H2C_MM_CTL_RESERVED1",
+ H2C_MM_CTL_RESERVED1_MASK},
+ {"H2C_MM_CTL_ERRC_EN",
+ H2C_MM_CTL_ERRC_EN_MASK},
+ {"H2C_MM_CTL_RESERVED0",
+ H2C_MM_CTL_RESERVED0_MASK},
+ {"H2C_MM_CTL_RUN",
+ H2C_MM_CTL_RUN_MASK},
+};
+
+
+static struct regfield_info
+ h2c_mm_status_field_info[] = {
+ {"H2C_MM_STATUS_RSVD_1",
+ H2C_MM_STATUS_RSVD_1_MASK},
+ {"H2C_MM_STATUS_RUN",
+ H2C_MM_STATUS_RUN_MASK},
+};
+
+
+static struct regfield_info
+ h2c_mm_cmpl_desc_cnt_field_info[] = {
+ {"H2C_MM_CMPL_DESC_CNT_H2C_CO",
+ H2C_MM_CMPL_DESC_CNT_H2C_CO_MASK},
+};
+
+
+static struct regfield_info
+ h2c_mm_err_code_enable_mask_field_info[] = {
+ {"H2C_MM_ERR_CODE_ENABLE_RESERVED5",
+ H2C_MM_ERR_CODE_ENABLE_RESERVED5_MASK},
+ {"H2C_MM_ERR_CODE_ENABLE_WR_SLV_ERR",
+ H2C_MM_ERR_CODE_ENABLE_WR_SLV_ERR_MASK},
+ {"H2C_MM_ERR_CODE_ENABLE_WR_DEC_ERR",
+ H2C_MM_ERR_CODE_ENABLE_WR_DEC_ERR_MASK},
+ {"H2C_MM_ERR_CODE_ENABLE_RESERVED4",
+ H2C_MM_ERR_CODE_ENABLE_RESERVED4_MASK},
+ {"H2C_MM_ERR_CODE_ENABLE_RD_RQ_DIS_ERR",
+ H2C_MM_ERR_CODE_ENABLE_RD_RQ_DIS_ERR_MASK},
+ {"H2C_MM_ERR_CODE_ENABLE_RESERVED3",
+ H2C_MM_ERR_CODE_ENABLE_RESERVED3_MASK},
+ {"H2C_MM_ERR_CODE_ENABLE_RD_DAT_POISON_ERR",
+ H2C_MM_ERR_CODE_ENABLE_RD_DAT_POISON_ERR_MASK},
+ {"H2C_MM_ERR_CODE_ENABLE_RESERVED2",
+ H2C_MM_ERR_CODE_ENABLE_RESERVED2_MASK},
+ {"H2C_MM_ERR_CODE_ENABLE_RD_FLR_ERR",
+ H2C_MM_ERR_CODE_ENABLE_RD_FLR_ERR_MASK},
+ {"H2C_MM_ERR_CODE_ENABLE_RESERVED1",
+ H2C_MM_ERR_CODE_ENABLE_RESERVED1_MASK},
+ {"H2C_MM_ERR_CODE_ENABLE_RD_HDR_ADR_ERR",
+ H2C_MM_ERR_CODE_ENABLE_RD_HDR_ADR_ERR_MASK},
+ {"H2C_MM_ERR_CODE_ENABLE_RD_HDR_PARA",
+ H2C_MM_ERR_CODE_ENABLE_RD_HDR_PARA_MASK},
+ {"H2C_MM_ERR_CODE_ENABLE_RD_HDR_BYTE_ERR",
+ H2C_MM_ERR_CODE_ENABLE_RD_HDR_BYTE_ERR_MASK},
+ {"H2C_MM_ERR_CODE_ENABLE_RD_UR_CA",
+ H2C_MM_ERR_CODE_ENABLE_RD_UR_CA_MASK},
+ {"H2C_MM_ERR_CODE_ENABLE_RD_HRD_POISON_ERR",
+ H2C_MM_ERR_CODE_ENABLE_RD_HRD_POISON_ERR_MASK},
+ {"H2C_MM_ERR_CODE_ENABLE_RESERVED0",
+ H2C_MM_ERR_CODE_ENABLE_RESERVED0_MASK},
+};
+
+
+static struct regfield_info
+ h2c_mm_err_code_field_info[] = {
+ {"H2C_MM_ERR_CODE_RSVD_1",
+ H2C_MM_ERR_CODE_RSVD_1_MASK},
+ {"H2C_MM_ERR_CODE_CIDX",
+ H2C_MM_ERR_CODE_CIDX_MASK},
+ {"H2C_MM_ERR_CODE_RESERVED0",
+ H2C_MM_ERR_CODE_RESERVED0_MASK},
+ {"H2C_MM_ERR_CODE_SUB_TYPE",
+ H2C_MM_ERR_CODE_SUB_TYPE_MASK},
+ {"H2C_MM_ERR_CODE",
+ H2C_MM_ERR_CODE_MASK},
+};
+
+
+static struct regfield_info
+ h2c_mm_err_info_field_info[] = {
+ {"H2C_MM_ERR_INFO_VALID",
+ H2C_MM_ERR_INFO_VALID_MASK},
+ {"H2C_MM_ERR_INFO_SEL",
+ H2C_MM_ERR_INFO_SEL_MASK},
+ {"H2C_MM_ERR_INFO_RSVD_1",
+ H2C_MM_ERR_INFO_RSVD_1_MASK},
+ {"H2C_MM_ERR_INFO_QID",
+ H2C_MM_ERR_INFO_QID_MASK},
+};
+
+
+static struct regfield_info
+ h2c_mm_perf_mon_ctl_field_info[] = {
+ {"H2C_MM_PERF_MON_CTL_RSVD_1",
+ H2C_MM_PERF_MON_CTL_RSVD_1_MASK},
+ {"H2C_MM_PERF_MON_CTL_IMM_START",
+ H2C_MM_PERF_MON_CTL_IMM_START_MASK},
+ {"H2C_MM_PERF_MON_CTL_RUN_START",
+ H2C_MM_PERF_MON_CTL_RUN_START_MASK},
+ {"H2C_MM_PERF_MON_CTL_IMM_CLEAR",
+ H2C_MM_PERF_MON_CTL_IMM_CLEAR_MASK},
+ {"H2C_MM_PERF_MON_CTL_RUN_CLEAR",
+ H2C_MM_PERF_MON_CTL_RUN_CLEAR_MASK},
+};
+
+
+static struct regfield_info
+ h2c_mm_perf_mon_cycle_cnt0_field_info[] = {
+ {"H2C_MM_PERF_MON_CYCLE_CNT0_CYC_CNT",
+ H2C_MM_PERF_MON_CYCLE_CNT0_CYC_CNT_MASK},
+};
+
+
+static struct regfield_info
+ h2c_mm_perf_mon_cycle_cnt1_field_info[] = {
+ {"H2C_MM_PERF_MON_CYCLE_CNT1_RSVD_1",
+ H2C_MM_PERF_MON_CYCLE_CNT1_RSVD_1_MASK},
+ {"H2C_MM_PERF_MON_CYCLE_CNT1_CYC_CNT",
+ H2C_MM_PERF_MON_CYCLE_CNT1_CYC_CNT_MASK},
+};
+
+
+static struct regfield_info
+ h2c_mm_perf_mon_data_cnt0_field_info[] = {
+ {"H2C_MM_PERF_MON_DATA_CNT0_DCNT",
+ H2C_MM_PERF_MON_DATA_CNT0_DCNT_MASK},
+};
+
+
+static struct regfield_info
+ h2c_mm_perf_mon_data_cnt1_field_info[] = {
+ {"H2C_MM_PERF_MON_DATA_CNT1_RSVD_1",
+ H2C_MM_PERF_MON_DATA_CNT1_RSVD_1_MASK},
+ {"H2C_MM_PERF_MON_DATA_CNT1_DCNT",
+ H2C_MM_PERF_MON_DATA_CNT1_DCNT_MASK},
+};
+
+
+static struct regfield_info
+ h2c_mm_dbg_field_info[] = {
+ {"H2C_MM_RSVD_1",
+ H2C_MM_RSVD_1_MASK},
+ {"H2C_MM_RRQ_ENTRIES",
+ H2C_MM_RRQ_ENTRIES_MASK},
+ {"H2C_MM_DAT_FIFO_SPC",
+ H2C_MM_DAT_FIFO_SPC_MASK},
+ {"H2C_MM_RD_STALL",
+ H2C_MM_RD_STALL_MASK},
+ {"H2C_MM_RRQ_FIFO_FI",
+ H2C_MM_RRQ_FIFO_FI_MASK},
+ {"H2C_MM_WR_STALL",
+ H2C_MM_WR_STALL_MASK},
+ {"H2C_MM_WRQ_FIFO_FI",
+ H2C_MM_WRQ_FIFO_FI_MASK},
+ {"H2C_MM_WBK_STALL",
+ H2C_MM_WBK_STALL_MASK},
+ {"H2C_MM_DSC_FIFO_EP",
+ H2C_MM_DSC_FIFO_EP_MASK},
+ {"H2C_MM_DSC_FIFO_FL",
+ H2C_MM_DSC_FIFO_FL_MASK},
+};
+
+
+static struct regfield_info
+ h2c_mm_data_throttle_field_info[] = {
+ {"H2C_MM_DATA_THROTTLE_RSVD_1",
+ H2C_MM_DATA_THROTTLE_RSVD_1_MASK},
+ {"H2C_MM_DATA_THROTTLE_DAT_EN",
+ H2C_MM_DATA_THROTTLE_DAT_EN_MASK},
+ {"H2C_MM_DATA_THROTTLE_DAT",
+ H2C_MM_DATA_THROTTLE_DAT_MASK},
+};
+
+
+static struct regfield_info
+ c2h_crdt_coal_cfg_1_field_info[] = {
+ {"C2H_CRDT_COAL_CFG_1_RSVD_1",
+ C2H_CRDT_COAL_CFG_1_RSVD_1_MASK},
+ {"C2H_CRDT_COAL_CFG_1_PLD_FIFO_TH",
+ C2H_CRDT_COAL_CFG_1_PLD_FIFO_TH_MASK},
+ {"C2H_CRDT_COAL_CFG_1_TIMER_TH",
+ C2H_CRDT_COAL_CFG_1_TIMER_TH_MASK},
+};
+
+
+static struct regfield_info
+ c2h_crdt_coal_cfg_2_field_info[] = {
+ {"C2H_CRDT_COAL_CFG_2_RSVD_1",
+ C2H_CRDT_COAL_CFG_2_RSVD_1_MASK},
+ {"C2H_CRDT_COAL_CFG_2_FIFO_TH",
+ C2H_CRDT_COAL_CFG_2_FIFO_TH_MASK},
+ {"C2H_CRDT_COAL_CFG_2_RESERVED1",
+ C2H_CRDT_COAL_CFG_2_RESERVED1_MASK},
+ {"C2H_CRDT_COAL_CFG_2_NT_TH",
+ C2H_CRDT_COAL_CFG_2_NT_TH_MASK},
+};
+
+
+static struct regfield_info
+ c2h_pfch_byp_qid_field_info[] = {
+ {"C2H_PFCH_BYP_QID_RSVD_1",
+ C2H_PFCH_BYP_QID_RSVD_1_MASK},
+ {"C2H_PFCH_BYP_QID",
+ C2H_PFCH_BYP_QID_MASK},
+};
+
+
+static struct regfield_info
+ c2h_pfch_byp_tag_field_info[] = {
+ {"C2H_PFCH_BYP_TAG_RSVD_1",
+ C2H_PFCH_BYP_TAG_RSVD_1_MASK},
+ {"C2H_PFCH_BYP_TAG_BYP_QID",
+ C2H_PFCH_BYP_TAG_BYP_QID_MASK},
+ {"C2H_PFCH_BYP_TAG_RSVD_2",
+ C2H_PFCH_BYP_TAG_RSVD_2_MASK},
+ {"C2H_PFCH_BYP_TAG",
+ C2H_PFCH_BYP_TAG_MASK},
+};
+
+
+static struct regfield_info
+ c2h_water_mark_field_info[] = {
+ {"C2H_WATER_MARK_HIGH_WM",
+ C2H_WATER_MARK_HIGH_WM_MASK},
+ {"C2H_WATER_MARK_LOW_WM",
+ C2H_WATER_MARK_LOW_WM_MASK},
+};
+
+
+static struct regfield_info
+ c2h_notify_empty_field_info[] = {
+ {"C2H_NOTIFY_EMPTY_RSVD_1",
+ C2H_NOTIFY_EMPTY_RSVD_1_MASK},
+ {"C2H_NOTIFY_EMPTY_NOE",
+ C2H_NOTIFY_EMPTY_NOE_MASK},
+};
+
+
+static struct regfield_info
+ c2h_stat_s_axis_c2h_accepted_1_field_info[] = {
+ {"C2H_STAT_S_AXIS_C2H_ACCEPTED_1",
+ C2H_STAT_S_AXIS_C2H_ACCEPTED_1_MASK},
+};
+
+
+static struct regfield_info
+ c2h_stat_s_axis_wrb_accepted_1_field_info[] = {
+ {"C2H_STAT_S_AXIS_WRB_ACCEPTED_1",
+ C2H_STAT_S_AXIS_WRB_ACCEPTED_1_MASK},
+};
+
+
+static struct regfield_info
+ c2h_stat_desc_rsp_pkt_accepted_1_field_info[] = {
+ {"C2H_STAT_DESC_RSP_PKT_ACCEPTED_1_D",
+ C2H_STAT_DESC_RSP_PKT_ACCEPTED_1_D_MASK},
+};
+
+
+static struct regfield_info
+ c2h_stat_axis_pkg_cmp_1_field_info[] = {
+ {"C2H_STAT_AXIS_PKG_CMP_1",
+ C2H_STAT_AXIS_PKG_CMP_1_MASK},
+};
+
+
+static struct regfield_info
+ c2h_stat_s_axis_wrb_accepted_2_field_info[] = {
+ {"C2H_STAT_S_AXIS_WRB_ACCEPTED_2",
+ C2H_STAT_S_AXIS_WRB_ACCEPTED_2_MASK},
+};
+
+
+static struct regfield_info
+ c2h_st_pld_fifo_depth_field_info[] = {
+ {"C2H_ST_PLD_FIFO_DEPTH",
+ C2H_ST_PLD_FIFO_DEPTH_MASK},
+};
+
+
+static struct regfield_info
+ c2h_stat_dbg_dma_eng_6_field_info[] = {
+ {"C2H_STAT_DMA_ENG_6_RSVD",
+ C2H_STAT_DMA_ENG_6_RSVD_MASK},
+ {"C2H_STAT_DMA_ENG_6_PLD_ST_FIFO_OUT_DATA_QID",
+ C2H_STAT_DMA_ENG_6_PLD_ST_FIFO_OUT_DATA_QID_MASK},
+ {"C2H_STAT_DMA_ENG_6_PLD_STS_FIFO_OUT_DATA_PLD_ST_PKT_ID",
+ C2H_STAT_DMA_ENG_6_PLD_STS_FIFO_OUT_DATA_PLD_ST_PKT_ID_MASK},
+ {"C2H_STAT_DMA_ENG_6_PLD_PKT_ID_LARGER_PLD_ST",
+ C2H_STAT_DMA_ENG_6_PLD_PKT_ID_LARGER_PLD_ST_MASK},
+};
+
+
+static struct regfield_info
+ c2h_stat_dbg_dma_eng_7_field_info[] = {
+ {"C2H_STAT_DMA_ENG_7_RSVD",
+ C2H_STAT_DMA_ENG_7_RSVD_MASK},
+ {"C2H_STAT_DMA_ENG_7_PLD_ST_FIFO_OUT_DATA_QID_1",
+ C2H_STAT_DMA_ENG_7_PLD_ST_FIFO_OUT_DATA_QID_1_MASK},
+ {"C2H_STAT_DMA_ENG_7_PLD_STS_FIFO_OUT_DATA_PLD_ST_PKT_ID_1",
+ C2H_STAT_DMA_ENG_7_PLD_STS_FIFO_OUT_DATA_PLD_ST_PKT_ID_1_MASK},
+ {"C2H_STAT_DMA_ENG_7_PLD_PKT_ID_LARGER_PLD_ST_1",
+ C2H_STAT_DMA_ENG_7_PLD_PKT_ID_LARGER_PLD_ST_1_MASK},
+};
+
+
+static struct regfield_info
+ c2h_stat_pcie_cmp_1_field_info[] = {
+ {"C2H_STAT_PCIE_CMP_1_DEPTH",
+ C2H_STAT_PCIE_CMP_1_DEPTH_MASK},
+};
+
+
+static struct regfield_info
+ c2h_pld_fifo_almost_full_field_info[] = {
+ {"C2H_PLD_FIFO_ALMOST_FULL_ENABLE",
+ C2H_PLD_FIFO_ALMOST_FULL_ENABLE_MASK},
+ {"C2H_PLD_FIFO_ALMOST_FULL_TH",
+ C2H_PLD_FIFO_ALMOST_FULL_TH_MASK},
+};
+
+
+static struct regfield_info
+ pfch_cfg_3_field_info[] = {
+ {"PFCH_CFG_3_RSVD",
+ PFCH_CFG_3_RSVD_MASK},
+ {"PFCH_CFG_3_VAR_DESC_FL_FREE_CNT_TH",
+ PFCH_CFG_3_VAR_DESC_FL_FREE_CNT_TH_MASK},
+ {"PFCH_CFG_3_VAR_DESC_LG_PKT_CAM_CN_TH",
+ PFCH_CFG_3_VAR_DESC_LG_PKT_CAM_CN_TH_MASK},
+};
+
+
+static struct regfield_info
+ cmpt_cfg_0_field_info[] = {
+ {"CMPT_CFG_0_RSVD",
+ CMPT_CFG_0_RSVD_MASK},
+ {"CMPT_CFG_0_VIO_SPRS_INT_AFTER_RTY",
+ CMPT_CFG_0_VIO_SPRS_INT_AFTER_RTY_MASK},
+ {"CMPT_CFG_0_VIO_EVNT_SUP_EN",
+ CMPT_CFG_0_VIO_EVNT_SUP_EN_MASK},
+};
+
+
+static struct regfield_info
+ pfch_cfg_4_field_info[] = {
+ {"PFCH_CFG_4_GLB_EVT_TIMER_TICK",
+ PFCH_CFG_4_GLB_EVT_TIMER_TICK_MASK},
+ {"PFCH_CFG_4_DISABLE_GLB_EVT_TIMER",
+ PFCH_CFG_4_DISABLE_GLB_EVT_TIMER_MASK},
+ {"PFCH_CFG_4_EVT_TIMER_TICK",
+ PFCH_CFG_4_EVT_TIMER_TICK_MASK},
+ {"PFCH_CFG_4_DISABLE_EVT_TIMER",
+ PFCH_CFG_4_DISABLE_EVT_TIMER_MASK},
+};
+
+static struct xreg_info eqdma_config_regs[] = {
+{"CFG_BLK_IDENTIFIER", 0x00,
+ 1, 0, 0, 0,
+ 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY,
+ ARRAY_SIZE(cfg_blk_identifier_field_info),
+ cfg_blk_identifier_field_info
+},
+{"CFG_BLK_PCIE_MAX_PLD_SIZE", 0x08,
+ 1, 0, 0, 0,
+ 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY,
+ ARRAY_SIZE(cfg_blk_pcie_max_pld_size_field_info),
+ cfg_blk_pcie_max_pld_size_field_info
+},
+{"CFG_BLK_PCIE_MAX_READ_REQ_SIZE", 0x0c,
+ 1, 0, 0, 0,
+ 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY,
+ ARRAY_SIZE(cfg_blk_pcie_max_read_req_size_field_info),
+ cfg_blk_pcie_max_read_req_size_field_info
+},
+{"CFG_BLK_SYSTEM_ID", 0x10,
+ 1, 0, 0, 0,
+ 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY,
+ ARRAY_SIZE(cfg_blk_system_id_field_info),
+ cfg_blk_system_id_field_info
+},
+{"CFG_BLK_MSIX_ENABLE", 0x014,
+ 1, 0, 0, 0,
+ 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY,
+ ARRAY_SIZE(cfg_blk_msix_enable_field_info),
+ cfg_blk_msix_enable_field_info
+},
+{"CFG_PCIE_DATA_WIDTH", 0x18,
+ 1, 0, 0, 0,
+ 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY,
+ ARRAY_SIZE(cfg_pcie_data_width_field_info),
+ cfg_pcie_data_width_field_info
+},
+{"CFG_PCIE_CTL", 0x1c,
+ 1, 0, 0, 0,
+ 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY,
+ ARRAY_SIZE(cfg_pcie_ctl_field_info),
+ cfg_pcie_ctl_field_info
+},
+{"CFG_BLK_MSI_ENABLE", 0x20,
+ 1, 0, 0, 0,
+ 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY,
+ ARRAY_SIZE(cfg_blk_msi_enable_field_info),
+ cfg_blk_msi_enable_field_info
+},
+{"CFG_AXI_USER_MAX_PLD_SIZE", 0x40,
+ 1, 0, 0, 0,
+ 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY,
+ ARRAY_SIZE(cfg_axi_user_max_pld_size_field_info),
+ cfg_axi_user_max_pld_size_field_info
+},
+{"CFG_AXI_USER_MAX_READ_REQ_SIZE", 0x44,
+ 1, 0, 0, 0,
+ 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY,
+ ARRAY_SIZE(cfg_axi_user_max_read_req_size_field_info),
+ cfg_axi_user_max_read_req_size_field_info
+},
+{"CFG_BLK_MISC_CTL", 0x4c,
+ 1, 0, 0, 0,
+ 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY,
+ ARRAY_SIZE(cfg_blk_misc_ctl_field_info),
+ cfg_blk_misc_ctl_field_info
+},
+{"CFG_PL_CRED_CTL", 0x68,
+ 1, 0, 0, 0,
+ 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY,
+ ARRAY_SIZE(cfg_pl_cred_ctl_field_info),
+ cfg_pl_cred_ctl_field_info
+},
+{"CFG_BLK_SCRATCH", 0x80,
+ 1, 0, 0, 0,
+ 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY,
+ ARRAY_SIZE(cfg_blk_scratch_field_info),
+ cfg_blk_scratch_field_info
+},
+{"CFG_GIC", 0xa0,
+ 1, 0, 0, 0,
+ 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY,
+ ARRAY_SIZE(cfg_gic_field_info),
+ cfg_gic_field_info
+},
+{"RAM_SBE_MSK_1_A", 0xe0,
+ 1, 0, 0, 0,
+ 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY,
+ ARRAY_SIZE(ram_sbe_msk_1_a_field_info),
+ ram_sbe_msk_1_a_field_info
+},
+{"RAM_SBE_STS_1_A", 0xe4,
+ 1, 0, 0, 0,
+ 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY,
+ ARRAY_SIZE(ram_sbe_sts_1_a_field_info),
+ ram_sbe_sts_1_a_field_info
+},
+{"RAM_DBE_MSK_1_A", 0xe8,
+ 1, 0, 0, 0,
+ 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY,
+ ARRAY_SIZE(ram_dbe_msk_1_a_field_info),
+ ram_dbe_msk_1_a_field_info
+},
+{"RAM_DBE_STS_1_A", 0xec,
+ 1, 0, 0, 0,
+ 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY,
+ ARRAY_SIZE(ram_dbe_sts_1_a_field_info),
+ ram_dbe_sts_1_a_field_info
+},
+{"RAM_SBE_MSK_A", 0xf0,
+ 1, 0, 0, 0,
+ 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY,
+ ARRAY_SIZE(ram_sbe_msk_a_field_info),
+ ram_sbe_msk_a_field_info
+},
+{"RAM_SBE_STS_A", 0xf4,
+ 1, 0, 0, 0,
+ 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY,
+ ARRAY_SIZE(ram_sbe_sts_a_field_info),
+ ram_sbe_sts_a_field_info
+},
+{"RAM_DBE_MSK_A", 0xf8,
+ 1, 0, 0, 0,
+ 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY,
+ ARRAY_SIZE(ram_dbe_msk_a_field_info),
+ ram_dbe_msk_a_field_info
+},
+{"RAM_DBE_STS_A", 0xfc,
+ 1, 0, 0, 0,
+ 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY,
+ ARRAY_SIZE(ram_dbe_sts_a_field_info),
+ ram_dbe_sts_a_field_info
+},
+{"GLBL2_IDENTIFIER", 0x100,
+ 1, 0, 0, 0,
+ 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY,
+ ARRAY_SIZE(glbl2_identifier_field_info),
+ glbl2_identifier_field_info
+},
+{"GLBL2_CHANNEL_INST", 0x114,
+ 1, 0, 0, 0,
+ 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY,
+ ARRAY_SIZE(glbl2_channel_inst_field_info),
+ glbl2_channel_inst_field_info
+},
+{"GLBL2_CHANNEL_MDMA", 0x118,
+ 1, 0, 0, 0,
+ 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY,
+ ARRAY_SIZE(glbl2_channel_mdma_field_info),
+ glbl2_channel_mdma_field_info
+},
+{"GLBL2_CHANNEL_STRM", 0x11c,
+ 1, 0, 0, 0,
+ 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY,
+ ARRAY_SIZE(glbl2_channel_strm_field_info),
+ glbl2_channel_strm_field_info
+},
+{"GLBL2_CHANNEL_CAP", 0x120,
+ 1, 0, 0, 0,
+ 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY,
+ ARRAY_SIZE(glbl2_channel_cap_field_info),
+ glbl2_channel_cap_field_info
+},
+{"GLBL2_CHANNEL_PASID_CAP", 0x128,
+ 1, 0, 0, 0,
+ 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY,
+ ARRAY_SIZE(glbl2_channel_pasid_cap_field_info),
+ glbl2_channel_pasid_cap_field_info
+},
+{"GLBL2_SYSTEM_ID", 0x130,
+ 1, 0, 0, 0,
+ 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY,
+ ARRAY_SIZE(glbl2_system_id_field_info),
+ glbl2_system_id_field_info
+},
+{"GLBL2_MISC_CAP", 0x134,
+ 1, 0, 0, 0,
+ 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY,
+ ARRAY_SIZE(glbl2_misc_cap_field_info),
+ glbl2_misc_cap_field_info
+},
+{"GLBL2_RRQ_BRG_THROT", 0x158,
+ 1, 0, 0, 0,
+ 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY,
+ ARRAY_SIZE(glbl2_rrq_brg_throt_field_info),
+ glbl2_rrq_brg_throt_field_info
+},
+{"GLBL2_RRQ_PCIE_THROT", 0x15c,
+ 1, 0, 0, 0,
+ 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY,
+ ARRAY_SIZE(glbl2_rrq_pcie_throt_field_info),
+ glbl2_rrq_pcie_throt_field_info
+},
+{"GLBL2_RRQ_AXIMM_THROT", 0x160,
+ 1, 0, 0, 0,
+ 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY,
+ ARRAY_SIZE(glbl2_rrq_aximm_throt_field_info),
+ glbl2_rrq_aximm_throt_field_info
+},
+{"GLBL2_RRQ_PCIE_LAT0", 0x164,
+ 1, 0, 0, 0,
+ 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY,
+ ARRAY_SIZE(glbl2_rrq_pcie_lat0_field_info),
+ glbl2_rrq_pcie_lat0_field_info
+},
+{"GLBL2_RRQ_PCIE_LAT1", 0x168,
+ 1, 0, 0, 0,
+ 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY,
+ ARRAY_SIZE(glbl2_rrq_pcie_lat1_field_info),
+ glbl2_rrq_pcie_lat1_field_info
+},
+{"GLBL2_RRQ_AXIMM_LAT0", 0x16c,
+ 1, 0, 0, 0,
+ 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY,
+ ARRAY_SIZE(glbl2_rrq_aximm_lat0_field_info),
+ glbl2_rrq_aximm_lat0_field_info
+},
+{"GLBL2_RRQ_AXIMM_LAT1", 0x170,
+ 1, 0, 0, 0,
+ 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY,
+ ARRAY_SIZE(glbl2_rrq_aximm_lat1_field_info),
+ glbl2_rrq_aximm_lat1_field_info
+},
+{"GLBL2_DBG_PCIE_RQ0", 0x1b8,
+ 1, 0, 0, 0,
+ 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY,
+ ARRAY_SIZE(glbl2_dbg_pcie_rq0_field_info),
+ glbl2_dbg_pcie_rq0_field_info
+},
+{"GLBL2_DBG_PCIE_RQ1", 0x1bc,
+ 1, 0, 0, 0,
+ 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY,
+ ARRAY_SIZE(glbl2_dbg_pcie_rq1_field_info),
+ glbl2_dbg_pcie_rq1_field_info
+},
+{"GLBL2_DBG_AXIMM_WR0", 0x1c0,
+ 1, 0, 0, 0,
+ 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY,
+ ARRAY_SIZE(glbl2_dbg_aximm_wr0_field_info),
+ glbl2_dbg_aximm_wr0_field_info
+},
+{"GLBL2_DBG_AXIMM_WR1", 0x1c4,
+ 1, 0, 0, 0,
+ 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY,
+ ARRAY_SIZE(glbl2_dbg_aximm_wr1_field_info),
+ glbl2_dbg_aximm_wr1_field_info
+},
+{"GLBL2_DBG_AXIMM_RD0", 0x1c8,
+ 1, 0, 0, 0,
+ 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY,
+ ARRAY_SIZE(glbl2_dbg_aximm_rd0_field_info),
+ glbl2_dbg_aximm_rd0_field_info
+},
+{"GLBL2_DBG_AXIMM_RD1", 0x1cc,
+ 1, 0, 0, 0,
+ 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY,
+ ARRAY_SIZE(glbl2_dbg_aximm_rd1_field_info),
+ glbl2_dbg_aximm_rd1_field_info
+},
+{"GLBL2_DBG_FAB0", 0x1d0,
+ 1, 0, 0, 0,
+ 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY,
+ ARRAY_SIZE(glbl2_dbg_fab0_field_info),
+ glbl2_dbg_fab0_field_info
+},
+{"GLBL2_DBG_FAB1", 0x1d4,
+ 1, 0, 0, 0,
+ 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY,
+ ARRAY_SIZE(glbl2_dbg_fab1_field_info),
+ glbl2_dbg_fab1_field_info
+},
+{"GLBL2_DBG_MATCH_SEL", 0x1f4,
+ 1, 0, 0, 0,
+ 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY,
+ ARRAY_SIZE(glbl2_dbg_match_sel_field_info),
+ glbl2_dbg_match_sel_field_info
+},
+{"GLBL2_DBG_MATCH_MSK", 0x1f8,
+ 1, 0, 0, 0,
+ 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY,
+ ARRAY_SIZE(glbl2_dbg_match_msk_field_info),
+ glbl2_dbg_match_msk_field_info
+},
+{"GLBL2_DBG_MATCH_PAT", 0x1fc,
+ 1, 0, 0, 0,
+ 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY,
+ ARRAY_SIZE(glbl2_dbg_match_pat_field_info),
+ glbl2_dbg_match_pat_field_info
+},
+{"GLBL_RNG_SZ_1", 0x204,
+ 1, 0, 0, 0,
+ 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_VF,
+ ARRAY_SIZE(glbl_rng_sz_1_field_info),
+ glbl_rng_sz_1_field_info
+},
+{"GLBL_RNG_SZ_2", 0x208,
+ 1, 0, 0, 0,
+ 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_VF,
+ ARRAY_SIZE(glbl_rng_sz_2_field_info),
+ glbl_rng_sz_2_field_info
+},
+{"GLBL_RNG_SZ_3", 0x20c,
+ 1, 0, 0, 0,
+ 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_VF,
+ ARRAY_SIZE(glbl_rng_sz_3_field_info),
+ glbl_rng_sz_3_field_info
+},
+{"GLBL_RNG_SZ_4", 0x210,
+ 1, 0, 0, 0,
+ 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_VF,
+ ARRAY_SIZE(glbl_rng_sz_4_field_info),
+ glbl_rng_sz_4_field_info
+},
+{"GLBL_RNG_SZ_5", 0x214,
+ 1, 0, 0, 0,
+ 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_VF,
+ ARRAY_SIZE(glbl_rng_sz_5_field_info),
+ glbl_rng_sz_5_field_info
+},
+{"GLBL_RNG_SZ_6", 0x218,
+ 1, 0, 0, 0,
+ 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_VF,
+ ARRAY_SIZE(glbl_rng_sz_6_field_info),
+ glbl_rng_sz_6_field_info
+},
+{"GLBL_RNG_SZ_7", 0x21c,
+ 1, 0, 0, 0,
+ 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_VF,
+ ARRAY_SIZE(glbl_rng_sz_7_field_info),
+ glbl_rng_sz_7_field_info
+},
+{"GLBL_RNG_SZ_8", 0x220,
+ 1, 0, 0, 0,
+ 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_VF,
+ ARRAY_SIZE(glbl_rng_sz_8_field_info),
+ glbl_rng_sz_8_field_info
+},
+{"GLBL_RNG_SZ_9", 0x224,
+ 1, 0, 0, 0,
+ 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_VF,
+ ARRAY_SIZE(glbl_rng_sz_9_field_info),
+ glbl_rng_sz_9_field_info
+},
+{"GLBL_RNG_SZ_A", 0x228,
+ 1, 0, 0, 0,
+ 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_VF,
+ ARRAY_SIZE(glbl_rng_sz_a_field_info),
+ glbl_rng_sz_a_field_info
+},
+{"GLBL_RNG_SZ_B", 0x22c,
+ 1, 0, 0, 0,
+ 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_VF,
+ ARRAY_SIZE(glbl_rng_sz_b_field_info),
+ glbl_rng_sz_b_field_info
+},
+{"GLBL_RNG_SZ_C", 0x230,
+ 1, 0, 0, 0,
+ 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_VF,
+ ARRAY_SIZE(glbl_rng_sz_c_field_info),
+ glbl_rng_sz_c_field_info
+},
+{"GLBL_RNG_SZ_D", 0x234,
+ 1, 0, 0, 0,
+ 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_VF,
+ ARRAY_SIZE(glbl_rng_sz_d_field_info),
+ glbl_rng_sz_d_field_info
+},
+{"GLBL_RNG_SZ_E", 0x238,
+ 1, 0, 0, 0,
+ 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_VF,
+ ARRAY_SIZE(glbl_rng_sz_e_field_info),
+ glbl_rng_sz_e_field_info
+},
+{"GLBL_RNG_SZ_F", 0x23c,
+ 1, 0, 0, 0,
+ 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_VF,
+ ARRAY_SIZE(glbl_rng_sz_f_field_info),
+ glbl_rng_sz_f_field_info
+},
+{"GLBL_RNG_SZ_10", 0x240,
+ 1, 0, 0, 0,
+ 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_VF,
+ ARRAY_SIZE(glbl_rng_sz_10_field_info),
+ glbl_rng_sz_10_field_info
+},
+{"GLBL_ERR_STAT", 0x248,
+ 1, 0, 0, 0,
+ 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_VF,
+ ARRAY_SIZE(glbl_err_stat_field_info),
+ glbl_err_stat_field_info
+},
+{"GLBL_ERR_MASK", 0x24c,
+ 1, 0, 0, 0,
+ 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_VF,
+ ARRAY_SIZE(glbl_err_mask_field_info),
+ glbl_err_mask_field_info
+},
+{"GLBL_DSC_CFG", 0x250,
+ 1, 0, 0, 0,
+ 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_VF,
+ ARRAY_SIZE(glbl_dsc_cfg_field_info),
+ glbl_dsc_cfg_field_info
+},
+{"GLBL_DSC_ERR_STS", 0x254,
+ 1, 0, 0, 0,
+ 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_VF,
+ ARRAY_SIZE(glbl_dsc_err_sts_field_info),
+ glbl_dsc_err_sts_field_info
+},
+{"GLBL_DSC_ERR_MSK", 0x258,
+ 1, 0, 0, 0,
+ 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_VF,
+ ARRAY_SIZE(glbl_dsc_err_msk_field_info),
+ glbl_dsc_err_msk_field_info
+},
+{"GLBL_DSC_ERR_LOG0", 0x25c,
+ 1, 0, 0, 0,
+ 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_VF,
+ ARRAY_SIZE(glbl_dsc_err_log0_field_info),
+ glbl_dsc_err_log0_field_info
+},
+{"GLBL_DSC_ERR_LOG1", 0x260,
+ 1, 0, 0, 0,
+ 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_VF,
+ ARRAY_SIZE(glbl_dsc_err_log1_field_info),
+ glbl_dsc_err_log1_field_info
+},
+{"GLBL_TRQ_ERR_STS", 0x264,
+ 1, 0, 0, 0,
+ 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_VF,
+ ARRAY_SIZE(glbl_trq_err_sts_field_info),
+ glbl_trq_err_sts_field_info
+},
+{"GLBL_TRQ_ERR_MSK", 0x268,
+ 1, 0, 0, 0,
+ 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_VF,
+ ARRAY_SIZE(glbl_trq_err_msk_field_info),
+ glbl_trq_err_msk_field_info
+},
+{"GLBL_TRQ_ERR_LOG", 0x26c,
+ 1, 0, 0, 0,
+ 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_VF,
+ ARRAY_SIZE(glbl_trq_err_log_field_info),
+ glbl_trq_err_log_field_info
+},
+{"GLBL_DSC_DBG_DAT0", 0x270,
+ 1, 0, 0, 0,
+ 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_VF,
+ ARRAY_SIZE(glbl_dsc_dbg_dat0_field_info),
+ glbl_dsc_dbg_dat0_field_info
+},
+{"GLBL_DSC_DBG_DAT1", 0x274,
+ 1, 0, 0, 0,
+ 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_VF,
+ ARRAY_SIZE(glbl_dsc_dbg_dat1_field_info),
+ glbl_dsc_dbg_dat1_field_info
+},
+{"GLBL_DSC_DBG_CTL", 0x278,
+ 1, 0, 0, 0,
+ 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_VF,
+ ARRAY_SIZE(glbl_dsc_dbg_ctl_field_info),
+ glbl_dsc_dbg_ctl_field_info
+},
+{"GLBL_DSC_ERR_LOG2", 0x27c,
+ 1, 0, 0, 0,
+ 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_VF,
+ ARRAY_SIZE(glbl_dsc_err_log2_field_info),
+ glbl_dsc_err_log2_field_info
+},
+{"GLBL_GLBL_INTERRUPT_CFG", 0x2c4,
+ 1, 0, 0, 0,
+ 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_VF,
+ ARRAY_SIZE(glbl_glbl_interrupt_cfg_field_info),
+ glbl_glbl_interrupt_cfg_field_info
+},
+{"GLBL_VCH_HOST_PROFILE", 0x2c8,
+ 1, 0, 0, 0,
+ 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_VF,
+ ARRAY_SIZE(glbl_vch_host_profile_field_info),
+ glbl_vch_host_profile_field_info
+},
+{"GLBL_BRIDGE_HOST_PROFILE", 0x308,
+ 1, 0, 0, 0,
+ 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_VF,
+ ARRAY_SIZE(glbl_bridge_host_profile_field_info),
+ glbl_bridge_host_profile_field_info
+},
+{"AXIMM_IRQ_DEST_ADDR", 0x30c,
+ 1, 0, 0, 0,
+ 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_VF,
+ ARRAY_SIZE(aximm_irq_dest_addr_field_info),
+ aximm_irq_dest_addr_field_info
+},
+{"FAB_ERR_LOG", 0x314,
+ 1, 0, 0, 0,
+ 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_VF,
+ ARRAY_SIZE(fab_err_log_field_info),
+ fab_err_log_field_info
+},
+{"GLBL_REQ_ERR_STS", 0x318,
1, 0, 0, 0,
0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY,
- ARRAY_SIZE(cfg_blk_identifier_field_info),
- cfg_blk_identifier_field_info
+ ARRAY_SIZE(glbl_req_err_sts_field_info),
+ glbl_req_err_sts_field_info
},
-{"CFG_BLK_PCIE_MAX_PLD_SIZE", 0x08,
+{"GLBL_REQ_ERR_MSK", 0x31c,
1, 0, 0, 0,
0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY,
- ARRAY_SIZE(cfg_blk_pcie_max_pld_size_field_info),
- cfg_blk_pcie_max_pld_size_field_info
+ ARRAY_SIZE(glbl_req_err_msk_field_info),
+ glbl_req_err_msk_field_info
},
-{"CFG_BLK_PCIE_MAX_READ_REQ_SIZE", 0x0c,
+{"GLBL_DSC_DBG_LAT0_A", 0x320,
1, 0, 0, 0,
0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY,
- ARRAY_SIZE(cfg_blk_pcie_max_read_req_size_field_info),
- cfg_blk_pcie_max_read_req_size_field_info
+ ARRAY_SIZE(glbl_dsc_dbg_lat0_a_field_info),
+ glbl_dsc_dbg_lat0_a_field_info
},
-{"CFG_BLK_SYSTEM_ID", 0x10,
+{"GLBL_DSC_DBG_LAT1_A", 0x324,
1, 0, 0, 0,
0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY,
- ARRAY_SIZE(cfg_blk_system_id_field_info),
- cfg_blk_system_id_field_info
+ ARRAY_SIZE(glbl_dsc_dbg_lat1_a_field_info),
+ glbl_dsc_dbg_lat1_a_field_info
},
-{"CFG_BLK_MSIX_ENABLE", 0x014,
+{"GLBL_DSC_CRD_CTR0_A", 0x328,
1, 0, 0, 0,
0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY,
- ARRAY_SIZE(cfg_blk_msix_enable_field_info),
- cfg_blk_msix_enable_field_info
+ ARRAY_SIZE(glbl_dsc_crd_ctr0_a_field_info),
+ glbl_dsc_crd_ctr0_a_field_info
},
-{"CFG_PCIE_DATA_WIDTH", 0x18,
+{"GLBL_DSC_CRD_CTR1_A", 0x32c,
1, 0, 0, 0,
0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY,
- ARRAY_SIZE(cfg_pcie_data_width_field_info),
- cfg_pcie_data_width_field_info
+ ARRAY_SIZE(glbl_dsc_crd_ctr1_a_field_info),
+ glbl_dsc_crd_ctr1_a_field_info
},
-{"CFG_PCIE_CTL", 0x1c,
+{"GLBL_DSC_CRD_CTR2_A", 0x330,
1, 0, 0, 0,
0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY,
- ARRAY_SIZE(cfg_pcie_ctl_field_info),
- cfg_pcie_ctl_field_info
+ ARRAY_SIZE(glbl_dsc_crd_ctr2_a_field_info),
+ glbl_dsc_crd_ctr2_a_field_info
},
-{"CFG_BLK_MSI_ENABLE", 0x20,
+{"GLBL_DSC_CRD_CTR3_A", 0x334,
1, 0, 0, 0,
0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY,
- ARRAY_SIZE(cfg_blk_msi_enable_field_info),
- cfg_blk_msi_enable_field_info
+ ARRAY_SIZE(glbl_dsc_crd_ctr3_a_field_info),
+ glbl_dsc_crd_ctr3_a_field_info
},
-{"CFG_AXI_USER_MAX_PLD_SIZE", 0x40,
+{"GLBL_DSC_IMM_CRD_CTR0_A", 0x338,
1, 0, 0, 0,
0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY,
- ARRAY_SIZE(cfg_axi_user_max_pld_size_field_info),
- cfg_axi_user_max_pld_size_field_info
+ ARRAY_SIZE(glbl_dsc_imm_crd_ctr0_a_field_info),
+ glbl_dsc_imm_crd_ctr0_a_field_info
},
-{"CFG_AXI_USER_MAX_READ_REQ_SIZE", 0x44,
+{"GLBL_DSC_IMM_CRD_CTR1_A", 0x33c,
1, 0, 0, 0,
0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY,
- ARRAY_SIZE(cfg_axi_user_max_read_req_size_field_info),
- cfg_axi_user_max_read_req_size_field_info
+ ARRAY_SIZE(glbl_dsc_imm_crd_ctr1_a_field_info),
+ glbl_dsc_imm_crd_ctr1_a_field_info
},
-{"CFG_BLK_MISC_CTL", 0x4c,
+{"GLBL_DSC_IMM_CRD_CTR2_A", 0x340,
1, 0, 0, 0,
0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY,
- ARRAY_SIZE(cfg_blk_misc_ctl_field_info),
- cfg_blk_misc_ctl_field_info
+ ARRAY_SIZE(glbl_dsc_imm_crd_ctr2_a_field_info),
+ glbl_dsc_imm_crd_ctr2_a_field_info
},
-{"CFG_PL_CRED_CTL", 0x68,
+{"GLBL_DSC_IMM_CRD_CTR3_A", 0x344,
1, 0, 0, 0,
0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY,
- ARRAY_SIZE(cfg_pl_cred_ctl_field_info),
- cfg_pl_cred_ctl_field_info
+ ARRAY_SIZE(glbl_dsc_imm_crd_ctr3_a_field_info),
+ glbl_dsc_imm_crd_ctr3_a_field_info
},
-{"CFG_BLK_SCRATCH", 0x80,
+{"GLBL_DSC_H2C_OUT_CTR0_A", 0x348,
1, 0, 0, 0,
0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY,
- ARRAY_SIZE(cfg_blk_scratch_field_info),
- cfg_blk_scratch_field_info
+ ARRAY_SIZE(glbl_dsc_h2c_out_ctr0_a_field_info),
+ glbl_dsc_h2c_out_ctr0_a_field_info
},
-{"CFG_GIC", 0xa0,
+{"GLBL_DSC_H2C_OUT_CTR1_A", 0x34c,
1, 0, 0, 0,
0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY,
- ARRAY_SIZE(cfg_gic_field_info),
- cfg_gic_field_info
+ ARRAY_SIZE(glbl_dsc_h2c_out_ctr1_a_field_info),
+ glbl_dsc_h2c_out_ctr1_a_field_info
},
-{"RAM_SBE_MSK_1_A", 0xe0,
+{"GLBL_DSC_H2C_OUT_CTR2_A", 0x350,
1, 0, 0, 0,
0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY,
- ARRAY_SIZE(ram_sbe_msk_1_a_field_info),
- ram_sbe_msk_1_a_field_info
+ ARRAY_SIZE(glbl_dsc_h2c_out_ctr2_a_field_info),
+ glbl_dsc_h2c_out_ctr2_a_field_info
},
-{"RAM_SBE_STS_1_A", 0xe4,
+{"GLBL_DSC_H2C_OUT_CTR3_A", 0x354,
1, 0, 0, 0,
0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY,
- ARRAY_SIZE(ram_sbe_sts_1_a_field_info),
- ram_sbe_sts_1_a_field_info
+ ARRAY_SIZE(glbl_dsc_h2c_out_ctr3_a_field_info),
+ glbl_dsc_h2c_out_ctr3_a_field_info
},
-{"RAM_DBE_MSK_1_A", 0xe8,
+{"GLBL_DSC_C2H_OUT_CTR0_A", 0x358,
1, 0, 0, 0,
0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY,
- ARRAY_SIZE(ram_dbe_msk_1_a_field_info),
- ram_dbe_msk_1_a_field_info
+ ARRAY_SIZE(glbl_dsc_c2h_out_ctr0_a_field_info),
+ glbl_dsc_c2h_out_ctr0_a_field_info
},
-{"RAM_DBE_STS_1_A", 0xec,
+{"GLBL_DSC_C2H_OUT_CTR1_A", 0x35c,
1, 0, 0, 0,
0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY,
- ARRAY_SIZE(ram_dbe_sts_1_a_field_info),
- ram_dbe_sts_1_a_field_info
+ ARRAY_SIZE(glbl_dsc_c2h_out_ctr1_a_field_info),
+ glbl_dsc_c2h_out_ctr1_a_field_info
},
-{"RAM_SBE_MSK_A", 0xf0,
+{"GLBL_DSC_C2H_OUT_CTR2_A", 0x360,
1, 0, 0, 0,
0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY,
- ARRAY_SIZE(ram_sbe_msk_a_field_info),
- ram_sbe_msk_a_field_info
+ ARRAY_SIZE(glbl_dsc_c2h_out_ctr2_a_field_info),
+ glbl_dsc_c2h_out_ctr2_a_field_info
},
-{"RAM_SBE_STS_A", 0xf4,
+{"GLBL_DSC_C2H_OUT_CTR3_A", 0x364,
1, 0, 0, 0,
0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY,
- ARRAY_SIZE(ram_sbe_sts_a_field_info),
- ram_sbe_sts_a_field_info
+ ARRAY_SIZE(glbl_dsc_c2h_out_ctr3_a_field_info),
+ glbl_dsc_c2h_out_ctr3_a_field_info
},
-{"RAM_DBE_MSK_A", 0xf8,
+{"T", 0x368,
1, 0, 0, 0,
0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY,
- ARRAY_SIZE(ram_dbe_msk_a_field_info),
- ram_dbe_msk_a_field_info
+ ARRAY_SIZE(t_field_info),
+ t_field_info
},
-{"RAM_DBE_STS_A", 0xfc,
+{"GLBL_PERF_CNTR_CTL_A1", 0x36c,
1, 0, 0, 0,
0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY,
- ARRAY_SIZE(ram_dbe_sts_a_field_info),
- ram_dbe_sts_a_field_info
+ ARRAY_SIZE(glbl_perf_cntr_ctl_a1_field_info),
+ glbl_perf_cntr_ctl_a1_field_info
},
-{"GLBL2_IDENTIFIER", 0x100,
+{"GLBL_FREE_CNT_A0", 0x370,
1, 0, 0, 0,
0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY,
- ARRAY_SIZE(glbl2_identifier_field_info),
- glbl2_identifier_field_info
+ ARRAY_SIZE(glbl_free_cnt_a0_field_info),
+ glbl_free_cnt_a0_field_info
},
-{"GLBL2_CHANNEL_INST", 0x114,
+{"GLBL_FREE_CNT_A1", 0x374,
1, 0, 0, 0,
0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY,
- ARRAY_SIZE(glbl2_channel_inst_field_info),
- glbl2_channel_inst_field_info
+ ARRAY_SIZE(glbl_free_cnt_a1_field_info),
+ glbl_free_cnt_a1_field_info
},
-{"GLBL2_CHANNEL_MDMA", 0x118,
+{"GLBL_AXIS_H2C_CNT_A0", 0x378,
1, 0, 0, 0,
0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY,
- ARRAY_SIZE(glbl2_channel_mdma_field_info),
- glbl2_channel_mdma_field_info
+ ARRAY_SIZE(glbl_axis_h2c_cnt_a0_field_info),
+ glbl_axis_h2c_cnt_a0_field_info
},
-{"GLBL2_CHANNEL_STRM", 0x11c,
+{"GLBL_AXIS_H2C_CNT_A1", 0x37c,
1, 0, 0, 0,
0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY,
- ARRAY_SIZE(glbl2_channel_strm_field_info),
- glbl2_channel_strm_field_info
+ ARRAY_SIZE(glbl_axis_h2c_cnt_a1_field_info),
+ glbl_axis_h2c_cnt_a1_field_info
},
-{"GLBL2_CHANNEL_CAP", 0x120,
+{"GLBL_AXIS_H2C_CNT_A2", 0x380,
1, 0, 0, 0,
0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY,
- ARRAY_SIZE(glbl2_channel_cap_field_info),
- glbl2_channel_cap_field_info
+ ARRAY_SIZE(glbl_axis_h2c_cnt_a2_field_info),
+ glbl_axis_h2c_cnt_a2_field_info
},
-{"GLBL2_CHANNEL_PASID_CAP", 0x128,
+{"GLBL_AXIS_H2C_CNT_A3", 0x384,
1, 0, 0, 0,
0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY,
- ARRAY_SIZE(glbl2_channel_pasid_cap_field_info),
- glbl2_channel_pasid_cap_field_info
+ ARRAY_SIZE(glbl_axis_h2c_cnt_a3_field_info),
+ glbl_axis_h2c_cnt_a3_field_info
},
-{"GLBL2_SYSTEM_ID", 0x130,
+{"GLBL_AXIS_H2C_CNT_A4", 0x388,
1, 0, 0, 0,
0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY,
- ARRAY_SIZE(glbl2_system_id_field_info),
- glbl2_system_id_field_info
+ ARRAY_SIZE(glbl_axis_h2c_cnt_a4_field_info),
+ glbl_axis_h2c_cnt_a4_field_info
},
-{"GLBL2_MISC_CAP", 0x134,
+{"GLBL_AXIS_H2C_CNT_A5", 0x38c,
1, 0, 0, 0,
0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY,
- ARRAY_SIZE(glbl2_misc_cap_field_info),
- glbl2_misc_cap_field_info
+ ARRAY_SIZE(glbl_axis_h2c_cnt_a5_field_info),
+ glbl_axis_h2c_cnt_a5_field_info
},
-{"GLBL2_DBG_PCIE_RQ0", 0x1b8,
+{"GLBL_AXIS_C2H_CNT_A0", 0x390,
1, 0, 0, 0,
0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY,
- ARRAY_SIZE(glbl2_dbg_pcie_rq0_field_info),
- glbl2_dbg_pcie_rq0_field_info
+ ARRAY_SIZE(glbl_axis_c2h_cnt_a0_field_info),
+ glbl_axis_c2h_cnt_a0_field_info
},
-{"GLBL2_DBG_PCIE_RQ1", 0x1bc,
+{"GLBL_AXIS_C2H_CNT_A1", 0x394,
1, 0, 0, 0,
0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY,
- ARRAY_SIZE(glbl2_dbg_pcie_rq1_field_info),
- glbl2_dbg_pcie_rq1_field_info
+ ARRAY_SIZE(glbl_axis_c2h_cnt_a1_field_info),
+ glbl_axis_c2h_cnt_a1_field_info
},
-{"GLBL2_DBG_AXIMM_WR0", 0x1c0,
+{"GLBL_AXIS_C2H_CNT_A2", 0x398,
1, 0, 0, 0,
0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY,
- ARRAY_SIZE(glbl2_dbg_aximm_wr0_field_info),
- glbl2_dbg_aximm_wr0_field_info
+ ARRAY_SIZE(glbl_axis_c2h_cnt_a2_field_info),
+ glbl_axis_c2h_cnt_a2_field_info
},
-{"GLBL2_DBG_AXIMM_WR1", 0x1c4,
+{"GLBL_AXIS_C2H_CNT_A3", 0x39c,
1, 0, 0, 0,
0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY,
- ARRAY_SIZE(glbl2_dbg_aximm_wr1_field_info),
- glbl2_dbg_aximm_wr1_field_info
+ ARRAY_SIZE(glbl_axis_c2h_cnt_a3_field_info),
+ glbl_axis_c2h_cnt_a3_field_info
},
-{"GLBL2_DBG_AXIMM_RD0", 0x1c8,
+{"GLBL_AXIS_C2H_CNT_A4", 0x3a0,
1, 0, 0, 0,
0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY,
- ARRAY_SIZE(glbl2_dbg_aximm_rd0_field_info),
- glbl2_dbg_aximm_rd0_field_info
+ ARRAY_SIZE(glbl_axis_c2h_cnt_a4_field_info),
+ glbl_axis_c2h_cnt_a4_field_info
},
-{"GLBL2_DBG_AXIMM_RD1", 0x1cc,
+{"GLBL_AXIS_C2H_CNT_A5", 0x3a4,
1, 0, 0, 0,
0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY,
- ARRAY_SIZE(glbl2_dbg_aximm_rd1_field_info),
- glbl2_dbg_aximm_rd1_field_info
+ ARRAY_SIZE(glbl_axis_c2h_cnt_a5_field_info),
+ glbl_axis_c2h_cnt_a5_field_info
},
-{"GLBL2_DBG_FAB0", 0x1d0,
+{"GLBL_M_AXI_WR_CNT_A0", 0x3a8,
1, 0, 0, 0,
0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY,
- ARRAY_SIZE(glbl2_dbg_fab0_field_info),
- glbl2_dbg_fab0_field_info
+ ARRAY_SIZE(glbl_m_axi_wr_cnt_a0_field_info),
+ glbl_m_axi_wr_cnt_a0_field_info
},
-{"GLBL2_DBG_FAB1", 0x1d4,
+{"GLBL_M_AXI_WR_CNT_A1", 0x3ac,
1, 0, 0, 0,
0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY,
- ARRAY_SIZE(glbl2_dbg_fab1_field_info),
- glbl2_dbg_fab1_field_info
+ ARRAY_SIZE(glbl_m_axi_wr_cnt_a1_field_info),
+ glbl_m_axi_wr_cnt_a1_field_info
},
-{"GLBL2_DBG_MATCH_SEL", 0x1f4,
+{"GLBL_M_AXI_WR_CNT_A2", 0x3b0,
1, 0, 0, 0,
0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY,
- ARRAY_SIZE(glbl2_dbg_match_sel_field_info),
- glbl2_dbg_match_sel_field_info
+ ARRAY_SIZE(glbl_m_axi_wr_cnt_a2_field_info),
+ glbl_m_axi_wr_cnt_a2_field_info
},
-{"GLBL2_DBG_MATCH_MSK", 0x1f8,
+{"GLBL_M_AXI_WR_CNT_A3", 0x3b4,
1, 0, 0, 0,
0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY,
- ARRAY_SIZE(glbl2_dbg_match_msk_field_info),
- glbl2_dbg_match_msk_field_info
+ ARRAY_SIZE(glbl_m_axi_wr_cnt_a3_field_info),
+ glbl_m_axi_wr_cnt_a3_field_info
},
-{"GLBL2_DBG_MATCH_PAT", 0x1fc,
+{"GLBL_M_AXI_WR_CNT_A4", 0x3b8,
1, 0, 0, 0,
0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY,
- ARRAY_SIZE(glbl2_dbg_match_pat_field_info),
- glbl2_dbg_match_pat_field_info
+ ARRAY_SIZE(glbl_m_axi_wr_cnt_a4_field_info),
+ glbl_m_axi_wr_cnt_a4_field_info
},
-{"GLBL_RNG_SZ_1", 0x204,
+{"GLBL_M_AXI_WR_CNT_A5", 0x3bc,
1, 0, 0, 0,
- 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_VF,
- ARRAY_SIZE(glbl_rng_sz_1_field_info),
- glbl_rng_sz_1_field_info
+ 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY,
+ ARRAY_SIZE(glbl_m_axi_wr_cnt_a5_field_info),
+ glbl_m_axi_wr_cnt_a5_field_info
},
-{"GLBL_RNG_SZ_2", 0x208,
+{"GLBL_M_AXI_RD_CNT_A0", 0x3c0,
1, 0, 0, 0,
- 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_VF,
- ARRAY_SIZE(glbl_rng_sz_2_field_info),
- glbl_rng_sz_2_field_info
+ 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY,
+ ARRAY_SIZE(glbl_m_axi_rd_cnt_a0_field_info),
+ glbl_m_axi_rd_cnt_a0_field_info
},
-{"GLBL_RNG_SZ_3", 0x20c,
+{"GLBL_M_AXI_RD_CNT_A1", 0x3c4,
1, 0, 0, 0,
- 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_VF,
- ARRAY_SIZE(glbl_rng_sz_3_field_info),
- glbl_rng_sz_3_field_info
+ 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY,
+ ARRAY_SIZE(glbl_m_axi_rd_cnt_a1_field_info),
+ glbl_m_axi_rd_cnt_a1_field_info
},
-{"GLBL_RNG_SZ_4", 0x210,
+{"GLBL_M_AXI_RD_CNT_A2", 0x3c8,
1, 0, 0, 0,
- 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_VF,
- ARRAY_SIZE(glbl_rng_sz_4_field_info),
- glbl_rng_sz_4_field_info
+ 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY,
+ ARRAY_SIZE(glbl_m_axi_rd_cnt_a2_field_info),
+ glbl_m_axi_rd_cnt_a2_field_info
},
-{"GLBL_RNG_SZ_5", 0x214,
+{"GLBL_M_AXI_RD_CNT_A3", 0x3cc,
1, 0, 0, 0,
- 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_VF,
- ARRAY_SIZE(glbl_rng_sz_5_field_info),
- glbl_rng_sz_5_field_info
+ 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY,
+ ARRAY_SIZE(glbl_m_axi_rd_cnt_a3_field_info),
+ glbl_m_axi_rd_cnt_a3_field_info
},
-{"GLBL_RNG_SZ_6", 0x218,
+{"GLBL_M_AXI_RD_CNT_A4", 0x3d0,
1, 0, 0, 0,
- 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_VF,
- ARRAY_SIZE(glbl_rng_sz_6_field_info),
- glbl_rng_sz_6_field_info
+ 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY,
+ ARRAY_SIZE(glbl_m_axi_rd_cnt_a4_field_info),
+ glbl_m_axi_rd_cnt_a4_field_info
},
-{"GLBL_RNG_SZ_7", 0x21c,
+{"GLBL_M_AXI_RD_CNT_A5", 0x3d4,
1, 0, 0, 0,
- 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_VF,
- ARRAY_SIZE(glbl_rng_sz_7_field_info),
- glbl_rng_sz_7_field_info
+ 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY,
+ ARRAY_SIZE(glbl_m_axi_rd_cnt_a5_field_info),
+ glbl_m_axi_rd_cnt_a5_field_info
},
-{"GLBL_RNG_SZ_8", 0x220,
+{"GLBL_M_AXIB_WR_CNT_A0", 0x3d8,
1, 0, 0, 0,
- 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_VF,
- ARRAY_SIZE(glbl_rng_sz_8_field_info),
- glbl_rng_sz_8_field_info
+ 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY,
+ ARRAY_SIZE(glbl_m_axib_wr_cnt_a0_field_info),
+ glbl_m_axib_wr_cnt_a0_field_info
},
-{"GLBL_RNG_SZ_9", 0x224,
+{"GLBL_M_AXIB_WR_CNT_A1", 0x3dc,
1, 0, 0, 0,
- 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_VF,
- ARRAY_SIZE(glbl_rng_sz_9_field_info),
- glbl_rng_sz_9_field_info
+ 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY,
+ ARRAY_SIZE(glbl_m_axib_wr_cnt_a1_field_info),
+ glbl_m_axib_wr_cnt_a1_field_info
},
-{"GLBL_RNG_SZ_A", 0x228,
+{"GLBL_M_AXIB_WR_CNT_A2", 0x3e0,
1, 0, 0, 0,
- 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_VF,
- ARRAY_SIZE(glbl_rng_sz_a_field_info),
- glbl_rng_sz_a_field_info
+ 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY,
+ ARRAY_SIZE(glbl_m_axib_wr_cnt_a2_field_info),
+ glbl_m_axib_wr_cnt_a2_field_info
},
-{"GLBL_RNG_SZ_B", 0x22c,
+{"GLBL_M_AXIB_WR_CNT_A3", 0x3e4,
1, 0, 0, 0,
- 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_VF,
- ARRAY_SIZE(glbl_rng_sz_b_field_info),
- glbl_rng_sz_b_field_info
+ 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY,
+ ARRAY_SIZE(glbl_m_axib_wr_cnt_a3_field_info),
+ glbl_m_axib_wr_cnt_a3_field_info
},
-{"GLBL_RNG_SZ_C", 0x230,
+{"GLBL_M_AXIB_WR_CNT_A4", 0x3e8,
1, 0, 0, 0,
- 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_VF,
- ARRAY_SIZE(glbl_rng_sz_c_field_info),
- glbl_rng_sz_c_field_info
+ 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY,
+ ARRAY_SIZE(glbl_m_axib_wr_cnt_a4_field_info),
+ glbl_m_axib_wr_cnt_a4_field_info
},
-{"GLBL_RNG_SZ_D", 0x234,
+{"GLBL_M_AXIB_WR_CNT_A5", 0x3ec,
1, 0, 0, 0,
- 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_VF,
- ARRAY_SIZE(glbl_rng_sz_d_field_info),
- glbl_rng_sz_d_field_info
+ 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY,
+ ARRAY_SIZE(glbl_m_axib_wr_cnt_a5_field_info),
+ glbl_m_axib_wr_cnt_a5_field_info
},
-{"GLBL_RNG_SZ_E", 0x238,
+{"GLBL_M_AXIB_RD_CNT_A0", 0x3f0,
1, 0, 0, 0,
- 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_VF,
- ARRAY_SIZE(glbl_rng_sz_e_field_info),
- glbl_rng_sz_e_field_info
+ 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY,
+ ARRAY_SIZE(glbl_m_axib_rd_cnt_a0_field_info),
+ glbl_m_axib_rd_cnt_a0_field_info
},
-{"GLBL_RNG_SZ_F", 0x23c,
+{"GLBL_M_AXIB_RD_CNT_A1", 0x3f4,
1, 0, 0, 0,
- 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_VF,
- ARRAY_SIZE(glbl_rng_sz_f_field_info),
- glbl_rng_sz_f_field_info
+ 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY,
+ ARRAY_SIZE(glbl_m_axib_rd_cnt_a1_field_info),
+ glbl_m_axib_rd_cnt_a1_field_info
},
-{"GLBL_RNG_SZ_10", 0x240,
+{"GLBL_M_AXIB_RD_CNT_A2", 0x3f8,
1, 0, 0, 0,
- 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_VF,
- ARRAY_SIZE(glbl_rng_sz_10_field_info),
- glbl_rng_sz_10_field_info
+ 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY,
+ ARRAY_SIZE(glbl_m_axib_rd_cnt_a2_field_info),
+ glbl_m_axib_rd_cnt_a2_field_info
},
-{"GLBL_ERR_STAT", 0x248,
+{"GLBL_M_AXIB_RD_CNT_A3", 0x3fc,
1, 0, 0, 0,
- 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_VF,
- ARRAY_SIZE(glbl_err_stat_field_info),
- glbl_err_stat_field_info
+ 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY,
+ ARRAY_SIZE(glbl_m_axib_rd_cnt_a3_field_info),
+ glbl_m_axib_rd_cnt_a3_field_info
},
-{"GLBL_ERR_MASK", 0x24c,
+{"GLBL_M_AXIB_RD_CNT_A4", 0x400,
1, 0, 0, 0,
- 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_VF,
- ARRAY_SIZE(glbl_err_mask_field_info),
- glbl_err_mask_field_info
+ 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY,
+ ARRAY_SIZE(glbl_m_axib_rd_cnt_a4_field_info),
+ glbl_m_axib_rd_cnt_a4_field_info
},
-{"GLBL_DSC_CFG", 0x250,
+{"GLBL_M_AXIB_RD_CNT_A5", 0x404,
1, 0, 0, 0,
- 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_VF,
- ARRAY_SIZE(glbl_dsc_cfg_field_info),
- glbl_dsc_cfg_field_info
+ 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY,
+ ARRAY_SIZE(glbl_m_axib_rd_cnt_a5_field_info),
+ glbl_m_axib_rd_cnt_a5_field_info
},
-{"GLBL_DSC_ERR_STS", 0x254,
+{"GLBL_S_AXI_WR_CNT_A0", 0x408,
1, 0, 0, 0,
- 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_VF,
- ARRAY_SIZE(glbl_dsc_err_sts_field_info),
- glbl_dsc_err_sts_field_info
+ 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY,
+ ARRAY_SIZE(glbl_s_axi_wr_cnt_a0_field_info),
+ glbl_s_axi_wr_cnt_a0_field_info
},
-{"GLBL_DSC_ERR_MSK", 0x258,
+{"GLBL_S_AXI_WR_CNT_A1", 0x40c,
1, 0, 0, 0,
- 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_VF,
- ARRAY_SIZE(glbl_dsc_err_msk_field_info),
- glbl_dsc_err_msk_field_info
+ 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY,
+ ARRAY_SIZE(glbl_s_axi_wr_cnt_a1_field_info),
+ glbl_s_axi_wr_cnt_a1_field_info
},
-{"GLBL_DSC_ERR_LOG0", 0x25c,
+{"GLBL_S_AXI_WR_CNT_A2", 0x410,
1, 0, 0, 0,
- 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_VF,
- ARRAY_SIZE(glbl_dsc_err_log0_field_info),
- glbl_dsc_err_log0_field_info
+ 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY,
+ ARRAY_SIZE(glbl_s_axi_wr_cnt_a2_field_info),
+ glbl_s_axi_wr_cnt_a2_field_info
},
-{"GLBL_DSC_ERR_LOG1", 0x260,
+{"GLBL_S_AXI_WR_CNT_A3", 0x414,
1, 0, 0, 0,
- 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_VF,
- ARRAY_SIZE(glbl_dsc_err_log1_field_info),
- glbl_dsc_err_log1_field_info
+ 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY,
+ ARRAY_SIZE(glbl_s_axi_wr_cnt_a3_field_info),
+ glbl_s_axi_wr_cnt_a3_field_info
},
-{"GLBL_TRQ_ERR_STS", 0x264,
+{"GLBL_S_AXI_WR_CNT_A4", 0x418,
1, 0, 0, 0,
- 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_VF,
- ARRAY_SIZE(glbl_trq_err_sts_field_info),
- glbl_trq_err_sts_field_info
+ 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY,
+ ARRAY_SIZE(glbl_s_axi_wr_cnt_a4_field_info),
+ glbl_s_axi_wr_cnt_a4_field_info
},
-{"GLBL_TRQ_ERR_MSK", 0x268,
+{"GLBL_S_AXI_WR_CNT_A5", 0x41c,
1, 0, 0, 0,
- 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_VF,
- ARRAY_SIZE(glbl_trq_err_msk_field_info),
- glbl_trq_err_msk_field_info
+ 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY,
+ ARRAY_SIZE(glbl_s_axi_wr_cnt_a5_field_info),
+ glbl_s_axi_wr_cnt_a5_field_info
},
-{"GLBL_TRQ_ERR_LOG", 0x26c,
+{"GLBL_S_AXI_RD_CNT_A0", 0x420,
1, 0, 0, 0,
- 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_VF,
- ARRAY_SIZE(glbl_trq_err_log_field_info),
- glbl_trq_err_log_field_info
+ 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY,
+ ARRAY_SIZE(glbl_s_axi_rd_cnt_a0_field_info),
+ glbl_s_axi_rd_cnt_a0_field_info
},
-{"GLBL_DSC_DBG_DAT0", 0x270,
+{"GLBL_S_AXI_RD_CNT_A1", 0x424,
1, 0, 0, 0,
- 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_VF,
- ARRAY_SIZE(glbl_dsc_dbg_dat0_field_info),
- glbl_dsc_dbg_dat0_field_info
+ 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY,
+ ARRAY_SIZE(glbl_s_axi_rd_cnt_a1_field_info),
+ glbl_s_axi_rd_cnt_a1_field_info
},
-{"GLBL_DSC_DBG_DAT1", 0x274,
+{"GLBL_S_AXI_RD_CNT_A2", 0x428,
1, 0, 0, 0,
- 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_VF,
- ARRAY_SIZE(glbl_dsc_dbg_dat1_field_info),
- glbl_dsc_dbg_dat1_field_info
+ 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY,
+ ARRAY_SIZE(glbl_s_axi_rd_cnt_a2_field_info),
+ glbl_s_axi_rd_cnt_a2_field_info
},
-{"GLBL_DSC_DBG_CTL", 0x278,
+{"GLBL_S_AXI_RD_CNT_A3", 0x42c,
1, 0, 0, 0,
- 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_VF,
- ARRAY_SIZE(glbl_dsc_dbg_ctl_field_info),
- glbl_dsc_dbg_ctl_field_info
+ 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY,
+ ARRAY_SIZE(glbl_s_axi_rd_cnt_a3_field_info),
+ glbl_s_axi_rd_cnt_a3_field_info
},
-{"GLBL_DSC_ERR_LOG2", 0x27c,
+{"GLBL_S_AXI_RD_CNT_A4", 0x430,
1, 0, 0, 0,
- 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_VF,
- ARRAY_SIZE(glbl_dsc_err_log2_field_info),
- glbl_dsc_err_log2_field_info
+ 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY,
+ ARRAY_SIZE(glbl_s_axi_rd_cnt_a4_field_info),
+ glbl_s_axi_rd_cnt_a4_field_info
},
-{"GLBL_GLBL_INTERRUPT_CFG", 0x2c4,
+{"GLBL_S_AXI_RD_CNT_A5", 0x434,
1, 0, 0, 0,
- 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_VF,
- ARRAY_SIZE(glbl_glbl_interrupt_cfg_field_info),
- glbl_glbl_interrupt_cfg_field_info
+ 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY,
+ ARRAY_SIZE(glbl_s_axi_rd_cnt_a5_field_info),
+ glbl_s_axi_rd_cnt_a5_field_info
},
-{"GLBL_VCH_HOST_PROFILE", 0x2c8,
+{"GLBL_S_AXIS_CMP_CNT_A0", 0x438,
1, 0, 0, 0,
- 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_VF,
- ARRAY_SIZE(glbl_vch_host_profile_field_info),
- glbl_vch_host_profile_field_info
+ 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY,
+ ARRAY_SIZE(glbl_s_axis_cmp_cnt_a0_field_info),
+ glbl_s_axis_cmp_cnt_a0_field_info
},
-{"GLBL_BRIDGE_HOST_PROFILE", 0x308,
+{"GLBL_S_AXIS_CMP_CNT_A1", 0x43c,
1, 0, 0, 0,
- 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_VF,
- ARRAY_SIZE(glbl_bridge_host_profile_field_info),
- glbl_bridge_host_profile_field_info
+ 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY,
+ ARRAY_SIZE(glbl_s_axis_cmp_cnt_a1_field_info),
+ glbl_s_axis_cmp_cnt_a1_field_info
},
-{"AXIMM_IRQ_DEST_ADDR", 0x30c,
+{"GLBL_S_AXIS_CMP_CNT_A2", 0x440,
1, 0, 0, 0,
- 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_VF,
- ARRAY_SIZE(aximm_irq_dest_addr_field_info),
- aximm_irq_dest_addr_field_info
+ 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY,
+ ARRAY_SIZE(glbl_s_axis_cmp_cnt_a2_field_info),
+ glbl_s_axis_cmp_cnt_a2_field_info
},
-{"FAB_ERR_LOG", 0x314,
+{"GLBL_S_AXIS_CMP_CNT_A3", 0x444,
1, 0, 0, 0,
- 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_VF,
- ARRAY_SIZE(fab_err_log_field_info),
- fab_err_log_field_info
+ 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY,
+ ARRAY_SIZE(glbl_s_axis_cmp_cnt_a3_field_info),
+ glbl_s_axis_cmp_cnt_a3_field_info
},
-{"GLBL_REQ_ERR_STS", 0x318,
+{"GLBL_S_AXIS_CMP_CNT_A4", 0x448,
1, 0, 0, 0,
0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY,
- ARRAY_SIZE(glbl_req_err_sts_field_info),
- glbl_req_err_sts_field_info
+ ARRAY_SIZE(glbl_s_axis_cmp_cnt_a4_field_info),
+ glbl_s_axis_cmp_cnt_a4_field_info
},
-{"GLBL_REQ_ERR_MSK", 0x31c,
+{"GLBL_S_AXIS_CMP_CNT_A5", 0x44c,
1, 0, 0, 0,
0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY,
- ARRAY_SIZE(glbl_req_err_msk_field_info),
- glbl_req_err_msk_field_info
+ ARRAY_SIZE(glbl_s_axis_cmp_cnt_a5_field_info),
+ glbl_s_axis_cmp_cnt_a5_field_info
},
{"IND_CTXT_DATA", 0x804,
1, 0, 0, 0,
@@ -3205,6 +4500,18 @@ static struct xreg_info eqdma_config_regs[] = {
ARRAY_SIZE(c2h_cnt_th_field_info),
c2h_cnt_th_field_info
},
+{"C2H_PFCH_CFG_1", 0xa80,
+ 1, 0, 0, 0,
+ 0, QDMA_ST_MODE, QDMA_REG_READ_PF_VF,
+ ARRAY_SIZE(c2h_pfch_cfg_1_field_info),
+ c2h_pfch_cfg_1_field_info
+},
+{"C2H_PFCH_CFG_2", 0xa84,
+ 1, 0, 0, 0,
+ 0, QDMA_ST_MODE, QDMA_REG_READ_PF_VF,
+ ARRAY_SIZE(c2h_pfch_cfg_2_field_info),
+ c2h_pfch_cfg_2_field_info
+},
{"C2H_STAT_S_AXIS_C2H_ACCEPTED", 0xa88,
1, 0, 0, 0,
1, QDMA_ST_MODE, QDMA_REG_READ_PF_VF,
@@ -3313,18 +4620,6 @@ static struct xreg_info eqdma_config_regs[] = {
ARRAY_SIZE(c2h_pfch_cfg_field_info),
c2h_pfch_cfg_field_info
},
-{"C2H_PFCH_CFG_1", 0xa80,
- 1, 0, 0, 0,
- 0, QDMA_COMPLETION_MODE, QDMA_REG_READ_PF_ONLY,
- ARRAY_SIZE(c2h_pfch_cfg_1_field_info),
- c2h_pfch_cfg_1_field_info
-},
-{"C2H_PFCH_CFG_2", 0xa84,
- 1, 0, 0, 0,
- 0, QDMA_COMPLETION_MODE, QDMA_REG_READ_PF_ONLY,
- ARRAY_SIZE(c2h_pfch_cfg_2_field_info),
- c2h_pfch_cfg_2_field_info
-},
{"C2H_INT_TIMER_TICK", 0xb0c,
1, 0, 0, 0,
0, QDMA_ST_MODE, QDMA_REG_READ_PF_ONLY,
@@ -3907,6 +5202,12 @@ static struct xreg_info eqdma_config_regs[] = {
ARRAY_SIZE(h2c_mm_dbg_field_info),
h2c_mm_dbg_field_info
},
+{"H2C_MM_DATA_THROTTLE", 0x12ec,
+ 1, 0, 0, 0,
+ 0, QDMA_MM_MODE, QDMA_REG_READ_PF_ONLY,
+ ARRAY_SIZE(h2c_mm_data_throttle_field_info),
+ h2c_mm_data_throttle_field_info
+},
{"C2H_CRDT_COAL_CFG_1", 0x1400,
1, 0, 0, 0,
0, QDMA_ST_MODE, QDMA_REG_READ_PF_ONLY,
@@ -3931,12 +5232,96 @@ static struct xreg_info eqdma_config_regs[] = {
ARRAY_SIZE(c2h_pfch_byp_tag_field_info),
c2h_pfch_byp_tag_field_info
},
-{"C2H_WATER_MARK", 0x1500,
+{"C2H_WATER_MARK", 0x1410,
1, 0, 0, 0,
0, QDMA_ST_MODE, QDMA_REG_READ_PF_ONLY,
ARRAY_SIZE(c2h_water_mark_field_info),
c2h_water_mark_field_info
},
+{"C2H_NOTIFY_EMPTY", 0x1450,
+ 1, 0, 0, 0,
+ 0, QDMA_ST_MODE, QDMA_REG_READ_PF_ONLY,
+ ARRAY_SIZE(c2h_notify_empty_field_info),
+ c2h_notify_empty_field_info
+},
+{"C2H_STAT_S_AXIS_C2H_ACCEPTED_1", 0x1454,
+ 1, 0, 0, 0,
+ 0, QDMA_ST_MODE, QDMA_REG_READ_PF_ONLY,
+ ARRAY_SIZE(c2h_stat_s_axis_c2h_accepted_1_field_info),
+ c2h_stat_s_axis_c2h_accepted_1_field_info
+},
+{"C2H_STAT_S_AXIS_WRB_ACCEPTED_1", 0x1458,
+ 1, 0, 0, 0,
+ 0, QDMA_ST_MODE, QDMA_REG_READ_PF_ONLY,
+ ARRAY_SIZE(c2h_stat_s_axis_wrb_accepted_1_field_info),
+ c2h_stat_s_axis_wrb_accepted_1_field_info
+},
+{"C2H_STAT_DESC_RSP_PKT_ACCEPTED_1", 0x145c,
+ 1, 0, 0, 0,
+ 0, QDMA_ST_MODE, QDMA_REG_READ_PF_ONLY,
+ ARRAY_SIZE(c2h_stat_desc_rsp_pkt_accepted_1_field_info),
+ c2h_stat_desc_rsp_pkt_accepted_1_field_info
+},
+{"C2H_STAT_AXIS_PKG_CMP_1", 0x1460,
+ 1, 0, 0, 0,
+ 0, QDMA_ST_MODE, QDMA_REG_READ_PF_ONLY,
+ ARRAY_SIZE(c2h_stat_axis_pkg_cmp_1_field_info),
+ c2h_stat_axis_pkg_cmp_1_field_info
+},
+{"C2H_STAT_S_AXIS_WRB_ACCEPTED_2", 0x1464,
+ 1, 0, 0, 0,
+ 0, QDMA_ST_MODE, QDMA_REG_READ_PF_ONLY,
+ ARRAY_SIZE(c2h_stat_s_axis_wrb_accepted_2_field_info),
+ c2h_stat_s_axis_wrb_accepted_2_field_info
+},
+{"C2H_ST_PLD_FIFO_DEPTH", 0x1468,
+ 1, 0, 0, 0,
+ 0, QDMA_ST_MODE, QDMA_REG_READ_PF_ONLY,
+ ARRAY_SIZE(c2h_st_pld_fifo_depth_field_info),
+ c2h_st_pld_fifo_depth_field_info
+},
+{"C2H_STAT_DBG_DMA_ENG_6", 0x146c,
+ 1, 0, 0, 0,
+ 0, QDMA_ST_MODE, QDMA_REG_READ_PF_ONLY,
+ ARRAY_SIZE(c2h_stat_dbg_dma_eng_6_field_info),
+ c2h_stat_dbg_dma_eng_6_field_info
+},
+{"C2H_STAT_DBG_DMA_ENG_7", 0x1470,
+ 1, 0, 0, 0,
+ 0, QDMA_ST_MODE, QDMA_REG_READ_PF_ONLY,
+ ARRAY_SIZE(c2h_stat_dbg_dma_eng_7_field_info),
+ c2h_stat_dbg_dma_eng_7_field_info
+},
+{"C2H_STAT_PCIE_CMP_1", 0x1474,
+ 1, 0, 0, 0,
+ 0, QDMA_ST_MODE, QDMA_REG_READ_PF_ONLY,
+ ARRAY_SIZE(c2h_stat_pcie_cmp_1_field_info),
+ c2h_stat_pcie_cmp_1_field_info
+},
+{"C2H_PLD_FIFO_ALMOST_FULL", 0x1478,
+ 1, 0, 0, 0,
+ 0, QDMA_ST_MODE, QDMA_REG_READ_PF_ONLY,
+ ARRAY_SIZE(c2h_pld_fifo_almost_full_field_info),
+ c2h_pld_fifo_almost_full_field_info
+},
+{"PFCH_CFG_3", 0x147c,
+ 1, 0, 0, 0,
+ 0, QDMA_ST_MODE, QDMA_REG_READ_PF_ONLY,
+ ARRAY_SIZE(pfch_cfg_3_field_info),
+ pfch_cfg_3_field_info
+},
+{"CMPT_CFG_0", 0x1480,
+ 1, 0, 0, 0,
+ 0, QDMA_ST_MODE, QDMA_REG_READ_PF_ONLY,
+ ARRAY_SIZE(cmpt_cfg_0_field_info),
+ cmpt_cfg_0_field_info
+},
+{"PFCH_CFG_4", 0x1484,
+ 1, 0, 0, 0,
+ 0, QDMA_ST_MODE, QDMA_REG_READ_PF_ONLY,
+ ARRAY_SIZE(pfch_cfg_4_field_info),
+ pfch_cfg_4_field_info
+},
};
diff --git a/QDMA/DPDK/drivers/net/qdma/qdma_access/qdma_access_common.c b/QDMA/DPDK/drivers/net/qdma/qdma_access/qdma_access_common.c
old mode 100644
new mode 100755
index 5253108f958db14adfd6d03b3f6aee9ef6f3518a..84a952618762d0ab96d9188b3a8657a02dc467dd
--- a/QDMA/DPDK/drivers/net/qdma/qdma_access/qdma_access_common.c
+++ b/QDMA/DPDK/drivers/net/qdma/qdma_access/qdma_access_common.c
@@ -1,5 +1,6 @@
/*
- * Copyright(c) 2019-2022 Xilinx, Inc. All rights reserved.
+ * Copyright (c) 2019-2022, Xilinx, Inc. All rights reserved.
+ * Copyright (c) 2022, Advanced Micro Devices, Inc. All rights reserved.
*
* BSD LICENSE
*
@@ -120,12 +121,24 @@ static const char *qdma_get_rtl_version(enum qdma_rtl_version rtl_version)
/**
* qdma_get_ip_type() - Function to get the ip type in string format
*
- * @ip_type: IP Type
+ * @dev_hndl: device handle
+ * @is_vf: Whether PF or VF
+ * @ip_type: IP Type
*
* Return: string - success and NULL on failure
*****************************************************************************/
-static const char *qdma_get_ip_type(enum qdma_ip_type ip_type)
+static const char *qdma_get_ip_type(void *dev_hndl, uint8_t is_vf,
+ enum qdma_ip_type ip_type)
{
+ uint32_t ip_version;
+ int rv = QDMA_SUCCESS;
+
+ if (!dev_hndl) {
+ qdma_log_error("%s: dev_handle is NULL, err:%d\n",
+ __func__, -QDMA_ERR_INV_PARAM);
+ return NULL;
+ }
+
switch (ip_type) {
case QDMA_VERSAL_HARD_IP:
return "Versal Hard IP";
@@ -134,7 +147,18 @@ static const char *qdma_get_ip_type(enum qdma_ip_type ip_type)
case QDMA_SOFT_IP:
return "QDMA Soft IP";
case EQDMA_SOFT_IP:
- return "EQDMA Soft IP";
+ rv = eqdma_get_ip_version(dev_hndl, is_vf, &ip_version);
+ if (rv != QDMA_SUCCESS)
+ return NULL;
+
+ if (ip_version == EQDMA_IP_VERSION_4)
+ return "EQDMA4.0 Soft IP";
+ else if (ip_version == EQDMA_IP_VERSION_5)
+ return "EQDMA5.0 Soft IP";
+
+ qdma_log_error("%s: invalid eqdma ip version(%d), err:%d\n",
+ __func__, ip_version, -QDMA_ERR_INV_PARAM);
+ return NULL;
default:
qdma_log_error("%s: invalid ip type(%d), err:%d\n",
__func__, ip_type, -QDMA_ERR_INV_PARAM);
@@ -227,12 +251,18 @@ void qdma_read_csr_values(void *dev_hndl, uint32_t reg_offst,
}
}
-void qdma_fetch_version_details(uint8_t is_vf, uint32_t version_reg_val,
- struct qdma_hw_version_info *version_info)
+void qdma_fetch_version_details(void *dev_hndl, uint8_t is_vf,
+ uint32_t version_reg_val, struct qdma_hw_version_info *version_info)
{
uint32_t rtl_version, vivado_release_id, ip_type, device_type;
const char *version_str;
+ if (!dev_hndl) {
+ qdma_log_error("%s: dev_handle is NULL, err:%d\n",
+ __func__, -QDMA_ERR_INV_PARAM);
+ return;
+ }
+
if (!is_vf) {
rtl_version = FIELD_GET(QDMA_GLBL2_RTL_VERSION_MASK,
version_reg_val);
@@ -303,6 +333,11 @@ void qdma_fetch_version_details(uint8_t is_vf, uint32_t version_reg_val,
version_info->ip_type = QDMA_SOFT_IP;
break;
case 1:
+ case 2:
+ /* For QDMA4.0 and QDMA5.0, HW design and
+ * register map is same except some
+ * performance optimizations
+ */
version_info->ip_type = EQDMA_SOFT_IP;
break;
default:
@@ -321,7 +356,7 @@ void qdma_fetch_version_details(uint8_t is_vf, uint32_t version_reg_val,
}
}
- version_str = qdma_get_ip_type(version_info->ip_type);
+ version_str = qdma_get_ip_type(dev_hndl, is_vf, version_info->ip_type);
if (version_str != NULL)
qdma_strncpy(version_info->qdma_ip_type_str,
version_str,
@@ -1346,7 +1381,7 @@ int qdma_hw_access_init(void *dev_hndl, uint8_t is_vf,
qdma_get_device_type(version_info.device_type));
qdma_log_info("IP Type: %s\n",
- qdma_get_ip_type(version_info.ip_type));
+ qdma_get_ip_type(dev_hndl, is_vf, version_info.ip_type));
qdma_log_info("Vivado Release: %s\n",
qdma_get_vivado_release_id(version_info.vivado_release));
diff --git a/QDMA/DPDK/drivers/net/qdma/qdma_access/qdma_access_common.h b/QDMA/DPDK/drivers/net/qdma/qdma_access/qdma_access_common.h
old mode 100644
new mode 100755
index 0edc640ea78ba7731ecc9160417a910dbe583e2b..99ba55e4683667345dacf9e884dad936467aa3a6
--- a/QDMA/DPDK/drivers/net/qdma/qdma_access/qdma_access_common.h
+++ b/QDMA/DPDK/drivers/net/qdma/qdma_access/qdma_access_common.h
@@ -1,5 +1,6 @@
/*
- * Copyright(c) 2019-2022 Xilinx, Inc. All rights reserved.
+ * Copyright (c) 2019-2022, Xilinx, Inc. All rights reserved.
+ * Copyright (c) 2022, Advanced Micro Devices, Inc. All rights reserved.
*
* BSD LICENSE
*
@@ -178,7 +179,7 @@ union qdma_ind_ctxt_cmd {
uint32_t busy:1;
uint32_t sel:4;
uint32_t op:2;
- uint32_t qid:11;
+ uint32_t qid:12;
uint32_t rsvd:14;
} bits;
};
@@ -924,9 +925,8 @@ int qdma_get_error_code(int acc_err_code);
*
* Return: Nothing
*****************************************************************************/
-void qdma_fetch_version_details(uint8_t is_vf, uint32_t version_reg_val,
- struct qdma_hw_version_info *version_info);
-
+void qdma_fetch_version_details(void *dev_hndl, uint8_t is_vf,
+ uint32_t version_reg_val, struct qdma_hw_version_info *version_info);
#ifdef __cplusplus
}
diff --git a/QDMA/DPDK/drivers/net/qdma/qdma_access/qdma_access_errors.h b/QDMA/DPDK/drivers/net/qdma/qdma_access/qdma_access_errors.h
old mode 100644
new mode 100755
index ed3c26367406a459ddd31d0d86c0f9b1240f582e..8eb2c582a88607c0a3ef08bdbaa69a2d6066380b
--- a/QDMA/DPDK/drivers/net/qdma/qdma_access/qdma_access_errors.h
+++ b/QDMA/DPDK/drivers/net/qdma/qdma_access/qdma_access_errors.h
@@ -1,5 +1,6 @@
/*
- * Copyright(c) 2019-2022 Xilinx, Inc. All rights reserved.
+ * Copyright (c) 2019-2022, Xilinx, Inc. All rights reserved.
+ * Copyright (c) 2022, Advanced Micro Devices, Inc. All rights reserved.
*
* BSD LICENSE
*
diff --git a/QDMA/DPDK/drivers/net/qdma/qdma_access/qdma_access_export.h b/QDMA/DPDK/drivers/net/qdma/qdma_access/qdma_access_export.h
old mode 100644
new mode 100755
index 3ad2f99f3d910c756edf69e43d43e0b1d2571bb4..dba818585271c9fd8d7f475855db9bbcf4357c75
--- a/QDMA/DPDK/drivers/net/qdma/qdma_access/qdma_access_export.h
+++ b/QDMA/DPDK/drivers/net/qdma/qdma_access/qdma_access_export.h
@@ -1,5 +1,6 @@
/*
- * Copyright(c) 2019-2022 Xilinx, Inc. All rights reserved.
+ * Copyright (c) 2019-2022, Xilinx, Inc. All rights reserved.
+ * Copyright (c) 2022, Advanced Micro Devices, Inc. All rights reserved.
*
* BSD LICENSE
*
diff --git a/QDMA/DPDK/drivers/net/qdma/qdma_access/qdma_access_version.h b/QDMA/DPDK/drivers/net/qdma/qdma_access/qdma_access_version.h
old mode 100644
new mode 100755
index 1bb008dd2be5ea08f014725472bc9082c3ae7883..d54fca8d291fafb6788c72407b28fa51b29c85a4
--- a/QDMA/DPDK/drivers/net/qdma/qdma_access/qdma_access_version.h
+++ b/QDMA/DPDK/drivers/net/qdma/qdma_access/qdma_access_version.h
@@ -1,5 +1,6 @@
/*
- * Copyright(c) 2019-2022 Xilinx, Inc. All rights reserved.
+ * Copyright (c) 2019-2022, Xilinx, Inc. All rights reserved.
+ * Copyright (c) 2022, Advanced Micro Devices, Inc. All rights reserved.
*
* BSD LICENSE
*
@@ -36,7 +37,7 @@
#define QDMA_VERSION_MAJOR 2022
#define QDMA_VERSION_MINOR 1
-#define QDMA_VERSION_PATCH 2
+#define QDMA_VERSION_PATCH 5
#define QDMA_VERSION_STR \
__stringify(QDMA_VERSION_MAJOR) "." \
diff --git a/QDMA/DPDK/drivers/net/qdma/qdma_access/qdma_cpm4_access/qdma_cpm4_access.c b/QDMA/DPDK/drivers/net/qdma/qdma_access/qdma_cpm4_access/qdma_cpm4_access.c
old mode 100644
new mode 100755
index 56b50217047dda35046a748fde94cb2b560e2a29..65b0d4c3a063f8e9c81d7e40f367de83e71c5a19
--- a/QDMA/DPDK/drivers/net/qdma/qdma_access/qdma_cpm4_access/qdma_cpm4_access.c
+++ b/QDMA/DPDK/drivers/net/qdma/qdma_access/qdma_cpm4_access/qdma_cpm4_access.c
@@ -1,5 +1,6 @@
/*
- * Copyright(c) 2019-2022 Xilinx, Inc. All rights reserved.
+ * Copyright (c) 2019-2022, Xilinx, Inc. All rights reserved.
+ * Copyright (c) 2022, Advanced Micro Devices, Inc. All rights reserved.
*
* BSD LICENSE
*
@@ -1427,7 +1428,7 @@ static int dump_cpm4_context(struct qdma_descq_context *queue_context,
int n;
int len = 0;
int rv;
- char banner[DEBGFS_LINE_SZ];
+ char banner[DEBGFS_LINE_SZ] = "";
if (queue_context == NULL) {
qdma_log_error("%s: queue_context is NULL, err:%d\n",
@@ -1941,7 +1942,7 @@ static int dump_cpm4_intr_context(struct qdma_indirect_intr_ctxt *intr_ctx,
int n;
int len = 0;
int rv;
- char banner[DEBGFS_LINE_SZ];
+ char banner[DEBGFS_LINE_SZ] = "";
qdma_cpm4_fill_intr_ctxt(intr_ctx);
diff --git a/QDMA/DPDK/drivers/net/qdma/qdma_access/qdma_cpm4_access/qdma_cpm4_access.h b/QDMA/DPDK/drivers/net/qdma/qdma_access/qdma_cpm4_access/qdma_cpm4_access.h
old mode 100644
new mode 100755
index 8335b518f8989b72cf68b980c7829d473259fd7b..33a1d068b7ea68056fc25a12f1c3cb2d645b92ee
--- a/QDMA/DPDK/drivers/net/qdma/qdma_access/qdma_cpm4_access/qdma_cpm4_access.h
+++ b/QDMA/DPDK/drivers/net/qdma/qdma_access/qdma_cpm4_access/qdma_cpm4_access.h
@@ -1,5 +1,6 @@
/*
- * Copyright(c) 2019-2022 Xilinx, Inc. All rights reserved.
+ * Copyright (c) 2019-2022, Xilinx, Inc. All rights reserved.
+ * Copyright (c) 2022, Advanced Micro Devices, Inc. All rights reserved.
*
* BSD LICENSE
*
diff --git a/QDMA/DPDK/drivers/net/qdma/qdma_access/qdma_cpm4_access/qdma_cpm4_reg.h b/QDMA/DPDK/drivers/net/qdma/qdma_access/qdma_cpm4_access/qdma_cpm4_reg.h
old mode 100644
new mode 100755
index c95d0154a55b0eceda23bbf2e086cda26255a5ae..00bba141cae53117ebd63418fffa7bcf9bc278a0
--- a/QDMA/DPDK/drivers/net/qdma/qdma_access/qdma_cpm4_access/qdma_cpm4_reg.h
+++ b/QDMA/DPDK/drivers/net/qdma/qdma_access/qdma_cpm4_access/qdma_cpm4_reg.h
@@ -1,5 +1,6 @@
/*
- * Copyright(c) 2019-2022 Xilinx, Inc. All rights reserved.
+ * Copyright (c) 2019-2022, Xilinx, Inc. All rights reserved.
+ * Copyright (c) 2022, Advanced Micro Devices, Inc. All rights reserved.
*
* BSD LICENSE
*
diff --git a/QDMA/DPDK/drivers/net/qdma/qdma_access/qdma_cpm4_access/qdma_cpm4_reg_dump.c b/QDMA/DPDK/drivers/net/qdma/qdma_access/qdma_cpm4_access/qdma_cpm4_reg_dump.c
old mode 100644
new mode 100755
index 34dafd3305e76407047d15951bcf83576ee1ba3a..2955d7a9567c4664a9ede3e9f427073f90d3d103
--- a/QDMA/DPDK/drivers/net/qdma/qdma_access/qdma_cpm4_access/qdma_cpm4_reg_dump.c
+++ b/QDMA/DPDK/drivers/net/qdma/qdma_access/qdma_cpm4_access/qdma_cpm4_reg_dump.c
@@ -1,5 +1,6 @@
/*
- * Copyright(c) 2019-2022 Xilinx, Inc. All rights reserved.
+ * Copyright (c) 2019-2022, Xilinx, Inc. All rights reserved.
+ * Copyright (c) 2022, Advanced Micro Devices, Inc. All rights reserved.
*
* BSD LICENSE
*
diff --git a/QDMA/DPDK/drivers/net/qdma/qdma_access/qdma_list.c b/QDMA/DPDK/drivers/net/qdma/qdma_access/qdma_list.c
old mode 100644
new mode 100755
index 28877f5e4e7680f2e8e0181c223067526cb4ef00..6cea8aa33387ef7cfd5ba442e8e87c8eef1d48a8
--- a/QDMA/DPDK/drivers/net/qdma/qdma_access/qdma_list.c
+++ b/QDMA/DPDK/drivers/net/qdma/qdma_access/qdma_list.c
@@ -1,5 +1,6 @@
/*
- * Copyright(c) 2019-2022 Xilinx, Inc. All rights reserved.
+ * Copyright (c) 2019-2022, Xilinx, Inc. All rights reserved.
+ * Copyright (c) 2022, Advanced Micro Devices, Inc. All rights reserved.
*
* BSD LICENSE
*
diff --git a/QDMA/DPDK/drivers/net/qdma/qdma_access/qdma_list.h b/QDMA/DPDK/drivers/net/qdma/qdma_access/qdma_list.h
old mode 100644
new mode 100755
index 6be25a37c3ddc1ec8a70f78fe41759be7d40618b..f4224a4eb43a27529ef555f066f2c3736e4bd852
--- a/QDMA/DPDK/drivers/net/qdma/qdma_access/qdma_list.h
+++ b/QDMA/DPDK/drivers/net/qdma/qdma_access/qdma_list.h
@@ -1,5 +1,6 @@
/*
- * Copyright(c) 2019-2022 Xilinx, Inc. All rights reserved.
+ * Copyright (c) 2019-2022, Xilinx, Inc. All rights reserved.
+ * Copyright (c) 2022, Advanced Micro Devices, Inc. All rights reserved.
*
* BSD LICENSE
*
diff --git a/QDMA/DPDK/drivers/net/qdma/qdma_access/qdma_mbox_protocol.c b/QDMA/DPDK/drivers/net/qdma/qdma_access/qdma_mbox_protocol.c
old mode 100644
new mode 100755
index 617eb079b7b3dde2c11b0d7c901123e4e4bcb450..3dbae0d856d72de3f04d1a52756372daec61b246
--- a/QDMA/DPDK/drivers/net/qdma/qdma_access/qdma_mbox_protocol.c
+++ b/QDMA/DPDK/drivers/net/qdma/qdma_access/qdma_mbox_protocol.c
@@ -1,5 +1,6 @@
/*
- * Copyright(c) 2019-2022 Xilinx, Inc. All rights reserved.
+ * Copyright (c) 2019-2022, Xilinx, Inc. All rights reserved.
+ * Copyright (c) 2022, Advanced Micro Devices, Inc. All rights reserved.
*
* BSD LICENSE
*
diff --git a/QDMA/DPDK/drivers/net/qdma/qdma_access/qdma_mbox_protocol.h b/QDMA/DPDK/drivers/net/qdma/qdma_access/qdma_mbox_protocol.h
old mode 100644
new mode 100755
index a2071e867c010f51e7563dfaf6d1c8ca9c6d06c6..243ee7570cc7899bacfc80525cc88a8f27bcf7e5
--- a/QDMA/DPDK/drivers/net/qdma/qdma_access/qdma_mbox_protocol.h
+++ b/QDMA/DPDK/drivers/net/qdma/qdma_access/qdma_mbox_protocol.h
@@ -1,5 +1,6 @@
/*
- * Copyright(c) 2019-2022 Xilinx, Inc. All rights reserved.
+ * Copyright (c) 2019-2022, Xilinx, Inc. All rights reserved.
+ * Copyright (c) 2022, Advanced Micro Devices, Inc. All rights reserved.
*
* BSD LICENSE
*
diff --git a/QDMA/DPDK/drivers/net/qdma/qdma_access/qdma_platform.h b/QDMA/DPDK/drivers/net/qdma/qdma_access/qdma_platform.h
old mode 100644
new mode 100755
index 28fe0428e18e6cfb1b7a9cdbd541bd2f5f9fd29d..9cdd9c6bbd839bc7619fb893c898bbf94e353ed0
--- a/QDMA/DPDK/drivers/net/qdma/qdma_access/qdma_platform.h
+++ b/QDMA/DPDK/drivers/net/qdma/qdma_access/qdma_platform.h
@@ -1,5 +1,6 @@
/*
- * Copyright(c) 2019-2022 Xilinx, Inc. All rights reserved.
+ * Copyright (c) 2019-2022, Xilinx, Inc. All rights reserved.
+ * Copyright (c) 2022, Advanced Micro Devices, Inc. All rights reserved.
*
* BSD LICENSE
*
diff --git a/QDMA/DPDK/drivers/net/qdma/qdma_access/qdma_reg_dump.h b/QDMA/DPDK/drivers/net/qdma/qdma_access/qdma_reg_dump.h
old mode 100644
new mode 100755
index 86cad5038727cd2346393a840f5f83300950e11e..b1a63c0242d14682c565b533ff4674262cb58b95
--- a/QDMA/DPDK/drivers/net/qdma/qdma_access/qdma_reg_dump.h
+++ b/QDMA/DPDK/drivers/net/qdma/qdma_access/qdma_reg_dump.h
@@ -1,5 +1,6 @@
/*
- * Copyright(c) 2019-2022 Xilinx, Inc. All rights reserved.
+ * Copyright (c) 2019-2022, Xilinx, Inc. All rights reserved.
+ * Copyright (c) 2022, Advanced Micro Devices, Inc. All rights reserved.
*
* BSD LICENSE
*
diff --git a/QDMA/DPDK/drivers/net/qdma/qdma_access/qdma_resource_mgmt.c b/QDMA/DPDK/drivers/net/qdma/qdma_access/qdma_resource_mgmt.c
old mode 100644
new mode 100755
index cbea0a057f953d1d5b3283d53492ec3840f229b6..d903859dca5921d7058ce7581ab25e59012b7257
--- a/QDMA/DPDK/drivers/net/qdma/qdma_access/qdma_resource_mgmt.c
+++ b/QDMA/DPDK/drivers/net/qdma/qdma_access/qdma_resource_mgmt.c
@@ -1,5 +1,6 @@
/*
- * Copyright(c) 2019-2022 Xilinx, Inc. All rights reserved.
+ * Copyright (c) 2019-2022, Xilinx, Inc. All rights reserved.
+ * Copyright (c) 2022, Advanced Micro Devices, Inc. All rights reserved.
*
* BSD LICENSE
*
diff --git a/QDMA/DPDK/drivers/net/qdma/qdma_access/qdma_resource_mgmt.h b/QDMA/DPDK/drivers/net/qdma/qdma_access/qdma_resource_mgmt.h
old mode 100644
new mode 100755
index 7f91c00aa9a3357617f4f754a59bbcc889352ea0..3361f165fa71882baaf9ccb936c72b14eb79a103
--- a/QDMA/DPDK/drivers/net/qdma/qdma_access/qdma_resource_mgmt.h
+++ b/QDMA/DPDK/drivers/net/qdma/qdma_access/qdma_resource_mgmt.h
@@ -1,5 +1,6 @@
/*
- * Copyright(c) 2019-2022 Xilinx, Inc. All rights reserved.
+ * Copyright (c) 2019-2022, Xilinx, Inc. All rights reserved.
+ * Copyright (c) 2022, Advanced Micro Devices, Inc. All rights reserved.
*
* BSD LICENSE
*
diff --git a/QDMA/DPDK/drivers/net/qdma/qdma_access/qdma_s80_hard_access/qdma_s80_hard_access.c b/QDMA/DPDK/drivers/net/qdma/qdma_access/qdma_s80_hard_access/qdma_s80_hard_access.c
deleted file mode 100644
index 00f8ba47ff4945d4a931844ee7cf86741101a885..0000000000000000000000000000000000000000
--- a/QDMA/DPDK/drivers/net/qdma/qdma_access/qdma_s80_hard_access/qdma_s80_hard_access.c
+++ /dev/null
@@ -1,5910 +0,0 @@
-/*
- * Copyright(c) 2019-2020 Xilinx, Inc. All rights reserved.
- *
- * BSD LICENSE
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- *
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in
- * the documentation and/or other materials provided with the
- * distribution.
- * * Neither the name of the copyright holder nor the names of its
- * contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
- * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
- * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
- * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
- * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
- * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
- * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- */
-
-#include "qdma_s80_hard_access.h"
-#include "qdma_s80_hard_reg.h"
-#include "qdma_reg_dump.h"
-
-#ifdef ENABLE_WPP_TRACING
-#include "qdma_s80_hard_access.tmh"
-#endif
-
-/** QDMA S80 Hard Context array size */
-#define QDMA_S80_HARD_SW_CONTEXT_NUM_WORDS 4
-#define QDMA_S80_HARD_CMPT_CONTEXT_NUM_WORDS 4
-#define QDMA_S80_HARD_QID2VEC_CONTEXT_NUM_WORDS 1
-#define QDMA_S80_HARD_HW_CONTEXT_NUM_WORDS 2
-#define QDMA_S80_HARD_CR_CONTEXT_NUM_WORDS 1
-#define QDMA_S80_HARD_IND_INTR_CONTEXT_NUM_WORDS 3
-#define QDMA_S80_HARD_PFETCH_CONTEXT_NUM_WORDS 2
-
-#define QDMA_S80_HARD_VF_USER_BAR_ID 2
-
-#define QDMA_S80_REG_GROUP_1_START_ADDR 0x000
-#define QDMA_S80_REG_GROUP_2_START_ADDR 0x400
-#define QDMA_S80_REG_GROUP_3_START_ADDR 0xB00
-#define QDMA_S80_REG_GROUP_4_START_ADDR 0x1014
-
-#define QDMA_S80_HARD_REG_TRQ_SEL_FMAP_STEP 4
-
-#define QDMA_S80_HARD_IND_CTXT_DATA_NUM_REGS 4
-
-#define QDMA_S80_HARD_TOTAL_LEAF_ERROR_AGGREGATORS 7
-#define QDMA_S80_HARD_GLBL_TRQ_ERR_ALL_MASK 0XB3
-#define QDMA_S80_HARD_GLBL_DSC_ERR_ALL_MASK 0X1F9037E
-#define QDMA_S80_HARD_C2H_ERR_ALL_MASK 0X3F6DF
-#define QDMA_S80_HARD_C2H_FATAL_ERR_ALL_MASK 0X1FDF1B
-#define QDMA_S80_HARD_H2C_ERR_ALL_MASK 0X3F
-#define QDMA_S80_HARD_SBE_ERR_ALL_MASK 0XFFFFFFFF
-#define QDMA_S80_HARD_DBE_ERR_ALL_MASK 0XFFFFFFFF
-
-#define QDMA_S80_HARD_OFFSET_DMAP_SEL_INT_CIDX 0x6400
-#define QDMA_S80_HARD_OFFSET_DMAP_SEL_H2C_DSC_PIDX 0x6404
-#define QDMA_S80_HARD_OFFSET_DMAP_SEL_C2H_DSC_PIDX 0x6408
-#define QDMA_S80_HARD_OFFSET_DMAP_SEL_CMPT_CIDX 0x640C
-
-#define QDMA_S80_HARD_OFFSET_VF_DMAP_SEL_INT_CIDX 0x3000
-#define QDMA_S80_HARD_OFFSET_VF_DMAP_SEL_H2C_DSC_PIDX 0x3004
-#define QDMA_S80_HARD_OFFSET_VF_DMAP_SEL_C2H_DSC_PIDX 0x3008
-#define QDMA_S80_HARD_OFFSET_VF_DMAP_SEL_CMPT_CIDX 0x300C
-
-#define QDMA_S80_HARD_DMA_SEL_INT_SW_CIDX_MASK GENMASK(15, 0)
-#define QDMA_S80_HARD_DMA_SEL_INT_RING_IDX_MASK GENMASK(23, 16)
-#define QDMA_S80_HARD_DMA_SEL_DESC_PIDX_MASK GENMASK(15, 0)
-#define QDMA_S80_HARD_DMA_SEL_IRQ_EN_MASK BIT(16)
-#define QDMA_S80_HARD_DMAP_SEL_CMPT_IRQ_EN_MASK BIT(28)
-#define QDMA_S80_HARD_DMAP_SEL_CMPT_STS_DESC_EN_MASK BIT(27)
-#define QDMA_S80_HARD_DMAP_SEL_CMPT_TRG_MODE_MASK GENMASK(26, 24)
-#define QDMA_S80_HARD_DMAP_SEL_CMPT_TMR_CNT_MASK GENMASK(23, 20)
-#define QDMA_S80_HARD_DMAP_SEL_CMPT_CNT_THRESH_MASK GENMASK(19, 16)
-#define QDMA_S80_HARD_DMAP_SEL_CMPT_WRB_CIDX_MASK GENMASK(15, 0)
-#define QDMA_S80_HARD_INTR_CTXT_BADDR_GET_H_MASK GENMASK_ULL(63, 35)
-#define QDMA_S80_HARD_INTR_CTXT_BADDR_GET_L_MASK GENMASK_ULL(34, 12)
-#define QDMA_S80_HARD_COMPL_CTXT_BADDR_GET_H_MASK GENMASK_ULL(63, 42)
-#define QDMA_S80_HARD_COMPL_CTXT_BADDR_GET_M_MASK GENMASK_ULL(41, 10)
-#define QDMA_S80_HARD_COMPL_CTXT_BADDR_GET_L_MASK GENMASK_ULL(9, 6)
-#define QDMA_S80_HARD_COMPL_CTXT_PIDX_GET_H_MASK GENMASK(15, 8)
-#define QDMA_S80_HARD_COMPL_CTXT_PIDX_GET_L_MASK GENMASK(7, 0)
-#define QDMA_S80_HARD_QID2VEC_H2C_VECTOR GENMASK(16, 9)
-#define QDMA_S80_HARD_QID2VEC_H2C_COAL_EN BIT(17)
-
-static void qdma_s80_hard_hw_st_h2c_err_process(void *dev_hndl);
-static void qdma_s80_hard_hw_st_c2h_err_process(void *dev_hndl);
-static void qdma_s80_hard_hw_desc_err_process(void *dev_hndl);
-static void qdma_s80_hard_hw_trq_err_process(void *dev_hndl);
-static void qdma_s80_hard_hw_ram_sbe_err_process(void *dev_hndl);
-static void qdma_s80_hard_hw_ram_dbe_err_process(void *dev_hndl);
-
-static struct qdma_s80_hard_hw_err_info
- qdma_s80_hard_err_info[QDMA_S80_HARD_ERRS_ALL] = {
- /* Descriptor errors */
- {
- QDMA_S80_HARD_DSC_ERR_POISON,
- "Poison error",
- QDMA_S80_HARD_GLBL_DSC_ERR_MSK_ADDR,
- QDMA_S80_HARD_GLBL_DSC_ERR_STS_ADDR,
- GLBL_DSC_ERR_STS_POISON_MASK,
- GLBL_ERR_STAT_ERR_DSC_MASK,
- &qdma_s80_hard_hw_desc_err_process
- },
- {
- QDMA_S80_HARD_DSC_ERR_UR_CA,
- "Unsupported request or completer aborted error",
- QDMA_S80_HARD_GLBL_DSC_ERR_MSK_ADDR,
- QDMA_S80_HARD_GLBL_DSC_ERR_STS_ADDR,
- GLBL_DSC_ERR_STS_UR_CA_MASK,
- GLBL_ERR_STAT_ERR_DSC_MASK,
- &qdma_s80_hard_hw_desc_err_process
- },
- {
- QDMA_S80_HARD_DSC_ERR_PARAM,
- "Parameter mismatch error",
- QDMA_S80_HARD_GLBL_DSC_ERR_MSK_ADDR,
- QDMA_S80_HARD_GLBL_DSC_ERR_STS_ADDR,
- GLBL_DSC_ERR_STS_PARAM_MASK,
- GLBL_ERR_STAT_ERR_DSC_MASK,
- &qdma_s80_hard_hw_desc_err_process
- },
- {
- QDMA_S80_HARD_DSC_ERR_ADDR,
- "Address mismatch error",
- QDMA_S80_HARD_GLBL_DSC_ERR_MSK_ADDR,
- QDMA_S80_HARD_GLBL_DSC_ERR_STS_ADDR,
- GLBL_DSC_ERR_STS_ADDR_MASK,
- GLBL_ERR_STAT_ERR_DSC_MASK,
- &qdma_s80_hard_hw_desc_err_process
- },
- {
- QDMA_S80_HARD_DSC_ERR_TAG,
- "Unexpected tag error",
- QDMA_S80_HARD_GLBL_DSC_ERR_MSK_ADDR,
- QDMA_S80_HARD_GLBL_DSC_ERR_STS_ADDR,
- GLBL_DSC_ERR_STS_TAG_MASK,
- GLBL_ERR_STAT_ERR_DSC_MASK,
- &qdma_s80_hard_hw_desc_err_process
- },
- {
- QDMA_S80_HARD_DSC_ERR_FLR,
- "FLR error",
- QDMA_S80_HARD_GLBL_DSC_ERR_MSK_ADDR,
- QDMA_S80_HARD_GLBL_DSC_ERR_STS_ADDR,
- GLBL_DSC_ERR_STS_FLR_MASK,
- GLBL_ERR_STAT_ERR_DSC_MASK,
- &qdma_s80_hard_hw_desc_err_process
- },
- {
- QDMA_S80_HARD_DSC_ERR_TIMEOUT,
- "Timed out error",
- QDMA_S80_HARD_GLBL_DSC_ERR_MSK_ADDR,
- QDMA_S80_HARD_GLBL_DSC_ERR_STS_ADDR,
- GLBL_DSC_ERR_STS_TIMEOUT_MASK,
- GLBL_ERR_STAT_ERR_DSC_MASK,
- &qdma_s80_hard_hw_desc_err_process
- },
- {
- QDMA_S80_HARD_DSC_ERR_DAT_POISON,
- "Poison data error",
- QDMA_S80_HARD_GLBL_DSC_ERR_MSK_ADDR,
- QDMA_S80_HARD_GLBL_DSC_ERR_STS_ADDR,
- GLBL_DSC_ERR_STS_DAT_POISON_MASK,
- GLBL_ERR_STAT_ERR_DSC_MASK,
- &qdma_s80_hard_hw_desc_err_process
- },
- {
- QDMA_S80_HARD_DSC_ERR_FLR_CANCEL,
- "Descriptor fetch cancelled due to FLR error",
- QDMA_S80_HARD_GLBL_DSC_ERR_MSK_ADDR,
- QDMA_S80_HARD_GLBL_DSC_ERR_STS_ADDR,
- GLBL_DSC_ERR_STS_FLR_CANCEL_MASK,
- GLBL_ERR_STAT_ERR_DSC_MASK,
- &qdma_s80_hard_hw_desc_err_process
- },
- {
- QDMA_S80_HARD_DSC_ERR_DMA,
- "DMA engine error",
- QDMA_S80_HARD_GLBL_DSC_ERR_MSK_ADDR,
- QDMA_S80_HARD_GLBL_DSC_ERR_STS_ADDR,
- GLBL_DSC_ERR_STS_DMA_MASK,
- GLBL_ERR_STAT_ERR_DSC_MASK,
- &qdma_s80_hard_hw_desc_err_process
- },
- {
- QDMA_S80_HARD_DSC_ERR_DSC,
- "Invalid PIDX update error",
- QDMA_S80_HARD_GLBL_DSC_ERR_MSK_ADDR,
- QDMA_S80_HARD_GLBL_DSC_ERR_STS_ADDR,
- GLBL_DSC_ERR_STS_DSC_MASK,
- GLBL_ERR_STAT_ERR_DSC_MASK,
- &qdma_s80_hard_hw_desc_err_process
- },
- {
- QDMA_S80_HARD_DSC_ERR_RQ_CANCEL,
- "Descriptor fetch cancelled due to disable register status error",
- QDMA_S80_HARD_GLBL_DSC_ERR_MSK_ADDR,
- QDMA_S80_HARD_GLBL_DSC_ERR_STS_ADDR,
- GLBL_DSC_ERR_STS_RQ_CANCEL_MASK,
- GLBL_ERR_STAT_ERR_DSC_MASK,
- &qdma_s80_hard_hw_desc_err_process
- },
- {
- QDMA_S80_HARD_DSC_ERR_DBE,
- "UNC_ERR_RAM_DBE error",
- QDMA_S80_HARD_GLBL_DSC_ERR_MSK_ADDR,
- QDMA_S80_HARD_GLBL_DSC_ERR_STS_ADDR,
- GLBL_DSC_ERR_STS_DBE_MASK,
- GLBL_ERR_STAT_ERR_DSC_MASK,
- &qdma_s80_hard_hw_desc_err_process
- },
- {
- QDMA_S80_HARD_DSC_ERR_SBE,
- "UNC_ERR_RAM_SBE error",
- QDMA_S80_HARD_GLBL_DSC_ERR_MSK_ADDR,
- QDMA_S80_HARD_GLBL_DSC_ERR_STS_ADDR,
- GLBL_DSC_ERR_STS_SBE_MASK,
- GLBL_ERR_STAT_ERR_DSC_MASK,
- &qdma_s80_hard_hw_desc_err_process
- },
- {
- QDMA_S80_HARD_DSC_ERR_ALL,
- "All Descriptor errors",
- QDMA_S80_HARD_GLBL_DSC_ERR_MSK_ADDR,
- QDMA_S80_HARD_GLBL_DSC_ERR_STS_ADDR,
- QDMA_S80_HARD_DBE_ERR_ALL_MASK,
- GLBL_ERR_STAT_ERR_DSC_MASK,
- &qdma_s80_hard_hw_desc_err_process
- },
-
- /* TRQ errors */
- {
- QDMA_S80_HARD_TRQ_ERR_UNMAPPED,
- "Access targeted unmapped register space via CSR pathway error",
- QDMA_S80_HARD_GLBL_TRQ_ERR_MSK_ADDR,
- QDMA_S80_HARD_GLBL_TRQ_ERR_STS_ADDR,
- GLBL_TRQ_ERR_STS_UNMAPPED_MASK,
- GLBL_ERR_STAT_ERR_TRQ_MASK,
- &qdma_s80_hard_hw_trq_err_process
- },
- {
- QDMA_S80_HARD_TRQ_ERR_QID_RANGE,
- "Qid range error",
- QDMA_S80_HARD_GLBL_TRQ_ERR_MSK_ADDR,
- QDMA_S80_HARD_GLBL_TRQ_ERR_STS_ADDR,
- GLBL_TRQ_ERR_STS_QID_RANGE_MASK,
- GLBL_ERR_STAT_ERR_TRQ_MASK,
- &qdma_s80_hard_hw_trq_err_process
- },
- {
- QDMA_S80_HARD_TRQ_ERR_VF_ACCESS_ERR,
- "VF attempted to access Global register space or Function map",
- QDMA_S80_HARD_GLBL_TRQ_ERR_MSK_ADDR,
- QDMA_S80_HARD_GLBL_TRQ_ERR_STS_ADDR,
- GLBL_TRQ_ERR_STS_VF_ACCESS_ERR_MASK,
- GLBL_ERR_STAT_ERR_TRQ_MASK,
- &qdma_s80_hard_hw_trq_err_process
- },
- {
- QDMA_S80_HARD_TRQ_ERR_TCP_TIMEOUT,
- "Timeout on request to dma internal csr register",
- QDMA_S80_HARD_GLBL_TRQ_ERR_MSK_ADDR,
- QDMA_S80_HARD_GLBL_TRQ_ERR_STS_ADDR,
- GLBL_TRQ_ERR_STS_TCP_TIMEOUT_MASK,
- GLBL_ERR_STAT_ERR_TRQ_MASK,
- &qdma_s80_hard_hw_trq_err_process
- },
- {
- QDMA_S80_HARD_TRQ_ERR_ALL,
- "All TRQ errors",
- QDMA_S80_HARD_GLBL_TRQ_ERR_MSK_ADDR,
- QDMA_S80_HARD_GLBL_TRQ_ERR_STS_ADDR,
- QDMA_S80_HARD_GLBL_TRQ_ERR_ALL_MASK,
- GLBL_ERR_STAT_ERR_TRQ_MASK,
- &qdma_s80_hard_hw_trq_err_process
- },
-
- /* C2H Errors*/
- {
- QDMA_S80_HARD_ST_C2H_ERR_MTY_MISMATCH,
- "MTY mismatch error",
- QDMA_S80_HARD_C2H_ERR_MASK_ADDR,
- QDMA_S80_HARD_C2H_ERR_STAT_ADDR,
- C2H_ERR_STAT_MTY_MISMATCH_MASK,
- GLBL_ERR_STAT_ERR_C2H_ST_MASK,
- &qdma_s80_hard_hw_st_c2h_err_process
- },
- {
- QDMA_S80_HARD_ST_C2H_ERR_LEN_MISMATCH,
- "Packet length mismatch error",
- QDMA_S80_HARD_C2H_ERR_MASK_ADDR,
- QDMA_S80_HARD_C2H_ERR_STAT_ADDR,
- C2H_ERR_STAT_LEN_MISMATCH_MASK,
- GLBL_ERR_STAT_ERR_C2H_ST_MASK,
- &qdma_s80_hard_hw_st_c2h_err_process
- },
- {
- QDMA_S80_HARD_ST_C2H_ERR_QID_MISMATCH,
- "Qid mismatch error",
- QDMA_S80_HARD_C2H_ERR_MASK_ADDR,
- QDMA_S80_HARD_C2H_ERR_STAT_ADDR,
- C2H_ERR_STAT_QID_MISMATCH_MASK,
- GLBL_ERR_STAT_ERR_C2H_ST_MASK,
- &qdma_s80_hard_hw_st_c2h_err_process
- },
- {
- QDMA_S80_HARD_ST_C2H_ERR_DESC_RSP_ERR,
- "Descriptor error bit set",
- QDMA_S80_HARD_C2H_ERR_MASK_ADDR,
- QDMA_S80_HARD_C2H_ERR_STAT_ADDR,
- C2H_ERR_STAT_DESC_RSP_ERR_MASK,
- GLBL_ERR_STAT_ERR_C2H_ST_MASK,
- &qdma_s80_hard_hw_st_c2h_err_process
- },
- {
- QDMA_S80_HARD_ST_C2H_ERR_ENG_WPL_DATA_PAR_ERR,
- "Data parity error",
- QDMA_S80_HARD_C2H_ERR_MASK_ADDR,
- QDMA_S80_HARD_C2H_ERR_STAT_ADDR,
- C2H_ERR_STAT_ENG_WPL_DATA_PAR_ERR_MASK,
- GLBL_ERR_STAT_ERR_C2H_ST_MASK,
- &qdma_s80_hard_hw_st_c2h_err_process
- },
- {
- QDMA_S80_HARD_ST_C2H_ERR_MSI_INT_FAIL,
- "MSI got a fail response error",
- QDMA_S80_HARD_C2H_ERR_MASK_ADDR,
- QDMA_S80_HARD_C2H_ERR_STAT_ADDR,
- C2H_ERR_STAT_MSI_INT_FAIL_MASK,
- GLBL_ERR_STAT_ERR_C2H_ST_MASK,
- &qdma_s80_hard_hw_st_c2h_err_process
- },
- {
- QDMA_S80_HARD_ST_C2H_ERR_ERR_DESC_CNT,
- "Descriptor count error",
- QDMA_S80_HARD_C2H_ERR_MASK_ADDR,
- QDMA_S80_HARD_C2H_ERR_STAT_ADDR,
- C2H_ERR_STAT_ERR_DESC_CNT_MASK,
- GLBL_ERR_STAT_ERR_C2H_ST_MASK,
- &qdma_s80_hard_hw_st_c2h_err_process
- },
- {
- QDMA_S80_HARD_ST_C2H_ERR_PORTID_CTXT_MISMATCH,
- "Port id in packet and pfetch ctxt mismatch error",
- QDMA_S80_HARD_C2H_ERR_MASK_ADDR,
- QDMA_S80_HARD_C2H_ERR_STAT_ADDR,
- C2H_ERR_STAT_PORT_ID_CTXT_MISMATCH_MASK,
- GLBL_ERR_STAT_ERR_C2H_ST_MASK,
- &qdma_s80_hard_hw_st_c2h_err_process
- },
- {
- QDMA_S80_HARD_ST_C2H_ERR_PORTID_BYP_IN_MISMATCH,
- "Port id in packet and bypass in mismatch error",
- QDMA_S80_HARD_C2H_ERR_MASK_ADDR,
- QDMA_S80_HARD_C2H_ERR_STAT_ADDR,
- C2H_ERR_STAT_PORT_ID_CTXT_MISMATCH_MASK,
- GLBL_ERR_STAT_ERR_C2H_ST_MASK,
- &qdma_s80_hard_hw_st_c2h_err_process
- },
- {
- QDMA_S80_HARD_ST_C2H_ERR_WRB_INV_Q_ERR,
- "Writeback on invalid queue error",
- QDMA_S80_HARD_C2H_ERR_MASK_ADDR,
- QDMA_S80_HARD_C2H_ERR_STAT_ADDR,
- C2H_ERR_STAT_WRB_INV_Q_ERR_MASK,
- GLBL_ERR_STAT_ERR_C2H_ST_MASK,
- &qdma_s80_hard_hw_st_c2h_err_process
- },
- {
- QDMA_S80_HARD_ST_C2H_ERR_WRB_QFULL_ERR,
- "Completion queue gets full error",
- QDMA_S80_HARD_C2H_ERR_MASK_ADDR,
- QDMA_S80_HARD_C2H_ERR_STAT_ADDR,
- C2H_ERR_STAT_WRB_QFULL_ERR_MASK,
- GLBL_ERR_STAT_ERR_C2H_ST_MASK,
- &qdma_s80_hard_hw_st_c2h_err_process
- },
- {
- QDMA_S80_HARD_ST_C2H_ERR_WRB_CIDX_ERR,
- "Bad CIDX update by the software error",
- QDMA_S80_HARD_C2H_ERR_MASK_ADDR,
- QDMA_S80_HARD_C2H_ERR_STAT_ADDR,
- C2H_ERR_STAT_WRB_CIDX_ERR_MASK,
- GLBL_ERR_STAT_ERR_C2H_ST_MASK,
- &qdma_s80_hard_hw_st_c2h_err_process
- },
- {
- QDMA_S80_HARD_ST_C2H_ERR_WRB_PRTY_ERR,
- "C2H completion Parity error",
- QDMA_S80_HARD_C2H_ERR_MASK_ADDR,
- QDMA_S80_HARD_C2H_ERR_STAT_ADDR,
- C2H_ERR_STAT_WRB_PRTY_ERR_MASK,
- GLBL_ERR_STAT_ERR_C2H_ST_MASK,
- &qdma_s80_hard_hw_st_c2h_err_process
- },
- {
- QDMA_S80_HARD_ST_C2H_ERR_ALL,
- "All C2h errors",
- QDMA_S80_HARD_C2H_ERR_MASK_ADDR,
- QDMA_S80_HARD_C2H_ERR_STAT_ADDR,
- QDMA_S80_HARD_C2H_ERR_ALL_MASK,
- GLBL_ERR_STAT_ERR_C2H_ST_MASK,
- &qdma_s80_hard_hw_st_c2h_err_process
- },
-
- /* C2H fatal errors */
- {
- QDMA_S80_HARD_ST_FATAL_ERR_MTY_MISMATCH,
- "Fatal MTY mismatch error",
- QDMA_S80_HARD_C2H_FATAL_ERR_MASK_ADDR,
- QDMA_S80_HARD_C2H_FATAL_ERR_STAT_ADDR,
- C2H_FATAL_ERR_STAT_MTY_MISMATCH_MASK,
- GLBL_ERR_STAT_ERR_C2H_ST_MASK,
- &qdma_s80_hard_hw_st_c2h_err_process
- },
- {
- QDMA_S80_HARD_ST_FATAL_ERR_LEN_MISMATCH,
- "Fatal Len mismatch error",
- QDMA_S80_HARD_C2H_FATAL_ERR_MASK_ADDR,
- QDMA_S80_HARD_C2H_FATAL_ERR_STAT_ADDR,
- C2H_FATAL_ERR_STAT_LEN_MISMATCH_MASK,
- GLBL_ERR_STAT_ERR_C2H_ST_MASK,
- &qdma_s80_hard_hw_st_c2h_err_process
- },
- {
- QDMA_S80_HARD_ST_FATAL_ERR_QID_MISMATCH,
- "Fatal Qid mismatch error",
- QDMA_S80_HARD_C2H_FATAL_ERR_MASK_ADDR,
- QDMA_S80_HARD_C2H_FATAL_ERR_STAT_ADDR,
- C2H_FATAL_ERR_STAT_QID_MISMATCH_MASK,
- GLBL_ERR_STAT_ERR_C2H_ST_MASK,
- &qdma_s80_hard_hw_st_c2h_err_process
- },
- {
- QDMA_S80_HARD_ST_FATAL_ERR_TIMER_FIFO_RAM_RDBE,
- "RAM double bit fatal error",
- QDMA_S80_HARD_C2H_FATAL_ERR_MASK_ADDR,
- QDMA_S80_HARD_C2H_FATAL_ERR_STAT_ADDR,
- C2H_FATAL_ERR_STAT_TIMER_FIFO_RAM_RDBE_MASK,
- GLBL_ERR_STAT_ERR_C2H_ST_MASK,
- &qdma_s80_hard_hw_st_c2h_err_process
- },
- {
- QDMA_S80_HARD_ST_FATAL_ERR_PFCH_II_RAM_RDBE,
- "RAM double bit fatal error",
- QDMA_S80_HARD_C2H_FATAL_ERR_MASK_ADDR,
- QDMA_S80_HARD_C2H_FATAL_ERR_STAT_ADDR,
- C2H_FATAL_ERR_STAT_PFCH_LL_RAM_RDBE_MASK,
- GLBL_ERR_STAT_ERR_C2H_ST_MASK,
- &qdma_s80_hard_hw_st_c2h_err_process
- },
- {
- QDMA_S80_HARD_ST_FATAL_ERR_WRB_CTXT_RAM_RDBE,
- "RAM double bit fatal error",
- QDMA_S80_HARD_C2H_FATAL_ERR_MASK_ADDR,
- QDMA_S80_HARD_C2H_FATAL_ERR_STAT_ADDR,
- C2H_FATAL_ERR_STAT_WRB_CTXT_RAM_RDBE_MASK,
- GLBL_ERR_STAT_ERR_C2H_ST_MASK,
- &qdma_s80_hard_hw_st_c2h_err_process
- },
- {
- QDMA_S80_HARD_ST_FATAL_ERR_PFCH_CTXT_RAM_RDBE,
- "RAM double bit fatal error",
- QDMA_S80_HARD_C2H_FATAL_ERR_MASK_ADDR,
- QDMA_S80_HARD_C2H_FATAL_ERR_STAT_ADDR,
- C2H_FATAL_ERR_STAT_PFCH_CTXT_RAM_RDBE_MASK,
- GLBL_ERR_STAT_ERR_C2H_ST_MASK,
- &qdma_s80_hard_hw_st_c2h_err_process
- },
- {
- QDMA_S80_HARD_ST_FATAL_ERR_DESC_REQ_FIFO_RAM_RDBE,
- "RAM double bit fatal error",
- QDMA_S80_HARD_C2H_FATAL_ERR_MASK_ADDR,
- QDMA_S80_HARD_C2H_FATAL_ERR_STAT_ADDR,
- C2H_FATAL_ERR_STAT_DESC_REQ_FIFO_RAM_RDBE_MASK,
- GLBL_ERR_STAT_ERR_C2H_ST_MASK,
- &qdma_s80_hard_hw_st_c2h_err_process
- },
- {
- QDMA_S80_HARD_ST_FATAL_ERR_INT_CTXT_RAM_RDBE,
- "RAM double bit fatal error",
- QDMA_S80_HARD_C2H_FATAL_ERR_MASK_ADDR,
- QDMA_S80_HARD_C2H_FATAL_ERR_STAT_ADDR,
- C2H_FATAL_ERR_STAT_INT_CTXT_RAM_RDBE_MASK,
- GLBL_ERR_STAT_ERR_C2H_ST_MASK,
- &qdma_s80_hard_hw_st_c2h_err_process
- },
- {
- QDMA_S80_HARD_ST_FATAL_ERR_INT_QID2VEC_RAM_RDBE,
- "RAM double bit fatal error",
- QDMA_S80_HARD_C2H_FATAL_ERR_MASK_ADDR,
- QDMA_S80_HARD_C2H_FATAL_ERR_STAT_ADDR,
- C2H_FATAL_ERR_STAT_INT_QID2VEC_RAM_RDBE_MASK,
- GLBL_ERR_STAT_ERR_C2H_ST_MASK,
- &qdma_s80_hard_hw_st_c2h_err_process
- },
- {
- QDMA_S80_HARD_ST_FATAL_ERR_WRB_COAL_DATA_RAM_RDBE,
- "RAM double bit fatal error",
- QDMA_S80_HARD_C2H_FATAL_ERR_MASK_ADDR,
- QDMA_S80_HARD_C2H_FATAL_ERR_STAT_ADDR,
- C2H_FATAL_ERR_STAT_WRB_COAL_DATA_RAM_RDBE_MASK,
- GLBL_ERR_STAT_ERR_C2H_ST_MASK,
- &qdma_s80_hard_hw_st_c2h_err_process
- },
- {
- QDMA_S80_HARD_ST_FATAL_ERR_TUSER_FIFO_RAM_RDBE,
- "RAM double bit fatal error",
- QDMA_S80_HARD_C2H_FATAL_ERR_MASK_ADDR,
- QDMA_S80_HARD_C2H_FATAL_ERR_STAT_ADDR,
- C2H_FATAL_ERR_STAT_TUSER_FIFO_RAM_RDBE_MASK,
- GLBL_ERR_STAT_ERR_C2H_ST_MASK,
- &qdma_s80_hard_hw_st_c2h_err_process
- },
- {
- QDMA_S80_HARD_ST_FATAL_ERR_QID_FIFO_RAM_RDBE,
- "RAM double bit fatal error",
- QDMA_S80_HARD_C2H_FATAL_ERR_MASK_ADDR,
- QDMA_S80_HARD_C2H_FATAL_ERR_STAT_ADDR,
- C2H_FATAL_ERR_STAT_QID_FIFO_RAM_RDBE_MASK,
- GLBL_ERR_STAT_ERR_C2H_ST_MASK,
- &qdma_s80_hard_hw_st_c2h_err_process
- },
- {
- QDMA_S80_HARD_ST_FATAL_ERR_PAYLOAD_FIFO_RAM_RDBE,
- "RAM double bit fatal error",
- QDMA_S80_HARD_C2H_FATAL_ERR_MASK_ADDR,
- QDMA_S80_HARD_C2H_FATAL_ERR_STAT_ADDR,
- C2H_FATAL_ERR_STAT_PLD_FIFO_RAM_RDBE_MASK,
- GLBL_ERR_STAT_ERR_C2H_ST_MASK,
- &qdma_s80_hard_hw_st_c2h_err_process
- },
- {
- QDMA_S80_HARD_ST_FATAL_ERR_WPL_DATA_PAR_ERR,
- "RAM double bit fatal error",
- QDMA_S80_HARD_C2H_FATAL_ERR_MASK_ADDR,
- QDMA_S80_HARD_C2H_FATAL_ERR_STAT_ADDR,
- C2H_FATAL_ERR_STAT_WPL_DATA_PAR_ERR_MASK,
- GLBL_ERR_STAT_ERR_C2H_ST_MASK,
- &qdma_s80_hard_hw_st_c2h_err_process
- },
- {
- QDMA_S80_HARD_ST_FATAL_ERR_ALL,
- "All fatal errors",
- QDMA_S80_HARD_C2H_FATAL_ERR_MASK_ADDR,
- QDMA_S80_HARD_C2H_FATAL_ERR_STAT_ADDR,
- QDMA_S80_HARD_C2H_FATAL_ERR_ALL_MASK,
- GLBL_ERR_STAT_ERR_C2H_ST_MASK,
- &qdma_s80_hard_hw_st_c2h_err_process
- },
-
- /* H2C St errors */
- {
- QDMA_S80_HARD_ST_H2C_ERR_ZERO_LEN_DESC_ERR,
- "Zero length descriptor error",
- QDMA_S80_HARD_H2C_ERR_MASK_ADDR,
- QDMA_S80_HARD_H2C_ERR_STAT_ADDR,
- H2C_ERR_STAT_ZERO_LEN_DS_MASK,
- GLBL_ERR_STAT_ERR_H2C_ST_MASK,
- &qdma_s80_hard_hw_st_h2c_err_process
- },
- {
- QDMA_S80_HARD_ST_H2C_ERR_SDI_MRKR_REQ_MOP_ERR,
- "A non-EOP descriptor received",
- QDMA_S80_HARD_H2C_ERR_MASK_ADDR,
- QDMA_S80_HARD_H2C_ERR_STAT_ADDR,
- H2C_ERR_STAT_SDI_MRKR_REQ_MOP_ERR_MASK,
- GLBL_ERR_STAT_ERR_H2C_ST_MASK,
- &qdma_s80_hard_hw_st_h2c_err_process
- },
- {
- QDMA_S80_HARD_ST_H2C_ERR_NO_DMA_DSC,
- "No DMA descriptor received error",
- QDMA_S80_HARD_H2C_ERR_MASK_ADDR,
- QDMA_S80_HARD_H2C_ERR_STAT_ADDR,
- H2C_ERR_STAT_NO_DMA_DS_MASK,
- GLBL_ERR_STAT_ERR_H2C_ST_MASK,
- &qdma_s80_hard_hw_st_h2c_err_process
- },
- {
- QDMA_S80_HARD_ST_H2C_ERR_DBE,
- "Double bit error detected on H2C-ST data error",
- QDMA_S80_HARD_H2C_ERR_MASK_ADDR,
- QDMA_S80_HARD_H2C_ERR_STAT_ADDR,
- H2C_ERR_STAT_DBE_MASK,
- GLBL_ERR_STAT_ERR_H2C_ST_MASK,
- &qdma_s80_hard_hw_st_h2c_err_process
- },
- {
- QDMA_S80_HARD_ST_H2C_ERR_SBE,
- "Single bit error detected on H2C-ST data error",
- QDMA_S80_HARD_H2C_ERR_MASK_ADDR,
- QDMA_S80_HARD_H2C_ERR_STAT_ADDR,
- H2C_ERR_STAT_SBE_MASK,
- GLBL_ERR_STAT_ERR_H2C_ST_MASK,
- &qdma_s80_hard_hw_st_h2c_err_process
- },
- {
- QDMA_S80_HARD_ST_H2C_ERR_ALL,
- "All H2C errors",
- QDMA_S80_HARD_H2C_ERR_MASK_ADDR,
- QDMA_S80_HARD_H2C_ERR_STAT_ADDR,
- QDMA_S80_HARD_H2C_ERR_ALL_MASK,
- GLBL_ERR_STAT_ERR_H2C_ST_MASK,
- &qdma_s80_hard_hw_st_h2c_err_process
- },
-
- /* SBE errors */
- {
- QDMA_S80_HARD_SBE_ERR_MI_H2C0_DAT,
- "H2C MM data buffer single bit ECC error",
- QDMA_S80_HARD_RAM_SBE_MSK_A_ADDR,
- QDMA_S80_HARD_RAM_SBE_STS_A_ADDR,
- RAM_SBE_STS_A_MI_H2C0_DAT_MASK,
- GLBL_ERR_STAT_ERR_RAM_SBE_MASK,
- &qdma_s80_hard_hw_ram_sbe_err_process
- },
- {
- QDMA_S80_HARD_SBE_ERR_MI_C2H0_DAT,
- "C2H MM data buffer single bit ECC error",
- QDMA_S80_HARD_RAM_SBE_MSK_A_ADDR,
- QDMA_S80_HARD_RAM_SBE_STS_A_ADDR,
- RAM_SBE_STS_A_MI_C2H0_DAT_MASK,
- GLBL_ERR_STAT_ERR_RAM_SBE_MASK,
- &qdma_s80_hard_hw_ram_sbe_err_process
- },
- {
- QDMA_S80_HARD_SBE_ERR_H2C_RD_BRG_DAT,
- "Bridge master read single bit ECC error",
- QDMA_S80_HARD_RAM_SBE_MSK_A_ADDR,
- QDMA_S80_HARD_RAM_SBE_STS_A_ADDR,
- RAM_SBE_STS_A_H2C_RD_BRG_DAT_MASK,
- GLBL_ERR_STAT_ERR_RAM_SBE_MASK,
- &qdma_s80_hard_hw_ram_sbe_err_process
- },
- {
- QDMA_S80_HARD_SBE_ERR_H2C_WR_BRG_DAT,
- "Bridge master write single bit ECC error",
- QDMA_S80_HARD_RAM_SBE_MSK_A_ADDR,
- QDMA_S80_HARD_RAM_SBE_STS_A_ADDR,
- RAM_SBE_STS_A_H2C_WR_BRG_DAT_MASK,
- GLBL_ERR_STAT_ERR_RAM_SBE_MASK,
- &qdma_s80_hard_hw_ram_sbe_err_process
- },
- {
- QDMA_S80_HARD_SBE_ERR_C2H_RD_BRG_DAT,
- "Bridge slave read data buffer single bit ECC error",
- QDMA_S80_HARD_RAM_SBE_MSK_A_ADDR,
- QDMA_S80_HARD_RAM_SBE_STS_A_ADDR,
- RAM_SBE_STS_A_C2H_RD_BRG_DAT_MASK,
- GLBL_ERR_STAT_ERR_RAM_SBE_MASK,
- &qdma_s80_hard_hw_ram_sbe_err_process
- },
- {
- QDMA_S80_HARD_SBE_ERR_C2H_WR_BRG_DAT,
- "Bridge slave write data buffer single bit ECC error",
- QDMA_S80_HARD_RAM_SBE_MSK_A_ADDR,
- QDMA_S80_HARD_RAM_SBE_STS_A_ADDR,
- RAM_SBE_STS_A_C2H_WR_BRG_DAT_MASK,
- GLBL_ERR_STAT_ERR_RAM_SBE_MASK,
- &qdma_s80_hard_hw_ram_sbe_err_process
- },
- {
- QDMA_S80_HARD_SBE_ERR_FUNC_MAP,
- "Function map RAM single bit ECC error",
- QDMA_S80_HARD_RAM_SBE_MSK_A_ADDR,
- QDMA_S80_HARD_RAM_SBE_STS_A_ADDR,
- RAM_SBE_STS_A_FUNC_MAP_MASK,
- GLBL_ERR_STAT_ERR_RAM_SBE_MASK,
- &qdma_s80_hard_hw_ram_sbe_err_process
- },
- {
- QDMA_S80_HARD_SBE_ERR_DSC_HW_CTXT,
- "Descriptor engine hardware context RAM single bit ECC error",
- QDMA_S80_HARD_RAM_SBE_MSK_A_ADDR,
- QDMA_S80_HARD_RAM_SBE_STS_A_ADDR,
- RAM_SBE_STS_A_DSC_HW_CTXT_MASK,
- GLBL_ERR_STAT_ERR_RAM_SBE_MASK,
- &qdma_s80_hard_hw_ram_sbe_err_process
- },
- {
- QDMA_S80_HARD_SBE_ERR_DSC_CRD_RCV,
- "Descriptor engine receive credit context RAM single bit ECC error",
- QDMA_S80_HARD_RAM_SBE_MSK_A_ADDR,
- QDMA_S80_HARD_RAM_SBE_STS_A_ADDR,
- RAM_SBE_STS_A_DSC_CRD_RCV_MASK,
- GLBL_ERR_STAT_ERR_RAM_SBE_MASK,
- &qdma_s80_hard_hw_ram_sbe_err_process
- },
- {
- QDMA_S80_HARD_SBE_ERR_DSC_SW_CTXT,
- "Descriptor engine software context RAM single bit ECC error",
- QDMA_S80_HARD_RAM_SBE_MSK_A_ADDR,
- QDMA_S80_HARD_RAM_SBE_STS_A_ADDR,
- RAM_SBE_STS_A_DSC_SW_CTXT_MASK,
- GLBL_ERR_STAT_ERR_RAM_SBE_MASK,
- &qdma_s80_hard_hw_ram_sbe_err_process
- },
- {
- QDMA_S80_HARD_SBE_ERR_DSC_CPLI,
- "Descriptor engine fetch completion information RAM single bit ECC error",
- QDMA_S80_HARD_RAM_SBE_MSK_A_ADDR,
- QDMA_S80_HARD_RAM_SBE_STS_A_ADDR,
- RAM_SBE_STS_A_DSC_CPLI_MASK,
- GLBL_ERR_STAT_ERR_RAM_SBE_MASK,
- &qdma_s80_hard_hw_ram_sbe_err_process
- },
- {
- QDMA_S80_HARD_SBE_ERR_DSC_CPLD,
- "Descriptor engine fetch completion data RAM single bit ECC error",
- QDMA_S80_HARD_RAM_SBE_MSK_A_ADDR,
- QDMA_S80_HARD_RAM_SBE_STS_A_ADDR,
- RAM_SBE_STS_A_DSC_CPLD_MASK,
- GLBL_ERR_STAT_ERR_RAM_SBE_MASK,
- &qdma_s80_hard_hw_ram_sbe_err_process
- },
- {
- QDMA_S80_HARD_SBE_ERR_PASID_CTXT_RAM,
- "Pasid ctxt FIFO RAM single bit ECC error",
- QDMA_S80_HARD_RAM_SBE_MSK_A_ADDR,
- QDMA_S80_HARD_RAM_SBE_STS_A_ADDR,
- RAM_SBE_STS_A_PASID_CTXT_RAM_MASK,
- GLBL_ERR_STAT_ERR_RAM_SBE_MASK,
- &qdma_s80_hard_hw_ram_sbe_err_process
- },
- {
- QDMA_S80_HARD_SBE_ERR_TIMER_FIFO_RAM,
- "Timer fifo RAM single bit ECC error",
- QDMA_S80_HARD_RAM_SBE_MSK_A_ADDR,
- QDMA_S80_HARD_RAM_SBE_STS_A_ADDR,
- RAM_SBE_STS_A_TIMER_FIFO_RAM_MASK,
- GLBL_ERR_STAT_ERR_RAM_SBE_MASK,
- &qdma_s80_hard_hw_ram_sbe_err_process
- },
- {
- QDMA_S80_HARD_SBE_ERR_PAYLOAD_FIFO_RAM,
- "C2H ST payload FIFO RAM single bit ECC error",
- QDMA_S80_HARD_RAM_SBE_MSK_A_ADDR,
- QDMA_S80_HARD_RAM_SBE_STS_A_ADDR,
- RAM_SBE_STS_A_PLD_FIFO_RAM_MASK,
- GLBL_ERR_STAT_ERR_RAM_SBE_MASK,
- &qdma_s80_hard_hw_ram_sbe_err_process
- },
- {
- QDMA_S80_HARD_SBE_ERR_QID_FIFO_RAM,
- "C2H ST QID FIFO RAM single bit ECC error",
- QDMA_S80_HARD_RAM_SBE_MSK_A_ADDR,
- QDMA_S80_HARD_RAM_SBE_STS_A_ADDR,
- RAM_SBE_STS_A_QID_FIFO_RAM_MASK,
- GLBL_ERR_STAT_ERR_RAM_SBE_MASK,
- &qdma_s80_hard_hw_ram_sbe_err_process
- },
- {
- QDMA_S80_HARD_SBE_ERR_TUSER_FIFO_RAM,
- "C2H ST TUSER FIFO RAM single bit ECC error",
- QDMA_S80_HARD_RAM_SBE_MSK_A_ADDR,
- QDMA_S80_HARD_RAM_SBE_STS_A_ADDR,
- RAM_SBE_STS_A_TUSER_FIFO_RAM_MASK,
- GLBL_ERR_STAT_ERR_RAM_SBE_MASK,
- &qdma_s80_hard_hw_ram_sbe_err_process
- },
- {
- QDMA_S80_HARD_SBE_ERR_WRB_COAL_DATA_RAM,
- "Writeback Coalescing RAM single bit ECC error",
- QDMA_S80_HARD_RAM_SBE_MSK_A_ADDR,
- QDMA_S80_HARD_RAM_SBE_STS_A_ADDR,
- RAM_SBE_STS_A_WRB_COAL_DATA_RAM_MASK,
- GLBL_ERR_STAT_ERR_RAM_SBE_MASK,
- &qdma_s80_hard_hw_ram_sbe_err_process
- },
- {
- QDMA_S80_HARD_SBE_ERR_INT_QID2VEC_RAM,
- "Interrupt QID2VEC RAM single bit ECC error",
- QDMA_S80_HARD_RAM_SBE_MSK_A_ADDR,
- QDMA_S80_HARD_RAM_SBE_STS_A_ADDR,
- RAM_SBE_STS_A_INT_QID2VEC_RAM_MASK,
- GLBL_ERR_STAT_ERR_RAM_SBE_MASK,
- &qdma_s80_hard_hw_ram_sbe_err_process
- },
- {
- QDMA_S80_HARD_SBE_ERR_INT_CTXT_RAM,
- "Interrupt context RAM single bit ECC error",
- QDMA_S80_HARD_RAM_SBE_MSK_A_ADDR,
- QDMA_S80_HARD_RAM_SBE_STS_A_ADDR,
- RAM_SBE_STS_A_INT_CTXT_RAM_MASK,
- GLBL_ERR_STAT_ERR_RAM_SBE_MASK,
- &qdma_s80_hard_hw_ram_sbe_err_process
- },
- {
- QDMA_S80_HARD_SBE_ERR_DESC_REQ_FIFO_RAM,
- "C2H ST descriptor request RAM single bit ECC error",
- QDMA_S80_HARD_RAM_SBE_MSK_A_ADDR,
- QDMA_S80_HARD_RAM_SBE_STS_A_ADDR,
- RAM_SBE_STS_A_DESC_REQ_FIFO_RAM_MASK,
- GLBL_ERR_STAT_ERR_RAM_SBE_MASK,
- &qdma_s80_hard_hw_ram_sbe_err_process
- },
- {
- QDMA_S80_HARD_SBE_ERR_PFCH_CTXT_RAM,
- "C2H ST prefetch RAM single bit ECC error",
- QDMA_S80_HARD_RAM_SBE_MSK_A_ADDR,
- QDMA_S80_HARD_RAM_SBE_STS_A_ADDR,
- RAM_SBE_STS_A_PFCH_CTXT_RAM_MASK,
- GLBL_ERR_STAT_ERR_RAM_SBE_MASK,
- &qdma_s80_hard_hw_ram_sbe_err_process
- },
- {
- QDMA_S80_HARD_SBE_ERR_WRB_CTXT_RAM,
- "C2H ST completion context RAM single bit ECC error",
- QDMA_S80_HARD_RAM_SBE_MSK_A_ADDR,
- QDMA_S80_HARD_RAM_SBE_STS_A_ADDR,
- RAM_SBE_STS_A_WRB_CTXT_RAM_MASK,
- GLBL_ERR_STAT_ERR_RAM_SBE_MASK,
- &qdma_s80_hard_hw_ram_sbe_err_process
- },
- {
- QDMA_S80_HARD_SBE_ERR_PFCH_LL_RAM,
- "C2H ST prefetch list RAM single bit ECC error",
- QDMA_S80_HARD_RAM_SBE_MSK_A_ADDR,
- QDMA_S80_HARD_RAM_SBE_STS_A_ADDR,
- RAM_SBE_STS_A_PFCH_LL_RAM_MASK,
- GLBL_ERR_STAT_ERR_RAM_SBE_MASK,
- &qdma_s80_hard_hw_ram_sbe_err_process
- },
- {
- QDMA_S80_HARD_SBE_ERR_ALL,
- "All SBE errors",
- QDMA_S80_HARD_RAM_SBE_MSK_A_ADDR,
- QDMA_S80_HARD_RAM_SBE_STS_A_ADDR,
- QDMA_S80_HARD_SBE_ERR_ALL_MASK,
- GLBL_ERR_STAT_ERR_RAM_SBE_MASK,
- &qdma_s80_hard_hw_ram_sbe_err_process
- },
-
-
- /* DBE errors */
- {
- QDMA_S80_HARD_DBE_ERR_MI_H2C0_DAT,
- "H2C MM data buffer single bit ECC error",
- QDMA_S80_HARD_RAM_DBE_MSK_A_ADDR,
- QDMA_S80_HARD_RAM_DBE_STS_A_ADDR,
- RAM_DBE_STS_A_MI_H2C0_DAT_MASK,
- GLBL_ERR_STAT_ERR_RAM_DBE_MASK,
- &qdma_s80_hard_hw_ram_dbe_err_process
- },
- {
- QDMA_S80_HARD_DBE_ERR_MI_C2H0_DAT,
- "C2H MM data buffer single bit ECC error",
- QDMA_S80_HARD_RAM_DBE_MSK_A_ADDR,
- QDMA_S80_HARD_RAM_DBE_STS_A_ADDR,
- RAM_DBE_STS_A_MI_C2H0_DAT_MASK,
- GLBL_ERR_STAT_ERR_RAM_DBE_MASK,
- &qdma_s80_hard_hw_ram_dbe_err_process
- },
- {
- QDMA_S80_HARD_DBE_ERR_H2C_RD_BRG_DAT,
- "Bridge master read single bit ECC error",
- QDMA_S80_HARD_RAM_DBE_MSK_A_ADDR,
- QDMA_S80_HARD_RAM_DBE_STS_A_ADDR,
- RAM_DBE_STS_A_H2C_RD_BRG_DAT_MASK,
- GLBL_ERR_STAT_ERR_RAM_DBE_MASK,
- &qdma_s80_hard_hw_ram_dbe_err_process
- },
- {
- QDMA_S80_HARD_DBE_ERR_H2C_WR_BRG_DAT,
- "Bridge master write single bit ECC error",
- QDMA_S80_HARD_RAM_DBE_MSK_A_ADDR,
- QDMA_S80_HARD_RAM_DBE_STS_A_ADDR,
- RAM_DBE_STS_A_H2C_WR_BRG_DAT_MASK,
- GLBL_ERR_STAT_ERR_RAM_DBE_MASK,
- &qdma_s80_hard_hw_ram_dbe_err_process
- },
- {
- QDMA_S80_HARD_DBE_ERR_C2H_RD_BRG_DAT,
- "Bridge slave read data buffer single bit ECC error",
- QDMA_S80_HARD_RAM_DBE_MSK_A_ADDR,
- QDMA_S80_HARD_RAM_DBE_STS_A_ADDR,
- RAM_DBE_STS_A_C2H_RD_BRG_DAT_MASK,
- GLBL_ERR_STAT_ERR_RAM_DBE_MASK,
- &qdma_s80_hard_hw_ram_dbe_err_process
- },
- {
- QDMA_S80_HARD_DBE_ERR_C2H_WR_BRG_DAT,
- "Bridge slave write data buffer single bit ECC error",
- QDMA_S80_HARD_RAM_DBE_MSK_A_ADDR,
- QDMA_S80_HARD_RAM_DBE_STS_A_ADDR,
- RAM_DBE_STS_A_C2H_WR_BRG_DAT_MASK,
- GLBL_ERR_STAT_ERR_RAM_DBE_MASK,
- &qdma_s80_hard_hw_ram_dbe_err_process
- },
- {
- QDMA_S80_HARD_DBE_ERR_FUNC_MAP,
- "Function map RAM single bit ECC error",
- QDMA_S80_HARD_RAM_DBE_MSK_A_ADDR,
- QDMA_S80_HARD_RAM_DBE_STS_A_ADDR,
- RAM_DBE_STS_A_FUNC_MAP_MASK,
- GLBL_ERR_STAT_ERR_RAM_DBE_MASK,
- &qdma_s80_hard_hw_ram_dbe_err_process
- },
- {
- QDMA_S80_HARD_DBE_ERR_DSC_HW_CTXT,
- "Descriptor engine hardware context RAM single bit ECC error",
- QDMA_S80_HARD_RAM_DBE_MSK_A_ADDR,
- QDMA_S80_HARD_RAM_DBE_STS_A_ADDR,
- RAM_DBE_STS_A_DSC_HW_CTXT_MASK,
- GLBL_ERR_STAT_ERR_RAM_DBE_MASK,
- &qdma_s80_hard_hw_ram_dbe_err_process
- },
- {
- QDMA_S80_HARD_DBE_ERR_DSC_CRD_RCV,
- "Descriptor engine receive credit context RAM single bit ECC error",
- QDMA_S80_HARD_RAM_DBE_MSK_A_ADDR,
- QDMA_S80_HARD_RAM_DBE_STS_A_ADDR,
- RAM_DBE_STS_A_DSC_CRD_RCV_MASK,
- GLBL_ERR_STAT_ERR_RAM_DBE_MASK,
- &qdma_s80_hard_hw_ram_dbe_err_process
- },
- {
- QDMA_S80_HARD_DBE_ERR_DSC_SW_CTXT,
- "Descriptor engine software context RAM single bit ECC error",
- QDMA_S80_HARD_RAM_DBE_MSK_A_ADDR,
- QDMA_S80_HARD_RAM_DBE_STS_A_ADDR,
- RAM_DBE_STS_A_DSC_SW_CTXT_MASK,
- GLBL_ERR_STAT_ERR_RAM_DBE_MASK,
- &qdma_s80_hard_hw_ram_dbe_err_process
- },
- {
- QDMA_S80_HARD_DBE_ERR_DSC_CPLI,
- "Descriptor engine fetch completion information RAM single bit ECC error",
- QDMA_S80_HARD_RAM_DBE_MSK_A_ADDR,
- QDMA_S80_HARD_RAM_DBE_STS_A_ADDR,
- RAM_DBE_STS_A_DSC_CPLI_MASK,
- GLBL_ERR_STAT_ERR_RAM_DBE_MASK,
- &qdma_s80_hard_hw_ram_dbe_err_process
- },
- {
- QDMA_S80_HARD_DBE_ERR_DSC_CPLD,
- "Descriptor engine fetch completion data RAM single bit ECC error",
- QDMA_S80_HARD_RAM_DBE_MSK_A_ADDR,
- QDMA_S80_HARD_RAM_DBE_STS_A_ADDR,
- RAM_DBE_STS_A_DSC_CPLD_MASK,
- GLBL_ERR_STAT_ERR_RAM_DBE_MASK,
- &qdma_s80_hard_hw_ram_dbe_err_process
- },
- {
- QDMA_S80_HARD_DBE_ERR_PASID_CTXT_RAM,
- "PASID CTXT RAM single bit ECC error",
- QDMA_S80_HARD_RAM_DBE_MSK_A_ADDR,
- QDMA_S80_HARD_RAM_DBE_STS_A_ADDR,
- RAM_DBE_STS_A_PASID_CTXT_RAM_MASK,
- GLBL_ERR_STAT_ERR_RAM_DBE_MASK,
- &qdma_s80_hard_hw_ram_dbe_err_process
- },
- {
- QDMA_S80_HARD_DBE_ERR_TIMER_FIFO_RAM,
- "Timer fifo RAM single bit ECC error",
- QDMA_S80_HARD_RAM_DBE_MSK_A_ADDR,
- QDMA_S80_HARD_RAM_DBE_STS_A_ADDR,
- RAM_DBE_STS_A_TIMER_FIFO_RAM_MASK,
- GLBL_ERR_STAT_ERR_RAM_DBE_MASK,
- &qdma_s80_hard_hw_ram_dbe_err_process
- },
- {
- QDMA_S80_HARD_DBE_ERR_PAYLOAD_FIFO_RAM,
- "Payload fifo RAM single bit ECC error",
- QDMA_S80_HARD_RAM_DBE_MSK_A_ADDR,
- QDMA_S80_HARD_RAM_DBE_STS_A_ADDR,
- RAM_DBE_STS_A_PLD_FIFO_RAM_MASK,
- GLBL_ERR_STAT_ERR_RAM_DBE_MASK,
- &qdma_s80_hard_hw_ram_dbe_err_process
- },
- {
- QDMA_S80_HARD_DBE_ERR_QID_FIFO_RAM,
- "C2H ST QID FIFO RAM single bit ECC error",
- QDMA_S80_HARD_RAM_DBE_MSK_A_ADDR,
- QDMA_S80_HARD_RAM_DBE_STS_A_ADDR,
- RAM_DBE_STS_A_QID_FIFO_RAM_MASK,
- GLBL_ERR_STAT_ERR_RAM_DBE_MASK,
- &qdma_s80_hard_hw_ram_dbe_err_process
- },
- {
- QDMA_S80_HARD_DBE_ERR_WRB_COAL_DATA_RAM,
- "Writeback Coalescing RAM single bit ECC error",
- QDMA_S80_HARD_RAM_DBE_MSK_A_ADDR,
- QDMA_S80_HARD_RAM_DBE_STS_A_ADDR,
- RAM_DBE_STS_A_WRB_COAL_DATA_RAM_MASK,
- GLBL_ERR_STAT_ERR_RAM_DBE_MASK,
- &qdma_s80_hard_hw_ram_dbe_err_process
- },
- {
- QDMA_S80_HARD_DBE_ERR_INT_QID2VEC_RAM,
- "QID2VEC RAM single bit ECC error",
- QDMA_S80_HARD_RAM_DBE_MSK_A_ADDR,
- QDMA_S80_HARD_RAM_DBE_STS_A_ADDR,
- RAM_DBE_STS_A_INT_QID2VEC_RAM_MASK,
- GLBL_ERR_STAT_ERR_RAM_DBE_MASK,
- &qdma_s80_hard_hw_ram_dbe_err_process
- },
- {
- QDMA_S80_HARD_DBE_ERR_INT_CTXT_RAM,
- "Interrupt context RAM single bit ECC error",
- QDMA_S80_HARD_RAM_DBE_MSK_A_ADDR,
- QDMA_S80_HARD_RAM_DBE_STS_A_ADDR,
- RAM_DBE_STS_A_INT_CTXT_RAM_MASK,
- GLBL_ERR_STAT_ERR_RAM_DBE_MASK,
- &qdma_s80_hard_hw_ram_dbe_err_process
- },
- {
- QDMA_S80_HARD_DBE_ERR_DESC_REQ_FIFO_RAM,
- "C2H ST descriptor request RAM single bit ECC error",
- QDMA_S80_HARD_RAM_DBE_MSK_A_ADDR,
- QDMA_S80_HARD_RAM_DBE_STS_A_ADDR,
- RAM_DBE_STS_A_DESC_REQ_FIFO_RAM_MASK,
- GLBL_ERR_STAT_ERR_RAM_DBE_MASK,
- &qdma_s80_hard_hw_ram_dbe_err_process
- },
- {
- QDMA_S80_HARD_DBE_ERR_PFCH_CTXT_RAM,
- "C2H ST prefetch RAM single bit ECC error",
- QDMA_S80_HARD_RAM_DBE_MSK_A_ADDR,
- QDMA_S80_HARD_RAM_DBE_STS_A_ADDR,
- RAM_DBE_STS_A_PFCH_CTXT_RAM_MASK,
- GLBL_ERR_STAT_ERR_RAM_DBE_MASK,
- &qdma_s80_hard_hw_ram_dbe_err_process
- },
- {
- QDMA_S80_HARD_DBE_ERR_WRB_CTXT_RAM,
- "C2H ST completion context RAM single bit ECC error",
- QDMA_S80_HARD_RAM_DBE_MSK_A_ADDR,
- QDMA_S80_HARD_RAM_DBE_STS_A_ADDR,
- RAM_DBE_STS_A_WRB_CTXT_RAM_MASK,
- GLBL_ERR_STAT_ERR_RAM_DBE_MASK,
- &qdma_s80_hard_hw_ram_dbe_err_process
- },
- {
- QDMA_S80_HARD_DBE_ERR_PFCH_LL_RAM,
- "C2H ST prefetch list RAM single bit ECC error",
- QDMA_S80_HARD_RAM_DBE_MSK_A_ADDR,
- QDMA_S80_HARD_RAM_DBE_STS_A_ADDR,
- RAM_DBE_STS_A_PFCH_LL_RAM_MASK,
- GLBL_ERR_STAT_ERR_RAM_DBE_MASK,
- &qdma_s80_hard_hw_ram_dbe_err_process
- },
- {
- QDMA_S80_HARD_DBE_ERR_ALL,
- "All DBE errors",
- QDMA_S80_HARD_RAM_DBE_MSK_A_ADDR,
- QDMA_S80_HARD_RAM_DBE_STS_A_ADDR,
- QDMA_S80_HARD_DBE_ERR_ALL_MASK,
- GLBL_ERR_STAT_ERR_RAM_DBE_MASK,
- &qdma_s80_hard_hw_ram_dbe_err_process
- }
-};
-
-static int32_t all_qdma_s80_hard_hw_errs[
- QDMA_S80_HARD_TOTAL_LEAF_ERROR_AGGREGATORS] = {
-
- QDMA_S80_HARD_DSC_ERR_ALL,
- QDMA_S80_HARD_TRQ_ERR_ALL,
- QDMA_S80_HARD_ST_C2H_ERR_ALL,
- QDMA_S80_HARD_ST_FATAL_ERR_ALL,
- QDMA_S80_HARD_ST_H2C_ERR_ALL,
- QDMA_S80_HARD_SBE_ERR_ALL,
- QDMA_S80_HARD_DBE_ERR_ALL
-};
-
-
-
-union qdma_s80_hard_ind_ctxt_cmd {
- uint32_t word;
- struct {
- uint32_t busy:1;
- uint32_t sel:4;
- uint32_t op:2;
- uint32_t qid:11;
- uint32_t rsvd:14;
- } bits;
-};
-
-struct qdma_s80_hard_indirect_ctxt_regs {
- uint32_t qdma_ind_ctxt_data[QDMA_S80_HARD_IND_CTXT_DATA_NUM_REGS];
- uint32_t qdma_ind_ctxt_mask[QDMA_S80_HARD_IND_CTXT_DATA_NUM_REGS];
- union qdma_s80_hard_ind_ctxt_cmd cmd;
-};
-
-static struct qctx_entry qdma_s80_hard_sw_ctxt_entries[] = {
- {"PIDX", 0},
- {"IRQ Arm", 0},
- {"Queue Enable", 0},
- {"Fetch Credit Enable", 0},
- {"Write back/Intr Check", 0},
- {"Write back/Intr Interval", 0},
- {"Function Id", 0},
- {"Ring Size", 0},
- {"Descriptor Size", 0},
- {"Bypass Enable", 0},
- {"MM Channel", 0},
- {"Writeback Enable", 0},
- {"Interrupt Enable", 0},
- {"Port Id", 0},
- {"Interrupt No Last", 0},
- {"Error", 0},
- {"Writeback Error Sent", 0},
- {"IRQ Request", 0},
- {"Marker Disable", 0},
- {"Is Memory Mapped", 0},
- {"Descriptor Ring Base Addr (Low)", 0},
- {"Descriptor Ring Base Addr (High)", 0},
-};
-
-static struct qctx_entry qdma_s80_hard_hw_ctxt_entries[] = {
- {"CIDX", 0},
- {"Credits Consumed", 0},
- {"Descriptors Pending", 0},
- {"Queue Invalid No Desc Pending", 0},
- {"Eviction Pending", 0},
- {"Fetch Pending", 0},
-};
-
-static struct qctx_entry qdma_s80_hard_credit_ctxt_entries[] = {
- {"Credit", 0},
-};
-
-static struct qctx_entry qdma_s80_hard_cmpt_ctxt_entries[] = {
- {"Enable Status Desc Update", 0},
- {"Enable Interrupt", 0},
- {"Trigger Mode", 0},
- {"Function Id", 0},
- {"Counter Index", 0},
- {"Timer Index", 0},
- {"Interrupt State", 0},
- {"Color", 0},
- {"Ring Size", 0},
- {"Base Address (Low)", 0},
- {"Base Address (High)", 0},
- {"Descriptor Size", 0},
- {"PIDX", 0},
- {"CIDX", 0},
- {"Valid", 0},
- {"Error", 0},
- {"Trigger Pending", 0},
- {"Timer Running", 0},
- {"Full Update", 0},
-};
-
-static struct qctx_entry qdma_s80_hard_c2h_pftch_ctxt_entries[] = {
- {"Bypass", 0},
- {"Buffer Size Index", 0},
- {"Port Id", 0},
- {"Error", 0},
- {"Prefetch Enable", 0},
- {"In Prefetch", 0},
- {"Software Credit", 0},
- {"Valid", 0},
-};
-
-static struct qctx_entry qdma_s80_hard_qid2vec_ctxt_entries[] = {
- {"c2h_vector", 0},
- {"c2h_en_coal", 0},
- {"h2c_vector", 0},
- {"h2c_en_coal", 0},
-};
-
-static struct qctx_entry qdma_s80_hard_ind_intr_ctxt_entries[] = {
- {"valid", 0},
- {"vec", 0},
- {"int_st", 0},
- {"color", 0},
- {"baddr_4k (Low)", 0},
- {"baddr_4k (High)", 0},
- {"page_size", 0},
- {"pidx", 0},
-};
-
-static int qdma_s80_hard_indirect_reg_invalidate(void *dev_hndl,
- enum ind_ctxt_cmd_sel sel, uint16_t hw_qid);
-static int qdma_s80_hard_indirect_reg_clear(void *dev_hndl,
- enum ind_ctxt_cmd_sel sel, uint16_t hw_qid);
-static int qdma_s80_hard_indirect_reg_read(void *dev_hndl,
- enum ind_ctxt_cmd_sel sel,
- uint16_t hw_qid, uint32_t cnt, uint32_t *data);
-static int qdma_s80_hard_indirect_reg_write(void *dev_hndl,
- enum ind_ctxt_cmd_sel sel,
- uint16_t hw_qid, uint32_t *data, uint16_t cnt);
-
-uint32_t qdma_s80_hard_get_config_num_regs(void)
-{
- return qdma_s80_hard_config_num_regs_get();
-}
-
-struct xreg_info *qdma_s80_hard_get_config_regs(void)
-{
- return qdma_s80_hard_config_regs_get();
-}
-
-uint32_t qdma_s80_hard_reg_dump_buf_len(void)
-{
- uint32_t length = (qdma_s80_hard_config_num_regs_get() + 1)
- * REG_DUMP_SIZE_PER_LINE;
- return length;
-}
-
-int qdma_s80_hard_context_buf_len(uint8_t st,
- enum qdma_dev_q_type q_type, uint32_t *req_buflen)
-{
- uint32_t len = 0;
- int rv = 0;
-
- if (q_type == QDMA_DEV_Q_TYPE_CMPT) {
- len += (((sizeof(qdma_s80_hard_cmpt_ctxt_entries) /
- sizeof(qdma_s80_hard_cmpt_ctxt_entries[0])) + 1) *
- REG_DUMP_SIZE_PER_LINE);
- } else {
- len += (((sizeof(qdma_s80_hard_sw_ctxt_entries) /
- sizeof(qdma_s80_hard_sw_ctxt_entries[0])) + 1) *
- REG_DUMP_SIZE_PER_LINE);
-
- len += (((sizeof(qdma_s80_hard_hw_ctxt_entries) /
- sizeof(qdma_s80_hard_hw_ctxt_entries[0])) + 1) *
- REG_DUMP_SIZE_PER_LINE);
-
- len += (((sizeof(qdma_s80_hard_credit_ctxt_entries) /
- sizeof(qdma_s80_hard_credit_ctxt_entries[0])) + 1) *
- REG_DUMP_SIZE_PER_LINE);
-
- if (st && (q_type == QDMA_DEV_Q_TYPE_C2H)) {
- len += (((sizeof(qdma_s80_hard_cmpt_ctxt_entries) /
- sizeof(qdma_s80_hard_cmpt_ctxt_entries[0])) + 1) *
- REG_DUMP_SIZE_PER_LINE);
-
- len += (((sizeof(qdma_s80_hard_c2h_pftch_ctxt_entries) /
- sizeof(qdma_s80_hard_c2h_pftch_ctxt_entries[0])) + 1) *
- REG_DUMP_SIZE_PER_LINE);
- }
- }
-
- *req_buflen = len;
- return rv;
-}
-
-static uint32_t qdma_s80_hard_intr_context_buf_len(void)
-{
- uint32_t len = 0;
-
- len += (((sizeof(qdma_s80_hard_ind_intr_ctxt_entries) /
- sizeof(qdma_s80_hard_ind_intr_ctxt_entries[0])) + 1) *
- REG_DUMP_SIZE_PER_LINE);
- return len;
-}
-
-/*
- * qdma_acc_fill_sw_ctxt() - Helper function to fill sw context into structure
- *
- */
-static void qdma_s80_hard_fill_sw_ctxt(struct qdma_descq_sw_ctxt *sw_ctxt)
-{
- qdma_s80_hard_sw_ctxt_entries[0].value = sw_ctxt->pidx;
- qdma_s80_hard_sw_ctxt_entries[1].value = sw_ctxt->irq_arm;
- qdma_s80_hard_sw_ctxt_entries[2].value = sw_ctxt->qen;
- qdma_s80_hard_sw_ctxt_entries[3].value = sw_ctxt->frcd_en;
- qdma_s80_hard_sw_ctxt_entries[4].value = sw_ctxt->wbi_chk;
- qdma_s80_hard_sw_ctxt_entries[5].value = sw_ctxt->wbi_intvl_en;
- qdma_s80_hard_sw_ctxt_entries[6].value = sw_ctxt->fnc_id;
- qdma_s80_hard_sw_ctxt_entries[7].value = sw_ctxt->rngsz_idx;
- qdma_s80_hard_sw_ctxt_entries[8].value = sw_ctxt->desc_sz;
- qdma_s80_hard_sw_ctxt_entries[9].value = sw_ctxt->bypass;
- qdma_s80_hard_sw_ctxt_entries[10].value = sw_ctxt->mm_chn;
- qdma_s80_hard_sw_ctxt_entries[11].value = sw_ctxt->wbk_en;
- qdma_s80_hard_sw_ctxt_entries[12].value = sw_ctxt->irq_en;
- qdma_s80_hard_sw_ctxt_entries[13].value = sw_ctxt->port_id;
- qdma_s80_hard_sw_ctxt_entries[14].value = sw_ctxt->irq_no_last;
- qdma_s80_hard_sw_ctxt_entries[15].value = sw_ctxt->err;
- qdma_s80_hard_sw_ctxt_entries[16].value = sw_ctxt->err_wb_sent;
- qdma_s80_hard_sw_ctxt_entries[17].value = sw_ctxt->irq_req;
- qdma_s80_hard_sw_ctxt_entries[18].value = sw_ctxt->mrkr_dis;
- qdma_s80_hard_sw_ctxt_entries[19].value = sw_ctxt->is_mm;
- qdma_s80_hard_sw_ctxt_entries[20].value =
- sw_ctxt->ring_bs_addr & 0xFFFFFFFF;
- qdma_s80_hard_sw_ctxt_entries[21].value =
- (sw_ctxt->ring_bs_addr >> 32) & 0xFFFFFFFF;
-}
-
-/*
- * qdma_acc_fill_cmpt_ctxt() - Helper function to fill completion context
- * into structure
- *
- */
-static void qdma_s80_hard_fill_cmpt_ctxt(struct qdma_descq_cmpt_ctxt *cmpt_ctxt)
-{
- qdma_s80_hard_cmpt_ctxt_entries[0].value = cmpt_ctxt->en_stat_desc;
- qdma_s80_hard_cmpt_ctxt_entries[1].value = cmpt_ctxt->en_int;
- qdma_s80_hard_cmpt_ctxt_entries[2].value = cmpt_ctxt->trig_mode;
- qdma_s80_hard_cmpt_ctxt_entries[3].value = cmpt_ctxt->fnc_id;
- qdma_s80_hard_cmpt_ctxt_entries[4].value = cmpt_ctxt->counter_idx;
- qdma_s80_hard_cmpt_ctxt_entries[5].value = cmpt_ctxt->timer_idx;
- qdma_s80_hard_cmpt_ctxt_entries[6].value = cmpt_ctxt->in_st;
- qdma_s80_hard_cmpt_ctxt_entries[7].value = cmpt_ctxt->color;
- qdma_s80_hard_cmpt_ctxt_entries[8].value = cmpt_ctxt->ringsz_idx;
- qdma_s80_hard_cmpt_ctxt_entries[9].value =
- cmpt_ctxt->bs_addr & 0xFFFFFFFF;
- qdma_s80_hard_cmpt_ctxt_entries[10].value =
- (cmpt_ctxt->bs_addr >> 32) & 0xFFFFFFFF;
- qdma_s80_hard_cmpt_ctxt_entries[11].value = cmpt_ctxt->desc_sz;
- qdma_s80_hard_cmpt_ctxt_entries[12].value = cmpt_ctxt->pidx;
- qdma_s80_hard_cmpt_ctxt_entries[13].value = cmpt_ctxt->cidx;
- qdma_s80_hard_cmpt_ctxt_entries[14].value = cmpt_ctxt->valid;
- qdma_s80_hard_cmpt_ctxt_entries[15].value = cmpt_ctxt->err;
- qdma_s80_hard_cmpt_ctxt_entries[16].value = cmpt_ctxt->user_trig_pend;
- qdma_s80_hard_cmpt_ctxt_entries[17].value = cmpt_ctxt->timer_running;
- qdma_s80_hard_cmpt_ctxt_entries[18].value = cmpt_ctxt->full_upd;
-
-}
-
-/*
- * qdma_acc_fill_hw_ctxt() - Helper function to fill HW context into structure
- *
- */
-static void qdma_s80_hard_fill_hw_ctxt(struct qdma_descq_hw_ctxt *hw_ctxt)
-{
- qdma_s80_hard_hw_ctxt_entries[0].value = hw_ctxt->cidx;
- qdma_s80_hard_hw_ctxt_entries[1].value = hw_ctxt->crd_use;
- qdma_s80_hard_hw_ctxt_entries[2].value = hw_ctxt->dsc_pend;
- qdma_s80_hard_hw_ctxt_entries[3].value = hw_ctxt->idl_stp_b;
- qdma_s80_hard_hw_ctxt_entries[4].value = hw_ctxt->evt_pnd;
- qdma_s80_hard_hw_ctxt_entries[5].value = hw_ctxt->fetch_pnd;
-}
-
-/*
- * qdma_acc_fill_credit_ctxt() - Helper function to fill Credit context
- * into structure
- *
- */
-static void qdma_s80_hard_fill_credit_ctxt(
- struct qdma_descq_credit_ctxt *cr_ctxt)
-{
- qdma_s80_hard_credit_ctxt_entries[0].value = cr_ctxt->credit;
-}
-
-/*
- * qdma_acc_fill_pfetch_ctxt() - Helper function to fill Prefetch context
- * into structure
- *
- */
-static void qdma_s80_hard_fill_pfetch_ctxt(
- struct qdma_descq_prefetch_ctxt *pfetch_ctxt)
-{
- qdma_s80_hard_c2h_pftch_ctxt_entries[0].value = pfetch_ctxt->bypass;
- qdma_s80_hard_c2h_pftch_ctxt_entries[1].value = pfetch_ctxt->bufsz_idx;
- qdma_s80_hard_c2h_pftch_ctxt_entries[2].value = pfetch_ctxt->port_id;
- qdma_s80_hard_c2h_pftch_ctxt_entries[3].value = pfetch_ctxt->err;
- qdma_s80_hard_c2h_pftch_ctxt_entries[4].value = pfetch_ctxt->pfch_en;
- qdma_s80_hard_c2h_pftch_ctxt_entries[5].value = pfetch_ctxt->pfch;
- qdma_s80_hard_c2h_pftch_ctxt_entries[6].value = pfetch_ctxt->sw_crdt;
- qdma_s80_hard_c2h_pftch_ctxt_entries[7].value = pfetch_ctxt->valid;
-}
-
-static void qdma_s80_hard_fill_qid2vec_ctxt(struct qdma_qid2vec *qid2vec_ctxt)
-{
- qdma_s80_hard_qid2vec_ctxt_entries[0].value = qid2vec_ctxt->c2h_vector;
- qdma_s80_hard_qid2vec_ctxt_entries[1].value = qid2vec_ctxt->c2h_en_coal;
- qdma_s80_hard_qid2vec_ctxt_entries[2].value = qid2vec_ctxt->h2c_vector;
- qdma_s80_hard_qid2vec_ctxt_entries[3].value = qid2vec_ctxt->h2c_en_coal;
-}
-
-static void qdma_s80_hard_fill_intr_ctxt(
- struct qdma_indirect_intr_ctxt *intr_ctxt)
-{
- qdma_s80_hard_ind_intr_ctxt_entries[0].value = intr_ctxt->valid;
- qdma_s80_hard_ind_intr_ctxt_entries[1].value = intr_ctxt->vec;
- qdma_s80_hard_ind_intr_ctxt_entries[2].value = intr_ctxt->int_st;
- qdma_s80_hard_ind_intr_ctxt_entries[3].value = intr_ctxt->color;
- qdma_s80_hard_ind_intr_ctxt_entries[4].value =
- intr_ctxt->baddr_4k & 0xFFFFFFFF;
- qdma_s80_hard_ind_intr_ctxt_entries[5].value =
- (intr_ctxt->baddr_4k >> 32) & 0xFFFFFFFF;
- qdma_s80_hard_ind_intr_ctxt_entries[6].value = intr_ctxt->page_size;
- qdma_s80_hard_ind_intr_ctxt_entries[7].value = intr_ctxt->pidx;
-}
-
-/*
- * dump_s80_hard_context() - Helper function to dump queue context into string
- *
- * return len - length of the string copied into buffer
- */
-static int dump_s80_hard_context(struct qdma_descq_context *queue_context,
- uint8_t st, enum qdma_dev_q_type q_type,
- char *buf, int buf_sz)
-{
- int i = 0;
- int n;
- int len = 0;
- int rv;
- char banner[DEBGFS_LINE_SZ];
-
- if (queue_context == NULL) {
- qdma_log_error("%s: queue_context is NULL, err:%d\n",
- __func__,
- -QDMA_ERR_INV_PARAM);
- return -QDMA_ERR_INV_PARAM;
- }
-
- if (q_type >= QDMA_DEV_Q_TYPE_CMPT) {
- qdma_log_error("%s: Invalid queue type(%d), err:%d\n",
- __func__,
- q_type,
- -QDMA_ERR_INV_PARAM);
- return -QDMA_ERR_INV_PARAM;
- }
-
- qdma_s80_hard_fill_sw_ctxt(&queue_context->sw_ctxt);
- qdma_s80_hard_fill_hw_ctxt(&queue_context->hw_ctxt);
- qdma_s80_hard_fill_credit_ctxt(&queue_context->cr_ctxt);
- qdma_s80_hard_fill_qid2vec_ctxt(&queue_context->qid2vec);
- if (st && (q_type == QDMA_DEV_Q_TYPE_C2H)) {
- qdma_s80_hard_fill_pfetch_ctxt(&queue_context->pfetch_ctxt);
- qdma_s80_hard_fill_cmpt_ctxt(&queue_context->cmpt_ctxt);
- }
-
- if (q_type != QDMA_DEV_Q_TYPE_CMPT) {
- for (i = 0; i < DEBGFS_LINE_SZ - 5; i++) {
- rv = QDMA_SNPRINTF_S(banner + i,
- (DEBGFS_LINE_SZ - i),
- sizeof("-"), "-");
- if ((rv < 0) || (rv > (int)sizeof("-"))) {
- qdma_log_error(
- "%d:%s QDMA_SNPRINTF_S() failed, err:%d\n",
- __LINE__, __func__,
- rv);
- goto INSUF_BUF_EXIT;
- }
- }
-
- /* SW context dump */
- n = sizeof(qdma_s80_hard_sw_ctxt_entries) /
- sizeof((qdma_s80_hard_sw_ctxt_entries)[0]);
- for (i = 0; i < n; i++) {
- if ((len >= buf_sz) ||
- ((len + DEBGFS_LINE_SZ) >= buf_sz))
- goto INSUF_BUF_EXIT;
-
- if (i == 0) {
- if ((len + (3 * DEBGFS_LINE_SZ)) >= buf_sz)
- goto INSUF_BUF_EXIT;
- rv = QDMA_SNPRINTF_S(buf + len, (buf_sz - len),
- DEBGFS_LINE_SZ, "\n%s", banner);
- if ((rv < 0) || (rv > DEBGFS_LINE_SZ)) {
- qdma_log_error(
- "%d:%s QDMA_SNPRINTF_S() failed, err:%d\n",
- __LINE__, __func__,
- rv);
- goto INSUF_BUF_EXIT;
- }
- len += rv;
-
- rv = QDMA_SNPRINTF_S(buf + len, (buf_sz - len),
- DEBGFS_LINE_SZ, "\n%40s", "SW Context");
- if ((rv < 0) || (rv > DEBGFS_LINE_SZ)) {
- qdma_log_error(
- "%d:%s QDMA_SNPRINTF_S() failed, err:%d\n",
- __LINE__, __func__,
- rv);
- goto INSUF_BUF_EXIT;
- }
- len += rv;
-
- rv = QDMA_SNPRINTF_S(buf + len, (buf_sz - len),
- DEBGFS_LINE_SZ, "\n%s\n", banner);
- if ((rv < 0) || (rv > DEBGFS_LINE_SZ)) {
- qdma_log_error(
- "%d:%s QDMA_SNPRINTF_S() failed, err:%d\n",
- __LINE__, __func__,
- rv);
- goto INSUF_BUF_EXIT;
- }
- len += rv;
- }
-
- rv = QDMA_SNPRINTF_S(buf + len, (buf_sz - len),
- DEBGFS_LINE_SZ,
- "%-47s %#-10x %u\n",
- qdma_s80_hard_sw_ctxt_entries[i].name,
- qdma_s80_hard_sw_ctxt_entries[i].value,
- qdma_s80_hard_sw_ctxt_entries[i].value);
- if ((rv < 0) || (rv > DEBGFS_LINE_SZ)) {
- qdma_log_error(
- "%d:%s QDMA_SNPRINTF_S() failed, err:%d\n",
- __LINE__, __func__,
- rv);
- goto INSUF_BUF_EXIT;
- }
- len += rv;
- }
-
- /* HW context dump */
- n = sizeof(qdma_s80_hard_hw_ctxt_entries) /
- sizeof((qdma_s80_hard_hw_ctxt_entries)[0]);
- for (i = 0; i < n; i++) {
- if ((len >= buf_sz) ||
- ((len + DEBGFS_LINE_SZ) >= buf_sz))
- goto INSUF_BUF_EXIT;
-
- if (i == 0) {
- if ((len + (3 * DEBGFS_LINE_SZ)) >= buf_sz)
- goto INSUF_BUF_EXIT;
-
- rv = QDMA_SNPRINTF_S(buf + len, (buf_sz - len),
- DEBGFS_LINE_SZ, "\n%s", banner);
- if ((rv < 0) || (rv > DEBGFS_LINE_SZ)) {
- qdma_log_error(
- "%d:%s QDMA_SNPRINTF_S() failed, err:%d\n",
- __LINE__, __func__,
- rv);
- goto INSUF_BUF_EXIT;
- }
- len += rv;
-
- rv = QDMA_SNPRINTF_S(buf + len, (buf_sz - len),
- DEBGFS_LINE_SZ, "\n%40s", "HW Context");
- if ((rv < 0) || (rv > DEBGFS_LINE_SZ)) {
- qdma_log_error(
- "%d:%s QDMA_SNPRINTF_S() failed, err:%d\n",
- __LINE__, __func__,
- rv);
- goto INSUF_BUF_EXIT;
- }
- len += rv;
-
- rv = QDMA_SNPRINTF_S(buf + len, (buf_sz - len),
- DEBGFS_LINE_SZ, "\n%s\n", banner);
- if ((rv < 0) || (rv > DEBGFS_LINE_SZ)) {
- qdma_log_error(
- "%d:%s QDMA_SNPRINTF_S() failed, err:%d\n",
- __LINE__, __func__,
- rv);
- goto INSUF_BUF_EXIT;
- }
- len += rv;
- }
-
- rv = QDMA_SNPRINTF_S(buf + len, (buf_sz - len),
- DEBGFS_LINE_SZ,
- "%-47s %#-10x %u\n",
- qdma_s80_hard_hw_ctxt_entries[i].name,
- qdma_s80_hard_hw_ctxt_entries[i].value,
- qdma_s80_hard_hw_ctxt_entries[i].value);
- if ((rv < 0) || (rv > DEBGFS_LINE_SZ)) {
- qdma_log_error(
- "%d:%s QDMA_SNPRINTF_S() failed, err:%d\n",
- __LINE__, __func__,
- rv);
- goto INSUF_BUF_EXIT;
- }
- len += rv;
- }
-
- /* Credit context dump */
- n = sizeof(qdma_s80_hard_credit_ctxt_entries) /
- sizeof((qdma_s80_hard_credit_ctxt_entries)[0]);
- for (i = 0; i < n; i++) {
- if ((len >= buf_sz) ||
- ((len + DEBGFS_LINE_SZ) >= buf_sz))
- goto INSUF_BUF_EXIT;
-
- if (i == 0) {
- if ((len + (3 * DEBGFS_LINE_SZ)) >= buf_sz)
- goto INSUF_BUF_EXIT;
-
- rv = QDMA_SNPRINTF_S(buf + len, (buf_sz - len),
- DEBGFS_LINE_SZ, "\n%s", banner);
- if ((rv < 0) || (rv > DEBGFS_LINE_SZ)) {
- qdma_log_error(
- "%d:%s QDMA_SNPRINTF_S() failed, err:%d\n",
- __LINE__, __func__,
- rv);
- goto INSUF_BUF_EXIT;
- }
- len += rv;
-
- rv = QDMA_SNPRINTF_S(buf + len, (buf_sz - len),
- DEBGFS_LINE_SZ, "\n%40s",
- "Credit Context");
- if ((rv < 0) || (rv > DEBGFS_LINE_SZ)) {
- qdma_log_error(
- "%d:%s QDMA_SNPRINTF_S() failed, err:%d\n",
- __LINE__, __func__,
- rv);
- goto INSUF_BUF_EXIT;
- }
- len += rv;
-
- rv = QDMA_SNPRINTF_S(buf + len, (buf_sz - len),
- DEBGFS_LINE_SZ, "\n%s\n", banner);
- if ((rv < 0) || (rv > DEBGFS_LINE_SZ)) {
- qdma_log_error(
- "%d:%s QDMA_SNPRINTF_S() failed, err:%d\n",
- __LINE__, __func__,
- rv);
- goto INSUF_BUF_EXIT;
- }
- len += rv;
- }
-
- rv = QDMA_SNPRINTF_S(buf + len, (buf_sz - len),
- DEBGFS_LINE_SZ,
- "%-47s %#-10x %u\n",
- qdma_s80_hard_credit_ctxt_entries[i].name,
- qdma_s80_hard_credit_ctxt_entries[i].value,
- qdma_s80_hard_credit_ctxt_entries[i].value);
- if ((rv < 0) || (rv > DEBGFS_LINE_SZ)) {
- qdma_log_error(
- "%d:%s QDMA_SNPRINTF_S() failed, err:%d\n",
- __LINE__, __func__,
- rv);
- goto INSUF_BUF_EXIT;
- }
- len += rv;
- }
- }
-
- /* SW context dump */
- n = sizeof(qdma_s80_hard_qid2vec_ctxt_entries) /
- sizeof((qdma_s80_hard_qid2vec_ctxt_entries)[0]);
- for (i = 0; i < n; i++) {
- if ((len >= buf_sz) ||
- ((len + DEBGFS_LINE_SZ) >= buf_sz))
- goto INSUF_BUF_EXIT;
-
- if (i == 0) {
- if ((len + (3 * DEBGFS_LINE_SZ)) >= buf_sz)
- goto INSUF_BUF_EXIT;
- rv = QDMA_SNPRINTF_S(buf + len, (buf_sz - len),
- DEBGFS_LINE_SZ, "\n%s", banner);
- if ((rv < 0) || (rv > DEBGFS_LINE_SZ)) {
- qdma_log_error(
- "%d:%s QDMA_SNPRINTF_S() failed, err:%d\n",
- __LINE__, __func__,
- rv);
- goto INSUF_BUF_EXIT;
- }
- len += rv;
-
- rv = QDMA_SNPRINTF_S(buf + len, (buf_sz - len),
- DEBGFS_LINE_SZ, "\n%40s",
- "QID2VEC Context");
- if ((rv < 0) || (rv > DEBGFS_LINE_SZ)) {
- qdma_log_error(
- "%d:%s QDMA_SNPRINTF_S() failed, err:%d\n",
- __LINE__, __func__,
- rv);
- goto INSUF_BUF_EXIT;
- }
- len += rv;
-
- rv = QDMA_SNPRINTF_S(buf + len, (buf_sz - len),
- DEBGFS_LINE_SZ, "\n%s\n", banner);
- if ((rv < 0) || (rv > DEBGFS_LINE_SZ)) {
- qdma_log_error(
- "%d:%s QDMA_SNPRINTF_S() failed, err:%d\n",
- __LINE__, __func__,
- rv);
- goto INSUF_BUF_EXIT;
- }
- len += rv;
- }
-
- rv = QDMA_SNPRINTF_S(buf + len, (buf_sz - len), DEBGFS_LINE_SZ,
- "%-47s %#-10x %u\n",
- qdma_s80_hard_qid2vec_ctxt_entries[i].name,
- qdma_s80_hard_qid2vec_ctxt_entries[i].value,
- qdma_s80_hard_qid2vec_ctxt_entries[i].value);
- if ((rv < 0) || (rv > DEBGFS_LINE_SZ)) {
- qdma_log_error(
- "%d:%s QDMA_SNPRINTF_S() failed, err:%d\n",
- __LINE__, __func__,
- rv);
- goto INSUF_BUF_EXIT;
- }
- len += rv;
- }
-
-
- if ((q_type == QDMA_DEV_Q_TYPE_CMPT) ||
- (st && q_type == QDMA_DEV_Q_TYPE_C2H)) {
- /* Completion context dump */
- n = sizeof(qdma_s80_hard_cmpt_ctxt_entries) /
- sizeof((qdma_s80_hard_cmpt_ctxt_entries)[0]);
- for (i = 0; i < n; i++) {
- if ((len >= buf_sz) ||
- ((len + DEBGFS_LINE_SZ) >= buf_sz))
- goto INSUF_BUF_EXIT;
-
- if (i == 0) {
- if ((len + (3 * DEBGFS_LINE_SZ)) >= buf_sz)
- goto INSUF_BUF_EXIT;
-
- rv = QDMA_SNPRINTF_S(buf + len, (buf_sz - len),
- DEBGFS_LINE_SZ, "\n%s", banner);
- if ((rv < 0) || (rv > DEBGFS_LINE_SZ)) {
- qdma_log_error(
- "%d:%s QDMA_SNPRINTF_S() failed, err:%d\n",
- __LINE__, __func__,
- rv);
- goto INSUF_BUF_EXIT;
- }
- len += rv;
-
- rv = QDMA_SNPRINTF_S(buf + len, (buf_sz - len),
- DEBGFS_LINE_SZ, "\n%40s",
- "Completion Context");
- if ((rv < 0) || (rv > DEBGFS_LINE_SZ)) {
- qdma_log_error(
- "%d:%s QDMA_SNPRINTF_S() failed, err:%d\n",
- __LINE__, __func__,
- rv);
- goto INSUF_BUF_EXIT;
- }
- len += rv;
-
- rv = QDMA_SNPRINTF_S(buf + len, (buf_sz - len),
- DEBGFS_LINE_SZ, "\n%s\n", banner);
- if ((rv < 0) || (rv > DEBGFS_LINE_SZ)) {
- qdma_log_error(
- "%d:%s QDMA_SNPRINTF_S() failed, err:%d\n",
- __LINE__, __func__,
- rv);
- goto INSUF_BUF_EXIT;
- }
- len += rv;
- }
-
- rv = QDMA_SNPRINTF_S(buf + len, (buf_sz - len),
- DEBGFS_LINE_SZ,
- "%-47s %#-10x %u\n",
- qdma_s80_hard_cmpt_ctxt_entries[i].name,
- qdma_s80_hard_cmpt_ctxt_entries[i].value,
- qdma_s80_hard_cmpt_ctxt_entries[i].value);
- if ((rv < 0) || (rv > DEBGFS_LINE_SZ)) {
- qdma_log_error(
- "%d:%s QDMA_SNPRINTF_S() failed, err:%d\n",
- __LINE__, __func__,
- rv);
- goto INSUF_BUF_EXIT;
- }
- len += rv;
- }
- }
-
- if (st && q_type == QDMA_DEV_Q_TYPE_C2H) {
- /* Prefetch context dump */
- n = sizeof(qdma_s80_hard_c2h_pftch_ctxt_entries) /
- sizeof(qdma_s80_hard_c2h_pftch_ctxt_entries[0]);
- for (i = 0; i < n; i++) {
- if ((len >= buf_sz) ||
- ((len + DEBGFS_LINE_SZ) >= buf_sz))
- goto INSUF_BUF_EXIT;
-
- if (i == 0) {
- if ((len + (3 * DEBGFS_LINE_SZ)) >= buf_sz)
- goto INSUF_BUF_EXIT;
-
- rv = QDMA_SNPRINTF_S(buf + len, (buf_sz - len),
- DEBGFS_LINE_SZ, "\n%s", banner);
- if ((rv < 0) || (rv > DEBGFS_LINE_SZ)) {
- qdma_log_error(
- "%d:%s QDMA_SNPRINTF_S() failed, err:%d\n",
- __LINE__, __func__,
- rv);
- goto INSUF_BUF_EXIT;
- }
- len += rv;
-
- rv = QDMA_SNPRINTF_S(buf + len, (buf_sz - len),
- DEBGFS_LINE_SZ, "\n%40s",
- "Prefetch Context");
- if ((rv < 0) || (rv > DEBGFS_LINE_SZ)) {
- qdma_log_error(
- "%d:%s QDMA_SNPRINTF_S() failed, err:%d\n",
- __LINE__, __func__,
- rv);
- goto INSUF_BUF_EXIT;
- }
- len += rv;
-
- rv = QDMA_SNPRINTF_S(buf + len, (buf_sz - len),
- DEBGFS_LINE_SZ, "\n%s\n", banner);
- if ((rv < 0) || (rv > DEBGFS_LINE_SZ)) {
- qdma_log_error(
- "%d:%s QDMA_SNPRINTF_S() failed, err:%d\n",
- __LINE__, __func__,
- rv);
- goto INSUF_BUF_EXIT;
- }
- len += rv;
- }
-
- rv = QDMA_SNPRINTF_S(buf + len, (buf_sz - len),
- DEBGFS_LINE_SZ,
- "%-47s %#-10x %u\n",
- qdma_s80_hard_c2h_pftch_ctxt_entries[i].name,
- qdma_s80_hard_c2h_pftch_ctxt_entries[i].value,
- qdma_s80_hard_c2h_pftch_ctxt_entries[i].value);
- if ((rv < 0) || (rv > DEBGFS_LINE_SZ)) {
- qdma_log_error(
- "%d:%s QDMA_SNPRINTF_S() failed, err:%d\n",
- __LINE__, __func__,
- rv);
- goto INSUF_BUF_EXIT;
- }
- len += rv;
- }
- }
-
- return len;
-
-INSUF_BUF_EXIT:
- if (buf_sz > DEBGFS_LINE_SZ) {
- rv = QDMA_SNPRINTF_S((buf + buf_sz - DEBGFS_LINE_SZ),
- buf_sz, DEBGFS_LINE_SZ,
- "\n\nInsufficient buffer size, partial context dump\n");
- if ((rv < 0) || (rv > DEBGFS_LINE_SZ)) {
- qdma_log_error(
- "%d:%s QDMA_SNPRINTF_S() failed, err:%d\n",
- __LINE__, __func__,
- rv);
- }
- }
-
- qdma_log_error("%s: Insufficient buffer size, err:%d\n",
- __func__, -QDMA_ERR_NO_MEM);
-
- return -QDMA_ERR_NO_MEM;
-}
-
-static int dump_s80_hard_intr_context(struct qdma_indirect_intr_ctxt *intr_ctx,
- int ring_index,
- char *buf, int buf_sz)
-{
- int i = 0;
- int n;
- int len = 0;
- int rv;
- char banner[DEBGFS_LINE_SZ];
-
- qdma_s80_hard_fill_intr_ctxt(intr_ctx);
-
- for (i = 0; i < DEBGFS_LINE_SZ - 5; i++) {
- rv = QDMA_SNPRINTF_S(banner + i,
- (DEBGFS_LINE_SZ - i),
- sizeof("-"), "-");
- if ((rv < 0) || (rv > (int)sizeof("-"))) {
- qdma_log_error(
- "%d:%s QDMA_SNPRINTF_S() failed, err:%d\n",
- __LINE__, __func__,
- rv);
- goto INSUF_BUF_EXIT;
- }
- }
-
- /* Interrupt context dump */
- n = sizeof(qdma_s80_hard_ind_intr_ctxt_entries) /
- sizeof((qdma_s80_hard_ind_intr_ctxt_entries)[0]);
- for (i = 0; i < n; i++) {
- if ((len >= buf_sz) || ((len + DEBGFS_LINE_SZ) >= buf_sz))
- goto INSUF_BUF_EXIT;
-
- if (i == 0) {
- if ((len + (3 * DEBGFS_LINE_SZ)) >= buf_sz)
- goto INSUF_BUF_EXIT;
-
- rv = QDMA_SNPRINTF_S(buf + len, (buf_sz - len),
- DEBGFS_LINE_SZ, "\n%s", banner);
- if ((rv < 0) || (rv > DEBGFS_LINE_SZ)) {
- qdma_log_error(
- "%d:%s QDMA_SNPRINTF_S() failed, err:%d\n",
- __LINE__, __func__,
- rv);
- goto INSUF_BUF_EXIT;
- }
- len += rv;
-
- rv = QDMA_SNPRINTF_S(buf + len, (buf_sz - len),
- DEBGFS_LINE_SZ, "\n%50s %d",
- "Interrupt Context for ring#", ring_index);
- if ((rv < 0) || (rv > DEBGFS_LINE_SZ)) {
- qdma_log_error(
- "%d:%s QDMA_SNPRINTF_S() failed, err:%d\n",
- __LINE__, __func__,
- rv);
- goto INSUF_BUF_EXIT;
- }
- len += rv;
-
- rv = QDMA_SNPRINTF_S(buf + len, (buf_sz - len),
- DEBGFS_LINE_SZ, "\n%s\n", banner);
- if ((rv < 0) || (rv > DEBGFS_LINE_SZ)) {
- qdma_log_error(
- "%d:%s QDMA_SNPRINTF_S() failed, err:%d\n",
- __LINE__, __func__,
- rv);
- goto INSUF_BUF_EXIT;
- }
- len += rv;
- }
-
- rv = QDMA_SNPRINTF_S(buf + len, (buf_sz - len), DEBGFS_LINE_SZ,
- "%-47s %#-10x %u\n",
- qdma_s80_hard_ind_intr_ctxt_entries[i].name,
- qdma_s80_hard_ind_intr_ctxt_entries[i].value,
- qdma_s80_hard_ind_intr_ctxt_entries[i].value);
- if ((rv < 0) || (rv > DEBGFS_LINE_SZ)) {
- qdma_log_error(
- "%d:%s QDMA_SNPRINTF_S() failed, err:%d\n",
- __LINE__, __func__,
- rv);
- goto INSUF_BUF_EXIT;
- }
- len += rv;
- }
-
- return len;
-
-INSUF_BUF_EXIT:
- if (buf_sz > DEBGFS_LINE_SZ) {
- rv = QDMA_SNPRINTF_S((buf + buf_sz - DEBGFS_LINE_SZ),
- buf_sz, DEBGFS_LINE_SZ,
- "\n\nInsufficient buffer size, partial intr context dump\n");
- if ((rv < 0) || (rv > DEBGFS_LINE_SZ)) {
- qdma_log_error(
- "%d:%s QDMA_SNPRINTF_S() failed, err:%d\n",
- __LINE__, __func__,
- rv);
- }
- }
-
- qdma_log_error("%s: Insufficient buffer size, err:%d\n",
- __func__, -QDMA_ERR_NO_MEM);
-
- return -QDMA_ERR_NO_MEM;
-}
-
-/*
- * qdma_s80_hard_indirect_reg_invalidate() - helper function to invalidate
- * indirect context registers.
- *
- * return -QDMA_ERR_HWACC_BUSY_TIMEOUT if register
- * value didn't match, QDMA_SUCCESS other wise
- */
-static int qdma_s80_hard_indirect_reg_invalidate(void *dev_hndl,
- enum ind_ctxt_cmd_sel sel, uint16_t hw_qid)
-{
- union qdma_s80_hard_ind_ctxt_cmd cmd;
-
- qdma_reg_access_lock(dev_hndl);
-
- /* set command register */
- cmd.word = 0;
- cmd.bits.qid = hw_qid;
- cmd.bits.op = QDMA_CTXT_CMD_INV;
- cmd.bits.sel = sel;
- qdma_reg_write(dev_hndl, QDMA_S80_HARD_IND_CTXT_CMD_ADDR, cmd.word);
-
- /* check if the operation went through well */
- if (hw_monitor_reg(dev_hndl, QDMA_S80_HARD_IND_CTXT_CMD_ADDR,
- IND_CTXT_CMD_BUSY_MASK, 0,
- QDMA_REG_POLL_DFLT_INTERVAL_US,
- QDMA_REG_POLL_DFLT_TIMEOUT_US)) {
- qdma_reg_access_release(dev_hndl);
- qdma_log_error("%s: hw_monitor_reg failed, err:%d\n",
- __func__,
- -QDMA_ERR_HWACC_BUSY_TIMEOUT);
- return -QDMA_ERR_HWACC_BUSY_TIMEOUT;
- }
-
- qdma_reg_access_release(dev_hndl);
-
- return QDMA_SUCCESS;
-}
-
-/*
- * qdma_s80_hard_indirect_reg_clear() - helper function to clear indirect
- * context registers.
- *
- * return -QDMA_ERR_HWACC_BUSY_TIMEOUT if register
- * value didn't match, QDMA_SUCCESS other wise
- */
-static int qdma_s80_hard_indirect_reg_clear(void *dev_hndl,
- enum ind_ctxt_cmd_sel sel, uint16_t hw_qid)
-{
- union qdma_s80_hard_ind_ctxt_cmd cmd;
-
- qdma_reg_access_lock(dev_hndl);
-
- /* set command register */
- cmd.word = 0;
- cmd.bits.qid = hw_qid;
- cmd.bits.op = QDMA_CTXT_CMD_CLR;
- cmd.bits.sel = sel;
-
- qdma_reg_write(dev_hndl, QDMA_S80_HARD_IND_CTXT_CMD_ADDR, cmd.word);
-
- /* check if the operation went through well */
- if (hw_monitor_reg(dev_hndl, QDMA_S80_HARD_IND_CTXT_CMD_ADDR,
- IND_CTXT_CMD_BUSY_MASK, 0,
- QDMA_REG_POLL_DFLT_INTERVAL_US,
- QDMA_REG_POLL_DFLT_TIMEOUT_US)) {
- qdma_reg_access_release(dev_hndl);
- qdma_log_error("%s: hw_monitor_reg failed, err:%d\n",
- __func__,
- -QDMA_ERR_HWACC_BUSY_TIMEOUT);
- return -QDMA_ERR_HWACC_BUSY_TIMEOUT;
- }
-
- qdma_reg_access_release(dev_hndl);
-
- return QDMA_SUCCESS;
-}
-
-/*
- * qdma_s80_hard_indirect_reg_read() - helper function to read indirect
- * context registers.
- *
- * return -QDMA_ERR_HWACC_BUSY_TIMEOUT if register
- * value didn't match, QDMA_SUCCESS other wise
- */
-static int qdma_s80_hard_indirect_reg_read(void *dev_hndl,
- enum ind_ctxt_cmd_sel sel,
- uint16_t hw_qid, uint32_t cnt, uint32_t *data)
-{
- uint32_t index = 0, reg_addr = QDMA_S80_HARD_IND_CTXT_DATA_3_ADDR;
- union qdma_s80_hard_ind_ctxt_cmd cmd;
-
- qdma_reg_access_lock(dev_hndl);
-
- /* set command register */
- cmd.word = 0;
- cmd.bits.qid = hw_qid;
- cmd.bits.op = QDMA_CTXT_CMD_RD;
- cmd.bits.sel = sel;
- qdma_reg_write(dev_hndl, QDMA_S80_HARD_IND_CTXT_CMD_ADDR, cmd.word);
-
- /* check if the operation went through well */
- if (hw_monitor_reg(dev_hndl, QDMA_S80_HARD_IND_CTXT_CMD_ADDR,
- IND_CTXT_CMD_BUSY_MASK, 0,
- QDMA_REG_POLL_DFLT_INTERVAL_US,
- QDMA_REG_POLL_DFLT_TIMEOUT_US)) {
- qdma_reg_access_release(dev_hndl);
- qdma_log_error("%s: hw_monitor_reg failed, err:%d\n",
- __func__,
- -QDMA_ERR_HWACC_BUSY_TIMEOUT);
- return -QDMA_ERR_HWACC_BUSY_TIMEOUT;
- }
-
- for (index = 0; index < cnt; index++, reg_addr += sizeof(uint32_t))
- data[index] = qdma_reg_read(dev_hndl, reg_addr);
-
- qdma_reg_access_release(dev_hndl);
-
- return QDMA_SUCCESS;
-}
-
-/*
- * qdma_s80_hard_indirect_reg_write() - helper function to write indirect
- * context registers.
- *
- * return -QDMA_ERR_HWACC_BUSY_TIMEOUT if register
- * value didn't match, QDMA_SUCCESS other wise
- */
-static int qdma_s80_hard_indirect_reg_write(void *dev_hndl,
- enum ind_ctxt_cmd_sel sel,
- uint16_t hw_qid, uint32_t *data, uint16_t cnt)
-{
- uint32_t index, reg_addr;
- struct qdma_s80_hard_indirect_ctxt_regs regs;
- uint32_t *wr_data = (uint32_t *)®s;
-
- qdma_reg_access_lock(dev_hndl);
-
- /* write the context data */
- for (index = 0; index < QDMA_S80_HARD_IND_CTXT_DATA_NUM_REGS;
- index++) {
- if (index < cnt)
- regs.qdma_ind_ctxt_data[index] = data[index];
- else
- regs.qdma_ind_ctxt_data[index] = 0;
- regs.qdma_ind_ctxt_mask[index] = 0xFFFFFFFF;
- }
-
- regs.cmd.word = 0;
- regs.cmd.bits.qid = hw_qid;
- regs.cmd.bits.op = QDMA_CTXT_CMD_WR;
- regs.cmd.bits.sel = sel;
- reg_addr = QDMA_S80_HARD_IND_CTXT_DATA_3_ADDR;
-
- for (index = 0;
- index < ((2 * QDMA_S80_HARD_IND_CTXT_DATA_NUM_REGS) + 1);
- index++, reg_addr += sizeof(uint32_t))
- qdma_reg_write(dev_hndl, reg_addr, wr_data[index]);
-
- /* check if the operation went through well */
- if (hw_monitor_reg(dev_hndl, QDMA_S80_HARD_IND_CTXT_CMD_ADDR,
- IND_CTXT_CMD_BUSY_MASK, 0,
- QDMA_REG_POLL_DFLT_INTERVAL_US,
- QDMA_REG_POLL_DFLT_TIMEOUT_US)) {
- qdma_reg_access_release(dev_hndl);
- qdma_log_error("%s: hw_monitor_reg failed, err:%d\n",
- __func__,
- -QDMA_ERR_HWACC_BUSY_TIMEOUT);
- return -QDMA_ERR_HWACC_BUSY_TIMEOUT;
- }
-
- qdma_reg_access_release(dev_hndl);
-
- return QDMA_SUCCESS;
-}
-
-/*****************************************************************************/
-/**
- * qdma_s80_hard_qid2vec_write() - create qid2vec context and program it
- *
- * @dev_hndl: device handle
- * @c2h: is c2h queue
- * @hw_qid: hardware qid of the queue
- * @ctxt: pointer to the context data
- *
- * Return: 0 - success and < 0 - failure
- *****************************************************************************/
-static int qdma_s80_hard_qid2vec_write(void *dev_hndl, uint8_t c2h,
- uint16_t hw_qid, struct qdma_qid2vec *ctxt)
-{
- uint32_t qid2vec = 0;
- enum ind_ctxt_cmd_sel sel = QDMA_CTXT_SEL_FMAP;
- int rv = 0;
-
- if (!dev_hndl || !ctxt) {
- qdma_log_error("%s: dev_hndl=%p qid2vec=%p, err:%d\n",
- __func__, dev_hndl, ctxt, -QDMA_ERR_INV_PARAM);
- return -QDMA_ERR_INV_PARAM;
- }
-
- rv = qdma_s80_hard_indirect_reg_read(dev_hndl, sel, hw_qid,
- 1, &qid2vec);
- if (rv < 0)
- return rv;
- if (c2h) {
- qid2vec = qid2vec & (QDMA_S80_HARD_QID2VEC_H2C_VECTOR |
- QDMA_S80_HARD_QID2VEC_H2C_COAL_EN);
- qid2vec |= FIELD_SET(C2H_QID2VEC_MAP_C2H_VECTOR_MASK,
- ctxt->c2h_vector) |
- FIELD_SET(C2H_QID2VEC_MAP_C2H_EN_COAL_MASK,
- ctxt->c2h_en_coal);
- } else {
- qid2vec = qid2vec & (C2H_QID2VEC_MAP_C2H_VECTOR_MASK |
- C2H_QID2VEC_MAP_C2H_EN_COAL_MASK);
- qid2vec |=
- FIELD_SET(QDMA_S80_HARD_QID2VEC_H2C_VECTOR,
- ctxt->h2c_vector) |
- FIELD_SET(QDMA_S80_HARD_QID2VEC_H2C_COAL_EN,
- ctxt->h2c_en_coal);
- }
-
- return qdma_s80_hard_indirect_reg_write(dev_hndl, sel, hw_qid,
- &qid2vec, QDMA_S80_HARD_QID2VEC_CONTEXT_NUM_WORDS);
-
-}
-
-/*****************************************************************************/
-/**
- * qdma_s80_hard_qid2vec_read() - read qid2vec context
- *
- * @dev_hndl: device handle
- * @c2h: is c2h queue
- * @hw_qid: hardware qid of the queue
- * @ctxt: pointer to the context data
- *
- * Return: 0 - success and < 0 - failure
- *****************************************************************************/
-static int qdma_s80_hard_qid2vec_read(void *dev_hndl, uint8_t c2h,
- uint16_t hw_qid, struct qdma_qid2vec *ctxt)
-{
- int rv = 0;
- uint32_t qid2vec[QDMA_S80_HARD_QID2VEC_CONTEXT_NUM_WORDS] = {0};
- enum ind_ctxt_cmd_sel sel = QDMA_CTXT_SEL_FMAP;
-
- if (!dev_hndl || !ctxt) {
- qdma_log_error("%s: dev_hndl=%p qid2vec=%p, err:%d\n",
- __func__, dev_hndl, ctxt, -QDMA_ERR_INV_PARAM);
- return -QDMA_ERR_INV_PARAM;
- }
-
- rv = qdma_s80_hard_indirect_reg_read(dev_hndl, sel, hw_qid,
- QDMA_S80_HARD_QID2VEC_CONTEXT_NUM_WORDS, qid2vec);
- if (rv < 0)
- return rv;
-
- if (c2h) {
- ctxt->c2h_vector = FIELD_GET(C2H_QID2VEC_MAP_C2H_VECTOR_MASK,
- qid2vec[0]);
- ctxt->c2h_en_coal =
- (uint8_t)(FIELD_GET(C2H_QID2VEC_MAP_C2H_EN_COAL_MASK,
- qid2vec[0]));
- } else {
- ctxt->h2c_vector =
- (uint8_t)(FIELD_GET(QDMA_S80_HARD_QID2VEC_H2C_VECTOR,
- qid2vec[0]));
- ctxt->h2c_en_coal =
- (uint8_t)(FIELD_GET(QDMA_S80_HARD_QID2VEC_H2C_COAL_EN,
- qid2vec[0]));
- }
-
- return QDMA_SUCCESS;
-}
-
-/*****************************************************************************/
-/**
- * qdma_s80_hard_qid2vec_clear() - clear qid2vec context
- *
- * @dev_hndl: device handle
- * @hw_qid: hardware qid of the queue
- *
- * Return: 0 - success and < 0 - failure
- *****************************************************************************/
-static int qdma_s80_hard_qid2vec_clear(void *dev_hndl, uint16_t hw_qid)
-{
- enum ind_ctxt_cmd_sel sel = QDMA_CTXT_SEL_FMAP;
-
- if (!dev_hndl) {
- qdma_log_error("%s: dev_handle is NULL, err:%d\n",
- __func__, -QDMA_ERR_INV_PARAM);
- return -QDMA_ERR_INV_PARAM;
- }
-
- return qdma_s80_hard_indirect_reg_clear(dev_hndl, sel, hw_qid);
-}
-
-/*****************************************************************************/
-/**
- * qdma_s80_hard_qid2vec_invalidate() - invalidate qid2vec context
- *
- * @dev_hndl: device handle
- * @hw_qid: hardware qid of the queue
- *
- * Return: 0 - success and < 0 - failure
- *****************************************************************************/
-static int qdma_s80_hard_qid2vec_invalidate(void *dev_hndl, uint16_t hw_qid)
-{
- enum ind_ctxt_cmd_sel sel = QDMA_CTXT_SEL_FMAP;
-
- if (!dev_hndl) {
- qdma_log_error("%s: dev_handle is NULL, err:%d\n",
- __func__, -QDMA_ERR_INV_PARAM);
- return -QDMA_ERR_INV_PARAM;
- }
-
- return qdma_s80_hard_indirect_reg_invalidate(dev_hndl, sel, hw_qid);
-}
-
-/*****************************************************************************/
-/**
- * qdma_s80_hard_qid2vec_conf() - configure qid2vector context
- *
- * @dev_hndl: device handle
- * @c2h: is c2h queue
- * @hw_qid: hardware qid of the queue
- * @ctxt: pointer to the context data
- * @access_type HW access type (qdma_hw_access_type enum) value
- *
- * Return: 0 - success and < 0 - failure
- *****************************************************************************/
-int qdma_s80_hard_qid2vec_conf(void *dev_hndl, uint8_t c2h, uint16_t hw_qid,
- struct qdma_qid2vec *ctxt,
- enum qdma_hw_access_type access_type)
-{
- int ret_val = 0;
-
- switch (access_type) {
- case QDMA_HW_ACCESS_READ:
- ret_val = qdma_s80_hard_qid2vec_read(dev_hndl, c2h,
- hw_qid, ctxt);
- break;
- case QDMA_HW_ACCESS_WRITE:
- ret_val = qdma_s80_hard_qid2vec_write(dev_hndl, c2h,
- hw_qid, ctxt);
- break;
- case QDMA_HW_ACCESS_CLEAR:
- ret_val = qdma_s80_hard_qid2vec_clear(dev_hndl, hw_qid);
- break;
- case QDMA_HW_ACCESS_INVALIDATE:
- ret_val = qdma_s80_hard_qid2vec_invalidate(dev_hndl, hw_qid);
- break;
- default:
- qdma_log_error("%s: access_type=%d is invalid, err:%d\n",
- __func__, access_type,
- -QDMA_ERR_INV_PARAM);
- ret_val = -QDMA_ERR_INV_PARAM;
- break;
- }
-
- return ret_val;
-}
-
-/*****************************************************************************/
-/**
- * qdma_s80_hard_fmap_write() - create fmap context and program it
- *
- * @dev_hndl: device handle
- * @func_id: function id of the device
- * @config: pointer to the fmap data strucutre
- *
- * Return: 0 - success and < 0 - failure
- *****************************************************************************/
-static int qdma_s80_hard_fmap_write(void *dev_hndl, uint16_t func_id,
- const struct qdma_fmap_cfg *config)
-{
- uint32_t fmap = 0;
-
- if (!dev_hndl || !config) {
- qdma_log_error("%s: dev_handle or config is NULL, err:%d\n",
- __func__, -QDMA_ERR_INV_PARAM);
- return -QDMA_ERR_INV_PARAM;
- }
-
- fmap = FIELD_SET(TRQ_SEL_FMAP_0_QID_BASE_MASK, config->qbase) |
- FIELD_SET(TRQ_SEL_FMAP_0_QID_MAX_MASK,
- config->qmax);
-
- qdma_reg_write(dev_hndl, QDMA_S80_HARD_TRQ_SEL_FMAP_0_ADDR +
- func_id * QDMA_S80_HARD_REG_TRQ_SEL_FMAP_STEP,
- fmap);
- return QDMA_SUCCESS;
-}
-
-/*****************************************************************************/
-/**
- * qdma_s80_hard_fmap_read() - read fmap context
- *
- * @dev_hndl: device handle
- * @func_id: function id of the device
- * @config: pointer to the output fmap data
- *
- * Return: 0 - success and < 0 - failure
- *****************************************************************************/
-static int qdma_s80_hard_fmap_read(void *dev_hndl, uint16_t func_id,
- struct qdma_fmap_cfg *config)
-{
- uint32_t fmap = 0;
-
- if (!dev_hndl || !config) {
- qdma_log_error("%s: dev_handle=%p fmap=%p NULL, err:%d\n",
- __func__, dev_hndl, config,
- -QDMA_ERR_INV_PARAM);
- return -QDMA_ERR_INV_PARAM;
- }
-
- fmap = qdma_reg_read(dev_hndl, QDMA_S80_HARD_TRQ_SEL_FMAP_0_ADDR +
- func_id * QDMA_S80_HARD_REG_TRQ_SEL_FMAP_STEP);
-
- config->qbase = FIELD_GET(TRQ_SEL_FMAP_0_QID_BASE_MASK, fmap);
- config->qmax =
- (uint16_t)(FIELD_GET(TRQ_SEL_FMAP_0_QID_MAX_MASK,
- fmap));
-
- return QDMA_SUCCESS;
-}
-
-/*****************************************************************************/
-/**
- * qdma_s80_hard_fmap_clear() - clear fmap context
- *
- * @dev_hndl: device handle
- * @func_id: function id of the device
- *
- * Return: 0 - success and < 0 - failure
- *****************************************************************************/
-static int qdma_s80_hard_fmap_clear(void *dev_hndl, uint16_t func_id)
-{
- uint32_t fmap = 0;
-
- if (!dev_hndl) {
- qdma_log_error("%s: dev_handle is NULL, err:%d\n",
- __func__, -QDMA_ERR_INV_PARAM);
- return -QDMA_ERR_INV_PARAM;
- }
-
- qdma_reg_write(dev_hndl, QDMA_S80_HARD_TRQ_SEL_FMAP_0_ADDR +
- func_id * QDMA_S80_HARD_REG_TRQ_SEL_FMAP_STEP,
- fmap);
-
- return QDMA_SUCCESS;
-}
-
-/*****************************************************************************/
-/**
- * qdma_s80_hard_fmap_conf() - configure fmap context
- *
- * @dev_hndl: device handle
- * @func_id: function id of the device
- * @config: pointer to the fmap data
- * @access_type HW access type (qdma_hw_access_type enum) value
- * QDMA_HW_ACCESS_INVALIDATE unsupported
- *
- * Return: 0 - success and < 0 - failure
- *****************************************************************************/
-int qdma_s80_hard_fmap_conf(void *dev_hndl, uint16_t func_id,
- struct qdma_fmap_cfg *config,
- enum qdma_hw_access_type access_type)
-{
- int ret_val = 0;
-
- switch (access_type) {
- case QDMA_HW_ACCESS_READ:
- ret_val = qdma_s80_hard_fmap_read(dev_hndl, func_id, config);
- break;
- case QDMA_HW_ACCESS_WRITE:
- ret_val = qdma_s80_hard_fmap_write(dev_hndl, func_id, config);
- break;
- case QDMA_HW_ACCESS_CLEAR:
- ret_val = qdma_s80_hard_fmap_clear(dev_hndl, func_id);
- break;
- case QDMA_HW_ACCESS_INVALIDATE:
- default:
- qdma_log_error("%s: access_type=%d is invalid, err:%d\n",
- __func__, access_type,
- -QDMA_ERR_INV_PARAM);
- ret_val = -QDMA_ERR_INV_PARAM;
- break;
- }
-
- return ret_val;
-}
-
-/*****************************************************************************/
-/**
- * qdma_s80_hard_sw_context_write() - create sw context and program it
- *
- * @dev_hndl: device handle
- * @c2h: is c2h queue
- * @hw_qid: hardware qid of the queue
- * @ctxt: pointer to the SW context data strucutre
- *
- * Return: 0 - success and < 0 - failure
- *****************************************************************************/
-static int qdma_s80_hard_sw_context_write(void *dev_hndl, uint8_t c2h,
- uint16_t hw_qid,
- const struct qdma_descq_sw_ctxt *ctxt)
-{
- uint32_t sw_ctxt[QDMA_S80_HARD_SW_CONTEXT_NUM_WORDS] = {0};
- uint16_t num_words_count = 0;
- enum ind_ctxt_cmd_sel sel = c2h ?
- QDMA_CTXT_SEL_SW_C2H : QDMA_CTXT_SEL_SW_H2C;
-
- /* Input args check */
- if (!dev_hndl || !ctxt) {
- qdma_log_error("%s: dev_hndl or ctxt is NULL, err:%d\n",
- __func__, -QDMA_ERR_INV_PARAM);
- return -QDMA_ERR_INV_PARAM;
- }
-
- if ((ctxt->desc_sz > QDMA_DESC_SIZE_64B) ||
- (ctxt->rngsz_idx >= QDMA_NUM_RING_SIZES)) {
- qdma_log_error("%s: Invalid desc_sz(%d)/rngidx(%d), err:%d\n",
- __func__,
- ctxt->desc_sz,
- ctxt->rngsz_idx,
- -QDMA_ERR_INV_PARAM);
- return -QDMA_ERR_INV_PARAM;
- }
-
- sw_ctxt[num_words_count++] =
- FIELD_SET(SW_IND_CTXT_DATA_W0_PIDX_MASK, ctxt->pidx) |
- FIELD_SET(SW_IND_CTXT_DATA_W0_IRQ_ARM_MASK, ctxt->irq_arm);
-
- sw_ctxt[num_words_count++] =
- FIELD_SET(SW_IND_CTXT_DATA_W1_QEN_MASK, ctxt->qen) |
- FIELD_SET(SW_IND_CTXT_DATA_W1_FCRD_EN_MASK, ctxt->frcd_en) |
- FIELD_SET(SW_IND_CTXT_DATA_W1_WBI_CHK_MASK, ctxt->wbi_chk) |
- FIELD_SET(SW_IND_CTXT_DATA_W1_WBI_INTVL_EN_MASK,
- ctxt->wbi_intvl_en) |
- FIELD_SET(SW_IND_CTXT_DATA_W1_FNC_ID_MASK, ctxt->fnc_id) |
- FIELD_SET(SW_IND_CTXT_DATA_W1_RNG_SZ_MASK, ctxt->rngsz_idx) |
- FIELD_SET(SW_IND_CTXT_DATA_W1_DSC_SZ_MASK, ctxt->desc_sz) |
- FIELD_SET(SW_IND_CTXT_DATA_W1_BYPASS_MASK, ctxt->bypass) |
- FIELD_SET(SW_IND_CTXT_DATA_W1_MM_CHN_MASK, ctxt->mm_chn) |
- FIELD_SET(SW_IND_CTXT_DATA_W1_WBK_EN_MASK, ctxt->wbk_en) |
- FIELD_SET(SW_IND_CTXT_DATA_W1_IRQ_EN_MASK, ctxt->irq_en) |
- FIELD_SET(SW_IND_CTXT_DATA_W1_PORT_ID_MASK, ctxt->port_id) |
- FIELD_SET(SW_IND_CTXT_DATA_W1_IRQ_NO_LAST_MASK,
- ctxt->irq_no_last) |
- FIELD_SET(SW_IND_CTXT_DATA_W1_ERR_MASK, ctxt->err) |
- FIELD_SET(SW_IND_CTXT_DATA_W1_ERR_WB_SENT_MASK,
- ctxt->err_wb_sent) |
- FIELD_SET(SW_IND_CTXT_DATA_W1_IRQ_REQ_MASK, ctxt->irq_req) |
- FIELD_SET(SW_IND_CTXT_DATA_W1_MRKR_DIS_MASK, ctxt->mrkr_dis) |
- FIELD_SET(SW_IND_CTXT_DATA_W1_IS_MM_MASK, ctxt->is_mm);
-
- sw_ctxt[num_words_count++] = ctxt->ring_bs_addr & 0xffffffff;
- sw_ctxt[num_words_count++] = (ctxt->ring_bs_addr >> 32) & 0xffffffff;
-
- return qdma_s80_hard_indirect_reg_write(dev_hndl, sel, hw_qid,
- sw_ctxt, num_words_count);
-}
-
-/*****************************************************************************/
-/**
- * qdma_s80_hard_sw_context_read() - read sw context
- *
- * @dev_hndl: device handle
- * @c2h: is c2h queue
- * @hw_qid: hardware qid of the queue
- * @ctxt: pointer to the output context data
- *
- * Return: 0 - success and < 0 - failure
- *****************************************************************************/
-static int qdma_s80_hard_sw_context_read(void *dev_hndl, uint8_t c2h,
- uint16_t hw_qid,
- struct qdma_descq_sw_ctxt *ctxt)
-{
- int rv = 0;
- uint32_t sw_ctxt[QDMA_S80_HARD_SW_CONTEXT_NUM_WORDS] = {0};
- enum ind_ctxt_cmd_sel sel = c2h ?
- QDMA_CTXT_SEL_SW_C2H : QDMA_CTXT_SEL_SW_H2C;
- struct qdma_qid2vec qid2vec_ctxt = {0};
-
- if (!dev_hndl || !ctxt) {
- qdma_log_error("%s: dev_hndl=%p sw_ctxt=%p, err:%d\n",
- __func__, dev_hndl, ctxt,
- -QDMA_ERR_INV_PARAM);
- return -QDMA_ERR_INV_PARAM;
- }
-
- rv = qdma_s80_hard_indirect_reg_read(dev_hndl, sel, hw_qid,
- QDMA_S80_HARD_SW_CONTEXT_NUM_WORDS, sw_ctxt);
- if (rv < 0)
- return rv;
-
- ctxt->pidx = FIELD_GET(SW_IND_CTXT_DATA_W0_PIDX_MASK, sw_ctxt[0]);
- ctxt->irq_arm =
- (uint8_t)(FIELD_GET(SW_IND_CTXT_DATA_W0_IRQ_ARM_MASK,
- sw_ctxt[0]));
-
- ctxt->qen = FIELD_GET(SW_IND_CTXT_DATA_W1_QEN_MASK, sw_ctxt[1]);
- ctxt->frcd_en = FIELD_GET(SW_IND_CTXT_DATA_W1_FCRD_EN_MASK,
- sw_ctxt[1]);
- ctxt->wbi_chk = FIELD_GET(SW_IND_CTXT_DATA_W1_WBI_CHK_MASK,
- sw_ctxt[1]);
- ctxt->wbi_intvl_en =
- FIELD_GET(SW_IND_CTXT_DATA_W1_WBI_INTVL_EN_MASK,
- sw_ctxt[1]);
- ctxt->fnc_id =
- (uint8_t)(FIELD_GET(SW_IND_CTXT_DATA_W1_FNC_ID_MASK,
- sw_ctxt[1]));
- ctxt->rngsz_idx =
- (uint8_t)(FIELD_GET(SW_IND_CTXT_DATA_W1_RNG_SZ_MASK,
- sw_ctxt[1]));
- ctxt->desc_sz =
- (uint8_t)(FIELD_GET(SW_IND_CTXT_DATA_W1_DSC_SZ_MASK,
- sw_ctxt[1]));
- ctxt->bypass =
- (uint8_t)(FIELD_GET(SW_IND_CTXT_DATA_W1_BYPASS_MASK,
- sw_ctxt[1]));
- ctxt->mm_chn =
- (uint8_t)(FIELD_GET(SW_IND_CTXT_DATA_W1_MM_CHN_MASK,
- sw_ctxt[1]));
- ctxt->wbk_en =
- (uint8_t)(FIELD_GET(SW_IND_CTXT_DATA_W1_WBK_EN_MASK,
- sw_ctxt[1]));
- ctxt->irq_en =
- (uint8_t)(FIELD_GET(SW_IND_CTXT_DATA_W1_IRQ_EN_MASK,
- sw_ctxt[1]));
- ctxt->port_id =
- (uint8_t)(FIELD_GET(SW_IND_CTXT_DATA_W1_PORT_ID_MASK,
- sw_ctxt[1]));
- ctxt->irq_no_last =
- (uint8_t)(FIELD_GET(SW_IND_CTXT_DATA_W1_IRQ_NO_LAST_MASK,
- sw_ctxt[1]));
- ctxt->err =
- (uint8_t)(FIELD_GET(SW_IND_CTXT_DATA_W1_ERR_MASK, sw_ctxt[1]));
- ctxt->err_wb_sent =
- (uint8_t)(FIELD_GET(SW_IND_CTXT_DATA_W1_ERR_WB_SENT_MASK,
- sw_ctxt[1]));
- ctxt->irq_req =
- (uint8_t)(FIELD_GET(SW_IND_CTXT_DATA_W1_IRQ_REQ_MASK,
- sw_ctxt[1]));
- ctxt->mrkr_dis =
- (uint8_t)(FIELD_GET(SW_IND_CTXT_DATA_W1_MRKR_DIS_MASK,
- sw_ctxt[1]));
- ctxt->is_mm =
- (uint8_t)(FIELD_GET(SW_IND_CTXT_DATA_W1_IS_MM_MASK,
- sw_ctxt[1]));
-
- ctxt->ring_bs_addr = ((uint64_t)sw_ctxt[3] << 32) | (sw_ctxt[2]);
-
- /** Read the QID2VEC Context Data */
- rv = qdma_s80_hard_qid2vec_read(dev_hndl, c2h, hw_qid, &qid2vec_ctxt);
- if (rv < 0)
- return rv;
-
- if (c2h) {
- ctxt->vec = qid2vec_ctxt.c2h_vector;
- ctxt->intr_aggr = qid2vec_ctxt.c2h_en_coal;
- } else {
- ctxt->vec = qid2vec_ctxt.h2c_vector;
- ctxt->intr_aggr = qid2vec_ctxt.h2c_en_coal;
- }
-
-
- return QDMA_SUCCESS;
-}
-
-/*****************************************************************************/
-/**
- * qdma_s80_hard_sw_context_clear() - clear sw context
- *
- * @dev_hndl: device handle
- * @c2h: is c2h queue
- * @hw_qid: hardware qid of the queue
- *
- * Return: 0 - success and < 0 - failure
- *****************************************************************************/
-static int qdma_s80_hard_sw_context_clear(void *dev_hndl, uint8_t c2h,
- uint16_t hw_qid)
-{
- enum ind_ctxt_cmd_sel sel = c2h ?
- QDMA_CTXT_SEL_SW_C2H : QDMA_CTXT_SEL_SW_H2C;
-
- if (!dev_hndl) {
- qdma_log_error("%s: dev_handle is NULL, err:%d\n",
- __func__, -QDMA_ERR_INV_PARAM);
- return -QDMA_ERR_INV_PARAM;
- }
-
- return qdma_s80_hard_indirect_reg_clear(dev_hndl, sel, hw_qid);
-}
-
-/*****************************************************************************/
-/**
- * qdma_s80_hard_sw_context_invalidate() - invalidate sw context
- *
- * @dev_hndl: device handle
- * @c2h: is c2h queue
- * @hw_qid: hardware qid of the queue
- *
- * Return: 0 - success and < 0 - failure
- *****************************************************************************/
-static int qdma_s80_hard_sw_context_invalidate(void *dev_hndl, uint8_t c2h,
- uint16_t hw_qid)
-{
- enum ind_ctxt_cmd_sel sel = c2h ?
- QDMA_CTXT_SEL_SW_C2H : QDMA_CTXT_SEL_SW_H2C;
-
- if (!dev_hndl) {
- qdma_log_error("%s: dev_handle is NULL, err:%d\n",
- __func__, -QDMA_ERR_INV_PARAM);
- return -QDMA_ERR_INV_PARAM;
- }
-
- return qdma_s80_hard_indirect_reg_invalidate(dev_hndl, sel, hw_qid);
-}
-
-/*****************************************************************************/
-/**
- * qdma_s80_hard_sw_ctx_conf() - configure SW context
- *
- * @dev_hndl: device handle
- * @c2h: is c2h queue
- * @hw_qid: hardware qid of the queue
- * @ctxt: pointer to the context data
- * @access_type HW access type (qdma_hw_access_type enum) value
- *
- * Return: 0 - success and < 0 - failure
- *****************************************************************************/
-int qdma_s80_hard_sw_ctx_conf(void *dev_hndl, uint8_t c2h, uint16_t hw_qid,
- struct qdma_descq_sw_ctxt *ctxt,
- enum qdma_hw_access_type access_type)
-{
- int ret_val = 0;
-
- switch (access_type) {
- case QDMA_HW_ACCESS_READ:
- ret_val = qdma_s80_hard_sw_context_read(dev_hndl, c2h, hw_qid,
- ctxt);
- break;
- case QDMA_HW_ACCESS_WRITE:
- ret_val = qdma_s80_hard_sw_context_write(dev_hndl, c2h, hw_qid,
- ctxt);
- break;
- case QDMA_HW_ACCESS_CLEAR:
- ret_val = qdma_s80_hard_sw_context_clear(dev_hndl, c2h, hw_qid);
- break;
- case QDMA_HW_ACCESS_INVALIDATE:
- ret_val = qdma_s80_hard_sw_context_invalidate(dev_hndl,
- c2h, hw_qid);
- break;
- default:
- qdma_log_error("%s: access_type=%d is invalid, err:%d\n",
- __func__, access_type,
- -QDMA_ERR_INV_PARAM);
- ret_val = -QDMA_ERR_INV_PARAM;
- break;
- }
- return ret_val;
-}
-
-/*****************************************************************************/
-/**
- * qdma_s80_hard_pfetch_context_write() - create prefetch context and program it
- *
- * @dev_hndl: device handle
- * @hw_qid: hardware qid of the queue
- * @ctxt: pointer to the prefetch context data strucutre
- *
- * Return: 0 - success and < 0 - failure
- *****************************************************************************/
-static int qdma_s80_hard_pfetch_context_write(void *dev_hndl, uint16_t hw_qid,
- const struct qdma_descq_prefetch_ctxt *ctxt)
-{
- uint32_t pfetch_ctxt[QDMA_S80_HARD_PFETCH_CONTEXT_NUM_WORDS] = {0};
- enum ind_ctxt_cmd_sel sel = QDMA_CTXT_SEL_PFTCH;
- uint32_t sw_crdt_l, sw_crdt_h;
- uint16_t num_words_count = 0;
-
- if (!dev_hndl || !ctxt) {
- qdma_log_error("%s: dev_hndl=%p pfetch_ctxt=%p, err:%d\n",
- __func__, dev_hndl, ctxt,
- -QDMA_ERR_INV_PARAM);
- return -QDMA_ERR_INV_PARAM;
- }
-
- sw_crdt_l =
- FIELD_GET(QDMA_PFTCH_CTXT_SW_CRDT_GET_L_MASK, ctxt->sw_crdt);
- sw_crdt_h =
- FIELD_GET(QDMA_PFTCH_CTXT_SW_CRDT_GET_H_MASK, ctxt->sw_crdt);
-
- pfetch_ctxt[num_words_count++] =
- FIELD_SET(PREFETCH_CTXT_DATA_W0_BYPASS_MASK, ctxt->bypass) |
- FIELD_SET(PREFETCH_CTXT_DATA_W0_BUF_SIZE_IDX_MASK,
- ctxt->bufsz_idx) |
- FIELD_SET(PREFETCH_CTXT_DATA_W0_PORT_ID_MASK, ctxt->port_id) |
- FIELD_SET(PREFETCH_CTXT_DATA_W0_ERR_MASK, ctxt->err) |
- FIELD_SET(PREFETCH_CTXT_DATA_W0_PFCH_EN_MASK, ctxt->pfch_en) |
- FIELD_SET(PREFETCH_CTXT_DATA_W0_PFCH_MASK, ctxt->pfch) |
- FIELD_SET(PREFETCH_CTXT_DATA_W0_SW_CRDT_L_MASK, sw_crdt_l);
-
- pfetch_ctxt[num_words_count++] =
- FIELD_SET(PREFETCH_CTXT_DATA_W1_SW_CRDT_H_MASK, sw_crdt_h) |
- FIELD_SET(PREFETCH_CTXT_DATA_W1_VALID_MASK, ctxt->valid);
-
- return qdma_s80_hard_indirect_reg_write(dev_hndl, sel, hw_qid,
- pfetch_ctxt, num_words_count);
-}
-
-/*****************************************************************************/
-/**
- * qdma_s80_hard_pfetch_context_read() - read prefetch context
- *
- * @dev_hndl: device handle
- * @hw_qid: hardware qid of the queue
- * @ctxt: pointer to the output context data
- *
- * Return: 0 - success and < 0 - failure
- *****************************************************************************/
-static int qdma_s80_hard_pfetch_context_read(void *dev_hndl, uint16_t hw_qid,
- struct qdma_descq_prefetch_ctxt *ctxt)
-{
- int rv = 0;
- uint32_t pfetch_ctxt[QDMA_S80_HARD_PFETCH_CONTEXT_NUM_WORDS] = {0};
- enum ind_ctxt_cmd_sel sel = QDMA_CTXT_SEL_PFTCH;
- uint32_t sw_crdt_l, sw_crdt_h;
-
- if (!dev_hndl || !ctxt) {
- qdma_log_error("%s: dev_hndl=%p pfetch_ctxt=%p, err:%d\n",
- __func__, dev_hndl, ctxt,
- -QDMA_ERR_INV_PARAM);
- return -QDMA_ERR_INV_PARAM;
- }
-
- rv = qdma_s80_hard_indirect_reg_read(dev_hndl, sel, hw_qid,
- QDMA_S80_HARD_PFETCH_CONTEXT_NUM_WORDS, pfetch_ctxt);
- if (rv < 0)
- return rv;
-
- ctxt->bypass =
- (uint8_t)(FIELD_GET(PREFETCH_CTXT_DATA_W0_BYPASS_MASK,
- pfetch_ctxt[0]));
- ctxt->bufsz_idx =
- (uint8_t)(FIELD_GET(PREFETCH_CTXT_DATA_W0_BUF_SIZE_IDX_MASK,
- pfetch_ctxt[0]));
- ctxt->port_id =
- (uint8_t)(FIELD_GET(PREFETCH_CTXT_DATA_W0_PORT_ID_MASK,
- pfetch_ctxt[0]));
- ctxt->err =
- (uint8_t)(FIELD_GET(PREFETCH_CTXT_DATA_W0_ERR_MASK,
- pfetch_ctxt[0]));
- ctxt->pfch_en =
- (uint8_t)(FIELD_GET(PREFETCH_CTXT_DATA_W0_PFCH_EN_MASK,
- pfetch_ctxt[0]));
- ctxt->pfch =
- (uint8_t)(FIELD_GET(PREFETCH_CTXT_DATA_W0_PFCH_MASK,
- pfetch_ctxt[0]));
- sw_crdt_l =
- (uint32_t)FIELD_GET(PREFETCH_CTXT_DATA_W0_SW_CRDT_L_MASK,
- pfetch_ctxt[0]);
-
- sw_crdt_h =
- (uint32_t)FIELD_GET(PREFETCH_CTXT_DATA_W1_SW_CRDT_H_MASK,
- pfetch_ctxt[1]);
- ctxt->valid =
- (uint8_t)(FIELD_GET(PREFETCH_CTXT_DATA_W1_VALID_MASK,
- pfetch_ctxt[1]));
-
- ctxt->sw_crdt =
- (uint16_t)(FIELD_SET(QDMA_PFTCH_CTXT_SW_CRDT_GET_L_MASK,
- sw_crdt_l) |
- FIELD_SET(QDMA_PFTCH_CTXT_SW_CRDT_GET_H_MASK, sw_crdt_h));
-
- return QDMA_SUCCESS;
-}
-
-/*****************************************************************************/
-/**
- * qdma_s80_hard_pfetch_context_clear() - clear prefetch context
- *
- * @dev_hndl: device handle
- * @hw_qid: hardware qid of the queue
- *
- * Return: 0 - success and < 0 - failure
- *****************************************************************************/
-static int qdma_s80_hard_pfetch_context_clear(void *dev_hndl, uint16_t hw_qid)
-{
- enum ind_ctxt_cmd_sel sel = QDMA_CTXT_SEL_PFTCH;
-
- if (!dev_hndl) {
- qdma_log_error("%s: dev_handle is NULL, err:%d\n",
- __func__, -QDMA_ERR_INV_PARAM);
- return -QDMA_ERR_INV_PARAM;
- }
-
- return qdma_s80_hard_indirect_reg_clear(dev_hndl, sel, hw_qid);
-}
-
-/*****************************************************************************/
-/**
- * qdma_s80_hard_pfetch_context_invalidate() - invalidate prefetch context
- *
- * @dev_hndl: device handle
- * @hw_qid: hardware qid of the queue
- *
- * Return: 0 - success and < 0 - failure
- *****************************************************************************/
-static int qdma_s80_hard_pfetch_context_invalidate(void *dev_hndl,
- uint16_t hw_qid)
-{
- enum ind_ctxt_cmd_sel sel = QDMA_CTXT_SEL_PFTCH;
-
- if (!dev_hndl) {
- qdma_log_error("%s: dev_handle is NULL, err:%d\n",
- __func__, -QDMA_ERR_INV_PARAM);
- return -QDMA_ERR_INV_PARAM;
- }
-
- return qdma_s80_hard_indirect_reg_invalidate(dev_hndl, sel, hw_qid);
-}
-
-/*****************************************************************************/
-/**
- * qdma_s80_hard_pfetch_ctx_conf() - configure prefetch context
- *
- * @dev_hndl: device handle
- * @hw_qid: hardware qid of the queue
- * @ctxt: pointer to context data
- * @access_type HW access type (qdma_hw_access_type enum) value
- *
- * Return: 0 - success and < 0 - failure
- *****************************************************************************/
-int qdma_s80_hard_pfetch_ctx_conf(void *dev_hndl, uint16_t hw_qid,
- struct qdma_descq_prefetch_ctxt *ctxt,
- enum qdma_hw_access_type access_type)
-{
- int ret_val = 0;
-
- switch (access_type) {
- case QDMA_HW_ACCESS_READ:
- ret_val = qdma_s80_hard_pfetch_context_read(dev_hndl,
- hw_qid, ctxt);
- break;
- case QDMA_HW_ACCESS_WRITE:
- ret_val = qdma_s80_hard_pfetch_context_write(dev_hndl,
- hw_qid, ctxt);
- break;
- case QDMA_HW_ACCESS_CLEAR:
- ret_val = qdma_s80_hard_pfetch_context_clear(dev_hndl, hw_qid);
- break;
- case QDMA_HW_ACCESS_INVALIDATE:
- ret_val = qdma_s80_hard_pfetch_context_invalidate(dev_hndl,
- hw_qid);
- break;
- default:
- qdma_log_error("%s: access_type=%d is invalid, err:%d\n",
- __func__, access_type,
- -QDMA_ERR_INV_PARAM);
- ret_val = -QDMA_ERR_INV_PARAM;
- break;
- }
-
- return ret_val;
-}
-
-/*****************************************************************************/
-/**
- * qdma_s80_hard_cmpt_context_write() - create completion context and program it
- *
- * @dev_hndl: device handle
- * @hw_qid: hardware qid of the queue
- * @ctxt: pointer to the cmpt context data strucutre
- *
- * Return: 0 - success and < 0 - failure
- *****************************************************************************/
-static int qdma_s80_hard_cmpt_context_write(void *dev_hndl, uint16_t hw_qid,
- const struct qdma_descq_cmpt_ctxt *ctxt)
-{
- uint32_t cmpt_ctxt[QDMA_S80_HARD_CMPT_CONTEXT_NUM_WORDS] = {0};
- uint16_t num_words_count = 0;
- uint32_t baddr_l, baddr_h, baddr_m, pidx_l, pidx_h;
- enum ind_ctxt_cmd_sel sel = QDMA_CTXT_SEL_CMPT;
-
- /* Input args check */
- if (!dev_hndl || !ctxt) {
- qdma_log_error("%s: dev_hndl=%p cmpt_ctxt=%p, err:%d\n",
- __func__, dev_hndl, ctxt,
- -QDMA_ERR_INV_PARAM);
- return -QDMA_ERR_INV_PARAM;
- }
-
- if ((ctxt->desc_sz > QDMA_DESC_SIZE_32B) ||
- (ctxt->ringsz_idx >= QDMA_NUM_RING_SIZES) ||
- (ctxt->counter_idx >= QDMA_NUM_C2H_COUNTERS) ||
- (ctxt->timer_idx >= QDMA_NUM_C2H_TIMERS) ||
- (ctxt->trig_mode > QDMA_CMPT_UPDATE_TRIG_MODE_TMR_CNTR)) {
- qdma_log_error
- ("%s Inv dsz(%d)/ridx(%d)/cntr(%d)/tmr(%d)/tm(%d), err:%d\n",
- __func__,
- ctxt->desc_sz,
- ctxt->ringsz_idx,
- ctxt->counter_idx,
- ctxt->timer_idx,
- ctxt->trig_mode,
- -QDMA_ERR_INV_PARAM);
- return -QDMA_ERR_INV_PARAM;
- }
-
- baddr_l =
- (uint32_t)FIELD_GET(QDMA_S80_HARD_COMPL_CTXT_BADDR_GET_L_MASK,
- ctxt->bs_addr);
- baddr_m =
- (uint32_t)FIELD_GET(QDMA_S80_HARD_COMPL_CTXT_BADDR_GET_M_MASK,
- ctxt->bs_addr);
- baddr_h =
- (uint32_t)FIELD_GET(QDMA_S80_HARD_COMPL_CTXT_BADDR_GET_H_MASK,
- ctxt->bs_addr);
-
- pidx_l = FIELD_GET(QDMA_S80_HARD_COMPL_CTXT_PIDX_GET_L_MASK,
- ctxt->pidx);
- pidx_h = FIELD_GET(QDMA_S80_HARD_COMPL_CTXT_PIDX_GET_H_MASK,
- ctxt->pidx);
-
- cmpt_ctxt[num_words_count++] =
- FIELD_SET(CMPL_CTXT_DATA_W0_EN_STAT_DESC_MASK,
- ctxt->en_stat_desc) |
- FIELD_SET(CMPL_CTXT_DATA_W0_EN_INT_MASK, ctxt->en_int) |
- FIELD_SET(CMPL_CTXT_DATA_W0_TRIG_MODE_MASK, ctxt->trig_mode) |
- FIELD_SET(CMPL_CTXT_DATA_W0_FNC_ID_MASK, ctxt->fnc_id) |
- FIELD_SET(CMPL_CTXT_DATA_W0_CNTER_IDX_MASK,
- ctxt->counter_idx) |
- FIELD_SET(CMPL_CTXT_DATA_W0_TIMER_IDX_MASK,
- ctxt->timer_idx) |
- FIELD_SET(CMPL_CTXT_DATA_W0_INT_ST_MASK,
- ctxt->in_st) |
- FIELD_SET(CMPL_CTXT_DATA_W0_COLOR_MASK,
- ctxt->color) |
- FIELD_SET(CMPL_CTXT_DATA_W0_QSIZE_IDX_MASK,
- ctxt->ringsz_idx) |
- FIELD_SET(CMPL_CTXT_DATA_W0_BADDR_64_L_MASK,
- baddr_l);
-
- cmpt_ctxt[num_words_count++] =
- FIELD_SET(CMPL_CTXT_DATA_W1_BADDR_64_M_MASK,
- baddr_m);
-
- cmpt_ctxt[num_words_count++] =
- FIELD_SET(CMPL_CTXT_DATA_W2_BADDR_64_H_MASK,
- baddr_h) |
- FIELD_SET(CMPL_CTXT_DATA_W2_DESC_SIZE_MASK,
- ctxt->desc_sz) |
- FIELD_SET(CMPL_CTXT_DATA_W2_PIDX_L_MASK,
- pidx_l);
-
- cmpt_ctxt[num_words_count++] =
- FIELD_SET(CMPL_CTXT_DATA_W3_PIDX_H_MASK,
- pidx_h) |
- FIELD_SET(CMPL_CTXT_DATA_W3_CIDX_MASK, ctxt->cidx) |
- FIELD_SET(CMPL_CTXT_DATA_W3_VALID_MASK, ctxt->valid) |
- FIELD_SET(CMPL_CTXT_DATA_W3_ERR_MASK, ctxt->err) |
- FIELD_SET(CMPL_CTXT_DATA_W3_USER_TRIG_PEND_MASK,
- ctxt->user_trig_pend) |
- FIELD_SET(CMPL_CTXT_DATA_W3_TIMER_RUNNING_MASK,
- ctxt->timer_running) |
- FIELD_SET(CMPL_CTXT_DATA_W3_FULL_UPD_MASK,
- ctxt->full_upd);
-
- return qdma_s80_hard_indirect_reg_write(dev_hndl, sel, hw_qid,
- cmpt_ctxt, num_words_count);
-
-}
-
-/*****************************************************************************/
-/**
- * qdma_s80_hard_cmpt_context_read() - read completion context
- *
- * @dev_hndl: device handle
- * @hw_qid: hardware qid of the queue
- * @ctxt: pointer to the context data
- *
- * Return: 0 - success and < 0 - failure
- *****************************************************************************/
-static int qdma_s80_hard_cmpt_context_read(void *dev_hndl, uint16_t hw_qid,
- struct qdma_descq_cmpt_ctxt *ctxt)
-{
- int rv = 0;
- uint32_t cmpt_ctxt[QDMA_S80_HARD_CMPT_CONTEXT_NUM_WORDS] = {0};
- enum ind_ctxt_cmd_sel sel = QDMA_CTXT_SEL_CMPT;
- uint32_t baddr_l, baddr_h, baddr_m,
- pidx_l, pidx_h;
-
- if (!dev_hndl || !ctxt) {
- qdma_log_error("%s: dev_hndl=%p cmpt_ctxt=%p, err:%d\n",
- __func__, dev_hndl, ctxt,
- -QDMA_ERR_INV_PARAM);
- return -QDMA_ERR_INV_PARAM;
- }
-
- rv = qdma_s80_hard_indirect_reg_read(dev_hndl, sel, hw_qid,
- QDMA_S80_HARD_CMPT_CONTEXT_NUM_WORDS, cmpt_ctxt);
- if (rv < 0)
- return rv;
-
- ctxt->en_stat_desc =
- FIELD_GET(CMPL_CTXT_DATA_W0_EN_STAT_DESC_MASK, cmpt_ctxt[0]);
- ctxt->en_int = FIELD_GET(CMPL_CTXT_DATA_W0_EN_INT_MASK,
- cmpt_ctxt[0]);
- ctxt->trig_mode =
- FIELD_GET(CMPL_CTXT_DATA_W0_TRIG_MODE_MASK, cmpt_ctxt[0]);
- ctxt->fnc_id =
- (uint8_t)(FIELD_GET(CMPL_CTXT_DATA_W0_FNC_ID_MASK,
- cmpt_ctxt[0]));
- ctxt->counter_idx =
- (uint8_t)(FIELD_GET(
- CMPL_CTXT_DATA_W0_CNTER_IDX_MASK,
- cmpt_ctxt[0]));
- ctxt->timer_idx =
- (uint8_t)(FIELD_GET(CMPL_CTXT_DATA_W0_TIMER_IDX_MASK,
- cmpt_ctxt[0]));
- ctxt->in_st =
- (uint8_t)(FIELD_GET(CMPL_CTXT_DATA_W0_INT_ST_MASK,
- cmpt_ctxt[0]));
- ctxt->color =
- (uint8_t)(FIELD_GET(CMPL_CTXT_DATA_W0_COLOR_MASK,
- cmpt_ctxt[0]));
- ctxt->ringsz_idx =
- (uint8_t)(FIELD_GET(CMPL_CTXT_DATA_W0_QSIZE_IDX_MASK,
- cmpt_ctxt[0]));
-
- baddr_l =
- FIELD_GET(CMPL_CTXT_DATA_W0_BADDR_64_L_MASK,
- cmpt_ctxt[0]);
- baddr_m =
- FIELD_GET(CMPL_CTXT_DATA_W1_BADDR_64_M_MASK,
- cmpt_ctxt[1]);
- baddr_h =
- FIELD_GET(CMPL_CTXT_DATA_W2_BADDR_64_H_MASK,
- cmpt_ctxt[2]);
-
- ctxt->desc_sz =
- (uint8_t)(FIELD_GET(CMPL_CTXT_DATA_W2_DESC_SIZE_MASK,
- cmpt_ctxt[2]));
- pidx_l = FIELD_GET(CMPL_CTXT_DATA_W2_PIDX_L_MASK,
- cmpt_ctxt[2]);
-
- pidx_h = FIELD_GET(CMPL_CTXT_DATA_W3_PIDX_H_MASK,
- cmpt_ctxt[3]);
- ctxt->cidx =
- (uint16_t)(FIELD_GET(CMPL_CTXT_DATA_W3_CIDX_MASK,
- cmpt_ctxt[3]));
- ctxt->valid =
- (uint8_t)(FIELD_GET(CMPL_CTXT_DATA_W3_VALID_MASK,
- cmpt_ctxt[3]));
- ctxt->err =
- (uint8_t)(FIELD_GET(CMPL_CTXT_DATA_W3_ERR_MASK,
- cmpt_ctxt[3]));
- ctxt->user_trig_pend =
- (uint8_t)(FIELD_GET(
- CMPL_CTXT_DATA_W3_USER_TRIG_PEND_MASK, cmpt_ctxt[3]));
-
- ctxt->timer_running =
- (uint8_t)(FIELD_GET(CMPL_CTXT_DATA_W3_TIMER_RUNNING_MASK,
- cmpt_ctxt[3]));
- ctxt->full_upd =
- (uint8_t)(FIELD_GET(CMPL_CTXT_DATA_W3_FULL_UPD_MASK,
- cmpt_ctxt[3]));
-
- ctxt->bs_addr =
- FIELD_SET(QDMA_S80_HARD_COMPL_CTXT_BADDR_GET_L_MASK,
- (uint64_t)baddr_l) |
- FIELD_SET(QDMA_S80_HARD_COMPL_CTXT_BADDR_GET_M_MASK,
- (uint64_t)baddr_m) |
- FIELD_SET(QDMA_S80_HARD_COMPL_CTXT_BADDR_GET_H_MASK,
- (uint64_t)baddr_h);
-
- ctxt->pidx =
- (uint16_t)(FIELD_SET(QDMA_S80_HARD_COMPL_CTXT_PIDX_GET_L_MASK,
- pidx_l) |
- FIELD_SET(QDMA_S80_HARD_COMPL_CTXT_PIDX_GET_H_MASK,
- pidx_h));
-
- return QDMA_SUCCESS;
-}
-
-/*****************************************************************************/
-/**
- * qdma_s80_hard_cmpt_context_clear() - clear completion context
- *
- * @dev_hndl: device handle
- * @hw_qid: hardware qid of the queue
- *
- * Return: 0 - success and < 0 - failure
- *****************************************************************************/
-static int qdma_s80_hard_cmpt_context_clear(void *dev_hndl, uint16_t hw_qid)
-{
- enum ind_ctxt_cmd_sel sel = QDMA_CTXT_SEL_CMPT;
-
- if (!dev_hndl) {
- qdma_log_error("%s: dev_handle is NULL, err:%d\n",
- __func__, -QDMA_ERR_INV_PARAM);
- return -QDMA_ERR_INV_PARAM;
- }
-
- return qdma_s80_hard_indirect_reg_clear(dev_hndl, sel, hw_qid);
-}
-
-/*****************************************************************************/
-/**
- * qdma_s80_hard_cmpt_context_invalidate() - invalidate completion context
- *
- * @dev_hndl: device handle
- * @hw_qid: hardware qid of the queue
- *
- * Return: 0 - success and < 0 - failure
- *****************************************************************************/
-static int qdma_s80_hard_cmpt_context_invalidate(void *dev_hndl,
- uint16_t hw_qid)
-{
- enum ind_ctxt_cmd_sel sel = QDMA_CTXT_SEL_CMPT;
-
- if (!dev_hndl) {
- qdma_log_error("%s: dev_handle is NULL, err:%d\n",
- __func__, -QDMA_ERR_INV_PARAM);
- return -QDMA_ERR_INV_PARAM;
- }
-
- return qdma_s80_hard_indirect_reg_invalidate(dev_hndl, sel, hw_qid);
-}
-
-/*****************************************************************************/
-/**
- * qdma_s80_hard_cmpt_ctx_conf() - configure completion context
- *
- * @dev_hndl: device handle
- * @hw_qid: hardware qid of the queue
- * @ctxt: pointer to context data
- * @access_type HW access type (qdma_hw_access_type enum) value
- *
- * Return: 0 - success and < 0 - failure
- *****************************************************************************/
-int qdma_s80_hard_cmpt_ctx_conf(void *dev_hndl, uint16_t hw_qid,
- struct qdma_descq_cmpt_ctxt *ctxt,
- enum qdma_hw_access_type access_type)
-{
- int ret_val = 0;
-
- if (!dev_hndl) {
- qdma_log_error("%s: dev_handle is NULL, err:%d\n",
- __func__, -QDMA_ERR_INV_PARAM);
- return -QDMA_ERR_INV_PARAM;
- }
-
- switch (access_type) {
- case QDMA_HW_ACCESS_READ:
- ret_val = qdma_s80_hard_cmpt_context_read(dev_hndl,
- hw_qid, ctxt);
- break;
- case QDMA_HW_ACCESS_WRITE:
- ret_val = qdma_s80_hard_cmpt_context_write(dev_hndl,
- hw_qid, ctxt);
- break;
- case QDMA_HW_ACCESS_CLEAR:
- ret_val = qdma_s80_hard_cmpt_context_clear(dev_hndl, hw_qid);
- break;
- case QDMA_HW_ACCESS_INVALIDATE:
- ret_val = qdma_s80_hard_cmpt_context_invalidate(dev_hndl,
- hw_qid);
- break;
- default:
- qdma_log_error("%s: access_type=%d is invalid, err:%d\n",
- __func__, access_type,
- -QDMA_ERR_INV_PARAM);
- ret_val = -QDMA_ERR_INV_PARAM;
- break;
- }
-
- return ret_val;
-}
-
-/*****************************************************************************/
-/**
- * qdma_s80_hard_hw_context_read() - read hardware context
- *
- * @dev_hndl: device handle
- * @c2h: is c2h queue
- * @hw_qid: hardware qid of the queue
- * @ctxt: pointer to the output context data
- *
- * Return: 0 - success and < 0 - failure
- *****************************************************************************/
-static int qdma_s80_hard_hw_context_read(void *dev_hndl, uint8_t c2h,
- uint16_t hw_qid, struct qdma_descq_hw_ctxt *ctxt)
-{
- int rv = 0;
- uint32_t hw_ctxt[QDMA_S80_HARD_HW_CONTEXT_NUM_WORDS] = {0};
- enum ind_ctxt_cmd_sel sel = c2h ? QDMA_CTXT_SEL_HW_C2H :
- QDMA_CTXT_SEL_HW_H2C;
-
- if (!dev_hndl || !ctxt) {
- qdma_log_error("%s: dev_hndl=%p hw_ctxt=%p, err:%d\n",
- __func__, dev_hndl, ctxt,
- -QDMA_ERR_INV_PARAM);
- return -QDMA_ERR_INV_PARAM;
- }
-
- rv = qdma_s80_hard_indirect_reg_read(dev_hndl, sel, hw_qid,
- QDMA_S80_HARD_HW_CONTEXT_NUM_WORDS, hw_ctxt);
- if (rv < 0)
- return rv;
-
- ctxt->cidx = FIELD_GET(HW_IND_CTXT_DATA_W0_CIDX_MASK, hw_ctxt[0]);
- ctxt->crd_use =
- (uint16_t)(FIELD_GET(HW_IND_CTXT_DATA_W0_CRD_USE_MASK,
- hw_ctxt[0]));
-
- ctxt->dsc_pend =
- (uint8_t)(FIELD_GET(HW_IND_CTXT_DATA_W1_DSC_PND_MASK,
- hw_ctxt[1]));
- ctxt->idl_stp_b =
- (uint8_t)(FIELD_GET(HW_IND_CTXT_DATA_W1_IDL_STP_B_MASK,
- hw_ctxt[1]));
- ctxt->fetch_pnd =
- (uint8_t)(FIELD_GET(HW_IND_CTXT_DATA_W1_FETCH_PND_MASK,
- hw_ctxt[1]));
-
- return QDMA_SUCCESS;
-}
-
-/*****************************************************************************/
-/**
- * qdma_s80_hard_hw_context_clear() - clear hardware context
- *
- * @dev_hndl: device handle
- * @c2h: is c2h queue
- * @hw_qid: hardware qid of the queue
- *
- * Return: 0 - success and < 0 - failure
- *****************************************************************************/
-static int qdma_s80_hard_hw_context_clear(void *dev_hndl, uint8_t c2h,
- uint16_t hw_qid)
-{
- enum ind_ctxt_cmd_sel sel = c2h ? QDMA_CTXT_SEL_HW_C2H :
- QDMA_CTXT_SEL_HW_H2C;
-
- if (!dev_hndl) {
- qdma_log_error("%s: dev_handle is NULL, err:%d\n",
- __func__, -QDMA_ERR_INV_PARAM);
- return -QDMA_ERR_INV_PARAM;
- }
-
- return qdma_s80_hard_indirect_reg_clear(dev_hndl, sel, hw_qid);
-}
-
-/*****************************************************************************/
-/**
- * qdma_s80_hard_hw_context_invalidate() - invalidate hardware context
- *
- * @dev_hndl: device handle
- * @c2h: is c2h queue
- * @hw_qid: hardware qid of the queue
- *
- * Return: 0 - success and < 0 - failure
- *****************************************************************************/
-static int qdma_s80_hard_hw_context_invalidate(void *dev_hndl, uint8_t c2h,
- uint16_t hw_qid)
-{
- enum ind_ctxt_cmd_sel sel = c2h ? QDMA_CTXT_SEL_HW_C2H :
- QDMA_CTXT_SEL_HW_H2C;
-
- if (!dev_hndl) {
- qdma_log_error("%s: dev_handle is NULL, err:%d\n",
- __func__, -QDMA_ERR_INV_PARAM);
- return -QDMA_ERR_INV_PARAM;
- }
-
- return qdma_s80_hard_indirect_reg_invalidate(dev_hndl, sel, hw_qid);
-}
-
-/*****************************************************************************/
-/**
- * qdma_s80_hard_hw_ctx_conf() - configure HW context
- *
- * @dev_hndl: device handle
- * @c2h: is c2h queue
- * @hw_qid: hardware qid of the queue
- * @ctxt: pointer to context data
- * @access_type HW access type (qdma_hw_access_type enum) value
- * QDMA_HW_ACCESS_WRITE unsupported
- *
- * Return: 0 - success and < 0 - failure
- *****************************************************************************/
-int qdma_s80_hard_hw_ctx_conf(void *dev_hndl, uint8_t c2h, uint16_t hw_qid,
- struct qdma_descq_hw_ctxt *ctxt,
- enum qdma_hw_access_type access_type)
-{
- int ret_val = 0;
-
- switch (access_type) {
- case QDMA_HW_ACCESS_READ:
- ret_val = qdma_s80_hard_hw_context_read(dev_hndl, c2h, hw_qid,
- ctxt);
- break;
- case QDMA_HW_ACCESS_CLEAR:
- ret_val = qdma_s80_hard_hw_context_clear(dev_hndl, c2h, hw_qid);
- break;
- case QDMA_HW_ACCESS_INVALIDATE:
- ret_val = qdma_s80_hard_hw_context_invalidate(dev_hndl, c2h,
- hw_qid);
- break;
- case QDMA_HW_ACCESS_WRITE:
- default:
- qdma_log_error("%s: access_type=%d is invalid, err:%d\n",
- __func__, access_type,
- -QDMA_ERR_INV_PARAM);
- ret_val = -QDMA_ERR_INV_PARAM;
- break;
- }
-
-
- return ret_val;
-}
-
-/*****************************************************************************/
-/**
- * qdma_s80_hard_indirect_intr_context_write() - create indirect
- * interrupt context and program it
- *
- * @dev_hndl: device handle
- * @ring_index: indirect interrupt ring index
- * @ctxt: pointer to the interrupt context data strucutre
- *
- * Return: 0 - success and < 0 - failure
- *****************************************************************************/
-static int qdma_s80_hard_indirect_intr_context_write(void *dev_hndl,
- uint16_t ring_index, const struct qdma_indirect_intr_ctxt *ctxt)
-{
- uint32_t intr_ctxt[QDMA_S80_HARD_IND_INTR_CONTEXT_NUM_WORDS] = {0};
- enum ind_ctxt_cmd_sel sel = QDMA_CTXT_SEL_INT_COAL;
- uint16_t num_words_count = 0;
- uint32_t baddr_l, baddr_h;
-
- if (!dev_hndl || !ctxt) {
- qdma_log_error("%s: dev_hndl=%p intr_ctxt=%p, err:%d\n",
- __func__, dev_hndl, ctxt,
- -QDMA_ERR_INV_PARAM);
- return -QDMA_ERR_INV_PARAM;
- }
-
- if (ctxt->page_size > QDMA_INDIRECT_INTR_RING_SIZE_32KB) {
- qdma_log_error("%s: ctxt->page_size=%u is too big, err:%d\n",
- __func__, ctxt->page_size,
- -QDMA_ERR_INV_PARAM);
- return -QDMA_ERR_INV_PARAM;
- }
-
- baddr_l =
- (uint32_t)FIELD_GET(QDMA_S80_HARD_INTR_CTXT_BADDR_GET_L_MASK,
- ctxt->baddr_4k);
- baddr_h =
- (uint32_t)FIELD_GET(QDMA_S80_HARD_INTR_CTXT_BADDR_GET_H_MASK,
- ctxt->baddr_4k);
-
- intr_ctxt[num_words_count++] =
- FIELD_SET(INTR_CTXT_DATA_W0_VALID_MASK, ctxt->valid) |
- FIELD_SET(INTR_CTXT_DATA_W0_VEC_MASK, ctxt->vec) |
- FIELD_SET(INTR_CTXT_DATA_W0_INT_ST_MASK,
- ctxt->int_st) |
- FIELD_SET(INTR_CTXT_DATA_W0_COLOR_MASK, ctxt->color) |
- FIELD_SET(INTR_CTXT_DATA_W0_BADDR_4K_L_MASK, baddr_l);
-
- intr_ctxt[num_words_count++] =
- FIELD_SET(INTR_CTXT_DATA_W1_BADDR_4K_H_MASK, baddr_h) |
- FIELD_SET(INTR_CTXT_DATA_W1_PAGE_SIZE_MASK,
- ctxt->page_size);
-
- intr_ctxt[num_words_count++] =
- FIELD_SET(INTR_CTXT_DATA_W2_PIDX_MASK, ctxt->pidx);
-
- return qdma_s80_hard_indirect_reg_write(dev_hndl, sel, ring_index,
- intr_ctxt, num_words_count);
-}
-
-/*****************************************************************************/
-/**
- * qdma_indirect_intr_context_read() - read indirect interrupt context
- *
- * @dev_hndl: device handle
- * @ring_index: indirect interrupt ring index
- * @ctxt: pointer to the output context data
- *
- * Return: 0 - success and < 0 - failure
- *****************************************************************************/
-static int qdma_s80_hard_indirect_intr_context_read(void *dev_hndl,
- uint16_t ring_index, struct qdma_indirect_intr_ctxt *ctxt)
-{
- int rv = 0;
- uint32_t intr_ctxt[QDMA_S80_HARD_IND_INTR_CONTEXT_NUM_WORDS] = {0};
- enum ind_ctxt_cmd_sel sel = QDMA_CTXT_SEL_INT_COAL;
- uint64_t baddr_l, baddr_h;
-
- if (!dev_hndl || !ctxt) {
- qdma_log_error("%s: dev_hndl=%p intr_ctxt=%p, err:%d\n",
- __func__, dev_hndl, ctxt,
- -QDMA_ERR_INV_PARAM);
- return -QDMA_ERR_INV_PARAM;
- }
-
- rv = qdma_s80_hard_indirect_reg_read(dev_hndl, sel, ring_index,
- QDMA_S80_HARD_IND_INTR_CONTEXT_NUM_WORDS, intr_ctxt);
- if (rv < 0)
- return rv;
-
- ctxt->valid = FIELD_GET(INTR_CTXT_DATA_W0_VALID_MASK, intr_ctxt[0]);
- ctxt->vec = FIELD_GET(INTR_CTXT_DATA_W0_VEC_MASK,
- intr_ctxt[0]);
- ctxt->int_st = FIELD_GET(INTR_CTXT_DATA_W0_INT_ST_MASK,
- intr_ctxt[0]);
- ctxt->color =
- (uint8_t)(FIELD_GET(INTR_CTXT_DATA_W0_COLOR_MASK,
- intr_ctxt[0]));
- baddr_l = FIELD_GET(INTR_CTXT_DATA_W0_BADDR_4K_L_MASK,
- intr_ctxt[0]);
-
- baddr_h = FIELD_GET(INTR_CTXT_DATA_W1_BADDR_4K_H_MASK,
- intr_ctxt[1]);
- ctxt->page_size =
- (uint8_t)(FIELD_GET(INTR_CTXT_DATA_W1_PAGE_SIZE_MASK,
- intr_ctxt[1]));
- ctxt->pidx = FIELD_GET(INTR_CTXT_DATA_W2_PIDX_MASK,
- intr_ctxt[2]);
-
- ctxt->baddr_4k =
- FIELD_SET(QDMA_S80_HARD_INTR_CTXT_BADDR_GET_L_MASK, baddr_l) |
- FIELD_SET(QDMA_S80_HARD_INTR_CTXT_BADDR_GET_H_MASK, baddr_h);
-
- return QDMA_SUCCESS;
-}
-
-/*****************************************************************************/
-/**
- * qdma_s80_hard_indirect_intr_context_clear() - clear indirect
- * interrupt context
- *
- * @dev_hndl: device handle
- * @ring_index: indirect interrupt ring index
- *
- * Return: 0 - success and < 0 - failure
- *****************************************************************************/
-static int qdma_s80_hard_indirect_intr_context_clear(void *dev_hndl,
- uint16_t ring_index)
-{
- enum ind_ctxt_cmd_sel sel = QDMA_CTXT_SEL_INT_COAL;
-
- if (!dev_hndl) {
- qdma_log_error("%s: dev_handle is NULL, err:%d\n",
- __func__, -QDMA_ERR_INV_PARAM);
- return -QDMA_ERR_INV_PARAM;
- }
-
- return qdma_s80_hard_indirect_reg_clear(dev_hndl, sel, ring_index);
-}
-
-/*****************************************************************************/
-/**
- * qdma_s80_hard_indirect_intr_context_invalidate() - invalidate
- * indirect interrupt context
- *
- * @dev_hndl: device handle
- * @ring_index: indirect interrupt ring index
- *
- * Return: 0 - success and < 0 - failure
- *****************************************************************************/
-static int qdma_s80_hard_indirect_intr_context_invalidate(void *dev_hndl,
- uint16_t ring_index)
-{
- enum ind_ctxt_cmd_sel sel = QDMA_CTXT_SEL_INT_COAL;
-
- if (!dev_hndl) {
- qdma_log_error("%s: dev_handle is NULL, err:%d\n",
- __func__, -QDMA_ERR_INV_PARAM);
- return -QDMA_ERR_INV_PARAM;
- }
-
- return qdma_s80_hard_indirect_reg_invalidate(dev_hndl, sel, ring_index);
-}
-
-/*****************************************************************************/
-/**
- * qdma_s80_hard_indirect_intr_ctx_conf() - configure indirect interrupt context
- *
- * @dev_hndl: device handle
- * @ring_index: indirect interrupt ring index
- * @ctxt: pointer to context data
- * @access_type HW access type (qdma_hw_access_type enum) value
- *
- * Return: 0 - success and < 0 - failure
- *****************************************************************************/
-int qdma_s80_hard_indirect_intr_ctx_conf(void *dev_hndl, uint16_t ring_index,
- struct qdma_indirect_intr_ctxt *ctxt,
- enum qdma_hw_access_type access_type)
-{
- int ret_val = 0;
-
- switch (access_type) {
- case QDMA_HW_ACCESS_READ:
- ret_val = qdma_s80_hard_indirect_intr_context_read(dev_hndl,
- ring_index,
- ctxt);
- break;
- case QDMA_HW_ACCESS_WRITE:
- ret_val = qdma_s80_hard_indirect_intr_context_write(dev_hndl,
- ring_index,
- ctxt);
- break;
- case QDMA_HW_ACCESS_CLEAR:
- ret_val = qdma_s80_hard_indirect_intr_context_clear(dev_hndl,
- ring_index);
- break;
- case QDMA_HW_ACCESS_INVALIDATE:
- ret_val = qdma_s80_hard_indirect_intr_context_invalidate(
- dev_hndl, ring_index);
- break;
- default:
- qdma_log_error("%s: access_type=%d is invalid, err:%d\n",
- __func__, access_type,
- -QDMA_ERR_INV_PARAM);
- ret_val = -QDMA_ERR_INV_PARAM;
- break;
- }
-
- return ret_val;
-}
-
-/*****************************************************************************/
-/**
- * qdma_s80_hard_set_default_global_csr() - function to set the global
- * CSR register to default values. The value can be modified later by using
- * the set/get csr functions
- *
- * @dev_hndl: device handle
- *
- * Return: 0 - success and < 0 - failure
- *****************************************************************************/
-int qdma_s80_hard_set_default_global_csr(void *dev_hndl)
-{
- /* Default values */
- uint32_t reg_val = 0;
- uint32_t rng_sz[QDMA_NUM_RING_SIZES] = {2049, 65, 129, 193, 257,
- 385, 513, 769, 1025, 1537, 3073, 4097, 6145,
- 8193, 12289, 16385};
- uint32_t tmr_cnt[QDMA_NUM_C2H_TIMERS] = {1, 2, 4, 5, 8, 10, 15, 20, 25,
- 30, 50, 75, 100, 125, 150, 200};
- uint32_t cnt_th[QDMA_NUM_C2H_COUNTERS] = {2, 4, 8, 16, 24,
- 32, 48, 64, 80, 96, 112, 128, 144,
- 160, 176, 192};
- uint32_t buf_sz[QDMA_NUM_C2H_BUFFER_SIZES] = {4096, 256, 512, 1024,
- 2048, 3968, 4096, 4096, 4096, 4096, 4096, 4096,
- 4096, 8192, 9018, 16384};
- struct qdma_dev_attributes dev_cap;
-
- if (!dev_hndl) {
- qdma_log_error("%s: dev_handle is NULL, err:%d\n",
- __func__, -QDMA_ERR_INV_PARAM);
- return -QDMA_ERR_INV_PARAM;
- }
-
- qdma_s80_hard_get_device_attributes(dev_hndl, &dev_cap);
-
- /* Configuring CSR registers */
- /* Global ring sizes */
- qdma_write_csr_values(dev_hndl, QDMA_S80_HARD_GLBL_RNG_SZ_1_ADDR, 0,
- QDMA_NUM_RING_SIZES, rng_sz);
-
- if (dev_cap.st_en || dev_cap.mm_cmpt_en) {
- /* Counter thresholds */
- qdma_write_csr_values(dev_hndl,
- QDMA_S80_HARD_C2H_CNT_TH_1_ADDR, 0,
- QDMA_NUM_C2H_COUNTERS, cnt_th);
-
- /* Timer Counters */
- qdma_write_csr_values(dev_hndl,
- QDMA_S80_HARD_C2H_TIMER_CNT_1_ADDR, 0,
- QDMA_NUM_C2H_TIMERS, tmr_cnt);
-
-
- /* Writeback Interval */
- reg_val =
- FIELD_SET(GLBL_DSC_CFG_MAXFETCH_MASK,
- DEFAULT_MAX_DSC_FETCH) |
- FIELD_SET(GLBL_DSC_CFG_WB_ACC_INT_MASK,
- DEFAULT_WRB_INT);
- qdma_reg_write(dev_hndl,
- QDMA_S80_HARD_GLBL_DSC_CFG_ADDR, reg_val);
- }
-
- if (dev_cap.st_en) {
- /* Buffer Sizes */
- qdma_write_csr_values(dev_hndl,
- QDMA_S80_HARD_C2H_BUF_SZ_0_ADDR, 0,
- QDMA_NUM_C2H_BUFFER_SIZES, buf_sz);
-
- /* Prefetch Configuration */
- reg_val =
- FIELD_SET(C2H_PFCH_CFG_FL_TH_MASK,
- DEFAULT_PFCH_STOP_THRESH) |
- FIELD_SET(C2H_PFCH_CFG_NUM_MASK,
- DEFAULT_PFCH_NUM_ENTRIES_PER_Q) |
- FIELD_SET(C2H_PFCH_CFG_QCNT_MASK,
- DEFAULT_PFCH_MAX_Q_CNT) |
- FIELD_SET(C2H_PFCH_CFG_EVT_QCNT_TH_MASK,
- DEFAULT_C2H_INTR_TIMER_TICK);
- qdma_reg_write(dev_hndl,
- QDMA_S80_HARD_C2H_PFCH_CFG_ADDR, reg_val);
-
- /* C2H interrupt timer tick */
- qdma_reg_write(dev_hndl, QDMA_S80_HARD_C2H_INT_TIMER_TICK_ADDR,
- DEFAULT_C2H_INTR_TIMER_TICK);
-
- /* C2h Completion Coalesce Configuration */
- reg_val =
- FIELD_SET(C2H_WRB_COAL_CFG_TICK_CNT_MASK,
- DEFAULT_CMPT_COAL_TIMER_CNT) |
- FIELD_SET(C2H_WRB_COAL_CFG_TICK_VAL_MASK,
- DEFAULT_CMPT_COAL_TIMER_TICK) |
- FIELD_SET(C2H_WRB_COAL_CFG_MAX_BUF_SZ_MASK,
- DEFAULT_CMPT_COAL_MAX_BUF_SZ);
- qdma_reg_write(dev_hndl,
- QDMA_S80_HARD_C2H_WRB_COAL_CFG_ADDR, reg_val);
-
-#if 0
- /* H2C throttle Configuration*/
- reg_val =
- FIELD_SET(QDMA_H2C_DATA_THRESH_MASK,
- DEFAULT_H2C_THROT_DATA_THRESH) |
- FIELD_SET(QDMA_H2C_REQ_THROT_EN_DATA_MASK,
- DEFAULT_THROT_EN_DATA);
- qdma_reg_write(dev_hndl, QDMA_OFFSET_H2C_REQ_THROT, reg_val);
-#endif
- }
-
- return QDMA_SUCCESS;
-}
-
-/*****************************************************************************/
-/**
- * qdma_s80_hard_queue_pidx_update() - function to update the desc PIDX
- *
- * @dev_hndl: device handle
- * @is_vf: Whether PF or VF
- * @qid: Queue id relative to the PF/VF calling this API
- * @is_c2h: Queue direction. Set 1 for C2H and 0 for H2C
- * @reg_info: data needed for the PIDX register update
- *
- * Return: 0 - success and < 0 - failure
- *****************************************************************************/
-int qdma_s80_hard_queue_pidx_update(void *dev_hndl, uint8_t is_vf, uint16_t qid,
- uint8_t is_c2h, const struct qdma_q_pidx_reg_info *reg_info)
-{
- uint32_t reg_addr = 0;
- uint32_t reg_val = 0;
-
- if (!dev_hndl) {
- qdma_log_error("%s: dev_handle is NULL, err:%d\n",
- __func__, -QDMA_ERR_INV_PARAM);
- return -QDMA_ERR_INV_PARAM;
- }
- if (!reg_info) {
- qdma_log_error("%s: reg_info is NULL, err:%d\n",
- __func__, -QDMA_ERR_INV_PARAM);
- return -QDMA_ERR_INV_PARAM;
- }
-
- if (!is_vf) {
- reg_addr = (is_c2h) ?
- QDMA_S80_HARD_OFFSET_DMAP_SEL_C2H_DSC_PIDX :
- QDMA_S80_HARD_OFFSET_DMAP_SEL_H2C_DSC_PIDX;
- } else {
- reg_addr = (is_c2h) ?
- QDMA_S80_HARD_OFFSET_VF_DMAP_SEL_C2H_DSC_PIDX :
- QDMA_S80_HARD_OFFSET_VF_DMAP_SEL_H2C_DSC_PIDX;
- }
-
- reg_addr += (qid * QDMA_PIDX_STEP);
-
- reg_val = FIELD_SET(QDMA_S80_HARD_DMA_SEL_DESC_PIDX_MASK,
- reg_info->pidx) |
- FIELD_SET(QDMA_S80_HARD_DMA_SEL_IRQ_EN_MASK,
- reg_info->irq_en);
-
- qdma_reg_write(dev_hndl, reg_addr, reg_val);
-
- return QDMA_SUCCESS;
-}
-
-/*****************************************************************************/
-/**
- * qdma_s80_hard_queue_cmpt_cidx_update() - function to update the CMPT
- * CIDX update
- *
- * @dev_hndl: device handle
- * @is_vf: Whether PF or VF
- * @qid: Queue id relative to the PF/VF calling this API
- * @reg_info: data needed for the CIDX register update
- *
- * Return: 0 - success and < 0 - failure
- *****************************************************************************/
-int qdma_s80_hard_queue_cmpt_cidx_update(void *dev_hndl, uint8_t is_vf,
- uint16_t qid, const struct qdma_q_cmpt_cidx_reg_info *reg_info)
-{
- uint32_t reg_addr = (is_vf) ?
- QDMA_S80_HARD_OFFSET_VF_DMAP_SEL_CMPT_CIDX :
- QDMA_S80_HARD_OFFSET_DMAP_SEL_CMPT_CIDX;
- uint32_t reg_val = 0;
-
- if (!dev_hndl) {
- qdma_log_error("%s: dev_handle is NULL, err:%d\n",
- __func__, -QDMA_ERR_INV_PARAM);
- return -QDMA_ERR_INV_PARAM;
- }
-
- if (!reg_info) {
- qdma_log_error("%s: reg_info is NULL, err:%d\n",
- __func__,
- -QDMA_ERR_INV_PARAM);
- return -QDMA_ERR_INV_PARAM;
- }
-
- reg_addr += (qid * QDMA_CMPT_CIDX_STEP);
-
- reg_val =
- FIELD_SET(QDMA_S80_HARD_DMAP_SEL_CMPT_WRB_CIDX_MASK,
- reg_info->wrb_cidx) |
- FIELD_SET(QDMA_S80_HARD_DMAP_SEL_CMPT_CNT_THRESH_MASK,
- reg_info->counter_idx) |
- FIELD_SET(QDMA_S80_HARD_DMAP_SEL_CMPT_TMR_CNT_MASK,
- reg_info->timer_idx) |
- FIELD_SET(QDMA_S80_HARD_DMAP_SEL_CMPT_TRG_MODE_MASK,
- reg_info->trig_mode) |
- FIELD_SET(QDMA_S80_HARD_DMAP_SEL_CMPT_STS_DESC_EN_MASK,
- reg_info->wrb_en) |
- FIELD_SET(QDMA_S80_HARD_DMAP_SEL_CMPT_IRQ_EN_MASK,
- reg_info->irq_en);
-
- qdma_reg_write(dev_hndl, reg_addr, reg_val);
-
- return QDMA_SUCCESS;
-}
-
-/*****************************************************************************/
-/**
- * qdma_s80_hard_queue_intr_cidx_update() - function to update the
- * CMPT CIDX update
- *
- * @dev_hndl: device handle
- * @is_vf: Whether PF or VF
- * @qid: Queue id relative to the PF/VF calling this API
- * @reg_info: data needed for the CIDX register update
- *
- * Return: 0 - success and < 0 - failure
- *****************************************************************************/
-int qdma_s80_hard_queue_intr_cidx_update(void *dev_hndl, uint8_t is_vf,
- uint16_t qid, const struct qdma_intr_cidx_reg_info *reg_info)
-{
- uint32_t reg_addr = (is_vf) ?
- QDMA_S80_HARD_OFFSET_VF_DMAP_SEL_INT_CIDX :
- QDMA_S80_HARD_OFFSET_DMAP_SEL_INT_CIDX;
- uint32_t reg_val = 0;
-
- if (!dev_hndl) {
- qdma_log_error("%s: dev_handle is NULL, err:%d\n",
- __func__, -QDMA_ERR_INV_PARAM);
- return -QDMA_ERR_INV_PARAM;
- }
-
- if (!reg_info) {
- qdma_log_error("%s: reg_info is NULL, err:%d\n",
- __func__, -QDMA_ERR_INV_PARAM);
- return -QDMA_ERR_INV_PARAM;
- }
-
- reg_addr += qid * QDMA_INT_CIDX_STEP;
-
- reg_val =
- FIELD_SET(QDMA_S80_HARD_DMA_SEL_INT_SW_CIDX_MASK,
- reg_info->sw_cidx) |
- FIELD_SET(QDMA_S80_HARD_DMA_SEL_INT_RING_IDX_MASK,
- reg_info->rng_idx);
-
- qdma_reg_write(dev_hndl, reg_addr, reg_val);
-
- return QDMA_SUCCESS;
-}
-
-/*****************************************************************************/
-/**
- * qdma_cmp_get_user_bar() - Function to get the
- * AXI Master Lite(user bar) number
- * @dev_hndl: device handle
- * @is_vf: Whether PF or VF
- * @func_id: function id of the PF
- * @user_bar: pointer to hold the AXI Master Lite(user bar) number
- *
- * Return: 0 - success and < 0 - failure
- *****************************************************************************/
-int qdma_cmp_get_user_bar(void *dev_hndl, uint8_t is_vf,
- uint8_t func_id, uint8_t *user_bar)
-{
- uint8_t bar_found = 0;
- uint8_t bar_idx = 0;
- uint32_t user_bar_id = 0;
- uint32_t reg_addr = 0;
-
- if (!dev_hndl) {
- qdma_log_error("%s: dev_handle is NULL, err:%d\n",
- __func__, -QDMA_ERR_INV_PARAM);
- return -QDMA_ERR_INV_PARAM;
- }
-
- if (!user_bar) {
- qdma_log_error("%s: user_bar is NULL, err:%d\n",
- __func__, -QDMA_ERR_INV_PARAM);
- return -QDMA_ERR_INV_PARAM;
- }
-
- reg_addr = (is_vf) ? QDMA_S80_HARD_GLBL2_PF_VF_BARLITE_EXT_ADDR :
- QDMA_S80_HARD_GLBL2_PF_BARLITE_EXT_ADDR;
-
- if (!is_vf) {
- user_bar_id = qdma_reg_read(dev_hndl, reg_addr);
- user_bar_id = (user_bar_id >> (6 * func_id)) & 0x3F;
- } else {
- *user_bar = QDMA_S80_HARD_VF_USER_BAR_ID;
- return QDMA_SUCCESS;
- }
-
- for (bar_idx = 0; bar_idx < QDMA_BAR_NUM; bar_idx++) {
- if (user_bar_id & (1 << bar_idx)) {
- *user_bar = bar_idx;
- bar_found = 1;
- break;
- }
- }
- if (bar_found == 0) {
- *user_bar = 0;
- qdma_log_error("%s: Bar not found, err:%d\n",
- __func__,
- -QDMA_ERR_HWACC_BAR_NOT_FOUND);
- return -QDMA_ERR_HWACC_BAR_NOT_FOUND;
- }
-
- return QDMA_SUCCESS;
-}
-
-/*****************************************************************************/
-/**
- * qdma_s80_hard_hw_ram_sbe_err_process() -Function to dump SBE err debug info
- *
- * @dev_hndl: device handle
- * @buf: Bufffer for the debug info to be dumped in
- * @buflen: Length of the buffer
- *
- * Return: void
- *****************************************************************************/
-static void qdma_s80_hard_hw_ram_sbe_err_process(void *dev_hndl)
-{
- qdma_s80_hard_dump_reg_info(dev_hndl, QDMA_S80_HARD_RAM_SBE_STS_A_ADDR,
- 1, NULL, 0);
-}
-
-/*****************************************************************************/
-/**
- * qdma_s80_hard_hw_ram_dbe_err_process() -Function to dump DBE err debug info
- *
- * @dev_hndl: device handle
- * @buf: Bufffer for the debug info to be dumped in
- * @buflen: Length of the buffer
- *
- * Return: void
- *****************************************************************************/
-static void qdma_s80_hard_hw_ram_dbe_err_process(void *dev_hndl)
-{
- qdma_s80_hard_dump_reg_info(dev_hndl, QDMA_S80_HARD_RAM_DBE_STS_A_ADDR,
- 1, NULL, 0);
-}
-
-/*****************************************************************************/
-/**
- * qdma_s80_hard_hw_desc_err_process() -Function to dump Descriptor Error info
- *
- * @dev_hndl: device handle
- * @buf: Bufffer for the debug info to be dumped in
- * @buflen: Length of the buffer
- *
- * Return: void
- *****************************************************************************/
-static void qdma_s80_hard_hw_desc_err_process(void *dev_hndl)
-{
- int i = 0;
- uint32_t desc_err_reg_list[] = {
- QDMA_S80_HARD_GLBL_DSC_ERR_STS_ADDR,
- QDMA_S80_HARD_GLBL_DSC_ERR_LOG0_ADDR,
- QDMA_S80_HARD_GLBL_DSC_ERR_LOG1_ADDR,
- QDMA_S80_HARD_GLBL_DSC_DBG_DAT0_ADDR,
- QDMA_S80_HARD_GLBL_DSC_DBG_DAT1_ADDR
- };
- int desc_err_num_regs = sizeof(desc_err_reg_list)/sizeof(uint32_t);
-
- for (i = 0; i < desc_err_num_regs; i++) {
- qdma_s80_hard_dump_reg_info(dev_hndl,
- desc_err_reg_list[i],
- 1, NULL, 0);
- }
-}
-
-/*****************************************************************************/
-/**
- * qdma_s80_hard_hw_trq_err_process() -Function to dump Target Access Err info
- *
- * @dev_hndl: device handle
- * @buf: Bufffer for the debug info to be dumped in
- * @buflen: Length of the buffer
- *
- * Return: void
- *****************************************************************************/
-static void qdma_s80_hard_hw_trq_err_process(void *dev_hndl)
-{
- int i = 0;
- uint32_t trq_err_reg_list[] = {
- QDMA_S80_HARD_GLBL_TRQ_ERR_STS_ADDR,
- QDMA_S80_HARD_GLBL_TRQ_ERR_LOG_ADDR
- };
- int trq_err_reg_num_regs = sizeof(trq_err_reg_list)/sizeof(uint32_t);
-
- for (i = 0; i < trq_err_reg_num_regs; i++) {
- qdma_s80_hard_dump_reg_info(dev_hndl, trq_err_reg_list[i],
- 1, NULL, 0);
- }
-
-
-}
-
-/*****************************************************************************/
-/**
- * qdma_s80_hard_hw_st_h2c_err_process() - Function to dump MM H2C Error info
- *
- * @dev_hndl: device handle
- * @buf: Bufffer for the debug info to be dumped in
- * @buflen: Length of the buffer
- *
- * Return: void
- *****************************************************************************/
-static void qdma_s80_hard_hw_st_h2c_err_process(void *dev_hndl)
-{
- int i = 0;
- uint32_t st_h2c_err_reg_list[] = {
- QDMA_S80_HARD_H2C_ERR_STAT_ADDR,
- QDMA_S80_HARD_H2C_FIRST_ERR_QID_ADDR,
- QDMA_S80_HARD_H2C_DBG_REG0_ADDR,
- QDMA_S80_HARD_H2C_DBG_REG1_ADDR,
- QDMA_S80_HARD_H2C_DBG_REG2_ADDR,
- QDMA_S80_HARD_H2C_DBG_REG3_ADDR,
- QDMA_S80_HARD_H2C_DBG_REG4_ADDR
- };
- int st_h2c_err_num_regs = sizeof(st_h2c_err_reg_list)/sizeof(uint32_t);
-
- for (i = 0; i < st_h2c_err_num_regs; i++) {
- qdma_s80_hard_dump_reg_info(dev_hndl,
- st_h2c_err_reg_list[i],
- 1, NULL, 0);
- }
-}
-
-
-/*****************************************************************************/
-/**
- * qdma_s80_hard_hw_st_c2h_err_process() - Function to dump MM H2C Error info
- *
- * @dev_hndl: device handle
- * @buf: Bufffer for the debug info to be dumped in
- * @buflen: Length of the buffer
- *
- * Return: void
- *****************************************************************************/
-static void qdma_s80_hard_hw_st_c2h_err_process(void *dev_hndl)
-{
- int i = 0;
- uint32_t st_c2h_err_reg_list[] = {
- QDMA_S80_HARD_C2H_ERR_STAT_ADDR,
- QDMA_S80_HARD_C2H_FATAL_ERR_STAT_ADDR,
- QDMA_S80_HARD_C2H_FIRST_ERR_QID_ADDR,
- QDMA_S80_HARD_C2H_STAT_S_AXIS_C2H_ACCEPTED_ADDR,
- QDMA_S80_HARD_C2H_STAT_S_AXIS_WRB_ACCEPTED_ADDR,
- QDMA_S80_HARD_C2H_STAT_DESC_RSP_PKT_ACCEPTED_ADDR,
- QDMA_S80_HARD_C2H_STAT_AXIS_PKG_CMP_ADDR,
- QDMA_S80_HARD_C2H_STAT_DBG_DMA_ENG_0_ADDR,
- QDMA_S80_HARD_C2H_STAT_DBG_DMA_ENG_1_ADDR,
- QDMA_S80_HARD_C2H_STAT_DBG_DMA_ENG_2_ADDR,
- QDMA_S80_HARD_C2H_STAT_DBG_DMA_ENG_3_ADDR,
- QDMA_S80_HARD_C2H_STAT_DESC_RSP_DROP_ACCEPTED_ADDR,
- QDMA_S80_HARD_C2H_STAT_DESC_RSP_ERR_ACCEPTED_ADDR
- };
- int st_c2h_err_num_regs = sizeof(st_c2h_err_reg_list)/sizeof(uint32_t);
-
- for (i = 0; i < st_c2h_err_num_regs; i++) {
- qdma_s80_hard_dump_reg_info(dev_hndl,
- st_c2h_err_reg_list[i],
- 1, NULL, 0);
- }
-}
-
-
-
-/*****************************************************************************/
-/**
- * qdma_s80_hard_hw_get_error_name() - Function to get the error in str format
- *
- * @err_idx: error index
- *
- * Return: string - success and NULL on failure
- *****************************************************************************/
-const char *qdma_s80_hard_hw_get_error_name(uint32_t err_idx)
-{
- if (err_idx >= QDMA_S80_HARD_ERRS_ALL) {
- qdma_log_error("%s: err_idx=%d is invalid, returning NULL\n",
- __func__,
- (enum qdma_s80_hard_error_idx)err_idx);
- return NULL;
- }
-
- return qdma_s80_hard_err_info[
- (enum qdma_s80_hard_error_idx)err_idx].err_name;
-}
-
-/*****************************************************************************/
-/**
- * qdma_s80_hard_hw_error_process() - Function to find the error that got
- * triggered and call the handler qdma_hw_error_handler of that
- * particular error.
- *
- * @dev_hndl: device handle
- *
- * Return: 0 - success and < 0 - failure
- *****************************************************************************/
-int qdma_s80_hard_hw_error_process(void *dev_hndl)
-{
- uint32_t glbl_err_stat = 0, err_stat = 0;
- uint32_t i = 0, j = 0;
- int32_t idx = 0;
- struct qdma_dev_attributes dev_cap;
- uint32_t hw_err_position[QDMA_S80_HARD_TOTAL_LEAF_ERROR_AGGREGATORS] = {
- QDMA_S80_HARD_DSC_ERR_POISON,
- QDMA_S80_HARD_TRQ_ERR_UNMAPPED,
- QDMA_S80_HARD_ST_C2H_ERR_MTY_MISMATCH,
- QDMA_S80_HARD_ST_FATAL_ERR_MTY_MISMATCH,
- QDMA_S80_HARD_ST_H2C_ERR_ZERO_LEN_DESC_ERR,
- QDMA_S80_HARD_SBE_ERR_MI_H2C0_DAT,
- QDMA_S80_HARD_DBE_ERR_MI_H2C0_DAT
- };
-
- if (!dev_hndl) {
- qdma_log_error("%s: dev_handle is NULL, err:%d\n",
- __func__, -QDMA_ERR_INV_PARAM);
- return -QDMA_ERR_INV_PARAM;
- }
-
-
- qdma_s80_hard_get_device_attributes(dev_hndl, &dev_cap);
-
- glbl_err_stat = qdma_reg_read(dev_hndl,
- QDMA_S80_HARD_GLBL_ERR_STAT_ADDR);
- if (!glbl_err_stat)
- return QDMA_HW_ERR_NOT_DETECTED;
-
- qdma_log_info("%s: Global Err Reg(0x%x) = 0x%x\n",
- __func__, QDMA_S80_HARD_GLBL_ERR_STAT_ADDR,
- glbl_err_stat);
-
- for (i = 0; i < QDMA_S80_HARD_TOTAL_LEAF_ERROR_AGGREGATORS; i++) {
- j = hw_err_position[i];
-
- if ((!dev_cap.st_en) &&
- (j == QDMA_S80_HARD_ST_C2H_ERR_MTY_MISMATCH ||
- j == QDMA_S80_HARD_ST_FATAL_ERR_MTY_MISMATCH ||
- j == QDMA_S80_HARD_ST_H2C_ERR_ZERO_LEN_DESC_ERR))
- continue;
-
- err_stat = qdma_reg_read(dev_hndl,
- qdma_s80_hard_err_info[j].stat_reg_addr);
- if (err_stat) {
- qdma_log_info("addr = 0x%08x val = 0x%08x",
- qdma_s80_hard_err_info[j].stat_reg_addr,
- err_stat);
-
- qdma_s80_hard_err_info[j].qdma_s80_hard_hw_err_process(
- dev_hndl);
- for (idx = j;
- idx < all_qdma_s80_hard_hw_errs[i];
- idx++) {
- /* call the platform specific handler */
- if (err_stat &
- qdma_s80_hard_err_info[idx].leaf_err_mask)
- qdma_log_error("%s detected %s\n",
- __func__,
- qdma_s80_hard_hw_get_error_name(
- idx));
- }
- qdma_reg_write(dev_hndl,
- qdma_s80_hard_err_info[j].stat_reg_addr,
- err_stat);
- }
-
- }
-
- /* Write 1 to the global status register to clear the bits */
- qdma_reg_write(dev_hndl,
- QDMA_S80_HARD_GLBL_ERR_STAT_ADDR, glbl_err_stat);
-
- return QDMA_SUCCESS;
-}
-
-/*****************************************************************************/
-/**
- * qdma_hw_error_enable() - Function to enable all or a specific error
- *
- * @dev_hndl: device handle
- * @err_idx: error index
- *
- * Return: 0 - success and < 0 - failure
- *****************************************************************************/
-int qdma_s80_hard_hw_error_enable(void *dev_hndl, uint32_t err_idx)
-{
- uint32_t idx = 0, i = 0;
- uint32_t reg_val = 0;
- struct qdma_dev_attributes dev_cap;
-
- if (!dev_hndl) {
- qdma_log_error("%s: dev_handle is NULL, err:%d\n",
- __func__, -QDMA_ERR_INV_PARAM);
- return -QDMA_ERR_INV_PARAM;
- }
-
- if (err_idx > QDMA_S80_HARD_ERRS_ALL) {
- qdma_log_error("%s: err_idx=%d is invalid, err:%d\n",
- __func__, (enum qdma_s80_hard_error_idx)err_idx,
- -QDMA_ERR_INV_PARAM);
- return -QDMA_ERR_INV_PARAM;
- }
-
- qdma_s80_hard_get_device_attributes(dev_hndl, &dev_cap);
-
- if (err_idx == QDMA_S80_HARD_ERRS_ALL) {
- for (i = 0;
- i < QDMA_S80_HARD_TOTAL_LEAF_ERROR_AGGREGATORS;
- i++) {
-
- idx = all_qdma_s80_hard_hw_errs[i];
-
- /* Don't access streaming registers in
- * MM only bitstreams
- */
- if (!dev_cap.st_en) {
- if (idx == QDMA_S80_HARD_ST_C2H_ERR_ALL ||
- idx == QDMA_S80_HARD_ST_FATAL_ERR_ALL ||
- idx == QDMA_S80_HARD_ST_H2C_ERR_ALL)
- continue;
- }
-
- reg_val = qdma_s80_hard_err_info[idx].leaf_err_mask;
- qdma_reg_write(dev_hndl,
- qdma_s80_hard_err_info[idx].mask_reg_addr,
- reg_val);
-
- reg_val = qdma_reg_read(dev_hndl,
- QDMA_S80_HARD_GLBL_ERR_MASK_ADDR);
- reg_val |= FIELD_SET(
- qdma_s80_hard_err_info[idx].global_err_mask, 1);
- qdma_reg_write(dev_hndl,
- QDMA_S80_HARD_GLBL_ERR_MASK_ADDR,
- reg_val);
- }
-
- } else {
- /* Don't access streaming registers in MM only bitstreams
- * QDMA_C2H_ERR_MTY_MISMATCH to QDMA_H2C_ERR_ALL are all
- * ST errors
- */
- if (!dev_cap.st_en) {
- if (err_idx >= QDMA_S80_HARD_ST_C2H_ERR_MTY_MISMATCH &&
- err_idx <= QDMA_S80_HARD_ST_H2C_ERR_ALL)
- return QDMA_SUCCESS;
- }
-
- reg_val = qdma_reg_read(dev_hndl,
- qdma_s80_hard_err_info[err_idx].mask_reg_addr);
- reg_val |=
- FIELD_SET(qdma_s80_hard_err_info[err_idx].leaf_err_mask,
- 1);
- qdma_reg_write(dev_hndl,
- qdma_s80_hard_err_info[err_idx].mask_reg_addr,
- reg_val);
-
- reg_val = qdma_reg_read(dev_hndl,
- QDMA_S80_HARD_GLBL_ERR_MASK_ADDR);
- reg_val |=
- FIELD_SET(
- qdma_s80_hard_err_info[err_idx].global_err_mask,
- 1);
- qdma_reg_write(dev_hndl,
- QDMA_S80_HARD_GLBL_ERR_MASK_ADDR, reg_val);
- }
-
- return QDMA_SUCCESS;
-}
-
-/*****************************************************************************/
-/**
- * qdma_s80_hard_get_device_attributes() - Function to get the qdma
- * device attributes
- *
- * @dev_hndl: device handle
- * @dev_info: pointer to hold the device info
- *
- * Return: 0 - success and < 0 - failure
- *****************************************************************************/
-int qdma_s80_hard_get_device_attributes(void *dev_hndl,
- struct qdma_dev_attributes *dev_info)
-{
- uint8_t count = 0;
- uint32_t reg_val = 0;
-
- if (!dev_hndl) {
- qdma_log_error("%s: dev_handle is NULL, err:%d\n",
- __func__, -QDMA_ERR_INV_PARAM);
- return -QDMA_ERR_INV_PARAM;
- }
- if (!dev_info) {
- qdma_log_error("%s: dev_info is NULL, err:%d\n",
- __func__, -QDMA_ERR_INV_PARAM);
- return -QDMA_ERR_INV_PARAM;
- }
-
- /* number of PFs */
- reg_val = qdma_reg_read(dev_hndl,
- QDMA_S80_HARD_GLBL2_PF_BARLITE_INT_ADDR);
- if (FIELD_GET(GLBL2_PF_BARLITE_INT_PF0_BAR_MAP_MASK, reg_val))
- count++;
- if (FIELD_GET(GLBL2_PF_BARLITE_INT_PF1_BAR_MAP_MASK, reg_val))
- count++;
- if (FIELD_GET(GLBL2_PF_BARLITE_INT_PF2_BAR_MAP_MASK, reg_val))
- count++;
- if (FIELD_GET(GLBL2_PF_BARLITE_INT_PF3_BAR_MAP_MASK, reg_val))
- count++;
- dev_info->num_pfs = count;
-
- /* Number of Qs */
- reg_val = qdma_reg_read(dev_hndl, QDMA_S80_HARD_GLBL2_CHANNEL_CAP_ADDR);
- dev_info->num_qs = (FIELD_GET(GLBL2_CHANNEL_CAP_MULTIQ_MAX_MASK,
- reg_val));
-
- /* FLR present */
- reg_val = qdma_reg_read(dev_hndl, QDMA_S80_HARD_GLBL2_MISC_CAP_ADDR);
- dev_info->mailbox_en = FIELD_GET(QDMA_GLBL2_MAILBOX_EN_MASK, reg_val);
- dev_info->flr_present = FIELD_GET(QDMA_GLBL2_FLR_PRESENT_MASK, reg_val);
- dev_info->mm_cmpt_en = 0;
-
- /* ST/MM enabled? */
- reg_val = qdma_reg_read(dev_hndl,
- QDMA_S80_HARD_GLBL2_CHANNEL_MDMA_ADDR);
- dev_info->mm_en = (FIELD_GET(GLBL2_CHANNEL_MDMA_C2H_ENG_MASK, reg_val)
- && FIELD_GET(GLBL2_CHANNEL_MDMA_H2C_ENG_MASK, reg_val)) ? 1 : 0;
- dev_info->st_en = (FIELD_GET(GLBL2_CHANNEL_MDMA_C2H_ST_MASK, reg_val)
- && FIELD_GET(GLBL2_CHANNEL_MDMA_H2C_ST_MASK,
- reg_val)) ? 1 : 0;
-
- /* num of mm channels for Versal Hard is 2 */
- dev_info->mm_channel_max = 2;
-
- dev_info->debug_mode = 0;
- dev_info->desc_eng_mode = 0;
- dev_info->qid2vec_ctx = 1;
- dev_info->cmpt_ovf_chk_dis = 0;
- dev_info->mailbox_intr = 0;
- dev_info->sw_desc_64b = 0;
- dev_info->cmpt_desc_64b = 0;
- dev_info->dynamic_bar = 0;
- dev_info->legacy_intr = 0;
- dev_info->cmpt_trig_count_timer = 0;
-
- return QDMA_SUCCESS;
-}
-
-
-/*****************************************************************************/
-/**
- * qdma_s80_hard_credit_context_read() - read credit context
- *
- * @dev_hndl: device handle
- * @c2h : is c2h queue
- * @hw_qid : hardware qid of the queue
- * @ctxt : pointer to the context data
- *
- * Return : 0 - success and < 0 - failure
- *****************************************************************************/
-static int qdma_s80_hard_credit_context_read(void *dev_hndl, uint8_t c2h,
- uint16_t hw_qid,
- struct qdma_descq_credit_ctxt *ctxt)
-{
- int rv = QDMA_SUCCESS;
- uint32_t cr_ctxt[QDMA_S80_HARD_CR_CONTEXT_NUM_WORDS] = {0};
- enum ind_ctxt_cmd_sel sel = c2h ? QDMA_CTXT_SEL_CR_C2H :
- QDMA_CTXT_SEL_CR_H2C;
-
- if (!dev_hndl || !ctxt) {
- qdma_log_error("%s: dev_hndl=%p credit_ctxt=%p, err:%d\n",
- __func__, dev_hndl, ctxt,
- -QDMA_ERR_INV_PARAM);
- return -QDMA_ERR_INV_PARAM;
- }
-
- rv = qdma_s80_hard_indirect_reg_read(dev_hndl, sel, hw_qid,
- QDMA_S80_HARD_CR_CONTEXT_NUM_WORDS, cr_ctxt);
- if (rv < 0)
- return rv;
-
- ctxt->credit = FIELD_GET(CRED_CTXT_DATA_W0_CREDT_MASK,
- cr_ctxt[0]);
-
- qdma_log_debug("%s: credit=%u\n", __func__, ctxt->credit);
-
- return QDMA_SUCCESS;
-}
-
-/*****************************************************************************/
-/**
- * qdma_s80_hard_credit_context_clear() - clear credit context
- *
- * @dev_hndl: device handle
- * @c2h : is c2h queue
- * @hw_qid : hardware qid of the queue
- *
- * Return : 0 - success and < 0 - failure
- *****************************************************************************/
-static int qdma_s80_hard_credit_context_clear(void *dev_hndl, uint8_t c2h,
- uint16_t hw_qid)
-{
- enum ind_ctxt_cmd_sel sel = c2h ? QDMA_CTXT_SEL_CR_C2H :
- QDMA_CTXT_SEL_CR_H2C;
-
- if (!dev_hndl) {
- qdma_log_error("%s: dev_handle is NULL, err:%d\n", __func__,
- -QDMA_ERR_INV_PARAM);
- return -QDMA_ERR_INV_PARAM;
- }
-
- return qdma_s80_hard_indirect_reg_clear(dev_hndl, sel, hw_qid);
-}
-
-/*****************************************************************************/
-/**
- * qdma_s80_hard_credit_context_invalidate() - invalidate credit context
- *
- * @dev_hndl: device handle
- * @c2h : is c2h queue
- * @hw_qid : hardware qid of the queue
- *
- * Return : 0 - success and < 0 - failure
- *****************************************************************************/
-static int qdma_s80_hard_credit_context_invalidate(void *dev_hndl, uint8_t c2h,
- uint16_t hw_qid)
-{
- enum ind_ctxt_cmd_sel sel = c2h ? QDMA_CTXT_SEL_CR_C2H :
- QDMA_CTXT_SEL_CR_H2C;
-
- if (!dev_hndl) {
- qdma_log_error("%s: dev_handle is NULL, err:%d\n", __func__,
- -QDMA_ERR_INV_PARAM);
- return -QDMA_ERR_INV_PARAM;
- }
-
- return qdma_s80_hard_indirect_reg_invalidate(dev_hndl, sel, hw_qid);
-}
-
-/*****************************************************************************/
-/**
- * qdma_s80_hard_credit_ctx_conf() - configure credit context
- *
- * @dev_hndl : device handle
- * @c2h : is c2h queue
- * @hw_qid : hardware qid of the queue
- * @ctxt : pointer to the context data
- * @access_type : HW access type (qdma_hw_access_type enum) value
- * QDMA_HW_ACCESS_WRITE Not supported
- *
- * Return : 0 - success and < 0 - failure
- *****************************************************************************/
-int qdma_s80_hard_credit_ctx_conf(void *dev_hndl, uint8_t c2h, uint16_t hw_qid,
- struct qdma_descq_credit_ctxt *ctxt,
- enum qdma_hw_access_type access_type)
-{
- int rv = QDMA_SUCCESS;
-
- switch (access_type) {
- case QDMA_HW_ACCESS_READ:
- rv = qdma_s80_hard_credit_context_read(dev_hndl, c2h,
- hw_qid, ctxt);
- break;
- case QDMA_HW_ACCESS_CLEAR:
- rv = qdma_s80_hard_credit_context_clear(dev_hndl, c2h, hw_qid);
- break;
- case QDMA_HW_ACCESS_INVALIDATE:
- rv = qdma_s80_hard_credit_context_invalidate(dev_hndl, c2h,
- hw_qid);
- break;
- case QDMA_HW_ACCESS_WRITE:
- default:
- qdma_log_error("%s: Invalid access type=%d, err:%d\n",
- __func__, access_type,
- -QDMA_ERR_INV_PARAM);
- rv = -QDMA_ERR_INV_PARAM;
- break;
- }
-
- return rv;
-}
-
-
-/*****************************************************************************/
-/**
- * qdma_s80_hard_dump_config_regs() - Function to get qdma config register
- * dump in a buffer
- *
- * @dev_hndl: device handle
- * @is_vf: Whether PF or VF
- * @buf : pointer to buffer to be filled
- * @buflen : Length of the buffer
- *
- * Return: Length up-till the buffer is filled -success and < 0 - failure
- *****************************************************************************/
-int qdma_s80_hard_dump_config_regs(void *dev_hndl, uint8_t is_vf,
- char *buf, uint32_t buflen)
-{
- uint32_t i = 0, j = 0;
- struct xreg_info *reg_info;
- uint32_t num_regs = qdma_s80_hard_config_num_regs_get();
- uint32_t len = 0, val = 0;
- int rv = QDMA_SUCCESS;
- char name[DEBGFS_GEN_NAME_SZ] = "";
- struct qdma_dev_attributes dev_cap;
-
- if (!dev_hndl) {
- qdma_log_error("%s: dev_handle is NULL, err:%d\n",
- __func__, -QDMA_ERR_INV_PARAM);
- return -QDMA_ERR_INV_PARAM;
- }
-
- if (buflen < qdma_s80_hard_reg_dump_buf_len()) {
- qdma_log_error("%s: Buffer too small, err:%d\n", __func__,
- -QDMA_ERR_NO_MEM);
- return -QDMA_ERR_NO_MEM;
- }
-
- if (is_vf) {
- qdma_log_error("%s: Wrong API used for VF, err:%d\n",
- __func__,
- -QDMA_ERR_HWACC_FEATURE_NOT_SUPPORTED);
- return -QDMA_ERR_HWACC_FEATURE_NOT_SUPPORTED;
- }
-
- qdma_s80_hard_get_device_attributes(dev_hndl, &dev_cap);
-
- reg_info = qdma_s80_hard_config_regs_get();
-
- for (i = 0; i < num_regs; i++) {
- if ((GET_CAPABILITY_MASK(dev_cap.mm_en, dev_cap.st_en,
- dev_cap.mm_cmpt_en, dev_cap.mailbox_en)
- & reg_info[i].mode) == 0)
- continue;
-
- for (j = 0; j < reg_info[i].repeat; j++) {
- rv = QDMA_SNPRINTF_S(name, DEBGFS_GEN_NAME_SZ,
- DEBGFS_GEN_NAME_SZ,
- "%s_%d", reg_info[i].name, j);
- if ((rv < 0) || (rv > DEBGFS_GEN_NAME_SZ)) {
- qdma_log_error(
- "%d:%s QDMA_SNPRINTF_S() failed, err:%d\n",
- __LINE__, __func__,
- rv);
- return -QDMA_ERR_NO_MEM;
- }
-
- val = qdma_reg_read(dev_hndl,
- (reg_info[i].addr + (j * 4)));
- rv = dump_reg(buf + len, buflen - len,
- (reg_info[i].addr + (j * 4)),
- name, val);
- if (rv < 0) {
- qdma_log_error(
- "%s Buff too small, err:%d\n",
- __func__,
- -QDMA_ERR_NO_MEM);
- return -QDMA_ERR_NO_MEM;
- }
- len += rv;
- }
- }
-
- return len;
-}
-
-/*****************************************************************************/
-/**
- * qdma_dump_s80_hard_queue_context() - Function to get qdma queue context dump
- * in a buffer
- *
- * @dev_hndl: device handle
- * @hw_qid: queue id
- * @buf : pointer to buffer to be filled
- * @buflen : Length of the buffer
- *
- * Return: Length up-till the buffer is filled -success and < 0 - failure
- *****************************************************************************/
-int qdma_s80_hard_dump_queue_context(void *dev_hndl,
- uint8_t st,
- enum qdma_dev_q_type q_type,
- struct qdma_descq_context *ctxt_data,
- char *buf, uint32_t buflen)
-{
- int rv = 0;
- uint32_t req_buflen = 0;
-
- if (!dev_hndl) {
- qdma_log_error("%s: dev_handle is NULL, err:%d\n",
- __func__, -QDMA_ERR_INV_PARAM);
-
- return -QDMA_ERR_INV_PARAM;
- }
-
- if (!ctxt_data) {
- qdma_log_error("%s: ctxt_data is NULL, err:%d\n",
- __func__, -QDMA_ERR_INV_PARAM);
-
- return -QDMA_ERR_INV_PARAM;
- }
-
- if (!buf) {
- qdma_log_error("%s: buf is NULL, err:%d\n",
- __func__, -QDMA_ERR_INV_PARAM);
-
- return -QDMA_ERR_INV_PARAM;
- }
- if (q_type >= QDMA_DEV_Q_TYPE_MAX) {
- qdma_log_error("%s: invalid q_type, err:%d\n",
- __func__, -QDMA_ERR_INV_PARAM);
-
- return -QDMA_ERR_INV_PARAM;
- }
-
- rv = qdma_s80_hard_context_buf_len(st, q_type, &req_buflen);
- if (rv != QDMA_SUCCESS)
- return rv;
-
- if (buflen < req_buflen) {
- qdma_log_error("%s: Too small buffer(%d), reqd(%d), err:%d\n",
- __func__, buflen, req_buflen, -QDMA_ERR_NO_MEM);
- return -QDMA_ERR_NO_MEM;
- }
-
- rv = dump_s80_hard_context(ctxt_data, st, q_type,
- buf, buflen);
-
- return rv;
-}
-
-/*****************************************************************************/
-/**
- * qdma_dump_s80_hard_intr_context() - Function to get qdma interrupt
- * context dump in a buffer
- *
- * @dev_hndl: device handle
- * @hw_qid: queue id
- * @buf : pointer to buffer to be filled
- * @buflen : Length of the buffer
- *
- * Return: Length up-till the buffer is filled -success and < 0 - failure
- *****************************************************************************/
-int qdma_s80_hard_dump_intr_context(void *dev_hndl,
- struct qdma_indirect_intr_ctxt *intr_ctx,
- int ring_index,
- char *buf, uint32_t buflen)
-{
- int rv = 0;
- uint32_t req_buflen = 0;
-
- if (!dev_hndl) {
- qdma_log_error("%s: dev_handle is NULL, err:%d\n",
- __func__, -QDMA_ERR_INV_PARAM);
-
- return -QDMA_ERR_INV_PARAM;
- }
-
- if (!intr_ctx) {
- qdma_log_error("%s: intr_ctx is NULL, err:%d\n",
- __func__, -QDMA_ERR_INV_PARAM);
-
- return -QDMA_ERR_INV_PARAM;
- }
-
- if (!buf) {
- qdma_log_error("%s: buf is NULL, err:%d\n",
- __func__, -QDMA_ERR_INV_PARAM);
- return -QDMA_ERR_INV_PARAM;
- }
- req_buflen = qdma_s80_hard_intr_context_buf_len();
- if (buflen < req_buflen) {
- qdma_log_error("%s: Too small buffer(%d), reqd(%d), err:%d\n",
- __func__, buflen, req_buflen, -QDMA_ERR_NO_MEM);
- return -QDMA_ERR_NO_MEM;
- }
-
- rv = dump_s80_hard_intr_context(intr_ctx, ring_index, buf, buflen);
-
- return rv;
-}
-
-/*****************************************************************************/
-/**
- * qdma_s80_hard_read_dump_queue_context() - Function to read and dump the queue
- * context in a buffer
- *
- * @dev_hndl: device handle
- * @hw_qid: queue id
- * @st: Queue Mode(ST or MM)
- * @q_type: Queue type(H2C/C2H/CMPT)
- * @buf : pointer to buffer to be filled
- * @buflen : Length of the buffer
- *
- * Return: Length up-till the buffer is filled -success and < 0 - failure
- *****************************************************************************/
-int qdma_s80_hard_read_dump_queue_context(void *dev_hndl,
- uint16_t qid_hw,
- uint8_t st,
- enum qdma_dev_q_type q_type,
- char *buf, uint32_t buflen)
-{
- int rv = QDMA_SUCCESS;
- uint32_t req_buflen = 0;
- struct qdma_descq_context context;
-
- if (!dev_hndl) {
- qdma_log_error("%s: dev_handle is NULL, err:%d\n",
- __func__, -QDMA_ERR_INV_PARAM);
-
- return -QDMA_ERR_INV_PARAM;
- }
-
- if (!buf) {
- qdma_log_error("%s: buf is NULL, err:%d\n",
- __func__, -QDMA_ERR_INV_PARAM);
-
- return -QDMA_ERR_INV_PARAM;
- }
-
- if (q_type >= QDMA_DEV_Q_TYPE_CMPT) {
- qdma_log_error("%s: Not supported for q_type, err = %d\n",
- __func__, -QDMA_ERR_INV_PARAM);
-
- return -QDMA_ERR_INV_PARAM;
- }
-
- rv = qdma_s80_hard_context_buf_len(st, q_type, &req_buflen);
-
- if (rv != QDMA_SUCCESS)
- return rv;
-
- if (buflen < req_buflen) {
- qdma_log_error("%s: Too small buffer(%d), reqd(%d), err:%d\n",
- __func__, buflen, req_buflen, -QDMA_ERR_NO_MEM);
- return -QDMA_ERR_NO_MEM;
- }
-
- qdma_memset(&context, 0, sizeof(struct qdma_descq_context));
-
- if (q_type != QDMA_DEV_Q_TYPE_CMPT) {
- rv = qdma_s80_hard_sw_ctx_conf(dev_hndl, (uint8_t)q_type,
- qid_hw, &(context.sw_ctxt),
- QDMA_HW_ACCESS_READ);
- if (rv < 0) {
- qdma_log_error(
- "%s: Failed to read sw context, err = %d",
- __func__, rv);
- return rv;
- }
-
- rv = qdma_s80_hard_hw_ctx_conf(dev_hndl, (uint8_t)q_type,
- qid_hw, &(context.hw_ctxt),
- QDMA_HW_ACCESS_READ);
- if (rv < 0) {
- qdma_log_error(
- "%s: Failed to read hw context, err = %d",
- __func__, rv);
- return rv;
- }
-
- rv = qdma_s80_hard_qid2vec_conf(dev_hndl, (uint8_t)q_type,
- qid_hw, &(context.qid2vec),
- QDMA_HW_ACCESS_READ);
- if (rv < 0) {
- qdma_log_error(
- "%s: Failed to read qid2vec context, err = %d",
- __func__, rv);
- return rv;
- }
-
- rv = qdma_s80_hard_credit_ctx_conf(dev_hndl, (uint8_t)q_type,
- qid_hw, &(context.cr_ctxt),
- QDMA_HW_ACCESS_READ);
- if (rv < 0) {
- qdma_log_error(
- "%s: Failed to read credit context, err = %d",
- __func__, rv);
- return rv;
- }
-
- if (st && (q_type == QDMA_DEV_Q_TYPE_C2H)) {
- rv = qdma_s80_hard_pfetch_ctx_conf(dev_hndl,
- qid_hw,
- &(context.pfetch_ctxt),
- QDMA_HW_ACCESS_READ);
- if (rv < 0) {
- qdma_log_error(
- "%s: Failed to read pftech context, err = %d",
- __func__, rv);
- return rv;
- }
- }
- }
-
- if ((st && (q_type == QDMA_DEV_Q_TYPE_C2H)) ||
- (!st && (q_type == QDMA_DEV_Q_TYPE_CMPT))) {
- rv = qdma_s80_hard_cmpt_ctx_conf(dev_hndl, qid_hw,
- &(context.cmpt_ctxt),
- QDMA_HW_ACCESS_READ);
- if (rv < 0) {
- qdma_log_error(
- "%s: Failed to read cmpt context, err = %d",
- __func__, rv);
- return rv;
- }
- }
-
-
-
- rv = dump_s80_hard_context(&context, st, q_type,
- buf, buflen);
-
- return rv;
-}
-
-/*****************************************************************************/
-/**
- * qdma_s80_hard_init_ctxt_memory() - Initialize the context for all queues
- *
- * @dev_hndl : device handle
- *
- * Return : 0 - success and < 0 - failure
- *****************************************************************************/
-
-int qdma_s80_hard_init_ctxt_memory(void *dev_hndl)
-{
-#ifdef ENABLE_INIT_CTXT_MEMORY
- uint32_t data[QDMA_REG_IND_CTXT_REG_COUNT];
- uint16_t i = 0;
- struct qdma_dev_attributes dev_info;
-
- if (!dev_hndl) {
- qdma_log_error("%s: dev_handle is NULL, err:%d\n",
- __func__, -QDMA_ERR_INV_PARAM);
- return -QDMA_ERR_INV_PARAM;
- }
-
- qdma_memset(data, 0, sizeof(uint32_t) * QDMA_REG_IND_CTXT_REG_COUNT);
- qdma_s80_hard_get_device_attributes(dev_hndl, &dev_info);
- qdma_log_info("%s: clearing the context for all qs",
- __func__);
- for (; i < dev_info.num_qs; i++) {
- int sel = QDMA_CTXT_SEL_SW_C2H;
- int rv;
-
- for (; sel <= QDMA_CTXT_SEL_PFTCH; sel++) {
- /** if the st mode(h2c/c2h) not enabled
- * in the design, then skip the PFTCH
- * and CMPT context setup
- */
- if ((dev_info.st_en == 0) &&
- (sel == QDMA_CTXT_SEL_PFTCH ||
- sel == QDMA_CTXT_SEL_CMPT)) {
- qdma_log_debug("%s: ST context is skipped:",
- __func__);
- qdma_log_debug(" sel = %d", sel);
- continue;
- }
-
- rv = qdma_s80_hard_indirect_reg_clear(dev_hndl,
- (enum ind_ctxt_cmd_sel)sel, i);
- if (rv < 0)
- return rv;
- }
- }
-
- /* fmap */
- for (i = 0; i < dev_info.num_pfs; i++)
- qdma_s80_hard_fmap_clear(dev_hndl, i);
-#else
- if (!dev_hndl) {
- qdma_log_error("%s: dev_handle is NULL, err:%d\n",
- __func__, -QDMA_ERR_INV_PARAM);
- return -QDMA_ERR_INV_PARAM;
- }
-#endif
- return 0;
-}
-
-static int get_reg_entry(uint32_t reg_addr, int *reg_entry)
-{
- uint32_t i = 0;
- struct xreg_info *reg_info;
- uint32_t num_regs = qdma_s80_hard_config_num_regs_get();
-
- reg_info = qdma_s80_hard_config_regs_get();
-
- for (i = 0; (i < num_regs - 1); i++) {
- if (reg_info[i].addr == reg_addr) {
- *reg_entry = i;
- break;
- }
- }
-
- if (i >= num_regs - 1) {
- qdma_log_error("%s: 0x%08x is missing register list, err:%d\n",
- __func__,
- reg_addr,
- -QDMA_ERR_INV_PARAM);
- *reg_entry = -1;
- return -QDMA_ERR_INV_PARAM;
- }
-
- return 0;
-}
-
-/*****************************************************************************/
-/**
- * qdma_s80_hard_dump_config_reg_list() - Dump the registers
- *
- * @dev_hndl: device handle
- * @total_regs : Max registers to read
- * @reg_list : array of reg addr and reg values
- * @buf : pointer to buffer to be filled
- * @buflen : Length of the buffer
- *
- * Return: returns the platform specific error code
- *****************************************************************************/
-int qdma_s80_hard_dump_config_reg_list(void *dev_hndl, uint32_t total_regs,
- struct qdma_reg_data *reg_list, char *buf, uint32_t buflen)
-{
- uint32_t j = 0, len = 0;
- uint32_t reg_count = 0;
- int reg_data_entry;
- int rv = 0;
- char name[DEBGFS_GEN_NAME_SZ] = "";
- struct xreg_info *reg_info = qdma_s80_hard_config_regs_get();
-
- if (!dev_hndl) {
- qdma_log_error("%s: dev_handle is NULL, err:%d\n",
- __func__, -QDMA_ERR_INV_PARAM);
- return -QDMA_ERR_INV_PARAM;
- }
-
- if (!buf) {
- qdma_log_error("%s: buf is NULL, err:%d\n",
- __func__, -QDMA_ERR_INV_PARAM);
- return -QDMA_ERR_INV_PARAM;
- }
-
- for (reg_count = 0;
- (reg_count < total_regs);) {
-
- rv = get_reg_entry(reg_list[reg_count].reg_addr,
- ®_data_entry);
- if (rv < 0) {
- qdma_log_error("%s: register missing in list, err:%d\n",
- __func__,
- -QDMA_ERR_INV_PARAM);
- return rv;
- }
-
- for (j = 0; j < reg_info[reg_data_entry].repeat; j++) {
- rv = QDMA_SNPRINTF_S(name, DEBGFS_GEN_NAME_SZ,
- DEBGFS_GEN_NAME_SZ,
- "%s_%d",
- reg_info[reg_data_entry].name, j);
- if ((rv < 0) || (rv > DEBGFS_GEN_NAME_SZ)) {
- qdma_log_error(
- "%d:%s snprintf failed, err:%d\n",
- __LINE__, __func__,
- rv);
- return -QDMA_ERR_NO_MEM;
- }
- rv = dump_reg(buf + len, buflen - len,
- (reg_info[reg_data_entry].addr + (j * 4)),
- name,
- reg_list[reg_count + j].reg_val);
- if (rv < 0) {
- qdma_log_error(
- "%s Buff too small, err:%d\n",
- __func__,
- -QDMA_ERR_NO_MEM);
- return -QDMA_ERR_NO_MEM;
- }
- len += rv;
- }
- reg_count += j;
- }
-
- return len;
-
-}
-
-
-/*****************************************************************************/
-/**
- * qdma_read_reg_list() - read the register values
- *
- * @dev_hndl: device handle
- * @is_vf: Whether PF or VF
- * @total_regs : Max registers to read
- * @reg_list : array of reg addr and reg values
- *
- * Return: returns the platform specific error code
- *****************************************************************************/
-int qdma_s80_hard_read_reg_list(void *dev_hndl, uint8_t is_vf,
- uint16_t reg_rd_slot,
- uint16_t *total_regs,
- struct qdma_reg_data *reg_list)
-{
- uint16_t reg_count = 0, i = 0, j = 0;
- uint32_t num_regs = qdma_s80_hard_config_num_regs_get();
- struct xreg_info *reg_info = qdma_s80_hard_config_regs_get();
- struct qdma_dev_attributes dev_cap;
- uint32_t reg_start_addr = 0;
- int reg_index = 0;
- int rv = 0;
-
- if (!is_vf) {
- qdma_log_error("%s: not supported for PF, err:%d\n",
- __func__,
- -QDMA_ERR_HWACC_FEATURE_NOT_SUPPORTED);
- return -QDMA_ERR_HWACC_FEATURE_NOT_SUPPORTED;
- }
-
- if (!dev_hndl) {
- qdma_log_error("%s: dev_handle is NULL, err:%d\n",
- __func__, -QDMA_ERR_INV_PARAM);
- return -QDMA_ERR_INV_PARAM;
- }
-
- if (!reg_list) {
- qdma_log_error("%s: reg_list is NULL, err:%d\n",
- __func__, -QDMA_ERR_INV_PARAM);
- return -QDMA_ERR_INV_PARAM;
- }
-
- qdma_s80_hard_get_device_attributes(dev_hndl, &dev_cap);
-
- switch (reg_rd_slot) {
- case QDMA_REG_READ_GROUP_1:
- reg_start_addr = QDMA_S80_REG_GROUP_1_START_ADDR;
- break;
- case QDMA_REG_READ_GROUP_2:
- reg_start_addr = QDMA_S80_REG_GROUP_2_START_ADDR;
- break;
- case QDMA_REG_READ_GROUP_3:
- reg_start_addr = QDMA_S80_REG_GROUP_3_START_ADDR;
- break;
- case QDMA_REG_READ_GROUP_4:
- reg_start_addr = QDMA_S80_REG_GROUP_4_START_ADDR;
- break;
- default:
- qdma_log_error("%s: Invalid slot received\n",
- __func__);
- return -QDMA_ERR_INV_PARAM;
- }
-
- rv = get_reg_entry(reg_start_addr, ®_index);
- if (rv < 0) {
- qdma_log_error("%s: register missing in list, err:%d\n",
- __func__,
- -QDMA_ERR_INV_PARAM);
- return rv;
- }
-
- for (i = 0, reg_count = 0;
- ((i < num_regs - 1 - reg_index) &&
- (reg_count < QDMA_MAX_REGISTER_DUMP)); i++) {
-
- if (((GET_CAPABILITY_MASK(dev_cap.mm_en, dev_cap.st_en,
- dev_cap.mm_cmpt_en, dev_cap.mailbox_en)
- & reg_info[i].mode) == 0) ||
- (reg_info[i].read_type == QDMA_REG_READ_PF_ONLY))
- continue;
-
- for (j = 0; j < reg_info[i].repeat &&
- (reg_count < QDMA_MAX_REGISTER_DUMP);
- j++) {
- reg_list[reg_count].reg_addr =
- (reg_info[i].addr + (j * 4));
- reg_list[reg_count].reg_val =
- qdma_reg_read(dev_hndl,
- reg_list[reg_count].reg_addr);
- reg_count++;
- }
- }
-
- *total_regs = reg_count;
- return rv;
-}
-
-/*****************************************************************************/
-/**
- * qdma_s80_hard_write_global_ring_sizes() - set the global ring size array
- *
- * @dev_hndl: device handle
- * @index: Index from where the values needs to written
- * @count: number of entries to be written
- * @glbl_rng_sz: pointer to the array having the values to write
- *
- * (index + count) shall not be more than 16
- *
- * Return: 0 - success and < 0 - failure
- *****************************************************************************/
-static int qdma_s80_hard_write_global_ring_sizes(void *dev_hndl, uint8_t index,
- uint8_t count, const uint32_t *glbl_rng_sz)
-{
- if (!dev_hndl || !glbl_rng_sz || !count) {
- qdma_log_error("%s: dev_hndl=%p glbl_rng_sz=%p, err:%d\n",
- __func__, dev_hndl, glbl_rng_sz,
- -QDMA_ERR_INV_PARAM);
- return -QDMA_ERR_INV_PARAM;
- }
-
- if ((index + count) > QDMA_NUM_RING_SIZES) {
- qdma_log_error("%s: index=%u count=%u > %d, err:%d\n",
- __func__, index, count,
- QDMA_NUM_RING_SIZES,
- -QDMA_ERR_INV_PARAM);
- return -QDMA_ERR_INV_PARAM;
- }
-
- qdma_write_csr_values(dev_hndl,
- QDMA_S80_HARD_GLBL_RNG_SZ_1_ADDR, index, count,
- glbl_rng_sz);
-
- return QDMA_SUCCESS;
-}
-
-/*****************************************************************************/
-/**
- * qdma_s80_hard_read_global_ring_sizes() - function to get the
- * global rng_sz array
- *
- * @dev_hndl: device handle
- * @index: Index from where the values needs to read
- * @count: number of entries to be read
- * @glbl_rng_sz: pointer to array to hold the values read
- *
- * (index + count) shall not be more than 16
- *
- * Return: 0 - success and < 0 - failure
- *****************************************************************************/
-static int qdma_s80_hard_read_global_ring_sizes(void *dev_hndl, uint8_t index,
- uint8_t count, uint32_t *glbl_rng_sz)
-{
- if (!dev_hndl || !glbl_rng_sz || !count) {
- qdma_log_error("%s: dev_hndl=%p glbl_rng_sz=%p, err:%d\n",
- __func__, dev_hndl, glbl_rng_sz,
- -QDMA_ERR_INV_PARAM);
- return -QDMA_ERR_INV_PARAM;
- }
-
- if ((index + count) > QDMA_NUM_RING_SIZES) {
- qdma_log_error("%s: index=%u count=%u > %d, err:%d\n",
- __func__, index, count,
- QDMA_NUM_C2H_BUFFER_SIZES,
- -QDMA_ERR_INV_PARAM);
- return -QDMA_ERR_INV_PARAM;
- }
-
- qdma_read_csr_values(dev_hndl,
- QDMA_S80_HARD_GLBL_RNG_SZ_1_ADDR, index, count,
- glbl_rng_sz);
-
- return QDMA_SUCCESS;
-}
-
-/*****************************************************************************/
-/**
- * qdma_s80_hard_write_global_timer_count() - function to set the timer values
- *
- * @dev_hndl: device handle
- * @glbl_tmr_cnt: pointer to the array having the values to write
- * @index: Index from where the values needs to written
- * @count: number of entries to be written
- *
- * (index + count) shall not be more than 16
- *
- * Return: 0 - success and < 0 - failure
- *****************************************************************************/
-static int qdma_s80_hard_write_global_timer_count(void *dev_hndl, uint8_t index,
- uint8_t count, const uint32_t *glbl_tmr_cnt)
-{
- struct qdma_dev_attributes dev_cap;
-
- if (!dev_hndl || !glbl_tmr_cnt || !count) {
- qdma_log_error("%s: dev_hndl=%p glbl_tmr_cnt=%p, err:%d\n",
- __func__, dev_hndl, glbl_tmr_cnt,
- -QDMA_ERR_INV_PARAM);
- return -QDMA_ERR_INV_PARAM;
- }
-
- if ((index + count) > QDMA_NUM_C2H_TIMERS) {
- qdma_log_error("%s: index=%u count=%u > %d, err:%d\n",
- __func__, index, count,
- QDMA_NUM_C2H_TIMERS,
- -QDMA_ERR_INV_PARAM);
- return -QDMA_ERR_INV_PARAM;
- }
-
- qdma_s80_hard_get_device_attributes(dev_hndl, &dev_cap);
-
- if (dev_cap.st_en || dev_cap.mm_cmpt_en)
- qdma_write_csr_values(dev_hndl,
- QDMA_S80_HARD_C2H_TIMER_CNT_1_ADDR,
- index, count, glbl_tmr_cnt);
- else {
- qdma_log_error("%s: ST or MM cmpt not supported, err:%d\n",
- __func__,
- -QDMA_ERR_HWACC_FEATURE_NOT_SUPPORTED);
- return -QDMA_ERR_HWACC_FEATURE_NOT_SUPPORTED;
- }
-
- return QDMA_SUCCESS;
-}
-
-/*****************************************************************************/
-/**
- * qdma_s80_hard_read_global_timer_count() - function to get the timer values
- *
- * @dev_hndl: device handle
- * @index: Index from where the values needs to read
- * @count: number of entries to be read
- * @glbl_tmr_cnt: pointer to array to hold the values read
- *
- * (index + count) shall not be more than 16
- *
- * Return: 0 - success and < 0 - failure
- *****************************************************************************/
-static int qdma_s80_hard_read_global_timer_count(void *dev_hndl, uint8_t index,
- uint8_t count, uint32_t *glbl_tmr_cnt)
-{
- struct qdma_dev_attributes dev_cap;
-
- if (!dev_hndl || !glbl_tmr_cnt || !count) {
- qdma_log_error("%s: dev_hndl=%p glbl_tmr_cnt=%p, err:%d\n",
- __func__, dev_hndl, glbl_tmr_cnt,
- -QDMA_ERR_INV_PARAM);
- return -QDMA_ERR_INV_PARAM;
- }
-
- if ((index + count) > QDMA_NUM_C2H_TIMERS) {
- qdma_log_error("%s: index=%u count=%u > %d, err:%d\n",
- __func__, index, count,
- QDMA_NUM_C2H_TIMERS,
- -QDMA_ERR_INV_PARAM);
- return -QDMA_ERR_INV_PARAM;
- }
-
- qdma_s80_hard_get_device_attributes(dev_hndl, &dev_cap);
-
- if (dev_cap.st_en || dev_cap.mm_cmpt_en)
- qdma_read_csr_values(dev_hndl,
- QDMA_S80_HARD_C2H_TIMER_CNT_1_ADDR, index,
- count, glbl_tmr_cnt);
- else {
- qdma_log_error("%s: ST or MM cmpt not supported, err:%d\n",
- __func__,
- -QDMA_ERR_HWACC_FEATURE_NOT_SUPPORTED);
- return -QDMA_ERR_HWACC_FEATURE_NOT_SUPPORTED;
- }
-
- return QDMA_SUCCESS;
-}
-
-/*****************************************************************************/
-/**
- * qdma_s80_hard_write_global_counter_threshold() - function to set the counter
- * threshold values
- *
- * @dev_hndl: device handle
- * @index: Index from where the values needs to written
- * @count: number of entries to be written
- * @glbl_cnt_th: pointer to the array having the values to write
- *
- * (index + count) shall not be more than 16
- *
- * Return: 0 - success and < 0 - failure
- *****************************************************************************/
-static int qdma_s80_hard_write_global_counter_threshold(void *dev_hndl,
- uint8_t index,
- uint8_t count, const uint32_t *glbl_cnt_th)
-{
- struct qdma_dev_attributes dev_cap;
-
- if (!dev_hndl || !glbl_cnt_th || !count) {
- qdma_log_error("%s: dev_hndl=%p glbl_cnt_th=%p, err:%d\n",
- __func__, dev_hndl, glbl_cnt_th,
- -QDMA_ERR_INV_PARAM);
- return -QDMA_ERR_INV_PARAM;
- }
-
- if ((index + count) > QDMA_NUM_C2H_COUNTERS) {
- qdma_log_error("%s: index=%u count=%u > %d, err:%d\n",
- __func__, index, count,
- QDMA_NUM_C2H_BUFFER_SIZES,
- -QDMA_ERR_INV_PARAM);
- return -QDMA_ERR_INV_PARAM;
- }
-
- qdma_s80_hard_get_device_attributes(dev_hndl, &dev_cap);
-
- if (dev_cap.st_en || dev_cap.mm_cmpt_en)
- qdma_write_csr_values(dev_hndl,
- QDMA_S80_HARD_C2H_CNT_TH_1_ADDR, index,
- count, glbl_cnt_th);
- else {
- qdma_log_error("%s: ST or MM cmpt not supported, err:%d\n",
- __func__,
- -QDMA_ERR_HWACC_FEATURE_NOT_SUPPORTED);
- return -QDMA_ERR_HWACC_FEATURE_NOT_SUPPORTED;
- }
-
- return QDMA_SUCCESS;
-}
-
-/*****************************************************************************/
-/**
- * qdma_s80_hard_read_global_counter_threshold() - get the counter
- * threshold values
- *
- * @dev_hndl: device handle
- * @index: Index from where the values needs to read
- * @count: number of entries to be read
- * @glbl_cnt_th: pointer to array to hold the values read
- *
- * (index + count) shall not be more than 16
- *
- * Return: 0 - success and < 0 - failure
- *****************************************************************************/
-static int qdma_s80_hard_read_global_counter_threshold(void *dev_hndl,
- uint8_t index,
- uint8_t count, uint32_t *glbl_cnt_th)
-{
- struct qdma_dev_attributes dev_cap;
-
- if (!dev_hndl || !glbl_cnt_th || !count) {
- qdma_log_error("%s: dev_hndl=%p glbl_cnt_th=%p, err:%d\n",
- __func__, dev_hndl, glbl_cnt_th,
- -QDMA_ERR_INV_PARAM);
- return -QDMA_ERR_INV_PARAM;
- }
-
- if ((index + count) > QDMA_NUM_C2H_COUNTERS) {
- qdma_log_error("%s: index=%u count=%u > %d, err:%d\n",
- __func__, index, count,
- QDMA_NUM_C2H_COUNTERS,
- -QDMA_ERR_INV_PARAM);
- return -QDMA_ERR_INV_PARAM;
- }
-
- qdma_s80_hard_get_device_attributes(dev_hndl, &dev_cap);
-
- if (dev_cap.st_en || dev_cap.mm_cmpt_en)
- qdma_read_csr_values(dev_hndl,
- QDMA_S80_HARD_C2H_CNT_TH_1_ADDR, index,
- count, glbl_cnt_th);
- else {
- qdma_log_error("%s: ST or MM cmpt not supported, err:%d\n",
- __func__, -QDMA_ERR_HWACC_FEATURE_NOT_SUPPORTED);
- return -QDMA_ERR_HWACC_FEATURE_NOT_SUPPORTED;
- }
-
- return QDMA_SUCCESS;
-}
-
-/*****************************************************************************/
-/**
- * qdma_s80_hard_write_global_buffer_sizes() - function to set the buffer sizes
- *
- * @dev_hndl: device handle
- * @index: Index from where the values needs to written
- * @count: number of entries to be written
- * @glbl_buf_sz: pointer to the array having the values to write
- *
- * (index + count) shall not be more than 16
- *
- * Return: 0 - success and < 0 - failure
- *****************************************************************************/
-static int qdma_s80_hard_write_global_buffer_sizes(void *dev_hndl,
- uint8_t index,
- uint8_t count, const uint32_t *glbl_buf_sz)
-{
- struct qdma_dev_attributes dev_cap;
-
- if (!dev_hndl || !glbl_buf_sz || !count) {
- qdma_log_error("%s: dev_hndl=%p glbl_buf_sz=%p, err:%d\n",
- __func__, dev_hndl, glbl_buf_sz,
- -QDMA_ERR_INV_PARAM);
- return -QDMA_ERR_INV_PARAM;
- }
-
- if ((index + count) > QDMA_NUM_C2H_BUFFER_SIZES) {
- qdma_log_error("%s: index=%u count=%u > %d, err:%d\n",
- __func__, index, count,
- QDMA_NUM_C2H_BUFFER_SIZES,
- -QDMA_ERR_INV_PARAM);
- return -QDMA_ERR_INV_PARAM;
- }
-
- qdma_s80_hard_get_device_attributes(dev_hndl, &dev_cap);
-
- if (dev_cap.st_en)
- qdma_write_csr_values(dev_hndl,
- QDMA_S80_HARD_C2H_BUF_SZ_0_ADDR, index,
- count, glbl_buf_sz);
- else {
- qdma_log_error("%s: ST not supported, err:%d\n",
- __func__,
- -QDMA_ERR_HWACC_FEATURE_NOT_SUPPORTED);
- return -QDMA_ERR_HWACC_FEATURE_NOT_SUPPORTED;
- }
-
- return QDMA_SUCCESS;
-}
-
-/*****************************************************************************/
-/**
- * qdma_s80_hard_read_global_buffer_sizes() - function to get the buffer sizes
- *
- * @dev_hndl: device handle
- * @index: Index from where the values needs to read
- * @count: number of entries to be read
- * @glbl_buf_sz: pointer to array to hold the values read
- *
- * (index + count) shall not be more than 16
- *
- * Return: 0 - success and < 0 - failure
- *****************************************************************************/
-static int qdma_s80_hard_read_global_buffer_sizes(void *dev_hndl, uint8_t index,
- uint8_t count, uint32_t *glbl_buf_sz)
-{
- struct qdma_dev_attributes dev_cap;
-
- if (!dev_hndl || !glbl_buf_sz || !count) {
- qdma_log_error("%s: dev_hndl=%p glbl_buf_sz=%p, err:%d\n",
- __func__, dev_hndl, glbl_buf_sz,
- -QDMA_ERR_INV_PARAM);
- return -QDMA_ERR_INV_PARAM;
- }
-
- if ((index + count) > QDMA_NUM_C2H_BUFFER_SIZES) {
- qdma_log_error("%s: index=%u count=%u > %d, err:%d\n",
- __func__, index, count,
- QDMA_NUM_C2H_BUFFER_SIZES,
- -QDMA_ERR_INV_PARAM);
- return -QDMA_ERR_INV_PARAM;
- }
-
- qdma_s80_hard_get_device_attributes(dev_hndl, &dev_cap);
-
- if (dev_cap.st_en)
- qdma_read_csr_values(dev_hndl,
- QDMA_S80_HARD_C2H_BUF_SZ_0_ADDR, index,
- count, glbl_buf_sz);
- else {
- qdma_log_error("%s: ST is not supported, err:%d\n",
- __func__,
- -QDMA_ERR_HWACC_FEATURE_NOT_SUPPORTED);
- return -QDMA_ERR_HWACC_FEATURE_NOT_SUPPORTED;
- }
-
- return QDMA_SUCCESS;
-}
-
-/*****************************************************************************/
-/**
- * qdma_s80_hard_global_csr_conf() - function to configure global csr
- *
- * @dev_hndl: device handle
- * @index: Index from where the values needs to read
- * @count: number of entries to be read
- * @csr_val: uint32_t pointer to csr value
- * @csr_type: Type of the CSR (qdma_global_csr_type enum) to configure
- * @access_type HW access type (qdma_hw_access_type enum) value
- * QDMA_HW_ACCESS_CLEAR - Not supported
- * QDMA_HW_ACCESS_INVALIDATE - Not supported
- *
- * (index + count) shall not be more than 16
- *
- * Return: 0 - success and < 0 - failure
- *****************************************************************************/
-int qdma_s80_hard_global_csr_conf(void *dev_hndl, uint8_t index, uint8_t count,
- uint32_t *csr_val,
- enum qdma_global_csr_type csr_type,
- enum qdma_hw_access_type access_type)
-{
- int rv = QDMA_SUCCESS;
-
- switch (csr_type) {
- case QDMA_CSR_RING_SZ:
- switch (access_type) {
- case QDMA_HW_ACCESS_READ:
- rv = qdma_s80_hard_read_global_ring_sizes(
- dev_hndl,
- index,
- count,
- csr_val);
- break;
- case QDMA_HW_ACCESS_WRITE:
- rv = qdma_s80_hard_write_global_ring_sizes(
- dev_hndl,
- index,
- count,
- csr_val);
- break;
- default:
- qdma_log_error("%s: access_type(%d) invalid, err:%d\n",
- __func__,
- access_type,
- -QDMA_ERR_INV_PARAM);
- rv = -QDMA_ERR_INV_PARAM;
- break;
- }
- break;
- case QDMA_CSR_TIMER_CNT:
- switch (access_type) {
- case QDMA_HW_ACCESS_READ:
- rv = qdma_s80_hard_read_global_timer_count(
- dev_hndl,
- index,
- count,
- csr_val);
- break;
- case QDMA_HW_ACCESS_WRITE:
- rv = qdma_s80_hard_write_global_timer_count(
- dev_hndl,
- index,
- count,
- csr_val);
- break;
- default:
- qdma_log_error("%s: access_type(%d) invalid, err:%d\n",
- __func__,
- access_type,
- -QDMA_ERR_INV_PARAM);
- rv = -QDMA_ERR_INV_PARAM;
- break;
- }
- break;
- case QDMA_CSR_CNT_TH:
- switch (access_type) {
- case QDMA_HW_ACCESS_READ:
- rv =
- qdma_s80_hard_read_global_counter_threshold(
- dev_hndl,
- index,
- count,
- csr_val);
- break;
- case QDMA_HW_ACCESS_WRITE:
- rv =
- qdma_s80_hard_write_global_counter_threshold(
- dev_hndl,
- index,
- count,
- csr_val);
- break;
- default:
- qdma_log_error("%s: access_type(%d) invalid, err:%d\n",
- __func__,
- access_type,
- -QDMA_ERR_INV_PARAM);
- rv = -QDMA_ERR_INV_PARAM;
- break;
- }
- break;
- case QDMA_CSR_BUF_SZ:
- switch (access_type) {
- case QDMA_HW_ACCESS_READ:
- rv =
- qdma_s80_hard_read_global_buffer_sizes(dev_hndl,
- index,
- count,
- csr_val);
- break;
- case QDMA_HW_ACCESS_WRITE:
- rv =
- qdma_s80_hard_write_global_buffer_sizes(dev_hndl,
- index,
- count,
- csr_val);
- break;
- default:
- qdma_log_error("%s: access_type(%d) invalid, err:%d\n",
- __func__,
- access_type,
- -QDMA_ERR_INV_PARAM);
- rv = -QDMA_ERR_INV_PARAM;
- break;
- }
- break;
- default:
- qdma_log_error("%s: csr_type(%d) invalid, err:%d\n",
- __func__,
- csr_type,
- -QDMA_ERR_INV_PARAM);
- rv = -QDMA_ERR_INV_PARAM;
- break;
- }
-
- return rv;
-}
-
-/*****************************************************************************/
-/**
- * qdma_s80_hard_global_writeback_interval_write() - function to set the
- * writeback interval
- *
- * @dev_hndl device handle
- * @wb_int: Writeback Interval
- *
- * Return: 0 - success and < 0 - failure
- *****************************************************************************/
-static int qdma_s80_hard_global_writeback_interval_write(void *dev_hndl,
- enum qdma_wrb_interval wb_int)
-{
- uint32_t reg_val;
- struct qdma_dev_attributes dev_cap;
-
- if (!dev_hndl) {
- qdma_log_error("%s: dev_handle is NULL, err:%d\n", __func__,
- -QDMA_ERR_INV_PARAM);
- return -QDMA_ERR_INV_PARAM;
- }
-
- if (wb_int >= QDMA_NUM_WRB_INTERVALS) {
- qdma_log_error("%s: wb_int=%d is invalid, err:%d\n",
- __func__, wb_int,
- -QDMA_ERR_INV_PARAM);
- return -QDMA_ERR_INV_PARAM;
- }
-
- qdma_s80_hard_get_device_attributes(dev_hndl, &dev_cap);
-
- if (dev_cap.st_en || dev_cap.mm_cmpt_en) {
- reg_val = qdma_reg_read(dev_hndl,
- QDMA_S80_HARD_GLBL_DSC_CFG_ADDR);
- reg_val |= FIELD_SET(GLBL_DSC_CFG_WB_ACC_INT_MASK, wb_int);
-
- qdma_reg_write(dev_hndl,
- QDMA_S80_HARD_GLBL_DSC_CFG_ADDR, reg_val);
- } else {
- qdma_log_error("%s: ST or MM cmpt not supported, err:%d\n",
- __func__, -QDMA_ERR_HWACC_FEATURE_NOT_SUPPORTED);
- return -QDMA_ERR_HWACC_FEATURE_NOT_SUPPORTED;
- }
-
- return QDMA_SUCCESS;
-}
-
-/*****************************************************************************/
-/**
- * qdma_s80_hard_global_writeback_interval_read() - function to get the
- * writeback interval
- *
- * @dev_hndl: device handle
- * @wb_int: pointer to the data to hold Writeback Interval
- *
- * Return: 0 - success and < 0 - failure
- *****************************************************************************/
-static int qdma_s80_hard_global_writeback_interval_read(void *dev_hndl,
- enum qdma_wrb_interval *wb_int)
-{
- uint32_t reg_val;
- struct qdma_dev_attributes dev_cap;
-
- if (!dev_hndl) {
- qdma_log_error("%s: dev_handle is NULL, err:%d\n", __func__,
- -QDMA_ERR_INV_PARAM);
- return -QDMA_ERR_INV_PARAM;
- }
-
- if (!wb_int) {
- qdma_log_error("%s: wb_int is NULL, err:%d\n", __func__,
- -QDMA_ERR_INV_PARAM);
- return -QDMA_ERR_INV_PARAM;
- }
-
- qdma_s80_hard_get_device_attributes(dev_hndl, &dev_cap);
-
- if (dev_cap.st_en || dev_cap.mm_cmpt_en) {
- reg_val = qdma_reg_read(dev_hndl,
- QDMA_S80_HARD_GLBL_DSC_CFG_ADDR);
- *wb_int = (enum qdma_wrb_interval)FIELD_GET(
- GLBL_DSC_CFG_WB_ACC_INT_MASK, reg_val);
- } else {
- qdma_log_error("%s: ST or MM cmpt not supported, err:%d\n",
- __func__, -QDMA_ERR_HWACC_FEATURE_NOT_SUPPORTED);
- return -QDMA_ERR_HWACC_FEATURE_NOT_SUPPORTED;
- }
-
- return QDMA_SUCCESS;
-}
-
-/*****************************************************************************/
-/**
- * qdma_s80_hard_global_writeback_interval_conf() - function to configure
- * the writeback interval
- *
- * @dev_hndl: device handle
- * @wb_int: pointer to the data to hold Writeback Interval
- * @access_type HW access type (qdma_hw_access_type enum) value
- * QDMA_HW_ACCESS_CLEAR - Not supported
- * QDMA_HW_ACCESS_INVALIDATE - Not supported
- *
- * Return: 0 - success and < 0 - failure
- *****************************************************************************/
-int qdma_s80_hard_global_writeback_interval_conf(void *dev_hndl,
- enum qdma_wrb_interval *wb_int,
- enum qdma_hw_access_type access_type)
-{
- int rv = QDMA_SUCCESS;
-
- switch (access_type) {
- case QDMA_HW_ACCESS_READ:
- rv =
- qdma_s80_hard_global_writeback_interval_read(dev_hndl, wb_int);
- break;
- case QDMA_HW_ACCESS_WRITE:
- rv =
- qdma_s80_hard_global_writeback_interval_write(dev_hndl,
- *wb_int);
- break;
- case QDMA_HW_ACCESS_CLEAR:
- case QDMA_HW_ACCESS_INVALIDATE:
- default:
- qdma_log_error("%s: access_type(%d) invalid, err:%d\n",
- __func__,
- access_type,
- -QDMA_ERR_INV_PARAM);
- rv = -QDMA_ERR_INV_PARAM;
- break;
- }
-
- return rv;
-}
-
-
-/*****************************************************************************/
-/**
- * qdma_s80_hard_mm_channel_conf() - Function to enable/disable the MM channel
- *
- * @dev_hndl: device handle
- * @channel: MM channel number
- * @is_c2h: Queue direction. Set 1 for C2H and 0 for H2C
- * @enable: Enable or disable MM channel
- *
- * Presently, we have only 1 MM channel
- *
- * Return: 0 - success and < 0 - failure
- *****************************************************************************/
-int qdma_s80_hard_mm_channel_conf(void *dev_hndl, uint8_t channel,
- uint8_t is_c2h,
- uint8_t enable)
-{
- uint32_t reg_addr = (is_c2h) ? QDMA_S80_HARD_C2H_CHANNEL_CTL_ADDR :
- QDMA_S80_HARD_H2C_CHANNEL_CTL_ADDR;
- struct qdma_dev_attributes dev_cap;
-
- if (!dev_hndl) {
- qdma_log_error("%s: dev_handle is NULL, err:%d\n",
- __func__, -QDMA_ERR_INV_PARAM);
- return -QDMA_ERR_INV_PARAM;
- }
-
- qdma_s80_hard_get_device_attributes(dev_hndl, &dev_cap);
-
- if (dev_cap.mm_en) {
- qdma_reg_write(dev_hndl,
- reg_addr + (channel * QDMA_MM_CONTROL_STEP),
- enable);
- }
-
- return QDMA_SUCCESS;
-}
-
-int qdma_s80_hard_dump_reg_info(void *dev_hndl, uint32_t reg_addr,
- uint32_t num_regs, char *buf, uint32_t buflen)
-{
- uint32_t total_num_regs = qdma_s80_hard_config_num_regs_get();
- struct xreg_info *config_regs = qdma_s80_hard_config_regs_get();
- const char *bitfield_name;
- uint32_t i = 0, num_regs_idx = 0, k = 0, j = 0,
- bitfield = 0, lsb = 0, msb = 31;
- int rv = 0;
- uint32_t reg_val;
- uint32_t data_len = 0;
-
- if (!dev_hndl) {
- qdma_log_error("%s: dev_handle is NULL, err:%d\n",
- __func__, -QDMA_ERR_INV_PARAM);
- return -QDMA_ERR_INV_PARAM;
- }
-
- for (i = 0; i < total_num_regs; i++) {
- if (reg_addr == config_regs[i].addr) {
- j = i;
- break;
- }
- }
-
- if (i == total_num_regs) {
- qdma_log_error("%s: Register not found err:%d\n",
- __func__, -QDMA_ERR_INV_PARAM);
- if (buf)
- QDMA_SNPRINTF_S(buf, buflen,
- DEBGFS_LINE_SZ,
- "Register not found 0x%x\n", reg_addr);
- return -QDMA_ERR_INV_PARAM;
- }
-
- num_regs_idx = (j + num_regs < total_num_regs) ?
- (j + num_regs) : total_num_regs;
-
- for (; j < num_regs_idx ; j++) {
- reg_val = qdma_reg_read(dev_hndl,
- config_regs[j].addr);
-
- if (buf) {
- rv = QDMA_SNPRINTF_S(buf, buflen,
- DEBGFS_LINE_SZ,
- "\n%-40s 0x%-7x %-#10x %-10d\n",
- config_regs[j].name,
- config_regs[j].addr,
- reg_val, reg_val);
- if ((rv < 0) || (rv > DEBGFS_LINE_SZ)) {
- qdma_log_error(
- "%s: Insufficient buffer, err:%d\n",
- __func__, -QDMA_ERR_NO_MEM);
- return -QDMA_ERR_NO_MEM;
- }
- buf += rv;
- data_len += rv;
- buflen -= rv;
- } else
- qdma_log_info("%-40s 0x%-7x %-#10x %-10d\n",
- config_regs[j].name,
- config_regs[j].addr,
- reg_val, reg_val);
-
-
- for (k = 0;
- k < config_regs[j].num_bitfields; k++) {
-
- bitfield =
- config_regs[j].bitfields[k].field_mask;
- bitfield_name =
- config_regs[i].bitfields[k].field_name;
- lsb = 0;
- msb = 31;
-
- while (!(BIT(lsb) & bitfield))
- lsb++;
-
- while (!(BIT(msb) & bitfield))
- msb--;
-
- if (msb != lsb) {
- if (buf) {
- rv = QDMA_SNPRINTF_S(buf, buflen,
- DEBGFS_LINE_SZ,
- "%-40s [%2u,%2u] %#-10x\n",
- bitfield_name,
- msb, lsb,
- (reg_val & bitfield) >>
- lsb);
- if ((rv < 0) || (rv > DEBGFS_LINE_SZ)) {
- qdma_log_error(
- "%s: Insufficient buffer, err:%d\n",
- __func__,
- -QDMA_ERR_NO_MEM);
- return -QDMA_ERR_NO_MEM;
- }
- buf += rv;
- data_len += rv;
- buflen -= rv;
- } else
- qdma_log_info(
- "%-40s [%2u,%2u] %#-10x\n",
- bitfield_name,
- msb, lsb,
- (reg_val & bitfield) >> lsb);
-
-
- } else {
- if (buf) {
- rv = QDMA_SNPRINTF_S(buf, buflen,
- DEBGFS_LINE_SZ,
- "%-40s [%5u] %#-10x\n",
- bitfield_name,
- lsb,
- (reg_val & bitfield) >>
- lsb);
- if ((rv < 0) || (rv > DEBGFS_LINE_SZ)) {
- qdma_log_error(
- "%s: Insufficient buffer, err:%d\n",
- __func__,
- -QDMA_ERR_NO_MEM);
- return -QDMA_ERR_NO_MEM;
- }
- buf += rv;
- data_len += rv;
- buflen -= rv;
- } else
- qdma_log_info(
- "%-40s [%5u] %#-10x\n",
- bitfield_name,
- lsb,
- (reg_val & bitfield) >> lsb);
-
- }
- }
- }
-
- return data_len;
-
-}
diff --git a/QDMA/DPDK/drivers/net/qdma/qdma_access/qdma_s80_hard_access/qdma_s80_hard_access.h b/QDMA/DPDK/drivers/net/qdma/qdma_access/qdma_s80_hard_access/qdma_s80_hard_access.h
deleted file mode 100644
index dbd7610d803fc9fef143302be24582a92f4f01de..0000000000000000000000000000000000000000
--- a/QDMA/DPDK/drivers/net/qdma/qdma_access/qdma_s80_hard_access/qdma_s80_hard_access.h
+++ /dev/null
@@ -1,294 +0,0 @@
-/*
- * Copyright(c) 2019-2020 Xilinx, Inc. All rights reserved.
- *
- * BSD LICENSE
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- *
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in
- * the documentation and/or other materials provided with the
- * distribution.
- * * Neither the name of the copyright holder nor the names of its
- * contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
- * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
- * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
- * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
- * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
- * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
- * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- */
-
-#ifndef __QDMA_S80_HARD_ACCESS_H_
-#define __QDMA_S80_HARD_ACCESS_H_
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-#include "qdma_platform.h"
-
-/**
- * enum qdma_error_idx - qdma errors
- */
-enum qdma_s80_hard_error_idx {
- /* Descriptor errors */
- QDMA_S80_HARD_DSC_ERR_POISON,
- QDMA_S80_HARD_DSC_ERR_UR_CA,
- QDMA_S80_HARD_DSC_ERR_PARAM,
- QDMA_S80_HARD_DSC_ERR_ADDR,
- QDMA_S80_HARD_DSC_ERR_TAG,
- QDMA_S80_HARD_DSC_ERR_FLR,
- QDMA_S80_HARD_DSC_ERR_TIMEOUT,
- QDMA_S80_HARD_DSC_ERR_DAT_POISON,
- QDMA_S80_HARD_DSC_ERR_FLR_CANCEL,
- QDMA_S80_HARD_DSC_ERR_DMA,
- QDMA_S80_HARD_DSC_ERR_DSC,
- QDMA_S80_HARD_DSC_ERR_RQ_CANCEL,
- QDMA_S80_HARD_DSC_ERR_DBE,
- QDMA_S80_HARD_DSC_ERR_SBE,
- QDMA_S80_HARD_DSC_ERR_ALL,
-
- /* TRQ Errors */
- QDMA_S80_HARD_TRQ_ERR_UNMAPPED,
- QDMA_S80_HARD_TRQ_ERR_QID_RANGE,
- QDMA_S80_HARD_TRQ_ERR_VF_ACCESS_ERR,
- QDMA_S80_HARD_TRQ_ERR_TCP_TIMEOUT,
- QDMA_S80_HARD_TRQ_ERR_ALL,
-
- /* C2H Errors */
- QDMA_S80_HARD_ST_C2H_ERR_MTY_MISMATCH,
- QDMA_S80_HARD_ST_C2H_ERR_LEN_MISMATCH,
- QDMA_S80_HARD_ST_C2H_ERR_QID_MISMATCH,
- QDMA_S80_HARD_ST_C2H_ERR_DESC_RSP_ERR,
- QDMA_S80_HARD_ST_C2H_ERR_ENG_WPL_DATA_PAR_ERR,
- QDMA_S80_HARD_ST_C2H_ERR_MSI_INT_FAIL,
- QDMA_S80_HARD_ST_C2H_ERR_ERR_DESC_CNT,
- QDMA_S80_HARD_ST_C2H_ERR_PORTID_CTXT_MISMATCH,
- QDMA_S80_HARD_ST_C2H_ERR_PORTID_BYP_IN_MISMATCH,
- QDMA_S80_HARD_ST_C2H_ERR_WRB_INV_Q_ERR,
- QDMA_S80_HARD_ST_C2H_ERR_WRB_QFULL_ERR,
- QDMA_S80_HARD_ST_C2H_ERR_WRB_CIDX_ERR,
- QDMA_S80_HARD_ST_C2H_ERR_WRB_PRTY_ERR,
- QDMA_S80_HARD_ST_C2H_ERR_ALL,
-
- /* Fatal Errors */
- QDMA_S80_HARD_ST_FATAL_ERR_MTY_MISMATCH,
- QDMA_S80_HARD_ST_FATAL_ERR_LEN_MISMATCH,
- QDMA_S80_HARD_ST_FATAL_ERR_QID_MISMATCH,
- QDMA_S80_HARD_ST_FATAL_ERR_TIMER_FIFO_RAM_RDBE,
- QDMA_S80_HARD_ST_FATAL_ERR_PFCH_II_RAM_RDBE,
- QDMA_S80_HARD_ST_FATAL_ERR_WRB_CTXT_RAM_RDBE,
- QDMA_S80_HARD_ST_FATAL_ERR_PFCH_CTXT_RAM_RDBE,
- QDMA_S80_HARD_ST_FATAL_ERR_DESC_REQ_FIFO_RAM_RDBE,
- QDMA_S80_HARD_ST_FATAL_ERR_INT_CTXT_RAM_RDBE,
- QDMA_S80_HARD_ST_FATAL_ERR_INT_QID2VEC_RAM_RDBE,
- QDMA_S80_HARD_ST_FATAL_ERR_WRB_COAL_DATA_RAM_RDBE,
- QDMA_S80_HARD_ST_FATAL_ERR_TUSER_FIFO_RAM_RDBE,
- QDMA_S80_HARD_ST_FATAL_ERR_QID_FIFO_RAM_RDBE,
- QDMA_S80_HARD_ST_FATAL_ERR_PAYLOAD_FIFO_RAM_RDBE,
- QDMA_S80_HARD_ST_FATAL_ERR_WPL_DATA_PAR_ERR,
- QDMA_S80_HARD_ST_FATAL_ERR_ALL,
-
- /* H2C Errors */
- QDMA_S80_HARD_ST_H2C_ERR_ZERO_LEN_DESC_ERR,
- QDMA_S80_HARD_ST_H2C_ERR_SDI_MRKR_REQ_MOP_ERR,
- QDMA_S80_HARD_ST_H2C_ERR_NO_DMA_DSC,
- QDMA_S80_HARD_ST_H2C_ERR_DBE,
- QDMA_S80_HARD_ST_H2C_ERR_SBE,
- QDMA_S80_HARD_ST_H2C_ERR_ALL,
-
- /* Single bit errors */
- QDMA_S80_HARD_SBE_ERR_MI_H2C0_DAT,
- QDMA_S80_HARD_SBE_ERR_MI_C2H0_DAT,
- QDMA_S80_HARD_SBE_ERR_H2C_RD_BRG_DAT,
- QDMA_S80_HARD_SBE_ERR_H2C_WR_BRG_DAT,
- QDMA_S80_HARD_SBE_ERR_C2H_RD_BRG_DAT,
- QDMA_S80_HARD_SBE_ERR_C2H_WR_BRG_DAT,
- QDMA_S80_HARD_SBE_ERR_FUNC_MAP,
- QDMA_S80_HARD_SBE_ERR_DSC_HW_CTXT,
- QDMA_S80_HARD_SBE_ERR_DSC_CRD_RCV,
- QDMA_S80_HARD_SBE_ERR_DSC_SW_CTXT,
- QDMA_S80_HARD_SBE_ERR_DSC_CPLI,
- QDMA_S80_HARD_SBE_ERR_DSC_CPLD,
- QDMA_S80_HARD_SBE_ERR_PASID_CTXT_RAM,
- QDMA_S80_HARD_SBE_ERR_TIMER_FIFO_RAM,
- QDMA_S80_HARD_SBE_ERR_PAYLOAD_FIFO_RAM,
- QDMA_S80_HARD_SBE_ERR_QID_FIFO_RAM,
- QDMA_S80_HARD_SBE_ERR_TUSER_FIFO_RAM,
- QDMA_S80_HARD_SBE_ERR_WRB_COAL_DATA_RAM,
- QDMA_S80_HARD_SBE_ERR_INT_QID2VEC_RAM,
- QDMA_S80_HARD_SBE_ERR_INT_CTXT_RAM,
- QDMA_S80_HARD_SBE_ERR_DESC_REQ_FIFO_RAM,
- QDMA_S80_HARD_SBE_ERR_PFCH_CTXT_RAM,
- QDMA_S80_HARD_SBE_ERR_WRB_CTXT_RAM,
- QDMA_S80_HARD_SBE_ERR_PFCH_LL_RAM,
- QDMA_S80_HARD_SBE_ERR_ALL,
-
- /* Double bit Errors */
- QDMA_S80_HARD_DBE_ERR_MI_H2C0_DAT,
- QDMA_S80_HARD_DBE_ERR_MI_C2H0_DAT,
- QDMA_S80_HARD_DBE_ERR_H2C_RD_BRG_DAT,
- QDMA_S80_HARD_DBE_ERR_H2C_WR_BRG_DAT,
- QDMA_S80_HARD_DBE_ERR_C2H_RD_BRG_DAT,
- QDMA_S80_HARD_DBE_ERR_C2H_WR_BRG_DAT,
- QDMA_S80_HARD_DBE_ERR_FUNC_MAP,
- QDMA_S80_HARD_DBE_ERR_DSC_HW_CTXT,
- QDMA_S80_HARD_DBE_ERR_DSC_CRD_RCV,
- QDMA_S80_HARD_DBE_ERR_DSC_SW_CTXT,
- QDMA_S80_HARD_DBE_ERR_DSC_CPLI,
- QDMA_S80_HARD_DBE_ERR_DSC_CPLD,
- QDMA_S80_HARD_DBE_ERR_PASID_CTXT_RAM,
- QDMA_S80_HARD_DBE_ERR_TIMER_FIFO_RAM,
- QDMA_S80_HARD_DBE_ERR_PAYLOAD_FIFO_RAM,
- QDMA_S80_HARD_DBE_ERR_QID_FIFO_RAM,
- QDMA_S80_HARD_DBE_ERR_WRB_COAL_DATA_RAM,
- QDMA_S80_HARD_DBE_ERR_INT_QID2VEC_RAM,
- QDMA_S80_HARD_DBE_ERR_INT_CTXT_RAM,
- QDMA_S80_HARD_DBE_ERR_DESC_REQ_FIFO_RAM,
- QDMA_S80_HARD_DBE_ERR_PFCH_CTXT_RAM,
- QDMA_S80_HARD_DBE_ERR_WRB_CTXT_RAM,
- QDMA_S80_HARD_DBE_ERR_PFCH_LL_RAM,
- QDMA_S80_HARD_DBE_ERR_ALL,
-
- QDMA_S80_HARD_ERRS_ALL
-};
-
-struct qdma_s80_hard_hw_err_info {
- enum qdma_s80_hard_error_idx idx;
- const char *err_name;
- uint32_t mask_reg_addr;
- uint32_t stat_reg_addr;
- uint32_t leaf_err_mask;
- uint32_t global_err_mask;
- void (*qdma_s80_hard_hw_err_process)(void *dev_hndl);
-};
-
-
-int qdma_s80_hard_init_ctxt_memory(void *dev_hndl);
-
-int qdma_s80_hard_qid2vec_conf(void *dev_hndl, uint8_t c2h, uint16_t hw_qid,
- struct qdma_qid2vec *ctxt,
- enum qdma_hw_access_type access_type);
-
-int qdma_s80_hard_fmap_conf(void *dev_hndl, uint16_t func_id,
- struct qdma_fmap_cfg *config,
- enum qdma_hw_access_type access_type);
-
-int qdma_s80_hard_sw_ctx_conf(void *dev_hndl, uint8_t c2h, uint16_t hw_qid,
- struct qdma_descq_sw_ctxt *ctxt,
- enum qdma_hw_access_type access_type);
-
-int qdma_s80_hard_pfetch_ctx_conf(void *dev_hndl, uint16_t hw_qid,
- struct qdma_descq_prefetch_ctxt *ctxt,
- enum qdma_hw_access_type access_type);
-
-int qdma_s80_hard_cmpt_ctx_conf(void *dev_hndl, uint16_t hw_qid,
- struct qdma_descq_cmpt_ctxt *ctxt,
- enum qdma_hw_access_type access_type);
-
-int qdma_s80_hard_hw_ctx_conf(void *dev_hndl, uint8_t c2h, uint16_t hw_qid,
- struct qdma_descq_hw_ctxt *ctxt,
- enum qdma_hw_access_type access_type);
-
-int qdma_s80_hard_credit_ctx_conf(void *dev_hndl, uint8_t c2h, uint16_t hw_qid,
- struct qdma_descq_credit_ctxt *ctxt,
- enum qdma_hw_access_type access_type);
-
-int qdma_s80_hard_indirect_intr_ctx_conf(void *dev_hndl, uint16_t ring_index,
- struct qdma_indirect_intr_ctxt *ctxt,
- enum qdma_hw_access_type access_type);
-
-int qdma_s80_hard_set_default_global_csr(void *dev_hndl);
-
-int qdma_s80_hard_queue_pidx_update(void *dev_hndl, uint8_t is_vf, uint16_t qid,
- uint8_t is_c2h, const struct qdma_q_pidx_reg_info *reg_info);
-
-int qdma_s80_hard_queue_cmpt_cidx_update(void *dev_hndl, uint8_t is_vf,
- uint16_t qid, const struct qdma_q_cmpt_cidx_reg_info *reg_info);
-
-int qdma_s80_hard_queue_intr_cidx_update(void *dev_hndl, uint8_t is_vf,
- uint16_t qid, const struct qdma_intr_cidx_reg_info *reg_info);
-
-int qdma_cmp_get_user_bar(void *dev_hndl, uint8_t is_vf,
- uint8_t func_id, uint8_t *user_bar);
-
-int qdma_s80_hard_get_device_attributes(void *dev_hndl,
- struct qdma_dev_attributes *dev_info);
-
-uint32_t qdma_s80_hard_reg_dump_buf_len(void);
-
-int qdma_s80_hard_context_buf_len(uint8_t st,
- enum qdma_dev_q_type q_type, uint32_t *req_buflen);
-
-int qdma_s80_hard_dump_config_regs(void *dev_hndl, uint8_t is_vf,
- char *buf, uint32_t buflen);
-
-int qdma_s80_hard_hw_error_process(void *dev_hndl);
-const char *qdma_s80_hard_hw_get_error_name(uint32_t err_idx);
-int qdma_s80_hard_hw_error_enable(void *dev_hndl, uint32_t err_idx);
-
-int qdma_s80_hard_dump_queue_context(void *dev_hndl,
- uint8_t st,
- enum qdma_dev_q_type q_type,
- struct qdma_descq_context *ctxt_data,
- char *buf, uint32_t buflen);
-
-int qdma_s80_hard_dump_intr_context(void *dev_hndl,
- struct qdma_indirect_intr_ctxt *intr_ctx,
- int ring_index,
- char *buf, uint32_t buflen);
-
-int qdma_s80_hard_read_dump_queue_context(void *dev_hndl,
- uint16_t qid_hw,
- uint8_t st,
- enum qdma_dev_q_type q_type,
- char *buf, uint32_t buflen);
-
-int qdma_s80_hard_dump_config_reg_list(void *dev_hndl,
- uint32_t total_regs,
- struct qdma_reg_data *reg_list,
- char *buf, uint32_t buflen);
-
-int qdma_s80_hard_read_reg_list(void *dev_hndl, uint8_t is_vf,
- uint16_t reg_rd_slot,
- uint16_t *total_regs,
- struct qdma_reg_data *reg_list);
-
-int qdma_s80_hard_global_csr_conf(void *dev_hndl, uint8_t index,
- uint8_t count,
- uint32_t *csr_val,
- enum qdma_global_csr_type csr_type,
- enum qdma_hw_access_type access_type);
-
-int qdma_s80_hard_global_writeback_interval_conf(void *dev_hndl,
- enum qdma_wrb_interval *wb_int,
- enum qdma_hw_access_type access_type);
-
-int qdma_s80_hard_mm_channel_conf(void *dev_hndl, uint8_t channel,
- uint8_t is_c2h,
- uint8_t enable);
-
-int qdma_s80_hard_dump_reg_info(void *dev_hndl, uint32_t reg_addr,
- uint32_t num_regs, char *buf, uint32_t buflen);
-
-uint32_t qdma_s80_hard_get_config_num_regs(void);
-
-struct xreg_info *qdma_s80_hard_get_config_regs(void);
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __QDMA_S80_HARD_ACCESS_H_ */
diff --git a/QDMA/DPDK/drivers/net/qdma/qdma_access/qdma_s80_hard_access/qdma_s80_hard_reg.h b/QDMA/DPDK/drivers/net/qdma/qdma_access/qdma_s80_hard_access/qdma_s80_hard_reg.h
deleted file mode 100644
index 31f57604c64b4f9da2451630b5d154952db6ed9a..0000000000000000000000000000000000000000
--- a/QDMA/DPDK/drivers/net/qdma/qdma_access/qdma_s80_hard_access/qdma_s80_hard_reg.h
+++ /dev/null
@@ -1,2061 +0,0 @@
-/*
- * Copyright(c) 2019-2020 Xilinx, Inc. All rights reserved.
- *
- * BSD LICENSE
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- *
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in
- * the documentation and/or other materials provided with the
- * distribution.
- * * Neither the name of the copyright holder nor the names of its
- * contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
- * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
- * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
- * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
- * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
- * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
- * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- */
-
-#ifndef __QDMA_S80_HARD_REG_H
-#define __QDMA_S80_HARD_REG_H
-
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-#include "qdma_platform.h"
-
-#ifdef CHAR_BIT
-#undef CHAR_BIT
-#endif
-#define CHAR_BIT 8
-
-#ifdef BIT
-#undef BIT
-#endif
-#define BIT(n) (1u << (n))
-
-#ifdef BITS_PER_BYTE
-#undef BITS_PER_BYTE
-#endif
-#define BITS_PER_BYTE CHAR_BIT
-
-#ifdef BITS_PER_LONG
-#undef BITS_PER_LONG
-#endif
-#define BITS_PER_LONG (sizeof(uint32_t) * BITS_PER_BYTE)
-
-#ifdef BITS_PER_LONG_LONG
-#undef BITS_PER_LONG_LONG
-#endif
-#define BITS_PER_LONG_LONG (sizeof(uint64_t) * BITS_PER_BYTE)
-
-#ifdef GENMASK
-#undef GENMASK
-#endif
-#define GENMASK(h, l) \
- ((0xFFFFFFFF << (l)) & (0xFFFFFFFF >> (BITS_PER_LONG - 1 - (h))))
-
-#ifdef GENMASK_ULL
-#undef GENMASK_ULL
-#endif
-#define GENMASK_ULL(h, l) \
- ((0xFFFFFFFFFFFFFFFF << (l)) & \
- (0xFFFFFFFFFFFFFFFF >> (BITS_PER_LONG_LONG - 1 - (h))))
-
-#define DEBGFS_LINE_SZ (81)
-
-#ifdef ARRAY_SIZE
-#undef ARRAY_SIZE
-#endif
-#define ARRAY_SIZE(arr) (sizeof(arr) / \
- sizeof(arr[0]))
-
-
-uint32_t qdma_s80_hard_config_num_regs_get(void);
-struct xreg_info *qdma_s80_hard_config_regs_get(void);
-#define QDMA_S80_HARD_CFG_BLK_IDENTIFIER_ADDR 0x00
-#define CFG_BLK_IDENTIFIER_MASK GENMASK(31, 20)
-#define CFG_BLK_IDENTIFIER_1_MASK GENMASK(19, 16)
-#define CFG_BLK_IDENTIFIER_RSVD_1_MASK GENMASK(15, 8)
-#define CFG_BLK_IDENTIFIER_VERSION_MASK GENMASK(7, 0)
-#define QDMA_S80_HARD_CFG_BLK_BUSDEV_ADDR 0x04
-#define CFG_BLK_BUSDEV_BDF_MASK GENMASK(15, 0)
-#define QDMA_S80_HARD_CFG_BLK_PCIE_MAX_PLD_SIZE_ADDR 0x08
-#define CFG_BLK_PCIE_MAX_PLD_SIZE_MASK GENMASK(2, 0)
-#define QDMA_S80_HARD_CFG_BLK_PCIE_MAX_READ_REQ_SIZE_ADDR 0x0C
-#define CFG_BLK_PCIE_MAX_READ_REQ_SIZE_MASK GENMASK(2, 0)
-#define QDMA_S80_HARD_CFG_BLK_SYSTEM_ID_ADDR 0x10
-#define CFG_BLK_SYSTEM_ID_MASK GENMASK(15, 0)
-#define QDMA_S80_HARD_CFG_BLK_MSI_ENABLE_ADDR 0x014
-#define CFG_BLK_MSI_ENABLE_3_MASK BIT(17)
-#define CFG_BLK_MSI_ENABLE_MSIX3_MASK BIT(16)
-#define CFG_BLK_MSI_ENABLE_2_MASK BIT(13)
-#define CFG_BLK_MSI_ENABLE_MSIX2_MASK BIT(12)
-#define CFG_BLK_MSI_ENABLE_1_MASK BIT(9)
-#define CFG_BLK_MSI_ENABLE_MSIX1_MASK BIT(8)
-#define CFG_BLK_MSI_ENABLE_0_MASK BIT(1)
-#define CFG_BLK_MSI_ENABLE_MSIX0_MASK BIT(0)
-#define QDMA_S80_HARD_CFG_PCIE_DATA_WIDTH_ADDR 0x18
-#define CFG_PCIE_DATA_WIDTH_DATAPATH_MASK GENMASK(2, 0)
-#define QDMA_S80_HARD_CFG_PCIE_CTL_ADDR 0x1C
-#define CFG_PCIE_CTL_RRQ_DISABLE_MASK BIT(1)
-#define CFG_PCIE_CTL_RELAXED_ORDERING_MASK BIT(0)
-#define QDMA_S80_HARD_CFG_AXI_USER_MAX_PLD_SIZE_ADDR 0x40
-#define CFG_AXI_USER_MAX_PLD_SIZE_ISSUED_MASK GENMASK(6, 4)
-#define CFG_AXI_USER_MAX_PLD_SIZE_PROG_MASK GENMASK(2, 0)
-#define QDMA_S80_HARD_CFG_AXI_USER_MAX_READ_REQ_SIZE_ADDR 0x44
-#define CFG_AXI_USER_MAX_READ_REQ_SIZE_USISSUED_MASK GENMASK(6, 4)
-#define CFG_AXI_USER_MAX_READ_REQ_SIZE_USPROG_MASK GENMASK(2, 0)
-#define QDMA_S80_HARD_CFG_BLK_MISC_CTL_ADDR 0x4C
-#define CFG_BLK_MISC_CTL_NUM_TAG_MASK GENMASK(19, 8)
-#define CFG_BLK_MISC_CTL_RQ_METERING_MULTIPLIER_MASK GENMASK(4, 0)
-#define QDMA_S80_HARD_CFG_BLK_SCRATCH_0_ADDR 0x80
-#define CFG_BLK_SCRATCH_0_MASK GENMASK(31, 0)
-#define QDMA_S80_HARD_CFG_BLK_SCRATCH_1_ADDR 0x84
-#define CFG_BLK_SCRATCH_1_MASK GENMASK(31, 0)
-#define QDMA_S80_HARD_CFG_BLK_SCRATCH_2_ADDR 0x88
-#define CFG_BLK_SCRATCH_2_MASK GENMASK(31, 0)
-#define QDMA_S80_HARD_CFG_BLK_SCRATCH_3_ADDR 0x8C
-#define CFG_BLK_SCRATCH_3_MASK GENMASK(31, 0)
-#define QDMA_S80_HARD_CFG_BLK_SCRATCH_4_ADDR 0x90
-#define CFG_BLK_SCRATCH_4_MASK GENMASK(31, 0)
-#define QDMA_S80_HARD_CFG_BLK_SCRATCH_5_ADDR 0x94
-#define CFG_BLK_SCRATCH_5_MASK GENMASK(31, 0)
-#define QDMA_S80_HARD_CFG_BLK_SCRATCH_6_ADDR 0x98
-#define CFG_BLK_SCRATCH_6_MASK GENMASK(31, 0)
-#define QDMA_S80_HARD_CFG_BLK_SCRATCH_7_ADDR 0x9C
-#define CFG_BLK_SCRATCH_7_MASK GENMASK(31, 0)
-#define QDMA_S80_HARD_RAM_SBE_MSK_A_ADDR 0xF0
-#define RAM_SBE_MSK_A_MASK GENMASK(31, 0)
-#define QDMA_S80_HARD_RAM_SBE_STS_A_ADDR 0xF4
-#define RAM_SBE_STS_A_RSVD_1_MASK BIT(31)
-#define RAM_SBE_STS_A_PFCH_LL_RAM_MASK BIT(30)
-#define RAM_SBE_STS_A_WRB_CTXT_RAM_MASK BIT(29)
-#define RAM_SBE_STS_A_PFCH_CTXT_RAM_MASK BIT(28)
-#define RAM_SBE_STS_A_DESC_REQ_FIFO_RAM_MASK BIT(27)
-#define RAM_SBE_STS_A_INT_CTXT_RAM_MASK BIT(26)
-#define RAM_SBE_STS_A_INT_QID2VEC_RAM_MASK BIT(25)
-#define RAM_SBE_STS_A_WRB_COAL_DATA_RAM_MASK BIT(24)
-#define RAM_SBE_STS_A_TUSER_FIFO_RAM_MASK BIT(23)
-#define RAM_SBE_STS_A_QID_FIFO_RAM_MASK BIT(22)
-#define RAM_SBE_STS_A_PLD_FIFO_RAM_MASK BIT(21)
-#define RAM_SBE_STS_A_TIMER_FIFO_RAM_MASK BIT(20)
-#define RAM_SBE_STS_A_PASID_CTXT_RAM_MASK BIT(19)
-#define RAM_SBE_STS_A_DSC_CPLD_MASK BIT(18)
-#define RAM_SBE_STS_A_DSC_CPLI_MASK BIT(17)
-#define RAM_SBE_STS_A_DSC_SW_CTXT_MASK BIT(16)
-#define RAM_SBE_STS_A_DSC_CRD_RCV_MASK BIT(15)
-#define RAM_SBE_STS_A_DSC_HW_CTXT_MASK BIT(14)
-#define RAM_SBE_STS_A_FUNC_MAP_MASK BIT(13)
-#define RAM_SBE_STS_A_C2H_WR_BRG_DAT_MASK BIT(12)
-#define RAM_SBE_STS_A_C2H_RD_BRG_DAT_MASK BIT(11)
-#define RAM_SBE_STS_A_H2C_WR_BRG_DAT_MASK BIT(10)
-#define RAM_SBE_STS_A_H2C_RD_BRG_DAT_MASK BIT(9)
-#define RAM_SBE_STS_A_RSVD_2_MASK GENMASK(8, 5)
-#define RAM_SBE_STS_A_MI_C2H0_DAT_MASK BIT(4)
-#define RAM_SBE_STS_A_RSVD_3_MASK GENMASK(3, 1)
-#define RAM_SBE_STS_A_MI_H2C0_DAT_MASK BIT(0)
-#define QDMA_S80_HARD_RAM_DBE_MSK_A_ADDR 0xF8
-#define RAM_DBE_MSK_A_MASK GENMASK(31, 0)
-#define QDMA_S80_HARD_RAM_DBE_STS_A_ADDR 0xFC
-#define RAM_DBE_STS_A_RSVD_1_MASK BIT(31)
-#define RAM_DBE_STS_A_PFCH_LL_RAM_MASK BIT(30)
-#define RAM_DBE_STS_A_WRB_CTXT_RAM_MASK BIT(29)
-#define RAM_DBE_STS_A_PFCH_CTXT_RAM_MASK BIT(28)
-#define RAM_DBE_STS_A_DESC_REQ_FIFO_RAM_MASK BIT(27)
-#define RAM_DBE_STS_A_INT_CTXT_RAM_MASK BIT(26)
-#define RAM_DBE_STS_A_INT_QID2VEC_RAM_MASK BIT(25)
-#define RAM_DBE_STS_A_WRB_COAL_DATA_RAM_MASK BIT(24)
-#define RAM_DBE_STS_A_TUSER_FIFO_RAM_MASK BIT(23)
-#define RAM_DBE_STS_A_QID_FIFO_RAM_MASK BIT(22)
-#define RAM_DBE_STS_A_PLD_FIFO_RAM_MASK BIT(21)
-#define RAM_DBE_STS_A_TIMER_FIFO_RAM_MASK BIT(20)
-#define RAM_DBE_STS_A_PASID_CTXT_RAM_MASK BIT(19)
-#define RAM_DBE_STS_A_DSC_CPLD_MASK BIT(18)
-#define RAM_DBE_STS_A_DSC_CPLI_MASK BIT(17)
-#define RAM_DBE_STS_A_DSC_SW_CTXT_MASK BIT(16)
-#define RAM_DBE_STS_A_DSC_CRD_RCV_MASK BIT(15)
-#define RAM_DBE_STS_A_DSC_HW_CTXT_MASK BIT(14)
-#define RAM_DBE_STS_A_FUNC_MAP_MASK BIT(13)
-#define RAM_DBE_STS_A_C2H_WR_BRG_DAT_MASK BIT(12)
-#define RAM_DBE_STS_A_C2H_RD_BRG_DAT_MASK BIT(11)
-#define RAM_DBE_STS_A_H2C_WR_BRG_DAT_MASK BIT(10)
-#define RAM_DBE_STS_A_H2C_RD_BRG_DAT_MASK BIT(9)
-#define RAM_DBE_STS_A_RSVD_2_MASK GENMASK(8, 5)
-#define RAM_DBE_STS_A_MI_C2H0_DAT_MASK BIT(4)
-#define RAM_DBE_STS_A_RSVD_3_MASK GENMASK(3, 1)
-#define RAM_DBE_STS_A_MI_H2C0_DAT_MASK BIT(0)
-#define QDMA_S80_HARD_GLBL2_IDENTIFIER_ADDR 0x100
-#define GLBL2_IDENTIFIER_MASK GENMASK(31, 8)
-#define GLBL2_IDENTIFIER_VERSION_MASK GENMASK(7, 0)
-#define QDMA_S80_HARD_GLBL2_PF_BARLITE_INT_ADDR 0x104
-#define GLBL2_PF_BARLITE_INT_PF3_BAR_MAP_MASK GENMASK(23, 18)
-#define GLBL2_PF_BARLITE_INT_PF2_BAR_MAP_MASK GENMASK(17, 12)
-#define GLBL2_PF_BARLITE_INT_PF1_BAR_MAP_MASK GENMASK(11, 6)
-#define GLBL2_PF_BARLITE_INT_PF0_BAR_MAP_MASK GENMASK(5, 0)
-#define QDMA_S80_HARD_GLBL2_PF_VF_BARLITE_INT_ADDR 0x108
-#define GLBL2_PF_VF_BARLITE_INT_PF3_MAP_MASK GENMASK(23, 18)
-#define GLBL2_PF_VF_BARLITE_INT_PF2_MAP_MASK GENMASK(17, 12)
-#define GLBL2_PF_VF_BARLITE_INT_PF1_MAP_MASK GENMASK(11, 6)
-#define GLBL2_PF_VF_BARLITE_INT_PF0_MAP_MASK GENMASK(5, 0)
-#define QDMA_S80_HARD_GLBL2_PF_BARLITE_EXT_ADDR 0x10C
-#define GLBL2_PF_BARLITE_EXT_PF3_BAR_MAP_MASK GENMASK(23, 18)
-#define GLBL2_PF_BARLITE_EXT_PF2_BAR_MAP_MASK GENMASK(17, 12)
-#define GLBL2_PF_BARLITE_EXT_PF1_BAR_MAP_MASK GENMASK(11, 6)
-#define GLBL2_PF_BARLITE_EXT_PF0_BAR_MAP_MASK GENMASK(5, 0)
-#define QDMA_S80_HARD_GLBL2_PF_VF_BARLITE_EXT_ADDR 0x110
-#define GLBL2_PF_VF_BARLITE_EXT_PF3_MAP_MASK GENMASK(23, 18)
-#define GLBL2_PF_VF_BARLITE_EXT_PF2_MAP_MASK GENMASK(17, 12)
-#define GLBL2_PF_VF_BARLITE_EXT_PF1_MAP_MASK GENMASK(11, 6)
-#define GLBL2_PF_VF_BARLITE_EXT_PF0_MAP_MASK GENMASK(5, 0)
-#define QDMA_S80_HARD_GLBL2_CHANNEL_INST_ADDR 0x114
-#define GLBL2_CHANNEL_INST_RSVD_1_MASK GENMASK(31, 18)
-#define GLBL2_CHANNEL_INST_C2H_ST_MASK BIT(17)
-#define GLBL2_CHANNEL_INST_H2C_ST_MASK BIT(16)
-#define GLBL2_CHANNEL_INST_RSVD_2_MASK GENMASK(15, 9)
-#define GLBL2_CHANNEL_INST_C2H_ENG_MASK BIT(8)
-#define GLBL2_CHANNEL_INST_RSVD_3_MASK GENMASK(7, 1)
-#define GLBL2_CHANNEL_INST_H2C_ENG_MASK BIT(0)
-#define QDMA_S80_HARD_GLBL2_CHANNEL_MDMA_ADDR 0x118
-#define GLBL2_CHANNEL_MDMA_RSVD_1_MASK GENMASK(31, 18)
-#define GLBL2_CHANNEL_MDMA_C2H_ST_MASK BIT(17)
-#define GLBL2_CHANNEL_MDMA_H2C_ST_MASK BIT(16)
-#define GLBL2_CHANNEL_MDMA_RSVD_2_MASK GENMASK(15, 9)
-#define GLBL2_CHANNEL_MDMA_C2H_ENG_MASK BIT(8)
-#define GLBL2_CHANNEL_MDMA_RSVD_3_MASK GENMASK(7, 1)
-#define GLBL2_CHANNEL_MDMA_H2C_ENG_MASK BIT(0)
-#define QDMA_S80_HARD_GLBL2_CHANNEL_STRM_ADDR 0x11C
-#define GLBL2_CHANNEL_STRM_RSVD_1_MASK GENMASK(31, 18)
-#define GLBL2_CHANNEL_STRM_C2H_ST_MASK BIT(17)
-#define GLBL2_CHANNEL_STRM_H2C_ST_MASK BIT(16)
-#define GLBL2_CHANNEL_STRM_RSVD_2_MASK GENMASK(15, 9)
-#define GLBL2_CHANNEL_STRM_C2H_ENG_MASK BIT(8)
-#define GLBL2_CHANNEL_STRM_RSVD_3_MASK GENMASK(7, 1)
-#define GLBL2_CHANNEL_STRM_H2C_ENG_MASK BIT(0)
-#define QDMA_S80_HARD_GLBL2_CHANNEL_CAP_ADDR 0x120
-#define GLBL2_CHANNEL_CAP_RSVD_1_MASK GENMASK(31, 12)
-#define GLBL2_CHANNEL_CAP_MULTIQ_MAX_MASK GENMASK(11, 0)
-#define QDMA_S80_HARD_GLBL2_CHANNEL_PASID_CAP_ADDR 0x128
-#define GLBL2_CHANNEL_PASID_CAP_RSVD_1_MASK GENMASK(31, 16)
-#define GLBL2_CHANNEL_PASID_CAP_BRIDGEOFFSET_MASK GENMASK(15, 4)
-#define GLBL2_CHANNEL_PASID_CAP_RSVD_2_MASK GENMASK(3, 2)
-#define GLBL2_CHANNEL_PASID_CAP_BRIDGEEN_MASK BIT(1)
-#define GLBL2_CHANNEL_PASID_CAP_DMAEN_MASK BIT(0)
-#define QDMA_S80_HARD_GLBL2_CHANNEL_FUNC_RET_ADDR 0x12C
-#define GLBL2_CHANNEL_FUNC_RET_RSVD_1_MASK GENMASK(31, 8)
-#define GLBL2_CHANNEL_FUNC_RET_FUNC_MASK GENMASK(7, 0)
-#define QDMA_S80_HARD_GLBL2_SYSTEM_ID_ADDR 0x130
-#define GLBL2_SYSTEM_ID_RSVD_1_MASK GENMASK(31, 16)
-#define GLBL2_SYSTEM_ID_MASK GENMASK(15, 0)
-#define QDMA_S80_HARD_GLBL2_MISC_CAP_ADDR 0x134
-#define GLBL2_MISC_CAP_RSVD_1_MASK GENMASK(31, 0)
-#define QDMA_S80_HARD_GLBL2_DBG_PCIE_RQ0_ADDR 0x1B8
-#define GLBL2_PCIE_RQ0_NPH_AVL_MASK GENMASK(31, 20)
-#define GLBL2_PCIE_RQ0_RCB_AVL_MASK GENMASK(19, 10)
-#define GLBL2_PCIE_RQ0_SLV_RD_CREDS_MASK GENMASK(9, 4)
-#define GLBL2_PCIE_RQ0_TAG_EP_MASK GENMASK(3, 2)
-#define GLBL2_PCIE_RQ0_TAG_FL_MASK GENMASK(1, 0)
-#define QDMA_S80_HARD_GLBL2_DBG_PCIE_RQ1_ADDR 0x1BC
-#define GLBL2_PCIE_RQ1_RSVD_1_MASK GENMASK(31, 17)
-#define GLBL2_PCIE_RQ1_WTLP_REQ_MASK BIT(16)
-#define GLBL2_PCIE_RQ1_WTLP_HEADER_FIFO_FL_MASK BIT(15)
-#define GLBL2_PCIE_RQ1_WTLP_HEADER_FIFO_EP_MASK BIT(14)
-#define GLBL2_PCIE_RQ1_RQ_FIFO_EP_MASK BIT(13)
-#define GLBL2_PCIE_RQ1_RQ_FIFO_FL_MASK BIT(12)
-#define GLBL2_PCIE_RQ1_TLPSM_MASK GENMASK(11, 9)
-#define GLBL2_PCIE_RQ1_TLPSM512_MASK GENMASK(8, 6)
-#define GLBL2_PCIE_RQ1_RREQ0_RCB_OK_MASK BIT(5)
-#define GLBL2_PCIE_RQ1_RREQ0_SLV_MASK BIT(4)
-#define GLBL2_PCIE_RQ1_RREQ0_VLD_MASK BIT(3)
-#define GLBL2_PCIE_RQ1_RREQ1_RCB_OK_MASK BIT(2)
-#define GLBL2_PCIE_RQ1_RREQ1_SLV_MASK BIT(1)
-#define GLBL2_PCIE_RQ1_RREQ1_VLD_MASK BIT(0)
-#define QDMA_S80_HARD_GLBL2_DBG_AXIMM_WR0_ADDR 0x1C0
-#define GLBL2_AXIMM_WR0_RSVD_1_MASK GENMASK(31, 27)
-#define GLBL2_AXIMM_WR0_WR_REQ_MASK BIT(26)
-#define GLBL2_AXIMM_WR0_WR_CHN_MASK GENMASK(25, 23)
-#define GLBL2_AXIMM_WR0_WTLP_DATA_FIFO_EP_MASK BIT(22)
-#define GLBL2_AXIMM_WR0_WPL_FIFO_EP_MASK BIT(21)
-#define GLBL2_AXIMM_WR0_BRSP_CLAIM_CHN_MASK GENMASK(20, 18)
-#define GLBL2_AXIMM_WR0_WRREQ_CNT_MASK GENMASK(17, 12)
-#define GLBL2_AXIMM_WR0_BID_MASK GENMASK(11, 9)
-#define GLBL2_AXIMM_WR0_BVALID_MASK BIT(8)
-#define GLBL2_AXIMM_WR0_BREADY_MASK BIT(7)
-#define GLBL2_AXIMM_WR0_WVALID_MASK BIT(6)
-#define GLBL2_AXIMM_WR0_WREADY_MASK BIT(5)
-#define GLBL2_AXIMM_WR0_AWID_MASK GENMASK(4, 2)
-#define GLBL2_AXIMM_WR0_AWVALID_MASK BIT(1)
-#define GLBL2_AXIMM_WR0_AWREADY_MASK BIT(0)
-#define QDMA_S80_HARD_GLBL2_DBG_AXIMM_WR1_ADDR 0x1C4
-#define GLBL2_AXIMM_WR1_RSVD_1_MASK GENMASK(31, 30)
-#define GLBL2_AXIMM_WR1_BRSP_CNT4_MASK GENMASK(29, 24)
-#define GLBL2_AXIMM_WR1_BRSP_CNT3_MASK GENMASK(23, 18)
-#define GLBL2_AXIMM_WR1_BRSP_CNT2_MASK GENMASK(17, 12)
-#define GLBL2_AXIMM_WR1_BRSP_CNT1_MASK GENMASK(11, 6)
-#define GLBL2_AXIMM_WR1_BRSP_CNT0_MASK GENMASK(5, 0)
-#define QDMA_S80_HARD_GLBL2_DBG_AXIMM_RD0_ADDR 0x1C8
-#define GLBL2_AXIMM_RD0_RSVD_1_MASK GENMASK(31, 23)
-#define GLBL2_AXIMM_RD0_PND_CNT_MASK GENMASK(22, 17)
-#define GLBL2_AXIMM_RD0_RD_CHNL_MASK GENMASK(16, 14)
-#define GLBL2_AXIMM_RD0_RD_REQ_MASK BIT(13)
-#define GLBL2_AXIMM_RD0_RRSP_CLAIM_CHNL_MASK GENMASK(12, 10)
-#define GLBL2_AXIMM_RD0_RID_MASK GENMASK(9, 7)
-#define GLBL2_AXIMM_RD0_RVALID_MASK BIT(6)
-#define GLBL2_AXIMM_RD0_RREADY_MASK BIT(5)
-#define GLBL2_AXIMM_RD0_ARID_MASK GENMASK(4, 2)
-#define GLBL2_AXIMM_RD0_ARVALID_MASK BIT(1)
-#define GLBL2_AXIMM_RD0_ARREADY_MASK BIT(0)
-#define QDMA_S80_HARD_GLBL2_DBG_AXIMM_RD1_ADDR 0x1CC
-#define GLBL2_AXIMM_RD1_RSVD_1_MASK GENMASK(31, 30)
-#define GLBL2_AXIMM_RD1_RRSP_CNT4_MASK GENMASK(29, 24)
-#define GLBL2_AXIMM_RD1_RRSP_CNT3_MASK GENMASK(23, 18)
-#define GLBL2_AXIMM_RD1_RRSP_CNT2_MASK GENMASK(17, 12)
-#define GLBL2_AXIMM_RD1_RRSP_CNT1_MASK GENMASK(11, 6)
-#define GLBL2_AXIMM_RD1_RRSP_CNT0_MASK GENMASK(5, 0)
-#define QDMA_S80_HARD_GLBL_RNG_SZ_1_ADDR 0x204
-#define GLBL_RNG_SZ_1_RSVD_1_MASK GENMASK(31, 16)
-#define GLBL_RNG_SZ_1_RING_SIZE_MASK GENMASK(15, 0)
-#define QDMA_S80_HARD_GLBL_RNG_SZ_2_ADDR 0x208
-#define GLBL_RNG_SZ_2_RSVD_1_MASK GENMASK(31, 16)
-#define GLBL_RNG_SZ_2_RING_SIZE_MASK GENMASK(15, 0)
-#define QDMA_S80_HARD_GLBL_RNG_SZ_3_ADDR 0x20C
-#define GLBL_RNG_SZ_3_RSVD_1_MASK GENMASK(31, 16)
-#define GLBL_RNG_SZ_3_RING_SIZE_MASK GENMASK(15, 0)
-#define QDMA_S80_HARD_GLBL_RNG_SZ_4_ADDR 0x210
-#define GLBL_RNG_SZ_4_RSVD_1_MASK GENMASK(31, 16)
-#define GLBL_RNG_SZ_4_RING_SIZE_MASK GENMASK(15, 0)
-#define QDMA_S80_HARD_GLBL_RNG_SZ_5_ADDR 0x214
-#define GLBL_RNG_SZ_5_RSVD_1_MASK GENMASK(31, 16)
-#define GLBL_RNG_SZ_5_RING_SIZE_MASK GENMASK(15, 0)
-#define QDMA_S80_HARD_GLBL_RNG_SZ_6_ADDR 0x218
-#define GLBL_RNG_SZ_6_RSVD_1_MASK GENMASK(31, 16)
-#define GLBL_RNG_SZ_6_RING_SIZE_MASK GENMASK(15, 0)
-#define QDMA_S80_HARD_GLBL_RNG_SZ_7_ADDR 0x21C
-#define GLBL_RNG_SZ_7_RSVD_1_MASK GENMASK(31, 16)
-#define GLBL_RNG_SZ_7_RING_SIZE_MASK GENMASK(15, 0)
-#define QDMA_S80_HARD_GLBL_RNG_SZ_8_ADDR 0x220
-#define GLBL_RNG_SZ_8_RSVD_1_MASK GENMASK(31, 16)
-#define GLBL_RNG_SZ_8_RING_SIZE_MASK GENMASK(15, 0)
-#define QDMA_S80_HARD_GLBL_RNG_SZ_9_ADDR 0x224
-#define GLBL_RNG_SZ_9_RSVD_1_MASK GENMASK(31, 16)
-#define GLBL_RNG_SZ_9_RING_SIZE_MASK GENMASK(15, 0)
-#define QDMA_S80_HARD_GLBL_RNG_SZ_A_ADDR 0x228
-#define GLBL_RNG_SZ_A_RSVD_1_MASK GENMASK(31, 16)
-#define GLBL_RNG_SZ_A_RING_SIZE_MASK GENMASK(15, 0)
-#define QDMA_S80_HARD_GLBL_RNG_SZ_B_ADDR 0x22C
-#define GLBL_RNG_SZ_B_RSVD_1_MASK GENMASK(31, 16)
-#define GLBL_RNG_SZ_B_RING_SIZE_MASK GENMASK(15, 0)
-#define QDMA_S80_HARD_GLBL_RNG_SZ_C_ADDR 0x230
-#define GLBL_RNG_SZ_C_RSVD_1_MASK GENMASK(31, 16)
-#define GLBL_RNG_SZ_C_RING_SIZE_MASK GENMASK(15, 0)
-#define QDMA_S80_HARD_GLBL_RNG_SZ_D_ADDR 0x234
-#define GLBL_RNG_SZ_D_RSVD_1_MASK GENMASK(31, 16)
-#define GLBL_RNG_SZ_D_RING_SIZE_MASK GENMASK(15, 0)
-#define QDMA_S80_HARD_GLBL_RNG_SZ_E_ADDR 0x238
-#define GLBL_RNG_SZ_E_RSVD_1_MASK GENMASK(31, 16)
-#define GLBL_RNG_SZ_E_RING_SIZE_MASK GENMASK(15, 0)
-#define QDMA_S80_HARD_GLBL_RNG_SZ_F_ADDR 0x23C
-#define GLBL_RNG_SZ_F_RSVD_1_MASK GENMASK(31, 16)
-#define GLBL_RNG_SZ_F_RING_SIZE_MASK GENMASK(15, 0)
-#define QDMA_S80_HARD_GLBL_RNG_SZ_10_ADDR 0x240
-#define GLBL_RNG_SZ_10_RSVD_1_MASK GENMASK(31, 16)
-#define GLBL_RNG_SZ_10_RING_SIZE_MASK GENMASK(15, 0)
-#define QDMA_S80_HARD_GLBL_ERR_STAT_ADDR 0x248
-#define GLBL_ERR_STAT_RSVD_1_MASK GENMASK(31, 12)
-#define GLBL_ERR_STAT_ERR_H2C_ST_MASK BIT(11)
-#define GLBL_ERR_STAT_ERR_BDG_MASK BIT(10)
-#define GLBL_ERR_STAT_IND_CTXT_CMD_ERR_MASK BIT(9)
-#define GLBL_ERR_STAT_ERR_C2H_ST_MASK BIT(8)
-#define GLBL_ERR_STAT_ERR_C2H_MM_1_MASK BIT(7)
-#define GLBL_ERR_STAT_ERR_C2H_MM_0_MASK BIT(6)
-#define GLBL_ERR_STAT_ERR_H2C_MM_1_MASK BIT(5)
-#define GLBL_ERR_STAT_ERR_H2C_MM_0_MASK BIT(4)
-#define GLBL_ERR_STAT_ERR_TRQ_MASK BIT(3)
-#define GLBL_ERR_STAT_ERR_DSC_MASK BIT(2)
-#define GLBL_ERR_STAT_ERR_RAM_DBE_MASK BIT(1)
-#define GLBL_ERR_STAT_ERR_RAM_SBE_MASK BIT(0)
-#define QDMA_S80_HARD_GLBL_ERR_MASK_ADDR 0x24C
-#define GLBL_ERR_RSVD_1_MASK GENMASK(31, 9)
-#define GLBL_ERR_MASK GENMASK(8, 0)
-#define QDMA_S80_HARD_GLBL_DSC_CFG_ADDR 0x250
-#define GLBL_DSC_CFG_RSVD_1_MASK GENMASK(31, 10)
-#define GLBL_DSC_CFG_UNC_OVR_COR_MASK BIT(9)
-#define GLBL_DSC_CFG_CTXT_FER_DIS_MASK BIT(8)
-#define GLBL_DSC_CFG_RSVD_2_MASK GENMASK(7, 6)
-#define GLBL_DSC_CFG_MAXFETCH_MASK GENMASK(5, 3)
-#define GLBL_DSC_CFG_WB_ACC_INT_MASK GENMASK(2, 0)
-#define QDMA_S80_HARD_GLBL_DSC_ERR_STS_ADDR 0x254
-#define GLBL_DSC_ERR_STS_RSVD_1_MASK GENMASK(31, 25)
-#define GLBL_DSC_ERR_STS_SBE_MASK BIT(24)
-#define GLBL_DSC_ERR_STS_DBE_MASK BIT(23)
-#define GLBL_DSC_ERR_STS_RQ_CANCEL_MASK BIT(22)
-#define GLBL_DSC_ERR_STS_DSC_MASK BIT(21)
-#define GLBL_DSC_ERR_STS_DMA_MASK BIT(20)
-#define GLBL_DSC_ERR_STS_FLR_CANCEL_MASK BIT(19)
-#define GLBL_DSC_ERR_STS_RSVD_2_MASK GENMASK(18, 17)
-#define GLBL_DSC_ERR_STS_DAT_POISON_MASK BIT(16)
-#define GLBL_DSC_ERR_STS_TIMEOUT_MASK BIT(9)
-#define GLBL_DSC_ERR_STS_FLR_MASK BIT(5)
-#define GLBL_DSC_ERR_STS_TAG_MASK BIT(4)
-#define GLBL_DSC_ERR_STS_ADDR_MASK BIT(3)
-#define GLBL_DSC_ERR_STS_PARAM_MASK BIT(2)
-#define GLBL_DSC_ERR_STS_UR_CA_MASK BIT(1)
-#define GLBL_DSC_ERR_STS_POISON_MASK BIT(0)
-#define QDMA_S80_HARD_GLBL_DSC_ERR_MSK_ADDR 0x258
-#define GLBL_DSC_ERR_MSK_MASK GENMASK(8, 0)
-#define QDMA_S80_HARD_GLBL_DSC_ERR_LOG0_ADDR 0x25C
-#define GLBL_DSC_ERR_LOG0_VALID_MASK BIT(31)
-#define GLBL_DSC_ERR_LOG0_RSVD_1_MASK GENMASK(30, 29)
-#define GLBL_DSC_ERR_LOG0_QID_MASK GENMASK(28, 17)
-#define GLBL_DSC_ERR_LOG0_SEL_MASK BIT(16)
-#define GLBL_DSC_ERR_LOG0_CIDX_MASK GENMASK(15, 0)
-#define QDMA_S80_HARD_GLBL_DSC_ERR_LOG1_ADDR 0x260
-#define GLBL_DSC_ERR_LOG1_RSVD_1_MASK GENMASK(31, 9)
-#define GLBL_DSC_ERR_LOG1_SUB_TYPE_MASK GENMASK(8, 5)
-#define GLBL_DSC_ERR_LOG1_ERR_TYPE_MASK GENMASK(4, 0)
-#define QDMA_S80_HARD_GLBL_TRQ_ERR_STS_ADDR 0x264
-#define GLBL_TRQ_ERR_STS_RSVD_1_MASK GENMASK(31, 4)
-#define GLBL_TRQ_ERR_STS_TCP_TIMEOUT_MASK BIT(3)
-#define GLBL_TRQ_ERR_STS_VF_ACCESS_ERR_MASK BIT(2)
-#define GLBL_TRQ_ERR_STS_QID_RANGE_MASK BIT(1)
-#define GLBL_TRQ_ERR_STS_UNMAPPED_MASK BIT(0)
-#define QDMA_S80_HARD_GLBL_TRQ_ERR_MSK_ADDR 0x268
-#define GLBL_TRQ_ERR_MSK_MASK GENMASK(31, 0)
-#define QDMA_S80_HARD_GLBL_TRQ_ERR_LOG_ADDR 0x26C
-#define GLBL_TRQ_ERR_LOG_RSVD_1_MASK GENMASK(31, 28)
-#define GLBL_TRQ_ERR_LOG_TARGET_MASK GENMASK(27, 24)
-#define GLBL_TRQ_ERR_LOG_FUNC_MASK GENMASK(23, 16)
-#define GLBL_TRQ_ERR_LOG_ADDRESS_MASK GENMASK(15, 0)
-#define QDMA_S80_HARD_GLBL_DSC_DBG_DAT0_ADDR 0x270
-#define GLBL_DSC_DAT0_RSVD_1_MASK GENMASK(31, 30)
-#define GLBL_DSC_DAT0_CTXT_ARB_DIR_MASK BIT(29)
-#define GLBL_DSC_DAT0_CTXT_ARB_QID_MASK GENMASK(28, 17)
-#define GLBL_DSC_DAT0_CTXT_ARB_REQ_MASK GENMASK(16, 12)
-#define GLBL_DSC_DAT0_IRQ_FIFO_FL_MASK BIT(11)
-#define GLBL_DSC_DAT0_TMSTALL_MASK BIT(10)
-#define GLBL_DSC_DAT0_RRQ_STALL_MASK GENMASK(9, 8)
-#define GLBL_DSC_DAT0_RCP_FIFO_SPC_STALL_MASK GENMASK(7, 6)
-#define GLBL_DSC_DAT0_RRQ_FIFO_SPC_STALL_MASK GENMASK(5, 4)
-#define GLBL_DSC_DAT0_FAB_MRKR_RSP_STALL_MASK GENMASK(3, 2)
-#define GLBL_DSC_DAT0_DSC_OUT_STALL_MASK GENMASK(1, 0)
-#define QDMA_S80_HARD_GLBL_DSC_DBG_DAT1_ADDR 0x274
-#define GLBL_DSC_DAT1_RSVD_1_MASK GENMASK(31, 28)
-#define GLBL_DSC_DAT1_EVT_SPC_C2H_MASK GENMASK(27, 22)
-#define GLBL_DSC_DAT1_EVT_SP_H2C_MASK GENMASK(21, 16)
-#define GLBL_DSC_DAT1_DSC_SPC_C2H_MASK GENMASK(15, 8)
-#define GLBL_DSC_DAT1_DSC_SPC_H2C_MASK GENMASK(7, 0)
-#define QDMA_S80_HARD_TRQ_SEL_FMAP_0_ADDR 0x400
-#define TRQ_SEL_FMAP_0_RSVD_1_MASK GENMASK(31, 23)
-#define TRQ_SEL_FMAP_0_QID_MAX_MASK GENMASK(22, 11)
-#define TRQ_SEL_FMAP_0_QID_BASE_MASK GENMASK(10, 0)
-#define QDMA_S80_HARD_TRQ_SEL_FMAP_1_ADDR 0x404
-#define TRQ_SEL_FMAP_1_RSVD_1_MASK GENMASK(31, 23)
-#define TRQ_SEL_FMAP_1_QID_MAX_MASK GENMASK(22, 11)
-#define TRQ_SEL_FMAP_1_QID_BASE_MASK GENMASK(10, 0)
-#define QDMA_S80_HARD_TRQ_SEL_FMAP_2_ADDR 0x408
-#define TRQ_SEL_FMAP_2_RSVD_1_MASK GENMASK(31, 23)
-#define TRQ_SEL_FMAP_2_QID_MAX_MASK GENMASK(22, 11)
-#define TRQ_SEL_FMAP_2_QID_BASE_MASK GENMASK(10, 0)
-#define QDMA_S80_HARD_TRQ_SEL_FMAP_3_ADDR 0x40C
-#define TRQ_SEL_FMAP_3_RSVD_1_MASK GENMASK(31, 23)
-#define TRQ_SEL_FMAP_3_QID_MAX_MASK GENMASK(22, 11)
-#define TRQ_SEL_FMAP_3_QID_BASE_MASK GENMASK(10, 0)
-#define QDMA_S80_HARD_TRQ_SEL_FMAP_4_ADDR 0x410
-#define TRQ_SEL_FMAP_4_RSVD_1_MASK GENMASK(31, 23)
-#define TRQ_SEL_FMAP_4_QID_MAX_MASK GENMASK(22, 11)
-#define TRQ_SEL_FMAP_4_QID_BASE_MASK GENMASK(10, 0)
-#define QDMA_S80_HARD_TRQ_SEL_FMAP_5_ADDR 0x414
-#define TRQ_SEL_FMAP_5_RSVD_1_MASK GENMASK(31, 23)
-#define TRQ_SEL_FMAP_5_QID_MAX_MASK GENMASK(22, 11)
-#define TRQ_SEL_FMAP_5_QID_BASE_MASK GENMASK(10, 0)
-#define QDMA_S80_HARD_TRQ_SEL_FMAP_6_ADDR 0x418
-#define TRQ_SEL_FMAP_6_RSVD_1_MASK GENMASK(31, 23)
-#define TRQ_SEL_FMAP_6_QID_MAX_MASK GENMASK(22, 11)
-#define TRQ_SEL_FMAP_6_QID_BASE_MASK GENMASK(10, 0)
-#define QDMA_S80_HARD_TRQ_SEL_FMAP_7_ADDR 0x41C
-#define TRQ_SEL_FMAP_7_RSVD_1_MASK GENMASK(31, 23)
-#define TRQ_SEL_FMAP_7_QID_MAX_MASK GENMASK(22, 11)
-#define TRQ_SEL_FMAP_7_QID_BASE_MASK GENMASK(10, 0)
-#define QDMA_S80_HARD_TRQ_SEL_FMAP_8_ADDR 0x420
-#define TRQ_SEL_FMAP_8_RSVD_1_MASK GENMASK(31, 23)
-#define TRQ_SEL_FMAP_8_QID_MAX_MASK GENMASK(22, 11)
-#define TRQ_SEL_FMAP_8_QID_BASE_MASK GENMASK(10, 0)
-#define QDMA_S80_HARD_TRQ_SEL_FMAP_9_ADDR 0x424
-#define TRQ_SEL_FMAP_9_RSVD_1_MASK GENMASK(31, 23)
-#define TRQ_SEL_FMAP_9_QID_MAX_MASK GENMASK(22, 11)
-#define TRQ_SEL_FMAP_9_QID_BASE_MASK GENMASK(10, 0)
-#define QDMA_S80_HARD_TRQ_SEL_FMAP_A_ADDR 0x428
-#define TRQ_SEL_FMAP_A_RSVD_1_MASK GENMASK(31, 23)
-#define TRQ_SEL_FMAP_A_QID_MAX_MASK GENMASK(22, 11)
-#define TRQ_SEL_FMAP_A_QID_BASE_MASK GENMASK(10, 0)
-#define QDMA_S80_HARD_TRQ_SEL_FMAP_B_ADDR 0x42C
-#define TRQ_SEL_FMAP_B_RSVD_1_MASK GENMASK(31, 23)
-#define TRQ_SEL_FMAP_B_QID_MAX_MASK GENMASK(22, 11)
-#define TRQ_SEL_FMAP_B_QID_BASE_MASK GENMASK(10, 0)
-#define QDMA_S80_HARD_TRQ_SEL_FMAP_D_ADDR 0x430
-#define TRQ_SEL_FMAP_D_RSVD_1_MASK GENMASK(31, 23)
-#define TRQ_SEL_FMAP_D_QID_MAX_MASK GENMASK(22, 11)
-#define TRQ_SEL_FMAP_D_QID_BASE_MASK GENMASK(10, 0)
-#define QDMA_S80_HARD_TRQ_SEL_FMAP_E_ADDR 0x434
-#define TRQ_SEL_FMAP_E_RSVD_1_MASK GENMASK(31, 23)
-#define TRQ_SEL_FMAP_E_QID_MAX_MASK GENMASK(22, 11)
-#define TRQ_SEL_FMAP_E_QID_BASE_MASK GENMASK(10, 0)
-#define QDMA_S80_HARD_TRQ_SEL_FMAP_F_ADDR 0x438
-#define TRQ_SEL_FMAP_F_RSVD_1_MASK GENMASK(31, 23)
-#define TRQ_SEL_FMAP_F_QID_MAX_MASK GENMASK(22, 11)
-#define TRQ_SEL_FMAP_F_QID_BASE_MASK GENMASK(10, 0)
-#define QDMA_S80_HARD_TRQ_SEL_FMAP_10_ADDR 0x43C
-#define TRQ_SEL_FMAP_10_RSVD_1_MASK GENMASK(31, 23)
-#define TRQ_SEL_FMAP_10_QID_MAX_MASK GENMASK(22, 11)
-#define TRQ_SEL_FMAP_10_QID_BASE_MASK GENMASK(10, 0)
-#define QDMA_S80_HARD_TRQ_SEL_FMAP_11_ADDR 0x440
-#define TRQ_SEL_FMAP_11_RSVD_1_MASK GENMASK(31, 23)
-#define TRQ_SEL_FMAP_11_QID_MAX_MASK GENMASK(22, 11)
-#define TRQ_SEL_FMAP_11_QID_BASE_MASK GENMASK(10, 0)
-#define QDMA_S80_HARD_TRQ_SEL_FMAP_12_ADDR 0x444
-#define TRQ_SEL_FMAP_12_RSVD_1_MASK GENMASK(31, 23)
-#define TRQ_SEL_FMAP_12_QID_MAX_MASK GENMASK(22, 11)
-#define TRQ_SEL_FMAP_12_QID_BASE_MASK GENMASK(10, 0)
-#define QDMA_S80_HARD_TRQ_SEL_FMAP_13_ADDR 0x448
-#define TRQ_SEL_FMAP_13_RSVD_1_MASK GENMASK(31, 23)
-#define TRQ_SEL_FMAP_13_QID_MAX_MASK GENMASK(22, 11)
-#define TRQ_SEL_FMAP_13_QID_BASE_MASK GENMASK(10, 0)
-#define QDMA_S80_HARD_TRQ_SEL_FMAP_14_ADDR 0x44C
-#define TRQ_SEL_FMAP_14_RSVD_1_MASK GENMASK(31, 23)
-#define TRQ_SEL_FMAP_14_QID_MAX_MASK GENMASK(22, 11)
-#define TRQ_SEL_FMAP_14_QID_BASE_MASK GENMASK(10, 0)
-#define QDMA_S80_HARD_TRQ_SEL_FMAP_15_ADDR 0x450
-#define TRQ_SEL_FMAP_15_RSVD_1_MASK GENMASK(31, 23)
-#define TRQ_SEL_FMAP_15_QID_MAX_MASK GENMASK(22, 11)
-#define TRQ_SEL_FMAP_15_QID_BASE_MASK GENMASK(10, 0)
-#define QDMA_S80_HARD_TRQ_SEL_FMAP_16_ADDR 0x454
-#define TRQ_SEL_FMAP_16_RSVD_1_MASK GENMASK(31, 23)
-#define TRQ_SEL_FMAP_16_QID_MAX_MASK GENMASK(22, 11)
-#define TRQ_SEL_FMAP_16_QID_BASE_MASK GENMASK(10, 0)
-#define QDMA_S80_HARD_TRQ_SEL_FMAP_17_ADDR 0x458
-#define TRQ_SEL_FMAP_17_RSVD_1_MASK GENMASK(31, 23)
-#define TRQ_SEL_FMAP_17_QID_MAX_MASK GENMASK(22, 11)
-#define TRQ_SEL_FMAP_17_QID_BASE_MASK GENMASK(10, 0)
-#define QDMA_S80_HARD_TRQ_SEL_FMAP_18_ADDR 0x45C
-#define TRQ_SEL_FMAP_18_RSVD_1_MASK GENMASK(31, 23)
-#define TRQ_SEL_FMAP_18_QID_MAX_MASK GENMASK(22, 11)
-#define TRQ_SEL_FMAP_18_QID_BASE_MASK GENMASK(10, 0)
-#define QDMA_S80_HARD_TRQ_SEL_FMAP_19_ADDR 0x460
-#define TRQ_SEL_FMAP_19_RSVD_1_MASK GENMASK(31, 23)
-#define TRQ_SEL_FMAP_19_QID_MAX_MASK GENMASK(22, 11)
-#define TRQ_SEL_FMAP_19_QID_BASE_MASK GENMASK(10, 0)
-#define QDMA_S80_HARD_TRQ_SEL_FMAP_1A_ADDR 0x464
-#define TRQ_SEL_FMAP_1A_RSVD_1_MASK GENMASK(31, 23)
-#define TRQ_SEL_FMAP_1A_QID_MAX_MASK GENMASK(22, 11)
-#define TRQ_SEL_FMAP_1A_QID_BASE_MASK GENMASK(10, 0)
-#define QDMA_S80_HARD_TRQ_SEL_FMAP_1B_ADDR 0x468
-#define TRQ_SEL_FMAP_1B_RSVD_1_MASK GENMASK(31, 23)
-#define TRQ_SEL_FMAP_1B_QID_MAX_MASK GENMASK(22, 11)
-#define TRQ_SEL_FMAP_1B_QID_BASE_MASK GENMASK(10, 0)
-#define QDMA_S80_HARD_TRQ_SEL_FMAP_1C_ADDR 0x46C
-#define TRQ_SEL_FMAP_1C_RSVD_1_MASK GENMASK(31, 23)
-#define TRQ_SEL_FMAP_1C_QID_MAX_MASK GENMASK(22, 11)
-#define TRQ_SEL_FMAP_1C_QID_BASE_MASK GENMASK(10, 0)
-#define QDMA_S80_HARD_TRQ_SEL_FMAP_1D_ADDR 0x470
-#define TRQ_SEL_FMAP_1D_RSVD_1_MASK GENMASK(31, 23)
-#define TRQ_SEL_FMAP_1D_QID_MAX_MASK GENMASK(22, 11)
-#define TRQ_SEL_FMAP_1D_QID_BASE_MASK GENMASK(10, 0)
-#define QDMA_S80_HARD_TRQ_SEL_FMAP_1E_ADDR 0x474
-#define TRQ_SEL_FMAP_1E_RSVD_1_MASK GENMASK(31, 23)
-#define TRQ_SEL_FMAP_1E_QID_MAX_MASK GENMASK(22, 11)
-#define TRQ_SEL_FMAP_1E_QID_BASE_MASK GENMASK(10, 0)
-#define QDMA_S80_HARD_TRQ_SEL_FMAP_1F_ADDR 0x478
-#define TRQ_SEL_FMAP_1F_RSVD_1_MASK GENMASK(31, 23)
-#define TRQ_SEL_FMAP_1F_QID_MAX_MASK GENMASK(22, 11)
-#define TRQ_SEL_FMAP_1F_QID_BASE_MASK GENMASK(10, 0)
-#define QDMA_S80_HARD_TRQ_SEL_FMAP_20_ADDR 0x47C
-#define TRQ_SEL_FMAP_20_RSVD_1_MASK GENMASK(31, 23)
-#define TRQ_SEL_FMAP_20_QID_MAX_MASK GENMASK(22, 11)
-#define TRQ_SEL_FMAP_20_QID_BASE_MASK GENMASK(10, 0)
-#define QDMA_S80_HARD_TRQ_SEL_FMAP_21_ADDR 0x480
-#define TRQ_SEL_FMAP_21_RSVD_1_MASK GENMASK(31, 23)
-#define TRQ_SEL_FMAP_21_QID_MAX_MASK GENMASK(22, 11)
-#define TRQ_SEL_FMAP_21_QID_BASE_MASK GENMASK(10, 0)
-#define QDMA_S80_HARD_TRQ_SEL_FMAP_22_ADDR 0x484
-#define TRQ_SEL_FMAP_22_RSVD_1_MASK GENMASK(31, 23)
-#define TRQ_SEL_FMAP_22_QID_MAX_MASK GENMASK(22, 11)
-#define TRQ_SEL_FMAP_22_QID_BASE_MASK GENMASK(10, 0)
-#define QDMA_S80_HARD_TRQ_SEL_FMAP_23_ADDR 0x488
-#define TRQ_SEL_FMAP_23_RSVD_1_MASK GENMASK(31, 23)
-#define TRQ_SEL_FMAP_23_QID_MAX_MASK GENMASK(22, 11)
-#define TRQ_SEL_FMAP_23_QID_BASE_MASK GENMASK(10, 0)
-#define QDMA_S80_HARD_TRQ_SEL_FMAP_24_ADDR 0x48C
-#define TRQ_SEL_FMAP_24_RSVD_1_MASK GENMASK(31, 23)
-#define TRQ_SEL_FMAP_24_QID_MAX_MASK GENMASK(22, 11)
-#define TRQ_SEL_FMAP_24_QID_BASE_MASK GENMASK(10, 0)
-#define QDMA_S80_HARD_TRQ_SEL_FMAP_25_ADDR 0x490
-#define TRQ_SEL_FMAP_25_RSVD_1_MASK GENMASK(31, 23)
-#define TRQ_SEL_FMAP_25_QID_MAX_MASK GENMASK(22, 11)
-#define TRQ_SEL_FMAP_25_QID_BASE_MASK GENMASK(10, 0)
-#define QDMA_S80_HARD_TRQ_SEL_FMAP_26_ADDR 0x494
-#define TRQ_SEL_FMAP_26_RSVD_1_MASK GENMASK(31, 23)
-#define TRQ_SEL_FMAP_26_QID_MAX_MASK GENMASK(22, 11)
-#define TRQ_SEL_FMAP_26_QID_BASE_MASK GENMASK(10, 0)
-#define QDMA_S80_HARD_TRQ_SEL_FMAP_27_ADDR 0x498
-#define TRQ_SEL_FMAP_27_RSVD_1_MASK GENMASK(31, 23)
-#define TRQ_SEL_FMAP_27_QID_MAX_MASK GENMASK(22, 11)
-#define TRQ_SEL_FMAP_27_QID_BASE_MASK GENMASK(10, 0)
-#define QDMA_S80_HARD_TRQ_SEL_FMAP_28_ADDR 0x49C
-#define TRQ_SEL_FMAP_28_RSVD_1_MASK GENMASK(31, 23)
-#define TRQ_SEL_FMAP_28_QID_MAX_MASK GENMASK(22, 11)
-#define TRQ_SEL_FMAP_28_QID_BASE_MASK GENMASK(10, 0)
-#define QDMA_S80_HARD_TRQ_SEL_FMAP_29_ADDR 0x4A0
-#define TRQ_SEL_FMAP_29_RSVD_1_MASK GENMASK(31, 23)
-#define TRQ_SEL_FMAP_29_QID_MAX_MASK GENMASK(22, 11)
-#define TRQ_SEL_FMAP_29_QID_BASE_MASK GENMASK(10, 0)
-#define QDMA_S80_HARD_TRQ_SEL_FMAP_2A_ADDR 0x4A4
-#define TRQ_SEL_FMAP_2A_RSVD_1_MASK GENMASK(31, 23)
-#define TRQ_SEL_FMAP_2A_QID_MAX_MASK GENMASK(22, 11)
-#define TRQ_SEL_FMAP_2A_QID_BASE_MASK GENMASK(10, 0)
-#define QDMA_S80_HARD_TRQ_SEL_FMAP_2B_ADDR 0x4A8
-#define TRQ_SEL_FMAP_2B_RSVD_1_MASK GENMASK(31, 23)
-#define TRQ_SEL_FMAP_2B_QID_MAX_MASK GENMASK(22, 11)
-#define TRQ_SEL_FMAP_2B_QID_BASE_MASK GENMASK(10, 0)
-#define QDMA_S80_HARD_TRQ_SEL_FMAP_2C_ADDR 0x4AC
-#define TRQ_SEL_FMAP_2C_RSVD_1_MASK GENMASK(31, 23)
-#define TRQ_SEL_FMAP_2C_QID_MAX_MASK GENMASK(22, 11)
-#define TRQ_SEL_FMAP_2C_QID_BASE_MASK GENMASK(10, 0)
-#define QDMA_S80_HARD_TRQ_SEL_FMAP_2D_ADDR 0x4B0
-#define TRQ_SEL_FMAP_2D_RSVD_1_MASK GENMASK(31, 23)
-#define TRQ_SEL_FMAP_2D_QID_MAX_MASK GENMASK(22, 11)
-#define TRQ_SEL_FMAP_2D_QID_BASE_MASK GENMASK(10, 0)
-#define QDMA_S80_HARD_TRQ_SEL_FMAP_2E_ADDR 0x4B4
-#define TRQ_SEL_FMAP_2E_RSVD_1_MASK GENMASK(31, 23)
-#define TRQ_SEL_FMAP_2E_QID_MAX_MASK GENMASK(22, 11)
-#define TRQ_SEL_FMAP_2E_QID_BASE_MASK GENMASK(10, 0)
-#define QDMA_S80_HARD_TRQ_SEL_FMAP_2F_ADDR 0x4B8
-#define TRQ_SEL_FMAP_2F_RSVD_1_MASK GENMASK(31, 23)
-#define TRQ_SEL_FMAP_2F_QID_MAX_MASK GENMASK(22, 11)
-#define TRQ_SEL_FMAP_2F_QID_BASE_MASK GENMASK(10, 0)
-#define QDMA_S80_HARD_TRQ_SEL_FMAP_30_ADDR 0x4BC
-#define TRQ_SEL_FMAP_30_RSVD_1_MASK GENMASK(31, 23)
-#define TRQ_SEL_FMAP_30_QID_MAX_MASK GENMASK(22, 11)
-#define TRQ_SEL_FMAP_30_QID_BASE_MASK GENMASK(10, 0)
-#define QDMA_S80_HARD_TRQ_SEL_FMAP_31_ADDR 0x4D0
-#define TRQ_SEL_FMAP_31_RSVD_1_MASK GENMASK(31, 23)
-#define TRQ_SEL_FMAP_31_QID_MAX_MASK GENMASK(22, 11)
-#define TRQ_SEL_FMAP_31_QID_BASE_MASK GENMASK(10, 0)
-#define QDMA_S80_HARD_TRQ_SEL_FMAP_32_ADDR 0x4D4
-#define TRQ_SEL_FMAP_32_RSVD_1_MASK GENMASK(31, 23)
-#define TRQ_SEL_FMAP_32_QID_MAX_MASK GENMASK(22, 11)
-#define TRQ_SEL_FMAP_32_QID_BASE_MASK GENMASK(10, 0)
-#define QDMA_S80_HARD_TRQ_SEL_FMAP_33_ADDR 0x4D8
-#define TRQ_SEL_FMAP_33_RSVD_1_MASK GENMASK(31, 23)
-#define TRQ_SEL_FMAP_33_QID_MAX_MASK GENMASK(22, 11)
-#define TRQ_SEL_FMAP_33_QID_BASE_MASK GENMASK(10, 0)
-#define QDMA_S80_HARD_TRQ_SEL_FMAP_34_ADDR 0x4DC
-#define TRQ_SEL_FMAP_34_RSVD_1_MASK GENMASK(31, 23)
-#define TRQ_SEL_FMAP_34_QID_MAX_MASK GENMASK(22, 11)
-#define TRQ_SEL_FMAP_34_QID_BASE_MASK GENMASK(10, 0)
-#define QDMA_S80_HARD_TRQ_SEL_FMAP_35_ADDR 0x4E0
-#define TRQ_SEL_FMAP_35_RSVD_1_MASK GENMASK(31, 23)
-#define TRQ_SEL_FMAP_35_QID_MAX_MASK GENMASK(22, 11)
-#define TRQ_SEL_FMAP_35_QID_BASE_MASK GENMASK(10, 0)
-#define QDMA_S80_HARD_TRQ_SEL_FMAP_36_ADDR 0x4E4
-#define TRQ_SEL_FMAP_36_RSVD_1_MASK GENMASK(31, 23)
-#define TRQ_SEL_FMAP_36_QID_MAX_MASK GENMASK(22, 11)
-#define TRQ_SEL_FMAP_36_QID_BASE_MASK GENMASK(10, 0)
-#define QDMA_S80_HARD_TRQ_SEL_FMAP_37_ADDR 0x4E8
-#define TRQ_SEL_FMAP_37_RSVD_1_MASK GENMASK(31, 23)
-#define TRQ_SEL_FMAP_37_QID_MAX_MASK GENMASK(22, 11)
-#define TRQ_SEL_FMAP_37_QID_BASE_MASK GENMASK(10, 0)
-#define QDMA_S80_HARD_TRQ_SEL_FMAP_38_ADDR 0x4EC
-#define TRQ_SEL_FMAP_38_RSVD_1_MASK GENMASK(31, 23)
-#define TRQ_SEL_FMAP_38_QID_MAX_MASK GENMASK(22, 11)
-#define TRQ_SEL_FMAP_38_QID_BASE_MASK GENMASK(10, 0)
-#define QDMA_S80_HARD_TRQ_SEL_FMAP_39_ADDR 0x4F0
-#define TRQ_SEL_FMAP_39_RSVD_1_MASK GENMASK(31, 23)
-#define TRQ_SEL_FMAP_39_QID_MAX_MASK GENMASK(22, 11)
-#define TRQ_SEL_FMAP_39_QID_BASE_MASK GENMASK(10, 0)
-#define QDMA_S80_HARD_TRQ_SEL_FMAP_3A_ADDR 0x4F4
-#define TRQ_SEL_FMAP_3A_RSVD_1_MASK GENMASK(31, 23)
-#define TRQ_SEL_FMAP_3A_QID_MAX_MASK GENMASK(22, 11)
-#define TRQ_SEL_FMAP_3A_QID_BASE_MASK GENMASK(10, 0)
-#define QDMA_S80_HARD_TRQ_SEL_FMAP_3B_ADDR 0x4F8
-#define TRQ_SEL_FMAP_3B_RSVD_1_MASK GENMASK(31, 23)
-#define TRQ_SEL_FMAP_3B_QID_MAX_MASK GENMASK(22, 11)
-#define TRQ_SEL_FMAP_3B_QID_BASE_MASK GENMASK(10, 0)
-#define QDMA_S80_HARD_TRQ_SEL_FMAP_3C_ADDR 0x4FC
-#define TRQ_SEL_FMAP_3C_RSVD_1_MASK GENMASK(31, 23)
-#define TRQ_SEL_FMAP_3C_QID_MAX_MASK GENMASK(22, 11)
-#define TRQ_SEL_FMAP_3C_QID_BASE_MASK GENMASK(10, 0)
-#define QDMA_S80_HARD_TRQ_SEL_FMAP_3D_ADDR 0x500
-#define TRQ_SEL_FMAP_3D_RSVD_1_MASK GENMASK(31, 23)
-#define TRQ_SEL_FMAP_3D_QID_MAX_MASK GENMASK(22, 11)
-#define TRQ_SEL_FMAP_3D_QID_BASE_MASK GENMASK(10, 0)
-#define QDMA_S80_HARD_TRQ_SEL_FMAP_3E_ADDR 0x504
-#define TRQ_SEL_FMAP_3E_RSVD_1_MASK GENMASK(31, 23)
-#define TRQ_SEL_FMAP_3E_QID_MAX_MASK GENMASK(22, 11)
-#define TRQ_SEL_FMAP_3E_QID_BASE_MASK GENMASK(10, 0)
-#define QDMA_S80_HARD_TRQ_SEL_FMAP_3F_ADDR 0x508
-#define TRQ_SEL_FMAP_3F_RSVD_1_MASK GENMASK(31, 23)
-#define TRQ_SEL_FMAP_3F_QID_MAX_MASK GENMASK(22, 11)
-#define TRQ_SEL_FMAP_3F_QID_BASE_MASK GENMASK(10, 0)
-#define QDMA_S80_HARD_TRQ_SEL_FMAP_40_ADDR 0x50C
-#define TRQ_SEL_FMAP_40_RSVD_1_MASK GENMASK(31, 23)
-#define TRQ_SEL_FMAP_40_QID_MAX_MASK GENMASK(22, 11)
-#define TRQ_SEL_FMAP_40_QID_BASE_MASK GENMASK(10, 0)
-#define QDMA_S80_HARD_TRQ_SEL_FMAP_41_ADDR 0x510
-#define TRQ_SEL_FMAP_41_RSVD_1_MASK GENMASK(31, 23)
-#define TRQ_SEL_FMAP_41_QID_MAX_MASK GENMASK(22, 11)
-#define TRQ_SEL_FMAP_41_QID_BASE_MASK GENMASK(10, 0)
-#define QDMA_S80_HARD_TRQ_SEL_FMAP_42_ADDR 0x514
-#define TRQ_SEL_FMAP_42_RSVD_1_MASK GENMASK(31, 23)
-#define TRQ_SEL_FMAP_42_QID_MAX_MASK GENMASK(22, 11)
-#define TRQ_SEL_FMAP_42_QID_BASE_MASK GENMASK(10, 0)
-#define QDMA_S80_HARD_TRQ_SEL_FMAP_43_ADDR 0x518
-#define TRQ_SEL_FMAP_43_RSVD_1_MASK GENMASK(31, 23)
-#define TRQ_SEL_FMAP_43_QID_MAX_MASK GENMASK(22, 11)
-#define TRQ_SEL_FMAP_43_QID_BASE_MASK GENMASK(10, 0)
-#define QDMA_S80_HARD_TRQ_SEL_FMAP_44_ADDR 0x51C
-#define TRQ_SEL_FMAP_44_RSVD_1_MASK GENMASK(31, 23)
-#define TRQ_SEL_FMAP_44_QID_MAX_MASK GENMASK(22, 11)
-#define TRQ_SEL_FMAP_44_QID_BASE_MASK GENMASK(10, 0)
-#define QDMA_S80_HARD_TRQ_SEL_FMAP_45_ADDR 0x520
-#define TRQ_SEL_FMAP_45_RSVD_1_MASK GENMASK(31, 23)
-#define TRQ_SEL_FMAP_45_QID_MAX_MASK GENMASK(22, 11)
-#define TRQ_SEL_FMAP_45_QID_BASE_MASK GENMASK(10, 0)
-#define QDMA_S80_HARD_TRQ_SEL_FMAP_46_ADDR 0x524
-#define TRQ_SEL_FMAP_46_RSVD_1_MASK GENMASK(31, 23)
-#define TRQ_SEL_FMAP_46_QID_MAX_MASK GENMASK(22, 11)
-#define TRQ_SEL_FMAP_46_QID_BASE_MASK GENMASK(10, 0)
-#define QDMA_S80_HARD_TRQ_SEL_FMAP_47_ADDR 0x528
-#define TRQ_SEL_FMAP_47_RSVD_1_MASK GENMASK(31, 23)
-#define TRQ_SEL_FMAP_47_QID_MAX_MASK GENMASK(22, 11)
-#define TRQ_SEL_FMAP_47_QID_BASE_MASK GENMASK(10, 0)
-#define QDMA_S80_HARD_TRQ_SEL_FMAP_48_ADDR 0x52C
-#define TRQ_SEL_FMAP_48_RSVD_1_MASK GENMASK(31, 23)
-#define TRQ_SEL_FMAP_48_QID_MAX_MASK GENMASK(22, 11)
-#define TRQ_SEL_FMAP_48_QID_BASE_MASK GENMASK(10, 0)
-#define QDMA_S80_HARD_TRQ_SEL_FMAP_49_ADDR 0x530
-#define TRQ_SEL_FMAP_49_RSVD_1_MASK GENMASK(31, 23)
-#define TRQ_SEL_FMAP_49_QID_MAX_MASK GENMASK(22, 11)
-#define TRQ_SEL_FMAP_49_QID_BASE_MASK GENMASK(10, 0)
-#define QDMA_S80_HARD_TRQ_SEL_FMAP_4A_ADDR 0x534
-#define TRQ_SEL_FMAP_4A_RSVD_1_MASK GENMASK(31, 23)
-#define TRQ_SEL_FMAP_4A_QID_MAX_MASK GENMASK(22, 11)
-#define TRQ_SEL_FMAP_4A_QID_BASE_MASK GENMASK(10, 0)
-#define QDMA_S80_HARD_TRQ_SEL_FMAP_4B_ADDR 0x538
-#define TRQ_SEL_FMAP_4B_RSVD_1_MASK GENMASK(31, 23)
-#define TRQ_SEL_FMAP_4B_QID_MAX_MASK GENMASK(22, 11)
-#define TRQ_SEL_FMAP_4B_QID_BASE_MASK GENMASK(10, 0)
-#define QDMA_S80_HARD_TRQ_SEL_FMAP_4C_ADDR 0x53C
-#define TRQ_SEL_FMAP_4C_RSVD_1_MASK GENMASK(31, 23)
-#define TRQ_SEL_FMAP_4C_QID_MAX_MASK GENMASK(22, 11)
-#define TRQ_SEL_FMAP_4C_QID_BASE_MASK GENMASK(10, 0)
-#define QDMA_S80_HARD_TRQ_SEL_FMAP_4D_ADDR 0x540
-#define TRQ_SEL_FMAP_4D_RSVD_1_MASK GENMASK(31, 23)
-#define TRQ_SEL_FMAP_4D_QID_MAX_MASK GENMASK(22, 11)
-#define TRQ_SEL_FMAP_4D_QID_BASE_MASK GENMASK(10, 0)
-#define QDMA_S80_HARD_TRQ_SEL_FMAP_4E_ADDR 0x544
-#define TRQ_SEL_FMAP_4E_RSVD_1_MASK GENMASK(31, 23)
-#define TRQ_SEL_FMAP_4E_QID_MAX_MASK GENMASK(22, 11)
-#define TRQ_SEL_FMAP_4E_QID_BASE_MASK GENMASK(10, 0)
-#define QDMA_S80_HARD_TRQ_SEL_FMAP_4F_ADDR 0x548
-#define TRQ_SEL_FMAP_4F_RSVD_1_MASK GENMASK(31, 23)
-#define TRQ_SEL_FMAP_4F_QID_MAX_MASK GENMASK(22, 11)
-#define TRQ_SEL_FMAP_4F_QID_BASE_MASK GENMASK(10, 0)
-#define QDMA_S80_HARD_TRQ_SEL_FMAP_50_ADDR 0x54C
-#define TRQ_SEL_FMAP_50_RSVD_1_MASK GENMASK(31, 23)
-#define TRQ_SEL_FMAP_50_QID_MAX_MASK GENMASK(22, 11)
-#define TRQ_SEL_FMAP_50_QID_BASE_MASK GENMASK(10, 0)
-#define QDMA_S80_HARD_TRQ_SEL_FMAP_51_ADDR 0x550
-#define TRQ_SEL_FMAP_51_RSVD_1_MASK GENMASK(31, 23)
-#define TRQ_SEL_FMAP_51_QID_MAX_MASK GENMASK(22, 11)
-#define TRQ_SEL_FMAP_51_QID_BASE_MASK GENMASK(10, 0)
-#define QDMA_S80_HARD_TRQ_SEL_FMAP_52_ADDR 0x554
-#define TRQ_SEL_FMAP_52_RSVD_1_MASK GENMASK(31, 23)
-#define TRQ_SEL_FMAP_52_QID_MAX_MASK GENMASK(22, 11)
-#define TRQ_SEL_FMAP_52_QID_BASE_MASK GENMASK(10, 0)
-#define QDMA_S80_HARD_TRQ_SEL_FMAP_53_ADDR 0x558
-#define TRQ_SEL_FMAP_53_RSVD_1_MASK GENMASK(31, 23)
-#define TRQ_SEL_FMAP_53_QID_MAX_MASK GENMASK(22, 11)
-#define TRQ_SEL_FMAP_53_QID_BASE_MASK GENMASK(10, 0)
-#define QDMA_S80_HARD_TRQ_SEL_FMAP_54_ADDR 0x55C
-#define TRQ_SEL_FMAP_54_RSVD_1_MASK GENMASK(31, 23)
-#define TRQ_SEL_FMAP_54_QID_MAX_MASK GENMASK(22, 11)
-#define TRQ_SEL_FMAP_54_QID_BASE_MASK GENMASK(10, 0)
-#define QDMA_S80_HARD_TRQ_SEL_FMAP_55_ADDR 0x560
-#define TRQ_SEL_FMAP_55_RSVD_1_MASK GENMASK(31, 23)
-#define TRQ_SEL_FMAP_55_QID_MAX_MASK GENMASK(22, 11)
-#define TRQ_SEL_FMAP_55_QID_BASE_MASK GENMASK(10, 0)
-#define QDMA_S80_HARD_TRQ_SEL_FMAP_56_ADDR 0x564
-#define TRQ_SEL_FMAP_56_RSVD_1_MASK GENMASK(31, 23)
-#define TRQ_SEL_FMAP_56_QID_MAX_MASK GENMASK(22, 11)
-#define TRQ_SEL_FMAP_56_QID_BASE_MASK GENMASK(10, 0)
-#define QDMA_S80_HARD_TRQ_SEL_FMAP_57_ADDR 0x568
-#define TRQ_SEL_FMAP_57_RSVD_1_MASK GENMASK(31, 23)
-#define TRQ_SEL_FMAP_57_QID_MAX_MASK GENMASK(22, 11)
-#define TRQ_SEL_FMAP_57_QID_BASE_MASK GENMASK(10, 0)
-#define QDMA_S80_HARD_TRQ_SEL_FMAP_58_ADDR 0x56C
-#define TRQ_SEL_FMAP_58_RSVD_1_MASK GENMASK(31, 23)
-#define TRQ_SEL_FMAP_58_QID_MAX_MASK GENMASK(22, 11)
-#define TRQ_SEL_FMAP_58_QID_BASE_MASK GENMASK(10, 0)
-#define QDMA_S80_HARD_TRQ_SEL_FMAP_59_ADDR 0x570
-#define TRQ_SEL_FMAP_59_RSVD_1_MASK GENMASK(31, 23)
-#define TRQ_SEL_FMAP_59_QID_MAX_MASK GENMASK(22, 11)
-#define TRQ_SEL_FMAP_59_QID_BASE_MASK GENMASK(10, 0)
-#define QDMA_S80_HARD_TRQ_SEL_FMAP_5A_ADDR 0x574
-#define TRQ_SEL_FMAP_5A_RSVD_1_MASK GENMASK(31, 23)
-#define TRQ_SEL_FMAP_5A_QID_MAX_MASK GENMASK(22, 11)
-#define TRQ_SEL_FMAP_5A_QID_BASE_MASK GENMASK(10, 0)
-#define QDMA_S80_HARD_TRQ_SEL_FMAP_5B_ADDR 0x578
-#define TRQ_SEL_FMAP_5B_RSVD_1_MASK GENMASK(31, 23)
-#define TRQ_SEL_FMAP_5B_QID_MAX_MASK GENMASK(22, 11)
-#define TRQ_SEL_FMAP_5B_QID_BASE_MASK GENMASK(10, 0)
-#define QDMA_S80_HARD_TRQ_SEL_FMAP_5C_ADDR 0x57C
-#define TRQ_SEL_FMAP_5C_RSVD_1_MASK GENMASK(31, 23)
-#define TRQ_SEL_FMAP_5C_QID_MAX_MASK GENMASK(22, 11)
-#define TRQ_SEL_FMAP_5C_QID_BASE_MASK GENMASK(10, 0)
-#define QDMA_S80_HARD_TRQ_SEL_FMAP_5D_ADDR 0x580
-#define TRQ_SEL_FMAP_5D_RSVD_1_MASK GENMASK(31, 23)
-#define TRQ_SEL_FMAP_5D_QID_MAX_MASK GENMASK(22, 11)
-#define TRQ_SEL_FMAP_5D_QID_BASE_MASK GENMASK(10, 0)
-#define QDMA_S80_HARD_TRQ_SEL_FMAP_5E_ADDR 0x584
-#define TRQ_SEL_FMAP_5E_RSVD_1_MASK GENMASK(31, 23)
-#define TRQ_SEL_FMAP_5E_QID_MAX_MASK GENMASK(22, 11)
-#define TRQ_SEL_FMAP_5E_QID_BASE_MASK GENMASK(10, 0)
-#define QDMA_S80_HARD_TRQ_SEL_FMAP_5F_ADDR 0x588
-#define TRQ_SEL_FMAP_5F_RSVD_1_MASK GENMASK(31, 23)
-#define TRQ_SEL_FMAP_5F_QID_MAX_MASK GENMASK(22, 11)
-#define TRQ_SEL_FMAP_5F_QID_BASE_MASK GENMASK(10, 0)
-#define QDMA_S80_HARD_TRQ_SEL_FMAP_60_ADDR 0x58C
-#define TRQ_SEL_FMAP_60_RSVD_1_MASK GENMASK(31, 23)
-#define TRQ_SEL_FMAP_60_QID_MAX_MASK GENMASK(22, 11)
-#define TRQ_SEL_FMAP_60_QID_BASE_MASK GENMASK(10, 0)
-#define QDMA_S80_HARD_TRQ_SEL_FMAP_61_ADDR 0x590
-#define TRQ_SEL_FMAP_61_RSVD_1_MASK GENMASK(31, 23)
-#define TRQ_SEL_FMAP_61_QID_MAX_MASK GENMASK(22, 11)
-#define TRQ_SEL_FMAP_61_QID_BASE_MASK GENMASK(10, 0)
-#define QDMA_S80_HARD_TRQ_SEL_FMAP_62_ADDR 0x594
-#define TRQ_SEL_FMAP_62_RSVD_1_MASK GENMASK(31, 23)
-#define TRQ_SEL_FMAP_62_QID_MAX_MASK GENMASK(22, 11)
-#define TRQ_SEL_FMAP_62_QID_BASE_MASK GENMASK(10, 0)
-#define QDMA_S80_HARD_TRQ_SEL_FMAP_63_ADDR 0x598
-#define TRQ_SEL_FMAP_63_RSVD_1_MASK GENMASK(31, 23)
-#define TRQ_SEL_FMAP_63_QID_MAX_MASK GENMASK(22, 11)
-#define TRQ_SEL_FMAP_63_QID_BASE_MASK GENMASK(10, 0)
-#define QDMA_S80_HARD_TRQ_SEL_FMAP_64_ADDR 0x59C
-#define TRQ_SEL_FMAP_64_RSVD_1_MASK GENMASK(31, 23)
-#define TRQ_SEL_FMAP_64_QID_MAX_MASK GENMASK(22, 11)
-#define TRQ_SEL_FMAP_64_QID_BASE_MASK GENMASK(10, 0)
-#define QDMA_S80_HARD_TRQ_SEL_FMAP_65_ADDR 0x5A0
-#define TRQ_SEL_FMAP_65_RSVD_1_MASK GENMASK(31, 23)
-#define TRQ_SEL_FMAP_65_QID_MAX_MASK GENMASK(22, 11)
-#define TRQ_SEL_FMAP_65_QID_BASE_MASK GENMASK(10, 0)
-#define QDMA_S80_HARD_TRQ_SEL_FMAP_66_ADDR 0x5A4
-#define TRQ_SEL_FMAP_66_RSVD_1_MASK GENMASK(31, 23)
-#define TRQ_SEL_FMAP_66_QID_MAX_MASK GENMASK(22, 11)
-#define TRQ_SEL_FMAP_66_QID_BASE_MASK GENMASK(10, 0)
-#define QDMA_S80_HARD_TRQ_SEL_FMAP_67_ADDR 0x5A8
-#define TRQ_SEL_FMAP_67_RSVD_1_MASK GENMASK(31, 23)
-#define TRQ_SEL_FMAP_67_QID_MAX_MASK GENMASK(22, 11)
-#define TRQ_SEL_FMAP_67_QID_BASE_MASK GENMASK(10, 0)
-#define QDMA_S80_HARD_TRQ_SEL_FMAP_68_ADDR 0x5AC
-#define TRQ_SEL_FMAP_68_RSVD_1_MASK GENMASK(31, 23)
-#define TRQ_SEL_FMAP_68_QID_MAX_MASK GENMASK(22, 11)
-#define TRQ_SEL_FMAP_68_QID_BASE_MASK GENMASK(10, 0)
-#define QDMA_S80_HARD_TRQ_SEL_FMAP_69_ADDR 0x5B0
-#define TRQ_SEL_FMAP_69_RSVD_1_MASK GENMASK(31, 23)
-#define TRQ_SEL_FMAP_69_QID_MAX_MASK GENMASK(22, 11)
-#define TRQ_SEL_FMAP_69_QID_BASE_MASK GENMASK(10, 0)
-#define QDMA_S80_HARD_TRQ_SEL_FMAP_6A_ADDR 0x5B4
-#define TRQ_SEL_FMAP_6A_RSVD_1_MASK GENMASK(31, 23)
-#define TRQ_SEL_FMAP_6A_QID_MAX_MASK GENMASK(22, 11)
-#define TRQ_SEL_FMAP_6A_QID_BASE_MASK GENMASK(10, 0)
-#define QDMA_S80_HARD_TRQ_SEL_FMAP_6B_ADDR 0x5B8
-#define TRQ_SEL_FMAP_6B_RSVD_1_MASK GENMASK(31, 23)
-#define TRQ_SEL_FMAP_6B_QID_MAX_MASK GENMASK(22, 11)
-#define TRQ_SEL_FMAP_6B_QID_BASE_MASK GENMASK(10, 0)
-#define QDMA_S80_HARD_TRQ_SEL_FMAP_6C_ADDR 0x5BC
-#define TRQ_SEL_FMAP_6C_RSVD_1_MASK GENMASK(31, 23)
-#define TRQ_SEL_FMAP_6C_QID_MAX_MASK GENMASK(22, 11)
-#define TRQ_SEL_FMAP_6C_QID_BASE_MASK GENMASK(10, 0)
-#define QDMA_S80_HARD_TRQ_SEL_FMAP_6D_ADDR 0x5C0
-#define TRQ_SEL_FMAP_6D_RSVD_1_MASK GENMASK(31, 23)
-#define TRQ_SEL_FMAP_6D_QID_MAX_MASK GENMASK(22, 11)
-#define TRQ_SEL_FMAP_6D_QID_BASE_MASK GENMASK(10, 0)
-#define QDMA_S80_HARD_TRQ_SEL_FMAP_6E_ADDR 0x5C4
-#define TRQ_SEL_FMAP_6E_RSVD_1_MASK GENMASK(31, 23)
-#define TRQ_SEL_FMAP_6E_QID_MAX_MASK GENMASK(22, 11)
-#define TRQ_SEL_FMAP_6E_QID_BASE_MASK GENMASK(10, 0)
-#define QDMA_S80_HARD_TRQ_SEL_FMAP_6F_ADDR 0x5C8
-#define TRQ_SEL_FMAP_6F_RSVD_1_MASK GENMASK(31, 23)
-#define TRQ_SEL_FMAP_6F_QID_MAX_MASK GENMASK(22, 11)
-#define TRQ_SEL_FMAP_6F_QID_BASE_MASK GENMASK(10, 0)
-#define QDMA_S80_HARD_TRQ_SEL_FMAP_70_ADDR 0x5CC
-#define TRQ_SEL_FMAP_70_RSVD_1_MASK GENMASK(31, 23)
-#define TRQ_SEL_FMAP_70_QID_MAX_MASK GENMASK(22, 11)
-#define TRQ_SEL_FMAP_70_QID_BASE_MASK GENMASK(10, 0)
-#define QDMA_S80_HARD_TRQ_SEL_FMAP_71_ADDR 0x5D0
-#define TRQ_SEL_FMAP_71_RSVD_1_MASK GENMASK(31, 23)
-#define TRQ_SEL_FMAP_71_QID_MAX_MASK GENMASK(22, 11)
-#define TRQ_SEL_FMAP_71_QID_BASE_MASK GENMASK(10, 0)
-#define QDMA_S80_HARD_TRQ_SEL_FMAP_72_ADDR 0x5D4
-#define TRQ_SEL_FMAP_72_RSVD_1_MASK GENMASK(31, 23)
-#define TRQ_SEL_FMAP_72_QID_MAX_MASK GENMASK(22, 11)
-#define TRQ_SEL_FMAP_72_QID_BASE_MASK GENMASK(10, 0)
-#define QDMA_S80_HARD_TRQ_SEL_FMAP_73_ADDR 0x5D8
-#define TRQ_SEL_FMAP_73_RSVD_1_MASK GENMASK(31, 23)
-#define TRQ_SEL_FMAP_73_QID_MAX_MASK GENMASK(22, 11)
-#define TRQ_SEL_FMAP_73_QID_BASE_MASK GENMASK(10, 0)
-#define QDMA_S80_HARD_TRQ_SEL_FMAP_74_ADDR 0x5DC
-#define TRQ_SEL_FMAP_74_RSVD_1_MASK GENMASK(31, 23)
-#define TRQ_SEL_FMAP_74_QID_MAX_MASK GENMASK(22, 11)
-#define TRQ_SEL_FMAP_74_QID_BASE_MASK GENMASK(10, 0)
-#define QDMA_S80_HARD_TRQ_SEL_FMAP_75_ADDR 0x5E0
-#define TRQ_SEL_FMAP_75_RSVD_1_MASK GENMASK(31, 23)
-#define TRQ_SEL_FMAP_75_QID_MAX_MASK GENMASK(22, 11)
-#define TRQ_SEL_FMAP_75_QID_BASE_MASK GENMASK(10, 0)
-#define QDMA_S80_HARD_TRQ_SEL_FMAP_76_ADDR 0x5E4
-#define TRQ_SEL_FMAP_76_RSVD_1_MASK GENMASK(31, 23)
-#define TRQ_SEL_FMAP_76_QID_MAX_MASK GENMASK(22, 11)
-#define TRQ_SEL_FMAP_76_QID_BASE_MASK GENMASK(10, 0)
-#define QDMA_S80_HARD_TRQ_SEL_FMAP_77_ADDR 0x5E8
-#define TRQ_SEL_FMAP_77_RSVD_1_MASK GENMASK(31, 23)
-#define TRQ_SEL_FMAP_77_QID_MAX_MASK GENMASK(22, 11)
-#define TRQ_SEL_FMAP_77_QID_BASE_MASK GENMASK(10, 0)
-#define QDMA_S80_HARD_TRQ_SEL_FMAP_78_ADDR 0x5EC
-#define TRQ_SEL_FMAP_78_RSVD_1_MASK GENMASK(31, 23)
-#define TRQ_SEL_FMAP_78_QID_MAX_MASK GENMASK(22, 11)
-#define TRQ_SEL_FMAP_78_QID_BASE_MASK GENMASK(10, 0)
-#define QDMA_S80_HARD_TRQ_SEL_FMAP_79_ADDR 0x5F0
-#define TRQ_SEL_FMAP_79_RSVD_1_MASK GENMASK(31, 23)
-#define TRQ_SEL_FMAP_79_QID_MAX_MASK GENMASK(22, 11)
-#define TRQ_SEL_FMAP_79_QID_BASE_MASK GENMASK(10, 0)
-#define QDMA_S80_HARD_TRQ_SEL_FMAP_7A_ADDR 0x5F4
-#define TRQ_SEL_FMAP_7A_RSVD_1_MASK GENMASK(31, 23)
-#define TRQ_SEL_FMAP_7A_QID_MAX_MASK GENMASK(22, 11)
-#define TRQ_SEL_FMAP_7A_QID_BASE_MASK GENMASK(10, 0)
-#define QDMA_S80_HARD_TRQ_SEL_FMAP_7B_ADDR 0x5F8
-#define TRQ_SEL_FMAP_7B_RSVD_1_MASK GENMASK(31, 23)
-#define TRQ_SEL_FMAP_7B_QID_MAX_MASK GENMASK(22, 11)
-#define TRQ_SEL_FMAP_7B_QID_BASE_MASK GENMASK(10, 0)
-#define QDMA_S80_HARD_TRQ_SEL_FMAP_7C_ADDR 0x5FC
-#define TRQ_SEL_FMAP_7C_RSVD_1_MASK GENMASK(31, 23)
-#define TRQ_SEL_FMAP_7C_QID_MAX_MASK GENMASK(22, 11)
-#define TRQ_SEL_FMAP_7C_QID_BASE_MASK GENMASK(10, 0)
-#define QDMA_S80_HARD_TRQ_SEL_FMAP_7D_ADDR 0x600
-#define TRQ_SEL_FMAP_7D_RSVD_1_MASK GENMASK(31, 23)
-#define TRQ_SEL_FMAP_7D_QID_MAX_MASK GENMASK(22, 11)
-#define TRQ_SEL_FMAP_7D_QID_BASE_MASK GENMASK(10, 0)
-#define QDMA_S80_HARD_TRQ_SEL_FMAP_7E_ADDR 0x604
-#define TRQ_SEL_FMAP_7E_RSVD_1_MASK GENMASK(31, 23)
-#define TRQ_SEL_FMAP_7E_QID_MAX_MASK GENMASK(22, 11)
-#define TRQ_SEL_FMAP_7E_QID_BASE_MASK GENMASK(10, 0)
-#define QDMA_S80_HARD_TRQ_SEL_FMAP_7F_ADDR 0x608
-#define TRQ_SEL_FMAP_7F_RSVD_1_MASK GENMASK(31, 23)
-#define TRQ_SEL_FMAP_7F_QID_MAX_MASK GENMASK(22, 11)
-#define TRQ_SEL_FMAP_7F_QID_BASE_MASK GENMASK(10, 0)
-#define QDMA_S80_HARD_TRQ_SEL_FMAP_80_ADDR 0x60C
-#define TRQ_SEL_FMAP_80_RSVD_1_MASK GENMASK(31, 23)
-#define TRQ_SEL_FMAP_80_QID_MAX_MASK GENMASK(22, 11)
-#define TRQ_SEL_FMAP_80_QID_BASE_MASK GENMASK(10, 0)
-#define QDMA_S80_HARD_TRQ_SEL_FMAP_81_ADDR 0x610
-#define TRQ_SEL_FMAP_81_RSVD_1_MASK GENMASK(31, 23)
-#define TRQ_SEL_FMAP_81_QID_MAX_MASK GENMASK(22, 11)
-#define TRQ_SEL_FMAP_81_QID_BASE_MASK GENMASK(10, 0)
-#define QDMA_S80_HARD_TRQ_SEL_FMAP_82_ADDR 0x614
-#define TRQ_SEL_FMAP_82_RSVD_1_MASK GENMASK(31, 23)
-#define TRQ_SEL_FMAP_82_QID_MAX_MASK GENMASK(22, 11)
-#define TRQ_SEL_FMAP_82_QID_BASE_MASK GENMASK(10, 0)
-#define QDMA_S80_HARD_TRQ_SEL_FMAP_83_ADDR 0x618
-#define TRQ_SEL_FMAP_83_RSVD_1_MASK GENMASK(31, 23)
-#define TRQ_SEL_FMAP_83_QID_MAX_MASK GENMASK(22, 11)
-#define TRQ_SEL_FMAP_83_QID_BASE_MASK GENMASK(10, 0)
-#define QDMA_S80_HARD_TRQ_SEL_FMAP_84_ADDR 0x61C
-#define TRQ_SEL_FMAP_84_RSVD_1_MASK GENMASK(31, 23)
-#define TRQ_SEL_FMAP_84_QID_MAX_MASK GENMASK(22, 11)
-#define TRQ_SEL_FMAP_84_QID_BASE_MASK GENMASK(10, 0)
-#define QDMA_S80_HARD_TRQ_SEL_FMAP_85_ADDR 0x620
-#define TRQ_SEL_FMAP_85_RSVD_1_MASK GENMASK(31, 23)
-#define TRQ_SEL_FMAP_85_QID_MAX_MASK GENMASK(22, 11)
-#define TRQ_SEL_FMAP_85_QID_BASE_MASK GENMASK(10, 0)
-#define QDMA_S80_HARD_TRQ_SEL_FMAP_86_ADDR 0x624
-#define TRQ_SEL_FMAP_86_RSVD_1_MASK GENMASK(31, 23)
-#define TRQ_SEL_FMAP_86_QID_MAX_MASK GENMASK(22, 11)
-#define TRQ_SEL_FMAP_86_QID_BASE_MASK GENMASK(10, 0)
-#define QDMA_S80_HARD_TRQ_SEL_FMAP_87_ADDR 0x628
-#define TRQ_SEL_FMAP_87_RSVD_1_MASK GENMASK(31, 23)
-#define TRQ_SEL_FMAP_87_QID_MAX_MASK GENMASK(22, 11)
-#define TRQ_SEL_FMAP_87_QID_BASE_MASK GENMASK(10, 0)
-#define QDMA_S80_HARD_TRQ_SEL_FMAP_88_ADDR 0x62C
-#define TRQ_SEL_FMAP_88_RSVD_1_MASK GENMASK(31, 23)
-#define TRQ_SEL_FMAP_88_QID_MAX_MASK GENMASK(22, 11)
-#define TRQ_SEL_FMAP_88_QID_BASE_MASK GENMASK(10, 0)
-#define QDMA_S80_HARD_TRQ_SEL_FMAP_89_ADDR 0x630
-#define TRQ_SEL_FMAP_89_RSVD_1_MASK GENMASK(31, 23)
-#define TRQ_SEL_FMAP_89_QID_MAX_MASK GENMASK(22, 11)
-#define TRQ_SEL_FMAP_89_QID_BASE_MASK GENMASK(10, 0)
-#define QDMA_S80_HARD_TRQ_SEL_FMAP_8A_ADDR 0x634
-#define TRQ_SEL_FMAP_8A_RSVD_1_MASK GENMASK(31, 23)
-#define TRQ_SEL_FMAP_8A_QID_MAX_MASK GENMASK(22, 11)
-#define TRQ_SEL_FMAP_8A_QID_BASE_MASK GENMASK(10, 0)
-#define QDMA_S80_HARD_TRQ_SEL_FMAP_8B_ADDR 0x638
-#define TRQ_SEL_FMAP_8B_RSVD_1_MASK GENMASK(31, 23)
-#define TRQ_SEL_FMAP_8B_QID_MAX_MASK GENMASK(22, 11)
-#define TRQ_SEL_FMAP_8B_QID_BASE_MASK GENMASK(10, 0)
-#define QDMA_S80_HARD_TRQ_SEL_FMAP_8C_ADDR 0x63C
-#define TRQ_SEL_FMAP_8C_RSVD_1_MASK GENMASK(31, 23)
-#define TRQ_SEL_FMAP_8C_QID_MAX_MASK GENMASK(22, 11)
-#define TRQ_SEL_FMAP_8C_QID_BASE_MASK GENMASK(10, 0)
-#define QDMA_S80_HARD_TRQ_SEL_FMAP_8D_ADDR 0x640
-#define TRQ_SEL_FMAP_8D_RSVD_1_MASK GENMASK(31, 23)
-#define TRQ_SEL_FMAP_8D_QID_MAX_MASK GENMASK(22, 11)
-#define TRQ_SEL_FMAP_8D_QID_BASE_MASK GENMASK(10, 0)
-#define QDMA_S80_HARD_TRQ_SEL_FMAP_8E_ADDR 0x644
-#define TRQ_SEL_FMAP_8E_RSVD_1_MASK GENMASK(31, 23)
-#define TRQ_SEL_FMAP_8E_QID_MAX_MASK GENMASK(22, 11)
-#define TRQ_SEL_FMAP_8E_QID_BASE_MASK GENMASK(10, 0)
-#define QDMA_S80_HARD_TRQ_SEL_FMAP_8F_ADDR 0x648
-#define TRQ_SEL_FMAP_8F_RSVD_1_MASK GENMASK(31, 23)
-#define TRQ_SEL_FMAP_8F_QID_MAX_MASK GENMASK(22, 11)
-#define TRQ_SEL_FMAP_8F_QID_BASE_MASK GENMASK(10, 0)
-#define QDMA_S80_HARD_TRQ_SEL_FMAP_90_ADDR 0x64C
-#define TRQ_SEL_FMAP_90_RSVD_1_MASK GENMASK(31, 23)
-#define TRQ_SEL_FMAP_90_QID_MAX_MASK GENMASK(22, 11)
-#define TRQ_SEL_FMAP_90_QID_BASE_MASK GENMASK(10, 0)
-#define QDMA_S80_HARD_TRQ_SEL_FMAP_91_ADDR 0x650
-#define TRQ_SEL_FMAP_91_RSVD_1_MASK GENMASK(31, 23)
-#define TRQ_SEL_FMAP_91_QID_MAX_MASK GENMASK(22, 11)
-#define TRQ_SEL_FMAP_91_QID_BASE_MASK GENMASK(10, 0)
-#define QDMA_S80_HARD_TRQ_SEL_FMAP_92_ADDR 0x654
-#define TRQ_SEL_FMAP_92_RSVD_1_MASK GENMASK(31, 23)
-#define TRQ_SEL_FMAP_92_QID_MAX_MASK GENMASK(22, 11)
-#define TRQ_SEL_FMAP_92_QID_BASE_MASK GENMASK(10, 0)
-#define QDMA_S80_HARD_TRQ_SEL_FMAP_93_ADDR 0x658
-#define TRQ_SEL_FMAP_93_RSVD_1_MASK GENMASK(31, 23)
-#define TRQ_SEL_FMAP_93_QID_MAX_MASK GENMASK(22, 11)
-#define TRQ_SEL_FMAP_93_QID_BASE_MASK GENMASK(10, 0)
-#define QDMA_S80_HARD_TRQ_SEL_FMAP_94_ADDR 0x65C
-#define TRQ_SEL_FMAP_94_RSVD_1_MASK GENMASK(31, 23)
-#define TRQ_SEL_FMAP_94_QID_MAX_MASK GENMASK(22, 11)
-#define TRQ_SEL_FMAP_94_QID_BASE_MASK GENMASK(10, 0)
-#define QDMA_S80_HARD_TRQ_SEL_FMAP_95_ADDR 0x660
-#define TRQ_SEL_FMAP_95_RSVD_1_MASK GENMASK(31, 23)
-#define TRQ_SEL_FMAP_95_QID_MAX_MASK GENMASK(22, 11)
-#define TRQ_SEL_FMAP_95_QID_BASE_MASK GENMASK(10, 0)
-#define QDMA_S80_HARD_TRQ_SEL_FMAP_96_ADDR 0x664
-#define TRQ_SEL_FMAP_96_RSVD_1_MASK GENMASK(31, 23)
-#define TRQ_SEL_FMAP_96_QID_MAX_MASK GENMASK(22, 11)
-#define TRQ_SEL_FMAP_96_QID_BASE_MASK GENMASK(10, 0)
-#define QDMA_S80_HARD_TRQ_SEL_FMAP_97_ADDR 0x668
-#define TRQ_SEL_FMAP_97_RSVD_1_MASK GENMASK(31, 23)
-#define TRQ_SEL_FMAP_97_QID_MAX_MASK GENMASK(22, 11)
-#define TRQ_SEL_FMAP_97_QID_BASE_MASK GENMASK(10, 0)
-#define QDMA_S80_HARD_TRQ_SEL_FMAP_98_ADDR 0x66C
-#define TRQ_SEL_FMAP_98_RSVD_1_MASK GENMASK(31, 23)
-#define TRQ_SEL_FMAP_98_QID_MAX_MASK GENMASK(22, 11)
-#define TRQ_SEL_FMAP_98_QID_BASE_MASK GENMASK(10, 0)
-#define QDMA_S80_HARD_TRQ_SEL_FMAP_99_ADDR 0x670
-#define TRQ_SEL_FMAP_99_RSVD_1_MASK GENMASK(31, 23)
-#define TRQ_SEL_FMAP_99_QID_MAX_MASK GENMASK(22, 11)
-#define TRQ_SEL_FMAP_99_QID_BASE_MASK GENMASK(10, 0)
-#define QDMA_S80_HARD_TRQ_SEL_FMAP_9A_ADDR 0x674
-#define TRQ_SEL_FMAP_9A_RSVD_1_MASK GENMASK(31, 23)
-#define TRQ_SEL_FMAP_9A_QID_MAX_MASK GENMASK(22, 11)
-#define TRQ_SEL_FMAP_9A_QID_BASE_MASK GENMASK(10, 0)
-#define QDMA_S80_HARD_TRQ_SEL_FMAP_9B_ADDR 0x678
-#define TRQ_SEL_FMAP_9B_RSVD_1_MASK GENMASK(31, 23)
-#define TRQ_SEL_FMAP_9B_QID_MAX_MASK GENMASK(22, 11)
-#define TRQ_SEL_FMAP_9B_QID_BASE_MASK GENMASK(10, 0)
-#define QDMA_S80_HARD_TRQ_SEL_FMAP_9C_ADDR 0x67C
-#define TRQ_SEL_FMAP_9C_RSVD_1_MASK GENMASK(31, 23)
-#define TRQ_SEL_FMAP_9C_QID_MAX_MASK GENMASK(22, 11)
-#define TRQ_SEL_FMAP_9C_QID_BASE_MASK GENMASK(10, 0)
-#define QDMA_S80_HARD_TRQ_SEL_FMAP_9D_ADDR 0x680
-#define TRQ_SEL_FMAP_9D_RSVD_1_MASK GENMASK(31, 23)
-#define TRQ_SEL_FMAP_9D_QID_MAX_MASK GENMASK(22, 11)
-#define TRQ_SEL_FMAP_9D_QID_BASE_MASK GENMASK(10, 0)
-#define QDMA_S80_HARD_TRQ_SEL_FMAP_9E_ADDR 0x684
-#define TRQ_SEL_FMAP_9E_RSVD_1_MASK GENMASK(31, 23)
-#define TRQ_SEL_FMAP_9E_QID_MAX_MASK GENMASK(22, 11)
-#define TRQ_SEL_FMAP_9E_QID_BASE_MASK GENMASK(10, 0)
-#define QDMA_S80_HARD_TRQ_SEL_FMAP_9F_ADDR 0x688
-#define TRQ_SEL_FMAP_9F_RSVD_1_MASK GENMASK(31, 23)
-#define TRQ_SEL_FMAP_9F_QID_MAX_MASK GENMASK(22, 11)
-#define TRQ_SEL_FMAP_9F_QID_BASE_MASK GENMASK(10, 0)
-#define QDMA_S80_HARD_TRQ_SEL_FMAP_A0_ADDR 0x68C
-#define TRQ_SEL_FMAP_A0_RSVD_1_MASK GENMASK(31, 23)
-#define TRQ_SEL_FMAP_A0_QID_MAX_MASK GENMASK(22, 11)
-#define TRQ_SEL_FMAP_A0_QID_BASE_MASK GENMASK(10, 0)
-#define QDMA_S80_HARD_TRQ_SEL_FMAP_A1_ADDR 0x690
-#define TRQ_SEL_FMAP_A1_RSVD_1_MASK GENMASK(31, 23)
-#define TRQ_SEL_FMAP_A1_QID_MAX_MASK GENMASK(22, 11)
-#define TRQ_SEL_FMAP_A1_QID_BASE_MASK GENMASK(10, 0)
-#define QDMA_S80_HARD_TRQ_SEL_FMAP_A2_ADDR 0x694
-#define TRQ_SEL_FMAP_A2_RSVD_1_MASK GENMASK(31, 23)
-#define TRQ_SEL_FMAP_A2_QID_MAX_MASK GENMASK(22, 11)
-#define TRQ_SEL_FMAP_A2_QID_BASE_MASK GENMASK(10, 0)
-#define QDMA_S80_HARD_TRQ_SEL_FMAP_A3_ADDR 0x698
-#define TRQ_SEL_FMAP_A3_RSVD_1_MASK GENMASK(31, 23)
-#define TRQ_SEL_FMAP_A3_QID_MAX_MASK GENMASK(22, 11)
-#define TRQ_SEL_FMAP_A3_QID_BASE_MASK GENMASK(10, 0)
-#define QDMA_S80_HARD_TRQ_SEL_FMAP_A4_ADDR 0x69C
-#define TRQ_SEL_FMAP_A4_RSVD_1_MASK GENMASK(31, 23)
-#define TRQ_SEL_FMAP_A4_QID_MAX_MASK GENMASK(22, 11)
-#define TRQ_SEL_FMAP_A4_QID_BASE_MASK GENMASK(10, 0)
-#define QDMA_S80_HARD_TRQ_SEL_FMAP_A5_ADDR 0x6A0
-#define TRQ_SEL_FMAP_A5_RSVD_1_MASK GENMASK(31, 23)
-#define TRQ_SEL_FMAP_A5_QID_MAX_MASK GENMASK(22, 11)
-#define TRQ_SEL_FMAP_A5_QID_BASE_MASK GENMASK(10, 0)
-#define QDMA_S80_HARD_TRQ_SEL_FMAP_A6_ADDR 0x6A4
-#define TRQ_SEL_FMAP_A6_RSVD_1_MASK GENMASK(31, 23)
-#define TRQ_SEL_FMAP_A6_QID_MAX_MASK GENMASK(22, 11)
-#define TRQ_SEL_FMAP_A6_QID_BASE_MASK GENMASK(10, 0)
-#define QDMA_S80_HARD_TRQ_SEL_FMAP_A7_ADDR 0x6A8
-#define TRQ_SEL_FMAP_A7_RSVD_1_MASK GENMASK(31, 23)
-#define TRQ_SEL_FMAP_A7_QID_MAX_MASK GENMASK(22, 11)
-#define TRQ_SEL_FMAP_A7_QID_BASE_MASK GENMASK(10, 0)
-#define QDMA_S80_HARD_TRQ_SEL_FMAP_A8_ADDR 0x6AC
-#define TRQ_SEL_FMAP_A8_RSVD_1_MASK GENMASK(31, 23)
-#define TRQ_SEL_FMAP_A8_QID_MAX_MASK GENMASK(22, 11)
-#define TRQ_SEL_FMAP_A8_QID_BASE_MASK GENMASK(10, 0)
-#define QDMA_S80_HARD_TRQ_SEL_FMAP_A9_ADDR 0x6B0
-#define TRQ_SEL_FMAP_A9_RSVD_1_MASK GENMASK(31, 23)
-#define TRQ_SEL_FMAP_A9_QID_MAX_MASK GENMASK(22, 11)
-#define TRQ_SEL_FMAP_A9_QID_BASE_MASK GENMASK(10, 0)
-#define QDMA_S80_HARD_TRQ_SEL_FMAP_AA_ADDR 0x6B4
-#define TRQ_SEL_FMAP_AA_RSVD_1_MASK GENMASK(31, 23)
-#define TRQ_SEL_FMAP_AA_QID_MAX_MASK GENMASK(22, 11)
-#define TRQ_SEL_FMAP_AA_QID_BASE_MASK GENMASK(10, 0)
-#define QDMA_S80_HARD_TRQ_SEL_FMAP_AB_ADDR 0x6B8
-#define TRQ_SEL_FMAP_AB_RSVD_1_MASK GENMASK(31, 23)
-#define TRQ_SEL_FMAP_AB_QID_MAX_MASK GENMASK(22, 11)
-#define TRQ_SEL_FMAP_AB_QID_BASE_MASK GENMASK(10, 0)
-#define QDMA_S80_HARD_TRQ_SEL_FMAP_AC_ADDR 0x6BC
-#define TRQ_SEL_FMAP_AC_RSVD_1_MASK GENMASK(31, 23)
-#define TRQ_SEL_FMAP_AC_QID_MAX_MASK GENMASK(22, 11)
-#define TRQ_SEL_FMAP_AC_QID_BASE_MASK GENMASK(10, 0)
-#define QDMA_S80_HARD_TRQ_SEL_FMAP_AD_ADDR 0x6D0
-#define TRQ_SEL_FMAP_AD_RSVD_1_MASK GENMASK(31, 23)
-#define TRQ_SEL_FMAP_AD_QID_MAX_MASK GENMASK(22, 11)
-#define TRQ_SEL_FMAP_AD_QID_BASE_MASK GENMASK(10, 0)
-#define QDMA_S80_HARD_TRQ_SEL_FMAP_AE_ADDR 0x6D4
-#define TRQ_SEL_FMAP_AE_RSVD_1_MASK GENMASK(31, 23)
-#define TRQ_SEL_FMAP_AE_QID_MAX_MASK GENMASK(22, 11)
-#define TRQ_SEL_FMAP_AE_QID_BASE_MASK GENMASK(10, 0)
-#define QDMA_S80_HARD_TRQ_SEL_FMAP_AF_ADDR 0x6D8
-#define TRQ_SEL_FMAP_AF_RSVD_1_MASK GENMASK(31, 23)
-#define TRQ_SEL_FMAP_AF_QID_MAX_MASK GENMASK(22, 11)
-#define TRQ_SEL_FMAP_AF_QID_BASE_MASK GENMASK(10, 0)
-#define QDMA_S80_HARD_TRQ_SEL_FMAP_B0_ADDR 0x6DC
-#define TRQ_SEL_FMAP_B0_RSVD_1_MASK GENMASK(31, 23)
-#define TRQ_SEL_FMAP_B0_QID_MAX_MASK GENMASK(22, 11)
-#define TRQ_SEL_FMAP_B0_QID_BASE_MASK GENMASK(10, 0)
-#define QDMA_S80_HARD_TRQ_SEL_FMAP_B1_ADDR 0x6E0
-#define TRQ_SEL_FMAP_B1_RSVD_1_MASK GENMASK(31, 23)
-#define TRQ_SEL_FMAP_B1_QID_MAX_MASK GENMASK(22, 11)
-#define TRQ_SEL_FMAP_B1_QID_BASE_MASK GENMASK(10, 0)
-#define QDMA_S80_HARD_TRQ_SEL_FMAP_B2_ADDR 0x6E4
-#define TRQ_SEL_FMAP_B2_RSVD_1_MASK GENMASK(31, 23)
-#define TRQ_SEL_FMAP_B2_QID_MAX_MASK GENMASK(22, 11)
-#define TRQ_SEL_FMAP_B2_QID_BASE_MASK GENMASK(10, 0)
-#define QDMA_S80_HARD_TRQ_SEL_FMAP_B3_ADDR 0x6E8
-#define TRQ_SEL_FMAP_B3_RSVD_1_MASK GENMASK(31, 23)
-#define TRQ_SEL_FMAP_B3_QID_MAX_MASK GENMASK(22, 11)
-#define TRQ_SEL_FMAP_B3_QID_BASE_MASK GENMASK(10, 0)
-#define QDMA_S80_HARD_TRQ_SEL_FMAP_B4_ADDR 0x6EC
-#define TRQ_SEL_FMAP_B4_RSVD_1_MASK GENMASK(31, 23)
-#define TRQ_SEL_FMAP_B4_QID_MAX_MASK GENMASK(22, 11)
-#define TRQ_SEL_FMAP_B4_QID_BASE_MASK GENMASK(10, 0)
-#define QDMA_S80_HARD_TRQ_SEL_FMAP_B5_ADDR 0x6F0
-#define TRQ_SEL_FMAP_B5_RSVD_1_MASK GENMASK(31, 23)
-#define TRQ_SEL_FMAP_B5_QID_MAX_MASK GENMASK(22, 11)
-#define TRQ_SEL_FMAP_B5_QID_BASE_MASK GENMASK(10, 0)
-#define QDMA_S80_HARD_TRQ_SEL_FMAP_B6_ADDR 0x6F4
-#define TRQ_SEL_FMAP_B6_RSVD_1_MASK GENMASK(31, 23)
-#define TRQ_SEL_FMAP_B6_QID_MAX_MASK GENMASK(22, 11)
-#define TRQ_SEL_FMAP_B6_QID_BASE_MASK GENMASK(10, 0)
-#define QDMA_S80_HARD_TRQ_SEL_FMAP_B7_ADDR 0x6F8
-#define TRQ_SEL_FMAP_B7_RSVD_1_MASK GENMASK(31, 23)
-#define TRQ_SEL_FMAP_B7_QID_MAX_MASK GENMASK(22, 11)
-#define TRQ_SEL_FMAP_B7_QID_BASE_MASK GENMASK(10, 0)
-#define QDMA_S80_HARD_TRQ_SEL_FMAP_B8_ADDR 0x6FC
-#define TRQ_SEL_FMAP_B8_RSVD_1_MASK GENMASK(31, 23)
-#define TRQ_SEL_FMAP_B8_QID_MAX_MASK GENMASK(22, 11)
-#define TRQ_SEL_FMAP_B8_QID_BASE_MASK GENMASK(10, 0)
-#define QDMA_S80_HARD_TRQ_SEL_FMAP_B9_ADDR 0x700
-#define TRQ_SEL_FMAP_B9_RSVD_1_MASK GENMASK(31, 23)
-#define TRQ_SEL_FMAP_B9_QID_MAX_MASK GENMASK(22, 11)
-#define TRQ_SEL_FMAP_B9_QID_BASE_MASK GENMASK(10, 0)
-#define QDMA_S80_HARD_TRQ_SEL_FMAP_BA_ADDR 0x704
-#define TRQ_SEL_FMAP_BA_RSVD_1_MASK GENMASK(31, 23)
-#define TRQ_SEL_FMAP_BA_QID_MAX_MASK GENMASK(22, 11)
-#define TRQ_SEL_FMAP_BA_QID_BASE_MASK GENMASK(10, 0)
-#define QDMA_S80_HARD_TRQ_SEL_FMAP_BB_ADDR 0x708
-#define TRQ_SEL_FMAP_BB_RSVD_1_MASK GENMASK(31, 23)
-#define TRQ_SEL_FMAP_BB_QID_MAX_MASK GENMASK(22, 11)
-#define TRQ_SEL_FMAP_BB_QID_BASE_MASK GENMASK(10, 0)
-#define QDMA_S80_HARD_TRQ_SEL_FMAP_BC_ADDR 0x70C
-#define TRQ_SEL_FMAP_BC_RSVD_1_MASK GENMASK(31, 23)
-#define TRQ_SEL_FMAP_BC_QID_MAX_MASK GENMASK(22, 11)
-#define TRQ_SEL_FMAP_BC_QID_BASE_MASK GENMASK(10, 0)
-#define QDMA_S80_HARD_TRQ_SEL_FMAP_BD_ADDR 0x710
-#define TRQ_SEL_FMAP_BD_RSVD_1_MASK GENMASK(31, 23)
-#define TRQ_SEL_FMAP_BD_QID_MAX_MASK GENMASK(22, 11)
-#define TRQ_SEL_FMAP_BD_QID_BASE_MASK GENMASK(10, 0)
-#define QDMA_S80_HARD_TRQ_SEL_FMAP_BE_ADDR 0x714
-#define TRQ_SEL_FMAP_BE_RSVD_1_MASK GENMASK(31, 23)
-#define TRQ_SEL_FMAP_BE_QID_MAX_MASK GENMASK(22, 11)
-#define TRQ_SEL_FMAP_BE_QID_BASE_MASK GENMASK(10, 0)
-#define QDMA_S80_HARD_TRQ_SEL_FMAP_BF_ADDR 0x718
-#define TRQ_SEL_FMAP_BF_RSVD_1_MASK GENMASK(31, 23)
-#define TRQ_SEL_FMAP_BF_QID_MAX_MASK GENMASK(22, 11)
-#define TRQ_SEL_FMAP_BF_QID_BASE_MASK GENMASK(10, 0)
-#define QDMA_S80_HARD_TRQ_SEL_FMAP_C0_ADDR 0x71C
-#define TRQ_SEL_FMAP_C0_RSVD_1_MASK GENMASK(31, 23)
-#define TRQ_SEL_FMAP_C0_QID_MAX_MASK GENMASK(22, 11)
-#define TRQ_SEL_FMAP_C0_QID_BASE_MASK GENMASK(10, 0)
-#define QDMA_S80_HARD_TRQ_SEL_FMAP_C1_ADDR 0x720
-#define TRQ_SEL_FMAP_C1_RSVD_1_MASK GENMASK(31, 23)
-#define TRQ_SEL_FMAP_C1_QID_MAX_MASK GENMASK(22, 11)
-#define TRQ_SEL_FMAP_C1_QID_BASE_MASK GENMASK(10, 0)
-#define QDMA_S80_HARD_TRQ_SEL_FMAP_C2_ADDR 0x734
-#define TRQ_SEL_FMAP_C2_RSVD_1_MASK GENMASK(31, 23)
-#define TRQ_SEL_FMAP_C2_QID_MAX_MASK GENMASK(22, 11)
-#define TRQ_SEL_FMAP_C2_QID_BASE_MASK GENMASK(10, 0)
-#define QDMA_S80_HARD_TRQ_SEL_FMAP_C3_ADDR 0x748
-#define TRQ_SEL_FMAP_C3_RSVD_1_MASK GENMASK(31, 23)
-#define TRQ_SEL_FMAP_C3_QID_MAX_MASK GENMASK(22, 11)
-#define TRQ_SEL_FMAP_C3_QID_BASE_MASK GENMASK(10, 0)
-#define QDMA_S80_HARD_TRQ_SEL_FMAP_C4_ADDR 0x74C
-#define TRQ_SEL_FMAP_C4_RSVD_1_MASK GENMASK(31, 23)
-#define TRQ_SEL_FMAP_C4_QID_MAX_MASK GENMASK(22, 11)
-#define TRQ_SEL_FMAP_C4_QID_BASE_MASK GENMASK(10, 0)
-#define QDMA_S80_HARD_TRQ_SEL_FMAP_C5_ADDR 0x750
-#define TRQ_SEL_FMAP_C5_RSVD_1_MASK GENMASK(31, 23)
-#define TRQ_SEL_FMAP_C5_QID_MAX_MASK GENMASK(22, 11)
-#define TRQ_SEL_FMAP_C5_QID_BASE_MASK GENMASK(10, 0)
-#define QDMA_S80_HARD_TRQ_SEL_FMAP_C6_ADDR 0x754
-#define TRQ_SEL_FMAP_C6_RSVD_1_MASK GENMASK(31, 23)
-#define TRQ_SEL_FMAP_C6_QID_MAX_MASK GENMASK(22, 11)
-#define TRQ_SEL_FMAP_C6_QID_BASE_MASK GENMASK(10, 0)
-#define QDMA_S80_HARD_TRQ_SEL_FMAP_C7_ADDR 0x758
-#define TRQ_SEL_FMAP_C7_RSVD_1_MASK GENMASK(31, 23)
-#define TRQ_SEL_FMAP_C7_QID_MAX_MASK GENMASK(22, 11)
-#define TRQ_SEL_FMAP_C7_QID_BASE_MASK GENMASK(10, 0)
-#define QDMA_S80_HARD_TRQ_SEL_FMAP_C8_ADDR 0x75C
-#define TRQ_SEL_FMAP_C8_RSVD_1_MASK GENMASK(31, 23)
-#define TRQ_SEL_FMAP_C8_QID_MAX_MASK GENMASK(22, 11)
-#define TRQ_SEL_FMAP_C8_QID_BASE_MASK GENMASK(10, 0)
-#define QDMA_S80_HARD_TRQ_SEL_FMAP_C9_ADDR 0x760
-#define TRQ_SEL_FMAP_C9_RSVD_1_MASK GENMASK(31, 23)
-#define TRQ_SEL_FMAP_C9_QID_MAX_MASK GENMASK(22, 11)
-#define TRQ_SEL_FMAP_C9_QID_BASE_MASK GENMASK(10, 0)
-#define QDMA_S80_HARD_TRQ_SEL_FMAP_CA_ADDR 0x764
-#define TRQ_SEL_FMAP_CA_RSVD_1_MASK GENMASK(31, 23)
-#define TRQ_SEL_FMAP_CA_QID_MAX_MASK GENMASK(22, 11)
-#define TRQ_SEL_FMAP_CA_QID_BASE_MASK GENMASK(10, 0)
-#define QDMA_S80_HARD_TRQ_SEL_FMAP_CB_ADDR 0x768
-#define TRQ_SEL_FMAP_CB_RSVD_1_MASK GENMASK(31, 23)
-#define TRQ_SEL_FMAP_CB_QID_MAX_MASK GENMASK(22, 11)
-#define TRQ_SEL_FMAP_CB_QID_BASE_MASK GENMASK(10, 0)
-#define QDMA_S80_HARD_TRQ_SEL_FMAP_CC_ADDR 0x76C
-#define TRQ_SEL_FMAP_CC_RSVD_1_MASK GENMASK(31, 23)
-#define TRQ_SEL_FMAP_CC_QID_MAX_MASK GENMASK(22, 11)
-#define TRQ_SEL_FMAP_CC_QID_BASE_MASK GENMASK(10, 0)
-#define QDMA_S80_HARD_TRQ_SEL_FMAP_CD_ADDR 0x770
-#define TRQ_SEL_FMAP_CD_RSVD_1_MASK GENMASK(31, 23)
-#define TRQ_SEL_FMAP_CD_QID_MAX_MASK GENMASK(22, 11)
-#define TRQ_SEL_FMAP_CD_QID_BASE_MASK GENMASK(10, 0)
-#define QDMA_S80_HARD_TRQ_SEL_FMAP_CE_ADDR 0x774
-#define TRQ_SEL_FMAP_CE_RSVD_1_MASK GENMASK(31, 23)
-#define TRQ_SEL_FMAP_CE_QID_MAX_MASK GENMASK(22, 11)
-#define TRQ_SEL_FMAP_CE_QID_BASE_MASK GENMASK(10, 0)
-#define QDMA_S80_HARD_TRQ_SEL_FMAP_CF_ADDR 0x778
-#define TRQ_SEL_FMAP_CF_RSVD_1_MASK GENMASK(31, 23)
-#define TRQ_SEL_FMAP_CF_QID_MAX_MASK GENMASK(22, 11)
-#define TRQ_SEL_FMAP_CF_QID_BASE_MASK GENMASK(10, 0)
-#define QDMA_S80_HARD_TRQ_SEL_FMAP_D0_ADDR 0x77C
-#define TRQ_SEL_FMAP_D0_RSVD_1_MASK GENMASK(31, 23)
-#define TRQ_SEL_FMAP_D0_QID_MAX_MASK GENMASK(22, 11)
-#define TRQ_SEL_FMAP_D0_QID_BASE_MASK GENMASK(10, 0)
-#define QDMA_S80_HARD_TRQ_SEL_FMAP_D1_ADDR 0x780
-#define TRQ_SEL_FMAP_D1_RSVD_1_MASK GENMASK(31, 23)
-#define TRQ_SEL_FMAP_D1_QID_MAX_MASK GENMASK(22, 11)
-#define TRQ_SEL_FMAP_D1_QID_BASE_MASK GENMASK(10, 0)
-#define QDMA_S80_HARD_TRQ_SEL_FMAP_D2_ADDR 0x784
-#define TRQ_SEL_FMAP_D2_RSVD_1_MASK GENMASK(31, 23)
-#define TRQ_SEL_FMAP_D2_QID_MAX_MASK GENMASK(22, 11)
-#define TRQ_SEL_FMAP_D2_QID_BASE_MASK GENMASK(10, 0)
-#define QDMA_S80_HARD_TRQ_SEL_FMAP_D3_ADDR 0x788
-#define TRQ_SEL_FMAP_D3_RSVD_1_MASK GENMASK(31, 23)
-#define TRQ_SEL_FMAP_D3_QID_MAX_MASK GENMASK(22, 11)
-#define TRQ_SEL_FMAP_D3_QID_BASE_MASK GENMASK(10, 0)
-#define QDMA_S80_HARD_TRQ_SEL_FMAP_D4_ADDR 0x78C
-#define TRQ_SEL_FMAP_D4_RSVD_1_MASK GENMASK(31, 23)
-#define TRQ_SEL_FMAP_D4_QID_MAX_MASK GENMASK(22, 11)
-#define TRQ_SEL_FMAP_D4_QID_BASE_MASK GENMASK(10, 0)
-#define QDMA_S80_HARD_TRQ_SEL_FMAP_D5_ADDR 0x790
-#define TRQ_SEL_FMAP_D5_RSVD_1_MASK GENMASK(31, 23)
-#define TRQ_SEL_FMAP_D5_QID_MAX_MASK GENMASK(22, 11)
-#define TRQ_SEL_FMAP_D5_QID_BASE_MASK GENMASK(10, 0)
-#define QDMA_S80_HARD_TRQ_SEL_FMAP_D6_ADDR 0x794
-#define TRQ_SEL_FMAP_D6_RSVD_1_MASK GENMASK(31, 23)
-#define TRQ_SEL_FMAP_D6_QID_MAX_MASK GENMASK(22, 11)
-#define TRQ_SEL_FMAP_D6_QID_BASE_MASK GENMASK(10, 0)
-#define QDMA_S80_HARD_TRQ_SEL_FMAP_D7_ADDR 0x798
-#define TRQ_SEL_FMAP_D7_RSVD_1_MASK GENMASK(31, 23)
-#define TRQ_SEL_FMAP_D7_QID_MAX_MASK GENMASK(22, 11)
-#define TRQ_SEL_FMAP_D7_QID_BASE_MASK GENMASK(10, 0)
-#define QDMA_S80_HARD_TRQ_SEL_FMAP_D8_ADDR 0x79C
-#define TRQ_SEL_FMAP_D8_RSVD_1_MASK GENMASK(31, 23)
-#define TRQ_SEL_FMAP_D8_QID_MAX_MASK GENMASK(22, 11)
-#define TRQ_SEL_FMAP_D8_QID_BASE_MASK GENMASK(10, 0)
-#define QDMA_S80_HARD_TRQ_SEL_FMAP_D9_ADDR 0x7A0
-#define TRQ_SEL_FMAP_D9_RSVD_1_MASK GENMASK(31, 23)
-#define TRQ_SEL_FMAP_D9_QID_MAX_MASK GENMASK(22, 11)
-#define TRQ_SEL_FMAP_D9_QID_BASE_MASK GENMASK(10, 0)
-#define QDMA_S80_HARD_TRQ_SEL_FMAP_DA_ADDR 0x7A4
-#define TRQ_SEL_FMAP_DA_RSVD_1_MASK GENMASK(31, 23)
-#define TRQ_SEL_FMAP_DA_QID_MAX_MASK GENMASK(22, 11)
-#define TRQ_SEL_FMAP_DA_QID_BASE_MASK GENMASK(10, 0)
-#define QDMA_S80_HARD_TRQ_SEL_FMAP_DB_ADDR 0x7A8
-#define TRQ_SEL_FMAP_DB_RSVD_1_MASK GENMASK(31, 23)
-#define TRQ_SEL_FMAP_DB_QID_MAX_MASK GENMASK(22, 11)
-#define TRQ_SEL_FMAP_DB_QID_BASE_MASK GENMASK(10, 0)
-#define QDMA_S80_HARD_TRQ_SEL_FMAP_DC_ADDR 0x7AC
-#define TRQ_SEL_FMAP_DC_RSVD_1_MASK GENMASK(31, 23)
-#define TRQ_SEL_FMAP_DC_QID_MAX_MASK GENMASK(22, 11)
-#define TRQ_SEL_FMAP_DC_QID_BASE_MASK GENMASK(10, 0)
-#define QDMA_S80_HARD_TRQ_SEL_FMAP_DD_ADDR 0x7B0
-#define TRQ_SEL_FMAP_DD_RSVD_1_MASK GENMASK(31, 23)
-#define TRQ_SEL_FMAP_DD_QID_MAX_MASK GENMASK(22, 11)
-#define TRQ_SEL_FMAP_DD_QID_BASE_MASK GENMASK(10, 0)
-#define QDMA_S80_HARD_TRQ_SEL_FMAP_DE_ADDR 0x7B4
-#define TRQ_SEL_FMAP_DE_RSVD_1_MASK GENMASK(31, 23)
-#define TRQ_SEL_FMAP_DE_QID_MAX_MASK GENMASK(22, 11)
-#define TRQ_SEL_FMAP_DE_QID_BASE_MASK GENMASK(10, 0)
-#define QDMA_S80_HARD_TRQ_SEL_FMAP_DF_ADDR 0x7B8
-#define TRQ_SEL_FMAP_DF_RSVD_1_MASK GENMASK(31, 23)
-#define TRQ_SEL_FMAP_DF_QID_MAX_MASK GENMASK(22, 11)
-#define TRQ_SEL_FMAP_DF_QID_BASE_MASK GENMASK(10, 0)
-#define QDMA_S80_HARD_TRQ_SEL_FMAP_E0_ADDR 0x7BC
-#define TRQ_SEL_FMAP_E0_RSVD_1_MASK GENMASK(31, 23)
-#define TRQ_SEL_FMAP_E0_QID_MAX_MASK GENMASK(22, 11)
-#define TRQ_SEL_FMAP_E0_QID_BASE_MASK GENMASK(10, 0)
-#define QDMA_S80_HARD_TRQ_SEL_FMAP_E1_ADDR 0x7C0
-#define TRQ_SEL_FMAP_E1_RSVD_1_MASK GENMASK(31, 23)
-#define TRQ_SEL_FMAP_E1_QID_MAX_MASK GENMASK(22, 11)
-#define TRQ_SEL_FMAP_E1_QID_BASE_MASK GENMASK(10, 0)
-#define QDMA_S80_HARD_TRQ_SEL_FMAP_E2_ADDR 0x7C4
-#define TRQ_SEL_FMAP_E2_RSVD_1_MASK GENMASK(31, 23)
-#define TRQ_SEL_FMAP_E2_QID_MAX_MASK GENMASK(22, 11)
-#define TRQ_SEL_FMAP_E2_QID_BASE_MASK GENMASK(10, 0)
-#define QDMA_S80_HARD_TRQ_SEL_FMAP_E3_ADDR 0x7C8
-#define TRQ_SEL_FMAP_E3_RSVD_1_MASK GENMASK(31, 23)
-#define TRQ_SEL_FMAP_E3_QID_MAX_MASK GENMASK(22, 11)
-#define TRQ_SEL_FMAP_E3_QID_BASE_MASK GENMASK(10, 0)
-#define QDMA_S80_HARD_TRQ_SEL_FMAP_E4_ADDR 0x7CC
-#define TRQ_SEL_FMAP_E4_RSVD_1_MASK GENMASK(31, 23)
-#define TRQ_SEL_FMAP_E4_QID_MAX_MASK GENMASK(22, 11)
-#define TRQ_SEL_FMAP_E4_QID_BASE_MASK GENMASK(10, 0)
-#define QDMA_S80_HARD_TRQ_SEL_FMAP_E5_ADDR 0x7D0
-#define TRQ_SEL_FMAP_E5_RSVD_1_MASK GENMASK(31, 23)
-#define TRQ_SEL_FMAP_E5_QID_MAX_MASK GENMASK(22, 11)
-#define TRQ_SEL_FMAP_E5_QID_BASE_MASK GENMASK(10, 0)
-#define QDMA_S80_HARD_TRQ_SEL_FMAP_E6_ADDR 0x7D4
-#define TRQ_SEL_FMAP_E6_RSVD_1_MASK GENMASK(31, 23)
-#define TRQ_SEL_FMAP_E6_QID_MAX_MASK GENMASK(22, 11)
-#define TRQ_SEL_FMAP_E6_QID_BASE_MASK GENMASK(10, 0)
-#define QDMA_S80_HARD_TRQ_SEL_FMAP_E7_ADDR 0x7D8
-#define TRQ_SEL_FMAP_E7_RSVD_1_MASK GENMASK(31, 23)
-#define TRQ_SEL_FMAP_E7_QID_MAX_MASK GENMASK(22, 11)
-#define TRQ_SEL_FMAP_E7_QID_BASE_MASK GENMASK(10, 0)
-#define QDMA_S80_HARD_TRQ_SEL_FMAP_E8_ADDR 0x7DC
-#define TRQ_SEL_FMAP_E8_RSVD_1_MASK GENMASK(31, 23)
-#define TRQ_SEL_FMAP_E8_QID_MAX_MASK GENMASK(22, 11)
-#define TRQ_SEL_FMAP_E8_QID_BASE_MASK GENMASK(10, 0)
-#define QDMA_S80_HARD_TRQ_SEL_FMAP_E9_ADDR 0x7E0
-#define TRQ_SEL_FMAP_E9_RSVD_1_MASK GENMASK(31, 23)
-#define TRQ_SEL_FMAP_E9_QID_MAX_MASK GENMASK(22, 11)
-#define TRQ_SEL_FMAP_E9_QID_BASE_MASK GENMASK(10, 0)
-#define QDMA_S80_HARD_TRQ_SEL_FMAP_EA_ADDR 0x7E4
-#define TRQ_SEL_FMAP_EA_RSVD_1_MASK GENMASK(31, 23)
-#define TRQ_SEL_FMAP_EA_QID_MAX_MASK GENMASK(22, 11)
-#define TRQ_SEL_FMAP_EA_QID_BASE_MASK GENMASK(10, 0)
-#define QDMA_S80_HARD_TRQ_SEL_FMAP_EB_ADDR 0x7E8
-#define TRQ_SEL_FMAP_EB_RSVD_1_MASK GENMASK(31, 23)
-#define TRQ_SEL_FMAP_EB_QID_MAX_MASK GENMASK(22, 11)
-#define TRQ_SEL_FMAP_EB_QID_BASE_MASK GENMASK(10, 0)
-#define QDMA_S80_HARD_TRQ_SEL_FMAP_EC_ADDR 0x7EC
-#define TRQ_SEL_FMAP_EC_RSVD_1_MASK GENMASK(31, 23)
-#define TRQ_SEL_FMAP_EC_QID_MAX_MASK GENMASK(22, 11)
-#define TRQ_SEL_FMAP_EC_QID_BASE_MASK GENMASK(10, 0)
-#define QDMA_S80_HARD_TRQ_SEL_FMAP_ED_ADDR 0x7F0
-#define TRQ_SEL_FMAP_ED_RSVD_1_MASK GENMASK(31, 23)
-#define TRQ_SEL_FMAP_ED_QID_MAX_MASK GENMASK(22, 11)
-#define TRQ_SEL_FMAP_ED_QID_BASE_MASK GENMASK(10, 0)
-#define QDMA_S80_HARD_TRQ_SEL_FMAP_EE_ADDR 0x7F4
-#define TRQ_SEL_FMAP_EE_RSVD_1_MASK GENMASK(31, 23)
-#define TRQ_SEL_FMAP_EE_QID_MAX_MASK GENMASK(22, 11)
-#define TRQ_SEL_FMAP_EE_QID_BASE_MASK GENMASK(10, 0)
-#define QDMA_S80_HARD_TRQ_SEL_FMAP_EF_ADDR 0x7F8
-#define TRQ_SEL_FMAP_EF_RSVD_1_MASK GENMASK(31, 23)
-#define TRQ_SEL_FMAP_EF_QID_MAX_MASK GENMASK(22, 11)
-#define TRQ_SEL_FMAP_EF_QID_BASE_MASK GENMASK(10, 0)
-#define QDMA_S80_HARD_TRQ_SEL_FMAP_F0_ADDR 0x7FC
-#define TRQ_SEL_FMAP_F0_RSVD_1_MASK GENMASK(31, 23)
-#define TRQ_SEL_FMAP_F0_QID_MAX_MASK GENMASK(22, 11)
-#define TRQ_SEL_FMAP_F0_QID_BASE_MASK GENMASK(10, 0)
-#define QDMA_S80_HARD_IND_CTXT_DATA_3_ADDR 0x804
-#define IND_CTXT_DATA_3_DATA_MASK GENMASK(31, 0)
-#define QDMA_S80_HARD_IND_CTXT_DATA_2_ADDR 0x808
-#define IND_CTXT_DATA_2_DATA_MASK GENMASK(31, 0)
-#define QDMA_S80_HARD_IND_CTXT_DATA_1_ADDR 0x80C
-#define IND_CTXT_DATA_1_DATA_MASK GENMASK(31, 0)
-#define QDMA_S80_HARD_IND_CTXT_DATA_0_ADDR 0x810
-#define IND_CTXT_DATA_0_DATA_MASK GENMASK(31, 0)
-#define QDMA_S80_HARD_IND_CTXT3_ADDR 0x814
-#define IND_CTXT3_MASK GENMASK(31, 0)
-#define QDMA_S80_HARD_IND_CTXT2_ADDR 0x818
-#define IND_CTXT2_MASK GENMASK(31, 0)
-#define QDMA_S80_HARD_IND_CTXT1_ADDR 0x81C
-#define IND_CTXT1_MASK GENMASK(31, 0)
-#define QDMA_S80_HARD_IND_CTXT0_ADDR 0x820
-#define IND_CTXT0_MASK GENMASK(31, 0)
-#define QDMA_S80_HARD_IND_CTXT_CMD_ADDR 0x824
-#define IND_CTXT_CMD_RSVD_1_MASK GENMASK(31, 18)
-#define IND_CTXT_CMD_QID_MASK GENMASK(17, 7)
-#define IND_CTXT_CMD_OP_MASK GENMASK(6, 5)
-#define IND_CTXT_CMD_SET_MASK GENMASK(4, 1)
-#define IND_CTXT_CMD_BUSY_MASK BIT(0)
-#define QDMA_S80_HARD_C2H_TIMER_CNT_1_ADDR 0xA00
-#define C2H_TIMER_CNT_1_RSVD_1_MASK GENMASK(31, 8)
-#define C2H_TIMER_CNT_1_MASK GENMASK(7, 0)
-#define QDMA_S80_HARD_C2H_TIMER_CNT_2_ADDR 0xA04
-#define C2H_TIMER_CNT_2_RSVD_1_MASK GENMASK(31, 8)
-#define C2H_TIMER_CNT_2_MASK GENMASK(7, 0)
-#define QDMA_S80_HARD_C2H_TIMER_CNT_3_ADDR 0xA08
-#define C2H_TIMER_CNT_3_RSVD_1_MASK GENMASK(31, 8)
-#define C2H_TIMER_CNT_3_MASK GENMASK(7, 0)
-#define QDMA_S80_HARD_C2H_TIMER_CNT_4_ADDR 0xA0C
-#define C2H_TIMER_CNT_4_RSVD_1_MASK GENMASK(31, 8)
-#define C2H_TIMER_CNT_4_MASK GENMASK(7, 0)
-#define QDMA_S80_HARD_C2H_TIMER_CNT_5_ADDR 0xA10
-#define C2H_TIMER_CNT_5_RSVD_1_MASK GENMASK(31, 8)
-#define C2H_TIMER_CNT_5_MASK GENMASK(7, 0)
-#define QDMA_S80_HARD_C2H_TIMER_CNT_6_ADDR 0xA14
-#define C2H_TIMER_CNT_6_RSVD_1_MASK GENMASK(31, 8)
-#define C2H_TIMER_CNT_6_MASK GENMASK(7, 0)
-#define QDMA_S80_HARD_C2H_TIMER_CNT_7_ADDR 0xA18
-#define C2H_TIMER_CNT_7_RSVD_1_MASK GENMASK(31, 8)
-#define C2H_TIMER_CNT_7_MASK GENMASK(7, 0)
-#define QDMA_S80_HARD_C2H_TIMER_CNT_8_ADDR 0xA1C
-#define C2H_TIMER_CNT_8_RSVD_1_MASK GENMASK(31, 8)
-#define C2H_TIMER_CNT_8_MASK GENMASK(7, 0)
-#define QDMA_S80_HARD_C2H_TIMER_CNT_9_ADDR 0xA20
-#define C2H_TIMER_CNT_9_RSVD_1_MASK GENMASK(31, 8)
-#define C2H_TIMER_CNT_9_MASK GENMASK(7, 0)
-#define QDMA_S80_HARD_C2H_TIMER_CNT_A_ADDR 0xA24
-#define C2H_TIMER_CNT_A_RSVD_1_MASK GENMASK(31, 8)
-#define C2H_TIMER_CNT_A_MASK GENMASK(7, 0)
-#define QDMA_S80_HARD_C2H_TIMER_CNT_B_ADDR 0xA28
-#define C2H_TIMER_CNT_B_RSVD_1_MASK GENMASK(31, 8)
-#define C2H_TIMER_CNT_B_MASK GENMASK(7, 0)
-#define QDMA_S80_HARD_C2H_TIMER_CNT_C_ADDR 0xA2C
-#define C2H_TIMER_CNT_C_RSVD_1_MASK GENMASK(31, 8)
-#define C2H_TIMER_CNT_C_MASK GENMASK(7, 0)
-#define QDMA_S80_HARD_C2H_TIMER_CNT_D_ADDR 0xA30
-#define C2H_TIMER_CNT_D_RSVD_1_MASK GENMASK(31, 8)
-#define C2H_TIMER_CNT_D_MASK GENMASK(7, 0)
-#define QDMA_S80_HARD_C2H_TIMER_CNT_E_ADDR 0xA34
-#define C2H_TIMER_CNT_E_RSVD_1_MASK GENMASK(31, 8)
-#define C2H_TIMER_CNT_E_MASK GENMASK(7, 0)
-#define QDMA_S80_HARD_C2H_TIMER_CNT_F_ADDR 0xA38
-#define C2H_TIMER_CNT_F_RSVD_1_MASK GENMASK(31, 8)
-#define C2H_TIMER_CNT_F_MASK GENMASK(7, 0)
-#define QDMA_S80_HARD_C2H_TIMER_CNT_10_ADDR 0xA3C
-#define C2H_TIMER_CNT_10_RSVD_1_MASK GENMASK(31, 8)
-#define C2H_TIMER_CNT_10_MASK GENMASK(7, 0)
-#define QDMA_S80_HARD_C2H_CNT_TH_1_ADDR 0xA40
-#define C2H_CNT_TH_1_RSVD_1_MASK GENMASK(31, 8)
-#define C2H_CNT_TH_1_THESHOLD_CNT_MASK GENMASK(7, 0)
-#define QDMA_S80_HARD_C2H_CNT_TH_2_ADDR 0xA44
-#define C2H_CNT_TH_2_RSVD_1_MASK GENMASK(31, 8)
-#define C2H_CNT_TH_2_THESHOLD_CNT_MASK GENMASK(7, 0)
-#define QDMA_S80_HARD_C2H_CNT_TH_3_ADDR 0xA48
-#define C2H_CNT_TH_3_RSVD_1_MASK GENMASK(31, 8)
-#define C2H_CNT_TH_3_THESHOLD_CNT_MASK GENMASK(7, 0)
-#define QDMA_S80_HARD_C2H_CNT_TH_4_ADDR 0xA4C
-#define C2H_CNT_TH_4_RSVD_1_MASK GENMASK(31, 8)
-#define C2H_CNT_TH_4_THESHOLD_CNT_MASK GENMASK(7, 0)
-#define QDMA_S80_HARD_C2H_CNT_TH_5_ADDR 0xA50
-#define C2H_CNT_TH_5_RSVD_1_MASK GENMASK(31, 8)
-#define C2H_CNT_TH_5_THESHOLD_CNT_MASK GENMASK(7, 0)
-#define QDMA_S80_HARD_C2H_CNT_TH_6_ADDR 0xA54
-#define C2H_CNT_TH_6_RSVD_1_MASK GENMASK(31, 8)
-#define C2H_CNT_TH_6_THESHOLD_CNT_MASK GENMASK(7, 0)
-#define QDMA_S80_HARD_C2H_CNT_TH_7_ADDR 0xA58
-#define C2H_CNT_TH_7_RSVD_1_MASK GENMASK(31, 8)
-#define C2H_CNT_TH_7_THESHOLD_CNT_MASK GENMASK(7, 0)
-#define QDMA_S80_HARD_C2H_CNT_TH_8_ADDR 0xA5C
-#define C2H_CNT_TH_8_RSVD_1_MASK GENMASK(31, 8)
-#define C2H_CNT_TH_8_THESHOLD_CNT_MASK GENMASK(7, 0)
-#define QDMA_S80_HARD_C2H_CNT_TH_9_ADDR 0xA60
-#define C2H_CNT_TH_9_RSVD_1_MASK GENMASK(31, 8)
-#define C2H_CNT_TH_9_THESHOLD_CNT_MASK GENMASK(7, 0)
-#define QDMA_S80_HARD_C2H_CNT_TH_A_ADDR 0xA64
-#define C2H_CNT_TH_A_RSVD_1_MASK GENMASK(31, 8)
-#define C2H_CNT_TH_A_THESHOLD_CNT_MASK GENMASK(7, 0)
-#define QDMA_S80_HARD_C2H_CNT_TH_B_ADDR 0xA68
-#define C2H_CNT_TH_B_RSVD_1_MASK GENMASK(31, 8)
-#define C2H_CNT_TH_B_THESHOLD_CNT_MASK GENMASK(7, 0)
-#define QDMA_S80_HARD_C2H_CNT_TH_C_ADDR 0xA6C
-#define C2H_CNT_TH_C_RSVD_1_MASK GENMASK(31, 8)
-#define C2H_CNT_TH_C_THESHOLD_CNT_MASK GENMASK(7, 0)
-#define QDMA_S80_HARD_C2H_CNT_TH_D_ADDR 0xA70
-#define C2H_CNT_TH_D_RSVD_1_MASK GENMASK(31, 8)
-#define C2H_CNT_TH_D_THESHOLD_CNT_MASK GENMASK(7, 0)
-#define QDMA_S80_HARD_C2H_CNT_TH_E_ADDR 0xA74
-#define C2H_CNT_TH_E_RSVD_1_MASK GENMASK(31, 8)
-#define C2H_CNT_TH_E_THESHOLD_CNT_MASK GENMASK(7, 0)
-#define QDMA_S80_HARD_C2H_CNT_TH_F_ADDR 0xA78
-#define C2H_CNT_TH_F_RSVD_1_MASK GENMASK(31, 8)
-#define C2H_CNT_TH_F_THESHOLD_CNT_MASK GENMASK(7, 0)
-#define QDMA_S80_HARD_C2H_CNT_TH_10_ADDR 0xA7C
-#define C2H_CNT_TH_10_RSVD_1_MASK GENMASK(31, 8)
-#define C2H_CNT_TH_10_THESHOLD_CNT_MASK GENMASK(7, 0)
-#define QDMA_S80_HARD_C2H_QID2VEC_MAP_QID_ADDR 0xA80
-#define C2H_QID2VEC_MAP_QID_RSVD_1_MASK GENMASK(31, 11)
-#define C2H_QID2VEC_MAP_QID_QID_MASK GENMASK(10, 0)
-#define QDMA_S80_HARD_C2H_QID2VEC_MAP_ADDR 0xA84
-#define C2H_QID2VEC_MAP_RSVD_1_MASK GENMASK(31, 19)
-#define C2H_QID2VEC_MAP_H2C_EN_COAL_MASK BIT(18)
-#define C2H_QID2VEC_MAP_H2C_VECTOR_MASK GENMASK(17, 9)
-#define C2H_QID2VEC_MAP_C2H_EN_COAL_MASK BIT(8)
-#define C2H_QID2VEC_MAP_C2H_VECTOR_MASK GENMASK(7, 0)
-#define QDMA_S80_HARD_C2H_STAT_S_AXIS_C2H_ACCEPTED_ADDR 0xA88
-#define C2H_STAT_S_AXIS_C2H_ACCEPTED_MASK GENMASK(31, 0)
-#define QDMA_S80_HARD_C2H_STAT_S_AXIS_WRB_ACCEPTED_ADDR 0xA8C
-#define C2H_STAT_S_AXIS_WRB_ACCEPTED_MASK GENMASK(31, 0)
-#define QDMA_S80_HARD_C2H_STAT_DESC_RSP_PKT_ACCEPTED_ADDR 0xA90
-#define C2H_STAT_DESC_RSP_PKT_ACCEPTED_D_MASK GENMASK(31, 0)
-#define QDMA_S80_HARD_C2H_STAT_AXIS_PKG_CMP_ADDR 0xA94
-#define C2H_STAT_AXIS_PKG_CMP_MASK GENMASK(31, 0)
-#define QDMA_S80_HARD_C2H_STAT_DESC_RSP_ACCEPTED_ADDR 0xA98
-#define C2H_STAT_DESC_RSP_ACCEPTED_D_MASK GENMASK(31, 0)
-#define QDMA_S80_HARD_C2H_STAT_DESC_RSP_CMP_ADDR 0xA9C
-#define C2H_STAT_DESC_RSP_CMP_D_MASK GENMASK(31, 0)
-#define QDMA_S80_HARD_C2H_STAT_WRQ_OUT_ADDR 0xAA0
-#define C2H_STAT_WRQ_OUT_MASK GENMASK(31, 0)
-#define QDMA_S80_HARD_C2H_STAT_WPL_REN_ACCEPTED_ADDR 0xAA4
-#define C2H_STAT_WPL_REN_ACCEPTED_MASK GENMASK(31, 0)
-#define QDMA_S80_HARD_C2H_STAT_TOTAL_WRQ_LEN_ADDR 0xAA8
-#define C2H_STAT_TOTAL_WRQ_LEN_MASK GENMASK(31, 0)
-#define QDMA_S80_HARD_C2H_STAT_TOTAL_WPL_LEN_ADDR 0xAAC
-#define C2H_STAT_TOTAL_WPL_LEN_MASK GENMASK(31, 0)
-#define QDMA_S80_HARD_C2H_BUF_SZ_0_ADDR 0xAB0
-#define C2H_BUF_SZ_0_SIZE_MASK GENMASK(31, 0)
-#define QDMA_S80_HARD_C2H_BUF_SZ_1_ADDR 0xAB4
-#define C2H_BUF_SZ_1_SIZE_MASK GENMASK(31, 0)
-#define QDMA_S80_HARD_C2H_BUF_SZ_2_ADDR 0xAB8
-#define C2H_BUF_SZ_2_SIZE_MASK GENMASK(31, 0)
-#define QDMA_S80_HARD_C2H_BUF_SZ_3_ADDR 0xABC
-#define C2H_BUF_SZ_3_SIZE_MASK GENMASK(31, 0)
-#define QDMA_S80_HARD_C2H_BUF_SZ_4_ADDR 0xAC0
-#define C2H_BUF_SZ_4_SIZE_MASK GENMASK(31, 0)
-#define QDMA_S80_HARD_C2H_BUF_SZ_5_ADDR 0xAC4
-#define C2H_BUF_SZ_5_SIZE_MASK GENMASK(31, 0)
-#define QDMA_S80_HARD_C2H_BUF_SZ_7_ADDR 0XAC8
-#define C2H_BUF_SZ_7_SIZE_MASK GENMASK(31, 0)
-#define QDMA_S80_HARD_C2H_BUF_SZ_8_ADDR 0XACC
-#define C2H_BUF_SZ_8_SIZE_MASK GENMASK(31, 0)
-#define QDMA_S80_HARD_C2H_BUF_SZ_9_ADDR 0xAD0
-#define C2H_BUF_SZ_9_SIZE_MASK GENMASK(31, 0)
-#define QDMA_S80_HARD_C2H_BUF_SZ_10_ADDR 0xAD4
-#define C2H_BUF_SZ_10_SIZE_MASK GENMASK(31, 0)
-#define QDMA_S80_HARD_C2H_BUF_SZ_11_ADDR 0xAD8
-#define C2H_BUF_SZ_11_SIZE_MASK GENMASK(31, 0)
-#define QDMA_S80_HARD_C2H_BUF_SZ_12_ADDR 0xAE0
-#define C2H_BUF_SZ_12_SIZE_MASK GENMASK(31, 0)
-#define QDMA_S80_HARD_C2H_BUF_SZ_13_ADDR 0xAE4
-#define C2H_BUF_SZ_13_SIZE_MASK GENMASK(31, 0)
-#define QDMA_S80_HARD_C2H_BUF_SZ_14_ADDR 0xAE8
-#define C2H_BUF_SZ_14_SIZE_MASK GENMASK(31, 0)
-#define QDMA_S80_HARD_C2H_BUF_SZ_15_ADDR 0XAEC
-#define C2H_BUF_SZ_15_SIZE_MASK GENMASK(31, 0)
-#define QDMA_S80_HARD_C2H_ERR_STAT_ADDR 0xAF0
-#define C2H_ERR_STAT_RSVD_1_MASK GENMASK(31, 16)
-#define C2H_ERR_STAT_WRB_PRTY_ERR_MASK BIT(15)
-#define C2H_ERR_STAT_WRB_CIDX_ERR_MASK BIT(14)
-#define C2H_ERR_STAT_WRB_QFULL_ERR_MASK BIT(13)
-#define C2H_ERR_STAT_WRB_INV_Q_ERR_MASK BIT(12)
-#define C2H_ERR_STAT_PORT_ID_BYP_IN_MISMATCH_MASK BIT(11)
-#define C2H_ERR_STAT_PORT_ID_CTXT_MISMATCH_MASK BIT(10)
-#define C2H_ERR_STAT_ERR_DESC_CNT_MASK BIT(9)
-#define C2H_ERR_STAT_RSVD_2_MASK BIT(8)
-#define C2H_ERR_STAT_MSI_INT_FAIL_MASK BIT(7)
-#define C2H_ERR_STAT_ENG_WPL_DATA_PAR_ERR_MASK BIT(6)
-#define C2H_ERR_STAT_RSVD_3_MASK BIT(5)
-#define C2H_ERR_STAT_DESC_RSP_ERR_MASK BIT(4)
-#define C2H_ERR_STAT_QID_MISMATCH_MASK BIT(3)
-#define C2H_ERR_STAT_RSVD_4_MASK BIT(2)
-#define C2H_ERR_STAT_LEN_MISMATCH_MASK BIT(1)
-#define C2H_ERR_STAT_MTY_MISMATCH_MASK BIT(0)
-#define QDMA_S80_HARD_C2H_ERR_MASK_ADDR 0xAF4
-#define C2H_ERR_EN_MASK GENMASK(31, 0)
-#define QDMA_S80_HARD_C2H_FATAL_ERR_STAT_ADDR 0xAF8
-#define C2H_FATAL_ERR_STAT_RSVD_1_MASK GENMASK(31, 19)
-#define C2H_FATAL_ERR_STAT_WPL_DATA_PAR_ERR_MASK BIT(18)
-#define C2H_FATAL_ERR_STAT_PLD_FIFO_RAM_RDBE_MASK BIT(17)
-#define C2H_FATAL_ERR_STAT_QID_FIFO_RAM_RDBE_MASK BIT(16)
-#define C2H_FATAL_ERR_STAT_TUSER_FIFO_RAM_RDBE_MASK BIT(15)
-#define C2H_FATAL_ERR_STAT_WRB_COAL_DATA_RAM_RDBE_MASK BIT(14)
-#define C2H_FATAL_ERR_STAT_INT_QID2VEC_RAM_RDBE_MASK BIT(13)
-#define C2H_FATAL_ERR_STAT_INT_CTXT_RAM_RDBE_MASK BIT(12)
-#define C2H_FATAL_ERR_STAT_DESC_REQ_FIFO_RAM_RDBE_MASK BIT(11)
-#define C2H_FATAL_ERR_STAT_PFCH_CTXT_RAM_RDBE_MASK BIT(10)
-#define C2H_FATAL_ERR_STAT_WRB_CTXT_RAM_RDBE_MASK BIT(9)
-#define C2H_FATAL_ERR_STAT_PFCH_LL_RAM_RDBE_MASK BIT(8)
-#define C2H_FATAL_ERR_STAT_TIMER_FIFO_RAM_RDBE_MASK GENMASK(7, 4)
-#define C2H_FATAL_ERR_STAT_QID_MISMATCH_MASK BIT(3)
-#define C2H_FATAL_ERR_STAT_RSVD_2_MASK BIT(2)
-#define C2H_FATAL_ERR_STAT_LEN_MISMATCH_MASK BIT(1)
-#define C2H_FATAL_ERR_STAT_MTY_MISMATCH_MASK BIT(0)
-#define QDMA_S80_HARD_C2H_FATAL_ERR_MASK_ADDR 0xAFC
-#define C2H_FATAL_ERR_C2HEN_MASK GENMASK(31, 0)
-#define QDMA_S80_HARD_C2H_FATAL_ERR_ENABLE_ADDR 0xB00
-#define C2H_FATAL_ERR_ENABLE_RSVD_1_MASK GENMASK(31, 2)
-#define C2H_FATAL_ERR_ENABLE_WPL_PAR_INV_MASK BIT(1)
-#define C2H_FATAL_ERR_ENABLE_WRQ_DIS_MASK BIT(0)
-#define QDMA_S80_HARD_GLBL_ERR_INT_ADDR 0xB04
-#define GLBL_ERR_INT_RSVD_1_MASK GENMASK(31, 18)
-#define GLBL_ERR_INT_ARM_MASK BIT(17)
-#define GLBL_ERR_INT_EN_COAL_MASK BIT(16)
-#define GLBL_ERR_INT_VEC_MASK GENMASK(15, 8)
-#define GLBL_ERR_INT_FUNC_MASK GENMASK(7, 0)
-#define QDMA_S80_HARD_C2H_PFCH_CFG_ADDR 0xB08
-#define C2H_PFCH_CFG_EVT_QCNT_TH_MASK GENMASK(31, 25)
-#define C2H_PFCH_CFG_QCNT_MASK GENMASK(24, 16)
-#define C2H_PFCH_CFG_NUM_MASK GENMASK(15, 8)
-#define C2H_PFCH_CFG_FL_TH_MASK GENMASK(7, 0)
-#define QDMA_S80_HARD_C2H_INT_TIMER_TICK_ADDR 0xB0C
-#define C2H_INT_TIMER_TICK_MASK GENMASK(31, 0)
-#define QDMA_S80_HARD_C2H_STAT_DESC_RSP_DROP_ACCEPTED_ADDR 0xB10
-#define C2H_STAT_DESC_RSP_DROP_ACCEPTED_D_MASK GENMASK(31, 0)
-#define QDMA_S80_HARD_C2H_STAT_DESC_RSP_ERR_ACCEPTED_ADDR 0xB14
-#define C2H_STAT_DESC_RSP_ERR_ACCEPTED_D_MASK GENMASK(31, 0)
-#define QDMA_S80_HARD_C2H_STAT_DESC_REQ_ADDR 0xB18
-#define C2H_STAT_DESC_REQ_MASK GENMASK(31, 0)
-#define QDMA_S80_HARD_C2H_STAT_DBG_DMA_ENG_0_ADDR 0xB1C
-#define C2H_STAT_DMA_ENG_0_RSVD_1_MASK BIT(31)
-#define C2H_STAT_DMA_ENG_0_WRB_FIFO_OUT_CNT_MASK GENMASK(30, 28)
-#define C2H_STAT_DMA_ENG_0_QID_FIFO_OUT_CNT_MASK GENMASK(27, 18)
-#define C2H_STAT_DMA_ENG_0_PLD_FIFO_OUT_CNT_MASK GENMASK(17, 8)
-#define C2H_STAT_DMA_ENG_0_WRQ_FIFO_OUT_CNT_MASK GENMASK(7, 5)
-#define C2H_STAT_DMA_ENG_0_WRB_SM_CS_MASK BIT(4)
-#define C2H_STAT_DMA_ENG_0_MAIN_SM_CS_MASK GENMASK(3, 0)
-#define QDMA_S80_HARD_C2H_STAT_DBG_DMA_ENG_1_ADDR 0xB20
-#define C2H_STAT_DMA_ENG_1_RSVD_1_MASK BIT(31)
-#define C2H_STAT_DMA_ENG_1_DESC_RSP_LAST_MASK BIT(30)
-#define C2H_STAT_DMA_ENG_1_PLD_FIFO_IN_CNT_MASK GENMASK(29, 20)
-#define C2H_STAT_DMA_ENG_1_PLD_FIFO_OUTPUT_CNT_MASK GENMASK(19, 10)
-#define C2H_STAT_DMA_ENG_1_QID_FIFO_IN_CNT_MASK GENMASK(9, 0)
-#define QDMA_S80_HARD_C2H_STAT_DBG_DMA_ENG_2_ADDR 0xB24
-#define C2H_STAT_DMA_ENG_2_RSVD_1_MASK GENMASK(31, 30)
-#define C2H_STAT_DMA_ENG_2_WRB_FIFO_IN_CNT_MASK GENMASK(29, 20)
-#define C2H_STAT_DMA_ENG_2_WRB_FIFO_OUTPUT_CNT_MASK GENMASK(19, 10)
-#define C2H_STAT_DMA_ENG_2_QID_FIFO_OUTPUT_CNT_MASK GENMASK(9, 0)
-#define QDMA_S80_HARD_C2H_STAT_DBG_DMA_ENG_3_ADDR 0xB28
-#define C2H_STAT_DMA_ENG_3_RSVD_1_MASK GENMASK(31, 30)
-#define C2H_STAT_DMA_ENG_3_ADDR_4K_SPLIT_CNT_MASK GENMASK(29, 20)
-#define C2H_STAT_DMA_ENG_3_WRQ_FIFO_IN_CNT_MASK GENMASK(19, 10)
-#define C2H_STAT_DMA_ENG_3_WRQ_FIFO_OUTPUT_CNT_MASK GENMASK(9, 0)
-#define QDMA_S80_HARD_C2H_DBG_PFCH_ERR_CTXT_ADDR 0xB2C
-#define C2H_PFCH_ERR_CTXT_RSVD_1_MASK GENMASK(31, 14)
-#define C2H_PFCH_ERR_CTXT_ERR_STAT_MASK BIT(13)
-#define C2H_PFCH_ERR_CTXT_CMD_WR_MASK BIT(12)
-#define C2H_PFCH_ERR_CTXT_QID_MASK GENMASK(11, 1)
-#define C2H_PFCH_ERR_CTXT_DONE_MASK BIT(0)
-#define QDMA_S80_HARD_C2H_FIRST_ERR_QID_ADDR 0xB30
-#define C2H_FIRST_ERR_QID_RSVD_1_MASK GENMASK(31, 21)
-#define C2H_FIRST_ERR_QID_ERR_STAT_MASK GENMASK(20, 16)
-#define C2H_FIRST_ERR_QID_CMD_WR_MASK GENMASK(15, 12)
-#define C2H_FIRST_ERR_QID_QID_MASK GENMASK(11, 0)
-#define QDMA_S80_HARD_STAT_NUM_WRB_IN_ADDR 0xB34
-#define STAT_NUM_WRB_IN_RSVD_1_MASK GENMASK(31, 16)
-#define STAT_NUM_WRB_IN_WRB_CNT_MASK GENMASK(15, 0)
-#define QDMA_S80_HARD_STAT_NUM_WRB_OUT_ADDR 0xB38
-#define STAT_NUM_WRB_OUT_RSVD_1_MASK GENMASK(31, 16)
-#define STAT_NUM_WRB_OUT_WRB_CNT_MASK GENMASK(15, 0)
-#define QDMA_S80_HARD_STAT_NUM_WRB_DRP_ADDR 0xB3C
-#define STAT_NUM_WRB_DRP_RSVD_1_MASK GENMASK(31, 16)
-#define STAT_NUM_WRB_DRP_WRB_CNT_MASK GENMASK(15, 0)
-#define QDMA_S80_HARD_STAT_NUM_STAT_DESC_OUT_ADDR 0xB40
-#define STAT_NUM_STAT_DESC_OUT_RSVD_1_MASK GENMASK(31, 16)
-#define STAT_NUM_STAT_DESC_OUT_CNT_MASK GENMASK(15, 0)
-#define QDMA_S80_HARD_STAT_NUM_DSC_CRDT_SENT_ADDR 0xB44
-#define STAT_NUM_DSC_CRDT_SENT_RSVD_1_MASK GENMASK(31, 16)
-#define STAT_NUM_DSC_CRDT_SENT_CNT_MASK GENMASK(15, 0)
-#define QDMA_S80_HARD_STAT_NUM_FCH_DSC_RCVD_ADDR 0xB48
-#define STAT_NUM_FCH_DSC_RCVD_RSVD_1_MASK GENMASK(31, 16)
-#define STAT_NUM_FCH_DSC_RCVD_DSC_CNT_MASK GENMASK(15, 0)
-#define QDMA_S80_HARD_STAT_NUM_BYP_DSC_RCVD_ADDR 0xB4C
-#define STAT_NUM_BYP_DSC_RCVD_RSVD_1_MASK GENMASK(31, 11)
-#define STAT_NUM_BYP_DSC_RCVD_DSC_CNT_MASK GENMASK(10, 0)
-#define QDMA_S80_HARD_C2H_WRB_COAL_CFG_ADDR 0xB50
-#define C2H_WRB_COAL_CFG_MAX_BUF_SZ_MASK GENMASK(31, 26)
-#define C2H_WRB_COAL_CFG_TICK_VAL_MASK GENMASK(25, 14)
-#define C2H_WRB_COAL_CFG_TICK_CNT_MASK GENMASK(13, 2)
-#define C2H_WRB_COAL_CFG_SET_GLB_FLUSH_MASK BIT(1)
-#define C2H_WRB_COAL_CFG_DONE_GLB_FLUSH_MASK BIT(0)
-#define QDMA_S80_HARD_C2H_INTR_H2C_REQ_ADDR 0xB54
-#define C2H_INTR_H2C_REQ_RSVD_1_MASK GENMASK(31, 18)
-#define C2H_INTR_H2C_REQ_CNT_MASK GENMASK(17, 0)
-#define QDMA_S80_HARD_C2H_INTR_C2H_MM_REQ_ADDR 0xB58
-#define C2H_INTR_C2H_MM_REQ_RSVD_1_MASK GENMASK(31, 18)
-#define C2H_INTR_C2H_MM_REQ_CNT_MASK GENMASK(17, 0)
-#define QDMA_S80_HARD_C2H_INTR_ERR_INT_REQ_ADDR 0xB5C
-#define C2H_INTR_ERR_INT_REQ_RSVD_1_MASK GENMASK(31, 18)
-#define C2H_INTR_ERR_INT_REQ_CNT_MASK GENMASK(17, 0)
-#define QDMA_S80_HARD_C2H_INTR_C2H_ST_REQ_ADDR 0xB60
-#define C2H_INTR_C2H_ST_REQ_RSVD_1_MASK GENMASK(31, 18)
-#define C2H_INTR_C2H_ST_REQ_CNT_MASK GENMASK(17, 0)
-#define QDMA_S80_HARD_C2H_INTR_H2C_ERR_C2H_MM_MSIX_ACK_ADDR 0xB64
-#define C2H_INTR_H2C_ERR_C2H_MM_MSIX_ACK_RSVD_1_MASK GENMASK(31, 18)
-#define C2H_INTR_H2C_ERR_C2H_MM_MSIX_ACK_CNT_MASK GENMASK(17, 0)
-#define QDMA_S80_HARD_C2H_INTR_H2C_ERR_C2H_MM_MSIX_FAIL_ADDR 0xB68
-#define C2H_INTR_H2C_ERR_C2H_MM_MSIX_FAIL_RSVD_1_MASK GENMASK(31, 18)
-#define C2H_INTR_H2C_ERR_C2H_MM_MSIX_FAIL_CNT_MASK GENMASK(17, 0)
-#define QDMA_S80_HARD_C2H_INTR_H2C_ERR_C2H_MM_MSIX_NO_MSIX_ADDR 0xB6C
-#define C2H_INTR_H2C_ERR_C2H_MM_MSIX_NO_MSIX_RSVD_1_MASK GENMASK(31, 18)
-#define C2H_INTR_H2C_ERR_C2H_MM_MSIX_NO_MSIX_CNT_MASK GENMASK(17, 0)
-#define QDMA_S80_HARD_C2H_INTR_H2C_ERR_C2H_MM_CTXT_INVAL_ADDR 0xB70
-#define C2H_INTR_H2C_ERR_C2H_MM_CTXT_INVAL_RSVD_1_MASK GENMASK(31, 18)
-#define C2H_INTR_H2C_ERR_C2H_MM_CTXT_INVAL_CNT_MASK GENMASK(17, 0)
-#define QDMA_S80_HARD_C2H_INTR_C2H_ST_MSIX_ACK_ADDR 0xB74
-#define C2H_INTR_C2H_ST_MSIX_ACK_RSVD_1_MASK GENMASK(31, 18)
-#define C2H_INTR_C2H_ST_MSIX_ACK_CNT_MASK GENMASK(17, 0)
-#define QDMA_S80_HARD_C2H_INTR_C2H_ST_MSIX_FAIL_ADDR 0xB78
-#define C2H_INTR_C2H_ST_MSIX_FAIL_RSVD_1_MASK GENMASK(31, 18)
-#define C2H_INTR_C2H_ST_MSIX_FAIL_CNT_MASK GENMASK(17, 0)
-#define QDMA_S80_HARD_C2H_INTR_C2H_ST_NO_MSIX_ADDR 0xB7C
-#define C2H_INTR_C2H_ST_NO_MSIX_RSVD_1_MASK GENMASK(31, 18)
-#define C2H_INTR_C2H_ST_NO_MSIX_CNT_MASK GENMASK(17, 0)
-#define QDMA_S80_HARD_C2H_INTR_C2H_ST_CTXT_INVAL_ADDR 0xB80
-#define C2H_INTR_C2H_ST_CTXT_INVAL_RSVD_1_MASK GENMASK(31, 18)
-#define C2H_INTR_C2H_ST_CTXT_INVAL_CNT_MASK GENMASK(17, 0)
-#define QDMA_S80_HARD_C2H_STAT_WR_CMP_ADDR 0xB84
-#define C2H_STAT_WR_CMP_RSVD_1_MASK GENMASK(31, 18)
-#define C2H_STAT_WR_CMP_CNT_MASK GENMASK(17, 0)
-#define QDMA_S80_HARD_C2H_STAT_DBG_DMA_ENG_4_ADDR 0xB88
-#define C2H_STAT_DMA_ENG_4_TUSER_FIFO_OUT_VLD_MASK BIT(31)
-#define C2H_STAT_DMA_ENG_4_WRB_FIFO_IN_RDY_MASK BIT(30)
-#define C2H_STAT_DMA_ENG_4_TUSER_FIFO_IN_CNT_MASK GENMASK(29, 20)
-#define C2H_STAT_DMA_ENG_4_TUSER_FIFO_OUTPUT_CNT_MASK GENMASK(19, 10)
-#define C2H_STAT_DMA_ENG_4_TUSER_FIFO_OUT_CNT_MASK GENMASK(9, 0)
-#define QDMA_S80_HARD_C2H_STAT_DBG_DMA_ENG_5_ADDR 0xB8C
-#define C2H_STAT_DMA_ENG_5_RSVD_1_MASK GENMASK(31, 25)
-#define C2H_STAT_DMA_ENG_5_TUSER_COMB_OUT_VLD_MASK BIT(24)
-#define C2H_STAT_DMA_ENG_5_TUSER_FIFO_IN_RDY_MASK BIT(23)
-#define C2H_STAT_DMA_ENG_5_TUSER_COMB_IN_CNT_MASK GENMASK(22, 13)
-#define C2H_STAT_DMA_ENG_5_TUSE_COMB_OUTPUT_CNT_MASK GENMASK(12, 3)
-#define C2H_STAT_DMA_ENG_5_TUSER_COMB_CNT_MASK GENMASK(2, 0)
-#define QDMA_S80_HARD_C2H_DBG_PFCH_QID_ADDR 0xB90
-#define C2H_PFCH_QID_RSVD_1_MASK GENMASK(31, 15)
-#define C2H_PFCH_QID_ERR_CTXT_MASK BIT(14)
-#define C2H_PFCH_QID_TARGET_MASK GENMASK(13, 11)
-#define C2H_PFCH_QID_QID_OR_TAG_MASK GENMASK(10, 0)
-#define QDMA_S80_HARD_C2H_DBG_PFCH_ADDR 0xB94
-#define C2H_PFCH_DATA_MASK GENMASK(31, 0)
-#define QDMA_S80_HARD_C2H_INT_DBG_ADDR 0xB98
-#define C2H_INT_RSVD_1_MASK GENMASK(31, 8)
-#define C2H_INT_INT_COAL_SM_MASK GENMASK(7, 4)
-#define C2H_INT_INT_SM_MASK GENMASK(3, 0)
-#define QDMA_S80_HARD_C2H_STAT_IMM_ACCEPTED_ADDR 0xB9C
-#define C2H_STAT_IMM_ACCEPTED_RSVD_1_MASK GENMASK(31, 18)
-#define C2H_STAT_IMM_ACCEPTED_CNT_MASK GENMASK(17, 0)
-#define QDMA_S80_HARD_C2H_STAT_MARKER_ACCEPTED_ADDR 0xBA0
-#define C2H_STAT_MARKER_ACCEPTED_RSVD_1_MASK GENMASK(31, 18)
-#define C2H_STAT_MARKER_ACCEPTED_CNT_MASK GENMASK(17, 0)
-#define QDMA_S80_HARD_C2H_STAT_DISABLE_CMP_ACCEPTED_ADDR 0xBA4
-#define C2H_STAT_DISABLE_CMP_ACCEPTED_RSVD_1_MASK GENMASK(31, 18)
-#define C2H_STAT_DISABLE_CMP_ACCEPTED_CNT_MASK GENMASK(17, 0)
-#define QDMA_S80_HARD_C2H_PLD_FIFO_CRDT_CNT_ADDR 0xBA8
-#define C2H_PLD_FIFO_CRDT_CNT_RSVD_1_MASK GENMASK(31, 18)
-#define C2H_PLD_FIFO_CRDT_CNT_CNT_MASK GENMASK(17, 0)
-#define QDMA_S80_HARD_H2C_ERR_STAT_ADDR 0xE00
-#define H2C_ERR_STAT_RSVD_1_MASK GENMASK(31, 5)
-#define H2C_ERR_STAT_SBE_MASK BIT(4)
-#define H2C_ERR_STAT_DBE_MASK BIT(3)
-#define H2C_ERR_STAT_NO_DMA_DS_MASK BIT(2)
-#define H2C_ERR_STAT_SDI_MRKR_REQ_MOP_ERR_MASK BIT(1)
-#define H2C_ERR_STAT_ZERO_LEN_DS_MASK BIT(0)
-#define QDMA_S80_HARD_H2C_ERR_MASK_ADDR 0xE04
-#define H2C_ERR_EN_MASK GENMASK(31, 0)
-#define QDMA_S80_HARD_H2C_FIRST_ERR_QID_ADDR 0xE08
-#define H2C_FIRST_ERR_QID_RSVD_1_MASK GENMASK(31, 20)
-#define H2C_FIRST_ERR_QID_ERR_TYPE_MASK GENMASK(19, 16)
-#define H2C_FIRST_ERR_QID_RSVD_2_MASK GENMASK(15, 12)
-#define H2C_FIRST_ERR_QID_QID_MASK GENMASK(11, 0)
-#define QDMA_S80_HARD_H2C_DBG_REG0_ADDR 0xE0C
-#define H2C_REG0_NUM_DSC_RCVD_MASK GENMASK(31, 16)
-#define H2C_REG0_NUM_WRB_SENT_MASK GENMASK(15, 0)
-#define QDMA_S80_HARD_H2C_DBG_REG1_ADDR 0xE10
-#define H2C_REG1_NUM_REQ_SENT_MASK GENMASK(31, 16)
-#define H2C_REG1_NUM_CMP_SENT_MASK GENMASK(15, 0)
-#define QDMA_S80_HARD_H2C_DBG_REG2_ADDR 0xE14
-#define H2C_REG2_RSVD_1_MASK GENMASK(31, 16)
-#define H2C_REG2_NUM_ERR_DSC_RCVD_MASK GENMASK(15, 0)
-#define QDMA_S80_HARD_H2C_DBG_REG3_ADDR 0xE18
-#define H2C_REG3_MASK BIT(31)
-#define H2C_REG3_DSCO_FIFO_EMPTY_MASK BIT(30)
-#define H2C_REG3_DSCO_FIFO_FULL_MASK BIT(29)
-#define H2C_REG3_CUR_RC_STATE_MASK GENMASK(28, 26)
-#define H2C_REG3_RDREQ_LINES_MASK GENMASK(25, 16)
-#define H2C_REG3_RDATA_LINES_AVAIL_MASK GENMASK(15, 6)
-#define H2C_REG3_PEND_FIFO_EMPTY_MASK BIT(5)
-#define H2C_REG3_PEND_FIFO_FULL_MASK BIT(4)
-#define H2C_REG3_CUR_RQ_STATE_MASK GENMASK(3, 2)
-#define H2C_REG3_DSCI_FIFO_FULL_MASK BIT(1)
-#define H2C_REG3_DSCI_FIFO_EMPTY_MASK BIT(0)
-#define QDMA_S80_HARD_H2C_DBG_REG4_ADDR 0xE1C
-#define H2C_REG4_RDREQ_ADDR_MASK GENMASK(31, 0)
-#define QDMA_S80_HARD_H2C_FATAL_ERR_EN_ADDR 0xE20
-#define H2C_FATAL_ERR_EN_RSVD_1_MASK GENMASK(31, 1)
-#define H2C_FATAL_ERR_EN_H2C_MASK BIT(0)
-#define QDMA_S80_HARD_C2H_CHANNEL_CTL_ADDR 0x1004
-#define C2H_CHANNEL_CTL_RSVD_1_MASK GENMASK(31, 1)
-#define C2H_CHANNEL_CTL_RUN_MASK BIT(0)
-#define QDMA_S80_HARD_C2H_CHANNEL_CTL_1_ADDR 0x1008
-#define C2H_CHANNEL_CTL_1_RUN_MASK GENMASK(31, 1)
-#define C2H_CHANNEL_CTL_1_RUN_1_MASK BIT(0)
-#define QDMA_S80_HARD_C2H_MM_STATUS_ADDR 0x1040
-#define C2H_MM_STATUS_RSVD_1_MASK GENMASK(31, 1)
-#define C2H_MM_STATUS_RUN_MASK BIT(0)
-#define QDMA_S80_HARD_C2H_CHANNEL_CMPL_DESC_CNT_ADDR 0x1048
-#define C2H_CHANNEL_CMPL_DESC_CNT_C2H_CO_MASK GENMASK(31, 0)
-#define QDMA_S80_HARD_C2H_MM_ERR_CODE_ENABLE_MASK_ADDR 0x1054
-#define C2H_MM_ERR_CODE_ENABLE_RSVD_1_MASK BIT(31)
-#define C2H_MM_ERR_CODE_ENABLE_WR_UC_RAM_MASK BIT(30)
-#define C2H_MM_ERR_CODE_ENABLE_WR_UR_MASK BIT(29)
-#define C2H_MM_ERR_CODE_ENABLE_WR_FLR_MASK BIT(28)
-#define C2H_MM_ERR_CODE_ENABLE_RSVD_2_MASK GENMASK(27, 2)
-#define C2H_MM_ERR_CODE_ENABLE_RD_SLV_ERR_MASK BIT(1)
-#define C2H_MM_ERR_CODE_ENABLE_WR_SLV_ERR_MASK BIT(0)
-#define QDMA_S80_HARD_C2H_MM_ERR_CODE_ADDR 0x1058
-#define C2H_MM_ERR_CODE_RSVD_1_MASK GENMASK(31, 18)
-#define C2H_MM_ERR_CODE_VALID_MASK BIT(17)
-#define C2H_MM_ERR_CODE_RDWR_MASK BIT(16)
-#define C2H_MM_ERR_CODE_MASK GENMASK(4, 0)
-#define QDMA_S80_HARD_C2H_MM_ERR_INFO_ADDR 0x105C
-#define C2H_MM_ERR_INFO_RSVD_1_MASK GENMASK(31, 29)
-#define C2H_MM_ERR_INFO_QID_MASK GENMASK(28, 17)
-#define C2H_MM_ERR_INFO_DIR_MASK BIT(16)
-#define C2H_MM_ERR_INFO_CIDX_MASK GENMASK(15, 0)
-#define QDMA_S80_HARD_C2H_MM_PERF_MON_CTL_ADDR 0x10C0
-#define C2H_MM_PERF_MON_CTL_RSVD_1_MASK GENMASK(31, 4)
-#define C2H_MM_PERF_MON_CTL_IMM_START_MASK BIT(3)
-#define C2H_MM_PERF_MON_CTL_RUN_START_MASK BIT(2)
-#define C2H_MM_PERF_MON_CTL_IMM_CLEAR_MASK BIT(1)
-#define C2H_MM_PERF_MON_CTL_RUN_CLEAR_MASK BIT(0)
-#define QDMA_S80_HARD_C2H_MM_PERF_MON_CYCLE_CNT0_ADDR 0x10C4
-#define C2H_MM_PERF_MON_CYCLE_CNT0_CYC_CNT_MASK GENMASK(31, 0)
-#define QDMA_S80_HARD_C2H_MM_PERF_MON_CYCLE_CNT1_ADDR 0x10C8
-#define C2H_MM_PERF_MON_CYCLE_CNT1_RSVD_1_MASK GENMASK(31, 10)
-#define C2H_MM_PERF_MON_CYCLE_CNT1_CYC_CNT_MASK GENMASK(9, 0)
-#define QDMA_S80_HARD_C2H_MM_PERF_MON_DATA_CNT0_ADDR 0x10CC
-#define C2H_MM_PERF_MON_DATA_CNT0_DCNT_MASK GENMASK(31, 0)
-#define QDMA_S80_HARD_C2H_MM_PERF_MON_DATA_CNT1_ADDR 0x10D0
-#define C2H_MM_PERF_MON_DATA_CNT1_RSVD_1_MASK GENMASK(31, 10)
-#define C2H_MM_PERF_MON_DATA_CNT1_DCNT_MASK GENMASK(9, 0)
-#define QDMA_S80_HARD_C2H_MM_DBG_ADDR 0x10E8
-#define C2H_MM_RSVD_1_MASK GENMASK(31, 24)
-#define C2H_MM_RRQ_ENTRIES_MASK GENMASK(23, 17)
-#define C2H_MM_DAT_FIFO_SPC_MASK GENMASK(16, 7)
-#define C2H_MM_RD_STALL_MASK BIT(6)
-#define C2H_MM_RRQ_FIFO_FI_MASK BIT(5)
-#define C2H_MM_WR_STALL_MASK BIT(4)
-#define C2H_MM_WRQ_FIFO_FI_MASK BIT(3)
-#define C2H_MM_WBK_STALL_MASK BIT(2)
-#define C2H_MM_DSC_FIFO_EP_MASK BIT(1)
-#define C2H_MM_DSC_FIFO_FL_MASK BIT(0)
-#define QDMA_S80_HARD_H2C_CHANNEL_CTL_ADDR 0x1204
-#define H2C_CHANNEL_CTL_RSVD_1_MASK GENMASK(31, 1)
-#define H2C_CHANNEL_CTL_RUN_MASK BIT(0)
-#define QDMA_S80_HARD_H2C_CHANNEL_CTL_1_ADDR 0x1208
-#define H2C_CHANNEL_CTL_1_RUN_MASK BIT(0)
-#define QDMA_S80_HARD_H2C_CHANNEL_CTL_2_ADDR 0x120C
-#define H2C_CHANNEL_CTL_2_RUN_MASK BIT(0)
-#define QDMA_S80_HARD_H2C_MM_STATUS_ADDR 0x1240
-#define H2C_MM_STATUS_RSVD_1_MASK GENMASK(31, 1)
-#define H2C_MM_STATUS_RUN_MASK BIT(0)
-#define QDMA_S80_HARD_H2C_CHANNEL_CMPL_DESC_CNT_ADDR 0x1248
-#define H2C_CHANNEL_CMPL_DESC_CNT_H2C_CO_MASK GENMASK(31, 0)
-#define QDMA_S80_HARD_H2C_MM_ERR_CODE_ENABLE_MASK_ADDR 0x1254
-#define H2C_MM_ERR_CODE_ENABLE_RSVD_1_MASK GENMASK(31, 30)
-#define H2C_MM_ERR_CODE_ENABLE_WR_SLV_ERR_MASK BIT(29)
-#define H2C_MM_ERR_CODE_ENABLE_WR_DEC_ERR_MASK BIT(28)
-#define H2C_MM_ERR_CODE_ENABLE_RSVD_2_MASK GENMASK(27, 23)
-#define H2C_MM_ERR_CODE_ENABLE_RD_RQ_DIS_ERR_MASK BIT(22)
-#define H2C_MM_ERR_CODE_ENABLE_RSVD_3_MASK GENMASK(21, 17)
-#define H2C_MM_ERR_CODE_ENABLE_RD_DAT_POISON_ERR_MASK BIT(16)
-#define H2C_MM_ERR_CODE_ENABLE_RSVD_4_MASK GENMASK(15, 9)
-#define H2C_MM_ERR_CODE_ENABLE_RD_FLR_ERR_MASK BIT(8)
-#define H2C_MM_ERR_CODE_ENABLE_RSVD_5_MASK GENMASK(7, 6)
-#define H2C_MM_ERR_CODE_ENABLE_RD_HDR_ADR_ERR_MASK BIT(5)
-#define H2C_MM_ERR_CODE_ENABLE_RD_HDR_PARA_MASK BIT(4)
-#define H2C_MM_ERR_CODE_ENABLE_RD_HDR_BYTE_ERR_MASK BIT(3)
-#define H2C_MM_ERR_CODE_ENABLE_RD_UR_CA_MASK BIT(2)
-#define H2C_MM_ERR_CODE_ENABLE_RD_HRD_POISON_ERR_MASK BIT(1)
-#define H2C_MM_ERR_CODE_ENABLE_RSVD_6_MASK BIT(0)
-#define QDMA_S80_HARD_H2C_MM_ERR_CODE_ADDR 0x1258
-#define H2C_MM_ERR_CODE_RSVD_1_MASK GENMASK(31, 18)
-#define H2C_MM_ERR_CODE_VALID_MASK BIT(17)
-#define H2C_MM_ERR_CODE_RDWR_MASK BIT(16)
-#define H2C_MM_ERR_CODE_MASK GENMASK(4, 0)
-#define QDMA_S80_HARD_H2C_MM_ERR_INFO_ADDR 0x125C
-#define H2C_MM_ERR_INFO_RSVD_1_MASK GENMASK(31, 29)
-#define H2C_MM_ERR_INFO_QID_MASK GENMASK(28, 17)
-#define H2C_MM_ERR_INFO_DIR_MASK BIT(16)
-#define H2C_MM_ERR_INFO_CIDX_MASK GENMASK(15, 0)
-#define QDMA_S80_HARD_H2C_MM_PERF_MON_CTL_ADDR 0x12C0
-#define H2C_MM_PERF_MON_CTL_RSVD_1_MASK GENMASK(31, 4)
-#define H2C_MM_PERF_MON_CTL_IMM_START_MASK BIT(3)
-#define H2C_MM_PERF_MON_CTL_RUN_START_MASK BIT(2)
-#define H2C_MM_PERF_MON_CTL_IMM_CLEAR_MASK BIT(1)
-#define H2C_MM_PERF_MON_CTL_RUN_CLEAR_MASK BIT(0)
-#define QDMA_S80_HARD_H2C_MM_PERF_MON_CYCLE_CNT0_ADDR 0x12C4
-#define H2C_MM_PERF_MON_CYCLE_CNT0_CYC_CNT_MASK GENMASK(31, 0)
-#define QDMA_S80_HARD_H2C_MM_PERF_MON_CYCLE_CNT1_ADDR 0x12C8
-#define H2C_MM_PERF_MON_CYCLE_CNT1_RSVD_1_MASK GENMASK(31, 10)
-#define H2C_MM_PERF_MON_CYCLE_CNT1_CYC_CNT_MASK GENMASK(9, 0)
-#define QDMA_S80_HARD_H2C_MM_PERF_MON_DATA_CNT0_ADDR 0x12CC
-#define H2C_MM_PERF_MON_DATA_CNT0_DCNT_MASK GENMASK(31, 0)
-#define QDMA_S80_HARD_H2C_MM_PERF_MON_DATA_CNT1_ADDR 0x12D0
-#define H2C_MM_PERF_MON_DATA_CNT1_RSVD_1_MASK GENMASK(31, 10)
-#define H2C_MM_PERF_MON_DATA_CNT1_DCNT_MASK GENMASK(9, 0)
-#define QDMA_S80_HARD_H2C_MM_DBG_ADDR 0x12E8
-#define H2C_MM_RSVD_1_MASK GENMASK(31, 24)
-#define H2C_MM_RRQ_ENTRIES_MASK GENMASK(23, 17)
-#define H2C_MM_DAT_FIFO_SPC_MASK GENMASK(16, 7)
-#define H2C_MM_RD_STALL_MASK BIT(6)
-#define H2C_MM_RRQ_FIFO_FI_MASK BIT(5)
-#define H2C_MM_WR_STALL_MASK BIT(4)
-#define H2C_MM_WRQ_FIFO_FI_MASK BIT(3)
-#define H2C_MM_WBK_STALL_MASK BIT(2)
-#define H2C_MM_DSC_FIFO_EP_MASK BIT(1)
-#define H2C_MM_DSC_FIFO_FL_MASK BIT(0)
-#define QDMA_S80_HARD_FUNC_STATUS_REG_ADDR 0x2400
-#define FUNC_STATUS_REG_RSVD_1_MASK GENMASK(31, 12)
-#define FUNC_STATUS_REG_CUR_SRC_FN_MASK GENMASK(11, 4)
-#define FUNC_STATUS_REG_ACK_MASK BIT(2)
-#define FUNC_STATUS_REG_O_MSG_MASK BIT(1)
-#define FUNC_STATUS_REG_I_MSG_MASK BIT(0)
-#define QDMA_S80_HARD_FUNC_CMD_REG_ADDR 0x2404
-#define FUNC_CMD_REG_RSVD_1_MASK GENMASK(31, 3)
-#define FUNC_CMD_REG_RSVD_2_MASK BIT(2)
-#define FUNC_CMD_REG_MSG_RCV_MASK BIT(1)
-#define FUNC_CMD_REG_MSG_SENT_MASK BIT(0)
-#define QDMA_S80_HARD_FUNC_INTERRUPT_VECTOR_REG_ADDR 0x2408
-#define FUNC_INTERRUPT_VECTOR_REG_RSVD_1_MASK GENMASK(31, 5)
-#define FUNC_INTERRUPT_VECTOR_REG_IN_MASK GENMASK(4, 0)
-#define QDMA_S80_HARD_TARGET_FUNC_REG_ADDR 0x240C
-#define TARGET_FUNC_REG_RSVD_1_MASK GENMASK(31, 8)
-#define TARGET_FUNC_REG_N_ID_MASK GENMASK(7, 0)
-#define QDMA_S80_HARD_FUNC_INTERRUPT_CTL_REG_ADDR 0x2410
-#define FUNC_INTERRUPT_CTL_REG_RSVD_1_MASK GENMASK(31, 1)
-#define FUNC_INTERRUPT_CTL_REG_INT_EN_MASK BIT(0)
-#define SW_IND_CTXT_DATA_W3_DSC_BASE_H_MASK GENMASK(31, 0)
-#define SW_IND_CTXT_DATA_W2_DSC_BASE_L_MASK GENMASK(31, 0)
-#define SW_IND_CTXT_DATA_W1_IS_MM_MASK BIT(31)
-#define SW_IND_CTXT_DATA_W1_MRKR_DIS_MASK BIT(30)
-#define SW_IND_CTXT_DATA_W1_IRQ_REQ_MASK BIT(29)
-#define SW_IND_CTXT_DATA_W1_ERR_WB_SENT_MASK BIT(28)
-#define SW_IND_CTXT_DATA_W1_ERR_MASK GENMASK(27, 26)
-#define SW_IND_CTXT_DATA_W1_IRQ_NO_LAST_MASK BIT(25)
-#define SW_IND_CTXT_DATA_W1_PORT_ID_MASK GENMASK(24, 22)
-#define SW_IND_CTXT_DATA_W1_IRQ_EN_MASK BIT(21)
-#define SW_IND_CTXT_DATA_W1_WBK_EN_MASK BIT(20)
-#define SW_IND_CTXT_DATA_W1_MM_CHN_MASK BIT(19)
-#define SW_IND_CTXT_DATA_W1_BYPASS_MASK BIT(18)
-#define SW_IND_CTXT_DATA_W1_DSC_SZ_MASK GENMASK(17, 16)
-#define SW_IND_CTXT_DATA_W1_RNG_SZ_MASK GENMASK(15, 12)
-#define SW_IND_CTXT_DATA_W1_FNC_ID_MASK GENMASK(11, 4)
-#define SW_IND_CTXT_DATA_W1_WBI_INTVL_EN_MASK BIT(3)
-#define SW_IND_CTXT_DATA_W1_WBI_CHK_MASK BIT(2)
-#define SW_IND_CTXT_DATA_W1_FCRD_EN_MASK BIT(1)
-#define SW_IND_CTXT_DATA_W1_QEN_MASK BIT(0)
-#define SW_IND_CTXT_DATA_W0_RSV_MASK GENMASK(31, 17)
-#define SW_IND_CTXT_DATA_W0_IRQ_ARM_MASK BIT(16)
-#define SW_IND_CTXT_DATA_W0_PIDX_MASK GENMASK(15, 0)
-#define HW_IND_CTXT_DATA_W1_RSVD_MASK GENMASK(15, 11)
-#define HW_IND_CTXT_DATA_W1_FETCH_PND_MASK BIT(10)
-#define HW_IND_CTXT_DATA_W1_IDL_STP_B_MASK BIT(9)
-#define HW_IND_CTXT_DATA_W1_DSC_PND_MASK BIT(8)
-#define HW_IND_CTXT_DATA_W1_RSVD_1_MASK GENMASK(7, 0)
-#define HW_IND_CTXT_DATA_W0_CRD_USE_MASK GENMASK(31, 16)
-#define HW_IND_CTXT_DATA_W0_CIDX_MASK GENMASK(15, 0)
-#define CRED_CTXT_DATA_W0_RSVD_1_MASK GENMASK(31, 16)
-#define CRED_CTXT_DATA_W0_CREDT_MASK GENMASK(15, 0)
-#define PREFETCH_CTXT_DATA_W1_VALID_MASK BIT(13)
-#define PREFETCH_CTXT_DATA_W1_SW_CRDT_H_MASK GENMASK(12, 0)
-#define PREFETCH_CTXT_DATA_W0_SW_CRDT_L_MASK GENMASK(31, 29)
-#define PREFETCH_CTXT_DATA_W0_PFCH_MASK BIT(28)
-#define PREFETCH_CTXT_DATA_W0_PFCH_EN_MASK BIT(27)
-#define PREFETCH_CTXT_DATA_W0_ERR_MASK BIT(26)
-#define PREFETCH_CTXT_DATA_W0_RSVD_MASK GENMASK(25, 8)
-#define PREFETCH_CTXT_DATA_W0_PORT_ID_MASK GENMASK(7, 5)
-#define PREFETCH_CTXT_DATA_W0_BUF_SIZE_IDX_MASK GENMASK(4, 1)
-#define PREFETCH_CTXT_DATA_W0_BYPASS_MASK BIT(0)
-#define CMPL_CTXT_DATA_W3_RSVD_MASK GENMASK(31, 30)
-#define CMPL_CTXT_DATA_W3_FULL_UPD_MASK BIT(29)
-#define CMPL_CTXT_DATA_W3_TIMER_RUNNING_MASK BIT(28)
-#define CMPL_CTXT_DATA_W3_USER_TRIG_PEND_MASK BIT(27)
-#define CMPL_CTXT_DATA_W3_ERR_MASK GENMASK(26, 25)
-#define CMPL_CTXT_DATA_W3_VALID_MASK BIT(24)
-#define CMPL_CTXT_DATA_W3_CIDX_MASK GENMASK(23, 8)
-#define CMPL_CTXT_DATA_W3_PIDX_H_MASK GENMASK(7, 0)
-#define CMPL_CTXT_DATA_W2_PIDX_L_MASK GENMASK(31, 24)
-#define CMPL_CTXT_DATA_W2_DESC_SIZE_MASK GENMASK(23, 22)
-#define CMPL_CTXT_DATA_W2_BADDR_64_H_MASK GENMASK(21, 0)
-#define CMPL_CTXT_DATA_W1_BADDR_64_M_MASK GENMASK(31, 0)
-#define CMPL_CTXT_DATA_W0_BADDR_64_L_MASK GENMASK(31, 28)
-#define CMPL_CTXT_DATA_W0_QSIZE_IDX_MASK GENMASK(27, 24)
-#define CMPL_CTXT_DATA_W0_COLOR_MASK BIT(23)
-#define CMPL_CTXT_DATA_W0_INT_ST_MASK GENMASK(22, 21)
-#define CMPL_CTXT_DATA_W0_TIMER_IDX_MASK GENMASK(20, 17)
-#define CMPL_CTXT_DATA_W0_CNTER_IDX_MASK GENMASK(16, 13)
-#define CMPL_CTXT_DATA_W0_FNC_ID_MASK GENMASK(12, 5)
-#define CMPL_CTXT_DATA_W0_TRIG_MODE_MASK GENMASK(4, 2)
-#define CMPL_CTXT_DATA_W0_EN_INT_MASK BIT(1)
-#define CMPL_CTXT_DATA_W0_EN_STAT_DESC_MASK BIT(0)
-#define INTR_CTXT_DATA_W2_PIDX_MASK GENMASK(11, 0)
-#define INTR_CTXT_DATA_W1_PAGE_SIZE_MASK GENMASK(31, 29)
-#define INTR_CTXT_DATA_W1_BADDR_4K_H_MASK GENMASK(28, 0)
-#define INTR_CTXT_DATA_W0_BADDR_4K_L_MASK GENMASK(31, 9)
-#define INTR_CTXT_DATA_W0_COLOR_MASK BIT(8)
-#define INTR_CTXT_DATA_W0_INT_ST_MASK BIT(7)
-#define INTR_CTXT_DATA_W0_RSVD_MASK BIT(6)
-#define INTR_CTXT_DATA_W0_VEC_MASK GENMASK(5, 1)
-#define INTR_CTXT_DATA_W0_VALID_MASK BIT(0)
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif
-
diff --git a/QDMA/DPDK/drivers/net/qdma/qdma_access/qdma_s80_hard_access/qdma_s80_hard_reg_dump.c b/QDMA/DPDK/drivers/net/qdma/qdma_access/qdma_s80_hard_access/qdma_s80_hard_reg_dump.c
deleted file mode 100644
index 2b6e684df7470d380da4afaa2badf06de6e7ca77..0000000000000000000000000000000000000000
--- a/QDMA/DPDK/drivers/net/qdma/qdma_access/qdma_s80_hard_access/qdma_s80_hard_reg_dump.c
+++ /dev/null
@@ -1,8028 +0,0 @@
-/*
- * Copyright(c) 2019-2020 Xilinx, Inc. All rights reserved.
- *
- * BSD LICENSE
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- *
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in
- * the documentation and/or other materials provided with the
- * distribution.
- * * Neither the name of the copyright holder nor the names of its
- * contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
- * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
- * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
- * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
- * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
- * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
- * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- */
-
-#include "qdma_s80_hard_reg.h"
-#include "qdma_reg_dump.h"
-
-#ifdef ENABLE_WPP_TRACING
-#include "qdma_s80_hard_reg_dump.tmh"
-#endif
-
-
-static struct regfield_info
- cfg_blk_identifier_field_info[] = {
- {"CFG_BLK_IDENTIFIER",
- CFG_BLK_IDENTIFIER_MASK},
- {"CFG_BLK_IDENTIFIER_1",
- CFG_BLK_IDENTIFIER_1_MASK},
- {"CFG_BLK_IDENTIFIER_RSVD_1",
- CFG_BLK_IDENTIFIER_RSVD_1_MASK},
- {"CFG_BLK_IDENTIFIER_VERSION",
- CFG_BLK_IDENTIFIER_VERSION_MASK},
-};
-
-
-static struct regfield_info
- cfg_blk_busdev_field_info[] = {
- {"CFG_BLK_BUSDEV_BDF",
- CFG_BLK_BUSDEV_BDF_MASK},
-};
-
-
-static struct regfield_info
- cfg_blk_pcie_max_pld_size_field_info[] = {
- {"CFG_BLK_PCIE_MAX_PLD_SIZE",
- CFG_BLK_PCIE_MAX_PLD_SIZE_MASK},
-};
-
-
-static struct regfield_info
- cfg_blk_pcie_max_read_req_size_field_info[] = {
- {"CFG_BLK_PCIE_MAX_READ_REQ_SIZE",
- CFG_BLK_PCIE_MAX_READ_REQ_SIZE_MASK},
-};
-
-
-static struct regfield_info
- cfg_blk_system_id_field_info[] = {
- {"CFG_BLK_SYSTEM_ID",
- CFG_BLK_SYSTEM_ID_MASK},
-};
-
-
-static struct regfield_info
- cfg_blk_msi_enable_field_info[] = {
- {"CFG_BLK_MSI_ENABLE_3",
- CFG_BLK_MSI_ENABLE_3_MASK},
- {"CFG_BLK_MSI_ENABLE_MSIX3",
- CFG_BLK_MSI_ENABLE_MSIX3_MASK},
- {"CFG_BLK_MSI_ENABLE_2",
- CFG_BLK_MSI_ENABLE_2_MASK},
- {"CFG_BLK_MSI_ENABLE_MSIX2",
- CFG_BLK_MSI_ENABLE_MSIX2_MASK},
- {"CFG_BLK_MSI_ENABLE_1",
- CFG_BLK_MSI_ENABLE_1_MASK},
- {"CFG_BLK_MSI_ENABLE_MSIX1",
- CFG_BLK_MSI_ENABLE_MSIX1_MASK},
- {"CFG_BLK_MSI_ENABLE_0",
- CFG_BLK_MSI_ENABLE_0_MASK},
- {"CFG_BLK_MSI_ENABLE_MSIX0",
- CFG_BLK_MSI_ENABLE_MSIX0_MASK},
-};
-
-
-static struct regfield_info
- cfg_pcie_data_width_field_info[] = {
- {"CFG_PCIE_DATA_WIDTH_DATAPATH",
- CFG_PCIE_DATA_WIDTH_DATAPATH_MASK},
-};
-
-
-static struct regfield_info
- cfg_pcie_ctl_field_info[] = {
- {"CFG_PCIE_CTL_RRQ_DISABLE",
- CFG_PCIE_CTL_RRQ_DISABLE_MASK},
- {"CFG_PCIE_CTL_RELAXED_ORDERING",
- CFG_PCIE_CTL_RELAXED_ORDERING_MASK},
-};
-
-
-static struct regfield_info
- cfg_axi_user_max_pld_size_field_info[] = {
- {"CFG_AXI_USER_MAX_PLD_SIZE_ISSUED",
- CFG_AXI_USER_MAX_PLD_SIZE_ISSUED_MASK},
- {"CFG_AXI_USER_MAX_PLD_SIZE_PROG",
- CFG_AXI_USER_MAX_PLD_SIZE_PROG_MASK},
-};
-
-
-static struct regfield_info
- cfg_axi_user_max_read_req_size_field_info[] = {
- {"CFG_AXI_USER_MAX_READ_REQ_SIZE_USISSUED",
- CFG_AXI_USER_MAX_READ_REQ_SIZE_USISSUED_MASK},
- {"CFG_AXI_USER_MAX_READ_REQ_SIZE_USPROG",
- CFG_AXI_USER_MAX_READ_REQ_SIZE_USPROG_MASK},
-};
-
-
-static struct regfield_info
- cfg_blk_misc_ctl_field_info[] = {
- {"CFG_BLK_MISC_CTL_NUM_TAG",
- CFG_BLK_MISC_CTL_NUM_TAG_MASK},
- {"CFG_BLK_MISC_CTL_RQ_METERING_MULTIPLIER",
- CFG_BLK_MISC_CTL_RQ_METERING_MULTIPLIER_MASK},
-};
-
-
-static struct regfield_info
- cfg_blk_scratch_0_field_info[] = {
- {"CFG_BLK_SCRATCH_0",
- CFG_BLK_SCRATCH_0_MASK},
-};
-
-
-static struct regfield_info
- cfg_blk_scratch_1_field_info[] = {
- {"CFG_BLK_SCRATCH_1",
- CFG_BLK_SCRATCH_1_MASK},
-};
-
-
-static struct regfield_info
- cfg_blk_scratch_2_field_info[] = {
- {"CFG_BLK_SCRATCH_2",
- CFG_BLK_SCRATCH_2_MASK},
-};
-
-
-static struct regfield_info
- cfg_blk_scratch_3_field_info[] = {
- {"CFG_BLK_SCRATCH_3",
- CFG_BLK_SCRATCH_3_MASK},
-};
-
-
-static struct regfield_info
- cfg_blk_scratch_4_field_info[] = {
- {"CFG_BLK_SCRATCH_4",
- CFG_BLK_SCRATCH_4_MASK},
-};
-
-
-static struct regfield_info
- cfg_blk_scratch_5_field_info[] = {
- {"CFG_BLK_SCRATCH_5",
- CFG_BLK_SCRATCH_5_MASK},
-};
-
-
-static struct regfield_info
- cfg_blk_scratch_6_field_info[] = {
- {"CFG_BLK_SCRATCH_6",
- CFG_BLK_SCRATCH_6_MASK},
-};
-
-
-static struct regfield_info
- cfg_blk_scratch_7_field_info[] = {
- {"CFG_BLK_SCRATCH_7",
- CFG_BLK_SCRATCH_7_MASK},
-};
-
-
-static struct regfield_info
- ram_sbe_msk_a_field_info[] = {
- {"RAM_SBE_MSK_A",
- RAM_SBE_MSK_A_MASK},
-};
-
-
-static struct regfield_info
- ram_sbe_sts_a_field_info[] = {
- {"RAM_SBE_STS_A_RSVD_1",
- RAM_SBE_STS_A_RSVD_1_MASK},
- {"RAM_SBE_STS_A_PFCH_LL_RAM",
- RAM_SBE_STS_A_PFCH_LL_RAM_MASK},
- {"RAM_SBE_STS_A_WRB_CTXT_RAM",
- RAM_SBE_STS_A_WRB_CTXT_RAM_MASK},
- {"RAM_SBE_STS_A_PFCH_CTXT_RAM",
- RAM_SBE_STS_A_PFCH_CTXT_RAM_MASK},
- {"RAM_SBE_STS_A_DESC_REQ_FIFO_RAM",
- RAM_SBE_STS_A_DESC_REQ_FIFO_RAM_MASK},
- {"RAM_SBE_STS_A_INT_CTXT_RAM",
- RAM_SBE_STS_A_INT_CTXT_RAM_MASK},
- {"RAM_SBE_STS_A_INT_QID2VEC_RAM",
- RAM_SBE_STS_A_INT_QID2VEC_RAM_MASK},
- {"RAM_SBE_STS_A_WRB_COAL_DATA_RAM",
- RAM_SBE_STS_A_WRB_COAL_DATA_RAM_MASK},
- {"RAM_SBE_STS_A_TUSER_FIFO_RAM",
- RAM_SBE_STS_A_TUSER_FIFO_RAM_MASK},
- {"RAM_SBE_STS_A_QID_FIFO_RAM",
- RAM_SBE_STS_A_QID_FIFO_RAM_MASK},
- {"RAM_SBE_STS_A_PLD_FIFO_RAM",
- RAM_SBE_STS_A_PLD_FIFO_RAM_MASK},
- {"RAM_SBE_STS_A_TIMER_FIFO_RAM",
- RAM_SBE_STS_A_TIMER_FIFO_RAM_MASK},
- {"RAM_SBE_STS_A_PASID_CTXT_RAM",
- RAM_SBE_STS_A_PASID_CTXT_RAM_MASK},
- {"RAM_SBE_STS_A_DSC_CPLD",
- RAM_SBE_STS_A_DSC_CPLD_MASK},
- {"RAM_SBE_STS_A_DSC_CPLI",
- RAM_SBE_STS_A_DSC_CPLI_MASK},
- {"RAM_SBE_STS_A_DSC_SW_CTXT",
- RAM_SBE_STS_A_DSC_SW_CTXT_MASK},
- {"RAM_SBE_STS_A_DSC_CRD_RCV",
- RAM_SBE_STS_A_DSC_CRD_RCV_MASK},
- {"RAM_SBE_STS_A_DSC_HW_CTXT",
- RAM_SBE_STS_A_DSC_HW_CTXT_MASK},
- {"RAM_SBE_STS_A_FUNC_MAP",
- RAM_SBE_STS_A_FUNC_MAP_MASK},
- {"RAM_SBE_STS_A_C2H_WR_BRG_DAT",
- RAM_SBE_STS_A_C2H_WR_BRG_DAT_MASK},
- {"RAM_SBE_STS_A_C2H_RD_BRG_DAT",
- RAM_SBE_STS_A_C2H_RD_BRG_DAT_MASK},
- {"RAM_SBE_STS_A_H2C_WR_BRG_DAT",
- RAM_SBE_STS_A_H2C_WR_BRG_DAT_MASK},
- {"RAM_SBE_STS_A_H2C_RD_BRG_DAT",
- RAM_SBE_STS_A_H2C_RD_BRG_DAT_MASK},
- {"RAM_SBE_STS_A_RSVD_2",
- RAM_SBE_STS_A_RSVD_2_MASK},
- {"RAM_SBE_STS_A_MI_C2H0_DAT",
- RAM_SBE_STS_A_MI_C2H0_DAT_MASK},
- {"RAM_SBE_STS_A_RSVD_3",
- RAM_SBE_STS_A_RSVD_3_MASK},
- {"RAM_SBE_STS_A_MI_H2C0_DAT",
- RAM_SBE_STS_A_MI_H2C0_DAT_MASK},
-};
-
-
-static struct regfield_info
- ram_dbe_msk_a_field_info[] = {
- {"RAM_DBE_MSK_A",
- RAM_DBE_MSK_A_MASK},
-};
-
-
-static struct regfield_info
- ram_dbe_sts_a_field_info[] = {
- {"RAM_DBE_STS_A_RSVD_1",
- RAM_DBE_STS_A_RSVD_1_MASK},
- {"RAM_DBE_STS_A_PFCH_LL_RAM",
- RAM_DBE_STS_A_PFCH_LL_RAM_MASK},
- {"RAM_DBE_STS_A_WRB_CTXT_RAM",
- RAM_DBE_STS_A_WRB_CTXT_RAM_MASK},
- {"RAM_DBE_STS_A_PFCH_CTXT_RAM",
- RAM_DBE_STS_A_PFCH_CTXT_RAM_MASK},
- {"RAM_DBE_STS_A_DESC_REQ_FIFO_RAM",
- RAM_DBE_STS_A_DESC_REQ_FIFO_RAM_MASK},
- {"RAM_DBE_STS_A_INT_CTXT_RAM",
- RAM_DBE_STS_A_INT_CTXT_RAM_MASK},
- {"RAM_DBE_STS_A_INT_QID2VEC_RAM",
- RAM_DBE_STS_A_INT_QID2VEC_RAM_MASK},
- {"RAM_DBE_STS_A_WRB_COAL_DATA_RAM",
- RAM_DBE_STS_A_WRB_COAL_DATA_RAM_MASK},
- {"RAM_DBE_STS_A_TUSER_FIFO_RAM",
- RAM_DBE_STS_A_TUSER_FIFO_RAM_MASK},
- {"RAM_DBE_STS_A_QID_FIFO_RAM",
- RAM_DBE_STS_A_QID_FIFO_RAM_MASK},
- {"RAM_DBE_STS_A_PLD_FIFO_RAM",
- RAM_DBE_STS_A_PLD_FIFO_RAM_MASK},
- {"RAM_DBE_STS_A_TIMER_FIFO_RAM",
- RAM_DBE_STS_A_TIMER_FIFO_RAM_MASK},
- {"RAM_DBE_STS_A_PASID_CTXT_RAM",
- RAM_DBE_STS_A_PASID_CTXT_RAM_MASK},
- {"RAM_DBE_STS_A_DSC_CPLD",
- RAM_DBE_STS_A_DSC_CPLD_MASK},
- {"RAM_DBE_STS_A_DSC_CPLI",
- RAM_DBE_STS_A_DSC_CPLI_MASK},
- {"RAM_DBE_STS_A_DSC_SW_CTXT",
- RAM_DBE_STS_A_DSC_SW_CTXT_MASK},
- {"RAM_DBE_STS_A_DSC_CRD_RCV",
- RAM_DBE_STS_A_DSC_CRD_RCV_MASK},
- {"RAM_DBE_STS_A_DSC_HW_CTXT",
- RAM_DBE_STS_A_DSC_HW_CTXT_MASK},
- {"RAM_DBE_STS_A_FUNC_MAP",
- RAM_DBE_STS_A_FUNC_MAP_MASK},
- {"RAM_DBE_STS_A_C2H_WR_BRG_DAT",
- RAM_DBE_STS_A_C2H_WR_BRG_DAT_MASK},
- {"RAM_DBE_STS_A_C2H_RD_BRG_DAT",
- RAM_DBE_STS_A_C2H_RD_BRG_DAT_MASK},
- {"RAM_DBE_STS_A_H2C_WR_BRG_DAT",
- RAM_DBE_STS_A_H2C_WR_BRG_DAT_MASK},
- {"RAM_DBE_STS_A_H2C_RD_BRG_DAT",
- RAM_DBE_STS_A_H2C_RD_BRG_DAT_MASK},
- {"RAM_DBE_STS_A_RSVD_2",
- RAM_DBE_STS_A_RSVD_2_MASK},
- {"RAM_DBE_STS_A_MI_C2H0_DAT",
- RAM_DBE_STS_A_MI_C2H0_DAT_MASK},
- {"RAM_DBE_STS_A_RSVD_3",
- RAM_DBE_STS_A_RSVD_3_MASK},
- {"RAM_DBE_STS_A_MI_H2C0_DAT",
- RAM_DBE_STS_A_MI_H2C0_DAT_MASK},
-};
-
-
-static struct regfield_info
- glbl2_identifier_field_info[] = {
- {"GLBL2_IDENTIFIER",
- GLBL2_IDENTIFIER_MASK},
- {"GLBL2_IDENTIFIER_VERSION",
- GLBL2_IDENTIFIER_VERSION_MASK},
-};
-
-
-static struct regfield_info
- glbl2_pf_barlite_int_field_info[] = {
- {"GLBL2_PF_BARLITE_INT_PF3_BAR_MAP",
- GLBL2_PF_BARLITE_INT_PF3_BAR_MAP_MASK},
- {"GLBL2_PF_BARLITE_INT_PF2_BAR_MAP",
- GLBL2_PF_BARLITE_INT_PF2_BAR_MAP_MASK},
- {"GLBL2_PF_BARLITE_INT_PF1_BAR_MAP",
- GLBL2_PF_BARLITE_INT_PF1_BAR_MAP_MASK},
- {"GLBL2_PF_BARLITE_INT_PF0_BAR_MAP",
- GLBL2_PF_BARLITE_INT_PF0_BAR_MAP_MASK},
-};
-
-
-static struct regfield_info
- glbl2_pf_vf_barlite_int_field_info[] = {
- {"GLBL2_PF_VF_BARLITE_INT_PF3_MAP",
- GLBL2_PF_VF_BARLITE_INT_PF3_MAP_MASK},
- {"GLBL2_PF_VF_BARLITE_INT_PF2_MAP",
- GLBL2_PF_VF_BARLITE_INT_PF2_MAP_MASK},
- {"GLBL2_PF_VF_BARLITE_INT_PF1_MAP",
- GLBL2_PF_VF_BARLITE_INT_PF1_MAP_MASK},
- {"GLBL2_PF_VF_BARLITE_INT_PF0_MAP",
- GLBL2_PF_VF_BARLITE_INT_PF0_MAP_MASK},
-};
-
-
-static struct regfield_info
- glbl2_pf_barlite_ext_field_info[] = {
- {"GLBL2_PF_BARLITE_EXT_PF3_BAR_MAP",
- GLBL2_PF_BARLITE_EXT_PF3_BAR_MAP_MASK},
- {"GLBL2_PF_BARLITE_EXT_PF2_BAR_MAP",
- GLBL2_PF_BARLITE_EXT_PF2_BAR_MAP_MASK},
- {"GLBL2_PF_BARLITE_EXT_PF1_BAR_MAP",
- GLBL2_PF_BARLITE_EXT_PF1_BAR_MAP_MASK},
- {"GLBL2_PF_BARLITE_EXT_PF0_BAR_MAP",
- GLBL2_PF_BARLITE_EXT_PF0_BAR_MAP_MASK},
-};
-
-
-static struct regfield_info
- glbl2_pf_vf_barlite_ext_field_info[] = {
- {"GLBL2_PF_VF_BARLITE_EXT_PF3_MAP",
- GLBL2_PF_VF_BARLITE_EXT_PF3_MAP_MASK},
- {"GLBL2_PF_VF_BARLITE_EXT_PF2_MAP",
- GLBL2_PF_VF_BARLITE_EXT_PF2_MAP_MASK},
- {"GLBL2_PF_VF_BARLITE_EXT_PF1_MAP",
- GLBL2_PF_VF_BARLITE_EXT_PF1_MAP_MASK},
- {"GLBL2_PF_VF_BARLITE_EXT_PF0_MAP",
- GLBL2_PF_VF_BARLITE_EXT_PF0_MAP_MASK},
-};
-
-
-static struct regfield_info
- glbl2_channel_inst_field_info[] = {
- {"GLBL2_CHANNEL_INST_RSVD_1",
- GLBL2_CHANNEL_INST_RSVD_1_MASK},
- {"GLBL2_CHANNEL_INST_C2H_ST",
- GLBL2_CHANNEL_INST_C2H_ST_MASK},
- {"GLBL2_CHANNEL_INST_H2C_ST",
- GLBL2_CHANNEL_INST_H2C_ST_MASK},
- {"GLBL2_CHANNEL_INST_RSVD_2",
- GLBL2_CHANNEL_INST_RSVD_2_MASK},
- {"GLBL2_CHANNEL_INST_C2H_ENG",
- GLBL2_CHANNEL_INST_C2H_ENG_MASK},
- {"GLBL2_CHANNEL_INST_RSVD_3",
- GLBL2_CHANNEL_INST_RSVD_3_MASK},
- {"GLBL2_CHANNEL_INST_H2C_ENG",
- GLBL2_CHANNEL_INST_H2C_ENG_MASK},
-};
-
-
-static struct regfield_info
- glbl2_channel_mdma_field_info[] = {
- {"GLBL2_CHANNEL_MDMA_RSVD_1",
- GLBL2_CHANNEL_MDMA_RSVD_1_MASK},
- {"GLBL2_CHANNEL_MDMA_C2H_ST",
- GLBL2_CHANNEL_MDMA_C2H_ST_MASK},
- {"GLBL2_CHANNEL_MDMA_H2C_ST",
- GLBL2_CHANNEL_MDMA_H2C_ST_MASK},
- {"GLBL2_CHANNEL_MDMA_RSVD_2",
- GLBL2_CHANNEL_MDMA_RSVD_2_MASK},
- {"GLBL2_CHANNEL_MDMA_C2H_ENG",
- GLBL2_CHANNEL_MDMA_C2H_ENG_MASK},
- {"GLBL2_CHANNEL_MDMA_RSVD_3",
- GLBL2_CHANNEL_MDMA_RSVD_3_MASK},
- {"GLBL2_CHANNEL_MDMA_H2C_ENG",
- GLBL2_CHANNEL_MDMA_H2C_ENG_MASK},
-};
-
-
-static struct regfield_info
- glbl2_channel_strm_field_info[] = {
- {"GLBL2_CHANNEL_STRM_RSVD_1",
- GLBL2_CHANNEL_STRM_RSVD_1_MASK},
- {"GLBL2_CHANNEL_STRM_C2H_ST",
- GLBL2_CHANNEL_STRM_C2H_ST_MASK},
- {"GLBL2_CHANNEL_STRM_H2C_ST",
- GLBL2_CHANNEL_STRM_H2C_ST_MASK},
- {"GLBL2_CHANNEL_STRM_RSVD_2",
- GLBL2_CHANNEL_STRM_RSVD_2_MASK},
- {"GLBL2_CHANNEL_STRM_C2H_ENG",
- GLBL2_CHANNEL_STRM_C2H_ENG_MASK},
- {"GLBL2_CHANNEL_STRM_RSVD_3",
- GLBL2_CHANNEL_STRM_RSVD_3_MASK},
- {"GLBL2_CHANNEL_STRM_H2C_ENG",
- GLBL2_CHANNEL_STRM_H2C_ENG_MASK},
-};
-
-
-static struct regfield_info
- glbl2_channel_cap_field_info[] = {
- {"GLBL2_CHANNEL_CAP_RSVD_1",
- GLBL2_CHANNEL_CAP_RSVD_1_MASK},
- {"GLBL2_CHANNEL_CAP_MULTIQ_MAX",
- GLBL2_CHANNEL_CAP_MULTIQ_MAX_MASK},
-};
-
-
-static struct regfield_info
- glbl2_channel_pasid_cap_field_info[] = {
- {"GLBL2_CHANNEL_PASID_CAP_RSVD_1",
- GLBL2_CHANNEL_PASID_CAP_RSVD_1_MASK},
- {"GLBL2_CHANNEL_PASID_CAP_BRIDGEOFFSET",
- GLBL2_CHANNEL_PASID_CAP_BRIDGEOFFSET_MASK},
- {"GLBL2_CHANNEL_PASID_CAP_RSVD_2",
- GLBL2_CHANNEL_PASID_CAP_RSVD_2_MASK},
- {"GLBL2_CHANNEL_PASID_CAP_BRIDGEEN",
- GLBL2_CHANNEL_PASID_CAP_BRIDGEEN_MASK},
- {"GLBL2_CHANNEL_PASID_CAP_DMAEN",
- GLBL2_CHANNEL_PASID_CAP_DMAEN_MASK},
-};
-
-
-static struct regfield_info
- glbl2_channel_func_ret_field_info[] = {
- {"GLBL2_CHANNEL_FUNC_RET_RSVD_1",
- GLBL2_CHANNEL_FUNC_RET_RSVD_1_MASK},
- {"GLBL2_CHANNEL_FUNC_RET_FUNC",
- GLBL2_CHANNEL_FUNC_RET_FUNC_MASK},
-};
-
-
-static struct regfield_info
- glbl2_system_id_field_info[] = {
- {"GLBL2_SYSTEM_ID_RSVD_1",
- GLBL2_SYSTEM_ID_RSVD_1_MASK},
- {"GLBL2_SYSTEM_ID",
- GLBL2_SYSTEM_ID_MASK},
-};
-
-
-static struct regfield_info
- glbl2_misc_cap_field_info[] = {
- {"GLBL2_MISC_CAP_RSVD_1",
- GLBL2_MISC_CAP_RSVD_1_MASK},
-};
-
-
-static struct regfield_info
- glbl2_dbg_pcie_rq0_field_info[] = {
- {"GLBL2_PCIE_RQ0_NPH_AVL",
- GLBL2_PCIE_RQ0_NPH_AVL_MASK},
- {"GLBL2_PCIE_RQ0_RCB_AVL",
- GLBL2_PCIE_RQ0_RCB_AVL_MASK},
- {"GLBL2_PCIE_RQ0_SLV_RD_CREDS",
- GLBL2_PCIE_RQ0_SLV_RD_CREDS_MASK},
- {"GLBL2_PCIE_RQ0_TAG_EP",
- GLBL2_PCIE_RQ0_TAG_EP_MASK},
- {"GLBL2_PCIE_RQ0_TAG_FL",
- GLBL2_PCIE_RQ0_TAG_FL_MASK},
-};
-
-
-static struct regfield_info
- glbl2_dbg_pcie_rq1_field_info[] = {
- {"GLBL2_PCIE_RQ1_RSVD_1",
- GLBL2_PCIE_RQ1_RSVD_1_MASK},
- {"GLBL2_PCIE_RQ1_WTLP_REQ",
- GLBL2_PCIE_RQ1_WTLP_REQ_MASK},
- {"GLBL2_PCIE_RQ1_WTLP_HEADER_FIFO_FL",
- GLBL2_PCIE_RQ1_WTLP_HEADER_FIFO_FL_MASK},
- {"GLBL2_PCIE_RQ1_WTLP_HEADER_FIFO_EP",
- GLBL2_PCIE_RQ1_WTLP_HEADER_FIFO_EP_MASK},
- {"GLBL2_PCIE_RQ1_RQ_FIFO_EP",
- GLBL2_PCIE_RQ1_RQ_FIFO_EP_MASK},
- {"GLBL2_PCIE_RQ1_RQ_FIFO_FL",
- GLBL2_PCIE_RQ1_RQ_FIFO_FL_MASK},
- {"GLBL2_PCIE_RQ1_TLPSM",
- GLBL2_PCIE_RQ1_TLPSM_MASK},
- {"GLBL2_PCIE_RQ1_TLPSM512",
- GLBL2_PCIE_RQ1_TLPSM512_MASK},
- {"GLBL2_PCIE_RQ1_RREQ0_RCB_OK",
- GLBL2_PCIE_RQ1_RREQ0_RCB_OK_MASK},
- {"GLBL2_PCIE_RQ1_RREQ0_SLV",
- GLBL2_PCIE_RQ1_RREQ0_SLV_MASK},
- {"GLBL2_PCIE_RQ1_RREQ0_VLD",
- GLBL2_PCIE_RQ1_RREQ0_VLD_MASK},
- {"GLBL2_PCIE_RQ1_RREQ1_RCB_OK",
- GLBL2_PCIE_RQ1_RREQ1_RCB_OK_MASK},
- {"GLBL2_PCIE_RQ1_RREQ1_SLV",
- GLBL2_PCIE_RQ1_RREQ1_SLV_MASK},
- {"GLBL2_PCIE_RQ1_RREQ1_VLD",
- GLBL2_PCIE_RQ1_RREQ1_VLD_MASK},
-};
-
-
-static struct regfield_info
- glbl2_dbg_aximm_wr0_field_info[] = {
- {"GLBL2_AXIMM_WR0_RSVD_1",
- GLBL2_AXIMM_WR0_RSVD_1_MASK},
- {"GLBL2_AXIMM_WR0_WR_REQ",
- GLBL2_AXIMM_WR0_WR_REQ_MASK},
- {"GLBL2_AXIMM_WR0_WR_CHN",
- GLBL2_AXIMM_WR0_WR_CHN_MASK},
- {"GLBL2_AXIMM_WR0_WTLP_DATA_FIFO_EP",
- GLBL2_AXIMM_WR0_WTLP_DATA_FIFO_EP_MASK},
- {"GLBL2_AXIMM_WR0_WPL_FIFO_EP",
- GLBL2_AXIMM_WR0_WPL_FIFO_EP_MASK},
- {"GLBL2_AXIMM_WR0_BRSP_CLAIM_CHN",
- GLBL2_AXIMM_WR0_BRSP_CLAIM_CHN_MASK},
- {"GLBL2_AXIMM_WR0_WRREQ_CNT",
- GLBL2_AXIMM_WR0_WRREQ_CNT_MASK},
- {"GLBL2_AXIMM_WR0_BID",
- GLBL2_AXIMM_WR0_BID_MASK},
- {"GLBL2_AXIMM_WR0_BVALID",
- GLBL2_AXIMM_WR0_BVALID_MASK},
- {"GLBL2_AXIMM_WR0_BREADY",
- GLBL2_AXIMM_WR0_BREADY_MASK},
- {"GLBL2_AXIMM_WR0_WVALID",
- GLBL2_AXIMM_WR0_WVALID_MASK},
- {"GLBL2_AXIMM_WR0_WREADY",
- GLBL2_AXIMM_WR0_WREADY_MASK},
- {"GLBL2_AXIMM_WR0_AWID",
- GLBL2_AXIMM_WR0_AWID_MASK},
- {"GLBL2_AXIMM_WR0_AWVALID",
- GLBL2_AXIMM_WR0_AWVALID_MASK},
- {"GLBL2_AXIMM_WR0_AWREADY",
- GLBL2_AXIMM_WR0_AWREADY_MASK},
-};
-
-
-static struct regfield_info
- glbl2_dbg_aximm_wr1_field_info[] = {
- {"GLBL2_AXIMM_WR1_RSVD_1",
- GLBL2_AXIMM_WR1_RSVD_1_MASK},
- {"GLBL2_AXIMM_WR1_BRSP_CNT4",
- GLBL2_AXIMM_WR1_BRSP_CNT4_MASK},
- {"GLBL2_AXIMM_WR1_BRSP_CNT3",
- GLBL2_AXIMM_WR1_BRSP_CNT3_MASK},
- {"GLBL2_AXIMM_WR1_BRSP_CNT2",
- GLBL2_AXIMM_WR1_BRSP_CNT2_MASK},
- {"GLBL2_AXIMM_WR1_BRSP_CNT1",
- GLBL2_AXIMM_WR1_BRSP_CNT1_MASK},
- {"GLBL2_AXIMM_WR1_BRSP_CNT0",
- GLBL2_AXIMM_WR1_BRSP_CNT0_MASK},
-};
-
-
-static struct regfield_info
- glbl2_dbg_aximm_rd0_field_info[] = {
- {"GLBL2_AXIMM_RD0_RSVD_1",
- GLBL2_AXIMM_RD0_RSVD_1_MASK},
- {"GLBL2_AXIMM_RD0_PND_CNT",
- GLBL2_AXIMM_RD0_PND_CNT_MASK},
- {"GLBL2_AXIMM_RD0_RD_CHNL",
- GLBL2_AXIMM_RD0_RD_CHNL_MASK},
- {"GLBL2_AXIMM_RD0_RD_REQ",
- GLBL2_AXIMM_RD0_RD_REQ_MASK},
- {"GLBL2_AXIMM_RD0_RRSP_CLAIM_CHNL",
- GLBL2_AXIMM_RD0_RRSP_CLAIM_CHNL_MASK},
- {"GLBL2_AXIMM_RD0_RID",
- GLBL2_AXIMM_RD0_RID_MASK},
- {"GLBL2_AXIMM_RD0_RVALID",
- GLBL2_AXIMM_RD0_RVALID_MASK},
- {"GLBL2_AXIMM_RD0_RREADY",
- GLBL2_AXIMM_RD0_RREADY_MASK},
- {"GLBL2_AXIMM_RD0_ARID",
- GLBL2_AXIMM_RD0_ARID_MASK},
- {"GLBL2_AXIMM_RD0_ARVALID",
- GLBL2_AXIMM_RD0_ARVALID_MASK},
- {"GLBL2_AXIMM_RD0_ARREADY",
- GLBL2_AXIMM_RD0_ARREADY_MASK},
-};
-
-
-static struct regfield_info
- glbl2_dbg_aximm_rd1_field_info[] = {
- {"GLBL2_AXIMM_RD1_RSVD_1",
- GLBL2_AXIMM_RD1_RSVD_1_MASK},
- {"GLBL2_AXIMM_RD1_RRSP_CNT4",
- GLBL2_AXIMM_RD1_RRSP_CNT4_MASK},
- {"GLBL2_AXIMM_RD1_RRSP_CNT3",
- GLBL2_AXIMM_RD1_RRSP_CNT3_MASK},
- {"GLBL2_AXIMM_RD1_RRSP_CNT2",
- GLBL2_AXIMM_RD1_RRSP_CNT2_MASK},
- {"GLBL2_AXIMM_RD1_RRSP_CNT1",
- GLBL2_AXIMM_RD1_RRSP_CNT1_MASK},
- {"GLBL2_AXIMM_RD1_RRSP_CNT0",
- GLBL2_AXIMM_RD1_RRSP_CNT0_MASK},
-};
-
-
-static struct regfield_info
- glbl_rng_sz_1_field_info[] = {
- {"GLBL_RNG_SZ_1_RSVD_1",
- GLBL_RNG_SZ_1_RSVD_1_MASK},
- {"GLBL_RNG_SZ_1_RING_SIZE",
- GLBL_RNG_SZ_1_RING_SIZE_MASK},
-};
-
-
-static struct regfield_info
- glbl_rng_sz_2_field_info[] = {
- {"GLBL_RNG_SZ_2_RSVD_1",
- GLBL_RNG_SZ_2_RSVD_1_MASK},
- {"GLBL_RNG_SZ_2_RING_SIZE",
- GLBL_RNG_SZ_2_RING_SIZE_MASK},
-};
-
-
-static struct regfield_info
- glbl_rng_sz_3_field_info[] = {
- {"GLBL_RNG_SZ_3_RSVD_1",
- GLBL_RNG_SZ_3_RSVD_1_MASK},
- {"GLBL_RNG_SZ_3_RING_SIZE",
- GLBL_RNG_SZ_3_RING_SIZE_MASK},
-};
-
-
-static struct regfield_info
- glbl_rng_sz_4_field_info[] = {
- {"GLBL_RNG_SZ_4_RSVD_1",
- GLBL_RNG_SZ_4_RSVD_1_MASK},
- {"GLBL_RNG_SZ_4_RING_SIZE",
- GLBL_RNG_SZ_4_RING_SIZE_MASK},
-};
-
-
-static struct regfield_info
- glbl_rng_sz_5_field_info[] = {
- {"GLBL_RNG_SZ_5_RSVD_1",
- GLBL_RNG_SZ_5_RSVD_1_MASK},
- {"GLBL_RNG_SZ_5_RING_SIZE",
- GLBL_RNG_SZ_5_RING_SIZE_MASK},
-};
-
-
-static struct regfield_info
- glbl_rng_sz_6_field_info[] = {
- {"GLBL_RNG_SZ_6_RSVD_1",
- GLBL_RNG_SZ_6_RSVD_1_MASK},
- {"GLBL_RNG_SZ_6_RING_SIZE",
- GLBL_RNG_SZ_6_RING_SIZE_MASK},
-};
-
-
-static struct regfield_info
- glbl_rng_sz_7_field_info[] = {
- {"GLBL_RNG_SZ_7_RSVD_1",
- GLBL_RNG_SZ_7_RSVD_1_MASK},
- {"GLBL_RNG_SZ_7_RING_SIZE",
- GLBL_RNG_SZ_7_RING_SIZE_MASK},
-};
-
-
-static struct regfield_info
- glbl_rng_sz_8_field_info[] = {
- {"GLBL_RNG_SZ_8_RSVD_1",
- GLBL_RNG_SZ_8_RSVD_1_MASK},
- {"GLBL_RNG_SZ_8_RING_SIZE",
- GLBL_RNG_SZ_8_RING_SIZE_MASK},
-};
-
-
-static struct regfield_info
- glbl_rng_sz_9_field_info[] = {
- {"GLBL_RNG_SZ_9_RSVD_1",
- GLBL_RNG_SZ_9_RSVD_1_MASK},
- {"GLBL_RNG_SZ_9_RING_SIZE",
- GLBL_RNG_SZ_9_RING_SIZE_MASK},
-};
-
-
-static struct regfield_info
- glbl_rng_sz_a_field_info[] = {
- {"GLBL_RNG_SZ_A_RSVD_1",
- GLBL_RNG_SZ_A_RSVD_1_MASK},
- {"GLBL_RNG_SZ_A_RING_SIZE",
- GLBL_RNG_SZ_A_RING_SIZE_MASK},
-};
-
-
-static struct regfield_info
- glbl_rng_sz_b_field_info[] = {
- {"GLBL_RNG_SZ_B_RSVD_1",
- GLBL_RNG_SZ_B_RSVD_1_MASK},
- {"GLBL_RNG_SZ_B_RING_SIZE",
- GLBL_RNG_SZ_B_RING_SIZE_MASK},
-};
-
-
-static struct regfield_info
- glbl_rng_sz_c_field_info[] = {
- {"GLBL_RNG_SZ_C_RSVD_1",
- GLBL_RNG_SZ_C_RSVD_1_MASK},
- {"GLBL_RNG_SZ_C_RING_SIZE",
- GLBL_RNG_SZ_C_RING_SIZE_MASK},
-};
-
-
-static struct regfield_info
- glbl_rng_sz_d_field_info[] = {
- {"GLBL_RNG_SZ_D_RSVD_1",
- GLBL_RNG_SZ_D_RSVD_1_MASK},
- {"GLBL_RNG_SZ_D_RING_SIZE",
- GLBL_RNG_SZ_D_RING_SIZE_MASK},
-};
-
-
-static struct regfield_info
- glbl_rng_sz_e_field_info[] = {
- {"GLBL_RNG_SZ_E_RSVD_1",
- GLBL_RNG_SZ_E_RSVD_1_MASK},
- {"GLBL_RNG_SZ_E_RING_SIZE",
- GLBL_RNG_SZ_E_RING_SIZE_MASK},
-};
-
-
-static struct regfield_info
- glbl_rng_sz_f_field_info[] = {
- {"GLBL_RNG_SZ_F_RSVD_1",
- GLBL_RNG_SZ_F_RSVD_1_MASK},
- {"GLBL_RNG_SZ_F_RING_SIZE",
- GLBL_RNG_SZ_F_RING_SIZE_MASK},
-};
-
-
-static struct regfield_info
- glbl_rng_sz_10_field_info[] = {
- {"GLBL_RNG_SZ_10_RSVD_1",
- GLBL_RNG_SZ_10_RSVD_1_MASK},
- {"GLBL_RNG_SZ_10_RING_SIZE",
- GLBL_RNG_SZ_10_RING_SIZE_MASK},
-};
-
-
-static struct regfield_info
- glbl_err_stat_field_info[] = {
- {"GLBL_ERR_STAT_RSVD_1",
- GLBL_ERR_STAT_RSVD_1_MASK},
- {"GLBL_ERR_STAT_ERR_H2C_ST",
- GLBL_ERR_STAT_ERR_H2C_ST_MASK},
- {"GLBL_ERR_STAT_ERR_BDG",
- GLBL_ERR_STAT_ERR_BDG_MASK},
- {"GLBL_ERR_STAT_IND_CTXT_CMD_ERR",
- GLBL_ERR_STAT_IND_CTXT_CMD_ERR_MASK},
- {"GLBL_ERR_STAT_ERR_C2H_ST",
- GLBL_ERR_STAT_ERR_C2H_ST_MASK},
- {"GLBL_ERR_STAT_ERR_C2H_MM_1",
- GLBL_ERR_STAT_ERR_C2H_MM_1_MASK},
- {"GLBL_ERR_STAT_ERR_C2H_MM_0",
- GLBL_ERR_STAT_ERR_C2H_MM_0_MASK},
- {"GLBL_ERR_STAT_ERR_H2C_MM_1",
- GLBL_ERR_STAT_ERR_H2C_MM_1_MASK},
- {"GLBL_ERR_STAT_ERR_H2C_MM_0",
- GLBL_ERR_STAT_ERR_H2C_MM_0_MASK},
- {"GLBL_ERR_STAT_ERR_TRQ",
- GLBL_ERR_STAT_ERR_TRQ_MASK},
- {"GLBL_ERR_STAT_ERR_DSC",
- GLBL_ERR_STAT_ERR_DSC_MASK},
- {"GLBL_ERR_STAT_ERR_RAM_DBE",
- GLBL_ERR_STAT_ERR_RAM_DBE_MASK},
- {"GLBL_ERR_STAT_ERR_RAM_SBE",
- GLBL_ERR_STAT_ERR_RAM_SBE_MASK},
-};
-
-
-static struct regfield_info
- glbl_err_mask_field_info[] = {
- {"GLBL_ERR_RSVD_1",
- GLBL_ERR_RSVD_1_MASK},
- {"GLBL_ERR",
- GLBL_ERR_MASK},
-};
-
-
-static struct regfield_info
- glbl_dsc_cfg_field_info[] = {
- {"GLBL_DSC_CFG_RSVD_1",
- GLBL_DSC_CFG_RSVD_1_MASK},
- {"GLBL_DSC_CFG_UNC_OVR_COR",
- GLBL_DSC_CFG_UNC_OVR_COR_MASK},
- {"GLBL_DSC_CFG_CTXT_FER_DIS",
- GLBL_DSC_CFG_CTXT_FER_DIS_MASK},
- {"GLBL_DSC_CFG_RSVD_2",
- GLBL_DSC_CFG_RSVD_2_MASK},
- {"GLBL_DSC_CFG_MAXFETCH",
- GLBL_DSC_CFG_MAXFETCH_MASK},
- {"GLBL_DSC_CFG_WB_ACC_INT",
- GLBL_DSC_CFG_WB_ACC_INT_MASK},
-};
-
-
-static struct regfield_info
- glbl_dsc_err_sts_field_info[] = {
- {"GLBL_DSC_ERR_STS_RSVD_1",
- GLBL_DSC_ERR_STS_RSVD_1_MASK},
- {"GLBL_DSC_ERR_STS_SBE",
- GLBL_DSC_ERR_STS_SBE_MASK},
- {"GLBL_DSC_ERR_STS_DBE",
- GLBL_DSC_ERR_STS_DBE_MASK},
- {"GLBL_DSC_ERR_STS_RQ_CANCEL",
- GLBL_DSC_ERR_STS_RQ_CANCEL_MASK},
- {"GLBL_DSC_ERR_STS_DSC",
- GLBL_DSC_ERR_STS_DSC_MASK},
- {"GLBL_DSC_ERR_STS_DMA",
- GLBL_DSC_ERR_STS_DMA_MASK},
- {"GLBL_DSC_ERR_STS_FLR_CANCEL",
- GLBL_DSC_ERR_STS_FLR_CANCEL_MASK},
- {"GLBL_DSC_ERR_STS_RSVD_2",
- GLBL_DSC_ERR_STS_RSVD_2_MASK},
- {"GLBL_DSC_ERR_STS_DAT_POISON",
- GLBL_DSC_ERR_STS_DAT_POISON_MASK},
- {"GLBL_DSC_ERR_STS_TIMEOUT",
- GLBL_DSC_ERR_STS_TIMEOUT_MASK},
- {"GLBL_DSC_ERR_STS_FLR",
- GLBL_DSC_ERR_STS_FLR_MASK},
- {"GLBL_DSC_ERR_STS_TAG",
- GLBL_DSC_ERR_STS_TAG_MASK},
- {"GLBL_DSC_ERR_STS_ADDR",
- GLBL_DSC_ERR_STS_ADDR_MASK},
- {"GLBL_DSC_ERR_STS_PARAM",
- GLBL_DSC_ERR_STS_PARAM_MASK},
- {"GLBL_DSC_ERR_STS_UR_CA",
- GLBL_DSC_ERR_STS_UR_CA_MASK},
- {"GLBL_DSC_ERR_STS_POISON",
- GLBL_DSC_ERR_STS_POISON_MASK},
-};
-
-
-static struct regfield_info
- glbl_dsc_err_msk_field_info[] = {
- {"GLBL_DSC_ERR_MSK",
- GLBL_DSC_ERR_MSK_MASK},
-};
-
-
-static struct regfield_info
- glbl_dsc_err_log0_field_info[] = {
- {"GLBL_DSC_ERR_LOG0_VALID",
- GLBL_DSC_ERR_LOG0_VALID_MASK},
- {"GLBL_DSC_ERR_LOG0_RSVD_1",
- GLBL_DSC_ERR_LOG0_RSVD_1_MASK},
- {"GLBL_DSC_ERR_LOG0_QID",
- GLBL_DSC_ERR_LOG0_QID_MASK},
- {"GLBL_DSC_ERR_LOG0_SEL",
- GLBL_DSC_ERR_LOG0_SEL_MASK},
- {"GLBL_DSC_ERR_LOG0_CIDX",
- GLBL_DSC_ERR_LOG0_CIDX_MASK},
-};
-
-
-static struct regfield_info
- glbl_dsc_err_log1_field_info[] = {
- {"GLBL_DSC_ERR_LOG1_RSVD_1",
- GLBL_DSC_ERR_LOG1_RSVD_1_MASK},
- {"GLBL_DSC_ERR_LOG1_SUB_TYPE",
- GLBL_DSC_ERR_LOG1_SUB_TYPE_MASK},
- {"GLBL_DSC_ERR_LOG1_ERR_TYPE",
- GLBL_DSC_ERR_LOG1_ERR_TYPE_MASK},
-};
-
-
-static struct regfield_info
- glbl_trq_err_sts_field_info[] = {
- {"GLBL_TRQ_ERR_STS_RSVD_1",
- GLBL_TRQ_ERR_STS_RSVD_1_MASK},
- {"GLBL_TRQ_ERR_STS_TCP_TIMEOUT",
- GLBL_TRQ_ERR_STS_TCP_TIMEOUT_MASK},
- {"GLBL_TRQ_ERR_STS_VF_ACCESS_ERR",
- GLBL_TRQ_ERR_STS_VF_ACCESS_ERR_MASK},
- {"GLBL_TRQ_ERR_STS_QID_RANGE",
- GLBL_TRQ_ERR_STS_QID_RANGE_MASK},
- {"GLBL_TRQ_ERR_STS_UNMAPPED",
- GLBL_TRQ_ERR_STS_UNMAPPED_MASK},
-};
-
-
-static struct regfield_info
- glbl_trq_err_msk_field_info[] = {
- {"GLBL_TRQ_ERR_MSK",
- GLBL_TRQ_ERR_MSK_MASK},
-};
-
-
-static struct regfield_info
- glbl_trq_err_log_field_info[] = {
- {"GLBL_TRQ_ERR_LOG_RSVD_1",
- GLBL_TRQ_ERR_LOG_RSVD_1_MASK},
- {"GLBL_TRQ_ERR_LOG_TARGET",
- GLBL_TRQ_ERR_LOG_TARGET_MASK},
- {"GLBL_TRQ_ERR_LOG_FUNC",
- GLBL_TRQ_ERR_LOG_FUNC_MASK},
- {"GLBL_TRQ_ERR_LOG_ADDRESS",
- GLBL_TRQ_ERR_LOG_ADDRESS_MASK},
-};
-
-
-static struct regfield_info
- glbl_dsc_dbg_dat0_field_info[] = {
- {"GLBL_DSC_DAT0_RSVD_1",
- GLBL_DSC_DAT0_RSVD_1_MASK},
- {"GLBL_DSC_DAT0_CTXT_ARB_DIR",
- GLBL_DSC_DAT0_CTXT_ARB_DIR_MASK},
- {"GLBL_DSC_DAT0_CTXT_ARB_QID",
- GLBL_DSC_DAT0_CTXT_ARB_QID_MASK},
- {"GLBL_DSC_DAT0_CTXT_ARB_REQ",
- GLBL_DSC_DAT0_CTXT_ARB_REQ_MASK},
- {"GLBL_DSC_DAT0_IRQ_FIFO_FL",
- GLBL_DSC_DAT0_IRQ_FIFO_FL_MASK},
- {"GLBL_DSC_DAT0_TMSTALL",
- GLBL_DSC_DAT0_TMSTALL_MASK},
- {"GLBL_DSC_DAT0_RRQ_STALL",
- GLBL_DSC_DAT0_RRQ_STALL_MASK},
- {"GLBL_DSC_DAT0_RCP_FIFO_SPC_STALL",
- GLBL_DSC_DAT0_RCP_FIFO_SPC_STALL_MASK},
- {"GLBL_DSC_DAT0_RRQ_FIFO_SPC_STALL",
- GLBL_DSC_DAT0_RRQ_FIFO_SPC_STALL_MASK},
- {"GLBL_DSC_DAT0_FAB_MRKR_RSP_STALL",
- GLBL_DSC_DAT0_FAB_MRKR_RSP_STALL_MASK},
- {"GLBL_DSC_DAT0_DSC_OUT_STALL",
- GLBL_DSC_DAT0_DSC_OUT_STALL_MASK},
-};
-
-
-static struct regfield_info
- glbl_dsc_dbg_dat1_field_info[] = {
- {"GLBL_DSC_DAT1_RSVD_1",
- GLBL_DSC_DAT1_RSVD_1_MASK},
- {"GLBL_DSC_DAT1_EVT_SPC_C2H",
- GLBL_DSC_DAT1_EVT_SPC_C2H_MASK},
- {"GLBL_DSC_DAT1_EVT_SP_H2C",
- GLBL_DSC_DAT1_EVT_SP_H2C_MASK},
- {"GLBL_DSC_DAT1_DSC_SPC_C2H",
- GLBL_DSC_DAT1_DSC_SPC_C2H_MASK},
- {"GLBL_DSC_DAT1_DSC_SPC_H2C",
- GLBL_DSC_DAT1_DSC_SPC_H2C_MASK},
-};
-
-
-static struct regfield_info
- trq_sel_fmap_0_field_info[] = {
- {"TRQ_SEL_FMAP_0_RSVD_1",
- TRQ_SEL_FMAP_0_RSVD_1_MASK},
- {"TRQ_SEL_FMAP_0_QID_MAX",
- TRQ_SEL_FMAP_0_QID_MAX_MASK},
- {"TRQ_SEL_FMAP_0_QID_BASE",
- TRQ_SEL_FMAP_0_QID_BASE_MASK},
-};
-
-
-static struct regfield_info
- trq_sel_fmap_1_field_info[] = {
- {"TRQ_SEL_FMAP_1_RSVD_1",
- TRQ_SEL_FMAP_1_RSVD_1_MASK},
- {"TRQ_SEL_FMAP_1_QID_MAX",
- TRQ_SEL_FMAP_1_QID_MAX_MASK},
- {"TRQ_SEL_FMAP_1_QID_BASE",
- TRQ_SEL_FMAP_1_QID_BASE_MASK},
-};
-
-
-static struct regfield_info
- trq_sel_fmap_2_field_info[] = {
- {"TRQ_SEL_FMAP_2_RSVD_1",
- TRQ_SEL_FMAP_2_RSVD_1_MASK},
- {"TRQ_SEL_FMAP_2_QID_MAX",
- TRQ_SEL_FMAP_2_QID_MAX_MASK},
- {"TRQ_SEL_FMAP_2_QID_BASE",
- TRQ_SEL_FMAP_2_QID_BASE_MASK},
-};
-
-
-static struct regfield_info
- trq_sel_fmap_3_field_info[] = {
- {"TRQ_SEL_FMAP_3_RSVD_1",
- TRQ_SEL_FMAP_3_RSVD_1_MASK},
- {"TRQ_SEL_FMAP_3_QID_MAX",
- TRQ_SEL_FMAP_3_QID_MAX_MASK},
- {"TRQ_SEL_FMAP_3_QID_BASE",
- TRQ_SEL_FMAP_3_QID_BASE_MASK},
-};
-
-
-static struct regfield_info
- trq_sel_fmap_4_field_info[] = {
- {"TRQ_SEL_FMAP_4_RSVD_1",
- TRQ_SEL_FMAP_4_RSVD_1_MASK},
- {"TRQ_SEL_FMAP_4_QID_MAX",
- TRQ_SEL_FMAP_4_QID_MAX_MASK},
- {"TRQ_SEL_FMAP_4_QID_BASE",
- TRQ_SEL_FMAP_4_QID_BASE_MASK},
-};
-
-
-static struct regfield_info
- trq_sel_fmap_5_field_info[] = {
- {"TRQ_SEL_FMAP_5_RSVD_1",
- TRQ_SEL_FMAP_5_RSVD_1_MASK},
- {"TRQ_SEL_FMAP_5_QID_MAX",
- TRQ_SEL_FMAP_5_QID_MAX_MASK},
- {"TRQ_SEL_FMAP_5_QID_BASE",
- TRQ_SEL_FMAP_5_QID_BASE_MASK},
-};
-
-
-static struct regfield_info
- trq_sel_fmap_6_field_info[] = {
- {"TRQ_SEL_FMAP_6_RSVD_1",
- TRQ_SEL_FMAP_6_RSVD_1_MASK},
- {"TRQ_SEL_FMAP_6_QID_MAX",
- TRQ_SEL_FMAP_6_QID_MAX_MASK},
- {"TRQ_SEL_FMAP_6_QID_BASE",
- TRQ_SEL_FMAP_6_QID_BASE_MASK},
-};
-
-
-static struct regfield_info
- trq_sel_fmap_7_field_info[] = {
- {"TRQ_SEL_FMAP_7_RSVD_1",
- TRQ_SEL_FMAP_7_RSVD_1_MASK},
- {"TRQ_SEL_FMAP_7_QID_MAX",
- TRQ_SEL_FMAP_7_QID_MAX_MASK},
- {"TRQ_SEL_FMAP_7_QID_BASE",
- TRQ_SEL_FMAP_7_QID_BASE_MASK},
-};
-
-
-static struct regfield_info
- trq_sel_fmap_8_field_info[] = {
- {"TRQ_SEL_FMAP_8_RSVD_1",
- TRQ_SEL_FMAP_8_RSVD_1_MASK},
- {"TRQ_SEL_FMAP_8_QID_MAX",
- TRQ_SEL_FMAP_8_QID_MAX_MASK},
- {"TRQ_SEL_FMAP_8_QID_BASE",
- TRQ_SEL_FMAP_8_QID_BASE_MASK},
-};
-
-
-static struct regfield_info
- trq_sel_fmap_9_field_info[] = {
- {"TRQ_SEL_FMAP_9_RSVD_1",
- TRQ_SEL_FMAP_9_RSVD_1_MASK},
- {"TRQ_SEL_FMAP_9_QID_MAX",
- TRQ_SEL_FMAP_9_QID_MAX_MASK},
- {"TRQ_SEL_FMAP_9_QID_BASE",
- TRQ_SEL_FMAP_9_QID_BASE_MASK},
-};
-
-
-static struct regfield_info
- trq_sel_fmap_a_field_info[] = {
- {"TRQ_SEL_FMAP_A_RSVD_1",
- TRQ_SEL_FMAP_A_RSVD_1_MASK},
- {"TRQ_SEL_FMAP_A_QID_MAX",
- TRQ_SEL_FMAP_A_QID_MAX_MASK},
- {"TRQ_SEL_FMAP_A_QID_BASE",
- TRQ_SEL_FMAP_A_QID_BASE_MASK},
-};
-
-
-static struct regfield_info
- trq_sel_fmap_b_field_info[] = {
- {"TRQ_SEL_FMAP_B_RSVD_1",
- TRQ_SEL_FMAP_B_RSVD_1_MASK},
- {"TRQ_SEL_FMAP_B_QID_MAX",
- TRQ_SEL_FMAP_B_QID_MAX_MASK},
- {"TRQ_SEL_FMAP_B_QID_BASE",
- TRQ_SEL_FMAP_B_QID_BASE_MASK},
-};
-
-
-static struct regfield_info
- trq_sel_fmap_d_field_info[] = {
- {"TRQ_SEL_FMAP_D_RSVD_1",
- TRQ_SEL_FMAP_D_RSVD_1_MASK},
- {"TRQ_SEL_FMAP_D_QID_MAX",
- TRQ_SEL_FMAP_D_QID_MAX_MASK},
- {"TRQ_SEL_FMAP_D_QID_BASE",
- TRQ_SEL_FMAP_D_QID_BASE_MASK},
-};
-
-
-static struct regfield_info
- trq_sel_fmap_e_field_info[] = {
- {"TRQ_SEL_FMAP_E_RSVD_1",
- TRQ_SEL_FMAP_E_RSVD_1_MASK},
- {"TRQ_SEL_FMAP_E_QID_MAX",
- TRQ_SEL_FMAP_E_QID_MAX_MASK},
- {"TRQ_SEL_FMAP_E_QID_BASE",
- TRQ_SEL_FMAP_E_QID_BASE_MASK},
-};
-
-
-static struct regfield_info
- trq_sel_fmap_f_field_info[] = {
- {"TRQ_SEL_FMAP_F_RSVD_1",
- TRQ_SEL_FMAP_F_RSVD_1_MASK},
- {"TRQ_SEL_FMAP_F_QID_MAX",
- TRQ_SEL_FMAP_F_QID_MAX_MASK},
- {"TRQ_SEL_FMAP_F_QID_BASE",
- TRQ_SEL_FMAP_F_QID_BASE_MASK},
-};
-
-
-static struct regfield_info
- trq_sel_fmap_10_field_info[] = {
- {"TRQ_SEL_FMAP_10_RSVD_1",
- TRQ_SEL_FMAP_10_RSVD_1_MASK},
- {"TRQ_SEL_FMAP_10_QID_MAX",
- TRQ_SEL_FMAP_10_QID_MAX_MASK},
- {"TRQ_SEL_FMAP_10_QID_BASE",
- TRQ_SEL_FMAP_10_QID_BASE_MASK},
-};
-
-
-static struct regfield_info
- trq_sel_fmap_11_field_info[] = {
- {"TRQ_SEL_FMAP_11_RSVD_1",
- TRQ_SEL_FMAP_11_RSVD_1_MASK},
- {"TRQ_SEL_FMAP_11_QID_MAX",
- TRQ_SEL_FMAP_11_QID_MAX_MASK},
- {"TRQ_SEL_FMAP_11_QID_BASE",
- TRQ_SEL_FMAP_11_QID_BASE_MASK},
-};
-
-
-static struct regfield_info
- trq_sel_fmap_12_field_info[] = {
- {"TRQ_SEL_FMAP_12_RSVD_1",
- TRQ_SEL_FMAP_12_RSVD_1_MASK},
- {"TRQ_SEL_FMAP_12_QID_MAX",
- TRQ_SEL_FMAP_12_QID_MAX_MASK},
- {"TRQ_SEL_FMAP_12_QID_BASE",
- TRQ_SEL_FMAP_12_QID_BASE_MASK},
-};
-
-
-static struct regfield_info
- trq_sel_fmap_13_field_info[] = {
- {"TRQ_SEL_FMAP_13_RSVD_1",
- TRQ_SEL_FMAP_13_RSVD_1_MASK},
- {"TRQ_SEL_FMAP_13_QID_MAX",
- TRQ_SEL_FMAP_13_QID_MAX_MASK},
- {"TRQ_SEL_FMAP_13_QID_BASE",
- TRQ_SEL_FMAP_13_QID_BASE_MASK},
-};
-
-
-static struct regfield_info
- trq_sel_fmap_14_field_info[] = {
- {"TRQ_SEL_FMAP_14_RSVD_1",
- TRQ_SEL_FMAP_14_RSVD_1_MASK},
- {"TRQ_SEL_FMAP_14_QID_MAX",
- TRQ_SEL_FMAP_14_QID_MAX_MASK},
- {"TRQ_SEL_FMAP_14_QID_BASE",
- TRQ_SEL_FMAP_14_QID_BASE_MASK},
-};
-
-
-static struct regfield_info
- trq_sel_fmap_15_field_info[] = {
- {"TRQ_SEL_FMAP_15_RSVD_1",
- TRQ_SEL_FMAP_15_RSVD_1_MASK},
- {"TRQ_SEL_FMAP_15_QID_MAX",
- TRQ_SEL_FMAP_15_QID_MAX_MASK},
- {"TRQ_SEL_FMAP_15_QID_BASE",
- TRQ_SEL_FMAP_15_QID_BASE_MASK},
-};
-
-
-static struct regfield_info
- trq_sel_fmap_16_field_info[] = {
- {"TRQ_SEL_FMAP_16_RSVD_1",
- TRQ_SEL_FMAP_16_RSVD_1_MASK},
- {"TRQ_SEL_FMAP_16_QID_MAX",
- TRQ_SEL_FMAP_16_QID_MAX_MASK},
- {"TRQ_SEL_FMAP_16_QID_BASE",
- TRQ_SEL_FMAP_16_QID_BASE_MASK},
-};
-
-
-static struct regfield_info
- trq_sel_fmap_17_field_info[] = {
- {"TRQ_SEL_FMAP_17_RSVD_1",
- TRQ_SEL_FMAP_17_RSVD_1_MASK},
- {"TRQ_SEL_FMAP_17_QID_MAX",
- TRQ_SEL_FMAP_17_QID_MAX_MASK},
- {"TRQ_SEL_FMAP_17_QID_BASE",
- TRQ_SEL_FMAP_17_QID_BASE_MASK},
-};
-
-
-static struct regfield_info
- trq_sel_fmap_18_field_info[] = {
- {"TRQ_SEL_FMAP_18_RSVD_1",
- TRQ_SEL_FMAP_18_RSVD_1_MASK},
- {"TRQ_SEL_FMAP_18_QID_MAX",
- TRQ_SEL_FMAP_18_QID_MAX_MASK},
- {"TRQ_SEL_FMAP_18_QID_BASE",
- TRQ_SEL_FMAP_18_QID_BASE_MASK},
-};
-
-
-static struct regfield_info
- trq_sel_fmap_19_field_info[] = {
- {"TRQ_SEL_FMAP_19_RSVD_1",
- TRQ_SEL_FMAP_19_RSVD_1_MASK},
- {"TRQ_SEL_FMAP_19_QID_MAX",
- TRQ_SEL_FMAP_19_QID_MAX_MASK},
- {"TRQ_SEL_FMAP_19_QID_BASE",
- TRQ_SEL_FMAP_19_QID_BASE_MASK},
-};
-
-
-static struct regfield_info
- trq_sel_fmap_1a_field_info[] = {
- {"TRQ_SEL_FMAP_1A_RSVD_1",
- TRQ_SEL_FMAP_1A_RSVD_1_MASK},
- {"TRQ_SEL_FMAP_1A_QID_MAX",
- TRQ_SEL_FMAP_1A_QID_MAX_MASK},
- {"TRQ_SEL_FMAP_1A_QID_BASE",
- TRQ_SEL_FMAP_1A_QID_BASE_MASK},
-};
-
-
-static struct regfield_info
- trq_sel_fmap_1b_field_info[] = {
- {"TRQ_SEL_FMAP_1B_RSVD_1",
- TRQ_SEL_FMAP_1B_RSVD_1_MASK},
- {"TRQ_SEL_FMAP_1B_QID_MAX",
- TRQ_SEL_FMAP_1B_QID_MAX_MASK},
- {"TRQ_SEL_FMAP_1B_QID_BASE",
- TRQ_SEL_FMAP_1B_QID_BASE_MASK},
-};
-
-
-static struct regfield_info
- trq_sel_fmap_1c_field_info[] = {
- {"TRQ_SEL_FMAP_1C_RSVD_1",
- TRQ_SEL_FMAP_1C_RSVD_1_MASK},
- {"TRQ_SEL_FMAP_1C_QID_MAX",
- TRQ_SEL_FMAP_1C_QID_MAX_MASK},
- {"TRQ_SEL_FMAP_1C_QID_BASE",
- TRQ_SEL_FMAP_1C_QID_BASE_MASK},
-};
-
-
-static struct regfield_info
- trq_sel_fmap_1d_field_info[] = {
- {"TRQ_SEL_FMAP_1D_RSVD_1",
- TRQ_SEL_FMAP_1D_RSVD_1_MASK},
- {"TRQ_SEL_FMAP_1D_QID_MAX",
- TRQ_SEL_FMAP_1D_QID_MAX_MASK},
- {"TRQ_SEL_FMAP_1D_QID_BASE",
- TRQ_SEL_FMAP_1D_QID_BASE_MASK},
-};
-
-
-static struct regfield_info
- trq_sel_fmap_1e_field_info[] = {
- {"TRQ_SEL_FMAP_1E_RSVD_1",
- TRQ_SEL_FMAP_1E_RSVD_1_MASK},
- {"TRQ_SEL_FMAP_1E_QID_MAX",
- TRQ_SEL_FMAP_1E_QID_MAX_MASK},
- {"TRQ_SEL_FMAP_1E_QID_BASE",
- TRQ_SEL_FMAP_1E_QID_BASE_MASK},
-};
-
-
-static struct regfield_info
- trq_sel_fmap_1f_field_info[] = {
- {"TRQ_SEL_FMAP_1F_RSVD_1",
- TRQ_SEL_FMAP_1F_RSVD_1_MASK},
- {"TRQ_SEL_FMAP_1F_QID_MAX",
- TRQ_SEL_FMAP_1F_QID_MAX_MASK},
- {"TRQ_SEL_FMAP_1F_QID_BASE",
- TRQ_SEL_FMAP_1F_QID_BASE_MASK},
-};
-
-
-static struct regfield_info
- trq_sel_fmap_20_field_info[] = {
- {"TRQ_SEL_FMAP_20_RSVD_1",
- TRQ_SEL_FMAP_20_RSVD_1_MASK},
- {"TRQ_SEL_FMAP_20_QID_MAX",
- TRQ_SEL_FMAP_20_QID_MAX_MASK},
- {"TRQ_SEL_FMAP_20_QID_BASE",
- TRQ_SEL_FMAP_20_QID_BASE_MASK},
-};
-
-
-static struct regfield_info
- trq_sel_fmap_21_field_info[] = {
- {"TRQ_SEL_FMAP_21_RSVD_1",
- TRQ_SEL_FMAP_21_RSVD_1_MASK},
- {"TRQ_SEL_FMAP_21_QID_MAX",
- TRQ_SEL_FMAP_21_QID_MAX_MASK},
- {"TRQ_SEL_FMAP_21_QID_BASE",
- TRQ_SEL_FMAP_21_QID_BASE_MASK},
-};
-
-
-static struct regfield_info
- trq_sel_fmap_22_field_info[] = {
- {"TRQ_SEL_FMAP_22_RSVD_1",
- TRQ_SEL_FMAP_22_RSVD_1_MASK},
- {"TRQ_SEL_FMAP_22_QID_MAX",
- TRQ_SEL_FMAP_22_QID_MAX_MASK},
- {"TRQ_SEL_FMAP_22_QID_BASE",
- TRQ_SEL_FMAP_22_QID_BASE_MASK},
-};
-
-
-static struct regfield_info
- trq_sel_fmap_23_field_info[] = {
- {"TRQ_SEL_FMAP_23_RSVD_1",
- TRQ_SEL_FMAP_23_RSVD_1_MASK},
- {"TRQ_SEL_FMAP_23_QID_MAX",
- TRQ_SEL_FMAP_23_QID_MAX_MASK},
- {"TRQ_SEL_FMAP_23_QID_BASE",
- TRQ_SEL_FMAP_23_QID_BASE_MASK},
-};
-
-
-static struct regfield_info
- trq_sel_fmap_24_field_info[] = {
- {"TRQ_SEL_FMAP_24_RSVD_1",
- TRQ_SEL_FMAP_24_RSVD_1_MASK},
- {"TRQ_SEL_FMAP_24_QID_MAX",
- TRQ_SEL_FMAP_24_QID_MAX_MASK},
- {"TRQ_SEL_FMAP_24_QID_BASE",
- TRQ_SEL_FMAP_24_QID_BASE_MASK},
-};
-
-
-static struct regfield_info
- trq_sel_fmap_25_field_info[] = {
- {"TRQ_SEL_FMAP_25_RSVD_1",
- TRQ_SEL_FMAP_25_RSVD_1_MASK},
- {"TRQ_SEL_FMAP_25_QID_MAX",
- TRQ_SEL_FMAP_25_QID_MAX_MASK},
- {"TRQ_SEL_FMAP_25_QID_BASE",
- TRQ_SEL_FMAP_25_QID_BASE_MASK},
-};
-
-
-static struct regfield_info
- trq_sel_fmap_26_field_info[] = {
- {"TRQ_SEL_FMAP_26_RSVD_1",
- TRQ_SEL_FMAP_26_RSVD_1_MASK},
- {"TRQ_SEL_FMAP_26_QID_MAX",
- TRQ_SEL_FMAP_26_QID_MAX_MASK},
- {"TRQ_SEL_FMAP_26_QID_BASE",
- TRQ_SEL_FMAP_26_QID_BASE_MASK},
-};
-
-
-static struct regfield_info
- trq_sel_fmap_27_field_info[] = {
- {"TRQ_SEL_FMAP_27_RSVD_1",
- TRQ_SEL_FMAP_27_RSVD_1_MASK},
- {"TRQ_SEL_FMAP_27_QID_MAX",
- TRQ_SEL_FMAP_27_QID_MAX_MASK},
- {"TRQ_SEL_FMAP_27_QID_BASE",
- TRQ_SEL_FMAP_27_QID_BASE_MASK},
-};
-
-
-static struct regfield_info
- trq_sel_fmap_28_field_info[] = {
- {"TRQ_SEL_FMAP_28_RSVD_1",
- TRQ_SEL_FMAP_28_RSVD_1_MASK},
- {"TRQ_SEL_FMAP_28_QID_MAX",
- TRQ_SEL_FMAP_28_QID_MAX_MASK},
- {"TRQ_SEL_FMAP_28_QID_BASE",
- TRQ_SEL_FMAP_28_QID_BASE_MASK},
-};
-
-
-static struct regfield_info
- trq_sel_fmap_29_field_info[] = {
- {"TRQ_SEL_FMAP_29_RSVD_1",
- TRQ_SEL_FMAP_29_RSVD_1_MASK},
- {"TRQ_SEL_FMAP_29_QID_MAX",
- TRQ_SEL_FMAP_29_QID_MAX_MASK},
- {"TRQ_SEL_FMAP_29_QID_BASE",
- TRQ_SEL_FMAP_29_QID_BASE_MASK},
-};
-
-
-static struct regfield_info
- trq_sel_fmap_2a_field_info[] = {
- {"TRQ_SEL_FMAP_2A_RSVD_1",
- TRQ_SEL_FMAP_2A_RSVD_1_MASK},
- {"TRQ_SEL_FMAP_2A_QID_MAX",
- TRQ_SEL_FMAP_2A_QID_MAX_MASK},
- {"TRQ_SEL_FMAP_2A_QID_BASE",
- TRQ_SEL_FMAP_2A_QID_BASE_MASK},
-};
-
-
-static struct regfield_info
- trq_sel_fmap_2b_field_info[] = {
- {"TRQ_SEL_FMAP_2B_RSVD_1",
- TRQ_SEL_FMAP_2B_RSVD_1_MASK},
- {"TRQ_SEL_FMAP_2B_QID_MAX",
- TRQ_SEL_FMAP_2B_QID_MAX_MASK},
- {"TRQ_SEL_FMAP_2B_QID_BASE",
- TRQ_SEL_FMAP_2B_QID_BASE_MASK},
-};
-
-
-static struct regfield_info
- trq_sel_fmap_2c_field_info[] = {
- {"TRQ_SEL_FMAP_2C_RSVD_1",
- TRQ_SEL_FMAP_2C_RSVD_1_MASK},
- {"TRQ_SEL_FMAP_2C_QID_MAX",
- TRQ_SEL_FMAP_2C_QID_MAX_MASK},
- {"TRQ_SEL_FMAP_2C_QID_BASE",
- TRQ_SEL_FMAP_2C_QID_BASE_MASK},
-};
-
-
-static struct regfield_info
- trq_sel_fmap_2d_field_info[] = {
- {"TRQ_SEL_FMAP_2D_RSVD_1",
- TRQ_SEL_FMAP_2D_RSVD_1_MASK},
- {"TRQ_SEL_FMAP_2D_QID_MAX",
- TRQ_SEL_FMAP_2D_QID_MAX_MASK},
- {"TRQ_SEL_FMAP_2D_QID_BASE",
- TRQ_SEL_FMAP_2D_QID_BASE_MASK},
-};
-
-
-static struct regfield_info
- trq_sel_fmap_2e_field_info[] = {
- {"TRQ_SEL_FMAP_2E_RSVD_1",
- TRQ_SEL_FMAP_2E_RSVD_1_MASK},
- {"TRQ_SEL_FMAP_2E_QID_MAX",
- TRQ_SEL_FMAP_2E_QID_MAX_MASK},
- {"TRQ_SEL_FMAP_2E_QID_BASE",
- TRQ_SEL_FMAP_2E_QID_BASE_MASK},
-};
-
-
-static struct regfield_info
- trq_sel_fmap_2f_field_info[] = {
- {"TRQ_SEL_FMAP_2F_RSVD_1",
- TRQ_SEL_FMAP_2F_RSVD_1_MASK},
- {"TRQ_SEL_FMAP_2F_QID_MAX",
- TRQ_SEL_FMAP_2F_QID_MAX_MASK},
- {"TRQ_SEL_FMAP_2F_QID_BASE",
- TRQ_SEL_FMAP_2F_QID_BASE_MASK},
-};
-
-
-static struct regfield_info
- trq_sel_fmap_30_field_info[] = {
- {"TRQ_SEL_FMAP_30_RSVD_1",
- TRQ_SEL_FMAP_30_RSVD_1_MASK},
- {"TRQ_SEL_FMAP_30_QID_MAX",
- TRQ_SEL_FMAP_30_QID_MAX_MASK},
- {"TRQ_SEL_FMAP_30_QID_BASE",
- TRQ_SEL_FMAP_30_QID_BASE_MASK},
-};
-
-
-static struct regfield_info
- trq_sel_fmap_31_field_info[] = {
- {"TRQ_SEL_FMAP_31_RSVD_1",
- TRQ_SEL_FMAP_31_RSVD_1_MASK},
- {"TRQ_SEL_FMAP_31_QID_MAX",
- TRQ_SEL_FMAP_31_QID_MAX_MASK},
- {"TRQ_SEL_FMAP_31_QID_BASE",
- TRQ_SEL_FMAP_31_QID_BASE_MASK},
-};
-
-
-static struct regfield_info
- trq_sel_fmap_32_field_info[] = {
- {"TRQ_SEL_FMAP_32_RSVD_1",
- TRQ_SEL_FMAP_32_RSVD_1_MASK},
- {"TRQ_SEL_FMAP_32_QID_MAX",
- TRQ_SEL_FMAP_32_QID_MAX_MASK},
- {"TRQ_SEL_FMAP_32_QID_BASE",
- TRQ_SEL_FMAP_32_QID_BASE_MASK},
-};
-
-
-static struct regfield_info
- trq_sel_fmap_33_field_info[] = {
- {"TRQ_SEL_FMAP_33_RSVD_1",
- TRQ_SEL_FMAP_33_RSVD_1_MASK},
- {"TRQ_SEL_FMAP_33_QID_MAX",
- TRQ_SEL_FMAP_33_QID_MAX_MASK},
- {"TRQ_SEL_FMAP_33_QID_BASE",
- TRQ_SEL_FMAP_33_QID_BASE_MASK},
-};
-
-
-static struct regfield_info
- trq_sel_fmap_34_field_info[] = {
- {"TRQ_SEL_FMAP_34_RSVD_1",
- TRQ_SEL_FMAP_34_RSVD_1_MASK},
- {"TRQ_SEL_FMAP_34_QID_MAX",
- TRQ_SEL_FMAP_34_QID_MAX_MASK},
- {"TRQ_SEL_FMAP_34_QID_BASE",
- TRQ_SEL_FMAP_34_QID_BASE_MASK},
-};
-
-
-static struct regfield_info
- trq_sel_fmap_35_field_info[] = {
- {"TRQ_SEL_FMAP_35_RSVD_1",
- TRQ_SEL_FMAP_35_RSVD_1_MASK},
- {"TRQ_SEL_FMAP_35_QID_MAX",
- TRQ_SEL_FMAP_35_QID_MAX_MASK},
- {"TRQ_SEL_FMAP_35_QID_BASE",
- TRQ_SEL_FMAP_35_QID_BASE_MASK},
-};
-
-
-static struct regfield_info
- trq_sel_fmap_36_field_info[] = {
- {"TRQ_SEL_FMAP_36_RSVD_1",
- TRQ_SEL_FMAP_36_RSVD_1_MASK},
- {"TRQ_SEL_FMAP_36_QID_MAX",
- TRQ_SEL_FMAP_36_QID_MAX_MASK},
- {"TRQ_SEL_FMAP_36_QID_BASE",
- TRQ_SEL_FMAP_36_QID_BASE_MASK},
-};
-
-
-static struct regfield_info
- trq_sel_fmap_37_field_info[] = {
- {"TRQ_SEL_FMAP_37_RSVD_1",
- TRQ_SEL_FMAP_37_RSVD_1_MASK},
- {"TRQ_SEL_FMAP_37_QID_MAX",
- TRQ_SEL_FMAP_37_QID_MAX_MASK},
- {"TRQ_SEL_FMAP_37_QID_BASE",
- TRQ_SEL_FMAP_37_QID_BASE_MASK},
-};
-
-
-static struct regfield_info
- trq_sel_fmap_38_field_info[] = {
- {"TRQ_SEL_FMAP_38_RSVD_1",
- TRQ_SEL_FMAP_38_RSVD_1_MASK},
- {"TRQ_SEL_FMAP_38_QID_MAX",
- TRQ_SEL_FMAP_38_QID_MAX_MASK},
- {"TRQ_SEL_FMAP_38_QID_BASE",
- TRQ_SEL_FMAP_38_QID_BASE_MASK},
-};
-
-
-static struct regfield_info
- trq_sel_fmap_39_field_info[] = {
- {"TRQ_SEL_FMAP_39_RSVD_1",
- TRQ_SEL_FMAP_39_RSVD_1_MASK},
- {"TRQ_SEL_FMAP_39_QID_MAX",
- TRQ_SEL_FMAP_39_QID_MAX_MASK},
- {"TRQ_SEL_FMAP_39_QID_BASE",
- TRQ_SEL_FMAP_39_QID_BASE_MASK},
-};
-
-
-static struct regfield_info
- trq_sel_fmap_3a_field_info[] = {
- {"TRQ_SEL_FMAP_3A_RSVD_1",
- TRQ_SEL_FMAP_3A_RSVD_1_MASK},
- {"TRQ_SEL_FMAP_3A_QID_MAX",
- TRQ_SEL_FMAP_3A_QID_MAX_MASK},
- {"TRQ_SEL_FMAP_3A_QID_BASE",
- TRQ_SEL_FMAP_3A_QID_BASE_MASK},
-};
-
-
-static struct regfield_info
- trq_sel_fmap_3b_field_info[] = {
- {"TRQ_SEL_FMAP_3B_RSVD_1",
- TRQ_SEL_FMAP_3B_RSVD_1_MASK},
- {"TRQ_SEL_FMAP_3B_QID_MAX",
- TRQ_SEL_FMAP_3B_QID_MAX_MASK},
- {"TRQ_SEL_FMAP_3B_QID_BASE",
- TRQ_SEL_FMAP_3B_QID_BASE_MASK},
-};
-
-
-static struct regfield_info
- trq_sel_fmap_3c_field_info[] = {
- {"TRQ_SEL_FMAP_3C_RSVD_1",
- TRQ_SEL_FMAP_3C_RSVD_1_MASK},
- {"TRQ_SEL_FMAP_3C_QID_MAX",
- TRQ_SEL_FMAP_3C_QID_MAX_MASK},
- {"TRQ_SEL_FMAP_3C_QID_BASE",
- TRQ_SEL_FMAP_3C_QID_BASE_MASK},
-};
-
-
-static struct regfield_info
- trq_sel_fmap_3d_field_info[] = {
- {"TRQ_SEL_FMAP_3D_RSVD_1",
- TRQ_SEL_FMAP_3D_RSVD_1_MASK},
- {"TRQ_SEL_FMAP_3D_QID_MAX",
- TRQ_SEL_FMAP_3D_QID_MAX_MASK},
- {"TRQ_SEL_FMAP_3D_QID_BASE",
- TRQ_SEL_FMAP_3D_QID_BASE_MASK},
-};
-
-
-static struct regfield_info
- trq_sel_fmap_3e_field_info[] = {
- {"TRQ_SEL_FMAP_3E_RSVD_1",
- TRQ_SEL_FMAP_3E_RSVD_1_MASK},
- {"TRQ_SEL_FMAP_3E_QID_MAX",
- TRQ_SEL_FMAP_3E_QID_MAX_MASK},
- {"TRQ_SEL_FMAP_3E_QID_BASE",
- TRQ_SEL_FMAP_3E_QID_BASE_MASK},
-};
-
-
-static struct regfield_info
- trq_sel_fmap_3f_field_info[] = {
- {"TRQ_SEL_FMAP_3F_RSVD_1",
- TRQ_SEL_FMAP_3F_RSVD_1_MASK},
- {"TRQ_SEL_FMAP_3F_QID_MAX",
- TRQ_SEL_FMAP_3F_QID_MAX_MASK},
- {"TRQ_SEL_FMAP_3F_QID_BASE",
- TRQ_SEL_FMAP_3F_QID_BASE_MASK},
-};
-
-
-static struct regfield_info
- trq_sel_fmap_40_field_info[] = {
- {"TRQ_SEL_FMAP_40_RSVD_1",
- TRQ_SEL_FMAP_40_RSVD_1_MASK},
- {"TRQ_SEL_FMAP_40_QID_MAX",
- TRQ_SEL_FMAP_40_QID_MAX_MASK},
- {"TRQ_SEL_FMAP_40_QID_BASE",
- TRQ_SEL_FMAP_40_QID_BASE_MASK},
-};
-
-
-static struct regfield_info
- trq_sel_fmap_41_field_info[] = {
- {"TRQ_SEL_FMAP_41_RSVD_1",
- TRQ_SEL_FMAP_41_RSVD_1_MASK},
- {"TRQ_SEL_FMAP_41_QID_MAX",
- TRQ_SEL_FMAP_41_QID_MAX_MASK},
- {"TRQ_SEL_FMAP_41_QID_BASE",
- TRQ_SEL_FMAP_41_QID_BASE_MASK},
-};
-
-
-static struct regfield_info
- trq_sel_fmap_42_field_info[] = {
- {"TRQ_SEL_FMAP_42_RSVD_1",
- TRQ_SEL_FMAP_42_RSVD_1_MASK},
- {"TRQ_SEL_FMAP_42_QID_MAX",
- TRQ_SEL_FMAP_42_QID_MAX_MASK},
- {"TRQ_SEL_FMAP_42_QID_BASE",
- TRQ_SEL_FMAP_42_QID_BASE_MASK},
-};
-
-
-static struct regfield_info
- trq_sel_fmap_43_field_info[] = {
- {"TRQ_SEL_FMAP_43_RSVD_1",
- TRQ_SEL_FMAP_43_RSVD_1_MASK},
- {"TRQ_SEL_FMAP_43_QID_MAX",
- TRQ_SEL_FMAP_43_QID_MAX_MASK},
- {"TRQ_SEL_FMAP_43_QID_BASE",
- TRQ_SEL_FMAP_43_QID_BASE_MASK},
-};
-
-
-static struct regfield_info
- trq_sel_fmap_44_field_info[] = {
- {"TRQ_SEL_FMAP_44_RSVD_1",
- TRQ_SEL_FMAP_44_RSVD_1_MASK},
- {"TRQ_SEL_FMAP_44_QID_MAX",
- TRQ_SEL_FMAP_44_QID_MAX_MASK},
- {"TRQ_SEL_FMAP_44_QID_BASE",
- TRQ_SEL_FMAP_44_QID_BASE_MASK},
-};
-
-
-static struct regfield_info
- trq_sel_fmap_45_field_info[] = {
- {"TRQ_SEL_FMAP_45_RSVD_1",
- TRQ_SEL_FMAP_45_RSVD_1_MASK},
- {"TRQ_SEL_FMAP_45_QID_MAX",
- TRQ_SEL_FMAP_45_QID_MAX_MASK},
- {"TRQ_SEL_FMAP_45_QID_BASE",
- TRQ_SEL_FMAP_45_QID_BASE_MASK},
-};
-
-
-static struct regfield_info
- trq_sel_fmap_46_field_info[] = {
- {"TRQ_SEL_FMAP_46_RSVD_1",
- TRQ_SEL_FMAP_46_RSVD_1_MASK},
- {"TRQ_SEL_FMAP_46_QID_MAX",
- TRQ_SEL_FMAP_46_QID_MAX_MASK},
- {"TRQ_SEL_FMAP_46_QID_BASE",
- TRQ_SEL_FMAP_46_QID_BASE_MASK},
-};
-
-
-static struct regfield_info
- trq_sel_fmap_47_field_info[] = {
- {"TRQ_SEL_FMAP_47_RSVD_1",
- TRQ_SEL_FMAP_47_RSVD_1_MASK},
- {"TRQ_SEL_FMAP_47_QID_MAX",
- TRQ_SEL_FMAP_47_QID_MAX_MASK},
- {"TRQ_SEL_FMAP_47_QID_BASE",
- TRQ_SEL_FMAP_47_QID_BASE_MASK},
-};
-
-
-static struct regfield_info
- trq_sel_fmap_48_field_info[] = {
- {"TRQ_SEL_FMAP_48_RSVD_1",
- TRQ_SEL_FMAP_48_RSVD_1_MASK},
- {"TRQ_SEL_FMAP_48_QID_MAX",
- TRQ_SEL_FMAP_48_QID_MAX_MASK},
- {"TRQ_SEL_FMAP_48_QID_BASE",
- TRQ_SEL_FMAP_48_QID_BASE_MASK},
-};
-
-
-static struct regfield_info
- trq_sel_fmap_49_field_info[] = {
- {"TRQ_SEL_FMAP_49_RSVD_1",
- TRQ_SEL_FMAP_49_RSVD_1_MASK},
- {"TRQ_SEL_FMAP_49_QID_MAX",
- TRQ_SEL_FMAP_49_QID_MAX_MASK},
- {"TRQ_SEL_FMAP_49_QID_BASE",
- TRQ_SEL_FMAP_49_QID_BASE_MASK},
-};
-
-
-static struct regfield_info
- trq_sel_fmap_4a_field_info[] = {
- {"TRQ_SEL_FMAP_4A_RSVD_1",
- TRQ_SEL_FMAP_4A_RSVD_1_MASK},
- {"TRQ_SEL_FMAP_4A_QID_MAX",
- TRQ_SEL_FMAP_4A_QID_MAX_MASK},
- {"TRQ_SEL_FMAP_4A_QID_BASE",
- TRQ_SEL_FMAP_4A_QID_BASE_MASK},
-};
-
-
-static struct regfield_info
- trq_sel_fmap_4b_field_info[] = {
- {"TRQ_SEL_FMAP_4B_RSVD_1",
- TRQ_SEL_FMAP_4B_RSVD_1_MASK},
- {"TRQ_SEL_FMAP_4B_QID_MAX",
- TRQ_SEL_FMAP_4B_QID_MAX_MASK},
- {"TRQ_SEL_FMAP_4B_QID_BASE",
- TRQ_SEL_FMAP_4B_QID_BASE_MASK},
-};
-
-
-static struct regfield_info
- trq_sel_fmap_4c_field_info[] = {
- {"TRQ_SEL_FMAP_4C_RSVD_1",
- TRQ_SEL_FMAP_4C_RSVD_1_MASK},
- {"TRQ_SEL_FMAP_4C_QID_MAX",
- TRQ_SEL_FMAP_4C_QID_MAX_MASK},
- {"TRQ_SEL_FMAP_4C_QID_BASE",
- TRQ_SEL_FMAP_4C_QID_BASE_MASK},
-};
-
-
-static struct regfield_info
- trq_sel_fmap_4d_field_info[] = {
- {"TRQ_SEL_FMAP_4D_RSVD_1",
- TRQ_SEL_FMAP_4D_RSVD_1_MASK},
- {"TRQ_SEL_FMAP_4D_QID_MAX",
- TRQ_SEL_FMAP_4D_QID_MAX_MASK},
- {"TRQ_SEL_FMAP_4D_QID_BASE",
- TRQ_SEL_FMAP_4D_QID_BASE_MASK},
-};
-
-
-static struct regfield_info
- trq_sel_fmap_4e_field_info[] = {
- {"TRQ_SEL_FMAP_4E_RSVD_1",
- TRQ_SEL_FMAP_4E_RSVD_1_MASK},
- {"TRQ_SEL_FMAP_4E_QID_MAX",
- TRQ_SEL_FMAP_4E_QID_MAX_MASK},
- {"TRQ_SEL_FMAP_4E_QID_BASE",
- TRQ_SEL_FMAP_4E_QID_BASE_MASK},
-};
-
-
-static struct regfield_info
- trq_sel_fmap_4f_field_info[] = {
- {"TRQ_SEL_FMAP_4F_RSVD_1",
- TRQ_SEL_FMAP_4F_RSVD_1_MASK},
- {"TRQ_SEL_FMAP_4F_QID_MAX",
- TRQ_SEL_FMAP_4F_QID_MAX_MASK},
- {"TRQ_SEL_FMAP_4F_QID_BASE",
- TRQ_SEL_FMAP_4F_QID_BASE_MASK},
-};
-
-
-static struct regfield_info
- trq_sel_fmap_50_field_info[] = {
- {"TRQ_SEL_FMAP_50_RSVD_1",
- TRQ_SEL_FMAP_50_RSVD_1_MASK},
- {"TRQ_SEL_FMAP_50_QID_MAX",
- TRQ_SEL_FMAP_50_QID_MAX_MASK},
- {"TRQ_SEL_FMAP_50_QID_BASE",
- TRQ_SEL_FMAP_50_QID_BASE_MASK},
-};
-
-
-static struct regfield_info
- trq_sel_fmap_51_field_info[] = {
- {"TRQ_SEL_FMAP_51_RSVD_1",
- TRQ_SEL_FMAP_51_RSVD_1_MASK},
- {"TRQ_SEL_FMAP_51_QID_MAX",
- TRQ_SEL_FMAP_51_QID_MAX_MASK},
- {"TRQ_SEL_FMAP_51_QID_BASE",
- TRQ_SEL_FMAP_51_QID_BASE_MASK},
-};
-
-
-static struct regfield_info
- trq_sel_fmap_52_field_info[] = {
- {"TRQ_SEL_FMAP_52_RSVD_1",
- TRQ_SEL_FMAP_52_RSVD_1_MASK},
- {"TRQ_SEL_FMAP_52_QID_MAX",
- TRQ_SEL_FMAP_52_QID_MAX_MASK},
- {"TRQ_SEL_FMAP_52_QID_BASE",
- TRQ_SEL_FMAP_52_QID_BASE_MASK},
-};
-
-
-static struct regfield_info
- trq_sel_fmap_53_field_info[] = {
- {"TRQ_SEL_FMAP_53_RSVD_1",
- TRQ_SEL_FMAP_53_RSVD_1_MASK},
- {"TRQ_SEL_FMAP_53_QID_MAX",
- TRQ_SEL_FMAP_53_QID_MAX_MASK},
- {"TRQ_SEL_FMAP_53_QID_BASE",
- TRQ_SEL_FMAP_53_QID_BASE_MASK},
-};
-
-
-static struct regfield_info
- trq_sel_fmap_54_field_info[] = {
- {"TRQ_SEL_FMAP_54_RSVD_1",
- TRQ_SEL_FMAP_54_RSVD_1_MASK},
- {"TRQ_SEL_FMAP_54_QID_MAX",
- TRQ_SEL_FMAP_54_QID_MAX_MASK},
- {"TRQ_SEL_FMAP_54_QID_BASE",
- TRQ_SEL_FMAP_54_QID_BASE_MASK},
-};
-
-
-static struct regfield_info
- trq_sel_fmap_55_field_info[] = {
- {"TRQ_SEL_FMAP_55_RSVD_1",
- TRQ_SEL_FMAP_55_RSVD_1_MASK},
- {"TRQ_SEL_FMAP_55_QID_MAX",
- TRQ_SEL_FMAP_55_QID_MAX_MASK},
- {"TRQ_SEL_FMAP_55_QID_BASE",
- TRQ_SEL_FMAP_55_QID_BASE_MASK},
-};
-
-
-static struct regfield_info
- trq_sel_fmap_56_field_info[] = {
- {"TRQ_SEL_FMAP_56_RSVD_1",
- TRQ_SEL_FMAP_56_RSVD_1_MASK},
- {"TRQ_SEL_FMAP_56_QID_MAX",
- TRQ_SEL_FMAP_56_QID_MAX_MASK},
- {"TRQ_SEL_FMAP_56_QID_BASE",
- TRQ_SEL_FMAP_56_QID_BASE_MASK},
-};
-
-
-static struct regfield_info
- trq_sel_fmap_57_field_info[] = {
- {"TRQ_SEL_FMAP_57_RSVD_1",
- TRQ_SEL_FMAP_57_RSVD_1_MASK},
- {"TRQ_SEL_FMAP_57_QID_MAX",
- TRQ_SEL_FMAP_57_QID_MAX_MASK},
- {"TRQ_SEL_FMAP_57_QID_BASE",
- TRQ_SEL_FMAP_57_QID_BASE_MASK},
-};
-
-
-static struct regfield_info
- trq_sel_fmap_58_field_info[] = {
- {"TRQ_SEL_FMAP_58_RSVD_1",
- TRQ_SEL_FMAP_58_RSVD_1_MASK},
- {"TRQ_SEL_FMAP_58_QID_MAX",
- TRQ_SEL_FMAP_58_QID_MAX_MASK},
- {"TRQ_SEL_FMAP_58_QID_BASE",
- TRQ_SEL_FMAP_58_QID_BASE_MASK},
-};
-
-
-static struct regfield_info
- trq_sel_fmap_59_field_info[] = {
- {"TRQ_SEL_FMAP_59_RSVD_1",
- TRQ_SEL_FMAP_59_RSVD_1_MASK},
- {"TRQ_SEL_FMAP_59_QID_MAX",
- TRQ_SEL_FMAP_59_QID_MAX_MASK},
- {"TRQ_SEL_FMAP_59_QID_BASE",
- TRQ_SEL_FMAP_59_QID_BASE_MASK},
-};
-
-
-static struct regfield_info
- trq_sel_fmap_5a_field_info[] = {
- {"TRQ_SEL_FMAP_5A_RSVD_1",
- TRQ_SEL_FMAP_5A_RSVD_1_MASK},
- {"TRQ_SEL_FMAP_5A_QID_MAX",
- TRQ_SEL_FMAP_5A_QID_MAX_MASK},
- {"TRQ_SEL_FMAP_5A_QID_BASE",
- TRQ_SEL_FMAP_5A_QID_BASE_MASK},
-};
-
-
-static struct regfield_info
- trq_sel_fmap_5b_field_info[] = {
- {"TRQ_SEL_FMAP_5B_RSVD_1",
- TRQ_SEL_FMAP_5B_RSVD_1_MASK},
- {"TRQ_SEL_FMAP_5B_QID_MAX",
- TRQ_SEL_FMAP_5B_QID_MAX_MASK},
- {"TRQ_SEL_FMAP_5B_QID_BASE",
- TRQ_SEL_FMAP_5B_QID_BASE_MASK},
-};
-
-
-static struct regfield_info
- trq_sel_fmap_5c_field_info[] = {
- {"TRQ_SEL_FMAP_5C_RSVD_1",
- TRQ_SEL_FMAP_5C_RSVD_1_MASK},
- {"TRQ_SEL_FMAP_5C_QID_MAX",
- TRQ_SEL_FMAP_5C_QID_MAX_MASK},
- {"TRQ_SEL_FMAP_5C_QID_BASE",
- TRQ_SEL_FMAP_5C_QID_BASE_MASK},
-};
-
-
-static struct regfield_info
- trq_sel_fmap_5d_field_info[] = {
- {"TRQ_SEL_FMAP_5D_RSVD_1",
- TRQ_SEL_FMAP_5D_RSVD_1_MASK},
- {"TRQ_SEL_FMAP_5D_QID_MAX",
- TRQ_SEL_FMAP_5D_QID_MAX_MASK},
- {"TRQ_SEL_FMAP_5D_QID_BASE",
- TRQ_SEL_FMAP_5D_QID_BASE_MASK},
-};
-
-
-static struct regfield_info
- trq_sel_fmap_5e_field_info[] = {
- {"TRQ_SEL_FMAP_5E_RSVD_1",
- TRQ_SEL_FMAP_5E_RSVD_1_MASK},
- {"TRQ_SEL_FMAP_5E_QID_MAX",
- TRQ_SEL_FMAP_5E_QID_MAX_MASK},
- {"TRQ_SEL_FMAP_5E_QID_BASE",
- TRQ_SEL_FMAP_5E_QID_BASE_MASK},
-};
-
-
-static struct regfield_info
- trq_sel_fmap_5f_field_info[] = {
- {"TRQ_SEL_FMAP_5F_RSVD_1",
- TRQ_SEL_FMAP_5F_RSVD_1_MASK},
- {"TRQ_SEL_FMAP_5F_QID_MAX",
- TRQ_SEL_FMAP_5F_QID_MAX_MASK},
- {"TRQ_SEL_FMAP_5F_QID_BASE",
- TRQ_SEL_FMAP_5F_QID_BASE_MASK},
-};
-
-
-static struct regfield_info
- trq_sel_fmap_60_field_info[] = {
- {"TRQ_SEL_FMAP_60_RSVD_1",
- TRQ_SEL_FMAP_60_RSVD_1_MASK},
- {"TRQ_SEL_FMAP_60_QID_MAX",
- TRQ_SEL_FMAP_60_QID_MAX_MASK},
- {"TRQ_SEL_FMAP_60_QID_BASE",
- TRQ_SEL_FMAP_60_QID_BASE_MASK},
-};
-
-
-static struct regfield_info
- trq_sel_fmap_61_field_info[] = {
- {"TRQ_SEL_FMAP_61_RSVD_1",
- TRQ_SEL_FMAP_61_RSVD_1_MASK},
- {"TRQ_SEL_FMAP_61_QID_MAX",
- TRQ_SEL_FMAP_61_QID_MAX_MASK},
- {"TRQ_SEL_FMAP_61_QID_BASE",
- TRQ_SEL_FMAP_61_QID_BASE_MASK},
-};
-
-
-static struct regfield_info
- trq_sel_fmap_62_field_info[] = {
- {"TRQ_SEL_FMAP_62_RSVD_1",
- TRQ_SEL_FMAP_62_RSVD_1_MASK},
- {"TRQ_SEL_FMAP_62_QID_MAX",
- TRQ_SEL_FMAP_62_QID_MAX_MASK},
- {"TRQ_SEL_FMAP_62_QID_BASE",
- TRQ_SEL_FMAP_62_QID_BASE_MASK},
-};
-
-
-static struct regfield_info
- trq_sel_fmap_63_field_info[] = {
- {"TRQ_SEL_FMAP_63_RSVD_1",
- TRQ_SEL_FMAP_63_RSVD_1_MASK},
- {"TRQ_SEL_FMAP_63_QID_MAX",
- TRQ_SEL_FMAP_63_QID_MAX_MASK},
- {"TRQ_SEL_FMAP_63_QID_BASE",
- TRQ_SEL_FMAP_63_QID_BASE_MASK},
-};
-
-
-static struct regfield_info
- trq_sel_fmap_64_field_info[] = {
- {"TRQ_SEL_FMAP_64_RSVD_1",
- TRQ_SEL_FMAP_64_RSVD_1_MASK},
- {"TRQ_SEL_FMAP_64_QID_MAX",
- TRQ_SEL_FMAP_64_QID_MAX_MASK},
- {"TRQ_SEL_FMAP_64_QID_BASE",
- TRQ_SEL_FMAP_64_QID_BASE_MASK},
-};
-
-
-static struct regfield_info
- trq_sel_fmap_65_field_info[] = {
- {"TRQ_SEL_FMAP_65_RSVD_1",
- TRQ_SEL_FMAP_65_RSVD_1_MASK},
- {"TRQ_SEL_FMAP_65_QID_MAX",
- TRQ_SEL_FMAP_65_QID_MAX_MASK},
- {"TRQ_SEL_FMAP_65_QID_BASE",
- TRQ_SEL_FMAP_65_QID_BASE_MASK},
-};
-
-
-static struct regfield_info
- trq_sel_fmap_66_field_info[] = {
- {"TRQ_SEL_FMAP_66_RSVD_1",
- TRQ_SEL_FMAP_66_RSVD_1_MASK},
- {"TRQ_SEL_FMAP_66_QID_MAX",
- TRQ_SEL_FMAP_66_QID_MAX_MASK},
- {"TRQ_SEL_FMAP_66_QID_BASE",
- TRQ_SEL_FMAP_66_QID_BASE_MASK},
-};
-
-
-static struct regfield_info
- trq_sel_fmap_67_field_info[] = {
- {"TRQ_SEL_FMAP_67_RSVD_1",
- TRQ_SEL_FMAP_67_RSVD_1_MASK},
- {"TRQ_SEL_FMAP_67_QID_MAX",
- TRQ_SEL_FMAP_67_QID_MAX_MASK},
- {"TRQ_SEL_FMAP_67_QID_BASE",
- TRQ_SEL_FMAP_67_QID_BASE_MASK},
-};
-
-
-static struct regfield_info
- trq_sel_fmap_68_field_info[] = {
- {"TRQ_SEL_FMAP_68_RSVD_1",
- TRQ_SEL_FMAP_68_RSVD_1_MASK},
- {"TRQ_SEL_FMAP_68_QID_MAX",
- TRQ_SEL_FMAP_68_QID_MAX_MASK},
- {"TRQ_SEL_FMAP_68_QID_BASE",
- TRQ_SEL_FMAP_68_QID_BASE_MASK},
-};
-
-
-static struct regfield_info
- trq_sel_fmap_69_field_info[] = {
- {"TRQ_SEL_FMAP_69_RSVD_1",
- TRQ_SEL_FMAP_69_RSVD_1_MASK},
- {"TRQ_SEL_FMAP_69_QID_MAX",
- TRQ_SEL_FMAP_69_QID_MAX_MASK},
- {"TRQ_SEL_FMAP_69_QID_BASE",
- TRQ_SEL_FMAP_69_QID_BASE_MASK},
-};
-
-
-static struct regfield_info
- trq_sel_fmap_6a_field_info[] = {
- {"TRQ_SEL_FMAP_6A_RSVD_1",
- TRQ_SEL_FMAP_6A_RSVD_1_MASK},
- {"TRQ_SEL_FMAP_6A_QID_MAX",
- TRQ_SEL_FMAP_6A_QID_MAX_MASK},
- {"TRQ_SEL_FMAP_6A_QID_BASE",
- TRQ_SEL_FMAP_6A_QID_BASE_MASK},
-};
-
-
-static struct regfield_info
- trq_sel_fmap_6b_field_info[] = {
- {"TRQ_SEL_FMAP_6B_RSVD_1",
- TRQ_SEL_FMAP_6B_RSVD_1_MASK},
- {"TRQ_SEL_FMAP_6B_QID_MAX",
- TRQ_SEL_FMAP_6B_QID_MAX_MASK},
- {"TRQ_SEL_FMAP_6B_QID_BASE",
- TRQ_SEL_FMAP_6B_QID_BASE_MASK},
-};
-
-
-static struct regfield_info
- trq_sel_fmap_6c_field_info[] = {
- {"TRQ_SEL_FMAP_6C_RSVD_1",
- TRQ_SEL_FMAP_6C_RSVD_1_MASK},
- {"TRQ_SEL_FMAP_6C_QID_MAX",
- TRQ_SEL_FMAP_6C_QID_MAX_MASK},
- {"TRQ_SEL_FMAP_6C_QID_BASE",
- TRQ_SEL_FMAP_6C_QID_BASE_MASK},
-};
-
-
-static struct regfield_info
- trq_sel_fmap_6d_field_info[] = {
- {"TRQ_SEL_FMAP_6D_RSVD_1",
- TRQ_SEL_FMAP_6D_RSVD_1_MASK},
- {"TRQ_SEL_FMAP_6D_QID_MAX",
- TRQ_SEL_FMAP_6D_QID_MAX_MASK},
- {"TRQ_SEL_FMAP_6D_QID_BASE",
- TRQ_SEL_FMAP_6D_QID_BASE_MASK},
-};
-
-
-static struct regfield_info
- trq_sel_fmap_6e_field_info[] = {
- {"TRQ_SEL_FMAP_6E_RSVD_1",
- TRQ_SEL_FMAP_6E_RSVD_1_MASK},
- {"TRQ_SEL_FMAP_6E_QID_MAX",
- TRQ_SEL_FMAP_6E_QID_MAX_MASK},
- {"TRQ_SEL_FMAP_6E_QID_BASE",
- TRQ_SEL_FMAP_6E_QID_BASE_MASK},
-};
-
-
-static struct regfield_info
- trq_sel_fmap_6f_field_info[] = {
- {"TRQ_SEL_FMAP_6F_RSVD_1",
- TRQ_SEL_FMAP_6F_RSVD_1_MASK},
- {"TRQ_SEL_FMAP_6F_QID_MAX",
- TRQ_SEL_FMAP_6F_QID_MAX_MASK},
- {"TRQ_SEL_FMAP_6F_QID_BASE",
- TRQ_SEL_FMAP_6F_QID_BASE_MASK},
-};
-
-
-static struct regfield_info
- trq_sel_fmap_70_field_info[] = {
- {"TRQ_SEL_FMAP_70_RSVD_1",
- TRQ_SEL_FMAP_70_RSVD_1_MASK},
- {"TRQ_SEL_FMAP_70_QID_MAX",
- TRQ_SEL_FMAP_70_QID_MAX_MASK},
- {"TRQ_SEL_FMAP_70_QID_BASE",
- TRQ_SEL_FMAP_70_QID_BASE_MASK},
-};
-
-
-static struct regfield_info
- trq_sel_fmap_71_field_info[] = {
- {"TRQ_SEL_FMAP_71_RSVD_1",
- TRQ_SEL_FMAP_71_RSVD_1_MASK},
- {"TRQ_SEL_FMAP_71_QID_MAX",
- TRQ_SEL_FMAP_71_QID_MAX_MASK},
- {"TRQ_SEL_FMAP_71_QID_BASE",
- TRQ_SEL_FMAP_71_QID_BASE_MASK},
-};
-
-
-static struct regfield_info
- trq_sel_fmap_72_field_info[] = {
- {"TRQ_SEL_FMAP_72_RSVD_1",
- TRQ_SEL_FMAP_72_RSVD_1_MASK},
- {"TRQ_SEL_FMAP_72_QID_MAX",
- TRQ_SEL_FMAP_72_QID_MAX_MASK},
- {"TRQ_SEL_FMAP_72_QID_BASE",
- TRQ_SEL_FMAP_72_QID_BASE_MASK},
-};
-
-
-static struct regfield_info
- trq_sel_fmap_73_field_info[] = {
- {"TRQ_SEL_FMAP_73_RSVD_1",
- TRQ_SEL_FMAP_73_RSVD_1_MASK},
- {"TRQ_SEL_FMAP_73_QID_MAX",
- TRQ_SEL_FMAP_73_QID_MAX_MASK},
- {"TRQ_SEL_FMAP_73_QID_BASE",
- TRQ_SEL_FMAP_73_QID_BASE_MASK},
-};
-
-
-static struct regfield_info
- trq_sel_fmap_74_field_info[] = {
- {"TRQ_SEL_FMAP_74_RSVD_1",
- TRQ_SEL_FMAP_74_RSVD_1_MASK},
- {"TRQ_SEL_FMAP_74_QID_MAX",
- TRQ_SEL_FMAP_74_QID_MAX_MASK},
- {"TRQ_SEL_FMAP_74_QID_BASE",
- TRQ_SEL_FMAP_74_QID_BASE_MASK},
-};
-
-
-static struct regfield_info
- trq_sel_fmap_75_field_info[] = {
- {"TRQ_SEL_FMAP_75_RSVD_1",
- TRQ_SEL_FMAP_75_RSVD_1_MASK},
- {"TRQ_SEL_FMAP_75_QID_MAX",
- TRQ_SEL_FMAP_75_QID_MAX_MASK},
- {"TRQ_SEL_FMAP_75_QID_BASE",
- TRQ_SEL_FMAP_75_QID_BASE_MASK},
-};
-
-
-static struct regfield_info
- trq_sel_fmap_76_field_info[] = {
- {"TRQ_SEL_FMAP_76_RSVD_1",
- TRQ_SEL_FMAP_76_RSVD_1_MASK},
- {"TRQ_SEL_FMAP_76_QID_MAX",
- TRQ_SEL_FMAP_76_QID_MAX_MASK},
- {"TRQ_SEL_FMAP_76_QID_BASE",
- TRQ_SEL_FMAP_76_QID_BASE_MASK},
-};
-
-
-static struct regfield_info
- trq_sel_fmap_77_field_info[] = {
- {"TRQ_SEL_FMAP_77_RSVD_1",
- TRQ_SEL_FMAP_77_RSVD_1_MASK},
- {"TRQ_SEL_FMAP_77_QID_MAX",
- TRQ_SEL_FMAP_77_QID_MAX_MASK},
- {"TRQ_SEL_FMAP_77_QID_BASE",
- TRQ_SEL_FMAP_77_QID_BASE_MASK},
-};
-
-
-static struct regfield_info
- trq_sel_fmap_78_field_info[] = {
- {"TRQ_SEL_FMAP_78_RSVD_1",
- TRQ_SEL_FMAP_78_RSVD_1_MASK},
- {"TRQ_SEL_FMAP_78_QID_MAX",
- TRQ_SEL_FMAP_78_QID_MAX_MASK},
- {"TRQ_SEL_FMAP_78_QID_BASE",
- TRQ_SEL_FMAP_78_QID_BASE_MASK},
-};
-
-
-static struct regfield_info
- trq_sel_fmap_79_field_info[] = {
- {"TRQ_SEL_FMAP_79_RSVD_1",
- TRQ_SEL_FMAP_79_RSVD_1_MASK},
- {"TRQ_SEL_FMAP_79_QID_MAX",
- TRQ_SEL_FMAP_79_QID_MAX_MASK},
- {"TRQ_SEL_FMAP_79_QID_BASE",
- TRQ_SEL_FMAP_79_QID_BASE_MASK},
-};
-
-
-static struct regfield_info
- trq_sel_fmap_7a_field_info[] = {
- {"TRQ_SEL_FMAP_7A_RSVD_1",
- TRQ_SEL_FMAP_7A_RSVD_1_MASK},
- {"TRQ_SEL_FMAP_7A_QID_MAX",
- TRQ_SEL_FMAP_7A_QID_MAX_MASK},
- {"TRQ_SEL_FMAP_7A_QID_BASE",
- TRQ_SEL_FMAP_7A_QID_BASE_MASK},
-};
-
-
-static struct regfield_info
- trq_sel_fmap_7b_field_info[] = {
- {"TRQ_SEL_FMAP_7B_RSVD_1",
- TRQ_SEL_FMAP_7B_RSVD_1_MASK},
- {"TRQ_SEL_FMAP_7B_QID_MAX",
- TRQ_SEL_FMAP_7B_QID_MAX_MASK},
- {"TRQ_SEL_FMAP_7B_QID_BASE",
- TRQ_SEL_FMAP_7B_QID_BASE_MASK},
-};
-
-
-static struct regfield_info
- trq_sel_fmap_7c_field_info[] = {
- {"TRQ_SEL_FMAP_7C_RSVD_1",
- TRQ_SEL_FMAP_7C_RSVD_1_MASK},
- {"TRQ_SEL_FMAP_7C_QID_MAX",
- TRQ_SEL_FMAP_7C_QID_MAX_MASK},
- {"TRQ_SEL_FMAP_7C_QID_BASE",
- TRQ_SEL_FMAP_7C_QID_BASE_MASK},
-};
-
-
-static struct regfield_info
- trq_sel_fmap_7d_field_info[] = {
- {"TRQ_SEL_FMAP_7D_RSVD_1",
- TRQ_SEL_FMAP_7D_RSVD_1_MASK},
- {"TRQ_SEL_FMAP_7D_QID_MAX",
- TRQ_SEL_FMAP_7D_QID_MAX_MASK},
- {"TRQ_SEL_FMAP_7D_QID_BASE",
- TRQ_SEL_FMAP_7D_QID_BASE_MASK},
-};
-
-
-static struct regfield_info
- trq_sel_fmap_7e_field_info[] = {
- {"TRQ_SEL_FMAP_7E_RSVD_1",
- TRQ_SEL_FMAP_7E_RSVD_1_MASK},
- {"TRQ_SEL_FMAP_7E_QID_MAX",
- TRQ_SEL_FMAP_7E_QID_MAX_MASK},
- {"TRQ_SEL_FMAP_7E_QID_BASE",
- TRQ_SEL_FMAP_7E_QID_BASE_MASK},
-};
-
-
-static struct regfield_info
- trq_sel_fmap_7f_field_info[] = {
- {"TRQ_SEL_FMAP_7F_RSVD_1",
- TRQ_SEL_FMAP_7F_RSVD_1_MASK},
- {"TRQ_SEL_FMAP_7F_QID_MAX",
- TRQ_SEL_FMAP_7F_QID_MAX_MASK},
- {"TRQ_SEL_FMAP_7F_QID_BASE",
- TRQ_SEL_FMAP_7F_QID_BASE_MASK},
-};
-
-
-static struct regfield_info
- trq_sel_fmap_80_field_info[] = {
- {"TRQ_SEL_FMAP_80_RSVD_1",
- TRQ_SEL_FMAP_80_RSVD_1_MASK},
- {"TRQ_SEL_FMAP_80_QID_MAX",
- TRQ_SEL_FMAP_80_QID_MAX_MASK},
- {"TRQ_SEL_FMAP_80_QID_BASE",
- TRQ_SEL_FMAP_80_QID_BASE_MASK},
-};
-
-
-static struct regfield_info
- trq_sel_fmap_81_field_info[] = {
- {"TRQ_SEL_FMAP_81_RSVD_1",
- TRQ_SEL_FMAP_81_RSVD_1_MASK},
- {"TRQ_SEL_FMAP_81_QID_MAX",
- TRQ_SEL_FMAP_81_QID_MAX_MASK},
- {"TRQ_SEL_FMAP_81_QID_BASE",
- TRQ_SEL_FMAP_81_QID_BASE_MASK},
-};
-
-
-static struct regfield_info
- trq_sel_fmap_82_field_info[] = {
- {"TRQ_SEL_FMAP_82_RSVD_1",
- TRQ_SEL_FMAP_82_RSVD_1_MASK},
- {"TRQ_SEL_FMAP_82_QID_MAX",
- TRQ_SEL_FMAP_82_QID_MAX_MASK},
- {"TRQ_SEL_FMAP_82_QID_BASE",
- TRQ_SEL_FMAP_82_QID_BASE_MASK},
-};
-
-
-static struct regfield_info
- trq_sel_fmap_83_field_info[] = {
- {"TRQ_SEL_FMAP_83_RSVD_1",
- TRQ_SEL_FMAP_83_RSVD_1_MASK},
- {"TRQ_SEL_FMAP_83_QID_MAX",
- TRQ_SEL_FMAP_83_QID_MAX_MASK},
- {"TRQ_SEL_FMAP_83_QID_BASE",
- TRQ_SEL_FMAP_83_QID_BASE_MASK},
-};
-
-
-static struct regfield_info
- trq_sel_fmap_84_field_info[] = {
- {"TRQ_SEL_FMAP_84_RSVD_1",
- TRQ_SEL_FMAP_84_RSVD_1_MASK},
- {"TRQ_SEL_FMAP_84_QID_MAX",
- TRQ_SEL_FMAP_84_QID_MAX_MASK},
- {"TRQ_SEL_FMAP_84_QID_BASE",
- TRQ_SEL_FMAP_84_QID_BASE_MASK},
-};
-
-
-static struct regfield_info
- trq_sel_fmap_85_field_info[] = {
- {"TRQ_SEL_FMAP_85_RSVD_1",
- TRQ_SEL_FMAP_85_RSVD_1_MASK},
- {"TRQ_SEL_FMAP_85_QID_MAX",
- TRQ_SEL_FMAP_85_QID_MAX_MASK},
- {"TRQ_SEL_FMAP_85_QID_BASE",
- TRQ_SEL_FMAP_85_QID_BASE_MASK},
-};
-
-
-static struct regfield_info
- trq_sel_fmap_86_field_info[] = {
- {"TRQ_SEL_FMAP_86_RSVD_1",
- TRQ_SEL_FMAP_86_RSVD_1_MASK},
- {"TRQ_SEL_FMAP_86_QID_MAX",
- TRQ_SEL_FMAP_86_QID_MAX_MASK},
- {"TRQ_SEL_FMAP_86_QID_BASE",
- TRQ_SEL_FMAP_86_QID_BASE_MASK},
-};
-
-
-static struct regfield_info
- trq_sel_fmap_87_field_info[] = {
- {"TRQ_SEL_FMAP_87_RSVD_1",
- TRQ_SEL_FMAP_87_RSVD_1_MASK},
- {"TRQ_SEL_FMAP_87_QID_MAX",
- TRQ_SEL_FMAP_87_QID_MAX_MASK},
- {"TRQ_SEL_FMAP_87_QID_BASE",
- TRQ_SEL_FMAP_87_QID_BASE_MASK},
-};
-
-
-static struct regfield_info
- trq_sel_fmap_88_field_info[] = {
- {"TRQ_SEL_FMAP_88_RSVD_1",
- TRQ_SEL_FMAP_88_RSVD_1_MASK},
- {"TRQ_SEL_FMAP_88_QID_MAX",
- TRQ_SEL_FMAP_88_QID_MAX_MASK},
- {"TRQ_SEL_FMAP_88_QID_BASE",
- TRQ_SEL_FMAP_88_QID_BASE_MASK},
-};
-
-
-static struct regfield_info
- trq_sel_fmap_89_field_info[] = {
- {"TRQ_SEL_FMAP_89_RSVD_1",
- TRQ_SEL_FMAP_89_RSVD_1_MASK},
- {"TRQ_SEL_FMAP_89_QID_MAX",
- TRQ_SEL_FMAP_89_QID_MAX_MASK},
- {"TRQ_SEL_FMAP_89_QID_BASE",
- TRQ_SEL_FMAP_89_QID_BASE_MASK},
-};
-
-
-static struct regfield_info
- trq_sel_fmap_8a_field_info[] = {
- {"TRQ_SEL_FMAP_8A_RSVD_1",
- TRQ_SEL_FMAP_8A_RSVD_1_MASK},
- {"TRQ_SEL_FMAP_8A_QID_MAX",
- TRQ_SEL_FMAP_8A_QID_MAX_MASK},
- {"TRQ_SEL_FMAP_8A_QID_BASE",
- TRQ_SEL_FMAP_8A_QID_BASE_MASK},
-};
-
-
-static struct regfield_info
- trq_sel_fmap_8b_field_info[] = {
- {"TRQ_SEL_FMAP_8B_RSVD_1",
- TRQ_SEL_FMAP_8B_RSVD_1_MASK},
- {"TRQ_SEL_FMAP_8B_QID_MAX",
- TRQ_SEL_FMAP_8B_QID_MAX_MASK},
- {"TRQ_SEL_FMAP_8B_QID_BASE",
- TRQ_SEL_FMAP_8B_QID_BASE_MASK},
-};
-
-
-static struct regfield_info
- trq_sel_fmap_8c_field_info[] = {
- {"TRQ_SEL_FMAP_8C_RSVD_1",
- TRQ_SEL_FMAP_8C_RSVD_1_MASK},
- {"TRQ_SEL_FMAP_8C_QID_MAX",
- TRQ_SEL_FMAP_8C_QID_MAX_MASK},
- {"TRQ_SEL_FMAP_8C_QID_BASE",
- TRQ_SEL_FMAP_8C_QID_BASE_MASK},
-};
-
-
-static struct regfield_info
- trq_sel_fmap_8d_field_info[] = {
- {"TRQ_SEL_FMAP_8D_RSVD_1",
- TRQ_SEL_FMAP_8D_RSVD_1_MASK},
- {"TRQ_SEL_FMAP_8D_QID_MAX",
- TRQ_SEL_FMAP_8D_QID_MAX_MASK},
- {"TRQ_SEL_FMAP_8D_QID_BASE",
- TRQ_SEL_FMAP_8D_QID_BASE_MASK},
-};
-
-
-static struct regfield_info
- trq_sel_fmap_8e_field_info[] = {
- {"TRQ_SEL_FMAP_8E_RSVD_1",
- TRQ_SEL_FMAP_8E_RSVD_1_MASK},
- {"TRQ_SEL_FMAP_8E_QID_MAX",
- TRQ_SEL_FMAP_8E_QID_MAX_MASK},
- {"TRQ_SEL_FMAP_8E_QID_BASE",
- TRQ_SEL_FMAP_8E_QID_BASE_MASK},
-};
-
-
-static struct regfield_info
- trq_sel_fmap_8f_field_info[] = {
- {"TRQ_SEL_FMAP_8F_RSVD_1",
- TRQ_SEL_FMAP_8F_RSVD_1_MASK},
- {"TRQ_SEL_FMAP_8F_QID_MAX",
- TRQ_SEL_FMAP_8F_QID_MAX_MASK},
- {"TRQ_SEL_FMAP_8F_QID_BASE",
- TRQ_SEL_FMAP_8F_QID_BASE_MASK},
-};
-
-
-static struct regfield_info
- trq_sel_fmap_90_field_info[] = {
- {"TRQ_SEL_FMAP_90_RSVD_1",
- TRQ_SEL_FMAP_90_RSVD_1_MASK},
- {"TRQ_SEL_FMAP_90_QID_MAX",
- TRQ_SEL_FMAP_90_QID_MAX_MASK},
- {"TRQ_SEL_FMAP_90_QID_BASE",
- TRQ_SEL_FMAP_90_QID_BASE_MASK},
-};
-
-
-static struct regfield_info
- trq_sel_fmap_91_field_info[] = {
- {"TRQ_SEL_FMAP_91_RSVD_1",
- TRQ_SEL_FMAP_91_RSVD_1_MASK},
- {"TRQ_SEL_FMAP_91_QID_MAX",
- TRQ_SEL_FMAP_91_QID_MAX_MASK},
- {"TRQ_SEL_FMAP_91_QID_BASE",
- TRQ_SEL_FMAP_91_QID_BASE_MASK},
-};
-
-
-static struct regfield_info
- trq_sel_fmap_92_field_info[] = {
- {"TRQ_SEL_FMAP_92_RSVD_1",
- TRQ_SEL_FMAP_92_RSVD_1_MASK},
- {"TRQ_SEL_FMAP_92_QID_MAX",
- TRQ_SEL_FMAP_92_QID_MAX_MASK},
- {"TRQ_SEL_FMAP_92_QID_BASE",
- TRQ_SEL_FMAP_92_QID_BASE_MASK},
-};
-
-
-static struct regfield_info
- trq_sel_fmap_93_field_info[] = {
- {"TRQ_SEL_FMAP_93_RSVD_1",
- TRQ_SEL_FMAP_93_RSVD_1_MASK},
- {"TRQ_SEL_FMAP_93_QID_MAX",
- TRQ_SEL_FMAP_93_QID_MAX_MASK},
- {"TRQ_SEL_FMAP_93_QID_BASE",
- TRQ_SEL_FMAP_93_QID_BASE_MASK},
-};
-
-
-static struct regfield_info
- trq_sel_fmap_94_field_info[] = {
- {"TRQ_SEL_FMAP_94_RSVD_1",
- TRQ_SEL_FMAP_94_RSVD_1_MASK},
- {"TRQ_SEL_FMAP_94_QID_MAX",
- TRQ_SEL_FMAP_94_QID_MAX_MASK},
- {"TRQ_SEL_FMAP_94_QID_BASE",
- TRQ_SEL_FMAP_94_QID_BASE_MASK},
-};
-
-
-static struct regfield_info
- trq_sel_fmap_95_field_info[] = {
- {"TRQ_SEL_FMAP_95_RSVD_1",
- TRQ_SEL_FMAP_95_RSVD_1_MASK},
- {"TRQ_SEL_FMAP_95_QID_MAX",
- TRQ_SEL_FMAP_95_QID_MAX_MASK},
- {"TRQ_SEL_FMAP_95_QID_BASE",
- TRQ_SEL_FMAP_95_QID_BASE_MASK},
-};
-
-
-static struct regfield_info
- trq_sel_fmap_96_field_info[] = {
- {"TRQ_SEL_FMAP_96_RSVD_1",
- TRQ_SEL_FMAP_96_RSVD_1_MASK},
- {"TRQ_SEL_FMAP_96_QID_MAX",
- TRQ_SEL_FMAP_96_QID_MAX_MASK},
- {"TRQ_SEL_FMAP_96_QID_BASE",
- TRQ_SEL_FMAP_96_QID_BASE_MASK},
-};
-
-
-static struct regfield_info
- trq_sel_fmap_97_field_info[] = {
- {"TRQ_SEL_FMAP_97_RSVD_1",
- TRQ_SEL_FMAP_97_RSVD_1_MASK},
- {"TRQ_SEL_FMAP_97_QID_MAX",
- TRQ_SEL_FMAP_97_QID_MAX_MASK},
- {"TRQ_SEL_FMAP_97_QID_BASE",
- TRQ_SEL_FMAP_97_QID_BASE_MASK},
-};
-
-
-static struct regfield_info
- trq_sel_fmap_98_field_info[] = {
- {"TRQ_SEL_FMAP_98_RSVD_1",
- TRQ_SEL_FMAP_98_RSVD_1_MASK},
- {"TRQ_SEL_FMAP_98_QID_MAX",
- TRQ_SEL_FMAP_98_QID_MAX_MASK},
- {"TRQ_SEL_FMAP_98_QID_BASE",
- TRQ_SEL_FMAP_98_QID_BASE_MASK},
-};
-
-
-static struct regfield_info
- trq_sel_fmap_99_field_info[] = {
- {"TRQ_SEL_FMAP_99_RSVD_1",
- TRQ_SEL_FMAP_99_RSVD_1_MASK},
- {"TRQ_SEL_FMAP_99_QID_MAX",
- TRQ_SEL_FMAP_99_QID_MAX_MASK},
- {"TRQ_SEL_FMAP_99_QID_BASE",
- TRQ_SEL_FMAP_99_QID_BASE_MASK},
-};
-
-
-static struct regfield_info
- trq_sel_fmap_9a_field_info[] = {
- {"TRQ_SEL_FMAP_9A_RSVD_1",
- TRQ_SEL_FMAP_9A_RSVD_1_MASK},
- {"TRQ_SEL_FMAP_9A_QID_MAX",
- TRQ_SEL_FMAP_9A_QID_MAX_MASK},
- {"TRQ_SEL_FMAP_9A_QID_BASE",
- TRQ_SEL_FMAP_9A_QID_BASE_MASK},
-};
-
-
-static struct regfield_info
- trq_sel_fmap_9b_field_info[] = {
- {"TRQ_SEL_FMAP_9B_RSVD_1",
- TRQ_SEL_FMAP_9B_RSVD_1_MASK},
- {"TRQ_SEL_FMAP_9B_QID_MAX",
- TRQ_SEL_FMAP_9B_QID_MAX_MASK},
- {"TRQ_SEL_FMAP_9B_QID_BASE",
- TRQ_SEL_FMAP_9B_QID_BASE_MASK},
-};
-
-
-static struct regfield_info
- trq_sel_fmap_9c_field_info[] = {
- {"TRQ_SEL_FMAP_9C_RSVD_1",
- TRQ_SEL_FMAP_9C_RSVD_1_MASK},
- {"TRQ_SEL_FMAP_9C_QID_MAX",
- TRQ_SEL_FMAP_9C_QID_MAX_MASK},
- {"TRQ_SEL_FMAP_9C_QID_BASE",
- TRQ_SEL_FMAP_9C_QID_BASE_MASK},
-};
-
-
-static struct regfield_info
- trq_sel_fmap_9d_field_info[] = {
- {"TRQ_SEL_FMAP_9D_RSVD_1",
- TRQ_SEL_FMAP_9D_RSVD_1_MASK},
- {"TRQ_SEL_FMAP_9D_QID_MAX",
- TRQ_SEL_FMAP_9D_QID_MAX_MASK},
- {"TRQ_SEL_FMAP_9D_QID_BASE",
- TRQ_SEL_FMAP_9D_QID_BASE_MASK},
-};
-
-
-static struct regfield_info
- trq_sel_fmap_9e_field_info[] = {
- {"TRQ_SEL_FMAP_9E_RSVD_1",
- TRQ_SEL_FMAP_9E_RSVD_1_MASK},
- {"TRQ_SEL_FMAP_9E_QID_MAX",
- TRQ_SEL_FMAP_9E_QID_MAX_MASK},
- {"TRQ_SEL_FMAP_9E_QID_BASE",
- TRQ_SEL_FMAP_9E_QID_BASE_MASK},
-};
-
-
-static struct regfield_info
- trq_sel_fmap_9f_field_info[] = {
- {"TRQ_SEL_FMAP_9F_RSVD_1",
- TRQ_SEL_FMAP_9F_RSVD_1_MASK},
- {"TRQ_SEL_FMAP_9F_QID_MAX",
- TRQ_SEL_FMAP_9F_QID_MAX_MASK},
- {"TRQ_SEL_FMAP_9F_QID_BASE",
- TRQ_SEL_FMAP_9F_QID_BASE_MASK},
-};
-
-
-static struct regfield_info
- trq_sel_fmap_a0_field_info[] = {
- {"TRQ_SEL_FMAP_A0_RSVD_1",
- TRQ_SEL_FMAP_A0_RSVD_1_MASK},
- {"TRQ_SEL_FMAP_A0_QID_MAX",
- TRQ_SEL_FMAP_A0_QID_MAX_MASK},
- {"TRQ_SEL_FMAP_A0_QID_BASE",
- TRQ_SEL_FMAP_A0_QID_BASE_MASK},
-};
-
-
-static struct regfield_info
- trq_sel_fmap_a1_field_info[] = {
- {"TRQ_SEL_FMAP_A1_RSVD_1",
- TRQ_SEL_FMAP_A1_RSVD_1_MASK},
- {"TRQ_SEL_FMAP_A1_QID_MAX",
- TRQ_SEL_FMAP_A1_QID_MAX_MASK},
- {"TRQ_SEL_FMAP_A1_QID_BASE",
- TRQ_SEL_FMAP_A1_QID_BASE_MASK},
-};
-
-
-static struct regfield_info
- trq_sel_fmap_a2_field_info[] = {
- {"TRQ_SEL_FMAP_A2_RSVD_1",
- TRQ_SEL_FMAP_A2_RSVD_1_MASK},
- {"TRQ_SEL_FMAP_A2_QID_MAX",
- TRQ_SEL_FMAP_A2_QID_MAX_MASK},
- {"TRQ_SEL_FMAP_A2_QID_BASE",
- TRQ_SEL_FMAP_A2_QID_BASE_MASK},
-};
-
-
-static struct regfield_info
- trq_sel_fmap_a3_field_info[] = {
- {"TRQ_SEL_FMAP_A3_RSVD_1",
- TRQ_SEL_FMAP_A3_RSVD_1_MASK},
- {"TRQ_SEL_FMAP_A3_QID_MAX",
- TRQ_SEL_FMAP_A3_QID_MAX_MASK},
- {"TRQ_SEL_FMAP_A3_QID_BASE",
- TRQ_SEL_FMAP_A3_QID_BASE_MASK},
-};
-
-
-static struct regfield_info
- trq_sel_fmap_a4_field_info[] = {
- {"TRQ_SEL_FMAP_A4_RSVD_1",
- TRQ_SEL_FMAP_A4_RSVD_1_MASK},
- {"TRQ_SEL_FMAP_A4_QID_MAX",
- TRQ_SEL_FMAP_A4_QID_MAX_MASK},
- {"TRQ_SEL_FMAP_A4_QID_BASE",
- TRQ_SEL_FMAP_A4_QID_BASE_MASK},
-};
-
-
-static struct regfield_info
- trq_sel_fmap_a5_field_info[] = {
- {"TRQ_SEL_FMAP_A5_RSVD_1",
- TRQ_SEL_FMAP_A5_RSVD_1_MASK},
- {"TRQ_SEL_FMAP_A5_QID_MAX",
- TRQ_SEL_FMAP_A5_QID_MAX_MASK},
- {"TRQ_SEL_FMAP_A5_QID_BASE",
- TRQ_SEL_FMAP_A5_QID_BASE_MASK},
-};
-
-
-static struct regfield_info
- trq_sel_fmap_a6_field_info[] = {
- {"TRQ_SEL_FMAP_A6_RSVD_1",
- TRQ_SEL_FMAP_A6_RSVD_1_MASK},
- {"TRQ_SEL_FMAP_A6_QID_MAX",
- TRQ_SEL_FMAP_A6_QID_MAX_MASK},
- {"TRQ_SEL_FMAP_A6_QID_BASE",
- TRQ_SEL_FMAP_A6_QID_BASE_MASK},
-};
-
-
-static struct regfield_info
- trq_sel_fmap_a7_field_info[] = {
- {"TRQ_SEL_FMAP_A7_RSVD_1",
- TRQ_SEL_FMAP_A7_RSVD_1_MASK},
- {"TRQ_SEL_FMAP_A7_QID_MAX",
- TRQ_SEL_FMAP_A7_QID_MAX_MASK},
- {"TRQ_SEL_FMAP_A7_QID_BASE",
- TRQ_SEL_FMAP_A7_QID_BASE_MASK},
-};
-
-
-static struct regfield_info
- trq_sel_fmap_a8_field_info[] = {
- {"TRQ_SEL_FMAP_A8_RSVD_1",
- TRQ_SEL_FMAP_A8_RSVD_1_MASK},
- {"TRQ_SEL_FMAP_A8_QID_MAX",
- TRQ_SEL_FMAP_A8_QID_MAX_MASK},
- {"TRQ_SEL_FMAP_A8_QID_BASE",
- TRQ_SEL_FMAP_A8_QID_BASE_MASK},
-};
-
-
-static struct regfield_info
- trq_sel_fmap_a9_field_info[] = {
- {"TRQ_SEL_FMAP_A9_RSVD_1",
- TRQ_SEL_FMAP_A9_RSVD_1_MASK},
- {"TRQ_SEL_FMAP_A9_QID_MAX",
- TRQ_SEL_FMAP_A9_QID_MAX_MASK},
- {"TRQ_SEL_FMAP_A9_QID_BASE",
- TRQ_SEL_FMAP_A9_QID_BASE_MASK},
-};
-
-
-static struct regfield_info
- trq_sel_fmap_aa_field_info[] = {
- {"TRQ_SEL_FMAP_AA_RSVD_1",
- TRQ_SEL_FMAP_AA_RSVD_1_MASK},
- {"TRQ_SEL_FMAP_AA_QID_MAX",
- TRQ_SEL_FMAP_AA_QID_MAX_MASK},
- {"TRQ_SEL_FMAP_AA_QID_BASE",
- TRQ_SEL_FMAP_AA_QID_BASE_MASK},
-};
-
-
-static struct regfield_info
- trq_sel_fmap_ab_field_info[] = {
- {"TRQ_SEL_FMAP_AB_RSVD_1",
- TRQ_SEL_FMAP_AB_RSVD_1_MASK},
- {"TRQ_SEL_FMAP_AB_QID_MAX",
- TRQ_SEL_FMAP_AB_QID_MAX_MASK},
- {"TRQ_SEL_FMAP_AB_QID_BASE",
- TRQ_SEL_FMAP_AB_QID_BASE_MASK},
-};
-
-
-static struct regfield_info
- trq_sel_fmap_ac_field_info[] = {
- {"TRQ_SEL_FMAP_AC_RSVD_1",
- TRQ_SEL_FMAP_AC_RSVD_1_MASK},
- {"TRQ_SEL_FMAP_AC_QID_MAX",
- TRQ_SEL_FMAP_AC_QID_MAX_MASK},
- {"TRQ_SEL_FMAP_AC_QID_BASE",
- TRQ_SEL_FMAP_AC_QID_BASE_MASK},
-};
-
-
-static struct regfield_info
- trq_sel_fmap_ad_field_info[] = {
- {"TRQ_SEL_FMAP_AD_RSVD_1",
- TRQ_SEL_FMAP_AD_RSVD_1_MASK},
- {"TRQ_SEL_FMAP_AD_QID_MAX",
- TRQ_SEL_FMAP_AD_QID_MAX_MASK},
- {"TRQ_SEL_FMAP_AD_QID_BASE",
- TRQ_SEL_FMAP_AD_QID_BASE_MASK},
-};
-
-
-static struct regfield_info
- trq_sel_fmap_ae_field_info[] = {
- {"TRQ_SEL_FMAP_AE_RSVD_1",
- TRQ_SEL_FMAP_AE_RSVD_1_MASK},
- {"TRQ_SEL_FMAP_AE_QID_MAX",
- TRQ_SEL_FMAP_AE_QID_MAX_MASK},
- {"TRQ_SEL_FMAP_AE_QID_BASE",
- TRQ_SEL_FMAP_AE_QID_BASE_MASK},
-};
-
-
-static struct regfield_info
- trq_sel_fmap_af_field_info[] = {
- {"TRQ_SEL_FMAP_AF_RSVD_1",
- TRQ_SEL_FMAP_AF_RSVD_1_MASK},
- {"TRQ_SEL_FMAP_AF_QID_MAX",
- TRQ_SEL_FMAP_AF_QID_MAX_MASK},
- {"TRQ_SEL_FMAP_AF_QID_BASE",
- TRQ_SEL_FMAP_AF_QID_BASE_MASK},
-};
-
-
-static struct regfield_info
- trq_sel_fmap_b0_field_info[] = {
- {"TRQ_SEL_FMAP_B0_RSVD_1",
- TRQ_SEL_FMAP_B0_RSVD_1_MASK},
- {"TRQ_SEL_FMAP_B0_QID_MAX",
- TRQ_SEL_FMAP_B0_QID_MAX_MASK},
- {"TRQ_SEL_FMAP_B0_QID_BASE",
- TRQ_SEL_FMAP_B0_QID_BASE_MASK},
-};
-
-
-static struct regfield_info
- trq_sel_fmap_b1_field_info[] = {
- {"TRQ_SEL_FMAP_B1_RSVD_1",
- TRQ_SEL_FMAP_B1_RSVD_1_MASK},
- {"TRQ_SEL_FMAP_B1_QID_MAX",
- TRQ_SEL_FMAP_B1_QID_MAX_MASK},
- {"TRQ_SEL_FMAP_B1_QID_BASE",
- TRQ_SEL_FMAP_B1_QID_BASE_MASK},
-};
-
-
-static struct regfield_info
- trq_sel_fmap_b2_field_info[] = {
- {"TRQ_SEL_FMAP_B2_RSVD_1",
- TRQ_SEL_FMAP_B2_RSVD_1_MASK},
- {"TRQ_SEL_FMAP_B2_QID_MAX",
- TRQ_SEL_FMAP_B2_QID_MAX_MASK},
- {"TRQ_SEL_FMAP_B2_QID_BASE",
- TRQ_SEL_FMAP_B2_QID_BASE_MASK},
-};
-
-
-static struct regfield_info
- trq_sel_fmap_b3_field_info[] = {
- {"TRQ_SEL_FMAP_B3_RSVD_1",
- TRQ_SEL_FMAP_B3_RSVD_1_MASK},
- {"TRQ_SEL_FMAP_B3_QID_MAX",
- TRQ_SEL_FMAP_B3_QID_MAX_MASK},
- {"TRQ_SEL_FMAP_B3_QID_BASE",
- TRQ_SEL_FMAP_B3_QID_BASE_MASK},
-};
-
-
-static struct regfield_info
- trq_sel_fmap_b4_field_info[] = {
- {"TRQ_SEL_FMAP_B4_RSVD_1",
- TRQ_SEL_FMAP_B4_RSVD_1_MASK},
- {"TRQ_SEL_FMAP_B4_QID_MAX",
- TRQ_SEL_FMAP_B4_QID_MAX_MASK},
- {"TRQ_SEL_FMAP_B4_QID_BASE",
- TRQ_SEL_FMAP_B4_QID_BASE_MASK},
-};
-
-
-static struct regfield_info
- trq_sel_fmap_b5_field_info[] = {
- {"TRQ_SEL_FMAP_B5_RSVD_1",
- TRQ_SEL_FMAP_B5_RSVD_1_MASK},
- {"TRQ_SEL_FMAP_B5_QID_MAX",
- TRQ_SEL_FMAP_B5_QID_MAX_MASK},
- {"TRQ_SEL_FMAP_B5_QID_BASE",
- TRQ_SEL_FMAP_B5_QID_BASE_MASK},
-};
-
-
-static struct regfield_info
- trq_sel_fmap_b6_field_info[] = {
- {"TRQ_SEL_FMAP_B6_RSVD_1",
- TRQ_SEL_FMAP_B6_RSVD_1_MASK},
- {"TRQ_SEL_FMAP_B6_QID_MAX",
- TRQ_SEL_FMAP_B6_QID_MAX_MASK},
- {"TRQ_SEL_FMAP_B6_QID_BASE",
- TRQ_SEL_FMAP_B6_QID_BASE_MASK},
-};
-
-
-static struct regfield_info
- trq_sel_fmap_b7_field_info[] = {
- {"TRQ_SEL_FMAP_B7_RSVD_1",
- TRQ_SEL_FMAP_B7_RSVD_1_MASK},
- {"TRQ_SEL_FMAP_B7_QID_MAX",
- TRQ_SEL_FMAP_B7_QID_MAX_MASK},
- {"TRQ_SEL_FMAP_B7_QID_BASE",
- TRQ_SEL_FMAP_B7_QID_BASE_MASK},
-};
-
-
-static struct regfield_info
- trq_sel_fmap_b8_field_info[] = {
- {"TRQ_SEL_FMAP_B8_RSVD_1",
- TRQ_SEL_FMAP_B8_RSVD_1_MASK},
- {"TRQ_SEL_FMAP_B8_QID_MAX",
- TRQ_SEL_FMAP_B8_QID_MAX_MASK},
- {"TRQ_SEL_FMAP_B8_QID_BASE",
- TRQ_SEL_FMAP_B8_QID_BASE_MASK},
-};
-
-
-static struct regfield_info
- trq_sel_fmap_b9_field_info[] = {
- {"TRQ_SEL_FMAP_B9_RSVD_1",
- TRQ_SEL_FMAP_B9_RSVD_1_MASK},
- {"TRQ_SEL_FMAP_B9_QID_MAX",
- TRQ_SEL_FMAP_B9_QID_MAX_MASK},
- {"TRQ_SEL_FMAP_B9_QID_BASE",
- TRQ_SEL_FMAP_B9_QID_BASE_MASK},
-};
-
-
-static struct regfield_info
- trq_sel_fmap_ba_field_info[] = {
- {"TRQ_SEL_FMAP_BA_RSVD_1",
- TRQ_SEL_FMAP_BA_RSVD_1_MASK},
- {"TRQ_SEL_FMAP_BA_QID_MAX",
- TRQ_SEL_FMAP_BA_QID_MAX_MASK},
- {"TRQ_SEL_FMAP_BA_QID_BASE",
- TRQ_SEL_FMAP_BA_QID_BASE_MASK},
-};
-
-
-static struct regfield_info
- trq_sel_fmap_bb_field_info[] = {
- {"TRQ_SEL_FMAP_BB_RSVD_1",
- TRQ_SEL_FMAP_BB_RSVD_1_MASK},
- {"TRQ_SEL_FMAP_BB_QID_MAX",
- TRQ_SEL_FMAP_BB_QID_MAX_MASK},
- {"TRQ_SEL_FMAP_BB_QID_BASE",
- TRQ_SEL_FMAP_BB_QID_BASE_MASK},
-};
-
-
-static struct regfield_info
- trq_sel_fmap_bc_field_info[] = {
- {"TRQ_SEL_FMAP_BC_RSVD_1",
- TRQ_SEL_FMAP_BC_RSVD_1_MASK},
- {"TRQ_SEL_FMAP_BC_QID_MAX",
- TRQ_SEL_FMAP_BC_QID_MAX_MASK},
- {"TRQ_SEL_FMAP_BC_QID_BASE",
- TRQ_SEL_FMAP_BC_QID_BASE_MASK},
-};
-
-
-static struct regfield_info
- trq_sel_fmap_bd_field_info[] = {
- {"TRQ_SEL_FMAP_BD_RSVD_1",
- TRQ_SEL_FMAP_BD_RSVD_1_MASK},
- {"TRQ_SEL_FMAP_BD_QID_MAX",
- TRQ_SEL_FMAP_BD_QID_MAX_MASK},
- {"TRQ_SEL_FMAP_BD_QID_BASE",
- TRQ_SEL_FMAP_BD_QID_BASE_MASK},
-};
-
-
-static struct regfield_info
- trq_sel_fmap_be_field_info[] = {
- {"TRQ_SEL_FMAP_BE_RSVD_1",
- TRQ_SEL_FMAP_BE_RSVD_1_MASK},
- {"TRQ_SEL_FMAP_BE_QID_MAX",
- TRQ_SEL_FMAP_BE_QID_MAX_MASK},
- {"TRQ_SEL_FMAP_BE_QID_BASE",
- TRQ_SEL_FMAP_BE_QID_BASE_MASK},
-};
-
-
-static struct regfield_info
- trq_sel_fmap_bf_field_info[] = {
- {"TRQ_SEL_FMAP_BF_RSVD_1",
- TRQ_SEL_FMAP_BF_RSVD_1_MASK},
- {"TRQ_SEL_FMAP_BF_QID_MAX",
- TRQ_SEL_FMAP_BF_QID_MAX_MASK},
- {"TRQ_SEL_FMAP_BF_QID_BASE",
- TRQ_SEL_FMAP_BF_QID_BASE_MASK},
-};
-
-
-static struct regfield_info
- trq_sel_fmap_c0_field_info[] = {
- {"TRQ_SEL_FMAP_C0_RSVD_1",
- TRQ_SEL_FMAP_C0_RSVD_1_MASK},
- {"TRQ_SEL_FMAP_C0_QID_MAX",
- TRQ_SEL_FMAP_C0_QID_MAX_MASK},
- {"TRQ_SEL_FMAP_C0_QID_BASE",
- TRQ_SEL_FMAP_C0_QID_BASE_MASK},
-};
-
-
-static struct regfield_info
- trq_sel_fmap_c1_field_info[] = {
- {"TRQ_SEL_FMAP_C1_RSVD_1",
- TRQ_SEL_FMAP_C1_RSVD_1_MASK},
- {"TRQ_SEL_FMAP_C1_QID_MAX",
- TRQ_SEL_FMAP_C1_QID_MAX_MASK},
- {"TRQ_SEL_FMAP_C1_QID_BASE",
- TRQ_SEL_FMAP_C1_QID_BASE_MASK},
-};
-
-
-static struct regfield_info
- trq_sel_fmap_c2_field_info[] = {
- {"TRQ_SEL_FMAP_C2_RSVD_1",
- TRQ_SEL_FMAP_C2_RSVD_1_MASK},
- {"TRQ_SEL_FMAP_C2_QID_MAX",
- TRQ_SEL_FMAP_C2_QID_MAX_MASK},
- {"TRQ_SEL_FMAP_C2_QID_BASE",
- TRQ_SEL_FMAP_C2_QID_BASE_MASK},
-};
-
-
-static struct regfield_info
- trq_sel_fmap_c3_field_info[] = {
- {"TRQ_SEL_FMAP_C3_RSVD_1",
- TRQ_SEL_FMAP_C3_RSVD_1_MASK},
- {"TRQ_SEL_FMAP_C3_QID_MAX",
- TRQ_SEL_FMAP_C3_QID_MAX_MASK},
- {"TRQ_SEL_FMAP_C3_QID_BASE",
- TRQ_SEL_FMAP_C3_QID_BASE_MASK},
-};
-
-
-static struct regfield_info
- trq_sel_fmap_c4_field_info[] = {
- {"TRQ_SEL_FMAP_C4_RSVD_1",
- TRQ_SEL_FMAP_C4_RSVD_1_MASK},
- {"TRQ_SEL_FMAP_C4_QID_MAX",
- TRQ_SEL_FMAP_C4_QID_MAX_MASK},
- {"TRQ_SEL_FMAP_C4_QID_BASE",
- TRQ_SEL_FMAP_C4_QID_BASE_MASK},
-};
-
-
-static struct regfield_info
- trq_sel_fmap_c5_field_info[] = {
- {"TRQ_SEL_FMAP_C5_RSVD_1",
- TRQ_SEL_FMAP_C5_RSVD_1_MASK},
- {"TRQ_SEL_FMAP_C5_QID_MAX",
- TRQ_SEL_FMAP_C5_QID_MAX_MASK},
- {"TRQ_SEL_FMAP_C5_QID_BASE",
- TRQ_SEL_FMAP_C5_QID_BASE_MASK},
-};
-
-
-static struct regfield_info
- trq_sel_fmap_c6_field_info[] = {
- {"TRQ_SEL_FMAP_C6_RSVD_1",
- TRQ_SEL_FMAP_C6_RSVD_1_MASK},
- {"TRQ_SEL_FMAP_C6_QID_MAX",
- TRQ_SEL_FMAP_C6_QID_MAX_MASK},
- {"TRQ_SEL_FMAP_C6_QID_BASE",
- TRQ_SEL_FMAP_C6_QID_BASE_MASK},
-};
-
-
-static struct regfield_info
- trq_sel_fmap_c7_field_info[] = {
- {"TRQ_SEL_FMAP_C7_RSVD_1",
- TRQ_SEL_FMAP_C7_RSVD_1_MASK},
- {"TRQ_SEL_FMAP_C7_QID_MAX",
- TRQ_SEL_FMAP_C7_QID_MAX_MASK},
- {"TRQ_SEL_FMAP_C7_QID_BASE",
- TRQ_SEL_FMAP_C7_QID_BASE_MASK},
-};
-
-
-static struct regfield_info
- trq_sel_fmap_c8_field_info[] = {
- {"TRQ_SEL_FMAP_C8_RSVD_1",
- TRQ_SEL_FMAP_C8_RSVD_1_MASK},
- {"TRQ_SEL_FMAP_C8_QID_MAX",
- TRQ_SEL_FMAP_C8_QID_MAX_MASK},
- {"TRQ_SEL_FMAP_C8_QID_BASE",
- TRQ_SEL_FMAP_C8_QID_BASE_MASK},
-};
-
-
-static struct regfield_info
- trq_sel_fmap_c9_field_info[] = {
- {"TRQ_SEL_FMAP_C9_RSVD_1",
- TRQ_SEL_FMAP_C9_RSVD_1_MASK},
- {"TRQ_SEL_FMAP_C9_QID_MAX",
- TRQ_SEL_FMAP_C9_QID_MAX_MASK},
- {"TRQ_SEL_FMAP_C9_QID_BASE",
- TRQ_SEL_FMAP_C9_QID_BASE_MASK},
-};
-
-
-static struct regfield_info
- trq_sel_fmap_ca_field_info[] = {
- {"TRQ_SEL_FMAP_CA_RSVD_1",
- TRQ_SEL_FMAP_CA_RSVD_1_MASK},
- {"TRQ_SEL_FMAP_CA_QID_MAX",
- TRQ_SEL_FMAP_CA_QID_MAX_MASK},
- {"TRQ_SEL_FMAP_CA_QID_BASE",
- TRQ_SEL_FMAP_CA_QID_BASE_MASK},
-};
-
-
-static struct regfield_info
- trq_sel_fmap_cb_field_info[] = {
- {"TRQ_SEL_FMAP_CB_RSVD_1",
- TRQ_SEL_FMAP_CB_RSVD_1_MASK},
- {"TRQ_SEL_FMAP_CB_QID_MAX",
- TRQ_SEL_FMAP_CB_QID_MAX_MASK},
- {"TRQ_SEL_FMAP_CB_QID_BASE",
- TRQ_SEL_FMAP_CB_QID_BASE_MASK},
-};
-
-
-static struct regfield_info
- trq_sel_fmap_cc_field_info[] = {
- {"TRQ_SEL_FMAP_CC_RSVD_1",
- TRQ_SEL_FMAP_CC_RSVD_1_MASK},
- {"TRQ_SEL_FMAP_CC_QID_MAX",
- TRQ_SEL_FMAP_CC_QID_MAX_MASK},
- {"TRQ_SEL_FMAP_CC_QID_BASE",
- TRQ_SEL_FMAP_CC_QID_BASE_MASK},
-};
-
-
-static struct regfield_info
- trq_sel_fmap_cd_field_info[] = {
- {"TRQ_SEL_FMAP_CD_RSVD_1",
- TRQ_SEL_FMAP_CD_RSVD_1_MASK},
- {"TRQ_SEL_FMAP_CD_QID_MAX",
- TRQ_SEL_FMAP_CD_QID_MAX_MASK},
- {"TRQ_SEL_FMAP_CD_QID_BASE",
- TRQ_SEL_FMAP_CD_QID_BASE_MASK},
-};
-
-
-static struct regfield_info
- trq_sel_fmap_ce_field_info[] = {
- {"TRQ_SEL_FMAP_CE_RSVD_1",
- TRQ_SEL_FMAP_CE_RSVD_1_MASK},
- {"TRQ_SEL_FMAP_CE_QID_MAX",
- TRQ_SEL_FMAP_CE_QID_MAX_MASK},
- {"TRQ_SEL_FMAP_CE_QID_BASE",
- TRQ_SEL_FMAP_CE_QID_BASE_MASK},
-};
-
-
-static struct regfield_info
- trq_sel_fmap_cf_field_info[] = {
- {"TRQ_SEL_FMAP_CF_RSVD_1",
- TRQ_SEL_FMAP_CF_RSVD_1_MASK},
- {"TRQ_SEL_FMAP_CF_QID_MAX",
- TRQ_SEL_FMAP_CF_QID_MAX_MASK},
- {"TRQ_SEL_FMAP_CF_QID_BASE",
- TRQ_SEL_FMAP_CF_QID_BASE_MASK},
-};
-
-
-static struct regfield_info
- trq_sel_fmap_d0_field_info[] = {
- {"TRQ_SEL_FMAP_D0_RSVD_1",
- TRQ_SEL_FMAP_D0_RSVD_1_MASK},
- {"TRQ_SEL_FMAP_D0_QID_MAX",
- TRQ_SEL_FMAP_D0_QID_MAX_MASK},
- {"TRQ_SEL_FMAP_D0_QID_BASE",
- TRQ_SEL_FMAP_D0_QID_BASE_MASK},
-};
-
-
-static struct regfield_info
- trq_sel_fmap_d1_field_info[] = {
- {"TRQ_SEL_FMAP_D1_RSVD_1",
- TRQ_SEL_FMAP_D1_RSVD_1_MASK},
- {"TRQ_SEL_FMAP_D1_QID_MAX",
- TRQ_SEL_FMAP_D1_QID_MAX_MASK},
- {"TRQ_SEL_FMAP_D1_QID_BASE",
- TRQ_SEL_FMAP_D1_QID_BASE_MASK},
-};
-
-
-static struct regfield_info
- trq_sel_fmap_d2_field_info[] = {
- {"TRQ_SEL_FMAP_D2_RSVD_1",
- TRQ_SEL_FMAP_D2_RSVD_1_MASK},
- {"TRQ_SEL_FMAP_D2_QID_MAX",
- TRQ_SEL_FMAP_D2_QID_MAX_MASK},
- {"TRQ_SEL_FMAP_D2_QID_BASE",
- TRQ_SEL_FMAP_D2_QID_BASE_MASK},
-};
-
-
-static struct regfield_info
- trq_sel_fmap_d3_field_info[] = {
- {"TRQ_SEL_FMAP_D3_RSVD_1",
- TRQ_SEL_FMAP_D3_RSVD_1_MASK},
- {"TRQ_SEL_FMAP_D3_QID_MAX",
- TRQ_SEL_FMAP_D3_QID_MAX_MASK},
- {"TRQ_SEL_FMAP_D3_QID_BASE",
- TRQ_SEL_FMAP_D3_QID_BASE_MASK},
-};
-
-
-static struct regfield_info
- trq_sel_fmap_d4_field_info[] = {
- {"TRQ_SEL_FMAP_D4_RSVD_1",
- TRQ_SEL_FMAP_D4_RSVD_1_MASK},
- {"TRQ_SEL_FMAP_D4_QID_MAX",
- TRQ_SEL_FMAP_D4_QID_MAX_MASK},
- {"TRQ_SEL_FMAP_D4_QID_BASE",
- TRQ_SEL_FMAP_D4_QID_BASE_MASK},
-};
-
-
-static struct regfield_info
- trq_sel_fmap_d5_field_info[] = {
- {"TRQ_SEL_FMAP_D5_RSVD_1",
- TRQ_SEL_FMAP_D5_RSVD_1_MASK},
- {"TRQ_SEL_FMAP_D5_QID_MAX",
- TRQ_SEL_FMAP_D5_QID_MAX_MASK},
- {"TRQ_SEL_FMAP_D5_QID_BASE",
- TRQ_SEL_FMAP_D5_QID_BASE_MASK},
-};
-
-
-static struct regfield_info
- trq_sel_fmap_d6_field_info[] = {
- {"TRQ_SEL_FMAP_D6_RSVD_1",
- TRQ_SEL_FMAP_D6_RSVD_1_MASK},
- {"TRQ_SEL_FMAP_D6_QID_MAX",
- TRQ_SEL_FMAP_D6_QID_MAX_MASK},
- {"TRQ_SEL_FMAP_D6_QID_BASE",
- TRQ_SEL_FMAP_D6_QID_BASE_MASK},
-};
-
-
-static struct regfield_info
- trq_sel_fmap_d7_field_info[] = {
- {"TRQ_SEL_FMAP_D7_RSVD_1",
- TRQ_SEL_FMAP_D7_RSVD_1_MASK},
- {"TRQ_SEL_FMAP_D7_QID_MAX",
- TRQ_SEL_FMAP_D7_QID_MAX_MASK},
- {"TRQ_SEL_FMAP_D7_QID_BASE",
- TRQ_SEL_FMAP_D7_QID_BASE_MASK},
-};
-
-
-static struct regfield_info
- trq_sel_fmap_d8_field_info[] = {
- {"TRQ_SEL_FMAP_D8_RSVD_1",
- TRQ_SEL_FMAP_D8_RSVD_1_MASK},
- {"TRQ_SEL_FMAP_D8_QID_MAX",
- TRQ_SEL_FMAP_D8_QID_MAX_MASK},
- {"TRQ_SEL_FMAP_D8_QID_BASE",
- TRQ_SEL_FMAP_D8_QID_BASE_MASK},
-};
-
-
-static struct regfield_info
- trq_sel_fmap_d9_field_info[] = {
- {"TRQ_SEL_FMAP_D9_RSVD_1",
- TRQ_SEL_FMAP_D9_RSVD_1_MASK},
- {"TRQ_SEL_FMAP_D9_QID_MAX",
- TRQ_SEL_FMAP_D9_QID_MAX_MASK},
- {"TRQ_SEL_FMAP_D9_QID_BASE",
- TRQ_SEL_FMAP_D9_QID_BASE_MASK},
-};
-
-
-static struct regfield_info
- trq_sel_fmap_da_field_info[] = {
- {"TRQ_SEL_FMAP_DA_RSVD_1",
- TRQ_SEL_FMAP_DA_RSVD_1_MASK},
- {"TRQ_SEL_FMAP_DA_QID_MAX",
- TRQ_SEL_FMAP_DA_QID_MAX_MASK},
- {"TRQ_SEL_FMAP_DA_QID_BASE",
- TRQ_SEL_FMAP_DA_QID_BASE_MASK},
-};
-
-
-static struct regfield_info
- trq_sel_fmap_db_field_info[] = {
- {"TRQ_SEL_FMAP_DB_RSVD_1",
- TRQ_SEL_FMAP_DB_RSVD_1_MASK},
- {"TRQ_SEL_FMAP_DB_QID_MAX",
- TRQ_SEL_FMAP_DB_QID_MAX_MASK},
- {"TRQ_SEL_FMAP_DB_QID_BASE",
- TRQ_SEL_FMAP_DB_QID_BASE_MASK},
-};
-
-
-static struct regfield_info
- trq_sel_fmap_dc_field_info[] = {
- {"TRQ_SEL_FMAP_DC_RSVD_1",
- TRQ_SEL_FMAP_DC_RSVD_1_MASK},
- {"TRQ_SEL_FMAP_DC_QID_MAX",
- TRQ_SEL_FMAP_DC_QID_MAX_MASK},
- {"TRQ_SEL_FMAP_DC_QID_BASE",
- TRQ_SEL_FMAP_DC_QID_BASE_MASK},
-};
-
-
-static struct regfield_info
- trq_sel_fmap_dd_field_info[] = {
- {"TRQ_SEL_FMAP_DD_RSVD_1",
- TRQ_SEL_FMAP_DD_RSVD_1_MASK},
- {"TRQ_SEL_FMAP_DD_QID_MAX",
- TRQ_SEL_FMAP_DD_QID_MAX_MASK},
- {"TRQ_SEL_FMAP_DD_QID_BASE",
- TRQ_SEL_FMAP_DD_QID_BASE_MASK},
-};
-
-
-static struct regfield_info
- trq_sel_fmap_de_field_info[] = {
- {"TRQ_SEL_FMAP_DE_RSVD_1",
- TRQ_SEL_FMAP_DE_RSVD_1_MASK},
- {"TRQ_SEL_FMAP_DE_QID_MAX",
- TRQ_SEL_FMAP_DE_QID_MAX_MASK},
- {"TRQ_SEL_FMAP_DE_QID_BASE",
- TRQ_SEL_FMAP_DE_QID_BASE_MASK},
-};
-
-
-static struct regfield_info
- trq_sel_fmap_df_field_info[] = {
- {"TRQ_SEL_FMAP_DF_RSVD_1",
- TRQ_SEL_FMAP_DF_RSVD_1_MASK},
- {"TRQ_SEL_FMAP_DF_QID_MAX",
- TRQ_SEL_FMAP_DF_QID_MAX_MASK},
- {"TRQ_SEL_FMAP_DF_QID_BASE",
- TRQ_SEL_FMAP_DF_QID_BASE_MASK},
-};
-
-
-static struct regfield_info
- trq_sel_fmap_e0_field_info[] = {
- {"TRQ_SEL_FMAP_E0_RSVD_1",
- TRQ_SEL_FMAP_E0_RSVD_1_MASK},
- {"TRQ_SEL_FMAP_E0_QID_MAX",
- TRQ_SEL_FMAP_E0_QID_MAX_MASK},
- {"TRQ_SEL_FMAP_E0_QID_BASE",
- TRQ_SEL_FMAP_E0_QID_BASE_MASK},
-};
-
-
-static struct regfield_info
- trq_sel_fmap_e1_field_info[] = {
- {"TRQ_SEL_FMAP_E1_RSVD_1",
- TRQ_SEL_FMAP_E1_RSVD_1_MASK},
- {"TRQ_SEL_FMAP_E1_QID_MAX",
- TRQ_SEL_FMAP_E1_QID_MAX_MASK},
- {"TRQ_SEL_FMAP_E1_QID_BASE",
- TRQ_SEL_FMAP_E1_QID_BASE_MASK},
-};
-
-
-static struct regfield_info
- trq_sel_fmap_e2_field_info[] = {
- {"TRQ_SEL_FMAP_E2_RSVD_1",
- TRQ_SEL_FMAP_E2_RSVD_1_MASK},
- {"TRQ_SEL_FMAP_E2_QID_MAX",
- TRQ_SEL_FMAP_E2_QID_MAX_MASK},
- {"TRQ_SEL_FMAP_E2_QID_BASE",
- TRQ_SEL_FMAP_E2_QID_BASE_MASK},
-};
-
-
-static struct regfield_info
- trq_sel_fmap_e3_field_info[] = {
- {"TRQ_SEL_FMAP_E3_RSVD_1",
- TRQ_SEL_FMAP_E3_RSVD_1_MASK},
- {"TRQ_SEL_FMAP_E3_QID_MAX",
- TRQ_SEL_FMAP_E3_QID_MAX_MASK},
- {"TRQ_SEL_FMAP_E3_QID_BASE",
- TRQ_SEL_FMAP_E3_QID_BASE_MASK},
-};
-
-
-static struct regfield_info
- trq_sel_fmap_e4_field_info[] = {
- {"TRQ_SEL_FMAP_E4_RSVD_1",
- TRQ_SEL_FMAP_E4_RSVD_1_MASK},
- {"TRQ_SEL_FMAP_E4_QID_MAX",
- TRQ_SEL_FMAP_E4_QID_MAX_MASK},
- {"TRQ_SEL_FMAP_E4_QID_BASE",
- TRQ_SEL_FMAP_E4_QID_BASE_MASK},
-};
-
-
-static struct regfield_info
- trq_sel_fmap_e5_field_info[] = {
- {"TRQ_SEL_FMAP_E5_RSVD_1",
- TRQ_SEL_FMAP_E5_RSVD_1_MASK},
- {"TRQ_SEL_FMAP_E5_QID_MAX",
- TRQ_SEL_FMAP_E5_QID_MAX_MASK},
- {"TRQ_SEL_FMAP_E5_QID_BASE",
- TRQ_SEL_FMAP_E5_QID_BASE_MASK},
-};
-
-
-static struct regfield_info
- trq_sel_fmap_e6_field_info[] = {
- {"TRQ_SEL_FMAP_E6_RSVD_1",
- TRQ_SEL_FMAP_E6_RSVD_1_MASK},
- {"TRQ_SEL_FMAP_E6_QID_MAX",
- TRQ_SEL_FMAP_E6_QID_MAX_MASK},
- {"TRQ_SEL_FMAP_E6_QID_BASE",
- TRQ_SEL_FMAP_E6_QID_BASE_MASK},
-};
-
-
-static struct regfield_info
- trq_sel_fmap_e7_field_info[] = {
- {"TRQ_SEL_FMAP_E7_RSVD_1",
- TRQ_SEL_FMAP_E7_RSVD_1_MASK},
- {"TRQ_SEL_FMAP_E7_QID_MAX",
- TRQ_SEL_FMAP_E7_QID_MAX_MASK},
- {"TRQ_SEL_FMAP_E7_QID_BASE",
- TRQ_SEL_FMAP_E7_QID_BASE_MASK},
-};
-
-
-static struct regfield_info
- trq_sel_fmap_e8_field_info[] = {
- {"TRQ_SEL_FMAP_E8_RSVD_1",
- TRQ_SEL_FMAP_E8_RSVD_1_MASK},
- {"TRQ_SEL_FMAP_E8_QID_MAX",
- TRQ_SEL_FMAP_E8_QID_MAX_MASK},
- {"TRQ_SEL_FMAP_E8_QID_BASE",
- TRQ_SEL_FMAP_E8_QID_BASE_MASK},
-};
-
-
-static struct regfield_info
- trq_sel_fmap_e9_field_info[] = {
- {"TRQ_SEL_FMAP_E9_RSVD_1",
- TRQ_SEL_FMAP_E9_RSVD_1_MASK},
- {"TRQ_SEL_FMAP_E9_QID_MAX",
- TRQ_SEL_FMAP_E9_QID_MAX_MASK},
- {"TRQ_SEL_FMAP_E9_QID_BASE",
- TRQ_SEL_FMAP_E9_QID_BASE_MASK},
-};
-
-
-static struct regfield_info
- trq_sel_fmap_ea_field_info[] = {
- {"TRQ_SEL_FMAP_EA_RSVD_1",
- TRQ_SEL_FMAP_EA_RSVD_1_MASK},
- {"TRQ_SEL_FMAP_EA_QID_MAX",
- TRQ_SEL_FMAP_EA_QID_MAX_MASK},
- {"TRQ_SEL_FMAP_EA_QID_BASE",
- TRQ_SEL_FMAP_EA_QID_BASE_MASK},
-};
-
-
-static struct regfield_info
- trq_sel_fmap_eb_field_info[] = {
- {"TRQ_SEL_FMAP_EB_RSVD_1",
- TRQ_SEL_FMAP_EB_RSVD_1_MASK},
- {"TRQ_SEL_FMAP_EB_QID_MAX",
- TRQ_SEL_FMAP_EB_QID_MAX_MASK},
- {"TRQ_SEL_FMAP_EB_QID_BASE",
- TRQ_SEL_FMAP_EB_QID_BASE_MASK},
-};
-
-
-static struct regfield_info
- trq_sel_fmap_ec_field_info[] = {
- {"TRQ_SEL_FMAP_EC_RSVD_1",
- TRQ_SEL_FMAP_EC_RSVD_1_MASK},
- {"TRQ_SEL_FMAP_EC_QID_MAX",
- TRQ_SEL_FMAP_EC_QID_MAX_MASK},
- {"TRQ_SEL_FMAP_EC_QID_BASE",
- TRQ_SEL_FMAP_EC_QID_BASE_MASK},
-};
-
-
-static struct regfield_info
- trq_sel_fmap_ed_field_info[] = {
- {"TRQ_SEL_FMAP_ED_RSVD_1",
- TRQ_SEL_FMAP_ED_RSVD_1_MASK},
- {"TRQ_SEL_FMAP_ED_QID_MAX",
- TRQ_SEL_FMAP_ED_QID_MAX_MASK},
- {"TRQ_SEL_FMAP_ED_QID_BASE",
- TRQ_SEL_FMAP_ED_QID_BASE_MASK},
-};
-
-
-static struct regfield_info
- trq_sel_fmap_ee_field_info[] = {
- {"TRQ_SEL_FMAP_EE_RSVD_1",
- TRQ_SEL_FMAP_EE_RSVD_1_MASK},
- {"TRQ_SEL_FMAP_EE_QID_MAX",
- TRQ_SEL_FMAP_EE_QID_MAX_MASK},
- {"TRQ_SEL_FMAP_EE_QID_BASE",
- TRQ_SEL_FMAP_EE_QID_BASE_MASK},
-};
-
-
-static struct regfield_info
- trq_sel_fmap_ef_field_info[] = {
- {"TRQ_SEL_FMAP_EF_RSVD_1",
- TRQ_SEL_FMAP_EF_RSVD_1_MASK},
- {"TRQ_SEL_FMAP_EF_QID_MAX",
- TRQ_SEL_FMAP_EF_QID_MAX_MASK},
- {"TRQ_SEL_FMAP_EF_QID_BASE",
- TRQ_SEL_FMAP_EF_QID_BASE_MASK},
-};
-
-
-static struct regfield_info
- trq_sel_fmap_f0_field_info[] = {
- {"TRQ_SEL_FMAP_F0_RSVD_1",
- TRQ_SEL_FMAP_F0_RSVD_1_MASK},
- {"TRQ_SEL_FMAP_F0_QID_MAX",
- TRQ_SEL_FMAP_F0_QID_MAX_MASK},
- {"TRQ_SEL_FMAP_F0_QID_BASE",
- TRQ_SEL_FMAP_F0_QID_BASE_MASK},
-};
-
-
-static struct regfield_info
- ind_ctxt_data_3_field_info[] = {
- {"IND_CTXT_DATA_3_DATA",
- IND_CTXT_DATA_3_DATA_MASK},
-};
-
-
-static struct regfield_info
- ind_ctxt_data_2_field_info[] = {
- {"IND_CTXT_DATA_2_DATA",
- IND_CTXT_DATA_2_DATA_MASK},
-};
-
-
-static struct regfield_info
- ind_ctxt_data_1_field_info[] = {
- {"IND_CTXT_DATA_1_DATA",
- IND_CTXT_DATA_1_DATA_MASK},
-};
-
-
-static struct regfield_info
- ind_ctxt_data_0_field_info[] = {
- {"IND_CTXT_DATA_0_DATA",
- IND_CTXT_DATA_0_DATA_MASK},
-};
-
-
-static struct regfield_info
- ind_ctxt3_field_info[] = {
- {"IND_CTXT3",
- IND_CTXT3_MASK},
-};
-
-
-static struct regfield_info
- ind_ctxt2_field_info[] = {
- {"IND_CTXT2",
- IND_CTXT2_MASK},
-};
-
-
-static struct regfield_info
- ind_ctxt1_field_info[] = {
- {"IND_CTXT1",
- IND_CTXT1_MASK},
-};
-
-
-static struct regfield_info
- ind_ctxt0_field_info[] = {
- {"IND_CTXT0",
- IND_CTXT0_MASK},
-};
-
-
-static struct regfield_info
- ind_ctxt_cmd_field_info[] = {
- {"IND_CTXT_CMD_RSVD_1",
- IND_CTXT_CMD_RSVD_1_MASK},
- {"IND_CTXT_CMD_QID",
- IND_CTXT_CMD_QID_MASK},
- {"IND_CTXT_CMD_OP",
- IND_CTXT_CMD_OP_MASK},
- {"IND_CTXT_CMD_SET",
- IND_CTXT_CMD_SET_MASK},
- {"IND_CTXT_CMD_BUSY",
- IND_CTXT_CMD_BUSY_MASK},
-};
-
-
-static struct regfield_info
- c2h_timer_cnt_1_field_info[] = {
- {"C2H_TIMER_CNT_1_RSVD_1",
- C2H_TIMER_CNT_1_RSVD_1_MASK},
- {"C2H_TIMER_CNT_1",
- C2H_TIMER_CNT_1_MASK},
-};
-
-
-static struct regfield_info
- c2h_timer_cnt_2_field_info[] = {
- {"C2H_TIMER_CNT_2_RSVD_1",
- C2H_TIMER_CNT_2_RSVD_1_MASK},
- {"C2H_TIMER_CNT_2",
- C2H_TIMER_CNT_2_MASK},
-};
-
-
-static struct regfield_info
- c2h_timer_cnt_3_field_info[] = {
- {"C2H_TIMER_CNT_3_RSVD_1",
- C2H_TIMER_CNT_3_RSVD_1_MASK},
- {"C2H_TIMER_CNT_3",
- C2H_TIMER_CNT_3_MASK},
-};
-
-
-static struct regfield_info
- c2h_timer_cnt_4_field_info[] = {
- {"C2H_TIMER_CNT_4_RSVD_1",
- C2H_TIMER_CNT_4_RSVD_1_MASK},
- {"C2H_TIMER_CNT_4",
- C2H_TIMER_CNT_4_MASK},
-};
-
-
-static struct regfield_info
- c2h_timer_cnt_5_field_info[] = {
- {"C2H_TIMER_CNT_5_RSVD_1",
- C2H_TIMER_CNT_5_RSVD_1_MASK},
- {"C2H_TIMER_CNT_5",
- C2H_TIMER_CNT_5_MASK},
-};
-
-
-static struct regfield_info
- c2h_timer_cnt_6_field_info[] = {
- {"C2H_TIMER_CNT_6_RSVD_1",
- C2H_TIMER_CNT_6_RSVD_1_MASK},
- {"C2H_TIMER_CNT_6",
- C2H_TIMER_CNT_6_MASK},
-};
-
-
-static struct regfield_info
- c2h_timer_cnt_7_field_info[] = {
- {"C2H_TIMER_CNT_7_RSVD_1",
- C2H_TIMER_CNT_7_RSVD_1_MASK},
- {"C2H_TIMER_CNT_7",
- C2H_TIMER_CNT_7_MASK},
-};
-
-
-static struct regfield_info
- c2h_timer_cnt_8_field_info[] = {
- {"C2H_TIMER_CNT_8_RSVD_1",
- C2H_TIMER_CNT_8_RSVD_1_MASK},
- {"C2H_TIMER_CNT_8",
- C2H_TIMER_CNT_8_MASK},
-};
-
-
-static struct regfield_info
- c2h_timer_cnt_9_field_info[] = {
- {"C2H_TIMER_CNT_9_RSVD_1",
- C2H_TIMER_CNT_9_RSVD_1_MASK},
- {"C2H_TIMER_CNT_9",
- C2H_TIMER_CNT_9_MASK},
-};
-
-
-static struct regfield_info
- c2h_timer_cnt_a_field_info[] = {
- {"C2H_TIMER_CNT_A_RSVD_1",
- C2H_TIMER_CNT_A_RSVD_1_MASK},
- {"C2H_TIMER_CNT_A",
- C2H_TIMER_CNT_A_MASK},
-};
-
-
-static struct regfield_info
- c2h_timer_cnt_b_field_info[] = {
- {"C2H_TIMER_CNT_B_RSVD_1",
- C2H_TIMER_CNT_B_RSVD_1_MASK},
- {"C2H_TIMER_CNT_B",
- C2H_TIMER_CNT_B_MASK},
-};
-
-
-static struct regfield_info
- c2h_timer_cnt_c_field_info[] = {
- {"C2H_TIMER_CNT_C_RSVD_1",
- C2H_TIMER_CNT_C_RSVD_1_MASK},
- {"C2H_TIMER_CNT_C",
- C2H_TIMER_CNT_C_MASK},
-};
-
-
-static struct regfield_info
- c2h_timer_cnt_d_field_info[] = {
- {"C2H_TIMER_CNT_D_RSVD_1",
- C2H_TIMER_CNT_D_RSVD_1_MASK},
- {"C2H_TIMER_CNT_D",
- C2H_TIMER_CNT_D_MASK},
-};
-
-
-static struct regfield_info
- c2h_timer_cnt_e_field_info[] = {
- {"C2H_TIMER_CNT_E_RSVD_1",
- C2H_TIMER_CNT_E_RSVD_1_MASK},
- {"C2H_TIMER_CNT_E",
- C2H_TIMER_CNT_E_MASK},
-};
-
-
-static struct regfield_info
- c2h_timer_cnt_f_field_info[] = {
- {"C2H_TIMER_CNT_F_RSVD_1",
- C2H_TIMER_CNT_F_RSVD_1_MASK},
- {"C2H_TIMER_CNT_F",
- C2H_TIMER_CNT_F_MASK},
-};
-
-
-static struct regfield_info
- c2h_timer_cnt_10_field_info[] = {
- {"C2H_TIMER_CNT_10_RSVD_1",
- C2H_TIMER_CNT_10_RSVD_1_MASK},
- {"C2H_TIMER_CNT_10",
- C2H_TIMER_CNT_10_MASK},
-};
-
-
-static struct regfield_info
- c2h_cnt_th_1_field_info[] = {
- {"C2H_CNT_TH_1_RSVD_1",
- C2H_CNT_TH_1_RSVD_1_MASK},
- {"C2H_CNT_TH_1_THESHOLD_CNT",
- C2H_CNT_TH_1_THESHOLD_CNT_MASK},
-};
-
-
-static struct regfield_info
- c2h_cnt_th_2_field_info[] = {
- {"C2H_CNT_TH_2_RSVD_1",
- C2H_CNT_TH_2_RSVD_1_MASK},
- {"C2H_CNT_TH_2_THESHOLD_CNT",
- C2H_CNT_TH_2_THESHOLD_CNT_MASK},
-};
-
-
-static struct regfield_info
- c2h_cnt_th_3_field_info[] = {
- {"C2H_CNT_TH_3_RSVD_1",
- C2H_CNT_TH_3_RSVD_1_MASK},
- {"C2H_CNT_TH_3_THESHOLD_CNT",
- C2H_CNT_TH_3_THESHOLD_CNT_MASK},
-};
-
-
-static struct regfield_info
- c2h_cnt_th_4_field_info[] = {
- {"C2H_CNT_TH_4_RSVD_1",
- C2H_CNT_TH_4_RSVD_1_MASK},
- {"C2H_CNT_TH_4_THESHOLD_CNT",
- C2H_CNT_TH_4_THESHOLD_CNT_MASK},
-};
-
-
-static struct regfield_info
- c2h_cnt_th_5_field_info[] = {
- {"C2H_CNT_TH_5_RSVD_1",
- C2H_CNT_TH_5_RSVD_1_MASK},
- {"C2H_CNT_TH_5_THESHOLD_CNT",
- C2H_CNT_TH_5_THESHOLD_CNT_MASK},
-};
-
-
-static struct regfield_info
- c2h_cnt_th_6_field_info[] = {
- {"C2H_CNT_TH_6_RSVD_1",
- C2H_CNT_TH_6_RSVD_1_MASK},
- {"C2H_CNT_TH_6_THESHOLD_CNT",
- C2H_CNT_TH_6_THESHOLD_CNT_MASK},
-};
-
-
-static struct regfield_info
- c2h_cnt_th_7_field_info[] = {
- {"C2H_CNT_TH_7_RSVD_1",
- C2H_CNT_TH_7_RSVD_1_MASK},
- {"C2H_CNT_TH_7_THESHOLD_CNT",
- C2H_CNT_TH_7_THESHOLD_CNT_MASK},
-};
-
-
-static struct regfield_info
- c2h_cnt_th_8_field_info[] = {
- {"C2H_CNT_TH_8_RSVD_1",
- C2H_CNT_TH_8_RSVD_1_MASK},
- {"C2H_CNT_TH_8_THESHOLD_CNT",
- C2H_CNT_TH_8_THESHOLD_CNT_MASK},
-};
-
-
-static struct regfield_info
- c2h_cnt_th_9_field_info[] = {
- {"C2H_CNT_TH_9_RSVD_1",
- C2H_CNT_TH_9_RSVD_1_MASK},
- {"C2H_CNT_TH_9_THESHOLD_CNT",
- C2H_CNT_TH_9_THESHOLD_CNT_MASK},
-};
-
-
-static struct regfield_info
- c2h_cnt_th_a_field_info[] = {
- {"C2H_CNT_TH_A_RSVD_1",
- C2H_CNT_TH_A_RSVD_1_MASK},
- {"C2H_CNT_TH_A_THESHOLD_CNT",
- C2H_CNT_TH_A_THESHOLD_CNT_MASK},
-};
-
-
-static struct regfield_info
- c2h_cnt_th_b_field_info[] = {
- {"C2H_CNT_TH_B_RSVD_1",
- C2H_CNT_TH_B_RSVD_1_MASK},
- {"C2H_CNT_TH_B_THESHOLD_CNT",
- C2H_CNT_TH_B_THESHOLD_CNT_MASK},
-};
-
-
-static struct regfield_info
- c2h_cnt_th_c_field_info[] = {
- {"C2H_CNT_TH_C_RSVD_1",
- C2H_CNT_TH_C_RSVD_1_MASK},
- {"C2H_CNT_TH_C_THESHOLD_CNT",
- C2H_CNT_TH_C_THESHOLD_CNT_MASK},
-};
-
-
-static struct regfield_info
- c2h_cnt_th_d_field_info[] = {
- {"C2H_CNT_TH_D_RSVD_1",
- C2H_CNT_TH_D_RSVD_1_MASK},
- {"C2H_CNT_TH_D_THESHOLD_CNT",
- C2H_CNT_TH_D_THESHOLD_CNT_MASK},
-};
-
-
-static struct regfield_info
- c2h_cnt_th_e_field_info[] = {
- {"C2H_CNT_TH_E_RSVD_1",
- C2H_CNT_TH_E_RSVD_1_MASK},
- {"C2H_CNT_TH_E_THESHOLD_CNT",
- C2H_CNT_TH_E_THESHOLD_CNT_MASK},
-};
-
-
-static struct regfield_info
- c2h_cnt_th_f_field_info[] = {
- {"C2H_CNT_TH_F_RSVD_1",
- C2H_CNT_TH_F_RSVD_1_MASK},
- {"C2H_CNT_TH_F_THESHOLD_CNT",
- C2H_CNT_TH_F_THESHOLD_CNT_MASK},
-};
-
-
-static struct regfield_info
- c2h_cnt_th_10_field_info[] = {
- {"C2H_CNT_TH_10_RSVD_1",
- C2H_CNT_TH_10_RSVD_1_MASK},
- {"C2H_CNT_TH_10_THESHOLD_CNT",
- C2H_CNT_TH_10_THESHOLD_CNT_MASK},
-};
-
-
-static struct regfield_info
- c2h_qid2vec_map_qid_field_info[] = {
- {"C2H_QID2VEC_MAP_QID_RSVD_1",
- C2H_QID2VEC_MAP_QID_RSVD_1_MASK},
- {"C2H_QID2VEC_MAP_QID_QID",
- C2H_QID2VEC_MAP_QID_QID_MASK},
-};
-
-
-static struct regfield_info
- c2h_qid2vec_map_field_info[] = {
- {"C2H_QID2VEC_MAP_RSVD_1",
- C2H_QID2VEC_MAP_RSVD_1_MASK},
- {"C2H_QID2VEC_MAP_H2C_EN_COAL",
- C2H_QID2VEC_MAP_H2C_EN_COAL_MASK},
- {"C2H_QID2VEC_MAP_H2C_VECTOR",
- C2H_QID2VEC_MAP_H2C_VECTOR_MASK},
- {"C2H_QID2VEC_MAP_C2H_EN_COAL",
- C2H_QID2VEC_MAP_C2H_EN_COAL_MASK},
- {"C2H_QID2VEC_MAP_C2H_VECTOR",
- C2H_QID2VEC_MAP_C2H_VECTOR_MASK},
-};
-
-
-static struct regfield_info
- c2h_stat_s_axis_c2h_accepted_field_info[] = {
- {"C2H_STAT_S_AXIS_C2H_ACCEPTED",
- C2H_STAT_S_AXIS_C2H_ACCEPTED_MASK},
-};
-
-
-static struct regfield_info
- c2h_stat_s_axis_wrb_accepted_field_info[] = {
- {"C2H_STAT_S_AXIS_WRB_ACCEPTED",
- C2H_STAT_S_AXIS_WRB_ACCEPTED_MASK},
-};
-
-
-static struct regfield_info
- c2h_stat_desc_rsp_pkt_accepted_field_info[] = {
- {"C2H_STAT_DESC_RSP_PKT_ACCEPTED_D",
- C2H_STAT_DESC_RSP_PKT_ACCEPTED_D_MASK},
-};
-
-
-static struct regfield_info
- c2h_stat_axis_pkg_cmp_field_info[] = {
- {"C2H_STAT_AXIS_PKG_CMP",
- C2H_STAT_AXIS_PKG_CMP_MASK},
-};
-
-
-static struct regfield_info
- c2h_stat_desc_rsp_accepted_field_info[] = {
- {"C2H_STAT_DESC_RSP_ACCEPTED_D",
- C2H_STAT_DESC_RSP_ACCEPTED_D_MASK},
-};
-
-
-static struct regfield_info
- c2h_stat_desc_rsp_cmp_field_info[] = {
- {"C2H_STAT_DESC_RSP_CMP_D",
- C2H_STAT_DESC_RSP_CMP_D_MASK},
-};
-
-
-static struct regfield_info
- c2h_stat_wrq_out_field_info[] = {
- {"C2H_STAT_WRQ_OUT",
- C2H_STAT_WRQ_OUT_MASK},
-};
-
-
-static struct regfield_info
- c2h_stat_wpl_ren_accepted_field_info[] = {
- {"C2H_STAT_WPL_REN_ACCEPTED",
- C2H_STAT_WPL_REN_ACCEPTED_MASK},
-};
-
-
-static struct regfield_info
- c2h_stat_total_wrq_len_field_info[] = {
- {"C2H_STAT_TOTAL_WRQ_LEN",
- C2H_STAT_TOTAL_WRQ_LEN_MASK},
-};
-
-
-static struct regfield_info
- c2h_stat_total_wpl_len_field_info[] = {
- {"C2H_STAT_TOTAL_WPL_LEN",
- C2H_STAT_TOTAL_WPL_LEN_MASK},
-};
-
-
-static struct regfield_info
- c2h_buf_sz_0_field_info[] = {
- {"C2H_BUF_SZ_0_SIZE",
- C2H_BUF_SZ_0_SIZE_MASK},
-};
-
-
-static struct regfield_info
- c2h_buf_sz_1_field_info[] = {
- {"C2H_BUF_SZ_1_SIZE",
- C2H_BUF_SZ_1_SIZE_MASK},
-};
-
-
-static struct regfield_info
- c2h_buf_sz_2_field_info[] = {
- {"C2H_BUF_SZ_2_SIZE",
- C2H_BUF_SZ_2_SIZE_MASK},
-};
-
-
-static struct regfield_info
- c2h_buf_sz_3_field_info[] = {
- {"C2H_BUF_SZ_3_SIZE",
- C2H_BUF_SZ_3_SIZE_MASK},
-};
-
-
-static struct regfield_info
- c2h_buf_sz_4_field_info[] = {
- {"C2H_BUF_SZ_4_SIZE",
- C2H_BUF_SZ_4_SIZE_MASK},
-};
-
-
-static struct regfield_info
- c2h_buf_sz_5_field_info[] = {
- {"C2H_BUF_SZ_5_SIZE",
- C2H_BUF_SZ_5_SIZE_MASK},
-};
-
-
-static struct regfield_info
- c2h_buf_sz_7_field_info[] = {
- {"C2H_BUF_SZ_7_SIZE",
- C2H_BUF_SZ_7_SIZE_MASK},
-};
-
-
-static struct regfield_info
- c2h_buf_sz_8_field_info[] = {
- {"C2H_BUF_SZ_8_SIZE",
- C2H_BUF_SZ_8_SIZE_MASK},
-};
-
-
-static struct regfield_info
- c2h_buf_sz_9_field_info[] = {
- {"C2H_BUF_SZ_9_SIZE",
- C2H_BUF_SZ_9_SIZE_MASK},
-};
-
-
-static struct regfield_info
- c2h_buf_sz_10_field_info[] = {
- {"C2H_BUF_SZ_10_SIZE",
- C2H_BUF_SZ_10_SIZE_MASK},
-};
-
-
-static struct regfield_info
- c2h_buf_sz_11_field_info[] = {
- {"C2H_BUF_SZ_11_SIZE",
- C2H_BUF_SZ_11_SIZE_MASK},
-};
-
-
-static struct regfield_info
- c2h_buf_sz_12_field_info[] = {
- {"C2H_BUF_SZ_12_SIZE",
- C2H_BUF_SZ_12_SIZE_MASK},
-};
-
-
-static struct regfield_info
- c2h_buf_sz_13_field_info[] = {
- {"C2H_BUF_SZ_13_SIZE",
- C2H_BUF_SZ_13_SIZE_MASK},
-};
-
-
-static struct regfield_info
- c2h_buf_sz_14_field_info[] = {
- {"C2H_BUF_SZ_14_SIZE",
- C2H_BUF_SZ_14_SIZE_MASK},
-};
-
-
-static struct regfield_info
- c2h_buf_sz_15_field_info[] = {
- {"C2H_BUF_SZ_15_SIZE",
- C2H_BUF_SZ_15_SIZE_MASK},
-};
-
-
-static struct regfield_info
- c2h_err_stat_field_info[] = {
- {"C2H_ERR_STAT_RSVD_1",
- C2H_ERR_STAT_RSVD_1_MASK},
- {"C2H_ERR_STAT_WRB_PRTY_ERR",
- C2H_ERR_STAT_WRB_PRTY_ERR_MASK},
- {"C2H_ERR_STAT_WRB_CIDX_ERR",
- C2H_ERR_STAT_WRB_CIDX_ERR_MASK},
- {"C2H_ERR_STAT_WRB_QFULL_ERR",
- C2H_ERR_STAT_WRB_QFULL_ERR_MASK},
- {"C2H_ERR_STAT_WRB_INV_Q_ERR",
- C2H_ERR_STAT_WRB_INV_Q_ERR_MASK},
- {"C2H_ERR_STAT_PORT_ID_BYP_IN_MISMATCH",
- C2H_ERR_STAT_PORT_ID_BYP_IN_MISMATCH_MASK},
- {"C2H_ERR_STAT_PORT_ID_CTXT_MISMATCH",
- C2H_ERR_STAT_PORT_ID_CTXT_MISMATCH_MASK},
- {"C2H_ERR_STAT_ERR_DESC_CNT",
- C2H_ERR_STAT_ERR_DESC_CNT_MASK},
- {"C2H_ERR_STAT_RSVD_2",
- C2H_ERR_STAT_RSVD_2_MASK},
- {"C2H_ERR_STAT_MSI_INT_FAIL",
- C2H_ERR_STAT_MSI_INT_FAIL_MASK},
- {"C2H_ERR_STAT_ENG_WPL_DATA_PAR_ERR",
- C2H_ERR_STAT_ENG_WPL_DATA_PAR_ERR_MASK},
- {"C2H_ERR_STAT_RSVD_3",
- C2H_ERR_STAT_RSVD_3_MASK},
- {"C2H_ERR_STAT_DESC_RSP_ERR",
- C2H_ERR_STAT_DESC_RSP_ERR_MASK},
- {"C2H_ERR_STAT_QID_MISMATCH",
- C2H_ERR_STAT_QID_MISMATCH_MASK},
- {"C2H_ERR_STAT_RSVD_4",
- C2H_ERR_STAT_RSVD_4_MASK},
- {"C2H_ERR_STAT_LEN_MISMATCH",
- C2H_ERR_STAT_LEN_MISMATCH_MASK},
- {"C2H_ERR_STAT_MTY_MISMATCH",
- C2H_ERR_STAT_MTY_MISMATCH_MASK},
-};
-
-
-static struct regfield_info
- c2h_err_mask_field_info[] = {
- {"C2H_ERR_EN",
- C2H_ERR_EN_MASK},
-};
-
-
-static struct regfield_info
- c2h_fatal_err_stat_field_info[] = {
- {"C2H_FATAL_ERR_STAT_RSVD_1",
- C2H_FATAL_ERR_STAT_RSVD_1_MASK},
- {"C2H_FATAL_ERR_STAT_WPL_DATA_PAR_ERR",
- C2H_FATAL_ERR_STAT_WPL_DATA_PAR_ERR_MASK},
- {"C2H_FATAL_ERR_STAT_PLD_FIFO_RAM_RDBE",
- C2H_FATAL_ERR_STAT_PLD_FIFO_RAM_RDBE_MASK},
- {"C2H_FATAL_ERR_STAT_QID_FIFO_RAM_RDBE",
- C2H_FATAL_ERR_STAT_QID_FIFO_RAM_RDBE_MASK},
- {"C2H_FATAL_ERR_STAT_TUSER_FIFO_RAM_RDBE",
- C2H_FATAL_ERR_STAT_TUSER_FIFO_RAM_RDBE_MASK},
- {"C2H_FATAL_ERR_STAT_WRB_COAL_DATA_RAM_RDBE",
- C2H_FATAL_ERR_STAT_WRB_COAL_DATA_RAM_RDBE_MASK},
- {"C2H_FATAL_ERR_STAT_INT_QID2VEC_RAM_RDBE",
- C2H_FATAL_ERR_STAT_INT_QID2VEC_RAM_RDBE_MASK},
- {"C2H_FATAL_ERR_STAT_INT_CTXT_RAM_RDBE",
- C2H_FATAL_ERR_STAT_INT_CTXT_RAM_RDBE_MASK},
- {"C2H_FATAL_ERR_STAT_DESC_REQ_FIFO_RAM_RDBE",
- C2H_FATAL_ERR_STAT_DESC_REQ_FIFO_RAM_RDBE_MASK},
- {"C2H_FATAL_ERR_STAT_PFCH_CTXT_RAM_RDBE",
- C2H_FATAL_ERR_STAT_PFCH_CTXT_RAM_RDBE_MASK},
- {"C2H_FATAL_ERR_STAT_WRB_CTXT_RAM_RDBE",
- C2H_FATAL_ERR_STAT_WRB_CTXT_RAM_RDBE_MASK},
- {"C2H_FATAL_ERR_STAT_PFCH_LL_RAM_RDBE",
- C2H_FATAL_ERR_STAT_PFCH_LL_RAM_RDBE_MASK},
- {"C2H_FATAL_ERR_STAT_TIMER_FIFO_RAM_RDBE",
- C2H_FATAL_ERR_STAT_TIMER_FIFO_RAM_RDBE_MASK},
- {"C2H_FATAL_ERR_STAT_QID_MISMATCH",
- C2H_FATAL_ERR_STAT_QID_MISMATCH_MASK},
- {"C2H_FATAL_ERR_STAT_RSVD_2",
- C2H_FATAL_ERR_STAT_RSVD_2_MASK},
- {"C2H_FATAL_ERR_STAT_LEN_MISMATCH",
- C2H_FATAL_ERR_STAT_LEN_MISMATCH_MASK},
- {"C2H_FATAL_ERR_STAT_MTY_MISMATCH",
- C2H_FATAL_ERR_STAT_MTY_MISMATCH_MASK},
-};
-
-
-static struct regfield_info
- c2h_fatal_err_mask_field_info[] = {
- {"C2H_FATAL_ERR_C2HEN",
- C2H_FATAL_ERR_C2HEN_MASK},
-};
-
-
-static struct regfield_info
- c2h_fatal_err_enable_field_info[] = {
- {"C2H_FATAL_ERR_ENABLE_RSVD_1",
- C2H_FATAL_ERR_ENABLE_RSVD_1_MASK},
- {"C2H_FATAL_ERR_ENABLE_WPL_PAR_INV",
- C2H_FATAL_ERR_ENABLE_WPL_PAR_INV_MASK},
- {"C2H_FATAL_ERR_ENABLE_WRQ_DIS",
- C2H_FATAL_ERR_ENABLE_WRQ_DIS_MASK},
-};
-
-
-static struct regfield_info
- glbl_err_int_field_info[] = {
- {"GLBL_ERR_INT_RSVD_1",
- GLBL_ERR_INT_RSVD_1_MASK},
- {"GLBL_ERR_INT_ARM",
- GLBL_ERR_INT_ARM_MASK},
- {"GLBL_ERR_INT_EN_COAL",
- GLBL_ERR_INT_EN_COAL_MASK},
- {"GLBL_ERR_INT_VEC",
- GLBL_ERR_INT_VEC_MASK},
- {"GLBL_ERR_INT_FUNC",
- GLBL_ERR_INT_FUNC_MASK},
-};
-
-
-static struct regfield_info
- c2h_pfch_cfg_field_info[] = {
- {"C2H_PFCH_CFG_EVT_QCNT_TH",
- C2H_PFCH_CFG_EVT_QCNT_TH_MASK},
- {"C2H_PFCH_CFG_QCNT",
- C2H_PFCH_CFG_QCNT_MASK},
- {"C2H_PFCH_CFG_NUM",
- C2H_PFCH_CFG_NUM_MASK},
- {"C2H_PFCH_CFG_FL_TH",
- C2H_PFCH_CFG_FL_TH_MASK},
-};
-
-
-static struct regfield_info
- c2h_int_timer_tick_field_info[] = {
- {"C2H_INT_TIMER_TICK",
- C2H_INT_TIMER_TICK_MASK},
-};
-
-
-static struct regfield_info
- c2h_stat_desc_rsp_drop_accepted_field_info[] = {
- {"C2H_STAT_DESC_RSP_DROP_ACCEPTED_D",
- C2H_STAT_DESC_RSP_DROP_ACCEPTED_D_MASK},
-};
-
-
-static struct regfield_info
- c2h_stat_desc_rsp_err_accepted_field_info[] = {
- {"C2H_STAT_DESC_RSP_ERR_ACCEPTED_D",
- C2H_STAT_DESC_RSP_ERR_ACCEPTED_D_MASK},
-};
-
-
-static struct regfield_info
- c2h_stat_desc_req_field_info[] = {
- {"C2H_STAT_DESC_REQ",
- C2H_STAT_DESC_REQ_MASK},
-};
-
-
-static struct regfield_info
- c2h_stat_dbg_dma_eng_0_field_info[] = {
- {"C2H_STAT_DMA_ENG_0_RSVD_1",
- C2H_STAT_DMA_ENG_0_RSVD_1_MASK},
- {"C2H_STAT_DMA_ENG_0_WRB_FIFO_OUT_CNT",
- C2H_STAT_DMA_ENG_0_WRB_FIFO_OUT_CNT_MASK},
- {"C2H_STAT_DMA_ENG_0_QID_FIFO_OUT_CNT",
- C2H_STAT_DMA_ENG_0_QID_FIFO_OUT_CNT_MASK},
- {"C2H_STAT_DMA_ENG_0_PLD_FIFO_OUT_CNT",
- C2H_STAT_DMA_ENG_0_PLD_FIFO_OUT_CNT_MASK},
- {"C2H_STAT_DMA_ENG_0_WRQ_FIFO_OUT_CNT",
- C2H_STAT_DMA_ENG_0_WRQ_FIFO_OUT_CNT_MASK},
- {"C2H_STAT_DMA_ENG_0_WRB_SM_CS",
- C2H_STAT_DMA_ENG_0_WRB_SM_CS_MASK},
- {"C2H_STAT_DMA_ENG_0_MAIN_SM_CS",
- C2H_STAT_DMA_ENG_0_MAIN_SM_CS_MASK},
-};
-
-
-static struct regfield_info
- c2h_stat_dbg_dma_eng_1_field_info[] = {
- {"C2H_STAT_DMA_ENG_1_RSVD_1",
- C2H_STAT_DMA_ENG_1_RSVD_1_MASK},
- {"C2H_STAT_DMA_ENG_1_DESC_RSP_LAST",
- C2H_STAT_DMA_ENG_1_DESC_RSP_LAST_MASK},
- {"C2H_STAT_DMA_ENG_1_PLD_FIFO_IN_CNT",
- C2H_STAT_DMA_ENG_1_PLD_FIFO_IN_CNT_MASK},
- {"C2H_STAT_DMA_ENG_1_PLD_FIFO_OUTPUT_CNT",
- C2H_STAT_DMA_ENG_1_PLD_FIFO_OUTPUT_CNT_MASK},
- {"C2H_STAT_DMA_ENG_1_QID_FIFO_IN_CNT",
- C2H_STAT_DMA_ENG_1_QID_FIFO_IN_CNT_MASK},
-};
-
-
-static struct regfield_info
- c2h_stat_dbg_dma_eng_2_field_info[] = {
- {"C2H_STAT_DMA_ENG_2_RSVD_1",
- C2H_STAT_DMA_ENG_2_RSVD_1_MASK},
- {"C2H_STAT_DMA_ENG_2_WRB_FIFO_IN_CNT",
- C2H_STAT_DMA_ENG_2_WRB_FIFO_IN_CNT_MASK},
- {"C2H_STAT_DMA_ENG_2_WRB_FIFO_OUTPUT_CNT",
- C2H_STAT_DMA_ENG_2_WRB_FIFO_OUTPUT_CNT_MASK},
- {"C2H_STAT_DMA_ENG_2_QID_FIFO_OUTPUT_CNT",
- C2H_STAT_DMA_ENG_2_QID_FIFO_OUTPUT_CNT_MASK},
-};
-
-
-static struct regfield_info
- c2h_stat_dbg_dma_eng_3_field_info[] = {
- {"C2H_STAT_DMA_ENG_3_RSVD_1",
- C2H_STAT_DMA_ENG_3_RSVD_1_MASK},
- {"C2H_STAT_DMA_ENG_3_ADDR_4K_SPLIT_CNT",
- C2H_STAT_DMA_ENG_3_ADDR_4K_SPLIT_CNT_MASK},
- {"C2H_STAT_DMA_ENG_3_WRQ_FIFO_IN_CNT",
- C2H_STAT_DMA_ENG_3_WRQ_FIFO_IN_CNT_MASK},
- {"C2H_STAT_DMA_ENG_3_WRQ_FIFO_OUTPUT_CNT",
- C2H_STAT_DMA_ENG_3_WRQ_FIFO_OUTPUT_CNT_MASK},
-};
-
-
-static struct regfield_info
- c2h_dbg_pfch_err_ctxt_field_info[] = {
- {"C2H_PFCH_ERR_CTXT_RSVD_1",
- C2H_PFCH_ERR_CTXT_RSVD_1_MASK},
- {"C2H_PFCH_ERR_CTXT_ERR_STAT",
- C2H_PFCH_ERR_CTXT_ERR_STAT_MASK},
- {"C2H_PFCH_ERR_CTXT_CMD_WR",
- C2H_PFCH_ERR_CTXT_CMD_WR_MASK},
- {"C2H_PFCH_ERR_CTXT_QID",
- C2H_PFCH_ERR_CTXT_QID_MASK},
- {"C2H_PFCH_ERR_CTXT_DONE",
- C2H_PFCH_ERR_CTXT_DONE_MASK},
-};
-
-
-static struct regfield_info
- c2h_first_err_qid_field_info[] = {
- {"C2H_FIRST_ERR_QID_RSVD_1",
- C2H_FIRST_ERR_QID_RSVD_1_MASK},
- {"C2H_FIRST_ERR_QID_ERR_STAT",
- C2H_FIRST_ERR_QID_ERR_STAT_MASK},
- {"C2H_FIRST_ERR_QID_CMD_WR",
- C2H_FIRST_ERR_QID_CMD_WR_MASK},
- {"C2H_FIRST_ERR_QID_QID",
- C2H_FIRST_ERR_QID_QID_MASK},
-};
-
-
-static struct regfield_info
- stat_num_wrb_in_field_info[] = {
- {"STAT_NUM_WRB_IN_RSVD_1",
- STAT_NUM_WRB_IN_RSVD_1_MASK},
- {"STAT_NUM_WRB_IN_WRB_CNT",
- STAT_NUM_WRB_IN_WRB_CNT_MASK},
-};
-
-
-static struct regfield_info
- stat_num_wrb_out_field_info[] = {
- {"STAT_NUM_WRB_OUT_RSVD_1",
- STAT_NUM_WRB_OUT_RSVD_1_MASK},
- {"STAT_NUM_WRB_OUT_WRB_CNT",
- STAT_NUM_WRB_OUT_WRB_CNT_MASK},
-};
-
-
-static struct regfield_info
- stat_num_wrb_drp_field_info[] = {
- {"STAT_NUM_WRB_DRP_RSVD_1",
- STAT_NUM_WRB_DRP_RSVD_1_MASK},
- {"STAT_NUM_WRB_DRP_WRB_CNT",
- STAT_NUM_WRB_DRP_WRB_CNT_MASK},
-};
-
-
-static struct regfield_info
- stat_num_stat_desc_out_field_info[] = {
- {"STAT_NUM_STAT_DESC_OUT_RSVD_1",
- STAT_NUM_STAT_DESC_OUT_RSVD_1_MASK},
- {"STAT_NUM_STAT_DESC_OUT_CNT",
- STAT_NUM_STAT_DESC_OUT_CNT_MASK},
-};
-
-
-static struct regfield_info
- stat_num_dsc_crdt_sent_field_info[] = {
- {"STAT_NUM_DSC_CRDT_SENT_RSVD_1",
- STAT_NUM_DSC_CRDT_SENT_RSVD_1_MASK},
- {"STAT_NUM_DSC_CRDT_SENT_CNT",
- STAT_NUM_DSC_CRDT_SENT_CNT_MASK},
-};
-
-
-static struct regfield_info
- stat_num_fch_dsc_rcvd_field_info[] = {
- {"STAT_NUM_FCH_DSC_RCVD_RSVD_1",
- STAT_NUM_FCH_DSC_RCVD_RSVD_1_MASK},
- {"STAT_NUM_FCH_DSC_RCVD_DSC_CNT",
- STAT_NUM_FCH_DSC_RCVD_DSC_CNT_MASK},
-};
-
-
-static struct regfield_info
- stat_num_byp_dsc_rcvd_field_info[] = {
- {"STAT_NUM_BYP_DSC_RCVD_RSVD_1",
- STAT_NUM_BYP_DSC_RCVD_RSVD_1_MASK},
- {"STAT_NUM_BYP_DSC_RCVD_DSC_CNT",
- STAT_NUM_BYP_DSC_RCVD_DSC_CNT_MASK},
-};
-
-
-static struct regfield_info
- c2h_wrb_coal_cfg_field_info[] = {
- {"C2H_WRB_COAL_CFG_MAX_BUF_SZ",
- C2H_WRB_COAL_CFG_MAX_BUF_SZ_MASK},
- {"C2H_WRB_COAL_CFG_TICK_VAL",
- C2H_WRB_COAL_CFG_TICK_VAL_MASK},
- {"C2H_WRB_COAL_CFG_TICK_CNT",
- C2H_WRB_COAL_CFG_TICK_CNT_MASK},
- {"C2H_WRB_COAL_CFG_SET_GLB_FLUSH",
- C2H_WRB_COAL_CFG_SET_GLB_FLUSH_MASK},
- {"C2H_WRB_COAL_CFG_DONE_GLB_FLUSH",
- C2H_WRB_COAL_CFG_DONE_GLB_FLUSH_MASK},
-};
-
-
-static struct regfield_info
- c2h_intr_h2c_req_field_info[] = {
- {"C2H_INTR_H2C_REQ_RSVD_1",
- C2H_INTR_H2C_REQ_RSVD_1_MASK},
- {"C2H_INTR_H2C_REQ_CNT",
- C2H_INTR_H2C_REQ_CNT_MASK},
-};
-
-
-static struct regfield_info
- c2h_intr_c2h_mm_req_field_info[] = {
- {"C2H_INTR_C2H_MM_REQ_RSVD_1",
- C2H_INTR_C2H_MM_REQ_RSVD_1_MASK},
- {"C2H_INTR_C2H_MM_REQ_CNT",
- C2H_INTR_C2H_MM_REQ_CNT_MASK},
-};
-
-
-static struct regfield_info
- c2h_intr_err_int_req_field_info[] = {
- {"C2H_INTR_ERR_INT_REQ_RSVD_1",
- C2H_INTR_ERR_INT_REQ_RSVD_1_MASK},
- {"C2H_INTR_ERR_INT_REQ_CNT",
- C2H_INTR_ERR_INT_REQ_CNT_MASK},
-};
-
-
-static struct regfield_info
- c2h_intr_c2h_st_req_field_info[] = {
- {"C2H_INTR_C2H_ST_REQ_RSVD_1",
- C2H_INTR_C2H_ST_REQ_RSVD_1_MASK},
- {"C2H_INTR_C2H_ST_REQ_CNT",
- C2H_INTR_C2H_ST_REQ_CNT_MASK},
-};
-
-
-static struct regfield_info
- c2h_intr_h2c_err_c2h_mm_msix_ack_field_info[] = {
- {"C2H_INTR_H2C_ERR_C2H_MM_MSIX_ACK_RSVD_1",
- C2H_INTR_H2C_ERR_C2H_MM_MSIX_ACK_RSVD_1_MASK},
- {"C2H_INTR_H2C_ERR_C2H_MM_MSIX_ACK_CNT",
- C2H_INTR_H2C_ERR_C2H_MM_MSIX_ACK_CNT_MASK},
-};
-
-
-static struct regfield_info
- c2h_intr_h2c_err_c2h_mm_msix_fail_field_info[] = {
- {"C2H_INTR_H2C_ERR_C2H_MM_MSIX_FAIL_RSVD_1",
- C2H_INTR_H2C_ERR_C2H_MM_MSIX_FAIL_RSVD_1_MASK},
- {"C2H_INTR_H2C_ERR_C2H_MM_MSIX_FAIL_CNT",
- C2H_INTR_H2C_ERR_C2H_MM_MSIX_FAIL_CNT_MASK},
-};
-
-
-static struct regfield_info
- c2h_intr_h2c_err_c2h_mm_msix_no_msix_field_info[] = {
- {"C2H_INTR_H2C_ERR_C2H_MM_MSIX_NO_MSIX_RSVD_1",
- C2H_INTR_H2C_ERR_C2H_MM_MSIX_NO_MSIX_RSVD_1_MASK},
- {"C2H_INTR_H2C_ERR_C2H_MM_MSIX_NO_MSIX_CNT",
- C2H_INTR_H2C_ERR_C2H_MM_MSIX_NO_MSIX_CNT_MASK},
-};
-
-
-static struct regfield_info
- c2h_intr_h2c_err_c2h_mm_ctxt_inval_field_info[] = {
- {"C2H_INTR_H2C_ERR_C2H_MM_CTXT_INVAL_RSVD_1",
- C2H_INTR_H2C_ERR_C2H_MM_CTXT_INVAL_RSVD_1_MASK},
- {"C2H_INTR_H2C_ERR_C2H_MM_CTXT_INVAL_CNT",
- C2H_INTR_H2C_ERR_C2H_MM_CTXT_INVAL_CNT_MASK},
-};
-
-
-static struct regfield_info
- c2h_intr_c2h_st_msix_ack_field_info[] = {
- {"C2H_INTR_C2H_ST_MSIX_ACK_RSVD_1",
- C2H_INTR_C2H_ST_MSIX_ACK_RSVD_1_MASK},
- {"C2H_INTR_C2H_ST_MSIX_ACK_CNT",
- C2H_INTR_C2H_ST_MSIX_ACK_CNT_MASK},
-};
-
-
-static struct regfield_info
- c2h_intr_c2h_st_msix_fail_field_info[] = {
- {"C2H_INTR_C2H_ST_MSIX_FAIL_RSVD_1",
- C2H_INTR_C2H_ST_MSIX_FAIL_RSVD_1_MASK},
- {"C2H_INTR_C2H_ST_MSIX_FAIL_CNT",
- C2H_INTR_C2H_ST_MSIX_FAIL_CNT_MASK},
-};
-
-
-static struct regfield_info
- c2h_intr_c2h_st_no_msix_field_info[] = {
- {"C2H_INTR_C2H_ST_NO_MSIX_RSVD_1",
- C2H_INTR_C2H_ST_NO_MSIX_RSVD_1_MASK},
- {"C2H_INTR_C2H_ST_NO_MSIX_CNT",
- C2H_INTR_C2H_ST_NO_MSIX_CNT_MASK},
-};
-
-
-static struct regfield_info
- c2h_intr_c2h_st_ctxt_inval_field_info[] = {
- {"C2H_INTR_C2H_ST_CTXT_INVAL_RSVD_1",
- C2H_INTR_C2H_ST_CTXT_INVAL_RSVD_1_MASK},
- {"C2H_INTR_C2H_ST_CTXT_INVAL_CNT",
- C2H_INTR_C2H_ST_CTXT_INVAL_CNT_MASK},
-};
-
-
-static struct regfield_info
- c2h_stat_wr_cmp_field_info[] = {
- {"C2H_STAT_WR_CMP_RSVD_1",
- C2H_STAT_WR_CMP_RSVD_1_MASK},
- {"C2H_STAT_WR_CMP_CNT",
- C2H_STAT_WR_CMP_CNT_MASK},
-};
-
-
-static struct regfield_info
- c2h_stat_dbg_dma_eng_4_field_info[] = {
- {"C2H_STAT_DMA_ENG_4_TUSER_FIFO_OUT_VLD",
- C2H_STAT_DMA_ENG_4_TUSER_FIFO_OUT_VLD_MASK},
- {"C2H_STAT_DMA_ENG_4_WRB_FIFO_IN_RDY",
- C2H_STAT_DMA_ENG_4_WRB_FIFO_IN_RDY_MASK},
- {"C2H_STAT_DMA_ENG_4_TUSER_FIFO_IN_CNT",
- C2H_STAT_DMA_ENG_4_TUSER_FIFO_IN_CNT_MASK},
- {"C2H_STAT_DMA_ENG_4_TUSER_FIFO_OUTPUT_CNT",
- C2H_STAT_DMA_ENG_4_TUSER_FIFO_OUTPUT_CNT_MASK},
- {"C2H_STAT_DMA_ENG_4_TUSER_FIFO_OUT_CNT",
- C2H_STAT_DMA_ENG_4_TUSER_FIFO_OUT_CNT_MASK},
-};
-
-
-static struct regfield_info
- c2h_stat_dbg_dma_eng_5_field_info[] = {
- {"C2H_STAT_DMA_ENG_5_RSVD_1",
- C2H_STAT_DMA_ENG_5_RSVD_1_MASK},
- {"C2H_STAT_DMA_ENG_5_TUSER_COMB_OUT_VLD",
- C2H_STAT_DMA_ENG_5_TUSER_COMB_OUT_VLD_MASK},
- {"C2H_STAT_DMA_ENG_5_TUSER_FIFO_IN_RDY",
- C2H_STAT_DMA_ENG_5_TUSER_FIFO_IN_RDY_MASK},
- {"C2H_STAT_DMA_ENG_5_TUSER_COMB_IN_CNT",
- C2H_STAT_DMA_ENG_5_TUSER_COMB_IN_CNT_MASK},
- {"C2H_STAT_DMA_ENG_5_TUSE_COMB_OUTPUT_CNT",
- C2H_STAT_DMA_ENG_5_TUSE_COMB_OUTPUT_CNT_MASK},
- {"C2H_STAT_DMA_ENG_5_TUSER_COMB_CNT",
- C2H_STAT_DMA_ENG_5_TUSER_COMB_CNT_MASK},
-};
-
-
-static struct regfield_info
- c2h_dbg_pfch_qid_field_info[] = {
- {"C2H_PFCH_QID_RSVD_1",
- C2H_PFCH_QID_RSVD_1_MASK},
- {"C2H_PFCH_QID_ERR_CTXT",
- C2H_PFCH_QID_ERR_CTXT_MASK},
- {"C2H_PFCH_QID_TARGET",
- C2H_PFCH_QID_TARGET_MASK},
- {"C2H_PFCH_QID_QID_OR_TAG",
- C2H_PFCH_QID_QID_OR_TAG_MASK},
-};
-
-
-static struct regfield_info
- c2h_dbg_pfch_field_info[] = {
- {"C2H_PFCH_DATA",
- C2H_PFCH_DATA_MASK},
-};
-
-
-static struct regfield_info
- c2h_int_dbg_field_info[] = {
- {"C2H_INT_RSVD_1",
- C2H_INT_RSVD_1_MASK},
- {"C2H_INT_INT_COAL_SM",
- C2H_INT_INT_COAL_SM_MASK},
- {"C2H_INT_INT_SM",
- C2H_INT_INT_SM_MASK},
-};
-
-
-static struct regfield_info
- c2h_stat_imm_accepted_field_info[] = {
- {"C2H_STAT_IMM_ACCEPTED_RSVD_1",
- C2H_STAT_IMM_ACCEPTED_RSVD_1_MASK},
- {"C2H_STAT_IMM_ACCEPTED_CNT",
- C2H_STAT_IMM_ACCEPTED_CNT_MASK},
-};
-
-
-static struct regfield_info
- c2h_stat_marker_accepted_field_info[] = {
- {"C2H_STAT_MARKER_ACCEPTED_RSVD_1",
- C2H_STAT_MARKER_ACCEPTED_RSVD_1_MASK},
- {"C2H_STAT_MARKER_ACCEPTED_CNT",
- C2H_STAT_MARKER_ACCEPTED_CNT_MASK},
-};
-
-
-static struct regfield_info
- c2h_stat_disable_cmp_accepted_field_info[] = {
- {"C2H_STAT_DISABLE_CMP_ACCEPTED_RSVD_1",
- C2H_STAT_DISABLE_CMP_ACCEPTED_RSVD_1_MASK},
- {"C2H_STAT_DISABLE_CMP_ACCEPTED_CNT",
- C2H_STAT_DISABLE_CMP_ACCEPTED_CNT_MASK},
-};
-
-
-static struct regfield_info
- c2h_pld_fifo_crdt_cnt_field_info[] = {
- {"C2H_PLD_FIFO_CRDT_CNT_RSVD_1",
- C2H_PLD_FIFO_CRDT_CNT_RSVD_1_MASK},
- {"C2H_PLD_FIFO_CRDT_CNT_CNT",
- C2H_PLD_FIFO_CRDT_CNT_CNT_MASK},
-};
-
-
-static struct regfield_info
- h2c_err_stat_field_info[] = {
- {"H2C_ERR_STAT_RSVD_1",
- H2C_ERR_STAT_RSVD_1_MASK},
- {"H2C_ERR_STAT_SBE",
- H2C_ERR_STAT_SBE_MASK},
- {"H2C_ERR_STAT_DBE",
- H2C_ERR_STAT_DBE_MASK},
- {"H2C_ERR_STAT_NO_DMA_DS",
- H2C_ERR_STAT_NO_DMA_DS_MASK},
- {"H2C_ERR_STAT_SDI_MRKR_REQ_MOP_ERR",
- H2C_ERR_STAT_SDI_MRKR_REQ_MOP_ERR_MASK},
- {"H2C_ERR_STAT_ZERO_LEN_DS",
- H2C_ERR_STAT_ZERO_LEN_DS_MASK},
-};
-
-
-static struct regfield_info
- h2c_err_mask_field_info[] = {
- {"H2C_ERR_EN",
- H2C_ERR_EN_MASK},
-};
-
-
-static struct regfield_info
- h2c_first_err_qid_field_info[] = {
- {"H2C_FIRST_ERR_QID_RSVD_1",
- H2C_FIRST_ERR_QID_RSVD_1_MASK},
- {"H2C_FIRST_ERR_QID_ERR_TYPE",
- H2C_FIRST_ERR_QID_ERR_TYPE_MASK},
- {"H2C_FIRST_ERR_QID_RSVD_2",
- H2C_FIRST_ERR_QID_RSVD_2_MASK},
- {"H2C_FIRST_ERR_QID_QID",
- H2C_FIRST_ERR_QID_QID_MASK},
-};
-
-
-static struct regfield_info
- h2c_dbg_reg0_field_info[] = {
- {"H2C_REG0_NUM_DSC_RCVD",
- H2C_REG0_NUM_DSC_RCVD_MASK},
- {"H2C_REG0_NUM_WRB_SENT",
- H2C_REG0_NUM_WRB_SENT_MASK},
-};
-
-
-static struct regfield_info
- h2c_dbg_reg1_field_info[] = {
- {"H2C_REG1_NUM_REQ_SENT",
- H2C_REG1_NUM_REQ_SENT_MASK},
- {"H2C_REG1_NUM_CMP_SENT",
- H2C_REG1_NUM_CMP_SENT_MASK},
-};
-
-
-static struct regfield_info
- h2c_dbg_reg2_field_info[] = {
- {"H2C_REG2_RSVD_1",
- H2C_REG2_RSVD_1_MASK},
- {"H2C_REG2_NUM_ERR_DSC_RCVD",
- H2C_REG2_NUM_ERR_DSC_RCVD_MASK},
-};
-
-
-static struct regfield_info
- h2c_dbg_reg3_field_info[] = {
- {"H2C_REG3",
- H2C_REG3_MASK},
- {"H2C_REG3_DSCO_FIFO_EMPTY",
- H2C_REG3_DSCO_FIFO_EMPTY_MASK},
- {"H2C_REG3_DSCO_FIFO_FULL",
- H2C_REG3_DSCO_FIFO_FULL_MASK},
- {"H2C_REG3_CUR_RC_STATE",
- H2C_REG3_CUR_RC_STATE_MASK},
- {"H2C_REG3_RDREQ_LINES",
- H2C_REG3_RDREQ_LINES_MASK},
- {"H2C_REG3_RDATA_LINES_AVAIL",
- H2C_REG3_RDATA_LINES_AVAIL_MASK},
- {"H2C_REG3_PEND_FIFO_EMPTY",
- H2C_REG3_PEND_FIFO_EMPTY_MASK},
- {"H2C_REG3_PEND_FIFO_FULL",
- H2C_REG3_PEND_FIFO_FULL_MASK},
- {"H2C_REG3_CUR_RQ_STATE",
- H2C_REG3_CUR_RQ_STATE_MASK},
- {"H2C_REG3_DSCI_FIFO_FULL",
- H2C_REG3_DSCI_FIFO_FULL_MASK},
- {"H2C_REG3_DSCI_FIFO_EMPTY",
- H2C_REG3_DSCI_FIFO_EMPTY_MASK},
-};
-
-
-static struct regfield_info
- h2c_dbg_reg4_field_info[] = {
- {"H2C_REG4_RDREQ_ADDR",
- H2C_REG4_RDREQ_ADDR_MASK},
-};
-
-
-static struct regfield_info
- h2c_fatal_err_en_field_info[] = {
- {"H2C_FATAL_ERR_EN_RSVD_1",
- H2C_FATAL_ERR_EN_RSVD_1_MASK},
- {"H2C_FATAL_ERR_EN_H2C",
- H2C_FATAL_ERR_EN_H2C_MASK},
-};
-
-
-static struct regfield_info
- c2h_channel_ctl_field_info[] = {
- {"C2H_CHANNEL_CTL_RSVD_1",
- C2H_CHANNEL_CTL_RSVD_1_MASK},
- {"C2H_CHANNEL_CTL_RUN",
- C2H_CHANNEL_CTL_RUN_MASK},
-};
-
-
-static struct regfield_info
- c2h_channel_ctl_1_field_info[] = {
- {"C2H_CHANNEL_CTL_1_RUN",
- C2H_CHANNEL_CTL_1_RUN_MASK},
- {"C2H_CHANNEL_CTL_1_RUN_1",
- C2H_CHANNEL_CTL_1_RUN_1_MASK},
-};
-
-
-static struct regfield_info
- c2h_mm_status_field_info[] = {
- {"C2H_MM_STATUS_RSVD_1",
- C2H_MM_STATUS_RSVD_1_MASK},
- {"C2H_MM_STATUS_RUN",
- C2H_MM_STATUS_RUN_MASK},
-};
-
-
-static struct regfield_info
- c2h_channel_cmpl_desc_cnt_field_info[] = {
- {"C2H_CHANNEL_CMPL_DESC_CNT_C2H_CO",
- C2H_CHANNEL_CMPL_DESC_CNT_C2H_CO_MASK},
-};
-
-
-static struct regfield_info
- c2h_mm_err_code_enable_mask_field_info[] = {
- {"C2H_MM_ERR_CODE_ENABLE_RSVD_1",
- C2H_MM_ERR_CODE_ENABLE_RSVD_1_MASK},
- {"C2H_MM_ERR_CODE_ENABLE_WR_UC_RAM",
- C2H_MM_ERR_CODE_ENABLE_WR_UC_RAM_MASK},
- {"C2H_MM_ERR_CODE_ENABLE_WR_UR",
- C2H_MM_ERR_CODE_ENABLE_WR_UR_MASK},
- {"C2H_MM_ERR_CODE_ENABLE_WR_FLR",
- C2H_MM_ERR_CODE_ENABLE_WR_FLR_MASK},
- {"C2H_MM_ERR_CODE_ENABLE_RSVD_2",
- C2H_MM_ERR_CODE_ENABLE_RSVD_2_MASK},
- {"C2H_MM_ERR_CODE_ENABLE_RD_SLV_ERR",
- C2H_MM_ERR_CODE_ENABLE_RD_SLV_ERR_MASK},
- {"C2H_MM_ERR_CODE_ENABLE_WR_SLV_ERR",
- C2H_MM_ERR_CODE_ENABLE_WR_SLV_ERR_MASK},
-};
-
-
-static struct regfield_info
- c2h_mm_err_code_field_info[] = {
- {"C2H_MM_ERR_CODE_RSVD_1",
- C2H_MM_ERR_CODE_RSVD_1_MASK},
- {"C2H_MM_ERR_CODE_VALID",
- C2H_MM_ERR_CODE_VALID_MASK},
- {"C2H_MM_ERR_CODE_RDWR",
- C2H_MM_ERR_CODE_RDWR_MASK},
- {"C2H_MM_ERR_CODE",
- C2H_MM_ERR_CODE_MASK},
-};
-
-
-static struct regfield_info
- c2h_mm_err_info_field_info[] = {
- {"C2H_MM_ERR_INFO_RSVD_1",
- C2H_MM_ERR_INFO_RSVD_1_MASK},
- {"C2H_MM_ERR_INFO_QID",
- C2H_MM_ERR_INFO_QID_MASK},
- {"C2H_MM_ERR_INFO_DIR",
- C2H_MM_ERR_INFO_DIR_MASK},
- {"C2H_MM_ERR_INFO_CIDX",
- C2H_MM_ERR_INFO_CIDX_MASK},
-};
-
-
-static struct regfield_info
- c2h_mm_perf_mon_ctl_field_info[] = {
- {"C2H_MM_PERF_MON_CTL_RSVD_1",
- C2H_MM_PERF_MON_CTL_RSVD_1_MASK},
- {"C2H_MM_PERF_MON_CTL_IMM_START",
- C2H_MM_PERF_MON_CTL_IMM_START_MASK},
- {"C2H_MM_PERF_MON_CTL_RUN_START",
- C2H_MM_PERF_MON_CTL_RUN_START_MASK},
- {"C2H_MM_PERF_MON_CTL_IMM_CLEAR",
- C2H_MM_PERF_MON_CTL_IMM_CLEAR_MASK},
- {"C2H_MM_PERF_MON_CTL_RUN_CLEAR",
- C2H_MM_PERF_MON_CTL_RUN_CLEAR_MASK},
-};
-
-
-static struct regfield_info
- c2h_mm_perf_mon_cycle_cnt0_field_info[] = {
- {"C2H_MM_PERF_MON_CYCLE_CNT0_CYC_CNT",
- C2H_MM_PERF_MON_CYCLE_CNT0_CYC_CNT_MASK},
-};
-
-
-static struct regfield_info
- c2h_mm_perf_mon_cycle_cnt1_field_info[] = {
- {"C2H_MM_PERF_MON_CYCLE_CNT1_RSVD_1",
- C2H_MM_PERF_MON_CYCLE_CNT1_RSVD_1_MASK},
- {"C2H_MM_PERF_MON_CYCLE_CNT1_CYC_CNT",
- C2H_MM_PERF_MON_CYCLE_CNT1_CYC_CNT_MASK},
-};
-
-
-static struct regfield_info
- c2h_mm_perf_mon_data_cnt0_field_info[] = {
- {"C2H_MM_PERF_MON_DATA_CNT0_DCNT",
- C2H_MM_PERF_MON_DATA_CNT0_DCNT_MASK},
-};
-
-
-static struct regfield_info
- c2h_mm_perf_mon_data_cnt1_field_info[] = {
- {"C2H_MM_PERF_MON_DATA_CNT1_RSVD_1",
- C2H_MM_PERF_MON_DATA_CNT1_RSVD_1_MASK},
- {"C2H_MM_PERF_MON_DATA_CNT1_DCNT",
- C2H_MM_PERF_MON_DATA_CNT1_DCNT_MASK},
-};
-
-
-static struct regfield_info
- c2h_mm_dbg_field_info[] = {
- {"C2H_MM_RSVD_1",
- C2H_MM_RSVD_1_MASK},
- {"C2H_MM_RRQ_ENTRIES",
- C2H_MM_RRQ_ENTRIES_MASK},
- {"C2H_MM_DAT_FIFO_SPC",
- C2H_MM_DAT_FIFO_SPC_MASK},
- {"C2H_MM_RD_STALL",
- C2H_MM_RD_STALL_MASK},
- {"C2H_MM_RRQ_FIFO_FI",
- C2H_MM_RRQ_FIFO_FI_MASK},
- {"C2H_MM_WR_STALL",
- C2H_MM_WR_STALL_MASK},
- {"C2H_MM_WRQ_FIFO_FI",
- C2H_MM_WRQ_FIFO_FI_MASK},
- {"C2H_MM_WBK_STALL",
- C2H_MM_WBK_STALL_MASK},
- {"C2H_MM_DSC_FIFO_EP",
- C2H_MM_DSC_FIFO_EP_MASK},
- {"C2H_MM_DSC_FIFO_FL",
- C2H_MM_DSC_FIFO_FL_MASK},
-};
-
-
-static struct regfield_info
- h2c_channel_ctl_field_info[] = {
- {"H2C_CHANNEL_CTL_RSVD_1",
- H2C_CHANNEL_CTL_RSVD_1_MASK},
- {"H2C_CHANNEL_CTL_RUN",
- H2C_CHANNEL_CTL_RUN_MASK},
-};
-
-
-static struct regfield_info
- h2c_channel_ctl_1_field_info[] = {
- {"H2C_CHANNEL_CTL_1_RUN",
- H2C_CHANNEL_CTL_1_RUN_MASK},
-};
-
-
-static struct regfield_info
- h2c_channel_ctl_2_field_info[] = {
- {"H2C_CHANNEL_CTL_2_RUN",
- H2C_CHANNEL_CTL_2_RUN_MASK},
-};
-
-
-static struct regfield_info
- h2c_mm_status_field_info[] = {
- {"H2C_MM_STATUS_RSVD_1",
- H2C_MM_STATUS_RSVD_1_MASK},
- {"H2C_MM_STATUS_RUN",
- H2C_MM_STATUS_RUN_MASK},
-};
-
-
-static struct regfield_info
- h2c_channel_cmpl_desc_cnt_field_info[] = {
- {"H2C_CHANNEL_CMPL_DESC_CNT_H2C_CO",
- H2C_CHANNEL_CMPL_DESC_CNT_H2C_CO_MASK},
-};
-
-
-static struct regfield_info
- h2c_mm_err_code_enable_mask_field_info[] = {
- {"H2C_MM_ERR_CODE_ENABLE_RSVD_1",
- H2C_MM_ERR_CODE_ENABLE_RSVD_1_MASK},
- {"H2C_MM_ERR_CODE_ENABLE_WR_SLV_ERR",
- H2C_MM_ERR_CODE_ENABLE_WR_SLV_ERR_MASK},
- {"H2C_MM_ERR_CODE_ENABLE_WR_DEC_ERR",
- H2C_MM_ERR_CODE_ENABLE_WR_DEC_ERR_MASK},
- {"H2C_MM_ERR_CODE_ENABLE_RSVD_2",
- H2C_MM_ERR_CODE_ENABLE_RSVD_2_MASK},
- {"H2C_MM_ERR_CODE_ENABLE_RD_RQ_DIS_ERR",
- H2C_MM_ERR_CODE_ENABLE_RD_RQ_DIS_ERR_MASK},
- {"H2C_MM_ERR_CODE_ENABLE_RSVD_3",
- H2C_MM_ERR_CODE_ENABLE_RSVD_3_MASK},
- {"H2C_MM_ERR_CODE_ENABLE_RD_DAT_POISON_ERR",
- H2C_MM_ERR_CODE_ENABLE_RD_DAT_POISON_ERR_MASK},
- {"H2C_MM_ERR_CODE_ENABLE_RSVD_4",
- H2C_MM_ERR_CODE_ENABLE_RSVD_4_MASK},
- {"H2C_MM_ERR_CODE_ENABLE_RD_FLR_ERR",
- H2C_MM_ERR_CODE_ENABLE_RD_FLR_ERR_MASK},
- {"H2C_MM_ERR_CODE_ENABLE_RSVD_5",
- H2C_MM_ERR_CODE_ENABLE_RSVD_5_MASK},
- {"H2C_MM_ERR_CODE_ENABLE_RD_HDR_ADR_ERR",
- H2C_MM_ERR_CODE_ENABLE_RD_HDR_ADR_ERR_MASK},
- {"H2C_MM_ERR_CODE_ENABLE_RD_HDR_PARA",
- H2C_MM_ERR_CODE_ENABLE_RD_HDR_PARA_MASK},
- {"H2C_MM_ERR_CODE_ENABLE_RD_HDR_BYTE_ERR",
- H2C_MM_ERR_CODE_ENABLE_RD_HDR_BYTE_ERR_MASK},
- {"H2C_MM_ERR_CODE_ENABLE_RD_UR_CA",
- H2C_MM_ERR_CODE_ENABLE_RD_UR_CA_MASK},
- {"H2C_MM_ERR_CODE_ENABLE_RD_HRD_POISON_ERR",
- H2C_MM_ERR_CODE_ENABLE_RD_HRD_POISON_ERR_MASK},
- {"H2C_MM_ERR_CODE_ENABLE_RSVD_6",
- H2C_MM_ERR_CODE_ENABLE_RSVD_6_MASK},
-};
-
-
-static struct regfield_info
- h2c_mm_err_code_field_info[] = {
- {"H2C_MM_ERR_CODE_RSVD_1",
- H2C_MM_ERR_CODE_RSVD_1_MASK},
- {"H2C_MM_ERR_CODE_VALID",
- H2C_MM_ERR_CODE_VALID_MASK},
- {"H2C_MM_ERR_CODE_RDWR",
- H2C_MM_ERR_CODE_RDWR_MASK},
- {"H2C_MM_ERR_CODE",
- H2C_MM_ERR_CODE_MASK},
-};
-
-
-static struct regfield_info
- h2c_mm_err_info_field_info[] = {
- {"H2C_MM_ERR_INFO_RSVD_1",
- H2C_MM_ERR_INFO_RSVD_1_MASK},
- {"H2C_MM_ERR_INFO_QID",
- H2C_MM_ERR_INFO_QID_MASK},
- {"H2C_MM_ERR_INFO_DIR",
- H2C_MM_ERR_INFO_DIR_MASK},
- {"H2C_MM_ERR_INFO_CIDX",
- H2C_MM_ERR_INFO_CIDX_MASK},
-};
-
-
-static struct regfield_info
- h2c_mm_perf_mon_ctl_field_info[] = {
- {"H2C_MM_PERF_MON_CTL_RSVD_1",
- H2C_MM_PERF_MON_CTL_RSVD_1_MASK},
- {"H2C_MM_PERF_MON_CTL_IMM_START",
- H2C_MM_PERF_MON_CTL_IMM_START_MASK},
- {"H2C_MM_PERF_MON_CTL_RUN_START",
- H2C_MM_PERF_MON_CTL_RUN_START_MASK},
- {"H2C_MM_PERF_MON_CTL_IMM_CLEAR",
- H2C_MM_PERF_MON_CTL_IMM_CLEAR_MASK},
- {"H2C_MM_PERF_MON_CTL_RUN_CLEAR",
- H2C_MM_PERF_MON_CTL_RUN_CLEAR_MASK},
-};
-
-
-static struct regfield_info
- h2c_mm_perf_mon_cycle_cnt0_field_info[] = {
- {"H2C_MM_PERF_MON_CYCLE_CNT0_CYC_CNT",
- H2C_MM_PERF_MON_CYCLE_CNT0_CYC_CNT_MASK},
-};
-
-
-static struct regfield_info
- h2c_mm_perf_mon_cycle_cnt1_field_info[] = {
- {"H2C_MM_PERF_MON_CYCLE_CNT1_RSVD_1",
- H2C_MM_PERF_MON_CYCLE_CNT1_RSVD_1_MASK},
- {"H2C_MM_PERF_MON_CYCLE_CNT1_CYC_CNT",
- H2C_MM_PERF_MON_CYCLE_CNT1_CYC_CNT_MASK},
-};
-
-
-static struct regfield_info
- h2c_mm_perf_mon_data_cnt0_field_info[] = {
- {"H2C_MM_PERF_MON_DATA_CNT0_DCNT",
- H2C_MM_PERF_MON_DATA_CNT0_DCNT_MASK},
-};
-
-
-static struct regfield_info
- h2c_mm_perf_mon_data_cnt1_field_info[] = {
- {"H2C_MM_PERF_MON_DATA_CNT1_RSVD_1",
- H2C_MM_PERF_MON_DATA_CNT1_RSVD_1_MASK},
- {"H2C_MM_PERF_MON_DATA_CNT1_DCNT",
- H2C_MM_PERF_MON_DATA_CNT1_DCNT_MASK},
-};
-
-
-static struct regfield_info
- h2c_mm_dbg_field_info[] = {
- {"H2C_MM_RSVD_1",
- H2C_MM_RSVD_1_MASK},
- {"H2C_MM_RRQ_ENTRIES",
- H2C_MM_RRQ_ENTRIES_MASK},
- {"H2C_MM_DAT_FIFO_SPC",
- H2C_MM_DAT_FIFO_SPC_MASK},
- {"H2C_MM_RD_STALL",
- H2C_MM_RD_STALL_MASK},
- {"H2C_MM_RRQ_FIFO_FI",
- H2C_MM_RRQ_FIFO_FI_MASK},
- {"H2C_MM_WR_STALL",
- H2C_MM_WR_STALL_MASK},
- {"H2C_MM_WRQ_FIFO_FI",
- H2C_MM_WRQ_FIFO_FI_MASK},
- {"H2C_MM_WBK_STALL",
- H2C_MM_WBK_STALL_MASK},
- {"H2C_MM_DSC_FIFO_EP",
- H2C_MM_DSC_FIFO_EP_MASK},
- {"H2C_MM_DSC_FIFO_FL",
- H2C_MM_DSC_FIFO_FL_MASK},
-};
-
-
-static struct regfield_info
- func_status_reg_field_info[] = {
- {"FUNC_STATUS_REG_RSVD_1",
- FUNC_STATUS_REG_RSVD_1_MASK},
- {"FUNC_STATUS_REG_CUR_SRC_FN",
- FUNC_STATUS_REG_CUR_SRC_FN_MASK},
- {"FUNC_STATUS_REG_ACK",
- FUNC_STATUS_REG_ACK_MASK},
- {"FUNC_STATUS_REG_O_MSG",
- FUNC_STATUS_REG_O_MSG_MASK},
- {"FUNC_STATUS_REG_I_MSG",
- FUNC_STATUS_REG_I_MSG_MASK},
-};
-
-
-static struct regfield_info
- func_cmd_reg_field_info[] = {
- {"FUNC_CMD_REG_RSVD_1",
- FUNC_CMD_REG_RSVD_1_MASK},
- {"FUNC_CMD_REG_RSVD_2",
- FUNC_CMD_REG_RSVD_2_MASK},
- {"FUNC_CMD_REG_MSG_RCV",
- FUNC_CMD_REG_MSG_RCV_MASK},
- {"FUNC_CMD_REG_MSG_SENT",
- FUNC_CMD_REG_MSG_SENT_MASK},
-};
-
-
-static struct regfield_info
- func_interrupt_vector_reg_field_info[] = {
- {"FUNC_INTERRUPT_VECTOR_REG_RSVD_1",
- FUNC_INTERRUPT_VECTOR_REG_RSVD_1_MASK},
- {"FUNC_INTERRUPT_VECTOR_REG_IN",
- FUNC_INTERRUPT_VECTOR_REG_IN_MASK},
-};
-
-
-static struct regfield_info
- target_func_reg_field_info[] = {
- {"TARGET_FUNC_REG_RSVD_1",
- TARGET_FUNC_REG_RSVD_1_MASK},
- {"TARGET_FUNC_REG_N_ID",
- TARGET_FUNC_REG_N_ID_MASK},
-};
-
-
-static struct regfield_info
- func_interrupt_ctl_reg_field_info[] = {
- {"FUNC_INTERRUPT_CTL_REG_RSVD_1",
- FUNC_INTERRUPT_CTL_REG_RSVD_1_MASK},
- {"FUNC_INTERRUPT_CTL_REG_INT_EN",
- FUNC_INTERRUPT_CTL_REG_INT_EN_MASK},
-};
-
-static struct xreg_info qdma_s80_hard_config_regs[] = {
-{"CFG_BLK_IDENTIFIER", 0x00,
- 1, 0, 0, 0,
- 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY,
- ARRAY_SIZE(cfg_blk_identifier_field_info),
- cfg_blk_identifier_field_info
-},
-{"CFG_BLK_BUSDEV", 0x04,
- 1, 0, 0, 0,
- 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY,
- ARRAY_SIZE(cfg_blk_busdev_field_info),
- cfg_blk_busdev_field_info
-},
-{"CFG_BLK_PCIE_MAX_PLD_SIZE", 0x08,
- 1, 0, 0, 0,
- 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY,
- ARRAY_SIZE(cfg_blk_pcie_max_pld_size_field_info),
- cfg_blk_pcie_max_pld_size_field_info
-},
-{"CFG_BLK_PCIE_MAX_READ_REQ_SIZE", 0x0c,
- 1, 0, 0, 0,
- 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY,
- ARRAY_SIZE(cfg_blk_pcie_max_read_req_size_field_info),
- cfg_blk_pcie_max_read_req_size_field_info
-},
-{"CFG_BLK_SYSTEM_ID", 0x10,
- 1, 0, 0, 0,
- 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY,
- ARRAY_SIZE(cfg_blk_system_id_field_info),
- cfg_blk_system_id_field_info
-},
-{"CFG_BLK_MSI_ENABLE", 0x014,
- 1, 0, 0, 0,
- 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY,
- ARRAY_SIZE(cfg_blk_msi_enable_field_info),
- cfg_blk_msi_enable_field_info
-},
-{"CFG_PCIE_DATA_WIDTH", 0x18,
- 1, 0, 0, 0,
- 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY,
- ARRAY_SIZE(cfg_pcie_data_width_field_info),
- cfg_pcie_data_width_field_info
-},
-{"CFG_PCIE_CTL", 0x1c,
- 1, 0, 0, 0,
- 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY,
- ARRAY_SIZE(cfg_pcie_ctl_field_info),
- cfg_pcie_ctl_field_info
-},
-{"CFG_AXI_USER_MAX_PLD_SIZE", 0x40,
- 1, 0, 0, 0,
- 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY,
- ARRAY_SIZE(cfg_axi_user_max_pld_size_field_info),
- cfg_axi_user_max_pld_size_field_info
-},
-{"CFG_AXI_USER_MAX_READ_REQ_SIZE", 0x44,
- 1, 0, 0, 0,
- 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY,
- ARRAY_SIZE(cfg_axi_user_max_read_req_size_field_info),
- cfg_axi_user_max_read_req_size_field_info
-},
-{"CFG_BLK_MISC_CTL", 0x4c,
- 1, 0, 0, 0,
- 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY,
- ARRAY_SIZE(cfg_blk_misc_ctl_field_info),
- cfg_blk_misc_ctl_field_info
-},
-{"CFG_BLK_SCRATCH_0", 0x80,
- 1, 0, 0, 0,
- 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY,
- ARRAY_SIZE(cfg_blk_scratch_0_field_info),
- cfg_blk_scratch_0_field_info
-},
-{"CFG_BLK_SCRATCH_1", 0x84,
- 1, 0, 0, 0,
- 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY,
- ARRAY_SIZE(cfg_blk_scratch_1_field_info),
- cfg_blk_scratch_1_field_info
-},
-{"CFG_BLK_SCRATCH_2", 0x88,
- 1, 0, 0, 0,
- 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY,
- ARRAY_SIZE(cfg_blk_scratch_2_field_info),
- cfg_blk_scratch_2_field_info
-},
-{"CFG_BLK_SCRATCH_3", 0x8c,
- 1, 0, 0, 0,
- 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY,
- ARRAY_SIZE(cfg_blk_scratch_3_field_info),
- cfg_blk_scratch_3_field_info
-},
-{"CFG_BLK_SCRATCH_4", 0x90,
- 1, 0, 0, 0,
- 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY,
- ARRAY_SIZE(cfg_blk_scratch_4_field_info),
- cfg_blk_scratch_4_field_info
-},
-{"CFG_BLK_SCRATCH_5", 0x94,
- 1, 0, 0, 0,
- 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY,
- ARRAY_SIZE(cfg_blk_scratch_5_field_info),
- cfg_blk_scratch_5_field_info
-},
-{"CFG_BLK_SCRATCH_6", 0x98,
- 1, 0, 0, 0,
- 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY,
- ARRAY_SIZE(cfg_blk_scratch_6_field_info),
- cfg_blk_scratch_6_field_info
-},
-{"CFG_BLK_SCRATCH_7", 0x9c,
- 1, 0, 0, 0,
- 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY,
- ARRAY_SIZE(cfg_blk_scratch_7_field_info),
- cfg_blk_scratch_7_field_info
-},
-{"RAM_SBE_MSK_A", 0xf0,
- 1, 0, 0, 0,
- 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY,
- ARRAY_SIZE(ram_sbe_msk_a_field_info),
- ram_sbe_msk_a_field_info
-},
-{"RAM_SBE_STS_A", 0xf4,
- 1, 0, 0, 0,
- 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY,
- ARRAY_SIZE(ram_sbe_sts_a_field_info),
- ram_sbe_sts_a_field_info
-},
-{"RAM_DBE_MSK_A", 0xf8,
- 1, 0, 0, 0,
- 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY,
- ARRAY_SIZE(ram_dbe_msk_a_field_info),
- ram_dbe_msk_a_field_info
-},
-{"RAM_DBE_STS_A", 0xfc,
- 1, 0, 0, 0,
- 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY,
- ARRAY_SIZE(ram_dbe_sts_a_field_info),
- ram_dbe_sts_a_field_info
-},
-{"GLBL2_IDENTIFIER", 0x100,
- 1, 0, 0, 0,
- 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY,
- ARRAY_SIZE(glbl2_identifier_field_info),
- glbl2_identifier_field_info
-},
-{"GLBL2_PF_BARLITE_INT", 0x104,
- 1, 0, 0, 0,
- 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY,
- ARRAY_SIZE(glbl2_pf_barlite_int_field_info),
- glbl2_pf_barlite_int_field_info
-},
-{"GLBL2_PF_VF_BARLITE_INT", 0x108,
- 1, 0, 0, 0,
- 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY,
- ARRAY_SIZE(glbl2_pf_vf_barlite_int_field_info),
- glbl2_pf_vf_barlite_int_field_info
-},
-{"GLBL2_PF_BARLITE_EXT", 0x10c,
- 1, 0, 0, 0,
- 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY,
- ARRAY_SIZE(glbl2_pf_barlite_ext_field_info),
- glbl2_pf_barlite_ext_field_info
-},
-{"GLBL2_PF_VF_BARLITE_EXT", 0x110,
- 1, 0, 0, 0,
- 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY,
- ARRAY_SIZE(glbl2_pf_vf_barlite_ext_field_info),
- glbl2_pf_vf_barlite_ext_field_info
-},
-{"GLBL2_CHANNEL_INST", 0x114,
- 1, 0, 0, 0,
- 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY,
- ARRAY_SIZE(glbl2_channel_inst_field_info),
- glbl2_channel_inst_field_info
-},
-{"GLBL2_CHANNEL_MDMA", 0x118,
- 1, 0, 0, 0,
- 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY,
- ARRAY_SIZE(glbl2_channel_mdma_field_info),
- glbl2_channel_mdma_field_info
-},
-{"GLBL2_CHANNEL_STRM", 0x11c,
- 1, 0, 0, 0,
- 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY,
- ARRAY_SIZE(glbl2_channel_strm_field_info),
- glbl2_channel_strm_field_info
-},
-{"GLBL2_CHANNEL_CAP", 0x120,
- 1, 0, 0, 0,
- 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY,
- ARRAY_SIZE(glbl2_channel_cap_field_info),
- glbl2_channel_cap_field_info
-},
-{"GLBL2_CHANNEL_PASID_CAP", 0x128,
- 1, 0, 0, 0,
- 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY,
- ARRAY_SIZE(glbl2_channel_pasid_cap_field_info),
- glbl2_channel_pasid_cap_field_info
-},
-{"GLBL2_CHANNEL_FUNC_RET", 0x12c,
- 1, 0, 0, 0,
- 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY,
- ARRAY_SIZE(glbl2_channel_func_ret_field_info),
- glbl2_channel_func_ret_field_info
-},
-{"GLBL2_SYSTEM_ID", 0x130,
- 1, 0, 0, 0,
- 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY,
- ARRAY_SIZE(glbl2_system_id_field_info),
- glbl2_system_id_field_info
-},
-{"GLBL2_MISC_CAP", 0x134,
- 1, 0, 0, 0,
- 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY,
- ARRAY_SIZE(glbl2_misc_cap_field_info),
- glbl2_misc_cap_field_info
-},
-{"GLBL2_DBG_PCIE_RQ0", 0x1b8,
- 1, 0, 0, 0,
- 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY,
- ARRAY_SIZE(glbl2_dbg_pcie_rq0_field_info),
- glbl2_dbg_pcie_rq0_field_info
-},
-{"GLBL2_DBG_PCIE_RQ1", 0x1bc,
- 1, 0, 0, 0,
- 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY,
- ARRAY_SIZE(glbl2_dbg_pcie_rq1_field_info),
- glbl2_dbg_pcie_rq1_field_info
-},
-{"GLBL2_DBG_AXIMM_WR0", 0x1c0,
- 1, 0, 0, 0,
- 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY,
- ARRAY_SIZE(glbl2_dbg_aximm_wr0_field_info),
- glbl2_dbg_aximm_wr0_field_info
-},
-{"GLBL2_DBG_AXIMM_WR1", 0x1c4,
- 1, 0, 0, 0,
- 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY,
- ARRAY_SIZE(glbl2_dbg_aximm_wr1_field_info),
- glbl2_dbg_aximm_wr1_field_info
-},
-{"GLBL2_DBG_AXIMM_RD0", 0x1c8,
- 1, 0, 0, 0,
- 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY,
- ARRAY_SIZE(glbl2_dbg_aximm_rd0_field_info),
- glbl2_dbg_aximm_rd0_field_info
-},
-{"GLBL2_DBG_AXIMM_RD1", 0x1cc,
- 1, 0, 0, 0,
- 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY,
- ARRAY_SIZE(glbl2_dbg_aximm_rd1_field_info),
- glbl2_dbg_aximm_rd1_field_info
-},
-{"GLBL_RNG_SZ_1", 0x204,
- 1, 0, 0, 0,
- 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_VF,
- ARRAY_SIZE(glbl_rng_sz_1_field_info),
- glbl_rng_sz_1_field_info
-},
-{"GLBL_RNG_SZ_2", 0x208,
- 1, 0, 0, 0,
- 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_VF,
- ARRAY_SIZE(glbl_rng_sz_2_field_info),
- glbl_rng_sz_2_field_info
-},
-{"GLBL_RNG_SZ_3", 0x20c,
- 1, 0, 0, 0,
- 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_VF,
- ARRAY_SIZE(glbl_rng_sz_3_field_info),
- glbl_rng_sz_3_field_info
-},
-{"GLBL_RNG_SZ_4", 0x210,
- 1, 0, 0, 0,
- 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_VF,
- ARRAY_SIZE(glbl_rng_sz_4_field_info),
- glbl_rng_sz_4_field_info
-},
-{"GLBL_RNG_SZ_5", 0x214,
- 1, 0, 0, 0,
- 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_VF,
- ARRAY_SIZE(glbl_rng_sz_5_field_info),
- glbl_rng_sz_5_field_info
-},
-{"GLBL_RNG_SZ_6", 0x218,
- 1, 0, 0, 0,
- 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_VF,
- ARRAY_SIZE(glbl_rng_sz_6_field_info),
- glbl_rng_sz_6_field_info
-},
-{"GLBL_RNG_SZ_7", 0x21c,
- 1, 0, 0, 0,
- 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_VF,
- ARRAY_SIZE(glbl_rng_sz_7_field_info),
- glbl_rng_sz_7_field_info
-},
-{"GLBL_RNG_SZ_8", 0x220,
- 1, 0, 0, 0,
- 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_VF,
- ARRAY_SIZE(glbl_rng_sz_8_field_info),
- glbl_rng_sz_8_field_info
-},
-{"GLBL_RNG_SZ_9", 0x224,
- 1, 0, 0, 0,
- 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_VF,
- ARRAY_SIZE(glbl_rng_sz_9_field_info),
- glbl_rng_sz_9_field_info
-},
-{"GLBL_RNG_SZ_A", 0x228,
- 1, 0, 0, 0,
- 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_VF,
- ARRAY_SIZE(glbl_rng_sz_a_field_info),
- glbl_rng_sz_a_field_info
-},
-{"GLBL_RNG_SZ_B", 0x22c,
- 1, 0, 0, 0,
- 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_VF,
- ARRAY_SIZE(glbl_rng_sz_b_field_info),
- glbl_rng_sz_b_field_info
-},
-{"GLBL_RNG_SZ_C", 0x230,
- 1, 0, 0, 0,
- 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_VF,
- ARRAY_SIZE(glbl_rng_sz_c_field_info),
- glbl_rng_sz_c_field_info
-},
-{"GLBL_RNG_SZ_D", 0x234,
- 1, 0, 0, 0,
- 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_VF,
- ARRAY_SIZE(glbl_rng_sz_d_field_info),
- glbl_rng_sz_d_field_info
-},
-{"GLBL_RNG_SZ_E", 0x238,
- 1, 0, 0, 0,
- 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_VF,
- ARRAY_SIZE(glbl_rng_sz_e_field_info),
- glbl_rng_sz_e_field_info
-},
-{"GLBL_RNG_SZ_F", 0x23c,
- 1, 0, 0, 0,
- 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_VF,
- ARRAY_SIZE(glbl_rng_sz_f_field_info),
- glbl_rng_sz_f_field_info
-},
-{"GLBL_RNG_SZ_10", 0x240,
- 1, 0, 0, 0,
- 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_VF,
- ARRAY_SIZE(glbl_rng_sz_10_field_info),
- glbl_rng_sz_10_field_info
-},
-{"GLBL_ERR_STAT", 0x248,
- 1, 0, 0, 0,
- 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_VF,
- ARRAY_SIZE(glbl_err_stat_field_info),
- glbl_err_stat_field_info
-},
-{"GLBL_ERR_MASK", 0x24c,
- 1, 0, 0, 0,
- 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_VF,
- ARRAY_SIZE(glbl_err_mask_field_info),
- glbl_err_mask_field_info
-},
-{"GLBL_DSC_CFG", 0x250,
- 1, 0, 0, 0,
- 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_VF,
- ARRAY_SIZE(glbl_dsc_cfg_field_info),
- glbl_dsc_cfg_field_info
-},
-{"GLBL_DSC_ERR_STS", 0x254,
- 1, 0, 0, 0,
- 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_VF,
- ARRAY_SIZE(glbl_dsc_err_sts_field_info),
- glbl_dsc_err_sts_field_info
-},
-{"GLBL_DSC_ERR_MSK", 0x258,
- 1, 0, 0, 0,
- 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_VF,
- ARRAY_SIZE(glbl_dsc_err_msk_field_info),
- glbl_dsc_err_msk_field_info
-},
-{"GLBL_DSC_ERR_LOG0", 0x25c,
- 1, 0, 0, 0,
- 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_VF,
- ARRAY_SIZE(glbl_dsc_err_log0_field_info),
- glbl_dsc_err_log0_field_info
-},
-{"GLBL_DSC_ERR_LOG1", 0x260,
- 1, 0, 0, 0,
- 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_VF,
- ARRAY_SIZE(glbl_dsc_err_log1_field_info),
- glbl_dsc_err_log1_field_info
-},
-{"GLBL_TRQ_ERR_STS", 0x264,
- 1, 0, 0, 0,
- 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_VF,
- ARRAY_SIZE(glbl_trq_err_sts_field_info),
- glbl_trq_err_sts_field_info
-},
-{"GLBL_TRQ_ERR_MSK", 0x268,
- 1, 0, 0, 0,
- 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_VF,
- ARRAY_SIZE(glbl_trq_err_msk_field_info),
- glbl_trq_err_msk_field_info
-},
-{"GLBL_TRQ_ERR_LOG", 0x26c,
- 1, 0, 0, 0,
- 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_VF,
- ARRAY_SIZE(glbl_trq_err_log_field_info),
- glbl_trq_err_log_field_info
-},
-{"GLBL_DSC_DBG_DAT0", 0x270,
- 1, 0, 0, 0,
- 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_VF,
- ARRAY_SIZE(glbl_dsc_dbg_dat0_field_info),
- glbl_dsc_dbg_dat0_field_info
-},
-{"GLBL_DSC_DBG_DAT1", 0x274,
- 1, 0, 0, 0,
- 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_VF,
- ARRAY_SIZE(glbl_dsc_dbg_dat1_field_info),
- glbl_dsc_dbg_dat1_field_info
-},
-{"TRQ_SEL_FMAP_0", 0x400,
- 1, 0, 0, 0,
- 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY,
- ARRAY_SIZE(trq_sel_fmap_0_field_info),
- trq_sel_fmap_0_field_info
-},
-{"TRQ_SEL_FMAP_1", 0x404,
- 1, 0, 0, 0,
- 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY,
- ARRAY_SIZE(trq_sel_fmap_1_field_info),
- trq_sel_fmap_1_field_info
-},
-{"TRQ_SEL_FMAP_2", 0x408,
- 1, 0, 0, 0,
- 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY,
- ARRAY_SIZE(trq_sel_fmap_2_field_info),
- trq_sel_fmap_2_field_info
-},
-{"TRQ_SEL_FMAP_3", 0x40c,
- 1, 0, 0, 0,
- 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY,
- ARRAY_SIZE(trq_sel_fmap_3_field_info),
- trq_sel_fmap_3_field_info
-},
-{"TRQ_SEL_FMAP_4", 0x410,
- 1, 0, 0, 0,
- 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY,
- ARRAY_SIZE(trq_sel_fmap_4_field_info),
- trq_sel_fmap_4_field_info
-},
-{"TRQ_SEL_FMAP_5", 0x414,
- 1, 0, 0, 0,
- 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY,
- ARRAY_SIZE(trq_sel_fmap_5_field_info),
- trq_sel_fmap_5_field_info
-},
-{"TRQ_SEL_FMAP_6", 0x418,
- 1, 0, 0, 0,
- 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY,
- ARRAY_SIZE(trq_sel_fmap_6_field_info),
- trq_sel_fmap_6_field_info
-},
-{"TRQ_SEL_FMAP_7", 0x41c,
- 1, 0, 0, 0,
- 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY,
- ARRAY_SIZE(trq_sel_fmap_7_field_info),
- trq_sel_fmap_7_field_info
-},
-{"TRQ_SEL_FMAP_8", 0x420,
- 1, 0, 0, 0,
- 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY,
- ARRAY_SIZE(trq_sel_fmap_8_field_info),
- trq_sel_fmap_8_field_info
-},
-{"TRQ_SEL_FMAP_9", 0x424,
- 1, 0, 0, 0,
- 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY,
- ARRAY_SIZE(trq_sel_fmap_9_field_info),
- trq_sel_fmap_9_field_info
-},
-{"TRQ_SEL_FMAP_A", 0x428,
- 1, 0, 0, 0,
- 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY,
- ARRAY_SIZE(trq_sel_fmap_a_field_info),
- trq_sel_fmap_a_field_info
-},
-{"TRQ_SEL_FMAP_B", 0x42c,
- 1, 0, 0, 0,
- 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY,
- ARRAY_SIZE(trq_sel_fmap_b_field_info),
- trq_sel_fmap_b_field_info
-},
-{"TRQ_SEL_FMAP_D", 0x430,
- 1, 0, 0, 0,
- 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY,
- ARRAY_SIZE(trq_sel_fmap_d_field_info),
- trq_sel_fmap_d_field_info
-},
-{"TRQ_SEL_FMAP_E", 0x434,
- 1, 0, 0, 0,
- 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY,
- ARRAY_SIZE(trq_sel_fmap_e_field_info),
- trq_sel_fmap_e_field_info
-},
-{"TRQ_SEL_FMAP_F", 0x438,
- 1, 0, 0, 0,
- 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY,
- ARRAY_SIZE(trq_sel_fmap_f_field_info),
- trq_sel_fmap_f_field_info
-},
-{"TRQ_SEL_FMAP_10", 0x43c,
- 1, 0, 0, 0,
- 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY,
- ARRAY_SIZE(trq_sel_fmap_10_field_info),
- trq_sel_fmap_10_field_info
-},
-{"TRQ_SEL_FMAP_11", 0x440,
- 1, 0, 0, 0,
- 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY,
- ARRAY_SIZE(trq_sel_fmap_11_field_info),
- trq_sel_fmap_11_field_info
-},
-{"TRQ_SEL_FMAP_12", 0x444,
- 1, 0, 0, 0,
- 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY,
- ARRAY_SIZE(trq_sel_fmap_12_field_info),
- trq_sel_fmap_12_field_info
-},
-{"TRQ_SEL_FMAP_13", 0x448,
- 1, 0, 0, 0,
- 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY,
- ARRAY_SIZE(trq_sel_fmap_13_field_info),
- trq_sel_fmap_13_field_info
-},
-{"TRQ_SEL_FMAP_14", 0x44c,
- 1, 0, 0, 0,
- 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY,
- ARRAY_SIZE(trq_sel_fmap_14_field_info),
- trq_sel_fmap_14_field_info
-},
-{"TRQ_SEL_FMAP_15", 0x450,
- 1, 0, 0, 0,
- 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY,
- ARRAY_SIZE(trq_sel_fmap_15_field_info),
- trq_sel_fmap_15_field_info
-},
-{"TRQ_SEL_FMAP_16", 0x454,
- 1, 0, 0, 0,
- 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY,
- ARRAY_SIZE(trq_sel_fmap_16_field_info),
- trq_sel_fmap_16_field_info
-},
-{"TRQ_SEL_FMAP_17", 0x458,
- 1, 0, 0, 0,
- 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY,
- ARRAY_SIZE(trq_sel_fmap_17_field_info),
- trq_sel_fmap_17_field_info
-},
-{"TRQ_SEL_FMAP_18", 0x45c,
- 1, 0, 0, 0,
- 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY,
- ARRAY_SIZE(trq_sel_fmap_18_field_info),
- trq_sel_fmap_18_field_info
-},
-{"TRQ_SEL_FMAP_19", 0x460,
- 1, 0, 0, 0,
- 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY,
- ARRAY_SIZE(trq_sel_fmap_19_field_info),
- trq_sel_fmap_19_field_info
-},
-{"TRQ_SEL_FMAP_1A", 0x464,
- 1, 0, 0, 0,
- 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY,
- ARRAY_SIZE(trq_sel_fmap_1a_field_info),
- trq_sel_fmap_1a_field_info
-},
-{"TRQ_SEL_FMAP_1B", 0x468,
- 1, 0, 0, 0,
- 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY,
- ARRAY_SIZE(trq_sel_fmap_1b_field_info),
- trq_sel_fmap_1b_field_info
-},
-{"TRQ_SEL_FMAP_1C", 0x46c,
- 1, 0, 0, 0,
- 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY,
- ARRAY_SIZE(trq_sel_fmap_1c_field_info),
- trq_sel_fmap_1c_field_info
-},
-{"TRQ_SEL_FMAP_1D", 0x470,
- 1, 0, 0, 0,
- 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY,
- ARRAY_SIZE(trq_sel_fmap_1d_field_info),
- trq_sel_fmap_1d_field_info
-},
-{"TRQ_SEL_FMAP_1E", 0x474,
- 1, 0, 0, 0,
- 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY,
- ARRAY_SIZE(trq_sel_fmap_1e_field_info),
- trq_sel_fmap_1e_field_info
-},
-{"TRQ_SEL_FMAP_1F", 0x478,
- 1, 0, 0, 0,
- 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY,
- ARRAY_SIZE(trq_sel_fmap_1f_field_info),
- trq_sel_fmap_1f_field_info
-},
-{"TRQ_SEL_FMAP_20", 0x47c,
- 1, 0, 0, 0,
- 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY,
- ARRAY_SIZE(trq_sel_fmap_20_field_info),
- trq_sel_fmap_20_field_info
-},
-{"TRQ_SEL_FMAP_21", 0x480,
- 1, 0, 0, 0,
- 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY,
- ARRAY_SIZE(trq_sel_fmap_21_field_info),
- trq_sel_fmap_21_field_info
-},
-{"TRQ_SEL_FMAP_22", 0x484,
- 1, 0, 0, 0,
- 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY,
- ARRAY_SIZE(trq_sel_fmap_22_field_info),
- trq_sel_fmap_22_field_info
-},
-{"TRQ_SEL_FMAP_23", 0x488,
- 1, 0, 0, 0,
- 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY,
- ARRAY_SIZE(trq_sel_fmap_23_field_info),
- trq_sel_fmap_23_field_info
-},
-{"TRQ_SEL_FMAP_24", 0x48c,
- 1, 0, 0, 0,
- 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY,
- ARRAY_SIZE(trq_sel_fmap_24_field_info),
- trq_sel_fmap_24_field_info
-},
-{"TRQ_SEL_FMAP_25", 0x490,
- 1, 0, 0, 0,
- 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY,
- ARRAY_SIZE(trq_sel_fmap_25_field_info),
- trq_sel_fmap_25_field_info
-},
-{"TRQ_SEL_FMAP_26", 0x494,
- 1, 0, 0, 0,
- 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY,
- ARRAY_SIZE(trq_sel_fmap_26_field_info),
- trq_sel_fmap_26_field_info
-},
-{"TRQ_SEL_FMAP_27", 0x498,
- 1, 0, 0, 0,
- 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY,
- ARRAY_SIZE(trq_sel_fmap_27_field_info),
- trq_sel_fmap_27_field_info
-},
-{"TRQ_SEL_FMAP_28", 0x49c,
- 1, 0, 0, 0,
- 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY,
- ARRAY_SIZE(trq_sel_fmap_28_field_info),
- trq_sel_fmap_28_field_info
-},
-{"TRQ_SEL_FMAP_29", 0x4a0,
- 1, 0, 0, 0,
- 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY,
- ARRAY_SIZE(trq_sel_fmap_29_field_info),
- trq_sel_fmap_29_field_info
-},
-{"TRQ_SEL_FMAP_2A", 0x4a4,
- 1, 0, 0, 0,
- 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY,
- ARRAY_SIZE(trq_sel_fmap_2a_field_info),
- trq_sel_fmap_2a_field_info
-},
-{"TRQ_SEL_FMAP_2B", 0x4a8,
- 1, 0, 0, 0,
- 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY,
- ARRAY_SIZE(trq_sel_fmap_2b_field_info),
- trq_sel_fmap_2b_field_info
-},
-{"TRQ_SEL_FMAP_2C", 0x4ac,
- 1, 0, 0, 0,
- 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY,
- ARRAY_SIZE(trq_sel_fmap_2c_field_info),
- trq_sel_fmap_2c_field_info
-},
-{"TRQ_SEL_FMAP_2D", 0x4b0,
- 1, 0, 0, 0,
- 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY,
- ARRAY_SIZE(trq_sel_fmap_2d_field_info),
- trq_sel_fmap_2d_field_info
-},
-{"TRQ_SEL_FMAP_2E", 0x4b4,
- 1, 0, 0, 0,
- 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY,
- ARRAY_SIZE(trq_sel_fmap_2e_field_info),
- trq_sel_fmap_2e_field_info
-},
-{"TRQ_SEL_FMAP_2F", 0x4b8,
- 1, 0, 0, 0,
- 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY,
- ARRAY_SIZE(trq_sel_fmap_2f_field_info),
- trq_sel_fmap_2f_field_info
-},
-{"TRQ_SEL_FMAP_30", 0x4bc,
- 1, 0, 0, 0,
- 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY,
- ARRAY_SIZE(trq_sel_fmap_30_field_info),
- trq_sel_fmap_30_field_info
-},
-{"TRQ_SEL_FMAP_31", 0x4d0,
- 1, 0, 0, 0,
- 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY,
- ARRAY_SIZE(trq_sel_fmap_31_field_info),
- trq_sel_fmap_31_field_info
-},
-{"TRQ_SEL_FMAP_32", 0x4d4,
- 1, 0, 0, 0,
- 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY,
- ARRAY_SIZE(trq_sel_fmap_32_field_info),
- trq_sel_fmap_32_field_info
-},
-{"TRQ_SEL_FMAP_33", 0x4d8,
- 1, 0, 0, 0,
- 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY,
- ARRAY_SIZE(trq_sel_fmap_33_field_info),
- trq_sel_fmap_33_field_info
-},
-{"TRQ_SEL_FMAP_34", 0x4dc,
- 1, 0, 0, 0,
- 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY,
- ARRAY_SIZE(trq_sel_fmap_34_field_info),
- trq_sel_fmap_34_field_info
-},
-{"TRQ_SEL_FMAP_35", 0x4e0,
- 1, 0, 0, 0,
- 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY,
- ARRAY_SIZE(trq_sel_fmap_35_field_info),
- trq_sel_fmap_35_field_info
-},
-{"TRQ_SEL_FMAP_36", 0x4e4,
- 1, 0, 0, 0,
- 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY,
- ARRAY_SIZE(trq_sel_fmap_36_field_info),
- trq_sel_fmap_36_field_info
-},
-{"TRQ_SEL_FMAP_37", 0x4e8,
- 1, 0, 0, 0,
- 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY,
- ARRAY_SIZE(trq_sel_fmap_37_field_info),
- trq_sel_fmap_37_field_info
-},
-{"TRQ_SEL_FMAP_38", 0x4ec,
- 1, 0, 0, 0,
- 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY,
- ARRAY_SIZE(trq_sel_fmap_38_field_info),
- trq_sel_fmap_38_field_info
-},
-{"TRQ_SEL_FMAP_39", 0x4f0,
- 1, 0, 0, 0,
- 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY,
- ARRAY_SIZE(trq_sel_fmap_39_field_info),
- trq_sel_fmap_39_field_info
-},
-{"TRQ_SEL_FMAP_3A", 0x4f4,
- 1, 0, 0, 0,
- 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY,
- ARRAY_SIZE(trq_sel_fmap_3a_field_info),
- trq_sel_fmap_3a_field_info
-},
-{"TRQ_SEL_FMAP_3B", 0x4f8,
- 1, 0, 0, 0,
- 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY,
- ARRAY_SIZE(trq_sel_fmap_3b_field_info),
- trq_sel_fmap_3b_field_info
-},
-{"TRQ_SEL_FMAP_3C", 0x4fc,
- 1, 0, 0, 0,
- 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY,
- ARRAY_SIZE(trq_sel_fmap_3c_field_info),
- trq_sel_fmap_3c_field_info
-},
-{"TRQ_SEL_FMAP_3D", 0x500,
- 1, 0, 0, 0,
- 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY,
- ARRAY_SIZE(trq_sel_fmap_3d_field_info),
- trq_sel_fmap_3d_field_info
-},
-{"TRQ_SEL_FMAP_3E", 0x504,
- 1, 0, 0, 0,
- 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY,
- ARRAY_SIZE(trq_sel_fmap_3e_field_info),
- trq_sel_fmap_3e_field_info
-},
-{"TRQ_SEL_FMAP_3F", 0x508,
- 1, 0, 0, 0,
- 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY,
- ARRAY_SIZE(trq_sel_fmap_3f_field_info),
- trq_sel_fmap_3f_field_info
-},
-{"TRQ_SEL_FMAP_40", 0x50c,
- 1, 0, 0, 0,
- 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY,
- ARRAY_SIZE(trq_sel_fmap_40_field_info),
- trq_sel_fmap_40_field_info
-},
-{"TRQ_SEL_FMAP_41", 0x510,
- 1, 0, 0, 0,
- 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY,
- ARRAY_SIZE(trq_sel_fmap_41_field_info),
- trq_sel_fmap_41_field_info
-},
-{"TRQ_SEL_FMAP_42", 0x514,
- 1, 0, 0, 0,
- 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY,
- ARRAY_SIZE(trq_sel_fmap_42_field_info),
- trq_sel_fmap_42_field_info
-},
-{"TRQ_SEL_FMAP_43", 0x518,
- 1, 0, 0, 0,
- 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY,
- ARRAY_SIZE(trq_sel_fmap_43_field_info),
- trq_sel_fmap_43_field_info
-},
-{"TRQ_SEL_FMAP_44", 0x51c,
- 1, 0, 0, 0,
- 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY,
- ARRAY_SIZE(trq_sel_fmap_44_field_info),
- trq_sel_fmap_44_field_info
-},
-{"TRQ_SEL_FMAP_45", 0x520,
- 1, 0, 0, 0,
- 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY,
- ARRAY_SIZE(trq_sel_fmap_45_field_info),
- trq_sel_fmap_45_field_info
-},
-{"TRQ_SEL_FMAP_46", 0x524,
- 1, 0, 0, 0,
- 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY,
- ARRAY_SIZE(trq_sel_fmap_46_field_info),
- trq_sel_fmap_46_field_info
-},
-{"TRQ_SEL_FMAP_47", 0x528,
- 1, 0, 0, 0,
- 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY,
- ARRAY_SIZE(trq_sel_fmap_47_field_info),
- trq_sel_fmap_47_field_info
-},
-{"TRQ_SEL_FMAP_48", 0x52c,
- 1, 0, 0, 0,
- 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY,
- ARRAY_SIZE(trq_sel_fmap_48_field_info),
- trq_sel_fmap_48_field_info
-},
-{"TRQ_SEL_FMAP_49", 0x530,
- 1, 0, 0, 0,
- 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY,
- ARRAY_SIZE(trq_sel_fmap_49_field_info),
- trq_sel_fmap_49_field_info
-},
-{"TRQ_SEL_FMAP_4A", 0x534,
- 1, 0, 0, 0,
- 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY,
- ARRAY_SIZE(trq_sel_fmap_4a_field_info),
- trq_sel_fmap_4a_field_info
-},
-{"TRQ_SEL_FMAP_4B", 0x538,
- 1, 0, 0, 0,
- 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY,
- ARRAY_SIZE(trq_sel_fmap_4b_field_info),
- trq_sel_fmap_4b_field_info
-},
-{"TRQ_SEL_FMAP_4C", 0x53c,
- 1, 0, 0, 0,
- 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY,
- ARRAY_SIZE(trq_sel_fmap_4c_field_info),
- trq_sel_fmap_4c_field_info
-},
-{"TRQ_SEL_FMAP_4D", 0x540,
- 1, 0, 0, 0,
- 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY,
- ARRAY_SIZE(trq_sel_fmap_4d_field_info),
- trq_sel_fmap_4d_field_info
-},
-{"TRQ_SEL_FMAP_4E", 0x544,
- 1, 0, 0, 0,
- 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY,
- ARRAY_SIZE(trq_sel_fmap_4e_field_info),
- trq_sel_fmap_4e_field_info
-},
-{"TRQ_SEL_FMAP_4F", 0x548,
- 1, 0, 0, 0,
- 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY,
- ARRAY_SIZE(trq_sel_fmap_4f_field_info),
- trq_sel_fmap_4f_field_info
-},
-{"TRQ_SEL_FMAP_50", 0x54c,
- 1, 0, 0, 0,
- 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY,
- ARRAY_SIZE(trq_sel_fmap_50_field_info),
- trq_sel_fmap_50_field_info
-},
-{"TRQ_SEL_FMAP_51", 0x550,
- 1, 0, 0, 0,
- 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY,
- ARRAY_SIZE(trq_sel_fmap_51_field_info),
- trq_sel_fmap_51_field_info
-},
-{"TRQ_SEL_FMAP_52", 0x554,
- 1, 0, 0, 0,
- 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY,
- ARRAY_SIZE(trq_sel_fmap_52_field_info),
- trq_sel_fmap_52_field_info
-},
-{"TRQ_SEL_FMAP_53", 0x558,
- 1, 0, 0, 0,
- 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY,
- ARRAY_SIZE(trq_sel_fmap_53_field_info),
- trq_sel_fmap_53_field_info
-},
-{"TRQ_SEL_FMAP_54", 0x55c,
- 1, 0, 0, 0,
- 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY,
- ARRAY_SIZE(trq_sel_fmap_54_field_info),
- trq_sel_fmap_54_field_info
-},
-{"TRQ_SEL_FMAP_55", 0x560,
- 1, 0, 0, 0,
- 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY,
- ARRAY_SIZE(trq_sel_fmap_55_field_info),
- trq_sel_fmap_55_field_info
-},
-{"TRQ_SEL_FMAP_56", 0x564,
- 1, 0, 0, 0,
- 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY,
- ARRAY_SIZE(trq_sel_fmap_56_field_info),
- trq_sel_fmap_56_field_info
-},
-{"TRQ_SEL_FMAP_57", 0x568,
- 1, 0, 0, 0,
- 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY,
- ARRAY_SIZE(trq_sel_fmap_57_field_info),
- trq_sel_fmap_57_field_info
-},
-{"TRQ_SEL_FMAP_58", 0x56c,
- 1, 0, 0, 0,
- 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY,
- ARRAY_SIZE(trq_sel_fmap_58_field_info),
- trq_sel_fmap_58_field_info
-},
-{"TRQ_SEL_FMAP_59", 0x570,
- 1, 0, 0, 0,
- 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY,
- ARRAY_SIZE(trq_sel_fmap_59_field_info),
- trq_sel_fmap_59_field_info
-},
-{"TRQ_SEL_FMAP_5A", 0x574,
- 1, 0, 0, 0,
- 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY,
- ARRAY_SIZE(trq_sel_fmap_5a_field_info),
- trq_sel_fmap_5a_field_info
-},
-{"TRQ_SEL_FMAP_5B", 0x578,
- 1, 0, 0, 0,
- 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY,
- ARRAY_SIZE(trq_sel_fmap_5b_field_info),
- trq_sel_fmap_5b_field_info
-},
-{"TRQ_SEL_FMAP_5C", 0x57c,
- 1, 0, 0, 0,
- 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY,
- ARRAY_SIZE(trq_sel_fmap_5c_field_info),
- trq_sel_fmap_5c_field_info
-},
-{"TRQ_SEL_FMAP_5D", 0x580,
- 1, 0, 0, 0,
- 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY,
- ARRAY_SIZE(trq_sel_fmap_5d_field_info),
- trq_sel_fmap_5d_field_info
-},
-{"TRQ_SEL_FMAP_5E", 0x584,
- 1, 0, 0, 0,
- 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY,
- ARRAY_SIZE(trq_sel_fmap_5e_field_info),
- trq_sel_fmap_5e_field_info
-},
-{"TRQ_SEL_FMAP_5F", 0x588,
- 1, 0, 0, 0,
- 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY,
- ARRAY_SIZE(trq_sel_fmap_5f_field_info),
- trq_sel_fmap_5f_field_info
-},
-{"TRQ_SEL_FMAP_60", 0x58c,
- 1, 0, 0, 0,
- 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY,
- ARRAY_SIZE(trq_sel_fmap_60_field_info),
- trq_sel_fmap_60_field_info
-},
-{"TRQ_SEL_FMAP_61", 0x590,
- 1, 0, 0, 0,
- 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY,
- ARRAY_SIZE(trq_sel_fmap_61_field_info),
- trq_sel_fmap_61_field_info
-},
-{"TRQ_SEL_FMAP_62", 0x594,
- 1, 0, 0, 0,
- 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY,
- ARRAY_SIZE(trq_sel_fmap_62_field_info),
- trq_sel_fmap_62_field_info
-},
-{"TRQ_SEL_FMAP_63", 0x598,
- 1, 0, 0, 0,
- 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY,
- ARRAY_SIZE(trq_sel_fmap_63_field_info),
- trq_sel_fmap_63_field_info
-},
-{"TRQ_SEL_FMAP_64", 0x59c,
- 1, 0, 0, 0,
- 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY,
- ARRAY_SIZE(trq_sel_fmap_64_field_info),
- trq_sel_fmap_64_field_info
-},
-{"TRQ_SEL_FMAP_65", 0x5a0,
- 1, 0, 0, 0,
- 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY,
- ARRAY_SIZE(trq_sel_fmap_65_field_info),
- trq_sel_fmap_65_field_info
-},
-{"TRQ_SEL_FMAP_66", 0x5a4,
- 1, 0, 0, 0,
- 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY,
- ARRAY_SIZE(trq_sel_fmap_66_field_info),
- trq_sel_fmap_66_field_info
-},
-{"TRQ_SEL_FMAP_67", 0x5a8,
- 1, 0, 0, 0,
- 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY,
- ARRAY_SIZE(trq_sel_fmap_67_field_info),
- trq_sel_fmap_67_field_info
-},
-{"TRQ_SEL_FMAP_68", 0x5ac,
- 1, 0, 0, 0,
- 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY,
- ARRAY_SIZE(trq_sel_fmap_68_field_info),
- trq_sel_fmap_68_field_info
-},
-{"TRQ_SEL_FMAP_69", 0x5b0,
- 1, 0, 0, 0,
- 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY,
- ARRAY_SIZE(trq_sel_fmap_69_field_info),
- trq_sel_fmap_69_field_info
-},
-{"TRQ_SEL_FMAP_6A", 0x5b4,
- 1, 0, 0, 0,
- 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY,
- ARRAY_SIZE(trq_sel_fmap_6a_field_info),
- trq_sel_fmap_6a_field_info
-},
-{"TRQ_SEL_FMAP_6B", 0x5b8,
- 1, 0, 0, 0,
- 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY,
- ARRAY_SIZE(trq_sel_fmap_6b_field_info),
- trq_sel_fmap_6b_field_info
-},
-{"TRQ_SEL_FMAP_6C", 0x5bc,
- 1, 0, 0, 0,
- 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY,
- ARRAY_SIZE(trq_sel_fmap_6c_field_info),
- trq_sel_fmap_6c_field_info
-},
-{"TRQ_SEL_FMAP_6D", 0x5c0,
- 1, 0, 0, 0,
- 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY,
- ARRAY_SIZE(trq_sel_fmap_6d_field_info),
- trq_sel_fmap_6d_field_info
-},
-{"TRQ_SEL_FMAP_6E", 0x5c4,
- 1, 0, 0, 0,
- 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY,
- ARRAY_SIZE(trq_sel_fmap_6e_field_info),
- trq_sel_fmap_6e_field_info
-},
-{"TRQ_SEL_FMAP_6F", 0x5c8,
- 1, 0, 0, 0,
- 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY,
- ARRAY_SIZE(trq_sel_fmap_6f_field_info),
- trq_sel_fmap_6f_field_info
-},
-{"TRQ_SEL_FMAP_70", 0x5cc,
- 1, 0, 0, 0,
- 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY,
- ARRAY_SIZE(trq_sel_fmap_70_field_info),
- trq_sel_fmap_70_field_info
-},
-{"TRQ_SEL_FMAP_71", 0x5d0,
- 1, 0, 0, 0,
- 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY,
- ARRAY_SIZE(trq_sel_fmap_71_field_info),
- trq_sel_fmap_71_field_info
-},
-{"TRQ_SEL_FMAP_72", 0x5d4,
- 1, 0, 0, 0,
- 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY,
- ARRAY_SIZE(trq_sel_fmap_72_field_info),
- trq_sel_fmap_72_field_info
-},
-{"TRQ_SEL_FMAP_73", 0x5d8,
- 1, 0, 0, 0,
- 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY,
- ARRAY_SIZE(trq_sel_fmap_73_field_info),
- trq_sel_fmap_73_field_info
-},
-{"TRQ_SEL_FMAP_74", 0x5dc,
- 1, 0, 0, 0,
- 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY,
- ARRAY_SIZE(trq_sel_fmap_74_field_info),
- trq_sel_fmap_74_field_info
-},
-{"TRQ_SEL_FMAP_75", 0x5e0,
- 1, 0, 0, 0,
- 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY,
- ARRAY_SIZE(trq_sel_fmap_75_field_info),
- trq_sel_fmap_75_field_info
-},
-{"TRQ_SEL_FMAP_76", 0x5e4,
- 1, 0, 0, 0,
- 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY,
- ARRAY_SIZE(trq_sel_fmap_76_field_info),
- trq_sel_fmap_76_field_info
-},
-{"TRQ_SEL_FMAP_77", 0x5e8,
- 1, 0, 0, 0,
- 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY,
- ARRAY_SIZE(trq_sel_fmap_77_field_info),
- trq_sel_fmap_77_field_info
-},
-{"TRQ_SEL_FMAP_78", 0x5ec,
- 1, 0, 0, 0,
- 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY,
- ARRAY_SIZE(trq_sel_fmap_78_field_info),
- trq_sel_fmap_78_field_info
-},
-{"TRQ_SEL_FMAP_79", 0x5f0,
- 1, 0, 0, 0,
- 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY,
- ARRAY_SIZE(trq_sel_fmap_79_field_info),
- trq_sel_fmap_79_field_info
-},
-{"TRQ_SEL_FMAP_7A", 0x5f4,
- 1, 0, 0, 0,
- 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY,
- ARRAY_SIZE(trq_sel_fmap_7a_field_info),
- trq_sel_fmap_7a_field_info
-},
-{"TRQ_SEL_FMAP_7B", 0x5f8,
- 1, 0, 0, 0,
- 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY,
- ARRAY_SIZE(trq_sel_fmap_7b_field_info),
- trq_sel_fmap_7b_field_info
-},
-{"TRQ_SEL_FMAP_7C", 0x5fc,
- 1, 0, 0, 0,
- 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY,
- ARRAY_SIZE(trq_sel_fmap_7c_field_info),
- trq_sel_fmap_7c_field_info
-},
-{"TRQ_SEL_FMAP_7D", 0x600,
- 1, 0, 0, 0,
- 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY,
- ARRAY_SIZE(trq_sel_fmap_7d_field_info),
- trq_sel_fmap_7d_field_info
-},
-{"TRQ_SEL_FMAP_7E", 0x604,
- 1, 0, 0, 0,
- 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY,
- ARRAY_SIZE(trq_sel_fmap_7e_field_info),
- trq_sel_fmap_7e_field_info
-},
-{"TRQ_SEL_FMAP_7F", 0x608,
- 1, 0, 0, 0,
- 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY,
- ARRAY_SIZE(trq_sel_fmap_7f_field_info),
- trq_sel_fmap_7f_field_info
-},
-{"TRQ_SEL_FMAP_80", 0x60c,
- 1, 0, 0, 0,
- 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY,
- ARRAY_SIZE(trq_sel_fmap_80_field_info),
- trq_sel_fmap_80_field_info
-},
-{"TRQ_SEL_FMAP_81", 0x610,
- 1, 0, 0, 0,
- 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY,
- ARRAY_SIZE(trq_sel_fmap_81_field_info),
- trq_sel_fmap_81_field_info
-},
-{"TRQ_SEL_FMAP_82", 0x614,
- 1, 0, 0, 0,
- 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY,
- ARRAY_SIZE(trq_sel_fmap_82_field_info),
- trq_sel_fmap_82_field_info
-},
-{"TRQ_SEL_FMAP_83", 0x618,
- 1, 0, 0, 0,
- 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY,
- ARRAY_SIZE(trq_sel_fmap_83_field_info),
- trq_sel_fmap_83_field_info
-},
-{"TRQ_SEL_FMAP_84", 0x61c,
- 1, 0, 0, 0,
- 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY,
- ARRAY_SIZE(trq_sel_fmap_84_field_info),
- trq_sel_fmap_84_field_info
-},
-{"TRQ_SEL_FMAP_85", 0x620,
- 1, 0, 0, 0,
- 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY,
- ARRAY_SIZE(trq_sel_fmap_85_field_info),
- trq_sel_fmap_85_field_info
-},
-{"TRQ_SEL_FMAP_86", 0x624,
- 1, 0, 0, 0,
- 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY,
- ARRAY_SIZE(trq_sel_fmap_86_field_info),
- trq_sel_fmap_86_field_info
-},
-{"TRQ_SEL_FMAP_87", 0x628,
- 1, 0, 0, 0,
- 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY,
- ARRAY_SIZE(trq_sel_fmap_87_field_info),
- trq_sel_fmap_87_field_info
-},
-{"TRQ_SEL_FMAP_88", 0x62c,
- 1, 0, 0, 0,
- 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY,
- ARRAY_SIZE(trq_sel_fmap_88_field_info),
- trq_sel_fmap_88_field_info
-},
-{"TRQ_SEL_FMAP_89", 0x630,
- 1, 0, 0, 0,
- 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY,
- ARRAY_SIZE(trq_sel_fmap_89_field_info),
- trq_sel_fmap_89_field_info
-},
-{"TRQ_SEL_FMAP_8A", 0x634,
- 1, 0, 0, 0,
- 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY,
- ARRAY_SIZE(trq_sel_fmap_8a_field_info),
- trq_sel_fmap_8a_field_info
-},
-{"TRQ_SEL_FMAP_8B", 0x638,
- 1, 0, 0, 0,
- 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY,
- ARRAY_SIZE(trq_sel_fmap_8b_field_info),
- trq_sel_fmap_8b_field_info
-},
-{"TRQ_SEL_FMAP_8C", 0x63c,
- 1, 0, 0, 0,
- 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY,
- ARRAY_SIZE(trq_sel_fmap_8c_field_info),
- trq_sel_fmap_8c_field_info
-},
-{"TRQ_SEL_FMAP_8D", 0x640,
- 1, 0, 0, 0,
- 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY,
- ARRAY_SIZE(trq_sel_fmap_8d_field_info),
- trq_sel_fmap_8d_field_info
-},
-{"TRQ_SEL_FMAP_8E", 0x644,
- 1, 0, 0, 0,
- 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY,
- ARRAY_SIZE(trq_sel_fmap_8e_field_info),
- trq_sel_fmap_8e_field_info
-},
-{"TRQ_SEL_FMAP_8F", 0x648,
- 1, 0, 0, 0,
- 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY,
- ARRAY_SIZE(trq_sel_fmap_8f_field_info),
- trq_sel_fmap_8f_field_info
-},
-{"TRQ_SEL_FMAP_90", 0x64c,
- 1, 0, 0, 0,
- 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY,
- ARRAY_SIZE(trq_sel_fmap_90_field_info),
- trq_sel_fmap_90_field_info
-},
-{"TRQ_SEL_FMAP_91", 0x650,
- 1, 0, 0, 0,
- 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY,
- ARRAY_SIZE(trq_sel_fmap_91_field_info),
- trq_sel_fmap_91_field_info
-},
-{"TRQ_SEL_FMAP_92", 0x654,
- 1, 0, 0, 0,
- 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY,
- ARRAY_SIZE(trq_sel_fmap_92_field_info),
- trq_sel_fmap_92_field_info
-},
-{"TRQ_SEL_FMAP_93", 0x658,
- 1, 0, 0, 0,
- 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY,
- ARRAY_SIZE(trq_sel_fmap_93_field_info),
- trq_sel_fmap_93_field_info
-},
-{"TRQ_SEL_FMAP_94", 0x65c,
- 1, 0, 0, 0,
- 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY,
- ARRAY_SIZE(trq_sel_fmap_94_field_info),
- trq_sel_fmap_94_field_info
-},
-{"TRQ_SEL_FMAP_95", 0x660,
- 1, 0, 0, 0,
- 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY,
- ARRAY_SIZE(trq_sel_fmap_95_field_info),
- trq_sel_fmap_95_field_info
-},
-{"TRQ_SEL_FMAP_96", 0x664,
- 1, 0, 0, 0,
- 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY,
- ARRAY_SIZE(trq_sel_fmap_96_field_info),
- trq_sel_fmap_96_field_info
-},
-{"TRQ_SEL_FMAP_97", 0x668,
- 1, 0, 0, 0,
- 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY,
- ARRAY_SIZE(trq_sel_fmap_97_field_info),
- trq_sel_fmap_97_field_info
-},
-{"TRQ_SEL_FMAP_98", 0x66c,
- 1, 0, 0, 0,
- 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY,
- ARRAY_SIZE(trq_sel_fmap_98_field_info),
- trq_sel_fmap_98_field_info
-},
-{"TRQ_SEL_FMAP_99", 0x670,
- 1, 0, 0, 0,
- 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY,
- ARRAY_SIZE(trq_sel_fmap_99_field_info),
- trq_sel_fmap_99_field_info
-},
-{"TRQ_SEL_FMAP_9A", 0x674,
- 1, 0, 0, 0,
- 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY,
- ARRAY_SIZE(trq_sel_fmap_9a_field_info),
- trq_sel_fmap_9a_field_info
-},
-{"TRQ_SEL_FMAP_9B", 0x678,
- 1, 0, 0, 0,
- 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY,
- ARRAY_SIZE(trq_sel_fmap_9b_field_info),
- trq_sel_fmap_9b_field_info
-},
-{"TRQ_SEL_FMAP_9C", 0x67c,
- 1, 0, 0, 0,
- 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY,
- ARRAY_SIZE(trq_sel_fmap_9c_field_info),
- trq_sel_fmap_9c_field_info
-},
-{"TRQ_SEL_FMAP_9D", 0x680,
- 1, 0, 0, 0,
- 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY,
- ARRAY_SIZE(trq_sel_fmap_9d_field_info),
- trq_sel_fmap_9d_field_info
-},
-{"TRQ_SEL_FMAP_9E", 0x684,
- 1, 0, 0, 0,
- 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY,
- ARRAY_SIZE(trq_sel_fmap_9e_field_info),
- trq_sel_fmap_9e_field_info
-},
-{"TRQ_SEL_FMAP_9F", 0x688,
- 1, 0, 0, 0,
- 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY,
- ARRAY_SIZE(trq_sel_fmap_9f_field_info),
- trq_sel_fmap_9f_field_info
-},
-{"TRQ_SEL_FMAP_A0", 0x68c,
- 1, 0, 0, 0,
- 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY,
- ARRAY_SIZE(trq_sel_fmap_a0_field_info),
- trq_sel_fmap_a0_field_info
-},
-{"TRQ_SEL_FMAP_A1", 0x690,
- 1, 0, 0, 0,
- 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY,
- ARRAY_SIZE(trq_sel_fmap_a1_field_info),
- trq_sel_fmap_a1_field_info
-},
-{"TRQ_SEL_FMAP_A2", 0x694,
- 1, 0, 0, 0,
- 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY,
- ARRAY_SIZE(trq_sel_fmap_a2_field_info),
- trq_sel_fmap_a2_field_info
-},
-{"TRQ_SEL_FMAP_A3", 0x698,
- 1, 0, 0, 0,
- 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY,
- ARRAY_SIZE(trq_sel_fmap_a3_field_info),
- trq_sel_fmap_a3_field_info
-},
-{"TRQ_SEL_FMAP_A4", 0x69c,
- 1, 0, 0, 0,
- 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY,
- ARRAY_SIZE(trq_sel_fmap_a4_field_info),
- trq_sel_fmap_a4_field_info
-},
-{"TRQ_SEL_FMAP_A5", 0x6a0,
- 1, 0, 0, 0,
- 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY,
- ARRAY_SIZE(trq_sel_fmap_a5_field_info),
- trq_sel_fmap_a5_field_info
-},
-{"TRQ_SEL_FMAP_A6", 0x6a4,
- 1, 0, 0, 0,
- 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY,
- ARRAY_SIZE(trq_sel_fmap_a6_field_info),
- trq_sel_fmap_a6_field_info
-},
-{"TRQ_SEL_FMAP_A7", 0x6a8,
- 1, 0, 0, 0,
- 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY,
- ARRAY_SIZE(trq_sel_fmap_a7_field_info),
- trq_sel_fmap_a7_field_info
-},
-{"TRQ_SEL_FMAP_A8", 0x6ac,
- 1, 0, 0, 0,
- 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY,
- ARRAY_SIZE(trq_sel_fmap_a8_field_info),
- trq_sel_fmap_a8_field_info
-},
-{"TRQ_SEL_FMAP_A9", 0x6b0,
- 1, 0, 0, 0,
- 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY,
- ARRAY_SIZE(trq_sel_fmap_a9_field_info),
- trq_sel_fmap_a9_field_info
-},
-{"TRQ_SEL_FMAP_AA", 0x6b4,
- 1, 0, 0, 0,
- 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY,
- ARRAY_SIZE(trq_sel_fmap_aa_field_info),
- trq_sel_fmap_aa_field_info
-},
-{"TRQ_SEL_FMAP_AB", 0x6b8,
- 1, 0, 0, 0,
- 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY,
- ARRAY_SIZE(trq_sel_fmap_ab_field_info),
- trq_sel_fmap_ab_field_info
-},
-{"TRQ_SEL_FMAP_AC", 0x6bc,
- 1, 0, 0, 0,
- 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY,
- ARRAY_SIZE(trq_sel_fmap_ac_field_info),
- trq_sel_fmap_ac_field_info
-},
-{"TRQ_SEL_FMAP_AD", 0x6d0,
- 1, 0, 0, 0,
- 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY,
- ARRAY_SIZE(trq_sel_fmap_ad_field_info),
- trq_sel_fmap_ad_field_info
-},
-{"TRQ_SEL_FMAP_AE", 0x6d4,
- 1, 0, 0, 0,
- 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY,
- ARRAY_SIZE(trq_sel_fmap_ae_field_info),
- trq_sel_fmap_ae_field_info
-},
-{"TRQ_SEL_FMAP_AF", 0x6d8,
- 1, 0, 0, 0,
- 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY,
- ARRAY_SIZE(trq_sel_fmap_af_field_info),
- trq_sel_fmap_af_field_info
-},
-{"TRQ_SEL_FMAP_B0", 0x6dc,
- 1, 0, 0, 0,
- 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY,
- ARRAY_SIZE(trq_sel_fmap_b0_field_info),
- trq_sel_fmap_b0_field_info
-},
-{"TRQ_SEL_FMAP_B1", 0x6e0,
- 1, 0, 0, 0,
- 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY,
- ARRAY_SIZE(trq_sel_fmap_b1_field_info),
- trq_sel_fmap_b1_field_info
-},
-{"TRQ_SEL_FMAP_B2", 0x6e4,
- 1, 0, 0, 0,
- 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY,
- ARRAY_SIZE(trq_sel_fmap_b2_field_info),
- trq_sel_fmap_b2_field_info
-},
-{"TRQ_SEL_FMAP_B3", 0x6e8,
- 1, 0, 0, 0,
- 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY,
- ARRAY_SIZE(trq_sel_fmap_b3_field_info),
- trq_sel_fmap_b3_field_info
-},
-{"TRQ_SEL_FMAP_B4", 0x6ec,
- 1, 0, 0, 0,
- 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY,
- ARRAY_SIZE(trq_sel_fmap_b4_field_info),
- trq_sel_fmap_b4_field_info
-},
-{"TRQ_SEL_FMAP_B5", 0x6f0,
- 1, 0, 0, 0,
- 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY,
- ARRAY_SIZE(trq_sel_fmap_b5_field_info),
- trq_sel_fmap_b5_field_info
-},
-{"TRQ_SEL_FMAP_B6", 0x6f4,
- 1, 0, 0, 0,
- 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY,
- ARRAY_SIZE(trq_sel_fmap_b6_field_info),
- trq_sel_fmap_b6_field_info
-},
-{"TRQ_SEL_FMAP_B7", 0x6f8,
- 1, 0, 0, 0,
- 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY,
- ARRAY_SIZE(trq_sel_fmap_b7_field_info),
- trq_sel_fmap_b7_field_info
-},
-{"TRQ_SEL_FMAP_B8", 0x6fc,
- 1, 0, 0, 0,
- 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY,
- ARRAY_SIZE(trq_sel_fmap_b8_field_info),
- trq_sel_fmap_b8_field_info
-},
-{"TRQ_SEL_FMAP_B9", 0x700,
- 1, 0, 0, 0,
- 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY,
- ARRAY_SIZE(trq_sel_fmap_b9_field_info),
- trq_sel_fmap_b9_field_info
-},
-{"TRQ_SEL_FMAP_BA", 0x704,
- 1, 0, 0, 0,
- 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY,
- ARRAY_SIZE(trq_sel_fmap_ba_field_info),
- trq_sel_fmap_ba_field_info
-},
-{"TRQ_SEL_FMAP_BB", 0x708,
- 1, 0, 0, 0,
- 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY,
- ARRAY_SIZE(trq_sel_fmap_bb_field_info),
- trq_sel_fmap_bb_field_info
-},
-{"TRQ_SEL_FMAP_BC", 0x70c,
- 1, 0, 0, 0,
- 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY,
- ARRAY_SIZE(trq_sel_fmap_bc_field_info),
- trq_sel_fmap_bc_field_info
-},
-{"TRQ_SEL_FMAP_BD", 0x710,
- 1, 0, 0, 0,
- 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY,
- ARRAY_SIZE(trq_sel_fmap_bd_field_info),
- trq_sel_fmap_bd_field_info
-},
-{"TRQ_SEL_FMAP_BE", 0x714,
- 1, 0, 0, 0,
- 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY,
- ARRAY_SIZE(trq_sel_fmap_be_field_info),
- trq_sel_fmap_be_field_info
-},
-{"TRQ_SEL_FMAP_BF", 0x718,
- 1, 0, 0, 0,
- 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY,
- ARRAY_SIZE(trq_sel_fmap_bf_field_info),
- trq_sel_fmap_bf_field_info
-},
-{"TRQ_SEL_FMAP_C0", 0x71c,
- 1, 0, 0, 0,
- 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY,
- ARRAY_SIZE(trq_sel_fmap_c0_field_info),
- trq_sel_fmap_c0_field_info
-},
-{"TRQ_SEL_FMAP_C1", 0x720,
- 1, 0, 0, 0,
- 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY,
- ARRAY_SIZE(trq_sel_fmap_c1_field_info),
- trq_sel_fmap_c1_field_info
-},
-{"TRQ_SEL_FMAP_C2", 0x734,
- 1, 0, 0, 0,
- 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY,
- ARRAY_SIZE(trq_sel_fmap_c2_field_info),
- trq_sel_fmap_c2_field_info
-},
-{"TRQ_SEL_FMAP_C3", 0x748,
- 1, 0, 0, 0,
- 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY,
- ARRAY_SIZE(trq_sel_fmap_c3_field_info),
- trq_sel_fmap_c3_field_info
-},
-{"TRQ_SEL_FMAP_C4", 0x74c,
- 1, 0, 0, 0,
- 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY,
- ARRAY_SIZE(trq_sel_fmap_c4_field_info),
- trq_sel_fmap_c4_field_info
-},
-{"TRQ_SEL_FMAP_C5", 0x750,
- 1, 0, 0, 0,
- 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY,
- ARRAY_SIZE(trq_sel_fmap_c5_field_info),
- trq_sel_fmap_c5_field_info
-},
-{"TRQ_SEL_FMAP_C6", 0x754,
- 1, 0, 0, 0,
- 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY,
- ARRAY_SIZE(trq_sel_fmap_c6_field_info),
- trq_sel_fmap_c6_field_info
-},
-{"TRQ_SEL_FMAP_C7", 0x758,
- 1, 0, 0, 0,
- 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY,
- ARRAY_SIZE(trq_sel_fmap_c7_field_info),
- trq_sel_fmap_c7_field_info
-},
-{"TRQ_SEL_FMAP_C8", 0x75c,
- 1, 0, 0, 0,
- 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY,
- ARRAY_SIZE(trq_sel_fmap_c8_field_info),
- trq_sel_fmap_c8_field_info
-},
-{"TRQ_SEL_FMAP_C9", 0x760,
- 1, 0, 0, 0,
- 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY,
- ARRAY_SIZE(trq_sel_fmap_c9_field_info),
- trq_sel_fmap_c9_field_info
-},
-{"TRQ_SEL_FMAP_CA", 0x764,
- 1, 0, 0, 0,
- 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY,
- ARRAY_SIZE(trq_sel_fmap_ca_field_info),
- trq_sel_fmap_ca_field_info
-},
-{"TRQ_SEL_FMAP_CB", 0x768,
- 1, 0, 0, 0,
- 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY,
- ARRAY_SIZE(trq_sel_fmap_cb_field_info),
- trq_sel_fmap_cb_field_info
-},
-{"TRQ_SEL_FMAP_CC", 0x76c,
- 1, 0, 0, 0,
- 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY,
- ARRAY_SIZE(trq_sel_fmap_cc_field_info),
- trq_sel_fmap_cc_field_info
-},
-{"TRQ_SEL_FMAP_CD", 0x770,
- 1, 0, 0, 0,
- 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY,
- ARRAY_SIZE(trq_sel_fmap_cd_field_info),
- trq_sel_fmap_cd_field_info
-},
-{"TRQ_SEL_FMAP_CE", 0x774,
- 1, 0, 0, 0,
- 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY,
- ARRAY_SIZE(trq_sel_fmap_ce_field_info),
- trq_sel_fmap_ce_field_info
-},
-{"TRQ_SEL_FMAP_CF", 0x778,
- 1, 0, 0, 0,
- 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY,
- ARRAY_SIZE(trq_sel_fmap_cf_field_info),
- trq_sel_fmap_cf_field_info
-},
-{"TRQ_SEL_FMAP_D0", 0x77c,
- 1, 0, 0, 0,
- 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY,
- ARRAY_SIZE(trq_sel_fmap_d0_field_info),
- trq_sel_fmap_d0_field_info
-},
-{"TRQ_SEL_FMAP_D1", 0x780,
- 1, 0, 0, 0,
- 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY,
- ARRAY_SIZE(trq_sel_fmap_d1_field_info),
- trq_sel_fmap_d1_field_info
-},
-{"TRQ_SEL_FMAP_D2", 0x784,
- 1, 0, 0, 0,
- 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY,
- ARRAY_SIZE(trq_sel_fmap_d2_field_info),
- trq_sel_fmap_d2_field_info
-},
-{"TRQ_SEL_FMAP_D3", 0x788,
- 1, 0, 0, 0,
- 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY,
- ARRAY_SIZE(trq_sel_fmap_d3_field_info),
- trq_sel_fmap_d3_field_info
-},
-{"TRQ_SEL_FMAP_D4", 0x78c,
- 1, 0, 0, 0,
- 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY,
- ARRAY_SIZE(trq_sel_fmap_d4_field_info),
- trq_sel_fmap_d4_field_info
-},
-{"TRQ_SEL_FMAP_D5", 0x790,
- 1, 0, 0, 0,
- 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY,
- ARRAY_SIZE(trq_sel_fmap_d5_field_info),
- trq_sel_fmap_d5_field_info
-},
-{"TRQ_SEL_FMAP_D6", 0x794,
- 1, 0, 0, 0,
- 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY,
- ARRAY_SIZE(trq_sel_fmap_d6_field_info),
- trq_sel_fmap_d6_field_info
-},
-{"TRQ_SEL_FMAP_D7", 0x798,
- 1, 0, 0, 0,
- 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY,
- ARRAY_SIZE(trq_sel_fmap_d7_field_info),
- trq_sel_fmap_d7_field_info
-},
-{"TRQ_SEL_FMAP_D8", 0x79c,
- 1, 0, 0, 0,
- 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY,
- ARRAY_SIZE(trq_sel_fmap_d8_field_info),
- trq_sel_fmap_d8_field_info
-},
-{"TRQ_SEL_FMAP_D9", 0x7a0,
- 1, 0, 0, 0,
- 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY,
- ARRAY_SIZE(trq_sel_fmap_d9_field_info),
- trq_sel_fmap_d9_field_info
-},
-{"TRQ_SEL_FMAP_DA", 0x7a4,
- 1, 0, 0, 0,
- 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY,
- ARRAY_SIZE(trq_sel_fmap_da_field_info),
- trq_sel_fmap_da_field_info
-},
-{"TRQ_SEL_FMAP_DB", 0x7a8,
- 1, 0, 0, 0,
- 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY,
- ARRAY_SIZE(trq_sel_fmap_db_field_info),
- trq_sel_fmap_db_field_info
-},
-{"TRQ_SEL_FMAP_DC", 0x7ac,
- 1, 0, 0, 0,
- 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY,
- ARRAY_SIZE(trq_sel_fmap_dc_field_info),
- trq_sel_fmap_dc_field_info
-},
-{"TRQ_SEL_FMAP_DD", 0x7b0,
- 1, 0, 0, 0,
- 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY,
- ARRAY_SIZE(trq_sel_fmap_dd_field_info),
- trq_sel_fmap_dd_field_info
-},
-{"TRQ_SEL_FMAP_DE", 0x7b4,
- 1, 0, 0, 0,
- 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY,
- ARRAY_SIZE(trq_sel_fmap_de_field_info),
- trq_sel_fmap_de_field_info
-},
-{"TRQ_SEL_FMAP_DF", 0x7b8,
- 1, 0, 0, 0,
- 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY,
- ARRAY_SIZE(trq_sel_fmap_df_field_info),
- trq_sel_fmap_df_field_info
-},
-{"TRQ_SEL_FMAP_E0", 0x7bc,
- 1, 0, 0, 0,
- 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY,
- ARRAY_SIZE(trq_sel_fmap_e0_field_info),
- trq_sel_fmap_e0_field_info
-},
-{"TRQ_SEL_FMAP_E1", 0x7c0,
- 1, 0, 0, 0,
- 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY,
- ARRAY_SIZE(trq_sel_fmap_e1_field_info),
- trq_sel_fmap_e1_field_info
-},
-{"TRQ_SEL_FMAP_E2", 0x7c4,
- 1, 0, 0, 0,
- 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY,
- ARRAY_SIZE(trq_sel_fmap_e2_field_info),
- trq_sel_fmap_e2_field_info
-},
-{"TRQ_SEL_FMAP_E3", 0x7c8,
- 1, 0, 0, 0,
- 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY,
- ARRAY_SIZE(trq_sel_fmap_e3_field_info),
- trq_sel_fmap_e3_field_info
-},
-{"TRQ_SEL_FMAP_E4", 0x7cc,
- 1, 0, 0, 0,
- 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY,
- ARRAY_SIZE(trq_sel_fmap_e4_field_info),
- trq_sel_fmap_e4_field_info
-},
-{"TRQ_SEL_FMAP_E5", 0x7d0,
- 1, 0, 0, 0,
- 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY,
- ARRAY_SIZE(trq_sel_fmap_e5_field_info),
- trq_sel_fmap_e5_field_info
-},
-{"TRQ_SEL_FMAP_E6", 0x7d4,
- 1, 0, 0, 0,
- 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY,
- ARRAY_SIZE(trq_sel_fmap_e6_field_info),
- trq_sel_fmap_e6_field_info
-},
-{"TRQ_SEL_FMAP_E7", 0x7d8,
- 1, 0, 0, 0,
- 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY,
- ARRAY_SIZE(trq_sel_fmap_e7_field_info),
- trq_sel_fmap_e7_field_info
-},
-{"TRQ_SEL_FMAP_E8", 0x7dc,
- 1, 0, 0, 0,
- 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY,
- ARRAY_SIZE(trq_sel_fmap_e8_field_info),
- trq_sel_fmap_e8_field_info
-},
-{"TRQ_SEL_FMAP_E9", 0x7e0,
- 1, 0, 0, 0,
- 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY,
- ARRAY_SIZE(trq_sel_fmap_e9_field_info),
- trq_sel_fmap_e9_field_info
-},
-{"TRQ_SEL_FMAP_EA", 0x7e4,
- 1, 0, 0, 0,
- 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY,
- ARRAY_SIZE(trq_sel_fmap_ea_field_info),
- trq_sel_fmap_ea_field_info
-},
-{"TRQ_SEL_FMAP_EB", 0x7e8,
- 1, 0, 0, 0,
- 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY,
- ARRAY_SIZE(trq_sel_fmap_eb_field_info),
- trq_sel_fmap_eb_field_info
-},
-{"TRQ_SEL_FMAP_EC", 0x7ec,
- 1, 0, 0, 0,
- 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY,
- ARRAY_SIZE(trq_sel_fmap_ec_field_info),
- trq_sel_fmap_ec_field_info
-},
-{"TRQ_SEL_FMAP_ED", 0x7f0,
- 1, 0, 0, 0,
- 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY,
- ARRAY_SIZE(trq_sel_fmap_ed_field_info),
- trq_sel_fmap_ed_field_info
-},
-{"TRQ_SEL_FMAP_EE", 0x7f4,
- 1, 0, 0, 0,
- 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY,
- ARRAY_SIZE(trq_sel_fmap_ee_field_info),
- trq_sel_fmap_ee_field_info
-},
-{"TRQ_SEL_FMAP_EF", 0x7f8,
- 1, 0, 0, 0,
- 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY,
- ARRAY_SIZE(trq_sel_fmap_ef_field_info),
- trq_sel_fmap_ef_field_info
-},
-{"TRQ_SEL_FMAP_F0", 0x7fc,
- 1, 0, 0, 0,
- 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY,
- ARRAY_SIZE(trq_sel_fmap_f0_field_info),
- trq_sel_fmap_f0_field_info
-},
-{"IND_CTXT_DATA_3", 0x804,
- 1, 0, 0, 0,
- 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY,
- ARRAY_SIZE(ind_ctxt_data_3_field_info),
- ind_ctxt_data_3_field_info
-},
-{"IND_CTXT_DATA_2", 0x808,
- 1, 0, 0, 0,
- 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY,
- ARRAY_SIZE(ind_ctxt_data_2_field_info),
- ind_ctxt_data_2_field_info
-},
-{"IND_CTXT_DATA_1", 0x80c,
- 1, 0, 0, 0,
- 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY,
- ARRAY_SIZE(ind_ctxt_data_1_field_info),
- ind_ctxt_data_1_field_info
-},
-{"IND_CTXT_DATA_0", 0x810,
- 1, 0, 0, 0,
- 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY,
- ARRAY_SIZE(ind_ctxt_data_0_field_info),
- ind_ctxt_data_0_field_info
-},
-{"IND_CTXT3", 0x814,
- 1, 0, 0, 0,
- 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY,
- ARRAY_SIZE(ind_ctxt3_field_info),
- ind_ctxt3_field_info
-},
-{"IND_CTXT2", 0x818,
- 1, 0, 0, 0,
- 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY,
- ARRAY_SIZE(ind_ctxt2_field_info),
- ind_ctxt2_field_info
-},
-{"IND_CTXT1", 0x81c,
- 1, 0, 0, 0,
- 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY,
- ARRAY_SIZE(ind_ctxt1_field_info),
- ind_ctxt1_field_info
-},
-{"IND_CTXT0", 0x820,
- 1, 0, 0, 0,
- 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY,
- ARRAY_SIZE(ind_ctxt0_field_info),
- ind_ctxt0_field_info
-},
-{"IND_CTXT_CMD", 0x824,
- 1, 0, 0, 0,
- 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY,
- ARRAY_SIZE(ind_ctxt_cmd_field_info),
- ind_ctxt_cmd_field_info
-},
-{"C2H_TIMER_CNT_1", 0xa00,
- 1, 0, 0, 0,
- 0, QDMA_COMPLETION_MODE, QDMA_REG_READ_PF_ONLY,
- ARRAY_SIZE(c2h_timer_cnt_1_field_info),
- c2h_timer_cnt_1_field_info
-},
-{"C2H_TIMER_CNT_2", 0xa04,
- 1, 0, 0, 0,
- 0, QDMA_COMPLETION_MODE, QDMA_REG_READ_PF_ONLY,
- ARRAY_SIZE(c2h_timer_cnt_2_field_info),
- c2h_timer_cnt_2_field_info
-},
-{"C2H_TIMER_CNT_3", 0xa08,
- 1, 0, 0, 0,
- 0, QDMA_COMPLETION_MODE, QDMA_REG_READ_PF_ONLY,
- ARRAY_SIZE(c2h_timer_cnt_3_field_info),
- c2h_timer_cnt_3_field_info
-},
-{"C2H_TIMER_CNT_4", 0xa0c,
- 1, 0, 0, 0,
- 0, QDMA_COMPLETION_MODE, QDMA_REG_READ_PF_ONLY,
- ARRAY_SIZE(c2h_timer_cnt_4_field_info),
- c2h_timer_cnt_4_field_info
-},
-{"C2H_TIMER_CNT_5", 0xa10,
- 1, 0, 0, 0,
- 0, QDMA_COMPLETION_MODE, QDMA_REG_READ_PF_ONLY,
- ARRAY_SIZE(c2h_timer_cnt_5_field_info),
- c2h_timer_cnt_5_field_info
-},
-{"C2H_TIMER_CNT_6", 0xa14,
- 1, 0, 0, 0,
- 0, QDMA_COMPLETION_MODE, QDMA_REG_READ_PF_ONLY,
- ARRAY_SIZE(c2h_timer_cnt_6_field_info),
- c2h_timer_cnt_6_field_info
-},
-{"C2H_TIMER_CNT_7", 0xa18,
- 1, 0, 0, 0,
- 0, QDMA_COMPLETION_MODE, QDMA_REG_READ_PF_ONLY,
- ARRAY_SIZE(c2h_timer_cnt_7_field_info),
- c2h_timer_cnt_7_field_info
-},
-{"C2H_TIMER_CNT_8", 0xa1c,
- 1, 0, 0, 0,
- 0, QDMA_COMPLETION_MODE, QDMA_REG_READ_PF_ONLY,
- ARRAY_SIZE(c2h_timer_cnt_8_field_info),
- c2h_timer_cnt_8_field_info
-},
-{"C2H_TIMER_CNT_9", 0xa20,
- 1, 0, 0, 0,
- 0, QDMA_COMPLETION_MODE, QDMA_REG_READ_PF_ONLY,
- ARRAY_SIZE(c2h_timer_cnt_9_field_info),
- c2h_timer_cnt_9_field_info
-},
-{"C2H_TIMER_CNT_A", 0xa24,
- 1, 0, 0, 0,
- 0, QDMA_COMPLETION_MODE, QDMA_REG_READ_PF_ONLY,
- ARRAY_SIZE(c2h_timer_cnt_a_field_info),
- c2h_timer_cnt_a_field_info
-},
-{"C2H_TIMER_CNT_B", 0xa28,
- 1, 0, 0, 0,
- 0, QDMA_COMPLETION_MODE, QDMA_REG_READ_PF_ONLY,
- ARRAY_SIZE(c2h_timer_cnt_b_field_info),
- c2h_timer_cnt_b_field_info
-},
-{"C2H_TIMER_CNT_C", 0xa2c,
- 1, 0, 0, 0,
- 0, QDMA_COMPLETION_MODE, QDMA_REG_READ_PF_ONLY,
- ARRAY_SIZE(c2h_timer_cnt_c_field_info),
- c2h_timer_cnt_c_field_info
-},
-{"C2H_TIMER_CNT_D", 0xa30,
- 1, 0, 0, 0,
- 0, QDMA_COMPLETION_MODE, QDMA_REG_READ_PF_ONLY,
- ARRAY_SIZE(c2h_timer_cnt_d_field_info),
- c2h_timer_cnt_d_field_info
-},
-{"C2H_TIMER_CNT_E", 0xa34,
- 1, 0, 0, 0,
- 0, QDMA_COMPLETION_MODE, QDMA_REG_READ_PF_ONLY,
- ARRAY_SIZE(c2h_timer_cnt_e_field_info),
- c2h_timer_cnt_e_field_info
-},
-{"C2H_TIMER_CNT_F", 0xa38,
- 1, 0, 0, 0,
- 0, QDMA_COMPLETION_MODE, QDMA_REG_READ_PF_ONLY,
- ARRAY_SIZE(c2h_timer_cnt_f_field_info),
- c2h_timer_cnt_f_field_info
-},
-{"C2H_TIMER_CNT_10", 0xa3c,
- 1, 0, 0, 0,
- 0, QDMA_COMPLETION_MODE, QDMA_REG_READ_PF_ONLY,
- ARRAY_SIZE(c2h_timer_cnt_10_field_info),
- c2h_timer_cnt_10_field_info
-},
-{"C2H_CNT_TH_1", 0xa40,
- 1, 0, 0, 0,
- 0, QDMA_COMPLETION_MODE, QDMA_REG_READ_PF_ONLY,
- ARRAY_SIZE(c2h_cnt_th_1_field_info),
- c2h_cnt_th_1_field_info
-},
-{"C2H_CNT_TH_2", 0xa44,
- 1, 0, 0, 0,
- 0, QDMA_COMPLETION_MODE, QDMA_REG_READ_PF_ONLY,
- ARRAY_SIZE(c2h_cnt_th_2_field_info),
- c2h_cnt_th_2_field_info
-},
-{"C2H_CNT_TH_3", 0xa48,
- 1, 0, 0, 0,
- 0, QDMA_COMPLETION_MODE, QDMA_REG_READ_PF_ONLY,
- ARRAY_SIZE(c2h_cnt_th_3_field_info),
- c2h_cnt_th_3_field_info
-},
-{"C2H_CNT_TH_4", 0xa4c,
- 1, 0, 0, 0,
- 0, QDMA_COMPLETION_MODE, QDMA_REG_READ_PF_ONLY,
- ARRAY_SIZE(c2h_cnt_th_4_field_info),
- c2h_cnt_th_4_field_info
-},
-{"C2H_CNT_TH_5", 0xa50,
- 1, 0, 0, 0,
- 0, QDMA_COMPLETION_MODE, QDMA_REG_READ_PF_ONLY,
- ARRAY_SIZE(c2h_cnt_th_5_field_info),
- c2h_cnt_th_5_field_info
-},
-{"C2H_CNT_TH_6", 0xa54,
- 1, 0, 0, 0,
- 0, QDMA_COMPLETION_MODE, QDMA_REG_READ_PF_ONLY,
- ARRAY_SIZE(c2h_cnt_th_6_field_info),
- c2h_cnt_th_6_field_info
-},
-{"C2H_CNT_TH_7", 0xa58,
- 1, 0, 0, 0,
- 0, QDMA_COMPLETION_MODE, QDMA_REG_READ_PF_ONLY,
- ARRAY_SIZE(c2h_cnt_th_7_field_info),
- c2h_cnt_th_7_field_info
-},
-{"C2H_CNT_TH_8", 0xa5c,
- 1, 0, 0, 0,
- 0, QDMA_COMPLETION_MODE, QDMA_REG_READ_PF_ONLY,
- ARRAY_SIZE(c2h_cnt_th_8_field_info),
- c2h_cnt_th_8_field_info
-},
-{"C2H_CNT_TH_9", 0xa60,
- 1, 0, 0, 0,
- 0, QDMA_COMPLETION_MODE, QDMA_REG_READ_PF_ONLY,
- ARRAY_SIZE(c2h_cnt_th_9_field_info),
- c2h_cnt_th_9_field_info
-},
-{"C2H_CNT_TH_A", 0xa64,
- 1, 0, 0, 0,
- 0, QDMA_COMPLETION_MODE, QDMA_REG_READ_PF_ONLY,
- ARRAY_SIZE(c2h_cnt_th_a_field_info),
- c2h_cnt_th_a_field_info
-},
-{"C2H_CNT_TH_B", 0xa68,
- 1, 0, 0, 0,
- 0, QDMA_COMPLETION_MODE, QDMA_REG_READ_PF_ONLY,
- ARRAY_SIZE(c2h_cnt_th_b_field_info),
- c2h_cnt_th_b_field_info
-},
-{"C2H_CNT_TH_C", 0xa6c,
- 1, 0, 0, 0,
- 0, QDMA_COMPLETION_MODE, QDMA_REG_READ_PF_ONLY,
- ARRAY_SIZE(c2h_cnt_th_c_field_info),
- c2h_cnt_th_c_field_info
-},
-{"C2H_CNT_TH_D", 0xa70,
- 1, 0, 0, 0,
- 0, QDMA_COMPLETION_MODE, QDMA_REG_READ_PF_ONLY,
- ARRAY_SIZE(c2h_cnt_th_d_field_info),
- c2h_cnt_th_d_field_info
-},
-{"C2H_CNT_TH_E", 0xa74,
- 1, 0, 0, 0,
- 0, QDMA_COMPLETION_MODE, QDMA_REG_READ_PF_ONLY,
- ARRAY_SIZE(c2h_cnt_th_e_field_info),
- c2h_cnt_th_e_field_info
-},
-{"C2H_CNT_TH_F", 0xa78,
- 1, 0, 0, 0,
- 0, QDMA_COMPLETION_MODE, QDMA_REG_READ_PF_ONLY,
- ARRAY_SIZE(c2h_cnt_th_f_field_info),
- c2h_cnt_th_f_field_info
-},
-{"C2H_CNT_TH_10", 0xa7c,
- 1, 0, 0, 0,
- 0, QDMA_COMPLETION_MODE, QDMA_REG_READ_PF_ONLY,
- ARRAY_SIZE(c2h_cnt_th_10_field_info),
- c2h_cnt_th_10_field_info
-},
-{"C2H_QID2VEC_MAP_QID", 0xa80,
- 1, 0, 0, 0,
- 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY,
- ARRAY_SIZE(c2h_qid2vec_map_qid_field_info),
- c2h_qid2vec_map_qid_field_info
-},
-{"C2H_QID2VEC_MAP", 0xa84,
- 1, 0, 0, 0,
- 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY,
- ARRAY_SIZE(c2h_qid2vec_map_field_info),
- c2h_qid2vec_map_field_info
-},
-{"C2H_STAT_S_AXIS_C2H_ACCEPTED", 0xa88,
- 1, 0, 0, 0,
- 0, QDMA_ST_MODE, QDMA_REG_READ_PF_VF,
- ARRAY_SIZE(c2h_stat_s_axis_c2h_accepted_field_info),
- c2h_stat_s_axis_c2h_accepted_field_info
-},
-{"C2H_STAT_S_AXIS_WRB_ACCEPTED", 0xa8c,
- 1, 0, 0, 0,
- 0, QDMA_ST_MODE, QDMA_REG_READ_PF_VF,
- ARRAY_SIZE(c2h_stat_s_axis_wrb_accepted_field_info),
- c2h_stat_s_axis_wrb_accepted_field_info
-},
-{"C2H_STAT_DESC_RSP_PKT_ACCEPTED", 0xa90,
- 1, 0, 0, 0,
- 0, QDMA_ST_MODE, QDMA_REG_READ_PF_VF,
- ARRAY_SIZE(c2h_stat_desc_rsp_pkt_accepted_field_info),
- c2h_stat_desc_rsp_pkt_accepted_field_info
-},
-{"C2H_STAT_AXIS_PKG_CMP", 0xa94,
- 1, 0, 0, 0,
- 0, QDMA_ST_MODE, QDMA_REG_READ_PF_VF,
- ARRAY_SIZE(c2h_stat_axis_pkg_cmp_field_info),
- c2h_stat_axis_pkg_cmp_field_info
-},
-{"C2H_STAT_DESC_RSP_ACCEPTED", 0xa98,
- 1, 0, 0, 0,
- 0, QDMA_ST_MODE, QDMA_REG_READ_PF_ONLY,
- ARRAY_SIZE(c2h_stat_desc_rsp_accepted_field_info),
- c2h_stat_desc_rsp_accepted_field_info
-},
-{"C2H_STAT_DESC_RSP_CMP", 0xa9c,
- 1, 0, 0, 0,
- 0, QDMA_ST_MODE, QDMA_REG_READ_PF_ONLY,
- ARRAY_SIZE(c2h_stat_desc_rsp_cmp_field_info),
- c2h_stat_desc_rsp_cmp_field_info
-},
-{"C2H_STAT_WRQ_OUT", 0xaa0,
- 1, 0, 0, 0,
- 0, QDMA_ST_MODE, QDMA_REG_READ_PF_ONLY,
- ARRAY_SIZE(c2h_stat_wrq_out_field_info),
- c2h_stat_wrq_out_field_info
-},
-{"C2H_STAT_WPL_REN_ACCEPTED", 0xaa4,
- 1, 0, 0, 0,
- 0, QDMA_ST_MODE, QDMA_REG_READ_PF_ONLY,
- ARRAY_SIZE(c2h_stat_wpl_ren_accepted_field_info),
- c2h_stat_wpl_ren_accepted_field_info
-},
-{"C2H_STAT_TOTAL_WRQ_LEN", 0xaa8,
- 1, 0, 0, 0,
- 0, QDMA_ST_MODE, QDMA_REG_READ_PF_ONLY,
- ARRAY_SIZE(c2h_stat_total_wrq_len_field_info),
- c2h_stat_total_wrq_len_field_info
-},
-{"C2H_STAT_TOTAL_WPL_LEN", 0xaac,
- 1, 0, 0, 0,
- 0, QDMA_ST_MODE, QDMA_REG_READ_PF_ONLY,
- ARRAY_SIZE(c2h_stat_total_wpl_len_field_info),
- c2h_stat_total_wpl_len_field_info
-},
-{"C2H_BUF_SZ_0", 0xab0,
- 1, 0, 0, 0,
- 0, QDMA_ST_MODE, QDMA_REG_READ_PF_ONLY,
- ARRAY_SIZE(c2h_buf_sz_0_field_info),
- c2h_buf_sz_0_field_info
-},
-{"C2H_BUF_SZ_1", 0xab4,
- 1, 0, 0, 0,
- 0, QDMA_ST_MODE, QDMA_REG_READ_PF_ONLY,
- ARRAY_SIZE(c2h_buf_sz_1_field_info),
- c2h_buf_sz_1_field_info
-},
-{"C2H_BUF_SZ_2", 0xab8,
- 1, 0, 0, 0,
- 0, QDMA_ST_MODE, QDMA_REG_READ_PF_ONLY,
- ARRAY_SIZE(c2h_buf_sz_2_field_info),
- c2h_buf_sz_2_field_info
-},
-{"C2H_BUF_SZ_3", 0xabc,
- 1, 0, 0, 0,
- 0, QDMA_ST_MODE, QDMA_REG_READ_PF_ONLY,
- ARRAY_SIZE(c2h_buf_sz_3_field_info),
- c2h_buf_sz_3_field_info
-},
-{"C2H_BUF_SZ_4", 0xac0,
- 1, 0, 0, 0,
- 0, QDMA_ST_MODE, QDMA_REG_READ_PF_ONLY,
- ARRAY_SIZE(c2h_buf_sz_4_field_info),
- c2h_buf_sz_4_field_info
-},
-{"C2H_BUF_SZ_5", 0xac4,
- 1, 0, 0, 0,
- 0, QDMA_ST_MODE, QDMA_REG_READ_PF_ONLY,
- ARRAY_SIZE(c2h_buf_sz_5_field_info),
- c2h_buf_sz_5_field_info
-},
-{"C2H_BUF_SZ_7", 0xac8,
- 1, 0, 0, 0,
- 0, QDMA_ST_MODE, QDMA_REG_READ_PF_ONLY,
- ARRAY_SIZE(c2h_buf_sz_7_field_info),
- c2h_buf_sz_7_field_info
-},
-{"C2H_BUF_SZ_8", 0xacc,
- 1, 0, 0, 0,
- 0, QDMA_ST_MODE, QDMA_REG_READ_PF_ONLY,
- ARRAY_SIZE(c2h_buf_sz_8_field_info),
- c2h_buf_sz_8_field_info
-},
-{"C2H_BUF_SZ_9", 0xad0,
- 1, 0, 0, 0,
- 0, QDMA_ST_MODE, QDMA_REG_READ_PF_ONLY,
- ARRAY_SIZE(c2h_buf_sz_9_field_info),
- c2h_buf_sz_9_field_info
-},
-{"C2H_BUF_SZ_10", 0xad4,
- 1, 0, 0, 0,
- 0, QDMA_ST_MODE, QDMA_REG_READ_PF_ONLY,
- ARRAY_SIZE(c2h_buf_sz_10_field_info),
- c2h_buf_sz_10_field_info
-},
-{"C2H_BUF_SZ_11", 0xad8,
- 1, 0, 0, 0,
- 0, QDMA_ST_MODE, QDMA_REG_READ_PF_ONLY,
- ARRAY_SIZE(c2h_buf_sz_11_field_info),
- c2h_buf_sz_11_field_info
-},
-{"C2H_BUF_SZ_12", 0xae0,
- 1, 0, 0, 0,
- 0, QDMA_ST_MODE, QDMA_REG_READ_PF_ONLY,
- ARRAY_SIZE(c2h_buf_sz_12_field_info),
- c2h_buf_sz_12_field_info
-},
-{"C2H_BUF_SZ_13", 0xae4,
- 1, 0, 0, 0,
- 0, QDMA_ST_MODE, QDMA_REG_READ_PF_ONLY,
- ARRAY_SIZE(c2h_buf_sz_13_field_info),
- c2h_buf_sz_13_field_info
-},
-{"C2H_BUF_SZ_14", 0xae8,
- 1, 0, 0, 0,
- 0, QDMA_ST_MODE, QDMA_REG_READ_PF_ONLY,
- ARRAY_SIZE(c2h_buf_sz_14_field_info),
- c2h_buf_sz_14_field_info
-},
-{"C2H_BUF_SZ_15", 0xaec,
- 1, 0, 0, 0,
- 0, QDMA_ST_MODE, QDMA_REG_READ_PF_ONLY,
- ARRAY_SIZE(c2h_buf_sz_15_field_info),
- c2h_buf_sz_15_field_info
-},
-{"C2H_ERR_STAT", 0xaf0,
- 1, 0, 0, 0,
- 0, QDMA_ST_MODE, QDMA_REG_READ_PF_VF,
- ARRAY_SIZE(c2h_err_stat_field_info),
- c2h_err_stat_field_info
-},
-{"C2H_ERR_MASK", 0xaf4,
- 1, 0, 0, 0,
- 0, QDMA_ST_MODE, QDMA_REG_READ_PF_VF,
- ARRAY_SIZE(c2h_err_mask_field_info),
- c2h_err_mask_field_info
-},
-{"C2H_FATAL_ERR_STAT", 0xaf8,
- 1, 0, 0, 0,
- 0, QDMA_ST_MODE, QDMA_REG_READ_PF_VF,
- ARRAY_SIZE(c2h_fatal_err_stat_field_info),
- c2h_fatal_err_stat_field_info
-},
-{"C2H_FATAL_ERR_MASK", 0xafc,
- 1, 0, 0, 0,
- 0, QDMA_ST_MODE, QDMA_REG_READ_PF_VF,
- ARRAY_SIZE(c2h_fatal_err_mask_field_info),
- c2h_fatal_err_mask_field_info
-},
-{"C2H_FATAL_ERR_ENABLE", 0xb00,
- 1, 0, 0, 0,
- 0, QDMA_ST_MODE, QDMA_REG_READ_PF_VF,
- ARRAY_SIZE(c2h_fatal_err_enable_field_info),
- c2h_fatal_err_enable_field_info
-},
-{"GLBL_ERR_INT", 0xb04,
- 1, 0, 0, 0,
- 0, QDMA_ST_MODE, QDMA_REG_READ_PF_VF,
- ARRAY_SIZE(glbl_err_int_field_info),
- glbl_err_int_field_info
-},
-{"C2H_PFCH_CFG", 0xb08,
- 1, 0, 0, 0,
- 0, QDMA_ST_MODE, QDMA_REG_READ_PF_ONLY,
- ARRAY_SIZE(c2h_pfch_cfg_field_info),
- c2h_pfch_cfg_field_info
-},
-{"C2H_INT_TIMER_TICK", 0xb0c,
- 1, 0, 0, 0,
- 0, QDMA_ST_MODE, QDMA_REG_READ_PF_ONLY,
- ARRAY_SIZE(c2h_int_timer_tick_field_info),
- c2h_int_timer_tick_field_info
-},
-{"C2H_STAT_DESC_RSP_DROP_ACCEPTED", 0xb10,
- 1, 0, 0, 0,
- 0, QDMA_ST_MODE, QDMA_REG_READ_PF_VF,
- ARRAY_SIZE(c2h_stat_desc_rsp_drop_accepted_field_info),
- c2h_stat_desc_rsp_drop_accepted_field_info
-},
-{"C2H_STAT_DESC_RSP_ERR_ACCEPTED", 0xb14,
- 1, 0, 0, 0,
- 0, QDMA_ST_MODE, QDMA_REG_READ_PF_VF,
- ARRAY_SIZE(c2h_stat_desc_rsp_err_accepted_field_info),
- c2h_stat_desc_rsp_err_accepted_field_info
-},
-{"C2H_STAT_DESC_REQ", 0xb18,
- 1, 0, 0, 0,
- 0, QDMA_ST_MODE, QDMA_REG_READ_PF_ONLY,
- ARRAY_SIZE(c2h_stat_desc_req_field_info),
- c2h_stat_desc_req_field_info
-},
-{"C2H_STAT_DBG_DMA_ENG_0", 0xb1c,
- 1, 0, 0, 0,
- 0, QDMA_ST_MODE, QDMA_REG_READ_PF_ONLY,
- ARRAY_SIZE(c2h_stat_dbg_dma_eng_0_field_info),
- c2h_stat_dbg_dma_eng_0_field_info
-},
-{"C2H_STAT_DBG_DMA_ENG_1", 0xb20,
- 1, 0, 0, 0,
- 0, QDMA_ST_MODE, QDMA_REG_READ_PF_ONLY,
- ARRAY_SIZE(c2h_stat_dbg_dma_eng_1_field_info),
- c2h_stat_dbg_dma_eng_1_field_info
-},
-{"C2H_STAT_DBG_DMA_ENG_2", 0xb24,
- 1, 0, 0, 0,
- 0, QDMA_ST_MODE, QDMA_REG_READ_PF_ONLY,
- ARRAY_SIZE(c2h_stat_dbg_dma_eng_2_field_info),
- c2h_stat_dbg_dma_eng_2_field_info
-},
-{"C2H_STAT_DBG_DMA_ENG_3", 0xb28,
- 1, 0, 0, 0,
- 0, QDMA_ST_MODE, QDMA_REG_READ_PF_ONLY,
- ARRAY_SIZE(c2h_stat_dbg_dma_eng_3_field_info),
- c2h_stat_dbg_dma_eng_3_field_info
-},
-{"C2H_DBG_PFCH_ERR_CTXT", 0xb2c,
- 1, 0, 0, 0,
- 0, QDMA_ST_MODE, QDMA_REG_READ_PF_ONLY,
- ARRAY_SIZE(c2h_dbg_pfch_err_ctxt_field_info),
- c2h_dbg_pfch_err_ctxt_field_info
-},
-{"C2H_FIRST_ERR_QID", 0xb30,
- 1, 0, 0, 0,
- 0, QDMA_ST_MODE, QDMA_REG_READ_PF_VF,
- ARRAY_SIZE(c2h_first_err_qid_field_info),
- c2h_first_err_qid_field_info
-},
-{"STAT_NUM_WRB_IN", 0xb34,
- 1, 0, 0, 0,
- 0, QDMA_ST_MODE, QDMA_REG_READ_PF_ONLY,
- ARRAY_SIZE(stat_num_wrb_in_field_info),
- stat_num_wrb_in_field_info
-},
-{"STAT_NUM_WRB_OUT", 0xb38,
- 1, 0, 0, 0,
- 0, QDMA_ST_MODE, QDMA_REG_READ_PF_ONLY,
- ARRAY_SIZE(stat_num_wrb_out_field_info),
- stat_num_wrb_out_field_info
-},
-{"STAT_NUM_WRB_DRP", 0xb3c,
- 1, 0, 0, 0,
- 0, QDMA_ST_MODE, QDMA_REG_READ_PF_ONLY,
- ARRAY_SIZE(stat_num_wrb_drp_field_info),
- stat_num_wrb_drp_field_info
-},
-{"STAT_NUM_STAT_DESC_OUT", 0xb40,
- 1, 0, 0, 0,
- 0, QDMA_ST_MODE, QDMA_REG_READ_PF_ONLY,
- ARRAY_SIZE(stat_num_stat_desc_out_field_info),
- stat_num_stat_desc_out_field_info
-},
-{"STAT_NUM_DSC_CRDT_SENT", 0xb44,
- 1, 0, 0, 0,
- 0, QDMA_ST_MODE, QDMA_REG_READ_PF_ONLY,
- ARRAY_SIZE(stat_num_dsc_crdt_sent_field_info),
- stat_num_dsc_crdt_sent_field_info
-},
-{"STAT_NUM_FCH_DSC_RCVD", 0xb48,
- 1, 0, 0, 0,
- 0, QDMA_ST_MODE, QDMA_REG_READ_PF_ONLY,
- ARRAY_SIZE(stat_num_fch_dsc_rcvd_field_info),
- stat_num_fch_dsc_rcvd_field_info
-},
-{"STAT_NUM_BYP_DSC_RCVD", 0xb4c,
- 1, 0, 0, 0,
- 0, QDMA_ST_MODE, QDMA_REG_READ_PF_ONLY,
- ARRAY_SIZE(stat_num_byp_dsc_rcvd_field_info),
- stat_num_byp_dsc_rcvd_field_info
-},
-{"C2H_WRB_COAL_CFG", 0xb50,
- 1, 0, 0, 0,
- 0, QDMA_ST_MODE, QDMA_REG_READ_PF_ONLY,
- ARRAY_SIZE(c2h_wrb_coal_cfg_field_info),
- c2h_wrb_coal_cfg_field_info
-},
-{"C2H_INTR_H2C_REQ", 0xb54,
- 1, 0, 0, 0,
- 0, QDMA_ST_MODE, QDMA_REG_READ_PF_VF,
- ARRAY_SIZE(c2h_intr_h2c_req_field_info),
- c2h_intr_h2c_req_field_info
-},
-{"C2H_INTR_C2H_MM_REQ", 0xb58,
- 1, 0, 0, 0,
- 0, QDMA_ST_MODE, QDMA_REG_READ_PF_VF,
- ARRAY_SIZE(c2h_intr_c2h_mm_req_field_info),
- c2h_intr_c2h_mm_req_field_info
-},
-{"C2H_INTR_ERR_INT_REQ", 0xb5c,
- 1, 0, 0, 0,
- 0, QDMA_ST_MODE, QDMA_REG_READ_PF_VF,
- ARRAY_SIZE(c2h_intr_err_int_req_field_info),
- c2h_intr_err_int_req_field_info
-},
-{"C2H_INTR_C2H_ST_REQ", 0xb60,
- 1, 0, 0, 0,
- 0, QDMA_ST_MODE, QDMA_REG_READ_PF_VF,
- ARRAY_SIZE(c2h_intr_c2h_st_req_field_info),
- c2h_intr_c2h_st_req_field_info
-},
-{"C2H_INTR_H2C_ERR_C2H_MM_MSIX_ACK", 0xb64,
- 1, 0, 0, 0,
- 0, QDMA_ST_MODE, QDMA_REG_READ_PF_ONLY,
- ARRAY_SIZE(c2h_intr_h2c_err_c2h_mm_msix_ack_field_info),
- c2h_intr_h2c_err_c2h_mm_msix_ack_field_info
-},
-{"C2H_INTR_H2C_ERR_C2H_MM_MSIX_FAIL", 0xb68,
- 1, 0, 0, 0,
- 0, QDMA_ST_MODE, QDMA_REG_READ_PF_ONLY,
- ARRAY_SIZE(c2h_intr_h2c_err_c2h_mm_msix_fail_field_info),
- c2h_intr_h2c_err_c2h_mm_msix_fail_field_info
-},
-{"C2H_INTR_H2C_ERR_C2H_MM_MSIX_NO_MSIX", 0xb6c,
- 1, 0, 0, 0,
- 0, QDMA_ST_MODE, QDMA_REG_READ_PF_ONLY,
- ARRAY_SIZE(c2h_intr_h2c_err_c2h_mm_msix_no_msix_field_info),
- c2h_intr_h2c_err_c2h_mm_msix_no_msix_field_info
-},
-{"C2H_INTR_H2C_ERR_C2H_MM_CTXT_INVAL", 0xb70,
- 1, 0, 0, 0,
- 0, QDMA_ST_MODE, QDMA_REG_READ_PF_ONLY,
- ARRAY_SIZE(c2h_intr_h2c_err_c2h_mm_ctxt_inval_field_info),
- c2h_intr_h2c_err_c2h_mm_ctxt_inval_field_info
-},
-{"C2H_INTR_C2H_ST_MSIX_ACK", 0xb74,
- 1, 0, 0, 0,
- 0, QDMA_ST_MODE, QDMA_REG_READ_PF_VF,
- ARRAY_SIZE(c2h_intr_c2h_st_msix_ack_field_info),
- c2h_intr_c2h_st_msix_ack_field_info
-},
-{"C2H_INTR_C2H_ST_MSIX_FAIL", 0xb78,
- 1, 0, 0, 0,
- 0, QDMA_ST_MODE, QDMA_REG_READ_PF_VF,
- ARRAY_SIZE(c2h_intr_c2h_st_msix_fail_field_info),
- c2h_intr_c2h_st_msix_fail_field_info
-},
-{"C2H_INTR_C2H_ST_NO_MSIX", 0xb7c,
- 1, 0, 0, 0,
- 0, QDMA_ST_MODE, QDMA_REG_READ_PF_ONLY,
- ARRAY_SIZE(c2h_intr_c2h_st_no_msix_field_info),
- c2h_intr_c2h_st_no_msix_field_info
-},
-{"C2H_INTR_C2H_ST_CTXT_INVAL", 0xb80,
- 1, 0, 0, 0,
- 0, QDMA_ST_MODE, QDMA_REG_READ_PF_ONLY,
- ARRAY_SIZE(c2h_intr_c2h_st_ctxt_inval_field_info),
- c2h_intr_c2h_st_ctxt_inval_field_info
-},
-{"C2H_STAT_WR_CMP", 0xb84,
- 1, 0, 0, 0,
- 0, QDMA_ST_MODE, QDMA_REG_READ_PF_ONLY,
- ARRAY_SIZE(c2h_stat_wr_cmp_field_info),
- c2h_stat_wr_cmp_field_info
-},
-{"C2H_STAT_DBG_DMA_ENG_4", 0xb88,
- 1, 0, 0, 0,
- 0, QDMA_ST_MODE, QDMA_REG_READ_PF_ONLY,
- ARRAY_SIZE(c2h_stat_dbg_dma_eng_4_field_info),
- c2h_stat_dbg_dma_eng_4_field_info
-},
-{"C2H_STAT_DBG_DMA_ENG_5", 0xb8c,
- 1, 0, 0, 0,
- 0, QDMA_ST_MODE, QDMA_REG_READ_PF_ONLY,
- ARRAY_SIZE(c2h_stat_dbg_dma_eng_5_field_info),
- c2h_stat_dbg_dma_eng_5_field_info
-},
-{"C2H_DBG_PFCH_QID", 0xb90,
- 1, 0, 0, 0,
- 0, QDMA_ST_MODE, QDMA_REG_READ_PF_ONLY,
- ARRAY_SIZE(c2h_dbg_pfch_qid_field_info),
- c2h_dbg_pfch_qid_field_info
-},
-{"C2H_DBG_PFCH", 0xb94,
- 1, 0, 0, 0,
- 0, QDMA_ST_MODE, QDMA_REG_READ_PF_ONLY,
- ARRAY_SIZE(c2h_dbg_pfch_field_info),
- c2h_dbg_pfch_field_info
-},
-{"C2H_INT_DBG", 0xb98,
- 1, 0, 0, 0,
- 0, QDMA_ST_MODE, QDMA_REG_READ_PF_ONLY,
- ARRAY_SIZE(c2h_int_dbg_field_info),
- c2h_int_dbg_field_info
-},
-{"C2H_STAT_IMM_ACCEPTED", 0xb9c,
- 1, 0, 0, 0,
- 0, QDMA_ST_MODE, QDMA_REG_READ_PF_ONLY,
- ARRAY_SIZE(c2h_stat_imm_accepted_field_info),
- c2h_stat_imm_accepted_field_info
-},
-{"C2H_STAT_MARKER_ACCEPTED", 0xba0,
- 1, 0, 0, 0,
- 0, QDMA_ST_MODE, QDMA_REG_READ_PF_ONLY,
- ARRAY_SIZE(c2h_stat_marker_accepted_field_info),
- c2h_stat_marker_accepted_field_info
-},
-{"C2H_STAT_DISABLE_CMP_ACCEPTED", 0xba4,
- 1, 0, 0, 0,
- 0, QDMA_ST_MODE, QDMA_REG_READ_PF_ONLY,
- ARRAY_SIZE(c2h_stat_disable_cmp_accepted_field_info),
- c2h_stat_disable_cmp_accepted_field_info
-},
-{"C2H_PLD_FIFO_CRDT_CNT", 0xba8,
- 1, 0, 0, 0,
- 0, QDMA_ST_MODE, QDMA_REG_READ_PF_ONLY,
- ARRAY_SIZE(c2h_pld_fifo_crdt_cnt_field_info),
- c2h_pld_fifo_crdt_cnt_field_info
-},
-{"H2C_ERR_STAT", 0xe00,
- 1, 0, 0, 0,
- 0, QDMA_ST_MODE, QDMA_REG_READ_PF_VF,
- ARRAY_SIZE(h2c_err_stat_field_info),
- h2c_err_stat_field_info
-},
-{"H2C_ERR_MASK", 0xe04,
- 1, 0, 0, 0,
- 0, QDMA_ST_MODE, QDMA_REG_READ_PF_VF,
- ARRAY_SIZE(h2c_err_mask_field_info),
- h2c_err_mask_field_info
-},
-{"H2C_FIRST_ERR_QID", 0xe08,
- 1, 0, 0, 0,
- 0, QDMA_ST_MODE, QDMA_REG_READ_PF_VF,
- ARRAY_SIZE(h2c_first_err_qid_field_info),
- h2c_first_err_qid_field_info
-},
-{"H2C_DBG_REG0", 0xe0c,
- 1, 0, 0, 0,
- 0, QDMA_ST_MODE, QDMA_REG_READ_PF_ONLY,
- ARRAY_SIZE(h2c_dbg_reg0_field_info),
- h2c_dbg_reg0_field_info
-},
-{"H2C_DBG_REG1", 0xe10,
- 1, 0, 0, 0,
- 0, QDMA_ST_MODE, QDMA_REG_READ_PF_ONLY,
- ARRAY_SIZE(h2c_dbg_reg1_field_info),
- h2c_dbg_reg1_field_info
-},
-{"H2C_DBG_REG2", 0xe14,
- 1, 0, 0, 0,
- 0, QDMA_ST_MODE, QDMA_REG_READ_PF_ONLY,
- ARRAY_SIZE(h2c_dbg_reg2_field_info),
- h2c_dbg_reg2_field_info
-},
-{"H2C_DBG_REG3", 0xe18,
- 1, 0, 0, 0,
- 0, QDMA_ST_MODE, QDMA_REG_READ_PF_ONLY,
- ARRAY_SIZE(h2c_dbg_reg3_field_info),
- h2c_dbg_reg3_field_info
-},
-{"H2C_DBG_REG4", 0xe1c,
- 1, 0, 0, 0,
- 0, QDMA_ST_MODE, QDMA_REG_READ_PF_ONLY,
- ARRAY_SIZE(h2c_dbg_reg4_field_info),
- h2c_dbg_reg4_field_info
-},
-{"H2C_FATAL_ERR_EN", 0xe20,
- 1, 0, 0, 0,
- 0, QDMA_ST_MODE, QDMA_REG_READ_PF_VF,
- ARRAY_SIZE(h2c_fatal_err_en_field_info),
- h2c_fatal_err_en_field_info
-},
-{"C2H_CHANNEL_CTL", 0x1004,
- 1, 0, 0, 0,
- 0, QDMA_MM_MODE, QDMA_REG_READ_PF_ONLY,
- ARRAY_SIZE(c2h_channel_ctl_field_info),
- c2h_channel_ctl_field_info
-},
-{"C2H_CHANNEL_CTL_1", 0x1008,
- 1, 0, 0, 0,
- 0, QDMA_MM_MODE, QDMA_REG_READ_PF_ONLY,
- ARRAY_SIZE(c2h_channel_ctl_1_field_info),
- c2h_channel_ctl_1_field_info
-},
-{"C2H_MM_STATUS", 0x1040,
- 1, 0, 0, 0,
- 0, QDMA_MM_MODE, QDMA_REG_READ_PF_ONLY,
- ARRAY_SIZE(c2h_mm_status_field_info),
- c2h_mm_status_field_info
-},
-{"C2H_CHANNEL_CMPL_DESC_CNT", 0x1048,
- 1, 0, 0, 0,
- 0, QDMA_MM_MODE, QDMA_REG_READ_PF_ONLY,
- ARRAY_SIZE(c2h_channel_cmpl_desc_cnt_field_info),
- c2h_channel_cmpl_desc_cnt_field_info
-},
-{"C2H_MM_ERR_CODE_ENABLE_MASK", 0x1054,
- 1, 0, 0, 0,
- 0, QDMA_MM_MODE, QDMA_REG_READ_PF_ONLY,
- ARRAY_SIZE(c2h_mm_err_code_enable_mask_field_info),
- c2h_mm_err_code_enable_mask_field_info
-},
-{"C2H_MM_ERR_CODE", 0x1058,
- 1, 0, 0, 0,
- 0, QDMA_MM_MODE, QDMA_REG_READ_PF_ONLY,
- ARRAY_SIZE(c2h_mm_err_code_field_info),
- c2h_mm_err_code_field_info
-},
-{"C2H_MM_ERR_INFO", 0x105c,
- 1, 0, 0, 0,
- 0, QDMA_MM_MODE, QDMA_REG_READ_PF_ONLY,
- ARRAY_SIZE(c2h_mm_err_info_field_info),
- c2h_mm_err_info_field_info
-},
-{"C2H_MM_PERF_MON_CTL", 0x10c0,
- 1, 0, 0, 0,
- 0, QDMA_MM_MODE, QDMA_REG_READ_PF_ONLY,
- ARRAY_SIZE(c2h_mm_perf_mon_ctl_field_info),
- c2h_mm_perf_mon_ctl_field_info
-},
-{"C2H_MM_PERF_MON_CYCLE_CNT0", 0x10c4,
- 1, 0, 0, 0,
- 0, QDMA_MM_MODE, QDMA_REG_READ_PF_ONLY,
- ARRAY_SIZE(c2h_mm_perf_mon_cycle_cnt0_field_info),
- c2h_mm_perf_mon_cycle_cnt0_field_info
-},
-{"C2H_MM_PERF_MON_CYCLE_CNT1", 0x10c8,
- 1, 0, 0, 0,
- 0, QDMA_MM_MODE, QDMA_REG_READ_PF_ONLY,
- ARRAY_SIZE(c2h_mm_perf_mon_cycle_cnt1_field_info),
- c2h_mm_perf_mon_cycle_cnt1_field_info
-},
-{"C2H_MM_PERF_MON_DATA_CNT0", 0x10cc,
- 1, 0, 0, 0,
- 0, QDMA_MM_MODE, QDMA_REG_READ_PF_ONLY,
- ARRAY_SIZE(c2h_mm_perf_mon_data_cnt0_field_info),
- c2h_mm_perf_mon_data_cnt0_field_info
-},
-{"C2H_MM_PERF_MON_DATA_CNT1", 0x10d0,
- 1, 0, 0, 0,
- 0, QDMA_MM_MODE, QDMA_REG_READ_PF_ONLY,
- ARRAY_SIZE(c2h_mm_perf_mon_data_cnt1_field_info),
- c2h_mm_perf_mon_data_cnt1_field_info
-},
-{"C2H_MM_DBG", 0x10e8,
- 1, 0, 0, 0,
- 0, QDMA_MM_MODE, QDMA_REG_READ_PF_ONLY,
- ARRAY_SIZE(c2h_mm_dbg_field_info),
- c2h_mm_dbg_field_info
-},
-{"H2C_CHANNEL_CTL", 0x1204,
- 1, 0, 0, 0,
- 0, QDMA_MM_MODE, QDMA_REG_READ_PF_ONLY,
- ARRAY_SIZE(h2c_channel_ctl_field_info),
- h2c_channel_ctl_field_info
-},
-{"H2C_CHANNEL_CTL_1", 0x1208,
- 1, 0, 0, 0,
- 0, QDMA_MM_MODE, QDMA_REG_READ_PF_ONLY,
- ARRAY_SIZE(h2c_channel_ctl_1_field_info),
- h2c_channel_ctl_1_field_info
-},
-{"H2C_CHANNEL_CTL_2", 0x120c,
- 1, 0, 0, 0,
- 0, QDMA_MM_MODE, QDMA_REG_READ_PF_ONLY,
- ARRAY_SIZE(h2c_channel_ctl_2_field_info),
- h2c_channel_ctl_2_field_info
-},
-{"H2C_MM_STATUS", 0x1240,
- 1, 0, 0, 0,
- 0, QDMA_MM_MODE, QDMA_REG_READ_PF_ONLY,
- ARRAY_SIZE(h2c_mm_status_field_info),
- h2c_mm_status_field_info
-},
-{"H2C_CHANNEL_CMPL_DESC_CNT", 0x1248,
- 1, 0, 0, 0,
- 0, QDMA_MM_MODE, QDMA_REG_READ_PF_ONLY,
- ARRAY_SIZE(h2c_channel_cmpl_desc_cnt_field_info),
- h2c_channel_cmpl_desc_cnt_field_info
-},
-{"H2C_MM_ERR_CODE_ENABLE_MASK", 0x1254,
- 1, 0, 0, 0,
- 0, QDMA_MM_MODE, QDMA_REG_READ_PF_ONLY,
- ARRAY_SIZE(h2c_mm_err_code_enable_mask_field_info),
- h2c_mm_err_code_enable_mask_field_info
-},
-{"H2C_MM_ERR_CODE", 0x1258,
- 1, 0, 0, 0,
- 0, QDMA_MM_MODE, QDMA_REG_READ_PF_ONLY,
- ARRAY_SIZE(h2c_mm_err_code_field_info),
- h2c_mm_err_code_field_info
-},
-{"H2C_MM_ERR_INFO", 0x125c,
- 1, 0, 0, 0,
- 0, QDMA_MM_MODE, QDMA_REG_READ_PF_ONLY,
- ARRAY_SIZE(h2c_mm_err_info_field_info),
- h2c_mm_err_info_field_info
-},
-{"H2C_MM_PERF_MON_CTL", 0x12c0,
- 1, 0, 0, 0,
- 0, QDMA_MM_MODE, QDMA_REG_READ_PF_ONLY,
- ARRAY_SIZE(h2c_mm_perf_mon_ctl_field_info),
- h2c_mm_perf_mon_ctl_field_info
-},
-{"H2C_MM_PERF_MON_CYCLE_CNT0", 0x12c4,
- 1, 0, 0, 0,
- 0, QDMA_MM_MODE, QDMA_REG_READ_PF_ONLY,
- ARRAY_SIZE(h2c_mm_perf_mon_cycle_cnt0_field_info),
- h2c_mm_perf_mon_cycle_cnt0_field_info
-},
-{"H2C_MM_PERF_MON_CYCLE_CNT1", 0x12c8,
- 1, 0, 0, 0,
- 0, QDMA_MM_MODE, QDMA_REG_READ_PF_ONLY,
- ARRAY_SIZE(h2c_mm_perf_mon_cycle_cnt1_field_info),
- h2c_mm_perf_mon_cycle_cnt1_field_info
-},
-{"H2C_MM_PERF_MON_DATA_CNT0", 0x12cc,
- 1, 0, 0, 0,
- 0, QDMA_MM_MODE, QDMA_REG_READ_PF_ONLY,
- ARRAY_SIZE(h2c_mm_perf_mon_data_cnt0_field_info),
- h2c_mm_perf_mon_data_cnt0_field_info
-},
-{"H2C_MM_PERF_MON_DATA_CNT1", 0x12d0,
- 1, 0, 0, 0,
- 0, QDMA_MM_MODE, QDMA_REG_READ_PF_ONLY,
- ARRAY_SIZE(h2c_mm_perf_mon_data_cnt1_field_info),
- h2c_mm_perf_mon_data_cnt1_field_info
-},
-{"H2C_MM_DBG", 0x12e8,
- 1, 0, 0, 0,
- 0, QDMA_MM_MODE, QDMA_REG_READ_PF_ONLY,
- ARRAY_SIZE(h2c_mm_dbg_field_info),
- h2c_mm_dbg_field_info
-},
-{"FUNC_STATUS_REG", 0x2400,
- 1, 0, 0, 0,
- 0, QDMA_MAILBOX, QDMA_REG_READ_PF_ONLY,
- ARRAY_SIZE(func_status_reg_field_info),
- func_status_reg_field_info
-},
-{"FUNC_CMD_REG", 0x2404,
- 1, 0, 0, 0,
- 0, QDMA_MAILBOX, QDMA_REG_READ_PF_ONLY,
- ARRAY_SIZE(func_cmd_reg_field_info),
- func_cmd_reg_field_info
-},
-{"FUNC_INTERRUPT_VECTOR_REG", 0x2408,
- 1, 0, 0, 0,
- 0, QDMA_MAILBOX, QDMA_REG_READ_PF_ONLY,
- ARRAY_SIZE(func_interrupt_vector_reg_field_info),
- func_interrupt_vector_reg_field_info
-},
-{"TARGET_FUNC_REG", 0x240c,
- 1, 0, 0, 0,
- 0, QDMA_MAILBOX, QDMA_REG_READ_PF_ONLY,
- ARRAY_SIZE(target_func_reg_field_info),
- target_func_reg_field_info
-},
-{"FUNC_INTERRUPT_CTL_REG", 0x2410,
- 1, 0, 0, 0,
- 0, QDMA_MAILBOX, QDMA_REG_READ_PF_ONLY,
- ARRAY_SIZE(func_interrupt_ctl_reg_field_info),
- func_interrupt_ctl_reg_field_info
-},
-
-};
-
-uint32_t qdma_s80_hard_config_num_regs_get(void)
-{
- return (sizeof(qdma_s80_hard_config_regs)/
- sizeof(qdma_s80_hard_config_regs[0]));
-}
-
-struct xreg_info *qdma_s80_hard_config_regs_get(void)
-{
- return qdma_s80_hard_config_regs;
-}
-
diff --git a/QDMA/DPDK/drivers/net/qdma/qdma_access/qdma_soft_access/qdma_soft_access.c b/QDMA/DPDK/drivers/net/qdma/qdma_access/qdma_soft_access/qdma_soft_access.c
old mode 100644
new mode 100755
index 2b333c16f8d284b8d46e1992e9c17529efff4dd7..0b242aa4e8678705fce44e6f7247a855dccb695d
--- a/QDMA/DPDK/drivers/net/qdma/qdma_access/qdma_soft_access/qdma_soft_access.c
+++ b/QDMA/DPDK/drivers/net/qdma/qdma_access/qdma_soft_access/qdma_soft_access.c
@@ -1,5 +1,6 @@
/*
- * Copyright(c) 2019-2022 Xilinx, Inc. All rights reserved.
+ * Copyright (c) 2019-2022, Xilinx, Inc. All rights reserved.
+ * Copyright (c) 2022, Advanced Micro Devices, Inc. All rights reserved.
*
* BSD LICENSE
*
@@ -2478,7 +2479,7 @@ int qdma_get_version(void *dev_hndl, uint8_t is_vf,
reg_val = qdma_reg_read(dev_hndl, reg_addr);
- qdma_fetch_version_details(is_vf, reg_val, version_info);
+ qdma_fetch_version_details(dev_hndl, is_vf, reg_val, version_info);
return QDMA_SUCCESS;
}
diff --git a/QDMA/DPDK/drivers/net/qdma/qdma_access/qdma_soft_access/qdma_soft_access.h b/QDMA/DPDK/drivers/net/qdma/qdma_access/qdma_soft_access/qdma_soft_access.h
old mode 100644
new mode 100755
index 433351b06cc86acce13bdf42cb6d0fd87cfe81b7..6640987bd60f3d71d3a513054ce2f7b6606daa2a
--- a/QDMA/DPDK/drivers/net/qdma/qdma_access/qdma_soft_access/qdma_soft_access.h
+++ b/QDMA/DPDK/drivers/net/qdma/qdma_access/qdma_soft_access/qdma_soft_access.h
@@ -1,5 +1,6 @@
/*
- * Copyright(c) 2019-2022 Xilinx, Inc. All rights reserved.
+ * Copyright (c) 2019-2022, Xilinx, Inc. All rights reserved.
+ * Copyright (c) 2022, Advanced Micro Devices, Inc. All rights reserved.
*
* BSD LICENSE
*
diff --git a/QDMA/DPDK/drivers/net/qdma/qdma_access/qdma_soft_access/qdma_soft_reg.h b/QDMA/DPDK/drivers/net/qdma/qdma_access/qdma_soft_access/qdma_soft_reg.h
old mode 100644
new mode 100755
index 45ee8f0fc4e81c14f4f33e7af2ba09246da1cca2..53671a6b959caa0848c86098fc82c25d619fb6e3
--- a/QDMA/DPDK/drivers/net/qdma/qdma_access/qdma_soft_access/qdma_soft_reg.h
+++ b/QDMA/DPDK/drivers/net/qdma/qdma_access/qdma_soft_access/qdma_soft_reg.h
@@ -1,5 +1,6 @@
/*
- * Copyright(c) 2019-2022 Xilinx, Inc. All rights reserved.
+ * Copyright (c) 2019-2022, Xilinx, Inc. All rights reserved.
+ * Copyright (c) 2022, Advanced Micro Devices, Inc. All rights reserved.
*
* BSD LICENSE
*
diff --git a/QDMA/DPDK/drivers/net/qdma/qdma_common.c b/QDMA/DPDK/drivers/net/qdma/qdma_common.c
old mode 100644
new mode 100755
index 89486eb2a501444a0a045be305a4e1407fb98060..bbbc5fe04a95422989a9d9e53a922d7bedbe341b
--- a/QDMA/DPDK/drivers/net/qdma/qdma_common.c
+++ b/QDMA/DPDK/drivers/net/qdma/qdma_common.c
@@ -1,7 +1,8 @@
/*-
* BSD LICENSE
*
- * Copyright(c) 2017-2022 Xilinx, Inc. All rights reserved.
+ * Copyright (c) 2017-2022 Xilinx, Inc. All rights reserved.
+ * Copyright (c) 2022, Advanced Micro Devices, Inc. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
@@ -74,7 +75,12 @@ uint32_t qdma_pci_read_reg(struct rte_eth_dev *dev, uint32_t bar, uint32_t reg)
printf("Error: PCI BAR number:%u not mapped\n", bar);
return -1;
}
+
+#ifdef TANDEM_BOOT_SUPPORTED
+ val = *((volatile uint64_t *)(baseaddr + reg));
+#else
val = *((volatile uint32_t *)(baseaddr + reg));
+#endif
return val;
}
@@ -96,7 +102,12 @@ void qdma_pci_write_reg(struct rte_eth_dev *dev, uint32_t bar,
printf("Error: PCI BAR number:%u not mapped\n", bar);
return;
}
+
+#ifdef TANDEM_BOOT_SUPPORTED
+ *((volatile uint64_t *)(baseaddr + reg)) = val;
+#else
*((volatile uint32_t *)(baseaddr + reg)) = val;
+#endif
}
void qdma_reset_rx_queue(struct qdma_rx_queue *rxq)
diff --git a/QDMA/DPDK/drivers/net/qdma/qdma_devops.c b/QDMA/DPDK/drivers/net/qdma/qdma_devops.c
old mode 100644
new mode 100755
index 03ba78f95b2560ee00eeb4ba8a2d5a5e57add037..2fe312fbecf3e4f83d2ff314c7d02a48b455fed2
--- a/QDMA/DPDK/drivers/net/qdma/qdma_devops.c
+++ b/QDMA/DPDK/drivers/net/qdma/qdma_devops.c
@@ -1,7 +1,8 @@
/*-
* BSD LICENSE
*
- * Copyright(c) 2017-2022 Xilinx, Inc. All rights reserved.
+ * Copyright (c) 2017-2022 Xilinx, Inc. All rights reserved.
+ * Copyright (c) 2022, Advanced Micro Devices, Inc. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
diff --git a/QDMA/DPDK/drivers/net/qdma/qdma_devops.h b/QDMA/DPDK/drivers/net/qdma/qdma_devops.h
old mode 100644
new mode 100755
index c408d28034ccb4de703c8d4855c6fd66bbbfa480..586a4b333f488b2c584131db528f9b27d277f9ba
--- a/QDMA/DPDK/drivers/net/qdma/qdma_devops.h
+++ b/QDMA/DPDK/drivers/net/qdma/qdma_devops.h
@@ -1,7 +1,8 @@
/*-
* BSD LICENSE
*
- * Copyright(c) 2020-2022 Xilinx, Inc. All rights reserved.
+ * Copyright (c) 2020-2022 Xilinx, Inc. All rights reserved.
+ * Copyright (c) 2022, Advanced Micro Devices, Inc. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
diff --git a/QDMA/DPDK/drivers/net/qdma/qdma_ethdev.c b/QDMA/DPDK/drivers/net/qdma/qdma_ethdev.c
old mode 100644
new mode 100755
index 7f9b0a31ac30dcd16804e103989e1f2dca812402..50c132d7497fa10dbd87bf3013ef90851b3132bc
--- a/QDMA/DPDK/drivers/net/qdma/qdma_ethdev.c
+++ b/QDMA/DPDK/drivers/net/qdma/qdma_ethdev.c
@@ -1,7 +1,8 @@
/*-
* BSD LICENSE
*
- * Copyright(c) 2017-2022 Xilinx, Inc. All rights reserved.
+ * Copyright (c) 2017-2022 Xilinx, Inc. All rights reserved.
+ * Copyright (c) 2022, Advanced Micro Devices, Inc. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
@@ -250,6 +251,13 @@ static struct rte_pci_id qdma_pci_id_tbl[] = {
RTE_PCI_DEV_ID_DECL(PCI_VENDOR_ID_XILINX, 0xb248) /** PF 2 */
RTE_PCI_DEV_ID_DECL(PCI_VENDOR_ID_XILINX, 0xb348) /** PF 3 */
+ /** Gen 5 PF */
+ /** PCIe lane width x8 */
+ RTE_PCI_DEV_ID_DECL(PCI_VENDOR_ID_XILINX, 0xb058) /** PF 0 */
+ RTE_PCI_DEV_ID_DECL(PCI_VENDOR_ID_XILINX, 0xb158) /** PF 1 */
+ RTE_PCI_DEV_ID_DECL(PCI_VENDOR_ID_XILINX, 0xb258) /** PF 2 */
+ RTE_PCI_DEV_ID_DECL(PCI_VENDOR_ID_XILINX, 0xb358) /** PF 3 */
+
{ .vendor_id = 0, /* sentinel */ },
};
diff --git a/QDMA/DPDK/drivers/net/qdma/qdma_log.h b/QDMA/DPDK/drivers/net/qdma/qdma_log.h
old mode 100644
new mode 100755
index efac25ca1508ba6200b6c1989c640c55cb1ea5f7..a6922693a92f9dac7fff84d01317d79874a34c7d
--- a/QDMA/DPDK/drivers/net/qdma/qdma_log.h
+++ b/QDMA/DPDK/drivers/net/qdma/qdma_log.h
@@ -1,7 +1,8 @@
/*-
* BSD LICENSE
*
- * Copyright(c) 2019-2022 Xilinx, Inc. All rights reserved.
+ * Copyright (c) 2019-2022 Xilinx, Inc. All rights reserved.
+ * Copyright (c) 2022, Advanced Micro Devices, Inc. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
diff --git a/QDMA/DPDK/drivers/net/qdma/qdma_mbox.c b/QDMA/DPDK/drivers/net/qdma/qdma_mbox.c
old mode 100644
new mode 100755
index 1915377da101d96f070748ec9ce819e8d371f8c0..63a31de5811cdc6625107495ba11c6b4b7bfece0
--- a/QDMA/DPDK/drivers/net/qdma/qdma_mbox.c
+++ b/QDMA/DPDK/drivers/net/qdma/qdma_mbox.c
@@ -1,7 +1,8 @@
/*-
* BSD LICENSE
*
- * Copyright(c) 2019-2022 Xilinx, Inc. All rights reserved.
+ * Copyright (c) 2019-2022 Xilinx, Inc. All rights reserved.
+ * Copyright (c) 2022, Advanced Micro Devices, Inc. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
diff --git a/QDMA/DPDK/drivers/net/qdma/qdma_mbox.h b/QDMA/DPDK/drivers/net/qdma/qdma_mbox.h
old mode 100644
new mode 100755
index d1364d838beeb008556cde5badf1ef1b8c415965..ff4fa588dd56c62a3c49d4c0d17800d30848ce95
--- a/QDMA/DPDK/drivers/net/qdma/qdma_mbox.h
+++ b/QDMA/DPDK/drivers/net/qdma/qdma_mbox.h
@@ -1,7 +1,8 @@
/*-
* BSD LICENSE
*
- * Copyright(c) 2019-2022 Xilinx, Inc. All rights reserved.
+ * Copyright (c) 2019-2022 Xilinx, Inc. All rights reserved.
+ * Copyright (c) 2022, Advanced Micro Devices, Inc. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
diff --git a/QDMA/DPDK/drivers/net/qdma/qdma_platform.c b/QDMA/DPDK/drivers/net/qdma/qdma_platform.c
old mode 100644
new mode 100755
index 5e8bda9dc79ad698a4a2e3243dc72b410c66e431..ba0d54eeb74832214c95d16a292761a30906b902
--- a/QDMA/DPDK/drivers/net/qdma/qdma_platform.c
+++ b/QDMA/DPDK/drivers/net/qdma/qdma_platform.c
@@ -1,7 +1,8 @@
/*-
* BSD LICENSE
*
- * Copyright(c) 2019-2022 Xilinx, Inc. All rights reserved.
+ * Copyright (c) 2019-2022 Xilinx, Inc. All rights reserved.
+ * Copyright (c) 2022, Advanced Micro Devices, Inc. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
diff --git a/QDMA/DPDK/drivers/net/qdma/qdma_platform_env.h b/QDMA/DPDK/drivers/net/qdma/qdma_platform_env.h
old mode 100644
new mode 100755
index 832d66a1423d8b4d192e2de4b7987b9e39d1652a..5bc4fbba6e30c9657a8d8dbad765019aed266572
--- a/QDMA/DPDK/drivers/net/qdma/qdma_platform_env.h
+++ b/QDMA/DPDK/drivers/net/qdma/qdma_platform_env.h
@@ -1,7 +1,8 @@
/*-
* BSD LICENSE
*
- * Copyright(c) 2019-2022 Xilinx, Inc. All rights reserved.
+ * Copyright (c) 2019-2022 Xilinx, Inc. All rights reserved.
+ * Copyright (c) 2022, Advanced Micro Devices, Inc. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
diff --git a/QDMA/DPDK/drivers/net/qdma/qdma_rxtx.c b/QDMA/DPDK/drivers/net/qdma/qdma_rxtx.c
old mode 100644
new mode 100755
index fc88c4e9f2f2ec4fcd0811fba985e9f324f0a9fb..06f0818879d7fc49cce630d94d631eebc72803c0
--- a/QDMA/DPDK/drivers/net/qdma/qdma_rxtx.c
+++ b/QDMA/DPDK/drivers/net/qdma/qdma_rxtx.c
@@ -1,7 +1,8 @@
/*-
* BSD LICENSE
*
- * Copyright(c) 2017-2022 Xilinx, Inc. All rights reserved.
+ * Copyright (c) 2017-2022 Xilinx, Inc. All rights reserved.
+ * Copyright (c) 2022, Advanced Micro Devices, Inc. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
@@ -344,7 +345,7 @@ void qdma_get_device_info(void *queue_hndl,
*ip_type = (enum qdma_ip_type)qdma_dev->ip_type;
}
-uint32_t get_mm_c2h_ep_addr(void *queue_hndl)
+uint64_t get_mm_c2h_ep_addr(void *queue_hndl)
{
struct qdma_rx_queue *rxq = (struct qdma_rx_queue *)queue_hndl;
@@ -395,7 +396,7 @@ struct qdma_ul_mm_desc *get_mm_h2c_desc(void *queue_hndl)
return desc;
}
-uint32_t get_mm_h2c_ep_addr(void *queue_hndl)
+uint64_t get_mm_h2c_ep_addr(void *queue_hndl)
{
struct qdma_tx_queue *txq = (struct qdma_tx_queue *)queue_hndl;
@@ -1604,7 +1605,9 @@ uint16_t qdma_xmit_pkts_mm(struct qdma_tx_queue *txq, struct rte_mbuf **tx_pkts,
PMD_DRV_LOG(DEBUG, "xmit number of bytes:%ld, count:%d ",
len, count);
+#ifndef TANDEM_BOOT_SUPPORTED
txq->ep_addr = (txq->ep_addr + len) % DMA_BRAM_SIZE;
+#endif
id = txq->q_pidx_info.pidx;
}
diff --git a/QDMA/DPDK/drivers/net/qdma/qdma_rxtx.h b/QDMA/DPDK/drivers/net/qdma/qdma_rxtx.h
old mode 100644
new mode 100755
index 94e0d21929e32357b43f5b68127a16007e2f7784..32123e4701b1af0758a6cd633a1b6ef5a05819e6
--- a/QDMA/DPDK/drivers/net/qdma/qdma_rxtx.h
+++ b/QDMA/DPDK/drivers/net/qdma/qdma_rxtx.h
@@ -1,7 +1,8 @@
/*-
* BSD LICENSE
*
- * Copyright(c) 2019-2022 Xilinx, Inc. All rights reserved.
+ * Copyright (c) 2019-2022 Xilinx, Inc. All rights reserved.
+ * Copyright (c) 2022, Advanced Micro Devices, Inc. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
@@ -41,8 +42,8 @@ void qdma_get_device_info(void *queue_hndl,
enum qdma_ip_type *ip_type);
struct qdma_ul_st_h2c_desc *get_st_h2c_desc(void *queue_hndl);
struct qdma_ul_mm_desc *get_mm_h2c_desc(void *queue_hndl);
-uint32_t get_mm_c2h_ep_addr(void *queue_hndl);
-uint32_t get_mm_h2c_ep_addr(void *queue_hndl);
+uint64_t get_mm_c2h_ep_addr(void *queue_hndl);
+uint64_t get_mm_h2c_ep_addr(void *queue_hndl);
uint32_t get_mm_buff_size(void *queue_hndl);
#endif /* QDMA_DPDK_RXTX_H_ */
diff --git a/QDMA/DPDK/drivers/net/qdma/qdma_user.c b/QDMA/DPDK/drivers/net/qdma/qdma_user.c
old mode 100644
new mode 100755
index d1543159d59c6727728bc11a209196dd1f84276f..ac3bfb86f64a2e05e5676f83575c0e52754031c7
--- a/QDMA/DPDK/drivers/net/qdma/qdma_user.c
+++ b/QDMA/DPDK/drivers/net/qdma/qdma_user.c
@@ -1,7 +1,8 @@
/*-
* BSD LICENSE
*
- * Copyright(c) 2019-2022 Xilinx, Inc. All rights reserved.
+ * Copyright (c) 2019-2022 Xilinx, Inc. All rights reserved.
+ * Copyright (c) 2022, Advanced Micro Devices, Inc. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
diff --git a/QDMA/DPDK/drivers/net/qdma/qdma_user.h b/QDMA/DPDK/drivers/net/qdma/qdma_user.h
old mode 100644
new mode 100755
index 0368f28eda821bde8c9b8ce63707ca6a5c1250c8..ee20be015e210c3c1c19603559400e1e60a20e12
--- a/QDMA/DPDK/drivers/net/qdma/qdma_user.h
+++ b/QDMA/DPDK/drivers/net/qdma/qdma_user.h
@@ -1,7 +1,8 @@
/*-
* BSD LICENSE
*
- * Copyright(c) 2018-2022 Xilinx, Inc. All rights reserved.
+ * Copyright (c) 2018-2022 Xilinx, Inc. All rights reserved.
+ * Copyright (c) 2022, Advanced Micro Devices, Inc. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
diff --git a/QDMA/DPDK/drivers/net/qdma/qdma_vf_ethdev.c b/QDMA/DPDK/drivers/net/qdma/qdma_vf_ethdev.c
old mode 100644
new mode 100755
index 48c12f0e9ae6efd66dde38ab9e84883678aac4be..e4366557cf55a3e85ebb2168b1ae9254e3691e6f
--- a/QDMA/DPDK/drivers/net/qdma/qdma_vf_ethdev.c
+++ b/QDMA/DPDK/drivers/net/qdma/qdma_vf_ethdev.c
@@ -1,7 +1,8 @@
/*-
* BSD LICENSE
*
- * Copyright(c) 2017-2022 Xilinx, Inc. All rights reserved.
+ * Copyright (c) 2017-2022 Xilinx, Inc. All rights reserved.
+ * Copyright (c) 2022, Advanced Micro Devices, Inc. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
@@ -234,6 +235,13 @@ static struct rte_pci_id qdma_vf_pci_id_tbl[] = {
RTE_PCI_DEV_ID_DECL(PCI_VENDOR_ID_XILINX, 0xc248) /* VF on PF 2 */
RTE_PCI_DEV_ID_DECL(PCI_VENDOR_ID_XILINX, 0xc348) /* VF on PF 3 */
+ /** Gen 5 VF */
+ /** PCIe lane width x8 */
+ RTE_PCI_DEV_ID_DECL(PCI_VENDOR_ID_XILINX, 0xc058) /* VF on PF 0 */
+ RTE_PCI_DEV_ID_DECL(PCI_VENDOR_ID_XILINX, 0xc158) /* VF on PF 1 */
+ RTE_PCI_DEV_ID_DECL(PCI_VENDOR_ID_XILINX, 0xc258) /* VF on PF 2 */
+ RTE_PCI_DEV_ID_DECL(PCI_VENDOR_ID_XILINX, 0xc358) /* VF on PF 3 */
+
{ .vendor_id = 0, /* sentinel */ },
};
diff --git a/QDMA/DPDK/drivers/net/qdma/qdma_xdebug.c b/QDMA/DPDK/drivers/net/qdma/qdma_xdebug.c
old mode 100644
new mode 100755
index 8617413d858ac875919895547017ecdbed7cd767..362add86ece9e368342fe06bb927ef3a0bd96176
--- a/QDMA/DPDK/drivers/net/qdma/qdma_xdebug.c
+++ b/QDMA/DPDK/drivers/net/qdma/qdma_xdebug.c
@@ -1,7 +1,8 @@
/*-
* BSD LICENSE
*
- * Copyright(c) 2017-2022 Xilinx, Inc. All rights reserved.
+ * Copyright (c) 2017-2022 Xilinx, Inc. All rights reserved.
+ * Copyright (c) 2022, Advanced Micro Devices, Inc. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
@@ -121,7 +122,7 @@ static int qdma_h2c_struct_dump(uint8_t port_id, uint16_t queue)
tx_q->port_id);
xdebug_info("\t\t ringszidx :%x\n",
tx_q->ringszidx);
- xdebug_info("\t\t ep_addr :%x\n",
+ xdebug_info("\t\t ep_addr :0x%" PRIx64 "\n",
tx_q->ep_addr);
}
@@ -170,7 +171,7 @@ static int qdma_c2h_struct_dump(uint8_t port_id, uint16_t queue)
rx_q->nb_rx_desc);
xdebug_info("\t\t nb_rx_cmpt_desc :%x\n",
rx_q->nb_rx_cmpt_desc);
- xdebug_info("\t\t ep_addr :%x\n",
+ xdebug_info("\t\t ep_addr :0x%" PRIx64 "\n",
rx_q->ep_addr);
xdebug_info("\t\t st_mode :%x\n",
rx_q->st_mode);
diff --git a/QDMA/DPDK/drivers/net/qdma/rte_pmd_qdma.c b/QDMA/DPDK/drivers/net/qdma/rte_pmd_qdma.c
old mode 100644
new mode 100755
index 2b99d258938b9f015b25e1f1eb1c26fc460cff0e..a4ff685c76d6b379da31c3b609a278a7037d4d6f
--- a/QDMA/DPDK/drivers/net/qdma/rte_pmd_qdma.c
+++ b/QDMA/DPDK/drivers/net/qdma/rte_pmd_qdma.c
@@ -1,7 +1,8 @@
/*-
* BSD LICENSE
*
- * Copyright(c) 2019-2022 Xilinx, Inc. All rights reserved.
+ * Copyright (c) 2019-2022 Xilinx, Inc. All rights reserved.
+ * Copyright (c) 2022, Advanced Micro Devices, Inc. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
@@ -893,7 +894,7 @@ int rte_pmd_qdma_set_c2h_descriptor_prefetch(int port_id, uint32_t qid,
* (rte_eth_tx_burst() and rte_eth_rx_burst()) are called.
*****************************************************************************/
int rte_pmd_qdma_set_mm_endpoint_addr(int port_id, uint32_t qid,
- enum rte_pmd_qdma_dir_type dir, uint32_t addr)
+ enum rte_pmd_qdma_dir_type dir, uint64_t addr)
{
struct rte_eth_dev *dev;
struct qdma_pci_dev *qdma_dev;
diff --git a/QDMA/DPDK/drivers/net/qdma/rte_pmd_qdma.h b/QDMA/DPDK/drivers/net/qdma/rte_pmd_qdma.h
old mode 100644
new mode 100755
index 346dc1cabc7afa13a56c4065c85ecfefc9a16439..8cd3dc6956e62624229d2200d0e782dbc387f992
--- a/QDMA/DPDK/drivers/net/qdma/rte_pmd_qdma.h
+++ b/QDMA/DPDK/drivers/net/qdma/rte_pmd_qdma.h
@@ -1,7 +1,8 @@
/*-
* BSD LICENSE
*
- * Copyright(c) 2019-2022 Xilinx, Inc. All rights reserved.
+ * Copyright (c) 2019-2022 Xilinx, Inc. All rights reserved.
+ * Copyright (c) 2022, Advanced Micro Devices, Inc. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
@@ -587,7 +588,7 @@ int rte_pmd_qdma_set_c2h_descriptor_prefetch(int port_id, uint32_t qid,
* @ingroup rte_pmd_qdma_func
*****************************************************************************/
int rte_pmd_qdma_set_mm_endpoint_addr(int port_id, uint32_t qid,
- enum rte_pmd_qdma_dir_type dir, uint32_t addr);
+ enum rte_pmd_qdma_dir_type dir, uint64_t addr);
/******************************************************************************/
/**
diff --git a/QDMA/DPDK/drivers/net/qdma/version.h b/QDMA/DPDK/drivers/net/qdma/version.h
old mode 100644
new mode 100755
index b1c48828f8702b0b8fd7b4ab43b690833b02ad31..b4b0fc4c351e9a13665e15f5b8ec1ef69495701e
--- a/QDMA/DPDK/drivers/net/qdma/version.h
+++ b/QDMA/DPDK/drivers/net/qdma/version.h
@@ -1,7 +1,8 @@
/*-
* BSD LICENSE
*
- * Copyright(c) 2017-2022 Xilinx, Inc. All rights reserved.
+ * Copyright (c) 2017-2022 Xilinx, Inc. All rights reserved.
+ * Copyright (c) 2022, Advanced Micro Devices, Inc. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
@@ -38,7 +39,7 @@
#define QDMA_PMD_MAJOR 2022
#define QDMA_PMD_MINOR 1
-#define QDMA_PMD_PATCHLEVEL 1
+#define QDMA_PMD_PATCHLEVEL 3
#define QDMA_PMD_VERSION \
qdma_stringify(QDMA_PMD_MAJOR) "." \
diff --git a/QDMA/DPDK/drivers/net/qdma/version.map b/QDMA/DPDK/drivers/net/qdma/version.map
old mode 100644
new mode 100755
index f95533b4360736869e6146510bd60f874295c4d3..840223b482b102f3d0890216186299e3b39378c4
--- a/QDMA/DPDK/drivers/net/qdma/version.map
+++ b/QDMA/DPDK/drivers/net/qdma/version.map
@@ -1,7 +1,8 @@
/*-
* BSD LICENSE
*
- * Copyright(c) 2017-2022 Xilinx, Inc. All rights reserved.
+ * Copyright (c) 2017-2022 Xilinx, Inc. All rights reserved.
+ * Copyright (c) 2022, Advanced Micro Devices, Inc. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
diff --git a/QDMA/DPDK/examples/qdma_testapp/Makefile b/QDMA/DPDK/examples/qdma_testapp/Makefile
old mode 100644
new mode 100755
index 830a1d6a2af4a58927ed8c3d20a8b2d847f9aaaf..89f9cf21a5d87fd9cc9f22f9cc0c75752b394836
--- a/QDMA/DPDK/examples/qdma_testapp/Makefile
+++ b/QDMA/DPDK/examples/qdma_testapp/Makefile
@@ -1,6 +1,7 @@
# BSD LICENSE
#
-# Copyright(c) 2017-2022 Xilinx, Inc. All rights reserved.
+# Copyright (c) 2017-2022 Xilinx, Inc. All rights reserved.
+# Copyright (c) 2022, Advanced Micro Devices, Inc. All rights reserved.
#
# Redistribution and use in source and binary forms, with or without
# modification, are permitted provided that the following conditions
diff --git a/QDMA/DPDK/examples/qdma_testapp/commands.c b/QDMA/DPDK/examples/qdma_testapp/commands.c
old mode 100644
new mode 100755
index b78354e709f9d5c0a3a10087177dfddc133c2a5b..7a6cee9e91dc6633b08152145db4a79555de960b
--- a/QDMA/DPDK/examples/qdma_testapp/commands.c
+++ b/QDMA/DPDK/examples/qdma_testapp/commands.c
@@ -1,7 +1,8 @@
/*-
* BSD LICENSE
*
- * Copyright(c) 2017-2022 Xilinx, Inc. All rights reserved.
+ * Copyright (c) 2017-2022 Xilinx, Inc. All rights reserved.
+ * Copyright (c) 2022, Advanced Micro Devices, Inc. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
@@ -33,7 +34,7 @@
/*-
* BSD LICENSE
*
- * Copyright(c) 2010-2014 Intel Corporation. All rights reserved.
+ * Copyright (c) 2010-2014 Intel Corporation. All rights reserved.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
@@ -612,9 +613,10 @@ static void cmd_obj_dma_to_device_parsed(void *parsed_result,
int ld_size = 0, loop = 0, ret, j, zbyte = 0, user_bar_idx;
off_t ret_val;
int port_id = 0, num_queues = 0, input_size = 0, num_loops = 0;
- int dst_addr = 0;
+ uint64_t dst_addr = 0;
uint32_t regval = 0;
unsigned int q_data_size = 0;
+ char *p = NULL;
cmdline_printf(cl, "xmit on Port:%s, filename:%s, num-queues:%s\n\n",
res->port_id, res->filename, res->queues);
@@ -651,15 +653,18 @@ static void cmd_obj_dma_to_device_parsed(void *parsed_result,
return;
}
user_bar_idx = pinfo[port_id].user_bar_idx;
+
+#if !defined(TANDEM_BOOT_SUPPORTED)
regval = PciRead(user_bar_idx, C2H_CONTROL_REG, port_id);
+#endif
input_size = atoi(res->size);
num_loops = atoi(res->loops);
- dst_addr = atoi(res->dst_addr);
+ dst_addr = strtoull(res->dst_addr, &p, 0);
-#ifndef PERF_BENCHMARK
+#if !defined(PERF_BENCHMARK) && !defined(TANDEM_BOOT_SUPPORTED)
if (dst_addr + input_size > BRAM_SIZE) {
- cmdline_printf(cl, "Error: (dst_addr %d + input size "
+ cmdline_printf(cl, "Error: (dst_addr %ld + input size "
"%d) shall be less than "
"BRAM_SIZE %d.\n", dst_addr,
input_size, BRAM_SIZE);
@@ -691,14 +696,17 @@ static void cmd_obj_dma_to_device_parsed(void *parsed_result,
do {
total_size = input_size;
- dst_addr = atoi(res->dst_addr);
+ dst_addr = strtoull(res->dst_addr, &p, 0);
q_data_size = 0;
/* transmit data on the number of Queues configured
* from the input file
*/
for (i = 0, j = 0; i < num_queues; i++, j++) {
dst_addr += q_data_size;
+
+#ifndef TANDEM_BOOT_SUPPORTED
dst_addr %= BRAM_SIZE;
+#endif
if ((unsigned int)i >=
pinfo[port_id].st_queues) {
@@ -839,7 +847,7 @@ static void cmd_obj_dma_from_device_parsed(void *parsed_result,
int loop = 0, ret, j;
off_t ret_val;
int port_id = 0, num_queues = 0, input_size = 0, num_loops = 0;
- int src_addr = 0;
+ uint64_t src_addr = 0;
unsigned int q_data_size = 0;
cmdline_printf(cl, "recv on Port:%s, filename:%s\n",
@@ -881,7 +889,7 @@ static void cmd_obj_dma_from_device_parsed(void *parsed_result,
src_addr = atoi(res->src_addr);
#ifndef PERF_BENCHMARK
if (src_addr + input_size > BRAM_SIZE) {
- cmdline_printf(cl, "Error: (src_addr %d + input "
+ cmdline_printf(cl, "Error: (src_addr %ld + input "
"size %d) shall be less than "
"BRAM_SIZE %d.\n", src_addr,
input_size, BRAM_SIZE);
diff --git a/QDMA/DPDK/examples/qdma_testapp/commands.h b/QDMA/DPDK/examples/qdma_testapp/commands.h
old mode 100644
new mode 100755
index 2db9af5b6e8b7a967f1f7598e7c290a5254f80a1..75d53433c93a76dc5c2a33a5a0f9e754c3d77d1b
--- a/QDMA/DPDK/examples/qdma_testapp/commands.h
+++ b/QDMA/DPDK/examples/qdma_testapp/commands.h
@@ -1,7 +1,7 @@
/*-
* BSD LICENSE
*
- * Copyright(c) 2010-2022 Intel Corporation. All rights reserved.
+ * Copyright (c) 2010-2022 Intel Corporation. All rights reserved.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
diff --git a/QDMA/DPDK/examples/qdma_testapp/parse_obj_list.c b/QDMA/DPDK/examples/qdma_testapp/parse_obj_list.c
old mode 100644
new mode 100755
index 7383a249ca543db1cf19428daa7aa359e83beef4..26c6cd999bb403b850a89d0680c620d97c8d6d62
--- a/QDMA/DPDK/examples/qdma_testapp/parse_obj_list.c
+++ b/QDMA/DPDK/examples/qdma_testapp/parse_obj_list.c
@@ -1,7 +1,8 @@
/*-
* BSD LICENSE
*
- * Copyright(c) 2017-2022 Xilinx, Inc. All rights reserved.
+ * Copyright (c) 2017-2022 Xilinx, Inc. All rights reserved.
+ * Copyright (c) 2022, Advanced Micro Devices, Inc. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
@@ -33,7 +34,7 @@
/*-
* BSD LICENSE
*
- * Copyright(c) 2010-2014 Intel Corporation. All rights reserved.
+ * Copyright (c) 2010-2014 Intel Corporation. All rights reserved.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
diff --git a/QDMA/DPDK/examples/qdma_testapp/parse_obj_list.h b/QDMA/DPDK/examples/qdma_testapp/parse_obj_list.h
old mode 100644
new mode 100755
index 5b1efdc804c0be0c62cd78d48eee2423f7050265..711d5c05362a651aabcddd98902b193c46af7d4a
--- a/QDMA/DPDK/examples/qdma_testapp/parse_obj_list.h
+++ b/QDMA/DPDK/examples/qdma_testapp/parse_obj_list.h
@@ -1,7 +1,8 @@
/*-
* BSD LICENSE
*
- * Copyright(c) 2017-2022 Xilinx, Inc. All rights reserved.
+ * Copyright (c) 2017-2022 Xilinx, Inc. All rights reserved.
+ * Copyright (c) 2022, Advanced Micro Devices, Inc. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
@@ -33,7 +34,7 @@
/*-
* BSD LICENSE
*
- * Copyright(c) 2010-2014 Intel Corporation. All rights reserved.
+ * Copyright (c) 2010-2014 Intel Corporation. All rights reserved.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
diff --git a/QDMA/DPDK/examples/qdma_testapp/pcierw.c b/QDMA/DPDK/examples/qdma_testapp/pcierw.c
old mode 100644
new mode 100755
index d812db4e0fe8ef9e6ba9611f4a6066b0cb28c87c..dcf4e8bddf796897419a3af5a962408d8e9b7df9
--- a/QDMA/DPDK/examples/qdma_testapp/pcierw.c
+++ b/QDMA/DPDK/examples/qdma_testapp/pcierw.c
@@ -1,7 +1,8 @@
/*-
* BSD LICENSE
*
- * Copyright(c) 2017-2022 Xilinx, Inc. All rights reserved.
+ * Copyright (c) 2017-2022 Xilinx, Inc. All rights reserved.
+ * Copyright (c) 2022, Advanced Micro Devices, Inc. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
diff --git a/QDMA/DPDK/examples/qdma_testapp/pcierw.h b/QDMA/DPDK/examples/qdma_testapp/pcierw.h
old mode 100644
new mode 100755
index b40a55479321fb72983539e546691f537350d9d4..14dbd9a2557bab7e6f2d8a6fb5126a3868a40b0d
--- a/QDMA/DPDK/examples/qdma_testapp/pcierw.h
+++ b/QDMA/DPDK/examples/qdma_testapp/pcierw.h
@@ -1,7 +1,8 @@
/*-
* BSD LICENSE
*
- * Copyright(c) 2017-2022 Xilinx, Inc. All rights reserved.
+ * Copyright (c) 2017-2022 Xilinx, Inc. All rights reserved.
+ * Copyright (c) 2022, Advanced Micro Devices, Inc. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
diff --git a/QDMA/DPDK/examples/qdma_testapp/qdma_regs.h b/QDMA/DPDK/examples/qdma_testapp/qdma_regs.h
old mode 100644
new mode 100755
index ab4e5cc1ad31c594593d15cd90a50c6b3b59cb6e..c7dac231359203884aa38d090d17e8afd42f93d5
--- a/QDMA/DPDK/examples/qdma_testapp/qdma_regs.h
+++ b/QDMA/DPDK/examples/qdma_testapp/qdma_regs.h
@@ -1,7 +1,8 @@
/*-
* BSD LICENSE
*
- * Copyright(c) 2017-2022 Xilinx, Inc. All rights reserved.
+ * Copyright (c) 2017-2022 Xilinx, Inc. All rights reserved.
+ * Copyright (c) 2022, Advanced Micro Devices, Inc. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
diff --git a/QDMA/DPDK/examples/qdma_testapp/testapp.c b/QDMA/DPDK/examples/qdma_testapp/testapp.c
old mode 100644
new mode 100755
index 2873959a366824c780f7cb6cf690abee1d3d72bc..a1ccf2e837512ea7cf35eab484b245f9943a732d
--- a/QDMA/DPDK/examples/qdma_testapp/testapp.c
+++ b/QDMA/DPDK/examples/qdma_testapp/testapp.c
@@ -1,7 +1,8 @@
/*-
* BSD LICENSE
*
- * Copyright(c) 2017-2022 Xilinx, Inc. All rights reserved.
+ * Copyright (c) 2017-2022 Xilinx, Inc. All rights reserved.
+ * Copyright (c) 2022, Advanced Micro Devices, Inc. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
@@ -522,8 +523,11 @@ int do_xmit(int port_id, int fd, int queueid, int ld_size, int tot_num_desc,
#endif //DUMP_MEMPOOL_USAGE_STATS
total_tx = num_pkts;
+
+#ifndef TANDEM_BOOT_SUPPORTED
PciWrite(user_bar_idx, C2H_ST_QID_REG, (queueid + qbase),
port_id);
+#endif
/* try to transmit TX_BURST_SZ packets */
#ifdef PERF_BENCHMARK
@@ -611,6 +615,7 @@ int do_xmit(int port_id, int fd, int queueid, int ld_size, int tot_num_desc,
rte_pktmbuf_free(mb[0]);
}
+#ifndef TANDEM_BOOT_SUPPORTED
reg_val = PciRead(user_bar_idx, C2H_CONTROL_REG, port_id);
reg_val &= C2H_CONTROL_REG_MASK;
if (!(reg_val & ST_LOOPBACK_EN)) {
@@ -621,6 +626,7 @@ int do_xmit(int port_id, int fd, int queueid, int ld_size, int tot_num_desc,
/** TO clear H2C DMA write **/
PciWrite(user_bar_idx, H2C_CONTROL_REG, 0x1, port_id);
}
+#endif
rte_spinlock_unlock(&pinfo[port_id].port_update_lock);
return 0;
diff --git a/QDMA/DPDK/examples/qdma_testapp/testapp.h b/QDMA/DPDK/examples/qdma_testapp/testapp.h
old mode 100644
new mode 100755
index 5c79fb8a6dab24f2277f60eb2054377097c96a7f..b487c35fbac81fbd047171fea031b221ab79f88c
--- a/QDMA/DPDK/examples/qdma_testapp/testapp.h
+++ b/QDMA/DPDK/examples/qdma_testapp/testapp.h
@@ -1,7 +1,8 @@
/*-
* BSD LICENSE
*
- * Copyright(c) 2017-2022 Xilinx, Inc. All rights reserved.
+ * Copyright (c) 2017-2022 Xilinx, Inc. All rights reserved.
+ * Copyright (c) 2022, Advanced Micro Devices, Inc. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
@@ -40,7 +41,7 @@
#else
#define NUM_RX_PKTS 32
#endif
-#define MAX_NUM_QUEUES 2048
+#define MAX_NUM_QUEUES 4096
#define DEFAULT_NUM_QUEUES 64
#define RX_TX_MAX_RETRY 1500
#define DEFAULT_RX_WRITEBACK_THRESH (64)
diff --git a/QDMA/DPDK/tools/0001-PKTGEN-20.12.0-Patch-to-add-Jumbo-packet-support.patch b/QDMA/DPDK/tools/0001-PKTGEN-20.12.0-Patch-to-add-Jumbo-packet-support.patch
old mode 100644
new mode 100755
diff --git a/QDMA/DPDK/tools/README.txt b/QDMA/DPDK/tools/README.txt
old mode 100644
new mode 100755
index d745931fd64a69d2ae0e49339058aa829e4fe9e4..843a5c40f0fad54d0640b49e38bebad5e6615288
--- a/QDMA/DPDK/tools/README.txt
+++ b/QDMA/DPDK/tools/README.txt
@@ -10,7 +10,8 @@ This patch is used for performance testing with dpdk-pktgen application.
/*-
* BSD LICENSE
*
- * Copyright(c) 2017-2022 Xilinx, Inc. All rights reserved.
+ * Copyright (c) 2017-2022 Xilinx, Inc. All rights reserved.
+ * Copyright (c) 2022, Advanced Micro Devices, Inc. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions