diff --git a/QDMA/DPDK/RELEASE b/QDMA/DPDK/RELEASE
index e3bac5a84098c7fdb192b52223763db433c50ee6..4642030b356660ed96ff33e08d622221edcfb6e2 100755
--- a/QDMA/DPDK/RELEASE
+++ b/QDMA/DPDK/RELEASE
@@ -1,8 +1,8 @@
-RELEASE: 2022.1.3
+RELEASE: 2023.1.0
 =================
 
-This release is based on DPDK v20.11 and contains QDMA poll mode driver and
-QDMA test application.
+This release is based on DPDK v20.11, v21.11 and v22.11 and
+contains QDMA poll mode driver and QDMA test application.
 
 This release is validated for
 	- On VCU1525 for QDMA5.0 2022.1 example design
@@ -10,10 +10,10 @@ This release is validated for
 	- On VCU1525 for QDMA3.1 2019.2 example design
 	- On XCVP1202 for CPM5 2022.1 example design
 
-This release includes a patch file for dpdk-pktgen v20.12.0 that extends
+This release includes patch files for dpdk-pktgen v20.12.0 and v22.04.1 that extends
 dpdk-pktgen application to handle packets with packet sizes more than 1518 bytes
 and it disables the packet size classification logic in dpdk-pktgen to remove
-application overhead in performance measurement.This patch is used for 
+application overhead in performance measurement.This patch is used for
 performance testing with dpdk-pktgen application.
 
 The driver is validated against dpdk-pktgen and testpmd applications for API compliance.
@@ -111,8 +111,20 @@ CPM5
 ----------------------
 - Added PF/VF 4K queues support for CPM5 design. This feature is applicable only when corresponding RTL support is added.
 
+2023.1.0 Updates
+----------------
+- Added support for DPDK framework v21.11 and v22.11 and retained the backward compatibility for v20.11
+- Enabled 128 bit SIMD vectorization for Intel and AMD platforms by default for qdma Receive and Transmit APIs
+- Added IO memory barriers for H2C/C2H producer index and completion ring consumer index updates
+
 KNOWN ISSUE:
 ============
+- CPM5:
+	- Performance optimizations are not finalized, Performance report with optimizations will be available in next patch release.
+
+- QDMA5.0:
+	- Performance optimizations are not finalized, Performance report with optimizations will be available in next patch release.
+
 - All Designs
 	- Function Level Reset(FLR) of PF device when VFs are attached to this PF results in mailbox communication failure
 	- DPDK C2H and Forwarding performance values for 8 queue is lesser compared to 4 queue case for both PF and VF.
@@ -126,14 +138,14 @@ DRIVER LIMITATIONS:
 - All Designs
 	- Big endian systems are not supported
 	- For optimal QDMA streaming performance, packet buffers of the descriptor ring should be aligned to at least 256 bytes.
-
+	- Current 2023.1.0 driver which is supporting DPDK 22.11/21.11 is not fully verified for stress, multicard, tandem boot and interop use cases. These will be verified and confirmed in next patch release.
 
 
 /*-
  *   BSD LICENSE
  *
  *   Copyright (c) 2017-2022 Xilinx, Inc. All rights reserved.
- *   Copyright (c) 2022, Advanced Micro Devices, Inc. All rights reserved.
+ *   Copyright (c) 2022-2023, Advanced Micro Devices, Inc. All rights reserved.
  *
  *   Redistribution and use in source and binary forms, with or without
  *   modification, are permitted provided that the following conditions
diff --git a/QDMA/DPDK/docs/README.txt b/QDMA/DPDK/docs/README.txt
old mode 100644
new mode 100755
diff --git a/QDMA/DPDK/drivers/net/qdma/meson.build b/QDMA/DPDK/drivers/net/qdma/meson.build
index 43fa60ad218d6ccdb24bbb723dae12c1073fe3c9..a0674b67a1e477b418e824936bfae44b7a64636d 100755
--- a/QDMA/DPDK/drivers/net/qdma/meson.build
+++ b/QDMA/DPDK/drivers/net/qdma/meson.build
@@ -1,7 +1,7 @@
 #   BSD LICENSE
 #
 #   Copyright (c) 2021-2022 Xilinx, Inc. All rights reserved.
-#   Copyright (c) 2022, Advanced Micro Devices, Inc. All rights reserved.
+#   Copyright (c) 2022-2023, Advanced Micro Devices, Inc. All rights reserved.
 #
 #   Redistribution and use in source and binary forms, with or without
 #   modification, are permitted provided that the following conditions
@@ -31,6 +31,17 @@
 
 cflags += ['-DRTE_LIBRTE_QDMA_PMD']
 cflags += ['-DDMA_BRAM_SIZE=524288']
+cflags += ['-DTHROUGHPUT_MEASUREMENT']
+
+# Enable vectorization in qdma data path to use 128-bit SIMD registers
+cflags += ['-DQDMA_RX_VEC_X86_64']
+cflags += ['-DQDMA_TX_VEC_X86_64']
+
+#Used QDMA_DPDK_20_11 flag for DPDK 22.11
+#Similar for DPDK 20.11 and 21.11,
+##QDMA_DPDK_20_11, QDMA_DPDK_20_11 flags we can set it it
+
+cflags += ['-DQDMA_DPDK_22_11']
 
 includes += include_directories('.')
 includes += include_directories('qdma_access')
@@ -64,5 +75,6 @@ sources = files(
 	'qdma_access/qdma_access_common.c',
 	'qdma_mbox.c',
 	'qdma_platform.c',
-	'rte_pmd_qdma.c'
+	'rte_pmd_qdma.c',
+	'qdma_dpdk_compat.c'
 )
diff --git a/QDMA/DPDK/drivers/net/qdma/qdma.h b/QDMA/DPDK/drivers/net/qdma/qdma.h
index 9cae38cef4ce5d20c986c3a08ff6f9ad24bf6ffd..182bd97fe85d222483366376a639776f0353d284 100755
--- a/QDMA/DPDK/drivers/net/qdma/qdma.h
+++ b/QDMA/DPDK/drivers/net/qdma/qdma.h
@@ -2,7 +2,7 @@
  * BSD LICENSE
  *
  * Copyright (c) 2017-2022 Xilinx, Inc. All rights reserved.
- * Copyright (c) 2022, Advanced Micro Devices, Inc. All rights reserved.
+ * Copyright (c) 2022-2023, Advanced Micro Devices, Inc. All rights reserved.
  *
  * Redistribution and use in source and binary forms, with or without
  * modification, are permitted provided that the following conditions
@@ -37,7 +37,6 @@
 #include <stdbool.h>
 #include <rte_dev.h>
 #include <rte_ethdev.h>
-#include <rte_ethdev_driver.h>
 #include <rte_spinlock.h>
 #include <rte_log.h>
 #include <rte_cycles.h>
@@ -49,6 +48,7 @@
 #include "qdma_mbox.h"
 #include "rte_pmd_qdma.h"
 #include "qdma_log.h"
+#include "qdma_dpdk_compat.h"
 
 #define QDMA_NUM_BARS          (6)
 #define DEFAULT_PF_CONFIG_BAR  (0)
diff --git a/QDMA/DPDK/drivers/net/qdma/qdma_access/eqdma_cpm5_access/eqdma_cpm5_access.c b/QDMA/DPDK/drivers/net/qdma/qdma_access/eqdma_cpm5_access/eqdma_cpm5_access.c
index 4e06d5f761e00169f7dd2a113b79ce81f3bbb440..504973383e189b3fabae722ecdd9c0ecf2a8a25d 100755
--- a/QDMA/DPDK/drivers/net/qdma/qdma_access/eqdma_cpm5_access/eqdma_cpm5_access.c
+++ b/QDMA/DPDK/drivers/net/qdma/qdma_access/eqdma_cpm5_access/eqdma_cpm5_access.c
@@ -99,9 +99,11 @@
 #define EQDMA_CPM5_GLBL2_FLR_PRESENT_MASK			BIT(1)
 #define EQDMA_CPM5_GLBL2_MAILBOX_EN_MASK			BIT(0)
 
+
+/* TODO: This is work around and this needs to be auto generated from ODS */
 /** EQDMA_CPM5_IND_REG_SEL_FMAP */
-#define EQDMA_CPM5_FMAP_CTXT_W1_QID_MAX_MASK         GENMASK(11, 0)
-#define EQDMA_CPM5_FMAP_CTXT_W0_QID_MASK             GENMASK(10, 0)
+#define EQDMA_CPM5_FMAP_CTXT_W1_QID_MAX_MASK         GENMASK(12, 0)
+#define EQDMA_CPM5_FMAP_CTXT_W0_QID_MASK             GENMASK(11, 0)
 
 static void eqdma_cpm5_hw_st_h2c_err_process(void *dev_hndl);
 static void eqdma_cpm5_hw_st_c2h_err_process(void *dev_hndl);
diff --git a/QDMA/DPDK/drivers/net/qdma/qdma_access/eqdma_soft_access/eqdma_soft_access.c b/QDMA/DPDK/drivers/net/qdma/qdma_access/eqdma_soft_access/eqdma_soft_access.c
index 2be31a0eb2ff6dcf03a7ab0bd7b245b685753edc..80a1ffb6b00097b1767ff757e91368ee19a64d50 100755
--- a/QDMA/DPDK/drivers/net/qdma/qdma_access/eqdma_soft_access/eqdma_soft_access.c
+++ b/QDMA/DPDK/drivers/net/qdma/qdma_access/eqdma_soft_access/eqdma_soft_access.c
@@ -79,10 +79,15 @@
 #define EQDMA5_H2C_THROT_REQ_THRESH        0xC0
 
 /* CSR Default values for QDMA 5.0 */
-#define EQDMA5_DEFAULT_H2C_UODSC_LIMIT     4
-#define EQDMA5_DEFAULT_MAX_DSC_FETCH       3
+#define EQDMA5_DEFAULT_C2H_UODSC_LIMIT     5
+#define EQDMA5_DEFAULT_H2C_UODSC_LIMIT     8
+#define EQDMA5_DEFAULT_MAX_DSC_FETCH       5
 #define EQDMA5_DEFAULT_WRB_INT             QDMA_WRB_INTERVAL_128
 
+/* C2H prefetch Throttle configuration. */
+#define EQDMA5_DEFAULT_C2H_EVT_QCNT_TH     0x38
+#define EQDMA5_DEFAULT_C2H_PFCH_QCNT       0x3c
+
 /** Auxillary Bitmasks for fields spanning multiple words */
 #define EQDMA_SW_CTXT_PASID_GET_H_MASK              GENMASK(21, 12)
 #define EQDMA_SW_CTXT_PASID_GET_L_MASK              GENMASK(11, 0)
@@ -2169,6 +2174,8 @@ int eqdma_set_default_global_csr(void *dev_hndl)
 			 * is same except some performance optimizations
 			 */
 			reg_val =
+				FIELD_SET(GLBL_DSC_CFG_C2H_UODSC_LIMIT_MASK,
+					EQDMA5_DEFAULT_C2H_UODSC_LIMIT) |
 				FIELD_SET(GLBL_DSC_CFG_H2C_UODSC_LIMIT_MASK,
 					EQDMA5_DEFAULT_H2C_UODSC_LIMIT) |
 				FIELD_SET(GLBL_DSC_CFG_MAXFETCH_MASK,
@@ -2190,12 +2197,21 @@ int eqdma_set_default_global_csr(void *dev_hndl)
 				QDMA_NUM_C2H_BUFFER_SIZES, buf_sz);
 
 		/* Prefetch Configuration */
-		reg_val = qdma_reg_read(dev_hndl,
-				EQDMA_C2H_PFCH_CACHE_DEPTH_ADDR);
-		cfg_val = FIELD_GET(C2H_PFCH_CACHE_DEPTH_MASK, reg_val);
-		reg_val = FIELD_SET(C2H_PFCH_CFG_1_QCNT_MASK, (cfg_val >> 2)) |
-				  FIELD_SET(C2H_PFCH_CFG_1_EVT_QCNT_TH_MASK,
+		if (eqdma_ip_version == EQDMA_IP_VERSION_4) {
+			reg_val = qdma_reg_read(dev_hndl,
+					EQDMA_C2H_PFCH_CACHE_DEPTH_ADDR);
+			cfg_val = FIELD_GET(C2H_PFCH_CACHE_DEPTH_MASK, reg_val);
+			reg_val = FIELD_SET(C2H_PFCH_CFG_1_QCNT_MASK,
+					(cfg_val >> 2)) |
+				FIELD_SET(C2H_PFCH_CFG_1_EVT_QCNT_TH_MASK,
 						((cfg_val >> 2) - 4));
+		} else {
+			/* Performance optimization for EQDMA5.0. */
+			reg_val = FIELD_SET(C2H_PFCH_CFG_1_QCNT_MASK,
+						EQDMA5_DEFAULT_C2H_PFCH_QCNT) |
+				  FIELD_SET(C2H_PFCH_CFG_1_EVT_QCNT_TH_MASK,
+						EQDMA5_DEFAULT_C2H_EVT_QCNT_TH);
+		}
 		qdma_reg_write(dev_hndl, EQDMA_C2H_PFCH_CFG_1_ADDR, reg_val);
 
 		reg_val = qdma_reg_read(dev_hndl, EQDMA_C2H_PFCH_CFG_2_ADDR);
diff --git a/QDMA/DPDK/drivers/net/qdma/qdma_access/qdma_access_common.h b/QDMA/DPDK/drivers/net/qdma/qdma_access/qdma_access_common.h
index 99ba55e4683667345dacf9e884dad936467aa3a6..24a2189766b2c8a1434a1d697e81612ef0192760 100755
--- a/QDMA/DPDK/drivers/net/qdma/qdma_access/qdma_access_common.h
+++ b/QDMA/DPDK/drivers/net/qdma/qdma_access/qdma_access_common.h
@@ -98,10 +98,17 @@ static inline uint32_t get_trailing_zeros(uint64_t value)
 #define DEFAULT_PFCH_NUM_ENTRIES_PER_Q      8
 #define DEFAULT_PFCH_MAX_Q_CNT              16
 #define DEFAULT_C2H_INTR_TIMER_TICK         25
-#define DEFAULT_CMPT_COAL_TIMER_CNT         5
 #define DEFAULT_CMPT_COAL_TIMER_TICK        25
 #define DEFAULT_CMPT_COAL_MAX_BUF_SZ        32
 
+#ifdef THROUGHPUT_MEASUREMENT
+/* Update WRB coalesce timer count for throughput measurement */
+#define DEFAULT_CMPT_COAL_TIMER_CNT         10
+#else
+/* Update WRB coalesce timer count for low latency measurement */
+#define DEFAULT_CMPT_COAL_TIMER_CNT         5
+#endif
+
 #define QDMA_BAR_NUM                        6
 
 /** Maximum data vectors to be used for each function
diff --git a/QDMA/DPDK/drivers/net/qdma/qdma_access/qdma_access_version.h b/QDMA/DPDK/drivers/net/qdma/qdma_access/qdma_access_version.h
index d54fca8d291fafb6788c72407b28fa51b29c85a4..602defd1a8808baa9eef338426f37df9f2a1fca1 100755
--- a/QDMA/DPDK/drivers/net/qdma/qdma_access/qdma_access_version.h
+++ b/QDMA/DPDK/drivers/net/qdma/qdma_access/qdma_access_version.h
@@ -35,9 +35,9 @@
 #define __QDMA_ACCESS_VERSION_H_
 
 
-#define QDMA_VERSION_MAJOR	2022
+#define QDMA_VERSION_MAJOR	2023
 #define QDMA_VERSION_MINOR	1
-#define QDMA_VERSION_PATCH	5
+#define QDMA_VERSION_PATCH	0
 
 #define QDMA_VERSION_STR	\
 	__stringify(QDMA_VERSION_MAJOR) "." \
diff --git a/QDMA/DPDK/drivers/net/qdma/qdma_access/qdma_platform.h b/QDMA/DPDK/drivers/net/qdma/qdma_access/qdma_platform.h
index 9cdd9c6bbd839bc7619fb893c898bbf94e353ed0..f44bd59dde38f64790a1b89eee33f31b9c7121e1 100755
--- a/QDMA/DPDK/drivers/net/qdma/qdma_access/qdma_platform.h
+++ b/QDMA/DPDK/drivers/net/qdma/qdma_access/qdma_platform.h
@@ -178,6 +178,14 @@ void qdma_strncpy(char *dest, const char *src, size_t n);
  *****************************************************************************/
 int qdma_get_err_code(int acc_err_code);
 
+/*****************************************************************************/
+/**
+ * qdma_io_wmb() - Write memory barrier for IO device
+ *
+ * Return:	0   - success and < 0 - failure
+ *****************************************************************************/
+int qdma_io_wmb(void);
+
 #ifdef __cplusplus
 }
 #endif
diff --git a/QDMA/DPDK/drivers/net/qdma/qdma_access/qdma_soft_access/qdma_soft_access.c b/QDMA/DPDK/drivers/net/qdma/qdma_access/qdma_soft_access/qdma_soft_access.c
index 0b242aa4e8678705fce44e6f7247a855dccb695d..b8f1a7ecc1d0c1061954fb898961d2d0343ad22e 100755
--- a/QDMA/DPDK/drivers/net/qdma/qdma_access/qdma_soft_access/qdma_soft_access.c
+++ b/QDMA/DPDK/drivers/net/qdma/qdma_access/qdma_soft_access/qdma_soft_access.c
@@ -4049,6 +4049,11 @@ int qdma_queue_pidx_update(void *dev_hndl, uint8_t is_vf, uint16_t qid,
 			  FIELD_SET(QDMA_DMA_SEL_IRQ_EN_MASK,
 			  reg_info->irq_en);
 
+	/* Make sure writes to the H2C/C2H descriptors are synchronized
+	 * before updating PIDX
+	 */
+	qdma_io_wmb();
+
 	qdma_reg_write(dev_hndl, reg_addr, reg_val);
 
 	return QDMA_SUCCESS;
@@ -4101,6 +4106,11 @@ int qdma_queue_cmpt_cidx_update(void *dev_hndl, uint8_t is_vf,
 				reg_info->wrb_en) |
 		FIELD_SET(QDMA_DMAP_SEL_CMPT_IRQ_EN_MASK, reg_info->irq_en);
 
+	/* Make sure writes to the CMPT ring are synchronized
+	 * before updating CIDX
+	 */
+	qdma_io_wmb();
+
 	qdma_reg_write(dev_hndl, reg_addr, reg_val);
 
 	return QDMA_SUCCESS;
diff --git a/QDMA/DPDK/drivers/net/qdma/qdma_common.c b/QDMA/DPDK/drivers/net/qdma/qdma_common.c
index bbbc5fe04a95422989a9d9e53a922d7bedbe341b..a25127eddb07aadd8aa02904911c8c64fe09ff69 100755
--- a/QDMA/DPDK/drivers/net/qdma/qdma_common.c
+++ b/QDMA/DPDK/drivers/net/qdma/qdma_common.c
@@ -2,7 +2,7 @@
  * BSD LICENSE
  *
  * Copyright (c) 2017-2022 Xilinx, Inc. All rights reserved.
- * Copyright (c) 2022, Advanced Micro Devices, Inc. All rights reserved.
+ * Copyright (c) 2022-2023, Advanced Micro Devices, Inc. All rights reserved.
  *
  * Redistribution and use in source and binary forms, with or without
  * modification, are permitted provided that the following conditions
@@ -34,12 +34,10 @@
 #include <stdint.h>
 #include <rte_malloc.h>
 #include <rte_common.h>
-#include <rte_ethdev_pci.h>
 #include <rte_cycles.h>
 #include <rte_kvargs.h>
 #include "qdma.h"
 #include "qdma_access_common.h"
-
 #include <fcntl.h>
 #include <unistd.h>
 
diff --git a/QDMA/DPDK/drivers/net/qdma/qdma_devops.c b/QDMA/DPDK/drivers/net/qdma/qdma_devops.c
index 2fe312fbecf3e4f83d2ff314c7d02a48b455fed2..648db10f2c032fba27313d0b734d340812f5d3a2 100755
--- a/QDMA/DPDK/drivers/net/qdma/qdma_devops.c
+++ b/QDMA/DPDK/drivers/net/qdma/qdma_devops.c
@@ -2,7 +2,7 @@
  * BSD LICENSE
  *
  * Copyright (c) 2017-2022 Xilinx, Inc. All rights reserved.
- * Copyright (c) 2022, Advanced Micro Devices, Inc. All rights reserved.
+ * Copyright (c) 2022-2023, Advanced Micro Devices, Inc. All rights reserved.
  *
  * Redistribution and use in source and binary forms, with or without
  * modification, are permitted provided that the following conditions
@@ -36,7 +36,6 @@
 #include <sys/fcntl.h>
 #include <rte_memzone.h>
 #include <rte_string_fns.h>
-#include <rte_ethdev_pci.h>
 #include <rte_malloc.h>
 #include <rte_dev.h>
 #include <rte_pci.h>
@@ -47,7 +46,6 @@
 #include <rte_atomic.h>
 #include <unistd.h>
 #include <string.h>
-
 #include "qdma.h"
 #include "qdma_access_common.h"
 #include "qdma_mbox_protocol.h"
@@ -949,79 +947,6 @@ void qdma_txq_pidx_update(void *arg)
 }
 #endif
 
-
-
-void qdma_dev_tx_queue_release(void *tqueue)
-{
-	struct qdma_tx_queue *txq = (struct qdma_tx_queue *)tqueue;
-	struct qdma_pci_dev *qdma_dev;
-
-	if (txq != NULL) {
-		PMD_DRV_LOG(INFO, "Remove H2C queue: %d", txq->queue_id);
-		qdma_dev = txq->dev->data->dev_private;
-
-		if (!qdma_dev->is_vf)
-			qdma_dev_decrement_active_queue(
-					qdma_dev->dma_device_index,
-					qdma_dev->func_id,
-					QDMA_DEV_Q_TYPE_H2C);
-		else
-			qdma_dev_notify_qdel(txq->dev, txq->queue_id +
-						qdma_dev->queue_base,
-						QDMA_DEV_Q_TYPE_H2C);
-		if (txq->sw_ring)
-			rte_free(txq->sw_ring);
-		if (txq->tx_mz)
-			rte_memzone_free(txq->tx_mz);
-		rte_free(txq);
-		PMD_DRV_LOG(INFO, "H2C queue %d removed", txq->queue_id);
-	}
-}
-
-void qdma_dev_rx_queue_release(void *rqueue)
-{
-	struct qdma_rx_queue *rxq = (struct qdma_rx_queue *)rqueue;
-	struct qdma_pci_dev *qdma_dev = NULL;
-
-	if (rxq != NULL) {
-		PMD_DRV_LOG(INFO, "Remove C2H queue: %d", rxq->queue_id);
-		qdma_dev = rxq->dev->data->dev_private;
-
-		if (!qdma_dev->is_vf) {
-			qdma_dev_decrement_active_queue(
-					qdma_dev->dma_device_index,
-					qdma_dev->func_id,
-					QDMA_DEV_Q_TYPE_C2H);
-
-			if (rxq->st_mode)
-				qdma_dev_decrement_active_queue(
-					qdma_dev->dma_device_index,
-					qdma_dev->func_id,
-					QDMA_DEV_Q_TYPE_CMPT);
-		} else {
-			qdma_dev_notify_qdel(rxq->dev, rxq->queue_id +
-					qdma_dev->queue_base,
-					QDMA_DEV_Q_TYPE_C2H);
-
-			if (rxq->st_mode)
-				qdma_dev_notify_qdel(rxq->dev, rxq->queue_id +
-						qdma_dev->queue_base,
-						QDMA_DEV_Q_TYPE_CMPT);
-		}
-
-		if (rxq->sw_ring)
-			rte_free(rxq->sw_ring);
-		if (rxq->st_mode) { /** if ST-mode **/
-			if (rxq->rx_cmpt_mz)
-				rte_memzone_free(rxq->rx_cmpt_mz);
-		}
-		if (rxq->rx_mz)
-			rte_memzone_free(rxq->rx_mz);
-		rte_free(rxq);
-		PMD_DRV_LOG(INFO, "C2H queue %d removed", rxq->queue_id);
-	}
-}
-
 /**
  * DPDK callback to start the device.
  *
@@ -1086,6 +1011,7 @@ int qdma_dev_link_update(struct rte_eth_dev *dev,
 	dev->data->dev_link.link_status = ETH_LINK_UP;
 	dev->data->dev_link.link_duplex = ETH_LINK_FULL_DUPLEX;
 	dev->data->dev_link.link_speed = ETH_SPEED_NUM_100G;
+
 	PMD_DRV_LOG(INFO, "Link update done\n");
 	return 0;
 }
diff --git a/QDMA/DPDK/drivers/net/qdma/qdma_devops.h b/QDMA/DPDK/drivers/net/qdma/qdma_devops.h
index 586a4b333f488b2c584131db528f9b27d277f9ba..56c0d2866561acd4d5b774d56335eec13fc01d23 100755
--- a/QDMA/DPDK/drivers/net/qdma/qdma_devops.h
+++ b/QDMA/DPDK/drivers/net/qdma/qdma_devops.h
@@ -2,7 +2,7 @@
  * BSD LICENSE
  *
  * Copyright (c) 2020-2022 Xilinx, Inc. All rights reserved.
- * Copyright (c) 2022, Advanced Micro Devices, Inc. All rights reserved.
+ * Copyright (c) 2022-2023, Advanced Micro Devices, Inc. All rights reserved.
  *
  * Redistribution and use in source and binary forms, with or without
  * modification, are permitted provided that the following conditions
@@ -34,7 +34,6 @@
 #ifndef __QDMA_DEVOPS_H__
 #define __QDMA_DEVOPS_H__
 
-
 #ifdef __cplusplus
 extern "C" {
 #endif
@@ -320,21 +319,6 @@ int qdma_dev_queue_stats_mapping(struct rte_eth_dev *dev,
 					     uint8_t stat_idx,
 					     uint8_t is_rx);
 
-/**
- * DPDK callback to get the number of used descriptors of a rx queue
- *
- * @param dev
- *   Pointer to Ethernet device structure
- * @param rx_queue_id
- *   The RX queue on the Ethernet device for which information will be
- *   retrieved
- *
- * @return
- *   The number of used descriptors in the specific queue
- * @ingroup dpdk_devops_func
- */
-uint32_t
-qdma_dev_rx_queue_count(struct rte_eth_dev *dev, uint16_t rx_queue_id);
 
 /**
  * DPDK callback to check the status of a Rx descriptor in the queue
@@ -465,30 +449,6 @@ int qdma_dev_tx_queue_stop(struct rte_eth_dev *dev, uint16_t qid);
  */
 int qdma_dev_stop(struct rte_eth_dev *dev);
 
-/**
- * DPDK callback to release a Rx queue.
- *
- * This API releases the descriptor rings and any additional memory allocated
- * for given C2H queue
- *
- * @param rqueue: Generic Rx queue pointer
- *
- * @ingroup dpdk_devops_func
- */
-void qdma_dev_rx_queue_release(void *rqueue);
-
-/**
- * DPDK callback to release a Tx queue.
- *
- * This API releases the descriptor rings and any additional memory allocated
- * for given H2C queue
- *
- * @param tqueue: Generic Tx queue pointer
- *
- * @ingroup dpdk_devops_func
- */
-void qdma_dev_tx_queue_release(void *tqueue);
-
 /**
  * DPDK callback to close the device.
  *
diff --git a/QDMA/DPDK/drivers/net/qdma/qdma_ethdev.c b/QDMA/DPDK/drivers/net/qdma/qdma_ethdev.c
index 50c132d7497fa10dbd87bf3013ef90851b3132bc..cb7b99721e815d31ad9600711cee1696f560c5ac 100755
--- a/QDMA/DPDK/drivers/net/qdma/qdma_ethdev.c
+++ b/QDMA/DPDK/drivers/net/qdma/qdma_ethdev.c
@@ -2,7 +2,7 @@
  * BSD LICENSE
  *
  * Copyright (c) 2017-2022 Xilinx, Inc. All rights reserved.
- * Copyright (c) 2022, Advanced Micro Devices, Inc. All rights reserved.
+ * Copyright (c) 2022-2023, Advanced Micro Devices, Inc. All rights reserved.
  *
  * Redistribution and use in source and binary forms, with or without
  * modification, are permitted provided that the following conditions
@@ -37,7 +37,6 @@
 #include <sys/fcntl.h>
 #include <rte_memzone.h>
 #include <rte_string_fns.h>
-#include <rte_ethdev_pci.h>
 #include <rte_malloc.h>
 #include <rte_dev.h>
 #include <rte_pci.h>
diff --git a/QDMA/DPDK/drivers/net/qdma/qdma_log.h b/QDMA/DPDK/drivers/net/qdma/qdma_log.h
index a6922693a92f9dac7fff84d01317d79874a34c7d..6851db7558f00b6b94bacac90e46e1482bf522d8 100755
--- a/QDMA/DPDK/drivers/net/qdma/qdma_log.h
+++ b/QDMA/DPDK/drivers/net/qdma/qdma_log.h
@@ -2,7 +2,7 @@
  * BSD LICENSE
  *
  * Copyright (c) 2019-2022 Xilinx, Inc. All rights reserved.
- * Copyright (c) 2022, Advanced Micro Devices, Inc. All rights reserved.
+ * Copyright (c) 2022-2023, Advanced Micro Devices, Inc. All rights reserved.
  *
  * Redistribution and use in source and binary forms, with or without
  * modification, are permitted provided that the following conditions
diff --git a/QDMA/DPDK/drivers/net/qdma/qdma_mbox.c b/QDMA/DPDK/drivers/net/qdma/qdma_mbox.c
index 63a31de5811cdc6625107495ba11c6b4b7bfece0..e1cd2a5ee6dfeac1c0dea700dc75282f8665cbd6 100755
--- a/QDMA/DPDK/drivers/net/qdma/qdma_mbox.c
+++ b/QDMA/DPDK/drivers/net/qdma/qdma_mbox.c
@@ -2,7 +2,7 @@
  * BSD LICENSE
  *
  * Copyright (c) 2019-2022 Xilinx, Inc. All rights reserved.
- * Copyright (c) 2022, Advanced Micro Devices, Inc. All rights reserved.
+ * Copyright (c) 2022-2023, Advanced Micro Devices, Inc. All rights reserved.
  *
  * Redistribution and use in source and binary forms, with or without
  * modification, are permitted provided that the following conditions
@@ -31,7 +31,6 @@
  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  */
 
-#include <rte_ethdev_pci.h>
 #include "qdma.h"
 #include "qdma_mbox.h"
 #include <rte_malloc.h>
@@ -358,7 +357,7 @@ int qdma_mbox_init(struct rte_eth_dev *dev)
 	struct qdma_pci_dev *qdma_dev = dev->data->dev_private;
 	struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
 	uint32_t raw_data[MBOX_MSG_REG_MAX] = {0};
-	struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
+	struct rte_intr_handle *intr_handle = pci_dev_intr_handle;
 
 	if (!qdma_dev->is_vf) {
 		int i;
@@ -395,7 +394,7 @@ void qdma_mbox_uninit(struct rte_eth_dev *dev)
 {
 	struct qdma_pci_dev *qdma_dev = dev->data->dev_private;
 	struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
-	struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
+	struct rte_intr_handle *intr_handle = pci_dev_intr_handle;
 
 	do {
 		rte_spinlock_lock(&qdma_dev->mbox.list_lock);
diff --git a/QDMA/DPDK/drivers/net/qdma/qdma_mbox.h b/QDMA/DPDK/drivers/net/qdma/qdma_mbox.h
index ff4fa588dd56c62a3c49d4c0d17800d30848ce95..d861342ffb21de719e6da9e5e2fb8f47ec966033 100755
--- a/QDMA/DPDK/drivers/net/qdma/qdma_mbox.h
+++ b/QDMA/DPDK/drivers/net/qdma/qdma_mbox.h
@@ -2,7 +2,7 @@
  * BSD LICENSE
  *
  * Copyright (c) 2019-2022 Xilinx, Inc. All rights reserved.
- * Copyright (c) 2022, Advanced Micro Devices, Inc. All rights reserved.
+ * Copyright (c) 2022-2023, Advanced Micro Devices, Inc. All rights reserved.
  *
  * Redistribution and use in source and binary forms, with or without
  * modification, are permitted provided that the following conditions
diff --git a/QDMA/DPDK/drivers/net/qdma/qdma_platform.c b/QDMA/DPDK/drivers/net/qdma/qdma_platform.c
index ba0d54eeb74832214c95d16a292761a30906b902..9abe8f65c01311112f484d7d39af8673cc94e9d6 100755
--- a/QDMA/DPDK/drivers/net/qdma/qdma_platform.c
+++ b/QDMA/DPDK/drivers/net/qdma/qdma_platform.c
@@ -2,7 +2,7 @@
  * BSD LICENSE
  *
  * Copyright (c) 2019-2022 Xilinx, Inc. All rights reserved.
- * Copyright (c) 2022, Advanced Micro Devices, Inc. All rights reserved.
+ * Copyright (c) 2022-2023, Advanced Micro Devices, Inc. All rights reserved.
  *
  * Redistribution and use in source and binary forms, with or without
  * modification, are permitted provided that the following conditions
@@ -33,6 +33,7 @@
 
 #include "qdma_access_common.h"
 #include "qdma_platform.h"
+#include "rte_pmd_qdma.h"
 #include "qdma.h"
 #include <rte_malloc.h>
 #include <rte_spinlock.h>
@@ -249,3 +250,15 @@ int qdma_get_err_code(int acc_err_code)
 
 	return -(error_code_map_list[acc_err_code].err_code);
 }
+
+/*****************************************************************************/
+/**
+ * qdma_io_wmb() - Write memory barrier for IO device
+ *
+ * Return:	0   - success and < 0 - failure
+ *****************************************************************************/
+int qdma_io_wmb(void)
+{
+	rte_io_wmb();
+	return 0;
+}
diff --git a/QDMA/DPDK/drivers/net/qdma/qdma_platform_env.h b/QDMA/DPDK/drivers/net/qdma/qdma_platform_env.h
index 5bc4fbba6e30c9657a8d8dbad765019aed266572..69d5e59194c6b5d091b9eb1158b0b79ce2c6521d 100755
--- a/QDMA/DPDK/drivers/net/qdma/qdma_platform_env.h
+++ b/QDMA/DPDK/drivers/net/qdma/qdma_platform_env.h
@@ -2,7 +2,7 @@
  * BSD LICENSE
  *
  * Copyright (c) 2019-2022 Xilinx, Inc. All rights reserved.
- * Copyright (c) 2022, Advanced Micro Devices, Inc. All rights reserved.
+ * Copyright (c) 2022-2023, Advanced Micro Devices, Inc. All rights reserved.
  *
  * Redistribution and use in source and binary forms, with or without
  * modification, are permitted provided that the following conditions
diff --git a/QDMA/DPDK/drivers/net/qdma/qdma_rxtx.c b/QDMA/DPDK/drivers/net/qdma/qdma_rxtx.c
index 06f0818879d7fc49cce630d94d631eebc72803c0..7ec2b5a3e7c7915ff5b1a85f39cf10a283fe3fa7 100755
--- a/QDMA/DPDK/drivers/net/qdma/qdma_rxtx.c
+++ b/QDMA/DPDK/drivers/net/qdma/qdma_rxtx.c
@@ -2,7 +2,7 @@
  * BSD LICENSE
  *
  * Copyright (c) 2017-2022 Xilinx, Inc. All rights reserved.
- * Copyright (c) 2022, Advanced Micro Devices, Inc. All rights reserved.
+ * Copyright (c) 2022-2023, Advanced Micro Devices, Inc. All rights reserved.
  *
  * Redistribution and use in source and binary forms, with or without
  * modification, are permitted provided that the following conditions
@@ -237,6 +237,10 @@ static int reclaim_tx_mbuf(struct qdma_tx_queue *txq,
 
 	id = txq->tx_fl_tail;
 	fl_desc = (int)cidx - id;
+
+	if (fl_desc == 0)
+		return 0;
+
 	if (fl_desc < 0)
 		fl_desc += (txq->nb_tx_desc - 1);
 
@@ -633,7 +637,7 @@ static int process_cmpt_ring(struct qdma_rx_queue *rxq,
 	return 0;
 }
 
-static uint32_t rx_queue_count(void *rx_queue)
+uint32_t rx_queue_count(void *rx_queue)
 {
 	struct qdma_rx_queue *rxq = rx_queue;
 	struct wb_status *wb_status;
@@ -685,24 +689,6 @@ static uint32_t rx_queue_count(void *rx_queue)
 	return nb_desc_used;
 }
 
-/**
- * DPDK callback to get the number of used descriptors of a rx queue.
- *
- * @param dev
- *   Pointer to Ethernet device structure.
- * @param rx_queue_id
- *   The RX queue on the Ethernet device for which information will be
- *   retrieved
- *
- * @return
- *   The number of used descriptors in the specific queue.
- */
-uint32_t
-qdma_dev_rx_queue_count(struct rte_eth_dev *dev, uint16_t rx_queue_id)
-{
-	return rx_queue_count(dev->data->rx_queues[rx_queue_id]);
-}
-
 /**
  * DPDK callback to check the status of a Rx descriptor in the queue.
  *
@@ -1467,6 +1453,12 @@ uint16_t qdma_xmit_pkts_st(struct qdma_tx_queue *txq, struct rte_mbuf **tx_pkts,
 #endif
 
 	id = txq->q_pidx_info.pidx;
+
+	/* Make sure reads to Tx ring are synchronized before
+	 * accessing the status descriptor.
+	 */
+	rte_rmb();
+
 	cidx = txq->wb_status->cidx;
 	PMD_DRV_LOG(DEBUG, "Xmit start on tx queue-id:%d, tail index:%d\n",
 			txq->queue_id, id);
@@ -1516,11 +1508,6 @@ uint16_t qdma_xmit_pkts_st(struct qdma_tx_queue *txq, struct rte_mbuf **tx_pkts,
 	txq->stats.pkts += count;
 	txq->stats.bytes += pkt_len;
 
-	/* Make sure writes to the H2C descriptors are synchronized
-	 * before updating PIDX
-	 */
-	rte_wmb();
-
 #if (MIN_TX_PIDX_UPDATE_THRESHOLD > 1)
 	rte_spinlock_lock(&txq->pidx_update_lock);
 #endif
@@ -1640,7 +1627,7 @@ uint16_t qdma_xmit_pkts_mm(struct qdma_tx_queue *txq, struct rte_mbuf **tx_pkts,
  * DPDK callback for transmitting packets in burst.
  *
  * @param tx_queue
- G*   Generic pointer to TX queue structure.
+ *   Generic pointer to TX queue structure.
  * @param[in] tx_pkts
  *   Packets to transmit.
  * @param nb_pkts
diff --git a/QDMA/DPDK/drivers/net/qdma/qdma_rxtx.h b/QDMA/DPDK/drivers/net/qdma/qdma_rxtx.h
index 32123e4701b1af0758a6cd633a1b6ef5a05819e6..58ac9e566d593ed12f82f718c90aedd8e94fbcac 100755
--- a/QDMA/DPDK/drivers/net/qdma/qdma_rxtx.h
+++ b/QDMA/DPDK/drivers/net/qdma/qdma_rxtx.h
@@ -2,7 +2,7 @@
  * BSD LICENSE
  *
  * Copyright (c) 2019-2022 Xilinx, Inc. All rights reserved.
- * Copyright (c) 2022, Advanced Micro Devices, Inc. All rights reserved.
+ * Copyright (c) 2022-2023, Advanced Micro Devices, Inc. All rights reserved.
  *
  * Redistribution and use in source and binary forms, with or without
  * modification, are permitted provided that the following conditions
@@ -46,4 +46,6 @@ uint64_t get_mm_c2h_ep_addr(void *queue_hndl);
 uint64_t get_mm_h2c_ep_addr(void *queue_hndl);
 uint32_t get_mm_buff_size(void *queue_hndl);
 
+uint32_t rx_queue_count(void *rx_queue);
+
 #endif /* QDMA_DPDK_RXTX_H_ */
diff --git a/QDMA/DPDK/drivers/net/qdma/qdma_user.c b/QDMA/DPDK/drivers/net/qdma/qdma_user.c
index ac3bfb86f64a2e05e5676f83575c0e52754031c7..222cf49bd5c0edd250d058e32d4954ee6a73b1d9 100755
--- a/QDMA/DPDK/drivers/net/qdma/qdma_user.c
+++ b/QDMA/DPDK/drivers/net/qdma/qdma_user.c
@@ -2,7 +2,7 @@
  * BSD LICENSE
  *
  * Copyright (c) 2019-2022 Xilinx, Inc. All rights reserved.
- * Copyright (c) 2022, Advanced Micro Devices, Inc. All rights reserved.
+ * Copyright (c) 2022-2023, Advanced Micro Devices, Inc. All rights reserved.
  *
  * Redistribution and use in source and binary forms, with or without
  * modification, are permitted provided that the following conditions
diff --git a/QDMA/DPDK/drivers/net/qdma/qdma_user.h b/QDMA/DPDK/drivers/net/qdma/qdma_user.h
index ee20be015e210c3c1c19603559400e1e60a20e12..9c3de6f8c4b1eda01682b6902900833ebc98257e 100755
--- a/QDMA/DPDK/drivers/net/qdma/qdma_user.h
+++ b/QDMA/DPDK/drivers/net/qdma/qdma_user.h
@@ -2,7 +2,7 @@
  * BSD LICENSE
  *
  * Copyright (c) 2018-2022 Xilinx, Inc. All rights reserved.
- * Copyright (c) 2022, Advanced Micro Devices, Inc. All rights reserved.
+ * Copyright (c) 2022-2023, Advanced Micro Devices, Inc. All rights reserved.
  *
  * Redistribution and use in source and binary forms, with or without
  * modification, are permitted provided that the following conditions
diff --git a/QDMA/DPDK/drivers/net/qdma/qdma_vf_ethdev.c b/QDMA/DPDK/drivers/net/qdma/qdma_vf_ethdev.c
index e4366557cf55a3e85ebb2168b1ae9254e3691e6f..ea94e2ca495e8b95c78c95d837088b68885e2de5 100755
--- a/QDMA/DPDK/drivers/net/qdma/qdma_vf_ethdev.c
+++ b/QDMA/DPDK/drivers/net/qdma/qdma_vf_ethdev.c
@@ -2,7 +2,7 @@
  * BSD LICENSE
  *
  * Copyright (c) 2017-2022 Xilinx, Inc. All rights reserved.
- * Copyright (c) 2022, Advanced Micro Devices, Inc. All rights reserved.
+ * Copyright (c) 2022-2023, Advanced Micro Devices, Inc. All rights reserved.
  *
  * Redistribution and use in source and binary forms, with or without
  * modification, are permitted provided that the following conditions
@@ -37,7 +37,6 @@
 #include <sys/fcntl.h>
 #include <rte_memzone.h>
 #include <rte_string_fns.h>
-#include <rte_ethdev_pci.h>
 #include <rte_malloc.h>
 #include <rte_dev.h>
 #include <rte_pci.h>
@@ -48,7 +47,6 @@
 #include <unistd.h>
 #include <string.h>
 #include <linux/pci.h>
-
 #include "qdma.h"
 #include "version.h"
 #include "qdma_access_common.h"
diff --git a/QDMA/DPDK/drivers/net/qdma/qdma_xdebug.c b/QDMA/DPDK/drivers/net/qdma/qdma_xdebug.c
index 362add86ece9e368342fe06bb927ef3a0bd96176..c0f48b9a26e1db3a04fb9bab349b37b20461cb96 100755
--- a/QDMA/DPDK/drivers/net/qdma/qdma_xdebug.c
+++ b/QDMA/DPDK/drivers/net/qdma/qdma_xdebug.c
@@ -2,7 +2,7 @@
  * BSD LICENSE
  *
  * Copyright (c) 2017-2022 Xilinx, Inc. All rights reserved.
- * Copyright (c) 2022, Advanced Micro Devices, Inc. All rights reserved.
+ * Copyright (c) 2022-2023, Advanced Micro Devices, Inc. All rights reserved.
  *
  * Redistribution and use in source and binary forms, with or without
  * modification, are permitted provided that the following conditions
@@ -36,7 +36,6 @@
 #include <sys/fcntl.h>
 #include <rte_memzone.h>
 #include <rte_string_fns.h>
-#include <rte_ethdev_pci.h>
 #include <rte_malloc.h>
 #include <rte_dev.h>
 #include <rte_pci.h>
@@ -53,6 +52,7 @@
 #include "qdma_reg_dump.h"
 #include "qdma_mbox_protocol.h"
 #include "qdma_mbox.h"
+
 #define xdebug_info(args...) rte_log(RTE_LOG_INFO, RTE_LOGTYPE_USER1,\
 					## args)
 #define xdebug_error(args...) rte_log(RTE_LOG_ERR, RTE_LOGTYPE_USER1,\
diff --git a/QDMA/DPDK/drivers/net/qdma/rte_pmd_qdma.c b/QDMA/DPDK/drivers/net/qdma/rte_pmd_qdma.c
index a4ff685c76d6b379da31c3b609a278a7037d4d6f..d2b93ba1a5d240834013d700789c1d0bd933aa49 100755
--- a/QDMA/DPDK/drivers/net/qdma/rte_pmd_qdma.c
+++ b/QDMA/DPDK/drivers/net/qdma/rte_pmd_qdma.c
@@ -2,7 +2,7 @@
  * BSD LICENSE
  *
  * Copyright (c) 2019-2022 Xilinx, Inc. All rights reserved.
- * Copyright (c) 2022, Advanced Micro Devices, Inc. All rights reserved.
+ * Copyright (c) 2022-2023, Advanced Micro Devices, Inc. All rights reserved.
  *
  * Redistribution and use in source and binary forms, with or without
  * modification, are permitted provided that the following conditions
@@ -37,7 +37,6 @@
 #include <sys/fcntl.h>
 #include <rte_memzone.h>
 #include <rte_string_fns.h>
-#include <rte_ethdev_pci.h>
 #include <rte_malloc.h>
 #include <rte_dev.h>
 #include <rte_pci.h>
@@ -1796,7 +1795,8 @@ int rte_pmd_qdma_dev_close(uint16_t port_id)
 	struct qdma_pci_dev *qdma_dev;
 
 	if (port_id >= rte_eth_dev_count_avail()) {
-		PMD_DRV_LOG(ERR, "Wrong port id %d\n", port_id);
+		PMD_DRV_LOG(ERR, "%s:%d Wrong port id %d\n", __func__, __LINE__,
+			port_id);
 		return -ENOTSUP;
 	}
 	dev = &rte_eth_devices[port_id];
@@ -1818,3 +1818,4 @@ int rte_pmd_qdma_dev_close(uint16_t port_id)
 
 	return 0;
 }
+
diff --git a/QDMA/DPDK/drivers/net/qdma/rte_pmd_qdma.h b/QDMA/DPDK/drivers/net/qdma/rte_pmd_qdma.h
index 8cd3dc6956e62624229d2200d0e782dbc387f992..cfff15381fdb19e6976d53d6073573e5c8954d34 100755
--- a/QDMA/DPDK/drivers/net/qdma/rte_pmd_qdma.h
+++ b/QDMA/DPDK/drivers/net/qdma/rte_pmd_qdma.h
@@ -2,7 +2,7 @@
  * BSD LICENSE
  *
  * Copyright (c) 2019-2022 Xilinx, Inc. All rights reserved.
- * Copyright (c) 2022, Advanced Micro Devices, Inc. All rights reserved.
+ * Copyright (c) 2022-2023, Advanced Micro Devices, Inc. All rights reserved.
  *
  * Redistribution and use in source and binary forms, with or without
  * modification, are permitted provided that the following conditions
@@ -735,6 +735,112 @@ uint16_t rte_pmd_qdma_mm_cmpt_process(int port_id, uint32_t qid,
  ******************************************************************************/
 int rte_pmd_qdma_dev_close(uint16_t port_id);
 
+/*****************************************************************************/
+/**
+ * DPDK PMD function to fill fast-path operations.
+ *
+ * @param   port_id Port ID
+ *
+ * @return  on success return 0
+ *
+ ******************************************************************************/
+int rte_pmd_qdma_dev_fp_ops_config(int port_id);
+
+/*****************************************************************************/
+/**
+ * DPDK PMD compatibility function to read pci registers.
+ *
+ * @param   port_id Port ID
+ * @param   bar Bar
+ * @param   offset Offset
+ *
+ * @return  pci_read_reg value
+ *
+ ******************************************************************************/
+unsigned int rte_pmd_qdma_compat_pci_read_reg(int port_id, unsigned int bar, unsigned int offset);
+
+/*****************************************************************************/
+/**
+ * DPDK PMD compatibility function to write pci registers.
+ *
+ * @param   port_id Port ID
+ * @param   bar Bar
+ * @param   offset Offset
+ * @param   reg_val Value which needs to write
+ *
+ ******************************************************************************/
+void rte_pmd_qdma_compat_pci_write_reg(int port_id, uint32_t bar, uint32_t offset, uint32_t reg_val);
+
+/*****************************************************************************/
+/**
+ * DPDK PMD compatibility function to get bdf
+ *
+ * @param   m_id Port ID
+ * @param   bus Bus
+ * @param   dev Device
+ * @param   fn Function
+ *
+ ******************************************************************************/
+void rte_pmd_qdma_get_bdf(uint32_t m_id, uint32_t *bus, uint32_t *dev, uint32_t *fn);
+
+/*****************************************************************************/
+/**
+ * DPDK PMD compatibility function to reserve memzone
+ *
+ ******************************************************************************/
+void rte_pmd_qdma_compat_memzone_reserve_aligned(void);
+
+/*****************************************************************************/
+/**
+ * DPDK PMD compatibility function to device remove
+ *
+ * @param   port_id Port ID
+ * @return  device id to remove
+ *
+ ******************************************************************************/
+int rte_pmd_qdma_dev_remove(int port_id);
+
+/*****************************************************************************/
+/**
+ * DPDK PMD compatibility function to get device id
+ *
+ * @param   port_id Port ID
+ * @return  device id to get
+ *
+ ******************************************************************************/
+uint16_t rte_pmd_qdma_get_dev_id(int port_id);
+
+/*****************************************************************************/
+/**
+ * DPDK PMD compatibility function to device started
+ *
+ * @param   port_id Port ID
+ * @param   status Enable/Disable
+ *
+ ******************************************************************************/
+void rte_pmd_qdma_dev_started(int port_id, bool status);
+
+/*****************************************************************************/
+/**
+ * DPDK PMD compatibility function for eth dev to pci
+ *
+ * @param   port_id Port ID
+ * @return  rte_pci_device* pci_device
+ *
+ ******************************************************************************/
+
+struct rte_pci_device* rte_pmd_qdma_eth_dev_to_pci(int port_id);
+
+/*****************************************************************************/
+/**
+ * DPDK PMD compatibility function to get rte device
+ *
+ * @param   port_id Port ID
+ * @return  rte_device* rte_device
+ *
+ ******************************************************************************/
+struct rte_device* rte_pmd_qdma_get_device(int port_id);
+
 #ifdef __cplusplus
 }
 #endif
diff --git a/QDMA/DPDK/drivers/net/qdma/version.h b/QDMA/DPDK/drivers/net/qdma/version.h
index b4b0fc4c351e9a13665e15f5b8ec1ef69495701e..0962b0fcea6395771b2b89cff6d3e5e09ad8364e 100755
--- a/QDMA/DPDK/drivers/net/qdma/version.h
+++ b/QDMA/DPDK/drivers/net/qdma/version.h
@@ -2,7 +2,7 @@
  * BSD LICENSE
  *
  * Copyright (c) 2017-2022 Xilinx, Inc. All rights reserved.
- * Copyright (c) 2022, Advanced Micro Devices, Inc. All rights reserved.
+ * Copyright (c) 2022-2023, Advanced Micro Devices, Inc. All rights reserved.
  *
  * Redistribution and use in source and binary forms, with or without
  * modification, are permitted provided that the following conditions
@@ -37,9 +37,9 @@
 #define qdma_stringify1(x...)	#x
 #define qdma_stringify(x...)	qdma_stringify1(x)
 
-#define QDMA_PMD_MAJOR		2022
+#define QDMA_PMD_MAJOR		2023
 #define QDMA_PMD_MINOR		1
-#define QDMA_PMD_PATCHLEVEL	3
+#define QDMA_PMD_PATCHLEVEL	0
 
 #define QDMA_PMD_VERSION      \
 	qdma_stringify(QDMA_PMD_MAJOR) "." \
diff --git a/QDMA/DPDK/drivers/net/qdma/version.map b/QDMA/DPDK/drivers/net/qdma/version.map
index 840223b482b102f3d0890216186299e3b39378c4..f866b5e1d03782cfa07af5281f40a6f34df11d00 100755
--- a/QDMA/DPDK/drivers/net/qdma/version.map
+++ b/QDMA/DPDK/drivers/net/qdma/version.map
@@ -2,7 +2,7 @@
  * BSD LICENSE
  *
  * Copyright (c) 2017-2022 Xilinx, Inc. All rights reserved.
- * Copyright (c) 2022, Advanced Micro Devices, Inc. All rights reserved.
+ * Copyright (c) 2022-2023, Advanced Micro Devices, Inc. All rights reserved.
  *
  * Redistribution and use in source and binary forms, with or without
  * modification, are permitted provided that the following conditions
@@ -62,6 +62,100 @@ DPDK_21 {
 	rte_pmd_qdma_dev_cmptq_stop;
 	rte_pmd_qdma_dbg_qdevice;
 	rte_pmd_qdma_dev_close;
+	rte_pmd_qdma_dev_fp_ops_config;
+
 
 	local: *;
 };
+
+DPDK_22 {
+        global:
+
+        rte_pmd_qdma_set_immediate_data_state;
+        rte_pmd_qdma_get_bar_details;
+        rte_pmd_qdma_get_queue_base;
+        rte_pmd_qdma_set_queue_mode;
+        rte_pmd_qdma_get_device_capabilities;
+        qdma_pci_read_reg;
+        qdma_pci_write_reg;
+        rte_pmd_qdma_set_mm_endpoint_addr;
+        rte_pmd_qdma_dbg_qdesc;
+        rte_pmd_qdma_dbg_regdump;
+        rte_pmd_qdma_dbg_reg_info_dump;
+        rte_pmd_qdma_dbg_qinfo;
+
+        rte_pmd_qdma_get_pci_func_type;
+        rte_pmd_qdma_configure_tx_bypass;
+        rte_pmd_qdma_configure_rx_bypass;
+        rte_pmd_qdma_set_cmpt_descriptor_size;
+        rte_pmd_qdma_set_c2h_descriptor_prefetch;
+        rte_pmd_qdma_set_cmpt_overflow_check;
+        rte_pmd_qdma_set_cmpt_trigger_mode;
+        rte_pmd_qdma_set_cmpt_timer;
+        rte_pmd_qdma_get_immediate_data_state;
+        rte_pmd_qdma_dev_cmptq_setup;
+        rte_pmd_qdma_dev_cmptq_start;
+        rte_pmd_qdma_mm_cmpt_process;
+        rte_pmd_qdma_dev_cmptq_stop;
+        rte_pmd_qdma_dbg_qdevice;
+        rte_pmd_qdma_dev_close;
+        rte_pmd_qdma_dev_fp_ops_config;
+        rte_pmd_qdma_compat_pci_write_reg;
+        rte_pmd_qdma_compat_pci_read_reg;
+        rte_pmd_qdma_compat_memzone_reserve_aligned;
+        rte_pmd_qdma_get_bdf;
+        rte_pmd_qdma_dev_remove;
+        rte_pmd_qdma_get_dev_id;
+        rte_pmd_qdma_dev_started;
+        rte_pmd_qdma_eth_dev_to_pci;
+	rte_pmd_qdma_get_device;
+
+
+        local: *;
+};
+
+DPDK_23 {
+        global:
+
+        rte_pmd_qdma_set_immediate_data_state;
+        rte_pmd_qdma_get_bar_details;
+        rte_pmd_qdma_get_queue_base;
+        rte_pmd_qdma_set_queue_mode;
+        rte_pmd_qdma_get_device_capabilities;
+        qdma_pci_read_reg;
+        qdma_pci_write_reg;
+        rte_pmd_qdma_set_mm_endpoint_addr;
+        rte_pmd_qdma_dbg_qdesc;
+        rte_pmd_qdma_dbg_regdump;
+        rte_pmd_qdma_dbg_reg_info_dump;
+        rte_pmd_qdma_dbg_qinfo;
+
+        rte_pmd_qdma_get_pci_func_type;
+        rte_pmd_qdma_configure_tx_bypass;
+        rte_pmd_qdma_configure_rx_bypass;
+        rte_pmd_qdma_set_cmpt_descriptor_size;
+        rte_pmd_qdma_set_c2h_descriptor_prefetch;
+        rte_pmd_qdma_set_cmpt_overflow_check;
+        rte_pmd_qdma_set_cmpt_trigger_mode;
+        rte_pmd_qdma_set_cmpt_timer;
+        rte_pmd_qdma_get_immediate_data_state;
+        rte_pmd_qdma_dev_cmptq_setup;
+        rte_pmd_qdma_dev_cmptq_start;
+        rte_pmd_qdma_mm_cmpt_process;
+        rte_pmd_qdma_dev_cmptq_stop;
+        rte_pmd_qdma_dbg_qdevice;
+        rte_pmd_qdma_dev_close;
+        rte_pmd_qdma_dev_fp_ops_config;
+        rte_pmd_qdma_compat_pci_write_reg;
+        rte_pmd_qdma_compat_pci_read_reg;
+        rte_pmd_qdma_compat_memzone_reserve_aligned;
+        rte_pmd_qdma_get_bdf;
+        rte_pmd_qdma_dev_remove;
+        rte_pmd_qdma_get_dev_id;
+        rte_pmd_qdma_dev_started;
+        rte_pmd_qdma_eth_dev_to_pci;
+	rte_pmd_qdma_get_device;
+
+
+        local: *;
+};
diff --git a/QDMA/DPDK/examples/qdma_testapp/Makefile b/QDMA/DPDK/examples/qdma_testapp/Makefile
index 89f9cf21a5d87fd9cc9f22f9cc0c75752b394836..177c5cf4e8187ae972e81225198e74b03f392be2 100755
--- a/QDMA/DPDK/examples/qdma_testapp/Makefile
+++ b/QDMA/DPDK/examples/qdma_testapp/Makefile
@@ -1,7 +1,7 @@
 #   BSD LICENSE
 #
 #   Copyright (c) 2017-2022 Xilinx, Inc. All rights reserved.
-#   Copyright (c) 2022, Advanced Micro Devices, Inc. All rights reserved.
+#   Copyright (c) 2022-2023, Advanced Micro Devices, Inc. All rights reserved.
 #
 #   Redistribution and use in source and binary forms, with or without
 #   modification, are permitted provided that the following conditions
diff --git a/QDMA/DPDK/examples/qdma_testapp/commands.c b/QDMA/DPDK/examples/qdma_testapp/commands.c
index 7a6cee9e91dc6633b08152145db4a79555de960b..c87bb9bef8b652a11ae4636fa3eef325726af5ba 100755
--- a/QDMA/DPDK/examples/qdma_testapp/commands.c
+++ b/QDMA/DPDK/examples/qdma_testapp/commands.c
@@ -2,7 +2,7 @@
  *   BSD LICENSE
  *
  *   Copyright (c) 2017-2022 Xilinx, Inc. All rights reserved.
- *   Copyright (c) 2022, Advanced Micro Devices, Inc. All rights reserved.
+ *   Copyright (c) 2022-2023, Advanced Micro Devices, Inc. All rights reserved.
  *
  *   Redistribution and use in source and binary forms, with or without
  *   modification, are permitted provided that the following conditions
@@ -1329,7 +1329,9 @@ static void cmd_obj_load_cmds_parsed(void *parsed_result,
 		return;
 	}
 
-	rdline_reset(&cl->rdl);
+
+	struct rdline *rdl = cmdline_get_rdline(cl);
+	rdline_reset(rdl);
 	{
 		cmdline_in(cl, "\r", 1);
 		while (fgets(buff, sizeof(buff), fp))
diff --git a/QDMA/DPDK/examples/qdma_testapp/commands.h b/QDMA/DPDK/examples/qdma_testapp/commands.h
index 75d53433c93a76dc5c2a33a5a0f9e754c3d77d1b..e598e4b68628c1469860a5da99db1756d435d5d6 100755
--- a/QDMA/DPDK/examples/qdma_testapp/commands.h
+++ b/QDMA/DPDK/examples/qdma_testapp/commands.h
@@ -1,7 +1,7 @@
 /*-
  *   BSD LICENSE
  *
- *   Copyright (c) 2010-2022 Intel Corporation. All rights reserved.
+ *   Copyright (c) 2010-2023 Intel Corporation. All rights reserved.
  *   All rights reserved.
  *
  *   Redistribution and use in source and binary forms, with or without
diff --git a/QDMA/DPDK/examples/qdma_testapp/parse_obj_list.c b/QDMA/DPDK/examples/qdma_testapp/parse_obj_list.c
index 26c6cd999bb403b850a89d0680c620d97c8d6d62..f0f38ed1a3c689ed21fe0535174db9e1e882cbfb 100755
--- a/QDMA/DPDK/examples/qdma_testapp/parse_obj_list.c
+++ b/QDMA/DPDK/examples/qdma_testapp/parse_obj_list.c
@@ -2,7 +2,7 @@
  *   BSD LICENSE
  *
  *   Copyright (c) 2017-2022 Xilinx, Inc. All rights reserved.
- *   Copyright (c) 2022, Advanced Micro Devices, Inc. All rights reserved.
+ *   Copyright (c) 2022-2023, Advanced Micro Devices, Inc. All rights reserved.
  *
  *   Redistribution and use in source and binary forms, with or without
  *   modification, are permitted provided that the following conditions
diff --git a/QDMA/DPDK/examples/qdma_testapp/parse_obj_list.h b/QDMA/DPDK/examples/qdma_testapp/parse_obj_list.h
index 711d5c05362a651aabcddd98902b193c46af7d4a..e35e9ded8f4dc3b76ca02d524316ec104600e0b0 100755
--- a/QDMA/DPDK/examples/qdma_testapp/parse_obj_list.h
+++ b/QDMA/DPDK/examples/qdma_testapp/parse_obj_list.h
@@ -2,7 +2,7 @@
  *   BSD LICENSE
  *
  *   Copyright (c) 2017-2022 Xilinx, Inc. All rights reserved.
- *   Copyright (c) 2022, Advanced Micro Devices, Inc. All rights reserved.
+ *   Copyright (c) 2022-2023, Advanced Micro Devices, Inc. All rights reserved.
  *
  *   Redistribution and use in source and binary forms, with or without
  *   modification, are permitted provided that the following conditions
diff --git a/QDMA/DPDK/examples/qdma_testapp/pcierw.c b/QDMA/DPDK/examples/qdma_testapp/pcierw.c
index dcf4e8bddf796897419a3af5a962408d8e9b7df9..ed6830362324255b58c70a534a18bec56f131a4d 100755
--- a/QDMA/DPDK/examples/qdma_testapp/pcierw.c
+++ b/QDMA/DPDK/examples/qdma_testapp/pcierw.c
@@ -2,7 +2,7 @@
  *   BSD LICENSE
  *
  *   Copyright (c) 2017-2022 Xilinx, Inc. All rights reserved.
- *   Copyright (c) 2022, Advanced Micro Devices, Inc. All rights reserved.
+ *   Copyright (c) 2022-2023, Advanced Micro Devices, Inc. All rights reserved.
  *
  *   Redistribution and use in source and binary forms, with or without
  *   modification, are permitted provided that the following conditions
@@ -38,20 +38,19 @@
 #include <stdlib.h>
 #include <string.h>
 #include <rte_ethdev.h>
+#include "../../drivers/net/qdma/rte_pmd_qdma.h"
+
 
 #include "pcierw.h"
 
 unsigned int PciRead(unsigned int bar, unsigned int offset, int port_id)
 {
-
-	return qdma_pci_read_reg(&rte_eth_devices[port_id], bar, offset);
+    return rte_pmd_qdma_compat_pci_read_reg(port_id, bar, offset);
 }
 
 
 void PciWrite(unsigned int bar, unsigned int offset, unsigned int reg_val,
 				int port_id)
 {
-
-	qdma_pci_write_reg(&rte_eth_devices[port_id], bar, offset, reg_val);
-
+    rte_pmd_qdma_compat_pci_write_reg(port_id, bar, offset, reg_val);
 }
diff --git a/QDMA/DPDK/examples/qdma_testapp/pcierw.h b/QDMA/DPDK/examples/qdma_testapp/pcierw.h
index 14dbd9a2557bab7e6f2d8a6fb5126a3868a40b0d..e88f91cd702869f56a9ddd5cda9923c64a93bb9b 100755
--- a/QDMA/DPDK/examples/qdma_testapp/pcierw.h
+++ b/QDMA/DPDK/examples/qdma_testapp/pcierw.h
@@ -2,7 +2,7 @@
  *   BSD LICENSE
  *
  *   Copyright (c) 2017-2022 Xilinx, Inc. All rights reserved.
- *   Copyright (c) 2022, Advanced Micro Devices, Inc. All rights reserved.
+ *   Copyright (c) 2022-2023, Advanced Micro Devices, Inc. All rights reserved.
  *
  *   Redistribution and use in source and binary forms, with or without
  *   modification, are permitted provided that the following conditions
diff --git a/QDMA/DPDK/examples/qdma_testapp/qdma_regs.h b/QDMA/DPDK/examples/qdma_testapp/qdma_regs.h
index c7dac231359203884aa38d090d17e8afd42f93d5..aaf7022c57f26c04d103afc2db4dd83a78a8a965 100755
--- a/QDMA/DPDK/examples/qdma_testapp/qdma_regs.h
+++ b/QDMA/DPDK/examples/qdma_testapp/qdma_regs.h
@@ -2,7 +2,7 @@
  *   BSD LICENSE
  *
  *   Copyright (c) 2017-2022 Xilinx, Inc. All rights reserved.
- *   Copyright (c) 2022, Advanced Micro Devices, Inc. All rights reserved.
+ *   Copyright (c) 2022-2023, Advanced Micro Devices, Inc. All rights reserved.
  *
  *   Redistribution and use in source and binary forms, with or without
  *   modification, are permitted provided that the following conditions
diff --git a/QDMA/DPDK/examples/qdma_testapp/testapp.c b/QDMA/DPDK/examples/qdma_testapp/testapp.c
index a1ccf2e837512ea7cf35eab484b245f9943a732d..79a00d6a9c37f4b759065ef0f479ce571d5c361e 100755
--- a/QDMA/DPDK/examples/qdma_testapp/testapp.c
+++ b/QDMA/DPDK/examples/qdma_testapp/testapp.c
@@ -2,7 +2,7 @@
  *   BSD LICENSE
  *
  *   Copyright (c) 2017-2022 Xilinx, Inc. All rights reserved.
- *   Copyright (c) 2022, Advanced Micro Devices, Inc. All rights reserved.
+ *   Copyright (c) 2022-2023, Advanced Micro Devices, Inc. All rights reserved.
  *
  *   Redistribution and use in source and binary forms, with or without
  *   modification, are permitted provided that the following conditions
@@ -62,6 +62,8 @@
 #include "testapp.h"
 #include "../../drivers/net/qdma/rte_pmd_qdma.h"
 
+#define RTE_LIBRTE_QDMA_PMD 1
+
 int num_ports;
 char *filename;
 
@@ -70,7 +72,6 @@ struct port_info pinfo[QDMA_MAX_PORTS];
 int do_recv_mm(int port_id, int fd, int queueid, int ld_size, int tot_num_desc)
 {
 	struct rte_mbuf *pkts[NUM_RX_PKTS] = { NULL };
-	struct rte_device *dev;
 	int nb_rx = 0, i = 0, ret = 0, num_pkts;
 	int tdesc;
 #ifdef PERF_BENCHMARK
@@ -84,8 +85,7 @@ int do_recv_mm(int port_id, int fd, int queueid, int ld_size, int tot_num_desc)
 
 	rte_spinlock_lock(&pinfo[port_id].port_update_lock);
 
-	dev = rte_eth_devices[port_id].device;
-	if (dev == NULL) {
+	if (rte_pmd_qdma_get_device(port_id) == NULL) {
 		printf("Port id %d already removed. "
 			"Relaunch application to use the port again\n",
 			port_id);
@@ -185,7 +185,6 @@ int do_recv_st(int port_id, int fd, int queueid, int input_size)
 	int regval;
 	int user_bar_idx;
 	struct rte_mbuf *nxtmb;
-	struct rte_device *dev;
 	int qbase = pinfo[port_id].queue_base, diag;
 	unsigned int max_completion_size, last_pkt_size = 0, total_rcv_pkts = 0;
 	unsigned int max_rx_retry, rcv_count = 0, num_pkts_recv = 0;
@@ -197,8 +196,7 @@ int do_recv_st(int port_id, int fd, int queueid, int input_size)
 
 	rte_spinlock_lock(&pinfo[port_id].port_update_lock);
 
-	dev = rte_eth_devices[port_id].device;
-	if (dev == NULL) {
+	if (rte_pmd_qdma_get_device(port_id) == NULL) {
 		printf("Port id %d already removed. "
 			"Relaunch application to use the port again\n",
 			port_id);
@@ -437,8 +435,7 @@ int do_xmit(int port_id, int fd, int queueid, int ld_size, int tot_num_desc,
 				int zbyte)
 {
 	struct rte_mempool *mp;
-	struct rte_mbuf *mb[NUM_RX_PKTS] = { NULL };
-	struct rte_device *dev;
+	struct rte_mbuf *mb[NUM_TX_PKTS] = { NULL };
 	int ret = 0, nb_tx, i = 0, tdesc, num_pkts = 0, total_tx = 0, reg_val;
 	int tmp = 0, user_bar_idx;
 	int qbase = pinfo[port_id].queue_base;
@@ -450,8 +447,7 @@ int do_xmit(int port_id, int fd, int queueid, int ld_size, int tot_num_desc,
 
 	rte_spinlock_lock(&pinfo[port_id].port_update_lock);
 
-	dev = rte_eth_devices[port_id].device;
-	if (dev == NULL) {
+	if (rte_pmd_qdma_get_device(port_id) == NULL) {
 		printf("Port id %d already removed. "
 			"Relaunch application to use the port again\n",
 			port_id);
@@ -475,8 +471,8 @@ int do_xmit(int port_id, int fd, int queueid, int ld_size, int tot_num_desc,
 		tdesc--;
 
 	while (tdesc) {
-		if (tdesc > NUM_RX_PKTS)
-			num_pkts = NUM_RX_PKTS;
+		if (tdesc > NUM_TX_PKTS)
+			num_pkts = NUM_TX_PKTS;
 		else
 			num_pkts = tdesc;
 
@@ -684,14 +680,12 @@ static int dev_remove_callback(uint16_t port_id,
 void port_close(int port_id)
 {
 	struct rte_mempool *mp;
-	struct rte_device  *dev;
 	struct rte_pmd_qdma_dev_attributes dev_attr;
 	int user_bar_idx;
 	int reg_val;
 	int ret = 0;
 
-	dev = rte_eth_devices[port_id].device;
-	if (dev == NULL) {
+	if (rte_pmd_qdma_dev_remove(port_id)) {
 		printf("Port id %d already removed. "
 			"Relaunch application to use the port again\n",
 			port_id);
@@ -741,12 +735,10 @@ int port_reset(int port_id, int num_queues, int st_queues,
 				int nb_descs, int buff_size)
 {
 	int ret = 0;
-	struct rte_device   *dev;
 
 	printf("%s is received\n", __func__);
 
-	dev = rte_eth_devices[port_id].device;
-	if (dev == NULL) {
+	if (rte_pmd_qdma_get_device(port_id) == NULL) {
 		printf("Port id %d already removed. "
 			"Relaunch application to use the port again\n",
 			port_id);
@@ -780,15 +772,13 @@ int port_reset(int port_id, int num_queues, int st_queues,
 
 int port_remove(int port_id)
 {
-	struct rte_device *dev;
 	int ret = 0;
 
 	printf("%s is received\n", __func__);
 
 	/* Detach the port, it will invoke device remove/uninit */
 	printf("Removing a device with port id %d\n", port_id);
-	dev = rte_eth_devices[port_id].device;
-	if (dev == NULL) {
+	if (rte_pmd_qdma_dev_remove(port_id)) {
 		printf("Port id %d already removed\n", port_id);
 		return 0;
 	}
@@ -797,7 +787,7 @@ int port_remove(int port_id)
 
 	port_close(port_id);
 
-	ret = rte_dev_remove(dev);
+	ret = rte_pmd_qdma_dev_remove(port_id);
 	if (ret < 0)
 		printf("Failed to remove device on port_id: %d\n", port_id);
 
@@ -865,12 +855,10 @@ int port_init(int port_id, int num_queues, int st_queues,
 	struct rte_eth_rxconf   rx_conf;
 	int                     diag, x;
 	uint32_t                queue_base, nb_buff;
-	struct rte_device       *dev;
 
 	printf("Setting up port :%d.\n", port_id);
 
-	dev = rte_eth_devices[port_id].device;
-	if (dev == NULL) {
+	if (rte_pmd_qdma_get_device(port_id) == NULL) {
 		printf("Port id %d already removed. "
 			"Relaunch application to use the port again\n",
 			port_id);
@@ -883,11 +871,11 @@ int port_init(int port_id, int num_queues, int st_queues,
 	/* Mbuf packet pool */
 	nb_buff = ((nb_descs) * num_queues * 2);
 
-	/* NUM_RX_PKTS should be added to every queue as that many descriptors
+	/* NUM_TX_PKTS should be added to every queue as that many descriptors
 	 * can be pending with application after Rx processing but before
 	 * consumed by application or sent to Tx
 	 */
-	nb_buff += ((NUM_RX_PKTS) * num_queues);
+	nb_buff += ((NUM_TX_PKTS) * num_queues);
 
 	mbuf_pool = rte_pktmbuf_pool_create(pinfo[port_id].mem_pool, nb_buff,
 			MP_CACHE_SZ, 0, buff_size +
@@ -1000,7 +988,8 @@ void load_file_cmds(struct cmdline *cl)
 		return;
 	}
 
-	rdline_reset(&cl->rdl);
+	struct rdline *rdl = cmdline_get_rdline(cl);
+	rdline_reset(rdl);
 	{
 		cmdline_in(cl, "\r", 1);
 		while (fgets(buff, sizeof(buff), fp))
@@ -1064,13 +1053,8 @@ int main(int argc, char **argv)
 	/* Make sure things are defined ... */
 	do_sanity_checks();
 
-	mz = rte_memzone_reserve_aligned("eth_devices", RTE_MAX_ETHPORTS *
-					  sizeof(*rte_eth_devices), 0, 0, 4096);
-	if (mz == NULL)
-		rte_exit(EXIT_FAILURE, "Failed to allocate aligned memzone\n");
-
-	memcpy(mz->addr, &rte_eth_devices[0], RTE_MAX_ETHPORTS *
-					sizeof(*rte_eth_devices));
+	/* Allocate aligned mezone */
+	rte_pmd_qdma_compat_memzone_reserve_aligned();
 
 	cl = cmdline_stdin_new(main_ctx, "xilinx-app> ");
 	if (cl == NULL)
@@ -1094,21 +1078,19 @@ int main(int argc, char **argv)
 		printf("Ports already removed\n");
 	else {
 		for (port_id = num_ports - 1; port_id >= 0; port_id--) {
-			struct rte_device *dev;
 
 			if (pinfo[port_id].num_queues)
 				port_close(port_id);
 
 			printf("Removing a device with port id %d\n", port_id);
-			dev = rte_eth_devices[port_id].device;
-			if (dev == NULL) {
+			if (rte_pmd_qdma_get_device(port_id) == NULL) {
 				printf("Port id %d already removed\n", port_id);
 				continue;
 			}
 			/* Detach the port, it will invoke
 			 * device remove/uninit
 			 */
-			if (rte_dev_remove(dev))
+			if (rte_pmd_qdma_dev_remove(port_id))
 				printf("Failed to detach port '%d'\n", port_id);
 		}
 	}
diff --git a/QDMA/DPDK/examples/qdma_testapp/testapp.h b/QDMA/DPDK/examples/qdma_testapp/testapp.h
index b487c35fbac81fbd047171fea031b221ab79f88c..5d58a0d02fb1298775bbce050984c92aaa123d23 100755
--- a/QDMA/DPDK/examples/qdma_testapp/testapp.h
+++ b/QDMA/DPDK/examples/qdma_testapp/testapp.h
@@ -2,7 +2,7 @@
  *   BSD LICENSE
  *
  *   Copyright (c) 2017-2022 Xilinx, Inc. All rights reserved.
- *   Copyright (c) 2022, Advanced Micro Devices, Inc. All rights reserved.
+ *   Copyright (c) 2022-2023, Advanced Micro Devices, Inc. All rights reserved.
  *
  *   Redistribution and use in source and binary forms, with or without
  *   modification, are permitted provided that the following conditions
@@ -41,6 +41,19 @@
 #else
 #define NUM_RX_PKTS 32
 #endif
+
+/* Tandem boot feature involves DMA transfer of
+ * second stage bootloader size greater than 2MB
+ * from Host to Slave Boot Interface(SBI) buffer.
+ * Increased the limit of pending tx packets that need
+ * to process by application to avoid transfer timeouts.
+ */
+#ifdef TANDEM_BOOT_SUPPORTED
+#define NUM_TX_PKTS 128
+#else
+#define NUM_TX_PKTS 32
+#endif
+
 #define MAX_NUM_QUEUES 4096
 #define DEFAULT_NUM_QUEUES 64
 #define RX_TX_MAX_RETRY			1500
diff --git a/QDMA/linux-kernel/RELEASE b/QDMA/linux-kernel/RELEASE
index 170685788ac7ae56f4cfbacae3d89bf882ee3bde..bab000f15c6442ec549cb901d87a39e7141c4587 100755
--- a/QDMA/linux-kernel/RELEASE
+++ b/QDMA/linux-kernel/RELEASE
@@ -127,19 +127,19 @@ CPM5
 ----------------------
 - Added PF/VF 4K queues support for CPM5 design. This feature is applicable only when corresponding RTL support is added.
 
-2023.1 Updates
---------------
+2023.1.0 Updates
+----------------
 - Updated the queue list command for >2048 Q's.
 - Added support to accomodate H2C & C2H Q's offset with fixed intervals for dma-perf application.
 
 KNOWN ISSUES:
 =============
 - CPM5 Only
-	- Data transfers are not happening when FLR is triggered with 10 VFs created on each PF.
-    - Performace optimizations are not finalized yet.
+	- When >10VFs are attached to PF and FLR is issued, mailbox timeouts are observed.
+    - Performace optimizations are not finalized, Performance report with optimizations will be available in next patch release.
 
 - QDAM5.0
-    - Performace optimizations are not finalized yet.
+    - Performace optimizations are not finalized, Performance report with optimizations will be available in next patch release.
 
 - All Designs
 	- In interrupt mode, Sometimes completions are not received when C2H PIDX updates are held for 64 descriptors