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Nursultan Kabylkas authored
* Summary: initial dromajo integration * some changes to Makefile to enable `make verilate DROMAJO=1` * adding ifdefs to ariane_tb.cpp to disable HTIF * adding dromajo repo * making dromajo repo a submodule * syncing with upstream * bumping to the latest dromajo commit * Summary: adding DPI functions for cosim * added new file tb/dpi/dromajo_cosim.cc that contains all DPIs for dromajo to work * editted Makefile to see the above file * Summary: fixing build issues * fixing syntax errors in dpi file * renaming dpi file due to name conflict with shared library * fixing path in Makefile to the shared dromajo lib * bumping to the latest dromajo change * Summary: loading checkpoint to bootrom This change adds `+checkpoint=` argument to the verilator simulator as well as corresponding changes to load the dromajo checkpoint into the bootrom. Dromajo checkpoint bootcode contains series of csrw and immediate loads to restore the architectural state of the processor. dromajo_bootrom.sv is a copy of a generated bootrom.sv file. This file parses the verilog plusargs and loads the bootrom with the code that is pointed by the +checkpoint. csr_regfile.sv Dromajo needs to start running the code in debug mode. The default value of debug_mode_q was changed to 1. * updating dromajo to the latest change * Summary: sync main memories of dromajo and ariane These changes load the checkpoint into the main memory of Ariane. The checkpointed memory that is dumped from dromajo contains (1) the binary and (2) the values of all stores that dromajo globally performed before dumping the checkpoint. dromajo_ram.sv This file is a copy of SyncSpRamBeNx64.sv and was modified to parse +checkpoint argument to load the memory from the path pointed by the argument. The remaining changes were introduced to instantiate the above file when DROMAJO=1 flag is set. * Summary: calling DPIs for cosimulation This change introduces the calls to DPI functions that interface with Dromajo. * updating to the latest commit of dromajo * disabling verbose output when preloading bootrom and mainram * Summary: bug fix - update logic of `dcsr_d.prv` This change was made per discussion with Florian via email. The current versionincorrectly implements the update logic of `dcsr_d.prv`. The confusion came from the fact that the core should update its `dcsr_d.prv` to the current running privilege level when entering debug mode. I've attached a patch which, as you suggested, removes the wrong update logic in the CSR write process and should now correctly handle the update when entering debug mode (4.9.1 Debug Control and Status of the debug specification). * bump to the latest version of dromajo * Summary: dromajo DPI change This change: * Ariane doesn't commit ebreaks and ecalls so some workaround was encorporated * Proper exit(0) on cosim pass * Summary: support for running binaries with dromajo This change adds the ability to run the following command: `make run_dromajo BIN=\path\to\riscv\bin` It automates the dromajo's checkpoint creation and runs the binary on Ariane with dromajo cosimulation. For this to work Ariane must be build with DROMAJO=1. * changing dromajo recipe name to be consistent with existing names * adding instructions on how to run cosim with dromajo * Bump to release 0.6.2 * added license headers * added more details about dromajo
Nursultan Kabylkas authored* Summary: initial dromajo integration * some changes to Makefile to enable `make verilate DROMAJO=1` * adding ifdefs to ariane_tb.cpp to disable HTIF * adding dromajo repo * making dromajo repo a submodule * syncing with upstream * bumping to the latest dromajo commit * Summary: adding DPI functions for cosim * added new file tb/dpi/dromajo_cosim.cc that contains all DPIs for dromajo to work * editted Makefile to see the above file * Summary: fixing build issues * fixing syntax errors in dpi file * renaming dpi file due to name conflict with shared library * fixing path in Makefile to the shared dromajo lib * bumping to the latest dromajo change * Summary: loading checkpoint to bootrom This change adds `+checkpoint=` argument to the verilator simulator as well as corresponding changes to load the dromajo checkpoint into the bootrom. Dromajo checkpoint bootcode contains series of csrw and immediate loads to restore the architectural state of the processor. dromajo_bootrom.sv is a copy of a generated bootrom.sv file. This file parses the verilog plusargs and loads the bootrom with the code that is pointed by the +checkpoint. csr_regfile.sv Dromajo needs to start running the code in debug mode. The default value of debug_mode_q was changed to 1. * updating dromajo to the latest change * Summary: sync main memories of dromajo and ariane These changes load the checkpoint into the main memory of Ariane. The checkpointed memory that is dumped from dromajo contains (1) the binary and (2) the values of all stores that dromajo globally performed before dumping the checkpoint. dromajo_ram.sv This file is a copy of SyncSpRamBeNx64.sv and was modified to parse +checkpoint argument to load the memory from the path pointed by the argument. The remaining changes were introduced to instantiate the above file when DROMAJO=1 flag is set. * Summary: calling DPIs for cosimulation This change introduces the calls to DPI functions that interface with Dromajo. * updating to the latest commit of dromajo * disabling verbose output when preloading bootrom and mainram * Summary: bug fix - update logic of `dcsr_d.prv` This change was made per discussion with Florian via email. The current versionincorrectly implements the update logic of `dcsr_d.prv`. The confusion came from the fact that the core should update its `dcsr_d.prv` to the current running privilege level when entering debug mode. I've attached a patch which, as you suggested, removes the wrong update logic in the CSR write process and should now correctly handle the update when entering debug mode (4.9.1 Debug Control and Status of the debug specification). * bump to the latest version of dromajo * Summary: dromajo DPI change This change: * Ariane doesn't commit ebreaks and ecalls so some workaround was encorporated * Proper exit(0) on cosim pass * Summary: support for running binaries with dromajo This change adds the ability to run the following command: `make run_dromajo BIN=\path\to\riscv\bin` It automates the dromajo's checkpoint creation and runs the binary on Ariane with dromajo cosimulation. For this to work Ariane must be build with DROMAJO=1. * changing dromajo recipe name to be consistent with existing names * adding instructions on how to run cosim with dromajo * Bump to release 0.6.2 * added license headers * added more details about dromajo
Flist.ariane 4.78 KiB
// Copyright (c) 2018 ETH Zurich, University of Bologna
// All rights reserved.
//
// This code is under development and not yet released to the public.
// Until it is released, the code is under the copyright of ETH Zurich and
// the University of Bologna, and may contain confidential and/or unpublished
// work. Any reuse/redistribution is strictly forbidden without written
// permission from ETH Zurich.
//
// Bug fixes and contributions will eventually be released under the
// SolderPad open hardware license in the context of the PULP platform
// (http://www.pulp-platform.org), under the copyright of ETH Zurich and the
// University of Bologna.
//
// Author: Michael Schaffner <schaffner@iis.ee.ethz.ch>, ETH Zurich
// Date: 15.08.2018
// Description: File list for OpenPiton flow
+incdir+src/common_cells/include/
+incdir+src/util/
include/riscv_pkg.sv
src/riscv-dbg/src/dm_pkg.sv
include/ariane_pkg.sv
src/common_cells/src/deprecated/rrarbiter.sv
src/common_cells/src/deprecated/fifo_v1.sv
src/common_cells/src/deprecated/fifo_v2.sv
src/common_cells/src/fifo_v3.sv
src/common_cells/src/lfsr_8bit.sv
src/common_cells/src/lzc.sv
src/common_cells/src/rr_arb_tree.sv
src/common_cells/src/rstgen_bypass.sv
src/common_cells/src/cdc_2phase.sv
src/common_cells/src/shift_reg.sv
src/common_cells/src/unread.sv
src/common_cells/src/popcount.sv
src/common_cells/src/exp_backoff.sv
src/register_interface/src/apb_to_reg.sv
src/register_interface/src/reg_intf_pkg.sv
src/register_interface/src/reg_intf.sv
src/fpu/src/fpnew_pkg.sv
src/fpu/src/fpu_div_sqrt_mvp/hdl/defs_div_sqrt_mvp.sv
src/fpu/src/fpu_div_sqrt_mvp/hdl/control_mvp.sv
src/fpu/src/fpu_div_sqrt_mvp/hdl/div_sqrt_mvp_wrapper.sv
src/fpu/src/fpu_div_sqrt_mvp/hdl/div_sqrt_top_mvp.sv
src/fpu/src/fpu_div_sqrt_mvp/hdl/iteration_div_sqrt_mvp.sv
src/fpu/src/fpu_div_sqrt_mvp/hdl/norm_div_sqrt_mvp.sv
src/fpu/src/fpu_div_sqrt_mvp/hdl/nrbd_nrsc_mvp.sv
src/fpu/src/fpu_div_sqrt_mvp/hdl/preprocess_mvp.sv
src/fpu/src/fpnew_cast_multi.sv
src/fpu/src/fpnew_classifier.sv
src/fpu/src/fpnew_divsqrt_multi.sv
src/fpu/src/fpnew_fma_multi.sv
src/fpu/src/fpnew_fma.sv
src/fpu/src/fpnew_noncomp.sv
src/fpu/src/fpnew_opgroup_block.sv
src/fpu/src/fpnew_opgroup_fmt_slice.sv
src/fpu/src/fpnew_opgroup_multifmt_slice.sv
src/fpu/src/fpnew_rounding.sv
src/fpu/src/fpnew_top.sv
src/axi/src/axi_pkg.sv
tb/ariane_soc_pkg.sv
include/ariane_axi_pkg.sv
include/wt_cache_pkg.sv
//include/std_cache_pkg.sv
include/axi_intf.sv
include/instr_tracer_pkg.sv
src/util/instr_tracer_if.sv
src/util/instr_tracer.sv
src/util/sram.sv
src/util/axi_master_connect.sv
src/util/axi_master_connect_rev.svsrc/util/axi_slave_connect.sv
src/util/axi_slave_connect_rev.sv
src/fpga-support/rtl/SyncSpRamBeNx64.sv
src/dromajo_ram.sv
src/axi_mem_if/src/axi2mem.sv
src/tech_cells_generic/src/pulp_clock_gating.sv
src/tech_cells_generic/src/cluster_clock_inverter.sv
src/tech_cells_generic/src/pulp_clock_mux2.sv
src/axi_adapter.sv
src/alu.sv
src/fpu_wrap.sv
src/ariane.sv
src/branch_unit.sv
src/compressed_decoder.sv
src/controller.sv
src/csr_buffer.sv
src/csr_regfile.sv
src/decoder.sv
src/ex_stage.sv
src/instr_realign.sv
src/frontend/btb.sv
src/frontend/bht.sv
src/frontend/ras.sv
src/frontend/instr_scan.sv
src/frontend/instr_queue.sv
src/frontend/frontend.sv
src/id_stage.sv
src/issue_read_operands.sv
src/issue_stage.sv
src/load_unit.sv
src/load_store_unit.sv
src/mmu.sv
src/mult.sv
src/multiplier.sv
src/serdiv.sv
src/perf_counters.sv
src/ptw.sv
src/ariane_regfile_ff.sv
src/re_name.sv
src/scoreboard.sv
src/store_buffer.sv
src/amo_buffer.sv
src/store_unit.sv
src/tlb.sv
src/commit_stage.sv
src/cache_subsystem/wt_dcache_ctrl.sv
src/cache_subsystem/wt_dcache_mem.sv
src/cache_subsystem/wt_dcache_missunit.sv
src/cache_subsystem/wt_dcache_wbuffer.sv
src/cache_subsystem/wt_dcache.sv
src/cache_subsystem/wt_icache.sv
src/cache_subsystem/wt_l15_adapter.sv
src/cache_subsystem/wt_cache_subsystem.sv
src/clint/clint.sv
src/clint/axi_lite_interface.sv
src/riscv-dbg/src/dm_csrs.sv
src/riscv-dbg/src/dm_mem.sv
src/riscv-dbg/src/dm_top.sv
src/riscv-dbg/src/dmi_cdc.sv
src/riscv-dbg/src/dmi_jtag.sv
src/riscv-dbg/src/dm_sba.sv
src/riscv-dbg/src/dmi_jtag_tap.sv
src/riscv-dbg/debug_rom/debug_rom.sv
openpiton/ariane_verilog_wrap.sv
openpiton/riscv_peripherals.sv
openpiton/bootrom/baremetal/bootrom.sv
openpiton/bootrom/linux/bootrom_linux.sv
src/rv_plic/rtl/rv_plic_target.sv
src/rv_plic/rtl/rv_plic_gateway.sv
src/rv_plic/rtl/plic_regmap.svsrc/rv_plic/rtl/plic_top.sv
fpga/src/axi2apb/src/axi2apb_wrap.sv
fpga/src/axi2apb/src/axi2apb.sv
fpga/src/axi2apb/src/axi2apb_64_32.sv
fpga/src/axi_slice/src/axi_w_buffer.sv
fpga/src/axi_slice/src/axi_b_buffer.sv
fpga/src/axi_slice/src/axi_slice_wrap.sv
fpga/src/axi_slice/src/axi_slice.sv
fpga/src/axi_slice/src/axi_single_slice.sv
fpga/src/axi_slice/src/axi_ar_buffer.sv
fpga/src/axi_slice/src/axi_r_buffer.sv
fpga/src/axi_slice/src/axi_aw_buffer.sv