Maturity fixes and AXI extensions for write-through cache system (#188)

* : Fix PITON_ARIANE define issues
* Fix write-back / cache read collision issue in serpent dcache.
* Add separate bootrom / device tree for openpiton (hardcoded for 1x1 tile config at the moment).
* Bootrom generation update (better compatibility with older python versions), new bootrom for OpenPiton+Ariane.
* Fix assertion in icache.
* Correct JTAG timing constraints.
* Fix parameter type in fpga toplevel (fix #168).
* Remove conflicting bootrom from fpga file list.
* This flushs the branch predictors when entering exception handlers in order to avoid speculative fetches from virtual addresses (to be improved with PMAs).
* Fix byte offset of IPIs in CLINT
* Disable DCache flushes on fence for write-through cache (not needed in that case)
* Fix blocking assignments in ff process.
* Fix register access issue in debug mode, only affects A0 (fix #179).
* Fix multiple driver issue in PLIC
* Do not assume replicated data in serpent dcache when reading from an NC region.
* Another byte offset fix in IPIs (CLINT)
* Add AXI64 compliance switch to dcache_mem
* Fix genesys 2 constraints
* Map serpent atomic requests onto AXI atomic/exclusive transactions.
* Cleanup of AXI memory plumbing, add separate AXI adapter module.
* Remove unneeded interface signals, increase wbuffer #pending tx
* Fix verilator compilation issues in AXI adapter.
* Delete unnecessary constraint
* Delete duplicate module instance
* Update gitlab CI script
* Small fixes to make riscv atomics work with serpent_axi_adapter.
* Update travis and gitlab-ci scripts
* Register b responses for better timing.
* Remove fpu div submodule, update Makefile paths and src lists
* Constant bits in haltsum reduction must be 1 (AND reduction).
* Switch to DTM from riscv-dbg submodule
* Further cleanup fixes in AXI/serpent atomics
* Bump riscv-dbg version