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Commit 095cda61 authored by Florian Zaruba's avatar Florian Zaruba
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load_store_unit: Fix #70 default assignment issue

parent 970022dd
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...@@ -10,6 +10,7 @@ and this project adheres to [Semantic Versioning](http://semver.org/spec/v2.0.0. ...@@ -10,6 +10,7 @@ and this project adheres to [Semantic Versioning](http://semver.org/spec/v2.0.0.
- Fix bug in wt_axi_adapter (only appeared when dcache lines were wider than icache lines) - Fix bug in wt_axi_adapter (only appeared when dcache lines were wider than icache lines)
- Fix potentially long timing path in `axi_lite_interface` - Fix potentially long timing path in `axi_lite_interface`
- Fix VCS elab warning in `load_store_unit`
### 4.1.2 ### 4.1.2
......
...@@ -435,13 +435,13 @@ module lsu_bypass ( ...@@ -435,13 +435,13 @@ module lsu_bypass (
end end
if (pop_st_i && pop_ld_i) if (pop_st_i && pop_ld_i)
mem_n = '{default: 0}; mem_n = '0;
if (flush_i) begin if (flush_i) begin
status_cnt = '0; status_cnt = '0;
write_pointer = '0; write_pointer = '0;
read_pointer = '0; read_pointer = '0;
mem_n = '{default: 0}; mem_n = '0;
end end
// default assignments // default assignments
read_pointer_n = read_pointer; read_pointer_n = read_pointer;
...@@ -461,7 +461,7 @@ module lsu_bypass ( ...@@ -461,7 +461,7 @@ module lsu_bypass (
// registers // registers
always_ff @(posedge clk_i or negedge rst_ni) begin always_ff @(posedge clk_i or negedge rst_ni) begin
if (~rst_ni) begin if (~rst_ni) begin
mem_q <= '{default: 0}; mem_q <= '0;
status_cnt_q <= '0; status_cnt_q <= '0;
write_pointer_q <= '0; write_pointer_q <= '0;
read_pointer_q <= '0; read_pointer_q <= '0;
......
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