Unverified Commit 0abb1a6d authored by sébastien jacq's avatar sébastien jacq Committed by GitHub
Browse files

Merge pull request #5 from sjthales/master

add ddr support 
parents 5965c3da 04ce150d
Pipeline #461 failed with stages
......@@ -288,7 +288,7 @@ cva6_ooc: $(ariane_pkg) $(util) $(src) $(fpga_src)
@echo read_verilog -sv {$(fpga_src)} >> fpga/scripts/add_sources.tcl
cd fpga && make cva6_ooc BOARD=$(BOARD) XILINX_PART=$(XILINX_PART) XILINX_BOARD=$(XILINX_BOARD) CLK_PERIOD_NS=$(CLK_PERIOD_NS) BATCH_MODE=$(BATCH_MODE)
.PHONY: cva6_ooc cva6_fpga program_cva6_fpga get_hs2_sn
.PHONY: cva6_ooc cva6_fpga program_cva6_fpga
cva6_fpga: $(ariane_pkg) $(util) $(src) $(fpga_src) $(uart_src)
@echo "[FPGA] Generate sources"
......@@ -298,7 +298,17 @@ cva6_fpga: $(ariane_pkg) $(util) $(src) $(fpga_src) $(uart_src)
@echo read_verilog -sv {$(filter-out $(fpga_filter), $(src))} >> fpga/scripts/add_sources.tcl
@echo read_verilog -sv {$(fpga_src)} >> fpga/scripts/add_sources.tcl
@echo "[FPGA] Generate Bitstream"
cd fpga && make cva6_fpga BOARD=$(BOARD) XILINX_PART=$(XILINX_PART) XILINX_BOARD=$(XILINX_BOARD) CLK_PERIOD_NS=$(CLK_PERIOD_NS) BATCH_MODE=$(BATCH_MODE)
cd fpga && make cva6_fpga BRAM=1 PS7_DDR=0 BOARD=$(BOARD) XILINX_PART=$(XILINX_PART) XILINX_BOARD=$(XILINX_BOARD) CLK_PERIOD_NS=$(CLK_PERIOD_NS) BATCH_MODE=$(BATCH_MODE)
cva6_fpga_ddr: $(ariane_pkg) $(util) $(src) $(fpga_src) $(uart_src)
@echo "[FPGA] Generate sources"
@echo read_vhdl {$(uart_src)} > fpga/scripts/add_sources.tcl
@echo read_verilog -sv {$(ariane_pkg)} >> fpga/scripts/add_sources.tcl
@echo read_verilog -sv {$(filter-out $(fpga_filter), $(util))} >> fpga/scripts/add_sources.tcl
@echo read_verilog -sv {$(filter-out $(fpga_filter), $(src))} >> fpga/scripts/add_sources.tcl
@echo read_verilog -sv {$(fpga_src)} >> fpga/scripts/add_sources.tcl
@echo "[FPGA] Generate Bitstream"
cd fpga && make cva6_fpga PS7_DDR=1 BRAM=0 XILINX_PART=$(XILINX_PART) XILINX_BOARD=$(XILINX_BOARD) CLK_PERIOD_NS=$(CLK_PERIOD_NS) BATCH_MODE=$(BATCH_MODE)
program_cva6_fpga:
......@@ -306,10 +316,6 @@ program_cva6_fpga:
cd fpga && make program_cva6_fpga BOARD=$(BOARD) XILINX_PART=$(XILINX_PART) XILINX_BOARD=$(XILINX_BOARD) CLK_PERIOD_NS=$(CLK_PERIOD_NS) BATCH_MODE=$(BATCH_MODE)
get_hs2_sn:
@echo "[FPGA] Get HS2 serial number"
cd fpga && make get_hs2_sn
clean:
rm -rf $(riscv-torture-dir)/output/test*
rm -rf $(library)/ $(dpi-library)/ $(ver-library)/
......
......@@ -234,32 +234,23 @@ The JTAG-HS2 programming cable is initially a cable that allows programming of X
In our case, we use this cable to program software applications on the CV32A6 instantiated in the FPGA through a PMOD connector.
We do not use the HS2 Cable in its original function therfore there is a preliminary step which consists in retrieving the serial number of the HS2 cable.
To do this, connect the HS2 cable to the host PC (Zybo Z7-20 board must be disconnected from the host PC) and run the following command:
```
make get_hs2_sn
```
you should see:
```
[FPGA] Get HS2 serial number
...............
###############################
# TARGEt: localhost:3121/xilinx_tcf/Digilent/<HS2's serial number>
###############################
......................
```
Replace the **HS2's serial number** in `fpga/scripts/program_cva-fpga.tcl` file by the serial number of your HS2 cable.
## Get started with Coremark application
1. First, make sure the Digilent **JTAG-HS2 debug adapter** is properly connected to the **PMOD JE** connector and that the USBUART adapter is properly connected to the **PMOD JB** connector of the Zybo Z7-20 board.
![alt text](https://github.com/sjthales/cva6-softcore-contest/blob/master/docs/pictures/20201204_150708.jpg)
2. Compile Coremark application in `sw/app`. Commands to compile Coremark application are described in `sw/app` directory.
3. Generate the bitstream of the FPGA platform:
3. Generate the bitstream of the FPGA platform. There are **two** FPGA platform, one using BRAM as main memory and another one using DDR conected to Zynq PS as main memory. Using the DDR allows savings of logic resources in FPGA fabric. You can choose the FPGA platform you want to implement :
If you want to implement the FPGA platform using BRAM, you have to run the following command:
```
$ make cva6_fpga
```
If you want to implement the FPGA platform using DDR, you have to run the following command:
```
$ make cva6_fpga_ddr
```
4. When the bitstream is generated, switch on Zybo board and run:
```
$ make program_cva6_fpga
......
......@@ -33,8 +33,9 @@ work-dir := work-fpga
bit := $(work-dir)/cva6_fpga.bit
ip-dir := xilinx
ips := xlnx_blk_mem_gen.xci \
xlnx_axi_clock_converter.xci \
ips := xlnx_blk_mem_gen.xci \
xlnx_processing_system7.xci \
xlnx_axi_clock_converter.xci \
xlnx_axi_dwidth_converter_dm_master.xci \
xlnx_axi_dwidth_converter_dm_slave.xci \
xlnx_clk_gen.xci
......@@ -56,12 +57,10 @@ else
$(VIVADO) -source scripts/run_cva6_fpga.tcl
endif
program_cva6_fpga:
ifeq ($(BATCH_MODE), 1)
$(VIVADO) -mode batch -source scripts/program_cva6_fpga.tcl
else
$(VIVADO) -source scripts/program_cva6_fpga.tcl
endif
xsct scripts/program_cva6_fpga.tcl
get_hs2_sn:
$(VIVADO) -mode batch -source scripts/get_hs2_sn.tcl
......
......@@ -19,35 +19,4 @@ set_max_delay -datapath_only -from [get_pins i_dmi_jtag/i_dmi_cdc/i_cdc_req/i_ds
set_multicycle_path -from [get_pins {i_rstgen_main/i_rstgen_bypass/synch_regs_q_reg[3]/C}] 4
set_multicycle_path -hold -from [get_pins {i_rstgen_main/i_rstgen_bypass/synch_regs_q_reg[3]/C}] 3
set_property MARK_DEBUG false [get_nets {debug_req[data][7]}]
set_property MARK_DEBUG false [get_nets {debug_req[data][4]}]
set_property MARK_DEBUG false [get_nets {debug_req[data][0]}]
set_property MARK_DEBUG false [get_nets {debug_req[data][1]}]
set_property MARK_DEBUG false [get_nets {debug_req[data][2]}]
set_property MARK_DEBUG false [get_nets {debug_req[data][3]}]
set_property MARK_DEBUG false [get_nets {debug_req[data][5]}]
set_property MARK_DEBUG false [get_nets {debug_req[data][6]}]
set_property MARK_DEBUG false [get_nets {debug_req[data][8]}]
set_property MARK_DEBUG false [get_nets {debug_req[data][11]}]
set_property MARK_DEBUG false [get_nets {debug_req[data][13]}]
set_property MARK_DEBUG false [get_nets {debug_req[data][15]}]
set_property MARK_DEBUG false [get_nets {debug_req[data][17]}]
set_property MARK_DEBUG false [get_nets {debug_req[data][19]}]
set_property MARK_DEBUG false [get_nets {debug_req[data][21]}]
set_property MARK_DEBUG false [get_nets {debug_req[data][23]}]
set_property MARK_DEBUG false [get_nets {debug_req[data][25]}]
set_property MARK_DEBUG false [get_nets {debug_req[data][27]}]
set_property MARK_DEBUG false [get_nets {debug_req[data][29]}]
set_property MARK_DEBUG false [get_nets {debug_req[data][31]}]
set_property MARK_DEBUG false [get_nets {debug_req[data][30]}]
set_property MARK_DEBUG false [get_nets {debug_req[data][28]}]
set_property MARK_DEBUG false [get_nets {debug_req[data][26]}]
set_property MARK_DEBUG false [get_nets {debug_req[data][24]}]
set_property MARK_DEBUG false [get_nets {debug_req[data][22]}]
set_property MARK_DEBUG false [get_nets {debug_req[data][20]}]
set_property MARK_DEBUG false [get_nets {debug_req[data][18]}]
set_property MARK_DEBUG false [get_nets {debug_req[data][16]}]
set_property MARK_DEBUG false [get_nets {debug_req[data][14]}]
set_property MARK_DEBUG false [get_nets {debug_req[data][12]}]
set_property MARK_DEBUG false [get_nets {debug_req[data][9]}]
set_property MARK_DEBUG false [get_nets {debug_req[data][10]}]
open_hw_manager
connect_hw_server
foreach TARGET [get_hw_targets] {
puts "###############################"
puts "# TARGET: $TARGET"
puts "###############################"
}
open_hw_manager
connect_hw_server
current_hw_target [get_hw_targets -filter {NAME!~"localhost:3121/xilinx_tcf/Digilent/<HS2's serial number>"}]
open_hw_target
set_property PROGRAM.FILE {cva6_fpga.runs/impl_1/cva6_zybo_z7_20.bit} [get_hw_devices xc7z020_1]
current_hw_device [get_hw_devices xc7z020_1]
refresh_hw_device -update_hw_probes false [lindex [get_hw_devices xc7z020_1] 0]
set_property PROBES.FILE {} [get_hw_devices xc7z020_1]
set_property FULL_PROBES.FILE {} [get_hw_devices xc7z020_1]
set_property PROGRAM.FILE {cva6_fpga.runs/impl_1/cva6_zybo_z7_20.bit} [get_hw_devices xc7z020_1]
program_hw_devices [get_hw_devices xc7z020_1]
refresh_hw_device [lindex [get_hw_devices xc7z020_1] 0]
connect -url tcp:127.0.0.1:3121
targets -set -nocase -filter {name =~"APU*"}
rst -system
after 3000
#targets -set -filter {jtag_cable_name =~ "Digilent Zybo Z7 210351AD67C0A" && level==0 && jtag_device_ctx=="jsn-Zybo Z7-210351AD67C0A-23727093-0"}
fpga -file cva6_fpga.runs/impl_1/cva6_zybo_z7_20.bit
#targets -set -nocase -filter {name =~"APU*"}
#loadhw -hw /home/sjacq/Work_dir/USE_CASE/2020/contest_softcore_cva6/migration2github/test/workspace/design_1_wrapper/export/design_1_wrapper/hw/design_1_wrapper.xsa -mem-ranges [list {0x40000000 0xbfffffff}] -regs
#configparams force-mem-access 1
targets -set -nocase -filter {name =~"APU*"}
source scripts/ps7_init.tcl
ps7_init
ps7_post_config
This diff is collapsed.
......@@ -43,6 +43,7 @@ set_msg_config -id {[Synth 8-4480]} -limit 1000
add_files -fileset constrs_1 -norecurse constraints/zybo_z7_20.xdc
read_ip xilinx/xlnx_processing_system7/ip/xlnx_processing_system7.xci
read_ip xilinx/xlnx_blk_mem_gen/ip/xlnx_blk_mem_gen.xci
read_ip xilinx/xlnx_axi_clock_converter/ip/xlnx_axi_clock_converter.xci
read_ip xilinx/xlnx_axi_dwidth_converter_dm_slave/ip/xlnx_axi_dwidth_converter_dm_slave.xci
......@@ -56,8 +57,16 @@ source scripts/add_sources.tcl
set_property top cva6_zybo_z7_20 [current_fileset]
read_verilog -sv {src/zybo-z7-20.svh ../src/common_cells/include/common_cells/registers.svh}
set file "src/zybo-z7-20.svh"
read_verilog -sv {src/zybo-z7-20.svh src/zybo-z7-20-ddr.svh ../src/common_cells/include/common_cells/registers.svh}
#set file "src/zybo-z7-20.svh"
if { $::env(PS7_DDR) == 1 } {
set file "src/zybo-z7-20-ddr.svh"
} elseif {$::env(BRAM) == 1} {
set file "src/zybo-z7-20.svh"
} else {
puts "None of the values is matching"
}
set registers "../src/common_cells/include/common_cells/registers.svh"
set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file" "$registers"]]
......@@ -67,8 +76,14 @@ update_compile_order -fileset sources_1
add_files -fileset constrs_1 -norecurse constraints/$project.xdc
synth_design -rtl -name rtl_1
# synth_design -verilog_define PS7_DDR=$::env(PS7_DDR) -verilog_define BRAM=$::env(BRAM) -rtl -name rtl_1
if { $::env(PS7_DDR) == 1 } {
synth_design -verilog_define PS7_DDR=PS7_DDR -rtl -name rtl_1
} elseif {$::env(BRAM) == 1} {
synth_design -verilog_define BRAM=BRAM -rtl -name rtl_1
} else {
puts "None of the values is matching"
}
set_property STEPS.SYNTH_DESIGN.ARGS.RETIMING true [get_runs synth_1]
......
......@@ -27,6 +27,32 @@ module cva6_zybo_z7_20 (
input logic clk_sys ,
input logic cpu_reset ,
`ifdef PS7_DDR
inout wire [14:0]DDR_addr,
inout wire [2:0]DDR_ba,
inout wire DDR_cas_n,
inout wire DDR_ck_n,
inout wire DDR_ck_p,
inout wire DDR_cke,
inout wire DDR_cs_n,
inout wire [3:0]DDR_dm,
inout wire [31:0]DDR_dq,
inout wire [3:0]DDR_dqs_n,
inout wire [3:0]DDR_dqs_p,
inout wire DDR_odt,
inout wire DDR_ras_n,
inout wire DDR_reset_n,
inout wire DDR_we_n,
inout wire ddr_vrn,
inout wire ddr_vrp,
inout wire [53:0]mio,
inout wire ps_clk,
inout wire ps_porb,
inout wire ps_srstb,
`endif
// common part
input logic trst_n ,
input logic tck ,
......@@ -34,7 +60,11 @@ module cva6_zybo_z7_20 (
input logic tdi ,
output wire tdo ,
input logic rx ,
output logic tx
output logic tx
);
// 24 MByte in 8 byte words
localparam NumWords = (24 * 1024 * 1024) / 8;
......@@ -716,6 +746,91 @@ logic [31 : 0] saxibram_araddr;
assign saxibram_awaddr = dram.aw_addr & 32'h7fff_ffff;
assign saxibram_araddr = dram.ar_addr & 32'h7fff_ffff;
`ifdef PS7_DDR
logic [5:0] S_AXI_HP0_BID;
logic [5:0] S_AXI_HP0_RID;
assign dram.b_id = S_AXI_HP0_BID[4:0];
assign dram.r_id = S_AXI_HP0_RID[4:0];
xlnx_processing_system7 i_xlnx_processing_system7(
//INTERNAL SIGNALS
.S_AXI_HP0_ARREADY (dram.ar_ready),//S_AXI_HP0_ARREADY : out STD_LOGIC;
.S_AXI_HP0_AWREADY (dram.aw_ready),//S_AXI_HP0_AWREADY : out STD_LOGIC;
.S_AXI_HP0_BVALID (dram.b_valid),//S_AXI_HP0_BVALID : out STD_LOGIC;
.S_AXI_HP0_RLAST (dram.r_last),//S_AXI_HP0_RLAST : out STD_LOGIC;
.S_AXI_HP0_RVALID (dram.r_valid),//S_AXI_HP0_RVALID : out STD_LOGIC;
.S_AXI_HP0_WREADY (dram.w_ready),//S_AXI_HP0_WREADY : out STD_LOGIC;
.S_AXI_HP0_BRESP (dram.b_resp),//S_AXI_HP0_BRESP : out STD_LOGIC_VECTOR ( 1 downto 0 );
.S_AXI_HP0_RRESP (dram.r_resp),//S_AXI_HP0_RRESP : out STD_LOGIC_VECTOR ( 1 downto 0 );
.S_AXI_HP0_BID (S_AXI_HP0_BID),//S_AXI_HP0_BID : out STD_LOGIC_VECTOR ( 5 downto 0 );
.S_AXI_HP0_RID (S_AXI_HP0_RID),//S_AXI_HP0_RID : out STD_LOGIC_VECTOR ( 5 downto 0 );
.S_AXI_HP0_RDATA (dram.r_data),//S_AXI_HP0_RDATA : out STD_LOGIC_VECTOR ( 63 downto 0 );
.S_AXI_HP0_RCOUNT (),//S_AXI_HP0_RCOUNT : out STD_LOGIC_VECTOR ( 7 downto 0 );
.S_AXI_HP0_WCOUNT (),//S_AXI_HP0_WCOUNT : out STD_LOGIC_VECTOR ( 7 downto 0 );
.S_AXI_HP0_RACOUNT (),//S_AXI_HP0_RACOUNT : out STD_LOGIC_VECTOR ( 2 downto 0 );
.S_AXI_HP0_WACOUNT (),//S_AXI_HP0_WACOUNT : out STD_LOGIC_VECTOR ( 5 downto 0 );
.S_AXI_HP0_ACLK (clk),//S_AXI_HP0_ACLK : in STD_LOGIC;
.S_AXI_HP0_ARVALID (dram.ar_valid),//S_AXI_HP0_ARVALID : in STD_LOGIC;
.S_AXI_HP0_AWVALID (dram.aw_valid),//S_AXI_HP0_AWVALID : in STD_LOGIC;
.S_AXI_HP0_BREADY (dram.b_ready),//S_AXI_HP0_BREADY : in STD_LOGIC;
.S_AXI_HP0_RDISSUECAP1_EN (1'b0),//S_AXI_HP0_RDISSUECAP1_EN : in STD_LOGIC;
.S_AXI_HP0_RREADY (dram.r_ready),//S_AXI_HP0_RREADY S_AXI_HP0_RREADY : in STD_LOGIC;
.S_AXI_HP0_WLAST (dram.w_last),//S_AXI_HP0_WLAST : in STD_LOGIC;
.S_AXI_HP0_WRISSUECAP1_EN (1'b0),//S_AXI_HP0_WRISSUECAP1_EN : in STD_LOGIC;
.S_AXI_HP0_WVALID (dram.w_valid),//S_AXI_HP0_WVALID : in STD_LOGIC;
.S_AXI_HP0_ARBURST (dram.ar_burst),//S_AXI_HP0_ARBURST : in STD_LOGIC_VECTOR ( 1 downto 0 );
.S_AXI_HP0_ARLOCK ({1'b0,dram.ar_lock}),//S_AXI_HP0_ARLOCK : in STD_LOGIC_VECTOR ( 1 downto 0 );
.S_AXI_HP0_ARSIZE (dram.ar_size),//S_AXI_HP0_ARSIZE : in STD_LOGIC_VECTOR ( 2 downto 0 );
.S_AXI_HP0_AWBURST (dram.aw_burst),//S_AXI_HP0_AWBURST : in STD_LOGIC_VECTOR ( 1 downto 0 );
.S_AXI_HP0_AWLOCK ({1'b0,dram.aw_lock}),//S_AXI_HP0_AWLOCK : in STD_LOGIC_VECTOR ( 1 downto 0 );
.S_AXI_HP0_AWSIZE (dram.aw_size),//S_AXI_HP0_AWSIZE : in STD_LOGIC_VECTOR ( 2 downto 0 );
.S_AXI_HP0_ARPROT (dram.ar_prot),//S_AXI_HP0_ARPROT : in STD_LOGIC_VECTOR ( 2 downto 0 );
.S_AXI_HP0_AWPROT (dram.aw_prot),//S_AXI_HP0_AWPROT : in STD_LOGIC_VECTOR ( 2 downto 0 );
.S_AXI_HP0_ARADDR (saxibram_araddr),//S_AXI_HP0_ARADDR : in STD_LOGIC_VECTOR ( 31 downto 0 );
.S_AXI_HP0_AWADDR (saxibram_awaddr),//S_AXI_HP0_AWADDR : in STD_LOGIC_VECTOR ( 31 downto 0 );
.S_AXI_HP0_ARCACHE (dram.ar_cache),//S_AXI_HP0_ARCACHE : in STD_LOGIC_VECTOR ( 3 downto 0 );
.S_AXI_HP0_ARLEN (dram.ar_len),//S_AXI_HP0_ARLEN : in STD_LOGIC_VECTOR ( 3 downto 0 );
.S_AXI_HP0_ARQOS (dram.ar_qos),//S_AXI_HP0_ARQOS : in STD_LOGIC_VECTOR ( 3 downto 0 );
.S_AXI_HP0_AWCACHE (dram.aw_cache),//S_AXI_HP0_AWCACHE : in STD_LOGIC_VECTOR ( 3 downto 0 );
.S_AXI_HP0_AWLEN (dram.aw_len),//S_AXI_HP0_AWLEN : in STD_LOGIC_VECTOR ( 3 downto 0 );
.S_AXI_HP0_AWQOS (dram.aw_qos),//S_AXI_HP0_AWQOS : in STD_LOGIC_VECTOR ( 3 downto 0 );
.S_AXI_HP0_ARID ({1'b0,dram.ar_id}),//S_AXI_HP0_ARID : in STD_LOGIC_VECTOR ( 5 downto 0 );
.S_AXI_HP0_AWID ({1'b0,dram.aw_id}),//S_AXI_HP0_AWID : in STD_LOGIC_VECTOR ( 5 downto 0 );
.S_AXI_HP0_WID ({1'b0,dram.aw_id}),//S_AXI_HP0_WID : in STD_LOGIC_VECTOR ( 5 downto 0 );
.S_AXI_HP0_WDATA (dram.w_data),//S_AXI_HP0_WDATA : in STD_LOGIC_VECTOR ( 63 downto 0 );
.S_AXI_HP0_WSTRB (dram.w_strb),//S_AXI_HP0_WSTRB : in STD_LOGIC_VECTOR ( 7 downto 0 );
//FPGA EXTERNAL PORT
.MIO (mio),//MIO : inout STD_LOGIC_VECTOR ( 53 downto 0 );
.DDR_Addr(DDR_addr[14:0]),//DDR_Addr : inout STD_LOGIC_VECTOR ( 14 downto 0 );
.DDR_BankAddr(DDR_ba[2:0]),//DDR_BankAddr : inout STD_LOGIC_VECTOR ( 2 downto 0 );
.DDR_CAS_n(DDR_cas_n),//DDR_CAS_n : inout STD_LOGIC;
.DDR_CKE(DDR_cke),//DDR_CKE : inout STD_LOGIC;
.DDR_CS_n(DDR_cs_n),//DDR_CS_n : inout STD_LOGIC;
.DDR_Clk(DDR_ck_p),//DDR_Clk : inout STD_LOGIC;
.DDR_Clk_n(DDR_ck_n),//DDR_Clk_n : inout STD_LOGIC;
.DDR_DM(DDR_dm[3:0]),//DDR_DM : inout STD_LOGIC_VECTOR ( 3 downto 0 );
.DDR_DQ(DDR_dq[31:0]),//DDR_DQ : inout STD_LOGIC_VECTOR ( 31 downto 0 );
.DDR_DQS(DDR_dqs_p[3:0]),//DDR_DQS : inout STD_LOGIC_VECTOR ( 3 downto 0 );
.DDR_DQS_n(DDR_dqs_n[3:0]),//DDR_DQS_n : inout STD_LOGIC_VECTOR ( 3 downto 0 );
.DDR_DRSTB(DDR_reset_n),//DDR_DRSTB : inout STD_LOGIC;
.DDR_ODT(DDR_odt),//DDR_ODT : inout STD_LOGIC;
.DDR_RAS_n(DDR_ras_n),//DDR_RAS_n : inout STD_LOGIC;
.DDR_VRN(ddr_vrn),//DDR_VRN : inout STD_LOGIC;
.DDR_VRP(ddr_vrp),//DDR_VRP : inout STD_LOGIC;
.DDR_WEB(DDR_we_n),//DDR_WEB : inout STD_LOGIC;
.PS_CLK(ps_clk),
.PS_PORB(ps_porb),
.PS_SRSTB(ps_srstb)
);
`elsif BRAM
xlnx_blk_mem_gen i_xlnx_blk_mem_gen (
.rsta_busy ( ),
......@@ -753,5 +868,7 @@ xlnx_blk_mem_gen i_xlnx_blk_mem_gen (
.s_axi_rready ( dram.r_ready )
);
`endif
endmodule
`define ARIANE_DATA_WIDTH 64
// Instantiate protocl checker
// `define PROTOCOL_CHECKER
// write-back cache
// `define WB_DCACHE
// write-through cache
`define WT_DCACHE
// debug probe
//`define LAUTERBACH_DEBUG_PROBE
// to use DDR connecting to Zynq PS
`define PS7_DDR
......@@ -11,4 +11,7 @@
`define WT_DCACHE
// debug probe
//`define LAUTERBACH_DEBUG_PROBE
`define LAUTERBACH_DEBUG_PROBE
// to use BRAM in FPGA fabric
`define BRAM
PROJECT:=xlnx_processing_system7
include ../common.mk
set partNumber $::env(XILINX_PART)
set boardName $::env(XILINX_BOARD)
set ipName xlnx_processing_system7
create_project $ipName . -force -part $partNumber
set_property board_part $boardName [current_project]
create_ip -name processing_system7 -vendor xilinx.com -library ip -module_name $ipName
set_property -dict [list CONFIG.PCW_ACT_APU_PERIPHERAL_FREQMHZ {666.666687} \
CONFIG.PCW_ACT_CAN_PERIPHERAL_FREQMHZ {10.000000} \
CONFIG.PCW_ACT_DCI_PERIPHERAL_FREQMHZ {10.158730} \
CONFIG.PCW_ACT_ENET0_PERIPHERAL_FREQMHZ {10.000000} \
CONFIG.PCW_ACT_ENET1_PERIPHERAL_FREQMHZ {10.000000} \
CONFIG.PCW_ACT_FPGA0_PERIPHERAL_FREQMHZ {10.000000} \
CONFIG.PCW_ACT_FPGA1_PERIPHERAL_FREQMHZ {10.000000} \
CONFIG.PCW_ACT_FPGA2_PERIPHERAL_FREQMHZ {10.000000} \
CONFIG.PCW_ACT_FPGA3_PERIPHERAL_FREQMHZ {10.000000} \
CONFIG.PCW_ACT_PCAP_PERIPHERAL_FREQMHZ {200.000000} \
CONFIG.PCW_ACT_QSPI_PERIPHERAL_FREQMHZ {10.000000} \
CONFIG.PCW_ACT_SDIO_PERIPHERAL_FREQMHZ {10.000000} \
CONFIG.PCW_ACT_SMC_PERIPHERAL_FREQMHZ {10.000000} \
CONFIG.PCW_ACT_SPI_PERIPHERAL_FREQMHZ {10.000000} \
CONFIG.PCW_ACT_TPIU_PERIPHERAL_FREQMHZ {200.000000} \
CONFIG.PCW_ACT_TTC0_CLK0_PERIPHERAL_FREQMHZ {111.111115} \
CONFIG.PCW_ACT_TTC0_CLK1_PERIPHERAL_FREQMHZ {111.111115} \
CONFIG.PCW_ACT_TTC0_CLK2_PERIPHERAL_FREQMHZ {111.111115} \
CONFIG.PCW_ACT_TTC1_CLK0_PERIPHERAL_FREQMHZ {111.111115} \
CONFIG.PCW_ACT_TTC1_CLK1_PERIPHERAL_FREQMHZ {111.111115} \
CONFIG.PCW_ACT_TTC1_CLK2_PERIPHERAL_FREQMHZ {111.111115} \
CONFIG.PCW_ACT_UART_PERIPHERAL_FREQMHZ {10.000000} \
CONFIG.PCW_ACT_WDT_PERIPHERAL_FREQMHZ {111.111115} \
CONFIG.PCW_ARMPLL_CTRL_FBDIV {40} \
CONFIG.PCW_CAN_PERIPHERAL_DIVISOR0 {1} \
CONFIG.PCW_CAN_PERIPHERAL_DIVISOR1 {1} \
CONFIG.PCW_CLK0_FREQ {10000000} \
CONFIG.PCW_CLK1_FREQ {10000000} \
CONFIG.PCW_CLK2_FREQ {10000000} \
CONFIG.PCW_CLK3_FREQ {10000000} \
CONFIG.PCW_CPU_CPU_PLL_FREQMHZ {1333.333} \
CONFIG.PCW_CPU_PERIPHERAL_DIVISOR0 {2} \
CONFIG.PCW_DCI_PERIPHERAL_DIVISOR0 {15} \
CONFIG.PCW_DCI_PERIPHERAL_DIVISOR1 {7} \
CONFIG.PCW_DDRPLL_CTRL_FBDIV {32} \
CONFIG.PCW_DDR_DDR_PLL_FREQMHZ {1066.667} \
CONFIG.PCW_DDR_PERIPHERAL_DIVISOR0 {2} \
CONFIG.PCW_DDR_RAM_HIGHADDR {0x3FFFFFFF} \
CONFIG.PCW_ENET0_PERIPHERAL_DIVISOR0 {1} \
CONFIG.PCW_ENET0_PERIPHERAL_DIVISOR1 {1} \
CONFIG.PCW_ENET1_PERIPHERAL_DIVISOR0 {1} \
CONFIG.PCW_ENET1_PERIPHERAL_DIVISOR1 {1} \
CONFIG.PCW_EN_CLK0_PORT {0} \
CONFIG.PCW_EN_RST0_PORT {0} \
CONFIG.PCW_FCLK0_PERIPHERAL_DIVISOR0 {1} \
CONFIG.PCW_FCLK0_PERIPHERAL_DIVISOR1 {1} \
CONFIG.PCW_FCLK1_PERIPHERAL_DIVISOR0 {1} \
CONFIG.PCW_FCLK1_PERIPHERAL_DIVISOR1 {1} \
CONFIG.PCW_FCLK2_PERIPHERAL_DIVISOR0 {1} \
CONFIG.PCW_FCLK2_PERIPHERAL_DIVISOR1 {1} \
CONFIG.PCW_FCLK3_PERIPHERAL_DIVISOR0 {1} \
CONFIG.PCW_FCLK3_PERIPHERAL_DIVISOR1 {1} \
CONFIG.PCW_FCLK_CLK0_BUF {FALSE} \
CONFIG.PCW_FPGA_FCLK0_ENABLE {0} \
CONFIG.PCW_FPGA_FCLK1_ENABLE {0} \
CONFIG.PCW_FPGA_FCLK2_ENABLE {0} \
CONFIG.PCW_FPGA_FCLK3_ENABLE {0} \
CONFIG.PCW_I2C_PERIPHERAL_FREQMHZ {25} \
CONFIG.PCW_IOPLL_CTRL_FBDIV {48} \
CONFIG.PCW_IO_IO_PLL_FREQMHZ {1600.000} \
CONFIG.PCW_PCAP_PERIPHERAL_DIVISOR0 {8} \
CONFIG.PCW_QSPI_PERIPHERAL_DIVISOR0 {1} \
CONFIG.PCW_SDIO_PERIPHERAL_DIVISOR0 {1} \
CONFIG.PCW_SMC_PERIPHERAL_DIVISOR0 {1} \
CONFIG.PCW_SPI_PERIPHERAL_DIVISOR0 {1} \
CONFIG.PCW_TPIU_PERIPHERAL_DIVISOR0 {1} \
CONFIG.PCW_UART_PERIPHERAL_DIVISOR0 {1} \
CONFIG.PCW_UIPARAM_ACT_DDR_FREQ_MHZ {533.333374} \
CONFIG.PCW_UIPARAM_DDR_BANK_ADDR_COUNT {3} \
CONFIG.PCW_UIPARAM_DDR_BL {8} \
CONFIG.PCW_UIPARAM_DDR_BOARD_DELAY0 {0.221} \
CONFIG.PCW_UIPARAM_DDR_BOARD_DELAY1 {0.222} \
CONFIG.PCW_UIPARAM_DDR_BOARD_DELAY2 {0.217} \
CONFIG.PCW_UIPARAM_DDR_BOARD_DELAY3 {0.244} \
CONFIG.PCW_UIPARAM_DDR_CL {7} \
CONFIG.PCW_UIPARAM_DDR_COL_ADDR_COUNT {10} \
CONFIG.PCW_UIPARAM_DDR_CWL {6} \
CONFIG.PCW_UIPARAM_DDR_DEVICE_CAPACITY {4096 MBits} \
CONFIG.PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_0 {-0.05} \
CONFIG.PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_1 {-0.044} \
CONFIG.PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_2 {-0.035} \
CONFIG.PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_3 {-0.100} \
CONFIG.PCW_UIPARAM_DDR_DRAM_WIDTH {16 Bits} \
CONFIG.PCW_UIPARAM_DDR_MEMORY_TYPE {DDR 3 (Low Voltage)} \
CONFIG.PCW_UIPARAM_DDR_PARTNO {MT41K256M16 RE-125} \
CONFIG.PCW_UIPARAM_DDR_ROW_ADDR_COUNT {15} \
CONFIG.PCW_UIPARAM_DDR_SPEED_BIN {DDR3_1066F} \
CONFIG.PCW_UIPARAM_DDR_T_FAW {40.0} \
CONFIG.PCW_UIPARAM_DDR_T_RAS_MIN {35.0} \
CONFIG.PCW_UIPARAM_DDR_T_RC {48.75} \
CONFIG.PCW_UIPARAM_DDR_T_RCD {7} \
CONFIG.PCW_UIPARAM_DDR_T_RP {7} \
CONFIG.PCW_USE_M_AXI_GP0 {0} \
CONFIG.PCW_USE_S_AXI_HP0 {1} \
] [get_ips $ipName]
generate_target {instantiation_template} [get_files ./$ipName.srcs/sources_1/ip/$ipName/$ipName.xci]
generate_target all [get_files ./$ipName.srcs/sources_1/ip/$ipName/$ipName.xci]
create_ip_run [get_files -of_objects [get_fileset sources_1] ./$ipName.srcs/sources_1/ip/$ipName/$ipName.xci]
launch_run -jobs 8 ${ipName}_synth_1
wait_on_run ${ipName}_synth_1
Supports Markdown
0% or .
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment