Merge branch 'master' of https://github.com/sjthales/cva6

README.md

@@ -36,15 +36,16 @@ $ make newlib
 When the installation is achieved, do not forget to add $RISCV/bin to your PATH.
 
 ## Questa tool
-Questa sim **version 10.7** has been used for simulations.
+Questa Prime **version 10.7** has been used for simulations.
 
 ## Vitis/Vivado setting up
+This section will be completed in a next release (the so-called "2<sup>nd</sup> kit" planned early December 2020).
 For the contest, CVA6 processor will be implemented on Zybo 7-20 board from Digilent. This board consists of Zynq 7 FPGA from Xilinx. 
 To do so, **Vitis 2020.1** environment from Xilinx need to be installed.
 
 Furthermore, Digilent provides board files for each development board.
 
-This files ease the creating of new projects with automated configuration of several complicated components such as Zynq Processing System and memory interfaces.
+This files ease the creation of new projects with automated configuration of several complicated components such as Zynq Processing System and memory interfaces.
 
 All guidelines to install **vitis 2020.1** and **Zybo 7-20** board files are explained to the following link:
 https://reference.digilentinc.com/reference/programmable-logic/guides/installation
@@ -86,7 +87,7 @@ In the first time, synthesis and place and route are carried in out of context m
 
 That allows to have an estimation of the logical resources used by the CVA6 in the FPGA fabric as well as the maximal frequency of CVA6 architecture.
 
-These both metrics are majors for a computation architecture.
+They are both major metrics for a computation architecture.
 
 Command to run for synthesis and place and route in out of context mode:
 ```

sw/bsp/config/link.ld

@@ -9,16 +9,16 @@
 /* This linker script is adapted from the default linker script for upstream
    RISC-V GCC.  It has been modified for use in verification of CORE-V cores.
 */
-// Additional contributions by:
-//         Sebastien Jacq - sjthales on github.com
-//
-// Description: linkerscript for the CV32A6 platform
-//
-// =========================================================================== //
-// Revisions  :
-// Date        Version  Author       Description
-// 2020-10-06  0.1      S.Jacq       modification of the Test for CV32A6 softcore
-// =========================================================================== //
+/* Additional contributions by:
+           Sebastien Jacq - sjthales on github.com
+
+   Description: linkerscript for the CV32A6 platform
+
+   =========================================================================== 
+   Revisions  :
+   Date        Version  Author       Description
+   2020-10-06  0.1      S.Jacq       modification of the Test for CV32A6 softcore
+   =========================================================================== */
 
 OUTPUT_FORMAT("elf32-littleriscv", "elf32-littleriscv",
 	      "elf32-littleriscv")