verifier: lock I$ on D$ writes

Signed-off-by: Alban Gruin <alban.gruin@irit.fr>

src/ariane.sv

@@ -103,6 +103,8 @@ module ariane import ariane_pkg::*; #(
   logic                     has_mem_access_is_verif;
   logic                     has_ctrl_flow_is_icache;
 
+  logic                     store_buffer_empty_verif;
+
   // --------------
   // ISSUE <-> EX
   // --------------
@@ -445,6 +447,7 @@ module ariane import ariane_pkg::*; #(
     .lsu_commit_ready_o     ( lsu_commit_ready_ex_commit  ), // to commit
     .commit_tran_id_i       ( lsu_commit_trans_id         ), // from commit
     .no_st_pending_o        ( no_st_pending_ex            ),
+    .store_buffer_empty_o   ( store_buffer_empty_verif    ),
     // FPU
     .fpu_ready_o            ( fpu_ready_ex_id             ),
     .fpu_valid_i            ( fpu_valid_id_ex             ),
@@ -664,6 +667,9 @@ module ariane import ariane_pkg::*; #(
     // I$
     .icache_miss_i (icache_miss_cache_perf),
 
+    // D$
+    .dcache_wbuffer_empty_i (dcache_commit_wbuffer_empty),
+
     // IF
     .if_has_mem_access_i (has_mem_access_if_verif),
     .if_has_cf_i         (has_ctrl_flow_if_icache),
@@ -677,7 +683,7 @@ module ariane import ariane_pkg::*; #(
     .is_has_cf_i         (has_ctrl_flow_is_icache),
 
     // LSU
-    .no_st_pending_commit_i (no_st_pending_ex),
+    .no_st_pending_commit_i (store_buffer_empty_verif),
 
     // CO
     .commit_instr_i (commit_instr_id_commit),

src/ex_stage.sv

@@ -71,6 +71,7 @@ module ex_stage import ariane_pkg::*; #(
     output logic                                   lsu_commit_ready_o, // commit queue is ready to accept another commit request
     input  logic [TRANS_ID_BITS-1:0]               commit_tran_id_i,
     output logic                                   no_st_pending_o,
+    output logic                                   store_buffer_empty_o,
     input  logic                                   amo_valid_commit_i,
     // FPU
     output logic                                   fpu_ready_o,      // FU is ready
@@ -277,6 +278,7 @@ module ex_stage import ariane_pkg::*; #(
         .rst_ni,
         .flush_i,
         .no_st_pending_o,
+        .store_buffer_empty_o,
         .fu_data_i             ( lsu_data ),
         .lsu_ready_o,
         .lsu_valid_i,

src/load_store_unit.sv

@@ -21,6 +21,7 @@ module load_store_unit import ariane_pkg::*; #(
     input  logic                     rst_ni,
     input  logic                     flush_i,
     output logic                     no_st_pending_o,
+    output logic                     store_buffer_empty_o,
     input  logic                     amo_valid_commit_i,
 
     input  fu_data_t                 fu_data_i,
@@ -196,9 +197,9 @@ module load_store_unit import ariane_pkg::*; #(
         end
     endgenerate
 
-
-   
     logic store_buffer_empty;
+    assign store_buffer_empty_o = store_buffer_empty;
+
     // ------------------
     // Store Unit
     // ------------------

src/verifier.sv

@@ -9,6 +9,9 @@ module verifier #(
   // I$
   input logic                       icache_miss_i,
 
+  // D$
+  input logic                       dcache_wbuffer_empty_i,
+
   // Frontend
   input logic                       if_has_mem_access_i,
   input logic                       if_has_cf_i,
@@ -35,7 +38,7 @@ module verifier #(
 
   // Bus accesses (I$ misses and memory instructions in the pipeline)
   logic                             has_mem_access;
-  assign has_mem_access = if_has_mem_access_i | id_has_mem_access_i | is_has_mem_access_i | (~no_st_pending_commit_i);
+  assign has_mem_access = if_has_mem_access_i | id_has_mem_access_i | is_has_mem_access_i | ~no_st_pending_commit_i | ~dcache_wbuffer_empty_i;
 
   // assign should_lock_icache_o = has_mem_access & icache_miss_i;
   assign should_lock_icache_o = has_mem_access | if_has_cf_i | id_has_cf_i | is_has_cf_i;