Skip to content
GitLab
Explore
Sign in
Primary navigation
Search or go to…
Project
M
MINOTAuR
Manage
Activity
Members
Labels
Plan
Issues
Issue boards
Milestones
Wiki
Code
Merge requests
Repository
Branches
Commits
Tags
Repository graph
Compare revisions
Snippets
Build
Pipelines
Jobs
Pipeline schedules
Artifacts
Deploy
Releases
Package registry
Model registry
Operate
Environments
Terraform modules
Monitor
Incidents
Analyze
Value stream analytics
Contributor analytics
CI/CD analytics
Repository analytics
Model experiments
Help
Help
Support
GitLab documentation
Compare GitLab plans
Community forum
Contribute to GitLab
Provide feedback
Keyboard shortcuts
?
Snippets
Groups
Projects
Show more breadcrumbs
MINOTAuR
MINOTAuR
Commits
3b3f217b
Commit
3b3f217b
authored
4 years ago
by
Alban Gruin
Browse files
Options
Downloads
Patches
Plain Diff
frontend: disable branch prediction, mkII
Signed-off-by:
Alban Gruin
<
alban.gruin@irit.fr
>
parent
82d5abd9
Branches
Branches containing commit
No related tags found
No related merge requests found
Changes
1
Hide whitespace changes
Inline
Side-by-side
Showing
1 changed file
src/frontend/frontend.sv
+20
-3
20 additions, 3 deletions
src/frontend/frontend.sv
with
20 additions
and
3 deletions
src/frontend/frontend.sv
+
20
−
3
View file @
3b3f217b
...
@@ -89,7 +89,9 @@ module frontend import ariane_pkg::*; #(
...
@@ -89,7 +89,9 @@ module frontend import ariane_pkg::*; #(
// re-aligned instruction and address (coming from cache - combinationally)
// re-aligned instruction and address (coming from cache - combinationally)
logic
[
INSTR_PER_FETCH
-
1
:
0
][
31
:
0
]
instr
;
logic
[
INSTR_PER_FETCH
-
1
:
0
][
31
:
0
]
instr
;
logic
[
INSTR_PER_FETCH
-
1
:
0
][
riscv
::
VLEN
-
1
:
0
]
addr
;
logic
[
INSTR_PER_FETCH
-
1
:
0
][
riscv
::
VLEN
-
1
:
0
]
addr
;
logic
[
INSTR_PER_FETCH
-
1
:
0
]
instruction_valid
;
logic
[
INSTR_PER_FETCH
-
1
:
0
]
instruction_valid
,
instruction_really_valid
;
logic
[
INSTR_PER_FETCH
-
1
:
0
]
instr_really_valid
;
// BHT, BTB and RAS prediction
// BHT, BTB and RAS prediction
bht_prediction_t
[
INSTR_PER_FETCH
-
1
:
0
]
bht_prediction
;
bht_prediction_t
[
INSTR_PER_FETCH
-
1
:
0
]
bht_prediction
;
btb_prediction_t
[
INSTR_PER_FETCH
-
1
:
0
]
btb_prediction
;
btb_prediction_t
[
INSTR_PER_FETCH
-
1
:
0
]
btb_prediction
;
...
@@ -239,13 +241,28 @@ module frontend import ariane_pkg::*; #(
...
@@ -239,13 +241,28 @@ module frontend import ariane_pkg::*; #(
end
end
end
end
end
end
logic
has_speculative
;
// or reduce struct
// or reduce struct
always_comb
begin
always_comb
begin
bp_valid
=
1'b0
;
bp_valid
=
1'b0
;
has_speculative
=
1'b0
;
instruction_really_valid
=
'0
;
// BP cannot be valid if we have a return instruction and the RAS is not giving a valid address
// BP cannot be valid if we have a return instruction and the RAS is not giving a valid address
// Check that we encountered a control flow and that for a return the RAS
// Check that we encountered a control flow and that for a return the RAS
// contains a valid prediction.
// contains a valid prediction.
for
(
int
i
=
0
;
i
<
INSTR_PER_FETCH
;
i
++
)
bp_valid
|=
((
cf_type
[
i
]
!=
NoCF
&
cf_type
[
i
]
!=
Return
)
|
((
cf_type
[
i
]
==
Return
)
&
ras_predict
.
valid
));
for
(
int
unsigned
i
=
0
;
i
<
INSTR_PER_FETCH
;
i
++
)
begin
bp_valid
|=
((
cf_type
[
i
]
!=
NoCF
&
cf_type
[
i
]
!=
Return
)
|
((
cf_type
[
i
]
==
Return
)
&
ras_predict
.
valid
));
has_speculative
|=
(
!
(
cf_type
[
i
]
inside
{
NoCF
,
Return
,
Jump
}
)
|
((
cf_type
[
i
]
==
Return
)
&
ras_predict
.
valid
));
if
(
enable_bp_i
)
begin
instruction_really_valid
[
i
]
=
instruction_valid
[
i
];
end
else
begin
instruction_really_valid
[
i
]
=
instruction_really_valid
[
i
]
&&
!
(
has_speculative
);
end
end
end
end
assign
is_mispredict
=
resolved_branch_i
.
valid
&
resolved_branch_i
.
is_mispredict
;
assign
is_mispredict
=
resolved_branch_i
.
valid
&
resolved_branch_i
.
is_mispredict
;
...
@@ -434,7 +451,7 @@ module frontend import ariane_pkg::*; #(
...
@@ -434,7 +451,7 @@ module frontend import ariane_pkg::*; #(
.
exception_addr_i
(
icache_vaddr_q
),
.
exception_addr_i
(
icache_vaddr_q
),
.
predict_address_i
(
predict_address
),
.
predict_address_i
(
predict_address
),
.
cf_type_i
(
cf_type
),
.
cf_type_i
(
cf_type
),
.
valid_i
(
instruction_valid
),
// from re-aligner
.
valid_i
(
instruction_
really_
valid
),
// from re-aligner
.
consumed_o
(
instr_queue_consumed
),
.
consumed_o
(
instr_queue_consumed
),
.
ready_o
(
instr_queue_ready
),
.
ready_o
(
instr_queue_ready
),
.
replay_o
(
replay
),
.
replay_o
(
replay
),
...
...
This diff is collapsed.
Click to expand it.
Preview
0%
Loading
Try again
or
attach a new file
.
Cancel
You are about to add
0
people
to the discussion. Proceed with caution.
Finish editing this message first!
Save comment
Cancel
Please
register
or
sign in
to comment