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Commit 3e76ea25 authored by sjthales's avatar sjthales
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updating README, top module,top module testbench on Zybo z7-20 board

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README.md
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......@@ -222,7 +222,7 @@ $ make cva6_ooc CLK_PERIOD_NS=20 BATCH_MODE=0
This command generates synthesis and place and route reports in **fpga/reports_cva6_ooc_synth** and **fpga/reports_cva6_ooc_impl**.
# FPGA emulation
# FPGA platform
A FPGA platform emulating **CV32A6** (CVA6 in 32b flavor) has been implemented on **Zybo Z7-20** board.
......@@ -234,7 +234,7 @@ Below is described steps to run Coremark application on CV32A6 FPGA platform, st
1. First, make sure the digilent **JTAG-HS2 debug adapter** is properly connected to the **PMOD JE** connector and that the USBAUART adapter is properly connected to the **PMOD JB** connector of the Zybo Z7-20 board.
![alt text](https://github.com/sjthales/cva6-softcore-contest/blob/master/docs/pictures/20201204_150708.jpg)
2. compile coremark application in `sw/app`
2. Compile coremark application in `sw/app`
3. Generate the bitstream of the FPGA platform:
```
$ make cva6_fpga
......@@ -243,14 +243,14 @@ $ make cva6_fpga
```
$ make program_cva6_fpga
```
When is loaded led `done` is lighting.
When bitstream is loaded green led `done` is lighting.
![alt text](https://github.com/sjthales/cva6-softcore-contest/blob/master/docs/pictures/20201204_160542.jpg)
5. then, in a terminal, launch **OpenOCD**:
5. Then, in a terminal, launch **OpenOCD**:
```
$ openocd -f fpga/openocd_digilent_hs2.cfg
```
If it is succesful, you should see something like that:
If it is succesful, you should see:
```
Open On-Chip Debugger 0.10.0+dev-00832-gaec5cca (2019-12-10-14:21)
Licensed under GNU GPL v2
......@@ -292,15 +292,15 @@ Type "apropos word" to search for commands related to "word"...
Reading symbols from sw/app/coremark.riscv...
(gdb)
```
7. In gdb, you need to connect gdb to openocd:
7. In **gdb**, you need to connect gdb to openocd:
```
(gdb) target remote :3333
```
if it is successful, you should see the gdb connection in openocd:
if it is successful, you should see the gdb connection in **openocd**:
```
Info : accepting 'gdb' connection on tcp/3333
```
8. In gdb, load **coremark.riscv** to CV32A6 FPGA platform:
8. In **gdb**, load **coremark.riscv** to CV32A6 FPGA platform by command **load**:
```
(gdb) load
Loading section .vectors, size 0x80 lma 0x80000000
......@@ -315,7 +315,7 @@ Start address 0x80000080, load size 110712
Transfer rate: 63 KB/sec, 7908 bytes/write.
```
9. At last, in gdb, you can run the coremark application by command `c`:
9. At last, in **gdb**, you can run the coremark application by command `c`:
```
(gdb) c
Continuing.
......
fpga/src/cva6_zybo_z7_20.sv
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tb/tb_cva6_zybo_z7_20.sv
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// Copyright (c) 2020 Thales.
// Copyright and related rights are licensed under the Solderpad Hardware
// License, Version 0.51 (the "License"); you may not use this file except in
// compliance with the License. You may obtain a copy of the License at
// http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law
// or agreed to in writing, software, hardware and materials distributed under
// this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR
// CONDITIONS OF ANY KIND, either express or implied. See the License for the
// specific language governing permissions and limitations under the License.
//
// Author: Sebastien Jacq Thales Research & Technology
// Date: 07/12/2020
//
// Additional contributions by:
// Sebastien Jacq - sjthales on github.com
//
// Description: Zybo z7-20 FPGA platform level testbench module.
//
// =========================================================================== //
// Revisions :
// Date Version Author Description
// 2020-12-07 0.1 S.Jacq Testbench to test Zybo z7-20 FPGA platform
// =========================================================================== //
`timescale 1ns/1ps
import ariane_pkg::*;
//import uvm_pkg::*;
import jtag_pkg::*;
//import pulp_tap_pkg::*;
//`include "uvm_macros.svh"
//`define MAIN_MEM(P) dut.i_sram.genblk1[0].i_ram.Mem_DP[(``P``)]
//import "DPI-C" function read_elf(input string filename);
//import "DPI-C" function byte get_section(output longint address, output longint len);
//import "DPI-C" context function byte read_section(input longint address, inout byte buffer[]);
`define EXIT_SUCCESS 0
......@@ -88,19 +103,19 @@ int exit_status = `EXIT_ERROR;
cva6_zybo_z7_20 DUT(
.clk_sys(clk_i),
.cpu_reset (rst_i), //input logic cpu_reset ,
.cpu_reset (rst_i),
// jtag
.trst_n (jtag_TRSTn), //input logic trst_n ,
.tck (jtag_TCK), //input logic tck ,
.tms (jtag_TMS), //input logic tms ,
.tdi (jtag_TDI), //input logic tdi ,
.tdo (jtag_TDO_data),//output wire tdo ,
.trst_n (jtag_TRSTn),
.tck (jtag_TCK),
.tms (jtag_TMS),
.tdi (jtag_TDI),
.tdo (jtag_TDO_data),
//uart
.rx (rx), //input logic rx ,
.tx (tx) //output logic tx
.rx (rx),
.tx (tx)
);
......@@ -146,7 +161,6 @@ uart_bus
automatic logic [9:0] FC_CORE_ID = {5'd0,5'd0};
$display("[TB] %t - Asserting hard reset", $realtime);
//rst_ni = 1'b0;
rst_i = 1'b1;
#200ns
......@@ -181,14 +195,14 @@ uart_bus
debug_mode_if.set_hartsel(FC_CORE_ID, s_tck, s_tms, s_trstn, s_tdi, s_tdo);
$display("[TB] %t - Halting the Core", $realtime);
debug_mode_if.halt_harts(s_tck, s_tms, s_trstn, s_tdi, s_tdo);
$display("[TB] %t - Halting the Core", $realtime);
debug_mode_if.halt_harts(s_tck, s_tms, s_trstn, s_tdi, s_tdo);
$display("[TB] %t - reading gpr 0x1000 ", $realtime);
debug_mode_if.read_reg_abstract_cmd(16'h1000, gpr, s_tck, s_tms, s_trstn, s_tdi, s_tdo);
$display("[TB] %t - reading gpr 0x1000 ", $realtime);
debug_mode_if.read_reg_abstract_cmd(16'h1000, gpr, s_tck, s_tms, s_trstn, s_tdi, s_tdo);
$display("[TB] %t - reading gpr 0x1001 ", $realtime);
debug_mode_if.read_reg_abstract_cmd(16'h1001, gpr, s_tck, s_tms, s_trstn, s_tdi, s_tdo);
$display("[TB] %t - reading gpr 0x1001 ", $realtime);
debug_mode_if.read_reg_abstract_cmd(16'h1001, gpr, s_tck, s_tms, s_trstn, s_tdi, s_tdo);
debug_mode_if.test_read_sbcs(s_tck, s_tms, s_trstn, s_tdi, s_tdo);
......@@ -197,14 +211,12 @@ uart_bus
// use debug module to load binary
debug_mode_if.load_L2_ini(num_stim, stimuli, s_tck, s_tms, s_trstn, s_tdi, s_tdo);
//debug_mode_if.load_L2_ariane(num_stim, stimuli, s_tck, s_tms, s_trstn, s_tdi, s_tdo);
// write dpc to addr_i so that we know where we resume
debug_mode_if.write_reg_abstract_cmd(riscv::CSR_DPC, BEGIN_MEM_INSTR,
s_tck, s_tms, s_trstn, s_tdi, s_tdo);
// we have set dpc and loaded the binary, we can go now
$display("[TB] %t - Resuming the CORE", $realtime);
debug_mode_if.resume_harts(s_tck, s_tms, s_trstn, s_tdi, s_tdo);
......
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