Bump FPU, DM and common cells

Flist.ariane

@@ -15,7 +15,7 @@
 // Author: Michael Schaffner <schaffner@iis.ee.ethz.ch>, ETH Zurich
 // Date: 15.08.2018
 // Description: File list for OpenPiton flow
-+incdir+src/common_cells/include/common_cells/
++incdir+src/common_cells/include/
 +incdir+src/util/
 src/common_cells/src/deprecated/rrarbiter.sv
 src/common_cells/src/deprecated/fifo_v1.sv

Makefile

@@ -152,8 +152,8 @@ src :=  $(filter-out src/ariane_regfile.sv, $(wildcard src/*.sv))              \
         src/common_cells/src/spill_register.sv                                 \
         src/common_cells/src/sync_wedge.sv                                     \
         src/common_cells/src/edge_detect.sv                                    \
-        src/common_cells/src/deprecated/stream_arbiter.sv                      \
-        src/common_cells/src/deprecated/stream_arbiter_flushable.sv            \
+        src/common_cells/src/stream_arbiter.sv                                 \
+        src/common_cells/src/stream_arbiter_flushable.sv                       \
         src/common_cells/src/deprecated/fifo_v1.sv                             \
         src/common_cells/src/deprecated/fifo_v2.sv                             \
         src/common_cells/src/fifo_v3.sv                                        \
@@ -201,7 +201,7 @@ riscv-fp-tests            := $(shell xargs printf '\n%s' < $(riscv-fp-tests-list
 riscv-benchmarks          := $(shell xargs printf '\n%s' < $(riscv-benchmarks-list) | cut -b 1-)
 
 # Search here for include files (e.g.: non-standalone components)
-incdir := src/common_cells/include/common_cells
+incdir := src/common_cells/include/
 # Compile and sim flags
 compile_flag     += +cover=bcfst+/dut -incr -64 -nologo -quiet -suppress 13262 -permissive +define+$(defines)
 uvm-flags        += +UVM_NO_RELNOTES +UVM_VERBOSITY=LOW

common_cells @ b6436016

-Subproject commit 9baf40457502a93b51b7aacd2c52dbe879e56db3
+Subproject commit b6436016a1022d0069e7d4424ef5087798ee9e67

fpu @ 41b652f6

-Subproject commit e06b882dae9b733973019275b558b6f6abfe674e
+Subproject commit 41b652f677d8290f096c5bc8d75e602d89a187a9

riscv-dbg @ 6d768ac6

-Subproject commit 031ea943fca9a4576068bff54d1414b6fe8b446e
+Subproject commit 6d768ac6371356b6e382c01ae7d860dd3e45248b