Bump common cells to v1.12

Bender.yml

 package:
   name: ariane
-  authors: [ "Florian Zaruba <zarubaf@iis.ee.ethz.ch>" ]
+  authors: [ "Florian Zaruba <zarubaf@iis.ee.ethz.ch>" "Michael Schaffner <schaffner@iis.ee.ethz.ch>"]
 
 dependencies:
   axi:                { git: "https://github.com/pulp-platform/axi.git",                version: 0.4.5 }
   axi_mem_if:         { git: "https://github.com/pulp-platform/axi_mem_if.git",         version: 0.2.0 }
   axi_node:           { git: "https://github.com/pulp-platform/axi_node.git",           version: 1.1.1 }
   tech_cells_generic: { git: "https://github.com/pulp-platform/tech_cells_generic.git", version: 0.1.1 }
-  common_cells:       { git: "https://github.com/pulp-platform/common_cells.git",       version: 1.8.0 }
+  common_cells:       { git: "https://github.com/pulp-platform/common_cells.git",       version: 1.12.0 }
   fpga-support:       { git: "https://github.com/pulp-platform/fpga-support.git",       version: 0.3.2 }
 
 sources:

Flist.ariane

@@ -21,6 +21,7 @@ src/common_cells/src/fifo_v2.sv
 src/common_cells/src/fifo_v3.sv
 src/common_cells/src/lfsr_8bit.sv
 src/common_cells/src/lzc.sv
+src/common_cells/src/rr_arb_tree.sv
 src/common_cells/src/rrarbiter.sv
 src/common_cells/src/rstgen_bypass.sv
 src/common_cells/src/sync_wedge.sv
@@ -72,6 +73,7 @@ src/util/axi_slave_connect.sv
 src/util/axi_slave_connect_rev.sv
 src/fpga-support/rtl/SyncSpRamBeNx64.sv
 src/axi_mem_if/src/axi2mem.sv
+src/tech_cells_generic/src/pulp_clock_gating.sv
 src/tech_cells_generic/src/cluster_clock_inverter.sv
 src/tech_cells_generic/src/pulp_clock_mux2.sv
 src/axi_adapter.sv

Makefile

@@ -157,12 +157,14 @@ src :=  $(filter-out src/ariane_regfile.sv, $(wildcard src/*.sv))              \
         src/common_cells/src/fifo_v2.sv                                        \
         src/common_cells/src/fifo_v1.sv                                        \
         src/common_cells/src/lzc.sv                                            \
+        src/common_cells/src/rr_arb_tree.sv                                    \
         src/common_cells/src/rrarbiter.sv                                      \
         src/common_cells/src/stream_delay.sv                                   \
         src/common_cells/src/lfsr_8bit.sv                                      \
         src/common_cells/src/lfsr_16bit.sv                                     \
         src/common_cells/src/counter.sv                                        \
         src/common_cells/src/shift_reg.sv                                      \
+        src/tech_cells_generic/src/pulp_clock_gating.sv                        \
         src/tech_cells_generic/src/cluster_clock_inverter.sv                   \
         src/tech_cells_generic/src/pulp_clock_mux2.sv                          \
         tb/ariane_testharness.sv                                               \

common_cells @ f59ce566

-Subproject commit 337f54a7cdfdad78b124cbdd2a627db3e0939141
+Subproject commit f59ce566d70bda95a0e056ee19037ce0b8fae531

tb/tb_wt_dcache/tb.list

@@ -12,6 +12,7 @@
 ../../src/common_cells/src/fifo_v2.sv
 ../../src/common_cells/src/fifo_v3.sv
 ../../src/common_cells/src/lzc.sv
+../../src/common_cells/src/rr_arb_tree.sv
 ../../src/common_cells/src/rrarbiter.sv
 ../../src/util/sram.sv
 hdl/tb_pkg.sv