Merge pull request #4 from sjthales/master

zybo kit adding

Makefile

@@ -288,7 +288,27 @@ cva6_ooc: $(ariane_pkg) $(util) $(src) $(fpga_src)
 	@echo read_verilog -sv {$(fpga_src)}   >> fpga/scripts/add_sources.tcl
 	cd fpga && make cva6_ooc BOARD=$(BOARD) XILINX_PART=$(XILINX_PART) XILINX_BOARD=$(XILINX_BOARD) CLK_PERIOD_NS=$(CLK_PERIOD_NS) BATCH_MODE=$(BATCH_MODE)
 
-.PHONY:  cva6_ooc
+.PHONY:  cva6_ooc cva6_fpga program_cva6_fpga get_hs2_id
+
+cva6_fpga: $(ariane_pkg) $(util) $(src) $(fpga_src) $(uart_src)
+	@echo "[FPGA] Generate sources"
+	@echo read_vhdl        {$(uart_src)}    > fpga/scripts/add_sources.tcl
+	@echo read_verilog -sv {$(ariane_pkg)} >> fpga/scripts/add_sources.tcl
+	@echo read_verilog -sv {$(filter-out $(fpga_filter), $(util))}     >> fpga/scripts/add_sources.tcl
+	@echo read_verilog -sv {$(filter-out $(fpga_filter), $(src))} 	   >> fpga/scripts/add_sources.tcl
+	@echo read_verilog -sv {$(fpga_src)}   >> fpga/scripts/add_sources.tcl
+	@echo "[FPGA] Generate Bitstream"
+	cd fpga && make cva6_fpga BOARD=$(BOARD) XILINX_PART=$(XILINX_PART) XILINX_BOARD=$(XILINX_BOARD) CLK_PERIOD_NS=$(CLK_PERIOD_NS) BATCH_MODE=$(BATCH_MODE)
+
+
+program_cva6_fpga: 
+	@echo "[FPGA] Program FPGA"
+	cd fpga && make program_cva6_fpga BOARD=$(BOARD) XILINX_PART=$(XILINX_PART) XILINX_BOARD=$(XILINX_BOARD) CLK_PERIOD_NS=$(CLK_PERIOD_NS) BATCH_MODE=$(BATCH_MODE)
+
+
+get_hs2_sn:
+	@echo "[FPGA] Get HS2 serial number"
+	cd fpga && make get_hs2_sn 
 
 clean:
 	rm -rf $(riscv-torture-dir)/output/test*

README.md

@@ -63,6 +63,8 @@ https://reference.digilentinc.com/reference/programmable-logic/guides/installati
 
 **be careful about your linux distribution and the supported version of Vitis 2020.1 environment**
 
+
+## Hardware 
 If you have not yet done so, start provisioning the following:
 
 | Reference	                 | URL                                                                             |	List price |	Remark                            |
@@ -73,15 +75,99 @@ If you have not yet done so, start provisioning the following:
 | Connectors                 |	https://store.digilentinc.com/pmod-cable-kit-2x6-pin-and-2x6-pin-to-dual-6-pin-pmod-splitter-cable/ | $5.99 |	At least a 6-pin connector Pmod is necessary; other references may offer it. |
 
 
-## Simulation get started
+## OpenOCD
+
+To be able to run and debug software applications on CVA6, you need to install the OpenOCD tool.
+OpenOCD is a free and open-source software distributed under the GPL-2.0 license.
+It provides on-chip programming and debugging support with a layered architecture of JTAG interface and TAP support.
+
+Global documentation on OpenOCD is available at https://github.com/ThalesGroup/pulpino-compliant-debug/tree/pulpino-dbg/doc/riscv-debug-notes/pdfs
+
+These documents aim at providing help about OpenOCD and RISC-V debug.
+
+Before setting up OpenOCD, other tools are needed:
+- make
+- libtool
+- pkg-congfig > 0.23
+- autoconf > 2.64
+- automake > 1.14
+- texinfo
+
+On Ubuntu, ensure that everything is installed with:
+```
+$ sudo apt install make libtool pkg-config autoconf automake texinfo
+```
+
+Furthermore, you need to set up libusb and libftdi libraries.
+On Ubuntu:
+```
+$ sudo apt install libusb-1.0-0-dev libftdi1-dev
+```
+
+Once all dependencies are installed, OpenOCD can be set up.
+- Download sources:
+```
+$ git clone https://github.com/riscv/riscv-openocd
+$ cd riscv-openocd
+```
+- Prepare a **build** directory:
+```
+$ mkdir build
+```
+- Launch the bootstrap script:
+```
+$ ./bootstrap
+```
+- Launch configure:
+```
+$ ./configure --enable-ftdi --prefix=<absolute path>/build --exec-prefix=<absolute path>/build
+```
+- Compile and install files:
+```
+$ make
+$ make install
+```
+When the installation is achieved, do not forget to add riscv-openocd/build/bin to your PATH.
+```
+$ export PATH=$PATH:<path to riscv-openocd>/build/bin
+```
+
+## HS2 cable
+
+It is necessary to add a udev rule to use the cable.
+OpenOCD provides a file containing the rule we need. Copy it into /etc/udev/rules.d/
+```
+$ sudo cp <path to riscv-openocd>/build/share/openocd/contrib/60-openocd.rules /etc/udev/rules.d
+```
+The file is also available here: https://github.com/riscv/riscv-openocd/blob/riscv/contrib/60-openocd.rules
+The particular entry about the HS2 cable is :
+```
+ATTRS{idVendor}=="0403", ATTRS{idProduct}=="6014", MODE="660", GROUP="plugdev", TAG+="uaccess"
+```
+Then either reboot your system or reload the udev configuration with :
+```
+$ sudo udevadm control --reload
+```
+
+To check if the cable is recognized, run lsusb. There should be a line like this:
+```
+$ lsusb
+```
+```
+Bus 005 Device 003: ID 0403:6014 Future Technology Devices International, Ltd FT232HSingle HS USB-UART/FIFO IC
+```
+
+
+
+# Simulation get started
 When the development environment is set up, it is now possible to run a simulation.
-Some software applications are available into the sw/app directory. Especially, there are benchmark applications such as Dhrystone and Coremark and other test applications.
+Some software applications are available into the sw/app directory. Especially, there are benchmark applications such as Dhrystone and CoreMark and other test applications.
 
 To simulate a software application on CVA6 processor, run the following command:
 ```
 $ make sim APP=’application to run’
 ```
-For instance, if you want to run Coremark application, you will have to run :
+For instance, if you want to run the CoreMark application, you will have to run :
 ```
 $ make sim APP=coremark
 ```
@@ -136,4 +222,132 @@ $ make cva6_ooc CLK_PERIOD_NS=20 BATCH_MODE=0
 This command generates synthesis and place and route reports in **fpga/reports_cva6_ooc_synth** and **fpga/reports_cva6_ooc_impl**.
 
 
+# FPGA platform
 
+A FPGA platform prototyping **CV32A6** (CVA6 in 32-bit flavor) has been implemented on **Zybo Z7-20** board.
+
+This platform integrates a CV32A6 processor (clocked to 25MHz), a JTAG interface to run and debug software applications and a UART interface to display strings on a hyperterminal.
+
+Below are described steps to run Coremark application on CV32A6 FPGA platform, steps are the same for Dhrystone application and other software applications.
+
+The JTAG-HS2 programming cable is initially a cable that allows programming of Xilinx FPGAs (bitstream loading) from a host PC.
+
+In our case, we use this cable to program software applications on the CV32A6 instantiated in the FPGA through a PMOD connector.
+
+We do not use the HS2 Cable in its original function therfore there is a preliminary step which consists in retrieving the serial number of the HS2 cable.
+
+To do this, connect the HS2 cable to the host PC (Zybo Z7-20 board must be disconnected from the host PC) and run the following command:
+```
+make get_hs2_sn
+```
+you should see:
+```
+[FPGA] Get HS2 serial number
+...............
+###############################
+# TARGEt: localhost:3121/xilinx_tcf/Digilent/<HS2's serial number>
+###############################
+......................
+```
+Replace the **HS2's serial number** in `fpga/scripts/program_cva-fpga.tcl` file by the serial number of your HS2 cable.
+
+## Get started with Coremark application
+
+1. First, make sure the Digilent **JTAG-HS2 debug adapter** is properly connected to the **PMOD JE** connector and that the USBUART adapter is properly connected to the **PMOD JB** connector of the Zybo Z7-20 board.
+![alt text](https://github.com/sjthales/cva6-softcore-contest/blob/master/docs/pictures/20201204_150708.jpg)
+2. Compile Coremark application in `sw/app`. Commands to compile Coremark application are described in `sw/app` directory.
+3. Generate the bitstream of the FPGA platform:
+```
+$ make cva6_fpga
+```
+4. When the bitstream is generated, switch on Zybo board and run:
+```
+$ make program_cva6_fpga
+```
+When the bitstream is loaded, the green LED `done` lights up.
+![alt text](https://github.com/sjthales/cva6-softcore-contest/blob/master/docs/pictures/20201204_160542.jpg)
+
+5. Then, in a terminal, launch **OpenOCD**:
+```
+$ openocd -f fpga/openocd_digilent_hs2.cfg
+```
+If it is successful, you should see:
+```
+Open On-Chip Debugger 0.10.0+dev-00832-gaec5cca (2019-12-10-14:21)
+Licensed under GNU GPL v2
+For bug reports, read
+    http://openocd.org/doc/doxygen/bugs.html
+Info : auto-selecting first available session transport "jtag". To override use 'transport select <transport>'.
+Info : clock speed 1000 kHz
+Info : JTAG tap: riscv.cpu tap/device found: 0x249511c3 (mfg: 0x0e1 (Wintec Industries), part: 0x4951, ver: 0x2)
+Info : datacount=2 progbufsize=8
+Info : Examined RISC-V core; found 1 harts
+Info :  hart 0: XLEN=32, misa=0x40141105
+Info : Listening on port 3333 for gdb connections
+Ready for Remote Connections
+Info : Listening on port 6666 for tcl connections
+Info : Listening on port 4444 for telnet connections
+
+```
+6. In separate terminal, launch **gdb**:
+```
+$ riscv32-unknown-elf-gdb sw/app/coremark.riscv
+```
+you must use the gdb from the RISC-V toolchain. If it is successful, you should see:
+```
+GNU gdb (GDB) 9.1
+Copyright (C) 2020 Free Software Foundation, Inc.
+License GPLv3+: GNU GPL version 3 or later <http://gnu.org/licenses/gpl.html>
+This is free software: you are free to change and redistribute it.
+There is NO WARRANTY, to the extent permitted by law.
+Type "show copying" and "show warranty" for details.
+This GDB was configured as "--host=x86_64-pc-linux-gnu --target=riscv32-unknown-elf".
+Type "show configuration" for configuration details.
+For bug reporting instructions, please see:
+<http://www.gnu.org/software/gdb/bugs/>.
+Find the GDB manual and other documentation resources online at:
+    <http://www.gnu.org/software/gdb/documentation/>.
+
+For help, type "help".
+Type "apropos word" to search for commands related to "word"...
+Reading symbols from sw/app/coremark.riscv...
+(gdb) 
+```
+7. In **gdb**, you need to connect gdb to openocd:
+```
+(gdb) target remote :3333
+```
+if it is successful, you should see the gdb connection in **openocd**:
+```
+Info : accepting 'gdb' connection on tcp/3333
+```
+8. In **gdb**, load **coremark.riscv** to CV32A6 FPGA platform by the **load** command:
+```
+(gdb) load
+Loading section .vectors, size 0x80 lma 0x80000000
+Loading section .init, size 0x60 lma 0x80000080
+Loading section .text, size 0x19010 lma 0x800000e0
+Loading section .rodata, size 0x1520 lma 0x800190f0
+Loading section .eh_frame, size 0x50 lma 0x8001a610
+Loading section .init_array, size 0x4 lma 0x8001a660
+Loading section .data, size 0x9d4 lma 0x8001a668
+Loading section .sdata, size 0x40 lma 0x8001b040
+Start address 0x80000080, load size 110712
+Transfer rate: 63 KB/sec, 7908 bytes/write.
+```
+
+9. At last, in **gdb**, you can run the coremark application by command `c`:
+```
+(gdb) c
+Continuing.
+(gdb) 
+```
+
+10. On the hyperterminal configured on /dev/ttyUSB0 11520-8-N-1, you should see:
+```
+2K performance run parameters for coremark.
+
+....
+
+CoreMark 1.0 : [the CoreMark score
+```

fpga/Makefile

@@ -29,15 +29,51 @@
 
 VIVADO ?= vivado
 
+work-dir := work-fpga
+bit := $(work-dir)/cva6_fpga.bit
+
+ip-dir := xilinx
+ips := xlnx_blk_mem_gen.xci  \
+       xlnx_axi_clock_converter.xci  \
+       xlnx_axi_dwidth_converter_dm_master.xci \
+       xlnx_axi_dwidth_converter_dm_slave.xci \
+       xlnx_clk_gen.xci             
+
 all: $(cva6_ooc)
 
 cva6_ooc: 
 ifeq ($(BATCH_MODE), 1)
 	$(VIVADO) -mode batch -source  scripts/run_cva6_ooc.tcl
 else
-	$(VIVADO) -source  scripts/run_cva6_ooc.tcl	
+	$(VIVADO) -source scripts/run_cva6_ooc.tcl	
+endif
+
+cva6_fpga: $(ips)
+ifeq ($(BATCH_MODE), 1)
+	mkdir -p $(work-dir)
+	$(VIVADO) -mode batch -source scripts/run_cva6_fpga.tcl
+else
+	$(VIVADO) -source scripts/run_cva6_fpga.tcl	
+endif
+
+program_cva6_fpga:
+ifeq ($(BATCH_MODE), 1)
+	$(VIVADO) -mode batch -source scripts/program_cva6_fpga.tcl
+else
+	$(VIVADO) -source scripts/program_cva6_fpga.tcl	
 endif
 
+get_hs2_sn:
+	$(VIVADO) -mode batch -source scripts/get_hs2_sn.tcl
+
+
+
+
+$(ips): %.xci :
+	mkdir -p $(work-dir)
+	@echo Generating $(@F)
+	@cd $(ip-dir)/$(basename $(@F)) && make clean && make
+	@cp $(ip-dir)/$(basename $(@F))/ip/$(@F) $@
 
 clean:
 	rm -rf 	*.log \
@@ -45,15 +81,25 @@ clean:
 		*.str \
 		*.mif \
 		*.xpr \
+		*.xci \
 		cva6_ooc.cache \
 		cva6_ooc.hw \
 		cva6_ooc.ip_user_files \
 		cva6_ooc.sim \
 		cva6_ooc.runs \
 		cva6_ooc.hbs \
+		cva6_fpga.cache \
+		cva6_fpga.hw \
+		cva6_fpga.ip_user_files \
+		cva6_fpga.sim \
+		cva6_fpga.runs \
+		cva6_fpga.hbs \
 		.Xil \
 		reports_cva6_ooc_synth \
-		reports_cva6_ooc_impl 
+		reports_cva6_ooc_impl \
+		reports_cva6_fpga_synth \
+		reports_cva6_fpga_impl \
+		$(work-dir)
 
 
 .PHONY:

fpga/constraints/cva6_fpga.xdc

+## Common Ariane XDCs
+
+create_clock -period 100.000 -name tck -waveform {0.000 50.000} [get_ports tck]
+set_input_jitter tck 1.000
+set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets tck_IBUF]
+
+# minimize routing delay
+set_input_delay -clock tck -clock_fall 5.000 [get_ports tdi]
+set_input_delay -clock tck -clock_fall 5.000 [get_ports tms]
+set_output_delay -clock tck 5.000 [get_ports tdo]
+set_false_path -from [get_ports trst_n]
+
+
+set_max_delay -datapath_only -from [get_pins i_dmi_jtag/i_dmi_cdc/i_cdc_resp/i_src/data_src_q_reg*/C] -to [get_pins i_dmi_jtag/i_dmi_cdc/i_cdc_resp/i_dst/data_dst_q_reg*/D] 20.000
+set_max_delay -datapath_only -from [get_pins i_dmi_jtag/i_dmi_cdc/i_cdc_resp/i_src/req_src_q_reg/C] -to [get_pins i_dmi_jtag/i_dmi_cdc/i_cdc_resp/i_dst/req_dst_q_reg/D] 20.000
+set_max_delay -datapath_only -from [get_pins i_dmi_jtag/i_dmi_cdc/i_cdc_req/i_dst/ack_dst_q_reg/C] -to [get_pins i_dmi_jtag/i_dmi_cdc/i_cdc_req/i_src/ack_src_q_reg/D] 20.000
+
+# set multicycle path on reset, on the FPGA we do not care about the reset anyway
+set_multicycle_path -from [get_pins {i_rstgen_main/i_rstgen_bypass/synch_regs_q_reg[3]/C}] 4
+set_multicycle_path -hold -from [get_pins {i_rstgen_main/i_rstgen_bypass/synch_regs_q_reg[3]/C}] 3
+
+set_property MARK_DEBUG false [get_nets {debug_req[data][7]}]
+set_property MARK_DEBUG false [get_nets {debug_req[data][4]}]
+set_property MARK_DEBUG false [get_nets {debug_req[data][0]}]
+set_property MARK_DEBUG false [get_nets {debug_req[data][1]}]
+set_property MARK_DEBUG false [get_nets {debug_req[data][2]}]
+set_property MARK_DEBUG false [get_nets {debug_req[data][3]}]
+set_property MARK_DEBUG false [get_nets {debug_req[data][5]}]
+set_property MARK_DEBUG false [get_nets {debug_req[data][6]}]
+set_property MARK_DEBUG false [get_nets {debug_req[data][8]}]
+set_property MARK_DEBUG false [get_nets {debug_req[data][11]}]
+set_property MARK_DEBUG false [get_nets {debug_req[data][13]}]
+set_property MARK_DEBUG false [get_nets {debug_req[data][15]}]
+set_property MARK_DEBUG false [get_nets {debug_req[data][17]}]
+set_property MARK_DEBUG false [get_nets {debug_req[data][19]}]
+set_property MARK_DEBUG false [get_nets {debug_req[data][21]}]
+set_property MARK_DEBUG false [get_nets {debug_req[data][23]}]
+set_property MARK_DEBUG false [get_nets {debug_req[data][25]}]
+set_property MARK_DEBUG false [get_nets {debug_req[data][27]}]
+set_property MARK_DEBUG false [get_nets {debug_req[data][29]}]
+set_property MARK_DEBUG false [get_nets {debug_req[data][31]}]
+set_property MARK_DEBUG false [get_nets {debug_req[data][30]}]
+set_property MARK_DEBUG false [get_nets {debug_req[data][28]}]
+set_property MARK_DEBUG false [get_nets {debug_req[data][26]}]
+set_property MARK_DEBUG false [get_nets {debug_req[data][24]}]
+set_property MARK_DEBUG false [get_nets {debug_req[data][22]}]
+set_property MARK_DEBUG false [get_nets {debug_req[data][20]}]
+set_property MARK_DEBUG false [get_nets {debug_req[data][18]}]
+set_property MARK_DEBUG false [get_nets {debug_req[data][16]}]
+set_property MARK_DEBUG false [get_nets {debug_req[data][14]}]
+set_property MARK_DEBUG false [get_nets {debug_req[data][12]}]
+set_property MARK_DEBUG false [get_nets {debug_req[data][9]}]
+set_property MARK_DEBUG false [get_nets {debug_req[data][10]}]

fpga/constraints/zybo_z7_20.xdc

+set_property PACKAGE_PIN K17 [get_ports clk_sys]
+set_property IOSTANDARD LVCMOS33 [get_ports clk_sys]
+
+## Buttons
+set_property -dict {PACKAGE_PIN Y16 IOSTANDARD LVCMOS33} [get_ports cpu_reset]
+
+## To use FTDI FT2232 JTAG
+set_property -dict {PACKAGE_PIN V13 IOSTANDARD LVCMOS33} [get_ports trst_n]
+set_property -dict {PACKAGE_PIN H15 IOSTANDARD LVCMOS33} [get_ports tck]
+set_property -dict {PACKAGE_PIN W16 IOSTANDARD LVCMOS33} [get_ports tdi]
+set_property -dict {PACKAGE_PIN J15 IOSTANDARD LVCMOS33} [get_ports tdo]
+set_property -dict {PACKAGE_PIN V12 IOSTANDARD LVCMOS33} [get_ports tms]
+
+## UART
+set_property -dict {PACKAGE_PIN W8 IOSTANDARD LVCMOS33} [get_ports tx]
+set_property -dict {PACKAGE_PIN U7 IOSTANDARD LVCMOS33} [get_ports rx]
+
+
+
+
+## JTAG
+# minimize routing delay
+
+set_max_delay -to [get_ports tdo] 20.000
+set_max_delay -from [get_ports tms] 20.000
+set_max_delay -from [get_ports tdi] 20.000
+set_max_delay -from [get_ports trst_n] 20.000
+
+# reset signal
+set_false_path -from [get_ports trst_n]
+
+

fpga/openocd_digilent_hs2.cfg

+
+
+# Digilent JTAG-HS2
+
+
+interface ftdi
+ftdi_device_desc "Digilent USB Device"
+ftdi_vid_pid 0x0403 0x6014
+##ftdi_serial 210249A85F9B
+ftdi_channel 0						
+ftdi_layout_init 0x00e8 0x60eb
+
+reset_config none
+
+
+adapter_khz     1000
+
+
+# TAP declaration
+set _CHIPNAME riscv
+jtag newtap $_CHIPNAME cpu -irlen 5 -expected-id 0x249511C3
+
+set _TARGETNAME $_CHIPNAME.cpu
+target create $_TARGETNAME riscv -chain-position $_TARGETNAME -coreid 0
+
+gdb_report_data_abort enable
+gdb_report_register_access_error enable
+
+riscv set_reset_timeout_sec 120
+riscv set_command_timeout_sec 120
+
+# prefer to use sba for system bus access
+riscv set_prefer_sba on
+
+# dump jtag chain
+scan_chain
+bindto 0.0.0.0
+
+init
+halt
+echo "Ready for Remote Connections"

fpga/scripts/get_hs2_sn.tcl

+open_hw_manager
+connect_hw_server
+foreach TARGET [get_hw_targets] {
+     puts "###############################"
+     puts "# TARGET: $TARGET"
+     puts "###############################"
+}
+

fpga/scripts/program_cva6_fpga.tcl

+open_hw_manager
+connect_hw_server
+current_hw_target [get_hw_targets -filter {NAME!~"localhost:3121/xilinx_tcf/Digilent/<HS2's serial number>"}]
+open_hw_target
+set_property PROGRAM.FILE {cva6_fpga.runs/impl_1/cva6_zybo_z7_20.bit} [get_hw_devices xc7z020_1]
+current_hw_device [get_hw_devices xc7z020_1]
+refresh_hw_device -update_hw_probes false [lindex [get_hw_devices xc7z020_1] 0]
+set_property PROBES.FILE {} [get_hw_devices xc7z020_1]
+set_property FULL_PROBES.FILE {} [get_hw_devices xc7z020_1]
+set_property PROGRAM.FILE {cva6_fpga.runs/impl_1/cva6_zybo_z7_20.bit} [get_hw_devices xc7z020_1]
+program_hw_devices [get_hw_devices xc7z020_1]
+refresh_hw_device [lindex [get_hw_devices xc7z020_1] 0]
+

fpga/scripts/run_cva6_fpga.tcl

+# Copyright (c) 2020 Thales.
+# 
+# Copyright and related rights are licensed under the Solderpad
+# License, Version 2.0 (the "License"); you may not use this file except in
+# compliance with the License.  You may obtain a copy of the License at
+# http://solderpad.org/licenses/SHL-2.0/ Unless required by applicable law
+# or agreed to in writing, software, hardware and materials distributed under
+# this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR
+# CONDITIONS OF ANY KIND, either express or implied. See the License for the
+# specific language governing permissions and limitations under the License.
+#
+# Author:         Sebastien Jacq - sjthales on github.com
+
+#
+# Additional contributions by:
+#
+#
+# script Name:    run_cva6_fpga
+# Project Name:   CVA6 softcore
+# Language:       tcl
+#
+# Description:    Script to generate bitstream of CVA6 architecture
+#                 in Zybo 7-20 board
+#
+# =========================================================================== #
+# Revisions  :
+# Date        Version  Author       Description
+# 2020-11-06  0.1      S.Jacq       Created
+# =========================================================================== #
+set project cva6_fpga
+
+create_project $project . -force -part $::env(XILINX_PART)
+set_property board_part $::env(XILINX_BOARD) [current_project]
+
+
+
+# set number of threads to 8 (maximum, unfortunately)
+set_param general.maxThreads 8
+
+set_msg_config -id {[Synth 8-5858]} -new_severity "info"
+
+set_msg_config -id {[Synth 8-4480]} -limit 1000
+
+add_files -fileset constrs_1 -norecurse constraints/zybo_z7_20.xdc
+
+read_ip xilinx/xlnx_blk_mem_gen/ip/xlnx_blk_mem_gen.xci
+read_ip xilinx/xlnx_axi_clock_converter/ip/xlnx_axi_clock_converter.xci
+read_ip xilinx/xlnx_axi_dwidth_converter_dm_slave/ip/xlnx_axi_dwidth_converter_dm_slave.xci
+read_ip xilinx/xlnx_axi_dwidth_converter_dm_master/ip/xlnx_axi_dwidth_converter_dm_master.xci
+
+read_ip xilinx/xlnx_clk_gen/ip/xlnx_clk_gen.xci
+
+set_property include_dirs { "src/axi_sd_bridge/include" "../src/common_cells/include" } [current_fileset]
+
+source scripts/add_sources.tcl
+
+set_property top cva6_zybo_z7_20 [current_fileset]
+
+read_verilog -sv {src/zybo-z7-20.svh ../src/common_cells/include/common_cells/registers.svh}
+set file "src/zybo-z7-20.svh"
+set registers "../src/common_cells/include/common_cells/registers.svh"
+
+set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file" "$registers"]]
+set_property -dict { file_type {Verilog Header} is_global_include 1} -objects $file_obj
+
+update_compile_order -fileset sources_1
+
+add_files -fileset constrs_1 -norecurse constraints/$project.xdc
+
+synth_design -rtl -name rtl_1
+
+
+set_property STEPS.SYNTH_DESIGN.ARGS.RETIMING true [get_runs synth_1]
+
+launch_runs synth_1
+wait_on_run synth_1
+open_run synth_1
+
+exec mkdir -p reports_cva6_fpga_synth/
+exec rm -rf reports_cva6_fpga_synth/*
+
+
+check_timing -verbose                                                   -file reports_cva6_fpga_synth/$project.check_timing.rpt
+report_timing -max_paths 100 -nworst 100 -delay_type max -sort_by slack -file reports_cva6_fpga_synth/$project.timing_WORST_100.rpt
+report_timing -nworst 1 -delay_type max -sort_by group                  -file reports_cva6_fpga_synth/$project.timing.rpt
+report_utilization -hierarchical                                        -file reports_cva6_fpga_synth/$project.utilization.rpt
+report_cdc                                                              -file reports_cva6_fpga_synth/$project.cdc.rpt
+report_clock_interaction                                                -file reports_cva6_fpga_synth/$project.clock_interaction.rpt
+
+# set for RuntimeOptimized implementation
+set_property "steps.place_design.args.directive" "RuntimeOptimized" [get_runs impl_1]
+set_property "steps.route_design.args.directive" "RuntimeOptimized" [get_runs impl_1]
+
+##create_clock -period $::env(CLK_PERIOD_NS) -name clk_i   [get_ports clk_i]
+
+#set_property HD.CLK_SRC BUFGCTRL_X1Y2 [get_ports clk_i]
+
+
+launch_runs impl_1
+wait_on_run impl_1
+launch_runs impl_1 -to_step write_bitstream
+wait_on_run impl_1
+open_run impl_1
+
+# reports
+exec mkdir -p reports_cva6_fpga_impl/
+exec rm -rf reports_cva6_fpga_impl/*
+check_timing                                                              -file reports_cva6_fpga_impl/${project}.check_timing.rpt
+report_timing -max_paths 100 -nworst 100 -delay_type max -sort_by slack   -file reports_cva6_fpga_impl/${project}.timing_WORST_100.rpt
+report_timing -nworst 1 -delay_type max -sort_by group                    -file reports_cva6_fpga_impl/${project}.timing.rpt
+report_utilization -hierarchical                                          -file reports_cva6_fpga_impl/${project}.utilization.rpt

fpga/src/ariane_peripherals_xilinx.sv

@@ -308,7 +308,7 @@ module ariane_peripherals #(
     // ---------------
     // 3. SPI
     // ---------------
-    assign spi.b_user = 1'b0;
+    //assign spi.b_user = 1'b0;
     assign spi.r_user = 1'b0;
 
     if (InclSPI) begin : gen_spi

fpga/src/fan_ctrl.sv

-// Copyright 2018 ETH Zurich and University of Bologna.
-// Copyright and related rights are licensed under the Solderpad Hardware
-// License, Version 0.51 (the "License"); you may not use this file except in
-// compliance with the License.  You may obtain a copy of the License at
-// http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law
-// or agreed to in writing, software, hardware and materials distributed under
-// this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR
-// CONDITIONS OF ANY KIND, either express or implied. See the License for the
-// specific language governing permissions and limitations under the License.
-
-// Description: PWM Fan Control for Genesys II board
-// Author: Florian Zaruba, zarubaf@iis.ee.ethz.ch
-
-module fan_ctrl (
-    input  logic       clk_i,
-    input  logic       rst_ni,
-    input  logic [3:0] pwm_setting_i,
-    output logic       fan_pwm_o
-);
-    logic [3:0]  ms_clock_d, ms_clock_q;
-    logic [19:0] cycle_counter_d, cycle_counter_q;
-
-    // clock divider
-    always_comb begin
-        cycle_counter_d = cycle_counter_q;
-        ms_clock_d = ms_clock_q;
-
-        // divide clock by 499999
-        if (cycle_counter_q == 499_999) begin
-            cycle_counter_d = 0;
-            ms_clock_d = ms_clock_q + 1;
-        end else begin
-            cycle_counter_d = cycle_counter_q + 1;
-        end
-
-        if (ms_clock_q == 15) begin
-            ms_clock_d = 0;
-        end
-    end
-
-    // duty cycle
-    always_comb begin
-        if (ms_clock_q < pwm_setting_i) begin
-            fan_pwm_o = 1'b1;
-        end else begin
-            fan_pwm_o = 1'b0;
-        end
-    end
-
-    always_ff @(posedge clk_i or negedge rst_ni) begin
-        if (~rst_ni) begin
-            ms_clock_q      <= '0;
-            cycle_counter_q <= '0;
-        end else begin
-            ms_clock_q      <= ms_clock_d;
-            cycle_counter_q <= cycle_counter_d;
-        end
-    end
-endmodule

fpga/src/genesysii.svh

-// Copyright 2018 ETH Zurich and University of Bologna.
-// Copyright and related rights are licensed under the Solderpad Hardware
-// License, Version 0.51 (the "License"); you may not use this file except in
-// compliance with the License.  You may obtain a copy of the License at
-// http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law
-// or agreed to in writing, software, hardware and materials distributed under
-// this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR
-// CONDITIONS OF ANY KIND, either express or implied. See the License for the
-// specific language governing permissions and limitations under the License.
-
-// Description: Set global FPGA degines
-// Author: Florian Zaruba <zarubaf@iis.ee.ethz.ch>
-
-`define GENESYSII
-// include KINTEX7 specific code (relevant for KC705, GENESYSII,...)
-`define KINTEX7
-
-`define ARIANE_DATA_WIDTH 64
-
-// Instantiate protocl checker
-// `define PROTOCOL_CHECKER
-
-// write-back cache
-// `define WB_DCACHE
-
-// write-through cache
-`define WT_DCACHE

fpga/src/kc705.svh

-// Copyright 2018 ETH Zurich and University of Bologna.
-// Copyright and related rights are licensed under the Solderpad Hardware
-// License, Version 0.51 (the "License"); you may not use this file except in
-// compliance with the License.  You may obtain a copy of the License at
-// http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law
-// or agreed to in writing, software, hardware and materials distributed under
-// this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR
-// CONDITIONS OF ANY KIND, either express or implied. See the License for the
-// specific language governing permissions and limitations under the License.
-
-// Description: Set global FPGA degines
-// Author: Florian Zaruba <zarubaf@iis.ee.ethz.ch>
-
-`define KC705
-// include KINTEX7 specific code (relevant for KC705, GENESYSII,...)
-`define KINTEX7
-
-`define ARIANE_DATA_WIDTH 64
-
-// Instantiate protocl checker
-// `define PROTOCOL_CHECKER
-
-// write-back cache
-// `define WB_DCACHE
-
-// write-through cache
-`define WT_DCACHE

fpga/src/vc707.svh

-// Copyright 2018 ETH Zurich and University of Bologna.
-// Copyright and related rights are licensed under the Solderpad Hardware
-// License, Version 0.51 (the "License"); you may not use this file except in
-// compliance with the License.  You may obtain a copy of the License at
-// http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law
-// or agreed to in writing, software, hardware and materials distributed under
-// this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR
-// CONDITIONS OF ANY KIND, either express or implied. See the License for the
-// specific language governing permissions and limitations under the License.
-
-// Description: Set global FPGA degines
-// Author: Florian Zaruba <zarubaf@iis.ee.ethz.ch>
-
-`define VC707
-
-`define ARIANE_DATA_WIDTH 64
-
-// Instantiate protocl checker
-// `define PROTOCOL_CHECKER
-
-// write-back cache
-// `define WB_DCACHE
-
-// write-through cache
-`define WT_DCACHE

fpga/src/vcu118.svh

-// Copyright 2018 ETH Zurich and University of Bologna.
-// Copyright and related rights are licensed under the Solderpad Hardware
-// License, Version 0.51 (the "License"); you may not use this file except in
-// compliance with the License.  You may obtain a copy of the License at
-// http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law
-// or agreed to in writing, software, hardware and materials distributed under
-// this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR
-// CONDITIONS OF ANY KIND, either express or implied. See the License for the
-// specific language governing permissions and limitations under the License.
-
-// Description: Set global FPGA degines
-// Author: Florian Zaruba <zarubaf@iis.ee.ethz.ch>
-
-`define VCU118

fpga/src/zybo-z7-20.svh

@@ -9,3 +9,6 @@
 
 // write-through cache
 `define WT_DCACHE
+
+// debug probe
+//`define LAUTERBACH_DEBUG_PROBE