sic: hide branch prediction stats

Signed-off-by: Alban Gruin <alban.gruin@irit.fr>

bench/sic/siccsrs.c

@@ -17,14 +17,24 @@ static inline void print_uint(const char *msg, uint32_t val) {
 
 static uint32_t base_time;
 static uint32_t base_committed;
+/* static uint32_t base_br; */
+/* static uint32_t base_mispred; */
 
 void sicsetup(void) {
+    /* asm volatile( */
+    /* 	    ".align 4\n" */
+    /* 	    "fence.i\n" */
+    /* 	    ".align 4\n" */
+    /* ); */
+
     READCSR(base_time, 0xB00);
     READCSR(base_committed, 0xB02);
+    /* READCSR(base_br, 0xB0B); */
+    /* READCSR(base_mispred, 0xB0E); */
 }
 
 void siccsrs(void) {
-    uint32_t brpending, mempending, lsu, imiss, imisscnt, mtotaltime, committed;
+    uint32_t brpending, mempending, lsu, imiss, imisscnt, mtotaltime, committed/* , br, mispred */;
 
     READCSR(brpending, 0xB11);
     READCSR(mempending, 0xB12);
@@ -33,6 +43,8 @@ void siccsrs(void) {
     READCSR(imisscnt, 0xB03);
     READCSR(mtotaltime, 0xB00);
     READCSR(committed, 0xB02);
+    /* READCSR(br, 0xB0B); */
+    /* READCSR(mispred, 0xB0E); */
 
     print_uint("brpending: ", brpending);
     print_uint("; mempending: ", mempending);
@@ -43,5 +55,9 @@ void siccsrs(void) {
     print_uint("; base time: ", base_time);
     print_uint("; total committed: ", committed);
     print_uint("; base committed: ", base_committed);
+    /* print_uint("; total br: ", br); */
+    /* print_uint("; base br: ", base_br); */
+    /* print_uint("; mispred: ", mispred); */
+    /* print_uint("; base mispred: ", base_mispred); */
     puts("\a");
 }