cache_subsystem: add signal dcache_load_delayed

Signed-off-by: Alban Gruin <alban.gruin@irit.fr>

src/ariane.sv

@@ -254,6 +254,7 @@ module ariane import ariane_pkg::*; #(
   dcache_req_o_t [2:0]      dcache_req_ports_cache_ex;
   logic                     dcache_commit_wbuffer_empty;
   logic                     dcache_commit_wbuffer_not_ni;
+  logic                     dcache_load_delayed;
 
   // --------------
   // Frontend
@@ -690,6 +691,7 @@ module ariane import ariane_pkg::*; #(
     .dcache_enable_i       ( dcache_en_csr_nbdcache      ),
     .dcache_flush_i        ( dcache_flush_ctrl_cache     ),
     .dcache_flush_ack_o    ( dcache_flush_ack_cache_ctrl ),
+    .dcache_load_delayed_o ( dcache_load_delayed         ),
     // to commit stage
     .dcache_amo_req_i      ( amo_req                     ),
     .dcache_amo_resp_o     ( amo_resp                    ),

src/cache_subsystem/wt_axi_adapter.sv

@@ -37,6 +37,8 @@ module wt_axi_adapter import ariane_pkg::*; import wt_cache_pkg::*; #(
   output logic                 dcache_rtrn_vld_o,
   output dcache_rtrn_t         dcache_rtrn_o,
 
+  output logic                 dcache_load_delayed_o,
+
   // AXI port
   output ariane_axi::req_t    axi_req_o,
   input  ariane_axi::resp_t   axi_resp_i
@@ -86,6 +88,7 @@ module wt_axi_adapter import ariane_pkg::*; import wt_cache_pkg::*; #(
 
   logic dcache_awaits_loads;
   logic dcache_has_no_loads;
+  logic icache_over_dcache;
 
   assign dcache_awaits_loads = ~dcache_has_no_loads;
 
@@ -141,6 +144,8 @@ module wt_axi_adapter import ariane_pkg::*; import wt_cache_pkg::*; #(
     axi_rd_lock  = '0;
     axi_rd_blen  = '0;
 
+    dcache_load_delayed_o = 1'b0;
+
     // arbiter mux
     if (arb_idx) begin
       axi_rd_addr  = {{64-riscv::PLEN{1'b0}}, dcache_data.paddr};
@@ -165,7 +170,8 @@ module wt_axi_adapter import ariane_pkg::*; import wt_cache_pkg::*; #(
       if (arb_idx == 0) begin
         //////////////////////////////////////
         // IMISS
-        axi_rd_req   = 1'b1;
+        axi_rd_req = 1'b1;
+        dcache_load_delayed_o = dcache_awaits_loads;
         //////////////////////////////////////
       end else begin
         unique case (dcache_data.rtype)

src/cache_subsystem/wt_cache_subsystem.sv

@@ -41,6 +41,7 @@ module wt_cache_subsystem import ariane_pkg::*; import wt_cache_pkg::*; #(
   input  logic                           dcache_flush_i,         // high until acknowledged
   output logic                           dcache_flush_ack_o,     // send a single cycle acknowledge signal when the cache is flushed
   output logic                           dcache_miss_o,          // we missed on a ld/st
+  output logic                           dcache_load_delayed_o,
   // AMO interface
   input amo_req_t                        dcache_amo_req_i,
   output amo_resp_t                      dcache_amo_resp_o,
@@ -148,6 +149,8 @@ module wt_cache_subsystem import ariane_pkg::*; import wt_cache_pkg::*; #(
     .l15_req_o          ( l15_req_o               ),
     .l15_rtrn_i         ( l15_rtrn_i              )
   );
+
+  assign dcache_load_delayed_o = 1'b0;
 `else
   wt_axi_adapter i_adapter (
     .clk_i              ( clk_i                   ),
@@ -162,6 +165,7 @@ module wt_cache_subsystem import ariane_pkg::*; import wt_cache_pkg::*; #(
     .dcache_data_i      ( dcache_adapter          ),
     .dcache_rtrn_vld_o  ( adapter_dcache_rtrn_vld ),
     .dcache_rtrn_o      ( adapter_dcache          ),
+    .dcache_load_delayed_o,
     .axi_req_o          ( axi_req_o               ),
     .axi_resp_i         ( axi_resp_i              )
   );