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MINOTAuR
MINOTAuR
Commits
8e24679b
Commit
8e24679b
authored
3 years ago
by
Alban Gruin
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Revert "ex_stage: add an arbitrer to the FLU bus"
This reverts commit 0c3a6d408777a0461b5476040b3dda8cf101daff.
parent
85213240
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src/ex_stage.sv
+13
-59
13 additions, 59 deletions
src/ex_stage.sv
with
13 additions
and
59 deletions
src/ex_stage.sv
+
13
−
59
View file @
8e24679b
...
...
@@ -108,11 +108,6 @@ module ex_stage import ariane_pkg::*; #(
input
logic
[
15
:
0
][
53
:
0
]
pmpaddr_i
);
typedef
struct
packed
{
riscv
::
xlen_t
result
;
logic
[
TRANS_ID_BITS
-
1
:
0
]
trans_id
;
}
flu_res_t
;
// -------------------------
// Fixed Latency Units
// -------------------------
...
...
@@ -148,10 +143,6 @@ module ex_stage import ariane_pkg::*; #(
logic
[
TRANS_ID_BITS
-
1
:
0
]
mult_trans_id
;
logic
mult_valid
;
// FLU arbitrer
flu_res_t
alu_res_in
,
alu_res_out
;
logic
push_alu_res
,
pop_alu_res
,
alu_empty
;
// 1. ALU (combinatorial)
// data silence operation
fu_data_t
alu_data
;
...
...
@@ -199,52 +190,30 @@ module ex_stage import ariane_pkg::*; #(
.
csr_addr_o
);
// ready flags for FLU
always_comb
begin
flu_ready_o
=
csr_ready
&
mult_ready
;
end
assign
flu_valid_o
=
alu_valid_i
|
branch_valid_i
|
csr_valid_i
|
mult_valid
;
// result MUX
always_comb
begin
pop_alu_res
=
1'b0
;
push_alu_res
=
1'b0
;
flu_result_o
=
branch_valid_i
?
{{
riscv
::
XLEN
-
riscv
::
VLEN
{
1'b0
}}
,
branch_result
}
:
alu_result
;
// Branch result as default case
flu_result_o
=
{{
riscv
::
XLEN
-
riscv
::
VLEN
{
1'b0
}}
,
branch_result
}
;
flu_trans_id_o
=
fu_data_i
.
trans_id
;
flu_valid_o
=
1'b0
;
alu_res_in
.
result
=
branch_valid_i
?
{{
riscv
::
XLEN
-
riscv
::
VLEN
{
1'b0
}}
,
branch_result
}
:
alu_result
;
alu_res_in
.
trans_id
=
fu_data_i
.
trans_id
;
if
(
csr_valid_i
)
begin
// ALU result
if
(
alu_valid_i
)
begin
flu_result_o
=
alu_result
;
// CSR result
end
else
if
(
csr_valid_i
)
begin
flu_result_o
=
csr_result
;
flu_valid_o
=
1'b1
;
if
(
mult_valid
)
begin
alu_res_in
.
result
=
mult_result
;
alu_res_in
.
trans_id
=
mult_trans_id
;
end
push_alu_res
=
mult_valid
|
alu_valid_i
|
branch_valid_i
;
end
else
if
(
mult_valid
)
begin
flu_result_o
=
mult_result
;
flu_trans_id_o
=
mult_trans_id
;
flu_valid_o
=
1'b1
;
push_alu_res
=
alu_valid_i
|
branch_valid_i
;
end
else
if
(
~
alu_empty
)
begin
flu_result_o
=
alu_res_out
.
result
;
flu_trans_id_o
=
alu_res_out
.
trans_id
;
flu_valid_o
=
1'b1
;
pop_alu_res
=
1'b1
;
push_alu_res
=
alu_valid_i
|
branch_valid_i
;
end
else
if
(
alu_valid_i
|
branch_valid_i
)
begin
flu_valid_o
=
1'b1
;
end
end
// ready flags for FLU
always_comb
begin
flu_ready_o
=
csr_ready
&
mult_ready
;
end
// 4. Multiplication (Sequential)
fu_data_t
mult_data
;
// input silencing of multiplier
...
...
@@ -262,21 +231,6 @@ module ex_stage import ariane_pkg::*; #(
.
mult_trans_id_o
(
mult_trans_id
)
);
fifo_v3
#(
.
DEPTH
(
ariane_pkg
::
NR_SB_ENTRIES
),
.
dtype
(
flu_res_t
)
)
i_fifo_alu_res
(
.
clk_i
(
clk_i
),
.
rst_ni
(
rst_ni
),
.
flush_i
(
flush_i
),
.
testmode_i
(
1'b0
),
.
empty_o
(
alu_empty
),
.
data_i
(
alu_res_in
),
.
push_i
(
push_alu_res
),
.
data_o
(
alu_res_out
),
.
pop_i
(
pop_alu_res
)
);
// ----------------
// FPU
// ----------------
...
...
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