perf_counters: add perf counters to check for SIC violations

Signed-off-by: Alban Gruin <alban.gruin@irit.fr>

include/riscv_pkg.sv

@@ -392,10 +392,10 @@ package riscv;
         CSR_MMIS_PREDICT    = 12'hB0E,  // Branch mis-predicted
         CSR_MSB_FULL        = 12'hB0F,  // Scoreboard full
         CSR_MIF_EMPTY       = 12'hB10,  // instruction fetch queue empty
-        CSR_MHPM_COUNTER_17 = 12'hB11,  // reserved
-        CSR_MHPM_COUNTER_18 = 12'hB12,  // reserved
-        CSR_MHPM_COUNTER_19 = 12'hB13,  // reserved
-        CSR_MHPM_COUNTER_20 = 12'hB14,  // reserved
+        CSR_MHPM_COUNTER_17 = 12'hB11,  // SIC / brpending
+        CSR_MHPM_COUNTER_18 = 12'hB12,  // SIC / mempending
+        CSR_MHPM_COUNTER_19 = 12'hB13,  // SIC / LSU blocked by an IF
+        CSR_MHPM_COUNTER_20 = 12'hB14,  // SIC / I$ miss && mempending
         CSR_MHPM_COUNTER_21 = 12'hB15,  // reserved
         CSR_MHPM_COUNTER_22 = 12'hB16,  // reserved
         CSR_MHPM_COUNTER_23 = 12'hB17,  // reserved

src/ariane.sv

@@ -80,6 +80,7 @@ module ariane import ariane_pkg::*; #(
   // IF -> verifier
   // --------------
   logic                     has_mem_access_if_verif;
+  logic                     bsp_if_perf;
 
   // --------------
   // ID <-> ISSUE
@@ -278,6 +279,7 @@ module ariane import ariane_pkg::*; #(
     .fetch_entry_valid_o ( fetch_valid_if_id             ),
     .fetch_entry_ready_i ( fetch_ready_id_if             ),
     .has_mem_access_o    ( has_mem_access_if_verif       ),
+    .branch_speculation_o( bsp_if_perf                   ),
     .*
   );
 
@@ -590,7 +592,12 @@ module ariane import ariane_pkg::*; #(
     .if_empty_i        ( ~fetch_valid_if_id     ),
     .ex_i              ( ex_commit              ),
     .eret_i            ( eret                   ),
-    .resolved_branch_i ( resolved_branch        )
+    .resolved_branch_i ( resolved_branch        ),
+
+    .branch_speculation_i    ( bsp_if_perf                                ),
+    .mempending_i            ( icache_stall_ctrl                          ),
+    .lsu_locked_i            ( 1'b0                                       ),
+    .icache_miss_while_mem_i ( icache_stall_ctrl & icache_miss_cache_perf )
   );
 
   // ------------

src/frontend/frontend.sv

@@ -45,7 +45,8 @@ module frontend import ariane_pkg::*; #(
   output logic               fetch_entry_valid_o, // instruction in IF is valid
   input  logic               fetch_entry_ready_i, // ID acknowledged this instruction
 
-  output logic               has_mem_access_o
+  output logic               has_mem_access_o,
+  output logic               branch_speculation_o
 );
     // Instruction Cache Registers, from I$
     logic [FETCH_WIDTH-1:0] icache_data_q;
@@ -137,6 +138,8 @@ module frontend import ariane_pkg::*; #(
     // address of the call/return already
     logic bp_valid;
 
+    assign branch_speculation_o = bp_valid;
+
     logic [INSTR_PER_FETCH-1:0] is_branch;
     logic [INSTR_PER_FETCH-1:0] is_call;
     logic [INSTR_PER_FETCH-1:0] is_jump;

src/perf_counters.sv

@@ -39,11 +39,17 @@ module perf_counters import ariane_pkg::*; (
   // from PC Gen
   input  exception_t                              ex_i,
   input  logic                                    eret_i,
-  input  bp_resolve_t                             resolved_branch_i
+  input  bp_resolve_t                             resolved_branch_i,
+
+  // SIC
+  input logic branch_speculation_i,
+  input logic mempending_i,
+  input logic lsu_locked_i,
+  input logic icache_miss_while_mem_i
 );
   localparam logic [6:0] RegOffset = riscv::CSR_ML1_ICACHE_MISS >> 5;
 
-  logic [riscv::CSR_MIF_EMPTY : riscv::CSR_ML1_ICACHE_MISS][riscv::XLEN-1:0] perf_counter_d, perf_counter_q;
+  logic [riscv::CSR_MHPM_COUNTER_20 : riscv::CSR_ML1_ICACHE_MISS][riscv::XLEN-1:0] perf_counter_d, perf_counter_q;
 
   always_comb begin : perf_counters
     perf_counter_d = perf_counter_q;
@@ -66,6 +72,18 @@ module perf_counters import ariane_pkg::*; (
       if (dtlb_miss_i)
         perf_counter_d[riscv::CSR_MDTLB_MISS] = perf_counter_q[riscv::CSR_MDTLB_MISS] + 1'b1;
 
+      if (branch_speculation_i)
+        perf_counter_d[riscv::CSR_MHPM_COUNTER_17] = perf_counter_q[riscv::CSR_MHPM_COUNTER_17] + 1'b1;
+
+      if (mempending_i)
+        perf_counter_d[riscv::CSR_MHPM_COUNTER_18] = perf_counter_q[riscv::CSR_MHPM_COUNTER_18] + 1'b1;
+
+      if (lsu_locked_i)
+        perf_counter_d[riscv::CSR_MHPM_COUNTER_19] = perf_counter_q[riscv::CSR_MHPM_COUNTER_19] + 1'b1;
+
+      if (icache_miss_while_mem_i)
+        perf_counter_d[riscv::CSR_MHPM_COUNTER_20] = perf_counter_q[riscv::CSR_MHPM_COUNTER_20] + 1'b1;
+
       // instruction related perf counters
       for (int unsigned i = 0; i < NR_COMMIT_PORTS-1; i++) begin
         if (commit_ack_i[i]) begin