export PATH=$PATH:<path to riscv-openocd>/build/bin
```
And finally, do not forget to check all the details of the contest at [https://github.com/sjthales/cva6-softcore-contest/blob/master/Annonce RISC-V contest v4.pdf](<https://github.com/sjthales/cva6-softcore-contest/blob/master/Annonce RISC-V contest v4.pdf>).
Ajouter une ligne à votre fichier de configuration de shell pour modifier la variable PATH au login.
# Prerequisites
## Configuration linux pour utiliser le Câble HS2
Connecter la carte zybo. 3 câbles relient la carte au PC.
## RISC-V tool chain setting up
The tool chain is available to this link: https://github.com/riscv/riscv-gnu-toolchain
At first, you have to get the sources of the RISCV GNU toolchain:
Allumer la carte (une led rouge s'allume).
Le câble de programmation JTAG-HS2 est un câble qui permet la programmation des Xilinx FPGAs (bitstream loading) à partir d'un port USB du PC (éviter de passer par un hub).
Il est utilisé pour les applications sur le coeur qui est instantié sur le FPGA à travers un connecteur PMOD JE.
Il faut ajouter une règle udev pour utiliser ce câble.
When the installation is achieved, do not forget to add $RISCV/bin to your PATH.
Une ligne ressemblant à cele-ci doit s'afficher :
```
$ export PATH=$PATH:$RISCV/bin
Bus 005 Device 003: ID 0403:6014 Future Technology Devices International, Ltd FT232HSingle HS USB-UART/FIFO IC
```
## Questa tool
Questa Prime **version 10.7** has been used for simulations.
Other simulation tools and versions can be used but will receive no support from the organization team.
Performances **must** be measured using the Questa simulator.
## Vitis/Vivado setting up
This section will be completed in a next release (planned early December 2020).
For the contest, the CVA6 processor will be implemented on Zybo Z7-20 board from Digilent. This board integrates a Zynq 7000 FPGA from Xilinx.
To do so, **Vitis 2020.1** environment from Xilinx need to be installed.
Furthermore, Digilent provides board files for each development board.
This files ease the creation of new projects with automated configuration of several complicated components such as Zynq Processing System and memory interfaces.
All guidelines to install **vitis 2020.1** and **Zybo Z7-20** board files are explained to the following link:
| Connectors | https://store.digilentinc.com/pmod-cable-kit-2x6-pin-and-2x6-pin-to-dual-6-pin-pmod-splitter-cable/ | $5.99 | At least a 6-pin connector Pmod is necessary; other references may offer it. |
## OpenOCD
To be able to run and debug software applications on CVA6, you need to install the OpenOCD tool.
OpenOCD is a free and open-source software distributed under the GPL-2.0 license.
It provides on-chip programming and debugging support with a layered architecture of JTAG interface and TAP support.
## Installer gdb-multiarch
Sur notre ubuntu, le gdb fourni dans la chaine gnu pour riscv provoque un segmentation fault. On utilisera donc gdb-multiarch à la place.
```
Dans un autre terminal :
Verifier quel ttyUSB est connecté au port uart JB de la carte
déconnecter le câble, ls /dev/ttyUSB*, reconnecter le cable, ls /dev/ttyUSB*. En comparant les deux résultats, on trouve le nouveau dev qui doit être utilisé (ttyUSB0 par la suite).
Soyez patient... Une fois terminé, modifier la variable PATH et le fichier de configuration du shell.
# Simulation get started
When the development environment is set up, it is now possible to run a simulation.
Some software applications are available into the sw/app directory. Especially, there are benchmark applications such as Dhrystone and CoreMark and other test applications.
To simulate a software application on CVA6 processor, run the following command:
```
$ make sim APP=’application to run’
```
For instance, if you want to run the CoreMark application, you will have to run :
```
$ make sim APP=coremark
```
For instance, if you want to run Dhrystone application, you will have to run :
```
$ make sim APP=dhrystone
export PATH=$PATH:$RISCV/bin
```
**This command:**
- Compiles CVA6 architecture and testbench with Questa Sim tool.
- Compiles the software application to be run on CVA6 with RISCV tool chain.
- Runs the simulation.
Questa tool will open with waveform window. Some signals will be displayed; you are free to add as many signals as you want.
Moreover, all `printf` used in software application will be displayed into the **transcript** window of Questa Sim and save into **uart** file to the root directory.
> Simulation may take lot of time, so you need to be patient to have results.
## Installer le support de la carte dans Vivado Enterprise 2024.1
A l'IRIT, la carte Zybo est la carte zybo-z7-20:1.0 qui n'est pas fournie d'emblée dans la bibliothèque de cartes de Vivado (seule la zybo-z7-20:1.1). Il nous faut donc celle-ci.
Dans la console TCL de Vivado (onglet dans la fenêtre du bas)
Simulation is programmed to run 10000000 cycles but the result is displayed before the end of simulation.
For Dhrystone application, at the end of the simulation, Dhrystone result is diplayed as following:
```
Dhrystones per Second:
```
and for coremark application, result at the end of simulation is displayed as following:
CVA6 software environment is detailed into `sw/app` directory.
Pour la carte zybo-z7-20:1.1, il suffit d'aller dans Settings et sélectionner le Project Device zybo-z7-20:1.1.
# Synthesis and place and route get started
You can perform synthesis and place and route of the CVA6 architecture.
In the first time, synthesis and place and route are carried in "out of context" mode, that means that the CVA6 architecture is synthetized in the FPGA fabric without consideration of the external IOs constraints.
## Installer le code du FPGA et construire les coremark
That allows to have an estimation of the logical resources used by the CVA6 in the FPGA fabric as well as the maximal frequency of CVA6 architecture. They are both major metrics for a computation architecture.
Command to run synthesis and place & route in "out of context" mode:
```
$ make cva6_ooc CLK_PERIOD_NS=<period of the architecture in ns>
```
For example, if you want to clock the architecture to 50 MHz, you have to run:
```
$ make cva6_ooc CLK_PERIOD_NS=20
```
By default, synthesis is performed in batch mode, however it is possible to run this command using Vivado GUI:
This command generates synthesis and place and route reports in **fpga/reports_cva6_ooc_synth** and **fpga/reports_cva6_ooc_impl**.
Les scripts liés à coremark sont en python2...
```
sudo rm /usr/bin/python
sudo ln -s /usr/bin/python2.7 /usr/bin/python
# FPGA platform
A FPGA platform prototyping **CV32A6** (CVA6 in 32-bit flavor) has been implemented on **Zybo Z7-20** board.
make coremark.mem
cd ../..
This platform integrates a CV32A6 processor (clocked to 25MHz), a JTAG interface to run and debug software applications and a UART interface to display strings on a hyperterminal.
sudo rm /usr/bin/python
sudo ln -s /usr/bin/python3 /usr/bin/python
Below are described steps to run Coremark application on CV32A6 FPGA platform, steps are the same for Dhrystone application and other software applications.
make cva6_fpga
```
The JTAG-HS2 programming cable is initially a cable that allows programming of Xilinx FPGAs (bitstream loading) from a host PC.
## Charger le projet dans Vivado.
Dans vivado :
In our case, we use this cable to program software applications on the CV32A6 instantiated in the FPGA through a PMOD connector.
Open project /fpga/cva6_fpga.xpr
Sous PROGRAM AND DEBUG/Open Hardware Manager
1. Open Target(AutoConnect)
1. Program Device(xc7z020_1)
## Get started with Coremark application
1. First, make sure the Digilent **JTAG-HS2 debug adapter** is properly connected to the **PMOD JE** connector and that the USBUART adapter is properly connected to the **PMOD JB** connector of the Zybo Z7-20 board.
2. Compile Coremark application in `sw/app`. Commands to compile Coremark application are described in `sw/app` directory.
3. Generate the bitstream of the FPGA platform. There are **two** FPGA platform, one using BRAM as main memory and another one using DDR conected to Zynq PS as main memory. Using the DDR allows savings of logic resources in FPGA fabric. You can choose the FPGA platform you want to implement :
Sur la carte zybo, la led verte s’allume quand le programme est chargé.
Fermer vivado.
If you want to implement the FPGA platform using BRAM, you have to run the following command:
## Configurer les communications pour exécuter les coremark sur le coeur
#### Lancer openocd
Dans un terminal :
Verifier quel ttyUSB est connecté au port uart JB de la carte
déconnecter le câble, `ls /dev/ttyUSB*`,
reconnecter le cable, `ls /dev/ttyUSB*`.
En comparant les deux résultats, on trouve le nouveau dev qui doit être utilisé (ttyUSB0 par la suite).
