Skip to content
GitLab
Explore
Sign in
Primary navigation
Search or go to…
Project
M
MINOTAuR
Manage
Activity
Members
Labels
Plan
Issues
Issue boards
Milestones
Wiki
Code
Merge requests
Repository
Branches
Commits
Tags
Repository graph
Compare revisions
Snippets
Build
Pipelines
Jobs
Pipeline schedules
Artifacts
Deploy
Releases
Package registry
Model registry
Operate
Environments
Terraform modules
Monitor
Incidents
Analyze
Value stream analytics
Contributor analytics
CI/CD analytics
Repository analytics
Model experiments
Help
Help
Support
GitLab documentation
Compare GitLab plans
Community forum
Contribute to GitLab
Provide feedback
Keyboard shortcuts
?
Snippets
Groups
Projects
Show more breadcrumbs
MINOTAuR
MINOTAuR
Commits
aba53f37
Unverified
Commit
aba53f37
authored
7 years ago
by
Florian Zaruba
Browse files
Options
Downloads
Patches
Plain Diff
Fix synthesis problems in miss handler
parent
8a326f76
Branches
Branches containing commit
No related tags found
No related merge requests found
Changes
1
Hide whitespace changes
Inline
Side-by-side
Showing
1 changed file
src/miss_handler.sv
+4
-34
4 additions, 34 deletions
src/miss_handler.sv
with
4 additions
and
34 deletions
src/miss_handler.sv
+
4
−
34
View file @
aba53f37
...
...
@@ -565,8 +565,9 @@ module arbiter #(
id_o
=
req_q
.
id
;
data_gnt_o
=
'0
;
// read port
data_rvalid_o
=
'0
;
data_rdata_o
[
req_q
.
id
]
=
data_rdata_i
;
data_rvalid_o
=
'0
;
data_rdata_o
=
'0
;
data_rdata_o
[
req_q
.
id
]
=
data_rdata_i
;
case
(
state_q
)
...
...
@@ -608,38 +609,6 @@ module arbiter #(
default
:
/* default */
;
endcase
end
// // addressing read and full write
// always_comb begin : read_req_write
// automatic logic [$clog2(NR_PORTS)-1:0] request_index;
// request_index = 0;
// data_req_o = 1'b0;
// data_gnt_o = '0;
// // pass through all signals from the correct slave port
// address_o = address_i[request_index];
// data_wdata_o = data_wdata_i[request_index];
// data_be_o = data_be_i[request_index];
// data_size_o = data_size_i[request_index];
// data_we_o = data_we_i[request_index];
// data_gnt_o[gnt_id_i] = data_gnt_i;
// id_o = request_index;
// end
// // ------------
// // Read port
// // ------------
// always_comb begin : slave_read_port
// data_rvalid_o = '0;
// data_rdata_o = '0;
// // if there is a valid signal the FIFO should not be empty anyway
// if (data_rvalid_i) begin
// data_rvalid_o[id_i] = data_rvalid_i;
// data_rdata_o [id_i] = data_rdata_i;
// end
// end
always_ff
@
(
posedge
clk_i
or
negedge
rst_ni
)
begin
if
(
~
rst_ni
)
begin
...
...
@@ -773,6 +742,7 @@ module axi_adapter #(
cache_line_d
=
cache_line_q
;
addr_offset_d
=
addr_offset_q
;
id_d
=
id_q
;
index
=
'0
;
case
(
state_q
)
...
...
This diff is collapsed.
Click to expand it.
Preview
0%
Loading
Try again
or
attach a new file
.
Cancel
You are about to add
0
people
to the discussion. Proceed with caution.
Finish editing this message first!
Save comment
Cancel
Please
register
or
sign in
to comment