verifier: hook up signal from the store buffer

Signed-off-by: Alban Gruin <alban.gruin@irit.fr>

src/ariane.sv

@@ -647,6 +647,9 @@ module ariane import ariane_pkg::*; #(
     // IS
     .is_has_mem_access_i (has_mem_access_is_verif),
 
+    // LSU
+    .no_st_pending_commit_i (no_st_pending_ex),
+
     // CO
     .commit_instr_i (commit_instr_id_commit),
     .commit_ack_i (commit_ack)

src/verifier.sv

@@ -18,6 +18,9 @@ module verifier #(
   // IS
   input logic                       is_has_mem_access_i,
 
+  // LSU
+  input logic                       no_st_pending_commit_i,
+
   // CO
   input                             ariane_pkg::scoreboard_entry_t [NR_COMMIT_PORTS-1:0] commit_instr_i,
   input logic [NR_COMMIT_PORTS-1:0] commit_ack_i,
@@ -29,7 +32,7 @@ module verifier #(
 
   // Bus accesses (I$ misses and memory instructions in the pipeline)
   logic                             has_mem_access;
-  assign has_mem_access = if_has_mem_access_i | id_has_mem_access_i | is_has_mem_access_i;
+  assign has_mem_access = if_has_mem_access_i | id_has_mem_access_i | is_has_mem_access_i | (~no_st_pending_commit_i);
   assign should_lock_icache_o = has_mem_access & icache_miss_i;
 
   // CO