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Commit fd12a3c9 authored by Alban Gruin's avatar Alban Gruin
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scoreboard: size improvements


Signed-off-by: default avatarAlban Gruin <alban.gruin@irit.fr>
parent cd7dabb4
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...@@ -86,8 +86,7 @@ module scoreboard #( ...@@ -86,8 +86,7 @@ module scoreboard #(
logic [NR_ENTRIES-1:0] flushed; logic [NR_ENTRIES-1:0] flushed;
logic [$clog2(NR_ENTRIES)-1:0] num_flush; logic [$clog2(NR_ENTRIES)-1:0] num_flush;
logic [NR_ENTRIES-1:0] has_mem_access_n, has_mem_access_q; logic [NR_ENTRIES-1:0] is_cf, has_mem_access;
logic [NR_ENTRIES-1:0] is_cf_n, is_cf_q;
// the issue queue is full don't issue any new instructions // the issue queue is full don't issue any new instructions
// works since aligned to power of 2 // works since aligned to power of 2
...@@ -104,8 +103,17 @@ module scoreboard #( ...@@ -104,8 +103,17 @@ module scoreboard #(
end end
// check instructions in the scoreboard for memory operations and ctrl flow // check instructions in the scoreboard for memory operations and ctrl flow
assign has_mem_access_o = (|has_mem_access_q); for (genvar i = 0; i < NR_ENTRIES; i++) begin
assign has_control_flow_o = (|is_cf_q); assign is_cf[i] = mem_q[i].issued && ~mem_q[i].sbe.valid &&
mem_q[i].sbe.fu == ariane_pkg::CTRL_FLOW &&
mem_q[i].sbe.op != ariane_pkg::ADD;
assign has_mem_access[i] = (mem_q[i].issued && ~mem_q[i].sbe.valid &&
mem_q[i].sbe.fu inside {ariane_pkg::LOAD, ariane_pkg::STORE}) ||
mem_q[i].sbe.valid && mem_q[i].sbe.fu == ariane_pkg::STORE;
end
assign has_control_flow_o = |is_cf;
assign has_mem_access_o = |has_mem_access;
// maintain a FIFO with issued instructions // maintain a FIFO with issued instructions
// keep track of all issued instructions // keep track of all issued instructions
...@@ -113,9 +121,6 @@ module scoreboard #( ...@@ -113,9 +121,6 @@ module scoreboard #(
// default assignment // default assignment
mem_n = mem_q; mem_n = mem_q;
issue_en = 1'b0; issue_en = 1'b0;
has_mem_access_n = has_mem_access_q;
is_cf_n = is_cf_q;
decoded_instr_ack_o = 1'b0;
flushed = '0; flushed = '0;
decoded_instr_ack_o = decoded_instr_valid_i && ~issue_full; decoded_instr_ack_o = decoded_instr_valid_i && ~issue_full;
...@@ -125,14 +130,11 @@ module scoreboard #( ...@@ -125,14 +130,11 @@ module scoreboard #(
// the decoded instruction we put in there is valid (1st bit) // the decoded instruction we put in there is valid (1st bit)
// increase the issue counter and advance issue pointer // increase the issue counter and advance issue pointer
issue_en = 1'b1; issue_en = 1'b1;
// decoded_instr_ack_o = 1'b1;
mem_n[write_pointer_q] = {1'b1, mem_n[write_pointer_q] = {1'b1,
1'b1, // valid bit 1'b1, // valid bit
ariane_pkg::is_rd_fpr(decoded_instr_i.op), // whether rd goes to the fpr ariane_pkg::is_rd_fpr(decoded_instr_i.op), // whether rd goes to the fpr
decoded_instr_i // decoded instruction record decoded_instr_i // decoded instruction record
}; };
has_mem_access_n[write_pointer_q] = decoded_instr_i.fu inside {ariane_pkg::LOAD, ariane_pkg::STORE};
is_cf_n[write_pointer_q] = decoded_instr_i.fu == ariane_pkg::CTRL_FLOW && decoded_instr_i.op != ariane_pkg::ADD;
end end
issue_instr_o = mem_n[issue_pointer_q]; issue_instr_o = mem_n[issue_pointer_q];
...@@ -149,8 +151,6 @@ module scoreboard #( ...@@ -149,8 +151,6 @@ module scoreboard #(
mem_n[i].pending = 1'b0; mem_n[i].pending = 1'b0;
mem_n[i].issued = 1'b0; mem_n[i].issued = 1'b0;
flushed[i] = 1'b1; flushed[i] = 1'b1;
has_mem_access_n[i] = 1'b0;
is_cf_n[i] = 1'b0;
end end
end end
end end
...@@ -181,11 +181,6 @@ module scoreboard #( ...@@ -181,11 +181,6 @@ module scoreboard #(
// write the fflags back from the FPU (exception valid is never set), leave tval intact // write the fflags back from the FPU (exception valid is never set), leave tval intact
else if (mem_q[trans_id_i[i]].sbe.fu inside {ariane_pkg::FPU, ariane_pkg::FPU_VEC}) else if (mem_q[trans_id_i[i]].sbe.fu inside {ariane_pkg::FPU, ariane_pkg::FPU_VEC})
mem_n[trans_id_i[i]].sbe.ex.cause = ex_i[i].cause; mem_n[trans_id_i[i]].sbe.ex.cause = ex_i[i].cause;
if (mem_q[trans_id_i[i]].sbe.fu != ariane_pkg::STORE)
has_mem_access_n[trans_id_i[i]] = 1'b0;
is_cf_n[trans_id_i[i]] = 1'b0;
end end
end end
...@@ -199,8 +194,6 @@ module scoreboard #( ...@@ -199,8 +194,6 @@ module scoreboard #(
mem_n[commit_pointer_q[i]].pending = 1'b0; mem_n[commit_pointer_q[i]].pending = 1'b0;
mem_n[commit_pointer_q[i]].issued = 1'b0; mem_n[commit_pointer_q[i]].issued = 1'b0;
mem_n[commit_pointer_q[i]].sbe.valid = 1'b0; mem_n[commit_pointer_q[i]].sbe.valid = 1'b0;
has_mem_access_n[commit_pointer_q[i]] = 1'b0;
is_cf_n[commit_pointer_q[i]] = 1'b0;
end end
end end
...@@ -214,8 +207,6 @@ module scoreboard #( ...@@ -214,8 +207,6 @@ module scoreboard #(
mem_n[i].issued = 1'b0; mem_n[i].issued = 1'b0;
mem_n[i].sbe.valid = 1'b0; mem_n[i].sbe.valid = 1'b0;
mem_n[i].sbe.ex.valid = 1'b0; mem_n[i].sbe.ex.valid = 1'b0;
has_mem_access_n[i] = 1'b0;
is_cf_n[i] = 1'b0;
end end
end end
end end
...@@ -360,16 +351,12 @@ module scoreboard #( ...@@ -360,16 +351,12 @@ module scoreboard #(
commit_pointer_q <= '0; commit_pointer_q <= '0;
issue_pointer_q <= '0; issue_pointer_q <= '0;
write_pointer_q <= '0; write_pointer_q <= '0;
has_mem_access_q <= '0;
is_cf_q <= '0;
end else begin end else begin
issue_cnt_q <= issue_cnt_n; issue_cnt_q <= issue_cnt_n;
issue_pointer_q <= issue_pointer_n; issue_pointer_q <= issue_pointer_n;
write_pointer_q <= write_pointer_n; write_pointer_q <= write_pointer_n;
mem_q <= mem_n; mem_q <= mem_n;
commit_pointer_q <= commit_pointer_n; commit_pointer_q <= commit_pointer_n;
has_mem_access_q <= has_mem_access_n;
is_cf_q <= is_cf_n;
end end
end end
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