Skip to content
Snippets Groups Projects

Repository graph

You can move around the graph by using the arrow keys.
Select Git revision
  • ariane
  • master default protected
  • minotaur
  • minotaur_beta
  • printemps
  • seqariane
  • sicariane
  • tacle-ariane
  • thales
  • minotaur-lru-sras-revision-rc
  • minotaur-revision-rc
11 results
Created with Raphaël 2.2.05Jan16Dec15141328Oct207Sep8Jul26May241119Mar1713Jan8515Dec87429Oct2827261615141312911Sep108228Aug2726252429Jul26161426Jun21191614231May181529Apr28261514114Mar1327Feb261810422Jan13Dec323Oct119827Sep1220Aug191224Jul14121023Jun433Apr30Mar26242120191818Feb1514876531Jan30292825242315129874Dec229Nov2827262523222120191817161513128765432131Oct302926251918171615141310sras: add assertionswt_icache: check the SpecDepth valuesras: improve segmented RAS ressource usagesras: reduce the size of the segmented RASsras: add assertionsMerge ag/predictable-lru in ag/sraswt_icache: lock if there is not enough backups for speculationwt_cache_subsystem: forward speculation signals to I$ariane: signal the beginning and the end of speculation to the cache subsystemwt_icache: make a backup of the LRU for each speculationwt_icache: modify the replacement policy to be a 4-way LRUfrontend: replace the RAS by a segmented RAScache_subsystem: add a 4-way LRU comparatorRevert "frontend: remove the RAS"frontend: add a signal to know if a prediction was correctfrontend: add a segmented RAS, based on the original RASfrontend: add asserts to assess the correct behaviour of the replay mechanismariane, frontend: add a signal to inform components that speculation is happeningwt_icache: don't fallback to the TLB_MISS state when stalled in READwt_icache: don't lock requests in the IDLE stateUpdate READMEmastermasterCompare CSRs before and after the benchmark, compile with -O2kernel, sequential: patch sourcesReplace dtor by a coccinelle patch, use -Os instead of -O3, lighter destructorAdd a destructor to dump some CSRs at the end of a benchAdd a Makefile to build tacle-bench for the CVA6 processorbin2mem: set the output file to the 2nd argumentMerge branch 'cva6-bsp' into ag/cva6Added READMEIRO: always allow an ALU instruction to be executedex_stage: add an arbitrer to the FLU busscoreboard: accept instructions even if they will not be issued next cycleariane_pkg: reduce queues sizeseqarianeseqarianeariane_pkg: reduce queue sizes to 1sicarianesicarianefrontend: remove the BTB and the BHTfrontend: remove the RASminotaurminotaurariane: lock I$ requests if there is a CF in the pipelineminotaur_betaminotaur_betafrontend: fix CF accountingissue_stage: add a signal to indicate whether or not there is a CFid_stage: add a signal to indicate whether or not there is a CF
Loading