* Fix latch and timing loop in debu_req

* Fix unconnected IPI signals in CLINT, and unconnected regs in CSR_REGFILE

* Fix several issues with AXI IDs in axi_adapter, add AXI ID width parameter, and assertions testing for invalid read/write data

* Eliminate sim, simc make targets for Questa. Tests can be directly invoked via typing name and optionally specifying the gui-mode.

* Initialize instruction traced shadow regfile to zero at start of simulation

Fix progbuf offsets and tie unsupported counters to zero to avoid propagation of X

Fix printouts of assertions

Modify bootrom to prevent assignment of X to output

* Make separate CI target for AMO tests

* Bump fpga-support version

* Add AMO tests list

* Fix FPU submodule version

* Change core_id + cluster_id into hart_id

* Rename gitlab CI tests

* Replace all SYNTHESIS macros with pragma translate_off

* Update readme, bump common cells, benderize

* Fix torture make target

* Remove unneeded signal